From 63e8f7ff8a698be6af390521017a3b6528b16cb9 Mon Sep 17 00:00:00 2001
From: Zhang Yubing <yubing.zhang@rock-chips.com>
Date: Sun, 21 Nov 2021 12:47:46 +0800
Subject: [PATCH] arm64: dts: rockchip: rk3588-evb3-lp5: change dp clk source

use v0pll as dp interface dclk source default.

Signed-off-by: Zhang Yubing <yubing.zhang@rock-chips.com>
Change-Id: I893bf3dc83632c500b8fafa664cf2e8177d809fc
---
 arch/arm64/boot/dts/rockchip/rk3588-evb3-lp5.dtsi | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/arch/arm64/boot/dts/rockchip/rk3588-evb3-lp5.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-evb3-lp5.dtsi
index 75678f8cfd97..5827d0072a7d 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588-evb3-lp5.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588-evb3-lp5.dtsi
@@ -1172,3 +1172,12 @@
 &usbhost_dwc3_0 {
 	status = "disabled";
 };
+
+&vop {
+	assigned-clocks = <&cru DCLK_VOP0_SRC>,
+			  <&cru DCLK_VOP1_SRC>,
+			  <&cru DCLK_VOP2_SRC>,
+			  <&cru DCLK_VOP3>;
+	assigned-clock-parents = <0>, <0>, <&cru PLL_V0PLL>, <0>;
+	status = "okay";
+};