From 63fa6ce137caac671dc88266e6caca67156f58a7 Mon Sep 17 00:00:00 2001 From: Liang Chen Date: Mon, 8 Jan 2018 18:01:25 +0800 Subject: [PATCH] arm64: dts: rockchip: auto select opp-table by leakage for rk3328 Change-Id: I5807d47085291efcd8eea61e59e931615b283ba5 Signed-off-by: Liang Chen --- arch/arm64/boot/dts/rockchip/rk3328.dtsi | 124 +++++++++++++++++++---- 1 file changed, 106 insertions(+), 18 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi index d1956d997d10..673acf724df6 100644 --- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi @@ -94,35 +94,54 @@ compatible = "operating-points-v2"; opp-shared; + rockchip,leakage-voltage-sel = < + 1 8 0 + 9 254 1 + >; + nvmem-cells = <&cpu_leakage>; + nvmem-cell-names = "cpu_leakage"; + opp-408000000 { opp-hz = /bits/ 64 <408000000>; - opp-microvolt = <950000>; + opp-microvolt = <975000>; + opp-microvolt-L0 = <975000>; + opp-microvolt-L1 = <950000>; clock-latency-ns = <40000>; opp-suspend; }; opp-600000000 { opp-hz = /bits/ 64 <600000000>; - opp-microvolt = <950000>; + opp-microvolt = <975000>; + opp-microvolt-L0 = <975000>; + opp-microvolt-L1 = <950000>; clock-latency-ns = <40000>; }; opp-816000000 { opp-hz = /bits/ 64 <816000000>; - opp-microvolt = <1000000>; + opp-microvolt = <1025000>; + opp-microvolt-L0 = <1025000>; + opp-microvolt-L1 = <1000000>; clock-latency-ns = <40000>; }; opp-1008000000 { opp-hz = /bits/ 64 <1008000000>; - opp-microvolt = <1100000>; + opp-microvolt = <1125000>; + opp-microvolt-L0 = <1125000>; + opp-microvolt-L1 = <1100000>; clock-latency-ns = <40000>; }; opp-1200000000 { opp-hz = /bits/ 64 <1200000000>; - opp-microvolt = <1225000>; + opp-microvolt = <1250000>; + opp-microvolt-L0 = <1250000>; + opp-microvolt-L1 = <1225000>; clock-latency-ns = <40000>; }; opp-1296000000 { opp-hz = /bits/ 64 <1296000000>; - opp-microvolt = <1300000>; + opp-microvolt = <1325000>; + opp-microvolt-L0 = <1325000>; + opp-microvolt-L1 = <1300000>; clock-latency-ns = <40000>; }; }; @@ -586,9 +605,46 @@ clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>; clock-names = "bus", "core"; #cooling-cells = <2>; /* min followed by max */ + operating-points-v2 = <&gpu_opp_table>; resets = <&cru SRST_GPU_A>; }; + gpu_opp_table: gpu-opp-table { + compatible = "operating-points-v2"; + + rockchip,leakage-voltage-sel = < + 1 8 0 + 9 254 1 + >; + nvmem-cells = <&logic_leakage>; + nvmem-cell-names = "gpu_leakage"; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + opp-microvolt = <925000>; + opp-microvolt-L0 = <925000>; + opp-microvolt-L1 = <900000>; + }; + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + opp-microvolt = <975000>; + opp-microvolt-L0 = <975000>; + opp-microvolt-L1 = <950000>; + }; + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + opp-microvolt = <1050000>; + opp-microvolt-L0 = <1050000>; + opp-microvolt-L1 = <1025000>; + }; + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <1125000>; + opp-microvolt-L0 = <1125000>; + opp-microvolt-L1 = <1100000>; + }; + }; + h265e: h265e@ff330000 { compatible = "rockchip,h265e"; rockchip,grf = <&grf>; @@ -744,17 +800,30 @@ rkvdec_opp_table: rkvdec-opp-table { compatible = "operating-points-v2"; + rockchip,leakage-voltage-sel = < + 1 8 0 + 9 254 1 + >; + nvmem-cells = <&logic_leakage>; + nvmem-cell-names = "rkvdec_leakage"; + opp-100000000 { opp-hz = /bits/ 64 <100000000>; - opp-microvolt = <950000>; + opp-microvolt = <975000>; + opp-microvolt-L0 = <975000>; + opp-microvolt-L1 = <950000>; }; opp-200000000 { opp-hz = /bits/ 64 <200000000>; - opp-microvolt = <950000>; + opp-microvolt = <975000>; + opp-microvolt-L0 = <975000>; + opp-microvolt-L1 = <950000>; }; opp-500000000 { opp-hz = /bits/ 64 <500000000>; - opp-microvolt = <1050000>; + opp-microvolt = <1075000>; + opp-microvolt-L0 = <1075000>; + opp-microvolt-L1 = <1050000>; }; }; @@ -1266,35 +1335,54 @@ dmc_opp_table: dmc-opp-table { compatible = "operating-points-v2"; + rockchip,leakage-voltage-sel = < + 1 8 0 + 9 254 1 + >; + nvmem-cells = <&logic_leakage>; + nvmem-cell-names = "ddr_leakage"; + opp-400000000 { opp-hz = /bits/ 64 <400000000>; - opp-microvolt = <900000>; - status = "disabled"; + opp-microvolt = <925000>; + opp-microvolt-L0 = <925000>; + opp-microvolt-L1 = <900000>; }; opp-600000000 { opp-hz = /bits/ 64 <600000000>; - opp-microvolt = <1000000>; - status = "disabled"; + opp-microvolt = <1025000>; + opp-microvolt-L0 = <1025000>; + opp-microvolt-L1 = <1000000>; }; opp-786000000 { opp-hz = /bits/ 64 <786000000>; - opp-microvolt = <1050000>; + opp-microvolt = <1075000>; + opp-microvolt-L0 = <1075000>; + opp-microvolt-L1 = <1050000>; }; opp-800000000 { opp-hz = /bits/ 64 <800000000>; - opp-microvolt = <1050000>; + opp-microvolt = <1075000>; + opp-microvolt-L0 = <1075000>; + opp-microvolt-L1 = <1050000>; }; opp-850000000 { opp-hz = /bits/ 64 <850000000>; - opp-microvolt = <1050000>; + opp-microvolt = <1075000>; + opp-microvolt-L0 = <1075000>; + opp-microvolt-L1 = <1050000>; }; opp-933000000 { opp-hz = /bits/ 64 <933000000>; - opp-microvolt = <1075000>; + opp-microvolt = <1100000>; + opp-microvolt-L0 = <1100000>; + opp-microvolt-L1 = <1075000>; }; opp-1066000000 { opp-hz = /bits/ 64 <1066000000>; - opp-microvolt = <1150000>; + opp-microvolt = <1175000>; + opp-microvolt-L0 = <1175000>; + opp-microvolt-L1 = <1150000>; }; };