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MALI: rockchip: upgrade bifrost DDK to g11p0-01eac0, from g10p0-01eac0

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Change-Id: I0642ec37f151711b8b19c3206488d3301422971d
Signed-off-by: Zhen Chen <chenzhen@rock-chips.com>
This commit is contained in:
Zhen Chen
2022-02-16 17:26:04 +08:00
committed by Tao Huang
parent 451a9752b5
commit 643f7908a0
201 changed files with 10229 additions and 6812 deletions
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35
include/uapi/gpu/arm/bifrost/csf/mali_base_csf_kernel.h
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@@ -1,7 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
/*
*
* (C) COPYRIGHT 2020-2021 ARM Limited. All rights reserved.
* (C) COPYRIGHT 2020-2022 ARM Limited. All rights reserved.
*
* This program is free software and is provided to you under the terms of the
* GNU General Public License version 2 as published by the Free Software
@@ -68,7 +68,8 @@
*/
#define BASEP_MEM_NO_USER_FREE ((base_mem_alloc_flags)1 << 7)
#define BASE_MEM_RESERVED_BIT_8 ((base_mem_alloc_flags)1 << 8)
/* Must be FIXED memory. */
#define BASE_MEM_FIXED ((base_mem_alloc_flags)1 << 8)
/* Grow backing store on GPU Page Fault
*/
@@ -160,11 +161,16 @@
/* Kernel side cache sync ops required */
#define BASE_MEM_KERNEL_SYNC ((base_mem_alloc_flags)1 << 28)
/* Must be FIXABLE memory: its GPU VA will be determined at a later point,
* at which time it will be at a fixed GPU VA.
*/
#define BASE_MEM_FIXABLE ((base_mem_alloc_flags)1 << 29)
/* Number of bits used as flags for base memory management
*
* Must be kept in sync with the base_mem_alloc_flags flags
*/
#define BASE_MEM_FLAGS_NR_BITS 29
#define BASE_MEM_FLAGS_NR_BITS 30
/* A mask of all the flags which are only valid for allocations within kbase,
* and may not be passed from user space.
@@ -183,8 +189,7 @@
/* A mask of all currently reserved flags
*/
#define BASE_MEM_FLAGS_RESERVED \
BASE_MEM_RESERVED_BIT_8 | BASE_MEM_RESERVED_BIT_20
#define BASE_MEM_FLAGS_RESERVED BASE_MEM_RESERVED_BIT_20
#define BASEP_MEM_INVALID_HANDLE (0ul)
#define BASE_MEM_MMU_DUMP_HANDLE (1ul << LOCAL_PAGE_SHIFT)
@@ -540,15 +545,17 @@ struct base_kcpu_command_group_suspend_info {
* @padding: padding to a multiple of 64 bits
* @info: structure which contains information about the kcpu command;
* actual type is determined by @p type
* @info.fence: Fence
* @info.cqs_wait: CQS wait
* @info.cqs_set: CQS set
* @info.import: import
* @info.jit_alloc: jit allocation
* @info.jit_free: jit deallocation
* @info.suspend_buf_copy: suspend buffer copy
* @info.sample_time: sample time
* @info.padding: padding
* @info.fence: Fence
* @info.cqs_wait: CQS wait
* @info.cqs_set: CQS set
* @info.cqs_wait_operation: CQS wait operation
* @info.cqs_set_operation: CQS set operation
* @info.import: import
* @info.jit_alloc: JIT allocation
* @info.jit_free: JIT deallocation
* @info.suspend_buf_copy: suspend buffer copy
* @info.sample_time: sample time
* @info.padding: padding
*/
struct base_kcpu_command {
__u8 type;

1521
include/uapi/gpu/arm/bifrost/csf/mali_gpu_csf_registers.h
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File diff suppressed because it is too large Load Diff

51
include/uapi/gpu/arm/bifrost/csf/mali_kbase_csf_ioctl.h
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@@ -1,7 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
/*
*
* (C) COPYRIGHT 2020-2021 ARM Limited. All rights reserved.
* (C) COPYRIGHT 2020-2022 ARM Limited. All rights reserved.
*
* This program is free software and is provided to you under the terms of the
* GNU General Public License version 2 as published by the Free Software
@@ -50,10 +50,16 @@
* - Added reserved field to QUEUE_GROUP_CREATE ioctl for future use
* 1.8:
* - Removed Kernel legacy HWC interface
* 1.9:
* - Reorganization of GPU-VA memory zones, including addition of
* FIXED_VA zone and auto-initialization of EXEC_VA zone.
* - Added new Base memory allocation interface
* 1.10:
* - First release of new HW performance counters interface.
*/
#define BASE_UK_VERSION_MAJOR 1
#define BASE_UK_VERSION_MINOR 8
#define BASE_UK_VERSION_MINOR 10
/**
* struct kbase_ioctl_version_check - Check version compatibility between
@@ -70,7 +76,6 @@ struct kbase_ioctl_version_check {
#define KBASE_IOCTL_VERSION_CHECK_RESERVED \
_IOWR(KBASE_IOCTL_TYPE, 0, struct kbase_ioctl_version_check)
/**
* struct kbase_ioctl_cs_queue_register - Register a GPU command queue with the
* base back-end
@@ -80,7 +85,7 @@ struct kbase_ioctl_version_check {
* @priority: Priority of the queue within a group when run within a process
* @padding: Currently unused, must be zero
*
* @Note: There is an identical sub-section in kbase_ioctl_cs_queue_register_ex.
* Note: There is an identical sub-section in kbase_ioctl_cs_queue_register_ex.
* Any change of this struct should also be mirrored to the latter.
*/
struct kbase_ioctl_cs_queue_register {
@@ -149,7 +154,7 @@ union kbase_ioctl_cs_queue_bind {
* @ex_event_state: Trace event states configuration
* @ex_padding: Currently unused, must be zero
*
* @Note: There is an identical sub-section at the start of this struct to that
* Note: There is an identical sub-section at the start of this struct to that
* of @ref kbase_ioctl_cs_queue_register. Any change of this sub-section
* must also be mirrored to the latter. Following the said sub-section,
* the remaining fields forms the extension, marked with ex_*.
@@ -257,6 +262,9 @@ union kbase_ioctl_cs_queue_group_create {
__u8 fragment_max;
__u8 compute_max;
__u8 padding[3];
/**
* @reserved: Reserved
*/
__u64 reserved;
} in;
struct {
@@ -390,7 +398,7 @@ struct kbase_ioctl_cs_tiler_heap_term {
* @in: Input parameters
* @in.max_group_num: The maximum number of groups to be read. Can be 0, in
* which case groups_ptr is unused.
* @in.max_total_stream _num: The maximum number of CSs to be read. Can be 0, in
* @in.max_total_stream_num: The maximum number of CSs to be read. Can be 0, in
* which case streams_ptr is unused.
* @in.groups_ptr: Pointer where to store all the group data (sequentially).
* @in.streams_ptr: Pointer where to store all the CS data (sequentially).
@@ -440,6 +448,37 @@ struct kbase_ioctl_cs_cpu_queue_info {
#define KBASE_IOCTL_CS_CPU_QUEUE_DUMP \
_IOW(KBASE_IOCTL_TYPE, 53, struct kbase_ioctl_cs_cpu_queue_info)
/**
* union kbase_ioctl_mem_alloc_ex - Allocate memory on the GPU
* @in: Input parameters
* @in.va_pages: The number of pages of virtual address space to reserve
* @in.commit_pages: The number of physical pages to allocate
* @in.extension: The number of extra pages to allocate on each GPU fault which grows the region
* @in.flags: Flags
* @in.fixed_address: The GPU virtual address requested for the allocation,
* if the allocation is using the BASE_MEM_FIXED flag.
* @in.extra: Space for extra parameters that may be added in the future.
* @out: Output parameters
* @out.flags: Flags
* @out.gpu_va: The GPU virtual address which is allocated
*/
union kbase_ioctl_mem_alloc_ex {
struct {
__u64 va_pages;
__u64 commit_pages;
__u64 extension;
__u64 flags;
__u64 fixed_address;
__u64 extra[3];
} in;
struct {
__u64 flags;
__u64 gpu_va;
} out;
};
#define KBASE_IOCTL_MEM_ALLOC_EX _IOWR(KBASE_IOCTL_TYPE, 59, union kbase_ioctl_mem_alloc_ex)
/***************
* test ioctls *
***************/

368
include/uapi/gpu/arm/bifrost/gpu/backend/mali_kbase_gpu_regmap_csf.h
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@@ -1,368 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
/*
*
* (C) COPYRIGHT 2019-2021 ARM Limited. All rights reserved.
*
* This program is free software and is provided to you under the terms of the
* GNU General Public License version 2 as published by the Free Software
* Foundation, and any use by you of this program is subject to the terms
* of such GNU license.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, you can access it online at
* http://www.gnu.org/licenses/gpl-2.0.html.
*
*/
#ifndef _UAPI_KBASE_GPU_REGMAP_CSF_H_
#define _UAPI_KBASE_GPU_REGMAP_CSF_H_
#include <linux/types.h>
#if !MALI_USE_CSF && defined(__KERNEL__)
#error "Cannot be compiled with JM"
#endif
/* GPU_CONTROL_MCU base address */
#define GPU_CONTROL_MCU_BASE 0x3000
/* MCU_SUBSYSTEM base address */
#define MCU_SUBSYSTEM_BASE 0x20000
/* IPA control registers */
#define IPA_CONTROL_BASE 0x40000
#define IPA_CONTROL_REG(r) (IPA_CONTROL_BASE+(r))
#define COMMAND 0x000 /* (WO) Command register */
#define STATUS 0x004 /* (RO) Status register */
#define TIMER 0x008 /* (RW) Timer control register */
#define SELECT_CSHW_LO 0x010 /* (RW) Counter select for CS hardware, low word */
#define SELECT_CSHW_HI 0x014 /* (RW) Counter select for CS hardware, high word */
#define SELECT_MEMSYS_LO 0x018 /* (RW) Counter select for Memory system, low word */
#define SELECT_MEMSYS_HI 0x01C /* (RW) Counter select for Memory system, high word */
#define SELECT_TILER_LO 0x020 /* (RW) Counter select for Tiler cores, low word */
#define SELECT_TILER_HI 0x024 /* (RW) Counter select for Tiler cores, high word */
#define SELECT_SHADER_LO 0x028 /* (RW) Counter select for Shader cores, low word */
#define SELECT_SHADER_HI 0x02C /* (RW) Counter select for Shader cores, high word */
/* Accumulated counter values for CS hardware */
#define VALUE_CSHW_BASE 0x100
#define VALUE_CSHW_REG_LO(n) (VALUE_CSHW_BASE + ((n) << 3)) /* (RO) Counter value #n, low word */
#define VALUE_CSHW_REG_HI(n) (VALUE_CSHW_BASE + ((n) << 3) + 4) /* (RO) Counter value #n, high word */
/* Accumulated counter values for memory system */
#define VALUE_MEMSYS_BASE 0x140
#define VALUE_MEMSYS_REG_LO(n) (VALUE_MEMSYS_BASE + ((n) << 3)) /* (RO) Counter value #n, low word */
#define VALUE_MEMSYS_REG_HI(n) (VALUE_MEMSYS_BASE + ((n) << 3) + 4) /* (RO) Counter value #n, high word */
#define VALUE_TILER_BASE 0x180
#define VALUE_TILER_REG_LO(n) (VALUE_TILER_BASE + ((n) << 3)) /* (RO) Counter value #n, low word */
#define VALUE_TILER_REG_HI(n) (VALUE_TILER_BASE + ((n) << 3) + 4) /* (RO) Counter value #n, high word */
#define VALUE_SHADER_BASE 0x1C0
#define VALUE_SHADER_REG_LO(n) (VALUE_SHADER_BASE + ((n) << 3)) /* (RO) Counter value #n, low word */
#define VALUE_SHADER_REG_HI(n) (VALUE_SHADER_BASE + ((n) << 3) + 4) /* (RO) Counter value #n, high word */
/* Set to implementation defined, outer caching */
#define AS_MEMATTR_AARCH64_OUTER_IMPL_DEF 0x88ull
/* Set to write back memory, outer caching */
#define AS_MEMATTR_AARCH64_OUTER_WA 0x8Dull
/* Set to inner non-cacheable, outer-non-cacheable
* Setting defined by the alloc bits is ignored, but set to a valid encoding:
* - no-alloc on read
* - no alloc on write
*/
#define AS_MEMATTR_AARCH64_NON_CACHEABLE 0x4Cull
/* Set to shared memory, that is inner cacheable on ACE and inner or outer
* shared, otherwise inner non-cacheable.
* Outer cacheable if inner or outer shared, otherwise outer non-cacheable.
*/
#define AS_MEMATTR_AARCH64_SHARED 0x8ull
/* Symbols for default MEMATTR to use
* Default is - HW implementation defined caching
*/
#define AS_MEMATTR_INDEX_DEFAULT 0
#define AS_MEMATTR_INDEX_DEFAULT_ACE 3
/* HW implementation defined caching */
#define AS_MEMATTR_INDEX_IMPL_DEF_CACHE_POLICY 0
/* Force cache on */
#define AS_MEMATTR_INDEX_FORCE_TO_CACHE_ALL 1
/* Write-alloc */
#define AS_MEMATTR_INDEX_WRITE_ALLOC 2
/* Outer coherent, inner implementation defined policy */
#define AS_MEMATTR_INDEX_OUTER_IMPL_DEF 3
/* Outer coherent, write alloc inner */
#define AS_MEMATTR_INDEX_OUTER_WA 4
/* Normal memory, inner non-cacheable, outer non-cacheable (ARMv8 mode only) */
#define AS_MEMATTR_INDEX_NON_CACHEABLE 5
/* Normal memory, shared between MCU and Host */
#define AS_MEMATTR_INDEX_SHARED 6
/* Configuration bits for the CSF. */
#define CSF_CONFIG 0xF00
/* CSF_CONFIG register */
#define CSF_CONFIG_FORCE_COHERENCY_FEATURES_SHIFT 2
/* GPU control registers */
#define CORE_FEATURES 0x008 /* () Shader Core Features */
#define MCU_CONTROL 0x700
#define MCU_STATUS 0x704
#define MCU_CNTRL_ENABLE (1 << 0)
#define MCU_CNTRL_AUTO (1 << 1)
#define MCU_CNTRL_DISABLE (0)
#define MCU_CNTRL_DOORBELL_DISABLE_SHIFT (31)
#define MCU_CNTRL_DOORBELL_DISABLE_MASK (1 << MCU_CNTRL_DOORBELL_DISABLE_SHIFT)
#define MCU_STATUS_HALTED (1 << 1)
#define PRFCNT_BASE_LO 0x060 /* (RW) Performance counter memory
* region base address, low word
*/
#define PRFCNT_BASE_HI 0x064 /* (RW) Performance counter memory
* region base address, high word
*/
#define PRFCNT_CONFIG 0x068 /* (RW) Performance counter
* configuration
*/
#define PRFCNT_CSHW_EN 0x06C /* (RW) Performance counter
* enable for CS Hardware
*/
#define PRFCNT_SHADER_EN 0x070 /* (RW) Performance counter enable
* flags for shader cores
*/
#define PRFCNT_TILER_EN 0x074 /* (RW) Performance counter enable
* flags for tiler
*/
#define PRFCNT_MMU_L2_EN 0x07C /* (RW) Performance counter enable
* flags for MMU/L2 cache
*/
/* JOB IRQ flags */
#define JOB_IRQ_GLOBAL_IF (1 << 31) /* Global interface interrupt received */
/* GPU_COMMAND codes */
#define GPU_COMMAND_CODE_NOP 0x00 /* No operation, nothing happens */
#define GPU_COMMAND_CODE_RESET 0x01 /* Reset the GPU */
#define GPU_COMMAND_CODE_PRFCNT 0x02 /* Clear or sample performance counters */
#define GPU_COMMAND_CODE_TIME 0x03 /* Configure time sources */
#define GPU_COMMAND_CODE_FLUSH_CACHES 0x04 /* Flush caches */
#define GPU_COMMAND_CODE_SET_PROTECTED_MODE 0x05 /* Places the GPU in protected mode */
#define GPU_COMMAND_CODE_FINISH_HALT 0x06 /* Halt CSF */
#define GPU_COMMAND_CODE_CLEAR_FAULT 0x07 /* Clear GPU_FAULTSTATUS and GPU_FAULTADDRESS, TODX */
/* GPU_COMMAND_RESET payloads */
/* This will leave the state of active jobs UNDEFINED, but will leave the external bus in a defined and idle state.
* Power domains will remain powered on.
*/
#define GPU_COMMAND_RESET_PAYLOAD_FAST_RESET 0x00
/* This will leave the state of active CSs UNDEFINED, but will leave the external bus in a defined and
* idle state.
*/
#define GPU_COMMAND_RESET_PAYLOAD_SOFT_RESET 0x01
/* This reset will leave the state of currently active streams UNDEFINED, will likely lose data, and may leave
* the system bus in an inconsistent state. Use only as a last resort when nothing else works.
*/
#define GPU_COMMAND_RESET_PAYLOAD_HARD_RESET 0x02
/* GPU_COMMAND_PRFCNT payloads */
#define GPU_COMMAND_PRFCNT_PAYLOAD_SAMPLE 0x01 /* Sample performance counters */
#define GPU_COMMAND_PRFCNT_PAYLOAD_CLEAR 0x02 /* Clear performance counters */
/* GPU_COMMAND_TIME payloads */
#define GPU_COMMAND_TIME_DISABLE 0x00 /* Disable cycle counter */
#define GPU_COMMAND_TIME_ENABLE 0x01 /* Enable cycle counter */
/* GPU_COMMAND_FLUSH_CACHES payloads bits for L2 caches */
#define GPU_COMMAND_FLUSH_PAYLOAD_L2_NONE 0x000 /* No flush */
#define GPU_COMMAND_FLUSH_PAYLOAD_L2_CLEAN 0x001 /* CLN only */
#define GPU_COMMAND_FLUSH_PAYLOAD_L2_CLEAN_INVALIDATE 0x003 /* CLN + INV */
/* GPU_COMMAND_FLUSH_CACHES payloads bits for Load-store caches */
#define GPU_COMMAND_FLUSH_PAYLOAD_LSC_NONE 0x000 /* No flush */
#define GPU_COMMAND_FLUSH_PAYLOAD_LSC_CLEAN 0x010 /* CLN only */
#define GPU_COMMAND_FLUSH_PAYLOAD_LSC_CLEAN_INVALIDATE 0x030 /* CLN + INV */
/* GPU_COMMAND_FLUSH_CACHES payloads bits for Other caches */
#define GPU_COMMAND_FLUSH_PAYLOAD_OTHER_NONE 0x000 /* No flush */
#define GPU_COMMAND_FLUSH_PAYLOAD_OTHER_INVALIDATE 0x200 /* INV only */
/* GPU_COMMAND command + payload */
#define GPU_COMMAND_CODE_PAYLOAD(opcode, payload) \
((__u32)opcode | ((__u32)payload << 8))
/* Final GPU_COMMAND form */
/* No operation, nothing happens */
#define GPU_COMMAND_NOP \
GPU_COMMAND_CODE_PAYLOAD(GPU_COMMAND_CODE_NOP, 0)
/* Stop all external bus interfaces, and then reset the entire GPU. */
#define GPU_COMMAND_SOFT_RESET \
GPU_COMMAND_CODE_PAYLOAD(GPU_COMMAND_CODE_RESET, GPU_COMMAND_RESET_PAYLOAD_SOFT_RESET)
/* Immediately reset the entire GPU. */
#define GPU_COMMAND_HARD_RESET \
GPU_COMMAND_CODE_PAYLOAD(GPU_COMMAND_CODE_RESET, GPU_COMMAND_RESET_PAYLOAD_HARD_RESET)
/* Clear all performance counters, setting them all to zero. */
#define GPU_COMMAND_PRFCNT_CLEAR \
GPU_COMMAND_CODE_PAYLOAD(GPU_COMMAND_CODE_PRFCNT, GPU_COMMAND_PRFCNT_PAYLOAD_CLEAR)
/* Sample all performance counters, writing them out to memory */
#define GPU_COMMAND_PRFCNT_SAMPLE \
GPU_COMMAND_CODE_PAYLOAD(GPU_COMMAND_CODE_PRFCNT, GPU_COMMAND_PRFCNT_PAYLOAD_SAMPLE)
/* Starts the cycle counter, and system timestamp propagation */
#define GPU_COMMAND_CYCLE_COUNT_START \
GPU_COMMAND_CODE_PAYLOAD(GPU_COMMAND_CODE_TIME, GPU_COMMAND_TIME_ENABLE)
/* Stops the cycle counter, and system timestamp propagation */
#define GPU_COMMAND_CYCLE_COUNT_STOP \
GPU_COMMAND_CODE_PAYLOAD(GPU_COMMAND_CODE_TIME, GPU_COMMAND_TIME_DISABLE)
/* Clean and invalidate L2 cache (Equivalent to FLUSH_PT) */
#define GPU_COMMAND_CACHE_CLN_INV_L2 \
GPU_COMMAND_CODE_PAYLOAD( \
GPU_COMMAND_CODE_FLUSH_CACHES, \
(GPU_COMMAND_FLUSH_PAYLOAD_L2_CLEAN_INVALIDATE | \
GPU_COMMAND_FLUSH_PAYLOAD_LSC_NONE | \
GPU_COMMAND_FLUSH_PAYLOAD_OTHER_NONE))
/* Clean and invalidate L2 and LSC caches (Equivalent to FLUSH_MEM) */
#define GPU_COMMAND_CACHE_CLN_INV_L2_LSC \
GPU_COMMAND_CODE_PAYLOAD( \
GPU_COMMAND_CODE_FLUSH_CACHES, \
(GPU_COMMAND_FLUSH_PAYLOAD_L2_CLEAN_INVALIDATE | \
GPU_COMMAND_FLUSH_PAYLOAD_LSC_CLEAN_INVALIDATE | \
GPU_COMMAND_FLUSH_PAYLOAD_OTHER_NONE))
/* Clean and invalidate L2, LSC, and Other caches */
#define GPU_COMMAND_CACHE_CLN_INV_FULL \
GPU_COMMAND_CODE_PAYLOAD( \
GPU_COMMAND_CODE_FLUSH_CACHES, \
(GPU_COMMAND_FLUSH_PAYLOAD_L2_CLEAN_INVALIDATE | \
GPU_COMMAND_FLUSH_PAYLOAD_LSC_CLEAN_INVALIDATE | \
GPU_COMMAND_FLUSH_PAYLOAD_OTHER_INVALIDATE))
/* Merge cache flush commands */
#define GPU_COMMAND_FLUSH_CACHE_MERGE(cmd1, cmd2) ((cmd1) | (cmd2))
/* Places the GPU in protected mode */
#define GPU_COMMAND_SET_PROTECTED_MODE \
GPU_COMMAND_CODE_PAYLOAD(GPU_COMMAND_CODE_SET_PROTECTED_MODE, 0)
/* Halt CSF */
#define GPU_COMMAND_FINISH_HALT \
GPU_COMMAND_CODE_PAYLOAD(GPU_COMMAND_CODE_FINISH_HALT, 0)
/* Clear GPU faults */
#define GPU_COMMAND_CLEAR_FAULT \
GPU_COMMAND_CODE_PAYLOAD(GPU_COMMAND_CODE_CLEAR_FAULT, 0)
/* End Command Values */
/* GPU_FAULTSTATUS register */
#define GPU_FAULTSTATUS_EXCEPTION_TYPE_SHIFT 0
#define GPU_FAULTSTATUS_EXCEPTION_TYPE_MASK (0xFFul)
#define GPU_FAULTSTATUS_EXCEPTION_TYPE_GET(reg_val) \
(((reg_val)&GPU_FAULTSTATUS_EXCEPTION_TYPE_MASK) \
>> GPU_FAULTSTATUS_EXCEPTION_TYPE_SHIFT)
#define GPU_FAULTSTATUS_ACCESS_TYPE_SHIFT 8
#define GPU_FAULTSTATUS_ACCESS_TYPE_MASK \
(0x3ul << GPU_FAULTSTATUS_ACCESS_TYPE_SHIFT)
#define GPU_FAULTSTATUS_ADDR_VALID_SHIFT 10
#define GPU_FAULTSTATUS_ADDR_VALID_FLAG \
(1ul << GPU_FAULTSTATUS_ADDR_VALID_SHIFT)
#define GPU_FAULTSTATUS_JASID_VALID_SHIFT 11
#define GPU_FAULTSTATUS_JASID_VALID_FLAG \
(1ul << GPU_FAULTSTATUS_JASID_VALID_SHIFT)
#define GPU_FAULTSTATUS_JASID_SHIFT 12
#define GPU_FAULTSTATUS_JASID_MASK (0xF << GPU_FAULTSTATUS_JASID_SHIFT)
#define GPU_FAULTSTATUS_JASID_GET(reg_val) \
(((reg_val)&GPU_FAULTSTATUS_JASID_MASK) >> GPU_FAULTSTATUS_JASID_SHIFT)
#define GPU_FAULTSTATUS_JASID_SET(reg_val, value) \
(((reg_val) & ~GPU_FAULTSTATUS_JASID_MASK) | \
(((value) << GPU_FAULTSTATUS_JASID_SHIFT) & GPU_FAULTSTATUS_JASID_MASK))
#define GPU_FAULTSTATUS_SOURCE_ID_SHIFT 16
#define GPU_FAULTSTATUS_SOURCE_ID_MASK \
(0xFFFFul << GPU_FAULTSTATUS_SOURCE_ID_SHIFT)
/* End GPU_FAULTSTATUS register */
/* GPU_FAULTSTATUS_ACCESS_TYPE values */
#define GPU_FAULTSTATUS_ACCESS_TYPE_ATOMIC 0x0
#define GPU_FAULTSTATUS_ACCESS_TYPE_EXECUTE 0x1
#define GPU_FAULTSTATUS_ACCESS_TYPE_READ 0x2
#define GPU_FAULTSTATUS_ACCESS_TYPE_WRITE 0x3
/* End of GPU_FAULTSTATUS_ACCESS_TYPE values */
/* Implementation-dependent exception codes used to indicate CSG
* and CS errors that are not specified in the specs.
*/
#define GPU_EXCEPTION_TYPE_SW_FAULT_0 ((__u8)0x70)
#define GPU_EXCEPTION_TYPE_SW_FAULT_1 ((__u8)0x71)
#define GPU_EXCEPTION_TYPE_SW_FAULT_2 ((__u8)0x72)
/* GPU_FAULTSTATUS_EXCEPTION_TYPE values */
#define GPU_FAULTSTATUS_EXCEPTION_TYPE_OK 0x00
#define GPU_FAULTSTATUS_EXCEPTION_TYPE_GPU_BUS_FAULT 0x80
#define GPU_FAULTSTATUS_EXCEPTION_TYPE_GPU_SHAREABILITY_FAULT 0x88
#define GPU_FAULTSTATUS_EXCEPTION_TYPE_SYSTEM_SHAREABILITY_FAULT 0x89
#define GPU_FAULTSTATUS_EXCEPTION_TYPE_GPU_CACHEABILITY_FAULT 0x8A
/* End of GPU_FAULTSTATUS_EXCEPTION_TYPE values */
#define GPU_FAULTSTATUS_ADDRESS_VALID_SHIFT GPU_U(10)
#define GPU_FAULTSTATUS_ADDRESS_VALID_MASK (GPU_U(0x1) << GPU_FAULTSTATUS_ADDRESS_VALID_SHIFT)
#define GPU_FAULTSTATUS_ADDRESS_VALID_GET(reg_val) \
(((reg_val)&GPU_FAULTSTATUS_ADDRESS_VALID_MASK) >> GPU_FAULTSTATUS_ADDRESS_VALID_SHIFT)
#define GPU_FAULTSTATUS_ADDRESS_VALID_SET(reg_val, value) \
(((reg_val) & ~GPU_FAULTSTATUS_ADDRESS_VALID_MASK) | \
(((value) << GPU_FAULTSTATUS_ADDRESS_VALID_SHIFT) & GPU_FAULTSTATUS_ADDRESS_VALID_MASK))
/* IRQ flags */
#define GPU_FAULT (1 << 0) /* A GPU Fault has occurred */
#define GPU_PROTECTED_FAULT (1 << 1) /* A GPU fault has occurred in protected mode */
#define RESET_COMPLETED (1 << 8) /* Set when a reset has completed. */
#define POWER_CHANGED_SINGLE (1 << 9) /* Set when a single core has finished powering up or down. */
#define POWER_CHANGED_ALL (1 << 10) /* Set when all cores have finished powering up or down. */
#define CLEAN_CACHES_COMPLETED (1 << 17) /* Set when a cache clean operation has completed. */
#define DOORBELL_MIRROR (1 << 18) /* Mirrors the doorbell interrupt line to the CPU */
#define MCU_STATUS_GPU_IRQ (1 << 19) /* MCU requires attention */
/*
* In Debug build,
* GPU_IRQ_REG_COMMON | POWER_CHANGED_SINGLE is used to clear and unmask interupts sources of GPU_IRQ
* by writing it onto GPU_IRQ_CLEAR/MASK registers.
*
* In Release build,
* GPU_IRQ_REG_COMMON is used.
*
* Note:
* CLEAN_CACHES_COMPLETED - Used separately for cache operation.
* DOORBELL_MIRROR - Do not have it included for GPU_IRQ_REG_COMMON
* as it can't be cleared by GPU_IRQ_CLEAR, thus interrupt storm might happen
*/
#define GPU_IRQ_REG_COMMON (GPU_FAULT | GPU_PROTECTED_FAULT | RESET_COMPLETED \
| POWER_CHANGED_ALL | MCU_STATUS_GPU_IRQ)
/* GPU_CONTROL_MCU.GPU_IRQ_RAWSTAT */
#define PRFCNT_SAMPLE_COMPLETED (1 << 16) /* Set when performance count sample has completed */
#endif /* _UAPI_KBASE_GPU_REGMAP_CSF_H_ */

267
include/uapi/gpu/arm/bifrost/gpu/backend/mali_kbase_gpu_regmap_jm.h
View File

@@ -22,276 +22,9 @@
#ifndef _UAPI_KBASE_GPU_REGMAP_JM_H_
#define _UAPI_KBASE_GPU_REGMAP_JM_H_
#if MALI_USE_CSF && defined(__KERNEL__)
#error "Cannot be compiled with CSF"
#endif
/* Set to implementation defined, outer caching */
#define AS_MEMATTR_AARCH64_OUTER_IMPL_DEF 0x88ull
/* Set to write back memory, outer caching */
#define AS_MEMATTR_AARCH64_OUTER_WA 0x8Dull
/* Set to inner non-cacheable, outer-non-cacheable
* Setting defined by the alloc bits is ignored, but set to a valid encoding:
* - no-alloc on read
* - no alloc on write
*/
#define AS_MEMATTR_AARCH64_NON_CACHEABLE 0x4Cull
/* Symbols for default MEMATTR to use
* Default is - HW implementation defined caching
*/
#define AS_MEMATTR_INDEX_DEFAULT 0
#define AS_MEMATTR_INDEX_DEFAULT_ACE 3
/* HW implementation defined caching */
#define AS_MEMATTR_INDEX_IMPL_DEF_CACHE_POLICY 0
/* Force cache on */
#define AS_MEMATTR_INDEX_FORCE_TO_CACHE_ALL 1
/* Write-alloc */
#define AS_MEMATTR_INDEX_WRITE_ALLOC 2
/* Outer coherent, inner implementation defined policy */
#define AS_MEMATTR_INDEX_OUTER_IMPL_DEF 3
/* Outer coherent, write alloc inner */
#define AS_MEMATTR_INDEX_OUTER_WA 4
/* Normal memory, inner non-cacheable, outer non-cacheable (ARMv8 mode only) */
#define AS_MEMATTR_INDEX_NON_CACHEABLE 5
/* GPU control registers */
#define CORE_FEATURES 0x008 /* (RO) Shader Core Features */
#define JS_PRESENT 0x01C /* (RO) Job slots present */
#define LATEST_FLUSH 0x038 /* (RO) Flush ID of latest
* clean-and-invalidate operation
*/
#define PRFCNT_BASE_LO 0x060 /* (RW) Performance counter memory
* region base address, low word
*/
#define PRFCNT_BASE_HI 0x064 /* (RW) Performance counter memory
* region base address, high word
*/
#define PRFCNT_CONFIG 0x068 /* (RW) Performance counter
* configuration
*/
#define PRFCNT_JM_EN 0x06C /* (RW) Performance counter enable
* flags for Job Manager
*/
#define PRFCNT_SHADER_EN 0x070 /* (RW) Performance counter enable
* flags for shader cores
*/
#define PRFCNT_TILER_EN 0x074 /* (RW) Performance counter enable
* flags for tiler
*/
#define PRFCNT_MMU_L2_EN 0x07C /* (RW) Performance counter enable
* flags for MMU/L2 cache
*/
#define JS0_FEATURES 0x0C0 /* (RO) Features of job slot 0 */
#define JS1_FEATURES 0x0C4 /* (RO) Features of job slot 1 */
#define JS2_FEATURES 0x0C8 /* (RO) Features of job slot 2 */
#define JS3_FEATURES 0x0CC /* (RO) Features of job slot 3 */
#define JS4_FEATURES 0x0D0 /* (RO) Features of job slot 4 */
#define JS5_FEATURES 0x0D4 /* (RO) Features of job slot 5 */
#define JS6_FEATURES 0x0D8 /* (RO) Features of job slot 6 */
#define JS7_FEATURES 0x0DC /* (RO) Features of job slot 7 */
#define JS8_FEATURES 0x0E0 /* (RO) Features of job slot 8 */
#define JS9_FEATURES 0x0E4 /* (RO) Features of job slot 9 */
#define JS10_FEATURES 0x0E8 /* (RO) Features of job slot 10 */
#define JS11_FEATURES 0x0EC /* (RO) Features of job slot 11 */
#define JS12_FEATURES 0x0F0 /* (RO) Features of job slot 12 */
#define JS13_FEATURES 0x0F4 /* (RO) Features of job slot 13 */
#define JS14_FEATURES 0x0F8 /* (RO) Features of job slot 14 */
#define JS15_FEATURES 0x0FC /* (RO) Features of job slot 15 */
#define JS_FEATURES_REG(n) GPU_CONTROL_REG(JS0_FEATURES + ((n) << 2))
#define JM_CONFIG 0xF00 /* (RW) Job manager configuration (implementation-specific) */
/* Job control registers */
#define JOB_IRQ_JS_STATE 0x010 /* status==active and _next == busy snapshot from last JOB_IRQ_CLEAR */
#define JOB_IRQ_THROTTLE 0x014 /* cycles to delay delivering an interrupt externally. The JOB_IRQ_STATUS is NOT affected by this, just the delivery of the interrupt. */
#define JOB_SLOT0 0x800 /* Configuration registers for job slot 0 */
#define JOB_SLOT1 0x880 /* Configuration registers for job slot 1 */
#define JOB_SLOT2 0x900 /* Configuration registers for job slot 2 */
#define JOB_SLOT3 0x980 /* Configuration registers for job slot 3 */
#define JOB_SLOT4 0xA00 /* Configuration registers for job slot 4 */
#define JOB_SLOT5 0xA80 /* Configuration registers for job slot 5 */
#define JOB_SLOT6 0xB00 /* Configuration registers for job slot 6 */
#define JOB_SLOT7 0xB80 /* Configuration registers for job slot 7 */
#define JOB_SLOT8 0xC00 /* Configuration registers for job slot 8 */
#define JOB_SLOT9 0xC80 /* Configuration registers for job slot 9 */
#define JOB_SLOT10 0xD00 /* Configuration registers for job slot 10 */
#define JOB_SLOT11 0xD80 /* Configuration registers for job slot 11 */
#define JOB_SLOT12 0xE00 /* Configuration registers for job slot 12 */
#define JOB_SLOT13 0xE80 /* Configuration registers for job slot 13 */
#define JOB_SLOT14 0xF00 /* Configuration registers for job slot 14 */
#define JOB_SLOT15 0xF80 /* Configuration registers for job slot 15 */
#define JOB_SLOT_REG(n, r) (JOB_CONTROL_REG(JOB_SLOT0 + ((n) << 7)) + (r))
#define JS_HEAD_LO 0x00 /* (RO) Job queue head pointer for job slot n, low word */
#define JS_HEAD_HI 0x04 /* (RO) Job queue head pointer for job slot n, high word */
#define JS_TAIL_LO 0x08 /* (RO) Job queue tail pointer for job slot n, low word */
#define JS_TAIL_HI 0x0C /* (RO) Job queue tail pointer for job slot n, high word */
#define JS_AFFINITY_LO 0x10 /* (RO) Core affinity mask for job slot n, low word */
#define JS_AFFINITY_HI 0x14 /* (RO) Core affinity mask for job slot n, high word */
#define JS_CONFIG 0x18 /* (RO) Configuration settings for job slot n */
/* (RO) Extended affinity mask for job slot n*/
#define JS_XAFFINITY 0x1C
#define JS_COMMAND 0x20 /* (WO) Command register for job slot n */
#define JS_STATUS 0x24 /* (RO) Status register for job slot n */
#define JS_HEAD_NEXT_LO 0x40 /* (RW) Next job queue head pointer for job slot n, low word */
#define JS_HEAD_NEXT_HI 0x44 /* (RW) Next job queue head pointer for job slot n, high word */
#define JS_AFFINITY_NEXT_LO 0x50 /* (RW) Next core affinity mask for job slot n, low word */
#define JS_AFFINITY_NEXT_HI 0x54 /* (RW) Next core affinity mask for job slot n, high word */
#define JS_CONFIG_NEXT 0x58 /* (RW) Next configuration settings for job slot n */
/* (RW) Next extended affinity mask for job slot n */
#define JS_XAFFINITY_NEXT 0x5C
#define JS_COMMAND_NEXT 0x60 /* (RW) Next command register for job slot n */
#define JS_FLUSH_ID_NEXT 0x70 /* (RW) Next job slot n cache flush ID */
/* No JM-specific MMU control registers */
/* No JM-specific MMU address space control registers */
/* JS_COMMAND register commands */
#define JS_COMMAND_NOP 0x00 /* NOP Operation. Writing this value is ignored */
#define JS_COMMAND_START 0x01 /* Start processing a job chain. Writing this value is ignored */
#define JS_COMMAND_SOFT_STOP 0x02 /* Gently stop processing a job chain */
#define JS_COMMAND_HARD_STOP 0x03 /* Rudely stop processing a job chain */
#define JS_COMMAND_SOFT_STOP_0 0x04 /* Execute SOFT_STOP if JOB_CHAIN_FLAG is 0 */
#define JS_COMMAND_HARD_STOP_0 0x05 /* Execute HARD_STOP if JOB_CHAIN_FLAG is 0 */
#define JS_COMMAND_SOFT_STOP_1 0x06 /* Execute SOFT_STOP if JOB_CHAIN_FLAG is 1 */
#define JS_COMMAND_HARD_STOP_1 0x07 /* Execute HARD_STOP if JOB_CHAIN_FLAG is 1 */
#define JS_COMMAND_MASK 0x07 /* Mask of bits currently in use by the HW */
/* Possible values of JS_CONFIG and JS_CONFIG_NEXT registers */
#define JS_CONFIG_START_FLUSH_NO_ACTION (0u << 0)
#define JS_CONFIG_START_FLUSH_CLEAN (1u << 8)
#define JS_CONFIG_START_FLUSH_INV_SHADER_OTHER (2u << 8)
#define JS_CONFIG_START_FLUSH_CLEAN_INVALIDATE (3u << 8)
#define JS_CONFIG_START_MMU (1u << 10)
#define JS_CONFIG_JOB_CHAIN_FLAG (1u << 11)
#define JS_CONFIG_END_FLUSH_NO_ACTION JS_CONFIG_START_FLUSH_NO_ACTION
#define JS_CONFIG_END_FLUSH_CLEAN (1u << 12)
#define JS_CONFIG_END_FLUSH_CLEAN_INVALIDATE (3u << 12)
#define JS_CONFIG_ENABLE_FLUSH_REDUCTION (1u << 14)
#define JS_CONFIG_DISABLE_DESCRIPTOR_WR_BK (1u << 15)
#define JS_CONFIG_THREAD_PRI(n) ((n) << 16)
/* JS_XAFFINITY register values */
#define JS_XAFFINITY_XAFFINITY_ENABLE (1u << 0)
#define JS_XAFFINITY_TILER_ENABLE (1u << 8)
#define JS_XAFFINITY_CACHE_ENABLE (1u << 16)
/* JS_STATUS register values */
/* NOTE: Please keep this values in sync with enum base_jd_event_code in mali_base_kernel.h.
* The values are separated to avoid dependency of userspace and kernel code.
*/
/* Group of values representing the job status instead of a particular fault */
#define JS_STATUS_NO_EXCEPTION_BASE 0x00
#define JS_STATUS_INTERRUPTED (JS_STATUS_NO_EXCEPTION_BASE + 0x02) /* 0x02 means INTERRUPTED */
#define JS_STATUS_STOPPED (JS_STATUS_NO_EXCEPTION_BASE + 0x03) /* 0x03 means STOPPED */
#define JS_STATUS_TERMINATED (JS_STATUS_NO_EXCEPTION_BASE + 0x04) /* 0x04 means TERMINATED */
/* General fault values */
#define JS_STATUS_FAULT_BASE 0x40
#define JS_STATUS_CONFIG_FAULT (JS_STATUS_FAULT_BASE) /* 0x40 means CONFIG FAULT */
#define JS_STATUS_POWER_FAULT (JS_STATUS_FAULT_BASE + 0x01) /* 0x41 means POWER FAULT */
#define JS_STATUS_READ_FAULT (JS_STATUS_FAULT_BASE + 0x02) /* 0x42 means READ FAULT */
#define JS_STATUS_WRITE_FAULT (JS_STATUS_FAULT_BASE + 0x03) /* 0x43 means WRITE FAULT */
#define JS_STATUS_AFFINITY_FAULT (JS_STATUS_FAULT_BASE + 0x04) /* 0x44 means AFFINITY FAULT */
#define JS_STATUS_BUS_FAULT (JS_STATUS_FAULT_BASE + 0x08) /* 0x48 means BUS FAULT */
/* Instruction or data faults */
#define JS_STATUS_INSTRUCTION_FAULT_BASE 0x50
#define JS_STATUS_INSTR_INVALID_PC (JS_STATUS_INSTRUCTION_FAULT_BASE) /* 0x50 means INSTR INVALID PC */
#define JS_STATUS_INSTR_INVALID_ENC (JS_STATUS_INSTRUCTION_FAULT_BASE + 0x01) /* 0x51 means INSTR INVALID ENC */
#define JS_STATUS_INSTR_TYPE_MISMATCH (JS_STATUS_INSTRUCTION_FAULT_BASE + 0x02) /* 0x52 means INSTR TYPE MISMATCH */
#define JS_STATUS_INSTR_OPERAND_FAULT (JS_STATUS_INSTRUCTION_FAULT_BASE + 0x03) /* 0x53 means INSTR OPERAND FAULT */
#define JS_STATUS_INSTR_TLS_FAULT (JS_STATUS_INSTRUCTION_FAULT_BASE + 0x04) /* 0x54 means INSTR TLS FAULT */
#define JS_STATUS_INSTR_BARRIER_FAULT (JS_STATUS_INSTRUCTION_FAULT_BASE + 0x05) /* 0x55 means INSTR BARRIER FAULT */
#define JS_STATUS_INSTR_ALIGN_FAULT (JS_STATUS_INSTRUCTION_FAULT_BASE + 0x06) /* 0x56 means INSTR ALIGN FAULT */
/* NOTE: No fault with 0x57 code defined in spec. */
#define JS_STATUS_DATA_INVALID_FAULT (JS_STATUS_INSTRUCTION_FAULT_BASE + 0x08) /* 0x58 means DATA INVALID FAULT */
#define JS_STATUS_TILE_RANGE_FAULT (JS_STATUS_INSTRUCTION_FAULT_BASE + 0x09) /* 0x59 means TILE RANGE FAULT */
#define JS_STATUS_ADDRESS_RANGE_FAULT (JS_STATUS_INSTRUCTION_FAULT_BASE + 0x0A) /* 0x5A means ADDRESS RANGE FAULT */
/* Other faults */
#define JS_STATUS_MEMORY_FAULT_BASE 0x60
#define JS_STATUS_OUT_OF_MEMORY (JS_STATUS_MEMORY_FAULT_BASE) /* 0x60 means OUT OF MEMORY */
#define JS_STATUS_UNKNOWN 0x7F /* 0x7F means UNKNOWN */
/* JS<n>_FEATURES register */
#define JS_FEATURE_NULL_JOB (1u << 1)
#define JS_FEATURE_SET_VALUE_JOB (1u << 2)
#define JS_FEATURE_CACHE_FLUSH_JOB (1u << 3)
#define JS_FEATURE_COMPUTE_JOB (1u << 4)
#define JS_FEATURE_VERTEX_JOB (1u << 5)
#define JS_FEATURE_GEOMETRY_JOB (1u << 6)
#define JS_FEATURE_TILER_JOB (1u << 7)
#define JS_FEATURE_FUSED_JOB (1u << 8)
#define JS_FEATURE_FRAGMENT_JOB (1u << 9)
/* JM_CONFIG register */
#define JM_TIMESTAMP_OVERRIDE (1ul << 0)
#define JM_CLOCK_GATE_OVERRIDE (1ul << 1)
#define JM_JOB_THROTTLE_ENABLE (1ul << 2)
#define JM_JOB_THROTTLE_LIMIT_SHIFT (3)
#define JM_MAX_JOB_THROTTLE_LIMIT (0x3F)
#define JM_FORCE_COHERENCY_FEATURES_SHIFT (2)
/* GPU_COMMAND values */
#define GPU_COMMAND_NOP 0x00 /* No operation, nothing happens */
#define GPU_COMMAND_SOFT_RESET 0x01 /* Stop all external bus interfaces, and then reset the entire GPU. */
#define GPU_COMMAND_HARD_RESET 0x02 /* Immediately reset the entire GPU. */
#define GPU_COMMAND_PRFCNT_CLEAR 0x03 /* Clear all performance counters, setting them all to zero. */
#define GPU_COMMAND_PRFCNT_SAMPLE 0x04 /* Sample all performance counters, writing them out to memory */
#define GPU_COMMAND_CYCLE_COUNT_START 0x05 /* Starts the cycle counter, and system timestamp propagation */
#define GPU_COMMAND_CYCLE_COUNT_STOP 0x06 /* Stops the cycle counter, and system timestamp propagation */
#define GPU_COMMAND_CLEAN_CACHES 0x07 /* Clean all caches */
#define GPU_COMMAND_CLEAN_INV_CACHES 0x08 /* Clean and invalidate all caches */
#define GPU_COMMAND_SET_PROTECTED_MODE 0x09 /* Places the GPU in protected mode */
/* GPU_COMMAND cache flush alias to CSF command payload */
#define GPU_COMMAND_CACHE_CLN_INV_L2 GPU_COMMAND_CLEAN_INV_CACHES
#define GPU_COMMAND_CACHE_CLN_INV_L2_LSC GPU_COMMAND_CLEAN_INV_CACHES
#define GPU_COMMAND_CACHE_CLN_INV_FULL GPU_COMMAND_CLEAN_INV_CACHES
/* Merge cache flush commands */
#define GPU_COMMAND_FLUSH_CACHE_MERGE(cmd1, cmd2) \
((cmd1) > (cmd2) ? (cmd1) : (cmd2))
/* IRQ flags */
#define GPU_FAULT (1 << 0) /* A GPU Fault has occurred */
#define MULTIPLE_GPU_FAULTS (1 << 7) /* More than one GPU Fault occurred. */
#define RESET_COMPLETED (1 << 8) /* Set when a reset has completed. */
#define POWER_CHANGED_SINGLE (1 << 9) /* Set when a single core has finished powering up or down. */
#define POWER_CHANGED_ALL (1 << 10) /* Set when all cores have finished powering up or down. */
#define PRFCNT_SAMPLE_COMPLETED (1 << 16) /* Set when a performance count sample has completed. */
#define CLEAN_CACHES_COMPLETED (1 << 17) /* Set when a cache clean operation has completed. */
/*
* In Debug build,
* GPU_IRQ_REG_COMMON | POWER_CHANGED_SINGLE is used to clear and enable interupts sources of GPU_IRQ
* by writing it onto GPU_IRQ_CLEAR/MASK registers.
*
* In Release build,
* GPU_IRQ_REG_COMMON is used.
*
* Note:
* CLEAN_CACHES_COMPLETED - Used separately for cache operation.
*/
#define GPU_IRQ_REG_COMMON (GPU_FAULT | MULTIPLE_GPU_FAULTS | RESET_COMPLETED \
| POWER_CHANGED_ALL | PRFCNT_SAMPLE_COMPLETED)
#endif /* _UAPI_KBASE_GPU_REGMAP_JM_H_ */

38
include/uapi/gpu/arm/bifrost/gpu/mali_kbase_gpu_id.h
View File

@@ -1,7 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
/*
*
* (C) COPYRIGHT 2015-2021 ARM Limited. All rights reserved.
* (C) COPYRIGHT 2015-2022 ARM Limited. All rights reserved.
*
* This program is free software and is provided to you under the terms of the
* GNU General Public License version 2 as published by the Free Software
@@ -25,14 +25,15 @@
#include <linux/types.h>
/* GPU_ID register */
#define GPU_ID_VERSION_STATUS_SHIFT 0
#define GPU_ID_VERSION_MINOR_SHIFT 4
#define GPU_ID_VERSION_MAJOR_SHIFT 12
#define GPU_ID_VERSION_PRODUCT_ID_SHIFT 16
#define GPU_ID_VERSION_STATUS (0xFu << GPU_ID_VERSION_STATUS_SHIFT)
#define GPU_ID_VERSION_MINOR (0xFFu << GPU_ID_VERSION_MINOR_SHIFT)
#define GPU_ID_VERSION_MAJOR (0xFu << GPU_ID_VERSION_MAJOR_SHIFT)
#define GPU_ID_VERSION_PRODUCT_ID (0xFFFFu << GPU_ID_VERSION_PRODUCT_ID_SHIFT)
#define KBASE_GPU_ID_VERSION_STATUS_SHIFT 0
#define KBASE_GPU_ID_VERSION_MINOR_SHIFT 4
#define KBASE_GPU_ID_VERSION_MAJOR_SHIFT 12
#define KBASE_GPU_ID_VERSION_PRODUCT_ID_SHIFT 16
#define GPU_ID_VERSION_STATUS (0xFu << KBASE_GPU_ID_VERSION_STATUS_SHIFT)
#define GPU_ID_VERSION_MINOR (0xFFu << KBASE_GPU_ID_VERSION_MINOR_SHIFT)
#define GPU_ID_VERSION_MAJOR (0xFu << KBASE_GPU_ID_VERSION_MAJOR_SHIFT)
#define GPU_ID_VERSION_PRODUCT_ID (0xFFFFu << KBASE_GPU_ID_VERSION_PRODUCT_ID_SHIFT)
#define GPU_ID2_VERSION_STATUS_SHIFT 0
#define GPU_ID2_VERSION_MINOR_SHIFT 4
@@ -126,13 +127,18 @@
#define GPU_ID2_PRODUCT_TTUX GPU_ID2_MODEL_MAKE(11, 2)
#define GPU_ID2_PRODUCT_LTUX GPU_ID2_MODEL_MAKE(11, 3)
/* Helper macro to create a GPU_ID assuming valid values for id, major,
* minor, status
/**
* GPU_ID_MAKE - Helper macro to generate GPU_ID using id, major, minor, status
*
* @id: Product Major of GPU ID
* @major: Version major of GPU ID
* @minor: Version minor of GPU ID
* @status: Version status of GPU ID
*/
#define GPU_ID_MAKE(id, major, minor, status) \
((((__u32)id) << GPU_ID_VERSION_PRODUCT_ID_SHIFT) | \
(((__u32)major) << GPU_ID_VERSION_MAJOR_SHIFT) | \
(((__u32)minor) << GPU_ID_VERSION_MINOR_SHIFT) | \
(((__u32)status) << GPU_ID_VERSION_STATUS_SHIFT))
#define GPU_ID_MAKE(id, major, minor, status) \
((((__u32)id) << KBASE_GPU_ID_VERSION_PRODUCT_ID_SHIFT) | \
(((__u32)major) << KBASE_GPU_ID_VERSION_MAJOR_SHIFT) | \
(((__u32)minor) << KBASE_GPU_ID_VERSION_MINOR_SHIFT) | \
(((__u32)status) << KBASE_GPU_ID_VERSION_STATUS_SHIFT))
#endif /* _UAPI_KBASE_GPU_ID_H_ */

561
include/uapi/gpu/arm/bifrost/gpu/mali_kbase_gpu_regmap.h
View File

@@ -1,7 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
/*
*
* (C) COPYRIGHT 2021 ARM Limited. All rights reserved.
* (C) COPYRIGHT 2019-2021 ARM Limited. All rights reserved.
*
* This program is free software and is provided to you under the terms of the
* GNU General Public License version 2 as published by the Free Software
@@ -22,568 +22,13 @@
#ifndef _UAPI_KBASE_GPU_REGMAP_H_
#define _UAPI_KBASE_GPU_REGMAP_H_
#include "mali_kbase_gpu_coherency.h"
#include "mali_kbase_gpu_id.h"
#if MALI_USE_CSF
#include "backend/mali_kbase_gpu_regmap_csf.h"
#else
#if !MALI_USE_CSF
#include "backend/mali_kbase_gpu_regmap_jm.h"
#endif
/* GPU_U definition */
#ifdef __ASSEMBLER__
#define GPU_U(x) x
#else
#define GPU_U(x) x##u
#endif /* __ASSEMBLER__ */
/* Begin Register Offsets */
/* GPU control registers */
#define GPU_CONTROL_BASE 0x0000
#define GPU_CONTROL_REG(r) (GPU_CONTROL_BASE + (r))
#define GPU_ID 0x000 /* (RO) GPU and revision identifier */
#define L2_FEATURES 0x004 /* (RO) Level 2 cache features */
#define TILER_FEATURES 0x00C /* (RO) Tiler Features */
#define MEM_FEATURES 0x010 /* (RO) Memory system features */
#define MMU_FEATURES 0x014 /* (RO) MMU features */
#define AS_PRESENT 0x018 /* (RO) Address space slots present */
#define GPU_IRQ_RAWSTAT 0x020 /* (RW) */
#define GPU_IRQ_CLEAR 0x024 /* (WO) */
#define GPU_IRQ_MASK 0x028 /* (RW) */
#define GPU_IRQ_STATUS 0x02C /* (RO) */
#define GPU_COMMAND 0x030 /* (WO) */
#define GPU_STATUS 0x034 /* (RO) */
#define GPU_DBGEN (1 << 8) /* DBGEN wire status */
#define GPU_FAULTSTATUS 0x03C /* (RO) GPU exception type and fault status */
#define GPU_FAULTADDRESS_LO 0x040 /* (RO) GPU exception fault address, low word */
#define GPU_FAULTADDRESS_HI 0x044 /* (RO) GPU exception fault address, high word */
#define L2_CONFIG 0x048 /* (RW) Level 2 cache configuration */
#define GROUPS_L2_COHERENT (1 << 0) /* Cores groups are l2 coherent */
#define SUPER_L2_COHERENT (1 << 1) /* Shader cores within a core
* supergroup are l2 coherent
*/
#define PWR_KEY 0x050 /* (WO) Power manager key register */
#define PWR_OVERRIDE0 0x054 /* (RW) Power manager override settings */
#define PWR_OVERRIDE1 0x058 /* (RW) Power manager override settings */
#define GPU_FEATURES_LO 0x060 /* (RO) GPU features, low word */
#define GPU_FEATURES_HI 0x064 /* (RO) GPU features, high word */
#define PRFCNT_FEATURES 0x068 /* (RO) Performance counter features */
#define TIMESTAMP_OFFSET_LO 0x088 /* (RW) Global time stamp offset, low word */
#define TIMESTAMP_OFFSET_HI 0x08C /* (RW) Global time stamp offset, high word */
#define CYCLE_COUNT_LO 0x090 /* (RO) Cycle counter, low word */
#define CYCLE_COUNT_HI 0x094 /* (RO) Cycle counter, high word */
#define TIMESTAMP_LO 0x098 /* (RO) Global time stamp counter, low word */
#define TIMESTAMP_HI 0x09C /* (RO) Global time stamp counter, high word */
#define THREAD_MAX_THREADS 0x0A0 /* (RO) Maximum number of threads per core */
#define THREAD_MAX_WORKGROUP_SIZE 0x0A4 /* (RO) Maximum workgroup size */
#define THREAD_MAX_BARRIER_SIZE 0x0A8 /* (RO) Maximum threads waiting at a barrier */
#define THREAD_FEATURES 0x0AC /* (RO) Thread features */
#define THREAD_TLS_ALLOC 0x310 /* (RO) Number of threads per core that TLS must be allocated for */
#define TEXTURE_FEATURES_0 0x0B0 /* (RO) Support flags for indexed texture formats 0..31 */
#define TEXTURE_FEATURES_1 0x0B4 /* (RO) Support flags for indexed texture formats 32..63 */
#define TEXTURE_FEATURES_2 0x0B8 /* (RO) Support flags for indexed texture formats 64..95 */
#define TEXTURE_FEATURES_3 0x0BC /* (RO) Support flags for texture order */
#define TEXTURE_FEATURES_REG(n) GPU_CONTROL_REG(TEXTURE_FEATURES_0 + ((n) << 2))
#define SHADER_PRESENT_LO 0x100 /* (RO) Shader core present bitmap, low word */
#define SHADER_PRESENT_HI 0x104 /* (RO) Shader core present bitmap, high word */
#define TILER_PRESENT_LO 0x110 /* (RO) Tiler core present bitmap, low word */
#define TILER_PRESENT_HI 0x114 /* (RO) Tiler core present bitmap, high word */
#define L2_PRESENT_LO 0x120 /* (RO) Level 2 cache present bitmap, low word */
#define L2_PRESENT_HI 0x124 /* (RO) Level 2 cache present bitmap, high word */
#define STACK_PRESENT_LO 0xE00 /* (RO) Core stack present bitmap, low word */
#define STACK_PRESENT_HI 0xE04 /* (RO) Core stack present bitmap, high word */
#define SHADER_READY_LO 0x140 /* (RO) Shader core ready bitmap, low word */
#define SHADER_READY_HI 0x144 /* (RO) Shader core ready bitmap, high word */
#define TILER_READY_LO 0x150 /* (RO) Tiler core ready bitmap, low word */
#define TILER_READY_HI 0x154 /* (RO) Tiler core ready bitmap, high word */
#define L2_READY_LO 0x160 /* (RO) Level 2 cache ready bitmap, low word */
#define L2_READY_HI 0x164 /* (RO) Level 2 cache ready bitmap, high word */
#define STACK_READY_LO 0xE10 /* (RO) Core stack ready bitmap, low word */
#define STACK_READY_HI 0xE14 /* (RO) Core stack ready bitmap, high word */
#define SHADER_PWRON_LO 0x180 /* (WO) Shader core power on bitmap, low word */
#define SHADER_PWRON_HI 0x184 /* (WO) Shader core power on bitmap, high word */
#define TILER_PWRON_LO 0x190 /* (WO) Tiler core power on bitmap, low word */
#define TILER_PWRON_HI 0x194 /* (WO) Tiler core power on bitmap, high word */
#define L2_PWRON_LO 0x1A0 /* (WO) Level 2 cache power on bitmap, low word */
#define L2_PWRON_HI 0x1A4 /* (WO) Level 2 cache power on bitmap, high word */
#define STACK_PWRON_LO 0xE20 /* (RO) Core stack power on bitmap, low word */
#define STACK_PWRON_HI 0xE24 /* (RO) Core stack power on bitmap, high word */
#define SHADER_PWROFF_LO 0x1C0 /* (WO) Shader core power off bitmap, low word */
#define SHADER_PWROFF_HI 0x1C4 /* (WO) Shader core power off bitmap, high word */
#define TILER_PWROFF_LO 0x1D0 /* (WO) Tiler core power off bitmap, low word */
#define TILER_PWROFF_HI 0x1D4 /* (WO) Tiler core power off bitmap, high word */
#define L2_PWROFF_LO 0x1E0 /* (WO) Level 2 cache power off bitmap, low word */
#define L2_PWROFF_HI 0x1E4 /* (WO) Level 2 cache power off bitmap, high word */
#define STACK_PWROFF_LO 0xE30 /* (RO) Core stack power off bitmap, low word */
#define STACK_PWROFF_HI 0xE34 /* (RO) Core stack power off bitmap, high word */
#define SHADER_PWRTRANS_LO 0x200 /* (RO) Shader core power transition bitmap, low word */
#define SHADER_PWRTRANS_HI 0x204 /* (RO) Shader core power transition bitmap, high word */
#define TILER_PWRTRANS_LO 0x210 /* (RO) Tiler core power transition bitmap, low word */
#define TILER_PWRTRANS_HI 0x214 /* (RO) Tiler core power transition bitmap, high word */
#define L2_PWRTRANS_LO 0x220 /* (RO) Level 2 cache power transition bitmap, low word */
#define L2_PWRTRANS_HI 0x224 /* (RO) Level 2 cache power transition bitmap, high word */
#define ASN_HASH_0 0x02C0 /* (RW) ASN hash function argument 0 */
#define ASN_HASH(n) (ASN_HASH_0 + (n)*4)
#define ASN_HASH_COUNT 3
#define SYSC_ALLOC0 0x0340 /* (RW) System cache allocation hint from source ID */
#define SYSC_ALLOC(n) (SYSC_ALLOC0 + (n)*4)
#define SYSC_ALLOC_COUNT 8
#define STACK_PWRTRANS_LO 0xE40 /* (RO) Core stack power transition bitmap, low word */
#define STACK_PWRTRANS_HI 0xE44 /* (RO) Core stack power transition bitmap, high word */
#define SHADER_PWRACTIVE_LO 0x240 /* (RO) Shader core active bitmap, low word */
#define SHADER_PWRACTIVE_HI 0x244 /* (RO) Shader core active bitmap, high word */
#define TILER_PWRACTIVE_LO 0x250 /* (RO) Tiler core active bitmap, low word */
#define TILER_PWRACTIVE_HI 0x254 /* (RO) Tiler core active bitmap, high word */
#define L2_PWRACTIVE_LO 0x260 /* (RO) Level 2 cache active bitmap, low word */
#define L2_PWRACTIVE_HI 0x264 /* (RO) Level 2 cache active bitmap, high word */
#define COHERENCY_FEATURES 0x300 /* (RO) Coherency features present */
#define COHERENCY_ENABLE 0x304 /* (RW) Coherency enable */
#define SHADER_CONFIG 0xF04 /* (RW) Shader core configuration (implementation-specific) */
#define TILER_CONFIG 0xF08 /* (RW) Tiler core configuration (implementation-specific) */
#define L2_MMU_CONFIG 0xF0C /* (RW) L2 cache and MMU configuration (implementation-specific) */
/* Job control registers */
#define JOB_CONTROL_BASE 0x1000
#define JOB_CONTROL_REG(r) (JOB_CONTROL_BASE + (r))
#define JOB_IRQ_RAWSTAT 0x000 /* Raw interrupt status register */
#define JOB_IRQ_CLEAR 0x004 /* Interrupt clear register */
#define JOB_IRQ_MASK 0x008 /* Interrupt mask register */
#define JOB_IRQ_STATUS 0x00C /* Interrupt status register */
#endif /* !MALI_USE_CSF */
/* MMU control registers */
#define MEMORY_MANAGEMENT_BASE 0x2000
#define MMU_REG(r) (MEMORY_MANAGEMENT_BASE + (r))
#define MMU_IRQ_RAWSTAT 0x000 /* (RW) Raw interrupt status register */
#define MMU_IRQ_CLEAR 0x004 /* (WO) Interrupt clear register */
#define MMU_IRQ_MASK 0x008 /* (RW) Interrupt mask register */
#define MMU_IRQ_STATUS 0x00C /* (RO) Interrupt status register */
#define MMU_AS0 0x400 /* Configuration registers for address space 0 */
#define MMU_AS1 0x440 /* Configuration registers for address space 1 */
#define MMU_AS2 0x480 /* Configuration registers for address space 2 */
#define MMU_AS3 0x4C0 /* Configuration registers for address space 3 */
#define MMU_AS4 0x500 /* Configuration registers for address space 4 */
#define MMU_AS5 0x540 /* Configuration registers for address space 5 */
#define MMU_AS6 0x580 /* Configuration registers for address space 6 */
#define MMU_AS7 0x5C0 /* Configuration registers for address space 7 */
#define MMU_AS8 0x600 /* Configuration registers for address space 8 */
#define MMU_AS9 0x640 /* Configuration registers for address space 9 */
#define MMU_AS10 0x680 /* Configuration registers for address space 10 */
#define MMU_AS11 0x6C0 /* Configuration registers for address space 11 */
#define MMU_AS12 0x700 /* Configuration registers for address space 12 */
#define MMU_AS13 0x740 /* Configuration registers for address space 13 */
#define MMU_AS14 0x780 /* Configuration registers for address space 14 */
#define MMU_AS15 0x7C0 /* Configuration registers for address space 15 */
/* MMU address space control registers */
#define MMU_AS_REG(n, r) (MMU_REG(MMU_AS0 + ((n) << 6)) + (r))
#define AS_TRANSTAB_LO 0x00 /* (RW) Translation Table Base Address for address space n, low word */
#define AS_TRANSTAB_HI 0x04 /* (RW) Translation Table Base Address for address space n, high word */
#define AS_MEMATTR_LO 0x08 /* (RW) Memory attributes for address space n, low word. */
#define AS_MEMATTR_HI 0x0C /* (RW) Memory attributes for address space n, high word. */
#define AS_LOCKADDR_LO 0x10 /* (RW) Lock region address for address space n, low word */
#define AS_LOCKADDR_HI 0x14 /* (RW) Lock region address for address space n, high word */
#define AS_COMMAND 0x18 /* (WO) MMU command register for address space n */
#define AS_FAULTSTATUS 0x1C /* (RO) MMU fault status register for address space n */
#define AS_FAULTADDRESS_LO 0x20 /* (RO) Fault Address for address space n, low word */
#define AS_FAULTADDRESS_HI 0x24 /* (RO) Fault Address for address space n, high word */
#define AS_STATUS 0x28 /* (RO) Status flags for address space n */
/* (RW) Translation table configuration for address space n, low word */
#define AS_TRANSCFG_LO 0x30
/* (RW) Translation table configuration for address space n, high word */
#define AS_TRANSCFG_HI 0x34
/* (RO) Secondary fault address for address space n, low word */
#define AS_FAULTEXTRA_LO 0x38
/* (RO) Secondary fault address for address space n, high word */
#define AS_FAULTEXTRA_HI 0x3C
/* End Register Offsets */
#define GPU_IRQ_REG_ALL (GPU_IRQ_REG_COMMON)
/*
* MMU_IRQ_RAWSTAT register values. Values are valid also for
* MMU_IRQ_CLEAR, MMU_IRQ_MASK, MMU_IRQ_STATUS registers.
*/
#define MMU_PAGE_FAULT_FLAGS 16
/* Macros returning a bitmask to retrieve page fault or bus error flags from
* MMU registers
*/
#define MMU_PAGE_FAULT(n) (1UL << (n))
#define MMU_BUS_ERROR(n) (1UL << ((n) + MMU_PAGE_FAULT_FLAGS))
/*
* Begin AARCH64 MMU TRANSTAB register values
*/
#define MMU_HW_OUTA_BITS 40
#define AS_TRANSTAB_BASE_MASK ((1ULL << MMU_HW_OUTA_BITS) - (1ULL << 4))
/*
* Begin MMU STATUS register values
*/
#define AS_STATUS_AS_ACTIVE 0x01
#define AS_FAULTSTATUS_EXCEPTION_CODE_MASK (0x7<<3)
#define AS_FAULTSTATUS_EXCEPTION_CODE_TRANSLATION_FAULT (0x0<<3)
#define AS_FAULTSTATUS_EXCEPTION_CODE_PERMISSION_FAULT (0x1<<3)
#define AS_FAULTSTATUS_EXCEPTION_CODE_TRANSTAB_BUS_FAULT (0x2<<3)
#define AS_FAULTSTATUS_EXCEPTION_CODE_ACCESS_FLAG (0x3<<3)
#define AS_FAULTSTATUS_EXCEPTION_CODE_ADDRESS_SIZE_FAULT (0x4<<3)
#define AS_FAULTSTATUS_EXCEPTION_CODE_MEMORY_ATTRIBUTES_FAULT (0x5<<3)
#define AS_FAULTSTATUS_EXCEPTION_TYPE_SHIFT 0
#define AS_FAULTSTATUS_EXCEPTION_TYPE_MASK (0xFF << AS_FAULTSTATUS_EXCEPTION_TYPE_SHIFT)
#define AS_FAULTSTATUS_EXCEPTION_TYPE_GET(reg_val) \
(((reg_val)&AS_FAULTSTATUS_EXCEPTION_TYPE_MASK) >> AS_FAULTSTATUS_EXCEPTION_TYPE_SHIFT)
#define AS_FAULTSTATUS_EXCEPTION_TYPE_TRANSLATION_FAULT_0 0xC0
#define AS_FAULTSTATUS_ACCESS_TYPE_SHIFT 8
#define AS_FAULTSTATUS_ACCESS_TYPE_MASK (0x3 << AS_FAULTSTATUS_ACCESS_TYPE_SHIFT)
#define AS_FAULTSTATUS_ACCESS_TYPE_GET(reg_val) \
(((reg_val)&AS_FAULTSTATUS_ACCESS_TYPE_MASK) >> AS_FAULTSTATUS_ACCESS_TYPE_SHIFT)
#define AS_FAULTSTATUS_ACCESS_TYPE_ATOMIC (0x0)
#define AS_FAULTSTATUS_ACCESS_TYPE_EX (0x1)
#define AS_FAULTSTATUS_ACCESS_TYPE_READ (0x2)
#define AS_FAULTSTATUS_ACCESS_TYPE_WRITE (0x3)
#define AS_FAULTSTATUS_SOURCE_ID_SHIFT 16
#define AS_FAULTSTATUS_SOURCE_ID_MASK (0xFFFF << AS_FAULTSTATUS_SOURCE_ID_SHIFT)
#define AS_FAULTSTATUS_SOURCE_ID_GET(reg_val) \
(((reg_val)&AS_FAULTSTATUS_SOURCE_ID_MASK) >> AS_FAULTSTATUS_SOURCE_ID_SHIFT)
#define PRFCNT_FEATURES_COUNTER_BLOCK_SIZE_SHIFT (0)
#define PRFCNT_FEATURES_COUNTER_BLOCK_SIZE_MASK \
((0xFF) << PRFCNT_FEATURES_COUNTER_BLOCK_SIZE_SHIFT)
#define PRFCNT_FEATURES_COUNTER_BLOCK_SIZE_GET(reg_val) \
(((reg_val)&PRFCNT_FEATURES_COUNTER_BLOCK_SIZE_MASK) >> \
PRFCNT_FEATURES_COUNTER_BLOCK_SIZE_SHIFT)
/*
* Begin MMU TRANSCFG register values
*/
#define AS_TRANSCFG_ADRMODE_LEGACY 0
#define AS_TRANSCFG_ADRMODE_UNMAPPED 1
#define AS_TRANSCFG_ADRMODE_IDENTITY 2
#define AS_TRANSCFG_ADRMODE_AARCH64_4K 6
#define AS_TRANSCFG_ADRMODE_AARCH64_64K 8
#define AS_TRANSCFG_ADRMODE_MASK 0xF
/*
* Begin TRANSCFG register values
*/
#define AS_TRANSCFG_PTW_MEMATTR_MASK (3ull << 24)
#define AS_TRANSCFG_PTW_MEMATTR_NON_CACHEABLE (1ull << 24)
#define AS_TRANSCFG_PTW_MEMATTR_WRITE_BACK (2ull << 24)
#define AS_TRANSCFG_PTW_SH_MASK ((3ull << 28))
#define AS_TRANSCFG_PTW_SH_OS (2ull << 28)
#define AS_TRANSCFG_PTW_SH_IS (3ull << 28)
#define AS_TRANSCFG_R_ALLOCATE (1ull << 30)
/*
* Begin Command Values
*/
/* AS_COMMAND register commands */
#define AS_COMMAND_NOP 0x00 /* NOP Operation */
#define AS_COMMAND_UPDATE 0x01 /* Broadcasts the values in AS_TRANSTAB and ASn_MEMATTR to all MMUs */
#define AS_COMMAND_LOCK 0x02 /* Issue a lock region command to all MMUs */
#define AS_COMMAND_UNLOCK 0x03 /* Issue a flush region command to all MMUs */
/* Flush all L2 caches then issue a flush region command to all MMUs */
#define AS_COMMAND_FLUSH_PT 0x04
/* Wait for memory accesses to complete, flush all the L1s cache then flush all
* L2 caches then issue a flush region command to all MMUs
*/
#define AS_COMMAND_FLUSH_MEM 0x05
/* AS_LOCKADDR register */
#define AS_LOCKADDR_LOCKADDR_SIZE_SHIFT GPU_U(0)
#define AS_LOCKADDR_LOCKADDR_SIZE_MASK \
(GPU_U(0x3F) << AS_LOCKADDR_LOCKADDR_SIZE_SHIFT)
#define AS_LOCKADDR_LOCKADDR_SIZE_GET(reg_val) \
(((reg_val)&AS_LOCKADDR_LOCKADDR_SIZE_MASK) >> \
AS_LOCKADDR_LOCKADDR_SIZE_SHIFT)
#define AS_LOCKADDR_LOCKADDR_SIZE_SET(reg_val, value) \
(((reg_val) & ~AS_LOCKADDR_LOCKADDR_SIZE_MASK) | \
(((value) << AS_LOCKADDR_LOCKADDR_SIZE_SHIFT) & \
AS_LOCKADDR_LOCKADDR_SIZE_MASK))
#define AS_LOCKADDR_LOCKADDR_BASE_SHIFT GPU_U(12)
#define AS_LOCKADDR_LOCKADDR_BASE_MASK \
(GPU_U(0xFFFFFFFFFFFFF) << AS_LOCKADDR_LOCKADDR_BASE_SHIFT)
#define AS_LOCKADDR_LOCKADDR_BASE_GET(reg_val) \
(((reg_val)&AS_LOCKADDR_LOCKADDR_BASE_MASK) >> \
AS_LOCKADDR_LOCKADDR_BASE_SHIFT)
#define AS_LOCKADDR_LOCKADDR_BASE_SET(reg_val, value) \
(((reg_val) & ~AS_LOCKADDR_LOCKADDR_BASE_MASK) | \
(((value) << AS_LOCKADDR_LOCKADDR_BASE_SHIFT) & \
AS_LOCKADDR_LOCKADDR_BASE_MASK))
/* GPU_STATUS values */
#define GPU_STATUS_PRFCNT_ACTIVE (1 << 2) /* Set if the performance counters are active. */
#define GPU_STATUS_CYCLE_COUNT_ACTIVE (1 << 6) /* Set if the cycle counter is active. */
#define GPU_STATUS_PROTECTED_MODE_ACTIVE (1 << 7) /* Set if protected mode is active */
/* PRFCNT_CONFIG register values */
#define PRFCNT_CONFIG_MODE_SHIFT 0 /* Counter mode position. */
#define PRFCNT_CONFIG_AS_SHIFT 4 /* Address space bitmap position. */
#define PRFCNT_CONFIG_SETSELECT_SHIFT 8 /* Set select position. */
/* The performance counters are disabled. */
#define PRFCNT_CONFIG_MODE_OFF 0
/* The performance counters are enabled, but are only written out when a
* PRFCNT_SAMPLE command is issued using the GPU_COMMAND register.
*/
#define PRFCNT_CONFIG_MODE_MANUAL 1
/* The performance counters are enabled, and are written out each time a tile
* finishes rendering.
*/
#define PRFCNT_CONFIG_MODE_TILE 2
/* AS<n>_MEMATTR values from MMU_MEMATTR_STAGE1: */
/* Use GPU implementation-defined caching policy. */
#define AS_MEMATTR_IMPL_DEF_CACHE_POLICY 0x88ull
/* The attribute set to force all resources to be cached. */
#define AS_MEMATTR_FORCE_TO_CACHE_ALL 0x8Full
/* Inner write-alloc cache setup, no outer caching */
#define AS_MEMATTR_WRITE_ALLOC 0x8Dull
/* Use GPU implementation-defined caching policy. */
#define AS_MEMATTR_LPAE_IMPL_DEF_CACHE_POLICY 0x48ull
/* The attribute set to force all resources to be cached. */
#define AS_MEMATTR_LPAE_FORCE_TO_CACHE_ALL 0x4Full
/* Inner write-alloc cache setup, no outer caching */
#define AS_MEMATTR_LPAE_WRITE_ALLOC 0x4Dull
/* Set to implementation defined, outer caching */
#define AS_MEMATTR_LPAE_OUTER_IMPL_DEF 0x88ull
/* Set to write back memory, outer caching */
#define AS_MEMATTR_LPAE_OUTER_WA 0x8Dull
/* There is no LPAE support for non-cacheable, since the memory type is always
* write-back.
* Marking this setting as reserved for LPAE
*/
#define AS_MEMATTR_LPAE_NON_CACHEABLE_RESERVED
/* L2_MMU_CONFIG register */
#define L2_MMU_CONFIG_ALLOW_SNOOP_DISPARITY_SHIFT (23)
#define L2_MMU_CONFIG_ALLOW_SNOOP_DISPARITY (0x1 << L2_MMU_CONFIG_ALLOW_SNOOP_DISPARITY_SHIFT)
/* End L2_MMU_CONFIG register */
/* THREAD_* registers */
/* THREAD_FEATURES IMPLEMENTATION_TECHNOLOGY values */
#define IMPLEMENTATION_UNSPECIFIED 0
#define IMPLEMENTATION_SILICON 1
#define IMPLEMENTATION_FPGA 2
#define IMPLEMENTATION_MODEL 3
/* Default values when registers are not supported by the implemented hardware */
#define THREAD_MT_DEFAULT 256
#define THREAD_MWS_DEFAULT 256
#define THREAD_MBS_DEFAULT 256
#define THREAD_MR_DEFAULT 1024
#define THREAD_MTQ_DEFAULT 4
#define THREAD_MTGS_DEFAULT 10
/* End THREAD_* registers */
/* SHADER_CONFIG register */
#define SC_LS_ALLOW_ATTR_TYPES (1ul << 16)
#define SC_TLS_HASH_ENABLE (1ul << 17)
#define SC_LS_ATTR_CHECK_DISABLE (1ul << 18)
#define SC_VAR_ALGORITHM (1ul << 29)
/* End SHADER_CONFIG register */
/* TILER_CONFIG register */
#define TC_CLOCK_GATE_OVERRIDE (1ul << 0)
/* End TILER_CONFIG register */
/* L2_CONFIG register */
#define L2_CONFIG_SIZE_SHIFT 16
#define L2_CONFIG_SIZE_MASK (0xFFul << L2_CONFIG_SIZE_SHIFT)
#define L2_CONFIG_HASH_SHIFT 24
#define L2_CONFIG_HASH_MASK (0xFFul << L2_CONFIG_HASH_SHIFT)
#define L2_CONFIG_ASN_HASH_ENABLE_SHIFT 24
#define L2_CONFIG_ASN_HASH_ENABLE_MASK (1ul << L2_CONFIG_ASN_HASH_ENABLE_SHIFT)
/* End L2_CONFIG register */
/* IDVS_GROUP register */
#define IDVS_GROUP_SIZE_SHIFT (16)
#define IDVS_GROUP_MAX_SIZE (0x3F)
/* SYSC_ALLOC read IDs */
#define SYSC_ALLOC_ID_R_OTHER 0x00
#define SYSC_ALLOC_ID_R_CSF 0x02
#define SYSC_ALLOC_ID_R_MMU 0x04
#define SYSC_ALLOC_ID_R_TILER_VERT 0x08
#define SYSC_ALLOC_ID_R_TILER_PTR 0x09
#define SYSC_ALLOC_ID_R_TILER_INDEX 0x0A
#define SYSC_ALLOC_ID_R_TILER_OTHER 0x0B
#define SYSC_ALLOC_ID_R_IC 0x10
#define SYSC_ALLOC_ID_R_ATTR 0x11
#define SYSC_ALLOC_ID_R_SCM 0x12
#define SYSC_ALLOC_ID_R_FSDC 0x13
#define SYSC_ALLOC_ID_R_VL 0x14
#define SYSC_ALLOC_ID_R_PLR 0x15
#define SYSC_ALLOC_ID_R_TEX 0x18
#define SYSC_ALLOC_ID_R_LSC 0x1c
/* SYSC_ALLOC write IDs */
#define SYSC_ALLOC_ID_W_OTHER 0x00
#define SYSC_ALLOC_ID_W_CSF 0x02
#define SYSC_ALLOC_ID_W_PCB 0x07
#define SYSC_ALLOC_ID_W_TILER_PTR 0x09
#define SYSC_ALLOC_ID_W_TILER_VERT_PLIST 0x0A
#define SYSC_ALLOC_ID_W_TILER_OTHER 0x0B
#define SYSC_ALLOC_ID_W_L2_EVICT 0x0C
#define SYSC_ALLOC_ID_W_L2_FLUSH 0x0D
#define SYSC_ALLOC_ID_W_TIB_COLOR 0x10
#define SYSC_ALLOC_ID_W_TIB_COLOR_AFBCH 0x11
#define SYSC_ALLOC_ID_W_TIB_COLOR_AFBCB 0x12
#define SYSC_ALLOC_ID_W_TIB_CRC 0x13
#define SYSC_ALLOC_ID_W_TIB_DS 0x14
#define SYSC_ALLOC_ID_W_TIB_DS_AFBCH 0x15
#define SYSC_ALLOC_ID_W_TIB_DS_AFBCB 0x16
#define SYSC_ALLOC_ID_W_LSC 0x1C
/* SYSC_ALLOC values */
#define SYSC_ALLOC_L2_ALLOC 0x0
#define SYSC_ALLOC_NEVER_ALLOC 0x2
#define SYSC_ALLOC_ALWAYS_ALLOC 0x3
#define SYSC_ALLOC_PTL_ALLOC 0x4
#define SYSC_ALLOC_L2_PTL_ALLOC 0x5
/* SYSC_ALLOC register */
#define SYSC_ALLOC_R_SYSC_ALLOC0_SHIFT (0)
#define SYSC_ALLOC_R_SYSC_ALLOC0_MASK ((0xF) << SYSC_ALLOC_R_SYSC_ALLOC0_SHIFT)
#define SYSC_ALLOC_R_SYSC_ALLOC0_GET(reg_val) \
(((reg_val)&SYSC_ALLOC_R_SYSC_ALLOC0_MASK) >> \
SYSC_ALLOC_R_SYSC_ALLOC0_SHIFT)
#define SYSC_ALLOC_R_SYSC_ALLOC0_SET(reg_val, value) \
(((reg_val) & ~SYSC_ALLOC_R_SYSC_ALLOC0_MASK) | \
(((value) << SYSC_ALLOC_R_SYSC_ALLOC0_SHIFT) & \
SYSC_ALLOC_R_SYSC_ALLOC0_MASK))
/* End of SYSC_ALLOC_R_SYSC_ALLOC0 values */
#define SYSC_ALLOC_W_SYSC_ALLOC0_SHIFT (4)
#define SYSC_ALLOC_W_SYSC_ALLOC0_MASK ((0xF) << SYSC_ALLOC_W_SYSC_ALLOC0_SHIFT)
#define SYSC_ALLOC_W_SYSC_ALLOC0_GET(reg_val) \
(((reg_val)&SYSC_ALLOC_W_SYSC_ALLOC0_MASK) >> \
SYSC_ALLOC_W_SYSC_ALLOC0_SHIFT)
#define SYSC_ALLOC_W_SYSC_ALLOC0_SET(reg_val, value) \
(((reg_val) & ~SYSC_ALLOC_W_SYSC_ALLOC0_MASK) | \
(((value) << SYSC_ALLOC_W_SYSC_ALLOC0_SHIFT) & \
SYSC_ALLOC_W_SYSC_ALLOC0_MASK))
/* End of SYSC_ALLOC_W_SYSC_ALLOC0 values */
#define SYSC_ALLOC_R_SYSC_ALLOC1_SHIFT (8)
#define SYSC_ALLOC_R_SYSC_ALLOC1_MASK ((0xF) << SYSC_ALLOC_R_SYSC_ALLOC1_SHIFT)
#define SYSC_ALLOC_R_SYSC_ALLOC1_GET(reg_val) \
(((reg_val)&SYSC_ALLOC_R_SYSC_ALLOC1_MASK) >> \
SYSC_ALLOC_R_SYSC_ALLOC1_SHIFT)
#define SYSC_ALLOC_R_SYSC_ALLOC1_SET(reg_val, value) \
(((reg_val) & ~SYSC_ALLOC_R_SYSC_ALLOC1_MASK) | \
(((value) << SYSC_ALLOC_R_SYSC_ALLOC1_SHIFT) & \
SYSC_ALLOC_R_SYSC_ALLOC1_MASK))
/* End of SYSC_ALLOC_R_SYSC_ALLOC1 values */
#define SYSC_ALLOC_W_SYSC_ALLOC1_SHIFT (12)
#define SYSC_ALLOC_W_SYSC_ALLOC1_MASK ((0xF) << SYSC_ALLOC_W_SYSC_ALLOC1_SHIFT)
#define SYSC_ALLOC_W_SYSC_ALLOC1_GET(reg_val) \
(((reg_val)&SYSC_ALLOC_W_SYSC_ALLOC1_MASK) >> \
SYSC_ALLOC_W_SYSC_ALLOC1_SHIFT)
#define SYSC_ALLOC_W_SYSC_ALLOC1_SET(reg_val, value) \
(((reg_val) & ~SYSC_ALLOC_W_SYSC_ALLOC1_MASK) | \
(((value) << SYSC_ALLOC_W_SYSC_ALLOC1_SHIFT) & \
SYSC_ALLOC_W_SYSC_ALLOC1_MASK))
/* End of SYSC_ALLOC_W_SYSC_ALLOC1 values */
#define SYSC_ALLOC_R_SYSC_ALLOC2_SHIFT (16)
#define SYSC_ALLOC_R_SYSC_ALLOC2_MASK ((0xF) << SYSC_ALLOC_R_SYSC_ALLOC2_SHIFT)
#define SYSC_ALLOC_R_SYSC_ALLOC2_GET(reg_val) \
(((reg_val)&SYSC_ALLOC_R_SYSC_ALLOC2_MASK) >> \
SYSC_ALLOC_R_SYSC_ALLOC2_SHIFT)
#define SYSC_ALLOC_R_SYSC_ALLOC2_SET(reg_val, value) \
(((reg_val) & ~SYSC_ALLOC_R_SYSC_ALLOC2_MASK) | \
(((value) << SYSC_ALLOC_R_SYSC_ALLOC2_SHIFT) & \
SYSC_ALLOC_R_SYSC_ALLOC2_MASK))
/* End of SYSC_ALLOC_R_SYSC_ALLOC2 values */
#define SYSC_ALLOC_W_SYSC_ALLOC2_SHIFT (20)
#define SYSC_ALLOC_W_SYSC_ALLOC2_MASK ((0xF) << SYSC_ALLOC_W_SYSC_ALLOC2_SHIFT)
#define SYSC_ALLOC_W_SYSC_ALLOC2_GET(reg_val) \
(((reg_val)&SYSC_ALLOC_W_SYSC_ALLOC2_MASK) >> \
SYSC_ALLOC_W_SYSC_ALLOC2_SHIFT)
#define SYSC_ALLOC_W_SYSC_ALLOC2_SET(reg_val, value) \
(((reg_val) & ~SYSC_ALLOC_W_SYSC_ALLOC2_MASK) | \
(((value) << SYSC_ALLOC_W_SYSC_ALLOC2_SHIFT) & \
SYSC_ALLOC_W_SYSC_ALLOC2_MASK))
/* End of SYSC_ALLOC_W_SYSC_ALLOC2 values */
#define SYSC_ALLOC_R_SYSC_ALLOC3_SHIFT (24)
#define SYSC_ALLOC_R_SYSC_ALLOC3_MASK ((0xF) << SYSC_ALLOC_R_SYSC_ALLOC3_SHIFT)
#define SYSC_ALLOC_R_SYSC_ALLOC3_GET(reg_val) \
(((reg_val)&SYSC_ALLOC_R_SYSC_ALLOC3_MASK) >> \
SYSC_ALLOC_R_SYSC_ALLOC3_SHIFT)
#define SYSC_ALLOC_R_SYSC_ALLOC3_SET(reg_val, value) \
(((reg_val) & ~SYSC_ALLOC_R_SYSC_ALLOC3_MASK) | \
(((value) << SYSC_ALLOC_R_SYSC_ALLOC3_SHIFT) & \
SYSC_ALLOC_R_SYSC_ALLOC3_MASK))
/* End of SYSC_ALLOC_R_SYSC_ALLOC3 values */
#define SYSC_ALLOC_W_SYSC_ALLOC3_SHIFT (28)
#define SYSC_ALLOC_W_SYSC_ALLOC3_MASK ((0xF) << SYSC_ALLOC_W_SYSC_ALLOC3_SHIFT)
#define SYSC_ALLOC_W_SYSC_ALLOC3_GET(reg_val) \
(((reg_val)&SYSC_ALLOC_W_SYSC_ALLOC3_MASK) >> \
SYSC_ALLOC_W_SYSC_ALLOC3_SHIFT)
#define SYSC_ALLOC_W_SYSC_ALLOC3_SET(reg_val, value) \
(((reg_val) & ~SYSC_ALLOC_W_SYSC_ALLOC3_MASK) | \
(((value) << SYSC_ALLOC_W_SYSC_ALLOC3_SHIFT) & \
SYSC_ALLOC_W_SYSC_ALLOC3_MASK))
/* End of SYSC_ALLOC_W_SYSC_ALLOC3 values */
#endif /* _UAPI_KBASE_GPU_REGMAP_H_ */

32
include/uapi/gpu/arm/bifrost/jm/mali_base_jm_kernel.h
View File

@@ -1,7 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
/*
*
* (C) COPYRIGHT 2019-2021 ARM Limited. All rights reserved.
* (C) COPYRIGHT 2019-2022 ARM Limited. All rights reserved.
*
* This program is free software and is provided to you under the terms of the
* GNU General Public License version 2 as published by the Free Software
@@ -68,6 +68,8 @@
*/
#define BASEP_MEM_NO_USER_FREE ((base_mem_alloc_flags)1 << 7)
/* Used as BASE_MEM_FIXED in other backends
*/
#define BASE_MEM_RESERVED_BIT_8 ((base_mem_alloc_flags)1 << 8)
/* Grow backing store on GPU Page Fault
@@ -116,15 +118,15 @@
#define BASE_MEM_IMPORT_SHARED ((base_mem_alloc_flags)1 << 18)
/**
* Bit 19 is reserved.
* BASE_MEM_RESERVED_BIT_19 - Bit 19 is reserved.
*
* Do not remove, use the next unreserved bit for new flags
*/
#define BASE_MEM_RESERVED_BIT_19 ((base_mem_alloc_flags)1 << 19)
/**
* Memory starting from the end of the initial commit is aligned to 'extension'
* pages, where 'extension' must be a power of 2 and no more than
* BASE_MEM_TILER_ALIGN_TOP - Memory starting from the end of the initial commit is aligned
* to 'extension' pages, where 'extension' must be a power of 2 and no more than
* BASE_MEM_TILER_ALIGN_TOP_EXTENSION_MAX_PAGES
*/
#define BASE_MEM_TILER_ALIGN_TOP ((base_mem_alloc_flags)1 << 20)
@@ -209,13 +211,14 @@
#define BASE_JIT_ALLOC_MEM_TILER_ALIGN_TOP (1 << 0)
/**
* If set, the heap info address points to a __u32 holding the used size in bytes;
* BASE_JIT_ALLOC_HEAP_INFO_IS_SIZE - If set, the heap info address points
* to a __u32 holding the used size in bytes;
* otherwise it points to a __u64 holding the lowest address of unused memory.
*/
#define BASE_JIT_ALLOC_HEAP_INFO_IS_SIZE (1 << 1)
/**
* Valid set of just-in-time memory allocation flags
* BASE_JIT_ALLOC_VALID_FLAGS - Valid set of just-in-time memory allocation flags
*
* Note: BASE_JIT_ALLOC_HEAP_INFO_IS_SIZE cannot be set if heap_info_gpu_addr
* in %base_jit_alloc_info is 0 (atom with BASE_JIT_ALLOC_HEAP_INFO_IS_SIZE set
@@ -314,12 +317,12 @@ typedef __u32 base_context_create_flags;
/**
* struct base_jd_udata - Per-job data
*
* @blob: per-job data array
*
* This structure is used to store per-job data, and is completely unused
* by the Base driver. It can be used to store things such as callback
* function pointer, data to handle job completion. It is guaranteed to be
* untouched by the Base driver.
*
* @blob: per-job data array
*/
struct base_jd_udata {
__u64 blob[2];
@@ -611,7 +614,8 @@ typedef __u32 base_jd_core_req;
BASE_JD_REQ_V | BASE_JD_REQ_SOFT_JOB | BASE_JD_REQ_ONLY_COMPUTE)
/**
* Mask of all bits in base_jd_core_req that control the type of a soft job.
* BASE_JD_REQ_SOFT_JOB_TYPE - Mask of all bits in base_jd_core_req that
* controls the type of a soft job.
*/
#define BASE_JD_REQ_SOFT_JOB_TYPE (BASE_JD_REQ_SOFT_JOB | 0x1f)
@@ -623,7 +627,7 @@ typedef __u32 base_jd_core_req;
((core_req) & BASE_JD_REQ_ATOM_TYPE) == BASE_JD_REQ_DEP)
/**
* enum kbase_jd_atom_state
* enum kbase_jd_atom_state - Atom states
*
* @KBASE_JD_ATOM_STATE_UNUSED: Atom is not used.
* @KBASE_JD_ATOM_STATE_QUEUED: Atom is queued in JD.
@@ -648,7 +652,7 @@ enum kbase_jd_atom_state {
typedef __u8 base_atom_id;
/**
* struct base_dependency -
* struct base_dependency - base dependency
*
* @atom_id: An atom number
* @dependency_type: Dependency type
@@ -1153,8 +1157,9 @@ enum base_jd_event_code {
/**
* struct base_jd_event_v2 - Event reporting structure
*
* @event_code: event code.
* @event_code: event code of type @ref base_jd_event_code.
* @atom_number: the atom number that has completed.
* @padding: padding.
* @udata: user data.
*
* This structure is used by the kernel driver to report information
@@ -1165,8 +1170,9 @@ enum base_jd_event_code {
* by ANDing with BASE_JD_SW_EVENT_TYPE_MASK.
*/
struct base_jd_event_v2 {
enum base_jd_event_code event_code;
__u32 event_code;
base_atom_id atom_number;
__u8 padding[3];
struct base_jd_udata udata;
};

6
include/uapi/gpu/arm/bifrost/jm/mali_kbase_jm_ioctl.h
View File

@@ -1,7 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
/*
*
* (C) COPYRIGHT 2020-2021 ARM Limited. All rights reserved.
* (C) COPYRIGHT 2020-2022 ARM Limited. All rights reserved.
*
* This program is free software and is provided to you under the terms of the
* GNU General Public License version 2 as published by the Free Software
@@ -123,9 +123,11 @@
* - Added new HW performance counters interface to all GPUs.
* 11.33:
* - Removed Kernel legacy HWC interface
* 11.34:
* - First release of new HW performance counters interface.
*/
#define BASE_UK_VERSION_MAJOR 11
#define BASE_UK_VERSION_MINOR 33
#define BASE_UK_VERSION_MINOR 34
/**
* struct kbase_ioctl_version_check - Check version compatibility between

80
include/uapi/gpu/arm/bifrost/mali_base_kernel.h
View File

@@ -1,7 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
/*
*
* (C) COPYRIGHT 2010-2021 ARM Limited. All rights reserved.
* (C) COPYRIGHT 2010-2022 ARM Limited. All rights reserved.
*
* This program is free software and is provided to you under the terms of the
* GNU General Public License version 2 as published by the Free Software
@@ -150,7 +150,7 @@ struct base_mem_import_user_buffer {
#define BASE_MEM_TILER_ALIGN_TOP_EXTENSION_MAX_PAGES \
(1ull << (BASE_MEM_TILER_ALIGN_TOP_EXTENSION_MAX_PAGES_LOG2))
/* Bit mask of cookies used for for memory allocation setup */
/* Bit mask of cookies used for memory allocation setup */
#define KBASE_COOKIE_MASK ~1UL /* bit 0 is reserved */
/* Maximum size allowed in a single KBASE_IOCTL_MEM_ALLOC call */
@@ -173,6 +173,12 @@ struct base_fence {
/**
* struct base_mem_aliasing_info - Memory aliasing info
*
* @handle: Handle to alias, can be BASE_MEM_WRITE_ALLOC_PAGES_HANDLE
* @offset: Offset within the handle to start aliasing from, in pages.
* Not used with BASE_MEM_WRITE_ALLOC_PAGES_HANDLE.
* @length: Length to alias, in pages. For BASE_MEM_WRITE_ALLOC_PAGES_HANDLE
* specifies the number of times the special page is needed.
*
* Describes a memory handle to be aliased.
* A subset of the handle can be chosen for aliasing, given an offset and a
* length.
@@ -184,12 +190,6 @@ struct base_fence {
* Offset and length are specified in pages.
* Offset must be within the size of the handle.
* Offset+length must not overrun the size of the handle.
*
* @handle: Handle to alias, can be BASE_MEM_WRITE_ALLOC_PAGES_HANDLE
* @offset: Offset within the handle to start aliasing from, in pages.
* Not used with BASE_MEM_WRITE_ALLOC_PAGES_HANDLE.
* @length: Length to alias, in pages. For BASE_MEM_WRITE_ALLOC_PAGES_HANDLE
* specifies the number of times the special page is needed.
*/
struct base_mem_aliasing_info {
struct base_mem_handle handle;
@@ -320,10 +320,9 @@ struct base_external_resource {
__u64 ext_resource;
};
/**
* The maximum number of external resources which can be mapped/unmapped
* in a single request.
* BASE_EXT_RES_COUNT_MAX - The maximum number of external resources
* which can be mapped/unmapped in a single request.
*/
#define BASE_EXT_RES_COUNT_MAX 10
@@ -348,7 +347,7 @@ struct base_jd_debug_copy_buffer {
#define GPU_MAX_JOB_SLOTS 16
/**
* User-side Base GPU Property Queries
* DOC: User-side Base GPU Property Queries
*
* The User-side Base GPU Property Query interface encapsulates two
* sub-modules:
@@ -459,36 +458,34 @@ struct base_jd_debug_copy_buffer {
* 16 coherent groups, since core groups are typically 4 cores.
*/
#define BASE_GPU_NUM_TEXTURE_FEATURES_REGISTERS 4
#define BASE_MAX_COHERENT_GROUPS 16
/**
* struct mali_base_gpu_core_props - GPU core props info
*
* @product_id: Pro specific value.
* @version_status: Status of the GPU release. No defined values, but starts at
* 0 and increases by one for each release status (alpha, beta, EAC, etc.).
* 4 bit values (0-15).
* 0 and increases by one for each release status (alpha, beta, EAC, etc.).
* 4 bit values (0-15).
* @minor_revision: Minor release number of the GPU. "P" part of an "RnPn"
* release number.
* 8 bit values (0-255).
* release number.
* 8 bit values (0-255).
* @major_revision: Major release number of the GPU. "R" part of an "RnPn"
* release number.
* 4 bit values (0-15).
* release number.
* 4 bit values (0-15).
* @padding: padding to allign to 8-byte
* @gpu_freq_khz_max: The maximum GPU frequency. Reported to applications by
* clGetDeviceInfo()
* clGetDeviceInfo()
* @log2_program_counter_size: Size of the shader program counter, in bits.
* @texture_features: TEXTURE_FEATURES_x registers, as exposed by the GPU. This
* is a bitpattern where a set bit indicates that the format is supported.
* Before using a texture format, it is recommended that the corresponding
* bit be checked.
* is a bitpattern where a set bit indicates that the format is supported.
* Before using a texture format, it is recommended that the corresponding
* bit be checked.
* @gpu_available_memory_size: Theoretical maximum memory available to the GPU.
* It is unlikely that a client will be able to allocate all of this memory
* for their own purposes, but this at least provides an upper bound on the
* memory available to the GPU.
* This is required for OpenCL's clGetDeviceInfo() call when
* CL_DEVICE_GLOBAL_MEM_SIZE is requested, for OpenCL GPU devices. The
* client will not be expecting to allocate anywhere near this value.
* It is unlikely that a client will be able to allocate all of this memory
* for their own purposes, but this at least provides an upper bound on the
* memory available to the GPU.
* This is required for OpenCL's clGetDeviceInfo() call when
* CL_DEVICE_GLOBAL_MEM_SIZE is requested, for OpenCL GPU devices. The
* client will not be expecting to allocate anywhere near this value.
* @num_exec_engines: The number of execution engines.
*/
struct mali_base_gpu_core_props {
@@ -557,13 +554,13 @@ struct mali_base_gpu_thread_props {
* @padding: padding to allign to 8-byte
*
* \c core_mask exposes all cores in that coherent group, and \c num_cores
* provides a cached population-count for that mask.
* provides a cached population-count for that mask.
*
* @note Whilst all cores are exposed in the mask, not all may be available to
* the application, depending on the Kernel Power policy.
* the application, depending on the Kernel Power policy.
*
* @note if u64s must be 8-byte aligned, then this structure has 32-bits of
* wastage.
* wastage.
*/
struct mali_base_gpu_coherent_group {
__u64 core_mask;
@@ -575,14 +572,15 @@ struct mali_base_gpu_coherent_group {
* struct mali_base_gpu_coherent_group_info - Coherency group information
* @num_groups: Number of coherent groups in the GPU.
* @num_core_groups: Number of core groups (coherent or not) in the GPU.
* Equivalent to the number of L2 Caches.
* The GPU Counter dumping writes 2048 bytes per core group, regardless
* of whether the core groups are coherent or not. Hence this member is
* needed to calculate how much memory is required for dumping.
* @note Do not use it to work out how many valid elements are in the
* group[] member. Use num_groups instead.
* Equivalent to the number of L2 Caches.
* The GPU Counter dumping writes 2048 bytes per core group,
* regardless of whether the core groups are coherent or not.
* Hence this member is needed to calculate how much memory
* is required for dumping.
* @note Do not use it to work out how many valid elements
* are in the group[] member. Use num_groups instead.
* @coherency: Coherency features of the memory, accessed by gpu_mem_features
* methods
* methods
* @padding: padding to allign to 8-byte
* @group: Descriptors of coherent groups
*

35
include/uapi/gpu/arm/bifrost/mali_kbase_hwcnt_reader.h
View File

@@ -1,7 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
/*
*
* (C) COPYRIGHT 2015, 2020-2021 ARM Limited. All rights reserved.
* (C) COPYRIGHT 2015, 2020-2022 ARM Limited. All rights reserved.
*
* This program is free software and is provided to you under the terms of the
* GNU General Public License version 2 as published by the Free Software
@@ -22,7 +22,7 @@
#ifndef _UAPI_KBASE_HWCNT_READER_H_
#define _UAPI_KBASE_HWCNT_READER_H_
#include <stddef.h>
#include <linux/stddef.h>
#include <linux/types.h>
/* The ids of ioctl commands. */
@@ -118,11 +118,12 @@ enum prfcnt_list_type {
};
#define FLEX_LIST_TYPE(type, subtype) \
(__u16)(((type & 0xf) << 12) | (subtype & 0xfff))
((__u16)(((type & 0xf) << 12) | (subtype & 0xfff)))
#define FLEX_LIST_TYPE_NONE FLEX_LIST_TYPE(0, 0)
#define PRFCNT_ENUM_TYPE_BLOCK FLEX_LIST_TYPE(PRFCNT_LIST_TYPE_ENUM, 0)
#define PRFCNT_ENUM_TYPE_REQUEST FLEX_LIST_TYPE(PRFCNT_LIST_TYPE_ENUM, 1)
#define PRFCNT_ENUM_TYPE_SAMPLE_INFO FLEX_LIST_TYPE(PRFCNT_LIST_TYPE_ENUM, 2)
#define PRFCNT_REQUEST_TYPE_MODE FLEX_LIST_TYPE(PRFCNT_LIST_TYPE_REQUEST, 0)
#define PRFCNT_REQUEST_TYPE_ENABLE FLEX_LIST_TYPE(PRFCNT_LIST_TYPE_REQUEST, 1)
@@ -183,8 +184,9 @@ enum prfcnt_set {
* @num_instances: How many instances of this block type exist in the hardware.
* @num_values: How many entries in the values array there are for samples
* from this block.
* @counter_mask: Bitmask that indicates the availability of counters in this
* block.
* @counter_mask: Bitmask that indicates counter availability in this block.
* A '0' indicates that a counter is not available at that
* index and will always return zeroes if requested.
*/
struct prfcnt_enum_block_counter {
__u8 block_type;
@@ -207,12 +209,23 @@ struct prfcnt_enum_request {
__u32 versions_mask;
};
/**
* struct prfcnt_enum_sample_info - Sample information descriptor.
* @num_clock_domains: Number of clock domains of the GPU.
* @pad: Padding bytes.
*/
struct prfcnt_enum_sample_info {
__u32 num_clock_domains;
__u32 pad;
};
/**
* struct prfcnt_enum_item - Performance counter enumeration item.
* @hdr: Header describing the type of item in the list.
* @u: Structure containing discriptor for enumeration item type.
* @u.block_counter: Performance counter block descriptor.
* @u.request: Request descriptor.
* @u.sample_info: Performance counter sample information descriptor.
*/
struct prfcnt_enum_item {
struct prfcnt_item_header hdr;
@@ -220,6 +233,7 @@ struct prfcnt_enum_item {
union {
struct prfcnt_enum_block_counter block_counter;
struct prfcnt_enum_request request;
struct prfcnt_enum_sample_info sample_info;
} u;
};
@@ -237,11 +251,11 @@ enum prfcnt_mode {
/**
* struct prfcnt_request_mode - Mode request descriptor.
* @mode: Capture mode for the session, either manual or periodic.
* @pad: Padding bytes.
* @mode_config: Structure containing configuration for periodic mode.
* @mode_config.period: Periodic config.
* @mode_config.period.period_ns: Period in nanoseconds, for periodic mode.
* @mode: Capture mode for the session, either manual or periodic.
* @pad: Padding bytes.
* @mode_config: Structure containing configuration for periodic mode.
* @mode_config.periodic: Periodic config.
* @mode_config.periodic.period_ns: Period in nanoseconds, for periodic mode.
*/
struct prfcnt_request_mode {
__u8 mode;
@@ -481,4 +495,3 @@ struct prfcnt_sample_access {
_IOW(KBASE_KINSTR_PRFCNT_READER, 0x10, struct prfcnt_sample_access)
#endif /* _UAPI_KBASE_HWCNT_READER_H_ */

4
include/uapi/gpu/arm/bifrost/mali_kbase_ioctl.h
View File

@@ -1,7 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
/*
*
* (C) COPYRIGHT 2017-2021 ARM Limited. All rights reserved.
* (C) COPYRIGHT 2017-2022 ARM Limited. All rights reserved.
*
* This program is free software and is provided to you under the terms of the
* GNU General Public License version 2 as published by the Free Software
@@ -515,7 +515,7 @@ struct kbase_ioctl_sticky_resource_map {
_IOW(KBASE_IOCTL_TYPE, 29, struct kbase_ioctl_sticky_resource_map)
/**
* struct kbase_ioctl_sticky_resource_map - Unmap a resource mapped which was
* struct kbase_ioctl_sticky_resource_unmap - Unmap a resource mapped which was
* previously permanently mapped
* @count: Number of resources
* @address: Array of __u64 GPU addresses of the external resources to unmap

6
include/uapi/gpu/arm/bifrost/mali_uk.h
View File

@@ -1,7 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
/*
*
* (C) COPYRIGHT 2010, 2012-2015, 2018, 2020-2021 ARM Limited. All rights reserved.
* (C) COPYRIGHT 2010, 2012-2015, 2018, 2020-2022 ARM Limited. All rights reserved.
*
* This program is free software and is provided to you under the terms of the
* GNU General Public License version 2 as published by the Free Software
@@ -20,8 +20,8 @@
*/
/**
* Types and definitions that are common across OSs for both the user
* and kernel side of the User-Kernel interface.
* DOC: Types and definitions that are common across OSs for both the user
* and kernel side of the User-Kernel interface.
*/
#ifndef _UAPI_UK_H_