From 64889d8edbc527088d53fef9db46afdcf8f53477 Mon Sep 17 00:00:00 2001 From: Joy Cho Date: Mon, 28 Jan 2019 15:50:39 +0900 Subject: [PATCH] hdmitx: custombuilt: consider hdmi pll output under 1GHz Change-Id: I3730ad2d4c9e914c28f8d2e57da93561a72abe47 --- .../media/vout/hdmitx/hdmi_tx_20/hw/hw_clk.c | 20 ++++++++++++++----- 1 file changed, 15 insertions(+), 5 deletions(-) diff --git a/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hw_clk.c b/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hw_clk.c index 7ba3558e0dc5..05af3ba30a42 100644 --- a/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hw_clk.c +++ b/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hw_clk.c @@ -1039,13 +1039,23 @@ static void hdmitx_set_clk_(struct hdmitx_dev *hdev) next: /* FIXME : consider pixel clocks over 200MHz */ if (vic == HDMI_CUSTOMBUILT) { - pr_info("[n2][%s] vic == HDMI_CUSTOMBUILT\n", __func__); custom_timing = get_custom_timing(); p_enc[j].hpll_clk_out = (custom_timing->frac_freq * 10); - /* control od dividers */ - p_enc[j].od1 = 1; - p_enc[j].od2 = 1; - p_enc[j].od3 = 2; + pr_info("[N2][%s] vic == HDMI_CUSTOMBUILT, frac_freq %d\n", + __func__, custom_timing->frac_freq); + /* check if hpll clk output is under (100*10)MHz */ + if (p_enc[j].hpll_clk_out < 1000000) { + p_enc[j].hpll_clk_out *= 4; + /* control od dividers */ + p_enc[j].od1 = 4; + p_enc[j].od2 = 1; + p_enc[j].od3 = 2; + } else { + /* control od dividers */ + p_enc[j].od1 = 1; + p_enc[j].od2 = 1; + p_enc[j].od3 = 2; + } } hdmitx_set_cts_sys_clk(hdev);