From 64d0859286467b59463daa27da173622098bd390 Mon Sep 17 00:00:00 2001 From: Andy Yan Date: Mon, 9 Nov 2020 16:53:16 +0800 Subject: [PATCH] drm/rockchip: vop2: Fix mipi pin/dclk polarity register defination Change-Id: Id674f00590e3f257b82620fb517d215fb56402f4 Signed-off-by: Andy Yan --- drivers/gpu/drm/rockchip/rockchip_vop2_reg.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/rockchip/rockchip_vop2_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop2_reg.c index 0c82d08c3296..69b128fe288e 100644 --- a/drivers/gpu/drm/rockchip/rockchip_vop2_reg.c +++ b/drivers/gpu/drm/rockchip/rockchip_vop2_reg.c @@ -888,8 +888,8 @@ static const struct vop2_ctrl rk3568_vop_ctrl = { .hdmi_dclk_pol = VOP_REG(RK3568_DSP_IF_POL, 0x1, 7), .edp_pin_pol = VOP_REG(RK3568_DSP_IF_POL, 0x3, 12), .edp_dclk_pol = VOP_REG(RK3568_DSP_IF_POL, 0x1, 15), - .mipi_dclk_pol = VOP_REG(RK3568_DSP_IF_POL, 0x7, 16), - .mipi_pin_pol = VOP_REG(RK3568_DSP_IF_POL, 0x1, 19), + .mipi_pin_pol = VOP_REG(RK3568_DSP_IF_POL, 0x7, 16), + .mipi_dclk_pol = VOP_REG(RK3568_DSP_IF_POL, 0x1, 19), .win_vp_id[0] = VOP_REG(RK3568_OVL_PORT_SEL, 0x3, 16), .win_vp_id[1] = VOP_REG(RK3568_OVL_PORT_SEL, 0x3, 18), .win_vp_id[2] = VOP_REG(RK3568_OVL_PORT_SEL, 0x3, 24),