mirror of
https://github.com/hardkernel/linux.git
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Merge tag 'sunxi-dt-for-3.12-2' of https://github.com/mripard/linux into next/dt
Allwinner sunXi DT additions for 3.12, take 2 These patches add basic support for: - Allwinner A31 and A20 SoCs - The Olimex A20-Olinuxino board - The Olimex A10s-Olinuxino board * tag 'sunxi-dt-for-3.12-2' of https://github.com/mripard/linux: ARM: sun7i: Add Olimex A20-Olinuxino-Micro support ARM: sun7i: Add Allwinner A20 DTSI ARM: sun6i: Add WITS Colombus A31 evaluation kit support ARM: sunxi: Add Allwinner A31 DTSI
This commit is contained in:
Kevin Hilman
@@ -213,7 +213,9 @@ dtb-$(CONFIG_ARCH_SUNXI) += \
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sun4i-a10-mini-xplus.dtb \
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sun4i-a10-hackberry.dtb \
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sun5i-a10s-olinuxino-micro.dtb \
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sun5i-a13-olinuxino.dtb
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sun5i-a13-olinuxino.dtb \
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sun6i-a31-colombus.dtb \
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sun7i-a20-olinuxino-micro.dtb
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dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \
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tegra20-iris-512.dtb \
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tegra20-medcom-wide.dtb \
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30
arch/arm/boot/dts/sun6i-a31-colombus.dts
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30
arch/arm/boot/dts/sun6i-a31-colombus.dts
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@@ -0,0 +1,30 @@
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/*
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* Copyright 2013 Maxime Ripard
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*
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* Maxime Ripard <maxime.ripard@free-electrons.com>
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*
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* The code contained herein is licensed under the GNU General Public
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* License. You may obtain a copy of the GNU General Public License
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* Version 2 or later at the following locations:
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*
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* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*/
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/dts-v1/;
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/include/ "sun6i-a31.dtsi"
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/ {
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model = "WITS A31 Colombus Evaluation Board";
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compatible = "wits,colombus", "allwinner,sun6i-a31";
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chosen {
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bootargs = "earlyprintk console=ttyS0,115200";
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};
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soc@01c00000 {
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uart0: serial@01c28000 {
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status = "okay";
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};
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};
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};
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156
arch/arm/boot/dts/sun6i-a31.dtsi
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156
arch/arm/boot/dts/sun6i-a31.dtsi
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@@ -0,0 +1,156 @@
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/*
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* Copyright 2013 Maxime Ripard
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*
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* Maxime Ripard <maxime.ripard@free-electrons.com>
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*
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* The code contained herein is licensed under the GNU General Public
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* License. You may obtain a copy of the GNU General Public License
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* Version 2 or later at the following locations:
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*
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* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*/
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/include/ "skeleton.dtsi"
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/ {
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interrupt-parent = <&gic>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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compatible = "arm,cortex-a7";
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device_type = "cpu";
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reg = <0>;
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};
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cpu@1 {
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compatible = "arm,cortex-a7";
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device_type = "cpu";
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reg = <1>;
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};
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cpu@2 {
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compatible = "arm,cortex-a7";
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device_type = "cpu";
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reg = <2>;
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};
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cpu@3 {
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compatible = "arm,cortex-a7";
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device_type = "cpu";
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reg = <3>;
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};
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};
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memory {
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reg = <0x40000000 0x80000000>;
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};
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clocks {
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#address-cells = <1>;
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#size-cells = <0>;
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osc: oscillator {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <24000000>;
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};
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};
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soc@01c00000 {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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timer@01c20c00 {
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compatible = "allwinner,sun4i-timer";
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reg = <0x01c20c00 0xa0>;
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interrupts = <0 18 1>,
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<0 19 1>,
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<0 20 1>,
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<0 21 1>,
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<0 22 1>;
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clocks = <&osc>;
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};
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wdt1: watchdog@01c20ca0 {
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compatible = "allwinner,sun6i-wdt";
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reg = <0x01c20ca0 0x20>;
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};
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uart0: serial@01c28000 {
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compatible = "snps,dw-apb-uart";
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reg = <0x01c28000 0x400>;
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interrupts = <0 0 1>;
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reg-shift = <2>;
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reg-io-width = <4>;
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clocks = <&osc>;
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status = "disabled";
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};
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uart1: serial@01c28400 {
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compatible = "snps,dw-apb-uart";
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reg = <0x01c28400 0x400>;
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interrupts = <0 1 1>;
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reg-shift = <2>;
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reg-io-width = <4>;
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clocks = <&osc>;
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status = "disabled";
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};
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uart2: serial@01c28800 {
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compatible = "snps,dw-apb-uart";
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reg = <0x01c28800 0x400>;
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interrupts = <0 2 1>;
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reg-shift = <2>;
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reg-io-width = <4>;
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clocks = <&osc>;
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status = "disabled";
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};
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uart3: serial@01c28c00 {
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compatible = "snps,dw-apb-uart";
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reg = <0x01c28c00 0x400>;
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interrupts = <0 3 1>;
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reg-shift = <2>;
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reg-io-width = <4>;
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clocks = <&osc>;
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status = "disabled";
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};
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uart4: serial@01c29000 {
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compatible = "snps,dw-apb-uart";
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reg = <0x01c29000 0x400>;
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interrupts = <0 4 1>;
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reg-shift = <2>;
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reg-io-width = <4>;
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clocks = <&osc>;
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status = "disabled";
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};
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uart5: serial@01c29400 {
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compatible = "snps,dw-apb-uart";
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reg = <0x01c29400 0x400>;
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interrupts = <0 5 1>;
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reg-shift = <2>;
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reg-io-width = <4>;
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clocks = <&osc>;
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status = "disabled";
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};
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gic: interrupt-controller@01c81000 {
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compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
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reg = <0x01c81000 0x1000>,
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<0x01c82000 0x1000>,
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<0x01c84000 0x2000>,
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<0x01c86000 0x2000>;
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interrupt-controller;
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#interrupt-cells = <3>;
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interrupts = <1 9 0xf04>;
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};
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};
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};
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34
arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts
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34
arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts
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@@ -0,0 +1,34 @@
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/*
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* Copyright 2013 Maxime Ripard
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*
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* Maxime Ripard <maxime.ripard@free-electrons.com>
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*
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* The code contained herein is licensed under the GNU General Public
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* License. You may obtain a copy of the GNU General Public License
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* Version 2 or later at the following locations:
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*
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* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*/
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/dts-v1/;
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/include/ "sun7i-a20.dtsi"
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/ {
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model = "Olimex A20-Olinuxino Micro";
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compatible = "olimex,a20-olinuxino-micro", "allwinner,sun7i-a20";
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soc@01c00000 {
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uart0: serial@01c28000 {
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status = "okay";
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};
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uart6: serial@01c29800 {
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status = "okay";
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};
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uart7: serial@01c29c00 {
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status = "okay";
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};
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};
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};
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172
arch/arm/boot/dts/sun7i-a20.dtsi
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172
arch/arm/boot/dts/sun7i-a20.dtsi
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@@ -0,0 +1,172 @@
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/*
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* Copyright 2013 Maxime Ripard
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*
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* Maxime Ripard <maxime.ripard@free-electrons.com>
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*
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* The code contained herein is licensed under the GNU General Public
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* License. You may obtain a copy of the GNU General Public License
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* Version 2 or later at the following locations:
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*
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* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*/
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/include/ "skeleton.dtsi"
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/ {
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interrupt-parent = <&gic>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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compatible = "arm,cortex-a7";
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device_type = "cpu";
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reg = <0>;
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};
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cpu@1 {
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compatible = "arm,cortex-a7";
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device_type = "cpu";
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reg = <1>;
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};
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};
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memory {
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reg = <0x40000000 0x80000000>;
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};
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clocks {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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osc24M: osc24M@01c20050 {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <24000000>;
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};
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osc32k: osc32k {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <32768>;
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};
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};
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soc@01c00000 {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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timer@01c20c00 {
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compatible = "allwinner,sun4i-timer";
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reg = <0x01c20c00 0x90>;
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interrupts = <0 22 1>,
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<0 23 1>,
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<0 24 1>,
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<0 25 1>,
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<0 67 1>,
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<0 68 1>;
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clocks = <&osc24M>;
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};
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wdt: watchdog@01c20c90 {
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compatible = "allwinner,sun4i-wdt";
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reg = <0x01c20c90 0x10>;
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};
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uart0: serial@01c28000 {
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compatible = "snps,dw-apb-uart";
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reg = <0x01c28000 0x400>;
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interrupts = <0 1 1>;
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reg-shift = <2>;
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reg-io-width = <4>;
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clocks = <&osc24M>;
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status = "disabled";
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};
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uart1: serial@01c28400 {
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compatible = "snps,dw-apb-uart";
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reg = <0x01c28400 0x400>;
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interrupts = <0 2 1>;
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reg-shift = <2>;
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reg-io-width = <4>;
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clocks = <&osc24M>;
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status = "disabled";
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};
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uart2: serial@01c28800 {
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compatible = "snps,dw-apb-uart";
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reg = <0x01c28800 0x400>;
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interrupts = <0 3 1>;
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reg-shift = <2>;
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reg-io-width = <4>;
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clocks = <&osc24M>;
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status = "disabled";
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};
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uart3: serial@01c28c00 {
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compatible = "snps,dw-apb-uart";
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reg = <0x01c28c00 0x400>;
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interrupts = <0 4 1>;
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reg-shift = <2>;
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reg-io-width = <4>;
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clocks = <&osc24M>;
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status = "disabled";
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};
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uart4: serial@01c29000 {
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compatible = "snps,dw-apb-uart";
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reg = <0x01c29000 0x400>;
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interrupts = <0 17 1>;
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reg-shift = <2>;
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reg-io-width = <4>;
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clocks = <&osc24M>;
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status = "disabled";
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};
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uart5: serial@01c29400 {
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compatible = "snps,dw-apb-uart";
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reg = <0x01c29400 0x400>;
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interrupts = <0 18 1>;
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reg-shift = <2>;
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reg-io-width = <4>;
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clocks = <&osc24M>;
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status = "disabled";
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};
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uart6: serial@01c29800 {
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compatible = "snps,dw-apb-uart";
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reg = <0x01c29800 0x400>;
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interrupts = <0 19 1>;
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reg-shift = <2>;
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reg-io-width = <4>;
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clocks = <&osc24M>;
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status = "disabled";
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};
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uart7: serial@01c29c00 {
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compatible = "snps,dw-apb-uart";
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reg = <0x01c29c00 0x400>;
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interrupts = <0 20 1>;
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reg-shift = <2>;
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reg-io-width = <4>;
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clocks = <&osc24M>;
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status = "disabled";
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};
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gic: interrupt-controller@01c81000 {
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compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
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reg = <0x01c81000 0x1000>,
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<0x01c82000 0x1000>,
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<0x01c84000 0x2000>,
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<0x01c86000 0x2000>;
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interrupt-controller;
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#interrupt-cells = <3>;
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interrupts = <1 9 0xf04>;
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};
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};
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};
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Reference in New Issue
Block a user