From 65ce8916b919e3e39b9abc208e6c7bdffb1625b6 Mon Sep 17 00:00:00 2001 From: Mark Yao Date: Fri, 20 Jan 2017 15:15:35 +0800 Subject: [PATCH] drm/rockchip: dw_hdmi: move vpll set rate to encoder enable Change-Id: I5cf7f32f15cf1ea3e85b69009615756be3809c5e Signed-off-by: Mark Yao --- drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 15 +++++---------- 1 file changed, 5 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c index cfd8b789700c..4967a8e3875e 100644 --- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c @@ -361,21 +361,17 @@ dw_hdmi_rockchip_encoder_mode_fixup(struct drm_encoder *encoder, return false; } -static void dw_hdmi_rockchip_encoder_mode_set(struct drm_encoder *encoder, - struct drm_display_mode *mode, - struct drm_display_mode *adj_mode) -{ - struct rockchip_hdmi *hdmi = to_rockchip_hdmi(encoder); - - clk_set_rate(hdmi->vpll_clk, adj_mode->clock * 1000); -} - static void dw_hdmi_rockchip_encoder_enable(struct drm_encoder *encoder) { struct rockchip_hdmi *hdmi = to_rockchip_hdmi(encoder); + struct drm_crtc *crtc = encoder->crtc; u32 val; int ret; + if (WARN_ON(!crtc || !crtc->state)) + return; + clk_set_rate(hdmi->vpll_clk, crtc->state->adjusted_mode.clock * 1000); + if (hdmi->chip_data->lcdsel_grf_reg < 0) return; @@ -415,7 +411,6 @@ dw_hdmi_rockchip_encoder_atomic_check(struct drm_encoder *encoder, static const struct drm_encoder_helper_funcs dw_hdmi_rockchip_encoder_helper_funcs = { .mode_fixup = dw_hdmi_rockchip_encoder_mode_fixup, - .mode_set = dw_hdmi_rockchip_encoder_mode_set, .enable = dw_hdmi_rockchip_encoder_enable, .disable = dw_hdmi_rockchip_encoder_disable, .atomic_check = dw_hdmi_rockchip_encoder_atomic_check,