From 67031fb1cc2ea097451289b6806226d14fefa1b7 Mon Sep 17 00:00:00 2001 From: Finley Xiao Date: Sat, 26 Mar 2022 17:10:49 +0800 Subject: [PATCH] arm64: dts: rockchip: rk3588s: Add leakage information Signed-off-by: Finley Xiao Change-Id: Icaa30bcda38461cb7fc69d83672e9ff8fe73abd3 --- arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 39 +++++++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi index 669ff52af05e..2704255b0ca2 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi @@ -570,6 +570,9 @@ compatible = "operating-points-v2"; opp-shared; + nvmem-cells = <&cpul_leakage>; + nvmem-cell-names = "leakage"; + rockchip,pvtm-voltage-sel = < 0 1410 0 1411 1434 1 @@ -699,6 +702,9 @@ compatible = "operating-points-v2"; opp-shared; + nvmem-cells = <&cpub0_leakage>; + nvmem-cell-names = "leakage"; + rockchip,pvtm-voltage-sel = < 0 1640 0 1641 1675 1 @@ -859,6 +865,9 @@ compatible = "operating-points-v2"; opp-shared; + nvmem-cells = <&cpub1_leakage>; + nvmem-cell-names = "leakage"; + rockchip,pvtm-voltage-sel = < 0 1640 0 1641 1675 1 @@ -1159,6 +1168,9 @@ dmc_opp_table: dmc-opp-table { compatible = "operating-points-v2"; + nvmem-cells = <&log_leakage>; + nvmem-cell-names = "leakage"; + opp-2750000000 { opp-hz = /bits/ 64 <2750000000>; opp-microvolt = <850000>; @@ -1509,6 +1521,9 @@ gpu_opp_table: gpu-opp-table { compatible = "operating-points-v2"; + nvmem-cells = <&gpu_leakage>; + nvmem-cell-names = "leakage"; + rockchip,pvtm-voltage-sel = < 0 830 0 831 855 1 @@ -2496,6 +2511,9 @@ npu_opp_table: npu-opp-table { compatible = "operating-points-v2"; + nvmem-cells = <&npu_leakage>; + nvmem-cell-names = "leakage"; + rockchip,pvtm-voltage-sel = < 0 840 0 841 865 1 @@ -5270,6 +5288,27 @@ reg = <0x1c 0x1>; bits = <3 3>; }; + cpub0_leakage: cpub0-leakage@17 { + reg = <0x17 0x1>; + }; + cpub1_leakage: cpub1-leakage@18 { + reg = <0x18 0x1>; + }; + cpul_leakage: cpul-leakage@19 { + reg = <0x19 0x1>; + }; + log_leakage: log-leakage@1a { + reg = <0x1a 0x1>; + }; + gpu_leakage: gpu-leakage@1b { + reg = <0x1b 0x1>; + }; + npu_leakage: npu-leakage@28 { + reg = <0x28 0x1>; + }; + codec_leakage: codec-leakage@29 { + reg = <0x29 0x1>; + }; }; mailbox2: mailbox@fece0000 {