From 02e897ae7ce5fa2c423d26448ce7a2bece32bf5d Mon Sep 17 00:00:00 2001 From: Steven Liu Date: Thu, 7 Sep 2023 19:58:29 +0800 Subject: [PATCH 1/6] arm64: dts: rockchip: rk3562-amp: support ap core for amp Signed-off-by: Steven Liu Change-Id: I5b70c643884ff236ab27a918d03fc278b9b1b377 --- arch/arm64/boot/dts/rockchip/rk3562-amp.dtsi | 22 ++++++++++++++----- .../rk3562-evb1-lp4x-v10-linux-amp.dts | 12 +++++++++- 2 files changed, 28 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3562-amp.dtsi b/arch/arm64/boot/dts/rockchip/rk3562-amp.dtsi index d0979a1b28a8..36c7febdf571 100644 --- a/arch/arm64/boot/dts/rockchip/rk3562-amp.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3562-amp.dtsi @@ -1,11 +1,13 @@ // SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* - * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * Copyright (c) 2023 Rockchip Electronics Co., Ltd. */ +#include + / { rockchip_amp: rockchip-amp { - compatible = "rockchip,mcu-amp"; + compatible = "rockchip,amp"; clocks = <&cru FCLK_BUS_CM0_CORE>, <&cru CLK_BUS_CM0_RTC>, <&cru PCLK_MAILBOX>, <&cru PCLK_INTC>, <&cru SCLK_UART7>, <&cru PCLK_UART7>, @@ -14,6 +16,9 @@ pinctrl-names = "default"; pinctrl-0 = <&uart7m1_xfer>; + amp-cpu-aff-maskbits = <0x0 0x1 0x1 0x2 0x2 0x4 0x3 0x8>; + amp-irqs = ; + status = "okay"; }; @@ -34,9 +39,9 @@ #size-cells = <2>; ranges; - /* mcu address */ - mcu_reserved: mcu@8200000 { - reg = <0x0 0x8200000 0x0 0x100000>; + /* remote amp core address */ + amp_shmem_reserved: amp-shmem@7800000 { + reg = <0x0 0x7800000 0x0 0x400000>; no-map; }; @@ -50,6 +55,13 @@ reg = <0x0 0x08000000 0x0 0x100000>; no-map; }; + + /* mcu address */ + mcu_reserved: mcu@8200000 { + reg = <0x0 0x8200000 0x0 0x100000>; + no-map; + }; + }; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3562-evb1-lp4x-v10-linux-amp.dts b/arch/arm64/boot/dts/rockchip/rk3562-evb1-lp4x-v10-linux-amp.dts index a449f6a7edc9..d39eba9b3a96 100644 --- a/arch/arm64/boot/dts/rockchip/rk3562-evb1-lp4x-v10-linux-amp.dts +++ b/arch/arm64/boot/dts/rockchip/rk3562-evb1-lp4x-v10-linux-amp.dts @@ -12,7 +12,17 @@ / { memory { device_type = "memory"; - reg = <0x0 0x01000000 0x0 0x07400000>, + reg = <0x0 0x02000000 0x0 0x06400000>, <0x0 0x0a200000 0x0 0xf1e00000>; }; }; + +&arm_pmu { + interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>; +}; + +/delete-node/ &cpu3; + +&sdmmc0 { + status = "disabled"; +}; From 51da9567aa254c0c2ac9986197c2fd249d860500 Mon Sep 17 00:00:00 2001 From: Binyuan Lan Date: Mon, 21 Aug 2023 09:27:26 +0000 Subject: [PATCH 2/6] ASoC: rockchip: rk817-codec: always enable mclk Change-Id: Id2a87aaf665c8f1030b425e7e7fa4727401ac70b Signed-off-by: Binyuan Lan --- sound/soc/codecs/rk817_codec.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/sound/soc/codecs/rk817_codec.c b/sound/soc/codecs/rk817_codec.c index c178da3e52a2..ef065580c2af 100644 --- a/sound/soc/codecs/rk817_codec.c +++ b/sound/soc/codecs/rk817_codec.c @@ -1238,9 +1238,9 @@ static int rk817_probe(struct snd_soc_component *component) rk817->chip_ver = (chip_ver & 0x0f); dev_info(component->dev, "%s: chip_name:0x%x, chip_ver:0x%x\n", __func__, chip_name, chip_ver); + /* always enable mclk, and will disable mclk in rk817_remove */ clk_prepare_enable(rk817->mclk); rk817_reset(component); - clk_disable_unprepare(rk817->mclk); mutex_init(&rk817->clk_lock); rk817->clk_capture = 0; rk817->clk_playback = 0; @@ -1265,6 +1265,7 @@ static void rk817_remove(struct snd_soc_component *component) rk817_codec_power_down(component, RK817_CODEC_ALL); snd_soc_component_exit_regmap(component); mutex_destroy(&rk817->clk_lock); + clk_disable_unprepare(rk817->mclk); mdelay(10); } From 933f963be6ac22e37c279ef509fb80eafbd35d1f Mon Sep 17 00:00:00 2001 From: Zhang Yubing Date: Wed, 9 Nov 2022 20:39:37 +0800 Subject: [PATCH 3/6] dt-bindings: mfd: add rkx110_x120 document Signed-off-by: Zhang Yubing Signed-off-by: Andy Yan Signed-off-by: Cai Wenzhong Change-Id: I3bc8ec325b05b743ddc73e2f7a2786c3836dfce0 --- .../devicetree/bindings/mfd/rkx110_x120.yaml | 564 ++++++++++++++++++ include/dt-bindings/mfd/rockchip-serdes.h | 151 +++++ 2 files changed, 715 insertions(+) create mode 100644 Documentation/devicetree/bindings/mfd/rkx110_x120.yaml create mode 100644 include/dt-bindings/mfd/rockchip-serdes.h diff --git a/Documentation/devicetree/bindings/mfd/rkx110_x120.yaml b/Documentation/devicetree/bindings/mfd/rkx110_x120.yaml new file mode 100644 index 000000000000..8f00d4c2e1d5 --- /dev/null +++ b/Documentation/devicetree/bindings/mfd/rkx110_x120.yaml @@ -0,0 +1,564 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/rockchip/rockchip-vop.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip SerDes MFD driver + +description: + Rockchip SerDes MFD driver is a pair chip for long distance transmitting + display image. + +maintainers: + - Zhang Yubing + +properties: + compatible: + enum: + - "rockchip,rkx110", "rockchip,rkx120" + + interrupts: + maxItems: 1 + description: + The Serdes interrupt is shared by RKX110/RKX120. + + clocks: + items: + - description: + + clock-names: + items: + - const: + + resets: + maxItems: 1 + + reset-names: + items: + - const: + + route: + type: object + description: + A route node descriptor serdes topology + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - resets + - reset-names + - route + +additionalProperties: false + +# example0: +# 1 video source input, 1 channel, 1 lane, 1 remote, 1 video output: +# disp in can select follow interface: +# dsi0_rx, dsi1_rx, lvds0_rx, lvds1_rx, dual-lvds_rx, rgb_rx +# disp out can select follow interface: +# dsi_tx, lvds0_tx, lvds1_tx, dual-lvds_tx, rgb_tx ++-------+ +---------+ +---------+ +--------+ +| | disp in | | cable0 | | disp out| | +| soc |--------->| RK110 +----------->| RK120 +-------->| screen | +| | | | | | | | ++-------+ +---------+ +---------+ +--------+ + +examples0: + - | + #include + &i2c1 { + status = "okay"; + + rkx110_x120: rkx110_x120@55 { + compatible = "rockchip,rkx110"; + enable-gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_LOW>; + status = "okay"; + + remote0-addr = <0x35>; + + panel { + compatible = "rockchip,serdes_panel"; + status = "okay"; + + local-port0 = ; + remote0-port0 = ; + + backlight0 = <&backlight>; + power0-supply = <&vcc3v3_lcd_n>; + reset0-gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_LOW>; + reset0-delay-ms = <20>; + enable0-delay-ms = <20>; + prepare0-delay-ms = <20>; + unprepare0-delay-ms = <20>; + disable0-delay-ms = <20>; + bus-format0 = ; + + display-timings { + native-mode = <&timing0>; + + timing0: timing0 { + clock-frequency = <27000000>; + hactive = <1024>; + vactive = <600>; + hback-porch = <160>; + hfront-porch = <160>; + vback-porch = <20>; + vfront-porch = <15>; + hsync-len = <6>; + vsync-len = <5>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + }; + }; + }; + +# example1: +# 1 video source input, 2 channel, 1 lane, 1 remote, 1 video output: +# disp in can select follow interface: +# dsi0_rx, dsi1_rx, lvds0_rx, lvds1_rx, dual-lvds_rx, rgb_rx +# disp out can select follow interface: +# dsi_tx, lvds0_tx, lvds1_tx, dual-lvds_tx, rgb_tx ++-------+ +---------+ cable0 +---------+ +--------+ +| | disp in | +----------->| | disp out| | +| soc |--------->| RK110 | cable1 | RK120 +-------->| screen | +| | | +----------->| | | | ++-------+ +---------+ +---------+ +--------+ + +examples1: + - | + #include + &i2c1 { + status = "okay"; + + rkx110_x120: rkx110_x120@55 { + compatible = "rockchip,rkx110"; + enable-gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_LOW>; + status = "okay"; + + remote0-addr = <0x35>; + + panel { + compatible = "rockchip,serdes_panel"; + status = "okay"; + + local-port0 = ; + remote0-port0 = ; + num-lanes = <2>; + + backlight0 = <&backlight>; + power0-supply = <&vcc3v3_lcd_n>; + reset0-gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_LOW>; + reset0-delay-ms = <20>; + enable0-delay-ms = <20>; + prepare0-delay-ms = <20>; + unprepare0-delay-ms = <20>; + disable0-delay-ms = <20>; + bus-format0 = ; + + display-timings { + native-mode = <&timing0>; + + timing0: timing0 { + clock-frequency = <27000000>; + hactive = <1024>; + vactive = <600>; + hback-porch = <160>; + hfront-porch = <160>; + vback-porch = <20>; + vfront-porch = <15>; + hsync-len = <6>; + vsync-len = <5>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + }; + }; + }; + +# example2: +# 1 video source input, 2 channel, 2 lane, 2 remote, 2 video output: +# disp in can select follow interface: +# dsi0_rx, dsi1_rx, lvds0_rx, lvds1_rx, dual-lvds_rx, rgb_rx +# disp out can select follow interface: +# dsi_tx, lvds0_tx, lvds1_tx, dual-lvds_tx, rgb_tx + +---------+ +--------+ + cable0 | |disp0 out| | + +------->| RK120 +-------->| screen | + | | | | | ++-------+ +---------+ | +---------+ +--------+ +| | disp in | +---+ +| soc |--------->| RK110 | +| | | +---+ ++-------+ +---------+ | +---------+ +--------+ + |cable1 | |disp1 out| | + +------->| RK120 +-------->| screen | + | | | | + +---------+ +--------+ + +examples2: + - | + #include + &i2c1 { + status = "okay"; + + rkx110_x120: rkx110_x120@55 { + compatible = "rockchip,rkx110"; + enable-gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_LOW>; + status = "okay"; + + remote0-addr = <0x35>; + remote1-addr = <0x36>; + + panel { + compatible = "rockchip,serdes_panel"; + status = "okay"; + + local-port0 = ; + remote0-port0 = ; + remote1-port0 = ; + + backlight0 = <&backlight>; + power0-supply = <&vcc3v3_lcd_n>; + reset0-gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_LOW>; + reset0-delay-ms = <20>; + enable0-delay-ms = <20>; + prepare0-delay-ms = <20>; + unprepare0-delay-ms = <20>; + disable0-delay-ms = <20>; + bus-format0 = ; + + display-timings { + native-mode = <&timing0>; + + timing0: timing0 { + clock-frequency = <27000000>; + hactive = <1024>; + vactive = <600>; + hback-porch = <160>; + hfront-porch = <160>; + vback-porch = <20>; + vfront-porch = <15>; + hsync-len = <6>; + vsync-len = <5>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + }; + }; + }; + +# example3: +# 1 video source input, 2 channel, 1 lane, 1 remote, 2 video output: +# disp in can select follow interface: +# dsi0_rx, dsi1_rx, lvds0_rx, lvds1_rx, dual-lvds_rx, rgb_rx +# disp out can select follow interface: +# lvds0_tx and lvds1_tx + +--------+ + lvds0_tx | | + +--->| screen | ++-------+ +---------+ +---------+ | | | +| | disp in | | cable0 | |----+ +--------+ +| soc |--------->| RK110 +----------->| RK120 | +| | | | | |----+ +--------+ ++-------+ +---------+ +---------+ | | | + +--->| screen | + lvds1_tx | | + +--------+ + +examples3: + - | + #include + &i2c1 { + status = "okay"; + + rkx110_x120: rkx110_x120@55 { + compatible = "rockchip,rkx110"; + enable-gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_LOW>; + status = "okay"; + + remote0-addr = <0x35>; + + panel { + compatible = "rockchip,serdes_panel"; + status = "okay"; + + local-port0 = ; + remote0-port0 = ; + remote0-port1 = ; + + backlight0 = <&backlight>; + power0-supply = <&vcc3v3_lcd_n>; + reset0-gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_LOW>; + reset0-delay-ms = <20>; + enable0-delay-ms = <20>; + prepare0-delay-ms = <20>; + unprepare0-delay-ms = <20>; + disable0-delay-ms = <20>; + bus-format0 = ; + + display-timings { + native-mode = <&timing0>; + + timing0: timing0 { + clock-frequency = <27000000>; + hactive = <1024>; + vactive = <600>; + hback-porch = <160>; + hfront-porch = <160>; + vback-porch = <20>; + vfront-porch = <15>; + hsync-len = <6>; + vsync-len = <5>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + }; + }; + }; + +# example4: +# 2 video source input, 2 channel, 1 lane, 1 remote, 2 video output: +# disp in can select follow interface: +# dsi0_rx and dsi1_rx, or lvds0_rx and lvds1_rx +# disp out can select follow interface: +# lvds0_tx and lvds1_tx + +--------+ + lvds0_tx | | + +--->| screen | ++-------+ disp0_rx +---------+ +---------+ | | | +| |--------->| | cable0 | |----+ +--------+ +| soc | disp1_rx | RK110 +----------->| RK120 | +| |--------->| | | |----+ +--------+ ++-------+ +---------+ +---------+ | | | + +--->| screen | + lvds1_tx | | + +--------+ + +examples4: + - | + #include + &i2c1 { + status = "okay"; + + rkx110_x120: rkx110_x120@55 { + compatible = "rockchip,rkx110"; + enable-gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_LOW>; + status = "okay"; + + remote0-addr = <0x35>; + + panel { + compatible = "rockchip,serdes_panel"; + status = "okay"; + + local-port0 = ; + local-port1 = ; + remote0-port0 = ; + remote0-port1 = ; + + backlight0 = <&backlight>; + power0-supply = <&vcc3v3_lcd_n>; + reset0-gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_LOW>; + reset0-delay-ms = <20>; + enable0-delay-ms = <20>; + prepare0-delay-ms = <20>; + unprepare0-delay-ms = <20>; + disable0-delay-ms = <20>; + bus-format0 = ; + + display-timings { + native-mode = <&timing0>; + + timing0: timing0 { + clock-frequency = <27000000>; + hactive = <1024>; + vactive = <600>; + hback-porch = <160>; + hfront-porch = <160>; + vback-porch = <20>; + vfront-porch = <15>; + hsync-len = <6>; + vsync-len = <5>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + }; + }; + }; + +# example5: +# 2 video source input, 2 channel, 2 lane, 1 remote, 2 video output: +# disp in can select follow interface: +# dsi0_rx and dsi1_rx, or lvds0_rx and lvds1_rx +# disp out can select follow interface: +# lvds0_tx and lvds1_tx + +--------+ + lvds0_tx | | + +--->| screen | ++-------+ disp0_rx +---------+ cable0 +---------+ | | | +| |--------->| +----------->| |----+ +--------+ +| soc | disp1_rx | RK110 | cable1 | RK120 | +| |--------->| +----------->| |----+ +--------+ ++-------+ +---------+ +---------+ | | | + +--->| screen | + lvds1_tx | | + +--------+ + +examples5: + - | + #include + &i2c1 { + status = "okay"; + + rkx110_x120: rkx110_x120@55 { + compatible = "rockchip,rkx110"; + enable-gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_LOW>; + status = "okay"; + + remote0-addr = <0x35>; + + panel { + compatible = "rockchip,serdes_panel"; + status = "okay"; + + local-port0 = ; + local-port1 = ; + remote0-port0 = ; + remote0-port1 = ; + num-lanes = <2>; + + backlight0 = <&backlight>; + power0-supply = <&vcc3v3_lcd_n>; + reset0-gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_LOW>; + reset0-delay-ms = <20>; + enable0-delay-ms = <20>; + prepare0-delay-ms = <20>; + unprepare0-delay-ms = <20>; + disable0-delay-ms = <20>; + bus-format0 = ; + + display-timings { + native-mode = <&timing0>; + + timing0: timing0 { + clock-frequency = <27000000>; + hactive = <1024>; + vactive = <600>; + hback-porch = <160>; + hfront-porch = <160>; + vback-porch = <20>; + vfront-porch = <15>; + hsync-len = <6>; + vsync-len = <5>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + }; + }; + }; + +# example6: +# 2 video source input, 2 channel, 2 lane, 2 remote, 2 video output: +# disp in can select follow interface: +# dsi0_rx and dsi1_rx, or lvds0_rx and lvds1_rx +# disp out can select follow interface: +# dsi_tx, lvds0_tx, lvds1_tx, dual-lvds_tx, rgb_tx + +---------+ +--------+ + cable0 | |disp0 out| | + +------->| RK120 +-------->| screen | + | | | | | ++-------+ disp0_rx +---------+ | +---------+ +--------+ +| |--------->| +---+ +| soc | disp1_rx | RK110 | +| |--------->| +---+ ++-------+ +---------+ | +---------+ +--------+ + |cable1 | |disp1 out| | + +------->| RK120 +-------->| screen | + | | | | + +---------+ +--------+ + +examples6: + - | + #include + &i2c1 { + status = "okay"; + + rkx110_x120: rkx110_x120@55 { + compatible = "rockchip,rkx110"; + enable-gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_LOW>; + status = "okay"; + + remote0-addr = <0x35>; + remote1-addr = <0x36>; + + panel { + compatible = "rockchip,serdes_panel"; + status = "okay"; + + local-port0 = ; + local-port1 = ; + remote0-port0 = ; + remote1-port0 = ; + + backlight0 = <&backlight>; + power0-supply = <&vcc3v3_lcd_n>; + reset0-gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_LOW>; + reset0-delay-ms = <20>; + enable0-delay-ms = <20>; + prepare0-delay-ms = <20>; + unprepare0-delay-ms = <20>; + disable0-delay-ms = <20>; + bus-format0 = ; + + display-timings { + native-mode = <&timing0>; + + timing0: timing0 { + clock-frequency = <27000000>; + hactive = <1024>; + vactive = <600>; + hback-porch = <160>; + hfront-porch = <160>; + vback-porch = <20>; + vfront-porch = <15>; + hsync-len = <6>; + vsync-len = <5>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + }; + }; + }; \ No newline at end of file diff --git a/include/dt-bindings/mfd/rockchip-serdes.h b/include/dt-bindings/mfd/rockchip-serdes.h new file mode 100644 index 000000000000..610a1e3f5be8 --- /dev/null +++ b/include/dt-bindings/mfd/rockchip-serdes.h @@ -0,0 +1,151 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ +/* + * This header provides macros for Rockchip SerDes device bindings. + * + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + */ + +#ifndef __DT_BINDINGS_MFD_ROCKCHIP_SERDES_H +#define __DT_BINDINGS_MFD_ROCKCHIP_SERDES_H + +#define RK_SERDES_RGB_RX (1 << 0) +#define RK_SERDES_LVDS_RX0 (1 << 1) +#define RK_SERDES_LVDS_RX1 (1 << 2) +#define RK_SERDES_DSI_RX0 (1 << 3) +#define RK_SERDES_DSI_RX1 (1 << 4) +#define RK_SERDES_DUAL_LVDS_RX (1 << 5) + +#define RK_SERDES_RGB_TX (1 << 0) +#define RK_SERDES_LVDS_TX0 (1 << 1) +#define RK_SERDES_LVDS_TX1 (1 << 2) +#define RK_SERDES_DSI_TX0 (1 << 3) +#define RK_SERDES_DSI_TX1 (1 << 4) +#define RK_SERDES_DUAL_LVDS_TX (1 << 5) + +/* Serdes camera stream port */ +#define RK_SERDES_CSI_RX0 (1 << 16) +#define RK_SERDES_DVP_RX (1 << 18) + +#define RK_SERDES_CSI_TX0 (1 << 16) +#define RK_SERDES_CSI_TX1 (1 << 17) +#define RK_SERDES_DVP_TX (1 << 18) + +/* Serdes chip type */ +#define RK_SERDES_CHIP_LOCAL 0 +#define RK_SERDES_CHIP_REMOTE0 1 +#define RK_SERDES_CHIP_REMOTE1 2 + +/* Seredes pin control */ +#define RK_SERDES_SER_GPIO_BANK0 (0) +#define RK_SERDES_SER_GPIO_BANK1 (1) +#define RK_SERDES_DES_GPIO_BANK0 (5) +#define RK_SERDES_DES_GPIO_BANK1 (6) + +/* + * Elements values convention: ffff f000 0000 00ss dddd dddd eepp xxxx + * - ffff f : Flag MUX/PUL/PEN/DRV/SMT + * - ss : Schmitt value + * - dddd dddd : Drive Level value + * - ee : Pull Enable value + * - pp : Pull Mode value + * - xxxx : IOMUX Function value + */ +#define RK_SERDES_FLAG_MUX (1 << 31) +#define RK_SERDES_FLAG_PUL (1 << 30) +#define RK_SERDES_FLAG_PEN (1 << 29) +#define RK_SERDES_FLAG_DRV (1 << 28) +#define RK_SERDES_FLAG_SMT (1 << 27) +#define RK_SERDES_SHIFT_MUX (0) +#define RK_SERDES_SHIFT_PUL (4) +#define RK_SERDES_SHIFT_PEN (6) +#define RK_SERDES_SHIFT_DRV (8) +#define RK_SERDES_SHIFT_SMT (16) +#define RK_SERDES_MASK_MUX (0xFU << RK_SERDES_SHIFT_MUX) +#define RK_SERDES_MASK_PUL (0x3U << RK_SERDES_SHIFT_PUL) +#define RK_SERDES_MASK_PEN (0x3U << RK_SERDES_SHIFT_PEN) +#define RK_SERDES_MASK_DRV (0xFFU << RK_SERDES_SHIFT_DRV) +#define RK_SERDES_MASK_SMT (0x3U << RK_SERDES_SHIFT_SMT) + +#define RK_SERDES_PIN_CONFIG_MUX_FUNC0 (0x0 << RK_SERDES_SHIFT_MUX | RK_SERDES_FLAG_MUX) +#define RK_SERDES_PIN_CONFIG_MUX_FUNC1 (0x1 << RK_SERDES_SHIFT_MUX | RK_SERDES_FLAG_MUX) +#define RK_SERDES_PIN_CONFIG_MUX_FUNC2 (0x2 << RK_SERDES_SHIFT_MUX | RK_SERDES_FLAG_MUX) +#define RK_SERDES_PIN_CONFIG_MUX_FUNC3 (0x3 << RK_SERDES_SHIFT_MUX | RK_SERDES_FLAG_MUX) +#define RK_SERDES_PIN_CONFIG_MUX_FUNC4 (0x4 << RK_SERDES_SHIFT_MUX | RK_SERDES_FLAG_MUX) +#define RK_SERDES_PIN_CONFIG_MUX_FUNC5 (0x5 << RK_SERDES_SHIFT_MUX | RK_SERDES_FLAG_MUX) +#define RK_SERDES_PIN_CONFIG_MUX_FUNC6 (0x6 << RK_SERDES_SHIFT_MUX | RK_SERDES_FLAG_MUX) +#define RK_SERDES_PIN_CONFIG_MUX_FUNC7 (0x7 << RK_SERDES_SHIFT_MUX | RK_SERDES_FLAG_MUX) +#define RK_SERDES_PIN_CONFIG_MUX_DEFAULT RK_SERDES_PIN_CONFIG_MUX_FUNC0 + +#define RK_SERDES_PIN_CONFIG_PUL_NORMAL (0x0 << RK_SERDES_SHIFT_PUL | RK_SERDES_FLAG_PUL) +#define RK_SERDES_PIN_CONFIG_PUL_UP (0x1 << RK_SERDES_SHIFT_PUL | RK_SERDES_FLAG_PUL) +#define RK_SERDES_PIN_CONFIG_PUL_DOWN (0x2 << RK_SERDES_SHIFT_PUL | RK_SERDES_FLAG_PUL) +#define RK_SERDES_PIN_CONFIG_PUL_KEEP (0x3 << RK_SERDES_SHIFT_PUL | RK_SERDES_FLAG_PUL) +#define RK_SERDES_PIN_CONFIG_PUL_DEFAULT RK_SERDES_PIN_CONFIG_PUL_NORMAL + +#define RK_SERDES_PIN_CONFIG_PEN_DISABLE (0x0 << RK_SERDES_SHIFT_PEN | RK_SERDES_FLAG_PEN) +#define RK_SERDES_PIN_CONFIG_PEN_ENABLE (0x1 << RK_SERDES_SHIFT_PEN | RK_SERDES_FLAG_PEN) +#define RK_SERDES_PIN_CONFIG_PEN_DEFAULT RK_SERDES_PIN_CONFIG_PEN_DISABLE + +#define RK_SERDES_PIN_CONFIG_DRV_LEVEL0 (0x0 << RK_SERDES_SHIFT_DRV | RK_SERDES_FLAG_DRV) +#define RK_SERDES_PIN_CONFIG_DRV_LEVEL1 (0x1 << RK_SERDES_SHIFT_DRV | RK_SERDES_FLAG_DRV) +#define RK_SERDES_PIN_CONFIG_DRV_LEVEL2 (0x2 << RK_SERDES_SHIFT_DRV | RK_SERDES_FLAG_DRV) +#define RK_SERDES_PIN_CONFIG_DRV_LEVEL3 (0x3 << RK_SERDES_SHIFT_DRV | RK_SERDES_FLAG_DRV) +#define RK_SERDES_PIN_CONFIG_DRV_LEVEL4 (0x4 << RK_SERDES_SHIFT_DRV | RK_SERDES_FLAG_DRV) +#define RK_SERDES_PIN_CONFIG_DRV_LEVEL5 (0x5 << RK_SERDES_SHIFT_DRV | RK_SERDES_FLAG_DRV) +#define RK_SERDES_PIN_CONFIG_DRV_LEVEL6 (0x6 << RK_SERDES_SHIFT_DRV | RK_SERDES_FLAG_DRV) +#define RK_SERDES_PIN_CONFIG_DRV_LEVEL7 (0x7 << RK_SERDES_SHIFT_DRV | RK_SERDES_FLAG_DRV) +#define RK_SERDES_PIN_CONFIG_DRV_LEVEL_DEFAULT RK_SERDES_PIN_CONFIG_DRV_LEVEL2 + +#define RK_SERDES_PIN_CONFIG_SMT_DISABLE (0x0 << RK_SERDES_SHIFT_SMT | RK_SERDES_FLAG_SMT) +#define RK_SERDES_PIN_CONFIG_SMT_ENABLE (0x1 << RK_SERDES_SHIFT_SMT | RK_SERDES_FLAG_SMT) +#define RK_SERDES_PIN_CONFIG_SMT_DEFAULT RK_SERDES_PIN_CONFIG_SMT_DISABLE + +#define RK_SERDES_PIN_CONFIG_MAX 0xFFFFFFFFU + +#define RK_SERDES_GPIO_PIN_A0 0x00000001U /*!< Pin 0 selected */ +#define RK_SERDES_GPIO_PIN_A1 0x00000002U /*!< Pin 1 selected */ +#define RK_SERDES_GPIO_PIN_A2 0x00000004U /*!< Pin 2 selected */ +#define RK_SERDES_GPIO_PIN_A3 0x00000008U /*!< Pin 3 selected */ +#define RK_SERDES_GPIO_PIN_A4 0x00000010U /*!< Pin 4 selected */ +#define RK_SERDES_GPIO_PIN_A5 0x00000020U /*!< Pin 5 selected */ +#define RK_SERDES_GPIO_PIN_A6 0x00000040U /*!< Pin 6 selected */ +#define RK_SERDES_GPIO_PIN_A7 0x00000080U /*!< Pin 7 selected */ +#define RK_SERDES_GPIO_PIN_B0 0x00000100U /*!< Pin 8 selected */ +#define RK_SERDES_GPIO_PIN_B1 0x00000200U /*!< Pin 9 selected */ +#define RK_SERDES_GPIO_PIN_B2 0x00000400U /*!< Pin 10 selected */ +#define RK_SERDES_GPIO_PIN_B3 0x00000800U /*!< Pin 11 selected */ +#define RK_SERDES_GPIO_PIN_B4 0x00001000U /*!< Pin 12 selected */ +#define RK_SERDES_GPIO_PIN_B5 0x00002000U /*!< Pin 13 selected */ +#define RK_SERDES_GPIO_PIN_B6 0x00004000U /*!< Pin 14 selected */ +#define RK_SERDES_GPIO_PIN_B7 0x00008000U /*!< Pin 15 selected */ +#define RK_SERDES_GPIO_PIN_C0 0x00010000U /*!< Pin 16 selected */ +#define RK_SERDES_GPIO_PIN_C1 0x00020000U /*!< Pin 17 selected */ +#define RK_SERDES_GPIO_PIN_C2 0x00040000U /*!< Pin 18 selected */ +#define RK_SERDES_GPIO_PIN_C3 0x00080000U /*!< Pin 19 selected */ +#define RK_SERDES_GPIO_PIN_C4 0x00100000U /*!< Pin 20 selected */ +#define RK_SERDES_GPIO_PIN_C5 0x00200000U /*!< Pin 21 selected */ +#define RK_SERDES_GPIO_PIN_C6 0x00400000U /*!< Pin 22 selected */ +#define RK_SERDES_GPIO_PIN_C7 0x00800000U /*!< Pin 23 selected */ +#define RK_SERDES_GPIO_PIN_D0 0x01000000U /*!< Pin 24 selected */ +#define RK_SERDES_GPIO_PIN_D1 0x02000000U /*!< Pin 25 selected */ +#define RK_SERDES_GPIO_PIN_D2 0x04000000U /*!< Pin 26 selected */ +#define RK_SERDES_GPIO_PIN_D3 0x08000000U /*!< Pin 27 selected */ +#define RK_SERDES_GPIO_PIN_D4 0x10000000U /*!< Pin 28 selected */ +#define RK_SERDES_GPIO_PIN_D5 0x20000000U /*!< Pin 29 selected */ +#define RK_SERDES_GPIO_PIN_D6 0x40000000U /*!< Pin 30 selected */ +#define RK_SERDES_GPIO_PIN_D7 0x80000000U /*!< Pin 31 selected */ +#define RK_SERDES_GPIO_PIN_ALL (0xFFFFFFFFU) /*!< All pins selected */ + +/* passthrough function */ +#define RK_SERDES_PASSTHROUGH_GPI_GPO_0 (0) +#define RK_SERDES_PASSTHROUGH_GPI_GPO_1 (1) +#define RK_SERDES_PASSTHROUGH_GPI_GPO_2 (2) +#define RK_SERDES_PASSTHROUGH_GPI_GPO_3 (3) +#define RK_SERDES_PASSTHROUGH_GPI_GPO_4 (4) +#define RK_SERDES_PASSTHROUGH_GPI_GPO_5 (5) +#define RK_SERDES_PASSTHROUGH_GPI_GPO_6 (6) +#define RK_SERDES_PASSTHROUGH_IRQ (7) +#define RK_SERDES_PASSTHROUGH_UART_0 (8) +#define RK_SERDES_PASSTHROUGH_UART_1 (9) +#define RK_SERDES_PASSTHROUGH_SPI (10) +#endif /* __DT_BINDINGS_MFD_ROCKCHIP_SERDES_H */ From 86a4b8b789f5ca1abcc294d5e2b6f35c7f8e096b Mon Sep 17 00:00:00 2001 From: Guochun Huang Date: Fri, 25 Nov 2022 13:24:52 +0000 Subject: [PATCH 4/6] arm64: configs: rockchip_defconfig: enable CONFIG_MFD_RKX110_X120 enable the rkx110/rkx120 serdes driver use on rk3568m-serdes-evb Change-Id: I5f7f8df6a4b9e4c7d95916b22e7db846d4bd0bc1 Signed-off-by: Guochun Huang --- arch/arm64/configs/rockchip_defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/configs/rockchip_defconfig b/arch/arm64/configs/rockchip_defconfig index 8323c122eb15..bfa664697885 100644 --- a/arch/arm64/configs/rockchip_defconfig +++ b/arch/arm64/configs/rockchip_defconfig @@ -554,6 +554,8 @@ CONFIG_MFD_RK628=y CONFIG_MFD_RK630_I2C=y CONFIG_MFD_RK806_SPI=y CONFIG_MFD_RK808=y +CONFIG_MFD_RKX110_X120=y +CONFIG_ROCKCHIP_SERDES_DRM_PANEL=y CONFIG_REGULATOR=y CONFIG_REGULATOR_FIXED_VOLTAGE=y CONFIG_REGULATOR_ACT8865=y From 997dc09f432d3113565815e33d593c66607207be Mon Sep 17 00:00:00 2001 From: Caesar Wang Date: Tue, 10 Jan 2023 17:23:16 +0800 Subject: [PATCH 5/6] arm64/configs: rockchip_linux_defconfig: enable CONFIG_MFD_RKX110_X120 Change-Id: I46b6b7c4941b9809c267f6efc4a504bc62ddea33 Signed-off-by: Caesar Wang --- arch/arm64/configs/rockchip_linux_defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/configs/rockchip_linux_defconfig b/arch/arm64/configs/rockchip_linux_defconfig index b1f8d1079528..368eff2b54b1 100644 --- a/arch/arm64/configs/rockchip_linux_defconfig +++ b/arch/arm64/configs/rockchip_linux_defconfig @@ -282,6 +282,8 @@ CONFIG_WATCHDOG=y CONFIG_DW_WATCHDOG=y CONFIG_MFD_RK806_SPI=y CONFIG_MFD_RK808=y +CONFIG_MFD_RKX110_X120=y +CONFIG_ROCKCHIP_SERDES_DRM_PANEL=y CONFIG_MFD_TPS6586X=y CONFIG_REGULATOR=y CONFIG_REGULATOR_FIXED_VOLTAGE=y From 6904d47493f4ae8f3a8981a7c1e4017e093c2fea Mon Sep 17 00:00:00 2001 From: Guochun Huang Date: Wed, 16 Nov 2022 06:59:08 +0000 Subject: [PATCH 6/6] arm64: dts: rockchip: add rk3568m serdes evb support Change-Id: Ia9e6580fa591076741f9e33ff2142df71f503b89 Signed-off-by: Guochun Huang Signed-off-by: Andy Yan Signed-off-by: Cai Wenzhong Signed-off-by: Zhang Yubing --- arch/arm64/boot/dts/rockchip/Makefile | 32 ++ .../rk3568m-serdes-evb-camera-csi-v10.dts | 25 ++ .../rk3568m-serdes-evb-camera-dvp-v10.dts | 25 ++ ...-evb-display-dsi0-command2dsi-lp4x-v10.dts | 409 ++++++++++++++++++ ...vb-display-dsi0-command2lvds0-lp4x-v10.dts | 137 ++++++ ...-evb-display-dsi0-command2rgb-lp4x-v10.dts | 137 ++++++ ...-evb-display-dsi1-command2dsi-lp4x-v10.dts | 409 ++++++++++++++++++ ...vb-display-dsi1-command2lvds0-lp4x-v10.dts | 137 ++++++ ...-evb-display-dsi1-command2rgb-lp4x-v10.dts | 137 ++++++ ...-serdes-evb-display-lvds2lvds-lp4x-v10.dts | 96 ++++ ...m-serdes-evb-display-lvds2rgb-lp4x-v10.dts | 96 ++++ ...8m-serdes-evb-display-rgb2dsi-lp4x-v10.dts | 345 +++++++++++++++ ...m-serdes-evb-display-rgb2lvds-lp4x-v10.dts | 88 ++++ ...8m-serdes-evb-display-rgb2rgb-lp4x-v10.dts | 88 ++++ .../rk3568m-serdes-evb-lp4x-v10-camera.dtsi | 195 +++++++++ .../rockchip/rk3568m-serdes-evb-lp4x-v10.dtsi | 211 +++++++++ ...-evb-display-dsi0-command2dsi-lp4x-v10.dts | 397 +++++++++++++++++ ...isplay-dsi0-command2dual_lvds-lp4x-v10.dts | 123 ++++++ ...vb-display-dsi0-command2lvds0-lp4x-v10.dts | 123 ++++++ ...dsi0-dsi1-command2dual_lvdsx2-lp4x-v10.dts | 165 +++++++ ...-evb-display-dsi1-command2dsi-lp4x-v10.dts | 397 +++++++++++++++++ ...isplay-dsi1-command2dual_lvds-lp4x-v10.dts | 123 ++++++ ...vb-display-dsi1-command2lvds0-lp4x-v10.dts | 123 ++++++ ...erdes-v1-evb-display-lvds2dsi-lp4x-v10.dts | 369 ++++++++++++++++ ...v1-evb-display-lvds2dual-lvds-lp4x-v10.dts | 112 +++++ ...isplay-lvds2dual-lvds-vehicle-lp4x-v10.dts | 112 +++++ ...rdes-v1-evb-display-lvds2lvds-lp4x-v10.dts | 112 +++++ ...erdes-v1-evb-display-lvds2rgb-lp4x-v10.dts | 112 +++++ ...serdes-v1-evb-display-rgb2dsi-lp4x-v10.dts | 370 ++++++++++++++++ ...-v1-evb-display-rgb2dual-lvds-lp4x-v10.dts | 113 +++++ ...display-rgb2dual-lvds-vehicle-lp4x-v10.dts | 113 +++++ ...erdes-v1-evb-display-rgb2lvds-lp4x-v10.dts | 112 +++++ ...serdes-v1-evb-display-rgb2rgb-lp4x-v10.dts | 113 +++++ ...-super-frame-dsi0-command2dsi-lp4x-v10.dts | 392 +++++++++++++++++ ...uper-frame-dsi0-command2lvds0-lp4x-v10.dts | 117 +++++ .../rk3568m-serdes-v1-evb-lp4x-v10.dtsi | 294 +++++++++++++ 36 files changed, 6459 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3568m-serdes-evb-camera-csi-v10.dts create mode 100644 arch/arm64/boot/dts/rockchip/rk3568m-serdes-evb-camera-dvp-v10.dts create mode 100644 arch/arm64/boot/dts/rockchip/rk3568m-serdes-evb-display-dsi0-command2dsi-lp4x-v10.dts create mode 100644 arch/arm64/boot/dts/rockchip/rk3568m-serdes-evb-display-dsi0-command2lvds0-lp4x-v10.dts create mode 100644 arch/arm64/boot/dts/rockchip/rk3568m-serdes-evb-display-dsi0-command2rgb-lp4x-v10.dts create mode 100644 arch/arm64/boot/dts/rockchip/rk3568m-serdes-evb-display-dsi1-command2dsi-lp4x-v10.dts create mode 100644 arch/arm64/boot/dts/rockchip/rk3568m-serdes-evb-display-dsi1-command2lvds0-lp4x-v10.dts create mode 100644 arch/arm64/boot/dts/rockchip/rk3568m-serdes-evb-display-dsi1-command2rgb-lp4x-v10.dts create mode 100644 arch/arm64/boot/dts/rockchip/rk3568m-serdes-evb-display-lvds2lvds-lp4x-v10.dts create mode 100644 arch/arm64/boot/dts/rockchip/rk3568m-serdes-evb-display-lvds2rgb-lp4x-v10.dts create mode 100644 arch/arm64/boot/dts/rockchip/rk3568m-serdes-evb-display-rgb2dsi-lp4x-v10.dts create mode 100644 arch/arm64/boot/dts/rockchip/rk3568m-serdes-evb-display-rgb2lvds-lp4x-v10.dts create mode 100644 arch/arm64/boot/dts/rockchip/rk3568m-serdes-evb-display-rgb2rgb-lp4x-v10.dts create mode 100644 arch/arm64/boot/dts/rockchip/rk3568m-serdes-evb-lp4x-v10-camera.dtsi create mode 100644 arch/arm64/boot/dts/rockchip/rk3568m-serdes-evb-lp4x-v10.dtsi create mode 100644 arch/arm64/boot/dts/rockchip/rk3568m-serdes-v1-evb-display-dsi0-command2dsi-lp4x-v10.dts create mode 100644 arch/arm64/boot/dts/rockchip/rk3568m-serdes-v1-evb-display-dsi0-command2dual_lvds-lp4x-v10.dts create mode 100644 arch/arm64/boot/dts/rockchip/rk3568m-serdes-v1-evb-display-dsi0-command2lvds0-lp4x-v10.dts create mode 100644 arch/arm64/boot/dts/rockchip/rk3568m-serdes-v1-evb-display-dsi0-dsi1-command2dual_lvdsx2-lp4x-v10.dts create mode 100644 arch/arm64/boot/dts/rockchip/rk3568m-serdes-v1-evb-display-dsi1-command2dsi-lp4x-v10.dts create mode 100644 arch/arm64/boot/dts/rockchip/rk3568m-serdes-v1-evb-display-dsi1-command2dual_lvds-lp4x-v10.dts create mode 100644 arch/arm64/boot/dts/rockchip/rk3568m-serdes-v1-evb-display-dsi1-command2lvds0-lp4x-v10.dts create mode 100644 arch/arm64/boot/dts/rockchip/rk3568m-serdes-v1-evb-display-lvds2dsi-lp4x-v10.dts create mode 100644 arch/arm64/boot/dts/rockchip/rk3568m-serdes-v1-evb-display-lvds2dual-lvds-lp4x-v10.dts create mode 100644 arch/arm64/boot/dts/rockchip/rk3568m-serdes-v1-evb-display-lvds2dual-lvds-vehicle-lp4x-v10.dts create mode 100644 arch/arm64/boot/dts/rockchip/rk3568m-serdes-v1-evb-display-lvds2lvds-lp4x-v10.dts create mode 100644 arch/arm64/boot/dts/rockchip/rk3568m-serdes-v1-evb-display-lvds2rgb-lp4x-v10.dts create mode 100644 arch/arm64/boot/dts/rockchip/rk3568m-serdes-v1-evb-display-rgb2dsi-lp4x-v10.dts create mode 100644 arch/arm64/boot/dts/rockchip/rk3568m-serdes-v1-evb-display-rgb2dual-lvds-lp4x-v10.dts create mode 100644 arch/arm64/boot/dts/rockchip/rk3568m-serdes-v1-evb-display-rgb2dual-lvds-vehicle-lp4x-v10.dts create mode 100644 arch/arm64/boot/dts/rockchip/rk3568m-serdes-v1-evb-display-rgb2lvds-lp4x-v10.dts create mode 100644 arch/arm64/boot/dts/rockchip/rk3568m-serdes-v1-evb-display-rgb2rgb-lp4x-v10.dts create mode 100644 arch/arm64/boot/dts/rockchip/rk3568m-serdes-v1-evb-display-super-frame-dsi0-command2dsi-lp4x-v10.dts create mode 100644 arch/arm64/boot/dts/rockchip/rk3568m-serdes-v1-evb-display-super-frame-dsi0-command2lvds0-lp4x-v10.dts create mode 100644 arch/arm64/boot/dts/rockchip/rk3568m-serdes-v1-evb-lp4x-v10.dtsi diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile index 1344678c9ee4..b23465825c79 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -157,6 +157,38 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-toybrick-sd0-android.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-toybrick-sd0-linux.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-toybrick-x0-android.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-toybrick-x0-linux.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568m-serdes-evb-camera-csi-v10.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568m-serdes-evb-camera-dvp-v10.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568m-serdes-evb-display-dsi0-command2dsi-lp4x-v10.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568m-serdes-evb-display-dsi0-command2lvds0-lp4x-v10.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568m-serdes-evb-display-dsi0-command2rgb-lp4x-v10.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568m-serdes-evb-display-dsi1-command2dsi-lp4x-v10.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568m-serdes-evb-display-dsi1-command2lvds0-lp4x-v10.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568m-serdes-evb-display-dsi1-command2rgb-lp4x-v10.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568m-serdes-evb-display-rgb2dsi-lp4x-v10.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568m-serdes-evb-display-rgb2lvds-lp4x-v10.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568m-serdes-evb-display-rgb2rgb-lp4x-v10.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568m-serdes-evb-display-lvds2lvds-lp4x-v10.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568m-serdes-evb-display-lvds2rgb-lp4x-v10.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568m-serdes-v1-evb-display-dsi0-command2dsi-lp4x-v10.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568m-serdes-v1-evb-display-dsi0-command2dual_lvds-lp4x-v10.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568m-serdes-v1-evb-display-dsi0-command2lvds0-lp4x-v10.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568m-serdes-v1-evb-display-dsi0-dsi1-command2dual_lvdsx2-lp4x-v10.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568m-serdes-v1-evb-display-dsi1-command2dsi-lp4x-v10.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568m-serdes-v1-evb-display-dsi1-command2dual_lvds-lp4x-v10.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568m-serdes-v1-evb-display-dsi1-command2lvds0-lp4x-v10.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568m-serdes-v1-evb-display-lvds2dsi-lp4x-v10.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568m-serdes-v1-evb-display-lvds2dual-lvds-lp4x-v10.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568m-serdes-v1-evb-display-lvds2dual-lvds-vehicle-lp4x-v10.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568m-serdes-v1-evb-display-lvds2lvds-lp4x-v10.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568m-serdes-v1-evb-display-lvds2rgb-lp4x-v10.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568m-serdes-v1-evb-display-rgb2dsi-lp4x-v10.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568m-serdes-v1-evb-display-rgb2dual-lvds-lp4x-v10.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568m-serdes-v1-evb-display-rgb2dual-lvds-vehicle-lp4x-v10.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568m-serdes-v1-evb-display-rgb2lvds-lp4x-v10.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568m-serdes-v1-evb-display-rgb2rgb-lp4x-v10.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568m-serdes-v1-evb-display-super-frame-dsi0-command2dsi-lp4x-v10.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568m-serdes-v1-evb-display-super-frame-dsi0-command2lvds0-lp4x-v10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-evb1-lp4-v10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-evb1-lp4-v10-dsi-dsc-MV2100UZ1.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-evb1-lp4-v10-ipc-6x-linux.dtb diff --git a/arch/arm64/boot/dts/rockchip/rk3568m-serdes-evb-camera-csi-v10.dts b/arch/arm64/boot/dts/rockchip/rk3568m-serdes-evb-camera-csi-v10.dts new file mode 100644 index 000000000000..35290244793c --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3568m-serdes-evb-camera-csi-v10.dts @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Rockchip Electronics Co., Ltd. + * + */ + +#include "rk3568m-serdes-evb-lp4x-v10-camera.dtsi" +#include "rk3568-android.dtsi" + +&rkx120_x110 { + enable-gpios = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio2 RK_PB0 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&rkx120_reset_gpio>; +}; + +&serdes_camera { + local-port0 = ; + remote0-port0 = ; +}; + +&i2c3 { + status = "okay"; + clock-frequency = <10000>; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3568m-serdes-evb-camera-dvp-v10.dts b/arch/arm64/boot/dts/rockchip/rk3568m-serdes-evb-camera-dvp-v10.dts new file mode 100644 index 000000000000..199b142acd31 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3568m-serdes-evb-camera-dvp-v10.dts @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Rockchip Electronics Co., Ltd. + * + */ + +#include "rk3568m-serdes-evb-lp4x-v10-camera.dtsi" +#include "rk3568-android.dtsi" + +&rkx120_x110 { + enable-gpios = <&gpio0 RK_PD6 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio4 RK_PB5 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&rkx120_reset_gpio>; +}; + +&serdes_camera { + local-port0 = ; + remote0-port0 = ; +}; + +&i2c3 { + status = "okay"; + clock-frequency = <10000>; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3568m-serdes-evb-display-dsi0-command2dsi-lp4x-v10.dts b/arch/arm64/boot/dts/rockchip/rk3568m-serdes-evb-display-dsi0-command2dsi-lp4x-v10.dts new file mode 100644 index 000000000000..2c5ae275ac4a --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3568m-serdes-evb-display-dsi0-command2dsi-lp4x-v10.dts @@ -0,0 +1,409 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +#include +#include "rk3568m-serdes-evb-lp4x-v10.dtsi" +#include "rk3568-android.dtsi" + +&i2c1 { + status = "okay"; + clock-frequency = <10000>; +}; + +&dsi1 { + status = "okay"; +}; + +&dsi1_in_vp0 { + status = "okay"; +}; + +&dsi1_in_vp1 { + status = "disabled"; +}; + +&dsi1_panel { + status = "okay"; + dsi,flags = <(MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET | + MIPI_DSI_CLOCK_NON_CONTINUOUS)>; + dsi,format = ; + dsi,lanes = <4>; + + panel-init-sequence = []; + panel-exit-sequence = []; +}; + +&dsi1_timing0 { + clock-frequency = <132000000>; + hactive = <1080>; + vactive = <1920>; + hfront-porch = <15>; + hsync-len = <2>; + hback-porch = <30>; + vfront-porch = <15>; + vsync-len = <2>; + vback-porch = <15>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <1>; +}; + +&video_phy1 { + status = "okay"; +}; + +&rgb { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + rgb_out_rkx110_x120: endpoint { + remote-endpoint = <&rkx110_x120_in_rgb>; + }; + }; + }; +}; + +&rgb_in_vp2 { + status = "okay"; +}; + +&rkx110_reset_gpio { + rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; +}; + +&rkx110_x120 { + enable-gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&rkx110_reset_gpio>; +}; + +&serdes_timing0 { + clock-frequency = <132000000>; + hactive = <1080>; + vactive = <1920>; + hfront-porch = <15>; + hsync-len = <2>; + hback-porch = <30>; + vfront-porch = <15>; + vsync-len = <2>; + vback-porch = <15>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <1>; +}; + +&serdes_panel { + dsi-rx,lanes = <4>; + //dsi-rx,video-mode; + local-port0 = ; + remote0-port0 = ; + dsi-tx,format = "rgb888"; + dsi-tx,lanes = <4>; + dsi-tx,video-mode; + + panel-init-sequence = [ + 23 00 02 FE 21 + 23 00 02 04 00 + 23 00 02 00 64 + 23 00 02 2A 00 + 23 00 02 26 64 + 23 00 02 54 00 + 23 00 02 50 64 + 23 00 02 7B 00 + 23 00 02 77 64 + 23 00 02 A2 00 + 23 00 02 9D 64 + 23 00 02 C9 00 + 23 00 02 C5 64 + 23 00 02 01 71 + 23 00 02 27 71 + 23 00 02 51 71 + 23 00 02 78 71 + 23 00 02 9E 71 + 23 00 02 C6 71 + 23 00 02 02 89 + 23 00 02 28 89 + 23 00 02 52 89 + 23 00 02 79 89 + 23 00 02 9F 89 + 23 00 02 C7 89 + 23 00 02 03 9E + 23 00 02 29 9E + 23 00 02 53 9E + 23 00 02 7A 9E + 23 00 02 A0 9E + 23 00 02 C8 9E + 23 00 02 09 00 + 23 00 02 05 B0 + 23 00 02 31 00 + 23 00 02 2B B0 + 23 00 02 5A 00 + 23 00 02 55 B0 + 23 00 02 80 00 + 23 00 02 7C B0 + 23 00 02 A7 00 + 23 00 02 A3 B0 + 23 00 02 CE 00 + 23 00 02 CA B0 + 23 00 02 06 C0 + 23 00 02 2D C0 + 23 00 02 56 C0 + 23 00 02 7D C0 + 23 00 02 A4 C0 + 23 00 02 CB C0 + 23 00 02 07 CF + 23 00 02 2F CF + 23 00 02 58 CF + 23 00 02 7E CF + 23 00 02 A5 CF + 23 00 02 CC CF + 23 00 02 08 DD + 23 00 02 30 DD + 23 00 02 59 DD + 23 00 02 7F DD + 23 00 02 A6 DD + 23 00 02 CD DD + 23 00 02 0E 15 + 23 00 02 0A E9 + 23 00 02 36 15 + 23 00 02 32 E9 + 23 00 02 5F 15 + 23 00 02 5B E9 + 23 00 02 85 15 + 23 00 02 81 E9 + 23 00 02 AD 15 + 23 00 02 A9 E9 + 23 00 02 D3 15 + 23 00 02 CF E9 + 23 00 02 0B 14 + 23 00 02 33 14 + 23 00 02 5C 14 + 23 00 02 82 14 + 23 00 02 AA 14 + 23 00 02 D0 14 + 23 00 02 0C 36 + 23 00 02 34 36 + 23 00 02 5D 36 + 23 00 02 83 36 + 23 00 02 AB 36 + 23 00 02 D1 36 + 23 00 02 0D 6B + 23 00 02 35 6B + 23 00 02 5E 6B + 23 00 02 84 6B + 23 00 02 AC 6B + 23 00 02 D2 6B + 23 00 02 13 5A + 23 00 02 0F 94 + 23 00 02 3B 5A + 23 00 02 37 94 + 23 00 02 64 5A + 23 00 02 60 94 + 23 00 02 8A 5A + 23 00 02 86 94 + 23 00 02 B2 5A + 23 00 02 AE 94 + 23 00 02 D8 5A + 23 00 02 D4 94 + 23 00 02 10 D1 + 23 00 02 38 D1 + 23 00 02 61 D1 + 23 00 02 87 D1 + 23 00 02 AF D1 + 23 00 02 D5 D1 + 23 00 02 11 04 + 23 00 02 39 04 + 23 00 02 62 04 + 23 00 02 88 04 + 23 00 02 B0 04 + 23 00 02 D6 04 + 23 00 02 12 05 + 23 00 02 3A 05 + 23 00 02 63 05 + 23 00 02 89 05 + 23 00 02 B1 05 + 23 00 02 D7 05 + 23 00 02 18 AA + 23 00 02 14 36 + 23 00 02 42 AA + 23 00 02 3D 36 + 23 00 02 69 AA + 23 00 02 65 36 + 23 00 02 8F AA + 23 00 02 8B 36 + 23 00 02 B7 AA + 23 00 02 B3 36 + 23 00 02 DD AA + 23 00 02 D9 36 + 23 00 02 15 74 + 23 00 02 3F 74 + 23 00 02 66 74 + 23 00 02 8C 74 + 23 00 02 B4 74 + 23 00 02 DA 74 + 23 00 02 16 9F + 23 00 02 40 9F + 23 00 02 67 9F + 23 00 02 8D 9F + 23 00 02 B5 9F + 23 00 02 DB 9F + 23 00 02 17 DC + 23 00 02 41 DC + 23 00 02 68 DC + 23 00 02 8E DC + 23 00 02 B6 DC + 23 00 02 DC DC + 23 00 02 1D FF + 23 00 02 19 03 + 23 00 02 47 FF + 23 00 02 43 03 + 23 00 02 6E FF + 23 00 02 6A 03 + 23 00 02 94 FF + 23 00 02 90 03 + 23 00 02 BC FF + 23 00 02 B8 03 + 23 00 02 E2 FF + 23 00 02 DE 03 + 23 00 02 1A 35 + 23 00 02 44 35 + 23 00 02 6B 35 + 23 00 02 91 35 + 23 00 02 B9 35 + 23 00 02 DF 35 + 23 00 02 1B 45 + 23 00 02 45 45 + 23 00 02 6C 45 + 23 00 02 92 45 + 23 00 02 BA 45 + 23 00 02 E0 45 + 23 00 02 1C 55 + 23 00 02 46 55 + 23 00 02 6D 55 + 23 00 02 93 55 + 23 00 02 BB 55 + 23 00 02 E1 55 + 23 00 02 22 FF + 23 00 02 1E 68 + 23 00 02 4C FF + 23 00 02 48 68 + 23 00 02 73 FF + 23 00 02 6F 68 + 23 00 02 99 FF + 23 00 02 95 68 + 23 00 02 C1 FF + 23 00 02 BD 68 + 23 00 02 E7 FF + 23 00 02 E3 68 + 23 00 02 1F 7E + 23 00 02 49 7E + 23 00 02 70 7E + 23 00 02 96 7E + 23 00 02 BE 7E + 23 00 02 E4 7E + 23 00 02 20 97 + 23 00 02 4A 97 + 23 00 02 71 97 + 23 00 02 97 97 + 23 00 02 BF 97 + 23 00 02 E5 97 + 23 00 02 21 B5 + 23 00 02 4B B5 + 23 00 02 72 B5 + 23 00 02 98 B5 + 23 00 02 C0 B5 + 23 00 02 E6 B5 + 23 00 02 25 F0 + 23 00 02 23 E8 + 23 00 02 4F F0 + 23 00 02 4D E8 + 23 00 02 76 F0 + 23 00 02 74 E8 + 23 00 02 9C F0 + 23 00 02 9A E8 + 23 00 02 C4 F0 + 23 00 02 C2 E8 + 23 00 02 EA F0 + 23 00 02 E8 E8 + 23 00 02 24 FF + 23 00 02 4E FF + 23 00 02 75 FF + 23 00 02 9B FF + 23 00 02 C3 FF + 23 00 02 E9 FF + 23 00 02 FE 3D + 23 00 02 00 04 + 23 00 02 FE 23 + 23 00 02 08 82 + 23 00 02 0A 00 + 23 00 02 0B 00 + 23 00 02 0C 01 + 23 00 02 16 00 + 23 00 02 18 02 + 23 00 02 1B 04 + 23 00 02 19 04 + 23 00 02 1C 81 + 23 00 02 1F 00 + 23 00 02 20 03 + 23 00 02 23 04 + 23 00 02 21 01 + 23 00 02 54 63 + 23 00 02 55 54 + 23 00 02 6E 45 + 23 00 02 6D 36 + 23 00 02 FE 3D + 23 00 02 55 78 + 23 00 02 FE 20 + 23 00 02 26 30 + 23 00 02 FE 3D + 23 00 02 20 71 + 23 00 02 50 8F + 23 00 02 51 8F + 23 00 02 FE 00 + 23 00 02 35 00 + 05 78 01 11 + 05 1E 01 29 + ]; + + panel-exit-sequence = [ + 05 00 01 28 + 05 00 01 10 + ]; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + rkx110_x120_in_rgb: endpoint { + remote-endpoint = <&rgb_out_rkx110_x120>; + }; + }; + }; +}; + +/* vp0 for HDMI, vp2 for rgb */ +&vp0 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER0 | 1 << ROCKCHIP_VOP2_ESMART0 | + 1 << ROCKCHIP_VOP2_SMART0)>; + rockchip,primary-plane = ; +}; + +&vp2 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER1 | 1 << ROCKCHIP_VOP2_ESMART1 | + 1 << ROCKCHIP_VOP2_SMART1)>; + rockchip,primary-plane = ; +}; + diff --git a/arch/arm64/boot/dts/rockchip/rk3568m-serdes-evb-display-dsi0-command2lvds0-lp4x-v10.dts b/arch/arm64/boot/dts/rockchip/rk3568m-serdes-evb-display-dsi0-command2lvds0-lp4x-v10.dts new file mode 100644 index 000000000000..167547bf9a95 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3568m-serdes-evb-display-dsi0-command2lvds0-lp4x-v10.dts @@ -0,0 +1,137 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +#include +#include "rk3568m-serdes-evb-lp4x-v10.dtsi" +#include "rk3568-android.dtsi" + +&i2c1 { + status = "okay"; + clock-frequency = <10000>; +}; + +&dsi1 { + status = "okay"; +}; + +&dsi1_in_vp0 { + status = "okay"; +}; + +&dsi1_in_vp1 { + status = "disabled"; +}; + +&dsi1_panel { + status = "okay"; + dsi,flags = <(MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET | + MIPI_DSI_CLOCK_NON_CONTINUOUS)>; + dsi,format = ; + dsi,lanes = <4>; + + panel-init-sequence = []; + panel-exit-sequence = []; +}; + +&dsi1_timing0 { + clock-frequency = <50000000>; + hactive = <1024>; + vactive = <600>; + hfront-porch = <160>; + hsync-len = <20>; + hback-porch = <140>; + vfront-porch = <12>; + vsync-len = <3>; + vback-porch = <20>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <1>; +}; + +&video_phy1 { + status = "okay"; +}; + +&rgb { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + rgb_out_rkx110_x120: endpoint { + remote-endpoint = <&rkx110_x120_in_rgb>; + }; + }; + }; +}; + +&rgb_in_vp2 { + status = "okay"; +}; + +&rkx110_reset_gpio { + rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; +}; + +&rkx110_x120 { + enable-gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&rkx110_reset_gpio>; +}; + +&serdes_timing0 { + clock-frequency = <50000000>; + hactive = <1024>; + vactive = <600>; + hfront-porch = <160>; + hsync-len = <20>; + hback-porch = <140>; + vfront-porch = <12>; + vsync-len = <3>; + vback-porch = <20>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <1>; +}; + +&serdes_panel { + dsi-rx,lanes = <4>; + //dsi-rx,video-mode; + local-port0 = ; + remote0-port0 = ; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + rkx110_x120_in_rgb: endpoint { + remote-endpoint = <&rgb_out_rkx110_x120>; + }; + }; + }; +}; + +/* vp0 for HDMI, vp2 for rgb */ +&vp0 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER0 | 1 << ROCKCHIP_VOP2_ESMART0 | + 1 << ROCKCHIP_VOP2_SMART0)>; + rockchip,primary-plane = ; +}; + +&vp2 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER1 | 1 << ROCKCHIP_VOP2_ESMART1 | + 1 << ROCKCHIP_VOP2_SMART1)>; + rockchip,primary-plane = ; +}; + diff --git a/arch/arm64/boot/dts/rockchip/rk3568m-serdes-evb-display-dsi0-command2rgb-lp4x-v10.dts b/arch/arm64/boot/dts/rockchip/rk3568m-serdes-evb-display-dsi0-command2rgb-lp4x-v10.dts new file mode 100644 index 000000000000..1e49df3fcf06 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3568m-serdes-evb-display-dsi0-command2rgb-lp4x-v10.dts @@ -0,0 +1,137 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +#include +#include "rk3568m-serdes-evb-lp4x-v10.dtsi" +#include "rk3568-android.dtsi" + +&i2c1 { + status = "okay"; + clock-frequency = <10000>; +}; + +&dsi1 { + status = "okay"; +}; + +&dsi1_in_vp0 { + status = "okay"; +}; + +&dsi1_in_vp1 { + status = "disabled"; +}; + +&dsi1_panel { + status = "okay"; + dsi,flags = <(MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET | + MIPI_DSI_CLOCK_NON_CONTINUOUS)>; + dsi,format = ; + dsi,lanes = <4>; + + panel-init-sequence = []; + panel-exit-sequence = []; +}; + +&dsi1_timing0 { + clock-frequency = <50000000>; + hactive = <1024>; + vactive = <600>; + hfront-porch = <160>; + hsync-len = <20>; + hback-porch = <140>; + vfront-porch = <12>; + vsync-len = <3>; + vback-porch = <20>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <1>; +}; + +&video_phy1 { + status = "okay"; +}; + +&rgb { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + rgb_out_rkx110_x120: endpoint { + remote-endpoint = <&rkx110_x120_in_rgb>; + }; + }; + }; +}; + +&rgb_in_vp2 { + status = "okay"; +}; + +&rkx110_reset_gpio { + rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; +}; + +&rkx110_x120 { + enable-gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&rkx110_reset_gpio>; +}; + +&serdes_timing0 { + clock-frequency = <50000000>; + hactive = <1024>; + vactive = <600>; + hfront-porch = <160>; + hsync-len = <20>; + hback-porch = <140>; + vfront-porch = <12>; + vsync-len = <3>; + vback-porch = <20>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <1>; +}; + +&serdes_panel { + dsi-rx,lanes = <4>; + //dsi-rx,video-mode; + local-port0 = ; + remote0-port0 = ; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + rkx110_x120_in_rgb: endpoint { + remote-endpoint = <&rgb_out_rkx110_x120>; + }; + }; + }; +}; + +/* vp0 for HDMI, vp2 for rgb */ +&vp0 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER0 | 1 << ROCKCHIP_VOP2_ESMART0 | + 1 << ROCKCHIP_VOP2_SMART0)>; + rockchip,primary-plane = ; +}; + +&vp2 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER1 | 1 << ROCKCHIP_VOP2_ESMART1 | + 1 << ROCKCHIP_VOP2_SMART1)>; + rockchip,primary-plane = ; +}; + diff --git a/arch/arm64/boot/dts/rockchip/rk3568m-serdes-evb-display-dsi1-command2dsi-lp4x-v10.dts b/arch/arm64/boot/dts/rockchip/rk3568m-serdes-evb-display-dsi1-command2dsi-lp4x-v10.dts new file mode 100644 index 000000000000..52500b6c185c --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3568m-serdes-evb-display-dsi1-command2dsi-lp4x-v10.dts @@ -0,0 +1,409 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +#include +#include "rk3568m-serdes-evb-lp4x-v10.dtsi" +#include "rk3568-android.dtsi" + +&i2c1 { + status = "okay"; + clock-frequency = <10000>; +}; + +&dsi0 { + status = "okay"; +}; + +&dsi0_in_vp0 { + status = "okay"; +}; + +&dsi0_in_vp1 { + status = "disabled"; +}; + +&dsi0_panel { + status = "okay"; + dsi,flags = <(MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET | + MIPI_DSI_CLOCK_NON_CONTINUOUS)>; + dsi,format = ; + dsi,lanes = <4>; + + panel-init-sequence = []; + panel-exit-sequence = []; +}; + +&dsi0_timing0 { + clock-frequency = <132000000>; + hactive = <1080>; + vactive = <1920>; + hfront-porch = <15>; + hsync-len = <2>; + hback-porch = <30>; + vfront-porch = <15>; + vsync-len = <2>; + vback-porch = <15>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <1>; +}; + +&video_phy0 { + status = "okay"; +}; + +&rgb { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + rgb_out_rkx110_x120: endpoint { + remote-endpoint = <&rkx110_x120_in_rgb>; + }; + }; + }; +}; + +&rgb_in_vp2 { + status = "okay"; +}; + +&rkx110_reset_gpio { + rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; +}; + +&rkx110_x120 { + enable-gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&rkx110_reset_gpio>; +}; + +&serdes_timing0 { + clock-frequency = <132000000>; + hactive = <1080>; + vactive = <1920>; + hfront-porch = <15>; + hsync-len = <2>; + hback-porch = <30>; + vfront-porch = <15>; + vsync-len = <2>; + vback-porch = <15>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <1>; +}; + +&serdes_panel { + dsi-rx,lanes = <4>; + //dsi-rx,video-mode; + local-port0 = ; + remote0-port0 = ; + dsi-tx,format = "rgb888"; + dsi-tx,lanes = <4>; + dsi-tx,video-mode; + + panel-init-sequence = [ + 23 00 02 FE 21 + 23 00 02 04 00 + 23 00 02 00 64 + 23 00 02 2A 00 + 23 00 02 26 64 + 23 00 02 54 00 + 23 00 02 50 64 + 23 00 02 7B 00 + 23 00 02 77 64 + 23 00 02 A2 00 + 23 00 02 9D 64 + 23 00 02 C9 00 + 23 00 02 C5 64 + 23 00 02 01 71 + 23 00 02 27 71 + 23 00 02 51 71 + 23 00 02 78 71 + 23 00 02 9E 71 + 23 00 02 C6 71 + 23 00 02 02 89 + 23 00 02 28 89 + 23 00 02 52 89 + 23 00 02 79 89 + 23 00 02 9F 89 + 23 00 02 C7 89 + 23 00 02 03 9E + 23 00 02 29 9E + 23 00 02 53 9E + 23 00 02 7A 9E + 23 00 02 A0 9E + 23 00 02 C8 9E + 23 00 02 09 00 + 23 00 02 05 B0 + 23 00 02 31 00 + 23 00 02 2B B0 + 23 00 02 5A 00 + 23 00 02 55 B0 + 23 00 02 80 00 + 23 00 02 7C B0 + 23 00 02 A7 00 + 23 00 02 A3 B0 + 23 00 02 CE 00 + 23 00 02 CA B0 + 23 00 02 06 C0 + 23 00 02 2D C0 + 23 00 02 56 C0 + 23 00 02 7D C0 + 23 00 02 A4 C0 + 23 00 02 CB C0 + 23 00 02 07 CF + 23 00 02 2F CF + 23 00 02 58 CF + 23 00 02 7E CF + 23 00 02 A5 CF + 23 00 02 CC CF + 23 00 02 08 DD + 23 00 02 30 DD + 23 00 02 59 DD + 23 00 02 7F DD + 23 00 02 A6 DD + 23 00 02 CD DD + 23 00 02 0E 15 + 23 00 02 0A E9 + 23 00 02 36 15 + 23 00 02 32 E9 + 23 00 02 5F 15 + 23 00 02 5B E9 + 23 00 02 85 15 + 23 00 02 81 E9 + 23 00 02 AD 15 + 23 00 02 A9 E9 + 23 00 02 D3 15 + 23 00 02 CF E9 + 23 00 02 0B 14 + 23 00 02 33 14 + 23 00 02 5C 14 + 23 00 02 82 14 + 23 00 02 AA 14 + 23 00 02 D0 14 + 23 00 02 0C 36 + 23 00 02 34 36 + 23 00 02 5D 36 + 23 00 02 83 36 + 23 00 02 AB 36 + 23 00 02 D1 36 + 23 00 02 0D 6B + 23 00 02 35 6B + 23 00 02 5E 6B + 23 00 02 84 6B + 23 00 02 AC 6B + 23 00 02 D2 6B + 23 00 02 13 5A + 23 00 02 0F 94 + 23 00 02 3B 5A + 23 00 02 37 94 + 23 00 02 64 5A + 23 00 02 60 94 + 23 00 02 8A 5A + 23 00 02 86 94 + 23 00 02 B2 5A + 23 00 02 AE 94 + 23 00 02 D8 5A + 23 00 02 D4 94 + 23 00 02 10 D1 + 23 00 02 38 D1 + 23 00 02 61 D1 + 23 00 02 87 D1 + 23 00 02 AF D1 + 23 00 02 D5 D1 + 23 00 02 11 04 + 23 00 02 39 04 + 23 00 02 62 04 + 23 00 02 88 04 + 23 00 02 B0 04 + 23 00 02 D6 04 + 23 00 02 12 05 + 23 00 02 3A 05 + 23 00 02 63 05 + 23 00 02 89 05 + 23 00 02 B1 05 + 23 00 02 D7 05 + 23 00 02 18 AA + 23 00 02 14 36 + 23 00 02 42 AA + 23 00 02 3D 36 + 23 00 02 69 AA + 23 00 02 65 36 + 23 00 02 8F AA + 23 00 02 8B 36 + 23 00 02 B7 AA + 23 00 02 B3 36 + 23 00 02 DD AA + 23 00 02 D9 36 + 23 00 02 15 74 + 23 00 02 3F 74 + 23 00 02 66 74 + 23 00 02 8C 74 + 23 00 02 B4 74 + 23 00 02 DA 74 + 23 00 02 16 9F + 23 00 02 40 9F + 23 00 02 67 9F + 23 00 02 8D 9F + 23 00 02 B5 9F + 23 00 02 DB 9F + 23 00 02 17 DC + 23 00 02 41 DC + 23 00 02 68 DC + 23 00 02 8E DC + 23 00 02 B6 DC + 23 00 02 DC DC + 23 00 02 1D FF + 23 00 02 19 03 + 23 00 02 47 FF + 23 00 02 43 03 + 23 00 02 6E FF + 23 00 02 6A 03 + 23 00 02 94 FF + 23 00 02 90 03 + 23 00 02 BC FF + 23 00 02 B8 03 + 23 00 02 E2 FF + 23 00 02 DE 03 + 23 00 02 1A 35 + 23 00 02 44 35 + 23 00 02 6B 35 + 23 00 02 91 35 + 23 00 02 B9 35 + 23 00 02 DF 35 + 23 00 02 1B 45 + 23 00 02 45 45 + 23 00 02 6C 45 + 23 00 02 92 45 + 23 00 02 BA 45 + 23 00 02 E0 45 + 23 00 02 1C 55 + 23 00 02 46 55 + 23 00 02 6D 55 + 23 00 02 93 55 + 23 00 02 BB 55 + 23 00 02 E1 55 + 23 00 02 22 FF + 23 00 02 1E 68 + 23 00 02 4C FF + 23 00 02 48 68 + 23 00 02 73 FF + 23 00 02 6F 68 + 23 00 02 99 FF + 23 00 02 95 68 + 23 00 02 C1 FF + 23 00 02 BD 68 + 23 00 02 E7 FF + 23 00 02 E3 68 + 23 00 02 1F 7E + 23 00 02 49 7E + 23 00 02 70 7E + 23 00 02 96 7E + 23 00 02 BE 7E + 23 00 02 E4 7E + 23 00 02 20 97 + 23 00 02 4A 97 + 23 00 02 71 97 + 23 00 02 97 97 + 23 00 02 BF 97 + 23 00 02 E5 97 + 23 00 02 21 B5 + 23 00 02 4B B5 + 23 00 02 72 B5 + 23 00 02 98 B5 + 23 00 02 C0 B5 + 23 00 02 E6 B5 + 23 00 02 25 F0 + 23 00 02 23 E8 + 23 00 02 4F F0 + 23 00 02 4D E8 + 23 00 02 76 F0 + 23 00 02 74 E8 + 23 00 02 9C F0 + 23 00 02 9A E8 + 23 00 02 C4 F0 + 23 00 02 C2 E8 + 23 00 02 EA F0 + 23 00 02 E8 E8 + 23 00 02 24 FF + 23 00 02 4E FF + 23 00 02 75 FF + 23 00 02 9B FF + 23 00 02 C3 FF + 23 00 02 E9 FF + 23 00 02 FE 3D + 23 00 02 00 04 + 23 00 02 FE 23 + 23 00 02 08 82 + 23 00 02 0A 00 + 23 00 02 0B 00 + 23 00 02 0C 01 + 23 00 02 16 00 + 23 00 02 18 02 + 23 00 02 1B 04 + 23 00 02 19 04 + 23 00 02 1C 81 + 23 00 02 1F 00 + 23 00 02 20 03 + 23 00 02 23 04 + 23 00 02 21 01 + 23 00 02 54 63 + 23 00 02 55 54 + 23 00 02 6E 45 + 23 00 02 6D 36 + 23 00 02 FE 3D + 23 00 02 55 78 + 23 00 02 FE 20 + 23 00 02 26 30 + 23 00 02 FE 3D + 23 00 02 20 71 + 23 00 02 50 8F + 23 00 02 51 8F + 23 00 02 FE 00 + 23 00 02 35 00 + 05 78 01 11 + 05 1E 01 29 + ]; + + panel-exit-sequence = [ + 05 00 01 28 + 05 00 01 10 + ]; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + rkx110_x120_in_rgb: endpoint { + remote-endpoint = <&rgb_out_rkx110_x120>; + }; + }; + }; +}; + +/* vp0 for HDMI, vp2 for rgb */ +&vp0 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER0 | 1 << ROCKCHIP_VOP2_ESMART0 | + 1 << ROCKCHIP_VOP2_SMART0)>; + rockchip,primary-plane = ; +}; + +&vp2 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER1 | 1 << ROCKCHIP_VOP2_ESMART1 | + 1 << ROCKCHIP_VOP2_SMART1)>; + rockchip,primary-plane = ; +}; + diff --git a/arch/arm64/boot/dts/rockchip/rk3568m-serdes-evb-display-dsi1-command2lvds0-lp4x-v10.dts b/arch/arm64/boot/dts/rockchip/rk3568m-serdes-evb-display-dsi1-command2lvds0-lp4x-v10.dts new file mode 100644 index 000000000000..6a8c5a2ddf12 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3568m-serdes-evb-display-dsi1-command2lvds0-lp4x-v10.dts @@ -0,0 +1,137 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +#include +#include "rk3568m-serdes-evb-lp4x-v10.dtsi" +#include "rk3568-android.dtsi" + +&i2c1 { + status = "okay"; + clock-frequency = <10000>; +}; + +&dsi0 { + status = "okay"; +}; + +&dsi0_in_vp0 { + status = "okay"; +}; + +&dsi0_in_vp1 { + status = "disabled"; +}; + +&dsi0_panel { + status = "okay"; + dsi,flags = <(MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET | + MIPI_DSI_CLOCK_NON_CONTINUOUS)>; + dsi,format = ; + dsi,lanes = <4>; + + panel-init-sequence = []; + panel-exit-sequence = []; +}; + +&dsi0_timing0 { + clock-frequency = <50000000>; + hactive = <1024>; + vactive = <600>; + hfront-porch = <160>; + hsync-len = <20>; + hback-porch = <140>; + vfront-porch = <12>; + vsync-len = <3>; + vback-porch = <20>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <1>; +}; + +&video_phy0 { + status = "okay"; +}; + +&rgb { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + rgb_out_rkx110_x120: endpoint { + remote-endpoint = <&rkx110_x120_in_rgb>; + }; + }; + }; +}; + +&rgb_in_vp2 { + status = "okay"; +}; + +&rkx110_reset_gpio { + rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; +}; + +&rkx110_x120 { + enable-gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&rkx110_reset_gpio>; +}; + +&serdes_timing0 { + clock-frequency = <50000000>; + hactive = <1024>; + vactive = <600>; + hfront-porch = <160>; + hsync-len = <20>; + hback-porch = <140>; + vfront-porch = <12>; + vsync-len = <3>; + vback-porch = <20>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <1>; +}; + +&serdes_panel { + dsi-rx,lanes = <4>; + //dsi-rx,video-mode; + local-port0 = ; + remote0-port0 = ; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + rkx110_x120_in_rgb: endpoint { + remote-endpoint = <&rgb_out_rkx110_x120>; + }; + }; + }; +}; + +/* vp0 for HDMI, vp2 for rgb */ +&vp0 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER0 | 1 << ROCKCHIP_VOP2_ESMART0 | + 1 << ROCKCHIP_VOP2_SMART0)>; + rockchip,primary-plane = ; +}; + +&vp2 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER1 | 1 << ROCKCHIP_VOP2_ESMART1 | + 1 << ROCKCHIP_VOP2_SMART1)>; + rockchip,primary-plane = ; +}; + diff --git a/arch/arm64/boot/dts/rockchip/rk3568m-serdes-evb-display-dsi1-command2rgb-lp4x-v10.dts b/arch/arm64/boot/dts/rockchip/rk3568m-serdes-evb-display-dsi1-command2rgb-lp4x-v10.dts new file mode 100644 index 000000000000..4a79bfb844b3 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3568m-serdes-evb-display-dsi1-command2rgb-lp4x-v10.dts @@ -0,0 +1,137 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +#include +#include "rk3568m-serdes-evb-lp4x-v10.dtsi" +#include "rk3568-android.dtsi" + +&i2c1 { + status = "okay"; + clock-frequency = <10000>; +}; + +&dsi0 { + status = "okay"; +}; + +&dsi0_in_vp0 { + status = "okay"; +}; + +&dsi0_in_vp1 { + status = "disabled"; +}; + +&dsi0_panel { + status = "okay"; + dsi,flags = <(MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET | + MIPI_DSI_CLOCK_NON_CONTINUOUS)>; + dsi,format = ; + dsi,lanes = <4>; + + panel-init-sequence = []; + panel-exit-sequence = []; +}; + +&dsi0_timing0 { + clock-frequency = <50000000>; + hactive = <1024>; + vactive = <600>; + hfront-porch = <160>; + hsync-len = <20>; + hback-porch = <140>; + vfront-porch = <12>; + vsync-len = <3>; + vback-porch = <20>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <1>; +}; + +&video_phy0 { + status = "okay"; +}; + +&rgb { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + rgb_out_rkx110_x120: endpoint { + remote-endpoint = <&rkx110_x120_in_rgb>; + }; + }; + }; +}; + +&rgb_in_vp2 { + status = "okay"; +}; + +&rkx110_reset_gpio { + rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; +}; + +&rkx110_x120 { + enable-gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&rkx110_reset_gpio>; +}; + +&serdes_timing0 { + clock-frequency = <50000000>; + hactive = <1024>; + vactive = <600>; + hfront-porch = <160>; + hsync-len = <20>; + hback-porch = <140>; + vfront-porch = <12>; + vsync-len = <3>; + vback-porch = <20>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <1>; +}; + +&serdes_panel { + dsi-rx,lanes = <4>; + //dsi-rx,video-mode; + local-port0 = ; + remote0-port0 = ; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + rkx110_x120_in_rgb: endpoint { + remote-endpoint = <&rgb_out_rkx110_x120>; + }; + }; + }; +}; + +/* vp0 for HDMI, vp2 for rgb */ +&vp0 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER0 | 1 << ROCKCHIP_VOP2_ESMART0 | + 1 << ROCKCHIP_VOP2_SMART0)>; + rockchip,primary-plane = ; +}; + +&vp2 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER1 | 1 << ROCKCHIP_VOP2_ESMART1 | + 1 << ROCKCHIP_VOP2_SMART1)>; + rockchip,primary-plane = ; +}; + diff --git a/arch/arm64/boot/dts/rockchip/rk3568m-serdes-evb-display-lvds2lvds-lp4x-v10.dts b/arch/arm64/boot/dts/rockchip/rk3568m-serdes-evb-display-lvds2lvds-lp4x-v10.dts new file mode 100644 index 000000000000..6bda338d374f --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3568m-serdes-evb-display-lvds2lvds-lp4x-v10.dts @@ -0,0 +1,96 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +#include +#include "rk3568m-serdes-evb-lp4x-v10.dtsi" +#include "rk3568-android.dtsi" + +&i2c1 { + status = "okay"; + clock-frequency = <10000>; +}; + +&lvds { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + lvds_out_rkx110_x120: endpoint { + remote-endpoint = <&rkx110_x120_in_lvds>; + }; + }; + }; +}; + +&lvds_in_vp2 { + status = "okay"; +}; + +&rkx110_x120 { + enable-gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&rkx110_reset_gpio>; +}; + +&serdes_timing0 { + clock-frequency = <50000000>; + hactive = <1024>; + vactive = <600>; + hfront-porch = <160>; + hsync-len = <20>; + hback-porch = <140>; + vfront-porch = <12>; + vsync-len = <3>; + vback-porch = <20>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <1>; +}; + +&serdes_panel { + local-port0 = ; + remote0-port0 = ; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + rkx110_x120_in_lvds: endpoint { + remote-endpoint = <&lvds_out_rkx110_x120>; + }; + }; + }; +}; + +&video_phy0 { + status = "okay"; +}; + +/* vp0 for HDMI, vp2 for rgb */ +&vp0 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER0 | 1 << ROCKCHIP_VOP2_ESMART0 | + 1 << ROCKCHIP_VOP2_SMART0)>; + rockchip,primary-plane = ; +}; + +&vp2 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER1 | 1 << ROCKCHIP_VOP2_ESMART1 | + 1 << ROCKCHIP_VOP2_SMART1)>; + rockchip,primary-plane = ; +}; + +&rkx110_reset_gpio { + rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; +}; + diff --git a/arch/arm64/boot/dts/rockchip/rk3568m-serdes-evb-display-lvds2rgb-lp4x-v10.dts b/arch/arm64/boot/dts/rockchip/rk3568m-serdes-evb-display-lvds2rgb-lp4x-v10.dts new file mode 100644 index 000000000000..291c5a385cec --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3568m-serdes-evb-display-lvds2rgb-lp4x-v10.dts @@ -0,0 +1,96 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +#include +#include "rk3568m-serdes-evb-lp4x-v10.dtsi" +#include "rk3568-android.dtsi" + +&i2c1 { + status = "okay"; + clock-frequency = <10000>; +}; + +&lvds { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + lvds_out_rkx110_x120: endpoint { + remote-endpoint = <&rkx110_x120_in_lvds>; + }; + }; + }; +}; + +&lvds_in_vp2 { + status = "okay"; +}; + +&rkx110_x120 { + enable-gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&rkx110_reset_gpio>; +}; + +&serdes_timing0 { + clock-frequency = <50000000>; + hactive = <1024>; + vactive = <600>; + hfront-porch = <160>; + hsync-len = <20>; + hback-porch = <140>; + vfront-porch = <12>; + vsync-len = <3>; + vback-porch = <20>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <1>; +}; + +&serdes_panel { + local-port0 = ; + remote0-port0 = ; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + rkx110_x120_in_lvds: endpoint { + remote-endpoint = <&lvds_out_rkx110_x120>; + }; + }; + }; +}; + +&video_phy0 { + status = "okay"; +}; + +/* vp0 for HDMI, vp2 for rgb */ +&vp0 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER0 | 1 << ROCKCHIP_VOP2_ESMART0 | + 1 << ROCKCHIP_VOP2_SMART0)>; + rockchip,primary-plane = ; +}; + +&vp2 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER1 | 1 << ROCKCHIP_VOP2_ESMART1 | + 1 << ROCKCHIP_VOP2_SMART1)>; + rockchip,primary-plane = ; +}; + +&rkx110_reset_gpio { + rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; +}; + diff --git a/arch/arm64/boot/dts/rockchip/rk3568m-serdes-evb-display-rgb2dsi-lp4x-v10.dts b/arch/arm64/boot/dts/rockchip/rk3568m-serdes-evb-display-rgb2dsi-lp4x-v10.dts new file mode 100644 index 000000000000..3c39e835e28f --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3568m-serdes-evb-display-rgb2dsi-lp4x-v10.dts @@ -0,0 +1,345 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +#include +#include "rk3568m-serdes-evb-lp4x-v10.dtsi" +#include "rk3568-android.dtsi" + +&i2c1 { + status = "okay"; + clock-frequency = <10000>; +}; + +&rgb { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + rgb_out_rkx110_x120: endpoint { + remote-endpoint = <&rkx110_x120_in_rgb>; + }; + }; + }; +}; + +&rgb_in_vp2 { + status = "okay"; +}; + +&rkx110_x120 { + enable-gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio2 RK_PA2 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&rkx110_reset_gpio>; +}; + +&serdes_panel { + local-port0 = ; + remote0-port0 = ; + + dsi-tx,format = "rgb888"; + dsi-tx,lanes = <4>; + dsi-tx,video-mode; + + panel-init-sequence = [ + 23 00 02 FE 21 + 23 00 02 04 00 + 23 00 02 00 64 + 23 00 02 2A 00 + 23 00 02 26 64 + 23 00 02 54 00 + 23 00 02 50 64 + 23 00 02 7B 00 + 23 00 02 77 64 + 23 00 02 A2 00 + 23 00 02 9D 64 + 23 00 02 C9 00 + 23 00 02 C5 64 + 23 00 02 01 71 + 23 00 02 27 71 + 23 00 02 51 71 + 23 00 02 78 71 + 23 00 02 9E 71 + 23 00 02 C6 71 + 23 00 02 02 89 + 23 00 02 28 89 + 23 00 02 52 89 + 23 00 02 79 89 + 23 00 02 9F 89 + 23 00 02 C7 89 + 23 00 02 03 9E + 23 00 02 29 9E + 23 00 02 53 9E + 23 00 02 7A 9E + 23 00 02 A0 9E + 23 00 02 C8 9E + 23 00 02 09 00 + 23 00 02 05 B0 + 23 00 02 31 00 + 23 00 02 2B B0 + 23 00 02 5A 00 + 23 00 02 55 B0 + 23 00 02 80 00 + 23 00 02 7C B0 + 23 00 02 A7 00 + 23 00 02 A3 B0 + 23 00 02 CE 00 + 23 00 02 CA B0 + 23 00 02 06 C0 + 23 00 02 2D C0 + 23 00 02 56 C0 + 23 00 02 7D C0 + 23 00 02 A4 C0 + 23 00 02 CB C0 + 23 00 02 07 CF + 23 00 02 2F CF + 23 00 02 58 CF + 23 00 02 7E CF + 23 00 02 A5 CF + 23 00 02 CC CF + 23 00 02 08 DD + 23 00 02 30 DD + 23 00 02 59 DD + 23 00 02 7F DD + 23 00 02 A6 DD + 23 00 02 CD DD + 23 00 02 0E 15 + 23 00 02 0A E9 + 23 00 02 36 15 + 23 00 02 32 E9 + 23 00 02 5F 15 + 23 00 02 5B E9 + 23 00 02 85 15 + 23 00 02 81 E9 + 23 00 02 AD 15 + 23 00 02 A9 E9 + 23 00 02 D3 15 + 23 00 02 CF E9 + 23 00 02 0B 14 + 23 00 02 33 14 + 23 00 02 5C 14 + 23 00 02 82 14 + 23 00 02 AA 14 + 23 00 02 D0 14 + 23 00 02 0C 36 + 23 00 02 34 36 + 23 00 02 5D 36 + 23 00 02 83 36 + 23 00 02 AB 36 + 23 00 02 D1 36 + 23 00 02 0D 6B + 23 00 02 35 6B + 23 00 02 5E 6B + 23 00 02 84 6B + 23 00 02 AC 6B + 23 00 02 D2 6B + 23 00 02 13 5A + 23 00 02 0F 94 + 23 00 02 3B 5A + 23 00 02 37 94 + 23 00 02 64 5A + 23 00 02 60 94 + 23 00 02 8A 5A + 23 00 02 86 94 + 23 00 02 B2 5A + 23 00 02 AE 94 + 23 00 02 D8 5A + 23 00 02 D4 94 + 23 00 02 10 D1 + 23 00 02 38 D1 + 23 00 02 61 D1 + 23 00 02 87 D1 + 23 00 02 AF D1 + 23 00 02 D5 D1 + 23 00 02 11 04 + 23 00 02 39 04 + 23 00 02 62 04 + 23 00 02 88 04 + 23 00 02 B0 04 + 23 00 02 D6 04 + 23 00 02 12 05 + 23 00 02 3A 05 + 23 00 02 63 05 + 23 00 02 89 05 + 23 00 02 B1 05 + 23 00 02 D7 05 + 23 00 02 18 AA + 23 00 02 14 36 + 23 00 02 42 AA + 23 00 02 3D 36 + 23 00 02 69 AA + 23 00 02 65 36 + 23 00 02 8F AA + 23 00 02 8B 36 + 23 00 02 B7 AA + 23 00 02 B3 36 + 23 00 02 DD AA + 23 00 02 D9 36 + 23 00 02 15 74 + 23 00 02 3F 74 + 23 00 02 66 74 + 23 00 02 8C 74 + 23 00 02 B4 74 + 23 00 02 DA 74 + 23 00 02 16 9F + 23 00 02 40 9F + 23 00 02 67 9F + 23 00 02 8D 9F + 23 00 02 B5 9F + 23 00 02 DB 9F + 23 00 02 17 DC + 23 00 02 41 DC + 23 00 02 68 DC + 23 00 02 8E DC + 23 00 02 B6 DC + 23 00 02 DC DC + 23 00 02 1D FF + 23 00 02 19 03 + 23 00 02 47 FF + 23 00 02 43 03 + 23 00 02 6E FF + 23 00 02 6A 03 + 23 00 02 94 FF + 23 00 02 90 03 + 23 00 02 BC FF + 23 00 02 B8 03 + 23 00 02 E2 FF + 23 00 02 DE 03 + 23 00 02 1A 35 + 23 00 02 44 35 + 23 00 02 6B 35 + 23 00 02 91 35 + 23 00 02 B9 35 + 23 00 02 DF 35 + 23 00 02 1B 45 + 23 00 02 45 45 + 23 00 02 6C 45 + 23 00 02 92 45 + 23 00 02 BA 45 + 23 00 02 E0 45 + 23 00 02 1C 55 + 23 00 02 46 55 + 23 00 02 6D 55 + 23 00 02 93 55 + 23 00 02 BB 55 + 23 00 02 E1 55 + 23 00 02 22 FF + 23 00 02 1E 68 + 23 00 02 4C FF + 23 00 02 48 68 + 23 00 02 73 FF + 23 00 02 6F 68 + 23 00 02 99 FF + 23 00 02 95 68 + 23 00 02 C1 FF + 23 00 02 BD 68 + 23 00 02 E7 FF + 23 00 02 E3 68 + 23 00 02 1F 7E + 23 00 02 49 7E + 23 00 02 70 7E + 23 00 02 96 7E + 23 00 02 BE 7E + 23 00 02 E4 7E + 23 00 02 20 97 + 23 00 02 4A 97 + 23 00 02 71 97 + 23 00 02 97 97 + 23 00 02 BF 97 + 23 00 02 E5 97 + 23 00 02 21 B5 + 23 00 02 4B B5 + 23 00 02 72 B5 + 23 00 02 98 B5 + 23 00 02 C0 B5 + 23 00 02 E6 B5 + 23 00 02 25 F0 + 23 00 02 23 E8 + 23 00 02 4F F0 + 23 00 02 4D E8 + 23 00 02 76 F0 + 23 00 02 74 E8 + 23 00 02 9C F0 + 23 00 02 9A E8 + 23 00 02 C4 F0 + 23 00 02 C2 E8 + 23 00 02 EA F0 + 23 00 02 E8 E8 + 23 00 02 24 FF + 23 00 02 4E FF + 23 00 02 75 FF + 23 00 02 9B FF + 23 00 02 C3 FF + 23 00 02 E9 FF + 23 00 02 FE 3D + 23 00 02 00 04 + 23 00 02 FE 23 + 23 00 02 08 82 + 23 00 02 0A 00 + 23 00 02 0B 00 + 23 00 02 0C 01 + 23 00 02 16 00 + 23 00 02 18 02 + 23 00 02 1B 04 + 23 00 02 19 04 + 23 00 02 1C 81 + 23 00 02 1F 00 + 23 00 02 20 03 + 23 00 02 23 04 + 23 00 02 21 01 + 23 00 02 54 63 + 23 00 02 55 54 + 23 00 02 6E 45 + 23 00 02 6D 36 + 23 00 02 FE 3D + 23 00 02 55 78 + 23 00 02 FE 20 + 23 00 02 26 30 + 23 00 02 FE 3D + 23 00 02 20 71 + 23 00 02 50 8F + 23 00 02 51 8F + 23 00 02 FE 00 + 23 00 02 35 00 + 05 78 01 11 + 05 1E 01 29 + ]; + + panel-exit-sequence = [ + 05 00 01 28 + 05 00 01 10 + ]; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + rkx110_x120_in_rgb: endpoint { + remote-endpoint = <&rgb_out_rkx110_x120>; + }; + }; + }; +}; + +/* vp0 for HDMI, vp2 for rgb */ +&vp0 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER0 | 1 << ROCKCHIP_VOP2_ESMART0 | + 1 << ROCKCHIP_VOP2_SMART0)>; + rockchip,primary-plane = ; +}; + +&vp2 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER1 | 1 << ROCKCHIP_VOP2_ESMART1 | + 1 << ROCKCHIP_VOP2_SMART1)>; + rockchip,primary-plane = ; +}; + diff --git a/arch/arm64/boot/dts/rockchip/rk3568m-serdes-evb-display-rgb2lvds-lp4x-v10.dts b/arch/arm64/boot/dts/rockchip/rk3568m-serdes-evb-display-rgb2lvds-lp4x-v10.dts new file mode 100644 index 000000000000..27837eb535d9 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3568m-serdes-evb-display-rgb2lvds-lp4x-v10.dts @@ -0,0 +1,88 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +#include +#include "rk3568m-serdes-evb-lp4x-v10.dtsi" +#include "rk3568-android.dtsi" + +&i2c1 { + status = "okay"; + clock-frequency = <10000>; +}; + +&rgb { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + rgb_out_rkx110_x120: endpoint { + remote-endpoint = <&rkx110_x120_in_rgb>; + }; + }; + }; +}; + +&rgb_in_vp2 { + status = "okay"; +}; + +&rkx110_x120 { + enable-gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio2 RK_PA2 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&rkx110_reset_gpio>; +}; + +&serdes_timing0 { + clock-frequency = <50000000>; + hactive = <1024>; + vactive = <600>; + hfront-porch = <160>; + hsync-len = <20>; + hback-porch = <140>; + vfront-porch = <12>; + vsync-len = <3>; + vback-porch = <20>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <1>; +}; + +&serdes_panel { + local-port0 = ; + remote0-port0 = ; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + rkx110_x120_in_rgb: endpoint { + remote-endpoint = <&rgb_out_rkx110_x120>; + }; + }; + }; +}; + +/* vp0 for HDMI, vp2 for rgb */ +&vp0 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER0 | 1 << ROCKCHIP_VOP2_ESMART0 | + 1 << ROCKCHIP_VOP2_SMART0)>; + rockchip,primary-plane = ; +}; + +&vp2 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER1 | 1 << ROCKCHIP_VOP2_ESMART1 | + 1 << ROCKCHIP_VOP2_SMART1)>; + rockchip,primary-plane = ; +}; + diff --git a/arch/arm64/boot/dts/rockchip/rk3568m-serdes-evb-display-rgb2rgb-lp4x-v10.dts b/arch/arm64/boot/dts/rockchip/rk3568m-serdes-evb-display-rgb2rgb-lp4x-v10.dts new file mode 100644 index 000000000000..706ad30563a6 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3568m-serdes-evb-display-rgb2rgb-lp4x-v10.dts @@ -0,0 +1,88 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +#include +#include "rk3568m-serdes-evb-lp4x-v10.dtsi" +#include "rk3568-android.dtsi" + +&i2c1 { + status = "okay"; + clock-frequency = <10000>; +}; + +&rgb { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + rgb_out_rkx110_x120: endpoint { + remote-endpoint = <&rkx110_x120_in_rgb>; + }; + }; + }; +}; + +&rgb_in_vp2 { + status = "okay"; +}; + +&rkx110_x120 { + enable-gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio2 RK_PA2 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&rkx110_reset_gpio>; +}; + +&serdes_timing0 { + clock-frequency = <50000000>; + hactive = <1024>; + vactive = <600>; + hfront-porch = <160>; + hsync-len = <20>; + hback-porch = <140>; + vfront-porch = <12>; + vsync-len = <3>; + vback-porch = <20>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <1>; +}; + +&serdes_panel { + local-port0 = ; + remote0-port0 = ; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + rkx110_x120_in_rgb: endpoint { + remote-endpoint = <&rgb_out_rkx110_x120>; + }; + }; + }; +}; + +/* vp0 for HDMI, vp2 for rgb */ +&vp0 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER0 | 1 << ROCKCHIP_VOP2_ESMART0 | + 1 << ROCKCHIP_VOP2_SMART0)>; + rockchip,primary-plane = ; +}; + +&vp2 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER1 | 1 << ROCKCHIP_VOP2_ESMART1 | + 1 << ROCKCHIP_VOP2_SMART1)>; + rockchip,primary-plane = ; +}; + diff --git a/arch/arm64/boot/dts/rockchip/rk3568m-serdes-evb-lp4x-v10-camera.dtsi b/arch/arm64/boot/dts/rockchip/rk3568m-serdes-evb-lp4x-v10-camera.dtsi new file mode 100644 index 000000000000..199c55ce54bf --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3568m-serdes-evb-lp4x-v10-camera.dtsi @@ -0,0 +1,195 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include +#include +#include +#include "rk3568.dtsi" +#include "rk3568-evb.dtsi" + +/ { + model = "Rockchip RK3568M SERDES EVB LP4X V10 Board"; + compatible = "rockchip,rk3568m-serdes-evb-lp4x-v10", "rockchip,rk3568"; + + vcc2v5_sys: vcc2v5-ddr { + compatible = "regulator-fixed"; + regulator-name = "vcc2v5-sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + vin-supply = <&vcc3v3_sys>; + }; + + vcc3v3_bu: vcc3v3-bu { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_bu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc5v0_sys>; + }; +}; + +/* + * pin conflict with i2c2 for serdes-debug + */ +>1x { + status = "disabled"; +}; + +&combphy0_us { + status = "okay"; +}; + +&combphy2_psq { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + gs_mxc6655xa: gs_mxc6655xa@15 { + status = "okay"; + compatible = "gs_mxc6655xa"; + pinctrl-names = "default"; + pinctrl-0 = <&mxc6655xa_irq_gpio>; + reg = <0x15>; + irq-gpio = <&gpio0 RK_PA4 IRQ_TYPE_LEVEL_LOW>; + irq_enable = <0>; + poll_delay_ms = <30>; + type = ; + power-off-in-suspend = <1>; + layout = <1>; + }; +}; + +&i2c3 { + status = "okay"; + clock-frequency = <100000>; + + rkx120_x110: rkx120_x110@54 { + compatible = "rockchip,rkx120"; + reg = <0x54>; + remote0-addr = <0x55>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + serdes_camera: serdes-camera { + compatible = "rockchip,serdes-camera"; + reg = <0>; + status = "okay"; + }; + }; +}; + +&i2c5 { + status = "disabled"; +}; + +&pinctrl { + mxc6655xa { + mxc6655xa_irq_gpio: mxc6655xa_irq_gpio { + rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + serdes { + rkx120_reset_gpio: rkx120-reset-gpio { + rockchip,pins = <2 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pmu_io_domains { + vccio6-supply = <&vcc_3v3>; +}; + +&pwm7 { + status = "disabled"; +}; + +&rk809_codec { + status = "disabled"; +}; + +&sdmmc0 { + status = "disabled"; +}; + +&sdmmc2 { + status = "disabled"; +}; + +&uart1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn>; +}; + +&wireless_wlan { + status = "disabled"; +}; + +&wireless_bluetooth { + status = "disabled"; +}; + +/* OTG0 */ +&combphy0_us { + rockchip,dis-u3otg0-port; + /* OTG and SATA0 not use combphy0_us, then disabled */ + status = "disabled"; +}; + +&u2phy0_otg { + vbus-supply = <&vcc5v0_otg>; + status = "okay"; +}; + +&usb2phy0 { + status = "okay"; +}; + +&usbdrd_dwc3 { + dr_mode = "otg"; + phys = <&u2phy0_otg>; + phy-names = "usb2-phy"; + extcon = <&usb2phy0>; + maximum-speed = "high-speed"; + snps,dis_u2_susphy_quirk; + status = "okay"; +}; + +&usbdrd30 { + status = "okay"; +}; + +/* HOST1 */ +&combphy1_usq { + status = "okay"; +}; + +&u2phy0_host { + phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&usb2phy0 { + status = "okay"; +}; + +&usbhost_dwc3 { + status = "okay"; +}; + +&usbhost30 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3568m-serdes-evb-lp4x-v10.dtsi b/arch/arm64/boot/dts/rockchip/rk3568m-serdes-evb-lp4x-v10.dtsi new file mode 100644 index 000000000000..78cb019fe9be --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3568m-serdes-evb-lp4x-v10.dtsi @@ -0,0 +1,211 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include +#include +#include +#include "rk3568.dtsi" +#include "rk3568-evb.dtsi" + +/ { + model = "Rockchip RK3568M SERDES EVB LP4X V10 Board"; + compatible = "rockchip,rk3568m-serdes-evb-lp4x-v10", "rockchip,rk3568"; + + vcc2v5_sys: vcc2v5-ddr { + compatible = "regulator-fixed"; + regulator-name = "vcc2v5-sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + vin-supply = <&vcc3v3_sys>; + }; + + vcc3v3_bu: vcc3v3-bu { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_bu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc5v0_sys>; + }; +}; + +&combphy0_us { + status = "okay"; +}; + +&combphy2_psq { + status = "okay"; +}; + +>1x { + status = "disabled"; +}; + +&i2c0 { + status = "okay"; + + gs_mxc6655xa: gs_mxc6655xa@15 { + status = "okay"; + compatible = "gs_mxc6655xa"; + pinctrl-names = "default"; + pinctrl-0 = <&mxc6655xa_irq_gpio>; + reg = <0x15>; + irq-gpio = <&gpio0 RK_PA4 IRQ_TYPE_LEVEL_LOW>; + irq_enable = <0>; + poll_delay_ms = <30>; + type = ; + power-off-in-suspend = <1>; + layout = <1>; + }; +}; + +&i2c5 { + status = "disabled"; +}; + +&pinctrl { + mxc6655xa { + mxc6655xa_irq_gpio: mxc6655xa_irq_gpio { + rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + serdes { + rkx110_reset_gpio: rkx110-reset-gpio { + rockchip,pins = <2 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pmu_io_domains { + vccio6-supply = <&vcc_3v3>; +}; + +&pwm7 { + status = "disabled"; +}; + +&rk809_codec { + status = "disabled"; +}; + +&sdmmc0 { + status = "disabled"; +}; + +&sdmmc2 { + status = "disabled"; +}; + +&uart1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn>; +}; + +&wireless_wlan { + status = "disabled"; +}; + +&wireless_bluetooth { + status = "disabled"; +}; + +/* OTG0 */ +&combphy0_us { + rockchip,dis-u3otg0-port; + /* OTG and SATA0 not use combphy0_us, then disabled */ + status = "disabled"; +}; + +&i2c1 { + status = "okay"; + clock-frequency = <100000>; + + rkx110_x120: rkx110-x120@55 { + compatible = "rockchip,rkx110"; + reg = <0x55>; + remote0-addr = <0x54>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + serdes_panel: serdes-panel { + compatible = "rockchip,serdes-panel"; + reg = <0>; + status = "okay"; + + display_timings0: display-timings { + native-mode = <&serdes_timing0>; + serdes_timing0: timing0 { + clock-frequency = <132000000>; + hactive = <1080>; + vactive = <1920>; + hfront-porch = <15>; + hsync-len = <2>; + hback-porch = <30>; + vfront-porch = <15>; + vsync-len = <2>; + vback-porch = <15>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <1>; + }; + }; + }; + }; +}; + +&u2phy0_otg { + vbus-supply = <&vcc5v0_otg>; + status = "okay"; +}; + +&usb2phy0 { + status = "okay"; +}; + +&usbdrd_dwc3 { + dr_mode = "otg"; + phys = <&u2phy0_otg>; + phy-names = "usb2-phy"; + extcon = <&usb2phy0>; + maximum-speed = "high-speed"; + snps,dis_u2_susphy_quirk; + status = "okay"; +}; + +&usbdrd30 { + status = "okay"; +}; + +/* HOST1 */ +&combphy1_usq { + status = "okay"; +}; + +&u2phy0_host { + phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&usb2phy0 { + status = "okay"; +}; + +&usbhost_dwc3 { + status = "okay"; +}; + +&usbhost30 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3568m-serdes-v1-evb-display-dsi0-command2dsi-lp4x-v10.dts b/arch/arm64/boot/dts/rockchip/rk3568m-serdes-v1-evb-display-dsi0-command2dsi-lp4x-v10.dts new file mode 100644 index 000000000000..c8344e1625d5 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3568m-serdes-v1-evb-display-dsi0-command2dsi-lp4x-v10.dts @@ -0,0 +1,397 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +#include +#include "rk3568m-serdes-v1-evb-lp4x-v10.dtsi" +#include "rk3568-android.dtsi" + +&backlight { + pwms = <&pwm4 0 25000 0>; + status = "okay"; +}; + +&i2c1 { + status = "okay"; + clock-frequency = <10000>; +}; + +&dsi1 { + status = "disabled"; +}; + +&dsi0_in_vp0 { + status = "okay"; +}; + +&dsi0_in_vp1 { + status = "disabled"; +}; + +/delete-node/ &dsi0_panel; + +&pwm4 { + pinctrl-names = "active"; + pinctrl-0 = <&pwm4_pins>; + status = "okay"; +}; + +&video_phy0 { + status = "okay"; +}; + +&dsi0 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi0_out_rkx110_x120: endpoint { + remote-endpoint = <&rkx110_x120_in_dsi0>; + }; + }; + }; +}; + +&rkx110_x120 { + pt-config { + rk-serdes,pt = , + , + ; + }; +}; + +&serdes_timing0 { + clock-frequency = <132000000>; + hactive = <1080>; + vactive = <1920>; + hfront-porch = <15>; + hsync-len = <2>; + hback-porch = <30>; + vfront-porch = <15>; + vsync-len = <2>; + vback-porch = <15>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <1>; +}; + +&serdes_panel { + dsi-rx,lanes = <4>; + //dsi-rx,video-mode; + local-port0 = ; + remote0-port0 = ; + dsi-tx,format = "rgb888"; + dsi-tx,lanes = <4>; + dsi-tx,video-mode; + + backlight = <&backlight>; + enable-gpios = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&panel_reset_ser0_gpio &panel_enable_ser0_gpio>; + + panel-init-sequence = [ + 23 00 02 FE 21 + 23 00 02 04 00 + 23 00 02 00 64 + 23 00 02 2A 00 + 23 00 02 26 64 + 23 00 02 54 00 + 23 00 02 50 64 + 23 00 02 7B 00 + 23 00 02 77 64 + 23 00 02 A2 00 + 23 00 02 9D 64 + 23 00 02 C9 00 + 23 00 02 C5 64 + 23 00 02 01 71 + 23 00 02 27 71 + 23 00 02 51 71 + 23 00 02 78 71 + 23 00 02 9E 71 + 23 00 02 C6 71 + 23 00 02 02 89 + 23 00 02 28 89 + 23 00 02 52 89 + 23 00 02 79 89 + 23 00 02 9F 89 + 23 00 02 C7 89 + 23 00 02 03 9E + 23 00 02 29 9E + 23 00 02 53 9E + 23 00 02 7A 9E + 23 00 02 A0 9E + 23 00 02 C8 9E + 23 00 02 09 00 + 23 00 02 05 B0 + 23 00 02 31 00 + 23 00 02 2B B0 + 23 00 02 5A 00 + 23 00 02 55 B0 + 23 00 02 80 00 + 23 00 02 7C B0 + 23 00 02 A7 00 + 23 00 02 A3 B0 + 23 00 02 CE 00 + 23 00 02 CA B0 + 23 00 02 06 C0 + 23 00 02 2D C0 + 23 00 02 56 C0 + 23 00 02 7D C0 + 23 00 02 A4 C0 + 23 00 02 CB C0 + 23 00 02 07 CF + 23 00 02 2F CF + 23 00 02 58 CF + 23 00 02 7E CF + 23 00 02 A5 CF + 23 00 02 CC CF + 23 00 02 08 DD + 23 00 02 30 DD + 23 00 02 59 DD + 23 00 02 7F DD + 23 00 02 A6 DD + 23 00 02 CD DD + 23 00 02 0E 15 + 23 00 02 0A E9 + 23 00 02 36 15 + 23 00 02 32 E9 + 23 00 02 5F 15 + 23 00 02 5B E9 + 23 00 02 85 15 + 23 00 02 81 E9 + 23 00 02 AD 15 + 23 00 02 A9 E9 + 23 00 02 D3 15 + 23 00 02 CF E9 + 23 00 02 0B 14 + 23 00 02 33 14 + 23 00 02 5C 14 + 23 00 02 82 14 + 23 00 02 AA 14 + 23 00 02 D0 14 + 23 00 02 0C 36 + 23 00 02 34 36 + 23 00 02 5D 36 + 23 00 02 83 36 + 23 00 02 AB 36 + 23 00 02 D1 36 + 23 00 02 0D 6B + 23 00 02 35 6B + 23 00 02 5E 6B + 23 00 02 84 6B + 23 00 02 AC 6B + 23 00 02 D2 6B + 23 00 02 13 5A + 23 00 02 0F 94 + 23 00 02 3B 5A + 23 00 02 37 94 + 23 00 02 64 5A + 23 00 02 60 94 + 23 00 02 8A 5A + 23 00 02 86 94 + 23 00 02 B2 5A + 23 00 02 AE 94 + 23 00 02 D8 5A + 23 00 02 D4 94 + 23 00 02 10 D1 + 23 00 02 38 D1 + 23 00 02 61 D1 + 23 00 02 87 D1 + 23 00 02 AF D1 + 23 00 02 D5 D1 + 23 00 02 11 04 + 23 00 02 39 04 + 23 00 02 62 04 + 23 00 02 88 04 + 23 00 02 B0 04 + 23 00 02 D6 04 + 23 00 02 12 05 + 23 00 02 3A 05 + 23 00 02 63 05 + 23 00 02 89 05 + 23 00 02 B1 05 + 23 00 02 D7 05 + 23 00 02 18 AA + 23 00 02 14 36 + 23 00 02 42 AA + 23 00 02 3D 36 + 23 00 02 69 AA + 23 00 02 65 36 + 23 00 02 8F AA + 23 00 02 8B 36 + 23 00 02 B7 AA + 23 00 02 B3 36 + 23 00 02 DD AA + 23 00 02 D9 36 + 23 00 02 15 74 + 23 00 02 3F 74 + 23 00 02 66 74 + 23 00 02 8C 74 + 23 00 02 B4 74 + 23 00 02 DA 74 + 23 00 02 16 9F + 23 00 02 40 9F + 23 00 02 67 9F + 23 00 02 8D 9F + 23 00 02 B5 9F + 23 00 02 DB 9F + 23 00 02 17 DC + 23 00 02 41 DC + 23 00 02 68 DC + 23 00 02 8E DC + 23 00 02 B6 DC + 23 00 02 DC DC + 23 00 02 1D FF + 23 00 02 19 03 + 23 00 02 47 FF + 23 00 02 43 03 + 23 00 02 6E FF + 23 00 02 6A 03 + 23 00 02 94 FF + 23 00 02 90 03 + 23 00 02 BC FF + 23 00 02 B8 03 + 23 00 02 E2 FF + 23 00 02 DE 03 + 23 00 02 1A 35 + 23 00 02 44 35 + 23 00 02 6B 35 + 23 00 02 91 35 + 23 00 02 B9 35 + 23 00 02 DF 35 + 23 00 02 1B 45 + 23 00 02 45 45 + 23 00 02 6C 45 + 23 00 02 92 45 + 23 00 02 BA 45 + 23 00 02 E0 45 + 23 00 02 1C 55 + 23 00 02 46 55 + 23 00 02 6D 55 + 23 00 02 93 55 + 23 00 02 BB 55 + 23 00 02 E1 55 + 23 00 02 22 FF + 23 00 02 1E 68 + 23 00 02 4C FF + 23 00 02 48 68 + 23 00 02 73 FF + 23 00 02 6F 68 + 23 00 02 99 FF + 23 00 02 95 68 + 23 00 02 C1 FF + 23 00 02 BD 68 + 23 00 02 E7 FF + 23 00 02 E3 68 + 23 00 02 1F 7E + 23 00 02 49 7E + 23 00 02 70 7E + 23 00 02 96 7E + 23 00 02 BE 7E + 23 00 02 E4 7E + 23 00 02 20 97 + 23 00 02 4A 97 + 23 00 02 71 97 + 23 00 02 97 97 + 23 00 02 BF 97 + 23 00 02 E5 97 + 23 00 02 21 B5 + 23 00 02 4B B5 + 23 00 02 72 B5 + 23 00 02 98 B5 + 23 00 02 C0 B5 + 23 00 02 E6 B5 + 23 00 02 25 F0 + 23 00 02 23 E8 + 23 00 02 4F F0 + 23 00 02 4D E8 + 23 00 02 76 F0 + 23 00 02 74 E8 + 23 00 02 9C F0 + 23 00 02 9A E8 + 23 00 02 C4 F0 + 23 00 02 C2 E8 + 23 00 02 EA F0 + 23 00 02 E8 E8 + 23 00 02 24 FF + 23 00 02 4E FF + 23 00 02 75 FF + 23 00 02 9B FF + 23 00 02 C3 FF + 23 00 02 E9 FF + 23 00 02 FE 3D + 23 00 02 00 04 + 23 00 02 FE 23 + 23 00 02 08 82 + 23 00 02 0A 00 + 23 00 02 0B 00 + 23 00 02 0C 01 + 23 00 02 16 00 + 23 00 02 18 02 + 23 00 02 1B 04 + 23 00 02 19 04 + 23 00 02 1C 81 + 23 00 02 1F 00 + 23 00 02 20 03 + 23 00 02 23 04 + 23 00 02 21 01 + 23 00 02 54 63 + 23 00 02 55 54 + 23 00 02 6E 45 + 23 00 02 6D 36 + 23 00 02 FE 3D + 23 00 02 55 78 + 23 00 02 FE 20 + 23 00 02 26 30 + 23 00 02 FE 3D + 23 00 02 20 71 + 23 00 02 50 8F + 23 00 02 51 8F + 23 00 02 FE 00 + 23 00 02 35 00 + 05 78 01 11 + 05 1E 01 29 + ]; + + panel-exit-sequence = [ + 05 00 01 28 + 05 00 01 10 + ]; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + rkx110_x120_in_dsi0: endpoint { + remote-endpoint = <&dsi0_out_rkx110_x120>; + }; + }; + }; +}; + +/* vp0 for HDMI, vp2 for rgb */ +&vp0 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER0 | 1 << ROCKCHIP_VOP2_ESMART0 | + 1 << ROCKCHIP_VOP2_SMART0)>; + rockchip,primary-plane = ; +}; + +&vp2 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER1 | 1 << ROCKCHIP_VOP2_ESMART1 | + 1 << ROCKCHIP_VOP2_SMART1)>; + rockchip,primary-plane = ; +}; + diff --git a/arch/arm64/boot/dts/rockchip/rk3568m-serdes-v1-evb-display-dsi0-command2dual_lvds-lp4x-v10.dts b/arch/arm64/boot/dts/rockchip/rk3568m-serdes-v1-evb-display-dsi0-command2dual_lvds-lp4x-v10.dts new file mode 100644 index 000000000000..111818c1c8b3 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3568m-serdes-v1-evb-display-dsi0-command2dual_lvds-lp4x-v10.dts @@ -0,0 +1,123 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +#include +#include "rk3568m-serdes-v1-evb-lp4x-v10.dtsi" +#include "rk3568-android.dtsi" + +&backlight { + pwms = <&pwm4 0 25000 0>; + status = "okay"; +}; + +&i2c1 { + status = "okay"; + clock-frequency = <10000>; +}; + +&dsi1 { + status = "disabled"; +}; + +&dsi0_in_vp0 { + status = "okay"; +}; + +&dsi0_in_vp1 { + status = "disabled"; +}; + +/delete-node/ &dsi0_panel; + +&pwm4 { + pinctrl-names = "active"; + pinctrl-0 = <&pwm4_pins>; + status = "okay"; +}; + +&video_phy0 { + status = "okay"; +}; + +&dsi0 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi0_out_rkx110_x120: endpoint { + remote-endpoint = <&rkx110_x120_in_dsi0>; + }; + }; + }; +}; + +&rkx110_x120 { + pt-config { + rk-serdes,pt = , + , + ; + }; +}; + +&serdes_timing0 { + clock-frequency = <148500000>; + hactive = <1920>; + vactive = <1080>; + hfront-porch = <88>; + hsync-len = <44>; + hback-porch = <148>; + vfront-porch = <4>; + vsync-len = <5>; + vback-porch = <36>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <1>; +}; + +&serdes_panel { + local-port0 = ; + remote0-port0 = ; + + backlight = <&backlight>; + enable-gpios = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&panel_reset_ser0_gpio &panel_enable_ser0_gpio>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + rkx110_x120_in_dsi0: endpoint { + remote-endpoint = <&dsi0_out_rkx110_x120>; + }; + }; + }; +}; + +/* vp0 for HDMI, vp2 for rgb */ +&vp0 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER0 | 1 << ROCKCHIP_VOP2_ESMART0 | + 1 << ROCKCHIP_VOP2_SMART0)>; + rockchip,primary-plane = ; +}; + +&vp2 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER1 | 1 << ROCKCHIP_VOP2_ESMART1 | + 1 << ROCKCHIP_VOP2_SMART1)>; + rockchip,primary-plane = ; +}; + diff --git a/arch/arm64/boot/dts/rockchip/rk3568m-serdes-v1-evb-display-dsi0-command2lvds0-lp4x-v10.dts b/arch/arm64/boot/dts/rockchip/rk3568m-serdes-v1-evb-display-dsi0-command2lvds0-lp4x-v10.dts new file mode 100644 index 000000000000..b0b1d405a342 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3568m-serdes-v1-evb-display-dsi0-command2lvds0-lp4x-v10.dts @@ -0,0 +1,123 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +#include +#include "rk3568m-serdes-v1-evb-lp4x-v10.dtsi" +#include "rk3568-android.dtsi" + +&backlight { + pwms = <&pwm4 0 25000 0>; + status = "okay"; +}; + +&i2c1 { + status = "okay"; + clock-frequency = <10000>; +}; + +&dsi1 { + status = "disabled"; +}; + +&dsi0_in_vp0 { + status = "okay"; +}; + +&dsi0_in_vp1 { + status = "disabled"; +}; + +/delete-node/ &dsi0_panel; + +&pwm4 { + pinctrl-names = "active"; + pinctrl-0 = <&pwm4_pins>; + status = "okay"; +}; + +&video_phy0 { + status = "okay"; +}; + +&dsi0 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi0_out_rkx110_x120: endpoint { + remote-endpoint = <&rkx110_x120_in_dsi0>; + }; + }; + }; +}; + +&rkx110_x120 { + pt-config { + rk-serdes,pt = , + , + ; + }; +}; + +&serdes_timing0 { + clock-frequency = <50000000>; + hactive = <1024>; + vactive = <600>; + hfront-porch = <160>; + hsync-len = <20>; + hback-porch = <140>; + vfront-porch = <12>; + vsync-len = <3>; + vback-porch = <20>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <1>; +}; + +&serdes_panel { + local-port0 = ; + remote0-port0 = ; + + backlight = <&backlight>; + enable-gpios = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&panel_reset_ser0_gpio &panel_enable_ser0_gpio>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + rkx110_x120_in_dsi0: endpoint { + remote-endpoint = <&dsi0_out_rkx110_x120>; + }; + }; + }; +}; + +/* vp0 for HDMI, vp2 for rgb */ +&vp0 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER0 | 1 << ROCKCHIP_VOP2_ESMART0 | + 1 << ROCKCHIP_VOP2_SMART0)>; + rockchip,primary-plane = ; +}; + +&vp2 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER1 | 1 << ROCKCHIP_VOP2_ESMART1 | + 1 << ROCKCHIP_VOP2_SMART1)>; + rockchip,primary-plane = ; +}; + diff --git a/arch/arm64/boot/dts/rockchip/rk3568m-serdes-v1-evb-display-dsi0-dsi1-command2dual_lvdsx2-lp4x-v10.dts b/arch/arm64/boot/dts/rockchip/rk3568m-serdes-v1-evb-display-dsi0-dsi1-command2dual_lvdsx2-lp4x-v10.dts new file mode 100644 index 000000000000..5017670a3623 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3568m-serdes-v1-evb-display-dsi0-dsi1-command2dual_lvdsx2-lp4x-v10.dts @@ -0,0 +1,165 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +#include +#include "rk3568m-serdes-v1-evb-lp4x-v10.dtsi" +#include "rk3568-android.dtsi" + +&backlight { + pwms = <&pwm4 0 25000 0>; + status = "okay"; +}; + +&i2c1 { + status = "okay"; + clock-frequency = <10000>; +}; + +&dsi1 { + status = "okay"; +}; + +&dsi0_in_vp0 { + status = "okay"; +}; + +&dsi0_in_vp1 { + status = "disabled"; +}; + +&dsi1_in_vp0 { + status = "disabled"; +}; + +&dsi1_in_vp1 { + status = "okay"; +}; + +&route_dsi1 { + status = "disabled"; + connect = <&vp1_out_dsi1>; +}; + +/delete-node/ &dsi0_panel; + +&dsi1_panel { + dsi,flags = <(MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; + panel-init-sequence = []; + panel-exit-sequence = []; +}; + +&disp_timings1 { + native-mode = <&dsi1_timing0>; + dsi1_timing0: timing0 { + clock-frequency = <148500000>; + hactive = <1920>; + vactive = <1080>; + hfront-porch = <140>; + hsync-len = <40>; + hback-porch = <100>; + vfront-porch = <15>; + vsync-len = <20>; + vback-porch = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <1>; + }; +}; + + +&pwm4 { + pinctrl-names = "active"; + pinctrl-0 = <&pwm4_pins>; + status = "okay"; +}; + +&video_phy0 { + status = "okay"; +}; + +&video_phy1 { + status = "okay"; +}; + +&dsi0 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi0_out_rkx110_x120: endpoint { + remote-endpoint = <&rkx110_x120_in_dsi0>; + }; + }; + }; +}; + +&rkx110_x120 { + remote1-addr = <0x54>; +}; + +&serdes_timing0 { + clock-frequency = <148500000>; + hactive = <1920>; + vactive = <1080>; + hfront-porch = <140>; + hsync-len = <40>; + hback-porch = <100>; + vfront-porch = <15>; + vsync-len = <20>; + vback-porch = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <1>; +}; + +&serdes_panel { + local-port0 = ; + local-port1 = ; + remote0-port0 = ; + remote1-port0 = ; + + backlight = <&backlight>; + enable-gpios = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&panel_reset_ser0_gpio &panel_enable_ser0_gpio>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + rkx110_x120_in_dsi0: endpoint { + remote-endpoint = <&dsi0_out_rkx110_x120>; + }; + }; + }; +}; + +/* vp0 for HDMI, vp2 for rgb */ +&vp0 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER1 | 1 << ROCKCHIP_VOP2_SMART1)>; + rockchip,primary-plane = ; +}; + +&vp1 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER0 | 1 << ROCKCHIP_VOP2_ESMART0 | + 1 << ROCKCHIP_VOP2_SMART0)>; + rockchip,primary-plane = ; +}; + +&vp2 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_ESMART1)>; + rockchip,primary-plane = ; +}; + diff --git a/arch/arm64/boot/dts/rockchip/rk3568m-serdes-v1-evb-display-dsi1-command2dsi-lp4x-v10.dts b/arch/arm64/boot/dts/rockchip/rk3568m-serdes-v1-evb-display-dsi1-command2dsi-lp4x-v10.dts new file mode 100644 index 000000000000..6f16477f420b --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3568m-serdes-v1-evb-display-dsi1-command2dsi-lp4x-v10.dts @@ -0,0 +1,397 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +#include +#include "rk3568m-serdes-v1-evb-lp4x-v10.dtsi" +#include "rk3568-android.dtsi" + +&backlight { + pwms = <&pwm4 0 25000 0>; + status = "okay"; +}; + +&i2c1 { + status = "okay"; + clock-frequency = <10000>; +}; + +&dsi0 { + status = "disabled"; +}; + +&dsi1_in_vp0 { + status = "okay"; +}; + +&dsi1_in_vp1 { + status = "disabled"; +}; + +/delete-node/ &dsi1_panel; + +&pwm4 { + pinctrl-names = "active"; + pinctrl-0 = <&pwm4_pins>; + status = "okay"; +}; + +&video_phy1 { + status = "okay"; +}; + +&dsi1 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi1_out_rkx110_x120: endpoint { + remote-endpoint = <&rkx110_x120_in_dsi1>; + }; + }; + }; +}; + +&rkx110_x120 { + pt-config { + rk-serdes,pt = , + , + ; + }; +}; + +&serdes_timing0 { + clock-frequency = <132000000>; + hactive = <1080>; + vactive = <1920>; + hfront-porch = <15>; + hsync-len = <2>; + hback-porch = <30>; + vfront-porch = <15>; + vsync-len = <2>; + vback-porch = <15>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <1>; +}; + +&serdes_panel { + dsi-rx,lanes = <4>; + //dsi-rx,video-mode; + local-port0 = ; + remote0-port0 = ; + dsi-tx,format = "rgb888"; + dsi-tx,lanes = <4>; + dsi-tx,video-mode; + + backlight = <&backlight>; + enable-gpios = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&panel_reset_ser0_gpio &panel_enable_ser0_gpio>; + + panel-init-sequence = [ + 23 00 02 FE 21 + 23 00 02 04 00 + 23 00 02 00 64 + 23 00 02 2A 00 + 23 00 02 26 64 + 23 00 02 54 00 + 23 00 02 50 64 + 23 00 02 7B 00 + 23 00 02 77 64 + 23 00 02 A2 00 + 23 00 02 9D 64 + 23 00 02 C9 00 + 23 00 02 C5 64 + 23 00 02 01 71 + 23 00 02 27 71 + 23 00 02 51 71 + 23 00 02 78 71 + 23 00 02 9E 71 + 23 00 02 C6 71 + 23 00 02 02 89 + 23 00 02 28 89 + 23 00 02 52 89 + 23 00 02 79 89 + 23 00 02 9F 89 + 23 00 02 C7 89 + 23 00 02 03 9E + 23 00 02 29 9E + 23 00 02 53 9E + 23 00 02 7A 9E + 23 00 02 A0 9E + 23 00 02 C8 9E + 23 00 02 09 00 + 23 00 02 05 B0 + 23 00 02 31 00 + 23 00 02 2B B0 + 23 00 02 5A 00 + 23 00 02 55 B0 + 23 00 02 80 00 + 23 00 02 7C B0 + 23 00 02 A7 00 + 23 00 02 A3 B0 + 23 00 02 CE 00 + 23 00 02 CA B0 + 23 00 02 06 C0 + 23 00 02 2D C0 + 23 00 02 56 C0 + 23 00 02 7D C0 + 23 00 02 A4 C0 + 23 00 02 CB C0 + 23 00 02 07 CF + 23 00 02 2F CF + 23 00 02 58 CF + 23 00 02 7E CF + 23 00 02 A5 CF + 23 00 02 CC CF + 23 00 02 08 DD + 23 00 02 30 DD + 23 00 02 59 DD + 23 00 02 7F DD + 23 00 02 A6 DD + 23 00 02 CD DD + 23 00 02 0E 15 + 23 00 02 0A E9 + 23 00 02 36 15 + 23 00 02 32 E9 + 23 00 02 5F 15 + 23 00 02 5B E9 + 23 00 02 85 15 + 23 00 02 81 E9 + 23 00 02 AD 15 + 23 00 02 A9 E9 + 23 00 02 D3 15 + 23 00 02 CF E9 + 23 00 02 0B 14 + 23 00 02 33 14 + 23 00 02 5C 14 + 23 00 02 82 14 + 23 00 02 AA 14 + 23 00 02 D0 14 + 23 00 02 0C 36 + 23 00 02 34 36 + 23 00 02 5D 36 + 23 00 02 83 36 + 23 00 02 AB 36 + 23 00 02 D1 36 + 23 00 02 0D 6B + 23 00 02 35 6B + 23 00 02 5E 6B + 23 00 02 84 6B + 23 00 02 AC 6B + 23 00 02 D2 6B + 23 00 02 13 5A + 23 00 02 0F 94 + 23 00 02 3B 5A + 23 00 02 37 94 + 23 00 02 64 5A + 23 00 02 60 94 + 23 00 02 8A 5A + 23 00 02 86 94 + 23 00 02 B2 5A + 23 00 02 AE 94 + 23 00 02 D8 5A + 23 00 02 D4 94 + 23 00 02 10 D1 + 23 00 02 38 D1 + 23 00 02 61 D1 + 23 00 02 87 D1 + 23 00 02 AF D1 + 23 00 02 D5 D1 + 23 00 02 11 04 + 23 00 02 39 04 + 23 00 02 62 04 + 23 00 02 88 04 + 23 00 02 B0 04 + 23 00 02 D6 04 + 23 00 02 12 05 + 23 00 02 3A 05 + 23 00 02 63 05 + 23 00 02 89 05 + 23 00 02 B1 05 + 23 00 02 D7 05 + 23 00 02 18 AA + 23 00 02 14 36 + 23 00 02 42 AA + 23 00 02 3D 36 + 23 00 02 69 AA + 23 00 02 65 36 + 23 00 02 8F AA + 23 00 02 8B 36 + 23 00 02 B7 AA + 23 00 02 B3 36 + 23 00 02 DD AA + 23 00 02 D9 36 + 23 00 02 15 74 + 23 00 02 3F 74 + 23 00 02 66 74 + 23 00 02 8C 74 + 23 00 02 B4 74 + 23 00 02 DA 74 + 23 00 02 16 9F + 23 00 02 40 9F + 23 00 02 67 9F + 23 00 02 8D 9F + 23 00 02 B5 9F + 23 00 02 DB 9F + 23 00 02 17 DC + 23 00 02 41 DC + 23 00 02 68 DC + 23 00 02 8E DC + 23 00 02 B6 DC + 23 00 02 DC DC + 23 00 02 1D FF + 23 00 02 19 03 + 23 00 02 47 FF + 23 00 02 43 03 + 23 00 02 6E FF + 23 00 02 6A 03 + 23 00 02 94 FF + 23 00 02 90 03 + 23 00 02 BC FF + 23 00 02 B8 03 + 23 00 02 E2 FF + 23 00 02 DE 03 + 23 00 02 1A 35 + 23 00 02 44 35 + 23 00 02 6B 35 + 23 00 02 91 35 + 23 00 02 B9 35 + 23 00 02 DF 35 + 23 00 02 1B 45 + 23 00 02 45 45 + 23 00 02 6C 45 + 23 00 02 92 45 + 23 00 02 BA 45 + 23 00 02 E0 45 + 23 00 02 1C 55 + 23 00 02 46 55 + 23 00 02 6D 55 + 23 00 02 93 55 + 23 00 02 BB 55 + 23 00 02 E1 55 + 23 00 02 22 FF + 23 00 02 1E 68 + 23 00 02 4C FF + 23 00 02 48 68 + 23 00 02 73 FF + 23 00 02 6F 68 + 23 00 02 99 FF + 23 00 02 95 68 + 23 00 02 C1 FF + 23 00 02 BD 68 + 23 00 02 E7 FF + 23 00 02 E3 68 + 23 00 02 1F 7E + 23 00 02 49 7E + 23 00 02 70 7E + 23 00 02 96 7E + 23 00 02 BE 7E + 23 00 02 E4 7E + 23 00 02 20 97 + 23 00 02 4A 97 + 23 00 02 71 97 + 23 00 02 97 97 + 23 00 02 BF 97 + 23 00 02 E5 97 + 23 00 02 21 B5 + 23 00 02 4B B5 + 23 00 02 72 B5 + 23 00 02 98 B5 + 23 00 02 C0 B5 + 23 00 02 E6 B5 + 23 00 02 25 F0 + 23 00 02 23 E8 + 23 00 02 4F F0 + 23 00 02 4D E8 + 23 00 02 76 F0 + 23 00 02 74 E8 + 23 00 02 9C F0 + 23 00 02 9A E8 + 23 00 02 C4 F0 + 23 00 02 C2 E8 + 23 00 02 EA F0 + 23 00 02 E8 E8 + 23 00 02 24 FF + 23 00 02 4E FF + 23 00 02 75 FF + 23 00 02 9B FF + 23 00 02 C3 FF + 23 00 02 E9 FF + 23 00 02 FE 3D + 23 00 02 00 04 + 23 00 02 FE 23 + 23 00 02 08 82 + 23 00 02 0A 00 + 23 00 02 0B 00 + 23 00 02 0C 01 + 23 00 02 16 00 + 23 00 02 18 02 + 23 00 02 1B 04 + 23 00 02 19 04 + 23 00 02 1C 81 + 23 00 02 1F 00 + 23 00 02 20 03 + 23 00 02 23 04 + 23 00 02 21 01 + 23 00 02 54 63 + 23 00 02 55 54 + 23 00 02 6E 45 + 23 00 02 6D 36 + 23 00 02 FE 3D + 23 00 02 55 78 + 23 00 02 FE 20 + 23 00 02 26 30 + 23 00 02 FE 3D + 23 00 02 20 71 + 23 00 02 50 8F + 23 00 02 51 8F + 23 00 02 FE 00 + 23 00 02 35 00 + 05 78 01 11 + 05 1E 01 29 + ]; + + panel-exit-sequence = [ + 05 00 01 28 + 05 00 01 10 + ]; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + rkx110_x120_in_dsi1: endpoint { + remote-endpoint = <&dsi1_out_rkx110_x120>; + }; + }; + }; +}; + +/* vp0 for HDMI, vp2 for rgb */ +&vp0 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER0 | 1 << ROCKCHIP_VOP2_ESMART0 | + 1 << ROCKCHIP_VOP2_SMART0)>; + rockchip,primary-plane = ; +}; + +&vp2 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER1 | 1 << ROCKCHIP_VOP2_ESMART1 | + 1 << ROCKCHIP_VOP2_SMART1)>; + rockchip,primary-plane = ; +}; + diff --git a/arch/arm64/boot/dts/rockchip/rk3568m-serdes-v1-evb-display-dsi1-command2dual_lvds-lp4x-v10.dts b/arch/arm64/boot/dts/rockchip/rk3568m-serdes-v1-evb-display-dsi1-command2dual_lvds-lp4x-v10.dts new file mode 100644 index 000000000000..ee5ecb29f75d --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3568m-serdes-v1-evb-display-dsi1-command2dual_lvds-lp4x-v10.dts @@ -0,0 +1,123 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +#include +#include "rk3568m-serdes-v1-evb-lp4x-v10.dtsi" +#include "rk3568-android.dtsi" + +&backlight { + pwms = <&pwm4 0 25000 0>; + status = "okay"; +}; + +&i2c1 { + status = "okay"; + clock-frequency = <10000>; +}; + +&dsi0 { + status = "disabled"; +}; + +&dsi1_in_vp0 { + status = "okay"; +}; + +&dsi1_in_vp1 { + status = "disabled"; +}; + +/delete-node/ &dsi1_panel; + +&pwm4 { + pinctrl-names = "active"; + pinctrl-0 = <&pwm4_pins>; + status = "okay"; +}; + +&video_phy1 { + status = "okay"; +}; + +&dsi1 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi0_out_rkx110_x120: endpoint { + remote-endpoint = <&rkx110_x120_in_dsi0>; + }; + }; + }; +}; + +&rkx110_x120 { + pt-config { + rk-serdes,pt = , + , + ; + }; +}; + +&serdes_timing0 { + clock-frequency = <148500000>; + hactive = <1920>; + vactive = <1080>; + hfront-porch = <88>; + hsync-len = <44>; + hback-porch = <148>; + vfront-porch = <4>; + vsync-len = <5>; + vback-porch = <36>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <1>; +}; + +&serdes_panel { + local-port0 = ; + remote0-port0 = ; + + backlight = <&backlight>; + enable-gpios = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&panel_reset_ser0_gpio &panel_enable_ser0_gpio>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + rkx110_x120_in_dsi0: endpoint { + remote-endpoint = <&dsi0_out_rkx110_x120>; + }; + }; + }; +}; + +/* vp0 for HDMI, vp2 for rgb */ +&vp0 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER0 | 1 << ROCKCHIP_VOP2_ESMART0 | + 1 << ROCKCHIP_VOP2_SMART0)>; + rockchip,primary-plane = ; +}; + +&vp2 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER1 | 1 << ROCKCHIP_VOP2_ESMART1 | + 1 << ROCKCHIP_VOP2_SMART1)>; + rockchip,primary-plane = ; +}; + diff --git a/arch/arm64/boot/dts/rockchip/rk3568m-serdes-v1-evb-display-dsi1-command2lvds0-lp4x-v10.dts b/arch/arm64/boot/dts/rockchip/rk3568m-serdes-v1-evb-display-dsi1-command2lvds0-lp4x-v10.dts new file mode 100644 index 000000000000..34e492a49de1 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3568m-serdes-v1-evb-display-dsi1-command2lvds0-lp4x-v10.dts @@ -0,0 +1,123 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +#include +#include "rk3568m-serdes-v1-evb-lp4x-v10.dtsi" +#include "rk3568-android.dtsi" + +&backlight { + pwms = <&pwm4 0 25000 0>; + status = "okay"; +}; + +&i2c1 { + status = "okay"; + clock-frequency = <10000>; +}; + +&dsi0 { + status = "disabled"; +}; + +&dsi1_in_vp0 { + status = "okay"; +}; + +&dsi1_in_vp1 { + status = "disabled"; +}; + +/delete-node/ &dsi1_panel; + +&pwm4 { + pinctrl-names = "active"; + pinctrl-0 = <&pwm4_pins>; + status = "okay"; +}; + +&video_phy1 { + status = "okay"; +}; + +&dsi1 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi0_out_rkx110_x120: endpoint { + remote-endpoint = <&rkx110_x120_in_dsi0>; + }; + }; + }; +}; + +&rkx110_x120 { + pt-config { + rk-serdes,pt = , + , + ; + }; +}; + +&serdes_timing0 { + clock-frequency = <50000000>; + hactive = <1024>; + vactive = <600>; + hfront-porch = <160>; + hsync-len = <20>; + hback-porch = <140>; + vfront-porch = <12>; + vsync-len = <3>; + vback-porch = <20>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <1>; +}; + +&serdes_panel { + local-port0 = ; + remote0-port0 = ; + + backlight = <&backlight>; + enable-gpios = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&panel_reset_ser0_gpio &panel_enable_ser0_gpio>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + rkx110_x120_in_dsi0: endpoint { + remote-endpoint = <&dsi0_out_rkx110_x120>; + }; + }; + }; +}; + +/* vp0 for HDMI, vp2 for rgb */ +&vp0 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER0 | 1 << ROCKCHIP_VOP2_ESMART0 | + 1 << ROCKCHIP_VOP2_SMART0)>; + rockchip,primary-plane = ; +}; + +&vp2 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER1 | 1 << ROCKCHIP_VOP2_ESMART1 | + 1 << ROCKCHIP_VOP2_SMART1)>; + rockchip,primary-plane = ; +}; + diff --git a/arch/arm64/boot/dts/rockchip/rk3568m-serdes-v1-evb-display-lvds2dsi-lp4x-v10.dts b/arch/arm64/boot/dts/rockchip/rk3568m-serdes-v1-evb-display-lvds2dsi-lp4x-v10.dts new file mode 100644 index 000000000000..f2e5c5ff5bc5 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3568m-serdes-v1-evb-display-lvds2dsi-lp4x-v10.dts @@ -0,0 +1,369 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +#include +#include "rk3568m-serdes-v1-evb-lp4x-v10.dtsi" +#include "rk3568-android.dtsi" + +&backlight { + pwms = <&pwm4 0 25000 0>; + status = "okay"; +}; + +&i2c1 { + status = "okay"; + clock-frequency = <10000>; +}; + +&lvds { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + lvds_out_rkx110_x120: endpoint { + remote-endpoint = <&rkx110_x120_in_lvds>; + }; + }; + }; +}; + +&lvds_in_vp2 { + status = "okay"; +}; + +&pwm4 { + pinctrl-names = "active"; + pinctrl-0 = <&pwm4_pins>; + status = "okay"; +}; + +&rkx110_x120 { + pt-config { + rk-serdes,pt = , + , + ; + }; +}; + +&serdes_panel { + local-port0 = ; + remote0-port0 = ; + + backlight = <&backlight>; + enable-gpios = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&panel_reset_ser0_gpio &panel_enable_ser0_gpio>; + + dsi-tx,format = "rgb888"; + dsi-tx,lanes = <4>; + dsi-tx,video-mode; + + panel-init-sequence = [ + 23 00 02 FE 21 + 23 00 02 04 00 + 23 00 02 00 64 + 23 00 02 2A 00 + 23 00 02 26 64 + 23 00 02 54 00 + 23 00 02 50 64 + 23 00 02 7B 00 + 23 00 02 77 64 + 23 00 02 A2 00 + 23 00 02 9D 64 + 23 00 02 C9 00 + 23 00 02 C5 64 + 23 00 02 01 71 + 23 00 02 27 71 + 23 00 02 51 71 + 23 00 02 78 71 + 23 00 02 9E 71 + 23 00 02 C6 71 + 23 00 02 02 89 + 23 00 02 28 89 + 23 00 02 52 89 + 23 00 02 79 89 + 23 00 02 9F 89 + 23 00 02 C7 89 + 23 00 02 03 9E + 23 00 02 29 9E + 23 00 02 53 9E + 23 00 02 7A 9E + 23 00 02 A0 9E + 23 00 02 C8 9E + 23 00 02 09 00 + 23 00 02 05 B0 + 23 00 02 31 00 + 23 00 02 2B B0 + 23 00 02 5A 00 + 23 00 02 55 B0 + 23 00 02 80 00 + 23 00 02 7C B0 + 23 00 02 A7 00 + 23 00 02 A3 B0 + 23 00 02 CE 00 + 23 00 02 CA B0 + 23 00 02 06 C0 + 23 00 02 2D C0 + 23 00 02 56 C0 + 23 00 02 7D C0 + 23 00 02 A4 C0 + 23 00 02 CB C0 + 23 00 02 07 CF + 23 00 02 2F CF + 23 00 02 58 CF + 23 00 02 7E CF + 23 00 02 A5 CF + 23 00 02 CC CF + 23 00 02 08 DD + 23 00 02 30 DD + 23 00 02 59 DD + 23 00 02 7F DD + 23 00 02 A6 DD + 23 00 02 CD DD + 23 00 02 0E 15 + 23 00 02 0A E9 + 23 00 02 36 15 + 23 00 02 32 E9 + 23 00 02 5F 15 + 23 00 02 5B E9 + 23 00 02 85 15 + 23 00 02 81 E9 + 23 00 02 AD 15 + 23 00 02 A9 E9 + 23 00 02 D3 15 + 23 00 02 CF E9 + 23 00 02 0B 14 + 23 00 02 33 14 + 23 00 02 5C 14 + 23 00 02 82 14 + 23 00 02 AA 14 + 23 00 02 D0 14 + 23 00 02 0C 36 + 23 00 02 34 36 + 23 00 02 5D 36 + 23 00 02 83 36 + 23 00 02 AB 36 + 23 00 02 D1 36 + 23 00 02 0D 6B + 23 00 02 35 6B + 23 00 02 5E 6B + 23 00 02 84 6B + 23 00 02 AC 6B + 23 00 02 D2 6B + 23 00 02 13 5A + 23 00 02 0F 94 + 23 00 02 3B 5A + 23 00 02 37 94 + 23 00 02 64 5A + 23 00 02 60 94 + 23 00 02 8A 5A + 23 00 02 86 94 + 23 00 02 B2 5A + 23 00 02 AE 94 + 23 00 02 D8 5A + 23 00 02 D4 94 + 23 00 02 10 D1 + 23 00 02 38 D1 + 23 00 02 61 D1 + 23 00 02 87 D1 + 23 00 02 AF D1 + 23 00 02 D5 D1 + 23 00 02 11 04 + 23 00 02 39 04 + 23 00 02 62 04 + 23 00 02 88 04 + 23 00 02 B0 04 + 23 00 02 D6 04 + 23 00 02 12 05 + 23 00 02 3A 05 + 23 00 02 63 05 + 23 00 02 89 05 + 23 00 02 B1 05 + 23 00 02 D7 05 + 23 00 02 18 AA + 23 00 02 14 36 + 23 00 02 42 AA + 23 00 02 3D 36 + 23 00 02 69 AA + 23 00 02 65 36 + 23 00 02 8F AA + 23 00 02 8B 36 + 23 00 02 B7 AA + 23 00 02 B3 36 + 23 00 02 DD AA + 23 00 02 D9 36 + 23 00 02 15 74 + 23 00 02 3F 74 + 23 00 02 66 74 + 23 00 02 8C 74 + 23 00 02 B4 74 + 23 00 02 DA 74 + 23 00 02 16 9F + 23 00 02 40 9F + 23 00 02 67 9F + 23 00 02 8D 9F + 23 00 02 B5 9F + 23 00 02 DB 9F + 23 00 02 17 DC + 23 00 02 41 DC + 23 00 02 68 DC + 23 00 02 8E DC + 23 00 02 B6 DC + 23 00 02 DC DC + 23 00 02 1D FF + 23 00 02 19 03 + 23 00 02 47 FF + 23 00 02 43 03 + 23 00 02 6E FF + 23 00 02 6A 03 + 23 00 02 94 FF + 23 00 02 90 03 + 23 00 02 BC FF + 23 00 02 B8 03 + 23 00 02 E2 FF + 23 00 02 DE 03 + 23 00 02 1A 35 + 23 00 02 44 35 + 23 00 02 6B 35 + 23 00 02 91 35 + 23 00 02 B9 35 + 23 00 02 DF 35 + 23 00 02 1B 45 + 23 00 02 45 45 + 23 00 02 6C 45 + 23 00 02 92 45 + 23 00 02 BA 45 + 23 00 02 E0 45 + 23 00 02 1C 55 + 23 00 02 46 55 + 23 00 02 6D 55 + 23 00 02 93 55 + 23 00 02 BB 55 + 23 00 02 E1 55 + 23 00 02 22 FF + 23 00 02 1E 68 + 23 00 02 4C FF + 23 00 02 48 68 + 23 00 02 73 FF + 23 00 02 6F 68 + 23 00 02 99 FF + 23 00 02 95 68 + 23 00 02 C1 FF + 23 00 02 BD 68 + 23 00 02 E7 FF + 23 00 02 E3 68 + 23 00 02 1F 7E + 23 00 02 49 7E + 23 00 02 70 7E + 23 00 02 96 7E + 23 00 02 BE 7E + 23 00 02 E4 7E + 23 00 02 20 97 + 23 00 02 4A 97 + 23 00 02 71 97 + 23 00 02 97 97 + 23 00 02 BF 97 + 23 00 02 E5 97 + 23 00 02 21 B5 + 23 00 02 4B B5 + 23 00 02 72 B5 + 23 00 02 98 B5 + 23 00 02 C0 B5 + 23 00 02 E6 B5 + 23 00 02 25 F0 + 23 00 02 23 E8 + 23 00 02 4F F0 + 23 00 02 4D E8 + 23 00 02 76 F0 + 23 00 02 74 E8 + 23 00 02 9C F0 + 23 00 02 9A E8 + 23 00 02 C4 F0 + 23 00 02 C2 E8 + 23 00 02 EA F0 + 23 00 02 E8 E8 + 23 00 02 24 FF + 23 00 02 4E FF + 23 00 02 75 FF + 23 00 02 9B FF + 23 00 02 C3 FF + 23 00 02 E9 FF + 23 00 02 FE 3D + 23 00 02 00 04 + 23 00 02 FE 23 + 23 00 02 08 82 + 23 00 02 0A 00 + 23 00 02 0B 00 + 23 00 02 0C 01 + 23 00 02 16 00 + 23 00 02 18 02 + 23 00 02 1B 04 + 23 00 02 19 04 + 23 00 02 1C 81 + 23 00 02 1F 00 + 23 00 02 20 03 + 23 00 02 23 04 + 23 00 02 21 01 + 23 00 02 54 63 + 23 00 02 55 54 + 23 00 02 6E 45 + 23 00 02 6D 36 + 23 00 02 FE 3D + 23 00 02 55 78 + 23 00 02 FE 20 + 23 00 02 26 30 + 23 00 02 FE 3D + 23 00 02 20 71 + 23 00 02 50 8F + 23 00 02 51 8F + 23 00 02 FE 00 + 23 00 02 35 00 + 05 78 01 11 + 05 1E 01 29 + ]; + + panel-exit-sequence = [ + 05 00 01 28 + 05 00 01 10 + ]; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + rkx110_x120_in_lvds: endpoint { + remote-endpoint = <&lvds_out_rkx110_x120>; + }; + }; + }; +}; + +&video_phy0 { + status = "okay"; +}; + +/* vp0 for HDMI, vp2 for rgb */ +&vp0 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER0 | 1 << ROCKCHIP_VOP2_ESMART0 | + 1 << ROCKCHIP_VOP2_SMART0)>; + rockchip,primary-plane = ; +}; + +&vp2 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER1 | 1 << ROCKCHIP_VOP2_ESMART1 | + 1 << ROCKCHIP_VOP2_SMART1)>; + rockchip,primary-plane = ; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3568m-serdes-v1-evb-display-lvds2dual-lvds-lp4x-v10.dts b/arch/arm64/boot/dts/rockchip/rk3568m-serdes-v1-evb-display-lvds2dual-lvds-lp4x-v10.dts new file mode 100644 index 000000000000..d66f43b34a4d --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3568m-serdes-v1-evb-display-lvds2dual-lvds-lp4x-v10.dts @@ -0,0 +1,112 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +#include +#include "rk3568m-serdes-v1-evb-lp4x-v10.dtsi" +#include "rk3568-android.dtsi" + +&backlight { + pwms = <&pwm4 0 25000 0>; + status = "okay"; +}; + +&i2c1 { + status = "okay"; + clock-frequency = <10000>; +}; + +&lvds { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + lvds_out_rkx110_x120: endpoint { + remote-endpoint = <&rkx110_x120_in_lvds>; + }; + }; + }; +}; + +&lvds_in_vp2 { + status = "okay"; +}; + +&pwm4 { + pinctrl-names = "active"; + pinctrl-0 = <&pwm4_pins>; + status = "okay"; +}; + +&rkx110_x120 { + pt-config { + rk-serdes,pt = , + , + ; + }; +}; + +&serdes_timing0 { + clock-frequency = <100000000>; + hactive = <1920>; + vactive = <1080>; + hfront-porch = <140>; + hsync-len = <40>; + hback-porch = <100>; + vfront-porch = <15>; + vsync-len = <20>; + vback-porch = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; +}; + +&serdes_panel { + local-port0 = ; + remote0-port0 = ; + + backlight = <&backlight>; + enable-gpios = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&panel_reset_ser0_gpio &panel_enable_ser0_gpio>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + rkx110_x120_in_lvds: endpoint { + remote-endpoint = <&lvds_out_rkx110_x120>; + }; + }; + }; +}; + +&video_phy0 { + status = "okay"; +}; + +/* vp0 for HDMI, vp2 for rgb */ +&vp0 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER0 | 1 << ROCKCHIP_VOP2_ESMART0 | + 1 << ROCKCHIP_VOP2_SMART0)>; + rockchip,primary-plane = ; +}; + +&vp2 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER1 | 1 << ROCKCHIP_VOP2_ESMART1 | + 1 << ROCKCHIP_VOP2_SMART1)>; + rockchip,primary-plane = ; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3568m-serdes-v1-evb-display-lvds2dual-lvds-vehicle-lp4x-v10.dts b/arch/arm64/boot/dts/rockchip/rk3568m-serdes-v1-evb-display-lvds2dual-lvds-vehicle-lp4x-v10.dts new file mode 100644 index 000000000000..eebaa234948c --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3568m-serdes-v1-evb-display-lvds2dual-lvds-vehicle-lp4x-v10.dts @@ -0,0 +1,112 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +#include +#include "rk3568m-serdes-v1-evb-lp4x-v10.dtsi" +#include "rk3568-android.dtsi" + +&backlight { + pwms = <&pwm4 0 25000 0>; + status = "okay"; +}; + +&i2c1 { + status = "okay"; + clock-frequency = <10000>; +}; + +&lvds { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + lvds_out_rkx110_x120: endpoint { + remote-endpoint = <&rkx110_x120_in_lvds>; + }; + }; + }; +}; + +&lvds_in_vp2 { + status = "okay"; +}; + +&pwm4 { + pinctrl-names = "active"; + pinctrl-0 = <&pwm4_pins>; + status = "okay"; +}; + +&rkx110_x120 { + pt-config { + rk-serdes,pt = , + , + ; + }; +}; + +&serdes_timing0 { + clock-frequency = <66000000>; + hactive = <1920>; + vactive = <720>; + hfront-porch = <28>; + hsync-len = <20>; + hback-porch = <20>; + vfront-porch = <7>; + vsync-len = <6>; + vback-porch = <8>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; +}; + +&serdes_panel { + local-port0 = ; + remote0-port0 = ; + + backlight = <&backlight>; + enable-gpios = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&panel_reset_ser0_gpio &panel_enable_ser0_gpio>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + rkx110_x120_in_lvds: endpoint { + remote-endpoint = <&lvds_out_rkx110_x120>; + }; + }; + }; +}; + +&video_phy0 { + status = "okay"; +}; + +/* vp0 for HDMI, vp2 for rgb */ +&vp0 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER0 | 1 << ROCKCHIP_VOP2_ESMART0 | + 1 << ROCKCHIP_VOP2_SMART0)>; + rockchip,primary-plane = ; +}; + +&vp2 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER1 | 1 << ROCKCHIP_VOP2_ESMART1 | + 1 << ROCKCHIP_VOP2_SMART1)>; + rockchip,primary-plane = ; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3568m-serdes-v1-evb-display-lvds2lvds-lp4x-v10.dts b/arch/arm64/boot/dts/rockchip/rk3568m-serdes-v1-evb-display-lvds2lvds-lp4x-v10.dts new file mode 100644 index 000000000000..cbc5b31e4e01 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3568m-serdes-v1-evb-display-lvds2lvds-lp4x-v10.dts @@ -0,0 +1,112 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +#include +#include "rk3568m-serdes-v1-evb-lp4x-v10.dtsi" +#include "rk3568-android.dtsi" + +&backlight { + pwms = <&pwm4 0 25000 0>; + status = "okay"; +}; + +&i2c1 { + status = "okay"; + clock-frequency = <10000>; +}; + +&lvds { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + lvds_out_rkx110_x120: endpoint { + remote-endpoint = <&rkx110_x120_in_lvds>; + }; + }; + }; +}; + +&lvds_in_vp2 { + status = "okay"; +}; + +&pwm4 { + pinctrl-names = "active"; + pinctrl-0 = <&pwm4_pins>; + status = "okay"; +}; + +&rkx110_x120 { + pt-config { + rk-serdes,pt = , + , + ; + }; +}; + +&serdes_timing0 { + clock-frequency = <50000000>; + hactive = <1024>; + vactive = <600>; + hfront-porch = <160>; + hsync-len = <20>; + hback-porch = <140>; + vfront-porch = <12>; + vsync-len = <3>; + vback-porch = <20>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <1>; +}; + +&serdes_panel { + local-port0 = ; + remote0-port0 = ; + + backlight = <&backlight>; + enable-gpios = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&panel_reset_ser0_gpio &panel_enable_ser0_gpio>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + rkx110_x120_in_lvds: endpoint { + remote-endpoint = <&lvds_out_rkx110_x120>; + }; + }; + }; +}; + +&video_phy0 { + status = "okay"; +}; + +/* vp0 for HDMI, vp2 for rgb */ +&vp0 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER0 | 1 << ROCKCHIP_VOP2_ESMART0 | + 1 << ROCKCHIP_VOP2_SMART0)>; + rockchip,primary-plane = ; +}; + +&vp2 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER1 | 1 << ROCKCHIP_VOP2_ESMART1 | + 1 << ROCKCHIP_VOP2_SMART1)>; + rockchip,primary-plane = ; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3568m-serdes-v1-evb-display-lvds2rgb-lp4x-v10.dts b/arch/arm64/boot/dts/rockchip/rk3568m-serdes-v1-evb-display-lvds2rgb-lp4x-v10.dts new file mode 100644 index 000000000000..2dd9385109ad --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3568m-serdes-v1-evb-display-lvds2rgb-lp4x-v10.dts @@ -0,0 +1,112 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +#include +#include "rk3568m-serdes-v1-evb-lp4x-v10.dtsi" +#include "rk3568-android.dtsi" + +&backlight { + pwms = <&pwm4 0 25000 0>; + status = "okay"; +}; + +&i2c1 { + status = "okay"; + clock-frequency = <10000>; +}; + +&lvds { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + lvds_out_rkx110_x120: endpoint { + remote-endpoint = <&rkx110_x120_in_lvds>; + }; + }; + }; +}; + +&lvds_in_vp2 { + status = "okay"; +}; + +&pwm4 { + pinctrl-names = "active"; + pinctrl-0 = <&pwm4_pins>; + status = "okay"; +}; + +&rkx110_x120 { + pt-config { + rk-serdes,pt = , + , + ; + }; +}; + +&serdes_timing0 { + clock-frequency = <50000000>; + hactive = <1024>; + vactive = <600>; + hfront-porch = <160>; + hsync-len = <20>; + hback-porch = <140>; + vfront-porch = <12>; + vsync-len = <3>; + vback-porch = <20>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <1>; +}; + +&serdes_panel { + local-port0 = ; + remote0-port0 = ; + + backlight = <&backlight>; + enable-gpios = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&panel_reset_ser0_gpio &panel_enable_ser0_gpio>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + rkx110_x120_in_lvds: endpoint { + remote-endpoint = <&lvds_out_rkx110_x120>; + }; + }; + }; +}; + +&video_phy0 { + status = "okay"; +}; + +/* vp0 for HDMI, vp2 for rgb */ +&vp0 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER0 | 1 << ROCKCHIP_VOP2_ESMART0 | + 1 << ROCKCHIP_VOP2_SMART0)>; + rockchip,primary-plane = ; +}; + +&vp2 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER1 | 1 << ROCKCHIP_VOP2_ESMART1 | + 1 << ROCKCHIP_VOP2_SMART1)>; + rockchip,primary-plane = ; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3568m-serdes-v1-evb-display-rgb2dsi-lp4x-v10.dts b/arch/arm64/boot/dts/rockchip/rk3568m-serdes-v1-evb-display-rgb2dsi-lp4x-v10.dts new file mode 100644 index 000000000000..90810248bd0c --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3568m-serdes-v1-evb-display-rgb2dsi-lp4x-v10.dts @@ -0,0 +1,370 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +#include +#include "rk3568m-serdes-v1-evb-lp4x-v10.dtsi" +#include "rk3568-android.dtsi" + +&backlight { + pwms = <&pwm10 0 25000 0>; + status = "okay"; +}; + +&i2c1 { + status = "disabled"; +}; + +&i2c4 { + status = "okay"; + clock-frequency = <10000>; +}; + +&pwm10 { + pinctrl-names = "active"; + pinctrl-0 = <&pwm10m1_pins>; + status = "okay"; +}; + +&rgb { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + rgb_out_rkx110_x120: endpoint { + remote-endpoint = <&rkx110_x120_in_rgb>; + }; + }; + }; +}; + +&rgb_in_vp2 { + status = "okay"; +}; + +&rkx110_x120_1 { + pt-config { + rk-serdes,pt = , + , + ; + }; +}; + +&serdes_panel1 { + local-port0 = ; + remote0-port0 = ; + + backlight = <&backlight>; + enable-gpios = <&gpio2 RK_PA0 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&panel_reset_ser1_gpio &panel_enable_ser1_gpio>; + + dsi-tx,format = "rgb888"; + dsi-tx,lanes = <4>; + dsi-tx,video-mode; + + panel-init-sequence = [ + 23 00 02 FE 21 + 23 00 02 04 00 + 23 00 02 00 64 + 23 00 02 2A 00 + 23 00 02 26 64 + 23 00 02 54 00 + 23 00 02 50 64 + 23 00 02 7B 00 + 23 00 02 77 64 + 23 00 02 A2 00 + 23 00 02 9D 64 + 23 00 02 C9 00 + 23 00 02 C5 64 + 23 00 02 01 71 + 23 00 02 27 71 + 23 00 02 51 71 + 23 00 02 78 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02 3F 74 + 23 00 02 66 74 + 23 00 02 8C 74 + 23 00 02 B4 74 + 23 00 02 DA 74 + 23 00 02 16 9F + 23 00 02 40 9F + 23 00 02 67 9F + 23 00 02 8D 9F + 23 00 02 B5 9F + 23 00 02 DB 9F + 23 00 02 17 DC + 23 00 02 41 DC + 23 00 02 68 DC + 23 00 02 8E DC + 23 00 02 B6 DC + 23 00 02 DC DC + 23 00 02 1D FF + 23 00 02 19 03 + 23 00 02 47 FF + 23 00 02 43 03 + 23 00 02 6E FF + 23 00 02 6A 03 + 23 00 02 94 FF + 23 00 02 90 03 + 23 00 02 BC FF + 23 00 02 B8 03 + 23 00 02 E2 FF + 23 00 02 DE 03 + 23 00 02 1A 35 + 23 00 02 44 35 + 23 00 02 6B 35 + 23 00 02 91 35 + 23 00 02 B9 35 + 23 00 02 DF 35 + 23 00 02 1B 45 + 23 00 02 45 45 + 23 00 02 6C 45 + 23 00 02 92 45 + 23 00 02 BA 45 + 23 00 02 E0 45 + 23 00 02 1C 55 + 23 00 02 46 55 + 23 00 02 6D 55 + 23 00 02 93 55 + 23 00 02 BB 55 + 23 00 02 E1 55 + 23 00 02 22 FF + 23 00 02 1E 68 + 23 00 02 4C FF + 23 00 02 48 68 + 23 00 02 73 FF + 23 00 02 6F 68 + 23 00 02 99 FF + 23 00 02 95 68 + 23 00 02 C1 FF + 23 00 02 BD 68 + 23 00 02 E7 FF + 23 00 02 E3 68 + 23 00 02 1F 7E + 23 00 02 49 7E + 23 00 02 70 7E + 23 00 02 96 7E + 23 00 02 BE 7E + 23 00 02 E4 7E + 23 00 02 20 97 + 23 00 02 4A 97 + 23 00 02 71 97 + 23 00 02 97 97 + 23 00 02 BF 97 + 23 00 02 E5 97 + 23 00 02 21 B5 + 23 00 02 4B B5 + 23 00 02 72 B5 + 23 00 02 98 B5 + 23 00 02 C0 B5 + 23 00 02 E6 B5 + 23 00 02 25 F0 + 23 00 02 23 E8 + 23 00 02 4F F0 + 23 00 02 4D E8 + 23 00 02 76 F0 + 23 00 02 74 E8 + 23 00 02 9C F0 + 23 00 02 9A E8 + 23 00 02 C4 F0 + 23 00 02 C2 E8 + 23 00 02 EA F0 + 23 00 02 E8 E8 + 23 00 02 24 FF + 23 00 02 4E FF + 23 00 02 75 FF + 23 00 02 9B FF + 23 00 02 C3 FF + 23 00 02 E9 FF + 23 00 02 FE 3D + 23 00 02 00 04 + 23 00 02 FE 23 + 23 00 02 08 82 + 23 00 02 0A 00 + 23 00 02 0B 00 + 23 00 02 0C 01 + 23 00 02 16 00 + 23 00 02 18 02 + 23 00 02 1B 04 + 23 00 02 19 04 + 23 00 02 1C 81 + 23 00 02 1F 00 + 23 00 02 20 03 + 23 00 02 23 04 + 23 00 02 21 01 + 23 00 02 54 63 + 23 00 02 55 54 + 23 00 02 6E 45 + 23 00 02 6D 36 + 23 00 02 FE 3D + 23 00 02 55 78 + 23 00 02 FE 20 + 23 00 02 26 30 + 23 00 02 FE 3D + 23 00 02 20 71 + 23 00 02 50 8F + 23 00 02 51 8F + 23 00 02 FE 00 + 23 00 02 35 00 + 05 78 01 11 + 05 1E 01 29 + ]; + + panel-exit-sequence = [ + 05 00 01 28 + 05 00 01 10 + ]; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + rkx110_x120_in_rgb: endpoint { + remote-endpoint = <&rgb_out_rkx110_x120>; + }; + }; + }; +}; + +/* vp0 for HDMI, vp2 for rgb */ +&vp0 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER0 | 1 << ROCKCHIP_VOP2_ESMART0 | + 1 << ROCKCHIP_VOP2_SMART0)>; + rockchip,primary-plane = ; +}; + +&vp2 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER1 | 1 << ROCKCHIP_VOP2_ESMART1 | + 1 << ROCKCHIP_VOP2_SMART1)>; + rockchip,primary-plane = ; +}; + diff --git a/arch/arm64/boot/dts/rockchip/rk3568m-serdes-v1-evb-display-rgb2dual-lvds-lp4x-v10.dts b/arch/arm64/boot/dts/rockchip/rk3568m-serdes-v1-evb-display-rgb2dual-lvds-lp4x-v10.dts new file mode 100644 index 000000000000..4efba83a1f9c --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3568m-serdes-v1-evb-display-rgb2dual-lvds-lp4x-v10.dts @@ -0,0 +1,113 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +#include +#include "rk3568m-serdes-v1-evb-lp4x-v10.dtsi" +#include "rk3568-android.dtsi" + +&backlight { + pwms = <&pwm10 0 25000 0>; + status = "okay"; +}; + +&i2c1 { + status = "disabled"; +}; + +&i2c4 { + status = "okay"; + clock-frequency = <10000>; +}; + +&pwm10 { + pinctrl-names = "active"; + pinctrl-0 = <&pwm10m1_pins>; + status = "okay"; +}; + +&rgb { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + rgb_out_rkx110_x120: endpoint { + remote-endpoint = <&rkx110_x120_in_rgb>; + }; + }; + }; +}; + +&rgb_in_vp2 { + status = "okay"; +}; + +&rkx110_x120_1 { + pt-config { + rk-serdes,pt = , + , + ; + }; +}; + +&serdes_timing1 { + clock-frequency = <148500000>; + hactive = <1920>; + vactive = <1080>; + hfront-porch = <140>; + hsync-len = <40>; + hback-porch = <100>; + vfront-porch = <15>; + vsync-len = <20>; + vback-porch = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; +}; + +&serdes_panel1 { + local-port0 = ; + remote0-port0 = ; + + backlight = <&backlight>; + enable-gpios = <&gpio2 RK_PA0 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&panel_reset_ser1_gpio &panel_enable_ser1_gpio>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + rkx110_x120_in_rgb: endpoint { + remote-endpoint = <&rgb_out_rkx110_x120>; + }; + }; + }; +}; + +/* vp0 for HDMI, vp2 for rgb */ +&vp0 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER0 | 1 << ROCKCHIP_VOP2_ESMART0 | + 1 << ROCKCHIP_VOP2_SMART0)>; + rockchip,primary-plane = ; +}; + +&vp2 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER1 | 1 << ROCKCHIP_VOP2_ESMART1 | + 1 << ROCKCHIP_VOP2_SMART1)>; + rockchip,primary-plane = ; +}; + diff --git a/arch/arm64/boot/dts/rockchip/rk3568m-serdes-v1-evb-display-rgb2dual-lvds-vehicle-lp4x-v10.dts b/arch/arm64/boot/dts/rockchip/rk3568m-serdes-v1-evb-display-rgb2dual-lvds-vehicle-lp4x-v10.dts new file mode 100644 index 000000000000..89297ebde57e --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3568m-serdes-v1-evb-display-rgb2dual-lvds-vehicle-lp4x-v10.dts @@ -0,0 +1,113 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +#include +#include "rk3568m-serdes-v1-evb-lp4x-v10.dtsi" +#include "rk3568-android.dtsi" + +&backlight { + pwms = <&pwm10 0 25000 0>; + status = "okay"; +}; + +&i2c1 { + status = "disabled"; +}; + +&i2c4 { + status = "okay"; + clock-frequency = <10000>; +}; + +&pwm10 { + pinctrl-names = "active"; + pinctrl-0 = <&pwm10m1_pins>; + status = "okay"; +}; + +&rgb { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + rgb_out_rkx110_x120: endpoint { + remote-endpoint = <&rkx110_x120_in_rgb>; + }; + }; + }; +}; + +&rgb_in_vp2 { + status = "okay"; +}; + +&rkx110_x120_1 { + pt-config { + rk-serdes,pt = , + , + ; + }; +}; + +&serdes_timing1 { + clock-frequency = <66000000>; + hactive = <1920>; + vactive = <720>; + hfront-porch = <28>; + hsync-len = <20>; + hback-porch = <20>; + vfront-porch = <7>; + vsync-len = <6>; + vback-porch = <8>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; +}; + +&serdes_panel1 { + local-port0 = ; + remote0-port0 = ; + + backlight = <&backlight>; + enable-gpios = <&gpio2 RK_PA0 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&panel_reset_ser1_gpio &panel_enable_ser1_gpio>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + rkx110_x120_in_rgb: endpoint { + remote-endpoint = <&rgb_out_rkx110_x120>; + }; + }; + }; +}; + +/* vp0 for HDMI, vp2 for rgb */ +&vp0 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER0 | 1 << ROCKCHIP_VOP2_ESMART0 | + 1 << ROCKCHIP_VOP2_SMART0)>; + rockchip,primary-plane = ; +}; + +&vp2 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER1 | 1 << ROCKCHIP_VOP2_ESMART1 | + 1 << ROCKCHIP_VOP2_SMART1)>; + rockchip,primary-plane = ; +}; + diff --git a/arch/arm64/boot/dts/rockchip/rk3568m-serdes-v1-evb-display-rgb2lvds-lp4x-v10.dts b/arch/arm64/boot/dts/rockchip/rk3568m-serdes-v1-evb-display-rgb2lvds-lp4x-v10.dts new file mode 100644 index 000000000000..3f7cc6ac8346 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3568m-serdes-v1-evb-display-rgb2lvds-lp4x-v10.dts @@ -0,0 +1,112 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +#include +#include "rk3568m-serdes-v1-evb-lp4x-v10.dtsi" +#include "rk3568-android.dtsi" + +&backlight { + pwms = <&pwm10 0 25000 0>; + status = "okay"; +}; + +&i2c1 { + status = "disabled"; +}; + +&i2c4 { + status = "okay"; + clock-frequency = <10000>; +}; + +&pwm10 { + pinctrl-names = "active"; + pinctrl-0 = <&pwm10m1_pins>; + status = "okay"; +}; + +&rgb { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + rgb_out_rkx110_x120: endpoint { + remote-endpoint = <&rkx110_x120_in_rgb>; + }; + }; + }; +}; + +&rgb_in_vp2 { + status = "okay"; +}; + +&rkx110_x120_1 { + pt-config { + rk-serdes,pt = , + , + ; + }; +}; + +&serdes_timing1 { + clock-frequency = <50000000>; + hactive = <1024>; + vactive = <600>; + hfront-porch = <160>; + hsync-len = <20>; + hback-porch = <140>; + vfront-porch = <12>; + vsync-len = <3>; + vback-porch = <20>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <1>; +}; + +&serdes_panel1 { + local-port0 = ; + remote0-port0 = ; + + backlight = <&backlight>; + enable-gpios = <&gpio2 RK_PA0 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&panel_reset_ser1_gpio &panel_enable_ser1_gpio>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + rkx110_x120_in_rgb: endpoint { + remote-endpoint = <&rgb_out_rkx110_x120>; + }; + }; + }; +}; + +/* vp0 for HDMI, vp2 for rgb */ +&vp0 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER0 | 1 << ROCKCHIP_VOP2_ESMART0 | + 1 << ROCKCHIP_VOP2_SMART0)>; + rockchip,primary-plane = ; +}; + +&vp2 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER1 | 1 << ROCKCHIP_VOP2_ESMART1 | + 1 << ROCKCHIP_VOP2_SMART1)>; + rockchip,primary-plane = ; +}; + diff --git a/arch/arm64/boot/dts/rockchip/rk3568m-serdes-v1-evb-display-rgb2rgb-lp4x-v10.dts b/arch/arm64/boot/dts/rockchip/rk3568m-serdes-v1-evb-display-rgb2rgb-lp4x-v10.dts new file mode 100644 index 000000000000..969f6d20a6de --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3568m-serdes-v1-evb-display-rgb2rgb-lp4x-v10.dts @@ -0,0 +1,113 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +#include +#include "rk3568m-serdes-v1-evb-lp4x-v10.dtsi" +#include "rk3568-android.dtsi" + +&backlight { + pwms = <&pwm10 0 25000 0>; + status = "okay"; +}; + +&i2c1 { + status = "disabled"; +}; + +&i2c4 { + status = "okay"; + clock-frequency = <10000>; +}; + +&pwm10 { + pinctrl-names = "active"; + pinctrl-0 = <&pwm10m1_pins>; + status = "okay"; +}; + +&rgb { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + rgb_out_rkx110_x120: endpoint { + remote-endpoint = <&rkx110_x120_in_rgb>; + }; + }; + }; +}; + +&rgb_in_vp2 { + status = "okay"; +}; + +&rkx110_x120_1 { + pt-config { + rk-serdes,pt = , + , + ; + }; +}; + +&serdes_timing1 { + clock-frequency = <50000000>; + hactive = <1024>; + vactive = <600>; + hfront-porch = <160>; + hsync-len = <20>; + hback-porch = <140>; + vfront-porch = <12>; + vsync-len = <3>; + vback-porch = <20>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <1>; +}; + +&serdes_panel1 { + local-port0 = ; + remote0-port0 = ; + + backlight = <&backlight>; + enable-gpios = <&gpio2 RK_PA0 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&panel_reset_ser1_gpio &panel_enable_ser1_gpio>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + rkx110_x120_in_rgb: endpoint { + remote-endpoint = <&rgb_out_rkx110_x120>; + }; + }; + }; +}; + +/* vp0 for HDMI, vp2 for rgb */ +&vp0 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER0 | 1 << ROCKCHIP_VOP2_ESMART0 | + 1 << ROCKCHIP_VOP2_SMART0)>; + rockchip,primary-plane = ; +}; + +&vp2 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER1 | 1 << ROCKCHIP_VOP2_ESMART1 | + 1 << ROCKCHIP_VOP2_SMART1)>; + rockchip,primary-plane = ; +}; + diff --git a/arch/arm64/boot/dts/rockchip/rk3568m-serdes-v1-evb-display-super-frame-dsi0-command2dsi-lp4x-v10.dts b/arch/arm64/boot/dts/rockchip/rk3568m-serdes-v1-evb-display-super-frame-dsi0-command2dsi-lp4x-v10.dts new file mode 100644 index 000000000000..cedd1a54b69f --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3568m-serdes-v1-evb-display-super-frame-dsi0-command2dsi-lp4x-v10.dts @@ -0,0 +1,392 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +#include +#include "rk3568m-serdes-v1-evb-lp4x-v10.dtsi" +#include "rk3568-android.dtsi" + +&backlight { + pwms = <&pwm4 0 25000 0>; + status = "okay"; +}; + +&i2c1 { + status = "okay"; + clock-frequency = <10000>; +}; + +&dsi1 { + status = "disabled"; +}; + +&dsi0_in_vp0 { + status = "okay"; +}; + +&dsi0_in_vp1 { + status = "disabled"; +}; + +/delete-node/ &dsi0_panel; + +&pwm4 { + pinctrl-names = "active"; + pinctrl-0 = <&pwm4_pins>; + status = "okay"; +}; + +&video_phy0 { + status = "okay"; +}; + +&dsi0 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi0_out_rkx110_x120: endpoint { + remote-endpoint = <&rkx110_x120_in_dsi0>; + }; + }; + }; +}; + +&rkx110_x120 { + remote1-addr = <0x54>; +}; + +&serdes_timing0 { + clock-frequency = <132000000>; + hactive = <2160>; + vactive = <1920>; + hfront-porch = <30>; + hsync-len = <4>; + hback-porch = <60>; + vfront-porch = <15>; + vsync-len = <2>; + vback-porch = <15>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <1>; +}; + +&serdes_panel { + dsi-rx,lanes = <4>; + //dsi-rx,video-mode; + local-port0 = ; + remote0-port0 = ; + remote1-port0 = ; + split-mode; + dsi-tx,format = "rgb888"; + dsi-tx,lanes = <4>; + dsi-tx,video-mode; + + backlight = <&backlight>; + enable-gpios = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&panel_reset_ser0_gpio &panel_enable_ser0_gpio>; + + panel-init-sequence = [ + 23 00 02 FE 21 + 23 00 02 04 00 + 23 00 02 00 64 + 23 00 02 2A 00 + 23 00 02 26 64 + 23 00 02 54 00 + 23 00 02 50 64 + 23 00 02 7B 00 + 23 00 02 77 64 + 23 00 02 A2 00 + 23 00 02 9D 64 + 23 00 02 C9 00 + 23 00 02 C5 64 + 23 00 02 01 71 + 23 00 02 27 71 + 23 00 02 51 71 + 23 00 02 78 71 + 23 00 02 9E 71 + 23 00 02 C6 71 + 23 00 02 02 89 + 23 00 02 28 89 + 23 00 02 52 89 + 23 00 02 79 89 + 23 00 02 9F 89 + 23 00 02 C7 89 + 23 00 02 03 9E + 23 00 02 29 9E + 23 00 02 53 9E + 23 00 02 7A 9E + 23 00 02 A0 9E + 23 00 02 C8 9E + 23 00 02 09 00 + 23 00 02 05 B0 + 23 00 02 31 00 + 23 00 02 2B B0 + 23 00 02 5A 00 + 23 00 02 55 B0 + 23 00 02 80 00 + 23 00 02 7C B0 + 23 00 02 A7 00 + 23 00 02 A3 B0 + 23 00 02 CE 00 + 23 00 02 CA B0 + 23 00 02 06 C0 + 23 00 02 2D C0 + 23 00 02 56 C0 + 23 00 02 7D C0 + 23 00 02 A4 C0 + 23 00 02 CB C0 + 23 00 02 07 CF + 23 00 02 2F CF + 23 00 02 58 CF + 23 00 02 7E CF + 23 00 02 A5 CF + 23 00 02 CC CF + 23 00 02 08 DD + 23 00 02 30 DD + 23 00 02 59 DD + 23 00 02 7F DD + 23 00 02 A6 DD + 23 00 02 CD DD + 23 00 02 0E 15 + 23 00 02 0A E9 + 23 00 02 36 15 + 23 00 02 32 E9 + 23 00 02 5F 15 + 23 00 02 5B E9 + 23 00 02 85 15 + 23 00 02 81 E9 + 23 00 02 AD 15 + 23 00 02 A9 E9 + 23 00 02 D3 15 + 23 00 02 CF E9 + 23 00 02 0B 14 + 23 00 02 33 14 + 23 00 02 5C 14 + 23 00 02 82 14 + 23 00 02 AA 14 + 23 00 02 D0 14 + 23 00 02 0C 36 + 23 00 02 34 36 + 23 00 02 5D 36 + 23 00 02 83 36 + 23 00 02 AB 36 + 23 00 02 D1 36 + 23 00 02 0D 6B + 23 00 02 35 6B + 23 00 02 5E 6B + 23 00 02 84 6B + 23 00 02 AC 6B + 23 00 02 D2 6B + 23 00 02 13 5A + 23 00 02 0F 94 + 23 00 02 3B 5A + 23 00 02 37 94 + 23 00 02 64 5A + 23 00 02 60 94 + 23 00 02 8A 5A + 23 00 02 86 94 + 23 00 02 B2 5A + 23 00 02 AE 94 + 23 00 02 D8 5A + 23 00 02 D4 94 + 23 00 02 10 D1 + 23 00 02 38 D1 + 23 00 02 61 D1 + 23 00 02 87 D1 + 23 00 02 AF D1 + 23 00 02 D5 D1 + 23 00 02 11 04 + 23 00 02 39 04 + 23 00 02 62 04 + 23 00 02 88 04 + 23 00 02 B0 04 + 23 00 02 D6 04 + 23 00 02 12 05 + 23 00 02 3A 05 + 23 00 02 63 05 + 23 00 02 89 05 + 23 00 02 B1 05 + 23 00 02 D7 05 + 23 00 02 18 AA + 23 00 02 14 36 + 23 00 02 42 AA + 23 00 02 3D 36 + 23 00 02 69 AA + 23 00 02 65 36 + 23 00 02 8F AA + 23 00 02 8B 36 + 23 00 02 B7 AA + 23 00 02 B3 36 + 23 00 02 DD AA + 23 00 02 D9 36 + 23 00 02 15 74 + 23 00 02 3F 74 + 23 00 02 66 74 + 23 00 02 8C 74 + 23 00 02 B4 74 + 23 00 02 DA 74 + 23 00 02 16 9F + 23 00 02 40 9F + 23 00 02 67 9F + 23 00 02 8D 9F + 23 00 02 B5 9F + 23 00 02 DB 9F + 23 00 02 17 DC + 23 00 02 41 DC + 23 00 02 68 DC + 23 00 02 8E DC + 23 00 02 B6 DC + 23 00 02 DC DC + 23 00 02 1D FF + 23 00 02 19 03 + 23 00 02 47 FF + 23 00 02 43 03 + 23 00 02 6E FF + 23 00 02 6A 03 + 23 00 02 94 FF + 23 00 02 90 03 + 23 00 02 BC FF + 23 00 02 B8 03 + 23 00 02 E2 FF + 23 00 02 DE 03 + 23 00 02 1A 35 + 23 00 02 44 35 + 23 00 02 6B 35 + 23 00 02 91 35 + 23 00 02 B9 35 + 23 00 02 DF 35 + 23 00 02 1B 45 + 23 00 02 45 45 + 23 00 02 6C 45 + 23 00 02 92 45 + 23 00 02 BA 45 + 23 00 02 E0 45 + 23 00 02 1C 55 + 23 00 02 46 55 + 23 00 02 6D 55 + 23 00 02 93 55 + 23 00 02 BB 55 + 23 00 02 E1 55 + 23 00 02 22 FF + 23 00 02 1E 68 + 23 00 02 4C FF + 23 00 02 48 68 + 23 00 02 73 FF + 23 00 02 6F 68 + 23 00 02 99 FF + 23 00 02 95 68 + 23 00 02 C1 FF + 23 00 02 BD 68 + 23 00 02 E7 FF + 23 00 02 E3 68 + 23 00 02 1F 7E + 23 00 02 49 7E + 23 00 02 70 7E + 23 00 02 96 7E + 23 00 02 BE 7E + 23 00 02 E4 7E + 23 00 02 20 97 + 23 00 02 4A 97 + 23 00 02 71 97 + 23 00 02 97 97 + 23 00 02 BF 97 + 23 00 02 E5 97 + 23 00 02 21 B5 + 23 00 02 4B B5 + 23 00 02 72 B5 + 23 00 02 98 B5 + 23 00 02 C0 B5 + 23 00 02 E6 B5 + 23 00 02 25 F0 + 23 00 02 23 E8 + 23 00 02 4F F0 + 23 00 02 4D E8 + 23 00 02 76 F0 + 23 00 02 74 E8 + 23 00 02 9C F0 + 23 00 02 9A E8 + 23 00 02 C4 F0 + 23 00 02 C2 E8 + 23 00 02 EA F0 + 23 00 02 E8 E8 + 23 00 02 24 FF + 23 00 02 4E FF + 23 00 02 75 FF + 23 00 02 9B FF + 23 00 02 C3 FF + 23 00 02 E9 FF + 23 00 02 FE 3D + 23 00 02 00 04 + 23 00 02 FE 23 + 23 00 02 08 82 + 23 00 02 0A 00 + 23 00 02 0B 00 + 23 00 02 0C 01 + 23 00 02 16 00 + 23 00 02 18 02 + 23 00 02 1B 04 + 23 00 02 19 04 + 23 00 02 1C 81 + 23 00 02 1F 00 + 23 00 02 20 03 + 23 00 02 23 04 + 23 00 02 21 01 + 23 00 02 54 63 + 23 00 02 55 54 + 23 00 02 6E 45 + 23 00 02 6D 36 + 23 00 02 FE 3D + 23 00 02 55 78 + 23 00 02 FE 20 + 23 00 02 26 30 + 23 00 02 FE 3D + 23 00 02 20 71 + 23 00 02 50 8F + 23 00 02 51 8F + 23 00 02 FE 00 + 23 00 02 35 00 + 05 78 01 11 + 05 1E 01 29 + ]; + + panel-exit-sequence = [ + 05 00 01 28 + 05 00 01 10 + ]; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + rkx110_x120_in_dsi0: endpoint { + remote-endpoint = <&dsi0_out_rkx110_x120>; + }; + }; + }; +}; + +/* vp0 for HDMI, vp2 for rgb */ +&vp0 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER0 | 1 << ROCKCHIP_VOP2_ESMART0 | + 1 << ROCKCHIP_VOP2_SMART0)>; + rockchip,primary-plane = ; +}; + +&vp2 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER1 | 1 << ROCKCHIP_VOP2_ESMART1 | + 1 << ROCKCHIP_VOP2_SMART1)>; + rockchip,primary-plane = ; +}; + diff --git a/arch/arm64/boot/dts/rockchip/rk3568m-serdes-v1-evb-display-super-frame-dsi0-command2lvds0-lp4x-v10.dts b/arch/arm64/boot/dts/rockchip/rk3568m-serdes-v1-evb-display-super-frame-dsi0-command2lvds0-lp4x-v10.dts new file mode 100644 index 000000000000..6008e9705a21 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3568m-serdes-v1-evb-display-super-frame-dsi0-command2lvds0-lp4x-v10.dts @@ -0,0 +1,117 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +#include +#include "rk3568m-serdes-v1-evb-lp4x-v10.dtsi" +#include "rk3568-android.dtsi" + +&backlight { + pwms = <&pwm4 0 25000 0>; + status = "okay"; +}; + +&i2c1 { + status = "okay"; + clock-frequency = <10000>; +}; + +&dsi1 { + status = "disabled"; +}; + +&dsi0_in_vp0 { + status = "okay"; +}; + +&dsi0_in_vp1 { + status = "disabled"; +}; + +/delete-node/ &dsi0_panel; + +&pwm4 { + pinctrl-names = "active"; + pinctrl-0 = <&pwm4_pins>; + status = "okay"; +}; + +&video_phy0 { + status = "okay"; +}; + +&dsi0 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi0_out_rkx110_x120: endpoint { + remote-endpoint = <&rkx110_x120_in_dsi0>; + }; + }; + }; +}; + +&rkx110_x120 { + remote1-addr = <0x54>; +}; + +&serdes_timing0 { + clock-frequency = <100000000>; + hactive = <2048>; + vactive = <600>; + hfront-porch = <320>; + hsync-len = <40>; + hback-porch = <280>; + vfront-porch = <12>; + vsync-len = <3>; + vback-porch = <20>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <1>; +}; + +&serdes_panel { + local-port0 = ; + remote0-port0 = ; + remote1-port0 = ; + split-mode; + backlight = <&backlight>; + enable-gpios = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&panel_reset_ser0_gpio &panel_enable_ser0_gpio>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + rkx110_x120_in_dsi0: endpoint { + remote-endpoint = <&dsi0_out_rkx110_x120>; + }; + }; + }; +}; + +/* vp0 for HDMI, vp2 for rgb */ +&vp0 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER0 | 1 << ROCKCHIP_VOP2_ESMART0 | + 1 << ROCKCHIP_VOP2_SMART0)>; + rockchip,primary-plane = ; +}; + +&vp2 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER1 | 1 << ROCKCHIP_VOP2_ESMART1 | + 1 << ROCKCHIP_VOP2_SMART1)>; + rockchip,primary-plane = ; +}; + diff --git a/arch/arm64/boot/dts/rockchip/rk3568m-serdes-v1-evb-lp4x-v10.dtsi b/arch/arm64/boot/dts/rockchip/rk3568m-serdes-v1-evb-lp4x-v10.dtsi new file mode 100644 index 000000000000..5e2b2f976ae8 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3568m-serdes-v1-evb-lp4x-v10.dtsi @@ -0,0 +1,294 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include +#include +#include +#include "rk3568.dtsi" +#include "rk3568-evb.dtsi" + +/ { + model = "Rockchip RK3568M SERDES EVB LP4X V10 Board"; + compatible = "rockchip,rk3568m-serdes-evb-lp4x-v10", "rockchip,rk3568"; + + vcc2v5_sys: vcc2v5-ddr { + compatible = "regulator-fixed"; + regulator-name = "vcc2v5-sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + vin-supply = <&vcc3v3_sys>; + }; + + vcc3v3_bu: vcc3v3-bu { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_bu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc5v0_sys>; + }; +}; + +&combphy0_us { + status = "okay"; +}; + +&combphy2_psq { + status = "okay"; +}; + +>1x { + status = "disabled"; +}; + +&i2c0 { + status = "okay"; + + gs_mxc6655xa: gs_mxc6655xa@15 { + status = "okay"; + compatible = "gs_mxc6655xa"; + pinctrl-names = "default"; + pinctrl-0 = <&mxc6655xa_irq_gpio>; + reg = <0x15>; + irq-gpio = <&gpio0 RK_PA4 IRQ_TYPE_LEVEL_LOW>; + irq_enable = <0>; + poll_delay_ms = <30>; + type = ; + power-off-in-suspend = <1>; + layout = <1>; + }; +}; + +&i2c5 { + status = "disabled"; +}; + +&pinctrl { + mxc6655xa { + mxc6655xa_irq_gpio: mxc6655xa_irq_gpio { + rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + serdes { + serdes_reset_ser0_gpio: serdes_reset_ser0_gpio { + rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + serdes_reset_ser1_gpio: serdes_reset_ser1_gpio { + rockchip,pins = <2 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + serdes_enable_ser0_gpio: serdes_enable_ser0_gpio { + rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + serdes_enable_ser1_gpio: serdes_enable_ser1_gpio { + rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + serdes_irq_ser0_gpio: serdes_irq_ser0_gpio { + rockchip,pins = <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + serdes_irq_ser1_gpio: serdes_irq_ser1_gpio { + rockchip,pins = <1 RK_PD7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + serdes_panel { + panel_reset_ser0_gpio: panel-reset-ser0-gpio { + rockchip,pins = <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + panel_enable_ser0_gpio: panel-enable-ser0-gpio { + rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + panel_reset_ser1_gpio: panel-reset-ser1-gpio { + rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + panel_enable_ser1_gpio: panel-enable-ser1-gpio { + rockchip,pins = <2 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pmu_io_domains { + vccio6-supply = <&vcc_3v3>; +}; + +&pwm7 { + status = "disabled"; +}; + +&rk809_codec { + status = "disabled"; +}; + +&sdmmc0 { + status = "disabled"; +}; + +&sdmmc2 { + status = "disabled"; +}; + +&uart1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn>; +}; + +&wireless_wlan { + status = "disabled"; +}; + +&wireless_bluetooth { + status = "disabled"; +}; + +/* OTG0 */ +&combphy0_us { + rockchip,dis-u3otg0-port; + /* OTG and SATA0 not use combphy0_us, then disabled */ + status = "disabled"; +}; + +&i2c1 { + status = "disabled"; + clock-frequency = <100000>; + + rkx110_x120: rkx110-x120@57 { + compatible = "rockchip,rkx110"; + reg = <0x57>; + remote0-addr = <0x54>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + enable-gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_LOW>; + irq-gpios = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&serdes_reset_ser0_gpio &serdes_enable_ser0_gpio + &serdes_irq_ser0_gpio>; + + serdes_panel: serdes-panel { + compatible = "rockchip,serdes-panel"; + reg = <0>; + status = "okay"; + + display_timings0: display-timings { + native-mode = <&serdes_timing0>; + serdes_timing0: timing0 { + clock-frequency = <132000000>; + hactive = <1080>; + vactive = <1920>; + hfront-porch = <15>; + hsync-len = <2>; + hback-porch = <30>; + vfront-porch = <15>; + vsync-len = <2>; + vback-porch = <15>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <1>; + }; + }; + }; + }; +}; + +&i2c4 { + status = "disabled"; + clock-frequency = <100000>; + + rkx110_x120_1: rkx110-x120@57 { + compatible = "rockchip,rkx110"; + reg = <0x57>; + remote0-addr = <0x54>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + enable-gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio2 RK_PA2 GPIO_ACTIVE_LOW>; + irq-gpios = <&gpio1 RK_PD7 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&serdes_reset_ser1_gpio &serdes_enable_ser1_gpio + &serdes_irq_ser1_gpio>; + + serdes_panel1: serdes-panel { + compatible = "rockchip,serdes-panel"; + reg = <0>; + status = "okay"; + + display_timings1: display-timings { + native-mode = <&serdes_timing0>; + serdes_timing1: timing0 { + clock-frequency = <132000000>; + hactive = <1080>; + vactive = <1920>; + hfront-porch = <15>; + hsync-len = <2>; + hback-porch = <30>; + vfront-porch = <15>; + vsync-len = <2>; + vback-porch = <15>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <1>; + }; + }; + }; + }; +}; + +&u2phy0_otg { + vbus-supply = <&vcc5v0_otg>; + status = "okay"; +}; + +&usb2phy0 { + status = "okay"; +}; + +&usbdrd_dwc3 { + dr_mode = "otg"; + phys = <&u2phy0_otg>; + phy-names = "usb2-phy"; + extcon = <&usb2phy0>; + maximum-speed = "high-speed"; + snps,dis_u2_susphy_quirk; + status = "okay"; +}; + +&usbdrd30 { + status = "okay"; +}; + +/* HOST1 */ +&combphy1_usq { + status = "okay"; +}; + +&u2phy0_host { + phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&usb2phy0 { + status = "okay"; +}; + +&usbhost_dwc3 { + status = "okay"; +}; + +&usbhost30 { + status = "okay"; +};