From 6732ca7f09c4bcc8d99dfa3b519b97f6294b2340 Mon Sep 17 00:00:00 2001 From: Elaine Zhang Date: Wed, 20 Sep 2017 10:03:28 +0800 Subject: [PATCH] clk: rockchip: rk3399: fix up the clk tree description for clk_uart4 slove clk_uart4 set rate error. Change-Id: Icf8f36a5c68658ed92a1b794dc68f37c729d2646 Signed-off-by: Elaine Zhang --- drivers/clk/rockchip/clk-rk3399.c | 7 +++++-- include/dt-bindings/clock/rk3399-cru.h | 1 + 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/clk/rockchip/clk-rk3399.c b/drivers/clk/rockchip/clk-rk3399.c index 285896cf4207..5d8d3db85e58 100644 --- a/drivers/clk/rockchip/clk-rk3399.c +++ b/drivers/clk/rockchip/clk-rk3399.c @@ -1543,8 +1543,11 @@ static struct rockchip_clk_branch rk3399_clk_pmu_branches[] __initdata = { MUX(0, "clk_testout_2io", mux_clk_testout2_2io_p, CLK_IGNORE_UNUSED, RK3399_PMU_CLKSEL_CON(4), 15, 1, MFLAGS), - COMPOSITE(0, "clk_uart4_div", mux_24m_ppll_p, 0, - RK3399_PMU_CLKSEL_CON(5), 10, 1, MFLAGS, 0, 7, DFLAGS, + MUX(SCLK_UART4_SRC, "clk_uart4_src", mux_24m_ppll_p, CLK_SET_RATE_NO_REPARENT, + RK3399_PMU_CLKSEL_CON(5), 10, 1, MFLAGS), + + COMPOSITE_NOMUX(0, "clk_uart4_div", "clk_uart4_src", CLK_SET_RATE_PARENT, + RK3399_PMU_CLKSEL_CON(5), 0, 7, DFLAGS, RK3399_PMU_CLKGATE_CON(0), 5, GFLAGS), COMPOSITE_FRACMUX(0, "clk_uart4_frac", "clk_uart4_div", 0, diff --git a/include/dt-bindings/clock/rk3399-cru.h b/include/dt-bindings/clock/rk3399-cru.h index dd2b9572340a..c06838c663ff 100644 --- a/include/dt-bindings/clock/rk3399-cru.h +++ b/include/dt-bindings/clock/rk3399-cru.h @@ -370,6 +370,7 @@ #define SCLK_I2C0_PMU 9 #define SCLK_I2C4_PMU 10 #define SCLK_I2C8_PMU 11 +#define SCLK_UART4_SRC 12 #define PCLK_SRC_PMU 19 #define PCLK_PMU 20