From 675523fe4ea1d62205bbc29e208f889c6c962385 Mon Sep 17 00:00:00 2001
From: Weixin Zhou <zwx@rock-chips.com>
Date: Mon, 3 Jun 2019 14:50:31 +0800
Subject: [PATCH] arm64: dts: rockchip: rk3399pro-npu: add i2c3/mipi_csi2

Change-Id: I792e3989489104d2bc73af78cec3d89ed1d593b0
Signed-off-by: Weixin Zhou <zwx@rock-chips.com>
---
 .../boot/dts/rockchip/rk3399pro-npu.dtsi      | 36 +++++++++++++++++++
 1 file changed, 36 insertions(+)

diff --git a/arch/arm64/boot/dts/rockchip/rk3399pro-npu.dtsi b/arch/arm64/boot/dts/rockchip/rk3399pro-npu.dtsi
index db70b557c1b3..a1512d9d52b5 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399pro-npu.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399pro-npu.dtsi
@@ -19,6 +19,7 @@
 	aliases {
 		i2c0 = &i2c0;
 		i2c1 = &i2c1;
+		i2c3 = &i2c3;
 		serial2 = &uart2;
 	};
 
@@ -666,6 +667,19 @@
 		status = "disabled";
 	};
 
+	i2c3: i2c@ff508000 {
+		compatible = "rockchip,rk3399-i2c";
+		reg = <0x0 0xff508000 0x0 0x1000>;
+		clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
+		clock-names = "i2c", "pclk";
+		interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&i2c3_xfer>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+	};
+
 	uart2: serial@ff550000 {
 		compatible = "rockchip,rk1808-uart", "snps,dw-apb-uart";
 		reg = <0x0 0xff550000 0x0 0x100>;
@@ -777,6 +791,18 @@
 		status = "disabled";
 	};
 
+	mipi_csi2: mipi-csi2@ffb10000 {
+		compatible = "rockchip,rk1808-mipi-csi2";
+		reg = <0x0 0xffb10000 0x0 0x100>;
+		reg-names = "csihost_regs";
+		interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "csi-intr1", "csi-intr2";
+		clocks = <&cru PCLK_CSI2HOST>;
+		clock-names = "pclk_csi2host";
+		status = "disabled";
+	};
+
 	csi_tx: csi@ffb20000 {
 		compatible = "rockchip,rk1808-mipi-csi";
 		reg = <0x0 0xffb20000 0x0 0x500>;
@@ -1162,6 +1188,16 @@
 			};
 		};
 
+		i2c3 {
+			i2c3_xfer: i2c3-xfer {
+				rockchip,pins =
+					/* i2c3_sda */
+					<2 RK_PD1 1 &pcfg_pull_none_2ma_smt>,
+					/* i2c3_scl */
+					<2 RK_PD0 1 &pcfg_pull_none_2ma_smt>;
+			};
+		};
+
 		pciusb {
 			pciusb_pins: pciusb-pins {
 				rockchip,pins =