diff --git a/MAINTAINERS b/MAINTAINERS index 9cf06d0bef91..292cbfd5ef4b 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -14297,3 +14297,7 @@ AMLOGIC PINCTRL DRIVER M: Xingyu Chen F: drivers/amlogic/pinctrl/* F: include/dt-bindings/gpio/* + +AMLOGIC GPU CONFIG +M: Jiyu Yang +F: arch/arm64/boot/dts/amlogic/mesong12a-dvalin.dtsi diff --git a/arch/arm64/boot/dts/amlogic/g12a_pxp.dts b/arch/arm64/boot/dts/amlogic/g12a_pxp.dts index 96919593fdd7..da3a4b64c5b2 100644 --- a/arch/arm64/boot/dts/amlogic/g12a_pxp.dts +++ b/arch/arm64/boot/dts/amlogic/g12a_pxp.dts @@ -54,6 +54,14 @@ reg = <0x0 0x05300000 0x0 0x2000000>; no-map; }; + + ion_cma_reserved:linux,ion-dev { + compatible = "shared-dma-pool"; + reusable; + size = <0x0 0x8000000>; + alignment = <0x0 0x400000>; + }; + }; vout { diff --git a/arch/arm64/boot/dts/amlogic/mesong12a-dvalin.dtsi b/arch/arm64/boot/dts/amlogic/mesong12a-dvalin.dtsi new file mode 100644 index 000000000000..e477c1565ca4 --- /dev/null +++ b/arch/arm64/boot/dts/amlogic/mesong12a-dvalin.dtsi @@ -0,0 +1,117 @@ +/* + * Amlogic G12a Platform gpu + * + * Copyright (c) 2017-2017 Amlogic Ltd + * + * This file is licensed under a dual GPLv2 or BSD license. + * + */ + +/ { + + dvalin@0xffe40000 { + compatible = "arm,malit60x", "arm,malit6xx", "arm,mali-midgard"; + #cooling-cells = <2>; /* min followed by max */ + reg = <0 0xFFE40000 0 0x04000>, /*mali APB bus base address*/ + <0 0xFFD01000 0 0x01000>, /*reset register*/ + <0 0xFF800000 0 0x01000>, /*aobus for gpu pmu domain*/ + <0 0xFF63c000 0 0x01000>, /*hiubus for gpu clk cntl*/ + <0 0xFFD01000 0 0x01000>; /*reset register*/ + interrupt-parent = <&gic>; + interrupts = <0 160 4>, <0 161 4>, <0 162 4>; + interrupt-names = "GPU", "MMU", "JOB"; + + num_of_pp = <3>; + sc_mpp = <1>; /* number of shader cores used most of time. */ + clocks = <&clkc CLKID_GPU_MUX &clkc CLKID_GP0_PLL>; + clock-names = "gpu_mux","gp0_pll"; + + + tbl = <&dvfs285_cfg + &dvfs400_cfg + &dvfs500_cfg + &dvfs666_cfg + &dvfs800_cfg>; + + dvfs125_cfg:clk125_cfg { + clk_freq = <125000000>; + clk_parent = "fclk_div4"; + clkp_freq = <500000000>; + clk_reg = <0xA03>; + voltage = <1150>; + keep_count = <5>; + threshold = <30 120>; + }; + + dvfs250_cfg:dvfs250_cfg { + clk_freq = <250000000>; + clk_parent = "fclk_div4"; + clkp_freq = <500000000>; + clk_reg = <0xA01>; + voltage = <1150>; + keep_count = <5>; + threshold = <80 170>; + }; + + dvfs285_cfg:dvfs285_cfg { + clk_freq = <285714285>; + clk_parent = "fclk_div7"; + clkp_freq = <285714285>; + clk_reg = <0xE00>; + voltage = <1150>; + keep_count = <5>; + threshold = <100 190>; + }; + + dvfs400_cfg:dvfs400_cfg { + clk_freq = <400000000>; + clk_parent = "fclk_div5"; + clkp_freq = <400000000>; + clk_reg = <0xC00>; + voltage = <1150>; + keep_count = <5>; + threshold = <152 207>; + }; + + dvfs500_cfg:dvfs500_cfg { + clk_freq = <500000000>; + clk_parent = "fclk_div4"; + clkp_freq = <500000000>; + clk_reg = <0xA00>; + voltage = <1150>; + keep_count = <5>; + threshold = <180 220>; + }; + + dvfs666_cfg:dvfs666_cfg { + clk_freq = <666666666>; + clk_parent = "fclk_div3"; + clkp_freq = <666666666>; + clk_reg = <0x800>; + voltage = <1150>; + keep_count = <5>; + threshold = <210 236>; + }; + + dvfs750_cfg:dvfs750_cfg { + clk_freq = <744000000>; + clk_parent = "gp0_pll"; + clkp_freq = <744000000>; + clk_reg = <0x200>; + voltage = <1150>; + keep_count = <5>; + threshold = <230 255>; + }; + + dvfs800_cfg:dvfs800_cfg { + clk_freq = <800000000>; + clk_parent = "gp0_pll"; + clkp_freq = <800000000>; + clk_reg = <0x600>; + voltage = <1150>; + keep_count = <5>; + threshold = <230 255>; + }; + }; + +};/* end of / */ diff --git a/arch/arm64/boot/dts/amlogic/mesong12a.dtsi b/arch/arm64/boot/dts/amlogic/mesong12a.dtsi index d3aeffa7ec0d..8af3cab9b14f 100644 --- a/arch/arm64/boot/dts/amlogic/mesong12a.dtsi +++ b/arch/arm64/boot/dts/amlogic/mesong12a.dtsi @@ -26,6 +26,7 @@ #include #include #include +#include "mesong12a-dvalin.dtsi" / { cpus:cpus { @@ -413,6 +414,11 @@ }; };/* end of hiubus*/ + ion_dev { + compatible = "amlogic, ion_dev"; + memory-region = <&ion_cma_reserved>; + };/* end of ion_dev*/ + }; /* end of soc*/ };/* end of / */