From 6863df1d71e73754d42a93474a232cb88cc3956f Mon Sep 17 00:00:00 2001 From: Zohn Ni Date: Fri, 30 Dec 2022 17:11:04 +0800 Subject: [PATCH] ASoC: rockchip: spdif: Fixed the spdif channel probability reverse issue Alternating playback of S16_LE and S32_LE audio may cause the channel order to be reversed. It need to clear MCLK domain logic before setting Fmclk/Fsdo. Change-Id: I7cbfa01f5136b8815e5e2c6dc5dcda28ce49d13a Signed-off-by: Zohn Ni --- sound/soc/rockchip/rockchip_spdif.c | 4 ++++ sound/soc/rockchip/rockchip_spdif.h | 4 ++++ 2 files changed, 8 insertions(+) diff --git a/sound/soc/rockchip/rockchip_spdif.c b/sound/soc/rockchip/rockchip_spdif.c index 868091894e4a..af5203bf0c28 100644 --- a/sound/soc/rockchip/rockchip_spdif.c +++ b/sound/soc/rockchip/rockchip_spdif.c @@ -170,6 +170,10 @@ static int rk_spdif_hw_params(struct snd_pcm_substream *substream, return -EINVAL; } + regmap_update_bits(spdif->regmap, SPDIF_CFGR, SPDIF_CFGR_CLR_MASK, + SPDIF_CFGR_CLR_EN); + + udelay(1); ret = regmap_update_bits(spdif->regmap, SPDIF_CFGR, SPDIF_CFGR_CLK_DIV_MASK | SPDIF_CFGR_HALFWORD_ENABLE | diff --git a/sound/soc/rockchip/rockchip_spdif.h b/sound/soc/rockchip/rockchip_spdif.h index 8d4bec97e017..5c656bd8fd18 100644 --- a/sound/soc/rockchip/rockchip_spdif.h +++ b/sound/soc/rockchip/rockchip_spdif.h @@ -17,6 +17,10 @@ #define SPDIF_CFGR_CLK_DIV_MASK (0xff << SPDIF_CFGR_CLK_DIV_SHIFT) #define SPDIF_CFGR_CLK_DIV(x) ((x - 1) << SPDIF_CFGR_CLK_DIV_SHIFT) +#define SPDIF_CFGR_CLR_MASK BIT(7) +#define SPDIF_CFGR_CLR_EN BIT(7) +#define SPDIF_CFGR_CLR_DIS 0 + #define SPDIF_CFGR_CSE_MASK BIT(6) #define SPDIF_CFGR_CSE_EN BIT(6) #define SPDIF_CFGR_CSE_DIS 0