From 690f783013e67006c39b51b99ac686951a9264a5 Mon Sep 17 00:00:00 2001
From: Elaine Zhang <zhangqing@rock-chips.com>
Date: Thu, 9 Dec 2021 11:42:11 +0800
Subject: [PATCH] arm64: dts: rockchip: rk3588: remove scmi_spll init

SPLL has been set in SPL and UBOOT.
Kernel resetting causes mipi display jitter.

Note: If without Uboot, SPLL needs to be set in advance.

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Change-Id: I59475ce1ea7712069e6c4a445a432d77f19227d5
---
 arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 3 ---
 1 file changed, 3 deletions(-)

diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
index 40049097a522..527f1a4d5a17 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
@@ -616,9 +616,6 @@
 			scmi_clk: protocol@14 {
 				reg = <0x14>;
 				#clock-cells = <1>;
-
-				assigned-clocks = <&scmi_clk SCMI_SPLL>;
-				assigned-clock-rates = <700000000>;
 			};
 
 			scmi_reset: protocol@16 {