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rk3066b: add clock support
This commit is contained in:
chenxing
3633
arch/arm/mach-rk30/clock_data-rk3066b.c
Normal file
3633
arch/arm/mach-rk30/clock_data-rk3066b.c
Normal file
File diff suppressed because it is too large
Load Diff
583
arch/arm/mach-rk30/include/mach/cru-rk3066b.h
Executable file
583
arch/arm/mach-rk30/include/mach/cru-rk3066b.h
Executable file
@@ -0,0 +1,583 @@
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enum rk_plls_id {
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APLL_ID = 0,
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DPLL_ID,
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CPLL_ID,
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GPLL_ID,
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END_PLL_ID,
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};
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/*****cru reg offset*****/
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#define CRU_MODE_CON 0x40
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#define CRU_CLKSEL_CON 0x44
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#define CRU_CLKGATE_CON 0xd0
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#define CRU_GLB_SRST_FST 0x100
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#define CRU_GLB_SRST_SND 0x104
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#define CRU_SOFTRST_CON 0x110
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#define PLL_CONS(id, i) ((id) * 0x10 + ((i) * 4))
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#define CRU_CLKSELS_CON_CNT (35)
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#define CRU_CLKSELS_CON(i) (CRU_CLKSEL_CON + ((i) * 4))
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#define CRU_CLKGATES_CON_CNT (10)
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#define CRU_CLKGATES_CON(i) (CRU_CLKGATE_CON + ((i) * 4))
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#define CRU_SOFTRSTS_CON_CNT (9)
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#define CRU_SOFTRSTS_CON(i) (CRU_SOFTRST_CON + ((i) * 4))
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#define CRU_MISC_CON (0x134)
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#define CRU_GLB_CNT_TH (0x140)
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/********************************************************************/
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#define CRU_GET_REG_BITS_VAL(reg,bits_shift, msk) (((reg) >> (bits_shift))&(msk))
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#define CRU_W_MSK(bits_shift, msk) ((msk) << ((bits_shift) + 16))
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#define CRU_SET_BITS(val,bits_shift, msk) (((val)&(msk)) << (bits_shift))
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#define CRU_W_MSK_SETBITS(val,bits_shift,msk) (CRU_W_MSK(bits_shift, msk)|CRU_SET_BITS(val,bits_shift, msk))
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/*******************PLL CON0 BITS***************************/
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#define PLL_CLKFACTOR_SET(val, shift, msk) \
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((((val) - 1) & (msk)) << (shift))
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#define PLL_CLKFACTOR_GET(reg, shift, msk) \
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((((reg) >> (shift)) & (msk)) + 1)
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#define PLL_OD_MSK (0x3f)
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#define PLL_OD_SHIFT (0x0)
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#define PLL_CLKOD(val) PLL_CLKFACTOR_SET(val, PLL_OD_SHIFT, PLL_OD_MSK)
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#define PLL_NO(reg) PLL_CLKFACTOR_GET(reg, PLL_OD_SHIFT, PLL_OD_MSK)
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#define PLL_NO_SHIFT(reg) PLL_CLKFACTOR_GET(reg, PLL_OD_SHIFT, PLL_OD_MSK)
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#define PLL_CLKOD_SET(val) (PLL_CLKOD(val) | CRU_W_MSK(PLL_OD_SHIFT, PLL_OD_MSK))
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#define PLL_NR_MSK (0x3f)
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#define PLL_NR_SHIFT (8)
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#define PLL_CLKR(val) PLL_CLKFACTOR_SET(val, PLL_NR_SHIFT, PLL_NR_MSK)
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#define PLL_NR(reg) PLL_CLKFACTOR_GET(reg, PLL_NR_SHIFT, PLL_NR_MSK)
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#define PLL_CLKR_SET(val) (PLL_CLKR(val) | CRU_W_MSK(PLL_NR_SHIFT, PLL_NR_MSK))
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/*******************PLL CON1 BITS***************************/
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#define PLL_NF_MSK (0xffff)
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#define PLL_NF_SHIFT (0)
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#define PLL_CLKF(val) PLL_CLKFACTOR_SET(val, PLL_NF_SHIFT, PLL_NF_MSK)
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#define PLL_NF(reg) PLL_CLKFACTOR_GET(reg, PLL_NF_SHIFT, PLL_NF_MSK)
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#define PLL_CLKF_SET(val) (PLL_CLKF(val) | CRU_W_MSK(PLL_NF_SHIFT, PLL_NF_MSK))
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/*******************PLL CON2 BITS***************************/
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#if 0
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#define PLL_BWADJ_MSK (0xfff)
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#define PLL_BWADJ_SHIFT (0)
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#define PLL_CLK_BWADJ_SET(val) ((val) | CRU_W_MSK(PLL_BWADJ_SHIFT, PLL_BWADJ_MSK))
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#endif
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/*******************PLL CON3 BITS***************************/
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#define PLL_REST_MSK (1 << 5)
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#define PLL_REST_W_MSK (PLL_REST_MSK << 16)
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#define PLL_REST (1 << 5)
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#define PLL_REST_RESM (0 << 5)
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#define PLL_BYPASS_MSK (1 << 0)
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#define PLL_BYPASS (1 << 0)
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#define PLL_NO_BYPASS (0 << 0)
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#define PLL_PWR_DN_MSK (1 << 1)
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#define PLL_PWR_DN_W_MSK (PLL_PWR_DN_MSK << 16)
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#define PLL_PWR_DN (1 << 1)
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#define PLL_PWR_ON (0 << 1)
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#define PLL_STANDBY_MSK (1 << 2)
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#define PLL_STANDBY (1 << 2)
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#define PLL_NO_STANDBY (0 << 2)
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/*******************CLKSEL0 BITS***************************/
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//core preiph div
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#define CORE_PERIPH_W_MSK (3 << 22)
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#define CORE_PERIPH_MSK (3 << 6)
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#define CORE_PERIPH_2 (0 << 6)
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#define CORE_PERIPH_4 (1 << 6)
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#define CORE_PERIPH_8 (2 << 6)
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#define CORE_PERIPH_16 (3 << 6)
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//arm clk pll sel
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#define CORE_SEL_PLL_MSK (1 << 8)
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#define CORE_SEL_PLL_W_MSK (1 << 24)
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#define CORE_SEL_APLL (0 << 8)
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#define CORE_SEL_GPLL (1 << 8)
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#define CORE_CLK_DIV_W_MSK (0x1F << 16)
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#define CORE_CLK_DIV_MSK (0x1F)
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#define CORE_CLK_DIV(i) (((i) - 1) & 0x1F)
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/*******************CLKSEL1 BITS***************************/
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//aclk div
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#define GET_CORE_ACLK_VAL(reg) ((reg)>=4 ?8:((reg)+1))
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#define CPU_ACLK_W_MSK (7 << 16)
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#define CPU_ACLK_MSK (7 << 0)
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#define CPU_ACLK_11 (0 << 0)
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#define CPU_ACLK_21 (1 << 0)
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#define CPU_ACLK_31 (2 << 0)
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#define CPU_ACLK_41 (3 << 0)
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#define CPU_ACLK_81 (4 << 0)
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#define CORE_ACLK_W_MSK (7 << 19)
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#define CORE_ACLK_MSK (7 << 3)
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#define CORE_ACLK_11 (0 << 3)
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#define CORE_ACLK_21 (1 << 3)
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#define CORE_ACLK_31 (2 << 3)
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#define CORE_ACLK_41 (3 << 3)
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#define CORE_ACLK_81 (4 << 3)
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//hclk div
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#define ACLK_HCLK_W_MSK (3 << 24)
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#define ACLK_HCLK_MSK (3 << 8)
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#define ACLK_HCLK_11 (0 << 8)
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#define ACLK_HCLK_21 (1 << 8)
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#define ACLK_HCLK_41 (2 << 8)
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// pclk div
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#define ACLK_PCLK_W_MSK (3 << 28)
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#define ACLK_PCLK_MSK (3 << 12)
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#define ACLK_PCLK_11 (0 << 12)
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#define ACLK_PCLK_21 (1 << 12)
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#define ACLK_PCLK_41 (2 << 12)
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#define ACLK_PCLK_81 (3 << 12)
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// ahb2apb div
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#define AHB2APB_W_MSK (3 << 30)
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#define AHB2APB_MSK (3 << 14)
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#define AHB2APB_11 (0 << 14)
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#define AHB2APB_21 (1 << 14)
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#define AHB2APB_41 (2 << 14)
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/*******************MODE BITS***************************/
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#define PLL_MODE_MSK(id) (0x3 << ((id) * 4))
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#define PLL_MODE_SLOW(id) ((0x0<<((id)*4))|(0x3<<(16+(id)*4)))
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#define PLL_MODE_NORM(id) ((0x1<<((id)*4))|(0x3<<(16+(id)*4)))
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#define PLL_MODE_DEEP(id) ((0x2<<((id)*4))|(0x3<<(16+(id)*4)))
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/*******************clksel10***************************/
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#define PERI_ACLK_DIV_MASK 0x1f
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#define PERI_ACLK_DIV_OFF 0
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#define PERI_HCLK_DIV_MASK 0x3
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#define PERI_HCLK_DIV_OFF 8
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#define PERI_PCLK_DIV_MASK 0x3
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#define PERI_PCLK_DIV_OFF 12
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/*******************gate BITS***************************/
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#define CLK_GATE_CLKID(i) (16 * (i))
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#define CLK_GATE_CLKID_CONS(i) CRU_CLKGATES_CON((i) / 16)
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#define CLK_GATE(i) (1 << ((i)%16))
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#define CLK_UN_GATE(i) (0)
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#define CLK_GATE_W_MSK(i) (1 << (((i) % 16) + 16))
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enum cru_clk_gate {
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/* SCU CLK GATE 0 CON */
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CLK_GATE_CORE_PERIPH = CLK_GATE_CLKID(0),
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CLK_GATE_CPU_GPLL_PATH,
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CLK_GATE_DDRPHY_SRC,
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CLK_GATE_ACLK_CPU,
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CLK_GATE_HCLK_CPU,
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CLK_GATE_PCLK_CPU,
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CLK_GATE_ATCLK_CPU,
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CLK_GATE_ACLK_CORE,
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CLK_GATE_0RES8,
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CLK_GATE_I2S0_SRC,
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CLK_GATE_I2S0_FRAC,
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CLK_GATE_0RES11,
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CLK_GATE_0RES12,
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CLK_GATE_SPDIF_SRC,
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CLK_GATE_SPDIF_FRAC,
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CLK_GATE_TESTCLK,
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CLK_GATE_TIMER0 = CLK_GATE_CLKID(1),
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CLK_GATE_TIMER1,
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CLK_GATE_TIMER2,
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CLK_GATE_JTAG,
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CLK_GATE_ACLK_LCDC1_SRC,
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CLK_GATE_OTGPHY0,
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CLK_GATE_OTGPHY1,
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CLK_GATE_DDR_GPLL,
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CLK_GATE_UART0_SRC,
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CLK_GATE_UART0_FRAC_SRC,
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CLK_GATE_UART1_SRC,
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CLK_GATE_UART1_FRAC_SRC,
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CLK_GATE_UART2_SRC,
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CLK_GATE_UART2_FRAC_SRC,
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CLK_GATE_UART3_SRC,
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CLK_GATE_UART3_FRAC_SRC,
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CLK_GATE_PERIPH_SRC = CLK_GATE_CLKID(2),
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CLK_GATE_ACLK_PERIPH,
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CLK_GATE_HCLK_PERIPH,
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CLK_GATE_PCLK_PERIPH,
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CLK_GATE_SMC_SRC,
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CLK_GATE_MAC_SRC,
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CLK_GATE_HSADC_SRC,
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CLK_GATE_HSADC_FRAC_SRC,
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CLK_GATE_SARADC_SRC,
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CLK_GATE_SPI0_SRC,
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CLK_GATE_SPI1_SRC,
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CLK_GATE_MMC0_SRC,
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CLK_GATE_MAC_LBTEST,
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CLK_GATE_SDIO_SRC,
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CLK_GATE_EMMC_SRC,
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CLK_GATE_2RES15,
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CLK_GATE_ACLK_LCDC0_SRC = CLK_GATE_CLKID(3),
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CLK_GATE_DCLK_LCDC0_SRC,
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CLK_GATE_DCLK_LCDC1_SRC,
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CLK_GATE_PCLKIN_CIF0,
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CLK_GATE_3RES4,
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CLK_GATE_3RES5,
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CLK_GATE_HSICPHY_SRC,
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CLK_GATE_CIF0_OUT,
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CLK_GATE_3RES8,
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CLK_GATE_ACLK_VEPU_SRC,
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CLK_GATE_HCLK_VEPU,
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CLK_GATE_ACLK_VDPU_SRC,
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CLK_GATE_HCLK_VDPU,
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CLK_GATE_3RES13,
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CLK_GATE_3RES14,
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CLK_GATE_3RES15,
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CLK_GATE_HCLK_PERI_AXI_MATRIX = CLK_GATE_CLKID(4),
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CLK_GATE_PCLK_PERI_AXI_MATRIX,
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CLK_GATE_ACLK_CPU_PERI,
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CLK_GATE_ACLK_PERI_AXI_MATRIX,
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CLK_GATE_ACLK_PEI_NIU,
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CLK_GATE_HCLK_USB_PERI,
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CLK_GATE_HCLK_PERI_AHB_ARBI,
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CLK_GATE_HCLK_EMEM_PERI,
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CLK_GATE_HCLK_CPUBUS,
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CLK_GATE_HCLK_AHB2APB,
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CLK_GATE_ACLK_STRC_SYS,
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CLK_GATE_ACLK_L2MEM_CON,
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CLK_GATE_ACLK_INTMEM,
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CLK_GATE_4RES13,
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CLK_GATE_4RES14,
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CLK_GATE_HCLK_L2MEM,
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CLK_GATE_ACLK_DMAC1 = CLK_GATE_CLKID(5),
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CLK_GATE_ACLK_DMAC2,
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CLK_GATE_PCLK_EFUSE,
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CLK_GATE_PCLK_TZPC,
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CLK_GATE_PCLK_GRF,
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CLK_GATE_PCLK_PMU,
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CLK_GATE_HCLK_ROM,
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CLK_GATE_PCLK_DDRUPCTL,
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CLK_GATE_ACLK_SMC,
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CLK_GATE_HCLK_NANDC,
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CLK_GATE_HCLK_SDMMC0,
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CLK_GATE_HCLK_SDIO,
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CLK_GATE_HCLK_EMMC,
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CLK_GATE_HCLK_OTG0,
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CLK_GATE_5RES14,
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CLK_GATE_5RES15,
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CLK_GATE_ACLK_LCDC0 = CLK_GATE_CLKID(6),
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CLK_GATE_HCLK_LCDC0,
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CLK_GATE_HCLK_LCDC1,
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CLK_GATE_ACLK_LCDC1,
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CLK_GATE_HCLK_CIF0,
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CLK_GATE_ACLK_CIF0,
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CLK_GATE_6RES6,
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CLK_GATE_6RES7,
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CLK_GATE_ACLK_IPP,
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CLK_GATE_HCLK_IPP,
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CLK_GATE_HCLK_RGA,
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CLK_GATE_ACLK_RGA,
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CLK_GATE_HCLK_VIO_BUS,
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CLK_GATE_ACLK_VIO0,
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CLK_GATE_ACLK_VCODEC,
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CLK_GATE_HCLK_VIDEO_H2H,
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CLK_GATE_HCLK_EMAC = CLK_GATE_CLKID(7),
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CLK_GATE_HCLK_SPDIF,
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CLK_GATE_HCLK_I2S0_2CH,
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CLK_GATE_HCLK_OTG1,
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CLK_GATE_HCLK_HSIC,
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CLK_GATE_HCLK_HSADC,
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CLK_GATE_HCLK_PIDF,
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CLK_GATE_PCLK_TIMER0,
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CLK_GATE_PCLK_TIMER1,
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CLK_GATE_PCLK_TIMER2,
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CLK_GATE_PCLK_PWM01,
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CLK_GATE_PCLK_PWM23,
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CLK_GATE_PCLK_SPI0,
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CLK_GATE_PCLK_SPI1,
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CLK_GATE_PCLK_SARADC,
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CLK_GATE_PCLK_WDT,
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CLK_GATE_PCLK_UART0 = CLK_GATE_CLKID(8),
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CLK_GATE_PCLK_UART1,
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CLK_GATE_PCLK_UART2,
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CLK_GATE_PCLK_UART3,
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CLK_GATE_PCLK_I2C0,
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CLK_GATE_PCLK_I2C1,
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CLK_GATE_PCLK_I2C2,
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CLK_GATE_PCLK_I2C3,
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CLK_GATE_PCLK_I2C4,
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CLK_GATE_PCLK_GPIO0,
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CLK_GATE_PCLK_GPIO1,
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CLK_GATE_PCLK_GPIO2,
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CLK_GATE_PCLK_GPIO3,
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CLK_GATE_HCLK_GPS,
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CLK_GATE_8RES14,
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CLK_GATE_8RES15,
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CLK_GATE_CLK_CORE_DBG = CLK_GATE_CLKID(9),
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CLK_GATE_PCLK_DBG,
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CLK_GATE_CLK_TRACE,
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CLK_GATE_ATCLK,
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CLK_GATE_CLK_L2C,
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CLK_GATE_ACLK_VIO1,
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CLK_GATE_PCLK_PUBL,
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CLK_GATE_ACLK_GPU_MST,
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CLK_GATE_ACLK_GPU_SLV,
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CLK_GATE_CLK_GPU,
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CLK_GATE_9RES10,
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CLK_GATE_9RES11,
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CLK_GATE_9RES12,
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CLK_GATE_9RES13,
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CLK_GATE_9RES14,
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CLK_GATE_9RES15,
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CLK_GATE_MAX,
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};
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#define SOFT_RST_ID(i) (16 * (i))
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enum cru_soft_reset {
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SOFT_RST_0RES0 = SOFT_RST_ID(0),
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SOFT_RST_0RES1,
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SOFT_RST_MCORE,
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SOFT_RST_CORE0,
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SOFT_RST_CORE1,
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SOFT_RST_0RES5,
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SOFT_RST_0RES6,
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SOFT_RST_MCORE_DBG,
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SOFT_RST_CORE0_DBG,
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SOFT_RST_CORE1_DBG,
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SOFT_RST_0RES10,
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SOFT_RST_0RES11,
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|
||||
SOFT_RST_CORE0_WDT,
|
||||
SOFT_RST_CORE1_WDT,
|
||||
SOFT_RST_STRC_SYS_AXI,
|
||||
SOFT_RST_L2C,
|
||||
|
||||
SOFT_RST_1RES0 = SOFT_RST_ID(1),
|
||||
SOFT_RST_CPUSYS_AHB,
|
||||
SOFT_RST_L2MEM_CON_AXI,
|
||||
SOFT_RST_AHB2APB,
|
||||
|
||||
SOFT_RST_DMA1,
|
||||
SOFT_RST_INTMEM,
|
||||
SOFT_RST_ROM,
|
||||
SOFT_RST_1RES7,
|
||||
|
||||
SOFT_RST_I2S,
|
||||
SOFT_RST_1RES9,
|
||||
SOFT_RST_SPDIF,
|
||||
SOFT_RST_TIMER0,
|
||||
|
||||
SOFT_RST_TIMER1,
|
||||
SOFT_RST_TIMER2,
|
||||
SOFT_RST_EFUSE_APB,
|
||||
SOFT_RST_1RES15,
|
||||
|
||||
SOFT_RST_GPIO0 = SOFT_RST_ID(2),
|
||||
SOFT_RST_GPIO1,
|
||||
SOFT_RST_GPIO2,
|
||||
SOFT_RST_GPIO3,
|
||||
|
||||
SOFT_RST_2RES4,
|
||||
SOFT_RST_2RES5,
|
||||
SOFT_RST_2RES6,
|
||||
SOFT_RST_UART0,
|
||||
|
||||
SOFT_RST_UART1,
|
||||
SOFT_RST_UART2,
|
||||
SOFT_RST_UART3,
|
||||
SOFT_RST_I2C0,
|
||||
|
||||
SOFT_RST_I2C1,
|
||||
SOFT_RST_I2C2,
|
||||
SOFT_RST_I2C3,
|
||||
SOFT_RST_I2C4,
|
||||
|
||||
SOFT_RST_PWM0 = SOFT_RST_ID(3),
|
||||
SOFT_RST_PWM1,
|
||||
SOFT_RST_DAP_PO,
|
||||
SOFT_RST_DAP,
|
||||
|
||||
SOFT_RST_DAP_SYS,
|
||||
SOFT_RST_TPIU_ATB,
|
||||
SOFT_RST_PMU_APB,
|
||||
SOFT_RST_GRF,
|
||||
|
||||
SOFT_RST_PMU,
|
||||
SOFT_RST_PERIPHSYS_AXI,
|
||||
SOFT_RST_PERIPHSYS_AHB,
|
||||
SOFT_RST_PERIPHSYS_APB,
|
||||
|
||||
SOFT_RST_PERIPH_NIU,
|
||||
SOFT_RST_CPU_PERI,
|
||||
SOFT_RST_EMEM_PERI,
|
||||
SOFT_RST_USB_PERI,
|
||||
|
||||
SOFT_RST_DMA2 = SOFT_RST_ID(4),
|
||||
SOFT_RST_SMC,
|
||||
SOFT_RST_MAC,
|
||||
SOFT_RST_GPS,
|
||||
|
||||
SOFT_RST_NANDC,
|
||||
SOFT_RST_USBOTG0,
|
||||
SOFT_RST_USBPHY0,
|
||||
SOFT_RST_OTGC0,
|
||||
|
||||
SOFT_RST_USBOTG1,
|
||||
SOFT_RST_USBPHY1,
|
||||
SOFT_RST_OTGC1,
|
||||
SOFT_RST_HSICPHY,
|
||||
|
||||
SOFT_RST_HSADC,
|
||||
SOFT_RST_PIDFILTER,
|
||||
SOFT_RST_4RES14,
|
||||
SOFT_RST_DDRMSCH,
|
||||
|
||||
SOFT_RST_TZPC = SOFT_RST_ID(5),
|
||||
SOFT_RST_MMC0,
|
||||
SOFT_RST_SDIO,
|
||||
SOFT_RST_EMMC,
|
||||
|
||||
SOFT_RST_SPI0,
|
||||
SOFT_RST_SPI1,
|
||||
SOFT_RST_WDT,
|
||||
SOFT_RST_SARADC,
|
||||
|
||||
SOFT_RST_DDRPHY,
|
||||
SOFT_RST_DDRPHY_APB,
|
||||
SOFT_RST_DDRCTRL,
|
||||
SOFT_RST_DDRCTRL_APB,
|
||||
|
||||
SOFT_RST_5RES12,
|
||||
SOFT_RST_DDRPHY_CTL,
|
||||
SOFT_RST_5RES14,
|
||||
SOFT_RST_5RES15,
|
||||
|
||||
SOFT_RST_6RES0 = SOFT_RST_ID(6),
|
||||
SOFT_RST_6RES1,
|
||||
SOFT_RST_VIO0_AXI,
|
||||
SOFT_RST_VIO_BUS_AHB,
|
||||
|
||||
SOFT_RST_LCDC0_AXI,
|
||||
SOFT_RST_LCDC0_AHB,
|
||||
SOFT_RST_LCDC0_DCLK,
|
||||
SOFT_RST_LCDC1_AXI,
|
||||
|
||||
SOFT_RST_LCDC1_AHB,
|
||||
SOFT_RST_LCDC1_DCLK,
|
||||
SOFT_RST_IPP_AXI,
|
||||
SOFT_RST_IPP_AHB,
|
||||
|
||||
SOFT_RST_RGA_AXI,
|
||||
SOFT_RST_RGA_AHB,
|
||||
SOFT_RST_CIF0,
|
||||
SOFT_RST_CIF1,//SOFT_RST_6RES15,
|
||||
|
||||
SOFT_RST_VCODEC_AXI = SOFT_RST_ID(7),
|
||||
SOFT_RST_VCODEC_AHB,
|
||||
SOFT_RST_VIO1_AXI,
|
||||
SOFT_RST_CPU_VCODEC,
|
||||
|
||||
SOFT_RST_VCODEC_NIU_AXI,
|
||||
SOFT_RST_HSIC_AHB,
|
||||
SOFT_RST_7RES6,
|
||||
SOFT_RST_7RES7,
|
||||
|
||||
SOFT_RST_GPU_CORE,
|
||||
SOFT_RST_7RES9,
|
||||
SOFT_RST_GPU_NIU_AXI,
|
||||
SOFT_RST_7RES11,
|
||||
|
||||
SOFT_RST_7RES12,
|
||||
SOFT_RST_TFUN_ATB,
|
||||
SOFT_RST_TFUN_APB,
|
||||
SOFT_RST_CTI4_APB,
|
||||
|
||||
SOFT_RST_TPIU_APB = SOFT_RST_ID(8),
|
||||
SOFT_RST_TRACE,
|
||||
SOFT_RST_CORE_DBG,
|
||||
SOFT_RST_DBG_APB,
|
||||
|
||||
SOFT_RST_CTI0,
|
||||
SOFT_RST_CTI0_APB,
|
||||
SOFT_RST_CTI1,
|
||||
SOFT_RST_CTI1_APB,
|
||||
|
||||
SOFT_RST_PTM_CORE0,
|
||||
SOFT_RST_PTM_CORE1,
|
||||
SOFT_RST_PTM0,
|
||||
SOFT_RST_PTM0_ATB,
|
||||
|
||||
SOFT_RST_PTM1,
|
||||
SOFT_RST_PTM1_ATB,
|
||||
SOFT_RST_CTM,
|
||||
SOFT_RST_TS,
|
||||
|
||||
SOFT_RST_MAX,
|
||||
};
|
||||
|
||||
/*****cru reg end*****/
|
||||
|
||||
static inline void cru_set_soft_reset(enum cru_soft_reset idx, bool on)
|
||||
{
|
||||
const void __iomem *reg = RK30_CRU_BASE + CRU_SOFTRSTS_CON(idx >> 4);
|
||||
u32 val = on ? 0x10001U << (idx & 0xf) : 0x10000U << (idx & 0xf);
|
||||
writel_relaxed(val, reg);
|
||||
dsb();
|
||||
}
|
||||
@@ -1,6 +1,8 @@
|
||||
#ifndef __MACH_CRU_H
|
||||
#define __MACH_CRU_H
|
||||
|
||||
#if defined(CONFIG_ARCH_RK3066B)
|
||||
#include <mach/cru-rk3066b.h>
|
||||
#elif defined(CONFIG_ARCH_RK30)
|
||||
enum rk_plls_id {
|
||||
APLL_ID = 0,
|
||||
DPLL_ID,
|
||||
@@ -510,3 +512,4 @@ static inline void cru_set_soft_reset(enum cru_soft_reset idx, bool on)
|
||||
}
|
||||
|
||||
#endif
|
||||
#endif
|
||||
|
||||
Reference in New Issue
Block a user