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soc: rockchip: power-domain: fix panic when pd power on for rk3588

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rockchip-pm-domain fd8d8000.power-management:power-controller: failed to set domain 'isp1', target_on= 1, val=0
Kernel panic - not syncing: panic_on_set_domain set ...
CPU: 4 PID: 1 Comm: swapper/0 Not tainted 5.10.66 #1
Call trace:
 dump_backtrace+0x0/0x1b4
 show_stack+0x24/0x30
 dump_stack_lvl+0xc8/0xf8
 dump_stack+0x18/0x34
 panic+0x170/0x340
 rockchip_do_pmu_set_power_domain+0xc0/0xf0
 rockchip_pd_power+0x16c/0x1ec
 rockchip_pd_power_on+0x28/0x3c
 _genpd_power_on+0xbc/0x138
 genpd_power_on.part.0+0x54/0x140
 genpd_power_on+0x20/0x34
 __genpd_dev_pm_attach+0x1a0/0x1f4
 genpd_dev_pm_attach+0x6c/0x70
 dev_pm_domain_attach+0x24/0x40
 platform_drv_probe+0x48/0xb0
 really_probe+0x2cc/0x45c
 driver_probe_device+0x134/0x144
 device_driver_attach+0x50/0x7c
 __driver_attach+0x14c/0x150
 bus_for_each_dev+0x7c/0xc8
 driver_attach+0x30/0x3c
 bus_add_driver+0x1b4/0x1fc
 driver_register+0xc0/0xf8
 __platform_driver_register+0x58/0x64
 rk_iommu_init+0x28/0x34
 do_one_initcall+0xa0/0x1e8
 do_initcalls+0x140/0x144
 kernel_init_freeable+0x12c/0x1a0
 kernel_init+0x20/0x11c
 ret_from_fork+0x10/0x30

Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Change-Id: I7252e474c1ae214e2cd79e9e72badb449ef3088b
This commit is contained in:
Finley Xiao
2022-04-08 21:49:40 +08:00
committed by Tao Huang
parent d5bc992f3c
commit 69b9adc8ad
1 changed files with 129 additions and 39 deletions
Download Patch File Download Diff File Expand all files Collapse all files

168
drivers/soc/rockchip/pm_domains.c
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@@ -48,9 +48,11 @@ struct rockchip_domain_info {
bool active_wakeup; bool active_wakeup;
int pwr_w_mask; int pwr_w_mask;
int req_w_mask; int req_w_mask;
int mem_status_mask;
int repair_status_mask; int repair_status_mask;
bool keepon_startup; bool keepon_startup;
u32 pwr_offset; u32 pwr_offset;
u32 mem_offset;
u32 req_offset; u32 req_offset;
}; };
@@ -60,6 +62,9 @@ struct rockchip_pmu_info {
u32 req_offset; u32 req_offset;
u32 idle_offset; u32 idle_offset;
u32 ack_offset; u32 ack_offset;
u32 mem_pwr_offset;
u32 chain_status_offset;
u32 mem_status_offset;
u32 repair_status_offset; u32 repair_status_offset;
u32 core_pwrcnt_offset; u32 core_pwrcnt_offset;
@@ -165,13 +170,15 @@ static void rockchip_pmu_unlock(struct rockchip_pm_domain *pd)
.req_offset = r_offset, \ .req_offset = r_offset, \
} }
#define DOMAIN_M_O_R(_name, p_offset, pwr, status, r_status, r_offset, req, idle, ack, wakeup, keepon) \ #define DOMAIN_M_O_R(_name, p_offset, pwr, status, m_offset, m_status, r_status, r_offset, req, idle, ack, wakeup, keepon) \
{ \ { \
.name = _name, \ .name = _name, \
.pwr_offset = p_offset, \ .pwr_offset = p_offset, \
.pwr_w_mask = (pwr) << 16, \ .pwr_w_mask = (pwr) << 16, \
.pwr_mask = (pwr), \ .pwr_mask = (pwr), \
.status_mask = (status), \ .status_mask = (status), \
.mem_offset = m_offset, \
.mem_status_mask = (m_status), \
.repair_status_mask = (r_status), \ .repair_status_mask = (r_status), \
.req_offset = r_offset, \ .req_offset = r_offset, \
.req_w_mask = (req) << 16, \ .req_w_mask = (req) << 16, \
@@ -234,11 +241,11 @@ static void rockchip_pmu_unlock(struct rockchip_pm_domain *pd)
#define DOMAIN_RK3568_PROTECT(name, pwr, req, wakeup) \ #define DOMAIN_RK3568_PROTECT(name, pwr, req, wakeup) \
DOMAIN_M(name, pwr, pwr, req, req, req, wakeup, true) DOMAIN_M(name, pwr, pwr, req, req, req, wakeup, true)
#define DOMAIN_RK3588(name, p_offset, pwr, status, r_status, r_offset, req, idle, wakeup) \ #define DOMAIN_RK3588(name, p_offset, pwr, status, m_offset, m_status, r_status, r_offset, req, idle, wakeup) \
DOMAIN_M_O_R(name, p_offset, pwr, status, r_status, r_offset, req, idle, idle, wakeup, false) DOMAIN_M_O_R(name, p_offset, pwr, status, m_offset, m_status, r_status, r_offset, req, idle, idle, wakeup, false)
#define DOMAIN_RK3588_P(name, p_offset, pwr, status, r_status, r_offset, req, idle, wakeup) \ #define DOMAIN_RK3588_P(name, p_offset, pwr, status, m_offset, m_status, r_status, r_offset, req, idle, wakeup) \
DOMAIN_M_O_R(name, p_offset, pwr, status, r_status, r_offset, req, idle, idle, wakeup, true) DOMAIN_M_O_R(name, p_offset, pwr, status, m_offset, m_status, r_status, r_offset, req, idle, idle, wakeup, true)
static bool rockchip_pmu_domain_is_idle(struct rockchip_pm_domain *pd) static bool rockchip_pmu_domain_is_idle(struct rockchip_pm_domain *pd)
{ {
@@ -431,6 +438,76 @@ int rockchip_restore_qos(struct device *dev)
} }
EXPORT_SYMBOL(rockchip_restore_qos); EXPORT_SYMBOL(rockchip_restore_qos);
static bool rockchip_pmu_domain_is_mem_on(struct rockchip_pm_domain *pd)
{
struct rockchip_pmu *pmu = pd->pmu;
unsigned int val;
regmap_read(pmu->regmap,
pmu->info->mem_status_offset + pd->info->mem_offset, &val);
/* 1'b0: power on, 1'b1: power off */
return !(val & pd->info->mem_status_mask);
}
static bool rockchip_pmu_domain_is_chain_on(struct rockchip_pm_domain *pd)
{
struct rockchip_pmu *pmu = pd->pmu;
unsigned int val;
regmap_read(pmu->regmap,
pmu->info->chain_status_offset + pd->info->mem_offset, &val);
/* 1'b1: power on, 1'b0: power off */
return val & pd->info->mem_status_mask;
}
static int rockchip_pmu_domain_mem_reset(struct rockchip_pm_domain *pd)
{
struct rockchip_pmu *pmu = pd->pmu;
struct generic_pm_domain *genpd = &pd->genpd;
bool is_on;
int ret = 0;
ret = readx_poll_timeout_atomic(rockchip_pmu_domain_is_chain_on, pd, is_on,
is_on == true, 0, 10000);
if (ret) {
dev_err(pmu->dev,
"failed to get chain status '%s', target_on=1, val=%d\n",
genpd->name, is_on);
goto error;
}
regmap_write(pmu->regmap, pmu->info->mem_pwr_offset + pd->info->pwr_offset,
(pd->info->pwr_mask | pd->info->pwr_w_mask));
dsb(sy);
ret = readx_poll_timeout_atomic(rockchip_pmu_domain_is_mem_on, pd, is_on,
is_on == false, 0, 10000);
if (ret) {
dev_err(pmu->dev,
"failed to get mem status '%s', target_on=0, val=%d\n",
genpd->name, is_on);
goto error;
}
regmap_write(pmu->regmap, pmu->info->mem_pwr_offset + pd->info->pwr_offset,
pd->info->pwr_w_mask);
dsb(sy);
ret = readx_poll_timeout_atomic(rockchip_pmu_domain_is_mem_on, pd, is_on,
is_on == true, 0, 10000);
if (ret) {
dev_err(pmu->dev,
"failed to get mem status '%s', target_on=1, val=%d\n",
genpd->name, is_on);
}
error:
return ret;
}
static bool rockchip_pmu_domain_is_on(struct rockchip_pm_domain *pd) static bool rockchip_pmu_domain_is_on(struct rockchip_pm_domain *pd)
{ {
struct rockchip_pmu *pmu = pd->pmu; struct rockchip_pmu *pmu = pd->pmu;
@@ -458,15 +535,19 @@ static int rockchip_do_pmu_set_power_domain(struct rockchip_pm_domain *pd,
struct rockchip_pmu *pmu = pd->pmu; struct rockchip_pmu *pmu = pd->pmu;
struct generic_pm_domain *genpd = &pd->genpd; struct generic_pm_domain *genpd = &pd->genpd;
u32 pd_pwr_offset = 0; u32 pd_pwr_offset = 0;
bool is_on; bool is_on, is_mem_on = false;
int ret = 0; int ret = 0;
if (pd->info->pwr_mask == 0)
return 0;
if (on && pd->info->mem_status_mask)
is_mem_on = rockchip_pmu_domain_is_mem_on(pd);
if (pd->info->pwr_offset) if (pd->info->pwr_offset)
pd_pwr_offset = pd->info->pwr_offset; pd_pwr_offset = pd->info->pwr_offset;
if (pd->info->pwr_mask == 0) if (pd->info->pwr_w_mask)
return 0;
else if (pd->info->pwr_w_mask)
regmap_write(pmu->regmap, pmu->info->pwr_offset + pd_pwr_offset, regmap_write(pmu->regmap, pmu->info->pwr_offset + pd_pwr_offset,
on ? pd->info->pwr_w_mask : on ? pd->info->pwr_w_mask :
(pd->info->pwr_mask | pd->info->pwr_w_mask)); (pd->info->pwr_mask | pd->info->pwr_w_mask));
@@ -477,6 +558,12 @@ static int rockchip_do_pmu_set_power_domain(struct rockchip_pm_domain *pd,
dsb(sy); dsb(sy);
if (is_mem_on) {
ret = rockchip_pmu_domain_mem_reset(pd);
if (ret)
goto error;
}
ret = readx_poll_timeout_atomic(rockchip_pmu_domain_is_on, pd, is_on, ret = readx_poll_timeout_atomic(rockchip_pmu_domain_is_on, pd, is_on,
is_on == on, 0, 10000); is_on == on, 0, 10000);
if (ret) { if (ret) {
@@ -1402,36 +1489,36 @@ static const struct rockchip_domain_info rk3568_pm_domains[] = {
}; };
static const struct rockchip_domain_info rk3588_pm_domains[] = { static const struct rockchip_domain_info rk3588_pm_domains[] = {
/* name p_offset pwr status r_status r_offset req idle wakeup */ /* name p_offset pwr status m_offset m_status r_status r_offset req idle wakeup */
[RK3588_PD_GPU] = DOMAIN_RK3588("gpu", 0x0, BIT(0), 0, BIT(1), 0x0, BIT(0), BIT(0), false), [RK3588_PD_GPU] = DOMAIN_RK3588("gpu", 0x0, BIT(0), 0, 0x0, 0, BIT(1), 0x0, BIT(0), BIT(0), false),
[RK3588_PD_NPU] = DOMAIN_RK3588("npu", 0x0, BIT(1), BIT(1), 0, 0x0, 0, 0, false), [RK3588_PD_NPU] = DOMAIN_RK3588("npu", 0x0, BIT(1), BIT(1), 0x0, 0, 0, 0x0, 0, 0, false),
[RK3588_PD_VCODEC] = DOMAIN_RK3588("vcodec", 0x0, BIT(2), BIT(2), 0, 0x0, 0, 0, false), [RK3588_PD_VCODEC] = DOMAIN_RK3588("vcodec", 0x0, BIT(2), BIT(2), 0x0, 0, 0, 0x0, 0, 0, false),
[RK3588_PD_NPUTOP] = DOMAIN_RK3588("nputop", 0x0, BIT(3), 0, BIT(2), 0x0, BIT(1), BIT(1), false), [RK3588_PD_NPUTOP] = DOMAIN_RK3588("nputop", 0x0, BIT(3), 0, 0x0, BIT(11), BIT(2), 0x0, BIT(1), BIT(1), false),
[RK3588_PD_NPU1] = DOMAIN_RK3588("npu1", 0x0, BIT(4), 0, BIT(3), 0x0, BIT(2), BIT(2), false), [RK3588_PD_NPU1] = DOMAIN_RK3588("npu1", 0x0, BIT(4), 0, 0x0, BIT(12), BIT(3), 0x0, BIT(2), BIT(2), false),
[RK3588_PD_NPU2] = DOMAIN_RK3588("npu2", 0x0, BIT(5), 0, BIT(4), 0x0, BIT(3), BIT(3), false), [RK3588_PD_NPU2] = DOMAIN_RK3588("npu2", 0x0, BIT(5), 0, 0x0, BIT(13), BIT(4), 0x0, BIT(3), BIT(3), false),
[RK3588_PD_VENC0] = DOMAIN_RK3588("venc0", 0x0, BIT(6), 0, BIT(5), 0x0, BIT(4), BIT(4), false), [RK3588_PD_VENC0] = DOMAIN_RK3588("venc0", 0x0, BIT(6), 0, 0x0, BIT(14), BIT(5), 0x0, BIT(4), BIT(4), false),
[RK3588_PD_VENC1] = DOMAIN_RK3588("venc1", 0x0, BIT(7), 0, BIT(6), 0x0, BIT(5), BIT(5), false), [RK3588_PD_VENC1] = DOMAIN_RK3588("venc1", 0x0, BIT(7), 0, 0x0, BIT(15), BIT(6), 0x0, BIT(5), BIT(5), false),
[RK3588_PD_RKVDEC0] = DOMAIN_RK3588("rkvdec0", 0x0, BIT(8), 0, BIT(7), 0x0, BIT(6), BIT(6), false), [RK3588_PD_RKVDEC0] = DOMAIN_RK3588("rkvdec0", 0x0, BIT(8), 0, 0x0, BIT(16), BIT(7), 0x0, BIT(6), BIT(6), false),
[RK3588_PD_RKVDEC1] = DOMAIN_RK3588("rkvdec1", 0x0, BIT(9), 0, BIT(8), 0x0, BIT(7), BIT(7), false), [RK3588_PD_RKVDEC1] = DOMAIN_RK3588("rkvdec1", 0x0, BIT(9), 0, 0x0, BIT(17), BIT(8), 0x0, BIT(7), BIT(7), false),
[RK3588_PD_VDPU] = DOMAIN_RK3588("vdpu", 0x0, BIT(10), 0, BIT(9), 0x0, BIT(8), BIT(8), false), [RK3588_PD_VDPU] = DOMAIN_RK3588("vdpu", 0x0, BIT(10), 0, 0x0, BIT(18), BIT(9), 0x0, BIT(8), BIT(8), false),
[RK3588_PD_RGA30] = DOMAIN_RK3588("rga30", 0x0, BIT(11), 0, BIT(10), 0x0, 0, 0, false), [RK3588_PD_RGA30] = DOMAIN_RK3588("rga30", 0x0, BIT(11), 0, 0x0, BIT(19), BIT(10), 0x0, 0, 0, false),
[RK3588_PD_AV1] = DOMAIN_RK3588("av1", 0x0, BIT(12), 0, BIT(11), 0x0, BIT(9), BIT(9), false), [RK3588_PD_AV1] = DOMAIN_RK3588("av1", 0x0, BIT(12), 0, 0x0, BIT(20), BIT(11), 0x0, BIT(9), BIT(9), false),
[RK3588_PD_VI] = DOMAIN_RK3588("vi", 0x0, BIT(13), 0, BIT(12), 0x0, BIT(10), BIT(10), false), [RK3588_PD_VI] = DOMAIN_RK3588("vi", 0x0, BIT(13), 0, 0x0, BIT(21), BIT(12), 0x0, BIT(10), BIT(10), false),
[RK3588_PD_FEC] = DOMAIN_RK3588("fec", 0x0, BIT(14), 0, BIT(13), 0x0, 0, 0, false), [RK3588_PD_FEC] = DOMAIN_RK3588("fec", 0x0, BIT(14), 0, 0x0, BIT(22), BIT(13), 0x0, 0, 0, false),
[RK3588_PD_ISP1] = DOMAIN_RK3588("isp1", 0x0, BIT(15), 0, BIT(14), 0x0, BIT(11), BIT(11), false), [RK3588_PD_ISP1] = DOMAIN_RK3588("isp1", 0x0, BIT(15), 0, 0x0, BIT(23), BIT(14), 0x0, BIT(11), BIT(11), false),
[RK3588_PD_RGA31] = DOMAIN_RK3588("rga31", 0x4, BIT(0), 0, BIT(15), 0x0, BIT(12), BIT(12), false), [RK3588_PD_RGA31] = DOMAIN_RK3588("rga31", 0x4, BIT(0), 0, 0x0, BIT(24), BIT(15), 0x0, BIT(12), BIT(12), false),
[RK3588_PD_VOP] = DOMAIN_RK3588_P("vop", 0x4, BIT(1), 0, BIT(16), 0x0, BIT(13) | BIT(14), BIT(13) | BIT(14), false), [RK3588_PD_VOP] = DOMAIN_RK3588_P("vop", 0x4, BIT(1), 0, 0x0, BIT(25), BIT(16), 0x0, BIT(13) | BIT(14), BIT(13) | BIT(14), false),
[RK3588_PD_VO0] = DOMAIN_RK3588_P("vo0", 0x4, BIT(2), 0, BIT(17), 0x0, BIT(15), BIT(15), false), [RK3588_PD_VO0] = DOMAIN_RK3588_P("vo0", 0x4, BIT(2), 0, 0x0, BIT(26), BIT(17), 0x0, BIT(15), BIT(15), false),
[RK3588_PD_VO1] = DOMAIN_RK3588_P("vo1", 0x4, BIT(3), 0, BIT(18), 0x4, BIT(0), BIT(16), false), [RK3588_PD_VO1] = DOMAIN_RK3588_P("vo1", 0x4, BIT(3), 0, 0x0, BIT(27), BIT(18), 0x4, BIT(0), BIT(16), false),
[RK3588_PD_AUDIO] = DOMAIN_RK3588("audio", 0x4, BIT(4), 0, BIT(19), 0x4, BIT(1), BIT(17), false), [RK3588_PD_AUDIO] = DOMAIN_RK3588("audio", 0x4, BIT(4), 0, 0x0, BIT(28), BIT(19), 0x4, BIT(1), BIT(17), false),
[RK3588_PD_PHP] = DOMAIN_RK3588("php", 0x4, BIT(5), 0, BIT(20), 0x4, BIT(5), BIT(21), false), [RK3588_PD_PHP] = DOMAIN_RK3588("php", 0x4, BIT(5), 0, 0x0, BIT(29), BIT(20), 0x4, BIT(5), BIT(21), false),
[RK3588_PD_GMAC] = DOMAIN_RK3588("gmac", 0x4, BIT(6), 0, BIT(21), 0x0, 0, 0, false), [RK3588_PD_GMAC] = DOMAIN_RK3588("gmac", 0x4, BIT(6), 0, 0x0, BIT(30), BIT(21), 0x0, 0, 0, false),
[RK3588_PD_PCIE] = DOMAIN_RK3588("pcie", 0x4, BIT(7), 0, BIT(22), 0x0, 0, 0, true), [RK3588_PD_PCIE] = DOMAIN_RK3588("pcie", 0x4, BIT(7), 0, 0x0, BIT(31), BIT(22), 0x0, 0, 0, true),
[RK3588_PD_NVM] = DOMAIN_RK3588("nvm", 0x4, BIT(8), BIT(24), 0, 0x4, BIT(2), BIT(18), false), [RK3588_PD_NVM] = DOMAIN_RK3588("nvm", 0x4, BIT(8), BIT(24), 0x4, 0, 0, 0x4, BIT(2), BIT(18), false),
[RK3588_PD_NVM0] = DOMAIN_RK3588("nvm0", 0x4, BIT(9), 0, BIT(23), 0x0, 0, 0, false), [RK3588_PD_NVM0] = DOMAIN_RK3588("nvm0", 0x4, BIT(9), 0, 0x4, BIT(1), BIT(23), 0x0, 0, 0, false),
[RK3588_PD_SDIO] = DOMAIN_RK3588("sdio", 0x4, BIT(10), 0, BIT(24), 0x4, BIT(3), BIT(19), false), [RK3588_PD_SDIO] = DOMAIN_RK3588("sdio", 0x4, BIT(10), 0, 0x4, BIT(2), BIT(24), 0x4, BIT(3), BIT(19), false),
[RK3588_PD_USB] = DOMAIN_RK3588("usb", 0x4, BIT(11), 0, BIT(25), 0x4, BIT(4), BIT(20), true), [RK3588_PD_USB] = DOMAIN_RK3588("usb", 0x4, BIT(11), 0, 0x4, BIT(3), BIT(25), 0x4, BIT(4), BIT(20), true),
[RK3588_PD_SDMMC] = DOMAIN_RK3588("sdmmc", 0x4, BIT(13), 0, BIT(26), 0x0, 0, 0, false), [RK3588_PD_SDMMC] = DOMAIN_RK3588("sdmmc", 0x4, BIT(13), 0, 0x4, BIT(5), BIT(26), 0x0, 0, 0, false),
}; };
static const struct rockchip_pmu_info px30_pmu = { static const struct rockchip_pmu_info px30_pmu = {
@@ -1608,6 +1695,9 @@ static const struct rockchip_pmu_info rk3588_pmu = {
.req_offset = 0x10c, .req_offset = 0x10c,
.idle_offset = 0x120, .idle_offset = 0x120,
.ack_offset = 0x118, .ack_offset = 0x118,
.mem_pwr_offset = 0x1a0,
.chain_status_offset = 0x1f0,
.mem_status_offset = 0x1f8,
.repair_status_offset = 0x290, .repair_status_offset = 0x290,
.num_domains = ARRAY_SIZE(rk3588_pm_domains), .num_domains = ARRAY_SIZE(rk3588_pm_domains),