From 69c3fdd97ff7277a6b0d83e57d9e910781001ca8 Mon Sep 17 00:00:00 2001 From: Yifeng Zhao Date: Sun, 21 Feb 2021 17:44:11 +0800 Subject: [PATCH] mmc: sdhci-of-dwcmshc: fix emmc cmd timeout issue while suspend and resume bug: [ 322.619045] PM: Syncing filesystems ... [ 322.669563] mmc2: error -110 doing runtime resume Disable DLL to reset emmc sample clock and the command conflict check function after the controller has been reset or config clock to 375Khz. Signed-off-by: Yifeng Zhao Change-Id: Ife306fdf1c8948e7ddef4d029b850735b43865e9 --- drivers/mmc/host/sdhci-of-dwcmshc.c | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-) diff --git a/drivers/mmc/host/sdhci-of-dwcmshc.c b/drivers/mmc/host/sdhci-of-dwcmshc.c index 5e43a76ce6ad..0fed2e9d113a 100644 --- a/drivers/mmc/host/sdhci-of-dwcmshc.c +++ b/drivers/mmc/host/sdhci-of-dwcmshc.c @@ -156,8 +156,16 @@ static void dwcmshc_rk_set_clock(struct sdhci_host *host, unsigned int clock) sdhci_set_clock(host, clock); - if (clock <= 400000) + /* Disable cmd conflict check */ + extra = sdhci_readl(host, DWCMSHC_HOST_CTRL3); + extra &= ~BIT(0); + sdhci_writel(host, extra, DWCMSHC_HOST_CTRL3); + + if (clock <= 400000) { + /* Disable DLL to reset sample clock */ + sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_CTRL); return; + } /* Reset DLL */ sdhci_writel(host, BIT(1), DWCMSHC_EMMC_DLL_CTRL); @@ -177,11 +185,6 @@ static void dwcmshc_rk_set_clock(struct sdhci_host *host, unsigned int clock) return; } - /* Disable cmd conflict check */ - extra = sdhci_readl(host, DWCMSHC_HOST_CTRL3); - extra &= ~BIT(0); - sdhci_writel(host, extra, DWCMSHC_HOST_CTRL3); - extra = 0x1 << 16 | /* tune clock stop en */ 0x2 << 17 | /* pre-change delay */ 0x3 << 19; /* post-change delay */