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riscv: Fixed wrong register in XIP_FIXUP_FLASH_OFFSET macro

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[ Upstream commit 5daa3726410288075ba73c336bb2e80d6b06aa4d ]

During the refactoring, a bug was introduced in the rarly used
XIP_FIXUP_FLASH_OFFSET macro.

Fixes: bee7fbc385 ("RISC-V CPU Idle Support")
Fixes: e7681beba9 ("RISC-V: Split out the XIP fixups into their own file")

Signed-off-by: Frederik Haxel <haxel@fzi.de>
Link: https://lore.kernel.org/r/20231212130116.848530-3-haxel@fzi.de
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
This commit is contained in:
Frederik Haxel
2023-12-12 14:01:13 +01:00
committed by Greg Kroah-Hartman
parent add57b5298
commit 69e9a6944d
1 changed files with 1 additions and 1 deletions
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2
arch/riscv/include/asm/xip_fixup.h
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@@ -13,7 +13,7 @@
add \reg, \reg, t0 add \reg, \reg, t0
.endm .endm
.macro XIP_FIXUP_FLASH_OFFSET reg .macro XIP_FIXUP_FLASH_OFFSET reg
la t1, __data_loc la t0, __data_loc
REG_L t1, _xip_phys_offset REG_L t1, _xip_phys_offset
sub \reg, \reg, t1 sub \reg, \reg, t1
add \reg, \reg, t0 add \reg, \reg, t0