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Merge tag 'dt64-cleanup-6.5' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-dt into soc/dt

Browse Source 
Minor improvements in ARM64 DTS for v6.5

Mostly minor improvements to fix dtbs_check warnings:
1. mba6ulx: use non-deprecated property for GPIO keys wake-up,
2. Add missing cache properties (APM, Amazon, HiSilicon, Realtek,
   Synaptics, AllWinner, Microchip).

Few older minor and major fixes which were waiting on mailing lists for
longer time for Microchip SparX-5:
1. Fix secondary CPU bring-up and crash when talking to PSCI on reference
   boards (Robert Marko),
2. Simplify CPU address-cells (Robert Marko),
3. Align pinctrl node names with bindings (Michael Walle).

* tag 'dt64-cleanup-6.5' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-dt:
  arm64: dts: sparx5: rename pinctrl nodes
  arm64: dts: microchip: sparx5: correct CPU address-cells
  arm64: dts: microchip: sparx5: do not use PSCI on reference boards
  arm64: dts: microchip: add missing cache properties
  arm64: dts: allwinner: a64: add missing cache properties
  arm64: dts: synaptics: add missing cache properties
  arm64: dts: realtek: add missing cache properties
  arm64: dts: hisilicon: add missing cache properties
  arm64: dts: amazon: add missing cache properties
  arm64: dts: apm: add missing cache properties
  arm64: dts: mba6ulx: correct GPIO keys wakeup

Link: https://lore.kernel.org/r/20230517131255.471002-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
2023-05-26 13:36:07 +02:00
parent 44c026a73b d5e64404e7
commit 6a02313612
20 changed files with 100 additions and 23 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
arch/arm/boot/dts/mba6ulx.dtsi
View File

@@ -57,7 +57,7 @@
label = "POWER";
linux,code = <KEY_POWER>;
gpios = <&gpio1 3 GPIO_ACTIVE_LOW>;
gpio-key,wakeup;
wakeup-source;
};
};

1
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
View File

@@ -93,6 +93,7 @@
L2: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
};

4
arch/arm64/boot/dts/amazon/alpine-v3.dtsi
View File

@@ -250,6 +250,7 @@
cache-line-size = <64>;
cache-sets = <2048>;
cache-level = <2>;
cache-unified;
};
cluster1_l2: cache@100 {
@@ -258,6 +259,7 @@
cache-line-size = <64>;
cache-sets = <2048>;
cache-level = <2>;
cache-unified;
};
cluster2_l2: cache@200 {
@@ -266,6 +268,7 @@
cache-line-size = <64>;
cache-sets = <2048>;
cache-level = <2>;
cache-unified;
};
cluster3_l2: cache@300 {
@@ -274,6 +277,7 @@
cache-line-size = <64>;
cache-sets = <2048>;
cache-level = <2>;
cache-unified;
};
};

8
arch/arm64/boot/dts/apm/apm-shadowcat.dtsi
View File

@@ -97,15 +97,23 @@
};
xgene_L2_0: l2-cache-0 {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
xgene_L2_1: l2-cache-1 {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
xgene_L2_2: l2-cache-2 {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
xgene_L2_3: l2-cache-3 {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
};

8
arch/arm64/boot/dts/apm/apm-storm.dtsi
View File

@@ -81,15 +81,23 @@
};
xgene_L2_0: l2-cache-0 {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
xgene_L2_1: l2-cache-1 {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
xgene_L2_2: l2-cache-2 {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
xgene_L2_3: l2-cache-3 {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
};

2
arch/arm64/boot/dts/hisilicon/hi3660.dtsi
View File

@@ -204,11 +204,13 @@
A53_L2: l2-cache0 {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
A73_L2: l2-cache1 {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
};

2
arch/arm64/boot/dts/hisilicon/hi6220.dtsi
View File

@@ -187,11 +187,13 @@
CLUSTER0_L2: l2-cache0 {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
CLUSTER1_L2: l2-cache1 {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
};

4
arch/arm64/boot/dts/hisilicon/hip05.dtsi
View File

@@ -212,21 +212,25 @@
cluster0_l2: l2-cache0 {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
cluster1_l2: l2-cache1 {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
cluster2_l2: l2-cache2 {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
cluster3_l2: l2-cache3 {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
};

4
arch/arm64/boot/dts/hisilicon/hip06.dtsi
View File

@@ -212,21 +212,25 @@
cluster0_l2: l2-cache0 {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
cluster1_l2: l2-cache1 {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
cluster2_l2: l2-cache2 {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
cluster3_l2: l2-cache3 {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
};

16
arch/arm64/boot/dts/hisilicon/hip07.dtsi
View File

@@ -843,81 +843,97 @@
cluster0_l2: l2-cache0 {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
cluster1_l2: l2-cache1 {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
cluster2_l2: l2-cache2 {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
cluster3_l2: l2-cache3 {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
cluster4_l2: l2-cache4 {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
cluster5_l2: l2-cache5 {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
cluster6_l2: l2-cache6 {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
cluster7_l2: l2-cache7 {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
cluster8_l2: l2-cache8 {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
cluster9_l2: l2-cache9 {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
cluster10_l2: l2-cache10 {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
cluster11_l2: l2-cache11 {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
cluster12_l2: l2-cache12 {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
cluster13_l2: l2-cache13 {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
cluster14_l2: l2-cache14 {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
cluster15_l2: l2-cache15 {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
};

10
arch/arm64/boot/dts/microchip/sparx5.dtsi
View File

@@ -24,7 +24,7 @@
};
cpus {
#address-cells = <2>;
#address-cells = <1>;
#size-cells = <0>;
cpu-map {
cluster0 {
@@ -39,19 +39,21 @@
cpu0: cpu@0 {
compatible = "arm,cortex-a53";
device_type = "cpu";
reg = <0x0 0x0>;
reg = <0x0>;
enable-method = "psci";
next-level-cache = <&L2_0>;
};
cpu1: cpu@1 {
compatible = "arm,cortex-a53";
device_type = "cpu";
reg = <0x0 0x1>;
reg = <0x1>;
enable-method = "psci";
next-level-cache = <&L2_0>;
};
L2_0: l2-cache0 {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
};
@@ -61,7 +63,7 @@
interrupt-affinity = <&cpu0>, <&cpu1>;
};
psci {
psci: psci {
compatible = "arm,psci-0.2";
method = "smc";
};

26
arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi
View File

@@ -325,69 +325,69 @@
};
&gpio {
i2cmux_pins_i: i2cmux-pins-i {
i2cmux_pins_i: i2cmux-pins {
pins = "GPIO_16", "GPIO_17", "GPIO_18", "GPIO_19",
"GPIO_20", "GPIO_22", "GPIO_36", "GPIO_35",
"GPIO_50", "GPIO_51", "GPIO_56", "GPIO_57";
function = "twi_scl_m";
output-low;
};
i2cmux_0: i2cmux-0 {
i2cmux_0: i2cmux-0-pins {
pins = "GPIO_16";
function = "twi_scl_m";
output-high;
};
i2cmux_1: i2cmux-1 {
i2cmux_1: i2cmux-1-pins {
pins = "GPIO_17";
function = "twi_scl_m";
output-high;
};
i2cmux_2: i2cmux-2 {
i2cmux_2: i2cmux-2-pins {
pins = "GPIO_18";
function = "twi_scl_m";
output-high;
};
i2cmux_3: i2cmux-3 {
i2cmux_3: i2cmux-3-pins {
pins = "GPIO_19";
function = "twi_scl_m";
output-high;
};
i2cmux_4: i2cmux-4 {
i2cmux_4: i2cmux-4-pins {
pins = "GPIO_20";
function = "twi_scl_m";
output-high;
};
i2cmux_5: i2cmux-5 {
i2cmux_5: i2cmux-5-pins {
pins = "GPIO_22";
function = "twi_scl_m";
output-high;
};
i2cmux_6: i2cmux-6 {
i2cmux_6: i2cmux-6-pins {
pins = "GPIO_36";
function = "twi_scl_m";
output-high;
};
i2cmux_7: i2cmux-7 {
i2cmux_7: i2cmux-7-pins {
pins = "GPIO_35";
function = "twi_scl_m";
output-high;
};
i2cmux_8: i2cmux-8 {
i2cmux_8: i2cmux-8-pins {
pins = "GPIO_50";
function = "twi_scl_m";
output-high;
};
i2cmux_9: i2cmux-9 {
i2cmux_9: i2cmux-9-pins {
pins = "GPIO_51";
function = "twi_scl_m";
output-high;
};
i2cmux_10: i2cmux-10 {
i2cmux_10: i2cmux-10-pins {
pins = "GPIO_56";
function = "twi_scl_m";
output-high;
};
i2cmux_11: i2cmux-11 {
i2cmux_11: i2cmux-11-pins {
pins = "GPIO_57";
function = "twi_scl_m";
output-high;

10
arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi
View File

@@ -59,28 +59,28 @@
};
&gpio {
i2cmux_pins_i: i2cmux-pins-i {
i2cmux_pins_i: i2cmux-pins {
pins = "GPIO_35", "GPIO_36",
"GPIO_50", "GPIO_51";
function = "twi_scl_m";
output-low;
};
i2cmux_s29: i2cmux-0 {
i2cmux_s29: i2cmux-0-pins {
pins = "GPIO_35";
function = "twi_scl_m";
output-high;
};
i2cmux_s30: i2cmux-1 {
i2cmux_s30: i2cmux-1-pins {
pins = "GPIO_36";
function = "twi_scl_m";
output-high;
};
i2cmux_s31: i2cmux-2 {
i2cmux_s31: i2cmux-2-pins {
pins = "GPIO_50";
function = "twi_scl_m";
output-high;
};
i2cmux_s32: i2cmux-3 {
i2cmux_s32: i2cmux-3-pins {
pins = "GPIO_51";
function = "twi_scl_m";
output-high;

12
arch/arm64/boot/dts/microchip/sparx5_pcb_common.dtsi
View File

@@ -6,6 +6,18 @@
/dts-v1/;
#include "sparx5.dtsi"
&psci {
status = "disabled";
};
&cpu0 {
enable-method = "spin-table";
};
&cpu1 {
enable-method = "spin-table";
};
&uart0 {
status = "okay";
};

2
arch/arm64/boot/dts/realtek/rtd1293.dtsi
View File

@@ -30,6 +30,8 @@
l2: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
};

2
arch/arm64/boot/dts/realtek/rtd1295.dtsi
View File

@@ -44,6 +44,8 @@
l2: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
};

2
arch/arm64/boot/dts/realtek/rtd1296.dtsi
View File

@@ -44,6 +44,8 @@
l2: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
};

2
arch/arm64/boot/dts/realtek/rtd1395.dtsi
View File

@@ -44,6 +44,8 @@
l2: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
};

4
arch/arm64/boot/dts/realtek/rtd16xx.dtsi
View File

@@ -88,11 +88,15 @@
l2: l2-cache {
compatible = "cache";
next-level-cache = <&l3>;
cache-level = <2>;
cache-unified;
};
l3: l3-cache {
compatible = "cache";
cache-level = <3>;
cache-unified;
};
};

2
arch/arm64/boot/dts/synaptics/berlin4ct.dtsi
View File

@@ -64,6 +64,8 @@
l2: cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
idle-states {