From 6a03ec9cb5bbb2fa7a8b4e29a03d3bd1da697e0c Mon Sep 17 00:00:00 2001 From: Yu Qiaowei Date: Thu, 29 May 2025 10:33:33 +0800 Subject: [PATCH] video: rockchip: rga3: modify the reset method to replace auto_rst on RK3576 1. Resetting only core_clk will cause abnormal src1 status in blend scenarios, so both aclk and core_clk must be reset. 2. Avoid the issue by shielding the wrong interrupt. Fixes: a2a7ce0bf0bf ("video: rockchip: rga3: add fix for hardware issuewith RK3576") Signed-off-by: Yu Qiaowei Change-Id: I3cb0034f6c3090faca19cea2c2f5b375388271f8 --- drivers/video/rockchip/rga3/rga2_reg_info.c | 23 ++++++++++++--------- 1 file changed, 13 insertions(+), 10 deletions(-) diff --git a/drivers/video/rockchip/rga3/rga2_reg_info.c b/drivers/video/rockchip/rga3/rga2_reg_info.c index 8e3d18f4dad1..1ec1f4183b62 100644 --- a/drivers/video/rockchip/rga3/rga2_reg_info.c +++ b/drivers/video/rockchip/rga3/rga2_reg_info.c @@ -2723,9 +2723,13 @@ static void rga2_soft_reset(struct rga_scheduler_t *scheduler) if (i == RGA_RESET_TIMEOUT) rga_err("%s[%#x] soft reset timeout.\n", rga_get_core_name(scheduler->core), scheduler->core); - else - rga_log("%s[%#x] soft reset complete.\n", - rga_get_core_name(scheduler->core), scheduler->core); +} + +static void rga2_soft_reset_print(struct rga_scheduler_t *scheduler) +{ + rga2_soft_reset(scheduler); + rga_log("%s[%#x] soft reset complete.\n", + rga_get_core_name(scheduler->core), scheduler->core); } static int rga2_check_param(struct rga_job *job, @@ -3132,12 +3136,11 @@ static int rga2_set_reg(struct rga_job *job, struct rga_scheduler_t *scheduler) sys_ctrl |= m_RGA2_SYS_CTRL_DST_WR_OPT_DIS | m_RGA2_SRC0_YUV420SP_RD_OPT_DIS; if (rga_hw_has_issue(scheduler, RGA_HW_ISSUE_DIS_AUTO_RST)) { - /* - * when RGA is running continuously, disabling auto_rst - * requires resetting core_clk. - */ - rga_write(m_RGA2_SYS_CTRL_AUTO_CKG | m_RGA2_SYS_CTRL_CCLK_SRESET_P, - RGA2_SYS_CTRL, scheduler); + /* disable all_finish & cur_finish intr_en */ + rga_write(0, RGA2_INT, scheduler); + rga_write(0, RGA2_CMD_REG_BASE + RGA2_MODE_CTRL_OFFSET, scheduler); + /* replace auto_rst */ + rga2_soft_reset(scheduler); } else { sys_ctrl |= m_RGA2_SYS_CTRL_AUTO_RST; } @@ -3346,7 +3349,7 @@ const struct rga_backend_ops rga2_ops = { .get_version = rga2_get_version, .set_reg = rga2_set_reg, .init_reg = rga2_init_reg, - .soft_reset = rga2_soft_reset, + .soft_reset = rga2_soft_reset_print, .read_back_reg = rga2_read_back_reg, .read_status = rga2_read_status, .irq = rga2_irq,