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vdin: add vdin support for tm2 [1/1]

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PD#SWPL-6701

Problem:
Need vdin supprt for sm2

Solution:
add vdin support for tm2

Verify:
test pass on tm2 ab311

Change-Id: I57d7b3014938011d18c5e168f18c78e4fa542fc7
Signed-off-by: Nian Jing <nian.jing@amlogic.com>

Conflicts:
	drivers/amlogic/media/vin/tvin/vdin/vdin_ctl.c
	drivers/amlogic/media/vin/tvin/vdin/vdin_drv.c
	drivers/amlogic/media/vin/tvin/viu/viuin.c
This commit is contained in:
Nian Jing
2019-04-04 20:46:46 +08:00
committed by Dongjin Kim
parent dc0d79e6fa
commit 6aa334dcd9
4 changed files with 87 additions and 32 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
drivers/amlogic/media/vin/tvin/bt656/bt656_601_in.c
View File

@@ -1129,7 +1129,8 @@ static int amvdec_656in_probe(struct platform_device *pdev)
if (is_meson_gxtvbb_cpu() || is_meson_gxl_cpu() ||
is_meson_gxm_cpu() || is_meson_g12a_cpu() ||
is_meson_g12b_cpu() || is_meson_tl1_cpu()) {
is_meson_g12b_cpu() || is_meson_tl1_cpu() ||
is_meson_tm2_cpu()) {
hw_cnt = 1;
} else if (is_meson_gxbb_cpu()) {
hw_cnt = 2;

52
drivers/amlogic/media/vin/tvin/vdin/vdin_ctl.c
View File

@@ -663,7 +663,9 @@ static void vdin_set_meas_mux(unsigned int offset, enum tvin_port_e port_,
meas_mux = MEAS_MUX_656_B;
else if ((is_meson_gxl_cpu() || is_meson_gxm_cpu() ||
is_meson_g12a_cpu() || is_meson_g12b_cpu() ||
is_meson_tl1_cpu()) && (bt_path == BT_PATH_GPIO))
is_meson_tl1_cpu() || is_meson_sm1_cpu() ||
is_meson_tm2_cpu()) &&
(bt_path == BT_PATH_GPIO))
meas_mux = MEAS_MUX_656;
else
pr_info("cpu not define or do not support bt656");
@@ -774,7 +776,9 @@ void vdin_set_top(unsigned int offset,
VDI9_ASFIFO_CTRL_BIT, VDI9_ASFIFO_CTRL_WID);
} else if ((is_meson_gxm_cpu() || is_meson_gxl_cpu() ||
is_meson_g12a_cpu() || is_meson_g12b_cpu() ||
is_meson_tl1_cpu()) && (bt_path == BT_PATH_GPIO)) {
is_meson_tl1_cpu() || is_meson_sm1_cpu() ||
is_meson_tm2_cpu()) &&
(bt_path == BT_PATH_GPIO)) {
vdin_mux = VDIN_MUX_656;
wr_bits(offset, VDIN_ASFIFO_CTRL0, 0xe4,
VDI1_ASFIFO_CTRL_BIT, VDI1_ASFIFO_CTRL_WID);
@@ -822,18 +826,36 @@ void vdin_set_top(unsigned int offset,
if (port != TVIN_PORT_VIU1)
wr_bits(offset, VDIN_ASFIFO_CTRL3, 0xe4,
VDI6_ASFIFO_CTRL_BIT, VDI6_ASFIFO_CTRL_WID);
else
wr_bits(offset, VDIN_ASFIFO_CTRL3, 0xf4,
VDI6_ASFIFO_CTRL_BIT, VDI6_ASFIFO_CTRL_WID);
else {
if (/*is_meson_gxlx2_cpu() || */is_meson_g12b_cpu()
|| is_meson_tl1_cpu() || is_meson_sm1_cpu() ||
is_meson_tm2_cpu())
wr_bits(offset, VDIN_ASFIFO_CTRL3, 0xd4,
VDI6_ASFIFO_CTRL_BIT,
VDI6_ASFIFO_CTRL_WID);
else
wr_bits(offset, VDIN_ASFIFO_CTRL3, 0xf4,
VDI6_ASFIFO_CTRL_BIT,
VDI6_ASFIFO_CTRL_WID);
}
break;
case 0xc0: /* viu2 */
vdin_mux = VDIN_MUX_VIU_2;
if (port != TVIN_PORT_VIU2)
wr_bits(offset, VDIN_ASFIFO_CTRL3, 0xe4,
VDI8_ASFIFO_CTRL_BIT, VDI8_ASFIFO_CTRL_WID);
else
wr_bits(offset, VDIN_ASFIFO_CTRL3, 0xf4,
VDI8_ASFIFO_CTRL_BIT, VDI8_ASFIFO_CTRL_WID);
else {
if (/*is_meson_gxlx2_cpu() || */is_meson_g12b_cpu()
|| is_meson_tl1_cpu() || is_meson_sm1_cpu() ||
is_meson_tm2_cpu())
wr_bits(offset, VDIN_ASFIFO_CTRL3, 0xd4,
VDI6_ASFIFO_CTRL_BIT,
VDI6_ASFIFO_CTRL_WID);
else
wr_bits(offset, VDIN_ASFIFO_CTRL3, 0xf4,
VDI6_ASFIFO_CTRL_BIT,
VDI6_ASFIFO_CTRL_WID);
}
break;
case 0x100:/* mipi in mybe need modify base on truth */
vdin_mux = VDIN_MUX_MIPI;
@@ -1568,7 +1590,8 @@ void vdin_set_matrix(struct vdin_dev_s *devp)
*/
wr_bits(offset, VDIN_MATRIX_CTRL, 0,
VDIN_MATRIX1_EN_BIT, VDIN_MATRIX1_EN_WID);
if (is_meson_g12a_cpu() || is_meson_g12b_cpu())
if (is_meson_g12a_cpu() || is_meson_g12b_cpu() ||
is_meson_sm1_cpu() || is_meson_tm2_cpu())
vdin_set_color_matrix0_g12a(devp->addr_offset,
devp->fmt_info_p,
devp->format_convert,
@@ -1601,7 +1624,8 @@ void vdin_set_matrix(struct vdin_dev_s *devp)
devp->prop.color_fmt_range,
devp->prop.vdin_hdr_Flag,
devp->color_range_mode);
if (is_meson_g12a_cpu() || is_meson_g12b_cpu())
if (is_meson_g12a_cpu() || is_meson_g12b_cpu() ||
is_meson_sm1_cpu() || is_meson_tm2_cpu())
vdin_set_color_matrix0_g12a(devp->addr_offset,
devp->fmt_info_p,
devp->format_convert,
@@ -1636,7 +1660,8 @@ void vdin_set_matrixs(struct vdin_dev_s *devp, unsigned char id,
{
switch (id) {
case 0:
if (is_meson_g12a_cpu() || is_meson_g12b_cpu())
if (is_meson_g12a_cpu() || is_meson_g12b_cpu() ||
is_meson_sm1_cpu() || is_meson_tm2_cpu())
vdin_set_color_matrix0_g12a(devp->addr_offset,
devp->fmt_info_p,
devp->format_convert,
@@ -1686,7 +1711,8 @@ void vdin_set_prob_xy(unsigned int offset,
devp->prop.color_fmt_range,
devp->prop.vdin_hdr_Flag,
devp->color_range_mode);
if (is_meson_g12a_cpu() || is_meson_g12b_cpu())
if (is_meson_g12a_cpu() || is_meson_g12b_cpu() ||
is_meson_sm1_cpu() || is_meson_tm2_cpu())
vdin_set_color_matrix0_g12a(devp->addr_offset,
devp->fmt_info_p,
devp->format_convert,
@@ -2699,6 +2725,8 @@ void vdin_set_default_regmap(unsigned int offset)
is_meson_gxtvbb_cpu() || is_meson_txl_cpu() ||
is_meson_txlx_cpu() || is_meson_tl1_cpu())
wr(offset, VDIN_LFIFO_CTRL, 0x00000f00);
else if (is_meson_tm2_cpu())
wr(offset, VDIN_LFIFO_CTRL, 0xc0020f00);
else
wr(offset, VDIN_LFIFO_CTRL, 0x00000780);
/* [15:14] clkgate.bbar = 0/(auto, off, on, on) */

50
drivers/amlogic/media/vin/tvin/vdin/vdin_drv.c
View File

@@ -296,8 +296,14 @@ static void vdin_game_mode_check(struct vdin_dev_s *devp)
(devp->parm.port != TVIN_PORT_CVBS3)) {
if (devp->h_active > 720 && ((devp->parm.info.fps == 50) ||
(devp->parm.info.fps == 60)))
devp->game_mode = (VDIN_GAME_MODE_0 | VDIN_GAME_MODE_1 |
VDIN_GAME_MODE_SWITCH_EN);
if (is_meson_tl1_cpu() || is_meson_tm2_cpu()) {
devp->game_mode = (VDIN_GAME_MODE_0 |
VDIN_GAME_MODE_1 |
VDIN_GAME_MODE_SWITCH_EN);
} else {
devp->game_mode = (VDIN_GAME_MODE_0 |
VDIN_GAME_MODE_1);
}
else
devp->game_mode = VDIN_GAME_MODE_0;
} else if (game_mode == 2)/*for debug force game mode*/
@@ -591,7 +597,7 @@ void vdin_start_dec(struct vdin_dev_s *devp)
vdin_hw_enable(devp->addr_offset);
vdin_set_all_regs(devp);
if (is_meson_tl1_cpu()) {
if (is_meson_tl1_cpu() || is_meson_tm2_cpu()) {
if (devp->afbce_mode == 0)
vdin_write_mif_or_afbce(devp, VDIN_OUTPUT_TO_MIF);
else if (devp->afbce_mode == 1)
@@ -651,7 +657,8 @@ void vdin_start_dec(struct vdin_dev_s *devp)
devp->index, jiffies_to_msecs(jiffies),
jiffies_to_msecs(jiffies)-devp->start_time);
if ((devp->afbce_mode == 1) && is_meson_tl1_cpu()) {
if ((devp->afbce_mode == 1) &&
(is_meson_tl1_cpu() || is_meson_tm2_cpu())) {
if ((devp->h_active >= 1920) && (devp->v_active >= 1080)) {
tl1_vdin1_preview_flag = 1;
tl1_vdin1_data_readied = 0;
@@ -696,7 +703,8 @@ void vdin_stop_dec(struct vdin_dev_s *devp)
disable_irq_nosync(devp->irq);
afbc_init_flag[devp->index] = 0;
if (is_meson_tl1_cpu() && (devp->afbce_mode == 1)) {
if ((is_meson_tl1_cpu() || is_meson_tm2_cpu())
&& (devp->afbce_mode == 1)) {
while (i++ < afbc_write_down_timeout) {
if (vdin_afbce_read_writedown_flag())
break;
@@ -738,7 +746,8 @@ void vdin_stop_dec(struct vdin_dev_s *devp)
vf_unreg_provider(&devp->vprov);
devp->dv.dv_config = 0;
if (is_meson_tl1_cpu() && (devp->afbce_mode == 1)) {
if ((is_meson_tl1_cpu() || is_meson_tm2_cpu())
&& (devp->afbce_mode == 1)) {
vdin_afbce_hw_disable();
vdin_afbce_soft_reset();
}
@@ -1418,7 +1427,8 @@ irqreturn_t vdin_isr(int irq, void *dev_id)
offset = devp->addr_offset;
if (is_meson_tl1_cpu() && (devp->afbce_mode == 1)) {
if ((is_meson_tl1_cpu() || is_meson_tm2_cpu())
&& (devp->afbce_mode == 1)) {
if (afbc_init_flag[devp->index] == 0) {
afbc_init_flag[devp->index] = 1;
/*set mem power on*/
@@ -1887,7 +1897,7 @@ irqreturn_t vdin_isr(int irq, void *dev_id)
vdin_vf_disp_mode_update(curr_wr_vfe, devp->vfp);
}
/*switch to game mode 2 from game mode 1,otherwise may appear blink*/
if (is_meson_tl1_cpu()) {
if (is_meson_tl1_cpu() || is_meson_tm2_cpu()) {
if (devp->game_mode & VDIN_GAME_MODE_SWITCH_EN) {
/* make sure phase lock for next few frames */
if (vlock_get_phlock_flag())
@@ -2293,7 +2303,8 @@ static int vdin_open(struct inode *inode, struct file *file)
return 0;
}
if (is_meson_tl1_cpu() && (devp->afbce_mode == 1))
if ((devp->afbce_mode == 1) &&
(is_meson_tl1_cpu() || is_meson_tm2_cpu()))
switch_vpu_mem_pd_vmod(VPU_AFBCE, VPU_MEM_POWER_ON);
devp->flags |= VDIN_FLAG_FS_OPENED;
@@ -2342,7 +2353,8 @@ static int vdin_release(struct inode *inode, struct file *file)
return 0;
}
if (is_meson_tl1_cpu() && (devp->afbce_mode == 1))
if ((devp->afbce_mode == 1) &&
(is_meson_tl1_cpu() || is_meson_tm2_cpu()))
switch_vpu_mem_pd_vmod(VPU_AFBCE, VPU_MEM_POWER_DOWN);
devp->flags &= (~VDIN_FLAG_FS_OPENED);
@@ -2991,7 +3003,11 @@ static long vdin_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
return -EFAULT;
}
memset(&param, 0, sizeof(struct vdin_parm_s));
param.port = TVIN_PORT_VIU1;
if (is_meson_tl1_cpu() || is_meson_sm1_cpu() ||
is_meson_tm2_cpu())
param.port = TVIN_PORT_VIU1_WB0_VPP;
else
param.port = TVIN_PORT_VIU1;
param.reserved |= PARAM_STATE_HISTGRAM;
param.h_active = vdin_v4l2_param.width;
param.v_active = vdin_v4l2_param.height;
@@ -3277,7 +3293,10 @@ static int vdin_drv_probe(struct platform_device *pdev)
vdevp->afbce_mode = 0;
pr_info("no afbce mode found, use normal mode\n");
} else {
if ((is_meson_tl1_cpu()) && (vdevp->index == 0)) {
vdevp->afbce_mode = val & 0xf;
vdevp->afbce_lossy_en = (val>>4)&0xf;
if ((is_meson_tl1_cpu() || is_meson_tm2_cpu()) &&
(vdevp->index == 0)) {
/* just use afbce at vdin0 */
pr_info("afbce mode = %d\n", vdevp->afbce_mode);
vdevp->afbce_info = devm_kzalloc(vdevp->dev,
@@ -3309,12 +3328,15 @@ static int vdin_drv_probe(struct platform_device *pdev)
if (is_meson_gxbb_cpu() && vdevp->index)
vdin_addr_offset[vdevp->index] = 0x70;
else if ((is_meson_g12a_cpu() || is_meson_g12b_cpu() ||
is_meson_tl1_cpu()) && vdevp->index)
is_meson_tl1_cpu() || is_meson_sm1_cpu() ||
is_meson_tm2_cpu()) && vdevp->index)
vdin_addr_offset[vdevp->index] = 0x100;
vdevp->addr_offset = vdin_addr_offset[vdevp->index];
vdevp->flags = 0;
/*canvas align number*/
if (is_meson_g12a_cpu() || is_meson_g12b_cpu() || is_meson_tl1_cpu())
if (is_meson_g12a_cpu() || is_meson_g12b_cpu() ||
is_meson_tl1_cpu() || is_meson_sm1_cpu() ||
is_meson_tm2_cpu())
vdevp->canvas_align = 64;
else
vdevp->canvas_align = 32;

14
drivers/amlogic/media/vin/tvin/viu/viuin.c
View File

@@ -178,8 +178,9 @@ static int viuin_open(struct tvin_frontend_s *fe, enum tvin_port_e port)
/*open the venc to vdin path*/
switch (rd_bits_viu(VPU_VIU_VENC_MUX_CTRL, 0, 2)) {
case 0:
if (is_meson_g12a_cpu() || is_meson_g12b_cpu()
|| is_meson_tl1_cpu())
if (is_meson_g12a_cpu() || is_meson_g12b_cpu() ||
is_meson_tl1_cpu() || is_meson_sm1_cpu() ||
is_meson_tm2_cpu())
viu_mux = 0x4;
else
viu_mux = 0x8;
@@ -213,7 +214,9 @@ static int viuin_open(struct tvin_frontend_s *fe, enum tvin_port_e port)
wr_viu(VPU_VIU2VDIN_HDN_CTRL, 0x40f00);
} else
wr_bits_viu(VPU_VIU2VDIN_HDN_CTRL, devp->parm.h_active, 0, 14);
if (is_meson_g12a_cpu() || is_meson_g12b_cpu() || is_meson_tl1_cpu()) {
if (is_meson_g12a_cpu() || is_meson_g12b_cpu() ||
is_meson_tl1_cpu() || is_meson_sm1_cpu() ||
is_meson_tm2_cpu()) {
if (((port >= TVIN_PORT_VIU1_WB0_VD1) &&
(port <= TVIN_PORT_VIU1_WB0_POST_BLEND)) ||
((port >= TVIN_PORT_VIU2_WB0_VD1) &&
@@ -308,8 +311,9 @@ static void viuin_close(struct tvin_frontend_s *fe)
if (open_cnt)
open_cnt--;
if (open_cnt == 0) {
if (is_meson_g12a_cpu() || is_meson_g12b_cpu()
|| is_meson_tl1_cpu()) {
if (is_meson_g12a_cpu() || is_meson_g12b_cpu() ||
is_meson_tl1_cpu() || is_meson_sm1_cpu() ||
is_meson_tm2_cpu()) {
wr_viu(VPU_VIU_VDIN_IF_MUX_CTRL, 0);
wr_viu(VPP_WRBAK_CTRL, 0);