From 6ac3d6c34fe5e39efe8998f3a20c7c272d7657bc Mon Sep 17 00:00:00 2001 From: Elaine Zhang Date: Mon, 23 Nov 2020 15:59:09 +0800 Subject: [PATCH] clk: rockchip: clk-cpu: fix up the pre_mux setting order Fixes: 655309b7b3f4 ("clk: rockchip: clk-cpu: add mux setting for cpu change frequency") Change-Id: Id281b0d4f874f83e61f4da898fa648cd1dbb0e9a Signed-off-by: Elaine Zhang --- drivers/clk/rockchip/clk-cpu.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/clk/rockchip/clk-cpu.c b/drivers/clk/rockchip/clk-cpu.c index 696c9fb5837d..94e3b4ca7132 100644 --- a/drivers/clk/rockchip/clk-cpu.c +++ b/drivers/clk/rockchip/clk-cpu.c @@ -217,14 +217,14 @@ static int rockchip_cpuclk_pre_rate_change(struct rockchip_cpuclk *cpuclk, } rockchip_boost_add_core_div(cpuclk->pll_hw, alt_prate); - rockchip_cpuclk_set_pre_muxs(cpuclk, rate); - /* select alternate parent */ writel(HIWORD_UPDATE(reg_data->mux_core_alt, reg_data->mux_core_mask, reg_data->mux_core_shift), cpuclk->reg_base + reg_data->core_reg); + rockchip_cpuclk_set_pre_muxs(cpuclk, rate); + spin_unlock_irqrestore(cpuclk->lock, flags); return 0; }