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arm: dts: rockchip: rk3288: Assigned i2s_src parent to GPLL

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The default parent of i2s_src is 200MHz CPLL, it doesn't meet
the constraint of fractional divider that denominator must be
20 times larger than numerator.

Change-Id: I986525ca7a92cb5883facd1b6e89079398302856
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
This commit is contained in:
Finley Xiao
2017-12-05 16:55:55 +08:00
committed by Tao Huang
parent e62d8931ec
commit 6ad0044b05
1 changed files with 2 additions and 0 deletions
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2
arch/arm/boot/dts/rk3288.dtsi
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@@ -1070,6 +1070,8 @@
dma-names = "tx", "rx";
clock-names = "i2s_hclk", "i2s_clk";
clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
assigned-clocks = <&cru SCLK_I2S_SRC>;
assigned-clock-parents = <&cru PLL_GPLL>;
pinctrl-names = "default";
pinctrl-0 = <&i2s0_bus>;
rockchip,playback-channels = <8>;