From 6ad0044b05be0b333b3ce511658cab181802782c Mon Sep 17 00:00:00 2001 From: Finley Xiao Date: Tue, 5 Dec 2017 16:55:55 +0800 Subject: [PATCH] arm: dts: rockchip: rk3288: Assigned i2s_src parent to GPLL The default parent of i2s_src is 200MHz CPLL, it doesn't meet the constraint of fractional divider that denominator must be 20 times larger than numerator. Change-Id: I986525ca7a92cb5883facd1b6e89079398302856 Signed-off-by: Finley Xiao --- arch/arm/boot/dts/rk3288.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi index 7ee2f4247629..026288e9a2c9 100644 --- a/arch/arm/boot/dts/rk3288.dtsi +++ b/arch/arm/boot/dts/rk3288.dtsi @@ -1070,6 +1070,8 @@ dma-names = "tx", "rx"; clock-names = "i2s_hclk", "i2s_clk"; clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>; + assigned-clocks = <&cru SCLK_I2S_SRC>; + assigned-clock-parents = <&cru PLL_GPLL>; pinctrl-names = "default"; pinctrl-0 = <&i2s0_bus>; rockchip,playback-channels = <8>;