diff --git a/MAINTAINERS b/MAINTAINERS index b974a989b589..e12694059412 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -13696,6 +13696,9 @@ AMLOGIC GPU DEVICETREE M: Jiyu Yang F: arch/arm64/boot/dts/amlogic/mesongxtvbb-gpu-t83x.dtsi F: arch/arm64/boot/dts/amlogic/mesong12a-bifrost.dtsi +F: arch/arm/boot/dts/amlogic/mesongxtvbb-gpu-t83x.dtsi +F: arch/arm/boot/dts/amlogic/mesongxm-gpu-t83x.dtsi +F: arch/arm/boot/dts/amlogic/mesong12a-bifrost.dtsi AMLOGIC GPU SYSTRACE M: Binqi Zhang diff --git a/arch/arm/boot/dts/amlogic/mesong12a-bifrost.dtsi b/arch/arm/boot/dts/amlogic/mesong12a-bifrost.dtsi new file mode 100644 index 000000000000..371a634836dd --- /dev/null +++ b/arch/arm/boot/dts/amlogic/mesong12a-bifrost.dtsi @@ -0,0 +1,128 @@ +/* + * arch/arm64/boot/dts/amlogic/mesong12a-bifrost.dtsi + * + * Copyright (C) 2017 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +/ { + + gpu:bifrost { + compatible = "arm,malit60x", "arm,malit6xx", "arm,mali-midgard"; + #cooling-cells = <2>; /* min followed by max */ + reg = <0xFFE40000 0x04000>, /*mali APB bus base address*/ + <0xFFD01000 0x01000>, /*reset register*/ + <0xFF800000 0x01000>, /*aobus for gpu pmu domain*/ + <0xFF63c000 0x01000>, /*hiubus for gpu clk cntl*/ + <0xFFD01000 0x01000>; /*reset register*/ + interrupt-parent = <&gic>; + interrupts = <0 160 4>, <0 161 4>, <0 162 4>; + interrupt-names = "GPU", "MMU", "JOB"; + /* ACE-Lite = 0; ACE = 1; No-coherency = 31; */ + /* system-coherency = <31>; */ + + num_of_pp = <2>; + sc_mpp = <1>; /* number of shader cores used most of time. */ + clocks = <&clkc CLKID_GPU_MUX &clkc CLKID_GP0_PLL>; + clock-names = "gpu_mux","gp0_pll"; + + + tbl = <&dvfs285_cfg + &dvfs400_cfg + &dvfs500_cfg + &dvfs666_cfg + &dvfs850_cfg + &dvfs850_cfg>; + + dvfs125_cfg:clk125_cfg { + clk_freq = <125000000>; + clk_parent = "fclk_div4"; + clkp_freq = <500000000>; + clk_reg = <0xA03>; + voltage = <1150>; + keep_count = <5>; + threshold = <30 120>; + }; + + dvfs250_cfg:dvfs250_cfg { + clk_freq = <250000000>; + clk_parent = "fclk_div4"; + clkp_freq = <500000000>; + clk_reg = <0xA01>; + voltage = <1150>; + keep_count = <5>; + threshold = <80 170>; + }; + + dvfs285_cfg:dvfs285_cfg { + clk_freq = <285714285>; + clk_parent = "fclk_div7"; + clkp_freq = <285714285>; + clk_reg = <0xE00>; + voltage = <1150>; + keep_count = <5>; + threshold = <100 190>; + }; + + dvfs400_cfg:dvfs400_cfg { + clk_freq = <400000000>; + clk_parent = "fclk_div5"; + clkp_freq = <400000000>; + clk_reg = <0xC00>; + voltage = <1150>; + keep_count = <5>; + threshold = <152 207>; + }; + + dvfs500_cfg:dvfs500_cfg { + clk_freq = <500000000>; + clk_parent = "fclk_div4"; + clkp_freq = <500000000>; + clk_reg = <0xA00>; + voltage = <1150>; + keep_count = <5>; + threshold = <180 220>; + }; + + dvfs666_cfg:dvfs666_cfg { + clk_freq = <666666666>; + clk_parent = "fclk_div3"; + clkp_freq = <666666666>; + clk_reg = <0x800>; + voltage = <1150>; + keep_count = <5>; + threshold = <210 236>; + }; + + dvfs800_cfg:dvfs800_cfg { + clk_freq = <800000000>; + clk_parent = "fclk_div2p5"; + clkp_freq = <800000000>; + clk_reg = <0x600>; + voltage = <1150>; + keep_count = <5>; + threshold = <230 255>; + }; + + dvfs850_cfg:dvfs850_cfg { + clk_freq = <846000000>; + clk_parent = "gp0_pll"; + clkp_freq = <846000000>; + clk_reg = <0x200>; + voltage = <1150>; + keep_count = <5>; + threshold = <230 255>; + }; + }; + +};/* end of / */ diff --git a/arch/arm/boot/dts/amlogic/mesongxm-gpu-t82x.dtsi b/arch/arm/boot/dts/amlogic/mesongxm-gpu-t82x.dtsi new file mode 100644 index 000000000000..e9fad7b0d4d5 --- /dev/null +++ b/arch/arm/boot/dts/amlogic/mesongxm-gpu-t82x.dtsi @@ -0,0 +1,110 @@ +/* + * Amlogic GXTVBB Platform gpu + * + * Copyright (c) 2015-2017 Amlogic Ltd + * + * This file is licensed under a dual GPLv2 or BSD license. + * + */ + +/ { + t82x_gpu:t82x@d00c0000{ + compatible = "arm,malit602", "arm,malit60x", + "arm,malit6xx", "arm,mali-midgard"; + #cooling-cells = <2>; /* min followed by max */ + reg = <0xd00c0000 0x100000>, + <0xc1104440 0x001000>, + <0xc8100000 0x001000>, + <0xc883c000 0x001000>, /* hiubus for gpu clk cntl*/ + <0xc1104440 0x001000>; + interrupt-parent = <&gic>; + interrupts = <0 160 4>, <0 161 4>, <0 162 4>; + interrupt-names = "GPU", "MMU", "JOB"; + num_of_pp = <3>; + sc_mpp = <1>; /* number of shader cores used most of time. */ + /* mali-supply = <&vdd_mali>; */ + operating-points = < + /* KHz uV */ + 666666 1000000 + 500000 1000000 + 400000 1000000 + 285714 1000000 + 250000 1000000 + 125000 1000000 + >; + + tbl = <&dvfs125_cfg + &dvfs285_cfg + &dvfs400_cfg + &dvfs500_cfg + &dvfs666_cfg + &dvfs750_cfg>; + + clocks = <&clkc CLKID_GPU_MUX &clkc CLKID_GP0_PLL>; + clock-names = "gpu_mux","gp0_pll"; + + dvfs125_cfg:clk125_cfg { + clk_freq = <125000000>; + clk_parent = "fclk_div4"; + clkp_freq = <500000000>; + voltage = <1150>; + keep_count = <5>; + threshold = <30 120>; + }; + + dvfs250_cfg:dvfs250_cfg { + clk_freq = <250000000>; + clk_parent = "fclk_div4"; + clkp_freq = <500000000>; + voltage = <1150>; + keep_count = <5>; + threshold = <80 170>; + }; + + dvfs285_cfg:dvfs285_cfg { + clk_freq = <285714285>; + clk_parent = "fclk_div7"; + clkp_freq = <285714285>; + voltage = <1150>; + keep_count = <5>; + threshold = <100 190>; + }; + + dvfs400_cfg:dvfs400_cfg { + clk_freq = <400000000>; + clk_parent = "fclk_div5"; + clkp_freq = <400000000>; + voltage = <1150>; + keep_count = <5>; + threshold = <152 207>; + }; + + dvfs500_cfg:dvfs500_cfg { + clk_freq = <500000000>; + clk_parent = "fclk_div4"; + clkp_freq = <500000000>; + voltage = <1150>; + keep_count = <5>; + threshold = <180 220>; + }; + + dvfs666_cfg:dvfs666_cfg { + clk_freq = <666666666>; + clk_parent = "fclk_div3"; + clkp_freq = <666666666>; + voltage = <1150>; + keep_count = <5>; + threshold = <210 236>; + }; + + dvfs750_cfg:dvfs750_cfg { + clk_freq = <744000000>; + clk_parent = "gp0_pll"; + clkp_freq = <744000000>; + voltage = <1150>; + keep_count = <5>; + threshold = <230 255>; + }; + }; + +};/* end of / */ diff --git a/arch/arm/boot/dts/amlogic/mesongxtvbb-gpu-t83x.dtsi b/arch/arm/boot/dts/amlogic/mesongxtvbb-gpu-t83x.dtsi new file mode 100644 index 000000000000..23ff90f89688 --- /dev/null +++ b/arch/arm/boot/dts/amlogic/mesongxtvbb-gpu-t83x.dtsi @@ -0,0 +1,110 @@ +/* + * Amlogic GXTVBB Platform gpu + * + * Copyright (c) 2015-2017 Amlogic Ltd + * + * This file is licensed under a dual GPLv2 or BSD license. + * + */ + +/ { + t83x_gpu:t83x@d00c0000{ + compatible = "arm,malit602", "arm,malit60x", + "arm,malit6xx", "arm,mali-midgard"; + #cooling-cells = <2>; /* min followed by max */ + reg = <0xd00c0000 0x100000>, + <0xc1104440 0x001000>, + <0xc8100000 0x001000>, + <0xc883c000 0x001000>, /* hiubus for gpu clk cntl*/ + <0xc1104440 0x001000>; + interrupt-parent = <&gic>; + interrupts = <0 160 4>, <0 161 4>, <0 162 4>; + interrupt-names = "GPU", "MMU", "JOB"; + num_of_pp = <2>; + sc_mpp = <1>; /* number of shader cores used most of time. */ + /* mali-supply = <&vdd_mali>; */ + operating-points = < + /* KHz uV */ + 666666 1000000 + 500000 1000000 + 400000 1000000 + 285714 1000000 + 250000 1000000 + 125000 1000000 + >; + + tbl = <&dvfs125_cfg + &dvfs285_cfg + &dvfs400_cfg + &dvfs500_cfg + &dvfs666_cfg + &dvfs666_cfg>; + + clocks = <&clkc CLKID_GPU_MUX &clkc CLKID_GP0_PLL>; + clock-names = "gpu_mux","gp0_pll"; + + dvfs125_cfg:clk125_cfg { + clk_freq = <125000000>; + clk_parent = "fclk_div4"; + clkp_freq = <500000000>; + voltage = <1150>; + keep_count = <5>; + threshold = <30 120>; + }; + + dvfs250_cfg:dvfs250_cfg { + clk_freq = <250000000>; + clk_parent = "fclk_div4"; + clkp_freq = <500000000>; + voltage = <1150>; + keep_count = <5>; + threshold = <80 170>; + }; + + dvfs285_cfg:dvfs285_cfg { + clk_freq = <285714000>; + clk_parent = "fclk_div7"; + clkp_freq = <285714285>; + voltage = <1150>; + keep_count = <5>; + threshold = <100 190>; + }; + + dvfs400_cfg:dvfs400_cfg { + clk_freq = <400000000>; + clk_parent = "fclk_div5"; + clkp_freq = <400000000>; + voltage = <1150>; + keep_count = <5>; + threshold = <152 207>; + }; + + dvfs500_cfg:dvfs500_cfg { + clk_freq = <500000000>; + clk_parent = "fclk_div4"; + clkp_freq = <500000000>; + voltage = <1150>; + keep_count = <5>; + threshold = <180 220>; + }; + + dvfs666_cfg:dvfs666_cfg { + clk_freq = <666666666>; + clk_parent = "fclk_div3"; + clkp_freq = <666666666>; + voltage = <1150>; + keep_count = <5>; + threshold = <210 236>; + }; + + dvfs750_cfg:dvfs750_cfg { + clk_freq = <744000000>; + clk_parent = "gp0_pll"; + clkp_freq = <744000000>; + voltage = <1150>; + keep_count = <5>; + threshold = <230 255>; + }; + }; + +};/* end of / */ diff --git a/arch/arm/boot/dts/amlogic/mesontl1.dtsi b/arch/arm/boot/dts/amlogic/mesontl1.dtsi index 59212e7d85df..6323f11262b7 100644 --- a/arch/arm/boot/dts/amlogic/mesontl1.dtsi +++ b/arch/arm/boot/dts/amlogic/mesontl1.dtsi @@ -23,6 +23,7 @@ #include #include #include +#include "mesong12a-bifrost.dtsi" / { interrupt-parent = <&gic>;