diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt index 012e88b02219..3e09d2548df1 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.txt +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt @@ -24,6 +24,13 @@ ampire Ampire Co., Ltd. ams AMS AG amstaos AMS-Taos Inc. analogix Analogix Semiconductor, Inc. +android +android,odm +android,product +android,fstab +android,vbmeta +android,vendor +android,firmware apm Applied Micro Circuits Corporation (APM) aptina Aptina Imaging arasan Arasan Chip Systems diff --git a/MAINTAINERS b/MAINTAINERS index 474cbe35d1f1..db2f4d87a9cf 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -13539,8 +13539,8 @@ F: arch/arm/mach-meson/Makefile.boot HDMITX OUTPUT DRIVER M: Yi Zhou -M: Kaifu Hu M: Zongdong Jiao +M: Kaifu Hu S: Maintained F: drivers/amlogic/media/vout/hdmitx/* F: drivers/amlogic/media/vout/hdmitx/hdcp/* @@ -13916,6 +13916,7 @@ F: drivers/amlogic/media/enhancement/amvecm/dolby_vision/* F: drivers/amlogic/media/enhancement/amvecm/arch/* F: drivers/amlogic/media/enhancement/amvecm/dnlp_algorithm/* F: include/linux/amlogic/media/amvecm/* +F: drivers/amlogic/media/enhancement/amvecm/hdr/* AMLOGIC GXL ADD SKT DTS M: Yun Cai @@ -14174,6 +14175,7 @@ F: driver/amlogic/drm/am_meson_drv.c F: driver/amlogic/drm/am_meson_drv.h F: driver/amlogic/drm/am_meson_vpu.c F: driver/amlogic/drm/am_meson_vpu.h +F: drivers/amlogic/media/enhancement/amvecm/amvecm_drm.c AMLOGIC ADD S400EMMC DTS M: Yue Gui @@ -14280,6 +14282,7 @@ F: sound/soc/amlogic/meson/dmic.h AMLOGIC GPIO IRQ M: Xingyu Chen F: drivers/amlogic/irqchip/* +F: drivers/amlogic/irqchip/irq-meson-gpio-double-edge.c F: Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.txt AMLOGIC PINCTRL DRIVER @@ -14640,6 +14643,8 @@ AMLOGIC DTBO PARTITION M: Xindong Xu F: arch/arm64/boot/dts/amlogic/common_overlay_dt.dts F: arch/arm/boot/dts/amlogic/common_overlay_dt.dts +F: arch/arm64/boot/dts/amlogic/android_p_overlay_dt.dts +F: arch/arm/boot/dts/amlogic/android_p_overlay_dt.dts AMLOGIC DTS M: Luan Yuan @@ -14651,6 +14656,59 @@ AMLOGIC DTS M: Luan Yuan F: arch/arm/boot/dts/amlogic/partition_mbox_p241_P.dtsi +AMLOGIC TL1 SOUND CARD +M: Xing Wang +F: arch\arm\boot\dts\amlogic\mesontl1_pxp-panel.dtsi +F: drivers\amlogic\media\vout\lcd\lcd_clk_ctrl.h +F: drivers\amlogic\media\vout\lcd\lcd_debug.h +F: drivers\amlogic\media\vout\lcd\lcd_tcon.c +F: drivers\amlogic\media\vout\lcd\lcd_tcon.h + +AMLOGIC VDIN DRIVERS +M: Xuhua Zhang +F: drivers/amlogic/media/vin/tvin/vdin/vdin_afbce.c +F: drivers/amlogic/media/vin/tvin/vdin/vdin_afbce.h + +AMLOGIC MESONAXG S400 DTS +M: Yuegui He +F: arch/arm64/boot/dts/amlogic/axg_s400_v03.dts +F: arch/arm64/boot/dts/amlogic/axg_s400emmc.dts +F: arch/arm64/boot/dts/amlogic/axg_s400emmc_v03.dts + +AMLOGIC MESON DTS +M: Huan Biao +F: arch/arm64/boot/dts/amlogic/g12a_s905d2_u200_buildroot_vccktest.dts +F: arch/arm64/boot/dts/amlogic/g12b_a311d_w400_buildroot_vccktest.dts + +AMLOGIC DDR TOOL +M: wenbiao zhang +F: include/linux/amlogic/aml_dmc.h + +AMLOGIC AB UPDATE DTS +M: Xindong Xu +F: arch/arm/boot/dts/amlogic/firmware_ab.dtsi +F: arch/arm/boot/dts/amlogic/firmware_avb_ab.dtsi +F: arch/arm64/boot/dts/amlogic/firmware_ab.dtsi +F: arch/arm/boot/dts/amlogic/partition_mbox_ab_P_32.dtsi +F: arch/arm64/boot/dts/amlogic/firmware_avb_ab.dtsi +F: arch/arm64/boot/dts/amlogic/partition_mbox_ab_P_32.dtsi + +AMLOGIC BACKLIGHT LDIM DRIVER +M: Evoke Zhang +F: drivers/amlogic/media/vout/backlight/aml_ldim/ldim_spi.c + HARDKERNEL S922D odroidn2 M: Joy Cho F: arch/arm64/configs/odroidn2_defconfig diff --git a/arch/arm/Makefile b/arch/arm/Makefile index cf89fef3a24f..936ce8dd68aa 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -337,6 +337,10 @@ $(INSTALL_TARGETS): %.dtb: | scripts $(Q)$(MAKE) $(build)=$(boot)/dts/amlogic MACHINE=$(MACHINE) $(boot)/dts/amlogic/$@ +ifeq ($(CONFIG_AMLOGIC_MODIFY),y) +%.dtbo: | scripts + $(Q)$(MAKE) $(build)=$(boot)/dts/amlogic MACHINE=$(MACHINE) $(boot)/dts/amlogic/$@ +endif PHONY += dtbs dtbs_install diff --git a/arch/arm/boot/dts/amlogic/android_p_overlay_dt.dts b/arch/arm/boot/dts/amlogic/android_p_overlay_dt.dts new file mode 100644 index 000000000000..de97c56e27a1 --- /dev/null +++ b/arch/arm/boot/dts/amlogic/android_p_overlay_dt.dts @@ -0,0 +1,43 @@ +/* + * arch/arm/boot/dts/amlogic/android_p_overlay_dt.dts + * + * Copyright (C) 2017 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +/dts-v1/; +/plugin/; + +/ { + fragment@0 { + //target = <&some_node>; + target-path="/"; + __overlay__ { + dummy-battery { + compatible = "amlogic, dummy-battery"; + status = "okay"; + }; + }; + }; + + fragment@1 { + //target = <&some_node>; + target-path="/"; + __overlay__ { + dummy-charger { + compatible = "amlogic, dummy-charger"; + status = "okay"; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/amlogic/atom.dts b/arch/arm/boot/dts/amlogic/atom.dts new file mode 100644 index 000000000000..e60f6ee8ed10 --- /dev/null +++ b/arch/arm/boot/dts/amlogic/atom.dts @@ -0,0 +1,1527 @@ +/* + * arch/arm/boot/dts/amlogic/atom.dts + * + * Copyright (C) 2017 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +/dts-v1/; +#include +#include + +#include "mesontxlx.dtsi" +#include "partition_mbox_normal.dtsi" + +/ { + model = "Amlogic"; + amlogic-dt-id = "atom"; + compatible = "amlogic, txlx"; + interrupt-parent = <&gic>; + #address-cells = <1>; + #size-cells = <1>; + + aliases { + serial0 = &uart_AO; + serial1 = &uart_A; + serial2 = &uart_B; + serial3 = &uart_C; + serial4 = &uart_AO_B; + }; + + ion_dev { + compatible = "amlogic, ion_dev"; + memory-region = <&ion_reserved>; + }; + + memory@00000000 { + device_type = "memory"; + linux,usable-memory = <0x100000 0x7ff00000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + /* global autoconfigured region for contiguous allocations */ + ramoops@0x07400000 { + compatible = "ramoops"; + reg = <0x07400000 0x00100000>; + record-size = <0x8000>; + console-size = <0x8000>; + ftrace-size = <0x0>; + pmsg-size = <0x8000>; + }; + secmon_reserved:linux,secmon { + compatible = "shared-dma-pool"; + reusable; + size = <0x400000>; + alignment = <0x400000>; + alloc-ranges = <0x05000000 0x400000>; + }; + + //secos_reserved:linux,secos { + // status = "disabled"; + // compatible = "amlogic, aml_secos_memory"; + // reg = <0x0 0x05300000 0x0 0x2000000>; + // no-map; + //}; + + + + logo_reserved:linux,meson-fb { + compatible = "shared-dma-pool"; + reusable; + size = <0x800000>; + alignment = <0x400000>; + alloc-ranges = <0x7f800000 0x800000>; + }; + + //carveout_reserved:linux,carveout-reserve { + // compatible = "amlogic, idev-mem"; + // size = <0x0 0x1000>; + //}; + + ion_reserved:linux,ion-dev { + compatible = "shared-dma-pool"; + reusable; + size = <0x7C00000>; + alignment = <0x400000>; + }; + + /*di CMA pool */ + di_cma_reserved:linux,di_cma { + compatible = "shared-dma-pool"; + reusable; + /* buffer_size = 3621952(yuv422 8bit) + * | 4736064(yuv422 10bit) + * | 4179008(yuv422 10bit full pack mode) + * 10x3621952=34.6M(0x23) support 8bit + * 10x4736064=45.2M(0x2e) support 12bit + * 10x4179008=40M(0x28) support 10bit + */ + size = <0x02800000>; + alignment = <0x400000>; + }; + + /* POST PROCESS MANAGER */ + ppmgr_reserved:linux,ppmgr { + compatible = "amlogic, ppmgr_memory"; + size = <0x0>; + }; + + codec_mm_cma:linux,codec_mm_cma { + compatible = "shared-dma-pool"; + reusable; + /* ion_codec_mm max can alloc size 80M*/ + size = <0x13400000>; + alignment = <0x400000>; + linux,contiguous-region; + }; + + picdec_cma_reserved:linux,picdec { + compatible = "shared-dma-pool"; + reusable; + size = <0x0>; + alignment = <0x0>; + linux,contiguous-region; + }; + + /* codec shared reserved */ + codec_mm_reserved:linux,codec_mm_reserved { + compatible = "amlogic, codec-mm-reserved"; + size = <0x0>; + alignment = <0x100000>; + //no-map; + }; + + demod_cma_reserved:linux,demod_cma { + compatible = "shared-dma-pool"; + reusable; + /* 5M */ + size = <0x0800000>; + alignment = <0x400000>; + }; + + /* vdin1 CMA pool */ + vdin1_cma_reserved:linux,vdin1_cma { + compatible = "shared-dma-pool"; + linux,phandle = <5>; + reusable; + /* 1920x1080x2x4 =16+4 M */ + size = <0x01400000>; + alignment = <0x400000>; + }; + + /*vbi reserved mem*/ + vbi_reserved:linux,vbi { + compatible = "amlogic, vbi-mem"; + size = <0x100000>; + alloc-ranges = <0x100000 0x20000000>; + }; + }; + + /* for external keypad */ + adc_keypad { + compatible = "amlogic, adc_keypad"; + status = "okay"; + key_name = "vol+","vol-","woofer_pairing"; + key_num = <3>; + io-channels = <&saradc SARADC_CH1>, + <&saradc SARADC_CH2>; + io-channel-names = "key-chan-1", "key-chan-2"; + key_chan = ; + key_code = <115 114 600>; + key_val = <0 180 0>; //val=voltage/1800mV*1023 + key_tolerance = <40 40 40>; + }; + + gpio_keypad{ + compatible = "amlogic, gpio_keypad"; + status = "okay"; + scan_period = <20>; + key_num = <3>; + key_name = "source", "bt_paring", "mute"; + key_code = <466 218 248>; + key-gpios = <&gpio GPIODV_0 GPIO_ACTIVE_HIGH + &gpio GPIODV_1 GPIO_ACTIVE_HIGH + &gpio_ao GPIOAO_3 GPIO_ACTIVE_HIGH>; + detect_mode = <0>;/*0:polling mode, 1:irq mode*/ + }; + + gpioleds { + compatible = "gpio-leds"; + status = "okay"; + + bluetooth { + label = "bluetooth"; + gpios = <&gpio GPIODV_6 GPIO_ACTIVE_HIGH>; + default-state = "off"; /* keep/on/off */ + linux,default-trigger = "none"; + }; + + rf_white { + label = "rf_white"; + gpios = <&gpio GPIOW_11 (GPIO_OPEN_DRAIN | + GPIO_ACTIVE_HIGH)>; + default-state = "off"; /* keep/on/off */ + linux,default-trigger = "none"; + }; + + rf_amber { + label = "rf_amber"; + gpios = <&gpio GPIOZ_7 GPIO_ACTIVE_HIGH>; + default-state = "off"; /* keep/on/off */ + linux,default-trigger = "none"; + }; + + }; + + pwmleds { + compatible = "pwm-leds"; + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&pwmleds_pins>; + + sys { + active-low; + label = "sysled"; + max-brightness = <255>; + pwms = <&pwm_AO_ab 0 50000 0>; + }; + }; + + ethmac: ethernet@0xff3f0000 { + compatible = "amlogic, gxbb-eth-dwmac"; + status = "okay"; + reg = <0xff3f0000 0x10000 + 0xff634540 0x8 + 0xff634558 0xc + 0xffd01084 0x4>; + interrupts = <0 8 1 + 0 9 1>; + + phy-mode= "rmii"; + mc_val_internal_phy = <0x1804>; + mc_val_external_phy = <0x1621>; + interrupt-names = "macirq", + "phyirq"; + clocks = <&clkc CLKID_ETH_CORE>; + clock-names = "ethclk81"; + internal_phy = <1>; + }; + + vout { + compatible = "amlogic, vout"; + dev_name = "vout"; + status = "okay"; + fr_auto_policy = <0>; + }; + + meson-fb { + compatible = "amlogic, meson-txlx"; + memory-region = <&logo_reserved>; + dev_name = "meson-fb"; + status = "okay"; + interrupts = <0 3 1 + 0 89 1>; + interrupt-names = "viu-vsync", "rdma"; + mem_size = <0x00800000 0x01800000 0x00100000>; + /* uboot logo,fb0/fb1 memory size,if afbcd fb0=0x01851000*/ + display_mode_default = "1080p60hz"; + /* 0:VPU free scale 1:OSD free scale 2:OSD super scale */ + scale_mode = <1>; + /* 1920*1080*4*3 = 0x17BB000 */ + display_size_default = <1920 1080 1920 3240 32>; + pxp_mode = <0>; /** 0:normal mode 1:pxp mode */ + logo_addr = "0x7f800000"; + }; + + ge2d { + compatible = "amlogic, ge2d-txlx"; + dev_name = "ge2d"; + status = "okay"; + interrupts = <0 150 1>; + interrupt-names = "ge2d"; + clocks = <&clkc CLKID_VAPB_MUX>, + <&clkc CLKID_G2D>, + <&clkc CLKID_GE2D_GATE>; + clock-names = "clk_vapb_0", + "clk_ge2d", + "clk_ge2d_gate"; + reg = <0xff940000 0x10000>; + }; + + codec_io { + compatible = "amlogic, codec_io"; + status = "okay"; + #address-cells=<1>; + #size-cells=<1>; + ranges; + io_cbus_base{ + reg = <0xffd00000 0x100000>; + }; + io_dos_base{ + reg = <0xff620000 0x10000>; + }; + io_hiubus_base{ + reg = <0xff63c000 0x2000>; + }; + io_aobus_base{ + reg = <0xff800000 0x10000>; + }; + io_vcbus_base{ + reg = <0xff900000 0x40000>; + }; + io_dmc_base{ + reg = <0xff638000 0x2000>; + }; + }; + + codec_mm { + compatible = "amlogic, codec, mm"; + memory-region = <&codec_mm_cma &codec_mm_reserved>; + dev_name = "codec_mm"; + status = "okay"; + }; + + mesonstream { + compatible = "amlogic, codec, streambuf"; + dev_name = "mesonstream"; + status = "okay"; + clocks = <&clkc CLKID_DOS_PARSER + &clkc CLKID_DEMUX + &clkc CLKID_DOS + &clkc CLKID_VDEC_MUX + &clkc CLKID_HCODEC_MUX + &clkc CLKID_HEVC_MUX>; + clock-names = "parser_top", + "demux", + "vdec", + "clk_vdec_mux", + "clk_hcodec_mux", + "clk_hevc_mux"; + }; + + vdec { + compatible = "amlogic, vdec"; + dev_name = "vdec.0"; + status = "okay"; + interrupts = <0 3 1 + 0 23 1 + 0 32 1 + 0 43 1 + 0 44 1 + 0 45 1>; + interrupt-names = "vsync", + "demux", + "parser", + "mailbox_0", + "mailbox_1", + "mailbox_2"; + }; + + meson-amvideom { + compatible = "amlogic, amvideom"; + dev_name = "amvideom"; + status = "okay"; + interrupts = <0 3 1>; + interrupt-names = "vsync"; + }; + + + + amvideocap { + compatible = "amlogic, amvideocap"; + dev_name = "amvideocap.0"; + status = "disabled"; + max_size = <8>;//8M + }; + + picdec { + compatible = "amlogic, picdec"; + memory-region = <&picdec_cma_reserved>; + dev_name = "picdec"; + status = "disabled"; + }; + + ppmgr { + compatible = "amlogic, ppmgr"; + memory-region = <&ppmgr_reserved>; + dev_name = "ppmgr"; + status = "okay"; + }; + + deinterlace { + compatible = "amlogic, deinterlace"; + status = "okay"; + /* 0:use reserved; 1:use cma; 2:use cma as reserved */ + flag_cma = <1>; + //memory-region = <&di_reserved>; + memory-region = <&di_cma_reserved>; + interrupts = <0 46 1 + 0 6 1>; + interrupt-names = "de_irq"; + clocks = <&clkc CLKID_VPU_MUX>, + <&clkc CLKID_FCLK_DIV4>, + <&clkc CLKID_VPU_CLKB_TMP_COMP>, + <&clkc CLKID_VPU_CLKB_COMP>; + clock-names = "vpu_mux", + "fclk_div4", + "vpu_clkb_tmp_composite", + "vpu_clkb_composite"; + clock-range = <250 500>; + /* buffer-size = <3621952>;(yuv422 8bit) */ + buffer-size = <4179008>;/*yuv422 fullpack*/ + /* reserve-iomap = "true"; */ + /* if enable nr10bit, set nr10bit-support to 1 */ + nr10bit-support = <1>; + }; + ionvideo { + compatible = "amlogic, ionvideo"; + dev_name = "ionvideo"; + status = "okay"; + }; + + amlvideo { + compatible = "amlogic, amlvideo"; + dev_name = "amlvideo"; + status = "okay"; + }; + + amlvideo2_0 { + compatible = "amlogic, amlvideo2"; + dev_name = "amlvideo2"; + status = "okay"; + amlvideo2_id = <0>; + cma_mode = <1>; + }; + + amlvideo2_1 { + compatible = "amlogic, amlvideo2"; + dev_name = "amlvideo2"; + status = "okay"; + amlvideo2_id = <1>; + cma_mode = <1>; + }; + + hdmirx { + compatible = "amlogic, hdmirx_txlx"; + #address-cells=<1>; + #size-cells=<1>; + dev_name = "hdmirx"; + status = "okay"; + pinctrl-names = "hdmirx_pins"; + pinctrl-0 = <&hdmirx_a_mux &hdmirx_b_mux &hdmirx_d_mux>; + repeat = <0>; + interrupts = <0 56 1>; + clocks = <&clkc CLKID_HDMIRX_MODET_COMP>, + <&clkc CLKID_HDMIRX_CFG_COMP>, + <&clkc CLKID_HDMIRX_ACR_COMP>, + <&clkc CLKID_HDMIRX_AUDMEAS_COMP>, + <&xtal>, + <&clkc CLKID_FCLK_DIV5>, + <&clkc CLKID_FCLK_DIV7>, + <&clkc CLKID_HDCP22_SKP_COMP>, + <&clkc CLKID_HDCP22_ESM_COMP>; + // <&clkc CLK_AUD_PLL2FS>, + // <&clkc CLK_AUD_PLL4FS>, + // <&clkc CLK_AUD_OUT>; + clock-names = "hdmirx_modet_clk", + "hdmirx_cfg_clk", + "hdmirx_acr_ref_clk", + "hdmirx_audmeas_clk", + "xtal", + "fclk_div5", + "fclk_div7", + "hdcp_rx22_skp", + "hdcp_rx22_esm"; + // "hdmirx_aud_pll2fs", + // "hdmirx_aud_pll4f", + // "clk_aud_out"; + hdmirx_id = <0>; + en_4k_2_2k = <0>; + reg = <0xffd26000 0xa00000 + 0xff63C000 0x2000 + 0xffe0d000 0x2000 + 0xff63e000 0x2000 + 0x0 0x0 + 0xff634400 0x2000 + 0xff646000 0x2000>; + }; + + vdin0 { + compatible = "amlogic, vdin"; + /*memory-region = <&vdin0_cma_reserved>;*/ + dev_name = "vdin0"; + status = "okay"; + reserve-iomap = "true"; + flag_cma = <1>;/*1:share with codec_mm;2:cma alone*/ + /* MByte, if 10bit disable: 64M(YUV422), + * if 10bit enable: 64*1.5 = 96M(YUV422) + * if support 4K2K-YUV444-10bit-WR:3840*2160*4*4 ~= 128M + * if support 4K2K-YUV444-10bit-WR:3840*2160*4*6 ~= 190M + * if support 4K2K-YUV422-10bit-wr:3840*2160*3*4 ~= 96M + * if support 4K2K-YUV422-8BIT-WR:3840*2160*2*4 ~= 64M + * if support 1080p-YUV422-8BIT-WR:1920*1080*2*4 ~= 16M + */ + cma_size = <190>; + interrupts = <0 83 1>; + rdma-irq = <2>; + clocks = <&clkc CLKID_FCLK_DIV5>, + <&clkc CLKID_VDIN_MEAS_COMP>; + clock-names = "fclk_div5", "cts_vdin_meas_clk"; + vdin_id = <0>; + /* vdin write mem color depth support: + * bit0:support 8bit + * bit1:support 9bit + * bit2:support 10bit + * bit3:support 12bit + * bit4:support yuv422 10bit full pack mode (from txl new add) + */ + tv_bit_mode = <21>; + }; + + vdin1 { + compatible = "amlogic, vdin"; + memory-region = <&vdin1_cma_reserved>; + dev_name = "vdin1"; + status = "okay"; + reserve-iomap = "true"; + flag_cma = <0>;/*1:share with codec_mm;0:cma alone*/ + interrupts = <0 85 1>; + rdma-irq = <4>; + clocks = <&clkc CLKID_FCLK_DIV5>, + <&clkc CLKID_VDIN_MEAS_COMP>; + clock-names = "fclk_div5", "cts_vdin_meas_clk"; + vdin_id = <1>; + /* vdin write mem color depth support: + * bit0:support 8bit + * bit1:support 9bit + * bit2:support 10bit + * bit3:support 12bit + */ + tv_bit_mode = <1>; + }; + + tvafe { + compatible = "amlogic, tvafe-txlx"; + /*memory-region = <&tvafe_cma_reserved>;*/ + dev_name = "tvafe"; + status = "okay"; + flag_cma = <1>;/*1:share with codec_mm;0:cma alone*/ + cma_size = <5>;/*MByte*/ + reg = <0xff642000 0x2000>;/*tvafe reg base*/ + reserve-iomap = "true"; + tvafe_id = <0>; + //pinctrl-names = "default"; + /*!!particular sequence, no more and no less!!!*/ + tvafe_pin_mux = < + 3 /* TVAFE_CVBS_IN2, CVBS_IN0 = 0 */ + 1 /* TVAFE_CVBS_IN0, CVBS_IN1 */ + 2 /* TVAFE_CVBS_IN1, CVBS_IN2 */ + 4 /* TVAFE_CVBS_IN3, CVBS_IN3 */ + >; + clocks = <&clkc CLKID_DAC_CLK>; + clock-names = "vdac_clk_gate"; + }; + + vbi { + compatible = "amlogic, vbi"; + memory-region = <&vbi_reserved>; + dev_name = "vbi"; + status = "okay"; + interrupts = <0 83 1>; + reserve-iomap = "true"; + }; + + tvafe_avin_detect { + compatible = "amlogic, tvafe_avin_detect"; + dev_name = "tvafe_avin_detect"; + status = "okay"; + device_mask = <1>;/*bit0:ch1;bit1:ch2*/ + interrupts = <0 12 1>, + <0 13 1>; + }; + + amlvecm { + compatible = "amlogic, vecm"; + dev_name = "aml_vecm"; + status = "okay"; + gamma_en = <0>;/*1:enabel ;0:disable*/ + wb_en = <0>;/*1:enabel ;0:disable*/ + cm_en = <0>;/*1:enabel ;0:disable*/ + wb_sel = <0>;/*1:mtx ;0:gainoff*/ + /*0: 709/601 1: bt2020*/ + tx_op_color_primary = <1>; + /*1:enabel osd lut 100 table;0:disable*/ + cfg_en_osd_100 = <1>; + }; + amdolby_vision { + compatible = "amlogic, dolby_vision_txlx"; + dev_name = "aml_amdolby_vision_driver"; + status = "okay"; + tv_mode = <0>;/*1:enabel ;0:disable*/ + }; + amvenc_avc { + compatible = "amlogic, amvenc_avc"; + //memory-region = <&amvenc_avc_reserved>; + //memory-region = <&avc_cma_reserved>; + dev_name = "amvenc_avc"; + status = "okay"; + interrupts = <0 45 1>; + interrupt-names = "mailbox_2"; + }; + + aml_atv_demod { + compatible = "amlogic, aml_atv_demod"; + dev_name = "aml_atv_demod"; + status = "disabled"; + ////pinctrl-names="atvdemod_agc"; + ////pinctrl-0=<&atvdemod_agc>; + reg = <0xff640000 0x2000 + 0xff648000 0x2000>; + /* default:0x88188832;r840 on haier:0x48188832 */ + reg_23cf = <0x88188832>; + }; + + bt-dev { + compatible = "amlogic, bt-dev"; + dev_name = "bt-dev"; + status = "okay"; + gpio_reset = <&gpio_ao GPIOAO_13 GPIO_ACTIVE_HIGH>; + //gpio_en = <&gpio_ao GPIOAO_5 GPIO_ACTIVE_HIGH>; + }; + + rtc { + compatible = "amlogic, aml_vrtc"; + alarm_reg_addr = <0xff8000a8>; + timer_e_addr = <0xffd0f188>; + init_date = "2015/01/01"; + status = "okay"; + }; + + wifi { + compatible = "amlogic, aml_wifi"; + dev_name = "aml_wifi"; + status = "okay"; + interrupt_pin = <&gpio_ao GPIOAO_4 GPIO_ACTIVE_HIGH>; + interrupts = <0 68 4>; + irq_trigger_type = "GPIO_IRQ_HIGH"; + dhd_static_buf; + power_on_pin = <&gpio_ao GPIOAO_5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_32k_pins>; + pwm_config = <&wifi_pwm_conf>; + }; + + wifi_pwm_conf: wifi_pwm_conf { + pwm_channel1_conf { + pwms = <&pwm_cd MESON_PWM_1 30040 0>; + duty-cycle = <15020>; + times = <10>; + }; + pwm_channel2_conf { + pwms = <&pwm_cd MESON_PWM_3 30030 0>; + duty-cycle = <15015>; + times = <12>; + }; + }; + + sd_emmc_c: emmc@ffe07000 { + status = "okay"; + compatible = "amlogic, meson-mmc-txlx"; + reg = <0xffe07000 0x2000>; + interrupts = <0 218 1>; + pinctrl-names = "emmc_clk_cmd_pins", "emmc_all_pins"; + pinctrl-0 = <&emmc_clk_cmd_pins>; + pinctrl-1 = <&emmc_conf_pull_up &emmc_conf_pull_done>; + clocks = <&clkc CLKID_SD_EMMC_C>, + <&clkc CLKID_SD_EMMC_C_P0_COMP>, + <&clkc CLKID_FCLK_DIV2>, + <&clkc CLKID_FCLK_DIV5>, + <&xtal>; + clock-names = "core", "clkin0", "clkin1", "clkin2", "xtal"; + + bus-width = <8>; + cap-sd-highspeed; + cap-mmc-highspeed; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + + max-frequency = <200000000>; + non-removable; + disable-wp; + emmc { + status = "disabled"; + pinname = "emmc"; + ocr_avail = <0x200080>; /**VDD voltage 3.3 ~ 3.4 */ + caps = "MMC_CAP_8_BIT_DATA", + "MMC_CAP_MMC_HIGHSPEED", + "MMC_CAP_SD_HIGHSPEED", + "MMC_CAP_NONREMOVABLE", + "MMC_CAP_1_8V_DDR", + "MMC_CAP_HW_RESET", + "MMC_CAP_ERASE", + "MMC_CAP_CMD23"; + caps2 = "MMC_CAP2_HS200", "MMC_CAP2_HS400"; + f_min = <400000>; + f_max = <200000000>; + max_req_size = <0x20000>; /**128KB*/ + gpio_dat3 = <&gpio BOOT_3 GPIO_ACTIVE_HIGH>; + hw_reset = <&gpio BOOT_9 GPIO_ACTIVE_HIGH>; + card_type = <1>; + /* 1:mmc card(include eMMC), + * 2:sd card(include tSD) + */ + }; + }; + + sd_emmc_b: sd@ffe05000 { + status = "okay"; + compatible = "amlogic, meson-mmc-txlx"; + reg = <0xffe05000 0x2000>; + interrupts = <0 217 4>; + pinctrl-names = "sd_clk_cmd_pins", "sd_all_pins"; + pinctrl-0 = <&sd_clk_cmd_pins>; + pinctrl-1 = <&sd_all_pins>; + clocks = <&clkc CLKID_SD_EMMC_B>, + <&clkc CLKID_SD_EMMC_B_P0_COMP>, + <&clkc CLKID_FCLK_DIV2>, + <&clkc CLKID_FCLK_DIV5>, + <&xtal>; + clock-names = "core", "clkin0", "clkin1", "clkin2", "xtal"; + + bus-width = <4>; + cap-sd-highspeed; + cap-mmc-highspeed; + max-frequency = <100000000>; + non-removable; + disable-wp; + sd { + status = "disabled"; + pinname = "sd"; + ocr_avail = <0x200080>; /**VDD voltage 3.3 ~ 3.4 */ + caps = "MMC_CAP_4_BIT_DATA", + "MMC_CAP_MMC_HIGHSPEED", + "MMC_CAP_SD_HIGHSPEED", + "MMC_CAP_NONREMOVABLE", + "MMC_CAP_UHS_SDR12", + "MMC_CAP_UHS_SDR25", + "MMC_CAP_UHS_SDR50", + "MMC_CAP_UHS_SDR104", + "MMC_PM_KEEP_POWER", + "MMC_CAP_SDIO_IRQ"; + f_min = <400000>; + f_max = <200000000>; + max_req_size = <0x20000>; /**128KB*/ + card_type = <3>; + /* 3:sdio device(ie:sdio-wifi), + * 4:SD combo (IO+mem) card + * 5:NON sdio device(means sd/mmc card) + */ + }; + }; + + unifykey { + compatible = "amlogic, unifykey"; + status = "okay"; + + unifykey-num = <21>; + unifykey-index-0 = <&keysn_0>; + unifykey-index-1 = <&keysn_1>; + unifykey-index-2 = <&keysn_2>; + unifykey-index-3 = <&keysn_3>; + unifykey-index-4 = <&keysn_4>; + unifykey-index-5 = <&keysn_5>; + unifykey-index-6 = <&keysn_6>; + unifykey-index-7 = <&keysn_7>; + unifykey-index-8 = <&keysn_8>; + unifykey-index-9 = <&keysn_9>; + unifykey-index-10= <&keysn_10>; + unifykey-index-11 = <&keysn_11>; + unifykey-index-12 = <&keysn_12>; + unifykey-index-13 = <&keysn_13>; + unifykey-index-14 = <&keysn_14>; + unifykey-index-15 = <&keysn_15>; + unifykey-index-16 = <&keysn_16>; + unifykey-index-17 = <&keysn_17>; + unifykey-index-18 = <&keysn_18>; + unifykey-index-19 = <&keysn_19>; + unifykey-index-20 = <&keysn_20>; + + keysn_0: key_0{ + key-name = "usid"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_1:key_1{ + key-name = "mac"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_2:key_2{ + key-name = "hdcp"; + key-device = "secure"; + key-type = "sha1"; + key-permit = "read","write","del"; + }; + keysn_3:key_3{ + key-name = "secure_boot_set"; + key-device = "efuse"; + key-permit = "write"; + }; + keysn_4:key_4{ + key-name = "mac_bt"; + key-device = "normal"; + key-permit = "read","write","del"; + key-type = "mac"; + }; + keysn_5:key_5{ + key-name = "mac_wifi"; + key-device = "normal"; + key-permit = "read","write","del"; + key-type = "mac"; + }; + keysn_6:key_6{ + key-name = "hdcp2_tx"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_7:key_7{ + key-name = "hdcp2_rx"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_8:key_8{ + key-name = "widevinekeybox"; + key-device = "secure"; + key-type = "sha1"; + key-permit = "read","write","del"; + }; + keysn_9:key_9{ + key-name = "deviceid"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_10:key_10{ + key-name = "hdcp22_fw_private"; + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_11:key_11{ + key-name = "hdcp22_rx_private"; + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_12:key_12{ + key-name = "hdcp22_rx_fw"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_13:key_13{ + key-name = "hdcp14_rx"; + key-device = "normal"; + key-type = "sha1"; + key-permit = "read","write","del"; + }; + keysn_14:key_14{ + key-name = "prpubkeybox";// PlayReady + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_15:key_15{ + key-name = "prprivkeybox";// PlayReady + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_16: key_16{ + key-name = "region_code"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_17:key_17{ + key-name = "attestationkeybox";// attestation key + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_18:key_18{ + key-name = "hdcp22_rprx_fw"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_19:key_19{ + key-name = "hdcp22_rprp_fw"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_20:key_20{ + key-name = "hdcp22_rp_private"; + key-device = "secure"; + key-permit = "read","write","del"; + }; + + }; /* End unifykey */ + + vdac { + compatible = "amlogic, vdac"; + dev_name = "vdac"; + status = "okay"; + }; + + cvbsout { + compatible = "amlogic, cvbsout-txlx"; + dev_name = "cvbsout"; + status = "okay"; + clocks = <&clkc CLKID_VCLK2_ENCI + &clkc CLKID_VCLK2_VENCI0 + &clkc CLKID_VCLK2_VENCI1 + &clkc CLKID_DAC_CLK>; + clock-names = "venci_top_gate", + "venci_0_gate", + "venci_1_gate", + "vdac_clk_gate"; + + /* performance: reg_address, reg_value */ + performance = <0x1b56 0x343 + 0x1b05 0xf4 + 0x1c59 0xfc48 + 0x1b12 0x8c00 + 0xffff 0x0>; /* ending flag */ + }; + + amhdmitx: amhdmitx { + compatible = "amlogic, amhdmitx"; + dev_name = "amhdmitx"; + status = "okay"; + pinctrl-names="default", "hdmitx_i2c"; + pinctrl-0=<&hdmitx_hpd &hdmitx_ddc>; + pinctrl-1=<&hdmitx_hpd_gpio &i2c2_h_pins>; + clocks = <&clkc CLKID_HDCP22_SKP_COMP>, + <&clkc CLKID_HDCP22_ESM_COMP>; + clock-names = "hdcp22_tx_skp", + "hdcp22_tx_esm"; + /* HPD, 57 + 32 = 89; CEC, 151 + 32 = 183*/ + interrupts = <0 57 1>; + interrupt-names = "hdmitx_hpd"; + /* 0:M8B 1:GXBB 2:GXTVBB 3:GXL 4:GXM + * 5:TXL 6:TXLX 7:AXG 8:GXLX 9:TXHD + */ + ic_type = <6>; + //gpio_i2c_en = <0>; + //repeater_tx = <0x1>; + //#address-cells = <2>; + //#size-cells = <2>; + //ranges; + }; + + i2c_gpio: i2c_gpio { + compatible = "i2c-gpio"; + dev_name = "i2c-gpio"; + status = "disabled"; + i2c-gpio,delay-us = <10>; /* 50 kHz */ + gpios = <&gpio GPIOH_2 0 + &gpio GPIOH_3 0>; + #address-cells = <1>; + #size-cells = <1>; + i2c-gpio,timeout-ms = <10>; + i2c_gpio_edid: i2c_gpio_edid { + compatible = "i2c-gpio"; + reg = <0x50 0x0>; + }; + }; + + aocec: aocec { + compatible = "amlogic, aocec-txlx"; + device_name = "aocec"; + status = "okay"; + vendor_name = "Amlogic"; /* Max Chars: 8 */ + /* Refer to the following URL at: + * http://standards.ieee.org/develop/regauth/oui/oui.txt + */ + vendor_id = <0x000000>; + product_desc = "TXLX"; /* Max Chars: 16 */ + cec_osd_string = "AML_TV"; /* Max Chars: 14 */ + port_num = <4>; /*all port number*/ + /*ee_cec;*/ + output = <1>; + arc_port_mask = <0x8>; + interrupts = <0 205 1 + 0 199 1>; + interrupt-names = "hdmi_aocecb","hdmi_aocec"; + pinctrl-names = "default","hdmitx_aocecb","cec_pin_sleep"; + pinctrl-0=<&hdmitx_aocec>; + pinctrl-1=<&hdmitx_aocecb>; + pinctrl-2=<&hdmitx_aocecb>; + reg = <0xFF80023c 0x4 + 0xFF800000 0x400>; + reg-names = "ao_exit","ao"; + }; + + + canvas { + compatible = "amlogic, meson, canvas"; + dev_name = "amlogic-canvas"; + status = "okay"; + reg = <0xff638000 0x2000>; + }; + + rdma { + compatible = "amlogic, meson, rdma"; + dev_name = "amlogic-rdma"; + status = "okay"; + interrupts = <0 89 1>; + interrupt-names = "rdma"; + }; + + dwc3: dwc3@ff500000 { + compatible = "synopsys, dwc3"; + status = "okay"; + reg = <0xff500000 0x100000>; + interrupts = <0 30 4>; + usb-phy = <&usb2_phy>, <&usb3_phy>; + cpu-type = "gxl"; + clock-src = "usb3.0"; + }; + + usb2_phy: usb2phy@ffe09000 { + compatible = "amlogic, amlogic-new-usb2"; + status = "okay"; + portnum = <4>; + reg = <0xffe09000 0x80 + 0xffd01008 0x4>; + }; + + usb3_phy: usb3phy@ffe09080 { + compatible = "amlogic, amlogic-new-usb3"; + status = "okay"; + portnum = <0>; + reg = <0xffe09080 0x20>; + }; + + dwc2_a { + compatible = "amlogic, dwc2"; + device_name = "dwc2_a"; + reg = <0xff400000 0x40000>; + status = "okay"; + interrupts = <0 31 4>; + pl-periph-id = <0>; /** lm name */ + clock-src = "usb0"; /** clock src */ + port-id = <0>; /** ref to mach/usb.h */ + port-type = <2>; /** 0: otg, 1: host, 2: slave */ + port-speed = <0>; /** 0: default, high, 1: full */ + port-config = <0>; /** 0: default */ + /*0:default,1:single,2:incr,3:incr4,4:incr8,5:incr16,6:disable*/ + port-dma = <0>; + port-id-mode = <0>; /** 0: hardware, 1: sw_host, 2: sw_slave*/ + usb-fifo = <728>; + cpu-type = "gxl"; + /** 0: normal, 1: otg+dwc3 host only, 2: otg+dwc3 device only*/ + controller-type = <1>; + phy-reg = <0xffe09000>; + phy-reg-size = <0xa0>; + clocks = <&clkc CLKID_USB_GENERAL + &clkc CLKID_USB1_TO_DDR>; + clock-names = "usb_general", + "usb1"; + }; + + /* Sound iomap */ + aml_snd_iomap { + compatible = "amlogic, meson-snd-iomap"; + status = "okay"; + #address-cells=<1>; + #size-cells=<1>; + ranges; + io_audin_base { + reg = <0xffd03000 0x100000>; + }; + io_aiu_base { + reg = <0xFFCFFC00 0x100000>; + }; + io_eqdrc_base { + reg = <0xFFCFF000 0x100000>; + }; + io_hiu_reset_base { + reg = <0xFFCFCC00 0x100000>; + }; + io_isa_base { + reg = <0xFFD05800 0x100000>; + }; + }; + + /* AUDIO DEVICES */ + i2s_dai: I2S { + #sound-dai-cells = <0>; + /* config mpll whether same with audin */ + clocks = <&clkc CLKID_MPLL3>, + <&clkc CLKID_AMCLK_COMP>, + <&clkc CLKID_AIU_GLUE>, + <&clkc CLKID_I2S_OUT>, + <&clkc CLKID_AMCLK_MEASURE>, + <&clkc CLKID_AIFIFO2>, + <&clkc CLKID_MIXER>, + <&clkc CLKID_MIXER_IFACE>, + <&clkc CLKID_ADC>, + <&clkc CLKID_AIU_TOP>, + <&clkc CLKID_AOCLK_GATE>, + <&clkc CLKID_I2S_SPDIF>, + <&clkc CLKID_DAC_CLK>; + clock-names = "mpll", + "mclk", + "top_glue", + "i2s_out", + "amclk_measure", + "aififo2", + "aud_mixer", + "mixer_reg", + "adc", + "top_level", + "aoclk", + "aud_in", + "vdac_clk"; + compatible = "amlogic, aml-i2s-dai"; + }; + + i2s2_dai: I2S2 { + #sound-dai-cells = <0>; + /* config mpll whether same with aiu */ + clocks = <&clkc CLKID_MPLL2>, + <&clkc CLKID_AUDIN_MCLK_COMP>, + <&clkc CLKID_AUDIN_SCLK_COMP>, + <&clkc CLKID_AUDIN_LRCLK_COMP>; + clock-names = "audin_mpll", + "audin_mclk", + "audin_sclk", + "audin_lrclk"; + compatible = "amlogic, aml-i2s2-dai"; + }; + + spdif_dai: SPDIF { + #sound-dai-cells = <0>; + compatible = "amlogic, aml-spdif-dai"; + clocks = <&clkc CLKID_MPLL1>, + <&clkc CLKID_IEC958_INT_COMP>, + <&clkc CLKID_AMCLK_COMP>, + <&clkc CLKID_IEC958_MUX>, + <&clkc CLKID_CLK81>, + <&clkc CLKID_IEC958>, + <&clkc CLKID_IEC958_GATE>; + clock-names = + "mpll1", + "i958", + "mclk", + "spdif", + "clk_81", + "iec958", + "iec958_amclk"; + }; + + pcm_dai: PCM { + #sound-dai-cells = <0>; + compatible = "amlogic, aml-pcm-dai"; + pinctrl-names = "audio_pcm"; + /* disable pcm pin mux temporary, enable it if necessary */ + /*pinctrl-0 = <&aml_audio_pcm>;*/ + clocks = <&clkc CLKID_MPLL0>, + <&clkc CLKID_PCM_MCLK_COMP>, + <&clkc CLKID_PCM_SCLK_COMP>; + clock-names = "mpll0", "pcm_mclk", "pcm_sclk"; + pcm_mode = <1>; /* 0=slave mode, 1=master mode */ + }; + + i2s_plat: i2s_platform { + compatible = "amlogic, aml-i2s"; + interrupts = <0 29 1>; + }; + + pcm_plat: pcm_platform { + compatible = "amlogic, aml-pcm"; + }; + + spdif_codec: spdif_codec{ + #sound-dai-cells = <0>; + compatible = "amlogic, aml-spdif-codec"; + pinctrl-names = "audio_spdif_in"; + pinctrl-0 = <&audio_spdif_in_pins>; + }; + + pcm_codec: pcm_codec{ + #sound-dai-cells = <0>; + compatible = "amlogic, pcm2BT-codec"; + }; + /* end of AUDIO DEVICES */ + + /* AUDIO board specific */ + dummy_codec:dummy{ + #sound-dai-cells = <0>; + compatible = "amlogic, aml_dummy_codec"; + status = "okay"; + }; + + amlogic_codec:txlx_acodec{ + #sound-dai-cells = <0>; + compatible = "amlogic, txlx_acodec"; + reg = <0xFF632000 0x1c>; + status = "okay"; + }; + + aml_snd_tv { + compatible = "amlogic, txlx-snd-tv"; + status = "okay"; + aml-sound-card,format = "i2s"; + aml_sound_card,name = "AML-TVAUDIO"; + pinctrl-names = "audio_i2s"; + pinctrl-0 = <&aml_audio_i2s>; + /*avout mute gpio*/ + mute_gpio-gpios = <&gpio GPIODV_5 GPIO_ACTIVE_HIGH>; + /*switch ARC_IN & SPDIF_IN*/ + source_switch-gpios = <&gpio GPIOZ_4 GPIO_ACTIVE_HIGH>; + source_switch_inv = <1>; + sleep_time = <100>; + /*analog amp mute*/ + amp_mute_gpio-gpios = <&gpio GPIOZ_2 GPIO_ACTIVE_HIGH>; + /*aux_dev = <&cs42528>;*/ + cpu_list = <&cpudai0 &cpudai1 &cpudai2>; + codec_list = <&codec0 &codec1 &codec2>; + plat_list = <&i2s_plat &i2s_plat &i2s_plat>; + cpudai0: cpudai0 { + sound-dai = <&i2s_dai>; + }; + cpudai1: cpudai1 { + sound-dai = <&spdif_dai>; + }; + cpudai2: cpudai2 { + sound-dai = <&i2s2_dai>; + }; + codec0: codec0 { + sound-dai = <&cs42528>; + }; + codec1: codec1 { + sound-dai = <&spdif_codec>; + }; + codec2: codec2 { + sound-dai = <&dummy_codec>; + }; + Channel_Mask { + /*i2s has 4 pins, 8channel, mux output*/ + Speaker_Channel_Mask = "i2s_2/3"; + DAC0_Channel_Mask = "i2s_0/1"; + DAC1_Channel_Mask = "i2s_0/1"; + EQ_DRC_Channel_Mask = "i2s_0/1"; + Spdif_samesource_Channel_Mask = "i2s_0/1"; + }; + }; + + amaudio2 { + compatible = "amlogic, aml_amaudio2"; + status = "okay"; + interrupts = <0 48 1>; + }; + /* end of AUDIO board specific */ + + dvb { + compatible = "amlogic, dvb"; + dev_name = "dvb"; + status = "disabled"; + /*"parallel","serial","disable"*/ + ts2 = "parallel"; + ts2_control = <0>; + ts2_invert = <0>; + //resets = <&clock GCLK_IDX_DEMUX + // &clock GCLK_IDX_ASYNC_FIFO + // &clock GCLK_IDX_AHB_ARB0 + // &clock GCLK_IDX_U_PARSER_TOP>; + //reset-names = "demux", "asyncfifo", "ahbarb0", "uparsertop"; + }; + + aml_sensor0: aml-sensor@0 { + compatible = "amlogic, aml-thermal"; + device_name = "thermal"; + status = "disabled"; + #thermal-sensor-cells = <1>; + cooling_devices { + cpufreq_cool_cluster0 { + min_state = <1000000>; + dyn_coeff = <140>; + cluster_id = <0>; + node_name = "cpus"; + device_type = "cpufreq"; + }; + cpucore_cool_cluster0 { + min_state = <1>; + dyn_coeff = <0>; + cluster_id = <0>; + node_name = "cpu_core_cluster0"; + device_type = "cpucore"; + }; + gpufreq_cool { + min_state = <400>; + dyn_coeff = <437>; + cluster_id = <0>; + node_name = "mali"; + device_type = "gpufreq"; + }; + gpucore_cool { + min_state = <1>; + dyn_coeff = <0>; + cluster_id = <0>; + node_name = "thermal_gpu_cores"; + device_type = "gpucore"; + }; + }; + cpu_cluster0:cpu_core_cluster0 { + #cooling-cells = <2>; /* min followed by max */ + }; + gpucore:thermal_gpu_cores { + #cooling-cells = <2>; /* min followed by max */ + }; + }; + + dvb { + compatible = "amlogic, dvb"; + dev_name = "dvb"; + status = "disabled"; + /*"parallel","serial","disable"*/ + ts2 = "parallel"; + ts2_control = <0>; + ts2_invert = <0>; + //resets = <&clock GCLK_IDX_DEMUX + // &clock GCLK_IDX_ASYNC_FIFO + // &clock GCLK_IDX_AHB_ARB0 + // &clock GCLK_IDX_U_PARSER_TOP>; + //reset-names = "demux", "asyncfifo", "ahbarb0", "uparsertop"; + }; + + dvbfe { + compatible = "amlogic, dvbfe"; + dev_name = "dvbfe"; + status = "disabled"; + dtv_demod0 = "AMLDEMOD"; + fe0_dtv_demod = <0>; + fe0_ts = <2>; + fe0_dev = <0>; + dtv_demod0_mem = <0>; + dtv_demod0_spectrum = <1>; + dtv_demod0_cma_flag = <1>; + dtv_demod0_cma_mem_size = <8>; + memory-region = <&demod_cma_reserved>;//<&demod_reserved>; + tuner0 = "si2151_tuner"; + tuner0_i2c_adap_id = <2>; + tuner0_i2c_addr = <0x60>; + //tuner0_reset_value = <0>; + //tuner0_reset_gpio = "GPIOY_10" ; /*GPIOX_8 76*/ + fe0_tuner = <0>; + atv_demod0 = "aml_atv_demod"; + fe0_atv_demod = <0>; + }; + + thermal-zones { + soc_thermal { + polling-delay = <1000>; + polling-delay-passive = <100>; + sustainable-power = <2150>; + + thermal-sensors = <&aml_sensor0 3>; + + trips { + switch_on: trip-point@0 { + temperature = <70000>; + hysteresis = <1000>; + type = "passive"; + }; + control: trip-point@1 { + temperature = <80000>; + hysteresis = <1000>; + type = "passive"; + }; + hot: trip-point@2 { + temperature = <85000>; + hysteresis = <5000>; + type = "hot"; + }; + critical: trip-point@3 { + temperature = <260000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + + cooling-maps { + cpufreq_cooling_map { + trip = <&control>; + cooling-device = <&cpus 0 4>; + contribution = <1024>; + }; + cpucore_cooling_map { + trip = <&control>; + cooling-device = <&cpu_cluster0 0 3>; + contribution = <1024>; + }; + gpufreq_cooling_map { + trip = <&control>; + //cooling-device = <&gpu 0 4>; + contribution = <1024>; + }; + gpucore_cooling_map { + trip = <&control>; + cooling-device = <&gpucore 0 2>; + contribution = <1024>; + }; + }; + }; + }; + +}; /* end of / */ + +&i2c0 { + status = "okay"; + pinctrl-names="default"; + pinctrl-0=<&i2c0_z_pins>; + + tas5707: tas5707@36 { + compatible = "ti,tas5707"; + #sound-dai-cells = <0>; + codec_name = "tas5707"; + reg = <0x1B>; + reset_pin = <&gpio GPIOZ_13 GPIO_ACTIVE_LOW>; + eq_enable = <0>; + drc_enable = <0>; + status = "disable"; + }; + cs42528: cs42528@4E { + compatible = "cirrus,cs42528"; + #sound-dai-cells = <0>; + codec_name = "cs42528"; + reg = <0x4E>; + reset_pin = <&gpio GPIOZ_17 GPIO_ACTIVE_LOW>; + status = "okay"; + }; +}; + +&pinctrl_periphs { + /*i2s*/ + aml_audio_i2s: aml_audio_i2s { + mux { + groups = "i2s_mclk_z", + "i2s_sclk_z", + "i2s_lrclk_z", + "i2s_dout01_z", + "i2s_dout23_z15", + "i2s_dout45_z", + "i2s_din67_z19", + "i2s_lrclk_h", + "i2s_sclk_h", + "i2s_din01_h6" + //, "i2s_dout67_z19" + //, "i2s_din23_h5" + //, "i2s_din23_h5" + //, "i2s_din67_h0" + ; + function = "i2s"; + }; + }; + /*spdif*/ + audio_spdif_in_pins: audio_spdif_in_pins { + mux { + groups = "spdif_in_z18"; + function = "spdif_in"; + }; + }; + /*pcm*/ + aml_audio_pcm: aml_audio_pcm { + mux { + groups = + "pcm_clk_a_dv", + "pcm_fs_a_dv", + "pcm_in_a_dv", + "pcm_out_a_dv"; + function = "pcm_a"; + }; + }; + spi_a_pins: spi_a { + mux { + groups = "spi_mosi_a"; + function = "spi_a"; + }; + }; +}; + +&uart_A { + status = "okay"; +}; + +&audio_data{ + status = "okay"; +}; + +&pwm_AO_ab { + status = "okay"; +}; + +&pwm_cd { + status = "okay"; +}; + +&spicc0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&spi_a_pins>; + //cs-gpios = <&gpio GPIOZ_3 0>; + spidev { + compatible = "rohm,dh2228fv"; + status = "okay"; + reg = <0>; + spi-max-frequency = <3340000>; + }; +}; + diff --git a/arch/arm/boot/dts/amlogic/axg_a113d_skt.dts b/arch/arm/boot/dts/amlogic/axg_a113d_skt.dts new file mode 100644 index 000000000000..96e74c949c3a --- /dev/null +++ b/arch/arm/boot/dts/amlogic/axg_a113d_skt.dts @@ -0,0 +1,998 @@ +/* + * arch/arm/boot/dts/amlogic/axg_a113d_skt.dts + * + * Copyright (C) 2017 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +/dts-v1/; + +#include "mesonaxg.dtsi" + +/ { + model = "Amlogic"; + amlogic-dt-id = "axg_a113d_skt_v1"; + compatible = "amlogic, axg"; + interrupt-parent = <&gic>; + #address-cells = <1>; + #size-cells = <1>; + + aliases { + serial0 = &uart_AO; + serial1 = &uart_A; + serial2 = &uart_B; + serial3 = &uart_AO_B; + }; + + memory@00000000 { + device_type = "memory"; + linux,usable-memory = <0x100000 0x3ff00000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + /* global autoconfigured region for contiguous allocations */ + ramoops@0x07400000 { + compatible = "ramoops"; + reg = <0x07400000 0x00100000>; + record-size = <0x8000>; + console-size = <0x8000>; + ftrace-size = <0x0>; + pmsg-size = <0x8000>; +}; + + secmon_reserved:linux,secmon { + compatible = "shared-dma-pool"; + reusable; + size = <0x400000>; + alignment = <0x400000>; + alloc-ranges = <0x05000000 0x400000>; + }; + + secos_reserved:linux,secos { + status = "disable"; + compatible = "amlogic, aml_secos_memory"; + reg = <0x05300000 0x2000000>; + no-map; + }; + }; + + mtd_nand { + compatible = "amlogic, aml_mtd_nand"; + dev_name = "mtdnand"; + status = "okay"; + reg = <0xFFE07800 0x200>; + interrupts = < 0 34 1 >; + pinctrl-names = "nand_rb_mod","nand_norb_mod", "nand_cs_only"; + pinctrl-0 = <&all_nand_pins>; + pinctrl-1 = <&all_nand_pins>; + pinctrl-2 = <&nand_cs_pins>; + device_id = <0>; + + /*fip/tpl configurations, must be same + * with uboot if bl_mode was set as 1 + * bl_mode: 0 compact mode; 1 descrete mode + * if bl_mode was set as 1, fip configeration will work + */ + bl_mode = <1>; + /*copy count of fip*/ + fip_copies = <4>; + /*size of each fip copy */ + fip_size = <0x200000>; + nand_clk_ctrl = <0xFFE07000>; + plat-names = "bootloader","nandnormal"; + plat-num = <2>; + plat-part-0 = <&bootloader>; + plat-part-1 = <&nandnormal>; + bootloader: bootloader{ + enable_pad ="ce0"; + busy_pad = "rb0"; + timming_mode = "mode5"; + bch_mode = "bch8_1k"; + t_rea = <20>; + t_rhoh = <15>; + chip_num = <1>; + part_num = <0>; + rb_detect = <1>; + }; + nandnormal: nandnormal{ + enable_pad ="ce0"; + busy_pad = "rb0"; + timming_mode = "mode5"; + bch_mode = "bch8_1k"; + plane_mode = "twoplane"; + t_rea = <20>; + t_rhoh = <15>; + chip_num = <2>; + part_num = <3>; + partition = <&nand_partitions>; + rb_detect = <1>; + }; + nand_partitions:nand_partition{ + /* + * if bl_mode is 1, tpl size was generate by + * fip_copies * fip_size which + * will not skip bad when calculating + * the partition size; + * + * if bl_mode is 0, + * tpl partition must be comment out. + */ + tpl{ + offset=<0x0 0x0>; + size=<0x0 0x0>; + }; + logo{ + offset=<0x0 0x0>; + size=<0x0 0x200000>; + }; + recovery{ + offset=<0x0 0x0>; + size=<0x0 0x1000000>; + }; + boot{ + offset=<0x0 0x0>; + size=<0x0 0xF00000>; + }; + system{ + offset=<0x0 0x0>; + size=<0x0 0xDC40000>; + }; + data{ + offset=<0xffffffff 0xffffffff>; + size=<0x0 0x0>; + }; + }; + }; + + ethmac: ethernet@0xff3f0000 { + compatible = "amlogic, gxbb-eth-dwmac"; + status = "disable"; + reg = <0xff3f0000 0x10000 + 0xff634540 0x8>; + interrupts = <0 8 1>; + pinctrl-names = "external_eth_pins"; + pinctrl-0 = <&external_eth_pins>; + mc_val_internal_phy = <0x1800>; + mc_val_external_phy = <0x1621>; + interrupt-names = "macirq"; + clocks = <&clkc CLKID_ETH_CORE>; + clock-names = "ethclk81"; + internal_phy=<0>; + }; + + aml_sensor0: aml-sensor@0 { + compatible = "amlogic, aml-thermal"; + device_name = "thermal"; + #thermal-sensor-cells = <1>; + cooling_devices { + cpufreq_cool_cluster0 { + min_state = <1000000>; + dyn_coeff = <140>; + cluster_id = <0>; + node_name = "cpufreq_cool0"; + device_type = "cpufreq"; + }; + cpucore_cool_cluster0 { + min_state = <1>; + dyn_coeff = <0>; + cluster_id = <0>; + node_name = "cpucore_cool0"; + device_type = "cpucore"; + }; + }; + cpufreq_cool0:cpufreq_cool0 { + #cooling-cells = <2>; /* min followed by max */ + }; + cpucore_cool0:cpucore_cool0 { + #cooling-cells = <2>; /* min followed by max */ + }; + }; + thermal-zones { + soc_thermal { + polling-delay = <1000>; + polling-delay-passive = <100>; + sustainable-power = <1050>; + + thermal-sensors = <&aml_sensor0 3>; + + trips { + switch_on: trip-point@0 { + temperature = <70000>; + hysteresis = <1000>; + type = "passive"; + }; + control: trip-point@1 { + temperature = <80000>; + hysteresis = <1000>; + type = "passive"; + }; + hot: trip-point@2 { + temperature = <85000>; + hysteresis = <5000>; + type = "hot"; + }; + critical: trip-point@3 { + temperature = <260000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + + cooling-maps { + cpufreq_cooling_map { + trip = <&control>; + cooling-device = <&cpufreq_cool0 0 4>; + contribution = <1024>; + }; + cpucore_cooling_map { + trip = <&control>; + cooling-device = <&cpucore_cool0 0 3>; + contribution = <1024>; + }; + }; + }; + }; + + dwc3: dwc3@ff500000 { + compatible = "synopsys, dwc3"; + status = "okay"; + reg = <0xff500000 0x100000>; + interrupts = <0 30 4>; + usb-phy = <&usb2_phy>, <&usb3_phy>; + cpu-type = "gxl"; + clock-src = "usb3.0"; + clocks = <&clkc CLKID_USB_GENERAL>; + clock-names = "dwc_general"; + }; + + usb2_phy: usb2phy@ffe09000 { + compatible = "amlogic, amlogic-new-usb2"; + status = "okay"; + portnum = <4>; + reg = <0xffe09000 0x80 + 0xffd01008 0x4>; + }; + usb3_phy: usb3phy@ffe09080 { + compatible = "amlogic, amlogic-new-usb3"; + status = "okay"; + portnum = <0>; + reg = <0xffe09080 0x20>; + interrupts = <0 16 4>; + otg = <1>; + gpio-vbus-power = "GPIOAO_5"; + gpios = <&gpio_ao GPIOAO_5 GPIO_ACTIVE_HIGH>; + }; + + dwc2_a { + compatible = "amlogic, dwc2"; + device_name = "dwc2_a"; + reg = <0xff400000 0x40000>; + status = "okay"; + interrupts = <0 31 4>; + pl-periph-id = <0>; /** lm name */ + clock-src = "usb0"; /** clock src */ + port-id = <0>; /** ref to mach/usb.h */ + port-type = <2>; /** 0: otg, 1: host, 2: slave */ + port-speed = <0>; /** 0: default, high, 1: full */ + port-config = <0>; /** 0: default */ + /*0:default,1:single,2:incr,3:incr4,4:incr8,5:incr16,6:disable*/ + port-dma = <0>; + port-id-mode = <0>; /** 0: hardware, 1: sw_host, 2: sw_slave*/ + usb-fifo = <728>; + cpu-type = "gxl"; + /** 0: normal, 1: otg+dwc3 host only, 2: otg+dwc3 device only*/ + controller-type = <3>; + phy-reg = <0xffe09000>; + phy-reg-size = <0xa0>; + clocks = <&clkc CLKID_USB_GENERAL + &clkc CLKID_USB1_TO_DDR + &clkc CLKID_USB1>; + clock-names = "usb_general", + "usb1", + "usb1_to_ddr"; + }; + + pcie_A: pcieA@f9800000 { + compatible = "amlogic, amlogic-pcie", "snps,dw-pcie"; + reg = <0xf9800000 0x400000 + 0xff646000 0x2000 + 0xf9f00000 0x100000 + PCIE_PHY_REG PCIE_PHY_SIZE + PCIE_RESET_REG PCIE_RESET_SIZE>; + reg-names = "elbi", "cfg", "config", "phy", "reset"; + reset-gpio = <&gpio GPIOX_19 GPIO_ACTIVE_HIGH>; + interrupts = <0 177 0>; + #interrupt-cells = <1>; + bus-range = <0x0 0xff>; + #address-cells = <3>; + #size-cells = <2>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 179 IRQ_TYPE_EDGE_RISING>; + device_type = "pci"; + ranges = <0x82000000 0 0 0xf9c00000 0 0x00300000>; + /* non-prefetchable memory */ + num-lanes = <1>; + pcie-num = <1>; + + clocks = <&clkc CLKID_USB_GENERAL + &clkc CLKID_PCIE_PLL + &clkc CLKID_MIPI_ENABLE_GATE + &clkc CLKID_MIPI_BANDGAP_GATE + &clkc CLKID_PCIE_A + &clkc CLKID_PCIE_CML_EN0>; + clock-names = "pcie_general", + "pcie_refpll", + "pcie_mipi_enable_gate", + "pcie_mipi_bandgap_gate", + "pcie", + "port"; + /*reset-gpio-type 0:Shared pad(no reset)1:OD pad2:Normal pad*/ + gpio-type = <2>; + status = "okay"; + }; + + pcie_B: pcieB@fa000000 { + compatible = "amlogic, amlogic-pcie", "snps,dw-pcie"; + reg = <0xfa000000 0x400000 + 0xff648000 0x2000 + 0xfa400000 0x100000 + PCIE_PHY_REG PCIE_PHY_SIZE + PCIE_RESET_REG PCIE_RESET_SIZE>; + reg-names = "elbi", "cfg", "config", "phy", "reset"; + reset-gpio = <&gpio GPIOX_19 GPIO_ACTIVE_HIGH>; + interrupts = <0 167 0>; + #interrupt-cells = <1>; + bus-range = <0x0 0xff>; + #address-cells = <3>; + #size-cells = <2>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 169 IRQ_TYPE_EDGE_RISING>; + device_type = "pci"; + ranges = <0x81000000 0 0 0xfa500000 0x0 0x10000 + /* downstream I/O */ + 0x82000000 0 0xfa510000 0xfa510000 0 0x002f0000>; + /* non-prefetchable memory */ + num-lanes = <1>; + pcie-num = <2>; + + clocks = <&clkc CLKID_USB_GENERAL + &clkc CLKID_PCIE_PLL + &clkc CLKID_MIPI_ENABLE_GATE + &clkc CLKID_MIPI_BANDGAP_GATE + &clkc CLKID_PCIE_B + &clkc CLKID_PCIE_CML_EN1>; + clock-names = "pcie_general", + "pcie_refpll", + "pcie_mipi_enable_gate", + "pcie_mipi_bandgap_gate", + "pcie", + "port"; + /*reset-gpio-type 0:Shared pad(no reset)1:OD pad2:Normal pad*/ + gpio-type = <0>; + status = "okay"; + }; + + uart_A: serial@ffd24000 { + compatible = "amlogic, meson-uart"; + reg = <0xffd24000 0x18>; + interrupts = <0 26 1>; + status = "disable"; + clocks = <&xtal + &clkc CLKID_UART0>; + clock-names = "clk_uart", + "clk_gate"; + fifosize = < 128 >; + pinctrl-names = "default"; + pinctrl-0 = <&a_uart_pins>; + }; + + uart_B: serial@ffd23000 { + compatible = "amlogic, meson-uart"; + reg = <0xffd23000 0x18>; + interrupts = <0 75 1>; + status = "disable"; + clocks = <&xtal + &clkc CLKID_UART1>; + clock-names = "clk_uart", + "clk_gate"; + fifosize = < 64 >; + pinctrl-names = "default"; + pinctrl-0 = <&b_uart_pins>; + }; + /* Sound iomap */ + aml_snd_iomap { + compatible = "amlogic, snd-iomap"; + status = "okay"; + #address-cells=<1>; + #size-cells=<1>; + ranges; + pdm_bus { + reg = <0xFF632000 0x2000>; + }; + audiobus_base { + reg = <0xFF642000 0x2000>; + }; + }; + pdm_codec:dummy{ + #sound-dai-cells = <0>; + compatible = "amlogic, pdm_dummy_codec"; + status = "okay"; + }; + dummy_codec:dummy{ + #sound-dai-cells = <0>; + compatible = "amlogic, aml_dummy_codec"; + status = "okay"; + }; + + auge_sound { + compatible = "amlogic, axg-sound-card"; + aml-audio-card,name = "AML-AUGESOUND"; + + aml-audio-card,dai-link@0 { + format = "dsp_a"; + mclk-fs = <512>; + //continuous-clock; + //bitclock-inversion; + //frame-inversion; + //bitclock-master = <&tdmacodec>; + //frame-master = <&tdmacodec>; + tdmacpu: cpu { + sound-dai = <&aml_tdma>; + dai-tdm-slot-tx-mask = + <1 1 1 1 1 1 1 1>; + dai-tdm-slot-rx-mask = + <1 1 1 1 1 1 1 1>; + dai-tdm-slot-num = <8>; + dai-tdm-slot-width = <32>; + system-clock-frequency = <24576000>; + }; + tdmacodec: codec { + sound-dai = <&dummy_codec &dummy_codec>; + }; + }; + + aml-audio-card,dai-link@1 { + format = "i2s"; + mclk-fs = <256>; + //continuous-clock; + //bitclock-inversion; + //frame-inversion; + //bitclock-master = <&aml_tdmb>; + //frame-master = <&aml_tdmb>; + cpu { + sound-dai = <&aml_tdmb>; + dai-tdm-slot-tx-mask = <1 1>; + dai-tdm-slot-rx-mask = <1 1>; + dai-tdm-slot-num = <2>; + dai-tdm-slot-width = <32>; + system-clock-frequency = <12288000>; + }; + codec { + sound-dai = <&dummy_codec &dummy_codec>; + }; + }; + + aml-audio-card,dai-link@2 { + format = "i2s"; + mclk-fs = <256>; + //continuous-clock; + //bitclock-inversion; + //frame-inversion; + //bitclock-master = <&aml_tdmc>; + //frame-master = <&aml_tdmc>; + cpu { + sound-dai = <&aml_tdmc>; + dai-tdm-slot-tx-mask = <1 1>; + dai-tdm-slot-rx-mask = <1 1>; + dai-tdm-slot-num = <2>; + dai-tdm-slot-width = <32>; + system-clock-frequency = <12288000>; + }; + codec { + sound-dai = <&tas5707_36 &tas5707_3a>; + }; + }; + + aml-audio-card,dai-link@3 { + mclk-fs = <64>; + cpu { + sound-dai = <&aml_pdm>; + }; + codec { + sound-dai = <&pdm_codec>; + }; + }; + + aml-audio-card,dai-link@4 { + mclk-fs = <128>; + cpu { + sound-dai = <&aml_spdif>; + system-clock-frequency = <6144000>; + }; + codec { + sound-dai = <&dummy_codec>; + }; + }; + }; + sd_emmc_c: emmc@ffe07000 { + status = "disable"; + compatible = "amlogic, meson-mmc-axg"; + reg = <0xffe07000 0x2000>; + interrupts = <0 218 1>; + pinctrl-names = "emmc_clk_cmd_pins", "emmc_all_pins"; + pinctrl-0 = <&emmc_clk_cmd_pins>; + pinctrl-1 = <&emmc_conf_pull_up &emmc_conf_pull_done>; + clocks = <&clkc CLKID_SD_EMMC_C>, + <&clkc CLKID_SD_EMMC_C_P0_COMP>, + <&clkc CLKID_FCLK_DIV2>, + <&clkc CLKID_FCLK_DIV5>, + <&xtal>; + clock-names = "core", "clkin0", "clkin1", "clkin2", "xtal"; + + bus-width = <8>; + cap-sd-highspeed; + cap-mmc-highspeed; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + + max-frequency = <200000000>; + non-removable; + disable-wp; + emmc { + pinname = "emmc"; + ocr_avail = <0x200080>; /**VDD voltage 3.3 ~ 3.4 */ + caps = "MMC_CAP_8_BIT_DATA", + "MMC_CAP_MMC_HIGHSPEED", + "MMC_CAP_SD_HIGHSPEED", + "MMC_CAP_NONREMOVABLE", + "MMC_CAP_1_8V_DDR", + "MMC_CAP_HW_RESET", + "MMC_CAP_ERASE", + "MMC_CAP_CMD23"; + /*caps2 = "MMC_CAP2_HS200", "MMC_CAP2_HS400";*/ + f_min = <400000>; + f_max = <100000000>; + max_req_size = <0x20000>; /**128KB*/ + gpio_dat3 = <&gpio BOOT_3 GPIO_ACTIVE_HIGH>; + hw_reset = <&gpio BOOT_9 GPIO_ACTIVE_HIGH>; + card_type = <1>; + /* 1:mmc card(include eMMC), + * 2:sd card(include tSD) + */ + }; + }; + + partitions: partitions{ + parts = <11>; + part-0 = <&logo>; + part-1 = <&recovery>; + part-2 = <&rsv>; + part-3 = <&tee>; + part-4 = <&crypt>; + part-5 = <&misc>; + part-6 = <&instaboot>; + part-7 = <&boot>; + part-8 = <&system>; + part-9 = <&cache>; + part-10 = <&data>; + + logo:logo{ + pname = "logo"; + size = <0x0 0x2000000>; + mask = <1>; + }; + recovery:recovery{ + pname = "recovery"; + size = <0x0 0x2000000>; + mask = <1>; + }; + rsv:rsv{ + pname = "rsv"; + size = <0x0 0x800000>; + mask = <1>; + }; + tee:tee{ + pname = "tee"; + size = <0x0 0x800000>; + mask = <1>; + }; + crypt:crypt{ + pname = "crypt"; + size = <0x0 0x2000000>; + mask = <1>; + }; + misc:misc{ + pname = "misc"; + size = <0x0 0x2000000>; + mask = <1>; + }; + instaboot:instaboot{ + pname = "instaboot"; + size = <0x0 0x400000>; + mask = <1>; + }; + boot:boot + { + pname = "boot"; + size = <0x0 0x2000000>; + mask = <1>; + }; + system:system + { + pname = "system"; + size = <0x0 0x80000000>; + mask = <1>; + }; + cache:cache + { + pname = "cache"; + size = <0x0 0x20000000>; + mask = <2>; + }; + data:data + { + pname = "data"; + size = <0xffffffff 0xffffffff>; + mask = <4>; + }; + }; + + adc_keypad { + compatible = "amlogic, adc_keypad"; + status = "okay"; + key_name = "power", "vol-", "vol+", "wifi", "<<", ">>"; + key_num = <6>; + io-channels = <&saradc SARADC_CH0>; + io-channel-names = "key-chan-0"; + key_chan = ; + key_code = <116 114 115 139 105 106>; + key_val = <0 143 266 389 512 635>; //val=voltage/1800mV*1023 + key_tolerance = <40 40 40 40 40 40>; + }; + + unifykey{ + compatible = "amlogic, unifykey"; + status = "ok"; + + unifykey-num = <6>; + unifykey-index-0 = <&keysn_0>; + unifykey-index-1 = <&keysn_1>; + unifykey-index-2 = <&keysn_2>; + unifykey-index-3 = <&keysn_3>; + unifykey-index-4 = <&keysn_4>; + unifykey-index-5 = <&keysn_5>; + + keysn_0: key_0{ + key-name = "usid"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_1:key_1{ + key-name = "mac"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_2:key_2{ + key-name = "secure_boot_set"; + key-device = "efuse"; + key-permit = "write"; + }; + keysn_3:key_3{ + key-name = "mac_bt"; + key-device = "normal"; + key-permit = "read","write","del"; + key-type = "mac"; + }; + keysn_4:key_4{ + key-name = "mac_wifi"; + key-device = "normal"; + key-permit = "read","write","del"; + key-type = "mac"; + }; + keysn_5:key_5{ + key-name = "deviceid"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + };//End unifykey + +}; /* end of / */ +&efuse { + status = "ok"; +}; + +/* Audio Related start */ +/* for spk board */ +&i2c1 { + status = "okay"; + pinctrl-names="default"; + pinctrl-0=<&b_i2c_master>; + tlv320adc3101_32: tlv320adc3101_32@30 { + compatible = "ti,tlv320adc3101"; + #sound-dai-cells = <0>; + reg = <0x32>; + status = "disabled"; + }; + + tas5707_36: tas5707_36@36 { + compatible = "ti,tas5707"; + #sound-dai-cells = <0>; + reg = <0x1b>; + status = "okay"; + reset_pin = <&gpio_ao GPIOAO_4 0>; + }; + + tas5707_3a: tas5707_3a@3a { + compatible = "ti,tas5707"; + #sound-dai-cells = <0>; + reg = <0x1d>; + status = "okay"; + }; +}; + +/* for mic board */ +&i2c_AO { + status = "okay"; + pinctrl-names="default"; + pinctrl-0=<&ao_i2c_master_pin2>; + + tlv320adc3101_30: tlv320adc3101_30@30 { + compatible = "ti,tlv320adc3101"; + #sound-dai-cells = <0>; + reg = <0x30>; + status = "okay"; + }; + tlv320adc3101_34: tlv320adc3101_34@30 { + compatible = "ti,tlv320adc3101"; + #sound-dai-cells = <0>; + reg = <0x34>; + status = "okay"; + }; + tlv320adc3101_36: tlv320adc3101_36@30 { + compatible = "ti,tlv320adc3101"; + #sound-dai-cells = <0>; + reg = <0x36>; + status = "okay"; + }; +}; + +&audiobus { + aml_tdma: tdma { + compatible = "amlogic, axg-snd-tdma"; + #sound-dai-cells = <0>; + dai-tdm-lane-slot-mask = <1>; + dai-tdm-clk-sel = <0>; + clocks = <&clkaudio CLKID_AUDIO_MCLK_A + &clkc CLKID_MPLL0>; + clock-names = "mclk", "clk_srcpll"; + pinctrl-names = "tdm_pins"; + pinctrl-0 = <&tdmout_a &tdmin_a>; + }; + + aml_tdmb: tdmb { + compatible = "amlogic, axg-snd-tdmb"; + #sound-dai-cells = <0>; + dai-tdm-lane-slot-mask = <1 1 1 1>; + dai-tdm-clk-sel = <1>; + clocks = <&clkaudio CLKID_AUDIO_MCLK_B + &clkc CLKID_MPLL1>; + clock-names = "mclk", "clk_srcpll"; + pinctrl-names = "tdm_pins"; + pinctrl-0 = <&tdmb_mclk &tdmout_b>; + }; + + aml_tdmc: tdmc { + compatible = "amlogic, axg-snd-tdmc"; + #sound-dai-cells = <0>; + dai-tdm-lane-slot-mask-in = <0 1 0 0>; + dai-tdm-lane-slot-mask-out = <1 0 1 1>; + dai-tdm-clk-sel = <2>; + clocks = <&clkaudio CLKID_AUDIO_MCLK_C + &clkc CLKID_MPLL2>; + clock-names = "mclk", "clk_srcpll"; + pinctrl-names = "tdm_pins"; + pinctrl-0 = <&tdmc_mclk &tdmout_c>;// &tdmin_c>; + }; + + aml_spdif: spdif { + compatible = "amlogic, axg-snd-spdif"; + #sound-dai-cells = <0>; + clocks = <&clkc CLKID_MPLL0 + &clkc CLKID_FCLK_DIV4 + &clkaudio CLKID_AUDIO_SPDIFIN + &clkaudio CLKID_AUDIO_SPDIFOUT + &clkaudio CLKID_AUDIO_SPDIFIN_CTRL + &clkaudio CLKID_AUDIO_SPDIFOUT_CTRL>; + clock-names = "sysclk", "fixed_clk", "gate_spdifin", + "gate_spdifout", "clk_spdifin", "clk_spdifout"; + interrupts = + ; + + interrupt-names = "irq_spdifin"; + pinctrl-names = "spdif_pins"; + pinctrl-0 = <&spdifout &spdifin>; + status = "okay"; + }; + aml_pdm: pdm { + compatible = "amlogic, axg-snd-pdm"; + #sound-dai-cells = <0>; + clocks = <&clkaudio CLKID_AUDIO_PDM + &clkc CLKID_FCLK_DIV3 + &clkc CLKID_MPLL3 + &clkaudio CLKID_AUDIO_PDMIN0 + &clkaudio CLKID_AUDIO_PDMIN1>; + clock-names = "gate", + "sysclk_srcpll", + "dclk_srcpll", + "pdm_dclk", + "pdm_sysclk"; + pinctrl-names = "pdm_pins"; + pinctrl-0 = <&pdmin>; + filter_mode = <1>; /* mode 0~4, defalut:1 */ + status = "okay"; + }; +}; /* end of audiobus */ + +&pinctrl_periphs { + tdmout_a: tdmout_a { + mux { + groups = "tdma_sclk", + "tdma_fs", + "tdma_dout0_x15"; + function = "tdma_out"; + }; + }; + + tdmin_a: tdmin_a { + mux { + groups = "tdma_din0"; + function = "tdma_in"; + }; + }; + + tdmb_mclk: tdmb_mclk { + mux { + groups = "mclk_b"; + function = "mclk_b"; + }; + }; + + tdmout_b: tdmout_b { + mux { + groups = "tdmb_sclk", + "tdmb_fs", + "tdmb_dout0", + "tdmb_dout1", + "tdmb_dout2_a12", + "tdmb_dout3_a13"; + function = "tdmb_out"; + }; + }; + + // tdmin and tdmout are the same pins. can't use at same time + /* + *tdmin_b:tdmin_b { + * mux { + * groups = "tdmb_din0", + * "tdmb_din1", + * "tdmb_din2_a12", + * "tdmb_din3_a13"; + * function = "tdmb_in"; + * }; + *}; + */ + + tdmc_mclk: tdmc_mclk { + mux { + groups = "mclk_a"; + function = "mclk_a"; + }; + }; + + tdmout_c:tdmout_c { + mux { + groups = "tdmc_sclk", + "tdmc_fs", + "tdmc_dout0", + "tdmc_dout1", + "tdmc_dout2_a6", + "tdmc_dout3_a7"; + function = "tdmc_out"; + }; + }; + + //tdmin_c:tdmin_c { + // mux { + // groups = "tdmc_din0", + // "tdmc_din1", + // "tdmc_din2_a6", + // "tdmc_din3_a7"; + // function = "tdmc_in"; + // }; + //}; + + spdifout: spidfout { + mux { + groups = "spdif_out_a20"; + function = "spdif_out"; + }; + }; + + spdifin: spidfin { + mux { + groups = "spdif_in_a19"; + function = "spdif_in"; + }; + }; + + pdmin: pdmin { + mux { + groups = "pdm_dclk_a14", + "pdm_din0", + "pdm_din1", + "pdm_din2", + "pdm_din3"; + function = "pdm"; + }; + }; +}; /* end of pinctrl_periphs */ +/* Audio Related End */ + +&spicc0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&spi0_pins>; + cs-gpios = <&gpio GPIOZ_3 0>; +}; + +&spicc1 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&spi1_x_pins>; + cs-gpios = <&gpio GPIOX_16 0>; +}; + +&aobus{ + uart_AO: serial@3000 { + compatible = "amlogic, meson-uart"; + reg = <0x3000 0x18>; + interrupts = <0 193 1>; + status = "okay"; + clocks = <&xtal>; + clock-names = "clk_uart"; + xtal_tick_en = <1>; + fifosize = < 64 >; + pinctrl-names = "default"; + pinctrl-0 = <&ao_uart_pins>; + support-sysrq = <0>; /* 0 not support , 1 support */ + }; + + uart_AO_B: serial@4000 { + compatible = "amlogic, meson-uart"; + reg = <0x4000 0x18>; + interrupts = <0 197 1>; + status = "disable"; + clocks = <&xtal>; + clock-names = "clk_uart"; + fifosize = < 64 >; + pinctrl-names = "default"; + pinctrl-0 = <&ao_b_uart_pins>; + }; +}; +&audio_data{ + status = "okay"; +}; diff --git a/arch/arm/boot/dts/amlogic/axg_a113x_skt.dts b/arch/arm/boot/dts/amlogic/axg_a113x_skt.dts new file mode 100644 index 000000000000..23aac380ea3e --- /dev/null +++ b/arch/arm/boot/dts/amlogic/axg_a113x_skt.dts @@ -0,0 +1,971 @@ +/* + * arch/arm/boot/dts/amlogic/axg_a113x_skt.dts + * + * Copyright (C) 2017 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +/dts-v1/; + +#include "mesonaxg.dtsi" + +/ { + model = "Amlogic"; + amlogic-dt-id = "axg_a113x_skt_v1"; + compatible = "amlogic, axg"; + interrupt-parent = <&gic>; + #address-cells = <1>; + #size-cells = <1>; + + aliases { + serial0 = &uart_AO; + serial1 = &uart_A; + }; + + memory@00000000 { + device_type = "memory"; + linux,usable-memory = <0x000000 0x20000000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + /* global autoconfigured region for contiguous allocations */ + ramoops@0x07400000 { + compatible = "ramoops"; + reg = <0x07400000 0x00100000>; + record-size = <0x8000>; + console-size = <0x8000>; + ftrace-size = <0x0>; + pmsg-size = <0x8000>; + }; + + secmon_reserved:linux,secmon { + compatible = "shared-dma-pool"; + reusable; + size = <0x400000>; + alignment = <0x400000>; + alloc-ranges = <0x05000000 0x400000>; + }; + + secos_reserved:linux,secos { + status = "disable"; + compatible = "amlogic, aml_secos_memory"; + reg = <0x05300000 0x2000000>; + no-map; + }; + }; + mtd_nand { + compatible = "amlogic, aml_mtd_nand"; + dev_name = "mtdnand"; + status = "okay"; + reg = <0xFFE07800 0x200>; + interrupts = < 0 34 1 >; + pinctrl-names = "nand_rb_mod","nand_norb_mod", "nand_cs_only"; + pinctrl-0 = <&all_nand_pins>; + pinctrl-1 = <&all_nand_pins>; + pinctrl-2 = <&nand_cs_pins>; + device_id = <0>; + + /*fip/tpl configurations, must be same + * with uboot if bl_mode was set as 1 + * bl_mode: 0 compact mode; 1 descrete mode + * if bl_mode was set as 1, fip configeration will work + */ + bl_mode = <1>; + /*copy count of fip*/ + fip_copies = <4>; + /*size of each fip copy */ + fip_size = <0x200000>; + nand_clk_ctrl = <0xFFE07000>; + plat-names = "bootloader","nandnormal"; + plat-num = <2>; + plat-part-0 = <&bootloader>; + plat-part-1 = <&nandnormal>; + bootloader: bootloader{ + enable_pad ="ce0"; + busy_pad = "rb0"; + timming_mode = "mode5"; + bch_mode = "bch8_1k"; + t_rea = <20>; + t_rhoh = <15>; + chip_num = <1>; + part_num = <0>; + rb_detect = <1>; + }; + nandnormal: nandnormal{ + enable_pad ="ce0"; + busy_pad = "rb0"; + timming_mode = "mode5"; + bch_mode = "bch8_1k"; + plane_mode = "twoplane"; + t_rea = <20>; + t_rhoh = <15>; + chip_num = <2>; + part_num = <3>; + partition = <&nand_partitions>; + rb_detect = <1>; + }; + nand_partitions:nand_partition{ + /* + * if bl_mode is 1, tpl size was generate by + * fip_copies * fip_size which + * will not skip bad when calculating + * the partition size; + * + * if bl_mode is 0, + * tpl partition must be comment out. + */ + tpl{ + offset=<0x0 0x0>; + size=<0x0 0x0>; + }; + logo{ + offset=<0x0 0x0>; + size=<0x0 0x200000>; + }; + recovery{ + offset=<0x0 0x0>; + size=<0x0 0x1000000>; + }; + boot{ + offset=<0x0 0x0>; + size=<0x0 0xF00000>; + }; + system{ + offset=<0x0 0x0>; + size=<0x0 0xDC40000>; + }; + data{ + offset=<0xffffffff 0xffffffff>; + size=<0x0 0x0>; + }; + }; + }; + + + aml_sensor0: aml-sensor@0 { + compatible = "amlogic, aml-thermal"; + device_name = "thermal"; + #thermal-sensor-cells = <1>; + cooling_devices { + cpufreq_cool_cluster0 { + min_state = <1000000>; + dyn_coeff = <140>; + cluster_id = <0>; + node_name = "cpufreq_cool0"; + device_type = "cpufreq"; + }; + cpucore_cool_cluster0 { + min_state = <1>; + dyn_coeff = <0>; + cluster_id = <0>; + node_name = "cpucore_cool0"; + device_type = "cpucore"; + }; + }; + cpufreq_cool0:cpufreq_cool0 { + #cooling-cells = <2>; /* min followed by max */ + }; + cpucore_cool0:cpucore_cool0 { + #cooling-cells = <2>; /* min followed by max */ + }; + }; + thermal-zones { + soc_thermal { + polling-delay = <1000>; + polling-delay-passive = <100>; + sustainable-power = <1050>; + + thermal-sensors = <&aml_sensor0 3>; + + trips { + switch_on: trip-point@0 { + temperature = <70000>; + hysteresis = <1000>; + type = "passive"; + }; + control: trip-point@1 { + temperature = <80000>; + hysteresis = <1000>; + type = "passive"; + }; + hot: trip-point@2 { + temperature = <85000>; + hysteresis = <5000>; + type = "hot"; + }; + critical: trip-point@3 { + temperature = <260000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + + cooling-maps { + cpufreq_cooling_map { + trip = <&control>; + cooling-device = <&cpufreq_cool0 0 4>; + contribution = <1024>; + }; + cpucore_cooling_map { + trip = <&control>; + cooling-device = <&cpucore_cool0 0 3>; + contribution = <1024>; + }; + }; + }; + }; + + dwc3: dwc3@ff500000 { + compatible = "synopsys, dwc3"; + status = "okay"; + reg = <0xff500000 0x100000>; + interrupts = <0 30 4>; + usb-phy = <&usb2_phy>, <&usb3_phy>; + cpu-type = "gxl"; + clock-src = "usb3.0"; + clocks = <&clkc CLKID_USB_GENERAL>; + clock-names = "dwc_general"; + }; + + usb2_phy: usb2phy@ffe09000 { + compatible = "amlogic, amlogic-new-usb2"; + status = "okay"; + portnum = <4>; + reg = <0xffe09000 0x80 + 0xffd01008 0x4>; + }; + + usb3_phy: usb3phy@ffe09080 { + compatible = "amlogic, amlogic-new-usb3"; + status = "okay"; + portnum = <0>; + reg = <0xffe09080 0x20>; + interrupts = <0 16 4>; + otg = <1>; + gpio-vbus-power = "GPIOAO_5"; + gpios = <&gpio_ao GPIOAO_5 GPIO_ACTIVE_HIGH>; + }; + + dwc2_a { + compatible = "amlogic, dwc2"; + device_name = "dwc2_a"; + reg = <0xff400000 0x40000>; + status = "okay"; + interrupts = <0 31 4>; + pl-periph-id = <0>; /** lm name */ + clock-src = "usb0"; /** clock src */ + port-id = <0>; /** ref to mach/usb.h */ + port-type = <2>; /** 0: otg, 1: host, 2: slave */ + port-speed = <0>; /** 0: default, high, 1: full */ + port-config = <0>; /** 0: default */ + /*0:default,1:single,2:incr,3:incr4,4:incr8,5:incr16,6:disable*/ + port-dma = <0>; + port-id-mode = <0>; /** 0: hardware, 1: sw_host, 2: sw_slave*/ + usb-fifo = <728>; + cpu-type = "gxl"; + /** 0: normal, 1: otg+dwc3 host only, 2: otg+dwc3 device only*/ + controller-type = <3>; + phy-reg = <0xffe09000>; + phy-reg-size = <0xa0>; + clocks = <&clkc CLKID_USB_GENERAL + &clkc CLKID_USB1_TO_DDR + &clkc CLKID_USB1>; + clock-names = "usb_general", + "usb1", + "usb1_to_ddr"; + }; + + uart_A: serial@ffd24000 { + compatible = "amlogic, meson-uart"; + reg = <0xffd24000 0x18>; + interrupts = <0 26 1>; + status = "okay"; + clocks = <&xtal + &clkc CLKID_UART0>; + clock-names = "clk_uart", + "clk_gate"; + fifosize = < 128 >; + pinctrl-names = "default"; + pinctrl-0 = <&a_uart_pins>; + }; + + uart_B: serial@ffd23000 { + compatible = "amlogic, meson-uart"; + reg = <0xffd23000 0x18>; + interrupts = <0 75 1>; + status = "disable"; + clocks = <&xtal + &clkc CLKID_UART1>; + clock-names = "clk_uart", + "clk_gate"; + fifosize = < 64 >; + pinctrl-names = "default"; + pinctrl-0 = <&b_uart_pins>; + }; + + /* Sound iomap */ + aml_snd_iomap { + compatible = "amlogic, snd-iomap"; + status = "okay"; + #address-cells=<1>; + #size-cells=<1>; + ranges; + pdm_bus { + reg = <0xFF632000 0x2000>; + }; + audiobus_base { + reg = <0xFF642000 0x2000>; + }; + }; + pdm_codec:dummy{ + #sound-dai-cells = <0>; + compatible = "amlogic, pdm_dummy_codec"; + status = "okay"; + }; + dummy_codec:dummy{ + #sound-dai-cells = <0>; + compatible = "amlogic, aml_dummy_codec"; + status = "okay"; + }; + + auge_sound { + compatible = "amlogic, axg-sound-card"; + aml-audio-card,name = "AML-AUGESOUND"; + + aml-audio-card,dai-link@0 { + format = "dsp_a"; + mclk-fs = <256>;//512 + //continuous-clock; + bitclock-inversion; + //frame-inversion; + bitclock-master = <&aml_tdma>; + frame-master = <&aml_tdma>; + cpu { + sound-dai = <&aml_tdma>; + dai-tdm-slot-tx-mask = <1 1>; + dai-tdm-slot-rx-mask = <1 1>; + dai-tdm-slot-num = <2>; + dai-tdm-slot-width = <32>; + system-clock-frequency = <12288000>; + }; + codec { + sound-dai = <&dummy_codec &dummy_codec>; + }; + }; + + aml-audio-card,dai-link@1 { + format = "i2s"; + mclk-fs = <256>; + //continuous-clock; + //bitclock-inversion; + //frame-inversion; + bitclock-master = <&aml_tdmb>; + frame-master = <&aml_tdmb>; + cpu { + sound-dai = <&aml_tdmb>; + dai-tdm-slot-tx-mask = <1 1>; + dai-tdm-slot-rx-mask = <1 1>; + dai-tdm-slot-num = <2>; + dai-tdm-slot-width = <32>; + system-clock-frequency = <12288000>; + }; + codec { + sound-dai = <&tas5707_36 &tlv320adc3101_32>; + }; + }; + + aml-audio-card,dai-link@2 { + format = "i2s"; + mclk-fs = <256>; + //continuous-clock; + /* tdmb clk using tdmc so no bclk-inv */ + //bitclock-inversion; + //frame-inversion; + bitclock-master = <&aml_tdmc>; + frame-master = <&aml_tdmc>; + cpu { + sound-dai = <&aml_tdmc>; + dai-tdm-slot-tx-mask = <1 1>; + dai-tdm-slot-rx-mask = <1 1>; + dai-tdm-slot-num = <2>; + dai-tdm-slot-width = <32>; + system-clock-frequency = <12288000>; + }; + codec { + sound-dai = <&dummy_codec>; + }; + }; + + aml-audio-card,dai-link@3 { + mclk-fs = <256>; + cpu { + sound-dai = <&aml_pdm>; + }; + codec { + sound-dai = <&pdm_codec>; + }; + }; + + /*aml-audio-card,dai-link@4 { + * mclk-fs = <128>; + * cpu { + * sound-dai = <&aml_spdif>; + * }; + * codec { + * sound-dai = <&dummy_codec>; + * }; + *}; + */ + }; + + bt-dev{ + compatible = "amlogic, bt-dev"; + dev_name = "bt-dev"; + status = "okay"; + gpio_reset = <&gpio GPIOX_21 GPIO_ACTIVE_HIGH>; + }; + + wifi{ + compatible = "amlogic, aml_wifi"; + dev_name = "aml_wifi"; + status = "okay"; + interrupt_pin = <&gpio GPIOX_6 GPIO_ACTIVE_HIGH>; + irq_trigger_type = "GPIO_IRQ_LOW"; + power_on_pin = <&gpio GPIOX_7 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_32k_pins>; + pwm_config = <&wifi_pwm_conf>; + }; + + wifi_pwm_conf:wifi_pwm_conf{ + pwm_channel1_conf { + pwms = <&pwm_ab MESON_PWM_0 30040 0>; + duty-cycle = <15020>; + times = <10>; + }; + pwm_channel2_conf { + pwms = <&pwm_ab MESON_PWM_2 30030 0>; + duty-cycle = <15015>; + times = <12>; + }; + }; + sd_emmc_c: emmc@ffe07000 { + status = "disabled"; + compatible = "amlogic, meson-mmc-axg"; + reg = <0xffe07000 0x2000>; + interrupts = <0 218 1>; + pinctrl-names = "emmc_clk_cmd_pins", "emmc_all_pins"; + pinctrl-0 = <&emmc_clk_cmd_pins>; + pinctrl-1 = <&emmc_conf_pull_up &emmc_conf_pull_done>; + clocks = <&clkc CLKID_SD_EMMC_C>, + <&clkc CLKID_SD_EMMC_C_P0_COMP>, + <&clkc CLKID_FCLK_DIV2>, + <&clkc CLKID_FCLK_DIV5>, + <&xtal>; + clock-names = "core", "clkin0", "clkin1", "clkin2", "xtal"; + + bus-width = <8>; + cap-sd-highspeed; + cap-mmc-highspeed; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + + max-frequency = <200000000>; + non-removable; + disable-wp; + emmc { + pinname = "emmc"; + ocr_avail = <0x200080>; /**VDD voltage 3.3 ~ 3.4 */ + caps = "MMC_CAP_8_BIT_DATA", + "MMC_CAP_MMC_HIGHSPEED", + "MMC_CAP_SD_HIGHSPEED", + "MMC_CAP_NONREMOVABLE", + "MMC_CAP_1_8V_DDR", + "MMC_CAP_HW_RESET", + "MMC_CAP_ERASE", + "MMC_CAP_CMD23"; + /*caps2 = "MMC_CAP2_HS200", "MMC_CAP2_HS400";*/ + f_min = <400000>; + f_max = <100000000>; + max_req_size = <0x20000>; /**128KB*/ + gpio_dat3 = <&gpio BOOT_3 GPIO_ACTIVE_HIGH>; + hw_reset = <&gpio BOOT_9 GPIO_ACTIVE_HIGH>; + card_type = <1>; + /* 1:mmc card(include eMMC), + * 2:sd card(include tSD) + */ + }; + }; + + sd_emmc_b:sdio@ffe05000 { + status = "okay"; + compatible = "amlogic, meson-mmc-axg"; + reg = <0xffe05000 0x2000>; + interrupts = <0 217 4>; + pinctrl-names = "sdio_clk_cmd_pins", "sdio_all_pins"; + pinctrl-0 = <&sdio_clk_cmd_pins>; + pinctrl-1 = <&sdio_all_pins>; + clocks = <&clkc CLKID_SD_EMMC_B>, + <&clkc CLKID_SD_EMMC_B_P0_COMP>, + <&clkc CLKID_FCLK_DIV2>; + clock-names = "core", "clkin0", "clkin1"; + + bus-width = <4>; + cap-sd-highspeed; + cap-mmc-highspeed; + max-frequency = <100000000>; + non-removable; + disable-wp; + sdio { + pinname = "sdio"; + ocr_avail = <0x200080>; /**VDD voltage 3.3 ~ 3.4 */ + caps = "MMC_CAP_4_BIT_DATA", + "MMC_CAP_MMC_HIGHSPEED", + "MMC_CAP_SD_HIGHSPEED", + "MMC_CAP_NONREMOVABLE", + "MMC_CAP_UHS_SDR12", + "MMC_CAP_UHS_SDR25", + "MMC_CAP_UHS_SDR50", + "MMC_CAP_UHS_SDR104", + "MMC_PM_KEEP_POWER", + "MMC_CAP_SDIO_IRQ"; + f_min = <400000>; + f_max = <200000000>; + max_req_size = <0x20000>; /**128KB*/ + card_type = <3>; + /* 3:sdio device(ie:sdio-wifi), + * 4:SD combo (IO+mem) card + */ + }; + }; + + adc_keypad { + compatible = "amlogic, adc_keypad"; + status = "okay"; + key_name = "power", "vol-", "vol+", "wifi", "<<", ">>"; + key_num = <6>; + io-channels = <&saradc SARADC_CH0>; + io-channel-names = "key-chan-0"; + key_chan = ; + key_code = <116 114 115 139 105 106>; + key_val = <0 143 266 389 512 635>; //val=voltage/1800mV*1023 + key_tolerance = <40 40 40 40 40 40>; + }; + + partitions: partitions{ + parts = <11>; + part-0 = <&logo>; + part-1 = <&recovery>; + part-2 = <&rsv>; + part-3 = <&tee>; + part-4 = <&crypt>; + part-5 = <&misc>; + part-6 = <&instaboot>; + part-7 = <&boot>; + part-8 = <&system>; + part-9 = <&cache>; + part-10 = <&data>; + + logo:logo{ + pname = "logo"; + size = <0x0 0x2000000>; + mask = <1>; + }; + recovery:recovery{ + pname = "recovery"; + size = <0x0 0x2000000>; + mask = <1>; + }; + rsv:rsv{ + pname = "rsv"; + size = <0x0 0x800000>; + mask = <1>; + }; + tee:tee{ + pname = "tee"; + size = <0x0 0x800000>; + mask = <1>; + }; + crypt:crypt{ + pname = "crypt"; + size = <0x0 0x2000000>; + mask = <1>; + }; + misc:misc{ + pname = "misc"; + size = <0x0 0x2000000>; + mask = <1>; + }; + instaboot:instaboot{ + pname = "instaboot"; + size = <0x0 0x400000>; + mask = <1>; + }; + boot:boot + { + pname = "boot"; + size = <0x0 0x2000000>; + mask = <1>; + }; + system:system + { + pname = "system"; + size = <0x0 0x80000000>; + mask = <1>; + }; + cache:cache + { + pname = "cache"; + size = <0x0 0x20000000>; + mask = <2>; + }; + data:data + { + pname = "data"; + size = <0xffffffff 0xffffffff>; + mask = <4>; + }; + }; + + unifykey{ + compatible = "amlogic, unifykey"; + status = "ok"; + + unifykey-num = <6>; + unifykey-index-0 = <&keysn_0>; + unifykey-index-1 = <&keysn_1>; + unifykey-index-2 = <&keysn_2>; + unifykey-index-3 = <&keysn_3>; + unifykey-index-4 = <&keysn_4>; + unifykey-index-5 = <&keysn_5>; + + keysn_0: key_0{ + key-name = "usid"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_1:key_1{ + key-name = "mac"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_2:key_2{ + key-name = "secure_boot_set"; + key-device = "efuse"; + key-permit = "write"; + }; + keysn_3:key_3{ + key-name = "mac_bt"; + key-device = "normal"; + key-permit = "read","write","del"; + key-type = "mac"; + }; + keysn_4:key_4{ + key-name = "mac_wifi"; + key-device = "normal"; + key-permit = "read","write","del"; + key-type = "mac"; + }; + keysn_5:key_5{ + key-name = "deviceid"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + };//End unifykey +}; /* end of / */ + +&efuse { + status = "ok"; +}; + +&pwm_ab { + status = "okay"; +}; +/* Audio Related start */ +/* for spk board */ +&i2c1 { + status = "okay"; + pinctrl-names="default"; + pinctrl-0=<&b_i2c_master>; + tlv320adc3101_32: tlv320adc3101_32@30 { + compatible = "ti,tlv320adc3101"; + #sound-dai-cells = <0>; + reg = <0x19>; + status = "okay"; + }; + + tas5707_36: tas5707_36@36 { + compatible = "ti,tas5707"; + #sound-dai-cells = <0>; + reg = <0x1b>; + status = "okay"; + reset_pin = <&gpio_ao GPIOAO_4 0>; + }; + + tas5707_3a: tas5707_3a@3a { + compatible = "ti,tas5707"; + #sound-dai-cells = <0>; + reg = <0x1d>; + status = "disable"; + }; +}; + +/* for mic board */ +&i2c_AO { + status = "okay"; + pinctrl-names="default"; + pinctrl-0=<&ao_i2c_master_pin2>; + + pca9557:pca9557@0x1f { + compatible = "nxp,pca9557"; + reg = <0x1f>; + status = "okay"; + }; + tlv320adc3101_30: tlv320adc3101_30@30 { + compatible = "ti,tlv320adc3101"; + #sound-dai-cells = <0>; + reg = <0x18>; + status = "disable"; + }; + tlv320adc3101_34: tlv320adc3101_34@30 { + compatible = "ti,tlv320adc3101"; + #sound-dai-cells = <0>; + reg = <0x1a>; + status = "disable"; + }; + tlv320adc3101_36: tlv320adc3101_36@30 { + compatible = "ti,tlv320adc3101"; + #sound-dai-cells = <0>; + reg = <0x1b>; + status = "disable"; + }; +}; + +&audiobus { + aml_tdma: tdma { + compatible = "amlogic, axg-snd-tdma"; + #sound-dai-cells = <0>; + dai-tdm-lane-slot-mask = <1 1 1 1>; + /* select tdm lr/bclk src, see aml_axg_tdm.c */ + dai-tdm-clk-sel = <0>; + clocks = <&clkaudio CLKID_AUDIO_MCLK_A + &clkc CLKID_MPLL0>; + clock-names = "mclk", "clk_srcpll"; + pinctrl-names = "tdm_pins"; + pinctrl-0 = <&tdmin_a &tdmout_a>; + }; + + aml_tdmb: tdmb { + compatible = "amlogic, axg-snd-tdmb"; + #sound-dai-cells = <0>; + dai-tdm-lane-slot-mask-out = <1 0>; + dai-tdm-lane-slot-mask-in = <0 1>; + dai-tdm-clk-sel = <2>; + clocks = <&clkaudio CLKID_AUDIO_MCLK_B + &clkc CLKID_MPLL1>; + clock-names = "mclk", "clk_srcpll"; + pinctrl-names = "tdm_pins"; + pinctrl-0 = <&tdmb_mclk &tdmout_b &tdmin_b>; + }; + + aml_tdmc: tdmc { + compatible = "amlogic, axg-snd-tdmc"; + #sound-dai-cells = <0>; + dai-tdm-lane-slot-mask-out = <1 0>; + dai-tdm-lane-slot-mask-in = <0 1>; + dai-tdm-clk-sel = <2>; + clocks = <&clkaudio CLKID_AUDIO_MCLK_C + &clkc CLKID_MPLL2>; + clock-names = "mclk", "clk_srcpll"; + pinctrl-names = "tdm_pins"; + pinctrl-0 = <&tdmc_mclk &tdmout_c &tdmin_c>; + }; + + aml_spdif: spdif { + compatible = "amlogic, axg-snd-spdif"; + #sound-dai-cells = <0>; + clocks = <&clkc CLKID_MPLL0 + &clkc CLKID_FCLK_DIV4 + &clkaudio CLKID_AUDIO_SPDIFIN + &clkaudio CLKID_AUDIO_SPDIFOUT + &clkaudio CLKID_AUDIO_SPDIFIN_CTRL + &clkaudio CLKID_AUDIO_SPDIFOUT_CTRL>; + clock-names = "sysclk", "fixed_clk", "gate_spdifin", + "gate_spdifout", "clk_spdifin", "clk_spdifout"; + interrupts = + ; + + interrupt-names = "irq_spdifin"; + pinctrl-names = "spdif_pins"; + pinctrl-0 = <&spdifout &spdifin>; + status = "disabled"; + }; + + aml_pdm: pdm { + compatible = "amlogic, axg-snd-pdm"; + #sound-dai-cells = <0>; + clocks = <&clkaudio CLKID_AUDIO_PDM + &clkc CLKID_FCLK_DIV3 + &clkc CLKID_MPLL3 + &clkaudio CLKID_AUDIO_PDMIN0 + &clkaudio CLKID_AUDIO_PDMIN1>; + clock-names = "gate", + "sysclk_srcpll", + "dclk_srcpll", + "pdm_dclk", + "pdm_sysclk"; + pinctrl-names = "pdm_pins"; + pinctrl-0 = <&pdmin>; + filter_mode = <1>; /* mode 0~4, defalut:1 */ + status = "okay"; + }; +}; /* end of audiobus */ + +&pinctrl_periphs { + tdmout_a: tdmout_a { + mux { + groups = "tdma_sclk", + "tdma_fs", + "tdma_dout0_x15"; + function = "tdma_out"; + }; + }; + + tdmin_a: tdmin_a { + mux { + groups = "tdma_din0"; + function = "tdma_in"; + }; + }; + + tdmb_mclk: tdmb_mclk { + mux { + groups = "mclk_b"; + function = "mclk_b"; + }; + }; + + tdmout_b: tdmout_b { + mux { + groups = "tdmb_sclk", + "tdmb_fs", + "tdmb_dout0"; + function = "tdmb_out"; + }; + }; + + // tdmin and tdmout are the same pins. can't use at same time + /* + *tdmin_b:tdmin_b { + * mux { + * groups = "tdmb_din0", + * "tdmb_din1", + * "tdmb_din2_a12", + * "tdmb_din3_a13"; + * function = "tdmb_in"; + * }; + *}; + */ + + tdmin_b: tdmin_b { + mux { + groups = "tdmb_din1"; + function = "tdmb_in"; + }; + }; + + tdmc_mclk: tdmc_mclk { + mux { + groups = "mclk_a"; + function = "mclk_a"; + }; + }; + + tdmout_c:tdmout_c { + mux { + groups = "tdmc_sclk", + "tdmc_fs", + "tdmc_dout0"; + function = "tdmc_out"; + }; + }; + + tdmin_c:tdmin_c { + mux { + groups = "tdmc_din1"; + function = "tdmc_in"; + }; + }; + + spdifout: spidfout { + mux { + groups = "spdif_out_a20"; + function = "spdif_out"; + }; + }; + + spdifin: spidfin { + mux { + groups = "spdif_in_a19"; + function = "spdif_in"; + }; + }; + + pdmin: pdmin { + mux { + groups = "pdm_dclk_a14", + "pdm_din0", + "pdm_din1", + "pdm_din2", + "pdm_din3"; + function = "pdm"; + }; + }; +}; /* end of pinctrl_periphs */ +/* Audio Related End */ + +&aobus{ + uart_AO: serial@3000 { + compatible = "amlogic, meson-uart"; + reg = <0x3000 0x18>; + interrupts = <0 193 1>; + status = "okay"; + clocks = <&xtal>; + clock-names = "clk_uart"; + xtal_tick_en = <1>; + fifosize = < 64 >; + pinctrl-names = "default"; + pinctrl-0 = <&ao_uart_pins>; + support-sysrq = <0>; /* 0 not support , 1 support */ + }; + + uart_AO_B: serial@4000 { + compatible = "amlogic, meson-uart"; + reg = <0x4000 0x18>; + interrupts = <0 197 1>; + status = "disable"; + clocks = <&xtal>; + clock-names = "clk_uart"; + fifosize = < 64 >; + pinctrl-names = "default"; + pinctrl-0 = <&ao_b_uart_pins>; + }; +}; + +&audio_data{ + status = "okay"; +}; diff --git a/arch/arm/boot/dts/amlogic/axg_pxp.dts b/arch/arm/boot/dts/amlogic/axg_pxp.dts new file mode 100644 index 000000000000..702352d18124 --- /dev/null +++ b/arch/arm/boot/dts/amlogic/axg_pxp.dts @@ -0,0 +1,628 @@ +/* + * arch/arm/boot/dts/amlogic/axg_pxp.dts + * + * Copyright (C) 2017 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +/dts-v1/; + +#include "mesonaxg.dtsi" + +/ { + model = "Amlogic"; + compatible = "amlogic, axg"; + interrupt-parent = <&gic>; + #address-cells = <1>; + #size-cells = <1>; + + aliases { + serial0 = &uart_AO; + }; + + memory@00000000 { + device_type = "memory"; + linux,usable-memory = <0x100000 0x3ff00000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + /* global autoconfigured region for contiguous allocations */ + secmon_reserved:linux,secmon { + compatible = "shared-dma-pool"; + reusable; + size = <0x400000>; + alignment = <0x400000>; + alloc-ranges = <0x05000000 0x400000>; + }; + + secos_reserved:linux,secos { + status = "disable"; + compatible = "amlogic, aml_secos_memory"; + reg = <0x05300000 0x2000000>; + no-map; + }; + fb_reserved:linux,meson-fb { + //compatible = "amlogic, fb-memory"; + //reg = <0x3e000000 0x1f00000>; + compatible = "shared-dma-pool"; + reusable; + size = <0x2000000>; + alignment = <0x400000>; + alloc-ranges = <0x3e000000 0x2000000>; + }; + }; + + + + aml_sensor0: aml-sensor@0 { + compatible = "amlogic, aml-thermal"; + device_name = "thermal"; + #thermal-sensor-cells = <1>; + cooling_devices { + cpufreq_cool_cluster0 { + min_state = <1000000>; + dyn_coeff = <140>; + cluster_id = <0>; + node_name = "cpufreq_cool0"; + device_type = "cpufreq"; + }; + cpucore_cool_cluster0 { + min_state = <1>; + dyn_coeff = <0>; + cluster_id = <0>; + node_name = "cpucore_cool0"; + device_type = "cpucore"; + }; + }; + cpufreq_cool0:cpufreq_cool0 { + #cooling-cells = <2>; /* min followed by max */ + }; + cpucore_cool0:cpucore_cool0 { + #cooling-cells = <2>; /* min followed by max */ + }; + }; + thermal-zones { + soc_thermal { + polling-delay = <1000>; + polling-delay-passive = <100>; + sustainable-power = <1050>; + + thermal-sensors = <&aml_sensor0 3>; + + trips { + switch_on: trip-point@0 { + temperature = <70000>; + hysteresis = <1000>; + type = "passive"; + }; + control: trip-point@1 { + temperature = <80000>; + hysteresis = <1000>; + type = "passive"; + }; + hot: trip-point@2 { + temperature = <85000>; + hysteresis = <5000>; + type = "hot"; + }; + critical: trip-point@3 { + temperature = <260000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + + cooling-maps { + cpufreq_cooling_map { + trip = <&control>; + cooling-device = <&cpufreq_cool0 0 4>; + contribution = <1024>; + }; + cpucore_cooling_map { + trip = <&control>; + cooling-device = <&cpucore_cool0 0 3>; + contribution = <1024>; + }; + }; + }; + }; + + pcie_A: pcie@f9800000 { + compatible = "amlogic, amlogic-pcie", "snps,dw-pcie"; + reg = <0xf9800000 0x400000 + 0xff644000 0x2000 + 0xff646000 0x2000 + 0xffd01080 0x10 + 0xf9c00000 0x100000>; + reg-names = "elbi", "phy", "cfg", "reset", "config"; + reset-gpio = <&gpio GPIOX_19 0>; + interrupts = <0 177 0>; + #interrupt-cells = <1>; + bus-range = <0x0 0xff>; + #address-cells = <3>; + #size-cells = <2>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 179 IRQ_TYPE_EDGE_RISING>; + device_type = "pci"; + ranges = <0x81000000 0 0 0xf9d00000 0x0 0x10000 + /*downstream I/O */ + 0x82000000 0 0xf9d10000 0xf9d10000 0 0x002f0000>; + /* non-prefetchable memory */ + num-lanes = <1>; + pcie-num = <1>; + + //clocks = <&clkc CLKID_PCIE_REFPLL + //&clkc CLKID_PCIE_A>; + //clock-names = "pcie_refpll", + // "pcie_a"; + + status = "disable"; + }; + pcie_B: pcie@fa000000 { + compatible = "amlogic, amlogic-pcie", "snps,dw-pcie"; + reg = <0xfa000000 0x400000 + 0xff644000 0x2000 + 0xff648000 0x2000 + 0xffd01080 0x10 + 0xfa400000 0x100000>; + reg-names = "elbi", "phy-unuse", "cfg", "reset-unuse", "config"; + interrupts = <0 167 0>; + #interrupt-cells = <1>; + bus-range = <0x0 0xff>; + #address-cells = <3>; + #size-cells = <2>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 169 IRQ_TYPE_EDGE_RISING>; + device_type = "pci"; + ranges = <0x81000000 0 0 0xfa500000 0x0 0x10000 + /* downstream I/O */ + 0x82000000 0 0xfa510000 0xfa510000 0 0x002f0000>; + /* non-prefetchable memory */ + num-lanes = <1>; + pcie-num = <2>; + + //clocks = <&clkc CLKID_PCIE_REFPLL + // &clkc CLKID_PCIE_B>; + //clock-names = "pcie_refpll", + // "pcie_b"; + + status = "disable"; + }; + + vpu { + compatible = "amlogic, vpu"; + dev_name = "vpu"; + status = "ok"; + clocks = <&clkc CLKID_VAPB_MUX + &clkc CLKID_VPU_INTR + &clkc CLKID_VPU_P0_MUX + &clkc CLKID_VPU_P1_MUX + &clkc CLKID_VPU_MUX>; + clock-names = "vapb_clk", + "vpu_intr_gate", + "vpu_clk0", + "vpu_clk1", + "vpu_clk"; + clk_level = <3>; + /* 0: 100.0M 1: 166.7M 2: 200.0M 3: 250.0M */ + }; + + meson-fb { + compatible = "amlogic, meson-axg"; + memory-region = <&fb_reserved>; + dev_name = "meson-fb"; + status = "okay"; + interrupts = <0 3 1 + 0 89 1>; + interrupt-names = "viu-vsync", "rdma"; + mem_size = <0x006AF000 0x01851000 0x00000000>; + /* uboot logo,fb0/fb1 memory size */ + display_mode_default = "1080p60hz"; + scale_mode = <0>; + /** 0:VPU free scale 1:OSD free scale 2:OSD super scale */ + display_size_default = <1920 1080 1920 3240 32>; + /*1920*1080*4*3 = 0x17BB000*/ + mem_alloc = <1>; + logo_addr = "0x3e000000"; + pxp_mode = <1>; /** 0:normal mode 1:pxp mode */ + }; + + ge2d { + compatible = "amlogic, ge2d-axg"; + dev_name = "ge2d"; + status = "okay"; + interrupts = <0 150 1>; + interrupt-names = "ge2d"; + clocks = <&clkc CLKID_VAPB_MUX>, + <&clkc CLKID_G2D>, + <&clkc CLKID_GE2D_GATE>; + clock-names = "clk_vapb_0", + "clk_ge2d", + "clk_ge2d_gate"; + reg = <0xff940000 0x10000>; + }; + + /* Sound iomap */ + aml_snd_iomap { + compatible = "amlogic, snd_iomap"; + status = "okay"; + #address-cells=<1>; + #size-cells=<1>; + ranges; + pdm_bus { + reg = <0xFF632000 0x2000>; + }; + audiobus_base { + reg = <0xFF642000 0x2000>; + }; + }; + pdm_codec:dummy{ + #sound-dai-cells = <0>; + compatible = "amlogic, pdm_dummy_codec"; + status = "okay"; + }; + dummy_codec:dummy{ + #sound-dai-cells = <0>; + compatible = "amlogic, aml_dummy_codec"; + status = "okay"; + }; + + auge_sound { + compatible = "amlogic, axg-sound-card"; + aml-audio-card,name = "AML-AUGESOUND"; + + aml-audio-card,dai-link@0 { + format = "dsp_a"; + mclk-fs = <512>; + //continuous-clock; + //bitclock-inversion; + //frame-inversion; + //bitclock-master = <&tdmacodec>; + //frame-master = <&tdmacodec>; + tdmacpu: cpu { + sound-dai = <&aml_tdma>; + dai-tdm-slot-tx-mask = + <1 1 1 1 1 1 1 1>; + dai-tdm-slot-rx-mask = + <1 1 1 1 1 1 1 1>; + dai-tdm-slot-num = <8>; + dai-tdm-slot-width = <32>; + system-clock-frequency = <24576000>; + }; + tdmacodec: codec { + sound-dai = <&dummy_codec &dummy_codec>; + }; + }; + + aml-audio-card,dai-link@1 { + format = "i2s"; + mclk-fs = <256>; + //continuous-clock; + //bitclock-inversion; + //frame-inversion; + bitclock-master = <&aml_tdmb>; + frame-master = <&aml_tdmb>; + cpu { + sound-dai = <&aml_tdmb>; + dai-tdm-slot-tx-mask = <1 1>; + dai-tdm-slot-rx-mask = <1 1>; + dai-tdm-slot-num = <2>; + dai-tdm-slot-width = <32>; + system-clock-frequency = <12288000>; + }; + codec { + sound-dai = <&dummy_codec &dummy_codec>; + }; + }; + + aml-audio-card,dai-link@2 { + format = "i2s"; + mclk-fs = <256>; + continuous-clock; + //bitclock-inversion; + //frame-inversion; + //bitclock-master = <&aml_tdmc>; + //frame-master = <&aml_tdmc>; + cpu { + sound-dai = <&aml_tdmc>; + dai-tdm-slot-tx-mask = <1 1>; + dai-tdm-slot-rx-mask = <1 1>; + dai-tdm-slot-num = <2>; + dai-tdm-slot-width = <32>; + system-clock-frequency = <12288000>; + }; + codec { + //sound-dai = <&tas5707_36 &tas5707_3a>; + sound-dai = <&dummy_codec &dummy_codec>; + }; + }; + + aml-audio-card,dai-link@3 { + mclk-fs = <64>; + cpu { + sound-dai = <&aml_pdm>; + }; + codec { + sound-dai = <&pdm_codec>; + }; + }; + + aml-audio-card,dai-link@4 { + mclk-fs = <128>; + cpu { + sound-dai = <&aml_spdif>; + system-clock-frequency = <6144000>; + }; + codec { + sound-dai = <&dummy_codec>; + }; + }; + }; + +}; /* end of / */ + +/* Audio Related start */ +/* for spk board */ +&i2c1 { + status = "okay"; + //pinctrl-names="default"; + //pinctrl-0=<&b_i2c_master>; + tlv320adc3101_32: tlv320adc3101_32@32 { + compatible = "ti,tlv320adc3101"; + #sound-dai-cells = <0>; + reg = <0x19>; + status = "disabled"; + }; + + tas5707_36: tas5707_36@36 { + compatible = "ti,tas5707"; + #sound-dai-cells = <0>; + reg = <0x1b>; + status = "disabled"; + reset_pin = <&gpio_ao GPIOAO_4 0>; + }; + + tas5707_3a: tas5707_3a@3a { + compatible = "ti,tas5707"; + #sound-dai-cells = <0>; + reg = <0x1d>; + status = "disabled"; + }; +}; + +/* for mic board */ +&i2c_AO { + status = "okay"; + pinctrl-names="default"; + pinctrl-0=<&ao_i2c_master_pin2>; + + tlv320adc3101_30: tlv320adc3101_30@30 { + compatible = "ti,tlv320adc3101"; + #sound-dai-cells = <0>; + reg = <0x18>; + status = "disabled"; + }; + tlv320adc3101_34: tlv320adc3101_34@30 { + compatible = "ti,tlv320adc3101"; + #sound-dai-cells = <0>; + reg = <0x1a>; + status = "disabled"; + }; + tlv320adc3101_36: tlv320adc3101_36@30 { + compatible = "ti,tlv320adc3101"; + #sound-dai-cells = <0>; + reg = <0x1b>; + status = "disabled"; + }; +}; + +&audiobus { + aml_tdma: tdma { + compatible = "amlogic, axg-snd-tdma"; + #sound-dai-cells = <0>; + dai-tdm-lane-slot-mask-in = <1 0>; + dai-tdm-lane-slot-mask-out = <0 1>; + dai-tdm-clk-sel = <0>; + clocks = <&clkaudio CLKID_AUDIO_MCLK_A + &clkc CLKID_MPLL0>; + clock-names = "mclk", "clk_srcpll"; + pinctrl-names = "tdm_pins"; + pinctrl-0 = <&tdmout_a &tdmin_a &tdmout_a_data>; + }; + + aml_tdmb: tdmb { + compatible = "amlogic, axg-snd-tdmb"; + #sound-dai-cells = <0>; + dai-tdm-lane-slot-mask-in = <1 1 1 1>; + dai-tdm-clk-sel = <1>; + clocks = <&clkaudio CLKID_AUDIO_MCLK_B + &clkc CLKID_MPLL1>; + clock-names = "mclk", "clk_srcpll"; + pinctrl-names = "tdm_pins"; + pinctrl-0 = <&tdmb_mclk &tdmout_b &tdmin_b>; + }; + + aml_tdmc: tdmc { + compatible = "amlogic, axg-snd-tdmc"; + #sound-dai-cells = <0>; + dai-tdm-lane-slot-mask-in = <0 1 0 0>; + dai-tdm-lane-slot-mask-out = <1 0 1 1>; + dai-tdm-clk-sel = <2>; + clocks = <&clkaudio CLKID_AUDIO_MCLK_C + &clkc CLKID_MPLL2>; + clock-names = "mclk", "clk_srcpll"; + pinctrl-names = "tdm_pins"; + pinctrl-0 = <&tdmc_mclk &tdmout_c &tdmin_c>; + }; + + aml_spdif: spdif { + compatible = "amlogic, axg-snd-spdif"; + #sound-dai-cells = <0>; + clocks = <&clkc CLKID_MPLL0 + &clkc CLKID_FCLK_DIV4 + &clkaudio CLKID_AUDIO_SPDIFIN + &clkaudio CLKID_AUDIO_SPDIFOUT + &clkaudio CLKID_AUDIO_SPDIFIN_CTRL + &clkaudio CLKID_AUDIO_SPDIFOUT_CTRL>; + clock-names = "sysclk", "fixed_clk", "gate_spdifin", + "gate_spdifout", "clk_spdifin", "clk_spdifout"; + interrupts = + ; + + interrupt-names = "irq_spdifin"; + pinctrl-names = "spdif_pins"; + pinctrl-0 = <&spdifout &spdifin>; + status = "okay"; + }; + aml_pdm: pdm { + compatible = "amlogic, axg-snd-pdm"; + #sound-dai-cells = <0>; + clocks = <&clkaudio CLKID_AUDIO_PDM + &clkc CLKID_FCLK_DIV3 + &clkc CLKID_MPLL3 + &clkaudio CLKID_AUDIO_PDMIN0 + &clkaudio CLKID_AUDIO_PDMIN1>; + clock-names = "gate", + "sysclk_srcpll", + "dclk_srcpll", + "pdm_dclk", + "pdm_sysclk"; + pinctrl-names = "pdm_pins"; + pinctrl-0 = <&pdmin>; + filter_mode = <1>; /* mode 0~4, defalut:1 */ + status = "okay"; + }; +}; /* end of audiobus */ + +&pinctrl_periphs { + tdmout_a: tdmout_a { + mux { + groups = "tdma_sclk", + "tdma_fs"; + function = "tdma_out"; + }; + }; + + tdmout_a_data: tdmout_a_data { + mux { + groups = "tdma_dout1_x15"; + function = "tdma_out"; + }; + }; + + tdmin_a: tdmin_a { + mux { + groups = "tdma_din0"; + function = "tdma_in"; + }; + }; + + tdmb_mclk: tdmb_mclk { + mux { + groups = "mclk_b"; + function = "mclk_b"; + }; + }; + + tdmout_b: tdmout_b { + mux { + groups = "tdmb_sclk", + "tdmb_fs"; + function = "tdmb_out"; + }; + }; + // tdmin and tdmout are the same pins. can't use at same time + tdmin_b:tdmin_b { + mux { + groups = "tdmb_din0", + "tdmb_din1", + "tdmb_din2_a12", + "tdmb_din3_a13"; + function = "tdmb_in"; + }; + }; + + tdmc_mclk: tdmc_mclk { + mux { + groups = "mclk_a"; + function = "mclk_a"; + }; + }; + + tdmout_c:tdmout_c { + mux { + groups = "tdmc_sclk", + "tdmc_fs", + "tdmc_dout0", + "tdmc_dout2_a6", + "tdmc_dout3_a7"; + function = "tdmc_out"; + }; + }; + + tdmin_c:tdmin_c { + mux { + groups = "tdmc_din1"; + function = "tdmc_in"; + }; + }; + + spdifout: spidfout { + mux { + groups = "spdif_out_a20"; + function = "spdif_out"; + }; + }; + + spdifin: spidfin { + mux { + groups = "spdif_in_a19"; + function = "spdif_in"; + }; + }; + + pdmin: pdmin { + mux { + groups = "pdm_dclk_a14", + "pdm_din0", + "pdm_din1", + "pdm_din2", + "pdm_din3"; + function = "pdm"; + }; + }; +}; /* end of pinctrl_periphs */ +/* Audio Related End */ + +&aobus{ + uart_AO: serial@3000 { + compatible = "amlogic, meson-uart"; + reg = <0x3000 0x18>; + interrupts = <0 193 1>; + status = "okay"; + clocks = <&xtal>; + clock-names = "clk_uart"; + xtal_tick_en = <1>; + fifosize = < 64 >; + pinctrl-names = "default"; + pinctrl-0 = <&ao_uart_pins>; + support-sysrq = <0>; /* 0 not support , 1 support */ + }; +}; + +&audio_data{ + status = "okay"; +}; diff --git a/arch/arm/boot/dts/amlogic/axg_s400_v03.dts b/arch/arm/boot/dts/amlogic/axg_s400_v03.dts new file mode 100644 index 000000000000..002962aa404f --- /dev/null +++ b/arch/arm/boot/dts/amlogic/axg_s400_v03.dts @@ -0,0 +1,1414 @@ +/* + * arch/arm/boot/dts/amlogic/axg_s400_v03.dts + * + * Copyright (C) 2017 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +/dts-v1/; + +#include "mesonaxg.dtsi" +#include "mesonaxg_s400-panel.dtsi" +/ { + model = "Amlogic"; + amlogic-dt-id = "axg_s400_v03"; + compatible = "amlogic, axg"; + interrupt-parent = <&gic>; + #address-cells = <1>; + #size-cells = <1>; + + aliases { + serial0 = &uart_AO; + serial1 = &uart_A; + }; + + memory@00000000 { + device_type = "memory"; + linux,usable-memory = <0x000000 0x40000000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + /* global autoconfigured region for contiguous allocations */ + ramoops@0x07400000 { + compatible = "ramoops"; + reg = <0x07400000 0x00100000>; + record-size = <0x8000>; + console-size = <0x8000>; + ftrace-size = <0x0>; + pmsg-size = <0x8000>; + }; + + secmon_reserved:linux,secmon { + compatible = "shared-dma-pool"; + reusable; + size = <0x400000>; + alignment = <0x400000>; + alloc-ranges = <0x05000000 0x400000>; + }; + + secos_reserved:linux,secos { + status = "disable"; + compatible = "amlogic, aml_secos_memory"; + reg = <0x05300000 0x2000000>; + no-map; + }; + fb_reserved:linux,meson-fb { + //compatible = "amlogic, fb-memory"; + //reg = <0x3e000000 0x1f00000>; + compatible = "shared-dma-pool"; + reusable; + size = <0x2000000>; + alignment = <0x400000>; + alloc-ranges = <0x3e000000 0x2000000>; + }; + }; + mtd_nand { + compatible = "amlogic, aml_mtd_nand"; + dev_name = "mtdnand"; + status = "okay"; + reg = <0xFFE07800 0x200>; + interrupts = < 0 34 1 >; + pinctrl-names = "nand_rb_mod","nand_norb_mod", "nand_cs_only"; + pinctrl-0 = <&all_nand_pins>; + pinctrl-1 = <&all_nand_pins>; + pinctrl-2 = <&nand_cs_pins>; + device_id = <0>; + + /*fip/tpl configurations, must be same + * with uboot if bl_mode was set as 1 + * bl_mode: 0 compact mode; 1 descrete mode + * if bl_mode was set as 1, fip configeration will work + */ + bl_mode = <1>; + /*copy count of fip*/ + fip_copies = <4>; + /*size of each fip copy */ + fip_size = <0x200000>; + nand_clk_ctrl = <0xFFE07000>; + plat-names = "bootloader","nandnormal"; + plat-num = <2>; + plat-part-0 = <&bootloader>; + plat-part-1 = <&nandnormal>; + bootloader: bootloader{ + enable_pad ="ce0"; + busy_pad = "rb0"; + timming_mode = "mode5"; + bch_mode = "bch8_1k"; + t_rea = <20>; + t_rhoh = <15>; + chip_num = <1>; + part_num = <0>; + rb_detect = <1>; + }; + nandnormal: nandnormal{ + enable_pad ="ce0"; + busy_pad = "rb0"; + timming_mode = "mode5"; + bch_mode = "bch8_1k"; + plane_mode = "twoplane"; + t_rea = <20>; + t_rhoh = <15>; + chip_num = <2>; + part_num = <3>; + partition = <&nand_partitions>; + rb_detect = <1>; + }; + nand_partitions:nand_partition{ + /* + * if bl_mode is 1, tpl size was generate by + * fip_copies * fip_size which + * will not skip bad when calculating + * the partition size; + * + * if bl_mode is 0, + * tpl partition must be comment out. + */ + tpl{ + offset=<0x0 0x0>; + size=<0x0 0x0>; + }; + misc{ + offset=<0x0 0x0>; + size=<0x0 0x200000>; + }; + logo{ + offset=<0x0 0x0>; + size=<0x0 0x200000>; + }; + recovery{ + offset=<0x0 0x0>; + size=<0x0 0x1000000>; + }; + boot{ + offset=<0x0 0x0>; + size=<0x0 0xF00000>; + }; + system{ + offset=<0x0 0x0>; + size=<0x0 0x11800000>; + }; + data{ + offset=<0xffffffff 0xffffffff>; + size=<0x0 0x0>; + }; + }; + }; + + + ethmac: ethernet@0xff3f0000 { + compatible = "amlogic, gxbb-eth-dwmac"; + reg = <0xff3f0000 0x10000 + 0xff634540 0x8>; + interrupts = <0 8 1>; + pinctrl-names = "external_eth_pins"; + pinctrl-0 = <&external_eth_pins>; + mc_val_internal_phy = <0x1800>; + mc_val_external_phy = <0x1621>; + interrupt-names = "macirq"; + clocks = <&clkc CLKID_ETH_CORE>; + clock-names = "ethclk81"; + internal_phy=<0>; + }; + + aml_sensor0: aml-sensor@0 { + compatible = "amlogic, aml-thermal"; + device_name = "thermal"; + #thermal-sensor-cells = <1>; + cooling_devices { + cpufreq_cool_cluster0 { + min_state = <1000000>; + dyn_coeff = <140>; + cluster_id = <0>; + node_name = "cpufreq_cool0"; + device_type = "cpufreq"; + }; + cpucore_cool_cluster0 { + min_state = <1>; + dyn_coeff = <0>; + cluster_id = <0>; + node_name = "cpucore_cool0"; + device_type = "cpucore"; + }; + }; + cpufreq_cool0:cpufreq_cool0 { + #cooling-cells = <2>; /* min followed by max */ + }; + cpucore_cool0:cpucore_cool0 { + #cooling-cells = <2>; /* min followed by max */ + }; + }; + thermal-zones { + soc_thermal { + polling-delay = <1000>; + polling-delay-passive = <100>; + sustainable-power = <1050>; + + thermal-sensors = <&aml_sensor0 3>; + + trips { + switch_on: trip-point@0 { + temperature = <70000>; + hysteresis = <1000>; + type = "passive"; + }; + control: trip-point@1 { + temperature = <80000>; + hysteresis = <1000>; + type = "passive"; + }; + hot: trip-point@2 { + temperature = <85000>; + hysteresis = <5000>; + type = "hot"; + }; + critical: trip-point@3 { + temperature = <260000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + + cooling-maps { + cpufreq_cooling_map { + trip = <&control>; + cooling-device = <&cpufreq_cool0 0 4>; + contribution = <1024>; + }; + cpucore_cooling_map { + trip = <&control>; + cooling-device = <&cpucore_cool0 0 3>; + contribution = <1024>; + }; + }; + }; + }; + + dwc3: dwc3@ff500000 { + compatible = "synopsys, dwc3"; + status = "okay"; + reg = <0xff500000 0x100000>; + interrupts = <0 30 4>; + usb-phy = <&usb2_phy>, <&usb3_phy>; + cpu-type = "gxl"; + clock-src = "usb3.0"; + clocks = <&clkc CLKID_USB_GENERAL>; + clock-names = "dwc_general"; + }; + + usb2_phy: usb2phy@ffe09000 { + compatible = "amlogic, amlogic-new-usb2"; + status = "okay"; + portnum = <4>; + reg = <0xffe09000 0x80 + 0xffd01008 0x4>; + }; + + usb3_phy: usb3phy@ffe09080 { + compatible = "amlogic, amlogic-new-usb3"; + status = "okay"; + portnum = <0>; + reg = <0xffe09080 0x20>; + interrupts = <0 16 4>; + otg = <1>; + gpio-vbus-power = "GPIOAO_5"; + gpios = <&gpio_ao GPIOAO_5 GPIO_ACTIVE_HIGH>; + }; + + dwc2_a { + compatible = "amlogic, dwc2"; + device_name = "dwc2_a"; + reg = <0xff400000 0x40000>; + status = "okay"; + interrupts = <0 31 4>; + pl-periph-id = <0>; /** lm name */ + clock-src = "usb0"; /** clock src */ + port-id = <0>; /** ref to mach/usb.h */ + port-type = <2>; /** 0: otg, 1: host, 2: slave */ + port-speed = <0>; /** 0: default, high, 1: full */ + port-config = <0>; /** 0: default */ + /*0:default,1:single,2:incr,3:incr4,4:incr8,5:incr16,6:disable*/ + port-dma = <0>; + port-id-mode = <0>; /** 0: hardware, 1: sw_host, 2: sw_slave*/ + usb-fifo = <728>; + cpu-type = "gxl"; + /** 0: normal, 1: otg+dwc3 host only, 2: otg+dwc3 device only*/ + controller-type = <3>; + phy-reg = <0xffe09000>; + phy-reg-size = <0xa0>; + clocks = <&clkc CLKID_USB_GENERAL + &clkc CLKID_USB1_TO_DDR + &clkc CLKID_USB1>; + clock-names = "usb_general", + "usb1", + "usb1_to_ddr"; + }; + + pcie_A: pcieA@f9800000 { + compatible = "amlogic, amlogic-pcie", "snps,dw-pcie"; + reg = <0xf9800000 0x400000 + 0xff646000 0x2000 + 0xf9f00000 0x100000 + PCIE_PHY_REG PCIE_PHY_SIZE + PCIE_RESET_REG PCIE_RESET_SIZE>; + reg-names = "elbi", "cfg", "config", "phy", "reset"; + reset-gpio = <&gpio GPIOX_19 GPIO_ACTIVE_HIGH>; + interrupts = <0 177 0>; + #interrupt-cells = <1>; + bus-range = <0x0 0xff>; + #address-cells = <3>; + #size-cells = <2>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 179 IRQ_TYPE_EDGE_RISING>; + device_type = "pci"; + ranges = <0x82000000 0 0 0xf9c00000 0 0x00300000>; + /* non-prefetchable memory */ + num-lanes = <1>; + pcie-num = <1>; + + clocks = <&clkc CLKID_USB_GENERAL + &clkc CLKID_PCIE_PLL + &clkc CLKID_MIPI_ENABLE_GATE + &clkc CLKID_MIPI_BANDGAP_GATE + &clkc CLKID_PCIE_A + &clkc CLKID_PCIE_CML_EN0>; + clock-names = "pcie_general", + "pcie_refpll", + "pcie_mipi_enable_gate", + "pcie_mipi_bandgap_gate", + "pcie", + "port"; + /*reset-gpio-type 0:Shared pad(no reset)1:OD pad2:Normal pad*/ + gpio-type = <2>; + status = "okay"; + }; + + pcie_B: pcieB@fa000000 { + compatible = "amlogic, amlogic-pcie", "snps,dw-pcie"; + reg = <0xfa000000 0x400000 + 0xff648000 0x2000 + 0xfa400000 0x100000 + PCIE_PHY_REG PCIE_PHY_SIZE + PCIE_RESET_REG PCIE_RESET_SIZE>; + reg-names = "elbi", "cfg", "config", "phy", "reset"; + reset-gpio = <&gpio GPIOZ_10 GPIO_ACTIVE_HIGH>; + interrupts = <0 167 0>; + #interrupt-cells = <1>; + bus-range = <0x0 0xff>; + #address-cells = <3>; + #size-cells = <2>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 169 IRQ_TYPE_EDGE_RISING>; + device_type = "pci"; + ranges = <0x81000000 0 0 0xfa500000 0x0 0x10000 + /* downstream I/O */ + 0x82000000 0 0xfa510000 0xfa510000 0 0x002f0000>; + /* non-prefetchable memory */ + num-lanes = <1>; + pcie-num = <2>; + + clocks = <&clkc CLKID_USB_GENERAL + &clkc CLKID_PCIE_PLL + &clkc CLKID_MIPI_ENABLE_GATE + &clkc CLKID_MIPI_BANDGAP_GATE + &clkc CLKID_PCIE_B + &clkc CLKID_PCIE_CML_EN1>; + clock-names = "pcie_general", + "pcie_refpll", + "pcie_mipi_enable_gate", + "pcie_mipi_bandgap_gate", + "pcie", + "port"; + /*reset-gpio-type 0:Shared pad(no reset)1:OD pad2:Normal pad*/ + gpio-type = <1>; + status = "okay"; + }; + + + uart_A: serial@ffd24000 { + compatible = "amlogic, meson-uart"; + reg = <0xffd24000 0x18>; + interrupts = <0 26 1>; + status = "okay"; + clocks = <&xtal + &clkc CLKID_UART0>; + clock-names = "clk_uart", + "clk_gate"; + fifosize = < 128 >; + pinctrl-names = "default"; + pinctrl-0 = <&a_uart_pins>; + }; + + uart_B: serial@ffd23000 { + compatible = "amlogic, meson-uart"; + reg = <0xffd23000 0x18>; + interrupts = <0 75 1>; + status = "disable"; + clocks = <&xtal + &clkc CLKID_UART1>; + clock-names = "clk_uart", + "clk_gate"; + fifosize = < 64 >; + pinctrl-names = "default"; + pinctrl-0 = <&b_uart_pins>; + }; + + vpu { + compatible = "amlogic, vpu-axg"; + dev_name = "vpu"; + status = "okay"; + clocks = <&clkc CLKID_VAPB_MUX>, + <&clkc CLKID_VPU_INTR>, + <&clkc CLKID_VPU_P0_COMP>, + <&clkc CLKID_VPU_P1_COMP>, + <&clkc CLKID_VPU_MUX>; + clock-names = "vapb_clk", + "vpu_intr_gate", + "vpu_clk0", + "vpu_clk1", + "vpu_clk"; + clk_level = <3>; + /* 0: 100.0M 1: 166.7M 2: 200.0M 3: 250.0M */ + }; + + vout { + compatible = "amlogic, vout"; + dev_name = "vout"; + status = "okay"; + }; + + /* Sound iomap */ + aml_snd_iomap { + compatible = "amlogic, snd-iomap"; + status = "okay"; + #address-cells=<1>; + #size-cells=<1>; + ranges; + pdm_bus { + reg = <0xFF632000 0x2000>; + }; + audiobus_base { + reg = <0xFF642000 0x2000>; + }; + }; + pdm_codec:dummy{ + #sound-dai-cells = <0>; + compatible = "amlogic, pdm_dummy_codec"; + status = "okay"; + }; + dummy_codec:dummy{ + #sound-dai-cells = <0>; + compatible = "amlogic, aml_dummy_codec"; + status = "okay"; + }; + + auge_sound { + compatible = "amlogic, axg-sound-card"; + aml-audio-card,name = "AML-AUGESOUND"; + + aml-audio-card,loopback = <&aml_loopback>; + + aml-audio-card,hp-det-gpio = <&gpio GPIOZ_7 GPIO_ACTIVE_LOW>; + + aml-audio-card,dai-link@0 { + format = "dsp_a"; + mclk-fs = <512>; + //continuous-clock; + //bitclock-inversion; + //frame-inversion; + //bitclock-master = <&tdmacodec>; + //frame-master = <&tdmacodec>; + tdmacpu: cpu { + sound-dai = <&aml_tdma>; + dai-tdm-slot-tx-mask = + <1>; + dai-tdm-slot-rx-mask = + <1>; + dai-tdm-slot-num = <1>; + dai-tdm-slot-width = <32>; + system-clock-frequency = <512000>; + }; + tdmacodec: codec { + sound-dai = <&dummy_codec &dummy_codec>; + }; + }; + + aml-audio-card,dai-link@1 { + format = "i2s"; + mclk-fs = <256>; + //continuous-clock; + //bitclock-inversion; + //frame-inversion; + bitclock-master = <&aml_tdmb>; + frame-master = <&aml_tdmb>; + cpu { + sound-dai = <&aml_tdmb>; + dai-tdm-slot-tx-mask = <1 1>; + dai-tdm-slot-rx-mask = <1 1>; + dai-tdm-slot-num = <2>; + dai-tdm-slot-width = <32>; + system-clock-frequency = <12288000>; + }; + codec { + /* + * prefix-names = "3101_A", "3101_B", + * "3101_C", "3101_D"; + * sound-dai = <&tlv320adc3101_32 + * &tlv320adc3101_30 + * &tlv320adc3101_34 + * &tlv320adc3101_36>; + */ + sound-dai = <&tlv320adc3101_32 &dummy_codec>; + }; + }; + + aml-audio-card,dai-link@2 { + format = "i2s"; + mclk-fs = <256>; + //continuous-clock; + //bitclock-inversion; + //frame-inversion; + //bitclock-master = <&aml_tdmc>; + //frame-master = <&aml_tdmc>; + cpu { + sound-dai = <&aml_tdmc>; + dai-tdm-slot-tx-mask = <1 1>; + dai-tdm-slot-rx-mask = <1 1>; + dai-tdm-slot-num = <2>; + dai-tdm-slot-width = <32>; + system-clock-frequency = <12288000>; + }; + codec { + prefix-names = "5707_A", "5707_B"; + sound-dai = <&tas5707_36 &tas5707_3a + &dummy_codec>; + }; + }; + + aml-audio-card,dai-link@3 { + mclk-fs = <256>; + cpu { + sound-dai = <&aml_pdm>; + }; + codec { + /* + *enable external loopback + *and tlv320adc3101 as loopback + */ + /*sound-dai = <&pdm_codec &tlv320adc3101_32>;*/ + /* + * enable internal loopback + * or disable loopback + */ + sound-dai = <&pdm_codec>; + }; + }; + + aml-audio-card,dai-link@4 { + mclk-fs = <128>; + cpu { + sound-dai = <&aml_spdif>; + system-clock-frequency = <6144000>; + }; + codec { + sound-dai = <&dummy_codec>; + }; + }; + }; + + bt-dev{ + compatible = "amlogic, bt-dev"; + dev_name = "bt-dev"; + status = "okay"; + gpio_reset = <&gpio GPIOX_21 GPIO_ACTIVE_HIGH>; + }; + + wifi{ + compatible = "amlogic, aml_wifi"; + dev_name = "aml_wifi"; + status = "okay"; + interrupt_pin = <&gpio GPIOX_6 GPIO_ACTIVE_HIGH>; + interrupts = < 0 67 4>; + irq_trigger_type = "GPIO_IRQ_LOW"; + power_on_pin2 = <&gpio GPIOX_16 GPIO_ACTIVE_HIGH>; + power_on_pin = <&gpio GPIOX_7 GPIO_ACTIVE_HIGH>; + dhd_static_buf; //if use bcm wifi, config dhd_static_buf + pinctrl-names = "default"; + pinctrl-0 = <&wifi_32k_pins>; + pwm_config = <&wifi_pwm_conf>; + }; + + wifi_pwm_conf:wifi_pwm_conf{ + pwm_channel1_conf { + pwms = <&pwm_ab MESON_PWM_0 30040 0>; + duty-cycle = <15020>; + times = <10>; + }; + pwm_channel2_conf { + pwms = <&pwm_ab MESON_PWM_2 30030 0>; + duty-cycle = <15015>; + times = <12>; + }; + }; + + sd_emmc_c: emmc@ffe07000 { + status = "disabled"; + compatible = "amlogic, meson-mmc-axg"; + reg = <0xffe07000 0x2000>; + interrupts = <0 218 1>; + pinctrl-names = "emmc_clk_cmd_pins", "emmc_all_pins"; + pinctrl-0 = <&emmc_clk_cmd_pins>; + pinctrl-1 = <&emmc_conf_pull_up &emmc_conf_pull_done>; + clocks = <&clkc CLKID_SD_EMMC_C>, + <&clkc CLKID_SD_EMMC_C_P0_COMP>, + <&clkc CLKID_FCLK_DIV2>, + <&clkc CLKID_FCLK_DIV5>, + <&xtal>; + clock-names = "core", "clkin0", "clkin1", "clkin2", "xtal"; + + bus-width = <8>; + cap-sd-highspeed; + cap-mmc-highspeed; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + + max-frequency = <200000000>; + non-removable; + disable-wp; + emmc { + pinname = "emmc"; + ocr_avail = <0x200080>; /**VDD voltage 3.3 ~ 3.4 */ + caps = "MMC_CAP_8_BIT_DATA", + "MMC_CAP_MMC_HIGHSPEED", + "MMC_CAP_SD_HIGHSPEED", + "MMC_CAP_NONREMOVABLE", + "MMC_CAP_1_8V_DDR", + "MMC_CAP_HW_RESET", + "MMC_CAP_ERASE", + "MMC_CAP_CMD23"; + caps2 = "MMC_CAP2_HS200", "MMC_CAP2_HS400"; + f_min = <400000>; + f_max = <200000000>; + max_req_size = <0x20000>; /**128KB*/ + gpio_dat3 = <&gpio BOOT_3 GPIO_ACTIVE_HIGH>; + tx_delay = <4>; + hw_reset = <&gpio BOOT_9 GPIO_ACTIVE_HIGH>; + card_type = <1>; + /* 1:mmc card(include eMMC), + * 2:sd card(include tSD) + */ + }; + }; + + sd_emmc_b:sdio@ffe05000 { + status = "okay"; + compatible = "amlogic, meson-mmc-axg"; + reg = <0xffe05000 0x2000>; + interrupts = <0 217 4>; + pinctrl-names = "sdio_clk_cmd_pins", "sdio_all_pins"; + pinctrl-0 = <&sdio_clk_cmd_pins>; + pinctrl-1 = <&sdio_all_pins>; + clocks = <&clkc CLKID_SD_EMMC_B>, + <&clkc CLKID_SD_EMMC_B_P0_COMP>, + <&clkc CLKID_FCLK_DIV2>, + <&clkc CLKID_FCLK_DIV5>, + <&xtal>; + clock-names = "core", "clkin0", "clkin1", "clkin2", "xtal"; + + bus-width = <4>; + cap-sd-highspeed; + cap-mmc-highspeed; + max-frequency = <100000000>; + non-removable; + disable-wp; + sdio { + pinname = "sdio"; + ocr_avail = <0x200080>; /**VDD voltage 3.3 ~ 3.4 */ + caps = "MMC_CAP_4_BIT_DATA", + "MMC_CAP_MMC_HIGHSPEED", + "MMC_CAP_SD_HIGHSPEED", + "MMC_CAP_NONREMOVABLE", + "MMC_CAP_UHS_SDR12", + "MMC_CAP_UHS_SDR25", + "MMC_CAP_UHS_SDR50", + "MMC_CAP_UHS_SDR104", + "MMC_PM_KEEP_POWER", + "MMC_CAP_SDIO_IRQ"; + f_min = <400000>; + f_max = <200000000>; + max_req_size = <0x20000>; /**128KB*/ + card_type = <3>; + /* 3:sdio device(ie:sdio-wifi), + * 4:SD combo (IO+mem) card + */ + }; + }; + + partitions: partitions{ + parts = <11>; + part-0 = <&logo>; + part-1 = <&recovery>; + part-2 = <&rsv>; + part-3 = <&tee>; + part-4 = <&crypt>; + part-5 = <&misc>; + part-6 = <&instaboot>; + part-7 = <&boot>; + part-8 = <&system>; + part-9 = <&cache>; + part-10 = <&data>; + + logo:logo{ + pname = "logo"; + size = <0x0 0x2000000>; + mask = <1>; + }; + recovery:recovery{ + pname = "recovery"; + size = <0x0 0x2000000>; + mask = <1>; + }; + rsv:rsv{ + pname = "rsv"; + size = <0x0 0x800000>; + mask = <1>; + }; + tee:tee{ + pname = "tee"; + size = <0x0 0x800000>; + mask = <1>; + }; + crypt:crypt{ + pname = "crypt"; + size = <0x0 0x2000000>; + mask = <1>; + }; + misc:misc{ + pname = "misc"; + size = <0x0 0x2000000>; + mask = <1>; + }; + instaboot:instaboot{ + pname = "instaboot"; + size = <0x0 0x400000>; + mask = <1>; + }; + boot:boot + { + pname = "boot"; + size = <0x0 0x2000000>; + mask = <1>; + }; + system:system + { + pname = "system"; + size = <0x0 0x80000000>; + mask = <1>; + }; + cache:cache + { + pname = "cache"; + size = <0x0 0x20000000>; + mask = <2>; + }; + data:data + { + pname = "data"; + size = <0xffffffff 0xffffffff>; + mask = <4>; + }; + }; + + meson-fb { + compatible = "amlogic, meson-axg"; + memory-region = <&fb_reserved>; + dev_name = "meson-fb"; + status = "okay"; + interrupts = <0 3 1 + 0 89 1>; + interrupt-names = "viu-vsync", "rdma"; + mem_size = <0x00300000 0x1800000 0x00000000>; + /* uboot logo,fb0/fb1 memory size */ + display_mode_default = "1080p60hz"; + scale_mode = <0>; + /** 0:VPU free scale 1:OSD free scale 2:OSD super scale */ + display_size_default = <768 1024 768 2048 32>; + /*768*1024*4*2 = 0x600000*/ + mem_alloc = <1>; + logo_addr = "0x3e000000"; + pxp_mode = <0>; /** 0:normal mode 1:pxp mode */ + }; + + ge2d { + compatible = "amlogic, ge2d-axg"; + dev_name = "ge2d"; + status = "okay"; + interrupts = <0 150 1>; + interrupt-names = "ge2d"; + clocks = <&clkc CLKID_VAPB_MUX>, + <&clkc CLKID_G2D>, + <&clkc CLKID_GE2D_GATE>; + clock-names = "clk_vapb_0", + "clk_ge2d", + "clk_ge2d_gate"; + reg = <0xff940000 0x10000>; + }; + + adc_keypad { + compatible = "amlogic, adc_keypad"; + status = "okay"; + key_name = "power", "vol-", "vol+", "wifi", "<<", ">>"; + key_num = <6>; + io-channels = <&saradc SARADC_CH0>; + io-channel-names = "key-chan-0"; + key_chan = ; + key_code = <116 114 115 139 105 106>; + key_val = <0 143 266 389 512 635>; //val=voltage/1800mV*1023 + key_tolerance = <40 40 40 40 40 40>; + }; + + unifykey{ + compatible = "amlogic, unifykey"; + status = "ok"; + + unifykey-num = <6>; + unifykey-index-0 = <&keysn_0>; + unifykey-index-1 = <&keysn_1>; + unifykey-index-2 = <&keysn_2>; + unifykey-index-3 = <&keysn_3>; + unifykey-index-4 = <&keysn_4>; + unifykey-index-5 = <&keysn_5>; + + keysn_0: key_0{ + key-name = "usid"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_1:key_1{ + key-name = "mac"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_2:key_2{ + key-name = "secure_boot_set"; + key-device = "efuse"; + key-permit = "write"; + }; + keysn_3:key_3{ + key-name = "mac_bt"; + key-device = "normal"; + key-permit = "read","write","del"; + key-type = "mac"; + }; + keysn_4:key_4{ + key-name = "mac_wifi"; + key-device = "normal"; + key-permit = "read","write","del"; + key-type = "mac"; + }; + keysn_5:key_5{ + key-name = "deviceid"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + };//End unifykey + +}; /* end of / */ +&efuse { + status = "ok"; +}; + +&pwm_ab { + status = "okay"; +}; +/* Audio Related start */ +/* for spk board */ +&i2c1 { + status = "okay"; + pinctrl-names="default"; + pinctrl-0=<&b_i2c_master>; + + tlv320adc3101_32: tlv320adc3101_32@32 { + compatible = "ti,tlv320adc3101"; + #sound-dai-cells = <0>; + reg = <0x19>; + differential_pair = <1>; + status = "okay"; + }; + + tas5707_36: tas5707_36@36 { + compatible = "ti,tas5707"; + #sound-dai-cells = <0>; + reg = <0x1b>; + status = "okay"; + reset_pin = <&gpio_ao GPIOAO_4 0>; + }; + + tas5707_3a: tas5707_3a@3a { + compatible = "ti,tas5707"; + #sound-dai-cells = <0>; + reg = <0x1d>; + status = "okay"; + }; +}; + +/* for mic board */ +&i2c_AO { + status = "okay"; + pinctrl-names="default"; + pinctrl-0=<&ao_i2c_master_pin2>; + + aml_pca9557: aml_pca9557@0x1f { + compatible = "aml, ledring"; + reg = <0x1f>; + mode = <0>; /*0: 6-led 1: 4key+2led */ + key_num = <4>; + led_dev_name = "aml_ledring"; + key_dev_name = "aml_pca_key"; + key_name = "mute", "pause", "vol+", "vol-"; + key_value = <200 201 202 203>; + status = "okay"; + }; + + tlv320adc3101_30: tlv320adc3101_30@30 { + compatible = "ti,tlv320adc3101"; + #sound-dai-cells = <0>; + reg = <0x18>; + status = "disable"; + }; + tlv320adc3101_34: tlv320adc3101_34@30 { + compatible = "ti,tlv320adc3101"; + #sound-dai-cells = <0>; + reg = <0x1a>; + status = "disable"; + }; + tlv320adc3101_36: tlv320adc3101_36@30 { + compatible = "ti,tlv320adc3101"; + #sound-dai-cells = <0>; + reg = <0x1b>; + status = "disable"; + }; + + es7243_10: es7243_10@10 { + compatible = "MicArray_0"; + #sound-dai-cells = <0>; + reg = <0x10>; + status = "disable"; + }; + es7243_12: es7243_12@12 { + compatible = "MicArray_1"; + #sound-dai-cells = <0>; + reg = <0x12>; + status = "disable"; + }; + es7243_13: es7243_13@13 { + compatible = "MicArray_2"; + #sound-dai-cells = <0>; + reg = <0x13>; + status = "disable"; + }; + is31fl3236a: is31f3236a@0x78 { + compatible = "issi,is31fl3236"; + reg = <0x3c>; + status = "disable"; + led1_r { + label="LED1_R"; + reg_offset = <24>; + }; + led1_g { + label="LED1_G"; + reg_offset = <23>; + }; + led1_b { + label="LED1_B"; + reg_offset = <22>; + }; + led2_r { + label="LED2_R"; + reg_offset = <21>; + }; + led2_g { + label="LED2_G"; + reg_offset = <20>; + }; + led2_b { + label="LED2_B"; + reg_offset = <19>; + }; + led3_r { + label="LED3_R"; + reg_offset = <18>; + }; + led3_g { + label="LED3_G"; + reg_offset = <17>; + }; + led3_b { + label="LED3_B"; + reg_offset = <16>; + }; + led4_r { + label="LED4_R"; + reg_offset = <15>; + }; + led4_g { + label="LED4_G"; + reg_offset = <14>; + }; + led4_b { + label="LED4_B"; + reg_offset = <13>; + }; + led5_r { + label="LED5_R"; + reg_offset = <36>; + }; + led5_g { + label="LED5_G"; + reg_offset = <35>; + }; + led5_b { + label="LED5_B"; + reg_offset = <34>; + }; + led6_r { + label="LED6_R"; + reg_offset = <33>; + }; + led6_g { + label="LED6_G"; + reg_offset = <32>; + }; + led6_b { + label="LED6_B"; + reg_offset = <31>; + }; + led7_r { + label="LED7_R"; + reg_offset = <30>; + }; + led7_g { + label="LED7_G"; + reg_offset = <29>; + }; + led7_b { + label="LED7_B"; + reg_offset = <28>; + }; + led8_r { + label="LED8_R"; + reg_offset = <27>; + }; + led8_g { + label="LED8_G"; + reg_offset = <26>; + }; + led8_b { + label="LED8_B"; + reg_offset = <25>; + }; + }; +}; + +&audiobus { + aml_tdma: tdma { + compatible = "amlogic, axg-snd-tdma"; + #sound-dai-cells = <0>; + dai-tdm-lane-slot-mask-in = <1 0>; + dai-tdm-lane-slot-mask-out = <0 1>; + dai-tdm-clk-sel = <0>; + clocks = <&clkaudio CLKID_AUDIO_MCLK_A + &clkc CLKID_MPLL0>; + clock-names = "mclk", "clk_srcpll"; + pinctrl-names = "tdm_pins"; + pinctrl-0 = <&tdmout_a &tdmin_a &tdmout_a_data>; + }; + + aml_tdmb: tdmb { + compatible = "amlogic, axg-snd-tdmb"; + #sound-dai-cells = <0>; + /*dai-tdm-lane-slot-mask-in = <1 1 1 1>;*/ + dai-tdm-lane-slot-mask-in = <0 0 0 1>; + dai-tdm-clk-sel = <1>; + clocks = <&clkaudio CLKID_AUDIO_MCLK_B + &clkc CLKID_MPLL1>; + clock-names = "mclk", "clk_srcpll"; + pinctrl-names = "tdm_pins"; + pinctrl-0 = <&tdmb_mclk &tdmout_b &tdmin_b>; + }; + + aml_tdmc: tdmc { + compatible = "amlogic, axg-snd-tdmc"; + #sound-dai-cells = <0>; + dai-tdm-lane-slot-mask-in = <0 1 0 0>; + dai-tdm-lane-slot-mask-out = <0 0 1 1>; + dai-tdm-clk-sel = <2>; + clocks = <&clkaudio CLKID_AUDIO_MCLK_C + &clkc CLKID_MPLL2>; + clock-names = "mclk", "clk_srcpll"; + pinctrl-names = "tdm_pins"; + pinctrl-0 = <&tdmc_mclk &tdmout_c &tdmin_c>; + }; + + aml_spdif: spdif { + compatible = "amlogic, axg-snd-spdif"; + #sound-dai-cells = <0>; + clocks = <&clkc CLKID_MPLL0 + &clkc CLKID_FCLK_DIV4 + &clkaudio CLKID_AUDIO_SPDIFIN + &clkaudio CLKID_AUDIO_SPDIFOUT + &clkaudio CLKID_AUDIO_SPDIFIN_CTRL + &clkaudio CLKID_AUDIO_SPDIFOUT_CTRL>; + clock-names = "sysclk", "fixed_clk", "gate_spdifin", + "gate_spdifout", "clk_spdifin", "clk_spdifout"; + interrupts = + ; + + interrupt-names = "irq_spdifin"; + pinctrl-names = "spdif_pins"; + pinctrl-0 = <&spdifout &spdifin>; + + /* + * whether do asrc for pcm. + * if raw data, asrc is disabled automatically + * 0: "Disable", + * 1: "Enable:32K", + * 2: "Enable:44K", + * 3: "Enable:48K", + * 4: "Enable:88K", + * 5: "Enable:96K", + * 6: "Enable:176K", + * 7: "Enable:192K", + */ + auto_asrc = <0>; + status = "okay"; + }; + aml_pdm: pdm { + compatible = "amlogic, axg-snd-pdm"; + #sound-dai-cells = <0>; + clocks = <&clkaudio CLKID_AUDIO_PDM + &clkc CLKID_FCLK_DIV3 + &clkc CLKID_MPLL3 + &clkaudio CLKID_AUDIO_PDMIN0 + &clkaudio CLKID_AUDIO_PDMIN1>; + clock-names = "gate", + "sysclk_srcpll", + "dclk_srcpll", + "pdm_dclk", + "pdm_sysclk"; + pinctrl-names = "pdm_pins"; + pinctrl-0 = <&pdmin>; + filter_mode = <1>; /* mode 0~4, defalut:1 */ + status = "okay"; + }; + + aml_loopback: loopback { + compatible = "amlogic, snd-loopback"; + + /* + * external loopback clock config + * enable clk while pdm record data + */ + /*clocks = <&clkc CLKID_MPLL1>;*/ + /*clock-names = "datalb_mpll";*/ + + /* + * 0: out rate = in data rate; + * 1: out rate = loopback data rate; + */ + + lb_mode = <0>; + + /* datain src + * 0: tdmin_a; + * 1: tdmin_b; + * 2: tdmin_c; + * 3: spdifin; + * 4: pdmin; + */ + datain_src = <4>; + datain_chnum = <8>; + datain_chmask = <0x7f>; + + /* tdmin_lb src + * 0: tdmoutA + * 1: tdmoutB + * 2: tdmoutC + * 3: PAD_tdminA + * 4: PAD_tdminB + * 5: PAD_tdminC + */ + + /*if tdmin_lb >= 3, use external loopback*/ + datalb_src = <2>; + datalb_chnum = <2>; + /*config which data pin as loopback*/ + /*datalb-lane-mask-in = <0 0 0 1>;*/ + datalb_chmask = <0x1>; + + status = "okay"; + }; + + audioresample: resample { + compatible = "amlogic, axg-resample"; + clocks = <&clkc CLKID_MPLL3 + &clkaudio CLKID_AUDIO_MCLK_F + &clkaudio CLKID_AUDIO_RESAMPLE_CTRL>; + clock-names = "resample_pll", "resample_src", "resample_clk"; + /*same with toddr_src + * TDMIN_A, + * TDMIN_B, + * TDMIN_C, + * SPDIFIN, + * PDMIN, + * NONE, + * TDMIN_LB, + * LOOPBACK, + */ + resample_module = <3>; + status = "okay"; + }; + aml_pwrdet: pwrdet { + compatible = "amlogic, axg-power-detect"; + + interrupts = ; + interrupt-names = "pwrdet_irq"; + + /* pwrdet source sel + * 7: loopback; + * 6: tdmin_lb; + * 5: reserved; + * 4: pdmin; + * 3: spdifin; + * 2: tdmin_c; + * 1: tdmin_b; + * 0: tdmin_a; + */ + pwrdet_src = <4>; + + hi_th = <0x70000>; + lo_th = <0x16000>; + + status = "disabled"; + }; +}; /* end of audiobus */ + +&pinctrl_periphs { + tdmout_a: tdmout_a { + mux { + groups = "tdma_sclk", + "tdma_fs"; + function = "tdma_out"; + }; + }; + + tdmout_a_data: tdmout_a_data { + mux { + groups = "tdma_dout1_x15"; + function = "tdma_out"; + }; + }; + + tdmin_a: tdmin_a { + mux { + groups = "tdma_din0"; + function = "tdma_in"; + }; + }; + + tdmb_mclk: tdmb_mclk { + mux { + groups = "mclk_b"; + function = "mclk_b"; + }; + }; + + tdmout_b: tdmout_b { + mux { + groups = "tdmb_sclk", + "tdmb_fs"; + function = "tdmb_out"; + }; + }; + // tdmin and tdmout are the same pins. can't use at same time + tdmin_b:tdmin_b { + mux { + groups = "tdmb_din0", + "tdmb_din1", + "tdmb_din2_a12", + "tdmb_din3_a13"; + function = "tdmb_in"; + }; + }; + + tdmc_mclk: tdmc_mclk { + mux { + groups = "mclk_a"; + function = "mclk_a"; + }; + }; + + tdmout_c:tdmout_c { + mux { + groups = "tdmc_sclk", + "tdmc_fs", + "tdmc_dout0", + "tdmc_dout2_a6", + "tdmc_dout3_a7"; + function = "tdmc_out"; + }; + }; + + + tdmin_c:tdmin_c { + mux { + groups = "tdmc_din1"; + function = "tdmc_in"; + }; + }; + + spdifout: spidfout { + mux { + groups = "spdif_out_a20"; + function = "spdif_out"; + }; + }; + + spdifin: spidfin { + mux { + groups = "spdif_in_a19"; + function = "spdif_in"; + }; + }; + + pdmin: pdmin { + mux { + groups = "pdm_dclk_a14", + "pdm_din0", + "pdm_din1", + "pdm_din2", + "pdm_din3"; + function = "pdm"; + }; + }; + + bl_pwm_on_pins: bl_pwm_on_pin { + mux { + groups = "pwm_b_z"; + function = "pwm_b"; + }; + }; + bl_pwm_off_pins:bl_pwm_off_pin { + mux { + pins = "GPIOZ_4"; + function = "gpio_periphs"; + output-high; + }; + }; +}; /* end of pinctrl_periphs */ +/* Audio Related End */ + +&aobus{ + uart_AO: serial@3000 { + compatible = "amlogic, meson-uart"; + reg = <0x3000 0x18>; + interrupts = <0 193 1>; + status = "okay"; + clocks = <&xtal>; + clock-names = "clk_uart"; + xtal_tick_en = <1>; + fifosize = < 64 >; + pinctrl-names = "default"; + pinctrl-0 = <&ao_uart_pins>; + support-sysrq = <0>; /* 0 not support , 1 support */ + }; + + uart_AO_B: serial@4000 { + compatible = "amlogic, meson-uart"; + reg = <0x4000 0x18>; + interrupts = <0 197 1>; + status = "disable"; + clocks = <&xtal>; + clock-names = "clk_uart"; + fifosize = < 64 >; + pinctrl-names = "default"; + pinctrl-0 = <&ao_b_uart_pins>; + }; +}; + +&audio_data{ + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/amlogic/axg_s400emmc.dts b/arch/arm/boot/dts/amlogic/axg_s400_v03gva.dts similarity index 85% rename from arch/arm64/boot/dts/amlogic/axg_s400emmc.dts rename to arch/arm/boot/dts/amlogic/axg_s400_v03gva.dts index d414c3d2dbbc..fb3949ba2e63 100644 --- a/arch/arm64/boot/dts/amlogic/axg_s400emmc.dts +++ b/arch/arm/boot/dts/amlogic/axg_s400_v03gva.dts @@ -1,5 +1,5 @@ /* - * arch/arm64/boot/dts/amlogic/axg_s400.dts + * arch/arm/boot/dts/amlogic/axg_s400_v03gva.dts * * Copyright (C) 2017 Amlogic, Inc. All rights reserved. * @@ -19,14 +19,13 @@ #include "mesonaxg.dtsi" #include "mesonaxg_s400-panel.dtsi" -#include "partition_mbox_normal.dtsi" / { model = "Amlogic"; - amlogic-dt-id = "axg_s400_1g"; + amlogic-dt-id = "axg_s400_v03gva"; compatible = "amlogic, axg"; interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; + #address-cells = <1>; + #size-cells = <1>; aliases { serial0 = &uart_AO; @@ -35,43 +34,52 @@ memory@00000000 { device_type = "memory"; - linux,usable-memory = <0x0 0x000000 0x0 0x40000000>; + linux,usable-memory = <0x000000 0x40000000>; }; reserved-memory { - #address-cells = <2>; - #size-cells = <2>; + #address-cells = <1>; + #size-cells = <1>; ranges; /* global autoconfigured region for contiguous allocations */ + ramoops@0x07400000 { + compatible = "ramoops"; + reg = <0x07400000 0x00100000>; + record-size = <0x8000>; + console-size = <0x8000>; + ftrace-size = <0x0>; + pmsg-size = <0x8000>; + }; + secmon_reserved:linux,secmon { compatible = "shared-dma-pool"; reusable; - size = <0x0 0x400000>; - alignment = <0x0 0x400000>; - alloc-ranges = <0x0 0x05000000 0x0 0x400000>; + size = <0x400000>; + alignment = <0x400000>; + alloc-ranges = <0x05000000 0x400000>; }; secos_reserved:linux,secos { status = "disable"; compatible = "amlogic, aml_secos_memory"; - reg = <0x0 0x05300000 0x0 0x2000000>; + reg = <0x05300000 0x2000000>; no-map; }; fb_reserved:linux,meson-fb { //compatible = "amlogic, fb-memory"; - //reg = <0x0 0x3e000000 0x0 0x1f00000>; + //reg = <0x3e000000 0x1f00000>; compatible = "shared-dma-pool"; reusable; - size = <0x0 0x2000000>; - alignment = <0x0 0x400000>; - alloc-ranges = <0x0 0x3e000000 0x0 0x2000000>; + size = <0x2000000>; + alignment = <0x400000>; + alloc-ranges = <0x3e000000 0x2000000>; }; }; mtd_nand { compatible = "amlogic, aml_mtd_nand"; dev_name = "mtdnand"; - status = "disable"; - reg = <0x0 0xFFE07800 0x0 0x200>; + status = "okay"; + reg = <0xFFE07800 0x200>; interrupts = < 0 34 1 >; pinctrl-names = "nand_rb_mod","nand_norb_mod", "nand_cs_only"; pinctrl-0 = <&all_nand_pins>; @@ -132,22 +140,22 @@ offset=<0x0 0x0>; size=<0x0 0x0>; }; - logo{ - offset=<0x0 0x0>; - size=<0x0 0x200000>; - }; recovery{ offset=<0x0 0x0>; size=<0x0 0x1000000>; }; boot{ offset=<0x0 0x0>; - size=<0x0 0xF00000>; + size=<0x0 0x1000000>; }; system{ offset=<0x0 0x0>; size=<0x0 0x11800000>; }; + factory{ + offset=<0x0 0x0>; + size=<0x0 0x1000000>; + }; data{ offset=<0xffffffff 0xffffffff>; size=<0x0 0x0>; @@ -158,8 +166,8 @@ ethmac: ethernet@0xff3f0000 { compatible = "amlogic, gxbb-eth-dwmac"; - reg = <0x0 0xff3f0000 0x0 0x10000 - 0x0 0xff634540 0x0 0x8>; + reg = <0xff3f0000 0x10000 + 0xff634540 0x8>; interrupts = <0 8 1>; pinctrl-names = "external_eth_pins"; pinctrl-0 = <&external_eth_pins>; @@ -247,7 +255,7 @@ dwc3: dwc3@ff500000 { compatible = "synopsys, dwc3"; status = "okay"; - reg = <0x0 0xff500000 0x0 0x100000>; + reg = <0xff500000 0x100000>; interrupts = <0 30 4>; usb-phy = <&usb2_phy>, <&usb3_phy>; cpu-type = "gxl"; @@ -260,15 +268,15 @@ compatible = "amlogic, amlogic-new-usb2"; status = "okay"; portnum = <4>; - reg = <0x0 0xffe09000 0x0 0x80 - 0x0 0xffd01008 0x0 0x4>; + reg = <0xffe09000 0x80 + 0xffd01008 0x4>; }; usb3_phy: usb3phy@ffe09080 { compatible = "amlogic, amlogic-new-usb3"; status = "okay"; portnum = <0>; - reg = <0x0 0xffe09080 0x0 0x20>; + reg = <0xffe09080 0x20>; interrupts = <0 16 4>; otg = <1>; gpio-vbus-power = "GPIOAO_5"; @@ -278,7 +286,7 @@ dwc2_a { compatible = "amlogic, dwc2"; device_name = "dwc2_a"; - reg = <0x0 0xff400000 0x0 0x40000>; + reg = <0xff400000 0x40000>; status = "okay"; interrupts = <0 31 4>; pl-periph-id = <0>; /** lm name */ @@ -306,11 +314,11 @@ pcie_A: pcieA@f9800000 { compatible = "amlogic, amlogic-pcie", "snps,dw-pcie"; - reg = <0x0 0xf9800000 0x0 0x400000 - 0x0 0xff646000 0x0 0x2000 - 0x0 0xf9f00000 0x0 0x100000 - 0x0 PCIE_PHY_REG 0x0 PCIE_PHY_SIZE - 0x0 PCIE_RESET_REG 0x0 PCIE_RESET_SIZE>; + reg = <0xf9800000 0x400000 + 0xff646000 0x2000 + 0xf9f00000 0x100000 + PCIE_PHY_REG PCIE_PHY_SIZE + PCIE_RESET_REG PCIE_RESET_SIZE>; reg-names = "elbi", "cfg", "config", "phy", "reset"; reset-gpio = <&gpio GPIOX_19 GPIO_ACTIVE_HIGH>; interrupts = <0 177 0>; @@ -321,7 +329,7 @@ interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &gic GIC_SPI 179 IRQ_TYPE_EDGE_RISING>; device_type = "pci"; - ranges = <0x82000000 0 0 0x0 0xf9c00000 0 0x00300000>; + ranges = <0x82000000 0 0 0xf9c00000 0 0x00300000>; /* non-prefetchable memory */ num-lanes = <1>; pcie-num = <1>; @@ -345,11 +353,11 @@ pcie_B: pcieB@fa000000 { compatible = "amlogic, amlogic-pcie", "snps,dw-pcie"; - reg = <0x0 0xfa000000 0x0 0x400000 - 0x0 0xff648000 0x0 0x2000 - 0x0 0xfa400000 0x0 0x100000 - 0x0 PCIE_PHY_REG 0x0 PCIE_PHY_SIZE - 0x0 PCIE_RESET_REG 0x0 PCIE_RESET_SIZE>; + reg = <0xfa000000 0x400000 + 0xff648000 0x2000 + 0xfa400000 0x100000 + PCIE_PHY_REG PCIE_PHY_SIZE + PCIE_RESET_REG PCIE_RESET_SIZE>; reg-names = "elbi", "cfg", "config", "phy", "reset"; reset-gpio = <&gpio GPIOZ_10 GPIO_ACTIVE_HIGH>; interrupts = <0 167 0>; @@ -360,9 +368,9 @@ interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &gic GIC_SPI 169 IRQ_TYPE_EDGE_RISING>; device_type = "pci"; - ranges = <0x81000000 0 0 0 0xfa500000 0x0 0x10000 + ranges = <0x81000000 0 0 0xfa500000 0x0 0x10000 /* downstream I/O */ - 0x82000000 0 0xfa510000 0x0 0xfa510000 0 0x002f0000>; + 0x82000000 0 0xfa510000 0xfa510000 0 0x002f0000>; /* non-prefetchable memory */ num-lanes = <1>; pcie-num = <2>; @@ -387,7 +395,7 @@ uart_A: serial@ffd24000 { compatible = "amlogic, meson-uart"; - reg = <0x0 0xffd24000 0x0 0x18>; + reg = <0xffd24000 0x18>; interrupts = <0 26 1>; status = "okay"; clocks = <&xtal @@ -401,7 +409,7 @@ uart_B: serial@ffd23000 { compatible = "amlogic, meson-uart"; - reg = <0x0 0xffd23000 0x0 0x18>; + reg = <0xffd23000 0x18>; interrupts = <0 75 1>; status = "disable"; clocks = <&xtal @@ -413,6 +421,14 @@ pinctrl-0 = <&b_uart_pins>; }; + meson-irblaster { + compatible = "amlogic, am_irblaster"; + dev_name = "meson-irblaster"; + status = "disable"; + pinctrl-names = "default"; + pinctrl-0 = <&irblaster_pins>; + }; + vpu { compatible = "amlogic, vpu-axg"; dev_name = "vpu"; @@ -441,14 +457,14 @@ aml_snd_iomap { compatible = "amlogic, snd-iomap"; status = "okay"; - #address-cells=<2>; - #size-cells=<2>; + #address-cells=<1>; + #size-cells=<1>; ranges; pdm_bus { - reg = <0x0 0xFF632000 0x0 0x2000>; + reg = <0xFF632000 0x2000>; }; audiobus_base { - reg = <0x0 0xFF642000 0x0 0x2000>; + reg = <0xFF642000 0x2000>; }; }; pdm_codec:dummy{ @@ -468,6 +484,8 @@ aml-audio-card,loopback = <&aml_loopback>; + aml-audio-card,hp-det-gpio = <&gpio GPIOZ_7 GPIO_ACTIVE_LOW>; + aml-audio-card,dai-link@0 { format = "dsp_a"; mclk-fs = <512>; @@ -479,12 +497,12 @@ tdmacpu: cpu { sound-dai = <&aml_tdma>; dai-tdm-slot-tx-mask = - <1 1 1 1 1 1 1 1>; + <1>; dai-tdm-slot-rx-mask = - <1 1 1 1 1 1 1 1>; - dai-tdm-slot-num = <8>; + <1>; + dai-tdm-slot-num = <1>; dai-tdm-slot-width = <32>; - system-clock-frequency = <24576000>; + system-clock-frequency = <512000>; }; tdmacodec: codec { sound-dai = <&dummy_codec &dummy_codec>; @@ -523,7 +541,7 @@ aml-audio-card,dai-link@2 { format = "i2s"; mclk-fs = <256>; - continuous-clock; + //continuous-clock; //bitclock-inversion; //frame-inversion; //bitclock-master = <&aml_tdmc>; @@ -544,7 +562,7 @@ }; aml-audio-card,dai-link@3 { - mclk-fs = <64>; + mclk-fs = <256>; cpu { sound-dai = <&aml_pdm>; }; @@ -586,6 +604,7 @@ dev_name = "aml_wifi"; status = "okay"; interrupt_pin = <&gpio GPIOX_6 GPIO_ACTIVE_HIGH>; + interrupts = < 0 67 4>; irq_trigger_type = "GPIO_IRQ_LOW"; power_on_pin2 = <&gpio GPIOX_16 GPIO_ACTIVE_HIGH>; power_on_pin = <&gpio GPIOX_7 GPIO_ACTIVE_HIGH>; @@ -609,9 +628,9 @@ }; sd_emmc_c: emmc@ffe07000 { - status = "okay"; + status = "disabled"; compatible = "amlogic, meson-mmc-axg"; - reg = <0x0 0xffe07000 0x0 0x2000>; + reg = <0xffe07000 0x2000>; interrupts = <0 218 1>; pinctrl-names = "emmc_clk_cmd_pins", "emmc_all_pins"; pinctrl-0 = <&emmc_clk_cmd_pins>; @@ -659,7 +678,7 @@ sd_emmc_b:sdio@ffe05000 { status = "okay"; compatible = "amlogic, meson-mmc-axg"; - reg = <0x0 0xffe05000 0x0 0x2000>; + reg = <0xffe05000 0x2000>; interrupts = <0 217 4>; pinctrl-names = "sdio_clk_cmd_pins", "sdio_all_pins"; pinctrl-0 = <&sdio_clk_cmd_pins>; @@ -701,7 +720,7 @@ }; partitions: partitions{ - parts = <14>; + parts = <11>; part-0 = <&logo>; part-1 = <&recovery>; part-2 = <&rsv>; @@ -710,12 +729,9 @@ part-5 = <&misc>; part-6 = <&instaboot>; part-7 = <&boot>; - part-8 = <&vendor>; - part-9 = <&odm>; - part-10 = <&system>; - part-11 = <&cache>; - part-12 = <&udisk>; - part-13 = <&data>; + part-8 = <&system>; + part-9 = <&cache>; + part-10 = <&data>; logo:logo{ pname = "logo"; @@ -758,22 +774,10 @@ size = <0x0 0x2000000>; mask = <1>; }; - vendor:vendor - { - pname = "vendor"; - size = <0x0 0x10000000>; - mask = <1>; - }; - odm:odm - { - pname = "odm"; - size = <0x0 0x10000000>; - mask = <1>; - }; system:system { pname = "system"; - size = <0x0 0x82000000>; + size = <0x0 0x80000000>; mask = <1>; }; cache:cache @@ -782,12 +786,6 @@ size = <0x0 0x20000000>; mask = <2>; }; - udisk:udisk - { - pname = "udisk"; - size = <0x0 0x20000000>; - mask = <2>; - }; data:data { pname = "data"; @@ -811,6 +809,7 @@ /** 0:VPU free scale 1:OSD free scale 2:OSD super scale */ display_size_default = <768 1024 768 2048 32>; /*768*1024*4*2 = 0x600000*/ + mem_alloc = <1>; logo_addr = "0x3e000000"; pxp_mode = <0>; /** 0:normal mode 1:pxp mode */ }; @@ -827,7 +826,7 @@ clock-names = "clk_vapb_0", "clk_ge2d", "clk_ge2d_gate"; - reg = <0x0 0xff940000 0x0 0x10000>; + reg = <0xff940000 0x10000>; }; adc_keypad { @@ -889,7 +888,11 @@ key-permit = "read","write","del"; }; };//End unifykey - + audio_data: audio_data { + compatible = "amlogic, audio_data"; + query_licence_cmd = <0x82000050>; + status = "okay"; + }; }; /* end of / */ &efuse { status = "ok"; @@ -935,11 +938,17 @@ pinctrl-names="default"; pinctrl-0=<&ao_i2c_master_pin2>; - pca9557: pca9557@0x1f { - compatible = "nxp,pca9557"; - reg = <0x1f>; - status = "okay"; + aml_pca9557: aml_pca9557@0x1f { + compatible = "amlogic,pca9557_keypad"; + reg = <0x1f>; + key_num = <4>; + key_name = "fdr", "hotword", "pause", "mute"; + key_value = <106 105 139 116>; + key_index_mask = <0x4 0x8 0x10 0x20>; + key_input_mask = <0x3C>; + status = "okay"; }; + tlv320adc3101_30: tlv320adc3101_30@30 { compatible = "ti,tlv320adc3101"; #sound-dai-cells = <0>; @@ -958,6 +967,84 @@ reg = <0x1b>; status = "disable"; }; + + es7243_10: es7243_10@10 { + compatible = "MicArray_0"; + #sound-dai-cells = <0>; + reg = <0x10>; + status = "disable"; + }; + es7243_12: es7243_12@12 { + compatible = "MicArray_1"; + #sound-dai-cells = <0>; + reg = <0x12>; + status = "disable"; + }; + es7243_13: es7243_13@13 { + compatible = "MicArray_2"; + #sound-dai-cells = <0>; + reg = <0x13>; + status = "disable"; + }; + cy8c4014_08: cy8c4014_08@08 { + compatible = "cy8c4014"; + #sound-dai-cells = <0>; + reg = <0x8>; + status = "okay"; + }; + is31fl3236a: is31f3236a@0x78 { + compatible = "issi,is31fl3236,gva"; + reg = <0x3c>; + status = "okay"; + led1_b { + label="LED1_B"; + reg_offset = <1>; + }; + led1_g { + label="LED1_G"; + reg_offset = <2>; + }; + led1_r { + label="LED1_R"; + reg_offset = <3>; + }; + led2_b { + label="LED2_B"; + reg_offset = <4>; + }; + led2_g { + label="LED2_G"; + reg_offset = <5>; + }; + led2_r { + label="LED2_R"; + reg_offset = <6>; + }; + led3_b { + label="LED3_B"; + reg_offset = <7>; + }; + led3_g { + label="LED3_G"; + reg_offset = <8>; + }; + led3_r { + label="LED3_R"; + reg_offset = <9>; + }; + led4_b { + label="LED4_B"; + reg_offset = <10>; + }; + led4_g { + label="LED4_G"; + reg_offset = <11>; + }; + led4_r { + label="LED4_R"; + reg_offset = <12>; + }; + }; }; &audiobus { @@ -977,7 +1064,8 @@ aml_tdmb: tdmb { compatible = "amlogic, axg-snd-tdmb"; #sound-dai-cells = <0>; - dai-tdm-lane-slot-mask-in = <1 1 1 1>; + /*dai-tdm-lane-slot-mask-in = <1 1 1 1>;*/ + dai-tdm-lane-slot-mask-in = <0 0 0 1>; dai-tdm-clk-sel = <1>; clocks = <&clkaudio CLKID_AUDIO_MCLK_B &clkc CLKID_MPLL1>; @@ -990,7 +1078,7 @@ compatible = "amlogic, axg-snd-tdmc"; #sound-dai-cells = <0>; dai-tdm-lane-slot-mask-in = <0 1 0 0>; - dai-tdm-lane-slot-mask-out = <1 0 1 1>; + dai-tdm-lane-slot-mask-out = <0 0 1 1>; dai-tdm-clk-sel = <2>; clocks = <&clkaudio CLKID_AUDIO_MCLK_C &clkc CLKID_MPLL2>; @@ -1016,20 +1104,6 @@ interrupt-names = "irq_spdifin"; pinctrl-names = "spdif_pins"; pinctrl-0 = <&spdifout &spdifin>; - - /* - * whether do asrc for pcm. - * if raw data, asrc is disabled automatically - * 0: "Disable", - * 1: "Enable:32K", - * 2: "Enable:44K", - * 3: "Enable:48K", - * 4: "Enable:88K", - * 5: "Enable:96K", - * 6: "Enable:176K", - * 7: "Enable:192K", - */ - auto_asrc = <0>; status = "okay"; }; aml_pdm: pdm { @@ -1053,6 +1127,7 @@ aml_loopback: loopback { compatible = "amlogic, snd-loopback"; + /* * external loopback clock config * enable clk while pdm record data @@ -1064,6 +1139,7 @@ * 0: out rate = in data rate; * 1: out rate = loopback data rate; */ + lb_mode = <0>; /* datain src @@ -1074,8 +1150,8 @@ * 4: pdmin; */ datain_src = <4>; - datain_chnum = <8>; - datain_chmask = <0x7f>; + datain_chnum = <4>; + datain_chmask = <0x3>; /* tdmin_lb src * 0: tdmoutA @@ -1085,58 +1161,16 @@ * 4: PAD_tdminB * 5: PAD_tdminC */ + /*if tdmin_lb >= 3, use external loopback*/ datalb_src = <2>; datalb_chnum = <2>; /*config which data pin as loopback*/ /*datalb-lane-mask-in = <0 0 0 1>;*/ - datalb_chmask = <0x1>; + datalb_chmask = <0x3>; status = "okay"; }; - - audioresample: resample { - compatible = "amlogic, axg-resample"; - clocks = <&clkc CLKID_MPLL3 - &clkaudio CLKID_AUDIO_MCLK_F - &clkaudio CLKID_AUDIO_RESAMPLE_CTRL>; - clock-names = "resample_pll", "resample_src", "resample_clk"; - /*same with toddr_src - * TDMIN_A, - * TDMIN_B, - * TDMIN_C, - * SPDIFIN, - * PDMIN, - * NONE, - * TDMIN_LB, - * LOOPBACK, - */ - resample_module = <3>; - status = "okay"; - }; - aml_pwrdet: pwrdet { - compatible = "amlogic, axg-power-detect"; - - interrupts = ; - interrupt-names = "pwrdet_irq"; - - /* pwrdet source sel - * 7: loopback; - * 6: tdmin_lb; - * 5: reserved; - * 4: pdmin; - * 3: spdifin; - * 2: tdmin_c; - * 1: tdmin_b; - * 0: tdmin_a; - */ - pwrdet_src = <4>; - - hi_th = <0x70000>; - lo_th = <0x16000>; - - status = "disabled"; - }; }; /* end of audiobus */ &pinctrl_periphs { @@ -1257,7 +1291,7 @@ &aobus{ uart_AO: serial@3000 { compatible = "amlogic, meson-uart"; - reg = <0x0 0x3000 0x0 0x18>; + reg = <0x3000 0x18>; interrupts = <0 193 1>; status = "okay"; clocks = <&xtal>; @@ -1271,7 +1305,7 @@ uart_AO_B: serial@4000 { compatible = "amlogic, meson-uart"; - reg = <0x0 0x4000 0x0 0x18>; + reg = <0x4000 0x18>; interrupts = <0 197 1>; status = "disable"; clocks = <&xtal>; diff --git a/arch/arm64/boot/dts/amlogic/axg_s400emmc_v03.dts b/arch/arm/boot/dts/amlogic/axg_s400emmc_512m.dts similarity index 91% rename from arch/arm64/boot/dts/amlogic/axg_s400emmc_v03.dts rename to arch/arm/boot/dts/amlogic/axg_s400emmc_512m.dts index aba276dff32f..d9655703c2d6 100644 --- a/arch/arm64/boot/dts/amlogic/axg_s400emmc_v03.dts +++ b/arch/arm/boot/dts/amlogic/axg_s400emmc_512m.dts @@ -1,5 +1,5 @@ /* - * arch/arm64/boot/dts/amlogic/axg_s400_v03.dts + * arch/arm/boot/dts/amlogic/axg_s400emmc.dts * * Copyright (C) 2017 Amlogic, Inc. All rights reserved. * @@ -19,32 +19,38 @@ #include "mesonaxg.dtsi" #include "mesonaxg_s400-panel.dtsi" +#include "partition_mbox_normal.dtsi" / { model = "Amlogic"; - amlogic-dt-id = "axg_s400_v03"; + amlogic-dt-id = "axg_s400emmc_512m"; compatible = "amlogic, axg"; interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; + #address-cells = <1>; + #size-cells = <1>; aliases { serial0 = &uart_AO; serial1 = &uart_A; }; + ion_dev { + compatible = "amlogic, ion_dev"; + memory-region = <&ion_reserved>; + }; + memory@00000000 { device_type = "memory"; - linux,usable-memory = <0x0 0x000000 0x0 0x40000000>; + linux,usable-memory = <0x000000 0x20000000>; }; reserved-memory { - #address-cells = <2>; - #size-cells = <2>; + #address-cells = <1>; + #size-cells = <1>; ranges; /* global autoconfigured region for contiguous allocations */ ramoops@0x07400000 { compatible = "ramoops"; - reg = <0x0 0x07400000 0x0 0x00100000>; + reg = <0x07400000 0x00100000>; record-size = <0x8000>; console-size = <0x8000>; ftrace-size = <0x0>; @@ -54,32 +60,39 @@ secmon_reserved:linux,secmon { compatible = "shared-dma-pool"; reusable; - size = <0x0 0x400000>; - alignment = <0x0 0x400000>; - alloc-ranges = <0x0 0x05000000 0x0 0x400000>; + size = <0x400000>; + alignment = <0x400000>; + alloc-ranges = <0x05000000 0x400000>; }; secos_reserved:linux,secos { status = "disable"; compatible = "amlogic, aml_secos_memory"; - reg = <0x0 0x05300000 0x0 0x2000000>; + reg = <0x05300000 0x2000000>; no-map; }; fb_reserved:linux,meson-fb { //compatible = "amlogic, fb-memory"; - //reg = <0x0 0x3e000000 0x0 0x1f00000>; + //reg = <0x3e000000 0x1f00000>; compatible = "shared-dma-pool"; reusable; - size = <0x0 0x2000000>; - alignment = <0x0 0x400000>; - alloc-ranges = <0x0 0x3e000000 0x0 0x2000000>; + size = <0x2000000>; + alignment = <0x400000>; + alloc-ranges = <0x3e000000 0x2000000>; + }; + + ion_reserved:linux,ion-dev { + compatible = "shared-dma-pool"; + reusable; + size = <0x2000000>; + alignment = <0x400000>; }; }; mtd_nand { compatible = "amlogic, aml_mtd_nand"; dev_name = "mtdnand"; status = "disable"; - reg = <0x0 0xFFE07800 0x0 0x200>; + reg = <0xFFE07800 0x200>; interrupts = < 0 34 1 >; pinctrl-names = "nand_rb_mod","nand_norb_mod", "nand_cs_only"; pinctrl-0 = <&all_nand_pins>; @@ -166,8 +179,8 @@ ethmac: ethernet@0xff3f0000 { compatible = "amlogic, gxbb-eth-dwmac"; - reg = <0x0 0xff3f0000 0x0 0x10000 - 0x0 0xff634540 0x0 0x8>; + reg = <0xff3f0000 0x10000 + 0xff634540 0x8>; interrupts = <0 8 1>; pinctrl-names = "external_eth_pins"; pinctrl-0 = <&external_eth_pins>; @@ -255,7 +268,7 @@ dwc3: dwc3@ff500000 { compatible = "synopsys, dwc3"; status = "okay"; - reg = <0x0 0xff500000 0x0 0x100000>; + reg = <0xff500000 0x100000>; interrupts = <0 30 4>; usb-phy = <&usb2_phy>, <&usb3_phy>; cpu-type = "gxl"; @@ -268,15 +281,15 @@ compatible = "amlogic, amlogic-new-usb2"; status = "okay"; portnum = <4>; - reg = <0x0 0xffe09000 0x0 0x80 - 0x0 0xffd01008 0x0 0x4>; + reg = <0xffe09000 0x80 + 0xffd01008 0x4>; }; usb3_phy: usb3phy@ffe09080 { compatible = "amlogic, amlogic-new-usb3"; status = "okay"; portnum = <0>; - reg = <0x0 0xffe09080 0x0 0x20>; + reg = <0xffe09080 0x20>; interrupts = <0 16 4>; otg = <1>; gpio-vbus-power = "GPIOAO_5"; @@ -286,7 +299,7 @@ dwc2_a { compatible = "amlogic, dwc2"; device_name = "dwc2_a"; - reg = <0x0 0xff400000 0x0 0x40000>; + reg = <0xff400000 0x40000>; status = "okay"; interrupts = <0 31 4>; pl-periph-id = <0>; /** lm name */ @@ -314,11 +327,11 @@ pcie_A: pcieA@f9800000 { compatible = "amlogic, amlogic-pcie", "snps,dw-pcie"; - reg = <0x0 0xf9800000 0x0 0x400000 - 0x0 0xff646000 0x0 0x2000 - 0x0 0xf9f00000 0x0 0x100000 - 0x0 PCIE_PHY_REG 0x0 PCIE_PHY_SIZE - 0x0 PCIE_RESET_REG 0x0 PCIE_RESET_SIZE>; + reg = <0xf9800000 0x400000 + 0xff646000 0x2000 + 0xf9f00000 0x100000 + PCIE_PHY_REG PCIE_PHY_SIZE + PCIE_RESET_REG PCIE_RESET_SIZE>; reg-names = "elbi", "cfg", "config", "phy", "reset"; reset-gpio = <&gpio GPIOX_19 GPIO_ACTIVE_HIGH>; interrupts = <0 177 0>; @@ -329,7 +342,7 @@ interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &gic GIC_SPI 179 IRQ_TYPE_EDGE_RISING>; device_type = "pci"; - ranges = <0x82000000 0 0 0x0 0xf9c00000 0 0x00300000>; + ranges = <0x82000000 0 0 0xf9c00000 0 0x00300000>; /* non-prefetchable memory */ num-lanes = <1>; pcie-num = <1>; @@ -353,11 +366,11 @@ pcie_B: pcieB@fa000000 { compatible = "amlogic, amlogic-pcie", "snps,dw-pcie"; - reg = <0x0 0xfa000000 0x0 0x400000 - 0x0 0xff648000 0x0 0x2000 - 0x0 0xfa400000 0x0 0x100000 - 0x0 PCIE_PHY_REG 0x0 PCIE_PHY_SIZE - 0x0 PCIE_RESET_REG 0x0 PCIE_RESET_SIZE>; + reg = <0xfa000000 0x400000 + 0xff648000 0x2000 + 0xfa400000 0x100000 + PCIE_PHY_REG PCIE_PHY_SIZE + PCIE_RESET_REG PCIE_RESET_SIZE>; reg-names = "elbi", "cfg", "config", "phy", "reset"; reset-gpio = <&gpio GPIOZ_10 GPIO_ACTIVE_HIGH>; interrupts = <0 167 0>; @@ -368,9 +381,9 @@ interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &gic GIC_SPI 169 IRQ_TYPE_EDGE_RISING>; device_type = "pci"; - ranges = <0x81000000 0 0 0 0xfa500000 0x0 0x10000 + ranges = <0x81000000 0 0 0xfa500000 0x0 0x10000 /* downstream I/O */ - 0x82000000 0 0xfa510000 0x0 0xfa510000 0 0x002f0000>; + 0x82000000 0 0xfa510000 0xfa510000 0 0x002f0000>; /* non-prefetchable memory */ num-lanes = <1>; pcie-num = <2>; @@ -395,7 +408,7 @@ uart_A: serial@ffd24000 { compatible = "amlogic, meson-uart"; - reg = <0x0 0xffd24000 0x0 0x18>; + reg = <0xffd24000 0x18>; interrupts = <0 26 1>; status = "okay"; clocks = <&xtal @@ -409,7 +422,7 @@ uart_B: serial@ffd23000 { compatible = "amlogic, meson-uart"; - reg = <0x0 0xffd23000 0x0 0x18>; + reg = <0xffd23000 0x18>; interrupts = <0 75 1>; status = "disable"; clocks = <&xtal @@ -449,14 +462,14 @@ aml_snd_iomap { compatible = "amlogic, snd-iomap"; status = "okay"; - #address-cells=<2>; - #size-cells=<2>; + #address-cells=<1>; + #size-cells=<1>; ranges; pdm_bus { - reg = <0x0 0xFF632000 0x0 0x2000>; + reg = <0xFF632000 0x2000>; }; audiobus_base { - reg = <0x0 0xFF642000 0x0 0x2000>; + reg = <0xFF642000 0x2000>; }; }; pdm_codec:dummy{ @@ -484,6 +497,10 @@ //frame-inversion; //bitclock-master = <&tdmacodec>; //frame-master = <&tdmacodec>; + /* suffix-name, sync with android audio hal + * what's the dai link used for + */ + suffix-name = "alsaPORT-pcm"; tdmacpu: cpu { sound-dai = <&aml_tdma>; dai-tdm-slot-tx-mask = @@ -507,6 +524,12 @@ //frame-inversion; bitclock-master = <&aml_tdmb>; frame-master = <&aml_tdmb>; + //bitclock-master = <&tdmbcodec>; + //frame-master = <&tdmbcodec>; + /* suffix-name, sync with android audio hal + * what's the dai link used for + */ + //suffix-name = "alsaPORT-i2s"; cpu { sound-dai = <&aml_tdmb>; dai-tdm-slot-tx-mask = <1 1>; @@ -531,11 +554,15 @@ aml-audio-card,dai-link@2 { format = "i2s"; mclk-fs = <256>; - //continuous-clock; + continuous-clock; //bitclock-inversion; //frame-inversion; //bitclock-master = <&aml_tdmc>; //frame-master = <&aml_tdmc>; + /* suffix-name, sync with android audio hal + * what's the dai link used for + */ + suffix-name = "alsaPORT-i2s"; cpu { sound-dai = <&aml_tdmc>; dai-tdm-slot-tx-mask = <1 1>; @@ -552,7 +579,11 @@ }; aml-audio-card,dai-link@3 { - mclk-fs = <256>; + mclk-fs = <64>; + /* suffix-name, sync with android audio hal + * what's the dai link used for + */ + suffix-name = "alsaPORT-pdm"; cpu { sound-dai = <&aml_pdm>; }; @@ -572,6 +603,10 @@ aml-audio-card,dai-link@4 { mclk-fs = <128>; + /* suffix-name, sync with android audio hal + * what's the dai link used for + */ + suffix-name = "alsaPORT-spdif"; cpu { sound-dai = <&aml_spdif>; system-clock-frequency = <6144000>; @@ -594,7 +629,6 @@ dev_name = "aml_wifi"; status = "okay"; interrupt_pin = <&gpio GPIOX_6 GPIO_ACTIVE_HIGH>; - interrupts = < 0 67 4>; irq_trigger_type = "GPIO_IRQ_LOW"; power_on_pin2 = <&gpio GPIOX_16 GPIO_ACTIVE_HIGH>; power_on_pin = <&gpio GPIOX_7 GPIO_ACTIVE_HIGH>; @@ -620,7 +654,7 @@ sd_emmc_c: emmc@ffe07000 { status = "okay"; compatible = "amlogic, meson-mmc-axg"; - reg = <0x0 0xffe07000 0x0 0x2000>; + reg = <0xffe07000 0x2000>; interrupts = <0 218 1>; pinctrl-names = "emmc_clk_cmd_pins", "emmc_all_pins"; pinctrl-0 = <&emmc_clk_cmd_pins>; @@ -652,11 +686,11 @@ "MMC_CAP_HW_RESET", "MMC_CAP_ERASE", "MMC_CAP_CMD23"; - caps2 = "MMC_CAP2_HS200", "MMC_CAP2_HS400"; f_min = <400000>; - f_max = <200000000>; + f_max = <100000000>; max_req_size = <0x20000>; /**128KB*/ gpio_dat3 = <&gpio BOOT_3 GPIO_ACTIVE_HIGH>; + tx_delay = <8>; hw_reset = <&gpio BOOT_9 GPIO_ACTIVE_HIGH>; card_type = <1>; /* 1:mmc card(include eMMC), @@ -668,7 +702,7 @@ sd_emmc_b:sdio@ffe05000 { status = "okay"; compatible = "amlogic, meson-mmc-axg"; - reg = <0x0 0xffe05000 0x0 0x2000>; + reg = <0xffe05000 0x2000>; interrupts = <0 217 4>; pinctrl-names = "sdio_clk_cmd_pins", "sdio_all_pins"; pinctrl-0 = <&sdio_clk_cmd_pins>; @@ -814,11 +848,11 @@ 0 89 1>; interrupt-names = "viu-vsync", "rdma"; mem_size = <0x00300000 0x1800000 0x00000000>; - /* uboot logo,fb0/fb1 memory size */ - display_mode_default = "1080p60hz"; + /* uboot logo,fb0/fb1 memory size,if afbcd fb0=0x0b51000*/ + display_mode_default = "720p60hz"; scale_mode = <0>; - /** 0:VPU free scale 1:OSD free scale 2:OSD super scale */ - display_size_default = <768 1024 768 2048 32>; + /*1280*720*4*2 = 0xA8C000*/ + display_size_default = <1280 720 1280 1440 32>; /*768*1024*4*2 = 0x600000*/ logo_addr = "0x3e000000"; pxp_mode = <0>; /** 0:normal mode 1:pxp mode */ @@ -836,7 +870,7 @@ clock-names = "clk_vapb_0", "clk_ge2d", "clk_ge2d_gate"; - reg = <0x0 0xff940000 0x0 0x10000>; + reg = <0xff940000 0x10000>; }; adc_keypad { @@ -1267,7 +1301,7 @@ &aobus{ uart_AO: serial@3000 { compatible = "amlogic, meson-uart"; - reg = <0x0 0x3000 0x0 0x18>; + reg = <0x3000 0x18>; interrupts = <0 193 1>; status = "okay"; clocks = <&xtal>; @@ -1281,7 +1315,7 @@ uart_AO_B: serial@4000 { compatible = "amlogic, meson-uart"; - reg = <0x0 0x4000 0x0 0x18>; + reg = <0x4000 0x18>; interrupts = <0 197 1>; status = "disable"; clocks = <&xtal>; diff --git a/arch/arm/boot/dts/amlogic/axg_s420_128m.dts b/arch/arm/boot/dts/amlogic/axg_s420_128m.dts new file mode 100644 index 000000000000..d9be9f0cf117 --- /dev/null +++ b/arch/arm/boot/dts/amlogic/axg_s420_128m.dts @@ -0,0 +1,1063 @@ +/* + * arch/arm/boot/dts/amlogic/axg_s420_128m.dts + * + * Copyright (C) 2017 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +/dts-v1/; + +#include "mesonaxg.dtsi" + +/ { + model = "Amlogic"; + amlogic-dt-id= "axg_s420_128m"; + compatible = "amlogic, axg"; + interrupt-parent = <&gic>; + #address-cells = <1>; + #size-cells = <1>; + + aliases { + serial0 = &uart_AO; + serial1 = &uart_A; + }; + + memory@00000000 { + device_type = "memory"; + linux,usable-memory = <0x000000 0x8000000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + /* global autoconfigured region for contiguous allocations */ + secmon_reserved:linux,secmon { + compatible = "shared-dma-pool"; + reusable; + size = <0x300000>; + alignment = <0x300000>; + alloc-ranges = <0x05000000 0x300000>; + }; + + secos_reserved:linux,secos { + status = "disable"; + compatible = "amlogic, aml_secos_memory"; + reg = <0x05300000 0x2000000>; + no-map; + }; + }; + mtd_nand { + compatible = "amlogic, aml_mtd_nand"; + dev_name = "mtdnand"; + status = "okay"; + reg = <0xFFE07800 0x200>; + interrupts = < 0 34 1 >; + pinctrl-names = "nand_rb_mod","nand_norb_mod", "nand_cs_only"; + pinctrl-0 = <&all_nand_pins>; + pinctrl-1 = <&all_nand_pins>; + pinctrl-2 = <&nand_cs_pins>; + device_id = <0>; + + /*fip/tpl configurations, must be same + * with uboot if bl_mode was set as 1 + * bl_mode: 0 compact mode; 1 descrete mode + * if bl_mode was set as 1, fip configeration will work + */ + bl_mode = <1>; + /*copy count of fip*/ + fip_copies = <4>; + /*size of each fip copy */ + fip_size = <0x200000>; + nand_clk_ctrl = <0xFFE07000>; + plat-names = "bootloader","nandnormal"; + plat-num = <2>; + plat-part-0 = <&bootloader>; + plat-part-1 = <&nandnormal>; + bootloader: bootloader{ + enable_pad ="ce0"; + busy_pad = "rb0"; + timming_mode = "mode5"; + bch_mode = "bch8_1k"; + t_rea = <20>; + t_rhoh = <15>; + chip_num = <1>; + part_num = <0>; + rb_detect = <1>; + }; + nandnormal: nandnormal{ + enable_pad ="ce0"; + busy_pad = "rb0"; + timming_mode = "mode5"; + bch_mode = "bch8_1k"; + plane_mode = "twoplane"; + t_rea = <20>; + t_rhoh = <15>; + chip_num = <2>; + part_num = <3>; + partition = <&nand_partitions>; + rb_detect = <1>; + }; + nand_partitions:nand_partition{ + /* + * if bl_mode is 1, tpl size was generate by + * fip_copies * fip_size which + * will not skip bad when calculating + * the partition size; + * + * if bl_mode is 0, + * tpl partition must be comment out. + */ + tpl{ + offset=<0x0 0x0>; + size=<0x0 0x0>; + }; + misc{ + offset=<0x0 0x0>; + size=<0x0 0x200000>; + }; + logo{ + offset=<0x0 0x0>; + size=<0x0 0x200000>; + }; + recovery{ + offset=<0x0 0x0>; + size=<0x0 0x1000000>; + }; + boot{ + offset=<0x0 0x0>; + size=<0x0 0xF00000>; + }; + system{ + offset=<0x0 0x0>; + size=<0x0 0x11800000>; + }; + data{ + offset=<0xffffffff 0xffffffff>; + size=<0x0 0x0>; + }; + }; + }; + + + aml_sensor0: aml-sensor@0 { + compatible = "amlogic, aml-thermal"; + device_name = "thermal"; + #thermal-sensor-cells = <1>; + cooling_devices { + cpufreq_cool_cluster0 { + min_state = <1000000>; + dyn_coeff = <140>; + cluster_id = <0>; + node_name = "cpufreq_cool0"; + device_type = "cpufreq"; + }; + cpucore_cool_cluster0 { + min_state = <1>; + dyn_coeff = <0>; + cluster_id = <0>; + node_name = "cpucore_cool0"; + device_type = "cpucore"; + }; + }; + cpufreq_cool0:cpufreq_cool0 { + #cooling-cells = <2>; /* min followed by max */ + }; + cpucore_cool0:cpucore_cool0 { + #cooling-cells = <2>; /* min followed by max */ + }; + }; + thermal-zones { + soc_thermal { + polling-delay = <1000>; + polling-delay-passive = <100>; + sustainable-power = <1050>; + + thermal-sensors = <&aml_sensor0 3>; + + trips { + switch_on: trip-point@0 { + temperature = <70000>; + hysteresis = <1000>; + type = "passive"; + }; + control: trip-point@1 { + temperature = <80000>; + hysteresis = <1000>; + type = "passive"; + }; + hot: trip-point@2 { + temperature = <85000>; + hysteresis = <5000>; + type = "hot"; + }; + critical: trip-point@3 { + temperature = <260000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + + cooling-maps { + cpufreq_cooling_map { + trip = <&control>; + cooling-device = <&cpufreq_cool0 0 4>; + contribution = <1024>; + }; + cpucore_cooling_map { + trip = <&control>; + cooling-device = <&cpucore_cool0 0 3>; + contribution = <1024>; + }; + }; + }; + }; + + dwc3: dwc3@ff500000 { + compatible = "synopsys, dwc3"; + status = "okay"; + reg = <0xff500000 0x100000>; + interrupts = <0 30 4>; + usb-phy = <&usb2_phy>, <&usb3_phy>; + cpu-type = "gxl"; + clock-src = "usb3.0"; + clocks = <&clkc CLKID_USB_GENERAL>; + clock-names = "dwc_general"; + }; + + usb2_phy: usb2phy@ffe09000 { + compatible = "amlogic, amlogic-new-usb2"; + status = "okay"; + portnum = <4>; + reg = <0xffe09000 0x80 + 0xffd01008 0x4>; + }; + + usb3_phy: usb3phy@ffe09080 { + compatible = "amlogic, amlogic-new-usb3"; + status = "okay"; + portnum = <0>; + reg = <0xffe09080 0x20>; + interrupts = <0 16 4>; + otg = <1>; + gpio-vbus-power = "GPIOAO_5"; + gpios = <&gpio_ao GPIOAO_5 GPIO_ACTIVE_HIGH>; + }; + + dwc2_a { + compatible = "amlogic, dwc2"; + device_name = "dwc2_a"; + reg = <0xff400000 0x40000>; + status = "okay"; + interrupts = <0 31 4>; + pl-periph-id = <0>; /** lm name */ + clock-src = "usb0"; /** clock src */ + port-id = <0>; /** ref to mach/usb.h */ + port-type = <2>; /** 0: otg, 1: host, 2: slave */ + port-speed = <0>; /** 0: default, high, 1: full */ + port-config = <0>; /** 0: default */ + /*0:default,1:single,2:incr,3:incr4,4:incr8,5:incr16,6:disable*/ + port-dma = <0>; + port-id-mode = <0>; /** 0: hardware, 1: sw_host, 2: sw_slave*/ + usb-fifo = <728>; + cpu-type = "gxl"; + /** 0: normal, 1: otg+dwc3 host only, 2: otg+dwc3 device only*/ + controller-type = <3>; + phy-reg = <0xffe09000>; + phy-reg-size = <0xa0>; + clocks = <&clkc CLKID_USB_GENERAL + &clkc CLKID_USB1_TO_DDR + &clkc CLKID_USB1>; + clock-names = "usb_general", + "usb1", + "usb1_to_ddr"; + }; + + uart_A: serial@ffd24000 { + compatible = "amlogic, meson-uart"; + reg = <0xffd24000 0x18>; + interrupts = <0 26 1>; + status = "okay"; + clocks = <&xtal + &clkc CLKID_UART0>; + clock-names = "clk_uart", + "clk_gate"; + fifosize = < 128 >; + pinctrl-names = "default"; + pinctrl-0 = <&a_uart_pins>; + }; + + uart_B: serial@ffd23000 { + compatible = "amlogic, meson-uart"; + reg = <0xffd23000 0x18>; + interrupts = <0 75 1>; + status = "disable"; + clocks = <&xtal + &clkc CLKID_UART1>; + clock-names = "clk_uart", + "clk_gate"; + fifosize = < 64 >; + pinctrl-names = "default"; + pinctrl-0 = <&b_uart_pins>; + }; + + /* Sound iomap */ + aml_snd_iomap { + compatible = "amlogic, snd-iomap"; + status = "okay"; + #address-cells=<1>; + #size-cells=<1>; + ranges; + pdm_bus { + reg = <0xFF632000 0x2000>; + }; + audiobus_base { + reg = <0xFF642000 0x2000>; + }; + }; + pdm_codec:dummy{ + #sound-dai-cells = <0>; + compatible = "amlogic, pdm_dummy_codec"; + status = "okay"; + }; + dummy_codec:dummy{ + #sound-dai-cells = <0>; + compatible = "amlogic, aml_dummy_codec"; + status = "okay"; + }; + + auge_sound { + compatible = "amlogic, axg-sound-card"; + aml-audio-card,name = "AML-AUGESOUND"; + + aml-audio-card,loopback = <&aml_loopback>; + + aml-audio-card,dai-link@0 { + format = "dsp_a"; + mclk-fs = <256>;//512 + continuous-clock; + //bitclock-inversion; + //frame-inversion; + bitclock-master = <&aml_tdma>; + frame-master = <&aml_tdma>; + cpu { + sound-dai = <&aml_tdma>; + dai-tdm-slot-tx-mask = <1 1>; + dai-tdm-slot-rx-mask = <1 1>; + dai-tdm-slot-num = <2>; + dai-tdm-slot-width = <32>; + system-clock-frequency = <12288000>; + }; + codec { + sound-dai = <&dummy_codec &dummy_codec>; + }; + }; + + aml-audio-card,dai-link@1 { + format = "i2s"; + mclk-fs = <256>; + //continuous-clock; + //bitclock-inversion; + //frame-inversion; + bitclock-master = <&aml_tdmb>; + frame-master = <&aml_tdmb>; + cpu { + sound-dai = <&aml_tdmb>; + dai-tdm-slot-tx-mask = <1 1>; + dai-tdm-slot-rx-mask = <1 1>; + dai-tdm-slot-num = <2>; + dai-tdm-slot-width = <32>; + }; + codec { + sound-dai = <&tlv320adc3101_32>; + /*&tlv320adc3101_30>;*/ + }; + }; + + aml-audio-card,dai-link@2 { + format = "i2s"; + mclk-fs = <256>; + continuous-clock; + /* tdmb clk using tdmc so no bclk-inv */ + //bitclock-inversion; + //frame-inversion; + bitclock-master = <&aml_tdmc>; + frame-master = <&aml_tdmc>; + cpu { + sound-dai = <&aml_tdmc>; + dai-tdm-slot-tx-mask = <1 1>; + dai-tdm-slot-rx-mask = <1 1>; + dai-tdm-slot-num = <2>; + dai-tdm-slot-width = <32>; + system-clock-frequency = <12288000>; + }; + codec { + sound-dai = <&tas5707_36 &dummy_codec>; + }; + }; + + aml-audio-card,dai-link@3 { + mclk-fs = <256>; + cpu { + sound-dai = <&aml_pdm>; + }; + codec { + /* + *enable external loopback + *and tlv320adc3101 as loopback + */ + /*sound-dai = <&pdm_codec &tlv320adc3101_32>;*/ + /* + * enable internal loopback + * or disable loopback + */ + sound-dai = <&pdm_codec>; + }; + }; + + aml-audio-card,dai-link@4 { + mclk-fs = <128>; + cpu { + sound-dai = <&aml_spdif>; + }; + codec { + sound-dai = <&dummy_codec>; + }; + }; + }; + + bt-dev{ + compatible = "amlogic, bt-dev"; + dev_name = "bt-dev"; + status = "okay"; + gpio_reset = <&gpio GPIOX_21 GPIO_ACTIVE_HIGH>; + }; + + wifi{ + compatible = "amlogic, aml_wifi"; + dev_name = "aml_wifi"; + status = "okay"; + interrupt_pin = <&gpio GPIOX_6 GPIO_ACTIVE_HIGH>; + irq_trigger_type = "GPIO_IRQ_LOW"; + power_on_pin = <&gpio GPIOX_7 GPIO_ACTIVE_HIGH>; + dhd_static_buf; //if use bcm wifi, config dhd_static_buf + pinctrl-names = "default"; + pinctrl-0 = <&wifi_32k_pins>; + pwm_config = <&wifi_pwm_conf>; + }; + + wifi_pwm_conf:wifi_pwm_conf{ + pwm_channel1_conf { + pwms = <&pwm_ab MESON_PWM_0 30040 0>; + duty-cycle = <15020>; + times = <10>; + }; + pwm_channel2_conf { + pwms = <&pwm_ab MESON_PWM_2 30030 0>; + duty-cycle = <15015>; + times = <12>; + }; + }; + sd_emmc_c: emmc@ffe07000 { + status = "disabled"; + compatible = "amlogic, meson-mmc-axg"; + reg = <0xffe07000 0x2000>; + interrupts = <0 218 1>; + pinctrl-names = "emmc_clk_cmd_pins", "emmc_all_pins"; + pinctrl-0 = <&emmc_clk_cmd_pins>; + pinctrl-1 = <&emmc_conf_pull_up &emmc_conf_pull_done>; + clocks = <&clkc CLKID_SD_EMMC_C>, + <&clkc CLKID_SD_EMMC_C_P0_COMP>, + <&clkc CLKID_FCLK_DIV2>, + <&clkc CLKID_FCLK_DIV5>, + <&xtal>; + clock-names = "core", "clkin0", "clkin1", "clkin2", "xtal"; + + bus-width = <8>; + cap-sd-highspeed; + cap-mmc-highspeed; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + + max-frequency = <200000000>; + non-removable; + disable-wp; + emmc { + pinname = "emmc"; + ocr_avail = <0x200080>; /**VDD voltage 3.3 ~ 3.4 */ + caps = "MMC_CAP_8_BIT_DATA", + "MMC_CAP_MMC_HIGHSPEED", + "MMC_CAP_SD_HIGHSPEED", + "MMC_CAP_NONREMOVABLE", + "MMC_CAP_1_8V_DDR", + "MMC_CAP_HW_RESET", + "MMC_CAP_ERASE", + "MMC_CAP_CMD23"; + /*caps2 = "MMC_CAP2_HS200", "MMC_CAP2_HS400";*/ + f_min = <400000>; + f_max = <100000000>; + max_req_size = <0x20000>; /**128KB*/ + gpio_dat3 = <&gpio BOOT_3 GPIO_ACTIVE_HIGH>; + hw_reset = <&gpio BOOT_9 GPIO_ACTIVE_HIGH>; + card_type = <1>; + /* 1:mmc card(include eMMC), + * 2:sd card(include tSD) + */ + }; + }; + + sd_emmc_b:sdio@ffe05000 { + status = "okay"; + compatible = "amlogic, meson-mmc-axg"; + reg = <0xffe05000 0x2000>; + interrupts = <0 217 4>; + pinctrl-names = "sdio_clk_cmd_pins", "sdio_all_pins"; + pinctrl-0 = <&sdio_clk_cmd_pins>; + pinctrl-1 = <&sdio_all_pins>; + clocks = <&clkc CLKID_SD_EMMC_B>, + <&clkc CLKID_SD_EMMC_B_P0_COMP>, + <&clkc CLKID_FCLK_DIV2>; + clock-names = "core", "clkin0", "clkin1"; + + bus-width = <4>; + cap-sd-highspeed; + cap-mmc-highspeed; + max-frequency = <100000000>; + non-removable; + disable-wp; + sdio { + pinname = "sdio"; + ocr_avail = <0x200080>; /**VDD voltage 3.3 ~ 3.4 */ + caps = "MMC_CAP_4_BIT_DATA", + "MMC_CAP_MMC_HIGHSPEED", + "MMC_CAP_SD_HIGHSPEED", + "MMC_CAP_NONREMOVABLE", + "MMC_CAP_UHS_SDR12", + "MMC_CAP_UHS_SDR25", + "MMC_CAP_UHS_SDR50", + "MMC_CAP_UHS_SDR104", + "MMC_PM_KEEP_POWER", + "MMC_CAP_SDIO_IRQ"; + f_min = <400000>; + f_max = <200000000>; + max_req_size = <0x20000>; /**128KB*/ + card_type = <3>; + /* 3:sdio device(ie:sdio-wifi), + * 4:SD combo (IO+mem) card + */ + }; + }; + + adc_keypad { + compatible = "amlogic, adc_keypad"; + status = "okay"; + key_name = "power", "vol-", "vol+", "wifi", "<<", ">>"; + key_num = <6>; + io-channels = <&saradc SARADC_CH0>; + io-channel-names = "key-chan-0"; + key_chan = ; + key_code = <116 114 115 139 105 106>; + key_val = <0 143 266 389 512 635>; //val=voltage/1800mV*1023 + key_tolerance = <40 40 40 40 40 40>; + }; + + partitions: partitions{ + parts = <11>; + part-0 = <&logo>; + part-1 = <&recovery>; + part-2 = <&rsv>; + part-3 = <&tee>; + part-4 = <&crypt>; + part-5 = <&misc>; + part-6 = <&instaboot>; + part-7 = <&boot>; + part-8 = <&system>; + part-9 = <&cache>; + part-10 = <&data>; + + logo:logo{ + pname = "logo"; + size = <0x0 0x2000000>; + mask = <1>; + }; + recovery:recovery{ + pname = "recovery"; + size = <0x0 0x2000000>; + mask = <1>; + }; + rsv:rsv{ + pname = "rsv"; + size = <0x0 0x800000>; + mask = <1>; + }; + tee:tee{ + pname = "tee"; + size = <0x0 0x800000>; + mask = <1>; + }; + crypt:crypt{ + pname = "crypt"; + size = <0x0 0x2000000>; + mask = <1>; + }; + misc:misc{ + pname = "misc"; + size = <0x0 0x2000000>; + mask = <1>; + }; + instaboot:instaboot{ + pname = "instaboot"; + size = <0x0 0x400000>; + mask = <1>; + }; + boot:boot + { + pname = "boot"; + size = <0x0 0x2000000>; + mask = <1>; + }; + system:system + { + pname = "system"; + size = <0x0 0x80000000>; + mask = <1>; + }; + cache:cache + { + pname = "cache"; + size = <0x0 0x20000000>; + mask = <2>; + }; + data:data + { + pname = "data"; + size = <0xffffffff 0xffffffff>; + mask = <4>; + }; + }; + + unifykey{ + compatible = "amlogic, unifykey"; + status = "ok"; + + unifykey-num = <6>; + unifykey-index-0 = <&keysn_0>; + unifykey-index-1 = <&keysn_1>; + unifykey-index-2 = <&keysn_2>; + unifykey-index-3 = <&keysn_3>; + unifykey-index-4 = <&keysn_4>; + unifykey-index-5 = <&keysn_5>; + + keysn_0: key_0{ + key-name = "usid"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_1:key_1{ + key-name = "mac"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_2:key_2{ + key-name = "secure_boot_set"; + key-device = "efuse"; + key-permit = "write"; + }; + keysn_3:key_3{ + key-name = "mac_bt"; + key-device = "normal"; + key-permit = "read","write","del"; + key-type = "mac"; + }; + keysn_4:key_4{ + key-name = "mac_wifi"; + key-device = "normal"; + key-permit = "read","write","del"; + key-type = "mac"; + }; + keysn_5:key_5{ + key-name = "deviceid"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + };//End unifykey +}; /* end of / */ + +&efuse { + status = "ok"; +}; + +&pwm_ab { + status = "okay"; +}; +/* Audio Related start */ +/* for spk board */ +&i2c1 { + status = "okay"; + pinctrl-names="default"; + pinctrl-0=<&b_i2c_master>; + + tlv320adc3101_32: tlv320adc3101_32@30 { + compatible = "ti,tlv320adc3101"; + #sound-dai-cells = <0>; + reg = <0x19>; + differential_pair = <1>; + status = "okay"; + }; + + tas5707_36: tas5707_36@36 { + compatible = "ti,tas5707"; + #sound-dai-cells = <0>; + reg = <0x1b>; + status = "okay"; + reset_pin = <&gpio_ao GPIOAO_4 0>; + }; + + tas5707_3a: tas5707_3a@3a { + compatible = "ti,tas5707"; + #sound-dai-cells = <0>; + reg = <0x1d>; + status = "disable"; + }; +}; + +/* for mic board */ +&i2c_AO { + status = "okay"; + pinctrl-names="default"; + pinctrl-0=<&ao_i2c_master_pin2>; + + pca9557:pca9557@0x1f { + compatible = "nxp,pca9557"; + reg = <0x1f>; + status = "okay"; + }; + tlv320adc3101_30: tlv320adc3101_30@30 { + compatible = "ti,tlv320adc3101"; + #sound-dai-cells = <0>; + reg = <0x18>; + status = "disable"; + }; + tlv320adc3101_34: tlv320adc3101_34@30 { + compatible = "ti,tlv320adc3101"; + #sound-dai-cells = <0>; + reg = <0x1a>; + status = "disable"; + }; + tlv320adc3101_36: tlv320adc3101_36@30 { + compatible = "ti,tlv320adc3101"; + #sound-dai-cells = <0>; + reg = <0x1b>; + status = "disable"; + }; +}; + +&audiobus { + aml_tdma: tdma { + compatible = "amlogic, axg-snd-tdma"; + #sound-dai-cells = <0>; + dai-tdm-lane-slot-mask-in = <1 0>; + dai-tdm-lane-slot-mask-out = <0 1>; + /* select tdm lr/bclk src, see aml_axg_tdm.c */ + dai-tdm-clk-sel = <0>; + clocks = <&clkaudio CLKID_AUDIO_MCLK_A + &clkc CLKID_MPLL0>; + clock-names = "mclk", "clk_srcpll"; + pinctrl-names = "tdm_pins"; + pinctrl-0 = <&tdmin_a &tdmout_a &tdmout_a_data>; + }; + + aml_tdmb: tdmb { + compatible = "amlogic, axg-snd-tdmb"; + #sound-dai-cells = <0>; + dai-tdm-lane-slot-mask-out = <1 0>; + dai-tdm-lane-slot-mask-in = <0 1>; + dai-tdm-clk-sel = <1>; + clocks = <&clkaudio CLKID_AUDIO_MCLK_B + &clkc CLKID_MPLL1>; + clock-names = "mclk", "clk_srcpll"; + pinctrl-names = "tdm_pins"; + pinctrl-0 = <&tdmb_mclk &tdmout_b &tdmin_b>; + }; + + aml_tdmc: tdmc { + compatible = "amlogic, axg-snd-tdmc"; + #sound-dai-cells = <0>; + dai-tdm-lane-slot-mask-out = <1 0>; + dai-tdm-lane-slot-mask-in = <0 1>; + dai-tdm-clk-sel = <2>; + clocks = <&clkaudio CLKID_AUDIO_MCLK_C + &clkc CLKID_MPLL2>; + clock-names = "mclk", "clk_srcpll"; + pinctrl-names = "tdm_pins"; + pinctrl-0 = <&tdmc_mclk &tdmout_c &tdmin_c>; + }; + + aml_spdif: spdif { + compatible = "amlogic, axg-snd-spdif"; + #sound-dai-cells = <0>; + clocks = <&clkc CLKID_MPLL0 + &clkc CLKID_FCLK_DIV4 + &clkaudio CLKID_AUDIO_SPDIFIN + &clkaudio CLKID_AUDIO_SPDIFOUT + &clkaudio CLKID_AUDIO_SPDIFIN_CTRL + &clkaudio CLKID_AUDIO_SPDIFOUT_CTRL>; + clock-names = "sysclk", "fixed_clk", "gate_spdifin", + "gate_spdifout", "clk_spdifin", "clk_spdifout"; + interrupts = + ; + + interrupt-names = "irq_spdifin"; + pinctrl-names = "spdif_pins"; + pinctrl-0 = <&spdifout &spdifin>; + + /* + * whether do asrc for pcm. + * if raw data, asrc is disabled automatically + * 0: "Disable", + * 1: "Enable:32K", + * 2: "Enable:44K", + * 3: "Enable:48K", + * 4: "Enable:88K", + * 5: "Enable:96K", + * 6: "Enable:176K", + * 7: "Enable:192K", + */ + auto_asrc = <0>; + status = "okay"; + }; + + aml_pdm: pdm { + compatible = "amlogic, axg-snd-pdm"; + #sound-dai-cells = <0>; + clocks = <&clkaudio CLKID_AUDIO_PDM + &clkc CLKID_FCLK_DIV3 + &clkc CLKID_MPLL3 + &clkaudio CLKID_AUDIO_PDMIN0 + &clkaudio CLKID_AUDIO_PDMIN1>; + clock-names = "gate", + "sysclk_srcpll", + "dclk_srcpll", + "pdm_dclk", + "pdm_sysclk"; + pinctrl-names = "pdm_pins"; + pinctrl-0 = <&pdmin>; + filter_mode = <1>; /* mode 0~4, defalut:1 */ + status = "okay"; + }; + + aml_loopback: loopback { + compatible = "amlogic, snd-loopback"; + /* + * external loopback clk config + * enable clk while pdm record data + */ + /*clocks = <&clkc CLKID_MPLL1>;*/ + /*clock-names = "datalb_mpll";*/ + /* + * 0: out rate = in data rate; + * 1: out rate = loopback data rate; + */ + lb_mode = <0>; + + /* datain src + * 0: tdmin_a; + * 1: tdmin_b; + * 2: tdmin_c; + * 3: spdifin; + * 4: pdmin; + */ + datain_src = <4>; + datain_chnum = <8>; + datain_chmask = <0x7f>; + + /* tdmin_lb src + * 0: tdmoutA + * 1: tdmoutB + * 2: tdmoutC + * 3: PAD_tdminA + * 4: PAD_tdminB + * 5: PAD_tdminC + */ + /*if tdmin_lb >= 3, use external loopback*/ + datalb_src = <2>; + datalb_chnum = <2>; + /*config which data pin as loopback*/ + /*datalb-lane-mask-in = <0 1>;*/ + datalb_chmask = <0x1>; + + status = "okay"; + }; + + audioresample: resample { + compatible = "amlogic, axg-resample"; + clocks = <&clkc CLKID_MPLL3 + &clkaudio CLKID_AUDIO_MCLK_F + &clkaudio CLKID_AUDIO_RESAMPLE_CTRL>; + clock-names = "resample_pll", "resample_src", "resample_clk"; + /*same with toddr_src + * TDMIN_A, + * TDMIN_B, + * TDMIN_C, + * SPDIFIN, + * PDMIN, + * NONE, + * TDMIN_LB, + * LOOPBACK, + */ + resample_module = <3>; + status = "okay"; + }; +}; /* end of audiobus */ + +&pinctrl_periphs { + tdmout_a: tdmout_a { + mux { + groups = "tdma_sclk", + "tdma_fs"; + function = "tdma_out"; + }; + }; + + tdmout_a_data: tdmout_a_data { + mux { + groups = "tdma_dout1_x15"; + function = "tdma_out"; + }; + }; + + tdmin_a: tdmin_a { + mux { + groups = "tdma_din0"; + function = "tdma_in"; + }; + }; + + tdmb_mclk: tdmb_mclk { + mux { + groups = "mclk_b"; + function = "mclk_b"; + }; + }; + + tdmout_b: tdmout_b { + mux { + groups = "tdmb_sclk", + "tdmb_fs"; + function = "tdmb_out"; + }; + }; + + // tdmin and tdmout are the same pins. can't use at same time + /* + *tdmin_b:tdmin_b { + * mux { + * groups = "tdmb_din0", + * "tdmb_din1", + * "tdmb_din2_a12", + * "tdmb_din3_a13"; + * function = "tdmb_in"; + * }; + *}; + */ + + tdmin_b: tdmin_b { + mux { + groups = "tdmb_din0", + "tdmb_din1"; + function = "tdmb_in"; + }; + }; + + tdmc_mclk: tdmc_mclk { + mux { + groups = "mclk_a"; + function = "mclk_a"; + }; + }; + + tdmout_c:tdmout_c { + mux { + groups = "tdmc_sclk", + "tdmc_fs", + "tdmc_dout0"; + function = "tdmc_out"; + }; + }; + + tdmin_c:tdmin_c { + mux { + groups = "tdmc_din1"; + function = "tdmc_in"; + }; + }; + + spdifout: spidfout { + mux { + groups = "spdif_out_a20"; + function = "spdif_out"; + }; + }; + + spdifin: spidfin { + mux { + groups = "spdif_in_a19"; + function = "spdif_in"; + }; + }; + + pdmin: pdmin { + mux { + groups = "pdm_dclk_a14", + "pdm_din0", + "pdm_din1", + "pdm_din2", + "pdm_din3"; + function = "pdm"; + }; + }; +}; /* end of pinctrl_periphs */ +/* Audio Related End */ + +&aobus{ + uart_AO: serial@3000 { + compatible = "amlogic, meson-uart"; + reg = <0x3000 0x18>; + interrupts = <0 193 1>; + status = "okay"; + clocks = <&xtal>; + clock-names = "clk_uart"; + xtal_tick_en = <1>; + fifosize = < 64 >; + pinctrl-names = "default"; + pinctrl-0 = <&ao_uart_pins>; + support-sysrq = <0>; /* 0 not support , 1 support */ + }; + + uart_AO_B: serial@4000 { + compatible = "amlogic, meson-uart"; + reg = <0x4000 0x18>; + interrupts = <0 197 1>; + status = "disable"; + clocks = <&xtal>; + clock-names = "clk_uart"; + fifosize = < 64 >; + pinctrl-names = "default"; + pinctrl-0 = <&ao_b_uart_pins>; + }; +}; + +&audio_data{ + status = "okay"; +}; diff --git a/arch/arm/boot/dts/amlogic/axg_s420_v03.dts b/arch/arm/boot/dts/amlogic/axg_s420_v03.dts new file mode 100644 index 000000000000..9a308bb12da3 --- /dev/null +++ b/arch/arm/boot/dts/amlogic/axg_s420_v03.dts @@ -0,0 +1,1202 @@ +/* + * arch/arm/boot/dts/amlogic/axg_s420_v03.dts + * + * Copyright (C) 2017 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +/dts-v1/; + +#include "mesonaxg.dtsi" + +/ { + model = "Amlogic"; + amlogic-dt-id = "axg_s420_v03"; + compatible = "amlogic, axg"; + interrupt-parent = <&gic>; + #address-cells = <1>; + #size-cells = <1>; + + aliases { + serial0 = &uart_AO; + serial1 = &uart_A; + }; + + memory@00000000 { + device_type = "memory"; + linux,usable-memory = <0x000000 0x20000000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + /* global autoconfigured region for contiguous allocations */ + ramoops@0x07400000 { + compatible = "ramoops"; + reg = <0x07400000 0x00100000>; + record-size = <0x8000>; + console-size = <0x8000>; + ftrace-size = <0x0>; + pmsg-size = <0x8000>; + }; + + secmon_reserved:linux,secmon { + compatible = "shared-dma-pool"; + reusable; + size = <0x400000>; + alignment = <0x400000>; + alloc-ranges = <0x05000000 0x400000>; + }; + + secos_reserved:linux,secos { + status = "disable"; + compatible = "amlogic, aml_secos_memory"; + reg = <0x05300000 0x2000000>; + no-map; + }; + }; + mtd_nand { + compatible = "amlogic, aml_mtd_nand"; + dev_name = "mtdnand"; + status = "okay"; + reg = <0xFFE07800 0x200>; + interrupts = < 0 34 1 >; + pinctrl-names = "nand_rb_mod","nand_norb_mod", "nand_cs_only"; + pinctrl-0 = <&all_nand_pins>; + pinctrl-1 = <&all_nand_pins>; + pinctrl-2 = <&nand_cs_pins>; + device_id = <0>; + + /*fip/tpl configurations, must be same + * with uboot if bl_mode was set as 1 + * bl_mode: 0 compact mode; 1 descrete mode + * if bl_mode was set as 1, fip configeration will work + */ + bl_mode = <1>; + /*copy count of fip*/ + fip_copies = <4>; + /*size of each fip copy */ + fip_size = <0x200000>; + nand_clk_ctrl = <0xFFE07000>; + plat-names = "bootloader","nandnormal"; + plat-num = <2>; + plat-part-0 = <&bootloader>; + plat-part-1 = <&nandnormal>; + bootloader: bootloader{ + enable_pad ="ce0"; + busy_pad = "rb0"; + timming_mode = "mode5"; + bch_mode = "bch8_1k"; + t_rea = <20>; + t_rhoh = <15>; + chip_num = <1>; + part_num = <0>; + rb_detect = <1>; + }; + nandnormal: nandnormal{ + enable_pad ="ce0"; + busy_pad = "rb0"; + timming_mode = "mode5"; + bch_mode = "bch8_1k"; + plane_mode = "twoplane"; + t_rea = <20>; + t_rhoh = <15>; + chip_num = <2>; + part_num = <3>; + partition = <&nand_partitions>; + rb_detect = <1>; + }; + nand_partitions:nand_partition{ + /* + * if bl_mode is 1, tpl size was generate by + * fip_copies * fip_size which + * will not skip bad when calculating + * the partition size; + * + * if bl_mode is 0, + * tpl partition must be comment out. + */ + tpl{ + offset=<0x0 0x0>; + size=<0x0 0x0>; + }; + misc{ + offset=<0x0 0x0>; + size=<0x0 0x200000>; + }; + logo{ + offset=<0x0 0x0>; + size=<0x0 0x200000>; + }; + recovery{ + offset=<0x0 0x0>; + size=<0x0 0x1000000>; + }; + boot{ + offset=<0x0 0x0>; + size=<0x0 0xF00000>; + }; + system{ + offset=<0x0 0x0>; + size=<0x0 0x11800000>; + }; + data{ + offset=<0xffffffff 0xffffffff>; + size=<0x0 0x0>; + }; + }; + }; + + + aml_sensor0: aml-sensor@0 { + compatible = "amlogic, aml-thermal"; + device_name = "thermal"; + #thermal-sensor-cells = <1>; + cooling_devices { + cpufreq_cool_cluster0 { + min_state = <1000000>; + dyn_coeff = <140>; + cluster_id = <0>; + node_name = "cpufreq_cool0"; + device_type = "cpufreq"; + }; + cpucore_cool_cluster0 { + min_state = <1>; + dyn_coeff = <0>; + cluster_id = <0>; + node_name = "cpucore_cool0"; + device_type = "cpucore"; + }; + }; + cpufreq_cool0:cpufreq_cool0 { + #cooling-cells = <2>; /* min followed by max */ + }; + cpucore_cool0:cpucore_cool0 { + #cooling-cells = <2>; /* min followed by max */ + }; + }; + thermal-zones { + soc_thermal { + polling-delay = <1000>; + polling-delay-passive = <100>; + sustainable-power = <1050>; + + thermal-sensors = <&aml_sensor0 3>; + + trips { + switch_on: trip-point@0 { + temperature = <70000>; + hysteresis = <1000>; + type = "passive"; + }; + control: trip-point@1 { + temperature = <80000>; + hysteresis = <1000>; + type = "passive"; + }; + hot: trip-point@2 { + temperature = <85000>; + hysteresis = <5000>; + type = "hot"; + }; + critical: trip-point@3 { + temperature = <260000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + + cooling-maps { + cpufreq_cooling_map { + trip = <&control>; + cooling-device = <&cpufreq_cool0 0 4>; + contribution = <1024>; + }; + cpucore_cooling_map { + trip = <&control>; + cooling-device = <&cpucore_cool0 0 3>; + contribution = <1024>; + }; + }; + }; + }; + + dwc3: dwc3@ff500000 { + compatible = "synopsys, dwc3"; + status = "okay"; + reg = <0xff500000 0x100000>; + interrupts = <0 30 4>; + usb-phy = <&usb2_phy>, <&usb3_phy>; + cpu-type = "gxl"; + clock-src = "usb3.0"; + clocks = <&clkc CLKID_USB_GENERAL>; + clock-names = "dwc_general"; + }; + + usb2_phy: usb2phy@ffe09000 { + compatible = "amlogic, amlogic-new-usb2"; + status = "okay"; + portnum = <4>; + reg = <0xffe09000 0x80 + 0xffd01008 0x4>; + }; + + usb3_phy: usb3phy@ffe09080 { + compatible = "amlogic, amlogic-new-usb3"; + status = "okay"; + portnum = <0>; + reg = <0xffe09080 0x20>; + interrupts = <0 16 4>; + otg = <1>; + gpio-vbus-power = "GPIOAO_5"; + gpios = <&gpio_ao GPIOAO_5 GPIO_ACTIVE_HIGH>; + }; + + dwc2_a { + compatible = "amlogic, dwc2"; + device_name = "dwc2_a"; + reg = <0xff400000 0x40000>; + status = "okay"; + interrupts = <0 31 4>; + pl-periph-id = <0>; /** lm name */ + clock-src = "usb0"; /** clock src */ + port-id = <0>; /** ref to mach/usb.h */ + port-type = <2>; /** 0: otg, 1: host, 2: slave */ + port-speed = <0>; /** 0: default, high, 1: full */ + port-config = <0>; /** 0: default */ + /*0:default,1:single,2:incr,3:incr4,4:incr8,5:incr16,6:disable*/ + port-dma = <0>; + port-id-mode = <0>; /** 0: hardware, 1: sw_host, 2: sw_slave*/ + usb-fifo = <728>; + cpu-type = "gxl"; + /** 0: normal, 1: otg+dwc3 host only, 2: otg+dwc3 device only*/ + controller-type = <3>; + phy-reg = <0xffe09000>; + phy-reg-size = <0xa0>; + clocks = <&clkc CLKID_USB_GENERAL + &clkc CLKID_USB1_TO_DDR + &clkc CLKID_USB1>; + clock-names = "usb_general", + "usb1", + "usb1_to_ddr"; + }; + + uart_A: serial@ffd24000 { + compatible = "amlogic, meson-uart"; + reg = <0xffd24000 0x18>; + interrupts = <0 26 1>; + status = "okay"; + clocks = <&xtal + &clkc CLKID_UART0>; + clock-names = "clk_uart", + "clk_gate"; + fifosize = < 128 >; + pinctrl-names = "default"; + pinctrl-0 = <&a_uart_pins>; + }; + + uart_B: serial@ffd23000 { + compatible = "amlogic, meson-uart"; + reg = <0xffd23000 0x18>; + interrupts = <0 75 1>; + status = "disable"; + clocks = <&xtal + &clkc CLKID_UART1>; + clock-names = "clk_uart", + "clk_gate"; + fifosize = < 64 >; + pinctrl-names = "default"; + pinctrl-0 = <&b_uart_pins>; + }; + + /* Sound iomap */ + aml_snd_iomap { + compatible = "amlogic, snd-iomap"; + status = "okay"; + #address-cells=<1>; + #size-cells=<1>; + ranges; + pdm_bus { + reg = <0xFF632000 0x2000>; + }; + audiobus_base { + reg = <0xFF642000 0x2000>; + }; + }; + pdm_codec:dummy{ + #sound-dai-cells = <0>; + compatible = "amlogic, pdm_dummy_codec"; + status = "okay"; + }; + dummy_codec:dummy{ + #sound-dai-cells = <0>; + compatible = "amlogic, aml_dummy_codec"; + status = "okay"; + }; + + auge_sound { + compatible = "amlogic, axg-sound-card"; + aml-audio-card,name = "AML-AUGESOUND"; + + aml-audio-card,loopback = <&aml_loopback>; + + aml-audio-card,hp-det-gpio = <&gpio GPIOZ_7 GPIO_ACTIVE_LOW>; + + aml-audio-card,dai-link@0 { + format = "dsp_a"; + mclk-fs = <256>;//512 + continuous-clock; + //bitclock-inversion; + //frame-inversion; + bitclock-master = <&aml_tdma>; + frame-master = <&aml_tdma>; + cpu { + sound-dai = <&aml_tdma>; + dai-tdm-slot-tx-mask = <1>; + dai-tdm-slot-rx-mask = <1>; + dai-tdm-slot-num = <1>; + dai-tdm-slot-width = <32>; + system-clock-frequency = <512000>; + }; + codec { + sound-dai = <&dummy_codec &dummy_codec>; + }; + }; + + aml-audio-card,dai-link@1 { + format = "i2s"; + mclk-fs = <256>; + //continuous-clock; + //bitclock-inversion; + //frame-inversion; + bitclock-master = <&aml_tdmb>; + frame-master = <&aml_tdmb>; + cpu { + sound-dai = <&aml_tdmb>; + dai-tdm-slot-tx-mask = <1 1>; + dai-tdm-slot-rx-mask = <1 1>; + dai-tdm-slot-num = <2>; + dai-tdm-slot-width = <32>; + system-clock-frequency = <12288000>; + }; + codec { + sound-dai = <&tlv320adc3101_32>; + /*&tlv320adc3101_30>;*/ + }; + }; + + aml-audio-card,dai-link@2 { + format = "i2s"; + mclk-fs = <256>; + continuous-clock; + /* tdmb clk using tdmc so no bclk-inv */ + //bitclock-inversion; + //frame-inversion; + bitclock-master = <&aml_tdmc>; + frame-master = <&aml_tdmc>; + cpu { + sound-dai = <&aml_tdmc>; + dai-tdm-slot-tx-mask = <1 1>; + dai-tdm-slot-rx-mask = <1 1>; + dai-tdm-slot-num = <2>; + dai-tdm-slot-width = <32>; + system-clock-frequency = <12288000>; + }; + codec { + sound-dai = <&tas5707_36 &dummy_codec>; + }; + }; + + aml-audio-card,dai-link@3 { + mclk-fs = <256>; + cpu { + sound-dai = <&aml_pdm>; + }; + codec { + /* + *enable external loopback + *and tlv320adc3101 as loopback + */ + /*sound-dai = <&pdm_codec &tlv320adc3101_32>;*/ + /* + * enable internal loopback + * or disable loopback + */ + sound-dai = <&pdm_codec>; + }; + }; + + aml-audio-card,dai-link@4 { + mclk-fs = <128>; + cpu { + sound-dai = <&aml_spdif>; + }; + codec { + sound-dai = <&dummy_codec>; + }; + }; + }; + + bt-dev{ + compatible = "amlogic, bt-dev"; + dev_name = "bt-dev"; + status = "okay"; + gpio_reset = <&gpio GPIOX_21 GPIO_ACTIVE_HIGH>; + }; + + wifi{ + compatible = "amlogic, aml_wifi"; + dev_name = "aml_wifi"; + status = "okay"; + interrupt_pin = <&gpio GPIOX_6 GPIO_ACTIVE_HIGH>; + irq_trigger_type = "GPIO_IRQ_LOW"; + power_on_pin = <&gpio GPIOX_7 GPIO_ACTIVE_HIGH>; + dhd_static_buf; //if use bcm wifi, config dhd_static_buf + pinctrl-names = "default"; + pinctrl-0 = <&wifi_32k_pins>; + pwm_config = <&wifi_pwm_conf>; + }; + + wifi_pwm_conf:wifi_pwm_conf{ + pwm_channel1_conf { + pwms = <&pwm_ab MESON_PWM_0 30040 0>; + duty-cycle = <15020>; + times = <10>; + }; + pwm_channel2_conf { + pwms = <&pwm_ab MESON_PWM_2 30030 0>; + duty-cycle = <15015>; + times = <12>; + }; + }; + sd_emmc_c: emmc@ffe07000 { + status = "disabled"; + compatible = "amlogic, meson-mmc-axg"; + reg = <0xffe07000 0x2000>; + interrupts = <0 218 1>; + pinctrl-names = "emmc_clk_cmd_pins", "emmc_all_pins"; + pinctrl-0 = <&emmc_clk_cmd_pins>; + pinctrl-1 = <&emmc_conf_pull_up &emmc_conf_pull_done>; + clocks = <&clkc CLKID_SD_EMMC_C>, + <&clkc CLKID_SD_EMMC_C_P0_COMP>, + <&clkc CLKID_FCLK_DIV2>, + <&clkc CLKID_FCLK_DIV5>, + <&xtal>; + clock-names = "core", "clkin0", "clkin1", "clkin2", "xtal"; + + bus-width = <8>; + cap-sd-highspeed; + cap-mmc-highspeed; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + + max-frequency = <200000000>; + non-removable; + disable-wp; + emmc { + pinname = "emmc"; + ocr_avail = <0x200080>; /**VDD voltage 3.3 ~ 3.4 */ + caps = "MMC_CAP_8_BIT_DATA", + "MMC_CAP_MMC_HIGHSPEED", + "MMC_CAP_SD_HIGHSPEED", + "MMC_CAP_NONREMOVABLE", + "MMC_CAP_1_8V_DDR", + "MMC_CAP_HW_RESET", + "MMC_CAP_ERASE", + "MMC_CAP_CMD23"; + /*caps2 = "MMC_CAP2_HS200", "MMC_CAP2_HS400";*/ + f_min = <400000>; + f_max = <100000000>; + max_req_size = <0x20000>; /**128KB*/ + gpio_dat3 = <&gpio BOOT_3 GPIO_ACTIVE_HIGH>; + hw_reset = <&gpio BOOT_9 GPIO_ACTIVE_HIGH>; + card_type = <1>; + /* 1:mmc card(include eMMC), + * 2:sd card(include tSD) + */ + }; + }; + + sd_emmc_b:sdio@ffe05000 { + status = "okay"; + compatible = "amlogic, meson-mmc-axg"; + reg = <0xffe05000 0x2000>; + interrupts = <0 217 4>; + pinctrl-names = "sdio_clk_cmd_pins", "sdio_all_pins"; + pinctrl-0 = <&sdio_clk_cmd_pins>; + pinctrl-1 = <&sdio_all_pins>; + clocks = <&clkc CLKID_SD_EMMC_B>, + <&clkc CLKID_SD_EMMC_B_P0_COMP>, + <&clkc CLKID_FCLK_DIV2>; + clock-names = "core", "clkin0", "clkin1"; + + bus-width = <4>; + cap-sd-highspeed; + cap-mmc-highspeed; + max-frequency = <100000000>; + non-removable; + disable-wp; + sdio { + pinname = "sdio"; + ocr_avail = <0x200080>; /**VDD voltage 3.3 ~ 3.4 */ + caps = "MMC_CAP_4_BIT_DATA", + "MMC_CAP_MMC_HIGHSPEED", + "MMC_CAP_SD_HIGHSPEED", + "MMC_CAP_NONREMOVABLE", + "MMC_CAP_UHS_SDR12", + "MMC_CAP_UHS_SDR25", + "MMC_CAP_UHS_SDR50", + "MMC_CAP_UHS_SDR104", + "MMC_PM_KEEP_POWER", + "MMC_CAP_SDIO_IRQ"; + f_min = <400000>; + f_max = <200000000>; + max_req_size = <0x20000>; /**128KB*/ + card_type = <3>; + /* 3:sdio device(ie:sdio-wifi), + * 4:SD combo (IO+mem) card + */ + }; + }; + + adc_keypad { + compatible = "amlogic, adc_keypad"; + status = "okay"; + key_name = "power", "vol-", "vol+", "wifi", "<<", ">>"; + key_num = <6>; + io-channels = <&saradc SARADC_CH0>; + io-channel-names = "key-chan-0"; + key_chan = ; + key_code = <116 114 115 139 105 106>; + key_val = <0 143 266 389 512 635>; //val=voltage/1800mV*1023 + key_tolerance = <40 40 40 40 40 40>; + }; + + partitions: partitions{ + parts = <11>; + part-0 = <&logo>; + part-1 = <&recovery>; + part-2 = <&rsv>; + part-3 = <&tee>; + part-4 = <&crypt>; + part-5 = <&misc>; + part-6 = <&instaboot>; + part-7 = <&boot>; + part-8 = <&system>; + part-9 = <&cache>; + part-10 = <&data>; + + logo:logo{ + pname = "logo"; + size = <0x0 0x2000000>; + mask = <1>; + }; + recovery:recovery{ + pname = "recovery"; + size = <0x0 0x2000000>; + mask = <1>; + }; + rsv:rsv{ + pname = "rsv"; + size = <0x0 0x800000>; + mask = <1>; + }; + tee:tee{ + pname = "tee"; + size = <0x0 0x800000>; + mask = <1>; + }; + crypt:crypt{ + pname = "crypt"; + size = <0x0 0x2000000>; + mask = <1>; + }; + misc:misc{ + pname = "misc"; + size = <0x0 0x2000000>; + mask = <1>; + }; + instaboot:instaboot{ + pname = "instaboot"; + size = <0x0 0x400000>; + mask = <1>; + }; + boot:boot + { + pname = "boot"; + size = <0x0 0x2000000>; + mask = <1>; + }; + system:system + { + pname = "system"; + size = <0x0 0x80000000>; + mask = <1>; + }; + cache:cache + { + pname = "cache"; + size = <0x0 0x20000000>; + mask = <2>; + }; + data:data + { + pname = "data"; + size = <0xffffffff 0xffffffff>; + mask = <4>; + }; + }; + + unifykey{ + compatible = "amlogic, unifykey"; + status = "ok"; + + unifykey-num = <6>; + unifykey-index-0 = <&keysn_0>; + unifykey-index-1 = <&keysn_1>; + unifykey-index-2 = <&keysn_2>; + unifykey-index-3 = <&keysn_3>; + unifykey-index-4 = <&keysn_4>; + unifykey-index-5 = <&keysn_5>; + + keysn_0: key_0{ + key-name = "usid"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_1:key_1{ + key-name = "mac"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_2:key_2{ + key-name = "secure_boot_set"; + key-device = "efuse"; + key-permit = "write"; + }; + keysn_3:key_3{ + key-name = "mac_bt"; + key-device = "normal"; + key-permit = "read","write","del"; + key-type = "mac"; + }; + keysn_4:key_4{ + key-name = "mac_wifi"; + key-device = "normal"; + key-permit = "read","write","del"; + key-type = "mac"; + }; + keysn_5:key_5{ + key-name = "deviceid"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + };//End unifykey +}; /* end of / */ + +&efuse { + status = "ok"; +}; + +&pwm_ab { + status = "okay"; +}; +/* Audio Related start */ +/* for spk board */ +&i2c1 { + status = "okay"; + pinctrl-names="default"; + pinctrl-0=<&b_i2c_master>; + + tlv320adc3101_32: tlv320adc3101_32@30 { + compatible = "ti,tlv320adc3101"; + #sound-dai-cells = <0>; + reg = <0x19>; + differential_pair = <1>; + status = "okay"; + }; + + tas5707_36: tas5707_36@36 { + compatible = "ti,tas5707"; + #sound-dai-cells = <0>; + reg = <0x1b>; + status = "okay"; + reset_pin = <&gpio_ao GPIOAO_4 0>; + }; + + tas5707_3a: tas5707_3a@3a { + compatible = "ti,tas5707"; + #sound-dai-cells = <0>; + reg = <0x1d>; + status = "disable"; + }; +}; + +/* for mic board */ +&i2c_AO { + status = "okay"; + pinctrl-names="default"; + pinctrl-0=<&ao_i2c_master_pin2>; + + aml_pca9557: aml_pca9557@0x1f { + compatible = "aml, ledring"; + reg = <0x1f>; + mode = <0>; /*0: 6-led 1: 4key+2led */ + key_num = <4>; + led_dev_name = "aml_ledring"; + key_dev_name = "aml_pca_key"; + key_name = "mute", "pause", "vol+", "vol-"; + key_value = <200 201 202 203>; + status = "okay"; + }; + + tlv320adc3101_30: tlv320adc3101_30@30 { + compatible = "ti,tlv320adc3101"; + #sound-dai-cells = <0>; + reg = <0x18>; + status = "disable"; + }; + tlv320adc3101_34: tlv320adc3101_34@30 { + compatible = "ti,tlv320adc3101"; + #sound-dai-cells = <0>; + reg = <0x1a>; + status = "disable"; + }; + tlv320adc3101_36: tlv320adc3101_36@30 { + compatible = "ti,tlv320adc3101"; + #sound-dai-cells = <0>; + reg = <0x1b>; + status = "disable"; + }; + es7243_10: es7243_10@10 { + compatible = "MicArray_0"; + #sound-dai-cells = <0>; + reg = <0x10>; + status = "disable"; + }; + es7243_12: es7243_12@12 { + compatible = "MicArray_1"; + #sound-dai-cells = <0>; + reg = <0x12>; + status = "disable"; + }; + es7243_13: es7243_13@13 { + compatible = "MicArray_2"; + #sound-dai-cells = <0>; + reg = <0x13>; + status = "disable"; + }; + is31fl3236a: is31f3236a@0x78 { + compatible = "issi,is31fl3236"; + reg = <0x3c>; + status = "disable"; + led1_r { + label="LED1_R"; + reg_offset = <24>; + }; + led1_g { + label="LED1_G"; + reg_offset = <23>; + }; + led1_b { + label="LED1_B"; + reg_offset = <22>; + }; + led2_r { + label="LED2_R"; + reg_offset = <21>; + }; + led2_g { + label="LED2_G"; + reg_offset = <20>; + }; + led2_b { + label="LED2_B"; + reg_offset = <19>; + }; + led3_r { + label="LED3_R"; + reg_offset = <18>; + }; + led3_g { + label="LED3_G"; + reg_offset = <17>; + }; + led3_b { + label="LED3_B"; + reg_offset = <16>; + }; + led4_r { + label="LED4_R"; + reg_offset = <15>; + }; + led4_g { + label="LED4_G"; + reg_offset = <14>; + }; + led4_b { + label="LED4_B"; + reg_offset = <13>; + }; + led5_r { + label="LED5_R"; + reg_offset = <36>; + }; + led5_g { + label="LED5_G"; + reg_offset = <35>; + }; + led5_b { + label="LED5_B"; + reg_offset = <34>; + }; + led6_r { + label="LED6_R"; + reg_offset = <33>; + }; + led6_g { + label="LED6_G"; + reg_offset = <32>; + }; + led6_b { + label="LED6_B"; + reg_offset = <31>; + }; + led7_r { + label="LED7_R"; + reg_offset = <30>; + }; + led7_g { + label="LED7_G"; + reg_offset = <29>; + }; + led7_b { + label="LED7_B"; + reg_offset = <28>; + }; + led8_r { + label="LED8_R"; + reg_offset = <27>; + }; + led8_g { + label="LED8_G"; + reg_offset = <26>; + }; + led8_b { + label="LED8_B"; + reg_offset = <25>; + }; + }; +}; + +&audiobus { + aml_tdma: tdma { + compatible = "amlogic, axg-snd-tdma"; + #sound-dai-cells = <0>; + dai-tdm-lane-slot-mask-in = <1 0>; + dai-tdm-lane-slot-mask-out = <0 1>; + /* select tdm lr/bclk src, see aml_axg_tdm.c */ + dai-tdm-clk-sel = <0>; + clocks = <&clkaudio CLKID_AUDIO_MCLK_A + &clkc CLKID_MPLL0>; + clock-names = "mclk", "clk_srcpll"; + pinctrl-names = "tdm_pins"; + pinctrl-0 = <&tdmin_a &tdmout_a &tdmout_a_data>; + }; + + aml_tdmb: tdmb { + compatible = "amlogic, axg-snd-tdmb"; + #sound-dai-cells = <0>; + dai-tdm-lane-slot-mask-out = <1 0>; + dai-tdm-lane-slot-mask-in = <0 1>; + dai-tdm-clk-sel = <1>; + clocks = <&clkaudio CLKID_AUDIO_MCLK_B + &clkc CLKID_MPLL1>; + clock-names = "mclk", "clk_srcpll"; + pinctrl-names = "tdm_pins"; + pinctrl-0 = <&tdmb_mclk &tdmout_b &tdmin_b>; + }; + + aml_tdmc: tdmc { + compatible = "amlogic, axg-snd-tdmc"; + #sound-dai-cells = <0>; + dai-tdm-lane-slot-mask-out = <1 0>; + dai-tdm-lane-slot-mask-in = <0 1>; + dai-tdm-clk-sel = <2>; + clocks = <&clkaudio CLKID_AUDIO_MCLK_C + &clkc CLKID_MPLL2>; + clock-names = "mclk", "clk_srcpll"; + pinctrl-names = "tdm_pins"; + pinctrl-0 = <&tdmc_mclk &tdmout_c &tdmin_c>; + }; + + aml_spdif: spdif { + compatible = "amlogic, axg-snd-spdif"; + #sound-dai-cells = <0>; + clocks = <&clkc CLKID_MPLL0 + &clkc CLKID_FCLK_DIV4 + &clkaudio CLKID_AUDIO_SPDIFIN + &clkaudio CLKID_AUDIO_SPDIFOUT + &clkaudio CLKID_AUDIO_SPDIFIN_CTRL + &clkaudio CLKID_AUDIO_SPDIFOUT_CTRL>; + clock-names = "sysclk", "fixed_clk", "gate_spdifin", + "gate_spdifout", "clk_spdifin", "clk_spdifout"; + interrupts = + ; + + interrupt-names = "irq_spdifin"; + pinctrl-names = "spdif_pins"; + pinctrl-0 = <&spdifout &spdifin>; + + /* + * whether do asrc for pcm. + * if raw data, asrc is disabled automatically + * 0: "Disable", + * 1: "Enable:32K", + * 2: "Enable:44K", + * 3: "Enable:48K", + * 4: "Enable:88K", + * 5: "Enable:96K", + * 6: "Enable:176K", + * 7: "Enable:192K", + */ + auto_asrc = <0>; + status = "okay"; + }; + + aml_pdm: pdm { + compatible = "amlogic, axg-snd-pdm"; + #sound-dai-cells = <0>; + clocks = <&clkaudio CLKID_AUDIO_PDM + &clkc CLKID_FCLK_DIV3 + &clkc CLKID_MPLL3 + &clkaudio CLKID_AUDIO_PDMIN0 + &clkaudio CLKID_AUDIO_PDMIN1>; + clock-names = "gate", + "sysclk_srcpll", + "dclk_srcpll", + "pdm_dclk", + "pdm_sysclk"; + pinctrl-names = "pdm_pins"; + pinctrl-0 = <&pdmin>; + filter_mode = <1>; /* mode 0~4, defalut:1 */ + status = "okay"; + }; + + aml_loopback: loopback { + compatible = "amlogic, snd-loopback"; + /* + * external loopback clk config + * enable clk while pdm record data + */ + /*clocks = <&clkc CLKID_MPLL1>;*/ + /*clock-names = "datalb_mpll";*/ + + /* + * 0: out rate = in data rate; + * 1: out rate = loopback data rate; + */ + lb_mode = <0>; + + /* datain src + * 0: tdmin_a; + * 1: tdmin_b; + * 2: tdmin_c; + * 3: spdifin; + * 4: pdmin; + */ + datain_src = <4>; + datain_chnum = <8>; + datain_chmask = <0x7f>; + + /* tdmin_lb src + * 0: tdmoutA + * 1: tdmoutB + * 2: tdmoutC + * 3: PAD_tdminA + * 4: PAD_tdminB + * 5: PAD_tdminC + */ + + /*if tdmin_lb >= 3, use external loopback*/ + datalb_src = <2>; + datalb_chnum = <2>; + /*config which data pin as loopback*/ + /*datalb-lane-mask-in = <0 1>;*/ + datalb_chmask = <0x1>; + + status = "okay"; + }; + + audioresample: resample { + compatible = "amlogic, axg-resample"; + clocks = <&clkc CLKID_MPLL3 + &clkaudio CLKID_AUDIO_MCLK_F + &clkaudio CLKID_AUDIO_RESAMPLE_CTRL>; + clock-names = "resample_pll", "resample_src", "resample_clk"; + /*same with toddr_src + * TDMIN_A, + * TDMIN_B, + * TDMIN_C, + * SPDIFIN, + * PDMIN, + * NONE, + * TDMIN_LB, + * LOOPBACK, + */ + resample_module = <3>; + status = "okay"; + }; +}; /* end of audiobus */ + +&pinctrl_periphs { + tdmout_a: tdmout_a { + mux { + groups = "tdma_sclk", + "tdma_fs"; + function = "tdma_out"; + }; + }; + + tdmout_a_data: tdmout_a_data { + mux { + groups = "tdma_dout1_x15"; + function = "tdma_out"; + }; + }; + + tdmin_a: tdmin_a { + mux { + groups = "tdma_din0"; + function = "tdma_in"; + }; + }; + + tdmb_mclk: tdmb_mclk { + mux { + groups = "mclk_b"; + function = "mclk_b"; + }; + }; + + tdmout_b: tdmout_b { + mux { + groups = "tdmb_sclk", + "tdmb_fs"; + function = "tdmb_out"; + }; + }; + + // tdmin and tdmout are the same pins. can't use at same time + /* + *tdmin_b:tdmin_b { + * mux { + * groups = "tdmb_din0", + * "tdmb_din1", + * "tdmb_din2_a12", + * "tdmb_din3_a13"; + * function = "tdmb_in"; + * }; + *}; + */ + + tdmin_b: tdmin_b { + mux { + groups = "tdmb_din0", + "tdmb_din1"; + function = "tdmb_in"; + }; + }; + + tdmc_mclk: tdmc_mclk { + mux { + groups = "mclk_a"; + function = "mclk_a"; + }; + }; + + tdmout_c:tdmout_c { + mux { + groups = "tdmc_sclk", + "tdmc_fs", + "tdmc_dout0"; + function = "tdmc_out"; + }; + }; + + tdmin_c:tdmin_c { + mux { + groups = "tdmc_din1"; + function = "tdmc_in"; + }; + }; + + spdifout: spidfout { + mux { + groups = "spdif_out_a20"; + function = "spdif_out"; + }; + }; + + spdifin: spidfin { + mux { + groups = "spdif_in_a19"; + function = "spdif_in"; + }; + }; + + pdmin: pdmin { + mux { + groups = "pdm_dclk_a14", + "pdm_din0", + "pdm_din1", + "pdm_din2", + "pdm_din3"; + function = "pdm"; + }; + }; +}; /* end of pinctrl_periphs */ +/* Audio Related End */ + +&aobus{ + uart_AO: serial@3000 { + compatible = "amlogic, meson-uart"; + reg = <0x3000 0x18>; + interrupts = <0 193 1>; + status = "okay"; + clocks = <&xtal>; + clock-names = "clk_uart"; + xtal_tick_en = <1>; + fifosize = < 64 >; + pinctrl-names = "default"; + pinctrl-0 = <&ao_uart_pins>; + support-sysrq = <0>; /* 0 not support , 1 support */ + }; + + uart_AO_B: serial@4000 { + compatible = "amlogic, meson-uart"; + reg = <0x4000 0x18>; + interrupts = <0 197 1>; + status = "disable"; + clocks = <&xtal>; + clock-names = "clk_uart"; + fifosize = < 64 >; + pinctrl-names = "default"; + pinctrl-0 = <&ao_b_uart_pins>; + }; +}; +&audio_data{ + status = "okay"; +}; diff --git a/arch/arm/boot/dts/amlogic/axg_s420_v03gva.dts b/arch/arm/boot/dts/amlogic/axg_s420_v03gva.dts new file mode 100644 index 000000000000..2a72e9d254cf --- /dev/null +++ b/arch/arm/boot/dts/amlogic/axg_s420_v03gva.dts @@ -0,0 +1,1135 @@ +/* + * arch/arm/boot/dts/amlogic/axg_s420_v03gva.dts + * + * Copyright (C) 2017 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +/dts-v1/; + +#include "mesonaxg.dtsi" + +/ { + model = "Amlogic"; + amlogic-dt-id = "axg_s420_v03gva"; + compatible = "amlogic, axg"; + interrupt-parent = <&gic>; + #address-cells = <1>; + #size-cells = <1>; + + aliases { + serial0 = &uart_AO; + serial1 = &uart_A; + }; + + memory@00000000 { + device_type = "memory"; + linux,usable-memory = <0x000000 0x20000000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + /* global autoconfigured region for contiguous allocations */ + ramoops@0x07400000 { + compatible = "ramoops"; + reg = <0x07400000 0x00100000>; + record-size = <0x8000>; + console-size = <0x8000>; + ftrace-size = <0x0>; + pmsg-size = <0x8000>; + }; + + secmon_reserved:linux,secmon { + compatible = "shared-dma-pool"; + reusable; + size = <0x400000>; + alignment = <0x400000>; + alloc-ranges = <0x05000000 0x400000>; + }; + + secos_reserved:linux,secos { + status = "disable"; + compatible = "amlogic, aml_secos_memory"; + reg = <0x05300000 0x2000000>; + no-map; + }; + }; + mtd_nand { + compatible = "amlogic, aml_mtd_nand"; + dev_name = "mtdnand"; + status = "okay"; + reg = <0xFFE07800 0x200>; + interrupts = < 0 34 1 >; + pinctrl-names = "nand_rb_mod","nand_norb_mod", "nand_cs_only"; + pinctrl-0 = <&all_nand_pins>; + pinctrl-1 = <&all_nand_pins>; + pinctrl-2 = <&nand_cs_pins>; + device_id = <0>; + + /*fip/tpl configurations, must be same + * with uboot if bl_mode was set as 1 + * bl_mode: 0 compact mode; 1 descrete mode + * if bl_mode was set as 1, fip configeration will work + */ + bl_mode = <1>; + /*copy count of fip*/ + fip_copies = <4>; + /*size of each fip copy */ + fip_size = <0x200000>; + nand_clk_ctrl = <0xFFE07000>; + plat-names = "bootloader","nandnormal"; + plat-num = <2>; + plat-part-0 = <&bootloader>; + plat-part-1 = <&nandnormal>; + bootloader: bootloader{ + enable_pad ="ce0"; + busy_pad = "rb0"; + timming_mode = "mode5"; + bch_mode = "bch8_1k"; + t_rea = <20>; + t_rhoh = <15>; + chip_num = <1>; + part_num = <0>; + rb_detect = <1>; + }; + nandnormal: nandnormal{ + enable_pad ="ce0"; + busy_pad = "rb0"; + timming_mode = "mode5"; + bch_mode = "bch8_1k"; + plane_mode = "twoplane"; + t_rea = <20>; + t_rhoh = <15>; + chip_num = <2>; + part_num = <3>; + partition = <&nand_partitions>; + rb_detect = <1>; + }; + nand_partitions:nand_partition{ + /* + * if bl_mode is 1, tpl size was generate by + * fip_copies * fip_size which + * will not skip bad when calculating + * the partition size; + * + * if bl_mode is 0, + * tpl partition must be comment out. + */ + tpl{ + offset=<0x0 0x0>; + size=<0x0 0x0>; + }; + recovery{ + offset=<0x0 0x0>; + size=<0x0 0x1000000>; + }; + boot{ + offset=<0x0 0x0>; + size=<0x0 0x1000000>; + }; + system{ + offset=<0x0 0x0>; + size=<0x0 0x11800000>; + }; + factory{ + offset=<0x0 0x0>; + size=<0x0 0x1000000>; + }; + data{ + offset=<0xffffffff 0xffffffff>; + size=<0x0 0x0>; + }; + }; + }; + + + aml_sensor0: aml-sensor@0 { + compatible = "amlogic, aml-thermal"; + device_name = "thermal"; + #thermal-sensor-cells = <1>; + cooling_devices { + cpufreq_cool_cluster0 { + min_state = <1000000>; + dyn_coeff = <140>; + cluster_id = <0>; + node_name = "cpufreq_cool0"; + device_type = "cpufreq"; + }; + cpucore_cool_cluster0 { + min_state = <1>; + dyn_coeff = <0>; + cluster_id = <0>; + node_name = "cpucore_cool0"; + device_type = "cpucore"; + }; + }; + cpufreq_cool0:cpufreq_cool0 { + #cooling-cells = <2>; /* min followed by max */ + }; + cpucore_cool0:cpucore_cool0 { + #cooling-cells = <2>; /* min followed by max */ + }; + }; + thermal-zones { + soc_thermal { + polling-delay = <1000>; + polling-delay-passive = <100>; + sustainable-power = <1050>; + + thermal-sensors = <&aml_sensor0 3>; + + trips { + switch_on: trip-point@0 { + temperature = <70000>; + hysteresis = <1000>; + type = "passive"; + }; + control: trip-point@1 { + temperature = <80000>; + hysteresis = <1000>; + type = "passive"; + }; + hot: trip-point@2 { + temperature = <85000>; + hysteresis = <5000>; + type = "hot"; + }; + critical: trip-point@3 { + temperature = <260000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + + cooling-maps { + cpufreq_cooling_map { + trip = <&control>; + cooling-device = <&cpufreq_cool0 0 4>; + contribution = <1024>; + }; + cpucore_cooling_map { + trip = <&control>; + cooling-device = <&cpucore_cool0 0 3>; + contribution = <1024>; + }; + }; + }; + }; + + dwc3: dwc3@ff500000 { + compatible = "synopsys, dwc3"; + status = "okay"; + reg = <0xff500000 0x100000>; + interrupts = <0 30 4>; + usb-phy = <&usb2_phy>, <&usb3_phy>; + cpu-type = "gxl"; + clock-src = "usb3.0"; + clocks = <&clkc CLKID_USB_GENERAL>; + clock-names = "dwc_general"; + }; + + usb2_phy: usb2phy@ffe09000 { + compatible = "amlogic, amlogic-new-usb2"; + status = "okay"; + portnum = <4>; + reg = <0xffe09000 0x80 + 0xffd01008 0x4>; + }; + + usb3_phy: usb3phy@ffe09080 { + compatible = "amlogic, amlogic-new-usb3"; + status = "okay"; + portnum = <0>; + reg = <0xffe09080 0x20>; + interrupts = <0 16 4>; + otg = <1>; + gpio-vbus-power = "GPIOAO_5"; + gpios = <&gpio_ao GPIOAO_5 GPIO_ACTIVE_HIGH>; + }; + + dwc2_a { + compatible = "amlogic, dwc2"; + device_name = "dwc2_a"; + reg = <0xff400000 0x40000>; + status = "okay"; + interrupts = <0 31 4>; + pl-periph-id = <0>; /** lm name */ + clock-src = "usb0"; /** clock src */ + port-id = <0>; /** ref to mach/usb.h */ + port-type = <2>; /** 0: otg, 1: host, 2: slave */ + port-speed = <0>; /** 0: default, high, 1: full */ + port-config = <0>; /** 0: default */ + /*0:default,1:single,2:incr,3:incr4,4:incr8,5:incr16,6:disable*/ + port-dma = <0>; + port-id-mode = <0>; /** 0: hardware, 1: sw_host, 2: sw_slave*/ + usb-fifo = <728>; + cpu-type = "gxl"; + /** 0: normal, 1: otg+dwc3 host only, 2: otg+dwc3 device only*/ + controller-type = <3>; + phy-reg = <0xffe09000>; + phy-reg-size = <0xa0>; + clocks = <&clkc CLKID_USB_GENERAL + &clkc CLKID_USB1_TO_DDR + &clkc CLKID_USB1>; + clock-names = "usb_general", + "usb1", + "usb1_to_ddr"; + }; + + uart_A: serial@ffd24000 { + compatible = "amlogic, meson-uart"; + reg = <0xffd24000 0x18>; + interrupts = <0 26 1>; + status = "okay"; + clocks = <&xtal + &clkc CLKID_UART0>; + clock-names = "clk_uart", + "clk_gate"; + fifosize = < 128 >; + pinctrl-names = "default"; + pinctrl-0 = <&a_uart_pins>; + }; + + uart_B: serial@ffd23000 { + compatible = "amlogic, meson-uart"; + reg = <0xffd23000 0x18>; + interrupts = <0 75 1>; + status = "disable"; + clocks = <&xtal + &clkc CLKID_UART1>; + clock-names = "clk_uart", + "clk_gate"; + fifosize = < 64 >; + pinctrl-names = "default"; + pinctrl-0 = <&b_uart_pins>; + }; + + meson-irblaster { + compatible = "amlogic, am_irblaster"; + dev_name = "meson-irblaster"; + status = "disable"; + pinctrl-names = "default"; + pinctrl-0 = <&irblaster_pins>; + }; + + /* Sound iomap */ + aml_snd_iomap { + compatible = "amlogic, snd-iomap"; + status = "okay"; + #address-cells=<1>; + #size-cells=<1>; + ranges; + pdm_bus { + reg = <0xFF632000 0x2000>; + }; + audiobus_base { + reg = <0xFF642000 0x2000>; + }; + }; + pdm_codec:dummy{ + #sound-dai-cells = <0>; + compatible = "amlogic, pdm_dummy_codec"; + status = "okay"; + }; + dummy_codec:dummy{ + #sound-dai-cells = <0>; + compatible = "amlogic, aml_dummy_codec"; + status = "okay"; + }; + + auge_sound { + compatible = "amlogic, axg-sound-card"; + aml-audio-card,name = "AML-AUGESOUND"; + + aml-audio-card,loopback = <&aml_loopback>; + + aml-audio-card,hp-det-gpio = <&gpio GPIOZ_7 GPIO_ACTIVE_LOW>; + + aml-audio-card,dai-link@0 { + format = "dsp_a"; + mclk-fs = <256>;//512 + continuous-clock; + //bitclock-inversion; + //frame-inversion; + bitclock-master = <&aml_tdma>; + frame-master = <&aml_tdma>; + cpu { + sound-dai = <&aml_tdma>; + dai-tdm-slot-tx-mask = <1>; + dai-tdm-slot-rx-mask = <1>; + dai-tdm-slot-num = <1>; + dai-tdm-slot-width = <32>; + system-clock-frequency = <512000>; + }; + codec { + sound-dai = <&dummy_codec &dummy_codec>; + }; + }; + + aml-audio-card,dai-link@1 { + format = "i2s"; + mclk-fs = <256>; + //continuous-clock; + //bitclock-inversion; + //frame-inversion; + bitclock-master = <&aml_tdmb>; + frame-master = <&aml_tdmb>; + cpu { + sound-dai = <&aml_tdmb>; + dai-tdm-slot-tx-mask = <1 1>; + dai-tdm-slot-rx-mask = <1 1>; + dai-tdm-slot-num = <2>; + dai-tdm-slot-width = <32>; + system-clock-frequency = <12288000>; + }; + codec { + sound-dai = <&tlv320adc3101_32>; + /*&tlv320adc3101_30>;*/ + }; + }; + + aml-audio-card,dai-link@2 { + format = "i2s"; + mclk-fs = <256>; + continuous-clock; + /* tdmb clk using tdmc so no bclk-inv */ + //bitclock-inversion; + //frame-inversion; + bitclock-master = <&aml_tdmc>; + frame-master = <&aml_tdmc>; + cpu { + sound-dai = <&aml_tdmc>; + dai-tdm-slot-tx-mask = <1 1>; + dai-tdm-slot-rx-mask = <1 1>; + dai-tdm-slot-num = <2>; + dai-tdm-slot-width = <32>; + system-clock-frequency = <12288000>; + }; + codec { + sound-dai = <&tas5707_36 &dummy_codec>; + }; + }; + + aml-audio-card,dai-link@3 { + mclk-fs = <256>; + cpu { + sound-dai = <&aml_pdm>; + }; + codec { + /* + *enable external loopback + *and tlv320adc3101 as loopback + */ + /*sound-dai = <&pdm_codec &tlv320adc3101_32>;*/ + /* + * enable internal loopback + * or disable loopback + */ + sound-dai = <&pdm_codec>; + }; + }; + + /*aml-audio-card,dai-link@4 { + * mclk-fs = <128>; + * cpu { + * sound-dai = <&aml_spdif>; + * }; + * codec { + * sound-dai = <&dummy_codec>; + * }; + *}; + */ + }; + + bt-dev{ + compatible = "amlogic, bt-dev"; + dev_name = "bt-dev"; + status = "okay"; + gpio_reset = <&gpio GPIOX_21 GPIO_ACTIVE_HIGH>; + }; + + wifi{ + compatible = "amlogic, aml_wifi"; + dev_name = "aml_wifi"; + status = "okay"; + interrupt_pin = <&gpio GPIOX_6 GPIO_ACTIVE_HIGH>; + irq_trigger_type = "GPIO_IRQ_LOW"; + power_on_pin = <&gpio GPIOX_7 GPIO_ACTIVE_HIGH>; + dhd_static_buf; //if use bcm wifi, config dhd_static_buf + pinctrl-names = "default"; + pinctrl-0 = <&wifi_32k_pins>; + pwm_config = <&wifi_pwm_conf>; + }; + + wifi_pwm_conf:wifi_pwm_conf{ + pwm_channel1_conf { + pwms = <&pwm_ab MESON_PWM_0 30040 0>; + duty-cycle = <15020>; + times = <10>; + }; + pwm_channel2_conf { + pwms = <&pwm_ab MESON_PWM_2 30030 0>; + duty-cycle = <15015>; + times = <12>; + }; + }; + sd_emmc_c: emmc@ffe07000 { + status = "disabled"; + compatible = "amlogic, meson-mmc-axg"; + reg = <0xffe07000 0x2000>; + interrupts = <0 218 1>; + pinctrl-names = "emmc_clk_cmd_pins", "emmc_all_pins"; + pinctrl-0 = <&emmc_clk_cmd_pins>; + pinctrl-1 = <&emmc_conf_pull_up &emmc_conf_pull_done>; + clocks = <&clkc CLKID_SD_EMMC_C>, + <&clkc CLKID_SD_EMMC_C_P0_COMP>, + <&clkc CLKID_FCLK_DIV2>, + <&clkc CLKID_FCLK_DIV5>, + <&xtal>; + clock-names = "core", "clkin0", "clkin1", "clkin2", "xtal"; + + bus-width = <8>; + cap-sd-highspeed; + cap-mmc-highspeed; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + + max-frequency = <200000000>; + non-removable; + disable-wp; + emmc { + pinname = "emmc"; + ocr_avail = <0x200080>; /**VDD voltage 3.3 ~ 3.4 */ + caps = "MMC_CAP_8_BIT_DATA", + "MMC_CAP_MMC_HIGHSPEED", + "MMC_CAP_SD_HIGHSPEED", + "MMC_CAP_NONREMOVABLE", + "MMC_CAP_1_8V_DDR", + "MMC_CAP_HW_RESET", + "MMC_CAP_ERASE", + "MMC_CAP_CMD23"; + /*caps2 = "MMC_CAP2_HS200", "MMC_CAP2_HS400";*/ + f_min = <400000>; + f_max = <100000000>; + max_req_size = <0x20000>; /**128KB*/ + gpio_dat3 = <&gpio BOOT_3 GPIO_ACTIVE_HIGH>; + hw_reset = <&gpio BOOT_9 GPIO_ACTIVE_HIGH>; + card_type = <1>; + /* 1:mmc card(include eMMC), + * 2:sd card(include tSD) + */ + }; + }; + + sd_emmc_b:sdio@ffe05000 { + status = "okay"; + compatible = "amlogic, meson-mmc-axg"; + reg = <0xffe05000 0x2000>; + interrupts = <0 217 4>; + pinctrl-names = "sdio_clk_cmd_pins", "sdio_all_pins"; + pinctrl-0 = <&sdio_clk_cmd_pins>; + pinctrl-1 = <&sdio_all_pins>; + clocks = <&clkc CLKID_SD_EMMC_B>, + <&clkc CLKID_SD_EMMC_B_P0_COMP>, + <&clkc CLKID_FCLK_DIV2>; + clock-names = "core", "clkin0", "clkin1"; + + bus-width = <4>; + cap-sd-highspeed; + cap-mmc-highspeed; + max-frequency = <100000000>; + non-removable; + disable-wp; + sdio { + pinname = "sdio"; + ocr_avail = <0x200080>; /**VDD voltage 3.3 ~ 3.4 */ + caps = "MMC_CAP_4_BIT_DATA", + "MMC_CAP_MMC_HIGHSPEED", + "MMC_CAP_SD_HIGHSPEED", + "MMC_CAP_NONREMOVABLE", + "MMC_CAP_UHS_SDR12", + "MMC_CAP_UHS_SDR25", + "MMC_CAP_UHS_SDR50", + "MMC_CAP_UHS_SDR104", + "MMC_PM_KEEP_POWER", + "MMC_CAP_SDIO_IRQ"; + f_min = <400000>; + f_max = <200000000>; + max_req_size = <0x20000>; /**128KB*/ + card_type = <3>; + /* 3:sdio device(ie:sdio-wifi), + * 4:SD combo (IO+mem) card + */ + }; + }; + + adc_keypad { + compatible = "amlogic, adc_keypad"; + status = "okay"; + key_name = "power", "vol-", "vol+", "wifi", "<<", ">>"; + key_num = <6>; + io-channels = <&saradc SARADC_CH0>; + io-channel-names = "key-chan-0"; + key_chan = ; + key_code = <116 114 115 139 105 106>; + key_val = <0 143 266 389 512 635>; //val=voltage/1800mV*1023 + key_tolerance = <40 40 40 40 40 40>; + }; + + partitions: partitions{ + parts = <11>; + part-0 = <&logo>; + part-1 = <&recovery>; + part-2 = <&rsv>; + part-3 = <&tee>; + part-4 = <&crypt>; + part-5 = <&misc>; + part-6 = <&instaboot>; + part-7 = <&boot>; + part-8 = <&system>; + part-9 = <&cache>; + part-10 = <&data>; + + logo:logo{ + pname = "logo"; + size = <0x0 0x2000000>; + mask = <1>; + }; + recovery:recovery{ + pname = "recovery"; + size = <0x0 0x2000000>; + mask = <1>; + }; + rsv:rsv{ + pname = "rsv"; + size = <0x0 0x800000>; + mask = <1>; + }; + tee:tee{ + pname = "tee"; + size = <0x0 0x800000>; + mask = <1>; + }; + crypt:crypt{ + pname = "crypt"; + size = <0x0 0x2000000>; + mask = <1>; + }; + misc:misc{ + pname = "misc"; + size = <0x0 0x2000000>; + mask = <1>; + }; + instaboot:instaboot{ + pname = "instaboot"; + size = <0x0 0x400000>; + mask = <1>; + }; + boot:boot + { + pname = "boot"; + size = <0x0 0x2000000>; + mask = <1>; + }; + system:system + { + pname = "system"; + size = <0x0 0x80000000>; + mask = <1>; + }; + cache:cache + { + pname = "cache"; + size = <0x0 0x20000000>; + mask = <2>; + }; + data:data + { + pname = "data"; + size = <0xffffffff 0xffffffff>; + mask = <4>; + }; + }; + + unifykey{ + compatible = "amlogic, unifykey"; + status = "ok"; + + unifykey-num = <6>; + unifykey-index-0 = <&keysn_0>; + unifykey-index-1 = <&keysn_1>; + unifykey-index-2 = <&keysn_2>; + unifykey-index-3 = <&keysn_3>; + unifykey-index-4 = <&keysn_4>; + unifykey-index-5 = <&keysn_5>; + + keysn_0: key_0{ + key-name = "usid"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_1:key_1{ + key-name = "mac"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_2:key_2{ + key-name = "secure_boot_set"; + key-device = "efuse"; + key-permit = "write"; + }; + keysn_3:key_3{ + key-name = "mac_bt"; + key-device = "normal"; + key-permit = "read","write","del"; + key-type = "mac"; + }; + keysn_4:key_4{ + key-name = "mac_wifi"; + key-device = "normal"; + key-permit = "read","write","del"; + key-type = "mac"; + }; + keysn_5:key_5{ + key-name = "deviceid"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + };//End unifykey + audio_data: audio_data { + compatible = "amlogic, audio_data"; + query_licence_cmd = <0x82000050>; + status = "okay"; + }; +}; /* end of / */ + +&efuse { + status = "ok"; +}; + +&pwm_ab { + status = "okay"; +}; +/* Audio Related start */ +/* for spk board */ +&i2c1 { + status = "okay"; + pinctrl-names="default"; + pinctrl-0=<&b_i2c_master>; + + tlv320adc3101_32: tlv320adc3101_32@30 { + compatible = "ti,tlv320adc3101"; + #sound-dai-cells = <0>; + reg = <0x19>; + differential_pair = <1>; + status = "okay"; + }; + + tas5707_36: tas5707_36@36 { + compatible = "ti,tas5707"; + #sound-dai-cells = <0>; + reg = <0x1b>; + status = "okay"; + reset_pin = <&gpio_ao GPIOAO_4 0>; + }; + + tas5707_3a: tas5707_3a@3a { + compatible = "ti,tas5707"; + #sound-dai-cells = <0>; + reg = <0x1d>; + status = "disable"; + }; +}; + +/* for mic board */ +&i2c_AO { + status = "okay"; + pinctrl-names="default"; + pinctrl-0=<&ao_i2c_master_pin2>; + + aml_pca9557: aml_pca9557@0x1f { + compatible = "amlogic,pca9557_keypad"; + reg = <0x1f>; + key_num = <4>; + key_name = "fdr", "hotword", "pause", "mute"; + key_value = <106 105 139 116>; + key_index_mask = <0x4 0x8 0x10 0x20>; + key_input_mask = <0x3C>; + status = "okay"; + }; + + tlv320adc3101_30: tlv320adc3101_30@30 { + compatible = "ti,tlv320adc3101"; + #sound-dai-cells = <0>; + reg = <0x18>; + status = "disable"; + }; + tlv320adc3101_34: tlv320adc3101_34@30 { + compatible = "ti,tlv320adc3101"; + #sound-dai-cells = <0>; + reg = <0x1a>; + status = "disable"; + }; + tlv320adc3101_36: tlv320adc3101_36@30 { + compatible = "ti,tlv320adc3101"; + #sound-dai-cells = <0>; + reg = <0x1b>; + status = "disable"; + }; + es7243_10: es7243_10@10 { + compatible = "MicArray_0"; + #sound-dai-cells = <0>; + reg = <0x10>; + status = "disable"; + }; + es7243_12: es7243_12@12 { + compatible = "MicArray_1"; + #sound-dai-cells = <0>; + reg = <0x12>; + status = "disable"; + }; + es7243_13: es7243_13@13 { + compatible = "MicArray_2"; + #sound-dai-cells = <0>; + reg = <0x13>; + status = "disable"; + }; + cy8c4014_08: cy8c4014_08@08 { + compatible = "cy8c4014"; + #sound-dai-cells = <0>; + reg = <0x8>; + status = "okay"; + }; + is31fl3236a: is31f3236a@0x78 { + compatible = "issi,is31fl3236,gva"; + reg = <0x3c>; + status = "okay"; + led1_b { + label="LED1_B"; + reg_offset = <1>; + }; + led1_g { + label="LED1_G"; + reg_offset = <2>; + }; + led1_r { + label="LED1_R"; + reg_offset = <3>; + }; + led2_b { + label="LED2_B"; + reg_offset = <4>; + }; + led2_g { + label="LED2_G"; + reg_offset = <5>; + }; + led2_r { + label="LED2_R"; + reg_offset = <6>; + }; + led3_b { + label="LED3_B"; + reg_offset = <7>; + }; + led3_g { + label="LED3_G"; + reg_offset = <8>; + }; + led3_r { + label="LED3_R"; + reg_offset = <9>; + }; + led4_b { + label="LED4_B"; + reg_offset = <10>; + }; + led4_g { + label="LED4_G"; + reg_offset = <11>; + }; + led4_r { + label="LED4_R"; + reg_offset = <12>; + }; + }; +}; + +&audiobus { + aml_tdma: tdma { + compatible = "amlogic, axg-snd-tdma"; + #sound-dai-cells = <0>; + dai-tdm-lane-slot-mask-in = <1 0>; + dai-tdm-lane-slot-mask-out = <0 1>; + /* select tdm lr/bclk src, see aml_axg_tdm.c */ + dai-tdm-clk-sel = <0>; + clocks = <&clkaudio CLKID_AUDIO_MCLK_A + &clkc CLKID_MPLL0>; + clock-names = "mclk", "clk_srcpll"; + pinctrl-names = "tdm_pins"; + pinctrl-0 = <&tdmin_a &tdmout_a &tdmout_a_data>; + }; + + aml_tdmb: tdmb { + compatible = "amlogic, axg-snd-tdmb"; + #sound-dai-cells = <0>; + dai-tdm-lane-slot-mask-out = <1 0>; + dai-tdm-lane-slot-mask-in = <0 1>; + dai-tdm-clk-sel = <1>; + clocks = <&clkaudio CLKID_AUDIO_MCLK_B + &clkc CLKID_MPLL1>; + clock-names = "mclk", "clk_srcpll"; + pinctrl-names = "tdm_pins"; + pinctrl-0 = <&tdmb_mclk &tdmout_b &tdmin_b>; + }; + + aml_tdmc: tdmc { + compatible = "amlogic, axg-snd-tdmc"; + #sound-dai-cells = <0>; + dai-tdm-lane-slot-mask-out = <1 0>; + dai-tdm-lane-slot-mask-in = <0 1>; + dai-tdm-clk-sel = <2>; + clocks = <&clkaudio CLKID_AUDIO_MCLK_C + &clkc CLKID_MPLL2>; + clock-names = "mclk", "clk_srcpll"; + pinctrl-names = "tdm_pins"; + pinctrl-0 = <&tdmc_mclk &tdmout_c &tdmin_c>; + }; + + aml_spdif: spdif { + compatible = "amlogic, axg-snd-spdif"; + #sound-dai-cells = <0>; + clocks = <&clkc CLKID_MPLL0 + &clkc CLKID_FCLK_DIV4 + &clkaudio CLKID_AUDIO_SPDIFIN + &clkaudio CLKID_AUDIO_SPDIFOUT + &clkaudio CLKID_AUDIO_SPDIFIN_CTRL + &clkaudio CLKID_AUDIO_SPDIFOUT_CTRL>; + clock-names = "sysclk", "fixed_clk", "gate_spdifin", + "gate_spdifout", "clk_spdifin", "clk_spdifout"; + interrupts = + ; + + interrupt-names = "irq_spdifin"; + pinctrl-names = "spdif_pins"; + pinctrl-0 = <&spdifout &spdifin>; + status = "okay"; + }; + + aml_pdm: pdm { + compatible = "amlogic, axg-snd-pdm"; + #sound-dai-cells = <0>; + clocks = <&clkaudio CLKID_AUDIO_PDM + &clkc CLKID_FCLK_DIV3 + &clkc CLKID_MPLL3 + &clkaudio CLKID_AUDIO_PDMIN0 + &clkaudio CLKID_AUDIO_PDMIN1>; + clock-names = "gate", + "sysclk_srcpll", + "dclk_srcpll", + "pdm_dclk", + "pdm_sysclk"; + pinctrl-names = "pdm_pins"; + pinctrl-0 = <&pdmin>; + filter_mode = <1>; /* mode 0~4, defalut:1 */ + status = "okay"; + }; + + aml_loopback: loopback { + compatible = "amlogic, snd-loopback"; + /* + * external loopback clk config + * enable clk while pdm record data + */ + /*clocks = <&clkc CLKID_MPLL1>;*/ + /*clock-names = "datalb_mpll";*/ + + /* + * 0: out rate = in data rate; + * 1: out rate = loopback data rate; + */ + lb_mode = <0>; + + /* datain src + * 0: tdmin_a; + * 1: tdmin_b; + * 2: tdmin_c; + * 3: spdifin; + * 4: pdmin; + */ + datain_src = <4>; + datain_chnum = <4>; + datain_chmask = <0x3>; + + /* tdmin_lb src + * 0: tdmoutA + * 1: tdmoutB + * 2: tdmoutC + * 3: PAD_tdminA + * 4: PAD_tdminB + * 5: PAD_tdminC + */ + + /*if tdmin_lb >= 3, use external loopback*/ + datalb_src = <2>; + datalb_chnum = <2>; + /*config which data pin as loopback*/ + /*datalb-lane-mask-in = <0 1>;*/ + datalb_chmask = <0x3>; + + status = "okay"; + }; +}; /* end of audiobus */ + +&pinctrl_periphs { + tdmout_a: tdmout_a { + mux { + groups = "tdma_sclk", + "tdma_fs"; + function = "tdma_out"; + }; + }; + + tdmout_a_data: tdmout_a_data { + mux { + groups = "tdma_dout1_x15"; + function = "tdma_out"; + }; + }; + + tdmin_a: tdmin_a { + mux { + groups = "tdma_din0"; + function = "tdma_in"; + }; + }; + + tdmb_mclk: tdmb_mclk { + mux { + groups = "mclk_b"; + function = "mclk_b"; + }; + }; + + tdmout_b: tdmout_b { + mux { + groups = "tdmb_sclk", + "tdmb_fs"; + function = "tdmb_out"; + }; + }; + + // tdmin and tdmout are the same pins. can't use at same time + /* + *tdmin_b:tdmin_b { + * mux { + * groups = "tdmb_din0", + * "tdmb_din1", + * "tdmb_din2_a12", + * "tdmb_din3_a13"; + * function = "tdmb_in"; + * }; + *}; + */ + + tdmin_b: tdmin_b { + mux { + groups = "tdmb_din0", + "tdmb_din1"; + function = "tdmb_in"; + }; + }; + + tdmc_mclk: tdmc_mclk { + mux { + groups = "mclk_a"; + function = "mclk_a"; + }; + }; + + tdmout_c:tdmout_c { + mux { + groups = "tdmc_sclk", + "tdmc_fs", + "tdmc_dout0"; + function = "tdmc_out"; + }; + }; + + tdmin_c:tdmin_c { + mux { + groups = "tdmc_din1"; + function = "tdmc_in"; + }; + }; + + spdifout: spidfout { + mux { + groups = "spdif_out_a20"; + function = "spdif_out"; + }; + }; + + spdifin: spidfin { + mux { + groups = "spdif_in_a19"; + function = "spdif_in"; + }; + }; + + pdmin: pdmin { + mux { + groups = "pdm_dclk_a14", + "pdm_din0", + "pdm_din1", + "pdm_din2", + "pdm_din3"; + function = "pdm"; + }; + }; +}; /* end of pinctrl_periphs */ +/* Audio Related End */ + +&aobus{ + uart_AO: serial@3000 { + compatible = "amlogic, meson-uart"; + reg = <0x3000 0x18>; + interrupts = <0 193 1>; + status = "okay"; + clocks = <&xtal>; + clock-names = "clk_uart"; + xtal_tick_en = <1>; + fifosize = < 64 >; + pinctrl-names = "default"; + pinctrl-0 = <&ao_uart_pins>; + support-sysrq = <0>; /* 0 not support , 1 support */ + }; + + uart_AO_B: serial@4000 { + compatible = "amlogic, meson-uart"; + reg = <0x4000 0x18>; + interrupts = <0 197 1>; + status = "disable"; + clocks = <&xtal>; + clock-names = "clk_uart"; + fifosize = < 64 >; + pinctrl-names = "default"; + pinctrl-0 = <&ao_b_uart_pins>; + }; +}; +&audio_data{ + status = "okay"; +}; diff --git a/arch/arm/boot/dts/amlogic/firmware_ab.dtsi b/arch/arm/boot/dts/amlogic/firmware_ab.dtsi new file mode 100644 index 000000000000..3b2d7d97d6d6 --- /dev/null +++ b/arch/arm/boot/dts/amlogic/firmware_ab.dtsi @@ -0,0 +1,54 @@ +/* + * arch/arm/boot/dts/amlogic/firmware_ab.dtsi + * + * Copyright (C) 2017 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +/ { +firmware { + android { + compatible = "android,firmware"; + vbmeta { + compatible = "android,vbmeta"; + parts = "vbmeta,boot,system,vendor"; + by_name_prefix="/dev/block"; + }; + fstab { + compatible = "android,fstab"; + + vendor { + compatible = "android,vendor"; + dev = "/dev/block/vendor"; + type = "ext4"; + mnt_flags = "ro,barrier=1,inode_readahead_blks=8"; + fsmgr_flags = "wait,slotselect"; + }; + product { + compatible = "android,product"; + dev = "/dev/block/product"; + type = "ext4"; + mnt_flags = "ro,barrier=1,inode_readahead_blks=8"; + fsmgr_flags = "wait,slotselect"; + }; + odm { + compatible = "android,odm"; + dev = "/dev/block/odm"; + type = "ext4"; + mnt_flags = "ro,barrier=1,inode_readahead_blks=8"; + fsmgr_flags = "wait,slotselect"; + }; + }; + }; +}; +};/* end of / */ diff --git a/arch/arm/boot/dts/amlogic/firmware_avb_ab.dtsi b/arch/arm/boot/dts/amlogic/firmware_avb_ab.dtsi new file mode 100644 index 000000000000..d1154cca4a93 --- /dev/null +++ b/arch/arm/boot/dts/amlogic/firmware_avb_ab.dtsi @@ -0,0 +1,54 @@ +/* + * arch/arm/boot/dts/amlogic/firmware_avb_ab.dtsi + * + * Copyright (C) 2017 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +/ { +firmware { + android { + compatible = "android,firmware"; + vbmeta { + compatible = "android,vbmeta"; + parts = "vbmeta,boot,system,vendor"; + by_name_prefix="/dev/block"; + }; + fstab { + compatible = "android,fstab"; + + vendor { + compatible = "android,vendor"; + dev = "/dev/block/vendor"; + type = "ext4"; + mnt_flags = "ro,barrier=1,inode_readahead_blks=8"; + fsmgr_flags = "wait,slotselect,avb"; + }; + product { + compatible = "android,product"; + dev = "/dev/block/product"; + type = "ext4"; + mnt_flags = "ro,barrier=1,inode_readahead_blks=8"; + fsmgr_flags = "wait,slotselect"; + }; + odm { + compatible = "android,odm"; + dev = "/dev/block/odm"; + type = "ext4"; + mnt_flags = "ro,barrier=1,inode_readahead_blks=8"; + fsmgr_flags = "wait,slotselect"; + }; + }; + }; +}; +};/* end of / */ diff --git a/arch/arm/boot/dts/amlogic/g12a_pxp.dts b/arch/arm/boot/dts/amlogic/g12a_pxp.dts new file mode 100644 index 000000000000..28c98cb1b4c1 --- /dev/null +++ b/arch/arm/boot/dts/amlogic/g12a_pxp.dts @@ -0,0 +1,729 @@ +/* + * arch/arm/boot/dts/amlogic/g12a_pxp.dts + * + * Copyright (C) 2017 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +/dts-v1/; + +#include "mesong12a.dtsi" + +/ { + model = "Amlogic"; + compatible = "amlogic, g12a"; + interrupt-parent = <&gic>; + #address-cells = <1>; + #size-cells = <1>; + + aliases { + serial0 = &uart_AO; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c_AO; + }; + + memory@00000000 { + device_type = "memory"; + linux,usable-memory = <0x100000 0x3ff00000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + /* global autoconfigured region for contiguous allocations */ + secmon_reserved:linux,secmon { + compatible = "shared-dma-pool"; + reusable; + size = <0x400000>; + alignment = <0x400000>; + alloc-ranges = <0x05000000 0x400000>; + }; + + secos_reserved:linux,secos { + status = "disable"; + compatible = "amlogic, aml_secos_memory"; + reg = <0x05300000 0x2000000>; + no-map; + }; + logo_reserved:linux,meson-fb { + compatible = "shared-dma-pool"; + reusable; + size = <0x800000>; + alignment = <0x400000>; + alloc-ranges = <0x3f800000 0x800000>; + }; + ion_cma_reserved:linux,ion-dev { + compatible = "shared-dma-pool"; + reusable; + size = <0x8000000>; + alignment = <0x400000>; + }; + + //di_reserved:linux,di { + //compatible = "amlogic, di-mem"; + /* buffer_size = 3621952(yuv422 8bit) */ + /* 4179008(yuv422 10bit full pack mode) */ + /** 10x3621952=34.6M(0x23) support 8bit **/ + /** 10x4736064=45.2M(0x2e) support 12bit **/ + /** 10x4179008=40M(0x28) support 10bit **/ + //size = <0x2800000>; + //no-map; + //}; + /*di CMA pool */ + di_cma_reserved:linux,di_cma { + compatible = "shared-dma-pool"; + reusable; + /* buffer_size = 3621952(yuv422 8bit) + * | 4736064(yuv422 10bit) + * | 4074560(yuv422 10bit full pack mode) + * 10x3621952=34.6M(0x23) support 8bit + * 10x4736064=45.2M(0x2e) support 12bit + * 10x4074560=40M(0x28) support 10bit + */ + size = <0x02800000>; + alignment = <0x400000>; + }; + codec_mm_cma:linux,codec_mm_cma { + compatible = "shared-dma-pool"; + reusable; + /* ion_codec_mm max can alloc size 80M*/ + size = <0x13400000>; + alignment = <0x400000>; + linux,contiguous-region; + }; + /* codec shared reserved */ + codec_mm_reserved:linux,codec_mm_reserved { + compatible = "amlogic, codec-mm-reserved"; + size = <0x0>; + alignment = <0x100000>; + //no-map; + }; + /* vdin0 CMA pool */ + vdin0_cma_reserved:linux,vdin0_cma { + compatible = "shared-dma-pool"; + reusable; + /* 1920x1080x2x4 =16+4 M */ + size = <0x04000000>; + alignment = <0x400000>; + }; + /* vdin1 CMA pool */ + vdin1_cma_reserved:linux,vdin1_cma { + compatible = "shared-dma-pool"; + reusable; + /* 1920x1080x2x4 =16 M */ + size = <0x04000000>; + alignment = <0x400000>; + }; + }; + + cvbsout { + compatible = "amlogic, cvbsout-g12a"; + dev_name = "cvbsout"; + status = "okay"; + clocks = <&clkc CLKID_VCLK2_ENCI + &clkc CLKID_VCLK2_VENCI0 + &clkc CLKID_VCLK2_VENCI1 + &clkc CLKID_DAC_CLK>; + clock-names = "venci_top_gate", + "venci_0_gate", + "venci_1_gate", + "vdac_clk_gate"; + clk_path = <0>; + + /* performance: reg_address, reg_value */ + /* g12a */ + performance = <0x1bf0 0x9 + 0x1b56 0x333 + 0x1b12 0x8080 + 0x1b05 0xfd + 0x1c59 0xf850 + 0xffff 0x0>; /* ending flag */ + performance_sarft = <0x1bf0 0x9 + 0x1b56 0x333 + 0x1b12 0x0 + 0x1b05 0x9 + 0x1c59 0xfc48 + 0xffff 0x0>; /* ending flag */ + performance_revB_telecom = <0x1bf0 0x9 + 0x1b56 0x546 + 0x1b12 0x8080 + 0x1b05 0x9 + 0x1c59 0xf850 + 0xffff 0x0>; /* ending flag */ + }; + + codec_mm { + compatible = "amlogic, codec, mm"; + memory-region = <&codec_mm_cma &codec_mm_reserved>; + dev_name = "codec_mm"; + status = "okay"; + }; + + deinterlace { + compatible = "amlogic, deinterlace"; + status = "okay"; + /* 0:use reserved; 1:use cma; 2:use cma as reserved */ + flag_cma = <1>; + //memory-region = <&di_reserved>; + memory-region = <&di_cma_reserved>; + interrupts = <0 46 1 + 0 40 1>; + interrupt-names = "pre_irq", "post_irq"; + clocks = <&clkc CLKID_VPU_CLKB_TMP_COMP>, + <&clkc CLKID_VPU_CLKB_COMP>; + clock-names = "vpu_clkb_tmp_composite", + "vpu_clkb_composite"; + clock-range = <334 667>; + /* buffer-size = <3621952>;(yuv422 8bit) */ + buffer-size = <4074560>;/*yuv422 fullpack*/ + /* reserve-iomap = "true"; */ + /* if enable nr10bit, set nr10bit-support to 1 */ + post-wr-support = <1>; + nr10bit-support = <1>; + nrds-enable = <1>; + pps-enable = <1>; + }; + + efusekey:efusekey{ + keynum = <4>; + key0 = <&key_0>; + key1 = <&key_1>; + key2 = <&key_2>; + key3 = <&key_3>; + key_0:key_0{ + keyname = "mac"; + offset = <0>; + size = <6>; + }; + key_1:key_1{ + keyname = "mac_bt"; + offset = <6>; + size = <6>; + }; + key_2:key_2{ + keyname = "mac_wifi"; + offset = <12>; + size = <6>; + }; + key_3:key_3{ + keyname = "usid"; + offset = <18>; + size = <16>; + }; + };//End efusekey + + amlvecm { + compatible = "amlogic, vecm"; + dev_name = "aml_vecm"; + status = "okay"; + gamma_en = <0>;/*1:enabel ;0:disable*/ + wb_en = <0>;/*1:enabel ;0:disable*/ + cm_en = <0>;/*1:enabel ;0:disable*/ + /*0: 709/601 1: bt2020*/ + tx_op_color_primary = <0>; + }; + amdolby_vision { + compatible = "amlogic, dolby_vision_g12a"; + dev_name = "aml_amdolby_vision_driver"; + status = "okay"; + tv_mode = <0>;/*1:enabel ;0:disable*/ + }; + + /* Audio Related start */ + + pdm_codec:dummy{ + #sound-dai-cells = <0>; + compatible = "amlogic, pdm_dummy_codec"; + status = "okay"; + }; + dummy_codec:dummy{ + #sound-dai-cells = <0>; + compatible = "amlogic, aml_dummy_codec"; + status = "okay"; + }; + amlogic_codec:t9015{ + #sound-dai-cells = <0>; + compatible = "amlogic, aml_codec_T9015"; + reg = <0xFF632000 0x2000>; + is_auge_used = <1>; /* meson or auge chipset used */ + tdmout_index = <0>; + status = "disabled"; + }; + auge_sound { + compatible = "amlogic, g12a-sound-card"; + aml-audio-card,name = "AML-AUGESOUND"; + + aml-audio-card,dai-link@0 { + format = "dsp_a"; + mclk-fs = <512>; + //continuous-clock; + //bitclock-inversion; + //frame-inversion; + //bitclock-master = <&tdmacodec>; + //frame-master = <&tdmacodec>; + tdmacpu: cpu { + sound-dai = <&aml_tdma>; + dai-tdm-slot-tx-mask = + <1 1 1 1 1 1 1 1>; + dai-tdm-slot-rx-mask = + <1 1 1 1 1 1 1 1>; + dai-tdm-slot-num = <8>; + dai-tdm-slot-width = <32>; + system-clock-frequency = <24576000>; + }; + tdmacodec: codec { + sound-dai = <&dummy_codec &dummy_codec>; + }; + }; + + aml-audio-card,dai-link@1 { + format = "i2s"; + mclk-fs = <256>; + //continuous-clock; + //bitclock-inversion; + //frame-inversion; + bitclock-master = <&aml_tdmb>; + frame-master = <&aml_tdmb>; + cpu { + sound-dai = <&aml_tdmb>; + dai-tdm-slot-tx-mask = <1 1>; + dai-tdm-slot-rx-mask = <1 1>; + dai-tdm-slot-num = <2>; + dai-tdm-slot-width = <32>; + system-clock-frequency = <12288000>; + }; + codec { + sound-dai = <&dummy_codec &dummy_codec>; + }; + }; + + aml-audio-card,dai-link@2 { + format = "i2s"; + mclk-fs = <256>; + continuous-clock; + //bitclock-inversion; + //frame-inversion; + bitclock-master = <&aml_tdmc>; + frame-master = <&aml_tdmc>; + cpu { + sound-dai = <&aml_tdmc>; + dai-tdm-slot-tx-mask = <1 1>; + dai-tdm-slot-rx-mask = <1 1>; + dai-tdm-slot-num = <2>; + dai-tdm-slot-width = <32>; + system-clock-frequency = <12288000>; + }; + codec { + sound-dai = <&dummy_codec &dummy_codec>; + }; + }; + + aml-audio-card,dai-link@3 { + mclk-fs = <64>; + cpu { + sound-dai = <&aml_pdm>; + }; + codec { + sound-dai = <&pdm_codec>; + }; + }; + + aml-audio-card,dai-link@4 { + mclk-fs = <128>; + cpu { + sound-dai = <&aml_spdif>; + system-clock-frequency = <6144000>; + }; + codec { + sound-dai = <&dummy_codec>; + }; + }; + aml-audio-card,dai-link@5 { + mclk-fs = <128>; + cpu { + sound-dai = <&aml_spdif_b>; + system-clock-frequency = <6144000>; + }; + codec { + sound-dai = <&dummy_codec>; + }; + }; + }; + audiolocker: locker { + compatible = "amlogic, audiolocker"; + clocks = <&clkaudio CLKID_AUDIO_LOCKER_OUT + &clkaudio CLKID_AUDIO_LOCKER_IN + &clkaudio CLKID_AUDIO_MCLK_D + &clkaudio CLKID_AUDIO_MCLK_E + &clkc CLKID_MPLL1 + &clkc CLKID_MPLL2>; + clock-names = "lock_out", "lock_in", "out_src", + "in_src", "out_calc", "in_ref"; + interrupts = ; + interrupt-names = "irq"; + frequency = <49000000>; /* pll */ + dividor = <49>; /* locker's parent */ + status = "disabled"; + }; + /* Audio Related end */ + + /*DCDC for MP8756GD*/ + cpu_opp_table0: cpu_opp_table0 { + compatible = "operating-points-v2"; + opp-shared; + + opp00 { + opp-hz = /bits/ 64 <100000000>; + opp-microvolt = <731000>; + }; + opp01 { + opp-hz = /bits/ 64 <250000000>; + opp-microvolt = <731000>; + }; + opp02 { + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <731000>; + }; + opp03 { + opp-hz = /bits/ 64 <667000000>; + opp-microvolt = <731000>; + }; + opp04 { + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <731000>; + }; + opp05 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <731000>; + }; + opp06 { + opp-hz = /bits/ 64 <1398000000>; + opp-microvolt = <761000>; + }; + opp07 { + opp-hz = /bits/ 64 <1512000000>; + opp-microvolt = <791000>; + }; + opp08 { + opp-hz = /bits/ 64 <1608000000>; + opp-microvolt = <831000>; + }; + opp09 { + opp-hz = /bits/ 64 <1704000000>; + opp-microvolt = <861000>; + }; + opp10 { + opp-hz = /bits/ 64 <1908000000>; + opp-microvolt = <981000>; + }; + }; + + cpufreq-meson { + compatible = "amlogic, cpufreq-meson"; + pinctrl-names = "default"; + pinctrl-0 = <&pwm_ao_d_pins3>; + status = "okay"; + }; + + +}; /* end of / */ + +&meson_fb { + status = "okay"; + display_size_default = <1920 1080 1920 2160 32>; + mem_size = <0x00800000 0x1980000 0x100000 0x100000 0x800000>; + logo_addr = "0x7f800000"; + mem_alloc = <1>; + pxp_mode = <1>; /** 0:normal mode 1:pxp mode */ +}; + +&pwm_AO_cd { + status = "okay"; + }; + +&audiobus { + aml_tdma: tdma { + compatible = "amlogic, g12a-snd-tdma"; + #sound-dai-cells = <0>; + dai-tdm-lane-slot-mask-in = <1 0>; + dai-tdm-lane-slot-mask-out = <0 1>; + dai-tdm-clk-sel = <0>; + clocks = <&clkaudio CLKID_AUDIO_MCLK_A + &clkc CLKID_MPLL0>; + clock-names = "mclk", "clk_srcpll"; + pinctrl-names = "tdm_pins"; + pinctrl-0 = <&tdmout_a &tdmin_a>; + }; + + aml_tdmb: tdmb { + compatible = "amlogic, g12a-snd-tdmb"; + #sound-dai-cells = <0>; + dai-tdm-lane-slot-mask-in = <1 1 1 1>; + dai-tdm-clk-sel = <1>; + clocks = <&clkaudio CLKID_AUDIO_MCLK_B + &clkc CLKID_MPLL1>; + clock-names = "mclk", "clk_srcpll"; + pinctrl-names = "tdm_pins"; + pinctrl-0 = <&tdmb_mclk /*&tdmout_b &tdmin_b*/>; + }; + + aml_tdmc: tdmc { + compatible = "amlogic, g12a-snd-tdmc"; + #sound-dai-cells = <0>; + dai-tdm-lane-slot-mask-in = <0 1 0 0>; + #dai-tdm-lane-slot-mask-out = <1 0 1 1>; + #dai-tdm-lane-oe-slot-mask-in = <0 0 0 0>; + dai-tdm-lane-oe-slot-mask-out = <1 0 0 0>; + dai-tdm-clk-sel = <2>; + clocks = <&clkaudio CLKID_AUDIO_MCLK_C + &clkc CLKID_MPLL2>; + clock-names = "mclk", "clk_srcpll"; + pinctrl-names = "tdm_pins"; + pinctrl-0 = <&tdmc_mclk &tdmout_c &tdmin_c>; + }; + + aml_spdif: spdif { + compatible = "amlogic, g12a-snd-spdif-a"; + #sound-dai-cells = <0>; + clocks = <&clkc CLKID_MPLL0 + &clkc CLKID_FCLK_DIV4 + &clkaudio CLKID_AUDIO_SPDIFIN + &clkaudio CLKID_AUDIO_SPDIFOUT + &clkaudio CLKID_AUDIO_SPDIFIN_CTRL + &clkaudio CLKID_AUDIO_SPDIFOUT_CTRL>; + clock-names = "sysclk", "fixed_clk", "gate_spdifin", + "gate_spdifout", "clk_spdifin", "clk_spdifout"; + interrupts = + ; + + interrupt-names = "irq_spdifin"; + pinctrl-names = "spdif_pins"; + pinctrl-0 = <&spdifout &spdifin>; + status = "okay"; + }; + aml_spdif_b: spdif_b { + compatible = "amlogic, g12a-snd-spdif-b"; + #sound-dai-cells = <0>; + clocks = <&clkc CLKID_MPLL0 /*CLKID_HIFI_PLL*/ + &clkaudio CLKID_AUDIO_SPDIFOUTB + &clkaudio CLKID_AUDIO_SPDIFOUTB_CTRL>; + clock-names = "sysclk", + "gate_spdifout", "clk_spdifout"; + pinctrl-names = "spdif_pins"; + pinctrl-0 = <&spdifout_b>; + status = "okay"; + }; + aml_pdm: pdm { + compatible = "amlogic, g12a-snd-pdm"; + #sound-dai-cells = <0>; + clocks = <&clkaudio CLKID_AUDIO_PDM + &clkc CLKID_FCLK_DIV3 + &clkc CLKID_MPLL3 + &clkaudio CLKID_AUDIO_PDMIN0 + &clkaudio CLKID_AUDIO_PDMIN1>; + clock-names = "gate", + "sysclk_srcpll", + "dclk_srcpll", + "pdm_dclk", + "pdm_sysclk"; + pinctrl-names = "pdm_pins"; + pinctrl-0 = <&pdmin>; + filter_mode = <1>; /* mode 0~4, defalut:1 */ + status = "okay"; + }; + aml_pwrdet: pwrdet { + compatible = "amlogic, g12a-power-detect"; + + interrupts = ; + interrupt-names = "pwrdet_irq"; + + /* pwrdet source sel + * 7: loopback; + * 6: tdmin_lb; + * 5: reserved; + * 4: pdmin; + * 3: spdifin; + * 2: tdmin_c; + * 1: tdmin_b; + * 0: tdmin_a; + */ + pwrdet_src = <4>; + + hi_th = <0x70000>; + lo_th = <0x16000>; + + status = "disabled"; + }; +}; /* end of audiobus */ + +&pinctrl_periphs { + tdmout_a: tdmout_a { + mux { /* GPIOX_11, GPIOX_10, GPIOX_8 */ + groups = "tdma_sclk", + "tdma_fs", + "tdma_dout1"; + function = "tdma_out"; + }; + }; + + tdmin_a: tdmin_a { + mux { /* GPIOX_9 */ + groups = "tdma_din0"; + function = "tdma_in"; + }; + }; + + tdmb_mclk: tdmb_mclk { + mux { + groups = "mclk0_a"; + function = "mclk0"; + }; + }; + + tdmc_mclk: tdmc_mclk { + mux { /* GPIOZ_8 */ + groups = "mclk1_z"; + function = "mclk1"; + }; + }; + + tdmout_c:tdmout_c { + mux { /* gpioz_7, gpioz_6, GPIOZ_2, GPIOZ_4, GPIOZ_5*/ + groups = "tdmc_sclk_z", + "tdmc_fs_z", + "tdmc_dout0_z" + /*,"tdmc_dout2_z", + *"tdmc_dout3_z" + */; + function = "tdmc_out"; + }; + }; + + tdmin_c:tdmin_c { + mux { /* GPIOZ_3 */ + groups = "tdmc_din1_z"; + function = "tdmc_in"; + }; + }; + + spdifin: spdifin { + mux {/* gpioa_10 */ + groups = "spdif_in_a10"; + function = "spdif_in"; + }; + }; + + spdifout: spdifout { + mux {/* gpioa_11 */ + groups = "spdif_out_a11"; + function = "spdif_out"; + }; + }; + + spdifout_b: spdifout_b { + mux { /* gpioa_13 */ + groups = "spdif_out_a13"; + function = "spdif_out"; + }; + }; + + pdmin: pdmin { + mux { /* gpioa_5, gpioa_6, gpioa_7, gpioa_8, gpioa_9*/ + groups = "pdm_din0_a", + "pdm_din1_a", + "pdm_din2_a", + "pdm_din3_a", + "pdm_dclk_a"; + function = "pdm"; + }; + }; + +}; /* end of pinctrl_periphs */ + +&pinctrl_aobus { + tdmout_b: tdmout_b { + mux { /* GPIOAO_7, GPIOAO_8, GPIOAO_4 */ + groups = "tdmb_fs_ao", + "tdmb_fs_ao", + "tdmb_dout0_ao"; + function = "tdmb_out_ao"; + }; + }; + + tdmin_b:tdmin_b { + mux { + groups = "tdmb_din2_ao"; + function = "tdmb_in_ao"; + }; + }; +}; /* end of pinctrl_aobus */ +/* Audio Related End */ + +&aobus{ + +}; + +&irblaster { + status = "disabled"; +}; + +/*if you want to use vdin just modify status to "ok"*/ +&vdin0 { + memory-region = <&vdin0_cma_reserved>; + status = "okay"; + /*vdin write mem color depth support: + *bit0:support 8bit + *bit1:support 9bit + *bit2:support 10bit + *bit3:support 12bit + *bit4:support yuv422 10bit full pack mode (from txl new add) + */ + tv_bit_mode = <0x15>; +}; +&vdin1 { + memory-region = <&vdin1_cma_reserved>; + status = "okay"; + /*vdin write mem color depth support: + *bit0:support 8bit + *bit1:support 9bit + *bit2:support 10bit + *bit3:support 12bit + */ + tv_bit_mode = <1>; +}; +&sd_emmc_b1 { + status = "okay"; + sd { + caps = "MMC_CAP_4_BIT_DATA", + "MMC_CAP_MMC_HIGHSPEED", + "MMC_CAP_SD_HIGHSPEED", + "MMC_CAP_NONREMOVABLE", + "MMC_CAP_UHS_SDR12", + "MMC_CAP_UHS_SDR25", + "MMC_CAP_UHS_SDR50", + "MMC_PM_KEEP_POWER", + "MMC_CAP_NONREMOVABLE"; /**ptm debug */ + f_min = <400000>; + f_max = <200000000>; + }; +}; + + +&defendkey { + status = "okay"; +}; + diff --git a/arch/arm/boot/dts/amlogic/g12a_s905d2_skt.dts b/arch/arm/boot/dts/amlogic/g12a_s905d2_skt.dts new file mode 100644 index 000000000000..0a8dec07a064 --- /dev/null +++ b/arch/arm/boot/dts/amlogic/g12a_s905d2_skt.dts @@ -0,0 +1,1298 @@ +/* + * arch/arm/boot/dts/amlogic/g12a_s905d2_skt.dts + * + * Copyright (C) 2017 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +/dts-v1/; + +#include "mesong12a.dtsi" +#include "partition_mbox_normal.dtsi" +#include "mesong12a_skt-panel.dtsi" + +/ { + model = "Amlogic"; + compatible = "amlogic, g12a"; + interrupt-parent = <&gic>; + #address-cells = <1>; + #size-cells = <1>; + + aliases { + serial0 = &uart_AO; + serial1 = &uart_A; + serial2 = &uart_B; + serial3 = &uart_C; + serial4 = &uart_AO_B; + tsensor0 = &p_tsensor; + tsensor1 = &d_tsensor; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c_AO; + }; + + memory@00000000 { + device_type = "memory"; + linux,usable-memory = <0x100000 0x7ff00000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + /* global autoconfigured region for contiguous allocations */ + ramoops@0x07400000 { + compatible = "ramoops"; + reg = <0x07400000 0x00100000>; + record-size = <0x8000>; + console-size = <0x8000>; + ftrace-size = <0x0>; + pmsg-size = <0x8000>; + }; + + secmon_reserved:linux,secmon { + compatible = "shared-dma-pool"; + reusable; + size = <0x400000>; + alignment = <0x400000>; + alloc-ranges = <0x05000000 0x400000>; + }; + secos_reserved:linux,secos { + status = "disable"; + compatible = "amlogic, aml_secos_memory"; + reg = <0x05300000 0x2000000>; + no-map; + }; + logo_reserved:linux,meson-fb { + compatible = "shared-dma-pool"; + reusable; + size = <0x800000>; + alignment = <0x400000>; + alloc-ranges = <0x7f800000 0x800000>; + }; + ion_cma_reserved:linux,ion-dev { + compatible = "shared-dma-pool"; + reusable; + size = <0x8000000>; + alignment = <0x400000>; + }; + //di_reserved:linux,di { + //compatible = "amlogic, di-mem"; + /* buffer_size = 3621952(yuv422 8bit) */ + /* 4179008(yuv422 10bit full pack mode) */ + /** 10x3621952=34.6M(0x23) support 8bit **/ + /** 10x4736064=45.2M(0x2e) support 12bit **/ + /** 10x4179008=40M(0x28) support 10bit **/ + //size = <0x2800000>; + //no-map; + //}; + /*di CMA pool */ + di_cma_reserved:linux,di_cma { + compatible = "shared-dma-pool"; + reusable; + /* buffer_size = 3621952(yuv422 8bit) + * | 4736064(yuv422 10bit) + * | 4074560(yuv422 10bit full pack mode) + * 10x3621952=34.6M(0x23) support 8bit + * 10x4736064=45.2M(0x2e) support 12bit + * 10x4074560=40M(0x28) support 10bit + */ + size = <0x02800000>; + alignment = <0x400000>; + }; + /* POST PROCESS MANAGER */ + ppmgr_reserved:linux,ppmgr { + compatible = "shared-dma-pool"; + size = <0x0>; + }; + + codec_mm_cma:linux,codec_mm_cma { + compatible = "shared-dma-pool"; + reusable; + /* ion_codec_mm max can alloc size 80M*/ + size = <0x13400000>; + alignment = <0x400000>; + linux,contiguous-region; + }; + /* codec shared reserved */ + codec_mm_reserved:linux,codec_mm_reserved { + compatible = "amlogic, codec-mm-reserved"; + size = <0x0>; + alignment = <0x100000>; + //no-map; + }; + /* vdin0 CMA pool */ + vdin0_cma_reserved:linux,vdin0_cma { + compatible = "shared-dma-pool"; + reusable; + /* 1920x1080x2x4 =16+4 M */ + size = <0x04000000>; + alignment = <0x400000>; + }; + /* vdin1 CMA pool */ + vdin1_cma_reserved:linux,vdin1_cma { + compatible = "shared-dma-pool"; + reusable; + /* 1920x1080x2x4 =16 M */ + size = <0x04000000>; + alignment = <0x400000>; + }; + }; + + cvbsout { + compatible = "amlogic, cvbsout-g12a"; + dev_name = "cvbsout"; + status = "okay"; + clocks = <&clkc CLKID_VCLK2_ENCI + &clkc CLKID_VCLK2_VENCI0 + &clkc CLKID_VCLK2_VENCI1 + &clkc CLKID_DAC_CLK>; + clock-names = "venci_top_gate", + "venci_0_gate", + "venci_1_gate", + "vdac_clk_gate"; + /* clk path */ + /* 0:vid_pll vid2_clk */ + /* 1:gp0_pll vid2_clk */ + /* 2:vid_pll vid1_clk */ + /* 3:gp0_pll vid1_clk */ + clk_path = <0>; + + /* performance: reg_address, reg_value */ + /* g12a */ + performance = <0x1bf0 0x9 + 0x1b56 0x333 + 0x1b12 0x8080 + 0x1b05 0xfd + 0x1c59 0xf850 + 0xffff 0x0>; /* ending flag */ + performance_sarft = <0x1bf0 0x9 + 0x1b56 0x333 + 0x1b12 0x0 + 0x1b05 0x9 + 0x1c59 0xfc48 + 0xffff 0x0>; /* ending flag */ + performance_revB_telecom = <0x1bf0 0x9 + 0x1b56 0x546 + 0x1b12 0x8080 + 0x1b05 0x9 + 0x1c59 0xf850 + 0xffff 0x0>; /* ending flag */ + }; + + bt-dev{ + compatible = "amlogic, bt-dev"; + dev_name = "bt-dev"; + status = "disable"; + gpio_reset = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>; + gpio_hostwake = <&gpio GPIOX_19 GPIO_ACTIVE_HIGH>; + }; + + wifi{ + compatible = "amlogic, aml_wifi"; + dev_name = "aml_wifi"; + status = "disable"; + interrupt_pin = <&gpio GPIOX_7 GPIO_ACTIVE_HIGH>; + irq_trigger_type = "GPIO_IRQ_LOW"; + power_on_pin = <&gpio GPIOX_6 GPIO_ACTIVE_HIGH>; + dhd_static_buf; //if use bcm wifi, config dhd_static_buf + pinctrl-names = "default"; + pinctrl-0 = <&pwm_e_pins>; + pwm_config = <&wifi_pwm_conf>; + }; + + wifi_pwm_conf:wifi_pwm_conf{ + pwm_channel1_conf { + pwms = <&pwm_ef MESON_PWM_0 30040 0>; + duty-cycle = <15020>; + times = <10>; + }; + pwm_channel2_conf { + pwms = <&pwm_ef MESON_PWM_2 30030 0>; + duty-cycle = <15015>; + times = <12>; + }; + }; + + codec_mm { + compatible = "amlogic, codec, mm"; + memory-region = <&codec_mm_cma &codec_mm_reserved>; + dev_name = "codec_mm"; + status = "okay"; + }; + + ppmgr { + compatible = "amlogic, ppmgr"; + memory-region = <&ppmgr_reserved>; + dev_name = "ppmgr"; + status = "okay"; + }; + + deinterlace { + compatible = "amlogic, deinterlace"; + status = "okay"; + /* 0:use reserved; 1:use cma; 2:use cma as reserved */ + flag_cma = <1>; + //memory-region = <&di_reserved>; + memory-region = <&di_cma_reserved>; + interrupts = <0 46 1 + 0 40 1>; + interrupt-names = "pre_irq", "post_irq"; + clocks = <&clkc CLKID_VPU_CLKB_TMP_COMP>, + <&clkc CLKID_VPU_CLKB_COMP>; + clock-names = "vpu_clkb_tmp_composite", + "vpu_clkb_composite"; + clock-range = <334 667>; + /* buffer-size = <3621952>;(yuv422 8bit) */ + buffer-size = <4074560>;/*yuv422 fullpack*/ + /* reserve-iomap = "true"; */ + /* if enable nr10bit, set nr10bit-support to 1 */ + post-wr-support = <1>; + nr10bit-support = <1>; + nrds-enable = <1>; + pps-enable = <1>; + }; + ionvideo { + compatible = "amlogic, ionvideo"; + dev_name = "ionvideo"; + status = "okay"; + }; + + unifykey{ + compatible = "amlogic, unifykey"; + status = "ok"; + unifykey-num = <15>; + unifykey-index-0 = <&keysn_0>; + unifykey-index-1 = <&keysn_1>; + unifykey-index-2 = <&keysn_2>; + unifykey-index-3 = <&keysn_3>; + unifykey-index-4 = <&keysn_4>; + unifykey-index-5 = <&keysn_5>; + unifykey-index-6 = <&keysn_6>; + unifykey-index-7 = <&keysn_7>; + unifykey-index-8 = <&keysn_8>; + unifykey-index-9 = <&keysn_9>; + unifykey-index-10= <&keysn_10>; + unifykey-index-11= <&keysn_11>; + unifykey-index-12= <&keysn_12>; + unifykey-index-13= <&keysn_13>; + unifykey-index-14= <&keysn_14>; + + keysn_0: key_0{ + key-name = "usid"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_1:key_1{ + key-name = "mac"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_2:key_2{ + key-name = "hdcp"; + key-device = "secure"; + key-type = "sha1"; + key-permit = "read","write","del"; + }; + keysn_3:key_3{ + key-name = "secure_boot_set"; + key-device = "efuse"; + key-permit = "write"; + }; + keysn_4:key_4{ + key-name = "mac_bt"; + key-device = "normal"; + key-permit = "read","write","del"; + key-type = "mac"; + }; + keysn_5:key_5{ + key-name = "mac_wifi"; + key-device = "normal"; + key-permit = "read","write","del"; + key-type = "mac"; + }; + keysn_6:key_6{ + key-name = "hdcp2_tx"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_7:key_7{ + key-name = "hdcp2_rx"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_8:key_8{ + key-name = "widevinekeybox"; + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_9:key_9{ + key-name = "deviceid"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_10:key_10{ + key-name = "hdcp22_fw_private"; + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_11:key_11{ + key-name = "PlayReadykeybox25"; + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_12:key_12{ + key-name = "prpubkeybox";// PlayReady + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_13:key_13{ + key-name = "prprivkeybox";// PlayReady + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_14:key_14{ + key-name = "attestationkeybox";// attestation key + key-device = "secure"; + key-permit = "read","write","del"; + }; + };//End unifykey + + efusekey:efusekey{ + keynum = <4>; + key0 = <&key_0>; + key1 = <&key_1>; + key2 = <&key_2>; + key3 = <&key_3>; + key_0:key_0{ + keyname = "mac"; + offset = <0>; + size = <6>; + }; + key_1:key_1{ + keyname = "mac_bt"; + offset = <6>; + size = <6>; + }; + key_2:key_2{ + keyname = "mac_wifi"; + offset = <12>; + size = <6>; + }; + key_3:key_3{ + keyname = "usid"; + offset = <18>; + size = <16>; + }; + };//End efusekey + + amlvecm { + compatible = "amlogic, vecm"; + dev_name = "aml_vecm"; + status = "okay"; + gamma_en = <0>;/*1:enabel ;0:disable*/ + wb_en = <0>;/*1:enabel ;0:disable*/ + cm_en = <0>;/*1:enabel ;0:disable*/ + /*0: 709/601 1: bt2020*/ + tx_op_color_primary = <0>; + }; + + amdolby_vision { + compatible = "amlogic, dolby_vision_g12a"; + dev_name = "aml_amdolby_vision_driver"; + status = "okay"; + tv_mode = <0>;/*1:enabel ;0:disable*/ + }; + + /* Audio Related start */ + pdm_codec:dummy{ + #sound-dai-cells = <0>; + compatible = "amlogic, pdm_dummy_codec"; + status = "okay"; + }; + dummy_codec:dummy{ + #sound-dai-cells = <0>; + compatible = "amlogic, aml_dummy_codec"; + status = "okay"; + }; + amlogic_codec:t9015{ + #sound-dai-cells = <0>; + compatible = "amlogic, aml_codec_T9015"; + reg = <0xFF632000 0x2000>; + is_auge_used = <1>; /* meson or auge chipset used */ + tdmout_index = <1>; + status = "okay"; + }; + audio_effect:eqdrc{ + /*eq_enable = <1>;*/ + /*drc_enable = <1>;*/ + /* + * 0:tdmout_a + * 1:tdmout_b + * 2:tdmout_c + * 3:spdifout + * 4:spdifout_b + */ + eqdrc_module = <1>; + /* max 0xf, each bit for one lane, usually one lane */ + lane_mask = <0x1>; + /* max 0xff, each bit for one channel */ + channel_mask = <0x3>; + }; + auge_sound { + compatible = "amlogic, g12a-sound-card"; + aml-audio-card,name = "AML-AUGESOUND"; + + aml-audio-card,loopback = <&aml_loopback>; + aml-audio-card,aux-devs = <&amlogic_codec>; + /*avout mute gpio*/ + avout_mute-gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_HIGH>; + /*for audio effect ,eqdrc */ + aml-audio-card,effect = <&audio_effect>; + + aml-audio-card,dai-link@0 { + format = "dsp_a"; + mclk-fs = <512>; + //continuous-clock; + //bitclock-inversion; + //frame-inversion; + //bitclock-master = <&tdmacodec>; + //frame-master = <&tdmacodec>; + /* suffix-name, sync with android audio hal + * what's the dai link used for + */ + suffix-name = "alsaPORT-pcm"; + tdmacpu: cpu { + sound-dai = <&aml_tdma>; + dai-tdm-slot-tx-mask = + <1 1 1 1 1 1 1 1>; + dai-tdm-slot-rx-mask = + <1 1 1 1 1 1 1 1>; + dai-tdm-slot-num = <8>; + dai-tdm-slot-width = <32>; + system-clock-frequency = <24576000>; + }; + tdmacodec: codec { + sound-dai = <&dummy_codec &dummy_codec>; + }; + }; + + aml-audio-card,dai-link@1 { + format = "i2s";// "dsp_a"; + mclk-fs = <256>; + //continuous-clock; + //bitclock-inversion; + //frame-inversion; + bitclock-master = <&aml_tdmb>; + frame-master = <&aml_tdmb>; + //bitclock-master = <&tdmbcodec>; + //frame-master = <&tdmbcodec>; + /* suffix-name, sync with android audio hal + * what's the dai link used for + */ + suffix-name = "alsaPORT-i2s"; + cpu { + sound-dai = <&aml_tdmb>; + dai-tdm-slot-tx-mask = <1 1>; + dai-tdm-slot-rx-mask = <1 1>; + dai-tdm-slot-num = <2>; + /* + * dai-tdm-slot-tx-mask = + * <1 1 1 1 1 1 1 1>; + * dai-tdm-slot-rx-mask = + * <1 1 1 1 1 1 1 1>; + * dai-tdm-slot-num = <8>; + */ + dai-tdm-slot-width = <32>; + system-clock-frequency = <12288000>; + }; + tdmbcodec: codec { + sound-dai = <&dummy_codec &dummy_codec + &amlogic_codec &ad82584f_62>; + }; + }; + + aml-audio-card,dai-link@2 { + format = "i2s"; + mclk-fs = <256>; + //continuous-clock; + //bitclock-inversion; + //frame-inversion; + bitclock-master = <&aml_tdmc>; + frame-master = <&aml_tdmc>; + /* suffix-name, sync with android audio hal + * what's the dai link used for + */ + //suffix-name = "alsaPORT-tdm"; + cpu { + sound-dai = <&aml_tdmc>; + dai-tdm-slot-tx-mask = <1 1>; + dai-tdm-slot-rx-mask = <1 1>; + dai-tdm-slot-num = <2>; + dai-tdm-slot-width = <32>; + system-clock-frequency = <12288000>; + }; + codec { + sound-dai = <&tlv320adc3101_32 &dummy_codec>; + }; + }; + + aml-audio-card,dai-link@3 { + mclk-fs = <64>; + /* suffix-name, sync with android audio hal + * what's the dai link used for + */ + suffix-name = "alsaPORT-pdm"; + cpu { + sound-dai = <&aml_pdm>; + }; + codec { + sound-dai = <&pdm_codec>; + }; + }; + + aml-audio-card,dai-link@4 { + mclk-fs = <128>; + /* suffix-name, sync with android audio hal + * what's the dai link used for + */ + suffix-name = "alsaPORT-spdif"; + cpu { + sound-dai = <&aml_spdif>; + system-clock-frequency = <6144000>; + }; + codec { + sound-dai = <&dummy_codec>; + }; + }; + /* spdif_b to hdmi, only playback */ + aml-audio-card,dai-link@5 { + mclk-fs = <128>; + continuous-clock; + /* suffix-name, sync with android audio hal + * what's the dai link used for + */ + suffix-name = "alsaPORT-spdifb2hdmi"; + cpu { + sound-dai = <&aml_spdif_b>; + system-clock-frequency = <6144000>; + }; + codec { + sound-dai = <&dummy_codec>; + }; + }; + }; + audiolocker: locker { + compatible = "amlogic, audiolocker"; + clocks = <&clkaudio CLKID_AUDIO_LOCKER_OUT + &clkaudio CLKID_AUDIO_LOCKER_IN + &clkaudio CLKID_AUDIO_MCLK_D + &clkaudio CLKID_AUDIO_MCLK_E + &clkc CLKID_MPLL1 + &clkc CLKID_MPLL2>; + clock-names = "lock_out", "lock_in", "out_src", + "in_src", "out_calc", "in_ref"; + interrupts = ; + interrupt-names = "irq"; + frequency = <49000000>; /* pll */ + dividor = <49>; /* locker's parent */ + status = "okay"; + }; + /* Audio Related end */ + + /*DCDC for MP8756GD*/ + cpu_opp_table0: cpu_opp_table0 { + compatible = "operating-points-v2"; + opp-shared; + + opp00 { + opp-hz = /bits/ 64 <100000000>; + opp-microvolt = <731000>; + }; + opp01 { + opp-hz = /bits/ 64 <250000000>; + opp-microvolt = <731000>; + }; + opp02 { + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <731000>; + }; + opp03 { + opp-hz = /bits/ 64 <667000000>; + opp-microvolt = <731000>; + }; + opp04 { + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <731000>; + }; + opp05 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <761000>; + }; + opp06 { + opp-hz = /bits/ 64 <1398000000>; + opp-microvolt = <791000>; + }; + opp07 { + opp-hz = /bits/ 64 <1512000000>; + opp-microvolt = <831000>; + }; + opp08 { + opp-hz = /bits/ 64 <1608000000>; + opp-microvolt = <871000>; + }; + opp09 { + opp-hz = /bits/ 64 <1704000000>; + opp-microvolt = <921000>; + }; + opp10 { + opp-hz = /bits/ 64 <1800000000>; + opp-microvolt = <981000>; + }; + }; + + cpufreq-meson { + compatible = "amlogic, cpufreq-meson"; + pinctrl-names = "default"; + pinctrl-0 = <&pwm_ao_d_pins3>; + status = "okay"; + }; + +}; /* end of / */ + +&meson_fb { + status = "okay"; + display_size_default = <1920 1080 1920 2160 32>; + mem_size = <0x00800000 0x1980000 0x100000 0x100000 0x800000>; + logo_addr = "0x7f800000"; + mem_alloc = <0>; + pxp_mode = <0>; /** 0:normal mode 1:pxp mode */ +}; + +&pwm_AO_cd { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + pinctrl-names="default"; + pinctrl-0=<&i2c0_master_pins2>; + clock-frequency = <400000>; + + gt9xx@5d { + compatible = "goodix,gt9xx"; + status = "disabled"; + reg = <0x5d>; + reset-gpio = <&gpio GPIOZ_9 0x00>; + irq-gpio = <&gpio GPIOZ_3 0x00>; + }; + + ftxx@38 { + compatible = "focaltech,fts"; + status = "disabled"; + reg = <0x38>; + reset-gpio = <&gpio GPIOZ_9 0x00>; + irq-gpio = <&gpio GPIOZ_3 0x00>; + x_max = <600>; + y_max = <1024>; + max-touch-number = <10>; + }; +}; + +&i2c3 { + status = "okay"; + pinctrl-names="default"; + pinctrl-0=<&i2c3_master_pins2>; + clock-frequency = <100000>; /* default 100k */ + + /* for ref board */ + ad82584f_62: ad82584f_62@62 { + compatible = "ESMT, ad82584f"; + #sound-dai-cells = <0>; + reg = <0x31>; + status = "okay"; + reset_pin = <&gpio GPIOA_5 0>; + }; + + tlv320adc3101_32: tlv320adc3101_32@32 { + compatible = "ti,tlv320adc3101"; + #sound-dai-cells = <0>; + reg = <0x19>; + differential_pair = <1>; + status = "okay"; + }; + + tas5707_36: tas5707_36@36 { + compatible = "ti,tas5707"; + #sound-dai-cells = <0>; + reg = <0x1b>; + status = "disabled"; + reset_pin = <&gpio GPIOA_5 0>; + }; + + bl_extern_i2c { + compatible = "amlogic, bl_extern_i2c"; + status = "disabled"; + reg = <0x2c>; /*reg_address for lp8556*/ + dev_name = "lp8556"; + }; + + lcd_extern_i2c0: lcd_extern_i2c@0 { + compatible = "lcd_ext, i2c"; + dev_name = "i2c_LT8912_0"; + reg = <0x48>; + status = "disabled"; + }; + + lcd_extern_i2c1: lcd_extern_i2c@1 { + compatible = "lcd_ext, i2c"; + dev_name = "i2c_LT8912_1"; + reg = <0x49>; + status = "disabled"; + }; +}; + +&audiobus { + aml_tdma: tdma { + compatible = "amlogic, g12a-snd-tdma"; + #sound-dai-cells = <0>; + dai-tdm-lane-slot-mask-in = <0 1>; + dai-tdm-oe-lane-slot-mask-out = <1 0>; + dai-tdm-clk-sel = <0>; + clocks = <&clkaudio CLKID_AUDIO_MCLK_A + &clkc CLKID_MPLL0>; + clock-names = "mclk", "clk_srcpll"; + pinctrl-names = "tdm_pins"; + pinctrl-0 = <&tdmout_a &tdmin_a>; + }; + + aml_tdmb: tdmb { + compatible = "amlogic, g12a-snd-tdmb"; + #sound-dai-cells = <0>; + dai-tdm-lane-slot-mask-in = <0 1 0 0>; + dai-tdm-lane-slot-mask-out = <1 0 0 0>; + dai-tdm-clk-sel = <1>; + clocks = <&clkaudio CLKID_AUDIO_MCLK_B + &clkc CLKID_MPLL1 + &clkc CLKID_MPLL0>; + clock-names = "mclk", "clk_srcpll", "samesource_sysclk"; + pinctrl-names = "tdm_pins"; + pinctrl-0 = <&tdmb_mclk &tdmout_b &tdmin_b>; + /* + * 0: tdmout_a; + * 1: tdmout_b; + * 2: tdmout_c; + * 3: spdifout; + * 4: spdifout_b; + */ + samesource_sel = <4>; + }; + + aml_tdmc: tdmc { + compatible = "amlogic, g12a-snd-tdmc"; + #sound-dai-cells = <0>; + dai-tdm-lane-slot-mask-in = <1 0 0 0>; + #dai-tdm-lane-slot-mask-out = <1 0 1 1>; + #dai-tdm-lane-oe-slot-mask-in = <0 0 0 0>; + #dai-tdm-lane-oe-slot-mask-out = <1 0 0 0>; + dai-tdm-clk-sel = <2>; + clocks = <&clkaudio CLKID_AUDIO_MCLK_C + &clkc CLKID_MPLL2>; + clock-names = "mclk", "clk_srcpll"; + pinctrl-names = "tdm_pins"; + pinctrl-0 = <&tdmc_mclk &tdmout_c &tdmin_c>; + }; + + + aml_spdif: spdif { + compatible = "amlogic, g12a-snd-spdif-a"; + #sound-dai-cells = <0>; + clocks = <&clkc CLKID_MPLL0 + &clkc CLKID_FCLK_DIV4 + &clkaudio CLKID_AUDIO_SPDIFIN + &clkaudio CLKID_AUDIO_SPDIFOUT + &clkaudio CLKID_AUDIO_SPDIFIN_CTRL + &clkaudio CLKID_AUDIO_SPDIFOUT_CTRL>; + clock-names = "sysclk", "fixed_clk", "gate_spdifin", + "gate_spdifout", "clk_spdifin", "clk_spdifout"; + interrupts = + ; + + interrupt-names = "irq_spdifin"; + pinctrl-names = "spdif_pins"; + pinctrl-0 = <&spdifout &spdifin>; + status = "okay"; + }; + aml_spdif_b: spdif_b { + compatible = "amlogic, g12a-snd-spdif-b"; + #sound-dai-cells = <0>; + clocks = <&clkc CLKID_MPLL0 /*CLKID_HIFI_PLL*/ + &clkaudio CLKID_AUDIO_SPDIFOUTB + &clkaudio CLKID_AUDIO_SPDIFOUTB_CTRL>; + clock-names = "sysclk", + "gate_spdifout", "clk_spdifout"; + status = "okay"; + }; + aml_pdm: pdm { + compatible = "amlogic, g12a-snd-pdm"; + #sound-dai-cells = <0>; + clocks = <&clkaudio CLKID_AUDIO_PDM + &clkc CLKID_FCLK_DIV3 + &clkc CLKID_MPLL3 + &clkaudio CLKID_AUDIO_PDMIN0 + &clkaudio CLKID_AUDIO_PDMIN1>; + clock-names = "gate", + "sysclk_srcpll", + "dclk_srcpll", + "pdm_dclk", + "pdm_sysclk"; + pinctrl-names = "pdm_pins"; + pinctrl-0 = <&pdmin>; + filter_mode = <1>; /* mode 0~4, defalut:1 */ + status = "okay"; + }; + aml_loopback: loopback { + compatible = "amlogic, snd-loopback"; + /* + * 0: out rate = in data rate; + * 1: out rate = loopback data rate; + */ + lb_mode = <0>; + + /* datain src + * 0: tdmin_a; + * 1: tdmin_b; + * 2: tdmin_c; + * 3: spdifin; + * 4: pdmin; + */ + datain_src = <4>; + datain_chnum = <8>; + datain_chmask = <0x3f>; + + /* tdmin_lb src + * 0: tdmoutA + * 1: tdmoutB + * 2: tdmoutC + * 3: PAD_tdminA + * 4: PAD_tdminB + * 5: PAD_tdminC + */ + datalb_src = <2>; + datalb_chnum = <8>; + datalb_chmask = <0x3>; + + status = "okay"; + }; + + audioresample: resample { + compatible = "amlogic, g12a-resample"; + clocks = <&clkc CLKID_MPLL3 + &clkaudio CLKID_AUDIO_MCLK_F + &clkaudio CLKID_AUDIO_RESAMPLE_CTRL>; + clock-names = "resample_pll", "resample_src", "resample_clk"; + /*same with toddr_src + * TDMIN_A, 0 + * TDMIN_B, 1 + * TDMIN_C, 2 + * SPDIFIN, 3 + * PDMIN, 4 + * NONE, + * TDMIN_LB, 6 + * LOOPBACK, 7 + */ + resample_module = <4>; + status = "okay"; + }; + aml_pwrdet: pwrdet { + compatible = "amlogic, g12a-power-detect"; + + interrupts = ; + interrupt-names = "pwrdet_irq"; + + /* pwrdet source sel + * 7: loopback; + * 6: tdmin_lb; + * 5: reserved; + * 4: pdmin; + * 3: spdifin; + * 2: tdmin_c; + * 1: tdmin_b; + * 0: tdmin_a; + */ + pwrdet_src = <4>; + + hi_th = <0x70000>; + lo_th = <0x16000>; + + status = "disabled"; + }; +}; /* end of audiobus */ + +&pinctrl_periphs { + tdmout_a: tdmout_a { + mux { /* GPIOX_11, GPIOX_10, GPIOX_9 */ + groups = "tdma_sclk", + "tdma_fs", + "tdma_dout0"; + function = "tdma_out"; + }; + }; + + tdmin_a: tdmin_a { + mux { /* GPIOX_8 */ + groups = "tdma_din1"; + function = "tdma_in"; + }; + }; + + tdmb_mclk: tdmb_mclk { + mux { + groups = "mclk0_a"; + function = "mclk0"; + drive-strength = <2>; + }; + }; + tdmout_b: tdmout_b { + mux { /* GPIOA_1, GPIOA_2, GPIOA_3 */ + groups = "tdmb_sclk", + "tdmb_fs", + "tdmb_dout0"; + function = "tdmb_out"; + drive-strength = <2>; + }; + }; + + tdmin_b:tdmin_b { + mux { /* GPIOA_4 */ + groups = "tdmb_din1" + /*,"tdmb_slv_sclk", "tdmb_slv_fs"*/; + function = "tdmb_in"; + drive-strength = <2>; + }; + }; + + tdmc_mclk: tdmc_mclk { + mux { /* GPIOA_11 */ + groups = "mclk1_a"; + function = "mclk1"; + }; + }; + + tdmout_c:tdmout_c { + mux { /* GPIOA_12, GPIOA_13, GPIOA_10, GPIOA_8, GPIOA_7*/ + groups = "tdmc_sclk_a", + "tdmc_fs_a", + "tdmc_dout0_a" + /*, "tdmc_dout2", + * "tdmc_dout3" + */; + function = "tdmc_out"; + }; + }; + + tdmin_c:tdmin_c { + mux { /* GPIOA_9 */ + groups = "tdmc_din1_a"; + function = "tdmc_in"; + }; + }; + + spdifin: spdifin { + mux {/* GPIOH_5 */ + groups = "spdif_in_h"; + function = "spdif_in"; + }; + }; + + /* GPIOH_4 */ + /* + * spdifout: spdifout { + * mux { + * groups = "spdif_out_h"; + * function = "spdif_out"; + * }; + *}; + */ + + pdmin: pdmin { + mux { /* gpioa_5, gpioa_6, gpioa_7, gpioa_8, gpioa_9*/ + groups = "pdm_din0_a", + /*"pdm_din1_a",*/ + "pdm_din2_a", + /*"pdm_din3_a",*/ + "pdm_dclk_a"; + function = "pdm"; + }; + }; + + bl_pwm_off_pins:bl_pwm_off_pin { + mux { + pins = "GPIOH_5"; + function = "gpio_periphs"; + output-high; + }; + }; + +}; /* end of pinctrl_periphs */ +&pinctrl_aobus { + spdifout: spdifout { + mux { /* gpiao_10 */ + groups = "spdif_out_ao"; + function = "spdif_out_ao"; + }; + }; +}; /* end of pinctrl_aobus */ + +&audio_data { + status = "okay"; +}; + +/* Audio Related End */ + +&spicc0 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&spicc0_pins_x>; + cs-gpios = <&gpio GPIOX_10 0>; +}; + +&spicc1 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&spicc1_pins>; + cs-gpios = <&gpio GPIOH_6 0>; +}; + +&pwm_ef { + status = "okay"; +}; + +&dwc3 { + status = "okay"; +}; + +&usb2_phy_v2 { + status = "okay"; + portnum = <2>; +}; + +&usb3_phy_v2 { + status = "okay"; + portnum = <0>; + otg = <1>; + gpio-vbus-power = "GPIOH_6"; + gpios = <&gpio GPIOH_6 GPIO_ACTIVE_HIGH>; +}; + +&dwc2_a { + status = "okay"; + /** 0: normal, 1: otg+dwc3 host only, 2: otg+dwc3 device only*/ + controller-type = <3>; +}; +ðmac { + status = "okay"; + pinctrl-names = "internal_eth_pins", "internal_gpio_pins"; + pinctrl-0 = <&internal_eth_pins>; + pinctrl-1 = <&internal_gpio_pins>; + mc_val = <0x4be04>; + + internal_phy=<1>; +}; + +&uart_A { + status = "okay"; +}; + +/*if you want to use vdin just modify status to "ok"*/ +&vdin0 { + memory-region = <&vdin0_cma_reserved>; + status = "okay"; + /*vdin write mem color depth support: + *bit0:support 8bit + *bit1:support 9bit + *bit2:support 10bit + *bit3:support 12bit + *bit4:support yuv422 10bit full pack mode (from txl new add) + */ + tv_bit_mode = <0x15>; +}; +&vdin1 { + memory-region = <&vdin1_cma_reserved>; + status = "okay"; + /*vdin write mem color depth support: + *bit0:support 8bit + *bit1:support 9bit + *bit2:support 10bit + *bit3:support 12bit + */ + tv_bit_mode = <1>; +}; + + +&sd_emmc_c { + status = "okay"; + emmc { + caps = "MMC_CAP_8_BIT_DATA", + "MMC_CAP_MMC_HIGHSPEED", + "MMC_CAP_SD_HIGHSPEED", + "MMC_CAP_NONREMOVABLE", + /* "MMC_CAP_1_8V_DDR", */ + "MMC_CAP_HW_RESET", + "MMC_CAP_ERASE", + "MMC_CAP_CMD23"; + caps2 = "MMC_CAP2_HS200"; + /* "MMC_CAP2_HS400";*/ + f_min = <400000>; + f_max = <200000000>; + }; +}; + +&sd_emmc_b1 { + status = "disable"; + sd { + caps = "MMC_CAP_4_BIT_DATA", + "MMC_CAP_MMC_HIGHSPEED", + "MMC_CAP_SD_HIGHSPEED"; + f_min = <400000>; + f_max = <50000000>; + }; +}; + +&sd_emmc_b2 { + status = "disabled"; + sd { + caps = "MMC_CAP_4_BIT_DATA", + "MMC_CAP_MMC_HIGHSPEED", + "MMC_CAP_SD_HIGHSPEED"; + f_min = <400000>; + f_max = <50000000>; + }; + + sdio { + caps = "MMC_CAP_4_BIT_DATA", + "MMC_CAP_MMC_HIGHSPEED", + "MMC_CAP_SD_HIGHSPEED", + "MMC_CAP_NONREMOVABLE", + "MMC_CAP_UHS_SDR12", + "MMC_CAP_UHS_SDR25", + "MMC_CAP_UHS_SDR50", + "MMC_CAP_UHS_SDR104", + "MMC_PM_KEEP_POWER", + "MMC_CAP_SDIO_IRQ"; + + f_min = <400000>; + f_max = <200000000>; + }; +}; + +&sd_emmc_a { + status = "disabled"; + sdio { + caps = "MMC_CAP_4_BIT_DATA", + "MMC_CAP_MMC_HIGHSPEED", + "MMC_CAP_SD_HIGHSPEED", + "MMC_CAP_NONREMOVABLE", + "MMC_CAP_UHS_SDR12", + "MMC_CAP_UHS_SDR25", + "MMC_CAP_UHS_SDR50", + "MMC_CAP_UHS_SDR104", + "MMC_PM_KEEP_POWER", + "MMC_CAP_SDIO_IRQ"; + f_min = <400000>; + f_max = <200000000>; + }; +}; + +&nand { + status = "disabled"; + plat-names = "bootloader","nandnormal"; + plat-num = <2>; + plat-part-0 = <&bootloader>; + plat-part-1 = <&nandnormal>; + bootloader: bootloader{ + enable_pad ="ce0"; + busy_pad = "rb0"; + timming_mode = "mode5"; + bch_mode = "bch8_1k"; + t_rea = <20>; + t_rhoh = <15>; + chip_num = <1>; + part_num = <0>; + rb_detect = <1>; + }; + nandnormal: nandnormal{ + enable_pad ="ce0"; + busy_pad = "rb0"; + timming_mode = "mode5"; + bch_mode = "bch8_1k"; + plane_mode = "twoplane"; + t_rea = <20>; + t_rhoh = <15>; + chip_num = <2>; + part_num = <3>; + partition = <&nand_partitions>; + rb_detect = <1>; + }; + nand_partitions:nand_partition{ + /* + * if bl_mode is 1, tpl size was generate by + * fip_copies * fip_size which + * will not skip bad when calculating + * the partition size; + * + * if bl_mode is 0, + * tpl partition must be comment out. + */ + tpl{ + offset=<0x0 0x0>; + size=<0x0 0x0>; + }; + logo{ + offset=<0x0 0x0>; + size=<0x0 0x200000>; + }; + recovery{ + offset=<0x0 0x0>; + size=<0x0 0x1000000>; + }; + boot{ + offset=<0x0 0x0>; + size=<0x0 0x1000000>; + }; + system{ + offset=<0x0 0x0>; + size=<0x0 0x4000000>; + }; + data{ + offset=<0xffffffff 0xffffffff>; + size=<0x0 0x0>; + }; + }; +}; + +&pcie_A { + reset-gpio = <&gpio GPIOX_7 GPIO_ACTIVE_HIGH>; + status = "disable"; +}; + +&meson_cooldev { + status = "okay"; +}; + +&defendkey { + status = "okay"; +}; + diff --git a/arch/arm/boot/dts/amlogic/g12a_s905d2_skt_buildroot.dts b/arch/arm/boot/dts/amlogic/g12a_s905d2_skt_buildroot.dts new file mode 100644 index 000000000000..1e4897abef31 --- /dev/null +++ b/arch/arm/boot/dts/amlogic/g12a_s905d2_skt_buildroot.dts @@ -0,0 +1,1240 @@ +/* + * arch/arm/boot/dts/amlogic/g12a_s905d2_skt_buildroot.dts + * + * Copyright (C) 2017 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +/dts-v1/; + +#include "mesong12a.dtsi" +#include "partition_mbox_normal.dtsi" +#include "mesong12a_skt-panel.dtsi" +#include "mesong12a_drm.dtsi" + +/ { + model = "Amlogic"; + compatible = "amlogic, g12a"; + interrupt-parent = <&gic>; + #address-cells = <1>; + #size-cells = <1>; + + aliases { + serial0 = &uart_AO; + serial1 = &uart_A; + serial2 = &uart_B; + serial3 = &uart_C; + serial4 = &uart_AO_B; + tsensor0 = &p_tsensor; + tsensor1 = &d_tsensor; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c_AO; + }; + + memory@00000000 { + device_type = "memory"; + linux,usable-memory = <0x100000 0x7ff00000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + /* global autoconfigured region for contiguous allocations */ + secmon_reserved:linux,secmon { + compatible = "shared-dma-pool"; + reusable; + size = <0x400000>; + alignment = <0x400000>; + alloc-ranges = <0x05000000 0x400000>; + }; + secos_reserved:linux,secos { + status = "disable"; + compatible = "amlogic, aml_secos_memory"; + reg = <0x05300000 0x2000000>; + no-map; + }; + logo_reserved:linux,meson-fb { + compatible = "shared-dma-pool"; + reusable; + size = <0x800000>; + alignment = <0x400000>; + alloc-ranges = <0x7f800000 0x800000>; + }; + ion_cma_reserved:linux,ion-dev { + compatible = "shared-dma-pool"; + reusable; + size = <0x8000000>; + alignment = <0x400000>; + }; + //di_reserved:linux,di { + //compatible = "amlogic, di-mem"; + /* buffer_size = 3621952(yuv422 8bit) */ + /* 4179008(yuv422 10bit full pack mode) */ + /** 10x3621952=34.6M(0x23) support 8bit **/ + /** 10x4736064=45.2M(0x2e) support 12bit **/ + /** 10x4179008=40M(0x28) support 10bit **/ + //size = <0x2800000>; + //no-map; + //}; + /*di CMA pool */ + di_cma_reserved:linux,di_cma { + compatible = "shared-dma-pool"; + reusable; + /* buffer_size = 3621952(yuv422 8bit) + * | 4736064(yuv422 10bit) + * | 4074560(yuv422 10bit full pack mode) + * 10x3621952=34.6M(0x23) support 8bit + * 10x4736064=45.2M(0x2e) support 12bit + * 10x4074560=40M(0x28) support 10bit + */ + size = <0x02800000>; + alignment = <0x400000>; + }; + /* POST PROCESS MANAGER */ + ppmgr_reserved:linux,ppmgr { + compatible = "shared-dma-pool"; + size = <0x0>; + }; + + codec_mm_cma:linux,codec_mm_cma { + compatible = "shared-dma-pool"; + reusable; + /* ion_codec_mm max can alloc size 80M*/ + size = <0x13400000>; + alignment = <0x400000>; + linux,contiguous-region; + }; + /* codec shared reserved */ + codec_mm_reserved:linux,codec_mm_reserved { + compatible = "amlogic, codec-mm-reserved"; + size = <0x0>; + alignment = <0x100000>; + //no-map; + }; + /* vdin0 CMA pool */ + vdin0_cma_reserved:linux,vdin0_cma { + compatible = "shared-dma-pool"; + reusable; + /* 1920x1080x2x4 =16+4 M */ + size = <0x04000000>; + alignment = <0x400000>; + }; + /* vdin1 CMA pool */ + vdin1_cma_reserved:linux,vdin1_cma { + compatible = "shared-dma-pool"; + reusable; + /* 1920x1080x2x4 =16 M */ + size = <0x04000000>; + alignment = <0x400000>; + }; + }; + + cvbsout { + compatible = "amlogic, cvbsout-g12a"; + dev_name = "cvbsout"; + status = "okay"; + clocks = <&clkc CLKID_VCLK2_ENCI + &clkc CLKID_VCLK2_VENCI0 + &clkc CLKID_VCLK2_VENCI1 + &clkc CLKID_DAC_CLK>; + clock-names = "venci_top_gate", + "venci_0_gate", + "venci_1_gate", + "vdac_clk_gate"; + clk_path = <0>; + + /* performance: reg_address, reg_value */ + /* g12a */ + performance = <0x1bf0 0x9 + 0x1b56 0x333 + 0x1b12 0x8080 + 0x1b05 0xfd + 0x1c59 0xf850 + 0xffff 0x0>; /* ending flag */ + performance_sarft = <0x1bf0 0x9 + 0x1b56 0x333 + 0x1b12 0x0 + 0x1b05 0x9 + 0x1c59 0xfc48 + 0xffff 0x0>; /* ending flag */ + performance_revB_telecom = <0x1bf0 0x9 + 0x1b56 0x546 + 0x1b12 0x8080 + 0x1b05 0x9 + 0x1c59 0xf850 + 0xffff 0x0>; /* ending flag */ + }; + + bt-dev{ + compatible = "amlogic, bt-dev"; + dev_name = "bt-dev"; + status = "disable"; + gpio_reset = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>; + gpio_hostwake = <&gpio GPIOX_19 GPIO_ACTIVE_HIGH>; + }; + + wifi{ + compatible = "amlogic, aml_wifi"; + dev_name = "aml_wifi"; + status = "disable"; + interrupt_pin = <&gpio GPIOX_7 GPIO_ACTIVE_HIGH>; + irq_trigger_type = "GPIO_IRQ_LOW"; + power_on_pin = <&gpio GPIOX_6 GPIO_ACTIVE_HIGH>; + dhd_static_buf; //if use bcm wifi, config dhd_static_buf + pinctrl-names = "default"; + pinctrl-0 = <&pwm_e_pins>; + pwm_config = <&wifi_pwm_conf>; + }; + + wifi_pwm_conf:wifi_pwm_conf{ + pwm_channel1_conf { + pwms = <&pwm_ef MESON_PWM_0 30040 0>; + duty-cycle = <15020>; + times = <10>; + }; + pwm_channel2_conf { + pwms = <&pwm_ef MESON_PWM_2 30030 0>; + duty-cycle = <15015>; + times = <12>; + }; + }; + + codec_mm { + compatible = "amlogic, codec, mm"; + memory-region = <&codec_mm_cma &codec_mm_reserved>; + dev_name = "codec_mm"; + status = "okay"; + }; + + ppmgr { + compatible = "amlogic, ppmgr"; + memory-region = <&ppmgr_reserved>; + dev_name = "ppmgr"; + status = "okay"; + }; + + deinterlace { + compatible = "amlogic, deinterlace"; + status = "okay"; + /* 0:use reserved; 1:use cma; 2:use cma as reserved */ + flag_cma = <1>; + //memory-region = <&di_reserved>; + memory-region = <&di_cma_reserved>; + interrupts = <0 46 1 + 0 40 1>; + interrupt-names = "pre_irq", "post_irq"; + clocks = <&clkc CLKID_VPU_CLKB_TMP_COMP>, + <&clkc CLKID_VPU_CLKB_COMP>; + clock-names = "vpu_clkb_tmp_composite", + "vpu_clkb_composite"; + clock-range = <334 667>; + /* buffer-size = <3621952>;(yuv422 8bit) */ + buffer-size = <4074560>;/*yuv422 fullpack*/ + /* reserve-iomap = "true"; */ + /* if enable nr10bit, set nr10bit-support to 1 */ + post-wr-support = <1>; + nr10bit-support = <1>; + nrds-enable = <1>; + pps-enable = <1>; + }; + ionvideo { + compatible = "amlogic, ionvideo"; + dev_name = "ionvideo"; + status = "okay"; + }; + + unifykey{ + compatible = "amlogic, unifykey"; + status = "ok"; + unifykey-num = <15>; + unifykey-index-0 = <&keysn_0>; + unifykey-index-1 = <&keysn_1>; + unifykey-index-2 = <&keysn_2>; + unifykey-index-3 = <&keysn_3>; + unifykey-index-4 = <&keysn_4>; + unifykey-index-5 = <&keysn_5>; + unifykey-index-6 = <&keysn_6>; + unifykey-index-7 = <&keysn_7>; + unifykey-index-8 = <&keysn_8>; + unifykey-index-9 = <&keysn_9>; + unifykey-index-10= <&keysn_10>; + unifykey-index-11= <&keysn_11>; + unifykey-index-12= <&keysn_12>; + unifykey-index-13= <&keysn_13>; + unifykey-index-14= <&keysn_14>; + + keysn_0: key_0{ + key-name = "usid"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_1:key_1{ + key-name = "mac"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_2:key_2{ + key-name = "hdcp"; + key-device = "secure"; + key-type = "sha1"; + key-permit = "read","write","del"; + }; + keysn_3:key_3{ + key-name = "secure_boot_set"; + key-device = "efuse"; + key-permit = "write"; + }; + keysn_4:key_4{ + key-name = "mac_bt"; + key-device = "normal"; + key-permit = "read","write","del"; + key-type = "mac"; + }; + keysn_5:key_5{ + key-name = "mac_wifi"; + key-device = "normal"; + key-permit = "read","write","del"; + key-type = "mac"; + }; + keysn_6:key_6{ + key-name = "hdcp2_tx"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_7:key_7{ + key-name = "hdcp2_rx"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_8:key_8{ + key-name = "widevinekeybox"; + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_9:key_9{ + key-name = "deviceid"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_10:key_10{ + key-name = "hdcp22_fw_private"; + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_11:key_11{ + key-name = "PlayReadykeybox25"; + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_12:key_12{ + key-name = "prpubkeybox";// PlayReady + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_13:key_13{ + key-name = "prprivkeybox";// PlayReady + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_14:key_14{ + key-name = "attestationkeybox";// attestation key + key-device = "secure"; + key-permit = "read","write","del"; + }; + };//End unifykey + + efusekey:efusekey{ + keynum = <4>; + key0 = <&key_0>; + key1 = <&key_1>; + key2 = <&key_2>; + key3 = <&key_3>; + key_0:key_0{ + keyname = "mac"; + offset = <0>; + size = <6>; + }; + key_1:key_1{ + keyname = "mac_bt"; + offset = <6>; + size = <6>; + }; + key_2:key_2{ + keyname = "mac_wifi"; + offset = <12>; + size = <6>; + }; + key_3:key_3{ + keyname = "usid"; + offset = <18>; + size = <16>; + }; + };//End efusekey + + amlvecm { + compatible = "amlogic, vecm"; + dev_name = "aml_vecm"; + status = "okay"; + gamma_en = <0>;/*1:enabel ;0:disable*/ + wb_en = <0>;/*1:enabel ;0:disable*/ + cm_en = <0>;/*1:enabel ;0:disable*/ + /*0: 709/601 1: bt2020*/ + tx_op_color_primary = <0>; + }; + + amdolby_vision { + compatible = "amlogic, dolby_vision_g12a"; + dev_name = "aml_amdolby_vision_driver"; + status = "okay"; + tv_mode = <0>;/*1:enabel ;0:disable*/ + }; + + /* Audio Related start */ + pdm_codec:dummy{ + #sound-dai-cells = <0>; + compatible = "amlogic, pdm_dummy_codec"; + status = "okay"; + }; + dummy_codec:dummy{ + #sound-dai-cells = <0>; + compatible = "amlogic, aml_dummy_codec"; + status = "okay"; + }; + amlogic_codec:t9015{ + #sound-dai-cells = <0>; + compatible = "amlogic, aml_codec_T9015"; + reg = <0xFF632000 0x2000>; + is_auge_used = <1>; /* meson or auge chipset used */ + tdmout_index = <1>; + status = "okay"; + }; + audio_effect:eqdrc{ + /*eq_enable = <1>;*/ + /*drc_enable = <1>;*/ + /* + * 0:tdmout_a + * 1:tdmout_b + * 2:tdmout_c + * 3:spdifout + * 4:spdifout_b + */ + eqdrc_module = <1>; + /* max 0xf, each bit for one lane, usually one lane */ + lane_mask = <0x1>; + /* max 0xff, each bit for one channel */ + channel_mask = <0x3>; + }; + auge_sound { + compatible = "amlogic, g12a-sound-card"; + aml-audio-card,name = "AML-AUGESOUND"; + + aml-audio-card,loopback = <&aml_loopback>; + aml-audio-card,aux-devs = <&amlogic_codec>; + /*avout mute gpio*/ + avout_mute-gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_HIGH>; + /*for audio effect ,eqdrc */ + aml-audio-card,effect = <&audio_effect>; + + aml-audio-card,dai-link@0 { + format = "dsp_a"; + mclk-fs = <512>; + //continuous-clock; + //bitclock-inversion; + //frame-inversion; + //bitclock-master = <&tdmacodec>; + //frame-master = <&tdmacodec>; + tdmacpu: cpu { + sound-dai = <&aml_tdma>; + dai-tdm-slot-tx-mask = + <1 1 1 1 1 1 1 1>; + dai-tdm-slot-rx-mask = + <1 1 1 1 1 1 1 1>; + dai-tdm-slot-num = <8>; + dai-tdm-slot-width = <32>; + system-clock-frequency = <24576000>; + }; + tdmacodec: codec { + sound-dai = <&dummy_codec &dummy_codec>; + }; + }; + + aml-audio-card,dai-link@1 { + format = "i2s";// "dsp_a"; + mclk-fs = <256>; + //continuous-clock; + //bitclock-inversion; + //frame-inversion; + bitclock-master = <&aml_tdmb>; + frame-master = <&aml_tdmb>; + //bitclock-master = <&tdmbcodec>; + //frame-master = <&tdmbcodec>; + cpu { + sound-dai = <&aml_tdmb>; + dai-tdm-slot-tx-mask = <1 1>; + dai-tdm-slot-rx-mask = <1 1>; + dai-tdm-slot-num = <2>; + /* + * dai-tdm-slot-tx-mask = + * <1 1 1 1 1 1 1 1>; + * dai-tdm-slot-rx-mask = + * <1 1 1 1 1 1 1 1>; + * dai-tdm-slot-num = <8>; + */ + dai-tdm-slot-width = <32>; + system-clock-frequency = <12288000>; + }; + tdmbcodec: codec { + sound-dai = <&dummy_codec &dummy_codec + &amlogic_codec /*&ad82584f_62*/>; + }; + }; + + aml-audio-card,dai-link@2 { + format = "i2s"; + mclk-fs = <256>; + //continuous-clock; + //bitclock-inversion; + //frame-inversion; + bitclock-master = <&aml_tdmc>; + frame-master = <&aml_tdmc>; + cpu { + sound-dai = <&aml_tdmc>; + dai-tdm-slot-tx-mask = <1 1>; + dai-tdm-slot-rx-mask = <1 1>; + dai-tdm-slot-num = <2>; + dai-tdm-slot-width = <32>; + system-clock-frequency = <12288000>; + }; + codec { + sound-dai = <&dummy_codec &dummy_codec>; + }; + }; + + aml-audio-card,dai-link@3 { + mclk-fs = <64>; + cpu { + sound-dai = <&aml_pdm>; + }; + codec { + sound-dai = <&pdm_codec>; + }; + }; + + aml-audio-card,dai-link@4 { + mclk-fs = <128>; + cpu { + sound-dai = <&aml_spdif>; + system-clock-frequency = <6144000>; + }; + codec { + sound-dai = <&dummy_codec>; + }; + }; + aml-audio-card,dai-link@5 { + mclk-fs = <128>; + cpu { + sound-dai = <&aml_spdif_b>; + system-clock-frequency = <6144000>; + }; + codec { + sound-dai = <&dummy_codec>; + }; + }; + }; + audiolocker: locker { + compatible = "amlogic, audiolocker"; + clocks = <&clkaudio CLKID_AUDIO_LOCKER_OUT + &clkaudio CLKID_AUDIO_LOCKER_IN + &clkaudio CLKID_AUDIO_MCLK_D + &clkaudio CLKID_AUDIO_MCLK_E + &clkc CLKID_MPLL1 + &clkc CLKID_MPLL2>; + clock-names = "lock_out", "lock_in", "out_src", + "in_src", "out_calc", "in_ref"; + interrupts = ; + interrupt-names = "irq"; + frequency = <49000000>; /* pll */ + dividor = <49>; /* locker's parent */ + status = "okay"; + }; + /* Audio Related end */ + + /*DCDC for MP8756GD*/ + cpu_opp_table0: cpu_opp_table0 { + compatible = "operating-points-v2"; + opp-shared; + + opp00 { + opp-hz = /bits/ 64 <100000000>; + opp-microvolt = <731000>; + }; + opp01 { + opp-hz = /bits/ 64 <250000000>; + opp-microvolt = <731000>; + }; + opp02 { + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <731000>; + }; + opp03 { + opp-hz = /bits/ 64 <667000000>; + opp-microvolt = <731000>; + }; + opp04 { + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <731000>; + }; + opp05 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <761000>; + }; + opp06 { + opp-hz = /bits/ 64 <1398000000>; + opp-microvolt = <791000>; + }; + opp07 { + opp-hz = /bits/ 64 <1512000000>; + opp-microvolt = <831000>; + }; + opp08 { + opp-hz = /bits/ 64 <1608000000>; + opp-microvolt = <871000>; + }; + opp09 { + opp-hz = /bits/ 64 <1704000000>; + opp-microvolt = <921000>; + }; + opp10 { + opp-hz = /bits/ 64 <1800000000>; + opp-microvolt = <981000>; + }; + }; + + cpufreq-meson { + compatible = "amlogic, cpufreq-meson"; + pinctrl-names = "default"; + pinctrl-0 = <&pwm_ao_d_pins3>; + status = "okay"; + }; + +}; /* end of / */ + +&meson_fb { + status = "okay"; + display_size_default = <1920 1080 1920 2160 32>; + mem_size = <0x00800000 0x1980000 0x100000 0x100000 0x800000>; + logo_addr = "0x7f800000"; + mem_alloc = <1>; + pxp_mode = <0>; /** 0:normal mode 1:pxp mode */ +}; + +&i2c0 { + status = "okay"; + pinctrl-names="default"; + pinctrl-0=<&i2c0_master_pins2>; + clock-frequency = <400000>; + + gt9xx@5d { + compatible = "goodix,gt9xx"; + status = "disabled"; + reg = <0x5d>; + reset-gpio = <&gpio GPIOZ_9 0x00>; + irq-gpio = <&gpio GPIOZ_3 0x00>; + }; + + ftxx@38 { + compatible = "focaltech,fts"; + status = "disabled"; + reg = <0x38>; + reset-gpio = <&gpio GPIOZ_9 0x00>; + irq-gpio = <&gpio GPIOZ_3 0x00>; + x_max = <600>; + y_max = <1024>; + max-touch-number = <10>; + }; +}; + +&i2c3 { + status = "okay"; + pinctrl-names="default"; + pinctrl-0=<&i2c3_master_pins2>; + clock-frequency = <100000>; /* default 100k */ + + /* for ref board */ + ad82584f_62: ad82584f_62@62 { + compatible = "ESMT, ad82584f"; + #sound-dai-cells = <0>; + reg = <0x31>; + status = "okay"; + reset_pin = <&gpio GPIOA_5 0>; + }; + + tas5707_36: tas5707_36@36 { + compatible = "ti,tas5707"; + #sound-dai-cells = <0>; + reg = <0x1b>; + status = "disabled"; + reset_pin = <&gpio GPIOA_5 0>; + }; + + bl_extern_i2c { + compatible = "amlogic, bl_extern_i2c"; + status = "disabled"; + reg = <0x2c>; /*reg_address for lp8556*/ + dev_name = "lp8556"; + }; + + lcd_extern_i2c0: lcd_extern_i2c@0 { + compatible = "lcd_ext, i2c"; + dev_name = "i2c_LT8912_0"; + reg = <0x48>; + status = "disabled"; + }; + + lcd_extern_i2c1: lcd_extern_i2c@1 { + compatible = "lcd_ext, i2c"; + dev_name = "i2c_LT8912_1"; + reg = <0x49>; + status = "disabled"; + }; +}; + +&audiobus { + aml_tdma: tdma { + compatible = "amlogic, g12a-snd-tdma"; + #sound-dai-cells = <0>; + dai-tdm-lane-slot-mask-in = <0 1>; + dai-tdm-oe-lane-slot-mask-out = <1 0>; + dai-tdm-clk-sel = <0>; + clocks = <&clkaudio CLKID_AUDIO_MCLK_A + &clkc CLKID_MPLL0>; + clock-names = "mclk", "clk_srcpll"; + pinctrl-names = "tdm_pins"; + pinctrl-0 = <&tdmout_a &tdmin_a>; + }; + + aml_tdmb: tdmb { + compatible = "amlogic, g12a-snd-tdmb"; + #sound-dai-cells = <0>; + dai-tdm-lane-slot-mask-in = <0 1 0 0>; + dai-tdm-lane-slot-mask-out = <1 0 0 0>; + dai-tdm-clk-sel = <1>; + clocks = <&clkaudio CLKID_AUDIO_MCLK_B + &clkc CLKID_MPLL1>; + clock-names = "mclk", "clk_srcpll"; + pinctrl-names = "tdm_pins"; + pinctrl-0 = <&tdmb_mclk &tdmout_b &tdmin_b>; + /* + * 0: tdmout_a; + * 1: tdmout_b; + * 2: tdmout_c; + * 3: spdifout; + * 4: spdifout_b; + */ + samesource_sel = <4>; + }; + + aml_tdmc: tdmc { + compatible = "amlogic, g12a-snd-tdmc"; + #sound-dai-cells = <0>; + dai-tdm-lane-slot-mask-in = <0 1 0 0>; + #dai-tdm-lane-slot-mask-out = <1 0 1 1>; + #dai-tdm-lane-oe-slot-mask-in = <0 0 0 0>; + dai-tdm-lane-oe-slot-mask-out = <1 0 0 0>; + dai-tdm-clk-sel = <2>; + clocks = <&clkaudio CLKID_AUDIO_MCLK_C + &clkc CLKID_MPLL2>; + clock-names = "mclk", "clk_srcpll"; + pinctrl-names = "tdm_pins"; + pinctrl-0 = <&tdmc_mclk &tdmout_c &tdmin_c>; + }; + + aml_spdif: spdif { + compatible = "amlogic, g12a-snd-spdif-a"; + #sound-dai-cells = <0>; + clocks = <&clkc CLKID_MPLL0 + &clkc CLKID_FCLK_DIV4 + &clkaudio CLKID_AUDIO_SPDIFIN + &clkaudio CLKID_AUDIO_SPDIFOUT + &clkaudio CLKID_AUDIO_SPDIFIN_CTRL + &clkaudio CLKID_AUDIO_SPDIFOUT_CTRL>; + clock-names = "sysclk", "fixed_clk", "gate_spdifin", + "gate_spdifout", "clk_spdifin", "clk_spdifout"; + interrupts = + ; + + interrupt-names = "irq_spdifin"; + pinctrl-names = "spdif_pins"; + pinctrl-0 = <&spdifout &spdifin>; + status = "okay"; + }; + aml_spdif_b: spdif_b { + compatible = "amlogic, g12a-snd-spdif-b"; + #sound-dai-cells = <0>; + clocks = <&clkc CLKID_MPLL0 /*CLKID_HIFI_PLL*/ + &clkaudio CLKID_AUDIO_SPDIFOUTB + &clkaudio CLKID_AUDIO_SPDIFOUTB_CTRL>; + clock-names = "sysclk", + "gate_spdifout", "clk_spdifout"; + status = "okay"; + }; + aml_pdm: pdm { + compatible = "amlogic, g12a-snd-pdm"; + #sound-dai-cells = <0>; + clocks = <&clkaudio CLKID_AUDIO_PDM + &clkc CLKID_FCLK_DIV3 + &clkc CLKID_MPLL3 + &clkaudio CLKID_AUDIO_PDMIN0 + &clkaudio CLKID_AUDIO_PDMIN1>; + clock-names = "gate", + "sysclk_srcpll", + "dclk_srcpll", + "pdm_dclk", + "pdm_sysclk"; + pinctrl-names = "pdm_pins"; + pinctrl-0 = <&pdmin>; + filter_mode = <1>; /* mode 0~4, defalut:1 */ + status = "okay"; + }; + aml_loopback: loopback { + compatible = "amlogic, snd-loopback"; + /* + * 0: out rate = in data rate; + * 1: out rate = loopback data rate; + */ + lb_mode = <0>; + + /* datain src + * 0: tdmin_a; + * 1: tdmin_b; + * 2: tdmin_c; + * 3: spdifin; + * 4: pdmin; + */ + datain_src = <4>; + datain_chnum = <8>; + datain_chmask = <0x3f>; + + /* tdmin_lb src + * 0: tdmoutA + * 1: tdmoutB + * 2: tdmoutC + * 3: PAD_tdminA + * 4: PAD_tdminB + * 5: PAD_tdminC + */ + datalb_src = <2>; + datalb_chnum = <8>; + datalb_chmask = <0x3>; + + status = "okay"; + }; + + audioresample: resample { + compatible = "amlogic, g12a-resample"; + clocks = <&clkc CLKID_MPLL3 + &clkaudio CLKID_AUDIO_MCLK_F + &clkaudio CLKID_AUDIO_RESAMPLE_CTRL>; + clock-names = "resample_pll", "resample_src", "resample_clk"; + /*same with toddr_src + * TDMIN_A, 0 + * TDMIN_B, 1 + * TDMIN_C, 2 + * SPDIFIN, 3 + * PDMIN, 4 + * NONE, + * TDMIN_LB, 6 + * LOOPBACK, 7 + */ + resample_module = <4>; + status = "okay"; + }; + aml_pwrdet: pwrdet { + compatible = "amlogic, g12a-power-detect"; + + interrupts = ; + interrupt-names = "pwrdet_irq"; + + /* pwrdet source sel + * 7: loopback; + * 6: tdmin_lb; + * 5: reserved; + * 4: pdmin; + * 3: spdifin; + * 2: tdmin_c; + * 1: tdmin_b; + * 0: tdmin_a; + */ + pwrdet_src = <4>; + + hi_th = <0x70000>; + lo_th = <0x16000>; + + status = "okay"; + }; +}; /* end of audiobus */ + +&pinctrl_periphs { + tdmout_a: tdmout_a { + mux { /* GPIOX_11, GPIOX_10, GPIOX_9 */ + groups = "tdma_sclk", + "tdma_fs", + "tdma_dout0"; + function = "tdma_out"; + }; + }; + + tdmin_a: tdmin_a { + mux { /* GPIOX_8 */ + groups = "tdma_din1"; + function = "tdma_in"; + }; + }; + + tdmb_mclk: tdmb_mclk { + mux { + groups = "mclk0_a"; + function = "mclk0"; + drive-strength = <2>; + }; + }; + tdmout_b: tdmout_b { + mux { /* GPIOA_1, GPIOA_2, GPIOA_3 */ + groups = "tdmb_sclk", + "tdmb_fs", + "tdmb_dout0"; + function = "tdmb_out"; + drive-strength = <2>; + }; + }; + + tdmin_b:tdmin_b { + mux { /* GPIOA_4 */ + groups = "tdmb_din1" + /*,"tdmb_slv_sclk", "tdmb_slv_fs"*/; + function = "tdmb_in"; + drive-strength = <2>; + }; + }; + + tdmc_mclk: tdmc_mclk { + mux { /* GPIOA_11 */ + groups = "mclk1_a"; + function = "mclk1"; + }; + }; + + tdmout_c:tdmout_c { + mux { /* GPIOA_12, GPIOA_13, GPIOA_10, GPIOA_8, GPIOA_7*/ + groups = "tdmc_sclk_a", + "tdmc_fs_a", + "tdmc_dout0_a" + /*, "tdmc_dout2", + * "tdmc_dout3" + */; + function = "tdmc_out"; + }; + }; + + tdmin_c:tdmin_c { + mux { /* GPIOA_9 */ + groups = "tdmc_din1_a"; + function = "tdmc_in"; + }; + }; + + spdifin: spdifin { + mux {/* GPIOH_5 */ + groups = "spdif_in_h"; + function = "spdif_in"; + }; + }; + + /* GPIOH_4 */ + /* + * spdifout: spdifout { + * mux { + * groups = "spdif_out_h"; + * function = "spdif_out"; + * }; + *}; + */ + + pdmin: pdmin { + mux { /* gpioa_5, gpioa_6, gpioa_7, gpioa_8, gpioa_9*/ + groups = "pdm_din0_a", + /*"pdm_din1_a",*/ + "pdm_din2_a", + /*"pdm_din3_a",*/ + "pdm_dclk_a"; + function = "pdm"; + }; + }; + + bl_pwm_off_pins:bl_pwm_off_pin { + mux { + pins = "GPIOH_5"; + function = "gpio_periphs"; + output-high; + }; + }; + +}; /* end of pinctrl_periphs */ +&pinctrl_aobus { + spdifout: spdifout { + mux { /* gpiao_10 */ + groups = "spdif_out_ao"; + function = "spdif_out_ao"; + }; + }; +}; /* end of pinctrl_aobus */ + +&audio_data { + status = "okay"; +}; + +/* Audio Related End */ + +&spicc0 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&spicc0_pins_x>; + cs-gpios = <&gpio GPIOX_10 0>; +}; + +&spicc1 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&spicc1_pins>; + cs-gpios = <&gpio GPIOH_6 0>; +}; + +&pwm_ef { + status = "okay"; +}; + +&dwc3 { + status = "okay"; +}; + +&usb2_phy_v2 { + status = "okay"; + portnum = <2>; +}; + +&usb3_phy_v2 { + status = "okay"; + portnum = <0>; + otg = <1>; + gpio-vbus-power = "GPIOH_6"; + gpios = <&gpio GPIOH_6 GPIO_ACTIVE_HIGH>; +}; + +&dwc2_a { + status = "okay"; + /** 0: normal, 1: otg+dwc3 host only, 2: otg+dwc3 device only*/ + controller-type = <3>; +}; +ðmac { + status = "okay"; + pinctrl-names = "internal_eth_pins"; + pinctrl-0 = <&internal_eth_pins>; + mc_val = <0x4be04>; + + internal_phy=<1>; +}; + +&uart_A { + status = "okay"; +}; + +/*if you want to use vdin just modify status to "ok"*/ +&vdin0 { + memory-region = <&vdin0_cma_reserved>; + status = "okay"; + /*vdin write mem color depth support: + *bit0:support 8bit + *bit1:support 9bit + *bit2:support 10bit + *bit3:support 12bit + *bit4:support yuv422 10bit full pack mode (from txl new add) + */ + tv_bit_mode = <0x15>; +}; +&vdin1 { + memory-region = <&vdin1_cma_reserved>; + status = "okay"; + /*vdin write mem color depth support: + *bit0:support 8bit + *bit1:support 9bit + *bit2:support 10bit + *bit3:support 12bit + */ + tv_bit_mode = <1>; +}; + + +&sd_emmc_c { + status = "okay"; + emmc { + caps = "MMC_CAP_8_BIT_DATA", + "MMC_CAP_MMC_HIGHSPEED", + "MMC_CAP_SD_HIGHSPEED", + "MMC_CAP_NONREMOVABLE", + /* "MMC_CAP_1_8V_DDR", */ + "MMC_CAP_HW_RESET", + "MMC_CAP_ERASE", + "MMC_CAP_CMD23"; + caps2 = "MMC_CAP2_HS200"; + /*"MMC_CAP2_HS400";*/ + f_min = <400000>; + f_max = <200000000>; + }; +}; + +&sd_emmc_b1 { + status = "disabled"; + sd { + caps = "MMC_CAP_4_BIT_DATA", + "MMC_CAP_MMC_HIGHSPEED", + "MMC_CAP_SD_HIGHSPEED"; + f_min = <400000>; + f_max = <50000000>; + }; +}; + +&sd_emmc_b2 { + status = "disabled"; + sd { + caps = "MMC_CAP_4_BIT_DATA", + "MMC_CAP_MMC_HIGHSPEED", + "MMC_CAP_SD_HIGHSPEED"; + f_min = <400000>; + f_max = <50000000>; + }; + + sdio { + caps = "MMC_CAP_4_BIT_DATA", + "MMC_CAP_MMC_HIGHSPEED", + "MMC_CAP_SD_HIGHSPEED", + "MMC_CAP_NONREMOVABLE", + "MMC_CAP_UHS_SDR12", + "MMC_CAP_UHS_SDR25", + "MMC_CAP_UHS_SDR50", + "MMC_CAP_UHS_SDR104", + "MMC_PM_KEEP_POWER", + "MMC_CAP_SDIO_IRQ"; + + f_min = <400000>; + f_max = <200000000>; + }; +}; + +&sd_emmc_a { + status = "disabled"; + sdio { + caps = "MMC_CAP_4_BIT_DATA", + "MMC_CAP_MMC_HIGHSPEED", + "MMC_CAP_SD_HIGHSPEED", + "MMC_CAP_NONREMOVABLE", + "MMC_PM_KEEP_POWER", + "MMC_CAP_SDIO_IRQ"; + f_min = <400000>; + f_max = <50000000>; + }; +}; + +&nand { + status = "disabled"; + plat-names = "bootloader","nandnormal"; + plat-num = <2>; + plat-part-0 = <&bootloader>; + plat-part-1 = <&nandnormal>; + bootloader: bootloader{ + enable_pad ="ce0"; + busy_pad = "rb0"; + timming_mode = "mode5"; + bch_mode = "bch8_1k"; + t_rea = <20>; + t_rhoh = <15>; + chip_num = <1>; + part_num = <0>; + rb_detect = <1>; + }; + nandnormal: nandnormal{ + enable_pad ="ce0"; + busy_pad = "rb0"; + timming_mode = "mode5"; + bch_mode = "bch8_1k"; + plane_mode = "twoplane"; + t_rea = <20>; + t_rhoh = <15>; + chip_num = <2>; + part_num = <3>; + partition = <&nand_partitions>; + rb_detect = <1>; + }; + nand_partitions:nand_partition{ + /* + * if bl_mode is 1, tpl size was generate by + * fip_copies * fip_size which + * will not skip bad when calculating + * the partition size; + * + * if bl_mode is 0, + * tpl partition must be comment out. + */ + tpl{ + offset=<0x0 0x0>; + size=<0x0 0x0>; + }; + logo{ + offset=<0x0 0x0>; + size=<0x0 0x200000>; + }; + recovery{ + offset=<0x0 0x0>; + size=<0x0 0x1000000>; + }; + boot{ + offset=<0x0 0x0>; + size=<0x0 0x1000000>; + }; + system{ + offset=<0x0 0x0>; + size=<0x0 0x4000000>; + }; + data{ + offset=<0xffffffff 0xffffffff>; + size=<0x0 0x0>; + }; + }; +}; + +&pcie_A { + reset-gpio = <&gpio GPIOX_7 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&meson_cooldev { + status = "okay"; +}; + +&defendkey { + status = "okay"; +}; + diff --git a/arch/arm/boot/dts/amlogic/g12a_s905d2_u200.dts b/arch/arm/boot/dts/amlogic/g12a_s905d2_u200.dts index 6b99519eadf9..3b95f4c8c5d8 100644 --- a/arch/arm/boot/dts/amlogic/g12a_s905d2_u200.dts +++ b/arch/arm/boot/dts/amlogic/g12a_s905d2_u200.dts @@ -80,14 +80,14 @@ reusable; size = <0x800000>; alignment = <0x400000>; - alloc-ranges = <0x0 0x30000000>; + alloc-ranges = <0x30000000 0x50000000>; }; ion_cma_reserved:linux,ion-dev { compatible = "shared-dma-pool"; reusable; size = <0x8000000>; alignment = <0x400000>; - alloc-ranges = <0x0 0x30000000>; + alloc-ranges = <0x30000000 0x50000000>; }; //di_reserved:linux,di { //compatible = "amlogic, di-mem"; @@ -126,7 +126,7 @@ size = <0x13400000>; alignment = <0x400000>; linux,contiguous-region; - alloc-ranges = <0x0 0x30000000>; + alloc-ranges = <0x30000000 0x50000000>; }; /* codec shared reserved */ codec_mm_reserved:linux,codec_mm_reserved { diff --git a/arch/arm/boot/dts/amlogic/g12a_s905d2_u200_1g.dts b/arch/arm/boot/dts/amlogic/g12a_s905d2_u200_1g.dts index 411bd71873c9..39f49da3102a 100644 --- a/arch/arm/boot/dts/amlogic/g12a_s905d2_u200_1g.dts +++ b/arch/arm/boot/dts/amlogic/g12a_s905d2_u200_1g.dts @@ -82,6 +82,16 @@ alignment = <0x400000>; alloc-ranges = <0x3f800000 0x800000>; }; + + codec_mm_cma:linux,codec_mm_cma { + compatible = "shared-dma-pool"; + reusable; + /* ion_codec_mm max can alloc size 80M*/ + size = <0xC400000>; + alignment = <0x400000>; + linux,contiguous-region; + alloc-ranges = <0x30000000 0x10000000>; + }; ion_cma_reserved:linux,ion-dev { compatible = "shared-dma-pool"; reusable; @@ -112,6 +122,7 @@ */ size = <0x02800000>; alignment = <0x400000>; + alloc-ranges = <0x30000000 0x10000000>; }; /* POST PROCESS MANAGER */ ppmgr_reserved:linux,ppmgr { @@ -119,15 +130,6 @@ size = <0x0>; }; - codec_mm_cma:linux,codec_mm_cma { - compatible = "shared-dma-pool"; - reusable; - /* ion_codec_mm max can alloc size 80M*/ - size = <0xC400000>; - alignment = <0x400000>; - linux,contiguous-region; - alloc-ranges = <0x0 0x30000000>; - }; /* codec shared reserved */ codec_mm_reserved:linux,codec_mm_reserved { compatible = "amlogic, codec-mm-reserved"; @@ -142,6 +144,7 @@ /* 1920x1080x2x4 =16+4 M */ size = <0x04000000>; alignment = <0x400000>; + alloc-ranges = <0x0 0x30000000>; }; /* vdin1 CMA pool */ vdin1_cma_reserved:linux,vdin1_cma { @@ -150,6 +153,7 @@ /* 1920x1080x2x4 =16 M */ size = <0x04000000>; alignment = <0x400000>; + alloc-ranges = <0x0 0x30000000>; }; }; diff --git a/arch/arm/boot/dts/amlogic/g12a_s905d2_u200_buildroot.dts b/arch/arm/boot/dts/amlogic/g12a_s905d2_u200_buildroot.dts new file mode 100644 index 000000000000..cecbd8078153 --- /dev/null +++ b/arch/arm/boot/dts/amlogic/g12a_s905d2_u200_buildroot.dts @@ -0,0 +1,1374 @@ +/* + * arch/arm/boot/dts/amlogic/g12a_s905d2_u200.dts + * + * Copyright (C) 2017 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +/dts-v1/; + +#include "mesong12a.dtsi" +#include "mesong12a_skt-panel.dtsi" + +/ { + model = "Amlogic"; + compatible = "amlogic, g12a"; + interrupt-parent = <&gic>; + #address-cells = <1>; + #size-cells = <1>; + + aliases { + serial0 = &uart_AO; + serial1 = &uart_A; + serial2 = &uart_B; + serial3 = &uart_C; + serial4 = &uart_AO_B; + tsensor0 = &p_tsensor; + tsensor1 = &d_tsensor; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c_AO; + }; + + memory@00000000 { + device_type = "memory"; + linux,usable-memory = <0x100000 0x7ff00000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + /* global autoconfigured region for contiguous allocations */ + secmon_reserved:linux,secmon { + compatible = "shared-dma-pool"; + reusable; + size = <0x400000>; + alignment = <0x400000>; + alloc-ranges = <0x05000000 0x400000>; + }; + secos_reserved:linux,secos { + status = "disable"; + compatible = "amlogic, aml_secos_memory"; + reg = <0x05300000 0x2000000>; + no-map; + }; + logo_reserved:linux,meson-fb { + compatible = "shared-dma-pool"; + reusable; + size = <0x800000>; + alignment = <0x400000>; + alloc-ranges = <0x7f800000 0x800000>; + }; + ion_cma_reserved:linux,ion-dev { + compatible = "shared-dma-pool"; + reusable; + size = <0x8000000>; + alignment = <0x400000>; + }; + //di_reserved:linux,di { + //compatible = "amlogic, di-mem"; + /* buffer_size = 3621952(yuv422 8bit) */ + /* 4179008(yuv422 10bit full pack mode) */ + /** 10x3621952=34.6M(0x23) support 8bit **/ + /** 10x4736064=45.2M(0x2e) support 12bit **/ + /** 10x4179008=40M(0x28) support 10bit **/ + //size = <0x2800000>; + //no-map; + //}; + /*di CMA pool */ + di_cma_reserved:linux,di_cma { + compatible = "shared-dma-pool"; + reusable; + /* buffer_size = 3621952(yuv422 8bit) + * | 4736064(yuv422 10bit) + * | 4074560(yuv422 10bit full pack mode) + * 10x3621952=34.6M(0x23) support 8bit + * 10x4736064=45.2M(0x2e) support 12bit + * 10x4074560=40M(0x28) support 10bit + */ + size = <0x02800000>; + alignment = <0x400000>; + }; + /* POST PROCESS MANAGER */ + ppmgr_reserved:linux,ppmgr { + compatible = "shared-dma-pool"; + size = <0x0>; + }; + + codec_mm_cma:linux,codec_mm_cma { + compatible = "shared-dma-pool"; + reusable; + /* ion_codec_mm max can alloc size 80M*/ + size = <0x13400000>; + alignment = <0x400000>; + linux,contiguous-region; + }; + /* codec shared reserved */ + codec_mm_reserved:linux,codec_mm_reserved { + compatible = "amlogic, codec-mm-reserved"; + size = <0x0>; + alignment = <0x100000>; + //no-map; + }; + /* vdin0 CMA pool */ + vdin0_cma_reserved:linux,vdin0_cma { + compatible = "shared-dma-pool"; + reusable; + /* 1920x1080x2x4 =16+4 M */ + size = <0x04000000>; + alignment = <0x400000>; + }; + /* vdin1 CMA pool */ + vdin1_cma_reserved:linux,vdin1_cma { + compatible = "shared-dma-pool"; + reusable; + /* 1920x1080x2x4 =16 M */ + size = <0x04000000>; + alignment = <0x400000>; + }; + }; + + gpioleds { + compatible = "gpio-leds"; + status = "okay"; + + sys_led { + label="sys_led"; + gpios=<&gpio_ao GPIOAO_11 GPIO_ACTIVE_HIGH>; + default-state ="on"; + retain-state-suspended; + linux,default-trigger="cpu0"; + }; + }; + + cvbsout { + compatible = "amlogic, cvbsout-g12a"; + dev_name = "cvbsout"; + status = "okay"; + clocks = <&clkc CLKID_VCLK2_ENCI + &clkc CLKID_VCLK2_VENCI0 + &clkc CLKID_VCLK2_VENCI1 + &clkc CLKID_DAC_CLK>; + clock-names = "venci_top_gate", + "venci_0_gate", + "venci_1_gate", + "vdac_clk_gate"; + clk_path = <0>; + + /* performance: reg_address, reg_value */ + /* g12a */ + performance = <0x1bf0 0x9 + 0x1b56 0x333 + 0x1b12 0x8080 + 0x1b05 0xfd + 0x1c59 0xf850 + 0xffff 0x0>; /* ending flag */ + performance_sarft = <0x1bf0 0x9 + 0x1b56 0x333 + 0x1b12 0x0 + 0x1b05 0x9 + 0x1c59 0xfc48 + 0xffff 0x0>; /* ending flag */ + performance_revB_telecom = <0x1bf0 0x9 + 0x1b56 0x546 + 0x1b12 0x8080 + 0x1b05 0x9 + 0x1c59 0xf850 + 0xffff 0x0>; /* ending flag */ + }; + + bt-dev{ + compatible = "amlogic, bt-dev"; + dev_name = "bt-dev"; + status = "okay"; + gpio_reset = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>; + gpio_hostwake = <&gpio GPIOX_19 GPIO_ACTIVE_HIGH>; + }; + + wifi{ + compatible = "amlogic, aml_wifi"; + dev_name = "aml_wifi"; + status = "okay"; + interrupt_pin = <&gpio GPIOX_7 GPIO_ACTIVE_HIGH>; + irq_trigger_type = "GPIO_IRQ_LOW"; + power_on_pin = <&gpio GPIOX_6 GPIO_ACTIVE_HIGH>; + dhd_static_buf; //if use bcm wifi, config dhd_static_buf + pinctrl-names = "default"; + pinctrl-0 = <&pwm_e_pins>; + pwm_config = <&wifi_pwm_conf>; + }; + + wifi_pwm_conf:wifi_pwm_conf{ + pwm_channel1_conf { + pwms = <&pwm_ef MESON_PWM_0 30040 0>; + duty-cycle = <15020>; + times = <10>; + }; + pwm_channel2_conf { + pwms = <&pwm_ef MESON_PWM_2 30030 0>; + duty-cycle = <15015>; + times = <12>; + }; + }; + + codec_mm { + compatible = "amlogic, codec, mm"; + memory-region = <&codec_mm_cma &codec_mm_reserved>; + dev_name = "codec_mm"; + status = "okay"; + }; + + ppmgr { + compatible = "amlogic, ppmgr"; + memory-region = <&ppmgr_reserved>; + dev_name = "ppmgr"; + status = "okay"; + }; + + deinterlace { + compatible = "amlogic, deinterlace"; + status = "okay"; + /* 0:use reserved; 1:use cma; 2:use cma as reserved */ + flag_cma = <1>; + //memory-region = <&di_reserved>; + memory-region = <&di_cma_reserved>; + interrupts = <0 46 1 + 0 40 1>; + interrupt-names = "pre_irq", "post_irq"; + clocks = <&clkc CLKID_VPU_CLKB_TMP_COMP>, + <&clkc CLKID_VPU_CLKB_COMP>; + clock-names = "vpu_clkb_tmp_composite", + "vpu_clkb_composite"; + clock-range = <334 667>; + /* buffer-size = <3621952>;(yuv422 8bit) */ + buffer-size = <4074560>;/*yuv422 fullpack*/ + /* reserve-iomap = "true"; */ + /* if enable nr10bit, set nr10bit-support to 1 */ + post-wr-support = <1>; + nr10bit-support = <1>; + nrds-enable = <1>; + pps-enable = <1>; + }; + ionvideo { + compatible = "amlogic, ionvideo"; + dev_name = "ionvideo"; + status = "okay"; + }; + + gpio_keypad{ + compatible = "amlogic, gpio_keypad"; + status = "okay"; + scan_period = <20>; + key_num = <1>; + key_name = "power"; + key_code = <116>; + key-gpios = <&gpio_ao GPIOAO_3 GPIO_ACTIVE_HIGH>; + detect_mode = <0>;/*0:polling mode, 1:irq mode*/ + }; + + adc_keypad { + compatible = "amlogic, adc_keypad"; + status = "okay"; + key_name = "vol-", "vol+", "enter"; + key_num = <3>; + io-channels = <&saradc SARADC_CH2>; + io-channel-names = "key-chan-2"; + key_chan = ; + key_code = <114 115 28>; + key_val = <143 266 389>; //val=voltage/1800mV*1023 + key_tolerance = <40 40 40>; + }; + + partitions: partitions{ + parts = <14>; + part-0 = <&logo>; + part-1 = <&recovery>; + part-2 = <&misc>; + part-3 = <&dto>; + part-4 = <&cri_data>; + part-5 = <¶m>; + part-6 = <&boot>; + part-7 = <&rsv>; + part-8 = <&tee>; + part-9 = <&vendor>; + part-10 = <&odm>; + part-11 = <&system>; + part-12 = <&cache>; + part-13 = <&data>; + + logo:logo{ + pname = "logo"; + size = <0x0 0x800000>; + mask = <1>; + }; + recovery:recovery{ + pname = "recovery"; + size = <0x0 0x1800000>; + mask = <1>; + }; + misc:misc{ + pname = "misc"; + size = <0x0 0x800000>; + mask = <1>; + }; + dto:dto{ + pname = "dto"; + size = <0x0 0x800000>; + mask = <1>; + }; + cri_data:cri_data{ + pname = "cri_data"; + size = <0x0 0x800000>; + mask = <2>; + }; + rsv:rsv{ + pname = "rsv"; + size = <0x0 0x1000000>; + mask = <1>; + }; + param:param{ + pname = "param"; + size = <0x0 0x1000000>; + mask = <2>; + }; + boot:boot{ + pname = "boot"; + size = <0x0 0x1000000>; + mask = <1>; + }; + tee:tee{ + pname = "tee"; + size = <0x0 0x2000000>; + mask = <1>; + }; + vendor:vendor{ + pname = "vendor"; + size = <0x0 0x10000000>; + mask = <1>; + }; + odm:odm{ + pname = "odm"; + size = <0x0 0x10000000>; + mask = <1>; + }; + system:system{ + pname = "system"; + size = <0x0 0x80000000>; + mask = <1>; + }; + cache:cache{ + pname = "cache"; + size = <0x0 0x46000000>; + mask = <2>; + }; + data:data{ + pname = "data"; + size = <0xffffffff 0xffffffff>; + mask = <4>; + }; + }; + unifykey{ + compatible = "amlogic, unifykey"; + status = "ok"; + unifykey-num = <14>; + unifykey-index-0 = <&keysn_0>; + unifykey-index-1 = <&keysn_1>; + unifykey-index-2 = <&keysn_2>; + unifykey-index-3 = <&keysn_3>; + unifykey-index-4 = <&keysn_4>; + unifykey-index-5 = <&keysn_5>; + unifykey-index-6 = <&keysn_6>; + unifykey-index-7 = <&keysn_7>; + unifykey-index-8 = <&keysn_8>; + unifykey-index-9 = <&keysn_9>; + unifykey-index-10= <&keysn_10>; + unifykey-index-11= <&keysn_11>; + unifykey-index-12= <&keysn_12>; + unifykey-index-13= <&keysn_13>; + + keysn_0: key_0{ + key-name = "usid"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_1:key_1{ + key-name = "mac"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_2:key_2{ + key-name = "hdcp"; + key-device = "secure"; + key-type = "sha1"; + key-permit = "read","write","del"; + }; + keysn_3:key_3{ + key-name = "secure_boot_set"; + key-device = "efuse"; + key-permit = "write"; + }; + keysn_4:key_4{ + key-name = "mac_bt"; + key-device = "normal"; + key-permit = "read","write","del"; + key-type = "mac"; + }; + keysn_5:key_5{ + key-name = "mac_wifi"; + key-device = "normal"; + key-permit = "read","write","del"; + key-type = "mac"; + }; + keysn_6:key_6{ + key-name = "hdcp2_tx"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_7:key_7{ + key-name = "hdcp2_rx"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_8:key_8{ + key-name = "widevinekeybox"; + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_9:key_9{ + key-name = "deviceid"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_10:key_10{ + key-name = "hdcp22_fw_private"; + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_11:key_11{ + key-name = "PlayReadykeybox25"; + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_12:key_12{ + key-name = "prpubkeybox";// PlayReady + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_13:key_13{ + key-name = "prprivkeybox";// PlayReady + key-device = "secure"; + key-permit = "read","write","del"; + }; + };//End unifykey + + efusekey:efusekey{ + keynum = <4>; + key0 = <&key_0>; + key1 = <&key_1>; + key2 = <&key_2>; + key3 = <&key_3>; + key_0:key_0{ + keyname = "mac"; + offset = <0>; + size = <6>; + }; + key_1:key_1{ + keyname = "mac_bt"; + offset = <6>; + size = <6>; + }; + key_2:key_2{ + keyname = "mac_wifi"; + offset = <12>; + size = <6>; + }; + key_3:key_3{ + keyname = "usid"; + offset = <18>; + size = <16>; + }; + };//End efusekey + + amlvecm { + compatible = "amlogic, vecm"; + dev_name = "aml_vecm"; + status = "okay"; + gamma_en = <0>;/*1:enabel ;0:disable*/ + wb_en = <0>;/*1:enabel ;0:disable*/ + cm_en = <0>;/*1:enabel ;0:disable*/ + /*0: 709/601 1: bt2020*/ + tx_op_color_primary = <0>; + }; + + amdolby_vision { + compatible = "amlogic, dolby_vision_g12a"; + dev_name = "aml_amdolby_vision_driver"; + status = "okay"; + tv_mode = <0>;/*1:enabel ;0:disable*/ + }; + + /* Audio Related start */ + pdm_codec:dummy{ + #sound-dai-cells = <0>; + compatible = "amlogic, pdm_dummy_codec"; + status = "okay"; + }; + dummy_codec:dummy{ + #sound-dai-cells = <0>; + compatible = "amlogic, aml_dummy_codec"; + status = "okay"; + }; + amlogic_codec:t9015{ + #sound-dai-cells = <0>; + compatible = "amlogic, aml_codec_T9015"; + reg = <0xFF632000 0x2000>; + is_auge_used = <1>; /* meson or auge chipset used */ + tdmout_index = <1>; + status = "okay"; + }; + audio_effect:eqdrc{ + /*eq_enable = <1>;*/ + /*drc_enable = <1>;*/ + /* + * 0:tdmout_a + * 1:tdmout_b + * 2:tdmout_c + * 3:spdifout + * 4:spdifout_b + */ + eqdrc_module = <1>; + /* max 0xf, each bit for one lane, usually one lane */ + lane_mask = <0x1>; + /* max 0xff, each bit for one channel */ + channel_mask = <0x3>; + }; + auge_sound { + compatible = "amlogic, g12a-sound-card"; + aml-audio-card,name = "AML-AUGESOUND"; + + aml-audio-card,loopback = <&aml_loopback>; + aml-audio-card,aux-devs = <&amlogic_codec>; + /*avout mute gpio*/ + avout_mute-gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_HIGH>; + /*for audio effect ,eqdrc */ + aml-audio-card,effect = <&audio_effect>; + + aml-audio-card,dai-link@0 { + format = "dsp_a"; + mclk-fs = <512>; + //continuous-clock; + //bitclock-inversion; + //frame-inversion; + //bitclock-master = <&tdmacodec>; + //frame-master = <&tdmacodec>; + /* suffix-name, sync with android audio hal + * what's the dai link used for + */ + suffix-name = "alsaPORT-pcm"; + tdmacpu: cpu { + sound-dai = <&aml_tdma>; + dai-tdm-slot-tx-mask = + <1 1 1 1 1 1 1 1>; + dai-tdm-slot-rx-mask = + <1 1 1 1 1 1 1 1>; + dai-tdm-slot-num = <8>; + dai-tdm-slot-width = <32>; + system-clock-frequency = <24576000>; + }; + tdmacodec: codec { + sound-dai = <&dummy_codec &dummy_codec>; + }; + }; + + aml-audio-card,dai-link@1 { + format = "i2s";// "dsp_a"; + mclk-fs = <256>; + //continuous-clock; + //bitclock-inversion; + //frame-inversion; + bitclock-master = <&aml_tdmb>; + frame-master = <&aml_tdmb>; + //bitclock-master = <&tdmbcodec>; + //frame-master = <&tdmbcodec>; + /* suffix-name, sync with android audio hal + * what's the dai link used for + */ + suffix-name = "alsaPORT-i2s"; + cpu { + sound-dai = <&aml_tdmb>; + dai-tdm-slot-tx-mask = <1 1>; + dai-tdm-slot-rx-mask = <1 1>; + dai-tdm-slot-num = <2>; + /* + * dai-tdm-slot-tx-mask = + * <1 1 1 1 1 1 1 1>; + * dai-tdm-slot-rx-mask = + * <1 1 1 1 1 1 1 1>; + * dai-tdm-slot-num = <8>; + */ + dai-tdm-slot-width = <32>; + system-clock-frequency = <12288000>; + }; + tdmbcodec: codec { + sound-dai = <&dummy_codec &dummy_codec + &amlogic_codec &ad82584f_62>; + }; + }; + + aml-audio-card,dai-link@2 { + format = "i2s"; + mclk-fs = <256>; + //continuous-clock; + //bitclock-inversion; + //frame-inversion; + bitclock-master = <&aml_tdmc>; + frame-master = <&aml_tdmc>; + /* suffix-name, sync with android audio hal + * what's the dai link used for + */ + //suffix-name = "alsaPORT-tdm"; + cpu { + sound-dai = <&aml_tdmc>; + dai-tdm-slot-tx-mask = <1 1>; + dai-tdm-slot-rx-mask = <1 1>; + dai-tdm-slot-num = <2>; + dai-tdm-slot-width = <32>; + system-clock-frequency = <12288000>; + }; + codec { + sound-dai = <&tlv320adc3101_32 &dummy_codec>; + }; + }; + + aml-audio-card,dai-link@3 { + mclk-fs = <64>; + /* suffix-name, sync with android audio hal + * what's the dai link used for + */ + suffix-name = "alsaPORT-pdm"; + cpu { + sound-dai = <&aml_pdm>; + }; + codec { + sound-dai = <&pdm_codec>; + }; + }; + + aml-audio-card,dai-link@4 { + mclk-fs = <128>; + /* suffix-name, sync with android audio hal + * what's the dai link used for + */ + suffix-name = "alsaPORT-spdif"; + cpu { + sound-dai = <&aml_spdif>; + system-clock-frequency = <6144000>; + }; + codec { + sound-dai = <&dummy_codec>; + }; + }; + /* spdif_b to hdmi, only playback */ + aml-audio-card,dai-link@5 { + mclk-fs = <128>; + continuous-clock; + /* suffix-name, sync with android audio hal + * what's the dai link used for + */ + suffix-name = "alsaPORT-spdifb2hdmi"; + cpu { + sound-dai = <&aml_spdif_b>; + system-clock-frequency = <6144000>; + }; + codec { + sound-dai = <&dummy_codec>; + }; + }; + }; + audiolocker: locker { + compatible = "amlogic, audiolocker"; + clocks = <&clkaudio CLKID_AUDIO_LOCKER_OUT + &clkaudio CLKID_AUDIO_LOCKER_IN + &clkaudio CLKID_AUDIO_MCLK_D + &clkaudio CLKID_AUDIO_MCLK_E + &clkc CLKID_MPLL1 + &clkc CLKID_MPLL2>; + clock-names = "lock_out", "lock_in", "out_src", + "in_src", "out_calc", "in_ref"; + interrupts = ; + interrupt-names = "irq"; + frequency = <49000000>; /* pll */ + dividor = <49>; /* locker's parent */ + status = "okay"; + }; + /* Audio Related end */ + + /*DCDC for MP8756GD*/ + cpu_opp_table0: cpu_opp_table0 { + compatible = "operating-points-v2"; + opp-shared; + + opp00 { + opp-hz = /bits/ 64 <100000000>; + opp-microvolt = <731000>; + }; + opp01 { + opp-hz = /bits/ 64 <250000000>; + opp-microvolt = <731000>; + }; + opp02 { + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <731000>; + }; + opp03 { + opp-hz = /bits/ 64 <667000000>; + opp-microvolt = <731000>; + }; + opp04 { + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <731000>; + }; + opp05 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <731000>; + }; + opp06 { + opp-hz = /bits/ 64 <1398000000>; + opp-microvolt = <761000>; + }; + opp07 { + opp-hz = /bits/ 64 <1512000000>; + opp-microvolt = <791000>; + }; + opp08 { + opp-hz = /bits/ 64 <1608000000>; + opp-microvolt = <831000>; + }; + opp09 { + opp-hz = /bits/ 64 <1704000000>; + opp-microvolt = <861000>; + }; + opp10 { + opp-hz = /bits/ 64 <1800000000>; + opp-microvolt = <981000>; + }; + }; + + cpufreq-meson { + compatible = "amlogic, cpufreq-meson"; + pinctrl-names = "default"; + pinctrl-0 = <&pwm_ao_d_pins3>; + status = "okay"; + }; + +}; /* end of / */ + +&meson_fb { + status = "okay"; + display_size_default = <1920 1080 1920 2160 32>; + mem_size = <0x00800000 0x1980000 0x100000 0x100000 0x800000>; + logo_addr = "0x7f800000"; + mem_alloc = <1>; + pxp_mode = <0>; /** 0:normal mode 1:pxp mode */ +}; + +&pwm_AO_cd { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + pinctrl-names="default"; + pinctrl-0=<&i2c0_master_pins2>; + clock-frequency = <400000>; + + gt9xx@5d { + compatible = "goodix,gt9xx"; + status = "disabled"; + reg = <0x5d>; + reset-gpio = <&gpio GPIOZ_9 0x00>; + irq-gpio = <&gpio GPIOZ_3 0x00>; + }; + + ftxx@38 { + compatible = "focaltech,fts"; + status = "disabled"; + reg = <0x38>; + reset-gpio = <&gpio GPIOZ_9 0x00>; + irq-gpio = <&gpio GPIOZ_3 0x00>; + x_max = <600>; + y_max = <1024>; + max-touch-number = <10>; + }; +}; + +&i2c3 { + status = "okay"; + pinctrl-names="default"; + pinctrl-0=<&i2c3_master_pins2>; + clock-frequency = <100000>; /* default 100k */ + + /* for ref board */ + ad82584f_62: ad82584f_62@62 { + compatible = "ESMT, ad82584f"; + #sound-dai-cells = <0>; + reg = <0x31>; + status = "okay"; + reset_pin = <&gpio GPIOA_5 0>; + }; + + tlv320adc3101_32: tlv320adc3101_32@32 { + compatible = "ti,tlv320adc3101"; + #sound-dai-cells = <0>; + reg = <0x19>; + differential_pair = <1>; + status = "okay"; + }; + + tas5707_36: tas5707_36@36 { + compatible = "ti,tas5707"; + #sound-dai-cells = <0>; + reg = <0x1b>; + status = "disabled"; + reset_pin = <&gpio GPIOA_5 0>; + }; + + bl_extern_i2c { + compatible = "bl_extern, i2c"; + dev_name = "lp8556"; + reg = <0x2c>; + status = "disabled"; + }; +}; + +&audiobus { + aml_tdma: tdma { + compatible = "amlogic, g12a-snd-tdma"; + #sound-dai-cells = <0>; + dai-tdm-lane-slot-mask-in = <0 1>; + dai-tdm-oe-lane-slot-mask-out = <1 0>; + dai-tdm-clk-sel = <0>; + clocks = <&clkaudio CLKID_AUDIO_MCLK_A + &clkc CLKID_MPLL0>; + clock-names = "mclk", "clk_srcpll"; + pinctrl-names = "tdm_pins"; + pinctrl-0 = <&tdmout_a &tdmin_a>; + }; + + aml_tdmb: tdmb { + compatible = "amlogic, g12a-snd-tdmb"; + #sound-dai-cells = <0>; + dai-tdm-lane-slot-mask-in = <0 1 0 0>; + dai-tdm-lane-slot-mask-out = <1 0 0 0>; + dai-tdm-clk-sel = <1>; + clocks = <&clkaudio CLKID_AUDIO_MCLK_B + &clkc CLKID_MPLL1 + &clkc CLKID_MPLL0>; + clock-names = "mclk", "clk_srcpll", "samesource_sysclk"; + pinctrl-names = "tdm_pins"; + pinctrl-0 = <&tdmb_mclk &tdmout_b &tdmin_b>; + /* + * 0: tdmout_a; + * 1: tdmout_b; + * 2: tdmout_c; + * 3: spdifout; + * 4: spdifout_b; + */ + samesource_sel = <3>; + }; + + aml_tdmc: tdmc { + compatible = "amlogic, g12a-snd-tdmc"; + #sound-dai-cells = <0>; + dai-tdm-lane-slot-mask-in = <1 0 0 0>; + #dai-tdm-lane-slot-mask-out = <1 0 1 1>; + #dai-tdm-lane-oe-slot-mask-in = <0 0 0 0>; + #dai-tdm-lane-oe-slot-mask-out = <1 0 0 0>; + dai-tdm-clk-sel = <2>; + clocks = <&clkaudio CLKID_AUDIO_MCLK_C + &clkc CLKID_MPLL2>; + clock-names = "mclk", "clk_srcpll"; + pinctrl-names = "tdm_pins"; + pinctrl-0 = <&tdmc_mclk &tdmout_c &tdmin_c>; + }; + + + aml_spdif: spdif { + compatible = "amlogic, g12a-snd-spdif-a"; + #sound-dai-cells = <0>; + clocks = <&clkc CLKID_MPLL0 + &clkc CLKID_FCLK_DIV4 + &clkaudio CLKID_AUDIO_SPDIFIN + &clkaudio CLKID_AUDIO_SPDIFOUT + &clkaudio CLKID_AUDIO_SPDIFIN_CTRL + &clkaudio CLKID_AUDIO_SPDIFOUT_CTRL>; + clock-names = "sysclk", "fixed_clk", "gate_spdifin", + "gate_spdifout", "clk_spdifin", "clk_spdifout"; + interrupts = + ; + + interrupt-names = "irq_spdifin"; + pinctrl-names = "spdif_pins"; + pinctrl-0 = <&spdifout &spdifin>; + status = "okay"; + }; + aml_spdif_b: spdif_b { + compatible = "amlogic, g12a-snd-spdif-b"; + #sound-dai-cells = <0>; + clocks = <&clkc CLKID_MPLL0 /*CLKID_HIFI_PLL*/ + &clkaudio CLKID_AUDIO_SPDIFOUTB + &clkaudio CLKID_AUDIO_SPDIFOUTB_CTRL>; + clock-names = "sysclk", + "gate_spdifout", "clk_spdifout"; + status = "okay"; + }; + aml_pdm: pdm { + compatible = "amlogic, g12a-snd-pdm"; + #sound-dai-cells = <0>; + clocks = <&clkaudio CLKID_AUDIO_PDM + &clkc CLKID_FCLK_DIV3 + &clkc CLKID_MPLL3 + &clkaudio CLKID_AUDIO_PDMIN0 + &clkaudio CLKID_AUDIO_PDMIN1>; + clock-names = "gate", + "sysclk_srcpll", + "dclk_srcpll", + "pdm_dclk", + "pdm_sysclk"; + pinctrl-names = "pdm_pins"; + pinctrl-0 = <&pdmin>; + filter_mode = <1>; /* mode 0~4, defalut:1 */ + status = "okay"; + }; + aml_loopback: loopback { + compatible = "amlogic, snd-loopback"; + /* + * 0: out rate = in data rate; + * 1: out rate = loopback data rate; + */ + lb_mode = <0>; + + /* datain src + * 0: tdmin_a; + * 1: tdmin_b; + * 2: tdmin_c; + * 3: spdifin; + * 4: pdmin; + */ + datain_src = <4>; + datain_chnum = <8>; + datain_chmask = <0x3f>; + + /* tdmin_lb src + * 0: tdmoutA + * 1: tdmoutB + * 2: tdmoutC + * 3: PAD_tdminA + * 4: PAD_tdminB + * 5: PAD_tdminC + */ + datalb_src = <2>; + datalb_chnum = <8>; + datalb_chmask = <0x3>; + + status = "okay"; + }; + + audioresample: resample { + compatible = "amlogic, g12a-resample"; + clocks = <&clkc CLKID_MPLL3 + &clkaudio CLKID_AUDIO_MCLK_F + &clkaudio CLKID_AUDIO_RESAMPLE_CTRL>; + clock-names = "resample_pll", "resample_src", "resample_clk"; + /*same with toddr_src + * TDMIN_A, 0 + * TDMIN_B, 1 + * TDMIN_C, 2 + * SPDIFIN, 3 + * PDMIN, 4 + * NONE, + * TDMIN_LB, 6 + * LOOPBACK, 7 + */ + resample_module = <4>; + status = "okay"; + }; + aml_pwrdet: pwrdet { + compatible = "amlogic, g12a-power-detect"; + + interrupts = ; + interrupt-names = "pwrdet_irq"; + + /* pwrdet source sel + * 7: loopback; + * 6: tdmin_lb; + * 5: reserved; + * 4: pdmin; + * 3: spdifin; + * 2: tdmin_c; + * 1: tdmin_b; + * 0: tdmin_a; + */ + pwrdet_src = <4>; + + hi_th = <0x70000>; + lo_th = <0x16000>; + + status = "okay"; + }; +}; /* end of audiobus */ + +&pinctrl_periphs { + tdmout_a: tdmout_a { + mux { /* GPIOX_11, GPIOX_10, GPIOX_9 */ + groups = "tdma_sclk", + "tdma_fs", + "tdma_dout0"; + function = "tdma_out"; + }; + }; + + tdmin_a: tdmin_a { + mux { /* GPIOX_8 */ + groups = "tdma_din1"; + function = "tdma_in"; + }; + }; + + tdmb_mclk: tdmb_mclk { + mux { + groups = "mclk0_a"; + function = "mclk0"; + drive-strength = <2>; + }; + }; + tdmout_b: tdmout_b { + mux { /* GPIOA_1, GPIOA_2, GPIOA_3 */ + groups = "tdmb_sclk", + "tdmb_fs", + "tdmb_dout0"; + function = "tdmb_out"; + drive-strength = <2>; + }; + }; + + tdmin_b:tdmin_b { + mux { /* GPIOA_4 */ + groups = "tdmb_din1" + /*,"tdmb_slv_sclk", "tdmb_slv_fs"*/; + function = "tdmb_in"; + drive-strength = <2>; + }; + }; + + tdmc_mclk: tdmc_mclk { + mux { /* GPIOA_11 */ + groups = "mclk1_a"; + function = "mclk1"; + }; + }; + + tdmout_c:tdmout_c { + mux { /* GPIOA_12, GPIOA_13, GPIOA_8, GPIOA_7*/ + groups = "tdmc_sclk_a", + "tdmc_fs_a", + "tdmc_dout0_a" + /*, "tdmc_dout2", + * "tdmc_dout3" + */; + function = "tdmc_out"; + }; + }; + + tdmin_c:tdmin_c { + mux { /* GPIOA_10 */ + groups = "tdmc_din0_a"; + function = "tdmc_in"; + }; + }; + + spdifin: spdifin { + mux {/* GPIOH_5 */ + groups = "spdif_in_h"; + function = "spdif_in"; + }; + }; + + /* GPIOH_4 */ + /* + * spdifout: spdifout { + * mux { + * groups = "spdif_out_h"; + * function = "spdif_out"; + * }; + *}; + */ + + pdmin: pdmin { + mux { /* gpioa_5, gpioa_6, gpioa_7, gpioa_8, gpioa_9*/ + groups = "pdm_din0_a", + /*"pdm_din1_a",*/ + "pdm_din2_a", + /*"pdm_din3_a",*/ + "pdm_dclk_a"; + function = "pdm"; + }; + }; + + bl_pwm_off_pins:bl_pwm_off_pin { + mux { + pins = "GPIOH_5"; + function = "gpio_periphs"; + output-high; + }; + }; + + +}; /* end of pinctrl_periphs */ +&pinctrl_aobus { + spdifout: spdifout { + mux { /* gpiao_10 */ + groups = "spdif_out_ao"; + function = "spdif_out_ao"; + }; + }; +}; /* end of pinctrl_aobus */ + +&audio_data { + status = "okay"; +}; + +/* Audio Related End */ + +&pwm_ef { + status = "okay"; +}; + +&dwc3 { + status = "okay"; +}; + +&usb2_phy_v2 { + status = "okay"; + portnum = <2>; +}; + +&usb3_phy_v2 { + status = "okay"; + portnum = <1>; + otg = <1>; + gpio-vbus-power = "GPIOH_6"; + gpios = <&gpio GPIOH_6 GPIO_ACTIVE_HIGH>; +}; + +&dwc2_a { + status = "okay"; + /** 0: normal, 1: otg+dwc3 host only, 2: otg+dwc3 device only*/ + controller-type = <3>; +}; +ðmac { + status = "okay"; + pinctrl-names = "internal_eth_pins"; + pinctrl-0 = <&internal_eth_pins>; + mc_val = <0x4be04>; + + internal_phy=<1>; +}; + +&uart_A { + status = "okay"; +}; + +/*if you want to use vdin just modify status to "ok"*/ +&vdin0 { + memory-region = <&vdin0_cma_reserved>; + status = "okay"; + /*vdin write mem color depth support: + *bit0:support 8bit + *bit1:support 9bit + *bit2:support 10bit + *bit3:support 12bit + *bit4:support yuv422 10bit full pack mode (from txl new add) + */ + tv_bit_mode = <0x15>; +}; +&vdin1 { + memory-region = <&vdin1_cma_reserved>; + status = "okay"; + /*vdin write mem color depth support: + *bit0:support 8bit + *bit1:support 9bit + *bit2:support 10bit + *bit3:support 12bit + */ + tv_bit_mode = <1>; +}; + + +&sd_emmc_c { + status = "okay"; + emmc { + caps = "MMC_CAP_8_BIT_DATA", + "MMC_CAP_MMC_HIGHSPEED", + "MMC_CAP_SD_HIGHSPEED", + "MMC_CAP_NONREMOVABLE", + /* "MMC_CAP_1_8V_DDR", */ + "MMC_CAP_HW_RESET", + "MMC_CAP_ERASE", + "MMC_CAP_CMD23"; + caps2 = "MMC_CAP2_HS200"; + /* "MMC_CAP2_HS400";*/ + f_min = <400000>; + f_max = <200000000>; + }; +}; + +&sd_emmc_b1 { + status = "disabled"; + sd { + caps = "MMC_CAP_4_BIT_DATA", + "MMC_CAP_MMC_HIGHSPEED", + "MMC_CAP_SD_HIGHSPEED"; + f_min = <400000>; + f_max = <50000000>; + }; +}; + +&sd_emmc_b2 { + status = "disabled"; + sd { + caps = "MMC_CAP_4_BIT_DATA", + "MMC_CAP_MMC_HIGHSPEED", + "MMC_CAP_SD_HIGHSPEED"; + f_min = <400000>; + f_max = <50000000>; + }; + + sdio { + caps = "MMC_CAP_4_BIT_DATA", + "MMC_CAP_MMC_HIGHSPEED", + "MMC_CAP_SD_HIGHSPEED", + "MMC_CAP_NONREMOVABLE", + "MMC_CAP_UHS_SDR12", + "MMC_CAP_UHS_SDR25", + "MMC_CAP_UHS_SDR50", + "MMC_CAP_UHS_SDR104", + "MMC_PM_KEEP_POWER", + "MMC_CAP_SDIO_IRQ"; + + f_min = <400000>; + f_max = <200000000>; + }; +}; + +&sd_emmc_a { + status = "disabled"; + sdio { + caps = "MMC_CAP_4_BIT_DATA", + "MMC_CAP_MMC_HIGHSPEED", + "MMC_CAP_SD_HIGHSPEED", + "MMC_CAP_NONREMOVABLE", + "MMC_CAP_UHS_SDR12", + "MMC_CAP_UHS_SDR25", + "MMC_CAP_UHS_SDR50", + "MMC_CAP_UHS_SDR104", + "MMC_PM_KEEP_POWER", + "MMC_CAP_SDIO_IRQ"; + f_min = <400000>; + f_max = <200000000>; + }; +}; + +&nand { + status = "disabled"; + plat-names = "bootloader","nandnormal"; + plat-num = <2>; + plat-part-0 = <&bootloader>; + plat-part-1 = <&nandnormal>; + bootloader: bootloader{ + enable_pad ="ce0"; + busy_pad = "rb0"; + timming_mode = "mode5"; + bch_mode = "bch8_1k"; + t_rea = <20>; + t_rhoh = <15>; + chip_num = <1>; + part_num = <0>; + rb_detect = <1>; + }; + nandnormal: nandnormal{ + enable_pad ="ce0"; + busy_pad = "rb0"; + timming_mode = "mode5"; + bch_mode = "bch8_1k"; + plane_mode = "twoplane"; + t_rea = <20>; + t_rhoh = <15>; + chip_num = <2>; + part_num = <3>; + partition = <&nand_partitions>; + rb_detect = <1>; + }; + nand_partitions:nand_partition{ + /* + * if bl_mode is 1, tpl size was generate by + * fip_copies * fip_size which + * will not skip bad when calculating + * the partition size; + * + * if bl_mode is 0, + * tpl partition must be comment out. + */ + tpl{ + offset=<0x0 0x0>; + size=<0x0 0x0>; + }; + logo{ + offset=<0x0 0x0>; + size=<0x0 0x200000>; + }; + recovery{ + offset=<0x0 0x0>; + size=<0x0 0x1000000>; + }; + boot{ + offset=<0x0 0x0>; + size=<0x0 0x1000000>; + }; + system{ + offset=<0x0 0x0>; + size=<0x0 0x4000000>; + }; + data{ + offset=<0xffffffff 0xffffffff>; + size=<0x0 0x0>; + }; + }; +}; + +&pcie_A { + reset-gpio = <&gpio GPIOX_7 GPIO_ACTIVE_HIGH>; + status = "disable"; +}; + +&meson_cooldev { + status = "okay"; +}; + +&defendkey { + status = "okay"; +}; + diff --git a/arch/arm/boot/dts/amlogic/g12a_s905d2_u200_buildroot_vccktest.dts b/arch/arm/boot/dts/amlogic/g12a_s905d2_u200_buildroot_vccktest.dts new file mode 100644 index 000000000000..8815f0730bb8 --- /dev/null +++ b/arch/arm/boot/dts/amlogic/g12a_s905d2_u200_buildroot_vccktest.dts @@ -0,0 +1,1393 @@ +/* + * arch/arm/boot/dts/amlogic/g12a_s905d2_u200.dts + * + * Copyright (C) 2017 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +/dts-v1/; + +#include "mesong12a.dtsi" +#include "mesong12a_skt-panel.dtsi" + +/ { + model = "Amlogic"; + compatible = "amlogic, g12a"; + interrupt-parent = <&gic>; + #address-cells = <1>; + #size-cells = <1>; + + aliases { + serial0 = &uart_AO; + serial1 = &uart_A; + serial2 = &uart_B; + serial3 = &uart_C; + serial4 = &uart_AO_B; + tsensor0 = &p_tsensor; + tsensor1 = &d_tsensor; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c_AO; + }; + + memory@00000000 { + device_type = "memory"; + linux,usable-memory = <0x100000 0x7ff00000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + /* global autoconfigured region for contiguous allocations */ + secmon_reserved:linux,secmon { + compatible = "shared-dma-pool"; + reusable; + size = <0x400000>; + alignment = <0x400000>; + alloc-ranges = <0x05000000 0x400000>; + }; + secos_reserved:linux,secos { + status = "disable"; + compatible = "amlogic, aml_secos_memory"; + reg = <0x05300000 0x2000000>; + no-map; + }; + logo_reserved:linux,meson-fb { + compatible = "shared-dma-pool"; + reusable; + size = <0x800000>; + alignment = <0x400000>; + alloc-ranges = <0x7f800000 0x800000>; + }; + ion_cma_reserved:linux,ion-dev { + compatible = "shared-dma-pool"; + reusable; + size = <0x8000000>; + alignment = <0x400000>; + }; + //di_reserved:linux,di { + //compatible = "amlogic, di-mem"; + /* buffer_size = 3621952(yuv422 8bit) */ + /* 4179008(yuv422 10bit full pack mode) */ + /** 10x3621952=34.6M(0x23) support 8bit **/ + /** 10x4736064=45.2M(0x2e) support 12bit **/ + /** 10x4179008=40M(0x28) support 10bit **/ + //size = <0x2800000>; + //no-map; + //}; + /*di CMA pool */ + di_cma_reserved:linux,di_cma { + compatible = "shared-dma-pool"; + reusable; + /* buffer_size = 3621952(yuv422 8bit) + * | 4736064(yuv422 10bit) + * | 4074560(yuv422 10bit full pack mode) + * 10x3621952=34.6M(0x23) support 8bit + * 10x4736064=45.2M(0x2e) support 12bit + * 10x4074560=40M(0x28) support 10bit + */ + size = <0x02800000>; + alignment = <0x400000>; + }; + /* POST PROCESS MANAGER */ + ppmgr_reserved:linux,ppmgr { + compatible = "shared-dma-pool"; + size = <0x0>; + }; + + codec_mm_cma:linux,codec_mm_cma { + compatible = "shared-dma-pool"; + reusable; + /* ion_codec_mm max can alloc size 80M*/ + size = <0x13400000>; + sustainable-power = <1460>; + alignment = <0x400000>; + linux,contiguous-region; + }; + /* codec shared reserved */ + codec_mm_reserved:linux,codec_mm_reserved { + compatible = "amlogic, codec-mm-reserved"; + size = <0x0>; + alignment = <0x100000>; + //no-map; + }; + /* vdin0 CMA pool */ + vdin0_cma_reserved:linux,vdin0_cma { + compatible = "shared-dma-pool"; + reusable; + /* 1920x1080x2x4 =16+4 M */ + size = <0x04000000>; + alignment = <0x400000>; + }; + /* vdin1 CMA pool */ + vdin1_cma_reserved:linux,vdin1_cma { + compatible = "shared-dma-pool"; + reusable; + /* 1920x1080x2x4 =16 M */ + size = <0x04000000>; + alignment = <0x400000>; + }; + }; + + gpioleds { + compatible = "gpio-leds"; + status = "okay"; + + sys_led { + label="sys_led"; + gpios=<&gpio_ao GPIOAO_11 GPIO_ACTIVE_HIGH>; + default-state ="on"; + retain-state-suspended; + linux,default-trigger="cpu0"; + }; + }; + + cvbsout { + compatible = "amlogic, cvbsout-g12a"; + dev_name = "cvbsout"; + status = "okay"; + clocks = <&clkc CLKID_VCLK2_ENCI + &clkc CLKID_VCLK2_VENCI0 + &clkc CLKID_VCLK2_VENCI1 + &clkc CLKID_DAC_CLK>; + clock-names = "venci_top_gate", + "venci_0_gate", + "venci_1_gate", + "vdac_clk_gate"; + clk_path = <0>; + + /* performance: reg_address, reg_value */ + /* g12a */ + performance = <0x1bf0 0x9 + 0x1b56 0x333 + 0x1b12 0x8080 + 0x1b05 0xfd + 0x1c59 0xf850 + 0xffff 0x0>; /* ending flag */ + performance_sarft = <0x1bf0 0x9 + 0x1b56 0x333 + 0x1b12 0x0 + 0x1b05 0x9 + 0x1c59 0xfc48 + 0xffff 0x0>; /* ending flag */ + performance_revB_telecom = <0x1bf0 0x9 + 0x1b56 0x546 + 0x1b12 0x8080 + 0x1b05 0x9 + 0x1c59 0xf850 + 0xffff 0x0>; /* ending flag */ + }; + + bt-dev{ + compatible = "amlogic, bt-dev"; + dev_name = "bt-dev"; + status = "okay"; + gpio_reset = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>; + gpio_hostwake = <&gpio GPIOX_19 GPIO_ACTIVE_HIGH>; + }; + + wifi{ + compatible = "amlogic, aml_wifi"; + dev_name = "aml_wifi"; + status = "okay"; + interrupt_pin = <&gpio GPIOX_7 GPIO_ACTIVE_HIGH>; + irq_trigger_type = "GPIO_IRQ_LOW"; + power_on_pin = <&gpio GPIOX_6 GPIO_ACTIVE_HIGH>; + dhd_static_buf; //if use bcm wifi, config dhd_static_buf + pinctrl-names = "default"; + pinctrl-0 = <&pwm_e_pins>; + pwm_config = <&wifi_pwm_conf>; + }; + + wifi_pwm_conf:wifi_pwm_conf{ + pwm_channel1_conf { + pwms = <&pwm_ef MESON_PWM_0 30040 0>; + duty-cycle = <15020>; + times = <10>; + }; + pwm_channel2_conf { + pwms = <&pwm_ef MESON_PWM_2 30030 0>; + duty-cycle = <15015>; + times = <12>; + }; + }; + + codec_mm { + compatible = "amlogic, codec, mm"; + memory-region = <&codec_mm_cma &codec_mm_reserved>; + dev_name = "codec_mm"; + status = "okay"; + }; + + ppmgr { + compatible = "amlogic, ppmgr"; + memory-region = <&ppmgr_reserved>; + dev_name = "ppmgr"; + status = "okay"; + }; + + deinterlace { + compatible = "amlogic, deinterlace"; + status = "okay"; + /* 0:use reserved; 1:use cma; 2:use cma as reserved */ + flag_cma = <1>; + //memory-region = <&di_reserved>; + memory-region = <&di_cma_reserved>; + interrupts = <0 46 1 + 0 40 1>; + interrupt-names = "pre_irq", "post_irq"; + clocks = <&clkc CLKID_VPU_CLKB_TMP_COMP>, + <&clkc CLKID_VPU_CLKB_COMP>; + clock-names = "vpu_clkb_tmp_composite", + "vpu_clkb_composite"; + clock-range = <334 667>; + /* buffer-size = <3621952>;(yuv422 8bit) */ + buffer-size = <4074560>;/*yuv422 fullpack*/ + /* reserve-iomap = "true"; */ + /* if enable nr10bit, set nr10bit-support to 1 */ + post-wr-support = <1>; + nr10bit-support = <1>; + nrds-enable = <1>; + pps-enable = <1>; + }; + ionvideo { + compatible = "amlogic, ionvideo"; + dev_name = "ionvideo"; + status = "okay"; + }; + + gpio_keypad{ + compatible = "amlogic, gpio_keypad"; + status = "okay"; + scan_period = <20>; + key_num = <1>; + key_name = "power"; + key_code = <116>; + key-gpios = <&gpio_ao GPIOAO_3 GPIO_ACTIVE_HIGH>; + detect_mode = <0>;/*0:polling mode, 1:irq mode*/ + }; + + adc_keypad { + compatible = "amlogic, adc_keypad"; + status = "okay"; + key_name = "vol-", "vol+", "enter"; + key_num = <3>; + io-channels = <&saradc SARADC_CH2>; + io-channel-names = "key-chan-2"; + key_chan = ; + key_code = <114 115 28>; + key_val = <143 266 389>; //val=voltage/1800mV*1023 + key_tolerance = <40 40 40>; + }; + + partitions: partitions{ + parts = <14>; + part-0 = <&logo>; + part-1 = <&recovery>; + part-2 = <&misc>; + part-3 = <&dto>; + part-4 = <&cri_data>; + part-5 = <¶m>; + part-6 = <&boot>; + part-7 = <&rsv>; + part-8 = <&tee>; + part-9 = <&vendor>; + part-10 = <&odm>; + part-11 = <&system>; + part-12 = <&cache>; + part-13 = <&data>; + + logo:logo{ + pname = "logo"; + size = <0x0 0x800000>; + mask = <1>; + }; + recovery:recovery{ + pname = "recovery"; + size = <0x0 0x1800000>; + mask = <1>; + }; + misc:misc{ + pname = "misc"; + size = <0x0 0x800000>; + mask = <1>; + }; + dto:dto{ + pname = "dto"; + size = <0x0 0x800000>; + mask = <1>; + }; + cri_data:cri_data{ + pname = "cri_data"; + size = <0x0 0x800000>; + mask = <2>; + }; + rsv:rsv{ + pname = "rsv"; + size = <0x0 0x1000000>; + mask = <1>; + }; + param:param{ + pname = "param"; + size = <0x0 0x1000000>; + mask = <2>; + }; + boot:boot{ + pname = "boot"; + size = <0x0 0x1000000>; + mask = <1>; + }; + tee:tee{ + pname = "tee"; + size = <0x0 0x2000000>; + mask = <1>; + }; + vendor:vendor{ + pname = "vendor"; + size = <0x0 0x10000000>; + mask = <1>; + }; + odm:odm{ + pname = "odm"; + size = <0x0 0x10000000>; + mask = <1>; + }; + system:system{ + pname = "system"; + size = <0x0 0x80000000>; + mask = <1>; + }; + cache:cache{ + pname = "cache"; + size = <0x0 0x46000000>; + mask = <2>; + }; + data:data{ + pname = "data"; + size = <0xffffffff 0xffffffff>; + mask = <4>; + }; + }; + unifykey{ + compatible = "amlogic, unifykey"; + status = "ok"; + unifykey-num = <14>; + unifykey-index-0 = <&keysn_0>; + unifykey-index-1 = <&keysn_1>; + unifykey-index-2 = <&keysn_2>; + unifykey-index-3 = <&keysn_3>; + unifykey-index-4 = <&keysn_4>; + unifykey-index-5 = <&keysn_5>; + unifykey-index-6 = <&keysn_6>; + unifykey-index-7 = <&keysn_7>; + unifykey-index-8 = <&keysn_8>; + unifykey-index-9 = <&keysn_9>; + unifykey-index-10= <&keysn_10>; + unifykey-index-11= <&keysn_11>; + unifykey-index-12= <&keysn_12>; + unifykey-index-13= <&keysn_13>; + + keysn_0: key_0{ + key-name = "usid"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_1:key_1{ + key-name = "mac"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_2:key_2{ + key-name = "hdcp"; + key-device = "secure"; + key-type = "sha1"; + key-permit = "read","write","del"; + }; + keysn_3:key_3{ + key-name = "secure_boot_set"; + key-device = "efuse"; + key-permit = "write"; + }; + keysn_4:key_4{ + key-name = "mac_bt"; + key-device = "normal"; + key-permit = "read","write","del"; + key-type = "mac"; + }; + keysn_5:key_5{ + key-name = "mac_wifi"; + key-device = "normal"; + key-permit = "read","write","del"; + key-type = "mac"; + }; + keysn_6:key_6{ + key-name = "hdcp2_tx"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_7:key_7{ + key-name = "hdcp2_rx"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_8:key_8{ + key-name = "widevinekeybox"; + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_9:key_9{ + key-name = "deviceid"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_10:key_10{ + key-name = "hdcp22_fw_private"; + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_11:key_11{ + key-name = "PlayReadykeybox25"; + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_12:key_12{ + key-name = "prpubkeybox";// PlayReady + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_13:key_13{ + key-name = "prprivkeybox";// PlayReady + key-device = "secure"; + key-permit = "read","write","del"; + }; + };//End unifykey + + efusekey:efusekey{ + keynum = <4>; + key0 = <&key_0>; + key1 = <&key_1>; + key2 = <&key_2>; + key3 = <&key_3>; + key_0:key_0{ + keyname = "mac"; + offset = <0>; + size = <6>; + }; + key_1:key_1{ + keyname = "mac_bt"; + offset = <6>; + size = <6>; + }; + key_2:key_2{ + keyname = "mac_wifi"; + offset = <12>; + size = <6>; + }; + key_3:key_3{ + keyname = "usid"; + offset = <18>; + size = <16>; + }; + };//End efusekey + + amlvecm { + compatible = "amlogic, vecm"; + dev_name = "aml_vecm"; + status = "okay"; + gamma_en = <0>;/*1:enabel ;0:disable*/ + wb_en = <0>;/*1:enabel ;0:disable*/ + cm_en = <0>;/*1:enabel ;0:disable*/ + /*0: 709/601 1: bt2020*/ + tx_op_color_primary = <0>; + }; + + amdolby_vision { + compatible = "amlogic, dolby_vision_g12a"; + dev_name = "aml_amdolby_vision_driver"; + status = "okay"; + tv_mode = <0>;/*1:enabel ;0:disable*/ + }; + + /* Audio Related start */ + pdm_codec:dummy{ + #sound-dai-cells = <0>; + compatible = "amlogic, pdm_dummy_codec"; + status = "okay"; + }; + dummy_codec:dummy{ + #sound-dai-cells = <0>; + compatible = "amlogic, aml_dummy_codec"; + status = "okay"; + }; + amlogic_codec:t9015{ + #sound-dai-cells = <0>; + compatible = "amlogic, aml_codec_T9015"; + reg = <0xFF632000 0x2000>; + is_auge_used = <1>; /* meson or auge chipset used */ + tdmout_index = <1>; + status = "okay"; + }; + audio_effect:eqdrc{ + /*eq_enable = <1>;*/ + /*drc_enable = <1>;*/ + /* + * 0:tdmout_a + * 1:tdmout_b + * 2:tdmout_c + * 3:spdifout + * 4:spdifout_b + */ + eqdrc_module = <1>; + /* max 0xf, each bit for one lane, usually one lane */ + lane_mask = <0x1>; + /* max 0xff, each bit for one channel */ + channel_mask = <0x3>; + }; + auge_sound { + compatible = "amlogic, g12a-sound-card"; + aml-audio-card,name = "AML-AUGESOUND"; + + aml-audio-card,loopback = <&aml_loopback>; + aml-audio-card,aux-devs = <&amlogic_codec>; + /*avout mute gpio*/ + avout_mute-gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_HIGH>; + /*for audio effect ,eqdrc */ + aml-audio-card,effect = <&audio_effect>; + + aml-audio-card,dai-link@0 { + format = "dsp_a"; + mclk-fs = <512>; + //continuous-clock; + //bitclock-inversion; + //frame-inversion; + //bitclock-master = <&tdmacodec>; + //frame-master = <&tdmacodec>; + /* suffix-name, sync with android audio hal + * what's the dai link used for + */ + suffix-name = "alsaPORT-pcm"; + tdmacpu: cpu { + sound-dai = <&aml_tdma>; + dai-tdm-slot-tx-mask = + <1 1 1 1 1 1 1 1>; + dai-tdm-slot-rx-mask = + <1 1 1 1 1 1 1 1>; + dai-tdm-slot-num = <8>; + dai-tdm-slot-width = <32>; + system-clock-frequency = <24576000>; + }; + tdmacodec: codec { + sound-dai = <&dummy_codec &dummy_codec>; + }; + }; + + aml-audio-card,dai-link@1 { + format = "i2s";// "dsp_a"; + mclk-fs = <256>; + //continuous-clock; + //bitclock-inversion; + //frame-inversion; + bitclock-master = <&aml_tdmb>; + frame-master = <&aml_tdmb>; + //bitclock-master = <&tdmbcodec>; + //frame-master = <&tdmbcodec>; + /* suffix-name, sync with android audio hal + * what's the dai link used for + */ + suffix-name = "alsaPORT-i2s"; + cpu { + sound-dai = <&aml_tdmb>; + dai-tdm-slot-tx-mask = <1 1>; + dai-tdm-slot-rx-mask = <1 1>; + dai-tdm-slot-num = <2>; + /* + * dai-tdm-slot-tx-mask = + * <1 1 1 1 1 1 1 1>; + * dai-tdm-slot-rx-mask = + * <1 1 1 1 1 1 1 1>; + * dai-tdm-slot-num = <8>; + */ + dai-tdm-slot-width = <32>; + system-clock-frequency = <12288000>; + }; + tdmbcodec: codec { + sound-dai = <&dummy_codec &dummy_codec + &amlogic_codec &ad82584f_62>; + }; + }; + + aml-audio-card,dai-link@2 { + format = "i2s"; + mclk-fs = <256>; + //continuous-clock; + //bitclock-inversion; + //frame-inversion; + bitclock-master = <&aml_tdmc>; + frame-master = <&aml_tdmc>; + /* suffix-name, sync with android audio hal + * what's the dai link used for + */ + //suffix-name = "alsaPORT-tdm"; + cpu { + sound-dai = <&aml_tdmc>; + dai-tdm-slot-tx-mask = <1 1>; + dai-tdm-slot-rx-mask = <1 1>; + dai-tdm-slot-num = <2>; + dai-tdm-slot-width = <32>; + system-clock-frequency = <12288000>; + }; + codec { + sound-dai = <&tlv320adc3101_32 &dummy_codec>; + }; + }; + + aml-audio-card,dai-link@3 { + mclk-fs = <64>; + /* suffix-name, sync with android audio hal + * what's the dai link used for + */ + suffix-name = "alsaPORT-pdm"; + cpu { + sound-dai = <&aml_pdm>; + }; + codec { + sound-dai = <&pdm_codec>; + }; + }; + + aml-audio-card,dai-link@4 { + mclk-fs = <128>; + /* suffix-name, sync with android audio hal + * what's the dai link used for + */ + suffix-name = "alsaPORT-spdif"; + cpu { + sound-dai = <&aml_spdif>; + system-clock-frequency = <6144000>; + }; + codec { + sound-dai = <&dummy_codec>; + }; + }; + /* spdif_b to hdmi, only playback */ + aml-audio-card,dai-link@5 { + mclk-fs = <128>; + continuous-clock; + /* suffix-name, sync with android audio hal + * what's the dai link used for + */ + suffix-name = "alsaPORT-spdifb2hdmi"; + cpu { + sound-dai = <&aml_spdif_b>; + system-clock-frequency = <6144000>; + }; + codec { + sound-dai = <&dummy_codec>; + }; + }; + }; + audiolocker: locker { + compatible = "amlogic, audiolocker"; + clocks = <&clkaudio CLKID_AUDIO_LOCKER_OUT + &clkaudio CLKID_AUDIO_LOCKER_IN + &clkaudio CLKID_AUDIO_MCLK_D + &clkaudio CLKID_AUDIO_MCLK_E + &clkc CLKID_MPLL1 + &clkc CLKID_MPLL2>; + clock-names = "lock_out", "lock_in", "out_src", + "in_src", "out_calc", "in_ref"; + interrupts = ; + interrupt-names = "irq"; + frequency = <49000000>; /* pll */ + dividor = <49>; /* locker's parent */ + status = "okay"; + }; + /* Audio Related end */ + + /*DCDC for MP8756GD*/ + cpu_opp_table0: cpu_opp_table0 { + compatible = "operating-points-v2"; + opp-shared; + + opp00 { + opp-hz = /bits/ 64 <100000000>; + opp-microvolt = <731000>; + }; + opp01 { + opp-hz = /bits/ 64 <250000000>; + opp-microvolt = <731000>; + }; + opp02 { + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <731000>; + }; + opp03 { + opp-hz = /bits/ 64 <667000000>; + opp-microvolt = <731000>; + }; + opp04 { + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <731000>; + }; + opp05 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <731000>; + }; + opp06 { + opp-hz = /bits/ 64 <1398000000>; + opp-microvolt = <761000>; + }; + opp07 { + opp-hz = /bits/ 64 <1512000000>; + opp-microvolt = <791000>; + }; + opp08 { + opp-hz = /bits/ 64 <1608000000>; + opp-microvolt = <831000>; + }; + opp09 { + opp-hz = /bits/ 64 <1704000000>; + opp-microvolt = <861000>; + }; + opp10 { + opp-hz = /bits/ 64 <1800000000>; + opp-microvolt = <981000>; + }; + opp11 { + opp-hz = /bits/ 64 <1908000000>; + opp-microvolt = <1010000>; + }; + opp12 { + opp-hz = /bits/ 64 <2016000000>; + opp-microvolt = <1010000>; + }; + opp13 { + opp-hz = /bits/ 64 <2100000000>; + opp-microvolt = <1010000>; + }; + }; + + cpufreq-meson { + compatible = "amlogic, cpufreq-meson"; + pinctrl-names = "default"; + pinctrl-0 = <&pwm_ao_d_pins3>; + status = "okay"; + }; + +}; /* end of / */ + +&meson_fb { + status = "okay"; + display_size_default = <1920 1080 1920 2160 32>; + mem_size = <0x00800000 0x1980000 0x100000 0x100000 0x800000>; + logo_addr = "0x7f800000"; + mem_alloc = <1>; + pxp_mode = <0>; /** 0:normal mode 1:pxp mode */ +}; + +&pwm_AO_cd { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + pinctrl-names="default"; + pinctrl-0=<&i2c0_master_pins2>; + clock-frequency = <400000>; + + gt9xx@5d { + compatible = "goodix,gt9xx"; + status = "disabled"; + reg = <0x5d>; + reset-gpio = <&gpio GPIOZ_9 0x00>; + irq-gpio = <&gpio GPIOZ_3 0x00>; + }; + + ftxx@38 { + compatible = "focaltech,fts"; + status = "disabled"; + reg = <0x38>; + reset-gpio = <&gpio GPIOZ_9 0x00>; + irq-gpio = <&gpio GPIOZ_3 0x00>; + x_max = <600>; + y_max = <1024>; + max-touch-number = <10>; + }; +}; + +&i2c3 { + status = "okay"; + pinctrl-names="default"; + pinctrl-0=<&i2c3_master_pins2>; + clock-frequency = <100000>; /* default 100k */ + + /* for ref board */ + ad82584f_62: ad82584f_62@62 { + compatible = "ESMT, ad82584f"; + #sound-dai-cells = <0>; + reg = <0x31>; + status = "okay"; + reset_pin = <&gpio GPIOA_5 0>; + }; + + tlv320adc3101_32: tlv320adc3101_32@32 { + compatible = "ti,tlv320adc3101"; + #sound-dai-cells = <0>; + reg = <0x19>; + differential_pair = <1>; + status = "okay"; + }; + + tas5707_36: tas5707_36@36 { + compatible = "ti,tas5707"; + #sound-dai-cells = <0>; + reg = <0x1b>; + status = "disabled"; + reset_pin = <&gpio GPIOA_5 0>; + }; + + bl_extern_i2c { + compatible = "amlogic, bl_extern_i2c"; + status = "disabled"; + reg = <0x2c>; /*reg_address for lp8556*/ + dev_name = "lp8556"; + }; + lcd_extern_i2c { + compatible = "amlogic, lcd_i2c_T5800Q"; + status = "disabled"; + reg = <0x1c>; /*reg_address for i2c_T5800Q*/ + dev_name = "i2c_T5800Q"; + }; +}; + +&audiobus { + aml_tdma: tdma { + compatible = "amlogic, g12a-snd-tdma"; + #sound-dai-cells = <0>; + dai-tdm-lane-slot-mask-in = <0 1>; + dai-tdm-oe-lane-slot-mask-out = <1 0>; + dai-tdm-clk-sel = <0>; + clocks = <&clkaudio CLKID_AUDIO_MCLK_A + &clkc CLKID_MPLL0>; + clock-names = "mclk", "clk_srcpll"; + pinctrl-names = "tdm_pins"; + pinctrl-0 = <&tdmout_a &tdmin_a>; + }; + + aml_tdmb: tdmb { + compatible = "amlogic, g12a-snd-tdmb"; + #sound-dai-cells = <0>; + dai-tdm-lane-slot-mask-in = <0 1 0 0>; + dai-tdm-lane-slot-mask-out = <1 0 0 0>; + dai-tdm-clk-sel = <1>; + clocks = <&clkaudio CLKID_AUDIO_MCLK_B + &clkc CLKID_MPLL1 + &clkc CLKID_MPLL0>; + clock-names = "mclk", "clk_srcpll", "samesource_sysclk"; + pinctrl-names = "tdm_pins"; + pinctrl-0 = <&tdmb_mclk &tdmout_b &tdmin_b>; + /* + * 0: tdmout_a; + * 1: tdmout_b; + * 2: tdmout_c; + * 3: spdifout; + * 4: spdifout_b; + */ + samesource_sel = <3>; + }; + + aml_tdmc: tdmc { + compatible = "amlogic, g12a-snd-tdmc"; + #sound-dai-cells = <0>; + dai-tdm-lane-slot-mask-in = <1 0 0 0>; + #dai-tdm-lane-slot-mask-out = <1 0 1 1>; + #dai-tdm-lane-oe-slot-mask-in = <0 0 0 0>; + #dai-tdm-lane-oe-slot-mask-out = <1 0 0 0>; + dai-tdm-clk-sel = <2>; + clocks = <&clkaudio CLKID_AUDIO_MCLK_C + &clkc CLKID_MPLL2>; + clock-names = "mclk", "clk_srcpll"; + pinctrl-names = "tdm_pins"; + pinctrl-0 = <&tdmc_mclk &tdmout_c &tdmin_c>; + }; + + + aml_spdif: spdif { + compatible = "amlogic, g12a-snd-spdif-a"; + #sound-dai-cells = <0>; + clocks = <&clkc CLKID_MPLL0 + &clkc CLKID_FCLK_DIV4 + &clkaudio CLKID_AUDIO_SPDIFIN + &clkaudio CLKID_AUDIO_SPDIFOUT + &clkaudio CLKID_AUDIO_SPDIFIN_CTRL + &clkaudio CLKID_AUDIO_SPDIFOUT_CTRL>; + clock-names = "sysclk", "fixed_clk", "gate_spdifin", + "gate_spdifout", "clk_spdifin", "clk_spdifout"; + interrupts = + ; + + interrupt-names = "irq_spdifin"; + pinctrl-names = "spdif_pins"; + pinctrl-0 = <&spdifout &spdifin>; + status = "okay"; + }; + aml_spdif_b: spdif_b { + compatible = "amlogic, g12a-snd-spdif-b"; + #sound-dai-cells = <0>; + clocks = <&clkc CLKID_MPLL0 /*CLKID_HIFI_PLL*/ + &clkaudio CLKID_AUDIO_SPDIFOUTB + &clkaudio CLKID_AUDIO_SPDIFOUTB_CTRL>; + clock-names = "sysclk", + "gate_spdifout", "clk_spdifout"; + status = "okay"; + }; + aml_pdm: pdm { + compatible = "amlogic, g12a-snd-pdm"; + #sound-dai-cells = <0>; + clocks = <&clkaudio CLKID_AUDIO_PDM + &clkc CLKID_FCLK_DIV3 + &clkc CLKID_MPLL3 + &clkaudio CLKID_AUDIO_PDMIN0 + &clkaudio CLKID_AUDIO_PDMIN1>; + clock-names = "gate", + "sysclk_srcpll", + "dclk_srcpll", + "pdm_dclk", + "pdm_sysclk"; + pinctrl-names = "pdm_pins"; + pinctrl-0 = <&pdmin>; + filter_mode = <1>; /* mode 0~4, defalut:1 */ + status = "okay"; + }; + aml_loopback: loopback { + compatible = "amlogic, snd-loopback"; + /* + * 0: out rate = in data rate; + * 1: out rate = loopback data rate; + */ + lb_mode = <0>; + + /* datain src + * 0: tdmin_a; + * 1: tdmin_b; + * 2: tdmin_c; + * 3: spdifin; + * 4: pdmin; + */ + datain_src = <4>; + datain_chnum = <8>; + datain_chmask = <0x3f>; + + /* tdmin_lb src + * 0: tdmoutA + * 1: tdmoutB + * 2: tdmoutC + * 3: PAD_tdminA + * 4: PAD_tdminB + * 5: PAD_tdminC + */ + datalb_src = <2>; + datalb_chnum = <8>; + datalb_chmask = <0x3>; + + status = "okay"; + }; + + audioresample: resample { + compatible = "amlogic, g12a-resample"; + clocks = <&clkc CLKID_MPLL3 + &clkaudio CLKID_AUDIO_MCLK_F + &clkaudio CLKID_AUDIO_RESAMPLE_CTRL>; + clock-names = "resample_pll", "resample_src", "resample_clk"; + /*same with toddr_src + * TDMIN_A, 0 + * TDMIN_B, 1 + * TDMIN_C, 2 + * SPDIFIN, 3 + * PDMIN, 4 + * NONE, + * TDMIN_LB, 6 + * LOOPBACK, 7 + */ + resample_module = <4>; + status = "okay"; + }; + aml_pwrdet: pwrdet { + compatible = "amlogic, g12a-power-detect"; + + interrupts = ; + interrupt-names = "pwrdet_irq"; + + /* pwrdet source sel + * 7: loopback; + * 6: tdmin_lb; + * 5: reserved; + * 4: pdmin; + * 3: spdifin; + * 2: tdmin_c; + * 1: tdmin_b; + * 0: tdmin_a; + */ + pwrdet_src = <4>; + + hi_th = <0x70000>; + lo_th = <0x16000>; + + status = "okay"; + }; +}; /* end of audiobus */ + +&pinctrl_periphs { + tdmout_a: tdmout_a { + mux { /* GPIOX_11, GPIOX_10, GPIOX_9 */ + groups = "tdma_sclk", + "tdma_fs", + "tdma_dout0"; + function = "tdma_out"; + }; + }; + + tdmin_a: tdmin_a { + mux { /* GPIOX_8 */ + groups = "tdma_din1"; + function = "tdma_in"; + }; + }; + + tdmb_mclk: tdmb_mclk { + mux { + groups = "mclk0_a"; + function = "mclk0"; + drive-strength = <2>; + }; + }; + tdmout_b: tdmout_b { + mux { /* GPIOA_1, GPIOA_2, GPIOA_3 */ + groups = "tdmb_sclk", + "tdmb_fs", + "tdmb_dout0"; + function = "tdmb_out"; + drive-strength = <2>; + }; + }; + + tdmin_b:tdmin_b { + mux { /* GPIOA_4 */ + groups = "tdmb_din1" + /*,"tdmb_slv_sclk", "tdmb_slv_fs"*/; + function = "tdmb_in"; + drive-strength = <2>; + }; + }; + + tdmc_mclk: tdmc_mclk { + mux { /* GPIOA_11 */ + groups = "mclk1_a"; + function = "mclk1"; + }; + }; + + tdmout_c:tdmout_c { + mux { /* GPIOA_12, GPIOA_13, GPIOA_8, GPIOA_7*/ + groups = "tdmc_sclk_a", + "tdmc_fs_a", + "tdmc_dout0_a" + /*, "tdmc_dout2", + * "tdmc_dout3" + */; + function = "tdmc_out"; + }; + }; + + tdmin_c:tdmin_c { + mux { /* GPIOA_10 */ + groups = "tdmc_din0_a"; + function = "tdmc_in"; + }; + }; + + spdifin: spdifin { + mux {/* GPIOH_5 */ + groups = "spdif_in_h"; + function = "spdif_in"; + }; + }; + + /* GPIOH_4 */ + /* + * spdifout: spdifout { + * mux { + * groups = "spdif_out_h"; + * function = "spdif_out"; + * }; + *}; + */ + + pdmin: pdmin { + mux { /* gpioa_5, gpioa_6, gpioa_7, gpioa_8, gpioa_9*/ + groups = "pdm_din0_a", + /*"pdm_din1_a",*/ + "pdm_din2_a", + /*"pdm_din3_a",*/ + "pdm_dclk_a"; + function = "pdm"; + }; + }; + + bl_pwm_off_pins:bl_pwm_off_pin { + mux { + pins = "GPIOH_5"; + function = "gpio_periphs"; + output-high; + }; + }; + + +}; /* end of pinctrl_periphs */ +&pinctrl_aobus { + spdifout: spdifout { + mux { /* gpiao_10 */ + groups = "spdif_out_ao"; + function = "spdif_out_ao"; + }; + }; +}; /* end of pinctrl_aobus */ + +&audio_data { + status = "okay"; +}; + +/* Audio Related End */ + +&pwm_ef { + status = "okay"; +}; + +&dwc3 { + status = "okay"; +}; + +&usb2_phy_v2 { + status = "okay"; + portnum = <2>; +}; + +&usb3_phy_v2 { + status = "okay"; + portnum = <1>; + otg = <1>; + gpio-vbus-power = "GPIOH_6"; + gpios = <&gpio GPIOH_6 GPIO_ACTIVE_HIGH>; +}; + +&dwc2_a { + status = "okay"; + /** 0: normal, 1: otg+dwc3 host only, 2: otg+dwc3 device only*/ + controller-type = <3>; +}; +ðmac { + status = "okay"; + pinctrl-names = "internal_eth_pins"; + pinctrl-0 = <&internal_eth_pins>; + mc_val = <0x4be04>; + + internal_phy=<1>; +}; + +&uart_A { + status = "okay"; +}; + +/*if you want to use vdin just modify status to "ok"*/ +&vdin0 { + memory-region = <&vdin0_cma_reserved>; + status = "okay"; + /*vdin write mem color depth support: + *bit0:support 8bit + *bit1:support 9bit + *bit2:support 10bit + *bit3:support 12bit + *bit4:support yuv422 10bit full pack mode (from txl new add) + */ + tv_bit_mode = <0x15>; +}; +&vdin1 { + memory-region = <&vdin1_cma_reserved>; + status = "okay"; + /*vdin write mem color depth support: + *bit0:support 8bit + *bit1:support 9bit + *bit2:support 10bit + *bit3:support 12bit + */ + tv_bit_mode = <1>; +}; + + +&sd_emmc_c { + status = "okay"; + emmc { + caps = "MMC_CAP_8_BIT_DATA", + "MMC_CAP_MMC_HIGHSPEED", + "MMC_CAP_SD_HIGHSPEED", + "MMC_CAP_NONREMOVABLE", + /* "MMC_CAP_1_8V_DDR", */ + "MMC_CAP_HW_RESET", + "MMC_CAP_ERASE", + "MMC_CAP_CMD23"; + caps2 = "MMC_CAP2_HS200"; + /* "MMC_CAP2_HS400";*/ + f_min = <400000>; + f_max = <200000000>; + }; +}; + +&sd_emmc_b1 { + status = "disabled"; + sd { + caps = "MMC_CAP_4_BIT_DATA", + "MMC_CAP_MMC_HIGHSPEED", + "MMC_CAP_SD_HIGHSPEED"; + f_min = <400000>; + f_max = <50000000>; + }; +}; + +&sd_emmc_b2 { + status = "disabled"; + sd { + caps = "MMC_CAP_4_BIT_DATA", + "MMC_CAP_MMC_HIGHSPEED", + "MMC_CAP_SD_HIGHSPEED"; + f_min = <400000>; + f_max = <50000000>; + }; + + sdio { + caps = "MMC_CAP_4_BIT_DATA", + "MMC_CAP_MMC_HIGHSPEED", + "MMC_CAP_SD_HIGHSPEED", + "MMC_CAP_NONREMOVABLE", + "MMC_CAP_UHS_SDR12", + "MMC_CAP_UHS_SDR25", + "MMC_CAP_UHS_SDR50", + "MMC_CAP_UHS_SDR104", + "MMC_PM_KEEP_POWER", + "MMC_CAP_SDIO_IRQ"; + + f_min = <400000>; + f_max = <200000000>; + }; +}; + +&sd_emmc_a { + status = "disabled"; + sdio { + caps = "MMC_CAP_4_BIT_DATA", + "MMC_CAP_MMC_HIGHSPEED", + "MMC_CAP_SD_HIGHSPEED", + "MMC_CAP_NONREMOVABLE", + "MMC_CAP_UHS_SDR12", + "MMC_CAP_UHS_SDR25", + "MMC_CAP_UHS_SDR50", + "MMC_CAP_UHS_SDR104", + "MMC_PM_KEEP_POWER", + "MMC_CAP_SDIO_IRQ"; + f_min = <400000>; + f_max = <200000000>; + }; +}; + +&nand { + status = "disabled"; + plat-names = "bootloader","nandnormal"; + plat-num = <2>; + plat-part-0 = <&bootloader>; + plat-part-1 = <&nandnormal>; + bootloader: bootloader{ + enable_pad ="ce0"; + busy_pad = "rb0"; + timming_mode = "mode5"; + bch_mode = "bch8_1k"; + t_rea = <20>; + t_rhoh = <15>; + chip_num = <1>; + part_num = <0>; + rb_detect = <1>; + }; + nandnormal: nandnormal{ + enable_pad ="ce0"; + busy_pad = "rb0"; + timming_mode = "mode5"; + bch_mode = "bch8_1k"; + plane_mode = "twoplane"; + t_rea = <20>; + t_rhoh = <15>; + chip_num = <2>; + part_num = <3>; + partition = <&nand_partitions>; + rb_detect = <1>; + }; + nand_partitions:nand_partition{ + /* + * if bl_mode is 1, tpl size was generate by + * fip_copies * fip_size which + * will not skip bad when calculating + * the partition size; + * + * if bl_mode is 0, + * tpl partition must be comment out. + */ + tpl{ + offset=<0x0 0x0>; + size=<0x0 0x0>; + }; + logo{ + offset=<0x0 0x0>; + size=<0x0 0x200000>; + }; + recovery{ + offset=<0x0 0x0>; + size=<0x0 0x1000000>; + }; + boot{ + offset=<0x0 0x0>; + size=<0x0 0x1000000>; + }; + system{ + offset=<0x0 0x0>; + size=<0x0 0x4000000>; + }; + data{ + offset=<0xffffffff 0xffffffff>; + size=<0x0 0x0>; + }; + }; +}; + +&pcie_A { + reset-gpio = <&gpio GPIOX_7 GPIO_ACTIVE_HIGH>; + status = "disable"; +}; + +&meson_cooldev { + status = "disbaled"; +}; + +&defendkey { + status = "okay"; +}; + diff --git a/arch/arm/boot/dts/amlogic/g12a_s905d2_u200_drm_buildroot.dts b/arch/arm/boot/dts/amlogic/g12a_s905d2_u200_drm_buildroot.dts new file mode 100644 index 000000000000..9f3f0a5f0e57 --- /dev/null +++ b/arch/arm/boot/dts/amlogic/g12a_s905d2_u200_drm_buildroot.dts @@ -0,0 +1,1391 @@ +/* + * arch/arm/boot/dts/amlogic/g12a_s905d2_u200.dts + * + * Copyright (C) 2017 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +/dts-v1/; + +#include "mesong12a.dtsi" +#include "mesong12a_skt-panel.dtsi" +#include "mesong12a_drm.dtsi" + +/ { + model = "Amlogic"; + compatible = "amlogic, g12a"; + interrupt-parent = <&gic>; + #address-cells = <1>; + #size-cells = <1>; + + aliases { + serial0 = &uart_AO; + serial1 = &uart_A; + serial2 = &uart_B; + serial3 = &uart_C; + serial4 = &uart_AO_B; + tsensor0 = &p_tsensor; + tsensor1 = &d_tsensor; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c_AO; + }; + + memory@00000000 { + device_type = "memory"; + linux,usable-memory = <0x100000 0x7ff00000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + /* global autoconfigured region for contiguous allocations */ + secmon_reserved:linux,secmon { + compatible = "shared-dma-pool"; + reusable; + size = <0x400000>; + alignment = <0x400000>; + alloc-ranges = <0x05000000 0x400000>; + }; + secos_reserved:linux,secos { + status = "disable"; + compatible = "amlogic, aml_secos_memory"; + reg = <0x05300000 0x2000000>; + no-map; + }; + logo_reserved:linux,meson-fb { + compatible = "shared-dma-pool"; + reusable; + size = <0x800000>; + alignment = <0x400000>; + alloc-ranges = <0x7f800000 0x800000>; + }; + ion_cma_reserved:linux,ion-dev { + compatible = "shared-dma-pool"; + reusable; + size = <0x8000000>; + alignment = <0x400000>; + }; + //di_reserved:linux,di { + //compatible = "amlogic, di-mem"; + /* buffer_size = 3621952(yuv422 8bit) */ + /* 4179008(yuv422 10bit full pack mode) */ + /** 10x3621952=34.6M(0x23) support 8bit **/ + /** 10x4736064=45.2M(0x2e) support 12bit **/ + /** 10x4179008=40M(0x28) support 10bit **/ + //size = <0x2800000>; + //no-map; + //}; + /*di CMA pool */ + di_cma_reserved:linux,di_cma { + compatible = "shared-dma-pool"; + reusable; + /* buffer_size = 3621952(yuv422 8bit) + * | 4736064(yuv422 10bit) + * | 4074560(yuv422 10bit full pack mode) + * 10x3621952=34.6M(0x23) support 8bit + * 10x4736064=45.2M(0x2e) support 12bit + * 10x4074560=40M(0x28) support 10bit + */ + size = <0x02800000>; + alignment = <0x400000>; + }; + /* POST PROCESS MANAGER */ + ppmgr_reserved:linux,ppmgr { + compatible = "shared-dma-pool"; + size = <0x0>; + }; + + codec_mm_cma:linux,codec_mm_cma { + compatible = "shared-dma-pool"; + reusable; + /* ion_codec_mm max can alloc size 80M*/ + size = <0x13400000>; + alignment = <0x400000>; + linux,contiguous-region; + }; + /* codec shared reserved */ + codec_mm_reserved:linux,codec_mm_reserved { + compatible = "amlogic, codec-mm-reserved"; + size = <0x0>; + alignment = <0x100000>; + //no-map; + }; + /* vdin0 CMA pool */ + vdin0_cma_reserved:linux,vdin0_cma { + compatible = "shared-dma-pool"; + reusable; + /* 1920x1080x2x4 =16+4 M */ + size = <0x04000000>; + alignment = <0x400000>; + }; + /* vdin1 CMA pool */ + vdin1_cma_reserved:linux,vdin1_cma { + compatible = "shared-dma-pool"; + reusable; + /* 1920x1080x2x4 =16 M */ + size = <0x04000000>; + alignment = <0x400000>; + }; + }; + + gpioleds { + compatible = "gpio-leds"; + status = "okay"; + + sys_led { + label="sys_led"; + gpios=<&gpio_ao GPIOAO_11 GPIO_ACTIVE_HIGH>; + default-state ="on"; + retain-state-suspended; + linux,default-trigger="cpu0"; + }; + }; + + cvbsout { + compatible = "amlogic, cvbsout-g12a"; + dev_name = "cvbsout"; + status = "okay"; + clocks = <&clkc CLKID_VCLK2_ENCI + &clkc CLKID_VCLK2_VENCI0 + &clkc CLKID_VCLK2_VENCI1 + &clkc CLKID_DAC_CLK>; + clock-names = "venci_top_gate", + "venci_0_gate", + "venci_1_gate", + "vdac_clk_gate"; + clk_path = <0>; + + /* performance: reg_address, reg_value */ + /* g12a */ + performance = <0x1bf0 0x9 + 0x1b56 0x333 + 0x1b12 0x8080 + 0x1b05 0xfd + 0x1c59 0xf850 + 0xffff 0x0>; /* ending flag */ + performance_sarft = <0x1bf0 0x9 + 0x1b56 0x333 + 0x1b12 0x0 + 0x1b05 0x9 + 0x1c59 0xfc48 + 0xffff 0x0>; /* ending flag */ + performance_revB_telecom = <0x1bf0 0x9 + 0x1b56 0x546 + 0x1b12 0x8080 + 0x1b05 0x9 + 0x1c59 0xf850 + 0xffff 0x0>; /* ending flag */ + }; + + bt-dev{ + compatible = "amlogic, bt-dev"; + dev_name = "bt-dev"; + status = "okay"; + gpio_reset = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>; + gpio_hostwake = <&gpio GPIOX_19 GPIO_ACTIVE_HIGH>; + }; + + wifi{ + compatible = "amlogic, aml_wifi"; + dev_name = "aml_wifi"; + status = "okay"; + interrupt_pin = <&gpio GPIOX_7 GPIO_ACTIVE_HIGH>; + irq_trigger_type = "GPIO_IRQ_LOW"; + power_on_pin = <&gpio GPIOX_6 GPIO_ACTIVE_HIGH>; + dhd_static_buf; //if use bcm wifi, config dhd_static_buf + pinctrl-names = "default"; + pinctrl-0 = <&pwm_e_pins>; + pwm_config = <&wifi_pwm_conf>; + }; + + wifi_pwm_conf:wifi_pwm_conf{ + pwm_channel1_conf { + pwms = <&pwm_ef MESON_PWM_0 30040 0>; + duty-cycle = <15020>; + times = <10>; + }; + pwm_channel2_conf { + pwms = <&pwm_ef MESON_PWM_2 30030 0>; + duty-cycle = <15015>; + times = <12>; + }; + }; + + codec_mm { + compatible = "amlogic, codec, mm"; + memory-region = <&codec_mm_cma &codec_mm_reserved>; + dev_name = "codec_mm"; + status = "okay"; + }; + + ppmgr { + compatible = "amlogic, ppmgr"; + memory-region = <&ppmgr_reserved>; + dev_name = "ppmgr"; + status = "okay"; + }; + + deinterlace { + compatible = "amlogic, deinterlace"; + status = "okay"; + /* 0:use reserved; 1:use cma; 2:use cma as reserved */ + flag_cma = <1>; + //memory-region = <&di_reserved>; + memory-region = <&di_cma_reserved>; + interrupts = <0 46 1 + 0 40 1>; + interrupt-names = "pre_irq", "post_irq"; + clocks = <&clkc CLKID_VPU_CLKB_TMP_COMP>, + <&clkc CLKID_VPU_CLKB_COMP>; + clock-names = "vpu_clkb_tmp_composite", + "vpu_clkb_composite"; + clock-range = <334 667>; + /* buffer-size = <3621952>;(yuv422 8bit) */ + buffer-size = <4074560>;/*yuv422 fullpack*/ + /* reserve-iomap = "true"; */ + /* if enable nr10bit, set nr10bit-support to 1 */ + post-wr-support = <1>; + nr10bit-support = <1>; + nrds-enable = <1>; + pps-enable = <1>; + }; + ionvideo { + compatible = "amlogic, ionvideo"; + dev_name = "ionvideo"; + status = "okay"; + }; + + gpio_keypad{ + compatible = "amlogic, gpio_keypad"; + status = "okay"; + scan_period = <20>; + key_num = <1>; + key_name = "power"; + key_code = <116>; + key-gpios = <&gpio_ao GPIOAO_3 GPIO_ACTIVE_HIGH>; + detect_mode = <0>;/*0:polling mode, 1:irq mode*/ + }; + + adc_keypad { + compatible = "amlogic, adc_keypad"; + status = "okay"; + key_name = "vol-", "vol+", "enter"; + key_num = <3>; + io-channels = <&saradc SARADC_CH2>; + io-channel-names = "key-chan-2"; + key_chan = ; + key_code = <114 115 28>; + key_val = <143 266 389>; //val=voltage/1800mV*1023 + key_tolerance = <40 40 40>; + }; + + partitions: partitions{ + parts = <14>; + part-0 = <&logo>; + part-1 = <&recovery>; + part-2 = <&misc>; + part-3 = <&dto>; + part-4 = <&cri_data>; + part-5 = <¶m>; + part-6 = <&boot>; + part-7 = <&rsv>; + part-8 = <&tee>; + part-9 = <&vendor>; + part-10 = <&odm>; + part-11 = <&system>; + part-12 = <&cache>; + part-13 = <&data>; + + logo:logo{ + pname = "logo"; + size = <0x0 0x800000>; + mask = <1>; + }; + recovery:recovery{ + pname = "recovery"; + size = <0x0 0x1800000>; + mask = <1>; + }; + misc:misc{ + pname = "misc"; + size = <0x0 0x800000>; + mask = <1>; + }; + dto:dto{ + pname = "dto"; + size = <0x0 0x800000>; + mask = <1>; + }; + cri_data:cri_data{ + pname = "cri_data"; + size = <0x0 0x800000>; + mask = <2>; + }; + rsv:rsv{ + pname = "rsv"; + size = <0x0 0x1000000>; + mask = <1>; + }; + param:param{ + pname = "param"; + size = <0x0 0x1000000>; + mask = <2>; + }; + boot:boot{ + pname = "boot"; + size = <0x0 0x1000000>; + mask = <1>; + }; + tee:tee{ + pname = "tee"; + size = <0x0 0x2000000>; + mask = <1>; + }; + vendor:vendor{ + pname = "vendor"; + size = <0x0 0x10000000>; + mask = <1>; + }; + odm:odm{ + pname = "odm"; + size = <0x0 0x10000000>; + mask = <1>; + }; + system:system{ + pname = "system"; + size = <0x0 0x80000000>; + mask = <1>; + }; + cache:cache{ + pname = "cache"; + size = <0x0 0x46000000>; + mask = <2>; + }; + data:data{ + pname = "data"; + size = <0xffffffff 0xffffffff>; + mask = <4>; + }; + }; + unifykey{ + compatible = "amlogic, unifykey"; + status = "ok"; + unifykey-num = <14>; + unifykey-index-0 = <&keysn_0>; + unifykey-index-1 = <&keysn_1>; + unifykey-index-2 = <&keysn_2>; + unifykey-index-3 = <&keysn_3>; + unifykey-index-4 = <&keysn_4>; + unifykey-index-5 = <&keysn_5>; + unifykey-index-6 = <&keysn_6>; + unifykey-index-7 = <&keysn_7>; + unifykey-index-8 = <&keysn_8>; + unifykey-index-9 = <&keysn_9>; + unifykey-index-10= <&keysn_10>; + unifykey-index-11= <&keysn_11>; + unifykey-index-12= <&keysn_12>; + unifykey-index-13= <&keysn_13>; + + keysn_0: key_0{ + key-name = "usid"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_1:key_1{ + key-name = "mac"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_2:key_2{ + key-name = "hdcp"; + key-device = "secure"; + key-type = "sha1"; + key-permit = "read","write","del"; + }; + keysn_3:key_3{ + key-name = "secure_boot_set"; + key-device = "efuse"; + key-permit = "write"; + }; + keysn_4:key_4{ + key-name = "mac_bt"; + key-device = "normal"; + key-permit = "read","write","del"; + key-type = "mac"; + }; + keysn_5:key_5{ + key-name = "mac_wifi"; + key-device = "normal"; + key-permit = "read","write","del"; + key-type = "mac"; + }; + keysn_6:key_6{ + key-name = "hdcp2_tx"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_7:key_7{ + key-name = "hdcp2_rx"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_8:key_8{ + key-name = "widevinekeybox"; + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_9:key_9{ + key-name = "deviceid"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_10:key_10{ + key-name = "hdcp22_fw_private"; + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_11:key_11{ + key-name = "PlayReadykeybox25"; + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_12:key_12{ + key-name = "prpubkeybox";// PlayReady + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_13:key_13{ + key-name = "prprivkeybox";// PlayReady + key-device = "secure"; + key-permit = "read","write","del"; + }; + };//End unifykey + + efusekey:efusekey{ + keynum = <4>; + key0 = <&key_0>; + key1 = <&key_1>; + key2 = <&key_2>; + key3 = <&key_3>; + key_0:key_0{ + keyname = "mac"; + offset = <0>; + size = <6>; + }; + key_1:key_1{ + keyname = "mac_bt"; + offset = <6>; + size = <6>; + }; + key_2:key_2{ + keyname = "mac_wifi"; + offset = <12>; + size = <6>; + }; + key_3:key_3{ + keyname = "usid"; + offset = <18>; + size = <16>; + }; + };//End efusekey + + amlvecm { + compatible = "amlogic, vecm"; + dev_name = "aml_vecm"; + status = "okay"; + gamma_en = <0>;/*1:enabel ;0:disable*/ + wb_en = <0>;/*1:enabel ;0:disable*/ + cm_en = <0>;/*1:enabel ;0:disable*/ + /*0: 709/601 1: bt2020*/ + tx_op_color_primary = <0>; + }; + + amdolby_vision { + compatible = "amlogic, dolby_vision_g12a"; + dev_name = "aml_amdolby_vision_driver"; + status = "okay"; + tv_mode = <0>;/*1:enabel ;0:disable*/ + }; + + /* Audio Related start */ + pdm_codec:dummy{ + #sound-dai-cells = <0>; + compatible = "amlogic, pdm_dummy_codec"; + status = "okay"; + }; + dummy_codec:dummy{ + #sound-dai-cells = <0>; + compatible = "amlogic, aml_dummy_codec"; + status = "okay"; + }; + amlogic_codec:t9015{ + #sound-dai-cells = <0>; + compatible = "amlogic, aml_codec_T9015"; + reg = <0xFF632000 0x2000>; + is_auge_used = <1>; /* meson or auge chipset used */ + tdmout_index = <1>; + status = "okay"; + }; + audio_effect:eqdrc{ + /*eq_enable = <1>;*/ + /*drc_enable = <1>;*/ + /* + * 0:tdmout_a + * 1:tdmout_b + * 2:tdmout_c + * 3:spdifout + * 4:spdifout_b + */ + eqdrc_module = <1>; + /* max 0xf, each bit for one lane, usually one lane */ + lane_mask = <0x1>; + /* max 0xff, each bit for one channel */ + channel_mask = <0x3>; + }; + auge_sound { + compatible = "amlogic, g12a-sound-card"; + aml-audio-card,name = "AML-AUGESOUND"; + + aml-audio-card,loopback = <&aml_loopback>; + aml-audio-card,aux-devs = <&amlogic_codec>; + /*avout mute gpio*/ + avout_mute-gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_HIGH>; + /*for audio effect ,eqdrc */ + aml-audio-card,effect = <&audio_effect>; + + aml-audio-card,dai-link@0 { + format = "dsp_a"; + mclk-fs = <512>; + //continuous-clock; + //bitclock-inversion; + //frame-inversion; + //bitclock-master = <&tdmacodec>; + //frame-master = <&tdmacodec>; + /* suffix-name, sync with android audio hal + * what's the dai link used for + */ + suffix-name = "alsaPORT-pcm"; + tdmacpu: cpu { + sound-dai = <&aml_tdma>; + dai-tdm-slot-tx-mask = + <1 1 1 1 1 1 1 1>; + dai-tdm-slot-rx-mask = + <1 1 1 1 1 1 1 1>; + dai-tdm-slot-num = <8>; + dai-tdm-slot-width = <32>; + system-clock-frequency = <24576000>; + }; + tdmacodec: codec { + sound-dai = <&dummy_codec &dummy_codec>; + }; + }; + + aml-audio-card,dai-link@1 { + format = "i2s";// "dsp_a"; + mclk-fs = <256>; + //continuous-clock; + //bitclock-inversion; + //frame-inversion; + bitclock-master = <&aml_tdmb>; + frame-master = <&aml_tdmb>; + //bitclock-master = <&tdmbcodec>; + //frame-master = <&tdmbcodec>; + /* suffix-name, sync with android audio hal + * what's the dai link used for + */ + suffix-name = "alsaPORT-i2s"; + cpu { + sound-dai = <&aml_tdmb>; + dai-tdm-slot-tx-mask = <1 1>; + dai-tdm-slot-rx-mask = <1 1>; + dai-tdm-slot-num = <2>; + /* + * dai-tdm-slot-tx-mask = + * <1 1 1 1 1 1 1 1>; + * dai-tdm-slot-rx-mask = + * <1 1 1 1 1 1 1 1>; + * dai-tdm-slot-num = <8>; + */ + dai-tdm-slot-width = <32>; + system-clock-frequency = <12288000>; + }; + tdmbcodec: codec { + sound-dai = <&dummy_codec &dummy_codec + &amlogic_codec &ad82584f_62>; + }; + }; + + aml-audio-card,dai-link@2 { + format = "i2s"; + mclk-fs = <256>; + //continuous-clock; + //bitclock-inversion; + //frame-inversion; + bitclock-master = <&aml_tdmc>; + frame-master = <&aml_tdmc>; + /* suffix-name, sync with android audio hal + * what's the dai link used for + */ + //suffix-name = "alsaPORT-tdm"; + cpu { + sound-dai = <&aml_tdmc>; + dai-tdm-slot-tx-mask = <1 1>; + dai-tdm-slot-rx-mask = <1 1>; + dai-tdm-slot-num = <2>; + dai-tdm-slot-width = <32>; + system-clock-frequency = <12288000>; + }; + codec { + sound-dai = <&tlv320adc3101_32 &dummy_codec>; + }; + }; + + aml-audio-card,dai-link@3 { + mclk-fs = <64>; + /* suffix-name, sync with android audio hal + * what's the dai link used for + */ + suffix-name = "alsaPORT-pdm"; + cpu { + sound-dai = <&aml_pdm>; + }; + codec { + sound-dai = <&pdm_codec>; + }; + }; + + aml-audio-card,dai-link@4 { + mclk-fs = <128>; + /* suffix-name, sync with android audio hal + * what's the dai link used for + */ + suffix-name = "alsaPORT-spdif"; + cpu { + sound-dai = <&aml_spdif>; + system-clock-frequency = <6144000>; + }; + codec { + sound-dai = <&dummy_codec>; + }; + }; + /* spdif_b to hdmi, only playback */ + aml-audio-card,dai-link@5 { + mclk-fs = <128>; + continuous-clock; + /* suffix-name, sync with android audio hal + * what's the dai link used for + */ + suffix-name = "alsaPORT-spdifb2hdmi"; + cpu { + sound-dai = <&aml_spdif_b>; + system-clock-frequency = <6144000>; + }; + codec { + sound-dai = <&dummy_codec>; + }; + }; + }; + audiolocker: locker { + compatible = "amlogic, audiolocker"; + clocks = <&clkaudio CLKID_AUDIO_LOCKER_OUT + &clkaudio CLKID_AUDIO_LOCKER_IN + &clkaudio CLKID_AUDIO_MCLK_D + &clkaudio CLKID_AUDIO_MCLK_E + &clkc CLKID_MPLL1 + &clkc CLKID_MPLL2>; + clock-names = "lock_out", "lock_in", "out_src", + "in_src", "out_calc", "in_ref"; + interrupts = ; + interrupt-names = "irq"; + frequency = <49000000>; /* pll */ + dividor = <49>; /* locker's parent */ + status = "okay"; + }; + /* Audio Related end */ + + /*DCDC for MP8756GD*/ + cpu_opp_table0: cpu_opp_table0 { + compatible = "operating-points-v2"; + opp-shared; + + opp00 { + opp-hz = /bits/ 64 <100000000>; + opp-microvolt = <731000>; + }; + opp01 { + opp-hz = /bits/ 64 <250000000>; + opp-microvolt = <731000>; + }; + opp02 { + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <731000>; + }; + opp03 { + opp-hz = /bits/ 64 <667000000>; + opp-microvolt = <731000>; + }; + opp04 { + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <731000>; + }; + opp05 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <731000>; + }; + opp06 { + opp-hz = /bits/ 64 <1398000000>; + opp-microvolt = <761000>; + }; + opp07 { + opp-hz = /bits/ 64 <1512000000>; + opp-microvolt = <791000>; + }; + opp08 { + opp-hz = /bits/ 64 <1608000000>; + opp-microvolt = <831000>; + }; + opp09 { + opp-hz = /bits/ 64 <1704000000>; + opp-microvolt = <861000>; + }; + opp10 { + opp-hz = /bits/ 64 <1800000000>; + opp-microvolt = <981000>; + }; + }; + + cpufreq-meson { + compatible = "amlogic, cpufreq-meson"; + pinctrl-names = "default"; + pinctrl-0 = <&pwm_ao_d_pins3>; + status = "okay"; + }; + +}; /* end of / */ + +&meson_fb { + status = "disable"; + display_size_default = <1920 1080 1920 2160 32>; + mem_size = <0x00800000 0x1980000 0x100000 0x100000 0x800000>; + logo_addr = "0x7f800000"; + mem_alloc = <1>; + pxp_mode = <0>; /** 0:normal mode 1:pxp mode */ +}; + +&drm_vpu { + status = "okay"; + logo_addr = "0x7f800000"; +}; + +&drm_amhdmitx { + status = "okay"; + hdcp = "disabled"; +}; + +&drm_lcd { + status = "okay"; +}; + +&pwm_AO_cd { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + pinctrl-names="default"; + pinctrl-0=<&i2c0_master_pins2>; + clock-frequency = <400000>; + + gt9xx@5d { + compatible = "goodix,gt9xx"; + status = "disabled"; + reg = <0x5d>; + reset-gpio = <&gpio GPIOZ_9 0x00>; + irq-gpio = <&gpio GPIOZ_3 0x00>; + }; + + ftxx@38 { + compatible = "focaltech,fts"; + status = "disabled"; + reg = <0x38>; + reset-gpio = <&gpio GPIOZ_9 0x00>; + irq-gpio = <&gpio GPIOZ_3 0x00>; + x_max = <600>; + y_max = <1024>; + max-touch-number = <10>; + }; +}; + +&i2c3 { + status = "okay"; + pinctrl-names="default"; + pinctrl-0=<&i2c3_master_pins2>; + clock-frequency = <100000>; /* default 100k */ + + /* for ref board */ + ad82584f_62: ad82584f_62@62 { + compatible = "ESMT, ad82584f"; + #sound-dai-cells = <0>; + reg = <0x31>; + status = "okay"; + reset_pin = <&gpio GPIOA_5 0>; + }; + + tlv320adc3101_32: tlv320adc3101_32@32 { + compatible = "ti,tlv320adc3101"; + #sound-dai-cells = <0>; + reg = <0x19>; + differential_pair = <1>; + status = "okay"; + }; + + tas5707_36: tas5707_36@36 { + compatible = "ti,tas5707"; + #sound-dai-cells = <0>; + reg = <0x1b>; + status = "disabled"; + reset_pin = <&gpio GPIOA_5 0>; + }; + + bl_extern_i2c { + compatible = "bl_extern, i2c"; + dev_name = "lp8556"; + reg = <0x2c>; + status = "disabled"; + }; +}; + +&audiobus { + aml_tdma: tdma { + compatible = "amlogic, g12a-snd-tdma"; + #sound-dai-cells = <0>; + dai-tdm-lane-slot-mask-in = <0 1>; + dai-tdm-oe-lane-slot-mask-out = <1 0>; + dai-tdm-clk-sel = <0>; + clocks = <&clkaudio CLKID_AUDIO_MCLK_A + &clkc CLKID_MPLL0>; + clock-names = "mclk", "clk_srcpll"; + pinctrl-names = "tdm_pins"; + pinctrl-0 = <&tdmout_a &tdmin_a>; + }; + + aml_tdmb: tdmb { + compatible = "amlogic, g12a-snd-tdmb"; + #sound-dai-cells = <0>; + dai-tdm-lane-slot-mask-in = <0 1 0 0>; + dai-tdm-lane-slot-mask-out = <1 0 0 0>; + dai-tdm-clk-sel = <1>; + clocks = <&clkaudio CLKID_AUDIO_MCLK_B + &clkc CLKID_MPLL1 + &clkc CLKID_MPLL0>; + clock-names = "mclk", "clk_srcpll", "samesource_sysclk"; + pinctrl-names = "tdm_pins"; + pinctrl-0 = <&tdmb_mclk &tdmout_b &tdmin_b>; + /* + * 0: tdmout_a; + * 1: tdmout_b; + * 2: tdmout_c; + * 3: spdifout; + * 4: spdifout_b; + */ + samesource_sel = <3>; + }; + + aml_tdmc: tdmc { + compatible = "amlogic, g12a-snd-tdmc"; + #sound-dai-cells = <0>; + dai-tdm-lane-slot-mask-in = <1 0 0 0>; + #dai-tdm-lane-slot-mask-out = <1 0 1 1>; + #dai-tdm-lane-oe-slot-mask-in = <0 0 0 0>; + #dai-tdm-lane-oe-slot-mask-out = <1 0 0 0>; + dai-tdm-clk-sel = <2>; + clocks = <&clkaudio CLKID_AUDIO_MCLK_C + &clkc CLKID_MPLL2>; + clock-names = "mclk", "clk_srcpll"; + pinctrl-names = "tdm_pins"; + pinctrl-0 = <&tdmc_mclk &tdmout_c &tdmin_c>; + }; + + + aml_spdif: spdif { + compatible = "amlogic, g12a-snd-spdif-a"; + #sound-dai-cells = <0>; + clocks = <&clkc CLKID_MPLL0 + &clkc CLKID_FCLK_DIV4 + &clkaudio CLKID_AUDIO_SPDIFIN + &clkaudio CLKID_AUDIO_SPDIFOUT + &clkaudio CLKID_AUDIO_SPDIFIN_CTRL + &clkaudio CLKID_AUDIO_SPDIFOUT_CTRL>; + clock-names = "sysclk", "fixed_clk", "gate_spdifin", + "gate_spdifout", "clk_spdifin", "clk_spdifout"; + interrupts = + ; + + interrupt-names = "irq_spdifin"; + pinctrl-names = "spdif_pins"; + pinctrl-0 = <&spdifout &spdifin>; + status = "okay"; + }; + aml_spdif_b: spdif_b { + compatible = "amlogic, g12a-snd-spdif-b"; + #sound-dai-cells = <0>; + clocks = <&clkc CLKID_MPLL0 /*CLKID_HIFI_PLL*/ + &clkaudio CLKID_AUDIO_SPDIFOUTB + &clkaudio CLKID_AUDIO_SPDIFOUTB_CTRL>; + clock-names = "sysclk", + "gate_spdifout", "clk_spdifout"; + status = "okay"; + }; + aml_pdm: pdm { + compatible = "amlogic, g12a-snd-pdm"; + #sound-dai-cells = <0>; + clocks = <&clkaudio CLKID_AUDIO_PDM + &clkc CLKID_FCLK_DIV3 + &clkc CLKID_MPLL3 + &clkaudio CLKID_AUDIO_PDMIN0 + &clkaudio CLKID_AUDIO_PDMIN1>; + clock-names = "gate", + "sysclk_srcpll", + "dclk_srcpll", + "pdm_dclk", + "pdm_sysclk"; + pinctrl-names = "pdm_pins"; + pinctrl-0 = <&pdmin>; + filter_mode = <1>; /* mode 0~4, defalut:1 */ + status = "okay"; + }; + aml_loopback: loopback { + compatible = "amlogic, snd-loopback"; + /* + * 0: out rate = in data rate; + * 1: out rate = loopback data rate; + */ + lb_mode = <0>; + + /* datain src + * 0: tdmin_a; + * 1: tdmin_b; + * 2: tdmin_c; + * 3: spdifin; + * 4: pdmin; + */ + datain_src = <4>; + datain_chnum = <8>; + datain_chmask = <0x3f>; + + /* tdmin_lb src + * 0: tdmoutA + * 1: tdmoutB + * 2: tdmoutC + * 3: PAD_tdminA + * 4: PAD_tdminB + * 5: PAD_tdminC + */ + datalb_src = <2>; + datalb_chnum = <8>; + datalb_chmask = <0x3>; + + status = "okay"; + }; + + audioresample: resample { + compatible = "amlogic, g12a-resample"; + clocks = <&clkc CLKID_MPLL3 + &clkaudio CLKID_AUDIO_MCLK_F + &clkaudio CLKID_AUDIO_RESAMPLE_CTRL>; + clock-names = "resample_pll", "resample_src", "resample_clk"; + /*same with toddr_src + * TDMIN_A, 0 + * TDMIN_B, 1 + * TDMIN_C, 2 + * SPDIFIN, 3 + * PDMIN, 4 + * NONE, + * TDMIN_LB, 6 + * LOOPBACK, 7 + */ + resample_module = <4>; + status = "okay"; + }; + aml_pwrdet: pwrdet { + compatible = "amlogic, g12a-power-detect"; + + interrupts = ; + interrupt-names = "pwrdet_irq"; + + /* pwrdet source sel + * 7: loopback; + * 6: tdmin_lb; + * 5: reserved; + * 4: pdmin; + * 3: spdifin; + * 2: tdmin_c; + * 1: tdmin_b; + * 0: tdmin_a; + */ + pwrdet_src = <4>; + + hi_th = <0x70000>; + lo_th = <0x16000>; + + status = "okay"; + }; +}; /* end of audiobus */ + +&pinctrl_periphs { + tdmout_a: tdmout_a { + mux { /* GPIOX_11, GPIOX_10, GPIOX_9 */ + groups = "tdma_sclk", + "tdma_fs", + "tdma_dout0"; + function = "tdma_out"; + }; + }; + + tdmin_a: tdmin_a { + mux { /* GPIOX_8 */ + groups = "tdma_din1"; + function = "tdma_in"; + }; + }; + + tdmb_mclk: tdmb_mclk { + mux { + groups = "mclk0_a"; + function = "mclk0"; + drive-strength = <2>; + }; + }; + tdmout_b: tdmout_b { + mux { /* GPIOA_1, GPIOA_2, GPIOA_3 */ + groups = "tdmb_sclk", + "tdmb_fs", + "tdmb_dout0"; + function = "tdmb_out"; + drive-strength = <2>; + }; + }; + + tdmin_b:tdmin_b { + mux { /* GPIOA_4 */ + groups = "tdmb_din1" + /*,"tdmb_slv_sclk", "tdmb_slv_fs"*/; + function = "tdmb_in"; + drive-strength = <2>; + }; + }; + + tdmc_mclk: tdmc_mclk { + mux { /* GPIOA_11 */ + groups = "mclk1_a"; + function = "mclk1"; + }; + }; + + tdmout_c:tdmout_c { + mux { /* GPIOA_12, GPIOA_13, GPIOA_8, GPIOA_7*/ + groups = "tdmc_sclk_a", + "tdmc_fs_a", + "tdmc_dout0_a" + /*, "tdmc_dout2", + * "tdmc_dout3" + */; + function = "tdmc_out"; + }; + }; + + tdmin_c:tdmin_c { + mux { /* GPIOA_10 */ + groups = "tdmc_din0_a"; + function = "tdmc_in"; + }; + }; + + spdifin: spdifin { + mux {/* GPIOH_5 */ + groups = "spdif_in_h"; + function = "spdif_in"; + }; + }; + + /* GPIOH_4 */ + /* + * spdifout: spdifout { + * mux { + * groups = "spdif_out_h"; + * function = "spdif_out"; + * }; + *}; + */ + + pdmin: pdmin { + mux { /* gpioa_5, gpioa_6, gpioa_7, gpioa_8, gpioa_9*/ + groups = "pdm_din0_a", + /*"pdm_din1_a",*/ + "pdm_din2_a", + /*"pdm_din3_a",*/ + "pdm_dclk_a"; + function = "pdm"; + }; + }; + + bl_pwm_off_pins:bl_pwm_off_pin { + mux { + pins = "GPIOH_5"; + function = "gpio_periphs"; + output-high; + }; + }; + + +}; /* end of pinctrl_periphs */ +&pinctrl_aobus { + spdifout: spdifout { + mux { /* gpiao_10 */ + groups = "spdif_out_ao"; + function = "spdif_out_ao"; + }; + }; +}; /* end of pinctrl_aobus */ + +&audio_data { + status = "okay"; +}; + +/* Audio Related End */ + +&pwm_ef { + status = "okay"; +}; + +&dwc3 { + status = "okay"; +}; + +&usb2_phy_v2 { + status = "okay"; + portnum = <2>; +}; + +&usb3_phy_v2 { + status = "okay"; + portnum = <1>; + otg = <1>; + gpio-vbus-power = "GPIOH_6"; + gpios = <&gpio GPIOH_6 GPIO_ACTIVE_HIGH>; +}; + +&dwc2_a { + status = "okay"; + /** 0: normal, 1: otg+dwc3 host only, 2: otg+dwc3 device only*/ + controller-type = <3>; +}; +ðmac { + status = "okay"; + pinctrl-names = "internal_eth_pins"; + pinctrl-0 = <&internal_eth_pins>; + mc_val = <0x4be04>; + + internal_phy=<1>; +}; + +&uart_A { + status = "okay"; +}; + +/*if you want to use vdin just modify status to "ok"*/ +&vdin0 { + memory-region = <&vdin0_cma_reserved>; + status = "okay"; + /*vdin write mem color depth support: + *bit0:support 8bit + *bit1:support 9bit + *bit2:support 10bit + *bit3:support 12bit + *bit4:support yuv422 10bit full pack mode (from txl new add) + */ + tv_bit_mode = <0x15>; +}; +&vdin1 { + memory-region = <&vdin1_cma_reserved>; + status = "okay"; + /*vdin write mem color depth support: + *bit0:support 8bit + *bit1:support 9bit + *bit2:support 10bit + *bit3:support 12bit + */ + tv_bit_mode = <1>; +}; + + +&sd_emmc_c { + status = "okay"; + emmc { + caps = "MMC_CAP_8_BIT_DATA", + "MMC_CAP_MMC_HIGHSPEED", + "MMC_CAP_SD_HIGHSPEED", + "MMC_CAP_NONREMOVABLE", + /* "MMC_CAP_1_8V_DDR", */ + "MMC_CAP_HW_RESET", + "MMC_CAP_ERASE", + "MMC_CAP_CMD23"; + caps2 = "MMC_CAP2_HS200"; + /* "MMC_CAP2_HS400";*/ + f_min = <400000>; + f_max = <200000000>; + }; +}; + +&sd_emmc_b1 { + status = "disabled"; + sd { + caps = "MMC_CAP_4_BIT_DATA", + "MMC_CAP_MMC_HIGHSPEED", + "MMC_CAP_SD_HIGHSPEED"; + f_min = <400000>; + f_max = <50000000>; + }; +}; + +&sd_emmc_b2 { + status = "disabled"; + sd { + caps = "MMC_CAP_4_BIT_DATA", + "MMC_CAP_MMC_HIGHSPEED", + "MMC_CAP_SD_HIGHSPEED"; + + f_min = <400000>; + f_max = <50000000>; + }; + + sdio { + caps = "MMC_CAP_4_BIT_DATA", + "MMC_CAP_MMC_HIGHSPEED", + "MMC_CAP_SD_HIGHSPEED", + "MMC_CAP_NONREMOVABLE", + "MMC_CAP_UHS_SDR12", + "MMC_CAP_UHS_SDR25", + "MMC_CAP_UHS_SDR50", + "MMC_CAP_UHS_SDR104", + "MMC_PM_KEEP_POWER", + "MMC_CAP_SDIO_IRQ"; + + f_min = <400000>; + f_max = <200000000>; + }; +}; + + +&sd_emmc_a { + status = "disabled"; + sdio { + caps = "MMC_CAP_4_BIT_DATA", + "MMC_CAP_MMC_HIGHSPEED", + "MMC_CAP_SD_HIGHSPEED", + "MMC_CAP_NONREMOVABLE", + "MMC_CAP_UHS_SDR12", + "MMC_CAP_UHS_SDR25", + "MMC_CAP_UHS_SDR50", + "MMC_CAP_UHS_SDR104", + "MMC_PM_KEEP_POWER", + "MMC_CAP_SDIO_IRQ"; + f_min = <400000>; + f_max = <200000000>; + }; +}; + +&nand { + status = "disabled"; + plat-names = "bootloader","nandnormal"; + plat-num = <2>; + plat-part-0 = <&bootloader>; + plat-part-1 = <&nandnormal>; + bootloader: bootloader{ + enable_pad ="ce0"; + busy_pad = "rb0"; + timming_mode = "mode5"; + bch_mode = "bch8_1k"; + t_rea = <20>; + t_rhoh = <15>; + chip_num = <1>; + part_num = <0>; + rb_detect = <1>; + }; + nandnormal: nandnormal{ + enable_pad ="ce0"; + busy_pad = "rb0"; + timming_mode = "mode5"; + bch_mode = "bch8_1k"; + plane_mode = "twoplane"; + t_rea = <20>; + t_rhoh = <15>; + chip_num = <2>; + part_num = <3>; + partition = <&nand_partitions>; + rb_detect = <1>; + }; + nand_partitions:nand_partition{ + /* + * if bl_mode is 1, tpl size was generate by + * fip_copies * fip_size which + * will not skip bad when calculating + * the partition size; + * + * if bl_mode is 0, + * tpl partition must be comment out. + */ + tpl{ + offset=<0x0 0x0>; + size=<0x0 0x0>; + }; + logo{ + offset=<0x0 0x0>; + size=<0x0 0x200000>; + }; + recovery{ + offset=<0x0 0x0>; + size=<0x0 0x1000000>; + }; + boot{ + offset=<0x0 0x0>; + size=<0x0 0x1000000>; + }; + system{ + offset=<0x0 0x0>; + size=<0x0 0x4000000>; + }; + data{ + offset=<0xffffffff 0xffffffff>; + size=<0x0 0x0>; + }; + }; +}; + +&pcie_A { + reset-gpio = <&gpio GPIOX_7 GPIO_ACTIVE_HIGH>; + status = "disable"; +}; + +&meson_cooldev { + status = "okay"; +}; + +&defendkey { + status = "okay"; +}; + diff --git a/arch/arm/boot/dts/amlogic/g12a_s905x2_u211.dts b/arch/arm/boot/dts/amlogic/g12a_s905x2_u211.dts new file mode 100644 index 000000000000..76e20d2762dd --- /dev/null +++ b/arch/arm/boot/dts/amlogic/g12a_s905x2_u211.dts @@ -0,0 +1,1342 @@ +/* + * arch/arm/boot/dts/amlogic/g12a_s905x2_u211.dts + * + * Copyright (C) 2017 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +/dts-v1/; + +#include "mesong12a.dtsi" +#include "partition_mbox_normal.dtsi" + +/ { + model = "Amlogic"; + amlogic-dt-id = "g12a_s905x2_u211"; + compatible = "amlogic, g12a"; + interrupt-parent = <&gic>; + #address-cells = <1>; + #size-cells = <1>; + + aliases { + serial0 = &uart_AO; + serial1 = &uart_A; + serial2 = &uart_B; + serial3 = &uart_C; + serial4 = &uart_AO_B; + tsensor0 = &p_tsensor; + tsensor1 = &d_tsensor; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c_AO; + }; + + memory@00000000 { + device_type = "memory"; + linux,usable-memory = <0x100000 0x7ff00000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + /* global autoconfigured region for contiguous allocations */ + ramoops@0x07400000 { + compatible = "ramoops"; + reg = <0x07400000 0x00100000>; + record-size = <0x8000>; + console-size = <0x8000>; + ftrace-size = <0x0>; + pmsg-size = <0x8000>; + }; + + secmon_reserved:linux,secmon { + compatible = "shared-dma-pool"; + reusable; + size = <0x400000>; + alignment = <0x400000>; + alloc-ranges = <0x05000000 0x400000>; + }; + secos_reserved:linux,secos { + status = "disable"; + compatible = "amlogic, aml_secos_memory"; + reg = <0x05300000 0x2000000>; + no-map; + }; + logo_reserved:linux,meson-fb { + compatible = "shared-dma-pool"; + reusable; + size = <0x800000>; + alignment = <0x400000>; + alloc-ranges = <0x7f800000 0x800000>; + }; + ion_cma_reserved:linux,ion-dev { + compatible = "shared-dma-pool"; + reusable; + size = <0x8000000>; + alignment = <0x400000>; + }; + //di_reserved:linux,di { + //compatible = "amlogic, di-mem"; + /* buffer_size = 3621952(yuv422 8bit) */ + /* 4179008(yuv422 10bit full pack mode) */ + /** 10x3621952=34.6M(0x23) support 8bit **/ + /** 10x4736064=45.2M(0x2e) support 12bit **/ + /** 10x4179008=40M(0x28) support 10bit **/ + //size = <0x2800000>; + //no-map; + //}; + /*di CMA pool */ + di_cma_reserved:linux,di_cma { + compatible = "shared-dma-pool"; + reusable; + /* buffer_size = 3621952(yuv422 8bit) + * | 4736064(yuv422 10bit) + * | 4074560(yuv422 10bit full pack mode) + * 10x3621952=34.6M(0x23) support 8bit + * 10x4736064=45.2M(0x2e) support 12bit + * 10x4074560=40M(0x28) support 10bit + */ + size = <0x02800000>; + alignment = <0x400000>; + }; + /* POST PROCESS MANAGER */ + ppmgr_reserved:linux,ppmgr { + compatible = "shared-dma-pool"; + size = <0x0>; + }; + + codec_mm_cma:linux,codec_mm_cma { + compatible = "shared-dma-pool"; + reusable; + /* ion_codec_mm max can alloc size 80M*/ + size = <0x13400000>; + alignment = <0x400000>; + linux,contiguous-region; + }; + /* codec shared reserved */ + codec_mm_reserved:linux,codec_mm_reserved { + compatible = "amlogic, codec-mm-reserved"; + size = <0x0>; + alignment = <0x100000>; + //no-map; + }; + /* vdin0 CMA pool */ + vdin0_cma_reserved:linux,vdin0_cma { + compatible = "shared-dma-pool"; + reusable; + /* 1920x1080x2x4 =16+4 M */ + size = <0x04000000>; + alignment = <0x400000>; + }; + /* vdin1 CMA pool */ + vdin1_cma_reserved:linux,vdin1_cma { + compatible = "shared-dma-pool"; + reusable; + /* 1920x1080x2x4 =16 M */ + size = <0x04000000>; + alignment = <0x400000>; + }; + }; + + amlogic_battery:dummy-battery { + compatible = "amlogic, dummy-battery"; + status = "disabled"; + }; + + amlogic_charger:dummy-charger { + compatible = "amlogic, dummy-charger"; + status = "disabled"; + }; + + gpioleds { + compatible = "gpio-leds"; + status = "okay"; + + net_red { + label="net_red"; + gpios=<&gpio GPIOA_14 GPIO_ACTIVE_LOW>; + default-state ="on"; + }; + + net_green { + label="net_green"; + gpios=<&gpio GPIOA_15 GPIO_ACTIVE_HIGH>; + default-state ="on"; + }; + + remote_led { + label = "remote_led"; + gpios = <&gpio_ao GPIOAO_10 GPIO_ACTIVE_LOW>; + default-state = "off"; + linux,default-trigger = "rc_feedback"; + }; + + sys_led { + label="sys_led"; + gpios=<&gpio_ao GPIOAO_11 GPIO_ACTIVE_LOW>; + default-state ="on"; + retain-state-suspended; + linux,default-trigger="cpu0"; + }; + }; + + cvbsout { + compatible = "amlogic, cvbsout-g12a"; + dev_name = "cvbsout"; + status = "okay"; + clocks = <&clkc CLKID_VCLK2_ENCI + &clkc CLKID_VCLK2_VENCI0 + &clkc CLKID_VCLK2_VENCI1 + &clkc CLKID_DAC_CLK>; + clock-names = "venci_top_gate", + "venci_0_gate", + "venci_1_gate", + "vdac_clk_gate"; + clk_path = <0>; + + /* performance: reg_address, reg_value */ + /* g12a */ + performance = <0x1bf0 0x9 + 0x1b56 0x333 + 0x1b12 0x8080 + 0x1b05 0xfd + 0x1c59 0xf850 + 0xffff 0x0>; /* ending flag */ + performance_sarft = <0x1bf0 0x9 + 0x1b56 0x333 + 0x1b12 0x0 + 0x1b05 0x9 + 0x1c59 0xfc48 + 0xffff 0x0>; /* ending flag */ + performance_revB_telecom = <0x1bf0 0x9 + 0x1b56 0x546 + 0x1b12 0x8080 + 0x1b05 0x9 + 0x1c59 0xf850 + 0xffff 0x0>; /* ending flag */ + }; + + bt-dev{ + compatible = "amlogic, bt-dev"; + dev_name = "bt-dev"; + status = "okay"; + gpio_reset = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>; + gpio_hostwake = <&gpio GPIOX_19 GPIO_ACTIVE_HIGH>; + }; + + wifi{ + compatible = "amlogic, aml_wifi"; + dev_name = "aml_wifi"; + status = "okay"; + interrupt_pin = <&gpio GPIOX_7 GPIO_ACTIVE_HIGH>; + irq_trigger_type = "GPIO_IRQ_LOW"; + power_on_pin = <&gpio GPIOX_6 GPIO_ACTIVE_HIGH>; + dhd_static_buf; //if use bcm wifi, config dhd_static_buf + pinctrl-names = "default"; + pinctrl-0 = <&pwm_e_pins>; + pwm_config = <&wifi_pwm_conf>; + }; + + wifi_pwm_conf:wifi_pwm_conf{ + pwm_channel1_conf { + pwms = <&pwm_ef MESON_PWM_0 30040 0>; + duty-cycle = <15020>; + times = <10>; + }; + pwm_channel2_conf { + pwms = <&pwm_ef MESON_PWM_2 30030 0>; + duty-cycle = <15015>; + times = <12>; + }; + }; + + codec_mm { + compatible = "amlogic, codec, mm"; + memory-region = <&codec_mm_cma &codec_mm_reserved>; + dev_name = "codec_mm"; + status = "okay"; + }; + + ppmgr { + compatible = "amlogic, ppmgr"; + memory-region = <&ppmgr_reserved>; + dev_name = "ppmgr"; + status = "okay"; + }; + + deinterlace { + compatible = "amlogic, deinterlace"; + status = "okay"; + /* 0:use reserved; 1:use cma; 2:use cma as reserved */ + flag_cma = <1>; + //memory-region = <&di_reserved>; + memory-region = <&di_cma_reserved>; + interrupts = <0 46 1 + 0 40 1>; + interrupt-names = "pre_irq", "post_irq"; + clocks = <&clkc CLKID_VPU_CLKB_TMP_COMP>, + <&clkc CLKID_VPU_CLKB_COMP>; + clock-names = "vpu_clkb_tmp_composite", + "vpu_clkb_composite"; + clock-range = <334 667>; + /* buffer-size = <3621952>;(yuv422 8bit) */ + buffer-size = <4074560>;/*yuv422 fullpack*/ + /* reserve-iomap = "true"; */ + /* if enable nr10bit, set nr10bit-support to 1 */ + post-wr-support = <1>; + nr10bit-support = <1>; + nrds-enable = <1>; + pps-enable = <1>; + }; + ionvideo { + compatible = "amlogic, ionvideo"; + dev_name = "ionvideo"; + status = "okay"; + }; + dvb{ + compatible = "amlogic, dvb"; + dev_name = "dvb"; + status = "ok"; + /*"parallel","serial","disable"*/ + ts2 = "parallel"; + ts2_control = <0>; + ts2_invert = <0>; + }; + unifykey{ + compatible = "amlogic, unifykey"; + status = "ok"; + unifykey-num = <15>; + unifykey-index-0 = <&keysn_0>; + unifykey-index-1 = <&keysn_1>; + unifykey-index-2 = <&keysn_2>; + unifykey-index-3 = <&keysn_3>; + unifykey-index-4 = <&keysn_4>; + unifykey-index-5 = <&keysn_5>; + unifykey-index-6 = <&keysn_6>; + unifykey-index-7 = <&keysn_7>; + unifykey-index-8 = <&keysn_8>; + unifykey-index-9 = <&keysn_9>; + unifykey-index-10= <&keysn_10>; + unifykey-index-11= <&keysn_11>; + unifykey-index-12= <&keysn_12>; + unifykey-index-13= <&keysn_13>; + unifykey-index-14= <&keysn_14>; + + keysn_0: key_0{ + key-name = "usid"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_1:key_1{ + key-name = "mac"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_2:key_2{ + key-name = "hdcp"; + key-device = "secure"; + key-type = "sha1"; + key-permit = "read","write","del"; + }; + keysn_3:key_3{ + key-name = "secure_boot_set"; + key-device = "efuse"; + key-permit = "write"; + }; + keysn_4:key_4{ + key-name = "mac_bt"; + key-device = "normal"; + key-permit = "read","write","del"; + key-type = "mac"; + }; + keysn_5:key_5{ + key-name = "mac_wifi"; + key-device = "normal"; + key-permit = "read","write","del"; + key-type = "mac"; + }; + keysn_6:key_6{ + key-name = "hdcp2_tx"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_7:key_7{ + key-name = "hdcp2_rx"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_8:key_8{ + key-name = "widevinekeybox"; + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_9:key_9{ + key-name = "deviceid"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_10:key_10{ + key-name = "hdcp22_fw_private"; + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_11:key_11{ + key-name = "PlayReadykeybox25"; + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_12:key_12{ + key-name = "prpubkeybox";// PlayReady + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_13:key_13{ + key-name = "prprivkeybox";// PlayReady + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_14:key_14{ + key-name = "attestationkeybox";// attestation key + key-device = "secure"; + key-permit = "read","write","del"; + }; + };//End unifykey + + efusekey:efusekey{ + keynum = <4>; + key0 = <&key_0>; + key1 = <&key_1>; + key2 = <&key_2>; + key3 = <&key_3>; + key_0:key_0{ + keyname = "mac"; + offset = <0>; + size = <6>; + }; + key_1:key_1{ + keyname = "mac_bt"; + offset = <6>; + size = <6>; + }; + key_2:key_2{ + keyname = "mac_wifi"; + offset = <12>; + size = <6>; + }; + key_3:key_3{ + keyname = "usid"; + offset = <18>; + size = <16>; + }; + };//End efusekey + + amlvecm { + compatible = "amlogic, vecm"; + dev_name = "aml_vecm"; + status = "okay"; + gamma_en = <0>;/*1:enabel ;0:disable*/ + wb_en = <0>;/*1:enabel ;0:disable*/ + cm_en = <0>;/*1:enabel ;0:disable*/ + /*0: 709/601 1: bt2020*/ + tx_op_color_primary = <0>; + }; + + amdolby_vision { + compatible = "amlogic, dolby_vision_g12a"; + dev_name = "aml_amdolby_vision_driver"; + status = "okay"; + tv_mode = <0>;/*1:enabel ;0:disable*/ + }; + + /* Audio Related start */ + pdm_codec:dummy{ + #sound-dai-cells = <0>; + compatible = "amlogic, pdm_dummy_codec"; + status = "okay"; + }; + dummy_codec:dummy{ + #sound-dai-cells = <0>; + compatible = "amlogic, aml_dummy_codec"; + status = "okay"; + }; + amlogic_codec:t9015{ + #sound-dai-cells = <0>; + compatible = "amlogic, aml_codec_T9015"; + reg = <0xFF632000 0x2000>; + is_auge_used = <1>; /* meson or auge chipset used */ + tdmout_index = <1>; + status = "okay"; + }; + audio_effect:eqdrc{ + /*eq_enable = <1>;*/ + /*drc_enable = <1>;*/ + /* + * 0:tdmout_a + * 1:tdmout_b + * 2:tdmout_c + * 3:spdifout + * 4:spdifout_b + */ + eqdrc_module = <1>; + /* max 0xf, each bit for one lane, usually one lane */ + lane_mask = <0x1>; + /* max 0xff, each bit for one channel */ + channel_mask = <0x3>; + }; + auge_sound { + compatible = "amlogic, g12a-sound-card"; + aml-audio-card,name = "AML-AUGESOUND"; + + aml-audio-card,loopback = <&aml_loopback>; + aml-audio-card,aux-devs = <&amlogic_codec>; + /*avout mute gpio*/ + avout_mute-gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_HIGH>; + /*for audio effect ,eqdrc */ + aml-audio-card,effect = <&audio_effect>; + + aml-audio-card,dai-link@0 { + format = "dsp_a"; + mclk-fs = <512>; + //continuous-clock; + //bitclock-inversion; + //frame-inversion; + //bitclock-master = <&tdmacodec>; + //frame-master = <&tdmacodec>; + /* suffix-name, sync with android audio hal + * what's the dai link used for + */ + suffix-name = "alsaPORT-pcm"; + tdmacpu: cpu { + sound-dai = <&aml_tdma>; + dai-tdm-slot-tx-mask = + <1 1 1 1 1 1 1 1>; + dai-tdm-slot-rx-mask = + <1 1 1 1 1 1 1 1>; + dai-tdm-slot-num = <8>; + dai-tdm-slot-width = <32>; + system-clock-frequency = <24576000>; + }; + tdmacodec: codec { + sound-dai = <&dummy_codec &dummy_codec>; + }; + }; + + aml-audio-card,dai-link@1 { + format = "i2s";// "dsp_a"; + mclk-fs = <256>; + //continuous-clock; + //bitclock-inversion; + //frame-inversion; + bitclock-master = <&aml_tdmb>; + frame-master = <&aml_tdmb>; + //bitclock-master = <&tdmbcodec>; + //frame-master = <&tdmbcodec>; + /* suffix-name, sync with android audio hal + * what's the dai link used for + */ + suffix-name = "alsaPORT-i2s"; + cpu { + sound-dai = <&aml_tdmb>; + dai-tdm-slot-tx-mask = <1 1>; + dai-tdm-slot-rx-mask = <1 1>; + dai-tdm-slot-num = <2>; + /* + * dai-tdm-slot-tx-mask = + * <1 1 1 1 1 1 1 1>; + * dai-tdm-slot-rx-mask = + * <1 1 1 1 1 1 1 1>; + * dai-tdm-slot-num = <8>; + */ + dai-tdm-slot-width = <32>; + system-clock-frequency = <12288000>; + }; + tdmbcodec: codec { + sound-dai = <&dummy_codec &dummy_codec + &amlogic_codec>; + }; + }; + + aml-audio-card,dai-link@2 { + format = "i2s"; + mclk-fs = <256>; + //continuous-clock; + //bitclock-inversion; + //frame-inversion; + bitclock-master = <&aml_tdmc>; + frame-master = <&aml_tdmc>; + /* suffix-name, sync with android audio hal + * what's the dai link used for + */ + //suffix-name = "alsaPORT-tdm"; + cpu { + sound-dai = <&aml_tdmc>; + dai-tdm-slot-tx-mask = <1 1>; + dai-tdm-slot-rx-mask = <1 1>; + dai-tdm-slot-num = <2>; + dai-tdm-slot-width = <32>; + system-clock-frequency = <12288000>; + }; + codec { + sound-dai = <&dummy_codec &dummy_codec>; + }; + }; + + aml-audio-card,dai-link@3 { + mclk-fs = <64>; + /* suffix-name, sync with android audio hal + * what's the dai link used for + */ + suffix-name = "alsaPORT-pdm"; + cpu { + sound-dai = <&aml_pdm>; + }; + codec { + sound-dai = <&pdm_codec>; + }; + }; + + aml-audio-card,dai-link@4 { + mclk-fs = <128>; + continuous-clock; + /* suffix-name, sync with android audio hal + * what's the dai link used for + */ + suffix-name = "alsaPORT-spdifb2hdmi"; + cpu { + sound-dai = <&aml_spdif>; + system-clock-frequency = <6144000>; + }; + codec { + sound-dai = <&dummy_codec>; + }; + }; + /* spdif_b to hdmi, only playback */ + aml-audio-card,dai-link@5 { + mclk-fs = <128>; + continuous-clock; + /* suffix-name, sync with android audio hal + * what's the dai link used for + */ + suffix-name = "alsaPORT-spdif"; + cpu { + sound-dai = <&aml_spdif_b>; + system-clock-frequency = <6144000>; + }; + codec { + sound-dai = <&dummy_codec>; + }; + }; + /* + * dai link for i2s to hdmix, + * Notice to select a tdm lane not used by hw + */ + /* + * aml-audio-card,dai-link@6 { + * format = "i2s"; + * mclk-fs = <256>; + * //continuous-clock; + * //bitclock-inversion; + * //frame-inversion; + * bitclock-master = <&aml_i2s2hdmi>; + * frame-master = <&aml_i2s2hdmi>; + * suffix-name = "alsaPORT-i2s2hdmi"; + * cpu { + * sound-dai = <&aml_i2s2hdmi>; + * dai-tdm-slot-tx-mask = <1 1>; + * dai-tdm-slot-num = <2>; + * dai-tdm-slot-width = <32>; + * system-clock-frequency = <12288000>; + * }; + * codec { + * sound-dai = <&dummy_codec>; + * }; + * }; + */ + }; + audiolocker: locker { + compatible = "amlogic, audiolocker"; + clocks = <&clkaudio CLKID_AUDIO_LOCKER_OUT + &clkaudio CLKID_AUDIO_LOCKER_IN + &clkaudio CLKID_AUDIO_MCLK_D + &clkaudio CLKID_AUDIO_MCLK_E + &clkc CLKID_MPLL1 + &clkc CLKID_MPLL2>; + clock-names = "lock_out", "lock_in", "out_src", + "in_src", "out_calc", "in_ref"; + interrupts = ; + interrupt-names = "irq"; + frequency = <49000000>; /* pll */ + dividor = <49>; /* locker's parent */ + status = "okay"; + }; + /* Audio Related end */ + + /*DCDC for SY8120B1ABC*/ + cpu_opp_table0: cpu_opp_table0 { + compatible = "operating-points-v2"; + opp-shared; + + opp00 { + opp-hz = /bits/ 64 <100000000>; + opp-microvolt = <731000>; + }; + opp01 { + opp-hz = /bits/ 64 <250000000>; + opp-microvolt = <731000>; + }; + opp02 { + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <731000>; + }; + opp03 { + opp-hz = /bits/ 64 <667000000>; + opp-microvolt = <731000>; + }; + opp04 { + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <731000>; + }; + opp05 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <761000>; + }; + opp06 { + opp-hz = /bits/ 64 <1398000000>; + opp-microvolt = <791000>; + }; + opp07 { + opp-hz = /bits/ 64 <1512000000>; + opp-microvolt = <831000>; + }; + opp08 { + opp-hz = /bits/ 64 <1608000000>; + opp-microvolt = <871000>; + }; + opp09 { + opp-hz = /bits/ 64 <1704000000>; + opp-microvolt = <921000>; + }; + opp10 { + opp-hz = /bits/ 64 <1800000000>; + opp-microvolt = <981000>; + }; + }; + + cpufreq-meson { + compatible = "amlogic, cpufreq-meson"; + pinctrl-names = "default"; + pinctrl-0 = <&pwm_ao_d_pins3>; + status = "okay"; + }; + +}; /* end of / */ + +&meson_fb { + status = "okay"; + display_size_default = <1920 1080 1920 2160 32>; + mem_size = <0x00800000 0x1980000 0x100000 0x100000 0x800000>; + logo_addr = "0x7f800000"; + mem_alloc = <0>; + pxp_mode = <0>; /** 0:normal mode 1:pxp mode */ +}; + +&pwm_AO_cd { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + pinctrl-names="default"; + pinctrl-0=<&i2c0_master_pins2>; + clock-frequency = <400000>; + + gt9xx@5d { + compatible = "goodix,gt9xx"; + status = "disabled"; + reg = <0x5d>; + reset-gpio = <&gpio GPIOZ_9 0x00>; + irq-gpio = <&gpio GPIOZ_3 0x00>; + }; + + ftxx@38 { + compatible = "focaltech,fts"; + status = "disabled"; + reg = <0x38>; + reset-gpio = <&gpio GPIOZ_9 0x00>; + irq-gpio = <&gpio GPIOZ_3 0x00>; + x_max = <600>; + y_max = <1024>; + max-touch-number = <10>; + }; +}; + +&i2c3 { + status = "disabled"; + pinctrl-names="default"; + pinctrl-0=<&i2c3_master_pins2>; + clock-frequency = <100000>; /* default 100k */ + + /* for ref board */ + ad82584f_62: ad82584f_62@62 { + compatible = "ESMT, ad82584f"; + #sound-dai-cells = <0>; + reg = <0x31>; + status = "disabled"; + reset_pin = <&gpio GPIOA_5 0>; + }; + + tas5707_36: tas5707_36@36 { + compatible = "ti,tas5707"; + #sound-dai-cells = <0>; + reg = <0x1b>; + status = "disabled"; + reset_pin = <&gpio GPIOA_5 0>; + }; + + bl_extern_i2c { + compatible = "amlogic, bl_extern_i2c"; + status = "disabled"; + reg = <0x2c>; /*reg_address for lp8556*/ + dev_name = "lp8556"; + }; +}; + +&audiobus { + aml_tdma: tdma { + compatible = "amlogic, g12a-snd-tdma"; + #sound-dai-cells = <0>; + dai-tdm-lane-slot-mask-in = <0 1>; + dai-tdm-oe-lane-slot-mask-out = <1 0>; + dai-tdm-clk-sel = <0>; + clocks = <&clkaudio CLKID_AUDIO_MCLK_A + &clkc CLKID_MPLL0>; + clock-names = "mclk", "clk_srcpll"; + pinctrl-names = "tdm_pins"; + pinctrl-0 = <&tdmout_a &tdmin_a>; + }; + + aml_tdmb: tdmb { + compatible = "amlogic, g12a-snd-tdmb"; + #sound-dai-cells = <0>; + dai-tdm-lane-slot-mask-in = <0 1 0 0>; + dai-tdm-lane-slot-mask-out = <1 0 0 0>; + dai-tdm-clk-sel = <1>; + clocks = <&clkaudio CLKID_AUDIO_MCLK_B + &clkc CLKID_MPLL1 + &clkc CLKID_MPLL0>; + clock-names = "mclk", "clk_srcpll", "samesource_sysclk"; + pinctrl-names = "tdm_pins"; + pinctrl-0 = <&tdmb_mclk &tdmout_b &tdmin_b>; + /* + * 0: tdmout_a; + * 1: tdmout_b; + * 2: tdmout_c; + * 3: spdifout; + * 4: spdifout_b; + */ + samesource_sel = <3>; + }; + + aml_tdmc: tdmc { + compatible = "amlogic, g12a-snd-tdmc"; + #sound-dai-cells = <0>; + dai-tdm-lane-slot-mask-in = <0 1 0 0>; + #dai-tdm-lane-slot-mask-out = <1 0 1 1>; + #dai-tdm-lane-oe-slot-mask-in = <0 0 0 0>; + dai-tdm-lane-oe-slot-mask-out = <1 0 0 0>; + dai-tdm-clk-sel = <2>; + clocks = <&clkaudio CLKID_AUDIO_MCLK_C + &clkc CLKID_MPLL2>; + clock-names = "mclk", "clk_srcpll"; + pinctrl-names = "tdm_pins"; + pinctrl-0 = <&tdmc_mclk &tdmout_c &tdmin_c>; + }; + + /* copy a useless tdm to output for hdmi, no pinmux */ + aml_i2s2hdmi: i2s2hdmi { + compatible = "amlogic, g12a-snd-tdmc"; + #sound-dai-cells = <0>; + dai-tdm-lane-slot-mask-out = <1 1 1 1>; + dai-tdm-clk-sel = <2>; + clocks = <&clkaudio CLKID_AUDIO_MCLK_C + &clkc CLKID_MPLL2>; + clock-names = "mclk", "clk_srcpll"; + + i2s2hdmi = <1>; + + status = "disabled"; + }; + + aml_spdif: spdif { + compatible = "amlogic, g12a-snd-spdif-a"; + #sound-dai-cells = <0>; + clocks = <&clkc CLKID_MPLL0 + &clkc CLKID_FCLK_DIV4 + &clkaudio CLKID_AUDIO_SPDIFIN + &clkaudio CLKID_AUDIO_SPDIFOUT + &clkaudio CLKID_AUDIO_SPDIFIN_CTRL + &clkaudio CLKID_AUDIO_SPDIFOUT_CTRL>; + clock-names = "sysclk", "fixed_clk", "gate_spdifin", + "gate_spdifout", "clk_spdifin", "clk_spdifout"; + interrupts = + ; + + interrupt-names = "irq_spdifin"; + pinctrl-names = "spdif_pins"; + pinctrl-0 = <&spdifout>; + status = "okay"; + }; + aml_spdif_b: spdif_b { + compatible = "amlogic, g12a-snd-spdif-b"; + #sound-dai-cells = <0>; + clocks = <&clkc CLKID_MPLL0 /*CLKID_HIFI_PLL*/ + &clkaudio CLKID_AUDIO_SPDIFOUTB + &clkaudio CLKID_AUDIO_SPDIFOUTB_CTRL>; + clock-names = "sysclk", + "gate_spdifout", "clk_spdifout"; + status = "okay"; + }; + aml_pdm: pdm { + compatible = "amlogic, g12a-snd-pdm"; + #sound-dai-cells = <0>; + clocks = <&clkaudio CLKID_AUDIO_PDM + &clkc CLKID_FCLK_DIV3 + &clkc CLKID_MPLL3 + &clkaudio CLKID_AUDIO_PDMIN0 + &clkaudio CLKID_AUDIO_PDMIN1>; + clock-names = "gate", + "sysclk_srcpll", + "dclk_srcpll", + "pdm_dclk", + "pdm_sysclk"; + pinctrl-names = "pdm_pins"; + pinctrl-0 = <&pdmin>; + filter_mode = <1>; /* mode 0~4, defalut:1 */ + status = "okay"; + }; + aml_loopback: loopback { + compatible = "amlogic, snd-loopback"; + /* + * 0: out rate = in data rate; + * 1: out rate = loopback data rate; + */ + lb_mode = <0>; + + /* datain src + * 0: tdmin_a; + * 1: tdmin_b; + * 2: tdmin_c; + * 3: spdifin; + * 4: pdmin; + */ + datain_src = <4>; + datain_chnum = <8>; + datain_chmask = <0x3f>; + + /* tdmin_lb src + * 0: tdmoutA + * 1: tdmoutB + * 2: tdmoutC + * 3: PAD_tdminA + * 4: PAD_tdminB + * 5: PAD_tdminC + */ + datalb_src = <2>; + datalb_chnum = <8>; + datalb_chmask = <0x3>; + + status = "okay"; + }; + + audioresample: resample { + compatible = "amlogic, g12a-resample"; + clocks = <&clkc CLKID_MPLL3 + &clkaudio CLKID_AUDIO_MCLK_F + &clkaudio CLKID_AUDIO_RESAMPLE_CTRL>; + clock-names = "resample_pll", "resample_src", "resample_clk"; + /*same with toddr_src + * TDMIN_A, 0 + * TDMIN_B, 1 + * TDMIN_C, 2 + * SPDIFIN, 3 + * PDMIN, 4 + * NONE, + * TDMIN_LB, 6 + * LOOPBACK, 7 + */ + resample_module = <4>; + status = "okay"; + }; + aml_pwrdet: pwrdet { + compatible = "amlogic, g12a-power-detect"; + + interrupts = ; + interrupt-names = "pwrdet_irq"; + + /* pwrdet source sel + * 7: loopback; + * 6: tdmin_lb; + * 5: reserved; + * 4: pdmin; + * 3: spdifin; + * 2: tdmin_c; + * 1: tdmin_b; + * 0: tdmin_a; + */ + pwrdet_src = <4>; + + hi_th = <0x70000>; + lo_th = <0x16000>; + + status = "disabled"; + }; +}; /* end of audiobus */ + +&pinctrl_periphs { + tdmout_a: tdmout_a { + mux { /* GPIOX_11, GPIOX_10, GPIOX_9 */ + groups = "tdma_sclk", + "tdma_fs", + "tdma_dout0"; + function = "tdma_out"; + }; + }; + + tdmin_a: tdmin_a { + mux { /* GPIOX_8 */ + groups = "tdma_din1"; + function = "tdma_in"; + }; + }; + + tdmb_mclk: tdmb_mclk { + mux { + groups = "mclk0_a"; + function = "mclk0"; + drive-strength = <2>; + }; + }; + tdmout_b: tdmout_b { + mux { /* GPIOA_1, GPIOA_2, GPIOA_3 */ + groups = "tdmb_sclk", + "tdmb_fs", + "tdmb_dout0"; + function = "tdmb_out"; + drive-strength = <2>; + }; + }; + + tdmin_b:tdmin_b { + mux { /* GPIOA_4 */ + groups = "tdmb_din1" + /*,"tdmb_slv_sclk", "tdmb_slv_fs"*/; + function = "tdmb_in"; + drive-strength = <2>; + }; + }; + + tdmc_mclk: tdmc_mclk { + mux { /* GPIOA_11 */ + groups = "mclk1_a"; + function = "mclk1"; + }; + }; + + tdmout_c:tdmout_c { + mux { /* GPIOA_12, GPIOA_13, GPIOA_10, GPIOA_8, GPIOA_7*/ + groups = "tdmc_sclk_a", + "tdmc_fs_a", + "tdmc_dout0_a" + /*, "tdmc_dout2", + * "tdmc_dout3" + */; + function = "tdmc_out"; + }; + }; + + tdmin_c:tdmin_c { + mux { /* GPIOA_9 */ + groups = "tdmc_din1_a"; + function = "tdmc_in"; + }; + }; + + spdifin: spdifin { + mux {/* GPIOH_5 */ + groups = "spdif_in_h"; + function = "spdif_in"; + }; + }; + + /* GPIOH_4 */ + spdifout: spdifout { + mux { + groups = "spdif_out_h"; + function = "spdif_out"; + }; + }; + + pdmin: pdmin { + mux { /* gpioa_5, gpioa_6, gpioa_7, gpioa_8, gpioa_9*/ + groups = "pdm_din0_a", + /*"pdm_din1_a",*/ + "pdm_din2_a", + /*"pdm_din3_a",*/ + "pdm_dclk_a"; + function = "pdm"; + }; + }; + + +}; /* end of pinctrl_periphs */ +&pinctrl_aobus { + /*gpiao_10*/ + /*spdifout: spdifout { */ + /* mux { */ + /* groups = "spdif_out_ao"; */ + /* function = "spdif_out_ao";*/ + /* }; */ + /*}; */ +}; /* end of pinctrl_aobus */ + +&audio_data { + status = "okay"; +}; + +/* Audio Related End */ + +&pwm_ef { + status = "okay"; +}; + +&dwc3 { + status = "okay"; +}; + +&usb2_phy_v2 { + status = "okay"; + portnum = <2>; +}; + +&usb3_phy_v2 { + status = "okay"; + portnum = <1>; + otg = <0>; +}; + +&dwc2_a { + status = "okay"; + /** 0: normal, 1: otg+dwc3 host only, 2: otg+dwc3 device only*/ + controller-type = <1>; +}; +ðmac { + status = "okay"; + pinctrl-names = "internal_eth_pins", "internal_gpio_pins"; + pinctrl-0 = <&internal_eth_pins>; + pinctrl-1 = <&internal_gpio_pins>; + mc_val = <0x4be04>; + + internal_phy=<1>; +}; + +&uart_A { + status = "okay"; +}; + +/*if you want to use vdin just modify status to "ok"*/ +&vdin0 { + memory-region = <&vdin0_cma_reserved>; + status = "okay"; + /*vdin write mem color depth support: + *bit0:support 8bit + *bit1:support 9bit + *bit2:support 10bit + *bit3:support 12bit + *bit4:support yuv422 10bit full pack mode (from txl new add) + */ + tv_bit_mode = <0x15>; +}; +&vdin1 { + memory-region = <&vdin1_cma_reserved>; + status = "okay"; + /*vdin write mem color depth support: + *bit0:support 8bit + *bit1:support 9bit + *bit2:support 10bit + *bit3:support 12bit + */ + tv_bit_mode = <1>; +}; + + +&sd_emmc_c { + status = "okay"; + emmc { + caps = "MMC_CAP_8_BIT_DATA", + "MMC_CAP_MMC_HIGHSPEED", + "MMC_CAP_SD_HIGHSPEED", + "MMC_CAP_NONREMOVABLE", + /* "MMC_CAP_1_8V_DDR", */ + "MMC_CAP_HW_RESET", + "MMC_CAP_ERASE", + "MMC_CAP_CMD23"; + caps2 = "MMC_CAP2_HS200"; + /* "MMC_CAP2_HS400";*/ + f_min = <400000>; + f_max = <200000000>; + }; +}; + +&sd_emmc_b1 { + status = "disabled"; + sd { + caps = "MMC_CAP_4_BIT_DATA", + "MMC_CAP_MMC_HIGHSPEED", + "MMC_CAP_SD_HIGHSPEED"; + f_min = <400000>; + f_max = <50000000>; + }; +}; + +&sd_emmc_b2 { + status = "disabled"; + sd { + caps = "MMC_CAP_4_BIT_DATA", + "MMC_CAP_MMC_HIGHSPEED", + "MMC_CAP_SD_HIGHSPEED"; + f_min = <400000>; + f_max = <50000000>; + }; + + sdio { + caps = "MMC_CAP_4_BIT_DATA", + "MMC_CAP_MMC_HIGHSPEED", + "MMC_CAP_SD_HIGHSPEED", + "MMC_CAP_NONREMOVABLE", + "MMC_CAP_UHS_SDR12", + "MMC_CAP_UHS_SDR25", + "MMC_CAP_UHS_SDR50", + "MMC_CAP_UHS_SDR104", + "MMC_PM_KEEP_POWER", + "MMC_CAP_SDIO_IRQ"; + + f_min = <400000>; + f_max = <200000000>; + }; +}; + +&sd_emmc_a { + status = "disabled"; + sdio { + caps = "MMC_CAP_4_BIT_DATA", + "MMC_CAP_MMC_HIGHSPEED", + "MMC_CAP_SD_HIGHSPEED", + "MMC_CAP_NONREMOVABLE", + "MMC_CAP_UHS_SDR12", + "MMC_CAP_UHS_SDR25", + "MMC_CAP_UHS_SDR50", + "MMC_CAP_UHS_SDR104", + "MMC_PM_KEEP_POWER", + "MMC_CAP_SDIO_IRQ"; + f_min = <400000>; + f_max = <200000000>; + }; +}; + +&nand { + status = "disabled"; + plat-names = "bootloader","nandnormal"; + plat-num = <2>; + plat-part-0 = <&bootloader>; + plat-part-1 = <&nandnormal>; + bootloader: bootloader{ + enable_pad ="ce0"; + busy_pad = "rb0"; + timming_mode = "mode5"; + bch_mode = "bch8_1k"; + t_rea = <20>; + t_rhoh = <15>; + chip_num = <1>; + part_num = <0>; + rb_detect = <1>; + }; + nandnormal: nandnormal{ + enable_pad ="ce0"; + busy_pad = "rb0"; + timming_mode = "mode5"; + bch_mode = "bch8_1k"; + plane_mode = "twoplane"; + t_rea = <20>; + t_rhoh = <15>; + chip_num = <2>; + part_num = <3>; + partition = <&nand_partitions>; + rb_detect = <1>; + }; + nand_partitions:nand_partition{ + /* + * if bl_mode is 1, tpl size was generate by + * fip_copies * fip_size which + * will not skip bad when calculating + * the partition size; + * + * if bl_mode is 0, + * tpl partition must be comment out. + */ + tpl{ + offset=<0x0 0x0>; + size=<0x0 0x0>; + }; + logo{ + offset=<0x0 0x0>; + size=<0x0 0x200000>; + }; + recovery{ + offset=<0x0 0x0>; + size=<0x0 0x1000000>; + }; + boot{ + offset=<0x0 0x0>; + size=<0x0 0x1000000>; + }; + system{ + offset=<0x0 0x0>; + size=<0x0 0x4000000>; + }; + data{ + offset=<0xffffffff 0xffffffff>; + size=<0x0 0x0>; + }; + }; +}; + +&pcie_A { + reset-gpio = <&gpio GPIOX_7 GPIO_ACTIVE_HIGH>; + status = "disable"; +}; + +&meson_cooldev { + status = "okay"; +}; + +&saradc { + status = "disabled"; +}; + +&defendkey { + status = "okay"; +}; + diff --git a/arch/arm/boot/dts/amlogic/g12a_s905x2_u211_1g.dts b/arch/arm/boot/dts/amlogic/g12a_s905x2_u211_1g.dts new file mode 100644 index 000000000000..74ec44c01106 --- /dev/null +++ b/arch/arm/boot/dts/amlogic/g12a_s905x2_u211_1g.dts @@ -0,0 +1,1327 @@ +/* + * arch/arm/boot/dts/amlogic/g12a_s905x2_u211.dts + * + * Copyright (C) 2017 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +/dts-v1/; + +#include "mesong12a.dtsi" +#include "partition_mbox_normal.dtsi" + +/ { + model = "Amlogic"; + amlogic-dt-id = "g12a_s905x2_u211_1g"; + compatible = "amlogic, g12a"; + interrupt-parent = <&gic>; + #address-cells = <1>; + #size-cells = <1>; + + aliases { + serial0 = &uart_AO; + serial1 = &uart_A; + serial2 = &uart_B; + serial3 = &uart_C; + serial4 = &uart_AO_B; + tsensor0 = &p_tsensor; + tsensor1 = &d_tsensor; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c_AO; + }; + + memory@00000000 { + device_type = "memory"; + linux,usable-memory = <0x100000 0x3ff00000>; + + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + /* global autoconfigured region for contiguous allocations */ + ramoops@0x07400000 { + compatible = "ramoops"; + reg = <0x07400000 0x00100000>; + record-size = <0x8000>; + console-size = <0x8000>; + ftrace-size = <0x0>; + pmsg-size = <0x8000>; + }; + + secmon_reserved:linux,secmon { + compatible = "shared-dma-pool"; + reusable; + size = <0x400000>; + alignment = <0x400000>; + alloc-ranges = <0x05000000 0x400000>; + }; + secos_reserved:linux,secos { + status = "disable"; + compatible = "amlogic, aml_secos_memory"; + reg = <0x05300000 0x2000000>; + no-map; + }; + logo_reserved:linux,meson-fb { + compatible = "shared-dma-pool"; + reusable; + size = <0x800000>; + alignment = <0x400000>; + alloc-ranges = <0x3f800000 0x800000>; + }; + ion_cma_reserved:linux,ion-dev { + compatible = "shared-dma-pool"; + reusable; + size = <0x8000000>; + alignment = <0x400000>; + }; + //di_reserved:linux,di { + //compatible = "amlogic, di-mem"; + /* buffer_size = 3621952(yuv422 8bit) */ + /* 4179008(yuv422 10bit full pack mode) */ + /** 10x3621952=34.6M(0x23) support 8bit **/ + /** 10x4736064=45.2M(0x2e) support 12bit **/ + /** 10x4179008=40M(0x28) support 10bit **/ + //size = <0x2800000>; + //no-map; + //}; + /*di CMA pool */ + di_cma_reserved:linux,di_cma { + compatible = "shared-dma-pool"; + reusable; + /* buffer_size = 3621952(yuv422 8bit) + * | 4736064(yuv422 10bit) + * | 4074560(yuv422 10bit full pack mode) + * 10x3621952=34.6M(0x23) support 8bit + * 10x4736064=45.2M(0x2e) support 12bit + * 10x4074560=40M(0x28) support 10bit + */ + size = <0x02800000>; + alignment = <0x400000>; + }; + /* POST PROCESS MANAGER */ + ppmgr_reserved:linux,ppmgr { + compatible = "shared-dma-pool"; + size = <0x0>; + }; + + codec_mm_cma:linux,codec_mm_cma { + compatible = "shared-dma-pool"; + reusable; + /* ion_codec_mm max can alloc size 80M*/ + size = <0xc000000>; + alignment = <0x400000>; + linux,contiguous-region; + }; + /* codec shared reserved */ + codec_mm_reserved:linux,codec_mm_reserved { + compatible = "amlogic, codec-mm-reserved"; + size = <0x0>; + alignment = <0x100000>; + //no-map; + }; + /* vdin0 CMA pool */ + vdin0_cma_reserved:linux,vdin0_cma { + compatible = "shared-dma-pool"; + reusable; + /* 1920x1080x2x4 =16+4 M */ + size = <0x04000000>; + alignment = <0x400000>; + }; + /* vdin1 CMA pool */ + vdin1_cma_reserved:linux,vdin1_cma { + compatible = "shared-dma-pool"; + reusable; + /* 1920x1080x2x4 =16 M */ + size = <0x04000000>; + alignment = <0x400000>; + }; + }; + + amlogic_battery:dummy-battery { + compatible = "amlogic, dummy-battery"; + status = "disabled"; + }; + + amlogic_charger:dummy-charger { + compatible = "amlogic, dummy-charger"; + status = "disabled"; + }; + + gpioleds { + compatible = "gpio-leds"; + status = "okay"; + + net_red { + label="net_red"; + gpios=<&gpio GPIOA_14 GPIO_ACTIVE_LOW>; + default-state ="on"; + }; + + net_green { + label="net_green"; + gpios=<&gpio GPIOA_15 GPIO_ACTIVE_HIGH>; + default-state ="on"; + }; + + remote_led { + label = "remote_led"; + gpios = <&gpio_ao GPIOAO_10 GPIO_ACTIVE_LOW>; + default-state = "off"; + linux,default-trigger = "rc_feedback"; + }; + + sys_led { + label="sys_led"; + gpios=<&gpio_ao GPIOAO_11 GPIO_ACTIVE_LOW>; + default-state ="on"; + retain-state-suspended; + linux,default-trigger="cpu0"; + }; + }; + + cvbsout { + compatible = "amlogic, cvbsout-g12a"; + dev_name = "cvbsout"; + status = "okay"; + clocks = <&clkc CLKID_VCLK2_ENCI + &clkc CLKID_VCLK2_VENCI0 + &clkc CLKID_VCLK2_VENCI1 + &clkc CLKID_DAC_CLK>; + clock-names = "venci_top_gate", + "venci_0_gate", + "venci_1_gate", + "vdac_clk_gate"; + + /* performance: reg_address, reg_value */ + /* g12a */ + performance = <0x1bf0 0x9 + 0x1b56 0x343 + 0x1b12 0x0 + 0x1b05 0x9 + 0x1c59 0xfc48 + 0xffff 0x0>; /* ending flag */ + performance_telecom = <0x1bf0 0x9 + 0x1b56 0x333 + 0x1b12 0x8080 + 0x1b05 0xfd + 0x1c59 0xf850 + 0xffff 0x0>; /* ending flag */ + }; + + bt-dev{ + compatible = "amlogic, bt-dev"; + dev_name = "bt-dev"; + status = "okay"; + gpio_reset = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>; + gpio_hostwake = <&gpio GPIOX_19 GPIO_ACTIVE_HIGH>; + }; + + wifi{ + compatible = "amlogic, aml_wifi"; + dev_name = "aml_wifi"; + status = "okay"; + interrupt_pin = <&gpio GPIOX_7 GPIO_ACTIVE_HIGH>; + irq_trigger_type = "GPIO_IRQ_LOW"; + power_on_pin = <&gpio GPIOX_6 GPIO_ACTIVE_HIGH>; + dhd_static_buf; //if use bcm wifi, config dhd_static_buf + pinctrl-names = "default"; + pinctrl-0 = <&pwm_e_pins>; + pwm_config = <&wifi_pwm_conf>; + }; + + wifi_pwm_conf:wifi_pwm_conf{ + pwm_channel1_conf { + pwms = <&pwm_ef MESON_PWM_0 30040 0>; + duty-cycle = <15020>; + times = <10>; + }; + pwm_channel2_conf { + pwms = <&pwm_ef MESON_PWM_2 30030 0>; + duty-cycle = <15015>; + times = <12>; + }; + }; + + codec_mm { + compatible = "amlogic, codec, mm"; + memory-region = <&codec_mm_cma &codec_mm_reserved>; + dev_name = "codec_mm"; + status = "okay"; + }; + + ppmgr { + compatible = "amlogic, ppmgr"; + memory-region = <&ppmgr_reserved>; + dev_name = "ppmgr"; + status = "okay"; + }; + + deinterlace { + compatible = "amlogic, deinterlace"; + status = "okay"; + /* 0:use reserved; 1:use cma; 2:use cma as reserved */ + flag_cma = <1>; + //memory-region = <&di_reserved>; + memory-region = <&di_cma_reserved>; + interrupts = <0 46 1 + 0 40 1>; + interrupt-names = "pre_irq", "post_irq"; + clocks = <&clkc CLKID_VPU_CLKB_TMP_COMP>, + <&clkc CLKID_VPU_CLKB_COMP>; + clock-names = "vpu_clkb_tmp_composite", + "vpu_clkb_composite"; + clock-range = <334 667>; + /* buffer-size = <3621952>;(yuv422 8bit) */ + buffer-size = <4074560>;/*yuv422 fullpack*/ + /* reserve-iomap = "true"; */ + /* if enable nr10bit, set nr10bit-support to 1 */ + post-wr-support = <1>; + nr10bit-support = <1>; + nrds-enable = <1>; + pps-enable = <1>; + }; + ionvideo { + compatible = "amlogic, ionvideo"; + dev_name = "ionvideo"; + status = "okay"; + }; + dvb{ + compatible = "amlogic, dvb"; + dev_name = "dvb"; + status = "ok"; + /*"parallel","serial","disable"*/ + ts2 = "parallel"; + ts2_control = <0>; + ts2_invert = <0>; + }; + unifykey{ + compatible = "amlogic, unifykey"; + status = "ok"; + unifykey-num = <15>; + unifykey-index-0 = <&keysn_0>; + unifykey-index-1 = <&keysn_1>; + unifykey-index-2 = <&keysn_2>; + unifykey-index-3 = <&keysn_3>; + unifykey-index-4 = <&keysn_4>; + unifykey-index-5 = <&keysn_5>; + unifykey-index-6 = <&keysn_6>; + unifykey-index-7 = <&keysn_7>; + unifykey-index-8 = <&keysn_8>; + unifykey-index-9 = <&keysn_9>; + unifykey-index-10= <&keysn_10>; + unifykey-index-11= <&keysn_11>; + unifykey-index-12= <&keysn_12>; + unifykey-index-13= <&keysn_13>; + unifykey-index-14= <&keysn_14>; + + keysn_0: key_0{ + key-name = "usid"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_1:key_1{ + key-name = "mac"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_2:key_2{ + key-name = "hdcp"; + key-device = "secure"; + key-type = "sha1"; + key-permit = "read","write","del"; + }; + keysn_3:key_3{ + key-name = "secure_boot_set"; + key-device = "efuse"; + key-permit = "write"; + }; + keysn_4:key_4{ + key-name = "mac_bt"; + key-device = "normal"; + key-permit = "read","write","del"; + key-type = "mac"; + }; + keysn_5:key_5{ + key-name = "mac_wifi"; + key-device = "normal"; + key-permit = "read","write","del"; + key-type = "mac"; + }; + keysn_6:key_6{ + key-name = "hdcp2_tx"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_7:key_7{ + key-name = "hdcp2_rx"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_8:key_8{ + key-name = "widevinekeybox"; + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_9:key_9{ + key-name = "deviceid"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_10:key_10{ + key-name = "hdcp22_fw_private"; + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_11:key_11{ + key-name = "PlayReadykeybox25"; + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_12:key_12{ + key-name = "prpubkeybox";// PlayReady + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_13:key_13{ + key-name = "prprivkeybox";// PlayReady + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_14:key_14{ + key-name = "attestationkeybox";// attestation key + key-device = "secure"; + key-permit = "read","write","del"; + }; + };//End unifykey + + efusekey:efusekey{ + keynum = <4>; + key0 = <&key_0>; + key1 = <&key_1>; + key2 = <&key_2>; + key3 = <&key_3>; + key_0:key_0{ + keyname = "mac"; + offset = <0>; + size = <6>; + }; + key_1:key_1{ + keyname = "mac_bt"; + offset = <6>; + size = <6>; + }; + key_2:key_2{ + keyname = "mac_wifi"; + offset = <12>; + size = <6>; + }; + key_3:key_3{ + keyname = "usid"; + offset = <18>; + size = <16>; + }; + };//End efusekey + + amlvecm { + compatible = "amlogic, vecm"; + dev_name = "aml_vecm"; + status = "okay"; + gamma_en = <0>;/*1:enabel ;0:disable*/ + wb_en = <0>;/*1:enabel ;0:disable*/ + cm_en = <0>;/*1:enabel ;0:disable*/ + }; + + amdolby_vision { + compatible = "amlogic, dolby_vision_g12a"; + dev_name = "aml_amdolby_vision_driver"; + status = "okay"; + tv_mode = <0>;/*1:enabel ;0:disable*/ + }; + + /* Audio Related start */ + pdm_codec:dummy{ + #sound-dai-cells = <0>; + compatible = "amlogic, pdm_dummy_codec"; + status = "okay"; + }; + dummy_codec:dummy{ + #sound-dai-cells = <0>; + compatible = "amlogic, aml_dummy_codec"; + status = "okay"; + }; + amlogic_codec:t9015{ + #sound-dai-cells = <0>; + compatible = "amlogic, aml_codec_T9015"; + reg = <0xFF632000 0x2000>; + is_auge_used = <1>; /* meson or auge chipset used */ + tdmout_index = <1>; + status = "okay"; + }; + audio_effect:eqdrc{ + /*eq_enable = <1>;*/ + /*drc_enable = <1>;*/ + /* + * 0:tdmout_a + * 1:tdmout_b + * 2:tdmout_c + * 3:spdifout + * 4:spdifout_b + */ + eqdrc_module = <1>; + /* max 0xf, each bit for one lane, usually one lane */ + lane_mask = <0x1>; + /* max 0xff, each bit for one channel */ + channel_mask = <0x3>; + }; + auge_sound { + compatible = "amlogic, g12a-sound-card"; + aml-audio-card,name = "AML-AUGESOUND"; + + aml-audio-card,loopback = <&aml_loopback>; + aml-audio-card,aux-devs = <&amlogic_codec>; + /*avout mute gpio*/ + avout_mute-gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_HIGH>; + /*for audio effect ,eqdrc */ + aml-audio-card,effect = <&audio_effect>; + + aml-audio-card,dai-link@0 { + format = "dsp_a"; + mclk-fs = <512>; + //continuous-clock; + //bitclock-inversion; + //frame-inversion; + //bitclock-master = <&tdmacodec>; + //frame-master = <&tdmacodec>; + /* suffix-name, sync with android audio hal + * what's the dai link used for + */ + suffix-name = "alsaPORT-pcm"; + tdmacpu: cpu { + sound-dai = <&aml_tdma>; + dai-tdm-slot-tx-mask = + <1 1 1 1 1 1 1 1>; + dai-tdm-slot-rx-mask = + <1 1 1 1 1 1 1 1>; + dai-tdm-slot-num = <8>; + dai-tdm-slot-width = <32>; + system-clock-frequency = <24576000>; + }; + tdmacodec: codec { + sound-dai = <&dummy_codec &dummy_codec>; + }; + }; + + aml-audio-card,dai-link@1 { + format = "i2s";// "dsp_a"; + mclk-fs = <256>; + //continuous-clock; + //bitclock-inversion; + //frame-inversion; + bitclock-master = <&aml_tdmb>; + frame-master = <&aml_tdmb>; + //bitclock-master = <&tdmbcodec>; + //frame-master = <&tdmbcodec>; + /* suffix-name, sync with android audio hal + * what's the dai link used for + */ + suffix-name = "alsaPORT-i2s"; + cpu { + sound-dai = <&aml_tdmb>; + dai-tdm-slot-tx-mask = <1 1>; + dai-tdm-slot-rx-mask = <1 1>; + dai-tdm-slot-num = <2>; + /* + * dai-tdm-slot-tx-mask = + * <1 1 1 1 1 1 1 1>; + * dai-tdm-slot-rx-mask = + * <1 1 1 1 1 1 1 1>; + * dai-tdm-slot-num = <8>; + */ + dai-tdm-slot-width = <32>; + system-clock-frequency = <12288000>; + }; + tdmbcodec: codec { + sound-dai = <&dummy_codec &dummy_codec + &amlogic_codec>; + }; + }; + + aml-audio-card,dai-link@2 { + format = "i2s"; + mclk-fs = <256>; + //continuous-clock; + //bitclock-inversion; + //frame-inversion; + bitclock-master = <&aml_tdmc>; + frame-master = <&aml_tdmc>; + /* suffix-name, sync with android audio hal + * what's the dai link used for + */ + //suffix-name = "alsaPORT-tdm"; + cpu { + sound-dai = <&aml_tdmc>; + dai-tdm-slot-tx-mask = <1 1>; + dai-tdm-slot-rx-mask = <1 1>; + dai-tdm-slot-num = <2>; + dai-tdm-slot-width = <32>; + system-clock-frequency = <12288000>; + }; + codec { + sound-dai = <&dummy_codec &dummy_codec>; + }; + }; + + aml-audio-card,dai-link@3 { + mclk-fs = <64>; + /* suffix-name, sync with android audio hal + * what's the dai link used for + */ + suffix-name = "alsaPORT-pdm"; + cpu { + sound-dai = <&aml_pdm>; + }; + codec { + sound-dai = <&pdm_codec>; + }; + }; + + aml-audio-card,dai-link@4 { + mclk-fs = <128>; + continuous-clock; + /* suffix-name, sync with android audio hal + * what's the dai link used for + */ + suffix-name = "alsaPORT-spdifb2hdmi"; + cpu { + sound-dai = <&aml_spdif>; + system-clock-frequency = <6144000>; + }; + codec { + sound-dai = <&dummy_codec>; + }; + }; + /* spdif_b to hdmi, only playback */ + aml-audio-card,dai-link@5 { + mclk-fs = <128>; + continuous-clock; + /* suffix-name, sync with android audio hal + * what's the dai link used for + */ + suffix-name = "alsaPORT-spdif"; + cpu { + sound-dai = <&aml_spdif_b>; + system-clock-frequency = <6144000>; + }; + codec { + sound-dai = <&dummy_codec>; + }; + }; + /* + * dai link for i2s to hdmix, + * Notice to select a tdm lane not used by hw + */ + /* + * aml-audio-card,dai-link@6 { + * format = "i2s"; + * mclk-fs = <256>; + * //continuous-clock; + * //bitclock-inversion; + * //frame-inversion; + * bitclock-master = <&aml_i2s2hdmi>; + * frame-master = <&aml_i2s2hdmi>; + * suffix-name = "alsaPORT-i2s2hdmi"; + * cpu { + * sound-dai = <&aml_i2s2hdmi>; + * dai-tdm-slot-tx-mask = <1 1>; + * dai-tdm-slot-num = <2>; + * dai-tdm-slot-width = <32>; + * system-clock-frequency = <12288000>; + * }; + * codec { + * sound-dai = <&dummy_codec>; + * }; + * }; + */ + }; + audiolocker: locker { + compatible = "amlogic, audiolocker"; + clocks = <&clkaudio CLKID_AUDIO_LOCKER_OUT + &clkaudio CLKID_AUDIO_LOCKER_IN + &clkaudio CLKID_AUDIO_MCLK_D + &clkaudio CLKID_AUDIO_MCLK_E + &clkc CLKID_MPLL1 + &clkc CLKID_MPLL2>; + clock-names = "lock_out", "lock_in", "out_src", + "in_src", "out_calc", "in_ref"; + interrupts = ; + interrupt-names = "irq"; + frequency = <49000000>; /* pll */ + dividor = <49>; /* locker's parent */ + status = "okay"; + }; + /* Audio Related end */ + + cpu_opp_table0: cpu_opp_table0 { + compatible = "operating-points-v2"; + opp-shared; + + opp00 { + opp-hz = /bits/ 64 <100000000>; + opp-microvolt = <731000>; + }; + opp01 { + opp-hz = /bits/ 64 <250000000>; + opp-microvolt = <731000>; + }; + opp02 { + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <731000>; + }; + opp03 { + opp-hz = /bits/ 64 <667000000>; + opp-microvolt = <731000>; + }; + opp04 { + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <731000>; + }; + opp05 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <761000>; + }; + opp06 { + opp-hz = /bits/ 64 <1398000000>; + opp-microvolt = <791000>; + }; + opp07 { + opp-hz = /bits/ 64 <1512000000>; + opp-microvolt = <831000>; + }; + opp08 { + opp-hz = /bits/ 64 <1608000000>; + opp-microvolt = <871000>; + }; + opp09 { + opp-hz = /bits/ 64 <1704000000>; + opp-microvolt = <921000>; + }; + opp10 { + opp-hz = /bits/ 64 <1800000000>; + opp-microvolt = <981000>; + }; + }; + + cpufreq-meson { + compatible = "amlogic, cpufreq-meson"; + pinctrl-names = "default"; + pinctrl-0 = <&pwm_ao_d_pins3>; + status = "okay"; + }; + +}; /* end of / */ + +&meson_fb { + status = "okay"; + display_size_default = <1920 1080 1920 2160 32>; + mem_size = <0x00800000 0x1980000 0x100000 0x100000 0x800000>; + logo_addr = "0x3f800000"; + mem_alloc = <0>; + pxp_mode = <0>; /** 0:normal mode 1:pxp mode */ +}; + +&pwm_AO_cd { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + pinctrl-names="default"; + pinctrl-0=<&i2c0_master_pins2>; + clock-frequency = <400000>; + + gt9xx@5d { + compatible = "goodix,gt9xx"; + status = "disabled"; + reg = <0x5d>; + reset-gpio = <&gpio GPIOZ_9 0x00>; + irq-gpio = <&gpio GPIOZ_3 0x00>; + }; + + ftxx@38 { + compatible = "focaltech,fts"; + status = "disabled"; + reg = <0x38>; + reset-gpio = <&gpio GPIOZ_9 0x00>; + irq-gpio = <&gpio GPIOZ_3 0x00>; + x_max = <600>; + y_max = <1024>; + max-touch-number = <10>; + }; +}; + +&i2c3 { + status = "disabled"; + pinctrl-names="default"; + pinctrl-0=<&i2c3_master_pins2>; + clock-frequency = <100000>; /* default 100k */ + + /* for ref board */ + ad82584f_62: ad82584f_62@62 { + compatible = "ESMT, ad82584f"; + #sound-dai-cells = <0>; + reg = <0x31>; + status = "disabled"; + reset_pin = <&gpio GPIOA_5 0>; + }; + + tas5707_36: tas5707_36@36 { + compatible = "ti,tas5707"; + #sound-dai-cells = <0>; + reg = <0x1b>; + status = "disabled"; + reset_pin = <&gpio GPIOA_5 0>; + }; + + bl_extern_i2c { + compatible = "amlogic, bl_extern_i2c"; + status = "disabled"; + reg = <0x2c>; /*reg_address for lp8556*/ + dev_name = "lp8556"; + }; +}; + +&audiobus { + aml_tdma: tdma { + compatible = "amlogic, g12a-snd-tdma"; + #sound-dai-cells = <0>; + dai-tdm-lane-slot-mask-in = <0 1>; + dai-tdm-oe-lane-slot-mask-out = <1 0>; + dai-tdm-clk-sel = <0>; + clocks = <&clkaudio CLKID_AUDIO_MCLK_A + &clkc CLKID_MPLL0>; + clock-names = "mclk", "clk_srcpll"; + pinctrl-names = "tdm_pins"; + pinctrl-0 = <&tdmout_a &tdmin_a>; + }; + + aml_tdmb: tdmb { + compatible = "amlogic, g12a-snd-tdmb"; + #sound-dai-cells = <0>; + dai-tdm-lane-slot-mask-in = <0 1 0 0>; + dai-tdm-lane-slot-mask-out = <1 0 0 0>; + dai-tdm-clk-sel = <1>; + clocks = <&clkaudio CLKID_AUDIO_MCLK_B + &clkc CLKID_MPLL1 + &clkc CLKID_MPLL0>; + clock-names = "mclk", "clk_srcpll", "samesource_sysclk"; + pinctrl-names = "tdm_pins"; + pinctrl-0 = <&tdmb_mclk &tdmout_b &tdmin_b>; + /* + * 0: tdmout_a; + * 1: tdmout_b; + * 2: tdmout_c; + * 3: spdifout; + * 4: spdifout_b; + */ + samesource_sel = <3>; + }; + + aml_tdmc: tdmc { + compatible = "amlogic, g12a-snd-tdmc"; + #sound-dai-cells = <0>; + dai-tdm-lane-slot-mask-in = <0 1 0 0>; + #dai-tdm-lane-slot-mask-out = <1 0 1 1>; + #dai-tdm-lane-oe-slot-mask-in = <0 0 0 0>; + dai-tdm-lane-oe-slot-mask-out = <1 0 0 0>; + dai-tdm-clk-sel = <2>; + clocks = <&clkaudio CLKID_AUDIO_MCLK_C + &clkc CLKID_MPLL2>; + clock-names = "mclk", "clk_srcpll"; + pinctrl-names = "tdm_pins"; + pinctrl-0 = <&tdmc_mclk &tdmout_c &tdmin_c>; + }; + + /* copy a useless tdm to output for hdmi, no pinmux */ + aml_i2s2hdmi: i2s2hdmi { + compatible = "amlogic, g12a-snd-tdmc"; + #sound-dai-cells = <0>; + dai-tdm-lane-slot-mask-out = <1 1 1 1>; + dai-tdm-clk-sel = <2>; + clocks = <&clkaudio CLKID_AUDIO_MCLK_C + &clkc CLKID_MPLL2>; + clock-names = "mclk", "clk_srcpll"; + + i2s2hdmi = <1>; + + status = "disabled"; + }; + + aml_spdif: spdif { + compatible = "amlogic, g12a-snd-spdif-a"; + #sound-dai-cells = <0>; + clocks = <&clkc CLKID_MPLL0 + &clkc CLKID_FCLK_DIV4 + &clkaudio CLKID_AUDIO_SPDIFIN + &clkaudio CLKID_AUDIO_SPDIFOUT + &clkaudio CLKID_AUDIO_SPDIFIN_CTRL + &clkaudio CLKID_AUDIO_SPDIFOUT_CTRL>; + clock-names = "sysclk", "fixed_clk", "gate_spdifin", + "gate_spdifout", "clk_spdifin", "clk_spdifout"; + interrupts = + ; + + interrupt-names = "irq_spdifin"; + pinctrl-names = "spdif_pins"; + pinctrl-0 = <&spdifout>; + status = "okay"; + }; + aml_spdif_b: spdif_b { + compatible = "amlogic, g12a-snd-spdif-b"; + #sound-dai-cells = <0>; + clocks = <&clkc CLKID_MPLL0 /*CLKID_HIFI_PLL*/ + &clkaudio CLKID_AUDIO_SPDIFOUTB + &clkaudio CLKID_AUDIO_SPDIFOUTB_CTRL>; + clock-names = "sysclk", + "gate_spdifout", "clk_spdifout"; + status = "okay"; + }; + aml_pdm: pdm { + compatible = "amlogic, g12a-snd-pdm"; + #sound-dai-cells = <0>; + clocks = <&clkaudio CLKID_AUDIO_PDM + &clkc CLKID_FCLK_DIV3 + &clkc CLKID_MPLL3 + &clkaudio CLKID_AUDIO_PDMIN0 + &clkaudio CLKID_AUDIO_PDMIN1>; + clock-names = "gate", + "sysclk_srcpll", + "dclk_srcpll", + "pdm_dclk", + "pdm_sysclk"; + pinctrl-names = "pdm_pins"; + pinctrl-0 = <&pdmin>; + filter_mode = <1>; /* mode 0~4, defalut:1 */ + status = "okay"; + }; + aml_loopback: loopback { + compatible = "amlogic, snd-loopback"; + /* + * 0: out rate = in data rate; + * 1: out rate = loopback data rate; + */ + lb_mode = <0>; + + /* datain src + * 0: tdmin_a; + * 1: tdmin_b; + * 2: tdmin_c; + * 3: spdifin; + * 4: pdmin; + */ + datain_src = <4>; + datain_chnum = <8>; + datain_chmask = <0x3f>; + + /* tdmin_lb src + * 0: tdmoutA + * 1: tdmoutB + * 2: tdmoutC + * 3: PAD_tdminA + * 4: PAD_tdminB + * 5: PAD_tdminC + */ + datalb_src = <2>; + datalb_chnum = <8>; + datalb_chmask = <0x3>; + + status = "okay"; + }; + + audioresample: resample { + compatible = "amlogic, g12a-resample"; + clocks = <&clkc CLKID_MPLL3 + &clkaudio CLKID_AUDIO_MCLK_F + &clkaudio CLKID_AUDIO_RESAMPLE_CTRL>; + clock-names = "resample_pll", "resample_src", "resample_clk"; + /*same with toddr_src + * TDMIN_A, 0 + * TDMIN_B, 1 + * TDMIN_C, 2 + * SPDIFIN, 3 + * PDMIN, 4 + * NONE, + * TDMIN_LB, 6 + * LOOPBACK, 7 + */ + resample_module = <4>; + status = "okay"; + }; + aml_pwrdet: pwrdet { + compatible = "amlogic, g12a-power-detect"; + + interrupts = ; + interrupt-names = "pwrdet_irq"; + + /* pwrdet source sel + * 7: loopback; + * 6: tdmin_lb; + * 5: reserved; + * 4: pdmin; + * 3: spdifin; + * 2: tdmin_c; + * 1: tdmin_b; + * 0: tdmin_a; + */ + pwrdet_src = <4>; + + hi_th = <0x70000>; + lo_th = <0x16000>; + + status = "okay"; + }; +}; /* end of audiobus */ + +&pinctrl_periphs { + tdmout_a: tdmout_a { + mux { /* GPIOX_11, GPIOX_10, GPIOX_9 */ + groups = "tdma_sclk", + "tdma_fs", + "tdma_dout0"; + function = "tdma_out"; + }; + }; + + tdmin_a: tdmin_a { + mux { /* GPIOX_8 */ + groups = "tdma_din1"; + function = "tdma_in"; + }; + }; + + tdmb_mclk: tdmb_mclk { + mux { + groups = "mclk0_a"; + function = "mclk0"; + drive-strength = <2>; + }; + }; + tdmout_b: tdmout_b { + mux { /* GPIOA_1, GPIOA_2, GPIOA_3 */ + groups = "tdmb_sclk", + "tdmb_fs", + "tdmb_dout0"; + function = "tdmb_out"; + drive-strength = <2>; + }; + }; + + tdmin_b:tdmin_b { + mux { /* GPIOA_4 */ + groups = "tdmb_din1" + /*,"tdmb_slv_sclk", "tdmb_slv_fs"*/; + function = "tdmb_in"; + drive-strength = <2>; + }; + }; + + tdmc_mclk: tdmc_mclk { + mux { /* GPIOA_11 */ + groups = "mclk1_a"; + function = "mclk1"; + }; + }; + + tdmout_c:tdmout_c { + mux { /* GPIOA_12, GPIOA_13, GPIOA_10, GPIOA_8, GPIOA_7*/ + groups = "tdmc_sclk_a", + "tdmc_fs_a", + "tdmc_dout0_a" + /*, "tdmc_dout2", + * "tdmc_dout3" + */; + function = "tdmc_out"; + }; + }; + + tdmin_c:tdmin_c { + mux { /* GPIOA_9 */ + groups = "tdmc_din1_a"; + function = "tdmc_in"; + }; + }; + + spdifin: spdifin { + mux {/* GPIOH_5 */ + groups = "spdif_in_h"; + function = "spdif_in"; + }; + }; + + /* GPIOH_4 */ + spdifout: spdifout { + mux { + groups = "spdif_out_h"; + function = "spdif_out"; + }; + }; + + pdmin: pdmin { + mux { /* gpioa_5, gpioa_6, gpioa_7, gpioa_8, gpioa_9*/ + groups = "pdm_din0_a", + /*"pdm_din1_a",*/ + "pdm_din2_a", + /*"pdm_din3_a",*/ + "pdm_dclk_a"; + function = "pdm"; + }; + }; + + +}; /* end of pinctrl_periphs */ +&pinctrl_aobus { + /*gpiao_10*/ + /*spdifout: spdifout { */ + /* mux { */ + /* groups = "spdif_out_ao"; */ + /* function = "spdif_out_ao";*/ + /* }; */ + /*}; */ +}; /* end of pinctrl_aobus */ + +&audio_data { + status = "okay"; +}; + +/* Audio Related End */ + +&pwm_ef { + status = "okay"; +}; + +&dwc3 { + status = "okay"; +}; + +&usb2_phy_v2 { + status = "okay"; + portnum = <2>; +}; + +&usb3_phy_v2 { + status = "okay"; + portnum = <1>; + otg = <0>; +}; + +&dwc2_a { + status = "okay"; + /** 0: normal, 1: otg+dwc3 host only, 2: otg+dwc3 device only*/ + controller-type = <1>; +}; +ðmac { + status = "okay"; + pinctrl-names = "internal_eth_pins"; + pinctrl-0 = <&internal_eth_pins>; + mc_val = <0x4be04>; + + internal_phy=<1>; +}; + +&uart_A { + status = "okay"; +}; + +/*if you want to use vdin just modify status to "ok"*/ +&vdin0 { + memory-region = <&vdin0_cma_reserved>; + status = "okay"; + /*vdin write mem color depth support: + *bit0:support 8bit + *bit1:support 9bit + *bit2:support 10bit + *bit3:support 12bit + *bit4:support yuv422 10bit full pack mode (from txl new add) + */ + tv_bit_mode = <0x15>; +}; +&vdin1 { + memory-region = <&vdin1_cma_reserved>; + status = "okay"; + /*vdin write mem color depth support: + *bit0:support 8bit + *bit1:support 9bit + *bit2:support 10bit + *bit3:support 12bit + */ + tv_bit_mode = <1>; +}; + + +&sd_emmc_c { + status = "okay"; + emmc { + caps = "MMC_CAP_8_BIT_DATA", + "MMC_CAP_MMC_HIGHSPEED", + "MMC_CAP_SD_HIGHSPEED", + "MMC_CAP_NONREMOVABLE", + /* "MMC_CAP_1_8V_DDR", */ + "MMC_CAP_HW_RESET", + "MMC_CAP_ERASE", + "MMC_CAP_CMD23"; + caps2 = "MMC_CAP2_HS200"; + /* "MMC_CAP2_HS400";*/ + f_min = <400000>; + f_max = <200000000>; + }; +}; + +&sd_emmc_b1 { + status = "disabled"; + sd { + caps = "MMC_CAP_4_BIT_DATA", + "MMC_CAP_MMC_HIGHSPEED", + "MMC_CAP_SD_HIGHSPEED"; + f_min = <400000>; + f_max = <50000000>; + }; +}; + +&sd_emmc_b2 { + status = "disabled"; + sd { + caps = "MMC_CAP_4_BIT_DATA", + "MMC_CAP_MMC_HIGHSPEED", + "MMC_CAP_SD_HIGHSPEED"; + f_min = <400000>; + f_max = <50000000>; + }; + + sdio { + caps = "MMC_CAP_4_BIT_DATA", + "MMC_CAP_MMC_HIGHSPEED", + "MMC_CAP_SD_HIGHSPEED", + "MMC_CAP_NONREMOVABLE", + "MMC_CAP_UHS_SDR12", + "MMC_CAP_UHS_SDR25", + "MMC_CAP_UHS_SDR50", + "MMC_CAP_UHS_SDR104", + "MMC_PM_KEEP_POWER", + "MMC_CAP_SDIO_IRQ"; + + f_min = <400000>; + f_max = <200000000>; + }; +}; + +&sd_emmc_a { + status = "disabled"; + sdio { + caps = "MMC_CAP_4_BIT_DATA", + "MMC_CAP_MMC_HIGHSPEED", + "MMC_CAP_SD_HIGHSPEED", + "MMC_CAP_NONREMOVABLE", + "MMC_CAP_UHS_SDR12", + "MMC_CAP_UHS_SDR25", + "MMC_CAP_UHS_SDR50", + "MMC_CAP_UHS_SDR104", + "MMC_PM_KEEP_POWER", + "MMC_CAP_SDIO_IRQ"; + f_min = <400000>; + f_max = <200000000>; + }; +}; + +&nand { + status = "disabled"; + plat-names = "bootloader","nandnormal"; + plat-num = <2>; + plat-part-0 = <&bootloader>; + plat-part-1 = <&nandnormal>; + bootloader: bootloader{ + enable_pad ="ce0"; + busy_pad = "rb0"; + timming_mode = "mode5"; + bch_mode = "bch8_1k"; + t_rea = <20>; + t_rhoh = <15>; + chip_num = <1>; + part_num = <0>; + rb_detect = <1>; + }; + nandnormal: nandnormal{ + enable_pad ="ce0"; + busy_pad = "rb0"; + timming_mode = "mode5"; + bch_mode = "bch8_1k"; + plane_mode = "twoplane"; + t_rea = <20>; + t_rhoh = <15>; + chip_num = <2>; + part_num = <3>; + partition = <&nand_partitions>; + rb_detect = <1>; + }; + nand_partitions:nand_partition{ + /* + * if bl_mode is 1, tpl size was generate by + * fip_copies * fip_size which + * will not skip bad when calculating + * the partition size; + * + * if bl_mode is 0, + * tpl partition must be comment out. + */ + tpl{ + offset=<0x0 0x0>; + size=<0x0 0x0>; + }; + logo{ + offset=<0x0 0x0>; + size=<0x0 0x200000>; + }; + recovery{ + offset=<0x0 0x0>; + size=<0x0 0x1000000>; + }; + boot{ + offset=<0x0 0x0>; + size=<0x0 0x1000000>; + }; + system{ + offset=<0x0 0x0>; + size=<0x0 0x4000000>; + }; + data{ + offset=<0xffffffff 0xffffffff>; + size=<0x0 0x0>; + }; + }; +}; + +&pcie_A { + reset-gpio = <&gpio GPIOX_7 GPIO_ACTIVE_HIGH>; + status = "disable"; +}; + +&meson_cooldev { + status = "okay"; +}; + +&saradc { + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/amlogic/g12a_s905x2_u211_512m.dts b/arch/arm/boot/dts/amlogic/g12a_s905x2_u211_512m.dts new file mode 100644 index 000000000000..17c90661cdce --- /dev/null +++ b/arch/arm/boot/dts/amlogic/g12a_s905x2_u211_512m.dts @@ -0,0 +1,1328 @@ +/* + * arch/arm/boot/dts/amlogic/g12a_s905x2_u211_512m.dts + * + * Copyright (C) 2017 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +/dts-v1/; + +#include "mesong12a.dtsi" +#include "partition_mbox_normal.dtsi" + +/ { + model = "Amlogic"; + compatible = "amlogic, g12a"; + interrupt-parent = <&gic>; + #address-cells = <1>; + #size-cells = <1>; + + aliases { + serial0 = &uart_AO; + serial1 = &uart_A; + serial2 = &uart_B; + serial3 = &uart_C; + serial4 = &uart_AO_B; + tsensor0 = &p_tsensor; + tsensor1 = &d_tsensor; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c_AO; + }; + + memory@00000000 { + device_type = "memory"; + linux,usable-memory = <0x0 0x20000000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + /* global autoconfigured region for contiguous allocations */ + ramoops@0x07400000 { + compatible = "ramoops"; + reg = <0x07400000 0x00100000>; + record-size = <0x8000>; + console-size = <0x8000>; + ftrace-size = <0x0>; + pmsg-size = <0x8000>; + }; + + secmon_reserved:linux,secmon { + compatible = "shared-dma-pool"; + reusable; + size = <0x400000>; + alignment = <0x400000>; + alloc-ranges = <0x05000000 0x400000>; + }; + secos_reserved:linux,secos { + status = "disable"; + compatible = "amlogic, aml_secos_memory"; + reg = <0x05300000 0x2000000>; + no-map; + }; + logo_reserved:linux,meson-fb { + compatible = "shared-dma-pool"; + reusable; + size = <0x800000>; + alignment = <0x400000>; + alloc-ranges = <0x1f800000 0x800000>; + }; + ion_cma_reserved:linux,ion-dev { + compatible = "shared-dma-pool"; + reusable; + size = <0x4000000>; + alignment = <0x400000>; + }; + //di_reserved:linux,di { + //compatible = "amlogic, di-mem"; + /* buffer_size = 3621952(yuv422 8bit) */ + /* 4179008(yuv422 10bit full pack mode) */ + /** 10x3621952=34.6M(0x23) support 8bit **/ + /** 10x4736064=45.2M(0x2e) support 12bit **/ + /** 10x4179008=40M(0x28) support 10bit **/ + //size = <0x2800000>; + //no-map; + //}; + /*di CMA pool */ + di_cma_reserved:linux,di_cma { + compatible = "shared-dma-pool"; + reusable; + /* buffer_size = 3621952(yuv422 8bit) + * | 4736064(yuv422 10bit) + * | 4074560(yuv422 10bit full pack mode) + * 10x3621952=34.6M(0x23) support 8bit + * 10x4736064=45.2M(0x2e) support 12bit + * 10x4074560=40M(0x28) support 10bit + */ + size = <0x0>; + alignment = <0x400000>; + }; + /* POST PROCESS MANAGER */ + ppmgr_reserved:linux,ppmgr { + compatible = "shared-dma-pool"; + size = <0x0>; + }; + + codec_mm_cma:linux,codec_mm_cma { + compatible = "shared-dma-pool"; + reusable; + /* ion_codec_mm max can alloc size 80M*/ + size = <0x4400000>; + alignment = <0x400000>; + linux,contiguous-region; + }; + /* codec shared reserved */ + codec_mm_reserved:linux,codec_mm_reserved { + compatible = "amlogic, codec-mm-reserved"; + size = <0x0>; + alignment = <0x100000>; + //no-map; + }; + /* vdin0 CMA pool */ + vdin0_cma_reserved:linux,vdin0_cma { + compatible = "shared-dma-pool"; + reusable; + /* 1920x1080x2x4 =16+4 M */ + size = <0x0>; + alignment = <0x400000>; + }; + /* vdin1 CMA pool */ + vdin1_cma_reserved:linux,vdin1_cma { + compatible = "shared-dma-pool"; + reusable; + /* 1920x1080x2x4 =16 M */ + size = <0x0>; + alignment = <0x400000>; + }; + }; + + gpioleds { + compatible = "gpio-leds"; + status = "okay"; + + net_red { + label="net_red"; + gpios=<&gpio GPIOA_14 GPIO_ACTIVE_LOW>; + default-state ="on"; + }; + + net_green { + label="net_green"; + gpios=<&gpio GPIOA_15 GPIO_ACTIVE_HIGH>; + default-state ="on"; + }; + + remote_led { + label = "remote_led"; + gpios = <&gpio_ao GPIOAO_10 GPIO_ACTIVE_LOW>; + default-state = "off"; + linux,default-trigger = "rc_feedback"; + }; + + sys_led { + label="sys_led"; + gpios=<&gpio_ao GPIOAO_11 GPIO_ACTIVE_LOW>; + default-state ="on"; + retain-state-suspended; + linux,default-trigger="cpu0"; + }; + }; + + cvbsout { + compatible = "amlogic, cvbsout-g12a"; + dev_name = "cvbsout"; + status = "okay"; + clocks = <&clkc CLKID_VCLK2_ENCI + &clkc CLKID_VCLK2_VENCI0 + &clkc CLKID_VCLK2_VENCI1 + &clkc CLKID_DAC_CLK>; + clock-names = "venci_top_gate", + "venci_0_gate", + "venci_1_gate", + "vdac_clk_gate"; + clk_path = <0>; + + /* performance: reg_address, reg_value */ + /* g12a */ + performance = <0x1bf0 0x9 + 0x1b56 0x333 + 0x1b12 0x8080 + 0x1b05 0xfd + 0x1c59 0xf850 + 0xffff 0x0>; /* ending flag */ + performance_sarft = <0x1bf0 0x9 + 0x1b56 0x333 + 0x1b12 0x0 + 0x1b05 0x9 + 0x1c59 0xfc48 + 0xffff 0x0>; /* ending flag */ + performance_revB_telecom = <0x1bf0 0x9 + 0x1b56 0x546 + 0x1b12 0x8080 + 0x1b05 0x9 + 0x1c59 0xf850 + 0xffff 0x0>; /* ending flag */ + }; + + bt-dev{ + compatible = "amlogic, bt-dev"; + dev_name = "bt-dev"; + status = "okay"; + gpio_reset = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>; + gpio_hostwake = <&gpio GPIOX_19 GPIO_ACTIVE_HIGH>; + }; + + wifi{ + compatible = "amlogic, aml_wifi"; + dev_name = "aml_wifi"; + status = "okay"; + interrupt_pin = <&gpio GPIOX_7 GPIO_ACTIVE_HIGH>; + irq_trigger_type = "GPIO_IRQ_LOW"; + power_on_pin = <&gpio GPIOX_6 GPIO_ACTIVE_HIGH>; + dhd_static_buf; //if use bcm wifi, config dhd_static_buf + pinctrl-names = "default"; + pinctrl-0 = <&pwm_e_pins>; + pwm_config = <&wifi_pwm_conf>; + }; + + wifi_pwm_conf:wifi_pwm_conf{ + pwm_channel1_conf { + pwms = <&pwm_ef MESON_PWM_0 30040 0>; + duty-cycle = <15020>; + times = <10>; + }; + pwm_channel2_conf { + pwms = <&pwm_ef MESON_PWM_2 30030 0>; + duty-cycle = <15015>; + times = <12>; + }; + }; + + codec_mm { + compatible = "amlogic, codec, mm"; + memory-region = <&codec_mm_cma &codec_mm_reserved>; + dev_name = "codec_mm"; + status = "okay"; + }; + + ppmgr { + compatible = "amlogic, ppmgr"; + memory-region = <&ppmgr_reserved>; + dev_name = "ppmgr"; + status = "okay"; + }; + + deinterlace { + compatible = "amlogic, deinterlace"; + status = "disable"; + /* 0:use reserved; 1:use cma; 2:use cma as reserved */ + flag_cma = <1>; + //memory-region = <&di_reserved>; + memory-region = <&di_cma_reserved>; + interrupts = <0 46 1 + 0 40 1>; + interrupt-names = "pre_irq", "post_irq"; + clocks = <&clkc CLKID_VPU_CLKB_TMP_COMP>, + <&clkc CLKID_VPU_CLKB_COMP>; + clock-names = "vpu_clkb_tmp_composite", + "vpu_clkb_composite"; + clock-range = <334 667>; + /* buffer-size = <3621952>;(yuv422 8bit) */ + buffer-size = <4074560>;/*yuv422 fullpack*/ + /* reserve-iomap = "true"; */ + /* if enable nr10bit, set nr10bit-support to 1 */ + post-wr-support = <1>; + nr10bit-support = <1>; + nrds-enable = <1>; + pps-enable = <1>; + }; + ionvideo { + compatible = "amlogic, ionvideo"; + dev_name = "ionvideo"; + status = "okay"; + }; + dvb{ + compatible = "amlogic, dvb"; + dev_name = "dvb"; + status = "ok"; + /*"parallel","serial","disable"*/ + ts2 = "parallel"; + ts2_control = <0>; + ts2_invert = <0>; + }; + unifykey{ + compatible = "amlogic, unifykey"; + status = "ok"; + unifykey-num = <15>; + unifykey-index-0 = <&keysn_0>; + unifykey-index-1 = <&keysn_1>; + unifykey-index-2 = <&keysn_2>; + unifykey-index-3 = <&keysn_3>; + unifykey-index-4 = <&keysn_4>; + unifykey-index-5 = <&keysn_5>; + unifykey-index-6 = <&keysn_6>; + unifykey-index-7 = <&keysn_7>; + unifykey-index-8 = <&keysn_8>; + unifykey-index-9 = <&keysn_9>; + unifykey-index-10= <&keysn_10>; + unifykey-index-11= <&keysn_11>; + unifykey-index-12= <&keysn_12>; + unifykey-index-13= <&keysn_13>; + unifykey-index-14= <&keysn_14>; + + keysn_0: key_0{ + key-name = "usid"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_1:key_1{ + key-name = "mac"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_2:key_2{ + key-name = "hdcp"; + key-device = "secure"; + key-type = "sha1"; + key-permit = "read","write","del"; + }; + keysn_3:key_3{ + key-name = "secure_boot_set"; + key-device = "efuse"; + key-permit = "write"; + }; + keysn_4:key_4{ + key-name = "mac_bt"; + key-device = "normal"; + key-permit = "read","write","del"; + key-type = "mac"; + }; + keysn_5:key_5{ + key-name = "mac_wifi"; + key-device = "normal"; + key-permit = "read","write","del"; + key-type = "mac"; + }; + keysn_6:key_6{ + key-name = "hdcp2_tx"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_7:key_7{ + key-name = "hdcp2_rx"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_8:key_8{ + key-name = "widevinekeybox"; + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_9:key_9{ + key-name = "deviceid"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_10:key_10{ + key-name = "hdcp22_fw_private"; + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_11:key_11{ + key-name = "PlayReadykeybox25"; + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_12:key_12{ + key-name = "prpubkeybox";// PlayReady + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_13:key_13{ + key-name = "prprivkeybox";// PlayReady + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_14:key_14{ + key-name = "attestationkeybox";// attestation key + key-device = "secure"; + key-permit = "read","write","del"; + }; + };//End unifykey + + efusekey:efusekey{ + keynum = <4>; + key0 = <&key_0>; + key1 = <&key_1>; + key2 = <&key_2>; + key3 = <&key_3>; + key_0:key_0{ + keyname = "mac"; + offset = <0>; + size = <6>; + }; + key_1:key_1{ + keyname = "mac_bt"; + offset = <6>; + size = <6>; + }; + key_2:key_2{ + keyname = "mac_wifi"; + offset = <12>; + size = <6>; + }; + key_3:key_3{ + keyname = "usid"; + offset = <18>; + size = <16>; + }; + };//End efusekey + + amlvecm { + compatible = "amlogic, vecm"; + dev_name = "aml_vecm"; + status = "okay"; + gamma_en = <0>;/*1:enabel ;0:disable*/ + wb_en = <0>;/*1:enabel ;0:disable*/ + cm_en = <0>;/*1:enabel ;0:disable*/ + }; + + amdolby_vision { + compatible = "amlogic, dolby_vision_g12a"; + dev_name = "aml_amdolby_vision_driver"; + status = "okay"; + tv_mode = <0>;/*1:enabel ;0:disable*/ + }; + + /* Audio Related start */ + pdm_codec:dummy{ + #sound-dai-cells = <0>; + compatible = "amlogic, pdm_dummy_codec"; + status = "okay"; + }; + dummy_codec:dummy{ + #sound-dai-cells = <0>; + compatible = "amlogic, aml_dummy_codec"; + status = "okay"; + }; + amlogic_codec:t9015{ + #sound-dai-cells = <0>; + compatible = "amlogic, aml_codec_T9015"; + reg = <0xFF632000 0x2000>; + is_auge_used = <1>; /* meson or auge chipset used */ + tdmout_index = <1>; + status = "okay"; + }; + audio_effect:eqdrc{ + /*eq_enable = <1>;*/ + /*drc_enable = <1>;*/ + /* + * 0:tdmout_a + * 1:tdmout_b + * 2:tdmout_c + * 3:spdifout + * 4:spdifout_b + */ + eqdrc_module = <1>; + /* max 0xf, each bit for one lane, usually one lane */ + lane_mask = <0x1>; + /* max 0xff, each bit for one channel */ + channel_mask = <0x3>; + }; + auge_sound { + compatible = "amlogic, g12a-sound-card"; + aml-audio-card,name = "AML-AUGESOUND"; + + aml-audio-card,loopback = <&aml_loopback>; + aml-audio-card,aux-devs = <&amlogic_codec>; + /*avout mute gpio*/ + avout_mute-gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_HIGH>; + /*for audio effect ,eqdrc */ + aml-audio-card,effect = <&audio_effect>; + + aml-audio-card,dai-link@0 { + format = "dsp_a"; + mclk-fs = <512>; + //continuous-clock; + //bitclock-inversion; + //frame-inversion; + //bitclock-master = <&tdmacodec>; + //frame-master = <&tdmacodec>; + /* suffix-name, sync with android audio hal + * what's the dai link used for + */ + suffix-name = "alsaPORT-pcm"; + tdmacpu: cpu { + sound-dai = <&aml_tdma>; + dai-tdm-slot-tx-mask = + <1 1 1 1 1 1 1 1>; + dai-tdm-slot-rx-mask = + <1 1 1 1 1 1 1 1>; + dai-tdm-slot-num = <8>; + dai-tdm-slot-width = <32>; + system-clock-frequency = <24576000>; + }; + tdmacodec: codec { + sound-dai = <&dummy_codec &dummy_codec>; + }; + }; + + aml-audio-card,dai-link@1 { + format = "i2s";// "dsp_a"; + mclk-fs = <256>; + //continuous-clock; + //bitclock-inversion; + //frame-inversion; + bitclock-master = <&aml_tdmb>; + frame-master = <&aml_tdmb>; + //bitclock-master = <&tdmbcodec>; + //frame-master = <&tdmbcodec>; + /* suffix-name, sync with android audio hal + * what's the dai link used for + */ + suffix-name = "alsaPORT-i2s"; + cpu { + sound-dai = <&aml_tdmb>; + dai-tdm-slot-tx-mask = <1 1>; + dai-tdm-slot-rx-mask = <1 1>; + dai-tdm-slot-num = <2>; + /* + * dai-tdm-slot-tx-mask = + * <1 1 1 1 1 1 1 1>; + * dai-tdm-slot-rx-mask = + * <1 1 1 1 1 1 1 1>; + * dai-tdm-slot-num = <8>; + */ + dai-tdm-slot-width = <32>; + system-clock-frequency = <12288000>; + }; + tdmbcodec: codec { + sound-dai = <&dummy_codec &dummy_codec + &amlogic_codec>; + }; + }; + + aml-audio-card,dai-link@2 { + format = "i2s"; + mclk-fs = <256>; + //continuous-clock; + //bitclock-inversion; + //frame-inversion; + bitclock-master = <&aml_tdmc>; + frame-master = <&aml_tdmc>; + /* suffix-name, sync with android audio hal + * what's the dai link used for + */ + //suffix-name = "alsaPORT-tdm"; + cpu { + sound-dai = <&aml_tdmc>; + dai-tdm-slot-tx-mask = <1 1>; + dai-tdm-slot-rx-mask = <1 1>; + dai-tdm-slot-num = <2>; + dai-tdm-slot-width = <32>; + system-clock-frequency = <12288000>; + }; + codec { + sound-dai = <&dummy_codec &dummy_codec>; + }; + }; + + aml-audio-card,dai-link@3 { + mclk-fs = <64>; + /* suffix-name, sync with android audio hal + * what's the dai link used for + */ + suffix-name = "alsaPORT-pdm"; + cpu { + sound-dai = <&aml_pdm>; + }; + codec { + sound-dai = <&pdm_codec>; + }; + }; + + aml-audio-card,dai-link@4 { + mclk-fs = <128>; + continuous-clock; + /* suffix-name, sync with android audio hal + * what's the dai link used for + */ + suffix-name = "alsaPORT-spdifb2hdmi"; + cpu { + sound-dai = <&aml_spdif>; + system-clock-frequency = <6144000>; + }; + codec { + sound-dai = <&dummy_codec>; + }; + }; + /* spdif_b to hdmi, only playback */ + aml-audio-card,dai-link@5 { + mclk-fs = <128>; + continuous-clock; + /* suffix-name, sync with android audio hal + * what's the dai link used for + */ + suffix-name = "alsaPORT-spdif"; + cpu { + sound-dai = <&aml_spdif_b>; + system-clock-frequency = <6144000>; + }; + codec { + sound-dai = <&dummy_codec>; + }; + }; + /* + * dai link for i2s to hdmix, + * Notice to select a tdm lane not used by hw + */ + /* + * aml-audio-card,dai-link@6 { + * format = "i2s"; + * mclk-fs = <256>; + * //continuous-clock; + * //bitclock-inversion; + * //frame-inversion; + * bitclock-master = <&aml_i2s2hdmi>; + * frame-master = <&aml_i2s2hdmi>; + * suffix-name = "alsaPORT-i2s2hdmi"; + * cpu { + * sound-dai = <&aml_i2s2hdmi>; + * dai-tdm-slot-tx-mask = <1 1>; + * dai-tdm-slot-num = <2>; + * dai-tdm-slot-width = <32>; + * system-clock-frequency = <12288000>; + * }; + * codec { + * sound-dai = <&dummy_codec>; + * }; + * }; + */ + }; + audiolocker: locker { + compatible = "amlogic, audiolocker"; + clocks = <&clkaudio CLKID_AUDIO_LOCKER_OUT + &clkaudio CLKID_AUDIO_LOCKER_IN + &clkaudio CLKID_AUDIO_MCLK_D + &clkaudio CLKID_AUDIO_MCLK_E + &clkc CLKID_MPLL1 + &clkc CLKID_MPLL2>; + clock-names = "lock_out", "lock_in", "out_src", + "in_src", "out_calc", "in_ref"; + interrupts = ; + interrupt-names = "irq"; + frequency = <49000000>; /* pll */ + dividor = <49>; /* locker's parent */ + status = "okay"; + }; + /* Audio Related end */ + + /*DCDC for SY8120B1ABC*/ + cpu_opp_table0: cpu_opp_table0 { + compatible = "operating-points-v2"; + opp-shared; + + opp00 { + opp-hz = /bits/ 64 <100000000>; + opp-microvolt = <731000>; + }; + opp01 { + opp-hz = /bits/ 64 <250000000>; + opp-microvolt = <731000>; + }; + opp02 { + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <731000>; + }; + opp03 { + opp-hz = /bits/ 64 <667000000>; + opp-microvolt = <731000>; + }; + opp04 { + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <731000>; + }; + opp05 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <761000>; + }; + opp06 { + opp-hz = /bits/ 64 <1398000000>; + opp-microvolt = <791000>; + }; + opp07 { + opp-hz = /bits/ 64 <1512000000>; + opp-microvolt = <831000>; + }; + opp08 { + opp-hz = /bits/ 64 <1608000000>; + opp-microvolt = <871000>; + }; + opp09 { + opp-hz = /bits/ 64 <1704000000>; + opp-microvolt = <921000>; + }; + opp10 { + opp-hz = /bits/ 64 <1800000000>; + opp-microvolt = <981000>; + }; + }; + + cpufreq-meson { + compatible = "amlogic, cpufreq-meson"; + pinctrl-names = "default"; + pinctrl-0 = <&pwm_ao_d_pins3>; + status = "okay"; + }; + +}; /* end of / */ + +&meson_fb { + status = "okay"; + display_size_default = <1920 1080 1920 2160 32>; + mem_size = <0x00800000 0x1980000 0x100000 0x100000 0x800000>; + logo_addr = "0x1f800000"; + mem_alloc = <0>; + pxp_mode = <0>; /** 0:normal mode 1:pxp mode */ +}; + +&pwm_AO_cd { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + pinctrl-names="default"; + pinctrl-0=<&i2c0_master_pins2>; + clock-frequency = <400000>; + + gt9xx@5d { + compatible = "goodix,gt9xx"; + status = "disabled"; + reg = <0x5d>; + reset-gpio = <&gpio GPIOZ_9 0x00>; + irq-gpio = <&gpio GPIOZ_3 0x00>; + }; + + ftxx@38 { + compatible = "focaltech,fts"; + status = "disabled"; + reg = <0x38>; + reset-gpio = <&gpio GPIOZ_9 0x00>; + irq-gpio = <&gpio GPIOZ_3 0x00>; + x_max = <600>; + y_max = <1024>; + max-touch-number = <10>; + }; +}; + +&i2c3 { + status = "disabled"; + pinctrl-names="default"; + pinctrl-0=<&i2c3_master_pins2>; + clock-frequency = <100000>; /* default 100k */ + + /* for ref board */ + ad82584f_62: ad82584f_62@62 { + compatible = "ESMT, ad82584f"; + #sound-dai-cells = <0>; + reg = <0x31>; + status = "disabled"; + reset_pin = <&gpio GPIOA_5 0>; + }; + + tas5707_36: tas5707_36@36 { + compatible = "ti,tas5707"; + #sound-dai-cells = <0>; + reg = <0x1b>; + status = "disabled"; + reset_pin = <&gpio GPIOA_5 0>; + }; + + bl_extern_i2c { + compatible = "amlogic, bl_extern_i2c"; + status = "disabled"; + reg = <0x2c>; /*reg_address for lp8556*/ + dev_name = "lp8556"; + }; +}; + +&audiobus { + aml_tdma: tdma { + compatible = "amlogic, g12a-snd-tdma"; + #sound-dai-cells = <0>; + dai-tdm-lane-slot-mask-in = <0 1>; + dai-tdm-oe-lane-slot-mask-out = <1 0>; + dai-tdm-clk-sel = <0>; + clocks = <&clkaudio CLKID_AUDIO_MCLK_A + &clkc CLKID_MPLL0>; + clock-names = "mclk", "clk_srcpll"; + pinctrl-names = "tdm_pins"; + pinctrl-0 = <&tdmout_a &tdmin_a>; + }; + + aml_tdmb: tdmb { + compatible = "amlogic, g12a-snd-tdmb"; + #sound-dai-cells = <0>; + dai-tdm-lane-slot-mask-in = <0 1 0 0>; + dai-tdm-lane-slot-mask-out = <1 0 0 0>; + dai-tdm-clk-sel = <1>; + clocks = <&clkaudio CLKID_AUDIO_MCLK_B + &clkc CLKID_MPLL1 + &clkc CLKID_MPLL0>; + clock-names = "mclk", "clk_srcpll", "samesource_sysclk"; + pinctrl-names = "tdm_pins"; + pinctrl-0 = <&tdmb_mclk &tdmout_b &tdmin_b>; + /* + * 0: tdmout_a; + * 1: tdmout_b; + * 2: tdmout_c; + * 3: spdifout; + * 4: spdifout_b; + */ + samesource_sel = <3>; + }; + + aml_tdmc: tdmc { + compatible = "amlogic, g12a-snd-tdmc"; + #sound-dai-cells = <0>; + dai-tdm-lane-slot-mask-in = <0 1 0 0>; + #dai-tdm-lane-slot-mask-out = <1 0 1 1>; + #dai-tdm-lane-oe-slot-mask-in = <0 0 0 0>; + dai-tdm-lane-oe-slot-mask-out = <1 0 0 0>; + dai-tdm-clk-sel = <2>; + clocks = <&clkaudio CLKID_AUDIO_MCLK_C + &clkc CLKID_MPLL2>; + clock-names = "mclk", "clk_srcpll"; + pinctrl-names = "tdm_pins"; + pinctrl-0 = <&tdmc_mclk &tdmout_c &tdmin_c>; + }; + + /* copy a useless tdm to output for hdmi, no pinmux */ + aml_i2s2hdmi: i2s2hdmi { + compatible = "amlogic, g12a-snd-tdmc"; + #sound-dai-cells = <0>; + dai-tdm-lane-slot-mask-out = <1 1 1 1>; + dai-tdm-clk-sel = <2>; + clocks = <&clkaudio CLKID_AUDIO_MCLK_C + &clkc CLKID_MPLL2>; + clock-names = "mclk", "clk_srcpll"; + + i2s2hdmi = <1>; + + status = "disabled"; + }; + + aml_spdif: spdif { + compatible = "amlogic, g12a-snd-spdif-a"; + #sound-dai-cells = <0>; + clocks = <&clkc CLKID_MPLL0 + &clkc CLKID_FCLK_DIV4 + &clkaudio CLKID_AUDIO_SPDIFIN + &clkaudio CLKID_AUDIO_SPDIFOUT + &clkaudio CLKID_AUDIO_SPDIFIN_CTRL + &clkaudio CLKID_AUDIO_SPDIFOUT_CTRL>; + clock-names = "sysclk", "fixed_clk", "gate_spdifin", + "gate_spdifout", "clk_spdifin", "clk_spdifout"; + interrupts = + ; + + interrupt-names = "irq_spdifin"; + pinctrl-names = "spdif_pins"; + pinctrl-0 = <&spdifout>; + status = "okay"; + }; + aml_spdif_b: spdif_b { + compatible = "amlogic, g12a-snd-spdif-b"; + #sound-dai-cells = <0>; + clocks = <&clkc CLKID_MPLL0 /*CLKID_HIFI_PLL*/ + &clkaudio CLKID_AUDIO_SPDIFOUTB + &clkaudio CLKID_AUDIO_SPDIFOUTB_CTRL>; + clock-names = "sysclk", + "gate_spdifout", "clk_spdifout"; + status = "okay"; + }; + aml_pdm: pdm { + compatible = "amlogic, g12a-snd-pdm"; + #sound-dai-cells = <0>; + clocks = <&clkaudio CLKID_AUDIO_PDM + &clkc CLKID_FCLK_DIV3 + &clkc CLKID_MPLL3 + &clkaudio CLKID_AUDIO_PDMIN0 + &clkaudio CLKID_AUDIO_PDMIN1>; + clock-names = "gate", + "sysclk_srcpll", + "dclk_srcpll", + "pdm_dclk", + "pdm_sysclk"; + pinctrl-names = "pdm_pins"; + pinctrl-0 = <&pdmin>; + filter_mode = <1>; /* mode 0~4, defalut:1 */ + status = "okay"; + }; + aml_loopback: loopback { + compatible = "amlogic, snd-loopback"; + /* + * 0: out rate = in data rate; + * 1: out rate = loopback data rate; + */ + lb_mode = <0>; + + /* datain src + * 0: tdmin_a; + * 1: tdmin_b; + * 2: tdmin_c; + * 3: spdifin; + * 4: pdmin; + */ + datain_src = <4>; + datain_chnum = <8>; + datain_chmask = <0x3f>; + + /* tdmin_lb src + * 0: tdmoutA + * 1: tdmoutB + * 2: tdmoutC + * 3: PAD_tdminA + * 4: PAD_tdminB + * 5: PAD_tdminC + */ + datalb_src = <2>; + datalb_chnum = <8>; + datalb_chmask = <0x3>; + + status = "okay"; + }; + + audioresample: resample { + compatible = "amlogic, g12a-resample"; + clocks = <&clkc CLKID_MPLL3 + &clkaudio CLKID_AUDIO_MCLK_F + &clkaudio CLKID_AUDIO_RESAMPLE_CTRL>; + clock-names = "resample_pll", "resample_src", "resample_clk"; + /*same with toddr_src + * TDMIN_A, 0 + * TDMIN_B, 1 + * TDMIN_C, 2 + * SPDIFIN, 3 + * PDMIN, 4 + * NONE, + * TDMIN_LB, 6 + * LOOPBACK, 7 + */ + resample_module = <4>; + status = "okay"; + }; + aml_pwrdet: pwrdet { + compatible = "amlogic, g12a-power-detect"; + + interrupts = ; + interrupt-names = "pwrdet_irq"; + + /* pwrdet source sel + * 7: loopback; + * 6: tdmin_lb; + * 5: reserved; + * 4: pdmin; + * 3: spdifin; + * 2: tdmin_c; + * 1: tdmin_b; + * 0: tdmin_a; + */ + pwrdet_src = <4>; + + hi_th = <0x70000>; + lo_th = <0x16000>; + + status = "disabled"; + }; +}; /* end of audiobus */ + +&pinctrl_periphs { + tdmout_a: tdmout_a { + mux { /* GPIOX_11, GPIOX_10, GPIOX_9 */ + groups = "tdma_sclk", + "tdma_fs", + "tdma_dout0"; + function = "tdma_out"; + }; + }; + + tdmin_a: tdmin_a { + mux { /* GPIOX_8 */ + groups = "tdma_din1"; + function = "tdma_in"; + }; + }; + + tdmb_mclk: tdmb_mclk { + mux { + groups = "mclk0_a"; + function = "mclk0"; + drive-strength = <2>; + }; + }; + tdmout_b: tdmout_b { + mux { /* GPIOA_1, GPIOA_2, GPIOA_3 */ + groups = "tdmb_sclk", + "tdmb_fs", + "tdmb_dout0"; + function = "tdmb_out"; + drive-strength = <2>; + }; + }; + + tdmin_b:tdmin_b { + mux { /* GPIOA_4 */ + groups = "tdmb_din1" + /*,"tdmb_slv_sclk", "tdmb_slv_fs"*/; + function = "tdmb_in"; + drive-strength = <2>; + }; + }; + + tdmc_mclk: tdmc_mclk { + mux { /* GPIOA_11 */ + groups = "mclk1_a"; + function = "mclk1"; + }; + }; + + tdmout_c:tdmout_c { + mux { /* GPIOA_12, GPIOA_13, GPIOA_10, GPIOA_8, GPIOA_7*/ + groups = "tdmc_sclk_a", + "tdmc_fs_a", + "tdmc_dout0_a" + /*, "tdmc_dout2", + * "tdmc_dout3" + */; + function = "tdmc_out"; + }; + }; + + tdmin_c:tdmin_c { + mux { /* GPIOA_9 */ + groups = "tdmc_din1_a"; + function = "tdmc_in"; + }; + }; + + spdifin: spdifin { + mux {/* GPIOH_5 */ + groups = "spdif_in_h"; + function = "spdif_in"; + }; + }; + + /* GPIOH_4 */ + spdifout: spdifout { + mux { + groups = "spdif_out_h"; + function = "spdif_out"; + }; + }; + + pdmin: pdmin { + mux { /* gpioa_5, gpioa_6, gpioa_7, gpioa_8, gpioa_9*/ + groups = "pdm_din0_a", + /*"pdm_din1_a",*/ + "pdm_din2_a", + /*"pdm_din3_a",*/ + "pdm_dclk_a"; + function = "pdm"; + }; + }; + + +}; /* end of pinctrl_periphs */ +&pinctrl_aobus { + /*gpiao_10*/ + /*spdifout: spdifout { */ + /* mux { */ + /* groups = "spdif_out_ao"; */ + /* function = "spdif_out_ao";*/ + /* }; */ + /*}; */ +}; /* end of pinctrl_aobus */ + +&audio_data { + status = "okay"; +}; + +/* Audio Related End */ + +&pwm_ef { + status = "okay"; +}; + +&dwc3 { + status = "okay"; +}; + +&usb2_phy_v2 { + status = "okay"; + portnum = <2>; +}; + +&usb3_phy_v2 { + status = "okay"; + portnum = <1>; + otg = <0>; +}; + +&dwc2_a { + status = "okay"; + /** 0: normal, 1: otg+dwc3 host only, 2: otg+dwc3 device only*/ + controller-type = <1>; +}; +ðmac { + status = "okay"; + pinctrl-names = "internal_eth_pins"; + pinctrl-0 = <&internal_eth_pins>; + mc_val = <0x4be04>; + + internal_phy=<1>; +}; + +&uart_A { + status = "okay"; +}; + +/*if you want to use vdin just modify status to "ok"*/ +&vdin0 { + memory-region = <&vdin0_cma_reserved>; + status = "disable"; + /*vdin write mem color depth support: + *bit0:support 8bit + *bit1:support 9bit + *bit2:support 10bit + *bit3:support 12bit + *bit4:support yuv422 10bit full pack mode (from txl new add) + */ + tv_bit_mode = <0x15>; +}; +&vdin1 { + memory-region = <&vdin1_cma_reserved>; + status = "disable"; + /*vdin write mem color depth support: + *bit0:support 8bit + *bit1:support 9bit + *bit2:support 10bit + *bit3:support 12bit + */ + tv_bit_mode = <1>; +}; + + +&sd_emmc_c { + status = "okay"; + emmc { + caps = "MMC_CAP_8_BIT_DATA", + "MMC_CAP_MMC_HIGHSPEED", + "MMC_CAP_SD_HIGHSPEED", + "MMC_CAP_NONREMOVABLE", + /* "MMC_CAP_1_8V_DDR", */ + "MMC_CAP_HW_RESET", + "MMC_CAP_ERASE", + "MMC_CAP_CMD23"; + caps2 = "MMC_CAP2_HS200"; + /* "MMC_CAP2_HS400";*/ + f_min = <400000>; + f_max = <200000000>; + }; +}; + +&sd_emmc_b1 { + status = "disabled"; + sd { + caps = "MMC_CAP_4_BIT_DATA", + "MMC_CAP_MMC_HIGHSPEED", + "MMC_CAP_SD_HIGHSPEED"; + f_min = <400000>; + f_max = <50000000>; + }; +}; + +&sd_emmc_b2 { + status = "disabled"; + sd { + caps = "MMC_CAP_4_BIT_DATA", + "MMC_CAP_MMC_HIGHSPEED", + "MMC_CAP_SD_HIGHSPEED"; + f_min = <400000>; + f_max = <50000000>; + }; + + sdio { + caps = "MMC_CAP_4_BIT_DATA", + "MMC_CAP_MMC_HIGHSPEED", + "MMC_CAP_SD_HIGHSPEED", + "MMC_CAP_NONREMOVABLE", + "MMC_CAP_UHS_SDR12", + "MMC_CAP_UHS_SDR25", + "MMC_CAP_UHS_SDR50", + "MMC_CAP_UHS_SDR104", + "MMC_PM_KEEP_POWER", + "MMC_CAP_SDIO_IRQ"; + + f_min = <400000>; + f_max = <200000000>; + }; +}; + +&sd_emmc_a { + status = "disabled"; + sdio { + caps = "MMC_CAP_4_BIT_DATA", + "MMC_CAP_MMC_HIGHSPEED", + "MMC_CAP_SD_HIGHSPEED", + "MMC_CAP_NONREMOVABLE", + "MMC_CAP_UHS_SDR12", + "MMC_CAP_UHS_SDR25", + "MMC_CAP_UHS_SDR50", + "MMC_CAP_UHS_SDR104", + "MMC_PM_KEEP_POWER", + "MMC_CAP_SDIO_IRQ"; + f_min = <400000>; + f_max = <200000000>; + }; +}; + +&nand { + status = "disabled"; + plat-names = "bootloader","nandnormal"; + plat-num = <2>; + plat-part-0 = <&bootloader>; + plat-part-1 = <&nandnormal>; + bootloader: bootloader{ + enable_pad ="ce0"; + busy_pad = "rb0"; + timming_mode = "mode5"; + bch_mode = "bch8_1k"; + t_rea = <20>; + t_rhoh = <15>; + chip_num = <1>; + part_num = <0>; + rb_detect = <1>; + }; + nandnormal: nandnormal{ + enable_pad ="ce0"; + busy_pad = "rb0"; + timming_mode = "mode5"; + bch_mode = "bch8_1k"; + plane_mode = "twoplane"; + t_rea = <20>; + t_rhoh = <15>; + chip_num = <2>; + part_num = <3>; + partition = <&nand_partitions>; + rb_detect = <1>; + }; + nand_partitions:nand_partition{ + /* + * if bl_mode is 1, tpl size was generate by + * fip_copies * fip_size which + * will not skip bad when calculating + * the partition size; + * + * if bl_mode is 0, + * tpl partition must be comment out. + */ + tpl{ + offset=<0x0 0x0>; + size=<0x0 0x0>; + }; + logo{ + offset=<0x0 0x0>; + size=<0x0 0x200000>; + }; + recovery{ + offset=<0x0 0x0>; + size=<0x0 0x1000000>; + }; + boot{ + offset=<0x0 0x0>; + size=<0x0 0x1000000>; + }; + system{ + offset=<0x0 0x0>; + size=<0x0 0x4000000>; + }; + data{ + offset=<0xffffffff 0xffffffff>; + size=<0x0 0x0>; + }; + }; +}; + +&pcie_A { + reset-gpio = <&gpio GPIOX_7 GPIO_ACTIVE_HIGH>; + status = "disable"; +}; + +&meson_cooldev { + status = "okay"; +}; + +&saradc { + status = "disabled"; +}; + +&defendkey { + status = "okay"; +}; + diff --git a/arch/arm/boot/dts/amlogic/g12a_s905x2_u211_buildroot.dts b/arch/arm/boot/dts/amlogic/g12a_s905x2_u211_buildroot.dts new file mode 100644 index 000000000000..ba27ad58f4e2 --- /dev/null +++ b/arch/arm/boot/dts/amlogic/g12a_s905x2_u211_buildroot.dts @@ -0,0 +1,1364 @@ +/* + * arch/arm/boot/dts/amlogic/g12a_s905x2_u211_buildroot.dts + * + * Copyright (C) 2017 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +/dts-v1/; + +#include "mesong12a.dtsi" + +/ { + model = "Amlogic"; + compatible = "amlogic, g12a"; + interrupt-parent = <&gic>; + #address-cells = <1>; + #size-cells = <1>; + + aliases { + serial0 = &uart_AO; + serial1 = &uart_A; + serial2 = &uart_B; + serial3 = &uart_C; + serial4 = &uart_AO_B; + tsensor0 = &p_tsensor; + tsensor1 = &d_tsensor; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c_AO; + }; + + memory@00000000 { + device_type = "memory"; + linux,usable-memory = <0x100000 0x7ff00000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + /* global autoconfigured region for contiguous allocations */ + secmon_reserved:linux,secmon { + compatible = "shared-dma-pool"; + reusable; + size = <0x400000>; + alignment = <0x400000>; + alloc-ranges = <0x05000000 0x400000>; + }; + secos_reserved:linux,secos { + status = "disable"; + compatible = "amlogic, aml_secos_memory"; + reg = <0x05300000 0x2000000>; + no-map; + }; + logo_reserved:linux,meson-fb { + compatible = "shared-dma-pool"; + reusable; + size = <0x800000>; + alignment = <0x400000>; + alloc-ranges = <0x7f800000 0x800000>; + }; + ion_cma_reserved:linux,ion-dev { + compatible = "shared-dma-pool"; + reusable; + size = <0x8000000>; + alignment = <0x400000>; + }; + //di_reserved:linux,di { + //compatible = "amlogic, di-mem"; + /* buffer_size = 3621952(yuv422 8bit) */ + /* 4179008(yuv422 10bit full pack mode) */ + /** 10x3621952=34.6M(0x23) support 8bit **/ + /** 10x4736064=45.2M(0x2e) support 12bit **/ + /** 10x4179008=40M(0x28) support 10bit **/ + //size = <0x2800000>; + //no-map; + //}; + /*di CMA pool */ + di_cma_reserved:linux,di_cma { + compatible = "shared-dma-pool"; + reusable; + /* buffer_size = 3621952(yuv422 8bit) + * | 4736064(yuv422 10bit) + * | 4074560(yuv422 10bit full pack mode) + * 10x3621952=34.6M(0x23) support 8bit + * 10x4736064=45.2M(0x2e) support 12bit + * 10x4074560=40M(0x28) support 10bit + */ + size = <0x02800000>; + alignment = <0x400000>; + }; + /* POST PROCESS MANAGER */ + ppmgr_reserved:linux,ppmgr { + compatible = "shared-dma-pool"; + size = <0x0>; + }; + + codec_mm_cma:linux,codec_mm_cma { + compatible = "shared-dma-pool"; + reusable; + /* ion_codec_mm max can alloc size 80M*/ + size = <0x13400000>; + alignment = <0x400000>; + linux,contiguous-region; + }; + /* codec shared reserved */ + codec_mm_reserved:linux,codec_mm_reserved { + compatible = "amlogic, codec-mm-reserved"; + size = <0x0>; + alignment = <0x100000>; + //no-map; + }; + /* vdin0 CMA pool */ + vdin0_cma_reserved:linux,vdin0_cma { + compatible = "shared-dma-pool"; + reusable; + /* 1920x1080x2x4 =16+4 M */ + size = <0x04000000>; + alignment = <0x400000>; + }; + /* vdin1 CMA pool */ + vdin1_cma_reserved:linux,vdin1_cma { + compatible = "shared-dma-pool"; + reusable; + /* 1920x1080x2x4 =16 M */ + size = <0x04000000>; + alignment = <0x400000>; + }; + }; + + gpioleds { + compatible = "gpio-leds"; + status = "okay"; + + net_red { + label="net_red"; + gpios=<&gpio GPIOA_14 GPIO_ACTIVE_LOW>; + default-state ="on"; + }; + + net_green { + label="net_green"; + gpios=<&gpio GPIOA_15 GPIO_ACTIVE_HIGH>; + default-state ="on"; + }; + + remote_led { + label = "remote_led"; + gpios = <&gpio_ao GPIOAO_10 GPIO_ACTIVE_LOW>; + default-state = "off"; + linux,default-trigger = "rc_feedback"; + }; + + sys_led { + label="sys_led"; + gpios=<&gpio_ao GPIOAO_11 GPIO_ACTIVE_LOW>; + default-state ="on"; + retain-state-suspended; + linux,default-trigger="cpu0"; + }; + }; + + cvbsout { + compatible = "amlogic, cvbsout-g12a"; + dev_name = "cvbsout"; + status = "okay"; + clocks = <&clkc CLKID_VCLK2_ENCI + &clkc CLKID_VCLK2_VENCI0 + &clkc CLKID_VCLK2_VENCI1 + &clkc CLKID_DAC_CLK>; + clock-names = "venci_top_gate", + "venci_0_gate", + "venci_1_gate", + "vdac_clk_gate"; + clk_path = <0>; + + /* performance: reg_address, reg_value */ + /* g12a */ + performance = <0x1bf0 0x9 + 0x1b56 0x343 + 0x1b12 0x0 + 0x1b05 0x9 + 0x1c59 0xfc48 + 0xffff 0x0>; /* ending flag */ + performance_telecom = <0x1bf0 0x9 + 0x1b56 0x333 + 0x1b12 0x8080 + 0x1b05 0xfd + 0x1c59 0xf850 + 0xffff 0x0>; /* ending flag */ + }; + + bt-dev{ + compatible = "amlogic, bt-dev"; + dev_name = "bt-dev"; + status = "okay"; + gpio_reset = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>; + gpio_hostwake = <&gpio GPIOX_19 GPIO_ACTIVE_HIGH>; + }; + + wifi{ + compatible = "amlogic, aml_wifi"; + dev_name = "aml_wifi"; + status = "okay"; + interrupt_pin = <&gpio GPIOX_7 GPIO_ACTIVE_HIGH>; + irq_trigger_type = "GPIO_IRQ_LOW"; + power_on_pin = <&gpio GPIOX_6 GPIO_ACTIVE_HIGH>; + dhd_static_buf; //if use bcm wifi, config dhd_static_buf + pinctrl-names = "default"; + pinctrl-0 = <&pwm_e_pins>; + pwm_config = <&wifi_pwm_conf>; + }; + + wifi_pwm_conf:wifi_pwm_conf{ + pwm_channel1_conf { + pwms = <&pwm_ef MESON_PWM_0 30040 0>; + duty-cycle = <15020>; + times = <10>; + }; + pwm_channel2_conf { + pwms = <&pwm_ef MESON_PWM_2 30030 0>; + duty-cycle = <15015>; + times = <12>; + }; + }; + + codec_mm { + compatible = "amlogic, codec, mm"; + memory-region = <&codec_mm_cma &codec_mm_reserved>; + dev_name = "codec_mm"; + status = "okay"; + }; + + ppmgr { + compatible = "amlogic, ppmgr"; + memory-region = <&ppmgr_reserved>; + dev_name = "ppmgr"; + status = "okay"; + }; + + deinterlace { + compatible = "amlogic, deinterlace"; + status = "okay"; + /* 0:use reserved; 1:use cma; 2:use cma as reserved */ + flag_cma = <1>; + //memory-region = <&di_reserved>; + memory-region = <&di_cma_reserved>; + interrupts = <0 46 1 + 0 40 1>; + interrupt-names = "pre_irq", "post_irq"; + clocks = <&clkc CLKID_VPU_CLKB_TMP_COMP>, + <&clkc CLKID_VPU_CLKB_COMP>; + clock-names = "vpu_clkb_tmp_composite", + "vpu_clkb_composite"; + clock-range = <334 667>; + /* buffer-size = <3621952>;(yuv422 8bit) */ + buffer-size = <4074560>;/*yuv422 fullpack*/ + /* reserve-iomap = "true"; */ + /* if enable nr10bit, set nr10bit-support to 1 */ + post-wr-support = <1>; + nr10bit-support = <1>; + nrds-enable = <1>; + pps-enable = <1>; + }; + ionvideo { + compatible = "amlogic, ionvideo"; + dev_name = "ionvideo"; + status = "okay"; + }; + + + partitions: partitions{ + parts = <14>; + part-0 = <&logo>; + part-1 = <&recovery>; + part-2 = <&misc>; + part-3 = <&dto>; + part-4 = <&cri_data>; + part-5 = <¶m>; + part-6 = <&boot>; + part-7 = <&rsv>; + part-8 = <&tee>; + part-9 = <&vendor>; + part-10 = <&odm>; + part-11 = <&system>; + part-12 = <&cache>; + part-13 = <&data>; + + logo:logo{ + pname = "logo"; + size = <0x0 0x800000>; + mask = <1>; + }; + recovery:recovery{ + pname = "recovery"; + size = <0x0 0x1800000>; + mask = <1>; + }; + misc:misc{ + pname = "misc"; + size = <0x0 0x800000>; + mask = <1>; + }; + dto:dto{ + pname = "dto"; + size = <0x0 0x800000>; + mask = <1>; + }; + cri_data:cri_data{ + pname = "cri_data"; + size = <0x0 0x800000>; + mask = <2>; + }; + rsv:rsv{ + pname = "rsv"; + size = <0x0 0x1000000>; + mask = <1>; + }; + param:param{ + pname = "param"; + size = <0x0 0x1000000>; + mask = <2>; + }; + boot:boot{ + pname = "boot"; + size = <0x0 0x1000000>; + mask = <1>; + }; + tee:tee{ + pname = "tee"; + size = <0x0 0x2000000>; + mask = <1>; + }; + vendor:vendor{ + pname = "vendor"; + size = <0x0 0x10000000>; + mask = <1>; + }; + odm:odm{ + pname = "odm"; + size = <0x0 0x10000000>; + mask = <1>; + }; + system:system{ + pname = "system"; + size = <0x0 0x80000000>; + mask = <1>; + }; + cache:cache{ + pname = "cache"; + size = <0x0 0x46000000>; + mask = <2>; + }; + data:data{ + pname = "data"; + size = <0xffffffff 0xffffffff>; + mask = <4>; + }; + }; + unifykey{ + compatible = "amlogic, unifykey"; + status = "ok"; + unifykey-num = <15>; + unifykey-index-0 = <&keysn_0>; + unifykey-index-1 = <&keysn_1>; + unifykey-index-2 = <&keysn_2>; + unifykey-index-3 = <&keysn_3>; + unifykey-index-4 = <&keysn_4>; + unifykey-index-5 = <&keysn_5>; + unifykey-index-6 = <&keysn_6>; + unifykey-index-7 = <&keysn_7>; + unifykey-index-8 = <&keysn_8>; + unifykey-index-9 = <&keysn_9>; + unifykey-index-10= <&keysn_10>; + unifykey-index-11= <&keysn_11>; + unifykey-index-12= <&keysn_12>; + unifykey-index-13= <&keysn_13>; + unifykey-index-14= <&keysn_14>; + + keysn_0: key_0{ + key-name = "usid"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_1:key_1{ + key-name = "mac"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_2:key_2{ + key-name = "hdcp"; + key-device = "secure"; + key-type = "sha1"; + key-permit = "read","write","del"; + }; + keysn_3:key_3{ + key-name = "secure_boot_set"; + key-device = "efuse"; + key-permit = "write"; + }; + keysn_4:key_4{ + key-name = "mac_bt"; + key-device = "normal"; + key-permit = "read","write","del"; + key-type = "mac"; + }; + keysn_5:key_5{ + key-name = "mac_wifi"; + key-device = "normal"; + key-permit = "read","write","del"; + key-type = "mac"; + }; + keysn_6:key_6{ + key-name = "hdcp2_tx"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_7:key_7{ + key-name = "hdcp2_rx"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_8:key_8{ + key-name = "widevinekeybox"; + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_9:key_9{ + key-name = "deviceid"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_10:key_10{ + key-name = "hdcp22_fw_private"; + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_11:key_11{ + key-name = "PlayReadykeybox25"; + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_12:key_12{ + key-name = "prpubkeybox";// PlayReady + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_13:key_13{ + key-name = "prprivkeybox";// PlayReady + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_14:key_14{ + key-name = "attestationkeybox";// attestation key + key-device = "secure"; + key-permit = "read","write","del"; + }; + };//End unifykey + + efusekey:efusekey{ + keynum = <4>; + key0 = <&key_0>; + key1 = <&key_1>; + key2 = <&key_2>; + key3 = <&key_3>; + key_0:key_0{ + keyname = "mac"; + offset = <0>; + size = <6>; + }; + key_1:key_1{ + keyname = "mac_bt"; + offset = <6>; + size = <6>; + }; + key_2:key_2{ + keyname = "mac_wifi"; + offset = <12>; + size = <6>; + }; + key_3:key_3{ + keyname = "usid"; + offset = <18>; + size = <16>; + }; + };//End efusekey + + amlvecm { + compatible = "amlogic, vecm"; + dev_name = "aml_vecm"; + status = "okay"; + gamma_en = <0>;/*1:enabel ;0:disable*/ + wb_en = <0>;/*1:enabel ;0:disable*/ + cm_en = <0>;/*1:enabel ;0:disable*/ + /*0: 709/601 1: bt2020*/ + tx_op_color_primary = <0>; + }; + + amdolby_vision { + compatible = "amlogic, dolby_vision_g12a"; + dev_name = "aml_amdolby_vision_driver"; + status = "okay"; + tv_mode = <0>;/*1:enabel ;0:disable*/ + }; + + meson-fb { + compatible = "amlogic, meson-g12a"; + /*memory-region = <&logo_reserved>;*/ + dev_name = "meson-fb"; + status = "okay"; + interrupts = <0 3 1 + 0 56 1 + 0 89 1>; + interrupt-names = "viu-vsync", "viu2-vsync", "rdma"; + mem_size = <0x00800000 0x1980000 0x100000 0x100000 0x800000>; + /* uboot logo,fb0/fb1 memory size,if afbcd fb0=0x01851000*/ + display_mode_default = "1080p60hz"; + scale_mode = <1>; + /** 0:VPU free scale 1:OSD free scale 2:OSD super scale */ + display_size_default = <1920 1080 1920 2160 32>; + /*1920*1080*4*3 = 0x17BB000*/ + pxp_mode = <0>; /** 0:normal mode 1:pxp mode */ + mem_alloc = <1>; + logo_addr = "0x3f800000"; + clocks = <&clkc CLKID_VPU_CLKC_MUX>; + clock-names = "vpu_clkc"; + }; + + /* Audio Related start */ + pdm_codec:dummy{ + #sound-dai-cells = <0>; + compatible = "amlogic, pdm_dummy_codec"; + status = "okay"; + }; + dummy_codec:dummy{ + #sound-dai-cells = <0>; + compatible = "amlogic, aml_dummy_codec"; + status = "okay"; + }; + amlogic_codec:t9015{ + #sound-dai-cells = <0>; + compatible = "amlogic, aml_codec_T9015"; + reg = <0xFF632000 0x2000>; + is_auge_used = <1>; /* meson or auge chipset used */ + tdmout_index = <1>; + status = "okay"; + }; + audio_effect:eqdrc{ + /*eq_enable = <1>;*/ + /*drc_enable = <1>;*/ + /* + * 0:tdmout_a + * 1:tdmout_b + * 2:tdmout_c + * 3:spdifout + * 4:spdifout_b + */ + eqdrc_module = <1>; + /* max 0xf, each bit for one lane, usually one lane */ + lane_mask = <0x1>; + /* max 0xff, each bit for one channel */ + channel_mask = <0x3>; + }; + auge_sound { + compatible = "amlogic, g12a-sound-card"; + aml-audio-card,name = "AML-AUGESOUND"; + + aml-audio-card,loopback = <&aml_loopback>; + aml-audio-card,aux-devs = <&amlogic_codec>; + /*avout mute gpio*/ + avout_mute-gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_HIGH>; + /*for audio effect ,eqdrc */ + aml-audio-card,effect = <&audio_effect>; + + aml-audio-card,dai-link@0 { + format = "dsp_a"; + mclk-fs = <512>; + //continuous-clock; + //bitclock-inversion; + //frame-inversion; + //bitclock-master = <&tdmacodec>; + //frame-master = <&tdmacodec>; + /* suffix-name, sync with android audio hal + * what's the dai link used for + */ + suffix-name = "alsaPORT-pcm"; + tdmacpu: cpu { + sound-dai = <&aml_tdma>; + dai-tdm-slot-tx-mask = + <1 1 1 1 1 1 1 1>; + dai-tdm-slot-rx-mask = + <1 1 1 1 1 1 1 1>; + dai-tdm-slot-num = <8>; + dai-tdm-slot-width = <32>; + system-clock-frequency = <24576000>; + }; + tdmacodec: codec { + sound-dai = <&dummy_codec &dummy_codec>; + }; + }; + + aml-audio-card,dai-link@1 { + format = "i2s";// "dsp_a"; + mclk-fs = <256>; + //continuous-clock; + //bitclock-inversion; + //frame-inversion; + bitclock-master = <&aml_tdmb>; + frame-master = <&aml_tdmb>; + //bitclock-master = <&tdmbcodec>; + //frame-master = <&tdmbcodec>; + /* suffix-name, sync with android audio hal + * what's the dai link used for + */ + suffix-name = "alsaPORT-i2s"; + cpu { + sound-dai = <&aml_tdmb>; + dai-tdm-slot-tx-mask = <1 1>; + dai-tdm-slot-rx-mask = <1 1>; + dai-tdm-slot-num = <2>; + /* + * dai-tdm-slot-tx-mask = + * <1 1 1 1 1 1 1 1>; + * dai-tdm-slot-rx-mask = + * <1 1 1 1 1 1 1 1>; + * dai-tdm-slot-num = <8>; + */ + dai-tdm-slot-width = <32>; + system-clock-frequency = <12288000>; + }; + tdmbcodec: codec { + sound-dai = <&dummy_codec &dummy_codec + &amlogic_codec>; + }; + }; + + aml-audio-card,dai-link@2 { + format = "i2s"; + mclk-fs = <256>; + //continuous-clock; + //bitclock-inversion; + //frame-inversion; + bitclock-master = <&aml_tdmc>; + frame-master = <&aml_tdmc>; + /* suffix-name, sync with android audio hal + * what's the dai link used for + */ + //suffix-name = "alsaPORT-tdm"; + cpu { + sound-dai = <&aml_tdmc>; + dai-tdm-slot-tx-mask = <1 1>; + dai-tdm-slot-rx-mask = <1 1>; + dai-tdm-slot-num = <2>; + dai-tdm-slot-width = <32>; + system-clock-frequency = <12288000>; + }; + codec { + sound-dai = <&dummy_codec &dummy_codec>; + }; + }; + + aml-audio-card,dai-link@3 { + mclk-fs = <64>; + /* suffix-name, sync with android audio hal + * what's the dai link used for + */ + suffix-name = "alsaPORT-pdm"; + cpu { + sound-dai = <&aml_pdm>; + }; + codec { + sound-dai = <&pdm_codec>; + }; + }; + + aml-audio-card,dai-link@4 { + mclk-fs = <128>; + /* suffix-name, sync with android audio hal + * what's the dai link used for + */ + suffix-name = "alsaPORT-spdif"; + cpu { + sound-dai = <&aml_spdif>; + system-clock-frequency = <6144000>; + }; + codec { + sound-dai = <&dummy_codec>; + }; + }; + /* spdif_b to hdmi, only playback */ + aml-audio-card,dai-link@5 { + mclk-fs = <128>; + continuous-clock; + /* suffix-name, sync with android audio hal + * what's the dai link used for + */ + suffix-name = "alsaPORT-spdifb2hdmi"; + cpu { + sound-dai = <&aml_spdif_b>; + system-clock-frequency = <6144000>; + }; + codec { + sound-dai = <&dummy_codec>; + }; + }; + }; + audiolocker: locker { + compatible = "amlogic, audiolocker"; + clocks = <&clkaudio CLKID_AUDIO_LOCKER_OUT + &clkaudio CLKID_AUDIO_LOCKER_IN + &clkaudio CLKID_AUDIO_MCLK_D + &clkaudio CLKID_AUDIO_MCLK_E + &clkc CLKID_MPLL1 + &clkc CLKID_MPLL2>; + clock-names = "lock_out", "lock_in", "out_src", + "in_src", "out_calc", "in_ref"; + interrupts = ; + interrupt-names = "irq"; + frequency = <49000000>; /* pll */ + dividor = <49>; /* locker's parent */ + status = "okay"; + }; + /* Audio Related end */ + + /*DCDC for SY8120B1ABC*/ + cpu_opp_table0: cpu_opp_table0 { + compatible = "operating-points-v2"; + opp-shared; + + opp00 { + opp-hz = /bits/ 64 <100000000>; + opp-microvolt = <731000>; + }; + opp01 { + opp-hz = /bits/ 64 <250000000>; + opp-microvolt = <731000>; + }; + opp02 { + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <731000>; + }; + opp03 { + opp-hz = /bits/ 64 <667000000>; + opp-microvolt = <731000>; + }; + opp04 { + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <731000>; + }; + opp05 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <731000>; + }; + opp06 { + opp-hz = /bits/ 64 <1398000000>; + opp-microvolt = <761000>; + }; + opp07 { + opp-hz = /bits/ 64 <1512000000>; + opp-microvolt = <791000>; + }; + opp08 { + opp-hz = /bits/ 64 <1608000000>; + opp-microvolt = <831000>; + }; + opp09 { + opp-hz = /bits/ 64 <1704000000>; + opp-microvolt = <861000>; + }; + opp10 { + opp-hz = /bits/ 64 <1800000000>; + opp-microvolt = <981000>; + }; + }; + + cpufreq-meson { + compatible = "amlogic, cpufreq-meson"; + pinctrl-names = "default"; + pinctrl-0 = <&pwm_ao_d_pins3>; + status = "okay"; + }; + +}; /* end of / */ + +&pwm_AO_cd { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + pinctrl-names="default"; + pinctrl-0=<&i2c0_master_pins2>; + clock-frequency = <400000>; + + gt9xx@5d { + compatible = "goodix,gt9xx"; + status = "disabled"; + reg = <0x5d>; + reset-gpio = <&gpio GPIOZ_9 0x00>; + irq-gpio = <&gpio GPIOZ_3 0x00>; + }; + + ftxx@38 { + compatible = "focaltech,fts"; + status = "disabled"; + reg = <0x38>; + reset-gpio = <&gpio GPIOZ_9 0x00>; + irq-gpio = <&gpio GPIOZ_3 0x00>; + x_max = <600>; + y_max = <1024>; + max-touch-number = <10>; + }; +}; + +&i2c3 { + status = "disabled"; + pinctrl-names="default"; + pinctrl-0=<&i2c3_master_pins2>; + clock-frequency = <100000>; /* default 100k */ + + /* for ref board */ + ad82584f_62: ad82584f_62@62 { + compatible = "ESMT, ad82584f"; + #sound-dai-cells = <0>; + reg = <0x31>; + status = "disabled"; + reset_pin = <&gpio GPIOA_5 0>; + }; + + tas5707_36: tas5707_36@36 { + compatible = "ti,tas5707"; + #sound-dai-cells = <0>; + reg = <0x1b>; + status = "disabled"; + reset_pin = <&gpio GPIOA_5 0>; + }; + + bl_extern_i2c { + compatible = "amlogic, bl_extern_i2c"; + status = "disabled"; + reg = <0x2c>; /*reg_address for lp8556*/ + dev_name = "lp8556"; + }; +}; + +&audiobus { + aml_tdma: tdma { + compatible = "amlogic, g12a-snd-tdma"; + #sound-dai-cells = <0>; + dai-tdm-lane-slot-mask-in = <0 1>; + dai-tdm-oe-lane-slot-mask-out = <1 0>; + dai-tdm-clk-sel = <0>; + clocks = <&clkaudio CLKID_AUDIO_MCLK_A + &clkc CLKID_MPLL0>; + clock-names = "mclk", "clk_srcpll"; + pinctrl-names = "tdm_pins"; + pinctrl-0 = <&tdmout_a &tdmin_a>; + }; + + aml_tdmb: tdmb { + compatible = "amlogic, g12a-snd-tdmb"; + #sound-dai-cells = <0>; + dai-tdm-lane-slot-mask-in = <0 1 0 0>; + dai-tdm-lane-slot-mask-out = <1 0 0 0>; + dai-tdm-clk-sel = <1>; + clocks = <&clkaudio CLKID_AUDIO_MCLK_B + &clkc CLKID_MPLL1 + &clkc CLKID_MPLL0>; + clock-names = "mclk", "clk_srcpll", "samesource_sysclk"; + pinctrl-names = "tdm_pins"; + pinctrl-0 = <&tdmb_mclk &tdmout_b &tdmin_b>; + /* + * 0: tdmout_a; + * 1: tdmout_b; + * 2: tdmout_c; + * 3: spdifout; + * 4: spdifout_b; + */ + samesource_sel = <3>; + }; + + aml_tdmc: tdmc { + compatible = "amlogic, g12a-snd-tdmc"; + #sound-dai-cells = <0>; + dai-tdm-lane-slot-mask-in = <0 1 0 0>; + #dai-tdm-lane-slot-mask-out = <1 0 1 1>; + #dai-tdm-lane-oe-slot-mask-in = <0 0 0 0>; + dai-tdm-lane-oe-slot-mask-out = <1 0 0 0>; + dai-tdm-clk-sel = <2>; + clocks = <&clkaudio CLKID_AUDIO_MCLK_C + &clkc CLKID_MPLL2>; + clock-names = "mclk", "clk_srcpll"; + pinctrl-names = "tdm_pins"; + pinctrl-0 = <&tdmc_mclk &tdmout_c &tdmin_c>; + }; + + + aml_spdif: spdif { + compatible = "amlogic, g12a-snd-spdif-a"; + #sound-dai-cells = <0>; + clocks = <&clkc CLKID_MPLL0 + &clkc CLKID_FCLK_DIV4 + &clkaudio CLKID_AUDIO_SPDIFIN + &clkaudio CLKID_AUDIO_SPDIFOUT + &clkaudio CLKID_AUDIO_SPDIFIN_CTRL + &clkaudio CLKID_AUDIO_SPDIFOUT_CTRL>; + clock-names = "sysclk", "fixed_clk", "gate_spdifin", + "gate_spdifout", "clk_spdifin", "clk_spdifout"; + interrupts = + ; + + interrupt-names = "irq_spdifin"; + pinctrl-names = "spdif_pins"; + pinctrl-0 = <&spdifout>; + status = "okay"; + }; + aml_spdif_b: spdif_b { + compatible = "amlogic, g12a-snd-spdif-b"; + #sound-dai-cells = <0>; + clocks = <&clkc CLKID_MPLL0 /*CLKID_HIFI_PLL*/ + &clkaudio CLKID_AUDIO_SPDIFOUTB + &clkaudio CLKID_AUDIO_SPDIFOUTB_CTRL>; + clock-names = "sysclk", + "gate_spdifout", "clk_spdifout"; + status = "okay"; + }; + aml_pdm: pdm { + compatible = "amlogic, g12a-snd-pdm"; + #sound-dai-cells = <0>; + clocks = <&clkaudio CLKID_AUDIO_PDM + &clkc CLKID_FCLK_DIV3 + &clkc CLKID_MPLL3 + &clkaudio CLKID_AUDIO_PDMIN0 + &clkaudio CLKID_AUDIO_PDMIN1>; + clock-names = "gate", + "sysclk_srcpll", + "dclk_srcpll", + "pdm_dclk", + "pdm_sysclk"; + pinctrl-names = "pdm_pins"; + pinctrl-0 = <&pdmin>; + filter_mode = <1>; /* mode 0~4, defalut:1 */ + status = "okay"; + }; + aml_loopback: loopback { + compatible = "amlogic, snd-loopback"; + /* + * 0: out rate = in data rate; + * 1: out rate = loopback data rate; + */ + lb_mode = <0>; + + /* datain src + * 0: tdmin_a; + * 1: tdmin_b; + * 2: tdmin_c; + * 3: spdifin; + * 4: pdmin; + */ + datain_src = <4>; + datain_chnum = <8>; + datain_chmask = <0x3f>; + + /* tdmin_lb src + * 0: tdmoutA + * 1: tdmoutB + * 2: tdmoutC + * 3: PAD_tdminA + * 4: PAD_tdminB + * 5: PAD_tdminC + */ + datalb_src = <2>; + datalb_chnum = <8>; + datalb_chmask = <0x3>; + + status = "okay"; + }; + + audioresample: resample { + compatible = "amlogic, g12a-resample"; + clocks = <&clkc CLKID_MPLL3 + &clkaudio CLKID_AUDIO_MCLK_F + &clkaudio CLKID_AUDIO_RESAMPLE_CTRL>; + clock-names = "resample_pll", "resample_src", "resample_clk"; + /*same with toddr_src + * TDMIN_A, 0 + * TDMIN_B, 1 + * TDMIN_C, 2 + * SPDIFIN, 3 + * PDMIN, 4 + * NONE, + * TDMIN_LB, 6 + * LOOPBACK, 7 + */ + resample_module = <4>; + status = "okay"; + }; + aml_pwrdet: pwrdet { + compatible = "amlogic, g12a-power-detect"; + + interrupts = ; + interrupt-names = "pwrdet_irq"; + + /* pwrdet source sel + * 7: loopback; + * 6: tdmin_lb; + * 5: reserved; + * 4: pdmin; + * 3: spdifin; + * 2: tdmin_c; + * 1: tdmin_b; + * 0: tdmin_a; + */ + pwrdet_src = <4>; + + hi_th = <0x70000>; + lo_th = <0x16000>; + + status = "okay"; + }; +}; /* end of audiobus */ + +&pinctrl_periphs { + tdmout_a: tdmout_a { + mux { /* GPIOX_11, GPIOX_10, GPIOX_9 */ + groups = "tdma_sclk", + "tdma_fs", + "tdma_dout0"; + function = "tdma_out"; + }; + }; + + tdmin_a: tdmin_a { + mux { /* GPIOX_8 */ + groups = "tdma_din1"; + function = "tdma_in"; + }; + }; + + tdmb_mclk: tdmb_mclk { + mux { + groups = "mclk0_a"; + function = "mclk0"; + drive-strength = <2>; + }; + }; + tdmout_b: tdmout_b { + mux { /* GPIOA_1, GPIOA_2, GPIOA_3 */ + groups = "tdmb_sclk", + "tdmb_fs", + "tdmb_dout0"; + function = "tdmb_out"; + drive-strength = <2>; + }; + }; + + tdmin_b:tdmin_b { + mux { /* GPIOA_4 */ + groups = "tdmb_din1" + /*,"tdmb_slv_sclk", "tdmb_slv_fs"*/; + function = "tdmb_in"; + drive-strength = <2>; + }; + }; + + tdmc_mclk: tdmc_mclk { + mux { /* GPIOA_11 */ + groups = "mclk1_a"; + function = "mclk1"; + }; + }; + + tdmout_c:tdmout_c { + mux { /* GPIOA_12, GPIOA_13, GPIOA_10, GPIOA_8, GPIOA_7*/ + groups = "tdmc_sclk_a", + "tdmc_fs_a", + "tdmc_dout0_a" + /*, "tdmc_dout2", + * "tdmc_dout3" + */; + function = "tdmc_out"; + }; + }; + + tdmin_c:tdmin_c { + mux { /* GPIOA_9 */ + groups = "tdmc_din1_a"; + function = "tdmc_in"; + }; + }; + + spdifin: spdifin { + mux {/* GPIOH_5 */ + groups = "spdif_in_h"; + function = "spdif_in"; + }; + }; + + /* GPIOH_4 */ + spdifout: spdifout { + mux { + groups = "spdif_out_h"; + function = "spdif_out"; + }; + }; + + pdmin: pdmin { + mux { /* gpioa_5, gpioa_6, gpioa_7, gpioa_8, gpioa_9*/ + groups = "pdm_din0_a", + /*"pdm_din1_a",*/ + "pdm_din2_a", + /*"pdm_din3_a",*/ + "pdm_dclk_a"; + function = "pdm"; + }; + }; + + +}; /* end of pinctrl_periphs */ +&pinctrl_aobus { + /*gpiao_10*/ + /*spdifout: spdifout { */ + /* mux { */ + /* groups = "spdif_out_ao"; */ + /* function = "spdif_out_ao";*/ + /* }; */ + /*}; */ +}; /* end of pinctrl_aobus */ + +&audio_data { + status = "okay"; +}; + +/* Audio Related End */ + +&pwm_ef { + status = "okay"; +}; + +&dwc3 { + status = "okay"; +}; + +&usb2_phy_v2 { + status = "okay"; + portnum = <2>; +}; + +&usb3_phy_v2 { + status = "okay"; + portnum = <1>; + otg = <0>; +}; + +&dwc2_a { + status = "okay"; + /** 0: normal, 1: otg+dwc3 host only, 2: otg+dwc3 device only*/ + controller-type = <1>; +}; +ðmac { + status = "okay"; + pinctrl-names = "internal_eth_pins"; + pinctrl-0 = <&internal_eth_pins>; + mc_val = <0x4be04>; + + internal_phy=<1>; +}; + +&uart_A { + status = "okay"; +}; + +/*if you want to use vdin just modify status to "ok"*/ +&vdin0 { + memory-region = <&vdin0_cma_reserved>; + status = "okay"; + /*vdin write mem color depth support: + *bit0:support 8bit + *bit1:support 9bit + *bit2:support 10bit + *bit3:support 12bit + *bit4:support yuv422 10bit full pack mode (from txl new add) + */ + tv_bit_mode = <0x15>; +}; +&vdin1 { + memory-region = <&vdin1_cma_reserved>; + status = "okay"; + /*vdin write mem color depth support: + *bit0:support 8bit + *bit1:support 9bit + *bit2:support 10bit + *bit3:support 12bit + */ + tv_bit_mode = <1>; +}; + + +&sd_emmc_c { + status = "okay"; + emmc { + caps = "MMC_CAP_8_BIT_DATA", + "MMC_CAP_MMC_HIGHSPEED", + "MMC_CAP_SD_HIGHSPEED", + "MMC_CAP_NONREMOVABLE", + /* "MMC_CAP_1_8V_DDR", */ + "MMC_CAP_HW_RESET", + "MMC_CAP_ERASE", + "MMC_CAP_CMD23"; + caps2 = "MMC_CAP2_HS200"; + /* "MMC_CAP2_HS400";*/ + f_min = <400000>; + f_max = <200000000>; + }; +}; + +&sd_emmc_b1 { + status = "disabled"; + sd { + caps = "MMC_CAP_4_BIT_DATA", + "MMC_CAP_MMC_HIGHSPEED", + "MMC_CAP_SD_HIGHSPEED"; + f_min = <400000>; + f_max = <50000000>; + }; +}; + +&sd_emmc_b2 { + status = "disabled"; + sd { + caps = "MMC_CAP_4_BIT_DATA", + "MMC_CAP_MMC_HIGHSPEED", + "MMC_CAP_SD_HIGHSPEED"; + f_min = <400000>; + f_max = <50000000>; + }; + + sdio { + caps = "MMC_CAP_4_BIT_DATA", + "MMC_CAP_MMC_HIGHSPEED", + "MMC_CAP_SD_HIGHSPEED", + "MMC_CAP_NONREMOVABLE", + "MMC_CAP_UHS_SDR12", + "MMC_CAP_UHS_SDR25", + "MMC_CAP_UHS_SDR50", + "MMC_CAP_UHS_SDR104", + "MMC_PM_KEEP_POWER", + "MMC_CAP_SDIO_IRQ"; + + f_min = <400000>; + f_max = <200000000>; + }; +}; + +&sd_emmc_a { + status = "disabled"; + sdio { + caps = "MMC_CAP_4_BIT_DATA", + "MMC_CAP_MMC_HIGHSPEED", + "MMC_CAP_SD_HIGHSPEED", + "MMC_CAP_NONREMOVABLE", + "MMC_CAP_UHS_SDR12", + "MMC_CAP_UHS_SDR25", + "MMC_CAP_UHS_SDR50", + "MMC_CAP_UHS_SDR104", + "MMC_PM_KEEP_POWER", + "MMC_CAP_SDIO_IRQ"; + f_min = <400000>; + f_max = <200000000>; + }; +}; + +&nand { + status = "disabled"; + plat-names = "bootloader","nandnormal"; + plat-num = <2>; + plat-part-0 = <&bootloader>; + plat-part-1 = <&nandnormal>; + bootloader: bootloader{ + enable_pad ="ce0"; + busy_pad = "rb0"; + timming_mode = "mode5"; + bch_mode = "bch8_1k"; + t_rea = <20>; + t_rhoh = <15>; + chip_num = <1>; + part_num = <0>; + rb_detect = <1>; + }; + nandnormal: nandnormal{ + enable_pad ="ce0"; + busy_pad = "rb0"; + timming_mode = "mode5"; + bch_mode = "bch8_1k"; + plane_mode = "twoplane"; + t_rea = <20>; + t_rhoh = <15>; + chip_num = <2>; + part_num = <3>; + partition = <&nand_partitions>; + rb_detect = <1>; + }; + nand_partitions:nand_partition{ + /* + * if bl_mode is 1, tpl size was generate by + * fip_copies * fip_size which + * will not skip bad when calculating + * the partition size; + * + * if bl_mode is 0, + * tpl partition must be comment out. + */ + tpl{ + offset=<0x0 0x0>; + size=<0x0 0x0>; + }; + logo{ + offset=<0x0 0x0>; + size=<0x0 0x200000>; + }; + recovery{ + offset=<0x0 0x0>; + size=<0x0 0x1000000>; + }; + boot{ + offset=<0x0 0x0>; + size=<0x0 0x1000000>; + }; + system{ + offset=<0x0 0x0>; + size=<0x0 0x4000000>; + }; + data{ + offset=<0xffffffff 0xffffffff>; + size=<0x0 0x0>; + }; + }; +}; + +&pcie_A { + reset-gpio = <&gpio GPIOX_7 GPIO_ACTIVE_HIGH>; + status = "disable"; +}; + +&meson_cooldev { + status = "okay"; +}; + +&defendkey { + status = "okay"; +}; + diff --git a/arch/arm/boot/dts/amlogic/g12a_s905x2_u212.dts b/arch/arm/boot/dts/amlogic/g12a_s905x2_u212.dts index 278d4c8d4839..1004379dd191 100644 --- a/arch/arm/boot/dts/amlogic/g12a_s905x2_u212.dts +++ b/arch/arm/boot/dts/amlogic/g12a_s905x2_u212.dts @@ -80,7 +80,7 @@ reusable; size = <0x800000>; alignment = <0x400000>; - alloc-ranges = <0x7f700000 0x800000>; + alloc-ranges = <0x7f800000 0x800000>; }; ion_cma_reserved:linux,ion-dev { compatible = "shared-dma-pool"; @@ -151,14 +151,14 @@ }; }; - dummy-battery { + amlogic_battery:dummy-battery { compatible = "amlogic, dummy-battery"; - status = "okay"; + status = "disabled"; }; - dummy-charger { + amlogic_charger:dummy-charger { compatible = "amlogic, dummy-charger"; - status = "okay"; + status = "disabled"; }; gpioleds { diff --git a/arch/arm/boot/dts/amlogic/g12a_s905x2_u212_1g.dts b/arch/arm/boot/dts/amlogic/g12a_s905x2_u212_1g.dts index aeb9cb0ddd09..547e68b264fc 100644 --- a/arch/arm/boot/dts/amlogic/g12a_s905x2_u212_1g.dts +++ b/arch/arm/boot/dts/amlogic/g12a_s905x2_u212_1g.dts @@ -83,6 +83,15 @@ alignment = <0x400000>; alloc-ranges = <0x3f800000 0x800000>; }; + codec_mm_cma:linux,codec_mm_cma { + compatible = "shared-dma-pool"; + reusable; + /* ion_codec_mm max can alloc size 80M*/ + size = <0xd000000>; + alignment = <0x400000>; + linux,contiguous-region; + alloc-ranges = <0x30000000 0x10000000>; + }; ion_cma_reserved:linux,ion-dev { compatible = "shared-dma-pool"; reusable; @@ -113,6 +122,7 @@ */ size = <0x02800000>; alignment = <0x400000>; + alloc-ranges = <0x30000000 0x10000000>; }; /* POST PROCESS MANAGER */ ppmgr_reserved:linux,ppmgr { @@ -120,15 +130,6 @@ size = <0x0>; }; - codec_mm_cma:linux,codec_mm_cma { - compatible = "shared-dma-pool"; - reusable; - /* ion_codec_mm max can alloc size 80M*/ - size = <0xd000000>; - alignment = <0x400000>; - linux,contiguous-region; - alloc-ranges = <0x00000000 0x30000000>; - }; /* codec shared reserved */ codec_mm_reserved:linux,codec_mm_reserved { compatible = "amlogic, codec-mm-reserved"; @@ -151,17 +152,18 @@ /* 1920x1080x2x4 =16 M */ size = <0x01000000>; alignment = <0x400000>; + alloc-ranges = <0x0 0x30000000>; }; }; - dummy-battery { + amlogic_battery:dummy-battery { compatible = "amlogic, dummy-battery"; - status = "okay"; + status = "disabled"; }; - dummy-charger { + amlogic_charger:dummy-charger { compatible = "amlogic, dummy-charger"; - status = "okay"; + status = "disabled"; }; gpioleds { diff --git a/arch/arm/boot/dts/amlogic/g12a_s905x2_u212_buildroot.dts b/arch/arm/boot/dts/amlogic/g12a_s905x2_u212_buildroot.dts new file mode 100644 index 000000000000..f70de86ef708 --- /dev/null +++ b/arch/arm/boot/dts/amlogic/g12a_s905x2_u212_buildroot.dts @@ -0,0 +1,1364 @@ +/* + * arch/arm/boot/dts/amlogic/g12a_s905x2_u212_buildroot.dts + * + * Copyright (C) 2017 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +/dts-v1/; + +#include "mesong12a.dtsi" + +/ { + model = "Amlogic"; + compatible = "amlogic, g12a"; + interrupt-parent = <&gic>; + #address-cells = <1>; + #size-cells = <1>; + + aliases { + serial0 = &uart_AO; + serial1 = &uart_A; + serial2 = &uart_B; + serial3 = &uart_C; + serial4 = &uart_AO_B; + tsensor0 = &p_tsensor; + tsensor1 = &d_tsensor; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c_AO; + }; + + memory@00000000 { + device_type = "memory"; + linux,usable-memory = <0x100000 0x7ff00000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + /* global autoconfigured region for contiguous allocations */ + secmon_reserved:linux,secmon { + compatible = "shared-dma-pool"; + reusable; + size = <0x400000>; + alignment = <0x400000>; + alloc-ranges = <0x05000000 0x400000>; + }; + secos_reserved:linux,secos { + status = "disable"; + compatible = "amlogic, aml_secos_memory"; + reg = <0x05300000 0x2000000>; + no-map; + }; + logo_reserved:linux,meson-fb { + compatible = "shared-dma-pool"; + reusable; + size = <0x800000>; + alignment = <0x400000>; + alloc-ranges = <0x7f800000 0x800000>; + }; + ion_cma_reserved:linux,ion-dev { + compatible = "shared-dma-pool"; + reusable; + size = <0x8000000>; + alignment = <0x400000>; + }; + //di_reserved:linux,di { + //compatible = "amlogic, di-mem"; + /* buffer_size = 3621952(yuv422 8bit) */ + /* 4179008(yuv422 10bit full pack mode) */ + /** 10x3621952=34.6M(0x23) support 8bit **/ + /** 10x4736064=45.2M(0x2e) support 12bit **/ + /** 10x4179008=40M(0x28) support 10bit **/ + //size = <0x2800000>; + //no-map; + //}; + /*di CMA pool */ + di_cma_reserved:linux,di_cma { + compatible = "shared-dma-pool"; + reusable; + /* buffer_size = 3621952(yuv422 8bit) + * | 4736064(yuv422 10bit) + * | 4074560(yuv422 10bit full pack mode) + * 10x3621952=34.6M(0x23) support 8bit + * 10x4736064=45.2M(0x2e) support 12bit + * 10x4074560=40M(0x28) support 10bit + */ + size = <0x02800000>; + alignment = <0x400000>; + }; + /* POST PROCESS MANAGER */ + ppmgr_reserved:linux,ppmgr { + compatible = "shared-dma-pool"; + size = <0x0>; + }; + + codec_mm_cma:linux,codec_mm_cma { + compatible = "shared-dma-pool"; + reusable; + /* ion_codec_mm max can alloc size 80M*/ + size = <0x13400000>; + alignment = <0x400000>; + linux,contiguous-region; + }; + /* codec shared reserved */ + codec_mm_reserved:linux,codec_mm_reserved { + compatible = "amlogic, codec-mm-reserved"; + size = <0x0>; + alignment = <0x100000>; + //no-map; + }; + /* vdin0 CMA pool */ + vdin0_cma_reserved:linux,vdin0_cma { + compatible = "shared-dma-pool"; + reusable; + /* 1920x1080x2x4 =16+4 M */ + size = <0x04000000>; + alignment = <0x400000>; + }; + /* vdin1 CMA pool */ + vdin1_cma_reserved:linux,vdin1_cma { + compatible = "shared-dma-pool"; + reusable; + /* 1920x1080x2x4 =16 M */ + size = <0x04000000>; + alignment = <0x400000>; + }; + }; + + gpioleds { + compatible = "gpio-leds"; + status = "okay"; + + net_red { + label="net_red"; + gpios=<&gpio GPIOA_14 GPIO_ACTIVE_LOW>; + default-state ="on"; + }; + + net_green { + label="net_green"; + gpios=<&gpio GPIOA_15 GPIO_ACTIVE_HIGH>; + default-state ="on"; + }; + + remote_led { + label = "remote_led"; + gpios = <&gpio_ao GPIOAO_10 GPIO_ACTIVE_LOW>; + default-state = "off"; + linux,default-trigger = "rc_feedback"; + }; + + sys_led { + label="sys_led"; + gpios=<&gpio_ao GPIOAO_11 GPIO_ACTIVE_LOW>; + default-state ="on"; + retain-state-suspended; + linux,default-trigger="cpu0"; + }; + }; + + cvbsout { + compatible = "amlogic, cvbsout-g12a"; + dev_name = "cvbsout"; + status = "okay"; + clocks = <&clkc CLKID_VCLK2_ENCI + &clkc CLKID_VCLK2_VENCI0 + &clkc CLKID_VCLK2_VENCI1 + &clkc CLKID_DAC_CLK>; + clock-names = "venci_top_gate", + "venci_0_gate", + "venci_1_gate", + "vdac_clk_gate"; + clk_path = <0>; + + /* performance: reg_address, reg_value */ + /* g12a */ + performance = <0x1bf0 0x9 + 0x1b56 0x343 + 0x1b12 0x0 + 0x1b05 0x9 + 0x1c59 0xfc48 + 0xffff 0x0>; /* ending flag */ + performance_telecom = <0x1bf0 0x9 + 0x1b56 0x333 + 0x1b12 0x8080 + 0x1b05 0xfd + 0x1c59 0xf850 + 0xffff 0x0>; /* ending flag */ + }; + + bt-dev{ + compatible = "amlogic, bt-dev"; + dev_name = "bt-dev"; + status = "okay"; + gpio_reset = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>; + gpio_hostwake = <&gpio GPIOX_19 GPIO_ACTIVE_HIGH>; + }; + + wifi{ + compatible = "amlogic, aml_wifi"; + dev_name = "aml_wifi"; + status = "okay"; + interrupt_pin = <&gpio GPIOX_7 GPIO_ACTIVE_HIGH>; + irq_trigger_type = "GPIO_IRQ_LOW"; + power_on_pin = <&gpio GPIOX_6 GPIO_ACTIVE_HIGH>; + dhd_static_buf; //if use bcm wifi, config dhd_static_buf + pinctrl-names = "default"; + pinctrl-0 = <&pwm_e_pins>; + pwm_config = <&wifi_pwm_conf>; + }; + + wifi_pwm_conf:wifi_pwm_conf{ + pwm_channel1_conf { + pwms = <&pwm_ef MESON_PWM_0 30040 0>; + duty-cycle = <15020>; + times = <10>; + }; + pwm_channel2_conf { + pwms = <&pwm_ef MESON_PWM_2 30030 0>; + duty-cycle = <15015>; + times = <12>; + }; + }; + + codec_mm { + compatible = "amlogic, codec, mm"; + memory-region = <&codec_mm_cma &codec_mm_reserved>; + dev_name = "codec_mm"; + status = "okay"; + }; + + ppmgr { + compatible = "amlogic, ppmgr"; + memory-region = <&ppmgr_reserved>; + dev_name = "ppmgr"; + status = "okay"; + }; + + deinterlace { + compatible = "amlogic, deinterlace"; + status = "okay"; + /* 0:use reserved; 1:use cma; 2:use cma as reserved */ + flag_cma = <1>; + //memory-region = <&di_reserved>; + memory-region = <&di_cma_reserved>; + interrupts = <0 46 1 + 0 40 1>; + interrupt-names = "pre_irq", "post_irq"; + clocks = <&clkc CLKID_VPU_CLKB_TMP_COMP>, + <&clkc CLKID_VPU_CLKB_COMP>; + clock-names = "vpu_clkb_tmp_composite", + "vpu_clkb_composite"; + clock-range = <334 667>; + /* buffer-size = <3621952>;(yuv422 8bit) */ + buffer-size = <4074560>;/*yuv422 fullpack*/ + /* reserve-iomap = "true"; */ + /* if enable nr10bit, set nr10bit-support to 1 */ + post-wr-support = <1>; + nr10bit-support = <1>; + nrds-enable = <1>; + pps-enable = <1>; + }; + ionvideo { + compatible = "amlogic, ionvideo"; + dev_name = "ionvideo"; + status = "okay"; + }; + + + partitions: partitions{ + parts = <14>; + part-0 = <&logo>; + part-1 = <&recovery>; + part-2 = <&misc>; + part-3 = <&dto>; + part-4 = <&cri_data>; + part-5 = <¶m>; + part-6 = <&boot>; + part-7 = <&rsv>; + part-8 = <&tee>; + part-9 = <&vendor>; + part-10 = <&odm>; + part-11 = <&system>; + part-12 = <&cache>; + part-13 = <&data>; + + logo:logo{ + pname = "logo"; + size = <0x0 0x800000>; + mask = <1>; + }; + recovery:recovery{ + pname = "recovery"; + size = <0x0 0x1800000>; + mask = <1>; + }; + misc:misc{ + pname = "misc"; + size = <0x0 0x800000>; + mask = <1>; + }; + dto:dto{ + pname = "dto"; + size = <0x0 0x800000>; + mask = <1>; + }; + cri_data:cri_data{ + pname = "cri_data"; + size = <0x0 0x800000>; + mask = <2>; + }; + rsv:rsv{ + pname = "rsv"; + size = <0x0 0x1000000>; + mask = <1>; + }; + param:param{ + pname = "param"; + size = <0x0 0x1000000>; + mask = <2>; + }; + boot:boot{ + pname = "boot"; + size = <0x0 0x1000000>; + mask = <1>; + }; + tee:tee{ + pname = "tee"; + size = <0x0 0x2000000>; + mask = <1>; + }; + vendor:vendor{ + pname = "vendor"; + size = <0x0 0x10000000>; + mask = <1>; + }; + odm:odm{ + pname = "odm"; + size = <0x0 0x10000000>; + mask = <1>; + }; + system:system{ + pname = "system"; + size = <0x0 0x80000000>; + mask = <1>; + }; + cache:cache{ + pname = "cache"; + size = <0x0 0x46000000>; + mask = <2>; + }; + data:data{ + pname = "data"; + size = <0xffffffff 0xffffffff>; + mask = <4>; + }; + }; + unifykey{ + compatible = "amlogic, unifykey"; + status = "ok"; + unifykey-num = <15>; + unifykey-index-0 = <&keysn_0>; + unifykey-index-1 = <&keysn_1>; + unifykey-index-2 = <&keysn_2>; + unifykey-index-3 = <&keysn_3>; + unifykey-index-4 = <&keysn_4>; + unifykey-index-5 = <&keysn_5>; + unifykey-index-6 = <&keysn_6>; + unifykey-index-7 = <&keysn_7>; + unifykey-index-8 = <&keysn_8>; + unifykey-index-9 = <&keysn_9>; + unifykey-index-10= <&keysn_10>; + unifykey-index-11= <&keysn_11>; + unifykey-index-12= <&keysn_12>; + unifykey-index-13= <&keysn_13>; + unifykey-index-14= <&keysn_14>; + + keysn_0: key_0{ + key-name = "usid"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_1:key_1{ + key-name = "mac"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_2:key_2{ + key-name = "hdcp"; + key-device = "secure"; + key-type = "sha1"; + key-permit = "read","write","del"; + }; + keysn_3:key_3{ + key-name = "secure_boot_set"; + key-device = "efuse"; + key-permit = "write"; + }; + keysn_4:key_4{ + key-name = "mac_bt"; + key-device = "normal"; + key-permit = "read","write","del"; + key-type = "mac"; + }; + keysn_5:key_5{ + key-name = "mac_wifi"; + key-device = "normal"; + key-permit = "read","write","del"; + key-type = "mac"; + }; + keysn_6:key_6{ + key-name = "hdcp2_tx"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_7:key_7{ + key-name = "hdcp2_rx"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_8:key_8{ + key-name = "widevinekeybox"; + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_9:key_9{ + key-name = "deviceid"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_10:key_10{ + key-name = "hdcp22_fw_private"; + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_11:key_11{ + key-name = "PlayReadykeybox25"; + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_12:key_12{ + key-name = "prpubkeybox";// PlayReady + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_13:key_13{ + key-name = "prprivkeybox";// PlayReady + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_14:key_14{ + key-name = "attestationkeybox";// attestation key + key-device = "secure"; + key-permit = "read","write","del"; + }; + };//End unifykey + + efusekey:efusekey{ + keynum = <4>; + key0 = <&key_0>; + key1 = <&key_1>; + key2 = <&key_2>; + key3 = <&key_3>; + key_0:key_0{ + keyname = "mac"; + offset = <0>; + size = <6>; + }; + key_1:key_1{ + keyname = "mac_bt"; + offset = <6>; + size = <6>; + }; + key_2:key_2{ + keyname = "mac_wifi"; + offset = <12>; + size = <6>; + }; + key_3:key_3{ + keyname = "usid"; + offset = <18>; + size = <16>; + }; + };//End efusekey + + amlvecm { + compatible = "amlogic, vecm"; + dev_name = "aml_vecm"; + status = "okay"; + gamma_en = <0>;/*1:enabel ;0:disable*/ + wb_en = <0>;/*1:enabel ;0:disable*/ + cm_en = <0>;/*1:enabel ;0:disable*/ + /*0: 709/601 1: bt2020*/ + tx_op_color_primary = <0>; + }; + + amdolby_vision { + compatible = "amlogic, dolby_vision_g12a"; + dev_name = "aml_amdolby_vision_driver"; + status = "okay"; + tv_mode = <0>;/*1:enabel ;0:disable*/ + }; + + meson-fb { + compatible = "amlogic, meson-g12a"; + /*memory-region = <&logo_reserved>;*/ + dev_name = "meson-fb"; + status = "okay"; + interrupts = <0 3 1 + 0 56 1 + 0 89 1>; + interrupt-names = "viu-vsync", "viu2-vsync", "rdma"; + mem_size = <0x00800000 0x1980000 0x100000 0x100000 0x800000>; + /* uboot logo,fb0/fb1 memory size,if afbcd fb0=0x01851000*/ + display_mode_default = "1080p60hz"; + scale_mode = <1>; + /** 0:VPU free scale 1:OSD free scale 2:OSD super scale */ + display_size_default = <1920 1080 1920 2160 32>; + /*1920*1080*4*3 = 0x17BB000*/ + pxp_mode = <0>; /** 0:normal mode 1:pxp mode */ + mem_alloc = <1>; + logo_addr = "0x3f800000"; + clocks = <&clkc CLKID_VPU_CLKC_MUX>; + clock-names = "vpu_clkc"; + }; + + /* Audio Related start */ + pdm_codec:dummy{ + #sound-dai-cells = <0>; + compatible = "amlogic, pdm_dummy_codec"; + status = "okay"; + }; + dummy_codec:dummy{ + #sound-dai-cells = <0>; + compatible = "amlogic, aml_dummy_codec"; + status = "okay"; + }; + amlogic_codec:t9015{ + #sound-dai-cells = <0>; + compatible = "amlogic, aml_codec_T9015"; + reg = <0xFF632000 0x2000>; + is_auge_used = <1>; /* meson or auge chipset used */ + tdmout_index = <1>; + status = "okay"; + }; + audio_effect:eqdrc{ + /*eq_enable = <1>;*/ + /*drc_enable = <1>;*/ + /* + * 0:tdmout_a + * 1:tdmout_b + * 2:tdmout_c + * 3:spdifout + * 4:spdifout_b + */ + eqdrc_module = <1>; + /* max 0xf, each bit for one lane, usually one lane */ + lane_mask = <0x1>; + /* max 0xff, each bit for one channel */ + channel_mask = <0x3>; + }; + auge_sound { + compatible = "amlogic, g12a-sound-card"; + aml-audio-card,name = "AML-AUGESOUND"; + + aml-audio-card,loopback = <&aml_loopback>; + aml-audio-card,aux-devs = <&amlogic_codec>; + /*avout mute gpio*/ + avout_mute-gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_HIGH>; + /*for audio effect ,eqdrc */ + aml-audio-card,effect = <&audio_effect>; + + aml-audio-card,dai-link@0 { + format = "dsp_a"; + mclk-fs = <512>; + //continuous-clock; + //bitclock-inversion; + //frame-inversion; + //bitclock-master = <&tdmacodec>; + //frame-master = <&tdmacodec>; + /* suffix-name, sync with android audio hal + * what's the dai link used for + */ + suffix-name = "alsaPORT-pcm"; + tdmacpu: cpu { + sound-dai = <&aml_tdma>; + dai-tdm-slot-tx-mask = + <1 1 1 1 1 1 1 1>; + dai-tdm-slot-rx-mask = + <1 1 1 1 1 1 1 1>; + dai-tdm-slot-num = <8>; + dai-tdm-slot-width = <32>; + system-clock-frequency = <24576000>; + }; + tdmacodec: codec { + sound-dai = <&dummy_codec &dummy_codec>; + }; + }; + + aml-audio-card,dai-link@1 { + format = "i2s";// "dsp_a"; + mclk-fs = <256>; + //continuous-clock; + //bitclock-inversion; + //frame-inversion; + bitclock-master = <&aml_tdmb>; + frame-master = <&aml_tdmb>; + //bitclock-master = <&tdmbcodec>; + //frame-master = <&tdmbcodec>; + /* suffix-name, sync with android audio hal + * what's the dai link used for + */ + suffix-name = "alsaPORT-i2s"; + cpu { + sound-dai = <&aml_tdmb>; + dai-tdm-slot-tx-mask = <1 1>; + dai-tdm-slot-rx-mask = <1 1>; + dai-tdm-slot-num = <2>; + /* + * dai-tdm-slot-tx-mask = + * <1 1 1 1 1 1 1 1>; + * dai-tdm-slot-rx-mask = + * <1 1 1 1 1 1 1 1>; + * dai-tdm-slot-num = <8>; + */ + dai-tdm-slot-width = <32>; + system-clock-frequency = <12288000>; + }; + tdmbcodec: codec { + sound-dai = <&dummy_codec &dummy_codec + &amlogic_codec>; + }; + }; + + aml-audio-card,dai-link@2 { + format = "i2s"; + mclk-fs = <256>; + //continuous-clock; + //bitclock-inversion; + //frame-inversion; + bitclock-master = <&aml_tdmc>; + frame-master = <&aml_tdmc>; + /* suffix-name, sync with android audio hal + * what's the dai link used for + */ + //suffix-name = "alsaPORT-tdm"; + cpu { + sound-dai = <&aml_tdmc>; + dai-tdm-slot-tx-mask = <1 1>; + dai-tdm-slot-rx-mask = <1 1>; + dai-tdm-slot-num = <2>; + dai-tdm-slot-width = <32>; + system-clock-frequency = <12288000>; + }; + codec { + sound-dai = <&dummy_codec &dummy_codec>; + }; + }; + + aml-audio-card,dai-link@3 { + mclk-fs = <64>; + /* suffix-name, sync with android audio hal + * what's the dai link used for + */ + suffix-name = "alsaPORT-pdm"; + cpu { + sound-dai = <&aml_pdm>; + }; + codec { + sound-dai = <&pdm_codec>; + }; + }; + + aml-audio-card,dai-link@4 { + mclk-fs = <128>; + /* suffix-name, sync with android audio hal + * what's the dai link used for + */ + suffix-name = "alsaPORT-spdif"; + cpu { + sound-dai = <&aml_spdif>; + system-clock-frequency = <6144000>; + }; + codec { + sound-dai = <&dummy_codec>; + }; + }; + /* spdif_b to hdmi, only playback */ + aml-audio-card,dai-link@5 { + mclk-fs = <128>; + continuous-clock; + /* suffix-name, sync with android audio hal + * what's the dai link used for + */ + suffix-name = "alsaPORT-spdifb2hdmi"; + cpu { + sound-dai = <&aml_spdif_b>; + system-clock-frequency = <6144000>; + }; + codec { + sound-dai = <&dummy_codec>; + }; + }; + }; + audiolocker: locker { + compatible = "amlogic, audiolocker"; + clocks = <&clkaudio CLKID_AUDIO_LOCKER_OUT + &clkaudio CLKID_AUDIO_LOCKER_IN + &clkaudio CLKID_AUDIO_MCLK_D + &clkaudio CLKID_AUDIO_MCLK_E + &clkc CLKID_MPLL1 + &clkc CLKID_MPLL2>; + clock-names = "lock_out", "lock_in", "out_src", + "in_src", "out_calc", "in_ref"; + interrupts = ; + interrupt-names = "irq"; + frequency = <49000000>; /* pll */ + dividor = <49>; /* locker's parent */ + status = "okay"; + }; + /* Audio Related end */ + + /*DCDC for SY8120B1ABC*/ + cpu_opp_table0: cpu_opp_table0 { + compatible = "operating-points-v2"; + opp-shared; + + opp00 { + opp-hz = /bits/ 64 <100000000>; + opp-microvolt = <731000>; + }; + opp01 { + opp-hz = /bits/ 64 <250000000>; + opp-microvolt = <731000>; + }; + opp02 { + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <731000>; + }; + opp03 { + opp-hz = /bits/ 64 <667000000>; + opp-microvolt = <731000>; + }; + opp04 { + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <731000>; + }; + opp05 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <731000>; + }; + opp06 { + opp-hz = /bits/ 64 <1398000000>; + opp-microvolt = <761000>; + }; + opp07 { + opp-hz = /bits/ 64 <1512000000>; + opp-microvolt = <791000>; + }; + opp08 { + opp-hz = /bits/ 64 <1608000000>; + opp-microvolt = <831000>; + }; + opp09 { + opp-hz = /bits/ 64 <1704000000>; + opp-microvolt = <861000>; + }; + opp10 { + opp-hz = /bits/ 64 <1800000000>; + opp-microvolt = <981000>; + }; + }; + + cpufreq-meson { + compatible = "amlogic, cpufreq-meson"; + pinctrl-names = "default"; + pinctrl-0 = <&pwm_ao_d_pins3>; + status = "okay"; + }; + +}; /* end of / */ + +&pwm_AO_cd { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + pinctrl-names="default"; + pinctrl-0=<&i2c0_master_pins2>; + clock-frequency = <400000>; + + gt9xx@5d { + compatible = "goodix,gt9xx"; + status = "disabled"; + reg = <0x5d>; + reset-gpio = <&gpio GPIOZ_9 0x00>; + irq-gpio = <&gpio GPIOZ_3 0x00>; + }; + + ftxx@38 { + compatible = "focaltech,fts"; + status = "disabled"; + reg = <0x38>; + reset-gpio = <&gpio GPIOZ_9 0x00>; + irq-gpio = <&gpio GPIOZ_3 0x00>; + x_max = <600>; + y_max = <1024>; + max-touch-number = <10>; + }; +}; + +&i2c3 { + status = "disabled"; + pinctrl-names="default"; + pinctrl-0=<&i2c3_master_pins2>; + clock-frequency = <100000>; /* default 100k */ + + /* for ref board */ + ad82584f_62: ad82584f_62@62 { + compatible = "ESMT, ad82584f"; + #sound-dai-cells = <0>; + reg = <0x31>; + status = "disabled"; + reset_pin = <&gpio GPIOA_5 0>; + }; + + tas5707_36: tas5707_36@36 { + compatible = "ti,tas5707"; + #sound-dai-cells = <0>; + reg = <0x1b>; + status = "disabled"; + reset_pin = <&gpio GPIOA_5 0>; + }; + + bl_extern_i2c { + compatible = "amlogic, bl_extern_i2c"; + status = "disabled"; + reg = <0x2c>; /*reg_address for lp8556*/ + dev_name = "lp8556"; + }; +}; + +&audiobus { + aml_tdma: tdma { + compatible = "amlogic, g12a-snd-tdma"; + #sound-dai-cells = <0>; + dai-tdm-lane-slot-mask-in = <0 1>; + dai-tdm-oe-lane-slot-mask-out = <1 0>; + dai-tdm-clk-sel = <0>; + clocks = <&clkaudio CLKID_AUDIO_MCLK_A + &clkc CLKID_MPLL0>; + clock-names = "mclk", "clk_srcpll"; + pinctrl-names = "tdm_pins"; + pinctrl-0 = <&tdmout_a &tdmin_a>; + }; + + aml_tdmb: tdmb { + compatible = "amlogic, g12a-snd-tdmb"; + #sound-dai-cells = <0>; + dai-tdm-lane-slot-mask-in = <0 1 0 0>; + dai-tdm-lane-slot-mask-out = <1 0 0 0>; + dai-tdm-clk-sel = <1>; + clocks = <&clkaudio CLKID_AUDIO_MCLK_B + &clkc CLKID_MPLL1 + &clkc CLKID_MPLL0>; + clock-names = "mclk", "clk_srcpll", "samesource_sysclk"; + pinctrl-names = "tdm_pins"; + pinctrl-0 = <&tdmb_mclk &tdmout_b &tdmin_b>; + /* + * 0: tdmout_a; + * 1: tdmout_b; + * 2: tdmout_c; + * 3: spdifout; + * 4: spdifout_b; + */ + samesource_sel = <3>; + }; + + aml_tdmc: tdmc { + compatible = "amlogic, g12a-snd-tdmc"; + #sound-dai-cells = <0>; + dai-tdm-lane-slot-mask-in = <0 1 0 0>; + #dai-tdm-lane-slot-mask-out = <1 0 1 1>; + #dai-tdm-lane-oe-slot-mask-in = <0 0 0 0>; + dai-tdm-lane-oe-slot-mask-out = <1 0 0 0>; + dai-tdm-clk-sel = <2>; + clocks = <&clkaudio CLKID_AUDIO_MCLK_C + &clkc CLKID_MPLL2>; + clock-names = "mclk", "clk_srcpll"; + pinctrl-names = "tdm_pins"; + pinctrl-0 = <&tdmc_mclk &tdmout_c &tdmin_c>; + }; + + + aml_spdif: spdif { + compatible = "amlogic, g12a-snd-spdif-a"; + #sound-dai-cells = <0>; + clocks = <&clkc CLKID_MPLL0 + &clkc CLKID_FCLK_DIV4 + &clkaudio CLKID_AUDIO_SPDIFIN + &clkaudio CLKID_AUDIO_SPDIFOUT + &clkaudio CLKID_AUDIO_SPDIFIN_CTRL + &clkaudio CLKID_AUDIO_SPDIFOUT_CTRL>; + clock-names = "sysclk", "fixed_clk", "gate_spdifin", + "gate_spdifout", "clk_spdifin", "clk_spdifout"; + interrupts = + ; + + interrupt-names = "irq_spdifin"; + pinctrl-names = "spdif_pins"; + pinctrl-0 = <&spdifout>; + status = "okay"; + }; + aml_spdif_b: spdif_b { + compatible = "amlogic, g12a-snd-spdif-b"; + #sound-dai-cells = <0>; + clocks = <&clkc CLKID_MPLL0 /*CLKID_HIFI_PLL*/ + &clkaudio CLKID_AUDIO_SPDIFOUTB + &clkaudio CLKID_AUDIO_SPDIFOUTB_CTRL>; + clock-names = "sysclk", + "gate_spdifout", "clk_spdifout"; + status = "okay"; + }; + aml_pdm: pdm { + compatible = "amlogic, g12a-snd-pdm"; + #sound-dai-cells = <0>; + clocks = <&clkaudio CLKID_AUDIO_PDM + &clkc CLKID_FCLK_DIV3 + &clkc CLKID_MPLL3 + &clkaudio CLKID_AUDIO_PDMIN0 + &clkaudio CLKID_AUDIO_PDMIN1>; + clock-names = "gate", + "sysclk_srcpll", + "dclk_srcpll", + "pdm_dclk", + "pdm_sysclk"; + pinctrl-names = "pdm_pins"; + pinctrl-0 = <&pdmin>; + filter_mode = <1>; /* mode 0~4, defalut:1 */ + status = "okay"; + }; + aml_loopback: loopback { + compatible = "amlogic, snd-loopback"; + /* + * 0: out rate = in data rate; + * 1: out rate = loopback data rate; + */ + lb_mode = <0>; + + /* datain src + * 0: tdmin_a; + * 1: tdmin_b; + * 2: tdmin_c; + * 3: spdifin; + * 4: pdmin; + */ + datain_src = <4>; + datain_chnum = <8>; + datain_chmask = <0x3f>; + + /* tdmin_lb src + * 0: tdmoutA + * 1: tdmoutB + * 2: tdmoutC + * 3: PAD_tdminA + * 4: PAD_tdminB + * 5: PAD_tdminC + */ + datalb_src = <2>; + datalb_chnum = <8>; + datalb_chmask = <0x3>; + + status = "okay"; + }; + + audioresample: resample { + compatible = "amlogic, g12a-resample"; + clocks = <&clkc CLKID_MPLL3 + &clkaudio CLKID_AUDIO_MCLK_F + &clkaudio CLKID_AUDIO_RESAMPLE_CTRL>; + clock-names = "resample_pll", "resample_src", "resample_clk"; + /*same with toddr_src + * TDMIN_A, 0 + * TDMIN_B, 1 + * TDMIN_C, 2 + * SPDIFIN, 3 + * PDMIN, 4 + * NONE, + * TDMIN_LB, 6 + * LOOPBACK, 7 + */ + resample_module = <4>; + status = "okay"; + }; + aml_pwrdet: pwrdet { + compatible = "amlogic, g12a-power-detect"; + + interrupts = ; + interrupt-names = "pwrdet_irq"; + + /* pwrdet source sel + * 7: loopback; + * 6: tdmin_lb; + * 5: reserved; + * 4: pdmin; + * 3: spdifin; + * 2: tdmin_c; + * 1: tdmin_b; + * 0: tdmin_a; + */ + pwrdet_src = <4>; + + hi_th = <0x70000>; + lo_th = <0x16000>; + + status = "okay"; + }; +}; /* end of audiobus */ + +&pinctrl_periphs { + tdmout_a: tdmout_a { + mux { /* GPIOX_11, GPIOX_10, GPIOX_9 */ + groups = "tdma_sclk", + "tdma_fs", + "tdma_dout0"; + function = "tdma_out"; + }; + }; + + tdmin_a: tdmin_a { + mux { /* GPIOX_8 */ + groups = "tdma_din1"; + function = "tdma_in"; + }; + }; + + tdmb_mclk: tdmb_mclk { + mux { + groups = "mclk0_a"; + function = "mclk0"; + drive-strength = <2>; + }; + }; + tdmout_b: tdmout_b { + mux { /* GPIOA_1, GPIOA_2, GPIOA_3 */ + groups = "tdmb_sclk", + "tdmb_fs", + "tdmb_dout0"; + function = "tdmb_out"; + drive-strength = <2>; + }; + }; + + tdmin_b:tdmin_b { + mux { /* GPIOA_4 */ + groups = "tdmb_din1" + /*,"tdmb_slv_sclk", "tdmb_slv_fs"*/; + function = "tdmb_in"; + drive-strength = <2>; + }; + }; + + tdmc_mclk: tdmc_mclk { + mux { /* GPIOA_11 */ + groups = "mclk1_a"; + function = "mclk1"; + }; + }; + + tdmout_c:tdmout_c { + mux { /* GPIOA_12, GPIOA_13, GPIOA_10, GPIOA_8, GPIOA_7*/ + groups = "tdmc_sclk_a", + "tdmc_fs_a", + "tdmc_dout0_a" + /*, "tdmc_dout2", + * "tdmc_dout3" + */; + function = "tdmc_out"; + }; + }; + + tdmin_c:tdmin_c { + mux { /* GPIOA_9 */ + groups = "tdmc_din1_a"; + function = "tdmc_in"; + }; + }; + + spdifin: spdifin { + mux {/* GPIOH_5 */ + groups = "spdif_in_h"; + function = "spdif_in"; + }; + }; + + /* GPIOH_4 */ + spdifout: spdifout { + mux { + groups = "spdif_out_h"; + function = "spdif_out"; + }; + }; + + pdmin: pdmin { + mux { /* gpioa_5, gpioa_6, gpioa_7, gpioa_8, gpioa_9*/ + groups = "pdm_din0_a", + /*"pdm_din1_a",*/ + "pdm_din2_a", + /*"pdm_din3_a",*/ + "pdm_dclk_a"; + function = "pdm"; + }; + }; + + +}; /* end of pinctrl_periphs */ +&pinctrl_aobus { + /*gpiao_10*/ + /*spdifout: spdifout { */ + /* mux { */ + /* groups = "spdif_out_ao"; */ + /* function = "spdif_out_ao";*/ + /* }; */ + /*}; */ +}; /* end of pinctrl_aobus */ + +&audio_data { + status = "okay"; +}; + +/* Audio Related End */ + +&pwm_ef { + status = "okay"; +}; + +&dwc3 { + status = "okay"; +}; + +&usb2_phy_v2 { + status = "okay"; + portnum = <2>; +}; + +&usb3_phy_v2 { + status = "okay"; + portnum = <1>; + otg = <0>; +}; + +&dwc2_a { + status = "okay"; + /** 0: normal, 1: otg+dwc3 host only, 2: otg+dwc3 device only*/ + controller-type = <1>; +}; +ðmac { + status = "okay"; + pinctrl-names = "internal_eth_pins"; + pinctrl-0 = <&internal_eth_pins>; + mc_val = <0x4be04>; + + internal_phy=<1>; +}; + +&uart_A { + status = "okay"; +}; + +/*if you want to use vdin just modify status to "ok"*/ +&vdin0 { + memory-region = <&vdin0_cma_reserved>; + status = "okay"; + /*vdin write mem color depth support: + *bit0:support 8bit + *bit1:support 9bit + *bit2:support 10bit + *bit3:support 12bit + *bit4:support yuv422 10bit full pack mode (from txl new add) + */ + tv_bit_mode = <0x15>; +}; +&vdin1 { + memory-region = <&vdin1_cma_reserved>; + status = "okay"; + /*vdin write mem color depth support: + *bit0:support 8bit + *bit1:support 9bit + *bit2:support 10bit + *bit3:support 12bit + */ + tv_bit_mode = <1>; +}; + + +&sd_emmc_c { + status = "okay"; + emmc { + caps = "MMC_CAP_8_BIT_DATA", + "MMC_CAP_MMC_HIGHSPEED", + "MMC_CAP_SD_HIGHSPEED", + "MMC_CAP_NONREMOVABLE", + /* "MMC_CAP_1_8V_DDR", */ + "MMC_CAP_HW_RESET", + "MMC_CAP_ERASE", + "MMC_CAP_CMD23"; + caps2 = "MMC_CAP2_HS200"; + /* "MMC_CAP2_HS400";*/ + f_min = <400000>; + f_max = <200000000>; + }; +}; + +&sd_emmc_b1 { + status = "disabled"; + sd { + caps = "MMC_CAP_4_BIT_DATA", + "MMC_CAP_MMC_HIGHSPEED", + "MMC_CAP_SD_HIGHSPEED"; + f_min = <400000>; + f_max = <50000000>; + }; +}; + +&sd_emmc_b2 { + status = "disabled"; + sd { + caps = "MMC_CAP_4_BIT_DATA", + "MMC_CAP_MMC_HIGHSPEED", + "MMC_CAP_SD_HIGHSPEED"; + f_min = <400000>; + f_max = <50000000>; + }; + + sdio { + caps = "MMC_CAP_4_BIT_DATA", + "MMC_CAP_MMC_HIGHSPEED", + "MMC_CAP_SD_HIGHSPEED", + "MMC_CAP_NONREMOVABLE", + "MMC_CAP_UHS_SDR12", + "MMC_CAP_UHS_SDR25", + "MMC_CAP_UHS_SDR50", + "MMC_CAP_UHS_SDR104", + "MMC_PM_KEEP_POWER", + "MMC_CAP_SDIO_IRQ"; + + f_min = <400000>; + f_max = <200000000>; + }; +}; + +&sd_emmc_a { + status = "disabled"; + sdio { + caps = "MMC_CAP_4_BIT_DATA", + "MMC_CAP_MMC_HIGHSPEED", + "MMC_CAP_SD_HIGHSPEED", + "MMC_CAP_NONREMOVABLE", + "MMC_CAP_UHS_SDR12", + "MMC_CAP_UHS_SDR25", + "MMC_CAP_UHS_SDR50", + "MMC_CAP_UHS_SDR104", + "MMC_PM_KEEP_POWER", + "MMC_CAP_SDIO_IRQ"; + f_min = <400000>; + f_max = <200000000>; + }; +}; + +&nand { + status = "disabled"; + plat-names = "bootloader","nandnormal"; + plat-num = <2>; + plat-part-0 = <&bootloader>; + plat-part-1 = <&nandnormal>; + bootloader: bootloader{ + enable_pad ="ce0"; + busy_pad = "rb0"; + timming_mode = "mode5"; + bch_mode = "bch8_1k"; + t_rea = <20>; + t_rhoh = <15>; + chip_num = <1>; + part_num = <0>; + rb_detect = <1>; + }; + nandnormal: nandnormal{ + enable_pad ="ce0"; + busy_pad = "rb0"; + timming_mode = "mode5"; + bch_mode = "bch8_1k"; + plane_mode = "twoplane"; + t_rea = <20>; + t_rhoh = <15>; + chip_num = <2>; + part_num = <3>; + partition = <&nand_partitions>; + rb_detect = <1>; + }; + nand_partitions:nand_partition{ + /* + * if bl_mode is 1, tpl size was generate by + * fip_copies * fip_size which + * will not skip bad when calculating + * the partition size; + * + * if bl_mode is 0, + * tpl partition must be comment out. + */ + tpl{ + offset=<0x0 0x0>; + size=<0x0 0x0>; + }; + logo{ + offset=<0x0 0x0>; + size=<0x0 0x200000>; + }; + recovery{ + offset=<0x0 0x0>; + size=<0x0 0x1000000>; + }; + boot{ + offset=<0x0 0x0>; + size=<0x0 0x1000000>; + }; + system{ + offset=<0x0 0x0>; + size=<0x0 0x4000000>; + }; + data{ + offset=<0xffffffff 0xffffffff>; + size=<0x0 0x0>; + }; + }; +}; + +&pcie_A { + reset-gpio = <&gpio GPIOX_7 GPIO_ACTIVE_HIGH>; + status = "disable"; +}; + +&meson_cooldev { + status = "okay"; +}; + +&defendkey { + status = "okay"; +}; + diff --git a/arch/arm/boot/dts/amlogic/g12a_s905y2_u220.dts b/arch/arm/boot/dts/amlogic/g12a_s905y2_u220.dts new file mode 100644 index 000000000000..0322b9c3fe69 --- /dev/null +++ b/arch/arm/boot/dts/amlogic/g12a_s905y2_u220.dts @@ -0,0 +1,1321 @@ +/* + * arch/arm/boot/dts/amlogic/g12a_s905y2_u220.dts + * + * Copyright (C) 2017 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +/dts-v1/; + +#include "mesong12a.dtsi" +#include "partition_mbox_normal.dtsi" + +/ { + model = "Amlogic"; + compatible = "amlogic, g12a"; + interrupt-parent = <&gic>; + #address-cells = <1>; + #size-cells = <1>; + + aliases { + serial0 = &uart_AO; + serial1 = &uart_A; + serial2 = &uart_B; + serial3 = &uart_C; + serial4 = &uart_AO_B; + tsensor0 = &p_tsensor; + tsensor1 = &d_tsensor; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c_AO; + }; + + memory@00000000 { + device_type = "memory"; + linux,usable-memory = <0x100000 0x7ff00000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + /* global autoconfigured region for contiguous allocations */ + ramoops@0x07400000 { + compatible = "ramoops"; + reg = <0x07400000 0x00100000>; + record-size = <0x8000>; + console-size = <0x8000>; + ftrace-size = <0x0>; + pmsg-size = <0x8000>; + }; + + secmon_reserved:linux,secmon { + compatible = "shared-dma-pool"; + reusable; + size = <0x400000>; + alignment = <0x400000>; + alloc-ranges = <0x05000000 0x400000>; + }; + secos_reserved:linux,secos { + status = "disable"; + compatible = "amlogic, aml_secos_memory"; + reg = <0x05300000 0x2000000>; + no-map; + }; + logo_reserved:linux,meson-fb { + compatible = "shared-dma-pool"; + reusable; + size = <0x800000>; + alignment = <0x400000>; + alloc-ranges = <0x7f800000 0x800000>; + }; + ion_cma_reserved:linux,ion-dev { + compatible = "shared-dma-pool"; + reusable; + size = <0x8000000>; + alignment = <0x400000>; + }; + //di_reserved:linux,di { + //compatible = "amlogic, di-mem"; + /* buffer_size = 3621952(yuv422 8bit) */ + /* 4179008(yuv422 10bit full pack mode) */ + /** 10x3621952=34.6M(0x23) support 8bit **/ + /** 10x4736064=45.2M(0x2e) support 12bit **/ + /** 10x4179008=40M(0x28) support 10bit **/ + //size = <0x2800000>; + //no-map; + //}; + /*di CMA pool */ + di_cma_reserved:linux,di_cma { + compatible = "shared-dma-pool"; + reusable; + /* buffer_size = 3621952(yuv422 8bit) + * | 4736064(yuv422 10bit) + * | 4074560(yuv422 10bit full pack mode) + * 10x3621952=34.6M(0x23) support 8bit + * 10x4736064=45.2M(0x2e) support 12bit + * 10x4074560=40M(0x28) support 10bit + */ + size = <0x02800000>; + alignment = <0x400000>; + }; + /* POST PROCESS MANAGER */ + ppmgr_reserved:linux,ppmgr { + compatible = "shared-dma-pool"; + size = <0x0>; + }; + + codec_mm_cma:linux,codec_mm_cma { + compatible = "shared-dma-pool"; + reusable; + /* ion_codec_mm max can alloc size 80M*/ + size = <0x13400000>; + alignment = <0x400000>; + linux,contiguous-region; + }; + /* codec shared reserved */ + codec_mm_reserved:linux,codec_mm_reserved { + compatible = "amlogic, codec-mm-reserved"; + size = <0x0>; + alignment = <0x100000>; + //no-map; + }; + /* vdin0 CMA pool */ + vdin0_cma_reserved:linux,vdin0_cma { + compatible = "shared-dma-pool"; + reusable; + /* 1920x1080x2x4 =16+4 M */ + size = <0x04000000>; + alignment = <0x400000>; + }; + /* vdin1 CMA pool */ + vdin1_cma_reserved:linux,vdin1_cma { + compatible = "shared-dma-pool"; + reusable; + /* 1920x1080x2x4 =16 M */ + size = <0x04000000>; + alignment = <0x400000>; + }; + }; + + cvbsout { + compatible = "amlogic, cvbsout-g12a"; + dev_name = "cvbsout"; + status = "okay"; + clocks = <&clkc CLKID_VCLK2_ENCI + &clkc CLKID_VCLK2_VENCI0 + &clkc CLKID_VCLK2_VENCI1 + &clkc CLKID_DAC_CLK>; + clock-names = "venci_top_gate", + "venci_0_gate", + "venci_1_gate", + "vdac_clk_gate"; + clk_path = <0>; + + /* performance: reg_address, reg_value */ + /* g12a */ + performance = <0x1bf0 0x9 + 0x1b56 0x333 + 0x1b12 0x8080 + 0x1b05 0xfd + 0x1c59 0xf850 + 0xffff 0x0>; /* ending flag */ + performance_sarft = <0x1bf0 0x9 + 0x1b56 0x333 + 0x1b12 0x0 + 0x1b05 0x9 + 0x1c59 0xfc48 + 0xffff 0x0>; /* ending flag */ + performance_revB_telecom = <0x1bf0 0x9 + 0x1b56 0x546 + 0x1b12 0x8080 + 0x1b05 0x9 + 0x1c59 0xf850 + 0xffff 0x0>; /* ending flag */ + }; + + bt-dev{ + compatible = "amlogic, bt-dev"; + dev_name = "bt-dev"; + status = "disable"; + gpio_reset = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>; + gpio_hostwake = <&gpio GPIOX_19 GPIO_ACTIVE_HIGH>; + }; + + wifi{ + compatible = "amlogic, aml_wifi"; + dev_name = "aml_wifi"; + status = "disable"; + interrupt_pin = <&gpio GPIOX_7 GPIO_ACTIVE_HIGH>; + irq_trigger_type = "GPIO_IRQ_LOW"; + power_on_pin = <&gpio GPIOX_6 GPIO_ACTIVE_HIGH>; + dhd_static_buf; //if use bcm wifi, config dhd_static_buf + pinctrl-names = "default"; + pinctrl-0 = <&pwm_e_pins>; + pwm_config = <&wifi_pwm_conf>; + }; + + wifi_pwm_conf:wifi_pwm_conf{ + pwm_channel1_conf { + pwms = <&pwm_ef MESON_PWM_0 30040 0>; + duty-cycle = <15020>; + times = <10>; + }; + pwm_channel2_conf { + pwms = <&pwm_ef MESON_PWM_2 30030 0>; + duty-cycle = <15015>; + times = <12>; + }; + }; + + codec_mm { + compatible = "amlogic, codec, mm"; + memory-region = <&codec_mm_cma &codec_mm_reserved>; + dev_name = "codec_mm"; + status = "okay"; + }; + + ppmgr { + compatible = "amlogic, ppmgr"; + memory-region = <&ppmgr_reserved>; + dev_name = "ppmgr"; + status = "okay"; + }; + + deinterlace { + compatible = "amlogic, deinterlace"; + status = "okay"; + /* 0:use reserved; 1:use cma; 2:use cma as reserved */ + flag_cma = <1>; + //memory-region = <&di_reserved>; + memory-region = <&di_cma_reserved>; + interrupts = <0 46 1 + 0 40 1>; + interrupt-names = "pre_irq", "post_irq"; + clocks = <&clkc CLKID_VPU_CLKB_TMP_COMP>, + <&clkc CLKID_VPU_CLKB_COMP>; + clock-names = "vpu_clkb_tmp_composite", + "vpu_clkb_composite"; + clock-range = <334 667>; + /* buffer-size = <3621952>;(yuv422 8bit) */ + buffer-size = <4074560>;/*yuv422 fullpack*/ + /* reserve-iomap = "true"; */ + /* if enable nr10bit, set nr10bit-support to 1 */ + post-wr-support = <1>; + nr10bit-support = <1>; + nrds-enable = <1>; + pps-enable = <1>; + }; + ionvideo { + compatible = "amlogic, ionvideo"; + dev_name = "ionvideo"; + status = "okay"; + }; + + gpio_keypad{ + compatible = "amlogic, gpio_keypad"; + status = "okay"; + scan_period = <20>; + key_num = <1>; + key_name = "power"; + key_code = <116>; + key-gpios = <&gpio_ao GPIOAO_3 GPIO_ACTIVE_HIGH>; + detect_mode = <0>;/*0:polling mode, 1:irq mode*/ + }; + + adc_keypad { + compatible = "amlogic, adc_keypad"; + status = "okay"; + key_name = "vol-", "vol+", "enter"; + key_num = <3>; + io-channels = <&saradc SARADC_CH2>; + io-channel-names = "key-chan-2"; + key_chan = ; + key_code = <114 115 28>; + key_val = <143 266 389>; //val=voltage/1800mV*1023 + key_tolerance = <40 40 40>; + }; + + unifykey{ + compatible = "amlogic, unifykey"; + status = "ok"; + unifykey-num = <15>; + unifykey-index-0 = <&keysn_0>; + unifykey-index-1 = <&keysn_1>; + unifykey-index-2 = <&keysn_2>; + unifykey-index-3 = <&keysn_3>; + unifykey-index-4 = <&keysn_4>; + unifykey-index-5 = <&keysn_5>; + unifykey-index-6 = <&keysn_6>; + unifykey-index-7 = <&keysn_7>; + unifykey-index-8 = <&keysn_8>; + unifykey-index-9 = <&keysn_9>; + unifykey-index-10= <&keysn_10>; + unifykey-index-11= <&keysn_11>; + unifykey-index-12= <&keysn_12>; + unifykey-index-13= <&keysn_13>; + unifykey-index-14= <&keysn_14>; + + keysn_0: key_0{ + key-name = "usid"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_1:key_1{ + key-name = "mac"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_2:key_2{ + key-name = "hdcp"; + key-device = "secure"; + key-type = "sha1"; + key-permit = "read","write","del"; + }; + keysn_3:key_3{ + key-name = "secure_boot_set"; + key-device = "efuse"; + key-permit = "write"; + }; + keysn_4:key_4{ + key-name = "mac_bt"; + key-device = "normal"; + key-permit = "read","write","del"; + key-type = "mac"; + }; + keysn_5:key_5{ + key-name = "mac_wifi"; + key-device = "normal"; + key-permit = "read","write","del"; + key-type = "mac"; + }; + keysn_6:key_6{ + key-name = "hdcp2_tx"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_7:key_7{ + key-name = "hdcp2_rx"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_8:key_8{ + key-name = "widevinekeybox"; + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_9:key_9{ + key-name = "deviceid"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_10:key_10{ + key-name = "hdcp22_fw_private"; + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_11:key_11{ + key-name = "PlayReadykeybox25"; + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_12:key_12{ + key-name = "prpubkeybox";// PlayReady + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_13:key_13{ + key-name = "prprivkeybox";// PlayReady + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_14:key_14{ + key-name = "attestationkeybox";// attestation key + key-device = "secure"; + key-permit = "read","write","del"; + }; + };//End unifykey + + efusekey:efusekey{ + keynum = <4>; + key0 = <&key_0>; + key1 = <&key_1>; + key2 = <&key_2>; + key3 = <&key_3>; + key_0:key_0{ + keyname = "mac"; + offset = <0>; + size = <6>; + }; + key_1:key_1{ + keyname = "mac_bt"; + offset = <6>; + size = <6>; + }; + key_2:key_2{ + keyname = "mac_wifi"; + offset = <12>; + size = <6>; + }; + key_3:key_3{ + keyname = "usid"; + offset = <18>; + size = <16>; + }; + };//End efusekey + + amlvecm { + compatible = "amlogic, vecm"; + dev_name = "aml_vecm"; + status = "okay"; + gamma_en = <0>;/*1:enabel ;0:disable*/ + wb_en = <0>;/*1:enabel ;0:disable*/ + cm_en = <0>;/*1:enabel ;0:disable*/ + /*0: 709/601 1: bt2020*/ + tx_op_color_primary = <0>; + }; + + amdolby_vision { + compatible = "amlogic, dolby_vision_g12a"; + dev_name = "aml_amdolby_vision_driver"; + status = "okay"; + tv_mode = <0>;/*1:enabel ;0:disable*/ + }; + + /* Audio Related start */ + pdm_codec:dummy{ + #sound-dai-cells = <0>; + compatible = "amlogic, pdm_dummy_codec"; + status = "okay"; + }; + dummy_codec:dummy{ + #sound-dai-cells = <0>; + compatible = "amlogic, aml_dummy_codec"; + status = "okay"; + }; + amlogic_codec:t9015{ + #sound-dai-cells = <0>; + compatible = "amlogic, aml_codec_T9015"; + reg = <0xFF632000 0x2000>; + is_auge_used = <1>; /* meson or auge chipset used */ + tdmout_index = <1>; + status = "okay"; + }; + audio_effect:eqdrc{ + /*eq_enable = <1>;*/ + /*drc_enable = <1>;*/ + /* + * 0:tdmout_a + * 1:tdmout_b + * 2:tdmout_c + * 3:spdifout + * 4:spdifout_b + */ + eqdrc_module = <1>; + /* max 0xf, each bit for one lane, usually one lane */ + lane_mask = <0x1>; + /* max 0xff, each bit for one channel */ + channel_mask = <0x3>; + }; + auge_sound { + compatible = "amlogic, g12a-sound-card"; + aml-audio-card,name = "AML-AUGESOUND"; + + aml-audio-card,loopback = <&aml_loopback>; + aml-audio-card,aux-devs = <&amlogic_codec>; + /*avout mute gpio*/ + avout_mute-gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_HIGH>; + /*for audio effect ,eqdrc */ + aml-audio-card,effect = <&audio_effect>; + + aml-audio-card,dai-link@0 { + format = "dsp_a"; + mclk-fs = <512>; + //continuous-clock; + //bitclock-inversion; + //frame-inversion; + //bitclock-master = <&tdmacodec>; + //frame-master = <&tdmacodec>; + /* suffix-name, sync with android audio hal + * what's the dai link used for + */ + suffix-name = "alsaPORT-pcm"; + tdmacpu: cpu { + sound-dai = <&aml_tdma>; + dai-tdm-slot-tx-mask = + <1 1 1 1 1 1 1 1>; + dai-tdm-slot-rx-mask = + <1 1 1 1 1 1 1 1>; + dai-tdm-slot-num = <8>; + dai-tdm-slot-width = <32>; + system-clock-frequency = <24576000>; + }; + tdmacodec: codec { + sound-dai = <&dummy_codec &dummy_codec>; + }; + }; + + aml-audio-card,dai-link@1 { + format = "i2s";// "dsp_a"; + mclk-fs = <256>; + //continuous-clock; + //bitclock-inversion; + //frame-inversion; + bitclock-master = <&aml_tdmb>; + frame-master = <&aml_tdmb>; + //bitclock-master = <&tdmbcodec>; + //frame-master = <&tdmbcodec>; + /* suffix-name, sync with android audio hal + * what's the dai link used for + */ + suffix-name = "alsaPORT-i2s"; + cpu { + sound-dai = <&aml_tdmb>; + dai-tdm-slot-tx-mask = <1 1>; + dai-tdm-slot-rx-mask = <1 1>; + dai-tdm-slot-num = <2>; + /* + * dai-tdm-slot-tx-mask = + * <1 1 1 1 1 1 1 1>; + * dai-tdm-slot-rx-mask = + * <1 1 1 1 1 1 1 1>; + * dai-tdm-slot-num = <8>; + */ + dai-tdm-slot-width = <32>; + system-clock-frequency = <12288000>; + }; + tdmbcodec: codec { + sound-dai = <&dummy_codec &dummy_codec + &amlogic_codec &ad82584f_62>; + }; + }; + + aml-audio-card,dai-link@2 { + format = "i2s"; + mclk-fs = <256>; + //continuous-clock; + //bitclock-inversion; + //frame-inversion; + bitclock-master = <&aml_tdmc>; + frame-master = <&aml_tdmc>; + /* suffix-name, sync with android audio hal + * what's the dai link used for + */ + //suffix-name = "alsaPORT-tdm"; + cpu { + sound-dai = <&aml_tdmc>; + dai-tdm-slot-tx-mask = <1 1>; + dai-tdm-slot-rx-mask = <1 1>; + dai-tdm-slot-num = <2>; + dai-tdm-slot-width = <32>; + system-clock-frequency = <12288000>; + }; + codec { + sound-dai = <&tlv320adc3101_32 &dummy_codec>; + }; + }; + + aml-audio-card,dai-link@3 { + mclk-fs = <64>; + /* suffix-name, sync with android audio hal + * what's the dai link used for + */ + suffix-name = "alsaPORT-pdm"; + cpu { + sound-dai = <&aml_pdm>; + }; + codec { + sound-dai = <&pdm_codec>; + }; + }; + + aml-audio-card,dai-link@4 { + mclk-fs = <128>; + continuous-clock; + /* suffix-name, sync with android audio hal + * what's the dai link used for + */ + suffix-name = "alsaPORT-spdifb2hdmi"; + cpu { + sound-dai = <&aml_spdif>; + system-clock-frequency = <6144000>; + }; + codec { + sound-dai = <&dummy_codec>; + }; + }; + /* spdif_b to hdmi, only playback */ + aml-audio-card,dai-link@5 { + mclk-fs = <128>; + continuous-clock; + /* suffix-name, sync with android audio hal + * what's the dai link used for + */ + suffix-name = "alsaPORT-spdif"; + cpu { + sound-dai = <&aml_spdif_b>; + system-clock-frequency = <6144000>; + }; + codec { + sound-dai = <&dummy_codec>; + }; + }; + /* + * dai link for i2s to hdmix, + * Notice to select a tdm lane not used by hw + */ + /* + * aml-audio-card,dai-link@6 { + * format = "i2s"; + * mclk-fs = <256>; + * //continuous-clock; + * //bitclock-inversion; + * //frame-inversion; + * bitclock-master = <&aml_i2s2hdmi>; + * frame-master = <&aml_i2s2hdmi>; + * suffix-name = "alsaPORT-i2s2hdmi"; + * cpu { + * sound-dai = <&aml_i2s2hdmi>; + * dai-tdm-slot-tx-mask = <1 1>; + * dai-tdm-slot-num = <2>; + * dai-tdm-slot-width = <32>; + * system-clock-frequency = <12288000>; + * }; + * codec { + * sound-dai = <&dummy_codec>; + * }; + * }; + */ + }; + audiolocker: locker { + compatible = "amlogic, audiolocker"; + clocks = <&clkaudio CLKID_AUDIO_LOCKER_OUT + &clkaudio CLKID_AUDIO_LOCKER_IN + &clkaudio CLKID_AUDIO_MCLK_D + &clkaudio CLKID_AUDIO_MCLK_E + &clkc CLKID_MPLL1 + &clkc CLKID_MPLL2>; + clock-names = "lock_out", "lock_in", "out_src", + "in_src", "out_calc", "in_ref"; + interrupts = ; + interrupt-names = "irq"; + frequency = <49000000>; /* pll */ + dividor = <49>; /* locker's parent */ + status = "okay"; + }; + /* Audio Related end */ + + /*DCDC for SY8120B1ABC*/ + cpu_opp_table0: cpu_opp_table0 { + compatible = "operating-points-v2"; + opp-shared; + + opp00 { + opp-hz = /bits/ 64 <100000000>; + opp-microvolt = <731000>; + }; + opp01 { + opp-hz = /bits/ 64 <250000000>; + opp-microvolt = <731000>; + }; + opp02 { + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <731000>; + }; + opp03 { + opp-hz = /bits/ 64 <667000000>; + opp-microvolt = <731000>; + }; + opp04 { + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <731000>; + }; + opp05 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <761000>; + }; + opp06 { + opp-hz = /bits/ 64 <1398000000>; + opp-microvolt = <791000>; + }; + opp07 { + opp-hz = /bits/ 64 <1512000000>; + opp-microvolt = <831000>; + }; + opp08 { + opp-hz = /bits/ 64 <1608000000>; + opp-microvolt = <871000>; + }; + opp09 { + opp-hz = /bits/ 64 <1704000000>; + opp-microvolt = <921000>; + }; + opp10 { + opp-hz = /bits/ 64 <1800000000>; + opp-microvolt = <981000>; + }; + }; + + cpufreq-meson { + compatible = "amlogic, cpufreq-meson"; + pinctrl-names = "default"; + pinctrl-0 = <&pwm_ao_d_pins3>; + status = "okay"; + }; + +}; /* end of / */ + +&meson_fb { + status = "okay"; + display_size_default = <1920 1080 1920 2160 32>; + mem_size = <0x00800000 0x1980000 0x100000 0x100000 0x800000>; + logo_addr = "0x7f800000"; + mem_alloc = <0>; + pxp_mode = <0>; /** 0:normal mode 1:pxp mode */ +}; + +&pwm_AO_cd { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + pinctrl-names="default"; + pinctrl-0=<&i2c0_master_pins2>; + clock-frequency = <400000>; + + gt9xx@5d { + compatible = "goodix,gt9xx"; + status = "disabled"; + reg = <0x5d>; + reset-gpio = <&gpio GPIOZ_9 0x00>; + irq-gpio = <&gpio GPIOZ_3 0x00>; + }; + + ftxx@38 { + compatible = "focaltech,fts"; + status = "disabled"; + reg = <0x38>; + reset-gpio = <&gpio GPIOZ_9 0x00>; + irq-gpio = <&gpio GPIOZ_3 0x00>; + x_max = <600>; + y_max = <1024>; + max-touch-number = <10>; + }; +}; + +&i2c3 { + status = "okay"; + pinctrl-names="default"; + pinctrl-0=<&i2c3_master_pins2>; + clock-frequency = <100000>; /* default 100k */ + + /* for ref board */ + ad82584f_62: ad82584f_62@62 { + compatible = "ESMT, ad82584f"; + #sound-dai-cells = <0>; + reg = <0x31>; + status = "okay"; + reset_pin = <&gpio GPIOA_5 0>; + }; + + tlv320adc3101_32: tlv320adc3101_32@32 { + compatible = "ti,tlv320adc3101"; + #sound-dai-cells = <0>; + reg = <0x19>; + differential_pair = <1>; + status = "okay"; + }; + + tas5707_36: tas5707_36@36 { + compatible = "ti,tas5707"; + #sound-dai-cells = <0>; + reg = <0x1b>; + status = "disabled"; + reset_pin = <&gpio GPIOA_5 0>; + }; + + bl_extern_i2c { + compatible = "amlogic, bl_extern_i2c"; + status = "disabled"; + reg = <0x2c>; /*reg_address for lp8556*/ + dev_name = "lp8556"; + }; +}; + +&audiobus { + aml_tdma: tdma { + compatible = "amlogic, g12a-snd-tdma"; + #sound-dai-cells = <0>; + dai-tdm-lane-slot-mask-in = <0 1>; + dai-tdm-oe-lane-slot-mask-out = <1 0>; + dai-tdm-clk-sel = <0>; + clocks = <&clkaudio CLKID_AUDIO_MCLK_A + &clkc CLKID_MPLL0>; + clock-names = "mclk", "clk_srcpll"; + pinctrl-names = "tdm_pins"; + pinctrl-0 = <&tdmout_a &tdmin_a>; + }; + + aml_tdmb: tdmb { + compatible = "amlogic, g12a-snd-tdmb"; + #sound-dai-cells = <0>; + dai-tdm-lane-slot-mask-in = <0 1 0 0>; + dai-tdm-lane-slot-mask-out = <1 0 0 0>; + dai-tdm-clk-sel = <1>; + clocks = <&clkaudio CLKID_AUDIO_MCLK_B + &clkc CLKID_MPLL1 + &clkc CLKID_MPLL0>; + clock-names = "mclk", "clk_srcpll", "samesource_sysclk"; + pinctrl-names = "tdm_pins"; + pinctrl-0 = <&tdmb_mclk &tdmout_b &tdmin_b>; + /* + * 0: tdmout_a; + * 1: tdmout_b; + * 2: tdmout_c; + * 3: spdifout; + * 4: spdifout_b; + */ + samesource_sel = <3>; + }; + + aml_tdmc: tdmc { + compatible = "amlogic, g12a-snd-tdmc"; + #sound-dai-cells = <0>; + dai-tdm-lane-slot-mask-in = <1 0 0 0>; + #dai-tdm-lane-slot-mask-out = <1 0 1 1>; + #dai-tdm-lane-oe-slot-mask-in = <0 0 0 0>; + #dai-tdm-lane-oe-slot-mask-out = <1 0 0 0>; + dai-tdm-clk-sel = <2>; + clocks = <&clkaudio CLKID_AUDIO_MCLK_C + &clkc CLKID_MPLL2>; + clock-names = "mclk", "clk_srcpll"; + pinctrl-names = "tdm_pins"; + pinctrl-0 = <&tdmc_mclk &tdmout_c &tdmin_c>; + }; + + /* copy a useless tdm to output for hdmi, no pinmux */ + aml_i2s2hdmi: i2s2hdmi { + compatible = "amlogic, g12a-snd-tdmc"; + #sound-dai-cells = <0>; + dai-tdm-lane-slot-mask-out = <1 1 1 1>; + dai-tdm-clk-sel = <2>; + clocks = <&clkaudio CLKID_AUDIO_MCLK_C + &clkc CLKID_MPLL2>; + clock-names = "mclk", "clk_srcpll"; + + i2s2hdmi = <1>; + + status = "disabled"; + }; + + aml_spdif: spdif { + compatible = "amlogic, g12a-snd-spdif-a"; + #sound-dai-cells = <0>; + clocks = <&clkc CLKID_MPLL0 + &clkc CLKID_FCLK_DIV4 + &clkaudio CLKID_AUDIO_SPDIFIN + &clkaudio CLKID_AUDIO_SPDIFOUT + &clkaudio CLKID_AUDIO_SPDIFIN_CTRL + &clkaudio CLKID_AUDIO_SPDIFOUT_CTRL>; + clock-names = "sysclk", "fixed_clk", "gate_spdifin", + "gate_spdifout", "clk_spdifin", "clk_spdifout"; + interrupts = + ; + + interrupt-names = "irq_spdifin"; + pinctrl-names = "spdif_pins"; + pinctrl-0 = <&spdifout &spdifin>; + status = "okay"; + }; + aml_spdif_b: spdif_b { + compatible = "amlogic, g12a-snd-spdif-b"; + #sound-dai-cells = <0>; + clocks = <&clkc CLKID_MPLL0 /*CLKID_HIFI_PLL*/ + &clkaudio CLKID_AUDIO_SPDIFOUTB + &clkaudio CLKID_AUDIO_SPDIFOUTB_CTRL>; + clock-names = "sysclk", + "gate_spdifout", "clk_spdifout"; + status = "okay"; + }; + aml_pdm: pdm { + compatible = "amlogic, g12a-snd-pdm"; + #sound-dai-cells = <0>; + clocks = <&clkaudio CLKID_AUDIO_PDM + &clkc CLKID_FCLK_DIV3 + &clkc CLKID_MPLL3 + &clkaudio CLKID_AUDIO_PDMIN0 + &clkaudio CLKID_AUDIO_PDMIN1>; + clock-names = "gate", + "sysclk_srcpll", + "dclk_srcpll", + "pdm_dclk", + "pdm_sysclk"; + pinctrl-names = "pdm_pins"; + pinctrl-0 = <&pdmin>; + filter_mode = <1>; /* mode 0~4, defalut:1 */ + status = "okay"; + }; + aml_loopback: loopback { + compatible = "amlogic, snd-loopback"; + /* + * 0: out rate = in data rate; + * 1: out rate = loopback data rate; + */ + lb_mode = <0>; + + /* datain src + * 0: tdmin_a; + * 1: tdmin_b; + * 2: tdmin_c; + * 3: spdifin; + * 4: pdmin; + */ + datain_src = <4>; + datain_chnum = <8>; + datain_chmask = <0x3f>; + + /* tdmin_lb src + * 0: tdmoutA + * 1: tdmoutB + * 2: tdmoutC + * 3: PAD_tdminA + * 4: PAD_tdminB + * 5: PAD_tdminC + */ + datalb_src = <2>; + datalb_chnum = <8>; + datalb_chmask = <0x3>; + + status = "okay"; + }; + + audioresample: resample { + compatible = "amlogic, g12a-resample"; + clocks = <&clkc CLKID_MPLL3 + &clkaudio CLKID_AUDIO_MCLK_F + &clkaudio CLKID_AUDIO_RESAMPLE_CTRL>; + clock-names = "resample_pll", "resample_src", "resample_clk"; + /*same with toddr_src + * TDMIN_A, 0 + * TDMIN_B, 1 + * TDMIN_C, 2 + * SPDIFIN, 3 + * PDMIN, 4 + * NONE, + * TDMIN_LB, 6 + * LOOPBACK, 7 + */ + resample_module = <4>; + status = "okay"; + }; + aml_pwrdet: pwrdet { + compatible = "amlogic, g12a-power-detect"; + + interrupts = ; + interrupt-names = "pwrdet_irq"; + + /* pwrdet source sel + * 7: loopback; + * 6: tdmin_lb; + * 5: reserved; + * 4: pdmin; + * 3: spdifin; + * 2: tdmin_c; + * 1: tdmin_b; + * 0: tdmin_a; + */ + pwrdet_src = <4>; + + hi_th = <0x70000>; + lo_th = <0x16000>; + + status = "disabled"; + }; +}; /* end of audiobus */ + +&pinctrl_periphs { + tdmout_a: tdmout_a { + mux { /* GPIOX_11, GPIOX_10, GPIOX_9 */ + groups = "tdma_sclk", + "tdma_fs", + "tdma_dout0"; + function = "tdma_out"; + }; + }; + + tdmin_a: tdmin_a { + mux { /* GPIOX_8 */ + groups = "tdma_din1"; + function = "tdma_in"; + }; + }; + + tdmb_mclk: tdmb_mclk { + mux { + groups = "mclk0_a"; + function = "mclk0"; + drive-strength = <2>; + }; + }; + tdmout_b: tdmout_b { + mux { /* GPIOA_1, GPIOA_2, GPIOA_3 */ + groups = "tdmb_sclk", + "tdmb_fs", + "tdmb_dout0"; + function = "tdmb_out"; + drive-strength = <2>; + }; + }; + + tdmin_b:tdmin_b { + mux { /* GPIOA_4 */ + groups = "tdmb_din1" + /*,"tdmb_slv_sclk", "tdmb_slv_fs"*/; + function = "tdmb_in"; + drive-strength = <2>; + }; + }; + + tdmc_mclk: tdmc_mclk { + mux { /* GPIOA_11 */ + groups = "mclk1_a"; + function = "mclk1"; + }; + }; + + tdmout_c:tdmout_c { + mux { /* GPIOA_12, GPIOA_13, GPIOA_8, GPIOA_7*/ + groups = "tdmc_sclk_a", + "tdmc_fs_a", + "tdmc_dout0_a" + /*, "tdmc_dout2", + * "tdmc_dout3" + */; + function = "tdmc_out"; + }; + }; + + tdmin_c:tdmin_c { + mux { /* GPIOA_10 */ + groups = "tdmc_din0_a"; + function = "tdmc_in"; + }; + }; + + spdifin: spdifin { + mux {/* GPIOH_5 */ + groups = "spdif_in_h"; + function = "spdif_in"; + }; + }; + + /* GPIOH_4 */ + /* + * spdifout: spdifout { + * mux { + * groups = "spdif_out_h"; + * function = "spdif_out"; + * }; + *}; + */ + + pdmin: pdmin { + mux { /* gpioa_5, gpioa_6, gpioa_7, gpioa_8, gpioa_9*/ + groups = "pdm_din0_a", + /*"pdm_din1_a",*/ + "pdm_din2_a", + /*"pdm_din3_a",*/ + "pdm_dclk_a"; + function = "pdm"; + }; + }; + + +}; /* end of pinctrl_periphs */ +&pinctrl_aobus { + spdifout: spdifout { + mux { /* gpiao_10 */ + groups = "spdif_out_ao"; + function = "spdif_out_ao"; + }; + }; +}; /* end of pinctrl_aobus */ + +&audio_data { + status = "okay"; +}; + +/* Audio Related End */ + +&pwm_ef { + status = "okay"; +}; + +&dwc3 { + status = "okay"; +}; + +&usb2_phy_v2 { + status = "okay"; + portnum = <2>; +}; + +&usb3_phy_v2 { + status = "okay"; + portnum = <1>; + otg = <1>; + gpio-vbus-power = "GPIOH_6"; + gpios = <&gpio GPIOH_6 GPIO_ACTIVE_HIGH>; +}; + +&dwc2_a { + status = "okay"; + /** 0: normal, 1: otg+dwc3 host only, 2: otg+dwc3 device only*/ + controller-type = <3>; +}; +ðmac { + status = "okay"; + pinctrl-names = "external_eth_pins"; + pinctrl-0 = <&external_eth_pins>; + mc_val = <0x1621>; + + internal_phy=<0>; +}; + +&uart_A { + status = "okay"; +}; + +/*if you want to use vdin just modify status to "ok"*/ +&vdin0 { + memory-region = <&vdin0_cma_reserved>; + status = "okay"; + /*vdin write mem color depth support: + *bit0:support 8bit + *bit1:support 9bit + *bit2:support 10bit + *bit3:support 12bit + *bit4:support yuv422 10bit full pack mode (from txl new add) + */ + tv_bit_mode = <0x15>; +}; +&vdin1 { + memory-region = <&vdin1_cma_reserved>; + status = "okay"; + /*vdin write mem color depth support: + *bit0:support 8bit + *bit1:support 9bit + *bit2:support 10bit + *bit3:support 12bit + */ + tv_bit_mode = <1>; +}; + + +&sd_emmc_c { + status = "okay"; + emmc { + caps = "MMC_CAP_8_BIT_DATA", + "MMC_CAP_MMC_HIGHSPEED", + "MMC_CAP_SD_HIGHSPEED", + "MMC_CAP_NONREMOVABLE", + /* "MMC_CAP_1_8V_DDR", */ + "MMC_CAP_HW_RESET", + "MMC_CAP_ERASE", + "MMC_CAP_CMD23"; + caps2 = "MMC_CAP2_HS200"; + /* "MMC_CAP2_HS400";*/ + f_min = <400000>; + f_max = <200000000>; + }; +}; + +&sd_emmc_b1 { + status = "disabled"; + sd { + caps = "MMC_CAP_4_BIT_DATA", + "MMC_CAP_MMC_HIGHSPEED", + "MMC_CAP_SD_HIGHSPEED"; + f_min = <400000>; + f_max = <50000000>; + }; +}; + +&sd_emmc_b2 { + status = "disabled"; + sd { + caps = "MMC_CAP_4_BIT_DATA", + "MMC_CAP_MMC_HIGHSPEED", + "MMC_CAP_SD_HIGHSPEED"; + f_min = <400000>; + f_max = <50000000>; + }; + + sdio { + caps = "MMC_CAP_4_BIT_DATA", + "MMC_CAP_MMC_HIGHSPEED", + "MMC_CAP_SD_HIGHSPEED", + "MMC_CAP_NONREMOVABLE", + "MMC_CAP_UHS_SDR12", + "MMC_CAP_UHS_SDR25", + "MMC_CAP_UHS_SDR50", + "MMC_CAP_UHS_SDR104", + "MMC_PM_KEEP_POWER", + "MMC_CAP_SDIO_IRQ"; + + f_min = <400000>; + f_max = <200000000>; + }; +}; + +&sd_emmc_a { + status = "disabled"; + sdio { + caps = "MMC_CAP_4_BIT_DATA", + "MMC_CAP_MMC_HIGHSPEED", + "MMC_CAP_SD_HIGHSPEED", + "MMC_CAP_NONREMOVABLE", + "MMC_CAP_UHS_SDR12", + "MMC_CAP_UHS_SDR25", + "MMC_CAP_UHS_SDR50", + "MMC_CAP_UHS_SDR104", + "MMC_PM_KEEP_POWER", + "MMC_CAP_SDIO_IRQ"; + f_min = <400000>; + f_max = <200000000>; + }; +}; + +&nand { + status = "disabled"; + plat-names = "bootloader","nandnormal"; + plat-num = <2>; + plat-part-0 = <&bootloader>; + plat-part-1 = <&nandnormal>; + bootloader: bootloader{ + enable_pad ="ce0"; + busy_pad = "rb0"; + timming_mode = "mode5"; + bch_mode = "bch8_1k"; + t_rea = <20>; + t_rhoh = <15>; + chip_num = <1>; + part_num = <0>; + rb_detect = <1>; + }; + nandnormal: nandnormal{ + enable_pad ="ce0"; + busy_pad = "rb0"; + timming_mode = "mode5"; + bch_mode = "bch8_1k"; + plane_mode = "twoplane"; + t_rea = <20>; + t_rhoh = <15>; + chip_num = <2>; + part_num = <3>; + partition = <&nand_partitions>; + rb_detect = <1>; + }; + nand_partitions:nand_partition{ + /* + * if bl_mode is 1, tpl size was generate by + * fip_copies * fip_size which + * will not skip bad when calculating + * the partition size; + * + * if bl_mode is 0, + * tpl partition must be comment out. + */ + tpl{ + offset=<0x0 0x0>; + size=<0x0 0x0>; + }; + logo{ + offset=<0x0 0x0>; + size=<0x0 0x200000>; + }; + recovery{ + offset=<0x0 0x0>; + size=<0x0 0x1000000>; + }; + boot{ + offset=<0x0 0x0>; + size=<0x0 0x1000000>; + }; + system{ + offset=<0x0 0x0>; + size=<0x0 0x4000000>; + }; + data{ + offset=<0xffffffff 0xffffffff>; + size=<0x0 0x0>; + }; + }; +}; + +&pcie_A { + reset-gpio = <&gpio GPIOX_7 GPIO_ACTIVE_HIGH>; + status = "disable"; +}; + +&meson_cooldev { + status = "okay"; +}; + +&defendkey { + status = "okay"; +}; + diff --git a/arch/arm/boot/dts/amlogic/g12a_s905y2_u221.dts b/arch/arm/boot/dts/amlogic/g12a_s905y2_u221.dts index 1755d33aa8f1..9317cf0a3b92 100644 --- a/arch/arm/boot/dts/amlogic/g12a_s905y2_u221.dts +++ b/arch/arm/boot/dts/amlogic/g12a_s905y2_u221.dts @@ -77,7 +77,7 @@ reusable; size = <0x8000000>; alignment = <0x400000>; - alloc-ranges = <0x0 0x30000000>; + alloc-ranges = <0x30000000 0x50000000>; }; //di_reserved:linux,di { //compatible = "amlogic, di-mem"; @@ -116,7 +116,7 @@ size = <0x13400000>; alignment = <0x400000>; linux,contiguous-region; - alloc-ranges = <0x0 0x30000000>; + alloc-ranges = <0x30000000 0x50000000>; }; /* codec shared reserved */ codec_mm_reserved:linux,codec_mm_reserved { @@ -653,23 +653,23 @@ }; opp05 { opp-hz = /bits/ 64 <1200000000>; - opp-microvolt = <731000>; + opp-microvolt = <761000>; }; opp06 { opp-hz = /bits/ 64 <1398000000>; - opp-microvolt = <761000>; + opp-microvolt = <791000>; }; opp07 { opp-hz = /bits/ 64 <1512000000>; - opp-microvolt = <791000>; + opp-microvolt = <831000>; }; opp08 { opp-hz = /bits/ 64 <1608000000>; - opp-microvolt = <831000>; + opp-microvolt = <871000>; }; opp09 { opp-hz = /bits/ 64 <1704000000>; - opp-microvolt = <861000>; + opp-microvolt = <921000>; }; opp10 { opp-hz = /bits/ 64 <1800000000>; diff --git a/arch/arm/boot/dts/amlogic/g12b-sched-energy.dtsi b/arch/arm/boot/dts/amlogic/g12b-sched-energy.dtsi new file mode 100644 index 000000000000..1c5fe160b001 --- /dev/null +++ b/arch/arm/boot/dts/amlogic/g12b-sched-energy.dtsi @@ -0,0 +1,85 @@ + +/ { + energy-costs { + CPU_COST_A73: core-cost0 { + busy-cost-data = < + 54 17 + 135 110 + 270 202 + 360 264 + 540 396 + 648 470 + 755 557 + 816 620 + 868 699 + 920 759 + /*1024 1024*/ + >; + idle-cost-data = < + 5 + 0 + 0 + >; + }; + CPU_COST_A53: core-cost1 { + busy-cost-data = < + 33 4 + 83 23 + 166 41 + 221 54 + 332 78 + 399 92 + 465 11 + 503 135 + 535 162 + 567 184 + 631 279 + >; + idle-cost-data = < + 3 + 0 + 0 + >; + }; + CLUSTER_COST_A73: cluster-cost0 { + busy-cost-data = < + 54 17 + 135 20 + 270 25 + 360 27 + 540 35 + 648 40 + 755 49 + 816 57 + 868 54 + 920 64 + /*1024 79*/ + >; + idle-cost-data = < + 10 + 10 + 0 + >; + }; + CLUSTER_COST_A53: cluster-cost1 { + busy-cost-data = < + 33 7 + 83 8 + 166 9 + 221 10 + 332 13 + 399 15 + 465 19 + 503 23 + 535 26 + 567 31 + 631 42 + >; + idle-cost-data = < + 6 + 6 + 0 + >; + }; + }; +}; diff --git a/arch/arm/boot/dts/amlogic/g12b_a311d_skt.dts b/arch/arm/boot/dts/amlogic/g12b_a311d_skt.dts new file mode 100644 index 000000000000..a448a5a6957b --- /dev/null +++ b/arch/arm/boot/dts/amlogic/g12b_a311d_skt.dts @@ -0,0 +1,1379 @@ +/* + * arch/arm/boot/dts/amlogic/g12b_a311d_skt.dts + * + * Copyright (C) 2017 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +/dts-v1/; + +#include "partition_mbox_normal.dtsi" +#include "mesong12b.dtsi" +#include "mesong12b_skt-panel.dtsi" + +/ { + model = "Amlogic"; + compatible = "amlogic, g12b"; + interrupt-parent = <&gic>; + #address-cells = <1>; + #size-cells = <1>; + + aliases { + serial0 = &uart_AO; + serial1 = &uart_A; + serial2 = &uart_B; + serial3 = &uart_C; + serial4 = &uart_AO_B; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c_AO; + tsensor0 = &p_tsensor; + tsensor1 = &d_tsensor; + }; + + memory@00000000 { + device_type = "memory"; + linux,usable-memory = <0x100000 0x7ff00000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + /* global autoconfigured region for contiguous allocations */ + ramoops@0x07400000 { + compatible = "ramoops"; + reg = <0x07400000 0x00100000>; + record-size = <0x8000>; + console-size = <0x8000>; + ftrace-size = <0x0>; + pmsg-size = <0x8000>; + }; + + secmon_reserved:linux,secmon { + compatible = "shared-dma-pool"; + reusable; + size = <0x400000>; + alignment = <0x400000>; + alloc-ranges = <0x05000000 0x400000>; + clear-map; + }; + + secos_reserved:linux,secos { + status = "disable"; + compatible = "amlogic, aml_secos_memory"; + reg = <0x05300000 0x2000000>; + no-map; + }; + logo_reserved:linux,meson-fb { + compatible = "shared-dma-pool"; + reusable; + size = <0x800000>; + alignment = <0x400000>; + alloc-ranges = <0x7f800000 0x800000>; + }; + ion_cma_reserved:linux,ion-dev { + compatible = "shared-dma-pool"; + reusable; + size = <0x8000000>; + alignment = <0x400000>; + }; + + //di_reserved:linux,di { + //compatible = "amlogic, di-mem"; + /* buffer_size = 3621952(yuv422 8bit) */ + /* 4179008(yuv422 10bit full pack mode) */ + /** 10x3621952=34.6M(0x23) support 8bit **/ + /** 10x4736064=45.2M(0x2e) support 12bit **/ + /** 10x4179008=40M(0x28) support 10bit **/ + //size = <0x2800000>; + //no-map; + //}; + /*di CMA pool */ + di_cma_reserved:linux,di_cma { + compatible = "shared-dma-pool"; + reusable; + /* buffer_size = 3621952(yuv422 8bit) + * | 4736064(yuv422 10bit) + * | 4074560(yuv422 10bit full pack mode) + * 10x3621952=34.6M(0x23) support 8bit + * 10x4736064=45.2M(0x2e) support 12bit + * 10x4074560=40M(0x28) support 10bit + */ + size = <0x02800000>; + alignment = <0x400000>; + }; + /* POST PROCESS MANAGER */ + ppmgr_reserved:linux,ppmgr { + compatible = "shared-dma-pool"; + size = <0x0>; + }; + codec_mm_cma:linux,codec_mm_cma { + compatible = "shared-dma-pool"; + reusable; + /* ion_codec_mm max can alloc size 80M*/ + size = <0x13400000>; + alignment = <0x400000>; + linux,contiguous-region; + }; + /* codec shared reserved */ + codec_mm_reserved:linux,codec_mm_reserved { + compatible = "amlogic, codec-mm-reserved"; + size = <0x0>; + alignment = <0x100000>; + //no-map; + }; + /* vdin0 CMA pool */ + vdin0_cma_reserved:linux,vdin0_cma { + compatible = "shared-dma-pool"; + reusable; + /* 1920x1080x2x4 =16+4 M */ + size = <0x04000000>; + alignment = <0x400000>; + }; + /* vdin1 CMA pool */ + vdin1_cma_reserved:linux,vdin1_cma { + compatible = "shared-dma-pool"; + reusable; + /* 1920x1080x2x4 =16 M */ + size = <0x04000000>; + alignment = <0x400000>; + }; + galcore_reserved:linux,galcore { + compatible = "shared-dma-pool"; + reusable; + size = <0x1000000>; + alignment = <0x400000>; + linux,contiguous-region; + }; + + isp_cma_reserved:linux,isp_cma { + compatible = "shared-dma-pool"; + reusable; + status = "okay"; + size = <0x1f000000>; + alignment = <0x400000>; + }; + + adapt_cma_reserved:linux,adapt_cma { + compatible = "shared-dma-pool"; + reusable; + status = "okay"; + size = <0x03000000>; + alignment = <0x400000>; + }; + gdc_cma_reserved:linux,gdc_cma { + compatible = "shared-dma-pool"; + reusable; + status = "okay"; + size = <0x04000000>; + alignment = <0x400000>; + }; + }; + galcore { + status = "okay"; + memory-region = <&galcore_reserved>; + }; + cvbsout { + compatible = "amlogic, cvbsout-g12b"; + dev_name = "cvbsout"; + status = "okay"; + clocks = <&clkc CLKID_VCLK2_ENCI + &clkc CLKID_VCLK2_VENCI0 + &clkc CLKID_VCLK2_VENCI1 + &clkc CLKID_DAC_CLK>; + clock-names = "venci_top_gate", + "venci_0_gate", + "venci_1_gate", + "vdac_clk_gate"; + clk_path = <0>; + + /* performance: reg_address, reg_value */ + /* g12b */ + performance = <0x1bf0 0x9 + 0x1b56 0x333 + 0x1b12 0x8080 + 0x1b05 0xfd + 0x1c59 0xf850 + 0xffff 0x0>; /* ending flag */ + performance_sarft = <0x1bf0 0x9 + 0x1b56 0x333 + 0x1b12 0x0 + 0x1b05 0x9 + 0x1c59 0xfc48 + 0xffff 0x0>; /* ending flag */ + }; + + bt-dev{ + compatible = "amlogic, bt-dev"; + dev_name = "bt-dev"; + status = "okay"; + gpio_reset = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>; + gpio_hostwake = <&gpio GPIOX_19 GPIO_ACTIVE_HIGH>; + }; + + wifi{ + compatible = "amlogic, aml_wifi"; + dev_name = "aml_wifi"; + status = "okay"; + interrupt_pin = <&gpio GPIOX_7 GPIO_ACTIVE_HIGH>; + irq_trigger_type = "GPIO_IRQ_LOW"; + power_on_pin = <&gpio GPIOX_6 GPIO_ACTIVE_HIGH>; + dhd_static_buf; //if use bcm wifi, config dhd_static_buf + pinctrl-names = "default"; + pinctrl-0 = <&pwm_e_pins>; + pwm_config = <&wifi_pwm_conf>; + }; + + wifi_pwm_conf:wifi_pwm_conf{ + pwm_channel1_conf { + pwms = <&pwm_ef MESON_PWM_0 30040 0>; + duty-cycle = <15020>; + times = <10>; + }; + pwm_channel2_conf { + pwms = <&pwm_ef MESON_PWM_2 30030 0>; + duty-cycle = <15015>; + times = <12>; + }; + }; + + codec_mm { + compatible = "amlogic, codec, mm"; + memory-region = <&codec_mm_cma &codec_mm_reserved>; + dev_name = "codec_mm"; + status = "okay"; + }; + + ppmgr { + compatible = "amlogic, ppmgr"; + memory-region = <&ppmgr_reserved>; + dev_name = "ppmgr"; + status = "okay"; + }; + + deinterlace { + compatible = "amlogic, deinterlace"; + status = "okay"; + /* 0:use reserved; 1:use cma; 2:use cma as reserved */ + flag_cma = <1>; + //memory-region = <&di_reserved>; + memory-region = <&di_cma_reserved>; + interrupts = <0 46 1 + 0 40 1>; + interrupt-names = "pre_irq", "post_irq"; + clocks = <&clkc CLKID_VPU_CLKB_TMP_COMP>, + <&clkc CLKID_VPU_CLKB_COMP>; + clock-names = "vpu_clkb_tmp_composite", + "vpu_clkb_composite"; + clock-range = <334 667>; + /* buffer-size = <3621952>;(yuv422 8bit) */ + buffer-size = <4074560>;/*yuv422 fullpack*/ + /* reserve-iomap = "true"; */ + /* if enable nr10bit, set nr10bit-support to 1 */ + post-wr-support = <1>; + nr10bit-support = <1>; + nrds-enable = <1>; + pps-enable = <1>; + }; + ionvideo { + compatible = "amlogic, ionvideo"; + dev_name = "ionvideo"; + status = "okay"; + }; + + gpio_keypad { + compatible = "amlogic, gpio_keypad"; + status = "okay"; + scan_period = <20>; + key_num = <1>; + key_name = "power"; + key_code = <116>; + key-gpios = <&gpio_ao GPIOAO_3 GPIO_ACTIVE_HIGH>; + detect_mode = <0>;/*0:polling mode, 1:irq mode*/ + }; + + adc_keypad { + compatible = "amlogic, adc_keypad"; + status = "okay"; + key_name = "menu", "vol-", "vol+", "esc", "home"; + key_num = <5>; + io-channels = <&saradc SARADC_CH2>; + io-channel-names = "key-chan-2"; + key_chan = ; + key_code = <139 114 115 1 102>; + key_val = <0 143 266 389 512>; //val=voltage/1800mV*1023 + key_tolerance = <40 40 40 40 40>; + }; + + unifykey{ + compatible = "amlogic, unifykey"; + status = "ok"; + unifykey-num = <15>; + unifykey-index-0 = <&keysn_0>; + unifykey-index-1 = <&keysn_1>; + unifykey-index-2 = <&keysn_2>; + unifykey-index-3 = <&keysn_3>; + unifykey-index-4 = <&keysn_4>; + unifykey-index-5 = <&keysn_5>; + unifykey-index-6 = <&keysn_6>; + unifykey-index-7 = <&keysn_7>; + unifykey-index-8 = <&keysn_8>; + unifykey-index-9 = <&keysn_9>; + unifykey-index-10= <&keysn_10>; + unifykey-index-11= <&keysn_11>; + unifykey-index-12= <&keysn_12>; + unifykey-index-13= <&keysn_13>; + unifykey-index-14= <&keysn_14>; + + keysn_0: key_0{ + key-name = "usid"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_1:key_1{ + key-name = "mac"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_2:key_2{ + key-name = "hdcp"; + key-device = "secure"; + key-type = "sha1"; + key-permit = "read","write","del"; + }; + keysn_3:key_3{ + key-name = "secure_boot_set"; + key-device = "efuse"; + key-permit = "write"; + }; + keysn_4:key_4{ + key-name = "mac_bt"; + key-device = "normal"; + key-permit = "read","write","del"; + key-type = "mac"; + }; + keysn_5:key_5{ + key-name = "mac_wifi"; + key-device = "normal"; + key-permit = "read","write","del"; + key-type = "mac"; + }; + keysn_6:key_6{ + key-name = "hdcp2_tx"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_7:key_7{ + key-name = "hdcp2_rx"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_8:key_8{ + key-name = "widevinekeybox"; + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_9:key_9{ + key-name = "deviceid"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_10:key_10{ + key-name = "hdcp22_fw_private"; + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_11:key_11{ + key-name = "PlayReadykeybox25"; + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_12:key_12{ + key-name = "prpubkeybox";// PlayReady + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_13:key_13{ + key-name = "prprivkeybox";// PlayReady + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_14:key_14{ + key-name = "attestationkeybox";// attestation key + key-device = "secure"; + key-permit = "read","write","del"; + }; + };//End unifykey + + efusekey:efusekey{ + keynum = <4>; + key0 = <&key_0>; + key1 = <&key_1>; + key2 = <&key_2>; + key3 = <&key_3>; + key_0:key_0{ + keyname = "mac"; + offset = <0>; + size = <6>; + }; + key_1:key_1{ + keyname = "mac_bt"; + offset = <6>; + size = <6>; + }; + key_2:key_2{ + keyname = "mac_wifi"; + offset = <12>; + size = <6>; + }; + key_3:key_3{ + keyname = "usid"; + offset = <18>; + size = <16>; + }; + };//End efusekey + + + amlvecm { + compatible = "amlogic, vecm"; + dev_name = "aml_vecm"; + status = "okay"; + gamma_en = <0>;/*1:enabel ;0:disable*/ + wb_en = <0>;/*1:enabel ;0:disable*/ + cm_en = <0>;/*1:enabel ;0:disable*/ + }; + amdolby_vision { + compatible = "amlogic, dolby_vision_g12a"; + dev_name = "aml_amdolby_vision_driver"; + status = "okay"; + tv_mode = <0>;/*1:enabel ;0:disable*/ + }; + + /* Audio Related start */ + pdm_codec:dummy{ + #sound-dai-cells = <0>; + compatible = "amlogic, pdm_dummy_codec"; + status = "okay"; + }; + dummy_codec:dummy{ + #sound-dai-cells = <0>; + compatible = "amlogic, aml_dummy_codec"; + status = "okay"; + }; + amlogic_codec:t9015{ + #sound-dai-cells = <0>; + /*compatible = "amlogic, aml_codec_T9015";*/ + reg = <0xFF632000 0x2000>; + is_auge_used = <1>; /* meson or auge chipset used */ + tdmout_index = <1>; + status = "disabled"; + }; + audio_effect:eqdrc{ + /*eq_enable = <1>;*/ + /*drc_enable = <1>;*/ + /* + * 0:tdmout_a + * 1:tdmout_b + * 2:tdmout_c + * 3:spdifout + * 4:spdifout_b + */ + eqdrc_module = <1>; + /* max 0xf, each bit for one lane, usually one lane */ + lane_mask = <0x1>; + /* max 0xff, each bit for one channel */ + channel_mask = <0x3>; + }; + auge_sound { + compatible = "amlogic, g12a-sound-card"; + aml-audio-card,name = "AML-AUGESOUND"; + + //aml-audio-card,loopback = <&aml_loopback>; + //aml-audio-card,aux-devs = <&amlogic_codec>; + /*avout mute gpio*/ + avout_mute-gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_HIGH>; + /*for audio effect ,eqdrc */ + aml-audio-card,effect = <&audio_effect>; + + aml-audio-card,dai-link@0 { + format = "dsp_a"; + mclk-fs = <512>; + //continuous-clock; + //bitclock-inversion; + //frame-inversion; + //bitclock-master = <&tdmacodec>; + //frame-master = <&tdmacodec>; + /* suffix-name, sync with android audio hal + * what's the dai link used for + */ + suffix-name = "alsaPORT-pcm"; + tdmacpu: cpu { + sound-dai = <&aml_tdma>; + dai-tdm-slot-tx-mask = + <1 1 1 1 1 1 1 1>; + dai-tdm-slot-rx-mask = + <1 1 1 1 1 1 1 1>; + dai-tdm-slot-num = <8>; + dai-tdm-slot-width = <32>; + system-clock-frequency = <24576000>; + }; + tdmacodec: codec { + sound-dai = <&dummy_codec &dummy_codec>; + }; + }; + + aml-audio-card,dai-link@1 { + format = "i2s"; + mclk-fs = <256>; + //continuous-clock; + //bitclock-inversion; + //frame-inversion; + bitclock-master = <&aml_tdmb>; + frame-master = <&aml_tdmb>; + //bitclock-master = <&tdmbcodec>; + //frame-master = <&tdmbcodec>; + /* suffix-name, sync with android audio hal + * what's the dai link used for + */ + suffix-name = "alsaPORT-i2s"; + cpu { + sound-dai = <&aml_tdmb>; + dai-tdm-slot-tx-mask = <1 1>; + dai-tdm-slot-rx-mask = <1 1>; + dai-tdm-slot-num = <2>; + dai-tdm-slot-width = <32>; + system-clock-frequency = <12288000>; + }; + tdmbcodec: codec { + sound-dai = <&dummy_codec &dummy_codec + &dummy_codec &ad82584f_62>; + }; + }; + + aml-audio-card,dai-link@2 { + format = "i2s"; + mclk-fs = <256>; + //continuous-clock; + //bitclock-inversion; + //frame-inversion; + bitclock-master = <&aml_tdmc>; + frame-master = <&aml_tdmc>; + /* suffix-name, sync with android audio hal + * what's the dai link used for + */ + //suffix-name = "alsaPORT-tdm"; + cpu { + sound-dai = <&aml_tdmc>; + dai-tdm-slot-tx-mask = <1 1>; + dai-tdm-slot-rx-mask = <1 1>; + dai-tdm-slot-num = <2>; + dai-tdm-slot-width = <32>; + system-clock-frequency = <12288000>; + }; + codec { + sound-dai = <&dummy_codec &dummy_codec>; + }; + }; + + aml-audio-card,dai-link@3 { + mclk-fs = <64>; + /* suffix-name, sync with android audio hal + * what's the dai link used for + */ + suffix-name = "alsaPORT-pdm"; + cpu { + sound-dai = <&aml_pdm>; + }; + codec { + sound-dai = <&pdm_codec>; + }; + }; + + aml-audio-card,dai-link@4 { + mclk-fs = <128>; + /* suffix-name, sync with android audio hal + * what's the dai link used for + */ + suffix-name = "alsaPORT-spdif"; + cpu { + sound-dai = <&aml_spdif>; + system-clock-frequency = <6144000>; + }; + codec { + sound-dai = <&dummy_codec>; + }; + }; + }; + audiolocker: locker { + compatible = "amlogic, audiolocker"; + clocks = <&clkaudio CLKID_AUDIO_LOCKER_OUT + &clkaudio CLKID_AUDIO_LOCKER_IN + &clkaudio CLKID_AUDIO_MCLK_D + &clkaudio CLKID_AUDIO_MCLK_E + &clkc CLKID_MPLL1 + &clkc CLKID_MPLL2>; + clock-names = "lock_out", "lock_in", "out_src", + "in_src", "out_calc", "in_ref"; + interrupts = ; + interrupt-names = "irq"; + frequency = <49000000>; /* pll */ + dividor = <49>; /* locker's parent */ + status = "okay"; + }; + /* Audio Related end */ + + cpu_opp_table0: cpu_opp_table0 { + compatible = "operating-points-v2"; + opp-shared; + + opp00 { + opp-hz = /bits/ 64 <100000000>; + opp-microvolt = <731000>; + }; + opp01 { + opp-hz = /bits/ 64 <250000000>; + opp-microvolt = <731000>; + }; + opp02 { + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <731000>; + }; + opp03 { + opp-hz = /bits/ 64 <667000000>; + opp-microvolt = <731000>; + }; + opp04 { + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <731000>; + }; + opp05 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <731000>; + }; + opp06 { + opp-hz = /bits/ 64 <1398000000>; + opp-microvolt = <761000>; + }; + opp07 { + opp-hz = /bits/ 64 <1512000000>; + opp-microvolt = <791000>; + }; + opp08 { + opp-hz = /bits/ 64 <1608000000>; + opp-microvolt = <831000>; + }; + opp09 { + opp-hz = /bits/ 64 <1704000000>; + opp-microvolt = <861000>; + }; + opp10 { + opp-hz = /bits/ 64 <1800000000>; + opp-microvolt = <981000>; + }; + }; + + cpu_opp_table1: cpu_opp_table1 { + compatible = "operating-points-v2"; + opp-shared; + + opp00 { + opp-hz = /bits/ 64 <100000000>; + opp-microvolt = <751000>; + }; + opp01 { + opp-hz = /bits/ 64 <250000000>; + opp-microvolt = <751000>; + }; + opp02 { + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <751000>; + }; + opp03 { + opp-hz = /bits/ 64 <667000000>; + opp-microvolt = <751000>; + }; + opp04 { + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <771000>; + }; + opp05 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <771000>; + }; + opp06 { + opp-hz = /bits/ 64 <1398000000>; + opp-microvolt = <791000>; + }; + opp07 { + opp-hz = /bits/ 64 <1512000000>; + opp-microvolt = <821000>; + }; + opp08 { + opp-hz = /bits/ 64 <1608000000>; + opp-microvolt = <861000>; + }; + opp09 { + opp-hz = /bits/ 64 <1704000000>; + opp-microvolt = <891000>; + }; + }; + + cpufreq-meson { + compatible = "amlogic, cpufreq-meson"; + status = "okay"; + }; + + sensor: sensor { + compatible = "soc, sensor"; + status = "okay"; + sensor-name = "imx290"; /*imx290;os08a10;imx227*/ + pinctrl-names="default"; + pinctrl-0=<&clk12_24_z_pins>; + clocks = <&clkc CLKID_24M>; + clock-names = "g12a_24m"; + reset = <&gpio GPIOZ_12 GPIO_ACTIVE_HIGH>; + ir_cut_gpio = <&gpio GPIOZ_11 GPIO_ACTIVE_HIGH + &gpio GPIOZ_7 GPIO_ACTIVE_HIGH>; + }; + + iq: iq { + compatible = "soc, iq"; + status = "okay"; + sensor-name = "imx290"; /*imx290;os08a10;imx227*/ + }; +}; /* end of / */ +&i2c2 { + status = "okay"; + pinctrl-names="default"; + pinctrl-0=<&i2c2_master_pins2>; + clock-frequency = <100000>; /* default 100k */ + sensor-i2c@6c { + compatible = "arm, i2c-sensor"; + reg = <0x6c>; + reg-names = "i2c-sensor"; + slave-addr = <0x6c>; + reg-type = <2>; + reg-data-type = <1>; + link-device = <&phycsi>; + }; + + lcd_extern_i2c0: lcd_extern_i2c@0 { + compatible = "lcd_ext, i2c"; + dev_name = "i2c_LT8912_0"; + reg = <0x48>; + status = "disabled"; + }; + + lcd_extern_i2c1: lcd_extern_i2c@1 { + compatible = "lcd_ext, i2c"; + dev_name = "i2c_LT8912_1"; + reg = <0x49>; + status = "disabled"; + }; +}; + +&isp { + status = "okay"; + memory-region = <&isp_cma_reserved>; +}; + +&adapter { + status = "okay"; + memory-region = <&adapt_cma_reserved>; +}; + +&gdc { + status = "okay"; + memory-region = <&gdc_cma_reserved>; +}; + +&meson_fb { + status = "okay"; + display_size_default = <1920 1080 1920 2160 32>; + mem_size = <0x00800000 0x1980000 0x100000 0x100000 0x800000>; + logo_addr = "0x7f800000"; + mem_alloc = <1>; + pxp_mode = <0>; /** 0:normal mode 1:pxp mode */ +}; + +&pwm_ab { + status = "okay"; + }; + +&pwm_ef { + status = "okay"; + }; + +&pwm_AO_cd { + status = "okay"; + }; + +&i2c0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_master_pins2>; + clock-frequency = <400000>; + + touchscreen@38 { + compatible = "focaltech,fts"; + status = "disabled"; + reg = <0x38>; + reset-gpio = <&gpio GPIOZ_9 GPIO_ACTIVE_HIGH>; + irq-gpio = <&gpio GPIOZ_3 GPIO_ACTIVE_HIGH>; + x_max = <720>; + y_max = <1280>; + max-touch-number = <10>; + }; +}; + +&i2c3 { + status = "okay"; + pinctrl-names="default"; + pinctrl-0=<&i2c3_master_pins2>; + clock-frequency = <100000>; /* default 100k */ + + /* for ref board */ + ad82584f_62: ad82584f_62@62 { + compatible = "ESMT, ad82584f"; + #sound-dai-cells = <0>; + reg = <0x31>; + status = "okay"; + reset_pin = <&gpio GPIOA_5 0>; + }; + + tlv320adc3101_32: tlv320adc3101_32@32 { + compatible = "ti,tlv320adc3101"; + #sound-dai-cells = <0>; + reg = <0x19>; + differential_pair = <1>; + status = "disabled"; + }; +}; + +&audiobus { + aml_tdma: tdma { + compatible = "amlogic, g12a-snd-tdma"; + #sound-dai-cells = <0>; + dai-tdm-lane-slot-mask-in = <0 1>; + dai-tdm-oe-lane-slot-mask-out = <1 0>; + dai-tdm-clk-sel = <0>; + clocks = <&clkaudio CLKID_AUDIO_MCLK_A + &clkc CLKID_MPLL0>; + clock-names = "mclk", "clk_srcpll"; + pinctrl-names = "tdm_pins"; + pinctrl-0 = <&tdmout_a &tdmin_a>; + }; + + aml_tdmb: tdmb { + compatible = "amlogic, g12a-snd-tdmb"; + #sound-dai-cells = <0>; + dai-tdm-lane-slot-mask-in = <0 1 0 0>; + dai-tdm-lane-slot-mask-out = <1 0 0 0>; + dai-tdm-clk-sel = <1>; + clocks = <&clkaudio CLKID_AUDIO_MCLK_B + &clkc CLKID_MPLL1 + &clkc CLKID_MPLL0>; + clock-names = "mclk", "clk_srcpll", "samesource_sysclk"; + pinctrl-names = "tdm_pins"; + pinctrl-0 = <&tdmb_mclk &tdmout_b &tdmin_b>; + /* + * 0: tdmout_a; + * 1: tdmout_b; + * 2: tdmout_c; + * 3: spdifout; + * 4: spdifout_b; + */ + samesource_sel = <4>; + }; + + aml_tdmc: tdmc { + compatible = "amlogic, g12a-snd-tdmc"; + #sound-dai-cells = <0>; + dai-tdm-lane-slot-mask-in = <1 0 0 0>; + #dai-tdm-lane-slot-mask-out = <1 0 1 1>; + #dai-tdm-lane-oe-slot-mask-in = <0 0 0 0>; + #dai-tdm-lane-oe-slot-mask-out = <1 0 0 0>; + dai-tdm-clk-sel = <2>; + clocks = <&clkaudio CLKID_AUDIO_MCLK_C + &clkc CLKID_MPLL2>; + clock-names = "mclk", "clk_srcpll"; + pinctrl-names = "tdm_pins"; + pinctrl-0 = <&tdmc_mclk &tdmout_c &tdmin_c>; + }; + + /* copy a useless tdm to output for hdmi, no pinmux */ + aml_i2s2hdmi: i2s2hdmi { + compatible = "amlogic, g12a-snd-tdmc"; + #sound-dai-cells = <0>; + dai-tdm-lane-slot-mask-out = <1 1 1 1>; + dai-tdm-clk-sel = <2>; + clocks = <&clkaudio CLKID_AUDIO_MCLK_C + &clkc CLKID_MPLL2>; + clock-names = "mclk", "clk_srcpll"; + + i2s2hdmi = <1>; + + status = "okay"; + }; + + aml_spdif: spdif { + compatible = "amlogic, g12a-snd-spdif-a"; + #sound-dai-cells = <0>; + clocks = <&clkc CLKID_MPLL0 + &clkc CLKID_FCLK_DIV4 + &clkaudio CLKID_AUDIO_SPDIFIN + &clkaudio CLKID_AUDIO_SPDIFOUT + &clkaudio CLKID_AUDIO_SPDIFIN_CTRL + &clkaudio CLKID_AUDIO_SPDIFOUT_CTRL>; + clock-names = "sysclk", "fixed_clk", "gate_spdifin", + "gate_spdifout", "clk_spdifin", "clk_spdifout"; + interrupts = + ; + + interrupt-names = "irq_spdifin"; + pinctrl-names = "spdif_pins"; + pinctrl-0 = <&spdifout &spdifin>; + status = "okay"; + }; + aml_spdif_b: spdif_b { + compatible = "amlogic, g12a-snd-spdif-b"; + #sound-dai-cells = <0>; + clocks = <&clkc CLKID_MPLL0 /*CLKID_HIFI_PLL*/ + &clkaudio CLKID_AUDIO_SPDIFOUTB + &clkaudio CLKID_AUDIO_SPDIFOUTB_CTRL>; + clock-names = "sysclk", + "gate_spdifout", "clk_spdifout"; + status = "disabled"; + }; + aml_pdm: pdm { + compatible = "amlogic, g12a-snd-pdm"; + #sound-dai-cells = <0>; + clocks = <&clkaudio CLKID_AUDIO_PDM + &clkc CLKID_FCLK_DIV3 + &clkc CLKID_MPLL3 + &clkaudio CLKID_AUDIO_PDMIN0 + &clkaudio CLKID_AUDIO_PDMIN1>; + clock-names = "gate", + "sysclk_srcpll", + "dclk_srcpll", + "pdm_dclk", + "pdm_sysclk"; + pinctrl-names = "pdm_pins"; + pinctrl-0 = <&pdmin>; + filter_mode = <1>; /* mode 0~4, defalut:1 */ + status = "okay"; + }; + aml_loopback: loopback { + compatible = "amlogic, snd-loopback"; + /* + * 0: out rate = in data rate; + * 1: out rate = loopback data rate; + */ + lb_mode = <0>; + + /* datain src + * 0: tdmin_a; + * 1: tdmin_b; + * 2: tdmin_c; + * 3: spdifin; + * 4: pdmin; + */ + datain_src = <4>; + datain_chnum = <8>; + datain_chmask = <0x3f>; + + /* tdmin_lb src + * 0: tdmoutA + * 1: tdmoutB + * 2: tdmoutC + * 3: PAD_tdminA + * 4: PAD_tdminB + * 5: PAD_tdminC + */ + datalb_src = <2>; + datalb_chnum = <8>; + datalb_chmask = <0x3>; + + status = "disabled"; + }; + + audioresample: resample { + compatible = "amlogic, g12a-resample"; + clocks = <&clkc CLKID_MPLL3 + &clkaudio CLKID_AUDIO_MCLK_F + &clkaudio CLKID_AUDIO_RESAMPLE_CTRL>; + clock-names = "resample_pll", "resample_src", "resample_clk"; + /*same with toddr_src + * TDMIN_A, 0 + * TDMIN_B, 1 + * TDMIN_C, 2 + * SPDIFIN, 3 + * PDMIN, 4 + * NONE, + * TDMIN_LB, 6 + * LOOPBACK, 7 + */ + resample_module = <4>; + status = "disabled"; + }; + aml_pwrdet: pwrdet { + compatible = "amlogic, g12a-power-detect"; + + interrupts = ; + interrupt-names = "pwrdet_irq"; + + /* pwrdet source sel + * 7: loopback; + * 6: tdmin_lb; + * 5: reserved; + * 4: pdmin; + * 3: spdifin; + * 2: tdmin_c; + * 1: tdmin_b; + * 0: tdmin_a; + */ + pwrdet_src = <4>; + + hi_th = <0x70000>; + lo_th = <0x16000>; + + status = "disabled"; + }; +}; /* end of audiobus */ + +&pinctrl_periphs { + tdmout_a: tdmout_a { + mux { /* GPIOX_11, GPIOX_10, GPIOX_9 */ + groups = "tdma_sclk", + "tdma_fs", + "tdma_dout0"; + function = "tdma_out"; + }; + }; + + tdmin_a: tdmin_a { + mux { /* GPIOX_8 */ + groups = "tdma_din1"; + function = "tdma_in"; + }; + }; + + tdmb_mclk: tdmb_mclk { + mux { + groups = "mclk0_a"; + function = "mclk0"; + drive-strength = <2>; + }; + }; + tdmout_b: tdmout_b { + mux { /* GPIOA_1, GPIOA_2, GPIOA_3 */ + groups = "tdmb_sclk", + "tdmb_fs", + "tdmb_dout0"; + function = "tdmb_out"; + drive-strength = <2>; + }; + }; + + tdmin_b:tdmin_b { + mux { /* GPIOA_4 */ + groups = "tdmb_din1" + /*,"tdmb_slv_sclk", "tdmb_slv_fs"*/; + function = "tdmb_in"; + drive-strength = <2>; + }; + }; + + tdmc_mclk: tdmc_mclk { + mux { /* GPIOA_11 */ + groups = "mclk1_a"; + function = "mclk1"; + }; + }; + + clk12_24_z_pins:clk12_24_z_pins { + mux { + groups = "clk12_24_z"; + function = "clk12_24_ee"; + drive-strength = <3>; + }; + }; + + tdmout_c:tdmout_c { + mux { /* GPIOA_12, GPIOA_13, GPIOA_8, GPIOA_7*/ + groups = "tdmc_sclk_a", + "tdmc_fs_a", + "tdmc_dout0_a" + /*, "tdmc_dout2", + * "tdmc_dout3" + */; + function = "tdmc_out"; + }; + }; + + tdmin_c:tdmin_c { + mux { /* GPIOA_10 */ + groups = "tdmc_din0_a"; + function = "tdmc_in"; + }; + }; + + spdifin: spdifin { + mux {/* GPIOH_5 */ + groups = "spdif_in_h"; + function = "spdif_in"; + }; + }; + + /* GPIOH_4 */ + /* + * spdifout: spdifout { + * mux { + * groups = "spdif_out_h"; + * function = "spdif_out"; + * }; + *}; + */ + + pdmin: pdmin { + mux { /* gpioa_5, gpioa_6, gpioa_7, gpioa_8, gpioa_9*/ + groups = "pdm_din0_a", + /*"pdm_din1_a",*/ + "pdm_din2_a", + /*"pdm_din3_a",*/ + "pdm_dclk_a"; + function = "pdm"; + }; + }; + + bl_pwm_off_pins:bl_pwm_off_pin { + mux { + pins = "GPIOH_5"; + function = "gpio_periphs"; + output-high; + }; + }; + +}; /* end of pinctrl_periphs */ + +&pinctrl_aobus { + spdifout: spdifout { + mux { /* gpiao_10 */ + groups = "spdif_out_ao"; + function = "spdif_out_ao"; + }; + }; +}; /* end of pinctrl_aobus */ + +&irblaster { + status = "disabled"; +}; + +&audio_data { + status = "okay"; +}; + +/*if you want to use vdin just modify status to "ok"*/ +&vdin0 { + memory-region = <&vdin0_cma_reserved>; + status = "okay"; + /*vdin write mem color depth support: + *bit0:support 8bit + *bit1:support 9bit + *bit2:support 10bit + *bit3:support 12bit + *bit4:support yuv422 10bit full pack mode (from txl new add) + */ + tv_bit_mode = <0x15>; +}; +&vdin1 { + memory-region = <&vdin1_cma_reserved>; + status = "okay"; + /*vdin write mem color depth support: + *bit0:support 8bit + *bit1:support 9bit + *bit2:support 10bit + *bit3:support 12bit + */ + tv_bit_mode = <1>; +}; + +&sd_emmc_c { + status = "okay"; + emmc { + caps = "MMC_CAP_8_BIT_DATA", + "MMC_CAP_MMC_HIGHSPEED", + "MMC_CAP_SD_HIGHSPEED", + "MMC_CAP_NONREMOVABLE", + /* "MMC_CAP_1_8V_DDR", */ + "MMC_CAP_HW_RESET", + "MMC_CAP_ERASE", + "MMC_CAP_CMD23"; + caps2 = "MMC_CAP2_HS200"; + /* "MMC_CAP2_HS400";*/ + f_min = <400000>; + f_max = <200000000>; + }; +}; + +&sd_emmc_b { + status = "okay"; + sd { + caps = "MMC_CAP_4_BIT_DATA", + "MMC_CAP_MMC_HIGHSPEED", + "MMC_CAP_SD_HIGHSPEED"; + f_min = <400000>; + f_max = <50000000>; + }; +}; + +&sd_emmc_a { + status = "okay"; + sdio { + caps = "MMC_CAP_4_BIT_DATA", + "MMC_CAP_MMC_HIGHSPEED", + "MMC_CAP_SD_HIGHSPEED", + "MMC_CAP_NONREMOVABLE", + "MMC_CAP_UHS_SDR12", + "MMC_CAP_UHS_SDR25", + "MMC_CAP_UHS_SDR50", + "MMC_CAP_UHS_SDR104", + "MMC_PM_KEEP_POWER", + "MMC_CAP_SDIO_IRQ"; + f_min = <400000>; + f_max = <200000000>; + }; +}; + +&nand { + status = "disabled"; + plat-names = "bootloader","nandnormal"; + plat-num = <2>; + plat-part-0 = <&bootloader>; + plat-part-1 = <&nandnormal>; + bootloader: bootloader{ + enable_pad ="ce0"; + busy_pad = "rb0"; + timming_mode = "mode5"; + bch_mode = "bch8_1k"; + t_rea = <20>; + t_rhoh = <15>; + chip_num = <1>; + part_num = <0>; + rb_detect = <1>; + }; + nandnormal: nandnormal{ + enable_pad ="ce0"; + busy_pad = "rb0"; + timming_mode = "mode5"; + bch_mode = "bch8_1k"; + plane_mode = "twoplane"; + t_rea = <20>; + t_rhoh = <15>; + chip_num = <2>; + part_num = <3>; + partition = <&nand_partitions>; + rb_detect = <1>; + }; + nand_partitions:nand_partition{ + /* + * if bl_mode is 1, tpl size was generate by + * fip_copies * fip_size which + * will not skip bad when calculating + * the partition size; + * + * if bl_mode is 0, + * tpl partition must be comment out. + */ + tpl{ + offset=<0x0 0x0>; + size=<0x0 0x0>; + }; + logo{ + offset=<0x0 0x0>; + size=<0x0 0x200000>; + }; + recovery{ + offset=<0x0 0x0>; + size=<0x0 0x1000000>; + }; + boot{ + offset=<0x0 0x0>; + size=<0x0 0x1000000>; + }; + system{ + offset=<0x0 0x0>; + size=<0x0 0x4000000>; + }; + data{ + offset=<0xffffffff 0xffffffff>; + size=<0x0 0x0>; + }; + }; +}; +&dwc3 { + status = "okay"; +}; + +&usb2_phy_v2 { + status = "okay"; + portnum = <2>; +}; + +&usb3_phy_v2 { + status = "okay"; + portnum = <0>; + otg = <1>; + gpio-vbus-power = "GPIOH_6"; + gpios = <&gpio GPIOH_6 GPIO_ACTIVE_HIGH>; +}; + +&dwc2_a { + status = "okay"; + /** 0: normal, 1: otg+dwc3 host only, 2: otg+dwc3 device only*/ + controller-type = <3>; +}; +ðmac { + status = "okay"; +/* //conflict with isp i2c + * pinctrl-names = "internal_eth_pins"; + * pinctrl-0 = <&internal_eth_pins>; + */ + mc_val = <0x4be04>; + + internal_phy=<1>; +}; + +&uart_A { + status = "okay"; +}; + +&pcie_A { + reset-gpio = <&gpio GPIOX_7 GPIO_ACTIVE_HIGH>; + status = "disabled"; +}; + +&saradc { + status = "okay"; +}; + +&spicc1 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&spicc1_pins>; + cs-gpios = <&gpio GPIOH_6 0>; +}; diff --git a/arch/arm/boot/dts/amlogic/g12b_a311d_w400.dts b/arch/arm/boot/dts/amlogic/g12b_a311d_w400.dts new file mode 100644 index 000000000000..b858e07da5dd --- /dev/null +++ b/arch/arm/boot/dts/amlogic/g12b_a311d_w400.dts @@ -0,0 +1,1293 @@ +/* + * arch/arm/boot/dts/amlogic/g12b_a311d_w400.dts + * + * Copyright (C) 2017 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +/dts-v1/; + +#include "partition_mbox_normal.dtsi" +#include "mesong12b.dtsi" +#include "mesong12b_skt-panel.dtsi" + +/ { + model = "Amlogic"; + compatible = "amlogic, g12b"; + interrupt-parent = <&gic>; + #address-cells = <1>; + #size-cells = <1>; + + aliases { + serial0 = &uart_AO; + serial1 = &uart_A; + serial2 = &uart_B; + serial3 = &uart_C; + serial4 = &uart_AO_B; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c_AO; + tsensor0 = &p_tsensor; + tsensor1 = &d_tsensor; + }; + + memory@00000000 { + device_type = "memory"; + linux,usable-memory = <0x100000 0x7ff00000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + /* global autoconfigured region for contiguous allocations */ + ramoops@0x07400000 { + compatible = "ramoops"; + reg = <0x07400000 0x00100000>; + record-size = <0x8000>; + console-size = <0x8000>; + ftrace-size = <0x0>; + pmsg-size = <0x8000>; + }; + + secmon_reserved:linux,secmon { + compatible = "shared-dma-pool"; + reusable; + size = <0x400000>; + alignment = <0x400000>; + alloc-ranges = <0x05000000 0x400000>; + clear-map; + }; + + secos_reserved:linux,secos { + status = "disable"; + compatible = "amlogic, aml_secos_memory"; + reg = <0x05300000 0x2000000>; + no-map; + }; + logo_reserved:linux,meson-fb { + compatible = "shared-dma-pool"; + reusable; + size = <0x800000>; + alignment = <0x400000>; + alloc-ranges = <0x7f800000 0x800000>; + }; + ion_cma_reserved:linux,ion-dev { + compatible = "shared-dma-pool"; + reusable; + size = <0x8000000>; + alignment = <0x400000>; + }; + + //di_reserved:linux,di { + //compatible = "amlogic, di-mem"; + /* buffer_size = 3621952(yuv422 8bit) */ + /* 4179008(yuv422 10bit full pack mode) */ + /** 10x3621952=34.6M(0x23) support 8bit **/ + /** 10x4736064=45.2M(0x2e) support 12bit **/ + /** 10x4179008=40M(0x28) support 10bit **/ + //size = <0x2800000>; + //no-map; + //}; + /*di CMA pool */ + di_cma_reserved:linux,di_cma { + compatible = "shared-dma-pool"; + reusable; + /* buffer_size = 3621952(yuv422 8bit) + * | 4736064(yuv422 10bit) + * | 4074560(yuv422 10bit full pack mode) + * 10x3621952=34.6M(0x23) support 8bit + * 10x4736064=45.2M(0x2e) support 12bit + * 10x4074560=40M(0x28) support 10bit + */ + size = <0x02800000>; + alignment = <0x400000>; + }; + codec_mm_cma:linux,codec_mm_cma { + compatible = "shared-dma-pool"; + reusable; + /* ion_codec_mm max can alloc size 80M*/ + size = <0x13400000>; + alignment = <0x400000>; + linux,contiguous-region; + }; + /* codec shared reserved */ + codec_mm_reserved:linux,codec_mm_reserved { + compatible = "amlogic, codec-mm-reserved"; + size = <0x0>; + alignment = <0x100000>; + //no-map; + }; + /* vdin0 CMA pool */ + vdin0_cma_reserved:linux,vdin0_cma { + compatible = "shared-dma-pool"; + reusable; + /* 1920x1080x2x4 =16+4 M */ + size = <0x04000000>; + alignment = <0x400000>; + }; + /* vdin1 CMA pool */ + vdin1_cma_reserved:linux,vdin1_cma { + compatible = "shared-dma-pool"; + reusable; + /* 1920x1080x2x4 =16 M */ + size = <0x04000000>; + alignment = <0x400000>; + }; + }; + + cvbsout { + compatible = "amlogic, cvbsout-g12b"; + dev_name = "cvbsout"; + status = "okay"; + clocks = <&clkc CLKID_VCLK2_ENCI + &clkc CLKID_VCLK2_VENCI0 + &clkc CLKID_VCLK2_VENCI1 + &clkc CLKID_DAC_CLK>; + clock-names = "venci_top_gate", + "venci_0_gate", + "venci_1_gate", + "vdac_clk_gate"; + /* clk path */ + /* 0:vid_pll vid2_clk */ + /* 1:gp0_pll vid2_clk */ + /* 2:vid_pll vid1_clk */ + /* 3:gp0_pll vid1_clk */ + clk_path = <0>; + + /* performance: reg_address, reg_value */ + /* g12b */ + performance = <0x1bf0 0x9 + 0x1b56 0x333 + 0x1b12 0x8080 + 0x1b05 0xfd + 0x1c59 0xf850 + 0xffff 0x0>; /* ending flag */ + performance_sarft = <0x1bf0 0x9 + 0x1b56 0x333 + 0x1b12 0x0 + 0x1b05 0x9 + 0x1c59 0xfc48 + 0xffff 0x0>; /* ending flag */ + }; + + bt-dev{ + compatible = "amlogic, bt-dev"; + dev_name = "bt-dev"; + status = "okay"; + gpio_reset = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>; + gpio_hostwake = <&gpio GPIOX_19 GPIO_ACTIVE_HIGH>; + }; + + wifi{ + compatible = "amlogic, aml_wifi"; + dev_name = "aml_wifi"; + status = "okay"; + interrupt_pin = <&gpio GPIOX_7 GPIO_ACTIVE_HIGH>; + irq_trigger_type = "GPIO_IRQ_LOW"; + power_on_pin = <&gpio GPIOX_6 GPIO_ACTIVE_HIGH>; + dhd_static_buf; //if use bcm wifi, config dhd_static_buf + pinctrl-names = "default"; + pinctrl-0 = <&pwm_e_pins>; + pwm_config = <&wifi_pwm_conf>; + }; + + wifi_pwm_conf:wifi_pwm_conf{ + pwm_channel1_conf { + pwms = <&pwm_ef MESON_PWM_0 30040 0>; + duty-cycle = <15020>; + times = <10>; + }; + pwm_channel2_conf { + pwms = <&pwm_ef MESON_PWM_2 30030 0>; + duty-cycle = <15015>; + times = <12>; + }; + }; + + codec_mm { + compatible = "amlogic, codec, mm"; + memory-region = <&codec_mm_cma &codec_mm_reserved>; + dev_name = "codec_mm"; + status = "okay"; + }; + + deinterlace { + compatible = "amlogic, deinterlace"; + status = "okay"; + /* 0:use reserved; 1:use cma; 2:use cma as reserved */ + flag_cma = <1>; + //memory-region = <&di_reserved>; + memory-region = <&di_cma_reserved>; + interrupts = <0 46 1 + 0 40 1>; + interrupt-names = "pre_irq", "post_irq"; + clocks = <&clkc CLKID_VPU_CLKB_TMP_COMP>, + <&clkc CLKID_VPU_CLKB_COMP>; + clock-names = "vpu_clkb_tmp_composite", + "vpu_clkb_composite"; + clock-range = <334 667>; + /* buffer-size = <3621952>;(yuv422 8bit) */ + buffer-size = <4074560>;/*yuv422 fullpack*/ + /* reserve-iomap = "true"; */ + /* if enable nr10bit, set nr10bit-support to 1 */ + post-wr-support = <1>; + nr10bit-support = <1>; + nrds-enable = <1>; + pps-enable = <1>; + }; + ionvideo { + compatible = "amlogic, ionvideo"; + dev_name = "ionvideo"; + status = "okay"; + }; + + gpio_keypad { + compatible = "amlogic, gpio_keypad"; + status = "okay"; + scan_period = <20>; + key_num = <1>; + key_name = "power"; + key_code = <116>; + key-gpios = <&gpio_ao GPIOAO_3 GPIO_ACTIVE_HIGH>; + detect_mode = <0>;/*0:polling mode, 1:irq mode*/ + }; + + adc_keypad { + compatible = "amlogic, adc_keypad"; + status = "okay"; + key_name = "vol-", "vol+", "enter"; + key_num = <3>; + io-channels = <&saradc SARADC_CH2>; + io-channel-names = "key-chan-2"; + key_chan = ; + key_code = <114 115 28>; + key_val = <143 266 389>; //val=voltage/1800mV*1023 + key_tolerance = <40 40 40>; + }; + + unifykey{ + compatible = "amlogic, unifykey"; + status = "ok"; + unifykey-num = <15>; + unifykey-index-0 = <&keysn_0>; + unifykey-index-1 = <&keysn_1>; + unifykey-index-2 = <&keysn_2>; + unifykey-index-3 = <&keysn_3>; + unifykey-index-4 = <&keysn_4>; + unifykey-index-5 = <&keysn_5>; + unifykey-index-6 = <&keysn_6>; + unifykey-index-7 = <&keysn_7>; + unifykey-index-8 = <&keysn_8>; + unifykey-index-9 = <&keysn_9>; + unifykey-index-10= <&keysn_10>; + unifykey-index-11= <&keysn_11>; + unifykey-index-12= <&keysn_12>; + unifykey-index-13= <&keysn_13>; + unifykey-index-14= <&keysn_14>; + + keysn_0: key_0{ + key-name = "usid"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_1:key_1{ + key-name = "mac"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_2:key_2{ + key-name = "hdcp"; + key-device = "secure"; + key-type = "sha1"; + key-permit = "read","write","del"; + }; + keysn_3:key_3{ + key-name = "secure_boot_set"; + key-device = "efuse"; + key-permit = "write"; + }; + keysn_4:key_4{ + key-name = "mac_bt"; + key-device = "normal"; + key-permit = "read","write","del"; + key-type = "mac"; + }; + keysn_5:key_5{ + key-name = "mac_wifi"; + key-device = "normal"; + key-permit = "read","write","del"; + key-type = "mac"; + }; + keysn_6:key_6{ + key-name = "hdcp2_tx"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_7:key_7{ + key-name = "hdcp2_rx"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_8:key_8{ + key-name = "widevinekeybox"; + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_9:key_9{ + key-name = "deviceid"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_10:key_10{ + key-name = "hdcp22_fw_private"; + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_11:key_11{ + key-name = "PlayReadykeybox25"; + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_12:key_12{ + key-name = "prpubkeybox";// PlayReady + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_13:key_13{ + key-name = "prprivkeybox";// PlayReady + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_14:key_14{ + key-name = "attestationkeybox";// attestation key + key-device = "secure"; + key-permit = "read","write","del"; + }; + };//End unifykey + + efusekey:efusekey{ + keynum = <4>; + key0 = <&key_0>; + key1 = <&key_1>; + key2 = <&key_2>; + key3 = <&key_3>; + key_0:key_0{ + keyname = "mac"; + offset = <0>; + size = <6>; + }; + key_1:key_1{ + keyname = "mac_bt"; + offset = <6>; + size = <6>; + }; + key_2:key_2{ + keyname = "mac_wifi"; + offset = <12>; + size = <6>; + }; + key_3:key_3{ + keyname = "usid"; + offset = <18>; + size = <16>; + }; + };//End efusekey + + amlvecm { + compatible = "amlogic, vecm"; + dev_name = "aml_vecm"; + status = "okay"; + gamma_en = <0>;/*1:enabel ;0:disable*/ + wb_en = <0>;/*1:enabel ;0:disable*/ + cm_en = <0>;/*1:enabel ;0:disable*/ + }; + amdolby_vision { + compatible = "amlogic, dolby_vision_g12a"; + dev_name = "aml_amdolby_vision_driver"; + status = "okay"; + tv_mode = <0>;/*1:enabel ;0:disable*/ + }; + + /* Audio Related start */ + pdm_codec:dummy{ + #sound-dai-cells = <0>; + compatible = "amlogic, pdm_dummy_codec"; + status = "okay"; + }; + dummy_codec:dummy{ + #sound-dai-cells = <0>; + compatible = "amlogic, aml_dummy_codec"; + status = "okay"; + }; + amlogic_codec:t9015{ + #sound-dai-cells = <0>; + compatible = "amlogic, aml_codec_T9015"; + reg = <0xFF632000 0x2000>; + is_auge_used = <1>; /* meson or auge chipset used */ + tdmout_index = <1>; + status = "okay"; + }; + audio_effect:eqdrc{ + /*eq_enable = <1>;*/ + /*drc_enable = <1>;*/ + /* + * 0:tdmout_a + * 1:tdmout_b + * 2:tdmout_c + * 3:spdifout + * 4:spdifout_b + */ + eqdrc_module = <1>; + /* max 0xf, each bit for one lane, usually one lane */ + lane_mask = <0x1>; + /* max 0xff, each bit for one channel */ + channel_mask = <0x3>; + }; + auge_sound { + compatible = "amlogic, g12a-sound-card"; + aml-audio-card,name = "AML-AUGESOUND"; + + //aml-audio-card,loopback = <&aml_loopback>; + //aml-audio-card,aux-devs = <&amlogic_codec>; + /*avout mute gpio*/ + avout_mute-gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_HIGH>; + /*for audio effect ,eqdrc */ + aml-audio-card,effect = <&audio_effect>; + + aml-audio-card,dai-link@0 { + format = "dsp_a"; + mclk-fs = <512>; + //continuous-clock; + //bitclock-inversion; + //frame-inversion; + //bitclock-master = <&tdmacodec>; + //frame-master = <&tdmacodec>; + /* suffix-name, sync with android audio hal + * what's the dai link used for + */ + suffix-name = "alsaPORT-pcm"; + tdmacpu: cpu { + sound-dai = <&aml_tdma>; + dai-tdm-slot-tx-mask = + <1 1 1 1 1 1 1 1>; + dai-tdm-slot-rx-mask = + <1 1 1 1 1 1 1 1>; + dai-tdm-slot-num = <8>; + dai-tdm-slot-width = <32>; + system-clock-frequency = <24576000>; + }; + tdmacodec: codec { + sound-dai = <&dummy_codec &dummy_codec>; + }; + }; + + aml-audio-card,dai-link@1 { + format = "i2s"; + mclk-fs = <256>; + //continuous-clock; + //bitclock-inversion; + //frame-inversion; + bitclock-master = <&aml_tdmb>; + frame-master = <&aml_tdmb>; + //bitclock-master = <&tdmbcodec>; + //frame-master = <&tdmbcodec>; + /* suffix-name, sync with android audio hal + * what's the dai link used for + */ + suffix-name = "alsaPORT-i2s"; + cpu { + sound-dai = <&aml_tdmb>; + dai-tdm-slot-tx-mask = <1 1>; + dai-tdm-slot-rx-mask = <1 1>; + dai-tdm-slot-num = <2>; + dai-tdm-slot-width = <32>; + system-clock-frequency = <12288000>; + }; + tdmbcodec: codec { + sound-dai = <&dummy_codec &dummy_codec + &amlogic_codec &ad82584f_62>; + }; + }; + + aml-audio-card,dai-link@2 { + format = "i2s"; + mclk-fs = <256>; + //continuous-clock; + //bitclock-inversion; + //frame-inversion; + bitclock-master = <&aml_tdmc>; + frame-master = <&aml_tdmc>; + /* suffix-name, sync with android audio hal + * what's the dai link used for + */ + //suffix-name = "alsaPORT-tdm"; + cpu { + sound-dai = <&aml_tdmc>; + dai-tdm-slot-tx-mask = <1 1>; + dai-tdm-slot-rx-mask = <1 1>; + dai-tdm-slot-num = <2>; + dai-tdm-slot-width = <32>; + system-clock-frequency = <12288000>; + }; + codec { + sound-dai = <&dummy_codec &dummy_codec>; + }; + }; + + aml-audio-card,dai-link@3 { + mclk-fs = <64>; + /* suffix-name, sync with android audio hal + * what's the dai link used for + */ + suffix-name = "alsaPORT-pdm"; + cpu { + sound-dai = <&aml_pdm>; + }; + codec { + sound-dai = <&pdm_codec>; + }; + }; + + aml-audio-card,dai-link@4 { + mclk-fs = <128>; + /* suffix-name, sync with android audio hal + * what's the dai link used for + */ + suffix-name = "alsaPORT-spdif"; + cpu { + sound-dai = <&aml_spdif>; + system-clock-frequency = <6144000>; + }; + codec { + sound-dai = <&dummy_codec>; + }; + }; + }; + audiolocker: locker { + compatible = "amlogic, audiolocker"; + clocks = <&clkaudio CLKID_AUDIO_LOCKER_OUT + &clkaudio CLKID_AUDIO_LOCKER_IN + &clkaudio CLKID_AUDIO_MCLK_D + &clkaudio CLKID_AUDIO_MCLK_E + &clkc CLKID_MPLL1 + &clkc CLKID_MPLL2>; + clock-names = "lock_out", "lock_in", "out_src", + "in_src", "out_calc", "in_ref"; + interrupts = ; + interrupt-names = "irq"; + frequency = <49000000>; /* pll */ + dividor = <49>; /* locker's parent */ + status = "okay"; + }; + /* Audio Related end */ + + cpu_opp_table0: cpu_opp_table0 { + compatible = "operating-points-v2"; + opp-shared; + + opp00 { + opp-hz = /bits/ 64 <100000000>; + opp-microvolt = <731000>; + }; + opp01 { + opp-hz = /bits/ 64 <250000000>; + opp-microvolt = <731000>; + }; + opp02 { + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <731000>; + }; + opp03 { + opp-hz = /bits/ 64 <667000000>; + opp-microvolt = <731000>; + }; + opp04 { + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <731000>; + }; + opp05 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <731000>; + }; + opp06 { + opp-hz = /bits/ 64 <1398000000>; + opp-microvolt = <761000>; + }; + opp07 { + opp-hz = /bits/ 64 <1512000000>; + opp-microvolt = <791000>; + }; + opp08 { + opp-hz = /bits/ 64 <1608000000>; + opp-microvolt = <831000>; + }; + opp09 { + opp-hz = /bits/ 64 <1704000000>; + opp-microvolt = <861000>; + }; + opp10 { + opp-hz = /bits/ 64 <1800000000>; + opp-microvolt = <981000>; + }; + }; + + cpu_opp_table1: cpu_opp_table1 { + compatible = "operating-points-v2"; + opp-shared; + + opp00 { + opp-hz = /bits/ 64 <100000000>; + opp-microvolt = <751000>; + }; + opp01 { + opp-hz = /bits/ 64 <250000000>; + opp-microvolt = <751000>; + }; + opp02 { + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <751000>; + }; + opp03 { + opp-hz = /bits/ 64 <667000000>; + opp-microvolt = <751000>; + }; + opp04 { + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <771000>; + }; + opp05 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <771000>; + }; + opp06 { + opp-hz = /bits/ 64 <1398000000>; + opp-microvolt = <791000>; + }; + opp07 { + opp-hz = /bits/ 64 <1512000000>; + opp-microvolt = <821000>; + }; + opp08 { + opp-hz = /bits/ 64 <1608000000>; + opp-microvolt = <861000>; + }; + opp09 { + opp-hz = /bits/ 64 <1704000000>; + opp-microvolt = <891000>; + }; + }; + + cpufreq-meson { + compatible = "amlogic, cpufreq-meson"; + status = "okay"; + }; + + +}; /* end of / */ + +&meson_fb { + status = "okay"; + display_size_default = <1920 1080 1920 2160 32>; + mem_size = <0x00800000 0x1980000 0x100000 0x100000 0x800000>; + logo_addr = "0x7f800000"; + mem_alloc = <0>; + pxp_mode = <0>; /** 0:normal mode 1:pxp mode */ +}; + +&pwm_ab { + status = "okay"; + }; + +&pwm_ef { + status = "okay"; + }; + +&pwm_AO_cd { + status = "okay"; + }; + +&i2c0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_master_pins2>; + clock-frequency = <400000>; + + touchscreen@5d { + compatible = "goodix,gt9xx"; + status = "disabled"; + reg = <0x5d>; + reset-gpio = <&gpio GPIOZ_9 GPIO_ACTIVE_HIGH>; + irq-gpio = <&gpio GPIOZ_3 GPIO_ACTIVE_HIGH>; + goodix,cfg-group0 = [ + 41 00 04 58 02 05 0C 00 02 54 07 + 0F 50 2D 03 05 00 00 00 00 40 00 + 04 20 10 F3 AA 07 28 0A 2C 2E 7C + 06 00 00 00 C9 03 24 00 01 00 00 + 00 00 FF 5D 66 98 32 28 64 94 C5 + 02 08 00 00 01 91 2C 00 8A 34 00 + 8A 3F 00 7E 4C 00 78 5B 00 78 00 + 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 + 00 00 02 04 06 08 0A 0C 0E 10 12 + 14 FF FF FF FF 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 + 02 04 06 08 0A 0C 1D 1E 1F 20 21 + 22 24 26 FF FF FF FF FF FF FF FF + FF FF FF 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 E3 01]; + }; + + touchscreen@38 { + compatible = "focaltech,fts"; + status = "disabled"; + reg = <0x38>; + reset-gpio = <&gpio GPIOZ_9 GPIO_ACTIVE_HIGH>; + irq-gpio = <&gpio GPIOZ_3 GPIO_ACTIVE_HIGH>; + x_max = <720>; + y_max = <1280>; + max-touch-number = <10>; + }; +}; + +&i2c3 { + status = "okay"; + pinctrl-names="default"; + pinctrl-0=<&i2c3_master_pins2>; + clock-frequency = <100000>; /* default 100k */ + + /* for ref board */ + ad82584f_62: ad82584f_62@62 { + compatible = "ESMT, ad82584f"; + #sound-dai-cells = <0>; + reg = <0x31>; + status = "okay"; + reset_pin = <&gpio GPIOA_5 0>; + }; + + tlv320adc3101_32: tlv320adc3101_32@32 { + compatible = "ti,tlv320adc3101"; + #sound-dai-cells = <0>; + reg = <0x19>; + differential_pair = <1>; + status = "disabled"; + }; + + bl_extern_i2c { + compatible = "bl_extern, i2c"; + dev_name = "lp8556"; + reg = <0x2c>; + status = "disabled"; + }; +}; + +&audiobus { + aml_tdma: tdma { + compatible = "amlogic, g12a-snd-tdma"; + #sound-dai-cells = <0>; + dai-tdm-lane-slot-mask-in = <0 1>; + dai-tdm-oe-lane-slot-mask-out = <1 0>; + dai-tdm-clk-sel = <0>; + clocks = <&clkaudio CLKID_AUDIO_MCLK_A + &clkc CLKID_MPLL0>; + clock-names = "mclk", "clk_srcpll"; + pinctrl-names = "tdm_pins"; + pinctrl-0 = <&tdmout_a &tdmin_a>; + }; + + aml_tdmb: tdmb { + compatible = "amlogic, g12a-snd-tdmb"; + #sound-dai-cells = <0>; + dai-tdm-lane-slot-mask-in = <0 1 0 0>; + dai-tdm-lane-slot-mask-out = <1 0 0 0>; + dai-tdm-clk-sel = <1>; + clocks = <&clkaudio CLKID_AUDIO_MCLK_B + &clkc CLKID_MPLL1 + &clkc CLKID_MPLL0>; + clock-names = "mclk", "clk_srcpll", "samesource_sysclk"; + pinctrl-names = "tdm_pins"; + pinctrl-0 = <&tdmb_mclk &tdmout_b &tdmin_b>; + /* + * 0: tdmout_a; + * 1: tdmout_b; + * 2: tdmout_c; + * 3: spdifout; + * 4: spdifout_b; + */ + samesource_sel = <3>; + }; + + aml_tdmc: tdmc { + compatible = "amlogic, g12a-snd-tdmc"; + #sound-dai-cells = <0>; + dai-tdm-lane-slot-mask-in = <1 0 0 0>; + #dai-tdm-lane-slot-mask-out = <1 0 1 1>; + #dai-tdm-lane-oe-slot-mask-in = <0 0 0 0>; + #dai-tdm-lane-oe-slot-mask-out = <1 0 0 0>; + dai-tdm-clk-sel = <2>; + clocks = <&clkaudio CLKID_AUDIO_MCLK_C + &clkc CLKID_MPLL2>; + clock-names = "mclk", "clk_srcpll"; + pinctrl-names = "tdm_pins"; + pinctrl-0 = <&tdmc_mclk &tdmout_c &tdmin_c>; + }; + + /* copy a useless tdm to output for hdmi, no pinmux */ + aml_i2s2hdmi: i2s2hdmi { + compatible = "amlogic, g12a-snd-tdmc"; + #sound-dai-cells = <0>; + dai-tdm-lane-slot-mask-out = <1 1 1 1>; + dai-tdm-clk-sel = <2>; + clocks = <&clkaudio CLKID_AUDIO_MCLK_C + &clkc CLKID_MPLL2>; + clock-names = "mclk", "clk_srcpll"; + + i2s2hdmi = <1>; + + status = "okay"; + }; + + aml_spdif: spdif { + compatible = "amlogic, g12a-snd-spdif-a"; + #sound-dai-cells = <0>; + clocks = <&clkc CLKID_MPLL0 + &clkc CLKID_FCLK_DIV4 + &clkaudio CLKID_AUDIO_SPDIFIN + &clkaudio CLKID_AUDIO_SPDIFOUT + &clkaudio CLKID_AUDIO_SPDIFIN_CTRL + &clkaudio CLKID_AUDIO_SPDIFOUT_CTRL>; + clock-names = "sysclk", "fixed_clk", "gate_spdifin", + "gate_spdifout", "clk_spdifin", "clk_spdifout"; + interrupts = + ; + + interrupt-names = "irq_spdifin"; + pinctrl-names = "spdif_pins"; + pinctrl-0 = <&spdifout &spdifin>; + status = "okay"; + }; + aml_spdif_b: spdif_b { + compatible = "amlogic, g12a-snd-spdif-b"; + #sound-dai-cells = <0>; + clocks = <&clkc CLKID_MPLL0 /*CLKID_HIFI_PLL*/ + &clkaudio CLKID_AUDIO_SPDIFOUTB + &clkaudio CLKID_AUDIO_SPDIFOUTB_CTRL>; + clock-names = "sysclk", + "gate_spdifout", "clk_spdifout"; + status = "disabled"; + }; + aml_pdm: pdm { + compatible = "amlogic, g12a-snd-pdm"; + #sound-dai-cells = <0>; + clocks = <&clkaudio CLKID_AUDIO_PDM + &clkc CLKID_FCLK_DIV3 + &clkc CLKID_MPLL3 + &clkaudio CLKID_AUDIO_PDMIN0 + &clkaudio CLKID_AUDIO_PDMIN1>; + clock-names = "gate", + "sysclk_srcpll", + "dclk_srcpll", + "pdm_dclk", + "pdm_sysclk"; + pinctrl-names = "pdm_pins"; + pinctrl-0 = <&pdmin>; + filter_mode = <1>; /* mode 0~4, defalut:1 */ + status = "okay"; + }; + aml_loopback: loopback { + compatible = "amlogic, snd-loopback"; + /* + * 0: out rate = in data rate; + * 1: out rate = loopback data rate; + */ + lb_mode = <0>; + + /* datain src + * 0: tdmin_a; + * 1: tdmin_b; + * 2: tdmin_c; + * 3: spdifin; + * 4: pdmin; + */ + datain_src = <4>; + datain_chnum = <8>; + datain_chmask = <0x3f>; + + /* tdmin_lb src + * 0: tdmoutA + * 1: tdmoutB + * 2: tdmoutC + * 3: PAD_tdminA + * 4: PAD_tdminB + * 5: PAD_tdminC + */ + datalb_src = <2>; + datalb_chnum = <8>; + datalb_chmask = <0x3>; + + status = "disabled"; + }; + + audioresample: resample { + compatible = "amlogic, g12a-resample"; + clocks = <&clkc CLKID_MPLL3 + &clkaudio CLKID_AUDIO_MCLK_F + &clkaudio CLKID_AUDIO_RESAMPLE_CTRL>; + clock-names = "resample_pll", "resample_src", "resample_clk"; + /*same with toddr_src + * TDMIN_A, 0 + * TDMIN_B, 1 + * TDMIN_C, 2 + * SPDIFIN, 3 + * PDMIN, 4 + * NONE, + * TDMIN_LB, 6 + * LOOPBACK, 7 + */ + resample_module = <4>; + status = "disabled"; + }; + aml_pwrdet: pwrdet { + compatible = "amlogic, g12a-power-detect"; + + interrupts = ; + interrupt-names = "pwrdet_irq"; + + /* pwrdet source sel + * 7: loopback; + * 6: tdmin_lb; + * 5: reserved; + * 4: pdmin; + * 3: spdifin; + * 2: tdmin_c; + * 1: tdmin_b; + * 0: tdmin_a; + */ + pwrdet_src = <4>; + + hi_th = <0x70000>; + lo_th = <0x16000>; + + status = "disabled"; + }; +}; /* end of audiobus */ + +&pinctrl_periphs { + tdmout_a: tdmout_a { + mux { /* GPIOX_11, GPIOX_10, GPIOX_9 */ + groups = "tdma_sclk", + "tdma_fs", + "tdma_dout0"; + function = "tdma_out"; + }; + }; + + tdmin_a: tdmin_a { + mux { /* GPIOX_8 */ + groups = "tdma_din1"; + function = "tdma_in"; + }; + }; + + tdmb_mclk: tdmb_mclk { + mux { + groups = "mclk0_a"; + function = "mclk0"; + drive-strength = <2>; + }; + }; + tdmout_b: tdmout_b { + mux { /* GPIOA_1, GPIOA_2, GPIOA_3 */ + groups = "tdmb_sclk", + "tdmb_fs", + "tdmb_dout0"; + function = "tdmb_out"; + drive-strength = <2>; + }; + }; + + tdmin_b:tdmin_b { + mux { /* GPIOA_4 */ + groups = "tdmb_din1" + /*,"tdmb_slv_sclk", "tdmb_slv_fs"*/; + function = "tdmb_in"; + drive-strength = <2>; + }; + }; + + tdmc_mclk: tdmc_mclk { + mux { /* GPIOA_11 */ + groups = "mclk1_a"; + function = "mclk1"; + }; + }; + + tdmout_c:tdmout_c { + mux { /* GPIOA_12, GPIOA_13, GPIOA_8, GPIOA_7*/ + groups = "tdmc_sclk_a", + "tdmc_fs_a", + "tdmc_dout0_a" + /*, "tdmc_dout2", + * "tdmc_dout3" + */; + function = "tdmc_out"; + }; + }; + + tdmin_c:tdmin_c { + mux { /* GPIOA_10 */ + groups = "tdmc_din0_a"; + function = "tdmc_in"; + }; + }; + + spdifin: spdifin { + mux {/* GPIOH_5 */ + groups = "spdif_in_h"; + function = "spdif_in"; + }; + }; + + /* GPIOH_4 */ + /* + * spdifout: spdifout { + * mux { + * groups = "spdif_out_h"; + * function = "spdif_out"; + * }; + *}; + */ + + pdmin: pdmin { + mux { /* gpioa_5, gpioa_6, gpioa_7, gpioa_8, gpioa_9*/ + groups = "pdm_din0_a", + /*"pdm_din1_a",*/ + "pdm_din2_a", + /*"pdm_din3_a",*/ + "pdm_dclk_a"; + function = "pdm"; + }; + }; + + bl_pwm_off_pins:bl_pwm_off_pin { + mux { + pins = "GPIOH_5"; + function = "gpio_periphs"; + output-high; + }; + }; + +}; /* end of pinctrl_periphs */ + +&pinctrl_aobus { + spdifout: spdifout { + mux { /* gpiao_10 */ + groups = "spdif_out_ao"; + function = "spdif_out_ao"; + }; + }; +}; /* end of pinctrl_aobus */ + +&irblaster { + status = "disabled"; +}; + +&audio_data { + status = "okay"; +}; + +/*if you want to use vdin just modify status to "ok"*/ +&vdin0 { + memory-region = <&vdin0_cma_reserved>; + status = "okay"; + /*vdin write mem color depth support: + *bit0:support 8bit + *bit1:support 9bit + *bit2:support 10bit + *bit3:support 12bit + *bit4:support yuv422 10bit full pack mode (from txl new add) + */ + tv_bit_mode = <0x15>; +}; +&vdin1 { + memory-region = <&vdin1_cma_reserved>; + status = "okay"; + /*vdin write mem color depth support: + *bit0:support 8bit + *bit1:support 9bit + *bit2:support 10bit + *bit3:support 12bit + */ + tv_bit_mode = <1>; +}; + +&sd_emmc_c { + status = "okay"; + emmc { + caps = "MMC_CAP_8_BIT_DATA", + "MMC_CAP_MMC_HIGHSPEED", + "MMC_CAP_SD_HIGHSPEED", + "MMC_CAP_NONREMOVABLE", + /* "MMC_CAP_1_8V_DDR", */ + "MMC_CAP_HW_RESET", + "MMC_CAP_ERASE", + "MMC_CAP_CMD23"; + caps2 = "MMC_CAP2_HS200"; + /* "MMC_CAP2_HS400";*/ + f_min = <400000>; + f_max = <200000000>; + }; +}; + +&sd_emmc_b { + status = "okay"; + sd { + caps = "MMC_CAP_4_BIT_DATA", + "MMC_CAP_MMC_HIGHSPEED", + "MMC_CAP_SD_HIGHSPEED"; + f_min = <400000>; + f_max = <50000000>; + }; +}; + +&sd_emmc_a { + status = "okay"; + sdio { + caps = "MMC_CAP_4_BIT_DATA", + "MMC_CAP_MMC_HIGHSPEED", + "MMC_CAP_SD_HIGHSPEED", + "MMC_CAP_NONREMOVABLE", + "MMC_CAP_UHS_SDR12", + "MMC_CAP_UHS_SDR25", + "MMC_CAP_UHS_SDR50", + "MMC_CAP_UHS_SDR104", + "MMC_PM_KEEP_POWER", + "MMC_CAP_SDIO_IRQ"; + f_min = <400000>; + f_max = <200000000>; + }; +}; + +&nand { + status = "disabled"; + plat-names = "bootloader","nandnormal"; + plat-num = <2>; + plat-part-0 = <&bootloader>; + plat-part-1 = <&nandnormal>; + bootloader: bootloader{ + enable_pad ="ce0"; + busy_pad = "rb0"; + timming_mode = "mode5"; + bch_mode = "bch8_1k"; + t_rea = <20>; + t_rhoh = <15>; + chip_num = <1>; + part_num = <0>; + rb_detect = <1>; + }; + nandnormal: nandnormal{ + enable_pad ="ce0"; + busy_pad = "rb0"; + timming_mode = "mode5"; + bch_mode = "bch8_1k"; + plane_mode = "twoplane"; + t_rea = <20>; + t_rhoh = <15>; + chip_num = <2>; + part_num = <3>; + partition = <&nand_partitions>; + rb_detect = <1>; + }; + nand_partitions:nand_partition{ + /* + * if bl_mode is 1, tpl size was generate by + * fip_copies * fip_size which + * will not skip bad when calculating + * the partition size; + * + * if bl_mode is 0, + * tpl partition must be comment out. + */ + tpl{ + offset=<0x0 0x0>; + size=<0x0 0x0>; + }; + logo{ + offset=<0x0 0x0>; + size=<0x0 0x200000>; + }; + recovery{ + offset=<0x0 0x0>; + size=<0x0 0x1000000>; + }; + boot{ + offset=<0x0 0x0>; + size=<0x0 0x1000000>; + }; + system{ + offset=<0x0 0x0>; + size=<0x0 0x4000000>; + }; + data{ + offset=<0xffffffff 0xffffffff>; + size=<0x0 0x0>; + }; + }; +}; +&dwc3 { + status = "okay"; +}; + +&usb2_phy_v2 { + status = "okay"; + portnum = <2>; +}; + +&usb3_phy_v2 { + status = "okay"; + portnum = <0>; + otg = <1>; + gpio-vbus-power = "GPIOH_6"; + gpios = <&gpio GPIOH_6 GPIO_ACTIVE_HIGH>; +}; + +&dwc2_a { + status = "okay"; + /** 0: normal, 1: otg+dwc3 host only, 2: otg+dwc3 device only*/ + controller-type = <3>; +}; +ðmac { + status = "okay"; + pinctrl-names = "internal_eth_pins"; + pinctrl-0 = <&internal_eth_pins>; + mc_val = <0x4be04>; + + internal_phy=<1>; +}; + +&uart_A { + status = "okay"; +}; + +&pcie_A { + reset-gpio = <&gpio GPIOX_7 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&saradc { + status = "okay"; +}; + diff --git a/arch/arm/boot/dts/amlogic/g12b_a311d_w400_buildroot.dts b/arch/arm/boot/dts/amlogic/g12b_a311d_w400_buildroot.dts new file mode 100644 index 000000000000..fe7d3a49a431 --- /dev/null +++ b/arch/arm/boot/dts/amlogic/g12b_a311d_w400_buildroot.dts @@ -0,0 +1,1436 @@ +/* + * arch/arm/boot/dts/amlogic/g12b_a311d_w400_buildroot.dts + * + * Copyright (C) 2017 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +/dts-v1/; + +#include "mesong12b.dtsi" +#include "mesong12b_skt-panel.dtsi" + +/ { + model = "Amlogic"; + compatible = "amlogic, g12b"; + interrupt-parent = <&gic>; + #address-cells = <1>; + #size-cells = <1>; + + aliases { + serial0 = &uart_AO; + serial1 = &uart_A; + serial2 = &uart_B; + serial3 = &uart_C; + serial4 = &uart_AO_B; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c_AO; + tsensor0 = &p_tsensor; + tsensor1 = &d_tsensor; + }; + + memory@00000000 { + device_type = "memory"; + linux,usable-memory = <0x100000 0x7ff00000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + /* global autoconfigured region for contiguous allocations */ + ramoops@0x07400000 { + compatible = "ramoops"; + reg = <0x07400000 0x00100000>; + record-size = <0x8000>; + console-size = <0x8000>; + ftrace-size = <0x0>; + pmsg-size = <0x8000>; + }; + + secmon_reserved:linux,secmon { + compatible = "shared-dma-pool"; + reusable; + size = <0x400000>; + alignment = <0x400000>; + alloc-ranges = <0x05000000 0x400000>; + clear-map; + }; + + secos_reserved:linux,secos { + status = "disable"; + compatible = "amlogic, aml_secos_memory"; + reg = <0x05300000 0x2000000>; + no-map; + }; + logo_reserved:linux,meson-fb { + compatible = "shared-dma-pool"; + reusable; + size = <0x800000>; + alignment = <0x400000>; + alloc-ranges = <0x7f800000 0x800000>; + }; + ion_cma_reserved:linux,ion-dev { + compatible = "shared-dma-pool"; + reusable; + size = <0x8000000>; + alignment = <0x400000>; + }; + + //di_reserved:linux,di { + //compatible = "amlogic, di-mem"; + /* buffer_size = 3621952(yuv422 8bit) */ + /* 4179008(yuv422 10bit full pack mode) */ + /** 10x3621952=34.6M(0x23) support 8bit **/ + /** 10x4736064=45.2M(0x2e) support 12bit **/ + /** 10x4179008=40M(0x28) support 10bit **/ + //size = <0x2800000>; + //no-map; + //}; + /*di CMA pool */ + di_cma_reserved:linux,di_cma { + compatible = "shared-dma-pool"; + reusable; + /* buffer_size = 3621952(yuv422 8bit) + * | 4736064(yuv422 10bit) + * | 4074560(yuv422 10bit full pack mode) + * 10x3621952=34.6M(0x23) support 8bit + * 10x4736064=45.2M(0x2e) support 12bit + * 10x4074560=40M(0x28) support 10bit + */ + size = <0x02800000>; + alignment = <0x400000>; + }; + /* POST PROCESS MANAGER */ + ppmgr_reserved:linux,ppmgr { + compatible = "shared-dma-pool"; + size = <0x0>; + }; + codec_mm_cma:linux,codec_mm_cma { + compatible = "shared-dma-pool"; + reusable; + /* ion_codec_mm max can alloc size 80M*/ + size = <0x13400000>; + alignment = <0x400000>; + linux,contiguous-region; + }; + /* codec shared reserved */ + codec_mm_reserved:linux,codec_mm_reserved { + compatible = "amlogic, codec-mm-reserved"; + size = <0x0>; + alignment = <0x100000>; + //no-map; + }; + /* vdin0 CMA pool */ + vdin0_cma_reserved:linux,vdin0_cma { + compatible = "shared-dma-pool"; + reusable; + /* 1920x1080x2x4 =16+4 M */ + size = <0x04000000>; + alignment = <0x400000>; + }; + /* vdin1 CMA pool */ + vdin1_cma_reserved:linux,vdin1_cma { + compatible = "shared-dma-pool"; + reusable; + /* 1920x1080x2x4 =16 M */ + size = <0x04000000>; + alignment = <0x400000>; + }; + galcore_reserved:linux,galcore { + compatible = "shared-dma-pool"; + reusable; + size = <0x1000000>; + alignment = <0x400000>; + linux,contiguous-region; + }; + + isp_cma_reserved:linux,isp_cma { + compatible = "shared-dma-pool"; + reusable; + status = "okay"; + size = <0x1f000000>; + alignment = <0x400000>; + }; + + adapt_cma_reserved:linux,adapt_cma { + compatible = "shared-dma-pool"; + reusable; + status = "okay"; + size = <0x03000000>; + alignment = <0x400000>; + }; + gdc_cma_reserved:linux,gdc_cma { + compatible = "shared-dma-pool"; + reusable; + status = "okay"; + size = <0x04000000>; + alignment = <0x400000>; + }; + }; + galcore { + status = "okay"; + memory-region = <&galcore_reserved>; + }; + gpioleds { + compatible = "gpio-leds"; + status = "okay"; + + sys_led { + label="sys_led"; + gpios=<&gpio_ao GPIOAO_11 GPIO_ACTIVE_HIGH>; + default-state ="on"; + retain-state-suspended; + linux,default-trigger="cpu0"; + }; + }; + + cvbsout { + compatible = "amlogic, cvbsout-g12b"; + dev_name = "cvbsout"; + status = "okay"; + clocks = <&clkc CLKID_VCLK2_ENCI + &clkc CLKID_VCLK2_VENCI0 + &clkc CLKID_VCLK2_VENCI1 + &clkc CLKID_DAC_CLK>; + clock-names = "venci_top_gate", + "venci_0_gate", + "venci_1_gate", + "vdac_clk_gate"; + + /* performance: reg_address, reg_value */ + /* g12b */ + performance = <0x1bf0 0x9 + 0x1b56 0x333 + 0x1b12 0x8080 + 0x1b05 0xfd + 0x1c59 0xf850 + 0xffff 0x0>; /* ending flag */ + performance_sarft = <0x1bf0 0x9 + 0x1b56 0x333 + 0x1b12 0x0 + 0x1b05 0x9 + 0x1c59 0xfc48 + 0xffff 0x0>; /* ending flag */ + }; + + bt-dev{ + compatible = "amlogic, bt-dev"; + dev_name = "bt-dev"; + status = "okay"; + gpio_reset = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>; + gpio_hostwake = <&gpio GPIOX_19 GPIO_ACTIVE_HIGH>; + }; + + wifi{ + compatible = "amlogic, aml_wifi"; + dev_name = "aml_wifi"; + status = "okay"; + interrupt_pin = <&gpio GPIOX_7 GPIO_ACTIVE_HIGH>; + irq_trigger_type = "GPIO_IRQ_LOW"; + power_on_pin = <&gpio GPIOX_6 GPIO_ACTIVE_HIGH>; + dhd_static_buf; //if use bcm wifi, config dhd_static_buf + pinctrl-names = "default"; + pinctrl-0 = <&pwm_e_pins>; + pwm_config = <&wifi_pwm_conf>; + }; + + wifi_pwm_conf:wifi_pwm_conf{ + pwm_channel1_conf { + pwms = <&pwm_ef MESON_PWM_0 30040 0>; + duty-cycle = <15020>; + times = <10>; + }; + pwm_channel2_conf { + pwms = <&pwm_ef MESON_PWM_2 30030 0>; + duty-cycle = <15015>; + times = <12>; + }; + }; + + codec_mm { + compatible = "amlogic, codec, mm"; + memory-region = <&codec_mm_cma &codec_mm_reserved>; + dev_name = "codec_mm"; + status = "okay"; + }; + + ppmgr { + compatible = "amlogic, ppmgr"; + memory-region = <&ppmgr_reserved>; + dev_name = "ppmgr"; + status = "okay"; + }; + + deinterlace { + compatible = "amlogic, deinterlace"; + status = "okay"; + /* 0:use reserved; 1:use cma; 2:use cma as reserved */ + flag_cma = <1>; + //memory-region = <&di_reserved>; + memory-region = <&di_cma_reserved>; + interrupts = <0 46 1 + 0 40 1>; + interrupt-names = "pre_irq", "post_irq"; + clocks = <&clkc CLKID_VPU_CLKB_TMP_COMP>, + <&clkc CLKID_VPU_CLKB_COMP>; + clock-names = "vpu_clkb_tmp_composite", + "vpu_clkb_composite"; + clock-range = <334 667>; + /* buffer-size = <3621952>;(yuv422 8bit) */ + buffer-size = <4074560>;/*yuv422 fullpack*/ + /* reserve-iomap = "true"; */ + /* if enable nr10bit, set nr10bit-support to 1 */ + post-wr-support = <1>; + nr10bit-support = <1>; + nrds-enable = <1>; + pps-enable = <1>; + }; + ionvideo { + compatible = "amlogic, ionvideo"; + dev_name = "ionvideo"; + status = "okay"; + }; + + + partitions: partitions{ + parts = <14>; + part-0 = <&logo>; + part-1 = <&recovery>; + part-2 = <&misc>; + part-3 = <&dto>; + part-4 = <&cri_data>; + part-5 = <¶m>; + part-6 = <&boot>; + part-7 = <&rsv>; + part-8 = <&tee>; + part-9 = <&vendor>; + part-10 = <&odm>; + part-11 = <&system>; + part-12 = <&cache>; + part-13 = <&data>; + + logo:logo{ + pname = "logo"; + size = <0x0 0x800000>; + mask = <1>; + }; + recovery:recovery{ + pname = "recovery"; + size = <0x0 0x1800000>; + mask = <1>; + }; + misc:misc{ + pname = "misc"; + size = <0x0 0x800000>; + mask = <1>; + }; + dto:dto{ + pname = "dto"; + size = <0x0 0x800000>; + mask = <1>; + }; + cri_data:cri_data{ + pname = "cri_data"; + size = <0x0 0x800000>; + mask = <2>; + }; + rsv:rsv{ + pname = "rsv"; + size = <0x0 0x1000000>; + mask = <1>; + }; + param:param{ + pname = "param"; + size = <0x0 0x1000000>; + mask = <2>; + }; + boot:boot{ + pname = "boot"; + size = <0x0 0x1000000>; + mask = <1>; + }; + tee:tee{ + pname = "tee"; + size = <0x0 0x2000000>; + mask = <1>; + }; + vendor:vendor{ + pname = "vendor"; + size = <0x0 0x10000000>; + mask = <1>; + }; + odm:odm{ + pname = "odm"; + size = <0x0 0x10000000>; + mask = <1>; + }; + system:system{ + pname = "system"; + size = <0x0 0x80000000>; + mask = <1>; + }; + cache:cache{ + pname = "cache"; + size = <0x0 0x46000000>; + mask = <2>; + }; + data:data{ + pname = "data"; + size = <0xffffffff 0xffffffff>; + mask = <4>; + }; + }; + + gpio_keypad { + compatible = "amlogic, gpio_keypad"; + status = "okay"; + scan_period = <20>; + key_num = <1>; + key_name = "power"; + key_code = <116>; + key-gpios = <&gpio_ao GPIOAO_3 GPIO_ACTIVE_HIGH>; + detect_mode = <0>;/*0:polling mode, 1:irq mode*/ + }; + + adc_keypad { + compatible = "amlogic, adc_keypad"; + status = "okay"; + key_name = "vol-", "vol+", "enter"; + key_num = <3>; + io-channels = <&saradc SARADC_CH2>; + io-channel-names = "key-chan-2"; + key_chan = ; + key_code = <114 115 28>; + key_val = <143 266 389>; //val=voltage/1800mV*1023 + key_tolerance = <40 40 40>; + }; + + unifykey{ + compatible = "amlogic, unifykey"; + status = "ok"; + unifykey-num = <14>; + unifykey-index-0 = <&keysn_0>; + unifykey-index-1 = <&keysn_1>; + unifykey-index-2 = <&keysn_2>; + unifykey-index-3 = <&keysn_3>; + unifykey-index-4 = <&keysn_4>; + unifykey-index-5 = <&keysn_5>; + unifykey-index-6 = <&keysn_6>; + unifykey-index-7 = <&keysn_7>; + unifykey-index-8 = <&keysn_8>; + unifykey-index-9 = <&keysn_9>; + unifykey-index-10= <&keysn_10>; + unifykey-index-11= <&keysn_11>; + unifykey-index-12= <&keysn_12>; + unifykey-index-13= <&keysn_13>; + + keysn_0: key_0{ + key-name = "usid"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_1:key_1{ + key-name = "mac"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_2:key_2{ + key-name = "hdcp"; + key-device = "secure"; + key-type = "sha1"; + key-permit = "read","write","del"; + }; + keysn_3:key_3{ + key-name = "secure_boot_set"; + key-device = "efuse"; + key-permit = "write"; + }; + keysn_4:key_4{ + key-name = "mac_bt"; + key-device = "normal"; + key-permit = "read","write","del"; + key-type = "mac"; + }; + keysn_5:key_5{ + key-name = "mac_wifi"; + key-device = "normal"; + key-permit = "read","write","del"; + key-type = "mac"; + }; + keysn_6:key_6{ + key-name = "hdcp2_tx"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_7:key_7{ + key-name = "hdcp2_rx"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_8:key_8{ + key-name = "widevinekeybox"; + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_9:key_9{ + key-name = "deviceid"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_10:key_10{ + key-name = "hdcp22_fw_private"; + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_11:key_11{ + key-name = "PlayReadykeybox25"; + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_12:key_12{ + key-name = "prpubkeybox";// PlayReady + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_13:key_13{ + key-name = "prprivkeybox";// PlayReady + key-device = "secure"; + key-permit = "read","write","del"; + }; + };//End unifykey + + amlvecm { + compatible = "amlogic, vecm"; + dev_name = "aml_vecm"; + status = "okay"; + gamma_en = <0>;/*1:enabel ;0:disable*/ + wb_en = <0>;/*1:enabel ;0:disable*/ + cm_en = <0>;/*1:enabel ;0:disable*/ + }; + amdolby_vision { + compatible = "amlogic, dolby_vision_g12a"; + dev_name = "aml_amdolby_vision_driver"; + status = "okay"; + tv_mode = <0>;/*1:enabel ;0:disable*/ + }; + + /* Audio Related start */ + pdm_codec:dummy{ + #sound-dai-cells = <0>; + compatible = "amlogic, pdm_dummy_codec"; + status = "okay"; + }; + dummy_codec:dummy{ + #sound-dai-cells = <0>; + compatible = "amlogic, aml_dummy_codec"; + status = "okay"; + }; + amlogic_codec:t9015{ + #sound-dai-cells = <0>; + compatible = "amlogic, aml_codec_T9015"; + reg = <0xFF632000 0x2000>; + is_auge_used = <1>; /* meson or auge chipset used */ + tdmout_index = <1>; + status = "okay"; + }; + audio_effect:eqdrc{ + /*eq_enable = <1>;*/ + /*drc_enable = <1>;*/ + /* + * 0:tdmout_a + * 1:tdmout_b + * 2:tdmout_c + * 3:spdifout + * 4:spdifout_b + */ + eqdrc_module = <1>; + /* max 0xf, each bit for one lane, usually one lane */ + lane_mask = <0x1>; + /* max 0xff, each bit for one channel */ + channel_mask = <0x3>; + }; + auge_sound { + compatible = "amlogic, g12a-sound-card"; + aml-audio-card,name = "AML-AUGESOUND"; + + //aml-audio-card,loopback = <&aml_loopback>; + //aml-audio-card,aux-devs = <&amlogic_codec>; + /*avout mute gpio*/ + avout_mute-gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_HIGH>; + /*for audio effect ,eqdrc */ + aml-audio-card,effect = <&audio_effect>; + + aml-audio-card,dai-link@0 { + format = "dsp_a"; + mclk-fs = <512>; + //continuous-clock; + //bitclock-inversion; + //frame-inversion; + //bitclock-master = <&tdmacodec>; + //frame-master = <&tdmacodec>; + /* suffix-name, sync with android audio hal + * what's the dai link used for + */ + suffix-name = "alsaPORT-pcm"; + tdmacpu: cpu { + sound-dai = <&aml_tdma>; + dai-tdm-slot-tx-mask = + <1 1 1 1 1 1 1 1>; + dai-tdm-slot-rx-mask = + <1 1 1 1 1 1 1 1>; + dai-tdm-slot-num = <8>; + dai-tdm-slot-width = <32>; + system-clock-frequency = <24576000>; + }; + tdmacodec: codec { + sound-dai = <&dummy_codec &dummy_codec>; + }; + }; + + aml-audio-card,dai-link@1 { + format = "i2s"; + mclk-fs = <256>; + //continuous-clock; + //bitclock-inversion; + //frame-inversion; + bitclock-master = <&aml_tdmb>; + frame-master = <&aml_tdmb>; + //bitclock-master = <&tdmbcodec>; + //frame-master = <&tdmbcodec>; + /* suffix-name, sync with android audio hal + * what's the dai link used for + */ + suffix-name = "alsaPORT-i2s"; + cpu { + sound-dai = <&aml_tdmb>; + dai-tdm-slot-tx-mask = <1 1>; + dai-tdm-slot-rx-mask = <1 1>; + dai-tdm-slot-num = <2>; + dai-tdm-slot-width = <32>; + system-clock-frequency = <12288000>; + }; + tdmbcodec: codec { + sound-dai = <&dummy_codec &dummy_codec + &amlogic_codec &ad82584f_62>; + }; + }; + + aml-audio-card,dai-link@2 { + format = "i2s"; + mclk-fs = <256>; + //continuous-clock; + //bitclock-inversion; + //frame-inversion; + bitclock-master = <&aml_tdmc>; + frame-master = <&aml_tdmc>; + /* suffix-name, sync with android audio hal + * what's the dai link used for + */ + //suffix-name = "alsaPORT-tdm"; + cpu { + sound-dai = <&aml_tdmc>; + dai-tdm-slot-tx-mask = <1 1>; + dai-tdm-slot-rx-mask = <1 1>; + dai-tdm-slot-num = <2>; + dai-tdm-slot-width = <32>; + system-clock-frequency = <12288000>; + }; + codec { + sound-dai = <&dummy_codec &dummy_codec>; + }; + }; + + aml-audio-card,dai-link@3 { + mclk-fs = <64>; + /* suffix-name, sync with android audio hal + * what's the dai link used for + */ + suffix-name = "alsaPORT-pdm"; + cpu { + sound-dai = <&aml_pdm>; + }; + codec { + sound-dai = <&pdm_codec>; + }; + }; + + aml-audio-card,dai-link@4 { + mclk-fs = <128>; + /* suffix-name, sync with android audio hal + * what's the dai link used for + */ + suffix-name = "alsaPORT-spdif"; + cpu { + sound-dai = <&aml_spdif>; + system-clock-frequency = <6144000>; + }; + codec { + sound-dai = <&dummy_codec>; + }; + }; + }; + audiolocker: locker { + compatible = "amlogic, audiolocker"; + clocks = <&clkaudio CLKID_AUDIO_LOCKER_OUT + &clkaudio CLKID_AUDIO_LOCKER_IN + &clkaudio CLKID_AUDIO_MCLK_D + &clkaudio CLKID_AUDIO_MCLK_E + &clkc CLKID_MPLL1 + &clkc CLKID_MPLL2>; + clock-names = "lock_out", "lock_in", "out_src", + "in_src", "out_calc", "in_ref"; + interrupts = ; + interrupt-names = "irq"; + frequency = <49000000>; /* pll */ + dividor = <49>; /* locker's parent */ + status = "okay"; + }; + /* Audio Related end */ + + cpu_opp_table0: cpu_opp_table0 { + compatible = "operating-points-v2"; + opp-shared; + + opp00 { + opp-hz = /bits/ 64 <100000000>; + opp-microvolt = <731000>; + }; + opp01 { + opp-hz = /bits/ 64 <250000000>; + opp-microvolt = <731000>; + }; + opp02 { + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <731000>; + }; + opp03 { + opp-hz = /bits/ 64 <667000000>; + opp-microvolt = <731000>; + }; + opp04 { + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <731000>; + }; + opp05 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <731000>; + }; + opp06 { + opp-hz = /bits/ 64 <1398000000>; + opp-microvolt = <761000>; + }; + opp07 { + opp-hz = /bits/ 64 <1512000000>; + opp-microvolt = <791000>; + }; + opp08 { + opp-hz = /bits/ 64 <1608000000>; + opp-microvolt = <831000>; + }; + opp09 { + opp-hz = /bits/ 64 <1704000000>; + opp-microvolt = <861000>; + }; + opp10 { + opp-hz = /bits/ 64 <1800000000>; + opp-microvolt = <981000>; + }; + }; + + cpu_opp_table1: cpu_opp_table1 { + compatible = "operating-points-v2"; + opp-shared; + + opp00 { + opp-hz = /bits/ 64 <100000000>; + opp-microvolt = <751000>; + }; + opp01 { + opp-hz = /bits/ 64 <250000000>; + opp-microvolt = <751000>; + }; + opp02 { + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <751000>; + }; + opp03 { + opp-hz = /bits/ 64 <667000000>; + opp-microvolt = <751000>; + }; + opp04 { + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <771000>; + }; + opp05 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <771000>; + }; + opp06 { + opp-hz = /bits/ 64 <1398000000>; + opp-microvolt = <791000>; + }; + opp07 { + opp-hz = /bits/ 64 <1512000000>; + opp-microvolt = <821000>; + }; + opp08 { + opp-hz = /bits/ 64 <1608000000>; + opp-microvolt = <861000>; + }; + opp09 { + opp-hz = /bits/ 64 <1704000000>; + opp-microvolt = <891000>; + }; + }; + + cpufreq-meson { + compatible = "amlogic, cpufreq-meson"; + status = "okay"; + }; + + sensor: sensor { + compatible = "soc, sensor"; + status = "okay"; + sensor-name = "imx290"; /*imx290;os08a10;imx227*/ + pinctrl-names="default"; + pinctrl-0=<&clk12_24_z_pins>; + clocks = <&clkc CLKID_24M>; + clock-names = "g12a_24m"; + reset = <&gpio GPIOZ_12 GPIO_ACTIVE_HIGH>; + }; + + iq: iq { + compatible = "soc, iq"; + status = "okay"; + sensor-name = "imx290"; /*imx290;os08a10;imx227*/ + }; +}; /* end of / */ + +&i2c2 { + status = "okay"; + pinctrl-names="default"; + pinctrl-0=<&i2c2_master_pins2>; + clock-frequency = <100000>; /* default 100k */ + sensor-i2c@6c { + compatible = "arm, i2c-sensor"; + reg = <0x6c>; + reg-names = "i2c-sensor"; + slave-addr = <0x6c>; + reg-type = <2>; + reg-data-type = <1>; + link-device = <&phycsi>; + }; +}; + +&isp { + status = "okay"; + memory-region = <&isp_cma_reserved>; +}; + +&adapter { + status = "okay"; + memory-region = <&adapt_cma_reserved>; +}; + +&gdc { + status = "okay"; + memory-region = <&gdc_cma_reserved>; +}; + +&meson_fb { + status = "okay"; + display_size_default = <1920 1080 1920 2160 32>; + mem_size = <0x00800000 0x1980000 0x100000 0x100000 0x800000>; + logo_addr = "0x7f800000"; + mem_alloc = <1>; + pxp_mode = <0>; /** 0:normal mode 1:pxp mode */ +}; + +&pwm_ab { + status = "okay"; + }; + +&pwm_ef { + status = "okay"; + }; + +&pwm_AO_cd { + status = "okay"; + }; + +&i2c0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_master_pins2>; + clock-frequency = <400000>; + + touchscreen@38 { + compatible = "focaltech,fts"; + status = "disabled"; + reg = <0x38>; + reset-gpio = <&gpio GPIOZ_9 GPIO_ACTIVE_HIGH>; + irq-gpio = <&gpio GPIOZ_3 GPIO_ACTIVE_HIGH>; + x_max = <720>; + y_max = <1280>; + max-touch-number = <10>; + }; +}; + +&i2c3 { + status = "okay"; + pinctrl-names="default"; + pinctrl-0=<&i2c3_master_pins2>; + clock-frequency = <100000>; /* default 100k */ + + /* for ref board */ + ad82584f_62: ad82584f_62@62 { + compatible = "ESMT, ad82584f"; + #sound-dai-cells = <0>; + reg = <0x31>; + status = "okay"; + reset_pin = <&gpio GPIOA_5 0>; + }; + + tlv320adc3101_32: tlv320adc3101_32@32 { + compatible = "ti,tlv320adc3101"; + #sound-dai-cells = <0>; + reg = <0x19>; + differential_pair = <1>; + status = "disabled"; + }; + + bl_extern_i2c { + compatible = "bl_extern, i2c"; + dev_name = "lp8556"; + reg = <0x2c>; + status = "disabled"; + }; +}; + +&audiobus { + aml_tdma: tdma { + compatible = "amlogic, g12a-snd-tdma"; + #sound-dai-cells = <0>; + dai-tdm-lane-slot-mask-in = <0 1>; + dai-tdm-oe-lane-slot-mask-out = <1 0>; + dai-tdm-clk-sel = <0>; + clocks = <&clkaudio CLKID_AUDIO_MCLK_A + &clkc CLKID_MPLL0>; + clock-names = "mclk", "clk_srcpll"; + pinctrl-names = "tdm_pins"; + pinctrl-0 = <&tdmout_a &tdmin_a>; + }; + + aml_tdmb: tdmb { + compatible = "amlogic, g12a-snd-tdmb"; + #sound-dai-cells = <0>; + dai-tdm-lane-slot-mask-in = <0 1 0 0>; + dai-tdm-lane-slot-mask-out = <1 0 0 0>; + dai-tdm-clk-sel = <1>; + clocks = <&clkaudio CLKID_AUDIO_MCLK_B + &clkc CLKID_MPLL1 + &clkc CLKID_MPLL0>; + clock-names = "mclk", "clk_srcpll", "samesource_sysclk"; + pinctrl-names = "tdm_pins"; + pinctrl-0 = <&tdmb_mclk &tdmout_b &tdmin_b>; + /* + * 0: tdmout_a; + * 1: tdmout_b; + * 2: tdmout_c; + * 3: spdifout; + * 4: spdifout_b; + */ + samesource_sel = <3>; + }; + + aml_tdmc: tdmc { + compatible = "amlogic, g12a-snd-tdmc"; + #sound-dai-cells = <0>; + dai-tdm-lane-slot-mask-in = <1 0 0 0>; + #dai-tdm-lane-slot-mask-out = <1 0 1 1>; + #dai-tdm-lane-oe-slot-mask-in = <0 0 0 0>; + #dai-tdm-lane-oe-slot-mask-out = <1 0 0 0>; + dai-tdm-clk-sel = <2>; + clocks = <&clkaudio CLKID_AUDIO_MCLK_C + &clkc CLKID_MPLL2>; + clock-names = "mclk", "clk_srcpll"; + pinctrl-names = "tdm_pins"; + pinctrl-0 = <&tdmc_mclk &tdmout_c &tdmin_c>; + }; + + /* copy a useless tdm to output for hdmi, no pinmux */ + aml_i2s2hdmi: i2s2hdmi { + compatible = "amlogic, g12a-snd-tdmc"; + #sound-dai-cells = <0>; + dai-tdm-lane-slot-mask-out = <1 1 1 1>; + dai-tdm-clk-sel = <2>; + clocks = <&clkaudio CLKID_AUDIO_MCLK_C + &clkc CLKID_MPLL2>; + clock-names = "mclk", "clk_srcpll"; + + i2s2hdmi = <1>; + + status = "okay"; + }; + + aml_spdif: spdif { + compatible = "amlogic, g12a-snd-spdif-a"; + #sound-dai-cells = <0>; + clocks = <&clkc CLKID_MPLL0 + &clkc CLKID_FCLK_DIV4 + &clkaudio CLKID_AUDIO_SPDIFIN + &clkaudio CLKID_AUDIO_SPDIFOUT + &clkaudio CLKID_AUDIO_SPDIFIN_CTRL + &clkaudio CLKID_AUDIO_SPDIFOUT_CTRL>; + clock-names = "sysclk", "fixed_clk", "gate_spdifin", + "gate_spdifout", "clk_spdifin", "clk_spdifout"; + interrupts = + ; + + interrupt-names = "irq_spdifin"; + pinctrl-names = "spdif_pins"; + pinctrl-0 = <&spdifout &spdifin>; + status = "okay"; + }; + aml_spdif_b: spdif_b { + compatible = "amlogic, g12a-snd-spdif-b"; + #sound-dai-cells = <0>; + clocks = <&clkc CLKID_MPLL0 /*CLKID_HIFI_PLL*/ + &clkaudio CLKID_AUDIO_SPDIFOUTB + &clkaudio CLKID_AUDIO_SPDIFOUTB_CTRL>; + clock-names = "sysclk", + "gate_spdifout", "clk_spdifout"; + status = "disabled"; + }; + aml_pdm: pdm { + compatible = "amlogic, g12a-snd-pdm"; + #sound-dai-cells = <0>; + clocks = <&clkaudio CLKID_AUDIO_PDM + &clkc CLKID_FCLK_DIV3 + &clkc CLKID_MPLL3 + &clkaudio CLKID_AUDIO_PDMIN0 + &clkaudio CLKID_AUDIO_PDMIN1>; + clock-names = "gate", + "sysclk_srcpll", + "dclk_srcpll", + "pdm_dclk", + "pdm_sysclk"; + pinctrl-names = "pdm_pins"; + pinctrl-0 = <&pdmin>; + filter_mode = <1>; /* mode 0~4, defalut:1 */ + status = "okay"; + }; + aml_loopback: loopback { + compatible = "amlogic, snd-loopback"; + /* + * 0: out rate = in data rate; + * 1: out rate = loopback data rate; + */ + lb_mode = <0>; + + /* datain src + * 0: tdmin_a; + * 1: tdmin_b; + * 2: tdmin_c; + * 3: spdifin; + * 4: pdmin; + */ + datain_src = <4>; + datain_chnum = <8>; + datain_chmask = <0x3f>; + + /* tdmin_lb src + * 0: tdmoutA + * 1: tdmoutB + * 2: tdmoutC + * 3: PAD_tdminA + * 4: PAD_tdminB + * 5: PAD_tdminC + */ + datalb_src = <2>; + datalb_chnum = <8>; + datalb_chmask = <0x3>; + + status = "disabled"; + }; + + audioresample: resample { + compatible = "amlogic, g12a-resample"; + clocks = <&clkc CLKID_MPLL3 + &clkaudio CLKID_AUDIO_MCLK_F + &clkaudio CLKID_AUDIO_RESAMPLE_CTRL>; + clock-names = "resample_pll", "resample_src", "resample_clk"; + /*same with toddr_src + * TDMIN_A, 0 + * TDMIN_B, 1 + * TDMIN_C, 2 + * SPDIFIN, 3 + * PDMIN, 4 + * NONE, + * TDMIN_LB, 6 + * LOOPBACK, 7 + */ + resample_module = <4>; + status = "disabled"; + }; + aml_pwrdet: pwrdet { + compatible = "amlogic, g12a-power-detect"; + + interrupts = ; + interrupt-names = "pwrdet_irq"; + + /* pwrdet source sel + * 7: loopback; + * 6: tdmin_lb; + * 5: reserved; + * 4: pdmin; + * 3: spdifin; + * 2: tdmin_c; + * 1: tdmin_b; + * 0: tdmin_a; + */ + pwrdet_src = <4>; + + hi_th = <0x70000>; + lo_th = <0x16000>; + + status = "disabled"; + }; +}; /* end of audiobus */ + +&pinctrl_periphs { + tdmout_a: tdmout_a { + mux { /* GPIOX_11, GPIOX_10, GPIOX_9 */ + groups = "tdma_sclk", + "tdma_fs", + "tdma_dout0"; + function = "tdma_out"; + }; + }; + + tdmin_a: tdmin_a { + mux { /* GPIOX_8 */ + groups = "tdma_din1"; + function = "tdma_in"; + }; + }; + + tdmb_mclk: tdmb_mclk { + mux { + groups = "mclk0_a"; + function = "mclk0"; + drive-strength = <2>; + }; + }; + tdmout_b: tdmout_b { + mux { /* GPIOA_1, GPIOA_2, GPIOA_3 */ + groups = "tdmb_sclk", + "tdmb_fs", + "tdmb_dout0"; + function = "tdmb_out"; + drive-strength = <2>; + }; + }; + + tdmin_b:tdmin_b { + mux { /* GPIOA_4 */ + groups = "tdmb_din1" + /*,"tdmb_slv_sclk", "tdmb_slv_fs"*/; + function = "tdmb_in"; + drive-strength = <2>; + }; + }; + + tdmc_mclk: tdmc_mclk { + mux { /* GPIOA_11 */ + groups = "mclk1_a"; + function = "mclk1"; + }; + }; + + clk12_24_z_pins:clk12_24_z_pins { + mux { + groups = "clk12_24_z"; + function = "clk12_24_ee"; + drive-strength = <3>; + }; + }; + + tdmout_c:tdmout_c { + mux { /* GPIOA_12, GPIOA_13, GPIOA_8, GPIOA_7*/ + groups = "tdmc_sclk_a", + "tdmc_fs_a", + "tdmc_dout0_a" + /*, "tdmc_dout2", + * "tdmc_dout3" + */; + function = "tdmc_out"; + }; + }; + + tdmin_c:tdmin_c { + mux { /* GPIOA_10 */ + groups = "tdmc_din0_a"; + function = "tdmc_in"; + }; + }; + + spdifin: spdifin { + mux {/* GPIOH_5 */ + groups = "spdif_in_h"; + function = "spdif_in"; + }; + }; + + /* GPIOH_4 */ + /* + * spdifout: spdifout { + * mux { + * groups = "spdif_out_h"; + * function = "spdif_out"; + * }; + *}; + */ + + pdmin: pdmin { + mux { /* gpioa_5, gpioa_6, gpioa_7, gpioa_8, gpioa_9*/ + groups = "pdm_din0_a", + /*"pdm_din1_a",*/ + "pdm_din2_a", + /*"pdm_din3_a",*/ + "pdm_dclk_a"; + function = "pdm"; + }; + }; + + bl_pwm_off_pins:bl_pwm_off_pin { + mux { + pins = "GPIOH_5"; + function = "gpio_periphs"; + output-high; + }; + }; + +}; /* end of pinctrl_periphs */ + +&pinctrl_aobus { + spdifout: spdifout { + mux { /* gpiao_10 */ + groups = "spdif_out_ao"; + function = "spdif_out_ao"; + }; + }; +}; /* end of pinctrl_aobus */ + +&irblaster { + status = "disabled"; +}; + +&audio_data { + status = "okay"; +}; + +/*if you want to use vdin just modify status to "ok"*/ +&vdin0 { + memory-region = <&vdin0_cma_reserved>; + status = "okay"; + /*vdin write mem color depth support: + *bit0:support 8bit + *bit1:support 9bit + *bit2:support 10bit + *bit3:support 12bit + *bit4:support yuv422 10bit full pack mode (from txl new add) + */ + tv_bit_mode = <0x15>; +}; +&vdin1 { + memory-region = <&vdin1_cma_reserved>; + status = "okay"; + /*vdin write mem color depth support: + *bit0:support 8bit + *bit1:support 9bit + *bit2:support 10bit + *bit3:support 12bit + */ + tv_bit_mode = <1>; +}; + +&sd_emmc_c { + status = "okay"; + emmc { + caps = "MMC_CAP_8_BIT_DATA", + "MMC_CAP_MMC_HIGHSPEED", + "MMC_CAP_SD_HIGHSPEED", + "MMC_CAP_NONREMOVABLE", + /* "MMC_CAP_1_8V_DDR", */ + "MMC_CAP_HW_RESET", + "MMC_CAP_ERASE", + "MMC_CAP_CMD23"; + caps2 = "MMC_CAP2_HS200"; + /* "MMC_CAP2_HS400";*/ + f_min = <400000>; + f_max = <200000000>; + }; +}; + +&sd_emmc_b { + status = "okay"; + sd { + caps = "MMC_CAP_4_BIT_DATA", + "MMC_CAP_MMC_HIGHSPEED", + "MMC_CAP_SD_HIGHSPEED"; + f_min = <400000>; + f_max = <50000000>; + }; +}; + +&sd_emmc_a { + status = "okay"; + sdio { + caps = "MMC_CAP_4_BIT_DATA", + "MMC_CAP_MMC_HIGHSPEED", + "MMC_CAP_SD_HIGHSPEED", + "MMC_CAP_NONREMOVABLE", + "MMC_CAP_UHS_SDR12", + "MMC_CAP_UHS_SDR25", + "MMC_CAP_UHS_SDR50", + "MMC_CAP_UHS_SDR104", + "MMC_PM_KEEP_POWER", + "MMC_CAP_SDIO_IRQ"; + f_min = <400000>; + f_max = <200000000>; + }; +}; + +&nand { + status = "disabled"; + plat-names = "bootloader","nandnormal"; + plat-num = <2>; + plat-part-0 = <&bootloader>; + plat-part-1 = <&nandnormal>; + bootloader: bootloader{ + enable_pad ="ce0"; + busy_pad = "rb0"; + timming_mode = "mode5"; + bch_mode = "bch8_1k"; + t_rea = <20>; + t_rhoh = <15>; + chip_num = <1>; + part_num = <0>; + rb_detect = <1>; + }; + nandnormal: nandnormal{ + enable_pad ="ce0"; + busy_pad = "rb0"; + timming_mode = "mode5"; + bch_mode = "bch8_1k"; + plane_mode = "twoplane"; + t_rea = <20>; + t_rhoh = <15>; + chip_num = <2>; + part_num = <3>; + partition = <&nand_partitions>; + rb_detect = <1>; + }; + nand_partitions:nand_partition{ + /* + * if bl_mode is 1, tpl size was generate by + * fip_copies * fip_size which + * will not skip bad when calculating + * the partition size; + * + * if bl_mode is 0, + * tpl partition must be comment out. + */ + tpl{ + offset=<0x0 0x0>; + size=<0x0 0x0>; + }; + logo{ + offset=<0x0 0x0>; + size=<0x0 0x200000>; + }; + recovery{ + offset=<0x0 0x0>; + size=<0x0 0x1000000>; + }; + boot{ + offset=<0x0 0x0>; + size=<0x0 0x1000000>; + }; + system{ + offset=<0x0 0x0>; + size=<0x0 0x4000000>; + }; + data{ + offset=<0xffffffff 0xffffffff>; + size=<0x0 0x0>; + }; + }; +}; +&dwc3 { + status = "okay"; +}; + +&usb2_phy_v2 { + status = "okay"; + portnum = <2>; +}; + +&usb3_phy_v2 { + status = "okay"; + portnum = <0>; + otg = <1>; + gpio-vbus-power = "GPIOH_6"; + gpios = <&gpio GPIOH_6 GPIO_ACTIVE_HIGH>; +}; + +&dwc2_a { + status = "okay"; + /** 0: normal, 1: otg+dwc3 host only, 2: otg+dwc3 device only*/ + controller-type = <3>; +}; +ðmac { + status = "okay"; +/* //conflict with isp i2c + * pinctrl-names = "internal_eth_pins"; + * pinctrl-0 = <&internal_eth_pins>; + */ + mc_val = <0x4be04>; + + internal_phy=<1>; +}; + +&uart_A { + status = "okay"; +}; + +&pcie_A { + reset-gpio = <&gpio GPIOX_7 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&saradc { + status = "okay"; +}; + +&spicc1 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&spicc1_pins>; + cs-gpios = <&gpio GPIOH_6 0>; +}; diff --git a/arch/arm/boot/dts/amlogic/g12b_a311d_w400_buildroot_vccktest.dts b/arch/arm/boot/dts/amlogic/g12b_a311d_w400_buildroot_vccktest.dts new file mode 100644 index 000000000000..27936bd825ef --- /dev/null +++ b/arch/arm/boot/dts/amlogic/g12b_a311d_w400_buildroot_vccktest.dts @@ -0,0 +1,1334 @@ +/* + * arch/arm/boot/dts/amlogic/g12b_a311d_w400_buildroot.dts + * + * Copyright (C) 2017 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +/dts-v1/; + +#include "mesong12b.dtsi" +#include "mesong12b_skt-panel.dtsi" + +/ { + model = "Amlogic"; + compatible = "amlogic, g12b"; + interrupt-parent = <&gic>; + #address-cells = <1>; + #size-cells = <1>; + + aliases { + serial0 = &uart_AO; + serial1 = &uart_A; + serial2 = &uart_B; + serial3 = &uart_C; + serial4 = &uart_AO_B; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c_AO; + tsensor0 = &p_tsensor; + tsensor1 = &d_tsensor; + }; + + memory@00000000 { + device_type = "memory"; + linux,usable-memory = <0x100000 0x7ff00000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + /* global autoconfigured region for contiguous allocations */ + ramoops@0x07400000 { + compatible = "ramoops"; + reg = <0x07400000 0x00100000>; + record-size = <0x8000>; + console-size = <0x8000>; + ftrace-size = <0x0>; + pmsg-size = <0x8000>; + }; + + secmon_reserved:linux,secmon { + compatible = "shared-dma-pool"; + reusable; + size = <0x400000>; + alignment = <0x400000>; + alloc-ranges = <0x05000000 0x400000>; + }; + + secos_reserved:linux,secos { + status = "disable"; + compatible = "amlogic, aml_secos_memory"; + reg = <0x05300000 0x2000000>; + no-map; + }; + logo_reserved:linux,meson-fb { + compatible = "shared-dma-pool"; + reusable; + size = <0x800000>; + alignment = <0x400000>; + alloc-ranges = <0x7f800000 0x800000>; + }; + ion_cma_reserved:linux,ion-dev { + compatible = "shared-dma-pool"; + reusable; + size = <0x8000000>; + alignment = <0x400000>; + }; + + //di_reserved:linux,di { + //compatible = "amlogic, di-mem"; + /* buffer_size = 3621952(yuv422 8bit) */ + /* 4179008(yuv422 10bit full pack mode) */ + /** 10x3621952=34.6M(0x23) support 8bit **/ + /** 10x4736064=45.2M(0x2e) support 12bit **/ + /** 10x4179008=40M(0x28) support 10bit **/ + //size = <0x2800000>; + //no-map; + //}; + /*di CMA pool */ + di_cma_reserved:linux,di_cma { + compatible = "shared-dma-pool"; + reusable; + /* buffer_size = 3621952(yuv422 8bit) + * | 4736064(yuv422 10bit) + * | 4074560(yuv422 10bit full pack mode) + * 10x3621952=34.6M(0x23) support 8bit + * 10x4736064=45.2M(0x2e) support 12bit + * 10x4074560=40M(0x28) support 10bit + */ + size = <0x02800000>; + alignment = <0x400000>; + }; + /* POST PROCESS MANAGER */ + ppmgr_reserved:linux,ppmgr { + compatible = "shared-dma-pool"; + size = <0x0>; + }; + codec_mm_cma:linux,codec_mm_cma { + compatible = "shared-dma-pool"; + reusable; + /* ion_codec_mm max can alloc size 80M*/ + size = <0x13400000>; + alignment = <0x400000>; + linux,contiguous-region; + }; + /* codec shared reserved */ + codec_mm_reserved:linux,codec_mm_reserved { + compatible = "amlogic, codec-mm-reserved"; + size = <0x0>; + alignment = <0x100000>; + //no-map; + }; + /* vdin0 CMA pool */ + vdin0_cma_reserved:linux,vdin0_cma { + compatible = "shared-dma-pool"; + reusable; + /* 1920x1080x2x4 =16+4 M */ + size = <0x04000000>; + alignment = <0x400000>; + }; + /* vdin1 CMA pool */ + vdin1_cma_reserved:linux,vdin1_cma { + compatible = "shared-dma-pool"; + reusable; + /* 1920x1080x2x4 =16 M */ + size = <0x04000000>; + alignment = <0x400000>; + }; + }; + + gpioleds { + compatible = "gpio-leds"; + status = "okay"; + + sys_led { + label="sys_led"; + gpios=<&gpio_ao GPIOAO_11 GPIO_ACTIVE_HIGH>; + default-state ="on"; + retain-state-suspended; + linux,default-trigger="cpu0"; + }; + }; + + cvbsout { + compatible = "amlogic, cvbsout-g12b"; + dev_name = "cvbsout"; + status = "okay"; + clocks = <&clkc CLKID_VCLK2_ENCI + &clkc CLKID_VCLK2_VENCI0 + &clkc CLKID_VCLK2_VENCI1 + &clkc CLKID_DAC_CLK>; + clock-names = "venci_top_gate", + "venci_0_gate", + "venci_1_gate", + "vdac_clk_gate"; + + /* performance: reg_address, reg_value */ + /* g12b */ + performance = <0x1bf0 0x9 + 0x1b56 0x333 + 0x1b12 0x8080 + 0x1b05 0xfd + 0x1c59 0xf850 + 0xffff 0x0>; /* ending flag */ + performance_sarft = <0x1bf0 0x9 + 0x1b56 0x333 + 0x1b12 0x0 + 0x1b05 0x9 + 0x1c59 0xfc48 + 0xffff 0x0>; /* ending flag */ + }; + + bt-dev{ + compatible = "amlogic, bt-dev"; + dev_name = "bt-dev"; + status = "okay"; + gpio_reset = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>; + gpio_hostwake = <&gpio GPIOX_19 GPIO_ACTIVE_HIGH>; + }; + + wifi{ + compatible = "amlogic, aml_wifi"; + dev_name = "aml_wifi"; + status = "okay"; + interrupt_pin = <&gpio GPIOX_7 GPIO_ACTIVE_HIGH>; + irq_trigger_type = "GPIO_IRQ_LOW"; + power_on_pin = <&gpio GPIOX_6 GPIO_ACTIVE_HIGH>; + dhd_static_buf; //if use bcm wifi, config dhd_static_buf + pinctrl-names = "default"; + pinctrl-0 = <&pwm_e_pins>; + pwm_config = <&wifi_pwm_conf>; + }; + + wifi_pwm_conf:wifi_pwm_conf{ + pwm_channel1_conf { + pwms = <&pwm_ef MESON_PWM_0 30040 0>; + duty-cycle = <15020>; + times = <10>; + }; + pwm_channel2_conf { + pwms = <&pwm_ef MESON_PWM_2 30030 0>; + duty-cycle = <15015>; + times = <12>; + }; + }; + + codec_mm { + compatible = "amlogic, codec, mm"; + memory-region = <&codec_mm_cma &codec_mm_reserved>; + dev_name = "codec_mm"; + status = "okay"; + }; + + ppmgr { + compatible = "amlogic, ppmgr"; + memory-region = <&ppmgr_reserved>; + dev_name = "ppmgr"; + status = "okay"; + }; + + deinterlace { + compatible = "amlogic, deinterlace"; + status = "okay"; + /* 0:use reserved; 1:use cma; 2:use cma as reserved */ + flag_cma = <1>; + //memory-region = <&di_reserved>; + memory-region = <&di_cma_reserved>; + interrupts = <0 46 1 + 0 40 1>; + interrupt-names = "pre_irq", "post_irq"; + clocks = <&clkc CLKID_VPU_CLKB_TMP_COMP>, + <&clkc CLKID_VPU_CLKB_COMP>; + clock-names = "vpu_clkb_tmp_composite", + "vpu_clkb_composite"; + clock-range = <334 667>; + /* buffer-size = <3621952>;(yuv422 8bit) */ + buffer-size = <4074560>;/*yuv422 fullpack*/ + /* reserve-iomap = "true"; */ + /* if enable nr10bit, set nr10bit-support to 1 */ + post-wr-support = <1>; + nr10bit-support = <1>; + nrds-enable = <1>; + pps-enable = <1>; + }; + ionvideo { + compatible = "amlogic, ionvideo"; + dev_name = "ionvideo"; + status = "okay"; + }; + + + partitions: partitions{ + parts = <14>; + part-0 = <&logo>; + part-1 = <&recovery>; + part-2 = <&misc>; + part-3 = <&dto>; + part-4 = <&cri_data>; + part-5 = <¶m>; + part-6 = <&boot>; + part-7 = <&rsv>; + part-8 = <&tee>; + part-9 = <&vendor>; + part-10 = <&odm>; + part-11 = <&system>; + part-12 = <&cache>; + part-13 = <&data>; + + logo:logo{ + pname = "logo"; + size = <0x0 0x800000>; + mask = <1>; + }; + recovery:recovery{ + pname = "recovery"; + size = <0x0 0x1800000>; + mask = <1>; + }; + misc:misc{ + pname = "misc"; + size = <0x0 0x800000>; + mask = <1>; + }; + dto:dto{ + pname = "dto"; + size = <0x0 0x800000>; + mask = <1>; + }; + cri_data:cri_data{ + pname = "cri_data"; + size = <0x0 0x800000>; + mask = <2>; + }; + rsv:rsv{ + pname = "rsv"; + size = <0x0 0x1000000>; + mask = <1>; + }; + param:param{ + pname = "param"; + size = <0x0 0x1000000>; + mask = <2>; + }; + boot:boot{ + pname = "boot"; + size = <0x0 0x1000000>; + mask = <1>; + }; + tee:tee{ + pname = "tee"; + size = <0x0 0x2000000>; + mask = <1>; + }; + vendor:vendor{ + pname = "vendor"; + size = <0x0 0x10000000>; + mask = <1>; + }; + odm:odm{ + pname = "odm"; + size = <0x0 0x10000000>; + mask = <1>; + }; + system:system{ + pname = "system"; + size = <0x0 0x80000000>; + mask = <1>; + }; + cache:cache{ + pname = "cache"; + size = <0x0 0x46000000>; + mask = <2>; + }; + data:data{ + pname = "data"; + size = <0xffffffff 0xffffffff>; + mask = <4>; + }; + }; + + gpio_keypad { + compatible = "amlogic, gpio_keypad"; + status = "okay"; + scan_period = <20>; + key_num = <1>; + key_name = "power"; + key_code = <116>; + key-gpios = <&gpio_ao GPIOAO_3 GPIO_ACTIVE_HIGH>; + detect_mode = <0>;/*0:polling mode, 1:irq mode*/ + }; + + adc_keypad { + compatible = "amlogic, adc_keypad"; + status = "okay"; + key_name = "vol-", "vol+", "enter"; + key_num = <3>; + io-channels = <&saradc SARADC_CH2>; + io-channel-names = "key-chan-2"; + key_chan = ; + key_code = <114 115 28>; + key_val = <143 266 389>; //val=voltage/1800mV*1023 + key_tolerance = <40 40 40>; + }; + + unifykey{ + compatible = "amlogic, unifykey"; + status = "ok"; + unifykey-num = <14>; + unifykey-index-0 = <&keysn_0>; + unifykey-index-1 = <&keysn_1>; + unifykey-index-2 = <&keysn_2>; + unifykey-index-3 = <&keysn_3>; + unifykey-index-4 = <&keysn_4>; + unifykey-index-5 = <&keysn_5>; + unifykey-index-6 = <&keysn_6>; + unifykey-index-7 = <&keysn_7>; + unifykey-index-8 = <&keysn_8>; + unifykey-index-9 = <&keysn_9>; + unifykey-index-10= <&keysn_10>; + unifykey-index-11= <&keysn_11>; + unifykey-index-12= <&keysn_12>; + unifykey-index-13= <&keysn_13>; + + keysn_0: key_0{ + key-name = "usid"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_1:key_1{ + key-name = "mac"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_2:key_2{ + key-name = "hdcp"; + key-device = "secure"; + key-type = "sha1"; + key-permit = "read","write","del"; + }; + keysn_3:key_3{ + key-name = "secure_boot_set"; + key-device = "efuse"; + key-permit = "write"; + }; + keysn_4:key_4{ + key-name = "mac_bt"; + key-device = "normal"; + key-permit = "read","write","del"; + key-type = "mac"; + }; + keysn_5:key_5{ + key-name = "mac_wifi"; + key-device = "normal"; + key-permit = "read","write","del"; + key-type = "mac"; + }; + keysn_6:key_6{ + key-name = "hdcp2_tx"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_7:key_7{ + key-name = "hdcp2_rx"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_8:key_8{ + key-name = "widevinekeybox"; + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_9:key_9{ + key-name = "deviceid"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_10:key_10{ + key-name = "hdcp22_fw_private"; + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_11:key_11{ + key-name = "PlayReadykeybox25"; + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_12:key_12{ + key-name = "prpubkeybox";// PlayReady + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_13:key_13{ + key-name = "prprivkeybox";// PlayReady + key-device = "secure"; + key-permit = "read","write","del"; + }; + };//End unifykey + + amlvecm { + compatible = "amlogic, vecm"; + dev_name = "aml_vecm"; + status = "okay"; + gamma_en = <0>;/*1:enabel ;0:disable*/ + wb_en = <0>;/*1:enabel ;0:disable*/ + cm_en = <0>;/*1:enabel ;0:disable*/ + }; + amdolby_vision { + compatible = "amlogic, dolby_vision_g12a"; + dev_name = "aml_amdolby_vision_driver"; + status = "okay"; + tv_mode = <0>;/*1:enabel ;0:disable*/ + }; + + /* Audio Related start */ + pdm_codec:dummy{ + #sound-dai-cells = <0>; + compatible = "amlogic, pdm_dummy_codec"; + status = "okay"; + }; + dummy_codec:dummy{ + #sound-dai-cells = <0>; + compatible = "amlogic, aml_dummy_codec"; + status = "okay"; + }; + amlogic_codec:t9015{ + #sound-dai-cells = <0>; + compatible = "amlogic, aml_codec_T9015"; + reg = <0xFF632000 0x2000>; + is_auge_used = <1>; /* meson or auge chipset used */ + tdmout_index = <1>; + status = "okay"; + }; + audio_effect:eqdrc{ + /*eq_enable = <1>;*/ + /*drc_enable = <1>;*/ + /* + * 0:tdmout_a + * 1:tdmout_b + * 2:tdmout_c + * 3:spdifout + * 4:spdifout_b + */ + eqdrc_module = <1>; + /* max 0xf, each bit for one lane, usually one lane */ + lane_mask = <0x1>; + /* max 0xff, each bit for one channel */ + channel_mask = <0x3>; + }; + auge_sound { + compatible = "amlogic, g12a-sound-card"; + aml-audio-card,name = "AML-AUGESOUND"; + + //aml-audio-card,loopback = <&aml_loopback>; + //aml-audio-card,aux-devs = <&amlogic_codec>; + /*avout mute gpio*/ + avout_mute-gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_HIGH>; + /*for audio effect ,eqdrc */ + aml-audio-card,effect = <&audio_effect>; + + aml-audio-card,dai-link@0 { + format = "dsp_a"; + mclk-fs = <512>; + //continuous-clock; + //bitclock-inversion; + //frame-inversion; + //bitclock-master = <&tdmacodec>; + //frame-master = <&tdmacodec>; + /* suffix-name, sync with android audio hal + * what's the dai link used for + */ + suffix-name = "alsaPORT-pcm"; + tdmacpu: cpu { + sound-dai = <&aml_tdma>; + dai-tdm-slot-tx-mask = + <1 1 1 1 1 1 1 1>; + dai-tdm-slot-rx-mask = + <1 1 1 1 1 1 1 1>; + dai-tdm-slot-num = <8>; + dai-tdm-slot-width = <32>; + system-clock-frequency = <24576000>; + }; + tdmacodec: codec { + sound-dai = <&dummy_codec &dummy_codec>; + }; + }; + + aml-audio-card,dai-link@1 { + format = "i2s"; + mclk-fs = <256>; + //continuous-clock; + //bitclock-inversion; + //frame-inversion; + bitclock-master = <&aml_tdmb>; + frame-master = <&aml_tdmb>; + //bitclock-master = <&tdmbcodec>; + //frame-master = <&tdmbcodec>; + /* suffix-name, sync with android audio hal + * what's the dai link used for + */ + suffix-name = "alsaPORT-i2s"; + cpu { + sound-dai = <&aml_tdmb>; + dai-tdm-slot-tx-mask = <1 1>; + dai-tdm-slot-rx-mask = <1 1>; + dai-tdm-slot-num = <2>; + dai-tdm-slot-width = <32>; + system-clock-frequency = <12288000>; + }; + tdmbcodec: codec { + sound-dai = <&dummy_codec &dummy_codec + &amlogic_codec &ad82584f_62>; + }; + }; + + aml-audio-card,dai-link@2 { + format = "i2s"; + mclk-fs = <256>; + //continuous-clock; + //bitclock-inversion; + //frame-inversion; + bitclock-master = <&aml_tdmc>; + frame-master = <&aml_tdmc>; + /* suffix-name, sync with android audio hal + * what's the dai link used for + */ + //suffix-name = "alsaPORT-tdm"; + cpu { + sound-dai = <&aml_tdmc>; + dai-tdm-slot-tx-mask = <1 1>; + dai-tdm-slot-rx-mask = <1 1>; + dai-tdm-slot-num = <2>; + dai-tdm-slot-width = <32>; + system-clock-frequency = <12288000>; + }; + codec { + sound-dai = <&dummy_codec &dummy_codec>; + }; + }; + + aml-audio-card,dai-link@3 { + mclk-fs = <64>; + /* suffix-name, sync with android audio hal + * what's the dai link used for + */ + suffix-name = "alsaPORT-pdm"; + cpu { + sound-dai = <&aml_pdm>; + }; + codec { + sound-dai = <&pdm_codec>; + }; + }; + + aml-audio-card,dai-link@4 { + mclk-fs = <128>; + /* suffix-name, sync with android audio hal + * what's the dai link used for + */ + suffix-name = "alsaPORT-spdif"; + cpu { + sound-dai = <&aml_spdif>; + system-clock-frequency = <6144000>; + }; + codec { + sound-dai = <&dummy_codec>; + }; + }; + }; + audiolocker: locker { + compatible = "amlogic, audiolocker"; + clocks = <&clkaudio CLKID_AUDIO_LOCKER_OUT + &clkaudio CLKID_AUDIO_LOCKER_IN + &clkaudio CLKID_AUDIO_MCLK_D + &clkaudio CLKID_AUDIO_MCLK_E + &clkc CLKID_MPLL1 + &clkc CLKID_MPLL2>; + clock-names = "lock_out", "lock_in", "out_src", + "in_src", "out_calc", "in_ref"; + interrupts = ; + interrupt-names = "irq"; + frequency = <49000000>; /* pll */ + dividor = <49>; /* locker's parent */ + status = "okay"; + }; + /* Audio Related end */ + + cpu_opp_table0: cpu_opp_table0 { + compatible = "operating-points-v2"; + opp-shared; + + opp00 { + opp-hz = /bits/ 64 <100000000>; + opp-microvolt = <731000>; + }; + opp01 { + opp-hz = /bits/ 64 <250000000>; + opp-microvolt = <731000>; + }; + opp02 { + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <731000>; + }; + opp03 { + opp-hz = /bits/ 64 <667000000>; + opp-microvolt = <731000>; + }; + opp04 { + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <731000>; + }; + opp05 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <731000>; + }; + opp06 { + opp-hz = /bits/ 64 <1398000000>; + opp-microvolt = <761000>; + }; + opp07 { + opp-hz = /bits/ 64 <1512000000>; + opp-microvolt = <791000>; + }; + opp08 { + opp-hz = /bits/ 64 <1608000000>; + opp-microvolt = <831000>; + }; + opp09 { + opp-hz = /bits/ 64 <1704000000>; + opp-microvolt = <861000>; + }; + opp10 { + opp-hz = /bits/ 64 <1896000000>; + opp-microvolt = <981000>; + }; + opp11 { + opp-hz = /bits/ 64 <2016000000>; + opp-microvolt = <1011000>; + }; + opp12 { + opp-hz = /bits/ 64 <2100000000>; + opp-microvolt = <1011000>; + }; + }; + + cpu_opp_table1: cpu_opp_table1 { + compatible = "operating-points-v2"; + opp-shared; + + opp00 { + opp-hz = /bits/ 64 <100000000>; + opp-microvolt = <751000>; + }; + opp01 { + opp-hz = /bits/ 64 <250000000>; + opp-microvolt = <751000>; + }; + opp02 { + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <751000>; + }; + opp03 { + opp-hz = /bits/ 64 <667000000>; + opp-microvolt = <751000>; + }; + opp04 { + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <771000>; + }; + opp05 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <771000>; + }; + opp06 { + opp-hz = /bits/ 64 <1398000000>; + opp-microvolt = <791000>; + }; + opp07 { + opp-hz = /bits/ 64 <1512000000>; + opp-microvolt = <821000>; + }; + opp08 { + opp-hz = /bits/ 64 <1608000000>; + opp-microvolt = <861000>; + }; + opp09 { + opp-hz = /bits/ 64 <1704000000>; + opp-microvolt = <891000>; + }; + opp10 { + opp-hz = /bits/ 64 <1800000000>; + opp-microvolt = <1011000>; + }; + opp11 { + opp-hz = /bits/ 64 <1908000000>; + opp-microvolt = <1011000>; + }; + opp12 { + opp-hz = /bits/ 64 <2016000000>; + opp-microvolt = <1011000>; + }; + }; + + cpufreq-meson { + compatible = "amlogic, cpufreq-meson"; + status = "okay"; + }; + + +}; /* end of / */ + +&meson_fb { + status = "okay"; + display_size_default = <1920 1080 1920 2160 32>; + mem_size = <0x00800000 0x1980000 0x100000 0x100000 0x800000>; + logo_addr = "0x7f800000"; + mem_alloc = <1>; + pxp_mode = <0>; /** 0:normal mode 1:pxp mode */ +}; + +&pwm_ab { + status = "okay"; + }; + +&pwm_ef { + status = "okay"; + }; + +&pwm_AO_cd { + status = "okay"; + }; + +&i2c3 { + status = "okay"; + pinctrl-names="default"; + pinctrl-0=<&i2c3_master_pins2>; + clock-frequency = <100000>; /* default 100k */ + + /* for ref board */ + ad82584f_62: ad82584f_62@62 { + compatible = "ESMT, ad82584f"; + #sound-dai-cells = <0>; + reg = <0x31>; + status = "okay"; + reset_pin = <&gpio GPIOA_5 0>; + }; + + tlv320adc3101_32: tlv320adc3101_32@32 { + compatible = "ti,tlv320adc3101"; + #sound-dai-cells = <0>; + reg = <0x19>; + differential_pair = <1>; + status = "disabled"; + }; +}; + +&audiobus { + aml_tdma: tdma { + compatible = "amlogic, g12a-snd-tdma"; + #sound-dai-cells = <0>; + dai-tdm-lane-slot-mask-in = <0 1>; + dai-tdm-oe-lane-slot-mask-out = <1 0>; + dai-tdm-clk-sel = <0>; + clocks = <&clkaudio CLKID_AUDIO_MCLK_A + &clkc CLKID_MPLL0>; + clock-names = "mclk", "clk_srcpll"; + pinctrl-names = "tdm_pins"; + pinctrl-0 = <&tdmout_a &tdmin_a>; + }; + + aml_tdmb: tdmb { + compatible = "amlogic, g12a-snd-tdmb"; + #sound-dai-cells = <0>; + dai-tdm-lane-slot-mask-in = <0 1 0 0>; + dai-tdm-lane-slot-mask-out = <1 0 0 0>; + dai-tdm-clk-sel = <1>; + clocks = <&clkaudio CLKID_AUDIO_MCLK_B + &clkc CLKID_MPLL1 + &clkc CLKID_MPLL0>; + clock-names = "mclk", "clk_srcpll", "samesource_sysclk"; + pinctrl-names = "tdm_pins"; + pinctrl-0 = <&tdmb_mclk &tdmout_b &tdmin_b>; + /* + * 0: tdmout_a; + * 1: tdmout_b; + * 2: tdmout_c; + * 3: spdifout; + * 4: spdifout_b; + */ + samesource_sel = <3>; + }; + + aml_tdmc: tdmc { + compatible = "amlogic, g12a-snd-tdmc"; + #sound-dai-cells = <0>; + dai-tdm-lane-slot-mask-in = <1 0 0 0>; + #dai-tdm-lane-slot-mask-out = <1 0 1 1>; + #dai-tdm-lane-oe-slot-mask-in = <0 0 0 0>; + #dai-tdm-lane-oe-slot-mask-out = <1 0 0 0>; + dai-tdm-clk-sel = <2>; + clocks = <&clkaudio CLKID_AUDIO_MCLK_C + &clkc CLKID_MPLL2>; + clock-names = "mclk", "clk_srcpll"; + pinctrl-names = "tdm_pins"; + pinctrl-0 = <&tdmc_mclk &tdmout_c &tdmin_c>; + }; + + /* copy a useless tdm to output for hdmi, no pinmux */ + aml_i2s2hdmi: i2s2hdmi { + compatible = "amlogic, g12a-snd-tdmc"; + #sound-dai-cells = <0>; + dai-tdm-lane-slot-mask-out = <1 1 1 1>; + dai-tdm-clk-sel = <2>; + clocks = <&clkaudio CLKID_AUDIO_MCLK_C + &clkc CLKID_MPLL2>; + clock-names = "mclk", "clk_srcpll"; + + i2s2hdmi = <1>; + + status = "okay"; + }; + + aml_spdif: spdif { + compatible = "amlogic, g12a-snd-spdif-a"; + #sound-dai-cells = <0>; + clocks = <&clkc CLKID_MPLL0 + &clkc CLKID_FCLK_DIV4 + &clkaudio CLKID_AUDIO_SPDIFIN + &clkaudio CLKID_AUDIO_SPDIFOUT + &clkaudio CLKID_AUDIO_SPDIFIN_CTRL + &clkaudio CLKID_AUDIO_SPDIFOUT_CTRL>; + clock-names = "sysclk", "fixed_clk", "gate_spdifin", + "gate_spdifout", "clk_spdifin", "clk_spdifout"; + interrupts = + ; + + interrupt-names = "irq_spdifin"; + pinctrl-names = "spdif_pins"; + pinctrl-0 = <&spdifout &spdifin>; + status = "okay"; + }; + aml_spdif_b: spdif_b { + compatible = "amlogic, g12a-snd-spdif-b"; + #sound-dai-cells = <0>; + clocks = <&clkc CLKID_MPLL0 /*CLKID_HIFI_PLL*/ + &clkaudio CLKID_AUDIO_SPDIFOUTB + &clkaudio CLKID_AUDIO_SPDIFOUTB_CTRL>; + clock-names = "sysclk", + "gate_spdifout", "clk_spdifout"; + status = "disabled"; + }; + aml_pdm: pdm { + compatible = "amlogic, g12a-snd-pdm"; + #sound-dai-cells = <0>; + clocks = <&clkaudio CLKID_AUDIO_PDM + &clkc CLKID_FCLK_DIV3 + &clkc CLKID_MPLL3 + &clkaudio CLKID_AUDIO_PDMIN0 + &clkaudio CLKID_AUDIO_PDMIN1>; + clock-names = "gate", + "sysclk_srcpll", + "dclk_srcpll", + "pdm_dclk", + "pdm_sysclk"; + pinctrl-names = "pdm_pins"; + pinctrl-0 = <&pdmin>; + filter_mode = <1>; /* mode 0~4, defalut:1 */ + status = "okay"; + }; + aml_loopback: loopback { + compatible = "amlogic, snd-loopback"; + /* + * 0: out rate = in data rate; + * 1: out rate = loopback data rate; + */ + lb_mode = <0>; + + /* datain src + * 0: tdmin_a; + * 1: tdmin_b; + * 2: tdmin_c; + * 3: spdifin; + * 4: pdmin; + */ + datain_src = <4>; + datain_chnum = <8>; + datain_chmask = <0x3f>; + + /* tdmin_lb src + * 0: tdmoutA + * 1: tdmoutB + * 2: tdmoutC + * 3: PAD_tdminA + * 4: PAD_tdminB + * 5: PAD_tdminC + */ + datalb_src = <2>; + datalb_chnum = <8>; + datalb_chmask = <0x3>; + + status = "disabled"; + }; + + audioresample: resample { + compatible = "amlogic, g12a-resample"; + clocks = <&clkc CLKID_MPLL3 + &clkaudio CLKID_AUDIO_MCLK_F + &clkaudio CLKID_AUDIO_RESAMPLE_CTRL>; + clock-names = "resample_pll", "resample_src", "resample_clk"; + /*same with toddr_src + * TDMIN_A, 0 + * TDMIN_B, 1 + * TDMIN_C, 2 + * SPDIFIN, 3 + * PDMIN, 4 + * NONE, + * TDMIN_LB, 6 + * LOOPBACK, 7 + */ + resample_module = <4>; + status = "disabled"; + }; + aml_pwrdet: pwrdet { + compatible = "amlogic, g12a-power-detect"; + + interrupts = ; + interrupt-names = "pwrdet_irq"; + + /* pwrdet source sel + * 7: loopback; + * 6: tdmin_lb; + * 5: reserved; + * 4: pdmin; + * 3: spdifin; + * 2: tdmin_c; + * 1: tdmin_b; + * 0: tdmin_a; + */ + pwrdet_src = <4>; + + hi_th = <0x70000>; + lo_th = <0x16000>; + + status = "disabled"; + }; +}; /* end of audiobus */ + +&pinctrl_periphs { + tdmout_a: tdmout_a { + mux { /* GPIOX_11, GPIOX_10, GPIOX_9 */ + groups = "tdma_sclk", + "tdma_fs", + "tdma_dout0"; + function = "tdma_out"; + }; + }; + + tdmin_a: tdmin_a { + mux { /* GPIOX_8 */ + groups = "tdma_din1"; + function = "tdma_in"; + }; + }; + + tdmb_mclk: tdmb_mclk { + mux { + groups = "mclk0_a"; + function = "mclk0"; + drive-strength = <2>; + }; + }; + tdmout_b: tdmout_b { + mux { /* GPIOA_1, GPIOA_2, GPIOA_3 */ + groups = "tdmb_sclk", + "tdmb_fs", + "tdmb_dout0"; + function = "tdmb_out"; + drive-strength = <2>; + }; + }; + + tdmin_b:tdmin_b { + mux { /* GPIOA_4 */ + groups = "tdmb_din1" + /*,"tdmb_slv_sclk", "tdmb_slv_fs"*/; + function = "tdmb_in"; + drive-strength = <2>; + }; + }; + + tdmc_mclk: tdmc_mclk { + mux { /* GPIOA_11 */ + groups = "mclk1_a"; + function = "mclk1"; + }; + }; + + tdmout_c:tdmout_c { + mux { /* GPIOA_12, GPIOA_13, GPIOA_8, GPIOA_7*/ + groups = "tdmc_sclk_a", + "tdmc_fs_a", + "tdmc_dout0_a" + /*, "tdmc_dout2", + * "tdmc_dout3" + */; + function = "tdmc_out"; + }; + }; + + tdmin_c:tdmin_c { + mux { /* GPIOA_10 */ + groups = "tdmc_din0_a"; + function = "tdmc_in"; + }; + }; + + spdifin: spdifin { + mux {/* GPIOH_5 */ + groups = "spdif_in_h"; + function = "spdif_in"; + }; + }; + + /* GPIOH_4 */ + /* + * spdifout: spdifout { + * mux { + * groups = "spdif_out_h"; + * function = "spdif_out"; + * }; + *}; + */ + + pdmin: pdmin { + mux { /* gpioa_5, gpioa_6, gpioa_7, gpioa_8, gpioa_9*/ + groups = "pdm_din0_a", + /*"pdm_din1_a",*/ + "pdm_din2_a", + /*"pdm_din3_a",*/ + "pdm_dclk_a"; + function = "pdm"; + }; + }; + + bl_pwm_off_pins:bl_pwm_off_pin { + mux { + pins = "GPIOH_5"; + function = "gpio_periphs"; + output-high; + }; + }; + +}; /* end of pinctrl_periphs */ + +&pinctrl_aobus { + spdifout: spdifout { + mux { /* gpiao_10 */ + groups = "spdif_out_ao"; + function = "spdif_out_ao"; + }; + }; +}; /* end of pinctrl_aobus */ + +&irblaster { + status = "disabled"; +}; + +&audio_data { + status = "okay"; +}; + +/*if you want to use vdin just modify status to "ok"*/ +&vdin0 { + memory-region = <&vdin0_cma_reserved>; + status = "okay"; + /*vdin write mem color depth support: + *bit0:support 8bit + *bit1:support 9bit + *bit2:support 10bit + *bit3:support 12bit + *bit4:support yuv422 10bit full pack mode (from txl new add) + */ + tv_bit_mode = <0x15>; +}; +&vdin1 { + memory-region = <&vdin1_cma_reserved>; + status = "okay"; + /*vdin write mem color depth support: + *bit0:support 8bit + *bit1:support 9bit + *bit2:support 10bit + *bit3:support 12bit + */ + tv_bit_mode = <1>; +}; + +&sd_emmc_c { + status = "okay"; + emmc { + caps = "MMC_CAP_8_BIT_DATA", + "MMC_CAP_MMC_HIGHSPEED", + "MMC_CAP_SD_HIGHSPEED", + "MMC_CAP_NONREMOVABLE", + /* "MMC_CAP_1_8V_DDR", */ + "MMC_CAP_HW_RESET", + "MMC_CAP_ERASE", + "MMC_CAP_CMD23"; + caps2 = "MMC_CAP2_HS200"; + /* "MMC_CAP2_HS400";*/ + f_min = <400000>; + f_max = <200000000>; + }; +}; + +&sd_emmc_b { + status = "okay"; + sd { + caps = "MMC_CAP_4_BIT_DATA", + "MMC_CAP_MMC_HIGHSPEED", + "MMC_CAP_SD_HIGHSPEED"; + f_min = <400000>; + f_max = <50000000>; + }; +}; + +&sd_emmc_a { + status = "okay"; + sdio { + caps = "MMC_CAP_4_BIT_DATA", + "MMC_CAP_MMC_HIGHSPEED", + "MMC_CAP_SD_HIGHSPEED", + "MMC_CAP_NONREMOVABLE", + "MMC_CAP_UHS_SDR12", + "MMC_CAP_UHS_SDR25", + "MMC_CAP_UHS_SDR50", + "MMC_CAP_UHS_SDR104", + "MMC_PM_KEEP_POWER", + "MMC_CAP_SDIO_IRQ"; + f_min = <400000>; + f_max = <200000000>; + }; +}; + +&nand { + status = "disabled"; + plat-names = "bootloader","nandnormal"; + plat-num = <2>; + plat-part-0 = <&bootloader>; + plat-part-1 = <&nandnormal>; + bootloader: bootloader{ + enable_pad ="ce0"; + busy_pad = "rb0"; + timming_mode = "mode5"; + bch_mode = "bch8_1k"; + t_rea = <20>; + t_rhoh = <15>; + chip_num = <1>; + part_num = <0>; + rb_detect = <1>; + }; + nandnormal: nandnormal{ + enable_pad ="ce0"; + busy_pad = "rb0"; + timming_mode = "mode5"; + bch_mode = "bch8_1k"; + plane_mode = "twoplane"; + t_rea = <20>; + t_rhoh = <15>; + chip_num = <2>; + part_num = <3>; + partition = <&nand_partitions>; + rb_detect = <1>; + }; + nand_partitions:nand_partition{ + /* + * if bl_mode is 1, tpl size was generate by + * fip_copies * fip_size which + * will not skip bad when calculating + * the partition size; + * + * if bl_mode is 0, + * tpl partition must be comment out. + */ + tpl{ + offset=<0x0 0x0>; + size=<0x0 0x0>; + }; + logo{ + offset=<0x0 0x0>; + size=<0x0 0x200000>; + }; + recovery{ + offset=<0x0 0x0>; + size=<0x0 0x1000000>; + }; + boot{ + offset=<0x0 0x0>; + size=<0x0 0x1000000>; + }; + system{ + offset=<0x0 0x0>; + size=<0x0 0x4000000>; + }; + data{ + offset=<0xffffffff 0xffffffff>; + size=<0x0 0x0>; + }; + }; +}; +&dwc3 { + status = "okay"; +}; + +&usb2_phy_v2 { + status = "okay"; + portnum = <2>; +}; + +&usb3_phy_v2 { + status = "okay"; + portnum = <0>; + otg = <1>; + gpio-vbus-power = "GPIOH_6"; + gpios = <&gpio GPIOH_6 GPIO_ACTIVE_HIGH>; +}; + +&dwc2_a { + status = "okay"; + /** 0: normal, 1: otg+dwc3 host only, 2: otg+dwc3 device only*/ + controller-type = <3>; +}; +ðmac { + status = "okay"; + pinctrl-names = "internal_eth_pins"; + pinctrl-0 = <&internal_eth_pins>; + mc_val = <0x4be04>; + + internal_phy=<1>; +}; + +&uart_A { + status = "okay"; +}; + +&pcie_A { + reset-gpio = <&gpio GPIOX_7 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&saradc { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/amlogic/g12b_pxp.dts b/arch/arm/boot/dts/amlogic/g12b_pxp.dts new file mode 100644 index 000000000000..e3c62014853e --- /dev/null +++ b/arch/arm/boot/dts/amlogic/g12b_pxp.dts @@ -0,0 +1,736 @@ +/* + * arch/arm/boot/dts/amlogic/g12b_pxp.dts + * + * Copyright (C) 2017 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +/dts-v1/; + +#include "mesong12b.dtsi" + +/ { + model = "Amlogic"; + compatible = "amlogic, g12b"; + interrupt-parent = <&gic>; + #address-cells = <1>; + #size-cells = <1>; + + aliases { + serial0 = &uart_AO; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c_AO; + }; + + memory@00000000 { + device_type = "memory"; + linux,usable-memory = <0x100000 0x3ff00000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + /* global autoconfigured region for contiguous allocations */ + secmon_reserved:linux,secmon { + compatible = "shared-dma-pool"; + reusable; + size = <0x400000>; + alignment = <0x400000>; + alloc-ranges = <0x05000000 0x400000>; + }; + + secos_reserved:linux,secos { + status = "disable"; + compatible = "amlogic, aml_secos_memory"; + reg = <0x05300000 0x2000000>; + no-map; + }; + logo_reserved:linux,meson-fb { + compatible = "shared-dma-pool"; + reusable; + size = <0x800000>; + alignment = <0x400000>; + alloc-ranges = <0x3f800000 0x800000>; + }; + ion_cma_reserved:linux,ion-dev { + compatible = "shared-dma-pool"; + reusable; + size = <0x8000000>; + alignment = <0x400000>; + }; + + //di_reserved:linux,di { + //compatible = "amlogic, di-mem"; + /* buffer_size = 3621952(yuv422 8bit) */ + /* 4179008(yuv422 10bit full pack mode) */ + /** 10x3621952=34.6M(0x23) support 8bit **/ + /** 10x4736064=45.2M(0x2e) support 12bit **/ + /** 10x4179008=40M(0x28) support 10bit **/ + //size = <0x2800000>; + //no-map; + //}; + /*di CMA pool */ + di_cma_reserved:linux,di_cma { + compatible = "shared-dma-pool"; + reusable; + /* buffer_size = 3621952(yuv422 8bit) + * | 4736064(yuv422 10bit) + * | 4074560(yuv422 10bit full pack mode) + * 10x3621952=34.6M(0x23) support 8bit + * 10x4736064=45.2M(0x2e) support 12bit + * 10x4074560=40M(0x28) support 10bit + */ + size = <0x02800000>; + alignment = <0x400000>; + }; + codec_mm_cma:linux,codec_mm_cma { + compatible = "shared-dma-pool"; + reusable; + /* ion_codec_mm max can alloc size 80M*/ + size = <0xd000000>; + alignment = <0x400000>; + linux,contiguous-region; + alloc-ranges = <0x0 0x30000000>; + }; + /* codec shared reserved */ + codec_mm_reserved:linux,codec_mm_reserved { + compatible = "amlogic, codec-mm-reserved"; + size = <0x0>; + alignment = <0x100000>; + //no-map; + }; + /* vdin0 CMA pool */ + vdin0_cma_reserved:linux,vdin0_cma { + compatible = "shared-dma-pool"; + reusable; + /* 1920x1080x2x4 =16+4 M */ + size = <0x04000000>; + alignment = <0x400000>; + }; + /* vdin1 CMA pool */ + vdin1_cma_reserved:linux,vdin1_cma { + compatible = "shared-dma-pool"; + reusable; + /* 1920x1080x2x4 =16 M */ + size = <0x04000000>; + alignment = <0x400000>; + }; + }; + + cvbsout { + compatible = "amlogic, cvbsout-g12b"; + dev_name = "cvbsout"; + status = "okay"; + clocks = <&clkc CLKID_VCLK2_ENCI + &clkc CLKID_VCLK2_VENCI0 + &clkc CLKID_VCLK2_VENCI1 + &clkc CLKID_DAC_CLK>; + clock-names = "venci_top_gate", + "venci_0_gate", + "venci_1_gate", + "vdac_clk_gate"; + clk_path = <0>; + + /* performance: reg_address, reg_value */ + /* g12b */ + performance = <0x1bf0 0x9 + 0x1b56 0x333 + 0x1b12 0x8080 + 0x1b05 0xfd + 0x1c59 0xf850 + 0xffff 0x0>; /* ending flag */ + performance_sarft = <0x1bf0 0x9 + 0x1b56 0x333 + 0x1b12 0x0 + 0x1b05 0x9 + 0x1c59 0xfc48 + 0xffff 0x0>; /* ending flag */ + }; + + codec_mm { + compatible = "amlogic, codec, mm"; + memory-region = <&codec_mm_cma &codec_mm_reserved>; + dev_name = "codec_mm"; + status = "okay"; + }; + + deinterlace { + compatible = "amlogic, deinterlace"; + status = "disabled"; + /* 0:use reserved; 1:use cma; 2:use cma as reserved */ + flag_cma = <1>; + //memory-region = <&di_reserved>; + memory-region = <&di_cma_reserved>; + interrupts = <0 46 1 + 0 40 1>; + interrupt-names = "pre_irq", "post_irq"; + clocks = <&clkc CLKID_VPU_CLKB_TMP_COMP>, + <&clkc CLKID_VPU_CLKB_COMP>; + clock-names = "vpu_clkb_tmp_composite", + "vpu_clkb_composite"; + clock-range = <334 667>; + /* buffer-size = <3621952>;(yuv422 8bit) */ + buffer-size = <4074560>;/*yuv422 fullpack*/ + /* reserve-iomap = "true"; */ + /* if enable nr10bit, set nr10bit-support to 1 */ + post-wr-support = <1>; + nr10bit-support = <1>; + nrds-enable = <1>; + pps-enable = <1>; + }; + + amlvecm { + compatible = "amlogic, vecm"; + dev_name = "aml_vecm"; + status = "disabled"; + gamma_en = <0>;/*1:enabel ;0:disable*/ + wb_en = <0>;/*1:enabel ;0:disable*/ + cm_en = <0>;/*1:enabel ;0:disable*/ + }; + amdolby_vision { + compatible = "amlogic, dolby_vision_g12a"; + dev_name = "aml_amdolby_vision_driver"; + status = "disabled"; + tv_mode = <0>;/*1:enabel ;0:disable*/ + }; + + /* Audio Related start */ + pdm_codec:dummy{ + #sound-dai-cells = <0>; + compatible = "amlogic, pdm_dummy_codec"; + status = "disabled"; + }; + dummy_codec:dummy{ + #sound-dai-cells = <0>; + compatible = "amlogic, aml_dummy_codec"; + status = "disabled"; + }; + amlogic_codec:t9015{ + #sound-dai-cells = <0>; + /*compatible = "amlogic, aml_codec_T9015";*/ + reg = <0xFF632000 0x2000>; + is_auge_used = <1>; /* meson or auge chipset used */ + tdmout_index = <0>; + status = "disabled"; + }; + auge_sound { + /*compatible = "amlogic, g12a-sound-card";*/ + aml-audio-card,name = "AML-AUGESOUND"; + + aml-audio-card,dai-link@0 { + format = "dsp_a"; + mclk-fs = <512>; + //continuous-clock; + //bitclock-inversion; + //frame-inversion; + //bitclock-master = <&tdmacodec>; + //frame-master = <&tdmacodec>; + tdmacpu: cpu { + sound-dai = <&aml_tdma>; + dai-tdm-slot-tx-mask = + <1 1 1 1 1 1 1 1>; + dai-tdm-slot-rx-mask = + <1 1 1 1 1 1 1 1>; + dai-tdm-slot-num = <8>; + dai-tdm-slot-width = <32>; + system-clock-frequency = <24576000>; + }; + tdmacodec: codec { + sound-dai = <&dummy_codec &dummy_codec>; + }; + }; + + aml-audio-card,dai-link@1 { + format = "i2s"; + mclk-fs = <256>; + //continuous-clock; + //bitclock-inversion; + //frame-inversion; + bitclock-master = <&aml_tdmb>; + frame-master = <&aml_tdmb>; + cpu { + sound-dai = <&aml_tdmb>; + dai-tdm-slot-tx-mask = <1 1>; + dai-tdm-slot-rx-mask = <1 1>; + dai-tdm-slot-num = <2>; + dai-tdm-slot-width = <32>; + system-clock-frequency = <12288000>; + }; + codec { + sound-dai = <&dummy_codec &dummy_codec>; + }; + }; + + aml-audio-card,dai-link@2 { + format = "i2s"; + mclk-fs = <256>; + continuous-clock; + //bitclock-inversion; + //frame-inversion; + bitclock-master = <&aml_tdmc>; + frame-master = <&aml_tdmc>; + cpu { + sound-dai = <&aml_tdmc>; + dai-tdm-slot-tx-mask = <1 1>; + dai-tdm-slot-rx-mask = <1 1>; + dai-tdm-slot-num = <2>; + dai-tdm-slot-width = <32>; + system-clock-frequency = <12288000>; + }; + codec { + sound-dai = <&dummy_codec &dummy_codec>; + }; + }; + + aml-audio-card,dai-link@3 { + mclk-fs = <64>; + cpu { + sound-dai = <&aml_pdm>; + }; + codec { + sound-dai = <&pdm_codec>; + }; + }; + + aml-audio-card,dai-link@4 { + mclk-fs = <128>; + cpu { + sound-dai = <&aml_spdif>; + system-clock-frequency = <6144000>; + }; + codec { + sound-dai = <&dummy_codec>; + }; + }; + aml-audio-card,dai-link@5 { + mclk-fs = <128>; + cpu { + sound-dai = <&aml_spdif_b>; + system-clock-frequency = <6144000>; + }; + codec { + sound-dai = <&dummy_codec>; + }; + }; + }; + audiolocker: locker { + compatible = "amlogic, audiolocker"; + clocks = <&clkaudio CLKID_AUDIO_LOCKER_OUT + &clkaudio CLKID_AUDIO_LOCKER_IN + &clkaudio CLKID_AUDIO_MCLK_D + &clkaudio CLKID_AUDIO_MCLK_E + &clkc CLKID_MPLL1 + &clkc CLKID_MPLL2>; + clock-names = "lock_out", "lock_in", "out_src", + "in_src", "out_calc", "in_ref"; + interrupts = ; + interrupt-names = "irq"; + frequency = <49000000>; /* pll */ + dividor = <49>; /* locker's parent */ + status = "disabled"; + }; + /* Audio Related end */ + + cpu_opp_table0: cpu_opp_table0 { + compatible = "operating-points-v2"; + opp-shared; + + opp00 { + opp-hz = /bits/ 64 <100000000>; + opp-microvolt = <731000>; + }; + opp01 { + opp-hz = /bits/ 64 <250000000>; + opp-microvolt = <731000>; + }; + opp02 { + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <731000>; + }; + opp03 { + opp-hz = /bits/ 64 <667000000>; + opp-microvolt = <731000>; + }; + opp04 { + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <731000>; + }; + opp05 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <731000>; + }; + opp06 { + opp-hz = /bits/ 64 <1398000000>; + opp-microvolt = <761000>; + }; + opp07 { + opp-hz = /bits/ 64 <1512000000>; + opp-microvolt = <791000>; + }; + opp08 { + opp-hz = /bits/ 64 <1608000000>; + opp-microvolt = <831000>; + }; + opp09 { + opp-hz = /bits/ 64 <1704000000>; + opp-microvolt = <861000>; + }; + opp10 { + opp-hz = /bits/ 64 <1800000000>; + opp-microvolt = <981000>; + }; + }; + + cpu_opp_table1: cpu_opp_table1 { + compatible = "operating-points-v2"; + opp-shared; + + opp00 { + opp-hz = /bits/ 64 <100000000>; + opp-microvolt = <751000>; + }; + opp01 { + opp-hz = /bits/ 64 <250000000>; + opp-microvolt = <751000>; + }; + opp02 { + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <751000>; + }; + opp03 { + opp-hz = /bits/ 64 <667000000>; + opp-microvolt = <751000>; + }; + opp04 { + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <771000>; + }; + opp05 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <771000>; + }; + opp06 { + opp-hz = /bits/ 64 <1398000000>; + opp-microvolt = <791000>; + }; + opp07 { + opp-hz = /bits/ 64 <1512000000>; + opp-microvolt = <821000>; + }; + opp08 { + opp-hz = /bits/ 64 <1608000000>; + opp-microvolt = <861000>; + }; + opp09 { + opp-hz = /bits/ 64 <1704000000>; + opp-microvolt = <891000>; + }; + }; + + cpufreq-meson { + compatible = "amlogic, cpufreq-meson"; + status = "okay"; + }; + + +}; /* end of / */ + +&meson_fb { + status = "okay"; + display_size_default = <1920 1080 1920 2160 32>; + mem_size = <0x00800000 0x1980000 0x100000 0x100000 0x800000>; + logo_addr = "0x3f800000"; + mem_alloc = <1>; + pxp_mode = <1>; /** 0:normal mode 1:pxp mode */ +}; + +&pwm_AO_cd { + status = "okay"; +}; + +&pwm_ab { + status = "okay"; +}; + + +&audiobus { + aml_tdma: tdma { + /*compatible = "amlogic, g12a-snd-tdma";*/ + #sound-dai-cells = <0>; + dai-tdm-lane-slot-mask-in = <1 0>; + dai-tdm-lane-slot-mask-out = <0 1>; + dai-tdm-clk-sel = <0>; + clocks = <&clkaudio CLKID_AUDIO_MCLK_A + &clkc CLKID_MPLL0>; + clock-names = "mclk", "clk_srcpll"; + pinctrl-names = "tdm_pins"; + pinctrl-0 = <&tdmout_a &tdmin_a>; + }; + + aml_tdmb: tdmb { + /*compatible = "amlogic, g12a-snd-tdmb";*/ + #sound-dai-cells = <0>; + dai-tdm-lane-slot-mask-in = <1 1 1 1>; + dai-tdm-clk-sel = <1>; + clocks = <&clkaudio CLKID_AUDIO_MCLK_B + &clkc CLKID_MPLL1>; + clock-names = "mclk", "clk_srcpll"; + pinctrl-names = "tdm_pins"; + pinctrl-0 = <&tdmb_mclk /*&tdmout_b &tdmin_b*/>; + }; + + aml_tdmc: tdmc { + /*compatible = "amlogic, g12a-snd-tdmc";*/ + #sound-dai-cells = <0>; + dai-tdm-lane-slot-mask-in = <0 1 0 0>; + #dai-tdm-lane-slot-mask-out = <1 0 1 1>; + #dai-tdm-lane-oe-slot-mask-in = <0 0 0 0>; + dai-tdm-lane-oe-slot-mask-out = <1 0 0 0>; + dai-tdm-clk-sel = <2>; + clocks = <&clkaudio CLKID_AUDIO_MCLK_C + &clkc CLKID_MPLL2>; + clock-names = "mclk", "clk_srcpll"; + pinctrl-names = "tdm_pins"; + pinctrl-0 = <&tdmc_mclk &tdmout_c &tdmin_c>; + }; + + aml_spdif: spdif { + /*compatible = "amlogic, g12a-snd-spdif-a";*/ + #sound-dai-cells = <0>; + clocks = <&clkc CLKID_MPLL0 + &clkc CLKID_FCLK_DIV4 + &clkaudio CLKID_AUDIO_SPDIFIN + &clkaudio CLKID_AUDIO_SPDIFOUT + &clkaudio CLKID_AUDIO_SPDIFIN_CTRL + &clkaudio CLKID_AUDIO_SPDIFOUT_CTRL>; + clock-names = "sysclk", "fixed_clk", "gate_spdifin", + "gate_spdifout", "clk_spdifin", "clk_spdifout"; + interrupts = + ; + + interrupt-names = "irq_spdifin"; + pinctrl-names = "spdif_pins"; + pinctrl-0 = <&spdifout &spdifin>; + status = "disabled"; + }; + aml_spdif_b: spdif_b { + /*compatible = "amlogic, g12a-snd-spdif-b";*/ + #sound-dai-cells = <0>; + clocks = <&clkc CLKID_MPLL0 /*CLKID_HIFI_PLL*/ + &clkaudio CLKID_AUDIO_SPDIFOUTB + &clkaudio CLKID_AUDIO_SPDIFOUTB_CTRL>; + clock-names = "sysclk", + "gate_spdifout", "clk_spdifout"; + pinctrl-names = "spdif_pins"; + pinctrl-0 = <&spdifout_b>; + status = "disabled"; + }; + aml_pdm: pdm { + /*compatible = "amlogic, g12a-snd-pdm";*/ + #sound-dai-cells = <0>; + clocks = <&clkaudio CLKID_AUDIO_PDM + &clkc CLKID_FCLK_DIV3 + &clkc CLKID_MPLL3 + &clkaudio CLKID_AUDIO_PDMIN0 + &clkaudio CLKID_AUDIO_PDMIN1>; + clock-names = "gate", + "sysclk_srcpll", + "dclk_srcpll", + "pdm_dclk", + "pdm_sysclk"; + pinctrl-names = "pdm_pins"; + pinctrl-0 = <&pdmin>; + filter_mode = <1>; /* mode 0~4, defalut:1 */ + status = "disabled"; + }; + aml_pwrdet: pwrdet { + compatible = "amlogic, g12a-power-detect"; + + interrupts = ; + interrupt-names = "pwrdet_irq"; + + /* pwrdet source sel + * 7: loopback; + * 6: tdmin_lb; + * 5: reserved; + * 4: pdmin; + * 3: spdifin; + * 2: tdmin_c; + * 1: tdmin_b; + * 0: tdmin_a; + */ + pwrdet_src = <4>; + + hi_th = <0x70000>; + lo_th = <0x16000>; + + status = "disabled"; + }; +}; /* end of audiobus */ + +&pinctrl_periphs { + tdmout_a: tdmout_a { + mux { /* GPIOX_11, GPIOX_10, GPIOX_8 */ + groups = "tdma_sclk", + "tdma_fs", + "tdma_dout1"; + function = "tdma_out"; + }; + }; + + tdmin_a: tdmin_a { + mux { /* GPIOX_9 */ + groups = "tdma_din0"; + function = "tdma_in"; + }; + }; + + tdmb_mclk: tdmb_mclk { + mux { + groups = "mclk0_a"; + function = "mclk0"; + }; + }; + + tdmc_mclk: tdmc_mclk { + mux { /* GPIOZ_8 */ + groups = "mclk1_z"; + function = "mclk1"; + }; + }; + + tdmout_c:tdmout_c { + mux { /* gpioz_7, gpioz_6, GPIOZ_2, GPIOZ_4, GPIOZ_5*/ + groups = "tdmc_sclk_z", + "tdmc_fs_z", + "tdmc_dout0_z" + /*,"tdmc_dout2_z", + *"tdmc_dout3_z" + */; + function = "tdmc_out"; + }; + }; + + tdmin_c:tdmin_c { + mux { /* GPIOZ_3 */ + groups = "tdmc_din1_z"; + function = "tdmc_in"; + }; + }; + + spdifin: spdifin { + mux {/* gpioa_10 */ + groups = "spdif_in_a10"; + function = "spdif_in"; + }; + }; + + spdifout: spdifout { + mux {/* gpioa_11 */ + groups = "spdif_out_a11"; + function = "spdif_out"; + }; + }; + + spdifout_b: spdifout_b { + mux { /* gpioa_13 */ + groups = "spdif_out_a13"; + function = "spdif_out"; + }; + }; + + pdmin: pdmin { + mux { /* gpioa_5, gpioa_6, gpioa_7, gpioa_8, gpioa_9*/ + groups = "pdm_din0_a", + "pdm_din1_a", + "pdm_din2_a", + "pdm_din3_a", + "pdm_dclk_a"; + function = "pdm"; + }; + }; + +}; /* end of pinctrl_periphs */ + +&pinctrl_aobus { + tdmout_b: tdmout_b { + mux { /* GPIOAO_7, GPIOAO_8, GPIOAO_4 */ + groups = "tdmb_fs_ao", + "tdmb_fs_ao", + "tdmb_dout0_ao"; + function = "tdmb_out_ao"; + }; + }; + + tdmin_b:tdmin_b { + mux { + groups = "tdmb_din2_ao"; + function = "tdmb_in_ao"; + }; + }; +}; /* end of pinctrl_aobus */ +/* Audio Related End */ + +&aobus{ + +}; + +&irblaster { + status = "disabled"; +}; + +/*if you want to use vdin just modify status to "ok"*/ +&vdin0 { + memory-region = <&vdin0_cma_reserved>; + status = "disabled"; + /*vdin write mem color depth support: + *bit0:support 8bit + *bit1:support 9bit + *bit2:support 10bit + *bit3:support 12bit + *bit4:support yuv422 10bit full pack mode (from txl new add) + */ + tv_bit_mode = <0x15>; +}; +&vdin1 { + memory-region = <&vdin1_cma_reserved>; + status = "disabled"; + /*vdin write mem color depth support: + *bit0:support 8bit + *bit1:support 9bit + *bit2:support 10bit + *bit3:support 12bit + */ + tv_bit_mode = <1>; +}; +&sd_emmc_b { + status = "disabled"; + sd { + caps = "MMC_CAP_4_BIT_DATA", + "MMC_CAP_MMC_HIGHSPEED", + "MMC_CAP_SD_HIGHSPEED", + "MMC_CAP_NONREMOVABLE", + "MMC_CAP_UHS_SDR12", + "MMC_CAP_UHS_SDR25", + "MMC_CAP_UHS_SDR50", + "MMC_PM_KEEP_POWER", + "MMC_CAP_NONREMOVABLE"; /**ptm debug */ + f_min = <400000>; + f_max = <200000000>; + }; +}; + diff --git a/arch/arm/boot/dts/amlogic/gxl_p212_1g.dts b/arch/arm/boot/dts/amlogic/gxl_p212_1g.dts index 3a35ca9e16e3..6712e7731504 100644 --- a/arch/arm/boot/dts/amlogic/gxl_p212_1g.dts +++ b/arch/arm/boot/dts/amlogic/gxl_p212_1g.dts @@ -70,6 +70,16 @@ alignment = <0x400000>; alloc-ranges = <0x3f800000 0x800000>; }; + + codec_mm_cma:linux,codec_mm_cma { + compatible = "shared-dma-pool"; + reusable; + /* ion_codec_mm max can alloc size 80M*/ + size = <0xd000000>; + alignment = <0x400000>; + linux,contiguous-region; + alloc-ranges = <0x30000000 0x10000000>; + }; //don't put other dts in front of logo_reserved //di_reserved:linux,di { @@ -84,13 +94,14 @@ /** 10x3133440=30M(0x1e) support 8bit **/ size = <0x2000000>; alignment = <0x400000>; + alloc-ranges = <0x30000000 0x10000000>; }; ion_reserved:linux,ion-dev { compatible = "shared-dma-pool"; reusable; size = <0x4C00000>; alignment = <0x400000>; - alloc-ranges = <0x0 0x2ee00000>; + alloc-ranges = <0x0 0x30000000>; }; /* vdin0 CMA pool */ @@ -109,6 +120,7 @@ /* 1920x1080x2x4 =16 M */ size = <0x01000000>; alignment = <0x400000>; + alloc-ranges = <0x0 0x30000000>; }; /* POST PROCESS MANAGER */ ppmgr_reserved:linux,ppmgr { @@ -116,15 +128,6 @@ size = <0x0>; }; - codec_mm_cma:linux,codec_mm_cma { - compatible = "shared-dma-pool"; - reusable; - /* ion_codec_mm max can alloc size 80M*/ - size = <0xd000000>; - alignment = <0x400000>; - linux,contiguous-region; - alloc-ranges = <0x12000000 0x13400000>; - }; picdec_cma_reserved:linux,picdec { compatible = "shared-dma-pool"; reusable; @@ -141,14 +144,14 @@ }; }; - dummy-battery { + amlogic_battery:dummy-battery { compatible = "amlogic, dummy-battery"; - status = "okay"; + status = "disabled"; }; - dummy-charger { + amlogic_charger:dummy-charger { compatible = "amlogic, dummy-charger"; - status = "okay"; + status = "disabled"; }; bt-dev{ @@ -1222,3 +1225,4 @@ delay_control = <0x15>; ssctl = <0>; }; + diff --git a/arch/arm/boot/dts/amlogic/gxl_p212_1g_buildroot.dts b/arch/arm/boot/dts/amlogic/gxl_p212_1g_buildroot.dts new file mode 100644 index 000000000000..2105b028b50a --- /dev/null +++ b/arch/arm/boot/dts/amlogic/gxl_p212_1g_buildroot.dts @@ -0,0 +1,1264 @@ +/* + * arch/arm/boot/dts/amlogic/gxl_p212_1g.dts + * + * Copyright (C) 2017 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +/dts-v1/; + +#include "mesongxl.dtsi" +#include "meson_drm.dtsi" +#include "mesongxl_p212-panel.dtsi" +/ { + model = "Amlogic"; + amlogic-dt-id = "gxl_p212_1g"; + compatible = "amlogic, Gxl"; + interrupt-parent = <&gic>; + #address-cells = <1>; + #size-cells = <1>; + + aliases { + serial0 = &uart_AO; + serial1 = &uart_A; + serial2 = &uart_B; + serial3 = &uart_C; + serial4 = &uart_AO_B; + }; + ion_dev { + compatible = "amlogic, ion_dev"; + }; + memory@00000000 { + device_type = "memory"; + linux,usable-memory = <0x0100000 0x3ff00000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + /* global autoconfigured region for contiguous allocations */ + secmon_reserved:linux,secmon { + compatible = "shared-dma-pool"; + reusable; + size = <0x400000>; + alignment = <0x400000>; + alloc-ranges = <0x05000000 0x400000>; + }; + secos_reserved:linux,secos { + status = "disable"; + compatible = "amlogic, aml_secos_memory"; + reg = <0x05300000 0x2000000>; + no-map; + }; + fb_reserved:linux,meson-fb { + compatible = "shared-dma-pool"; + reusable; + size = <0x2400000>; + alignment = <0x400000>; + alloc-ranges = <0x3dc00000 0x2400000>; + }; + //don't put other dts in front of fb_reserved + + //di_reserved:linux,di { + // compatible = "amlogic, di-mem"; + /** 10x3133440=30M(0x1e) support 8bit **/ + // size = <0x1e00000>; + //no-map; + //}; + di_cma_reserved:linux,di_cma { + compatible = "shared-dma-pool"; + reusable; + /** 10x3133440=30M(0x1e) support 8bit **/ + size = <0x2000000>; + alignment = <0x400000>; + }; + /* vdin0 CMA pool */ + //vdin0_cma_reserved:linux,vdin0_cma { + // compatible = "shared-dma-pool"; + // linux,phandle = <4>; + // reusable; + /* 1920x1080x2x4 =16+4 M */ + // size = <0x01400000>; + // alignment = <0x400000>; + //}; + /* vdin1 CMA pool */ + vdin1_cma_reserved:linux,vdin1_cma { + compatible = "shared-dma-pool"; + reusable; + /* 1920x1080x2x4 =16 M */ + size = <0x01000000>; + alignment = <0x400000>; + alloc-ranges = <0x0 0x30000000>; + }; + /* POST PROCESS MANAGER */ + ppmgr_reserved:linux,ppmgr { + compatible = "shared-dma-pool"; + size = <0x0>; + }; + + codec_mm_cma:linux,codec_mm_cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x10400000>; + alignment = <0x400000>; + linux,contiguous-region; + }; + picdec_cma_reserved:linux,picdec { + compatible = "shared-dma-pool"; + reusable; + size = <0x0>; + alignment = <0x0>; + linux,contiguous-region; + }; + /* codec shared reserved */ + codec_mm_reserved:linux,codec_mm_reserved { + compatible = "amlogic, codec-mm-reserved"; + size = <0x0>; + alignment = <0x100000>; + //no-map; + }; + }; + + bt-dev{ + compatible = "amlogic, bt-dev"; + dev_name = "bt-dev"; + status = "okay"; + gpio_reset = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>; + }; + + wifi{ + compatible = "amlogic, aml_wifi"; + dev_name = "aml_wifi"; + status = "okay"; + interrupt_pin = <&gpio GPIOX_7 GPIO_ACTIVE_HIGH>; + irq_trigger_type = "GPIO_IRQ_LOW"; + power_on_pin = <&gpio GPIOX_6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_32k_pins>; + pwm_config = <&wifi_pwm_conf>; + }; + + wifi_pwm_conf:wifi_pwm_conf{ + pwm_channel1_conf { + pwms = <&pwm_ef MESON_PWM_0 30040 0>; + duty-cycle = <15020>; + times = <8>; + }; + pwm_channel2_conf { + pwms = <&pwm_ef MESON_PWM_2 30030 0>; + duty-cycle = <15015>; + times = <12>; + }; + }; + + sd_emmc_c: emmc@d0074000 { + status = "okay"; + compatible = "amlogic, meson-mmc-gxl"; + reg = <0xd0074000 0x2000>; + interrupts = <0 218 1>; + pinctrl-names = "emmc_clk_cmd_pins", "emmc_all_pins"; + pinctrl-0 = <&emmc_clk_cmd_pins>; + pinctrl-1 = <&emmc_conf_pull_up &emmc_conf_pull_done>; + clocks = <&clkc CLKID_SD_EMMC_C>, + <&clkc CLKID_SD_EMMC_C_P0_COMP>, + <&clkc CLKID_FCLK_DIV2>; + clock-names = "core", "clkin0", "clkin1"; + + bus-width = <8>; + cap-sd-highspeed; + cap-mmc-highspeed; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + + max-frequency = <200000000>; + non-removable; + disable-wp; + emmc { + pinname = "emmc"; + ocr_avail = <0x200080>; /**VDD voltage 3.3 ~ 3.4 */ + caps = "MMC_CAP_8_BIT_DATA", + "MMC_CAP_MMC_HIGHSPEED", + "MMC_CAP_SD_HIGHSPEED", + "MMC_CAP_NONREMOVABLE", + "MMC_CAP_1_8V_DDR", + "MMC_CAP_HW_RESET", + "MMC_CAP_ERASE", + "MMC_CAP_CMD23"; + caps2 = "MMC_CAP2_HS200", "MMC_CAP2_HS400"; + f_min = <400000>; + f_max = <100000000>; + max_req_size = <0x20000>; /**128KB*/ + gpio_dat3 = <&gpio BOOT_3 GPIO_ACTIVE_HIGH>; + hw_reset = <&gpio BOOT_9 GPIO_ACTIVE_HIGH>; + card_type = <1>; + /* 1:mmc card(include eMMC), + * 2:sd card(include tSD) + */ + }; + }; + + sd_emmc_b:sd@d0072000 { + status = "okay"; + compatible = "amlogic, meson-mmc-gxl"; + reg = <0xd0072000 0x2000>; + interrupts = <0 217 1>; + pinctrl-names = "sd_all_pins", + "sd_clk_cmd_pins", + "sd_1bit_pins", + "sd_clk_cmd_uart_pins", + "sd_1bit_uart_pins", + "sd_to_ao_uart_pins", + "ao_to_sd_uart_pins", + "ao_to_sd_jtag_pins", + "sd_to_ao_jtag_pins"; + pinctrl-0 = <&sd_all_pins>; + pinctrl-1 = <&sd_clk_cmd_pins>; + pinctrl-2 = <&sd_1bit_pins>; + pinctrl-3 = <&sd_to_ao_uart_clr_pins + &sd_clk_cmd_pins &ao_to_sd_uart_pins>; + pinctrl-4 = <&sd_to_ao_uart_clr_pins + &sd_1bit_pins &ao_to_sd_uart_pins>; + pinctrl-5 = <&sd_all_pins &sd_to_ao_uart_pins>; + pinctrl-6 = <&sd_to_ao_uart_clr_pins &ao_to_sd_uart_pins>; + pinctrl-7 = <&sd_to_ao_uart_clr_pins &ao_to_sd_uart_pins>; + pinctrl-8 = <&sd_all_pins &sd_to_ao_uart_pins>; + clocks = <&clkc CLKID_SD_EMMC_B>, + <&clkc CLKID_SD_EMMC_B_P0_COMP>, + <&clkc CLKID_FCLK_DIV2>; + clock-names = "core", "clkin0", "clkin1"; + + bus-width = <4>; + cap-sd-highspeed; + max-frequency = <100000000>; + disable-wp; + sd { + pinname = "sd"; + ocr_avail = <0x200080>; /**VDD voltage 3.3 ~ 3.4 */ + caps = "MMC_CAP_4_BIT_DATA", + "MMC_CAP_MMC_HIGHSPEED", + "MMC_CAP_SD_HIGHSPEED"; + /* "MMC_CAP_UHS_SDR12", + * "MMC_CAP_UHS_SDR25", + * "MMC_CAP_UHS_SDR50", + * "MMC_CAP_UHS_SDR104"; + */ + f_min = <400000>; + f_max = <100000000>; + max_req_size = <0x20000>; /**128KB*/ + gpio_dat3 = <&gpio CARD_4 GPIO_ACTIVE_HIGH>; + jtag_pin = <&gpio CARD_0 GPIO_ACTIVE_HIGH>; + gpio_cd = <&gpio CARD_6 GPIO_ACTIVE_HIGH>; + card_type = <5>; + /* 0:unknown, + * 1:mmc card(include eMMC), + * 2:sd card(include tSD), + * 3:sdio device(ie:sdio-wifi), + * 4:SD combo (IO+mem) card, + * 5:NON sdio device(means sd/mmc card), + * other:reserved + */ + }; + }; + + sd_emmc_a:sdio@d0070000 { + status = "okay"; + compatible = "amlogic, meson-mmc-gxl"; + reg = <0xd0070000 0x2000>; + interrupts = <0 216 4>; + pinctrl-names = "sdio_clk_cmd_pins", "sdio_all_pins"; + pinctrl-0 = <&sdio_clk_cmd_pins>; + pinctrl-1 = <&sdio_all_pins>; + clocks = <&clkc CLKID_SD_EMMC_A>, + <&clkc CLKID_SD_EMMC_A_P0_COMP>, + <&clkc CLKID_FCLK_DIV2>; + clock-names = "core", "clkin0", "clkin1"; + + bus-width = <4>; + cap-sd-highspeed; + cap-mmc-highspeed; + max-frequency = <100000000>; + non-removable; + disable-wp; + sdio { + pinname = "sdio"; + ocr_avail = <0x200080>; /**VDD voltage 3.3 ~ 3.4 */ + caps = "MMC_CAP_4_BIT_DATA", + "MMC_CAP_MMC_HIGHSPEED", + "MMC_CAP_SD_HIGHSPEED", + "MMC_CAP_NONREMOVABLE", + "MMC_CAP_UHS_SDR12", + "MMC_CAP_UHS_SDR25", + "MMC_CAP_UHS_SDR50", + "MMC_CAP_UHS_SDR104", + "MMC_PM_KEEP_POWER", + "MMC_CAP_SDIO_IRQ"; + f_min = <400000>; + f_max = <200000000>; + max_req_size = <0x20000>; /**128KB*/ + card_type = <3>; + /* 3:sdio device(ie:sdio-wifi), + * 4:SD combo (IO+mem) card + */ + }; + }; + mtd_nand{ + compatible = "amlogic, aml_mtd_nand"; + dev_name = "mtdnand"; + status = "disabled"; + reg = <0xd0074800 0x200>; + interrupts = < 0 34 1 >; + pinctrl-names = "nand_rb_mod","nand_norb_mod", "nand_cs_only"; + pinctrl-0 = <&all_nand_pins>; + pinctrl-1 = <&all_nand_pins>; + pinctrl-2 = <&nand_cs_pins>; + device_id = <0>; + plat-names = "bootloader","nandnormal"; + plat-num = <2>; + plat-part-0 = <&bootloader>; + plat-part-1 = <&nandnormal>; + bootloader: bootloader{ + enable_pad ="ce0"; + busy_pad = "rb0"; + timming_mode = "mode5"; + bch_mode = "bch60_1k"; + t_rea = <20>; + t_rhoh = <15>; + chip_num = <1>; + part_num = <0>; + rb_detect = <1>; + }; + nandnormal: nandnormal{ + enable_pad ="ce0","ce1"; + busy_pad = "rb0","rb1"; + timming_mode = "mode5"; + bch_mode = "bch60_1k"; + plane_mode = "twoplane"; + t_rea = <20>; + t_rhoh = <15>; + chip_num = <2>; + part_num = <3>; + partition = <&nand_partitions>; + rb_detect = <1>; + }; + nand_partitions:nand_partition{ + logo{ + offset=<0x0 0x0>; + size=<0x0 0x200000>; + }; + recovery{ + offset=<0x0 0x0>; + size=<0x0 0x1000000>; + }; + boot{ + offset=<0x0 0x0>; + size=<0x0 0xC00000>; + }; + system{ + offset=<0x0 0x0>; + size=<0x0 0xDC40000>; + }; + data{ + offset=<0xffffffff 0xffffffff>; + size=<0x0 0x0>; + }; + }; + }; + + ethmac: ethernet@0xc9410000 { + compatible = "amlogic, gxbb-eth-dwmac"; + reg = <0xc9410000 0x10000 + 0xc8834540 0x8 + 0xc8834558 0xc>; + interrupts = <0 8 1>; + pinctrl-names = "external_eth_pins"; + pinctrl-0 = <&external_eth_pins>; + rst_pin-gpios = <&gpio GPIOZ_14 0>; + GPIOZ4_pin-gpios = <&gpio GPIOZ_4 0>; + GPIOZ5_pin-gpios = <&gpio GPIOZ_5 0>; + mc_val_internal_phy = <0x1800>; + mc_val_external_phy = <0x1621>; + cali_val = <0x20000>; + interrupt-names = "macirq"; + clocks = <&clkc CLKID_ETH>; + clock-names = "ethclk81"; + internal_phy=<1>; + }; + + aml_sensor0: aml-sensor@0 { + compatible = "amlogic, aml-thermal"; + device_name = "thermal"; + #thermal-sensor-cells = <1>; + cooling_devices { + cpufreq_cool_cluster0 { + min_state = <1000000>; + dyn_coeff = <140>; + cluster_id = <0>; + node_name = "cpufreq_cool0"; + device_type = "cpufreq"; + }; + cpucore_cool_cluster0 { + min_state = <1>; + dyn_coeff = <0>; + cluster_id = <0>; + node_name = "cpucore_cool0"; + device_type = "cpucore"; + }; + gpufreq_cool { + min_state = <400>; + dyn_coeff = <437>; + cluster_id = <0>; + node_name = "gpufreq_cool0"; + device_type = "gpufreq"; + }; + gpucore_cool { + min_state = <1>; + dyn_coeff = <0>; + cluster_id = <0>; + node_name = "gpucore_cool0"; + device_type = "gpucore"; + }; + }; + cpufreq_cool0:cpufreq_cool0 { + #cooling-cells = <2>; /* min followed by max */ + }; + cpucore_cool0:cpucore_cool0 { + #cooling-cells = <2>; /* min followed by max */ + }; + gpufreq_cool0:gpufreq_cool0 { + #cooling-cells = <2>; /* min followed by max */ + }; + gpucore_cool0:gpucore_cool0 { + #cooling-cells = <2>; /* min followed by max */ + }; + }; + thermal-zones { + soc_thermal { + polling-delay = <1000>; + polling-delay-passive = <100>; + sustainable-power = <2150>; + + thermal-sensors = <&aml_sensor0 3>; + + trips { + switch_on: trip-point@0 { + temperature = <70000>; + hysteresis = <1000>; + type = "passive"; + }; + control: trip-point@1 { + temperature = <80000>; + hysteresis = <1000>; + type = "passive"; + }; + hot: trip-point@2 { + temperature = <85000>; + hysteresis = <5000>; + type = "hot"; + }; + critical: trip-point@3 { + temperature = <260000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + + cooling-maps { + cpufreq_cooling_map { + trip = <&control>; + cooling-device = <&cpufreq_cool0 0 4>; + contribution = <1024>; + }; + cpucore_cooling_map { + trip = <&control>; + cooling-device = <&cpucore_cool0 0 3>; + contribution = <1024>; + }; + gpufreq_cooling_map { + trip = <&control>; + cooling-device = <&gpufreq_cool0 0 4>; + contribution = <1024>; + }; + gpucore_cooling_map { + trip = <&control>; + cooling-device = <&gpucore_cool0 0 2>; + contribution = <1024>; + }; + }; + }; + }; + + dwc3: dwc3@c9000000 { + compatible = "synopsys, dwc3"; + reg = <0xc9000000 0x100000>; + interrupts = <0 30 4>; + usb-phy = <&usb2_phy>, <&usb3_phy>; + cpu-type = "gxl"; + clock-src = "usb3.0"; + }; + + usb2_phy: usb2phy@d0078000 { + compatible = "amlogic, amlogic-new-usb2"; + portnum = <3>; + reg = <0xd0078000 0x80 + 0xc1104408 0x4>; + }; + + usb3_phy: usb3phy@d0078080 { + compatible = "amlogic, amlogic-new-usb3"; + portnum = <0>; + reg = <0xd0078080 0x20>; + }; + + dwc2_a { + compatible = "amlogic, dwc2"; + device_name = "dwc2_a"; + reg = <0xc9100000 0x40000>; + status = "okay"; + interrupts = <0 31 4>; + pl-periph-id = <0>; /** lm name */ + clock-src = "usb0"; /** clock src */ + port-id = <0>; /** ref to mach/usb.h */ + port-type = <2>; /** 0: otg, 1: host, 2: slave */ + port-speed = <0>; /** 0: default, high, 1: full */ + port-config = <0>; /** 0: default */ + port-dma = <0>; /** 0: default ... 6: disable*/ + port-id-mode = <0>; /** 0: hardware, 1: sw_host, 2: sw_slave*/ + usb-fifo = <728>; + cpu-type = "gxl"; + controller-type = <1>; /** 0: normal, 1: host, 2: device*/ + phy-reg = <0xd0078000>; + phy-reg-size = <0xa0>; + clocks = <&clkc CLKID_USB_GENERAL + &clkc CLKID_USB1_TO_DDR + &clkc CLKID_USB1>; + clock-names = "usb_general", + "usb1", + "usb1_to_ddr"; + }; + + meson-amvideom { + compatible = "amlogic, amvideom"; + dev_name = "amvideom"; + status = "okay"; + interrupts = <0 3 1>; + interrupt-names = "vsync"; + }; + + vout { + compatible = "amlogic, vout"; + dev_name = "vout"; + status = "okay"; + fr_auto_policy = <0>; + }; + + cvbsout { + compatible = "amlogic, cvbsout-gxl"; + dev_name = "cvbsout"; + status = "okay"; + clocks = <&clkc CLKID_VCLK2_ENCI + &clkc CLKID_VCLK2_VENCI0 + &clkc CLKID_VCLK2_VENCI1 + &clkc CLKID_DAC_CLK>; + clock-names = "venci_top_gate", + "venci_0_gate", + "venci_1_gate", + "vdac_clk_gate"; + + /* performance: reg_address, reg_value */ + /* s905x */ + performance = <0x1bf0 0x9 + 0x1b56 0x343 + 0x1b12 0x8080 + 0x1b05 0xfd + 0x1c59 0xf752 + 0xffff 0x0>; /* ending flag */ + }; + + amhdmitx: amhdmitx{ + compatible = "amlogic, amhdmitx"; + dev_name = "amhdmitx"; + status = "okay"; + vend-data = <&vend_data>; + pinctrl-names="hdmitx_hpd", "hdmitx_ddc"; + pinctrl-0=<&hdmitx_hpd>; + pinctrl-1=<&hdmitx_ddc>; + /* HPD, 57 + 32 = 89; CEC, 151 + 32 = 183*/ + interrupts = <0 57 1>; + interrupt-names = "hdmitx_hpd"; + /* 0:M8B 1:GXBB 2:GXTVBB 3:GXL 4:GXM + * 5:TXL 6:TXLX 7:AXG 8:GXLX 9:TXHD + */ + ic_type = <3>; + vend_data: vend_data{ /* Should modified by Customer */ + vendor_name = "Amlogic"; /* Max Chars: 8 */ + /* standards.ieee.org/develop/regauth/oui/oui.txt */ + vendor_id = <0x000000>; + product_desc = "MBox Meson Ref"; /* Max Chars: 16 */ + }; + }; + + aocec: aocec{ + compatible = "amlogic, amlogic-aocec"; + device_name = "aocec"; + status = "okay"; + vendor_id = <0x000000>; + cec_osd_string = "MBox"; /* Max Chars: 14 */ + cec_version = <6>; /* 5: 1.4, 6: 2.0 */ + port_num = <1>; + arc_port_mask = <0x0>; + interrupts = <0 199 1>; + interrupt-names = "hdmi_aocec"; + pinctrl-names = "default"; + pinctrl-0=<&hdmitx_aocec>; + reg = <0xc810023c 0x4 + 0xc8100000 0x200>; + reg-names = "ao_exit","ao"; + }; + + sysled { + compatible = "amlogic, sysled"; + dev_name = "sysled"; + status = "disabled"; + led_gpio = <&gpio GPIODV_24 GPIO_ACTIVE_HIGH>; + led_active_low = <1>; + }; + + codec_io { + compatible = "amlogic, codec_io"; + #address-cells=<1>; + #size-cells=<1>; + ranges; + io_cbus_base{ + reg = <0xC1100000 0x100000>; + }; + io_dos_base{ + reg = <0xc8820000 0x10000>; + }; + io_hiubus_base{ + reg = <0xc883c000 0x2000>; + }; + io_aobus_base{ + reg = <0xc8100000 0x100000>; + }; + io_vcbus_base{ + reg = <0xd0100000 0x40000>; + }; + io_dmc_base{ + reg = <0xc8838000 0x400>; + }; + }; + + codec_mm { + compatible = "amlogic, codec, mm"; + memory-region = <&codec_mm_cma &codec_mm_reserved>; + dev_name = "codec_mm"; + status = "okay"; + }; + + canvas{ + compatible = "amlogic, meson, canvas"; + dev_name = "amlogic-canvas"; + status = "ok"; + reg = <0xc8838000 0x400>; + }; + + mesonstream { + compatible = "amlogic, codec, streambuf"; + dev_name = "mesonstream"; + status = "okay"; + clocks = <&clkc CLKID_DOS_PARSER + &clkc CLKID_DEMUX + &clkc CLKID_DOS + &clkc CLKID_CLK81 + &clkc CLKID_VDEC_MUX + &clkc CLKID_HCODEC_MUX + &clkc CLKID_HEVC_MUX>; + clock-names = "parser_top", + "demux", + "vdec", + "clk_81", + "clk_vdec_mux", + "clk_hcodec_mux", + "clk_hevc_mux"; + }; + + vdec { + compatible = "amlogic, vdec"; + dev_name = "vdec.0"; + status = "okay"; + interrupts = <0 3 1 + 0 23 1 + 0 32 1 + 0 43 1 + 0 44 1 + 0 45 1>; + interrupt-names = "vsync", + "demux", + "parser", + "mailbox_0", + "mailbox_1", + "mailbox_2"; + }; + + meson-fb { + compatible = "amlogic, meson-gxl"; + memory-region = <&fb_reserved>; + dev_name = "meson-fb"; + status = "okay"; + interrupts = <0 3 1 + 0 89 1>; + interrupt-names = "viu-vsync", "rdma"; + mem_size = <0x00800000 0x1800000 0x00100000>; + /* uboot logo,fb0/fb1 memory size,if afbcd fb0=0x01851000 */ + display_mode_default = "1080p60hz"; + scale_mode = <1>; + /** 0:VPU free scale 1:OSD free scale 2:OSD super scale */ + display_size_default = <1920 1080 1920 3240 32>; + /*1920*1080*4*3 = 0x17BB000*/ + mem_alloc = <1>; + logo_addr = "0x3dc00000"; + }; + ge2d { + compatible = "amlogic, ge2d-gxl"; + dev_name = "ge2d"; + status = "okay"; + interrupts = <0 150 1>; + interrupt-names = "ge2d"; + clocks = <&clkc CLKID_VAPB_MUX>, + <&clkc CLKID_G2D>, + <&clkc CLKID_GE2D_GATE>; + clock-names = "clk_vapb_0", + "clk_ge2d", + "clk_ge2d_gate"; + }; + + + /* AUDIO MESON DEVICES */ + i2s_dai: I2S { + #sound-dai-cells = <0>; + compatible = "amlogic, aml-i2s-dai"; + clocks = + <&clkc CLKID_MPLL2>, + <&clkc CLKID_AMCLK_COMP>, + <&clkc CLKID_AIU_GLUE>, + <&clkc CLKID_IEC958>, + <&clkc CLKID_I2S_OUT>, + <&clkc CLKID_AMCLK>, + <&clkc CLKID_AIFIFO2>, + <&clkc CLKID_MIXER>, + <&clkc CLKID_MIXER_IFACE>, + <&clkc CLKID_ADC>, + <&clkc CLKID_AIU_TOP>, + <&clkc CLKID_AOCLK_GATE>, + <&clkc CLKID_I2S_SPDIF>; + clock-names = + "mpll", + "mclk", + "top_glue", + "aud_buf", + "i2s_out", + "amclk_measure", + "aififo2", + "aud_mixer", + "mixer_reg", + "adc", + "top_level", + "aoclk", + "aud_in"; + i2s_pos_sync = <0>; + /*DMIC;*/ /* I2s Mic or Dmic, default for I2S mic */ + }; + dmic:snd_dmic { + #sound-dai-cells = <0>; + compatible = "aml, aml_snd_dmic"; + reg = <0xd0042000 0x2000>; + status = "disabled"; + resets = < + &clkc CLKID_PDM_GATE + >; + reset-names = "pdm"; + pinctrl-names = "audio_dmic"; + pinctrl-0 = <&aml_dmic_pins>; + clocks = <&clkc CLKID_PDM_COMP>, + <&clkc CLKID_AMCLK_COMP>; + clock-names = "pdm", "mclk"; + }; + spdif_dai: SPDIF { + #sound-dai-cells = <0>; + compatible = "amlogic, aml-spdif-dai"; + clocks = + <&clkc CLKID_MPLL1>, + <&clkc CLKID_I958_COMP>, + <&clkc CLKID_AMCLK_COMP>, + <&clkc CLKID_I958_COMP_SPDIF>, + <&clkc CLKID_CLK81>, + <&clkc CLKID_IEC958>, + <&clkc CLKID_IEC958_GATE>; + clock-names = + "mpll1", + "i958", + "mclk", + "spdif", + "clk_81", + "iec958", + "iec958_amclk"; + }; + pcm_dai: PCM { + #sound-dai-cells = <0>; + compatible = "amlogic, aml-pcm-dai"; + pinctrl-names = "audio_pcm"; + pinctrl-0 = <&audio_pcm_pins>; + clocks = + <&clkc CLKID_MPLL0>, + <&clkc CLKID_PCM_MCLK_COMP>, + <&clkc CLKID_PCM_SCLK_GATE>; + clock-names = + "mpll0", + "pcm_mclk", + "pcm_sclk"; + pcm_mode = <1>; /* 0=slave mode, 1=master mode */ + }; + i2s_plat: i2s_platform { + compatible = "amlogic, aml-i2s"; + interrupts = <0 29 1>; + }; + pcm_plat: pcm_platform { + compatible = "amlogic, aml-pcm"; + }; + spdif_codec: spdif_codec{ + #sound-dai-cells = <0>; + compatible = "amlogic, aml-spdif-codec"; + pinctrl-names = "audio_spdif"; + pinctrl-0 = <&audio_spdif_pins>; + }; + pcm_codec: pcm_codec{ + #sound-dai-cells = <0>; + compatible = "amlogic, pcm2BT-codec"; + }; + /* endof AUDIO MESON DEVICES */ + + /* AUDIO board specific */ + dummy_codec:dummy{ + #sound-dai-cells = <0>; + compatible = "amlogic, aml_dummy_codec"; + status = "disable"; + }; + amlogic_codec:t9015{ + #sound-dai-cells = <0>; + compatible = "amlogic, aml_codec_T9015"; + reg = <0xc8832000 0x14>; + status = "okay"; + }; + aml_sound_meson { + compatible = "aml, meson-snd-card"; + status = "okay"; + aml-sound-card,format = "i2s"; + aml_sound_card,name = "AML-MESONAUDIO"; + aml,audio-routing = + "Ext Spk","LOUTL", + "Ext Spk","LOUTR"; + + mute_gpio-gpios = <&gpio GPIOH_5 0>; + mute_inv; + hp_disable; + hp_paraments = <800 300 0 5 1>; + pinctrl-names = "audio_i2s"; + pinctrl-0 = <&audio_i2s_pins>; + cpu_list = <&cpudai0 &cpudai1 &cpudai2>; + codec_list = <&codec0 &codec1 &codec2>; + plat_list = <&i2s_plat &i2s_plat &pcm_plat>; + cpudai0: cpudai0 { + sound-dai = <&i2s_dai>; + }; + cpudai1: cpudai1 { + sound-dai = <&spdif_dai>; + }; + cpudai2: cpudai2 { + sound-dai = <&pcm_dai>; + }; + codec0: codec0 { + sound-dai = <&amlogic_codec>; + }; + codec1: codec1 { + sound-dai = <&spdif_codec>; + }; + codec2: codec2 { + sound-dai = <&pcm_codec>; + }; + }; + /* END OF AUDIO board specific */ + rdma{ + compatible = "amlogic, meson, rdma"; + dev_name = "amlogic-rdma"; + status = "ok"; + interrupts = <0 89 1>; + interrupt-names = "rdma"; + }; + + amvenc_avc{ + compatible = "amlogic, amvenc_avc"; + dev_name = "amvenc_avc"; + status = "okay"; + interrupts = <0 45 1>; + interrupt-names = "mailbox_2"; + }; + + hevc_enc{ + compatible = "cnm, HevcEnc"; + dev_name = "HevcEnc"; + status = "okay"; + interrupts = <0 187 1>; + interrupt-names = "wave420l_irq"; + #address-cells=<1>; + #size-cells=<1>; + ranges; + io_reg_base{ + reg = <0xc8810000 0x4000>; + }; + }; + + partitions: partitions{ + parts = <12>; + part-0 = <&logo>; + part-1 = <&recovery>; + part-2 = <&rsv>; + part-3 = <&tee>; + part-4 = <&crypt>; + part-5 = <&misc>; + part-6 = <&boot>; + part-7 = <&system>; + part-8 = <&cache>; + part-9 = <&vendor>; + part-10 = <&odm>; + part-11 = <&data>; + + logo:logo{ + pname = "logo"; + size = <0x0 0x2000000>; + mask = <1>; + }; + recovery:recovery{ + pname = "recovery"; + size = <0x0 0x2000000>; + mask = <1>; + }; + rsv:rsv{ + pname = "rsv"; + size = <0x0 0x800000>; + mask = <1>; + }; + tee:tee{ + pname = "tee"; + size = <0x0 0x800000>; + mask = <1>; + }; + crypt:crypt{ + pname = "crypt"; + size = <0x0 0x2000000>; + mask = <1>; + }; + misc:misc{ + pname = "misc"; + size = <0x0 0x2000000>; + mask = <1>; + }; + boot:boot + { + pname = "boot"; + size = <0x0 0x2000000>; + mask = <1>; + }; + system:system + { + pname = "system"; + size = <0x0 0x80000000>; + mask = <1>; + }; + vendor:vendor + { + pname = "vendor"; + size = <0x0 0x10000000>; + mask = <1>; + }; + odm:odm + { + pname = "odm"; + size = <0x0 0x10000000>; + mask = <1>; + }; + cache:cache + { + pname = "cache"; + size = <0x0 0x20000000>; + mask = <2>; + }; + data:data + { + pname = "data"; + size = <0xffffffff 0xffffffff>; + mask = <4>; + }; + }; + + ppmgr { + compatible = "amlogic, ppmgr"; + memory-region = <&ppmgr_reserved>; + dev_name = "ppmgr"; + status = "okay"; + }; + + deinterlace { + compatible = "amlogic, deinterlace"; + status = "okay"; + flag_cma = <1>;/*0:use reserved;1:use cma*/ + //memory-region = <&di_reserved>; + memory-region = <&di_cma_reserved>; + interrupts = <0 46 1 0 6 1>; + interrupt-names = "de_irq", "timerc"; + /* + * nr_size(byte) = 1920*544*2(yuv422 8bit) | + * 1920*544*2*12/8(yuv422 10bit) + * | 1920*544*2*10/8(yuv422 10bit full pack mode) + */ + /* mtn_size(byte) = 1920*544/2 */ + /* count_size(byte) = 1920*544/2 */ + buffer-size = <3133440>; + hw-version = <2>; + }; + + ionvideo { + compatible = "amlogic, ionvideo"; + dev_name = "ionvideo"; + status = "okay"; + }; + + amlvideo { + compatible = "amlogic, amlvideo"; + dev_name = "amlvideo"; + status = "okay"; + }; + + amlvideo2_0 { + compatible = "amlogic, amlvideo2"; + dev_name = "amlvideo2"; + status = "okay"; + amlvideo2_id = <0>; + cma_mode = <1>; + }; + + amlvideo2_1 { + compatible = "amlogic, amlvideo2"; + dev_name = "amlvideo2"; + status = "okay"; + amlvideo2_id = <1>; + cma_mode = <1>; + }; + + /*if you want to use vdin just modify status to "ok"*/ + vdin0 { + compatible = "amlogic, vdin"; + /*memory-region = <&vdin0_cma_reserved>;*/ + dev_name = "vdin0"; + status = "ok"; + reserve-iomap = "true"; + flag_cma = <1>;/*1:share with codec_mm;2:cma alone*/ + /*MByte, if 10bit disable: 64M(YUV422), + *if 10bit enable: 64*1.5 = 96M(YUV422) + *if support 4K2K-YUV444-10bit-WR:3840*2160*4*4 ~= 128M + *if support 4K2K-YUV422-10bit-wr:3840*2160*3*4 ~= 96M + *if support 4K2K-YUV422-8BIT-WR:3840*2160*2*4 ~= 64M + *if support 1080p-YUV422-8BIT-WR:1920*1080*2*4 ~= 16M + */ + cma_size = <16>; + interrupts = <0 83 1>; + rdma-irq = <2>; + /*clocks = <&clock CLK_FPLL_DIV5>, + * <&clock CLK_VDIN_MEAS_CLK>; + *clock-names = "fclk_div5", "cts_vdin_meas_clk"; + */ + vdin_id = <0>; + /*vdin write mem color depth support: + *bit0:support 8bit + *bit1:support 9bit + *bit2:support 10bit + *bit3:support 12bit + *bit4:support yuv422 10bit full pack mode (from txl new add) + */ + tv_bit_mode = <1>; + }; + vdin1 { + compatible = "amlogic, vdin"; + memory-region = <&vdin1_cma_reserved>; + dev_name = "vdin1"; + status = "ok"; + reserve-iomap = "true"; + flag_cma = <0>;/*1:share with codec_mm;0:cma alone*/ + interrupts = <0 85 1>; + rdma-irq = <4>; + /*clocks = <&clock CLK_FPLL_DIV5>, + * <&clock CLK_VDIN_MEAS_CLK>; + *clock-names = "fclk_div5", "cts_vdin_meas_clk"; + */ + vdin_id = <1>; + /*vdin write mem color depth support: + *bit0:support 8bit + *bit1:support 9bit + *bit2:support 10bit + *bit3:support 12bit + */ + tv_bit_mode = <1>; + }; + + amlvecm { + compatible = "amlogic, vecm"; + dev_name = "aml_vecm"; + status = "okay"; + gamma_en = <0>;/*1:enabel ;0:disable*/ + wb_en = <0>;/*1:enabel ;0:disable*/ + cm_en = <0>;/*1:enabel ;0:disable*/ + /*1:enabel osd lut 100 table;0:disable*/ + cfg_en_osd_100 = <1>; + /*0: 709/601 1: bt2020*/ + tx_op_color_primary = <0>; + }; + + unifykey{ + compatible = "amlogic, unifykey"; + status = "ok"; + + unifykey-num = <15>; + unifykey-index-0 = <&keysn_0>; + unifykey-index-1 = <&keysn_1>; + unifykey-index-2 = <&keysn_2>; + unifykey-index-3 = <&keysn_3>; + unifykey-index-4 = <&keysn_4>; + unifykey-index-5 = <&keysn_5>; + unifykey-index-6 = <&keysn_6>; + unifykey-index-7 = <&keysn_7>; + unifykey-index-8 = <&keysn_8>; + unifykey-index-9 = <&keysn_9>; + unifykey-index-10= <&keysn_10>; + unifykey-index-11= <&keysn_11>; + unifykey-index-12= <&keysn_12>; + unifykey-index-13= <&keysn_13>; + unifykey-index-14= <&keysn_14>; + + keysn_0: key_0{ + key-name = "usid"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_1:key_1{ + key-name = "mac"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_2:key_2{ + key-name = "hdcp"; + key-device = "secure"; + key-type = "sha1"; + key-permit = "read","write","del"; + }; + keysn_3:key_3{ + key-name = "secure_boot_set"; + key-device = "efuse"; + key-permit = "write"; + }; + keysn_4:key_4{ + key-name = "mac_bt"; + key-device = "normal"; + key-permit = "read","write","del"; + key-type = "mac"; + }; + keysn_5:key_5{ + key-name = "mac_wifi"; + key-device = "normal"; + key-permit = "read","write","del"; + key-type = "mac"; + }; + keysn_6:key_6{ + key-name = "hdcp2_tx"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_7:key_7{ + key-name = "hdcp2_rx"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_8:key_8{ + key-name = "widevinekeybox"; + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_9:key_9{ + key-name = "deviceid"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_10:key_10{ + key-name = "hdcp22_fw_private"; + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_11:key_11{ + key-name = "PlayReadykeybox25"; + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_12:key_12{ + key-name = "prpubkeybox";// PlayReady + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_13:key_13{ + key-name = "prprivkeybox";// PlayReady + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_14:key_14{ + key-name = "attestationkeybox";// attestation key + key-device = "secure"; + key-permit = "read","write","del"; + }; + };//End unifykey + +}; +&efuse { + status = "ok"; +}; + +&pwm_ef { + status = "okay"; +}; + +&audio_data{ + status = "okay"; +}; +&spicc{ + status = "disabled"; + pinctrl-names = "spicc_pulldown","spicc_pullup"; + pinctrl-0 = <&spicc_pulldown_x8x9x11>; + pinctrl-1 = <&spicc_pullup_x8x9x11>; + num_chipselect = <1>; + cs-gpios = <&gpio GPIOX_10 GPIO_ACTIVE_HIGH>; + dma_en = <0>; + dma_tx_threshold = <3>; + dma_rx_threshold = <3>; + dma_num_per_read_burst = <3>; + dma_num_per_write_burst = <3>; + delay_control = <0x15>; + ssctl = <0>; +}; + diff --git a/arch/arm/boot/dts/amlogic/gxl_p212_1g_hd.dts b/arch/arm/boot/dts/amlogic/gxl_p212_1g_hd.dts new file mode 100644 index 000000000000..1c9feacbf504 --- /dev/null +++ b/arch/arm/boot/dts/amlogic/gxl_p212_1g_hd.dts @@ -0,0 +1,1208 @@ +/* + * arch/arm/boot/dts/amlogic/gxl_p212_1g.dts + * + * Copyright (C) 2017 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +/dts-v1/; + +#include "mesongxl.dtsi" +#include "partition_mbox_normal.dtsi" +/ { + model = "Amlogic"; + amlogic-dt-id = "gxl_p212_1g"; + compatible = "amlogic, Gxl"; + interrupt-parent = <&gic>; + #address-cells = <1>; + #size-cells = <1>; + + aliases { + serial0 = &uart_AO; + serial1 = &uart_A; + serial2 = &uart_B; + serial3 = &uart_C; + serial4 = &uart_AO_B; + }; + + ion_dev { + compatible = "amlogic, ion_dev"; + memory-region = <&ion_reserved>; + }; + + memory@00000000 { + device_type = "memory"; + linux,usable-memory = <0x0100000 0x3ff00000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + /* global autoconfigured region for contiguous allocations */ + secmon_reserved:linux,secmon { + compatible = "shared-dma-pool"; + reusable; + size = <0x400000>; + alignment = <0x400000>; + alloc-ranges = <0x05000000 0x400000>; + }; + secos_reserved:linux,secos { + status = "disable"; + compatible = "amlogic, aml_secos_memory"; + reg = <0x05300000 0x2000000>; + no-map; + }; + logo_reserved:linux,meson-fb { + compatible = "shared-dma-pool"; + reusable; + size = <0x400000>; + alignment = <0x400000>; + alloc-ranges = <0x3fc00000 0x400000>; + }; + //don't put other dts in front of logo_reserved + + //di_reserved:linux,di { + // compatible = "amlogic, di-mem"; + /** 10x3133440=30M(0x1e) support 8bit **/ + // size = <0x1e00000>; + //no-map; + //}; + di_cma_reserved:linux,di_cma { + compatible = "shared-dma-pool"; + reusable; + /** 10x3133440=30M(0x1e) support 8bit **/ + size = <0x2000000>; + alignment = <0x400000>; + }; + ion_reserved:linux,ion-dev { + compatible = "shared-dma-pool"; + reusable; + size = <0x1000000>; + alignment = <0x400000>; + alloc-ranges = <0x0 0x30000000>; + }; + + /* vdin0 CMA pool */ + //vdin0_cma_reserved:linux,vdin0_cma { + // compatible = "shared-dma-pool"; + // linux,phandle = <4>; + // reusable; + /* 1920x1080x2x4 =16+4 M */ + // size = <0x01400000>; + // alignment = <0x400000>; + //}; + /* vdin1 CMA pool */ + vdin1_cma_reserved:linux,vdin1_cma { + compatible = "shared-dma-pool"; + reusable; + /* 1920x1080x2x4 =16 M */ + size = <0x01000000>; + alignment = <0x400000>; + }; + /* POST PROCESS MANAGER */ + ppmgr_reserved:linux,ppmgr { + compatible = "shared-dma-pool"; + size = <0x0>; + }; + + codec_mm_cma:linux,codec_mm_cma { + compatible = "shared-dma-pool"; + reusable; + /* ion_codec_mm max can alloc size 80M*/ + size = <0x10400000>; + alignment = <0x400000>; + linux,contiguous-region; + }; + picdec_cma_reserved:linux,picdec { + compatible = "shared-dma-pool"; + reusable; + size = <0x0>; + alignment = <0x0>; + linux,contiguous-region; + }; + /* codec shared reserved */ + codec_mm_reserved:linux,codec_mm_reserved { + compatible = "amlogic, codec-mm-reserved"; + size = <0x0>; + alignment = <0x100000>; + //no-map; + }; + }; + + bt-dev{ + compatible = "amlogic, bt-dev"; + dev_name = "bt-dev"; + status = "okay"; + gpio_reset = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>; + }; + + wifi{ + compatible = "amlogic, aml_wifi"; + dev_name = "aml_wifi"; + status = "okay"; + interrupt_pin = <&gpio GPIOX_7 GPIO_ACTIVE_HIGH>; + irq_trigger_type = "GPIO_IRQ_LOW"; + dhd_static_buf; //dhd_static_buf support + power_on_pin = <&gpio GPIOX_6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_32k_pins>; + pwm_config = <&wifi_pwm_conf>; + }; + + wifi_pwm_conf:wifi_pwm_conf{ + pwm_channel1_conf { + pwms = <&pwm_ef MESON_PWM_0 30040 0>; + duty-cycle = <15020>; + times = <8>; + }; + pwm_channel2_conf { + pwms = <&pwm_ef MESON_PWM_2 30030 0>; + duty-cycle = <15015>; + times = <12>; + }; + }; + + sd_emmc_c: emmc@d0074000 { + status = "okay"; + compatible = "amlogic, meson-mmc-gxl"; + reg = <0xd0074000 0x2000>; + interrupts = <0 218 1>; + pinctrl-names = "emmc_clk_cmd_pins", "emmc_all_pins"; + pinctrl-0 = <&emmc_clk_cmd_pins>; + pinctrl-1 = <&emmc_conf_pull_up &emmc_conf_pull_done>; + clocks = <&clkc CLKID_SD_EMMC_C>, + <&clkc CLKID_SD_EMMC_C_P0_COMP>, + <&clkc CLKID_FCLK_DIV2>; + clock-names = "core", "clkin0", "clkin1"; + + bus-width = <8>; + cap-sd-highspeed; + cap-mmc-highspeed; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + + max-frequency = <200000000>; + non-removable; + disable-wp; + emmc { + pinname = "emmc"; + ocr_avail = <0x200080>; /**VDD voltage 3.3 ~ 3.4 */ + caps = "MMC_CAP_8_BIT_DATA", + "MMC_CAP_MMC_HIGHSPEED", + "MMC_CAP_SD_HIGHSPEED", + "MMC_CAP_NONREMOVABLE", + "MMC_CAP_1_8V_DDR", + "MMC_CAP_HW_RESET", + "MMC_CAP_ERASE", + "MMC_CAP_CMD23"; + caps2 = "MMC_CAP2_HS200", "MMC_CAP2_HS400"; + f_min = <400000>; + f_max = <100000000>; + max_req_size = <0x20000>; /**128KB*/ + gpio_dat3 = <&gpio BOOT_3 GPIO_ACTIVE_HIGH>; + hw_reset = <&gpio BOOT_9 GPIO_ACTIVE_HIGH>; + card_type = <1>; + /* 1:mmc card(include eMMC), + * 2:sd card(include tSD) + */ + }; + }; + + sd_emmc_b:sd@d0072000 { + status = "okay"; + compatible = "amlogic, meson-mmc-gxl"; + reg = <0xd0072000 0x2000>; + interrupts = <0 217 1>; + pinctrl-names = "sd_all_pins", + "sd_clk_cmd_pins", + "sd_1bit_pins", + "sd_clk_cmd_uart_pins", + "sd_1bit_uart_pins", + "sd_to_ao_uart_pins", + "ao_to_sd_uart_pins", + "ao_to_sd_jtag_pins", + "sd_to_ao_jtag_pins"; + pinctrl-0 = <&sd_all_pins>; + pinctrl-1 = <&sd_clk_cmd_pins>; + pinctrl-2 = <&sd_1bit_pins>; + pinctrl-3 = <&sd_to_ao_uart_clr_pins + &sd_clk_cmd_pins &ao_to_sd_uart_pins>; + pinctrl-4 = <&sd_to_ao_uart_clr_pins + &sd_1bit_pins &ao_to_sd_uart_pins>; + pinctrl-5 = <&sd_all_pins &sd_to_ao_uart_pins>; + pinctrl-6 = <&sd_to_ao_uart_clr_pins &ao_to_sd_uart_pins>; + pinctrl-7 = <&sd_to_ao_uart_clr_pins &ao_to_sd_uart_pins>; + pinctrl-8 = <&sd_all_pins &sd_to_ao_uart_pins>; + clocks = <&clkc CLKID_SD_EMMC_B>, + <&clkc CLKID_SD_EMMC_B_P0_COMP>, + <&clkc CLKID_FCLK_DIV2>; + clock-names = "core", "clkin0", "clkin1"; + + bus-width = <4>; + cap-sd-highspeed; + max-frequency = <100000000>; + disable-wp; + sd { + pinname = "sd"; + ocr_avail = <0x200080>; /**VDD voltage 3.3 ~ 3.4 */ + caps = "MMC_CAP_4_BIT_DATA", + "MMC_CAP_MMC_HIGHSPEED", + "MMC_CAP_SD_HIGHSPEED"; + /* "MMC_CAP_UHS_SDR12", + * "MMC_CAP_UHS_SDR25", + * "MMC_CAP_UHS_SDR50", + * "MMC_CAP_UHS_SDR104"; + */ + f_min = <400000>; + f_max = <100000000>; + max_req_size = <0x20000>; /**128KB*/ + gpio_dat3 = <&gpio CARD_4 GPIO_ACTIVE_HIGH>; + jtag_pin = <&gpio CARD_0 GPIO_ACTIVE_HIGH>; + gpio_cd = <&gpio CARD_6 GPIO_ACTIVE_HIGH>; + card_type = <5>; + /* 0:unknown, + * 1:mmc card(include eMMC), + * 2:sd card(include tSD), + * 3:sdio device(ie:sdio-wifi), + * 4:SD combo (IO+mem) card, + * 5:NON sdio device(means sd/mmc card), + * other:reserved + */ + }; + }; + + sd_emmc_a:sdio@d0070000 { + status = "okay"; + compatible = "amlogic, meson-mmc-gxl"; + reg = <0xd0070000 0x2000>; + interrupts = <0 216 4>; + pinctrl-names = "sdio_clk_cmd_pins", "sdio_all_pins"; + pinctrl-0 = <&sdio_clk_cmd_pins>; + pinctrl-1 = <&sdio_all_pins>; + clocks = <&clkc CLKID_SD_EMMC_A>, + <&clkc CLKID_SD_EMMC_A_P0_COMP>, + <&clkc CLKID_FCLK_DIV2>; + clock-names = "core", "clkin0", "clkin1"; + + bus-width = <4>; + cap-sd-highspeed; + cap-mmc-highspeed; + max-frequency = <100000000>; + non-removable; + disable-wp; + sdio { + pinname = "sdio"; + ocr_avail = <0x200080>; /**VDD voltage 3.3 ~ 3.4 */ + caps = "MMC_CAP_4_BIT_DATA", + "MMC_CAP_MMC_HIGHSPEED", + "MMC_CAP_SD_HIGHSPEED", + "MMC_CAP_NONREMOVABLE", + "MMC_CAP_UHS_SDR12", + "MMC_CAP_UHS_SDR25", + "MMC_CAP_UHS_SDR50", + "MMC_CAP_UHS_SDR104", + "MMC_PM_KEEP_POWER", + "MMC_CAP_SDIO_IRQ"; + f_min = <400000>; + f_max = <200000000>; + max_req_size = <0x20000>; /**128KB*/ + card_type = <3>; + /* 3:sdio device(ie:sdio-wifi), + * 4:SD combo (IO+mem) card + */ + }; + }; + mtd_nand{ + compatible = "amlogic, aml_mtd_nand"; + dev_name = "mtdnand"; + status = "disabled"; + reg = <0xd0074800 0x200>; + interrupts = < 0 34 1 >; + pinctrl-names = "nand_rb_mod","nand_norb_mod", "nand_cs_only"; + pinctrl-0 = <&all_nand_pins>; + pinctrl-1 = <&all_nand_pins>; + pinctrl-2 = <&nand_cs_pins>; + device_id = <0>; + plat-names = "bootloader","nandnormal"; + plat-num = <2>; + plat-part-0 = <&bootloader>; + plat-part-1 = <&nandnormal>; + bootloader: bootloader{ + enable_pad ="ce0"; + busy_pad = "rb0"; + timming_mode = "mode5"; + bch_mode = "bch60_1k"; + t_rea = <20>; + t_rhoh = <15>; + chip_num = <1>; + part_num = <0>; + rb_detect = <1>; + }; + nandnormal: nandnormal{ + enable_pad ="ce0","ce1"; + busy_pad = "rb0","rb1"; + timming_mode = "mode5"; + bch_mode = "bch60_1k"; + plane_mode = "twoplane"; + t_rea = <20>; + t_rhoh = <15>; + chip_num = <2>; + part_num = <3>; + partition = <&nand_partitions>; + rb_detect = <1>; + }; + nand_partitions:nand_partition{ + logo{ + offset=<0x0 0x0>; + size=<0x0 0x200000>; + }; + recovery{ + offset=<0x0 0x0>; + size=<0x0 0x1000000>; + }; + boot{ + offset=<0x0 0x0>; + size=<0x0 0xC00000>; + }; + system{ + offset=<0x0 0x0>; + size=<0x0 0xDC40000>; + }; + data{ + offset=<0xffffffff 0xffffffff>; + size=<0x0 0x0>; + }; + }; + }; + + ethmac: ethernet@0xc9410000 { + compatible = "amlogic, gxbb-eth-dwmac"; + reg = <0xc9410000 0x10000 + 0xc8834540 0x8 + 0xc8834558 0xc>; + interrupts = <0 8 1>; + pinctrl-names = "external_eth_pins"; + pinctrl-0 = <&external_eth_pins>; + rst_pin-gpios = <&gpio GPIOZ_14 0>; + GPIOZ4_pin-gpios = <&gpio GPIOZ_4 0>; + GPIOZ5_pin-gpios = <&gpio GPIOZ_5 0>; + mc_val_internal_phy = <0x1800>; + mc_val_external_phy = <0x1621>; + cali_val = <0x20000>; + interrupt-names = "macirq"; + clocks = <&clkc CLKID_ETH>; + clock-names = "ethclk81"; + internal_phy=<1>; + }; + + aml_sensor0: aml-sensor@0 { + compatible = "amlogic, aml-thermal"; + device_name = "thermal"; + #thermal-sensor-cells = <1>; + cooling_devices { + cpufreq_cool_cluster0 { + min_state = <1000000>; + dyn_coeff = <140>; + cluster_id = <0>; + node_name = "cpufreq_cool0"; + device_type = "cpufreq"; + }; + cpucore_cool_cluster0 { + min_state = <1>; + dyn_coeff = <0>; + cluster_id = <0>; + node_name = "cpucore_cool0"; + device_type = "cpucore"; + }; + gpufreq_cool { + min_state = <400>; + dyn_coeff = <437>; + cluster_id = <0>; + node_name = "gpufreq_cool0"; + device_type = "gpufreq"; + }; + gpucore_cool { + min_state = <1>; + dyn_coeff = <0>; + cluster_id = <0>; + node_name = "gpucore_cool0"; + device_type = "gpucore"; + }; + }; + cpufreq_cool0:cpufreq_cool0 { + #cooling-cells = <2>; /* min followed by max */ + }; + cpucore_cool0:cpucore_cool0 { + #cooling-cells = <2>; /* min followed by max */ + }; + gpufreq_cool0:gpufreq_cool0 { + #cooling-cells = <2>; /* min followed by max */ + }; + gpucore_cool0:gpucore_cool0 { + #cooling-cells = <2>; /* min followed by max */ + }; + }; + thermal-zones { + soc_thermal { + polling-delay = <1000>; + polling-delay-passive = <100>; + sustainable-power = <2150>; + + thermal-sensors = <&aml_sensor0 3>; + + trips { + switch_on: trip-point@0 { + temperature = <70000>; + hysteresis = <1000>; + type = "passive"; + }; + control: trip-point@1 { + temperature = <80000>; + hysteresis = <1000>; + type = "passive"; + }; + hot: trip-point@2 { + temperature = <85000>; + hysteresis = <5000>; + type = "hot"; + }; + critical: trip-point@3 { + temperature = <260000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + + cooling-maps { + cpufreq_cooling_map { + trip = <&control>; + cooling-device = <&cpufreq_cool0 0 4>; + contribution = <1024>; + }; + cpucore_cooling_map { + trip = <&control>; + cooling-device = <&cpucore_cool0 0 3>; + contribution = <1024>; + }; + gpufreq_cooling_map { + trip = <&control>; + cooling-device = <&gpufreq_cool0 0 4>; + contribution = <1024>; + }; + gpucore_cooling_map { + trip = <&control>; + cooling-device = <&gpucore_cool0 0 2>; + contribution = <1024>; + }; + }; + }; + }; + + dwc3: dwc3@c9000000 { + compatible = "synopsys, dwc3"; + reg = <0xc9000000 0x100000>; + interrupts = <0 30 4>; + usb-phy = <&usb2_phy>, <&usb3_phy>; + cpu-type = "gxl"; + clock-src = "usb3.0"; + }; + + usb2_phy: usb2phy@d0078000 { + compatible = "amlogic, amlogic-new-usb2"; + portnum = <3>; + reg = <0xd0078000 0x80 + 0xc1104408 0x4>; + }; + + usb3_phy: usb3phy@d0078080 { + compatible = "amlogic, amlogic-new-usb3"; + portnum = <0>; + reg = <0xd0078080 0x20>; + }; + + dwc2_a { + compatible = "amlogic, dwc2"; + device_name = "dwc2_a"; + reg = <0xc9100000 0x40000>; + status = "okay"; + interrupts = <0 31 4>; + pl-periph-id = <0>; /** lm name */ + clock-src = "usb0"; /** clock src */ + port-id = <0>; /** ref to mach/usb.h */ + port-type = <2>; /** 0: otg, 1: host, 2: slave */ + port-speed = <0>; /** 0: default, high, 1: full */ + port-config = <0>; /** 0: default */ + port-dma = <0>; /** 0: default ... 6: disable*/ + port-id-mode = <0>; /** 0: hardware, 1: sw_host, 2: sw_slave*/ + usb-fifo = <728>; + cpu-type = "gxl"; + controller-type = <1>; /** 0: normal, 1: host, 2: device*/ + phy-reg = <0xd0078000>; + phy-reg-size = <0xa0>; + clocks = <&clkc CLKID_USB_GENERAL + &clkc CLKID_USB1_TO_DDR + &clkc CLKID_USB1>; + clock-names = "usb_general", + "usb1", + "usb1_to_ddr"; + }; + + meson-amvideom { + compatible = "amlogic, amvideom"; + dev_name = "amvideom"; + status = "okay"; + interrupts = <0 3 1>; + interrupt-names = "vsync"; + }; + + vout { + compatible = "amlogic, vout"; + dev_name = "vout"; + status = "okay"; + fr_auto_policy = <0>; + }; + + cvbsout { + compatible = "amlogic, cvbsout-gxl"; + dev_name = "cvbsout"; + status = "okay"; + clocks = <&clkc CLKID_VCLK2_ENCI + &clkc CLKID_VCLK2_VENCI0 + &clkc CLKID_VCLK2_VENCI1 + &clkc CLKID_DAC_CLK>; + clock-names = "venci_top_gate", + "venci_0_gate", + "venci_1_gate", + "vdac_clk_gate"; + + /* performance: reg_address, reg_value */ + /* s905x */ + performance = <0x1bf0 0x9 + 0x1b56 0x343 + 0x1b12 0x8080 + 0x1b05 0xfd + 0x1c59 0xf752 + 0xffff 0x0>; /* ending flag */ + }; + + amhdmitx: amhdmitx{ + compatible = "amlogic, amhdmitx"; + dev_name = "amhdmitx"; + status = "okay"; + vend-data = <&vend_data>; + pinctrl-names="hdmitx_hpd", "hdmitx_ddc"; + pinctrl-0=<&hdmitx_hpd>; + pinctrl-1=<&hdmitx_ddc>; + /* HPD, 57 + 32 = 89; CEC, 151 + 32 = 183*/ + interrupts = <0 57 1>; + interrupt-names = "hdmitx_hpd"; + /* 0:M8B 1:GXBB 2:GXTVBB 3:GXL 4:GXM + * 5:TXL 6:TXLX 7:AXG 8:GXLX 9:TXHD + */ + ic_type = <3>; + vend_data: vend_data{ /* Should modified by Customer */ + vendor_name = "Amlogic"; /* Max Chars: 8 */ + /* standards.ieee.org/develop/regauth/oui/oui.txt */ + vendor_id = <0x000000>; + product_desc = "MBox Meson Ref"; /* Max Chars: 16 */ + }; + }; + + aocec: aocec{ + compatible = "amlogic, amlogic-aocec"; + device_name = "aocec"; + status = "okay"; + vendor_id = <0x000000>; + cec_osd_string = "MBox"; /* Max Chars: 14 */ + cec_version = <5>; /* 5: 1.4, 6: 2.0 */ + port_num = <1>; + arc_port_mask = <0x0>; + interrupts = <0 199 1>; + interrupt-names = "hdmi_aocec"; + pinctrl-names = "default"; + pinctrl-0=<&hdmitx_aocec>; + reg = <0xc810023c 0x4 + 0xc8100000 0x200>; + reg-names = "ao_exit","ao"; + }; + + sysled { + compatible = "amlogic, sysled"; + dev_name = "sysled"; + status = "disabled"; + led_gpio = <&gpio GPIODV_24 GPIO_ACTIVE_HIGH>; + led_active_low = <1>; + }; + + codec_io { + compatible = "amlogic, codec_io"; + #address-cells=<1>; + #size-cells=<1>; + ranges; + io_cbus_base{ + reg = <0xC1100000 0x100000>; + }; + io_dos_base{ + reg = <0xc8820000 0x10000>; + }; + io_hiubus_base{ + reg = <0xc883c000 0x2000>; + }; + io_aobus_base{ + reg = <0xc8100000 0x100000>; + }; + io_vcbus_base{ + reg = <0xd0100000 0x40000>; + }; + io_dmc_base{ + reg = <0xc8838000 0x400>; + }; + }; + + codec_mm { + compatible = "amlogic, codec, mm"; + memory-region = <&codec_mm_cma &codec_mm_reserved>; + dev_name = "codec_mm"; + status = "okay"; + }; + + canvas{ + compatible = "amlogic, meson, canvas"; + dev_name = "amlogic-canvas"; + status = "ok"; + reg = <0xc8838000 0x400>; + }; + + mesonstream { + compatible = "amlogic, codec, streambuf"; + dev_name = "mesonstream"; + status = "okay"; + clocks = <&clkc CLKID_DOS_PARSER + &clkc CLKID_DEMUX + &clkc CLKID_DOS + &clkc CLKID_CLK81 + &clkc CLKID_VDEC_MUX + &clkc CLKID_HCODEC_MUX + &clkc CLKID_HEVC_MUX>; + clock-names = "parser_top", + "demux", + "vdec", + "clk_81", + "clk_vdec_mux", + "clk_hcodec_mux", + "clk_hevc_mux"; + }; + + vdec { + compatible = "amlogic, vdec"; + dev_name = "vdec.0"; + status = "okay"; + interrupts = <0 3 1 + 0 23 1 + 0 32 1 + 0 43 1 + 0 44 1 + 0 45 1>; + interrupt-names = "vsync", + "demux", + "parser", + "mailbox_0", + "mailbox_1", + "mailbox_2"; + }; + + gpio_keypad{ + compatible = "amlogic, gpio_keypad"; + status = "okay"; + scan_period = <20>; + key_num = <1>; + key_name = "power"; + key_code = <116>; + key-gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_HIGH>; + detect_mode = <0>;/*0:polling mode, 1:irq mode*/ + }; + meson-fb { + compatible = "amlogic, meson-gxl"; + memory-region = <&logo_reserved>; + dev_name = "meson-fb"; + status = "okay"; + interrupts = <0 3 1 + 0 89 1>; + interrupt-names = "viu-vsync", "rdma"; + mem_size = <0x00400000 0x01800000 0x00100000>; + /* uboot logo,fb0/fb1 memory size,if afbcd fb0=0x01851000*/ + display_mode_default = "720p60hz"; + scale_mode = <1>; + /** 0:VPU free scale 1:OSD free scale 2:OSD super scale */ + display_size_default = <1280 720 1280 2160 32>; + /*1920*1080*4*3 = 0xA8C000*/ + logo_addr = "0x3fc00000"; + }; + ge2d { + compatible = "amlogic, ge2d-gxl"; + dev_name = "ge2d"; + status = "okay"; + interrupts = <0 150 1>; + interrupt-names = "ge2d"; + clocks = <&clkc CLKID_VAPB_MUX>, + <&clkc CLKID_G2D>, + <&clkc CLKID_GE2D_GATE>; + clock-names = "clk_vapb_0", + "clk_ge2d", + "clk_ge2d_gate"; + }; + + + /* AUDIO MESON DEVICES */ + i2s_dai: I2S { + #sound-dai-cells = <0>; + compatible = "amlogic, aml-i2s-dai"; + clocks = + <&clkc CLKID_MPLL2>, + <&clkc CLKID_AMCLK_COMP>, + <&clkc CLKID_AIU_GLUE>, + <&clkc CLKID_IEC958>, + <&clkc CLKID_I2S_OUT>, + <&clkc CLKID_AMCLK>, + <&clkc CLKID_AIFIFO2>, + <&clkc CLKID_MIXER>, + <&clkc CLKID_MIXER_IFACE>, + <&clkc CLKID_ADC>, + <&clkc CLKID_AIU_TOP>, + <&clkc CLKID_AOCLK_GATE>, + <&clkc CLKID_I2S_SPDIF>; + clock-names = + "mpll", + "mclk", + "top_glue", + "aud_buf", + "i2s_out", + "amclk_measure", + "aififo2", + "aud_mixer", + "mixer_reg", + "adc", + "top_level", + "aoclk", + "aud_in"; + i2s_pos_sync = <0>; + /*DMIC;*/ /* I2s Mic or Dmic, default for I2S mic */ + }; + dmic:snd_dmic { + #sound-dai-cells = <0>; + compatible = "aml, aml_snd_dmic"; + reg = <0xd0042000 0x2000>; + status = "disabled"; + resets = < + &clkc CLKID_PDM_GATE + >; + reset-names = "pdm"; + pinctrl-names = "audio_dmic"; + pinctrl-0 = <&aml_dmic_pins>; + clocks = <&clkc CLKID_PDM_COMP>, + <&clkc CLKID_AMCLK_COMP>; + clock-names = "pdm", "mclk"; + }; + spdif_dai: SPDIF { + #sound-dai-cells = <0>; + compatible = "amlogic, aml-spdif-dai"; + clocks = + <&clkc CLKID_MPLL1>, + <&clkc CLKID_I958_COMP>, + <&clkc CLKID_AMCLK_COMP>, + <&clkc CLKID_I958_COMP_SPDIF>, + <&clkc CLKID_CLK81>, + <&clkc CLKID_IEC958>, + <&clkc CLKID_IEC958_GATE>; + clock-names = + "mpll1", + "i958", + "mclk", + "spdif", + "clk_81", + "iec958", + "iec958_amclk"; + }; + pcm_dai: PCM { + #sound-dai-cells = <0>; + compatible = "amlogic, aml-pcm-dai"; + pinctrl-names = "audio_pcm"; + pinctrl-0 = <&audio_pcm_pins>; + clocks = + <&clkc CLKID_MPLL0>, + <&clkc CLKID_PCM_MCLK_COMP>, + <&clkc CLKID_PCM_SCLK_GATE>; + clock-names = + "mpll0", + "pcm_mclk", + "pcm_sclk"; + pcm_mode = <1>; /* 0=slave mode, 1=master mode */ + }; + i2s_plat: i2s_platform { + compatible = "amlogic, aml-i2s"; + interrupts = <0 29 1>; + }; + pcm_plat: pcm_platform { + compatible = "amlogic, aml-pcm"; + }; + spdif_codec: spdif_codec{ + #sound-dai-cells = <0>; + compatible = "amlogic, aml-spdif-codec"; + pinctrl-names = "audio_spdif"; + pinctrl-0 = <&audio_spdif_pins>; + }; + pcm_codec: pcm_codec{ + #sound-dai-cells = <0>; + compatible = "amlogic, pcm2BT-codec"; + }; + /* endof AUDIO MESON DEVICES */ + + /* AUDIO board specific */ + dummy_codec:dummy{ + #sound-dai-cells = <0>; + compatible = "amlogic, aml_dummy_codec"; + status = "disable"; + }; + amlogic_codec:t9015{ + #sound-dai-cells = <0>; + compatible = "amlogic, aml_codec_T9015"; + reg = <0xc8832000 0x14>; + status = "okay"; + }; + aml_sound_meson { + compatible = "aml, meson-snd-card"; + status = "okay"; + aml-sound-card,format = "i2s"; + aml_sound_card,name = "AML-MESONAUDIO"; + aml,audio-routing = + "Ext Spk","LOUTL", + "Ext Spk","LOUTR"; + + mute_gpio-gpios = <&gpio GPIOH_5 0>; + mute_inv; + hp_disable; + hp_paraments = <800 300 0 5 1>; + pinctrl-names = "audio_i2s"; + pinctrl-0 = <&audio_i2s_pins>; + cpu_list = <&cpudai0 &cpudai1 &cpudai2>; + codec_list = <&codec0 &codec1 &codec2>; + plat_list = <&i2s_plat &i2s_plat &pcm_plat>; + cpudai0: cpudai0 { + sound-dai = <&i2s_dai>; + }; + cpudai1: cpudai1 { + sound-dai = <&spdif_dai>; + }; + cpudai2: cpudai2 { + sound-dai = <&pcm_dai>; + }; + codec0: codec0 { + sound-dai = <&amlogic_codec>; + }; + codec1: codec1 { + sound-dai = <&spdif_codec>; + }; + codec2: codec2 { + sound-dai = <&pcm_codec>; + }; + }; + /* END OF AUDIO board specific */ + rdma{ + compatible = "amlogic, meson, rdma"; + dev_name = "amlogic-rdma"; + status = "ok"; + interrupts = <0 89 1>; + interrupt-names = "rdma"; + }; + + amvenc_avc{ + compatible = "amlogic, amvenc_avc"; + dev_name = "amvenc_avc"; + status = "okay"; + interrupts = <0 45 1>; + interrupt-names = "mailbox_2"; + }; + + hevc_enc{ + compatible = "cnm, HevcEnc"; + dev_name = "HevcEnc"; + status = "okay"; + interrupts = <0 187 1>; + interrupt-names = "wave420l_irq"; + #address-cells=<1>; + #size-cells=<1>; + ranges; + io_reg_base{ + reg = <0xc8810000 0x4000>; + }; + }; + + picdec { + compatible = "amlogic, picdec"; + memory-region = <&picdec_cma_reserved>; + dev_name = "picdec"; + status = "okay"; + }; + + ppmgr { + compatible = "amlogic, ppmgr"; + memory-region = <&ppmgr_reserved>; + dev_name = "ppmgr"; + status = "okay"; + }; + + deinterlace { + compatible = "amlogic, deinterlace"; + status = "okay"; + flag_cma = <1>;/*0:use reserved;1:use cma*/ + //memory-region = <&di_reserved>; + memory-region = <&di_cma_reserved>; + interrupts = <0 46 1 0 6 1>; + interrupt-names = "de_irq", "timerc"; + /* + * nr_size(byte) = 1920*544*2(yuv422 8bit) | + * 1920*544*2*12/8(yuv422 10bit) + * | 1920*544*2*10/8(yuv422 10bit full pack mode) + */ + /* mtn_size(byte) = 1920*544/2 */ + /* count_size(byte) = 1920*544/2 */ + buffer-size = <3133440>; + hw-version = <2>; + }; + + ionvideo { + compatible = "amlogic, ionvideo"; + dev_name = "ionvideo"; + status = "okay"; + }; + + amlvideo { + compatible = "amlogic, amlvideo"; + dev_name = "amlvideo"; + status = "okay"; + }; + + amlvideo2_0 { + compatible = "amlogic, amlvideo2"; + dev_name = "amlvideo2"; + status = "okay"; + amlvideo2_id = <0>; + cma_mode = <1>; + }; + + amlvideo2_1 { + compatible = "amlogic, amlvideo2"; + dev_name = "amlvideo2"; + status = "okay"; + amlvideo2_id = <1>; + cma_mode = <1>; + }; + + /*if you want to use vdin just modify status to "ok"*/ + vdin0 { + compatible = "amlogic, vdin"; + /*memory-region = <&vdin0_cma_reserved>;*/ + dev_name = "vdin0"; + status = "ok"; + reserve-iomap = "true"; + flag_cma = <1>;/*1:share with codec_mm;2:cma alone*/ + /*MByte, if 10bit disable: 64M(YUV422), + *if 10bit enable: 64*1.5 = 96M(YUV422) + *if support 4K2K-YUV444-10bit-WR:3840*2160*4*4 ~= 128M + *if support 4K2K-YUV422-10bit-wr:3840*2160*3*4 ~= 96M + *if support 4K2K-YUV422-8BIT-WR:3840*2160*2*4 ~= 64M + *if support 1080p-YUV422-8BIT-WR:1920*1080*2*4 ~= 16M + */ + cma_size = <16>; + interrupts = <0 83 1>; + rdma-irq = <2>; + /*clocks = <&clock CLK_FPLL_DIV5>, + * <&clock CLK_VDIN_MEAS_CLK>; + *clock-names = "fclk_div5", "cts_vdin_meas_clk"; + */ + vdin_id = <0>; + /*vdin write mem color depth support: + *bit0:support 8bit + *bit1:support 9bit + *bit2:support 10bit + *bit3:support 12bit + *bit4:support yuv422 10bit full pack mode (from txl new add) + */ + tv_bit_mode = <1>; + }; + vdin1 { + compatible = "amlogic, vdin"; + memory-region = <&vdin1_cma_reserved>; + dev_name = "vdin1"; + status = "ok"; + reserve-iomap = "true"; + flag_cma = <0>;/*1:share with codec_mm;0:cma alone*/ + interrupts = <0 85 1>; + rdma-irq = <4>; + /*clocks = <&clock CLK_FPLL_DIV5>, + * <&clock CLK_VDIN_MEAS_CLK>; + *clock-names = "fclk_div5", "cts_vdin_meas_clk"; + */ + vdin_id = <1>; + /*vdin write mem color depth support: + *bit0:support 8bit + *bit1:support 9bit + *bit2:support 10bit + *bit3:support 12bit + */ + tv_bit_mode = <1>; + }; + + amlvecm { + compatible = "amlogic, vecm"; + dev_name = "aml_vecm"; + status = "okay"; + gamma_en = <0>;/*1:enabel ;0:disable*/ + wb_en = <0>;/*1:enabel ;0:disable*/ + cm_en = <0>;/*1:enabel ;0:disable*/ + /*1:enabel osd lut 100 table;0:disable*/ + cfg_en_osd_100 = <1>; + /*0: 709/601 1: bt2020*/ + tx_op_color_primary = <0>; + }; + + unifykey{ + compatible = "amlogic, unifykey"; + status = "ok"; + + unifykey-num = <15>; + unifykey-index-0 = <&keysn_0>; + unifykey-index-1 = <&keysn_1>; + unifykey-index-2 = <&keysn_2>; + unifykey-index-3 = <&keysn_3>; + unifykey-index-4 = <&keysn_4>; + unifykey-index-5 = <&keysn_5>; + unifykey-index-6 = <&keysn_6>; + unifykey-index-7 = <&keysn_7>; + unifykey-index-8 = <&keysn_8>; + unifykey-index-9 = <&keysn_9>; + unifykey-index-10= <&keysn_10>; + unifykey-index-11= <&keysn_11>; + unifykey-index-12= <&keysn_12>; + unifykey-index-13= <&keysn_13>; + unifykey-index-14= <&keysn_14>; + + keysn_0: key_0{ + key-name = "usid"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_1:key_1{ + key-name = "mac"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_2:key_2{ + key-name = "hdcp"; + key-device = "secure"; + key-type = "sha1"; + key-permit = "read","write","del"; + }; + keysn_3:key_3{ + key-name = "secure_boot_set"; + key-device = "efuse"; + key-permit = "write"; + }; + keysn_4:key_4{ + key-name = "mac_bt"; + key-device = "normal"; + key-permit = "read","write","del"; + key-type = "mac"; + }; + keysn_5:key_5{ + key-name = "mac_wifi"; + key-device = "normal"; + key-permit = "read","write","del"; + key-type = "mac"; + }; + keysn_6:key_6{ + key-name = "hdcp2_tx"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_7:key_7{ + key-name = "hdcp2_rx"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_8:key_8{ + key-name = "widevinekeybox"; + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_9:key_9{ + key-name = "deviceid"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_10:key_10{ + key-name = "hdcp22_fw_private"; + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_11:key_11{ + key-name = "PlayReadykeybox25"; + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_12:key_12{ + key-name = "prpubkeybox";// PlayReady + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_13:key_13{ + key-name = "prprivkeybox";// PlayReady + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_14:key_14{ + key-name = "attestationkeybox";// attestation key + key-device = "secure"; + key-permit = "read","write","del"; + }; + };//End unifykey + +}; +&efuse { + status = "ok"; +}; + +&pwm_ef { + status = "okay"; +}; + +&audio_data{ + status = "okay"; +}; +&spicc{ + status = "disabled"; + pinctrl-names = "spicc_pulldown","spicc_pullup"; + pinctrl-0 = <&spicc_pulldown_x8x9x11>; + pinctrl-1 = <&spicc_pullup_x8x9x11>; + num_chipselect = <1>; + cs-gpios = <&gpio GPIOX_10 GPIO_ACTIVE_HIGH>; + dma_en = <0>; + dma_tx_threshold = <3>; + dma_rx_threshold = <3>; + dma_num_per_read_burst = <3>; + dma_num_per_write_burst = <3>; + delay_control = <0x15>; + ssctl = <0>; +}; + diff --git a/arch/arm/boot/dts/amlogic/gxl_p212_2g.dts b/arch/arm/boot/dts/amlogic/gxl_p212_2g.dts index fcfbb3911c41..04e17f3a95f2 100644 --- a/arch/arm/boot/dts/amlogic/gxl_p212_2g.dts +++ b/arch/arm/boot/dts/amlogic/gxl_p212_2g.dts @@ -99,7 +99,7 @@ reusable; size = <0x7C00000>; alignment = <0x400000>; - alloc-ranges = <0x0 0x2ee00000>; + alloc-ranges = <0x30000000 0x50000000>; }; /* vdin0 CMA pool */ @@ -132,7 +132,7 @@ size = <0x13400000>; alignment = <0x400000>; linux,contiguous-region; - alloc-ranges = <0x12000000 0x13400000>; + alloc-ranges = <0x30000000 0x50000000>; }; picdec_cma_reserved:linux,picdec { compatible = "shared-dma-pool"; @@ -150,14 +150,14 @@ }; }; - dummy-battery { + amlogic_battery:dummy-battery { compatible = "amlogic, dummy-battery"; - status = "okay"; + status = "disabled"; }; - dummy-charger { + amlogic_charger:dummy-charger { compatible = "amlogic, dummy-charger"; - status = "okay"; + status = "disabled"; }; bt-dev{ @@ -1216,3 +1216,4 @@ &audio_data{ status = "okay"; }; + diff --git a/arch/arm/boot/dts/amlogic/gxl_p212_2g_buildroot.dts b/arch/arm/boot/dts/amlogic/gxl_p212_2g_buildroot.dts new file mode 100644 index 000000000000..d3c1a0fc2e63 --- /dev/null +++ b/arch/arm/boot/dts/amlogic/gxl_p212_2g_buildroot.dts @@ -0,0 +1,1248 @@ +/* + * arch/arm/boot/dts/amlogic/gxl_p212_2g.dts + * + * Copyright (C) 2017 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +/dts-v1/; + +#include +#include "mesongxl.dtsi" +#include "meson_drm.dtsi" +#include "mesongxl_p212-panel.dtsi" +/ { + model = "Amlogic"; + amlogic-dt-id = "gxl_p212_2g"; + compatible = "amlogic, Gxl"; + interrupt-parent = <&gic>; + #address-cells = <1>; + #size-cells = <1>; + + aliases { + serial0 = &uart_AO; + serial1 = &uart_A; + serial2 = &uart_B; + serial3 = &uart_C; + serial4 = &uart_AO_B; + }; + ion_dev { + compatible = "amlogic, ion_dev"; + memory-region = <&ion_reserved>; + }; + memory@00000000 { + device_type = "memory"; + linux,usable-memory = <0x0100000 0x7ff00000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + /* global autoconfigured region for contiguous allocations */ + secmon_reserved:linux,secmon { + compatible = "shared-dma-pool"; + reusable; + size = <0x400000>; + alignment = <0x400000>; + alloc-ranges = <0x05000000 0x400000>; + }; + secos_reserved:linux,secos { + status = "disable"; + compatible = "amlogic, aml_secos_memory"; + reg = <0x05300000 0x2000000>; + no-map; + }; + ion_reserved:linux,ion-dev { + compatible = "shared-dma-pool"; + reusable; + size = <0x8000000>; + alignment = <0x400000>; + }; + //don't put other dts in front of fb_reserved + + //di_reserved:linux,di { + // compatible = "amlogic, di-mem"; + /** 10x3133440=30M(0x1e) support 8bit **/ + // size = <0x1e00000>; + //no-map; + //}; + di_cma_reserved:linux,di_cma { + compatible = "shared-dma-pool"; + reusable; + /** 10x3133440=30M(0x1e) support 8bit **/ + size = <0x2000000>; + alignment = <0x400000>; + }; + /* vdin0 CMA pool */ + //vdin0_cma_reserved:linux,vdin0_cma { + // compatible = "shared-dma-pool"; + // linux,phandle = <4>; + // reusable; + /* 1920x1080x2x4 =16+4 M */ + // size = <0x01400000>; + // alignment = <0x400000>; + //}; + /* vdin1 CMA pool */ + vdin1_cma_reserved:linux,vdin1_cma { + compatible = "shared-dma-pool"; + reusable; + /* 1920x1080x2x4 =16 M */ + size = <0x01000000>; + alignment = <0x400000>; + }; + /* POST PROCESS MANAGER */ + ppmgr_reserved:linux,ppmgr { + compatible = "shared-dma-pool"; + size = <0x0>; + }; + + codec_mm_cma:linux,codec_mm_cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x10400000>; + alignment = <0x400000>; + linux,contiguous-region; + }; + picdec_cma_reserved:linux,picdec { + compatible = "shared-dma-pool"; + reusable; + size = <0x0>; + alignment = <0x0>; + linux,contiguous-region; + }; + /* codec shared reserved */ + codec_mm_reserved:linux,codec_mm_reserved { + compatible = "amlogic, codec-mm-reserved"; + size = <0x0>; + alignment = <0x100000>; + //no-map; + }; + }; + + bt-dev{ + compatible = "amlogic, bt-dev"; + dev_name = "bt-dev"; + status = "okay"; + gpio_reset = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>; + }; + + wifi{ + compatible = "amlogic, aml_wifi"; + dev_name = "aml_wifi"; + status = "okay"; + interrupt_pin = <&gpio GPIOX_7 GPIO_ACTIVE_HIGH>; + irq_trigger_type = "GPIO_IRQ_LOW"; + dhd_static_buf; //dhd_static_buf support + power_on_pin = <&gpio GPIOX_6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_32k_pins>; + pwm_config = <&wifi_pwm_conf>; + }; + + wifi_pwm_conf:wifi_pwm_conf{ + pwm_channel1_conf { + pwms = <&pwm_ef MESON_PWM_0 30040 0>; + duty-cycle = <15020>; + times = <8>; + }; + pwm_channel2_conf { + pwms = <&pwm_ef MESON_PWM_2 30030 0>; + duty-cycle = <15015>; + times = <12>; + }; + }; + + sd_emmc_c: emmc@d0074000 { + status = "okay"; + compatible = "amlogic, meson-mmc-gxl"; + reg = <0xd0074000 0x2000>; + interrupts = <0 218 1>; + pinctrl-names = "emmc_clk_cmd_pins", "emmc_all_pins"; + pinctrl-0 = <&emmc_clk_cmd_pins>; + pinctrl-1 = <&emmc_conf_pull_up &emmc_conf_pull_done>; + clocks = <&clkc CLKID_SD_EMMC_C>, + <&clkc CLKID_SD_EMMC_C_P0_COMP>, + <&clkc CLKID_FCLK_DIV2>; + clock-names = "core", "clkin0", "clkin1"; + + bus-width = <8>; + cap-sd-highspeed; + cap-mmc-highspeed; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + + max-frequency = <200000000>; + non-removable; + disable-wp; + emmc { + pinname = "emmc"; + ocr_avail = <0x200080>; /**VDD voltage 3.3 ~ 3.4 */ + caps = "MMC_CAP_8_BIT_DATA", + "MMC_CAP_MMC_HIGHSPEED", + "MMC_CAP_SD_HIGHSPEED", + "MMC_CAP_NONREMOVABLE", + "MMC_CAP_1_8V_DDR", + "MMC_CAP_HW_RESET", + "MMC_CAP_ERASE", + "MMC_CAP_CMD23"; + caps2 = "MMC_CAP2_HS200", "MMC_CAP2_HS400"; + f_min = <400000>; + f_max = <100000000>; + max_req_size = <0x20000>; /**128KB*/ + gpio_dat3 = <&gpio BOOT_3 GPIO_ACTIVE_HIGH>; + hw_reset = <&gpio BOOT_9 GPIO_ACTIVE_HIGH>; + card_type = <1>; + /* 1:mmc card(include eMMC), + * 2:sd card(include tSD) + */ + }; + }; + + sd_emmc_b:sd@d0072000 { + status = "okay"; + compatible = "amlogic, meson-mmc-gxl"; + reg = <0xd0072000 0x2000>; + interrupts = <0 217 1>; + pinctrl-names = "sd_all_pins", + "sd_clk_cmd_pins", + "sd_1bit_pins", + "sd_clk_cmd_uart_pins", + "sd_1bit_uart_pins", + "sd_to_ao_uart_pins", + "ao_to_sd_uart_pins", + "ao_to_sd_jtag_pins", + "sd_to_ao_jtag_pins"; + pinctrl-0 = <&sd_all_pins>; + pinctrl-1 = <&sd_clk_cmd_pins>; + pinctrl-2 = <&sd_1bit_pins>; + pinctrl-3 = <&sd_to_ao_uart_clr_pins + &sd_clk_cmd_pins &ao_to_sd_uart_pins>; + pinctrl-4 = <&sd_to_ao_uart_clr_pins + &sd_1bit_pins &ao_to_sd_uart_pins>; + pinctrl-5 = <&sd_all_pins &sd_to_ao_uart_pins>; + pinctrl-6 = <&sd_to_ao_uart_clr_pins &ao_to_sd_uart_pins>; + pinctrl-7 = <&sd_to_ao_uart_clr_pins &ao_to_sd_uart_pins>; + pinctrl-8 = <&sd_all_pins &sd_to_ao_uart_pins>; + clocks = <&clkc CLKID_SD_EMMC_B>, + <&clkc CLKID_SD_EMMC_B_P0_COMP>, + <&clkc CLKID_FCLK_DIV2>; + clock-names = "core", "clkin0", "clkin1"; + + bus-width = <4>; + cap-sd-highspeed; + max-frequency = <100000000>; + disable-wp; + sd { + pinname = "sd"; + ocr_avail = <0x200080>; /**VDD voltage 3.3 ~ 3.4 */ + caps = "MMC_CAP_4_BIT_DATA", + "MMC_CAP_MMC_HIGHSPEED", + "MMC_CAP_SD_HIGHSPEED"; + /* "MMC_CAP_UHS_SDR12", + * "MMC_CAP_UHS_SDR25", + * "MMC_CAP_UHS_SDR50", + * "MMC_CAP_UHS_SDR104"; + */ + f_min = <400000>; + f_max = <100000000>; + max_req_size = <0x20000>; /**128KB*/ + gpio_dat3 = <&gpio CARD_4 GPIO_ACTIVE_HIGH>; + jtag_pin = <&gpio CARD_0 GPIO_ACTIVE_HIGH>; + gpio_cd = <&gpio CARD_6 GPIO_ACTIVE_HIGH>; + card_type = <5>; + /* 0:unknown, + * 1:mmc card(include eMMC), + * 2:sd card(include tSD), + * 3:sdio device(ie:sdio-wifi), + * 4:SD combo (IO+mem) card, + * 5:NON sdio device(means sd/mmc card), + * other:reserved + */ + }; + }; + + sd_emmc_a:sdio@d0070000 { + status = "okay"; + compatible = "amlogic, meson-mmc-gxl"; + reg = <0xd0070000 0x2000>; + interrupts = <0 216 4>; + pinctrl-names = "sdio_clk_cmd_pins", "sdio_all_pins"; + pinctrl-0 = <&sdio_clk_cmd_pins>; + pinctrl-1 = <&sdio_all_pins>; + clocks = <&clkc CLKID_SD_EMMC_A>, + <&clkc CLKID_SD_EMMC_A_P0_COMP>, + <&clkc CLKID_FCLK_DIV2>; + clock-names = "core", "clkin0", "clkin1"; + + bus-width = <4>; + cap-sd-highspeed; + cap-mmc-highspeed; + max-frequency = <100000000>; + non-removable; + disable-wp; + sdio { + pinname = "sdio"; + ocr_avail = <0x200080>; /**VDD voltage 3.3 ~ 3.4 */ + caps = "MMC_CAP_4_BIT_DATA", + "MMC_CAP_MMC_HIGHSPEED", + "MMC_CAP_SD_HIGHSPEED", + "MMC_CAP_NONREMOVABLE", + "MMC_CAP_UHS_SDR12", + "MMC_CAP_UHS_SDR25", + "MMC_CAP_UHS_SDR50", + "MMC_CAP_UHS_SDR104", + "MMC_PM_KEEP_POWER", + "MMC_CAP_SDIO_IRQ"; + f_min = <400000>; + f_max = <200000000>; + max_req_size = <0x20000>; /**128KB*/ + card_type = <3>; + /* 3:sdio device(ie:sdio-wifi), + * 4:SD combo (IO+mem) card + */ + }; + }; + mtd_nand{ + compatible = "amlogic, aml_mtd_nand"; + dev_name = "mtdnand"; + status = "disabled"; + reg = <0xd0074800 0x200>; + interrupts = < 0 34 1 >; + pinctrl-names = "nand_rb_mod","nand_norb_mod", "nand_cs_only"; + pinctrl-0 = <&all_nand_pins>; + pinctrl-1 = <&all_nand_pins>; + pinctrl-2 = <&nand_cs_pins>; + device_id = <0>; + plat-names = "bootloader","nandnormal"; + plat-num = <2>; + plat-part-0 = <&bootloader>; + plat-part-1 = <&nandnormal>; + bootloader: bootloader{ + enable_pad ="ce0"; + busy_pad = "rb0"; + timming_mode = "mode5"; + bch_mode = "bch60_1k"; + t_rea = <20>; + t_rhoh = <15>; + chip_num = <1>; + part_num = <0>; + rb_detect = <1>; + }; + nandnormal: nandnormal{ + enable_pad ="ce0","ce1"; + busy_pad = "rb0","rb1"; + timming_mode = "mode5"; + bch_mode = "bch60_1k"; + plane_mode = "twoplane"; + t_rea = <20>; + t_rhoh = <15>; + chip_num = <2>; + part_num = <3>; + partition = <&nand_partitions>; + rb_detect = <1>; + }; + nand_partitions:nand_partition{ + logo{ + offset=<0x0 0x0>; + size=<0x0 0x200000>; + }; + recovery{ + offset=<0x0 0x0>; + size=<0x0 0x1000000>; + }; + boot{ + offset=<0x0 0x0>; + size=<0x0 0xC00000>; + }; + system{ + offset=<0x0 0x0>; + size=<0x0 0xDC40000>; + }; + data{ + offset=<0xffffffff 0xffffffff>; + size=<0x0 0x0>; + }; + }; + }; + + ethmac: ethernet@0xc9410000 { + compatible = "amlogic, gxbb-eth-dwmac"; + reg = <0xc9410000 0x10000 + 0xc8834540 0x8 + 0xc8834558 0xc>; + interrupts = <0 8 1>; + pinctrl-names = "external_eth_pins"; + pinctrl-0 = <&external_eth_pins>; + rst_pin-gpios = <&gpio GPIOZ_14 0>; + GPIOZ4_pin-gpios = <&gpio GPIOZ_4 0>; + GPIOZ5_pin-gpios = <&gpio GPIOZ_5 0>; + mc_val_internal_phy = <0x1800>; + mc_val_external_phy = <0x1621>; + cali_val = <0x20000>; + interrupt-names = "macirq"; + clocks = <&clkc CLKID_ETH>; + clock-names = "ethclk81"; + internal_phy=<1>; + }; + + codec_io { + compatible = "amlogic, codec_io"; + #address-cells=<1>; + #size-cells=<1>; + ranges; + io_cbus_base{ + reg = <0xC1100000 0x100000>; + }; + io_dos_base{ + reg = <0xc8820000 0x10000>; + }; + io_hiubus_base{ + reg = <0xc883c000 0x2000>; + }; + io_aobus_base{ + reg = <0xc8100000 0x100000>; + }; + io_vcbus_base{ + reg = <0xd0100000 0x40000>; + }; + io_dmc_base{ + reg = <0xc8838000 0x400>; + }; + }; + + codec_mm { + compatible = "amlogic, codec, mm"; + memory-region = <&codec_mm_cma &codec_mm_reserved>; + dev_name = "codec_mm"; + status = "okay"; + }; + + canvas{ + compatible = "amlogic, meson, canvas"; + dev_name = "amlogic-canvas"; + status = "ok"; + reg = <0xc8838000 0x400>; + }; + + mesonstream { + compatible = "amlogic, codec, streambuf"; + dev_name = "mesonstream"; + status = "okay"; + clocks = <&clkc CLKID_DOS_PARSER + &clkc CLKID_DEMUX + &clkc CLKID_DOS + &clkc CLKID_CLK81 + &clkc CLKID_VDEC_MUX + &clkc CLKID_HCODEC_MUX + &clkc CLKID_HEVC_MUX>; + clock-names = "parser_top", + "demux", + "vdec", + "clk_81", + "clk_vdec_mux", + "clk_hcodec_mux", + "clk_hevc_mux"; + }; + + vdec { + compatible = "amlogic, vdec"; + dev_name = "vdec.0"; + status = "okay"; + interrupts = <0 3 1 + 0 23 1 + 0 32 1 + 0 43 1 + 0 44 1 + 0 45 1>; + interrupt-names = "vsync", + "demux", + "parser", + "mailbox_0", + "mailbox_1", + "mailbox_2"; + }; + + aml_sensor0: aml-sensor@0 { + compatible = "amlogic, aml-thermal"; + device_name = "thermal"; + #thermal-sensor-cells = <1>; + cooling_devices { + cpufreq_cool_cluster0 { + min_state = <1000000>; + dyn_coeff = <140>; + cluster_id = <0>; + node_name = "cpufreq_cool0"; + device_type = "cpufreq"; + }; + cpucore_cool_cluster0 { + min_state = <1>; + dyn_coeff = <0>; + cluster_id = <0>; + node_name = "cpucore_cool0"; + device_type = "cpucore"; + }; + gpufreq_cool { + min_state = <400>; + dyn_coeff = <437>; + cluster_id = <0>; + node_name = "gpufreq_cool0"; + device_type = "gpufreq"; + }; + gpucore_cool { + min_state = <1>; + dyn_coeff = <0>; + cluster_id = <0>; + node_name = "gpucore_cool0"; + device_type = "gpucore"; + }; + }; + cpufreq_cool0:cpufreq_cool0 { + #cooling-cells = <2>; /* min followed by max */ + }; + cpucore_cool0:cpucore_cool0 { + #cooling-cells = <2>; /* min followed by max */ + }; + gpufreq_cool0:gpufreq_cool0 { + #cooling-cells = <2>; /* min followed by max */ + }; + gpucore_cool0:gpucore_cool0 { + #cooling-cells = <2>; /* min followed by max */ + }; + }; + thermal-zones { + soc_thermal { + polling-delay = <1000>; + polling-delay-passive = <100>; + sustainable-power = <2150>; + + thermal-sensors = <&aml_sensor0 3>; + + trips { + switch_on: trip-point@0 { + temperature = <70000>; + hysteresis = <1000>; + type = "passive"; + }; + control: trip-point@1 { + temperature = <80000>; + hysteresis = <1000>; + type = "passive"; + }; + hot: trip-point@2 { + temperature = <85000>; + hysteresis = <5000>; + type = "hot"; + }; + critical: trip-point@3 { + temperature = <260000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + + cooling-maps { + cpufreq_cooling_map { + trip = <&control>; + cooling-device = <&cpufreq_cool0 0 4>; + contribution = <1024>; + }; + cpucore_cooling_map { + trip = <&control>; + cooling-device = <&cpucore_cool0 0 3>; + contribution = <1024>; + }; + gpufreq_cooling_map { + trip = <&control>; + cooling-device = <&gpufreq_cool0 0 4>; + contribution = <1024>; + }; + gpucore_cooling_map { + trip = <&control>; + cooling-device = <&gpucore_cool0 0 2>; + contribution = <1024>; + }; + }; + }; + }; + + dwc3: dwc3@c9000000 { + compatible = "synopsys, dwc3"; + reg = <0xc9000000 0x100000>; + interrupts = <0 30 4>; + usb-phy = <&usb2_phy>, <&usb3_phy>; + cpu-type = "gxl"; + clock-src = "usb3.0"; + }; + + usb2_phy: usb2phy@d0078000 { + compatible = "amlogic, amlogic-new-usb2"; + portnum = <3>; + reg = <0xd0078000 0x80 + 0xc1104408 0x4>; + }; + + usb3_phy: usb3phy@d0078080 { + compatible = "amlogic, amlogic-new-usb3"; + portnum = <0>; + reg = <0xd0078080 0x20>; + }; + + dwc2_a { + compatible = "amlogic, dwc2"; + device_name = "dwc2_a"; + reg = <0xc9100000 0x40000>; + status = "okay"; + interrupts = <0 31 4>; + pl-periph-id = <0>; /** lm name */ + clock-src = "usb0"; /** clock src */ + port-id = <0>; /** ref to mach/usb.h */ + port-type = <2>; /** 0: otg, 1: host, 2: slave */ + port-speed = <0>; /** 0: default, high, 1: full */ + port-config = <0>; /** 0: default */ + port-dma = <0>; /** 0: default ... 6: disable*/ + port-id-mode = <0>; /** 0: hardware, 1: sw_host, 2: sw_slave*/ + usb-fifo = <728>; + cpu-type = "gxl"; + controller-type = <1>; /** 0: normal, 1: host, 2: device*/ + phy-reg = <0xd0078000>; + phy-reg-size = <0xa0>; + clocks = <&clkc CLKID_USB_GENERAL + &clkc CLKID_USB1_TO_DDR + &clkc CLKID_USB1>; + clock-names = "usb_general", + "usb1", + "usb1_to_ddr"; + }; + + meson-amvideom { + compatible = "amlogic, amvideom"; + dev_name = "amvideom"; + status = "okay"; + interrupts = <0 3 1>; + interrupt-names = "vsync"; + }; + + vout { + compatible = "amlogic, vout"; + dev_name = "vout"; + status = "okay"; + fr_auto_policy = <0>; + }; + + cvbsout { + compatible = "amlogic, cvbsout-gxl"; + dev_name = "cvbsout"; + status = "okay"; + clocks = <&clkc CLKID_VCLK2_ENCI + &clkc CLKID_VCLK2_VENCI0 + &clkc CLKID_VCLK2_VENCI1 + &clkc CLKID_DAC_CLK>; + clock-names = "venci_top_gate", + "venci_0_gate", + "venci_1_gate", + "vdac_clk_gate"; + + /* performance: reg_address, reg_value */ + /* s905x */ + performance = <0x1bf0 0x9 + 0x1b56 0x343 + 0x1b12 0x8080 + 0x1b05 0xfd + 0x1c59 0xf752 + 0xffff 0x0>; /* ending flag */ + }; + + amhdmitx: amhdmitx{ + compatible = "amlogic, amhdmitx"; + dev_name = "amhdmitx"; + status = "okay"; + vend-data = <&vend_data>; + pinctrl-names="hdmitx_hpd", "hdmitx_ddc"; + pinctrl-0=<&hdmitx_hpd>; + pinctrl-1=<&hdmitx_ddc>; + /* HPD, 57 + 32 = 89; CEC, 151 + 32 = 183*/ + interrupts = <0 57 1>; + interrupt-names = "hdmitx_hpd"; + /* 0:M8B 1:GXBB 2:GXTVBB 3:GXL 4:GXM + * 5:TXL 6:TXLX 7:AXG 8:GXLX 9:TXHD + */ + ic_type = <3>; + vend_data: vend_data{ /* Should modified by Customer */ + vendor_name = "Amlogic"; /* Max Chars: 8 */ + /* standards.ieee.org/develop/regauth/oui/oui.txt */ + vendor_id = <0x000000>; + product_desc = "MBox Meson Ref"; /* Max Chars: 16 */ + }; + }; + + aocec: aocec{ + compatible = "amlogic, amlogic-aocec"; + device_name = "aocec"; + status = "okay"; + vendor_id = <0x000000>; + cec_osd_string = "MBox"; /* Max Chars: 14 */ + cec_version = <6>; /* 5: 1.4, 6: 2.0 */ + port_num = <1>; + arc_port_mask = <0x0>; + interrupts = <0 199 1>; + interrupt-names = "hdmi_aocec"; + pinctrl-names = "default"; + pinctrl-0=<&hdmitx_aocec>; + reg = <0xc810023c 0x4 + 0xc8100000 0x200>; + reg-names = "ao_exit","ao"; + }; + + sysled { + compatible = "amlogic, sysled"; + dev_name = "sysled"; + status = "disabled"; + led_gpio = <&gpio GPIODV_24 GPIO_ACTIVE_HIGH>; + led_active_low = <1>; + }; + + meson-fb { + compatible = "amlogic, meson-gxl"; + dev_name = "meson-fb"; + status = "okay"; + interrupts = <0 3 1 + 0 89 1>; + interrupt-names = "viu-vsync", "rdma"; + mem_size = <0x00800000 0x1800000 0x00100000>; + /* uboot logo,fb0/fb1 memory size,if afbcd fb0=0x01851000 */ + display_mode_default = "1080p60hz"; + scale_mode = <1>; + /** 0:VPU free scale 1:OSD free scale 2:OSD super scale */ + display_size_default = <1920 1080 1920 3240 32>; + /*1920*1080*4*3 = 0x17BB000*/ + mem_alloc = <1>; + logo_addr = "0x7dc00000"; + }; + ge2d { + compatible = "amlogic, ge2d-gxl"; + dev_name = "ge2d"; + status = "okay"; + interrupts = <0 150 1>; + interrupt-names = "ge2d"; + clocks = <&clkc CLKID_VAPB_MUX>, + <&clkc CLKID_G2D>, + <&clkc CLKID_GE2D_GATE>; + clock-names = "clk_vapb_0", + "clk_ge2d", + "clk_ge2d_gate"; + }; + + + /* AUDIO MESON DEVICES */ + i2s_dai: I2S { + #sound-dai-cells = <0>; + compatible = "amlogic, aml-i2s-dai"; + clocks = + <&clkc CLKID_MPLL2>, + <&clkc CLKID_AMCLK_COMP>, + <&clkc CLKID_AIU_GLUE>, + <&clkc CLKID_IEC958>, + <&clkc CLKID_I2S_OUT>, + <&clkc CLKID_AMCLK>, + <&clkc CLKID_AIFIFO2>, + <&clkc CLKID_MIXER>, + <&clkc CLKID_MIXER_IFACE>, + <&clkc CLKID_ADC>, + <&clkc CLKID_AIU_TOP>, + <&clkc CLKID_AOCLK_GATE>, + <&clkc CLKID_I2S_SPDIF>; + clock-names = + "mpll", + "mclk", + "top_glue", + "aud_buf", + "i2s_out", + "amclk_measure", + "aififo2", + "aud_mixer", + "mixer_reg", + "adc", + "top_level", + "aoclk", + "aud_in"; + i2s_pos_sync = <0>; + /*DMIC;*/ /* I2s Mic or Dmic, default for I2S mic */ + }; + dmic:snd_dmic { + #sound-dai-cells = <0>; + compatible = "aml, aml_snd_dmic"; + reg = <0xd0042000 0x2000>; + status = "disabled"; + resets = < + &clkc CLKID_PDM_GATE + >; + reset-names = "pdm"; + pinctrl-names = "audio_dmic"; + pinctrl-0 = <&aml_dmic_pins>; + clocks = <&clkc CLKID_PDM_COMP>, + <&clkc CLKID_AMCLK_COMP>; + clock-names = "pdm", "mclk"; + }; + spdif_dai: SPDIF { + #sound-dai-cells = <0>; + compatible = "amlogic, aml-spdif-dai"; + clocks = + <&clkc CLKID_MPLL1>, + <&clkc CLKID_I958_COMP>, + <&clkc CLKID_AMCLK_COMP>, + <&clkc CLKID_I958_COMP_SPDIF>, + <&clkc CLKID_CLK81>, + <&clkc CLKID_IEC958>, + <&clkc CLKID_IEC958_GATE>; + clock-names = + "mpll1", + "i958", + "mclk", + "spdif", + "clk_81", + "iec958", + "iec958_amclk"; + }; + pcm_dai: PCM { + #sound-dai-cells = <0>; + compatible = "amlogic, aml-pcm-dai"; + pinctrl-names = "audio_pcm"; + pinctrl-0 = <&audio_pcm_pins>; + clocks = + <&clkc CLKID_MPLL0>, + <&clkc CLKID_PCM_MCLK_COMP>, + <&clkc CLKID_PCM_SCLK_GATE>; + clock-names = + "mpll0", + "pcm_mclk", + "pcm_sclk"; + pcm_mode = <1>; /* 0=slave mode, 1=master mode */ + }; + i2s_plat: i2s_platform { + compatible = "amlogic, aml-i2s"; + interrupts = <0 29 1>; + }; + pcm_plat: pcm_platform { + compatible = "amlogic, aml-pcm"; + }; + spdif_codec: spdif_codec{ + #sound-dai-cells = <0>; + compatible = "amlogic, aml-spdif-codec"; + pinctrl-names = "audio_spdif"; + pinctrl-0 = <&audio_spdif_pins>; + }; + pcm_codec: pcm_codec{ + #sound-dai-cells = <0>; + compatible = "amlogic, pcm2BT-codec"; + }; + /* endof AUDIO MESON DEVICES */ + + /* AUDIO board specific */ + dummy_codec:dummy{ + #sound-dai-cells = <0>; + compatible = "amlogic, aml_dummy_codec"; + status = "disable"; + }; + amlogic_codec:t9015{ + #sound-dai-cells = <0>; + compatible = "amlogic, aml_codec_T9015"; + reg = <0xc8832000 0x14>; + status = "okay"; + }; + aml_sound_meson { + compatible = "aml, meson-snd-card"; + status = "okay"; + aml-sound-card,format = "i2s"; + aml_sound_card,name = "AML-MESONAUDIO"; + aml,audio-routing = + "Ext Spk","LOUTL", + "Ext Spk","LOUTR"; + + mute_gpio-gpios = <&gpio GPIOH_5 0>; + mute_inv; + hp_disable; + hp_paraments = <800 300 0 5 1>; + pinctrl-names = "audio_i2s"; + pinctrl-0 = <&audio_i2s_pins>; + cpu_list = <&cpudai0 &cpudai1 &cpudai2>; + codec_list = <&codec0 &codec1 &codec2>; + plat_list = <&i2s_plat &i2s_plat &pcm_plat>; + cpudai0: cpudai0 { + sound-dai = <&i2s_dai>; + }; + cpudai1: cpudai1 { + sound-dai = <&spdif_dai>; + }; + cpudai2: cpudai2 { + sound-dai = <&pcm_dai>; + }; + codec0: codec0 { + sound-dai = <&amlogic_codec>; + }; + codec1: codec1 { + sound-dai = <&spdif_codec>; + }; + codec2: codec2 { + sound-dai = <&pcm_codec>; + }; + }; + /* END OF AUDIO board specific */ + rdma{ + compatible = "amlogic, meson, rdma"; + dev_name = "amlogic-rdma"; + status = "ok"; + interrupts = <0 89 1>; + interrupt-names = "rdma"; + }; + + amvenc_avc{ + compatible = "amlogic, amvenc_avc"; + dev_name = "amvenc_avc"; + status = "okay"; + interrupts = <0 45 1>; + interrupt-names = "mailbox_2"; + }; + + hevc_enc{ + compatible = "cnm, HevcEnc"; + dev_name = "HevcEnc"; + status = "okay"; + interrupts = <0 187 1>; + interrupt-names = "wave420l_irq"; + #address-cells=<1>; + #size-cells=<1>; + ranges; + io_reg_base{ + reg = <0xc8810000 0x4000>; + }; + }; + + partitions: partitions{ + parts = <12>; + part-0 = <&logo>; + part-1 = <&recovery>; + part-2 = <&rsv>; + part-3 = <&tee>; + part-4 = <&crypt>; + part-5 = <&misc>; + part-6 = <&boot>; + part-7 = <&system>; + part-8 = <&cache>; + part-9 = <&vendor>; + part-10 = <&odm>; + part-11 = <&data>; + + logo:logo{ + pname = "logo"; + size = <0x0 0x2000000>; + mask = <1>; + }; + recovery:recovery{ + pname = "recovery"; + size = <0x0 0x2000000>; + mask = <1>; + }; + rsv:rsv{ + pname = "rsv"; + size = <0x0 0x800000>; + mask = <1>; + }; + tee:tee{ + pname = "tee"; + size = <0x0 0x800000>; + mask = <1>; + }; + crypt:crypt{ + pname = "crypt"; + size = <0x0 0x2000000>; + mask = <1>; + }; + misc:misc{ + pname = "misc"; + size = <0x0 0x2000000>; + mask = <1>; + }; + boot:boot + { + pname = "boot"; + size = <0x0 0x2000000>; + mask = <1>; + }; + system:system + { + pname = "system"; + size = <0x0 0x80000000>; + mask = <1>; + }; + vendor:vendor + { + pname = "vendor"; + size = <0x0 0x10000000>; + mask = <1>; + }; + odm:odm + { + pname = "odm"; + size = <0x0 0x10000000>; + mask = <1>; + }; + cache:cache + { + pname = "cache"; + size = <0x0 0x20000000>; + mask = <2>; + }; + data:data + { + pname = "data"; + size = <0xffffffff 0xffffffff>; + mask = <4>; + }; + }; + + ppmgr { + compatible = "amlogic, ppmgr"; + memory-region = <&ppmgr_reserved>; + dev_name = "ppmgr"; + status = "okay"; + }; + + deinterlace { + compatible = "amlogic, deinterlace"; + status = "okay"; + flag_cma = <1>;/*0:use reserved;1:use cma*/ + //memory-region = <&di_reserved>; + memory-region = <&di_cma_reserved>; + interrupts = <0 46 1 0 6 1>; + interrupt-names = "de_irq", "timerc"; + /* + * nr_size(byte) = 1920*544*2(yuv422 8bit) | + * 1920*544*2*12/8(yuv422 10bit) + * | 1920*544*2*10/8(yuv422 10bit full pack mode) + */ + /* mtn_size(byte) = 1920*544/2 */ + /* count_size(byte) = 1920*544/2 */ + buffer-size = <3133440>; + hw-version = <2>; + }; + + ionvideo { + compatible = "amlogic, ionvideo"; + dev_name = "ionvideo"; + status = "okay"; + }; + + amlvideo { + compatible = "amlogic, amlvideo"; + dev_name = "amlvideo"; + status = "okay"; + }; + + amlvideo2_0 { + compatible = "amlogic, amlvideo2"; + dev_name = "amlvideo2"; + status = "okay"; + amlvideo2_id = <0>; + cma_mode = <1>; + }; + + amlvideo2_1 { + compatible = "amlogic, amlvideo2"; + dev_name = "amlvideo2"; + status = "okay"; + amlvideo2_id = <1>; + cma_mode = <1>; + }; + + /*if you want to use vdin just modify status to "ok"*/ + vdin0 { + compatible = "amlogic, vdin"; + /*memory-region = <&vdin0_cma_reserved>;*/ + dev_name = "vdin0"; + status = "ok"; + reserve-iomap = "true"; + flag_cma = <1>;/*1:share with codec_mm;2:cma alone*/ + /*MByte, if 10bit disable: 64M(YUV422), + *if 10bit enable: 64*1.5 = 96M(YUV422) + *if support 4K2K-YUV444-10bit-WR:3840*2160*4*4 ~= 128M + *if support 4K2K-YUV422-10bit-wr:3840*2160*3*4 ~= 96M + *if support 4K2K-YUV422-8BIT-WR:3840*2160*2*4 ~= 64M + *if support 1080p-YUV422-8BIT-WR:1920*1080*2*4 ~= 16M + */ + cma_size = <16>; + interrupts = <0 83 1>; + rdma-irq = <2>; + /*clocks = <&clock CLK_FPLL_DIV5>, + * <&clock CLK_VDIN_MEAS_CLK>; + *clock-names = "fclk_div5", "cts_vdin_meas_clk"; + */ + vdin_id = <0>; + /*vdin write mem color depth support: + *bit0:support 8bit + *bit1:support 9bit + *bit2:support 10bit + *bit3:support 12bit + *bit4:support yuv422 10bit full pack mode (from txl new add) + */ + tv_bit_mode = <1>; + }; + vdin1 { + compatible = "amlogic, vdin"; + memory-region = <&vdin1_cma_reserved>; + dev_name = "vdin1"; + status = "ok"; + reserve-iomap = "true"; + flag_cma = <0>;/*1:share with codec_mm;0:cma alone*/ + interrupts = <0 85 1>; + rdma-irq = <4>; + /*clocks = <&clock CLK_FPLL_DIV5>, + * <&clock CLK_VDIN_MEAS_CLK>; + *clock-names = "fclk_div5", "cts_vdin_meas_clk"; + */ + vdin_id = <1>; + /*vdin write mem color depth support: + *bit0:support 8bit + *bit1:support 9bit + *bit2:support 10bit + *bit3:support 12bit + */ + tv_bit_mode = <1>; + }; + + amlvecm { + compatible = "amlogic, vecm"; + dev_name = "aml_vecm"; + status = "okay"; + gamma_en = <0>;/*1:enabel ;0:disable*/ + wb_en = <0>;/*1:enabel ;0:disable*/ + cm_en = <0>;/*1:enabel ;0:disable*/ + /*1:enabel osd lut 100 table;0:disable*/ + cfg_en_osd_100 = <1>; + /*0: 709/601 1: bt2020*/ + tx_op_color_primary = <0>; + }; + + unifykey{ + compatible = "amlogic, unifykey"; + status = "ok"; + + unifykey-num = <15>; + unifykey-index-0 = <&keysn_0>; + unifykey-index-1 = <&keysn_1>; + unifykey-index-2 = <&keysn_2>; + unifykey-index-3 = <&keysn_3>; + unifykey-index-4 = <&keysn_4>; + unifykey-index-5 = <&keysn_5>; + unifykey-index-6 = <&keysn_6>; + unifykey-index-7 = <&keysn_7>; + unifykey-index-8 = <&keysn_8>; + unifykey-index-9 = <&keysn_9>; + unifykey-index-10= <&keysn_10>; + unifykey-index-11= <&keysn_11>; + unifykey-index-12= <&keysn_12>; + unifykey-index-13= <&keysn_13>; + unifykey-index-14= <&keysn_14>; + + keysn_0: key_0{ + key-name = "usid"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_1:key_1{ + key-name = "mac"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_2:key_2{ + key-name = "hdcp"; + key-device = "secure"; + key-type = "sha1"; + key-permit = "read","write","del"; + }; + keysn_3:key_3{ + key-name = "secure_boot_set"; + key-device = "efuse"; + key-permit = "write"; + }; + keysn_4:key_4{ + key-name = "mac_bt"; + key-device = "normal"; + key-permit = "read","write","del"; + key-type = "mac"; + }; + keysn_5:key_5{ + key-name = "mac_wifi"; + key-device = "normal"; + key-permit = "read","write","del"; + key-type = "mac"; + }; + keysn_6:key_6{ + key-name = "hdcp2_tx"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_7:key_7{ + key-name = "hdcp2_rx"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_8:key_8{ + key-name = "widevinekeybox"; + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_9:key_9{ + key-name = "deviceid"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_10:key_10{ + key-name = "hdcp22_fw_private"; + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_11:key_11{ + key-name = "PlayReadykeybox25"; + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_12:key_12{ + key-name = "prpubkeybox";// PlayReady + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_13:key_13{ + key-name = "prprivkeybox";// PlayReady + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_14:key_14{ + key-name = "attestationkeybox";// attestation key + key-device = "secure"; + key-permit = "read","write","del"; + }; + };//End unifykey +}; +&efuse { + status = "ok"; +}; + +&pwm_ef { + status = "okay"; +}; + +&audio_data{ + status = "okay"; +}; + diff --git a/arch/arm/boot/dts/amlogic/gxl_p230_2g.dts b/arch/arm/boot/dts/amlogic/gxl_p230_2g.dts new file mode 100644 index 000000000000..5c8314d53d9a --- /dev/null +++ b/arch/arm/boot/dts/amlogic/gxl_p230_2g.dts @@ -0,0 +1,1352 @@ +/* + * arch/arm/boot/dts/amlogic/gxl_p230_2g.dts + * + * Copyright (C) 2017 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +/dts-v1/; + +#include +#include "mesongxl.dtsi" +#include "partition_mbox_ab.dtsi" +/ { + model = "Amlogic"; + amlogic-dt-id = "gxl_p230_2g"; + compatible = "amlogic,gxl"; + interrupt-parent = <&gic>; + #address-cells = <1>; + #size-cells = <1>; + + aliases { + serial0 = &uart_AO; + serial1 = &uart_A; + serial2 = &uart_B; + serial3 = &uart_C; + serial4 = &uart_AO_B; + }; + + ion_dev { + compatible = "amlogic, ion_dev"; + memory-region = <&ion_reserved>; + }; + + memory@00000000 { + device_type = "memory"; + linux,usable-memory = <0x0100000 0x7ff00000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + /* global autoconfigured region for contiguous allocations */ + ramoops@0x07400000 { + compatible = "ramoops"; + reg = <0x07400000 0x00100000>; + record-size = <0x8000>; + console-size = <0x8000>; + ftrace-size = <0x0>; + pmsg-size = <0x8000>; + }; + secmon_reserved:linux,secmon { + compatible = "shared-dma-pool"; + reusable; + size = <0x400000>; + alignment = <0x400000>; + alloc-ranges = <0x05000000 0x400000>; + }; + secos_reserved:linux,secos { + status = "disable"; + compatible = "amlogic, aml_secos_memory"; + reg = <0x05300000 0x2000000>; + no-map; + }; + logo_reserved:linux,meson-fb { + compatible = "shared-dma-pool"; + reusable; + size = <0x800000>; + alignment = <0x400000>; + alloc-ranges = <0x7f800000 0x800000>; + }; + //don't put other dts in front of logo_reserved + + //di_reserved:linux,di { + // compatible = "amlogic, di-mem"; + /** 10x3133440=30M(0x1e) support 8bit **/ + // size = <0x1e00000>; + //no-map; + //}; + di_cma_reserved:linux,di_cma { + compatible = "shared-dma-pool"; + reusable; + /** 10x3133440=30M(0x1e) support 8bit **/ + size = <0x2000000>; + alignment = <0x400000>; + }; + ion_reserved:linux,ion-dev { + compatible = "shared-dma-pool"; + reusable; + size = <0x7C00000>; + alignment = <0x400000>; + alloc-ranges = <0x30000000 0x50000000>; + }; + + /* vdin0 CMA pool */ + //vdin0_cma_reserved:linux,vdin0_cma { + // compatible = "shared-dma-pool"; + // linux,phandle = <4>; + // reusable; + /* 1920x1080x2x4 =16+4 M */ + // size = <0x01400000>; + // alignment = <0x400000>; + //}; + /* vdin1 CMA pool */ + vdin1_cma_reserved:linux,vdin1_cma { + compatible = "shared-dma-pool"; + reusable; + /* 1920x1080x2x4 =16 M */ + size = <0x01000000>; + alignment = <0x400000>; + }; + /* POST PROCESS MANAGER */ + ppmgr_reserved:linux,ppmgr { + compatible = "shared-dma-pool"; + size = <0x0>; + }; + + codec_mm_cma:linux,codec_mm_cma { + compatible = "shared-dma-pool"; + reusable; + /* ion_codec_mm max can alloc size 80M*/ + size = <0x13400000>; + alignment = <0x400000>; + linux,contiguous-region; + alloc-ranges = <0x30000000 0x50000000>; + }; + picdec_cma_reserved:linux,picdec { + compatible = "shared-dma-pool"; + reusable; + size = <0x0>; + alignment = <0x0>; + linux,contiguous-region; + }; + /* codec shared reserved */ + codec_mm_reserved:linux,codec_mm_reserved { + compatible = "amlogic, codec-mm-reserved"; + size = <0x0>; + alignment = <0x100000>; + //no-map; + }; + }; + bt-dev{ + compatible = "amlogic, bt-dev"; + dev_name = "bt-dev"; + status = "okay"; + gpio_reset = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>; + }; + wifi{ + compatible = "amlogic, aml_wifi"; + dev_name = "aml_wifi"; + status = "okay"; + interrupt_pin = <&gpio GPIOX_7 GPIO_ACTIVE_HIGH>; + irq_trigger_type = "GPIO_IRQ_LOW"; + power_on_pin = <&gpio GPIOX_6 GPIO_ACTIVE_HIGH>; + //if use bcm wifi, config dhd_static_buf and 32k as bellow + dhd_static_buf; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_32k_pins>; + pwm_config = <&wifi_pwm_conf>; + }; + + wifi_pwm_conf:wifi_pwm_conf{ + pwm_channel1_conf { + pwms = <&pwm_ef MESON_PWM_0 30040 0>; + duty-cycle = <15020>; + times = <8>; + }; + pwm_channel2_conf { + pwms = <&pwm_ef MESON_PWM_2 30030 0>; + duty-cycle = <15015>; + times = <12>; + }; + }; + + sd_emmc_c: emmc@d0074000 { + status = "okay"; + compatible = "amlogic, meson-mmc-gxl"; + reg = <0xd0074000 0x2000>; + interrupts = <0 218 1>; + pinctrl-names = "emmc_clk_cmd_pins", "emmc_all_pins"; + pinctrl-0 = <&emmc_clk_cmd_pins>; + pinctrl-1 = <&emmc_conf_pull_up &emmc_conf_pull_done>; + clocks = <&clkc CLKID_SD_EMMC_C>, + <&clkc CLKID_SD_EMMC_C_P0_COMP>, + <&clkc CLKID_FCLK_DIV2>; + clock-names = "core", "clkin0", "clkin1"; + + bus-width = <8>; + cap-sd-highspeed; + cap-mmc-highspeed; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + + max-frequency = <200000000>; + non-removable; + disable-wp; + emmc { + pinname = "emmc"; + ocr_avail = <0x200080>; /**VDD voltage 3.3 ~ 3.4 */ + caps = "MMC_CAP_8_BIT_DATA", + "MMC_CAP_MMC_HIGHSPEED", + "MMC_CAP_SD_HIGHSPEED", + "MMC_CAP_NONREMOVABLE", + "MMC_CAP_1_8V_DDR", + "MMC_CAP_HW_RESET", + "MMC_CAP_ERASE", + "MMC_CAP_CMD23"; + caps2 = "MMC_CAP2_HS200", "MMC_CAP2_HS400"; + f_min = <400000>; + f_max = <100000000>; + max_req_size = <0x20000>; /**128KB*/ + gpio_dat3 = <&gpio BOOT_3 GPIO_ACTIVE_HIGH>; + hw_reset = <&gpio BOOT_9 GPIO_ACTIVE_HIGH>; + card_type = <1>; + /* 1:mmc card(include eMMC), + * 2:sd card(include tSD) + */ + }; + }; + + sd_emmc_b:sd@d0072000 { + status = "okay"; + compatible = "amlogic, meson-mmc-gxl"; + reg = <0xd0072000 0x2000>; + interrupts = <0 217 1>; + pinctrl-names = "sd_all_pins", + "sd_clk_cmd_pins", + "sd_1bit_pins", + "sd_clk_cmd_uart_pins", + "sd_1bit_uart_pins", + "sd_to_ao_uart_pins", + "ao_to_sd_uart_pins", + "ao_to_sd_jtag_pins", + "sd_to_ao_jtag_pins"; + pinctrl-0 = <&sd_all_pins>; + pinctrl-1 = <&sd_clk_cmd_pins>; + pinctrl-2 = <&sd_1bit_pins>; + pinctrl-3 = <&sd_to_ao_uart_clr_pins + &sd_clk_cmd_pins &ao_to_sd_uart_pins>; + pinctrl-4 = <&sd_to_ao_uart_clr_pins + &sd_1bit_pins &ao_to_sd_uart_pins>; + pinctrl-5 = <&sd_all_pins &sd_to_ao_uart_pins>; + pinctrl-6 = <&sd_to_ao_uart_clr_pins &ao_to_sd_uart_pins>; + pinctrl-7 = <&sd_to_ao_uart_clr_pins &ao_to_sd_uart_pins>; + pinctrl-8 = <&sd_all_pins &sd_to_ao_uart_pins>; + clocks = <&clkc CLKID_SD_EMMC_B>, + <&clkc CLKID_SD_EMMC_B_P0_COMP>, + <&clkc CLKID_FCLK_DIV2>; + clock-names = "core", "clkin0", "clkin1"; + + bus-width = <4>; + cap-sd-highspeed; + max-frequency = <100000000>; + disable-wp; + sd { + pinname = "sd"; + ocr_avail = <0x200080>; /**VDD voltage 3.3 ~ 3.4 */ + caps = "MMC_CAP_4_BIT_DATA", + "MMC_CAP_MMC_HIGHSPEED", + "MMC_CAP_SD_HIGHSPEED"; + /* "MMC_CAP_UHS_SDR12", + * "MMC_CAP_UHS_SDR25", + * "MMC_CAP_UHS_SDR50", + * "MMC_CAP_UHS_SDR104"; + */ + f_min = <400000>; + f_max = <100000000>; + max_req_size = <0x20000>; /**128KB*/ + gpio_dat3 = <&gpio CARD_4 GPIO_ACTIVE_HIGH>; + jtag_pin = <&gpio CARD_0 GPIO_ACTIVE_HIGH>; + gpio_cd = <&gpio CARD_6 GPIO_ACTIVE_HIGH>; + card_type = <5>; + /* 0:unknown, + * 1:mmc card(include eMMC), + * 2:sd card(include tSD), + * 3:sdio device(ie:sdio-wifi), + * 4:SD combo (IO+mem) card, + * 5:NON sdio device(means sd/mmc card), + * other:reserved + */ + }; + }; + + sd_emmc_a:sdio@d0070000 { + status = "okay"; + compatible = "amlogic, meson-mmc-gxl"; + reg = <0xd0070000 0x2000>; + interrupts = <0 216 4>; + pinctrl-names = "sdio_clk_cmd_pins", "sdio_all_pins"; + pinctrl-0 = <&sdio_clk_cmd_pins>; + pinctrl-1 = <&sdio_all_pins>; + clocks = <&clkc CLKID_SD_EMMC_A>, + <&clkc CLKID_SD_EMMC_A_P0_COMP>, + <&clkc CLKID_FCLK_DIV2>; + clock-names = "core", "clkin0", "clkin1"; + + bus-width = <4>; + cap-sd-highspeed; + cap-mmc-highspeed; + max-frequency = <100000000>; + non-removable; + disable-wp; + sdio { + pinname = "sdio"; + ocr_avail = <0x200080>; /**VDD voltage 3.3 ~ 3.4 */ + caps = "MMC_CAP_4_BIT_DATA", + "MMC_CAP_MMC_HIGHSPEED", + "MMC_CAP_SD_HIGHSPEED", + "MMC_CAP_NONREMOVABLE", + "MMC_CAP_UHS_SDR12", + "MMC_CAP_UHS_SDR25", + "MMC_CAP_UHS_SDR50", + "MMC_CAP_UHS_SDR104", + "MMC_PM_KEEP_POWER", + "MMC_CAP_SDIO_IRQ"; + f_min = <400000>; + f_max = <200000000>; + max_req_size = <0x20000>; /**128KB*/ + card_type = <3>; + /* 3:sdio device(ie:sdio-wifi), + * 4:SD combo (IO+mem) card + */ + }; + }; + mtd_nand{ + compatible = "amlogic, aml_mtd_nand"; + dev_name = "mtdnand"; + status = "disabled"; + reg = <0xd0074800 0x200>; + interrupts = < 0 34 1 >; + pinctrl-names = "nand_rb_mod","nand_norb_mod", "nand_cs_only"; + pinctrl-0 = <&all_nand_pins>; + pinctrl-1 = <&all_nand_pins>; + pinctrl-2 = <&nand_cs_pins>; + device_id = <0>; + plat-names = "bootloader","nandnormal"; + plat-num = <2>; + plat-part-0 = <&bootloader>; + plat-part-1 = <&nandnormal>; + bootloader: bootloader{ + enable_pad ="ce0"; + busy_pad = "rb0"; + timming_mode = "mode5"; + bch_mode = "bch60_1k"; + t_rea = <20>; + t_rhoh = <15>; + chip_num = <1>; + part_num = <0>; + rb_detect = <1>; + }; + nandnormal: nandnormal{ + enable_pad ="ce0","ce1"; + busy_pad = "rb0","rb1"; + timming_mode = "mode5"; + bch_mode = "bch60_1k"; + plane_mode = "twoplane"; + t_rea = <20>; + t_rhoh = <15>; + chip_num = <2>; + part_num = <3>; + partition = <&nand_partitions>; + rb_detect = <1>; + }; + nand_partitions:nand_partition{ + boot{ + offset=<0x0 0x300000>; + size=<0x0 0x800000>; + }; + /* + *recovery{ + * offset=<0x0 0xB00000>; + * size=<0x0 0xA00000>; + *}; + */ + upgrade{ + offset=<0x0 0xB00000>; + size=<0x0 0x5800000>; + }; + data{ + offset=<0xffffffff 0xffffffff>; + size=<0x0 0x0>; + }; + }; + }; + + ethmac: ethernet@0xc9410000 { + compatible = "amlogic, gxbb-eth-dwmac"; + reg = <0xc9410000 0x10000 + 0xc8834540 0x8 + 0xc8834558 0xc>; + interrupts = <0 8 1>; + pinctrl-names = "external_eth_pins"; + pinctrl-0 = <&external_eth_pins>; + rst_pin-gpios = <&gpio GPIOZ_14 0>; + GPIOZ4_pin-gpios = <&gpio GPIOZ_4 0>; + GPIOZ5_pin-gpios = <&gpio GPIOZ_5 0>; + mc_val_internal_phy = <0x1800>; + mc_val_external_phy = <0x1621>; + cali_val = <0x20000>; + interrupt-names = "macirq"; + clocks = <&clkc CLKID_ETH>; + clock-names = "ethclk81"; + internal_phy=<0>; + }; + + codec_io { + compatible = "amlogic, codec_io"; + #address-cells=<1>; + #size-cells=<1>; + ranges; + io_cbus_base{ + reg = <0xC1100000 0x100000>; + }; + io_dos_base{ + reg = <0xc8820000 0x10000>; + }; + io_hiubus_base{ + reg = <0xc883c000 0x2000>; + }; + io_aobus_base{ + reg = <0xc8100000 0x100000>; + }; + io_vcbus_base{ + reg = <0xd0100000 0x40000>; + }; + io_dmc_base{ + reg = <0xc8838000 0x400>; + }; + }; + + codec_mm { + compatible = "amlogic, codec, mm"; + memory-region = <&codec_mm_cma &codec_mm_reserved>; + dev_name = "codec_mm"; + status = "okay"; + }; + + canvas{ + compatible = "amlogic, meson, canvas"; + dev_name = "amlogic-canvas"; + status = "ok"; + reg = <0xc8838000 0x400>; + }; + + mesonstream { + compatible = "amlogic, codec, streambuf"; + dev_name = "mesonstream"; + status = "okay"; + clocks = <&clkc CLKID_DOS_PARSER + &clkc CLKID_DEMUX + &clkc CLKID_DOS + &clkc CLKID_CLK81 + &clkc CLKID_VDEC_MUX + &clkc CLKID_HCODEC_MUX + &clkc CLKID_HEVC_MUX>; + clock-names = "parser_top", + "demux", + "vdec", + "clk_81", + "clk_vdec_mux", + "clk_hcodec_mux", + "clk_hevc_mux"; + }; + + vdec { + compatible = "amlogic, vdec"; + dev_name = "vdec.0"; + status = "okay"; + interrupts = <0 3 1 + 0 23 1 + 0 32 1 + 0 43 1 + 0 44 1 + 0 45 1>; + interrupt-names = "vsync", + "demux", + "parser", + "mailbox_0", + "mailbox_1", + "mailbox_2"; + }; + + gpio_keypad{ + compatible = "amlogic, gpio_keypad"; + status = "okay"; + scan_period = <20>; + key_num = <1>; + key_name = "power"; + key_code = <116>; + irq_keyup = <6>; + irq_keydown = <7>; + key-gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_HIGH>; + detect_mode = <0>;/*0:polling mode, 1:irq mode*/ + }; + + + aml_sensor0: aml-sensor@0 { + compatible = "amlogic, aml-thermal"; + device_name = "thermal"; + #thermal-sensor-cells = <1>; + cooling_devices { + cpufreq_cool_cluster0 { + min_state = <1000000>; + dyn_coeff = <140>; + cluster_id = <0>; + node_name = "cpufreq_cool0"; + device_type = "cpufreq"; + }; + cpucore_cool_cluster0 { + min_state = <1>; + dyn_coeff = <0>; + cluster_id = <0>; + node_name = "cpucore_cool0"; + device_type = "cpucore"; + }; + gpufreq_cool { + min_state = <400>; + dyn_coeff = <437>; + cluster_id = <0>; + node_name = "gpufreq_cool0"; + device_type = "gpufreq"; + }; + gpucore_cool { + min_state = <1>; + dyn_coeff = <0>; + cluster_id = <0>; + node_name = "gpucore_cool0"; + device_type = "gpucore"; + }; + }; + cpufreq_cool0:cpufreq_cool0 { + #cooling-cells = <2>; /* min followed by max */ + }; + cpucore_cool0:cpucore_cool0 { + #cooling-cells = <2>; /* min followed by max */ + }; + gpufreq_cool0:gpufreq_cool0 { + #cooling-cells = <2>; /* min followed by max */ + }; + gpucore_cool0:gpucore_cool0 { + #cooling-cells = <2>; /* min followed by max */ + }; + }; + thermal-zones { + soc_thermal { + polling-delay = <1000>; + polling-delay-passive = <100>; + sustainable-power = <2150>; + + thermal-sensors = <&aml_sensor0 3>; + + trips { + switch_on: trip-point@0 { + temperature = <70000>; + hysteresis = <1000>; + type = "passive"; + }; + control: trip-point@1 { + temperature = <80000>; + hysteresis = <1000>; + type = "passive"; + }; + hot: trip-point@2 { + temperature = <85000>; + hysteresis = <5000>; + type = "hot"; + }; + critical: trip-point@3 { + temperature = <260000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + + cooling-maps { + cpufreq_cooling_map { + trip = <&control>; + cooling-device = <&cpufreq_cool0 0 4>; + contribution = <1024>; + }; + cpucore_cooling_map { + trip = <&control>; + cooling-device = <&cpucore_cool0 0 3>; + contribution = <1024>; + }; + gpufreq_cooling_map { + trip = <&control>; + cooling-device = <&gpufreq_cool0 0 4>; + contribution = <1024>; + }; + gpucore_cooling_map { + trip = <&control>; + cooling-device = <&gpucore_cool0 0 2>; + contribution = <1024>; + }; + }; + }; + }; + + dwc3: dwc3@c9000000 { + compatible = "synopsys, dwc3"; + reg = <0xc9000000 0x100000>; + interrupts = <0 30 4>; + usb-phy = <&usb2_phy>, <&usb3_phy>; + cpu-type = "gxl"; + clock-src = "usb3.0"; + }; + + usb2_phy: usb2phy@d0078000 { + compatible = "amlogic, amlogic-new-usb2"; + portnum = <3>; + reg = <0xd0078000 0x80 + 0xc1104408 0x4>; + }; + + usb3_phy: usb3phy@d0078080 { + compatible = "amlogic, amlogic-new-usb3"; + portnum = <0>; + reg = <0xd0078080 0x20>; + }; + + dwc2_a { + compatible = "amlogic, dwc2"; + device_name = "dwc2_a"; + reg = <0xc9100000 0x40000>; + status = "okay"; + interrupts = <0 31 4>; + pl-periph-id = <0>; /** lm name */ + clock-src = "usb0"; /** clock src */ + port-id = <0>; /** ref to mach/usb.h */ + port-type = <2>; /** 0: otg, 1: host, 2: slave */ + port-speed = <0>; /** 0: default, high, 1: full */ + port-config = <0>; /** 0: default */ + port-dma = <0>; /** 0: default ... 6: disable*/ + port-id-mode = <0>; /** 0: hardware, 1: sw_host, 2: sw_slave*/ + usb-fifo = <728>; + cpu-type = "gxl"; + controller-type = <3>; /** 0: normal,1:host,2:device,3:otg*/ + phy-reg = <0xd0078000>; + phy-reg-size = <0xa0>; + clocks = <&clkc CLKID_USB_GENERAL + &clkc CLKID_USB1_TO_DDR + &clkc CLKID_USB1>; + clock-names = "usb_general", + "usb1", + "usb1_to_ddr"; + }; + + meson-amvideom { + compatible = "amlogic, amvideom"; + dev_name = "amvideom"; + status = "okay"; + interrupts = <0 3 1>; + interrupt-names = "vsync"; + }; + + vout { + compatible = "amlogic, vout"; + dev_name = "vout"; + status = "okay"; + fr_auto_policy = <0>; + }; + + cvbsout { + compatible = "amlogic, cvbsout-gxl"; + dev_name = "cvbsout"; + status = "okay"; + clocks = <&clkc CLKID_VCLK2_ENCI + &clkc CLKID_VCLK2_VENCI0 + &clkc CLKID_VCLK2_VENCI1 + &clkc CLKID_DAC_CLK>; + clock-names = "venci_top_gate", + "venci_0_gate", + "venci_1_gate", + "vdac_clk_gate"; + + /* performance: reg_address, reg_value */ + /* s905d */ + performance = <0x1bf0 0x9 + 0x1b56 0x343 + 0x1b12 0x8080 + 0x1b05 0xfd + 0x1c59 0xf752 + 0xffff 0x0>; /* ending flag */ + }; + + amhdmitx: amhdmitx{ + compatible = "amlogic, amhdmitx"; + dev_name = "amhdmitx"; + status = "okay"; + vend-data = <&vend_data>; + pinctrl-names="hdmitx_hpd", "hdmitx_ddc"; + pinctrl-0=<&hdmitx_hpd>; + pinctrl-1=<&hdmitx_ddc>; + /* HPD, 57 + 32 = 89; CEC, 151 + 32 = 183*/ + interrupts = <0 57 1>; + interrupt-names = "hdmitx_hpd"; + /* 0:M8B 1:GXBB 2:GXTVBB 3:GXL 4:GXM + * 5:TXL 6:TXLX 7:AXG 8:GXLX 9:TXHD + */ + ic_type = <3>; + vend_data: vend_data{ /* Should modified by Customer */ + vendor_name = "Amlogic"; /* Max Chars: 8 */ + /* standards.ieee.org/develop/regauth/oui/oui.txt */ + vendor_id = <0x000000>; + product_desc = "MBox Meson Ref"; /* Max Chars: 16 */ + }; + }; + + aocec: aocec{ + compatible = "amlogic, amlogic-aocec"; + device_name = "aocec"; + status = "okay"; + vendor_id = <0x000000>; + cec_osd_string = "MBox"; /* Max Chars: 14 */ + cec_version = <6>; /* 5: 1.4, 6: 2.0 */ + port_num = <1>; + arc_port_mask = <0x0>; + interrupts = <0 199 1>; + interrupt-names = "hdmi_aocec"; + pinctrl-names = "default"; + pinctrl-0=<&hdmitx_aocec>; + reg = <0xc810023c 0x4 + 0xc8100000 0x200>; + reg-names = "ao_exit","ao"; + }; + + sysled { + compatible = "amlogic, sysled"; + dev_name = "sysled"; + status = "disabled"; + led_gpio = <&gpio GPIODV_24 GPIO_ACTIVE_HIGH>; + led_active_low = <1>; + }; + + meson-fb { + compatible = "amlogic, meson-gxl"; + memory-region = <&logo_reserved>; + dev_name = "meson-fb"; + status = "okay"; + interrupts = <0 3 1 + 0 89 1>; + interrupt-names = "viu-vsync", "rdma"; + mem_size = <0x00800000 0x01800000 0x00100000>; + /* uboot logo,fb0/fb1 memory size,if afbcd fb0=0x01851000*/ + display_mode_default = "1080p60hz"; + scale_mode = <1>; + /** 0:VPU free scale 1:OSD free scale 2:OSD super scale */ + display_size_default = <1920 1080 1920 3240 32>; + /*1920*1080*4*3 = 0x17BB000*/ + logo_addr = "0x7f800000"; + }; + ge2d { + compatible = "amlogic, ge2d-gxl"; + dev_name = "ge2d"; + status = "okay"; + interrupts = <0 150 1>; + interrupt-names = "ge2d"; + clocks = <&clkc CLKID_VAPB_MUX>, + <&clkc CLKID_G2D>, + <&clkc CLKID_GE2D_GATE>; + clock-names = "clk_vapb_0", + "clk_ge2d", + "clk_ge2d_gate"; + }; + + + /* AUDIO MESON DEVICES */ + i2s_dai: I2S { + #sound-dai-cells = <0>; + compatible = "amlogic, aml-i2s-dai"; + clocks = + <&clkc CLKID_MPLL2>, + <&clkc CLKID_AMCLK_COMP>, + <&clkc CLKID_AIU_GLUE>, + <&clkc CLKID_IEC958>, + <&clkc CLKID_I2S_OUT>, + <&clkc CLKID_AMCLK>, + <&clkc CLKID_AIFIFO2>, + <&clkc CLKID_MIXER>, + <&clkc CLKID_MIXER_IFACE>, + <&clkc CLKID_ADC>, + <&clkc CLKID_AIU_TOP>, + <&clkc CLKID_AOCLK_GATE>, + <&clkc CLKID_I2S_SPDIF>; + clock-names = + "mpll", + "mclk", + "top_glue", + "aud_buf", + "i2s_out", + "amclk_measure", + "aififo2", + "aud_mixer", + "mixer_reg", + "adc", + "top_level", + "aoclk", + "aud_in"; + i2s_pos_sync = <0>; + /*DMIC;*/ /* I2s Mic or Dmic, default for I2S mic */ + }; + dmic:snd_dmic { + #sound-dai-cells = <0>; + compatible = "aml, aml_snd_dmic"; + reg = <0xd0042000 0x2000>; + status = "okay"; + resets = < + &clkc CLKID_PDM_GATE + >; + reset-names = "pdm"; + pinctrl-names = "audio_dmic"; + pinctrl-0 = <&aml_dmic_pins>; + clocks = <&clkc CLKID_PDM_COMP>, + <&clkc CLKID_AMCLK_COMP>; + clock-names = "pdm", "mclk"; + }; + spdif_dai: SPDIF { + #sound-dai-cells = <0>; + compatible = "amlogic, aml-spdif-dai"; + clocks = + <&clkc CLKID_MPLL1>, + <&clkc CLKID_I958_COMP>, + <&clkc CLKID_AMCLK_COMP>, + <&clkc CLKID_I958_COMP_SPDIF>, + <&clkc CLKID_CLK81>, + <&clkc CLKID_IEC958>, + <&clkc CLKID_IEC958_GATE>; + clock-names = + "mpll1", + "i958", + "mclk", + "spdif", + "clk_81", + "iec958", + "iec958_amclk"; + }; + pcm_dai: PCM { + #sound-dai-cells = <0>; + compatible = "amlogic, aml-pcm-dai"; + pinctrl-names = "audio_pcm"; + pinctrl-0 = <&audio_pcm_pins>; + clocks = + <&clkc CLKID_MPLL0>, + <&clkc CLKID_PCM_MCLK_COMP>, + <&clkc CLKID_PCM_SCLK_GATE>; + clock-names = + "mpll0", + "pcm_mclk", + "pcm_sclk"; + pcm_mode = <1>; /* 0=slave mode, 1=master mode */ + }; + i2s_plat: i2s_platform { + compatible = "amlogic, aml-i2s"; + interrupts = <0 29 1>; + }; + pcm_plat: pcm_platform { + compatible = "amlogic, aml-pcm"; + }; + spdif_codec: spdif_codec{ + #sound-dai-cells = <0>; + compatible = "amlogic, aml-spdif-codec"; + pinctrl-names = "audio_spdif_out"; + pinctrl-0 = <&audio_spdif_out_pins>; + }; + pcm_codec: pcm_codec{ + #sound-dai-cells = <0>; + compatible = "amlogic, pcm2BT-codec"; + }; + /* endof AUDIO MESON DEVICES */ + + /* AUDIO board specific */ + dummy_codec:dummy{ + #sound-dai-cells = <0>; + compatible = "amlogic, aml_dummy_codec"; + status = "disable"; + }; + amlogic_codec:t9015{ + #sound-dai-cells = <0>; + compatible = "amlogic, aml_codec_T9015"; + reg = <0xc8832000 0x14>; + status = "okay"; + }; + aml_sound_meson { + compatible = "aml, meson-snd-card"; + status = "okay"; + aml-sound-card,format = "i2s"; + aml_sound_card,name = "AML-MESONAUDIO"; + aml,audio-routing = + "Ext Spk","LOUTL", + "Ext Spk","LOUTR"; + + mute_gpio-gpios = <&gpio GPIOH_5 0>; + mute_inv; + hp_disable; + hp_paraments = <800 300 0 5 1>; + pinctrl-names = "audio_i2s"; + pinctrl-0 = <&audio_i2s_pins>; + cpu_list = <&cpudai0 &cpudai1 &cpudai2>; + codec_list = <&codec0 &codec1 &codec2>; + plat_list = <&i2s_plat &i2s_plat &pcm_plat>; + cpudai0: cpudai0 { + sound-dai = <&i2s_dai>; + }; + cpudai1: cpudai1 { + sound-dai = <&spdif_dai>; + }; + cpudai2: cpudai2 { + sound-dai = <&pcm_dai>; + }; + codec0: codec0 { + sound-dai = <&amlogic_codec>; + }; + codec1: codec1 { + sound-dai = <&spdif_codec>; + }; + codec2: codec2 { + sound-dai = <&pcm_codec>; + }; + }; + /* END OF AUDIO board specific */ + rdma{ + compatible = "amlogic, meson, rdma"; + dev_name = "amlogic-rdma"; + status = "ok"; + interrupts = <0 89 1>; + interrupt-names = "rdma"; + }; + + amvenc_avc{ + compatible = "amlogic, amvenc_avc"; + dev_name = "amvenc_avc"; + status = "okay"; + interrupts = <0 45 1>; + interrupt-names = "mailbox_2"; + }; + + hevc_enc{ + compatible = "cnm, HevcEnc"; + dev_name = "HevcEnc"; + status = "okay"; + interrupts = <0 187 1>; + interrupt-names = "wave420l_irq"; + #address-cells=<1>; + #size-cells=<1>; + ranges; + io_reg_base{ + reg = <0xc8810000 0x4000>; + }; + }; + + picdec { + compatible = "amlogic, picdec"; + memory-region = <&picdec_cma_reserved>; + dev_name = "picdec"; + status = "okay"; + }; + + ppmgr { + compatible = "amlogic, ppmgr"; + memory-region = <&ppmgr_reserved>; + dev_name = "ppmgr"; + status = "okay"; + }; + + deinterlace { + compatible = "amlogic, deinterlace"; + status = "okay"; + flag_cma = <1>;/*0:use reserved;1:use cma*/ + //memory-region = <&di_reserved>; + memory-region = <&di_cma_reserved>; + interrupts = <0 46 1 0 6 1>; + interrupt-names = "de_irq", "timerc"; + /* + * nr_size(byte) = 1920*544*2(yuv422 8bit) | + * 1920*544*2*12/8(yuv422 10bit) + * | 1920*544*2*10/8(yuv422 10bit full pack mode) + */ + /* mtn_size(byte) = 1920*544/2 */ + /* count_size(byte) = 1920*544/2 */ + buffer-size = <3133440>; + hw-version = <2>; + }; + + ionvideo { + compatible = "amlogic, ionvideo"; + dev_name = "ionvideo"; + status = "okay"; + }; + + amlvideo { + compatible = "amlogic, amlvideo"; + dev_name = "amlvideo"; + status = "okay"; + }; + + amlvideo2_0 { + compatible = "amlogic, amlvideo2"; + dev_name = "amlvideo2"; + status = "okay"; + amlvideo2_id = <0>; + cma_mode = <1>; + }; + + amlvideo2_1 { + compatible = "amlogic, amlvideo2"; + dev_name = "amlvideo2"; + status = "okay"; + amlvideo2_id = <1>; + cma_mode = <1>; + }; + + /*if you want to use vdin just modify status to "ok"*/ + vdin0 { + compatible = "amlogic, vdin"; + /*memory-region = <&vdin0_cma_reserved>;*/ + dev_name = "vdin0"; + status = "ok"; + reserve-iomap = "true"; + flag_cma = <1>;/*1:share with codec_mm;2:cma alone*/ + /*MByte, if 10bit disable: 64M(YUV422), + *if 10bit enable: 64*1.5 = 96M(YUV422) + *if support 4K2K-YUV444-10bit-WR:3840*2160*4*4 ~= 128M + *if support 4K2K-YUV422-10bit-wr:3840*2160*3*4 ~= 96M + *if support 4K2K-YUV422-8BIT-WR:3840*2160*2*4 ~= 64M + *if support 1080p-YUV422-8BIT-WR:1920*1080*2*4 ~= 16M + */ + cma_size = <16>; + interrupts = <0 83 1>; + rdma-irq = <2>; + /*clocks = <&clock CLK_FPLL_DIV5>, + * <&clock CLK_VDIN_MEAS_CLK>; + *clock-names = "fclk_div5", "cts_vdin_meas_clk"; + */ + vdin_id = <0>; + /*vdin write mem color depth support: + *bit0:support 8bit + *bit1:support 9bit + *bit2:support 10bit + *bit3:support 12bit + *bit4:support yuv422 10bit full pack mode (from txl new add) + */ + tv_bit_mode = <1>; + }; + vdin1 { + compatible = "amlogic, vdin"; + memory-region = <&vdin1_cma_reserved>; + dev_name = "vdin1"; + status = "ok"; + reserve-iomap = "true"; + flag_cma = <0>;/*1:share with codec_mm;0:cma alone*/ + interrupts = <0 85 1>; + rdma-irq = <4>; + /*clocks = <&clock CLK_FPLL_DIV5>, + * <&clock CLK_VDIN_MEAS_CLK>; + *clock-names = "fclk_div5", "cts_vdin_meas_clk"; + */ + vdin_id = <1>; + /*vdin write mem color depth support: + *bit0:support 8bit + *bit1:support 9bit + *bit2:support 10bit + *bit3:support 12bit + */ + tv_bit_mode = <1>; + }; + amvdec_656in { + compatible = "amlogic, amvdec_656in"; + dev_name = "amvdec_656in"; + status = "disabled"; + reg = <0xd0048000 0x7c>, + <0xd0050000 0x7c>; + clocks = <&clkc CLKID_BT656_CLK1_COMP>, + <&clkc CLKID_BT656>, + <&clkc CLKID_BT656_PCLK1>; + clock-names = "cts_bt656_clk1", + "clk_gate_bt656", + "clk_gate_bt656_pclk1"; + + /* bt656in1, bt656in2 */ + bt656in1 { + bt656_id = <1>; + status = "okay"; + }; + }; + hdmirx_ext { + compatible = "amlogic, hdmirx_ext"; + dev_name = "hdmirx_ext"; + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&hdmirx_ext_pins>; + vdin_sel = <0>; + bt656_sel = <1>; + reset-gpios = <&gpio GPIODV_20 GPIO_ACTIVE_HIGH>; + reset_gpio_name = "GPIODV_20"; + reset_gpio_val = <0 1>; /* reset_on, reset_off */ + + ext_dev_name = "sii9135"; + i2c_addr = <0x30>; /* pull_up: 0x31, pull_down: 0x30 */ + i2c_bus = "i2c_bus_c"; + }; + + amlvecm { + compatible = "amlogic, vecm"; + dev_name = "aml_vecm"; + status = "okay"; + gamma_en = <0>;/*1:enabel ;0:disable*/ + wb_en = <0>;/*1:enabel ;0:disable*/ + cm_en = <0>;/*1:enabel ;0:disable*/ + /*1:enabel osd lut 100 table;0:disable*/ + cfg_en_osd_100 = <1>; + /*0: 709/601 1: bt2020*/ + tx_op_color_primary = <0>; + }; + + unifykey{ + compatible = "amlogic, unifykey"; + status = "ok"; + + unifykey-num = <16>; + unifykey-index-0 = <&keysn_0>; + unifykey-index-1 = <&keysn_1>; + unifykey-index-2 = <&keysn_2>; + unifykey-index-3 = <&keysn_3>; + unifykey-index-4 = <&keysn_4>; + unifykey-index-5 = <&keysn_5>; + unifykey-index-6 = <&keysn_6>; + unifykey-index-7 = <&keysn_7>; + unifykey-index-8 = <&keysn_8>; + unifykey-index-9 = <&keysn_9>; + unifykey-index-10= <&keysn_10>; + unifykey-index-11= <&keysn_11>; + unifykey-index-12= <&keysn_12>; + unifykey-index-13= <&keysn_13>; + unifykey-index-14= <&keysn_14>; + unifykey-index-15= <&keysn_15>; + + keysn_0: key_0{ + key-name = "usid"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_1:key_1{ + key-name = "mac"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_2:key_2{ + key-name = "hdcp"; + key-device = "secure"; + key-type = "sha1"; + key-permit = "read","write","del"; + }; + keysn_3:key_3{ + key-name = "secure_boot_set"; + key-device = "efuse"; + key-permit = "write"; + }; + keysn_4:key_4{ + key-name = "mac_bt"; + key-device = "normal"; + key-permit = "read","write","del"; + key-type = "mac"; + }; + keysn_5:key_5{ + key-name = "mac_wifi"; + key-device = "normal"; + key-permit = "read","write","del"; + key-type = "mac"; + }; + keysn_6:key_6{ + key-name = "hdcp2_tx"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_7:key_7{ + key-name = "hdcp2_rx"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_8:key_8{ + key-name = "widevinekeybox"; + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_9:key_9{ + key-name = "deviceid"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_10:key_10{ + key-name = "hdcp22_fw_private"; + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_11:key_11{ + key-name = "PlayReadykeybox25"; + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_12:key_12{ + key-name = "prpubkeybox";// PlayReady + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_13:key_13{ + key-name = "prprivkeybox";// PlayReady + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_14:key_14{ + key-name = "attestationkeybox";// attestation key + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_15:key_15{ + key-name = "region_code"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + };//End unifykey + dvb { + compatible = "amlogic, dvb"; + dev_name = "dvb"; + + fe0_mode = "external"; + fe0_demod = "Atbm8881"; + fe0_i2c_adap_id = <&i2c1>; + fe0_demod_i2c_addr = <0xc0>; + fe0_ts = <0>; + fe0_reset_value = <0>; + fe0_reset_gpio = <&gpio GPIODV_14 GPIO_ACTIVE_HIGH>; + + ts0 = "parallel"; + ts0_control = <0>; + ts0_invert = <0>; + interrupts = <0 23 1 + 0 5 1 + 0 21 1 + 0 19 1 + 0 25 1 + 0 18 1 + 0 24 1>; + interrupt-names = "demux0_irq", + "demux1_irq", + "demux2_irq", + "dvr0_irq", + "dvr1_irq", + "dvrfill0_fill", + "dvrfill1_flush"; + pinctrl-names = "p_ts0", "s_ts0"; + pinctrl-0 = <&dvb_p_ts0_pins>; + pinctrl-1 = <&dvb_s_ts0_pins>; + clocks = <&clkc CLKID_DEMUX + &clkc CLKID_ASYNC_FIFO + &clkc CLKID_AHB_ARB0 + &clkc CLKID_HIU_IFACE>; + clock-names = "demux", "asyncfifo", "ahbarb0", "uparsertop"; + }; + + /* SMC */ + smartcard{ + compatible = "amlogic,smartcard"; + irq_trigger_type = "GPIO_IRQ_LOW"; + + reset_pin-gpios = <&gpio GPIODV_21 GPIO_ACTIVE_HIGH>; + detect_pin-gpios = <&gpio GPIODV_20 GPIO_ACTIVE_HIGH>; + enable_5v3v_pin-gpios = <&gpio GPIODV_19 GPIO_ACTIVE_HIGH>; + enable_pin-gpios = <&gpio GPIODV_20 GPIO_ACTIVE_HIGH>; + + interrupts = <0 37 1>; + interrupt-names = "smc0_irq"; + /* + *Smc clock source, if change this, + *you must adjust clk and divider in smartcard.c + */ + smc0_clock_source = <0>; + smc0_irq = <37>; //smc irq + /*0: high voltage on detect pin indicates card in.*/ + smc0_det_invert = <0>; + smc0_5v3v_level = <0>; + /*Ordinarily,smartcard controller needs a enable pin.*/ + smc_need_enable_pin = "no"; + reset_level = <0>; + smc0_enable_level = <0>; + + pinctrl-names = "default"; + pinctrl-0 = <&sd_iso7816_pins>; + clocks = <&clkc CLKID_SMART_CARD>; + clock-names = "smartcard"; + status = "okay"; + }; +}; +&efuse { + status = "ok"; +}; + +&pwm_ef { + status = "okay"; +}; + +&audio_data{ + status = "okay"; +}; +//&i2c_a { +// status = "disabled"; +//}; +//&i2c_b { +// status = "okay"; +//}; + +//&i2c_c { +// status = "okay"; +// pinctrl-0=<&c_i2c_master_pin1>; +//}; + +&i2c1 { + status = "okay"; + clock-frequency = <300000>; + pinctrl-names="default"; + pinctrl-0=<&b_i2c_master>; +}; +&pinctrl_periphs { + hdmirx_ext_pins: hdmirx_ext_pins { + mux { + groups = "dvp_vs", + "dvp_hs", + "dvp_clk", + "dvp_d2_9"; + function = "dvp"; + }; + }; + + /*spdif*/ + audio_spdif_out_pins: audio_spdif_out_pins { + mux { + groups = "spdif_out"; + function = "spdif_out"; + }; + }; +}; /* end of pinctrl_periphs */ + diff --git a/arch/arm/boot/dts/amlogic/gxl_p230_2g_buildroot.dts b/arch/arm/boot/dts/amlogic/gxl_p230_2g_buildroot.dts new file mode 100644 index 000000000000..4213a292a4b3 --- /dev/null +++ b/arch/arm/boot/dts/amlogic/gxl_p230_2g_buildroot.dts @@ -0,0 +1,1319 @@ +/* + * arch/arm/boot/dts/amlogic/gxl_p230_2g.dts + * + * Copyright (C) 2017 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +/dts-v1/; + +#include +#include "mesongxl.dtsi" +#include "meson_drm.dtsi" +/ { + model = "Amlogic"; + amlogic-dt-id = "gxl_p230_2g"; + compatible = "amlogic, Gxl"; + interrupt-parent = <&gic>; + #address-cells = <1>; + #size-cells = <1>; + + aliases { + serial0 = &uart_AO; + serial1 = &uart_A; + serial2 = &uart_B; + serial3 = &uart_C; + serial4 = &uart_AO_B; + }; + + ion_dev { + compatible = "amlogic, ion_dev"; + memory-region = <&ion_reserved>; + }; + + memory@00000000 { + device_type = "memory"; + linux,usable-memory = <0x0100000 0x7ff00000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + /* global autoconfigured region for contiguous allocations */ + ramoops@0x07400000 { + compatible = "ramoops"; + reg = <0x07400000 0x00100000>; + record-size = <0x8000>; + console-size = <0x8000>; + ftrace-size = <0x0>; + pmsg-size = <0x8000>; + }; + + secmon_reserved:linux,secmon { + compatible = "shared-dma-pool"; + reusable; + size = <0x400000>; + alignment = <0x400000>; + alloc-ranges = <0x05000000 0x400000>; + }; + secos_reserved:linux,secos { + status = "disable"; + compatible = "amlogic, aml_secos_memory"; + reg = <0x05300000 0x2000000>; + no-map; + }; + logo_reserved:linux,meson-fb { + compatible = "shared-dma-pool"; + reusable; + size = <0x800000>; + alignment = <0x400000>; + alloc-ranges = <0x7f800000 0x800000>; + }; + //don't put other dts in front of logo_reserved + + //di_reserved:linux,di { + // compatible = "amlogic, di-mem"; + /** 10x3133440=30M(0x1e) support 8bit **/ + // size = <0x1e00000>; + //no-map; + //}; + di_cma_reserved:linux,di_cma { + compatible = "shared-dma-pool"; + reusable; + /** 10x3133440=30M(0x1e) support 8bit **/ + size = <0x2000000>; + alignment = <0x400000>; + }; + ion_reserved:linux,ion-dev { + compatible = "shared-dma-pool"; + reusable; + size = <0x5C00000>; + alignment = <0x400000>; + }; + + /* vdin0 CMA pool */ + //vdin0_cma_reserved:linux,vdin0_cma { + // compatible = "shared-dma-pool"; + // linux,phandle = <4>; + // reusable; + /* 1920x1080x2x4 =16+4 M */ + // size = <0x01400000>; + // alignment = <0x400000>; + //}; + /* vdin1 CMA pool */ + vdin1_cma_reserved:linux,vdin1_cma { + compatible = "shared-dma-pool"; + reusable; + /* 1920x1080x2x4 =16 M */ + size = <0x01000000>; + alignment = <0x400000>; + }; + /* POST PROCESS MANAGER */ + ppmgr_reserved:linux,ppmgr { + compatible = "shared-dma-pool"; + size = <0x0>; + }; + + codec_mm_cma:linux,codec_mm_cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x13400000>; + alignment = <0x400000>; + linux,contiguous-region; + }; + picdec_cma_reserved:linux,picdec { + compatible = "shared-dma-pool"; + reusable; + size = <0x0>; + alignment = <0x0>; + linux,contiguous-region; + }; + /* codec shared reserved */ + codec_mm_reserved:linux,codec_mm_reserved { + compatible = "amlogic, codec-mm-reserved"; + size = <0x0>; + alignment = <0x100000>; + //no-map; + }; + }; + bt-dev{ + compatible = "amlogic, bt-dev"; + dev_name = "bt-dev"; + status = "okay"; + gpio_reset = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>; + }; + wifi{ + compatible = "amlogic, aml_wifi"; + dev_name = "aml_wifi"; + status = "okay"; + interrupt_pin = <&gpio GPIOX_7 GPIO_ACTIVE_HIGH>; + irq_trigger_type = "GPIO_IRQ_LOW"; + power_on_pin = <&gpio GPIOX_6 GPIO_ACTIVE_HIGH>; + //if use bcm wifi, config dhd_static_buf and 32k as bellow + dhd_static_buf; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_32k_pins>; + pwm_config = <&wifi_pwm_conf>; + }; + + wifi_pwm_conf:wifi_pwm_conf{ + pwm_channel1_conf { + pwms = <&pwm_ef MESON_PWM_0 30040 0>; + duty-cycle = <15020>; + times = <8>; + }; + pwm_channel2_conf { + pwms = <&pwm_ef MESON_PWM_2 30030 0>; + duty-cycle = <15015>; + times = <12>; + }; + }; + + sd_emmc_c: emmc@d0074000 { + status = "okay"; + compatible = "amlogic, meson-mmc-gxl"; + reg = <0xd0074000 0x2000>; + interrupts = <0 218 1>; + pinctrl-names = "emmc_clk_cmd_pins", "emmc_all_pins"; + pinctrl-0 = <&emmc_clk_cmd_pins>; + pinctrl-1 = <&emmc_conf_pull_up &emmc_conf_pull_done>; + clocks = <&clkc CLKID_SD_EMMC_C>, + <&clkc CLKID_SD_EMMC_C_P0_COMP>, + <&clkc CLKID_FCLK_DIV2>; + clock-names = "core", "clkin0", "clkin1"; + + bus-width = <8>; + cap-sd-highspeed; + cap-mmc-highspeed; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + + max-frequency = <200000000>; + non-removable; + disable-wp; + emmc { + pinname = "emmc"; + ocr_avail = <0x200080>; /**VDD voltage 3.3 ~ 3.4 */ + caps = "MMC_CAP_8_BIT_DATA", + "MMC_CAP_MMC_HIGHSPEED", + "MMC_CAP_SD_HIGHSPEED", + "MMC_CAP_NONREMOVABLE", + "MMC_CAP_1_8V_DDR", + "MMC_CAP_HW_RESET", + "MMC_CAP_ERASE", + "MMC_CAP_CMD23"; + caps2 = "MMC_CAP2_HS200", "MMC_CAP2_HS400"; + f_min = <400000>; + f_max = <100000000>; + max_req_size = <0x20000>; /**128KB*/ + gpio_dat3 = <&gpio BOOT_3 GPIO_ACTIVE_HIGH>; + hw_reset = <&gpio BOOT_9 GPIO_ACTIVE_HIGH>; + card_type = <1>; + /* 1:mmc card(include eMMC), + * 2:sd card(include tSD) + */ + }; + }; + + sd_emmc_b:sd@d0072000 { + status = "okay"; + compatible = "amlogic, meson-mmc-gxl"; + reg = <0xd0072000 0x2000>; + interrupts = <0 217 1>; + pinctrl-names = "sd_all_pins", + "sd_clk_cmd_pins", + "sd_1bit_pins", + "sd_clk_cmd_uart_pins", + "sd_1bit_uart_pins", + "sd_to_ao_uart_pins", + "ao_to_sd_uart_pins", + "ao_to_sd_jtag_pins", + "sd_to_ao_jtag_pins"; + pinctrl-0 = <&sd_all_pins>; + pinctrl-1 = <&sd_clk_cmd_pins>; + pinctrl-2 = <&sd_1bit_pins>; + pinctrl-3 = <&sd_to_ao_uart_clr_pins + &sd_clk_cmd_pins &ao_to_sd_uart_pins>; + pinctrl-4 = <&sd_to_ao_uart_clr_pins + &sd_1bit_pins &ao_to_sd_uart_pins>; + pinctrl-5 = <&sd_all_pins &sd_to_ao_uart_pins>; + pinctrl-6 = <&sd_to_ao_uart_clr_pins &ao_to_sd_uart_pins>; + pinctrl-7 = <&sd_to_ao_uart_clr_pins &ao_to_sd_uart_pins>; + pinctrl-8 = <&sd_all_pins &sd_to_ao_uart_pins>; + clocks = <&clkc CLKID_SD_EMMC_B>, + <&clkc CLKID_SD_EMMC_B_P0_COMP>, + <&clkc CLKID_FCLK_DIV2>; + clock-names = "core", "clkin0", "clkin1"; + + bus-width = <4>; + cap-sd-highspeed; + max-frequency = <100000000>; + disable-wp; + sd { + pinname = "sd"; + ocr_avail = <0x200080>; /**VDD voltage 3.3 ~ 3.4 */ + caps = "MMC_CAP_4_BIT_DATA", + "MMC_CAP_MMC_HIGHSPEED", + "MMC_CAP_SD_HIGHSPEED"; + /* "MMC_CAP_UHS_SDR12", + * "MMC_CAP_UHS_SDR25", + * "MMC_CAP_UHS_SDR50", + * "MMC_CAP_UHS_SDR104"; + */ + f_min = <400000>; + f_max = <100000000>; + max_req_size = <0x20000>; /**128KB*/ + gpio_dat3 = <&gpio CARD_4 GPIO_ACTIVE_HIGH>; + jtag_pin = <&gpio CARD_0 GPIO_ACTIVE_HIGH>; + gpio_cd = <&gpio CARD_6 GPIO_ACTIVE_HIGH>; + card_type = <5>; + /* 0:unknown, + * 1:mmc card(include eMMC), + * 2:sd card(include tSD), + * 3:sdio device(ie:sdio-wifi), + * 4:SD combo (IO+mem) card, + * 5:NON sdio device(means sd/mmc card), + * other:reserved + */ + }; + }; + + sd_emmc_a:sdio@d0070000 { + status = "okay"; + compatible = "amlogic, meson-mmc-gxl"; + reg = <0xd0070000 0x2000>; + interrupts = <0 216 4>; + pinctrl-names = "sdio_clk_cmd_pins", "sdio_all_pins"; + pinctrl-0 = <&sdio_clk_cmd_pins>; + pinctrl-1 = <&sdio_all_pins>; + clocks = <&clkc CLKID_SD_EMMC_A>, + <&clkc CLKID_SD_EMMC_A_P0_COMP>, + <&clkc CLKID_FCLK_DIV2>; + clock-names = "core", "clkin0", "clkin1"; + + bus-width = <4>; + cap-sd-highspeed; + cap-mmc-highspeed; + max-frequency = <100000000>; + non-removable; + disable-wp; + sdio { + pinname = "sdio"; + ocr_avail = <0x200080>; /**VDD voltage 3.3 ~ 3.4 */ + caps = "MMC_CAP_4_BIT_DATA", + "MMC_CAP_MMC_HIGHSPEED", + "MMC_CAP_SD_HIGHSPEED", + "MMC_CAP_NONREMOVABLE", + "MMC_CAP_UHS_SDR12", + "MMC_CAP_UHS_SDR25", + "MMC_CAP_UHS_SDR50", + "MMC_CAP_UHS_SDR104", + "MMC_PM_KEEP_POWER", + "MMC_CAP_SDIO_IRQ"; + f_min = <400000>; + f_max = <200000000>; + max_req_size = <0x20000>; /**128KB*/ + card_type = <3>; + /* 3:sdio device(ie:sdio-wifi), + * 4:SD combo (IO+mem) card + */ + }; + }; + mtd_nand{ + compatible = "amlogic, aml_mtd_nand"; + dev_name = "mtdnand"; + status = "disabled"; + reg = <0xd0074800 0x200>; + interrupts = < 0 34 1 >; + pinctrl-names = "nand_rb_mod","nand_norb_mod", "nand_cs_only"; + pinctrl-0 = <&all_nand_pins>; + pinctrl-1 = <&all_nand_pins>; + pinctrl-2 = <&nand_cs_pins>; + device_id = <0>; + plat-names = "bootloader","nandnormal"; + plat-num = <2>; + plat-part-0 = <&bootloader>; + plat-part-1 = <&nandnormal>; + bootloader: bootloader{ + enable_pad ="ce0"; + busy_pad = "rb0"; + timming_mode = "mode5"; + bch_mode = "bch60_1k"; + t_rea = <20>; + t_rhoh = <15>; + chip_num = <1>; + part_num = <0>; + rb_detect = <1>; + }; + nandnormal: nandnormal{ + enable_pad ="ce0","ce1"; + busy_pad = "rb0","rb1"; + timming_mode = "mode5"; + bch_mode = "bch60_1k"; + plane_mode = "twoplane"; + t_rea = <20>; + t_rhoh = <15>; + chip_num = <2>; + part_num = <3>; + partition = <&nand_partitions>; + rb_detect = <1>; + }; + nand_partitions:nand_partition{ + boot{ + offset=<0x0 0x300000>; + size=<0x0 0x800000>; + }; + /* + *recovery{ + * offset=<0x0 0xB00000>; + * size=<0x0 0xA00000>; + *}; + */ + upgrade{ + offset=<0x0 0xB00000>; + size=<0x0 0x5800000>; + }; + data{ + offset=<0xffffffff 0xffffffff>; + size=<0x0 0x0>; + }; + }; + }; + + ethmac: ethernet@0xc9410000 { + compatible = "amlogic, gxbb-eth-dwmac"; + reg = <0xc9410000 0x10000 + 0xc8834540 0x8 + 0xc8834558 0xc>; + interrupts = <0 8 1>; + pinctrl-names = "external_eth_pins"; + pinctrl-0 = <&external_eth_pins>; + rst_pin-gpios = <&gpio GPIOZ_14 0>; + GPIOZ4_pin-gpios = <&gpio GPIOZ_4 0>; + GPIOZ5_pin-gpios = <&gpio GPIOZ_5 0>; + mc_val_internal_phy = <0x1800>; + mc_val_external_phy = <0x1621>; + cali_val = <0x20000>; + interrupt-names = "macirq"; + clocks = <&clkc CLKID_ETH>; + clock-names = "ethclk81"; + internal_phy=<0>; + }; + + codec_io { + compatible = "amlogic, codec_io"; + #address-cells=<1>; + #size-cells=<1>; + ranges; + io_cbus_base{ + reg = <0xC1100000 0x100000>; + }; + io_dos_base{ + reg = <0xc8820000 0x10000>; + }; + io_hiubus_base{ + reg = <0xc883c000 0x2000>; + }; + io_aobus_base{ + reg = <0xc8100000 0x100000>; + }; + io_vcbus_base{ + reg = <0xd0100000 0x40000>; + }; + io_dmc_base{ + reg = <0xc8838000 0x400>; + }; + }; + + codec_mm { + compatible = "amlogic, codec, mm"; + memory-region = <&codec_mm_cma &codec_mm_reserved>; + dev_name = "codec_mm"; + status = "okay"; + }; + + canvas{ + compatible = "amlogic, meson, canvas"; + dev_name = "amlogic-canvas"; + status = "ok"; + reg = <0xc8838000 0x400>; + }; + + mesonstream { + compatible = "amlogic, codec, streambuf"; + dev_name = "mesonstream"; + status = "okay"; + clocks = <&clkc CLKID_DOS_PARSER + &clkc CLKID_DEMUX + &clkc CLKID_DOS + &clkc CLKID_CLK81 + &clkc CLKID_VDEC_MUX + &clkc CLKID_HCODEC_MUX + &clkc CLKID_HEVC_MUX>; + clock-names = "parser_top", + "demux", + "vdec", + "clk_81", + "clk_vdec_mux", + "clk_hcodec_mux", + "clk_hevc_mux"; + }; + + vdec { + compatible = "amlogic, vdec"; + dev_name = "vdec.0"; + status = "okay"; + interrupts = <0 3 1 + 0 23 1 + 0 32 1 + 0 43 1 + 0 44 1 + 0 45 1>; + interrupt-names = "vsync", + "demux", + "parser", + "mailbox_0", + "mailbox_1", + "mailbox_2"; + }; + + aml_sensor0: aml-sensor@0 { + compatible = "amlogic, aml-thermal"; + device_name = "thermal"; + #thermal-sensor-cells = <1>; + cooling_devices { + cpufreq_cool_cluster0 { + min_state = <1000000>; + dyn_coeff = <140>; + cluster_id = <0>; + node_name = "cpufreq_cool0"; + device_type = "cpufreq"; + }; + cpucore_cool_cluster0 { + min_state = <1>; + dyn_coeff = <0>; + cluster_id = <0>; + node_name = "cpucore_cool0"; + device_type = "cpucore"; + }; + gpufreq_cool { + min_state = <400>; + dyn_coeff = <437>; + cluster_id = <0>; + node_name = "gpufreq_cool0"; + device_type = "gpufreq"; + }; + gpucore_cool { + min_state = <1>; + dyn_coeff = <0>; + cluster_id = <0>; + node_name = "gpucore_cool0"; + device_type = "gpucore"; + }; + }; + cpufreq_cool0:cpufreq_cool0 { + #cooling-cells = <2>; /* min followed by max */ + }; + cpucore_cool0:cpucore_cool0 { + #cooling-cells = <2>; /* min followed by max */ + }; + gpufreq_cool0:gpufreq_cool0 { + #cooling-cells = <2>; /* min followed by max */ + }; + gpucore_cool0:gpucore_cool0 { + #cooling-cells = <2>; /* min followed by max */ + }; + }; + thermal-zones { + soc_thermal { + polling-delay = <1000>; + polling-delay-passive = <100>; + sustainable-power = <2150>; + + thermal-sensors = <&aml_sensor0 3>; + + trips { + switch_on: trip-point@0 { + temperature = <70000>; + hysteresis = <1000>; + type = "passive"; + }; + control: trip-point@1 { + temperature = <80000>; + hysteresis = <1000>; + type = "passive"; + }; + hot: trip-point@2 { + temperature = <85000>; + hysteresis = <5000>; + type = "hot"; + }; + critical: trip-point@3 { + temperature = <260000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + + cooling-maps { + cpufreq_cooling_map { + trip = <&control>; + cooling-device = <&cpufreq_cool0 0 4>; + contribution = <1024>; + }; + cpucore_cooling_map { + trip = <&control>; + cooling-device = <&cpucore_cool0 0 3>; + contribution = <1024>; + }; + gpufreq_cooling_map { + trip = <&control>; + cooling-device = <&gpufreq_cool0 0 4>; + contribution = <1024>; + }; + gpucore_cooling_map { + trip = <&control>; + cooling-device = <&gpucore_cool0 0 2>; + contribution = <1024>; + }; + }; + }; + }; + + dwc3: dwc3@c9000000 { + compatible = "synopsys, dwc3"; + reg = <0xc9000000 0x100000>; + interrupts = <0 30 4>; + usb-phy = <&usb2_phy>, <&usb3_phy>; + cpu-type = "gxl"; + clock-src = "usb3.0"; + }; + + usb2_phy: usb2phy@d0078000 { + compatible = "amlogic, amlogic-new-usb2"; + portnum = <3>; + reg = <0xd0078000 0x80 + 0xc1104408 0x4>; + }; + + usb3_phy: usb3phy@d0078080 { + compatible = "amlogic, amlogic-new-usb3"; + portnum = <0>; + reg = <0xd0078080 0x20>; + }; + + dwc2_a { + compatible = "amlogic, dwc2"; + device_name = "dwc2_a"; + reg = <0xc9100000 0x40000>; + status = "okay"; + interrupts = <0 31 4>; + pl-periph-id = <0>; /** lm name */ + clock-src = "usb0"; /** clock src */ + port-id = <0>; /** ref to mach/usb.h */ + port-type = <2>; /** 0: otg, 1: host, 2: slave */ + port-speed = <0>; /** 0: default, high, 1: full */ + port-config = <0>; /** 0: default */ + port-dma = <0>; /** 0: default ... 6: disable*/ + port-id-mode = <0>; /** 0: hardware, 1: sw_host, 2: sw_slave*/ + usb-fifo = <728>; + cpu-type = "gxl"; + controller-type = <3>; /** 0: normal,1:host,2:device,3:otg*/ + phy-reg = <0xd0078000>; + phy-reg-size = <0xa0>; + clocks = <&clkc CLKID_USB_GENERAL + &clkc CLKID_USB1_TO_DDR + &clkc CLKID_USB1>; + clock-names = "usb_general", + "usb1", + "usb1_to_ddr"; + }; + + meson-amvideom { + compatible = "amlogic, amvideom"; + dev_name = "amvideom"; + status = "okay"; + interrupts = <0 3 1>; + interrupt-names = "vsync"; + }; + + vout { + compatible = "amlogic, vout"; + dev_name = "vout"; + status = "okay"; + fr_auto_policy = <0>; + }; + + cvbsout { + compatible = "amlogic, cvbsout-gxl"; + dev_name = "cvbsout"; + status = "okay"; + clocks = <&clkc CLKID_VCLK2_ENCI + &clkc CLKID_VCLK2_VENCI0 + &clkc CLKID_VCLK2_VENCI1 + &clkc CLKID_DAC_CLK>; + clock-names = "venci_top_gate", + "venci_0_gate", + "venci_1_gate", + "vdac_clk_gate"; + + /* performance: reg_address, reg_value */ + /* s905d */ + performance = <0x1bf0 0x9 + 0x1b56 0x343 + 0x1b12 0x8080 + 0x1b05 0xfd + 0x1c59 0xf752 + 0xffff 0x0>; /* ending flag */ + }; + + amhdmitx: amhdmitx{ + compatible = "amlogic, amhdmitx"; + dev_name = "amhdmitx"; + status = "okay"; + vend-data = <&vend_data>; + pinctrl-names="hdmitx_hpd", "hdmitx_ddc"; + pinctrl-0=<&hdmitx_hpd>; + pinctrl-1=<&hdmitx_ddc>; + /* HPD, 57 + 32 = 89; CEC, 151 + 32 = 183*/ + interrupts = <0 57 1>; + interrupt-names = "hdmitx_hpd"; + /* 0:M8B 1:GXBB 2:GXTVBB 3:GXL 4:GXM + * 5:TXL 6:TXLX 7:AXG 8:GXLX 9:TXHD + */ + ic_type = <3>; + vend_data: vend_data{ /* Should modified by Customer */ + vendor_name = "Amlogic"; /* Max Chars: 8 */ + /* standards.ieee.org/develop/regauth/oui/oui.txt */ + vendor_id = <0x000000>; + product_desc = "MBox Meson Ref"; /* Max Chars: 16 */ + }; + }; + + aocec: aocec{ + compatible = "amlogic, amlogic-aocec"; + device_name = "aocec"; + status = "okay"; + vendor_id = <0x000000>; + cec_osd_string = "MBox"; /* Max Chars: 14 */ + cec_version = <6>; /* 5: 1.4, 6: 2.0 */ + port_num = <1>; + arc_port_mask = <0x0>; + interrupts = <0 199 1>; + interrupt-names = "hdmi_aocec"; + pinctrl-names = "default"; + pinctrl-0=<&hdmitx_aocec>; + reg = <0xc810023c 0x4 + 0xc8100000 0x200>; + reg-names = "ao_exit","ao"; + }; + + sysled { + compatible = "amlogic, sysled"; + dev_name = "sysled"; + status = "disabled"; + led_gpio = <&gpio GPIODV_24 GPIO_ACTIVE_HIGH>; + led_active_low = <1>; + }; + + meson-fb { + compatible = "amlogic, meson-gxl"; + memory-region = <&logo_reserved>; + dev_name = "meson-fb"; + status = "okay"; + interrupts = <0 3 1 + 0 89 1>; + interrupt-names = "viu-vsync", "rdma"; + mem_size = <0x00800000 0x01800000 0x00100000>; + /* uboot logo,fb0/fb1 memory size,if afbcd fb0=0x01851000*/ + display_mode_default = "1080p60hz"; + scale_mode = <1>; + /** 0:VPU free scale 1:OSD free scale 2:OSD super scale */ + display_size_default = <1920 1080 1920 3240 32>; + /*1920*1080*4*3 = 0x17BB000*/ + mem_alloc = <1>; + logo_addr = "0x7dc00000"; + }; + ge2d { + compatible = "amlogic, ge2d-gxl"; + dev_name = "ge2d"; + status = "okay"; + interrupts = <0 150 1>; + interrupt-names = "ge2d"; + clocks = <&clkc CLKID_VAPB_MUX>, + <&clkc CLKID_G2D>, + <&clkc CLKID_GE2D_GATE>; + clock-names = "clk_vapb_0", + "clk_ge2d", + "clk_ge2d_gate"; + }; + + + /* AUDIO MESON DEVICES */ + i2s_dai: I2S { + #sound-dai-cells = <0>; + compatible = "amlogic, aml-i2s-dai"; + clocks = + <&clkc CLKID_MPLL2>, + <&clkc CLKID_AMCLK_COMP>, + <&clkc CLKID_AIU_GLUE>, + <&clkc CLKID_IEC958>, + <&clkc CLKID_I2S_OUT>, + <&clkc CLKID_AMCLK>, + <&clkc CLKID_AIFIFO2>, + <&clkc CLKID_MIXER>, + <&clkc CLKID_MIXER_IFACE>, + <&clkc CLKID_ADC>, + <&clkc CLKID_AIU_TOP>, + <&clkc CLKID_AOCLK_GATE>, + <&clkc CLKID_I2S_SPDIF>; + clock-names = + "mpll", + "mclk", + "top_glue", + "aud_buf", + "i2s_out", + "amclk_measure", + "aififo2", + "aud_mixer", + "mixer_reg", + "adc", + "top_level", + "aoclk", + "aud_in"; + i2s_pos_sync = <0>; + /*DMIC;*/ /* I2s Mic or Dmic, default for I2S mic */ + }; + dmic:snd_dmic { + #sound-dai-cells = <0>; + compatible = "aml, aml_snd_dmic"; + reg = <0xd0042000 0x2000>; + status = "okay"; + resets = < + &clkc CLKID_PDM_GATE + >; + reset-names = "pdm"; + pinctrl-names = "audio_dmic"; + pinctrl-0 = <&aml_dmic_pins>; + clocks = <&clkc CLKID_PDM_COMP>, + <&clkc CLKID_AMCLK_COMP>; + clock-names = "pdm", "mclk"; + }; + spdif_dai: SPDIF { + #sound-dai-cells = <0>; + compatible = "amlogic, aml-spdif-dai"; + clocks = + <&clkc CLKID_MPLL1>, + <&clkc CLKID_I958_COMP>, + <&clkc CLKID_AMCLK_COMP>, + <&clkc CLKID_I958_COMP_SPDIF>, + <&clkc CLKID_CLK81>, + <&clkc CLKID_IEC958>, + <&clkc CLKID_IEC958_GATE>; + clock-names = + "mpll1", + "i958", + "mclk", + "spdif", + "clk_81", + "iec958", + "iec958_amclk"; + }; + pcm_dai: PCM { + #sound-dai-cells = <0>; + compatible = "amlogic, aml-pcm-dai"; + pinctrl-names = "audio_pcm"; + pinctrl-0 = <&audio_pcm_pins>; + clocks = + <&clkc CLKID_MPLL0>, + <&clkc CLKID_PCM_MCLK_COMP>, + <&clkc CLKID_PCM_SCLK_GATE>; + clock-names = + "mpll0", + "pcm_mclk", + "pcm_sclk"; + pcm_mode = <1>; /* 0=slave mode, 1=master mode */ + }; + i2s_plat: i2s_platform { + compatible = "amlogic, aml-i2s"; + interrupts = <0 29 1>; + }; + pcm_plat: pcm_platform { + compatible = "amlogic, aml-pcm"; + }; + spdif_codec: spdif_codec{ + #sound-dai-cells = <0>; + compatible = "amlogic, aml-spdif-codec"; + pinctrl-names = "audio_spdif_out"; + pinctrl-0 = <&audio_spdif_out_pins>; + }; + pcm_codec: pcm_codec{ + #sound-dai-cells = <0>; + compatible = "amlogic, pcm2BT-codec"; + }; + /* endof AUDIO MESON DEVICES */ + + /* AUDIO board specific */ + dummy_codec:dummy{ + #sound-dai-cells = <0>; + compatible = "amlogic, aml_dummy_codec"; + status = "disable"; + }; + amlogic_codec:t9015{ + #sound-dai-cells = <0>; + compatible = "amlogic, aml_codec_T9015"; + reg = <0xc8832000 0x14>; + status = "okay"; + }; + aml_sound_meson { + compatible = "aml, meson-snd-card"; + status = "okay"; + aml-sound-card,format = "i2s"; + aml_sound_card,name = "AML-MESONAUDIO"; + aml,audio-routing = + "Ext Spk","LOUTL", + "Ext Spk","LOUTR"; + + mute_gpio-gpios = <&gpio GPIOH_5 0>; + mute_inv; + hp_disable; + hp_paraments = <800 300 0 5 1>; + pinctrl-names = "audio_i2s"; + pinctrl-0 = <&audio_i2s_pins>; + cpu_list = <&cpudai0 &cpudai1 &cpudai2>; + codec_list = <&codec0 &codec1 &codec2>; + plat_list = <&i2s_plat &i2s_plat &pcm_plat>; + cpudai0: cpudai0 { + sound-dai = <&i2s_dai>; + }; + cpudai1: cpudai1 { + sound-dai = <&spdif_dai>; + }; + cpudai2: cpudai2 { + sound-dai = <&pcm_dai>; + }; + codec0: codec0 { + sound-dai = <&amlogic_codec>; + }; + codec1: codec1 { + sound-dai = <&spdif_codec>; + }; + codec2: codec2 { + sound-dai = <&pcm_codec>; + }; + }; + /* END OF AUDIO board specific */ + rdma{ + compatible = "amlogic, meson, rdma"; + dev_name = "amlogic-rdma"; + status = "ok"; + interrupts = <0 89 1>; + interrupt-names = "rdma"; + }; + + amvenc_avc{ + compatible = "amlogic, amvenc_avc"; + dev_name = "amvenc_avc"; + status = "okay"; + interrupts = <0 45 1>; + interrupt-names = "mailbox_2"; + }; + + hevc_enc{ + compatible = "cnm, HevcEnc"; + dev_name = "HevcEnc"; + status = "okay"; + interrupts = <0 187 1>; + interrupt-names = "wave420l_irq"; + #address-cells=<1>; + #size-cells=<1>; + ranges; + io_reg_base{ + reg = <0xc8810000 0x4000>; + }; + }; + + partitions: partitions{ + parts = <12>; + part-0 = <&logo>; + part-1 = <&recovery>; + part-2 = <&rsv>; + part-3 = <&tee>; + part-4 = <&crypt>; + part-5 = <&misc>; + part-6 = <&boot>; + part-7 = <&system>; + part-8 = <&cache>; + part-9 = <&vendor>; + part-10 = <&odm>; + part-11 = <&data>; + + logo:logo{ + pname = "logo"; + size = <0x0 0x2000000>; + mask = <1>; + }; + recovery:recovery{ + pname = "recovery"; + size = <0x0 0x2000000>; + mask = <1>; + }; + rsv:rsv{ + pname = "rsv"; + size = <0x0 0x800000>; + mask = <1>; + }; + tee:tee{ + pname = "tee"; + size = <0x0 0x800000>; + mask = <1>; + }; + crypt:crypt{ + pname = "crypt"; + size = <0x0 0x2000000>; + mask = <1>; + }; + misc:misc{ + pname = "misc"; + size = <0x0 0x2000000>; + mask = <1>; + }; + boot:boot + { + pname = "boot"; + size = <0x0 0x2000000>; + mask = <1>; + }; + system:system + { + pname = "system"; + size = <0x0 0x80000000>; + mask = <1>; + }; + vendor:vendor + { + pname = "vendor"; + size = <0x0 0x10000000>; + mask = <1>; + }; + odm:odm + { + pname = "odm"; + size = <0x0 0x10000000>; + mask = <1>; + }; + cache:cache + { + pname = "cache"; + size = <0x0 0x20000000>; + mask = <2>; + }; + data:data + { + pname = "data"; + size = <0xffffffff 0xffffffff>; + mask = <4>; + }; + }; + + ppmgr { + compatible = "amlogic, ppmgr"; + memory-region = <&ppmgr_reserved>; + dev_name = "ppmgr"; + status = "okay"; + }; + + deinterlace { + compatible = "amlogic, deinterlace"; + status = "okay"; + flag_cma = <1>;/*0:use reserved;1:use cma*/ + //memory-region = <&di_reserved>; + memory-region = <&di_cma_reserved>; + interrupts = <0 46 1 0 6 1>; + interrupt-names = "de_irq", "timerc"; + /* + * nr_size(byte) = 1920*544*2(yuv422 8bit) | + * 1920*544*2*12/8(yuv422 10bit) + * | 1920*544*2*10/8(yuv422 10bit full pack mode) + */ + /* mtn_size(byte) = 1920*544/2 */ + /* count_size(byte) = 1920*544/2 */ + buffer-size = <3133440>; + hw-version = <2>; + }; + + ionvideo { + compatible = "amlogic, ionvideo"; + dev_name = "ionvideo"; + status = "okay"; + }; + + amlvideo { + compatible = "amlogic, amlvideo"; + dev_name = "amlvideo"; + status = "okay"; + }; + + amlvideo2_0 { + compatible = "amlogic, amlvideo2"; + dev_name = "amlvideo2"; + status = "okay"; + amlvideo2_id = <0>; + cma_mode = <1>; + }; + + amlvideo2_1 { + compatible = "amlogic, amlvideo2"; + dev_name = "amlvideo2"; + status = "okay"; + amlvideo2_id = <1>; + cma_mode = <1>; + }; + + /*if you want to use vdin just modify status to "ok"*/ + vdin0 { + compatible = "amlogic, vdin"; + /*memory-region = <&vdin0_cma_reserved>;*/ + dev_name = "vdin0"; + status = "ok"; + reserve-iomap = "true"; + flag_cma = <1>;/*1:share with codec_mm;2:cma alone*/ + /*MByte, if 10bit disable: 64M(YUV422), + *if 10bit enable: 64*1.5 = 96M(YUV422) + *if support 4K2K-YUV444-10bit-WR:3840*2160*4*4 ~= 128M + *if support 4K2K-YUV422-10bit-wr:3840*2160*3*4 ~= 96M + *if support 4K2K-YUV422-8BIT-WR:3840*2160*2*4 ~= 64M + *if support 1080p-YUV422-8BIT-WR:1920*1080*2*4 ~= 16M + */ + cma_size = <16>; + interrupts = <0 83 1>; + rdma-irq = <2>; + /*clocks = <&clock CLK_FPLL_DIV5>, + * <&clock CLK_VDIN_MEAS_CLK>; + *clock-names = "fclk_div5", "cts_vdin_meas_clk"; + */ + vdin_id = <0>; + /*vdin write mem color depth support: + *bit0:support 8bit + *bit1:support 9bit + *bit2:support 10bit + *bit3:support 12bit + *bit4:support yuv422 10bit full pack mode (from txl new add) + */ + tv_bit_mode = <1>; + }; + vdin1 { + compatible = "amlogic, vdin"; + memory-region = <&vdin1_cma_reserved>; + dev_name = "vdin1"; + status = "ok"; + reserve-iomap = "true"; + flag_cma = <0>;/*1:share with codec_mm;0:cma alone*/ + interrupts = <0 85 1>; + rdma-irq = <4>; + /*clocks = <&clock CLK_FPLL_DIV5>, + * <&clock CLK_VDIN_MEAS_CLK>; + *clock-names = "fclk_div5", "cts_vdin_meas_clk"; + */ + vdin_id = <1>; + /*vdin write mem color depth support: + *bit0:support 8bit + *bit1:support 9bit + *bit2:support 10bit + *bit3:support 12bit + */ + tv_bit_mode = <1>; + }; + amvdec_656in { + compatible = "amlogic, amvdec_656in"; + dev_name = "amvdec_656in"; + status = "disabled"; + reg = <0xd0048000 0x7c>, + <0xd0050000 0x7c>; + clocks = <&clkc CLKID_BT656_CLK1_COMP>, + <&clkc CLKID_BT656>, + <&clkc CLKID_BT656_PCLK1>; + clock-names = "cts_bt656_clk1", + "clk_gate_bt656", + "clk_gate_bt656_pclk1"; + + /* bt656in1, bt656in2 */ + bt656in1 { + bt656_id = <1>; + status = "okay"; + }; + }; + hdmirx_ext { + compatible = "amlogic, hdmirx_ext"; + dev_name = "hdmirx_ext"; + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&hdmirx_ext_pins>; + vdin_sel = <0>; + bt656_sel = <1>; + reset-gpios = <&gpio GPIODV_20 GPIO_ACTIVE_HIGH>; + reset_gpio_name = "GPIODV_20"; + reset_gpio_val = <0 1>; /* reset_on, reset_off */ + + ext_dev_name = "sii9135"; + i2c_addr = <0x30>; /* pull_up: 0x31, pull_down: 0x30 */ + i2c_bus = "i2c_bus_c"; + }; + + amlvecm { + compatible = "amlogic, vecm"; + dev_name = "aml_vecm"; + status = "okay"; + gamma_en = <0>;/*1:enabel ;0:disable*/ + wb_en = <0>;/*1:enabel ;0:disable*/ + cm_en = <0>;/*1:enabel ;0:disable*/ + /*1:enabel osd lut 100 table;0:disable*/ + cfg_en_osd_100 = <1>; + /*0: 709/601 1: bt2020*/ + tx_op_color_primary = <0>; + }; + + unifykey{ + compatible = "amlogic, unifykey"; + status = "ok"; + + unifykey-num = <15>; + unifykey-index-0 = <&keysn_0>; + unifykey-index-1 = <&keysn_1>; + unifykey-index-2 = <&keysn_2>; + unifykey-index-3 = <&keysn_3>; + unifykey-index-4 = <&keysn_4>; + unifykey-index-5 = <&keysn_5>; + unifykey-index-6 = <&keysn_6>; + unifykey-index-7 = <&keysn_7>; + unifykey-index-8 = <&keysn_8>; + unifykey-index-9 = <&keysn_9>; + unifykey-index-10= <&keysn_10>; + unifykey-index-11= <&keysn_11>; + unifykey-index-12= <&keysn_12>; + unifykey-index-13= <&keysn_13>; + unifykey-index-14= <&keysn_14>; + + keysn_0: key_0{ + key-name = "usid"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_1:key_1{ + key-name = "mac"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_2:key_2{ + key-name = "hdcp"; + key-device = "secure"; + key-type = "sha1"; + key-permit = "read","write","del"; + }; + keysn_3:key_3{ + key-name = "secure_boot_set"; + key-device = "efuse"; + key-permit = "write"; + }; + keysn_4:key_4{ + key-name = "mac_bt"; + key-device = "normal"; + key-permit = "read","write","del"; + key-type = "mac"; + }; + keysn_5:key_5{ + key-name = "mac_wifi"; + key-device = "normal"; + key-permit = "read","write","del"; + key-type = "mac"; + }; + keysn_6:key_6{ + key-name = "hdcp2_tx"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_7:key_7{ + key-name = "hdcp2_rx"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_8:key_8{ + key-name = "widevinekeybox"; + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_9:key_9{ + key-name = "deviceid"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_10:key_10{ + key-name = "hdcp22_fw_private"; + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_11:key_11{ + key-name = "PlayReadykeybox25"; + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_12:key_12{ + key-name = "prpubkeybox";// PlayReady + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_13:key_13{ + key-name = "prprivkeybox";// PlayReady + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_14:key_14{ + key-name = "attestationkeybox";// attestation key + key-device = "secure"; + key-permit = "read","write","del"; + }; + };//End unifykey +}; +&efuse { + status = "ok"; +}; + +&pwm_ef { + status = "okay"; +}; + +&audio_data{ + status = "okay"; +}; + +&pinctrl_periphs { + hdmirx_ext_pins: hdmirx_ext_pins { + mux { + groups = "dvp_vs", + "dvp_hs", + "dvp_clk", + "dvp_d2_9"; + function = "dvp"; + }; + }; + + /*spdif*/ + audio_spdif_out_pins: audio_spdif_out_pins { + mux { + groups = "spdif_out"; + function = "spdif_out"; + }; + }; +}; /* end of pinctrl_periphs */ + diff --git a/arch/arm/boot/dts/amlogic/gxl_p231_1g.dts b/arch/arm/boot/dts/amlogic/gxl_p231_1g.dts new file mode 100644 index 000000000000..8ca654332e4d --- /dev/null +++ b/arch/arm/boot/dts/amlogic/gxl_p231_1g.dts @@ -0,0 +1,1123 @@ +/* + * arch/arm/boot/dts/amlogic/gxl_p231_1g.dts + * + * Copyright (C) 2017 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +/dts-v1/; + +#include +#include "mesongxl.dtsi" +#include "partition_mbox_normal.dtsi" +/ { + model = "Amlogic"; + amlogic-dt-id = "gxl_p231_1g"; + compatible = "amlogic, Gxl"; + interrupt-parent = <&gic>; + #address-cells = <1>; + #size-cells = <1>; + + aliases { + serial0 = &uart_AO; + serial1 = &uart_A; + serial2 = &uart_B; + serial3 = &uart_C; + serial4 = &uart_AO_B; + }; + + ion_dev { + compatible = "amlogic, ion_dev"; + memory-region = <&ion_reserved>; + }; + + memory@00000000 { + device_type = "memory"; + linux,usable-memory = <0x0100000 0x3ff00000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + /* global autoconfigured region for contiguous allocations */ + ramoops@0x07400000 { + compatible = "ramoops"; + reg = <0x07400000 0x00100000>; + record-size = <0x8000>; + console-size = <0x8000>; + ftrace-size = <0x0>; + pmsg-size = <0x8000>; + }; + + secmon_reserved:linux,secmon { + compatible = "shared-dma-pool"; + reusable; + size = <0x400000>; + alignment = <0x400000>; + alloc-ranges = <0x05000000 0x400000>; + }; + secos_reserved:linux,secos { + status = "disable"; + compatible = "amlogic, aml_secos_memory"; + reg = <0x05300000 0x2000000>; + no-map; + }; + logo_reserved:linux,meson-fb { + compatible = "shared-dma-pool"; + reusable; + size = <0x800000>; + alignment = <0x400000>; + alloc-ranges = <0x3f800000 0x800000>; + }; + //don't put other dts in front of logo_reserved + + //di_reserved:linux,di { + // compatible = "amlogic, di-mem"; + /** 10x3133440=30M(0x1e) support 8bit **/ + // size = <0x0 0x1e00000>; + //no-map; + //}; + di_cma_reserved:linux,di_cma { + compatible = "shared-dma-pool"; + reusable; + /** 10x3133440=30M(0x1e) support 8bit **/ + size = <0x2000000>; + alignment = <0x400000>; + }; + ion_reserved:linux,ion-dev { + compatible = "shared-dma-pool"; + reusable; + size = <0x7C00000>; + alignment = <0x400000>; + alloc-ranges = <0x0 0x30000000>; + }; + + /* vdin0 CMA pool */ + //vdin0_cma_reserved:linux,vdin0_cma { + // compatible = "shared-dma-pool"; + // linux,phandle = <4>; + // reusable; + /* 1920x1080x2x4 =16+4 M */ + // size = <0x0 0x01400000>; + // alignment = <0x0 0x400000>; + //}; + /* vdin1 CMA pool */ + vdin1_cma_reserved:linux,vdin1_cma { + compatible = "shared-dma-pool"; + reusable; + /* 1920x1080x2x4 =16 M */ + size = <0x01000000>; + alignment = <0x400000>; + }; + /* POST PROCESS MANAGER */ + ppmgr_reserved:linux,ppmgr { + compatible = "shared-dma-pool"; + size = <0x0>; + }; + + codec_mm_cma:linux,codec_mm_cma { + compatible = "shared-dma-pool"; + reusable; + /* ion_codec_mm max can alloc size 80M*/ + size = <0xc000000>; + alignment = <0x400000>; + linux,contiguous-region; + }; + picdec_cma_reserved:linux,picdec { + compatible = "shared-dma-pool"; + reusable; + size = <0x0>; + alignment = <0x0>; + linux,contiguous-region; + }; + /* codec shared reserved */ + codec_mm_reserved:linux,codec_mm_reserved { + compatible = "amlogic, codec-mm-reserved"; + size = <0x0>; + alignment = <0x100000>; + //no-map; + }; + }; + + bt-dev{ + compatible = "amlogic, bt-dev"; + dev_name = "bt-dev"; + status = "okay"; + gpio_reset = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>; + }; + + wifi{ + compatible = "amlogic, aml_wifi"; + dev_name = "aml_wifi"; + status = "okay"; + interrupt_pin = <&gpio GPIOX_7 GPIO_ACTIVE_HIGH>; + irq_trigger_type = "GPIO_IRQ_LOW"; + power_on_pin = <&gpio GPIOX_6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_32k_pins>; + pwm_config = <&wifi_pwm_conf>; + }; + + wifi_pwm_conf:wifi_pwm_conf{ + pwm_channel1_conf { + pwms = <&pwm_ef MESON_PWM_0 30040 0>; + duty-cycle = <15020>; + times = <8>; + }; + pwm_channel2_conf { + pwms = <&pwm_ef MESON_PWM_2 30030 0>; + duty-cycle = <15015>; + times = <12>; + }; + }; + + sd_emmc_c: emmc@d0074000 { + status = "okay"; + compatible = "amlogic, meson-mmc-gxl"; + reg = <0xd0074000 0x2000>; + interrupts = <0 218 1>; + pinctrl-names = "emmc_clk_cmd_pins", "emmc_all_pins"; + pinctrl-0 = <&emmc_clk_cmd_pins>; + pinctrl-1 = <&emmc_conf_pull_up &emmc_conf_pull_done>; + clocks = <&clkc CLKID_SD_EMMC_C>, + <&clkc CLKID_SD_EMMC_C_P0_COMP>, + <&clkc CLKID_FCLK_DIV2>; + clock-names = "core", "clkin0", "clkin1"; + + bus-width = <8>; + cap-sd-highspeed; + cap-mmc-highspeed; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + + max-frequency = <200000000>; + non-removable; + disable-wp; + emmc { + pinname = "emmc"; + ocr_avail = <0x200080>; /**VDD voltage 3.3 ~ 3.4 */ + caps = "MMC_CAP_8_BIT_DATA", + "MMC_CAP_MMC_HIGHSPEED", + "MMC_CAP_SD_HIGHSPEED", + "MMC_CAP_NONREMOVABLE", + "MMC_CAP_1_8V_DDR", + "MMC_CAP_HW_RESET", + "MMC_CAP_ERASE", + "MMC_CAP_CMD23"; + caps2 = "MMC_CAP2_HS200", "MMC_CAP2_HS400"; + f_min = <400000>; + f_max = <100000000>; + max_req_size = <0x20000>; /**128KB*/ + gpio_dat3 = <&gpio BOOT_3 GPIO_ACTIVE_HIGH>; + hw_reset = <&gpio BOOT_9 GPIO_ACTIVE_HIGH>; + card_type = <1>; + /* 1:mmc card(include eMMC), + * 2:sd card(include tSD) + */ + }; + }; + + sd_emmc_b:sd@d0072000 { + status = "okay"; + compatible = "amlogic, meson-mmc-gxl"; + reg = <0xd0072000 0x2000>; + interrupts = <0 217 1>; + pinctrl-names = "sd_all_pins", + "sd_clk_cmd_pins", + "sd_1bit_pins", + "sd_clk_cmd_uart_pins", + "sd_1bit_uart_pins", + "sd_to_ao_uart_pins", + "ao_to_sd_uart_pins", + "ao_to_sd_jtag_pins", + "sd_to_ao_jtag_pins"; + pinctrl-0 = <&sd_all_pins>; + pinctrl-1 = <&sd_clk_cmd_pins>; + pinctrl-2 = <&sd_1bit_pins>; + pinctrl-3 = <&sd_to_ao_uart_clr_pins + &sd_clk_cmd_pins &ao_to_sd_uart_pins>; + pinctrl-4 = <&sd_to_ao_uart_clr_pins + &sd_1bit_pins &ao_to_sd_uart_pins>; + pinctrl-5 = <&sd_all_pins &sd_to_ao_uart_pins>; + pinctrl-6 = <&sd_to_ao_uart_clr_pins &ao_to_sd_uart_pins>; + pinctrl-7 = <&sd_to_ao_uart_clr_pins &ao_to_sd_uart_pins>; + pinctrl-8 = <&sd_all_pins &sd_to_ao_uart_pins>; + clocks = <&clkc CLKID_SD_EMMC_B>, + <&clkc CLKID_SD_EMMC_B_P0_COMP>, + <&clkc CLKID_FCLK_DIV2>; + clock-names = "core", "clkin0", "clkin1"; + + bus-width = <4>; + cap-sd-highspeed; + max-frequency = <100000000>; + disable-wp; + sd { + pinname = "sd"; + ocr_avail = <0x200080>; /**VDD voltage 3.3 ~ 3.4 */ + caps = "MMC_CAP_4_BIT_DATA", + "MMC_CAP_MMC_HIGHSPEED", + "MMC_CAP_SD_HIGHSPEED"; + /* "MMC_CAP_UHS_SDR12", + * "MMC_CAP_UHS_SDR25", + * "MMC_CAP_UHS_SDR50", + * "MMC_CAP_UHS_SDR104"; + */ + f_min = <400000>; + f_max = <100000000>; + max_req_size = <0x20000>; /**128KB*/ + gpio_dat3 = <&gpio CARD_4 GPIO_ACTIVE_HIGH>; + jtag_pin = <&gpio CARD_0 GPIO_ACTIVE_HIGH>; + gpio_cd = <&gpio CARD_6 GPIO_ACTIVE_HIGH>; + card_type = <5>; + /* 0:unknown, + * 1:mmc card(include eMMC), + * 2:sd card(include tSD), + * 3:sdio device(ie:sdio-wifi), + * 4:SD combo (IO+mem) card, + * 5:NON sdio device(means sd/mmc card), + * other:reserved + */ + }; + }; + + sd_emmc_a:sdio@d0070000 { + status = "okay"; + compatible = "amlogic, meson-mmc-gxl"; + reg = <0xd0070000 0x2000>; + interrupts = <0 216 4>; + pinctrl-names = "sdio_clk_cmd_pins", "sdio_all_pins"; + pinctrl-0 = <&sdio_clk_cmd_pins>; + pinctrl-1 = <&sdio_all_pins>; + clocks = <&clkc CLKID_SD_EMMC_A>, + <&clkc CLKID_SD_EMMC_A_P0_COMP>, + <&clkc CLKID_FCLK_DIV2>; + clock-names = "core", "clkin0", "clkin1"; + + bus-width = <4>; + cap-sd-highspeed; + cap-mmc-highspeed; + max-frequency = <100000000>; + non-removable; + disable-wp; + sdio { + pinname = "sdio"; + ocr_avail = <0x200080>; /**VDD voltage 3.3 ~ 3.4 */ + caps = "MMC_CAP_4_BIT_DATA", + "MMC_CAP_MMC_HIGHSPEED", + "MMC_CAP_SD_HIGHSPEED", + "MMC_CAP_NONREMOVABLE", + "MMC_CAP_UHS_SDR12", + "MMC_CAP_UHS_SDR25", + "MMC_CAP_UHS_SDR50", + "MMC_CAP_UHS_SDR104", + "MMC_PM_KEEP_POWER", + "MMC_CAP_SDIO_IRQ"; + f_min = <400000>; + f_max = <200000000>; + max_req_size = <0x20000>; /**128KB*/ + card_type = <3>; + /* 3:sdio device(ie:sdio-wifi), + * 4:SD combo (IO+mem) card + */ + }; + }; + + ethmac: ethernet@0xc9410000 { + compatible = "amlogic, gxbb-eth-dwmac"; + reg = <0xc9410000 0x10000 + 0xc8834540 0x8 + 0xc8834558 0xc>; + interrupts = <0 8 1>; + pinctrl-names = "external_eth_pins"; + pinctrl-0 = <&external_eth_pins>; + rst_pin-gpios = <&gpio GPIOZ_14 0>; + GPIOZ4_pin-gpios = <&gpio GPIOZ_4 0>; + GPIOZ5_pin-gpios = <&gpio GPIOZ_5 0>; + mc_val_internal_phy = <0x1800>; + mc_val_external_phy = <0x1621>; + cali_val = <0x20000>; + interrupt-names = "macirq"; + clocks = <&clkc CLKID_ETH>; + clock-names = "ethclk81"; + internal_phy=<1>; + }; + + codec_io { + compatible = "amlogic, codec_io"; + #address-cells=<1>; + #size-cells=<1>; + ranges; + io_cbus_base{ + reg = <0xC1100000 0x100000>; + }; + io_dos_base{ + reg = <0xc8820000 0x10000>; + }; + io_hiubus_base{ + reg = <0xc883c000 0x2000>; + }; + io_aobus_base{ + reg = <0xc8100000 0x100000>; + }; + io_vcbus_base{ + reg = <0xd0100000 0x40000>; + }; + io_dmc_base{ + reg = <0xc8838000 0x400>; + }; + }; + + codec_mm { + compatible = "amlogic, codec, mm"; + memory-region = <&codec_mm_cma &codec_mm_reserved>; + dev_name = "codec_mm"; + status = "okay"; + }; + + canvas{ + compatible = "amlogic, meson, canvas"; + dev_name = "amlogic-canvas"; + status = "ok"; + reg = <0xc8838000 0x400>; + }; + + mesonstream { + compatible = "amlogic, codec, streambuf"; + dev_name = "mesonstream"; + status = "okay"; + clocks = <&clkc CLKID_DOS_PARSER + &clkc CLKID_DEMUX + &clkc CLKID_DOS + &clkc CLKID_VDEC_MUX + &clkc CLKID_HCODEC_MUX + &clkc CLKID_HEVC_MUX>; + clock-names = "parser_top", + "demux", + "vdec", + "clk_vdec_mux", + "clk_hcodec_mux", + "clk_hevc_mux"; + }; + + vdec { + compatible = "amlogic, vdec"; + dev_name = "vdec.0"; + status = "okay"; + interrupts = <0 3 1 + 0 23 1 + 0 32 1 + 0 43 1 + 0 44 1 + 0 45 1>; + interrupt-names = "vsync", + "demux", + "parser", + "mailbox_0", + "mailbox_1", + "mailbox_2"; + }; + + aml_sensor0: aml-sensor@0 { + compatible = "amlogic, aml-thermal"; + device_name = "thermal"; + #thermal-sensor-cells = <1>; + cooling_devices { + cpufreq_cool_cluster0 { + min_state = <1000000>; + dyn_coeff = <140>; + cluster_id = <0>; + node_name = "cpufreq_cool0"; + device_type = "cpufreq"; + }; + cpucore_cool_cluster0 { + min_state = <1>; + dyn_coeff = <0>; + cluster_id = <0>; + node_name = "cpucore_cool0"; + device_type = "cpucore"; + }; + gpufreq_cool { + min_state = <400>; + dyn_coeff = <437>; + cluster_id = <0>; + node_name = "gpufreq_cool0"; + device_type = "gpufreq"; + }; + gpucore_cool { + min_state = <1>; + dyn_coeff = <0>; + cluster_id = <0>; + node_name = "gpucore_cool0"; + device_type = "gpucore"; + }; + }; + cpufreq_cool0:cpufreq_cool0 { + #cooling-cells = <2>; /* min followed by max */ + }; + cpucore_cool0:cpucore_cool0 { + #cooling-cells = <2>; /* min followed by max */ + }; + gpufreq_cool0:gpufreq_cool0 { + #cooling-cells = <2>; /* min followed by max */ + }; + gpucore_cool0:gpucore_cool0 { + #cooling-cells = <2>; /* min followed by max */ + }; + }; + thermal-zones { + soc_thermal { + polling-delay = <1000>; + polling-delay-passive = <100>; + sustainable-power = <2150>; + + thermal-sensors = <&aml_sensor0 3>; + + trips { + switch_on: trip-point@0 { + temperature = <70000>; + hysteresis = <1000>; + type = "passive"; + }; + control: trip-point@1 { + temperature = <80000>; + hysteresis = <1000>; + type = "passive"; + }; + hot: trip-point@2 { + temperature = <85000>; + hysteresis = <5000>; + type = "hot"; + }; + critical: trip-point@3 { + temperature = <260000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + + cooling-maps { + cpufreq_cooling_map { + trip = <&control>; + cooling-device = <&cpufreq_cool0 0 4>; + contribution = <1024>; + }; + cpucore_cooling_map { + trip = <&control>; + cooling-device = <&cpucore_cool0 0 3>; + contribution = <1024>; + }; + gpufreq_cooling_map { + trip = <&control>; + cooling-device = <&gpufreq_cool0 0 4>; + contribution = <1024>; + }; + gpucore_cooling_map { + trip = <&control>; + cooling-device = <&gpucore_cool0 0 2>; + contribution = <1024>; + }; + }; + }; + }; + + dwc3: dwc3@c9000000 { + compatible = "synopsys, dwc3"; + reg = <0xc9000000 0x100000>; + interrupts = <0 30 4>; + usb-phy = <&usb2_phy>, <&usb3_phy>; + cpu-type = "gxl"; + clock-src = "usb3.0"; + }; + + usb2_phy: usb2phy@d0078000 { + compatible = "amlogic, amlogic-new-usb2"; + portnum = <3>; + reg = <0xd0078000 0x80 + 0xc1104408 0x4>; + }; + + usb3_phy: usb3phy@d0078080 { + compatible = "amlogic, amlogic-new-usb3"; + portnum = <0>; + reg = <0xd0078080 0x20>; + }; + + dwc2_a { + compatible = "amlogic, dwc2"; + device_name = "dwc2_a"; + reg = <0xc9100000 0x40000>; + status = "okay"; + interrupts = <0 31 4>; + pl-periph-id = <0>; /** lm name */ + clock-src = "usb0"; /** clock src */ + port-id = <0>; /** ref to mach/usb.h */ + port-type = <2>; /** 0: otg, 1: host, 2: slave */ + port-speed = <0>; /** 0: default, high, 1: full */ + port-config = <0>; /** 0: default */ + port-dma = <0>; /** 0: default ... 6: disable*/ + port-id-mode = <0>; /** 0: hardware, 1: sw_host, 2: sw_slave*/ + usb-fifo = <728>; + cpu-type = "gxl"; + controller-type = <1>; /** 0: normal, 1: host, 2: device*/ + phy-reg = <0xd0078000>; + phy-reg-size = <0xa0>; + clocks = <&clkc CLKID_USB_GENERAL + &clkc CLKID_USB1_TO_DDR + &clkc CLKID_USB1>; + clock-names = "usb_general", + "usb1", + "usb1_to_ddr"; + }; + + meson-amvideom { + compatible = "amlogic, amvideom"; + dev_name = "amvideom"; + status = "okay"; + interrupts = <0 3 1>; + interrupt-names = "vsync"; + }; + + vout { + compatible = "amlogic, vout"; + dev_name = "vout"; + status = "okay"; + fr_auto_policy = <0>; + }; + + cvbsout { + compatible = "amlogic, cvbsout-gxl"; + dev_name = "cvbsout"; + status = "okay"; + clocks = <&clkc CLKID_VCLK2_ENCI + &clkc CLKID_VCLK2_VENCI0 + &clkc CLKID_VCLK2_VENCI1 + &clkc CLKID_DAC_CLK>; + clock-names = "venci_top_gate", + "venci_0_gate", + "venci_1_gate", + "vdac_clk_gate"; + + /* performance: reg_address, reg_value */ + /* s905d */ + performance = <0x1bf0 0x9 + 0x1b56 0x343 + 0x1b12 0x8080 + 0x1b05 0xfd + 0x1c59 0xf752 + 0xffff 0x0>; /* ending flag */ + }; + + amhdmitx: amhdmitx{ + compatible = "amlogic, amhdmitx"; + dev_name = "amhdmitx"; + status = "okay"; + vend-data = <&vend_data>; + pinctrl-names="hdmitx_hpd", "hdmitx_ddc"; + pinctrl-0=<&hdmitx_hpd>; + pinctrl-1=<&hdmitx_ddc>; + /* HPD, 57 + 32 = 89; CEC, 151 + 32 = 183*/ + interrupts = <0 57 1>; + interrupt-names = "hdmitx_hpd"; + /* 0:M8B 1:GXBB 2:GXTVBB 3:GXL 4:GXM + * 5:TXL 6:TXLX 7:AXG 8:GXLX 9:TXHD + */ + ic_type = <3>; + vend_data: vend_data{ /* Should modified by Customer */ + vendor_name = "Amlogic"; /* Max Chars: 8 */ + /* standards.ieee.org/develop/regauth/oui/oui.txt */ + vendor_id = <0x000000>; + product_desc = "MBox Meson Ref"; /* Max Chars: 16 */ + }; + }; + + aocec: aocec{ + compatible = "amlogic, amlogic-aocec"; + device_name = "aocec"; + status = "okay"; + vendor_id = <0x000000>; + cec_osd_string = "MBox"; /* Max Chars: 14 */ + cec_version = <5>; /* 5: 1.4, 6: 2.0 */ + port_num = <1>; + arc_port_mask = <0x0>; + interrupts = <0 199 1>; + interrupt-names = "hdmi_aocec"; + pinctrl-names = "default"; + pinctrl-0=<&hdmitx_aocec>; + reg = <0xc810023c 0x4 + 0xc8100000 0x200>; + reg-names = "ao_exit","ao"; + }; + + sysled { + compatible = "amlogic, sysled"; + dev_name = "sysled"; + status = "disabled"; + led_gpio = <&gpio GPIODV_24 GPIO_ACTIVE_HIGH>; + led_active_low = <1>; + }; + + meson-fb { + compatible = "amlogic, meson-gxl"; + memory-region = <&logo_reserved>; + dev_name = "meson-fb"; + status = "okay"; + interrupts = <0 3 1 + 0 89 1>; + interrupt-names = "viu-vsync", "rdma"; + mem_size = <0x00800000 0x01800000 0x00100000>; + /* uboot logo,fb0/fb1 memory size,if afbcd fb0=0x01851000*/ + display_mode_default = "1080p60hz"; + scale_mode = <1>; + /** 0:VPU free scale 1:OSD free scale 2:OSD super scale */ + display_size_default = <1920 1080 1920 3240 32>; + /*1920*1080*4*3 = 0x17BB000*/ + logo_addr = "0x3f800000"; + }; + ge2d { + compatible = "amlogic, ge2d-gxl"; + dev_name = "ge2d"; + status = "okay"; + interrupts = <0 150 1>; + interrupt-names = "ge2d"; + clocks = <&clkc CLKID_VAPB_MUX>, + <&clkc CLKID_G2D>, + <&clkc CLKID_GE2D_GATE>; + clock-names = "clk_vapb_0", + "clk_ge2d", + "clk_ge2d_gate"; + }; + + + /* AUDIO MESON DEVICES */ + i2s_dai: I2S { + #sound-dai-cells = <0>; + compatible = "amlogic, aml-i2s-dai"; + clocks = + <&clkc CLKID_MPLL2>, + <&clkc CLKID_AMCLK_COMP>, + <&clkc CLKID_AIU_GLUE>, + <&clkc CLKID_IEC958>, + <&clkc CLKID_I2S_OUT>, + <&clkc CLKID_AMCLK>, + <&clkc CLKID_AIFIFO2>, + <&clkc CLKID_MIXER>, + <&clkc CLKID_MIXER_IFACE>, + <&clkc CLKID_ADC>, + <&clkc CLKID_AIU_TOP>, + <&clkc CLKID_AOCLK_GATE>, + <&clkc CLKID_I2S_SPDIF>; + clock-names = + "mpll", + "mclk", + "top_glue", + "aud_buf", + "i2s_out", + "amclk_measure", + "aififo2", + "aud_mixer", + "mixer_reg", + "adc", + "top_level", + "aoclk", + "aud_in"; + i2s_pos_sync = <0>; + /*DMIC;*/ /* I2s Mic or Dmic, default for I2S mic */ + }; + dmic:snd_dmic { + #sound-dai-cells = <0>; + compatible = "aml, aml_snd_dmic"; + reg = <0xd0042000 0x2000>; + status = "okay"; + resets = < + &clkc CLKID_PDM_GATE + >; + reset-names = "pdm"; + pinctrl-names = "audio_dmic"; + pinctrl-0 = <&aml_dmic_pins>; + clocks = <&clkc CLKID_PDM_COMP>, + <&clkc CLKID_AMCLK_COMP>; + clock-names = "pdm", "mclk"; + }; + spdif_dai: SPDIF { + #sound-dai-cells = <0>; + compatible = "amlogic, aml-spdif-dai"; + clocks = + <&clkc CLKID_MPLL1>, + <&clkc CLKID_I958_COMP>, + <&clkc CLKID_AMCLK_COMP>, + <&clkc CLKID_I958_COMP_SPDIF>, + <&clkc CLKID_CLK81>, + <&clkc CLKID_IEC958>, + <&clkc CLKID_IEC958_GATE>; + clock-names = + "mpll1", + "i958", + "mclk", + "spdif", + "clk_81", + "iec958", + "iec958_amclk"; + }; + pcm_dai: PCM { + #sound-dai-cells = <0>; + compatible = "amlogic, aml-pcm-dai"; + pinctrl-names = "audio_pcm"; + pinctrl-0 = <&audio_pcm_pins>; + clocks = + <&clkc CLKID_MPLL0>, + <&clkc CLKID_PCM_MCLK_COMP>, + <&clkc CLKID_PCM_SCLK_GATE>; + clock-names = + "mpll0", + "pcm_mclk", + "pcm_sclk"; + pcm_mode = <1>; /* 0=slave mode, 1=master mode */ + }; + i2s_plat: i2s_platform { + compatible = "amlogic, aml-i2s"; + interrupts = <0 29 1>; + }; + pcm_plat: pcm_platform { + compatible = "amlogic, aml-pcm"; + }; + spdif_codec: spdif_codec{ + #sound-dai-cells = <0>; + compatible = "amlogic, aml-spdif-codec"; + pinctrl-names = "audio_spdif"; + pinctrl-0 = <&audio_spdif_pins>; + }; + pcm_codec: pcm_codec{ + #sound-dai-cells = <0>; + compatible = "amlogic, pcm2BT-codec"; + }; + /* endof AUDIO MESON DEVICES */ + + /* AUDIO board specific */ + dummy_codec:dummy{ + #sound-dai-cells = <0>; + compatible = "amlogic, aml_dummy_codec"; + status = "disable"; + }; + amlogic_codec:t9015{ + #sound-dai-cells = <0>; + compatible = "amlogic, aml_codec_T9015"; + reg = <0xc8832000 0x14>; + status = "okay"; + }; + aml_sound_meson { + compatible = "aml, meson-snd-card"; + status = "okay"; + aml-sound-card,format = "i2s"; + aml_sound_card,name = "AML-MESONAUDIO"; + aml,audio-routing = + "Ext Spk","LOUTL", + "Ext Spk","LOUTR"; + + mute_gpio-gpios = <&gpio GPIOH_5 0>; + mute_inv; + hp_disable; + hp_paraments = <800 300 0 5 1>; + pinctrl-names = "audio_i2s"; + pinctrl-0 = <&audio_i2s_pins>; + cpu_list = <&cpudai0 &cpudai1 &cpudai2>; + codec_list = <&codec0 &codec1 &codec2>; + plat_list = <&i2s_plat &i2s_plat &pcm_plat>; + cpudai0: cpudai0 { + sound-dai = <&i2s_dai>; + }; + cpudai1: cpudai1 { + sound-dai = <&spdif_dai>; + }; + cpudai2: cpudai2 { + sound-dai = <&pcm_dai>; + }; + codec0: codec0 { + sound-dai = <&amlogic_codec>; + }; + codec1: codec1 { + sound-dai = <&spdif_codec>; + }; + codec2: codec2 { + sound-dai = <&pcm_codec>; + }; + }; + /* END OF AUDIO board specific */ + rdma{ + compatible = "amlogic, meson, rdma"; + dev_name = "amlogic-rdma"; + status = "ok"; + interrupts = <0 89 1>; + interrupt-names = "rdma"; + }; + + amvenc_avc{ + compatible = "amlogic, amvenc_avc"; + dev_name = "amvenc_avc"; + status = "okay"; + interrupts = <0 45 1>; + interrupt-names = "mailbox_2"; + }; + + hevc_enc{ + compatible = "cnm, HevcEnc"; + dev_name = "HevcEnc"; + status = "okay"; + interrupts = <0 187 1>; + interrupt-names = "wave420l_irq"; + #address-cells=<1>; + #size-cells=<1>; + ranges; + io_reg_base{ + reg = <0xc8810000 0x4000>; + }; + }; + + picdec { + compatible = "amlogic, picdec"; + memory-region = <&picdec_cma_reserved>; + dev_name = "picdec"; + status = "okay"; + }; + + ppmgr { + compatible = "amlogic, ppmgr"; + memory-region = <&ppmgr_reserved>; + dev_name = "ppmgr"; + status = "okay"; + }; + + deinterlace { + compatible = "amlogic, deinterlace"; + status = "okay"; + flag_cma = <1>;/*0:use reserved;1:use cma*/ + //memory-region = <&di_reserved>; + memory-region = <&di_cma_reserved>; + interrupts = <0 46 1 0 6 1>; + interrupt-names = "de_irq", "timerc"; + /* + * nr_size(byte) = 1920*544*2(yuv422 8bit) | + * 1920*544*2*12/8(yuv422 10bit) + * | 1920*544*2*10/8(yuv422 10bit full pack mode) + */ + /* mtn_size(byte) = 1920*544/2 */ + /* count_size(byte) = 1920*544/2 */ + buffer-size = <3133440>; + hw-version = <2>; + }; + + ionvideo { + compatible = "amlogic, ionvideo"; + dev_name = "ionvideo"; + status = "okay"; + }; + + amlvideo { + compatible = "amlogic, amlvideo"; + dev_name = "amlvideo"; + status = "okay"; + }; + + amlvideo2_0 { + compatible = "amlogic, amlvideo2"; + dev_name = "amlvideo2"; + status = "okay"; + amlvideo2_id = <0>; + cma_mode = <1>; + }; + + amlvideo2_1 { + compatible = "amlogic, amlvideo2"; + dev_name = "amlvideo2"; + status = "okay"; + amlvideo2_id = <1>; + cma_mode = <1>; + }; + + /*if you want to use vdin just modify status to "ok"*/ + vdin0 { + compatible = "amlogic, vdin"; + /*memory-region = <&vdin0_cma_reserved>;*/ + dev_name = "vdin0"; + status = "ok"; + reserve-iomap = "true"; + flag_cma = <1>;/*1:share with codec_mm;2:cma alone*/ + /*MByte, if 10bit disable: 64M(YUV422), + *if 10bit enable: 64*1.5 = 96M(YUV422) + *if support 4K2K-YUV444-10bit-WR:3840*2160*4*4 ~= 128M + *if support 4K2K-YUV422-10bit-wr:3840*2160*3*4 ~= 96M + *if support 4K2K-YUV422-8BIT-WR:3840*2160*2*4 ~= 64M + *if support 1080p-YUV422-8BIT-WR:1920*1080*2*4 ~= 16M + */ + cma_size = <16>; + interrupts = <0 83 1>; + rdma-irq = <2>; + /*clocks = <&clock CLK_FPLL_DIV5>, + * <&clock CLK_VDIN_MEAS_CLK>; + *clock-names = "fclk_div5", "cts_vdin_meas_clk"; + */ + vdin_id = <0>; + /*vdin write mem color depth support: + *bit0:support 8bit + *bit1:support 9bit + *bit2:support 10bit + *bit3:support 12bit + *bit4:support yuv422 10bit full pack mode (from txl new add) + */ + tv_bit_mode = <1>; + }; + vdin1 { + compatible = "amlogic, vdin"; + memory-region = <&vdin1_cma_reserved>; + dev_name = "vdin1"; + status = "ok"; + reserve-iomap = "true"; + flag_cma = <0>;/*1:share with codec_mm;0:cma alone*/ + interrupts = <0 85 1>; + rdma-irq = <4>; + /*clocks = <&clock CLK_FPLL_DIV5>, + * <&clock CLK_VDIN_MEAS_CLK>; + *clock-names = "fclk_div5", "cts_vdin_meas_clk"; + */ + vdin_id = <1>; + /*vdin write mem color depth support: + *bit0:support 8bit + *bit1:support 9bit + *bit2:support 10bit + *bit3:support 12bit + */ + tv_bit_mode = <1>; + }; + + amlvecm { + compatible = "amlogic, vecm"; + dev_name = "aml_vecm"; + status = "okay"; + gamma_en = <0>;/*1:enabel ;0:disable*/ + wb_en = <0>;/*1:enabel ;0:disable*/ + cm_en = <0>;/*1:enabel ;0:disable*/ + /*1:enabel osd lut 100 table;0:disable*/ + cfg_en_osd_100 = <1>; + /*0: 709/601 1: bt2020*/ + tx_op_color_primary = <0>; + }; + + unifykey{ + compatible = "amlogic, unifykey"; + status = "ok"; + + unifykey-num = <15>; + unifykey-index-0 = <&keysn_0>; + unifykey-index-1 = <&keysn_1>; + unifykey-index-2 = <&keysn_2>; + unifykey-index-3 = <&keysn_3>; + unifykey-index-4 = <&keysn_4>; + unifykey-index-5 = <&keysn_5>; + unifykey-index-6 = <&keysn_6>; + unifykey-index-7 = <&keysn_7>; + unifykey-index-8 = <&keysn_8>; + unifykey-index-9 = <&keysn_9>; + unifykey-index-10= <&keysn_10>; + unifykey-index-11= <&keysn_11>; + unifykey-index-12= <&keysn_12>; + unifykey-index-13= <&keysn_13>; + unifykey-index-14= <&keysn_14>; + + keysn_0: key_0{ + key-name = "usid"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_1:key_1{ + key-name = "mac"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_2:key_2{ + key-name = "hdcp"; + key-device = "secure"; + key-type = "sha1"; + key-permit = "read","write","del"; + }; + keysn_3:key_3{ + key-name = "secure_boot_set"; + key-device = "efuse"; + key-permit = "write"; + }; + keysn_4:key_4{ + key-name = "mac_bt"; + key-device = "normal"; + key-permit = "read","write","del"; + key-type = "mac"; + }; + keysn_5:key_5{ + key-name = "mac_wifi"; + key-device = "normal"; + key-permit = "read","write","del"; + key-type = "mac"; + }; + keysn_6:key_6{ + key-name = "hdcp2_tx"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_7:key_7{ + key-name = "hdcp2_rx"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_8:key_8{ + key-name = "widevinekeybox"; + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_9:key_9{ + key-name = "deviceid"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_10:key_10{ + key-name = "hdcp22_fw_private"; + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_11:key_11{ + key-name = "PlayReadykeybox25"; + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_12:key_12{ + key-name = "prpubkeybox";// PlayReady + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_13:key_13{ + key-name = "prprivkeybox";// PlayReady + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_14:key_14{ + key-name = "attestationkeybox";// attestation key + key-device = "secure"; + key-permit = "read","write","del"; + }; + };//End unifykey +}; +&efuse { + status = "ok"; +}; + +&pwm_ef { + status = "okay"; +}; + diff --git a/arch/arm/boot/dts/amlogic/gxl_p231_2g.dts b/arch/arm/boot/dts/amlogic/gxl_p231_2g.dts new file mode 100644 index 000000000000..95e97dbd9967 --- /dev/null +++ b/arch/arm/boot/dts/amlogic/gxl_p231_2g.dts @@ -0,0 +1,1122 @@ +/* + * arch/arm/boot/dts/amlogic/gxl_p231_2g.dts + * + * Copyright (C) 2017 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +/dts-v1/; + +#include +#include "mesongxl.dtsi" +#include "partition_mbox_normal.dtsi" +/ { + model = "Amlogic"; + amlogic-dt-id = "gxl_p231_2g"; + compatible = "amlogic, Gxl"; + interrupt-parent = <&gic>; + #address-cells = <1>; + #size-cells = <1>; + + aliases { + serial0 = &uart_AO; + serial1 = &uart_A; + serial2 = &uart_B; + serial3 = &uart_C; + serial4 = &uart_AO_B; + }; + + ion_dev { + compatible = "amlogic, ion_dev"; + memory-region = <&ion_reserved>; + }; + + memory@00000000 { + device_type = "memory"; + linux,usable-memory = <0x0100000 0x7ff00000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + /* global autoconfigured region for contiguous allocations */ + ramoops@0x07400000 { + compatible = "ramoops"; + reg = <0x07400000 0x00100000>; + record-size = <0x8000>; + console-size = <0x8000>; + ftrace-size = <0x0>; + pmsg-size = <0x8000>; + }; + + secmon_reserved:linux,secmon { + compatible = "shared-dma-pool"; + reusable; + size = <0x400000>; + alignment = <0x400000>; + alloc-ranges = <0x05000000 0x400000>; + }; + secos_reserved:linux,secos { + status = "disable"; + compatible = "amlogic, aml_secos_memory"; + reg = <0x05300000 0x2000000>; + no-map; + }; + logo_reserved:linux,meson-fb { + compatible = "shared-dma-pool"; + reusable; + size = <0x800000>; + alignment = <0x400000>; + alloc-ranges = <0x7f800000 0x800000>; + }; + //don't put other dts in front of logo_reserved + + //di_reserved:linux,di { + // compatible = "amlogic, di-mem"; + /** 10x3133440=30M(0x1e) support 8bit **/ + // size = <0x0 0x1e00000>; + //no-map; + //}; + di_cma_reserved:linux,di_cma { + compatible = "shared-dma-pool"; + reusable; + /** 10x3133440=30M(0x1e) support 8bit **/ + size = <0x2000000>; + alignment = <0x400000>; + }; + ion_reserved:linux,ion-dev { + compatible = "shared-dma-pool"; + reusable; + size = <0x7C00000>; + alignment = <0x400000>; + }; + + /* vdin0 CMA pool */ + //vdin0_cma_reserved:linux,vdin0_cma { + // compatible = "shared-dma-pool"; + // linux,phandle = <4>; + // reusable; + /* 1920x1080x2x4 =16+4 M */ + // size = <0x01400000>; + // alignment = <0x400000>; + //}; + /* vdin1 CMA pool */ + vdin1_cma_reserved:linux,vdin1_cma { + compatible = "shared-dma-pool"; + reusable; + /* 1920x1080x2x4 =16 M */ + size = <0x01000000>; + alignment = <0x400000>; + }; + /* POST PROCESS MANAGER */ + ppmgr_reserved:linux,ppmgr { + compatible = "shared-dma-pool"; + size = <0x0>; + }; + + codec_mm_cma:linux,codec_mm_cma { + compatible = "shared-dma-pool"; + reusable; + /* ion_codec_mm max can alloc size 80M*/ + size = <0x13400000>; + alignment = <0x400000>; + linux,contiguous-region; + }; + picdec_cma_reserved:linux,picdec { + compatible = "shared-dma-pool"; + reusable; + size = <0x0>; + alignment = <0x0>; + linux,contiguous-region; + }; + /* codec shared reserved */ + codec_mm_reserved:linux,codec_mm_reserved { + compatible = "amlogic, codec-mm-reserved"; + size = <0x0>; + alignment = <0x100000>; + //no-map; + }; + }; + + bt-dev{ + compatible = "amlogic, bt-dev"; + dev_name = "bt-dev"; + status = "okay"; + gpio_reset = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>; + }; + + wifi{ + compatible = "amlogic, aml_wifi"; + dev_name = "aml_wifi"; + status = "okay"; + interrupt_pin = <&gpio GPIOX_7 GPIO_ACTIVE_HIGH>; + irq_trigger_type = "GPIO_IRQ_LOW"; + power_on_pin = <&gpio GPIOX_6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_32k_pins>; + pwm_config = <&wifi_pwm_conf>; + }; + + wifi_pwm_conf:wifi_pwm_conf{ + pwm_channel1_conf { + pwms = <&pwm_ef MESON_PWM_0 30040 0>; + duty-cycle = <15020>; + times = <8>; + }; + pwm_channel2_conf { + pwms = <&pwm_ef MESON_PWM_2 30030 0>; + duty-cycle = <15015>; + times = <12>; + }; + }; + + sd_emmc_c: emmc@d0074000 { + status = "okay"; + compatible = "amlogic, meson-mmc-gxl"; + reg = <0xd0074000 0x2000>; + interrupts = <0 218 1>; + pinctrl-names = "emmc_clk_cmd_pins", "emmc_all_pins"; + pinctrl-0 = <&emmc_clk_cmd_pins>; + pinctrl-1 = <&emmc_conf_pull_up &emmc_conf_pull_done>; + clocks = <&clkc CLKID_SD_EMMC_C>, + <&clkc CLKID_SD_EMMC_C_P0_COMP>, + <&clkc CLKID_FCLK_DIV2>; + clock-names = "core", "clkin0", "clkin1"; + + bus-width = <8>; + cap-sd-highspeed; + cap-mmc-highspeed; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + + max-frequency = <200000000>; + non-removable; + disable-wp; + emmc { + pinname = "emmc"; + ocr_avail = <0x200080>; /**VDD voltage 3.3 ~ 3.4 */ + caps = "MMC_CAP_8_BIT_DATA", + "MMC_CAP_MMC_HIGHSPEED", + "MMC_CAP_SD_HIGHSPEED", + "MMC_CAP_NONREMOVABLE", + "MMC_CAP_1_8V_DDR", + "MMC_CAP_HW_RESET", + "MMC_CAP_ERASE", + "MMC_CAP_CMD23"; + caps2 = "MMC_CAP2_HS200", "MMC_CAP2_HS400"; + f_min = <400000>; + f_max = <100000000>; + max_req_size = <0x20000>; /**128KB*/ + gpio_dat3 = <&gpio BOOT_3 GPIO_ACTIVE_HIGH>; + hw_reset = <&gpio BOOT_9 GPIO_ACTIVE_HIGH>; + card_type = <1>; + /* 1:mmc card(include eMMC), + * 2:sd card(include tSD) + */ + }; + }; + + sd_emmc_b:sd@d0072000 { + status = "okay"; + compatible = "amlogic, meson-mmc-gxl"; + reg = <0xd0072000 0x2000>; + interrupts = <0 217 1>; + pinctrl-names = "sd_all_pins", + "sd_clk_cmd_pins", + "sd_1bit_pins", + "sd_clk_cmd_uart_pins", + "sd_1bit_uart_pins", + "sd_to_ao_uart_pins", + "ao_to_sd_uart_pins", + "ao_to_sd_jtag_pins", + "sd_to_ao_jtag_pins"; + pinctrl-0 = <&sd_all_pins>; + pinctrl-1 = <&sd_clk_cmd_pins>; + pinctrl-2 = <&sd_1bit_pins>; + pinctrl-3 = <&sd_to_ao_uart_clr_pins + &sd_clk_cmd_pins &ao_to_sd_uart_pins>; + pinctrl-4 = <&sd_to_ao_uart_clr_pins + &sd_1bit_pins &ao_to_sd_uart_pins>; + pinctrl-5 = <&sd_all_pins &sd_to_ao_uart_pins>; + pinctrl-6 = <&sd_to_ao_uart_clr_pins &ao_to_sd_uart_pins>; + pinctrl-7 = <&sd_to_ao_uart_clr_pins &ao_to_sd_uart_pins>; + pinctrl-8 = <&sd_all_pins &sd_to_ao_uart_pins>; + clocks = <&clkc CLKID_SD_EMMC_B>, + <&clkc CLKID_SD_EMMC_B_P0_COMP>, + <&clkc CLKID_FCLK_DIV2>; + clock-names = "core", "clkin0", "clkin1"; + + bus-width = <4>; + cap-sd-highspeed; + max-frequency = <100000000>; + disable-wp; + sd { + pinname = "sd"; + ocr_avail = <0x200080>; /**VDD voltage 3.3 ~ 3.4 */ + caps = "MMC_CAP_4_BIT_DATA", + "MMC_CAP_MMC_HIGHSPEED", + "MMC_CAP_SD_HIGHSPEED"; + /* "MMC_CAP_UHS_SDR12", + * "MMC_CAP_UHS_SDR25", + * "MMC_CAP_UHS_SDR50", + * "MMC_CAP_UHS_SDR104"; + */ + f_min = <400000>; + f_max = <100000000>; + max_req_size = <0x20000>; /**128KB*/ + gpio_dat3 = <&gpio CARD_4 GPIO_ACTIVE_HIGH>; + jtag_pin = <&gpio CARD_0 GPIO_ACTIVE_HIGH>; + gpio_cd = <&gpio CARD_6 GPIO_ACTIVE_HIGH>; + card_type = <5>; + /* 0:unknown, + * 1:mmc card(include eMMC), + * 2:sd card(include tSD), + * 3:sdio device(ie:sdio-wifi), + * 4:SD combo (IO+mem) card, + * 5:NON sdio device(means sd/mmc card), + * other:reserved + */ + }; + }; + + sd_emmc_a:sdio@d0070000 { + status = "okay"; + compatible = "amlogic, meson-mmc-gxl"; + reg = <0xd0070000 0x2000>; + interrupts = <0 216 4>; + pinctrl-names = "sdio_clk_cmd_pins", "sdio_all_pins"; + pinctrl-0 = <&sdio_clk_cmd_pins>; + pinctrl-1 = <&sdio_all_pins>; + clocks = <&clkc CLKID_SD_EMMC_A>, + <&clkc CLKID_SD_EMMC_A_P0_COMP>, + <&clkc CLKID_FCLK_DIV2>; + clock-names = "core", "clkin0", "clkin1"; + + bus-width = <4>; + cap-sd-highspeed; + cap-mmc-highspeed; + max-frequency = <100000000>; + non-removable; + disable-wp; + sdio { + pinname = "sdio"; + ocr_avail = <0x200080>; /**VDD voltage 3.3 ~ 3.4 */ + caps = "MMC_CAP_4_BIT_DATA", + "MMC_CAP_MMC_HIGHSPEED", + "MMC_CAP_SD_HIGHSPEED", + "MMC_CAP_NONREMOVABLE", + "MMC_CAP_UHS_SDR12", + "MMC_CAP_UHS_SDR25", + "MMC_CAP_UHS_SDR50", + "MMC_CAP_UHS_SDR104", + "MMC_PM_KEEP_POWER", + "MMC_CAP_SDIO_IRQ"; + f_min = <400000>; + f_max = <200000000>; + max_req_size = <0x20000>; /**128KB*/ + card_type = <3>; + /* 3:sdio device(ie:sdio-wifi), + * 4:SD combo (IO+mem) card + */ + }; + }; + + ethmac: ethernet@0xc9410000 { + compatible = "amlogic, gxbb-eth-dwmac"; + reg = <0xc9410000 0x10000 + 0xc8834540 0x8 + 0xc8834558 0xc>; + interrupts = <0 8 1>; + pinctrl-names = "external_eth_pins"; + pinctrl-0 = <&external_eth_pins>; + rst_pin-gpios = <&gpio GPIOZ_14 0>; + GPIOZ4_pin-gpios = <&gpio GPIOZ_4 0>; + GPIOZ5_pin-gpios = <&gpio GPIOZ_5 0>; + mc_val_internal_phy = <0x1800>; + mc_val_external_phy = <0x1621>; + cali_val = <0x20000>; + interrupt-names = "macirq"; + clocks = <&clkc CLKID_ETH>; + clock-names = "ethclk81"; + internal_phy=<1>; + }; + + codec_io { + compatible = "amlogic, codec_io"; + #address-cells=<1>; + #size-cells=<1>; + ranges; + io_cbus_base{ + reg = <0xC1100000 0x100000>; + }; + io_dos_base{ + reg = <0xc8820000 0x10000>; + }; + io_hiubus_base{ + reg = <0xc883c000 0x2000>; + }; + io_aobus_base{ + reg = <0xc8100000 0x100000>; + }; + io_vcbus_base{ + reg = <0xd0100000 0x40000>; + }; + io_dmc_base{ + reg = <0xc8838000 0x400>; + }; + }; + + codec_mm { + compatible = "amlogic, codec, mm"; + memory-region = <&codec_mm_cma &codec_mm_reserved>; + dev_name = "codec_mm"; + status = "okay"; + }; + + canvas{ + compatible = "amlogic, meson, canvas"; + dev_name = "amlogic-canvas"; + status = "ok"; + reg = <0xc8838000 0x400>; + }; + + mesonstream { + compatible = "amlogic, codec, streambuf"; + dev_name = "mesonstream"; + status = "okay"; + clocks = <&clkc CLKID_DOS_PARSER + &clkc CLKID_DEMUX + &clkc CLKID_DOS + &clkc CLKID_VDEC_MUX + &clkc CLKID_HCODEC_MUX + &clkc CLKID_HEVC_MUX>; + clock-names = "parser_top", + "demux", + "vdec", + "clk_vdec_mux", + "clk_hcodec_mux", + "clk_hevc_mux"; + }; + + vdec { + compatible = "amlogic, vdec"; + dev_name = "vdec.0"; + status = "okay"; + interrupts = <0 3 1 + 0 23 1 + 0 32 1 + 0 43 1 + 0 44 1 + 0 45 1>; + interrupt-names = "vsync", + "demux", + "parser", + "mailbox_0", + "mailbox_1", + "mailbox_2"; + }; + + aml_sensor0: aml-sensor@0 { + compatible = "amlogic, aml-thermal"; + device_name = "thermal"; + #thermal-sensor-cells = <1>; + cooling_devices { + cpufreq_cool_cluster0 { + min_state = <1000000>; + dyn_coeff = <140>; + cluster_id = <0>; + node_name = "cpufreq_cool0"; + device_type = "cpufreq"; + }; + cpucore_cool_cluster0 { + min_state = <1>; + dyn_coeff = <0>; + cluster_id = <0>; + node_name = "cpucore_cool0"; + device_type = "cpucore"; + }; + gpufreq_cool { + min_state = <400>; + dyn_coeff = <437>; + cluster_id = <0>; + node_name = "gpufreq_cool0"; + device_type = "gpufreq"; + }; + gpucore_cool { + min_state = <1>; + dyn_coeff = <0>; + cluster_id = <0>; + node_name = "gpucore_cool0"; + device_type = "gpucore"; + }; + }; + cpufreq_cool0:cpufreq_cool0 { + #cooling-cells = <2>; /* min followed by max */ + }; + cpucore_cool0:cpucore_cool0 { + #cooling-cells = <2>; /* min followed by max */ + }; + gpufreq_cool0:gpufreq_cool0 { + #cooling-cells = <2>; /* min followed by max */ + }; + gpucore_cool0:gpucore_cool0 { + #cooling-cells = <2>; /* min followed by max */ + }; + }; + thermal-zones { + soc_thermal { + polling-delay = <1000>; + polling-delay-passive = <100>; + sustainable-power = <2150>; + + thermal-sensors = <&aml_sensor0 3>; + + trips { + switch_on: trip-point@0 { + temperature = <70000>; + hysteresis = <1000>; + type = "passive"; + }; + control: trip-point@1 { + temperature = <80000>; + hysteresis = <1000>; + type = "passive"; + }; + hot: trip-point@2 { + temperature = <85000>; + hysteresis = <5000>; + type = "hot"; + }; + critical: trip-point@3 { + temperature = <260000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + + cooling-maps { + cpufreq_cooling_map { + trip = <&control>; + cooling-device = <&cpufreq_cool0 0 4>; + contribution = <1024>; + }; + cpucore_cooling_map { + trip = <&control>; + cooling-device = <&cpucore_cool0 0 3>; + contribution = <1024>; + }; + gpufreq_cooling_map { + trip = <&control>; + cooling-device = <&gpufreq_cool0 0 4>; + contribution = <1024>; + }; + gpucore_cooling_map { + trip = <&control>; + cooling-device = <&gpucore_cool0 0 2>; + contribution = <1024>; + }; + }; + }; + }; + + dwc3: dwc3@c9000000 { + compatible = "synopsys, dwc3"; + reg = <0xc9000000 0x100000>; + interrupts = <0 30 4>; + usb-phy = <&usb2_phy>, <&usb3_phy>; + cpu-type = "gxl"; + clock-src = "usb3.0"; + }; + + usb2_phy: usb2phy@d0078000 { + compatible = "amlogic, amlogic-new-usb2"; + portnum = <3>; + reg = <0xd0078000 0x80 + 0xc1104408 0x4>; + }; + + usb3_phy: usb3phy@d0078080 { + compatible = "amlogic, amlogic-new-usb3"; + portnum = <0>; + reg = <0xd0078080 0x20>; + }; + + dwc2_a { + compatible = "amlogic, dwc2"; + device_name = "dwc2_a"; + reg = <0xc9100000 0x40000>; + status = "okay"; + interrupts = <0 31 4>; + pl-periph-id = <0>; /** lm name */ + clock-src = "usb0"; /** clock src */ + port-id = <0>; /** ref to mach/usb.h */ + port-type = <2>; /** 0: otg, 1: host, 2: slave */ + port-speed = <0>; /** 0: default, high, 1: full */ + port-config = <0>; /** 0: default */ + port-dma = <0>; /** 0: default ... 6: disable*/ + port-id-mode = <0>; /** 0: hardware, 1: sw_host, 2: sw_slave*/ + usb-fifo = <728>; + cpu-type = "gxl"; + controller-type = <1>; /** 0: normal, 1: host, 2: device*/ + phy-reg = <0xd0078000>; + phy-reg-size = <0xa0>; + clocks = <&clkc CLKID_USB_GENERAL + &clkc CLKID_USB1_TO_DDR + &clkc CLKID_USB1>; + clock-names = "usb_general", + "usb1", + "usb1_to_ddr"; + }; + + meson-amvideom { + compatible = "amlogic, amvideom"; + dev_name = "amvideom"; + status = "okay"; + interrupts = <0 3 1>; + interrupt-names = "vsync"; + }; + + vout { + compatible = "amlogic, vout"; + dev_name = "vout"; + status = "okay"; + fr_auto_policy = <0>; + }; + + cvbsout { + compatible = "amlogic, cvbsout-gxl"; + dev_name = "cvbsout"; + status = "okay"; + clocks = <&clkc CLKID_VCLK2_ENCI + &clkc CLKID_VCLK2_VENCI0 + &clkc CLKID_VCLK2_VENCI1 + &clkc CLKID_DAC_CLK>; + clock-names = "venci_top_gate", + "venci_0_gate", + "venci_1_gate", + "vdac_clk_gate"; + + /* performance: reg_address, reg_value */ + /* s905d */ + performance = <0x1bf0 0x9 + 0x1b56 0x343 + 0x1b12 0x8080 + 0x1b05 0xfd + 0x1c59 0xf752 + 0xffff 0x0>; /* ending flag */ + }; + + amhdmitx: amhdmitx{ + compatible = "amlogic, amhdmitx"; + dev_name = "amhdmitx"; + status = "okay"; + vend-data = <&vend_data>; + pinctrl-names="hdmitx_hpd", "hdmitx_ddc"; + pinctrl-0=<&hdmitx_hpd>; + pinctrl-1=<&hdmitx_ddc>; + /* HPD, 57 + 32 = 89; CEC, 151 + 32 = 183*/ + interrupts = <0 57 1>; + interrupt-names = "hdmitx_hpd"; + /* 0:M8B 1:GXBB 2:GXTVBB 3:GXL 4:GXM + * 5:TXL 6:TXLX 7:AXG 8:GXLX 9:TXHD + */ + ic_type = <3>; + vend_data: vend_data{ /* Should modified by Customer */ + vendor_name = "Amlogic"; /* Max Chars: 8 */ + /* standards.ieee.org/develop/regauth/oui/oui.txt */ + vendor_id = <0x000000>; + product_desc = "MBox Meson Ref"; /* Max Chars: 16 */ + }; + }; + + aocec: aocec{ + compatible = "amlogic, amlogic-aocec"; + device_name = "aocec"; + status = "okay"; + vendor_id = <0x000000>; + cec_osd_string = "MBox"; /* Max Chars: 14 */ + cec_version = <5>; /* 5: 1.4, 6: 2.0 */ + port_num = <1>; + arc_port_mask = <0x0>; + interrupts = <0 199 1>; + interrupt-names = "hdmi_aocec"; + pinctrl-names = "default"; + pinctrl-0=<&hdmitx_aocec>; + reg = <0xc810023c 0x4 + 0xc8100000 0x200>; + reg-names = "ao_exit","ao"; + }; + + sysled { + compatible = "amlogic, sysled"; + dev_name = "sysled"; + status = "disabled"; + led_gpio = <&gpio GPIODV_24 GPIO_ACTIVE_HIGH>; + led_active_low = <1>; + }; + + meson-fb { + compatible = "amlogic, meson-gxl"; + memory-region = <&logo_reserved>; + dev_name = "meson-fb"; + status = "okay"; + interrupts = <0 3 1 + 0 89 1>; + interrupt-names = "viu-vsync", "rdma"; + mem_size = <0x00800000 0x01800000 0x00100000>; + /* uboot logo,fb0/fb1 memory size,if afbcd fb0=0x01851000*/ + display_mode_default = "1080p60hz"; + scale_mode = <1>; + /** 0:VPU free scale 1:OSD free scale 2:OSD super scale */ + display_size_default = <1920 1080 1920 3240 32>; + /*1920*1080*4*3 = 0x17BB000*/ + logo_addr = "0x7f800000"; + }; + ge2d { + compatible = "amlogic, ge2d-gxl"; + dev_name = "ge2d"; + status = "okay"; + interrupts = <0 150 1>; + interrupt-names = "ge2d"; + clocks = <&clkc CLKID_VAPB_MUX>, + <&clkc CLKID_G2D>, + <&clkc CLKID_GE2D_GATE>; + clock-names = "clk_vapb_0", + "clk_ge2d", + "clk_ge2d_gate"; + }; + + + /* AUDIO MESON DEVICES */ + i2s_dai: I2S { + #sound-dai-cells = <0>; + compatible = "amlogic, aml-i2s-dai"; + clocks = + <&clkc CLKID_MPLL2>, + <&clkc CLKID_AMCLK_COMP>, + <&clkc CLKID_AIU_GLUE>, + <&clkc CLKID_IEC958>, + <&clkc CLKID_I2S_OUT>, + <&clkc CLKID_AMCLK>, + <&clkc CLKID_AIFIFO2>, + <&clkc CLKID_MIXER>, + <&clkc CLKID_MIXER_IFACE>, + <&clkc CLKID_ADC>, + <&clkc CLKID_AIU_TOP>, + <&clkc CLKID_AOCLK_GATE>, + <&clkc CLKID_I2S_SPDIF>; + clock-names = + "mpll", + "mclk", + "top_glue", + "aud_buf", + "i2s_out", + "amclk_measure", + "aififo2", + "aud_mixer", + "mixer_reg", + "adc", + "top_level", + "aoclk", + "aud_in"; + i2s_pos_sync = <0>; + /*DMIC;*/ /* I2s Mic or Dmic, default for I2S mic */ + }; + dmic:snd_dmic { + #sound-dai-cells = <0>; + compatible = "aml, aml_snd_dmic"; + reg = <0xd0042000 0x2000>; + status = "okay"; + resets = < + &clkc CLKID_PDM_GATE + >; + reset-names = "pdm"; + pinctrl-names = "audio_dmic"; + pinctrl-0 = <&aml_dmic_pins>; + clocks = <&clkc CLKID_PDM_COMP>, + <&clkc CLKID_AMCLK_COMP>; + clock-names = "pdm", "mclk"; + }; + spdif_dai: SPDIF { + #sound-dai-cells = <0>; + compatible = "amlogic, aml-spdif-dai"; + clocks = + <&clkc CLKID_MPLL1>, + <&clkc CLKID_I958_COMP>, + <&clkc CLKID_AMCLK_COMP>, + <&clkc CLKID_I958_COMP_SPDIF>, + <&clkc CLKID_CLK81>, + <&clkc CLKID_IEC958>, + <&clkc CLKID_IEC958_GATE>; + clock-names = + "mpll1", + "i958", + "mclk", + "spdif", + "clk_81", + "iec958", + "iec958_amclk"; + }; + pcm_dai: PCM { + #sound-dai-cells = <0>; + compatible = "amlogic, aml-pcm-dai"; + pinctrl-names = "audio_pcm"; + pinctrl-0 = <&audio_pcm_pins>; + clocks = + <&clkc CLKID_MPLL0>, + <&clkc CLKID_PCM_MCLK_COMP>, + <&clkc CLKID_PCM_SCLK_GATE>; + clock-names = + "mpll0", + "pcm_mclk", + "pcm_sclk"; + pcm_mode = <1>; /* 0=slave mode, 1=master mode */ + }; + i2s_plat: i2s_platform { + compatible = "amlogic, aml-i2s"; + interrupts = <0 29 1>; + }; + pcm_plat: pcm_platform { + compatible = "amlogic, aml-pcm"; + }; + spdif_codec: spdif_codec{ + #sound-dai-cells = <0>; + compatible = "amlogic, aml-spdif-codec"; + pinctrl-names = "audio_spdif"; + pinctrl-0 = <&audio_spdif_pins>; + }; + pcm_codec: pcm_codec{ + #sound-dai-cells = <0>; + compatible = "amlogic, pcm2BT-codec"; + }; + /* endof AUDIO MESON DEVICES */ + + /* AUDIO board specific */ + dummy_codec:dummy{ + #sound-dai-cells = <0>; + compatible = "amlogic, aml_dummy_codec"; + status = "disable"; + }; + amlogic_codec:t9015{ + #sound-dai-cells = <0>; + compatible = "amlogic, aml_codec_T9015"; + reg = <0xc8832000 0x14>; + status = "okay"; + }; + aml_sound_meson { + compatible = "aml, meson-snd-card"; + status = "okay"; + aml-sound-card,format = "i2s"; + aml_sound_card,name = "AML-MESONAUDIO"; + aml,audio-routing = + "Ext Spk","LOUTL", + "Ext Spk","LOUTR"; + + mute_gpio-gpios = <&gpio GPIOH_5 0>; + mute_inv; + hp_disable; + hp_paraments = <800 300 0 5 1>; + pinctrl-names = "audio_i2s"; + pinctrl-0 = <&audio_i2s_pins>; + cpu_list = <&cpudai0 &cpudai1 &cpudai2>; + codec_list = <&codec0 &codec1 &codec2>; + plat_list = <&i2s_plat &i2s_plat &pcm_plat>; + cpudai0: cpudai0 { + sound-dai = <&i2s_dai>; + }; + cpudai1: cpudai1 { + sound-dai = <&spdif_dai>; + }; + cpudai2: cpudai2 { + sound-dai = <&pcm_dai>; + }; + codec0: codec0 { + sound-dai = <&amlogic_codec>; + }; + codec1: codec1 { + sound-dai = <&spdif_codec>; + }; + codec2: codec2 { + sound-dai = <&pcm_codec>; + }; + }; + /* END OF AUDIO board specific */ + rdma{ + compatible = "amlogic, meson, rdma"; + dev_name = "amlogic-rdma"; + status = "ok"; + interrupts = <0 89 1>; + interrupt-names = "rdma"; + }; + + amvenc_avc{ + compatible = "amlogic, amvenc_avc"; + dev_name = "amvenc_avc"; + status = "okay"; + interrupts = <0 45 1>; + interrupt-names = "mailbox_2"; + }; + + hevc_enc{ + compatible = "cnm, HevcEnc"; + dev_name = "HevcEnc"; + status = "okay"; + interrupts = <0 187 1>; + interrupt-names = "wave420l_irq"; + #address-cells=<1>; + #size-cells=<1>; + ranges; + io_reg_base{ + reg = <0xc8810000 0x4000>; + }; + }; + + picdec { + compatible = "amlogic, picdec"; + memory-region = <&picdec_cma_reserved>; + dev_name = "picdec"; + status = "okay"; + }; + + ppmgr { + compatible = "amlogic, ppmgr"; + memory-region = <&ppmgr_reserved>; + dev_name = "ppmgr"; + status = "okay"; + }; + + deinterlace { + compatible = "amlogic, deinterlace"; + status = "okay"; + flag_cma = <1>;/*0:use reserved;1:use cma*/ + //memory-region = <&di_reserved>; + memory-region = <&di_cma_reserved>; + interrupts = <0 46 1 0 6 1>; + interrupt-names = "de_irq", "timerc"; + /* + * nr_size(byte) = 1920*544*2(yuv422 8bit) | + * 1920*544*2*12/8(yuv422 10bit) + * | 1920*544*2*10/8(yuv422 10bit full pack mode) + */ + /* mtn_size(byte) = 1920*544/2 */ + /* count_size(byte) = 1920*544/2 */ + buffer-size = <3133440>; + hw-version = <2>; + }; + + ionvideo { + compatible = "amlogic, ionvideo"; + dev_name = "ionvideo"; + status = "okay"; + }; + + amlvideo { + compatible = "amlogic, amlvideo"; + dev_name = "amlvideo"; + status = "okay"; + }; + + amlvideo2_0 { + compatible = "amlogic, amlvideo2"; + dev_name = "amlvideo2"; + status = "okay"; + amlvideo2_id = <0>; + cma_mode = <1>; + }; + + amlvideo2_1 { + compatible = "amlogic, amlvideo2"; + dev_name = "amlvideo2"; + status = "okay"; + amlvideo2_id = <1>; + cma_mode = <1>; + }; + + /*if you want to use vdin just modify status to "ok"*/ + vdin0 { + compatible = "amlogic, vdin"; + /*memory-region = <&vdin0_cma_reserved>;*/ + dev_name = "vdin0"; + status = "ok"; + reserve-iomap = "true"; + flag_cma = <1>;/*1:share with codec_mm;2:cma alone*/ + /*MByte, if 10bit disable: 64M(YUV422), + *if 10bit enable: 64*1.5 = 96M(YUV422) + *if support 4K2K-YUV444-10bit-WR:3840*2160*4*4 ~= 128M + *if support 4K2K-YUV422-10bit-wr:3840*2160*3*4 ~= 96M + *if support 4K2K-YUV422-8BIT-WR:3840*2160*2*4 ~= 64M + *if support 1080p-YUV422-8BIT-WR:1920*1080*2*4 ~= 16M + */ + cma_size = <16>; + interrupts = <0 83 1>; + rdma-irq = <2>; + /*clocks = <&clock CLK_FPLL_DIV5>, + * <&clock CLK_VDIN_MEAS_CLK>; + *clock-names = "fclk_div5", "cts_vdin_meas_clk"; + */ + vdin_id = <0>; + /*vdin write mem color depth support: + *bit0:support 8bit + *bit1:support 9bit + *bit2:support 10bit + *bit3:support 12bit + *bit4:support yuv422 10bit full pack mode (from txl new add) + */ + tv_bit_mode = <1>; + }; + vdin1 { + compatible = "amlogic, vdin"; + memory-region = <&vdin1_cma_reserved>; + dev_name = "vdin1"; + status = "ok"; + reserve-iomap = "true"; + flag_cma = <0>;/*1:share with codec_mm;0:cma alone*/ + interrupts = <0 85 1>; + rdma-irq = <4>; + /*clocks = <&clock CLK_FPLL_DIV5>, + * <&clock CLK_VDIN_MEAS_CLK>; + *clock-names = "fclk_div5", "cts_vdin_meas_clk"; + */ + vdin_id = <1>; + /*vdin write mem color depth support: + *bit0:support 8bit + *bit1:support 9bit + *bit2:support 10bit + *bit3:support 12bit + */ + tv_bit_mode = <1>; + }; + + amlvecm { + compatible = "amlogic, vecm"; + dev_name = "aml_vecm"; + status = "okay"; + gamma_en = <0>;/*1:enabel ;0:disable*/ + wb_en = <0>;/*1:enabel ;0:disable*/ + cm_en = <0>;/*1:enabel ;0:disable*/ + /*1:enabel osd lut 100 table;0:disable*/ + cfg_en_osd_100 = <1>; + /*0: 709/601 1: bt2020*/ + tx_op_color_primary = <0>; + }; + + unifykey{ + compatible = "amlogic, unifykey"; + status = "ok"; + + unifykey-num = <15>; + unifykey-index-0 = <&keysn_0>; + unifykey-index-1 = <&keysn_1>; + unifykey-index-2 = <&keysn_2>; + unifykey-index-3 = <&keysn_3>; + unifykey-index-4 = <&keysn_4>; + unifykey-index-5 = <&keysn_5>; + unifykey-index-6 = <&keysn_6>; + unifykey-index-7 = <&keysn_7>; + unifykey-index-8 = <&keysn_8>; + unifykey-index-9 = <&keysn_9>; + unifykey-index-10= <&keysn_10>; + unifykey-index-11= <&keysn_11>; + unifykey-index-12= <&keysn_12>; + unifykey-index-13= <&keysn_13>; + unifykey-index-14= <&keysn_14>; + + keysn_0: key_0{ + key-name = "usid"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_1:key_1{ + key-name = "mac"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_2:key_2{ + key-name = "hdcp"; + key-device = "secure"; + key-type = "sha1"; + key-permit = "read","write","del"; + }; + keysn_3:key_3{ + key-name = "secure_boot_set"; + key-device = "efuse"; + key-permit = "write"; + }; + keysn_4:key_4{ + key-name = "mac_bt"; + key-device = "normal"; + key-permit = "read","write","del"; + key-type = "mac"; + }; + keysn_5:key_5{ + key-name = "mac_wifi"; + key-device = "normal"; + key-permit = "read","write","del"; + key-type = "mac"; + }; + keysn_6:key_6{ + key-name = "hdcp2_tx"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_7:key_7{ + key-name = "hdcp2_rx"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_8:key_8{ + key-name = "widevinekeybox"; + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_9:key_9{ + key-name = "deviceid"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_10:key_10{ + key-name = "hdcp22_fw_private"; + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_11:key_11{ + key-name = "PlayReadykeybox25"; + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_12:key_12{ + key-name = "prpubkeybox";// PlayReady + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_13:key_13{ + key-name = "prprivkeybox";// PlayReady + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_14:key_14{ + key-name = "attestationkeybox";// attestation key + key-device = "secure"; + key-permit = "read","write","del"; + }; + };//End unifykey +}; +&efuse { + status = "ok"; +}; + +&pwm_ef { + status = "okay"; +}; + diff --git a/arch/arm/boot/dts/amlogic/gxl_p231_2g_buildroot.dts b/arch/arm/boot/dts/amlogic/gxl_p231_2g_buildroot.dts new file mode 100644 index 000000000000..658cb5b7ed32 --- /dev/null +++ b/arch/arm/boot/dts/amlogic/gxl_p231_2g_buildroot.dts @@ -0,0 +1,1191 @@ +/* + * arch/arm/boot/dts/amlogic/gxl_p231_2g.dts + * + * Copyright (C) 2017 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +/dts-v1/; + +#include +#include "mesongxl.dtsi" +#include "meson_drm.dtsi" +/ { + model = "Amlogic"; + amlogic-dt-id = "gxl_p231_2g"; + compatible = "amlogic, Gxl"; + interrupt-parent = <&gic>; + #address-cells = <1>; + #size-cells = <1>; + + aliases { + serial0 = &uart_AO; + serial1 = &uart_A; + serial2 = &uart_B; + serial3 = &uart_C; + serial4 = &uart_AO_B; + }; + ion_dev { + compatible = "amlogic, ion_dev"; + }; + memory@00000000 { + device_type = "memory"; + linux,usable-memory = <0x0100000 0x7ff00000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + /* global autoconfigured region for contiguous allocations */ + ramoops@0x07400000 { + compatible = "ramoops"; + reg = <0x07400000 0x00100000>; + record-size = <0x8000>; + console-size = <0x8000>; + ftrace-size = <0x0>; + pmsg-size = <0x8000>; + }; + + secmon_reserved:linux,secmon { + compatible = "shared-dma-pool"; + reusable; + size = <0x400000>; + alignment = <0x400000>; + alloc-ranges = <0x05000000 0x400000>; + }; + secos_reserved:linux,secos { + status = "disable"; + compatible = "amlogic, aml_secos_memory"; + reg = <0x05300000 0x2000000>; + no-map; + }; + fb_reserved:linux,meson-fb { + compatible = "shared-dma-pool"; + reusable; + size = <0x2400000>; + alignment = <0x400000>; + alloc-ranges = <0x7dc00000 0x2400000>; + }; + //don't put other dts in front of fb_reserved + + //di_reserved:linux,di { + // compatible = "amlogic, di-mem"; + /** 10x3133440=30M(0x1e) support 8bit **/ + // size = <0x1e00000>; + //no-map; + //}; + di_cma_reserved:linux,di_cma { + compatible = "shared-dma-pool"; + reusable; + /** 10x3133440=30M(0x1e) support 8bit **/ + size = <0x2000000>; + alignment = <0x400000>; + }; + + + /* vdin0 CMA pool */ + //vdin0_cma_reserved:linux,vdin0_cma { + // compatible = "shared-dma-pool"; + // linux,phandle = <4>; + // reusable; + /* 1920x1080x2x4 =16+4 M */ + // size = <0x01400000>; + // alignment = <0x400000>; + //}; + /* vdin1 CMA pool */ + vdin1_cma_reserved:linux,vdin1_cma { + compatible = "shared-dma-pool"; + reusable; + /* 1920x1080x2x4 =16 M */ + size = <0x01000000>; + alignment = <0x400000>; + }; + /* POST PROCESS MANAGER */ + ppmgr_reserved:linux,ppmgr { + compatible = "shared-dma-pool"; + size = <0x0>; + }; + + codec_mm_cma:linux,codec_mm_cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x10400000>; + alignment = <0x400000>; + linux,contiguous-region; + }; + picdec_cma_reserved:linux,picdec { + compatible = "shared-dma-pool"; + reusable; + size = <0x0>; + alignment = <0x0>; + linux,contiguous-region; + }; + /* codec shared reserved */ + codec_mm_reserved:linux,codec_mm_reserved { + compatible = "amlogic, codec-mm-reserved"; + size = <0x0>; + alignment = <0x100000>; + //no-map; + }; + }; + + bt-dev{ + compatible = "amlogic, bt-dev"; + dev_name = "bt-dev"; + status = "okay"; + gpio_reset = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>; + }; + + wifi{ + compatible = "amlogic, aml_wifi"; + dev_name = "aml_wifi"; + status = "okay"; + interrupt_pin = <&gpio GPIOX_7 GPIO_ACTIVE_HIGH>; + irq_trigger_type = "GPIO_IRQ_LOW"; + dhd_static_buf; //dhd_static_buf support + power_on_pin = <&gpio GPIOX_6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_32k_pins>; + pwm_config = <&wifi_pwm_conf>; + }; + + wifi_pwm_conf:wifi_pwm_conf{ + pwm_channel1_conf { + pwms = <&pwm_ef MESON_PWM_0 30040 0>; + duty-cycle = <15020>; + times = <8>; + }; + pwm_channel2_conf { + pwms = <&pwm_ef MESON_PWM_2 30030 0>; + duty-cycle = <15015>; + times = <12>; + }; + }; + + sd_emmc_c: emmc@d0074000 { + status = "okay"; + compatible = "amlogic, meson-mmc-gxl"; + reg = <0xd0074000 0x2000>; + interrupts = <0 218 1>; + pinctrl-names = "emmc_clk_cmd_pins", "emmc_all_pins"; + pinctrl-0 = <&emmc_clk_cmd_pins>; + pinctrl-1 = <&emmc_conf_pull_up &emmc_conf_pull_done>; + clocks = <&clkc CLKID_SD_EMMC_C>, + <&clkc CLKID_SD_EMMC_C_P0_COMP>, + <&clkc CLKID_FCLK_DIV2>; + clock-names = "core", "clkin0", "clkin1"; + + bus-width = <8>; + cap-sd-highspeed; + cap-mmc-highspeed; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + + max-frequency = <200000000>; + non-removable; + disable-wp; + emmc { + pinname = "emmc"; + ocr_avail = <0x200080>; /**VDD voltage 3.3 ~ 3.4 */ + caps = "MMC_CAP_8_BIT_DATA", + "MMC_CAP_MMC_HIGHSPEED", + "MMC_CAP_SD_HIGHSPEED", + "MMC_CAP_NONREMOVABLE", + "MMC_CAP_1_8V_DDR", + "MMC_CAP_HW_RESET", + "MMC_CAP_ERASE", + "MMC_CAP_CMD23"; + caps2 = "MMC_CAP2_HS200", "MMC_CAP2_HS400"; + f_min = <400000>; + f_max = <100000000>; + max_req_size = <0x20000>; /**128KB*/ + gpio_dat3 = <&gpio BOOT_3 GPIO_ACTIVE_HIGH>; + hw_reset = <&gpio BOOT_9 GPIO_ACTIVE_HIGH>; + card_type = <1>; + /* 1:mmc card(include eMMC), + * 2:sd card(include tSD) + */ + }; + }; + + sd_emmc_b:sd@d0072000 { + status = "okay"; + compatible = "amlogic, meson-mmc-gxl"; + reg = <0xd0072000 0x2000>; + interrupts = <0 217 1>; + pinctrl-names = "sd_all_pins", + "sd_clk_cmd_pins", + "sd_1bit_pins", + "sd_clk_cmd_uart_pins", + "sd_1bit_uart_pins", + "sd_to_ao_uart_pins", + "ao_to_sd_uart_pins", + "ao_to_sd_jtag_pins", + "sd_to_ao_jtag_pins"; + pinctrl-0 = <&sd_all_pins>; + pinctrl-1 = <&sd_clk_cmd_pins>; + pinctrl-2 = <&sd_1bit_pins>; + pinctrl-3 = <&sd_to_ao_uart_clr_pins + &sd_clk_cmd_pins &ao_to_sd_uart_pins>; + pinctrl-4 = <&sd_to_ao_uart_clr_pins + &sd_1bit_pins &ao_to_sd_uart_pins>; + pinctrl-5 = <&sd_all_pins &sd_to_ao_uart_pins>; + pinctrl-6 = <&sd_to_ao_uart_clr_pins &ao_to_sd_uart_pins>; + pinctrl-7 = <&sd_to_ao_uart_clr_pins &ao_to_sd_uart_pins>; + pinctrl-8 = <&sd_all_pins &sd_to_ao_uart_pins>; + clocks = <&clkc CLKID_SD_EMMC_B>, + <&clkc CLKID_SD_EMMC_B_P0_COMP>, + <&clkc CLKID_FCLK_DIV2>; + clock-names = "core", "clkin0", "clkin1"; + + bus-width = <4>; + cap-sd-highspeed; + max-frequency = <100000000>; + disable-wp; + sd { + pinname = "sd"; + ocr_avail = <0x200080>; /**VDD voltage 3.3 ~ 3.4 */ + caps = "MMC_CAP_4_BIT_DATA", + "MMC_CAP_MMC_HIGHSPEED", + "MMC_CAP_SD_HIGHSPEED"; + /* "MMC_CAP_UHS_SDR12", + * "MMC_CAP_UHS_SDR25", + * "MMC_CAP_UHS_SDR50", + * "MMC_CAP_UHS_SDR104"; + */ + f_min = <400000>; + f_max = <100000000>; + max_req_size = <0x20000>; /**128KB*/ + gpio_dat3 = <&gpio CARD_4 GPIO_ACTIVE_HIGH>; + jtag_pin = <&gpio CARD_0 GPIO_ACTIVE_HIGH>; + gpio_cd = <&gpio CARD_6 GPIO_ACTIVE_HIGH>; + card_type = <5>; + /* 0:unknown, + * 1:mmc card(include eMMC), + * 2:sd card(include tSD), + * 3:sdio device(ie:sdio-wifi), + * 4:SD combo (IO+mem) card, + * 5:NON sdio device(means sd/mmc card), + * other:reserved + */ + }; + }; + + sd_emmc_a:sdio@d0070000 { + status = "okay"; + compatible = "amlogic, meson-mmc-gxl"; + reg = <0xd0070000 0x2000>; + interrupts = <0 216 4>; + pinctrl-names = "sdio_clk_cmd_pins", "sdio_all_pins"; + pinctrl-0 = <&sdio_clk_cmd_pins>; + pinctrl-1 = <&sdio_all_pins>; + clocks = <&clkc CLKID_SD_EMMC_A>, + <&clkc CLKID_SD_EMMC_A_P0_COMP>, + <&clkc CLKID_FCLK_DIV2>; + clock-names = "core", "clkin0", "clkin1"; + + bus-width = <4>; + cap-sd-highspeed; + cap-mmc-highspeed; + max-frequency = <100000000>; + non-removable; + disable-wp; + sdio { + pinname = "sdio"; + ocr_avail = <0x200080>; /**VDD voltage 3.3 ~ 3.4 */ + caps = "MMC_CAP_4_BIT_DATA", + "MMC_CAP_MMC_HIGHSPEED", + "MMC_CAP_SD_HIGHSPEED", + "MMC_CAP_NONREMOVABLE", + "MMC_CAP_UHS_SDR12", + "MMC_CAP_UHS_SDR25", + "MMC_CAP_UHS_SDR50", + "MMC_CAP_UHS_SDR104", + "MMC_PM_KEEP_POWER", + "MMC_CAP_SDIO_IRQ"; + f_min = <400000>; + f_max = <200000000>; + max_req_size = <0x20000>; /**128KB*/ + card_type = <3>; + /* 3:sdio device(ie:sdio-wifi), + * 4:SD combo (IO+mem) card + */ + }; + }; + + ethmac: ethernet@0xc9410000 { + compatible = "amlogic, gxbb-eth-dwmac"; + reg = <0xc9410000 0x10000 + 0xc8834540 0x8 + 0xc8834558 0xc>; + interrupts = <0 8 1>; + pinctrl-names = "external_eth_pins"; + pinctrl-0 = <&external_eth_pins>; + rst_pin-gpios = <&gpio GPIOZ_14 0>; + GPIOZ4_pin-gpios = <&gpio GPIOZ_4 0>; + GPIOZ5_pin-gpios = <&gpio GPIOZ_5 0>; + mc_val_internal_phy = <0x1800>; + mc_val_external_phy = <0x1621>; + cali_val = <0x20000>; + interrupt-names = "macirq"; + clocks = <&clkc CLKID_ETH>; + clock-names = "ethclk81"; + internal_phy=<1>; + }; + + codec_io { + compatible = "amlogic, codec_io"; + #address-cells=<1>; + #size-cells=<1>; + ranges; + io_cbus_base{ + reg = <0xC1100000 0x100000>; + }; + io_dos_base{ + reg = <0xc8820000 0x10000>; + }; + io_hiubus_base{ + reg = <0xc883c000 0x2000>; + }; + io_aobus_base{ + reg = <0xc8100000 0x100000>; + }; + io_vcbus_base{ + reg = <0xd0100000 0x40000>; + }; + io_dmc_base{ + reg = <0xc8838000 0x400>; + }; + }; + + codec_mm { + compatible = "amlogic, codec, mm"; + memory-region = <&codec_mm_cma &codec_mm_reserved>; + dev_name = "codec_mm"; + status = "okay"; + }; + + canvas{ + compatible = "amlogic, meson, canvas"; + dev_name = "amlogic-canvas"; + status = "ok"; + reg = <0xc8838000 0x400>; + }; + + mesonstream { + compatible = "amlogic, codec, streambuf"; + dev_name = "mesonstream"; + status = "okay"; + clocks = <&clkc CLKID_DOS_PARSER + &clkc CLKID_DEMUX + &clkc CLKID_DOS + &clkc CLKID_VDEC_MUX + &clkc CLKID_HCODEC_MUX + &clkc CLKID_HEVC_MUX>; + clock-names = "parser_top", + "demux", + "vdec", + "clk_vdec_mux", + "clk_hcodec_mux", + "clk_hevc_mux"; + }; + + vdec { + compatible = "amlogic, vdec"; + dev_name = "vdec.0"; + status = "okay"; + interrupts = <0 3 1 + 0 23 1 + 0 32 1 + 0 43 1 + 0 44 1 + 0 45 1>; + interrupt-names = "vsync", + "demux", + "parser", + "mailbox_0", + "mailbox_1", + "mailbox_2"; + }; + + aml_sensor0: aml-sensor@0 { + compatible = "amlogic, aml-thermal"; + device_name = "thermal"; + #thermal-sensor-cells = <1>; + cooling_devices { + cpufreq_cool_cluster0 { + min_state = <1000000>; + dyn_coeff = <140>; + cluster_id = <0>; + node_name = "cpufreq_cool0"; + device_type = "cpufreq"; + }; + cpucore_cool_cluster0 { + min_state = <1>; + dyn_coeff = <0>; + cluster_id = <0>; + node_name = "cpucore_cool0"; + device_type = "cpucore"; + }; + gpufreq_cool { + min_state = <400>; + dyn_coeff = <437>; + cluster_id = <0>; + node_name = "gpufreq_cool0"; + device_type = "gpufreq"; + }; + gpucore_cool { + min_state = <1>; + dyn_coeff = <0>; + cluster_id = <0>; + node_name = "gpucore_cool0"; + device_type = "gpucore"; + }; + }; + cpufreq_cool0:cpufreq_cool0 { + #cooling-cells = <2>; /* min followed by max */ + }; + cpucore_cool0:cpucore_cool0 { + #cooling-cells = <2>; /* min followed by max */ + }; + gpufreq_cool0:gpufreq_cool0 { + #cooling-cells = <2>; /* min followed by max */ + }; + gpucore_cool0:gpucore_cool0 { + #cooling-cells = <2>; /* min followed by max */ + }; + }; + thermal-zones { + soc_thermal { + polling-delay = <1000>; + polling-delay-passive = <100>; + sustainable-power = <2150>; + + thermal-sensors = <&aml_sensor0 3>; + + trips { + switch_on: trip-point@0 { + temperature = <70000>; + hysteresis = <1000>; + type = "passive"; + }; + control: trip-point@1 { + temperature = <80000>; + hysteresis = <1000>; + type = "passive"; + }; + hot: trip-point@2 { + temperature = <85000>; + hysteresis = <5000>; + type = "hot"; + }; + critical: trip-point@3 { + temperature = <260000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + + cooling-maps { + cpufreq_cooling_map { + trip = <&control>; + cooling-device = <&cpufreq_cool0 0 4>; + contribution = <1024>; + }; + cpucore_cooling_map { + trip = <&control>; + cooling-device = <&cpucore_cool0 0 3>; + contribution = <1024>; + }; + gpufreq_cooling_map { + trip = <&control>; + cooling-device = <&gpufreq_cool0 0 4>; + contribution = <1024>; + }; + gpucore_cooling_map { + trip = <&control>; + cooling-device = <&gpucore_cool0 0 2>; + contribution = <1024>; + }; + }; + }; + }; + + dwc3: dwc3@c9000000 { + compatible = "synopsys, dwc3"; + reg = <0xc9000000 0x100000>; + interrupts = <0 30 4>; + usb-phy = <&usb2_phy>, <&usb3_phy>; + cpu-type = "gxl"; + clock-src = "usb3.0"; + }; + + usb2_phy: usb2phy@d0078000 { + compatible = "amlogic, amlogic-new-usb2"; + portnum = <3>; + reg = <0xd0078000 0x80 + 0xc1104408 0x4>; + }; + + usb3_phy: usb3phy@d0078080 { + compatible = "amlogic, amlogic-new-usb3"; + portnum = <0>; + reg = <0xd0078080 0x20>; + }; + + dwc2_a { + compatible = "amlogic, dwc2"; + device_name = "dwc2_a"; + reg = <0xc9100000 0x40000>; + status = "okay"; + interrupts = <0 31 4>; + pl-periph-id = <0>; /** lm name */ + clock-src = "usb0"; /** clock src */ + port-id = <0>; /** ref to mach/usb.h */ + port-type = <2>; /** 0: otg, 1: host, 2: slave */ + port-speed = <0>; /** 0: default, high, 1: full */ + port-config = <0>; /** 0: default */ + port-dma = <0>; /** 0: default ... 6: disable*/ + port-id-mode = <0>; /** 0: hardware, 1: sw_host, 2: sw_slave*/ + usb-fifo = <728>; + cpu-type = "gxl"; + controller-type = <1>; /** 0: normal, 1: host, 2: device*/ + phy-reg = <0xd0078000>; + phy-reg-size = <0xa0>; + clocks = <&clkc CLKID_USB_GENERAL + &clkc CLKID_USB1_TO_DDR + &clkc CLKID_USB1>; + clock-names = "usb_general", + "usb1", + "usb1_to_ddr"; + }; + + meson-amvideom { + compatible = "amlogic, amvideom"; + dev_name = "amvideom"; + status = "okay"; + interrupts = <0 3 1>; + interrupt-names = "vsync"; + }; + + vout { + compatible = "amlogic, vout"; + dev_name = "vout"; + status = "okay"; + fr_auto_policy = <0>; + }; + + cvbsout { + compatible = "amlogic, cvbsout-gxl"; + dev_name = "cvbsout"; + status = "okay"; + clocks = <&clkc CLKID_VCLK2_ENCI + &clkc CLKID_VCLK2_VENCI0 + &clkc CLKID_VCLK2_VENCI1 + &clkc CLKID_DAC_CLK>; + clock-names = "venci_top_gate", + "venci_0_gate", + "venci_1_gate", + "vdac_clk_gate"; + + /* performance: reg_address, reg_value */ + /* s905d */ + performance = <0x1bf0 0x9 + 0x1b56 0x343 + 0x1b12 0x8080 + 0x1b05 0xfd + 0x1c59 0xf752 + 0xffff 0x0>; /* ending flag */ + }; + + amhdmitx: amhdmitx{ + compatible = "amlogic, amhdmitx"; + dev_name = "amhdmitx"; + status = "okay"; + vend-data = <&vend_data>; + pinctrl-names="hdmitx_hpd", "hdmitx_ddc"; + pinctrl-0=<&hdmitx_hpd>; + pinctrl-1=<&hdmitx_ddc>; + /* HPD, 57 + 32 = 89; CEC, 151 + 32 = 183*/ + interrupts = <0 57 1>; + interrupt-names = "hdmitx_hpd"; + /* 0:M8B 1:GXBB 2:GXTVBB 3:GXL 4:GXM + * 5:TXL 6:TXLX 7:AXG 8:GXLX 9:TXHD + */ + ic_type = <3>; + vend_data: vend_data{ /* Should modified by Customer */ + vendor_name = "Amlogic"; /* Max Chars: 8 */ + /* standards.ieee.org/develop/regauth/oui/oui.txt */ + vendor_id = <0x000000>; + product_desc = "MBox Meson Ref"; /* Max Chars: 16 */ + }; + }; + + aocec: aocec{ + compatible = "amlogic, amlogic-aocec"; + device_name = "aocec"; + status = "okay"; + vendor_id = <0x000000>; + cec_osd_string = "MBox"; /* Max Chars: 14 */ + cec_version = <6>; /* 5: 1.4, 6: 2.0 */ + port_num = <1>; + arc_port_mask = <0x0>; + interrupts = <0 199 1>; + interrupt-names = "hdmi_aocec"; + pinctrl-names = "default"; + pinctrl-0=<&hdmitx_aocec>; + reg = <0xc810023c 0x4 + 0xc8100000 0x200>; + reg-names = "ao_exit","ao"; + }; + + sysled { + compatible = "amlogic, sysled"; + dev_name = "sysled"; + status = "disabled"; + led_gpio = <&gpio GPIODV_24 GPIO_ACTIVE_HIGH>; + led_active_low = <1>; + }; + + meson-fb { + compatible = "amlogic, meson-gxl"; + memory-region = <&fb_reserved>; + dev_name = "meson-fb"; + status = "okay"; + interrupts = <0 3 1 + 0 89 1>; + interrupt-names = "viu-vsync", "rdma"; + mem_size = <0x00800000 0x1800000 0x00100000>; + /* uboot logo,fb0/fb1 memory size,if afbcd fb0=0x01851000 */ + display_mode_default = "1080p60hz"; + scale_mode = <1>; + /** 0:VPU free scale 1:OSD free scale 2:OSD super scale */ + display_size_default = <1920 1080 1920 3240 32>; + /*1920*1080*4*3 = 0x17BB000*/ + mem_alloc = <1>; + logo_addr = "0x7dc00000"; + }; + ge2d { + compatible = "amlogic, ge2d-gxl"; + dev_name = "ge2d"; + status = "okay"; + interrupts = <0 150 1>; + interrupt-names = "ge2d"; + clocks = <&clkc CLKID_VAPB_MUX>, + <&clkc CLKID_G2D>, + <&clkc CLKID_GE2D_GATE>; + clock-names = "clk_vapb_0", + "clk_ge2d", + "clk_ge2d_gate"; + }; + + + /* AUDIO MESON DEVICES */ + i2s_dai: I2S { + #sound-dai-cells = <0>; + compatible = "amlogic, aml-i2s-dai"; + clocks = + <&clkc CLKID_MPLL2>, + <&clkc CLKID_AMCLK_COMP>, + <&clkc CLKID_AIU_GLUE>, + <&clkc CLKID_IEC958>, + <&clkc CLKID_I2S_OUT>, + <&clkc CLKID_AMCLK>, + <&clkc CLKID_AIFIFO2>, + <&clkc CLKID_MIXER>, + <&clkc CLKID_MIXER_IFACE>, + <&clkc CLKID_ADC>, + <&clkc CLKID_AIU_TOP>, + <&clkc CLKID_AOCLK_GATE>, + <&clkc CLKID_I2S_SPDIF>; + clock-names = + "mpll", + "mclk", + "top_glue", + "aud_buf", + "i2s_out", + "amclk_measure", + "aififo2", + "aud_mixer", + "mixer_reg", + "adc", + "top_level", + "aoclk", + "aud_in"; + i2s_pos_sync = <0>; + /*DMIC;*/ /* I2s Mic or Dmic, default for I2S mic */ + }; + dmic:snd_dmic { + #sound-dai-cells = <0>; + compatible = "aml, aml_snd_dmic"; + reg = <0xd0042000 0x2000>; + status = "okay"; + resets = < + &clkc CLKID_PDM_GATE + >; + reset-names = "pdm"; + pinctrl-names = "audio_dmic"; + pinctrl-0 = <&aml_dmic_pins>; + clocks = <&clkc CLKID_PDM_COMP>, + <&clkc CLKID_AMCLK_COMP>; + clock-names = "pdm", "mclk"; + }; + spdif_dai: SPDIF { + #sound-dai-cells = <0>; + compatible = "amlogic, aml-spdif-dai"; + clocks = + <&clkc CLKID_MPLL1>, + <&clkc CLKID_I958_COMP>, + <&clkc CLKID_AMCLK_COMP>, + <&clkc CLKID_I958_COMP_SPDIF>, + <&clkc CLKID_CLK81>, + <&clkc CLKID_IEC958>, + <&clkc CLKID_IEC958_GATE>; + clock-names = + "mpll1", + "i958", + "mclk", + "spdif", + "clk_81", + "iec958", + "iec958_amclk"; + }; + pcm_dai: PCM { + #sound-dai-cells = <0>; + compatible = "amlogic, aml-pcm-dai"; + pinctrl-names = "audio_pcm"; + pinctrl-0 = <&audio_pcm_pins>; + clocks = + <&clkc CLKID_MPLL0>, + <&clkc CLKID_PCM_MCLK_COMP>, + <&clkc CLKID_PCM_SCLK_GATE>; + clock-names = + "mpll0", + "pcm_mclk", + "pcm_sclk"; + pcm_mode = <1>; /* 0=slave mode, 1=master mode */ + }; + i2s_plat: i2s_platform { + compatible = "amlogic, aml-i2s"; + interrupts = <0 29 1>; + }; + pcm_plat: pcm_platform { + compatible = "amlogic, aml-pcm"; + }; + spdif_codec: spdif_codec{ + #sound-dai-cells = <0>; + compatible = "amlogic, aml-spdif-codec"; + pinctrl-names = "audio_spdif"; + pinctrl-0 = <&audio_spdif_pins>; + }; + pcm_codec: pcm_codec{ + #sound-dai-cells = <0>; + compatible = "amlogic, pcm2BT-codec"; + }; + /* endof AUDIO MESON DEVICES */ + + /* AUDIO board specific */ + dummy_codec:dummy{ + #sound-dai-cells = <0>; + compatible = "amlogic, aml_dummy_codec"; + status = "disable"; + }; + amlogic_codec:t9015{ + #sound-dai-cells = <0>; + compatible = "amlogic, aml_codec_T9015"; + reg = <0xc8832000 0x14>; + status = "okay"; + }; + aml_sound_meson { + compatible = "aml, meson-snd-card"; + status = "okay"; + aml-sound-card,format = "i2s"; + aml_sound_card,name = "AML-MESONAUDIO"; + aml,audio-routing = + "Ext Spk","LOUTL", + "Ext Spk","LOUTR"; + + mute_gpio-gpios = <&gpio GPIOH_5 0>; + mute_inv; + hp_disable; + hp_paraments = <800 300 0 5 1>; + pinctrl-names = "audio_i2s"; + pinctrl-0 = <&audio_i2s_pins>; + cpu_list = <&cpudai0 &cpudai1 &cpudai2>; + codec_list = <&codec0 &codec1 &codec2>; + plat_list = <&i2s_plat &i2s_plat &pcm_plat>; + cpudai0: cpudai0 { + sound-dai = <&i2s_dai>; + }; + cpudai1: cpudai1 { + sound-dai = <&spdif_dai>; + }; + cpudai2: cpudai2 { + sound-dai = <&pcm_dai>; + }; + codec0: codec0 { + sound-dai = <&amlogic_codec>; + }; + codec1: codec1 { + sound-dai = <&spdif_codec>; + }; + codec2: codec2 { + sound-dai = <&pcm_codec>; + }; + }; + /* END OF AUDIO board specific */ + rdma{ + compatible = "amlogic, meson, rdma"; + dev_name = "amlogic-rdma"; + status = "ok"; + interrupts = <0 89 1>; + interrupt-names = "rdma"; + }; + + amvenc_avc{ + compatible = "amlogic, amvenc_avc"; + dev_name = "amvenc_avc"; + status = "okay"; + interrupts = <0 45 1>; + interrupt-names = "mailbox_2"; + }; + + hevc_enc{ + compatible = "cnm, HevcEnc"; + dev_name = "HevcEnc"; + status = "okay"; + interrupts = <0 187 1>; + interrupt-names = "wave420l_irq"; + #address-cells=<1>; + #size-cells=<1>; + ranges; + io_reg_base{ + reg = <0xc8810000 0x4000>; + }; + }; + + partitions: partitions{ + parts = <12>; + part-0 = <&logo>; + part-1 = <&recovery>; + part-2 = <&rsv>; + part-3 = <&tee>; + part-4 = <&crypt>; + part-5 = <&misc>; + part-6 = <&boot>; + part-7 = <&system>; + part-8 = <&cache>; + part-9 = <&vendor>; + part-10 = <&odm>; + part-11 = <&data>; + + logo:logo{ + pname = "logo"; + size = <0x0 0x2000000>; + mask = <1>; + }; + recovery:recovery{ + pname = "recovery"; + size = <0x0 0x2000000>; + mask = <1>; + }; + rsv:rsv{ + pname = "rsv"; + size = <0x0 0x800000>; + mask = <1>; + }; + tee:tee{ + pname = "tee"; + size = <0x0 0x800000>; + mask = <1>; + }; + crypt:crypt{ + pname = "crypt"; + size = <0x0 0x2000000>; + mask = <1>; + }; + misc:misc{ + pname = "misc"; + size = <0x0 0x2000000>; + mask = <1>; + }; + boot:boot + { + pname = "boot"; + size = <0x0 0x2000000>; + mask = <1>; + }; + system:system + { + pname = "system"; + size = <0x0 0x80000000>; + mask = <1>; + }; + vendor:vendor + { + pname = "vendor"; + size = <0x0 0x10000000>; + mask = <1>; + }; + odm:odm + { + pname = "odm"; + size = <0x0 0x10000000>; + mask = <1>; + }; + cache:cache + { + pname = "cache"; + size = <0x0 0x20000000>; + mask = <2>; + }; + data:data + { + pname = "data"; + size = <0xffffffff 0xffffffff>; + mask = <4>; + }; + }; + + ppmgr { + compatible = "amlogic, ppmgr"; + memory-region = <&ppmgr_reserved>; + dev_name = "ppmgr"; + status = "okay"; + }; + + deinterlace { + compatible = "amlogic, deinterlace"; + status = "okay"; + flag_cma = <1>;/*0:use reserved;1:use cma*/ + //memory-region = <&di_reserved>; + memory-region = <&di_cma_reserved>; + interrupts = <0 46 1 0 6 1>; + interrupt-names = "de_irq", "timerc"; + /* + * nr_size(byte) = 1920*544*2(yuv422 8bit) | + * 1920*544*2*12/8(yuv422 10bit) + * | 1920*544*2*10/8(yuv422 10bit full pack mode) + */ + /* mtn_size(byte) = 1920*544/2 */ + /* count_size(byte) = 1920*544/2 */ + buffer-size = <3133440>; + hw-version = <2>; + }; + + ionvideo { + compatible = "amlogic, ionvideo"; + dev_name = "ionvideo"; + status = "okay"; + }; + + amlvideo { + compatible = "amlogic, amlvideo"; + dev_name = "amlvideo"; + status = "okay"; + }; + + amlvideo2_0 { + compatible = "amlogic, amlvideo2"; + dev_name = "amlvideo2"; + status = "okay"; + amlvideo2_id = <0>; + cma_mode = <1>; + }; + + amlvideo2_1 { + compatible = "amlogic, amlvideo2"; + dev_name = "amlvideo2"; + status = "okay"; + amlvideo2_id = <1>; + cma_mode = <1>; + }; + + /*if you want to use vdin just modify status to "ok"*/ + vdin0 { + compatible = "amlogic, vdin"; + /*memory-region = <&vdin0_cma_reserved>;*/ + dev_name = "vdin0"; + status = "ok"; + reserve-iomap = "true"; + flag_cma = <1>;/*1:share with codec_mm;2:cma alone*/ + /*MByte, if 10bit disable: 64M(YUV422), + *if 10bit enable: 64*1.5 = 96M(YUV422) + *if support 4K2K-YUV444-10bit-WR:3840*2160*4*4 ~= 128M + *if support 4K2K-YUV422-10bit-wr:3840*2160*3*4 ~= 96M + *if support 4K2K-YUV422-8BIT-WR:3840*2160*2*4 ~= 64M + *if support 1080p-YUV422-8BIT-WR:1920*1080*2*4 ~= 16M + */ + cma_size = <16>; + interrupts = <0 83 1>; + rdma-irq = <2>; + /*clocks = <&clock CLK_FPLL_DIV5>, + * <&clock CLK_VDIN_MEAS_CLK>; + *clock-names = "fclk_div5", "cts_vdin_meas_clk"; + */ + vdin_id = <0>; + /*vdin write mem color depth support: + *bit0:support 8bit + *bit1:support 9bit + *bit2:support 10bit + *bit3:support 12bit + *bit4:support yuv422 10bit full pack mode (from txl new add) + */ + tv_bit_mode = <1>; + }; + vdin1 { + compatible = "amlogic, vdin"; + memory-region = <&vdin1_cma_reserved>; + dev_name = "vdin1"; + status = "ok"; + reserve-iomap = "true"; + flag_cma = <0>;/*1:share with codec_mm;0:cma alone*/ + interrupts = <0 85 1>; + rdma-irq = <4>; + /*clocks = <&clock CLK_FPLL_DIV5>, + * <&clock CLK_VDIN_MEAS_CLK>; + *clock-names = "fclk_div5", "cts_vdin_meas_clk"; + */ + vdin_id = <1>; + /*vdin write mem color depth support: + *bit0:support 8bit + *bit1:support 9bit + *bit2:support 10bit + *bit3:support 12bit + */ + tv_bit_mode = <1>; + }; + + amlvecm { + compatible = "amlogic, vecm"; + dev_name = "aml_vecm"; + status = "okay"; + gamma_en = <0>;/*1:enabel ;0:disable*/ + wb_en = <0>;/*1:enabel ;0:disable*/ + cm_en = <0>;/*1:enabel ;0:disable*/ + /*1:enabel osd lut 100 table;0:disable*/ + cfg_en_osd_100 = <1>; + /*0: 709/601 1: bt2020*/ + tx_op_color_primary = <0>; + }; + + unifykey{ + compatible = "amlogic, unifykey"; + status = "ok"; + + unifykey-num = <15>; + unifykey-index-0 = <&keysn_0>; + unifykey-index-1 = <&keysn_1>; + unifykey-index-2 = <&keysn_2>; + unifykey-index-3 = <&keysn_3>; + unifykey-index-4 = <&keysn_4>; + unifykey-index-5 = <&keysn_5>; + unifykey-index-6 = <&keysn_6>; + unifykey-index-7 = <&keysn_7>; + unifykey-index-8 = <&keysn_8>; + unifykey-index-9 = <&keysn_9>; + unifykey-index-10= <&keysn_10>; + unifykey-index-11= <&keysn_11>; + unifykey-index-12= <&keysn_12>; + unifykey-index-13= <&keysn_13>; + unifykey-index-14= <&keysn_14>; + + keysn_0: key_0{ + key-name = "usid"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_1:key_1{ + key-name = "mac"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_2:key_2{ + key-name = "hdcp"; + key-device = "secure"; + key-type = "sha1"; + key-permit = "read","write","del"; + }; + keysn_3:key_3{ + key-name = "secure_boot_set"; + key-device = "efuse"; + key-permit = "write"; + }; + keysn_4:key_4{ + key-name = "mac_bt"; + key-device = "normal"; + key-permit = "read","write","del"; + key-type = "mac"; + }; + keysn_5:key_5{ + key-name = "mac_wifi"; + key-device = "normal"; + key-permit = "read","write","del"; + key-type = "mac"; + }; + keysn_6:key_6{ + key-name = "hdcp2_tx"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_7:key_7{ + key-name = "hdcp2_rx"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_8:key_8{ + key-name = "widevinekeybox"; + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_9:key_9{ + key-name = "deviceid"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_10:key_10{ + key-name = "hdcp22_fw_private"; + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_11:key_11{ + key-name = "PlayReadykeybox25"; + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_12:key_12{ + key-name = "prpubkeybox";// PlayReady + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_13:key_13{ + key-name = "prprivkeybox";// PlayReady + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_14:key_14{ + key-name = "attestationkeybox";// attestation key + key-device = "secure"; + key-permit = "read","write","del"; + }; + };//End unifykey +}; +&efuse { + status = "ok"; +}; + +&pwm_ef { + status = "okay"; +}; + diff --git a/arch/arm/boot/dts/amlogic/gxl_p241_1g.dts b/arch/arm/boot/dts/amlogic/gxl_p241_1g.dts index a69c391bf60f..590b3c0198f8 100644 --- a/arch/arm/boot/dts/amlogic/gxl_p241_1g.dts +++ b/arch/arm/boot/dts/amlogic/gxl_p241_1g.dts @@ -79,6 +79,15 @@ alignment = <0x400000>; alloc-ranges = <0x3fc00000 0x400000>; }; + codec_mm_cma:linux,codec_mm_cma { + compatible = "shared-dma-pool"; + reusable; + /* ion_codec_mm max can alloc size 80M*/ + size = <0xd000000>; + alignment = <0x400000>; + linux,contiguous-region; + alloc-ranges = <0x30000000 0x10000000>; + }; //don't put other dts in front of logo_reserved //di_reserved:linux,di { @@ -96,13 +105,14 @@ /** 10x4074560=39M(0x27) support 10bit **/ size = <0x02400000>; alignment = <0x400000>; + alloc-ranges = <0x30000000 0x10000000>; }; ion_reserved:linux,ion-dev { compatible = "shared-dma-pool"; reusable; size = <0x4C00000>; alignment = <0x400000>; - alloc-ranges = <0x0 0x2ee00000>; + alloc-ranges = <0x0 0x30000000>; }; /* vdin0 CMA pool */ @@ -121,6 +131,7 @@ /* 1920x1080x2x4 =16 M */ size = <0x01000000>; alignment = <0x400000>; + alloc-ranges = <0x0 0x30000000>; }; /* POST PROCESS MANAGER */ ppmgr_reserved:linux,ppmgr { @@ -129,15 +140,6 @@ multi-use; }; - codec_mm_cma:linux,codec_mm_cma { - compatible = "shared-dma-pool"; - reusable; - /* ion_codec_mm max can alloc size 80M*/ - size = <0xd000000>; - alignment = <0x400000>; - linux,contiguous-region; - alloc-ranges = <0x12000000 0x13400000>; - }; picdec_cma_reserved:linux,picdec { compatible = "shared-dma-pool"; reusable; @@ -154,14 +156,14 @@ }; }; - dummy-battery { + amlogic_battery:dummy-battery { compatible = "amlogic, dummy-battery"; - status = "okay"; + status = "disabled"; }; - dummy-charger { + amlogic_charger:dummy-charger { compatible = "amlogic, dummy-charger"; - status = "okay"; + status = "disabled"; }; vpu { @@ -1301,3 +1303,4 @@ delay_control = <0x15>; ssctl = <0>; }; + diff --git a/arch/arm/boot/dts/amlogic/gxl_p241_1g_buildroot.dts b/arch/arm/boot/dts/amlogic/gxl_p241_1g_buildroot.dts new file mode 100644 index 000000000000..f68d359c54d3 --- /dev/null +++ b/arch/arm/boot/dts/amlogic/gxl_p241_1g_buildroot.dts @@ -0,0 +1,1358 @@ +/* + * arch/arm/boot/dts/amlogic/gxl_p241_1g.dts + * + * Copyright (C) 2017 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +/dts-v1/; + +#include "mesongxl.dtsi" +#include "meson_drm.dtsi" +/ { + model = "Amlogic"; + amlogic-dt-id = "gxl_p241_1g"; + compatible = "amlogic, Gxl"; + interrupt-parent = <&gic>; + #address-cells = <1>; + #size-cells = <1>; + + aliases { + serial0 = &uart_AO; + serial1 = &uart_C; + serial2 = &uart_B; + serial3 = &uart_A; + serial4 = &uart_AO_B; + }; + + ion_dev { + compatible = "amlogic, ion_dev"; + memory-region = <&ion_reserved>; + }; + + memory@00000000 { + device_type = "memory"; + linux,usable-memory = <0x0100000 0x3ff00000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + /* global autoconfigured region for contiguous allocations */ + ramoops@0x07400000 { + compatible = "ramoops"; + reg = <0x07400000 0x00100000>; + record-size = <0x8000>; + console-size = <0x8000>; + ftrace-size = <0x0>; + pmsg-size = <0x8000>; + }; + + secmon_reserved:linux,secmon { + compatible = "shared-dma-pool"; + reusable; + size = <0x400000>; + alignment = <0x400000>; + alloc-ranges = <0x05000000 0x400000>; + }; + secos_reserved:linux,secos { + status = "disable"; + compatible = "amlogic, aml_secos_memory"; + reg = <0x05300000 0x2000000>; + no-map; + }; + ion_reserved:linux,ion-dev { + compatible = "shared-dma-pool"; + reusable; + size = <0x8000000>; + alignment = <0x400000>; + }; + //don't put other dts in front of fb_reserved + + //di_reserved:linux,di { + // compatible = "amlogic, di-mem"; + /** 10x3133440=30M(0x1e) support 8bit **/ + // size = <0x1e00000>; + //no-map; + //}; + /*di CMA pool */ + di_cma_reserved:linux,di_cma { + compatible = "shared-dma-pool"; + reusable; + /** 10x3552320=34M(0x22) support 8bit **/ + /** 10x44596800=44M(0x2c) support 12bit **/ + /** 10x4074560=39M(0x27) support 10bit **/ + size = <0x02400000>; + alignment = <0x400000>; + }; + + /* vdin0 CMA pool */ + //vdin0_cma_reserved:linux,vdin0_cma { + // compatible = "shared-dma-pool"; + // linux,phandle = <4>; + // reusable; + /* 1920x1080x2x4 =16+4 M */ + // size = <0x01400000>; + // alignment = <0x400000>; + //}; + /* vdin1 CMA pool */ + vdin1_cma_reserved:linux,vdin1_cma { + compatible = "shared-dma-pool"; + reusable; + /* 1920x1080x2x4 =16 M */ + size = <0x01000000>; + alignment = <0x400000>; + alloc-ranges = <0x0 0x30000000>; + }; + /* POST PROCESS MANAGER */ + ppmgr_reserved:linux,ppmgr { + compatible = "shared-dma-pool"; + size = <0x0>; + }; + + codec_mm_cma:linux,codec_mm_cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x7800000>; + alignment = <0x400000>; + linux,contiguous-region; + }; + picdec_cma_reserved:linux,picdec { + compatible = "shared-dma-pool"; + reusable; + size = <0x0>; + alignment = <0x0>; + linux,contiguous-region; + }; + /* codec shared reserved */ + codec_mm_reserved:linux,codec_mm_reserved { + compatible = "amlogic, codec-mm-reserved"; + size = <0x0>; + alignment = <0x100000>; + //no-map; + }; + }; + + vpu { + clk_level = <2>; + /* 0: 100.0M 1: 166.7M 2: 200.0M 3: 250.0M */ + /* 4: 333.3M 5: 400.0M 6: 500.0M 7: 666.7M */ + }; + + uart_AO: serial@c81004c0 { + compatible = "amlogic, meson-uart"; + reg = <0xc81004c0 0x18>; + interrupts = <0 193 1>; + status = "okay"; + clocks = <&xtal>; + clock-names = "clk_uart"; + xtal_tick_en = <1>; + fifosize = < 64 >; + pinctrl-names = "default"; + pinctrl-0 = <&ao_uart_pins>; + support-sysrq = <0>; /* 0 not support , 1 support */ + }; + + uart_A: serial@c11084c0 { + compatible = "amlogic, meson-uart"; + reg = <0xc11084c0 0x18>; + interrupts = <0 26 1>; + status = "disable"; + clocks = <&clkc CLKID_UART0>; + clock-names = "clk_uart"; + fifosize = < 128 >; + pinctrl-names = "default"; + // pinctrl-0 = <&a_uart_pins>; + }; + + uart_B: serial@c11084dc { + compatible = "amlogic, meson-uart"; + reg = <0xc11084dc 0x18>; + interrupts = <0 75 1>; + status = "disabled"; + clocks = <&clkc CLKID_UART1>; + clock-names = "clk_uart"; + fifosize = < 64 >; + pinctrl-names = "default"; + pinctrl-0 = <&b_uart_pins>; + }; + + uart_C: serial@c1108700 { + compatible = "amlogic, meson-uart"; + reg = <0xc1108700 0x18>; + interrupts = <0 93 1>; + status = "okay"; + clocks = <&clkc CLKID_UART2>; + clock-names = "clk_uart"; + fifosize = < 64 >; + pinctrl-names = "default"; + pinctrl-0 = <&c_uart_pins>; + }; + + uart_AO_B: serial@c81004e0 { + compatible = "amlogic, meson-uart"; + reg = <0xc81004e0 0x18>; + interrupts = <0 197 1>; + status = "disable"; + clocks = <&xtal>; + clock-names = "clk_uart"; + fifosize = < 64 >; + pinctrl-names = "default"; + pinctrl-0 = <&ao_b_uart_pins>; + }; + + bt-dev{ + compatible = "amlogic, bt-dev"; + dev_name = "bt-dev"; + status = "okay"; + gpio_reset = <&gpio GPIOX_12 GPIO_ACTIVE_HIGH>; + }; + + wifi{ + compatible = "amlogic, aml_wifi"; + dev_name = "aml_wifi"; + status = "okay"; + interrupt_pin = <&gpio GPIOX_7 GPIO_ACTIVE_HIGH>; + interrupts = < 0 68 4>; + irq_trigger_type = "GPIO_IRQ_LOW"; + dhd_static_buf; //dhd_static_buf support + power_on_pin = <&gpio GPIODV_25 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_32k_pins>; + pwm_config = <&wifi_pwm_conf>; + }; + + wifi_pwm_conf:wifi_pwm_conf{ + pwm_channel1_conf { + pwms = <&pwm_ef MESON_PWM_0 30040 0>; + duty-cycle = <15020>; + times = <8>; + }; + pwm_channel2_conf { + pwms = <&pwm_ef MESON_PWM_2 30030 0>; + duty-cycle = <15015>; + times = <12>; + }; + }; + + sd_emmc_c: emmc@d0074000 { + status = "okay"; + compatible = "amlogic, meson-mmc-gxl"; + reg = <0xd0074000 0x2000>; + interrupts = <0 218 1>; + pinctrl-names = "emmc_clk_cmd_pins", "emmc_all_pins"; + pinctrl-0 = <&emmc_clk_cmd_pins>; + pinctrl-1 = <&emmc_conf_pull_up &emmc_conf_pull_done>; + clocks = <&clkc CLKID_SD_EMMC_C>, + <&clkc CLKID_SD_EMMC_C_P0_COMP>, + <&clkc CLKID_FCLK_DIV2>; + clock-names = "core", "clkin0", "clkin1"; + + bus-width = <8>; + cap-sd-highspeed; + cap-mmc-highspeed; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + + max-frequency = <200000000>; + non-removable; + disable-wp; + emmc { + pinname = "emmc"; + ocr_avail = <0x200080>; /**VDD voltage 3.3 ~ 3.4 */ + caps = "MMC_CAP_8_BIT_DATA", + "MMC_CAP_MMC_HIGHSPEED", + "MMC_CAP_SD_HIGHSPEED", + "MMC_CAP_NONREMOVABLE", + "MMC_CAP_1_8V_DDR", + "MMC_CAP_HW_RESET", + "MMC_CAP_ERASE", + "MMC_CAP_CMD23"; + // caps2 = "MMC_CAP2_HS200", "MMC_CAP2_HS400"; + f_min = <300000>; + f_max = <50000000>; + max_req_size = <0x20000>; /**128KB*/ + gpio_dat3 = <&gpio BOOT_3 GPIO_ACTIVE_HIGH>; + hw_reset = <&gpio BOOT_9 GPIO_ACTIVE_HIGH>; + card_type = <1>; + /* 1:mmc card(include eMMC), + * 2:sd card(include tSD) + */ + }; + }; + + sd_emmc_b:sd@d0072000 { + status = "okay"; + compatible = "amlogic, meson-mmc-gxl"; + reg = <0xd0072000 0x2000>; + interrupts = <0 217 1>; + pinctrl-names = "sd_all_pins", + "sd_clk_cmd_pins", + "sd_clk_cmd_uart_pins", + "sd_to_ao_uart_pins", + "ao_to_sd_uart_pins"; + pinctrl-0 = <&sd_all_pins>; + pinctrl-1 = <&sd_clk_cmd_pins>; + pinctrl-2 = <&sd_clk_cmd_pins &ao_to_sd_uart_pins>; + pinctrl-3 = <&sd_to_ao_uart_pins>; + pinctrl-4 = <&ao_to_sd_uart_pins>; + clocks = <&clkc CLKID_SD_EMMC_B>, + <&clkc CLKID_SD_EMMC_B_P0_COMP>, + <&clkc CLKID_FCLK_DIV2>; + clock-names = "core", "clkin0", "clkin1"; + + bus-width = <4>; + cap-sd-highspeed; + max-frequency = <100000000>; + disable-wp; + sd { + pinname = "sd"; + ocr_avail = <0x200080>; /**VDD voltage 3.3 ~ 3.4 */ + caps = "MMC_CAP_4_BIT_DATA", + "MMC_CAP_MMC_HIGHSPEED", + "MMC_CAP_SD_HIGHSPEED"; + /* "MMC_CAP_UHS_SDR12", + * "MMC_CAP_UHS_SDR25", + * "MMC_CAP_UHS_SDR50", + * "MMC_CAP_UHS_SDR104"; + */ + f_min = <400000>; + f_max = <100000000>; + max_req_size = <0x20000>; /**128KB*/ + gpio_dat3 = <&gpio CARD_4 GPIO_ACTIVE_HIGH>; + jtag_pin = <&gpio CARD_0 GPIO_ACTIVE_HIGH>; + gpio_cd = <&gpio CARD_6 GPIO_ACTIVE_HIGH>; + card_type = <5>; + /* 0:unknown, + * 1:mmc card(include eMMC), + * 2:sd card(include tSD), + * 3:sdio device(ie:sdio-wifi), + * 4:SD combo (IO+mem) card, + * 5:NON sdio device(means sd/mmc card), + * other:reserved + */ + }; + }; + + sd_emmc_a:sdio@d0070000 { + status = "okay"; + compatible = "amlogic, meson-mmc-gxl"; + reg = <0xd0070000 0x2000>; + interrupts = <0 216 4>; + pinctrl-names = "sdio_clk_cmd_pins", "sdio_all_pins"; + pinctrl-0 = <&sdio_clk_cmd_pins>; + pinctrl-1 = <&sdio_all_pins>; + clocks = <&clkc CLKID_SD_EMMC_A>, + <&clkc CLKID_SD_EMMC_A_P0_COMP>, + <&clkc CLKID_FCLK_DIV2>; + clock-names = "core", "clkin0", "clkin1"; + + bus-width = <4>; + cap-sd-highspeed; + cap-mmc-highspeed; + max-frequency = <100000000>; + non-removable; + disable-wp; + sdio { + pinname = "sdio"; + ocr_avail = <0x200080>; /**VDD voltage 3.3 ~ 3.4 */ + caps = "MMC_CAP_4_BIT_DATA", + "MMC_CAP_MMC_HIGHSPEED", + "MMC_CAP_SD_HIGHSPEED", + "MMC_CAP_NONREMOVABLE", + "MMC_CAP_UHS_SDR12", + "MMC_CAP_UHS_SDR25", + "MMC_CAP_UHS_SDR50", + "MMC_CAP_UHS_SDR104", + "MMC_PM_KEEP_POWER", + "MMC_CAP_SDIO_IRQ"; + f_min = <400000>; + f_max = <200000000>; + max_req_size = <0x20000>; /**128KB*/ + card_type = <3>; + /* 3:sdio device(ie:sdio-wifi), + * 4:SD combo (IO+mem) card + */ + }; + }; + mtd_nand{ + compatible = "amlogic, aml_mtd_nand"; + dev_name = "mtdnand"; + status = "disabled"; + reg = <0xd0074800 0x200>; + interrupts = < 0 34 1 >; + pinctrl-names = "nand_rb_mod","nand_norb_mod", "nand_cs_only"; + pinctrl-0 = <&all_nand_pins>; + pinctrl-1 = <&all_nand_pins>; + pinctrl-2 = <&nand_cs_pins>; + device_id = <0>; + plat-names = "bootloader","nandnormal"; + plat-num = <2>; + plat-part-0 = <&bootloader>; + plat-part-1 = <&nandnormal>; + bootloader: bootloader{ + enable_pad ="ce0"; + busy_pad = "rb0"; + timming_mode = "mode5"; + bch_mode = "bch60_1k"; + t_rea = <20>; + t_rhoh = <15>; + chip_num = <1>; + part_num = <0>; + rb_detect = <1>; + }; + nandnormal: nandnormal{ + enable_pad ="ce0","ce1"; + busy_pad = "rb0","rb1"; + timming_mode = "mode5"; + bch_mode = "bch60_1k"; + plane_mode = "twoplane"; + t_rea = <20>; + t_rhoh = <15>; + chip_num = <2>; + part_num = <3>; + partition = <&nand_partitions>; + rb_detect = <1>; + }; + nand_partitions:nand_partition{ + logo{ + offset=<0x0 0x0>; + size=<0x0 0x200000>; + }; + recovery{ + offset=<0x0 0x0>; + size=<0x0 0x1000000>; + }; + boot{ + offset=<0x0 0x0>; + size=<0x0 0xC00000>; + }; + system{ + offset=<0x0 0x0>; + size=<0x0 0xDC40000>; + }; + data{ + offset=<0xffffffff 0xffffffff>; + size=<0x0 0x0>; + }; + }; + }; + + ethmac: ethernet@0xc9410000 { + compatible = "amlogic, gxbb-eth-dwmac"; + reg = <0xc9410000 0x10000 + 0xc8834540 0x8 + 0xc8834558 0xc>; + interrupts = <0 8 1>; + pinctrl-names = "external_eth_pins"; + pinctrl-0 = <&external_eth_pins>; + rst_pin-gpios = <&gpio GPIOZ_14 0>; + GPIOZ4_pin-gpios = <&gpio GPIOZ_4 0>; + GPIOZ5_pin-gpios = <&gpio GPIOZ_5 0>; + mc_val_internal_phy = <0x1800>; + mc_val_external_phy = <0x1621>; + cali_val = <0x20000>; + interrupt-names = "macirq"; + clocks = <&clkc CLKID_ETH>; + clock-names = "ethclk81"; + internal_phy=<1>; + }; + + aml_sensor0: aml-sensor@0 { + compatible = "amlogic, aml-thermal"; + device_name = "thermal"; + #thermal-sensor-cells = <1>; + cooling_devices { + cpufreq_cool_cluster0 { + min_state = <1000000>; + dyn_coeff = <140>; + cluster_id = <0>; + node_name = "cpufreq_cool0"; + device_type = "cpufreq"; + }; + cpucore_cool_cluster0 { + min_state = <1>; + dyn_coeff = <0>; + cluster_id = <0>; + node_name = "cpucore_cool0"; + device_type = "cpucore"; + }; + gpufreq_cool { + min_state = <400>; + dyn_coeff = <437>; + cluster_id = <0>; + node_name = "gpufreq_cool0"; + device_type = "gpufreq"; + }; + gpucore_cool { + min_state = <1>; + dyn_coeff = <0>; + cluster_id = <0>; + node_name = "gpucore_cool0"; + device_type = "gpucore"; + }; + }; + cpufreq_cool0:cpufreq_cool0 { + #cooling-cells = <2>; /* min followed by max */ + }; + cpucore_cool0:cpucore_cool0 { + #cooling-cells = <2>; /* min followed by max */ + }; + gpufreq_cool0:gpufreq_cool0 { + #cooling-cells = <2>; /* min followed by max */ + }; + gpucore_cool0:gpucore_cool0 { + #cooling-cells = <2>; /* min followed by max */ + }; + }; + thermal-zones { + soc_thermal { + polling-delay = <1000>; + polling-delay-passive = <100>; + sustainable-power = <2150>; + + thermal-sensors = <&aml_sensor0 3>; + + trips { + switch_on: trip-point@0 { + temperature = <70000>; + hysteresis = <1000>; + type = "passive"; + }; + control: trip-point@1 { + temperature = <80000>; + hysteresis = <1000>; + type = "passive"; + }; + hot: trip-point@2 { + temperature = <85000>; + hysteresis = <5000>; + type = "hot"; + }; + critical: trip-point@3 { + temperature = <260000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + + cooling-maps { + cpufreq_cooling_map { + trip = <&control>; + cooling-device = <&cpufreq_cool0 0 4>; + contribution = <1024>; + }; + cpucore_cooling_map { + trip = <&control>; + cooling-device = <&cpucore_cool0 0 3>; + contribution = <1024>; + }; + gpufreq_cooling_map { + trip = <&control>; + cooling-device = <&gpufreq_cool0 0 4>; + contribution = <1024>; + }; + gpucore_cooling_map { + trip = <&control>; + cooling-device = <&gpucore_cool0 0 2>; + contribution = <1024>; + }; + }; + }; + }; + + dwc3: dwc3@c9000000 { + compatible = "synopsys, dwc3"; + reg = <0xc9000000 0x100000>; + interrupts = <0 30 4>; + usb-phy = <&usb2_phy>, <&usb3_phy>; + cpu-type = "gxl"; + clock-src = "usb3.0"; + }; + + usb2_phy: usb2phy@d0078000 { + compatible = "amlogic, amlogic-new-usb2"; + portnum = <3>; + reg = <0xd0078000 0x80 + 0xc1104408 0x4>; + }; + + usb3_phy: usb3phy@d0078080 { + compatible = "amlogic, amlogic-new-usb3"; + portnum = <0>; + reg = <0xd0078080 0x20>; + }; + + dwc2_a { + compatible = "amlogic, dwc2"; + device_name = "dwc2_a"; + reg = <0xc9100000 0x40000>; + status = "okay"; + interrupts = <0 31 4>; + pl-periph-id = <0>; /** lm name */ + clock-src = "usb0"; /** clock src */ + port-id = <0>; /** ref to mach/usb.h */ + port-type = <2>; /** 0: otg, 1: host, 2: slave */ + port-speed = <0>; /** 0: default, high, 1: full */ + port-config = <0>; /** 0: default */ + port-dma = <0>; /** 0: default ... 6: disable*/ + port-id-mode = <0>; /** 0: hardware, 1: sw_host, 2: sw_slave*/ + usb-fifo = <728>; + cpu-type = "gxl"; + controller-type = <1>; /** 0: normal, 1: host, 2: device*/ + phy-reg = <0xd0078000>; + phy-reg-size = <0xa0>; + clocks = <&clkc CLKID_USB_GENERAL + &clkc CLKID_USB1_TO_DDR + &clkc CLKID_USB1>; + clock-names = "usb_general", + "usb1", + "usb1_to_ddr"; + }; + + meson-amvideom { + compatible = "amlogic, amvideom"; + dev_name = "amvideom"; + status = "okay"; + interrupts = <0 3 1>; + interrupt-names = "vsync"; + }; + + vout { + compatible = "amlogic, vout"; + dev_name = "vout"; + status = "okay"; + fr_auto_policy = <0>; + }; + + cvbsout { + compatible = "amlogic, cvbsout-gxl"; + dev_name = "cvbsout"; + status = "okay"; + clocks = <&clkc CLKID_VCLK2_ENCI + &clkc CLKID_VCLK2_VENCI0 + &clkc CLKID_VCLK2_VENCI1 + &clkc CLKID_DAC_CLK>; + clock-names = "venci_top_gate", + "venci_0_gate", + "venci_1_gate", + "vdac_clk_gate"; + + /* performance: reg_address, reg_value */ + /* s805x */ + performance = <0x1bf0 0x9 + 0x1b56 0x343 + 0x1b12 0x8080 + 0x1b05 0xfd + 0x1c59 0xf752 + 0xffff 0x0>; /* ending flag */ + }; + + amhdmitx: amhdmitx{ + compatible = "amlogic, amhdmitx"; + dev_name = "amhdmitx"; + status = "okay"; + vend-data = <&vend_data>; + pinctrl-names="hdmitx_hpd", "hdmitx_ddc"; + pinctrl-0=<&hdmitx_hpd>; + pinctrl-1=<&hdmitx_ddc>; + /* HPD, 57 + 32 = 89; CEC, 151 + 32 = 183*/ + interrupts = <0 57 1>; + interrupt-names = "hdmitx_hpd"; + /* 0:M8B 1:GXBB 2:GXTVBB 3:GXL 4:GXM + * 5:TXL 6:TXLX 7:AXG 8:GXLX 9:TXHD + */ + ic_type = <3>; + vend_data: vend_data{ /* Should modified by Customer */ + vendor_name = "Amlogic"; /* Max Chars: 8 */ + /* standards.ieee.org/develop/regauth/oui/oui.txt */ + vendor_id = <0x000000>; + product_desc = "MBox Meson Ref"; /* Max Chars: 16 */ + }; + }; + + aocec: aocec{ + compatible = "amlogic, amlogic-aocec"; + device_name = "aocec"; + status = "okay"; + vendor_id = <0x000000>; + cec_osd_string = "MBox"; /* Max Chars: 14 */ + cec_version = <6>; /* 5: 1.4, 6: 2.0 */ + port_num = <1>; + arc_port_mask = <0x0>; + interrupts = <0 199 1>; + interrupt-names = "hdmi_aocec"; + pinctrl-names = "default"; + pinctrl-0=<&hdmitx_aocec>; + reg = <0xc810023c 0x4 + 0xc8100000 0x200>; + reg-names = "ao_exit","ao"; + }; + + sysled { + compatible = "amlogic, sysled"; + dev_name = "sysled"; + status = "okay"; + led_gpio = <&gpio GPIODV_27 GPIO_ACTIVE_HIGH>; + led_active_low = <1>; + }; + + codec_io { + compatible = "amlogic, codec_io"; + #address-cells=<1>; + #size-cells=<1>; + ranges; + io_cbus_base{ + reg = <0xC1100000 0x100000>; + }; + io_dos_base{ + reg = <0xc8820000 0x10000>; + }; + io_hiubus_base{ + reg = <0xc883c000 0x2000>; + }; + io_aobus_base{ + reg = <0xc8100000 0x100000>; + }; + io_vcbus_base{ + reg = <0xd0100000 0x40000>; + }; + io_dmc_base{ + reg = <0xc8838000 0x400>; + }; + }; + + codec_mm { + compatible = "amlogic, codec, mm"; + memory-region = <&codec_mm_cma &codec_mm_reserved>; + dev_name = "codec_mm"; + status = "okay"; + }; + + canvas{ + compatible = "amlogic, meson, canvas"; + dev_name = "amlogic-canvas"; + status = "ok"; + reg = <0xc8838000 0x400>; + }; + + mesonstream { + compatible = "amlogic, codec, streambuf"; + dev_name = "mesonstream"; + status = "okay"; + clocks = <&clkc CLKID_DOS_PARSER + &clkc CLKID_DEMUX + &clkc CLKID_DOS + &clkc CLKID_VDEC_MUX + &clkc CLKID_HCODEC_MUX + &clkc CLKID_HEVC_MUX>; + clock-names = "parser_top", + "demux", + "vdec", + "clk_vdec_mux", + "clk_hcodec_mux", + "clk_hevc_mux"; + }; + + vdec { + compatible = "amlogic, vdec"; + dev_name = "vdec.0"; + status = "okay"; + interrupts = <0 3 1 + 0 23 1 + 0 32 1 + 0 43 1 + 0 44 1 + 0 45 1>; + interrupt-names = "vsync", + "demux", + "parser", + "mailbox_0", + "mailbox_1", + "mailbox_2"; + }; + + meson-fb { + compatible = "amlogic, meson-gxl"; + dev_name = "meson-fb"; + status = "okay"; + interrupts = <0 3 1 + 0 89 1>; + interrupt-names = "viu-vsync", "rdma"; + mem_size = <0x00300000 0x00b00000 0x00100000>; + /* uboot logo,fb0/fb1 memory size */ + display_mode_default = "720p60hz"; + scale_mode = <1>; + /** 0:VPU free scale 1:OSD free scale 2:OSD super scale */ + display_size_default = <1280 720 1280 2160 32>; + /*1920*1080*4*3 = 0x17BB000*/ + mem_alloc = <1>; + logo_addr = "0x3f000000"; + }; + ge2d { + compatible = "amlogic, ge2d-gxl"; + dev_name = "ge2d"; + status = "okay"; + interrupts = <0 150 1>; + interrupt-names = "ge2d"; + clocks = <&clkc CLKID_VAPB_MUX>, + <&clkc CLKID_G2D>, + <&clkc CLKID_GE2D_GATE>; + clock-names = "clk_vapb_0", + "clk_ge2d", + "clk_ge2d_gate"; + }; + + + /* AUDIO MESON DEVICES */ + i2s_dai: I2S { + #sound-dai-cells = <0>; + compatible = "amlogic, aml-i2s-dai"; + clocks = + <&clkc CLKID_MPLL2>, + <&clkc CLKID_AMCLK_COMP>, + <&clkc CLKID_AIU_GLUE>, + <&clkc CLKID_IEC958>, + <&clkc CLKID_I2S_OUT>, + <&clkc CLKID_AMCLK>, + <&clkc CLKID_AIFIFO2>, + <&clkc CLKID_MIXER>, + <&clkc CLKID_MIXER_IFACE>, + <&clkc CLKID_ADC>, + <&clkc CLKID_AIU_TOP>, + <&clkc CLKID_AOCLK_GATE>, + <&clkc CLKID_I2S_SPDIF>; + clock-names = + "mpll", + "mclk", + "top_glue", + "aud_buf", + "i2s_out", + "amclk_measure", + "aififo2", + "aud_mixer", + "mixer_reg", + "adc", + "top_level", + "aoclk", + "aud_in"; + i2s_pos_sync = <0>; + /*DMIC;*/ /* I2s Mic or Dmic, default for I2S mic */ + }; + dmic:snd_dmic { + #sound-dai-cells = <0>; + compatible = "aml, aml_snd_dmic"; + reg = <0xd0042000 0x2000>; + status = "disabled"; + resets = < + &clkc CLKID_PDM_GATE + >; + reset-names = "pdm"; + pinctrl-names = "audio_dmic"; + pinctrl-0 = <&aml_dmic_pins>; + clocks = <&clkc CLKID_PDM_COMP>, + <&clkc CLKID_AMCLK_COMP>; + clock-names = "pdm", "mclk"; + }; + spdif_dai: SPDIF { + #sound-dai-cells = <0>; + compatible = "amlogic, aml-spdif-dai"; + clocks = + <&clkc CLKID_MPLL1>, + <&clkc CLKID_I958_COMP>, + <&clkc CLKID_AMCLK_COMP>, + <&clkc CLKID_I958_COMP_SPDIF>, + <&clkc CLKID_CLK81>, + <&clkc CLKID_IEC958>, + <&clkc CLKID_IEC958_GATE>; + clock-names = + "mpll1", + "i958", + "mclk", + "spdif", + "clk_81", + "iec958", + "iec958_amclk"; + }; + pcm_dai: PCM { + #sound-dai-cells = <0>; + compatible = "amlogic, aml-pcm-dai"; + pinctrl-names = "audio_pcm"; + // pinctrl-0 = <&audio_pcm_pins>; + clocks = + <&clkc CLKID_MPLL0>, + <&clkc CLKID_PCM_MCLK_COMP>, + <&clkc CLKID_PCM_SCLK_GATE>; + clock-names = + "mpll0", + "pcm_mclk", + "pcm_sclk"; + pcm_mode = <1>; /* 0=slave mode, 1=master mode */ + }; + i2s_plat: i2s_platform { + compatible = "amlogic, aml-i2s"; + interrupts = <0 29 1>; + }; + pcm_plat: pcm_platform { + compatible = "amlogic, aml-pcm"; + }; + spdif_codec: spdif_codec{ + #sound-dai-cells = <0>; + compatible = "amlogic, aml-spdif-codec"; + pinctrl-names = "audio_spdif"; + pinctrl-0 = <&audio_spdif_pins>; + }; + pcm_codec: pcm_codec{ + #sound-dai-cells = <0>; + compatible = "amlogic, pcm2BT-codec"; + }; + /* endof AUDIO MESON DEVICES */ + + /* AUDIO board specific */ + dummy_codec:dummy{ + #sound-dai-cells = <0>; + compatible = "amlogic, aml_dummy_codec"; + status = "disable"; + }; + amlogic_codec:t9015{ + #sound-dai-cells = <0>; + compatible = "amlogic, aml_codec_T9015"; + reg = <0xc8832000 0x14>; + status = "okay"; + }; + aml_sound_meson { + compatible = "aml, meson-snd-card"; + status = "okay"; + aml-sound-card,format = "i2s"; + aml_sound_card,name = "AML-MESONAUDIO"; + aml,audio-routing = + "Ext Spk","LOUTL", + "Ext Spk","LOUTR"; + + mute_gpio-gpios = <&gpio GPIOH_5 0>; + mute_inv; + hp_disable; + hp_paraments = <800 300 0 5 1>; + pinctrl-names = "audio_i2s"; + pinctrl-0 = <&audio_i2s_pins>; + cpu_list = <&cpudai0 &cpudai1 &cpudai2>; + codec_list = <&codec0 &codec1 &codec2>; + plat_list = <&i2s_plat &i2s_plat &pcm_plat>; + cpudai0: cpudai0 { + sound-dai = <&i2s_dai>; + }; + cpudai1: cpudai1 { + sound-dai = <&spdif_dai>; + }; + cpudai2: cpudai2 { + sound-dai = <&pcm_dai>; + }; + codec0: codec0 { + sound-dai = <&amlogic_codec>; + }; + codec1: codec1 { + sound-dai = <&spdif_codec>; + }; + codec2: codec2 { + sound-dai = <&pcm_codec>; + }; + }; + /* END OF AUDIO board specific */ + + rdma{ + compatible = "amlogic, meson, rdma"; + dev_name = "amlogic-rdma"; + status = "ok"; + interrupts = <0 89 1>; + interrupt-names = "rdma"; + }; + + amvenc_avc{ + compatible = "amlogic, amvenc_avc"; + dev_name = "amvenc_avc"; + status = "okay"; + interrupts = <0 45 1>; + interrupt-names = "mailbox_2"; + }; + + hevc_enc{ + compatible = "cnm, HevcEnc"; + dev_name = "HevcEnc"; + status = "okay"; + interrupts = <0 187 1>; + interrupt-names = "wave420l_irq"; + #address-cells=<1>; + #size-cells=<1>; + ranges; + io_reg_base{ + reg = <0xc8810000 0x4000>; + }; + }; + + partitions: partitions{ + parts = <14>; + part-0 = <&logo>; + part-1 = <&recovery>; + part-2 = <&misc>; + part-3 = <&dto>; + part-4 = <&cri_data>; + part-5 = <¶m>; + part-6 = <&boot>; + part-7 = <&rsv>; + part-8 = <&tee>; + part-9 = <&vendor>; + part-10 = <&odm>; + part-11 = <&system>; + part-12 = <&cache>; + part-13 = <&data>; + + logo:logo{ + pname = "logo"; + size = <0x0 0x800000>; + mask = <1>; + }; + recovery:recovery{ + pname = "recovery"; + size = <0x0 0x1800000>; + mask = <1>; + }; + misc:misc{ + pname = "misc"; + size = <0x0 0x800000>; + mask = <1>; + }; + dto:dto{ + pname = "dto"; + size = <0x0 0x800000>; + mask = <1>; + }; + cri_data:cri_data + { + pname = "cri_data"; + size = <0x0 0x800000>; + mask = <2>; + }; + rsv:rsv{ + pname = "rsv"; + size = <0x0 0x1000000>; + mask = <1>; + }; + param:param{ + pname = "param"; + size = <0x0 0x1000000>; + mask = <2>; + }; + boot:boot + { + pname = "boot"; + size = <0x0 0x1000000>; + mask = <1>; + }; + tee:tee{ + pname = "tee"; + size = <0x0 0x2000000>; + mask = <1>; + }; + vendor:vendor + { + pname = "vendor"; + size = <0x0 0x10000000>; + mask = <1>; + }; + odm:odm + { + pname = "odm"; + size = <0x0 0x10000000>; + mask = <1>; + }; + system:system + { + pname = "system"; + size = <0x0 0x80000000>; + mask = <1>; + }; + cache:cache + { + pname = "cache"; + size = <0x0 0x46000000>; + mask = <2>; + }; + data:data + { + pname = "data"; + size = <0xffffffff 0xffffffff>; + mask = <4>; + }; + }; + + ppmgr { + compatible = "amlogic, ppmgr"; + memory-region = <&ppmgr_reserved>; + dev_name = "ppmgr"; + status = "okay"; + }; + + deinterlace { + compatible = "amlogic, deinterlace"; + status = "okay"; + flag_cma = <1>;/*0:use reserved;1:use cma*/ + //memory-region = <&di_reserved>; + memory-region = <&di_cma_reserved>; + interrupts = <0 46 1 + 0 6 1>; + interrupt-names = "de_irq", + "timerc"; + /* mtn_size(byte) = 1920*544/2 */ + /* count_size(byte) = 1920*544/2 */ + /* mv_size(byte) = 1920*544*2/5 */ + /* mc_size(byte) = 544*2 */ + buffer-size = <3552320>; + hw-version = <2>; + /* reserve-iomap = "true"; */ + /* if enable nr10bit, set nr10bit-surpport to 1 */ + nr10bit-surpport = <0>; + }; + + ionvideo { + compatible = "amlogic, ionvideo"; + dev_name = "ionvideo"; + status = "okay"; + }; + + amlvideo { + compatible = "amlogic, amlvideo"; + dev_name = "amlvideo"; + status = "okay"; + }; + + amlvideo2_0 { + compatible = "amlogic, amlvideo2"; + dev_name = "amlvideo2"; + status = "okay"; + amlvideo2_id = <0>; + cma_mode = <1>; + }; + + amlvideo2_1 { + compatible = "amlogic, amlvideo2"; + dev_name = "amlvideo2"; + status = "okay"; + amlvideo2_id = <1>; + cma_mode = <1>; + }; + + /*if you want to use vdin just modify status to "ok"*/ + vdin0 { + compatible = "amlogic, vdin"; + /*memory-region = <&vdin0_cma_reserved>;*/ + dev_name = "vdin0"; + status = "ok"; + reserve-iomap = "true"; + flag_cma = <1>;/*1:share with codec_mm;2:cma alone*/ + /*MByte, if 10bit disable: 64M(YUV422), + *if 10bit enable: 64*1.5 = 96M(YUV422) + *if support 4K2K-YUV444-10bit-WR:3840*2160*4*4 ~= 128M + *if support 4K2K-YUV422-10bit-wr:3840*2160*3*4 ~= 96M + *if support 4K2K-YUV422-8BIT-WR:3840*2160*2*4 ~= 64M + *if support 1080p-YUV422-8BIT-WR:1920*1080*2*4 ~= 16M + */ + cma_size = <16>; + interrupts = <0 83 1>; + rdma-irq = <2>; + /*clocks = <&clock CLK_FPLL_DIV5>, + * <&clock CLK_VDIN_MEAS_CLK>; + *clock-names = "fclk_div5", "cts_vdin_meas_clk"; + */ + vdin_id = <0>; + /*vdin write mem color depth support: + *bit0:support 8bit + *bit1:support 9bit + *bit2:support 10bit + *bit3:support 12bit + *bit4:support yuv422 10bit full pack mode (from txl new add) + */ + tv_bit_mode = <1>; + }; + vdin1 { + compatible = "amlogic, vdin"; + memory-region = <&vdin1_cma_reserved>; + dev_name = "vdin1"; + status = "ok"; + reserve-iomap = "true"; + flag_cma = <0>;/*1:share with codec_mm;0:cma alone*/ + interrupts = <0 85 1>; + rdma-irq = <4>; + /*clocks = <&clock CLK_FPLL_DIV5>, + * <&clock CLK_VDIN_MEAS_CLK>; + *clock-names = "fclk_div5", "cts_vdin_meas_clk"; + */ + vdin_id = <1>; + /*vdin write mem color depth support: + *bit0:support 8bit + *bit1:support 9bit + *bit2:support 10bit + *bit3:support 12bit + */ + tv_bit_mode = <1>; + }; + + amlvecm { + compatible = "amlogic, vecm"; + dev_name = "aml_vecm"; + status = "okay"; + gamma_en = <0>;/*1:enabel ;0:disable*/ + wb_en = <0>;/*1:enabel ;0:disable*/ + cm_en = <0>;/*1:enabel ;0:disable*/ + /*1:enabel osd lut 100 table;0:disable*/ + cfg_en_osd_100 = <1>; + /*0: 709/601 1: bt2020*/ + tx_op_color_primary = <0>; + }; + + unifykey{ + compatible = "amlogic, unifykey"; + status = "ok"; + + unifykey-num = <15>; + unifykey-index-0 = <&keysn_0>; + unifykey-index-1 = <&keysn_1>; + unifykey-index-2 = <&keysn_2>; + unifykey-index-3 = <&keysn_3>; + unifykey-index-4 = <&keysn_4>; + unifykey-index-5 = <&keysn_5>; + unifykey-index-6 = <&keysn_6>; + unifykey-index-7 = <&keysn_7>; + unifykey-index-8 = <&keysn_8>; + unifykey-index-9 = <&keysn_9>; + unifykey-index-10= <&keysn_10>; + unifykey-index-11= <&keysn_11>; + unifykey-index-12= <&keysn_12>; + unifykey-index-13= <&keysn_13>; + unifykey-index-14= <&keysn_14>; + + keysn_0: key_0{ + key-name = "usid"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_1:key_1{ + key-name = "mac"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_2:key_2{ + key-name = "hdcp"; + key-device = "secure"; + key-type = "sha1"; + key-permit = "read","write","del"; + }; + keysn_3:key_3{ + key-name = "secure_boot_set"; + key-device = "efuse"; + key-permit = "write"; + }; + keysn_4:key_4{ + key-name = "mac_bt"; + key-device = "normal"; + key-permit = "read","write","del"; + key-type = "mac"; + }; + keysn_5:key_5{ + key-name = "mac_wifi"; + key-device = "normal"; + key-permit = "read","write","del"; + key-type = "mac"; + }; + keysn_6:key_6{ + key-name = "hdcp2_tx"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_7:key_7{ + key-name = "hdcp2_rx"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_8:key_8{ + key-name = "widevinekeybox"; + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_9:key_9{ + key-name = "deviceid"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_10:key_10{ + key-name = "hdcp22_fw_private"; + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_11:key_11{ + key-name = "PlayReadykeybox25"; + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_12:key_12{ + key-name = "prpubkeybox";// PlayReady + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_13:key_13{ + key-name = "prprivkeybox";// PlayReady + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_14:key_14{ + key-name = "attestationkeybox";// attestation key + key-device = "secure"; + key-permit = "read","write","del"; + }; + };//End unifykey + +}; + +&gpu{ + /*max gpu is 650M*/ + tbl = <&clk125_cfg &clk285_cfg &clk400_cfg + &clk500_cfg &clk666_cfg &clk666_cfg>; +}; + +&efuse { + status = "ok"; +}; + +&pwm_ef { + status = "okay"; +}; + +&audio_data{ + status = "okay"; +}; +&spicc{ + status = "disabled"; + pinctrl-names = "spicc_pulldown","spicc_pullup"; + pinctrl-0 = <&spicc_pulldown_x8x9x11>; + pinctrl-1 = <&spicc_pullup_x8x9x11>; + num_chipselect = <1>; + cs-gpios = <&gpio GPIOX_10 GPIO_ACTIVE_HIGH>; + dma_en = <0>; + dma_tx_threshold = <3>; + dma_rx_threshold = <3>; + dma_num_per_read_burst = <3>; + dma_num_per_write_burst = <3>; + delay_control = <0x15>; + ssctl = <0>; +}; + diff --git a/arch/arm/boot/dts/amlogic/gxl_p241_v2-1g.dts b/arch/arm/boot/dts/amlogic/gxl_p241_v2-1g.dts index eeb5267261a5..f7cf504250b0 100644 --- a/arch/arm/boot/dts/amlogic/gxl_p241_v2-1g.dts +++ b/arch/arm/boot/dts/amlogic/gxl_p241_v2-1g.dts @@ -79,6 +79,16 @@ alignment = <0x400000>; alloc-ranges = <0x3fc00000 0x400000>; }; + + codec_mm_cma:linux,codec_mm_cma { + compatible = "shared-dma-pool"; + reusable; + /* ion_codec_mm max can alloc size 80M*/ + size = <0xd000000>; + alignment = <0x400000>; + linux,contiguous-region; + alloc-ranges = <0x30000000 0x10000000>; + }; //don't put other dts in front of logo_reserved //di_reserved:linux,di { @@ -96,13 +106,14 @@ /** 10x4074560=39M(0x27) support 10bit **/ size = <0x02400000>; alignment = <0x400000>; + alloc-ranges = <0x30000000 0x10000000>; }; ion_reserved:linux,ion-dev { compatible = "shared-dma-pool"; reusable; size = <0x4C00000>; alignment = <0x400000>; - alloc-ranges = <0x0 0x2ee00000>; + alloc-ranges = <0x0 0x30000000>; }; /* vdin0 CMA pool */ @@ -121,6 +132,7 @@ /* 1920x1080x2x4 =16 M */ size = <0x01000000>; alignment = <0x400000>; + alloc-ranges = <0x0 0x30000000>; }; /* POST PROCESS MANAGER */ ppmgr_reserved:linux,ppmgr { @@ -128,16 +140,6 @@ size = <0x0>; multi-use; }; - - codec_mm_cma:linux,codec_mm_cma { - compatible = "shared-dma-pool"; - reusable; - /* ion_codec_mm max can alloc size 80M*/ - size = <0xd000000>; - alignment = <0x400000>; - linux,contiguous-region; - alloc-ranges = <0x12000000 0x13400000>; - }; picdec_cma_reserved:linux,picdec { compatible = "shared-dma-pool"; reusable; @@ -154,14 +156,14 @@ }; }; - dummy-battery { + amlogic_battery:dummy-battery { compatible = "amlogic, dummy-battery"; - status = "okay"; + status = "disabled"; }; - dummy-charger { + amlogic_charger:dummy-charger { compatible = "amlogic, dummy-charger"; - status = "okay"; + status = "disabled"; }; vpu { @@ -1301,3 +1303,4 @@ delay_control = <0x15>; ssctl = <0>; }; + diff --git a/arch/arm/boot/dts/amlogic/gxl_p241_v2_1g_buildroot.dts b/arch/arm/boot/dts/amlogic/gxl_p241_v2_1g_buildroot.dts new file mode 100644 index 000000000000..70808ebaf1f1 --- /dev/null +++ b/arch/arm/boot/dts/amlogic/gxl_p241_v2_1g_buildroot.dts @@ -0,0 +1,1357 @@ +/* + * arch/arm/boot/dts/amlogic/gxl_p241_v2-1g.dts + * + * Copyright (C) 2017 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +/dts-v1/; + +#include "mesongxl.dtsi" +#include "meson_drm.dtsi" +/ { + model = "Amlogic"; + amlogic-dt-id = "gxl_p241_v2-1g"; + compatible = "amlogic, Gxl"; + interrupt-parent = <&gic>; + #address-cells = <1>; + #size-cells = <1>; + + aliases { + serial0 = &uart_AO; + serial1 = &uart_C; + serial2 = &uart_B; + serial3 = &uart_A; + serial4 = &uart_AO_B; + }; + + ion_dev { + compatible = "amlogic, ion_dev"; + memory-region = <&ion_reserved>; + }; + + memory@00000000 { + device_type = "memory"; + linux,usable-memory = <0x0100000 0x3ff00000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + /* global autoconfigured region for contiguous allocations */ + ramoops@0x07400000 { + compatible = "ramoops"; + reg = <0x07400000 0x00100000>; + record-size = <0x8000>; + console-size = <0x8000>; + ftrace-size = <0x0>; + pmsg-size = <0x8000>; + }; + + secmon_reserved:linux,secmon { + compatible = "shared-dma-pool"; + reusable; + size = <0x400000>; + alignment = <0x400000>; + alloc-ranges = <0x05000000 0x400000>; + }; + secos_reserved:linux,secos { + status = "disable"; + compatible = "amlogic, aml_secos_memory"; + reg = <0x05300000 0x2000000>; + no-map; + }; + ion_reserved:linux,ion-dev { + compatible = "shared-dma-pool"; + reusable; + size = <0x8000000>; + alignment = <0x400000>; + }; + //don't put other dts in front of fb_reserved + + //di_reserved:linux,di { + // compatible = "amlogic, di-mem"; + /** 10x3133440=30M(0x1e) support 8bit **/ + // size = <0x1e00000>; + //no-map; + //}; + /*di CMA pool */ + di_cma_reserved:linux,di_cma { + compatible = "shared-dma-pool"; + reusable; + /** 10x3552320=34M(0x22) support 8bit **/ + /** 10x44596800=44M(0x2c) support 12bit **/ + /** 10x4074560=39M(0x27) support 10bit **/ + size = <0x02400000>; + alignment = <0x400000>; + }; + /* vdin0 CMA pool */ + //vdin0_cma_reserved:linux,vdin0_cma { + // compatible = "shared-dma-pool"; + // linux,phandle = <4>; + // reusable; + /* 1920x1080x2x4 =16+4 M */ + // size = <0x01400000>; + // alignment = <0x400000>; + //}; + /* vdin1 CMA pool */ + vdin1_cma_reserved:linux,vdin1_cma { + compatible = "shared-dma-pool"; + reusable; + /* 1920x1080x2x4 =16 M */ + size = <0x01000000>; + alignment = <0x400000>; + alloc-ranges = <0x0 0x30000000>; + }; + /* POST PROCESS MANAGER */ + ppmgr_reserved:linux,ppmgr { + compatible = "shared-dma-pool"; + size = <0x0>; + }; + + codec_mm_cma:linux,codec_mm_cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x7800000>; + alignment = <0x400000>; + linux,contiguous-region; + }; + picdec_cma_reserved:linux,picdec { + compatible = "shared-dma-pool"; + reusable; + size = <0x0>; + alignment = <0x0>; + linux,contiguous-region; + }; + /* codec shared reserved */ + codec_mm_reserved:linux,codec_mm_reserved { + compatible = "amlogic, codec-mm-reserved"; + size = <0x0>; + alignment = <0x100000>; + //no-map; + }; + }; + + vpu { + clk_level = <2>; + /* 0: 100.0M 1: 166.7M 2: 200.0M 3: 250.0M */ + /* 4: 333.3M 5: 400.0M 6: 500.0M 7: 666.7M */ + }; + + uart_AO: serial@c81004c0 { + compatible = "amlogic, meson-uart"; + reg = <0xc81004c0 0x18>; + interrupts = <0 193 1>; + status = "okay"; + clocks = <&xtal>; + clock-names = "clk_uart"; + xtal_tick_en = <1>; + fifosize = < 64 >; + pinctrl-names = "default"; + pinctrl-0 = <&ao_uart_pins>; + support-sysrq = <0>; /* 0 not support , 1 support */ + }; + + uart_A: serial@c11084c0 { + compatible = "amlogic, meson-uart"; + reg = <0xc11084c0 0x18>; + interrupts = <0 26 1>; + status = "disable"; + clocks = <&clkc CLKID_UART0>; + clock-names = "clk_uart"; + fifosize = < 128 >; + pinctrl-names = "default"; + // pinctrl-0 = <&a_uart_pins>; + }; + + uart_B: serial@c11084dc { + compatible = "amlogic, meson-uart"; + reg = <0xc11084dc 0x18>; + interrupts = <0 75 1>; + status = "disabled"; + clocks = <&clkc CLKID_UART1>; + clock-names = "clk_uart"; + fifosize = < 64 >; + pinctrl-names = "default"; + pinctrl-0 = <&b_uart_pins>; + }; + + uart_C: serial@c1108700 { + compatible = "amlogic, meson-uart"; + reg = <0xc1108700 0x18>; + interrupts = <0 93 1>; + status = "okay"; + clocks = <&clkc CLKID_UART2>; + clock-names = "clk_uart"; + fifosize = < 64 >; + pinctrl-names = "default"; + pinctrl-0 = <&c_uart_pins>; + }; + + uart_AO_B: serial@c81004e0 { + compatible = "amlogic, meson-uart"; + reg = <0xc81004e0 0x18>; + interrupts = <0 197 1>; + status = "disable"; + clocks = <&xtal>; + clock-names = "clk_uart"; + fifosize = < 64 >; + pinctrl-names = "default"; + pinctrl-0 = <&ao_b_uart_pins>; + }; + + bt-dev{ + compatible = "amlogic, bt-dev"; + dev_name = "bt-dev"; + status = "okay"; + gpio_reset = <&gpio GPIOX_12 GPIO_ACTIVE_HIGH>; + }; + + wifi{ + compatible = "amlogic, aml_wifi"; + dev_name = "aml_wifi"; + status = "okay"; + interrupt_pin = <&gpio GPIOX_7 GPIO_ACTIVE_HIGH>; + interrupts = < 0 68 4>; + irq_trigger_type = "GPIO_IRQ_LOW"; + dhd_static_buf; //dhd_static_buf support + power_on_pin = <&gpio GPIOX_6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_32k_pins>; + pwm_config = <&wifi_pwm_conf>; + }; + + wifi_pwm_conf:wifi_pwm_conf{ + pwm_channel1_conf { + pwms = <&pwm_ef MESON_PWM_0 30040 0>; + duty-cycle = <15020>; + times = <8>; + }; + pwm_channel2_conf { + pwms = <&pwm_ef MESON_PWM_2 30030 0>; + duty-cycle = <15015>; + times = <12>; + }; + }; + + sd_emmc_c: emmc@d0074000 { + status = "okay"; + compatible = "amlogic, meson-mmc-gxl"; + reg = <0xd0074000 0x2000>; + interrupts = <0 218 1>; + pinctrl-names = "emmc_clk_cmd_pins", "emmc_all_pins"; + pinctrl-0 = <&emmc_clk_cmd_pins>; + pinctrl-1 = <&emmc_conf_pull_up &emmc_conf_pull_done>; + clocks = <&clkc CLKID_SD_EMMC_C>, + <&clkc CLKID_SD_EMMC_C_P0_COMP>, + <&clkc CLKID_FCLK_DIV2>; + clock-names = "core", "clkin0", "clkin1"; + + bus-width = <8>; + cap-sd-highspeed; + cap-mmc-highspeed; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + + max-frequency = <200000000>; + non-removable; + disable-wp; + emmc { + pinname = "emmc"; + ocr_avail = <0x200080>; /**VDD voltage 3.3 ~ 3.4 */ + caps = "MMC_CAP_8_BIT_DATA", + "MMC_CAP_MMC_HIGHSPEED", + "MMC_CAP_SD_HIGHSPEED", + "MMC_CAP_NONREMOVABLE", + "MMC_CAP_1_8V_DDR", + "MMC_CAP_HW_RESET", + "MMC_CAP_ERASE", + "MMC_CAP_CMD23"; + // caps2 = "MMC_CAP2_HS200", "MMC_CAP2_HS400"; + f_min = <300000>; + f_max = <50000000>; + max_req_size = <0x20000>; /**128KB*/ + gpio_dat3 = <&gpio BOOT_3 GPIO_ACTIVE_HIGH>; + hw_reset = <&gpio BOOT_9 GPIO_ACTIVE_HIGH>; + card_type = <1>; + /* 1:mmc card(include eMMC), + * 2:sd card(include tSD) + */ + }; + }; + + sd_emmc_b:sd@d0072000 { + status = "okay"; + compatible = "amlogic, meson-mmc-gxl"; + reg = <0xd0072000 0x2000>; + interrupts = <0 217 1>; + pinctrl-names = "sd_all_pins", + "sd_clk_cmd_pins", + "sd_clk_cmd_uart_pins", + "sd_to_ao_uart_pins", + "ao_to_sd_uart_pins"; + pinctrl-0 = <&sd_all_pins>; + pinctrl-1 = <&sd_clk_cmd_pins>; + pinctrl-2 = <&sd_clk_cmd_pins &ao_to_sd_uart_pins>; + pinctrl-3 = <&sd_to_ao_uart_pins>; + pinctrl-4 = <&ao_to_sd_uart_pins>; + clocks = <&clkc CLKID_SD_EMMC_B>, + <&clkc CLKID_SD_EMMC_B_P0_COMP>, + <&clkc CLKID_FCLK_DIV2>; + clock-names = "core", "clkin0", "clkin1"; + + bus-width = <4>; + cap-sd-highspeed; + max-frequency = <100000000>; + disable-wp; + sd { + pinname = "sd"; + ocr_avail = <0x200080>; /**VDD voltage 3.3 ~ 3.4 */ + caps = "MMC_CAP_4_BIT_DATA", + "MMC_CAP_MMC_HIGHSPEED", + "MMC_CAP_SD_HIGHSPEED"; + /* "MMC_CAP_UHS_SDR12", + * "MMC_CAP_UHS_SDR25", + * "MMC_CAP_UHS_SDR50", + * "MMC_CAP_UHS_SDR104"; + */ + f_min = <400000>; + f_max = <100000000>; + max_req_size = <0x20000>; /**128KB*/ + gpio_dat3 = <&gpio CARD_4 GPIO_ACTIVE_HIGH>; + jtag_pin = <&gpio CARD_0 GPIO_ACTIVE_HIGH>; + gpio_cd = <&gpio CARD_6 GPIO_ACTIVE_HIGH>; + card_type = <5>; + /* 0:unknown, + * 1:mmc card(include eMMC), + * 2:sd card(include tSD), + * 3:sdio device(ie:sdio-wifi), + * 4:SD combo (IO+mem) card, + * 5:NON sdio device(means sd/mmc card), + * other:reserved + */ + }; + }; + + sd_emmc_a:sdio@d0070000 { + status = "okay"; + compatible = "amlogic, meson-mmc-gxl"; + reg = <0xd0070000 0x2000>; + interrupts = <0 216 4>; + pinctrl-names = "sdio_clk_cmd_pins", "sdio_all_pins"; + pinctrl-0 = <&sdio_clk_cmd_pins>; + pinctrl-1 = <&sdio_all_pins>; + clocks = <&clkc CLKID_SD_EMMC_A>, + <&clkc CLKID_SD_EMMC_A_P0_COMP>, + <&clkc CLKID_FCLK_DIV2>; + clock-names = "core", "clkin0", "clkin1"; + + bus-width = <4>; + cap-sd-highspeed; + cap-mmc-highspeed; + max-frequency = <100000000>; + non-removable; + disable-wp; + sdio { + pinname = "sdio"; + ocr_avail = <0x200080>; /**VDD voltage 3.3 ~ 3.4 */ + caps = "MMC_CAP_4_BIT_DATA", + "MMC_CAP_MMC_HIGHSPEED", + "MMC_CAP_SD_HIGHSPEED", + "MMC_CAP_NONREMOVABLE", + "MMC_CAP_UHS_SDR12", + "MMC_CAP_UHS_SDR25", + "MMC_CAP_UHS_SDR50", + "MMC_CAP_UHS_SDR104", + "MMC_PM_KEEP_POWER", + "MMC_CAP_SDIO_IRQ"; + f_min = <400000>; + f_max = <200000000>; + max_req_size = <0x20000>; /**128KB*/ + card_type = <3>; + /* 3:sdio device(ie:sdio-wifi), + * 4:SD combo (IO+mem) card + */ + }; + }; + mtd_nand{ + compatible = "amlogic, aml_mtd_nand"; + dev_name = "mtdnand"; + status = "disabled"; + reg = <0xd0074800 0x200>; + interrupts = < 0 34 1 >; + pinctrl-names = "nand_rb_mod","nand_norb_mod", "nand_cs_only"; + pinctrl-0 = <&all_nand_pins>; + pinctrl-1 = <&all_nand_pins>; + pinctrl-2 = <&nand_cs_pins>; + device_id = <0>; + plat-names = "bootloader","nandnormal"; + plat-num = <2>; + plat-part-0 = <&bootloader>; + plat-part-1 = <&nandnormal>; + bootloader: bootloader{ + enable_pad ="ce0"; + busy_pad = "rb0"; + timming_mode = "mode5"; + bch_mode = "bch60_1k"; + t_rea = <20>; + t_rhoh = <15>; + chip_num = <1>; + part_num = <0>; + rb_detect = <1>; + }; + nandnormal: nandnormal{ + enable_pad ="ce0","ce1"; + busy_pad = "rb0","rb1"; + timming_mode = "mode5"; + bch_mode = "bch60_1k"; + plane_mode = "twoplane"; + t_rea = <20>; + t_rhoh = <15>; + chip_num = <2>; + part_num = <3>; + partition = <&nand_partitions>; + rb_detect = <1>; + }; + nand_partitions:nand_partition{ + logo{ + offset=<0x0 0x0>; + size=<0x0 0x200000>; + }; + recovery{ + offset=<0x0 0x0>; + size=<0x0 0x1000000>; + }; + boot{ + offset=<0x0 0x0>; + size=<0x0 0xC00000>; + }; + system{ + offset=<0x0 0x0>; + size=<0x0 0xDC40000>; + }; + data{ + offset=<0xffffffff 0xffffffff>; + size=<0x0 0x0>; + }; + }; + }; + + ethmac: ethernet@0xc9410000 { + compatible = "amlogic, gxbb-eth-dwmac"; + reg = <0xc9410000 0x10000 + 0xc8834540 0x8 + 0xc8834558 0xc>; + interrupts = <0 8 1>; + pinctrl-names = "external_eth_pins"; + pinctrl-0 = <&external_eth_pins>; + rst_pin-gpios = <&gpio GPIOZ_14 0>; + GPIOZ4_pin-gpios = <&gpio GPIOZ_4 0>; + GPIOZ5_pin-gpios = <&gpio GPIOZ_5 0>; + mc_val_internal_phy = <0x1800>; + mc_val_external_phy = <0x1621>; + cali_val = <0x20000>; + interrupt-names = "macirq"; + clocks = <&clkc CLKID_ETH>; + clock-names = "ethclk81"; + internal_phy=<1>; + }; + + aml_sensor0: aml-sensor@0 { + compatible = "amlogic, aml-thermal"; + device_name = "thermal"; + #thermal-sensor-cells = <1>; + cooling_devices { + cpufreq_cool_cluster0 { + min_state = <1000000>; + dyn_coeff = <140>; + cluster_id = <0>; + node_name = "cpufreq_cool0"; + device_type = "cpufreq"; + }; + cpucore_cool_cluster0 { + min_state = <1>; + dyn_coeff = <0>; + cluster_id = <0>; + node_name = "cpucore_cool0"; + device_type = "cpucore"; + }; + gpufreq_cool { + min_state = <400>; + dyn_coeff = <437>; + cluster_id = <0>; + node_name = "gpufreq_cool0"; + device_type = "gpufreq"; + }; + gpucore_cool { + min_state = <1>; + dyn_coeff = <0>; + cluster_id = <0>; + node_name = "gpucore_cool0"; + device_type = "gpucore"; + }; + }; + cpufreq_cool0:cpufreq_cool0 { + #cooling-cells = <2>; /* min followed by max */ + }; + cpucore_cool0:cpucore_cool0 { + #cooling-cells = <2>; /* min followed by max */ + }; + gpufreq_cool0:gpufreq_cool0 { + #cooling-cells = <2>; /* min followed by max */ + }; + gpucore_cool0:gpucore_cool0 { + #cooling-cells = <2>; /* min followed by max */ + }; + }; + thermal-zones { + soc_thermal { + polling-delay = <1000>; + polling-delay-passive = <100>; + sustainable-power = <2150>; + + thermal-sensors = <&aml_sensor0 3>; + + trips { + switch_on: trip-point@0 { + temperature = <70000>; + hysteresis = <1000>; + type = "passive"; + }; + control: trip-point@1 { + temperature = <80000>; + hysteresis = <1000>; + type = "passive"; + }; + hot: trip-point@2 { + temperature = <85000>; + hysteresis = <5000>; + type = "hot"; + }; + critical: trip-point@3 { + temperature = <260000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + + cooling-maps { + cpufreq_cooling_map { + trip = <&control>; + cooling-device = <&cpufreq_cool0 0 4>; + contribution = <1024>; + }; + cpucore_cooling_map { + trip = <&control>; + cooling-device = <&cpucore_cool0 0 3>; + contribution = <1024>; + }; + gpufreq_cooling_map { + trip = <&control>; + cooling-device = <&gpufreq_cool0 0 4>; + contribution = <1024>; + }; + gpucore_cooling_map { + trip = <&control>; + cooling-device = <&gpucore_cool0 0 2>; + contribution = <1024>; + }; + }; + }; + }; + + dwc3: dwc3@c9000000 { + compatible = "synopsys, dwc3"; + reg = <0xc9000000 0x100000>; + interrupts = <0 30 4>; + usb-phy = <&usb2_phy>, <&usb3_phy>; + cpu-type = "gxl"; + clock-src = "usb3.0"; + }; + + usb2_phy: usb2phy@d0078000 { + compatible = "amlogic, amlogic-new-usb2"; + portnum = <3>; + reg = <0xd0078000 0x80 + 0xc1104408 0x4>; + }; + + usb3_phy: usb3phy@d0078080 { + compatible = "amlogic, amlogic-new-usb3"; + portnum = <0>; + reg = <0xd0078080 0x20>; + }; + + dwc2_a { + compatible = "amlogic, dwc2"; + device_name = "dwc2_a"; + reg = <0xc9100000 0x40000>; + status = "okay"; + interrupts = <0 31 4>; + pl-periph-id = <0>; /** lm name */ + clock-src = "usb0"; /** clock src */ + port-id = <0>; /** ref to mach/usb.h */ + port-type = <2>; /** 0: otg, 1: host, 2: slave */ + port-speed = <0>; /** 0: default, high, 1: full */ + port-config = <0>; /** 0: default */ + port-dma = <0>; /** 0: default ... 6: disable*/ + port-id-mode = <0>; /** 0: hardware, 1: sw_host, 2: sw_slave*/ + usb-fifo = <728>; + cpu-type = "gxl"; + controller-type = <1>; /** 0: normal, 1: host, 2: device*/ + phy-reg = <0xd0078000>; + phy-reg-size = <0xa0>; + clocks = <&clkc CLKID_USB_GENERAL + &clkc CLKID_USB1_TO_DDR + &clkc CLKID_USB1>; + clock-names = "usb_general", + "usb1", + "usb1_to_ddr"; + }; + + meson-amvideom { + compatible = "amlogic, amvideom"; + dev_name = "amvideom"; + status = "okay"; + interrupts = <0 3 1>; + interrupt-names = "vsync"; + }; + + vout { + compatible = "amlogic, vout"; + dev_name = "vout"; + status = "okay"; + fr_auto_policy = <0>; + }; + + cvbsout { + compatible = "amlogic, cvbsout-gxl"; + dev_name = "cvbsout"; + status = "okay"; + clocks = <&clkc CLKID_VCLK2_ENCI + &clkc CLKID_VCLK2_VENCI0 + &clkc CLKID_VCLK2_VENCI1 + &clkc CLKID_DAC_CLK>; + clock-names = "venci_top_gate", + "venci_0_gate", + "venci_1_gate", + "vdac_clk_gate"; + + /* performance: reg_address, reg_value */ + /* s805x */ + performance = <0x1bf0 0x9 + 0x1b56 0x343 + 0x1b12 0x8080 + 0x1b05 0xfd + 0x1c59 0xf752 + 0xffff 0x0>; /* ending flag */ + }; + + amhdmitx: amhdmitx{ + compatible = "amlogic, amhdmitx"; + dev_name = "amhdmitx"; + status = "okay"; + vend-data = <&vend_data>; + pinctrl-names="hdmitx_hpd", "hdmitx_ddc"; + pinctrl-0=<&hdmitx_hpd>; + pinctrl-1=<&hdmitx_ddc>; + /* HPD, 57 + 32 = 89; CEC, 151 + 32 = 183*/ + interrupts = <0 57 1>; + interrupt-names = "hdmitx_hpd"; + /* 0:M8B 1:GXBB 2:GXTVBB 3:GXL 4:GXM + * 5:TXL 6:TXLX 7:AXG 8:GXLX 9:TXHD + */ + ic_type = <3>; + vend_data: vend_data{ /* Should modified by Customer */ + vendor_name = "Amlogic"; /* Max Chars: 8 */ + /* standards.ieee.org/develop/regauth/oui/oui.txt */ + vendor_id = <0x000000>; + product_desc = "MBox Meson Ref"; /* Max Chars: 16 */ + }; + }; + + aocec: aocec{ + compatible = "amlogic, amlogic-aocec"; + device_name = "aocec"; + status = "okay"; + vendor_id = <0x000000>; + cec_osd_string = "MBox"; /* Max Chars: 14 */ + cec_version = <6>; /* 5: 1.4, 6: 2.0 */ + port_num = <1>; + arc_port_mask = <0x0>; + interrupts = <0 199 1>; + interrupt-names = "hdmi_aocec"; + pinctrl-names = "default"; + pinctrl-0=<&hdmitx_aocec>; + reg = <0xc810023c 0x4 + 0xc8100000 0x200>; + reg-names = "ao_exit","ao"; + }; + + sysled { + compatible = "amlogic, sysled"; + dev_name = "sysled"; + status = "okay"; + led_gpio = <&gpio GPIODV_27 GPIO_ACTIVE_HIGH>; + led_active_low = <1>; + }; + + codec_io { + compatible = "amlogic, codec_io"; + #address-cells=<1>; + #size-cells=<1>; + ranges; + io_cbus_base{ + reg = <0xC1100000 0x100000>; + }; + io_dos_base{ + reg = <0xc8820000 0x10000>; + }; + io_hiubus_base{ + reg = <0xc883c000 0x2000>; + }; + io_aobus_base{ + reg = <0xc8100000 0x100000>; + }; + io_vcbus_base{ + reg = <0xd0100000 0x40000>; + }; + io_dmc_base{ + reg = <0xc8838000 0x400>; + }; + }; + + codec_mm { + compatible = "amlogic, codec, mm"; + memory-region = <&codec_mm_cma &codec_mm_reserved>; + dev_name = "codec_mm"; + status = "okay"; + }; + + canvas{ + compatible = "amlogic, meson, canvas"; + dev_name = "amlogic-canvas"; + status = "ok"; + reg = <0xc8838000 0x400>; + }; + + mesonstream { + compatible = "amlogic, codec, streambuf"; + dev_name = "mesonstream"; + status = "okay"; + clocks = <&clkc CLKID_DOS_PARSER + &clkc CLKID_DEMUX + &clkc CLKID_DOS + &clkc CLKID_VDEC_MUX + &clkc CLKID_HCODEC_MUX + &clkc CLKID_HEVC_MUX>; + clock-names = "parser_top", + "demux", + "vdec", + "clk_vdec_mux", + "clk_hcodec_mux", + "clk_hevc_mux"; + }; + + vdec { + compatible = "amlogic, vdec"; + dev_name = "vdec.0"; + status = "okay"; + interrupts = <0 3 1 + 0 23 1 + 0 32 1 + 0 43 1 + 0 44 1 + 0 45 1>; + interrupt-names = "vsync", + "demux", + "parser", + "mailbox_0", + "mailbox_1", + "mailbox_2"; + }; + + meson-fb { + compatible = "amlogic, meson-gxl"; + dev_name = "meson-fb"; + status = "okay"; + interrupts = <0 3 1 + 0 89 1>; + interrupt-names = "viu-vsync", "rdma"; + mem_size = <0x00300000 0x00b00000 0x00100000>; + /* uboot logo,fb0/fb1 memory size */ + display_mode_default = "720p60hz"; + scale_mode = <1>; + /** 0:VPU free scale 1:OSD free scale 2:OSD super scale */ + display_size_default = <1280 720 1280 2160 32>; + /*1920*1080*4*3 = 0x17BB000*/ + mem_alloc = <1>; + logo_addr = "0x3f000000"; + }; + ge2d { + compatible = "amlogic, ge2d-gxl"; + dev_name = "ge2d"; + status = "okay"; + interrupts = <0 150 1>; + interrupt-names = "ge2d"; + clocks = <&clkc CLKID_VAPB_MUX>, + <&clkc CLKID_G2D>, + <&clkc CLKID_GE2D_GATE>; + clock-names = "clk_vapb_0", + "clk_ge2d", + "clk_ge2d_gate"; + }; + + + /* AUDIO MESON DEVICES */ + i2s_dai: I2S { + #sound-dai-cells = <0>; + compatible = "amlogic, aml-i2s-dai"; + clocks = + <&clkc CLKID_MPLL2>, + <&clkc CLKID_AMCLK_COMP>, + <&clkc CLKID_AIU_GLUE>, + <&clkc CLKID_IEC958>, + <&clkc CLKID_I2S_OUT>, + <&clkc CLKID_AMCLK>, + <&clkc CLKID_AIFIFO2>, + <&clkc CLKID_MIXER>, + <&clkc CLKID_MIXER_IFACE>, + <&clkc CLKID_ADC>, + <&clkc CLKID_AIU_TOP>, + <&clkc CLKID_AOCLK_GATE>, + <&clkc CLKID_I2S_SPDIF>; + clock-names = + "mpll", + "mclk", + "top_glue", + "aud_buf", + "i2s_out", + "amclk_measure", + "aififo2", + "aud_mixer", + "mixer_reg", + "adc", + "top_level", + "aoclk", + "aud_in"; + i2s_pos_sync = <0>; + /*DMIC;*/ /* I2s Mic or Dmic, default for I2S mic */ + }; + dmic:snd_dmic { + #sound-dai-cells = <0>; + compatible = "aml, aml_snd_dmic"; + reg = <0xd0042000 0x2000>; + status = "okay"; + resets = < + &clkc CLKID_PDM_GATE + >; + reset-names = "pdm"; + pinctrl-names = "audio_dmic"; + pinctrl-0 = <&aml_dmic_pins>; + clocks = <&clkc CLKID_PDM_COMP>, + <&clkc CLKID_AMCLK_COMP>; + clock-names = "pdm", "mclk"; + }; + spdif_dai: SPDIF { + #sound-dai-cells = <0>; + compatible = "amlogic, aml-spdif-dai"; + clocks = + <&clkc CLKID_MPLL1>, + <&clkc CLKID_I958_COMP>, + <&clkc CLKID_AMCLK_COMP>, + <&clkc CLKID_I958_COMP_SPDIF>, + <&clkc CLKID_CLK81>, + <&clkc CLKID_IEC958>, + <&clkc CLKID_IEC958_GATE>; + clock-names = + "mpll1", + "i958", + "mclk", + "spdif", + "clk_81", + "iec958", + "iec958_amclk"; + }; + pcm_dai: PCM { + #sound-dai-cells = <0>; + compatible = "amlogic, aml-pcm-dai"; + pinctrl-names = "audio_pcm"; + // pinctrl-0 = <&audio_pcm_pins>; + clocks = + <&clkc CLKID_MPLL0>, + <&clkc CLKID_PCM_MCLK_COMP>, + <&clkc CLKID_PCM_SCLK_GATE>; + clock-names = + "mpll0", + "pcm_mclk", + "pcm_sclk"; + pcm_mode = <1>; /* 0=slave mode, 1=master mode */ + }; + i2s_plat: i2s_platform { + compatible = "amlogic, aml-i2s"; + interrupts = <0 29 1>; + }; + pcm_plat: pcm_platform { + compatible = "amlogic, aml-pcm"; + }; + spdif_codec: spdif_codec{ + #sound-dai-cells = <0>; + compatible = "amlogic, aml-spdif-codec"; + pinctrl-names = "audio_spdif"; + pinctrl-0 = <&audio_spdif_pins>; + }; + pcm_codec: pcm_codec{ + #sound-dai-cells = <0>; + compatible = "amlogic, pcm2BT-codec"; + }; + /* endof AUDIO MESON DEVICES */ + + /* AUDIO board specific */ + dummy_codec:dummy{ + #sound-dai-cells = <0>; + compatible = "amlogic, aml_dummy_codec"; + status = "disable"; + }; + amlogic_codec:t9015{ + #sound-dai-cells = <0>; + compatible = "amlogic, aml_codec_T9015"; + reg = <0xc8832000 0x14>; + status = "okay"; + }; + aml_sound_meson { + compatible = "aml, meson-snd-card"; + status = "okay"; + aml-sound-card,format = "i2s"; + aml_sound_card,name = "AML-MESONAUDIO"; + aml,audio-routing = + "Ext Spk","LOUTL", + "Ext Spk","LOUTR"; + + mute_gpio-gpios = <&gpio GPIOH_5 0>; + mute_inv; + hp_disable; + hp_paraments = <800 300 0 5 1>; + pinctrl-names = "audio_i2s"; + pinctrl-0 = <&audio_i2s_pins>; + cpu_list = <&cpudai0 &cpudai1 &cpudai2>; + codec_list = <&codec0 &codec1 &codec2>; + plat_list = <&i2s_plat &i2s_plat &pcm_plat>; + cpudai0: cpudai0 { + sound-dai = <&i2s_dai>; + }; + cpudai1: cpudai1 { + sound-dai = <&spdif_dai>; + }; + cpudai2: cpudai2 { + sound-dai = <&pcm_dai>; + }; + codec0: codec0 { + sound-dai = <&amlogic_codec>; + }; + codec1: codec1 { + sound-dai = <&spdif_codec>; + }; + codec2: codec2 { + sound-dai = <&pcm_codec>; + }; + }; + /* END OF AUDIO board specific */ + + rdma{ + compatible = "amlogic, meson, rdma"; + dev_name = "amlogic-rdma"; + status = "ok"; + interrupts = <0 89 1>; + interrupt-names = "rdma"; + }; + + amvenc_avc{ + compatible = "amlogic, amvenc_avc"; + dev_name = "amvenc_avc"; + status = "okay"; + interrupts = <0 45 1>; + interrupt-names = "mailbox_2"; + }; + + hevc_enc{ + compatible = "cnm, HevcEnc"; + dev_name = "HevcEnc"; + status = "okay"; + interrupts = <0 187 1>; + interrupt-names = "wave420l_irq"; + #address-cells=<1>; + #size-cells=<1>; + ranges; + io_reg_base{ + reg = <0xc8810000 0x4000>; + }; + }; + + partitions: partitions{ + parts = <14>; + part-0 = <&logo>; + part-1 = <&recovery>; + part-2 = <&misc>; + part-3 = <&dto>; + part-4 = <&cri_data>; + part-5 = <¶m>; + part-6 = <&boot>; + part-7 = <&rsv>; + part-8 = <&tee>; + part-9 = <&vendor>; + part-10 = <&odm>; + part-11 = <&system>; + part-12 = <&cache>; + part-13 = <&data>; + + logo:logo{ + pname = "logo"; + size = <0x0 0x800000>; + mask = <1>; + }; + recovery:recovery{ + pname = "recovery"; + size = <0x0 0x1800000>; + mask = <1>; + }; + misc:misc{ + pname = "misc"; + size = <0x0 0x800000>; + mask = <1>; + }; + dto:dto{ + pname = "dto"; + size = <0x0 0x800000>; + mask = <1>; + }; + cri_data:cri_data + { + pname = "cri_data"; + size = <0x0 0x800000>; + mask = <2>; + }; + rsv:rsv{ + pname = "rsv"; + size = <0x0 0x1000000>; + mask = <1>; + }; + param:param{ + pname = "param"; + size = <0x0 0x1000000>; + mask = <2>; + }; + boot:boot + { + pname = "boot"; + size = <0x0 0x1000000>; + mask = <1>; + }; + tee:tee{ + pname = "tee"; + size = <0x0 0x2000000>; + mask = <1>; + }; + vendor:vendor + { + pname = "vendor"; + size = <0x0 0x10000000>; + mask = <1>; + }; + odm:odm + { + pname = "odm"; + size = <0x0 0x10000000>; + mask = <1>; + }; + system:system + { + pname = "system"; + size = <0x0 0x80000000>; + mask = <1>; + }; + cache:cache + { + pname = "cache"; + size = <0x0 0x46000000>; + mask = <2>; + }; + data:data + { + pname = "data"; + size = <0xffffffff 0xffffffff>; + mask = <4>; + }; + }; + + ppmgr { + compatible = "amlogic, ppmgr"; + memory-region = <&ppmgr_reserved>; + dev_name = "ppmgr"; + status = "okay"; + }; + + deinterlace { + compatible = "amlogic, deinterlace"; + status = "okay"; + flag_cma = <1>;/*0:use reserved;1:use cma*/ + //memory-region = <&di_reserved>; + memory-region = <&di_cma_reserved>; + interrupts = <0 46 1 + 0 6 1>; + interrupt-names = "de_irq", + "timerc"; + /* mtn_size(byte) = 1920*544/2 */ + /* count_size(byte) = 1920*544/2 */ + /* mv_size(byte) = 1920*544*2/5 */ + /* mc_size(byte) = 544*2 */ + buffer-size = <3552320>; + hw-version = <2>; + /* reserve-iomap = "true"; */ + /* if enable nr10bit, set nr10bit-surpport to 1 */ + nr10bit-surpport = <0>; + }; + + ionvideo { + compatible = "amlogic, ionvideo"; + dev_name = "ionvideo"; + status = "okay"; + }; + + amlvideo { + compatible = "amlogic, amlvideo"; + dev_name = "amlvideo"; + status = "okay"; + }; + + amlvideo2_0 { + compatible = "amlogic, amlvideo2"; + dev_name = "amlvideo2"; + status = "okay"; + amlvideo2_id = <0>; + cma_mode = <1>; + }; + + amlvideo2_1 { + compatible = "amlogic, amlvideo2"; + dev_name = "amlvideo2"; + status = "okay"; + amlvideo2_id = <1>; + cma_mode = <1>; + }; + + /*if you want to use vdin just modify status to "ok"*/ + vdin0 { + compatible = "amlogic, vdin"; + /*memory-region = <&vdin0_cma_reserved>;*/ + dev_name = "vdin0"; + status = "ok"; + reserve-iomap = "true"; + flag_cma = <1>;/*1:share with codec_mm;2:cma alone*/ + /*MByte, if 10bit disable: 64M(YUV422), + *if 10bit enable: 64*1.5 = 96M(YUV422) + *if support 4K2K-YUV444-10bit-WR:3840*2160*4*4 ~= 128M + *if support 4K2K-YUV422-10bit-wr:3840*2160*3*4 ~= 96M + *if support 4K2K-YUV422-8BIT-WR:3840*2160*2*4 ~= 64M + *if support 1080p-YUV422-8BIT-WR:1920*1080*2*4 ~= 16M + */ + cma_size = <16>; + interrupts = <0 83 1>; + rdma-irq = <2>; + /*clocks = <&clock CLK_FPLL_DIV5>, + * <&clock CLK_VDIN_MEAS_CLK>; + *clock-names = "fclk_div5", "cts_vdin_meas_clk"; + */ + vdin_id = <0>; + /*vdin write mem color depth support: + *bit0:support 8bit + *bit1:support 9bit + *bit2:support 10bit + *bit3:support 12bit + *bit4:support yuv422 10bit full pack mode (from txl new add) + */ + tv_bit_mode = <1>; + }; + vdin1 { + compatible = "amlogic, vdin"; + memory-region = <&vdin1_cma_reserved>; + dev_name = "vdin1"; + status = "ok"; + reserve-iomap = "true"; + flag_cma = <0>;/*1:share with codec_mm;0:cma alone*/ + interrupts = <0 85 1>; + rdma-irq = <4>; + /*clocks = <&clock CLK_FPLL_DIV5>, + * <&clock CLK_VDIN_MEAS_CLK>; + *clock-names = "fclk_div5", "cts_vdin_meas_clk"; + */ + vdin_id = <1>; + /*vdin write mem color depth support: + *bit0:support 8bit + *bit1:support 9bit + *bit2:support 10bit + *bit3:support 12bit + */ + tv_bit_mode = <1>; + }; + + amlvecm { + compatible = "amlogic, vecm"; + dev_name = "aml_vecm"; + status = "okay"; + gamma_en = <0>;/*1:enabel ;0:disable*/ + wb_en = <0>;/*1:enabel ;0:disable*/ + cm_en = <0>;/*1:enabel ;0:disable*/ + /*1:enabel osd lut 100 table;0:disable*/ + cfg_en_osd_100 = <1>; + /*0: 709/601 1: bt2020*/ + tx_op_color_primary = <0>; + }; + + unifykey{ + compatible = "amlogic, unifykey"; + status = "ok"; + + unifykey-num = <15>; + unifykey-index-0 = <&keysn_0>; + unifykey-index-1 = <&keysn_1>; + unifykey-index-2 = <&keysn_2>; + unifykey-index-3 = <&keysn_3>; + unifykey-index-4 = <&keysn_4>; + unifykey-index-5 = <&keysn_5>; + unifykey-index-6 = <&keysn_6>; + unifykey-index-7 = <&keysn_7>; + unifykey-index-8 = <&keysn_8>; + unifykey-index-9 = <&keysn_9>; + unifykey-index-10= <&keysn_10>; + unifykey-index-11= <&keysn_11>; + unifykey-index-12= <&keysn_12>; + unifykey-index-13= <&keysn_13>; + unifykey-index-14= <&keysn_14>; + + keysn_0: key_0{ + key-name = "usid"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_1:key_1{ + key-name = "mac"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_2:key_2{ + key-name = "hdcp"; + key-device = "secure"; + key-type = "sha1"; + key-permit = "read","write","del"; + }; + keysn_3:key_3{ + key-name = "secure_boot_set"; + key-device = "efuse"; + key-permit = "write"; + }; + keysn_4:key_4{ + key-name = "mac_bt"; + key-device = "normal"; + key-permit = "read","write","del"; + key-type = "mac"; + }; + keysn_5:key_5{ + key-name = "mac_wifi"; + key-device = "normal"; + key-permit = "read","write","del"; + key-type = "mac"; + }; + keysn_6:key_6{ + key-name = "hdcp2_tx"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_7:key_7{ + key-name = "hdcp2_rx"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_8:key_8{ + key-name = "widevinekeybox"; + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_9:key_9{ + key-name = "deviceid"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_10:key_10{ + key-name = "hdcp22_fw_private"; + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_11:key_11{ + key-name = "PlayReadykeybox25"; + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_12:key_12{ + key-name = "prpubkeybox";// PlayReady + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_13:key_13{ + key-name = "prprivkeybox";// PlayReady + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_14:key_14{ + key-name = "attestationkeybox";// attestation key + key-device = "secure"; + key-permit = "read","write","del"; + }; + };//End unifykey + +}; + +&gpu{ + /*max gpu is 650M*/ + tbl = <&clk125_cfg &clk285_cfg &clk400_cfg + &clk500_cfg &clk666_cfg &clk666_cfg>; +}; + +&efuse { + status = "ok"; +}; + +&pwm_ef { + status = "okay"; +}; + +&audio_data{ + status = "okay"; +}; +&spicc{ + status = "disabled"; + pinctrl-names = "spicc_pulldown","spicc_pullup"; + pinctrl-0 = <&spicc_pulldown_x8x9x11>; + pinctrl-1 = <&spicc_pullup_x8x9x11>; + num_chipselect = <1>; + cs-gpios = <&gpio GPIOX_10 GPIO_ACTIVE_HIGH>; + dma_en = <0>; + dma_tx_threshold = <3>; + dma_rx_threshold = <3>; + dma_num_per_read_burst = <3>; + dma_num_per_write_burst = <3>; + delay_control = <0x15>; + ssctl = <0>; +}; + diff --git a/arch/arm/boot/dts/amlogic/gxl_p400_2g.dts b/arch/arm/boot/dts/amlogic/gxl_p400_2g.dts new file mode 100644 index 000000000000..8300389f44a1 --- /dev/null +++ b/arch/arm/boot/dts/amlogic/gxl_p400_2g.dts @@ -0,0 +1,873 @@ +/* + * arch/arm/boot/dts/amlogic/gxl_p400_2g.dts + * + * Copyright (C) 2017 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +/dts-v1/; + +#include +#include "mesongxl.dtsi" +/ { + model = "Amlogic"; + amlogic-dt-id = "gxl_p400_2g"; + compatible = "amlogic, Gxl"; + interrupt-parent = <&gic>; + #address-cells = <1>; + #size-cells = <1>; + + aliases { + serial0 = &uart_AO; + serial1 = &uart_A; + serial2 = &uart_B; + serial3 = &uart_C; + serial4 = &uart_AO_B; + }; + + + memory@00000000 { + device_type = "memory"; + linux,usable-memory = <0x0100000 0x7ff00000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + /* global autoconfigured region for contiguous allocations */ + ramoops@0x07400000 { + compatible = "ramoops"; + reg = <0x07400000 0x00100000>; + record-size = <0x8000>; + console-size = <0x8000>; + ftrace-size = <0x0>; + pmsg-size = <0x8000>; + }; + + secmon_reserved:linux,secmon { + compatible = "shared-dma-pool"; + reusable; + size = <0x400000>; + alignment = <0x400000>; + alloc-ranges = <0x05000000 0x400000>; + }; + secos_reserved:linux,secos { + status = "disable"; + compatible = "amlogic, aml_secos_memory"; + reg = <0x05300000 0x2000000>; + no-map; + }; + fb_reserved:linux,meson-fb { + compatible = "shared-dma-pool"; + reusable; + size = <0x2400000>; + alignment = <0x400000>; + alloc-ranges = <0x7dc00000 0x2400000>; + }; + }; + + wifi{ + compatible = "amlogic, aml_wifi"; + dev_name = "aml_wifi"; + status = "okay"; + interrupt_pin = <&gpio GPIOX_7 GPIO_ACTIVE_HIGH>; + irq_trigger_type = "GPIO_IRQ_LOW"; + power_on_pin = <&gpio GPIOX_6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_32k_pins>; + pwm_config = <&wifi_pwm_conf>; + }; + + wifi_pwm_conf:wifi_pwm_conf{ + pwm_channel1_conf { + pwms = <&pwm_ef MESON_PWM_0 30040 0>; + duty-cycle = <15020>; + times = <8>; + }; + pwm_channel2_conf { + pwms = <&pwm_ef MESON_PWM_2 30030 0>; + duty-cycle = <15015>; + times = <12>; + }; + }; + + sd_emmc_c: emmc@d0074000 { + status = "okay"; + compatible = "amlogic, meson-mmc-gxl"; + reg = <0xd0074000 0x2000>; + interrupts = <0 218 1>; + pinctrl-names = "emmc_clk_cmd_pins", "emmc_all_pins"; + pinctrl-0 = <&emmc_clk_cmd_pins>; + pinctrl-1 = <&emmc_conf_pull_up &emmc_conf_pull_done>; + clocks = <&clkc CLKID_SD_EMMC_C>, + <&clkc CLKID_SD_EMMC_C_P0_COMP>, + <&clkc CLKID_FCLK_DIV2>; + clock-names = "core", "clkin0", "clkin1"; + + bus-width = <8>; + cap-sd-highspeed; + cap-mmc-highspeed; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + + max-frequency = <200000000>; + non-removable; + disable-wp; + emmc { + pinname = "emmc"; + ocr_avail = <0x200080>; /**VDD voltage 3.3 ~ 3.4 */ + caps = "MMC_CAP_8_BIT_DATA", + "MMC_CAP_MMC_HIGHSPEED", + "MMC_CAP_SD_HIGHSPEED", + "MMC_CAP_NONREMOVABLE", + "MMC_CAP_1_8V_DDR", + "MMC_CAP_HW_RESET", + "MMC_CAP_ERASE", + "MMC_CAP_CMD23"; + caps2 = "MMC_CAP2_HS200", "MMC_CAP2_HS400"; + f_min = <400000>; + f_max = <100000000>; + max_req_size = <0x20000>; /**128KB*/ + gpio_dat3 = <&gpio BOOT_3 GPIO_ACTIVE_HIGH>; + hw_reset = <&gpio BOOT_9 GPIO_ACTIVE_HIGH>; + card_type = <1>; + /* 1:mmc card(include eMMC), + * 2:sd card(include tSD) + */ + }; + }; + + sd_emmc_b:sd@d0072000 { + status = "okay"; + compatible = "amlogic, meson-mmc-gxl"; + reg = <0xd0072000 0x2000>; + interrupts = <0 217 1>; + pinctrl-names = "sd_all_pins", + "sd_clk_cmd_pins", + "sd_1bit_pins", + "sd_clk_cmd_uart_pins", + "sd_1bit_uart_pins", + "sd_to_ao_uart_pins", + "ao_to_sd_uart_pins", + "ao_to_sd_jtag_pins", + "sd_to_ao_jtag_pins"; + pinctrl-0 = <&sd_all_pins>; + pinctrl-1 = <&sd_clk_cmd_pins>; + pinctrl-2 = <&sd_1bit_pins>; + pinctrl-3 = <&sd_to_ao_uart_clr_pins + &sd_clk_cmd_pins &ao_to_sd_uart_pins>; + pinctrl-4 = <&sd_to_ao_uart_clr_pins + &sd_1bit_pins &ao_to_sd_uart_pins>; + pinctrl-5 = <&sd_all_pins &sd_to_ao_uart_pins>; + pinctrl-6 = <&sd_to_ao_uart_clr_pins &ao_to_sd_uart_pins>; + pinctrl-7 = <&sd_to_ao_uart_clr_pins &ao_to_sd_uart_pins>; + pinctrl-8 = <&sd_all_pins &sd_to_ao_uart_pins>; + clocks = <&clkc CLKID_SD_EMMC_B>, + <&clkc CLKID_SD_EMMC_B_P0_COMP>, + <&clkc CLKID_FCLK_DIV2>; + clock-names = "core", "clkin0", "clkin1"; + + bus-width = <4>; + cap-sd-highspeed; + max-frequency = <100000000>; + disable-wp; + sd { + pinname = "sd"; + ocr_avail = <0x200080>; /**VDD voltage 3.3 ~ 3.4 */ + caps = "MMC_CAP_4_BIT_DATA", + "MMC_CAP_MMC_HIGHSPEED", + "MMC_CAP_SD_HIGHSPEED"; + /* "MMC_CAP_UHS_SDR12", + * "MMC_CAP_UHS_SDR25", + * "MMC_CAP_UHS_SDR50", + * "MMC_CAP_UHS_SDR104"; + */ + f_min = <400000>; + f_max = <100000000>; + max_req_size = <0x20000>; /**128KB*/ + gpio_dat3 = <&gpio CARD_4 GPIO_ACTIVE_HIGH>; + jtag_pin = <&gpio CARD_0 GPIO_ACTIVE_HIGH>; + gpio_cd = <&gpio CARD_6 GPIO_ACTIVE_HIGH>; + card_type = <5>; + /* 0:unknown, + * 1:mmc card(include eMMC), + * 2:sd card(include tSD), + * 3:sdio device(ie:sdio-wifi), + * 4:SD combo (IO+mem) card, + * 5:NON sdio device(means sd/mmc card), + * other:reserved + */ + }; + }; + + sd_emmc_a:sdio@d0070000 { + status = "okay"; + compatible = "amlogic, meson-mmc-gxl"; + reg = <0xd0070000 0x2000>; + interrupts = <0 216 4>; + pinctrl-names = "sdio_clk_cmd_pins", "sdio_all_pins"; + pinctrl-0 = <&sdio_clk_cmd_pins>; + pinctrl-1 = <&sdio_all_pins>; + clocks = <&clkc CLKID_SD_EMMC_A>, + <&clkc CLKID_SD_EMMC_A_P0_COMP>, + <&clkc CLKID_FCLK_DIV2>; + clock-names = "core", "clkin0", "clkin1"; + + bus-width = <4>; + cap-sd-highspeed; + cap-mmc-highspeed; + max-frequency = <100000000>; + non-removable; + disable-wp; + sdio { + pinname = "sdio"; + ocr_avail = <0x200080>; /**VDD voltage 3.3 ~ 3.4 */ + caps = "MMC_CAP_4_BIT_DATA", + "MMC_CAP_MMC_HIGHSPEED", + "MMC_CAP_SD_HIGHSPEED", + "MMC_CAP_NONREMOVABLE", + "MMC_CAP_UHS_SDR12", + "MMC_CAP_UHS_SDR25", + "MMC_CAP_UHS_SDR50", + "MMC_CAP_UHS_SDR104", + "MMC_PM_KEEP_POWER", + "MMC_CAP_SDIO_IRQ"; + f_min = <400000>; + f_max = <200000000>; + max_req_size = <0x20000>; /**128KB*/ + card_type = <3>; + /* 3:sdio device(ie:sdio-wifi), + * 4:SD combo (IO+mem) card + */ + }; + }; + + ethmac: ethernet@0xc9410000 { + compatible = "amlogic, gxbb-eth-dwmac"; + reg = <0xc9410000 0x10000 + 0xc8834540 0x8 + 0xc8834558 0xc>; + interrupts = <0 8 1>; + pinctrl-names = "external_eth_pins"; + pinctrl-0 = <&external_eth_pins>; + rst_pin-gpios = <&gpio GPIOZ_14 0>; + GPIOZ4_pin-gpios = <&gpio GPIOZ_4 0>; + GPIOZ5_pin-gpios = <&gpio GPIOZ_5 0>; + mc_val_internal_phy = <0x1800>; + mc_val_external_phy = <0x1621>; + cali_val = <0x20000>; + interrupt-names = "macirq"; + clocks = <&clkc CLKID_ETH>; + clock-names = "ethclk81"; + internal_phy=<1>; + }; + + codec_io { + compatible = "amlogic, codec_io"; + #address-cells=<1>; + #size-cells=<1>; + ranges; + io_cbus_base{ + reg = <0xC1100000 0x100000>; + }; + io_dos_base{ + reg = <0xc8820000 0x10000>; + }; + io_hiubus_base{ + reg = <0xc883c000 0x2000>; + }; + io_aobus_base{ + reg = <0xc8100000 0x100000>; + }; + io_vcbus_base{ + reg = <0xd0100000 0x40000>; + }; + io_dmc_base{ + reg = <0xc8838000 0x400>; + }; + }; + + aml_sensor0: aml-sensor@0 { + compatible = "amlogic, aml-thermal"; + device_name = "thermal"; + #thermal-sensor-cells = <1>; + cooling_devices { + cpufreq_cool_cluster0 { + min_state = <1000000>; + dyn_coeff = <140>; + cluster_id = <0>; + node_name = "cpufreq_cool0"; + device_type = "cpufreq"; + }; + cpucore_cool_cluster0 { + min_state = <1>; + dyn_coeff = <0>; + cluster_id = <0>; + node_name = "cpucore_cool0"; + device_type = "cpucore"; + }; + gpufreq_cool { + min_state = <400>; + dyn_coeff = <437>; + cluster_id = <0>; + node_name = "gpufreq_cool0"; + device_type = "gpufreq"; + }; + gpucore_cool { + min_state = <1>; + dyn_coeff = <0>; + cluster_id = <0>; + node_name = "gpucore_cool0"; + device_type = "gpucore"; + }; + }; + cpufreq_cool0:cpufreq_cool0 { + #cooling-cells = <2>; /* min followed by max */ + }; + cpucore_cool0:cpucore_cool0 { + #cooling-cells = <2>; /* min followed by max */ + }; + gpufreq_cool0:gpufreq_cool0 { + #cooling-cells = <2>; /* min followed by max */ + }; + gpucore_cool0:gpucore_cool0 { + #cooling-cells = <2>; /* min followed by max */ + }; + }; + thermal-zones { + soc_thermal { + polling-delay = <1000>; + polling-delay-passive = <100>; + sustainable-power = <2150>; + + thermal-sensors = <&aml_sensor0 3>; + + trips { + switch_on: trip-point@0 { + temperature = <70000>; + hysteresis = <1000>; + type = "passive"; + }; + control: trip-point@1 { + temperature = <80000>; + hysteresis = <1000>; + type = "passive"; + }; + hot: trip-point@2 { + temperature = <85000>; + hysteresis = <5000>; + type = "hot"; + }; + critical: trip-point@3 { + temperature = <260000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + + cooling-maps { + cpufreq_cooling_map { + trip = <&control>; + cooling-device = <&cpufreq_cool0 0 4>; + contribution = <1024>; + }; + cpucore_cooling_map { + trip = <&control>; + cooling-device = <&cpucore_cool0 0 3>; + contribution = <1024>; + }; + gpufreq_cooling_map { + trip = <&control>; + cooling-device = <&gpufreq_cool0 0 4>; + contribution = <1024>; + }; + gpucore_cooling_map { + trip = <&control>; + cooling-device = <&gpucore_cool0 0 2>; + contribution = <1024>; + }; + }; + }; + }; + + dwc3: dwc3@c9000000 { + compatible = "synopsys, dwc3"; + reg = <0xc9000000 0x100000>; + interrupts = <0 30 4>; + usb-phy = <&usb2_phy>, <&usb3_phy>; + cpu-type = "gxl"; + clock-src = "usb3.0"; + }; + + usb2_phy: usb2phy@d0078000 { + compatible = "amlogic, amlogic-new-usb2"; + portnum = <3>; + reg = <0xd0078000 0x80 + 0xc1104408 0x4>; + }; + + usb3_phy: usb3phy@d0078080 { + compatible = "amlogic, amlogic-new-usb3"; + portnum = <0>; + reg = <0xd0078080 0x20>; + interrupts = <0 16 4>; + otg = <1>; + gpio-vbus-power = "GPIOAO_5"; + gpios = <&gpio_ao GPIOAO_5 GPIO_ACTIVE_HIGH>; + }; + + dwc2_a { + compatible = "amlogic, dwc2"; + device_name = "dwc2_a"; + reg = <0xc9100000 0x40000>; + status = "okay"; + interrupts = <0 31 4>; + pl-periph-id = <0>; /** lm name */ + clock-src = "usb0"; /** clock src */ + port-id = <0>; /** ref to mach/usb.h */ + port-type = <2>; /** 0: otg, 1: host, 2: slave */ + port-speed = <0>; /** 0: default, high, 1: full */ + port-config = <0>; /** 0: default */ + port-dma = <0>; /** 0: default ... 6: disable*/ + port-id-mode = <0>; /** 0: hardware, 1: sw_host, 2: sw_slave*/ + usb-fifo = <728>; + cpu-type = "gxl"; + controller-type = <3>; /** 0: normal,1:host,2:device,3:otg*/ + phy-reg = <0xd0078000>; + phy-reg-size = <0xa0>; + clocks = <&clkc CLKID_USB_GENERAL + &clkc CLKID_USB1_TO_DDR + &clkc CLKID_USB1>; + clock-names = "usb_general", + "usb1", + "usb1_to_ddr"; + }; + + meson-amvideom { + compatible = "amlogic, amvideom"; + dev_name = "amvideom"; + status = "okay"; + interrupts = <0 3 1>; + interrupt-names = "vsync"; + }; + + vout { + compatible = "amlogic, vout"; + dev_name = "vout"; + status = "okay"; + fr_auto_policy = <0>; + }; + + meson-fb { + compatible = "amlogic, meson-gxl"; + memory-region = <&fb_reserved>; + dev_name = "meson-fb"; + status = "okay"; + interrupts = <0 3 1 + 0 89 1>; + interrupt-names = "viu-vsync", "rdma"; + mem_size = <0x00800000 0x01800000 0x00100000>; + /* uboot logo,fb0/fb1 memory size,if afbcd fb0=0x01851000 */ + display_mode_default = "1080p60hz"; + scale_mode = <1>; + /** 0:VPU free scale 1:OSD free scale 2:OSD super scale */ + display_size_default = <1920 1080 1920 3240 32>; + /*1920*1080*4*3 = 0x17BB000*/ + mem_alloc = <1>; + logo_addr = "0x7dc00000"; + }; + + ge2d { + compatible = "amlogic, ge2d-gxl"; + dev_name = "ge2d"; + status = "okay"; + interrupts = <0 150 1>; + interrupt-names = "ge2d"; + clocks = <&clkc CLKID_VAPB_MUX>, + <&clkc CLKID_G2D>, + <&clkc CLKID_GE2D_GATE>; + clock-names = "clk_vapb_0", + "clk_ge2d", + "clk_ge2d_gate"; + }; + + /* AUDIO MESON DEVICES */ + i2s_dai: I2S { + #sound-dai-cells = <0>; + compatible = "amlogic, aml-i2s-dai"; + clocks = + <&clkc CLKID_MPLL2>, + <&clkc CLKID_AMCLK_COMP>, + <&clkc CLKID_AIU_GLUE>, + <&clkc CLKID_IEC958>, + <&clkc CLKID_I2S_OUT>, + <&clkc CLKID_AMCLK>, + <&clkc CLKID_AIFIFO2>, + <&clkc CLKID_MIXER>, + <&clkc CLKID_MIXER_IFACE>, + <&clkc CLKID_ADC>, + <&clkc CLKID_AIU_TOP>, + <&clkc CLKID_AOCLK_GATE>, + <&clkc CLKID_I2S_SPDIF>; + clock-names = + "mpll", + "mclk", + "top_glue", + "aud_buf", + "i2s_out", + "amclk_measure", + "aififo2", + "aud_mixer", + "mixer_reg", + "adc", + "top_level", + "aoclk", + "aud_in"; + i2s_pos_sync = <1>; + /*DMIC;*/ /* I2s Mic or Dmic, default for I2S mic */ + }; + dmic:snd_dmic { + #sound-dai-cells = <0>; + compatible = "aml, aml_snd_dmic"; + reg = <0xd0042000 0x2000>; + status = "okay"; + resets = < + &clkc CLKID_PDM_GATE + >; + reset-names = "pdm"; + pinctrl-names = "audio_dmic"; + pinctrl-0 = <&aml_dmic_pins>; + clocks = <&clkc CLKID_PDM_COMP>, + <&clkc CLKID_AMCLK_COMP>; + clock-names = "pdm", "mclk"; + }; + spdif_dai: SPDIF { + #sound-dai-cells = <0>; + compatible = "amlogic, aml-spdif-dai"; + clocks = + <&clkc CLKID_MPLL1>, + <&clkc CLKID_I958_COMP>, + <&clkc CLKID_AMCLK_COMP>, + <&clkc CLKID_I958_COMP_SPDIF>, + <&clkc CLKID_CLK81>, + <&clkc CLKID_IEC958>, + <&clkc CLKID_IEC958_GATE>; + clock-names = + "mpll1", + "i958", + "mclk", + "spdif", + "clk_81", + "iec958", + "iec958_amclk"; + }; + pcm_dai: PCM { + #sound-dai-cells = <0>; + compatible = "amlogic, aml-pcm-dai"; + pinctrl-names = "audio_pcm"; + pinctrl-0 = <&audio_pcm_pins>; + clocks = + <&clkc CLKID_MPLL0>, + <&clkc CLKID_PCM_MCLK_COMP>, + <&clkc CLKID_PCM_SCLK_GATE>; + clock-names = + "mpll0", + "pcm_mclk", + "pcm_sclk"; + pcm_mode = <1>; /* 0=slave mode, 1=master mode */ + }; + i2s_plat: i2s_platform { + compatible = "amlogic, aml-i2s"; + interrupts = <0 29 1>; + }; + pcm_plat: pcm_platform { + compatible = "amlogic, aml-pcm"; + }; + spdif_codec: spdif_codec{ + #sound-dai-cells = <0>; + compatible = "amlogic, aml-spdif-codec"; + pinctrl-names = "audio_spdif"; + pinctrl-0 = <&audio_spdif_pins>; + }; + pcm_codec: pcm_codec{ + #sound-dai-cells = <0>; + compatible = "amlogic, pcm2BT-codec"; + }; + /* endof AUDIO MESON DEVICES */ + + /* AUDIO board specific */ + dummy_codec:dummy{ + #sound-dai-cells = <0>; + compatible = "amlogic, aml_dummy_codec"; + status = "okay"; + }; + amlogic_codec:t9015{ + #sound-dai-cells = <0>; + compatible = "amlogic, aml_codec_T9015"; + reg = <0xc8832000 0x14>; + status = "disable"; + }; + aml_sound_meson { + compatible = "aml, meson-snd-card"; + status = "okay"; + aml-sound-card,format = "i2s"; + aml_sound_card,name = "AML-MESONAUDIO"; + aml,audio-routing = + "Ext Spk","LOUTL", + "Ext Spk","LOUTR"; + + mute_gpio-gpios = <&gpio GPIOH_5 0>; + mute_inv; + hp_disable; + hp_paraments = <800 300 0 5 1>; + pinctrl-names = "audio_i2s"; + pinctrl-0 = <&audio_i2s_pins>; + cpu_list = <&cpudai0 &cpudai1 &cpudai2>; + codec_list = <&codec0 &codec1 &codec2>; + plat_list = <&i2s_plat &i2s_plat &pcm_plat>; + cpudai0: cpudai0 { + sound-dai = <&i2s_dai>; + }; + cpudai1: cpudai1 { + sound-dai = <&spdif_dai>; + }; + cpudai2: cpudai2 { + sound-dai = <&pcm_dai>; + }; + codec0: codec0 { + sound-dai = <&dummy_codec>; + }; + codec1: codec1 { + sound-dai = <&spdif_codec>; + }; + codec2: codec2 { + sound-dai = <&pcm_codec>; + }; + }; + /* END OF AUDIO board specific */ + rdma{ + compatible = "amlogic, meson, rdma"; + dev_name = "amlogic-rdma"; + status = "ok"; + interrupts = <0 89 1>; + interrupt-names = "rdma"; + }; + + partitions: partitions{ + parts = <11>; + part-0 = <&logo>; + part-1 = <&recovery>; + part-2 = <&rsv>; + part-3 = <&tee>; + part-4 = <&crypt>; + part-5 = <&misc>; + part-6 = <&instaboot>; + part-7 = <&boot>; + part-8 = <&system>; + part-9 = <&cache>; + part-10 = <&data>; + + logo:logo{ + pname = "logo"; + size = <0x0 0x2000000>; + mask = <1>; + }; + recovery:recovery{ + pname = "recovery"; + size = <0x0 0x2000000>; + mask = <1>; + }; + rsv:rsv{ + pname = "rsv"; + size = <0x0 0x800000>; + mask = <1>; + }; + tee:tee{ + pname = "tee"; + size = <0x0 0x800000>; + mask = <1>; + }; + crypt:crypt{ + pname = "crypt"; + size = <0x0 0x2000000>; + mask = <1>; + }; + misc:misc{ + pname = "misc"; + size = <0x0 0x2000000>; + mask = <1>; + }; + instaboot:instaboot{ + pname = "instaboot"; + size = <0x0 0x400000>; + mask = <1>; + }; + boot:boot + { + pname = "boot"; + size = <0x0 0x2000000>; + mask = <1>; + }; + system:system + { + pname = "system"; + size = <0x0 0x80000000>; + mask = <1>; + }; + cache:cache + { + pname = "cache"; + size = <0x0 0x20000000>; + mask = <2>; + }; + data:data + { + pname = "data"; + size = <0xffffffff 0xffffffff>; + mask = <4>; + }; + }; + + unifykey{ + compatible = "amlogic, unifykey"; + status = "ok"; + + unifykey-num = <15>; + unifykey-index-0 = <&keysn_0>; + unifykey-index-1 = <&keysn_1>; + unifykey-index-2 = <&keysn_2>; + unifykey-index-3 = <&keysn_3>; + unifykey-index-4 = <&keysn_4>; + unifykey-index-5 = <&keysn_5>; + unifykey-index-6 = <&keysn_6>; + unifykey-index-7 = <&keysn_7>; + unifykey-index-8 = <&keysn_8>; + unifykey-index-9 = <&keysn_9>; + unifykey-index-10= <&keysn_10>; + unifykey-index-11= <&keysn_11>; + unifykey-index-12= <&keysn_12>; + unifykey-index-13= <&keysn_13>; + unifykey-index-14= <&keysn_14>; + + keysn_0: key_0{ + key-name = "usid"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_1:key_1{ + key-name = "mac"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_2:key_2{ + key-name = "hdcp"; + key-device = "secure"; + key-type = "sha1"; + key-permit = "read","write","del"; + }; + keysn_3:key_3{ + key-name = "secure_boot_set"; + key-device = "efuse"; + key-permit = "write"; + }; + keysn_4:key_4{ + key-name = "mac_bt"; + key-device = "normal"; + key-permit = "read","write","del"; + key-type = "mac"; + }; + keysn_5:key_5{ + key-name = "mac_wifi"; + key-device = "normal"; + key-permit = "read","write","del"; + key-type = "mac"; + }; + keysn_6:key_6{ + key-name = "hdcp2_tx"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_7:key_7{ + key-name = "hdcp2_rx"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_8:key_8{ + key-name = "widevinekeybox"; + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_9:key_9{ + key-name = "deviceid"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_10:key_10{ + key-name = "hdcp22_fw_private"; + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_11:key_11{ + key-name = "PlayReadykeybox25"; + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_12:key_12{ + key-name = "prpubkeybox";// PlayReady + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_13:key_13{ + key-name = "prprivkeybox";// PlayReady + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_14:key_14{ + key-name = "attestationkeybox";// attestation key + key-device = "secure"; + key-permit = "read","write","del"; + }; + };//End unifykey +}; + +&efuse { + status = "ok"; +}; + +&pwm_ef { + status = "okay"; +}; + +&audio_i2s_pins { + mux { + groups = "i2s_am_clk", + "i2s_ao_clk_out", + "i2s_lr_clk_out", + "i2sout_ch01", + "i2sin_ch23", + "i2sin_ch45", + "i2sin_ch67"; + function = "i2s"; + }; +}; + +&i2c_AO { + status = "okay"; + pca9557:pca9557@0x1f{ + compatible = "nxp,pca9557"; + reg = <0x1f>; + status = "okay"; + }; +}; + diff --git a/arch/arm/boot/dts/amlogic/gxl_p401_2g.dts b/arch/arm/boot/dts/amlogic/gxl_p401_2g.dts new file mode 100644 index 000000000000..6fa99b61e3f3 --- /dev/null +++ b/arch/arm/boot/dts/amlogic/gxl_p401_2g.dts @@ -0,0 +1,961 @@ +/* + * arch/arm/boot/dts/amlogic/gxl_p401_2g.dts + * + * Copyright (C) 2017 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +/dts-v1/; + +#include +#include "mesongxl.dtsi" +/ { + model = "Amlogic"; + amlogic-dt-id = "gxl_p401_2g"; + compatible = "amlogic, Gxl"; + interrupt-parent = <&gic>; + #address-cells = <1>; + #size-cells = <1>; + + aliases { + serial0 = &uart_AO; + serial1 = &uart_A; + serial2 = &uart_B; + serial3 = &uart_C; + serial4 = &uart_AO_B; + }; + + + memory@00000000 { + device_type = "memory"; + linux,usable-memory = <0x0100000 0x7ff00000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + /* global autoconfigured region for contiguous allocations */ + ramoops@0x07400000 { + compatible = "ramoops"; + reg = <0x07400000 0x00100000>; + record-size = <0x8000>; + console-size = <0x8000>; + ftrace-size = <0x0>; + pmsg-size = <0x8000>; + }; + + secmon_reserved:linux,secmon { + compatible = "shared-dma-pool"; + reusable; + size = <0x400000>; + alignment = <0x400000>; + alloc-ranges = <0x05000000 0x400000>; + }; + secos_reserved:linux,secos { + status = "disable"; + compatible = "amlogic, aml_secos_memory"; + reg = <0x05300000 0x2000000>; + no-map; + }; + fb_reserved:linux,meson-fb { + compatible = "shared-dma-pool"; + reusable; + size = <0x2400000>; + alignment = <0x400000>; + alloc-ranges = <0x7dc00000 0x2400000>; + }; + }; + + wifi{ + compatible = "amlogic, aml_wifi"; + dev_name = "aml_wifi"; + status = "okay"; + interrupt_pin = <&gpio GPIOX_7 GPIO_ACTIVE_HIGH>; + irq_trigger_type = "GPIO_IRQ_LOW"; + power_on_pin = <&gpio GPIOX_6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_32k_pins>; + pwm_config = <&wifi_pwm_conf>; + }; + + wifi_pwm_conf:wifi_pwm_conf{ + pwm_channel1_conf { + pwms = <&pwm_ef MESON_PWM_0 30040 0>; + duty-cycle = <15020>; + times = <8>; + }; + pwm_channel2_conf { + pwms = <&pwm_ef MESON_PWM_2 30030 0>; + duty-cycle = <15015>; + times = <12>; + }; + }; + + sd_emmc_c: emmc@d0074000 { + status = "disabled"; + compatible = "amlogic, meson-mmc-gxl"; + reg = <0xd0074000 0x2000>; + interrupts = <0 218 1>; + pinctrl-names = "emmc_clk_cmd_pins", "emmc_all_pins"; + pinctrl-0 = <&emmc_clk_cmd_pins>; + pinctrl-1 = <&emmc_conf_pull_up &emmc_conf_pull_done>; + clocks = <&clkc CLKID_SD_EMMC_C>, + <&clkc CLKID_SD_EMMC_C_P0_COMP>, + <&clkc CLKID_FCLK_DIV2>; + clock-names = "core", "clkin0", "clkin1"; + + bus-width = <8>; + cap-sd-highspeed; + cap-mmc-highspeed; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + + max-frequency = <200000000>; + non-removable; + disable-wp; + emmc { + pinname = "emmc"; + ocr_avail = <0x200080>; /**VDD voltage 3.3 ~ 3.4 */ + caps = "MMC_CAP_8_BIT_DATA", + "MMC_CAP_MMC_HIGHSPEED", + "MMC_CAP_SD_HIGHSPEED", + "MMC_CAP_NONREMOVABLE", + "MMC_CAP_1_8V_DDR", + "MMC_CAP_HW_RESET", + "MMC_CAP_ERASE", + "MMC_CAP_CMD23"; + caps2 = "MMC_CAP2_HS200", "MMC_CAP2_HS400"; + f_min = <400000>; + f_max = <100000000>; + max_req_size = <0x20000>; /**128KB*/ + gpio_dat3 = <&gpio BOOT_3 GPIO_ACTIVE_HIGH>; + hw_reset = <&gpio BOOT_9 GPIO_ACTIVE_HIGH>; + card_type = <1>; + /* 1:mmc card(include eMMC), + * 2:sd card(include tSD) + */ + }; + }; + + sd_emmc_b:sd@d0072000 { + status = "okay"; + compatible = "amlogic, meson-mmc-gxl"; + reg = <0xd0072000 0x2000>; + interrupts = <0 217 1>; + pinctrl-names = "sd_all_pins", + "sd_clk_cmd_pins", + "sd_1bit_pins", + "sd_clk_cmd_uart_pins", + "sd_1bit_uart_pins", + "sd_to_ao_uart_pins", + "ao_to_sd_uart_pins", + "ao_to_sd_jtag_pins", + "sd_to_ao_jtag_pins"; + pinctrl-0 = <&sd_all_pins>; + pinctrl-1 = <&sd_clk_cmd_pins>; + pinctrl-2 = <&sd_1bit_pins>; + pinctrl-3 = <&sd_to_ao_uart_clr_pins + &sd_clk_cmd_pins &ao_to_sd_uart_pins>; + pinctrl-4 = <&sd_to_ao_uart_clr_pins + &sd_1bit_pins &ao_to_sd_uart_pins>; + pinctrl-5 = <&sd_all_pins &sd_to_ao_uart_pins>; + pinctrl-6 = <&sd_to_ao_uart_clr_pins &ao_to_sd_uart_pins>; + pinctrl-7 = <&sd_to_ao_uart_clr_pins &ao_to_sd_uart_pins>; + pinctrl-8 = <&sd_all_pins &sd_to_ao_uart_pins>; + clocks = <&clkc CLKID_SD_EMMC_B>, + <&clkc CLKID_SD_EMMC_B_P0_COMP>, + <&clkc CLKID_FCLK_DIV2>; + clock-names = "core", "clkin0", "clkin1"; + + bus-width = <4>; + cap-sd-highspeed; + max-frequency = <100000000>; + disable-wp; + sd { + pinname = "sd"; + ocr_avail = <0x200080>; /**VDD voltage 3.3 ~ 3.4 */ + caps = "MMC_CAP_4_BIT_DATA", + "MMC_CAP_MMC_HIGHSPEED", + "MMC_CAP_SD_HIGHSPEED"; + /* "MMC_CAP_UHS_SDR12", + * "MMC_CAP_UHS_SDR25", + * "MMC_CAP_UHS_SDR50", + * "MMC_CAP_UHS_SDR104"; + */ + f_min = <400000>; + f_max = <100000000>; + max_req_size = <0x20000>; /**128KB*/ + gpio_dat3 = <&gpio CARD_4 GPIO_ACTIVE_HIGH>; + jtag_pin = <&gpio CARD_0 GPIO_ACTIVE_HIGH>; + gpio_cd = <&gpio CARD_6 GPIO_ACTIVE_HIGH>; + card_type = <5>; + /* 0:unknown, + * 1:mmc card(include eMMC), + * 2:sd card(include tSD), + * 3:sdio device(ie:sdio-wifi), + * 4:SD combo (IO+mem) card, + * 5:NON sdio device(means sd/mmc card), + * other:reserved + */ + }; + }; + + sd_emmc_a:sdio@d0070000 { + status = "okay"; + compatible = "amlogic, meson-mmc-gxl"; + reg = <0xd0070000 0x2000>; + interrupts = <0 216 4>; + pinctrl-names = "sdio_clk_cmd_pins", "sdio_all_pins"; + pinctrl-0 = <&sdio_clk_cmd_pins>; + pinctrl-1 = <&sdio_all_pins>; + clocks = <&clkc CLKID_SD_EMMC_A>, + <&clkc CLKID_SD_EMMC_A_P0_COMP>, + <&clkc CLKID_FCLK_DIV2>; + clock-names = "core", "clkin0", "clkin1"; + + bus-width = <4>; + cap-sd-highspeed; + cap-mmc-highspeed; + max-frequency = <100000000>; + non-removable; + disable-wp; + sdio { + pinname = "sdio"; + ocr_avail = <0x200080>; /**VDD voltage 3.3 ~ 3.4 */ + caps = "MMC_CAP_4_BIT_DATA", + "MMC_CAP_MMC_HIGHSPEED", + "MMC_CAP_SD_HIGHSPEED", + "MMC_CAP_NONREMOVABLE", + "MMC_CAP_UHS_SDR12", + "MMC_CAP_UHS_SDR25", + "MMC_CAP_UHS_SDR50", + "MMC_CAP_UHS_SDR104", + "MMC_PM_KEEP_POWER", + "MMC_CAP_SDIO_IRQ"; + f_min = <400000>; + f_max = <200000000>; + max_req_size = <0x20000>; /**128KB*/ + card_type = <3>; + /* 3:sdio device(ie:sdio-wifi), + * 4:SD combo (IO+mem) card + */ + }; + }; + mtd_nand{ + compatible = "amlogic, aml_mtd_nand"; + dev_name = "mtdnand"; + status = "okay"; + reg = <0xd0074800 0x200>; + interrupts = < 0 34 1 >; + pinctrl-names = "nand_rb_mod","nand_norb_mod", "nand_cs_only"; + pinctrl-0 = <&all_nand_pins>; + pinctrl-1 = <&all_nand_pins>; + pinctrl-2 = <&nand_cs_pins>; + device_id = <0>; + + /*fip/tpl configurations, must be same + * with uboot if bl_mode was set as 1 + * bl_mode: 0 compact mode; 1 descrete mode + * if bl_mode was set as 1, fip configeration will work + */ + bl_mode = <1>; + /*copy count of fip*/ + fip_copies = <4>; + /*size of each fip copy */ + fip_size = <0x200000>; + nand_clk_ctrl = <0xd0074000>; + plat-names = "bootloader","nandnormal"; + plat-num = <2>; + plat-part-0 = <&bootloader>; + plat-part-1 = <&nandnormal>; + bootloader: bootloader{ + enable_pad ="ce0"; + busy_pad = "rb0"; + timming_mode = "mode5"; + bch_mode = "bch60_1k"; + t_rea = <20>; + t_rhoh = <15>; + chip_num = <1>; + part_num = <0>; + rb_detect = <1>; + }; + nandnormal: nandnormal{ + enable_pad ="ce0","ce1"; + busy_pad = "rb0","rb1"; + timming_mode = "mode5"; + bch_mode = "bch60_1k"; + plane_mode = "twoplane"; + t_rea = <20>; + t_rhoh = <15>; + chip_num = <2>; + part_num = <3>; + partition = <&nand_partitions>; + rb_detect = <1>; + }; + nand_partitions:nand_partition{ + + /* + * if bl_mode is 1, tpl size was generate by + * fip_copies * fip_size which + * will not skip bad when calculating + * the partition size; + * + * if bl_mode is 0, + * tpl partition must be comment out. + */ + tpl{ + offset=<0x0 0x0>; + size=<0x0 0x0>; + }; + logo{ + offset=<0x0 0x0>; + size=<0x0 0x200000>; + }; + recovery{ + offset=<0x0 0x0>; + size=<0x0 0x1000000>; + }; + boot{ + offset=<0x0 0x0>; + size=<0x0 0x1000000>; + }; + system{ + offset=<0x0 0x0>; + size=<0x0 0xDC00000>; + }; + data{ + offset=<0xffffffff 0xffffffff>; + size=<0x0 0x0>; + }; + }; + }; + + ethmac: ethernet@0xc9410000 { + compatible = "amlogic, gxbb-eth-dwmac"; + reg = <0xc9410000 0x10000 + 0xc8834540 0x8 + 0xc8834558 0xc>; + interrupts = <0 8 1>; + pinctrl-names = "external_eth_pins"; + pinctrl-0 = <&external_eth_pins>; + rst_pin-gpios = <&gpio GPIOZ_14 0>; + GPIOZ4_pin-gpios = <&gpio GPIOZ_4 0>; + GPIOZ5_pin-gpios = <&gpio GPIOZ_5 0>; + mc_val_internal_phy = <0x1800>; + mc_val_external_phy = <0x1621>; + cali_val = <0x20000>; + interrupt-names = "macirq"; + clocks = <&clkc CLKID_ETH>; + clock-names = "ethclk81"; + internal_phy=<1>; + }; + + codec_io { + compatible = "amlogic, codec_io"; + #address-cells=<1>; + #size-cells=<1>; + ranges; + io_cbus_base{ + reg = <0xC1100000 0x100000>; + }; + io_dos_base{ + reg = <0xc8820000 0x10000>; + }; + io_hiubus_base{ + reg = <0xc883c000 0x2000>; + }; + io_aobus_base{ + reg = <0xc8100000 0x100000>; + }; + io_vcbus_base{ + reg = <0xd0100000 0x40000>; + }; + io_dmc_base{ + reg = <0xc8838000 0x400>; + }; + }; + + aml_sensor0: aml-sensor@0 { + compatible = "amlogic, aml-thermal"; + device_name = "thermal"; + #thermal-sensor-cells = <1>; + cooling_devices { + cpufreq_cool_cluster0 { + min_state = <1000000>; + dyn_coeff = <140>; + cluster_id = <0>; + node_name = "cpufreq_cool0"; + device_type = "cpufreq"; + }; + cpucore_cool_cluster0 { + min_state = <1>; + dyn_coeff = <0>; + cluster_id = <0>; + node_name = "cpucore_cool0"; + device_type = "cpucore"; + }; + gpufreq_cool { + min_state = <400>; + dyn_coeff = <437>; + cluster_id = <0>; + node_name = "gpufreq_cool0"; + device_type = "gpufreq"; + }; + gpucore_cool { + min_state = <1>; + dyn_coeff = <0>; + cluster_id = <0>; + node_name = "gpucore_cool0"; + device_type = "gpucore"; + }; + }; + cpufreq_cool0:cpufreq_cool0 { + #cooling-cells = <2>; /* min followed by max */ + }; + cpucore_cool0:cpucore_cool0 { + #cooling-cells = <2>; /* min followed by max */ + }; + gpufreq_cool0:gpufreq_cool0 { + #cooling-cells = <2>; /* min followed by max */ + }; + gpucore_cool0:gpucore_cool0 { + #cooling-cells = <2>; /* min followed by max */ + }; + }; + thermal-zones { + soc_thermal { + polling-delay = <1000>; + polling-delay-passive = <100>; + sustainable-power = <2150>; + + thermal-sensors = <&aml_sensor0 3>; + + trips { + switch_on: trip-point@0 { + temperature = <70000>; + hysteresis = <1000>; + type = "passive"; + }; + control: trip-point@1 { + temperature = <80000>; + hysteresis = <1000>; + type = "passive"; + }; + hot: trip-point@2 { + temperature = <85000>; + hysteresis = <5000>; + type = "hot"; + }; + critical: trip-point@3 { + temperature = <260000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + + cooling-maps { + cpufreq_cooling_map { + trip = <&control>; + cooling-device = <&cpufreq_cool0 0 4>; + contribution = <1024>; + }; + cpucore_cooling_map { + trip = <&control>; + cooling-device = <&cpucore_cool0 0 3>; + contribution = <1024>; + }; + gpufreq_cooling_map { + trip = <&control>; + cooling-device = <&gpufreq_cool0 0 4>; + contribution = <1024>; + }; + gpucore_cooling_map { + trip = <&control>; + cooling-device = <&gpucore_cool0 0 2>; + contribution = <1024>; + }; + }; + }; + }; + + dwc3: dwc3@c9000000 { + compatible = "synopsys, dwc3"; + reg = <0xc9000000 0x100000>; + interrupts = <0 30 4>; + usb-phy = <&usb2_phy>, <&usb3_phy>; + cpu-type = "gxl"; + clock-src = "usb3.0"; + }; + + usb2_phy: usb2phy@d0078000 { + compatible = "amlogic, amlogic-new-usb2"; + portnum = <3>; + reg = <0xd0078000 0x80 + 0xc1104408 0x4>; + }; + + usb3_phy: usb3phy@d0078080 { + compatible = "amlogic, amlogic-new-usb3"; + portnum = <0>; + reg = <0xd0078080 0x20>; + interrupts = <0 16 4>; + otg = <1>; + gpio-vbus-power = "GPIOAO_5"; + gpios = <&gpio_ao GPIOAO_5 GPIO_ACTIVE_HIGH>; + }; + + dwc2_a { + compatible = "amlogic, dwc2"; + device_name = "dwc2_a"; + reg = <0xc9100000 0x40000>; + status = "okay"; + interrupts = <0 31 4>; + pl-periph-id = <0>; /** lm name */ + clock-src = "usb0"; /** clock src */ + port-id = <0>; /** ref to mach/usb.h */ + port-type = <2>; /** 0: otg, 1: host, 2: slave */ + port-speed = <0>; /** 0: default, high, 1: full */ + port-config = <0>; /** 0: default */ + port-dma = <0>; /** 0: default ... 6: disable*/ + port-id-mode = <0>; /** 0: hardware, 1: sw_host, 2: sw_slave*/ + usb-fifo = <728>; + cpu-type = "gxl"; + controller-type = <3>; /** 0: normal,1:host,2:device,3:otg*/ + phy-reg = <0xd0078000>; + phy-reg-size = <0xa0>; + clocks = <&clkc CLKID_USB_GENERAL + &clkc CLKID_USB1_TO_DDR + &clkc CLKID_USB1>; + clock-names = "usb_general", + "usb1", + "usb1_to_ddr"; + }; + + meson-amvideom { + compatible = "amlogic, amvideom"; + dev_name = "amvideom"; + status = "okay"; + interrupts = <0 3 1>; + interrupt-names = "vsync"; + }; + + vout { + compatible = "amlogic, vout"; + dev_name = "vout"; + status = "okay"; + fr_auto_policy = <0>; + }; + + meson-fb { + compatible = "amlogic, meson-gxl"; + memory-region = <&fb_reserved>; + dev_name = "meson-fb"; + status = "okay"; + interrupts = <0 3 1 + 0 89 1>; + interrupt-names = "viu-vsync", "rdma"; + mem_size = <0x00800000 0x01800000 0x00100000>; + /* uboot logo,fb0/fb1 memory size,if afbcd fb0=0x01851000 */ + display_mode_default = "1080p60hz"; + scale_mode = <1>; + /** 0:VPU free scale 1:OSD free scale 2:OSD super scale */ + display_size_default = <1920 1080 1920 3240 32>; + /*1920*1080*4*3 = 0x17BB000*/ + mem_alloc = <1>; + logo_addr = "0x7dc00000"; + }; + + ge2d { + compatible = "amlogic, ge2d-gxl"; + dev_name = "ge2d"; + status = "okay"; + interrupts = <0 150 1>; + interrupt-names = "ge2d"; + clocks = <&clkc CLKID_VAPB_MUX>, + <&clkc CLKID_G2D>, + <&clkc CLKID_GE2D_GATE>; + clock-names = "clk_vapb_0", + "clk_ge2d", + "clk_ge2d_gate"; + }; + + /* AUDIO MESON DEVICES */ + i2s_dai: I2S { + #sound-dai-cells = <0>; + compatible = "amlogic, aml-i2s-dai"; + clocks = + <&clkc CLKID_MPLL2>, + <&clkc CLKID_AMCLK_COMP>, + <&clkc CLKID_AIU_GLUE>, + <&clkc CLKID_IEC958>, + <&clkc CLKID_I2S_OUT>, + <&clkc CLKID_AMCLK>, + <&clkc CLKID_AIFIFO2>, + <&clkc CLKID_MIXER>, + <&clkc CLKID_MIXER_IFACE>, + <&clkc CLKID_ADC>, + <&clkc CLKID_AIU_TOP>, + <&clkc CLKID_AOCLK_GATE>, + <&clkc CLKID_I2S_SPDIF>; + clock-names = + "mpll", + "mclk", + "top_glue", + "aud_buf", + "i2s_out", + "amclk_measure", + "aififo2", + "aud_mixer", + "mixer_reg", + "adc", + "top_level", + "aoclk", + "aud_in"; + i2s_pos_sync = <1>; + /*DMIC;*/ /* I2s Mic or Dmic, default for I2S mic */ + }; + dmic:snd_dmic { + #sound-dai-cells = <0>; + compatible = "aml, aml_snd_dmic"; + reg = <0xd0042000 0x2000>; + status = "okay"; + resets = < + &clkc CLKID_PDM_GATE + >; + reset-names = "pdm"; + pinctrl-names = "audio_dmic"; + pinctrl-0 = <&aml_dmic_pins>; + clocks = <&clkc CLKID_PDM_COMP>, + <&clkc CLKID_AMCLK_COMP>; + clock-names = "pdm", "mclk"; + }; + spdif_dai: SPDIF { + #sound-dai-cells = <0>; + compatible = "amlogic, aml-spdif-dai"; + clocks = + <&clkc CLKID_MPLL1>, + <&clkc CLKID_I958_COMP>, + <&clkc CLKID_AMCLK_COMP>, + <&clkc CLKID_I958_COMP_SPDIF>, + <&clkc CLKID_CLK81>, + <&clkc CLKID_IEC958>, + <&clkc CLKID_IEC958_GATE>; + clock-names = + "mpll1", + "i958", + "mclk", + "spdif", + "clk_81", + "iec958", + "iec958_amclk"; + }; + pcm_dai: PCM { + #sound-dai-cells = <0>; + compatible = "amlogic, aml-pcm-dai"; + pinctrl-names = "audio_pcm"; + pinctrl-0 = <&audio_pcm_pins>; + clocks = + <&clkc CLKID_MPLL0>, + <&clkc CLKID_PCM_MCLK_COMP>, + <&clkc CLKID_PCM_SCLK_GATE>; + clock-names = + "mpll0", + "pcm_mclk", + "pcm_sclk"; + pcm_mode = <1>; /* 0=slave mode, 1=master mode */ + }; + i2s_plat: i2s_platform { + compatible = "amlogic, aml-i2s"; + interrupts = <0 29 1>; + }; + pcm_plat: pcm_platform { + compatible = "amlogic, aml-pcm"; + }; + spdif_codec: spdif_codec{ + #sound-dai-cells = <0>; + compatible = "amlogic, aml-spdif-codec"; + pinctrl-names = "audio_spdif"; + pinctrl-0 = <&audio_spdif_pins>; + }; + pcm_codec: pcm_codec{ + #sound-dai-cells = <0>; + compatible = "amlogic, pcm2BT-codec"; + }; + /* endof AUDIO MESON DEVICES */ + + /* AUDIO board specific */ + dummy_codec:dummy{ + #sound-dai-cells = <0>; + compatible = "amlogic, aml_dummy_codec"; + status = "okay"; + }; + amlogic_codec:t9015{ + #sound-dai-cells = <0>; + compatible = "amlogic, aml_codec_T9015"; + reg = <0xc8832000 0x14>; + status = "disable"; + }; + aml_sound_meson { + compatible = "aml, meson-snd-card"; + status = "okay"; + aml-sound-card,format = "i2s"; + aml_sound_card,name = "AML-MESONAUDIO"; + aml,audio-routing = + "Ext Spk","LOUTL", + "Ext Spk","LOUTR"; + + mute_gpio-gpios = <&gpio GPIOH_5 0>; + mute_inv; + hp_disable; + hp_paraments = <800 300 0 5 1>; + pinctrl-names = "audio_i2s"; + pinctrl-0 = <&audio_i2s_pins>; + cpu_list = <&cpudai0 &cpudai1 &cpudai2>; + codec_list = <&codec0 &codec1 &codec2>; + plat_list = <&i2s_plat &i2s_plat &pcm_plat>; + cpudai0: cpudai0 { + sound-dai = <&i2s_dai>; + }; + cpudai1: cpudai1 { + sound-dai = <&spdif_dai>; + }; + cpudai2: cpudai2 { + sound-dai = <&pcm_dai>; + }; + codec0: codec0 { + sound-dai = <&dummy_codec>; + }; + codec1: codec1 { + sound-dai = <&spdif_codec>; + }; + codec2: codec2 { + sound-dai = <&pcm_codec>; + }; + }; + /* END OF AUDIO board specific */ + rdma{ + compatible = "amlogic, meson, rdma"; + dev_name = "amlogic-rdma"; + status = "ok"; + interrupts = <0 89 1>; + interrupt-names = "rdma"; + }; + + partitions: partitions{ + parts = <11>; + part-0 = <&logo>; + part-1 = <&recovery>; + part-2 = <&rsv>; + part-3 = <&tee>; + part-4 = <&crypt>; + part-5 = <&misc>; + part-6 = <&instaboot>; + part-7 = <&boot>; + part-8 = <&system>; + part-9 = <&cache>; + part-10 = <&data>; + + logo:logo{ + pname = "logo"; + size = <0x0 0x2000000>; + mask = <1>; + }; + recovery:recovery{ + pname = "recovery"; + size = <0x0 0x2000000>; + mask = <1>; + }; + rsv:rsv{ + pname = "rsv"; + size = <0x0 0x800000>; + mask = <1>; + }; + tee:tee{ + pname = "tee"; + size = <0x0 0x800000>; + mask = <1>; + }; + crypt:crypt{ + pname = "crypt"; + size = <0x0 0x2000000>; + mask = <1>; + }; + misc:misc{ + pname = "misc"; + size = <0x0 0x2000000>; + mask = <1>; + }; + instaboot:instaboot{ + pname = "instaboot"; + size = <0x0 0x400000>; + mask = <1>; + }; + boot:boot + { + pname = "boot"; + size = <0x0 0x2000000>; + mask = <1>; + }; + system:system + { + pname = "system"; + size = <0x0 0x80000000>; + mask = <1>; + }; + cache:cache + { + pname = "cache"; + size = <0x0 0x20000000>; + mask = <2>; + }; + data:data + { + pname = "data"; + size = <0xffffffff 0xffffffff>; + mask = <4>; + }; + }; + + unifykey{ + compatible = "amlogic, unifykey"; + status = "ok"; + + unifykey-num = <15>; + unifykey-index-0 = <&keysn_0>; + unifykey-index-1 = <&keysn_1>; + unifykey-index-2 = <&keysn_2>; + unifykey-index-3 = <&keysn_3>; + unifykey-index-4 = <&keysn_4>; + unifykey-index-5 = <&keysn_5>; + unifykey-index-6 = <&keysn_6>; + unifykey-index-7 = <&keysn_7>; + unifykey-index-8 = <&keysn_8>; + unifykey-index-9 = <&keysn_9>; + unifykey-index-10= <&keysn_10>; + unifykey-index-11= <&keysn_11>; + unifykey-index-12= <&keysn_12>; + unifykey-index-13= <&keysn_13>; + unifykey-index-14= <&keysn_14>; + + keysn_0: key_0{ + key-name = "usid"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_1:key_1{ + key-name = "mac"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_2:key_2{ + key-name = "hdcp"; + key-device = "secure"; + key-type = "sha1"; + key-permit = "read","write","del"; + }; + keysn_3:key_3{ + key-name = "secure_boot_set"; + key-device = "efuse"; + key-permit = "write"; + }; + keysn_4:key_4{ + key-name = "mac_bt"; + key-device = "normal"; + key-permit = "read","write","del"; + key-type = "mac"; + }; + keysn_5:key_5{ + key-name = "mac_wifi"; + key-device = "normal"; + key-permit = "read","write","del"; + key-type = "mac"; + }; + keysn_6:key_6{ + key-name = "hdcp2_tx"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_7:key_7{ + key-name = "hdcp2_rx"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_8:key_8{ + key-name = "widevinekeybox"; + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_9:key_9{ + key-name = "deviceid"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_10:key_10{ + key-name = "hdcp22_fw_private"; + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_11:key_11{ + key-name = "PlayReadykeybox25"; + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_12:key_12{ + key-name = "prpubkeybox";// PlayReady + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_13:key_13{ + key-name = "prprivkeybox";// PlayReady + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_14:key_14{ + key-name = "attestationkeybox";// attestation key + key-device = "secure"; + key-permit = "read","write","del"; + }; + };//End unifykey +}; + +&efuse { + status = "ok"; +}; + +&pwm_ef { + status = "okay"; +}; + +&audio_i2s_pins { + mux { + groups = "i2s_am_clk", + "i2s_ao_clk_out", + "i2s_lr_clk_out", + "i2sout_ch01", + "i2sin_ch23", + "i2sin_ch45", + "i2sin_ch67"; + function = "i2s"; + }; +}; + +&i2c_AO { + status = "okay"; + pca9557:pca9557@0x1f{ + compatible = "nxp,pca9557"; + reg = <0x1f>; + status = "okay"; + }; +}; + diff --git a/arch/arm/boot/dts/amlogic/gxl_sei210_1g.dts b/arch/arm/boot/dts/amlogic/gxl_sei210_1g.dts new file mode 100644 index 000000000000..d3220d565d5c --- /dev/null +++ b/arch/arm/boot/dts/amlogic/gxl_sei210_1g.dts @@ -0,0 +1,1208 @@ +/* + * arch/arm/boot/dts/amlogic/gxl_p212_1g.dts + * + * Copyright (C) 2017 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +/dts-v1/; + +#include "mesongxl.dtsi" +#include "partition_mbox_normal_sei32bit.dtsi" +/ { + model = "Amlogic"; + amlogic-dt-id = "gxl_sei210_1g"; + compatible = "amlogic, Gxl"; + interrupt-parent = <&gic>; + #address-cells = <1>; + #size-cells = <1>; + + aliases { + serial0 = &uart_AO; + serial1 = &uart_A; + serial2 = &uart_B; + serial3 = &uart_C; + serial4 = &uart_AO_B; + }; + + ion_dev { + compatible = "amlogic, ion_dev"; + memory-region = <&ion_reserved>; + }; + + memory@00000000 { + device_type = "memory"; + linux,usable-memory = <0x0100000 0x3ff00000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + /* global autoconfigured region for contiguous allocations */ + secmon_reserved:linux,secmon { + compatible = "shared-dma-pool"; + reusable; + size = <0x400000>; + alignment = <0x400000>; + alloc-ranges = <0x05000000 0x400000>; + }; + secos_reserved:linux,secos { + status = "disable"; + compatible = "amlogic, aml_secos_memory"; + reg = <0x05300000 0x2000000>; + no-map; + }; + logo_reserved:linux,meson-fb { + compatible = "shared-dma-pool"; + reusable; + size = <0x800000>; + alignment = <0x400000>; + alloc-ranges = <0x3f800000 0x800000>; + }; + //don't put other dts in front of logo_reserved + + //di_reserved:linux,di { + // compatible = "amlogic, di-mem"; + /** 10x3133440=30M(0x1e) support 8bit **/ + // size = <0x1e00000>; + //no-map; + //}; + di_cma_reserved:linux,di_cma { + compatible = "shared-dma-pool"; + reusable; + /** 10x3133440=30M(0x1e) support 8bit **/ + size = <0x2000000>; + alignment = <0x400000>; + }; + ion_reserved:linux,ion-dev { + compatible = "shared-dma-pool"; + reusable; + size = <0x7C00000>; + alignment = <0x400000>; + alloc-ranges = <0x0 0x30000000>; + }; + + /* vdin0 CMA pool */ + //vdin0_cma_reserved:linux,vdin0_cma { + // compatible = "shared-dma-pool"; + // linux,phandle = <4>; + // reusable; + /* 1920x1080x2x4 =16+4 M */ + // size = <0x01400000>; + // alignment = <0x400000>; + //}; + /* vdin1 CMA pool */ + vdin1_cma_reserved:linux,vdin1_cma { + compatible = "shared-dma-pool"; + reusable; + /* 1920x1080x2x4 =16 M */ + size = <0x01000000>; + alignment = <0x400000>; + }; + /* POST PROCESS MANAGER */ + ppmgr_reserved:linux,ppmgr { + compatible = "shared-dma-pool"; + size = <0x0>; + }; + + codec_mm_cma:linux,codec_mm_cma { + compatible = "shared-dma-pool"; + reusable; + /* ion_codec_mm max can alloc size 80M*/ + size = <0xc000000>; + alignment = <0x400000>; + linux,contiguous-region; + }; + picdec_cma_reserved:linux,picdec { + compatible = "shared-dma-pool"; + reusable; + size = <0x0>; + alignment = <0x0>; + linux,contiguous-region; + }; + /* codec shared reserved */ + codec_mm_reserved:linux,codec_mm_reserved { + compatible = "amlogic, codec-mm-reserved"; + size = <0x0>; + alignment = <0x100000>; + //no-map; + }; + }; + + bt-dev{ + compatible = "amlogic, bt-dev"; + dev_name = "bt-dev"; + status = "okay"; + gpio_reset = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>; + }; + + wifi{ + compatible = "amlogic, aml_wifi"; + dev_name = "aml_wifi"; + status = "okay"; + interrupt_pin = <&gpio GPIOX_7 GPIO_ACTIVE_HIGH>; + irq_trigger_type = "GPIO_IRQ_LOW"; + dhd_static_buf; //dhd_static_buf support + power_on_pin = <&gpio GPIOX_6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_32k_pins>; + pwm_config = <&wifi_pwm_conf>; + }; + + wifi_pwm_conf:wifi_pwm_conf{ + pwm_channel1_conf { + pwms = <&pwm_ef MESON_PWM_0 30040 0>; + duty-cycle = <15020>; + times = <8>; + }; + pwm_channel2_conf { + pwms = <&pwm_ef MESON_PWM_2 30030 0>; + duty-cycle = <15015>; + times = <12>; + }; + }; + + sd_emmc_c: emmc@d0074000 { + status = "okay"; + compatible = "amlogic, meson-mmc-gxl"; + reg = <0xd0074000 0x2000>; + interrupts = <0 218 1>; + pinctrl-names = "emmc_clk_cmd_pins", "emmc_all_pins"; + pinctrl-0 = <&emmc_clk_cmd_pins>; + pinctrl-1 = <&emmc_conf_pull_up &emmc_conf_pull_done>; + clocks = <&clkc CLKID_SD_EMMC_C>, + <&clkc CLKID_SD_EMMC_C_P0_COMP>, + <&clkc CLKID_FCLK_DIV2>; + clock-names = "core", "clkin0", "clkin1"; + + bus-width = <8>; + cap-sd-highspeed; + cap-mmc-highspeed; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + + max-frequency = <200000000>; + non-removable; + disable-wp; + emmc { + pinname = "emmc"; + ocr_avail = <0x200080>; /**VDD voltage 3.3 ~ 3.4 */ + caps = "MMC_CAP_8_BIT_DATA", + "MMC_CAP_MMC_HIGHSPEED", + "MMC_CAP_SD_HIGHSPEED", + "MMC_CAP_NONREMOVABLE", + "MMC_CAP_1_8V_DDR", + "MMC_CAP_HW_RESET", + "MMC_CAP_ERASE", + "MMC_CAP_CMD23"; + caps2 = "MMC_CAP2_HS200", "MMC_CAP2_HS400"; + f_min = <400000>; + f_max = <100000000>; + max_req_size = <0x20000>; /**128KB*/ + gpio_dat3 = <&gpio BOOT_3 GPIO_ACTIVE_HIGH>; + hw_reset = <&gpio BOOT_9 GPIO_ACTIVE_HIGH>; + card_type = <1>; + /* 1:mmc card(include eMMC), + * 2:sd card(include tSD) + */ + }; + }; + + sd_emmc_b:sd@d0072000 { + status = "okay"; + compatible = "amlogic, meson-mmc-gxl"; + reg = <0xd0072000 0x2000>; + interrupts = <0 217 1>; + pinctrl-names = "sd_all_pins", + "sd_clk_cmd_pins", + "sd_1bit_pins", + "sd_clk_cmd_uart_pins", + "sd_1bit_uart_pins", + "sd_to_ao_uart_pins", + "ao_to_sd_uart_pins", + "ao_to_sd_jtag_pins", + "sd_to_ao_jtag_pins"; + pinctrl-0 = <&sd_all_pins>; + pinctrl-1 = <&sd_clk_cmd_pins>; + pinctrl-2 = <&sd_1bit_pins>; + pinctrl-3 = <&sd_to_ao_uart_clr_pins + &sd_clk_cmd_pins &ao_to_sd_uart_pins>; + pinctrl-4 = <&sd_to_ao_uart_clr_pins + &sd_1bit_pins &ao_to_sd_uart_pins>; + pinctrl-5 = <&sd_all_pins &sd_to_ao_uart_pins>; + pinctrl-6 = <&sd_to_ao_uart_clr_pins &ao_to_sd_uart_pins>; + pinctrl-7 = <&sd_to_ao_uart_clr_pins &ao_to_sd_uart_pins>; + pinctrl-8 = <&sd_all_pins &sd_to_ao_uart_pins>; + clocks = <&clkc CLKID_SD_EMMC_B>, + <&clkc CLKID_SD_EMMC_B_P0_COMP>, + <&clkc CLKID_FCLK_DIV2>; + clock-names = "core", "clkin0", "clkin1"; + + bus-width = <4>; + cap-sd-highspeed; + max-frequency = <100000000>; + disable-wp; + sd { + pinname = "sd"; + ocr_avail = <0x200080>; /**VDD voltage 3.3 ~ 3.4 */ + caps = "MMC_CAP_4_BIT_DATA", + "MMC_CAP_MMC_HIGHSPEED", + "MMC_CAP_SD_HIGHSPEED"; + /* "MMC_CAP_UHS_SDR12", + * "MMC_CAP_UHS_SDR25", + * "MMC_CAP_UHS_SDR50", + * "MMC_CAP_UHS_SDR104"; + */ + f_min = <400000>; + f_max = <100000000>; + max_req_size = <0x20000>; /**128KB*/ + gpio_dat3 = <&gpio CARD_4 GPIO_ACTIVE_HIGH>; + jtag_pin = <&gpio CARD_0 GPIO_ACTIVE_HIGH>; + gpio_cd = <&gpio CARD_6 GPIO_ACTIVE_HIGH>; + card_type = <5>; + /* 0:unknown, + * 1:mmc card(include eMMC), + * 2:sd card(include tSD), + * 3:sdio device(ie:sdio-wifi), + * 4:SD combo (IO+mem) card, + * 5:NON sdio device(means sd/mmc card), + * other:reserved + */ + }; + }; + + sd_emmc_a:sdio@d0070000 { + status = "okay"; + compatible = "amlogic, meson-mmc-gxl"; + reg = <0xd0070000 0x2000>; + interrupts = <0 216 4>; + pinctrl-names = "sdio_clk_cmd_pins", "sdio_all_pins"; + pinctrl-0 = <&sdio_clk_cmd_pins>; + pinctrl-1 = <&sdio_all_pins>; + clocks = <&clkc CLKID_SD_EMMC_A>, + <&clkc CLKID_SD_EMMC_A_P0_COMP>, + <&clkc CLKID_FCLK_DIV2>; + clock-names = "core", "clkin0", "clkin1"; + + bus-width = <4>; + cap-sd-highspeed; + cap-mmc-highspeed; + max-frequency = <100000000>; + non-removable; + disable-wp; + sdio { + pinname = "sdio"; + ocr_avail = <0x200080>; /**VDD voltage 3.3 ~ 3.4 */ + caps = "MMC_CAP_4_BIT_DATA", + "MMC_CAP_MMC_HIGHSPEED", + "MMC_CAP_SD_HIGHSPEED", + "MMC_CAP_NONREMOVABLE", + "MMC_CAP_UHS_SDR12", + "MMC_CAP_UHS_SDR25", + "MMC_CAP_UHS_SDR50", + "MMC_CAP_UHS_SDR104", + "MMC_PM_KEEP_POWER", + "MMC_CAP_SDIO_IRQ"; + f_min = <400000>; + f_max = <200000000>; + max_req_size = <0x20000>; /**128KB*/ + card_type = <3>; + /* 3:sdio device(ie:sdio-wifi), + * 4:SD combo (IO+mem) card + */ + }; + }; + mtd_nand{ + compatible = "amlogic, aml_mtd_nand"; + dev_name = "mtdnand"; + status = "disabled"; + reg = <0xd0074800 0x200>; + interrupts = < 0 34 1 >; + pinctrl-names = "nand_rb_mod","nand_norb_mod", "nand_cs_only"; + pinctrl-0 = <&all_nand_pins>; + pinctrl-1 = <&all_nand_pins>; + pinctrl-2 = <&nand_cs_pins>; + device_id = <0>; + plat-names = "bootloader","nandnormal"; + plat-num = <2>; + plat-part-0 = <&bootloader>; + plat-part-1 = <&nandnormal>; + bootloader: bootloader{ + enable_pad ="ce0"; + busy_pad = "rb0"; + timming_mode = "mode5"; + bch_mode = "bch60_1k"; + t_rea = <20>; + t_rhoh = <15>; + chip_num = <1>; + part_num = <0>; + rb_detect = <1>; + }; + nandnormal: nandnormal{ + enable_pad ="ce0","ce1"; + busy_pad = "rb0","rb1"; + timming_mode = "mode5"; + bch_mode = "bch60_1k"; + plane_mode = "twoplane"; + t_rea = <20>; + t_rhoh = <15>; + chip_num = <2>; + part_num = <3>; + partition = <&nand_partitions>; + rb_detect = <1>; + }; + nand_partitions:nand_partition{ + logo{ + offset=<0x0 0x0>; + size=<0x0 0x200000>; + }; + recovery{ + offset=<0x0 0x0>; + size=<0x0 0x1000000>; + }; + boot{ + offset=<0x0 0x0>; + size=<0x0 0xC00000>; + }; + system{ + offset=<0x0 0x0>; + size=<0x0 0xDC40000>; + }; + data{ + offset=<0xffffffff 0xffffffff>; + size=<0x0 0x0>; + }; + }; + }; + + ethmac: ethernet@0xc9410000 { + compatible = "amlogic, gxbb-eth-dwmac"; + reg = <0xc9410000 0x10000 + 0xc8834540 0x8 + 0xc8834558 0xc>; + interrupts = <0 8 1>; + pinctrl-names = "external_eth_pins"; + pinctrl-0 = <&external_eth_pins>; + rst_pin-gpios = <&gpio GPIOZ_14 0>; + GPIOZ4_pin-gpios = <&gpio GPIOZ_4 0>; + GPIOZ5_pin-gpios = <&gpio GPIOZ_5 0>; + mc_val_internal_phy = <0x1800>; + mc_val_external_phy = <0x1621>; + cali_val = <0x20000>; + interrupt-names = "macirq"; + clocks = <&clkc CLKID_ETH>; + clock-names = "ethclk81"; + internal_phy=<1>; + }; + + aml_sensor0: aml-sensor@0 { + compatible = "amlogic, aml-thermal"; + device_name = "thermal"; + #thermal-sensor-cells = <1>; + cooling_devices { + cpufreq_cool_cluster0 { + min_state = <1000000>; + dyn_coeff = <140>; + cluster_id = <0>; + node_name = "cpufreq_cool0"; + device_type = "cpufreq"; + }; + cpucore_cool_cluster0 { + min_state = <1>; + dyn_coeff = <0>; + cluster_id = <0>; + node_name = "cpucore_cool0"; + device_type = "cpucore"; + }; + gpufreq_cool { + min_state = <400>; + dyn_coeff = <437>; + cluster_id = <0>; + node_name = "gpufreq_cool0"; + device_type = "gpufreq"; + }; + gpucore_cool { + min_state = <1>; + dyn_coeff = <0>; + cluster_id = <0>; + node_name = "gpucore_cool0"; + device_type = "gpucore"; + }; + }; + cpufreq_cool0:cpufreq_cool0 { + #cooling-cells = <2>; /* min followed by max */ + }; + cpucore_cool0:cpucore_cool0 { + #cooling-cells = <2>; /* min followed by max */ + }; + gpufreq_cool0:gpufreq_cool0 { + #cooling-cells = <2>; /* min followed by max */ + }; + gpucore_cool0:gpucore_cool0 { + #cooling-cells = <2>; /* min followed by max */ + }; + }; + thermal-zones { + soc_thermal { + polling-delay = <1000>; + polling-delay-passive = <100>; + sustainable-power = <2150>; + + thermal-sensors = <&aml_sensor0 3>; + + trips { + switch_on: trip-point@0 { + temperature = <70000>; + hysteresis = <1000>; + type = "passive"; + }; + control: trip-point@1 { + temperature = <80000>; + hysteresis = <1000>; + type = "passive"; + }; + hot: trip-point@2 { + temperature = <85000>; + hysteresis = <5000>; + type = "hot"; + }; + critical: trip-point@3 { + temperature = <260000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + + cooling-maps { + cpufreq_cooling_map { + trip = <&control>; + cooling-device = <&cpufreq_cool0 0 4>; + contribution = <1024>; + }; + cpucore_cooling_map { + trip = <&control>; + cooling-device = <&cpucore_cool0 0 3>; + contribution = <1024>; + }; + gpufreq_cooling_map { + trip = <&control>; + cooling-device = <&gpufreq_cool0 0 4>; + contribution = <1024>; + }; + gpucore_cooling_map { + trip = <&control>; + cooling-device = <&gpucore_cool0 0 2>; + contribution = <1024>; + }; + }; + }; + }; + + dwc3: dwc3@c9000000 { + compatible = "synopsys, dwc3"; + reg = <0xc9000000 0x100000>; + interrupts = <0 30 4>; + usb-phy = <&usb2_phy>, <&usb3_phy>; + cpu-type = "gxl"; + clock-src = "usb3.0"; + }; + + usb2_phy: usb2phy@d0078000 { + compatible = "amlogic, amlogic-new-usb2"; + portnum = <3>; + reg = <0xd0078000 0x80 + 0xc1104408 0x4>; + }; + + usb3_phy: usb3phy@d0078080 { + compatible = "amlogic, amlogic-new-usb3"; + portnum = <0>; + reg = <0xd0078080 0x20>; + }; + + dwc2_a { + compatible = "amlogic, dwc2"; + device_name = "dwc2_a"; + reg = <0xc9100000 0x40000>; + status = "okay"; + interrupts = <0 31 4>; + pl-periph-id = <0>; /** lm name */ + clock-src = "usb0"; /** clock src */ + port-id = <0>; /** ref to mach/usb.h */ + port-type = <2>; /** 0: otg, 1: host, 2: slave */ + port-speed = <0>; /** 0: default, high, 1: full */ + port-config = <0>; /** 0: default */ + port-dma = <0>; /** 0: default ... 6: disable*/ + port-id-mode = <0>; /** 0: hardware, 1: sw_host, 2: sw_slave*/ + usb-fifo = <728>; + cpu-type = "gxl"; + controller-type = <1>; /** 0: normal, 1: host, 2: device*/ + phy-reg = <0xd0078000>; + phy-reg-size = <0xa0>; + clocks = <&clkc CLKID_USB_GENERAL + &clkc CLKID_USB1_TO_DDR + &clkc CLKID_USB1>; + clock-names = "usb_general", + "usb1", + "usb1_to_ddr"; + }; + + meson-amvideom { + compatible = "amlogic, amvideom"; + dev_name = "amvideom"; + status = "okay"; + interrupts = <0 3 1>; + interrupt-names = "vsync"; + }; + + vout { + compatible = "amlogic, vout"; + dev_name = "vout"; + status = "okay"; + fr_auto_policy = <0>; + }; + + cvbsout { + compatible = "amlogic, cvbsout-gxl"; + dev_name = "cvbsout"; + status = "okay"; + clocks = <&clkc CLKID_VCLK2_ENCI + &clkc CLKID_VCLK2_VENCI0 + &clkc CLKID_VCLK2_VENCI1 + &clkc CLKID_DAC_CLK>; + clock-names = "venci_top_gate", + "venci_0_gate", + "venci_1_gate", + "vdac_clk_gate"; + + /* performance: reg_address, reg_value */ + /* s905x */ + performance = <0x1bf0 0x9 + 0x1b56 0x343 + 0x1b12 0x8080 + 0x1b05 0xfd + 0x1c59 0xf752 + 0xffff 0x0>; /* ending flag */ + }; + + amhdmitx: amhdmitx{ + compatible = "amlogic, amhdmitx"; + dev_name = "amhdmitx"; + status = "okay"; + vend-data = <&vend_data>; + pinctrl-names="hdmitx_hpd", "hdmitx_ddc"; + pinctrl-0=<&hdmitx_hpd>; + pinctrl-1=<&hdmitx_ddc>; + /* HPD, 57 + 32 = 89; CEC, 151 + 32 = 183*/ + interrupts = <0 57 1>; + interrupt-names = "hdmitx_hpd"; + /* 0:M8B 1:GXBB 2:GXTVBB 3:GXL 4:GXM + * 5:TXL 6:TXLX 7:AXG 8:GXLX 9:TXHD + */ + ic_type = <3>; + vend_data: vend_data{ /* Should modified by Customer */ + vendor_name = "Amlogic"; /* Max Chars: 8 */ + /* standards.ieee.org/develop/regauth/oui/oui.txt */ + vendor_id = <0x000000>; + product_desc = "MBox Meson Ref"; /* Max Chars: 16 */ + }; + }; + + aocec: aocec{ + compatible = "amlogic, amlogic-aocec"; + device_name = "aocec"; + status = "okay"; + vendor_id = <0x000000>; + cec_osd_string = "MBox"; /* Max Chars: 14 */ + cec_version = <5>; /* 5: 1.4, 6: 2.0 */ + port_num = <1>; + arc_port_mask = <0x0>; + interrupts = <0 199 1>; + interrupt-names = "hdmi_aocec"; + pinctrl-names = "default"; + pinctrl-0=<&hdmitx_aocec>; + reg = <0xc810023c 0x4 + 0xc8100000 0x200>; + reg-names = "ao_exit","ao"; + }; + + sysled { + compatible = "amlogic, sysled"; + dev_name = "sysled"; + status = "disabled"; + led_gpio = <&gpio GPIODV_24 GPIO_ACTIVE_HIGH>; + led_active_low = <1>; + }; + + codec_io { + compatible = "amlogic, codec_io"; + #address-cells=<1>; + #size-cells=<1>; + ranges; + io_cbus_base{ + reg = <0xC1100000 0x100000>; + }; + io_dos_base{ + reg = <0xc8820000 0x10000>; + }; + io_hiubus_base{ + reg = <0xc883c000 0x2000>; + }; + io_aobus_base{ + reg = <0xc8100000 0x100000>; + }; + io_vcbus_base{ + reg = <0xd0100000 0x40000>; + }; + io_dmc_base{ + reg = <0xc8838000 0x400>; + }; + }; + + codec_mm { + compatible = "amlogic, codec, mm"; + memory-region = <&codec_mm_cma &codec_mm_reserved>; + dev_name = "codec_mm"; + status = "okay"; + }; + + canvas{ + compatible = "amlogic, meson, canvas"; + dev_name = "amlogic-canvas"; + status = "ok"; + reg = <0xc8838000 0x400>; + }; + + mesonstream { + compatible = "amlogic, codec, streambuf"; + dev_name = "mesonstream"; + status = "okay"; + clocks = <&clkc CLKID_DOS_PARSER + &clkc CLKID_DEMUX + &clkc CLKID_DOS + &clkc CLKID_VDEC_MUX + &clkc CLKID_HCODEC_MUX + &clkc CLKID_HEVC_MUX>; + clock-names = "parser_top", + "demux", + "vdec", + "clk_vdec_mux", + "clk_hcodec_mux", + "clk_hevc_mux"; + }; + + vdec { + compatible = "amlogic, vdec"; + dev_name = "vdec.0"; + status = "okay"; + interrupts = <0 3 1 + 0 23 1 + 0 32 1 + 0 43 1 + 0 44 1 + 0 45 1>; + interrupt-names = "vsync", + "demux", + "parser", + "mailbox_0", + "mailbox_1", + "mailbox_2"; + }; + + gpio_keypad{ + compatible = "amlogic, gpio_keypad"; + status = "okay"; + scan_period = <20>; + key_num = <1>; + key_name = "power"; + key_code = <116>; + key-gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_HIGH>; + detect_mode = <0>;/*0:polling mode, 1:irq mode*/ + }; + meson-fb { + compatible = "amlogic, meson-gxl"; + memory-region = <&logo_reserved>; + dev_name = "meson-fb"; + status = "okay"; + interrupts = <0 3 1 + 0 89 1>; + interrupt-names = "viu-vsync", "rdma"; + mem_size = <0x00800000 0x01800000 0x00100000>; + /* uboot logo,fb0/fb1 memory size,if afbcd fb0=0x01851000*/ + display_mode_default = "1080p60hz"; + scale_mode = <1>; + /** 0:VPU free scale 1:OSD free scale 2:OSD super scale */ + display_size_default = <1920 1080 1920 3240 32>; + /*1920*1080*4*3 = 0x17BB000*/ + logo_addr = "0x3f800000"; + }; + ge2d { + compatible = "amlogic, ge2d"; + dev_name = "ge2d"; + status = "okay"; + interrupts = <0 150 1>; + interrupt-names = "ge2d"; + clocks = <&clkc CLKID_VAPB_MUX>, + <&clkc CLKID_G2D>, + <&clkc CLKID_GE2D_GATE>; + clock-names = "clk_vapb_0", + "clk_ge2d", + "clk_ge2d_gate"; + }; + + + /* AUDIO MESON DEVICES */ + i2s_dai: I2S { + #sound-dai-cells = <0>; + compatible = "amlogic, aml-i2s-dai"; + clocks = + <&clkc CLKID_MPLL2>, + <&clkc CLKID_AMCLK_COMP>, + <&clkc CLKID_AIU_GLUE>, + <&clkc CLKID_IEC958>, + <&clkc CLKID_I2S_OUT>, + <&clkc CLKID_AMCLK>, + <&clkc CLKID_AIFIFO2>, + <&clkc CLKID_MIXER>, + <&clkc CLKID_MIXER_IFACE>, + <&clkc CLKID_ADC>, + <&clkc CLKID_AIU_TOP>, + <&clkc CLKID_AOCLK_GATE>, + <&clkc CLKID_I2S_SPDIF>; + clock-names = + "mpll", + "mclk", + "top_glue", + "aud_buf", + "i2s_out", + "amclk_measure", + "aififo2", + "aud_mixer", + "mixer_reg", + "adc", + "top_level", + "aoclk", + "aud_in"; + i2s_pos_sync = <0>; + /*DMIC;*/ /* I2s Mic or Dmic, default for I2S mic */ + }; + dmic:snd_dmic { + #sound-dai-cells = <0>; + compatible = "aml, aml_snd_dmic"; + reg = <0xd0042000 0x2000>; + status = "disabled"; + resets = < + &clkc CLKID_PDM_GATE + >; + reset-names = "pdm"; + pinctrl-names = "audio_dmic"; + pinctrl-0 = <&aml_dmic_pins>; + clocks = <&clkc CLKID_PDM_COMP>, + <&clkc CLKID_AMCLK_COMP>; + clock-names = "pdm", "mclk"; + }; + spdif_dai: SPDIF { + #sound-dai-cells = <0>; + compatible = "amlogic, aml-spdif-dai"; + clocks = + <&clkc CLKID_MPLL1>, + <&clkc CLKID_I958_COMP>, + <&clkc CLKID_AMCLK_COMP>, + <&clkc CLKID_I958_COMP_SPDIF>, + <&clkc CLKID_CLK81>, + <&clkc CLKID_IEC958>, + <&clkc CLKID_IEC958_GATE>; + clock-names = + "mpll1", + "i958", + "mclk", + "spdif", + "clk_81", + "iec958", + "iec958_amclk"; + }; + pcm_dai: PCM { + #sound-dai-cells = <0>; + compatible = "amlogic, aml-pcm-dai"; + pinctrl-names = "audio_pcm"; + pinctrl-0 = <&audio_pcm_pins>; + clocks = + <&clkc CLKID_MPLL0>, + <&clkc CLKID_PCM_MCLK_COMP>, + <&clkc CLKID_PCM_SCLK_GATE>; + clock-names = + "mpll0", + "pcm_mclk", + "pcm_sclk"; + pcm_mode = <1>; /* 0=slave mode, 1=master mode */ + }; + i2s_plat: i2s_platform { + compatible = "amlogic, aml-i2s"; + interrupts = <0 29 1>; + }; + pcm_plat: pcm_platform { + compatible = "amlogic, aml-pcm"; + }; + spdif_codec: spdif_codec{ + #sound-dai-cells = <0>; + compatible = "amlogic, aml-spdif-codec"; + pinctrl-names = "audio_spdif"; + pinctrl-0 = <&audio_spdif_pins>; + }; + pcm_codec: pcm_codec{ + #sound-dai-cells = <0>; + compatible = "amlogic, pcm2BT-codec"; + }; + /* endof AUDIO MESON DEVICES */ + + /* AUDIO board specific */ + dummy_codec:dummy{ + #sound-dai-cells = <0>; + compatible = "amlogic, aml_dummy_codec"; + status = "disable"; + }; + amlogic_codec:t9015{ + #sound-dai-cells = <0>; + compatible = "amlogic, aml_codec_T9015"; + reg = <0xc8832000 0x14>; + status = "okay"; + }; + aml_sound_meson { + compatible = "aml, meson-snd-card"; + status = "okay"; + aml-sound-card,format = "i2s"; + aml_sound_card,name = "AML-MESONAUDIO"; + aml,audio-routing = + "Ext Spk","LOUTL", + "Ext Spk","LOUTR"; + + mute_gpio-gpios = <&gpio GPIOH_5 0>; + mute_inv; + hp_disable; + hp_paraments = <800 300 0 5 1>; + pinctrl-names = "audio_i2s"; + pinctrl-0 = <&audio_i2s_pins>; + cpu_list = <&cpudai0 &cpudai1 &cpudai2>; + codec_list = <&codec0 &codec1 &codec2>; + plat_list = <&i2s_plat &i2s_plat &pcm_plat>; + cpudai0: cpudai0 { + sound-dai = <&i2s_dai>; + }; + cpudai1: cpudai1 { + sound-dai = <&spdif_dai>; + }; + cpudai2: cpudai2 { + sound-dai = <&pcm_dai>; + }; + codec0: codec0 { + sound-dai = <&amlogic_codec>; + }; + codec1: codec1 { + sound-dai = <&spdif_codec>; + }; + codec2: codec2 { + sound-dai = <&pcm_codec>; + }; + }; + /* END OF AUDIO board specific */ + rdma{ + compatible = "amlogic, meson, rdma"; + dev_name = "amlogic-rdma"; + status = "ok"; + interrupts = <0 89 1>; + interrupt-names = "rdma"; + }; + + amvenc_avc{ + compatible = "amlogic, amvenc_avc"; + dev_name = "amvenc_avc"; + status = "okay"; + interrupts = <0 45 1>; + interrupt-names = "mailbox_2"; + }; + + hevc_enc{ + compatible = "cnm, HevcEnc"; + dev_name = "HevcEnc"; + status = "okay"; + interrupts = <0 187 1>; + interrupt-names = "wave420l_irq"; + #address-cells=<1>; + #size-cells=<1>; + ranges; + io_reg_base{ + reg = <0xc8810000 0x4000>; + }; + }; + + picdec { + compatible = "amlogic, picdec"; + memory-region = <&picdec_cma_reserved>; + dev_name = "picdec"; + status = "okay"; + }; + + ppmgr { + compatible = "amlogic, ppmgr"; + memory-region = <&ppmgr_reserved>; + dev_name = "ppmgr"; + status = "okay"; + }; + + deinterlace { + compatible = "amlogic, deinterlace"; + status = "okay"; + flag_cma = <1>;/*0:use reserved;1:use cma*/ + //memory-region = <&di_reserved>; + memory-region = <&di_cma_reserved>; + interrupts = <0 46 1 0 6 1>; + interrupt-names = "de_irq", "timerc"; + /* + * nr_size(byte) = 1920*544*2(yuv422 8bit) | + * 1920*544*2*12/8(yuv422 10bit) + * | 1920*544*2*10/8(yuv422 10bit full pack mode) + */ + /* mtn_size(byte) = 1920*544/2 */ + /* count_size(byte) = 1920*544/2 */ + buffer-size = <3133440>; + hw-version = <2>; + }; + + ionvideo { + compatible = "amlogic, ionvideo"; + dev_name = "ionvideo"; + status = "okay"; + }; + + amlvideo { + compatible = "amlogic, amlvideo"; + dev_name = "amlvideo"; + status = "okay"; + }; + + amlvideo2_0 { + compatible = "amlogic, amlvideo2"; + dev_name = "amlvideo2"; + status = "okay"; + amlvideo2_id = <0>; + cma_mode = <1>; + }; + + amlvideo2_1 { + compatible = "amlogic, amlvideo2"; + dev_name = "amlvideo2"; + status = "okay"; + amlvideo2_id = <1>; + cma_mode = <1>; + }; + + /*if you want to use vdin just modify status to "ok"*/ + vdin0 { + compatible = "amlogic, vdin"; + /*memory-region = <&vdin0_cma_reserved>;*/ + dev_name = "vdin0"; + status = "ok"; + reserve-iomap = "true"; + flag_cma = <1>;/*1:share with codec_mm;2:cma alone*/ + /*MByte, if 10bit disable: 64M(YUV422), + *if 10bit enable: 64*1.5 = 96M(YUV422) + *if support 4K2K-YUV444-10bit-WR:3840*2160*4*4 ~= 128M + *if support 4K2K-YUV422-10bit-wr:3840*2160*3*4 ~= 96M + *if support 4K2K-YUV422-8BIT-WR:3840*2160*2*4 ~= 64M + *if support 1080p-YUV422-8BIT-WR:1920*1080*2*4 ~= 16M + */ + cma_size = <16>; + interrupts = <0 83 1>; + rdma-irq = <2>; + /*clocks = <&clock CLK_FPLL_DIV5>, + * <&clock CLK_VDIN_MEAS_CLK>; + *clock-names = "fclk_div5", "cts_vdin_meas_clk"; + */ + vdin_id = <0>; + /*vdin write mem color depth support: + *bit0:support 8bit + *bit1:support 9bit + *bit2:support 10bit + *bit3:support 12bit + *bit4:support yuv422 10bit full pack mode (from txl new add) + */ + tv_bit_mode = <1>; + }; + vdin1 { + compatible = "amlogic, vdin"; + memory-region = <&vdin1_cma_reserved>; + dev_name = "vdin1"; + status = "ok"; + reserve-iomap = "true"; + flag_cma = <0>;/*1:share with codec_mm;0:cma alone*/ + interrupts = <0 85 1>; + rdma-irq = <4>; + /*clocks = <&clock CLK_FPLL_DIV5>, + * <&clock CLK_VDIN_MEAS_CLK>; + *clock-names = "fclk_div5", "cts_vdin_meas_clk"; + */ + vdin_id = <1>; + /*vdin write mem color depth support: + *bit0:support 8bit + *bit1:support 9bit + *bit2:support 10bit + *bit3:support 12bit + */ + tv_bit_mode = <1>; + }; + + amlvecm { + compatible = "amlogic, vecm"; + dev_name = "aml_vecm"; + status = "okay"; + gamma_en = <0>;/*1:enabel ;0:disable*/ + wb_en = <0>;/*1:enabel ;0:disable*/ + cm_en = <0>;/*1:enabel ;0:disable*/ + }; + + unifykey{ + compatible = "amlogic, unifykey"; + status = "ok"; + + unifykey-num = <16>; + unifykey-index-0 = <&keysn_0>; + unifykey-index-1 = <&keysn_1>; + unifykey-index-2 = <&keysn_2>; + unifykey-index-3 = <&keysn_3>; + unifykey-index-4 = <&keysn_4>; + unifykey-index-5 = <&keysn_5>; + unifykey-index-6 = <&keysn_6>; + unifykey-index-7 = <&keysn_7>; + unifykey-index-8 = <&keysn_8>; + unifykey-index-9 = <&keysn_9>; + unifykey-index-10= <&keysn_10>; + unifykey-index-11= <&keysn_11>; + unifykey-index-12= <&keysn_12>; + unifykey-index-13= <&keysn_13>; + unifykey-index-14= <&keysn_14>; + unifykey-index-15= <&keysn_15>; + + keysn_0: key_0{ + key-name = "usid"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_1:key_1{ + key-name = "mac"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_2:key_2{ + key-name = "hdcp"; + key-device = "secure"; + key-type = "sha1"; + key-permit = "read","write","del"; + }; + keysn_3:key_3{ + key-name = "secure_boot_set"; + key-device = "efuse"; + key-permit = "write"; + }; + keysn_4:key_4{ + key-name = "mac_bt"; + key-device = "normal"; + key-permit = "read","write","del"; + key-type = "mac"; + }; + keysn_5:key_5{ + key-name = "mac_wifi"; + key-device = "normal"; + key-permit = "read","write","del"; + key-type = "mac"; + }; + keysn_6:key_6{ + key-name = "hdcp2_tx"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_7:key_7{ + key-name = "hdcp2_rx"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_8:key_8{ + key-name = "widevinekeybox"; + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_9:key_9{ + key-name = "deviceid"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_10:key_10{ + key-name = "hdcp22_fw_private"; + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_11:key_11{ + key-name = "PlayReadykeybox25"; + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_12:key_12{ + key-name = "prpubkeybox";// PlayReady + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_13:key_13{ + key-name = "prprivkeybox";// PlayReady + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_14:key_14{ + key-name = "attestationkeybox";// attestation key + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_15: key_15{ + key-name = "region_code"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + };//End unifykey + +}; +&efuse { + status = "ok"; +}; + +&pwm_ef { + status = "okay"; +}; + +&audio_data{ + status = "okay"; +}; +&spicc{ + status = "disabled"; + pinctrl-names = "spicc_pulldown","spicc_pullup"; + pinctrl-0 = <&spicc_pulldown_x8x9x11>; + pinctrl-1 = <&spicc_pullup_x8x9x11>; + num_chipselect = <1>; + cs-gpios = <&gpio GPIOX_10 GPIO_ACTIVE_HIGH>; + dma_en = <0>; + dma_tx_threshold = <3>; + dma_rx_threshold = <3>; + dma_num_per_read_burst = <3>; + dma_num_per_write_burst = <3>; + delay_control = <0x15>; + ssctl = <0>; +}; + diff --git a/arch/arm/boot/dts/amlogic/gxl_sei210_2g.dts b/arch/arm/boot/dts/amlogic/gxl_sei210_2g.dts new file mode 100644 index 000000000000..8f36cb84457e --- /dev/null +++ b/arch/arm/boot/dts/amlogic/gxl_sei210_2g.dts @@ -0,0 +1,1202 @@ +/* + * arch/arm/boot/dts/amlogic/gxl_sei210_2g.dts + * + * Copyright (C) 2017 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +/dts-v1/; + +#include +#include "partition_mbox_normal_sei32bit.dtsi" +#include "mesongxl_sei210.dtsi" +/ { + model = "Amlogic"; + amlogic-dt-id = "gxl_sei210_2g"; + compatible = "amlogic, Gxl"; + interrupt-parent = <&gic>; + #address-cells = <1>; + #size-cells = <1>; + + aliases { + serial0 = &uart_AO; + serial1 = &uart_A; + serial2 = &uart_B; + serial3 = &uart_C; + serial4 = &uart_AO_B; + }; + + ion_dev { + compatible = "amlogic, ion_dev"; + memory-region = <&ion_reserved>; + }; + + memory@00000000 { + device_type = "memory"; + linux,usable-memory = <0x0100000 0x7ff00000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + /* global autoconfigured region for contiguous allocations */ + ramoops@0x07400000 { + compatible = "ramoops"; + reg = <0x07400000 0x00100000>; + record-size = <0x8000>; + console-size = <0x8000>; + ftrace-size = <0x0>; + pmsg-size = <0x8000>; + }; + secmon_reserved:linux,secmon { + compatible = "shared-dma-pool"; + reusable; + size = <0x400000>; + alignment = <0x400000>; + alloc-ranges = <0x05000000 0x400000>; + }; + secos_reserved:linux,secos { + status = "disable"; + compatible = "amlogic, aml_secos_memory"; + reg = <0x05300000 0x2000000>; + no-map; + }; + logo_reserved:linux,meson-fb { + compatible = "shared-dma-pool"; + reusable; + size = <0x800000>; + alignment = <0x400000>; + alloc-ranges = <0x7f800000 0x800000>; + }; + //don't put other dts in front of logo_reserved + + //di_reserved:linux,di { + // compatible = "amlogic, di-mem"; + /** 10x3133440=30M(0x1e) support 8bit **/ + // size = <0x1e00000>; + //no-map; + //}; + di_cma_reserved:linux,di_cma { + compatible = "shared-dma-pool"; + reusable; + /** 10x3133440=30M(0x1e) support 8bit **/ + size = <0x2000000>; + alignment = <0x400000>; + }; + ion_reserved:linux,ion-dev { + compatible = "shared-dma-pool"; + reusable; + size = <0x7C00000>; + alignment = <0x400000>; + }; + + /* vdin0 CMA pool */ + //vdin0_cma_reserved:linux,vdin0_cma { + // compatible = "shared-dma-pool"; + // linux,phandle = <4>; + // reusable; + /* 1920x1080x2x4 =16+4 M */ + // size = <0x01400000>; + // alignment = <0x400000>; + //}; + /* vdin1 CMA pool */ + vdin1_cma_reserved:linux,vdin1_cma { + compatible = "shared-dma-pool"; + reusable; + /* 1920x1080x2x4 =16 M */ + size = <0x01000000>; + alignment = <0x400000>; + }; + /* POST PROCESS MANAGER */ + ppmgr_reserved:linux,ppmgr { + compatible = "shared-dma-pool"; + size = <0x0>; + }; + + codec_mm_cma:linux,codec_mm_cma { + compatible = "shared-dma-pool"; + reusable; + /* ion_codec_mm max can alloc size 80M*/ + size = <0x13400000>; + alignment = <0x400000>; + linux,contiguous-region; + }; + picdec_cma_reserved:linux,picdec { + compatible = "shared-dma-pool"; + reusable; + size = <0x0>; + alignment = <0x0>; + linux,contiguous-region; + }; + /* codec shared reserved */ + codec_mm_reserved:linux,codec_mm_reserved { + compatible = "amlogic, codec-mm-reserved"; + size = <0x0>; + alignment = <0x100000>; + //no-map; + }; + }; + + bt-dev{ + compatible = "amlogic, bt-dev"; + dev_name = "bt-dev"; + status = "okay"; + gpio_reset = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>; + }; + + wifi{ + compatible = "amlogic, aml_wifi"; + dev_name = "aml_wifi"; + status = "okay"; + interrupt_pin = <&gpio GPIOX_7 GPIO_ACTIVE_HIGH>; + irq_trigger_type = "GPIO_IRQ_LOW"; + dhd_static_buf; //dhd_static_buf support + power_on_pin = <&gpio GPIOX_6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_32k_pins>; + pwm_config = <&wifi_pwm_conf>; + }; + + wifi_pwm_conf:wifi_pwm_conf{ + pwm_channel1_conf { + pwms = <&pwm_ef MESON_PWM_0 30040 0>; + duty-cycle = <15020>; + times = <8>; + }; + pwm_channel2_conf { + pwms = <&pwm_ef MESON_PWM_2 30030 0>; + duty-cycle = <15015>; + times = <12>; + }; + }; + + sd_emmc_c: emmc@d0074000 { + status = "okay"; + compatible = "amlogic, meson-mmc-gxl"; + reg = <0xd0074000 0x2000>; + interrupts = <0 218 1>; + pinctrl-names = "emmc_clk_cmd_pins", "emmc_all_pins"; + pinctrl-0 = <&emmc_clk_cmd_pins>; + pinctrl-1 = <&emmc_conf_pull_up &emmc_conf_pull_done>; + clocks = <&clkc CLKID_SD_EMMC_C>, + <&clkc CLKID_SD_EMMC_C_P0_COMP>, + <&clkc CLKID_FCLK_DIV2>; + clock-names = "core", "clkin0", "clkin1"; + + bus-width = <8>; + cap-sd-highspeed; + cap-mmc-highspeed; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + + max-frequency = <200000000>; + non-removable; + disable-wp; + emmc { + pinname = "emmc"; + ocr_avail = <0x200080>; /**VDD voltage 3.3 ~ 3.4 */ + caps = "MMC_CAP_8_BIT_DATA", + "MMC_CAP_MMC_HIGHSPEED", + "MMC_CAP_SD_HIGHSPEED", + "MMC_CAP_NONREMOVABLE", + "MMC_CAP_1_8V_DDR", + "MMC_CAP_HW_RESET", + "MMC_CAP_ERASE", + "MMC_CAP_CMD23"; + caps2 = "MMC_CAP2_HS200"; + f_min = <400000>; + f_max = <100000000>; + max_req_size = <0x20000>; /**128KB*/ + gpio_dat3 = <&gpio BOOT_3 GPIO_ACTIVE_HIGH>; + hw_reset = <&gpio BOOT_9 GPIO_ACTIVE_HIGH>; + card_type = <1>; + /* 1:mmc card(include eMMC), + * 2:sd card(include tSD) + */ + }; + }; + + sd_emmc_b:sd@d0072000 { + status = "disabled"; + compatible = "amlogic, meson-mmc-gxl"; + reg = <0xd0072000 0x2000>; + interrupts = <0 217 1>; + pinctrl-names = "sd_all_pins", + "sd_clk_cmd_pins", + "sd_1bit_pins", + "sd_clk_cmd_uart_pins", + "sd_1bit_uart_pins", + "sd_to_ao_uart_pins", + "ao_to_sd_uart_pins", + "ao_to_sd_jtag_pins", + "sd_to_ao_jtag_pins"; + pinctrl-0 = <&sd_all_pins>; + pinctrl-1 = <&sd_clk_cmd_pins>; + pinctrl-2 = <&sd_1bit_pins>; + pinctrl-3 = <&sd_to_ao_uart_clr_pins + &sd_clk_cmd_pins &ao_to_sd_uart_pins>; + pinctrl-4 = <&sd_to_ao_uart_clr_pins + &sd_1bit_pins &ao_to_sd_uart_pins>; + pinctrl-5 = <&sd_all_pins &sd_to_ao_uart_pins>; + pinctrl-6 = <&sd_to_ao_uart_clr_pins &ao_to_sd_uart_pins>; + pinctrl-7 = <&sd_to_ao_uart_clr_pins &ao_to_sd_uart_pins>; + pinctrl-8 = <&sd_all_pins &sd_to_ao_uart_pins>; + clocks = <&clkc CLKID_SD_EMMC_B>, + <&clkc CLKID_SD_EMMC_B_P0_COMP>, + <&clkc CLKID_FCLK_DIV2>; + clock-names = "core", "clkin0", "clkin1"; + + bus-width = <4>; + cap-sd-highspeed; + max-frequency = <100000000>; + disable-wp; + sd { + pinname = "sd"; + ocr_avail = <0x200080>; /**VDD voltage 3.3 ~ 3.4 */ + caps = "MMC_CAP_4_BIT_DATA", + "MMC_CAP_MMC_HIGHSPEED", + "MMC_CAP_SD_HIGHSPEED"; + /* "MMC_CAP_UHS_SDR12", + * "MMC_CAP_UHS_SDR25", + * "MMC_CAP_UHS_SDR50", + * "MMC_CAP_UHS_SDR104"; + */ + f_min = <400000>; + f_max = <100000000>; + max_req_size = <0x20000>; /**128KB*/ + gpio_dat3 = <&gpio CARD_4 GPIO_ACTIVE_HIGH>; + jtag_pin = <&gpio CARD_0 GPIO_ACTIVE_HIGH>; + gpio_cd = <&gpio CARD_6 GPIO_ACTIVE_HIGH>; + card_type = <5>; + /* 0:unknown, + * 1:mmc card(include eMMC), + * 2:sd card(include tSD), + * 3:sdio device(ie:sdio-wifi), + * 4:SD combo (IO+mem) card, + * 5:NON sdio device(means sd/mmc card), + * other:reserved + */ + }; + }; + + sd_emmc_a:sdio@d0070000 { + status = "okay"; + compatible = "amlogic, meson-mmc-gxl"; + reg = <0xd0070000 0x2000>; + interrupts = <0 216 4>; + pinctrl-names = "sdio_clk_cmd_pins", "sdio_all_pins"; + pinctrl-0 = <&sdio_clk_cmd_pins>; + pinctrl-1 = <&sdio_all_pins>; + clocks = <&clkc CLKID_SD_EMMC_A>, + <&clkc CLKID_SD_EMMC_A_P0_COMP>, + <&clkc CLKID_FCLK_DIV2>; + clock-names = "core", "clkin0", "clkin1"; + + bus-width = <4>; + cap-sd-highspeed; + cap-mmc-highspeed; + max-frequency = <100000000>; + non-removable; + disable-wp; + sdio { + pinname = "sdio"; + ocr_avail = <0x200080>; /**VDD voltage 3.3 ~ 3.4 */ + caps = "MMC_CAP_4_BIT_DATA", + "MMC_CAP_MMC_HIGHSPEED", + "MMC_CAP_SD_HIGHSPEED", + "MMC_CAP_NONREMOVABLE", + "MMC_CAP_UHS_SDR12", + "MMC_CAP_UHS_SDR25", + "MMC_CAP_UHS_SDR50", + "MMC_CAP_UHS_SDR104", + "MMC_PM_KEEP_POWER", + "MMC_CAP_SDIO_IRQ"; + f_min = <400000>; + f_max = <180000000>; + max_req_size = <0x20000>; /**128KB*/ + card_type = <3>; + /* 3:sdio device(ie:sdio-wifi), + * 4:SD combo (IO+mem) card + */ + }; + }; + mtd_nand{ + compatible = "amlogic, aml_mtd_nand"; + dev_name = "mtdnand"; + status = "disabled"; + reg = <0xd0074800 0x200>; + interrupts = < 0 34 1 >; + pinctrl-names = "nand_rb_mod","nand_norb_mod", "nand_cs_only"; + pinctrl-0 = <&all_nand_pins>; + pinctrl-1 = <&all_nand_pins>; + pinctrl-2 = <&nand_cs_pins>; + device_id = <0>; + plat-names = "bootloader","nandnormal"; + plat-num = <2>; + plat-part-0 = <&bootloader>; + plat-part-1 = <&nandnormal>; + bootloader: bootloader{ + enable_pad ="ce0"; + busy_pad = "rb0"; + timming_mode = "mode5"; + bch_mode = "bch60_1k"; + t_rea = <20>; + t_rhoh = <15>; + chip_num = <1>; + part_num = <0>; + rb_detect = <1>; + }; + nandnormal: nandnormal{ + enable_pad ="ce0","ce1"; + busy_pad = "rb0","rb1"; + timming_mode = "mode5"; + bch_mode = "bch60_1k"; + plane_mode = "twoplane"; + t_rea = <20>; + t_rhoh = <15>; + chip_num = <2>; + part_num = <3>; + partition = <&nand_partitions>; + rb_detect = <1>; + }; + nand_partitions:nand_partition{ + logo{ + offset=<0x0 0x0>; + size=<0x0 0x200000>; + }; + recovery{ + offset=<0x0 0x0>; + size=<0x0 0x1000000>; + }; + boot{ + offset=<0x0 0x0>; + size=<0x0 0xC00000>; + }; + system{ + offset=<0x0 0x0>; + size=<0x0 0xDC40000>; + }; + data{ + offset=<0xffffffff 0xffffffff>; + size=<0x0 0x0>; + }; + }; + }; + + ethmac: ethernet@0xc9410000 { + status = "disabled"; + compatible = "amlogic, gxbb-eth-dwmac"; + reg = <0xc9410000 0x10000 + 0xc8834540 0x8 + 0xc8834558 0xc>; + interrupts = <0 8 1>; + pinctrl-names = "external_eth_pins"; + pinctrl-0 = <&external_eth_pins>; + rst_pin-gpios = <&gpio GPIOZ_14 0>; + GPIOZ4_pin-gpios = <&gpio GPIOZ_4 0>; + GPIOZ5_pin-gpios = <&gpio GPIOZ_5 0>; + mc_val_internal_phy = <0x1800>; + mc_val_external_phy = <0x1621>; + cali_val = <0x20000>; + interrupt-names = "macirq"; + clocks = <&clkc CLKID_ETH>; + clock-names = "ethclk81"; + internal_phy=<1>; + }; + + codec_io { + compatible = "amlogic, codec_io"; + #address-cells=<1>; + #size-cells=<1>; + ranges; + io_cbus_base{ + reg = <0xC1100000 0x100000>; + }; + io_dos_base{ + reg = <0xc8820000 0x10000>; + }; + io_hiubus_base{ + reg = <0xc883c000 0x2000>; + }; + io_aobus_base{ + reg = <0xc8100000 0x100000>; + }; + io_vcbus_base{ + reg = <0xd0100000 0x40000>; + }; + io_dmc_base{ + reg = <0xc8838000 0x400>; + }; + }; + + codec_mm { + compatible = "amlogic, codec, mm"; + memory-region = <&codec_mm_cma &codec_mm_reserved>; + dev_name = "codec_mm"; + status = "okay"; + }; + + canvas{ + compatible = "amlogic, meson, canvas"; + dev_name = "amlogic-canvas"; + status = "ok"; + reg = <0xc8838000 0x400>; + }; + + mesonstream { + compatible = "amlogic, codec, streambuf"; + dev_name = "mesonstream"; + status = "okay"; + clocks = <&clkc CLKID_DOS_PARSER + &clkc CLKID_DEMUX + &clkc CLKID_DOS + &clkc CLKID_VDEC_MUX + &clkc CLKID_HCODEC_MUX + &clkc CLKID_HEVC_MUX>; + clock-names = "parser_top", + "demux", + "vdec", + "clk_vdec_mux", + "clk_hcodec_mux", + "clk_hevc_mux"; + }; + + vdec { + compatible = "amlogic, vdec"; + dev_name = "vdec.0"; + status = "okay"; + interrupts = <0 3 1 + 0 23 1 + 0 32 1 + 0 43 1 + 0 44 1 + 0 45 1>; + interrupt-names = "vsync", + "demux", + "parser", + "mailbox_0", + "mailbox_1", + "mailbox_2"; + }; + + gpio_keypad{ + compatible = "amlogic, gpio_keypad"; + status = "okay"; + scan_period = <20>; + key_num = <1>; + key_name = "power"; + key_code = <116>; + key-gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_HIGH>; + detect_mode = <0>;/*0:polling mode, 1:irq mode*/ + }; + + aml_sensor0: aml-sensor@0 { + compatible = "amlogic, aml-thermal"; + device_name = "thermal"; + #thermal-sensor-cells = <1>; + cooling_devices { + cpufreq_cool_cluster0 { + min_state = <1000000>; + dyn_coeff = <140>; + cluster_id = <0>; + node_name = "cpufreq_cool0"; + device_type = "cpufreq"; + }; + cpucore_cool_cluster0 { + min_state = <1>; + dyn_coeff = <0>; + cluster_id = <0>; + node_name = "cpucore_cool0"; + device_type = "cpucore"; + }; + gpufreq_cool { + min_state = <400>; + dyn_coeff = <437>; + cluster_id = <0>; + node_name = "gpufreq_cool0"; + device_type = "gpufreq"; + }; + gpucore_cool { + min_state = <1>; + dyn_coeff = <0>; + cluster_id = <0>; + node_name = "gpucore_cool0"; + device_type = "gpucore"; + }; + }; + cpufreq_cool0:cpufreq_cool0 { + #cooling-cells = <2>; /* min followed by max */ + }; + cpucore_cool0:cpucore_cool0 { + #cooling-cells = <2>; /* min followed by max */ + }; + gpufreq_cool0:gpufreq_cool0 { + #cooling-cells = <2>; /* min followed by max */ + }; + gpucore_cool0:gpucore_cool0 { + #cooling-cells = <2>; /* min followed by max */ + }; + }; + thermal-zones { + soc_thermal { + polling-delay = <1000>; + polling-delay-passive = <100>; + sustainable-power = <2150>; + + thermal-sensors = <&aml_sensor0 3>; + + trips { + switch_on: trip-point@0 { + temperature = <70000>; + hysteresis = <1000>; + type = "passive"; + }; + control: trip-point@1 { + temperature = <80000>; + hysteresis = <1000>; + type = "passive"; + }; + hot: trip-point@2 { + temperature = <85000>; + hysteresis = <5000>; + type = "hot"; + }; + critical: trip-point@3 { + temperature = <260000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + + cooling-maps { + cpufreq_cooling_map { + trip = <&control>; + cooling-device = <&cpufreq_cool0 0 4>; + contribution = <1024>; + }; + cpucore_cooling_map { + trip = <&control>; + cooling-device = <&cpucore_cool0 0 3>; + contribution = <1024>; + }; + gpufreq_cooling_map { + trip = <&control>; + cooling-device = <&gpufreq_cool0 0 4>; + contribution = <1024>; + }; + gpucore_cooling_map { + trip = <&control>; + cooling-device = <&gpucore_cool0 0 2>; + contribution = <1024>; + }; + }; + }; + }; + + dwc3: dwc3@c9000000 { + compatible = "synopsys, dwc3"; + reg = <0xc9000000 0x100000>; + interrupts = <0 30 4>; + usb-phy = <&usb2_phy>, <&usb3_phy>; + cpu-type = "gxl"; + clock-src = "usb3.0"; + }; + + usb2_phy: usb2phy@d0078000 { + compatible = "amlogic, amlogic-new-usb2"; + portnum = <3>; + reg = <0xd0078000 0x80 + 0xc1104408 0x4>; + }; + + usb3_phy: usb3phy@d0078080 { + compatible = "amlogic, amlogic-new-usb3"; + portnum = <0>; + reg = <0xd0078080 0x20>; + }; + + dwc2_a { + compatible = "amlogic, dwc2"; + device_name = "dwc2_a"; + reg = <0xc9100000 0x40000>; + status = "okay"; + interrupts = <0 31 4>; + pl-periph-id = <0>; /** lm name */ + clock-src = "usb0"; /** clock src */ + port-id = <0>; /** ref to mach/usb.h */ + port-type = <2>; /** 0: otg, 1: host, 2: slave */ + port-speed = <0>; /** 0: default, high, 1: full */ + port-config = <0>; /** 0: default */ + port-dma = <0>; /** 0: default ... 6: disable*/ + port-id-mode = <0>; /** 0: hardware, 1: sw_host, 2: sw_slave*/ + usb-fifo = <728>; + cpu-type = "gxl"; + controller-type = <1>; /** 0: normal, 1: host, 2: device*/ + phy-reg = <0xd0078000>; + phy-reg-size = <0xa0>; + clocks = <&clkc CLKID_USB_GENERAL + &clkc CLKID_USB1_TO_DDR + &clkc CLKID_USB1>; + clock-names = "usb_general", + "usb1", + "usb1_to_ddr"; + }; + + meson-amvideom { + compatible = "amlogic, amvideom"; + dev_name = "amvideom"; + status = "okay"; + interrupts = <0 3 1>; + interrupt-names = "vsync"; + }; + + vout { + compatible = "amlogic, vout"; + dev_name = "vout"; + status = "okay"; + fr_auto_policy = <0>; + }; + + cvbsout { + compatible = "amlogic, cvbsout-gxl"; + dev_name = "cvbsout"; + status = "disabled"; + clocks = <&clkc CLKID_VCLK2_ENCI + &clkc CLKID_VCLK2_VENCI0 + &clkc CLKID_VCLK2_VENCI1 + &clkc CLKID_DAC_CLK>; + clock-names = "venci_top_gate", + "venci_0_gate", + "venci_1_gate", + "vdac_clk_gate"; + + /* performance: reg_address, reg_value */ + /* s905x */ + performance = <0x1bf0 0x9 + 0x1b56 0x343 + 0x1b12 0x8080 + 0x1b05 0xfd + 0x1c59 0xf752 + 0xffff 0x0>; /* ending flag */ + }; + + amhdmitx: amhdmitx{ + compatible = "amlogic, amhdmitx"; + dev_name = "amhdmitx"; + status = "okay"; + vend-data = <&vend_data>; + pinctrl-names="hdmitx_hpd", "hdmitx_ddc"; + pinctrl-0=<&hdmitx_hpd>; + pinctrl-1=<&hdmitx_ddc>; + /* HPD, 57 + 32 = 89; CEC, 151 + 32 = 183*/ + interrupts = <0 57 1>; + interrupt-names = "hdmitx_hpd"; + /* 0:M8B 1:GXBB 2:GXTVBB 3:GXL 4:GXM + * 5:TXL 6:TXLX 7:AXG 8:GXLX 9:TXHD + */ + ic_type = <3>; + vend_data: vend_data{ /* Should modified by Customer */ + vendor_name = "Amlogic"; /* Max Chars: 8 */ + /* standards.ieee.org/develop/regauth/oui/oui.txt */ + vendor_id = <0x000000>; + product_desc = "MBox Meson Ref"; /* Max Chars: 16 */ + }; + }; + + aocec: aocec{ + compatible = "amlogic, amlogic-aocec"; + device_name = "aocec"; + status = "okay"; + vendor_id = <0x000000>; + cec_osd_string = "MBox"; /* Max Chars: 14 */ + cec_version = <5>; /* 5: 1.4, 6: 2.0 */ + port_num = <1>; + arc_port_mask = <0x0>; + interrupts = <0 199 1>; + interrupt-names = "hdmi_aocec"; + pinctrl-names = "default"; + pinctrl-0=<&hdmitx_aocec>; + reg = <0xc810023c 0x4 + 0xc8100000 0x200>; + reg-names = "ao_exit","ao"; + }; + + sysled { + compatible = "amlogic, sysled"; + dev_name = "sysled"; + status = "disabled"; + led_gpio = <&gpio GPIODV_24 GPIO_ACTIVE_HIGH>; + led_active_low = <1>; + }; + + meson-fb { + compatible = "amlogic, meson-gxl"; + memory-region = <&logo_reserved>; + dev_name = "meson-fb"; + status = "okay"; + interrupts = <0 3 1 + 0 89 1>; + interrupt-names = "viu-vsync", "rdma"; + mem_size = <0x00800000 0x01800000 0x00100000>; + /* uboot logo,fb0/fb1 memory size,if afbcd fb0=0x01851000*/ + display_mode_default = "1080p60hz"; + scale_mode = <1>; + /** 0:VPU free scale 1:OSD free scale 2:OSD super scale */ + display_size_default = <1920 1080 1920 3240 32>; + /*1920*1080*4*3 = 0x17BB000*/ + logo_addr = "0x7f800000"; + }; + ge2d { + compatible = "amlogic, ge2d-gxl"; + dev_name = "ge2d"; + status = "okay"; + interrupts = <0 150 1>; + interrupt-names = "ge2d"; + clocks = <&clkc CLKID_VAPB_MUX>, + <&clkc CLKID_G2D>, + <&clkc CLKID_GE2D_GATE>; + clock-names = "clk_vapb_0", + "clk_ge2d", + "clk_ge2d_gate"; + }; + + + /* AUDIO MESON DEVICES */ + i2s_dai: I2S { + #sound-dai-cells = <0>; + compatible = "amlogic, aml-i2s-dai"; + clocks = + <&clkc CLKID_MPLL2>, + <&clkc CLKID_AMCLK_COMP>, + <&clkc CLKID_AIU_GLUE>, + <&clkc CLKID_IEC958>, + <&clkc CLKID_I2S_OUT>, + <&clkc CLKID_AMCLK>, + <&clkc CLKID_AIFIFO2>, + <&clkc CLKID_MIXER>, + <&clkc CLKID_MIXER_IFACE>, + <&clkc CLKID_ADC>, + <&clkc CLKID_AIU_TOP>, + <&clkc CLKID_AOCLK_GATE>, + <&clkc CLKID_I2S_SPDIF>; + clock-names = + "mpll", + "mclk", + "top_glue", + "aud_buf", + "i2s_out", + "amclk_measure", + "aififo2", + "aud_mixer", + "mixer_reg", + "adc", + "top_level", + "aoclk", + "aud_in"; + i2s_pos_sync = <0>; + /*DMIC;*/ /* I2s Mic or Dmic, default for I2S mic */ + }; + dmic:snd_dmic { + #sound-dai-cells = <0>; + compatible = "aml, aml_snd_dmic"; + reg = <0xd0042000 0x2000>; + status = "disabled"; + resets = < + &clkc CLKID_PDM_GATE + >; + reset-names = "pdm"; + pinctrl-names = "audio_dmic"; + pinctrl-0 = <&aml_dmic_pins>; + clocks = <&clkc CLKID_PDM_COMP>, + <&clkc CLKID_AMCLK_COMP>; + clock-names = "pdm", "mclk"; + }; + spdif_dai: SPDIF { + #sound-dai-cells = <0>; + compatible = "amlogic, aml-spdif-dai"; + clocks = + <&clkc CLKID_MPLL1>, + <&clkc CLKID_I958_COMP>, + <&clkc CLKID_AMCLK_COMP>, + <&clkc CLKID_I958_COMP_SPDIF>, + <&clkc CLKID_CLK81>, + <&clkc CLKID_IEC958>, + <&clkc CLKID_IEC958_GATE>; + clock-names = + "mpll1", + "i958", + "mclk", + "spdif", + "clk_81", + "iec958", + "iec958_amclk"; + }; + pcm_dai: PCM { + #sound-dai-cells = <0>; + compatible = "amlogic, aml-pcm-dai"; + pinctrl-names = "audio_pcm"; + pinctrl-0 = <&audio_pcm_pins>; + clocks = + <&clkc CLKID_MPLL0>, + <&clkc CLKID_PCM_MCLK_COMP>, + <&clkc CLKID_PCM_SCLK_GATE>; + clock-names = + "mpll0", + "pcm_mclk", + "pcm_sclk"; + pcm_mode = <1>; /* 0=slave mode, 1=master mode */ + }; + i2s_plat: i2s_platform { + compatible = "amlogic, aml-i2s"; + interrupts = <0 29 1>; + }; + pcm_plat: pcm_platform { + compatible = "amlogic, aml-pcm"; + }; + spdif_codec: spdif_codec{ + #sound-dai-cells = <0>; + compatible = "amlogic, aml-spdif-codec"; + pinctrl-names = "audio_spdif"; + pinctrl-0 = <&audio_spdif_pins>; + }; + pcm_codec: pcm_codec{ + #sound-dai-cells = <0>; + compatible = "amlogic, pcm2BT-codec"; + }; + /* endof AUDIO MESON DEVICES */ + + /* AUDIO board specific */ + dummy_codec:dummy{ + #sound-dai-cells = <0>; + compatible = "amlogic, aml_dummy_codec"; + status = "okay"; + }; + amlogic_codec:t9015{ + #sound-dai-cells = <0>; + compatible = "amlogic, aml_codec_T9015"; + reg = <0xc8832000 0x14>; + status = "disabled"; + }; + aml_sound_meson { + compatible = "aml, meson-snd-card"; + status = "okay"; + aml-sound-card,format = "i2s"; + aml_sound_card,name = "AML-MESONAUDIO"; + aml,audio-routing = + "Ext Spk","LOUTL", + "Ext Spk","LOUTR"; + + mute_gpio-gpios = <&gpio GPIOH_5 0>; + mute_inv; + hp_disable; + hp_paraments = <800 300 0 5 1>; + pinctrl-names = "audio_i2s"; + pinctrl-0 = <&audio_i2s_pins>; + cpu_list = <&cpudai0 &cpudai1 &cpudai2>; + codec_list = <&codec0 &codec1 &codec2>; + plat_list = <&i2s_plat &i2s_plat &pcm_plat>; + cpudai0: cpudai0 { + sound-dai = <&i2s_dai>; + }; + cpudai1: cpudai1 { + sound-dai = <&spdif_dai>; + }; + cpudai2: cpudai2 { + sound-dai = <&pcm_dai>; + }; + codec0: codec0 { + sound-dai = <&dummy_codec>; + }; + codec1: codec1 { + sound-dai = <&spdif_codec>; + }; + codec2: codec2 { + sound-dai = <&pcm_codec>; + }; + }; + /* END OF AUDIO board specific */ + rdma{ + compatible = "amlogic, meson, rdma"; + dev_name = "amlogic-rdma"; + status = "ok"; + interrupts = <0 89 1>; + interrupt-names = "rdma"; + }; + + amvenc_avc{ + compatible = "amlogic, amvenc_avc"; + dev_name = "amvenc_avc"; + status = "okay"; + interrupts = <0 45 1>; + interrupt-names = "mailbox_2"; + }; + + hevc_enc{ + compatible = "cnm, HevcEnc"; + dev_name = "HevcEnc"; + status = "okay"; + interrupts = <0 187 1>; + interrupt-names = "wave420l_irq"; + #address-cells=<1>; + #size-cells=<1>; + ranges; + io_reg_base{ + reg = <0xc8810000 0x4000>; + }; + }; + + picdec { + compatible = "amlogic, picdec"; + memory-region = <&picdec_cma_reserved>; + dev_name = "picdec"; + status = "okay"; + }; + + ppmgr { + compatible = "amlogic, ppmgr"; + memory-region = <&ppmgr_reserved>; + dev_name = "ppmgr"; + status = "okay"; + }; + + deinterlace { + compatible = "amlogic, deinterlace"; + status = "okay"; + flag_cma = <1>;/*0:use reserved;1:use cma*/ + //memory-region = <&di_reserved>; + memory-region = <&di_cma_reserved>; + interrupts = <0 46 1 0 6 1>; + interrupt-names = "de_irq", "timerc"; + /* + * nr_size(byte) = 1920*544*2(yuv422 8bit) | + * 1920*544*2*12/8(yuv422 10bit) + * | 1920*544*2*10/8(yuv422 10bit full pack mode) + */ + /* mtn_size(byte) = 1920*544/2 */ + /* count_size(byte) = 1920*544/2 */ + buffer-size = <3133440>; + hw-version = <2>; + }; + + ionvideo { + compatible = "amlogic, ionvideo"; + dev_name = "ionvideo"; + status = "okay"; + }; + + amlvideo { + compatible = "amlogic, amlvideo"; + dev_name = "amlvideo"; + status = "okay"; + }; + + amlvideo2_0 { + compatible = "amlogic, amlvideo2"; + dev_name = "amlvideo2"; + status = "okay"; + amlvideo2_id = <0>; + cma_mode = <1>; + }; + + amlvideo2_1 { + compatible = "amlogic, amlvideo2"; + dev_name = "amlvideo2"; + status = "okay"; + amlvideo2_id = <1>; + cma_mode = <1>; + }; + + /*if you want to use vdin just modify status to "ok"*/ + vdin0 { + compatible = "amlogic, vdin"; + /*memory-region = <&vdin0_cma_reserved>;*/ + dev_name = "vdin0"; + status = "ok"; + reserve-iomap = "true"; + flag_cma = <1>;/*1:share with codec_mm;2:cma alone*/ + /*MByte, if 10bit disable: 64M(YUV422), + *if 10bit enable: 64*1.5 = 96M(YUV422) + *if support 4K2K-YUV444-10bit-WR:3840*2160*4*4 ~= 128M + *if support 4K2K-YUV422-10bit-wr:3840*2160*3*4 ~= 96M + *if support 4K2K-YUV422-8BIT-WR:3840*2160*2*4 ~= 64M + *if support 1080p-YUV422-8BIT-WR:1920*1080*2*4 ~= 16M + */ + cma_size = <16>; + interrupts = <0 83 1>; + rdma-irq = <2>; + /*clocks = <&clock CLK_FPLL_DIV5>, + * <&clock CLK_VDIN_MEAS_CLK>; + *clock-names = "fclk_div5", "cts_vdin_meas_clk"; + */ + vdin_id = <0>; + /*vdin write mem color depth support: + *bit0:support 8bit + *bit1:support 9bit + *bit2:support 10bit + *bit3:support 12bit + *bit4:support yuv422 10bit full pack mode (from txl new add) + */ + tv_bit_mode = <1>; + }; + vdin1 { + compatible = "amlogic, vdin"; + memory-region = <&vdin1_cma_reserved>; + dev_name = "vdin1"; + status = "ok"; + reserve-iomap = "true"; + flag_cma = <0>;/*1:share with codec_mm;0:cma alone*/ + interrupts = <0 85 1>; + rdma-irq = <4>; + /*clocks = <&clock CLK_FPLL_DIV5>, + * <&clock CLK_VDIN_MEAS_CLK>; + *clock-names = "fclk_div5", "cts_vdin_meas_clk"; + */ + vdin_id = <1>; + /*vdin write mem color depth support: + *bit0:support 8bit + *bit1:support 9bit + *bit2:support 10bit + *bit3:support 12bit + */ + tv_bit_mode = <1>; + }; + + amlvecm { + compatible = "amlogic, vecm"; + dev_name = "aml_vecm"; + status = "okay"; + gamma_en = <0>;/*1:enabel ;0:disable*/ + wb_en = <0>;/*1:enabel ;0:disable*/ + cm_en = <0>;/*1:enabel ;0:disable*/ + }; + + unifykey{ + compatible = "amlogic, unifykey"; + status = "ok"; + + unifykey-num = <16>; + unifykey-index-0 = <&keysn_0>; + unifykey-index-1 = <&keysn_1>; + unifykey-index-2 = <&keysn_2>; + unifykey-index-3 = <&keysn_3>; + unifykey-index-4 = <&keysn_4>; + unifykey-index-5 = <&keysn_5>; + unifykey-index-6 = <&keysn_6>; + unifykey-index-7 = <&keysn_7>; + unifykey-index-8 = <&keysn_8>; + unifykey-index-9 = <&keysn_9>; + unifykey-index-10= <&keysn_10>; + unifykey-index-11= <&keysn_11>; + unifykey-index-12= <&keysn_12>; + unifykey-index-13= <&keysn_13>; + unifykey-index-14= <&keysn_14>; + unifykey-index-15= <&keysn_15>; + + keysn_0: key_0{ + key-name = "usid"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_1:key_1{ + key-name = "mac"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_2:key_2{ + key-name = "hdcp"; + key-device = "secure"; + key-type = "sha1"; + key-permit = "read","write","del"; + }; + keysn_3:key_3{ + key-name = "secure_boot_set"; + key-device = "efuse"; + key-permit = "write"; + }; + keysn_4:key_4{ + key-name = "mac_bt"; + key-device = "normal"; + key-permit = "read","write","del"; + key-type = "mac"; + }; + keysn_5:key_5{ + key-name = "mac_wifi"; + key-device = "normal"; + key-permit = "read","write","del"; + key-type = "mac"; + }; + keysn_6:key_6{ + key-name = "hdcp2_tx"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_7:key_7{ + key-name = "hdcp2_rx"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_8:key_8{ + key-name = "widevinekeybox"; + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_9:key_9{ + key-name = "deviceid"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_10:key_10{ + key-name = "hdcp22_fw_private"; + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_11:key_11{ + key-name = "PlayReadykeybox25"; + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_12:key_12{ + key-name = "prpubkeybox";// PlayReady + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_13:key_13{ + key-name = "prprivkeybox";// PlayReady + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_14:key_14{ + key-name = "attestationkeybox";// attestation key + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_15: key_15{ + key-name = "region_code"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + };//End unifykey +}; +&efuse { + status = "ok"; +}; + +&pwm_ef { + status = "okay"; +}; + +&audio_data{ + status = "okay"; +}; + diff --git a/arch/arm/boot/dts/amlogic/gxl_skt.dts b/arch/arm/boot/dts/amlogic/gxl_skt.dts new file mode 100644 index 000000000000..44914a81580e --- /dev/null +++ b/arch/arm/boot/dts/amlogic/gxl_skt.dts @@ -0,0 +1,1214 @@ +/* + * arch/arm/boot/dts/amlogic/gxl_skt.dts + * + * Copyright (C) 2017 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +/dts-v1/; + +#include "mesongxl.dtsi" +#include "partition_mbox_normal.dtsi" +/ { + model = "Amlogic"; + amlogic-dt-id = "gxl_p212_1g"; + compatible = "amlogic, Gxl"; + interrupt-parent = <&gic>; + #address-cells = <1>; + #size-cells = <1>; + + aliases { + serial0 = &uart_AO; + serial1 = &uart_A; + serial2 = &uart_B; + serial3 = &uart_C; + serial4 = &uart_AO_B; + }; + + ion_dev { + compatible = "amlogic, ion_dev"; + memory-region = <&ion_reserved>; + }; + + memory@00000000 { + device_type = "memory"; + linux,usable-memory = <0x0100000 0x3ff00000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + /* global autoconfigured region for contiguous allocations */ + secmon_reserved:linux,secmon { + compatible = "shared-dma-pool"; + reusable; + size = <0x400000>; + alignment = <0x400000>; + alloc-ranges = <0x05000000 0x400000>; + }; + secos_reserved:linux,secos { + status = "disable"; + compatible = "amlogic, aml_secos_memory"; + reg = <0x05300000 0x2000000>; + no-map; + }; + logo_reserved:linux,meson-fb { + compatible = "shared-dma-pool"; + reusable; + size = <0x800000>; + alignment = <0x400000>; + alloc-ranges = <0x3f800000 0x800000>; + }; + //don't put other dts in front of logo_reserved + + //di_reserved:linux,di { + // compatible = "amlogic, di-mem"; + /** 10x3133440=30M(0x1e) support 8bit **/ + // size = <0x1e00000>; + //no-map; + //}; + di_cma_reserved:linux,di_cma { + compatible = "shared-dma-pool"; + reusable; + /** 10x3133440=30M(0x1e) support 8bit **/ + size = <0x2000000>; + alignment = <0x400000>; + }; + + ion_reserved:linux,ion-dev { + compatible = "shared-dma-pool"; + reusable; + size = <0x4C00000>; + alignment = <0x400000>; + alloc-ranges = <0x0 0x30000000>; + }; + + /* vdin0 CMA pool */ + //vdin0_cma_reserved:linux,vdin0_cma { + // compatible = "shared-dma-pool"; + // linux,phandle = <4>; + // reusable; + /* 1920x1080x2x4 =16+4 M */ + // size = <0x01400000>; + // alignment = <0x400000>; + //}; + /* vdin1 CMA pool */ + vdin1_cma_reserved:linux,vdin1_cma { + compatible = "shared-dma-pool"; + reusable; + /* 1920x1080x2x4 =16 M */ + size = <0x01000000>; + alignment = <0x400000>; + }; + /* POST PROCESS MANAGER */ + ppmgr_reserved:linux,ppmgr { + compatible = "shared-dma-pool"; + size = <0x0>; + }; + + codec_mm_cma:linux,codec_mm_cma { + compatible = "shared-dma-pool"; + reusable; + /* ion_codec_mm max can alloc size 80M*/ + size = <0xd000000>; + alignment = <0x400000>; + linux,contiguous-region; + }; + picdec_cma_reserved:linux,picdec { + compatible = "shared-dma-pool"; + reusable; + size = <0x0>; + alignment = <0x0>; + linux,contiguous-region; + }; + /* codec shared reserved */ + codec_mm_reserved:linux,codec_mm_reserved { + compatible = "amlogic, codec-mm-reserved"; + size = <0x0>; + alignment = <0x100000>; + //no-map; + }; + }; + + amlogic_battery:dummy-battery { + compatible = "amlogic, dummy-battery"; + status = "disabled"; + }; + + amlogic_charger:dummy-charger { + compatible = "amlogic, dummy-charger"; + status = "disabled"; + }; + + bt-dev{ + compatible = "amlogic, bt-dev"; + dev_name = "bt-dev"; + status = "okay"; + gpio_reset = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>; + }; + wifi{ + compatible = "amlogic, aml_wifi"; + dev_name = "aml_wifi"; + status = "okay"; + interrupt_pin = <&gpio GPIOX_7 GPIO_ACTIVE_HIGH>; + irq_trigger_type = "GPIO_IRQ_LOW"; + dhd_static_buf; //dhd_static_buf support + power_on_pin = <&gpio GPIOX_6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_32k_pins>; + pwm_config = <&wifi_pwm_conf>; + }; + + wifi_pwm_conf:wifi_pwm_conf{ + pwm_channel1_conf { + pwms = <&pwm_ef MESON_PWM_0 30040 0>; + duty-cycle = <15020>; + times = <8>; + }; + pwm_channel2_conf { + pwms = <&pwm_ef MESON_PWM_2 30030 0>; + duty-cycle = <15015>; + times = <12>; + }; + }; + + sd_emmc_c: emmc@d0074000 { + status = "okay"; + compatible = "amlogic, meson-mmc-gxl"; + reg = <0xd0074000 0x2000>; + interrupts = <0 218 1>; + pinctrl-names = "emmc_clk_cmd_pins", "emmc_all_pins"; + pinctrl-0 = <&emmc_clk_cmd_pins>; + pinctrl-1 = <&emmc_conf_pull_up &emmc_conf_pull_done>; + clocks = <&clkc CLKID_SD_EMMC_C>, + <&clkc CLKID_SD_EMMC_C_P0_COMP>, + <&clkc CLKID_FCLK_DIV2>; + clock-names = "core", "clkin0", "clkin1"; + + bus-width = <8>; + cap-sd-highspeed; + cap-mmc-highspeed; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + + max-frequency = <200000000>; + non-removable; + disable-wp; + emmc { + pinname = "emmc"; + ocr_avail = <0x200080>; /**VDD voltage 3.3 ~ 3.4 */ + caps = "MMC_CAP_8_BIT_DATA", + "MMC_CAP_MMC_HIGHSPEED", + "MMC_CAP_SD_HIGHSPEED", + "MMC_CAP_NONREMOVABLE", + "MMC_CAP_1_8V_DDR", + "MMC_CAP_HW_RESET", + "MMC_CAP_ERASE", + "MMC_CAP_CMD23"; + caps2 = "MMC_CAP2_HS200", "MMC_CAP2_HS400"; + f_min = <400000>; + f_max = <100000000>; + max_req_size = <0x20000>; /**128KB*/ + gpio_dat3 = <&gpio BOOT_3 GPIO_ACTIVE_HIGH>; + hw_reset = <&gpio BOOT_9 GPIO_ACTIVE_HIGH>; + card_type = <1>; + /* 1:mmc card(include eMMC), + * 2:sd card(include tSD) + */ + }; + }; + + sd_emmc_b:sd@d0072000 { + status = "okay"; + compatible = "amlogic, meson-mmc-gxl"; + reg = <0xd0072000 0x2000>; + interrupts = <0 217 1>; + pinctrl-names = "sd_all_pins", + "sd_clk_cmd_pins", + "sd_1bit_pins", + "sd_clk_cmd_uart_pins", + "sd_1bit_uart_pins", + "sd_to_ao_uart_pins", + "ao_to_sd_uart_pins", + "ao_to_sd_jtag_pins", + "sd_to_ao_jtag_pins"; + pinctrl-0 = <&sd_all_pins>; + pinctrl-1 = <&sd_clk_cmd_pins>; + pinctrl-2 = <&sd_1bit_pins>; + pinctrl-3 = <&sd_to_ao_uart_clr_pins + &sd_clk_cmd_pins &ao_to_sd_uart_pins>; + pinctrl-4 = <&sd_to_ao_uart_clr_pins + &sd_1bit_pins &ao_to_sd_uart_pins>; + pinctrl-5 = <&sd_all_pins &sd_to_ao_uart_pins>; + pinctrl-6 = <&sd_to_ao_uart_clr_pins &ao_to_sd_uart_pins>; + pinctrl-7 = <&sd_to_ao_uart_clr_pins &ao_to_sd_uart_pins>; + pinctrl-8 = <&sd_all_pins &sd_to_ao_uart_pins>; + clocks = <&clkc CLKID_SD_EMMC_B>, + <&clkc CLKID_SD_EMMC_B_P0_COMP>, + <&clkc CLKID_FCLK_DIV2>; + clock-names = "core", "clkin0", "clkin1"; + + bus-width = <4>; + cap-sd-highspeed; + max-frequency = <100000000>; + disable-wp; + sd { + pinname = "sd"; + ocr_avail = <0x200080>; /**VDD voltage 3.3 ~ 3.4 */ + caps = "MMC_CAP_4_BIT_DATA", + "MMC_CAP_MMC_HIGHSPEED", + "MMC_CAP_SD_HIGHSPEED"; + /* "MMC_CAP_UHS_SDR12", + * "MMC_CAP_UHS_SDR25", + * "MMC_CAP_UHS_SDR50", + * "MMC_CAP_UHS_SDR104"; + */ + f_min = <400000>; + f_max = <100000000>; + max_req_size = <0x20000>; /**128KB*/ + gpio_dat3 = <&gpio CARD_4 GPIO_ACTIVE_HIGH>; + jtag_pin = <&gpio CARD_0 GPIO_ACTIVE_HIGH>; + gpio_cd = <&gpio CARD_6 GPIO_ACTIVE_HIGH>; + card_type = <5>; + /* 0:unknown, + * 1:mmc card(include eMMC), + * 2:sd card(include tSD), + * 3:sdio device(ie:sdio-wifi), + * 4:SD combo (IO+mem) card, + * 5:NON sdio device(means sd/mmc card), + * other:reserved + */ + }; + }; + + sd_emmc_a:sdio@d0070000 { + status = "okay"; + compatible = "amlogic, meson-mmc-gxl"; + reg = <0xd0070000 0x2000>; + interrupts = <0 216 4>; + pinctrl-names = "sdio_clk_cmd_pins", "sdio_all_pins"; + pinctrl-0 = <&sdio_clk_cmd_pins>; + pinctrl-1 = <&sdio_all_pins>; + clocks = <&clkc CLKID_SD_EMMC_A>, + <&clkc CLKID_SD_EMMC_A_P0_COMP>, + <&clkc CLKID_FCLK_DIV2>; + clock-names = "core", "clkin0", "clkin1"; + + bus-width = <4>; + cap-sd-highspeed; + cap-mmc-highspeed; + max-frequency = <100000000>; + non-removable; + disable-wp; + sdio { + pinname = "sdio"; + ocr_avail = <0x200080>; /**VDD voltage 3.3 ~ 3.4 */ + caps = "MMC_CAP_4_BIT_DATA", + "MMC_CAP_MMC_HIGHSPEED", + "MMC_CAP_SD_HIGHSPEED", + "MMC_CAP_NONREMOVABLE", + "MMC_CAP_UHS_SDR12", + "MMC_CAP_UHS_SDR25", + "MMC_CAP_UHS_SDR50", + "MMC_CAP_UHS_SDR104", + "MMC_PM_KEEP_POWER", + "MMC_CAP_SDIO_IRQ"; + f_min = <400000>; + f_max = <200000000>; + max_req_size = <0x20000>; /**128KB*/ + card_type = <3>; + /* 3:sdio device(ie:sdio-wifi), + * 4:SD combo (IO+mem) card + */ + }; + }; + mtd_nand{ + compatible = "amlogic, aml_mtd_nand"; + dev_name = "mtdnand"; + status = "disabled"; + reg = <0xd0074800 0x200>; + interrupts = < 0 34 1 >; + pinctrl-names = "nand_rb_mod","nand_norb_mod", "nand_cs_only"; + pinctrl-0 = <&all_nand_pins>; + pinctrl-1 = <&all_nand_pins>; + pinctrl-2 = <&nand_cs_pins>; + device_id = <0>; + plat-names = "bootloader","nandnormal"; + plat-num = <2>; + plat-part-0 = <&bootloader>; + plat-part-1 = <&nandnormal>; + bootloader: bootloader{ + enable_pad ="ce0"; + busy_pad = "rb0"; + timming_mode = "mode5"; + bch_mode = "bch60_1k"; + t_rea = <20>; + t_rhoh = <15>; + chip_num = <1>; + part_num = <0>; + rb_detect = <1>; + }; + nandnormal: nandnormal{ + enable_pad ="ce0","ce1"; + busy_pad = "rb0","rb1"; + timming_mode = "mode5"; + bch_mode = "bch60_1k"; + plane_mode = "twoplane"; + t_rea = <20>; + t_rhoh = <15>; + chip_num = <2>; + part_num = <3>; + partition = <&nand_partitions>; + rb_detect = <1>; + }; + nand_partitions:nand_partition{ + logo{ + offset=<0x0 0x0>; + size=<0x0 0x200000>; + }; + recovery{ + offset=<0x0 0x0>; + size=<0x0 0x1000000>; + }; + boot{ + offset=<0x0 0x0>; + size=<0x0 0xC00000>; + }; + system{ + offset=<0x0 0x0>; + size=<0x0 0xDC40000>; + }; + data{ + offset=<0xffffffff 0xffffffff>; + size=<0x0 0x0>; + }; + }; + }; + + ethmac: ethernet@0xc9410000 { + compatible = "amlogic, gxbb-eth-dwmac"; + reg = <0xc9410000 0x10000 + 0xc8834540 0x8 + 0xc8834558 0xc>; + interrupts = <0 8 1>; + pinctrl-names = "external_eth_pins"; + pinctrl-0 = <&external_eth_pins>; + rst_pin-gpios = <&gpio GPIOZ_14 0>; + GPIOZ4_pin-gpios = <&gpio GPIOZ_4 0>; + GPIOZ5_pin-gpios = <&gpio GPIOZ_5 0>; + mc_val_internal_phy = <0x1800>; + mc_val_external_phy = <0x1621>; + cali_val = <0x20000>; + interrupt-names = "macirq"; + clocks = <&clkc CLKID_ETH>; + clock-names = "ethclk81"; + internal_phy=<1>; + }; + + aml_sensor0: aml-sensor@0 { + compatible = "amlogic, aml-thermal"; + device_name = "thermal"; + #thermal-sensor-cells = <1>; + cooling_devices { + cpufreq_cool_cluster0 { + min_state = <1000000>; + dyn_coeff = <140>; + cluster_id = <0>; + node_name = "cpufreq_cool0"; + device_type = "cpufreq"; + }; + cpucore_cool_cluster0 { + min_state = <1>; + dyn_coeff = <0>; + cluster_id = <0>; + node_name = "cpucore_cool0"; + device_type = "cpucore"; + }; + gpufreq_cool { + min_state = <400>; + dyn_coeff = <437>; + cluster_id = <0>; + node_name = "gpufreq_cool0"; + device_type = "gpufreq"; + }; + gpucore_cool { + min_state = <1>; + dyn_coeff = <0>; + cluster_id = <0>; + node_name = "gpucore_cool0"; + device_type = "gpucore"; + }; + }; + cpufreq_cool0:cpufreq_cool0 { + #cooling-cells = <2>; /* min followed by max */ + }; + cpucore_cool0:cpucore_cool0 { + #cooling-cells = <2>; /* min followed by max */ + }; + gpufreq_cool0:gpufreq_cool0 { + #cooling-cells = <2>; /* min followed by max */ + }; + gpucore_cool0:gpucore_cool0 { + #cooling-cells = <2>; /* min followed by max */ + }; + }; + thermal-zones { + soc_thermal { + polling-delay = <1000>; + polling-delay-passive = <100>; + sustainable-power = <2150>; + + thermal-sensors = <&aml_sensor0 3>; + + trips { + switch_on: trip-point@0 { + temperature = <70000>; + hysteresis = <1000>; + type = "passive"; + }; + control: trip-point@1 { + temperature = <80000>; + hysteresis = <1000>; + type = "passive"; + }; + hot: trip-point@2 { + temperature = <85000>; + hysteresis = <5000>; + type = "hot"; + }; + critical: trip-point@3 { + temperature = <260000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + + cooling-maps { + cpufreq_cooling_map { + trip = <&control>; + cooling-device = <&cpufreq_cool0 0 4>; + contribution = <1024>; + }; + cpucore_cooling_map { + trip = <&control>; + cooling-device = <&cpucore_cool0 0 3>; + contribution = <1024>; + }; + gpufreq_cooling_map { + trip = <&control>; + cooling-device = <&gpufreq_cool0 0 4>; + contribution = <1024>; + }; + gpucore_cooling_map { + trip = <&control>; + cooling-device = <&gpucore_cool0 0 2>; + contribution = <1024>; + }; + }; + }; + }; + + dwc3: dwc3@c9000000 { + compatible = "synopsys, dwc3"; + reg = <0xc9000000 0x100000>; + interrupts = <0 30 4>; + usb-phy = <&usb2_phy>, <&usb3_phy>; + cpu-type = "gxl"; + clock-src = "usb3.0"; + }; + + usb2_phy: usb2phy@d0078000 { + compatible = "amlogic, amlogic-new-usb2"; + portnum = <3>; + reg = <0xd0078000 0x80 + 0xc1104408 0x4>; + }; + + usb3_phy: usb3phy@d0078080 { + compatible = "amlogic, amlogic-new-usb3"; + portnum = <0>; + reg = <0xd0078080 0x20>; + }; + + dwc2_a { + compatible = "amlogic, dwc2"; + device_name = "dwc2_a"; + reg = <0xc9100000 0x40000>; + status = "okay"; + interrupts = <0 31 4>; + pl-periph-id = <0>; /** lm name */ + clock-src = "usb0"; /** clock src */ + port-id = <0>; /** ref to mach/usb.h */ + port-type = <2>; /** 0: otg, 1: host, 2: slave */ + port-speed = <0>; /** 0: default, high, 1: full */ + port-config = <0>; /** 0: default */ + port-dma = <0>; /** 0: default ... 6: disable*/ + port-id-mode = <0>; /** 0: hardware, 1: sw_host, 2: sw_slave*/ + usb-fifo = <728>; + cpu-type = "gxl"; + controller-type = <1>; /** 0: normal, 1: host, 2: device*/ + phy-reg = <0xd0078000>; + phy-reg-size = <0xa0>; + clocks = <&clkc CLKID_USB_GENERAL + &clkc CLKID_USB1_TO_DDR + &clkc CLKID_USB1>; + clock-names = "usb_general", + "usb1", + "usb1_to_ddr"; + }; + + meson-amvideom { + compatible = "amlogic, amvideom"; + dev_name = "amvideom"; + status = "okay"; + interrupts = <0 3 1>; + interrupt-names = "vsync"; + }; + + vout { + compatible = "amlogic, vout"; + dev_name = "vout"; + status = "okay"; + fr_auto_policy = <0>; + }; + + cvbsout { + compatible = "amlogic, cvbsout-gxl"; + dev_name = "cvbsout"; + status = "okay"; + clocks = <&clkc CLKID_VCLK2_ENCI + &clkc CLKID_VCLK2_VENCI0 + &clkc CLKID_VCLK2_VENCI1 + &clkc CLKID_DAC_CLK>; + clock-names = "venci_top_gate", + "venci_0_gate", + "venci_1_gate", + "vdac_clk_gate"; + + /* performance: reg_address, reg_value */ + /* s905x */ + performance = <0x1bf0 0x9 + 0x1b56 0x343 + 0x1b12 0x8080 + 0x1b05 0xfd + 0x1c59 0xf752 + 0xffff 0x0>; /* ending flag */ + }; + + amhdmitx: amhdmitx{ + compatible = "amlogic, amhdmitx"; + dev_name = "amhdmitx"; + status = "okay"; + vend-data = <&vend_data>; + pinctrl-names="hdmitx_hpd", "hdmitx_ddc"; + pinctrl-0=<&hdmitx_hpd>; + pinctrl-1=<&hdmitx_ddc>; + /* HPD, 57 + 32 = 89; CEC, 151 + 32 = 183*/ + interrupts = <0 57 1>; + interrupt-names = "hdmitx_hpd"; + /* 0:M8B 1:GXBB 2:GXTVBB 3:GXL 4:GXM + * 5:TXL 6:TXLX 7:AXG 8:GXLX 9:TXHD + */ + ic_type = <3>; + vend_data: vend_data{ /* Should modified by Customer */ + vendor_name = "Amlogic"; /* Max Chars: 8 */ + /* standards.ieee.org/develop/regauth/oui/oui.txt */ + vendor_id = <0x000000>; + product_desc = "MBox Meson Ref"; /* Max Chars: 16 */ + }; + }; + + aocec: aocec{ + compatible = "amlogic, amlogic-aocec"; + device_name = "aocec"; + status = "okay"; + vendor_id = <0x000000>; + cec_osd_string = "MBox"; /* Max Chars: 14 */ + cec_version = <5>; /* 5: 1.4, 6: 2.0 */ + port_num = <1>; + arc_port_mask = <0x0>; + interrupts = <0 199 1>; + interrupt-names = "hdmi_aocec"; + pinctrl-names = "default"; + pinctrl-0=<&hdmitx_aocec>; + reg = <0xc810023c 0x4 + 0xc8100000 0x200>; + reg-names = "ao_exit","ao"; + }; + + sysled { + compatible = "amlogic, sysled"; + dev_name = "sysled"; + status = "disabled"; + led_gpio = <&gpio GPIODV_24 GPIO_ACTIVE_HIGH>; + led_active_low = <1>; + }; + + codec_io { + compatible = "amlogic, codec_io"; + #address-cells=<1>; + #size-cells=<1>; + ranges; + io_cbus_base{ + reg = <0xC1100000 0x100000>; + }; + io_dos_base{ + reg = <0xc8820000 0x10000>; + }; + io_hiubus_base{ + reg = <0xc883c000 0x2000>; + }; + io_aobus_base{ + reg = <0xc8100000 0x100000>; + }; + io_vcbus_base{ + reg = <0xd0100000 0x40000>; + }; + io_dmc_base{ + reg = <0xc8838000 0x400>; + }; + }; + + codec_mm { + compatible = "amlogic, codec, mm"; + memory-region = <&codec_mm_cma &codec_mm_reserved>; + dev_name = "codec_mm"; + status = "okay"; + }; + + canvas{ + compatible = "amlogic, meson, canvas"; + dev_name = "amlogic-canvas"; + status = "ok"; + reg = <0xc8838000 0x400>; + }; + + mesonstream { + compatible = "amlogic, codec, streambuf"; + dev_name = "mesonstream"; + status = "okay"; + clocks = <&clkc CLKID_DOS_PARSER + &clkc CLKID_DEMUX + &clkc CLKID_DOS + &clkc CLKID_CLK81 + &clkc CLKID_VDEC_MUX + &clkc CLKID_HCODEC_MUX + &clkc CLKID_HEVC_MUX>; + clock-names = "parser_top", + "demux", + "vdec", + "clk_81", + "clk_vdec_mux", + "clk_hcodec_mux", + "clk_hevc_mux"; + }; + + vdec { + compatible = "amlogic, vdec"; + dev_name = "vdec.0"; + status = "okay"; + interrupts = <0 3 1 + 0 23 1 + 0 32 1 + 0 43 1 + 0 44 1 + 0 45 1>; + interrupt-names = "vsync", + "demux", + "parser", + "mailbox_0", + "mailbox_1", + "mailbox_2"; + }; + + meson-fb { + compatible = "amlogic, meson-gxl"; + memory-region = <&logo_reserved>; + dev_name = "meson-fb"; + status = "okay"; + interrupts = <0 3 1 + 0 89 1>; + interrupt-names = "viu-vsync", "rdma"; + mem_size = <0x00800000 0x01800000 0x00100000>; + /* uboot logo,fb0/fb1 memory size,if afbcd fb0=0x01851000*/ + display_mode_default = "1080p60hz"; + scale_mode = <1>; + /** 0:VPU free scale 1:OSD free scale 2:OSD super scale */ + display_size_default = <1920 1080 1920 3240 32>; + /*1920*1080*4*3 = 0x17BB000*/ + logo_addr = "0x3f800000"; + }; + ge2d { + compatible = "amlogic, ge2d-gxl"; + dev_name = "ge2d"; + status = "okay"; + interrupts = <0 150 1>; + interrupt-names = "ge2d"; + clocks = <&clkc CLKID_VAPB_MUX>, + <&clkc CLKID_G2D>, + <&clkc CLKID_GE2D_GATE>; + clock-names = "clk_vapb_0", + "clk_ge2d", + "clk_ge2d_gate"; + }; + + + /* AUDIO MESON DEVICES */ + i2s_dai: I2S { + #sound-dai-cells = <0>; + compatible = "amlogic, aml-i2s-dai"; + clocks = + <&clkc CLKID_MPLL2>, + <&clkc CLKID_AMCLK_COMP>, + <&clkc CLKID_AIU_GLUE>, + <&clkc CLKID_IEC958>, + <&clkc CLKID_I2S_OUT>, + <&clkc CLKID_AMCLK>, + <&clkc CLKID_AIFIFO2>, + <&clkc CLKID_MIXER>, + <&clkc CLKID_MIXER_IFACE>, + <&clkc CLKID_ADC>, + <&clkc CLKID_AIU_TOP>, + <&clkc CLKID_AOCLK_GATE>, + <&clkc CLKID_I2S_SPDIF>; + clock-names = + "mpll", + "mclk", + "top_glue", + "aud_buf", + "i2s_out", + "amclk_measure", + "aififo2", + "aud_mixer", + "mixer_reg", + "adc", + "top_level", + "aoclk", + "aud_in"; + i2s_pos_sync = <0>; + /*DMIC;*/ /* I2s Mic or Dmic, default for I2S mic */ + }; + dmic:snd_dmic { + #sound-dai-cells = <0>; + compatible = "aml, aml_snd_dmic"; + reg = <0xd0042000 0x2000>; + status = "disabled"; + resets = < + &clkc CLKID_PDM_GATE + >; + reset-names = "pdm"; + pinctrl-names = "audio_dmic"; + pinctrl-0 = <&aml_dmic_pins>; + clocks = <&clkc CLKID_PDM_COMP>, + <&clkc CLKID_AMCLK_COMP>; + clock-names = "pdm", "mclk"; + }; + spdif_dai: SPDIF { + #sound-dai-cells = <0>; + compatible = "amlogic, aml-spdif-dai"; + clocks = + <&clkc CLKID_MPLL1>, + <&clkc CLKID_I958_COMP>, + <&clkc CLKID_AMCLK_COMP>, + <&clkc CLKID_I958_COMP_SPDIF>, + <&clkc CLKID_CLK81>, + <&clkc CLKID_IEC958>, + <&clkc CLKID_IEC958_GATE>; + clock-names = + "mpll1", + "i958", + "mclk", + "spdif", + "clk_81", + "iec958", + "iec958_amclk"; + }; + pcm_dai: PCM { + #sound-dai-cells = <0>; + compatible = "amlogic, aml-pcm-dai"; + pinctrl-names = "audio_pcm"; + pinctrl-0 = <&audio_pcm_pins>; + clocks = + <&clkc CLKID_MPLL0>, + <&clkc CLKID_PCM_MCLK_COMP>, + <&clkc CLKID_PCM_SCLK_GATE>; + clock-names = + "mpll0", + "pcm_mclk", + "pcm_sclk"; + pcm_mode = <1>; /* 0=slave mode, 1=master mode */ + }; + i2s_plat: i2s_platform { + compatible = "amlogic, aml-i2s"; + interrupts = <0 29 1>; + }; + pcm_plat: pcm_platform { + compatible = "amlogic, aml-pcm"; + }; + spdif_codec: spdif_codec{ + #sound-dai-cells = <0>; + compatible = "amlogic, aml-spdif-codec"; + pinctrl-names = "audio_spdif"; + pinctrl-0 = <&audio_spdif_pins>; + }; + pcm_codec: pcm_codec{ + #sound-dai-cells = <0>; + compatible = "amlogic, pcm2BT-codec"; + }; + /* endof AUDIO MESON DEVICES */ + + /* AUDIO board specific */ + dummy_codec:dummy{ + #sound-dai-cells = <0>; + compatible = "amlogic, aml_dummy_codec"; + status = "disable"; + }; + amlogic_codec:t9015{ + #sound-dai-cells = <0>; + compatible = "amlogic, aml_codec_T9015"; + reg = <0xc8832000 0x14>; + status = "okay"; + }; + aml_sound_meson { + compatible = "aml, meson-snd-card"; + status = "okay"; + aml-sound-card,format = "i2s"; + aml_sound_card,name = "AML-MESONAUDIO"; + aml,audio-routing = + "Ext Spk","LOUTL", + "Ext Spk","LOUTR"; + + mute_gpio-gpios = <&gpio GPIOH_5 0>; + mute_inv; + hp_disable; + hp_paraments = <800 300 0 5 1>; + pinctrl-names = "audio_i2s"; + pinctrl-0 = <&audio_i2s_pins>; + cpu_list = <&cpudai0 &cpudai1 &cpudai2>; + codec_list = <&codec0 &codec1 &codec2>; + plat_list = <&i2s_plat &i2s_plat &pcm_plat>; + cpudai0: cpudai0 { + sound-dai = <&i2s_dai>; + }; + cpudai1: cpudai1 { + sound-dai = <&spdif_dai>; + }; + cpudai2: cpudai2 { + sound-dai = <&pcm_dai>; + }; + codec0: codec0 { + sound-dai = <&amlogic_codec>; + }; + codec1: codec1 { + sound-dai = <&spdif_codec>; + }; + codec2: codec2 { + sound-dai = <&pcm_codec>; + }; + }; + /* END OF AUDIO board specific */ + rdma{ + compatible = "amlogic, meson, rdma"; + dev_name = "amlogic-rdma"; + status = "ok"; + interrupts = <0 89 1>; + interrupt-names = "rdma"; + }; + + amvenc_avc{ + compatible = "amlogic, amvenc_avc"; + dev_name = "amvenc_avc"; + status = "okay"; + interrupts = <0 45 1>; + interrupt-names = "mailbox_2"; + }; + + hevc_enc{ + compatible = "cnm, HevcEnc"; + dev_name = "HevcEnc"; + status = "okay"; + interrupts = <0 187 1>; + interrupt-names = "wave420l_irq"; + #address-cells=<1>; + #size-cells=<1>; + ranges; + io_reg_base{ + reg = <0xc8810000 0x4000>; + }; + }; + + picdec { + compatible = "amlogic, picdec"; + memory-region = <&picdec_cma_reserved>; + dev_name = "picdec"; + status = "okay"; + }; + + ppmgr { + compatible = "amlogic, ppmgr"; + memory-region = <&ppmgr_reserved>; + dev_name = "ppmgr"; + status = "okay"; + }; + + deinterlace { + compatible = "amlogic, deinterlace"; + status = "okay"; + flag_cma = <1>;/*0:use reserved;1:use cma*/ + //memory-region = <&di_reserved>; + memory-region = <&di_cma_reserved>; + interrupts = <0 46 1 0 6 1>; + interrupt-names = "de_irq", "timerc"; + /* + * nr_size(byte) = 1920*544*2(yuv422 8bit) | + * 1920*544*2*12/8(yuv422 10bit) + * | 1920*544*2*10/8(yuv422 10bit full pack mode) + */ + /* mtn_size(byte) = 1920*544/2 */ + /* count_size(byte) = 1920*544/2 */ + buffer-size = <3133440>; + hw-version = <2>; + }; + + ionvideo { + compatible = "amlogic, ionvideo"; + dev_name = "ionvideo"; + status = "okay"; + }; + + amlvideo { + compatible = "amlogic, amlvideo"; + dev_name = "amlvideo"; + status = "okay"; + }; + + amlvideo2_0 { + compatible = "amlogic, amlvideo2"; + dev_name = "amlvideo2"; + status = "okay"; + amlvideo2_id = <0>; + cma_mode = <1>; + }; + + amlvideo2_1 { + compatible = "amlogic, amlvideo2"; + dev_name = "amlvideo2"; + status = "okay"; + amlvideo2_id = <1>; + cma_mode = <1>; + }; + + /*if you want to use vdin just modify status to "ok"*/ + vdin0 { + compatible = "amlogic, vdin"; + /*memory-region = <&vdin0_cma_reserved>;*/ + dev_name = "vdin0"; + status = "ok"; + reserve-iomap = "true"; + flag_cma = <1>;/*1:share with codec_mm;2:cma alone*/ + /*MByte, if 10bit disable: 64M(YUV422), + *if 10bit enable: 64*1.5 = 96M(YUV422) + *if support 4K2K-YUV444-10bit-WR:3840*2160*4*4 ~= 128M + *if support 4K2K-YUV422-10bit-wr:3840*2160*3*4 ~= 96M + *if support 4K2K-YUV422-8BIT-WR:3840*2160*2*4 ~= 64M + *if support 1080p-YUV422-8BIT-WR:1920*1080*2*4 ~= 16M + */ + cma_size = <16>; + interrupts = <0 83 1>; + rdma-irq = <2>; + /*clocks = <&clock CLK_FPLL_DIV5>, + * <&clock CLK_VDIN_MEAS_CLK>; + *clock-names = "fclk_div5", "cts_vdin_meas_clk"; + */ + vdin_id = <0>; + /*vdin write mem color depth support: + *bit0:support 8bit + *bit1:support 9bit + *bit2:support 10bit + *bit3:support 12bit + *bit4:support yuv422 10bit full pack mode (from txl new add) + */ + tv_bit_mode = <1>; + }; + vdin1 { + compatible = "amlogic, vdin"; + memory-region = <&vdin1_cma_reserved>; + dev_name = "vdin1"; + status = "ok"; + reserve-iomap = "true"; + flag_cma = <0>;/*1:share with codec_mm;0:cma alone*/ + interrupts = <0 85 1>; + rdma-irq = <4>; + /*clocks = <&clock CLK_FPLL_DIV5>, + * <&clock CLK_VDIN_MEAS_CLK>; + *clock-names = "fclk_div5", "cts_vdin_meas_clk"; + */ + vdin_id = <1>; + /*vdin write mem color depth support: + *bit0:support 8bit + *bit1:support 9bit + *bit2:support 10bit + *bit3:support 12bit + */ + tv_bit_mode = <1>; + }; + + amlvecm { + compatible = "amlogic, vecm"; + dev_name = "aml_vecm"; + status = "okay"; + gamma_en = <0>;/*1:enabel ;0:disable*/ + wb_en = <0>;/*1:enabel ;0:disable*/ + cm_en = <0>;/*1:enabel ;0:disable*/ + /*1:enabel osd lut 100 table;0:disable*/ + cfg_en_osd_100 = <1>; + /*0: 709/601 1: bt2020*/ + tx_op_color_primary = <0>; + }; + + unifykey{ + compatible = "amlogic, unifykey"; + status = "ok"; + + unifykey-num = <16>; + unifykey-index-0 = <&keysn_0>; + unifykey-index-1 = <&keysn_1>; + unifykey-index-2 = <&keysn_2>; + unifykey-index-3 = <&keysn_3>; + unifykey-index-4 = <&keysn_4>; + unifykey-index-5 = <&keysn_5>; + unifykey-index-6 = <&keysn_6>; + unifykey-index-7 = <&keysn_7>; + unifykey-index-8 = <&keysn_8>; + unifykey-index-9 = <&keysn_9>; + unifykey-index-10= <&keysn_10>; + unifykey-index-11= <&keysn_11>; + unifykey-index-12= <&keysn_12>; + unifykey-index-13= <&keysn_13>; + unifykey-index-14= <&keysn_14>; + unifykey-index-15= <&keysn_15>; + + keysn_0: key_0{ + key-name = "usid"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_1:key_1{ + key-name = "mac"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_2:key_2{ + key-name = "hdcp"; + key-device = "secure"; + key-type = "sha1"; + key-permit = "read","write","del"; + }; + keysn_3:key_3{ + key-name = "secure_boot_set"; + key-device = "efuse"; + key-permit = "write"; + }; + keysn_4:key_4{ + key-name = "mac_bt"; + key-device = "normal"; + key-permit = "read","write","del"; + key-type = "mac"; + }; + keysn_5:key_5{ + key-name = "mac_wifi"; + key-device = "normal"; + key-permit = "read","write","del"; + key-type = "mac"; + }; + keysn_6:key_6{ + key-name = "hdcp2_tx"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_7:key_7{ + key-name = "hdcp2_rx"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_8:key_8{ + key-name = "widevinekeybox"; + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_9:key_9{ + key-name = "deviceid"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_10:key_10{ + key-name = "hdcp22_fw_private"; + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_11:key_11{ + key-name = "PlayReadykeybox25"; + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_12:key_12{ + key-name = "prpubkeybox";// PlayReady + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_13:key_13{ + key-name = "prprivkeybox";// PlayReady + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_14:key_14{ + key-name = "attestationkeybox";// attestation key + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_15:key_15{ + key-name = "region_code"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + };//End unifykey + +}; +&efuse { + status = "ok"; +}; + +&pwm_ef { + status = "okay"; +}; + +&audio_data{ + status = "okay"; +}; +&spicc{ + status = "disabled"; + pinctrl-names = "spicc_pulldown","spicc_pullup"; + pinctrl-0 = <&spicc_pulldown_x8x9x11>; + pinctrl-1 = <&spicc_pullup_x8x9x11>; + num_chipselect = <1>; + cs-gpios = <&gpio GPIOX_10 GPIO_ACTIVE_HIGH>; + dma_en = <0>; + dma_tx_threshold = <3>; + dma_rx_threshold = <3>; + dma_num_per_read_burst = <3>; + dma_num_per_write_burst = <3>; + delay_control = <0x15>; + ssctl = <0>; +}; + diff --git a/arch/arm/boot/dts/amlogic/gxm_q200_2g.dts b/arch/arm/boot/dts/amlogic/gxm_q200_2g.dts new file mode 100644 index 000000000000..24022e74c347 --- /dev/null +++ b/arch/arm/boot/dts/amlogic/gxm_q200_2g.dts @@ -0,0 +1,1223 @@ +/* + * arch/arm/boot/dts/amlogic/gxm_q200_2g.dts + * + * Copyright (C) 2017 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +/dts-v1/; + +#include "mesongxm.dtsi" +#include "partition_mbox_normal.dtsi" +/ { + model = "Amlogic"; + amlogic-dt-id = "gxm_q200_2g"; + compatible = "amlogic, Gxm"; + interrupt-parent = <&gic>; + #address-cells = <1>; + #size-cells = <1>; + + aliases { + serial0 = &uart_AO; + serial1 = &uart_A; + serial2 = &uart_B; + serial3 = &uart_C; + serial4 = &uart_AO_B; + }; + + ion_dev { + compatible = "amlogic, ion_dev"; + memory-region = <&ion_reserved>; + }; + + memory@00000000 { + device_type = "memory"; + linux,usable-memory = <0x0100000 0x7ff00000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + /* global autoconfigured region for contiguous allocations */ + ramoops@0x07400000 { + compatible = "ramoops"; + reg = <0x07400000 0x00100000>; + record-size = <0x8000>; + console-size = <0x8000>; + ftrace-size = <0x0>; + pmsg-size = <0x8000>; + }; + secmon_reserved:linux,secmon { + compatible = "shared-dma-pool"; + reusable; + size = <0x400000>; + alignment = <0x400000>; + alloc-ranges = <0x05000000 0x400000>; + }; + secos_reserved:linux,secos { + status = "disable"; + compatible = "amlogic, aml_secos_memory"; + reg = <0x05300000 0x2000000>; + no-map; + }; + logo_reserved:linux,meson-fb { + compatible = "shared-dma-pool"; + reusable; + size = <0x800000>; + alignment = <0x400000>; + alloc-ranges = <0x7f800000 0x800000>; + }; + //don't put other dts in front of logo_reserved + + //di_reserved:linux,di { + // compatible = "amlogic, di-mem"; + /** 10x3133440=30M(0x1e) support 8bit **/ + // size = <0x1e00000>; + //no-map; + //}; + di_cma_reserved:linux,di_cma { + compatible = "shared-dma-pool"; + reusable; + /** 10x3133440=30M(0x1e) support 8bit **/ + size = <0x2000000>; + alignment = <0x400000>; + }; + ion_reserved:linux,ion-dev { + compatible = "shared-dma-pool"; + reusable; + size = <0x7C00000>; + alignment = <0x400000>; + }; + + /* vdin0 CMA pool */ + //vdin0_cma_reserved:linux,vdin0_cma { + // compatible = "shared-dma-pool"; + // linux,phandle = <4>; + // reusable; + /* 1920x1080x2x4 =16+4 M */ + // size = <0x01400000>; + // alignment = <0x400000>; + //}; + /* vdin1 CMA pool */ + vdin1_cma_reserved:linux,vdin1_cma { + compatible = "shared-dma-pool"; + reusable; + /* 1920x1080x2x4 =16 M */ + size = <0x01000000>; + alignment = <0x400000>; + }; + /* POST PROCESS MANAGER */ + ppmgr_reserved:linux,ppmgr { + compatible = "shared-dma-pool"; + size = <0x0>; + }; + + codec_mm_cma:linux,codec_mm_cma { + compatible = "shared-dma-pool"; + reusable; + /* ion_codec_mm max can alloc size 80M*/ + size = <0x13400000>; + alignment = <0x400000>; + linux,contiguous-region; + }; + picdec_cma_reserved:linux,picdec { + compatible = "shared-dma-pool"; + reusable; + size = <0x0>; + alignment = <0x0>; + linux,contiguous-region; + }; + /* codec shared reserved */ + codec_mm_reserved:linux,codec_mm_reserved { + compatible = "amlogic, codec-mm-reserved"; + size = <0x0>; + alignment = <0x100000>; + //no-map; + }; + }; + + wifi{ + compatible = "amlogic, aml_wifi"; + dev_name = "aml_wifi"; + status = "okay"; + interrupt_pin = <&gpio GPIOX_7 GPIO_ACTIVE_HIGH>; + irq_trigger_type = "GPIO_IRQ_LOW"; + dhd_static_buf; + power_on_pin = <&gpio GPIOX_6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_32k_pins>; + pwm_config = <&wifi_pwm_conf>; + }; + + wifi_pwm_conf:wifi_pwm_conf{ + pwm_channel1_conf { + pwms = <&pwm_ef MESON_PWM_0 30040 0>; + duty-cycle = <15020>; + times = <8>; + }; + pwm_channel2_conf { + pwms = <&pwm_ef MESON_PWM_2 30030 0>; + duty-cycle = <15015>; + times = <12>; + }; + }; + + sd_emmc_c: emmc@d0074000 { + status = "okay"; + compatible = "amlogic, meson-mmc-gxm"; + reg = <0xd0074000 0x2000>; + interrupts = <0 218 1>; + pinctrl-names = "emmc_clk_cmd_pins", "emmc_all_pins"; + pinctrl-0 = <&emmc_clk_cmd_pins>; + pinctrl-1 = <&emmc_conf_pull_up &emmc_conf_pull_done>; + clocks = <&clkc CLKID_SD_EMMC_C>, + <&clkc CLKID_SD_EMMC_C_P0_COMP>, + <&clkc CLKID_FCLK_DIV2>; + clock-names = "core", "clkin0", "clkin1"; + + bus-width = <8>; + cap-sd-highspeed; + cap-mmc-highspeed; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + + max-frequency = <200000000>; + non-removable; + disable-wp; + emmc { + pinname = "emmc"; + ocr_avail = <0x200080>; /**VDD voltage 3.3 ~ 3.4 */ + caps = "MMC_CAP_8_BIT_DATA", + "MMC_CAP_MMC_HIGHSPEED", + "MMC_CAP_SD_HIGHSPEED", + "MMC_CAP_NONREMOVABLE", + "MMC_CAP_1_8V_DDR", + "MMC_CAP_HW_RESET", + "MMC_CAP_ERASE", + "MMC_CAP_CMD23"; + caps2 = "MMC_CAP2_HS200", "MMC_CAP2_HS400"; + f_min = <400000>; + f_max = <100000000>; + max_req_size = <0x20000>; /**128KB*/ + gpio_dat3 = <&gpio BOOT_3 GPIO_ACTIVE_HIGH>; + hw_reset = <&gpio BOOT_9 GPIO_ACTIVE_HIGH>; + card_type = <1>; + /* 1:mmc card(include eMMC), + * 2:sd card(include tSD) + */ + }; + }; + + sd_emmc_b:sd@d0072000 { + status = "okay"; + compatible = "amlogic, meson-mmc-gxm"; + reg = <0xd0072000 0x2000>; + interrupts = <0 217 1>; + pinctrl-names = "sd_all_pins", + "sd_clk_cmd_pins", + "sd_1bit_pins", + "sd_clk_cmd_uart_pins", + "sd_1bit_uart_pins", + "sd_to_ao_uart_pins", + "ao_to_sd_uart_pins", + "ao_to_sd_jtag_pins", + "sd_to_ao_jtag_pins"; + pinctrl-0 = <&sd_all_pins>; + pinctrl-1 = <&sd_clk_cmd_pins>; + pinctrl-2 = <&sd_1bit_pins>; + pinctrl-3 = <&sd_to_ao_uart_clr_pins + &sd_clk_cmd_pins &ao_to_sd_uart_pins>; + pinctrl-4 = <&sd_to_ao_uart_clr_pins + &sd_1bit_pins &ao_to_sd_uart_pins>; + pinctrl-5 = <&sd_all_pins &sd_to_ao_uart_pins>; + pinctrl-6 = <&sd_to_ao_uart_clr_pins &ao_to_sd_uart_pins>; + pinctrl-7 = <&sd_to_ao_uart_clr_pins &ao_to_sd_uart_pins>; + pinctrl-8 = <&sd_all_pins &sd_to_ao_uart_pins>; + clocks = <&clkc CLKID_SD_EMMC_B>, + <&clkc CLKID_SD_EMMC_B_P0_COMP>, + <&clkc CLKID_FCLK_DIV2>; + clock-names = "core", "clkin0", "clkin1"; + + bus-width = <4>; + cap-sd-highspeed; + max-frequency = <100000000>; + disable-wp; + sd { + pinname = "sd"; + ocr_avail = <0x200080>; /**VDD voltage 3.3 ~ 3.4 */ + caps = "MMC_CAP_4_BIT_DATA", + "MMC_CAP_MMC_HIGHSPEED", + "MMC_CAP_SD_HIGHSPEED"; + /* "MMC_CAP_UHS_SDR12", + * "MMC_CAP_UHS_SDR25", + * "MMC_CAP_UHS_SDR50", + * "MMC_CAP_UHS_SDR104"; + */ + f_min = <400000>; + f_max = <100000000>; + max_req_size = <0x20000>; /**128KB*/ + gpio_dat3 = <&gpio CARD_4 GPIO_ACTIVE_HIGH>; + jtag_pin = <&gpio CARD_0 GPIO_ACTIVE_HIGH>; + gpio_cd = <&gpio CARD_6 GPIO_ACTIVE_HIGH>; + card_type = <5>; + /* 0:unknown, + * 1:mmc card(include eMMC), + * 2:sd card(include tSD), + * 3:sdio device(ie:sdio-wifi), + * 4:SD combo (IO+mem) card, + * 5:NON sdio device(means sd/mmc card), + * other:reserved + */ + }; + }; + + sd_emmc_a:sdio@d0070000 { + status = "okay"; + compatible = "amlogic, meson-mmc-gxm"; + reg = <0xd0070000 0x2000>; + interrupts = <0 216 4>; + pinctrl-names = "sdio_clk_cmd_pins", "sdio_all_pins"; + pinctrl-0 = <&sdio_clk_cmd_pins>; + pinctrl-1 = <&sdio_all_pins>; + clocks = <&clkc CLKID_SD_EMMC_A>, + <&clkc CLKID_SD_EMMC_A_P0_COMP>, + <&clkc CLKID_FCLK_DIV2>; + clock-names = "core", "clkin0", "clkin1"; + + bus-width = <4>; + cap-sd-highspeed; + cap-mmc-highspeed; + max-frequency = <100000000>; + non-removable; + disable-wp; + sdio { + pinname = "sdio"; + ocr_avail = <0x200080>; /**VDD voltage 3.3 ~ 3.4 */ + caps = "MMC_CAP_4_BIT_DATA", + "MMC_CAP_MMC_HIGHSPEED", + "MMC_CAP_SD_HIGHSPEED", + "MMC_CAP_NONREMOVABLE", + "MMC_CAP_UHS_SDR12", + "MMC_CAP_UHS_SDR25", + "MMC_CAP_UHS_SDR50", + "MMC_CAP_UHS_SDR104", + "MMC_PM_KEEP_POWER", + "MMC_CAP_SDIO_IRQ"; + f_min = <400000>; + f_max = <200000000>; + max_req_size = <0x20000>; /**128KB*/ + card_type = <3>; + /* 3:sdio device(ie:sdio-wifi), + * 4:SD combo (IO+mem) card + */ + }; + }; + mtd_nand{ + compatible = "amlogic, aml_mtd_nand"; + dev_name = "mtdnand"; + status = "disabled"; + reg = <0xd0074800 0x200>; + interrupts = < 0 34 1 >; + pinctrl-names = "nand_rb_mod","nand_norb_mod", "nand_cs_only"; + pinctrl-0 = <&all_nand_pins>; + pinctrl-1 = <&all_nand_pins>; + pinctrl-2 = <&nand_cs_pins>; + device_id = <0>; + plat-names = "nandboot","nandnormal"; + plat-num = <2>; + plat-part-0 = <&nandboot>; + plat-part-1 = <&nandnormal>; + nandboot: nandboot{ + enable_pad ="ce0"; + busy_pad = "rb0"; + timming_mode = "mode5"; + bch_mode = "bch60_1k"; + t_rea = <20>; + t_rhoh = <15>; + chip_num = <1>; + part_num = <0>; + rb_detect = <1>; + }; + nandnormal: nandnormal{ + enable_pad ="ce0","ce1"; + busy_pad = "rb0","rb1"; + timming_mode = "mode5"; + bch_mode = "bch60_1k"; + plane_mode = "twoplane"; + t_rea = <20>; + t_rhoh = <15>; + chip_num = <2>; + part_num = <3>; + partition = <&nand_partitions>; + rb_detect = <1>; + }; + nand_partitions:nand_partition{ + logo{ + offset=<0x0 0x0>; + size=<0x0 0x200000>; + }; + recovery{ + offset=<0x0 0x0>; + size=<0x0 0x1000000>; + }; + boot{ + offset=<0x0 0x0>; + size=<0x0 0xC00000>; + }; + system{ + offset=<0x0 0x0>; + size=<0x0 0xDC40000>; + }; + data{ + offset=<0xffffffff 0xffffffff>; + size=<0x0 0x0>; + }; + }; + }; + + ethmac: ethernet@0xc9410000 { + compatible = "amlogic, gxbb-eth-dwmac"; + reg = <0xc9410000 0x10000 + 0xc8834540 0x8 + 0xc8834558 0xc>; + interrupts = <0 8 1>; + pinctrl-names = "external_eth_pins"; + pinctrl-0 = <&external_eth_pins>; + rst_pin-gpios = <&gpio GPIOZ_14 0>; + GPIOZ4_pin-gpios = <&gpio GPIOZ_4 0>; + GPIOZ5_pin-gpios = <&gpio GPIOZ_5 0>; + mc_val_internal_phy = <0x1800>; + mc_val_external_phy = <0x1621>; + cali_val = <0x20000>; + interrupt-names = "macirq"; + clocks = <&clkc CLKID_ETH>; + clock-names = "ethclk81"; + internal_phy=<0>; + }; + + codec_io { + compatible = "amlogic, codec_io"; + #address-cells=<1>; + #size-cells=<1>; + ranges; + io_cbus_base{ + reg = <0xC1100000 0x100000>; + }; + io_dos_base{ + reg = <0xc8820000 0x10000>; + }; + io_hiubus_base{ + reg = <0xc883c000 0x2000>; + }; + io_aobus_base{ + reg = <0xc8100000 0x100000>; + }; + io_vcbus_base{ + reg = <0xd0100000 0x40000>; + }; + io_dmc_base{ + reg = <0xc8838000 0x400>; + }; + }; + + codec_mm { + compatible = "amlogic, codec, mm"; + memory-region = <&codec_mm_cma &codec_mm_reserved>; + dev_name = "codec_mm"; + status = "okay"; + }; + + canvas{ + compatible = "amlogic, meson, canvas"; + dev_name = "amlogic-canvas"; + status = "ok"; + reg = <0xc8838000 0x400>; + }; + + mesonstream { + compatible = "amlogic, codec, streambuf"; + dev_name = "mesonstream"; + status = "okay"; + clocks = <&clkc CLKID_DOS_PARSER + &clkc CLKID_DEMUX + &clkc CLKID_DOS + &clkc CLKID_CLK81 + &clkc CLKID_VDEC_MUX + &clkc CLKID_HCODEC_MUX + &clkc CLKID_HEVC_MUX>; + clock-names = "parser_top", + "demux", + "vdec", + "clk_81", + "clk_vdec_mux", + "clk_hcodec_mux", + "clk_hevc_mux"; + }; + + vdec { + compatible = "amlogic, vdec"; + dev_name = "vdec.0"; + status = "okay"; + interrupts = <0 3 1 + 0 23 1 + 0 32 1 + 0 43 1 + 0 44 1 + 0 45 1>; + interrupt-names = "vsync", + "demux", + "parser", + "mailbox_0", + "mailbox_1", + "mailbox_2"; + }; + + aml_sensor0: aml-sensor@0 { + compatible = "amlogic, aml-thermal"; + device_name = "thermal"; + #thermal-sensor-cells = <1>; + cooling_devices { + cpufreq_cool_cluster0 { + min_state = <1000000>; + dyn_coeff = <140>; + cluster_id = <0>; + node_name = "cpufreq_cool0"; + device_type = "cpufreq"; + }; + cpufreq_cool_cluster1 { + min_state = <500000>; + dyn_coeff = <140>; + cluster_id = <1>; + node_name = "cpufreq_cool1"; + device_type = "cpufreq"; + }; + cpucore_cool_cluster0 { + min_state = <1>; + dyn_coeff = <0>; + cluster_id = <0>; + node_name = "cpucore_cool0"; + device_type = "cpucore"; + }; + cpucore_cool_cluster1 { + min_state = <1>; + dyn_coeff = <0>; + cluster_id = <1>; + node_name = "cpucore_cool1"; + device_type = "cpucore"; + }; + gpufreq_cool { + min_state = <400>; + dyn_coeff = <437>; + cluster_id = <0>; + node_name = "gpufreq_cool0"; + device_type = "gpufreq"; + }; + gpucore_cool { + min_state = <1>; + dyn_coeff = <0>; + cluster_id = <0>; + node_name = "gpucore_cool0"; + device_type = "gpucore"; + }; + }; + cpufreq_cool0:cpufreq_cool0 { + #cooling-cells = <2>; /* min followed by max */ + }; + cpufreq_cool1:cpufreq_cool1 { + #cooling-cells = <2>; /* min followed by max */ + }; + cpucore_cool0:cpucore_cool0 { + #cooling-cells = <2>; /* min followed by max */ + }; + cpucore_cool1:cpucore_cool1 { + #cooling-cells = <2>; /* min followed by max */ + }; + gpufreq_cool0:gpufreq_cool0 { + #cooling-cells = <2>; /* min followed by max */ + }; + gpucore_cool0:gpucore_cool0 { + #cooling-cells = <2>; /* min followed by max */ + }; + }; + thermal-zones { + soc_thermal { + polling-delay = <1000>; + polling-delay-passive = <100>; + sustainable-power = <2450>; + + thermal-sensors = <&aml_sensor0 3>; + + trips { + switch_on: trip-point@0 { + temperature = <70000>; + hysteresis = <1000>; + type = "passive"; + }; + control: trip-point@1 { + temperature = <80000>; + hysteresis = <1000>; + type = "passive"; + }; + hot: trip-point@2 { + temperature = <85000>; + hysteresis = <5000>; + type = "hot"; + }; + critical: trip-point@3 { + temperature = <260000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + + cooling-maps { + cpufreq_cooling_map0 { + trip = <&control>; + cooling-device = <&cpufreq_cool0 0 4>; + contribution = <1024>; + }; + cpufreq_cooling_map1 { + trip = <&control>; + cooling-device = <&cpufreq_cool1 0 4>; + contribution = <1024>; + }; + cpucore_cooling_map0 { + trip = <&control>; + cooling-device = <&cpucore_cool0 0 3>; + contribution = <1024>; + }; + cpucore_cooling_map1 { + trip = <&control>; + cooling-device = <&cpucore_cool1 0 3>; + contribution = <1024>; + }; + gpufreq_cooling_map { + trip = <&control>; + cooling-device = <&gpufreq_cool0 0 4>; + contribution = <1024>; + }; + gpucore_cooling_map { + trip = <&control>; + cooling-device = <&gpucore_cool0 0 2>; + contribution = <1024>; + }; + }; + }; + }; + + dwc3: dwc3@c9000000 { + compatible = "synopsys, dwc3"; + reg = <0xc9000000 0x100000>; + interrupts = <0 30 4>; + usb-phy = <&usb2_phy>, <&usb3_phy>; + cpu-type = "gxl"; + clock-src = "usb3.0"; + }; + + usb2_phy: usb2phy@d0078000 { + compatible = "amlogic, amlogic-new-usb2"; + portnum = <3>; + reg = <0xd0078000 0x80 + 0xc1104408 0x4>; + }; + + usb3_phy: usb3phy@d0078080 { + compatible = "amlogic, amlogic-new-usb3"; + portnum = <0>; + reg = <0xd0078080 0x20>; + interrupts = <0 16 4>; + otg = <1>; + gpio-vbus-power = "GPIOAO_5"; + gpios = <&gpio_ao GPIOAO_5 GPIO_ACTIVE_HIGH>; + }; + + dwc2_a { + compatible = "amlogic, dwc2"; + device_name = "dwc2_a"; + reg = <0xc9100000 0x40000>; + status = "okay"; + interrupts = <0 31 4>; + pl-periph-id = <0>; /** lm name */ + clock-src = "usb0"; /** clock src */ + port-id = <0>; /** ref to mach/usb.h */ + port-type = <2>; /** 0: otg, 1: host, 2: slave */ + port-speed = <0>; /** 0: default, high, 1: full */ + port-config = <0>; /** 0: default */ + port-dma = <0>; /** 0: default ... 6: disable*/ + port-id-mode = <0>; /** 0: hardware, 1: sw_host, 2: sw_slave*/ + usb-fifo = <728>; + cpu-type = "gxl"; + controller-type = <3>; /** 0: normal,1:host,2:device,3:otg*/ + phy-reg = <0xd0078000>; + phy-reg-size = <0xa0>; + clocks = <&clkc CLKID_USB_GENERAL + &clkc CLKID_USB1_TO_DDR + &clkc CLKID_USB1>; + clock-names = "usb_general", + "usb1", + "usb1_to_ddr"; + }; + + meson-amvideom { + compatible = "amlogic, amvideom"; + dev_name = "amvideom"; + status = "okay"; + interrupts = <0 3 1>; + interrupt-names = "vsync"; + }; + + vout { + compatible = "amlogic, vout"; + dev_name = "vout"; + status = "okay"; + fr_auto_policy = <0>; + }; + + cvbsout { + compatible = "amlogic, cvbsout-gxm"; + dev_name = "cvbsout"; + status = "okay"; + clocks = <&clkc CLKID_VCLK2_ENCI + &clkc CLKID_VCLK2_VENCI0 + &clkc CLKID_VCLK2_VENCI1 + &clkc CLKID_DAC_CLK>; + clock-names = "venci_top_gate", + "venci_0_gate", + "venci_1_gate", + "vdac_clk_gate"; + + /* performance: reg_address, reg_value */ + performance = <0x1bf0 0x9 + 0x1b56 0x343 + 0x1b12 0x8080 + 0x1b05 0xfd + 0x1c59 0xf752 + 0xffff 0x0>; /* ending flag */ + }; + + amhdmitx: amhdmitx{ + compatible = "amlogic, amhdmitx"; + dev_name = "amhdmitx"; + status = "okay"; + vend-data = <&vend_data>; + pinctrl-names="hdmitx_hpd", "hdmitx_ddc"; + pinctrl-0=<&hdmitx_hpd>; + pinctrl-1=<&hdmitx_ddc>; + /* HPD, 57 + 32 = 89; CEC, 151 + 32 = 183*/ + interrupts = <0 57 1>; + interrupt-names = "hdmitx_hpd"; + /* 0:M8B 1:GXBB 2:GXTVBB 3:GXL 4:GXM + * 5:TXL 6:TXLX 7:AXG 8:GXLX 9:TXHD + */ + ic_type = <4>; + vend_data: vend_data{ /* Should modified by Customer */ + vendor_name = "Amlogic"; /* Max Chars: 8 */ + /* standards.ieee.org/develop/regauth/oui/oui.txt */ + vendor_id = <0x000000>; + product_desc = "MBox Meson Ref"; /* Max Chars: 16 */ + }; + }; + + aocec: aocec{ + compatible = "amlogic, amlogic-aocec"; + device_name = "aocec"; + status = "okay"; + vendor_id = <0x000000>; + cec_osd_string = "MBox"; /* Max Chars: 14 */ + cec_version = <6>; /* 5: 1.4, 6: 2.0 */ + port_num = <1>; + arc_port_mask = <0x0>; + interrupts = <0 199 1>; + interrupt-names = "hdmi_aocec"; + pinctrl-names = "default"; + pinctrl-0=<&hdmitx_aocec>; + reg = <0xc810023c 0x4 + 0xc8100000 0x200>; + reg-names = "ao_exit","ao"; + }; + + sysled { + compatible = "amlogic, sysled"; + dev_name = "sysled"; + status = "disabled"; + led_gpio = <&gpio GPIODV_24 GPIO_ACTIVE_HIGH>; + led_active_low = <1>; + }; + + meson-fb { + compatible = "amlogic, meson-gxm"; + memory-region = <&logo_reserved>; + dev_name = "meson-fb"; + status = "okay"; + interrupts = <0 3 1 + 0 89 1>; + interrupt-names = "viu-vsync", "rdma"; + mem_size = <0x00800000 0x01851000 0x00100000>; + /* uboot logo,fb0/fb1 memory size,if afbcd fb0=0x01851000*/ + display_mode_default = "1080p60hz"; + scale_mode = <1>; + /** 0:VPU free scale 1:OSD free scale 2:OSD super scale */ + display_size_default = <1920 1080 1920 3240 32>; + /*1920*1080*4*3 = 0x17BB000*/ + logo_addr = "0x7f800000"; + }; + ge2d { + compatible = "amlogic, ge2d-gxm"; + dev_name = "ge2d"; + status = "okay"; + interrupts = <0 150 1>; + interrupt-names = "ge2d"; + clocks = <&clkc CLKID_VAPB_MUX>, + <&clkc CLKID_G2D>, + <&clkc CLKID_GE2D_GATE>; + clock-names = "clk_vapb_0", + "clk_ge2d", + "clk_ge2d_gate"; + }; + + + /* AUDIO MESON DEVICES */ + i2s_dai: I2S { + #sound-dai-cells = <0>; + compatible = "amlogic, aml-i2s-dai"; + clocks = + <&clkc CLKID_MPLL2>, + <&clkc CLKID_AMCLK_COMP>, + <&clkc CLKID_AIU_GLUE>, + <&clkc CLKID_IEC958>, + <&clkc CLKID_I2S_OUT>, + <&clkc CLKID_AMCLK>, + <&clkc CLKID_AIFIFO2>, + <&clkc CLKID_MIXER>, + <&clkc CLKID_MIXER_IFACE>, + <&clkc CLKID_ADC>, + <&clkc CLKID_AIU_TOP>, + <&clkc CLKID_AOCLK_GATE>, + <&clkc CLKID_I2S_SPDIF>; + clock-names = + "mpll", + "mclk", + "top_glue", + "aud_buf", + "i2s_out", + "amclk_measure", + "aififo2", + "aud_mixer", + "mixer_reg", + "adc", + "top_level", + "aoclk", + "aud_in"; + i2s_pos_sync = <0>; + /*DMIC;*/ /* I2s Mic or Dmic, default for I2S mic */ + }; + dmic:snd_dmic { + #sound-dai-cells = <0>; + compatible = "aml, aml_snd_dmic"; + reg = <0xd0042000 0x2000>; + status = "okay"; + resets = < + &clkc CLKID_PDM_GATE + >; + reset-names = "pdm"; + pinctrl-names = "audio_dmic"; + pinctrl-0 = <&aml_dmic_pins>; + clocks = <&clkc CLKID_PDM_COMP>, + <&clkc CLKID_AMCLK_COMP>; + clock-names = "pdm", "mclk"; + }; + spdif_dai: SPDIF { + #sound-dai-cells = <0>; + compatible = "amlogic, aml-spdif-dai"; + clocks = + <&clkc CLKID_MPLL1>, + <&clkc CLKID_I958_COMP>, + <&clkc CLKID_AMCLK_COMP>, + <&clkc CLKID_I958_COMP_SPDIF>, + <&clkc CLKID_CLK81>, + <&clkc CLKID_IEC958>, + <&clkc CLKID_IEC958_GATE>; + clock-names = + "mpll1", + "i958", + "mclk", + "spdif", + "clk_81", + "iec958", + "iec958_amclk"; + }; + pcm_dai: PCM { + #sound-dai-cells = <0>; + compatible = "amlogic, aml-pcm-dai"; + pinctrl-names = "audio_pcm"; + pinctrl-0 = <&audio_pcm_pins>; + clocks = + <&clkc CLKID_MPLL0>, + <&clkc CLKID_PCM_MCLK_COMP>, + <&clkc CLKID_PCM_SCLK_GATE>; + clock-names = + "mpll0", + "pcm_mclk", + "pcm_sclk"; + pcm_mode = <1>; /* 0=slave mode, 1=master mode */ + }; + i2s_plat: i2s_platform { + compatible = "amlogic, aml-i2s"; + interrupts = <0 29 1>; + }; + pcm_plat: pcm_platform { + compatible = "amlogic, aml-pcm"; + }; + spdif_codec: spdif_codec{ + #sound-dai-cells = <0>; + compatible = "amlogic, aml-spdif-codec"; + pinctrl-names = "audio_spdif"; + pinctrl-0 = <&audio_spdif_pins>; + }; + pcm_codec: pcm_codec{ + #sound-dai-cells = <0>; + compatible = "amlogic, pcm2BT-codec"; + }; + /* endof AUDIO MESON DEVICES */ + + /* AUDIO board specific */ + dummy_codec:dummy{ + #sound-dai-cells = <0>; + compatible = "amlogic, aml_dummy_codec"; + status = "disable"; + }; + amlogic_codec:t9015{ + #sound-dai-cells = <0>; + compatible = "amlogic, aml_codec_T9015"; + reg = <0xc8832000 0x14>; + status = "okay"; + }; + aml_sound_meson { + compatible = "aml, meson-snd-card"; + status = "okay"; + aml-sound-card,format = "i2s"; + aml_sound_card,name = "AML-MESONAUDIO"; + aml,audio-routing = + "Ext Spk","LOUTL", + "Ext Spk","LOUTR"; + + mute_gpio-gpios = <&gpio GPIOH_5 0>; + mute_inv; + hp_disable; + hp_paraments = <800 300 0 5 1>; + pinctrl-names = "audio_i2s"; + pinctrl-0 = <&audio_i2s_pins>; + cpu_list = <&cpudai0 &cpudai1 &cpudai2>; + codec_list = <&codec0 &codec1 &codec2>; + plat_list = <&i2s_plat &i2s_plat &pcm_plat>; + cpudai0: cpudai0 { + sound-dai = <&i2s_dai>; + }; + cpudai1: cpudai1 { + sound-dai = <&spdif_dai>; + }; + cpudai2: cpudai2 { + sound-dai = <&pcm_dai>; + }; + codec0: codec0 { + sound-dai = <&amlogic_codec>; + }; + codec1: codec1 { + sound-dai = <&spdif_codec>; + }; + codec2: codec2 { + sound-dai = <&pcm_codec>; + }; + }; + /* END OF AUDIO board specific */ + + rdma{ + compatible = "amlogic, meson, rdma"; + dev_name = "amlogic-rdma"; + status = "ok"; + interrupts = <0 89 1>; + interrupt-names = "rdma"; + }; + + amvenc_avc{ + compatible = "amlogic, amvenc_avc"; + dev_name = "amvenc_avc"; + status = "okay"; + interrupts = <0 45 1>; + interrupt-names = "mailbox_2"; + }; + + hevc_enc{ + compatible = "cnm, HevcEnc"; + dev_name = "HevcEnc"; + status = "okay"; + interrupts = <0 187 1>; + interrupt-names = "wave420l_irq"; + #address-cells=<1>; + #size-cells=<1>; + ranges; + io_reg_base{ + reg = <0xc8810000 0x4000>; + }; + }; + + picdec { + compatible = "amlogic, picdec"; + memory-region = <&picdec_cma_reserved>; + dev_name = "picdec"; + status = "okay"; + }; + + ppmgr { + compatible = "amlogic, ppmgr"; + memory-region = <&ppmgr_reserved>; + dev_name = "ppmgr"; + status = "okay"; + }; + + deinterlace { + compatible = "amlogic, deinterlace"; + status = "okay"; + flag_cma = <1>;/*0:use reserved;1:use cma*/ + //memory-region = <&di_reserved>; + memory-region = <&di_cma_reserved>; + interrupts = <0 46 1 0 6 1>; + interrupt-names = "de_irq", "timerc"; + /* + * nr_size(byte) = 1920*544*2(yuv422 8bit) | + * 1920*544*2*12/8(yuv422 10bit) + * | 1920*544*2*10/8(yuv422 10bit full pack mode) + */ + /* mtn_size(byte) = 1920*544/2 */ + /* count_size(byte) = 1920*544/2 */ + buffer-size = <3133440>; + hw-version = <2>; + }; + + ionvideo { + compatible = "amlogic, ionvideo"; + dev_name = "ionvideo"; + status = "okay"; + }; + + amlvideo { + compatible = "amlogic, amlvideo"; + dev_name = "amlvideo"; + status = "okay"; + }; + + amlvideo2_0 { + compatible = "amlogic, amlvideo2"; + dev_name = "amlvideo2"; + status = "okay"; + amlvideo2_id = <0>; + cma_mode = <1>; + }; + + amlvideo2_1 { + compatible = "amlogic, amlvideo2"; + dev_name = "amlvideo2"; + status = "okay"; + amlvideo2_id = <1>; + cma_mode = <1>; + }; + + /*if you want to use vdin just modify status to "ok"*/ + vdin0 { + compatible = "amlogic, vdin"; + /*memory-region = <&vdin0_cma_reserved>;*/ + dev_name = "vdin0"; + status = "ok"; + reserve-iomap = "true"; + flag_cma = <1>;/*1:share with codec_mm;2:cma alone*/ + /*MByte, if 10bit disable: 64M(YUV422), + *if 10bit enable: 64*1.5 = 96M(YUV422) + *if support 4K2K-YUV444-10bit-WR:3840*2160*4*4 ~= 128M + *if support 4K2K-YUV422-10bit-wr:3840*2160*3*4 ~= 96M + *if support 4K2K-YUV422-8BIT-WR:3840*2160*2*4 ~= 64M + *if support 1080p-YUV422-8BIT-WR:1920*1080*2*4 ~= 16M + */ + cma_size = <16>; + interrupts = <0 83 1>; + rdma-irq = <2>; + /*clocks = <&clkc CLKID_FCLK_DIV5>, + * <&clkc CLK_VDIN_MEAS_CLK>; + *clock-names = "fclk_div5", "cts_vdin_meas_clk"; + */ + vdin_id = <0>; + /*vdin write mem color depth support: + *bit0:support 8bit + *bit1:support 9bit + *bit2:support 10bit + *bit3:support 12bit + *bit4:support yuv422 10bit full pack mode (from txl new add) + */ + tv_bit_mode = <1>; + }; + vdin1 { + compatible = "amlogic, vdin"; + memory-region = <&vdin1_cma_reserved>; + dev_name = "vdin1"; + status = "ok"; + reserve-iomap = "true"; + flag_cma = <0>;/*1:share with codec_mm;0:cma alone*/ + interrupts = <0 85 1>; + rdma-irq = <4>; + /*clocks = <&clock CLK_FPLL_DIV5>, + * <&clock CLK_VDIN_MEAS_CLK>; + *clock-names = "fclk_div5", "cts_vdin_meas_clk"; + */ + vdin_id = <1>; + /*vdin write mem color depth support: + *bit0:support 8bit + *bit1:support 9bit + *bit2:support 10bit + *bit3:support 12bit + */ + tv_bit_mode = <1>; + }; + + amlvecm { + compatible = "amlogic, vecm"; + dev_name = "aml_vecm"; + status = "okay"; + gamma_en = <0>;/*1:enabel ;0:disable*/ + wb_en = <0>;/*1:enabel ;0:disable*/ + cm_en = <0>;/*1:enabel ;0:disable*/ + /*1:enabel osd lut 100 table;0:disable*/ + cfg_en_osd_100 = <1>; + /*0: 709/601 1: bt2020*/ + tx_op_color_primary = <0>; + }; + amdolby_vision { + compatible = "amlogic, dolby_vision_gxm"; + dev_name = "aml_amdolby_vision_driver"; + status = "okay"; + tv_mode = <0>;/*1:enabel ;0:disable*/ + }; + unifykey{ + compatible = "amlogic, unifykey"; + status = "ok"; + + unifykey-num = <15>; + unifykey-index-0 = <&keysn_0>; + unifykey-index-1 = <&keysn_1>; + unifykey-index-2 = <&keysn_2>; + unifykey-index-3 = <&keysn_3>; + unifykey-index-4 = <&keysn_4>; + unifykey-index-5 = <&keysn_5>; + unifykey-index-6 = <&keysn_6>; + unifykey-index-7 = <&keysn_7>; + unifykey-index-8 = <&keysn_8>; + unifykey-index-9 = <&keysn_9>; + unifykey-index-10= <&keysn_10>; + unifykey-index-11= <&keysn_11>; + unifykey-index-12= <&keysn_12>; + unifykey-index-13= <&keysn_13>; + unifykey-index-14= <&keysn_14>; + + keysn_0: key_0{ + key-name = "usid"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_1:key_1{ + key-name = "mac"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_2:key_2{ + key-name = "hdcp"; + key-device = "secure"; + key-type = "sha1"; + key-permit = "read","write","del"; + }; + keysn_3:key_3{ + key-name = "secure_boot_set"; + key-device = "efuse"; + key-permit = "write"; + }; + keysn_4:key_4{ + key-name = "mac_bt"; + key-device = "normal"; + key-permit = "read","write","del"; + key-type = "mac"; + }; + keysn_5:key_5{ + key-name = "mac_wifi"; + key-device = "normal"; + key-permit = "read","write","del"; + key-type = "mac"; + }; + keysn_6:key_6{ + key-name = "hdcp2_tx"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_7:key_7{ + key-name = "hdcp2_rx"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_8:key_8{ + key-name = "widevinekeybox"; + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_9:key_9{ + key-name = "deviceid"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_10:key_10{ + key-name = "hdcp22_fw_private"; + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_11:key_11{ + key-name = "PlayReadykeybox25"; + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_12:key_12{ + key-name = "prpubkeybox";// PlayReady + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_13:key_13{ + key-name = "prprivkeybox";// PlayReady + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_14:key_14{ + key-name = "attestationkeybox";// attestation key + key-device = "secure"; + key-permit = "read","write","del"; + }; + };//End unifykey +}; +&efuse { + status = "ok"; +}; + +&pwm_ef { + status = "okay"; +}; + +&audio_data{ + status = "okay"; +}; +&i2c1 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/amlogic/gxm_q200_2g_buildroot.dts b/arch/arm/boot/dts/amlogic/gxm_q200_2g_buildroot.dts new file mode 100644 index 000000000000..acb411acd524 --- /dev/null +++ b/arch/arm/boot/dts/amlogic/gxm_q200_2g_buildroot.dts @@ -0,0 +1,1289 @@ +/* + * arch/arm/boot/dts/amlogic/gxm_q200_2g_buildroot.dts + * + * Copyright (C) 2017 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +/dts-v1/; + +#include "mesongxm.dtsi" +/ { + model = "Amlogic"; + amlogic-dt-id = "gxm_q200_2g"; + compatible = "amlogic, Gxm"; + interrupt-parent = <&gic>; + #address-cells = <1>; + #size-cells = <1>; + + aliases { + serial0 = &uart_AO; + serial1 = &uart_A; + serial2 = &uart_B; + serial3 = &uart_C; + serial4 = &uart_AO_B; + }; + + ion_dev { + compatible = "amlogic, ion_dev"; + memory-region = <&ion_reserved>; + }; + + memory@00000000 { + device_type = "memory"; + linux,usable-memory = <0x0100000 0x7ff00000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + /* global autoconfigured region for contiguous allocations */ + ramoops@0x07400000 { + compatible = "ramoops"; + reg = <0x07400000 0x00100000>; + record-size = <0x8000>; + console-size = <0x8000>; + ftrace-size = <0x0>; + pmsg-size = <0x8000>; + }; + + secmon_reserved:linux,secmon { + compatible = "shared-dma-pool"; + reusable; + size = <0x400000>; + alignment = <0x400000>; + alloc-ranges = <0x05000000 0x400000>; + }; + secos_reserved:linux,secos { + status = "disable"; + compatible = "amlogic, aml_secos_memory"; + reg = <0x05300000 0x2000000>; + no-map; + }; + ion_reserved:linux,ion-dev { + compatible = "shared-dma-pool"; + reusable; + size = <0x8000000>; + alignment = <0x400000>; + }; + + //di_reserved:linux,di { + // compatible = "amlogic, di-mem"; + /** 10x3133440=30M(0x1e) support 8bit **/ + // size = <0x1e00000>; + //no-map; + //}; + di_cma_reserved:linux,di_cma { + compatible = "shared-dma-pool"; + reusable; + /** 10x3133440=30M(0x1e) support 8bit **/ + size = <0x2000000>; + alignment = <0x400000>; + }; + + /* vdin0 CMA pool */ + //vdin0_cma_reserved:linux,vdin0_cma { + // compatible = "shared-dma-pool"; + // linux,phandle = <4>; + // reusable; + /* 1920x1080x2x4 =16+4 M */ + // size = <0x01400000>; + // alignment = <0x400000>; + //}; + /* vdin1 CMA pool */ + vdin1_cma_reserved:linux,vdin1_cma { + compatible = "shared-dma-pool"; + reusable; + /* 1920x1080x2x4 =16 M */ + size = <0x01000000>; + alignment = <0x400000>; + }; + /* POST PROCESS MANAGER */ + ppmgr_reserved:linux,ppmgr { + compatible = "shared-dma-pool"; + size = <0x0>; + }; + + codec_mm_cma:linux,codec_mm_cma { + compatible = "shared-dma-pool"; + reusable; + /* ion_codec_mm max can alloc size 80M*/ + size = <0x10400000>; + alignment = <0x400000>; + linux,contiguous-region; + }; + picdec_cma_reserved:linux,picdec { + compatible = "shared-dma-pool"; + reusable; + size = <0x0>; + alignment = <0x0>; + linux,contiguous-region; + }; + /* codec shared reserved */ + codec_mm_reserved:linux,codec_mm_reserved { + compatible = "amlogic, codec-mm-reserved"; + size = <0x0>; + alignment = <0x100000>; + //no-map; + }; + }; + + wifi{ + compatible = "amlogic, aml_wifi"; + dev_name = "aml_wifi"; + status = "okay"; + interrupt_pin = <&gpio GPIOX_7 GPIO_ACTIVE_HIGH>; + irq_trigger_type = "GPIO_IRQ_LOW"; + dhd_static_buf; + power_on_pin = <&gpio GPIOX_6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_32k_pins>; + pwm_config = <&wifi_pwm_conf>; + }; + + wifi_pwm_conf:wifi_pwm_conf{ + pwm_channel1_conf { + pwms = <&pwm_ef MESON_PWM_0 30040 0>; + duty-cycle = <15020>; + times = <8>; + }; + pwm_channel2_conf { + pwms = <&pwm_ef MESON_PWM_2 30030 0>; + duty-cycle = <15015>; + times = <12>; + }; + }; + + sd_emmc_c: emmc@d0074000 { + status = "okay"; + compatible = "amlogic, meson-mmc-gxm"; + reg = <0xd0074000 0x2000>; + interrupts = <0 218 1>; + pinctrl-names = "emmc_clk_cmd_pins", "emmc_all_pins"; + pinctrl-0 = <&emmc_clk_cmd_pins>; + pinctrl-1 = <&emmc_conf_pull_up &emmc_conf_pull_done>; + clocks = <&clkc CLKID_SD_EMMC_C>, + <&clkc CLKID_SD_EMMC_C_P0_COMP>, + <&clkc CLKID_FCLK_DIV2>; + clock-names = "core", "clkin0", "clkin1"; + + bus-width = <8>; + cap-sd-highspeed; + cap-mmc-highspeed; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + + max-frequency = <200000000>; + non-removable; + disable-wp; + emmc { + status = "disabled"; + pinname = "emmc"; + ocr_avail = <0x200080>; /**VDD voltage 3.3 ~ 3.4 */ + caps = "MMC_CAP_8_BIT_DATA", + "MMC_CAP_MMC_HIGHSPEED", + "MMC_CAP_SD_HIGHSPEED", + "MMC_CAP_NONREMOVABLE", + "MMC_CAP_1_8V_DDR", + "MMC_CAP_HW_RESET", + "MMC_CAP_ERASE", + "MMC_CAP_CMD23"; + caps2 = "MMC_CAP2_HS200", "MMC_CAP2_HS400"; + f_min = <400000>; + f_max = <100000000>; + max_req_size = <0x20000>; /**128KB*/ + gpio_dat3 = <&gpio BOOT_3 GPIO_ACTIVE_HIGH>; + hw_reset = <&gpio BOOT_9 GPIO_ACTIVE_HIGH>; + card_type = <1>; + /* 1:mmc card(include eMMC), + * 2:sd card(include tSD) + */ + }; + }; + + sd_emmc_b:sd@d0072000 { + status = "okay"; + compatible = "amlogic, meson-mmc-gxm"; + reg = <0xd0072000 0x2000>; + interrupts = <0 217 1>; + pinctrl-names = "sd_all_pins", + "sd_clk_cmd_pins", + "sd_1bit_pins", + "sd_clk_cmd_uart_pins", + "sd_1bit_uart_pins", + "sd_to_ao_uart_pins", + "ao_to_sd_uart_pins", + "ao_to_sd_jtag_pins", + "sd_to_ao_jtag_pins"; + pinctrl-0 = <&sd_all_pins>; + pinctrl-1 = <&sd_clk_cmd_pins>; + pinctrl-2 = <&sd_1bit_pins>; + pinctrl-3 = <&sd_to_ao_uart_clr_pins + &sd_clk_cmd_pins &ao_to_sd_uart_pins>; + pinctrl-4 = <&sd_to_ao_uart_clr_pins + &sd_1bit_pins &ao_to_sd_uart_pins>; + pinctrl-5 = <&sd_all_pins &sd_to_ao_uart_pins>; + pinctrl-6 = <&sd_to_ao_uart_clr_pins &ao_to_sd_uart_pins>; + pinctrl-7 = <&sd_to_ao_uart_clr_pins &ao_to_sd_uart_pins>; + pinctrl-8 = <&sd_all_pins &sd_to_ao_uart_pins>; + clocks = <&clkc CLKID_SD_EMMC_B>, + <&clkc CLKID_SD_EMMC_B_P0_COMP>, + <&clkc CLKID_FCLK_DIV2>; + clock-names = "core", "clkin0", "clkin1"; + + bus-width = <4>; + cap-sd-highspeed; + max-frequency = <100000000>; + disable-wp; + sd { + status = "disabled"; + pinname = "sd"; + ocr_avail = <0x200080>; /**VDD voltage 3.3 ~ 3.4 */ + caps = "MMC_CAP_4_BIT_DATA", + "MMC_CAP_MMC_HIGHSPEED", + "MMC_CAP_SD_HIGHSPEED"; + /* "MMC_CAP_UHS_SDR12", + * "MMC_CAP_UHS_SDR25", + * "MMC_CAP_UHS_SDR50", + * "MMC_CAP_UHS_SDR104"; + */ + f_min = <400000>; + f_max = <100000000>; + max_req_size = <0x20000>; /**128KB*/ + gpio_dat3 = <&gpio CARD_4 GPIO_ACTIVE_HIGH>; + jtag_pin = <&gpio CARD_0 GPIO_ACTIVE_HIGH>; + gpio_cd = <&gpio CARD_6 GPIO_ACTIVE_HIGH>; + card_type = <5>; + /* 0:unknown, + * 1:mmc card(include eMMC), + * 2:sd card(include tSD), + * 3:sdio device(ie:sdio-wifi), + * 4:SD combo (IO+mem) card, + * 5:NON sdio device(means sd/mmc card), + * other:reserved + */ + }; + }; + + sd_emmc_a:sdio@d0070000 { + status = "okay"; + compatible = "amlogic, meson-mmc-gxm"; + reg = <0xd0070000 0x2000>; + interrupts = <0 216 4>; + pinctrl-names = "sdio_clk_cmd_pins", "sdio_all_pins"; + pinctrl-0 = <&sdio_clk_cmd_pins>; + pinctrl-1 = <&sdio_all_pins>; + clocks = <&clkc CLKID_SD_EMMC_A>, + <&clkc CLKID_SD_EMMC_A_P0_COMP>, + <&clkc CLKID_FCLK_DIV2>; + clock-names = "core", "clkin0", "clkin1"; + + bus-width = <4>; + cap-sd-highspeed; + cap-mmc-highspeed; + max-frequency = <100000000>; + non-removable; + disable-wp; + sdio { + status = "disabled"; + pinname = "sdio"; + ocr_avail = <0x200080>; /**VDD voltage 3.3 ~ 3.4 */ + caps = "MMC_CAP_4_BIT_DATA", + "MMC_CAP_MMC_HIGHSPEED", + "MMC_CAP_SD_HIGHSPEED", + "MMC_CAP_NONREMOVABLE", + "MMC_CAP_UHS_SDR12", + "MMC_CAP_UHS_SDR25", + "MMC_CAP_UHS_SDR50", + "MMC_CAP_UHS_SDR104", + "MMC_PM_KEEP_POWER", + "MMC_CAP_SDIO_IRQ"; + f_min = <400000>; + f_max = <200000000>; + max_req_size = <0x20000>; /**128KB*/ + card_type = <3>; + /* 3:sdio device(ie:sdio-wifi), + * 4:SD combo (IO+mem) card + */ + }; + }; + mtd_nand{ + compatible = "amlogic, aml_mtd_nand"; + dev_name = "mtdnand"; + status = "disabled"; + reg = <0xd0074800 0x200>; + interrupts = < 0 34 1 >; + pinctrl-names = "nand_rb_mod","nand_norb_mod", "nand_cs_only"; + pinctrl-0 = <&all_nand_pins>; + pinctrl-1 = <&all_nand_pins>; + pinctrl-2 = <&nand_cs_pins>; + device_id = <0>; + plat-names = "nandboot","nandnormal"; + plat-num = <2>; + plat-part-0 = <&nandboot>; + plat-part-1 = <&nandnormal>; + nandboot: nandboot{ + enable_pad ="ce0"; + busy_pad = "rb0"; + timming_mode = "mode5"; + bch_mode = "bch60_1k"; + t_rea = <20>; + t_rhoh = <15>; + chip_num = <1>; + part_num = <0>; + rb_detect = <1>; + }; + nandnormal: nandnormal{ + enable_pad ="ce0","ce1"; + busy_pad = "rb0","rb1"; + timming_mode = "mode5"; + bch_mode = "bch60_1k"; + plane_mode = "twoplane"; + t_rea = <20>; + t_rhoh = <15>; + chip_num = <2>; + part_num = <3>; + partition = <&nand_partitions>; + rb_detect = <1>; + }; + nand_partitions:nand_partition{ + logo{ + offset=<0x0 0x0>; + size=<0x0 0x200000>; + }; + recovery{ + offset=<0x0 0x0>; + size=<0x0 0x1000000>; + }; + boot{ + offset=<0x0 0x0>; + size=<0x0 0xC00000>; + }; + system{ + offset=<0x0 0x0>; + size=<0x0 0x80000000>; + }; + data{ + offset=<0xffffffff 0xffffffff>; + size=<0x0 0x0>; + }; + }; + }; + + ethmac: ethernet@0xc9410000 { + compatible = "amlogic, gxbb-eth-dwmac"; + reg = <0xc9410000 0x10000 + 0xc8834540 0x8 + 0xc8834558 0xc>; + interrupts = <0 8 1>; + pinctrl-names = "external_eth_pins"; + pinctrl-0 = <&external_eth_pins>; + rst_pin-gpios = <&gpio GPIOZ_14 0>; + GPIOZ4_pin-gpios = <&gpio GPIOZ_4 0>; + GPIOZ5_pin-gpios = <&gpio GPIOZ_5 0>; + mc_val_internal_phy = <0x1800>; + mc_val_external_phy = <0x1621>; + cali_val = <0x20000>; + interrupt-names = "macirq"; + clocks = <&clkc CLKID_ETH>; + clock-names = "ethclk81"; + internal_phy=<0>; + }; + + codec_io { + compatible = "amlogic, codec_io"; + #address-cells=<1>; + #size-cells=<1>; + ranges; + io_cbus_base{ + reg = <0xC1100000 0x100000>; + }; + io_dos_base{ + reg = <0xc8820000 0x10000>; + }; + io_hiubus_base{ + reg = <0xc883c000 0x2000>; + }; + io_aobus_base{ + reg = <0xc8100000 0x100000>; + }; + io_vcbus_base{ + reg = <0xd0100000 0x40000>; + }; + io_dmc_base{ + reg = <0xc8838000 0x400>; + }; + }; + + codec_mm { + compatible = "amlogic, codec, mm"; + memory-region = <&codec_mm_cma &codec_mm_reserved>; + dev_name = "codec_mm"; + status = "okay"; + }; + + canvas{ + compatible = "amlogic, meson, canvas"; + dev_name = "amlogic-canvas"; + status = "ok"; + reg = <0xc8838000 0x400>; + }; + + mesonstream { + compatible = "amlogic, codec, streambuf"; + dev_name = "mesonstream"; + status = "okay"; + clocks = <&clkc CLKID_DOS_PARSER + &clkc CLKID_DEMUX + &clkc CLKID_DOS + &clkc CLKID_CLK81 + &clkc CLKID_VDEC_MUX + &clkc CLKID_HCODEC_MUX + &clkc CLKID_HEVC_MUX>; + clock-names = "parser_top", + "demux", + "vdec", + "clk_81", + "clk_vdec_mux", + "clk_hcodec_mux", + "clk_hevc_mux"; + }; + + vdec { + compatible = "amlogic, vdec"; + dev_name = "vdec.0"; + status = "okay"; + interrupts = <0 3 1 + 0 23 1 + 0 32 1 + 0 43 1 + 0 44 1 + 0 45 1>; + interrupt-names = "vsync", + "demux", + "parser", + "mailbox_0", + "mailbox_1", + "mailbox_2"; + }; + + aml_sensor0: aml-sensor@0 { + compatible = "amlogic, aml-thermal"; + device_name = "thermal"; + #thermal-sensor-cells = <1>; + cooling_devices { + cpufreq_cool_cluster0 { + min_state = <1000000>; + dyn_coeff = <140>; + cluster_id = <0>; + node_name = "cpufreq_cool0"; + device_type = "cpufreq"; + }; + cpufreq_cool_cluster1 { + min_state = <500000>; + dyn_coeff = <140>; + cluster_id = <1>; + node_name = "cpufreq_cool1"; + device_type = "cpufreq"; + }; + cpucore_cool_cluster0 { + min_state = <1>; + dyn_coeff = <0>; + cluster_id = <0>; + node_name = "cpucore_cool0"; + device_type = "cpucore"; + }; + cpucore_cool_cluster1 { + min_state = <1>; + dyn_coeff = <0>; + cluster_id = <1>; + node_name = "cpucore_cool1"; + device_type = "cpucore"; + }; + gpufreq_cool { + min_state = <400>; + dyn_coeff = <437>; + cluster_id = <0>; + node_name = "gpufreq_cool0"; + device_type = "gpufreq"; + }; + gpucore_cool { + min_state = <1>; + dyn_coeff = <0>; + cluster_id = <0>; + node_name = "gpucore_cool0"; + device_type = "gpucore"; + }; + }; + cpufreq_cool0:cpufreq_cool0 { + #cooling-cells = <2>; /* min followed by max */ + }; + cpufreq_cool1:cpufreq_cool1 { + #cooling-cells = <2>; /* min followed by max */ + }; + cpucore_cool0:cpucore_cool0 { + #cooling-cells = <2>; /* min followed by max */ + }; + cpucore_cool1:cpucore_cool1 { + #cooling-cells = <2>; /* min followed by max */ + }; + gpufreq_cool0:gpufreq_cool0 { + #cooling-cells = <2>; /* min followed by max */ + }; + gpucore_cool0:gpucore_cool0 { + #cooling-cells = <2>; /* min followed by max */ + }; + }; + thermal-zones { + soc_thermal { + polling-delay = <1000>; + polling-delay-passive = <100>; + sustainable-power = <2450>; + + thermal-sensors = <&aml_sensor0 3>; + + trips { + switch_on: trip-point@0 { + temperature = <70000>; + hysteresis = <1000>; + type = "passive"; + }; + control: trip-point@1 { + temperature = <80000>; + hysteresis = <1000>; + type = "passive"; + }; + hot: trip-point@2 { + temperature = <85000>; + hysteresis = <5000>; + type = "hot"; + }; + critical: trip-point@3 { + temperature = <260000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + + cooling-maps { + cpufreq_cooling_map0 { + trip = <&control>; + cooling-device = <&cpufreq_cool0 0 4>; + contribution = <1024>; + }; + cpufreq_cooling_map1 { + trip = <&control>; + cooling-device = <&cpufreq_cool1 0 4>; + contribution = <1024>; + }; + cpucore_cooling_map0 { + trip = <&control>; + cooling-device = <&cpucore_cool0 0 3>; + contribution = <1024>; + }; + cpucore_cooling_map1 { + trip = <&control>; + cooling-device = <&cpucore_cool1 0 3>; + contribution = <1024>; + }; + gpufreq_cooling_map { + trip = <&control>; + cooling-device = <&gpufreq_cool0 0 4>; + contribution = <1024>; + }; + gpucore_cooling_map { + trip = <&control>; + cooling-device = <&gpucore_cool0 0 2>; + contribution = <1024>; + }; + }; + }; + }; + + dwc3: dwc3@c9000000 { + compatible = "synopsys, dwc3"; + reg = <0xc9000000 0x100000>; + interrupts = <0 30 4>; + usb-phy = <&usb2_phy>, <&usb3_phy>; + cpu-type = "gxl"; + clock-src = "usb3.0"; + }; + + usb2_phy: usb2phy@d0078000 { + compatible = "amlogic, amlogic-new-usb2"; + portnum = <3>; + reg = <0xd0078000 0x80 + 0xc1104408 0x4>; + }; + + usb3_phy: usb3phy@d0078080 { + compatible = "amlogic, amlogic-new-usb3"; + portnum = <0>; + reg = <0xd0078080 0x20>; + interrupts = <0 16 4>; + otg = <1>; + gpio-vbus-power = "GPIOAO_5"; + gpios = <&gpio_ao GPIOAO_5 GPIO_ACTIVE_HIGH>; + }; + + dwc2_a { + compatible = "amlogic, dwc2"; + device_name = "dwc2_a"; + reg = <0xc9100000 0x40000>; + status = "okay"; + interrupts = <0 31 4>; + pl-periph-id = <0>; /** lm name */ + clock-src = "usb0"; /** clock src */ + port-id = <0>; /** ref to mach/usb.h */ + port-type = <2>; /** 0: otg, 1: host, 2: slave */ + port-speed = <0>; /** 0: default, high, 1: full */ + port-config = <0>; /** 0: default */ + port-dma = <0>; /** 0: default ... 6: disable*/ + port-id-mode = <0>; /** 0: hardware, 1: sw_host, 2: sw_slave*/ + usb-fifo = <728>; + cpu-type = "gxl"; + controller-type = <3>; /** 0: normal,1:host,2:device,3:otg*/ + phy-reg = <0xd0078000>; + phy-reg-size = <0xa0>; + clocks = <&clkc CLKID_USB_GENERAL + &clkc CLKID_USB1_TO_DDR + &clkc CLKID_USB1>; + clock-names = "usb_general", + "usb1", + "usb1_to_ddr"; + }; + + meson-amvideom { + compatible = "amlogic, amvideom"; + dev_name = "amvideom"; + status = "okay"; + interrupts = <0 3 1>; + interrupt-names = "vsync"; + }; + + vout { + compatible = "amlogic, vout"; + dev_name = "vout"; + status = "okay"; + fr_auto_policy = <0>; + }; + + cvbsout { + compatible = "amlogic, cvbsout-gxm"; + dev_name = "cvbsout"; + status = "okay"; + clocks = <&clkc CLKID_VCLK2_ENCI + &clkc CLKID_VCLK2_VENCI0 + &clkc CLKID_VCLK2_VENCI1 + &clkc CLKID_DAC_CLK>; + clock-names = "venci_top_gate", + "venci_0_gate", + "venci_1_gate", + "vdac_clk_gate"; + + /* performance: reg_address, reg_value */ + performance = <0x1bf0 0x9 + 0x1b56 0x343 + 0x1b12 0x8080 + 0x1b05 0xfd + 0x1c59 0xf752 + 0xffff 0x0>; /* ending flag */ + }; + + amhdmitx: amhdmitx{ + compatible = "amlogic, amhdmitx"; + dev_name = "amhdmitx"; + status = "okay"; + vend-data = <&vend_data>; + pinctrl-names="hdmitx_hpd", "hdmitx_ddc"; + pinctrl-0=<&hdmitx_hpd>; + pinctrl-1=<&hdmitx_ddc>; + /* HPD, 57 + 32 = 89; CEC, 151 + 32 = 183*/ + interrupts = <0 57 1>; + interrupt-names = "hdmitx_hpd"; + /* 0:M8B 1:GXBB 2:GXTVBB 3:GXL 4:GXM + * 5:TXL 6:TXLX 7:AXG 8:GXLX 9:TXHD + */ + ic_type = <4>; + vend_data: vend_data{ /* Should modified by Customer */ + vendor_name = "Amlogic"; /* Max Chars: 8 */ + /* standards.ieee.org/develop/regauth/oui/oui.txt */ + vendor_id = <0x000000>; + product_desc = "MBox Meson Ref"; /* Max Chars: 16 */ + }; + }; + + aocec: aocec{ + compatible = "amlogic, amlogic-aocec"; + device_name = "aocec"; + status = "okay"; + vendor_id = <0x000000>; + cec_osd_string = "MBox"; /* Max Chars: 14 */ + cec_version = <6>; /* 5: 1.4, 6: 2.0 */ + port_num = <1>; + arc_port_mask = <0x0>; + interrupts = <0 199 1>; + interrupt-names = "hdmi_aocec"; + pinctrl-names = "default"; + pinctrl-0=<&hdmitx_aocec>; + reg = <0xc810023c 0x4 + 0xc8100000 0x200>; + reg-names = "ao_exit","ao"; + }; + + sysled { + compatible = "amlogic, sysled"; + dev_name = "sysled"; + status = "disabled"; + led_gpio = <&gpio GPIODV_24 GPIO_ACTIVE_HIGH>; + led_active_low = <1>; + }; + + meson-fb { + compatible = "amlogic, meson-gxm"; + dev_name = "meson-fb"; + status = "okay"; + interrupts = <0 3 1 + 0 89 1>; + interrupt-names = "viu-vsync", "rdma"; + mem_size = <0x00800000 0x01800000 0x00100000>; + /* uboot logo,fb0/fb1 memory size,if afbcd fb0=0x01851000*/ + display_mode_default = "1080p60hz"; + scale_mode = <1>; + /** 0:VPU free scale 1:OSD free scale 2:OSD super scale */ + display_size_default = <1920 1080 1920 3240 32>; + /*1920*1080*4*3 = 0x17BB000*/ + mem_alloc = <1>; + logo_addr = "0x7dc00000"; + }; + ge2d { + compatible = "amlogic, ge2d-gxm"; + dev_name = "ge2d"; + status = "okay"; + interrupts = <0 150 1>; + interrupt-names = "ge2d"; + clocks = <&clkc CLKID_VAPB_MUX>, + <&clkc CLKID_G2D>, + <&clkc CLKID_GE2D_GATE>; + clock-names = "clk_vapb_0", + "clk_ge2d", + "clk_ge2d_gate"; + }; + + + /* AUDIO MESON DEVICES */ + i2s_dai: I2S { + #sound-dai-cells = <0>; + compatible = "amlogic, aml-i2s-dai"; + clocks = + <&clkc CLKID_MPLL2>, + <&clkc CLKID_AMCLK_COMP>, + <&clkc CLKID_AIU_GLUE>, + <&clkc CLKID_IEC958>, + <&clkc CLKID_I2S_OUT>, + <&clkc CLKID_AMCLK>, + <&clkc CLKID_AIFIFO2>, + <&clkc CLKID_MIXER>, + <&clkc CLKID_MIXER_IFACE>, + <&clkc CLKID_ADC>, + <&clkc CLKID_AIU_TOP>, + <&clkc CLKID_AOCLK_GATE>, + <&clkc CLKID_I2S_SPDIF>; + clock-names = + "mpll", + "mclk", + "top_glue", + "aud_buf", + "i2s_out", + "amclk_measure", + "aififo2", + "aud_mixer", + "mixer_reg", + "adc", + "top_level", + "aoclk", + "aud_in"; + i2s_pos_sync = <0>; + /*DMIC;*/ /* I2s Mic or Dmic, default for I2S mic */ + }; + dmic:snd_dmic { + #sound-dai-cells = <0>; + compatible = "aml, aml_snd_dmic"; + reg = <0xd0042000 0x2000>; + status = "okay"; + resets = < + &clkc CLKID_PDM_GATE + >; + reset-names = "pdm"; + pinctrl-names = "audio_dmic"; + pinctrl-0 = <&aml_dmic_pins>; + clocks = <&clkc CLKID_PDM_COMP>, + <&clkc CLKID_AMCLK_COMP>; + clock-names = "pdm", "mclk"; + }; + spdif_dai: SPDIF { + #sound-dai-cells = <0>; + compatible = "amlogic, aml-spdif-dai"; + clocks = + <&clkc CLKID_MPLL1>, + <&clkc CLKID_I958_COMP>, + <&clkc CLKID_AMCLK_COMP>, + <&clkc CLKID_I958_COMP_SPDIF>, + <&clkc CLKID_CLK81>, + <&clkc CLKID_IEC958>, + <&clkc CLKID_IEC958_GATE>; + clock-names = + "mpll1", + "i958", + "mclk", + "spdif", + "clk_81", + "iec958", + "iec958_amclk"; + }; + pcm_dai: PCM { + #sound-dai-cells = <0>; + compatible = "amlogic, aml-pcm-dai"; + pinctrl-names = "audio_pcm"; + pinctrl-0 = <&audio_pcm_pins>; + clocks = + <&clkc CLKID_MPLL0>, + <&clkc CLKID_PCM_MCLK_COMP>, + <&clkc CLKID_PCM_SCLK_GATE>; + clock-names = + "mpll0", + "pcm_mclk", + "pcm_sclk"; + pcm_mode = <1>; /* 0=slave mode, 1=master mode */ + }; + i2s_plat: i2s_platform { + compatible = "amlogic, aml-i2s"; + interrupts = <0 29 1>; + }; + pcm_plat: pcm_platform { + compatible = "amlogic, aml-pcm"; + }; + spdif_codec: spdif_codec{ + #sound-dai-cells = <0>; + compatible = "amlogic, aml-spdif-codec"; + pinctrl-names = "audio_spdif"; + pinctrl-0 = <&audio_spdif_pins>; + }; + pcm_codec: pcm_codec{ + #sound-dai-cells = <0>; + compatible = "amlogic, pcm2BT-codec"; + }; + /* endof AUDIO MESON DEVICES */ + + /* AUDIO board specific */ + dummy_codec:dummy{ + #sound-dai-cells = <0>; + compatible = "amlogic, aml_dummy_codec"; + status = "disable"; + }; + amlogic_codec:t9015{ + #sound-dai-cells = <0>; + compatible = "amlogic, aml_codec_T9015"; + reg = <0xc8832000 0x14>; + status = "okay"; + }; + aml_sound_meson { + compatible = "aml, meson-snd-card"; + status = "okay"; + aml-sound-card,format = "i2s"; + aml_sound_card,name = "AML-MESONAUDIO"; + aml,audio-routing = + "Ext Spk","LOUTL", + "Ext Spk","LOUTR"; + + mute_gpio-gpios = <&gpio GPIOH_5 0>; + mute_inv; + hp_disable; + hp_paraments = <800 300 0 5 1>; + pinctrl-names = "audio_i2s"; + pinctrl-0 = <&audio_i2s_pins>; + cpu_list = <&cpudai0 &cpudai1 &cpudai2>; + codec_list = <&codec0 &codec1 &codec2>; + plat_list = <&i2s_plat &i2s_plat &pcm_plat>; + cpudai0: cpudai0 { + sound-dai = <&i2s_dai>; + }; + cpudai1: cpudai1 { + sound-dai = <&spdif_dai>; + }; + cpudai2: cpudai2 { + sound-dai = <&pcm_dai>; + }; + codec0: codec0 { + sound-dai = <&amlogic_codec>; + }; + codec1: codec1 { + sound-dai = <&spdif_codec>; + }; + codec2: codec2 { + sound-dai = <&pcm_codec>; + }; + }; + /* END OF AUDIO board specific */ + + rdma{ + compatible = "amlogic, meson, rdma"; + dev_name = "amlogic-rdma"; + status = "ok"; + interrupts = <0 89 1>; + interrupt-names = "rdma"; + }; + + amvenc_avc{ + compatible = "amlogic, amvenc_avc"; + dev_name = "amvenc_avc"; + status = "okay"; + interrupts = <0 45 1>; + interrupt-names = "mailbox_2"; + }; + + hevc_enc{ + compatible = "cnm, HevcEnc"; + dev_name = "HevcEnc"; + status = "okay"; + interrupts = <0 187 1>; + interrupt-names = "wave420l_irq"; + #address-cells=<1>; + #size-cells=<1>; + ranges; + io_reg_base{ + reg = <0xc8810000 0x4000>; + }; + }; + + picdec { + compatible = "amlogic, picdec"; + memory-region = <&picdec_cma_reserved>; + dev_name = "picdec"; + status = "okay"; + }; + + ppmgr { + compatible = "amlogic, ppmgr"; + memory-region = <&ppmgr_reserved>; + dev_name = "ppmgr"; + status = "okay"; + }; + + deinterlace { + compatible = "amlogic, deinterlace"; + status = "okay"; + flag_cma = <1>;/*0:use reserved;1:use cma*/ + //memory-region = <&di_reserved>; + memory-region = <&di_cma_reserved>; + interrupts = <0 46 1 0 6 1>; + interrupt-names = "de_irq", "timerc"; + /* + * nr_size(byte) = 1920*544*2(yuv422 8bit) | + * 1920*544*2*12/8(yuv422 10bit) + * | 1920*544*2*10/8(yuv422 10bit full pack mode) + */ + /* mtn_size(byte) = 1920*544/2 */ + /* count_size(byte) = 1920*544/2 */ + buffer-size = <3133440>; + hw-version = <2>; + }; + + ionvideo { + compatible = "amlogic, ionvideo"; + dev_name = "ionvideo"; + status = "okay"; + }; + + amlvideo { + compatible = "amlogic, amlvideo"; + dev_name = "amlvideo"; + status = "okay"; + }; + + amlvideo2_0 { + compatible = "amlogic, amlvideo2"; + dev_name = "amlvideo2"; + status = "okay"; + amlvideo2_id = <0>; + cma_mode = <1>; + }; + + amlvideo2_1 { + compatible = "amlogic, amlvideo2"; + dev_name = "amlvideo2"; + status = "okay"; + amlvideo2_id = <1>; + cma_mode = <1>; + }; + + /*if you want to use vdin just modify status to "ok"*/ + vdin0 { + compatible = "amlogic, vdin"; + /*memory-region = <&vdin0_cma_reserved>;*/ + dev_name = "vdin0"; + status = "ok"; + reserve-iomap = "true"; + flag_cma = <1>;/*1:share with codec_mm;2:cma alone*/ + /*MByte, if 10bit disable: 64M(YUV422), + *if 10bit enable: 64*1.5 = 96M(YUV422) + *if support 4K2K-YUV444-10bit-WR:3840*2160*4*4 ~= 128M + *if support 4K2K-YUV422-10bit-wr:3840*2160*3*4 ~= 96M + *if support 4K2K-YUV422-8BIT-WR:3840*2160*2*4 ~= 64M + *if support 1080p-YUV422-8BIT-WR:1920*1080*2*4 ~= 16M + */ + cma_size = <16>; + interrupts = <0 83 1>; + rdma-irq = <2>; + /*clocks = <&clkc CLKID_FCLK_DIV5>, + * <&clkc CLK_VDIN_MEAS_CLK>; + *clock-names = "fclk_div5", "cts_vdin_meas_clk"; + */ + vdin_id = <0>; + /*vdin write mem color depth support: + *bit0:support 8bit + *bit1:support 9bit + *bit2:support 10bit + *bit3:support 12bit + *bit4:support yuv422 10bit full pack mode (from txl new add) + */ + tv_bit_mode = <1>; + }; + vdin1 { + compatible = "amlogic, vdin"; + memory-region = <&vdin1_cma_reserved>; + dev_name = "vdin1"; + status = "ok"; + reserve-iomap = "true"; + flag_cma = <0>;/*1:share with codec_mm;0:cma alone*/ + interrupts = <0 85 1>; + rdma-irq = <4>; + /*clocks = <&clock CLK_FPLL_DIV5>, + * <&clock CLK_VDIN_MEAS_CLK>; + *clock-names = "fclk_div5", "cts_vdin_meas_clk"; + */ + vdin_id = <1>; + /*vdin write mem color depth support: + *bit0:support 8bit + *bit1:support 9bit + *bit2:support 10bit + *bit3:support 12bit + */ + tv_bit_mode = <1>; + }; + + amlvecm { + compatible = "amlogic, vecm"; + dev_name = "aml_vecm"; + status = "okay"; + gamma_en = <0>;/*1:enabel ;0:disable*/ + wb_en = <0>;/*1:enabel ;0:disable*/ + cm_en = <0>;/*1:enabel ;0:disable*/ + /*1:enabel osd lut 100 table;0:disable*/ + cfg_en_osd_100 = <1>; + /*0: 709/601 1: bt2020*/ + tx_op_color_primary = <0>; + }; + + partitions: partitions{ + parts = <12>; + part-0 = <&logo>; + part-1 = <&recovery>; + part-2 = <&rsv>; + part-3 = <&tee>; + part-4 = <&crypt>; + part-5 = <&misc>; + part-6 = <&boot>; + part-7 = <&system>; + part-8 = <&cache>; + part-9 = <&vendor>; + part-10 = <&odm>; + part-11 = <&data>; + + logo:logo{ + pname = "logo"; + size = <0x0 0x2000000>; + mask = <1>; + }; + recovery:recovery{ + pname = "recovery"; + size = <0x0 0x2000000>; + mask = <1>; + }; + rsv:rsv{ + pname = "rsv"; + size = <0x0 0x800000>; + mask = <1>; + }; + tee:tee{ + pname = "tee"; + size = <0x0 0x800000>; + mask = <1>; + }; + crypt:crypt{ + pname = "crypt"; + size = <0x0 0x2000000>; + mask = <1>; + }; + misc:misc{ + pname = "misc"; + size = <0x0 0x2000000>; + mask = <1>; + }; + boot:boot + { + pname = "boot"; + size = <0x0 0x2000000>; + mask = <1>; + }; + system:system + { + pname = "system"; + size = <0x0 0x80000000>; + mask = <1>; + }; + vendor:vendor + { + pname = "vendor"; + size = <0x0 0x10000000>; + mask = <1>; + }; + odm:odm + { + pname = "odm"; + size = <0x0 0x10000000>; + mask = <1>; + }; + cache:cache + { + pname = "cache"; + size = <0x0 0x20000000>; + mask = <2>; + }; + data:data + { + pname = "data"; + size = <0xffffffff 0xffffffff>; + mask = <4>; + }; + }; + unifykey{ + compatible = "amlogic, unifykey"; + status = "ok"; + + unifykey-num = <14>; + unifykey-index-0 = <&keysn_0>; + unifykey-index-1 = <&keysn_1>; + unifykey-index-2 = <&keysn_2>; + unifykey-index-3 = <&keysn_3>; + unifykey-index-4 = <&keysn_4>; + unifykey-index-5 = <&keysn_5>; + unifykey-index-6 = <&keysn_6>; + unifykey-index-7 = <&keysn_7>; + unifykey-index-8 = <&keysn_8>; + unifykey-index-9 = <&keysn_9>; + unifykey-index-10= <&keysn_10>; + unifykey-index-11= <&keysn_11>; + unifykey-index-12= <&keysn_12>; + unifykey-index-13= <&keysn_13>; + + keysn_0: key_0{ + key-name = "usid"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_1:key_1{ + key-name = "mac"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_2:key_2{ + key-name = "hdcp"; + key-device = "secure"; + key-type = "sha1"; + key-permit = "read","write","del"; + }; + keysn_3:key_3{ + key-name = "secure_boot_set"; + key-device = "efuse"; + key-permit = "write"; + }; + keysn_4:key_4{ + key-name = "mac_bt"; + key-device = "normal"; + key-permit = "read","write","del"; + key-type = "mac"; + }; + keysn_5:key_5{ + key-name = "mac_wifi"; + key-device = "normal"; + key-permit = "read","write","del"; + key-type = "mac"; + }; + keysn_6:key_6{ + key-name = "hdcp2_tx"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_7:key_7{ + key-name = "hdcp2_rx"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_8:key_8{ + key-name = "widevinekeybox"; + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_9:key_9{ + key-name = "deviceid"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_10:key_10{ + key-name = "hdcp22_fw_private"; + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_11:key_11{ + key-name = "PlayReadykeybox25"; + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_12:key_12{ + key-name = "prpubkeybox";// PlayReady + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_13:key_13{ + key-name = "prprivkeybox";// PlayReady + key-device = "secure"; + key-permit = "read","write","del"; + }; + };//End unifykey +}; +&efuse { + status = "ok"; +}; + +&pwm_ef { + status = "okay"; +}; + +&audio_data{ + status = "okay"; +}; +&i2c1 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/amlogic/gxm_q201_1g.dts b/arch/arm/boot/dts/amlogic/gxm_q201_1g.dts new file mode 100644 index 000000000000..e96da973279d --- /dev/null +++ b/arch/arm/boot/dts/amlogic/gxm_q201_1g.dts @@ -0,0 +1,1231 @@ +/* + * arch/arm/boot/dts/amlogic/gxm_q201_1g.dts + * + * Copyright (C) 2017 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +/dts-v1/; + +#include "mesongxm.dtsi" +#include "partition_mbox_normal.dtsi" +/ { + model = "Amlogic"; + amlogic-dt-id = "gxm_q201_1g"; + compatible = "amlogic, Gxm"; + interrupt-parent = <&gic>; + #address-cells = <1>; + #size-cells = <1>; + + aliases { + serial0 = &uart_AO; + serial1 = &uart_A; + serial2 = &uart_B; + serial3 = &uart_C; + serial4 = &uart_AO_B; + }; + + ion_dev { + compatible = "amlogic, ion_dev"; + memory-region = <&ion_reserved>; + }; + + memory@00000000 { + device_type = "memory"; + linux,usable-memory = <0x0100000 0x3ff00000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + /* global autoconfigured region for contiguous allocations */ + ramoops@0x07400000 { + compatible = "ramoops"; + reg = <0x07400000 0x00100000>; + record-size = <0x8000>; + console-size = <0x8000>; + ftrace-size = <0x0>; + pmsg-size = <0x8000>; +}; + + secmon_reserved:linux,secmon { + compatible = "shared-dma-pool"; + reusable; + size = <0x400000>; + alignment = <0x400000>; + alloc-ranges = <0x05000000 0x400000>; + }; + secos_reserved:linux,secos { + status = "disable"; + compatible = "amlogic, aml_secos_memory"; + reg = <0x05300000 0x2000000>; + no-map; + }; + logo_reserved:linux,meson-fb { + compatible = "shared-dma-pool"; + reusable; + size = <0x800000>; + alignment = <0x400000>; + alloc-ranges = <0x7f800000 0x800000>; + }; + //don't put other dts in front of logo_reserved + + //di_reserved:linux,di { + // compatible = "amlogic, di-mem"; + /** 10x3133440=30M(0x1e) support 8bit **/ + // size = <0x1e00000>; + //no-map; + //}; + di_cma_reserved:linux,di_cma { + compatible = "shared-dma-pool"; + reusable; + /** 10x3133440=30M(0x1e) support 8bit **/ + size = <0x2000000>; + alignment = <0x400000>; + }; + ion_reserved:linux,ion-dev { + compatible = "shared-dma-pool"; + reusable; + size = <0x7C00000>; + alignment = <0x400000>; + }; + + /* vdin0 CMA pool */ + //vdin0_cma_reserved:linux,vdin0_cma { + // compatible = "shared-dma-pool"; + // linux,phandle = <4>; + // reusable; + /* 1920x1080x2x4 =16+4 M */ + // size = <0x01400000>; + // alignment = <0x400000>; + //}; + /* vdin1 CMA pool */ + vdin1_cma_reserved:linux,vdin1_cma { + compatible = "shared-dma-pool"; + reusable; + /* 1920x1080x2x4 =16 M */ + size = <0x01000000>; + alignment = <0x400000>; + }; + /* POST PROCESS MANAGER */ + ppmgr_reserved:linux,ppmgr { + compatible = "amlogic, ppmgr_memory"; + size = <0x0>; + }; + + codec_mm_cma:linux,codec_mm_cma { + compatible = "shared-dma-pool"; + reusable; + /* ion_codec_mm max can alloc size 80M*/ + size = <0xc000000>; + alignment = <0x400000>; + linux,contiguous-region; + }; + picdec_cma_reserved:linux,picdec { + compatible = "shared-dma-pool"; + reusable; + size = <0x0>; + alignment = <0x0>; + linux,contiguous-region; + }; + /* codec shared reserved */ + codec_mm_reserved:linux,codec_mm_reserved { + compatible = "amlogic, codec-mm-reserved"; + size = <0x0>; + alignment = <0x100000>; + //no-map; + }; + }; + + bt-dev{ + compatible = "amlogic, bt-dev"; + dev_name = "bt-dev"; + status = "okay"; + gpio_reset = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>; + }; + + wifi{ + compatible = "amlogic, aml_wifi"; + dev_name = "aml_wifi"; + status = "okay"; + interrupt_pin = <&gpio GPIOX_7 GPIO_ACTIVE_HIGH>; + irq_trigger_type = "GPIO_IRQ_LOW"; + dhd_static_buf; + power_on_pin = <&gpio GPIOX_6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_32k_pins>; + pwm_config = <&wifi_pwm_conf>; + }; + + wifi_pwm_conf:wifi_pwm_conf{ + pwm_channel1_conf { + pwms = <&pwm_ef MESON_PWM_0 30040 0>; + duty-cycle = <15020>; + times = <8>; + }; + pwm_channel2_conf { + pwms = <&pwm_ef MESON_PWM_2 30030 0>; + duty-cycle = <15015>; + times = <12>; + }; + }; + + sd_emmc_c: emmc@d0074000 { + status = "okay"; + compatible = "amlogic, meson-mmc-gxm"; + reg = <0xd0074000 0x2000>; + interrupts = <0 218 1>; + pinctrl-names = "emmc_clk_cmd_pins", "emmc_all_pins"; + pinctrl-0 = <&emmc_clk_cmd_pins>; + pinctrl-1 = <&emmc_conf_pull_up &emmc_conf_pull_done>; + clocks = <&clkc CLKID_SD_EMMC_C>, + <&clkc CLKID_SD_EMMC_C_P0_COMP>, + <&clkc CLKID_FCLK_DIV2>; + clock-names = "core", "clkin0", "clkin1"; + + bus-width = <8>; + cap-sd-highspeed; + cap-mmc-highspeed; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + + max-frequency = <200000000>; + non-removable; + disable-wp; + emmc { + pinname = "emmc"; + ocr_avail = <0x200080>; /**VDD voltage 3.3 ~ 3.4 */ + caps = "MMC_CAP_8_BIT_DATA", + "MMC_CAP_MMC_HIGHSPEED", + "MMC_CAP_SD_HIGHSPEED", + "MMC_CAP_NONREMOVABLE", + "MMC_CAP_1_8V_DDR", + "MMC_CAP_HW_RESET", + "MMC_CAP_ERASE", + "MMC_CAP_CMD23"; + caps2 = "MMC_CAP2_HS200", "MMC_CAP2_HS400"; + f_min = <400000>; + f_max = <100000000>; + max_req_size = <0x20000>; /**128KB*/ + gpio_dat3 = <&gpio BOOT_3 GPIO_ACTIVE_HIGH>; + hw_reset = <&gpio BOOT_9 GPIO_ACTIVE_HIGH>; + card_type = <1>; + /* 1:mmc card(include eMMC), + * 2:sd card(include tSD) + */ + }; + }; + + sd_emmc_b:sd@d0072000 { + status = "okay"; + compatible = "amlogic, meson-mmc-gxm"; + reg = <0xd0072000 0x2000>; + interrupts = <0 217 1>; + pinctrl-names = "sd_all_pins", + "sd_clk_cmd_pins", + "sd_1bit_pins", + "sd_clk_cmd_uart_pins", + "sd_1bit_uart_pins", + "sd_to_ao_uart_pins", + "ao_to_sd_uart_pins", + "ao_to_sd_jtag_pins", + "sd_to_ao_jtag_pins"; + pinctrl-0 = <&sd_all_pins>; + pinctrl-1 = <&sd_clk_cmd_pins>; + pinctrl-2 = <&sd_1bit_pins>; + pinctrl-3 = <&sd_to_ao_uart_clr_pins + &sd_clk_cmd_pins &ao_to_sd_uart_pins>; + pinctrl-4 = <&sd_to_ao_uart_clr_pins + &sd_1bit_pins &ao_to_sd_uart_pins>; + pinctrl-5 = <&sd_all_pins &sd_to_ao_uart_pins>; + pinctrl-6 = <&sd_to_ao_uart_clr_pins &ao_to_sd_uart_pins>; + pinctrl-7 = <&sd_to_ao_uart_clr_pins &ao_to_sd_uart_pins>; + pinctrl-8 = <&sd_all_pins &sd_to_ao_uart_pins>; + clocks = <&clkc CLKID_SD_EMMC_B>, + <&clkc CLKID_SD_EMMC_B_P0_COMP>, + <&clkc CLKID_FCLK_DIV2>; + clock-names = "core", "clkin0", "clkin1"; + + bus-width = <4>; + cap-sd-highspeed; + max-frequency = <100000000>; + disable-wp; + sd { + pinname = "sd"; + ocr_avail = <0x200080>; /**VDD voltage 3.3 ~ 3.4 */ + caps = "MMC_CAP_4_BIT_DATA", + "MMC_CAP_MMC_HIGHSPEED", + "MMC_CAP_SD_HIGHSPEED"; + /* "MMC_CAP_UHS_SDR12", + * "MMC_CAP_UHS_SDR25", + * "MMC_CAP_UHS_SDR50", + * "MMC_CAP_UHS_SDR104"; + */ + f_min = <400000>; + f_max = <100000000>; + max_req_size = <0x20000>; /**128KB*/ + gpio_dat3 = <&gpio CARD_4 GPIO_ACTIVE_HIGH>; + jtag_pin = <&gpio CARD_0 GPIO_ACTIVE_HIGH>; + gpio_cd = <&gpio CARD_6 GPIO_ACTIVE_HIGH>; + card_type = <5>; + /* 0:unknown, + * 1:mmc card(include eMMC), + * 2:sd card(include tSD), + * 3:sdio device(ie:sdio-wifi), + * 4:SD combo (IO+mem) card, + * 5:NON sdio device(means sd/mmc card), + * other:reserved + */ + }; + }; + + sd_emmc_a:sdio@d0070000 { + status = "okay"; + compatible = "amlogic, meson-mmc-gxm"; + reg = <0xd0070000 0x2000>; + interrupts = <0 216 4>; + pinctrl-names = "sdio_clk_cmd_pins", "sdio_all_pins"; + pinctrl-0 = <&sdio_clk_cmd_pins>; + pinctrl-1 = <&sdio_all_pins>; + clocks = <&clkc CLKID_SD_EMMC_A>, + <&clkc CLKID_SD_EMMC_A_P0_COMP>, + <&clkc CLKID_FCLK_DIV2>; + clock-names = "core", "clkin0", "clkin1"; + + bus-width = <4>; + cap-sd-highspeed; + cap-mmc-highspeed; + max-frequency = <100000000>; + non-removable; + disable-wp; + sdio { + pinname = "sdio"; + ocr_avail = <0x200080>; /**VDD voltage 3.3 ~ 3.4 */ + caps = "MMC_CAP_4_BIT_DATA", + "MMC_CAP_MMC_HIGHSPEED", + "MMC_CAP_SD_HIGHSPEED", + "MMC_CAP_NONREMOVABLE", + "MMC_CAP_UHS_SDR12", + "MMC_CAP_UHS_SDR25", + "MMC_CAP_UHS_SDR50", + "MMC_CAP_UHS_SDR104", + "MMC_PM_KEEP_POWER", + "MMC_CAP_SDIO_IRQ"; + f_min = <400000>; + f_max = <200000000>; + max_req_size = <0x20000>; /**128KB*/ + card_type = <3>; + /* 3:sdio device(ie:sdio-wifi), + * 4:SD combo (IO+mem) card + */ + }; + }; + mtd_nand{ + compatible = "amlogic, aml_mtd_nand"; + dev_name = "mtdnand"; + status = "disabled"; + reg = <0xd0074800 0x200>; + interrupts = < 0 34 1 >; + pinctrl-names = "nand_rb_mod","nand_norb_mod", "nand_cs_only"; + pinctrl-0 = <&all_nand_pins>; + pinctrl-1 = <&all_nand_pins>; + pinctrl-2 = <&nand_cs_pins>; + device_id = <0>; + plat-names = "nandboot","nandnormal"; + plat-num = <2>; + plat-part-0 = <&nandboot>; + plat-part-1 = <&nandnormal>; + nandboot: nandboot{ + enable_pad ="ce0"; + busy_pad = "rb0"; + timming_mode = "mode5"; + bch_mode = "bch60_1k"; + t_rea = <20>; + t_rhoh = <15>; + chip_num = <1>; + part_num = <0>; + rb_detect = <1>; + }; + nandnormal: nandnormal{ + enable_pad ="ce0","ce1"; + busy_pad = "rb0","rb1"; + timming_mode = "mode5"; + bch_mode = "bch60_1k"; + plane_mode = "twoplane"; + t_rea = <20>; + t_rhoh = <15>; + chip_num = <2>; + part_num = <3>; + partition = <&nand_partitions>; + rb_detect = <1>; + }; + nand_partitions:nand_partition{ + boot{ + offset=<0x0 0x300000>; + size=<0x0 0x800000>; + }; + /* + *recovery{ + * offset=<0x0 0xB00000>; + * size=<0x0 0xA00000>; + *}; + */ + upgrade{ + offset=<0x0 0xB00000>; + size=<0x0 0x5800000>; + }; + data{ + offset=<0xffffffff 0xffffffff>; + size=<0x0 0x0>; + }; + }; + }; + + ethmac: ethernet@0xc9410000 { + compatible = "amlogic, gxbb-eth-dwmac"; + reg = <0xc9410000 0x10000 + 0xc8834540 0x8 + 0xc8834558 0xc>; + interrupts = <0 8 1>; + pinctrl-names = "external_eth_pins"; + pinctrl-0 = <&external_eth_pins>; + rst_pin-gpios = <&gpio GPIOZ_14 0>; + GPIOZ4_pin-gpios = <&gpio GPIOZ_4 0>; + GPIOZ5_pin-gpios = <&gpio GPIOZ_5 0>; + mc_val_internal_phy = <0x1800>; + mc_val_external_phy = <0x1621>; + cali_val = <0x20000>; + interrupt-names = "macirq"; + clocks = <&clkc CLKID_ETH>; + clock-names = "ethclk81"; + internal_phy=<0>; + }; + + codec_io { + compatible = "amlogic, codec_io"; + #address-cells=<1>; + #size-cells=<1>; + ranges; + io_cbus_base{ + reg = <0xC1100000 0x100000>; + }; + io_dos_base{ + reg = <0xc8820000 0x10000>; + }; + io_hiubus_base{ + reg = <0xc883c000 0x2000>; + }; + io_aobus_base{ + reg = <0xc8100000 0x100000>; + }; + io_vcbus_base{ + reg = <0xd0100000 0x40000>; + }; + io_dmc_base{ + reg = <0xc8838000 0x400>; + }; + }; + + codec_mm { + compatible = "amlogic, codec, mm"; + memory-region = <&codec_mm_cma &codec_mm_reserved>; + dev_name = "codec_mm"; + status = "okay"; + }; + + canvas{ + compatible = "amlogic, meson, canvas"; + dev_name = "amlogic-canvas"; + status = "ok"; + reg = <0xc8838000 0x400>; + }; + + mesonstream { + compatible = "amlogic, codec, streambuf"; + dev_name = "mesonstream"; + status = "okay"; + clocks = <&clkc CLKID_DOS_PARSER + &clkc CLKID_DEMUX + &clkc CLKID_DOS + &clkc CLKID_VDEC_MUX + &clkc CLKID_HCODEC_MUX + &clkc CLKID_HEVC_MUX>; + clock-names = "parser_top", + "demux", + "vdec", + "clk_vdec_mux", + "clk_hcodec_mux", + "clk_hevc_mux"; + }; + + vdec { + compatible = "amlogic, vdec"; + dev_name = "vdec.0"; + status = "okay"; + interrupts = <0 3 1 + 0 23 1 + 0 32 1 + 0 43 1 + 0 44 1 + 0 45 1>; + interrupt-names = "vsync", + "demux", + "parser", + "mailbox_0", + "mailbox_1", + "mailbox_2"; + }; + + aml_sensor0: aml-sensor@0 { + compatible = "amlogic, aml-thermal"; + device_name = "thermal"; + #thermal-sensor-cells = <1>; + cooling_devices { + cpufreq_cool_cluster0 { + min_state = <1000000>; + dyn_coeff = <140>; + cluster_id = <0>; + node_name = "cpufreq_cool0"; + device_type = "cpufreq"; + }; + cpufreq_cool_cluster1 { + min_state = <500000>; + dyn_coeff = <140>; + cluster_id = <1>; + node_name = "cpufreq_cool1"; + device_type = "cpufreq"; + }; + cpucore_cool_cluster0 { + min_state = <1>; + dyn_coeff = <0>; + cluster_id = <0>; + node_name = "cpucore_cool0"; + device_type = "cpucore"; + }; + cpucore_cool_cluster1 { + min_state = <1>; + dyn_coeff = <0>; + cluster_id = <1>; + node_name = "cpucore_cool1"; + device_type = "cpucore"; + }; + gpufreq_cool { + min_state = <400>; + dyn_coeff = <437>; + cluster_id = <0>; + node_name = "gpufreq_cool0"; + device_type = "gpufreq"; + }; + gpucore_cool { + min_state = <1>; + dyn_coeff = <0>; + cluster_id = <0>; + node_name = "gpucore_cool0"; + device_type = "gpucore"; + }; + }; + cpufreq_cool0:cpufreq_cool0 { + #cooling-cells = <2>; /* min followed by max */ + }; + cpufreq_cool1:cpufreq_cool1 { + #cooling-cells = <2>; /* min followed by max */ + }; + cpucore_cool0:cpucore_cool0 { + #cooling-cells = <2>; /* min followed by max */ + }; + cpucore_cool1:cpucore_cool1 { + #cooling-cells = <2>; /* min followed by max */ + }; + gpufreq_cool0:gpufreq_cool0 { + #cooling-cells = <2>; /* min followed by max */ + }; + gpucore_cool0:gpucore_cool0 { + #cooling-cells = <2>; /* min followed by max */ + }; + }; + thermal-zones { + soc_thermal { + polling-delay = <1000>; + polling-delay-passive = <100>; + sustainable-power = <2450>; + + thermal-sensors = <&aml_sensor0 3>; + + trips { + switch_on: trip-point@0 { + temperature = <70000>; + hysteresis = <1000>; + type = "passive"; + }; + control: trip-point@1 { + temperature = <80000>; + hysteresis = <1000>; + type = "passive"; + }; + hot: trip-point@2 { + temperature = <85000>; + hysteresis = <5000>; + type = "hot"; + }; + critical: trip-point@3 { + temperature = <260000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + + cooling-maps { + cpufreq_cooling_map0 { + trip = <&control>; + cooling-device = <&cpufreq_cool0 0 4>; + contribution = <1024>; + }; + cpufreq_cooling_map1 { + trip = <&control>; + cooling-device = <&cpufreq_cool1 0 4>; + contribution = <1024>; + }; + cpucore_cooling_map0 { + trip = <&control>; + cooling-device = <&cpucore_cool0 0 3>; + contribution = <1024>; + }; + cpucore_cooling_map1 { + trip = <&control>; + cooling-device = <&cpucore_cool1 0 3>; + contribution = <1024>; + }; + gpufreq_cooling_map { + trip = <&control>; + cooling-device = <&gpufreq_cool0 0 4>; + contribution = <1024>; + }; + gpucore_cooling_map { + trip = <&control>; + cooling-device = <&gpucore_cool0 0 2>; + contribution = <1024>; + }; + }; + }; + }; + + dwc3: dwc3@c9000000 { + compatible = "synopsys, dwc3"; + reg = <0xc9000000 0x100000>; + interrupts = <0 30 4>; + usb-phy = <&usb2_phy>, <&usb3_phy>; + cpu-type = "gxl"; + clock-src = "usb3.0"; + }; + + usb2_phy: usb2phy@d0078000 { + compatible = "amlogic, amlogic-new-usb2"; + portnum = <3>; + reg = <0xd0078000 0x80 + 0xc1104408 0x4>; + }; + + usb3_phy: usb3phy@d0078080 { + compatible = "amlogic, amlogic-new-usb3"; + portnum = <0>; + reg = <0xd0078080 0x20>; + interrupts = <0 16 4>; + otg = <1>; + gpio-vbus-power = "GPIOAO_5"; + gpios = <&gpio_ao GPIOAO_5 GPIO_ACTIVE_HIGH>; + }; + + dwc2_a { + compatible = "amlogic, dwc2"; + device_name = "dwc2_a"; + reg = <0xc9100000 0x40000>; + status = "okay"; + interrupts = <0 31 4>; + pl-periph-id = <0>; /** lm name */ + clock-src = "usb0"; /** clock src */ + port-id = <0>; /** ref to mach/usb.h */ + port-type = <2>; /** 0: otg, 1: host, 2: slave */ + port-speed = <0>; /** 0: default, high, 1: full */ + port-config = <0>; /** 0: default */ + port-dma = <0>; /** 0: default ... 6: disable*/ + port-id-mode = <0>; /** 0: hardware, 1: sw_host, 2: sw_slave*/ + usb-fifo = <728>; + cpu-type = "gxl"; + controller-type = <3>; /** 0: normal,1:host,2:device,3:otg*/ + phy-reg = <0xd0078000>; + phy-reg-size = <0xa0>; + clocks = <&clkc CLKID_USB_GENERAL + &clkc CLKID_USB1_TO_DDR + &clkc CLKID_USB1>; + clock-names = "usb_general", + "usb1", + "usb1_to_ddr"; + }; + + meson-amvideom { + compatible = "amlogic, amvideom"; + dev_name = "amvideom"; + status = "okay"; + interrupts = <0 3 1>; + interrupt-names = "vsync"; + }; + + vout { + compatible = "amlogic, vout"; + dev_name = "vout"; + status = "okay"; + fr_auto_policy = <0>; + }; + + cvbsout { + compatible = "amlogic, cvbsout-gxm"; + dev_name = "cvbsout"; + status = "okay"; + clocks = <&clkc CLKID_VCLK2_ENCI + &clkc CLKID_VCLK2_VENCI0 + &clkc CLKID_VCLK2_VENCI1 + &clkc CLKID_DAC_CLK>; + clock-names = "venci_top_gate", + "venci_0_gate", + "venci_1_gate", + "vdac_clk_gate"; + + /* performance: reg_address, reg_value */ + performance = <0x1bf0 0x9 + 0x1b56 0x343 + 0x1b12 0x8080 + 0x1b05 0xfd + 0x1c59 0xf752 + 0xffff 0x0>; /* ending flag */ + }; + + amhdmitx: amhdmitx{ + compatible = "amlogic, amhdmitx"; + dev_name = "amhdmitx"; + status = "okay"; + vend-data = <&vend_data>; + pinctrl-names="hdmitx_hpd", "hdmitx_ddc"; + pinctrl-0=<&hdmitx_hpd>; + pinctrl-1=<&hdmitx_ddc>; + /* HPD, 57 + 32 = 89; CEC, 151 + 32 = 183*/ + interrupts = <0 57 1>; + interrupt-names = "hdmitx_hpd"; + /* 0:M8B 1:GXBB 2:GXTVBB 3:GXL 4:GXM + * 5:TXL 6:TXLX 7:AXG 8:GXLX 9:TXHD + */ + ic_type = <4>; + vend_data: vend_data{ /* Should modified by Customer */ + vendor_name = "Amlogic"; /* Max Chars: 8 */ + /* standards.ieee.org/develop/regauth/oui/oui.txt */ + vendor_id = <0x000000>; + product_desc = "MBox Meson Ref"; /* Max Chars: 16 */ + }; + }; + + aocec: aocec{ + compatible = "amlogic, amlogic-aocec"; + device_name = "aocec"; + status = "okay"; + vendor_id = <0x000000>; + cec_osd_string = "MBox"; /* Max Chars: 14 */ + cec_version = <6>; /* 5: 1.4, 6: 2.0 */ + port_num = <1>; + arc_port_mask = <0x0>; + interrupts = <0 199 1>; + interrupt-names = "hdmi_aocec"; + pinctrl-names = "default"; + pinctrl-0=<&hdmitx_aocec>; + reg = <0xc810023c 0x4 + 0xc8100000 0x200>; + }; + + sysled { + compatible = "amlogic, sysled"; + dev_name = "sysled"; + status = "disabled"; + led_gpio = <&gpio GPIODV_24 GPIO_ACTIVE_HIGH>; + led_active_low = <1>; + }; + + meson-fb { + compatible = "amlogic, meson-gxm"; + dev_name = "meson-fb"; + status = "okay"; + interrupts = <0 3 1 + 0 89 1>; + interrupt-names = "viu-vsync", "rdma"; + mem_size = <0x00800000 0x01851000 0x00100000>; + /* uboot logo,fb0/fb1 memory size,if afbcd fb0=0x01851000*/ + display_mode_default = "1080p60hz"; + scale_mode = <1>; + /** 0:VPU free scale 1:OSD free scale 2:OSD super scale */ + display_size_default = <1920 1080 1920 3240 32>; + /*1920*1080*4*3 = 0x17BB000*/ + logo_addr = "0x7f800000"; + }; + ge2d { + compatible = "amlogic, ge2d-gxm"; + dev_name = "ge2d"; + status = "okay"; + interrupts = <0 150 1>; + interrupt-names = "ge2d"; + clocks = <&clkc CLKID_VAPB_MUX>, + <&clkc CLKID_G2D>, + <&clkc CLKID_GE2D_GATE>; + clock-names = "clk_vapb_0", + "clk_ge2d", + "clk_ge2d_gate"; + }; + + + /* AUDIO MESON DEVICES */ + i2s_dai: I2S { + #sound-dai-cells = <0>; + compatible = "amlogic, aml-i2s-dai"; + clocks = + <&clkc CLKID_MPLL2>, + <&clkc CLKID_AMCLK_COMP>, + <&clkc CLKID_AIU_GLUE>, + <&clkc CLKID_IEC958>, + <&clkc CLKID_I2S_OUT>, + <&clkc CLKID_AMCLK>, + <&clkc CLKID_AIFIFO2>, + <&clkc CLKID_MIXER>, + <&clkc CLKID_MIXER_IFACE>, + <&clkc CLKID_ADC>, + <&clkc CLKID_AIU_TOP>, + <&clkc CLKID_AOCLK_GATE>, + <&clkc CLKID_I2S_SPDIF>; + clock-names = + "mpll", + "mclk", + "top_glue", + "aud_buf", + "i2s_out", + "amclk_measure", + "aififo2", + "aud_mixer", + "mixer_reg", + "adc", + "top_level", + "aoclk", + "aud_in"; + i2s_pos_sync = <0>; + /*DMIC;*/ /* I2s Mic or Dmic, default for I2S mic */ + }; + dmic:snd_dmic { + #sound-dai-cells = <0>; + compatible = "aml, aml_snd_dmic"; + reg = <0xd0042000 0x2000>; + status = "okay"; + resets = < + &clkc CLKID_PDM_GATE + >; + reset-names = "pdm"; + pinctrl-names = "audio_dmic"; + pinctrl-0 = <&aml_dmic_pins>; + clocks = <&clkc CLKID_PDM_COMP>, + <&clkc CLKID_AMCLK_COMP>; + clock-names = "pdm", "mclk"; + }; + spdif_dai: SPDIF { + #sound-dai-cells = <0>; + compatible = "amlogic, aml-spdif-dai"; + clocks = + <&clkc CLKID_MPLL1>, + <&clkc CLKID_I958_COMP>, + <&clkc CLKID_AMCLK_COMP>, + <&clkc CLKID_I958_COMP_SPDIF>, + <&clkc CLKID_CLK81>, + <&clkc CLKID_IEC958>, + <&clkc CLKID_IEC958_GATE>; + clock-names = + "mpll1", + "i958", + "mclk", + "spdif", + "clk_81", + "iec958", + "iec958_amclk"; + }; + pcm_dai: PCM { + #sound-dai-cells = <0>; + compatible = "amlogic, aml-pcm-dai"; + pinctrl-names = "audio_pcm"; + pinctrl-0 = <&audio_pcm_pins>; + clocks = + <&clkc CLKID_MPLL0>, + <&clkc CLKID_PCM_MCLK_COMP>, + <&clkc CLKID_PCM_SCLK_GATE>; + clock-names = + "mpll0", + "pcm_mclk", + "pcm_sclk"; + pcm_mode = <1>; /* 0=slave mode, 1=master mode */ + }; + i2s_plat: i2s_platform { + compatible = "amlogic, aml-i2s"; + interrupts = <0 29 1>; + }; + pcm_plat: pcm_platform { + compatible = "amlogic, aml-pcm"; + }; + spdif_codec: spdif_codec{ + #sound-dai-cells = <0>; + compatible = "amlogic, aml-spdif-codec"; + pinctrl-names = "audio_spdif"; + pinctrl-0 = <&audio_spdif_pins>; + }; + pcm_codec: pcm_codec{ + #sound-dai-cells = <0>; + compatible = "amlogic, pcm2BT-codec"; + }; + /* endof AUDIO MESON DEVICES */ + + /* AUDIO board specific */ + dummy_codec:dummy{ + #sound-dai-cells = <0>; + compatible = "amlogic, aml_dummy_codec"; + status = "disable"; + }; + amlogic_codec:t9015{ + #sound-dai-cells = <0>; + compatible = "amlogic, aml_codec_T9015"; + reg = <0xc8832000 0x14>; + status = "okay"; + }; + aml_sound_meson { + compatible = "aml, meson-snd-card"; + status = "okay"; + aml-sound-card,format = "i2s"; + aml_sound_card,name = "AML-MESONAUDIO"; + aml,audio-routing = + "Ext Spk","LOUTL", + "Ext Spk","LOUTR"; + + mute_gpio-gpios = <&gpio GPIOH_5 0>; + mute_inv; + hp_disable; + hp_paraments = <800 300 0 5 1>; + pinctrl-names = "audio_i2s"; + pinctrl-0 = <&audio_i2s_pins>; + cpu_list = <&cpudai0 &cpudai1 &cpudai2>; + codec_list = <&codec0 &codec1 &codec2>; + plat_list = <&i2s_plat &i2s_plat &pcm_plat>; + cpudai0: cpudai0 { + sound-dai = <&i2s_dai>; + }; + cpudai1: cpudai1 { + sound-dai = <&spdif_dai>; + }; + cpudai2: cpudai2 { + sound-dai = <&pcm_dai>; + }; + codec0: codec0 { + sound-dai = <&amlogic_codec>; + }; + codec1: codec1 { + sound-dai = <&spdif_codec>; + }; + codec2: codec2 { + sound-dai = <&pcm_codec>; + }; + }; + /* END OF AUDIO board specific */ + + rdma{ + compatible = "amlogic, meson, rdma"; + dev_name = "amlogic-rdma"; + status = "ok"; + interrupts = <0 89 1>; + interrupt-names = "rdma"; + }; + + amvenc_avc{ + compatible = "amlogic, amvenc_avc"; + dev_name = "amvenc_avc"; + status = "okay"; + interrupts = <0 45 1>; + interrupt-names = "mailbox_2"; + }; + + hevc_enc{ + compatible = "cnm, HevcEnc"; + dev_name = "HevcEnc"; + status = "okay"; + interrupts = <0 187 1>; + interrupt-names = "wave420l_irq"; + #address-cells=<1>; + #size-cells=<1>; + ranges; + io_reg_base{ + reg = <0xc8810000 0x4000>; + }; + }; + + picdec { + compatible = "amlogic, picdec"; + memory-region = <&picdec_cma_reserved>; + dev_name = "picdec"; + status = "okay"; + }; + + ppmgr { + compatible = "amlogic, ppmgr"; + memory-region = <&ppmgr_reserved>; + dev_name = "ppmgr"; + status = "okay"; + }; + + deinterlace { + compatible = "amlogic, deinterlace"; + status = "okay"; + flag_cma = <1>;/*0:use reserved;1:use cma*/ + //memory-region = <&di_reserved>; + memory-region = <&di_cma_reserved>; + interrupts = <0 46 1 0 6 1>; + interrupt-names = "de_irq", "timerc"; + /* + * nr_size(byte) = 1920*544*2(yuv422 8bit) | + * 1920*544*2*12/8(yuv422 10bit) + * | 1920*544*2*10/8(yuv422 10bit full pack mode) + */ + /* mtn_size(byte) = 1920*544/2 */ + /* count_size(byte) = 1920*544/2 */ + buffer-size = <3133440>; + hw-version = <2>; + }; + + ionvideo { + compatible = "amlogic, ionvideo"; + dev_name = "ionvideo"; + status = "okay"; + }; + + amlvideo { + compatible = "amlogic, amlvideo"; + dev_name = "amlvideo"; + status = "okay"; + }; + + amlvideo2_0 { + compatible = "amlogic, amlvideo2"; + dev_name = "amlvideo2"; + status = "okay"; + amlvideo2_id = <0>; + cma_mode = <1>; + }; + + amlvideo2_1 { + compatible = "amlogic, amlvideo2"; + dev_name = "amlvideo2"; + status = "okay"; + amlvideo2_id = <1>; + cma_mode = <1>; + }; + + /*if you want to use vdin just modify status to "ok"*/ + vdin0 { + compatible = "amlogic, vdin"; + /*memory-region = <&vdin0_cma_reserved>;*/ + dev_name = "vdin0"; + status = "ok"; + reserve-iomap = "true"; + flag_cma = <1>;/*1:share with codec_mm;2:cma alone*/ + /*MByte, if 10bit disable: 64M(YUV422), + *if 10bit enable: 64*1.5 = 96M(YUV422) + *if support 4K2K-YUV444-10bit-WR:3840*2160*4*4 ~= 128M + *if support 4K2K-YUV422-10bit-wr:3840*2160*3*4 ~= 96M + *if support 4K2K-YUV422-8BIT-WR:3840*2160*2*4 ~= 64M + *if support 1080p-YUV422-8BIT-WR:1920*1080*2*4 ~= 16M + */ + cma_size = <16>; + interrupts = <0 83 1>; + rdma-irq = <2>; + /*clocks = <&clkc CLKID_FCLK_DIV5>, + * <&clkc CLK_VDIN_MEAS_CLK>; + *clock-names = "fclk_div5", "cts_vdin_meas_clk"; + */ + vdin_id = <0>; + /*vdin write mem color depth support: + *bit0:support 8bit + *bit1:support 9bit + *bit2:support 10bit + *bit3:support 12bit + *bit4:support yuv422 10bit full pack mode (from txl new add) + */ + tv_bit_mode = <1>; + }; + vdin1 { + compatible = "amlogic, vdin"; + memory-region = <&vdin1_cma_reserved>; + dev_name = "vdin1"; + status = "ok"; + reserve-iomap = "true"; + flag_cma = <0>;/*1:share with codec_mm;0:cma alone*/ + interrupts = <0 85 1>; + rdma-irq = <4>; + /*clocks = <&clock CLK_FPLL_DIV5>, + * <&clock CLK_VDIN_MEAS_CLK>; + *clock-names = "fclk_div5", "cts_vdin_meas_clk"; + */ + vdin_id = <1>; + /*vdin write mem color depth support: + *bit0:support 8bit + *bit1:support 9bit + *bit2:support 10bit + *bit3:support 12bit + */ + tv_bit_mode = <1>; + }; + + amlvecm { + compatible = "amlogic, vecm"; + dev_name = "aml_vecm"; + status = "okay"; + gamma_en = <0>;/*1:enabel ;0:disable*/ + wb_en = <0>;/*1:enabel ;0:disable*/ + cm_en = <0>;/*1:enabel ;0:disable*/ + /*1:enabel osd lut 100 table;0:disable*/ + cfg_en_osd_100 = <1>; + /*0: 709/601 1: bt2020*/ + tx_op_color_primary = <0>; + }; + amdolby_vision { + compatible = "amlogic, dolby_vision_gxm"; + dev_name = "aml_amdolby_vision_driver"; + status = "okay"; + tv_mode = <0>;/*1:enabel ;0:disable*/ + }; + unifykey{ + compatible = "amlogic, unifykey"; + status = "ok"; + + unifykey-num = <16>; + unifykey-index-0 = <&keysn_0>; + unifykey-index-1 = <&keysn_1>; + unifykey-index-2 = <&keysn_2>; + unifykey-index-3 = <&keysn_3>; + unifykey-index-4 = <&keysn_4>; + unifykey-index-5 = <&keysn_5>; + unifykey-index-6 = <&keysn_6>; + unifykey-index-7 = <&keysn_7>; + unifykey-index-8 = <&keysn_8>; + unifykey-index-9 = <&keysn_9>; + unifykey-index-10= <&keysn_10>; + unifykey-index-11= <&keysn_11>; + unifykey-index-12= <&keysn_12>; + unifykey-index-13= <&keysn_13>; + unifykey-index-14= <&keysn_14>; + unifykey-index-15= <&keysn_15>; + + keysn_0: key_0{ + key-name = "usid"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_1:key_1{ + key-name = "mac"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_2:key_2{ + key-name = "hdcp"; + key-device = "secure"; + key-type = "sha1"; + key-permit = "read","write","del"; + }; + keysn_3:key_3{ + key-name = "secure_boot_set"; + key-device = "efuse"; + key-permit = "write"; + }; + keysn_4:key_4{ + key-name = "mac_bt"; + key-device = "normal"; + key-permit = "read","write","del"; + key-type = "mac"; + }; + keysn_5:key_5{ + key-name = "mac_wifi"; + key-device = "normal"; + key-permit = "read","write","del"; + key-type = "mac"; + }; + keysn_6:key_6{ + key-name = "hdcp2_tx"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_7:key_7{ + key-name = "hdcp2_rx"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_8:key_8{ + key-name = "widevinekeybox"; + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_9:key_9{ + key-name = "deviceid"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_10:key_10{ + key-name = "hdcp22_fw_private"; + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_11:key_11{ + key-name = "PlayReadykeybox25"; + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_12:key_12{ + key-name = "prpubkeybox";// PlayReady + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_13:key_13{ + key-name = "prprivkeybox";// PlayReady + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_14:key_14{ + key-name = "attestationkeybox";// attestation key + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_15:key_15{ + key-name = "region_code"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + };//End unifykey +}; +&efuse { + status = "ok"; +}; + +&pwm_ef { + status = "okay"; +}; + +&audio_data{ + status = "okay"; +}; +&i2c1 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/amlogic/gxm_q201_2g.dts b/arch/arm/boot/dts/amlogic/gxm_q201_2g.dts new file mode 100644 index 000000000000..12f3dc75b8c6 --- /dev/null +++ b/arch/arm/boot/dts/amlogic/gxm_q201_2g.dts @@ -0,0 +1,1234 @@ +/* + * arch/arm/boot/dts/amlogic/gxm_q201_2g.dts + * + * Copyright (C) 2017 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +/dts-v1/; + +#include "mesongxm.dtsi" +#include "partition_mbox_normal.dtsi" +/ { + model = "Amlogic"; + amlogic-dt-id = "gxm_q201_2g"; + compatible = "amlogic, Gxm"; + interrupt-parent = <&gic>; + #address-cells = <1>; + #size-cells = <1>; + + aliases { + serial0 = &uart_AO; + serial1 = &uart_A; + serial2 = &uart_B; + serial3 = &uart_C; + serial4 = &uart_AO_B; + }; + + ion_dev { + compatible = "amlogic, ion_dev"; + memory-region = <&ion_reserved>; + }; + + memory@00000000 { + device_type = "memory"; + linux,usable-memory = <0x0100000 0x7ff00000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + /* global autoconfigured region for contiguous allocations */ + ramoops@0x07400000 { + compatible = "ramoops"; + reg = <0x07400000 0x00100000>; + record-size = <0x8000>; + console-size = <0x8000>; + ftrace-size = <0x0>; + pmsg-size = <0x8000>; + }; + + secmon_reserved:linux,secmon { + compatible = "shared-dma-pool"; + reusable; + size = <0x400000>; + alignment = <0x400000>; + alloc-ranges = <0x05000000 0x400000>; + }; + secos_reserved:linux,secos { + status = "disable"; + compatible = "amlogic, aml_secos_memory"; + reg = <0x05300000 0x2000000>; + no-map; + }; + logo_reserved:linux,meson-fb { + compatible = "shared-dma-pool"; + reusable; + size = <0x800000>; + alignment = <0x400000>; + alloc-ranges = <0x7f800000 0x800000>; + }; + //don't put other dts in front of logo_reserved + + //di_reserved:linux,di { + // compatible = "amlogic, di-mem"; + /** 10x3133440=30M(0x1e) support 8bit **/ + // size = <0x1e00000>; + //no-map; + //}; + di_cma_reserved:linux,di_cma { + compatible = "shared-dma-pool"; + reusable; + /** 10x3133440=30M(0x1e) support 8bit **/ + size = <0x2000000>; + alignment = <0x400000>; + }; + ion_reserved:linux,ion-dev { + compatible = "shared-dma-pool"; + reusable; + size = <0x7C00000>; + alignment = <0x400000>; + }; + + /* vdin0 CMA pool */ + //vdin0_cma_reserved:linux,vdin0_cma { + // compatible = "shared-dma-pool"; + // linux,phandle = <4>; + // reusable; + /* 1920x1080x2x4 =16+4 M */ + // size = <0x01400000>; + // alignment = <0x400000>; + //}; + /* vdin1 CMA pool */ + vdin1_cma_reserved:linux,vdin1_cma { + compatible = "shared-dma-pool"; + reusable; + /* 1920x1080x2x4 =16 M */ + size = <0x01000000>; + alignment = <0x400000>; + }; + /* POST PROCESS MANAGER */ + ppmgr_reserved:linux,ppmgr { + compatible = "shared-dma-pool"; + size = <0x0>; + }; + + codec_mm_cma:linux,codec_mm_cma { + compatible = "shared-dma-pool"; + reusable; + /* ion_codec_mm max can alloc size 80M*/ + size = <0x13400000>; + alignment = <0x400000>; + linux,contiguous-region; + }; + picdec_cma_reserved:linux,picdec { + compatible = "shared-dma-pool"; + reusable; + size = <0x0>; + alignment = <0x0>; + linux,contiguous-region; + }; + /* codec shared reserved */ + codec_mm_reserved:linux,codec_mm_reserved { + compatible = "amlogic, codec-mm-reserved"; + size = <0x0>; + alignment = <0x100000>; + //no-map; + }; + }; + + bt-dev{ + compatible = "amlogic, bt-dev"; + dev_name = "bt-dev"; + status = "okay"; + gpio_reset = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>; + }; + + wifi{ + compatible = "amlogic, aml_wifi"; + dev_name = "aml_wifi"; + status = "okay"; + interrupt_pin = <&gpio GPIOX_7 GPIO_ACTIVE_HIGH>; + irq_trigger_type = "GPIO_IRQ_LOW"; + dhd_static_buf; + power_on_pin = <&gpio GPIOX_6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_32k_pins>; + pwm_config = <&wifi_pwm_conf>; + }; + + wifi_pwm_conf:wifi_pwm_conf{ + pwm_channel1_conf { + pwms = <&pwm_ef MESON_PWM_0 30040 0>; + duty-cycle = <15020>; + times = <8>; + }; + pwm_channel2_conf { + pwms = <&pwm_ef MESON_PWM_2 30030 0>; + duty-cycle = <15015>; + times = <12>; + }; + }; + + sd_emmc_c: emmc@d0074000 { + status = "okay"; + compatible = "amlogic, meson-mmc-gxm"; + reg = <0xd0074000 0x2000>; + interrupts = <0 218 1>; + pinctrl-names = "emmc_clk_cmd_pins", "emmc_all_pins"; + pinctrl-0 = <&emmc_clk_cmd_pins>; + pinctrl-1 = <&emmc_conf_pull_up &emmc_conf_pull_done>; + clocks = <&clkc CLKID_SD_EMMC_C>, + <&clkc CLKID_SD_EMMC_C_P0_COMP>, + <&clkc CLKID_FCLK_DIV2>; + clock-names = "core", "clkin0", "clkin1"; + + bus-width = <8>; + cap-sd-highspeed; + cap-mmc-highspeed; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + + max-frequency = <200000000>; + non-removable; + disable-wp; + emmc { + pinname = "emmc"; + ocr_avail = <0x200080>; /**VDD voltage 3.3 ~ 3.4 */ + caps = "MMC_CAP_8_BIT_DATA", + "MMC_CAP_MMC_HIGHSPEED", + "MMC_CAP_SD_HIGHSPEED", + "MMC_CAP_NONREMOVABLE", + "MMC_CAP_1_8V_DDR", + "MMC_CAP_HW_RESET", + "MMC_CAP_ERASE", + "MMC_CAP_CMD23"; + caps2 = "MMC_CAP2_HS200", "MMC_CAP2_HS400"; + f_min = <400000>; + f_max = <100000000>; + max_req_size = <0x20000>; /**128KB*/ + gpio_dat3 = <&gpio BOOT_3 GPIO_ACTIVE_HIGH>; + hw_reset = <&gpio BOOT_9 GPIO_ACTIVE_HIGH>; + card_type = <1>; + /* 1:mmc card(include eMMC), + * 2:sd card(include tSD) + */ + }; + }; + + sd_emmc_b:sd@d0072000 { + status = "okay"; + compatible = "amlogic, meson-mmc-gxm"; + reg = <0xd0072000 0x2000>; + interrupts = <0 217 1>; + pinctrl-names = "sd_all_pins", + "sd_clk_cmd_pins", + "sd_1bit_pins", + "sd_clk_cmd_uart_pins", + "sd_1bit_uart_pins", + "sd_to_ao_uart_pins", + "ao_to_sd_uart_pins", + "ao_to_sd_jtag_pins", + "sd_to_ao_jtag_pins"; + pinctrl-0 = <&sd_all_pins>; + pinctrl-1 = <&sd_clk_cmd_pins>; + pinctrl-2 = <&sd_1bit_pins>; + pinctrl-3 = <&sd_to_ao_uart_clr_pins + &sd_clk_cmd_pins &ao_to_sd_uart_pins>; + pinctrl-4 = <&sd_to_ao_uart_clr_pins + &sd_1bit_pins &ao_to_sd_uart_pins>; + pinctrl-5 = <&sd_all_pins &sd_to_ao_uart_pins>; + pinctrl-6 = <&sd_to_ao_uart_clr_pins &ao_to_sd_uart_pins>; + pinctrl-7 = <&sd_to_ao_uart_clr_pins &ao_to_sd_uart_pins>; + pinctrl-8 = <&sd_all_pins &sd_to_ao_uart_pins>; + clocks = <&clkc CLKID_SD_EMMC_B>, + <&clkc CLKID_SD_EMMC_B_P0_COMP>, + <&clkc CLKID_FCLK_DIV2>; + clock-names = "core", "clkin0", "clkin1"; + + bus-width = <4>; + cap-sd-highspeed; + max-frequency = <100000000>; + disable-wp; + sd { + pinname = "sd"; + ocr_avail = <0x200080>; /**VDD voltage 3.3 ~ 3.4 */ + caps = "MMC_CAP_4_BIT_DATA", + "MMC_CAP_MMC_HIGHSPEED", + "MMC_CAP_SD_HIGHSPEED"; + /* "MMC_CAP_UHS_SDR12", + * "MMC_CAP_UHS_SDR25", + * "MMC_CAP_UHS_SDR50", + * "MMC_CAP_UHS_SDR104"; + */ + f_min = <400000>; + f_max = <100000000>; + max_req_size = <0x20000>; /**128KB*/ + gpio_dat3 = <&gpio CARD_4 GPIO_ACTIVE_HIGH>; + jtag_pin = <&gpio CARD_0 GPIO_ACTIVE_HIGH>; + gpio_cd = <&gpio CARD_6 GPIO_ACTIVE_HIGH>; + card_type = <5>; + /* 0:unknown, + * 1:mmc card(include eMMC), + * 2:sd card(include tSD), + * 3:sdio device(ie:sdio-wifi), + * 4:SD combo (IO+mem) card, + * 5:NON sdio device(means sd/mmc card), + * other:reserved + */ + }; + }; + + sd_emmc_a:sdio@d0070000 { + status = "okay"; + compatible = "amlogic, meson-mmc-gxm"; + reg = <0xd0070000 0x2000>; + interrupts = <0 216 4>; + pinctrl-names = "sdio_clk_cmd_pins", "sdio_all_pins"; + pinctrl-0 = <&sdio_clk_cmd_pins>; + pinctrl-1 = <&sdio_all_pins>; + clocks = <&clkc CLKID_SD_EMMC_A>, + <&clkc CLKID_SD_EMMC_A_P0_COMP>, + <&clkc CLKID_FCLK_DIV2>; + clock-names = "core", "clkin0", "clkin1"; + + bus-width = <4>; + cap-sd-highspeed; + cap-mmc-highspeed; + max-frequency = <100000000>; + non-removable; + disable-wp; + sdio { + pinname = "sdio"; + ocr_avail = <0x200080>; /**VDD voltage 3.3 ~ 3.4 */ + caps = "MMC_CAP_4_BIT_DATA", + "MMC_CAP_MMC_HIGHSPEED", + "MMC_CAP_SD_HIGHSPEED", + "MMC_CAP_NONREMOVABLE", + "MMC_CAP_UHS_SDR12", + "MMC_CAP_UHS_SDR25", + "MMC_CAP_UHS_SDR50", + "MMC_CAP_UHS_SDR104", + "MMC_PM_KEEP_POWER", + "MMC_CAP_SDIO_IRQ"; + f_min = <400000>; + f_max = <200000000>; + max_req_size = <0x20000>; /**128KB*/ + card_type = <3>; + /* 3:sdio device(ie:sdio-wifi), + * 4:SD combo (IO+mem) card + */ + }; + }; + mtd_nand{ + compatible = "amlogic, aml_mtd_nand"; + dev_name = "mtdnand"; + status = "disabled"; + reg = <0xd0074800 0x200>; + interrupts = < 0 34 1 >; + pinctrl-names = "nand_rb_mod","nand_norb_mod", "nand_cs_only"; + pinctrl-0 = <&all_nand_pins>; + pinctrl-1 = <&all_nand_pins>; + pinctrl-2 = <&nand_cs_pins>; + device_id = <0>; + plat-names = "nandboot","nandnormal"; + plat-num = <2>; + plat-part-0 = <&nandboot>; + plat-part-1 = <&nandnormal>; + nandboot: nandboot{ + enable_pad ="ce0"; + busy_pad = "rb0"; + timming_mode = "mode5"; + bch_mode = "bch60_1k"; + t_rea = <20>; + t_rhoh = <15>; + chip_num = <1>; + part_num = <0>; + rb_detect = <1>; + }; + nandnormal: nandnormal{ + enable_pad ="ce0","ce1"; + busy_pad = "rb0","rb1"; + timming_mode = "mode5"; + bch_mode = "bch60_1k"; + plane_mode = "twoplane"; + t_rea = <20>; + t_rhoh = <15>; + chip_num = <2>; + part_num = <3>; + partition = <&nand_partitions>; + rb_detect = <1>; + }; + nand_partitions:nand_partition{ + logo{ + offset=<0x0 0x0>; + size=<0x0 0x200000>; + }; + recovery{ + offset=<0x0 0x0>; + size=<0x0 0x1000000>; + }; + boot{ + offset=<0x0 0x0>; + size=<0x0 0xC00000>; + }; + system{ + offset=<0x0 0x0>; + size=<0x0 0xDC40000>; + }; + data{ + offset=<0xffffffff 0xffffffff>; + size=<0x0 0x0>; + }; + }; + }; + + ethmac: ethernet@0xc9410000 { + compatible = "amlogic, gxbb-eth-dwmac"; + reg = <0xc9410000 0x10000 + 0xc8834540 0x8 + 0xc8834558 0xc>; + interrupts = <0 8 1>; + pinctrl-names = "external_eth_pins"; + pinctrl-0 = <&external_eth_pins>; + rst_pin-gpios = <&gpio GPIOZ_14 0>; + GPIOZ4_pin-gpios = <&gpio GPIOZ_4 0>; + GPIOZ5_pin-gpios = <&gpio GPIOZ_5 0>; + mc_val_internal_phy = <0x1800>; + mc_val_external_phy = <0x1621>; + cali_val = <0x20000>; + interrupt-names = "macirq"; + clocks = <&clkc CLKID_ETH>; + clock-names = "ethclk81"; + internal_phy=<0>; + }; + + codec_io { + compatible = "amlogic, codec_io"; + #address-cells=<1>; + #size-cells=<1>; + ranges; + io_cbus_base{ + reg = <0xC1100000 0x100000>; + }; + io_dos_base{ + reg = <0xc8820000 0x10000>; + }; + io_hiubus_base{ + reg = <0xc883c000 0x2000>; + }; + io_aobus_base{ + reg = <0xc8100000 0x100000>; + }; + io_vcbus_base{ + reg = <0xd0100000 0x40000>; + }; + io_dmc_base{ + reg = <0xc8838000 0x400>; + }; + }; + + codec_mm { + compatible = "amlogic, codec, mm"; + memory-region = <&codec_mm_cma &codec_mm_reserved>; + dev_name = "codec_mm"; + status = "okay"; + }; + + canvas{ + compatible = "amlogic, meson, canvas"; + dev_name = "amlogic-canvas"; + status = "ok"; + reg = <0xc8838000 0x400>; + }; + + mesonstream { + compatible = "amlogic, codec, streambuf"; + dev_name = "mesonstream"; + status = "okay"; + clocks = <&clkc CLKID_DOS_PARSER + &clkc CLKID_DEMUX + &clkc CLKID_DOS + &clkc CLKID_VDEC_MUX + &clkc CLKID_HCODEC_MUX + &clkc CLKID_HEVC_MUX>; + clock-names = "parser_top", + "demux", + "vdec", + "clk_vdec_mux", + "clk_hcodec_mux", + "clk_hevc_mux"; + }; + + vdec { + compatible = "amlogic, vdec"; + dev_name = "vdec.0"; + status = "okay"; + interrupts = <0 3 1 + 0 23 1 + 0 32 1 + 0 43 1 + 0 44 1 + 0 45 1>; + interrupt-names = "vsync", + "demux", + "parser", + "mailbox_0", + "mailbox_1", + "mailbox_2"; + }; + + aml_sensor0: aml-sensor@0 { + compatible = "amlogic, aml-thermal"; + device_name = "thermal"; + #thermal-sensor-cells = <1>; + cooling_devices { + cpufreq_cool_cluster0 { + min_state = <1000000>; + dyn_coeff = <140>; + cluster_id = <0>; + node_name = "cpufreq_cool0"; + device_type = "cpufreq"; + }; + cpufreq_cool_cluster1 { + min_state = <500000>; + dyn_coeff = <140>; + cluster_id = <1>; + node_name = "cpufreq_cool1"; + device_type = "cpufreq"; + }; + cpucore_cool_cluster0 { + min_state = <1>; + dyn_coeff = <0>; + cluster_id = <0>; + node_name = "cpucore_cool0"; + device_type = "cpucore"; + }; + cpucore_cool_cluster1 { + min_state = <1>; + dyn_coeff = <0>; + cluster_id = <1>; + node_name = "cpucore_cool1"; + device_type = "cpucore"; + }; + gpufreq_cool { + min_state = <400>; + dyn_coeff = <437>; + cluster_id = <0>; + node_name = "gpufreq_cool0"; + device_type = "gpufreq"; + }; + gpucore_cool { + min_state = <1>; + dyn_coeff = <0>; + cluster_id = <0>; + node_name = "gpucore_cool0"; + device_type = "gpucore"; + }; + }; + cpufreq_cool0:cpufreq_cool0 { + #cooling-cells = <2>; /* min followed by max */ + }; + cpufreq_cool1:cpufreq_cool1 { + #cooling-cells = <2>; /* min followed by max */ + }; + cpucore_cool0:cpucore_cool0 { + #cooling-cells = <2>; /* min followed by max */ + }; + cpucore_cool1:cpucore_cool1 { + #cooling-cells = <2>; /* min followed by max */ + }; + gpufreq_cool0:gpufreq_cool0 { + #cooling-cells = <2>; /* min followed by max */ + }; + gpucore_cool0:gpucore_cool0 { + #cooling-cells = <2>; /* min followed by max */ + }; + }; + thermal-zones { + soc_thermal { + polling-delay = <1000>; + polling-delay-passive = <100>; + sustainable-power = <2450>; + + thermal-sensors = <&aml_sensor0 3>; + + trips { + switch_on: trip-point@0 { + temperature = <70000>; + hysteresis = <1000>; + type = "passive"; + }; + control: trip-point@1 { + temperature = <80000>; + hysteresis = <1000>; + type = "passive"; + }; + hot: trip-point@2 { + temperature = <85000>; + hysteresis = <5000>; + type = "hot"; + }; + critical: trip-point@3 { + temperature = <260000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + + cooling-maps { + cpufreq_cooling_map0 { + trip = <&control>; + cooling-device = <&cpufreq_cool0 0 4>; + contribution = <1024>; + }; + cpufreq_cooling_map1 { + trip = <&control>; + cooling-device = <&cpufreq_cool1 0 4>; + contribution = <1024>; + }; + cpucore_cooling_map0 { + trip = <&control>; + cooling-device = <&cpucore_cool0 0 3>; + contribution = <1024>; + }; + cpucore_cooling_map1 { + trip = <&control>; + cooling-device = <&cpucore_cool1 0 3>; + contribution = <1024>; + }; + gpufreq_cooling_map { + trip = <&control>; + cooling-device = <&gpufreq_cool0 0 4>; + contribution = <1024>; + }; + gpucore_cooling_map { + trip = <&control>; + cooling-device = <&gpucore_cool0 0 2>; + contribution = <1024>; + }; + }; + }; + }; + + dwc3: dwc3@c9000000 { + compatible = "synopsys, dwc3"; + reg = <0xc9000000 0x100000>; + interrupts = <0 30 4>; + usb-phy = <&usb2_phy>, <&usb3_phy>; + cpu-type = "gxl"; + clock-src = "usb3.0"; + }; + + usb2_phy: usb2phy@d0078000 { + compatible = "amlogic, amlogic-new-usb2"; + portnum = <3>; + reg = <0xd0078000 0x80 + 0xc1104408 0x4>; + }; + + usb3_phy: usb3phy@d0078080 { + compatible = "amlogic, amlogic-new-usb3"; + portnum = <0>; + reg = <0xd0078080 0x20>; + interrupts = <0 16 4>; + otg = <1>; + gpio-vbus-power = "GPIOAO_5"; + gpios = <&gpio_ao GPIOAO_5 GPIO_ACTIVE_HIGH>; + }; + + dwc2_a { + compatible = "amlogic, dwc2"; + device_name = "dwc2_a"; + reg = <0xc9100000 0x40000>; + status = "okay"; + interrupts = <0 31 4>; + pl-periph-id = <0>; /** lm name */ + clock-src = "usb0"; /** clock src */ + port-id = <0>; /** ref to mach/usb.h */ + port-type = <2>; /** 0: otg, 1: host, 2: slave */ + port-speed = <0>; /** 0: default, high, 1: full */ + port-config = <0>; /** 0: default */ + port-dma = <0>; /** 0: default ... 6: disable*/ + port-id-mode = <0>; /** 0: hardware, 1: sw_host, 2: sw_slave*/ + usb-fifo = <728>; + cpu-type = "gxl"; + controller-type = <3>; /** 0: normal,1:host,2:device,3:otg*/ + phy-reg = <0xd0078000>; + phy-reg-size = <0xa0>; + clocks = <&clkc CLKID_USB_GENERAL + &clkc CLKID_USB1_TO_DDR + &clkc CLKID_USB1>; + clock-names = "usb_general", + "usb1", + "usb1_to_ddr"; + }; + + meson-amvideom { + compatible = "amlogic, amvideom"; + dev_name = "amvideom"; + status = "okay"; + interrupts = <0 3 1>; + interrupt-names = "vsync"; + }; + + vout { + compatible = "amlogic, vout"; + dev_name = "vout"; + status = "okay"; + fr_auto_policy = <0>; + }; + + cvbsout { + compatible = "amlogic, cvbsout-gxm"; + dev_name = "cvbsout"; + status = "okay"; + clocks = <&clkc CLKID_VCLK2_ENCI + &clkc CLKID_VCLK2_VENCI0 + &clkc CLKID_VCLK2_VENCI1 + &clkc CLKID_DAC_CLK>; + clock-names = "venci_top_gate", + "venci_0_gate", + "venci_1_gate", + "vdac_clk_gate"; + + /* performance: reg_address, reg_value */ + performance = <0x1bf0 0x9 + 0x1b56 0x343 + 0x1b12 0x8080 + 0x1b05 0xfd + 0x1c59 0xf752 + 0xffff 0x0>; /* ending flag */ + }; + + amhdmitx: amhdmitx{ + compatible = "amlogic, amhdmitx"; + dev_name = "amhdmitx"; + status = "okay"; + vend-data = <&vend_data>; + pinctrl-names="hdmitx_hpd", "hdmitx_ddc"; + pinctrl-0=<&hdmitx_hpd>; + pinctrl-1=<&hdmitx_ddc>; + /* HPD, 57 + 32 = 89; CEC, 151 + 32 = 183*/ + interrupts = <0 57 1>; + interrupt-names = "hdmitx_hpd"; + /* 0:M8B 1:GXBB 2:GXTVBB 3:GXL 4:GXM + * 5:TXL 6:TXLX 7:AXG 8:GXLX 9:TXHD + */ + ic_type = <4>; + vend_data: vend_data{ /* Should modified by Customer */ + vendor_name = "Amlogic"; /* Max Chars: 8 */ + /* standards.ieee.org/develop/regauth/oui/oui.txt */ + vendor_id = <0x000000>; + product_desc = "MBox Meson Ref"; /* Max Chars: 16 */ + }; + }; + + aocec: aocec{ + compatible = "amlogic, amlogic-aocec"; + device_name = "aocec"; + status = "okay"; + vendor_id = <0x000000>; + cec_osd_string = "MBox"; /* Max Chars: 14 */ + cec_version = <6>; /* 5: 1.4, 6: 2.0 */ + port_num = <1>; + arc_port_mask = <0x0>; + interrupts = <0 199 1>; + interrupt-names = "hdmi_aocec"; + pinctrl-names = "default"; + pinctrl-0=<&hdmitx_aocec>; + reg = <0xc810023c 0x4 + 0xc8100000 0x200>; + reg-names = "ao_exit","ao"; + }; + + sysled { + compatible = "amlogic, sysled"; + dev_name = "sysled"; + status = "disabled"; + led_gpio = <&gpio GPIODV_24 GPIO_ACTIVE_HIGH>; + led_active_low = <1>; + }; + + meson-fb { + compatible = "amlogic, meson-gxm"; + dev_name = "meson-fb"; + status = "okay"; + interrupts = <0 3 1 + 0 89 1>; + interrupt-names = "viu-vsync", "rdma"; + mem_size = <0x00800000 0x01851000 0x00100000>; + /* uboot logo,fb0/fb1 memory size,if afbcd fb0=0x01851000*/ + display_mode_default = "1080p60hz"; + scale_mode = <1>; + /** 0:VPU free scale 1:OSD free scale 2:OSD super scale */ + display_size_default = <1920 1080 1920 3240 32>; + /*1920*1080*4*3 = 0x17BB000*/ + logo_addr = "0x7f800000"; + }; + ge2d { + compatible = "amlogic, ge2d-gxm"; + dev_name = "ge2d"; + status = "okay"; + interrupts = <0 150 1>; + interrupt-names = "ge2d"; + clocks = <&clkc CLKID_VAPB_MUX>, + <&clkc CLKID_G2D>, + <&clkc CLKID_GE2D_GATE>; + clock-names = "clk_vapb_0", + "clk_ge2d", + "clk_ge2d_gate"; + }; + + + /* AUDIO MESON DEVICES */ + i2s_dai: I2S { + #sound-dai-cells = <0>; + compatible = "amlogic, aml-i2s-dai"; + clocks = + <&clkc CLKID_MPLL2>, + <&clkc CLKID_AMCLK_COMP>, + <&clkc CLKID_AIU_GLUE>, + <&clkc CLKID_IEC958>, + <&clkc CLKID_I2S_OUT>, + <&clkc CLKID_AMCLK>, + <&clkc CLKID_AIFIFO2>, + <&clkc CLKID_MIXER>, + <&clkc CLKID_MIXER_IFACE>, + <&clkc CLKID_ADC>, + <&clkc CLKID_AIU_TOP>, + <&clkc CLKID_AOCLK_GATE>, + <&clkc CLKID_I2S_SPDIF>; + clock-names = + "mpll", + "mclk", + "top_glue", + "aud_buf", + "i2s_out", + "amclk_measure", + "aififo2", + "aud_mixer", + "mixer_reg", + "adc", + "top_level", + "aoclk", + "aud_in"; + i2s_pos_sync = <0>; + /*DMIC;*/ /* I2s Mic or Dmic, default for I2S mic */ + }; + dmic:snd_dmic { + #sound-dai-cells = <0>; + compatible = "aml, aml_snd_dmic"; + reg = <0xd0042000 0x2000>; + status = "okay"; + resets = < + &clkc CLKID_PDM_GATE + >; + reset-names = "pdm"; + pinctrl-names = "audio_dmic"; + pinctrl-0 = <&aml_dmic_pins>; + clocks = <&clkc CLKID_PDM_COMP>, + <&clkc CLKID_AMCLK_COMP>; + clock-names = "pdm", "mclk"; + }; + spdif_dai: SPDIF { + #sound-dai-cells = <0>; + compatible = "amlogic, aml-spdif-dai"; + clocks = + <&clkc CLKID_MPLL1>, + <&clkc CLKID_I958_COMP>, + <&clkc CLKID_AMCLK_COMP>, + <&clkc CLKID_I958_COMP_SPDIF>, + <&clkc CLKID_CLK81>, + <&clkc CLKID_IEC958>, + <&clkc CLKID_IEC958_GATE>; + clock-names = + "mpll1", + "i958", + "mclk", + "spdif", + "clk_81", + "iec958", + "iec958_amclk"; + }; + pcm_dai: PCM { + #sound-dai-cells = <0>; + compatible = "amlogic, aml-pcm-dai"; + pinctrl-names = "audio_pcm"; + pinctrl-0 = <&audio_pcm_pins>; + clocks = + <&clkc CLKID_MPLL0>, + <&clkc CLKID_PCM_MCLK_COMP>, + <&clkc CLKID_PCM_SCLK_GATE>; + clock-names = + "mpll0", + "pcm_mclk", + "pcm_sclk"; + pcm_mode = <1>; /* 0=slave mode, 1=master mode */ + }; + i2s_plat: i2s_platform { + compatible = "amlogic, aml-i2s"; + interrupts = <0 29 1>; + }; + pcm_plat: pcm_platform { + compatible = "amlogic, aml-pcm"; + }; + spdif_codec: spdif_codec{ + #sound-dai-cells = <0>; + compatible = "amlogic, aml-spdif-codec"; + pinctrl-names = "audio_spdif"; + pinctrl-0 = <&audio_spdif_pins>; + }; + pcm_codec: pcm_codec{ + #sound-dai-cells = <0>; + compatible = "amlogic, pcm2BT-codec"; + }; + /* endof AUDIO MESON DEVICES */ + + /* AUDIO board specific */ + dummy_codec:dummy{ + #sound-dai-cells = <0>; + compatible = "amlogic, aml_dummy_codec"; + status = "disable"; + }; + amlogic_codec:t9015{ + #sound-dai-cells = <0>; + compatible = "amlogic, aml_codec_T9015"; + reg = <0xc8832000 0x14>; + status = "okay"; + }; + aml_sound_meson { + compatible = "aml, meson-snd-card"; + status = "okay"; + aml-sound-card,format = "i2s"; + aml_sound_card,name = "AML-MESONAUDIO"; + aml,audio-routing = + "Ext Spk","LOUTL", + "Ext Spk","LOUTR"; + + mute_gpio-gpios = <&gpio GPIOH_5 0>; + mute_inv; + hp_disable; + hp_paraments = <800 300 0 5 1>; + pinctrl-names = "audio_i2s"; + pinctrl-0 = <&audio_i2s_pins>; + cpu_list = <&cpudai0 &cpudai1 &cpudai2>; + codec_list = <&codec0 &codec1 &codec2>; + plat_list = <&i2s_plat &i2s_plat &pcm_plat>; + cpudai0: cpudai0 { + sound-dai = <&i2s_dai>; + }; + cpudai1: cpudai1 { + sound-dai = <&spdif_dai>; + }; + cpudai2: cpudai2 { + sound-dai = <&pcm_dai>; + }; + codec0: codec0 { + sound-dai = <&amlogic_codec>; + }; + codec1: codec1 { + sound-dai = <&spdif_codec>; + }; + codec2: codec2 { + sound-dai = <&pcm_codec>; + }; + }; + /* END OF AUDIO board specific */ + + rdma{ + compatible = "amlogic, meson, rdma"; + dev_name = "amlogic-rdma"; + status = "ok"; + interrupts = <0 89 1>; + interrupt-names = "rdma"; + }; + + amvenc_avc{ + compatible = "amlogic, amvenc_avc"; + dev_name = "amvenc_avc"; + status = "okay"; + interrupts = <0 45 1>; + interrupt-names = "mailbox_2"; + }; + + hevc_enc{ + compatible = "cnm, HevcEnc"; + dev_name = "HevcEnc"; + status = "okay"; + interrupts = <0 187 1>; + interrupt-names = "wave420l_irq"; + #address-cells=<1>; + #size-cells=<1>; + ranges; + io_reg_base{ + reg = <0xc8810000 0x4000>; + }; + }; + + picdec { + compatible = "amlogic, picdec"; + memory-region = <&picdec_cma_reserved>; + dev_name = "picdec"; + status = "okay"; + }; + + ppmgr { + compatible = "amlogic, ppmgr"; + memory-region = <&ppmgr_reserved>; + dev_name = "ppmgr"; + status = "okay"; + }; + + deinterlace { + compatible = "amlogic, deinterlace"; + status = "okay"; + flag_cma = <1>;/*0:use reserved;1:use cma*/ + //memory-region = <&di_reserved>; + memory-region = <&di_cma_reserved>; + interrupts = <0 46 1 0 6 1>; + interrupt-names = "de_irq", "timerc"; + /* + * nr_size(byte) = 1920*544*2(yuv422 8bit) | + * 1920*544*2*12/8(yuv422 10bit) + * | 1920*544*2*10/8(yuv422 10bit full pack mode) + */ + /* mtn_size(byte) = 1920*544/2 */ + /* count_size(byte) = 1920*544/2 */ + buffer-size = <3133440>; + hw-version = <2>; + }; + + ionvideo { + compatible = "amlogic, ionvideo"; + dev_name = "ionvideo"; + status = "okay"; + }; + + amlvideo { + compatible = "amlogic, amlvideo"; + dev_name = "amlvideo"; + status = "okay"; + }; + + amlvideo2_0 { + compatible = "amlogic, amlvideo2"; + dev_name = "amlvideo2"; + status = "okay"; + amlvideo2_id = <0>; + cma_mode = <1>; + }; + + amlvideo2_1 { + compatible = "amlogic, amlvideo2"; + dev_name = "amlvideo2"; + status = "okay"; + amlvideo2_id = <1>; + cma_mode = <1>; + }; + + /*if you want to use vdin just modify status to "ok"*/ + vdin0 { + compatible = "amlogic, vdin"; + /*memory-region = <&vdin0_cma_reserved>;*/ + dev_name = "vdin0"; + status = "ok"; + reserve-iomap = "true"; + flag_cma = <1>;/*1:share with codec_mm;2:cma alone*/ + /*MByte, if 10bit disable: 64M(YUV422), + *if 10bit enable: 64*1.5 = 96M(YUV422) + *if support 4K2K-YUV444-10bit-WR:3840*2160*4*4 ~= 128M + *if support 4K2K-YUV422-10bit-wr:3840*2160*3*4 ~= 96M + *if support 4K2K-YUV422-8BIT-WR:3840*2160*2*4 ~= 64M + *if support 1080p-YUV422-8BIT-WR:1920*1080*2*4 ~= 16M + */ + cma_size = <16>; + interrupts = <0 83 1>; + rdma-irq = <2>; + /*clocks = <&clkc CLKID_FCLK_DIV5>, + * <&clkc CLK_VDIN_MEAS_CLK>; + *clock-names = "fclk_div5", "cts_vdin_meas_clk"; + */ + vdin_id = <0>; + /*vdin write mem color depth support: + *bit0:support 8bit + *bit1:support 9bit + *bit2:support 10bit + *bit3:support 12bit + *bit4:support yuv422 10bit full pack mode (from txl new add) + */ + tv_bit_mode = <1>; + }; + vdin1 { + compatible = "amlogic, vdin"; + memory-region = <&vdin1_cma_reserved>; + dev_name = "vdin1"; + status = "ok"; + reserve-iomap = "true"; + flag_cma = <0>;/*1:share with codec_mm;0:cma alone*/ + interrupts = <0 85 1>; + rdma-irq = <4>; + /*clocks = <&clock CLK_FPLL_DIV5>, + * <&clock CLK_VDIN_MEAS_CLK>; + *clock-names = "fclk_div5", "cts_vdin_meas_clk"; + */ + vdin_id = <1>; + /*vdin write mem color depth support: + *bit0:support 8bit + *bit1:support 9bit + *bit2:support 10bit + *bit3:support 12bit + */ + tv_bit_mode = <1>; + }; + + amlvecm { + compatible = "amlogic, vecm"; + dev_name = "aml_vecm"; + status = "okay"; + gamma_en = <0>;/*1:enabel ;0:disable*/ + wb_en = <0>;/*1:enabel ;0:disable*/ + cm_en = <0>;/*1:enabel ;0:disable*/ + /*1:enabel osd lut 100 table;0:disable*/ + cfg_en_osd_100 = <1>; + /*0: 709/601 1: bt2020*/ + tx_op_color_primary = <0>; + }; + amdolby_vision { + compatible = "amlogic, dolby_vision_gxm"; + dev_name = "aml_amdolby_vision_driver"; + status = "okay"; + tv_mode = <0>;/*1:enabel ;0:disable*/ + }; + unifykey{ + compatible = "amlogic, unifykey"; + status = "ok"; + + unifykey-num = <16>; + unifykey-index-0 = <&keysn_0>; + unifykey-index-1 = <&keysn_1>; + unifykey-index-2 = <&keysn_2>; + unifykey-index-3 = <&keysn_3>; + unifykey-index-4 = <&keysn_4>; + unifykey-index-5 = <&keysn_5>; + unifykey-index-6 = <&keysn_6>; + unifykey-index-7 = <&keysn_7>; + unifykey-index-8 = <&keysn_8>; + unifykey-index-9 = <&keysn_9>; + unifykey-index-10= <&keysn_10>; + unifykey-index-11= <&keysn_11>; + unifykey-index-12= <&keysn_12>; + unifykey-index-13= <&keysn_13>; + unifykey-index-14= <&keysn_14>; + unifykey-index-15= <&keysn_15>; + + keysn_0: key_0{ + key-name = "usid"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_1:key_1{ + key-name = "mac"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_2:key_2{ + key-name = "hdcp"; + key-device = "secure"; + key-type = "sha1"; + key-permit = "read","write","del"; + }; + keysn_3:key_3{ + key-name = "secure_boot_set"; + key-device = "efuse"; + key-permit = "write"; + }; + keysn_4:key_4{ + key-name = "mac_bt"; + key-device = "normal"; + key-permit = "read","write","del"; + key-type = "mac"; + }; + keysn_5:key_5{ + key-name = "mac_wifi"; + key-device = "normal"; + key-permit = "read","write","del"; + key-type = "mac"; + }; + keysn_6:key_6{ + key-name = "hdcp2_tx"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_7:key_7{ + key-name = "hdcp2_rx"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_8:key_8{ + key-name = "widevinekeybox"; + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_9:key_9{ + key-name = "deviceid"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_10:key_10{ + key-name = "hdcp22_fw_private"; + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_11:key_11{ + key-name = "PlayReadykeybox25"; + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_12:key_12{ + key-name = "prpubkeybox";// PlayReady + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_13:key_13{ + key-name = "prprivkeybox";// PlayReady + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_14:key_14{ + key-name = "attestationkeybox";// attestation key + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_15:key_15{ + key-name = "region_code"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + };//End unifykey +}; +&efuse { + status = "ok"; +}; + +&pwm_ef { + status = "okay"; +}; + +&audio_data{ + status = "okay"; +}; +&i2c1 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/amlogic/gxm_skt.dts b/arch/arm/boot/dts/amlogic/gxm_skt.dts new file mode 100644 index 000000000000..b6ff2bba3430 --- /dev/null +++ b/arch/arm/boot/dts/amlogic/gxm_skt.dts @@ -0,0 +1,1053 @@ +/* + * arch/arm/boot/dts/amlogic/gxm_skt.dts + * + * Copyright (C) 2017 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +/dts-v1/; + +#include +#include "mesongxm.dtsi" + +/ { + model = "Amlogic"; + compatible = "amlogic, Gxm"; + interrupt-parent = <&gic>; + #address-cells = <1>; + #size-cells = <1>; + + aliases { + serial0 = &uart_AO; + serial1 = &uart_A; + serial2 = &uart_B; + serial3 = &uart_C; + serial4 = &uart_AO_B; + }; + + ion_dev { + compatible = "amlogic, ion_dev"; + memory-region = <&ion_reserved>; + }; + + memory@00000000 { + device_type = "memory"; + linux,usable-memory = <0x100000 0x3ff00000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + /* global autoconfigured region for contiguous allocations */ + ramoops@0x07400000 { + compatible = "ramoops"; + reg = <0x07400000 0x00100000>; + record-size = <0x8000>; + console-size = <0x8000>; + ftrace-size = <0x0>; + pmsg-size = <0x8000>; + }; + + secmon_reserved:linux,secmon { + compatible = "shared-dma-pool"; + reusable; + size = <0x400000>; + alignment = <0x400000>; + alloc-ranges = <0x05000000 0x400000>; + }; + secos_reserved:linux,secos { + status = "disable"; + compatible = "amlogic, aml_secos_memory"; + reg = <0x05300000 0x2000000>; + no-map; + }; + logo_reserved:linux,meson-fb { + compatible = "shared-dma-pool"; + reusable; + size = <0x800000>; + alignment = <0x400000>; + alloc-ranges = <0x3f800000 0x800000>; + }; + //don't put other dts in front of logo_reserved + + //di_reserved:linux,di { + // compatible = "amlogic, di-mem"; + /** 10x3133440=30M(0x1e) support 8bit **/ + // size = <0x1e00000>; + //no-map; + //}; + di_cma_reserved:linux,di_cma { + compatible = "shared-dma-pool"; + reusable; + /** 10x3133440=30M(0x1e) support 8bit **/ + size = <0x2000000>; + alignment = <0x400000>; + }; + ion_reserved:linux,ion-dev { + compatible = "shared-dma-pool"; + reusable; + size = <0x7C00000>; + alignment = <0x400000>; + }; + + /* vdin0 CMA pool */ + //vdin0_cma_reserved:linux,vdin0_cma { + // compatible = "shared-dma-pool"; + // linux,phandle = <4>; + // reusable; + /* 1920x1080x2x4 =16+4 M */ + // size = <0x01400000>; + // alignment = <0x400000>; + //}; + /* vdin1 CMA pool */ + vdin1_cma_reserved:linux,vdin1_cma { + compatible = "shared-dma-pool"; + reusable; + /* 1920x1080x2x4 =16 M */ + size = <0x01000000>; + alignment = <0x400000>; + }; + /* POST PROCESS MANAGER */ + ppmgr_reserved:linux,ppmgr { + compatible = "shared-dma-pool"; + size = <0x0>; + }; + + codec_mm_cma:linux,codec_mm_cma { + compatible = "shared-dma-pool"; + reusable; + /* ion_codec_mm max can alloc size 80M*/ + size = <0x13400000>; + alignment = <0x400000>; + linux,contiguous-region; + }; + picdec_cma_reserved:linux,picdec { + compatible = "shared-dma-pool"; + reusable; + size = <0x0>; + alignment = <0x0>; + linux,contiguous-region; + }; + /* codec shared reserved */ + codec_mm_reserved:linux,codec_mm_reserved { + compatible = "amlogic, codec-mm-reserved"; + size = <0x0>; + alignment = <0x100000>; + //no-map; + }; + }; + + sd_emmc_c: emmc@d0074000 { + status = "okay"; + compatible = "amlogic, meson-mmc-gxm"; + reg = <0xd0074000 0x2000>; + interrupts = <0 218 1>; + pinctrl-names = "emmc_clk_cmd_pins", "emmc_all_pins"; + pinctrl-0 = <&emmc_clk_cmd_pins>; + pinctrl-1 = <&emmc_conf_pull_up &emmc_conf_pull_done>; + clocks = <&clkc CLKID_SD_EMMC_C>, + <&clkc CLKID_SD_EMMC_C_P0_COMP>, + <&clkc CLKID_FCLK_DIV2>; + clock-names = "core", "clkin0", "clkin1"; + + bus-width = <8>; + cap-sd-highspeed; + cap-mmc-highspeed; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + + max-frequency = <200000000>; + non-removable; + disable-wp; + emmc { + pinname = "emmc"; + ocr_avail = <0x200080>; /**VDD voltage 3.3 ~ 3.4 */ + caps = "MMC_CAP_8_BIT_DATA", + "MMC_CAP_MMC_HIGHSPEED", + "MMC_CAP_SD_HIGHSPEED", + "MMC_CAP_NONREMOVABLE", + "MMC_CAP_1_8V_DDR", + "MMC_CAP_HW_RESET", + "MMC_CAP_ERASE", + "MMC_CAP_CMD23"; + caps2 = "MMC_CAP2_HS200", "MMC_CAP2_HS400"; + f_min = <400000>; + f_max = <100000000>; + max_req_size = <0x20000>; /**128KB*/ + gpio_dat3 = <&gpio BOOT_3 GPIO_ACTIVE_HIGH>; + hw_reset = <&gpio BOOT_9 GPIO_ACTIVE_HIGH>; + card_type = <1>; + /* 1:mmc card(include eMMC), + * 2:sd card(include tSD) + */ + }; + }; + + sd_emmc_b:sd@d0072000 { + status = "okay"; + compatible = "amlogic, meson-mmc-gxm"; + reg = <0xd0072000 0x2000>; + interrupts = <0 217 1>; + pinctrl-names = "sd_all_pins", + "sd_clk_cmd_pins", + "sd_1bit_pins", + "sd_clk_cmd_uart_pins", + "sd_1bit_uart_pins", + "sd_to_ao_uart_pins", + "ao_to_sd_uart_pins", + "ao_to_sd_jtag_pins", + "sd_to_ao_jtag_pins"; + pinctrl-0 = <&sd_all_pins>; + pinctrl-1 = <&sd_clk_cmd_pins>; + pinctrl-2 = <&sd_1bit_pins>; + pinctrl-3 = <&sd_to_ao_uart_clr_pins + &sd_clk_cmd_pins &ao_to_sd_uart_pins>; + pinctrl-4 = <&sd_to_ao_uart_clr_pins + &sd_1bit_pins &ao_to_sd_uart_pins>; + pinctrl-5 = <&sd_all_pins &sd_to_ao_uart_pins>; + pinctrl-6 = <&sd_to_ao_uart_clr_pins &ao_to_sd_uart_pins>; + pinctrl-7 = <&sd_to_ao_uart_clr_pins &ao_to_sd_uart_pins>; + pinctrl-8 = <&sd_all_pins &sd_to_ao_uart_pins>; + clocks = <&clkc CLKID_SD_EMMC_B>, + <&clkc CLKID_SD_EMMC_B_P0_COMP>, + <&clkc CLKID_FCLK_DIV2>; + clock-names = "core", "clkin0", "clkin1"; + + bus-width = <4>; + cap-sd-highspeed; + max-frequency = <100000000>; + disable-wp; + sd { + pinname = "sd"; + ocr_avail = <0x200080>; /**VDD voltage 3.3 ~ 3.4 */ + caps = "MMC_CAP_4_BIT_DATA", + "MMC_CAP_MMC_HIGHSPEED", + "MMC_CAP_SD_HIGHSPEED"; + /* "MMC_CAP_UHS_SDR12", + * "MMC_CAP_UHS_SDR25", + * "MMC_CAP_UHS_SDR50", + * "MMC_CAP_UHS_SDR104"; + */ + f_min = <400000>; + f_max = <100000000>; + max_req_size = <0x20000>; /**128KB*/ + gpio_dat3 = <&gpio CARD_4 GPIO_ACTIVE_HIGH>; + jtag_pin = <&gpio CARD_0 GPIO_ACTIVE_HIGH>; + gpio_cd = <&gpio CARD_6 GPIO_ACTIVE_HIGH>; + card_type = <5>; + /* 0:unknown, + * 1:mmc card(include eMMC), + * 2:sd card(include tSD), + * 3:sdio device(ie:sdio-wifi), + * 4:SD combo (IO+mem) card, + * 5:NON sdio device(means sd/mmc card), + * other:reserved + */ + }; + }; + + sd_emmc_a:sdio@d0070000 { + status = "okay"; + compatible = "amlogic, meson-mmc-gxm"; + reg = <0xd0070000 0x2000>; + interrupts = <0 216 4>; + pinctrl-names = "sdio_clk_cmd_pins", "sdio_all_pins"; + pinctrl-0 = <&sdio_clk_cmd_pins>; + pinctrl-1 = <&sdio_all_pins>; + clocks = <&clkc CLKID_SD_EMMC_A>, + <&clkc CLKID_SD_EMMC_A_P0_COMP>, + <&clkc CLKID_FCLK_DIV2>; + clock-names = "core", "clkin0", "clkin1"; + + bus-width = <4>; + cap-sd-highspeed; + cap-mmc-highspeed; + max-frequency = <100000000>; + non-removable; + disable-wp; + sdio { + pinname = "sdio"; + ocr_avail = <0x200080>; /**VDD voltage 3.3 ~ 3.4 */ + caps = "MMC_CAP_4_BIT_DATA", + "MMC_CAP_MMC_HIGHSPEED", + "MMC_CAP_SD_HIGHSPEED", + "MMC_CAP_NONREMOVABLE", + "MMC_CAP_UHS_SDR12", + "MMC_CAP_UHS_SDR25", + "MMC_CAP_UHS_SDR50", + "MMC_CAP_UHS_SDR104", + "MMC_PM_KEEP_POWER", + "MMC_CAP_SDIO_IRQ"; + f_min = <400000>; + f_max = <200000000>; + max_req_size = <0x20000>; /**128KB*/ + card_type = <3>; + /* 3:sdio device(ie:sdio-wifi), + * 4:SD combo (IO+mem) card + */ + }; + }; + mtd_nand{ + compatible = "amlogic, aml_mtd_nand"; + dev_name = "mtdnand"; + status = "disabled"; + reg = <0xd0074800 0x200>; + interrupts = < 0 34 1 >; + pinctrl-names = "nand_rb_mod","nand_norb_mod", "nand_cs_only"; + pinctrl-0 = <&all_nand_pins>; + pinctrl-1 = <&all_nand_pins>; + pinctrl-2 = <&nand_cs_pins>; + device_id = <0>; + plat-names = "bootloader","nandnormal"; + plat-num = <2>; + plat-part-0 = <&bootloader>; + plat-part-1 = <&nandnormal>; + bootloader: bootloader{ + enable_pad ="ce0"; + busy_pad = "rb0"; + timming_mode = "mode5"; + bch_mode = "bch60_1k"; + t_rea = <20>; + t_rhoh = <15>; + chip_num = <1>; + part_num = <0>; + rb_detect = <1>; + }; + nandnormal: nandnormal{ + enable_pad ="ce0","ce1"; + busy_pad = "rb0","rb1"; + timming_mode = "mode5"; + bch_mode = "bch60_1k"; + plane_mode = "twoplane"; + t_rea = <20>; + t_rhoh = <15>; + chip_num = <2>; + part_num = <3>; + partition = <&nand_partitions>; + rb_detect = <1>; + }; + nand_partitions:nand_partition{ + logo{ + offset=<0x0 0x0>; + size=<0x0 0x200000>; + }; + recovery{ + offset=<0x0 0x0>; + size=<0x0 0x1000000>; + }; + boot{ + offset=<0x0 0x0>; + size=<0x0 0xC00000>; + }; + system{ + offset=<0x0 0x0>; + size=<0x0 0xDC40000>; + }; + data{ + offset=<0xffffffff 0xffffffff>; + size=<0x0 0x0>; + }; + }; + }; + + codec_io { + compatible = "amlogic, codec_io"; + #address-cells=<1>; + #size-cells=<1>; + ranges; + io_cbus_base{ + reg = <0xC1100000 0x100000>; + }; + io_dos_base{ + reg = <0xc8820000 0x10000>; + }; + io_hiubus_base{ + reg = <0xc883c000 0x2000>; + }; + io_aobus_base{ + reg = <0xc8100000 0x100000>; + }; + io_vcbus_base{ + reg = <0xd0100000 0x40000>; + }; + io_dmc_base{ + reg = <0xc8838000 0x400>; + }; + }; + + codec_mm { + compatible = "amlogic, codec, mm"; + memory-region = <&codec_mm_cma &codec_mm_reserved>; + dev_name = "codec_mm"; + status = "okay"; + }; + + canvas{ + compatible = "amlogic, meson, canvas"; + dev_name = "amlogic-canvas"; + status = "ok"; + reg = <0xc8838000 0x400>; + }; + + mesonstream { + compatible = "amlogic, codec, streambuf"; + dev_name = "mesonstream"; + status = "okay"; + clocks = <&clkc CLKID_DOS_PARSER + &clkc CLKID_DEMUX + &clkc CLKID_DOS + &clkc CLKID_VDEC_MUX + &clkc CLKID_HCODEC_MUX + &clkc CLKID_HEVC_MUX>; + clock-names = "parser_top", + "demux", + "vdec", + "clk_vdec_mux", + "clk_hcodec_mux", + "clk_hevc_mux"; + }; + + vdec { + compatible = "amlogic, vdec"; + dev_name = "vdec.0"; + status = "okay"; + interrupts = <0 3 1 + 0 23 1 + 0 32 1 + 0 43 1 + 0 44 1 + 0 45 1>; + interrupt-names = "vsync", + "demux", + "parser", + "mailbox_0", + "mailbox_1", + "mailbox_2"; + }; + + aml_sensor0: aml-sensor@0 { + compatible = "amlogic, aml-thermal"; + device_name = "thermal"; + #thermal-sensor-cells = <1>; + cooling_devices { + cpufreq_cool_cluster0 { + min_state = <1000000>; + dyn_coeff = <140>; + cluster_id = <0>; + node_name = "cpufreq_cool0"; + device_type = "cpufreq"; + }; + cpufreq_cool_cluster1 { + min_state = <500000>; + dyn_coeff = <140>; + cluster_id = <1>; + node_name = "cpufreq_cool1"; + device_type = "cpufreq"; + }; + cpucore_cool_cluster0 { + min_state = <1>; + dyn_coeff = <0>; + cluster_id = <0>; + node_name = "cpucore_cool0"; + device_type = "cpucore"; + }; + cpucore_cool_cluster1 { + min_state = <1>; + dyn_coeff = <0>; + cluster_id = <1>; + node_name = "cpucore_cool1"; + device_type = "cpucore"; + }; + gpufreq_cool { + min_state = <400>; + dyn_coeff = <437>; + cluster_id = <0>; + node_name = "gpufreq_cool0"; + device_type = "gpufreq"; + }; + gpucore_cool { + min_state = <1>; + dyn_coeff = <0>; + cluster_id = <0>; + node_name = "gpucore_cool0"; + device_type = "gpucore"; + }; + }; + cpufreq_cool0:cpufreq_cool0 { + #cooling-cells = <2>; /* min followed by max */ + }; + cpufreq_cool1:cpufreq_cool1 { + #cooling-cells = <2>; /* min followed by max */ + }; + cpucore_cool0:cpucore_cool0 { + #cooling-cells = <2>; /* min followed by max */ + }; + cpucore_cool1:cpucore_cool1 { + #cooling-cells = <2>; /* min followed by max */ + }; + gpufreq_cool0:gpufreq_cool0 { + #cooling-cells = <2>; /* min followed by max */ + }; + gpucore_cool0:gpucore_cool0 { + #cooling-cells = <2>; /* min followed by max */ + }; + }; + thermal-zones { + soc_thermal { + polling-delay = <1000>; + polling-delay-passive = <100>; + sustainable-power = <2450>; + + thermal-sensors = <&aml_sensor0 3>; + + trips { + switch_on: trip-point@0 { + temperature = <70000>; + hysteresis = <1000>; + type = "passive"; + }; + control: trip-point@1 { + temperature = <80000>; + hysteresis = <1000>; + type = "passive"; + }; + hot: trip-point@2 { + temperature = <85000>; + hysteresis = <5000>; + type = "hot"; + }; + critical: trip-point@3 { + temperature = <260000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + + cooling-maps { + cpufreq_cooling_map0 { + trip = <&control>; + cooling-device = <&cpufreq_cool0 0 4>; + contribution = <1024>; + }; + cpufreq_cooling_map1 { + trip = <&control>; + cooling-device = <&cpufreq_cool1 0 4>; + contribution = <1024>; + }; + cpucore_cooling_map0 { + trip = <&control>; + cooling-device = <&cpucore_cool0 0 3>; + contribution = <1024>; + }; + cpucore_cooling_map1 { + trip = <&control>; + cooling-device = <&cpucore_cool1 0 3>; + contribution = <1024>; + }; + gpufreq_cooling_map { + trip = <&control>; + cooling-device = <&gpufreq_cool0 0 4>; + contribution = <1024>; + }; + gpucore_cooling_map { + trip = <&control>; + cooling-device = <&gpucore_cool0 0 2>; + contribution = <1024>; + }; + }; + }; + }; + + meson-amvideom { + compatible = "amlogic, amvideom"; + dev_name = "amvideom"; + status = "okay"; + interrupts = <0 3 1>; + interrupt-names = "vsync"; + }; + + vout { + compatible = "amlogic, vout"; + dev_name = "vout"; + status = "okay"; + fr_auto_policy = <0>; + }; + + cvbsout { + compatible = "amlogic, cvbsout-gxm"; + dev_name = "cvbsout"; + status = "okay"; + clocks = <&clkc CLKID_VCLK2_ENCI + &clkc CLKID_VCLK2_VENCI0 + &clkc CLKID_VCLK2_VENCI1 + &clkc CLKID_DAC_CLK>; + clock-names = "venci_top_gate", + "venci_0_gate", + "venci_1_gate", + "vdac_clk_gate"; + + /* performance: reg_address, reg_value */ + performance = <0x1bf0 0x9 + 0x1b56 0x343 + 0x1b12 0x8080 + 0x1b05 0xfd + 0x1c59 0xf752 + 0xffff 0x0>; /* ending flag */ + }; + + amhdmitx: amhdmitx{ + compatible = "amlogic, amhdmitx"; + dev_name = "amhdmitx"; + status = "okay"; + vend-data = <&vend_data>; + pinctrl-names="hdmitx_hpd", "hdmitx_ddc"; + pinctrl-0=<&hdmitx_hpd>; + pinctrl-1=<&hdmitx_ddc>; + /* HPD, 57 + 32 = 89; CEC, 151 + 32 = 183*/ + interrupts = <0 57 1>; + interrupt-names = "hdmitx_hpd"; + vend_data: vend_data{ /* Should modified by Customer */ + vendor_name = "Amlogic"; /* Max Chars: 8 */ + /* standards.ieee.org/develop/regauth/oui/oui.txt */ + vendor_id = <0x000000>; + product_desc = "MBox Meson Ref"; /* Max Chars: 16 */ + }; + }; + + aocec: aocec{ + compatible = "amlogic, amlogic-aocec"; + device_name = "aocec"; + status = "okay"; + vendor_id = <0x000000>; + cec_osd_string = "MBox"; /* Max Chars: 14 */ + cec_version = <6>; /* 5: 1.4, 6: 2.0 */ + port_num = <1>; + arc_port_mask = <0x0>; + interrupts = <0 199 1>; + interrupt-names = "hdmi_aocec"; + pinctrl-names = "default"; + pinctrl-0=<&hdmitx_aocec>; + reg = <0xc810023c 0x4 + 0xc8100000 0x200>; + reg-names = "ao_exit","ao"; + }; + + meson-fb { + compatible = "amlogic, meson-gxm"; + memory-region = <&logo_reserved>; + dev_name = "meson-fb"; + status = "okay"; + interrupts = <0 3 1 + 0 89 1>; + interrupt-names = "viu-vsync", "rdma"; + mem_size = <0x00800000 0x01851000 0x00100000>; + /* uboot logo,fb0/fb1 memory size,if afbcd fb0=0x01851000*/ + display_mode_default = "1080p60hz"; + scale_mode = <1>; + /** 0:VPU free scale 1:OSD free scale 2:OSD super scale */ + display_size_default = <1920 1080 1920 3240 32>; + /*1920*1080*4*3 = 0x17BB000*/ + logo_addr = "0x3f800000"; + }; + ge2d { + compatible = "amlogic, ge2d-gxm"; + dev_name = "ge2d"; + status = "okay"; + interrupts = <0 150 1>; + interrupt-names = "ge2d"; + clocks = <&clkc CLKID_VAPB_MUX>, + <&clkc CLKID_G2D>, + <&clkc CLKID_GE2D_GATE>; + clock-names = "clk_vapb_0", + "clk_ge2d", + "clk_ge2d_gate"; + }; + + + /* AUDIO MESON DEVICES */ + i2s_dai: I2S { + #sound-dai-cells = <0>; + compatible = "amlogic, aml-i2s-dai"; + clocks = + <&clkc CLKID_MPLL2>, + <&clkc CLKID_AMCLK_COMP>, + <&clkc CLKID_AIU_GLUE>, + <&clkc CLKID_IEC958>, + <&clkc CLKID_I2S_OUT>, + <&clkc CLKID_AMCLK>, + <&clkc CLKID_AIFIFO2>, + <&clkc CLKID_MIXER>, + <&clkc CLKID_MIXER_IFACE>, + <&clkc CLKID_ADC>, + <&clkc CLKID_AIU_TOP>, + <&clkc CLKID_AOCLK_GATE>, + <&clkc CLKID_I2S_SPDIF>; + clock-names = + "mpll", + "mclk", + "top_glue", + "aud_buf", + "i2s_out", + "amclk_measure", + "aififo2", + "aud_mixer", + "mixer_reg", + "adc", + "top_level", + "aoclk", + "aud_in"; + i2s_pos_sync = <0>; + /*DMIC;*/ /* I2s Mic or Dmic, default for I2S mic */ + }; + dmic:snd_dmic { + #sound-dai-cells = <0>; + compatible = "aml, aml_snd_dmic"; + reg = <0xd0042000 0x2000>; + status = "okay"; + resets = < + &clkc CLKID_PDM_GATE + >; + reset-names = "pdm"; + pinctrl-names = "audio_dmic"; + pinctrl-0 = <&aml_dmic_pins>; + clocks = <&clkc CLKID_PDM_COMP>, + <&clkc CLKID_AMCLK_COMP>; + clock-names = "pdm", "mclk"; + }; + spdif_dai: SPDIF { + #sound-dai-cells = <0>; + compatible = "amlogic, aml-spdif-dai"; + clocks = + <&clkc CLKID_MPLL1>, + <&clkc CLKID_I958_COMP>, + <&clkc CLKID_AMCLK_COMP>, + <&clkc CLKID_I958_COMP_SPDIF>, + <&clkc CLKID_CLK81>, + <&clkc CLKID_IEC958>, + <&clkc CLKID_IEC958_GATE>; + clock-names = + "mpll1", + "i958", + "mclk", + "spdif", + "clk_81", + "iec958", + "iec958_amclk"; + }; + pcm_dai: PCM { + #sound-dai-cells = <0>; + compatible = "amlogic, aml-pcm-dai"; + pinctrl-names = "audio_pcm"; + pinctrl-0 = <&audio_pcm_pins>; + clocks = + <&clkc CLKID_MPLL0>, + <&clkc CLKID_PCM_MCLK_COMP>, + <&clkc CLKID_PCM_SCLK_GATE>; + clock-names = + "mpll0", + "pcm_mclk", + "pcm_sclk"; + pcm_mode = <1>; /* 0=slave mode, 1=master mode */ + }; + i2s_plat: i2s_platform { + compatible = "amlogic, aml-i2s"; + interrupts = <0 29 1>; + }; + pcm_plat: pcm_platform { + compatible = "amlogic, aml-pcm"; + }; + spdif_codec: spdif_codec{ + #sound-dai-cells = <0>; + compatible = "amlogic, aml-spdif-codec"; + pinctrl-names = "audio_spdif"; + pinctrl-0 = <&audio_spdif_pins>; + }; + pcm_codec: pcm_codec{ + #sound-dai-cells = <0>; + compatible = "amlogic, pcm2BT-codec"; + }; + /* endof AUDIO MESON DEVICES */ + + /* AUDIO board specific */ + dummy_codec:dummy{ + #sound-dai-cells = <0>; + compatible = "amlogic, aml_dummy_codec"; + status = "disable"; + }; + amlogic_codec:t9015{ + #sound-dai-cells = <0>; + compatible = "amlogic, aml_codec_T9015"; + reg = <0xc8832000 0x14>; + status = "okay"; + }; + aml_sound_meson { + compatible = "aml, meson-snd-card"; + status = "okay"; + aml-sound-card,format = "i2s"; + aml_sound_card,name = "AML-MESONAUDIO"; + aml,audio-routing = + "Ext Spk","LOUTL", + "Ext Spk","LOUTR"; + + mute_gpio-gpios = <&gpio GPIOH_5 0>; + mute_inv; + hp_disable; + hp_paraments = <800 300 0 5 1>; + pinctrl-names = "audio_i2s"; + pinctrl-0 = <&audio_i2s_pins>; + cpu_list = <&cpudai0 &cpudai1 &cpudai2>; + codec_list = <&codec0 &codec1 &codec2>; + plat_list = <&i2s_plat &i2s_plat &pcm_plat>; + cpudai0: cpudai0 { + sound-dai = <&i2s_dai>; + }; + cpudai1: cpudai1 { + sound-dai = <&spdif_dai>; + }; + cpudai2: cpudai2 { + sound-dai = <&pcm_dai>; + }; + codec0: codec0 { + sound-dai = <&amlogic_codec>; + }; + codec1: codec1 { + sound-dai = <&spdif_codec>; + }; + codec2: codec2 { + sound-dai = <&pcm_codec>; + }; + }; + /* END OF AUDIO board specific */ + + rdma{ + compatible = "amlogic, meson, rdma"; + dev_name = "amlogic-rdma"; + status = "ok"; + interrupts = <0 89 1>; + interrupt-names = "rdma"; + }; + + picdec { + compatible = "amlogic, picdec"; + memory-region = <&picdec_cma_reserved>; + dev_name = "picdec"; + status = "okay"; + }; + + ppmgr { + compatible = "amlogic, ppmgr"; + memory-region = <&ppmgr_reserved>; + dev_name = "ppmgr"; + status = "okay"; + }; + + ionvideo { + compatible = "amlogic, ionvideo"; + dev_name = "ionvideo"; + status = "okay"; + }; + + amlvideo { + compatible = "amlogic, amlvideo"; + dev_name = "amlvideo"; + status = "okay"; + }; + + amlvideo2_0 { + compatible = "amlogic, amlvideo2"; + dev_name = "amlvideo2"; + status = "okay"; + amlvideo2_id = <0>; + cma_mode = <1>; + }; + + amlvideo2_1 { + compatible = "amlogic, amlvideo2"; + dev_name = "amlvideo2"; + status = "okay"; + amlvideo2_id = <1>; + cma_mode = <1>; + }; + + /*if you want to use vdin just modify status to "ok"*/ + vdin0 { + compatible = "amlogic, vdin"; + /*memory-region = <&vdin0_cma_reserved>;*/ + dev_name = "vdin0"; + status = "ok"; + reserve-iomap = "true"; + flag_cma = <1>;/*1:share with codec_mm;2:cma alone*/ + /*MByte, if 10bit disable: 64M(YUV422), + *if 10bit enable: 64*1.5 = 96M(YUV422) + *if support 4K2K-YUV444-10bit-WR:3840*2160*4*4 ~= 128M + *if support 4K2K-YUV422-10bit-wr:3840*2160*3*4 ~= 96M + *if support 4K2K-YUV422-8BIT-WR:3840*2160*2*4 ~= 64M + *if support 1080p-YUV422-8BIT-WR:1920*1080*2*4 ~= 16M + */ + cma_size = <16>; + interrupts = <0 83 1>; + rdma-irq = <2>; + /*clocks = <&clock CLK_FPLL_DIV5>, + * <&clock CLK_VDIN_MEAS_CLK>; + *clock-names = "fclk_div5", "cts_vdin_meas_clk"; + */ + vdin_id = <0>; + /*vdin write mem color depth support: + *bit0:support 8bit + *bit1:support 9bit + *bit2:support 10bit + *bit3:support 12bit + *bit4:support yuv422 10bit full pack mode (from txl new add) + */ + tv_bit_mode = <1>; + }; + vdin1 { + compatible = "amlogic, vdin"; + memory-region = <&vdin1_cma_reserved>; + dev_name = "vdin1"; + status = "ok"; + reserve-iomap = "true"; + flag_cma = <0>;/*1:share with codec_mm;0:cma alone*/ + interrupts = <0 85 1>; + rdma-irq = <4>; + /*clocks = <&clock CLK_FPLL_DIV5>, + * <&clock CLK_VDIN_MEAS_CLK>; + *clock-names = "fclk_div5", "cts_vdin_meas_clk"; + */ + vdin_id = <1>; + /*vdin write mem color depth support: + *bit0:support 8bit + *bit1:support 9bit + *bit2:support 10bit + *bit3:support 12bit + */ + tv_bit_mode = <1>; + }; + + amlvecm { + compatible = "amlogic, vecm"; + dev_name = "aml_vecm"; + status = "okay"; + gamma_en = <0>;/*1:enabel ;0:disable*/ + wb_en = <0>;/*1:enabel ;0:disable*/ + cm_en = <0>;/*1:enabel ;0:disable*/ + /*1:enabel osd lut 100 table;0:disable*/ + cfg_en_osd_100 = <1>; + /*0: 709/601 1: bt2020*/ + tx_op_color_primary = <0>; + }; + amdolby_vision { + compatible = "amlogic, dolby_vision_gxm"; + dev_name = "aml_amdolby_vision_driver"; + status = "okay"; + tv_mode = <0>;/*1:enabel ;0:disable*/ + }; + partitions: partitions{ + parts = <11>; + part-0 = <&logo>; + part-1 = <&recovery>; + part-2 = <&rsv>; + part-3 = <&tee>; + part-4 = <&crypt>; + part-5 = <&misc>; + part-6 = <&instaboot>; + part-7 = <&boot>; + part-8 = <&system>; + part-9 = <&cache>; + part-10 = <&data>; + + logo:logo{ + pname = "logo"; + size = <0x0 0x2000000>; + mask = <1>; + }; + recovery:recovery{ + pname = "recovery"; + size = <0x0 0x2000000>; + mask = <1>; + }; + rsv:rsv{ + pname = "rsv"; + size = <0x0 0x800000>; + mask = <1>; + }; + tee:tee{ + pname = "tee"; + size = <0x0 0x800000>; + mask = <1>; + }; + crypt:crypt{ + pname = "crypt"; + size = <0x0 0x2000000>; + mask = <1>; + }; + misc:misc{ + pname = "misc"; + size = <0x0 0x2000000>; + mask = <1>; + }; + instaboot:instaboot{ + pname = "instaboot"; + size = <0x0 0x400000>; + mask = <1>; + }; + boot:boot + { + pname = "boot"; + size = <0x0 0x2000000>; + mask = <1>; + }; + system:system + { + pname = "system"; + size = <0x0 0x80000000>; + mask = <1>; + }; + cache:cache + { + pname = "cache"; + size = <0x0 0x20000000>; + mask = <2>; + }; + data:data + { + pname = "data"; + size = <0xffffffff 0xffffffff>; + mask = <4>; + }; + }; + + deinterlace { + compatible = "amlogic, deinterlace"; + status = "okay"; + flag_cma = <1>;/*0:use reserved;1:use cma*/ + //memory-region = <&di_reserved>; + memory-region = <&di_cma_reserved>; + interrupts = <0 46 1 0 6 1>; + interrupt-names = "de_irq", "timerc"; + /* + * nr_size(byte) = 1920*544*2(yuv422 8bit) | + * 1920*544*2*12/8(yuv422 10bit) + * | 1920*544*2*10/8(yuv422 10bit full pack mode) + */ + /* mtn_size(byte) = 1920*544/2 */ + /* count_size(byte) = 1920*544/2 */ + buffer-size = <3133440>; + hw-version = <2>; + }; + +}; +&efuse { + status = "ok"; +}; diff --git a/arch/arm/boot/dts/amlogic/meson_drm.dtsi b/arch/arm/boot/dts/amlogic/meson_drm.dtsi new file mode 100644 index 000000000000..9f391ba1e3c5 --- /dev/null +++ b/arch/arm/boot/dts/amlogic/meson_drm.dtsi @@ -0,0 +1,104 @@ +/* + * arch/arm/boot/dts/amlogic/meson_drm.dtsi + * + * Copyright (C) 2015 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +/ { + drm_amhdmitx: drm-amhdmitx { + status = "disabled"; + hdcp = "disabled"; + compatible = "amlogic,drm-amhdmitx"; + dev_name = "meson-amhdmitx"; + interrupts = ; + ports { + port { + #address-cells = <1>; + #size-cells = <0>; + hdmi_in_vpu: endpoint@0 { + reg = <0>; + remote-endpoint = <&vpu_out_hdmi>; + }; + }; + }; + }; + + drm_lcd: drm-lcd { + status = "disabled"; + compatible = "amlogic,drm-lcd"; + dev_name = "meson-lcd"; + ports { + port { + #address-cells = <1>; + #size-cells = <0>; + lcd_in_vpu: endpoint@0 { + reg = <0>; + remote-endpoint = <&vpu_out_lcd>; + }; + }; + }; + }; + + drm_vpu: drm-vpu@0xff900000 { + status = "disabled"; + compatible = "amlogic,meson-gxbb-vpu"; + reg = <0xd0100000 0x100000>, + <0xc883c000 0x1000>, + <0xc8838000 0x1000>; + reg-names = "base", "hhi", "dmc"; + interrupts = ; + dma-coherent; + vpu_out: port { + #address-cells = <1>; + #size-cells = <0>; + + vpu_out_hdmi: endpoint@0 { + reg = <0>; + remote-endpoint = <&hdmi_in_vpu>; + }; + vpu_out_lcd: endpoint@1 { + reg = <1>; + remote-endpoint = <&lcd_in_vpu>; + }; + }; + }; + + drm_subsystem: drm-subsystem { + status = "okay"; + compatible = "amlogic,drm-subsystem"; + ports = <&vpu_out>; + }; +}; + +&gpu{ + /*gpu max freq is 750M*/ + def_clk = <1>; + tbl = <&clk285_cfg &clk666_cfg &clk750_cfg &clk750_cfg>; + + clk285_cfg:clk285_cfg { + keep_count = <2>; + threshold = <100 200>; + }; + + clk666_cfg:clk666_cfg { + keep_count = <1>; + threshold = <85 200>; + }; + + clk750_cfg:clk750_cfg { + keep_count = <1>; + threshold = <179 255>; + }; + +}; diff --git a/arch/arm/boot/dts/amlogic/mesonaxg.dtsi b/arch/arm/boot/dts/amlogic/mesonaxg.dtsi index 0292a1ebbf76..0c9b2c5e905e 100644 --- a/arch/arm/boot/dts/amlogic/mesonaxg.dtsi +++ b/arch/arm/boot/dts/amlogic/mesonaxg.dtsi @@ -50,7 +50,7 @@ }; CPU0:cpu@0 { device_type = "cpu"; - compatible = "arm,cortex-a9"; + compatible = "arm,cortex-a53","arm,armv8"; reg = <0x0 0x0>; enable-method = "psci"; clocks = <&scpi_dvfs 0>; @@ -60,7 +60,7 @@ CPU1:cpu@1 { device_type = "cpu"; - compatible = "arm,cortex-a9"; + compatible = "arm,cortex-a53","arm,armv8"; reg = <0x0 0x1>; enable-method = "psci"; clocks = <&scpi_dvfs 0>; @@ -69,7 +69,7 @@ }; CPU2:cpu@2 { device_type = "cpu"; - compatible = "arm,cortex-a9"; + compatible = "arm,cortex-a53","arm,armv8"; reg = <0x0 0x2>; enable-method = "psci"; clocks = <&scpi_dvfs 0>; @@ -79,7 +79,7 @@ CPU3:cpu@3 { device_type = "cpu"; - compatible = "arm,cortex-a9"; + compatible = "arm,cortex-a53","arm,armv8"; reg = <0x0 0x3>; enable-method = "psci"; clocks = <&scpi_dvfs 0>; diff --git a/arch/arm/boot/dts/amlogic/mesong12a.dtsi b/arch/arm/boot/dts/amlogic/mesong12a.dtsi index fb5c8f3e6ecc..baa41874bd6f 100644 --- a/arch/arm/boot/dts/amlogic/mesong12a.dtsi +++ b/arch/arm/boot/dts/amlogic/mesong12a.dtsi @@ -52,7 +52,7 @@ CPU0:cpu@0 { device_type = "cpu"; - compatible = "arm,cortex-a9"; + compatible = "arm,cortex-a53","arm,armv8"; reg = <0x0>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0>; @@ -70,7 +70,7 @@ CPU1:cpu@1 { device_type = "cpu"; - compatible = "arm,cortex-a9"; + compatible = "arm,cortex-a53","arm,armv8"; reg = <0x1>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0>; @@ -88,7 +88,7 @@ CPU2:cpu@2 { device_type = "cpu"; - compatible = "arm,cortex-a9"; + compatible = "arm,cortex-a53","arm,armv8"; reg = <0x2>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0>; @@ -106,7 +106,7 @@ CPU3:cpu@3 { device_type = "cpu"; - compatible = "arm,cortex-a9"; + compatible = "arm,cortex-a53","arm,armv8"; reg = <0x3>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0>; @@ -430,8 +430,14 @@ }; wdt: watchdog@0xffd0f0d0 { - compatible = "amlogic,meson-g12a-wdt"; + compatible = "amlogic, meson-wdt"; status = "okay"; + default_timeout=<10>; + reset_watchdog_method=<1>; /* 0:sysfs,1:kernel */ + reset_watchdog_time=<2>; + shutdown_timeout=<10>; + firmware_timeout=<6>; + suspend_timeout=<6>; reg = <0xffd0f0d0 0x10>; clock-names = "xtal"; clocks = <&xtal>; @@ -1361,6 +1367,7 @@ /*caps defined in dts*/ tx_delay = <0>; co_phase = <3>; + calc_f = <1>; max_req_size = <0x20000>; /**128KB*/ gpio_dat3 = <&gpio BOOT_3 GPIO_ACTIVE_HIGH>; hw_reset = <&gpio BOOT_9 GPIO_ACTIVE_HIGH>; @@ -1791,8 +1798,8 @@ defendkey: defendkey { compatible = "amlogic, defendkey"; reg = <0xff630218 0x4>; /*RNG_USR_DATA*/ - mem_size = <0x1000>; - status = "disabled"; + mem_size = <0 0x100000>; + status = "okay"; }; aml_dma { diff --git a/arch/arm/boot/dts/amlogic/mesong12a_drm.dtsi b/arch/arm/boot/dts/amlogic/mesong12a_drm.dtsi new file mode 100644 index 000000000000..b6597c677d88 --- /dev/null +++ b/arch/arm/boot/dts/amlogic/mesong12a_drm.dtsi @@ -0,0 +1,109 @@ +/* + * arch/arm/boot/dts/amlogic/meson_drm.dtsi + * + * Copyright (C) 2015 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +/ { + venc-cvbs { + status = "okay"; + compatible = "amlogic,meson-gxbb-cvbs"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + enc_cvbs_in: port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + //venc_cvbs_in_vpu: endpoint@0 { + // reg = <0>; + // remote-endpoint = <&vpu_out_venc_cvbs>; + //}; + }; + }; + }; + + drm_amhdmitx: drm-amhdmitx { + status = "disabled"; + hdcp = "disabled"; + compatible = "amlogic,drm-amhdmitx"; + dev_name = "meson-amhdmitx"; + interrupts = ; + ports { + port { + #address-cells = <1>; + #size-cells = <0>; + hdmi_in_vpu: endpoint@0 { + reg = <0>; + remote-endpoint = <&vpu_out_hdmi>; + }; + }; + }; + }; + + drm_lcd: drm-lcd { + status = "disabled"; + compatible = "amlogic,drm-lcd"; + dev_name = "meson-lcd"; + ports { + port { + #address-cells = <1>; + #size-cells = <0>; + lcd_in_vpu: endpoint@0 { + reg = <0>; + remote-endpoint = <&vpu_out_lcd>; + }; + }; + }; + }; + + drm_vpu: drm-vpu@0xff900000 { + status = "disabled"; + compatible = "amlogic,meson-g12a-vpu"; + memory-region = <&logo_reserved>; + reg = <0xff900000 0x40000>, + <0xff63c000 0x2000>, + <0xff638000 0x2000>; + reg-names = "base", "hhi", "dmc"; + interrupts = , + ; + interrupt-names = "viu-vsync", "viu2-vsync"; + clocks = <&clkc CLKID_VPU_CLKC_MUX>; + clock-names = "vpu_clkc"; + dma-coherent; + vpu_out: port { + #address-cells = <1>; + #size-cells = <0>; + + vpu_out_hdmi: endpoint@0 { + reg = <0>; + remote-endpoint = <&hdmi_in_vpu>; + }; + vpu_out_lcd: endpoint@1 { + reg = <1>; + remote-endpoint = <&lcd_in_vpu>; + }; + }; + }; + + drm_subsystem: drm-subsystem { + status = "okay"; + compatible = "amlogic,drm-subsystem"; + ports = <&vpu_out>; + }; +}; + diff --git a/arch/arm/boot/dts/amlogic/mesong12b.dtsi b/arch/arm/boot/dts/amlogic/mesong12b.dtsi new file mode 100644 index 000000000000..cfca75cbef31 --- /dev/null +++ b/arch/arm/boot/dts/amlogic/mesong12b.dtsi @@ -0,0 +1,2588 @@ +/* + * arch/arm/boot/dts/amlogic/mesong12a.dtsi + * + * Copyright (C) 2017 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "mesong12a-bifrost.dtsi" +#include "g12b-sched-energy.dtsi" + +/ { + cpus:cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu-map { + cluster0:cluster0 { + core0 { + cpu = <&CPU0>; + }; + core1 { + cpu = <&CPU1>; + }; + }; + cluster1:cluster1 { + core0 { + cpu = <&CPU2>; + }; + core1 { + cpu = <&CPU3>; + }; + core2 { + cpu = <&CPU4>; + }; + core3 { + cpu = <&CPU5>; + }; + }; + }; + + CPU0:cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0x0>; + enable-method = "psci"; + //cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>; + clocks = <&clkc CLKID_CPU_CLK>, + <&clkc CLKID_CPU_FCLK_P>, + <&clkc CLKID_SYS1_PLL>; + clock-names = "core_clk", + "low_freq_clk_parent", + "high_freq_clk_parent"; + operating-points-v2 = <&cpu_opp_table0>; + cpu-supply = <&vddcpu0>; + voltage-tolerance = <0>; + clock-latency = <50000>; + }; + + CPU1:cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0x1>; + enable-method = "psci"; + sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>; + clocks = <&clkc CLKID_CPU_CLK>, + <&clkc CLKID_CPU_FCLK_P>, + <&clkc CLKID_SYS1_PLL>; + clock-names = "core_clk", + "low_freq_clk_parent", + "high_freq_clk_parent"; + operating-points-v2 = <&cpu_opp_table0>; + cpu-supply = <&vddcpu0>; + voltage-tolerance = <0>; + clock-latency = <50000>; + }; + + CPU2:cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a73","arm,armv8"; + reg = <0x100>; + enable-method = "psci"; + //cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + sched-energy-costs = <&CPU_COST_A73 &CLUSTER_COST_A73>; + clocks = <&clkc CLKID_CPUB_CLK>, + <&clkc CLKID_CPUB_FCLK_P>, + <&clkc CLKID_SYS_PLL>; + clock-names = "core_clk", + "low_freq_clk_parent", + "high_freq_clk_parent"; + operating-points-v2 = <&cpu_opp_table1>; + cpu-supply = <&vddcpu1>; + voltage-tolerance = <0>; + clock-latency = <50000>; + }; + + CPU3:cpu@101 { + device_type = "cpu"; + compatible = "arm,cortex-a73","arm,armv8"; + reg = <0x101>; + enable-method = "psci"; + //cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + sched-energy-costs = <&CPU_COST_A73 &CLUSTER_COST_A73>; + clocks = <&clkc CLKID_CPUB_CLK>, + <&clkc CLKID_CPUB_FCLK_P>, + <&clkc CLKID_SYS_PLL>; + clock-names = "core_clk", + "low_freq_clk_parent", + "high_freq_clk_parent"; + operating-points-v2 = <&cpu_opp_table1>; + cpu-supply = <&vddcpu1>; + voltage-tolerance = <0>; + clock-latency = <50000>; + }; + + CPU4:cpu@102 { + device_type = "cpu"; + compatible = "arm,cortex-a73","arm,armv8"; + reg = <0x102>; + enable-method = "psci"; + //cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + sched-energy-costs = <&CPU_COST_A73 &CLUSTER_COST_A73>; + clocks = <&clkc CLKID_CPUB_CLK>, + <&clkc CLKID_CPUB_FCLK_P>, + <&clkc CLKID_SYS_PLL>; + clock-names = "core_clk", + "low_freq_clk_parent", + "high_freq_clk_parent"; + operating-points-v2 = <&cpu_opp_table1>; + cpu-supply = <&vddcpu1>; + voltage-tolerance = <0>; + clock-latency = <50000>; + }; + + CPU5:cpu@103 { + device_type = "cpu"; + compatible = "arm,cortex-a73","arm,armv8"; + reg = <0x103>; + enable-method = "psci"; + //cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + sched-energy-costs = <&CPU_COST_A73 &CLUSTER_COST_A73>; + clocks = <&clkc CLKID_CPUB_CLK>, + <&clkc CLKID_CPUB_FCLK_P>, + <&clkc CLKID_SYS_PLL>; + clock-names = "core_clk", + "low_freq_clk_parent", + "high_freq_clk_parent"; + operating-points-v2 = <&cpu_opp_table1>; + cpu-supply = <&vddcpu1>; + voltage-tolerance = <0>; + clock-latency = <50000>; + }; + + idle-states { + entry-method = "arm,psci"; + + CPU_SLEEP_0: cpu-sleep-0 { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x0010000>; + local-timer-stop; + entry-latency-us = <8000>; + exit-latency-us = <8000>; + min-residency-us = <20000>; + }; + + CLUSTER_SLEEP_0: cluster-sleep-0 { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x1010000>; + local-timer-stop; + entry-latency-us = <9000>; + exit-latency-us = <9000>; + min-residency-us = <25000>; + }; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + }; + + timer_bc { + compatible = "arm, meson-bc-timer"; + reg= <0xffd0f190 0x4 0xffd0f194 0x4>; + timer_name = "Meson TimerF"; + clockevent-rating=<300>; + clockevent-shift=<20>; + clockevent-features=<0x23>; + interrupts = <0 60 1>; + bit_enable=<16>; + bit_mode=<12>; + bit_resolution=<0>; + }; + arm_pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = <0 137 4>; + }; + + gic: interrupt-controller@2c001000 { + compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0xffc01000 0x1000>, + <0xffc02000 0x0100>; + interrupts = ; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + meson_suspend:pm { + compatible = "amlogic, pm"; + status = "okay"; + device_name = "aml_pm"; + reg = <0xff8000a8 0x4>, + <0xff80023c 0x4>; + }; + + secmon { + compatible = "amlogic, secmon"; + memory-region = <&secmon_reserved>; + in_base_func = <0x82000020>; + out_base_func = <0x82000021>; + reserve_mem_size = <0x00300000>; + clear_range = <0x05100000 0x200000>; + }; + + securitykey { + compatible = "aml, securitykey"; + storage_query = <0x82000060>; + storage_read = <0x82000061>; + storage_write = <0x82000062>; + storage_tell = <0x82000063>; + storage_verify = <0x82000064>; + storage_status = <0x82000065>; + storage_list = <0x82000067>; + storage_remove = <0x82000068>; + storage_in_func = <0x82000023>; + storage_out_func = <0x82000024>; + storage_block_func = <0x82000025>; + storage_size_func = <0x82000027>; + storage_set_enctype = <0x8200006A>; + storage_get_enctype = <0x8200006B>; + storage_version = <0x8200006C>; + }; + + mailbox: mhu@c883c400 { + compatible = "amlogic, meson_mhu"; + reg = <0xff63c400 0x4c>, /* MHU registers */ + <0xfffe7000 0x800>; /* Payload area */ + interrupts = <0 209 1>, /* low priority interrupt */ + <0 210 1>; /* high priority interrupt */ + #mbox-cells = <1>; + mbox-names = "cpu_to_scp_low", "cpu_to_scp_high"; + mboxes = <&mailbox 0 &mailbox 1>; + }; + + cpu_iomap { + compatible = "amlogic, iomap"; + #address-cells=<1>; + #size-cells=<1>; + ranges; + io_cbus_base { + reg = <0xffd00000 0x26000>; + }; + io_apb_base { + reg = <0xffe01000 0x7f000>; + }; + io_aobus_base { + reg = <0xff800000 0xb000>; + }; + io_vapb_base { + reg = <0xff900000 0x50000>; + }; + io_hiu_base { + reg = <0xff63c000 0x2000>; + }; + }; + + xtal: xtal-clk { + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "xtal"; + #clock-cells = <0>; + }; + + cpu_info { + compatible = "amlogic, cpuinfo"; + status = "okay"; + cpuinfo_cmd = <0x82000044>; + }; + + aml_reboot{ + compatible = "aml, reboot"; + sys_reset = <0x84000009>; + sys_poweroff = <0x84000008>; + }; + + vpu { + compatible = "amlogic, vpu-g12b"; + dev_name = "vpu"; + status = "okay"; + clocks = <&clkc CLKID_VAPB_MUX>, + <&clkc CLKID_VPU_INTR>, + <&clkc CLKID_VPU_P0_COMP>, + <&clkc CLKID_VPU_P1_COMP>, + <&clkc CLKID_VPU_MUX>; + clock-names = "vapb_clk", + "vpu_intr_gate", + "vpu_clk0", + "vpu_clk1", + "vpu_clk"; + clk_level = <7>; + /* 0: 100.0M 1: 166.7M 2: 200.0M 3: 250.0M */ + /* 4: 333.3M 5: 400.0M 6: 500.0M 7: 666.7M */ + }; + + ethmac: ethernet@ff3f0000 { + compatible = "amlogic, g12a-eth-dwmac","snps,dwmac"; + reg = <0xff3f0000 0x10000 + 0xff634540 0x8 + 0xff64c000 0xa0>; + reg-names = "eth_base", "eth_cfg", "eth_pll"; + interrupts = <0 8 1>; + interrupt-names = "macirq"; + status = "disabled"; + clocks = <&clkc CLKID_ETH_CORE>; + clock-names = "ethclk81"; + pll_val = <0x9c0040a 0x927e0000 0xac5f49e5>; + analog_val = <0x20200000 0x0000c000 0x00000023>; + }; + + pinctrl_aobus: pinctrl@ff800014{ + compatible = "amlogic,meson-g12a-aobus-pinctrl"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + gpio_ao: ao-bank@ff800014{ + reg = <0xff800014 0x8>, + <0xff800024 0x14>, + <0xff80001c 0x8>; + reg-names = "mux","gpio", "drive-strength"; + gpio-controller; + #gpio-cells = <2>; + }; + }; + + pinctrl_periphs: pinctrl@ff634480{ + compatible = "amlogic,meson-g12a-periphs-pinctrl"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + gpio: banks@ff6346c0{ + reg = <0xff6346c0 0x40>, + <0xff6344e8 0x18>, + <0xff634520 0x18>, + <0xff634440 0x4c>, + <0xff634740 0x1c>; + reg-names = "mux", + "pull", + "pull-enable", + "gpio", + "drive-strength"; + gpio-controller; + #gpio-cells = <2>; + }; + }; + + audio_data: audio_data { + compatible = "amlogic, audio_data"; + query_licence_cmd = <0x82000050>; + status = "disabled"; + }; + + dwc3: dwc3@ff500000 { + compatible = "synopsys, dwc3"; + status = "disabled"; + reg = <0xff500000 0x100000>; + interrupts = <0 30 4>; + usb-phy = <&usb2_phy_v2>, <&usb3_phy_v2>; + cpu-type = "gxl"; + clock-src = "usb3.0"; + clocks = <&clkc CLKID_USB_GENERAL>; + clock-names = "dwc_general"; + }; + + usb2_phy_v2: usb2phy@ffe09000 { + compatible = "amlogic, amlogic-new-usb2-v2"; + status = "disabled"; + reg = <0xffe09000 0x80 + 0xffd01008 0x100 + 0xff636000 0x2000 + 0xff63a000 0x2000>; + pll-setting-1 = <0x09400414>; + pll-setting-2 = <0x927E0000>; + pll-setting-3 = <0xac5f69e5>; + pll-setting-4 = <0xfe18>; + pll-setting-5 = <0x8000fff>; + pll-setting-6 = <0x78000>; + pll-setting-7 = <0xe0004>; + pll-setting-8 = <0xe000c>; + }; + + usb3_phy_v2: usb3phy@ffe09080 { + compatible = "amlogic, amlogic-new-usb3-v2"; + status = "disabled"; + reg = <0xffe09080 0x20>; + phy-reg = <0xff646000>; + phy-reg-size = <0x2000>; + usb2-phy-reg = <0xffe09000>; + usb2-phy-reg-size = <0x80>; + interrupts = <0 16 4>; + clocks = <&clkc CLKID_PCIE_PLL>; + clock-names = "pcie_refpll"; + }; + + dwc2_a: dwc2_a@ff400000 { + compatible = "amlogic, dwc2"; + status = "disabled"; + device_name = "dwc2_a"; + reg = <0xff400000 0x40000>; + interrupts = <0 31 4>; + pl-periph-id = <0>; /** lm name */ + clock-src = "usb0"; /** clock src */ + port-id = <0>; /** ref to mach/usb.h */ + port-type = <2>; /** 0: otg, 1: host, 2: slave */ + port-speed = <0>; /** 0: default, high, 1: full */ + port-config = <0>; /** 0: default */ + /*0:default,1:single,2:incr,3:incr4,4:incr8,5:incr16,6:disable*/ + port-dma = <0>; + port-id-mode = <0>; /** 0: hardware, 1: sw_host, 2: sw_slave*/ + usb-fifo = <728>; + cpu-type = "v2"; + phy-reg = <0xffe09000>; + phy-reg-size = <0xa0>; + /** phy-interface: 0x0: amlogic phy, 0x1: synopsys phy **/ + phy-interface = <0x0>; + clocks = <&clkc CLKID_USB_GENERAL + &clkc CLKID_USB1_TO_DDR>; + clock-names = "usb_general", + "usb1"; + }; + + wdt: watchdog@0xffd0f0d0 { + compatible = "amlogic, meson-wdt"; + status = "okay"; + default_timeout=<10>; + reset_watchdog_method=<1>; /* 0:sysfs,1:kernel */ + reset_watchdog_time=<2>; + shutdown_timeout=<10>; + firmware_timeout=<6>; + suspend_timeout=<6>; + reg = <0xffd0f0d0 0x10>; + clock-names = "xtal"; + clocks = <&xtal>; + }; + + saradc:saradc { + compatible = "amlogic,meson-g12a-saradc"; + status = "disabled"; + #io-channel-cells = <1>; + clocks = <&xtal>, <&clkc CLKID_SARADC_GATE>; + clock-names = "xtal", "saradc_clk"; + interrupts = ; + reg = <0xff809000 0x48>; + }; + + p_tsensor: p_tsensor@ff634594 { + compatible = "amlogic, r1p1-tsensor"; + device_name = "meson-pthermal"; + status = "okay"; + reg = <0xff634800 0x50>, + <0xff800268 0x4>; + cal_type = <0x1>; + cal_a = <324>; + cal_b = <424>; + cal_c = <3159>; + cal_d = <9411>; + rtemp = <115000>; + interrupts = <0 35 0>; + clocks = <&clkc CLKID_TS_COMP>; /* CLKID_TS_COMP>;*/ + clock-names = "ts_comp"; + #thermal-sensor-cells = <1>; + }; + + d_tsensor: d_tsensor@ff800228 { + compatible = "amlogic, r1p1-tsensor"; + device_name = "meson-dthermal"; + status = "okay"; + reg = <0xff634c00 0x50>, + <0xff800230 0x4>; + cal_type = <0x1>; + cal_a = <324>; + cal_b = <424>; + cal_c = <3159>; + cal_d = <9411>; + rtemp = <115000>; + interrupts = <0 36 0>; + clocks = <&clkc CLKID_TS_COMP>; /* CLKID_TS_COMP>;*/ + clock-names = "ts_comp"; + #thermal-sensor-cells = <1>; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + cbus: cbus@ffd00000 { + compatible = "simple-bus"; + reg = <0xffd00000 0x26000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xffd00000 0x26000>; + + gpio_intc: interrupt-controller@f080 { + compatible = "amlogic,meson-gpio-intc", + "amlogic,meson-g12a-gpio-intc"; + reg = <0xf080 0x10>; + interrupt-controller; + #interrupt-cells = <2>; + amlogic,channel-interrupts = + <64 65 66 67 68 69 70 71>; + status = "okay"; + }; + + meson_clk_msr { + compatible = "amlogic, gxl_measure"; + reg = <0x18004 0x4 + 0x1800c 0x4>; + }; + + pwm_ab: pwm@1b000 { + compatible = "amlogic,g12b-ee-pwm"; + reg = <0x1b000 0x20>; + #pwm-cells = <3>; + clocks = <&xtal>, + <&xtal>, + <&xtal>, + <&xtal>; + clock-names = "clkin0", + "clkin1", + "clkin2", + "clkin3"; + /* default xtal 24m clkin0-clkin2 and + * clkin1-clkin3 should be set the same + */ + status = "disabled"; + }; + + pwm_cd: pwm@1a000 { + compatible = "amlogic,g12b-ee-pwm"; + reg = <0x1a000 0x20>; + #pwm-cells = <3>; + clocks = <&xtal>, + <&xtal>, + <&xtal>, + <&xtal>; + clock-names = "clkin0", + "clkin1", + "clkin2", + "clkin3"; + status = "disabled"; + }; + + pwm_ef: pwm@19000 { + compatible = "amlogic,g12b-ee-pwm"; + reg = <0x19000 0x20>; + #pwm-cells = <3>; + clocks = <&xtal>, + <&xtal>, + <&xtal>, + <&xtal>; + clock-names = "clkin0", + "clkin1", + "clkin2", + "clkin3"; + status = "disabled"; + }; + + i2c0: i2c@1f000 { + compatible = "amlogic,meson-g12b-i2c"; + status = "disabled"; + reg = <0x1f000 0x20>; + interrupts = , + ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clkc CLKID_I2C>; + clock-names = "clk_i2c"; + }; + + i2c1: i2c@1e000 { + compatible = "amlogic,meson-g12b-i2c"; + status = "disabled"; + reg = <0x1e000 0x20>; + interrupts = , + ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clkc CLKID_I2C>; + clock-names = "clk_i2c"; + }; + + i2c2: i2c@1d000 { + compatible = "amlogic,meson-g12b-i2c"; + status = "disabled"; + reg = <0x1d000 0x20>; + interrupts = , + ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clkc CLKID_I2C>; + clock-names = "clk_i2c"; + }; + + i2c3: i2c@1c000 { + compatible = "amlogic,meson-g12b-i2c"; + status = "disabled"; + reg = <0x1c000 0x20>; + interrupts = , + ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clkc CLKID_I2C>; + clock-names = "clk_i2c"; + }; + + spicc0: spi@13000 { + compatible = "amlogic,meson-g12b-spicc", + "amlogic,meson-g12a-spicc"; + reg = <0x13000 0x44>; + interrupts = ; + clocks = <&clkc CLKID_SPICC0>, + <&clkc CLKID_SPICC0_COMP>; + clock-names = "core", "comp"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spicc1: spi@15000 { + compatible = "amlogic,meson-g12b-spicc", + "amlogic,meson-g12a-spicc"; + reg = <0x15000 0x44>; + interrupts = ; + clocks = <&clkc CLKID_SPICC1>, + <&clkc CLKID_SPICC1_COMP>; + clock-names = "core", "comp"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; /* end of cbus */ + + aobus: aobus@ff800000 { + compatible = "simple-bus"; + reg = <0xff800000 0xb000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xff800000 0xb000>; + + cpu_version { + reg=<0x220 0x4>; + }; + + aoclkc: clock-controller@0 { + compatible = "amlogic,g12b-aoclkc"; + #clock-cells = <1>; + reg = <0x0 0x320>; + }; + + pwm_AO_ab: pwm@7000 { + compatible = "amlogic,g12b-ao-pwm"; + reg = <0x7000 0x20>; + #pwm-cells = <3>; + clocks = <&xtal>, + <&xtal>, + <&xtal>, + <&xtal>; + clock-names = "clkin0", + "clkin1", + "clkin2", + "clkin3"; + status = "disabled"; + }; + + pwm_AO_cd: pwm@2000 { + compatible = "amlogic,g12b-ao-pwm"; + reg = <0x2000 0x20>; + #pwm-cells = <3>; + clocks = <&xtal>, + <&xtal>, + <&xtal>, + <&xtal>; + clock-names = "clkin0", + "clkin1", + "clkin2", + "clkin3"; + status = "disabled"; + }; + + i2c_AO: i2c@5000 { + compatible = "amlogic,meson-g12b-i2c"; + status = "disabled"; + reg = <0x05000 0x20>; + interrupts = , + ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clkc CLKID_I2C>; + clock-names = "clk_i2c"; + }; + + i2c_AO_slave:i2c_slave@6000 { + compatible = "amlogic, meson-i2c-slave"; + status = "disabled"; + reg = <0x6000 0x20>; + interrupts = <0 194 1>; + pinctrl-names="default"; + pinctrl-0=<&ao_i2c_slave_pins>; + }; + + uart_AO: serial@3000 { + compatible = "amlogic, meson-uart"; + reg = <0x3000 0x18>; + interrupts = <0 193 1>; + status = "okay"; + clocks = <&xtal>; + clock-names = "clk_uart"; + xtal_tick_en = <2>; + fifosize = < 64 >; + pinctrl-names = "default"; + /*pinctrl-0 = <&ao_uart_pins>;*/ + support-sysrq = <0>; /* 0 not support*/ + }; + + uart_AO_B: serial@4000 { + compatible = "amlogic, meson-uart"; + reg = <0x4000 0x18>; + interrupts = <0 197 1>; + status = "disabled"; + clocks = <&xtal>; + clock-names = "clk_uart"; + fifosize = < 64 >; + pinctrl-names = "default"; + pinctrl-0 = <&ao_b_uart_pins>; + }; + };/* end of aobus */ + + periphs: periphs@ff634400 { + compatible = "simple-bus"; + reg = <0xff634400 0x400>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xff634400 0x400>; + + };/* end of periphs */ + + hiubus: hiubus@ff63c000 { + compatible = "simple-bus"; + reg = <0xff63c000 0x2000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xff63c000 0x2000>; + + clkc: clock-controller@0 { + compatible = "amlogic,g12b-clkc-1"; + #clock-cells = <1>; + reg = <0x0 0x3dc>; + }; + clkc_b: clock-controller@1 { + compatible = "amlogic,g12b-clkc-2"; + #clock-cells = <1>; + reg = <0x0 0x3dc>; + }; + };/* end of hiubus*/ + + ion_dev { + compatible = "amlogic, ion_dev"; + memory-region = <&ion_cma_reserved>; + };/* end of ion_dev*/ + + audiobus: audiobus@0xff642000 { + compatible = "amlogic, audio-controller", "simple-bus"; + reg = <0xff642000 0x2000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xff642000 0x2000>; + clkaudio: audio_clocks { + compatible = "amlogic, g12a-audio-clocks"; + #clock-cells = <1>; + reg = <0x0 0xb0>; + }; + ddr_manager { + compatible = "amlogic, g12a-audio-ddr-manager"; + interrupts = < + GIC_SPI 148 IRQ_TYPE_EDGE_RISING + GIC_SPI 149 IRQ_TYPE_EDGE_RISING + GIC_SPI 150 IRQ_TYPE_EDGE_RISING + GIC_SPI 152 IRQ_TYPE_EDGE_RISING + GIC_SPI 153 IRQ_TYPE_EDGE_RISING + GIC_SPI 154 IRQ_TYPE_EDGE_RISING + >; + interrupt-names = + "toddr_a", "toddr_b", "toddr_c", + "frddr_a", "frddr_b", "frddr_c"; + }; + };/* end of audiobus*/ + + }; /* end of soc*/ + + remote:rc@0xff808040 { + compatible = "amlogic, aml_remote"; + dev_name = "meson-remote"; + reg = <0xff808040 0x44>, /*Multi-format IR controller*/ + <0xff808000 0x20>; /*Legacy IR controller*/ + status = "okay"; + protocol = ; + interrupts = <0 196 1>; + pinctrl-names = "default"; + pinctrl-0 = <&remote_pins>; + map = <&custom_maps>; + max_frame_time = <200>; /*set software decoder max frame time*/ + }; + + custom_maps:custom_maps { + mapnum = <3>; + map0 = <&map_0>; + map1 = <&map_1>; + map2 = <&map_2>; + map_0: map_0{ + mapname = "amlogic-remote-1"; + customcode = <0xfb04>; + release_delay = <80>; + size = <50>; /*keymap size*/ + keymap = ; + }; + map_1: map_1{ + mapname = "amlogic-remote-2"; + customcode = <0xfe01>; + release_delay = <80>; + size = <53>; + keymap = ; + }; + map_2: map_2{ + mapname = "amlogic-remote-3"; + customcode = <0xbd02>; + release_delay = <80>; + size = <17>; + keymap = ; + }; + }; + + uart_A: serial@ffd24000 { + compatible = "amlogic, meson-uart"; + reg = <0xffd24000 0x18>; + interrupts = <0 26 1>; + status = "disabled"; + clocks = <&xtal + &clkc CLKID_UART0>; + clock-names = "clk_uart", + "clk_gate"; + fifosize = < 128 >; + pinctrl-names = "default"; + pinctrl-0 = <&a_uart_pins>; + }; + + uart_B: serial@ffd23000 { + compatible = "amlogic, meson-uart"; + reg = <0xffd23000 0x18>; + interrupts = <0 75 1>; + status = "disabled"; + clocks = <&xtal + &clkc CLKID_UART1>; + clock-names = "clk_uart", + "clk_gate"; + fifosize = < 64 >; + pinctrl-names = "default"; + pinctrl-0 = <&b_uart_pins>; + }; + + uart_C: serial@ffd22000 { + compatible = "amlogic, meson-uart"; + reg = <0xffd22000 0x18>; + interrupts = <0 93 1>; + status = "disabled"; + clocks = <&xtal + &clkc CLKID_UART1>; + clock-names = "clk_uart", + "clk_gate"; + fifosize = < 64 >; + pinctrl-names = "default"; + pinctrl-0 = <&c_uart_pins>; + }; + + + pcie_A: pcieA@fc000000 { + compatible = "amlogic, amlogic-pcie-v2", "snps,dw-pcie"; + reg = <0xfc000000 0x400000 + 0xff648000 0x2000 + 0xfc400000 0x200000 + 0xff646000 0x2000 + 0xffd01080 0x10>; + reg-names = "elbi", "cfg", "config", "phy", "reset"; + interrupts = <0 221 0>; + #interrupt-cells = <1>; + bus-range = <0x0 0xff>; + #address-cells = <3>; + #size-cells = <2>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 223 IRQ_TYPE_EDGE_RISING>; + device_type = "pci"; + ranges = <0x81000000 0 0 0xfc600000 0x0 0x100000 + /* downstream I/O */ + 0x82000000 0 0xfc700000 0xfc700000 0 0x1900000>; + /* non-prefetchable memory */ + num-lanes = <1>; + pcie-num = <1>; + + clocks = <&clkc CLKID_PCIE_PLL + &clkc CLKID_PCIE_COMB + &clkc CLKID_PCIE_PHY>; + clock-names = "pcie_refpll", + "pcie", + "pcie_phy"; + /*reset-gpio-type 0:Shared pad(no reset)1:OD pad2:Normal pad*/ + gpio-type = <2>; + pcie-apb-rst-bit = <15>; + pcie-phy-rst-bit = <14>; + pcie-ctrl-a-rst-bit = <12>; + status = "disabled"; + }; + + amhdmitx: amhdmitx{ + compatible = "amlogic, amhdmitx"; + dev_name = "amhdmitx"; + status = "okay"; + vend-data = <&vend_data>; + pinctrl-names="default", "hdmitx_i2c"; + pinctrl-0=<&hdmitx_hpd &hdmitx_ddc>; + pinctrl-1=<&hdmitx_hpd_gpio &i2c3_master_pins1>; + clocks = <&clkc CLKID_VCLK2_ENCI + &clkc CLKID_VCLK2_VENCI0 + &clkc CLKID_VCLK2_VENCI1 + &clkc CLKID_VAPB_MUX + &clkc CLKID_VPU_MUX>; + clock-names = "venci_top_gate", + "venci_0_gate", + "venci_1_gate", + "hdmi_vapb_clk", + "hdmi_vpu_clk"; + /* HPD, 57 + 32 = 89; CEC, 151 + 32 = 183*/ + interrupts = <0 57 1>; + interrupt-names = "hdmitx_hpd"; + /* 0:M8B 1:GXBB 2:GXTVBB 3:GXL 4:GXM + * 5:TXL 6:TXLX 7:AXG 8:GXLX 9:TXHD + * 10:G12A 11:G12B + */ + ic_type = <11>; + vend_data: vend_data{ /* Should modified by Customer */ + vendor_name = "Amlogic"; /* Max Chars: 8 */ + /* standards.ieee.org/develop/regauth/oui/oui.txt */ + vendor_id = <0x000000>; + }; + }; + + galcore { + compatible = "amlogic, galcore"; + dev_name = "galcore"; + status = "disabled"; + clocks = <&clkc CLKID_VNANOQ_AXI_CLK_COMP>, + <&clkc CLKID_VNANOQ_CORE_CLK_COMP>; + clock-names = "cts_vipnanoq_axi_clk_composite", + "cts_vipnanoq_core_clk_composite"; + interrupts = <0 147 1>; + interrupt-names = "galcore"; + reg = <0xff100000 0x800 + 0xff000000 0x400000>; + }; + + aocec: aocec { + compatible = "amlogic, aocec-g12a"; + device_name = "aocec"; + status = "okay"; + vendor_name = "Amlogic"; /* Max Chars: 8 */ + /* Refer to the following URL at: + * http://standards.ieee.org/develop/regauth/oui/oui.txt + */ + vendor_id = <0x000000>; + product_desc = "G12B"; /* Max Chars: 16 */ + cec_osd_string = "AML_MBOX"; /* Max Chars: 14 */ + port_num = <1>; + ee_cec; + arc_port_mask = <0x2>; + interrupts = <0 203 1 + 0 199 1>; /*0:snps 1:ts*/ + interrupt-names = "hdmi_aocecb","hdmi_aocec"; + pinctrl-names = "default","hdmitx_aocecb","cec_pin_sleep"; + pinctrl-0=<&eecec_a>; + pinctrl-1=<&eecec_b>; + pinctrl-2=<&eecec_b>; + reg = <0xFF80023c 0x4 + 0xFF800000 0x400 + 0xFF634400 0x26>; + reg-names = "ao_exit","ao","periphs"; + }; + + /*if you want to use vdin just modify status to "ok"*/ + vdin0: vdin0 { + compatible = "amlogic, vdin"; + dev_name = "vdin0"; + status = "disabled"; + reserve-iomap = "true"; + flag_cma = <0>;/*1:share with codec_mm;2:cma alone*/ + /*MByte, if 10bit disable: 64M(YUV422), + *if 10bit enable: 64*1.5 = 96M(YUV422) + *if support 4K2K-YUV444-10bit-WR:3840*2160*4*4 ~= 128M + *if support 4K2K-YUV422-10bit-wr:3840*2160*3*4 ~= 96M + *if support 4K2K-YUV422-8BIT-WR:3840*2160*2*4 ~= 64M + *if support 1080p-YUV422-8BIT-WR:1920*1080*2*4 ~= 16M + */ + /*cma_size = <16>;*/ + interrupts = <0 83 1>; + rdma-irq = <2>; + /*clocks = <&clock CLK_FPLL_DIV5>, + * <&clock CLK_VDIN_MEAS_CLK>; + *clock-names = "fclk_div5", "cts_vdin_meas_clk"; + */ + vdin_id = <0>; + }; + vdin1: vdin1 { + compatible = "amlogic, vdin"; + dev_name = "vdin1"; + status = "disabled"; + reserve-iomap = "true"; + flag_cma = <0>;/*1:share with codec_mm;0:cma alone*/ + interrupts = <0 85 1>; + rdma-irq = <4>; + /*clocks = <&clock CLK_FPLL_DIV5>, + * <&clock CLK_VDIN_MEAS_CLK>; + *clock-names = "fclk_div5", "cts_vdin_meas_clk"; + */ + vdin_id = <1>; + }; + + vout { + compatible = "amlogic, vout"; + dev_name = "vout"; + status = "okay"; + }; + + vout2 { + compatible = "amlogic, vout2"; + dev_name = "vout"; + status = "okay"; + clocks = <&clkc CLKID_VPU_CLKC_P0_COMP>, + <&clkc CLKID_VPU_CLKC_MUX>; + clock-names = "vpu_clkc0", + "vpu_clkc"; + }; + + vdac { + compatible = "amlogic, vdac-g12b"; + status = "okay"; + }; + + canvas: canvas{ + compatible = "amlogic, meson, canvas"; + dev_name = "amlogic-canvas"; + status = "okay"; + reg = <0xff638000 0x2000>; + }; + + ge2d { + compatible = "amlogic, ge2d-g12a"; + dev_name = "ge2d"; + status = "okay"; + interrupts = <0 146 1>; + interrupt-names = "ge2d"; + clocks = <&clkc CLKID_VAPB_MUX>, + <&clkc CLKID_G2D>, + <&clkc CLKID_GE2D_GATE>; + clock-names = "clk_vapb_0", + "clk_ge2d", + "clk_ge2d_gate"; + reg = <0xff940000 0x10000>; + }; + + meson-amvideom { + compatible = "amlogic, amvideom"; + dev_name = "amvideom"; + status = "okay"; + interrupts = <0 3 1>; + interrupt-names = "vsync"; + }; + + codec_io: codec_io { + compatible = "amlogic, codec_io"; + status = "okay"; + #address-cells=<1>; + #size-cells=<1>; + ranges; + io_cbus_base{ + reg = <0xffd00000 0x100000>; + }; + io_dos_base{ + reg = <0xff620000 0x10000>; + }; + io_hiubus_base{ + reg = <0xff63c000 0x2000>; + }; + io_aobus_base{ + reg = <0xff800000 0x10000>; + }; + io_vcbus_base{ + reg = <0xff900000 0x40000>; + }; + io_dmc_base{ + reg = <0xff638000 0x2000>; + }; + io_efuse_base{ + reg = <0xff630000 0x2000>; + }; + }; + + gdc:gdc { + #address-cells=<1>; + #size-cells=<1>; + status = "ok"; + compatible = "amlogic, g12b-gdc"; + reg = <0xFF950000 0x0000100 + 0xFF63C16C 0x0000004 + 0xFF63C100 0x0000004>; + interrupts = <0 144 1>; + interrupt-names = "GDC"; + clocks = <&clkc CLKID_GDC_CORE_CLK_COMP + &clkc CLKID_GDC_AXI_CLK_COMP >; + clock-names = "core","axi"; + }; + + mesonstream { + compatible = "amlogic, codec, streambuf"; + dev_name = "mesonstream"; + status = "okay"; + clocks = <&clkc CLKID_DOS_PARSER + &clkc CLKID_DEMUX + &clkc CLKID_AHB_ARB0 + &clkc CLKID_DOS + &clkc CLKID_VDEC_MUX + &clkc CLKID_HCODEC_MUX + &clkc CLKID_HEVC_MUX + &clkc CLKID_HEVCF_MUX>; + clock-names = "parser_top", + "demux", + "ahbarb0", + "vdec", + "clk_vdec_mux", + "clk_hcodec_mux", + "clk_hevc_mux", + "clk_hevcb_mux"; + }; + + vdec { + compatible = "amlogic, vdec"; + dev_name = "vdec.0"; + status = "okay"; + interrupts = <0 3 1 + 0 23 1 + 0 32 1 + 0 43 1 + 0 44 1 + 0 45 1>; + interrupt-names = "vsync", + "demux", + "parser", + "mailbox_0", + "mailbox_1", + "mailbox_2"; + }; + + amvenc_avc{ + compatible = "amlogic, amvenc_avc"; + dev_name = "amvenc_avc"; + status = "okay"; + interrupts = <0 45 1>; + interrupt-names = "mailbox_2"; + }; + + hevc_enc{ + compatible = "cnm, HevcEnc"; + //memory-region = <&hevc_enc_reserved>; + dev_name = "HevcEnc"; + status = "okay"; + interrupts = <0 187 1>; + interrupt-names = "wave420l_irq"; + #address-cells=<1>; + #size-cells=<1>; + ranges; + io_reg_base{ + reg = <0xff610000 0x4000>; + }; + }; + + rdma{ + compatible = "amlogic, meson, rdma"; + dev_name = "amlogic-rdma"; + status = "okay"; + interrupts = <0 89 1>; + interrupt-names = "rdma"; + }; + + meson_fb: meson-fb { + compatible = "amlogic, meson-g12b"; + memory-region = <&logo_reserved>; + dev_name = "meson-fb"; + status = "disable"; + interrupts = <0 3 1 + 0 56 1 + 0 89 1>; + interrupt-names = "viu-vsync", "viu2-vsync", "rdma"; + /* uboot logo,fb0/fb1 memory size,if afbcd fb0=0x01851000*/ + display_mode_default = "1080p60hz"; + scale_mode = <1>; + /** 0:VPU free scale 1:OSD free scale 2:OSD super scale */ + display_size_default = <1920 1080 1920 2160 32>; + /*1920*1080*4*3 = 0x17BB000*/ + clocks = <&clkc CLKID_VPU_CLKC_MUX>; + clock-names = "vpu_clkc"; + }; + irblaster: meson-irblaster { + compatible = "amlogic, meson_irblaster"; + reg = <0xff80014c 0x10>, + <0xff800040 0x4>; + pinctrl-names = "default"; + pinctrl-0 = <&irblaster_pins>; + interrupts = <0 198 1>; + status = "disabled"; + }; + + sd_emmc_c: emmc@ffe07000 { + status = "disabled"; + compatible = "amlogic, meson-mmc-g12b"; + reg = <0xffe07000 0x800>; + interrupts = <0 191 1>; + pinctrl-names = "emmc_clk_cmd_pins", "emmc_all_pins"; + pinctrl-0 = <&emmc_clk_cmd_pins>; + pinctrl-1 = <&emmc_conf_pull_up &emmc_conf_pull_done>; + clocks = <&clkc CLKID_SD_EMMC_C>, + <&clkc CLKID_SD_EMMC_C_P0_COMP>, + <&clkc CLKID_FCLK_DIV2>, + <&clkc CLKID_FCLK_DIV5>, + <&xtal>; + clock-names = "core", "clkin0", "clkin1", "clkin2", "xtal"; + + bus-width = <8>; + cap-sd-highspeed; + cap-mmc-highspeed; + /* mmc-ddr-1_8v; */ + /* mmc-hs200-1_8v; */ + + max-frequency = <200000000>; + non-removable; + disable-wp; + emmc { + pinname = "emmc"; + ocr_avail = <0x200080>; /**VDD voltage 3.3 ~ 3.4 */ + /*caps defined in dts*/ + tx_delay = <0>; + max_req_size = <0x20000>; /**128KB*/ + gpio_dat3 = <&gpio BOOT_3 GPIO_ACTIVE_HIGH>; + hw_reset = <&gpio BOOT_9 GPIO_ACTIVE_HIGH>; + card_type = <1>; + /* 1:mmc card(include eMMC), + * 2:sd card(include tSD) + */ + }; + }; + + sd_emmc_b:sd@ffe05000 { + status = "disabled"; + compatible = "amlogic, meson-mmc-g12b"; + reg = <0xffe05000 0x800>; + interrupts = <0 190 1>; + + pinctrl-names = "sd_all_pins", + "sd_clk_cmd_pins", + "sd_1bit_pins", + "sd_clk_cmd_uart_pins", + "sd_1bit_uart_pins", + "sd_to_ao_uart_pins", + "ao_to_sd_uart_pins", + "sd_to_ao_jtag_pins", + "ao_to_sd_jtag_pins"; + pinctrl-0 = <&sd_all_pins>; + pinctrl-1 = <&sd_clk_cmd_pins>; + pinctrl-2 = <&sd_1bit_pins>; + pinctrl-3 = <&sd_to_ao_uart_clr_pins + &sd_clk_cmd_pins &ao_to_sd_uart_pins>; + pinctrl-4 = <&sd_to_ao_uart_clr_pins + &sd_1bit_pins &ao_to_sd_uart_pins>; + pinctrl-5 = <&sd_all_pins &sd_to_ao_uart_pins>; + pinctrl-6 = <&sd_to_ao_uart_clr_pins &ao_to_sd_uart_pins>; + pinctrl-7 = <&sd_all_pins &sd_to_ao_uart_pins>; + pinctrl-8 = <&sd_to_ao_uart_clr_pins &ao_to_sd_uart_pins>; + + clocks = <&clkc CLKID_SD_EMMC_B>, + <&clkc CLKID_SD_EMMC_B_P0_COMP>, + <&clkc CLKID_FCLK_DIV2>, + <&clkc CLKID_FCLK_DIV5>, + <&xtal>; + clock-names = "core", "clkin0", "clkin1", "clkin2", "xtal"; + + bus-width = <4>; + cap-sd-highspeed; + cap-mmc-highspeed; + max-frequency = <100000000>; + disable-wp; + sd { + pinname = "sd"; + ocr_avail = <0x200080>; /**VDD voltage 3.3 ~ 3.4 */ + max_req_size = <0x20000>; /**128KB*/ + gpio_dat3 = <&gpio GPIOC_3 GPIO_ACTIVE_HIGH>; + jtag_pin = <&gpio GPIOC_0 GPIO_ACTIVE_HIGH>; + gpio_cd = <&gpio GPIOC_6 GPIO_ACTIVE_HIGH>; + card_type = <5>; + /* 3:sdio device(ie:sdio-wifi), + * 4:SD combo (IO+mem) card + */ + }; + }; + + sd_emmc_a:sdio@ffe03000 { + status = "disabled"; + compatible = "amlogic, meson-mmc-g12b"; + reg = <0xffe03000 0x800>; + interrupts = <0 189 4>; + + pinctrl-names = "sdio_all_pins", + "sdio_clk_cmd_pins"; + pinctrl-0 = <&sdio_all_pins>; + pinctrl-1 = <&sdio_clk_cmd_pins>; + + clocks = <&clkc CLKID_SD_EMMC_A>, + <&clkc CLKID_SD_EMMC_A_P0_COMP>, + <&clkc CLKID_FCLK_DIV2>, + <&clkc CLKID_FCLK_DIV5>, + <&xtal>; + clock-names = "core", "clkin0", "clkin1", "clkin2", "xtal"; + + bus-width = <4>; + cap-sd-highspeed; + cap-mmc-highspeed; + max-frequency = <100000000>; + disable-wp; + sdio { + pinname = "sdio"; + ocr_avail = <0x200080>; /**VDD voltage 3.3 ~ 3.4 */ + max_req_size = <0x20000>; /**128KB*/ + card_type = <3>; + /* 3:sdio device(ie:sdio-wifi), + * 4:SD combo (IO+mem) card + */ + }; + }; + + nand: nfc@0 { + compatible = "amlogic, aml_mtd_nand"; + dev_name = "mtdnand"; + status = "disabled"; + reg = <0xFFE07800 0x200>; + interrupts = <0 34 1>; + + pinctrl-names = "nand_rb_mod","nand_norb_mod", "nand_cs_only"; + pinctrl-0 = <&all_nand_pins>; + pinctrl-1 = <&all_nand_pins>; + pinctrl-2 = <&nand_cs_pins>; + clocks = <&clkc CLKID_SD_EMMC_C>, + <&clkc CLKID_SD_EMMC_C_P0_COMP>; + clock-names = "core", "clkin"; + + device_id = <0>; + /*fip/tpl configurations, must be same + * with uboot if bl_mode was set as 1 + * bl_mode: 0 compact mode; 1 descrete mode + * if bl_mode was set as 1, fip configuration will work + */ + bl_mode = <1>; + /*copy count of fip*/ + fip_copies = <4>; + /*size of each fip copy */ + fip_size = <0x200000>; + nand_clk_ctrl = <0xFFE07000>; + /*partions defined in dts */ + }; + + meson_cooldev: meson-cooldev@0 { + status = "okay"; + compatible = "amlogic, meson-cooldev"; + device_name = "mcooldev"; + cooling_devices { + cpufreq_cool_cluster0 { + min_state = <1000000>; + dyn_coeff = <120>; + cluster_id = <0>; + gpu_pp = <2>; + node_name = "cpufreq_cool0"; + device_type = "cpufreq"; + }; + cpufreq_cool_cluster1 { + min_state = <1000000>; + dyn_coeff = <460>; + cluster_id = <1>; + gpu_pp = <2>; + node_name = "cpufreq_cool1"; + device_type = "cpufreq"; + }; + cpucore_cool_cluster0 { + min_state = <1>; + dyn_coeff = <0>; + cluster_id = <0>; + gpu_pp = <2>; + node_name = "cpucore_cool0"; + device_type = "cpucore"; + }; + cpucore_cool_cluster1 { + min_state = <0>; + dyn_coeff = <0>; + cluster_id = <1>; + gpu_pp = <2>; + node_name = "cpucore_cool1"; + device_type = "cpucore"; + }; + gpufreq_cool { + min_state = <400>; + dyn_coeff = <358>; + cluster_id = <0>; + gpu_pp = <2>; + node_name = "gpufreq_cool0"; + device_type = "gpufreq"; + }; + gpucore_cool { + min_state = <1>; + dyn_coeff = <0>; + cluster_id = <0>; + gpu_pp = <2>; + node_name = "gpucore_cool0"; + device_type = "gpucore"; + }; + }; + cpufreq_cool0:cpufreq_cool0 { + #cooling-cells = <2>; /* min followed by max */ + }; + cpufreq_cool1:cpufreq_cool1 { + #cooling-cells = <2>; /* min followed by max */ + }; + cpucore_cool0:cpucore_cool0 { + #cooling-cells = <2>; /* min followed by max */ + }; + cpucore_cool1:cpucore_cool1 { + #cooling-cells = <2>; /* min followed by max */ + }; + gpufreq_cool0:gpufreq_cool0 { + #cooling-cells = <2>; /* min followed by max */ + }; + gpucore_cool0:gpucore_cool0 { + #cooling-cells = <2>; /* min followed by max */ + }; + }; + /*meson cooling devices end*/ + + thermal-zones { + soc_thermal: soc_thermal { + polling-delay = <1000>; + polling-delay-passive = <100>; + sustainable-power = <3550>; + thermal-sensors = <&p_tsensor 0>; + trips { + pswitch_on: trip-point@0 { + temperature = <60000>; + hysteresis = <5000>; + type = "passive"; + }; + pcontrol: trip-point@1 { + temperature = <75000>; + hysteresis = <5000>; + type = "passive"; + }; + phot: trip-point@2 { + temperature = <85000>; + hysteresis = <5000>; + type = "hot"; + }; + pcritical: trip-point@3 { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + + cooling-maps { + cpufreq_cooling_map0 { + trip = <&pcontrol>; + cooling-device = <&cpufreq_cool0 0 10>; + contribution = <1024>; + }; + cpufreq_cooling_map1 { + trip = <&pcontrol>; + cooling-device = <&cpufreq_cool1 0 9>; + contribution = <1024>; + }; + cpucore_cooling_map0 { + trip = <&pcontrol>; + cooling-device = <&cpucore_cool0 0 1>; + contribution = <1024>; + }; + cpucore_cooling_map1 { + trip = <&pcontrol>; + cooling-device = <&cpucore_cool1 0 4>; + contribution = <1024>; + }; + gpufreq_cooling_map { + trip = <&pcontrol>; + cooling-device = <&gpufreq_cool0 0 4>; + contribution = <1024>; + }; + gpucore_cooling_map { + trip = <&pcontrol>; + cooling-device = <&gpucore_cool0 0 2>; + contribution = <1024>; + }; + }; + }; + ddr_thermal: ddr_thermal { + polling-delay = <1000>; + polling-delay-passive = <100>; + sustainable-power = <3550>; + thermal-sensors = <&d_tsensor 1>; + trips { + dswitch_on: trip-point@0 { + temperature = <60000>; + hysteresis = <5000>; + type = "passive"; + }; + dcontrol: trip-point@1 { + temperature = <75000>; + hysteresis = <5000>; + type = "passive"; + }; + dhot: trip-point@2 { + temperature = <85000>; + hysteresis = <5000>; + type = "hot"; + }; + dcritical: trip-point@3 { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + + }; + }; + /*thermal zone end*/ + + /* Sound iomap */ + aml_snd_iomap { + compatible = "amlogic, snd-iomap"; + status = "okay"; + #address-cells=<1>; + #size-cells=<1>; + ranges; + pdm_bus { + reg = <0xFF640000 0x2000>; + }; + audiobus_base { + reg = <0xFF642000 0x2000>; + }; + audiolocker_base { + reg = <0xFF64A000 0x2000>; + }; + eqdrc_base { + reg = <0xFF656000 0x1800>; + }; + reset_base { + reg = <0xFFD01000 0x1000>; + }; + }; + + vddcpu0: pwmao_d-regulator { + compatible = "pwm-regulator"; + pinctrl-names = "default"; + pinctrl-0 = <&pwm_ao_d_pins3>; + pwms = <&pwm_AO_cd MESON_PWM_1 1250 0>; + regulator-name = "vddcpu0"; + regulator-min-microvolt = <721000>; + regulator-max-microvolt = <1022000>; + regulator-always-on; + max-duty-cycle = <1250>; + /* Voltage Duty-Cycle */ + voltage-table = <1022000 0>, + <1011000 3>, + <1001000 6>, + <991000 10>, + <981000 13>, + <971000 16>, + <961000 20>, + <951000 23>, + <941000 26>, + <931000 30>, + <921000 33>, + <911000 36>, + <901000 40>, + <891000 43>, + <881000 46>, + <871000 50>, + <861000 53>, + <851000 56>, + <841000 60>, + <831000 63>, + <821000 67>, + <811000 70>, + <801000 73>, + <791000 76>, + <781000 80>, + <771000 83>, + <761000 86>, + <751000 90>, + <741000 93>, + <731000 96>, + <721000 100>; + status = "okay"; + }; + + vddcpu1: pwmab_a-regulator { + compatible = "pwm-regulator"; + pinctrl-names = "default"; + pinctrl-0 = <&pwm_a_e2>; + pwms = <&pwm_ab MESON_PWM_0 1250 0>; + regulator-name = "vddcpu1"; + regulator-min-microvolt = <721000>; + regulator-max-microvolt = <1022000>; + regulator-always-on; + max-duty-cycle = <1250>; + /* Voltage Duty-Cycle */ + voltage-table = <1022000 0>, + <1011000 3>, + <1001000 6>, + <991000 10>, + <981000 13>, + <971000 16>, + <961000 20>, + <951000 23>, + <941000 26>, + <931000 30>, + <921000 33>, + <911000 36>, + <901000 40>, + <891000 43>, + <881000 46>, + <871000 50>, + <861000 53>, + <851000 56>, + <841000 60>, + <831000 63>, + <821000 67>, + <811000 70>, + <801000 73>, + <791000 76>, + <781000 80>, + <771000 83>, + <761000 86>, + <751000 90>, + <741000 93>, + <731000 96>, + <721000 100>; + status = "okay"; + }; + + ddr_bandwidth { + compatible = "amlogic, ddr-bandwidth"; + status = "okay"; + reg = <0xff638000 0x100 + 0xff638c00 0x100>; + interrupts = <0 52 1>; + interrupt-names = "ddr_bandwidth"; + }; + dmc_monitor { + compatible = "amlogic, dmc_monitor"; + status = "okay"; + reg_base = <0xff639000>; + interrupts = <0 51 1>; + }; + + isp_sc: isp-sc@ff655400 { + compatible = "amlogic, isp-sc"; + reg = <0xff655400 0x00001000>; + reg-names = "isp_sc"; + interrupts = <0 17 0>; + interrupt-names = "isp_sc"; + }; + + isp: isp@ff140000 { + compatible = "arm, isp"; + reg = <0xff140000 0x00040000>; + reg-names = "ISP"; + interrupts = <0 142 4>; + interrupt-names = "ISP"; + clocks = <&clkc CLKID_MIPI_ISP_CLK_COMP>, + <&clkc CLKID_MIPI_CSI_PHY_CLK0_COMP>; + clock-names = "cts_mipi_isp_clk_composite", + "cts_mipi_csi_phy_clk0_composite"; + link-device = <&isp_sc>; + }; + + adapter: isp-adapter@ff650000 { + compatible = "amlogic, isp-adapter"; + reg = <0xff650000 0x00006000>; + reg-names = "adapter"; + interrupts = <0 179 0>; + interrupt-names = "adapter-irq"; + }; + + phycsi: phy-csi@ff650000 { + compatible = "amlogic, phy-csi"; + reg = <0xff650000 0x00002000>, + <0xff652000 0x00002000>, + <0xff63c300 0x00000100>, + <0xff654000 0x00000100>, + <0xff654400 0x00000100>; + reg-names = "csi2_phy0", "csi2_phy1", "aphy_reg", + "csi0_host", "csi1_host"; + interrupts = <0 41 0>, + <0 42 0>, + <0 72 0>, + <0 74 0>, + <0 87 0>, + <0 88 0>; + interrupt-names = "phy0-irq", + "phy1-irq", + "csi-host0-intr2", + "csi-host0-intr1", + "csi-host1-intr2", + "csi-host1-intr1"; + link-device = <&adapter>; + }; + + defendkey: defendkey { + compatible = "amlogic, defendkey"; + reg = <0xff630218 0x4>; /*RNG_USR_DATA*/ + mem_size = <0 0x100000>; + status = "okay"; + }; +};/* end of / */ + +&pinctrl_aobus { + ao_uart_pins:ao_uart { + mux { + groups = "uart_ao_tx_a", + "uart_ao_rx_a"; + function = "uart_ao_a"; + }; + }; + + ao_b_uart_pins:ao_b_uart { + mux { + groups = "uart_ao_tx_b_2", + "uart_ao_rx_b_3"; + function = "uart_ao_b"; + }; + }; + + ao_i2c_master_pins1:ao_i2c_pins1 { + mux { + groups = "i2c_ao_sck", + "i2c_ao_sda"; + function = "i2c_ao"; + bias-pull-up; + drive-strength = <2>; + }; + }; + + ao_i2c_master_pins2:ao_i2c_pins2 { + mux { + groups = "i2c_ao_sck_e", + "i2c_ao_sda_e"; + function = "i2c_ao"; + bias-pull-up; + drive-strength = <2>; + }; + }; + + ao_i2c_slave_pins:ao_i2c_slave_pins { + mux { + groups = "i2c_ao_slave_sck", + "i2c_ao_slave_sda"; + function = "i2c_ao_slave"; + }; + }; + + pwm_ao_a_pins: pwm_ao_a { + mux { + groups = "pwm_ao_a"; + function = "pwm_ao_a"; + }; + }; + + pwm_ao_a_hiz_pins: pwm_ao_a_hiz { + mux { + groups = "pwm_ao_a_hiz"; + function = "pwm_ao_a"; + }; + }; + + pwm_ao_b_pins: pwm_ao_b { + mux { + groups = "pwm_ao_b"; + function = "pwm_ao_b"; + }; + }; + + pwm_ao_c_pins1: pwm_ao_c_pins1 { + mux { + groups = "pwm_ao_c_4"; + function = "pwm_ao_c"; + }; + }; + + pwm_ao_c_pins2: pwm_ao_c_pins2 { + mux { + groups = "pwm_ao_c_6"; + function = "pwm_ao_c"; + }; + }; + + pwm_ao_c_hiz_pins: pwm_ao_c_hiz { + mux { + groups = "pwm_ao_c_hiz_4"; + function = "pwm_ao_c"; + }; + }; + + pwm_ao_d_pins1: pwm_ao_d_pins1 { + mux { + groups = "pwm_ao_d_5"; + function = "pwm_ao_d"; + }; + }; + + pwm_ao_d_pins2: pwm_ao_d_pins2 { + mux { + groups = "pwm_ao_d_10"; + function = "pwm_ao_d"; + }; + }; + + pwm_ao_d_pins3: pwm_ao_d_pins3 { + mux { + groups = "pwm_ao_d_e"; + function = "pwm_ao_d"; + }; + }; + + aocec_a: ao_ceca { + mux { + groups = "cec_ao_a"; + function = "cec_ao"; + }; + }; + + aocec_b: ao_cecb { + mux { + groups = "cec_ao_b"; + function = "cec_ao"; + }; + }; + pwm_a_e2: pwm_a_e2 { + mux { + groups = "pwm_a_e2"; + function = "pwm_a_gpioe"; + }; + }; +}; + +&pinctrl_periphs { + /* sdemmc portC */ + emmc_clk_cmd_pins:emmc_clk_cmd_pins { + mux { + groups = "emmc_clk", + "emmc_cmd"; + function = "emmc"; + input-enable; + bias-pull-up; + drive-strength = <3>; + }; + }; + + emmc_conf_pull_up:emmc_conf_pull_up { + mux { + groups = "emmc_nand_d7", + "emmc_nand_d6", + "emmc_nand_d5", + "emmc_nand_d4", + "emmc_nand_d3", + "emmc_nand_d2", + "emmc_nand_d1", + "emmc_nand_d0", + "emmc_clk", + "emmc_cmd"; + function = "emmc"; + input-enable; + bias-pull-up; + drive-strength = <3>; + }; + }; + + emmc_conf_pull_done:emmc_conf_pull_done { + mux { + groups = "emmc_nand_ds"; + function = "emmc"; + input-enable; + bias-pull-down; + drive-strength = <3>; + }; + }; + + /* sdemmc portB */ + sd_clk_cmd_pins:sd_clk_cmd_pins { + mux { + groups = "sdcard_cmd_c", + "sdcard_clk_c"; + function = "sdcard"; + input-enable; + bias-pull-up; + drive-strength = <3>; + }; + }; + + sd_all_pins:sd_all_pins { + mux { + groups = "sdcard_d0_c", + "sdcard_d1_c", + "sdcard_d2_c", + "sdcard_d3_c", + "sdcard_cmd_c", + "sdcard_clk_c"; + function = "sdcard"; + input-enable; + bias-pull-up; + drive-strength = <3>; + }; + }; + sd_1bit_pins:sd_1bit_pins { + mux { + groups = "sdcard_d0_c", + "sdcard_cmd_c", + "sdcard_clk_c"; + function = "sdcard"; + input-enable; + bias-pull-up; + drive-strength = <3>; + }; + }; + + ao_to_sd_uart_pins:ao_to_sd_uart_pins { + mux { + groups = "uart_ao_tx_a_c3", + "uart_ao_rx_a_c2"; + function = "uart_ao_a_ee"; + bias-pull-up; + input-enable; + }; + }; + /* sdemmc portA */ + sdio_clk_cmd_pins:sdio_clk_cmd_pins { + mux { + groups = "sdio_clk", + "sdio_cmd"; + function = "sdio"; + input-enable; + bias-pull-up; + drive-strength = <3>; + }; + }; + + sdio_all_pins:sdio_all_pins { + mux { + groups = "sdio_d0", + "sdio_d1", + "sdio_d2", + "sdio_d3", + "sdio_clk", + "sdio_cmd"; + function = "sdio"; + input-enable; + bias-pull-up; + drive-strength = <3>; + }; + }; + all_nand_pins: all_nand_pins { + mux { + groups = "emmc_nand_d0", + "emmc_nand_d1", + "emmc_nand_d2", + "emmc_nand_d3", + "emmc_nand_d4", + "emmc_nand_d5", + "emmc_nand_d6", + "emmc_nand_d7", + "nand_ce0", + "nand_ale", + "nand_cle", + "nand_wen_clk", + "nand_ren_wr", + "nand_rb0"; + function = "nand"; + input-enable; + }; + }; + + nand_cs_pins: nand_cs { + mux { + groups = "nand_ce0"; + function = "nand"; + }; + }; + + i2c0_master_pins1:i2c0_pins1 { + mux { + groups = "i2c0_sda_c", + "i2c0_sck_c"; + function = "i2c0"; + bias-pull-up; + drive-strength = <2>; + }; + }; + + i2c0_master_pins2:i2c0_pins2 { + mux { + groups = "i2c0_sda_z0", + "i2c0_sck_z1"; + function = "i2c0"; + bias-pull-up; + drive-strength = <2>; + }; + }; + + i2c0_master_pins3:i2c0_pins3 { + mux { + groups = "i2c0_sda_z7", + "i2c0_sck_z8"; + function = "i2c0"; + bias-pull-up; + drive-strength = <2>; + }; + }; + + i2c1_master_pins1:i2c1_pins1 { + mux { + groups = "i2c1_sda_x", + "i2c1_sck_x"; + function = "i2c1"; + bias-pull-up; + drive-strength = <2>; + }; + }; + + i2c1_master_pins2:i2c1_pins2 { + mux { + groups = "i2c1_sda_h2", + "i2c1_sck_h3"; + function = "i2c1"; + bias-pull-up; + drive-strength = <2>; + }; + }; + + i2c1_master_pins3:i2c1_pins3 { + mux { + groups = "i2c1_sda_h6", + "i2c1_sck_h7"; + function = "i2c1"; + bias-pull-up; + drive-strength = <2>; + }; + }; + + i2c2_master_pins1:i2c2_pins1 { + mux { + groups = "i2c2_sda_x", + "i2c2_sck_x"; + function = "i2c2"; + bias-pull-up; + drive-strength = <2>; + }; + }; + + i2c2_master_pins2:i2c2_pins2 { + mux { + groups = "i2c2_sda_z", + "i2c2_sck_z"; + function = "i2c2"; + bias-pull-up; + drive-strength = <2>; + }; + }; + + i2c3_master_pins1:i2c3_pins1 { + mux { + groups = "i2c3_sda_h", + "i2c3_sck_h"; + function = "i2c3"; + bias-pull-up; + drive-strength = <2>; + }; + }; + + i2c3_master_pins2:i2c3_pins2 { + mux { + groups = "i2c3_sda_a", + "i2c3_sck_a"; + function = "i2c3"; + bias-pull-up; + drive-strength = <2>; + }; + }; + + pwm_a_pins: pwm_a { + mux { + groups = "pwm_a"; + function = "pwm_a"; + }; + }; + + pwm_b_pins1: pwm_b_pins1 { + mux { + groups = "pwm_b_x7"; + function = "pwm_b"; + }; + }; + + pwm_b_pins2: pwm_b_pins2 { + mux { + groups = "pwm_b_x19"; + function = "pwm_b"; + }; + }; + + pwm_b_pins3: pwm_b_pins3 { + mux { + groups = "pwm_b_h"; + function = "pwm_b"; + }; + }; + + pwm_b_pins4: pwm_b_pins4 { + mux { + groups = "pwm_b_z0"; + function = "pwm_b"; + }; + }; + + pwm_b_pins5: pwm_b_pins5 { + mux { + groups = "pwm_b_z13"; + function = "pwm_b"; + }; + }; + + pwm_c_pins1: pwm_c_pins1 { + mux { + groups = "pwm_c_c4"; + function = "pwm_c"; + }; + }; + + pwm_c_pins2: pwm_c_pins2 { + mux { + groups = "pwm_c_x5"; + function = "pwm_c"; + }; + }; + + pwm_c_pins3: pwm_c_pins3 { + mux { + groups = "pwm_c_x8"; + function = "pwm_c"; + }; + }; + + pwm_c_pins4: pwm_c_pins4 { + mux { + groups = "pwm_c_z"; + function = "pwm_c"; + }; + }; + + pwm_d_pins1: pwm_d_pins1 { + mux { + groups = "pwm_d_x3"; + function = "pwm_d"; + }; + }; + + pwm_d_pins2: pwm_d_pins2 { + mux { + groups = "pwm_d_x6"; + function = "pwm_d"; + }; + }; + + pwm_d_pins3: pwm_d_pins3 { + mux { + groups = "pwm_d_z"; + function = "pwm_d"; + }; + }; + + pwm_d_pins4: pwm_d_pins4 { + mux { + groups = "pwm_d_a4"; + function = "pwm_d"; + }; + }; + + pwm_e_pins: pwm_e { + mux { + groups = "pwm_e"; + function = "pwm_e"; + }; + }; + + pwm_f_pins1: pwm_f_pins1 { + mux { + groups = "pwm_f_x"; + function = "pwm_f"; + }; + }; + + pwm_f_pins2: pwm_f_pins2 { + mux { + groups = "pwm_f_h"; + function = "pwm_f"; + }; + }; + + pwm_f_pins3: pwm_f_pins3 { + mux { + groups = "pwm_f_z"; + function = "pwm_f"; + }; + }; + + pwm_f_pins4: pwm_f_pins4 { + mux { + groups = "pwm_f_a11"; + function = "pwm_f"; + }; + }; + + spicc0_pins_x: spicc0_pins_x { + mux { + groups = "spi0_mosi_x", + "spi0_miso_x", + //"spi0_ss0_x", + "spi0_clk_x"; + function = "spi0"; + drive-strength = <1>; + }; + }; + + spicc1_pins: spicc1_pins { + mux { + groups = "spi1_mosi", + "spi1_miso", + //"spi1_ss0", + "spi1_clk"; + function = "spi1"; + drive-strength = <1>; + }; + }; + + a_uart_pins:a_uart { + mux { + groups = "uart_tx_a", + "uart_rx_a", + "uart_cts_a", + "uart_rts_a"; + function = "uart_a"; + }; + }; + + b_uart_pins:b_uart { + mux { + groups = "uart_tx_b", + "uart_rx_b"; + function = "uart_b"; + }; + }; + + c_uart_pins:c_uart { + mux { + groups = "uart_tx_c", + "uart_rx_c"; + function = "uart_c"; + }; + }; + + hdmitx_hpd: hdmitx_hpd { + mux { + groups = "hdmitx_hpd_in"; + function = "hdmitx"; + bias-disable; + }; + }; + + hdmitx_hpd_gpio: hdmitx_hpd_gpio { + mux { + groups = "GPIOH_1"; + function = "gpio_periphs"; + bias-disable; + }; + }; + + hdmitx_ddc: hdmitx_ddc { + mux { + groups = "hdmitx_sda", + "hdmitx_sck"; + function = "hdmitx"; + bias-disable; + }; + }; + + eecec_a: ee_ceca { + mux { + groups = "cec_ao_a_ee"; + function = "cec_ao_ee"; + }; + }; + + eecec_b: ee_cecb { + mux { + groups = "cec_ao_b_ee"; + function = "cec_ao_ee"; + }; + }; + + internal_eth_pins: internal_eth_pins { + mux { + groups = "eth_link_led", + "eth_act_led"; + function = "eth"; + }; + }; + + external_eth_pins: external_eth_pins { + mux { + groups = "eth_mdio", + "eth_mdc", + "eth_rgmii_rx_clk", + "eth_rx_dv", + "eth_rxd0", + "eth_rxd1", + "eth_rxd2_rgmii", + "eth_rxd3_rgmii", + "eth_rgmii_tx_clk", + "eth_txen", + "eth_txd0", + "eth_txd1", + "eth_txd2_rgmii", + "eth_txd3_rgmii"; + function = "eth"; + drive-strength = <3>; + }; + }; + + irblaster_pins2:irblaster_pins2 { + mux { + groups = "remote_out_h"; + function = "remote_out"; + }; + }; + + irblaster_pins3:irblaster_pins3 { + mux { + groups = "remote_out_z"; + function = "remote_out"; + }; + }; +}; + +&gpu{ + system-coherency = <0>; + tbl = <&dvfs285_cfg + &dvfs400_cfg + &dvfs500_cfg + &dvfs666_cfg + &dvfs800_cfg + &dvfs800_cfg>; +}; + +&pinctrl_aobus { + sd_to_ao_uart_clr_pins:sd_to_ao_uart_clr_pins { + mux { + groups = "GPIOAO_0", + "GPIOAO_1"; + function = "gpio_aobus"; + }; + }; + + sd_to_ao_uart_pins:sd_to_ao_uart_pins { + mux { + groups = "uart_ao_tx_a", + "uart_ao_rx_a"; + function = "uart_ao_a"; + bias-pull-up; + input-enable; + }; + }; + + remote_pins:remote_pin { + mux { + groups = "remote_input_ao"; + function = "remote_input_ao"; + }; + }; + + irblaster_pins:irblaster_pin { + mux { + groups = "remote_out_ao"; + function = "remote_out_ao"; + }; + }; + + irblaster_pins1:irblaster_pin1 { + mux { + groups = "remote_out_ao9"; + function = "remote_out_ao"; + }; + }; +}; /* end of pinctrl_aobus */ diff --git a/arch/arm/boot/dts/amlogic/mesong12b_skt-panel.dtsi b/arch/arm/boot/dts/amlogic/mesong12b_skt-panel.dtsi new file mode 100644 index 000000000000..aaa48ccf6394 --- /dev/null +++ b/arch/arm/boot/dts/amlogic/mesong12b_skt-panel.dtsi @@ -0,0 +1,823 @@ +/* + * arch/arm/boot/dts/amlogic/mesong12b_skt-panel.dtsi + * + * Copyright (C) 2016 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +/ { + lcd{ + compatible = "amlogic, lcd-g12b"; + mode = "tablet"; + status = "okay"; + key_valid = <0>; + clocks = <&clkc CLKID_MIPI_DSI_HOST + &clkc CLKID_MIPI_DSI_PHY + &clkc CLKID_DSI_MEAS_COMP + &clkc CLKID_VCLK2_ENCL + &clkc CLKID_VCLK2_VENCL + &clkc CLKID_GP0_PLL>; + clock-names = "dsi_host_gate", + "dsi_phy_gate", + "dsi_meas", + "encl_top_gate", + "encl_int_gate", + "gp0_pll"; + reg = <0xffd07000 0x400 /* dsi_host */ + 0xff644000 0x200>; /* dsi_phy */ + interrupts = <0 3 1 + 0 56 1>; + interrupt-names = "vsync","vsync2"; + pinctrl_version = <2>; /* for uboot */ + + /* power type: + * (0=cpu_gpio, 1=pmu_gpio, 2=signal,3=extern, 0xff=ending) + * power index: + * (point gpios_index, or extern_index,0xff=invalid) + * power value:(0=output low, 1=output high, 2=input) + * power delay:(unit in ms) + */ + lcd_cpu-gpios = <&gpio GPIOZ_9 GPIO_ACTIVE_HIGH + &gpio GPIOZ_8 GPIO_ACTIVE_HIGH>; + lcd_cpu_gpio_names = "GPIOZ_9","GPIOZ_8"; + + lcd_0{ + model_name = "B080XAN01"; + interface = "mipi"; + basic_setting = <768 1024 /*h_active, v_active*/ + 948 1140 /*h_period, v_period*/ + 8 /*lcd_bits*/ + 119 159>; /*screen_widht, screen_height*/ + lcd_timing = <64 56 0 /*hs_width, hs_bp, hs_pol*/ + 50 30 0>; /*vs_width, vs_bp, vs_pol*/ + clk_attr = <0 /*fr_adj_type(0=clk, 1=htotal, 2=vtotal)*/ + 0 /*clk_ss_level */ + 1 /*clk_auto_generate*/ + 64843200>; /*pixel_clk(unit in Hz)*/ + mipi_attr = <4 /*lane_num*/ + 550 /*bit_rate_max(MHz)*/ + 0 /*factor(*100, default 0 for auto)*/ + 1 /*operation_mode_init(0=video, 1=command)*/ + 0 /*operation_mode_display(0=video, 1=command)*/ + 2 /* + *video_mode_type + *(0=sync_pulse,1=sync_event,2=burst) + */ + 1 /*clk_always_hs(0=disable,1=enable)*/ + 0>; /*phy_switch(0=auto,1=standard,2=slow)*/ + + /* dsi_init: data_type, num, data... */ + dsi_init_on = <0x05 1 0x11 + 0xfd 1 20 /*delay(ms)*/ + 0x05 1 0x29 + 0xfd 1 20 /*delay(ms)*/ + 0xff 0>; /*ending*/ + dsi_init_off = <0x05 1 0x28 + 0xfd 1 10 /*delay(ms)*/ + 0x05 1 0x10 + 0xfd 1 10 /*delay(ms)*/ + 0xff 0>; /*ending*/ + extern_init = <0xff>; /*0xff for invalid*/ + + /* power step: type, index, value, delay(ms) */ + power_on_step = < + 0 1 0 100 + 0 0 0 10 + 0 0 1 20 + 2 0 0 0 + 0xff 0 0 0>; /*ending*/ + power_off_step = < + 2 0 0 50 + 0 0 0 10 + 0 1 1 100 + 0xff 0 0 0>; /*ending*/ + backlight_index = <0>; + }; + + lcd_1{ + model_name = "TL070WSH27"; + interface = "mipi"; + basic_setting = <1024 600 /*h_active, v_active*/ + 1250 630 /*h_period, v_period*/ + 8 /*lcd_bits*/ + 154 86>; /*screen_widht, screen_height*/ + lcd_timing = <80 100 0 /*hs_width, hs_bp, hs_pol*/ + 5 20 0>; /*vs_width, vs_bp, vs_pol*/ + clk_attr = <0 /*fr_adj_type(0=clk, 1=htotal, 2=vtotal)*/ + 0 /*clk_ss_level */ + 1 /*clk_auto_generate*/ + 47250000>; /*pixel_clk(unit in Hz)*/ + mipi_attr = <4 /*lane_num*/ + 300 /*bit_rate_max(MHz)*/ + 0 /*factor(*100, default 0 for auto)*/ + 1 /*operation_mode_init(0=video, 1=command)*/ + 0 /*operation_mode_display(0=video, 1=command)*/ + 2 /* + *video_mode_type + *(0=sync_pulse,1=sync_event,2=burst) + */ + 1 /*clk_always_hs(0=disable,1=enable)*/ + 0>; /*phy_switch(0=auto,1=standard,2=slow)*/ + + /* dsi_init: data_type, num, data... */ + dsi_init_on = <0x05 1 0x11 + 0xfd 1 200 /*delay(ms)*/ + 0x05 1 0x29 + 0xfd 1 20 /*delay(ms)*/ + 0xff 0>; /*ending*/ + dsi_init_off = <0x05 1 0x28 + 0xfd 1 10 /*delay(ms)*/ + 0x05 1 0x10 + 0xfd 1 10 /*delay(ms)*/ + 0xff 0>; /*ending*/ + extern_init = <0xff>; /*0xff for invalid*/ + + /* power step: type, index, value, delay(ms) */ + power_on_step = < + 0 1 0 100 + 0 0 0 10 + 0 0 1 20 + 2 0 0 0 + 0xff 0 0 0>; /*ending*/ + power_off_step = < + 2 0 0 50 + 0 0 0 10 + 0 1 1 100 + 0xff 0 0 0>; /*ending*/ + backlight_index = <0>; + }; + + lcd_2{ + model_name = "TL070HDV03CT"; + interface = "mipi"; + basic_setting = <720 1280 /*h_active, v_active*/ + 970 1364 /*h_period, v_period*/ + 8 /*lcd_bits*/ + 87 154>; /*screen_widht, screen_height*/ + lcd_timing = <10 120 0 /*hs_width, hs_bp, hs_pol*/ + 4 40 0>; /*vs_width, vs_bp, vs_pol*/ + clk_attr = <0 /*fr_adj_type(0=clk, 1=htotal, 2=vtotal)*/ + 0 /*clk_ss_level */ + 1 /*clk_auto_generate*/ + 79385000>; /*pixel_clk(unit in Hz)*/ + mipi_attr = <4 /*lane_num*/ + 500 /*bit_rate_max(MHz)*/ + 0 /*factor(*100, default 0 for auto)*/ + 1 /*operation_mode_init(0=video, 1=command)*/ + 0 /*operation_mode_display(0=video, 1=command)*/ + 2 /* + *video_mode_type + *(0=sync_pulse,1=sync_event,2=burst) + */ + 1 /*clk_always_hs(0=disable,1=enable)*/ + 0>; /*phy_switch(0=auto,1=standard,2=slow)*/ + + /* dsi_init: data_type, num, data... */ + dsi_init_on = <0xff 0>; /*ending*/ + dsi_init_off = <0xff 0>; /*ending*/ + extern_init = <1>; /*0xff for invalid*/ + + /* power step: type, index, value, delay(ms) */ + power_on_step = < + 0 1 0 100 + 0 0 0 10 + 0 0 1 20 + 2 0 0 0 + 0xff 0 0 0>; /*ending*/ + power_off_step = < + 2 0 0 50 + 0 0 0 10 + 0 1 1 100 + 0xff 0 0 0>; /*ending*/ + backlight_index = <0>; + }; + + lcd_3{ + model_name = "P070ACB_FT"; + interface = "mipi"; + basic_setting = <600 1024 /*h_active, v_active*/ + 770 1070 /*h_period, v_period*/ + 8 /*lcd_bits*/ + 3 5>; /*screen_widht, screen_height*/ + lcd_timing = <10 80 0 /*hs_width,hs_bp,hs_pol*/ + 6 20 0>; /*vs_width,vs_bp,vs_pol*/ + clk_attr = <0 /*fr_adj_type(0=clock,1=htotal,2=vtotal)*/ + 0 /*clk_ss_level*/ + 1 /*clk_auto_generate*/ + 49434000>; /*pixel_clk(unit in Hz)*/ + mipi_attr = <4 /*lane_num*/ + 400 /*bit_rate_max(MHz)*/ + 0 /*factor(*100, default 0 for auto)*/ + 1 /*operation_mode_init(0=video, 1=command)*/ + 0 /*operation_mode_display(0=video, 1=command)*/ + 2 /* + *video_mode_type + *(0=sync_pulse,1=sync_event,2=burst) + */ + 0 /*clk_always_hs(0=disable,1=enable)*/ + 0>; /*phy_switch(0=auto,1=standard,2=slow)*/ + /* dsi_init: data_type, num, data... */ + dsi_init_on = < + 0xff 10 + 0xf0 3 0 1 30 /* reset high, delay 30ms */ + 0xf0 3 0 0 10 /* reset low, delay 10ms */ + 0xf0 3 0 1 30 /* reset high, delay 30ms */ + 0xfc 2 0x04 3 /* check_reg, check_cnt */ + 0xff 0>; /* ending flag */ + dsi_init_off = <0xff 0>; /* ending flag */ + /* extern_init: 0xff for invalid */ + extern_init = <2>; + /* power step: type,index,value,delay(ms) */ + power_on_step = < + 0 1 0 200 /* panel power on */ + 2 0 0 0 + 0xff 0 0 0>; + power_off_step = < + 2 0 0 0 + 0 0 0 20 /* reset low */ + 0 1 1 100 /* panel power off */ + 0xff 0 0 0>; + backlight_index = <0>; + }; + }; + + lcd_extern{ + compatible = "amlogic, lcd_extern"; + status = "okay"; + i2c_bus = "i2c_bus_0"; + key_valid = <0>; + + extern_0{ + index = <0>; + extern_name = "mipi_default";/*default*/ + status = "okay"; + type = <2>; /* 0=i2c, 1=spi, 2=mipi */ + cmd_size = <0xff>; + init_on = < + 0xfd 1 10 + 0x05 1 0x11 + 0xfd 1 120 /* delay 120ms */ + 0x05 1 0x29 + 0xff 0>; /*ending*/ + init_off = < + 0x05 1 0x28 /* display off */ + 0xfd 1 10 /* delay 10ms */ + 0x05 1 0x10 /* sleep in */ + 0xfd 1 150 /* delay 150ms */ + 0xff 0>; /*ending*/ + }; + + extern_1{ + index = <1>; + extern_name = "mipi_default";/*TL070HDV03CT*/ + status = "okay"; + type = <2>; /* 0=i2c, 1=spi, 2=mipi */ + cmd_size = <0xff>; + init_on = < + 0x39 4 0xFF 0x98 0x81 0x03 + 0x15 2 0x01 0x00 + 0x15 2 0x02 0x00 + 0x15 2 0x03 0x72 + 0x15 2 0x04 0x00 + 0x15 2 0x05 0x00 + 0x15 2 0x06 0x09 + 0x15 2 0x07 0x00 + 0x15 2 0x08 0x00 + 0x15 2 0x09 0x01 + 0x15 2 0x0A 0x00 + 0x15 2 0x0B 0x00 + 0x15 2 0x0C 0x01 + 0x15 2 0x0D 0x00 + 0x15 2 0x0E 0x00 + 0x15 2 0x0F 0x14 + 0x15 2 0x10 0x14 + 0x15 2 0x11 0x00 + 0x15 2 0x12 0x00 + 0x15 2 0x13 0x00 + 0x15 2 0x14 0x00 + 0x15 2 0x15 0x00 + 0x15 2 0x16 0x00 + 0x15 2 0x17 0x00 + 0x15 2 0x18 0x00 + 0x15 2 0x19 0x00 + 0x15 2 0x1A 0x00 + 0x15 2 0x1B 0x00 + 0x15 2 0x1C 0x00 + 0x15 2 0x1D 0x00 + 0x15 2 0x1E 0x40 + 0x15 2 0x1F 0x80 + 0x15 2 0x20 0x05 + 0x15 2 0x21 0x02 + 0x15 2 0x22 0x00 + 0x15 2 0x23 0x00 + 0x15 2 0x24 0x00 + 0x15 2 0x25 0x00 + 0x15 2 0x26 0x00 + 0x15 2 0x27 0x00 + 0x15 2 0x28 0x33 + 0x15 2 0x29 0x02 + 0x15 2 0x2A 0x00 + 0x15 2 0x2B 0x00 + 0x15 2 0x2C 0x00 + 0x15 2 0x2D 0x00 + 0x15 2 0x2E 0x00 + 0x15 2 0x2F 0x00 + 0x15 2 0x30 0x00 + 0x15 2 0x31 0x00 + 0x15 2 0x32 0x00 + 0x15 2 0x33 0x00 + 0x15 2 0x34 0x04 + 0x15 2 0x35 0x00 + 0x15 2 0x36 0x00 + 0x15 2 0x37 0x00 + 0x15 2 0x38 0x3C + 0x15 2 0x39 0x00 + 0x15 2 0x3A 0x00 + 0x15 2 0x3B 0x00 + 0x15 2 0x3C 0x00 + 0x15 2 0x3D 0x00 + 0x15 2 0x3E 0x00 + 0x15 2 0x3F 0x00 + 0x15 2 0x40 0x00 + 0x15 2 0x41 0x00 + 0x15 2 0x42 0x00 + 0x15 2 0x43 0x00 + 0x15 2 0x44 0x00 + + 0x15 2 0x50 0x10 + 0x15 2 0x51 0x32 + 0x15 2 0x52 0x54 + 0x15 2 0x53 0x76 + 0x15 2 0x54 0x98 + 0x15 2 0x55 0xBA + 0x15 2 0x56 0x10 + 0x15 2 0x57 0x32 + 0x15 2 0x58 0x54 + 0x15 2 0x59 0x76 + 0x15 2 0x5A 0x98 + 0x15 2 0x5B 0xBA + 0x15 2 0x5C 0xDC + 0x15 2 0x5D 0xFE + 0x15 2 0x5E 0x00 + 0x15 2 0x5F 0x0E + 0x15 2 0x60 0x0F + 0x15 2 0x61 0x0C + 0x15 2 0x62 0x0D + 0x15 2 0x63 0x06 + 0x15 2 0x64 0x07 + 0x15 2 0x65 0x02 + 0x15 2 0x66 0x02 + 0x15 2 0x67 0x02 + 0x15 2 0x68 0x02 + 0x15 2 0x69 0x01 + 0x15 2 0x6A 0x00 + 0x15 2 0x6B 0x02 + 0x15 2 0x6C 0x15 + 0x15 2 0x6D 0x14 + 0x15 2 0x6E 0x02 + 0x15 2 0x6F 0x02 + 0x15 2 0x70 0x02 + 0x15 2 0x71 0x02 + 0x15 2 0x72 0x02 + 0x15 2 0x73 0x02 + 0x15 2 0x74 0x02 + 0x15 2 0x75 0x0E + 0x15 2 0x76 0x0F + 0x15 2 0x77 0x0C + 0x15 2 0x78 0x0D + 0x15 2 0x79 0x06 + 0x15 2 0x7A 0x07 + 0x15 2 0x7B 0x02 + 0x15 2 0x7C 0x02 + 0x15 2 0x7D 0x02 + 0x15 2 0x7E 0x02 + 0x15 2 0x7F 0x01 + 0x15 2 0x80 0x00 + 0x15 2 0x81 0x02 + 0x15 2 0x82 0x14 + 0x15 2 0x83 0x15 + 0x15 2 0x84 0x02 + 0x15 2 0x85 0x02 + 0x15 2 0x86 0x02 + 0x15 2 0x87 0x02 + 0x15 2 0x88 0x02 + 0x15 2 0x89 0x02 + 0x15 2 0x8A 0x02 + + 0x39 4 0xFF 0x98 0x81 0x04 + 0x15 2 0x6C 0x15 + 0x15 2 0x6E 0x2A + 0x15 2 0x6F 0x33 /* 33 */ + 0x15 2 0x3A 0x94 + 0x15 2 0x8D 0x14 + 0x15 2 0x87 0xBA + 0x15 2 0x26 0x76 + 0x15 2 0xB2 0xD1 + 0x15 2 0xB5 0x06 + + 0x39 4 0xFF 0x98 0x81 0x01 + 0x15 2 0x22 0x02 /* xiugai RGB */ + 0x15 2 0x31 0x00 /* dot inv */ + /*0x15 2 0x52 0x00*/ + 0x15 2 0x53 0x72 /* vcom */ + /*0x15 2 0x54 0x00 // vcom */ + 0x15 2 0x55 0x88 + + 0x15 2 0x40 0x33 + + 0x15 2 0x50 0x96 + 0x15 2 0x51 0x96 + + 0x15 2 0x60 0x08 + + 0x15 2 0xA0 0x08 /* GAMMA P */ + 0x15 2 0xA1 0x1D + 0x15 2 0xA2 0x2A + 0x15 2 0xA3 0x10 + 0x15 2 0xA4 0x15 + 0x15 2 0xA5 0x28 + 0x15 2 0xA6 0x1C + 0x15 2 0xA7 0x1D + 0x15 2 0xA8 0x7E + 0x15 2 0xA9 0x1D + 0x15 2 0xAA 0x29 + 0x15 2 0xAB 0x6B + 0x15 2 0xAC 0x1A + 0x15 2 0xAD 0x18 + 0x15 2 0xAE 0x4B + 0x15 2 0xAF 0x20 + 0x15 2 0xB0 0x27 + 0x15 2 0xB1 0x50 + 0x15 2 0xB2 0x64 + 0x15 2 0xB3 0x39 + + 0x15 2 0xC0 0x08 /* GAMMA N */ + 0x15 2 0xC1 0x1D + 0x15 2 0xC2 0x2A + 0x15 2 0xC3 0x10 + 0x15 2 0xC4 0x15 + 0x15 2 0xC5 0x28 + 0x15 2 0xC6 0x1C + 0x15 2 0xC7 0x1D + 0x15 2 0xC8 0x7E + 0x15 2 0xC9 0x1D + 0x15 2 0xCA 0x29 + 0x15 2 0xCB 0x6B + 0x15 2 0xCC 0x1A + 0x15 2 0xCD 0x18 + 0x15 2 0xCE 0x4B + 0x15 2 0xCF 0x20 + 0x15 2 0xD0 0x27 + 0x15 2 0xD1 0x50 + 0x15 2 0xD2 0x64 + 0x15 2 0xD3 0x39 + + 0x39 4 0xFF 0x98 0x81 0x00 + + 0x15 2 0x3A 0x77 + 0xfd 1 2 + + 0x15 2 0x36 0x08 + + 0x05 1 0x11 /* display on */ + 0xfd 1 200 + + 0x05 1 0x29 /* display on */ + 0xfd 1 200 + 0xFF 0>; /*ending*/ + init_off = < + 0x05 1 0x28 /* display off */ + 0xfd 1 10 /* delay 10ms */ + 0x05 1 0x10 /* sleep in */ + 0xfd 1 150 /* delay 150ms */ + 0xff 0>; /*ending*/ + }; + + extern_2{ + index = <2>; + extern_name = "mipi_default";/*P070ACB_FT*/ + status = "okay"; + type = <2>; /* 0=i2c, 1=spi, 2=mipi */ + cmd_size = <0xff>; + init_on = < + 0x23 2 0xE0 0x00 /* Page 0 */ + 0x23 2 0xE1 0x93 /* PASSWORD */ + 0x23 2 0xE2 0x65 + 0x23 2 0xE3 0xF8 + 0x23 2 0x80 0x03 + 0x23 2 0xE0 0x01 /* Page 01 */ + 0x23 2 0x0C 0x74 /* Set PWRIC */ + 0x23 2 0x17 0x00 /* Set Gamma Power */ + 0x23 2 0x18 0xEF /* VGMP=5.1V */ + 0x23 2 0x19 0x00 + 0x23 2 0x1A 0x00 + 0x23 2 0x1B 0xEF /* VGMN=-5.1V */ + 0x23 2 0x1C 0x00 + 0x23 2 0x1F 0x70 /* Set Gate Power */ + 0x23 2 0x20 0x2D + 0x23 2 0x21 0x2D + 0x23 2 0x22 0x7E + 0x23 2 0x26 0xF3 /* VDDD from IOVCC */ + 0x23 2 0x37 0x09 /* SetPanel */ + 0x23 2 0x38 0x04 /* SET RGBCYC */ + 0x23 2 0x39 0x00 + 0x23 2 0x3A 0x01 + 0x23 2 0x3C 0x90 + 0x23 2 0x3D 0xFF + 0x23 2 0x3E 0xFF + 0x23 2 0x3F 0xFF + 0x23 2 0x40 0x02 /* Set TCON */ + 0x23 2 0x41 0x80 + 0x23 2 0x42 0x99 + 0x23 2 0x43 0x14 + 0x23 2 0x44 0x19 + 0x23 2 0x45 0x5A + 0x23 2 0x4B 0x04 + 0x23 2 0x55 0x02 /* power voltage */ + 0x23 2 0x56 0x01 + 0x23 2 0x57 0x69 + 0x23 2 0x58 0x0A + 0x23 2 0x59 0x0A + 0x23 2 0x5A 0x2E /* VGH = 16.2V */ + 0x23 2 0x5B 0x19 /* VGL = -12V */ + 0x23 2 0x5C 0x15 + 0x23 2 0x5D 0x77 /* Gamma */ + 0x23 2 0x5E 0x56 + 0x23 2 0x5F 0x45 + 0x23 2 0x60 0x38 + 0x23 2 0x61 0x35 + 0x23 2 0x62 0x27 + 0x23 2 0x63 0x2D + 0x23 2 0x64 0x18 + 0x23 2 0x65 0x33 + 0x23 2 0x66 0x34 + 0x23 2 0x67 0x35 + 0x23 2 0x68 0x56 + 0x23 2 0x69 0x45 + 0x23 2 0x6A 0x4F + 0x23 2 0x6B 0x42 + 0x23 2 0x6C 0x40 + 0x23 2 0x6D 0x34 + 0x23 2 0x6E 0x25 + 0x23 2 0x6F 0x02 + 0x23 2 0x70 0x77 + 0x23 2 0x71 0x56 + 0x23 2 0x72 0x45 + 0x23 2 0x73 0x38 + 0x23 2 0x74 0x35 + 0x23 2 0x75 0x27 + 0x23 2 0x76 0x2D + 0x23 2 0x77 0x18 + 0x23 2 0x78 0x33 + 0x23 2 0x79 0x34 + 0x23 2 0x7A 0x35 + 0x23 2 0x7B 0x56 + 0x23 2 0x7C 0x45 + 0x23 2 0x7D 0x4F + 0x23 2 0x7E 0x42 + 0x23 2 0x7F 0x40 + 0x23 2 0x80 0x34 + 0x23 2 0x81 0x25 + 0x23 2 0x82 0x02 + 0x23 2 0xE0 0x02 /* Page2 */ + 0x23 2 0x00 0x53 + /* GIP_L Pin mapping RESET_EVEN */ + 0x23 2 0x01 0x55 /* VSSG_EVEN */ + 0x23 2 0x02 0x55 /* VSSA_EVEN */ + 0x23 2 0x03 0x51 /* STV2_EVEN */ + 0x23 2 0x04 0x77 /* VDD2_EVEN */ + 0x23 2 0x05 0x57 /* VDD1_EVEN */ + 0x23 2 0x06 0x1F + 0x23 2 0x07 0x4F /* CK12 */ + 0x23 2 0x08 0x4D /* CK10 */ + 0x23 2 0x09 0x1F + 0x23 2 0x0A 0x4B /* CK8 */ + 0x23 2 0x0B 0x49 /* CK6 */ + 0x23 2 0x0C 0x1F + 0x23 2 0x0D 0x47 /* CK4 */ + 0x23 2 0x0E 0x45 /* CK2 */ + 0x23 2 0x0F 0x41 /* STV1_EVEN */ + 0x23 2 0x10 0x1F + 0x23 2 0x11 0x1F + 0x23 2 0x12 0x1F + 0x23 2 0x13 0x55 /* VGG */ + 0x23 2 0x14 0x1F + 0x23 2 0x15 0x1F + 0x23 2 0x16 0x52 + /* GIP_R Pin mapping RESET_ODD */ + 0x23 2 0x17 0x55 /* VSSG_ODD */ + 0x23 2 0x18 0x55 /* VSSA_ODD */ + 0x23 2 0x19 0x50 /* STV2_ODD */ + 0x23 2 0x1A 0x77 /* VDD2_ODD */ + 0x23 2 0x1B 0x57 /* VDD1_ODD */ + 0x23 2 0x1C 0x1F + 0x23 2 0x1D 0x4E /* CK11 */ + 0x23 2 0x1E 0x4C /* CK9 */ + 0x23 2 0x1F 0x1F + 0x23 2 0x20 0x4A /* CK7 */ + 0x23 2 0x21 0x48 /* CK5 */ + 0x23 2 0x22 0x1F + 0x23 2 0x23 0x46 /* CK3 */ + 0x23 2 0x24 0x44 /* CK1 */ + 0x23 2 0x25 0x40 /* STV1_ODD */ + 0x23 2 0x26 0x1F + 0x23 2 0x27 0x1F + 0x23 2 0x28 0x1F + 0x23 2 0x29 0x1F + 0x23 2 0x2A 0x1F + 0x23 2 0x2B 0x55 /* VGG */ + 0x23 2 0x2C 0x12 /* GIP_L_GS Pin mapping */ + 0x23 2 0x2D 0x15 + 0x23 2 0x2E 0x15 + 0x23 2 0x2F 0x00 + 0x23 2 0x30 0x37 + 0x23 2 0x31 0x17 + 0x23 2 0x32 0x1F + 0x23 2 0x33 0x08 + 0x23 2 0x34 0x0A + 0x23 2 0x35 0x1F + 0x23 2 0x36 0x0C + 0x23 2 0x37 0x0E + 0x23 2 0x38 0x1F + 0x23 2 0x39 0x04 + 0x23 2 0x3A 0x06 + 0x23 2 0x3B 0x10 + 0x23 2 0x3C 0x1F + 0x23 2 0x3D 0x1F + 0x23 2 0x3E 0x1F + 0x23 2 0x3F 0x15 + 0x23 2 0x40 0x1F + 0x23 2 0x41 0x1F + 0x23 2 0x42 0x13 /* GIP_R_GS Pin mapping */ + 0x23 2 0x43 0x15 + 0x23 2 0x44 0x15 + 0x23 2 0x45 0x01 + 0x23 2 0x46 0x37 + 0x23 2 0x47 0x17 + 0x23 2 0x48 0x1F + 0x23 2 0x49 0x09 + 0x23 2 0x4A 0x0B + 0x23 2 0x4B 0x1F + 0x23 2 0x4C 0x0D + 0x23 2 0x4D 0x0F + 0x23 2 0x4E 0x1F + 0x23 2 0x4F 0x05 + 0x23 2 0x50 0x07 + 0x23 2 0x51 0x11 + 0x23 2 0x52 0x1F + 0x23 2 0x53 0x1F + 0x23 2 0x54 0x1F + 0x23 2 0x55 0x1F + 0x23 2 0x56 0x1F + 0x23 2 0x57 0x15 + 0x23 2 0x58 0x40 /* GIP Timing */ + 0x23 2 0x59 0x00 + 0x23 2 0x5A 0x00 + 0x23 2 0x5B 0x10 + 0x23 2 0x5C 0x14 + 0x23 2 0x5D 0x40 + 0x23 2 0x5E 0x01 + 0x23 2 0x5F 0x02 + 0x23 2 0x60 0x40 + 0x23 2 0x61 0x03 + 0x23 2 0x62 0x04 + 0x23 2 0x63 0x7A + 0x23 2 0x64 0x7A + 0x23 2 0x65 0x74 + 0x23 2 0x66 0x16 + 0x23 2 0x67 0xB4 + 0x23 2 0x68 0x16 + 0x23 2 0x69 0x7A + 0x23 2 0x6A 0x7A + 0x23 2 0x6B 0x0C + 0x23 2 0x6C 0x00 + 0x23 2 0x6D 0x04 + 0x23 2 0x6E 0x04 + 0x23 2 0x6F 0x88 + 0x23 2 0x70 0x00 + 0x23 2 0x71 0x00 + 0x23 2 0x72 0x06 + 0x23 2 0x73 0x7B + 0x23 2 0x74 0x00 + 0x23 2 0x75 0xBC + 0x23 2 0x76 0x00 + 0x23 2 0x77 0x04 + 0x23 2 0x78 0x2C + 0x23 2 0x79 0x00 + 0x23 2 0x7A 0x00 + 0x23 2 0x7B 0x00 + 0x23 2 0x7C 0x00 + 0x23 2 0x7D 0x03 + 0x23 2 0x7E 0x7B + 0x23 2 0xE0 0x04 /* Page4 */ + 0x23 2 0x09 0x11 /* Set RGBCYC2 */ + 0x23 2 0x0E 0x48 + 0x23 2 0x2B 0x2B /* ESD Protect */ + 0x23 2 0x2E 0x44 + 0x23 2 0xE0 0x00 /* Page0 */ + 0x23 2 0xE6 0x02 /* Watch dog */ + 0x23 2 0xE7 0x0C + 0x05 1 0x11 /* sleep out */ + 0xfd 1 120 + 0x05 1 0x29 /* display on */ + 0x05 1 0x35 + 0xfd 1 20 /* delay(ms) */ + 0xFF 0>; /*ending*/ + init_off = < + 0x05 1 0x28 /* display off */ + 0xfd 1 10 /* delay 10ms */ + 0x05 1 0x10 /* sleep in */ + 0xfd 1 150 /* delay 150ms */ + 0xff 0>; /*ending*/ + }; + }; + + backlight{ + compatible = "amlogic, backlight-g12b"; + status = "okay"; + key_valid = <0>; + pinctrl-names = "pwm_on","pwm_off"; + pinctrl-0 = <&pwm_f_pins2>; + pinctrl-1 = <&bl_pwm_off_pins>; + pinctrl_version = <2>; /* for uboot */ + bl_pwm_config = <&bl_pwm_conf>; + bl-gpios = <&gpio GPIOH_4 GPIO_ACTIVE_HIGH + &gpio GPIOH_5 GPIO_ACTIVE_HIGH>; + bl_gpio_names = "GPIOH_4","GPIOH_5"; + + /* pwm port: PWM_A, PWM_B, PWM_C, PWM_D, PWM_E, PWM_F, PWM_VS*/ + /* power index:(point gpios_index, 0xff=invalid) + * power value:(0=output low, 1=output high, 2=input) + * power delay:(unit in ms) + */ + + backlight_0{ + index = <0>; + bl_name = "backlight_pwm"; + bl_level_default_uboot_kernel = <100 100>; + bl_level_attr = <255 10 /*max, min*/ + 128 128>; /*mid, mid_mapping*/ + bl_ctrl_method = <1>; /* 1=pwm, 2=pwm_combo, 4=extern */ + bl_power_attr = <0 /*en_gpio_index*/ + 1 0 /*on_value, off_value*/ + 200 200>; /*on_delay(ms), off_delay(ms)*/ + bl_pwm_port = "PWM_F"; + bl_pwm_attr = <0 /*pwm_method*/ + 180 /*pwm_freq(pwm:Hz, pwm_vs:multiple of vs)*/ + 100 25>; /*duty_max(%), duty_min(%)*/ + bl_pwm_power = <1 1 /*pwm_gpio_index, pwm_gpio_off*/ + 10 10>; /*pwm_on_delay(ms), pwm_off_delay(ms)*/ + bl_pwm_en_sequence_reverse = <0>; /* 1 for reverse */ + }; + backlight_1{ + index = <1>; + bl_name = "bl_extern"; + bl_level_default_uboot_kernel = <100 100>; + bl_level_attr = <255 10 /*max, min*/ + 128 128>; /*mid, mid_mapping*/ + bl_ctrl_method = <4>; /*1=pwm, 2=pwm_combo, 4=extern*/ + bl_power_attr = <1 /*en_gpio_index*/ + 1 0 /*on_value, off_value*/ + 200 200>; /*on_delay(ms), off_delay(ms)*/ + bl_extern_index = <0>; + }; + }; + bl_pwm_conf:bl_pwm_conf{ + pwm_channel_0 { + pwm_port_index = <5>; + pwms = <&pwm_ef MESON_PWM_1 30040 0>; + }; + }; + + bl_extern{ + compatible = "amlogic, bl_extern"; + status = "disabled"; + i2c_bus = "i2c_bus_3"; + + extern_0{ + index = <0>; + extern_name = "i2c_lp8556"; + type = <0>; /*0=i2c, 1=spi, 2=mipi*/ + i2c_address = <0x2c>; /*7bit i2c address*/ + dim_max_min = <255 10>; + }; + + extern_1{ + index = <1>; + extern_name = "mipi_lt070me05"; + type = <2>; /*0=i2c, 1=spi, 2=mipi*/ + dim_max_min = <255 10>; + }; + }; +};/* end of panel */ + diff --git a/arch/arm/boot/dts/amlogic/mesongxl.dtsi b/arch/arm/boot/dts/amlogic/mesongxl.dtsi index 10a3a83e2b02..a220ea1c4fd3 100644 --- a/arch/arm/boot/dts/amlogic/mesongxl.dtsi +++ b/arch/arm/boot/dts/amlogic/mesongxl.dtsi @@ -49,7 +49,7 @@ }; CPU0:cpu@0 { device_type = "cpu"; - compatible = "arm,cortex-a9"; + compatible = "arm,cortex-a53","arm,armv8"; reg = <0x0>; enable-method = "psci"; clocks = <&scpi_dvfs 0>; @@ -60,7 +60,7 @@ CPU1:cpu@1 { device_type = "cpu"; - compatible = "arm,cortex-a9"; + compatible = "arm,cortex-a53","arm,armv8"; reg = <0x1>; enable-method = "psci"; clocks = <&scpi_dvfs 0>; @@ -70,7 +70,7 @@ }; CPU2:cpu@2 { device_type = "cpu"; - compatible = "arm,cortex-a9"; + compatible = "arm,cortex-a53","arm,armv8"; reg = <0x2>; enable-method = "psci"; clocks = <&scpi_dvfs 0>; @@ -81,7 +81,7 @@ CPU3:cpu@3 { device_type = "cpu"; - compatible = "arm,cortex-a9"; + compatible = "arm,cortex-a53","arm,armv8"; reg = <0x3>; enable-method = "psci"; clocks = <&scpi_dvfs 0>; @@ -232,7 +232,8 @@ status = "okay"; }; - watchdog { + + wdt: watchdog@0xffd0f0d0 { compatible = "amlogic, meson-wdt"; status = "okay"; default_timeout=<10>; @@ -567,6 +568,13 @@ compatible = "amlogic, vdac-gxl"; status = "okay"; }; + + defendkey: defendkey { + compatible = "amlogic, defendkey"; + reg = <0xc8834500 0x4>; /*RNG_USR_DATA*/ + mem_size = <0x0 0x100000>; + status = "okay"; + }; }; /* end of root */ &pinctrl_aobus { diff --git a/arch/arm/boot/dts/amlogic/mesongxl_p212-panel.dtsi b/arch/arm/boot/dts/amlogic/mesongxl_p212-panel.dtsi new file mode 100644 index 000000000000..655fae9a687b --- /dev/null +++ b/arch/arm/boot/dts/amlogic/mesongxl_p212-panel.dtsi @@ -0,0 +1,148 @@ +/* + * arch/arm/boot/dts/amlogic/mesongxl_p212-panel.dtsi + * + * Copyright (C) 2016 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +/ { + lcd{ + compatible = "amlogic, lcd-gxl"; + mode = "tablet"; + status = "okay"; + key_valid = <0>; + /* clocks = <&clkc CLKID_VCLK2_ENCL + * &clkc CLKID_VCLK2_VENCL>; + * clock-names = "vencl_top_gate", + * "vencl_int_gate"; + */ + reg = <0xc8834400 0x100>; + interrupts = <0 3 1>; + interrupt-names = "vsync"; + pinctrl_version = <1>; /* for uboot */ + pinctrl-names = "ttl_6bit_hvsync_de_on", + "ttl_6bit_hvsync_on", + "ttl_6bit_de_on", + "ttl_6bit_hvsync_de_off", + "ttl_8bit_hvsync_de_on", + "ttl_8bit_hvsync_on", + "ttl_8bit_de_on", + "ttl_8bit_hvsync_de_off"; + pinctrl-0 = <&lcd_ttl_rgb_6bit_on_pins + &lcd_ttl_de_hvsync_on_pins>; + pinctrl-1 = <&lcd_ttl_rgb_6bit_on_pins + &lcd_ttl_hvsync_on_pins>; + pinctrl-2 = <&lcd_ttl_rgb_6bit_on_pins + &lcd_ttl_de_on_pins>; + pinctrl-3 = <&lcd_ttl_rgb_6bit_off_pins + &lcd_ttl_de_hvsync_off_pins>; + pinctrl-4 = <&lcd_ttl_rgb_8bit_on_pins + &lcd_ttl_de_hvsync_on_pins>; + pinctrl-5 = <&lcd_ttl_rgb_8bit_on_pins + &lcd_ttl_hvsync_on_pins>; + pinctrl-6 = <&lcd_ttl_rgb_8bit_on_pins + &lcd_ttl_de_on_pins>; + pinctrl-7 = <&lcd_ttl_rgb_8bit_off_pins + &lcd_ttl_de_hvsync_off_pins>; + + /* power type: + * (0=cpu_gpio, 1=pmu_gpio, 2=signal,3=extern, 0xff=ending) + * power index: + * (point gpios_index, or extern_index,0xff=invalid) + * power value:(0=output low, 1=output high, 2=input) + * power delay:(unit in ms) + */ + /*lcd_cpu-gpios = <&gpio GPIOX_3 GPIO_ACTIVE_HIGH>;*/ + /*lcd_cpu_gpio_names = "GPIOX_3";*/ + + lcd_0{ + model_name = "LCD720P"; + interface = "ttl"; + basic_setting = <1280 720 /*h_active, v_active*/ + 1650 750 /*h_period, v_period*/ + 8 /*lcd_bits */ + 16 9>; /*screen_widht, screen_height*/ + lcd_timing = <40 220 1 /*hs_width, hs_bp, hs_pol*/ + 5 20 1>; /*vs_width, vs_bp, vs_pol*/ + clk_attr = <0 /*fr_adj_type(0=clk, 1=htotal, 2=vtotal)*/ + 0 /*clk_ss_level*/ + 1 /*clk_auto_generate*/ + 74250000>; /*pixel_clk(unit in Hz)*/ + ttl_attr = <0 /*clk_pol*/ + 1 /*de_valid*/ + 1 /*hvsync_valid*/ + 0 /*rb_swap*/ + 0>; /*bit_swap*/ + + /* power step: type, index, value, delay(ms) */ + power_on_step = <2 0 0 0 + 0xff 0 0 0>; /*ending*/ + power_off_step = <2 0 0 50 + 0xff 0 0 0>; /*ending*/ + backlight_index = <0xff>; + }; + }; + + lcd_extern{ + compatible = "amlogic, lcd_extern"; + status = "disabled"; + i2c_bus = "i2c_bus_d"; + key_valid = <0>; + + extern_0{ + index = <0>; + extern_name = "ext_default"; + status = "disabled"; + type = <0>; /* 0=i2c, 1=spi, 2=mipi */ + i2c_address = <0x1c>; /* 7bit i2c address */ + i2c_address2 = <0xff>; /* 0xff for none */ + cmd_size = <0xff>; /*0xff for dynamic cmd_size*/ + + /* init on/off: + * fixed cmd_size: (type, value...); + * cmd_size include all data. + * dynamic cmd_size: (type, cmd_size, value...); + * cmd_size include value. + */ + /* type: 0x00=cmd with delay(bit[3:0]=1 for address2), + * 0xc0=cmd(bit[3:0]=1 for address2), + * 0xf0=gpio, + * 0xfd=delay, + * 0xff=ending + */ + /* value: i2c or spi cmd, or gpio index & level */ + /* delay: unit ms */ + init_on = < + 0xc0 7 0x20 0x01 0x02 0x00 0x40 0xFF 0x00 + 0xc0 7 0x80 0x02 0x00 0x40 0x62 0x51 0x73 + 0xc0 7 0x61 0x06 0x00 0x00 0x00 0x00 0x00 + 0xc0 7 0xC1 0x05 0x0F 0x00 0x08 0x70 0x00 + 0xc0 7 0x13 0x01 0x00 0x00 0x00 0x00 0x00 + 0xc0 7 0x3D 0x02 0x01 0x00 0x00 0x00 0x00 + 0xc0 7 0xED 0x0D 0x01 0x00 0x00 0x00 0x00 + 0xc0 7 0x23 0x02 0x00 0x00 0x00 0x00 0x00 + 0xfd 1 10 /* delay 10ms */ + 0xff 0>; /*ending*/ + init_off = <0xff 0>; /*ending*/ + }; + + extern_1{ + index = <1>; + extern_name = "i2c_DLPC3439"; + status = "disabled"; + type = <0>; /* 0=i2c, 1=spi, 2=mipi */ + i2c_address = <0x1b>; /* 7bit i2c address */ + }; + }; +};/* end of panel */ + diff --git a/arch/arm/boot/dts/amlogic/mesongxl_sei210.dtsi b/arch/arm/boot/dts/amlogic/mesongxl_sei210.dtsi new file mode 100644 index 000000000000..9f4e451d488d --- /dev/null +++ b/arch/arm/boot/dts/amlogic/mesongxl_sei210.dtsi @@ -0,0 +1,1324 @@ +/* + * arch/arm/boot/dts/amlogic/mesongxl.dtsi + * + * Copyright (C) 2017 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "mesongxbb-gpu-mali450.dtsi" +/ { + cpus:cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu-map { + cluster0:cluster0 { + core0 { + cpu = <&CPU0>; + }; + core1 { + cpu = <&CPU1>; + }; + core2 { + cpu = <&CPU2>; + }; + core3 { + cpu = <&CPU3>; + }; + }; + }; + CPU0:cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0x0>; + enable-method = "psci"; + clocks = <&scpi_dvfs 0>; + clock-names = "cpu-cluster.0"; + cpu-idle-states = <&SYSTEM_SLEEP_0>; + /*cpu-idle-states = <&CPU_SLEEP_0 &SYSTEM_SLEEP_0>;*/ + }; + + CPU1:cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0x1>; + enable-method = "psci"; + clocks = <&scpi_dvfs 0>; + clock-names = "cpu-cluster.0"; + cpu-idle-states = <&SYSTEM_SLEEP_0>; + /*cpu-idle-states = <&CPU_SLEEP_0 &SYSTEM_SLEEP_0>;*/ + }; + CPU2:cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0x2>; + enable-method = "psci"; + clocks = <&scpi_dvfs 0>; + clock-names = "cpu-cluster.0"; + cpu-idle-states = <&SYSTEM_SLEEP_0>; + /*cpu-idle-states = <&CPU_SLEEP_0 &SYSTEM_SLEEP_0>;*/ + }; + + CPU3:cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0x3>; + enable-method = "psci"; + clocks = <&scpi_dvfs 0>; + clock-names = "cpu-cluster.0"; + cpu-idle-states = <&SYSTEM_SLEEP_0>; + /*cpu-idle-states = <&CPU_SLEEP_0 &SYSTEM_SLEEP_0>;*/ + }; + + + idle-states { + entry-method = "arm,psci"; +/* + * CPU_SLEEP_0: cpu-sleep-0 { + * compatible = "arm,idle-state"; + * arm,psci-suspend-param = <0x0010000>; + * local-timer-stop; + * entry-latency-us = <3000>; + * exit-latency-us = <3000>; + * min-residency-us = <8000>; + * }; + */ + SYSTEM_SLEEP_0: system-sleep-0 { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x0010000>; + local-timer-stop; + entry-latency-us = <0x3fffffff>; + exit-latency-us = <0x40000000>; + min-residency-us = <0xffffffff>; + }; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + }; + timer_bc { + compatible = "arm, meson-bc-timer"; + reg= <0xc1109990 0x4 0xc1109994 0x4>; + timer_name = "Meson TimerF"; + clockevent-rating=<300>; + clockevent-shift=<20>; + clockevent-features=<0x23>; + interrupts = <0 60 1>; + bit_enable=<16>; + bit_mode=<12>; + bit_resolution=<0>; + }; + arm_pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = <0 137 4>, + <0 138 4>, + <0 153 4>, + <0 154 4>; + }; + + gic: interrupt-controller@2c001000 { + compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0xc4301000 0 0x1000>, + <0xc4302000 0 0x0100>; + interrupts = ; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + meson_suspend:pm{ + compatible = "amlogic, pm"; + device_name = "aml_pm"; + reg = <0xc81000a8 0x4 + 0xc810023c 0x4>; + }; + + secmon { + compatible = "amlogic, secmon"; + memory-region = <&secmon_reserved>; + in_base_func = <0x82000020>; + out_base_func = <0x82000021>; + reserve_mem_size = <0x00300000>; + }; + + securitykey { + compatible = "aml, securitykey"; + storage_query = <0x82000060>; + storage_read = <0x82000061>; + storage_write = <0x82000062>; + storage_tell = <0x82000063>; + storage_verify = <0x82000064>; + storage_status = <0x82000065>; + storage_list = <0x82000067>; + storage_remove = <0x82000068>; + storage_in_func = <0x82000023>; + storage_out_func = <0x82000024>; + storage_block_func = <0x82000025>; + storage_size_func = <0x82000027>; + storage_set_enctype = <0x8200006A>; + storage_get_enctype = <0x8200006B>; + storage_version = <0x8200006C>; + }; + + cpu_iomap{ + compatible = "amlogic, iomap"; + #address-cells=<1>; + #size-cells=<1>; + ranges; + io_cbus_base{ + reg = <0xc1100000 0x100000>; + }; + io_apb_base{ + reg = <0xd0050000 0x50000>; + }; + io_aobus_base{ + reg = <0xc8100000 0x100000>; + }; + io_vapb_base{ + reg = <0xd0100000 0x100000>; + }; + io_hiu_base{ + reg = <0xc883c000 0x2000>; + }; + }; + + cpu_info{ + compatible = "amlogic, cpuinfo"; + cpuinfo_cmd = <0x82000044>; + status = "okay"; + }; + + watchdog { + compatible = "amlogic, meson-wdt"; + status = "disabled"; + default_timeout=<10>; + reset_watchdog_method=<1>; /* 0:sysfs,1:kernel */ + reset_watchdog_time=<2>; + shutdown_timeout=<10>; + firmware_timeout=<6>; + suspend_timeout=<6>; + reg = <0xc11098d0 0x10>; + clock-names = "xtal"; + clocks = <&xtal>; + }; + + jtag { + compatible = "amlogic, jtag"; + status = "okay"; + select = "apao"; /* disable/apao/apee */ + jtagao-gpios = <&gpio GPIOH_6 0 + &gpio GPIOH_7 0 + &gpio GPIOH_8 0 + &gpio GPIOH_9 0>; + jtagee-gpios = <&gpio CARD_0 0 + &gpio CARD_1 0 + &gpio CARD_2 0 + &gpio CARD_3 0>; + }; + + mailbox: mhu@c883c400 { + compatible = "amlogic, meson_mhu"; + reg = <0xc883c400 0x4c>, /* MHU registers */ + <0xc8013000 0x800>; /* Payload area */ + interrupts = <0 209 1>, /* low priority interrupt */ + <0 210 1>; /* high priority interrupt */ + #mbox-cells = <1>; + mbox-names = "cpu_to_scp_low", "cpu_to_scp_high"; + mboxes = <&mailbox 0 &mailbox 1>; + }; + + scpi_clocks { + compatible = "arm, scpi-clks"; + + scpi_dvfs: scpi_clocks@0 { + compatible = "arm, scpi-clk-indexed"; + #clock-cells = <1>; + clock-indices = <0>; + clock-output-names = "vcpu"; + }; + + }; + + xtal: xtal-clk { + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "xtal"; + #clock-cells = <0>; + }; + + vpu { + compatible = "amlogic, vpu-gxl"; + dev_name = "vpu"; + status = "okay"; + clocks = <&clkc CLKID_VAPB_MUX>, + <&clkc CLKID_VPU_INTR>, + <&clkc CLKID_GP0_PLL>, + <&clkc CLKID_VPU_P0_COMP>, + <&clkc CLKID_VPU_P1_COMP>, + <&clkc CLKID_VPU_MUX>; + clock-names = "vapb_clk", + "vpu_intr", + "gp_pll", + "vpu_clk0", + "vpu_clk1", + "vpu_clk"; + clk_level = <7>; + /* 0: 100.0M 1: 166.7M 2: 200.0M 3: 250.0M */ + /* 4: 333.3M 5: 400.0M 6: 500.0M 7: 666.7M */ + }; + + spicc:@c1108d80{ + compatible = "amlogic, spicc"; + status = "disabled"; + reg = <0xc1108d80 0x28>; + clocks = <&clkc CLKID_SPICC>; + clock-names = "spicc_clk"; + interrupts = <0 81 1>; + device_id = <0>; + }; + + uart_AO: serial@c81004c0 { + compatible = "amlogic, meson-uart"; + reg = <0xc81004c0 0x18>; + interrupts = <0 193 1>; + status = "okay"; + clocks = <&xtal>; + clock-names = "clk_uart"; + xtal_tick_en = <1>; + fifosize = < 64 >; + pinctrl-names = "default"; + /*pinctrl-0 = <&ao_uart_pins>;*/ + support-sysrq = <0>; /* 0 not support , 1 support */ + }; + + uart_A: serial@c11084c0 { + compatible = "amlogic, meson-uart"; + reg = <0xc11084c0 0x18>; + interrupts = <0 26 1>; + status = "okay"; + clocks = <&clkc CLKID_UART0>; + clock-names = "clk_uart"; + fifosize = < 128 >; + pinctrl-names = "default"; + pinctrl-0 = <&a_uart_pins>; + }; + + uart_B: serial@c11084dc { + compatible = "amlogic, meson-uart"; + reg = <0xc11084dc 0x18>; + interrupts = <0 75 1>; + status = "disabled"; + clocks = <&clkc CLKID_UART1>; + clock-names = "clk_uart"; + fifosize = < 64 >; + pinctrl-names = "default"; + pinctrl-0 = <&b_uart_pins>; + }; + + uart_C: serial@c1108700 { + compatible = "amlogic, meson-uart"; + reg = <0xc1108700 0x18>; + interrupts = <0 93 1>; + status = "disabled"; + clocks = <&clkc CLKID_UART2>; + clock-names = "clk_uart"; + fifosize = < 64 >; + pinctrl-names = "default"; + pinctrl-0 = <&c_uart_pins>; + }; + + uart_AO_B: serial@c81004e0 { + compatible = "amlogic, meson-uart"; + reg = <0xc81004e0 0x18>; + interrupts = <0 197 1>; + status = "disable"; + clocks = <&xtal>; + clock-names = "clk_uart"; + fifosize = < 64 >; + pinctrl-names = "default"; + pinctrl-0 = <&ao_b_uart_pins>; + }; + + pinctrl_aobus: pinctrl@14 { + compatible = "amlogic,meson-gxl-aobus-pinctrl"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + gpio_ao: bank@14 { + reg = <0xc8100014 0x8>, + <0xc810002c 0x4>, + <0xc8100024 0x8>; + reg-names = "mux", "pull", "gpio"; + gpio-controller; + #gpio-cells = <2>; + }; + }; + + pinctrl_periphs: pinctrl@4b0 { + compatible = "amlogic,meson-gxl-periphs-pinctrl"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + gpio: bank@4b0 { + reg = <0xc88344b0 0x28>, + <0xc88344e8 0x14>, + <0xc8834520 0x14>, + <0xc8834430 0x40>; + reg-names = "mux", "pull", + "pull-enable", "gpio"; + gpio-controller; + #gpio-cells = <2>; + }; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + cbus: cbus@c1100000 { + compatible = "simple-bus"; + reg = <0xc1100000 0x100000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xc1100000 0x100000>; + + gpio_intc: interrupt-controller@9880 { + compatible = "amlogic,meson-gpio-intc", + "amlogic,meson-gxl-gpio-intc"; + reg = <0x9880 0x10>; + interrupt-controller; + #interrupt-cells = <2>; + amlogic,channel-interrupts = + <64 65 66 67 68 69 70 71>; + status = "okay"; + }; + + meson_clk_msr{ + compatible = "amlogic, gxl_measure"; + reg = <0x875c 0x4 + 0x8764 0x4>; + }; + + /*i2c-A*/ + i2c0: i2c@8500 { + compatible = "amlogic,meson-gx-i2c"; + status = "disabled"; + reg = <0x8500 0x20>; + interrupts = , + ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clkc CLKID_I2C>; + clock-names = "clk_i2c"; + }; + + /*i2c-B*/ + i2c1: i2c@87c0 { + compatible = "amlogic,meson-gx-i2c"; + status = "disabled"; + reg = <0x87c0 0x20>; + interrupts = , + ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clkc CLKID_I2C>; + clock-names = "clk_i2c"; + }; + + /*i2c-C*/ + i2c2: i2c@87e0 { + compatible = "amlogic,meson-gx-i2c"; + status = "disabled"; + reg = <0x87e0 0x20>; + interrupts = , + ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clkc CLKID_I2C>; + clock-names = "clk_i2c"; + }; + + /*i2c-D*/ + i2c3: i2c@8d20 { + compatible = "amlogic,meson-gx-i2c"; + status = "disabled"; + reg = <0x8d20 0x20>; + interrupts = , + ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clkc CLKID_I2C>; + clock-names = "clk_i2c"; + }; + }; + + aobus: aobus@c8100000 { + compatible = "simple-bus"; + reg = <0xc8100000 0x100000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xc8100000 0x100000>; + + cpu_version{ + reg=<0x0220 0x4>; + }; + + i2c_AO: i2c@0500 { + compatible = "amlogic,meson-gx-i2c"; + status = "disabled"; + reg = <0x0500 0x20>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clkc CLKID_I2C>; + clock-names = "clk_i2c"; + }; + }; + + periphs: periphs@c8834000 { + compatible = "simple-bus"; + reg = <0xc8834000 0x2000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xc8834000 0x2000>; + }; + + hiubus: hiubus@c883c000 { + compatible = "simple-bus"; + reg = <0xc883c000 0x2000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xc883c000 0x2000>; + + clkc: clock-controller@0 { + compatible = "amlogic,gxl-clkc"; + #clock-cells = <1>; + reg = <0x0 0x3db>; + }; + }; + + apb: apb@d0000000 { + compatible = "simple-bus"; + reg = <0xd0000000 0x200000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xd0000000 0x200000>; + }; + }; /* end of soc */ + + vdac { + compatible = "amlogic, vdac-gxl"; + status = "okay"; + }; + + defendkey: defendkey { + compatible = "amlogic, defendkey"; + reg = <0xc8834500 0x4>; /*RNG_USR_DATA*/ + mem_size = <0x0 0x100000>; + status = "okay"; + }; +}; /* end of root */ + +&pinctrl_aobus { + remote_pins:remote_pin { + mux { + groups = "remote_input"; + function = "remote"; + }; + }; + + sd_to_ao_uart_clr_pins:sd_to_ao_uart_clr_pins { + mux { + groups = "GPIOAO_0", + "GPIOAO_1"; + function = "gpio_aobus"; + }; + }; + + sd_to_ao_uart_pins:sd_to_ao_uart_pins { + mux { + groups = "uart_tx_ao_a_0", + "uart_rx_ao_a_0"; + function = "uart_ao"; + bias-pull-up; + input-enable; + }; + }; + + ao_uart_pins:ao_uart { + mux { + groups = "uart_tx_ao_a_0", + "uart_rx_ao_a_0"; + function = "uart_ao"; + }; + }; + + ao_b_uart_pins:ao_b_uart { + mux { + groups = "uart_tx_ao_b_0", + "uart_rx_ao_b_0"; + function = "uart_ao_b"; + }; + }; + ao_i2c_master:ao_i2c{ + mux { + groups = "i2c_sda_ao", + "i2c_sck_ao"; + function = "i2c_ao"; + }; + }; + + hdmitx_aocec: hdmitx_aocec { + mux { + groups = "ao_cec"; + function = "ao_cec"; + }; + }; + + hdmitx_eecec: hdmitx_eecec { + mux { + groups = "ee_cec"; + function = "ee_cec"; + }; + }; +}; /* end of pinctrl_aobus*/ + +&pinctrl_periphs { + external_eth_pins:external_eth_pins { + mux { + groups = "eth_mdio", + "eth_mdc", + "eth_clk_rx_clk", + "eth_rx_dv", + "eth_rxd0", + "eth_rxd1", + "eth_rxd2", + "eth_rxd3", + "eth_rgmii_tx_clk", + "eth_tx_en", + "eth_txd0", + "eth_txd1", + "eth_txd2", + "eth_txd3"; + function = "eth"; + }; + }; + + jtag_apao_pins:jtag_apao_pin { + mux { + groups = "jtag_tdi_0", + "jtag_tdo_0", + "jtag_clk_0", + "jtag_tms_0"; + function = "jtag"; + }; + }; + + jtag_apee_pins:jtag_apee_pin { + mux { + groups ="jtag_tdi_1", + "jtag_tdo_1", + "jtag_clk_1", + "jtag_tms_1"; + function = "jtag"; + }; + }; + + a_uart_pins:a_uart { + mux { + groups = "uart_tx_a", + "uart_rx_a", + "uart_rts_a"; + function = "uart_a"; + }; + }; + + b_uart_pins:b_uart { + mux { + groups = "uart_tx_b", + "uart_rx_b", + "uart_cts_b", + "uart_rts_b"; + function = "uart_b"; + }; + }; + + c_uart_pins:c_uart { + mux { + groups = "uart_tx_c", + "uart_rx_c", + "uart_cts_c", + "uart_rts_c"; + function = "uart_c"; + }; + }; + + wifi_32k_pins:wifi_32k_pins { + mux { + groups ="pwm_e"; + function = "pwm_e"; + }; + }; + +/* + * sd_clk_cmd_pins:sd_clk_cmd_pins{ + * }; + * sd_all_pins:sd_all_pins { + * }; + * sd_1bit_uart_pins:sd_1bit_uart_pins{ + * }; + * sd_clk_cmd_uart_pins:sd_clk_cmd_uart_pins { + * }; + * sd_to_ao_jtag_pins:sd_to_ao_jtag_pins{ + * }; + */ + ao_to_sd_uart_clr_pins:ao_to_sd_uart_clr_pins { + mux { + groups = "sdcard_d2", + "sdcard_d3"; + function = "sdcard"; + input-enable; + bias-pull-up; + }; + }; + + sd_1bit_pins:sd_1bit_pins { + mux { + groups = "sdcard_d0", + "sdcard_cmd", + "sdcard_clk"; + function = "sdcard"; + input-enable; + bias-pull-up; + }; + }; + + ao_to_sd_uart_pins:ao_to_sd_uart_pins { + mux { + groups = "uart_tx_ao_a_card4", + "uart_rx_ao_a_card5"; + function = "uart_ao_a_card"; + bias-pull-up; + input-enable; + }; + }; + + emmc_clk_cmd_pins:emmc_clk_cmd_pins { + mux { + groups = "emmc_cmd", + "emmc_clk"; + function = "emmc"; + input-enable; + bias-pull-up; + }; + }; + + + emmc_conf_pull_up:emmc_conf_pull_up { + mux { + groups = "emmc_nand_d07", + "emmc_clk", + "emmc_cmd"; + function = "emmc"; + input-enable; + bias-pull-up; + }; + }; + + emmc_conf_pull_done:emmc_conf_pull_done { + mux { + groups = "emmc_ds"; + function = "emmc"; + input-enable; + bias-pull-down; + }; + }; + + sd_clk_cmd_pins:sd_clk_cmd_pins{ + mux { + groups = "sdcard_cmd", + "sdcard_clk"; + function = "sdcard"; + input-enable; + bias-pull-up; + }; + }; + + sd_all_pins:sd_all_pins{ + mux { + groups = "sdcard_d0", + "sdcard_d1", + "sdcard_d2", + "sdcard_d3", + "sdcard_cmd", + "sdcard_clk"; + function = "sdcard"; + input-enable; + bias-pull-up; + }; + }; + + sdio_clk_cmd_pins:sdio_clk_cmd_pins { + mux { + groups = "sdio_clk", + "sdio_cmd"; + function = "sdio"; + input-enable; + bias-pull-up; + }; + }; + + sdio_all_pins:sdio_all_pins { + mux { + groups = "sdio_d0", + "sdio_d1", + "sdio_d2", + "sdio_d3", + "sdio_clk", + "sdio_cmd"; + function = "sdio"; + input-enable; + bias-pull-up; + }; + }; + + nand_pulldown: nand_pulldown { + mux { + groups = "emmc_nand_d07", + "emmc_ds"; + function = "emmc"; + bias-pull-down; + }; + }; + + nand_pullup: nand_pullup { + mux { + groups = "emmc_clk", + "emmc_cmd"; + function = "emmc"; + bias-pull-up; + }; + }; + + all_nand_pins: all_nand_pins { + mux { + groups = "emmc_nand_d07", + "nand_ce0", + "nand_ce1", + "nand_rb0", + "nand_ale", + "nand_cle", + "nand_wen_clk", + "nand_ren_wr", + "nand_dqs"; + function = "nand"; + input-enable; + }; + }; + + nand_cs_pins: nand_cs { + mux { + groups = "nand_ce0", + "nand_ce1"; + function = "nand"; + }; + }; + + hdmitx_hpd: hdmitx_hpd { + mux { + groups = "hdmi_hpd"; + function = "hdmi_hpd"; + }; + }; + + hdmitx_ddc: hdmitx_ddc { + mux { + groups = "hdmi_sda", + "hdmi_scl"; + function = "hdmi_ddc"; + }; + }; + + a_i2c_master:a_i2c { + mux { + groups = "i2c_sda_a", + "i2c_scl_a"; + function = "i2c_a"; + }; + }; + + b_i2c_master:b_i2c { + mux { + groups = "i2c_sda_b", + "i2c_scl_b"; + function = "i2c_b"; + }; + }; + + /* c_i2c_master: dv28 dv29 */ + /* c_i2c_master_pin1: dv18 dv19 */ + c_i2c_master:c_i2c { + mux { + groups = "i2c_sda_c_dv28", + "i2c_scl_c_dv29"; + function = "i2c_c"; + }; + }; + c_i2c_master_pin1:c_i2c_pin1{ + mux { + groups = "i2c_sda_c_dv18", + "i2c_scl_c_dv19"; + function = "i2c_c"; + }; + }; + + d_i2c_master:d_i2c { + mux { + groups = "i2c_sda_d", + "i2c_scl_d"; + function = "i2c_d"; + }; + }; + + spicc_pulldown_z11z12z13: spicc_pulldown_z11z12z13 { + mux { + groups = "spi_sclk_0", + "spi_miso_0", + "spi_mosi_0"; + function = "spi"; + }; + }; + + spicc_pullup_z11z12z13: spicc_pullup_z11z12z13 { + mux { + groups = "spi_sclk_0", + "spi_miso_0", + "spi_mosi_0"; + function = "spi"; + }; + }; + + spicc_pulldown_x8x9x11: spicc_pulldown_x8x9x11 { + mux { + groups = "spi_sclk_1", + "spi_miso_1", + "spi_mosi_1"; + function = "spi"; + bias-pull-down; + }; + }; + + spicc_pullup_x8x9x11: spicc_pullup_x8x9x11 { + mux { + groups = "spi_sclk_1", + "spi_miso_1", + "spi_mosi_1"; + function = "spi"; + bias-pull-up; + }; + }; + + audio_i2s_pins:audio_i2s { + mux { + groups = "i2s_am_clk", + "i2s_ao_clk_out", + "i2s_lr_clk_out", + "i2sout_ch01"; + function = "i2s"; + }; + }; + + audio_spdif_pins:audio_spdif { + mux { + groups = "spdif_out"; + function = "spdif_out"; + }; + }; + + audio_spdif_in_pins:audio_spdif_in { + mux { + groups = "spdif_in_z14"; + function = "spdif_in"; + }; + }; + + audio_spdif_in_1_pins:audio_spdif_in_1 { + mux { + groups = "spdif_in_h4"; + function = "spdif_in"; + }; + }; + + audio_pcm_pins:audio_pcm { + mux { + groups = "pcm_out_a", + "pcm_in_a", + "pcm_fs_a", + "pcm_clk_a"; + function = "pcm_a"; + }; + }; + aml_dmic_pins:audio_dmic { + mux { + groups = "dmic_in_dv24", + "dmic_clk_dv25"; + function = "dmic"; + }; + }; + dvb_p_ts0_pins: dvb_p_ts0_pins { + tsin_a { + groups = "tsin_sop_a_dv9", + "tsin_d_valid_a_dv10", + "tsin_d0_a_dv0", + "tsin_d1_7_a_dv1_7", + "tsin_clk_a_dv8"; + function = "tsin_a"; + }; + }; + dvb_s_ts0_pins: dvb_s_ts0_pins { + tsin_a { + groups = "tsin_sop_a_dv9", + "tsin_d_valid_a_dv10", + "tsin_clk_a_dv8", + "tsin_d0_a_dv0"; + function = "tsin_a"; + }; + }; + +}; /* end of pinctrl_periphs */ + +&periphs { + rng { + compatible = "amlogic,meson-rng"; + reg = <0x0 0x4>; + }; +}; + +&cbus{ + reset: reset-controller@4404 { + compatible = "amlogic,reset"; + reg = <0x04404 0x20>; + #reset-cells = <1>; + }; +}; + +/{ + aml_dma { + compatible = "amlogic,aml_gxl_dma"; + reg = <0xc883e000 0x28>; + interrupts = <0 188 1>; + + aml_aes { + compatible = "amlogic,aes_dma"; + dev_name = "aml_aes_dma"; + status = "okay"; + }; + + aml_tdes { + compatible = "amlogic,des_dma,tdes_dma"; + dev_name = "aml_tdes_dma"; + status = "okay"; + }; + }; + + audio_data:audio_data { + compatible = "amlogic, audio_data"; + query_licence_cmd = <0x82000050>; + status = "disabled"; + }; + + saradc: saradc { + compatible = "amlogic,meson-gxl-saradc"; + status = "okay"; + #io-channel-cells = <1>; + clocks = <&xtal>, <&clkc CLKID_SARADC>, + <&clkc CLKID_SARADC_COMP>; + clock-names = "xtal", "clk81_gate", "saradc_clk"; + interrupts = ; + reg = <0xc1108680 0x38>; + }; + + efuse: efuse{ + compatible = "amlogic, efuse"; + read_cmd = <0x82000030>; + write_cmd = <0x82000031>; + get_max_cmd = <0x82000033>; + key = <&efusekey>; + clocks = <&clkc CLKID_EFUSE>; + clock-names = "efuse_clk"; + status = "disabled"; + }; + + efusekey:efusekey{ + keynum = <4>; + key0 = <&key_0>; + key1 = <&key_1>; + key2 = <&key_2>; + key3 = <&key_3>; + key_0:key_0{ + keyname = "mac"; + offset = <0>; + size = <6>; + }; + key_1:key_1{ + keyname = "mac_bt"; + offset = <6>; + size = <6>; + }; + key_2:key_2{ + keyname = "mac_wifi"; + offset = <12>; + size = <6>; + }; + key_3:key_3{ + keyname = "usid"; + offset = <18>; + size = <16>; + }; + }; + + remote:rc@c8100580 { + compatible = "amlogic, aml_remote"; + dev_name = "meson-remote"; + reg = <0xc8100580 0x00 0x44>, /*Multi-format IR controller*/ + <0xc8100480 0x00 0x20>; /*Legacy IR controller*/ + status = "okay"; + protocol = ; + interrupts = <0 196 1>; + pinctrl-names = "default"; + pinctrl-0 = <&remote_pins>; + map = <&custom_maps>; + max_frame_time = <200>; /*set software decoder max frame time*/ + }; + + custom_maps:custom_maps { + mapnum = <3>; + map0 = <&map_0>; + map1 = <&map_1>; + map2 = <&map_2>; + map_0: map_0{ + mapname = "amlogic-remote-1"; + customcode = <0xfb04>; + release_delay = <80>; + size = <50>; /*keymap size*/ + keymap = ; + }; + map_1: map_1{ + mapname = "amlogic-remote-2"; + customcode = <0xfe01>; + release_delay = <80>; + size = <53>; + keymap = ; + }; + map_2: map_2{ + mapname = "amlogic-remote-3"; + customcode = <0xbd02>; + release_delay = <80>; + size = <17>; + keymap = ; + }; + }; + aml_reboot{ + compatible = "aml, reboot"; + sys_reset = <0x84000009>; + sys_poweroff = <0x84000008>; + }; + + rtc{ + compatible = "amlogic, aml_vrtc"; + alarm_reg_addr = <0xc81000a8>; + timer_e_addr = <0xc1109988>; + init_date = "2017/01/01"; + status = "okay"; + }; + + pwm_ab: pwm@c1108550 { + compatible = "amlogic,gx-ee-pwm"; + reg = <0xc1108550 0x1c>; + #pwm-cells = <3>; + clocks = <&xtal>,<&xtal>,<&xtal>,<&xtal>; + clock-names = "clkin0","clkin1","clkin2","clkin3"; + status = "disabled"; + }; + pwm_cd: pwm@c1108640 { + compatible = "amlogic,gx-ee-pwm"; + reg = <0xc1108640 0x1c>; + #pwm-cells = <3>; + clocks = <&xtal>,<&xtal>,<&xtal>,<&xtal>; + clock-names = "clkin0","clkin1","clkin2","clkin3"; + status = "disabled"; + }; + pwm_ef: pwm@c11086c0 { + compatible = "amlogic,gx-ee-pwm"; + reg = <0xc11086c0 0x1c>; + #pwm-cells = <3>; + clocks = <&xtal>,<&xtal>,<&xtal>,<&xtal>; + clock-names = "clkin0","clkin1","clkin2","clkin3"; + status = "disabled"; + }; + pwm_aoab: pwm@c8100550 { + compatible = "amlogic,gx-ao-pwm"; + reg = <0xc8100550 0x1c>; + #pwm-cells = <3>; + clocks = <&xtal>,<&xtal>,<&xtal>,<&xtal>; + clock-names = "clkin0","clkin1","clkin2","clkin3"; + status = "disabled"; + }; +}; + +&gpu{ + /*gpu max freq is 750M*/ + tbl = <&clk125_cfg &clk285_cfg &clk400_cfg + &clk500_cfg &clk500_cfg &clk500_cfg &clk500_cfg>; +}; diff --git a/arch/arm/boot/dts/amlogic/mesongxm.dtsi b/arch/arm/boot/dts/amlogic/mesongxm.dtsi new file mode 100644 index 000000000000..91a1e260630b --- /dev/null +++ b/arch/arm/boot/dts/amlogic/mesongxm.dtsi @@ -0,0 +1,1479 @@ +/* + * arch/arm/boot/dts/amlogic/mesongxm.dtsi + * + * Copyright (C) 2017 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "mesongxm-gpu-t82x.dtsi" +/ { + cpus:cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu-map { + cluster0:cluster0 { + core0 { + cpu = <&CPU0>; + }; + core1 { + cpu = <&CPU1>; + }; + core2 { + cpu = <&CPU2>; + }; + core3 { + cpu = <&CPU3>; + }; + }; + cluster1:cluster1 { + core0 { + cpu = <&CPU4>; + }; + core1 { + cpu = <&CPU5>; + }; + core2 { + cpu = <&CPU6>; + }; + core3 { + cpu = <&CPU7>; + }; + }; + }; + CPU0:cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0x0>; + enable-method = "psci"; + clocks = <&scpi_dvfs 0>; + clock-names = "cpu-cluster.0"; + cpu-idle-states = <&SYSTEM_SLEEP_0>; +/* + * cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0 + * &SYSTEM_SLEEP_0>; + */ + }; + + CPU1:cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0x1>; + enable-method = "psci"; + clocks = <&scpi_dvfs 0>; + clock-names = "cpu-cluster.0"; + cpu-idle-states = <&SYSTEM_SLEEP_0>; +/* + * cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0 + * &SYSTEM_SLEEP_0>; + */ + }; + + CPU2:cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0x2>; + enable-method = "psci"; + clocks = <&scpi_dvfs 0>; + clock-names = "cpu-cluster.0"; + cpu-idle-states = <&SYSTEM_SLEEP_0>; +/* + * cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0 + * &SYSTEM_SLEEP_0>; + */ + }; + + CPU3:cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0x3>; + enable-method = "psci"; + clocks = <&scpi_dvfs 0>; + clock-names = "cpu-cluster.0"; + cpu-idle-states = <&SYSTEM_SLEEP_0>; +/* + * cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0 + * &SYSTEM_SLEEP_0>; + */ + }; + + CPU4:cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0x100>; + enable-method = "psci"; + clocks = <&scpi_dvfs 1>; + clock-names = "cpu-cluster.1"; + cpu-idle-states = <&SYSTEM_SLEEP_0>; +/* + * cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0 + * &SYSTEM_SLEEP_0>; + */ + }; + + CPU5:cpu@101 { + device_type = "cpu"; + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0x101>; + enable-method = "psci"; + clocks = <&scpi_dvfs 1>; + clock-names = "cpu-cluster.1"; + cpu-idle-states = <&SYSTEM_SLEEP_0>; +/* + * cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0 + * &SYSTEM_SLEEP_0>; + */ + }; + CPU6:cpu@102 { + device_type = "cpu"; + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0x102>; + enable-method = "psci"; + clocks = <&scpi_dvfs 1>; + clock-names = "cpu-cluster.1"; + cpu-idle-states = <&SYSTEM_SLEEP_0>; +/* + * cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0 + * &SYSTEM_SLEEP_0>; + */ + }; + + CPU7:cpu@103 { + device_type = "cpu"; + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0x103>; + enable-method = "psci"; + clocks = <&scpi_dvfs 1>; + clock-names = "cpu-cluster.1"; + cpu-idle-states = <&SYSTEM_SLEEP_0>; +/* + * cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0 + * &SYSTEM_SLEEP_0>; + */ + }; + + idle-states { + entry-method = "arm,psci"; +/* + CPU_SLEEP_0: cpu-sleep-0 { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x0010000>; + local-timer-stop; + entry-latency-us = <3000>; + exit-latency-us = <3000>; + min-residency-us = <8000>; + }; + + CLUSTER_SLEEP_0: cluster-sleep-0 { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x1010000>; + local-timer-stop; + entry-latency-us = <3000>; + exit-latency-us = <3000>; + min-residency-us = <15000>; + }; +*/ + SYSTEM_SLEEP_0: system-sleep-0 { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x1010000>; + local-timer-stop; + entry-latency-us = <0x3fffffff>; + exit-latency-us = <0x40000000>; + min-residency-us = <0xffffffff>; + }; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + }; + timer_bc { + compatible = "arm, meson-bc-timer"; + reg= <0xc1109990 0x4 0xc1109994 0x4>; + timer_name = "Meson TimerF"; + clockevent-rating=<300>; + clockevent-shift=<20>; + clockevent-features=<0x23>; + interrupts = <0 60 1>; + bit_enable=<16>; + bit_mode=<12>; + bit_resolution=<0>; + }; + arm_pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = <0 137 4>, + <0 138 4>, + <0 153 4>, + <0 154 4>; + }; + + gic: interrupt-controller@2c001000 { + compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0xc4301000 0x1000>, + <0xc4302000 0x0100>; + interrupts = ; + }; + + watchdog { + compatible = "amlogic, meson-wdt"; + status = "okay"; + default_timeout=<10>; + reset_watchdog_method=<1>; /* 0:sysfs,1:kernel */ + reset_watchdog_time=<2>; + shutdown_timeout=<10>; + firmware_timeout=<6>; + suspend_timeout=<6>; + reg = <0xc11098d0 0x10>; + clock-names = "xtal"; + clocks = <&xtal>; + }; + + ram-dump { + compatible = "amlogic, ram_dump"; + status = "okay"; + }; + + jtag { + compatible = "amlogic, jtag"; + status = "disabled"; + pinctrl-names = "jtag_apao_pins", "jtag_apee_pins"; + pinctrl-0 = <&jtag_apao_pins>; + pinctrl-1 = <&jtag_apee_pins>; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + meson_suspend:pm{ + compatible = "amlogic, pm"; + device_name = "aml_pm"; + reg = <0xc81000a8 0x4>, + <0xc810023c 0x4>; + }; + + secmon { + compatible = "amlogic, secmon"; + memory-region = <&secmon_reserved>; + in_base_func = <0x82000020>; + out_base_func = <0x82000021>; + reserve_mem_size = <0x00300000>; + }; + + vcodec_dec { + compatible = "amlogic, vcodec-dec"; + dev_name = "aml-vcodec-dec"; + status = "okay"; + }; + + securitykey { + compatible = "aml, securitykey"; + storage_query = <0x82000060>; + storage_read = <0x82000061>; + storage_write = <0x82000062>; + storage_tell = <0x82000063>; + storage_verify = <0x82000064>; + storage_status = <0x82000065>; + storage_list = <0x82000067>; + storage_remove = <0x82000068>; + storage_in_func = <0x82000023>; + storage_out_func = <0x82000024>; + storage_block_func = <0x82000025>; + storage_size_func = <0x82000027>; + storage_set_enctype = <0x8200006A>; + storage_get_enctype = <0x8200006B>; + storage_version = <0x8200006C>; + }; + + cpu_iomap{ + compatible = "amlogic, iomap"; + #address-cells=<1>; + #size-cells=<1>; + ranges; + io_cbus_base{ + reg = <0xc1100000 0x100000>; + }; + io_apb_base{ + reg = <0xd0050000 0x50000>; + }; + io_aobus_base{ + reg = <0xc8100000 0x100000>; + }; + io_vapb_base{ + reg = <0xd0100000 0x100000>; + }; + io_hiu_base{ + reg = <0xc883c000 0x2000>; + }; + }; + + cpu_info{ + compatible = "amlogic, cpuinfo"; + cpuinfo_cmd = <0x82000044>; + status = "okay"; + }; + + mailbox: mhu@c883c400 { + compatible = "amlogic, meson_mhu"; + reg = <0xc883c400 0x4c>, /* MHU registers */ + <0xc8013000 0x800>; /* Payload area */ + interrupts = <0 209 1>, /* low priority interrupt */ + <0 210 1>; /* high priority interrupt */ + #mbox-cells = <1>; + mbox-names = "cpu_to_scp_low", "cpu_to_scp_high"; + mboxes = <&mailbox 0 &mailbox 1>; + }; + + scpi_clocks { + compatible = "arm, scpi-clks"; + + scpi_dvfs: scpi_clocks@0 { + compatible = "arm, scpi-clk-indexed"; + #clock-cells = <1>; + clock-indices = <0 1>; + clock-output-names = "vbig", "vlittle"; + }; + + }; + xtal: xtal-clk { + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "xtal"; + #clock-cells = <0>; + }; + + vpu { + compatible = "amlogic, vpu-gxm"; + dev_name = "vpu"; + status = "okay"; + clocks = <&clkc CLKID_VAPB_MUX>, + <&clkc CLKID_VPU_INTR>, + <&clkc CLKID_GP0_PLL>, + <&clkc CLKID_VPU_P0_COMP>, + <&clkc CLKID_VPU_P1_COMP>, + <&clkc CLKID_VPU_MUX>; + clock-names = "vapb_clk", + "vpu_intr_gate", + "gp_pll", + "vpu_clk0", + "vpu_clk1", + "vpu_clk"; + clk_level = <7>; + /* 0: 100.0M 1: 166.7M 2: 200.0M 3: 250.0M */ + /* 4: 333.3M 5: 400.0M 6: 500.0M 7: 666.7M */ + }; + + spicc:@c1108d80{ + compatible = "amlogic, spicc"; + status = "disabled"; + reg = <0xc1108d80 0x28>; + clocks = <&clkc CLKID_SPICC>; + clock-names = "spicc_clk"; + interrupts = <0 81 1>; + device_id = <0>; + }; + + uart_AO: serial@c81004c0 { + compatible = "amlogic, meson-uart"; + reg = <0xc81004c0 0x18>; + interrupts = <0 193 1>; + status = "okay"; + clocks = <&xtal>; + clock-names = "clk_uart"; + xtal_tick_en = <1>; + fifosize = < 64 >; + pinctrl-names = "default"; + /*pinctrl-0 = <&ao_uart_pins>;*/ + support-sysrq = <0>; /* 0 not support , 1 support */ + }; + + uart_A: serial@c11084c0 { + compatible = "amlogic, meson-uart"; + reg = <0xc11084c0 0x18>; + interrupts = <0 26 1>; + status = "okay"; + clocks = <&clkc CLKID_UART0>; + clock-names = "clk_uart"; + fifosize = < 128 >; + pinctrl-names = "default"; + pinctrl-0 = <&a_uart_pins>; + }; + + uart_B: serial@c11084dc { + compatible = "amlogic, meson-uart"; + reg = <0xc11084dc 0x18>; + interrupts = <0 75 1>; + status = "okay"; + clocks = <&clkc CLKID_UART1>; + clock-names = "clk_uart"; + fifosize = < 64 >; + pinctrl-names = "default"; + pinctrl-0 = <&b_uart_pins>; + }; + + uart_C: serial@c1108700 { + compatible = "amlogic, meson-uart"; + reg = <0xc1108700 0x18>; + interrupts = <0 93 1>; + status = "disabled"; + clocks = <&clkc CLKID_UART2>; + clock-names = "clk_uart"; + fifosize = < 64 >; + pinctrl-names = "default"; + pinctrl-0 = <&c_uart_pins>; + }; + + uart_AO_B: serial@c81004e0 { + compatible = "amlogic, meson-uart"; + reg = <0xc81004e0 0x18>; + interrupts = <0 197 1>; + status = "disable"; + clocks = <&xtal>; + clock-names = "clk_uart"; + fifosize = < 64 >; + pinctrl-names = "default"; + pinctrl-0 = <&ao_b_uart_pins>; + }; + + pinctrl_aobus: pinctrl@14 { + compatible = "amlogic,meson-gxl-aobus-pinctrl"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + gpio_ao: bank@14 { + reg = <0xc8100014 0x8>, + <0xc810002c 0x4>, + <0xc8100024 0x8>; + reg-names = "mux", "pull", "gpio"; + gpio-controller; + #gpio-cells = <2>; + }; + }; + + pinctrl_periphs: pinctrl@4b0 { + compatible = "amlogic,meson-gxl-periphs-pinctrl"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + gpio: bank@4b0 { + reg = <0xc88344b0 0x28>, + <0xc88344e8 0x14>, + <0xc8834520 0x14>, + <0xc8834430 0x40>; + reg-names = "mux", "pull", + "pull-enable", "gpio"; + gpio-controller; + #gpio-cells = <2>; + }; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + cbus: cbus@c1100000 { + compatible = "simple-bus"; + reg = <0xc1100000 0x100000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xc1100000 0x100000>; + + gpio_intc: interrupt-controller@9880 { + compatible = "amlogic,meson-gpio-intc", + "amlogic,meson-gxl-gpio-intc"; + reg = <0x9880 0x10>; + interrupt-controller; + #interrupt-cells = <2>; + amlogic,channel-interrupts = + <64 65 66 67 68 69 70 71>; + status = "okay"; + }; + + meson_clk_msr{ + compatible = "amlogic, gxl_measure"; + reg = <0x875c 0x4 + 0x8764 0x4>; + }; + + /*i2c-A*/ + i2c0: i2c@8500 { + compatible = "amlogic,meson-gx-i2c"; + status = "disabled"; + reg = <0x8500 0x20>; + interrupts = , + ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clkc CLKID_I2C>; + clock-names = "clk_i2c"; + }; + + /*i2c-B*/ + i2c1: i2c@87c0 { + compatible = "amlogic,meson-gx-i2c"; + status = "disabled"; + reg = <0x87c0 0x20>; + interrupts = , + ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clkc CLKID_I2C>; + clock-names = "clk_i2c"; + }; + + /*i2c-C*/ + i2c2: i2c@87e0 { + compatible = "amlogic,meson-gx-i2c"; + status = "disabled"; + reg = <0x87e0 0x20>; + interrupts = , + ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clkc CLKID_I2C>; + clock-names = "clk_i2c"; + }; + + /*i2c-D*/ + i2c3: i2c@8d20 { + compatible = "amlogic,meson-gx-i2c"; + status = "disabled"; + reg = <0x8d20 0x20>; + interrupts = , + ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clkc CLKID_I2C>; + clock-names = "clk_i2c"; + }; + }; + + aobus: aobus@c8100000 { + compatible = "simple-bus"; + reg = <0xc8100000 0x100000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xc8100000 0x100000>; + + cpu_version{ + reg=<0x0220 0x4>; + }; + + i2c_AO: i2c@0500 { + compatible = "amlogic,meson-gx-i2c"; + status = "disabled"; + reg = <0x0500 0x20>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clkc CLKID_I2C>; + clock-names = "clk_i2c"; + }; + }; + + periphs: periphs@c8834000 { + compatible = "simple-bus"; + reg = <0xc8834000 0x2000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xc8834000 0x2000>; + }; + + hiubus: hiubus@c883c000 { + compatible = "simple-bus"; + reg = <0xc883c000 0x2000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xc883c000 0x2000>; + + clkc: clock-controller@0 { + compatible = "amlogic,gxl-clkc"; + #clock-cells = <1>; + reg = <0x0 0x3db>; + }; + }; + + apb: apb@d0000000 { + compatible = "simple-bus"; + reg = <0xd0000000 0x200000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xd0000000 0x200000>; + }; + }; /* end of soc */ + + cpu_ver_name { + compatible = "amlogic, cpu-major-id-gxm"; + }; + + vdac { + compatible = "amlogic, vdac-gxm"; + status = "okay"; + }; +}; /* end of root */ + +&pinctrl_aobus { + remote_pins:remote_pin { + mux { + groups = "remote_input"; + function = "remote"; + }; + }; + + sd_to_ao_uart_clr_pins:sd_to_ao_uart_clr_pins { + mux { + groups = "GPIOAO_0", + "GPIOAO_1"; + function = "gpio_aobus"; + }; + }; + + sd_to_ao_uart_pins:sd_to_ao_uart_pins { + mux { + groups = "uart_tx_ao_a_0", + "uart_rx_ao_a_0"; + function = "uart_ao"; + bias-pull-up; + input-enable; + }; + }; + + ao_uart_pins:ao_uart { + mux { + groups = "uart_tx_ao_a_0", + "uart_rx_ao_a_0"; + function = "uart_ao"; + }; + }; + + ao_b_uart_pins:ao_b_uart { + mux { + groups = "uart_tx_ao_b_0", + "uart_rx_ao_b_0"; + function = "uart_ao_b"; + }; + }; + ao_i2c_master:ao_i2c{ + mux { + groups = "i2c_sda_ao", + "i2c_sck_ao"; + function = "i2c_ao"; + }; + }; + + hdmitx_aocec: hdmitx_aocec { + mux { + groups = "ao_cec"; + function = "ao_cec"; + }; + }; + + hdmitx_eecec: hdmitx_eecec { + mux { + groups = "ee_cec"; + function = "ee_cec"; + }; + }; +}; /* end of pinctrl_aobus*/ + +&pinctrl_periphs { + external_eth_pins:external_eth_pins { + mux { + groups = "eth_mdio", + "eth_mdc", + "eth_clk_rx_clk", + "eth_rx_dv", + "eth_rxd0", + "eth_rxd1", + "eth_rxd2", + "eth_rxd3", + "eth_rgmii_tx_clk", + "eth_tx_en", + "eth_txd0", + "eth_txd1", + "eth_txd2", + "eth_txd3"; + function = "eth"; + }; + }; + + jtag_apao_pins:jtag_apao_pin { + mux { + groups = "jtag_tdi_0", + "jtag_tdo_0", + "jtag_clk_0", + "jtag_tms_0"; + function = "jtag"; + }; + }; + + jtag_apee_pins:jtag_apee_pin { + mux { + groups ="jtag_tdi_1", + "jtag_tdo_1", + "jtag_clk_1", + "jtag_tms_1"; + function = "jtag"; + }; + }; + + a_uart_pins:a_uart { + mux { + groups = "uart_tx_a", + "uart_rx_a", + "uart_cts_a", + "uart_rts_a"; + function = "uart_a"; + }; + }; + + b_uart_pins:b_uart { + mux { + groups = "uart_tx_b", + "uart_rx_b", + "uart_cts_b", + "uart_rts_b"; + function = "uart_b"; + }; + }; + + c_uart_pins:c_uart { + mux { + groups = "uart_tx_c", + "uart_rx_c", + "uart_cts_c", + "uart_rts_c"; + function = "uart_c"; + }; + }; + + wifi_32k_pins:wifi_32k_pins { + mux { + groups ="pwm_e"; + function = "pwm_e"; + }; + }; + +/* +* sd_clk_cmd_pins:sd_clk_cmd_pins{ +* }; +* sd_all_pins:sd_all_pins { +* }; +* sd_1bit_uart_pins:sd_1bit_uart_pins{ +* }; +* sd_clk_cmd_uart_pins:sd_clk_cmd_uart_pins { +* }; +* sd_to_ao_jtag_pins:sd_to_ao_jtag_pins{ +* }; +*/ + ao_to_sd_uart_clr_pins:ao_to_sd_uart_clr_pins { + mux { + groups = "sdcard_d2", + "sdcard_d3"; + function = "sdcard"; + input-enable; + bias-pull-up; + }; + }; + + sd_1bit_pins:sd_1bit_pins { + mux { + groups = "sdcard_d0", + "sdcard_cmd", + "sdcard_clk"; + function = "sdcard"; + input-enable; + bias-pull-up; + }; + }; + + ao_to_sd_uart_pins:ao_to_sd_uart_pins { + mux { + groups = "uart_tx_ao_a_card4", + "uart_rx_ao_a_card5"; + function = "uart_ao_a_card"; + bias-pull-up; + input-enable; + }; + }; + + emmc_clk_cmd_pins:emmc_clk_cmd_pins { + mux { + groups = "emmc_cmd", + "emmc_clk"; + function = "emmc"; + input-enable; + bias-pull-up; + }; + }; + + + emmc_conf_pull_up:emmc_conf_pull_up { + mux { + groups = "emmc_nand_d07", + "emmc_clk", + "emmc_cmd"; + function = "emmc"; + input-enable; + bias-pull-up; + }; + }; + + emmc_conf_pull_done:emmc_conf_pull_done { + mux { + groups = "emmc_ds"; + function = "emmc"; + input-enable; + bias-pull-down; + }; + }; + + sd_clk_cmd_pins:sd_clk_cmd_pins{ + mux { + groups = "sdcard_cmd", + "sdcard_clk"; + function = "sdcard"; + input-enable; + bias-pull-up; + }; + }; + + sd_all_pins:sd_all_pins{ + mux { + groups = "sdcard_d0", + "sdcard_d1", + "sdcard_d2", + "sdcard_d3", + "sdcard_cmd", + "sdcard_clk"; + function = "sdcard"; + input-enable; + bias-pull-up; + }; + }; + + sdio_clk_cmd_pins:sdio_clk_cmd_pins { + mux { + groups = "sdio_clk", + "sdio_cmd"; + function = "sdio"; + input-enable; + bias-pull-up; + }; + }; + + sdio_all_pins:sdio_all_pins { + mux { + groups = "sdio_d0", + "sdio_d1", + "sdio_d2", + "sdio_d3", + "sdio_clk", + "sdio_cmd"; + function = "sdio"; + input-enable; + bias-pull-up; + }; + }; + + nand_pulldown: nand_pulldown { + mux { + groups = "emmc_nand_d07", + "emmc_ds"; + function = "emmc"; + bias-pull-down; + }; + }; + + nand_pullup: nand_pullup { + mux { + groups = "emmc_clk", + "emmc_cmd"; + function = "emmc"; + bias-pull-up; + }; + }; + + all_nand_pins: all_nand_pins { + mux { + groups = "emmc_nand_d07", + "nand_ce0", + "nand_ce1", + "nand_rb0", + "nand_ale", + "nand_cle", + "nand_wen_clk", + "nand_ren_wr", + "nand_dqs"; + function = "nand"; + input-enable; + }; + }; + + nand_cs_pins: nand_cs { + mux { + groups = "nand_ce0", + "nand_ce1"; + function = "nand"; + }; + }; + + hdmitx_hpd: hdmitx_hpd { + mux { + groups = "hdmi_hpd"; + function = "hdmi_hpd"; + }; + }; + + hdmitx_ddc: hdmitx_ddc { + mux { + groups = "hdmi_sda", + "hdmi_scl"; + function = "hdmi_ddc"; + }; + }; + + a_i2c_master:a_i2c { + mux { + groups = "i2c_sda_a", + "i2c_scl_a"; + function = "i2c_a"; + }; + }; + + b_i2c_master:b_i2c { + mux { + groups = "i2c_sda_b", + "i2c_scl_b"; + function = "i2c_b"; + }; + }; + + /* c_i2c_master: dv28 dv29 */ + /* c_i2c_master_pin1: dv18 dv19 */ + c_i2c_master:c_i2c { + mux { + groups = "i2c_sda_c_dv28", + "i2c_scl_c_dv29"; + function = "i2c_c"; + }; + }; + c_i2c_master_pin1:c_i2c_pin1{ + mux { + groups = "i2c_sda_c_dv18", + "i2c_scl_c_dv19"; + function = "i2c_c"; + }; + }; + + d_i2c_master:d_i2c { + mux { + groups = "i2c_sda_d", + "i2c_scl_d"; + function = "i2c_d"; + }; + }; + + spicc_pulldown_z11z12z13: spicc_pulldown_z11z12z13 { + mux { + groups = "spi_sclk_0", + "spi_miso_0", + "spi_mosi_0"; + function = "spi"; + }; + }; + + spicc_pullup_z11z12z13: spicc_pullup_z11z12z13 { + mux { + groups = "spi_sclk_0", + "spi_miso_0", + "spi_mosi_0"; + function = "spi"; + }; + }; + + spicc_pulldown_x8x9x11: spicc_pulldown_x8x9x11 { + mux { + groups = "spi_sclk_1", + "spi_miso_1", + "spi_mosi_1"; + function = "spi"; + bias-pull-down; + }; + }; + + spicc_pullup_x8x9x11: spicc_pullup_x8x9x11 { + mux { + groups = "spi_sclk_1", + "spi_miso_1", + "spi_mosi_1"; + function = "spi"; + bias-pull-up; + }; + }; + + audio_i2s_pins:audio_i2s { + mux { + groups = "i2s_am_clk", + "i2s_ao_clk_out", + "i2s_lr_clk_out", + "i2sout_ch01"; + function = "i2s"; + }; + }; + + audio_spdif_pins:audio_spdif { + mux { + groups = "spdif_out"; + function = "spdif_out"; + }; + }; + + audio_spdif_in_pins:audio_spdif_in { + mux { + groups = "spdif_in_z14"; + function = "spdif_in"; + }; + }; + + audio_spdif_in_1_pins:audio_spdif_in_1 { + mux { + groups = "spdif_in_h4"; + function = "spdif_in"; + }; + }; + + audio_pcm_pins:audio_pcm { + mux { + groups = "pcm_out_a", + "pcm_in_a", + "pcm_fs_a", + "pcm_clk_a"; + function = "pcm_a"; + }; + }; + aml_dmic_pins:audio_dmic { + mux { + groups = "dmic_in_dv24", + "dmic_clk_dv25"; + function = "dmic"; + }; + }; + + lcd_ttl_rgb_6bit_on_pins:lcd_ttl_rgb_6bit_on{ + mux { + groups = "lcd_r2_7", + "lcd_g2_7", + "lcd_b2_7"; + function = "lcd_ttl"; + }; + }; + lcd_ttl_rgb_6bit_off_pins:lcd_ttl_rgb_6bit_off{ + mux { + groups = "GPIODV_2","GPIODV_3","GPIODV_4", + "GPIODV_5","GPIODV_6","GPIODV_7", + "GPIODV_10","GPIODV_11","GPIODV_12", + "GPIODV_13","GPIODV_14","GPIODV_15", + "GPIODV_18","GPIODV_19","GPIODV_20", + "GPIODV_21","GPIODV_22","GPIODV_23"; + function = "gpio_periphs"; + input-enable; + }; + }; + + lcd_ttl_rgb_8bit_on_pins:lcd_ttl_rgb_8bit_on{ + mux { + groups = "lcd_r0_1", "lcd_r2_7", + "lcd_g0_1", "lcd_g2_7", + "lcd_b0_1", "lcd_b2_7"; + function = "lcd_ttl"; + }; + }; + lcd_ttl_rgb_8bit_off_pins:lcd_ttl_rgb_8bit_off{ + mux { + groups = "GPIODV_0","GPIODV_1","GPIODV_2","GPIODV_3", + "GPIODV_4","GPIODV_5","GPIODV_6","GPIODV_7", + "GPIODV_8","GPIODV_9","GPIODV_10","GPIODV_11", + "GPIODV_12","GPIODV_13","GPIODV_14","GPIODV_15", + "GPIODV_16","GPIODV_17","GPIODV_18","GPIODV_19", + "GPIODV_20","GPIODV_21","GPIODV_22","GPIODV_23"; + function = "gpio_periphs"; + input-enable; + }; + }; + /* DE + clk */ + lcd_ttl_de_on_pins:lcd_ttl_de_on_pin{ + mux { + groups = "tcon_cph", /* clk */ + "tcon_oeh"; /* DE */ + function = "lcd_ttl"; + }; + }; + /* hvsync + clk */ + lcd_ttl_hvsync_on_pins:lcd_ttl_hvsync_on_pin{ + mux { + groups = "tcon_cph", /* clk */ + "tcon_stv1", /* vs */ + "tcon_sth1"; /* hs */ + function = "lcd_ttl"; + }; + }; + /* DE + hvsync + clk */ + lcd_ttl_de_hvsync_on_pins:lcd_ttl_de_hvsync_on_pin{ + mux { + groups = "tcon_cph", /* clk */ + "tcon_oeh", /* DE */ + "tcon_stv1", /* vs */ + "tcon_sth1"; /* hs */ + function = "lcd_ttl"; + }; + }; + lcd_ttl_de_hvsync_off_pins:lcd_ttl_de_hvsync_off_pin{ + mux { + groups = "GPIODV_26", /* clk */ + "GPIODV_27", /* DE */ + "GPIODV_24", /* vs */ + "GPIODV_25"; /* hs */ + function = "gpio_periphs"; + input-enable; + }; + }; +}; /* end of pinctrl_periphs */ + +&periphs { + rng { + compatible = "amlogic,meson-rng"; + reg = <0x0 0x4>; + quality = /bits/ 16 <1000>; + }; +}; + +&cbus{ + reset: reset-controller@4404 { + compatible = "amlogic,reset"; + reg = <0x04404 0x20>; + #reset-cells = <1>; + }; +}; + +/{ + aml_dma { + compatible = "amlogic,aml_gxl_dma"; + reg = <0xc883e000 0x28>; + interrupts = <0 188 1>; + + aml_aes { + compatible = "amlogic,aes_dma"; + dev_name = "aml_aes_dma"; + status = "okay"; + }; + + aml_tdes { + compatible = "amlogic,des_dma,tdes_dma"; + dev_name = "aml_tdes_dma"; + status = "okay"; + }; + }; + + audio_data:audio_data { + compatible = "amlogic, audio_data"; + query_licence_cmd = <0x82000050>; + status = "disabled"; + }; + + saradc: saradc { + compatible = "amlogic,meson-gxl-saradc"; + status = "okay"; + #io-channel-cells = <1>; + clocks = <&xtal>, <&clkc CLKID_SARADC>, + <&clkc CLKID_SARADC_COMP>; + clock-names = "xtal", "clk81_gate", "saradc_clk"; + interrupts = ; + reg = <0xc1108680 0x38>; + }; + + efuse: efuse{ + compatible = "amlogic, efuse"; + read_cmd = <0x82000030>; + write_cmd = <0x82000031>; + get_max_cmd = <0x82000033>; + key = <&efusekey>; + clocks = <&clkc CLKID_EFUSE>; + clock-names = "efuse_clk"; + status = "disabled"; + }; + + efusekey:efusekey{ + keynum = <4>; + key0 = <&key_0>; + key1 = <&key_1>; + key2 = <&key_2>; + key3 = <&key_3>; + key_0:key_0{ + keyname = "mac"; + offset = <0>; + size = <6>; + }; + key_1:key_1{ + keyname = "mac_bt"; + offset = <6>; + size = <6>; + }; + key_2:key_2{ + keyname = "mac_wifi"; + offset = <12>; + size = <6>; + }; + key_3:key_3{ + keyname = "usid"; + offset = <18>; + size = <16>; + }; + }; + + remote:rc@c8100580 { + compatible = "amlogic, aml_remote"; + dev_name = "meson-remote"; + reg = <0xc8100580 0x44>, /*Multi-format IR controller*/ + <0xc8100480 0x20>; /*Legacy IR controller*/ + status = "okay"; + protocol = ; + interrupts = <0 196 1>; + pinctrl-names = "default"; + pinctrl-0 = <&remote_pins>; + map = <&custom_maps>; + max_frame_time = <200>; /*set software decoder max frame time*/ + }; + + custom_maps:custom_maps { + mapnum = <3>; + map0 = <&map_0>; + map1 = <&map_1>; + map2 = <&map_2>; + map_0: map_0{ + mapname = "amlogic-remote-1"; + customcode = <0xfb04>; + release_delay = <80>; + size = <44>; /*keymap size*/ + keymap = ; + }; + map_1: map_1{ + mapname = "amlogic-remote-2"; + customcode = <0xfe01>; + release_delay = <80>; + size = <53>; + keymap = ; + }; + map_2: map_2{ + mapname = "amlogic-remote-3"; + customcode = <0xbd02>; + release_delay = <80>; + size = <17>; + keymap = ; + }; + }; + aml_reboot{ + compatible = "aml, reboot"; + sys_reset = <0x84000009>; + sys_poweroff = <0x84000008>; + }; + + rtc{ + compatible = "amlogic, aml_vrtc"; + alarm_reg_addr = <0xc81000a8>; + timer_e_addr = <0xc1109988>; + init_date = "2017/01/01"; + status = "okay"; + }; + + pwm_ab: pwm@c1108550 { + compatible = "amlogic,gx-ee-pwm"; + reg = <0xc1108550 0x1c>; + #pwm-cells = <3>; + clocks = <&xtal>,<&xtal>,<&xtal>,<&xtal>; + clock-names = "clkin0","clkin1","clkin2","clkin3"; + status = "disabled"; + }; + pwm_cd: pwm@c1108640 { + compatible = "amlogic,gx-ee-pwm"; + reg = <0xc1108640 0x1c>; + #pwm-cells = <3>; + clocks = <&xtal>,<&xtal>,<&xtal>,<&xtal>; + clock-names = "clkin0","clkin1","clkin2","clkin3"; + status = "disabled"; + }; + pwm_ef: pwm@c11086c0 { + compatible = "amlogic,gx-ee-pwm"; + reg = <0xc11086c0 0x1c>; + #pwm-cells = <3>; + clocks = <&xtal>,<&xtal>,<&xtal>,<&xtal>; + clock-names = "clkin0","clkin1","clkin2","clkin3"; + status = "disabled"; + }; + pwm_aoab: pwm@c8100550 { + compatible = "amlogic,gx-ao-pwm"; + reg = <0xc8100550 0x1c>; + #pwm-cells = <3>; + clocks = <&xtal>,<&xtal>,<&xtal>,<&xtal>; + clock-names = "clkin0","clkin1","clkin2","clkin3"; + status = "disabled"; + }; + ddr_bandwidth { + compatible = "amlogic, ddr-bandwidth"; + status = "okay"; + reg = <0xc8838000 0x100 + 0xc8837000 0x100>; + interrupts = <0 52 1>; + interrupt-names = "ddr_bandwidth"; + }; + dmc_monitor { + compatible = "amlogic, dmc_monitor"; + status = "okay"; + reg_base = <0xda838400>; + interrupts = <0 51 1>; + }; +}; + diff --git a/arch/arm/boot/dts/amlogic/mesontl1.dtsi b/arch/arm/boot/dts/amlogic/mesontl1.dtsi index 26cafb005b14..4cb13274269d 100644 --- a/arch/arm/boot/dts/amlogic/mesontl1.dtsi +++ b/arch/arm/boot/dts/amlogic/mesontl1.dtsi @@ -23,6 +23,7 @@ #include #include #include +#include #include "mesong12a-bifrost.dtsi" / { @@ -241,6 +242,20 @@ gpio-controller; #gpio-cells = <2>; }; + + aoceca_mux:aoceca_mux { + mux { + groups = "cec_ao_a"; + function = "cec_ao"; + }; + }; + + aocecb_mux:aocecb_mux { + mux { + groups = "cec_ao_b"; + function = "cec_ao"; + }; + }; }; pinctrl_periphs: pinctrl@ff6346c0 { @@ -263,11 +278,43 @@ gpio-controller; #gpio-cells = <2>; }; + + + hdmirx_a_mux:hdmirx_a_mux { + mux { + groups = "hdmirx_a_hpd", "hdmirx_a_det", + "hdmirx_a_sda", "hdmirx_a_sck"; + function = "hdmirx_a"; + }; + }; + + hdmirx_b_mux:hdmirx_b_mux { + mux { + groups = "hdmirx_b_hpd", "hdmirx_b_det", + "hdmirx_b_sda", "hdmirx_b_sck"; + function = "hdmirx_b"; + }; + }; + + hdmirx_c_mux:hdmirx_c_mux { + mux { + groups = "hdmirx_c_hpd", "hdmirx_c_det", + "hdmirx_c_sda", "hdmirx_c_sck"; + function = "hdmirx_c"; + }; + }; + }; wdt: watchdog@0xffd0f0d0 { - compatible = "amlogic,meson-tl1-wdt"; + compatible = "amlogic, meson-wdt"; status = "okay"; + default_timeout=<10>; + reset_watchdog_method=<1>; /* 0:sysfs,1:kernel */ + reset_watchdog_time=<2>; + shutdown_timeout=<10>; + firmware_timeout=<6>; + suspend_timeout=<6>; reg = <0xffd0f0d0 0x10>; clock-names = "xtal"; clocks = <&xtal>; @@ -307,6 +354,66 @@ }; };/* end of hiubus*/ + audiobus: audiobus@0xff600000 { + compatible = "amlogic, audio-controller", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0xff600000 0x10000>; + ranges = <0x0 0xff600000 0x10000>; + + clkaudio:audio_clocks { + compatible = "amlogic, tl1-audio-clocks"; + #clock-cells = <1>; + reg = <0x0 0xb0>; + }; + + ddr_manager { + compatible = "amlogic, tl1-audio-ddr-manager"; + interrupts = < + GIC_SPI 148 IRQ_TYPE_EDGE_RISING + GIC_SPI 149 IRQ_TYPE_EDGE_RISING + GIC_SPI 150 IRQ_TYPE_EDGE_RISING + GIC_SPI 48 IRQ_TYPE_EDGE_RISING + GIC_SPI 152 IRQ_TYPE_EDGE_RISING + GIC_SPI 153 IRQ_TYPE_EDGE_RISING + GIC_SPI 154 IRQ_TYPE_EDGE_RISING + GIC_SPI 49 IRQ_TYPE_EDGE_RISING + >; + interrupt-names = + "toddr_a", "toddr_b", "toddr_c", + "toddr_d", + "frddr_a", "frddr_b", "frddr_c", + "frddr_d"; + }; + };/* end of audiobus*/ + + /* Sound iomap */ + aml_snd_iomap { + compatible = "amlogic, snd-iomap"; + status = "okay"; + #address-cells=<1>; + #size-cells=<1>; + ranges; + pdm_bus { + reg = <0xFF601000 0x400>; + }; + audiobus_base { + reg = <0xFF600000 0x1000>; + }; + audiolocker_base { + reg = <0xFF601400 0x400>; + }; + eqdrc_base { + reg = <0xFF602000 0x2000>; + }; + reset_base { + reg = <0xFFD01000 0x1000>; + }; + vad_base { + reg = <0xFF601800 0x800>; + }; + }; + cbus: cbus@ffd00000 { compatible = "simple-bus"; reg = <0xffd00000 0x27000>; @@ -549,6 +656,12 @@ pinctrl-0=<&i2c_ao_slave_pins>; }; };/* end of aobus */ + + ion_dev { + compatible = "amlogic, ion_dev"; + status = "okay"; + memory-region = <&ion_cma_reserved>; + };/* end of ion_dev*/ }; /* end of soc*/ custom_maps: custom_maps { @@ -841,6 +954,134 @@ /*partions defined in dts*/ }; + mesonstream { + compatible = "amlogic, codec, streambuf"; + status = "okay"; + clocks = <&clkc CLKID_U_PARSER + &clkc CLKID_DEMUX + &clkc CLKID_AHB_ARB0 + &clkc CLKID_DOS + &clkc CLKID_VDEC_MUX + &clkc CLKID_HCODEC_MUX + &clkc CLKID_HEVC_MUX + &clkc CLKID_HEVCF_MUX>; + clock-names = "parser_top", + "demux", + "ahbarb0", + "vdec", + "clk_vdec_mux", + "clk_hcodec_mux", + "clk_hevc_mux", + "clk_hevcb_mux"; + }; + + vcodec-dec { + compatible = "amlogic, vcodec-dec"; + status = "okay"; + }; + + vdec { + compatible = "amlogic, vdec"; + status = "okay"; + interrupts = <0 3 1 + 0 23 1 + 0 32 1 + 0 43 1 + 0 44 1 + 0 45 1>; + interrupt-names = "vsync", + "demux", + "parser", + "mailbox_0", + "mailbox_1", + "mailbox_2"; + }; + + canvas: canvas { + compatible = "amlogic, meson, canvas"; + status = "okay"; + reg = <0xff638000 0x2000>; + }; + + codec_io: codec_io { + compatible = "amlogic, codec_io"; + status = "okay"; + #address-cells=<1>; + #size-cells=<1>; + ranges; + io_cbus_base{ + reg = <0xffd00000 0x100000>; + }; + io_dos_base{ + reg = <0xff620000 0x10000>; + }; + io_hiubus_base{ + reg = <0xff63c000 0x2000>; + }; + io_aobus_base{ + reg = <0xff800000 0x10000>; + }; + io_vcbus_base{ + reg = <0xff900000 0x40000>; + }; + io_dmc_base{ + reg = <0xff638000 0x2000>; + }; + io_efuse_base{ + reg = <0xff630000 0x2000>; + }; + }; + + rdma { + compatible = "amlogic, meson-tl1, rdma"; + status = "okay"; + interrupts = <0 89 1>; + interrupt-names = "rdma"; + }; + + meson_fb: fb { + compatible = "amlogic, meson-tl1"; + memory-region = <&logo_reserved>; + status = "disabled"; + interrupts = <0 3 1 + 0 56 1 + 0 89 1>; + interrupt-names = "viu-vsync", "viu2-vsync", "rdma"; + /* uboot logo,fb0/fb1 memory size,if afbcd fb0=0x01851000*/ + display_mode_default = "1080p60hz"; + scale_mode = <1>; + /** 0:VPU free scale 1:OSD free scale 2:OSD super scale */ + display_size_default = <1920 1080 1920 2160 32>; + /*1920*1080*4*3 = 0x17BB000*/ + clocks = <&clkc CLKID_VPU_CLKC_MUX>; + clock-names = "vpu_clkc"; + }; + + ge2d { + compatible = "amlogic, ge2d-g12a"; + status = "okay"; + interrupts = <0 146 1>; + interrupt-names = "ge2d"; + clocks = <&clkc CLKID_VAPB_MUX>, + <&clkc CLKID_G2D>, + <&clkc CLKID_GE2D_GATE>; + clock-names = "clk_vapb_0", + "clk_ge2d", + "clk_ge2d_gate"; + reg = <0xff940000 0x10000>; + }; + + meson-amvideom { + compatible = "amlogic, amvideom"; + status = "okay"; + interrupts = <0 3 1>; + interrupt-names = "vsync"; + }; + + vdac { + compatible = "amlogic, vdac-tl1"; + status = "okay"; + }; }; /* end of / */ &pinctrl_aobus { diff --git a/arch/arm/boot/dts/amlogic/mesontl1_pxp-panel.dtsi b/arch/arm/boot/dts/amlogic/mesontl1_pxp-panel.dtsi new file mode 100644 index 000000000000..765211c88d49 --- /dev/null +++ b/arch/arm/boot/dts/amlogic/mesontl1_pxp-panel.dtsi @@ -0,0 +1,92 @@ +/* + * arch/arm64/boot/dts/amlogic/mesontl1_pxp-panel.dtsi + * + * Copyright (C) 2016 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +/ { + lcd { + compatible = "amlogic, lcd-tl1"; + status = "okay"; + mode = "tv"; + fr_auto_policy = <0>; /* 0=disable, 1=60/50hz, 2=60/50/48hz */ + key_valid = <0>; + clocks = <&clkc CLKID_VCLK2_ENCL + &clkc CLKID_VCLK2_VENCL + &clkc CLKID_TCON + &clkc CLKID_FCLK_DIV5 + &clkc CLKID_TCON_PLL_COMP>; + clock-names = "encl_top_gate", + "encl_int_gate", + "tcon_gate", + "fclk_div5", + "clk_tcon"; + reg = <0xff660000 0x8100 + 0xff634400 0x100>; + interrupts = <0 3 1 + 0 78 1 + 0 88 1>; + interrupt-names = "vsync","vbyone","tcon"; + pinctrl_version = <2>; /* for uboot */ + + /* power type:(0=cpu_gpio, 2=signal, 3=extern, 0xff=ending) */ + /* power index:(gpios_index, or extern_index, 0xff=invalid) */ + /* power value:(0=output low, 1=output high, 2=input) */ + /* power delay:(unit in ms) */ + + lvds_0{ + model_name = "1080p-vfreq"; + interface = "lvds"; /*lcd_interface(lvds, vbyone)*/ + basic_setting = < + 1920 1080 /*h_active, v_active*/ + 2200 1125 /*h_period, v_period*/ + 8 /*lcd_bits */ + 16 9>; /*screen_widht, screen_height*/ + range_setting = < + 2060 2650 /*h_period_min,max*/ + 1100 1480 /*v_period_min,max*/ + 120000000 160000000>; /*pclk_min,max*/ + lcd_timing = < + 44 148 0 /*hs_width, hs_bp, hs_pol*/ + 5 30 0>; /*vs_width, vs_bp, vs_pol*/ + clk_attr = < + 2 /*fr_adj_type + *(0=clk, 1=htotal, 2=vtotal, 3=auto_range, + * 4=hdmi_mode) + */ + 0 /*clk_ss_level*/ + 1 /*clk_auto_generate*/ + 0>; /*pixel_clk(unit in Hz)*/ + lvds_attr = < + 1 /*lvds_repack*/ + 1 /*dual_port*/ + 0 /*pn_swap*/ + 0 /*port_swap*/ + 0>; /*lane_reverse*/ + phy_attr=< + 3 0 /*vswing_level, preem_level*/ + 0 0>; /*clk vswing_level, preem_level*/ + + /* power step: type, index, value, delay(ms) */ + power_on_step = < + 2 0 0 0 /*signal enable*/ + 0xff 0 0 0>; /*ending*/ + power_off_step = < + 2 0 0 10 /*signal disable*/ + 0xff 0 0 0>; /*ending*/ + backlight_index = <0xff>; + }; + }; /* end of lcd */ + +}; /* end of / */ diff --git a/arch/arm/boot/dts/amlogic/mesontxl.dtsi b/arch/arm/boot/dts/amlogic/mesontxl.dtsi index be4c888c2953..9cb47c6bcc9b 100644 --- a/arch/arm/boot/dts/amlogic/mesontxl.dtsi +++ b/arch/arm/boot/dts/amlogic/mesontxl.dtsi @@ -55,7 +55,7 @@ CPU0:cpu@0 { device_type = "cpu"; - compatible = "arm,cortex-a9"; + compatible = "arm,cortex-a53","arm,armv8"; reg = <0x0>; enable-method = "psci"; clocks = <&scpi_dvfs 0>; @@ -65,7 +65,7 @@ CPU1:cpu@1 { device_type = "cpu"; - compatible = "arm,cortex-a9"; + compatible = "arm,cortex-a53","arm,armv8"; reg = <0x1>; enable-method = "psci"; clocks = <&scpi_dvfs 0>; @@ -75,7 +75,7 @@ CPU2:cpu@2 { device_type = "cpu"; - compatible = "arm,cortex-a9"; + compatible = "arm,cortex-a53","arm,armv8"; reg = <0x2>; enable-method = "psci"; clocks = <&scpi_dvfs 0>; @@ -85,7 +85,7 @@ CPU3:cpu@3 { device_type = "cpu"; - compatible = "arm,cortex-a9"; + compatible = "arm,cortex-a53","arm,armv8"; reg = <0x3>; enable-method = "psci"; clocks = <&scpi_dvfs 0>; @@ -388,6 +388,14 @@ sys_poweroff = <0x84000008>; }; + rtc { + compatible = "amlogic, aml_vrtc"; + alarm_reg_addr = <0xc81000a8>; + timer_e_addr = <0xc1109988>; + init_date = "2018/01/01"; + status = "okay"; + }; + soc { compatible = "simple-bus"; #address-cells = <1>; @@ -552,8 +560,14 @@ }; wdt_ee: watchdog@98d0 { - compatible = "amlogic,meson-txl-wdt"; + compatible = "amlogic, meson-wdt"; status = "okay"; + default_timeout=<10>; + reset_watchdog_method=<1>;/*0:sysfs,1:kernel*/ + reset_watchdog_time=<2>; + shutdown_timeout=<10>; + firmware_timeout=<6>; + suspend_timeout=<6>; reg = <0x98d0 0x10>; clock-names = "xtal"; clocks = <&xtal>; diff --git a/arch/arm/boot/dts/amlogic/mesontxlx.dtsi b/arch/arm/boot/dts/amlogic/mesontxlx.dtsi index bbc9680715df..6db6187ca2fa 100644 --- a/arch/arm/boot/dts/amlogic/mesontxlx.dtsi +++ b/arch/arm/boot/dts/amlogic/mesontxlx.dtsi @@ -49,7 +49,7 @@ }; CPU0:cpu@0 { device_type = "cpu"; - compatible = "arm,cortex-a9"; + compatible = "arm,cortex-a53","arm,armv8"; reg = <0x0>; enable-method = "psci"; clocks = <&scpi_dvfs 0>; @@ -59,7 +59,7 @@ CPU1:cpu@1 { device_type = "cpu"; - compatible = "arm,cortex-a9"; + compatible = "arm,cortex-a53","arm,armv8"; reg = <0x1>; enable-method = "psci"; clocks = <&scpi_dvfs 0>; @@ -68,7 +68,7 @@ }; CPU2:cpu@2 { device_type = "cpu"; - compatible = "arm,cortex-a9"; + compatible = "arm,cortex-a53","arm,armv8"; reg = <0x2>; enable-method = "psci"; clocks = <&scpi_dvfs 0>; @@ -78,7 +78,7 @@ CPU3:cpu@3 { device_type = "cpu"; - compatible = "arm,cortex-a9"; + compatible = "arm,cortex-a53","arm,armv8"; reg = <0x0 0x3>; enable-method = "psci"; clocks = <&scpi_dvfs 0>; diff --git a/arch/arm/boot/dts/amlogic/mesontxlx_r311-panel.dtsi b/arch/arm/boot/dts/amlogic/mesontxlx_r311-panel.dtsi index 31276336f24f..73df62601014 100644 --- a/arch/arm/boot/dts/amlogic/mesontxlx_r311-panel.dtsi +++ b/arch/arm/boot/dts/amlogic/mesontxlx_r311-panel.dtsi @@ -818,6 +818,7 @@ 0xc0 2 0x34 0xc8 0xc0 2 0x35 0xbf 0xff 0>; + init_off = <0xff 0>; }; }; diff --git a/arch/arm/boot/dts/amlogic/partition_mbox_ab.dtsi b/arch/arm/boot/dts/amlogic/partition_mbox_ab.dtsi new file mode 100644 index 000000000000..a78cd67fdc23 --- /dev/null +++ b/arch/arm/boot/dts/amlogic/partition_mbox_ab.dtsi @@ -0,0 +1,169 @@ +/* + * Amlogic partition set for normal + * + * Copyright (c) 2017-2017 Amlogic Ltd + * + * This file is licensed under a dual GPLv2 or BSD license. + * + */ +/ { + partitions: partitions{ + parts = <18>; + part-0 = <&logo>; + part-1 = <&boot_a>; + part-2 = <&misc>; + part-3 = <&dto>; + part-4 = <&cri_data>; + part-5 = <¶m>; + part-6 = <&boot_b>; + part-7 = <&vbmeta_a>; + part-8 = <&vbmeta_b>; + part-9 = <&rsv>; + part-10 = <&tee>; + part-11 = <&vendor_a>; + part-12 = <&vendor_b>; + part-13 = <&odm_a>; + part-14 = <&odm_b>; + part-15 = <&system_a>; + part-16 = <&system_b>; + part-17 = <&data>; + + logo:logo{ + pname = "logo"; + size = <0x0 0x800000>; + mask = <1>; + }; + boot_a:boot_a{ + pname = "boot_a"; + size = <0x0 0x1000000>; + mask = <1>; + }; + misc:misc{ + pname = "misc"; + size = <0x0 0x800000>; + mask = <1>; + }; + dto:dto{ + pname = "dto"; + size = <0x0 0x800000>; + mask = <1>; + }; + cri_data:cri_data + { + pname = "cri_data"; + size = <0x0 0x800000>; + mask = <2>; + }; + vbmeta_a:vbmeta_a{ + pname = "vbmeta_a"; + size = <0x0 0x100000>; + mask = <1>; + }; + vbmeta_b:vbmeta_b{ + pname = "vbmeta_b"; + size = <0x0 0x100000>; + mask = <1>; + }; + rsv:rsv{ + pname = "rsv"; + size = <0x0 0xE00000>; + mask = <1>; + }; + param:param{ + pname = "param"; + size = <0x0 0x1000000>; + mask = <2>; + }; + boot_b:boot_b + { + pname = "boot_b"; + size = <0x0 0x1000000>; + mask = <1>; + }; + tee:tee{ + pname = "tee"; + size = <0x0 0x2000000>; + mask = <1>; + }; + vendor_a:vendor_a + { + pname = "vendor_a"; + size = <0x0 0x10000000>; + mask = <1>; + }; + vendor_b:vendor_b + { + pname = "vendor_b"; + size = <0x0 0x10000000>; + mask = <1>; + }; + odm_a:odm_a + { + pname = "odm_a"; + size = <0x0 0x10000000>; + mask = <1>; + }; + odm_b:odm_b + { + pname = "odm_b"; + size = <0x0 0x10000000>; + mask = <1>; + }; + system_a:system_a + { + pname = "system_a"; + size = <0x0 0x74000000>; + mask = <1>; + }; + system_b:system_b + { + pname = "system_b"; + size = <0x0 0x74000000>; + mask = <1>; + }; + data:data + { + pname = "data"; + size = <0xffffffff 0xffffffff>; + mask = <4>; + }; + }; + + firmware { + android { + compatible = "android,firmware"; + vbmeta { + compatible = "android,vbmeta"; + parts = "boot,system,vendor"; + by_name_prefix="/dev/block"; + }; + fstab { + compatible = "android,fstab"; + system { + compatible = "android,system"; + dev = "/dev/block/system"; + type = "ext4"; + mnt_flags = "ro,barrier=1,inode_readahead_blks=8"; + fsmgr_flags = "wait,slotselect"; + }; + + vendor { + compatible = "android,vendor"; + dev = "/dev/block/vendor"; + type = "ext4"; + mnt_flags = "ro,barrier=1,inode_readahead_blks=8"; + fsmgr_flags = "wait,slotselect"; + }; + + odm { + compatible = "android,odm"; + dev = "/dev/block/odm"; + type = "ext4"; + mnt_flags = "ro,barrier=1,inode_readahead_blks=8"; + fsmgr_flags = "wait,slotselect"; + }; + }; + }; + }; + +};/* end of / */ diff --git a/arch/arm/boot/dts/amlogic/partition_mbox_ab_P_32.dtsi b/arch/arm/boot/dts/amlogic/partition_mbox_ab_P_32.dtsi new file mode 100644 index 000000000000..d210d928d4a1 --- /dev/null +++ b/arch/arm/boot/dts/amlogic/partition_mbox_ab_P_32.dtsi @@ -0,0 +1,173 @@ +/* + * arch/arm/boot/dts/amlogic/partition_mbox_ab_P_32.dtsi + * + * Copyright (C) 2017 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +#include "firmware_ab.dtsi" + +/ { + partitions: partitions{ + parts = <23>; + part-0 = <&logo>; + part-1 = <&boot_a>; + part-2 = <&misc>; + part-3 = <&dtbo_a>; + part-4 = <&dtbo_b>; + part-5 = <&cri_data>; + part-6 = <¶m>; + part-7 = <&boot_b>; + part-8 = <&rsv>; + part-9 = <&metadata_a>; + part-10 = <&metadata_b>; + part-11 = <&vbmeta_a>; + part-12 = <&vbmeta_b>; + part-13 = <&tee>; + part-14 = <&vendor_a>; + part-15 = <&vendor_b>; + part-16 = <&odm_a>; + part-17 = <&odm_b>; + part-18 = <&system_a>; + part-19 = <&system_b>; + part-20 = <&product_a>; + part-21 = <&product_b>; + part-22 = <&data>; + + logo:logo{ + pname = "logo"; + size = <0x0 0x800000>; + mask = <1>; + }; + boot_a:boot_a + { + pname = "boot_a"; + size = <0x0 0x1000000>; + mask = <1>; + }; + misc:misc{ + pname = "misc"; + size = <0x0 0x800000>; + mask = <1>; + }; + dtbo_a:dtbo_a{ + pname = "dtbo_a"; + size = <0x0 0x800000>; + mask = <1>; + }; + dtbo_b:dtbo_b{ + pname = "dtbo_b"; + size = <0x0 0x800000>; + mask = <1>; + }; + cri_data:cri_data + { + pname = "cri_data"; + size = <0x0 0x800000>; + mask = <2>; + }; + rsv:rsv{ + pname = "rsv"; + size = <0x0 0x1000000>; + mask = <1>; + }; + metadata_a:metadata_a{ + pname = "metadata_a"; + size = <0x0 0x1000000>; + mask = <1>; + }; + metadata_b:metadata_b{ + pname = "metadata_b"; + size = <0x0 0x1000000>; + mask = <1>; + }; + vbmeta_a:vbmeta_a{ + pname = "vbmeta_a"; + size = <0x0 0x200000>; + mask = <1>; + }; + vbmeta_b:vbmeta_b{ + pname = "vbmeta_b"; + size = <0x0 0x200000>; + mask = <1>; + }; + param:param{ + pname = "param"; + size = <0x0 0x1000000>; + mask = <2>; + }; + boot_b:boot_b + { + pname = "boot_b"; + size = <0x0 0x1000000>; + mask = <1>; + }; + tee:tee{ + pname = "tee"; + size = <0x0 0x2000000>; + mask = <1>; + }; + vendor_a:vendor_a + { + pname = "vendor_a"; + size = <0x0 0x10000000>; + mask = <1>; + }; + vendor_b:vendor_b + { + pname = "vendor_b"; + size = <0x0 0x10000000>; + mask = <1>; + }; + odm_a:odm_a + { + pname = "odm_a"; + size = <0x0 0x8000000>; + mask = <1>; + }; + odm_b:odm_b + { + pname = "odm_b"; + size = <0x0 0x8000000>; + mask = <1>; + }; + system_a:system_a + { + pname = "system_a"; + size = <0x0 0x50000000>; + mask = <1>; + }; + system_b:system_b + { + pname = "system_b"; + size = <0x0 0x50000000>; + mask = <1>; + }; + product_a:product_a{ + pname = "product_a"; + size = <0x0 0x8000000>; + mask = <1>; + }; + product_b:product_b{ + pname = "product_b"; + size = <0x0 0x8000000>; + mask = <1>; + }; + data:data + { + pname = "data"; + size = <0xffffffff 0xffffffff>; + mask = <4>; + }; + }; +};/* end of / */ diff --git a/arch/arm/boot/dts/amlogic/partition_mbox_normal_sei32bit.dtsi b/arch/arm/boot/dts/amlogic/partition_mbox_normal_sei32bit.dtsi new file mode 100644 index 000000000000..6ca9cb94166c --- /dev/null +++ b/arch/arm/boot/dts/amlogic/partition_mbox_normal_sei32bit.dtsi @@ -0,0 +1,141 @@ +/* + * Amlogic partition set for normal + * + * Copyright (c) 2017-2017 Amlogic Ltd + * + * This file is licensed under a dual GPLv2 or BSD license. + * + */ +/ { + partitions: partitions{ + parts = <14>; + part-0 = <&logo>; + part-1 = <&recovery>; + part-2 = <&misc>; + part-3 = <&dtbo>; + part-4 = <&cri_data>; + part-5 = <¶m>; + part-6 = <&boot>; + part-7 = <&rsv>; + part-8 = <&tee>; + part-9 = <&vendor>; + part-10 = <&odm>; + part-11 = <&system>; + part-12 = <&cache>; + part-13 = <&data>; + + logo:logo{ + pname = "logo"; + size = <0x0 0x800000>; + mask = <1>; + }; + recovery:recovery{ + pname = "recovery"; + size = <0x0 0x1800000>; + mask = <1>; + }; + misc:misc{ + pname = "misc"; + size = <0x0 0x800000>; + mask = <1>; + }; + dtbo:dtbo{ + pname = "dtbo"; + size = <0x0 0x800000>; + mask = <1>; + }; + cri_data:cri_data + { + pname = "cri_data"; + size = <0x0 0x800000>; + mask = <2>; + }; + rsv:rsv{ + pname = "rsv"; + size = <0x0 0x1000000>; + mask = <1>; + }; + param:param{ + pname = "param"; + size = <0x0 0x1000000>; + mask = <2>; + }; + boot:boot + { + pname = "boot"; + size = <0x0 0x1000000>; + mask = <1>; + }; + tee:tee{ + pname = "tee"; + size = <0x0 0x2000000>; + mask = <1>; + }; + vendor:vendor + { + pname = "vendor"; + size = <0x0 0x10000000>; + mask = <1>; + }; + odm:odm + { + pname = "odm"; + size = <0x0 0x9000000>; + mask = <1>; + }; + system:system + { + pname = "system"; + size = <0x0 0x67000000>; + mask = <1>; + }; + cache:cache + { + pname = "cache"; + size = <0x0 0x32000000>; + mask = <2>; + }; + data:data + { + pname = "data"; + size = <0xffffffff 0xffffffff>; + mask = <4>; + }; + }; + + firmware { + android { + compatible = "android,firmware"; + vbmeta { + compatible = "android,vbmeta"; + parts = "boot,system,vendor"; + by_name_prefix="/dev/block"; + }; + fstab { + compatible = "android,fstab"; + system { + compatible = "android,system"; + dev = "/dev/block/system"; + type = "ext4"; + mnt_flags = "ro,barrier=1,inode_readahead_blks=8"; + fsmgr_flags = "wait"; + }; + + vendor { + compatible = "android,vendor"; + dev = "/dev/block/vendor"; + type = "ext4"; + mnt_flags = "ro,barrier=1,inode_readahead_blks=8"; + fsmgr_flags = "wait"; + }; + odm { + compatible = "android,odm"; + dev = "/dev/block/odm"; + type = "ext4"; + mnt_flags = "ro,barrier=1,inode_readahead_blks=8"; + fsmgr_flags = "wait"; + }; + }; + }; + }; +};/* end of / */ diff --git a/arch/arm/boot/dts/amlogic/partition_tv_4G.dtsi b/arch/arm/boot/dts/amlogic/partition_tv_4G.dtsi new file mode 100644 index 000000000000..9368933bb2ac --- /dev/null +++ b/arch/arm/boot/dts/amlogic/partition_tv_4G.dtsi @@ -0,0 +1,141 @@ +/* + * Amlogic partition set for normal + * + * Copyright (c) 2017-2017 Amlogic Ltd + * + * This file is licensed under a dual GPLv2 or BSD license. + * + */ +/ { + partitions: partitions{ + parts = <14>; + part-0 = <&logo>; + part-1 = <&recovery>; + part-2 = <&misc>; + part-3 = <&dto>; + part-4 = <&cri_data>; + part-5 = <¶m>; + part-6 = <&boot>; + part-7 = <&rsv>; + part-8 = <&tee>; + part-9 = <&vendor>; + part-10 = <&odm>; + part-11 = <&system>; + part-12 = <&cache>; + part-13 = <&data>; + + logo:logo{ + pname = "logo"; + size = <0x0 0x800000>; + mask = <1>; + }; + recovery:recovery{ + pname = "recovery"; + size = <0x0 0x1800000>; + mask = <1>; + }; + misc:misc{ + pname = "misc"; + size = <0x0 0x800000>; + mask = <1>; + }; + dto:dto{ + pname = "dto"; + size = <0x0 0x800000>; + mask = <1>; + }; + cri_data:cri_data + { + pname = "cri_data"; + size = <0x0 0x800000>; + mask = <2>; + }; + rsv:rsv{ + pname = "rsv"; + size = <0x0 0x1000000>; + mask = <1>; + }; + param:param{ + pname = "param"; + size = <0x0 0x1000000>; + mask = <2>; + }; + boot:boot + { + pname = "boot"; + size = <0x0 0x1000000>; + mask = <1>; + }; + tee:tee{ + pname = "tee"; + size = <0x0 0x2000000>; + mask = <1>; + }; + vendor:vendor + { + pname = "vendor"; + size = <0x0 0x10000000>; + mask = <1>; + }; + odm:odm + { + pname = "odm"; + size = <0x0 0x10000000>; + mask = <1>; + }; + system:system + { + pname = "system"; + size = <0x0 0x46000000>; + mask = <1>; + }; + cache:cache + { + pname = "cache"; + size = <0x0 0x25000000>; + mask = <2>; + }; + data:data + { + pname = "data"; + size = <0xffffffff 0xffffffff>; + mask = <4>; + }; + }; + + firmware { + android { + compatible = "android,firmware"; + vbmeta { + compatible = "android,vbmeta"; + parts = "boot,system,vendor"; + by_name_prefix="/dev/block"; + }; + fstab { + compatible = "android,fstab"; + system { + compatible = "android,system"; + dev = "/dev/block/system"; + type = "ext4"; + mnt_flags = "ro,barrier=1,inode_readahead_blks=8"; + fsmgr_flags = "wait"; + }; + + vendor { + compatible = "android,vendor"; + dev = "/dev/block/vendor"; + type = "ext4"; + mnt_flags = "ro,barrier=1,inode_readahead_blks=8"; + fsmgr_flags = "wait"; + }; + odm { + compatible = "android,odm"; + dev = "/dev/block/odm"; + type = "ext4"; + mnt_flags = "ro,barrier=1,inode_readahead_blks=8"; + fsmgr_flags = "wait"; + }; + }; + }; + }; +};/* end of / */ diff --git a/arch/arm/boot/dts/amlogic/tl1_pxp.dts b/arch/arm/boot/dts/amlogic/tl1_pxp.dts index b56c2de0fd9d..2df2461aae66 100644 --- a/arch/arm/boot/dts/amlogic/tl1_pxp.dts +++ b/arch/arm/boot/dts/amlogic/tl1_pxp.dts @@ -34,7 +34,7 @@ memory@00000000 { device_type = "memory"; - linux,usable-memory = <0x100000 0x7ff00000>; + linux,usable-memory = <0x000000 0x80000000>; }; reserved-memory { @@ -49,26 +49,625 @@ alignment = <0x400000>; alloc-ranges = <0x05000000 0x400000>; }; + + codec_mm_cma:linux,codec_mm_cma { + compatible = "shared-dma-pool"; + reusable; + /* ion_codec_mm max can alloc size 80M*/ + size = <0x13400000>; + alignment = <0x400000>; + linux,contiguous-region; + alloc-ranges = <0x30000000 0x50000000>; + }; + + /* codec shared reserved */ + codec_mm_reserved:linux,codec_mm_reserved { + compatible = "amlogic, codec-mm-reserved"; + size = <0x0>; + alignment = <0x100000>; + //no-map; + }; + + logo_reserved:linux,meson-fb { + compatible = "shared-dma-pool"; + reusable; + size = <0x800000>; + alignment = <0x400000>; + alloc-ranges = <0x7f800000 0x800000>; + }; + + ion_cma_reserved:linux,ion-dev { + compatible = "shared-dma-pool"; + reusable; + size = <0x8000000>; + alignment = <0x400000>; + }; + + /* vdin0 CMA pool */ + //vdin0_cma_reserved:linux,vdin0_cma { + // compatible = "shared-dma-pool"; + // reusable; + /* 3840x2160x4x4 ~=128 M */ + // size = <0xc400000>; + // alignment = <0x400000>; + //}; + + /* vdin1 CMA pool */ + vdin1_cma_reserved:linux,vdin1_cma { + compatible = "shared-dma-pool"; + reusable; + /* 1920x1080x2x4 =16 M */ + size = <0x1400000>; + alignment = <0x400000>; + }; + + /* for hdmi rx emp use */ + hdmirx_emp_cma_reserved:linux,emp_cma { + compatible = "shared-dma-pool"; + /*linux,phandle = <5>;*/ + reusable; + /* 2M-30M for emp or tmds to ddr */ + size = <0x01e00000>; + alignment = <0x10000>; + alloc-ranges = <0x30000000 0x50000000>; + }; + }; /* end of reserved-memory */ + + codec_mm { + compatible = "amlogic, codec, mm"; + status = "okay"; + memory-region = <&codec_mm_cma &codec_mm_reserved>; }; -}; + + vout { + compatible = "amlogic, vout"; + status = "okay"; + fr_auto_policy = <0>; + }; + + /* Audio Related start */ + pdm_codec:dummy { + #sound-dai-cells = <0>; + compatible = "amlogic, pdm_dummy_codec"; + status = "okay"; + }; + + dummy_codec:dummy { + #sound-dai-cells = <0>; + compatible = "amlogic, aml_dummy_codec"; + status = "okay"; + }; + + tl1_codec:codec { + #sound-dai-cells = <0>; + compatible = "amlogic, tl1_acodec"; + status = "disabled"; + reg = <0xff632000 0x1c>; + tdmout_index = <1>; + }; + + auge_sound { + compatible = "amlogic, tl1-sound-card"; + aml-audio-card,name = "AML-AUGESOUND"; + + aml-audio-card,dai-link@0 { + format = "dsp_a"; + mclk-fs = <512>; + //continuous-clock; + //bitclock-inversion; + //frame-inversion; + /* master mode */ + bitclock-master = <&tdma>; + frame-master = <&tdma>; + /* slave mode */ + /* + * bitclock-master = <&tdmacodec>; + * frame-master = <&tdmacodec>; + */ + /* suffix-name, sync with android audio hal used for */ + suffix-name = "alsaPORT-pcm"; + tdmacpu: cpu { + sound-dai = <&tdma>; + dai-tdm-slot-tx-mask = + <1 1 1 1 1 1 1 1>; + dai-tdm-slot-rx-mask = + <1 1 1 1 1 1 1 1>; + dai-tdm-slot-num = <8>; + dai-tdm-slot-width = <32>; + system-clock-frequency = <24576000>; + }; + tdmacodec: codec { + sound-dai = <&dummy_codec>; + }; + }; + + aml-audio-card,dai-link@1 { + format = "i2s"; + mclk-fs = <256>; + //continuous-clock; + //bitclock-inversion; + //frame-inversion; + /* master mode */ + bitclock-master = <&tdmb>; + frame-master = <&tdmb>; + /* slave mode */ + //bitclock-master = <&tdmbcodec>; + //frame-master = <&tdmbcodec>; + /* suffix-name, sync with android audio hal used for */ + suffix-name = "alsaPORT-i2s"; + cpu { + sound-dai = <&tdmb>; + dai-tdm-slot-tx-mask = <1 1>; + dai-tdm-slot-rx-mask = <1 1>; + dai-tdm-slot-num = <2>; + /* + * dai-tdm-slot-tx-mask = + * <1 1 1 1 1 1 1 1>; + * dai-tdm-slot-rx-mask = + * <1 1 1 1 1 1 1 1>; + * dai-tdm-slot-num = <8>; + */ + dai-tdm-slot-width = <32>; + system-clock-frequency = <12288000>; + }; + tdmbcodec: codec { + sound-dai = <&dummy_codec>; + }; + }; + + aml-audio-card,dai-link@2 { + format = "i2s"; + mclk-fs = <256>; + //continuous-clock; + //bitclock-inversion; + //frame-inversion; + /* master mode */ + bitclock-master = <&tdmc>; + frame-master = <&tdmc>; + /* slave mode */ + //bitclock-master = <&tdmccodec>; + //frame-master = <&tdmccodec>; + /* suffix-name, sync with android audio hal used for */ + //suffix-name = "alsaPORT-tdm"; + cpu { + sound-dai = <&tdmc>; + dai-tdm-slot-tx-mask = <1 1>; + dai-tdm-slot-rx-mask = <1 1>; + dai-tdm-slot-num = <2>; + dai-tdm-slot-width = <32>; + system-clock-frequency = <12288000>; + }; + tdmccodec: codec { + sound-dai = <&dummy_codec>; + }; + }; + + aml-audio-card,dai-link@3 { + mclk-fs = <64>; + /* suffix-name, sync with android audio hal used for */ + suffix-name = "alsaPORT-pdm"; + cpu { + sound-dai = <&pdm>; + }; + codec { + sound-dai = <&pdm_codec>; + }; + }; + + aml-audio-card,dai-link@4 { + mclk-fs = <128>; + /* suffix-name, sync with android audio hal used for */ + suffix-name = "alsaPORT-spdif"; + cpu { + sound-dai = <&spdif_a>; + system-clock-frequency = <6144000>; + }; + codec { + sound-dai = <&dummy_codec>; + }; + }; + + aml-audio-card,dai-link@5 { + mclk-fs = <128>; + cpu { + sound-dai = <&spdif_b>; + system-clock-frequency = <6144000>; + }; + codec { + sound-dai = <&dummy_codec>; + }; + }; + + aml-audio-card,dai-link@6 { + mclk-fs = <256>; + cpu { + sound-dai = <&extn>; + system-clock-frequency = <12288000>; + }; + codec { + sound-dai = <&dummy_codec>; + }; + }; + + }; + /* Audio Related end */ + + tvafe_avin_detect { + compatible = "amlogic, tl1_tvafe_avin_detect"; + status = "okay"; + device_mask = <1>;/*bit0:ch1;bit1:ch2*/ + interrupts = <0 12 1>, + <0 13 1>; + }; + + vdin@0 { + compatible = "amlogic, vdin"; + /*memory-region = <&vdin0_cma_reserved>;*/ + status = "okay"; + /*bit0:(1:share with codec_mm;0:cma alone) + *bit8:(1:alloc in discontinus way;0:alone in continuous way) + */ + flag_cma = <0x101>; + /*MByte, if 10bit disable: 64M(YUV422), + *if 10bit enable: 64*1.5 = 96M(YUV422) + *if support 4K2K-YUV444-10bit-WR:3840*2160*4*4 ~= 128M + *if support 4K2K-YUV422-10bit-wr:3840*2160*3*4 ~= 96M + *if support 4K2K-YUV422-8BIT-WR:3840*2160*2*4 ~= 64M + *if support 1080p-YUV422-8BIT-WR:1920*1080*2*4 ~= 16M + */ + cma_size = <190>; + interrupts = <0 83 1>; + rdma-irq = <2>; + clocks = <&clkc CLKID_FCLK_DIV5>, + <&clkc CLKID_VDIN_MEAS_COMP>; + clock-names = "fclk_div5", "cts_vdin_meas_clk"; + vdin_id = <0>; + /*vdin write mem color depth support: + * bit0:support 8bit + * bit1:support 9bit + * bit2:support 10bit + * bit3:support 12bit + * bit4:support yuv422 10bit full pack mode (from txl new add) + * bit8:use 8bit at 4k_50/60hz_10bit + * bit9:use 10bit at 4k_50/60hz_10bit + */ + tv_bit_mode = <0x215>; + /* afbce_bit_mode: (amlogic frame buff compression encoder) + * 0: normal mode, not use afbce + * 1: use afbce non-mmu mode + * 2: use afbce mmu mode + */ + afbce_bit_mode = <0>; + }; + + vdin@1 { + compatible = "amlogic, vdin"; + memory-region = <&vdin1_cma_reserved>; + status = "okay"; + /*bit0:(1:share with codec_mm;0:cma alone) + *bit8:(1:alloc in discontinus way;0:alone in continuous way) + */ + flag_cma = <0>; + interrupts = <0 85 1>; + rdma-irq = <4>; + clocks = <&clkc CLKID_FCLK_DIV5>, + <&clkc CLKID_VDIN_MEAS_COMP>; + clock-names = "fclk_div5", "cts_vdin_meas_clk"; + vdin_id = <1>; + /*vdin write mem color depth support: + *bit0:support 8bit + *bit1:support 9bit + *bit2:support 10bit + *bit3:support 12bit + */ + tv_bit_mode = <0x15>; + }; + + hdmirx { + compatible = "amlogic, hdmirx_tl1"; + #address-cells=<1>; + #size-cells=<1>; + memory-region = <&hdmirx_emp_cma_reserved>; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&hdmirx_a_mux &hdmirx_b_mux + &hdmirx_c_mux>; + repeat = <0>; + interrupts = <0 56 1>; + clocks = <&clkc CLKID_HDMIRX_MODET_COMP>, + <&clkc CLKID_HDMIRX_CFG_COMP>, + <&clkc CLKID_HDMIRX_ACR_COMP>, + <&clkc CLKID_HDMIRX_AUDMEAS_COMP>, + <&xtal>, + <&clkc CLKID_FCLK_DIV5>, + <&clkc CLKID_FCLK_DIV7>, + <&clkc CLKID_HDCP22_SKP_COMP>, + <&clkc CLKID_HDCP22_ESM_COMP>; + // <&clkc CLK_AUD_PLL2FS>, + // <&clkc CLK_AUD_PLL4FS>, + // <&clkc CLK_AUD_OUT>; + clock-names = "hdmirx_modet_clk", + "hdmirx_cfg_clk", + "hdmirx_acr_ref_clk", + "hdmirx_audmeas_clk", + "xtal", + "fclk_div5", + "fclk_div7", + "hdcp_rx22_skp", + "hdcp_rx22_esm"; + // "hdmirx_aud_pll2fs", + // "hdmirx_aud_pll4f", + // "clk_aud_out"; + hdmirx_id = <0>; + en_4k_2_2k = <0>; + hpd_low_cec_off = <1>; + /* bit4: enable feature, bit3~0: port number */ + disable_port = <0x0>; + /* MAP_ADDR_MODULE_CBUS */ + /* MAP_ADDR_MODULE_HIU */ + /* MAP_ADDR_MODULE_HDMIRX_CAPB3 */ + /* MAP_ADDR_MODULE_SEC_AHB */ + /* MAP_ADDR_MODULE_SEC_AHB2 */ + /* MAP_ADDR_MODULE_APB4 */ + /* MAP_ADDR_MODULE_TOP */ + reg = < 0x0 0x0 + 0xff63C000 0x2000 + 0xffe0d000 0x2000 + 0x0 0x0 + 0x0 0x0 + 0x0 0x0 + 0xff610000 0xa000>; + }; + + aocec: aocec { + compatible = "amlogic, aocec-tl1"; + /*device_name = "aocec";*/ + status = "okay"; + vendor_name = "Amlogic"; /* Max Chars: 8 */ + /* Refer to the following URL at: + * http://standards.ieee.org/develop/regauth/oui/oui.txt + */ + vendor_id = <0x000000>; + product_desc = "TL1"; /* Max Chars: 16 */ + cec_osd_string = "AML_TV"; /* Max Chars: 14 */ + port_num = <3>; + ee_cec; + arc_port_mask = <0x2>; + interrupts = <0 205 1 + 0 199 1>; + interrupt-names = "hdmi_aocecb","hdmi_aocec"; + pinctrl-names = "default","hdmitx_aocecb","cec_pin_sleep"; + pinctrl-0=<&aoceca_mux>; + pinctrl-1=<&aocecb_mux>; + pinctrl-2=<&aoceca_mux>; + reg = <0xFF80023c 0x4 + 0xFF800000 0x400>; + reg-names = "ao_exit","ao"; + }; + +}; /* end of / */ + +&audiobus { + tdma:tdm { + compatible = "amlogic, tl1-snd-tdma"; + #sound-dai-cells = <0>; + + dai-tdm-lane-slot-mask-in = <1 0>; + dai-tdm-lane-slot-mask-out = <1 0>; + dai-tdm-clk-sel = <0>; + + clocks = <&clkaudio CLKID_AUDIO_MCLK_A + &clkc CLKID_MPLL0>; + clock-names = "mclk", "clk_srcpll"; + + pinctrl-names = "tdm_pins"; + pinctrl-0 = <&tdma_mclk &tdmout_a &tdmin_a>; + + status = "okay"; + }; + + tdmb:tdm { + compatible = "amlogic, tl1-snd-tdmb"; + #sound-dai-cells = <0>; + + dai-tdm-lane-slot-mask-in = <1 0 0 0>; + dai-tdm-lane-slot-mask-out = <1 0 0 0>; + dai-tdm-clk-sel = <1>; + + clocks = <&clkaudio CLKID_AUDIO_MCLK_B + &clkc CLKID_MPLL1>; + clock-names = "mclk", "clk_srcpll"; + + status = "okay"; + }; + + tdmc:tdm { + compatible = "amlogic, tl1-snd-tdmc"; + #sound-dai-cells = <0>; + + dai-tdm-lane-slot-mask-in = <1 0 0 0>; + dai-tdm-lane-slot-mask-out = <1 0 0 0>; + dai-tdm-clk-sel = <2>; + + clocks = <&clkaudio CLKID_AUDIO_MCLK_C + &clkc CLKID_MPLL2>; + clock-names = "mclk", "clk_srcpll"; + + pinctrl-names = "tdm_pins"; + pinctrl-0 = <&tdmout_c &tdmin_c>; + + status = "okay"; + }; + + spdif_a:spdif { + compatible = "amlogic, tl1-snd-spdif-a"; + #sound-dai-cells = <0>; + + clocks = <&clkc CLKID_MPLL0 + &clkc CLKID_FCLK_DIV4 + &clkaudio CLKID_AUDIO_SPDIFIN + &clkaudio CLKID_AUDIO_SPDIFOUT + &clkaudio CLKID_AUDIO_SPDIFIN_CTRL + &clkaudio CLKID_AUDIO_SPDIFOUT_CTRL>; + clock-names = "sysclk", "fixed_clk", "gate_spdifin", + "gate_spdifout", "clk_spdifin", "clk_spdifout"; + + interrupts = + ; + interrupt-names = "irq_spdifin"; + + pinctrl-names = "spdif_pins"; + pinctrl-0 = <&spdifout_a &spdifin_a>; + + status = "okay"; + }; + + spdif_b:spdif { + compatible = "amlogic, tl1-snd-spdif-b"; + #sound-dai-cells = <0>; + + clocks = <&clkc CLKID_MPLL0 /*CLKID_HIFI_PLL*/ + &clkaudio CLKID_AUDIO_SPDIFOUTB + &clkaudio CLKID_AUDIO_SPDIFOUTB_CTRL>; + clock-names = "sysclk", + "gate_spdifout", "clk_spdifout"; + + status = "okay"; + }; + + pdm:pdm { + compatible = "amlogic, tl1-snd-pdm"; + #sound-dai-cells = <0>; + + clocks = <&clkaudio CLKID_AUDIO_PDM + &clkc CLKID_FCLK_DIV3 + &clkc CLKID_MPLL3 + &clkaudio CLKID_AUDIO_PDMIN0 + &clkaudio CLKID_AUDIO_PDMIN1>; + clock-names = "gate", + "sysclk_srcpll", + "dclk_srcpll", + "pdm_dclk", + "pdm_sysclk"; + + pinctrl-names = "pdm_pins"; + pinctrl-0 = <&pdmin>; + + /* mode 0~4, defalut:1 */ + filter_mode = <1>; + + status = "okay"; + }; + + extn:extn { + compatible = "amlogic, snd-extn"; + #sound-dai-cells = <0>; + + interrupts = + ; + interrupt-names = "irq_frhdmirx"; + + status = "okay"; + }; + +}; /* end of audiobus */ + +&pinctrl_periphs { + /* audio pin mux */ + + tdma_mclk: tdma_mclk { + mux { /* GPIOZ_0 */ + groups = "mclk0_z"; + function = "mclk0"; + }; + }; + + tdmout_a: tdmout_a { + mux { /* GPIOZ_1, GPIOZ_2, GPIOZ_3, GPIOZ_5, GPIOZ_6 */ + groups = "tdma_sclk_z", + "tdma_fs_z", + "tdma_dout0_z", + "tdma_dout2_z", + "tdma_dout3_z"; + function = "tdma_out"; + }; + }; + + tdmin_a: tdmin_a { + mux { /* GPIOZ_9 */ + groups = "tdma_din2_z"; + function = "tdma_in"; + }; + }; + + tdmout_c: tdmout_c { + mux { /* GPIODV_7, GPIODV_8, GPIODV_9 */ + groups = "tdmc_sclk", + "tdmc_fs", + "tdmc_dout0"; + function = "tdmc_out"; + }; + }; + + tdmin_c: tdmin_c { + mux { /* GPIODV_10 */ + groups = "tdmc_din1"; + function = "tdmc_in"; + }; + }; + + spdifin_a: spdifin_a { + mux { /* GPIODV_5 */ + groups = "spdif_in"; + function = "spdif_in"; + }; + }; + + spdifout_a: spdifout_a { + mux { /* GPIODV_4 */ + groups = "spdif_out_dv4"; + function = "spdif_out"; + }; + }; + + pdmin: pdmin { + mux { /* GPIOZ_7, GPIOZ_8*/ + groups = "pdm_dclk_z", + "pdm_din0_z"; + function = "pdm"; + }; + }; + + +}; /* end of pinctrl_periphs */ + +&pinctrl_aobus { + spdifout: spdifout { + mux { /* gpiao_10 */ + groups = "spdif_out_ao"; + function = "spdif_out_ao"; + }; + }; +}; /* end of pinctrl_aobus */ + &sd_emmc_b { status = "okay"; sd { caps = "MMC_CAP_4_BIT_DATA", - "MMC_CAP_MMC_HIGHSPEED", - "MMC_CAP_SD_HIGHSPEED", - "MMC_CAP_NONREMOVABLE"; /**ptm debug */ + "MMC_CAP_MMC_HIGHSPEED", + "MMC_CAP_SD_HIGHSPEED", + "MMC_CAP_NONREMOVABLE"; /**ptm debug */ f_min = <400000>; f_max = <200000000>; }; -}; /* end of / */ +}; &spifc { status = "disabled"; spi-nor@0 { cs_gpios = <&gpio BOOT_13 GPIO_ACTIVE_HIGH>; - }; }; +}; &slc_nand { status = "disabled"; @@ -143,3 +742,12 @@ pinctrl-0 = <&spicc0_pins_h>; cs-gpios = <&gpio GPIOH_20 0>; }; + +&meson_fb { + status = "okay"; + display_size_default = <1920 1080 1920 2160 32>; + mem_size = <0x00800000 0x1980000 0x100000 0x800000>; + logo_addr = "0x7f800000"; + mem_alloc = <1>; + pxp_mode = <1>; /** 0:normal mode 1:pxp mode */ +}; diff --git a/arch/arm/boot/dts/amlogic/txl_t950_p341.dts b/arch/arm/boot/dts/amlogic/txl_t950_p341.dts new file mode 100644 index 000000000000..4f53cadaa1f1 --- /dev/null +++ b/arch/arm/boot/dts/amlogic/txl_t950_p341.dts @@ -0,0 +1,1132 @@ +/* + * arch/arm/boot/dts/amlogic/txl_t950_341.dts + * + * Copyright (C) 2018 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +/dts-v1/; + +#include "mesontxl.dtsi" +#include "partition_mbox_normal.dtsi" +#include "mesontxl_p321-panel.dtsi" + +/ { + model = "Amlogic TXL T950 P341 Reference Board"; + compatible = "amlogic, txl_t950_p341"; + amlogic-dt-id = "txl_p341_v1"; + + aliases { + serial0 = &uart_AO; + serial1 = &uart_A; + serial2 = &uart_B; + serial3 = &uart_C; + serial4 = &uart_AO_B; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c_AO; + }; + + ion_dev { + compatible = "amlogic, ion_dev"; + memory-region = <&ion_reserved>; + }; + + memory@00000000 { + device_type = "memory"; + linux,usable-memory = <0x100000 0x3ff00000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + /* global autoconfigured region for contiguous allocations */ + + defendkey_reserved:linux,defendkey { + compatible = "amlogic, defendkey"; + reg = <0x08300000 0x100000>; + }; + + secmon_reserved:linux,secmon { + compatible = "shared-dma-pool"; + reusable; + size = <0x400000>; + alignment = <0x400000>; + alloc-ranges = <0x05000000 0x400000>; + }; + + secos_reserved:linux,secos { + compatible = "amlogic, aml_secos_memory"; + status = "disable"; + reg = <0x05300000 0x2000000>; + no-map; + }; + + logo_reserved:linux,meson-fb { + compatible = "shared-dma-pool"; + reusable; + size = <0x800000>; + alignment = <0x400000>; + alloc-ranges = <0x3f800000 0x800000>; + }; + + ion_reserved:linux,ion-dev { + compatible = "shared-dma-pool"; + reusable; + // if no direct render, ion size = fb0_size x 3 + fb1_size + 4 M + size = <0x2400000>; + alignment = <0x400000>; + }; + + codec_mm_cma:linux,codec_mm_cma { + compatible = "shared-dma-pool"; + reusable; + /* ion_codec_mm max can alloc size 80M*/ + size = <0xd000000>; + alignment = <0x400000>; + linux,contiguous-region; + alloc-ranges = <0x0 0x30000000>; + }; + + /* codec shared reserved */ + codec_mm_reserved:linux,codec_mm_reserved { + compatible = "amlogic, codec-mm-reserved"; + size = <0x0>; + alignment = <0x100000>; + //no-map; + }; + + //di_reserved:linux,di { + //compatible = "amlogic, di-mem"; + /* buffer_size = 3621952(yuv422 8bit) */ + /* 4179008(yuv422 10bit full pack mode) */ + /** 10x3621952=34.6M(0x23) support 8bit **/ + /** 10x4736064=45.2M(0x2e) support 12bit **/ + /** 10x4179008=40M(0x28) support 10bit **/ + //size = <0x2800000>; + //no-map; + //}; + + /*di CMA pool */ + di_cma_reserved:linux,di_cma { + compatible = "shared-dma-pool"; + reusable; + /* buffer_size = 3621952(yuv422 8bit) + * | 4736064(yuv422 10bit) + * | 4179008(yuv422 10bit full pack mode) + * 10x3621952=34.6M(0x23) support 8bit + * 10x4736064=45.2M(0x2e) support 12bit + * 10x4179008=40M(0x28) support 10bit + */ + size = <0x02800000>; + alignment = <0x400000>; + }; + + /* POST PROCESS MANAGER */ + ppmgr_reserved:linux,ppmgr { + compatible = "amlogic, ppmgr_memory"; + size = <0x0>; + }; + + picdec_cma_reserved:linux,picdec { + compatible = "shared-dma-pool"; + reusable; + size = <0x0>; + alignment = <0x0>; + linux,contiguous-region; + }; + + demod_cma_reserved:linux,demod_cma { + compatible = "shared-dma-pool"; + reusable; + /* 5M */ + size = <0x0800000>; + alignment = <0x400000>; + }; + + /* vdin0 CMA pool */ + vdin0_cma_reserved:linux,vdin0_cma { + compatible = "shared-dma-pool"; + reusable; + /* 1920x1080x2x4 =16+4 M */ + size = <0x04000000>; + alignment = <0x400000>; + }; + + /* vdin1 CMA pool */ + vdin1_cma_reserved:linux,vdin1_cma { + compatible = "shared-dma-pool"; + reusable; + /* 1920x1080x2x4 =16 M */ + size = <0x04000000>; + alignment = <0x400000>; + }; + }; /* end of reserved-memory */ + + secmon { + compatible = "amlogic, secmon"; + memory-region = <&secmon_reserved>; + in_base_func = <0x82000020>; + out_base_func = <0x82000021>; + reserve_mem_size = <0x00300000>; + }; + + gpioleds { + compatible = "gpio-leds"; + status = "disabled"; + + sys_led { + label = "sys_led"; + gpios = <&gpio_ao GPIOAO_3 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + }; + + /*for external keypad*/ + adc-keypad { + compatible = "amlogic, adc_keypad"; + status = "okay"; + key_name = "menu","down", "up","source","left","right","enter"; + key_num = <7>; + io-channels = <&saradc SARADC_CH2>; + io-channel-names = "key-chan-2"; + key_chan = ; + key_code = <139 108 103 466 105 106 28>; + key_val = <152 283 421 557 718 852 0>; + key_tolerance = <40 40 40 40 40 40 40>; + }; + + avin_detect { + compatible = "amlogic, avin_detect"; + status = "okay"; + avin_device_num = <2>; + gpios = <&gpio GPIODV_8 GPIO_ACTIVE_HIGH>, + <&gpio GPIODV_6 GPIO_ACTIVE_HIGH>; + detect_interval_length = <100>; + set_detect_times = <5>; + set_fault_tolerance = <1>; + }; + + meson-fb { + compatible = "amlogic, meson-txl"; + memory-region = <&logo_reserved>; + dev_name = "meson-fb"; + status = "okay"; + interrupts = <0 3 1 + 0 89 1>; + interrupt-names = "viu-vsync", "rdma"; + mem_size = <0x00800000 0x01800000 0x00100000>; + /* uboot logo,fb0/fb1 memory size,if afbcd fb0=0x01851000*/ + display_mode_default = "1080p60hz"; + /* 0:VPU free scale 1:OSD free scale 2:OSD super scale */ + scale_mode = <1>; + /* 1920*1080*4*3 = 0x17BB000 */ + display_size_default = <1920 1080 1920 3240 32>; + pxp_mode = <0>; /** 0:normal mode 1:pxp mode */ + logo_addr = "0x3f800000"; + }; + + picdec { + compatible = "amlogic, picdec"; + status = "okay"; + memory-region = <&picdec_cma_reserved>; + }; + + ppmgr { + compatible = "amlogic, ppmgr"; + status = "okay"; + memory-region = <&ppmgr_reserved>; + }; + + deinterlace { + compatible = "amlogic, deinterlace"; + status = "okay"; + /* 0:use reserved; 1:use cma; 2:use cma as reserved */ + flag_cma = <1>; + //memory-region = <&di_reserved>; + memory-region = <&di_cma_reserved>; + interrupts = <0 46 1 + 0 6 1>; + interrupt-names = "de_irq"; + clocks = <&clkc CLKID_VPU_MUX>, + <&clkc CLKID_FCLK_DIV4>, + <&clkc CLKID_VPU_CLKB_TMP_COMP>, + <&clkc CLKID_VPU_CLKB_COMP>; + clock-names = "vpu_mux", + "fclk_div4", + "vpu_clkb_tmp_composite", + "vpu_clkb_composite"; + clock-range = <333 333>; + /* buffer-size = <3621952>;(yuv422 8bit) */ + buffer-size = <4179008>;/*yuv422 fullpack*/ + /* reserve-iomap = "true"; */ + /* if enable nr10bit, set nr10bit-support to 1 */ + nr10bit-support = <1>; + }; + + ionvideo { + compatible = "amlogic, ionvideo"; + dev_name = "ionvideo"; + status = "okay"; + }; + + hdmirx { + compatible = "amlogic, hdmirx-txl"; + status = "okay"; + #address-cells=<1>; + #size-cells=<1>; + dev_name = "hdmirx"; + pinctrl-names = "hdmirx_pins"; + pinctrl-0 = <&hdmirx_a_mux &hdmirx_b_mux + &hdmirx_c_mux>; + repeat = <0>; + interrupts = <0 56 1>; + clocks = <&clkc CLKID_HDMIRX_MODET_COMP>, + <&clkc CLKID_HDMIRX_CFG_COMP>, + <&clkc CLKID_HDMIRX_ACR_COMP>, + <&clkc CLKID_HDMIRX_AUDMEAS_COMP>, + <&xtal>, + <&clkc CLKID_FCLK_DIV5>, + <&clkc CLKID_FCLK_DIV7>, + <&clkc CLKID_HDCP22_SKP_COMP>, + <&clkc CLKID_HDCP22_ESM_COMP>; + //<&clkc CLK_AUD_PLL2FS>, + //<&clkc CLK_AUD_PLL4FS>, + //<&clkc CLK_AUD_OUT>; + clock-names = "hdmirx_modet_clk", + "hdmirx_cfg_clk", + "hdmirx_acr_ref_clk", + "hdmirx_audmeas_clk", + "xtal", + "fclk_div5", + "fclk_div7", + "hdcp_rx22_skp", + "hdcp_rx22_esm"; + //"hdmirx_aud_pll2fs", + //"hdmirx_aud_pll4f", + //"clk_aud_out"; + hdmirx_id = <0>; + en_4k_2_2k = <0>; + hpd_low_cec_off = <1>; + /* bit4: enable feature, bit3~0: port number */ + disable_port = <0x0>; + reg = <0xc0800000 0xa00000 + 0xC883C000 0x2000 + 0xd0076000 0x2000 + 0xc883e000 0x2000 + 0xda83e000 0x2000 + 0xc8834000 0x2000 + 0xda846000 0x2000>; + }; + + vdin@0 { + compatible = "amlogic, vdin"; + /*memory-region = <&vdin0_cma_reserved>;*/ + dev_name = "vdin0"; + status = "okay"; + reserve-iomap = "true"; + /*bit0:(1:share with codec_mm;0:cma alone)*/ + /*bit8:(1:alloc in discontinus way;0:alone in continuous way)*/ + flag_cma = <0x101>; + /* MByte, if 10bit disable: 64M(YUV422), + * if 10bit enable: 64*1.5 = 96M(YUV422) + * if support 4K2K-YUV444-10bit-WR:3840*2160*4*4 ~= 128M + * if support 4K2K-YUV444-10bit-WR:3840*2160*4*6 ~= 190M + * if support 4K2K-YUV422-10bit-wr:3840*2160*3*4 ~= 96M + * if support 4K2K-YUV422-8BIT-WR:3840*2160*2*4 ~= 64M + * if support 1080p-YUV422-8BIT-WR:1920*1080*2*4 ~= 16M + */ + cma_size = <190>; + interrupts = <0 83 1>; + rdma-irq = <2>; + clocks = <&clkc CLKID_FCLK_DIV5>, + <&clkc CLKID_VDIN_MEAS_COMP>; + clock-names = "fclk_div5", "cts_vdin_meas_clk"; + vdin_id = <0>; + /* vdin write mem color depth support: + * bit0:support 8bit + * bit1:support 9bit + * bit2:support 10bit + * bit3:support 12bit + * bit4:support yuv422 10bit full pack mode (from txl new add) + * bit8:use 8bit at 4k_50/60hz_10bit + * bit9:use 10bit at 4k_50/60hz_10bit + */ + tv_bit_mode = <0x215>; + }; + + vdin@1 { + compatible = "amlogic, vdin"; + status = "okay"; + memory-region = <&vdin1_cma_reserved>; + dev_name = "vdin1"; + reserve-iomap = "true"; + flag_cma = <0>;/*1:share with codec_mm;0:cma alone*/ + interrupts = <0 85 1>; + rdma-irq = <4>; + clocks = <&clkc CLKID_FCLK_DIV5>, + <&clkc CLKID_VDIN_MEAS_COMP>; + clock-names = "fclk_div5", "cts_vdin_meas_clk"; + vdin_id = <1>; + /* vdin write mem color depth support: + * bit0:support 8bit + * bit1:support 9bit + * bit2:support 10bit + * bit3:support 12bit + */ + tv_bit_mode = <21>; + }; + + tvafe:tvafe@c8842000 { + compatible = "amlogic, tvafe-txl"; + status = "okay"; + /*memory-region = <&tvafe_cma_reserved>;*/ + dev_name = "tvafe"; + flag_cma = <1>;/*1:share with codec_mm;0:cma alone*/ + cma_size = <5>;/*MByte*/ + reg = <0xc8842000 0x2000>;/*tvafe reg base*/ + reserve-iomap = "true"; + tvafe_id = <0>; + //pinctrl-names = "default"; + /*!!particular sequence, no more and no less!!!*/ + tvafe_pin_mux = < + 3 /* TVAFE_CVBS_IN2, CVBS_IN0 = 0 */ + 1 /* TVAFE_CVBS_IN0, CVBS_IN1 */ + 2 /* TVAFE_CVBS_IN1, CVBS_IN2 */ + 4 /* TVAFE_CVBS_IN3, CVBS_IN3 */ + >; + clocks = <&clkc CLKID_DAC_CLK>; + clock-names = "vdac_clk_gate"; + }; + + vecm { + compatible = "amlogic, vecm"; + dev_name = "aml_vecm"; + status = "okay"; + gamma_en = <1>;/*1:enabel ;0:disable*/ + wb_en = <1>;/*1:enabel ;0:disable*/ + cm_en = <1>;/*1:enabel ;0:disable*/ + wb_sel = <1>;/*1:mtx ;0:gainoff*/ + vlock_en = <1>;/*1:enable;0:disable*/ + vlock_mode = <0x4>; + /* vlock work mode: + *bit0:auto ENC + *bit1:auto PLL + *bit2:manual PLL + *bit3:manual ENC + *bit4:manual soft ENC + *bit5:manual MIX PLL ENC + */ + vlock_pll_m_limit = <1>; + vlock_line_limit = <3>; + }; + + tuner: tuner { + status = "okay"; + tuner_name = "r842_tuner"; + tuner_i2c_adap = <&i2c1>; + tuner_i2c_addr = <0xf6>; + tuner_xtal = <1>; /* 0: 16MHz, 1: 24MHz, 3: 27MHz */ + tuner_xtal_mode = <3>; + /* NO_SHARE_XTAL(0) + * MASTER_TO_SLAVE_XTAL_IN(1) + * MASTER_TO_SLAVE_XTAL_OUT(2) + * SLAVE_XTAL_OUT(3) + */ + tuner_xtal_cap = <0>; /* 0 ~ 41 (pf) */ + }; + + atv-demod { + compatible = "amlogic, atv-demod"; + status = "okay"; + tuner = <&tuner>; + btsc_sap_mode = <1>; + pinctrl-names = "atvdemod_agc_pins"; + pinctrl-0 = <&atvdemod_agc_pins>; + reg = <0xc8840000 0x2000 /* demod reg */ + 0xc883c000 0x2000 /* hiu reg */ + 0xc8834000 0x2000>; /* periphs reg */ + reg_23cf = <0x88188832>; + /*default:0x88188832;r840 on haier:0x48188832*/ + }; + + sd_emmc_c: emmc@d0074000 { + compatible = "amlogic, meson-mmc-txl"; + status = "okay"; + reg = <0xd0074000 0x2000>; + interrupts = <0 218 1>; + pinctrl-names = "emmc_clk_cmd_pins", "emmc_all_pins"; + pinctrl-0 = <&emmc_clk_cmd_pins>; + pinctrl-1 = <&emmc_conf_pull_up &emmc_conf_pull_done>; + clocks = <&clkc CLKID_SD_EMMC_C>, + <&clkc CLKID_SD_EMMC_C_COMP>, + <&clkc CLKID_FCLK_DIV2>; + clock-names = "core", "clkin0", "clkin1"; + + bus-width = <8>; + cap-sd-highspeed; + cap-mmc-highspeed; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + + max-frequency = <200000000>; + non-removable; + disable-wp; + emmc { + pinname = "emmc"; + ocr_avail = <0x200080>; /**VDD voltage 3.3 ~ 3.4 */ + caps = "MMC_CAP_8_BIT_DATA", + "MMC_CAP_MMC_HIGHSPEED", + "MMC_CAP_SD_HIGHSPEED", + "MMC_CAP_NONREMOVABLE", + "MMC_CAP_1_8V_DDR", + "MMC_CAP_HW_RESET", + "MMC_CAP_ERASE", + "MMC_CAP_CMD23"; + caps2 = "MMC_CAP2_HS200"; + f_min = <400000>; + f_max = <100000000>; + max_req_size = <0x20000>; /**128KB*/ + gpio_dat3 = <&gpio BOOT_3 GPIO_ACTIVE_HIGH>; + hw_reset = <&gpio BOOT_9 GPIO_ACTIVE_HIGH>; + tx_phase = <3>; + card_type = <1>; + /* 1:mmc card(include eMMC), + * 2:sd card(include tSD) + */ + }; + }; + + sd_emmc_b:sd@d0072000 { + compatible = "amlogic, meson-mmc-txl"; + status = "okay"; + reg = <0xd0072000 0x2000>; + interrupts = <0 217 1>; + pinctrl-names = "sd_all_pins", + "sd_clk_cmd_pins"; + pinctrl-0 = <&sd_all_pins>; + pinctrl-1 = <&sd_clk_cmd_pins>; + clocks = <&clkc CLKID_SD_EMMC_B>, + <&clkc CLKID_SD_EMMC_B_COMP>, + <&clkc CLKID_FCLK_DIV2>; + clock-names = "core", "clkin0", "clkin1"; + + bus-width = <4>; + cap-sd-highspeed; + max-frequency = <100000000>; + disable-wp; + sd { + pinname = "sd"; + ocr_avail = <0x200080>; /**VDD voltage 3.3 ~ 3.4 */ + caps = "MMC_CAP_4_BIT_DATA", + "MMC_CAP_MMC_HIGHSPEED", + "MMC_CAP_SD_HIGHSPEED", + "MMC_CAP_NONREMOVABLE", + "MMC_CAP_UHS_SDR12", + "MMC_CAP_UHS_SDR25", + "MMC_CAP_UHS_SDR50", + "MMC_CAP_UHS_SDR104", + "MMC_CAP_SDIO_IRQ"; + f_min = <400000>; + f_max = <100000000>; + max_req_size = <0x20000>; /**128KB*/ + card_type = <3>; + /* 0:unknown, + * 1:mmc card(include eMMC), + * 2:sd card(include tSD), + * 3:sdio device(ie:sdio-wifi), + * 4:SD combo (IO+mem) card, + * 5:NON sdio device(means sd/mmc card), + * other:reserved + */ + }; + }; + + unifykey { + compatible = "amlogic, unifykey"; + status = "okay"; + + unifykey-num = <19>; + unifykey-index-0 = <&keysn_0>; + unifykey-index-1 = <&keysn_1>; + unifykey-index-2 = <&keysn_2>; + unifykey-index-3 = <&keysn_3>; + unifykey-index-4 = <&keysn_4>; + unifykey-index-5 = <&keysn_5>; + unifykey-index-6 = <&keysn_6>; + unifykey-index-7 = <&keysn_7>; + unifykey-index-8 = <&keysn_8>; + unifykey-index-9 = <&keysn_9>; + unifykey-index-10= <&keysn_10>; + unifykey-index-11 = <&keysn_11>; + unifykey-index-12 = <&keysn_12>; + unifykey-index-13 = <&keysn_13>; + unifykey-index-14 = <&keysn_14>; + unifykey-index-15 = <&keysn_15>; + unifykey-index-16 = <&keysn_16>; + unifykey-index-17 = <&keysn_17>; + unifykey-index-18 = <&keysn_18>; + + keysn_0: key_0{ + key-name = "usid"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_1:key_1{ + key-name = "mac"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_2:key_2{ + key-name = "hdcp"; + key-device = "secure"; + key-type = "sha1"; + key-permit = "read","write","del"; + }; + keysn_3:key_3{ + key-name = "secure_boot_set"; + key-device = "efuse"; + key-permit = "write"; + }; + keysn_4:key_4{ + key-name = "mac_bt"; + key-device = "normal"; + key-permit = "read","write","del"; + key-type = "mac"; + }; + keysn_5:key_5{ + key-name = "mac_wifi"; + key-device = "normal"; + key-permit = "read","write","del"; + key-type = "mac"; + }; + keysn_6:key_6{ + key-name = "hdcp2_tx"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_7:key_7{ + key-name = "hdcp2_rx"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_8:key_8{ + key-name = "widevinekeybox"; + key-device = "secure"; + key-type = "sha1"; + key-permit = "read","write","del"; + }; + keysn_9:key_9{ + key-name = "deviceid"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_10:key_10{ + key-name = "hdcp22_fw_private"; + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_11:key_11{ + key-name = "hdcp22_rx_private"; + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_12:key_12{ + key-name = "hdcp22_rx_fw"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_13:key_13{ + key-name = "hdcp14_rx"; + key-device = "normal"; + key-type = "sha1"; + key-permit = "read","write","del"; + }; + keysn_14:key_14{ + key-name = "prpubkeybox";// PlayReady + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_15:key_15{ + key-name = "prprivkeybox";// PlayReady + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_16:key_16{ + key-name = "lcd"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_17:key_17{ + key-name = "lcd_extern"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_18:key_18{ + key-name = "backlight"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + }; /* End unifykey */ + + vout { + compatible = "amlogic, vout"; + dev_name = "vout"; + status = "okay"; + fr_auto_policy = <0>; + }; + + dvb { + compatible = "amlogic, dvb"; + dev_name = "dvb"; + status = "okay"; + fe0_mode = "internal"; + fe0_tuner = <&tuner>; + + /*"parallel","serial","disable"*/ + ts2 = "parallel"; + ts2_control = <0>; + ts2_invert = <0>; + interrupts = <0 23 1 + 0 5 1 + 0 53 1 + 0 19 1 + 0 25 1 + 0 18 1 + 0 24 1>; + interrupt-names = "demux0_irq", + "demux1_irq", + "demux2_irq", + "dvr0_irq", + "dvr1_irq", + "dvrfill0_fill", + "dvrfill1_flush"; + clocks = <&clkc CLKID_DEMUX + &clkc CLKID_ASYNC_FIFO + &clkc CLKID_AHB_ARB0 + &clkc CLKID_DOS_PARSER>; + clock-names = "demux", "asyncfifo", "ahbarb0", "uparsertop"; + }; + + meson_sensor: sensor@0 { + compatible = "amlogic, aml-thermal"; + #thermal-sensor-cells = <1>; + cooling_devices { + cpufreq_cool_cluster0 { + min_state = <1000000>; + dyn_coeff = <140>; + cluster_id = <0>; + node_name = "cpus"; + device_type = "cpufreq"; + }; + cpucore_cool_cluster0 { + min_state = <1>; + dyn_coeff = <0>; + cluster_id = <0>; + node_name = "cpu_core_cluster0"; + device_type = "cpucore"; + }; + gpufreq_cool { + min_state = <400>; + dyn_coeff = <437>; + cluster_id = <0>; + node_name = "mali"; + device_type = "gpufreq"; + }; + gpucore_cool { + min_state = <1>; + dyn_coeff = <0>; + cluster_id = <0>; + node_name = "thermal_gpu_cores"; + device_type = "gpucore"; + }; + }; + cpu_cluster0:cpu_core_cluster0 { + #cooling-cells = <2>; /* min followed by max */ + }; + gpucore:thermal_gpu_cores { + #cooling-cells = <2>; /* min followed by max */ + }; + }; + + dtv-demod { + compatible = "amlogic, ddemod-txl"; + status = "okay"; + + pinctrl-names = "dtvdemod_agc_pins"; + pinctrl-0 = <&dtvdemod_agc_pins>; + + clocks = <&clkc CLKID_DAC_CLK>; + clock-names = "vdac_clk_gate"; + + reg = <0xc8844000 0x2000 /*dtv demod base*/ + 0xc883c000 0x2000 /*hiu reg base*/ + 0xc8100000 0x1000 /*io_aobus_base*/ + 0xc1104400 0x1000 /*reset*/ + >; + /*move from dvbfe*/ + dtv_demod0_mem = <0>; // need move to aml_dtv_demod ? + spectrum = <1>; + cma_flag = <1>; + cma_mem_size = <8>; + memory-region = <&demod_cma_reserved>;//<&demod_reserved>; + }; + + thermal-zones { + soc_thermal { + polling-delay = <1000>; + polling-delay-passive = <100>; + sustainable-power = <2150>; + thermal-sensors = <&meson_sensor 3>; + + trips { + switch_on: trip-point@0 { + temperature = <70000>; + hysteresis = <1000>; + type = "passive"; + }; + control: trip-point@1 { + temperature = <80000>; + hysteresis = <1000>; + type = "passive"; + }; + hot: trip-point@2 { + temperature = <85000>; + hysteresis = <5000>; + type = "hot"; + }; + critical: trip-point@3 { + temperature = <260000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + + cooling-maps { + cpufreq_cooling_map { + trip = <&control>; + cooling-device = <&cpus 0 4>; + contribution = <1024>; + }; + cpucore_cooling_map { + trip = <&control>; + cooling-device = <&cpu_cluster0 0 3>; + contribution = <1024>; + }; + gpufreq_cooling_map { + trip = <&control>; + cooling-device = <&gpu 0 4>; + contribution = <1024>; + }; + gpucore_cooling_map { + trip = <&control>; + cooling-device = <&gpucore 0 2>; + contribution = <1024>; + }; + }; + }; + }; + + /* start AUDIO_RELATED */ + i2s_dai: I2S { + #sound-dai-cells = <0>; + compatible = "amlogic, aml-i2s-dai"; + clocks = < + &clkc CLKID_MPLL3 + &clkc CLKID_AMCLK_COMP + &clkc CLKID_AIU_GLUE + &clkc CLKID_I2S_OUT + &clkc CLKID_AMCLK_MEASURE + &clkc CLKID_AIFIFO2 + &clkc CLKID_MIXER + &clkc CLKID_MIXER_IFACE + &clkc CLKID_ADC + &clkc CLKID_AIU_TOP + &clkc CLKID_AOCLK_GATE + &clkc CLKID_I2S_SPDIF + >; + clock-names = + "mpll", + "mclk", + "top_glue", + "i2s_out", + "amclk_measure", + "aififo2", + "aud_mixer", + "mixer_reg", + "adc", + "top_level", + "aoclk", + "aud_in"; + }; + + spdif_dai: SPDIF { + #sound-dai-cells = <0>; + compatible = "amlogic, aml-spdif-dai"; + clocks = < + &clkc CLKID_MPLL1 + &clkc CLKID_IEC958_INT_COMP + &clkc CLKID_AMCLK_COMP + &clkc CLKID_IEC958_MUX + &clkc CLKID_CLK81 + &clkc CLKID_IEC958 + &clkc CLKID_IEC958_GATE + >; + clock-names = + "mpll1", + "i958", + "mclk", + "spdif", + "clk_81", + "iec958", + "iec958_amclk"; + }; + + pcm_dai: PCM { + #sound-dai-cells = <0>; + compatible = "amlogic, aml-pcm-dai"; + pinctrl-names = "audio_pcm"; + /* disable pcm pin mux temporary, enable it if necessary */ + /*pinctrl-0 = <&aml_audio_pcm>;*/ + clocks = < + &clkc CLKID_MPLL0 + &clkc CLKID_PCM_MCLK_COMP + &clkc CLKID_PCM_SCLK_COMP + >; + clock-names = "mpll0", "pcm_mclk", "pcm_sclk"; + pcm_mode = <1>; /* 0=slave mode, 1=master mode */ + }; + + i2s_plat: i2s_platform { + compatible = "amlogic, aml-i2s"; + interrupts = <0 29 1>; + }; + + pcm_plat: pcm_platform { + compatible = "amlogic, aml-pcm"; + }; + + spdif_codec: spdif_codec { + #sound-dai-cells = <0>; + compatible = "amlogic, aml-spdif-codec"; + status = "okay"; + pinctrl-names = "audio_spdif_out"; + pinctrl-0 = <&audio_spdif_out_pins>; + }; + + pcm_codec: pcm_codec { + #sound-dai-cells = <0>; + compatible = "amlogic, pcm2BT-codec"; + status = "okay"; + }; + /* endof AUDIO MESON8 DEVICES */ + + /* AUDIO board specific */ + dummy_codec:dummy { + #sound-dai-cells = <0>; + compatible = "amlogic, aml_dummy_codec"; + status = "disabled"; + }; + + amlogic_codec:t9015S { + #sound-dai-cells = <0>; + compatible = "amlogic, aml_codec_T9015S"; + status = "okay"; + reg = <0xc8832000 0x14>; + }; + + aml_snd_tv { + compatible = "amlogic, txl-snd-tv"; + status = "okay"; + aml-sound-card,format = "i2s"; + aml_sound_card,name = "AML-TVAUDIO"; + pinctrl-names = "audio_i2s"; + pinctrl-0 = <&aml_audio_i2s>; + /*avout mute gpio, if av_mute_inv = 1, invert gpio*/ + mute_gpio-gpios = <&gpio GPIODV_11 GPIO_ACTIVE_LOW>; + av_mute_inv = <0>; + /*after sleep time, unmute avout*/ + sleep_time = <0>; + /*analog amp mute pinmux*/ + amp_mute_gpio-gpios = <&gpio GPIOZ_13 GPIO_ACTIVE_LOW>; + amp_mute_inv = <0>; + /* if 1, enable switch AV / HS Detect */ + av_hs_switch = <1>; + hp_det-gpios = <&gpio GPIODV_10 GPIO_ACTIVE_HIGH>; + hp_det_inv = <0>; + /*audio soc*/ + cpu_list = <&cpudai0 &cpudai1 &cpudai2>; + codec_list = <&codec0 &codec1 &codec2>; + plat_list = <&i2s_plat &i2s_plat &pcm_plat>; + cpudai0: cpudai0 { + sound-dai = <&i2s_dai>; + }; + cpudai1: cpudai1 { + sound-dai = <&spdif_dai>; + }; + cpudai2: cpudai2 { + sound-dai = <&pcm_dai>; + }; + codec0: codec0 { + sound-dai = <&amlogic_codec>; + }; + codec1: codec1 { + sound-dai = <&spdif_codec>; + }; + codec2: codec2 { + sound-dai = <&pcm_codec>; + }; + Channel_Mask { + /*i2s has 4 pins, 8channel, mux output*/ + DAC0_Channel_Mask = "i2s_2/3"; + }; + }; + + amaudio2 { + compatible = "amlogic, aml_amaudio2"; + status = "okay"; + interrupts = <0 48 1>; + }; + /* end of AUDIO_RELATED */ + + wifi { + compatible = "amlogic, aml_wifi"; + status = "okay"; + power_on_pin = <&gpio_ao GPIOAO_5 GPIO_ACTIVE_HIGH>; + }; +}; /* end of / */ + +&pinctrl_periphs { + /* start AUDIO_RELATED */ + /*i2s*/ + aml_audio_i2s: aml_audio_i2s { + mux { + groups = "i2s_amclk_z", + "i2s_aoclk_out_z", + "i2s_lrclk_out_z" + /*,"i2s_out_ch01_z"*/ + ,"i2s_out_ch23" + ; + function = "i2s"; + }; + }; + + /*spdif*/ + audio_spdif_out_pins: audio_spdif_out_pins { + mux { + groups = "spdif_out"; + function = "spdif_out"; + }; + }; + + /*pcm*/ + aml_audio_pcm: aml_audio_pcm { + mux { + groups = + "pcm_clk_a", + "pcm_fs_a", + "pcm_in_a", + "pcm_out_a"; + function = "pcm_a"; + }; + }; + /* end AUDIO_RELATED */ + + /*lcd_extern*/ + lcd_extern_off_pins:lcd_extern_off_pin { + mux { + pins = "GPIOH_2", + "GPIOH_3"; + function = "gpio_periphs"; + /*output-high;*/ + output-low; + /*input-enable;*/ + }; + }; + + /*backlight*/ + bl_pwm_off_pins:bl_pwm_off_pin { + mux { + pins = "GPIOZ_6"; + function = "gpio_periphs"; + output-low; + }; + }; + bl_pwm_combo_off_pins:bl_pwm_combo_off_pin { + mux { + pins = "GPIOZ_6", + "GPIOZ_7"; + function = "gpio_periphs"; + output-low; + }; + }; +}; + +&i2c1 { + status = "okay"; + clock-frequency = <300000>; + pinctrl-names="default"; + pinctrl-0=<&i2c1_dv_pins>; +}; + +&i2c2 { + status = "disabled"; + pinctrl-names="default"; + pinctrl-0=<&i2c2_h_pins>; + + lcd_extern_i2c0: lcd_extern_i2c@0 { + compatible = "lcd_ext, i2c"; + dev_name = "i2c_T5800Q"; + reg = <0x1c>; + status = "disabled"; + }; +}; + +&dwc3 { + status = "okay"; +}; + +&usb2_phy { + status = "okay"; +}; + +&usb3_phy { + status = "okay"; +}; + +&dwc2_a { + status = "okay"; + /** 0: normal, 1: otg+dwc3 host only, 2: otg+dwc3 device only*/ + controller-type = <1>; +}; + +&audio_data{ + status = "okay"; +}; + +&pwm_ab { + status = "okay"; +}; + +&pwm_cd { + status = "okay"; +}; + +ðmac { + status = "okay"; +}; + diff --git a/arch/arm/boot/dts/amlogic/txl_t960_p346.dts b/arch/arm/boot/dts/amlogic/txl_t960_p346.dts new file mode 100644 index 000000000000..454b1f112f5f --- /dev/null +++ b/arch/arm/boot/dts/amlogic/txl_t960_p346.dts @@ -0,0 +1,1139 @@ +/* + * arch/arm/boot/dts/amlogic/txl_t960_p346.dts + * + * Copyright (C) 2018 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +/dts-v1/; + +#include "mesontxl.dtsi" +#include "partition_tv_4G.dtsi" +#include "mesontxl_p321-panel.dtsi" + +/ { + model = "Amlogic TXL T960 P346 Reference Board"; + compatible = "amlogic, txl_t960_p346"; + amlogic-dt-id = "txl_p346_v1"; + + aliases { + serial0 = &uart_AO; + serial1 = &uart_A; + serial2 = &uart_B; + serial3 = &uart_C; + serial4 = &uart_AO_B; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c_AO; + }; + + ion_dev { + compatible = "amlogic, ion_dev"; + memory-region = <&ion_reserved>; + }; + + memory@00000000 { + device_type = "memory"; + linux,usable-memory = <0x100000 0x3ff00000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + /* global autoconfigured region for contiguous allocations */ + + defendkey_reserved:linux,defendkey { + compatible = "amlogic, defendkey"; + reg = <0x08300000 0x100000>; + }; + + secmon_reserved:linux,secmon { + compatible = "shared-dma-pool"; + reusable; + size = <0x400000>; + alignment = <0x400000>; + alloc-ranges = <0x05000000 0x400000>; + }; + + secos_reserved:linux,secos { + compatible = "amlogic, aml_secos_memory"; + status = "disable"; + reg = <0x05300000 0x2000000>; + no-map; + }; + + logo_reserved:linux,meson-fb { + compatible = "shared-dma-pool"; + reusable; + size = <0x800000>; + alignment = <0x400000>; + alloc-ranges = <0x3f800000 0x800000>; + }; + + ion_reserved:linux,ion-dev { + compatible = "shared-dma-pool"; + reusable; + // if no direct render, ion size = fb0_size x 3 + fb1_size + 4 M + size = <0x2400000>; + alignment = <0x400000>; + }; + + codec_mm_cma:linux,codec_mm_cma { + compatible = "shared-dma-pool"; + reusable; + /* ion_codec_mm max can alloc size 80M*/ + size = <0xd000000>; + alignment = <0x400000>; + linux,contiguous-region; + alloc-ranges = <0x0 0x30000000>; + }; + + /* codec shared reserved */ + codec_mm_reserved:linux,codec_mm_reserved { + compatible = "amlogic, codec-mm-reserved"; + size = <0x0>; + alignment = <0x100000>; + //no-map; + }; + + //di_reserved:linux,di { + //compatible = "amlogic, di-mem"; + /* buffer_size = 3621952(yuv422 8bit) */ + /* 4179008(yuv422 10bit full pack mode) */ + /** 10x3621952=34.6M(0x23) support 8bit **/ + /** 10x4736064=45.2M(0x2e) support 12bit **/ + /** 10x4179008=40M(0x28) support 10bit **/ + //size = <0x2800000>; + //no-map; + //}; + + /*di CMA pool */ + di_cma_reserved:linux,di_cma { + compatible = "shared-dma-pool"; + reusable; + /* buffer_size = 3621952(yuv422 8bit) + * | 4736064(yuv422 10bit) + * | 4179008(yuv422 10bit full pack mode) + * 10x3621952=34.6M(0x23) support 8bit + * 10x4736064=45.2M(0x2e) support 12bit + * 10x4179008=40M(0x28) support 10bit + */ + size = <0x02800000>; + alignment = <0x400000>; + }; + + /* POST PROCESS MANAGER */ + ppmgr_reserved:linux,ppmgr { + compatible = "amlogic, ppmgr_memory"; + size = <0x0>; + }; + + picdec_cma_reserved:linux,picdec { + compatible = "shared-dma-pool"; + reusable; + size = <0x0>; + alignment = <0x0>; + linux,contiguous-region; + }; + + demod_cma_reserved:linux,demod_cma { + compatible = "shared-dma-pool"; + reusable; + /* 5M */ + size = <0x0800000>; + alignment = <0x400000>; + }; + + /* vdin0 CMA pool */ + vdin0_cma_reserved:linux,vdin0_cma { + compatible = "shared-dma-pool"; + reusable; + /* 1920x1080x2x4 =16+4 M */ + size = <0x04000000>; + alignment = <0x400000>; + }; + + /* vdin1 CMA pool */ + vdin1_cma_reserved:linux,vdin1_cma { + compatible = "shared-dma-pool"; + reusable; + /* 1920x1080x2x4 =16 M */ + size = <0x04000000>; + alignment = <0x400000>; + }; + }; /* end of reserved-memory */ + + secmon { + compatible = "amlogic, secmon"; + memory-region = <&secmon_reserved>; + in_base_func = <0x82000020>; + out_base_func = <0x82000021>; + reserve_mem_size = <0x00300000>; + }; + + gpioleds { + compatible = "gpio-leds"; + status = "disabled"; + + sys_led { + label = "sys_led"; + gpios = <&gpio_ao GPIOAO_3 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + }; + + /*for external keypad*/ + adc-keypad { + compatible = "amlogic, adc_keypad"; + status = "okay"; + key_name = "power","up", "down","enter","left","right","home"; + key_num = <7>; + io-channels = <&saradc SARADC_CH2>, + <&saradc SARADC_CH3>; + io-channel-names = "key-chan-2", "key-chan-3"; + key_chan = ; + key_code = <116 103 108 28 105 106 102>; + key_val = <0 143 266 389 512 143 266>; //val=voltage/1800mV*1023 + key_tolerance = <40 40 40 40 40 40 40>; + }; + + avin_detect { + compatible = "amlogic, avin_detect"; + status = "okay"; + avin_device_num = <2>; + gpios = <&gpio GPIODV_8 GPIO_ACTIVE_HIGH>, + <&gpio GPIODV_6 GPIO_ACTIVE_HIGH>; + detect_interval_length = <100>; + set_detect_times = <5>; + set_fault_tolerance = <1>; + }; + + meson-fb { + compatible = "amlogic, meson-txl"; + memory-region = <&logo_reserved>; + dev_name = "meson-fb"; + status = "okay"; + interrupts = <0 3 1 + 0 89 1>; + interrupt-names = "viu-vsync", "rdma"; + mem_size = <0x00800000 0x01800000 0x00100000>; + /* uboot logo,fb0/fb1 memory size,if afbcd fb0=0x01851000*/ + display_mode_default = "1080p60hz"; + /* 0:VPU free scale 1:OSD free scale 2:OSD super scale */ + scale_mode = <1>; + /* 1920*1080*4*3 = 0x17BB000 */ + display_size_default = <1920 1080 1920 3240 32>; + pxp_mode = <0>; /** 0:normal mode 1:pxp mode */ + logo_addr = "0x3f800000"; + }; + + picdec { + compatible = "amlogic, picdec"; + status = "okay"; + memory-region = <&picdec_cma_reserved>; + }; + + ppmgr { + compatible = "amlogic, ppmgr"; + status = "okay"; + memory-region = <&ppmgr_reserved>; + }; + + deinterlace { + compatible = "amlogic, deinterlace"; + status = "okay"; + /* 0:use reserved; 1:use cma; 2:use cma as reserved */ + flag_cma = <1>; + //memory-region = <&di_reserved>; + memory-region = <&di_cma_reserved>; + interrupts = <0 46 1 + 0 6 1>; + interrupt-names = "de_irq"; + clocks = <&clkc CLKID_VPU_MUX>, + <&clkc CLKID_FCLK_DIV4>, + <&clkc CLKID_VPU_CLKB_TMP_COMP>, + <&clkc CLKID_VPU_CLKB_COMP>; + clock-names = "vpu_mux", + "fclk_div4", + "vpu_clkb_tmp_composite", + "vpu_clkb_composite"; + clock-range = <333 333>; + /* buffer-size = <3621952>;(yuv422 8bit) */ + buffer-size = <4179008>;/*yuv422 fullpack*/ + /* reserve-iomap = "true"; */ + /* if enable nr10bit, set nr10bit-support to 1 */ + nr10bit-support = <1>; + }; + + ionvideo { + compatible = "amlogic, ionvideo"; + dev_name = "ionvideo"; + status = "okay"; + }; + + hdmirx { + compatible = "amlogic, hdmirx-txl"; + status = "okay"; + #address-cells=<1>; + #size-cells=<1>; + dev_name = "hdmirx"; + pinctrl-names = "hdmirx_pins"; + pinctrl-0 = <&hdmirx_a_mux &hdmirx_b_mux + &hdmirx_c_mux>; + repeat = <0>; + interrupts = <0 56 1>; + clocks = <&clkc CLKID_HDMIRX_MODET_COMP>, + <&clkc CLKID_HDMIRX_CFG_COMP>, + <&clkc CLKID_HDMIRX_ACR_COMP>, + <&clkc CLKID_HDMIRX_AUDMEAS_COMP>, + <&xtal>, + <&clkc CLKID_FCLK_DIV5>, + <&clkc CLKID_FCLK_DIV7>, + <&clkc CLKID_HDCP22_SKP_COMP>, + <&clkc CLKID_HDCP22_ESM_COMP>; + //<&clkc CLK_AUD_PLL2FS>, + //<&clkc CLK_AUD_PLL4FS>, + //<&clkc CLK_AUD_OUT>; + clock-names = "hdmirx_modet_clk", + "hdmirx_cfg_clk", + "hdmirx_acr_ref_clk", + "hdmirx_audmeas_clk", + "xtal", + "fclk_div5", + "fclk_div7", + "hdcp_rx22_skp", + "hdcp_rx22_esm"; + //"hdmirx_aud_pll2fs", + //"hdmirx_aud_pll4f", + //"clk_aud_out"; + hdmirx_id = <0>; + en_4k_2_2k = <0>; + hpd_low_cec_off = <1>; + /* bit4: enable feature, bit3~0: port number */ + disable_port = <0x0>; + reg = <0xc0800000 0xa00000 + 0xC883C000 0x2000 + 0xd0076000 0x2000 + 0xc883e000 0x2000 + 0xda83e000 0x2000 + 0xc8834000 0x2000 + 0xda846000 0x2000>; + }; + + vdin@0 { + compatible = "amlogic, vdin"; + /*memory-region = <&vdin0_cma_reserved>;*/ + dev_name = "vdin0"; + status = "okay"; + reserve-iomap = "true"; + /*bit0:(1:share with codec_mm;0:cma alone)*/ + /*bit8:(1:alloc in discontinus way;0:alone in continuous way)*/ + flag_cma = <0x101>; + /* MByte, if 10bit disable: 64M(YUV422), + * if 10bit enable: 64*1.5 = 96M(YUV422) + * if support 4K2K-YUV444-10bit-WR:3840*2160*4*4 ~= 128M + * if support 4K2K-YUV444-10bit-WR:3840*2160*4*6 ~= 190M + * if support 4K2K-YUV422-10bit-wr:3840*2160*3*4 ~= 96M + * if support 4K2K-YUV422-8BIT-WR:3840*2160*2*4 ~= 64M + * if support 1080p-YUV422-8BIT-WR:1920*1080*2*4 ~= 16M + */ + cma_size = <190>; + interrupts = <0 83 1>; + rdma-irq = <2>; + clocks = <&clkc CLKID_FCLK_DIV5>, + <&clkc CLKID_VDIN_MEAS_COMP>; + clock-names = "fclk_div5", "cts_vdin_meas_clk"; + vdin_id = <0>; + /* vdin write mem color depth support: + * bit0:support 8bit + * bit1:support 9bit + * bit2:support 10bit + * bit3:support 12bit + * bit4:support yuv422 10bit full pack mode (from txl new add) + * bit8:use 8bit at 4k_50/60hz_10bit + * bit9:use 10bit at 4k_50/60hz_10bit + */ + tv_bit_mode = <0x215>; + }; + + vdin@1 { + compatible = "amlogic, vdin"; + status = "okay"; + memory-region = <&vdin1_cma_reserved>; + dev_name = "vdin1"; + reserve-iomap = "true"; + flag_cma = <0>;/*1:share with codec_mm;0:cma alone*/ + interrupts = <0 85 1>; + rdma-irq = <4>; + clocks = <&clkc CLKID_FCLK_DIV5>, + <&clkc CLKID_VDIN_MEAS_COMP>; + clock-names = "fclk_div5", "cts_vdin_meas_clk"; + vdin_id = <1>; + /* vdin write mem color depth support: + * bit0:support 8bit + * bit1:support 9bit + * bit2:support 10bit + * bit3:support 12bit + */ + tv_bit_mode = <21>; + }; + + tvafe:tvafe@c8842000 { + compatible = "amlogic, tvafe-txl"; + status = "okay"; + /*memory-region = <&tvafe_cma_reserved>;*/ + dev_name = "tvafe"; + flag_cma = <1>;/*1:share with codec_mm;0:cma alone*/ + cma_size = <5>;/*MByte*/ + reg = <0xc8842000 0x2000>;/*tvafe reg base*/ + reserve-iomap = "true"; + tvafe_id = <0>; + //pinctrl-names = "default"; + /*!!particular sequence, no more and no less!!!*/ + tvafe_pin_mux = < + 3 /* TVAFE_CVBS_IN2, CVBS_IN0 = 0 */ + 1 /* TVAFE_CVBS_IN0, CVBS_IN1 */ + 2 /* TVAFE_CVBS_IN1, CVBS_IN2 */ + 4 /* TVAFE_CVBS_IN3, CVBS_IN3 */ + >; + clocks = <&clkc CLKID_DAC_CLK>; + clock-names = "vdac_clk_gate"; + }; + + vecm { + compatible = "amlogic, vecm"; + dev_name = "aml_vecm"; + status = "okay"; + gamma_en = <1>;/*1:enabel ;0:disable*/ + wb_en = <1>;/*1:enabel ;0:disable*/ + cm_en = <1>;/*1:enabel ;0:disable*/ + wb_sel = <1>;/*1:mtx ;0:gainoff*/ + vlock_en = <1>;/*1:enable;0:disable*/ + vlock_mode = <0x4>; + /* vlock work mode: + *bit0:auto ENC + *bit1:auto PLL + *bit2:manual PLL + *bit3:manual ENC + *bit4:manual soft ENC + *bit5:manual MIX PLL ENC + */ + vlock_pll_m_limit = <1>; + vlock_line_limit = <3>; + }; + + tuner: tuner { + status = "okay"; + tuner_name = "r842_tuner"; + tuner_i2c_adap = <&i2c1>; + tuner_i2c_addr = <0xf6>; + tuner_xtal = <1>; /* 0: 16MHz, 1: 24MHz, 3: 27MHz */ + tuner_xtal_mode = <3>; + /* NO_SHARE_XTAL(0) + * MASTER_TO_SLAVE_XTAL_IN(1) + * MASTER_TO_SLAVE_XTAL_OUT(2) + * SLAVE_XTAL_OUT(3) + */ + tuner_xtal_cap = <0>; /* 0 ~ 41 (pf) */ + }; + + atv-demod { + compatible = "amlogic, atv-demod"; + status = "okay"; + tuner = <&tuner>; + btsc_sap_mode = <1>; + pinctrl-names = "atvdemod_agc_pins"; + pinctrl-0 = <&atvdemod_agc_pins>; + reg = <0xc8840000 0x2000 /* demod reg */ + 0xc883c000 0x2000 /* hiu reg */ + 0xc8834000 0x2000>; /* periphs reg */ + reg_23cf = <0x88188832>; + /*default:0x88188832;r840 on haier:0x48188832*/ + }; + + sd_emmc_c: emmc@d0074000 { + compatible = "amlogic, meson-mmc-txl"; + status = "okay"; + reg = <0xd0074000 0x2000>; + interrupts = <0 218 1>; + pinctrl-names = "emmc_clk_cmd_pins", "emmc_all_pins"; + pinctrl-0 = <&emmc_clk_cmd_pins>; + pinctrl-1 = <&emmc_conf_pull_up &emmc_conf_pull_done>; + clocks = <&clkc CLKID_SD_EMMC_C>, + <&clkc CLKID_SD_EMMC_C_COMP>, + <&clkc CLKID_FCLK_DIV2>; + clock-names = "core", "clkin0", "clkin1"; + + bus-width = <8>; + cap-sd-highspeed; + cap-mmc-highspeed; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + + max-frequency = <200000000>; + non-removable; + disable-wp; + emmc { + pinname = "emmc"; + ocr_avail = <0x200080>; /**VDD voltage 3.3 ~ 3.4 */ + caps = "MMC_CAP_8_BIT_DATA", + "MMC_CAP_MMC_HIGHSPEED", + "MMC_CAP_SD_HIGHSPEED", + "MMC_CAP_NONREMOVABLE", + "MMC_CAP_1_8V_DDR", + "MMC_CAP_HW_RESET", + "MMC_CAP_ERASE", + "MMC_CAP_CMD23"; + caps2 = "MMC_CAP2_HS200"; + f_min = <400000>; + f_max = <100000000>; + max_req_size = <0x20000>; /**128KB*/ + gpio_dat3 = <&gpio BOOT_3 GPIO_ACTIVE_HIGH>; + hw_reset = <&gpio BOOT_9 GPIO_ACTIVE_HIGH>; + tx_phase = <3>; + card_type = <1>; + /* 1:mmc card(include eMMC), + * 2:sd card(include tSD) + */ + }; + }; + + sd_emmc_b:sd@d0072000 { + compatible = "amlogic, meson-mmc-txl"; + status = "okay"; + reg = <0xd0072000 0x2000>; + interrupts = <0 217 1>; + pinctrl-names = "sd_all_pins", + "sd_clk_cmd_pins", + "sd_1bit_pins", + "sd_clk_cmd_uart_pins", + "sd_1bit_uart_pins", + "sd_to_ao_uart_pins", + "ao_to_sd_uart_pins", + "ao_to_sd_jtag_pins", + "sd_to_ao_jtag_pins"; + pinctrl-0 = <&sd_all_pins>; + pinctrl-1 = <&sd_clk_cmd_pins>; + pinctrl-2 = <&sd_1bit_pins>; + pinctrl-3 = <&sd_to_ao_uart_clr_pins + &sd_clk_cmd_pins &ao_to_sd_uart_pins>; + pinctrl-4 = <&sd_to_ao_uart_clr_pins + &sd_1bit_pins &ao_to_sd_uart_pins>; + pinctrl-5 = <&sd_all_pins &sd_to_ao_uart_pins>; + pinctrl-6 = <&sd_to_ao_uart_clr_pins &ao_to_sd_uart_pins>; + pinctrl-7 = <&sd_to_ao_uart_clr_pins &ao_to_sd_uart_pins>; + pinctrl-8 = <&sd_all_pins &sd_to_ao_uart_pins>; + clocks = <&clkc CLKID_SD_EMMC_B>, + <&clkc CLKID_SD_EMMC_B_COMP>, + <&clkc CLKID_FCLK_DIV2>; + clock-names = "core", "clkin0", "clkin1"; + + bus-width = <4>; + cap-sd-highspeed; + max-frequency = <100000000>; + disable-wp; + sd { + pinname = "sd"; + ocr_avail = <0x200080>; /**VDD voltage 3.3 ~ 3.4 */ + caps = "MMC_CAP_4_BIT_DATA", + "MMC_CAP_MMC_HIGHSPEED", + "MMC_CAP_SD_HIGHSPEED"; + /* "MMC_CAP_UHS_SDR12", + * "MMC_CAP_UHS_SDR25", + * "MMC_CAP_UHS_SDR50", + * "MMC_CAP_UHS_SDR104"; + */ + f_min = <400000>; + f_max = <100000000>; + max_req_size = <0x20000>; /**128KB*/ + gpio_dat3 = <&gpio CARD_4 GPIO_ACTIVE_HIGH>; + jtag_pin = <&gpio CARD_0 GPIO_ACTIVE_HIGH>; + gpio_cd = <&gpio CARD_6 GPIO_ACTIVE_HIGH>; + card_type = <5>; + /* 0:unknown, + * 1:mmc card(include eMMC), + * 2:sd card(include tSD), + * 3:sdio device(ie:sdio-wifi), + * 4:SD combo (IO+mem) card, + * 5:NON sdio device(means sd/mmc card), + * other:reserved + */ + }; + }; + + unifykey { + compatible = "amlogic, unifykey"; + status = "okay"; + + unifykey-num = <17>; + unifykey-index-0 = <&keysn_0>; + unifykey-index-1 = <&keysn_1>; + unifykey-index-2 = <&keysn_2>; + unifykey-index-3 = <&keysn_3>; + unifykey-index-4 = <&keysn_4>; + unifykey-index-5 = <&keysn_5>; + unifykey-index-6 = <&keysn_6>; + unifykey-index-7 = <&keysn_7>; + unifykey-index-8 = <&keysn_8>; + unifykey-index-9 = <&keysn_9>; + unifykey-index-10= <&keysn_10>; + unifykey-index-11 = <&keysn_11>; + unifykey-index-12 = <&keysn_12>; + unifykey-index-13 = <&keysn_13>; + unifykey-index-14 = <&keysn_14>; + unifykey-index-15 = <&keysn_15>; + unifykey-index-16 = <&keysn_16>; + + keysn_0: key_0{ + key-name = "usid"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_1:key_1{ + key-name = "mac"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_2:key_2{ + key-name = "hdcp"; + key-device = "secure"; + key-type = "sha1"; + key-permit = "read","write","del"; + }; + keysn_3:key_3{ + key-name = "secure_boot_set"; + key-device = "efuse"; + key-permit = "write"; + }; + keysn_4:key_4{ + key-name = "mac_bt"; + key-device = "normal"; + key-permit = "read","write","del"; + key-type = "mac"; + }; + keysn_5:key_5{ + key-name = "mac_wifi"; + key-device = "normal"; + key-permit = "read","write","del"; + key-type = "mac"; + }; + keysn_6:key_6{ + key-name = "hdcp2_tx"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_7:key_7{ + key-name = "hdcp2_rx"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_8:key_8{ + key-name = "widevinekeybox"; + key-device = "secure"; + key-type = "sha1"; + key-permit = "read","write","del"; + }; + keysn_9:key_9{ + key-name = "deviceid"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_10:key_10{ + key-name = "hdcp22_fw_private"; + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_11:key_11{ + key-name = "hdcp22_rx_private"; + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_12:key_12{ + key-name = "hdcp22_rx_fw"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_13:key_13{ + key-name = "hdcp14_rx"; + key-device = "normal"; + key-type = "sha1"; + key-permit = "read","write","del"; + }; + keysn_14:key_14{ + key-name = "lcd"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_15:key_15{ + key-name = "lcd_extern"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_16:key_16{ + key-name = "backlight"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + }; /* End unifykey */ + + vout { + compatible = "amlogic, vout"; + dev_name = "vout"; + status = "okay"; + fr_auto_policy = <0>; + }; + + dvb { + compatible = "amlogic, dvb"; + dev_name = "dvb"; + status = "okay"; + fe0_mode = "internal"; + fe0_tuner = <&tuner>; + + /*"parallel","serial","disable"*/ + ts2 = "parallel"; + ts2_control = <0>; + ts2_invert = <0>; + interrupts = <0 23 1 + 0 5 1 + 0 53 1 + 0 19 1 + 0 25 1 + 0 18 1 + 0 24 1>; + interrupt-names = "demux0_irq", + "demux1_irq", + "demux2_irq", + "dvr0_irq", + "dvr1_irq", + "dvrfill0_fill", + "dvrfill1_flush"; + clocks = <&clkc CLKID_DEMUX + &clkc CLKID_ASYNC_FIFO + &clkc CLKID_AHB_ARB0 + &clkc CLKID_DOS_PARSER>; + clock-names = "demux", "asyncfifo", "ahbarb0", "uparsertop"; + }; + + meson_sensor: sensor@0 { + compatible = "amlogic, aml-thermal"; + #thermal-sensor-cells = <1>; + cooling_devices { + cpufreq_cool_cluster0 { + min_state = <1000000>; + dyn_coeff = <140>; + cluster_id = <0>; + node_name = "cpus"; + device_type = "cpufreq"; + }; + cpucore_cool_cluster0 { + min_state = <1>; + dyn_coeff = <0>; + cluster_id = <0>; + node_name = "cpu_core_cluster0"; + device_type = "cpucore"; + }; + gpufreq_cool { + min_state = <400>; + dyn_coeff = <437>; + cluster_id = <0>; + node_name = "mali"; + device_type = "gpufreq"; + }; + gpucore_cool { + min_state = <1>; + dyn_coeff = <0>; + cluster_id = <0>; + node_name = "thermal_gpu_cores"; + device_type = "gpucore"; + }; + }; + cpu_cluster0:cpu_core_cluster0 { + #cooling-cells = <2>; /* min followed by max */ + }; + gpucore:thermal_gpu_cores { + #cooling-cells = <2>; /* min followed by max */ + }; + }; + + dtv-demod { + compatible = "amlogic, ddemod-txl"; + status = "okay"; + + pinctrl-names = "dtvdemod_agc_pins"; + pinctrl-0 = <&dtvdemod_agc_pins>; + + clocks = <&clkc CLKID_DAC_CLK>; + clock-names = "vdac_clk_gate"; + + reg = <0xc8844000 0x2000 /*dtv demod base*/ + 0xc883c000 0x2000 /*hiu reg base*/ + 0xc8100000 0x1000 /*io_aobus_base*/ + 0xc1104400 0x1000 /*reset*/ + >; + /*move from dvbfe*/ + dtv_demod0_mem = <0>; // need move to aml_dtv_demod ? + spectrum = <1>; + cma_flag = <1>; + cma_mem_size = <8>; + memory-region = <&demod_cma_reserved>;//<&demod_reserved>; + }; + + thermal-zones { + soc_thermal { + polling-delay = <1000>; + polling-delay-passive = <100>; + sustainable-power = <2150>; + thermal-sensors = <&meson_sensor 3>; + + trips { + switch_on: trip-point@0 { + temperature = <70000>; + hysteresis = <1000>; + type = "passive"; + }; + control: trip-point@1 { + temperature = <80000>; + hysteresis = <1000>; + type = "passive"; + }; + hot: trip-point@2 { + temperature = <85000>; + hysteresis = <5000>; + type = "hot"; + }; + critical: trip-point@3 { + temperature = <260000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + + cooling-maps { + cpufreq_cooling_map { + trip = <&control>; + cooling-device = <&cpus 0 4>; + contribution = <1024>; + }; + cpucore_cooling_map { + trip = <&control>; + cooling-device = <&cpu_cluster0 0 3>; + contribution = <1024>; + }; + gpufreq_cooling_map { + trip = <&control>; + cooling-device = <&gpu 0 4>; + contribution = <1024>; + }; + gpucore_cooling_map { + trip = <&control>; + cooling-device = <&gpucore 0 2>; + contribution = <1024>; + }; + }; + }; + }; + + /* start AUDIO_RELATED */ + i2s_dai: I2S { + #sound-dai-cells = <0>; + compatible = "amlogic, aml-i2s-dai"; + clocks = < + &clkc CLKID_MPLL3 + &clkc CLKID_AMCLK_COMP + &clkc CLKID_AIU_GLUE + &clkc CLKID_I2S_OUT + &clkc CLKID_AMCLK_MEASURE + &clkc CLKID_AIFIFO2 + &clkc CLKID_MIXER + &clkc CLKID_MIXER_IFACE + &clkc CLKID_ADC + &clkc CLKID_AIU_TOP + &clkc CLKID_AOCLK_GATE + &clkc CLKID_I2S_SPDIF + >; + clock-names = + "mpll", + "mclk", + "top_glue", + "i2s_out", + "amclk_measure", + "aififo2", + "aud_mixer", + "mixer_reg", + "adc", + "top_level", + "aoclk", + "aud_in"; + }; + + spdif_dai: SPDIF { + #sound-dai-cells = <0>; + compatible = "amlogic, aml-spdif-dai"; + clocks = < + &clkc CLKID_MPLL1 + &clkc CLKID_IEC958_INT_COMP + &clkc CLKID_AMCLK_COMP + &clkc CLKID_IEC958_MUX + &clkc CLKID_CLK81 + &clkc CLKID_IEC958 + &clkc CLKID_IEC958_GATE + >; + clock-names = + "mpll1", + "i958", + "mclk", + "spdif", + "clk_81", + "iec958", + "iec958_amclk"; + }; + + pcm_dai: PCM { + #sound-dai-cells = <0>; + compatible = "amlogic, aml-pcm-dai"; + pinctrl-names = "audio_pcm"; + /* disable pcm pin mux temporary, enable it if necessary */ + /*pinctrl-0 = <&aml_audio_pcm>;*/ + clocks = < + &clkc CLKID_MPLL0 + &clkc CLKID_PCM_MCLK_COMP + &clkc CLKID_PCM_SCLK_COMP + >; + clock-names = "mpll0", "pcm_mclk", "pcm_sclk"; + pcm_mode = <1>; /* 0=slave mode, 1=master mode */ + }; + + i2s_plat: i2s_platform { + compatible = "amlogic, aml-i2s"; + interrupts = <0 29 1>; + }; + + pcm_plat: pcm_platform { + compatible = "amlogic, aml-pcm"; + }; + + spdif_codec: spdif_codec { + #sound-dai-cells = <0>; + compatible = "amlogic, aml-spdif-codec"; + status = "okay"; + pinctrl-names = "audio_spdif_out"; + pinctrl-0 = <&audio_spdif_out_pins>; + }; + + pcm_codec: pcm_codec { + #sound-dai-cells = <0>; + compatible = "amlogic, pcm2BT-codec"; + status = "okay"; + }; + /* endof AUDIO MESON8 DEVICES */ + + /* AUDIO board specific */ + dummy_codec:dummy { + #sound-dai-cells = <0>; + compatible = "amlogic, aml_dummy_codec"; + status = "disabled"; + }; + + amlogic_codec:t9015S { + #sound-dai-cells = <0>; + compatible = "amlogic, aml_codec_T9015S"; + status = "okay"; + reg = <0xc8832000 0x14>; + }; + + aml_snd_tv { + compatible = "amlogic, txl-snd-tv"; + status = "okay"; + aml-sound-card,format = "i2s"; + aml_sound_card,name = "AML-TVAUDIO"; + pinctrl-names = "audio_i2s"; + pinctrl-0 = <&aml_audio_i2s>; + /*avout mute gpio, if av_mute_inv = 1, invert gpio*/ + mute_gpio-gpios = <&gpio GPIODV_11 GPIO_ACTIVE_LOW>; + av_mute_inv = <0>; + /*after sleep time, unmute avout*/ + sleep_time = <0>; + /*analog amp mute pinmux*/ + amp_mute_gpio-gpios = <&gpio GPIOZ_13 GPIO_ACTIVE_LOW>; + amp_mute_inv = <0>; + /* if 1, enable switch AV / HS Detect */ + av_hs_switch = <1>; + hp_det-gpios = <&gpio GPIODV_10 GPIO_ACTIVE_HIGH>; + hp_det_inv = <0>; + /*audio soc*/ + cpu_list = <&cpudai0 &cpudai1 &cpudai2>; + codec_list = <&codec0 &codec1 &codec2>; + plat_list = <&i2s_plat &i2s_plat &pcm_plat>; + cpudai0: cpudai0 { + sound-dai = <&i2s_dai>; + }; + cpudai1: cpudai1 { + sound-dai = <&spdif_dai>; + }; + cpudai2: cpudai2 { + sound-dai = <&pcm_dai>; + }; + codec0: codec0 { + sound-dai = <&amlogic_codec>; + }; + codec1: codec1 { + sound-dai = <&spdif_codec>; + }; + codec2: codec2 { + sound-dai = <&pcm_codec>; + }; + Channel_Mask { + /*i2s has 4 pins, 8channel, mux output*/ + DAC0_Channel_Mask = "i2s_2/3"; + }; + }; + + amaudio2 { + compatible = "amlogic, aml_amaudio2"; + status = "okay"; + interrupts = <0 48 1>; + }; + /* end of AUDIO_RELATED */ + + wifi { + compatible = "amlogic, aml_wifi"; + status = "okay"; + power_on_pin = <&gpio_ao GPIOAO_5 GPIO_ACTIVE_HIGH>; + }; +}; /* end of / */ + +&pinctrl_periphs { + /* start AUDIO_RELATED */ + /*i2s*/ + aml_audio_i2s: aml_audio_i2s { + mux { + groups = "i2s_amclk_z", + "i2s_aoclk_out_z", + "i2s_lrclk_out_z" + /*,"i2s_out_ch01_z"*/ + ,"i2s_out_ch23" + ; + function = "i2s"; + }; + }; + + /*spdif*/ + audio_spdif_out_pins: audio_spdif_out_pins { + mux { + groups = "spdif_out"; + function = "spdif_out"; + }; + }; + + /*pcm*/ + aml_audio_pcm: aml_audio_pcm { + mux { + groups = + "pcm_clk_a", + "pcm_fs_a", + "pcm_in_a", + "pcm_out_a"; + function = "pcm_a"; + }; + }; + /* end AUDIO_RELATED */ + + /*lcd_extern*/ + lcd_extern_off_pins:lcd_extern_off_pin { + mux { + pins = "GPIOH_2", + "GPIOH_3"; + function = "gpio_periphs"; + /*output-high;*/ + output-low; + /*input-enable;*/ + }; + }; + + /*backlight*/ + bl_pwm_off_pins:bl_pwm_off_pin { + mux { + pins = "GPIOZ_6"; + function = "gpio_periphs"; + output-low; + }; + }; + bl_pwm_combo_off_pins:bl_pwm_combo_off_pin { + mux { + pins = "GPIOZ_6", + "GPIOZ_7"; + function = "gpio_periphs"; + output-low; + }; + }; +}; + +&i2c1 { + status = "okay"; + clock-frequency = <300000>; + pinctrl-names="default"; + pinctrl-0=<&i2c1_dv_pins>; +}; + +&i2c2 { + status = "disabled"; + pinctrl-names="default"; + pinctrl-0=<&i2c2_h_pins>; + + lcd_extern_i2c0: lcd_extern_i2c@0 { + compatible = "lcd_ext, i2c"; + dev_name = "i2c_T5800Q"; + reg = <0x1c>; + status = "disabled"; + }; +}; + +&dwc3 { + status = "okay"; +}; + +&usb2_phy { + status = "okay"; +}; + +&usb3_phy { + status = "okay"; +}; + +&dwc2_a { + status = "okay"; + /** 0: normal, 1: otg+dwc3 host only, 2: otg+dwc3 device only*/ + controller-type = <1>; +}; + +&audio_data{ + status = "okay"; +}; + +&pwm_ab { + status = "okay"; +}; + +&pwm_cd { + status = "okay"; +}; + +ðmac { + status = "okay"; +}; + diff --git a/arch/arm/boot/dts/amlogic/txl_t962_p320.dts b/arch/arm/boot/dts/amlogic/txl_t962_p320.dts new file mode 100644 index 000000000000..154b9f41532c --- /dev/null +++ b/arch/arm/boot/dts/amlogic/txl_t962_p320.dts @@ -0,0 +1,1148 @@ +/* + * arch/arm/boot/dts/amlogic/txl_t962_320.dts + * + * Copyright (C) 2018 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +/dts-v1/; + +#include "mesontxl.dtsi" +#include "partition_mbox_normal.dtsi" +#include "mesontxl_p321-panel.dtsi" + +/ { + model = "Amlogic TXL T962 P320 Development Board"; + compatible = "amlogic, txl_t962_p320"; + amlogic-dt-id = "txl_p320_v1"; + + aliases { + serial0 = &uart_AO; + serial1 = &uart_A; + serial2 = &uart_B; + serial3 = &uart_C; + serial4 = &uart_AO_B; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c_AO; + }; + + ion_dev { + compatible = "amlogic, ion_dev"; + memory-region = <&ion_reserved>; + }; + + memory@00000000 { + device_type = "memory"; + linux,usable-memory = <0x100000 0x7ff00000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + /* global autoconfigured region for contiguous allocations */ + + defendkey_reserved:linux,defendkey { + compatible = "amlogic, defendkey"; + reg = <0x08300000 0x100000>; + }; + + secmon_reserved:linux,secmon { + compatible = "shared-dma-pool"; + reusable; + size = <0x400000>; + alignment = <0x400000>; + alloc-ranges = <0x05000000 0x400000>; + }; + + secos_reserved:linux,secos { + compatible = "amlogic, aml_secos_memory"; + status = "disable"; + reg = <0x05300000 0x2000000>; + no-map; + }; + + logo_reserved:linux,meson-fb { + compatible = "shared-dma-pool"; + reusable; + size = <0x800000>; + alignment = <0x400000>; + alloc-ranges = <0x3f800000 0x800000>; + }; + + ion_reserved:linux,ion-dev { + compatible = "shared-dma-pool"; + reusable; + // if no direct render, ion size = fb0_size x 3 + fb1_size + 4 M + size = <0x2400000>; + alignment = <0x400000>; + }; + + codec_mm_cma:linux,codec_mm_cma { + compatible = "shared-dma-pool"; + reusable; + /* ion_codec_mm max can alloc size 80M*/ + size = <0x13400000>; + alignment = <0x400000>; + linux,contiguous-region; + }; + + /* codec shared reserved */ + codec_mm_reserved:linux,codec_mm_reserved { + compatible = "amlogic, codec-mm-reserved"; + size = <0x0>; + alignment = <0x100000>; + //no-map; + }; + + //di_reserved:linux,di { + //compatible = "amlogic, di-mem"; + /* buffer_size = 3621952(yuv422 8bit) */ + /* 4179008(yuv422 10bit full pack mode) */ + /** 10x3621952=34.6M(0x23) support 8bit **/ + /** 10x4736064=45.2M(0x2e) support 12bit **/ + /** 10x4179008=40M(0x28) support 10bit **/ + //size = <0x2800000>; + //no-map; + //}; + + /*di CMA pool */ + di_cma_reserved:linux,di_cma { + compatible = "shared-dma-pool"; + reusable; + /* buffer_size = 3621952(yuv422 8bit) + * | 4736064(yuv422 10bit) + * | 4179008(yuv422 10bit full pack mode) + * 10x3621952=34.6M(0x23) support 8bit + * 10x4736064=45.2M(0x2e) support 12bit + * 10x4179008=40M(0x28) support 10bit + */ + size = <0x02800000>; + alignment = <0x400000>; + }; + + /* POST PROCESS MANAGER */ + ppmgr_reserved:linux,ppmgr { + compatible = "amlogic, ppmgr_memory"; + size = <0x0>; + }; + + picdec_cma_reserved:linux,picdec { + compatible = "shared-dma-pool"; + reusable; + size = <0x0>; + alignment = <0x0>; + linux,contiguous-region; + }; + + demod_cma_reserved:linux,demod_cma { + compatible = "shared-dma-pool"; + reusable; + /* 5M */ + size = <0x0800000>; + alignment = <0x400000>; + }; + + /* vdin1 CMA pool */ + vdin1_cma_reserved:linux,vdin1_cma { + compatible = "shared-dma-pool"; + reusable; + /* 1920x1080x2x4 =16+4 M */ + size = <0x04000000>; + alignment = <0x400000>; + }; + }; /* end of reserved-memory */ + + secmon { + compatible = "amlogic, secmon"; + memory-region = <&secmon_reserved>; + in_base_func = <0x82000020>; + out_base_func = <0x82000021>; + reserve_mem_size = <0x00300000>; + }; + + gpioleds { + compatible = "gpio-leds"; + status = "disabled"; + + sys_led { + label = "sys_led"; + gpios = <&gpio_ao GPIOAO_3 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + }; + + /*for external keypad*/ + adc-keypad { + compatible = "amlogic, adc_keypad"; + status = "okay"; + key_name = "power","up", "down","enter","left","right"; + key_num = <6>; + io-channels = <&saradc SARADC_CH2>, + <&saradc SARADC_CH3>; + io-channel-names = "key-chan-2", "key-chan-3"; + key_chan = ; + key_code = <116 103 108 28 105 106>; + key_val = <0 143 266 0 143 266>; //val=voltage/1800mV*1023 + key_tolerance = <40 40 40 40 40 40>; + }; + + avin_detect { + compatible = "amlogic, avin_detect"; + status = "okay"; + avin_device_num = <2>; + gpios = <&gpio GPIODV_8 GPIO_ACTIVE_HIGH>, + <&gpio GPIODV_10 GPIO_ACTIVE_HIGH>; + detect_interval_length = <100>; + set_detect_times = <5>; + set_fault_tolerance = <1>; + }; + + meson-fb { + compatible = "amlogic, meson-txl"; + memory-region = <&logo_reserved>; + dev_name = "meson-fb"; + status = "okay"; + interrupts = <0 3 1 + 0 89 1>; + interrupt-names = "viu-vsync", "rdma"; + mem_size = <0x00800000 0x01800000 0x00100000>; + /* uboot logo,fb0/fb1 memory size,if afbcd fb0=0x01851000*/ + display_mode_default = "1080p60hz"; + /* 0:VPU free scale 1:OSD free scale 2:OSD super scale */ + scale_mode = <1>; + /* 1920*1080*4*3 = 0x17BB000 */ + display_size_default = <1920 1080 1920 3240 32>; + pxp_mode = <0>; /** 0:normal mode 1:pxp mode */ + logo_addr = "0x3f800000"; + }; + + picdec { + compatible = "amlogic, picdec"; + status = "okay"; + memory-region = <&picdec_cma_reserved>; + }; + + ppmgr { + compatible = "amlogic, ppmgr"; + status = "okay"; + memory-region = <&ppmgr_reserved>; + }; + + deinterlace { + compatible = "amlogic, deinterlace"; + status = "okay"; + /* 0:use reserved; 1:use cma; 2:use cma as reserved */ + flag_cma = <1>; + //memory-region = <&di_reserved>; + memory-region = <&di_cma_reserved>; + interrupts = <0 46 1 + 0 6 1>; + interrupt-names = "de_irq"; + clocks = <&clkc CLKID_VPU_MUX>, + <&clkc CLKID_FCLK_DIV4>, + <&clkc CLKID_VPU_CLKB_TMP_COMP>, + <&clkc CLKID_VPU_CLKB_COMP>; + clock-names = "vpu_mux", + "fclk_div4", + "vpu_clkb_tmp_composite", + "vpu_clkb_composite"; + clock-range = <333 333>; + /* buffer-size = <3621952>;(yuv422 8bit) */ + buffer-size = <4179008>;/*yuv422 fullpack*/ + /* reserve-iomap = "true"; */ + /* if enable nr10bit, set nr10bit-support to 1 */ + nr10bit-support = <1>; + }; + + ionvideo { + compatible = "amlogic, ionvideo"; + dev_name = "ionvideo"; + status = "okay"; + }; + + hdmirx { + compatible = "amlogic, hdmirx-txl"; + status = "okay"; + #address-cells=<1>; + #size-cells=<1>; + dev_name = "hdmirx"; + pinctrl-names = "hdmirx_pins"; + pinctrl-0 = <&hdmirx_a_mux &hdmirx_b_mux + &hdmirx_c_mux>; + repeat = <0>; + interrupts = <0 56 1>; + clocks = <&clkc CLKID_HDMIRX_MODET_COMP>, + <&clkc CLKID_HDMIRX_CFG_COMP>, + <&clkc CLKID_HDMIRX_ACR_COMP>, + <&clkc CLKID_HDMIRX_AUDMEAS_COMP>, + <&xtal>, + <&clkc CLKID_FCLK_DIV5>, + <&clkc CLKID_FCLK_DIV7>, + <&clkc CLKID_HDCP22_SKP_COMP>, + <&clkc CLKID_HDCP22_ESM_COMP>; + //<&clkc CLK_AUD_PLL2FS>, + //<&clkc CLK_AUD_PLL4FS>, + //<&clkc CLK_AUD_OUT>; + clock-names = "hdmirx_modet_clk", + "hdmirx_cfg_clk", + "hdmirx_acr_ref_clk", + "hdmirx_audmeas_clk", + "xtal", + "fclk_div5", + "fclk_div7", + "hdcp_rx22_skp", + "hdcp_rx22_esm"; + //"hdmirx_aud_pll2fs", + //"hdmirx_aud_pll4f", + //"clk_aud_out"; + hdmirx_id = <0>; + en_4k_2_2k = <0>; + hpd_low_cec_off = <1>; + /* bit4: enable feature, bit3~0: port number */ + disable_port = <0x0>; + reg = <0xc0800000 0xa00000 + 0xC883C000 0x2000 + 0xd0076000 0x2000 + 0xc883e000 0x2000 + 0xda83e000 0x2000 + 0xc8834000 0x2000 + 0xda846000 0x2000>; + }; + + vdin@0 { + compatible = "amlogic, vdin"; + /*memory-region = <&vdin0_cma_reserved>;*/ + dev_name = "vdin0"; + status = "okay"; + reserve-iomap = "true"; + /*bit0:(1:share with codec_mm;0:cma alone)*/ + /*bit8:(1:alloc in discontinus way;0:alone in continuous way)*/ + flag_cma = <0x101>; + /* MByte, if 10bit disable: 64M(YUV422), + * if 10bit enable: 64*1.5 = 96M(YUV422) + * if support 4K2K-YUV444-10bit-WR:3840*2160*4*4 ~= 128M + * if support 4K2K-YUV444-10bit-WR:3840*2160*4*6 ~= 190M + * if support 4K2K-YUV422-10bit-wr:3840*2160*3*4 ~= 96M + * if support 4K2K-YUV422-8BIT-WR:3840*2160*2*4 ~= 64M + * if support 1080p-YUV422-8BIT-WR:1920*1080*2*4 ~= 16M + */ + cma_size = <190>; + interrupts = <0 83 1>; + rdma-irq = <2>; + clocks = <&clkc CLKID_FCLK_DIV5>, + <&clkc CLKID_VDIN_MEAS_COMP>; + clock-names = "fclk_div5", "cts_vdin_meas_clk"; + vdin_id = <0>; + /* vdin write mem color depth support: + * bit0:support 8bit + * bit1:support 9bit + * bit2:support 10bit + * bit3:support 12bit + * bit4:support yuv422 10bit full pack mode (from txl new add) + * bit8:use 8bit at 4k_50/60hz_10bit + * bit9:use 10bit at 4k_50/60hz_10bit + */ + tv_bit_mode = <0x215>; + }; + + vdin@1 { + compatible = "amlogic, vdin"; + status = "okay"; + memory-region = <&vdin1_cma_reserved>; + dev_name = "vdin1"; + reserve-iomap = "true"; + flag_cma = <0>;/*1:share with codec_mm;0:cma alone*/ + interrupts = <0 85 1>; + rdma-irq = <4>; + clocks = <&clkc CLKID_FCLK_DIV5>, + <&clkc CLKID_VDIN_MEAS_COMP>; + clock-names = "fclk_div5", "cts_vdin_meas_clk"; + vdin_id = <1>; + /* vdin write mem color depth support: + * bit0:support 8bit + * bit1:support 9bit + * bit2:support 10bit + * bit3:support 12bit + */ + tv_bit_mode = <21>; + }; + + tvafe:tvafe@c8842000 { + compatible = "amlogic, tvafe-txl"; + status = "okay"; + /*memory-region = <&tvafe_cma_reserved>;*/ + dev_name = "tvafe"; + flag_cma = <1>;/*1:share with codec_mm;0:cma alone*/ + cma_size = <5>;/*MByte*/ + reg = <0xc8842000 0x2000>;/*tvafe reg base*/ + reserve-iomap = "true"; + tvafe_id = <0>; + //pinctrl-names = "default"; + /*!!particular sequence, no more and no less!!!*/ + tvafe_pin_mux = < + 3 /* TVAFE_CVBS_IN2, CVBS_IN0 = 0 */ + 1 /* TVAFE_CVBS_IN0, CVBS_IN1 */ + 2 /* TVAFE_CVBS_IN1, CVBS_IN2 */ + 4 /* TVAFE_CVBS_IN3, CVBS_IN3 */ + >; + clocks = <&clkc CLKID_DAC_CLK>; + clock-names = "vdac_clk_gate"; + }; + + vecm { + compatible = "amlogic, vecm"; + dev_name = "aml_vecm"; + status = "okay"; + gamma_en = <1>;/*1:enabel ;0:disable*/ + wb_en = <1>;/*1:enabel ;0:disable*/ + cm_en = <1>;/*1:enabel ;0:disable*/ + wb_sel = <1>;/*1:mtx ;0:gainoff*/ + vlock_en = <1>;/*1:enable;0:disable*/ + vlock_mode = <0x4>; + /* vlock work mode: + *bit0:auto ENC + *bit1:auto PLL + *bit2:manual PLL + *bit3:manual ENC + *bit4:manual soft ENC + *bit5:manual MIX PLL ENC + */ + vlock_pll_m_limit = <1>; + vlock_line_limit = <3>; + }; + + tuner: tuner { + status = "okay"; + tuner_name = "si2151_tuner"; + tuner_i2c_adap = <&i2c1>; + tuner_i2c_addr = <0x60>; + /* tuner_xtal = <0>; */ /* unuse for si2151 */ + /* tuner_xtal_mode = <0>; */ + /* tuner_xtal_cap = <0>; */ + }; + + atv-demod { + compatible = "amlogic, atv-demod"; + status = "okay"; + tuner = <&tuner>; + btsc_sap_mode = <1>; + /* pinctrl-names = "atvdemod_agc_pins"; */ + /* pinctrl-0 = <&atvdemod_agc_pins>; */ + reg = <0xc8840000 0x2000 /* demod reg */ + 0xc883c000 0x2000 /* hiu reg */ + 0xc8834000 0x2000>; /* periphs reg */ + reg_23cf = <0x88188832>; + /*default:0x88188832;r840 on haier:0x48188832*/ + }; + + sd_emmc_c: emmc@d0074000 { + compatible = "amlogic, meson-mmc-txl"; + status = "okay"; + reg = <0xd0074000 0x2000>; + interrupts = <0 218 1>; + pinctrl-names = "emmc_clk_cmd_pins", "emmc_all_pins"; + pinctrl-0 = <&emmc_clk_cmd_pins>; + pinctrl-1 = <&emmc_conf_pull_up &emmc_conf_pull_done>; + clocks = <&clkc CLKID_SD_EMMC_C>, + <&clkc CLKID_SD_EMMC_C_COMP>, + <&clkc CLKID_FCLK_DIV2>; + clock-names = "core", "clkin0", "clkin1"; + + bus-width = <8>; + cap-sd-highspeed; + cap-mmc-highspeed; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + + max-frequency = <200000000>; + non-removable; + disable-wp; + emmc { + pinname = "emmc"; + ocr_avail = <0x200080>; /**VDD voltage 3.3 ~ 3.4 */ + caps = "MMC_CAP_8_BIT_DATA", + "MMC_CAP_MMC_HIGHSPEED", + "MMC_CAP_SD_HIGHSPEED", + "MMC_CAP_NONREMOVABLE", + "MMC_CAP_1_8V_DDR", + "MMC_CAP_HW_RESET", + "MMC_CAP_ERASE", + "MMC_CAP_CMD23"; + caps2 = "MMC_CAP2_HS200"; + f_min = <400000>; + f_max = <100000000>; + max_req_size = <0x20000>; /**128KB*/ + gpio_dat3 = <&gpio BOOT_3 GPIO_ACTIVE_HIGH>; + hw_reset = <&gpio BOOT_9 GPIO_ACTIVE_HIGH>; + tx_phase = <3>; + card_type = <1>; + /* 1:mmc card(include eMMC), + * 2:sd card(include tSD) + */ + }; + }; + + sd_emmc_b:sd@d0072000 { + compatible = "amlogic, meson-mmc-txl"; + status = "okay"; + reg = <0xd0072000 0x2000>; + interrupts = <0 217 1>; + pinctrl-names = "sd_all_pins", + "sd_clk_cmd_pins", + "sd_1bit_pins", + "sd_clk_cmd_uart_pins", + "sd_1bit_uart_pins", + "sd_to_ao_uart_pins", + "ao_to_sd_uart_pins", + "ao_to_sd_jtag_pins", + "sd_to_ao_jtag_pins"; + pinctrl-0 = <&sd_all_pins>; + pinctrl-1 = <&sd_clk_cmd_pins>; + pinctrl-2 = <&sd_1bit_pins>; + pinctrl-3 = <&sd_to_ao_uart_clr_pins + &sd_clk_cmd_pins &ao_to_sd_uart_pins>; + pinctrl-4 = <&sd_to_ao_uart_clr_pins + &sd_1bit_pins &ao_to_sd_uart_pins>; + pinctrl-5 = <&sd_all_pins &sd_to_ao_uart_pins>; + pinctrl-6 = <&sd_to_ao_uart_clr_pins &ao_to_sd_uart_pins>; + pinctrl-7 = <&sd_to_ao_uart_clr_pins &ao_to_sd_uart_pins>; + pinctrl-8 = <&sd_all_pins &sd_to_ao_uart_pins>; + clocks = <&clkc CLKID_SD_EMMC_B>, + <&clkc CLKID_SD_EMMC_B_COMP>, + <&clkc CLKID_FCLK_DIV2>; + clock-names = "core", "clkin0", "clkin1"; + + bus-width = <4>; + cap-sd-highspeed; + max-frequency = <100000000>; + disable-wp; + sd { + pinname = "sd"; + ocr_avail = <0x200080>; /**VDD voltage 3.3 ~ 3.4 */ + caps = "MMC_CAP_4_BIT_DATA", + "MMC_CAP_MMC_HIGHSPEED", + "MMC_CAP_SD_HIGHSPEED"; + /* "MMC_CAP_UHS_SDR12", + * "MMC_CAP_UHS_SDR25", + * "MMC_CAP_UHS_SDR50", + * "MMC_CAP_UHS_SDR104"; + */ + f_min = <400000>; + f_max = <100000000>; + max_req_size = <0x20000>; /**128KB*/ + gpio_dat3 = <&gpio CARD_4 GPIO_ACTIVE_HIGH>; + jtag_pin = <&gpio CARD_0 GPIO_ACTIVE_HIGH>; + gpio_cd = <&gpio CARD_6 GPIO_ACTIVE_HIGH>; + card_type = <5>; + /* 0:unknown, + * 1:mmc card(include eMMC), + * 2:sd card(include tSD), + * 3:sdio device(ie:sdio-wifi), + * 4:SD combo (IO+mem) card, + * 5:NON sdio device(means sd/mmc card), + * other:reserved + */ + }; + }; + + unifykey { + compatible = "amlogic, unifykey"; + status = "okay"; + + unifykey-num = <19>; + unifykey-index-0 = <&keysn_0>; + unifykey-index-1 = <&keysn_1>; + unifykey-index-2 = <&keysn_2>; + unifykey-index-3 = <&keysn_3>; + unifykey-index-4 = <&keysn_4>; + unifykey-index-5 = <&keysn_5>; + unifykey-index-6 = <&keysn_6>; + unifykey-index-7 = <&keysn_7>; + unifykey-index-8 = <&keysn_8>; + unifykey-index-9 = <&keysn_9>; + unifykey-index-10= <&keysn_10>; + unifykey-index-11 = <&keysn_11>; + unifykey-index-12 = <&keysn_12>; + unifykey-index-13 = <&keysn_13>; + unifykey-index-14 = <&keysn_14>; + unifykey-index-15 = <&keysn_15>; + unifykey-index-16 = <&keysn_16>; + unifykey-index-17 = <&keysn_17>; + unifykey-index-18 = <&keysn_18>; + + keysn_0: key_0{ + key-name = "usid"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_1:key_1{ + key-name = "mac"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_2:key_2{ + key-name = "hdcp"; + key-device = "secure"; + key-type = "sha1"; + key-permit = "read","write","del"; + }; + keysn_3:key_3{ + key-name = "secure_boot_set"; + key-device = "efuse"; + key-permit = "write"; + }; + keysn_4:key_4{ + key-name = "mac_bt"; + key-device = "normal"; + key-permit = "read","write","del"; + key-type = "mac"; + }; + keysn_5:key_5{ + key-name = "mac_wifi"; + key-device = "normal"; + key-permit = "read","write","del"; + key-type = "mac"; + }; + keysn_6:key_6{ + key-name = "hdcp2_tx"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_7:key_7{ + key-name = "hdcp2_rx"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_8:key_8{ + key-name = "widevinekeybox"; + key-device = "secure"; + key-type = "sha1"; + key-permit = "read","write","del"; + }; + keysn_9:key_9{ + key-name = "deviceid"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_10:key_10{ + key-name = "hdcp22_fw_private"; + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_11:key_11{ + key-name = "hdcp22_rx_private"; + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_12:key_12{ + key-name = "hdcp22_rx_fw"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_13:key_13{ + key-name = "hdcp14_rx"; + key-device = "normal"; + key-type = "sha1"; + key-permit = "read","write","del"; + }; + keysn_14:key_14{ + key-name = "prpubkeybox";// PlayReady + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_15:key_15{ + key-name = "prprivkeybox";// PlayReady + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_16:key_16{ + key-name = "lcd"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_17:key_17{ + key-name = "lcd_extern"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_18:key_18{ + key-name = "backlight"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + }; /* End unifykey */ + + vout { + compatible = "amlogic, vout"; + dev_name = "vout"; + status = "okay"; + fr_auto_policy = <0>; + }; + + dvb { + compatible = "amlogic, dvb"; + dev_name = "dvb"; + status = "okay"; + fe0_mode = "internal"; + fe0_tuner = <&tuner>; + + /*"parallel","serial","disable"*/ + ts2 = "parallel"; + ts2_control = <0>; + ts2_invert = <0>; + interrupts = <0 23 1 + 0 5 1 + 0 53 1 + 0 19 1 + 0 25 1 + 0 18 1 + 0 24 1>; + interrupt-names = "demux0_irq", + "demux1_irq", + "demux2_irq", + "dvr0_irq", + "dvr1_irq", + "dvrfill0_fill", + "dvrfill1_flush"; + clocks = <&clkc CLKID_DEMUX + &clkc CLKID_ASYNC_FIFO + &clkc CLKID_AHB_ARB0 + &clkc CLKID_DOS_PARSER>; + clock-names = "demux", "asyncfifo", "ahbarb0", "uparsertop"; + }; + + meson_sensor: sensor@0 { + compatible = "amlogic, aml-thermal"; + #thermal-sensor-cells = <1>; + cooling_devices { + cpufreq_cool_cluster0 { + min_state = <1000000>; + dyn_coeff = <140>; + cluster_id = <0>; + node_name = "cpus"; + device_type = "cpufreq"; + }; + cpucore_cool_cluster0 { + min_state = <1>; + dyn_coeff = <0>; + cluster_id = <0>; + node_name = "cpu_core_cluster0"; + device_type = "cpucore"; + }; + gpufreq_cool { + min_state = <400>; + dyn_coeff = <437>; + cluster_id = <0>; + node_name = "mali"; + device_type = "gpufreq"; + }; + gpucore_cool { + min_state = <1>; + dyn_coeff = <0>; + cluster_id = <0>; + node_name = "thermal_gpu_cores"; + device_type = "gpucore"; + }; + }; + cpu_cluster0:cpu_core_cluster0 { + #cooling-cells = <2>; /* min followed by max */ + }; + gpucore:thermal_gpu_cores { + #cooling-cells = <2>; /* min followed by max */ + }; + }; + + dtv-demod { + compatible = "amlogic, ddemod-txl"; + status = "okay"; + + pinctrl-names = "dtvdemod_agc_pins"; + pinctrl-0 = <&dtvdemod_agc_pins>; + + clocks = <&clkc CLKID_DAC_CLK>; + clock-names = "vdac_clk_gate"; + + reg = <0xc8844000 0x2000 /*dtv demod base*/ + 0xc883c000 0x2000 /*hiu reg base*/ + 0xc8100000 0x1000 /*io_aobus_base*/ + 0xc1104400 0x1000 /*reset*/ + >; + /*move from dvbfe*/ + dtv_demod0_mem = <0>; // need move to aml_dtv_demod ? + spectrum = <1>; + cma_flag = <1>; + cma_mem_size = <8>; + memory-region = <&demod_cma_reserved>;//<&demod_reserved>; + }; + + thermal-zones { + soc_thermal { + polling-delay = <1000>; + polling-delay-passive = <100>; + sustainable-power = <2150>; + thermal-sensors = <&meson_sensor 3>; + + trips { + switch_on: trip-point@0 { + temperature = <70000>; + hysteresis = <1000>; + type = "passive"; + }; + control: trip-point@1 { + temperature = <80000>; + hysteresis = <1000>; + type = "passive"; + }; + hot: trip-point@2 { + temperature = <85000>; + hysteresis = <5000>; + type = "hot"; + }; + critical: trip-point@3 { + temperature = <260000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + + cooling-maps { + cpufreq_cooling_map { + trip = <&control>; + cooling-device = <&cpus 0 4>; + contribution = <1024>; + }; + cpucore_cooling_map { + trip = <&control>; + cooling-device = <&cpu_cluster0 0 3>; + contribution = <1024>; + }; + gpufreq_cooling_map { + trip = <&control>; + cooling-device = <&gpu 0 4>; + contribution = <1024>; + }; + gpucore_cooling_map { + trip = <&control>; + cooling-device = <&gpucore 0 2>; + contribution = <1024>; + }; + }; + }; + }; + + /* start AUDIO_RELATED */ + i2s_dai: I2S { + #sound-dai-cells = <0>; + compatible = "amlogic, aml-i2s-dai"; + clocks = < + &clkc CLKID_MPLL3 + &clkc CLKID_AMCLK_COMP + &clkc CLKID_AIU_GLUE + &clkc CLKID_I2S_OUT + &clkc CLKID_AMCLK_MEASURE + &clkc CLKID_AIFIFO2 + &clkc CLKID_MIXER + &clkc CLKID_MIXER_IFACE + &clkc CLKID_ADC + &clkc CLKID_AIU_TOP + &clkc CLKID_AOCLK_GATE + &clkc CLKID_I2S_SPDIF + >; + clock-names = + "mpll", + "mclk", + "top_glue", + "i2s_out", + "amclk_measure", + "aififo2", + "aud_mixer", + "mixer_reg", + "adc", + "top_level", + "aoclk", + "aud_in"; + }; + + spdif_dai: SPDIF { + #sound-dai-cells = <0>; + compatible = "amlogic, aml-spdif-dai"; + clocks = < + &clkc CLKID_MPLL1 + &clkc CLKID_IEC958_INT_COMP + &clkc CLKID_AMCLK_COMP + &clkc CLKID_IEC958_MUX + &clkc CLKID_CLK81 + &clkc CLKID_IEC958 + &clkc CLKID_IEC958_GATE + >; + clock-names = + "mpll1", + "i958", + "mclk", + "spdif", + "clk_81", + "iec958", + "iec958_amclk"; + }; + + pcm_dai: PCM { + #sound-dai-cells = <0>; + compatible = "amlogic, aml-pcm-dai"; + pinctrl-names = "audio_pcm"; + /* disable pcm pin mux temporary, enable it if necessary */ + /*pinctrl-0 = <&aml_audio_pcm>;*/ + clocks = < + &clkc CLKID_MPLL0 + &clkc CLKID_PCM_MCLK_COMP + &clkc CLKID_PCM_SCLK_COMP + >; + clock-names = "mpll0", "pcm_mclk", "pcm_sclk"; + pcm_mode = <1>; /* 0=slave mode, 1=master mode */ + }; + + i2s_plat: i2s_platform { + compatible = "amlogic, aml-i2s"; + interrupts = <0 29 1>; + }; + + pcm_plat: pcm_platform { + compatible = "amlogic, aml-pcm"; + }; + + spdif_codec: spdif_codec { + #sound-dai-cells = <0>; + compatible = "amlogic, aml-spdif-codec"; + status = "okay"; + pinctrl-names = "audio_spdif_out"; + pinctrl-0 = <&audio_spdif_out_pins>; + }; + + pcm_codec: pcm_codec { + #sound-dai-cells = <0>; + compatible = "amlogic, pcm2BT-codec"; + status = "okay"; + }; + /* endof AUDIO MESON8 DEVICES */ + + /* AUDIO board specific */ + dummy_codec:dummy { + #sound-dai-cells = <0>; + compatible = "amlogic, aml_dummy_codec"; + status = "disabled"; + }; + + amlogic_codec:t9015S { + #sound-dai-cells = <0>; + compatible = "amlogic, aml_codec_T9015S"; + status = "okay"; + reg = <0xc8832000 0x14>; + }; + + aml_snd_tv { + compatible = "amlogic, txl-snd-tv"; + status = "okay"; + aml-sound-card,format = "i2s"; + aml_sound_card,name = "AML-TVAUDIO"; + pinctrl-names = "audio_i2s"; + pinctrl-0 = <&aml_audio_i2s>; + /*avout mute gpio*/ + mute_gpio-gpios = <&gpio GPIODV_11 GPIO_ACTIVE_HIGH>; + sleep_time = <20>; + aux_dev = <&tas5707>; + cpu_list = <&cpudai0 &cpudai1 &cpudai2>; + codec_list = <&codec0 &codec1 &codec2>; + plat_list = <&i2s_plat &i2s_plat &pcm_plat>; + cpudai0: cpudai0 { + sound-dai = <&i2s_dai>; + }; + cpudai1: cpudai1 { + sound-dai = <&spdif_dai>; + }; + cpudai2: cpudai2 { + sound-dai = <&pcm_dai>; + }; + codec0: codec0 { + sound-dai = <&amlogic_codec>; + }; + codec1: codec1 { + sound-dai = <&spdif_codec>; + }; + codec2: codec2 { + sound-dai = <&pcm_codec>; + }; + Channel_Mask { + /*i2s has 4 pins, 8channel, mux output*/ + Speaker1_Channel_Mask = "i2s_2/3"; + DAC0_Channel_Mask = "i2s_0/1"; + }; + }; + + amaudio2 { + compatible = "amlogic, aml_amaudio2"; + status = "okay"; + interrupts = <0 48 1>; + }; + /* end of AUDIO_RELATED */ + + wifi { + compatible = "amlogic, aml_wifi"; + status = "okay"; + power_on_pin = <&gpio_ao GPIOAO_5 GPIO_ACTIVE_HIGH>; + }; +}; /* end of / */ + +&pinctrl_periphs { + /* start AUDIO_RELATED */ + /*i2s*/ + aml_audio_i2s: aml_audio_i2s { + mux { + groups = "i2s_amclk_z", + "i2s_aoclk_out_z", + "i2s_lrclk_out_z" + /*,"i2s_out_ch01_z"*/ + ,"i2s_out_ch23" + ; + function = "i2s"; + }; + }; + + /*spdif*/ + audio_spdif_out_pins: audio_spdif_out_pins { + mux { + groups = "spdif_out"; + function = "spdif_out"; + }; + }; + + /*pcm*/ + aml_audio_pcm: aml_audio_pcm { + mux { + groups = + "pcm_clk_a", + "pcm_fs_a", + "pcm_in_a", + "pcm_out_a"; + function = "pcm_a"; + }; + }; + /* end AUDIO_RELATED */ + + /*lcd_extern*/ + lcd_extern_off_pins:lcd_extern_off_pin { + mux { + pins = "GPIOH_2", + "GPIOH_3"; + function = "gpio_periphs"; + /*output-high;*/ + output-low; + /*input-enable;*/ + }; + }; + + /*backlight*/ + bl_pwm_off_pins:bl_pwm_off_pin { + mux { + pins = "GPIOZ_6"; + function = "gpio_periphs"; + output-low; + }; + }; + bl_pwm_combo_off_pins:bl_pwm_combo_off_pin { + mux { + pins = "GPIOZ_6", + "GPIOZ_7"; + function = "gpio_periphs"; + output-low; + }; + }; +}; + +&i2c0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_z_pins>; + + /* start AUDIO_RELATED */ + tas5707: tas5707@36 { + #sound-dai-cells = <0>; + compatible = "ti,tas5707"; + status = "okay"; + codec_name = "tas5707"; + reg = <0x1B>; + reset_pin = <&gpio GPIOZ_13 GPIO_ACTIVE_LOW>; + eq_enable = <0>; + drc_enable = <0>; + }; + /* end AUDIO_RELATED */ +}; + + +&i2c1 { + status = "okay"; + clock-frequency = <300000>; + pinctrl-names="default"; + pinctrl-0=<&i2c1_dv_pins>; +}; + +&i2c2 { + status = "okay"; + pinctrl-names="default"; + pinctrl-0=<&i2c2_h_pins>; + + lcd_extern_i2c0: lcd_extern_i2c@0 { + compatible = "lcd_ext, i2c"; + dev_name = "i2c_T5800Q"; + reg = <0x1c>; + status = "okay"; + }; +}; + +&dwc3 { + status = "okay"; +}; + +&usb2_phy { + status = "okay"; +}; + +&usb3_phy { + status = "okay"; +}; + +&dwc2_a { + status = "okay"; + /** 0: normal, 1: otg+dwc3 host only, 2: otg+dwc3 device only*/ + controller-type = <1>; +}; + +&audio_data{ + status = "okay"; +}; + +&pwm_ab { + status = "okay"; +}; + +&pwm_cd { + status = "okay"; +}; + +ðmac { + status = "okay"; +}; + diff --git a/arch/arm/boot/dts/amlogic/txl_t962_p321.dts b/arch/arm/boot/dts/amlogic/txl_t962_p321.dts index fce14f4110cb..c896f12a95d0 100644 --- a/arch/arm/boot/dts/amlogic/txl_t962_p321.dts +++ b/arch/arm/boot/dts/amlogic/txl_t962_p321.dts @@ -53,8 +53,13 @@ #address-cells = <1>; #size-cells = <1>; ranges; - /* global autoconfigured region for contiguous allocations */ + + defendkey_reserved:linux,defendkey { + compatible = "amlogic, defendkey"; + reg = <0x08300000 0x100000>; + }; + secmon_reserved:linux,secmon { compatible = "shared-dma-pool"; reusable; @@ -78,13 +83,24 @@ alloc-ranges = <0x3f800000 0x800000>; }; + codec_mm_cma:linux,codec_mm_cma { + compatible = "shared-dma-pool"; + reusable; + /* ion_codec_mm max can alloc size 80M*/ + size = <0xd000000>; + alignment = <0x400000>; + linux,contiguous-region; + /** alloc by self **/ + alloc-ranges = <0x30000000 0x10000000>; + }; + ion_reserved:linux,ion-dev { compatible = "shared-dma-pool"; reusable; size = <0x4C00000>; alignment = <0x400000>; /* alloc by self */ - alloc-ranges = <0x0 0x2ee00000>; + alloc-ranges = <0x0 0x30000000>; }; /*di CMA pool */ @@ -100,25 +116,13 @@ */ size = <0x02800000>; alignment = <0x400000>; - alloc-ranges = <0x32000000 0xc800000>; + alloc-ranges = <0x30000000 0x10000000>; }; /* POST PROCESS MANAGER */ ppmgr_reserved:linux,ppmgr { compatible = "amlogic, ppmgr_memory"; size = <0x0>; - alloc-ranges = <0x32000000 0xc800000>; - }; - - codec_mm_cma:linux,codec_mm_cma { - compatible = "shared-dma-pool"; - reusable; - /* ion_codec_mm max can alloc size 80M*/ - size = <0xd000000>; - alignment = <0x400000>; - linux,contiguous-region; - /** alloc by self **/ - alloc-ranges = <0x0 0x2ee00000>; }; picdec_cma_reserved:linux,picdec { @@ -127,7 +131,6 @@ size = <0x0>; alignment = <0x0>; linux,contiguous-region; - alloc-ranges = <0x32000000 0xc800000>; }; /* codec shared reserved */ @@ -144,7 +147,7 @@ /* 5M */ size = <0x0800000>; alignment = <0x400000>; - alloc-ranges = <0x32000000 0xc800000>; + alloc-ranges = <0x00000000 0x30000000>; }; /* vdin1 CMA pool */ @@ -155,18 +158,18 @@ size = <0x01000000>; alignment = <0x400000>; /** alloc by self **/ - alloc-ranges = <0x32000000 0xc800000>; + alloc-ranges = <0x00000000 0x30000000>; }; }; /* end of reserved-memory */ - dummy-battery { + amlogic_battery:dummy-battery { compatible = "amlogic, dummy-battery"; - status = "okay"; + status = "disabled"; }; - dummy-charger { + amlogic_charger:dummy-charger { compatible = "amlogic, dummy-charger"; - status = "okay"; + status = "disabled"; }; secmon { diff --git a/arch/arm/boot/dts/amlogic/txl_t962_p321_720p.dts b/arch/arm/boot/dts/amlogic/txl_t962_p321_720p.dts new file mode 100644 index 000000000000..5548335d502f --- /dev/null +++ b/arch/arm/boot/dts/amlogic/txl_t962_p321_720p.dts @@ -0,0 +1,1182 @@ +/* + * arch/arm/boot/dts/amlogic/txl_t962_321.dts + * + * Copyright (C) 2018 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +/dts-v1/; + +#include "mesontxl.dtsi" +#include "partition_mbox_normal_P_32.dtsi" +#include "mesontxl_p321-panel.dtsi" + +/ { + model = "Amlogic TXL T962 P321 Reference Board"; + compatible = "amlogic, txl_t962_p321"; + amlogic-dt-id = "txl_p321_v1_720p"; + + aliases { + serial0 = &uart_AO; + serial1 = &uart_A; + serial2 = &uart_B; + serial3 = &uart_C; + serial4 = &uart_AO_B; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c_AO; + }; + + ion_dev { + compatible = "amlogic, ion_dev"; + memory-region = <&ion_reserved>; + }; + + memory@00000000 { + device_type = "memory"; + linux,usable-memory = <0x100000 0x3ff00000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + /* global autoconfigured region for contiguous allocations */ + + defendkey_reserved:linux,defendkey { + compatible = "amlogic, defendkey"; + reg = <0x08300000 0x100000>; + }; + + secmon_reserved:linux,secmon { + compatible = "shared-dma-pool"; + reusable; + size = <0x400000>; + alignment = <0x400000>; + alloc-ranges = <0x05000000 0x400000>; + }; + + //secos_reserved:linux,secos { + // status = "disabled"; + // compatible = "amlogic, aml_secos_memory"; + // reg = <0x0 0x05300000 0x0 0x2000000>; + // no-map; + //}; + + logo_reserved:linux,meson-fb { + compatible = "shared-dma-pool"; + reusable; + size = <0x400000>; + alignment = <0x400000>; + alloc-ranges = <0x0 0x30000000>; + }; + codec_mm_cma:linux,codec_mm_cma { + compatible = "shared-dma-pool"; + reusable; + /* ion_codec_mm max can alloc size 80M*/ + size = <0xd000000>; + alignment = <0x400000>; + linux,contiguous-region; + /** alloc by self **/ + alloc-ranges = <0x30000000 0x10000000>; + }; + + + ion_reserved:linux,ion-dev { + compatible = "shared-dma-pool"; + reusable; + size = <0x4C00000>; + alignment = <0x400000>; + /* alloc by self */ + alloc-ranges = <0x0 0x30000000>; + }; + + /*di CMA pool */ + di_cma_reserved:linux,di_cma { + compatible = "shared-dma-pool"; + reusable; + /* buffer_size = 3621952(yuv422 8bit) + * | 4736064(yuv422 10bit) + * | 4179008(yuv422 10bit full pack mode) + * 10x3621952=34.6M(0x23) support 8bit + * 10x4736064=45.2M(0x2e) support 12bit + * 10x4179008=40M(0x28) support 10bit + */ + size = <0x02800000>; + alignment = <0x400000>; + alloc-ranges = <0x30000000 0x10000000>; + }; + + /* POST PROCESS MANAGER */ + ppmgr_reserved:linux,ppmgr { + compatible = "amlogic, ppmgr_memory"; + size = <0x0>; + }; + + picdec_cma_reserved:linux,picdec { + compatible = "shared-dma-pool"; + reusable; + size = <0x0>; + alignment = <0x0>; + linux,contiguous-region; + }; + + /* codec shared reserved */ + codec_mm_reserved:linux,codec_mm_reserved { + compatible = "amlogic, codec-mm-reserved"; + size = <0x0>; + alignment = <0x100000>; + //no-map; + }; + + demod_cma_reserved:linux,demod_cma { + compatible = "shared-dma-pool"; + reusable; + /* 5M */ + size = <0x0800000>; + alignment = <0x400000>; + alloc-ranges = <0x0 0x30000000>; + }; + + /* vdin1 CMA pool */ + vdin1_cma_reserved:linux,vdin1_cma { + compatible = "shared-dma-pool"; + reusable; + /* 1920x1080x2x4 =16 M */ + size = <0x01000000>; + alignment = <0x400000>; + /** alloc by self **/ + alloc-ranges = <0x0 0x30000000>; + }; + }; /* end of reserved-memory */ + + amlogic_battery:dummy-battery { + compatible = "amlogic, dummy-battery"; + status = "disabled"; + }; + + amlogic_charger:dummy-charger { + compatible = "amlogic, dummy-charger"; + status = "disabled"; + }; + + secmon { + compatible = "amlogic, secmon"; + memory-region = <&secmon_reserved>; + in_base_func = <0x82000020>; + out_base_func = <0x82000021>; + reserve_mem_size = <0x00300000>; + }; + + gpioleds { + compatible = "gpio-leds"; + status = "disabled"; + + sys_led { + label = "sys_led"; + gpios = <&gpio_ao GPIOAO_3 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + }; + + /*for external keypad*/ + adc-keypad { + compatible = "amlogic, adc_keypad"; + status = "okay"; + key_name = "power","up", "down","enter","left","right","home"; + key_num = <7>; + io-channels = <&saradc SARADC_CH2>, + <&saradc SARADC_CH3>; + io-channel-names = "key-chan-2", "key-chan-3"; + key_chan = ; + key_code = <116 103 108 28 105 106 102>; + key_val = <0 143 266 389 512 143 266>; //val=voltage/1800mV*1023 + key_tolerance = <40 40 40 40 40 40 40>; + }; + + avin_detect { + compatible = "amlogic, avin_detect"; + status = "okay"; + avin_device_num = <1>; + gpios = <&gpio GPIODV_8 GPIO_ACTIVE_HIGH>; + detect_interval_length = <100>; + set_detect_times = <5>; + set_fault_tolerance = <1>; + }; + + meson-fb { + compatible = "amlogic, meson-txl"; + memory-region = <&logo_reserved>; + dev_name = "meson-fb"; + status = "okay"; + interrupts = <0 3 1 + 0 89 1>; + interrupt-names = "viu-vsync", "rdma"; + mem_size = <0x00400000 0x00b00000 0x00100000>; + /* uboot logo,fb0/fb1 memory size,if afbcd fb0=0x0b51000*/ + display_mode_default = "720p60hz"; + /* 0:VPU free scale 1:OSD free scale 2:OSD super scale */ + scale_mode = <1>; + /*1280*720*4*3 = 0xA8C000*/ + display_size_default = <1280 720 1280 2160 32>; + pxp_mode = <0>; /** 0:normal mode 1:pxp mode */ + logo_addr = "0x3fc00000"; + }; + + picdec { + compatible = "amlogic, picdec"; + status = "okay"; + memory-region = <&picdec_cma_reserved>; + }; + + ppmgr { + compatible = "amlogic, ppmgr"; + status = "okay"; + memory-region = <&ppmgr_reserved>; + }; + + deinterlace { + compatible = "amlogic, deinterlace"; + status = "okay"; + /* 0:use reserved; 1:use cma; 2:use cma as reserved */ + flag_cma = <1>; + //memory-region = <&di_reserved>; + memory-region = <&di_cma_reserved>; + interrupts = <0 46 1 + 0 6 1>; + interrupt-names = "de_irq"; + clocks = <&clkc CLKID_VPU_MUX>, + <&clkc CLKID_FCLK_DIV4>, + <&clkc CLKID_VPU_CLKB_TMP_COMP>, + <&clkc CLKID_VPU_CLKB_COMP>; + clock-names = "vpu_mux", + "fclk_div4", + "vpu_clkb_tmp_composite", + "vpu_clkb_composite"; + clock-range = <333 333>; + /* buffer-size = <3621952>;(yuv422 8bit) */ + buffer-size = <4179008>;/*yuv422 fullpack*/ + /* reserve-iomap = "true"; */ + /* if enable nr10bit, set nr10bit-support to 1 */ + nr10bit-support = <1>; + }; + + ionvideo { + compatible = "amlogic, ionvideo"; + dev_name = "ionvideo"; + status = "okay"; + }; + + hdmirx { + compatible = "amlogic, hdmirx-txl"; + status = "okay"; + #address-cells=<1>; + #size-cells=<1>; + dev_name = "hdmirx"; + pinctrl-names = "hdmirx_pins"; + pinctrl-0 = <&hdmirx_a_mux &hdmirx_b_mux + &hdmirx_c_mux>; + repeat = <0>; + interrupts = <0 56 1>; + clocks = <&clkc CLKID_HDMIRX_MODET_COMP>, + <&clkc CLKID_HDMIRX_CFG_COMP>, + <&clkc CLKID_HDMIRX_ACR_COMP>, + <&clkc CLKID_HDMIRX_AUDMEAS_COMP>, + <&xtal>, + <&clkc CLKID_FCLK_DIV5>, + <&clkc CLKID_FCLK_DIV7>, + <&clkc CLKID_HDCP22_SKP_COMP>, + <&clkc CLKID_HDCP22_ESM_COMP>; + //<&clkc CLK_AUD_PLL2FS>, + //<&clkc CLK_AUD_PLL4FS>, + //<&clkc CLK_AUD_OUT>; + clock-names = "hdmirx_modet_clk", + "hdmirx_cfg_clk", + "hdmirx_acr_ref_clk", + "hdmirx_audmeas_clk", + "xtal", + "fclk_div5", + "fclk_div7", + "hdcp_rx22_skp", + "hdcp_rx22_esm"; + //"hdmirx_aud_pll2fs", + //"hdmirx_aud_pll4f", + //"clk_aud_out"; + hdmirx_id = <0>; + en_4k_2_2k = <0>; + hpd_low_cec_off = <1>; + /* bit4: enable feature, bit3~0: port number */ + disable_port = <0x0>; + reg = <0xc0800000 0xa00000 + 0xC883C000 0x2000 + 0xd0076000 0x2000 + 0xc883e000 0x2000 + 0xda83e000 0x2000 + 0xc8834000 0x2000 + 0xda846000 0x2000>; + }; + + vdin@0 { + compatible = "amlogic, vdin"; + /*memory-region = <&vdin0_cma_reserved>;*/ + dev_name = "vdin0"; + status = "okay"; + reserve-iomap = "true"; + /*bit0:(1:share with codec_mm;0:cma alone)*/ + /*bit8:(1:alloc in discontinus way;0:alone in continuous way)*/ + flag_cma = <0x101>; + /* MByte, if 10bit disable: 64M(YUV422), + * if 10bit enable: 64*1.5 = 96M(YUV422) + * if support 4K2K-YUV444-10bit-WR:3840*2160*4*4 ~= 128M + * if support 4K2K-YUV444-10bit-WR:3840*2160*4*6 ~= 190M + * if support 4K2K-YUV422-10bit-wr:3840*2160*3*4 ~= 96M + * if support 4K2K-YUV422-8BIT-WR:3840*2160*2*4 ~= 64M + * if support 1080p-YUV422-8BIT-WR:1920*1080*2*4 ~= 16M + */ + cma_size = <190>; + interrupts = <0 83 1>; + rdma-irq = <2>; + clocks = <&clkc CLKID_FCLK_DIV5>, + <&clkc CLKID_VDIN_MEAS_COMP>; + clock-names = "fclk_div5", "cts_vdin_meas_clk"; + vdin_id = <0>; + /* vdin write mem color depth support: + * bit0:support 8bit + * bit1:support 9bit + * bit2:support 10bit + * bit3:support 12bit + * bit4:support yuv422 10bit full pack mode (from txl new add) + * bit8:use 8bit at 4k_50/60hz_10bit + * bit9:use 10bit at 4k_50/60hz_10bit + */ + tv_bit_mode = <0x215>; + }; + + vdin@1 { + compatible = "amlogic, vdin"; + memory-region = <&vdin1_cma_reserved>; + dev_name = "vdin1"; + status = "okay"; + reserve-iomap = "true"; + flag_cma = <0>;/*1:share with codec_mm;0:cma alone*/ + interrupts = <0 85 1>; + rdma-irq = <4>; + clocks = <&clkc CLKID_FCLK_DIV5>, + <&clkc CLKID_VDIN_MEAS_COMP>; + clock-names = "fclk_div5", "cts_vdin_meas_clk"; + vdin_id = <1>; + /* vdin write mem color depth support: + * bit0:support 8bit + * bit1:support 9bit + * bit2:support 10bit + * bit3:support 12bit + */ + tv_bit_mode = <21>; + }; + + tvafe:tvafe@c8842000 { + compatible = "amlogic, tvafe-txl"; + status = "okay"; + /*memory-region = <&tvafe_cma_reserved>;*/ + dev_name = "tvafe"; + flag_cma = <1>;/*1:share with codec_mm;0:cma alone*/ + cma_size = <5>;/*MByte*/ + reg = <0xc8842000 0x2000>;/*tvafe reg base*/ + reserve-iomap = "true"; + tvafe_id = <0>; + //pinctrl-names = "default"; + /*!!particular sequence, no more and no less!!!*/ + tvafe_pin_mux = < + 3 /* TVAFE_CVBS_IN2, CVBS_IN0 = 0 */ + 1 /* TVAFE_CVBS_IN0, CVBS_IN1 */ + 2 /* TVAFE_CVBS_IN1, CVBS_IN2 */ + 4 /* TVAFE_CVBS_IN3, CVBS_IN3 */ + >; + clocks = <&clkc CLKID_DAC_CLK>; + clock-names = "vdac_clk_gate"; + }; + + vecm { + compatible = "amlogic, vecm"; + dev_name = "aml_vecm"; + status = "okay"; + gamma_en = <1>;/*1:enabel ;0:disable*/ + wb_en = <1>;/*1:enabel ;0:disable*/ + cm_en = <1>;/*1:enabel ;0:disable*/ + wb_sel = <1>;/*1:mtx ;0:gainoff*/ + vlock_en = <1>;/*1:enable;0:disable*/ + vlock_mode = <0x4>; + /* vlock work mode: + *bit0:auto ENC + *bit1:auto PLL + *bit2:manual PLL + *bit3:manual ENC + *bit4:manual soft ENC + *bit5:manual MIX PLL ENC + */ + vlock_pll_m_limit = <1>; + vlock_line_limit = <3>; + }; + + tuner: tuner { + status = "okay"; + tuner_name = "r842_tuner"; + tuner_i2c_adap = <&i2c1>; + tuner_i2c_addr = <0xf6>; + tuner_xtal = <1>; /* 0: 16MHz, 1: 24MHz, 3: 27MHz */ + tuner_xtal_mode = <0>; + /* NO_SHARE_XTAL(0) + * MASTER_TO_SLAVE_XTAL_IN(1) + * MASTER_TO_SLAVE_XTAL_OUT(2) + * SLAVE_XTAL_OUT(3) + */ + tuner_xtal_cap = <38>; /* 0 ~ 41 (pf) */ + }; + + atv-demod { + compatible = "amlogic, atv-demod"; + status = "okay"; + tuner = <&tuner>; + btsc_sap_mode = <1>; + pinctrl-names = "atvdemod_agc_pins"; + pinctrl-0 = <&atvdemod_agc_pins>; + reg = <0xc8840000 0x2000 /* demod reg */ + 0xc883c000 0x2000 /* hiu reg */ + 0xc8834000 0x2000>; /* periphs reg */ + reg_23cf = <0x88188832>; + /*default:0x88188832;r840 on haier:0x48188832*/ + }; + + sd_emmc_c: emmc@d0074000 { + compatible = "amlogic, meson-mmc-txl"; + status = "okay"; + reg = <0xd0074000 0x2000>; + interrupts = <0 218 1>; + pinctrl-names = "emmc_clk_cmd_pins", "emmc_all_pins"; + pinctrl-0 = <&emmc_clk_cmd_pins>; + pinctrl-1 = <&emmc_conf_pull_up &emmc_conf_pull_done>; + clocks = <&clkc CLKID_SD_EMMC_C>, + <&clkc CLKID_SD_EMMC_C_COMP>, + <&clkc CLKID_FCLK_DIV2>; + clock-names = "core", "clkin0", "clkin1"; + + bus-width = <8>; + cap-sd-highspeed; + cap-mmc-highspeed; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + + max-frequency = <200000000>; + non-removable; + disable-wp; + emmc { + pinname = "emmc"; + ocr_avail = <0x200080>; /**VDD voltage 3.3 ~ 3.4 */ + caps = "MMC_CAP_8_BIT_DATA", + "MMC_CAP_MMC_HIGHSPEED", + "MMC_CAP_SD_HIGHSPEED", + "MMC_CAP_NONREMOVABLE", + "MMC_CAP_1_8V_DDR", + "MMC_CAP_HW_RESET", + "MMC_CAP_ERASE", + "MMC_CAP_CMD23"; + caps2 = "MMC_CAP2_HS200"; + f_min = <400000>; + f_max = <100000000>; + max_req_size = <0x20000>; /**128KB*/ + gpio_dat3 = <&gpio BOOT_3 GPIO_ACTIVE_HIGH>; + hw_reset = <&gpio BOOT_9 GPIO_ACTIVE_HIGH>; + tx_phase = <3>; + card_type = <1>; + /* 1:mmc card(include eMMC), + * 2:sd card(include tSD) + */ + }; + }; + + sd_emmc_b:sd@d0072000 { + compatible = "amlogic, meson-mmc-txl"; + status = "okay"; + reg = <0xd0072000 0x2000>; + interrupts = <0 217 1>; + pinctrl-names = "sd_all_pins", + "sd_clk_cmd_pins", + "sd_1bit_pins", + "sd_clk_cmd_uart_pins", + "sd_1bit_uart_pins", + "sd_to_ao_uart_pins", + "ao_to_sd_uart_pins", + "ao_to_sd_jtag_pins", + "sd_to_ao_jtag_pins"; + pinctrl-0 = <&sd_all_pins>; + pinctrl-1 = <&sd_clk_cmd_pins>; + pinctrl-2 = <&sd_1bit_pins>; + pinctrl-3 = <&sd_to_ao_uart_clr_pins + &sd_clk_cmd_pins &ao_to_sd_uart_pins>; + pinctrl-4 = <&sd_to_ao_uart_clr_pins + &sd_1bit_pins &ao_to_sd_uart_pins>; + pinctrl-5 = <&sd_all_pins &sd_to_ao_uart_pins>; + pinctrl-6 = <&sd_to_ao_uart_clr_pins &ao_to_sd_uart_pins>; + pinctrl-7 = <&sd_to_ao_uart_clr_pins &ao_to_sd_uart_pins>; + pinctrl-8 = <&sd_all_pins &sd_to_ao_uart_pins>; + clocks = <&clkc CLKID_SD_EMMC_B>, + <&clkc CLKID_SD_EMMC_B_COMP>, + <&clkc CLKID_FCLK_DIV2>; + clock-names = "core", "clkin0", "clkin1"; + + bus-width = <4>; + cap-sd-highspeed; + max-frequency = <100000000>; + disable-wp; + sd { + pinname = "sd"; + ocr_avail = <0x200080>; /**VDD voltage 3.3 ~ 3.4 */ + caps = "MMC_CAP_4_BIT_DATA", + "MMC_CAP_MMC_HIGHSPEED", + "MMC_CAP_SD_HIGHSPEED"; + /* "MMC_CAP_UHS_SDR12", + * "MMC_CAP_UHS_SDR25", + * "MMC_CAP_UHS_SDR50", + * "MMC_CAP_UHS_SDR104"; + */ + f_min = <400000>; + f_max = <100000000>; + max_req_size = <0x20000>; /**128KB*/ + gpio_dat3 = <&gpio CARD_4 GPIO_ACTIVE_HIGH>; + jtag_pin = <&gpio CARD_0 GPIO_ACTIVE_HIGH>; + gpio_cd = <&gpio CARD_6 GPIO_ACTIVE_HIGH>; + card_type = <5>; + /* 0:unknown, + * 1:mmc card(include eMMC), + * 2:sd card(include tSD), + * 3:sdio device(ie:sdio-wifi), + * 4:SD combo (IO+mem) card, + * 5:NON sdio device(means sd/mmc card), + * other:reserved + */ + }; + }; + + spifc: spifc@c1108c80 { + status = "disabled"; + compatible = "amlogic,aml-spi-nor"; + reg = <0xc1108c80 0x80>; + pinctrl-names = "default"; + pinctrl-0 = <&spifc_all_pins>; + clocks = <&clkc CLKID_CLK81>; + clock-names = "core"; + spi-nor@0 { + compatible = "jedec,spi-nor"; + spifc-frequency = <40000000>; + read-capability = <2>;/* dual read 1_1_2 */ + spifc-io-width = <2>;/* txl only support 2 io */ + cs_gpios = <&gpio BOOT_11 GPIO_ACTIVE_HIGH>; + }; + }; + + unifykey { + compatible = "amlogic, unifykey"; + status = "okay"; + + unifykey-num = <19>; + unifykey-index-0 = <&keysn_0>; + unifykey-index-1 = <&keysn_1>; + unifykey-index-2 = <&keysn_2>; + unifykey-index-3 = <&keysn_3>; + unifykey-index-4 = <&keysn_4>; + unifykey-index-5 = <&keysn_5>; + unifykey-index-6 = <&keysn_6>; + unifykey-index-7 = <&keysn_7>; + unifykey-index-8 = <&keysn_8>; + unifykey-index-9 = <&keysn_9>; + unifykey-index-10= <&keysn_10>; + unifykey-index-11 = <&keysn_11>; + unifykey-index-12 = <&keysn_12>; + unifykey-index-13 = <&keysn_13>; + unifykey-index-14 = <&keysn_14>; + unifykey-index-15 = <&keysn_15>; + unifykey-index-16 = <&keysn_16>; + unifykey-index-17 = <&keysn_17>; + unifykey-index-18 = <&keysn_18>; + + keysn_0: key_0{ + key-name = "usid"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_1:key_1{ + key-name = "mac"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_2:key_2{ + key-name = "hdcp"; + key-device = "secure"; + key-type = "sha1"; + key-permit = "read","write","del"; + }; + keysn_3:key_3{ + key-name = "secure_boot_set"; + key-device = "efuse"; + key-permit = "write"; + }; + keysn_4:key_4{ + key-name = "mac_bt"; + key-device = "normal"; + key-permit = "read","write","del"; + key-type = "mac"; + }; + keysn_5:key_5{ + key-name = "mac_wifi"; + key-device = "normal"; + key-permit = "read","write","del"; + key-type = "mac"; + }; + keysn_6:key_6{ + key-name = "hdcp2_tx"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_7:key_7{ + key-name = "hdcp2_rx"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_8:key_8{ + key-name = "widevinekeybox"; + key-device = "secure"; + key-type = "sha1"; + key-permit = "read","write","del"; + }; + keysn_9:key_9{ + key-name = "deviceid"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_10:key_10{ + key-name = "hdcp22_fw_private"; + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_11:key_11{ + key-name = "hdcp22_rx_private"; + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_12:key_12{ + key-name = "hdcp22_rx_fw"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_13:key_13{ + key-name = "hdcp14_rx"; + key-device = "normal"; + key-type = "sha1"; + key-permit = "read","write","del"; + }; + keysn_14:key_14{ + key-name = "prpubkeybox";// PlayReady + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_15:key_15{ + key-name = "prprivkeybox";// PlayReady + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_16:key_16{ + key-name = "lcd"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_17:key_17{ + key-name = "lcd_extern"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_18:key_18{ + key-name = "backlight"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + }; /* End unifykey */ + + vout { + compatible = "amlogic, vout"; + dev_name = "vout"; + status = "okay"; + fr_auto_policy = <0>; + }; + + dvb { + compatible = "amlogic, dvb"; + dev_name = "dvb"; + status = "okay"; + fe0_mode = "internal"; + fe0_tuner = <&tuner>; + + /*"parallel","serial","disable"*/ + ts2 = "parallel"; + ts2_control = <0>; + ts2_invert = <0>; + interrupts = <0 23 1 + 0 5 1 + 0 53 1 + 0 19 1 + 0 25 1 + 0 18 1 + 0 24 1>; + interrupt-names = "demux0_irq", + "demux1_irq", + "demux2_irq", + "dvr0_irq", + "dvr1_irq", + "dvrfill0_fill", + "dvrfill1_flush"; + clocks = <&clkc CLKID_DEMUX + &clkc CLKID_ASYNC_FIFO + &clkc CLKID_AHB_ARB0 + &clkc CLKID_DOS_PARSER>; + clock-names = "demux", "asyncfifo", "ahbarb0", "uparsertop"; + }; + + meson_sensor: sensor@0 { + compatible = "amlogic, aml-thermal"; + #thermal-sensor-cells = <1>; + cooling_devices { + cpufreq_cool_cluster0 { + min_state = <1000000>; + dyn_coeff = <140>; + cluster_id = <0>; + node_name = "cpus"; + device_type = "cpufreq"; + }; + cpucore_cool_cluster0 { + min_state = <1>; + dyn_coeff = <0>; + cluster_id = <0>; + node_name = "cpu_core_cluster0"; + device_type = "cpucore"; + }; + gpufreq_cool { + min_state = <400>; + dyn_coeff = <437>; + cluster_id = <0>; + node_name = "mali"; + device_type = "gpufreq"; + }; + gpucore_cool { + min_state = <1>; + dyn_coeff = <0>; + cluster_id = <0>; + node_name = "thermal_gpu_cores"; + device_type = "gpucore"; + }; + }; + cpu_cluster0:cpu_core_cluster0 { + #cooling-cells = <2>; /* min followed by max */ + }; + gpucore:thermal_gpu_cores { + #cooling-cells = <2>; /* min followed by max */ + }; + }; + + dtv-demod { + compatible = "amlogic, ddemod-txl"; + status = "okay"; + + pinctrl-names = "dtvdemod_agc_pins"; + pinctrl-0 = <&dtvdemod_agc_pins>; + + clocks = <&clkc CLKID_DAC_CLK>; + clock-names = "vdac_clk_gate"; + + reg = <0xc8844000 0x2000 /*dtv demod base*/ + 0xc883c000 0x2000 /*hiu reg base*/ + 0xc8100000 0x1000 /*io_aobus_base*/ + 0xc1104400 0x1000 /*reset*/ + >; + /*move from dvbfe*/ + dtv_demod0_mem = <0>; // need move to aml_dtv_demod ? + spectrum = <1>; + cma_flag = <1>; + cma_mem_size = <8>; + memory-region = <&demod_cma_reserved>;//<&demod_reserved>; + }; + + thermal-zones { + soc_thermal { + polling-delay = <1000>; + polling-delay-passive = <100>; + sustainable-power = <2150>; + thermal-sensors = <&meson_sensor 3>; + + trips { + switch_on: trip-point@0 { + temperature = <70000>; + hysteresis = <1000>; + type = "passive"; + }; + control: trip-point@1 { + temperature = <80000>; + hysteresis = <1000>; + type = "passive"; + }; + hot: trip-point@2 { + temperature = <85000>; + hysteresis = <5000>; + type = "hot"; + }; + critical: trip-point@3 { + temperature = <260000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + + cooling-maps { + cpufreq_cooling_map { + trip = <&control>; + cooling-device = <&cpus 0 4>; + contribution = <1024>; + }; + cpucore_cooling_map { + trip = <&control>; + cooling-device = <&cpu_cluster0 0 3>; + contribution = <1024>; + }; + gpufreq_cooling_map { + trip = <&control>; + cooling-device = <&gpu 0 4>; + contribution = <1024>; + }; + gpucore_cooling_map { + trip = <&control>; + cooling-device = <&gpucore 0 2>; + contribution = <1024>; + }; + }; + }; + }; + + /* start AUDIO_RELATED */ + i2s_dai: I2S { + #sound-dai-cells = <0>; + compatible = "amlogic, aml-i2s-dai"; + clocks = < + &clkc CLKID_MPLL3 + &clkc CLKID_AMCLK_COMP + &clkc CLKID_AIU_GLUE + &clkc CLKID_I2S_OUT + &clkc CLKID_AMCLK_MEASURE + &clkc CLKID_AIFIFO2 + &clkc CLKID_MIXER + &clkc CLKID_MIXER_IFACE + &clkc CLKID_ADC + &clkc CLKID_AIU_TOP + &clkc CLKID_AOCLK_GATE + &clkc CLKID_I2S_SPDIF + >; + clock-names = + "mpll", + "mclk", + "top_glue", + "i2s_out", + "amclk_measure", + "aififo2", + "aud_mixer", + "mixer_reg", + "adc", + "top_level", + "aoclk", + "aud_in"; + }; + + spdif_dai: SPDIF { + #sound-dai-cells = <0>; + compatible = "amlogic, aml-spdif-dai"; + clocks = < + &clkc CLKID_MPLL1 + &clkc CLKID_IEC958_INT_COMP + &clkc CLKID_AMCLK_COMP + &clkc CLKID_IEC958_MUX + &clkc CLKID_CLK81 + &clkc CLKID_IEC958 + &clkc CLKID_IEC958_GATE + >; + clock-names = + "mpll1", + "i958", + "mclk", + "spdif", + "clk_81", + "iec958", + "iec958_amclk"; + }; + + pcm_dai: PCM { + #sound-dai-cells = <0>; + compatible = "amlogic, aml-pcm-dai"; + pinctrl-names = "audio_pcm"; + /* disable pcm pin mux temporary, enable it if necessary */ + /*pinctrl-0 = <&aml_audio_pcm>;*/ + clocks = < + &clkc CLKID_MPLL0 + &clkc CLKID_PCM_MCLK_COMP + &clkc CLKID_PCM_SCLK_COMP + >; + clock-names = "mpll0", "pcm_mclk", "pcm_sclk"; + pcm_mode = <1>; /* 0=slave mode, 1=master mode */ + }; + + i2s_plat: i2s_platform { + compatible = "amlogic, aml-i2s"; + interrupts = <0 29 1>; + }; + + pcm_plat: pcm_platform { + compatible = "amlogic, aml-pcm"; + }; + + spdif_codec: spdif_codec { + #sound-dai-cells = <0>; + compatible = "amlogic, aml-spdif-codec"; + status = "okay"; + pinctrl-names = "audio_spdif_out"; + pinctrl-0 = <&audio_spdif_out_pins>; + }; + + pcm_codec: pcm_codec { + #sound-dai-cells = <0>; + compatible = "amlogic, pcm2BT-codec"; + status = "okay"; + }; + /* endof AUDIO MESON8 DEVICES */ + + /* AUDIO board specific */ + dummy_codec:dummy { + #sound-dai-cells = <0>; + compatible = "amlogic, aml_dummy_codec"; + status = "disabled"; + }; + + amlogic_codec:t9015S { + #sound-dai-cells = <0>; + compatible = "amlogic, aml_codec_T9015S"; + status = "okay"; + reg = <0xc8832000 0x14>; + }; + + aml_snd_tv { + compatible = "amlogic, txl-snd-tv"; + status = "okay"; + aml-sound-card,format = "i2s"; + aml_sound_card,name = "AML-TVAUDIO"; + pinctrl-names = "audio_i2s"; + pinctrl-0 = <&aml_audio_i2s>; + /*avout mute gpio*/ + mute_gpio-gpios = <&gpio GPIODV_11 GPIO_ACTIVE_HIGH>; + sleep_time = <20>; + aux_dev = <&tas5707>; + cpu_list = <&cpudai0 &cpudai1 &cpudai2>; + codec_list = <&codec0 &codec1 &codec2>; + plat_list = <&i2s_plat &i2s_plat &pcm_plat>; + cpudai0: cpudai0 { + sound-dai = <&i2s_dai>; + }; + cpudai1: cpudai1 { + sound-dai = <&spdif_dai>; + }; + cpudai2: cpudai2 { + sound-dai = <&pcm_dai>; + }; + codec0: codec0 { + sound-dai = <&amlogic_codec>; + }; + codec1: codec1 { + sound-dai = <&spdif_codec>; + }; + codec2: codec2 { + sound-dai = <&pcm_codec>; + }; + Channel_Mask { + /*i2s has 4 pins, 8channel, mux output*/ + Speaker1_Channel_Mask = "i2s_2/3"; + DAC0_Channel_Mask = "i2s_0/1"; + }; + }; + + amaudio2 { + compatible = "amlogic, aml_amaudio2"; + status = "okay"; + interrupts = <0 48 1>; + }; + /* end of AUDIO_RELATED */ + + wifi { + compatible = "amlogic, aml_wifi"; + status = "okay"; + power_on_pin = <&gpio_ao GPIOAO_5 GPIO_ACTIVE_HIGH>; + }; +}; /* end of / */ + +&pinctrl_periphs { + /* start AUDIO_RELATED */ + /*i2s*/ + aml_audio_i2s: aml_audio_i2s { + mux { + groups = "i2s_amclk_z", + "i2s_aoclk_out_z", + "i2s_lrclk_out_z" + /*,"i2s_out_ch01_z"*/ + ,"i2s_out_ch23" + ; + function = "i2s"; + }; + }; + + /*spdif*/ + audio_spdif_out_pins: audio_spdif_out_pins { + mux { + groups = "spdif_out"; + function = "spdif_out"; + }; + }; + + /*pcm*/ + aml_audio_pcm: aml_audio_pcm { + mux { + groups = + "pcm_clk_a", + "pcm_fs_a", + "pcm_in_a", + "pcm_out_a"; + function = "pcm_a"; + }; + }; + /* end AUDIO_RELATED */ + + /*lcd_extern*/ + lcd_extern_off_pins:lcd_extern_off_pin { + mux { + pins = "GPIOH_2", + "GPIOH_3"; + function = "gpio_periphs"; + /*output-high;*/ + output-low; + /*input-enable;*/ + }; + }; + + /*backlight*/ + bl_pwm_off_pins:bl_pwm_off_pin { + mux { + pins = "GPIOZ_6"; + function = "gpio_periphs"; + output-low; + }; + }; + bl_pwm_combo_off_pins:bl_pwm_combo_off_pin { + mux { + pins = "GPIOZ_6", + "GPIOZ_7"; + function = "gpio_periphs"; + output-low; + }; + }; +}; + +&i2c0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_z_pins>; + + /* start AUDIO_RELATED */ + tas5707: tas5707@36 { + #sound-dai-cells = <0>; + compatible = "ti,tas5707"; + status = "okay"; + codec_name = "tas5707"; + reg = <0x1B>; + reset_pin = <&gpio GPIOZ_13 GPIO_ACTIVE_LOW>; + eq_enable = <0>; + drc_enable = <0>; + }; + /* end AUDIO_RELATED */ +}; + + +&i2c1 { + status = "okay"; + clock-frequency = <300000>; + pinctrl-names="default"; + pinctrl-0=<&i2c1_dv_pins>; +}; + +&i2c2 { + status = "okay"; + pinctrl-names="default"; + pinctrl-0=<&i2c2_h_pins>; + + lcd_extern_i2c0: lcd_extern_i2c@0 { + compatible = "lcd_ext, i2c"; + dev_name = "i2c_T5800Q"; + reg = <0x1c>; + status = "okay"; + }; +}; + +&dwc3 { + status = "okay"; +}; + +&usb2_phy { + status = "okay"; +}; + +&usb3_phy { + status = "okay"; +}; + +&dwc2_a { + status = "okay"; + /** 0: normal, 1: otg+dwc3 host only, 2: otg+dwc3 device only*/ + controller-type = <1>; +}; + +&audio_data{ + status = "okay"; +}; + +&pwm_ab { + status = "okay"; +}; + +&pwm_cd { + status = "okay"; +}; + +ðmac { + status = "okay"; +}; + +&spicc { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&spicc_pins>; + cs-gpios = <&gpio GPIOZ_3 0>; +}; + diff --git a/arch/arm/boot/dts/amlogic/txlx_t962e_r321.dts b/arch/arm/boot/dts/amlogic/txlx_t962e_r321.dts index 777fe5663043..36f67ec2d3b2 100644 --- a/arch/arm/boot/dts/amlogic/txlx_t962e_r321.dts +++ b/arch/arm/boot/dts/amlogic/txlx_t962e_r321.dts @@ -45,7 +45,7 @@ memory@00000000 { device_type = "memory"; - linux,usable-memory = <0x100000 0x7ff00000>; + linux,usable-memory = <0x000000 0x80000000>; }; reserved-memory { @@ -213,13 +213,13 @@ }; }; - dummy-battery { + amlogic_battery:dummy-battery { compatible = "amlogic, dummy-battery"; - status = "okay"; + status = "disabled"; }; - dummy-charger { + amlogic_charger:dummy-charger { compatible = "amlogic, dummy-charger"; - status = "okay"; + status = "disabled"; }; ethmac: ethernet@0xff3f0000 { @@ -792,7 +792,7 @@ compatible = "amlogic, unifykey"; status = "okay"; - unifykey-num = <18>; + unifykey-num = <21>; unifykey-index-0 = <&keysn_0>; unifykey-index-1 = <&keysn_1>; unifykey-index-2 = <&keysn_2>; @@ -811,6 +811,9 @@ unifykey-index-15 = <&keysn_15>; unifykey-index-16 = <&keysn_16>; unifykey-index-17 = <&keysn_17>; + unifykey-index-18 = <&keysn_18>; + unifykey-index-19 = <&keysn_19>; + unifykey-index-20 = <&keysn_20>; keysn_0: key_0{ key-name = "usid"; @@ -907,6 +910,21 @@ key-device = "normal"; key-permit = "read","write","del"; }; + keysn_18:key_18{ + key-name = "hdcp22_rprx_fw"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_19:key_19{ + key-name = "hdcp22_rprp_fw"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_20:key_20{ + key-name = "hdcp22_rp_private"; + key-device = "secure"; + key-permit = "read","write","del"; + }; }; /* End unifykey */ cvbsout { @@ -949,7 +967,7 @@ */ ic_type = <6>; //gpio_i2c_en = <0>; - //repeater_tx = <0x1>; + repeater_tx = <0x1>; //#address-cells = <2>; //#size-cells = <2>; //ranges; @@ -984,6 +1002,7 @@ cec_osd_string = "AML_TV"; /* Max Chars: 14 */ port_num = <4>; /*all port number*/ /*ee_cec;*/ + cec_sel = <2>; output = <1>; /*output port number*/ /*arc support port:bit 0-3, according to portmap*/ arc_port_mask = <0x8>; @@ -991,9 +1010,9 @@ 0 199 1>; interrupt-names = "hdmi_aocecb","hdmi_aocec"; pinctrl-names = "default","hdmitx_aocecb","cec_pin_sleep"; - pinctrl-0=<&hdmitx_aocec>; - pinctrl-1=<&hdmitx_aocecb>; - pinctrl-2=<&hdmitx_aocecb>; + pinctrl-0=<&hdmitx_aocec &hdmitx_aocecb1>; + pinctrl-1=<&hdmitx_aocec &hdmitx_aocecb1>; + pinctrl-2=<&hdmitx_aocec &hdmitx_aocecb1>; reg = <0xFF80023c 0x4 0xFF800000 0x400>; reg-names = "ao_exit","ao"; diff --git a/arch/arm/boot/dts/amlogic/txlx_t962e_r321_buildroot.dts b/arch/arm/boot/dts/amlogic/txlx_t962e_r321_buildroot.dts new file mode 100644 index 000000000000..89eee0fc8c10 --- /dev/null +++ b/arch/arm/boot/dts/amlogic/txlx_t962e_r321_buildroot.dts @@ -0,0 +1,1594 @@ +/* + * arch/arm/boot/dts/amlogic/txlx_t962e_r321.dts + * + * Copyright (C) 2017 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +/dts-v1/; +#include +#include + +#include "mesontxlx.dtsi" + +/ { + model = "Amlogic"; + amlogic-dt-id = "txlx_t962e_r321"; + compatible = "amlogic, txlx"; + interrupt-parent = <&gic>; + #address-cells = <1>; + #size-cells = <1>; + + aliases { + serial0 = &uart_AO; + serial1 = &uart_A; + serial2 = &uart_B; + serial3 = &uart_C; + serial4 = &uart_AO_B; + }; + + ion_dev { + compatible = "amlogic, ion_dev"; + memory-region = <&ion_reserved>; + }; + + memory@00000000 { + device_type = "memory"; + linux,usable-memory = <0x100000 0x7ff00000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + /* global autoconfigured region for contiguous allocations */ + ramoops@0x07400000 { + compatible = "ramoops"; + reg = <0x07400000 0x00100000>; + record-size = <0x8000>; + console-size = <0x8000>; + ftrace-size = <0x0>; + pmsg-size = <0x8000>; + }; + + secmon_reserved:linux,secmon { + compatible = "shared-dma-pool"; + reusable; + size = <0x400000>; + alignment = <0x400000>; + alloc-ranges = <0x05000000 0x400000>; + }; + + //secos_reserved:linux,secos { + // status = "disabled"; + // compatible = "amlogic, aml_secos_memory"; + // reg = <0x05300000 0x2000000>; + // no-map; + //}; + + + + ion_reserved:linux,ion-dev { + compatible = "shared-dma-pool"; + reusable; + size = <0x8000000>; + alignment = <0x400000>; + }; + + //carveout_reserved:linux,carveout-reserve { + // compatible = "amlogic, idev-mem"; + // size = <0x1000>; + //}; + + /*di CMA pool */ + di_cma_reserved:linux,di_cma { + compatible = "shared-dma-pool"; + reusable; + /* buffer_size = 3621952(yuv422 8bit) + * | 4736064(yuv422 10bit) + * | 4179008(yuv422 10bit full pack mode) + * 10x3621952=34.6M(0x23) support 8bit + * 10x4736064=45.2M(0x2e) support 12bit + * 10x4179008=40M(0x28) support 10bit + */ + size = <0x02800000>; + alignment = <0x400000>; + }; + + /* POST PROCESS MANAGER */ + ppmgr_reserved:linux,ppmgr { + compatible = "amlogic, ppmgr_memory"; + size = <0x0>; + }; + + codec_mm_cma:linux,codec_mm_cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x10400000>; + alignment = <0x400000>; + linux,contiguous-region; + }; + + picdec_cma_reserved:linux,picdec { + compatible = "shared-dma-pool"; + reusable; + size = <0x0>; + alignment = <0x0>; + linux,contiguous-region; + }; + + /* codec shared reserved */ + codec_mm_reserved:linux,codec_mm_reserved { + compatible = "amlogic, codec-mm-reserved"; + size = <0x0>; + alignment = <0x100000>; + //no-map; + }; + + demod_cma_reserved:linux,demod_cma { + compatible = "shared-dma-pool"; + reusable; + /* 5M */ + size = <0x0800000>; + alignment = <0x400000>; + }; + + /* vdin1 CMA pool */ + vdin1_cma_reserved:linux,vdin1_cma { + compatible = "shared-dma-pool"; + linux,phandle = <5>; + reusable; + /* 1920x1080x2x4 =16+4 M */ + size = <0x01400000>; + alignment = <0x400000>; + }; + + /*vbi reserved mem*/ + vbi_reserved:linux,vbi { + compatible = "amlogic, vbi-mem"; + size = <0x100000>; + alloc-ranges = <0x0 0x30000000>; + }; + }; + + /* for external keypad */ + adc_keypad { + compatible = "amlogic, adc_keypad"; + status = "okay"; + key_name = "power","up","down","enter","left","right","home"; + key_num = <7>; + io-channels = <&saradc SARADC_CH2>, + <&saradc SARADC_CH3>; + io-channel-names = "key-chan-2", "key-chan-3"; + key_chan = ; + key_code = <116 103 108 28 105 106 102>; + key_val = <0 143 266 389 512 143 266>; //val=voltage/1800mV*1023 + key_tolerance = <40 40 40 40 40 40 40>; + }; + + pwmleds { + compatible = "pwm-leds"; + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&pwmleds_pins>; + + sys { + active-low; + label = "sysled"; + max-brightness = <255>; + pwms = <&pwm_AO_ab 0 50000 0>; + }; + }; + + ethmac: ethernet@0xff3f0000 { + compatible = "amlogic, gxbb-eth-dwmac"; + status = "okay"; + reg = <0xff3f0000 0x10000 + 0xff634540 0x8 + 0xff634558 0xc + 0xffd01084 0x4>; + interrupts = <0 8 1 + 0 9 1>; + + phy-mode= "rmii"; + mc_val_internal_phy = <0x1804>; + mc_val_external_phy = <0x1621>; + interrupt-names = "macirq", + "phyirq"; + clocks = <&clkc CLKID_ETH_CORE>; + clock-names = "ethclk81"; + internal_phy = <1>; + }; + + vout { + compatible = "amlogic, vout"; + dev_name = "vout"; + status = "okay"; + fr_auto_policy = <0>; + }; + + meson-fb { + compatible = "amlogic, meson-txlx"; + dev_name = "meson-fb"; + status = "okay"; + interrupts = <0 3 1 + 0 89 1>; + interrupt-names = "viu-vsync", "rdma"; + mem_size = <0x00800000 0x01800000 0x00100000>; + /* uboot logo,fb0/fb1 memory size,if afbcd fb0=0x01851000*/ + display_mode_default = "1080p60hz"; + /* 0:VPU free scale 1:OSD free scale 2:OSD super scale */ + scale_mode = <1>; + /* 1920*1080*4*3 = 0x17BB000 */ + display_size_default = <1920 1080 1920 3240 32>; + pxp_mode = <0>; /** 0:normal mode 1:pxp mode */ + mem_alloc = <1>; + logo_addr = "0x7dc00000"; + }; + + ge2d { + compatible = "amlogic, ge2d-txlx"; + dev_name = "ge2d"; + status = "okay"; + interrupts = <0 150 1>; + interrupt-names = "ge2d"; + clocks = <&clkc CLKID_VAPB_MUX>, + <&clkc CLKID_G2D>, + <&clkc CLKID_GE2D_GATE>; + clock-names = "clk_vapb_0", + "clk_ge2d", + "clk_ge2d_gate"; + reg = <0xff940000 0x10000>; + }; + + codec_io { + compatible = "amlogic, codec_io"; + status = "okay"; + #address-cells=<1>; + #size-cells=<1>; + ranges; + io_cbus_base{ + reg = <0xffd00000 0x100000>; + }; + io_dos_base{ + reg = <0xff620000 0x10000>; + }; + io_hiubus_base{ + reg = <0xff63c000 0x2000>; + }; + io_aobus_base{ + reg = <0xff800000 0x10000>; + }; + io_vcbus_base{ + reg = <0xff900000 0x40000>; + }; + io_dmc_base{ + reg = <0xff638000 0x2000>; + }; + }; + + codec_mm { + compatible = "amlogic, codec, mm"; + memory-region = <&codec_mm_cma &codec_mm_reserved>; + dev_name = "codec_mm"; + status = "okay"; + }; + + mesonstream { + compatible = "amlogic, codec, streambuf"; + dev_name = "mesonstream"; + status = "okay"; + clocks = <&clkc CLKID_DOS_PARSER + &clkc CLKID_DEMUX + &clkc CLKID_DOS + &clkc CLKID_CLK81 + &clkc CLKID_VDEC_MUX + &clkc CLKID_HCODEC_MUX + &clkc CLKID_HEVC_MUX>; + clock-names = "parser_top", + "demux", + "vdec", + "clk_81", + "clk_vdec_mux", + "clk_hcodec_mux", + "clk_hevc_mux"; + }; + + vdec { + compatible = "amlogic, vdec"; + dev_name = "vdec.0"; + status = "okay"; + interrupts = <0 3 1 + 0 23 1 + 0 32 1 + 0 43 1 + 0 44 1 + 0 45 1>; + interrupt-names = "vsync", + "demux", + "parser", + "mailbox_0", + "mailbox_1", + "mailbox_2"; + }; + + meson-amvideom { + compatible = "amlogic, amvideom"; + dev_name = "amvideom"; + status = "okay"; + interrupts = <0 3 1>; + interrupt-names = "vsync"; + }; + + + + amvideocap { + compatible = "amlogic, amvideocap"; + dev_name = "amvideocap.0"; + status = "disabled"; + max_size = <8>;//8M + }; + + partitions: partitions{ + parts = <12>; + part-0 = <&logo>; + part-1 = <&recovery>; + part-2 = <&rsv>; + part-3 = <&tee>; + part-4 = <&crypt>; + part-5 = <&misc>; + part-6 = <&boot>; + part-7 = <&system>; + part-8 = <&cache>; + part-9 = <&vendor>; + part-10 = <&odm>; + part-11 = <&data>; + + logo:logo{ + pname = "logo"; + size = <0x0 0x2000000>; + mask = <1>; + }; + recovery:recovery{ + pname = "recovery"; + size = <0x0 0x2000000>; + mask = <1>; + }; + rsv:rsv{ + pname = "rsv"; + size = <0x0 0x800000>; + mask = <1>; + }; + tee:tee{ + pname = "tee"; + size = <0x0 0x800000>; + mask = <1>; + }; + crypt:crypt{ + pname = "crypt"; + size = <0x0 0x2000000>; + mask = <1>; + }; + misc:misc{ + pname = "misc"; + size = <0x0 0x2000000>; + mask = <1>; + }; + boot:boot + { + pname = "boot"; + size = <0x0 0x2000000>; + mask = <1>; + }; + system:system + { + pname = "system"; + size = <0x0 0x80000000>; + mask = <1>; + }; + vendor:vendor + { + pname = "vendor"; + size = <0x0 0x10000000>; + mask = <1>; + }; + odm:odm + { + pname = "odm"; + size = <0x0 0x10000000>; + mask = <1>; + }; + cache:cache + { + pname = "cache"; + size = <0x0 0x20000000>; + mask = <2>; + }; + data:data + { + pname = "data"; + size = <0xffffffff 0xffffffff>; + mask = <4>; + }; + }; + + ppmgr { + compatible = "amlogic, ppmgr"; + memory-region = <&ppmgr_reserved>; + dev_name = "ppmgr"; + status = "okay"; + }; + + deinterlace { + compatible = "amlogic, deinterlace"; + status = "okay"; + /* 0:use reserved; 1:use cma; 2:use cma as reserved */ + flag_cma = <1>; + //memory-region = <&di_reserved>; + memory-region = <&di_cma_reserved>; + interrupts = <0 46 1 + 0 6 1>; + interrupt-names = "de_irq"; + clocks = <&clkc CLKID_VPU_MUX>, + <&clkc CLKID_FCLK_DIV4>, + <&clkc CLKID_VPU_CLKB_TMP_COMP>, + <&clkc CLKID_VPU_CLKB_COMP>; + clock-names = "vpu_mux", + "fclk_div4", + "vpu_clkb_tmp_composite", + "vpu_clkb_composite"; + clock-range = <250 500>; + /* buffer-size = <3621952>;(yuv422 8bit) */ + buffer-size = <4179008>;/*yuv422 fullpack*/ + /* reserve-iomap = "true"; */ + /* if enable nr10bit, set nr10bit-support to 1 */ + nr10bit-support = <1>; + }; + ionvideo { + compatible = "amlogic, ionvideo"; + dev_name = "ionvideo"; + status = "okay"; + }; + + amlvideo { + compatible = "amlogic, amlvideo"; + dev_name = "amlvideo"; + status = "okay"; + }; + + amlvideo2_0 { + compatible = "amlogic, amlvideo2"; + dev_name = "amlvideo2"; + status = "okay"; + amlvideo2_id = <0>; + cma_mode = <1>; + }; + + amlvideo2_1 { + compatible = "amlogic, amlvideo2"; + dev_name = "amlvideo2"; + status = "okay"; + amlvideo2_id = <1>; + cma_mode = <1>; + }; + + hdmirx { + compatible = "amlogic, hdmirx_txlx"; + #address-cells=<1>; + #size-cells=<1>; + dev_name = "hdmirx"; + status = "okay"; + pinctrl-names = "hdmirx_pins"; + pinctrl-0 = <&hdmirx_a_mux &hdmirx_b_mux &hdmirx_d_mux>; + repeat = <0>; + interrupts = <0 56 1>; + clocks = <&clkc CLKID_HDMIRX_MODET_COMP>, + <&clkc CLKID_HDMIRX_CFG_COMP>, + <&clkc CLKID_HDMIRX_ACR_COMP>, + <&clkc CLKID_HDMIRX_AUDMEAS_COMP>, + <&xtal>, + <&clkc CLKID_FCLK_DIV5>, + <&clkc CLKID_FCLK_DIV7>, + <&clkc CLKID_HDCP22_SKP_COMP>, + <&clkc CLKID_HDCP22_ESM_COMP>; + // <&clkc CLK_AUD_PLL2FS>, + // <&clkc CLK_AUD_PLL4FS>, + // <&clkc CLK_AUD_OUT>; + clock-names = "hdmirx_modet_clk", + "hdmirx_cfg_clk", + "hdmirx_acr_ref_clk", + "hdmirx_audmeas_clk", + "xtal", + "fclk_div5", + "fclk_div7", + "hdcp_rx22_skp", + "hdcp_rx22_esm"; + // "hdmirx_aud_pll2fs", + // "hdmirx_aud_pll4f", + // "clk_aud_out"; + hdmirx_id = <0>; + en_4k_2_2k = <0>; + hpd_low_cec_off = <1>; + /* bit4: enable feature, bit3~0: port number */ + disable_port = <0x0>; + reg = <0xffd26000 0xa00000 + 0xff63C000 0x2000 + 0xffe0d000 0x2000 + 0xff63e000 0x2000 + 0x0 0x0 + 0xff634400 0x2000 + 0xff646000 0x2000>; + }; + + vdin0 { + compatible = "amlogic, vdin"; + /*memory-region = <&vdin0_cma_reserved>;*/ + dev_name = "vdin0"; + status = "okay"; + reserve-iomap = "true"; + /*bit0:(1:share with codec_mm;0:cma alone)*/ + /*bit8:(1:alloc in discontinus way;0:alone in continuous way)*/ + flag_cma = <0x101>; + /* MByte, if 10bit disable: 64M(YUV422), + * if 10bit enable: 64*1.5 = 96M(YUV422) + * if support 4K2K-YUV444-10bit-WR:3840*2160*4*4 ~= 128M + * if support 4K2K-YUV444-10bit-WR:3840*2160*4*6 ~= 190M + * if support 4K2K-YUV422-10bit-wr:3840*2160*3*4 ~= 96M + * if support 4K2K-YUV422-8BIT-WR:3840*2160*2*4 ~= 64M + * if support 1080p-YUV422-8BIT-WR:1920*1080*2*4 ~= 16M + */ + cma_size = <190>; + interrupts = <0 83 1>; + rdma-irq = <2>; + clocks = <&clkc CLKID_FCLK_DIV5>, + <&clkc CLKID_VDIN_MEAS_COMP>; + clock-names = "fclk_div5", "cts_vdin_meas_clk"; + vdin_id = <0>; + /* vdin write mem color depth support: + * bit0:support 8bit + * bit1:support 9bit + * bit2:support 10bit + * bit3:support 12bit + * bit4:support yuv422 10bit full pack mode (from txl new add) + */ + tv_bit_mode = <21>; + }; + + vdin1 { + compatible = "amlogic, vdin"; + memory-region = <&vdin1_cma_reserved>; + dev_name = "vdin1"; + status = "okay"; + reserve-iomap = "true"; + flag_cma = <0>;/*1:share with codec_mm;0:cma alone*/ + interrupts = <0 85 1>; + rdma-irq = <4>; + clocks = <&clkc CLKID_FCLK_DIV5>, + <&clkc CLKID_VDIN_MEAS_COMP>; + clock-names = "fclk_div5", "cts_vdin_meas_clk"; + vdin_id = <1>; + /* vdin write mem color depth support: + * bit0:support 8bit + * bit1:support 9bit + * bit2:support 10bit + * bit3:support 12bit + */ + tv_bit_mode = <1>; + }; + + tvafe { + compatible = "amlogic, tvafe-txlx"; + /*memory-region = <&tvafe_cma_reserved>;*/ + dev_name = "tvafe"; + status = "okay"; + flag_cma = <1>;/*1:share with codec_mm;0:cma alone*/ + cma_size = <5>;/*MByte*/ + reg = <0xff642000 0x2000>;/*tvafe reg base*/ + reserve-iomap = "true"; + tvafe_id = <0>; + //pinctrl-names = "default"; + /*!!particular sequence, no more and no less!!!*/ + tvafe_pin_mux = < + 3 /* TVAFE_CVBS_IN2, CVBS_IN0 = 0 */ + 1 /* TVAFE_CVBS_IN0, CVBS_IN1 */ + 2 /* TVAFE_CVBS_IN1, CVBS_IN2 */ + 4 /* TVAFE_CVBS_IN3, CVBS_IN3 */ + >; + clocks = <&clkc CLKID_DAC_CLK>; + clock-names = "vdac_clk_gate"; + }; + + vbi { + compatible = "amlogic, vbi"; + memory-region = <&vbi_reserved>; + dev_name = "vbi"; + status = "okay"; + interrupts = <0 83 1>; + reserve-iomap = "true"; + }; + + tvafe_avin_detect { + compatible = "amlogic, tvafe_avin_detect"; + dev_name = "tvafe_avin_detect"; + status = "okay"; + device_mask = <1>;/*bit0:ch1;bit1:ch2*/ + interrupts = <0 12 1>, + <0 13 1>; + }; + + amlvecm { + compatible = "amlogic, vecm"; + dev_name = "aml_vecm"; + status = "okay"; + gamma_en = <0>;/*1:enabel ;0:disable*/ + wb_en = <0>;/*1:enabel ;0:disable*/ + cm_en = <0>;/*1:enabel ;0:disable*/ + wb_sel = <0>;/*1:mtx ;0:gainoff*/ + /*0: 709/601 1: bt2020*/ + tx_op_color_primary = <0>; + /*1:enabel osd lut 100 table;0:disable*/ + cfg_en_osd_100 = <1>; + + vlock_en = <0>;/*1:enable;0:disable*/ + vlock_mode = <0x4>; + /* vlock work mode: + *bit0:auto ENC + *bit1:auto PLL + *bit2:manual PLL + *bit3:manual ENC + *bit4:manual soft ENC + *bit5:manual MIX PLL ENC + */ + vlock_pll_m_limit = <1>; + vlock_line_limit = <3>; + }; + amdolby_vision { + compatible = "amlogic, dolby_vision_txlx"; + dev_name = "aml_amdolby_vision_driver"; + status = "okay"; + tv_mode = <0>;/*1:enabel ;0:disable*/ + }; + amvenc_avc { + compatible = "amlogic, amvenc_avc"; + //memory-region = <&amvenc_avc_reserved>; + //memory-region = <&avc_cma_reserved>; + dev_name = "amvenc_avc"; + status = "okay"; + interrupts = <0 45 1>; + interrupt-names = "mailbox_2"; + }; + + tuner: tuner { + status = "okay"; + tuner_name = "si2151_tuner"; + tuner_i2c_adap = <&i2c1>; + tuner_i2c_addr = <0x60>; + /* tuner_xtal = <0>; */ /* unuse for si2151 */ + /* tuner_xtal_mode = <0>; */ + /* tuner_xtal_cap = <0>; */ + }; + + atv-demod { + compatible = "amlogic, atv-demod"; + status = "okay"; + tuner = <&tuner>; + btsc_sap_mode = <1>; + /* pinctrl-names="atvdemod_agc_pins"; */ + /* pinctrl-0=<&atvdemod_agc_pins>; */ + reg = <0xff640000 0x2000 /* demod reg */ + 0xff63c000 0x2000 /* hiu reg */ + 0xff634000 0x2000 /* periphs reg */ + 0xff648000 0x2000>; /* audio reg */ + reg_23cf = <0x88188832>; + /*default:0x88188832;r840 on haier:0x48188832*/ + }; + + bt-dev { + compatible = "amlogic, bt-dev"; + dev_name = "bt-dev"; + status = "okay"; + gpio_reset = <&gpio_ao GPIOAO_13 GPIO_ACTIVE_HIGH>; + //gpio_en = <&gpio_ao GPIOAO_5 GPIO_ACTIVE_HIGH>; + }; + + rtc { + compatible = "amlogic, aml_vrtc"; + alarm_reg_addr = <0xff8000a8>; + timer_e_addr = <0xffd0f188>; + init_date = "2015/01/01"; + status = "okay"; + }; + + wifi { + compatible = "amlogic, aml_wifi"; + dev_name = "aml_wifi"; + status = "okay"; + interrupt_pin = <&gpio_ao GPIOAO_4 GPIO_ACTIVE_HIGH>; + interrupts = <0 68 4>; + irq_trigger_type = "GPIO_IRQ_HIGH"; + dhd_static_buf; + power_on_pin = <&gpio_ao GPIOAO_5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_32k_pins>; + pwm_config = <&wifi_pwm_conf>; + }; + + wifi_pwm_conf: wifi_pwm_conf { + pwm_channel1_conf { + pwms = <&pwm_cd MESON_PWM_1 30040 0>; + duty-cycle = <15020>; + times = <10>; + }; + pwm_channel2_conf { + pwms = <&pwm_cd MESON_PWM_3 30030 0>; + duty-cycle = <15015>; + times = <12>; + }; + }; + + sd_emmc_c: emmc@ffe07000 { + status = "okay"; + compatible = "amlogic, meson-mmc-txlx"; + reg = <0xffe07000 0x2000>; + interrupts = <0 218 1>; + pinctrl-names = "emmc_clk_cmd_pins", "emmc_all_pins"; + pinctrl-0 = <&emmc_clk_cmd_pins>; + pinctrl-1 = <&emmc_conf_pull_up &emmc_conf_pull_done>; + clocks = <&clkc CLKID_SD_EMMC_C>, + <&clkc CLKID_SD_EMMC_C_P0_COMP>, + <&clkc CLKID_FCLK_DIV2>, + <&clkc CLKID_FCLK_DIV5>, + <&xtal>; + clock-names = "core", "clkin0", "clkin1", "clkin2", "xtal"; + + bus-width = <8>; + cap-sd-highspeed; + cap-mmc-highspeed; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + + max-frequency = <200000000>; + non-removable; + disable-wp; + emmc { + status = "disabled"; + pinname = "emmc"; + ocr_avail = <0x200080>; /**VDD voltage 3.3 ~ 3.4 */ + caps = "MMC_CAP_8_BIT_DATA", + "MMC_CAP_MMC_HIGHSPEED", + "MMC_CAP_SD_HIGHSPEED", + "MMC_CAP_NONREMOVABLE", + "MMC_CAP_1_8V_DDR", + "MMC_CAP_HW_RESET", + "MMC_CAP_ERASE", + "MMC_CAP_CMD23"; + caps2 = "MMC_CAP2_HS200", "MMC_CAP2_HS400"; + f_min = <400000>; + f_max = <200000000>; + max_req_size = <0x20000>; /**128KB*/ + gpio_dat3 = <&gpio BOOT_3 GPIO_ACTIVE_HIGH>; + hw_reset = <&gpio BOOT_9 GPIO_ACTIVE_HIGH>; + card_type = <1>; + /* 1:mmc card(include eMMC), + * 2:sd card(include tSD) + */ + }; + }; + + sd_emmc_b: sd@ffe05000 { + status = "okay"; + compatible = "amlogic, meson-mmc-txlx"; + reg = <0xffe05000 0x2000>; + interrupts = <0 217 4>; + pinctrl-names = "sd_clk_cmd_pins", "sd_all_pins"; + pinctrl-0 = <&sd_clk_cmd_pins>; + pinctrl-1 = <&sd_all_pins>; + clocks = <&clkc CLKID_SD_EMMC_B>, + <&clkc CLKID_SD_EMMC_B_P0_COMP>, + <&clkc CLKID_FCLK_DIV2>, + <&clkc CLKID_FCLK_DIV5>, + <&xtal>; + clock-names = "core", "clkin0", "clkin1", "clkin2", "xtal"; + + bus-width = <4>; + cap-sd-highspeed; + cap-mmc-highspeed; + max-frequency = <100000000>; + non-removable; + disable-wp; + sd { + status = "disabled"; + pinname = "sd"; + ocr_avail = <0x200080>; /**VDD voltage 3.3 ~ 3.4 */ + caps = "MMC_CAP_4_BIT_DATA", + "MMC_CAP_MMC_HIGHSPEED", + "MMC_CAP_SD_HIGHSPEED", + "MMC_CAP_NONREMOVABLE", + "MMC_CAP_UHS_SDR12", + "MMC_CAP_UHS_SDR25", + "MMC_CAP_UHS_SDR50", + "MMC_CAP_UHS_SDR104", + "MMC_PM_KEEP_POWER", + "MMC_CAP_SDIO_IRQ"; + f_min = <400000>; + f_max = <200000000>; + max_req_size = <0x20000>; /**128KB*/ + card_type = <3>; + /* 3:sdio device(ie:sdio-wifi), + * 4:SD combo (IO+mem) card + * 5:NON sdio device(means sd/mmc card) + */ + }; + }; + + unifykey { + compatible = "amlogic, unifykey"; + status = "okay"; + + unifykey-num = <17>; + unifykey-index-0 = <&keysn_0>; + unifykey-index-1 = <&keysn_1>; + unifykey-index-2 = <&keysn_2>; + unifykey-index-3 = <&keysn_3>; + unifykey-index-4 = <&keysn_4>; + unifykey-index-5 = <&keysn_5>; + unifykey-index-6 = <&keysn_6>; + unifykey-index-7 = <&keysn_7>; + unifykey-index-8 = <&keysn_8>; + unifykey-index-9 = <&keysn_9>; + unifykey-index-10= <&keysn_10>; + unifykey-index-11 = <&keysn_11>; + unifykey-index-12 = <&keysn_12>; + unifykey-index-13 = <&keysn_13>; + unifykey-index-14 = <&keysn_14>; + unifykey-index-15 = <&keysn_15>; + unifykey-index-16 = <&keysn_16>; + + keysn_0: key_0{ + key-name = "usid"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_1:key_1{ + key-name = "mac"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_2:key_2{ + key-name = "hdcp"; + key-device = "secure"; + key-type = "sha1"; + key-permit = "read","write","del"; + }; + keysn_3:key_3{ + key-name = "secure_boot_set"; + key-device = "efuse"; + key-permit = "write"; + }; + keysn_4:key_4{ + key-name = "mac_bt"; + key-device = "normal"; + key-permit = "read","write","del"; + key-type = "mac"; + }; + keysn_5:key_5{ + key-name = "mac_wifi"; + key-device = "normal"; + key-permit = "read","write","del"; + key-type = "mac"; + }; + keysn_6:key_6{ + key-name = "hdcp2_tx"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_7:key_7{ + key-name = "hdcp2_rx"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_8:key_8{ + key-name = "widevinekeybox"; + key-device = "secure"; + key-type = "sha1"; + key-permit = "read","write","del"; + }; + keysn_9:key_9{ + key-name = "deviceid"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_10:key_10{ + key-name = "hdcp22_fw_private"; + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_11:key_11{ + key-name = "hdcp22_rx_private"; + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_12:key_12{ + key-name = "hdcp22_rx_fw"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_13:key_13{ + key-name = "hdcp14_rx"; + key-device = "normal"; + key-type = "sha1"; + key-permit = "read","write","del"; + }; + keysn_14:key_14{ + key-name = "prpubkeybox";// PlayReady + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_15:key_15{ + key-name = "prprivkeybox";// PlayReady + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_16:key_16{ + key-name = "attestationkeybox";// attestation key + key-device = "secure"; + key-permit = "read","write","del"; + }; + }; /* End unifykey */ + + cvbsout { + compatible = "amlogic, cvbsout-txlx"; + dev_name = "cvbsout"; + status = "disabled"; + clocks = <&clkc CLKID_VCLK2_ENCI + &clkc CLKID_VCLK2_VENCI0 + &clkc CLKID_VCLK2_VENCI1 + &clkc CLKID_DAC_CLK>; + clock-names = "venci_top_gate", + "venci_0_gate", + "venci_1_gate", + "vdac_clk_gate"; + + /* performance: reg_address, reg_value */ + performance = <0x1b56 0x343 + 0x1b05 0xf4 + 0x1c59 0xfc48 + 0x1b12 0x8c00 + 0xffff 0x0>; /* ending flag */ + }; + + amhdmitx: amhdmitx { + compatible = "amlogic, amhdmitx"; + dev_name = "amhdmitx"; + status = "okay"; + pinctrl-names="default", "hdmitx_i2c"; + pinctrl-0=<&hdmitx_hpd &hdmitx_ddc>; + pinctrl-1=<&hdmitx_hpd_gpio &i2c2_h_pins>; + clocks = <&clkc CLKID_HDCP22_SKP_COMP>, + <&clkc CLKID_HDCP22_ESM_COMP>; + clock-names = "hdcp22_tx_skp", + "hdcp22_tx_esm"; + /* HPD, 57 + 32 = 89; CEC, 151 + 32 = 183*/ + interrupts = <0 57 1>; + interrupt-names = "hdmitx_hpd"; + /* 0:M8B 1:GXBB 2:GXTVBB 3:GXL 4:GXM + * 5:TXL 6:TXLX 7:AXG 8:GXLX 9:TXHD + */ + ic_type = <6>; + //gpio_i2c_en = <0>; + //repeater_tx = <0x1>; + //#address-cells = <2>; + //#size-cells = <2>; + //ranges; + }; + + i2c_gpio: i2c_gpio { + compatible = "i2c-gpio"; + dev_name = "i2c-gpio"; + status = "disabled"; + i2c-gpio,delay-us = <10>; /* 50 kHz */ + gpios = <&gpio GPIOH_2 0 + &gpio GPIOH_3 0>; + #address-cells = <2>; + #size-cells = <2>; + i2c-gpio,timeout-ms = <10>; + i2c_gpio_edid: i2c_gpio_edid { + compatible = "i2c-gpio"; + reg = <0x50 0x0 0x0 0x0>; + }; + }; + + aocec: aocec { + compatible = "amlogic, aocec-txlx"; + device_name = "aocec"; + status = "okay"; + vendor_name = "Amlogic"; /* Max Chars: 8 */ + /* Refer to the following URL at: + * http://standards.ieee.org/develop/regauth/oui/oui.txt + */ + vendor_id = <0x000000>; + product_desc = "TXLX"; /* Max Chars: 16 */ + cec_osd_string = "AML_TV"; /* Max Chars: 14 */ + port_num = <4>; /*all port number*/ + /*ee_cec;*/ + output = <1>; /*output port number*/ + /*arc support port:bit 0-3, according to portmap*/ + arc_port_mask = <0x8>; + interrupts = <0 205 1 + 0 199 1>; + interrupt-names = "hdmi_aocecb","hdmi_aocec"; + pinctrl-names = "default","hdmitx_aocecb","cec_pin_sleep"; + pinctrl-0=<&hdmitx_aocec>; + pinctrl-1=<&hdmitx_aocecb>; + pinctrl-2=<&hdmitx_aocecb>; + reg = <0xFF80023c 0x4 + 0xFF800000 0x400>; + reg-names = "ao_exit","ao"; + }; + + + canvas { + compatible = "amlogic, meson, canvas"; + dev_name = "amlogic-canvas"; + status = "okay"; + reg = <0xff638000 0x2000>; + }; + + rdma { + compatible = "amlogic, meson, rdma"; + dev_name = "amlogic-rdma"; + status = "okay"; + interrupts = <0 89 1>; + interrupt-names = "rdma"; + }; + + dwc3: dwc3@ff500000 { + compatible = "synopsys, dwc3"; + status = "okay"; + reg = <0xff500000 0x100000>; + interrupts = <0 30 4>; + usb-phy = <&usb2_phy>, <&usb3_phy>; + cpu-type = "gxl"; + clock-src = "usb3.0"; + }; + + usb2_phy: usb2phy@ffe09000 { + compatible = "amlogic, amlogic-new-usb2"; + status = "okay"; + portnum = <4>; + reg = <0xffe09000 0x80 + 0xffd01008 0x4>; + }; + + usb3_phy: usb3phy@ffe09080 { + compatible = "amlogic, amlogic-new-usb3"; + status = "okay"; + portnum = <0>; + reg = <0xffe09080 0x20>; + }; + + dwc2_a { + compatible = "amlogic, dwc2"; + device_name = "dwc2_a"; + reg = <0xff400000 0x40000>; + status = "okay"; + interrupts = <0 31 4>; + pl-periph-id = <0>; /** lm name */ + clock-src = "usb0"; /** clock src */ + port-id = <0>; /** ref to mach/usb.h */ + port-type = <2>; /** 0: otg, 1: host, 2: slave */ + port-speed = <0>; /** 0: default, high, 1: full */ + port-config = <0>; /** 0: default */ + /*0:default,1:single,2:incr,3:incr4,4:incr8,5:incr16,6:disable*/ + port-dma = <0>; + port-id-mode = <0>; /** 0: hardware, 1: sw_host, 2: sw_slave*/ + usb-fifo = <728>; + cpu-type = "gxl"; + /** 0: normal, 1: otg+dwc3 host only, 2: otg+dwc3 device only*/ + controller-type = <1>; + phy-reg = <0xffe09000>; + phy-reg-size = <0xa0>; + clocks = <&clkc CLKID_USB_GENERAL + &clkc CLKID_USB1_TO_DDR>; + clock-names = "usb_general", + "usb1"; + }; + + /* Sound iomap */ + aml_snd_iomap { + compatible = "amlogic, meson-snd-iomap"; + status = "okay"; + #address-cells=<1>; + #size-cells=<1>; + ranges; + io_audin_base { + reg = <0xffd03000 0x100000>; + }; + io_aiu_base { + reg = <0xFFCFFC00 0x100000>; + }; + io_eqdrc_base { + reg = <0xFFCFF000 0x100000>; + }; + io_hiu_reset_base { + reg = <0xFFCFCC00 0x100000>; + }; + io_isa_base { + reg = <0xFFD05800 0x100000>; + }; + }; + + /* AUDIO DEVICES */ + i2s_dai: I2S { + #sound-dai-cells = <0>; + /* config mpll whether same with audin */ + clocks = <&clkc CLKID_MPLL3>, + <&clkc CLKID_AMCLK_COMP>, + <&clkc CLKID_AIU_GLUE>, + <&clkc CLKID_I2S_OUT>, + <&clkc CLKID_AMCLK_MEASURE>, + <&clkc CLKID_AIFIFO2>, + <&clkc CLKID_MIXER>, + <&clkc CLKID_MIXER_IFACE>, + <&clkc CLKID_ADC>, + <&clkc CLKID_AIU_TOP>, + <&clkc CLKID_AOCLK_GATE>, + <&clkc CLKID_I2S_SPDIF>, + <&clkc CLKID_DAC_CLK>; + clock-names = "mpll", + "mclk", + "top_glue", + "i2s_out", + "amclk_measure", + "aififo2", + "aud_mixer", + "mixer_reg", + "adc", + "top_level", + "aoclk", + "aud_in", + "vdac_clk"; + compatible = "amlogic, aml-i2s-dai"; + }; + + i2s2_dai: I2S2 { + #sound-dai-cells = <0>; + /* config mpll whether same with aiu */ + clocks = <&clkc CLKID_MPLL2>, + <&clkc CLKID_AUDIN_MCLK_COMP>, + <&clkc CLKID_AUDIN_SCLK_COMP>, + <&clkc CLKID_AUDIN_LRCLK_COMP>; + clock-names = "audin_mpll", + "audin_mclk", + "audin_sclk", + "audin_lrclk"; + compatible = "amlogic, aml-i2s2-dai"; + }; + + spdif_dai: SPDIF { + #sound-dai-cells = <0>; + compatible = "amlogic, aml-spdif-dai"; + clocks = <&clkc CLKID_MPLL1>, + <&clkc CLKID_IEC958_INT_COMP>, + <&clkc CLKID_AMCLK_COMP>, + <&clkc CLKID_IEC958_MUX>, + <&clkc CLKID_CLK81>, + <&clkc CLKID_IEC958>, + <&clkc CLKID_IEC958_GATE>; + clock-names = + "mpll1", + "i958", + "mclk", + "spdif", + "clk_81", + "iec958", + "iec958_amclk"; + }; + + pcm_dai: PCM { + #sound-dai-cells = <0>; + compatible = "amlogic, aml-pcm-dai"; + pinctrl-names = "audio_pcm"; + /* disable pcm pin mux temporary, enable it if necessary */ + /*pinctrl-0 = <&aml_audio_pcm>;*/ + clocks = <&clkc CLKID_MPLL0>, + <&clkc CLKID_PCM_MCLK_COMP>, + <&clkc CLKID_PCM_SCLK_COMP>; + clock-names = "mpll0", "pcm_mclk", "pcm_sclk"; + pcm_mode = <1>; /* 0=slave mode, 1=master mode */ + }; + + i2s_plat: i2s_platform { + compatible = "amlogic, aml-i2s"; + interrupts = <0 29 1>; + }; + + pcm_plat: pcm_platform { + compatible = "amlogic, aml-pcm"; + }; + + spdif_codec: spdif_codec{ + #sound-dai-cells = <0>; + compatible = "amlogic, aml-spdif-codec"; + pinctrl-names = "audio_spdif_out", + "audio_spdif_out_mute", + "audio_spdif_in", + "audio_spdif_in_mute"; + pinctrl-0 = <&audio_spdif_out_pins>; + pinctrl-1 = <&audio_spdif_out_mute_pins>; + pinctrl-2 = <&audio_spdif_in_pins>; + pinctrl-3 = <&audio_spdif_in_mute_pins>; + }; + + pcm_codec: pcm_codec{ + #sound-dai-cells = <0>; + compatible = "amlogic, pcm2BT-codec"; + }; + /* end of AUDIO DEVICES */ + + /* AUDIO board specific */ + dummy_codec:dummy{ + #sound-dai-cells = <0>; + compatible = "amlogic, aml_dummy_codec"; + status = "okay"; + }; + + amlogic_codec:txlx_acodec{ + #sound-dai-cells = <0>; + compatible = "amlogic, txlx_acodec"; + reg = <0xFF632000 0x1c>; + status = "okay"; + }; + + aml_snd_tv { + compatible = "amlogic, txlx-snd-tv"; + status = "okay"; + aml-sound-card,format = "i2s"; + aml_sound_card,name = "AML-TVAUDIO"; + pinctrl-names = "audio_i2s"; + pinctrl-0 = <&aml_audio_i2s>; + /*avout mute gpio*/ + mute_gpio-gpios = <&gpio GPIOZ_7 GPIO_ACTIVE_HIGH>; + /*switch ARC_IN & SPDIF_IN*/ + source_switch-gpios = <&gpio GPIOZ_4 GPIO_ACTIVE_HIGH>; + /*analog amp mute*/ + /*amp_mute_gpio-gpios = <&gpio GPIOZ_18 GPIO_ACTIVE_LOW>;*/ + aux_dev = <&tas5707>; + cpu_list = <&cpudai0 &cpudai1 &cpudai2 &cpudai3>; + codec_list = <&codec0 &codec1 &codec2 &codec3>; + plat_list = <&i2s_plat &i2s_plat &pcm_plat &i2s_plat>; + cpudai0: cpudai0 { + sound-dai = <&i2s_dai>; + }; + cpudai1: cpudai1 { + sound-dai = <&spdif_dai>; + }; + cpudai2: cpudai2 { + sound-dai = <&pcm_dai>; + }; + cpudai3: cpudai3 { + sound-dai = <&i2s2_dai>; + }; + codec0: codec0 { + sound-dai = <&amlogic_codec>; + }; + codec1: codec1 { + sound-dai = <&spdif_codec>; + }; + codec2: codec2 { + sound-dai = <&pcm_codec>; + }; + codec3: codec3 { + sound-dai = <&dummy_codec>; + }; + Channel_Mask { + /*i2s has 4 pins, 8channel, mux output*/ + Speaker0_Channel_Mask = "i2s_2/3"; + DAC0_Channel_Mask = "i2s_2/3"; + DAC1_Channel_Mask = "i2s_2/3"; + EQ_DRC_Channel_Mask = "i2s_2/3"; + Spdif_samesource_Channel_Mask = "i2s_0/1"; + }; + }; + + amaudio2 { + compatible = "amlogic, aml_amaudio2"; + status = "okay"; + interrupts = <0 48 1>; + }; + /* end of AUDIO board specific */ + + aml_sensor0: aml-sensor@0 { + compatible = "amlogic, aml-thermal"; + device_name = "thermal"; + status = "disabled"; + #thermal-sensor-cells = <1>; + cooling_devices { + cpufreq_cool_cluster0 { + min_state = <1000000>; + dyn_coeff = <140>; + cluster_id = <0>; + node_name = "cpus"; + device_type = "cpufreq"; + }; + cpucore_cool_cluster0 { + min_state = <1>; + dyn_coeff = <0>; + cluster_id = <0>; + node_name = "cpu_core_cluster0"; + device_type = "cpucore"; + }; + gpufreq_cool { + min_state = <400>; + dyn_coeff = <437>; + cluster_id = <0>; + node_name = "mali"; + device_type = "gpufreq"; + }; + gpucore_cool { + min_state = <1>; + dyn_coeff = <0>; + cluster_id = <0>; + node_name = "thermal_gpu_cores"; + device_type = "gpucore"; + }; + }; + cpu_cluster0:cpu_core_cluster0 { + #cooling-cells = <2>; /* min followed by max */ + }; + gpucore:thermal_gpu_cores { + #cooling-cells = <2>; /* min followed by max */ + }; + }; + + dvb { + compatible = "amlogic, dvb"; + dev_name = "dvb"; + status = "okay"; + fe0_mode = "internal"; + fe0_tuner = <&tuner>; + + /*"parallel","serial","disable"*/ + ts2 = "parallel"; + ts2_control = <0>; + ts2_invert = <0>; + interrupts = <0 23 1 + 0 5 1 + 0 53 1 + 0 19 1 + 0 25 1 + 0 18 1 + 0 24 1>; + interrupt-names = "demux0_irq", + "demux1_irq", + "demux2_irq", + "dvr0_irq", + "dvr1_irq", + "dvrfill0_fill", + "dvrfill1_flush"; + clocks = <&clkc CLKID_DEMUX + &clkc CLKID_ASYNC_FIFO + &clkc CLKID_AHB_ARB0 + &clkc CLKID_DOS_PARSER>; + clock-names = "demux", "asyncfifo", "ahbarb0", "uparsertop"; + }; + aml_dtv_demod { + compatible = "amlogic, ddemod-txlx"; + dev_name = "aml_dtv_demod"; + status = "okay"; + + //pinctrl-names="dtvdemod_agc"; + //pinctrl-0=<&dtvdemod_agc>; + + clocks = <&clkc CLKID_DAC_CLK>; + clock-names = "vdac_clk_gate"; + + reg = <0xff644000 0x2000 /*dtv demod base*/ + 0xff63c000 0x2000 /*hiu reg base*/ + 0xff800000 0x1000 /*io_aobus_base*/ + 0xffd01000 0x1000 /*reset*/ + >; + /*move from dvbfe*/ + dtv_demod0_mem = <0>; // need move to aml_dtv_demod ? + spectrum = <1>; + cma_flag = <1>; + cma_mem_size = <8>; + memory-region = <&demod_cma_reserved>;//<&demod_reserved>; + }; + dvbfe { + compatible = "amlogic, dvbfe"; + dev_name = "dvbfe"; + status = "disabled"; + dtv_demod0 = "AMLDEMOD"; + fe0_dtv_demod = <0>; + fe0_ts = <2>; + fe0_dev = <0>; + dtv_demod0_mem = <0>; + dtv_demod0_spectrum = <1>; + dtv_demod0_cma_flag = <1>; + dtv_demod0_cma_mem_size = <8>; + memory-region = <&demod_cma_reserved>;//<&demod_reserved>; + tuner0 = "si2151_tuner"; + tuner0_i2c_adap_id = <2>; + tuner0_i2c_addr = <0x60>; + //tuner0_reset_value = <0>; + //tuner0_reset_gpio = "GPIOY_10" ; /*GPIOX_8 76*/ + fe0_tuner = <0>; + atv_demod0 = "aml_atv_demod"; + fe0_atv_demod = <0>; + }; + + thermal-zones { + soc_thermal { + polling-delay = <1000>; + polling-delay-passive = <100>; + sustainable-power = <2150>; + + thermal-sensors = <&aml_sensor0 3>; + + trips { + switch_on: trip-point@0 { + temperature = <70000>; + hysteresis = <1000>; + type = "passive"; + }; + control: trip-point@1 { + temperature = <80000>; + hysteresis = <1000>; + type = "passive"; + }; + hot: trip-point@2 { + temperature = <85000>; + hysteresis = <5000>; + type = "hot"; + }; + critical: trip-point@3 { + temperature = <260000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + + cooling-maps { + cpufreq_cooling_map { + trip = <&control>; + cooling-device = <&cpus 0 4>; + contribution = <1024>; + }; + cpucore_cooling_map { + trip = <&control>; + cooling-device = <&cpu_cluster0 0 3>; + contribution = <1024>; + }; + gpufreq_cooling_map { + trip = <&control>; + //cooling-device = <&gpu 0 4>; + contribution = <1024>; + }; + gpucore_cooling_map { + trip = <&control>; + cooling-device = <&gpucore 0 2>; + contribution = <1024>; + }; + }; + }; + }; + +}; /* end of / */ + +&i2c0 { + status = "okay"; + pinctrl-names="default"; + pinctrl-0=<&i2c0_z_pins>; + + tas5707: tas5707@36 { + compatible = "ti,tas5707"; + #sound-dai-cells = <0>; + codec_name = "tas5707"; + reg = <0x1B>; + reset_pin = <&gpio GPIOZ_13 GPIO_ACTIVE_LOW>; + eq_enable = <0>; + drc_enable = <0>; + status = "okay"; + }; +}; + +&i2c1 { + status = "okay"; + clock-frequency = <300000>; + pinctrl-names="default"; + pinctrl-0=<&i2c1_dv_pins>; +}; + +&pinctrl_periphs { + /*i2s*/ + aml_audio_i2s: aml_audio_i2s { + mux { + groups = "i2s_mclk_z", + "i2s_sclk_z", + "i2s_lrclk_z", + "i2s_dout01_z" + //, "i2s_dout23_z15" + //, "i2s_dout45_z" + //, "i2s_dout67_z19" + //, "i2s_din01_h6" + //, "i2s_din23_h5" + //, "i2s_din23_h5" + //, "i2s_din67_h0" + ; + function = "i2s"; + }; + }; + /*spdif*/ + audio_spdif_out_pins: audio_spdif_out_pins { + mux { + groups = "spdif_out_z"; + function = "spdif_out"; + }; + }; + audio_spdif_out_mute_pins: audio_spdif_out_mute_pins { + mux { + groups = "GPIOZ_17"; + function = "gpio_periphs"; + }; + }; + audio_spdif_in_pins: audio_spdif_in_pins { + mux { + groups = "spdif_in_z18"; + function = "spdif_in"; + }; + }; + audio_spdif_in_mute_pins: audio_spdif_in_mute_pins { + mux { + groups = "GPIOZ_18"; + function = "gpio_periphs"; + }; + }; + /*pcm*/ + aml_audio_pcm: aml_audio_pcm { + mux { + groups = + "pcm_clk_a_dv", + "pcm_fs_a_dv", + "pcm_in_a_dv", + "pcm_out_a_dv"; + function = "pcm_a"; + }; + }; + +}; + +&uart_A { + status = "okay"; +}; + +&audio_data{ + status = "okay"; +}; + +&pwm_AO_ab { + status = "okay"; +}; + +&pwm_cd { + status = "okay"; +}; + + +&spicc0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&spi_a_pins>; + cs-gpios = <&gpio GPIOZ_3 0>; +}; diff --git a/arch/arm/boot/dts/amlogic/txlx_t962x_r311_1g.dts b/arch/arm/boot/dts/amlogic/txlx_t962x_r311_1g.dts index 2c5963c68ac0..7e057d94586d 100644 --- a/arch/arm/boot/dts/amlogic/txlx_t962x_r311_1g.dts +++ b/arch/arm/boot/dts/amlogic/txlx_t962x_r311_1g.dts @@ -37,6 +37,8 @@ serial2 = &uart_B; serial3 = &uart_C; serial4 = &uart_AO_B; + spi0 = &spicc0; + spi1 = &spicc1; }; ion_dev { @@ -46,7 +48,7 @@ memory@00000000 { device_type = "memory"; - linux,usable-memory = <0x100000 0x3ff00000>; + linux,usable-memory = <0x000000 0x40000000>; }; reserved-memory { @@ -92,12 +94,22 @@ // size = <0x0 0x1000>; //}; + + codec_mm_cma:linux,codec_mm_cma { + compatible = "shared-dma-pool"; + reusable; + /* ion_codec_mm max can alloc size 80M*/ + size = <0xd000000>; + alignment = <0x400000>; + linux,contiguous-region; + alloc-ranges = <0x30000000 0x10000000>; + }; ion_reserved:linux,ion-dev { compatible = "shared-dma-pool"; reusable; size = <0x4C00000>; alignment = <0x400000>; - alloc-ranges = <0x0 0x2ee00000>; + alloc-ranges = <0x0 0x30000000>; }; /*di CMA pool */ @@ -113,6 +125,7 @@ */ size = <0x02800000>; alignment = <0x400000>; + alloc-ranges = <0x30000000 0x10000000>; }; /* POST PROCESS MANAGER */ @@ -121,16 +134,6 @@ size = <0x0>; }; - codec_mm_cma:linux,codec_mm_cma { - compatible = "shared-dma-pool"; - reusable; - /* ion_codec_mm max can alloc size 80M*/ - size = <0xd000000>; - alignment = <0x400000>; - linux,contiguous-region; - alloc-ranges = <0x12000000 0x13400000>; - }; - picdec_cma_reserved:linux,picdec { compatible = "shared-dma-pool"; reusable; @@ -153,6 +156,7 @@ /* 5M */ size = <0x0800000>; alignment = <0x400000>; + alloc-ranges = <0x0 0x30000000>; }; /* vdin1 CMA pool */ @@ -163,6 +167,7 @@ /* 1920x1080x2x4 =16+4 M */ size = <0x01400000>; alignment = <0x400000>; + alloc-ranges = <0x0 0x30000000>; }; /*vbi reserved mem*/ @@ -173,14 +178,14 @@ }; }; - dummy-battery { + amlogic_battery:dummy-battery { compatible = "amlogic, dummy-battery"; - status = "okay"; + status = "disabled"; }; - dummy-charger { + amlogic_charger:dummy-charger { compatible = "amlogic, dummy-charger"; - status = "okay"; + status = "disabled"; }; /* for external keypad */ @@ -1277,8 +1282,8 @@ Channel_Mask { /*i2s has 4 pins, 8channel, mux output*/ Speaker0_Channel_Mask = "i2s_2/3"; - DAC0_Channel_Mask = "i2s_2/3"; - DAC1_Channel_Mask = "i2s_2/3"; + DAC0_Channel_Mask = "i2s_4/5"; + DAC1_Channel_Mask = "i2s_4/5"; EQ_DRC_Channel_Mask = "i2s_2/3"; Spdif_samesource_Channel_Mask = "i2s_0/1"; }; diff --git a/arch/arm/boot/dts/amlogic/txlx_t962x_r311_2g.dts b/arch/arm/boot/dts/amlogic/txlx_t962x_r311_2g.dts index ea892b92fafe..e5f94bfd022c 100644 --- a/arch/arm/boot/dts/amlogic/txlx_t962x_r311_2g.dts +++ b/arch/arm/boot/dts/amlogic/txlx_t962x_r311_2g.dts @@ -37,6 +37,8 @@ serial2 = &uart_B; serial3 = &uart_C; serial4 = &uart_AO_B; + spi0 = &spicc0; + spi1 = &spicc1; }; ion_dev { @@ -46,7 +48,7 @@ memory@00000000 { device_type = "memory"; - linux,usable-memory = <0x100000 0x7ff00000>; + linux,usable-memory = <0x000000 0x80000000>; }; reserved-memory { @@ -97,7 +99,7 @@ reusable; size = <0x7C00000>; alignment = <0x400000>; - alloc-ranges = <0x0 0x2ee00000>; + alloc-ranges = <0x30000000 0x50000000>; }; /*di CMA pool */ @@ -128,7 +130,7 @@ size = <0x13400000>; alignment = <0x400000>; linux,contiguous-region; - alloc-ranges = <0x12000000 0x13400000>; + alloc-ranges = <0x30000000 0x50000000>; }; picdec_cma_reserved:linux,picdec { @@ -173,14 +175,14 @@ }; }; - dummy-battery { + amlogic_battery:dummy-battery { compatible = "amlogic, dummy-battery"; - status = "okay"; + status = "disabled"; }; - dummy-charger { + amlogic_charger:dummy-charger { compatible = "amlogic, dummy-charger"; - status = "okay"; + status = "disabled"; }; /* for external keypad */ @@ -1283,8 +1285,8 @@ Channel_Mask { /*i2s has 4 pins, 8channel, mux output*/ Speaker0_Channel_Mask = "i2s_2/3"; - DAC0_Channel_Mask = "i2s_2/3"; - DAC1_Channel_Mask = "i2s_2/3"; + DAC0_Channel_Mask = "i2s_4/5"; + DAC1_Channel_Mask = "i2s_4/5"; EQ_DRC_Channel_Mask = "i2s_2/3"; Spdif_samesource_Channel_Mask = "i2s_0/1"; }; diff --git a/arch/arm/boot/dts/amlogic/txlx_t962x_r311_720p.dts b/arch/arm/boot/dts/amlogic/txlx_t962x_r311_720p.dts new file mode 100644 index 000000000000..970ae170f83a --- /dev/null +++ b/arch/arm/boot/dts/amlogic/txlx_t962x_r311_720p.dts @@ -0,0 +1,1643 @@ +/* + * arch/arm/boot/dts/amlogic/txlx_t962x_r311_1g.dts + * + * Copyright (C) 2017 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +/dts-v1/; +#include +#include + +#include "mesontxlx.dtsi" +#include "partition_mbox_normal.dtsi" +#include "mesontxlx_r311-panel.dtsi" + +/ { + model = "Amlogic"; + amlogic-dt-id = "txlx_t962x_r311-720p"; + compatible = "amlogic, txlx"; + interrupt-parent = <&gic>; + #address-cells = <1>; + #size-cells = <1>; + + aliases { + serial0 = &uart_AO; + serial1 = &uart_A; + serial2 = &uart_B; + serial3 = &uart_C; + serial4 = &uart_AO_B; + }; + + ion_dev { + compatible = "amlogic, ion_dev"; + memory-region = <&ion_reserved>; + }; + + memory@00000000 { + device_type = "memory"; + linux,usable-memory = <0x100000 0x3ff00000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + /* global autoconfigured region for contiguous allocations */ + ramoops@0x07400000 { + compatible = "ramoops"; + reg = <0x07400000 0x00100000>; + record-size = <0x8000>; + console-size = <0x8000>; + ftrace-size = <0x0>; + pmsg-size = <0x8000>; + }; + secmon_reserved:linux,secmon { + compatible = "shared-dma-pool"; + reusable; + size = <0x400000>; + alignment = <0x400000>; + alloc-ranges = <0x05000000 0x400000>; + }; + + //secos_reserved:linux,secos { + // status = "disabled"; + // compatible = "amlogic, aml_secos_memory"; + // reg = <0x05300000 0x2000000>; + // no-map; + //}; + + + + logo_reserved:linux,meson-fb { + compatible = "shared-dma-pool"; + reusable; + size = <0x400000>; + alignment = <0x400000>; + alloc-ranges = <0x3fc00000 0x400000>; + }; + + //carveout_reserved:linux,carveout-reserve { + // compatible = "amlogic, idev-mem"; + // size = <0x1000>; + //}; + + ion_reserved:linux,ion-dev { + compatible = "shared-dma-pool"; + reusable; + size = <0x4C00000>; + alignment = <0x400000>; + alloc-ranges = <0x0 0x30000000>; + }; + + /*di CMA pool */ + di_cma_reserved:linux,di_cma { + compatible = "shared-dma-pool"; + reusable; + /* buffer_size = 3621952(yuv422 8bit) + * | 4736064(yuv422 10bit) + * | 4179008(yuv422 10bit full pack mode) + * 10x3621952=34.6M(0x23) support 8bit + * 10x4736064=45.2M(0x2e) support 12bit + * 10x4179008=40M(0x28) support 10bit + */ + size = <0x02800000>; + alignment = <0x400000>; + }; + + /* POST PROCESS MANAGER */ + ppmgr_reserved:linux,ppmgr { + compatible = "amlogic, ppmgr_memory"; + size = <0x0>; + }; + + codec_mm_cma:linux,codec_mm_cma { + compatible = "shared-dma-pool"; + reusable; + /* ion_codec_mm max can alloc size 80M*/ + size = <0xd000000>; + alignment = <0x400000>; + linux,contiguous-region; + }; + + picdec_cma_reserved:linux,picdec { + compatible = "shared-dma-pool"; + reusable; + size = <0x0>; + alignment = <0x0>; + linux,contiguous-region; + }; + + /* codec shared reserved */ + codec_mm_reserved:linux,codec_mm_reserved { + compatible = "amlogic, codec-mm-reserved"; + size = <0x0>; + alignment = <0x100000>; + //no-map; + }; + + demod_cma_reserved:linux,demod_cma { + compatible = "shared-dma-pool"; + reusable; + /* 5M */ + size = <0x0800000>; + alignment = <0x400000>; + }; + + /* vdin1 CMA pool */ + vdin1_cma_reserved:linux,vdin1_cma { + compatible = "shared-dma-pool"; + linux,phandle = <5>; + reusable; + /* 1920x1080x2x4 =16+4 M */ + size = <0x01400000>; + alignment = <0x400000>; + }; + + /*vbi reserved mem*/ + vbi_reserved:linux,vbi { + compatible = "amlogic, vbi-mem"; + size = <0x100000>; + alloc-ranges = <0x0 0x30000000>; + }; + }; + + amlogic_battery:dummy-battery { + compatible = "amlogic, dummy-battery"; + status = "disabled"; + }; + + amlogic_charger:dummy-charger { + compatible = "amlogic, dummy-charger"; + status = "disabled"; + }; + + /* for external keypad */ + adc_keypad { + compatible = "amlogic, adc_keypad"; + status = "okay"; + key_name = "power","up","down","enter","left","right","home"; + key_num = <7>; + io-channels = <&saradc SARADC_CH2>, + <&saradc SARADC_CH3>; + io-channel-names = "key-chan-2", "key-chan-3"; + key_chan = ; + key_code = <116 103 108 28 105 106 102>; + key_val = <0 143 266 389 512 143 266>; //val=voltage/1800mV*1023 + key_tolerance = <40 40 40 40 40 40 40>; + }; + + gpioleds { + compatible = "gpio-leds"; + status = "okay"; + + sys { + label = "sysled"; + gpios = <&gpio_ao GPIOAO_3 GPIO_ACTIVE_HIGH>; + default-state = "on"; /* keep/on/off */ + linux,default-trigger = "none"; + }; + + }; + + pwmleds { + compatible = "pwm-leds"; + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&pwmleds_pins>; + + sys { + active-low; + label = "sysled"; + max-brightness = <255>; + pwms = <&pwm_AO_ab 0 50000 0>; + }; + }; + + ethmac: ethernet@0xff3f0000 { + compatible = "amlogic, gxbb-eth-dwmac"; + status = "okay"; + reg = <0xff3f0000 0x10000 + 0xff634540 0x8 + 0xff634558 0xc + 0xffd01084 0x4>; + interrupts = <0 8 1 + 0 9 1>; + + phy-mode= "rmii"; + mc_val_internal_phy = <0x1804>; + mc_val_external_phy = <0x1621>; + interrupt-names = "macirq", + "phyirq"; + clocks = <&clkc CLKID_ETH_CORE>; + clock-names = "ethclk81"; + internal_phy = <1>; + }; + + vout { + compatible = "amlogic, vout"; + dev_name = "vout"; + status = "okay"; + fr_auto_policy = <0>; + }; + + meson-fb { + compatible = "amlogic, meson-txlx"; + memory-region = <&logo_reserved>; + dev_name = "meson-fb"; + status = "okay"; + interrupts = <0 3 1 + 0 89 1>; + interrupt-names = "viu-vsync", "rdma"; + mem_size = <0x00400000 0x00b00000 0x00100000>; + /* uboot logo,fb0/fb1 memory size,if afbcd fb0=0x0b51000*/ + display_mode_default = "720p60hz"; + scale_mode = <1>; + /*1280*720*4*3 = 0xA8C000*/ + display_size_default = <1280 720 1280 2160 32>; + pxp_mode = <0>; /** 0:normal mode 1:pxp mode */ + logo_addr = "0x3fc00000"; + }; + + ge2d { + compatible = "amlogic, ge2d-txlx"; + dev_name = "ge2d"; + status = "okay"; + interrupts = <0 150 1>; + interrupt-names = "ge2d"; + clocks = <&clkc CLKID_VAPB_MUX>, + <&clkc CLKID_G2D>, + <&clkc CLKID_GE2D_GATE>; + clock-names = "clk_vapb_0", + "clk_ge2d", + "clk_ge2d_gate"; + reg = <0xff940000 0x10000>; + }; + + codec_io { + compatible = "amlogic, codec_io"; + status = "okay"; + #address-cells=<1>; + #size-cells=<1>; + ranges; + io_cbus_base{ + reg = <0xffd00000 0x100000>; + }; + io_dos_base{ + reg = <0xff620000 0x10000>; + }; + io_hiubus_base{ + reg = <0xff63c000 0x2000>; + }; + io_aobus_base{ + reg = <0xff800000 0x10000>; + }; + io_vcbus_base{ + reg = <0xff900000 0x40000>; + }; + io_dmc_base{ + reg = <0xff638000 0x2000>; + }; + }; + + codec_mm { + compatible = "amlogic, codec, mm"; + memory-region = <&codec_mm_cma &codec_mm_reserved>; + dev_name = "codec_mm"; + status = "okay"; + }; + + mesonstream { + compatible = "amlogic, codec, streambuf"; + dev_name = "mesonstream"; + status = "okay"; + clocks = <&clkc CLKID_DOS_PARSER + &clkc CLKID_DEMUX + &clkc CLKID_DOS + &clkc CLKID_CLK81 + &clkc CLKID_VDEC_MUX + &clkc CLKID_HCODEC_MUX + &clkc CLKID_HEVC_MUX>; + clock-names = "parser_top", + "demux", + "vdec", + "clk_81", + "clk_vdec_mux", + "clk_hcodec_mux", + "clk_hevc_mux"; + }; + + vdec { + compatible = "amlogic, vdec"; + dev_name = "vdec.0"; + status = "okay"; + interrupts = <0 3 1 + 0 23 1 + 0 32 1 + 0 43 1 + 0 44 1 + 0 45 1>; + interrupt-names = "vsync", + "demux", + "parser", + "mailbox_0", + "mailbox_1", + "mailbox_2"; + }; + + meson-amvideom { + compatible = "amlogic, amvideom"; + dev_name = "amvideom"; + status = "okay"; + interrupts = <0 3 1>; + interrupt-names = "vsync"; + }; + + + + amvideocap { + compatible = "amlogic, amvideocap"; + dev_name = "amvideocap.0"; + status = "disabled"; + max_size = <8>;//8M + }; + + picdec { + compatible = "amlogic, picdec"; + memory-region = <&picdec_cma_reserved>; + dev_name = "picdec"; + status = "okay"; + }; + + ppmgr { + compatible = "amlogic, ppmgr"; + memory-region = <&ppmgr_reserved>; + dev_name = "ppmgr"; + status = "okay"; + }; + + deinterlace { + compatible = "amlogic, deinterlace"; + status = "okay"; + /* 0:use reserved; 1:use cma; 2:use cma as reserved */ + flag_cma = <1>; + //memory-region = <&di_reserved>; + memory-region = <&di_cma_reserved>; + interrupts = <0 46 1 + 0 6 1>; + interrupt-names = "de_irq"; + clocks = <&clkc CLKID_VPU_MUX>, + <&clkc CLKID_FCLK_DIV4>, + <&clkc CLKID_VPU_CLKB_TMP_COMP>, + <&clkc CLKID_VPU_CLKB_COMP>; + clock-names = "vpu_mux", + "fclk_div4", + "vpu_clkb_tmp_composite", + "vpu_clkb_composite"; + clock-range = <250 500>; + /* buffer-size = <3621952>;(yuv422 8bit) */ + buffer-size = <4179008>;/*yuv422 fullpack*/ + /* reserve-iomap = "true"; */ + /* if enable nr10bit, set nr10bit-support to 1 */ + nr10bit-support = <1>; + }; + ionvideo { + compatible = "amlogic, ionvideo"; + dev_name = "ionvideo"; + status = "okay"; + }; + + amlvideo { + compatible = "amlogic, amlvideo"; + dev_name = "amlvideo"; + status = "okay"; + }; + + amlvideo2_0 { + compatible = "amlogic, amlvideo2"; + dev_name = "amlvideo2"; + status = "okay"; + amlvideo2_id = <0>; + cma_mode = <1>; + }; + + amlvideo2_1 { + compatible = "amlogic, amlvideo2"; + dev_name = "amlvideo2"; + status = "okay"; + amlvideo2_id = <1>; + cma_mode = <1>; + }; + + hdmirx { + compatible = "amlogic, hdmirx_txlx"; + #address-cells=<1>; + #size-cells=<1>; + dev_name = "hdmirx"; + status = "okay"; + pinctrl-names = "hdmirx_pins"; + pinctrl-0 = <&hdmirx_a_mux &hdmirx_b_mux + &hdmirx_c_mux &hdmirx_d_mux>; + repeat = <0>; + interrupts = <0 56 1>; + clocks = <&clkc CLKID_HDMIRX_MODET_COMP>, + <&clkc CLKID_HDMIRX_CFG_COMP>, + <&clkc CLKID_HDMIRX_ACR_COMP>, + <&clkc CLKID_HDMIRX_AUDMEAS_COMP>, + <&xtal>, + <&clkc CLKID_FCLK_DIV5>, + <&clkc CLKID_FCLK_DIV7>, + <&clkc CLKID_HDCP22_SKP_COMP>, + <&clkc CLKID_HDCP22_ESM_COMP>; + // <&clkc CLK_AUD_PLL2FS>, + // <&clkc CLK_AUD_PLL4FS>, + // <&clkc CLK_AUD_OUT>; + clock-names = "hdmirx_modet_clk", + "hdmirx_cfg_clk", + "hdmirx_acr_ref_clk", + "hdmirx_audmeas_clk", + "xtal", + "fclk_div5", + "fclk_div7", + "hdcp_rx22_skp", + "hdcp_rx22_esm"; + // "hdmirx_aud_pll2fs", + // "hdmirx_aud_pll4f", + // "clk_aud_out"; + hdmirx_id = <0>; + en_4k_2_2k = <0>; + hpd_low_cec_off = <1>; + /* bit4: enable feature, bit3~0: port number */ + disable_port = <0x0>; + reg = <0xffd26000 0xa00000 + 0xff63C000 0x2000 + 0xffe0d000 0x2000 + 0xff63e000 0x2000 + 0x0 0x0 + 0xff634400 0x2000 + 0xff646000 0x2000>; + }; + + vdin0 { + compatible = "amlogic, vdin"; + /*memory-region = <&vdin0_cma_reserved>;*/ + dev_name = "vdin0"; + status = "okay"; + reserve-iomap = "true"; + /*bit0:(1:share with codec_mm;0:cma alone)*/ + /*bit8:(1:alloc in discontinus way;0:alone in continuous way)*/ + flag_cma = <0x101>; + /* MByte, if 10bit disable: 64M(YUV422), + * if 10bit enable: 64*1.5 = 96M(YUV422) + * if support 4K2K-YUV444-10bit-WR:3840*2160*4*4 ~= 128M + * if support 4K2K-YUV444-10bit-WR:3840*2160*4*6 ~= 190M + * if support 4K2K-YUV422-10bit-wr:3840*2160*3*4 ~= 96M + * if support 4K2K-YUV422-8BIT-WR:3840*2160*2*4 ~= 64M + * if support 1080p-YUV422-8BIT-WR:1920*1080*2*4 ~= 16M + */ + cma_size = <190>; + interrupts = <0 83 1>; + rdma-irq = <2>; + clocks = <&clkc CLKID_FCLK_DIV5>, + <&clkc CLKID_VDIN_MEAS_COMP>; + clock-names = "fclk_div5", "cts_vdin_meas_clk"; + vdin_id = <0>; + /* vdin write mem color depth support: + * bit0:support 8bit + * bit1:support 9bit + * bit2:support 10bit + * bit3:support 12bit + * bit4:support yuv422 10bit full pack mode (from txl new add) + * bit8:use 8bit at 4k_50/60hz_10bit + * bit9:use 10bit at 4k_50/60hz_10bit + */ + tv_bit_mode = <0x215>; + }; + + vdin1 { + compatible = "amlogic, vdin"; + memory-region = <&vdin1_cma_reserved>; + dev_name = "vdin1"; + status = "okay"; + reserve-iomap = "true"; + flag_cma = <0>;/*1:share with codec_mm;0:cma alone*/ + interrupts = <0 85 1>; + rdma-irq = <4>; + clocks = <&clkc CLKID_FCLK_DIV5>, + <&clkc CLKID_VDIN_MEAS_COMP>; + clock-names = "fclk_div5", "cts_vdin_meas_clk"; + vdin_id = <1>; + /* vdin write mem color depth support: + * bit0:support 8bit + * bit1:support 9bit + * bit2:support 10bit + * bit3:support 12bit + */ + tv_bit_mode = <1>; + }; + + tvafe { + compatible = "amlogic, tvafe-txlx"; + /*memory-region = <&tvafe_cma_reserved>;*/ + dev_name = "tvafe"; + status = "okay"; + flag_cma = <1>;/*1:share with codec_mm;0:cma alone*/ + cma_size = <5>;/*MByte*/ + reg = <0xff642000 0x2000>;/*tvafe reg base*/ + reserve-iomap = "true"; + tvafe_id = <0>; + //pinctrl-names = "default"; + /*!!particular sequence, no more and no less!!!*/ + tvafe_pin_mux = < + 3 /* TVAFE_CVBS_IN2, CVBS_IN0 = 0 */ + 1 /* TVAFE_CVBS_IN0, CVBS_IN1 */ + 2 /* TVAFE_CVBS_IN1, CVBS_IN2 */ + 4 /* TVAFE_CVBS_IN3, CVBS_IN3 */ + >; + clocks = <&clkc CLKID_DAC_CLK>; + clock-names = "vdac_clk_gate"; + }; + + vbi { + compatible = "amlogic, vbi"; + memory-region = <&vbi_reserved>; + dev_name = "vbi"; + status = "okay"; + interrupts = <0 83 1>; + reserve-iomap = "true"; + }; + + tvafe_avin_detect { + compatible = "amlogic, tvafe_avin_detect"; + dev_name = "tvafe_avin_detect"; + status = "okay"; + device_mask = <1>;/*bit0:ch1;bit1:ch2*/ + interrupts = <0 12 1>, + <0 13 1>; + }; + + amlvecm { + compatible = "amlogic, vecm"; + dev_name = "aml_vecm"; + status = "okay"; + gamma_en = <1>;/*1:enabel ;0:disable*/ + wb_en = <1>;/*1:enabel ;0:disable*/ + cm_en = <1>;/*1:enabel ;0:disable*/ + wb_sel = <1>;/*1:mtx ;0:gainoff*/ + vlock_en = <1>;/*1:enable;0:disable*/ + vlock_mode = <0x4>; + /* vlock work mode: + *bit0:auto ENC + *bit1:auto PLL + *bit2:manual PLL + *bit3:manual ENC + *bit4:manual soft ENC + *bit5:manual MIX PLL ENC + */ + vlock_pll_m_limit = <1>; + vlock_line_limit = <3>; + }; + amdolby_vision { + compatible = "amlogic, dolby_vision_txlx"; + dev_name = "aml_amdolby_vision_driver"; + status = "okay"; + tv_mode = <1>;/*1:enabel ;0:disable*/ + }; + amvenc_avc { + compatible = "amlogic, amvenc_avc"; + //memory-region = <&amvenc_avc_reserved>; + //memory-region = <&avc_cma_reserved>; + dev_name = "amvenc_avc"; + status = "okay"; + interrupts = <0 45 1>; + interrupt-names = "mailbox_2"; + }; + + tuner: tuner { + status = "okay"; + tuner_name = "mxl661_tuner"; + tuner_i2c_adap = <&i2c1>; + tuner_i2c_addr = <0x60>; + tuner_xtal = <0>; /* 0: 16MHz, 1: 24MHz */ + tuner_xtal_mode = <0>; + /* NO_SHARE_XTAL(0) + * SLAVE_XTAL_SHARE(1) + */ + tuner_xtal_cap = <30>; /* when tuner_xtal_mode = 1, set 25 */ + }; + + atv-demod { + compatible = "amlogic, atv-demod"; + status = "okay"; + tuner = <&tuner>; + btsc_sap_mode = <1>; + /* pinctrl-names="atvdemod_agc_pins"; */ + /* pinctrl-0=<&atvdemod_agc_pins>; */ + reg = <0xff640000 0x2000 /* demod reg */ + 0xff63c000 0x2000 /* hiu reg */ + 0xff634000 0x2000 /* periphs reg */ + 0xff648000 0x2000>; /* audio reg */ + reg_23cf = <0x88188832>; + /*default:0x88188832;r840 on haier:0x48188832*/ + }; + + bt-dev { + compatible = "amlogic, bt-dev"; + dev_name = "bt-dev"; + status = "okay"; + power_down_disable = <1>; + gpio_reset = <&gpio_ao GPIOAO_8 GPIO_ACTIVE_HIGH>; + //gpio_en = <&gpio_ao GPIOAO_5 GPIO_ACTIVE_HIGH>; + }; + + rtc { + compatible = "amlogic, aml_vrtc"; + alarm_reg_addr = <0xff8000a8>; + timer_e_addr = <0xffd0f188>; + init_date = "2015/01/01"; + status = "okay"; + }; + + wifi { + compatible = "amlogic, aml_wifi"; + dev_name = "aml_wifi"; + status = "okay"; + interrupt_pin = <&gpio_ao GPIOAO_4 GPIO_ACTIVE_HIGH>; + interrupts = <0 68 4>; + irq_trigger_type = "GPIO_IRQ_HIGH"; + dhd_static_buf; + power_on_pin = <&gpio_ao GPIOAO_5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_32k_pins>; + pwm_config = <&wifi_pwm_conf>; + }; + + wifi_pwm_conf: wifi_pwm_conf { + pwm_channel1_conf { + pwms = <&pwm_cd MESON_PWM_1 30040 0>; + duty-cycle = <15020>; + times = <10>; + }; + pwm_channel2_conf { + pwms = <&pwm_cd MESON_PWM_3 30030 0>; + duty-cycle = <15015>; + times = <12>; + }; + }; + + sd_emmc_c: emmc@ffe07000 { + status = "okay"; + compatible = "amlogic, meson-mmc-txlx"; + reg = <0xffe07000 0x2000>; + interrupts = <0 218 1>; + pinctrl-names = "emmc_clk_cmd_pins", "emmc_all_pins"; + pinctrl-0 = <&emmc_clk_cmd_pins>; + pinctrl-1 = <&emmc_conf_pull_up &emmc_conf_pull_done>; + clocks = <&clkc CLKID_SD_EMMC_C>, + <&clkc CLKID_SD_EMMC_C_P0_COMP>, + <&clkc CLKID_FCLK_DIV2>, + <&clkc CLKID_FCLK_DIV5>, + <&xtal>; + clock-names = "core", "clkin0", "clkin1", "clkin2", "xtal"; + + bus-width = <8>; + cap-sd-highspeed; + cap-mmc-highspeed; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + + max-frequency = <200000000>; + non-removable; + disable-wp; + emmc { + status = "disabled"; + pinname = "emmc"; + ocr_avail = <0x200080>; /**VDD voltage 3.3 ~ 3.4 */ + caps = "MMC_CAP_8_BIT_DATA", + "MMC_CAP_MMC_HIGHSPEED", + "MMC_CAP_SD_HIGHSPEED", + "MMC_CAP_NONREMOVABLE", + "MMC_CAP_1_8V_DDR", + "MMC_CAP_HW_RESET", + "MMC_CAP_ERASE", + "MMC_CAP_CMD23"; + caps2 = "MMC_CAP2_HS200", "MMC_CAP2_HS400"; + f_min = <400000>; + f_max = <200000000>; + max_req_size = <0x20000>; /**128KB*/ + gpio_dat3 = <&gpio BOOT_3 GPIO_ACTIVE_HIGH>; + hw_reset = <&gpio BOOT_9 GPIO_ACTIVE_HIGH>; + card_type = <1>; + /* 1:mmc card(include eMMC), + * 2:sd card(include tSD) + */ + }; + }; + + sd_emmc_b: sd@ffe05000 { + status = "okay"; + compatible = "amlogic, meson-mmc-txlx"; + reg = <0xffe05000 0x2000>; + interrupts = <0 217 1>; + pinctrl-names = "sd_all_pins", + "sd_clk_cmd_pins", + "sd_1bit_pins", + "sd_clk_cmd_uart_pins", + "sd_1bit_uart_pins", + "sd_to_ao_uart_pins", + "ao_to_sd_uart_pins", + "ao_to_sd_jtag_pins", + "sd_to_ao_jtag_pins"; + pinctrl-0 = <&sd_all_pins>; + pinctrl-1 = <&sd_clk_cmd_pins>; + pinctrl-2 = <&sd_1bit_pins>; + pinctrl-3 = <&sd_to_ao_uart_clr_pins + &sd_clk_cmd_pins &ao_to_sd_uart_pins>; + pinctrl-4 = <&sd_to_ao_uart_clr_pins + &sd_1bit_pins &ao_to_sd_uart_pins>; + pinctrl-5 = <&sd_all_pins &sd_to_ao_uart_pins>; + pinctrl-6 = <&sd_to_ao_uart_clr_pins &ao_to_sd_uart_pins>; + pinctrl-7 = <&sd_to_ao_uart_clr_pins &ao_to_sd_uart_pins>; + pinctrl-8 = <&sd_all_pins &sd_to_ao_uart_pins>; + clocks = <&clkc CLKID_SD_EMMC_B>, + <&clkc CLKID_SD_EMMC_B_P0_COMP>, + <&clkc CLKID_FCLK_DIV2>, + <&clkc CLKID_FCLK_DIV5>, + <&xtal>; + clock-names = "core", "clkin0", "clkin1", "clkin2", "xtal"; + + bus-width = <4>; + cap-sd-highspeed; + max-frequency = <100000000>; + disable-wp; + sd { + status = "disabled"; + pinname = "sd"; + ocr_avail = <0x200080>; /**VDD voltage 3.3 ~ 3.4 */ + caps = "MMC_CAP_4_BIT_DATA", + "MMC_CAP_MMC_HIGHSPEED", + "MMC_CAP_SD_HIGHSPEED"; + /* "MMC_CAP_UHS_SDR12", + * "MMC_CAP_UHS_SDR25", + * "MMC_CAP_UHS_SDR50", + * "MMC_CAP_UHS_SDR104"; + */ + f_min = <400000>; + f_max = <200000000>; + max_req_size = <0x20000>; /**128KB*/ + gpio_dat3 = <&gpio GPIOC_4 GPIO_ACTIVE_HIGH>; + jtag_pin = <&gpio GPIOC_0 GPIO_ACTIVE_HIGH>; + gpio_cd = <&gpio GPIOH_10 GPIO_ACTIVE_HIGH>; + card_type = <5>; + /* 3:sdio device(ie:sdio-wifi), + * 4:SD combo (IO+mem) card + * 5:NON sdio device(means sd/mmc card) + */ + }; + }; + + unifykey { + compatible = "amlogic, unifykey"; + status = "okay"; + + unifykey-num = <20>; + unifykey-index-0 = <&keysn_0>; + unifykey-index-1 = <&keysn_1>; + unifykey-index-2 = <&keysn_2>; + unifykey-index-3 = <&keysn_3>; + unifykey-index-4 = <&keysn_4>; + unifykey-index-5 = <&keysn_5>; + unifykey-index-6 = <&keysn_6>; + unifykey-index-7 = <&keysn_7>; + unifykey-index-8 = <&keysn_8>; + unifykey-index-9 = <&keysn_9>; + unifykey-index-10= <&keysn_10>; + unifykey-index-11 = <&keysn_11>; + unifykey-index-12 = <&keysn_12>; + unifykey-index-13 = <&keysn_13>; + unifykey-index-14 = <&keysn_14>; + unifykey-index-15 = <&keysn_15>; + unifykey-index-16 = <&keysn_16>; + unifykey-index-17 = <&keysn_17>; + unifykey-index-18 = <&keysn_18>; + unifykey-index-19 = <&keysn_19>; + + keysn_0: key_0{ + key-name = "usid"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_1:key_1{ + key-name = "mac"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_2:key_2{ + key-name = "hdcp"; + key-device = "secure"; + key-type = "sha1"; + key-permit = "read","write","del"; + }; + keysn_3:key_3{ + key-name = "secure_boot_set"; + key-device = "efuse"; + key-permit = "write"; + }; + keysn_4:key_4{ + key-name = "mac_bt"; + key-device = "normal"; + key-permit = "read","write","del"; + key-type = "mac"; + }; + keysn_5:key_5{ + key-name = "mac_wifi"; + key-device = "normal"; + key-permit = "read","write","del"; + key-type = "mac"; + }; + keysn_6:key_6{ + key-name = "hdcp2_tx"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_7:key_7{ + key-name = "hdcp2_rx"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_8:key_8{ + key-name = "widevinekeybox"; + key-device = "secure"; + key-type = "sha1"; + key-permit = "read","write","del"; + }; + keysn_9:key_9{ + key-name = "deviceid"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_10:key_10{ + key-name = "hdcp22_fw_private"; + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_11:key_11{ + key-name = "hdcp22_rx_private"; + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_12:key_12{ + key-name = "hdcp22_rx_fw"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_13:key_13{ + key-name = "hdcp14_rx"; + key-device = "normal"; + key-type = "sha1"; + key-permit = "read","write","del"; + }; + keysn_14:key_14{ + key-name = "prpubkeybox";// PlayReady + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_15:key_15{ + key-name = "prprivkeybox";// PlayReady + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_16:key_16{ + key-name = "lcd"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_17:key_17{ + key-name = "lcd_extern"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_18:key_18{ + key-name = "backlight"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_19:key_19{ + key-name = "attestationkeybox";// attestation key + key-device = "secure"; + key-permit = "read","write","del"; + }; + }; /* End unifykey */ + + cvbsout { + compatible = "amlogic, cvbsout-txlx"; + dev_name = "cvbsout"; + status = "disabled"; + clocks = <&clkc CLKID_VCLK2_ENCI + &clkc CLKID_VCLK2_VENCI0 + &clkc CLKID_VCLK2_VENCI1 + &clkc CLKID_DAC_CLK>; + clock-names = "venci_top_gate", + "venci_0_gate", + "venci_1_gate", + "vdac_clk_gate"; + + /* performance: reg_address, reg_value */ + performance = <0x1b56 0x343 + 0x1b05 0xf4 + 0x1c59 0xfc48 + 0x1b12 0x8c00 + 0xffff 0x0>; /* ending flag */ + }; + + amhdmitx: amhdmitx { + compatible = "amlogic, amhdmitx"; + dev_name = "amhdmitx"; + status = "disabled"; + pinctrl-names="default", "hdmitx_i2c"; + pinctrl-0=<&hdmitx_hpd &hdmitx_ddc>; + pinctrl-1=<&hdmitx_hpd_gpio &i2c2_h_pins>; + /* HPD, 57 + 32 = 89; CEC, 151 + 32 = 183*/ + interrupts = <0 57 1>; + interrupt-names = "hdmitx_hpd"; + /* 0:M8B 1:GXBB 2:GXTVBB 3:GXL 4:GXM + * 5:TXL 6:TXLX 7:AXG 8:GXLX 9:TXHD + */ + ic_type = <6>; + //gpio_i2c_en = <0>; + //repeater_tx = <0x1>; + //#address-cells = <2>; + //#size-cells = <2>; + //ranges; + }; + + i2c_gpio: i2c_gpio { + compatible = "i2c-gpio"; + dev_name = "i2c-gpio"; + status = "disabled"; + i2c-gpio,delay-us = <10>; /* 50 kHz */ + gpios = <&gpio GPIOH_2 0 + &gpio GPIOH_3 0>; + #address-cells = <2>; + #size-cells = <2>; + i2c-gpio,timeout-ms = <10>; + i2c_gpio_edid: i2c_gpio_edid { + compatible = "i2c-gpio"; + reg = <0x50 0x0 0x0 0x0>; + }; + }; + + aocec: aocec { + compatible = "amlogic, aocec-txlx"; + device_name = "aocec"; + status = "okay"; + vendor_name = "Amlogic"; /* Max Chars: 8 */ + /* Refer to the following URL at: + * http://standards.ieee.org/develop/regauth/oui/oui.txt + */ + vendor_id = <0x000000>; + product_desc = "TXLX"; /* Max Chars: 16 */ + cec_osd_string = "AML_TV"; /* Max Chars: 14 */ + port_num = <4>; + /*ee_cec;*/ + arc_port_mask = <0x2>; + interrupts = <0 205 1 + 0 199 1>; + interrupt-names = "hdmi_aocecb","hdmi_aocec"; + pinctrl-names = "default","hdmitx_aocecb","cec_pin_sleep"; + pinctrl-0=<&hdmitx_aocec>; + pinctrl-1=<&hdmitx_aocecb>; + pinctrl-2=<&hdmitx_aocecb>; + reg = <0xFF80023c 0x4 + 0xFF800000 0x400>; + reg-names = "ao_exit","ao"; + }; + + + canvas { + compatible = "amlogic, meson, canvas"; + dev_name = "amlogic-canvas"; + status = "okay"; + reg = <0xff638000 0x2000>; + }; + + rdma { + compatible = "amlogic, meson, rdma"; + dev_name = "amlogic-rdma"; + status = "okay"; + interrupts = <0 89 1>; + interrupt-names = "rdma"; + }; + + dwc3: dwc3@ff500000 { + compatible = "synopsys, dwc3"; + status = "okay"; + reg = <0xff500000 0x100000>; + interrupts = <0 30 4>; + usb-phy = <&usb2_phy>, <&usb3_phy>; + cpu-type = "gxl"; + clock-src = "usb3.0"; + }; + + usb2_phy: usb2phy@ffe09000 { + compatible = "amlogic, amlogic-new-usb2"; + status = "okay"; + portnum = <4>; + reg = <0xffe09000 0x80 + 0xffd01008 0x4>; + }; + + usb3_phy: usb3phy@ffe09080 { + compatible = "amlogic, amlogic-new-usb3"; + status = "okay"; + portnum = <0>; + reg = <0xffe09080 0x20>; + }; + + dwc2_a { + compatible = "amlogic, dwc2"; + device_name = "dwc2_a"; + reg = <0xff400000 0x40000>; + status = "okay"; + interrupts = <0 31 4>; + pl-periph-id = <0>; /** lm name */ + clock-src = "usb0"; /** clock src */ + port-id = <0>; /** ref to mach/usb.h */ + port-type = <2>; /** 0: otg, 1: host, 2: slave */ + port-speed = <0>; /** 0: default, high, 1: full */ + port-config = <0>; /** 0: default */ + /*0:default,1:single,2:incr,3:incr4,4:incr8,5:incr16,6:disable*/ + port-dma = <0>; + port-id-mode = <0>; /** 0: hardware, 1: sw_host, 2: sw_slave*/ + usb-fifo = <728>; + cpu-type = "gxl"; + /** 0: normal, 1: otg+dwc3 host only, 2: otg+dwc3 device only*/ + controller-type = <1>; + phy-reg = <0xffe09000>; + phy-reg-size = <0xa0>; + clocks = <&clkc CLKID_USB_GENERAL + &clkc CLKID_USB1_TO_DDR>; + clock-names = "usb_general", + "usb1"; + }; + + /* Sound iomap */ + aml_snd_iomap { + compatible = "amlogic, meson-snd-iomap"; + status = "okay"; + #address-cells=<1>; + #size-cells=<1>; + ranges; + io_audin_base { + reg = <0xffd03000 0x100000>; + }; + io_aiu_base { + reg = <0xFFCFFC00 0x100000>; + }; + io_eqdrc_base { + reg = <0xFFCFF000 0x100000>; + }; + io_hiu_reset_base { + reg = <0xFFCFCC00 0x100000>; + }; + io_isa_base { + reg = <0xFFD05800 0x100000>; + }; + }; + + /* AUDIO DEVICES */ + i2s_dai: I2S { + #sound-dai-cells = <0>; + /* config mpll whether same with audin */ + clocks = <&clkc CLKID_MPLL3>, + <&clkc CLKID_AMCLK_COMP>, + <&clkc CLKID_AIU_GLUE>, + <&clkc CLKID_I2S_OUT>, + <&clkc CLKID_AMCLK_MEASURE>, + <&clkc CLKID_AIFIFO2>, + <&clkc CLKID_MIXER>, + <&clkc CLKID_MIXER_IFACE>, + <&clkc CLKID_ADC>, + <&clkc CLKID_AIU_TOP>, + <&clkc CLKID_AOCLK_GATE>, + <&clkc CLKID_I2S_SPDIF>, + <&clkc CLKID_DAC_CLK>; + clock-names = "mpll", + "mclk", + "top_glue", + "i2s_out", + "amclk_measure", + "aififo2", + "aud_mixer", + "mixer_reg", + "adc", + "top_level", + "aoclk", + "aud_in", + "vdac_clk"; + compatible = "amlogic, aml-i2s-dai"; + }; + + i2s2_dai: I2S2 { + #sound-dai-cells = <0>; + /* config mpll whether same with aiu */ + clocks = <&clkc CLKID_MPLL2>, + <&clkc CLKID_AUDIN_MCLK_COMP>, + <&clkc CLKID_AUDIN_SCLK_COMP>, + <&clkc CLKID_AUDIN_LRCLK_COMP>; + clock-names = "audin_mpll", + "audin_mclk", + "audin_sclk", + "audin_lrclk"; + compatible = "amlogic, aml-i2s2-dai"; + }; + + spdif_dai: SPDIF { + #sound-dai-cells = <0>; + compatible = "amlogic, aml-spdif-dai"; + clocks = <&clkc CLKID_MPLL1>, + <&clkc CLKID_IEC958_INT_COMP>, + <&clkc CLKID_AMCLK_COMP>, + <&clkc CLKID_IEC958_MUX>, + <&clkc CLKID_CLK81>, + <&clkc CLKID_IEC958>, + <&clkc CLKID_IEC958_GATE>; + clock-names = + "mpll1", + "i958", + "mclk", + "spdif", + "clk_81", + "iec958", + "iec958_amclk"; + }; + + pcm_dai: PCM { + #sound-dai-cells = <0>; + compatible = "amlogic, aml-pcm-dai"; + pinctrl-names = "audio_pcm"; + /* disable pcm pin mux temporary, enable it if necessary */ + /*pinctrl-0 = <&aml_audio_pcm>;*/ + clocks = <&clkc CLKID_MPLL0>, + <&clkc CLKID_PCM_MCLK_COMP>, + <&clkc CLKID_PCM_SCLK_COMP>; + clock-names = "mpll0", "pcm_mclk", "pcm_sclk"; + pcm_mode = <1>; /* 0=slave mode, 1=master mode */ + }; + + i2s_plat: i2s_platform { + compatible = "amlogic, aml-i2s"; + interrupts = <0 29 1>; + }; + + pcm_plat: pcm_platform { + compatible = "amlogic, aml-pcm"; + }; + + spdif_codec: spdif_codec{ + #sound-dai-cells = <0>; + compatible = "amlogic, aml-spdif-codec"; + pinctrl-names = "audio_spdif_out", "audio_spdif_out_mute"; + pinctrl-0 = <&audio_spdif_out_pins>; + pinctrl-1 = <&audio_spdif_out_mute_pins>; + }; + + pcm_codec: pcm_codec{ + #sound-dai-cells = <0>; + compatible = "amlogic, pcm2BT-codec"; + }; + /* end of AUDIO DEVICES */ + + /* AUDIO board specific */ + dummy_codec:dummy{ + #sound-dai-cells = <0>; + compatible = "amlogic, aml_dummy_codec"; + status = "okay"; + }; + + amlogic_codec:txlx_acodec{ + #sound-dai-cells = <0>; + compatible = "amlogic, txlx_acodec"; + reg = <0xFF632000 0x1c>; + status = "okay"; + }; + + aml_snd_tv { + compatible = "amlogic, txlx-snd-tv"; + status = "okay"; + aml-sound-card,format = "i2s"; + aml_sound_card,name = "AML-TVAUDIO"; + pinctrl-names = "audio_i2s"; + pinctrl-0 = <&aml_audio_i2s>; + /*avout mute gpio*/ + mute_gpio-gpios = <&gpio GPIODV_5 GPIO_ACTIVE_HIGH>; + /*analog amp mute*/ + /*amp_mute_gpio-gpios = <&gpio GPIOZ_18 GPIO_ACTIVE_LOW>;*/ + aux_dev = <&tas5707>; + cpu_list = <&cpudai0 &cpudai1 &cpudai2 &cpudai3>; + codec_list = <&codec0 &codec1 &codec2 &codec3>; + plat_list = <&i2s_plat &i2s_plat &pcm_plat &i2s_plat>; + cpudai0: cpudai0 { + sound-dai = <&i2s_dai>; + }; + cpudai1: cpudai1 { + sound-dai = <&spdif_dai>; + }; + cpudai2: cpudai2 { + sound-dai = <&pcm_dai>; + }; + cpudai3: cpudai3 { + sound-dai = <&i2s2_dai>; + }; + codec0: codec0 { + sound-dai = <&amlogic_codec>; + }; + codec1: codec1 { + sound-dai = <&spdif_codec>; + }; + codec2: codec2 { + sound-dai = <&pcm_codec>; + }; + codec3: codec3 { + sound-dai = <&dummy_codec>; + }; + Channel_Mask { + /*i2s has 4 pins, 8channel, mux output*/ + Speaker0_Channel_Mask = "i2s_2/3"; + DAC0_Channel_Mask = "i2s_4/5"; + DAC1_Channel_Mask = "i2s_4/5"; + EQ_DRC_Channel_Mask = "i2s_2/3"; + Spdif_samesource_Channel_Mask = "i2s_0/1"; + }; + }; + + amaudio2 { + compatible = "amlogic, aml_amaudio2"; + status = "okay"; + interrupts = <0 48 1>; + }; + /* end of AUDIO board specific */ + + aml_sensor0: aml-sensor@0 { + compatible = "amlogic, aml-thermal"; + device_name = "thermal"; + status = "okay"; + #thermal-sensor-cells = <1>; + cooling_devices { + cpufreq_cool_cluster0 { + min_state = <1000000>; + dyn_coeff = <140>; + cluster_id = <0>; + node_name = "cpus"; + device_type = "cpufreq"; + }; + cpucore_cool_cluster0 { + min_state = <1>; + dyn_coeff = <0>; + cluster_id = <0>; + node_name = "cpu_core_cluster0"; + device_type = "cpucore"; + }; + gpufreq_cool { + min_state = <400>; + dyn_coeff = <437>; + cluster_id = <0>; + node_name = "mali"; + device_type = "gpufreq"; + }; + gpucore_cool { + min_state = <1>; + dyn_coeff = <0>; + cluster_id = <0>; + node_name = "thermal_gpu_cores"; + device_type = "gpucore"; + }; + }; + cpu_cluster0:cpu_core_cluster0 { + #cooling-cells = <2>; /* min followed by max */ + }; + gpucore:thermal_gpu_cores { + #cooling-cells = <2>; /* min followed by max */ + }; + }; + + dvb { + compatible = "amlogic, dvb"; + dev_name = "dvb"; + status = "okay"; + fe0_mode = "internal"; + fe0_tuner = <&tuner>; + /*"parallel","serial","disable"*/ + ts2 = "parallel"; + ts2_control = <0>; + ts2_invert = <0>; + interrupts = <0 23 1 + 0 5 1 + 0 53 1 + 0 19 1 + 0 25 1 + 0 18 1 + 0 24 1>; + interrupt-names = "demux0_irq", + "demux1_irq", + "demux2_irq", + "dvr0_irq", + "dvr1_irq", + "dvrfill0_fill", + "dvrfill1_flush"; + clocks = <&clkc CLKID_DEMUX + &clkc CLKID_ASYNC_FIFO + &clkc CLKID_AHB_ARB0 + &clkc CLKID_DOS_PARSER>; + clock-names = "demux", "asyncfifo", "ahbarb0", "uparsertop"; + }; + aml_dtv_demod { + compatible = "amlogic, ddemod-txlx"; + dev_name = "aml_dtv_demod"; + status = "okay"; + + //pinctrl-names="dtvdemod_agc"; + //pinctrl-0=<&dtvdemod_agc>; + + + clocks = <&clkc CLKID_DAC_CLK>; + clock-names = "vdac_clk_gate"; + + + reg = <0xff644000 0x2000 /*dtv demod base*/ + 0xff63c000 0x2000 /*hiu reg base*/ + 0xff800000 0x1000 /*io_aobus_base*/ + 0xffd01000 0x1000 /*reset*/ + >; + /*move from dvbfe*/ + dtv_demod0_mem = <0>; // need move to aml_dtv_demod ? + spectrum = <1>; + cma_flag = <1>; + cma_mem_size = <8>; + memory-region = <&demod_cma_reserved>;//<&demod_reserved>; + }; + dvbfe { + compatible = "amlogic, dvbfe"; + dev_name = "dvbfe"; + status = "disabled"; + dtv_demod0 = "AMLDEMOD"; + fe0_dtv_demod = <0>; + fe0_ts = <2>; + fe0_dev = <0>; + dtv_demod0_mem = <0>; + dtv_demod0_spectrum = <1>; + dtv_demod0_cma_flag = <1>; + dtv_demod0_cma_mem_size = <8>; + memory-region = <&demod_cma_reserved>;//<&demod_reserved>; + tuner0 = "si2151_tuner"; + tuner0_i2c_adap_id = <2>; + tuner0_i2c_addr = <0x60>; + //tuner0_reset_value = <0>; + //tuner0_reset_gpio = "GPIOY_10" ; /*GPIOX_8 76*/ + fe0_tuner = <0>; + atv_demod0 = "aml_atv_demod"; + fe0_atv_demod = <0>; + }; + + thermal-zones { + soc_thermal { + polling-delay = <1000>; + polling-delay-passive = <100>; + sustainable-power = <2150>; + + thermal-sensors = <&aml_sensor0 3>; + + trips { + switch_on: trip-point@0 { + temperature = <70000>; + hysteresis = <1000>; + type = "passive"; + }; + control: trip-point@1 { + temperature = <80000>; + hysteresis = <1000>; + type = "passive"; + }; + hot: trip-point@2 { + temperature = <85000>; + hysteresis = <5000>; + type = "hot"; + }; + critical: trip-point@3 { + temperature = <260000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + + cooling-maps { + cpufreq_cooling_map { + trip = <&control>; + cooling-device = <&cpus 0 4>; + contribution = <1024>; + }; + cpucore_cooling_map { + trip = <&control>; + cooling-device = <&cpu_cluster0 0 3>; + contribution = <1024>; + }; + gpufreq_cooling_map { + trip = <&control>; + cooling-device = <&gpu 0 4>; + contribution = <1024>; + }; + gpucore_cooling_map { + trip = <&control>; + cooling-device = <&gpucore 0 2>; + contribution = <1024>; + }; + }; + }; + }; + +}; /* end of / */ + +&i2c2 { + status = "okay"; + pinctrl-names="default"; + pinctrl-0=<&i2c2_h_pins>; + + tas5707: tas5707@36 { + compatible = "ti,tas5707"; + #sound-dai-cells = <0>; + codec_name = "tas5707"; + reg = <0x1B>; + reset_pin = <&gpio GPIODV_4 GPIO_ACTIVE_LOW>; + eq_enable = <0>; + drc_enable = <0>; + status = "okay"; + }; + + lcd_extern_i2c0: lcd_extern_i2c@0 { + compatible = "lcd_ext, i2c"; + dev_name = "i2c_T5800Q"; + reg = <0x1c>; + status = "okay"; + }; + + lcd_extern_i2c1: lcd_extern_i2c@1 { + compatible = "lcd_ext, i2c"; + dev_name = "i2c_ANX6862"; + reg = <0x20>; + status = "okay"; + }; + + lcd_extern_i2c2: lcd_extern_i2c@2 { + compatible = "lcd_ext, i2c"; + dev_name = "i2c_ANX7911"; + reg = <0x74>; + status = "okay"; + }; +}; + +&i2c1 { + status = "okay"; + clock-frequency = <300000>; + pinctrl-names="default"; + pinctrl-0=<&i2c1_dv_pins>; +}; + +&pinctrl_periphs { + /*i2s*/ + aml_audio_i2s: aml_audio_i2s { + mux { + groups = "i2s_mclk_h", + "i2s_sclk_h", + "i2s_lrclk_h", + "i2s_dout01_h6"; + function = "i2s"; + }; + }; + /*spdif*/ + audio_spdif_out_pins: audio_spdif_out_pins { + mux { + groups = "spdif_out_dv"; + function = "spdif_out"; + }; + }; + audio_spdif_out_mute_pins: audio_spdif_out_mute_pins { + mux { + groups = "GPIODV_6"; + function = "gpio_periphs"; + }; + }; + /*pcm*/ + aml_audio_pcm: aml_audio_pcm { + mux { + groups = + "pcm_clk_a_dv", + "pcm_fs_a_dv", + "pcm_in_a_dv", + "pcm_out_a_dv"; + function = "pcm_a"; + }; + }; + + /*lcd_extern*/ + lcd_extern_off_pins:lcd_extern_off_pin { + mux { + pins = "GPIOH_2", + "GPIOH_3"; + function = "gpio_periphs"; + /*output-high;*/ + output-low; + /*input-enable;*/ + }; + }; + + /*backlight*/ + bl_pwm_on_pins:bl_pwm_on_pin { + mux { + pins = "pwm_b"; + function = "pwm_b"; + }; + }; + bl_pwm_vs_on_pins:bl_pwm_vs_on_pin { + mux { + pins = "pwm_vs_z6"; + function = "pwm_vs"; + }; + }; + bl_pwm_off_pins:bl_pwm_off_pin { + mux { + pins = "GPIOZ_6"; + function = "gpio_periphs"; + output-low; + }; + }; + bl_pwm_combo_0_on_pins:bl_pwm_combo_0_on_pin { + mux { + pins = "pwm_b"; + function = "pwm_b"; + }; + }; + bl_pwm_combo_1_on_pins:bl_pwm_combo_1_on_pin { + mux { + pins = "pwm_c_z"; + function = "pwm_c"; + }; + }; + bl_pwm_combo_0_vs_on_pins:bl_pwm_combo_0_vs_on_pin { + mux { + pins = "pwm_vs_z6"; + function = "pwm_vs"; + }; + }; + bl_pwm_combo_1_vs_on_pins:bl_pwm_combo_1_vs_on_pin { + mux { + pins = "pwm_vs_z7"; + function = "pwm_vs"; + }; + }; + bl_pwm_combo_off_pins:bl_pwm_combo_off_pin { + mux { + pins = "GPIOZ_6", + "GPIOZ_7"; + function = "gpio_periphs"; + output-low; + }; + }; +}; + +&uart_A { + status = "okay"; +}; + +&audio_data{ + status = "okay"; +}; + +&pwm_AO_ab { + status = "okay"; +}; + +&pwm_ab { + status = "okay"; +}; + +&pwm_cd { + status = "okay"; +}; + +&spicc0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&spi_a_pins>; + cs-gpios = <&gpio GPIOZ_3 0>; +}; diff --git a/arch/arm/boot/dts/amlogic/txlx_t962x_r314.dts b/arch/arm/boot/dts/amlogic/txlx_t962x_r314.dts new file mode 100644 index 000000000000..dd614f178f72 --- /dev/null +++ b/arch/arm/boot/dts/amlogic/txlx_t962x_r314.dts @@ -0,0 +1,1651 @@ +/* + * arch/arm/boot/dts/amlogic/txlx_t962x_r311_1g.dts + * + * Copyright (C) 2017 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +/dts-v1/; +#include +#include + +#include "mesontxlx.dtsi" +#include "partition_mbox_normal_P_32.dtsi" +#include "mesontxlx_r311-panel.dtsi" + +/ { + model = "Amlogic"; + amlogic-dt-id = "txlx_t962x_r314"; + compatible = "amlogic, txlx"; + interrupt-parent = <&gic>; + #address-cells = <1>; + #size-cells = <1>; + + aliases { + serial0 = &uart_AO; + serial1 = &uart_A; + serial2 = &uart_B; + serial3 = &uart_C; + serial4 = &uart_AO_B; + spi0 = &spicc0; + spi1 = &spicc1; + }; + + ion_dev { + compatible = "amlogic, ion_dev"; + memory-region = <&ion_reserved>; + }; + + memory@00000000 { + device_type = "memory"; + linux,usable-memory = <0x100000 0x5ff00000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + /* global autoconfigured region for contiguous allocations */ + ramoops@0x07400000 { + compatible = "ramoops"; + reg = <0x07400000 0x00100000>; + record-size = <0x8000>; + console-size = <0x8000>; + ftrace-size = <0x0>; + pmsg-size = <0x8000>; + }; + secmon_reserved:linux,secmon { + compatible = "shared-dma-pool"; + reusable; + size = <0x400000>; + alignment = <0x400000>; + alloc-ranges = <0x05000000 0x400000>; + }; + + //secos_reserved:linux,secos { + // status = "disabled"; + // compatible = "amlogic, aml_secos_memory"; + // reg = <0x0 0x05300000 0x0 0x2000000>; + // no-map; + //}; + + + + logo_reserved:linux,meson-fb { + compatible = "shared-dma-pool"; + reusable; + size = <0x800000>; + alignment = <0x400000>; + alloc-ranges = <0x5f800000 0x800000>; + }; + + //carveout_reserved:linux,carveout-reserve { + // compatible = "amlogic, idev-mem"; + // size = <0x0 0x1000>; + //}; + + + codec_mm_cma:linux,codec_mm_cma { + compatible = "shared-dma-pool"; + reusable; + /* ion_codec_mm max can alloc size 80M*/ + size = <0xd000000>; + alignment = <0x400000>; + linux,contiguous-region; + alloc-ranges = <0x30000000 0x10000000>; + }; + ion_reserved:linux,ion-dev { + compatible = "shared-dma-pool"; + reusable; + size = <0x4C00000>; + alignment = <0x400000>; + alloc-ranges = <0x0 0x30000000>; + }; + + /*di CMA pool */ + di_cma_reserved:linux,di_cma { + compatible = "shared-dma-pool"; + reusable; + /* buffer_size = 3621952(yuv422 8bit) + * | 4736064(yuv422 10bit) + * | 4179008(yuv422 10bit full pack mode) + * 10x3621952=34.6M(0x23) support 8bit + * 10x4736064=45.2M(0x2e) support 12bit + * 10x4179008=40M(0x28) support 10bit + */ + size = <0x02800000>; + alignment = <0x400000>; + alloc-ranges = <0x30000000 0x10000000>; + }; + + /* POST PROCESS MANAGER */ + ppmgr_reserved:linux,ppmgr { + compatible = "amlogic, ppmgr_memory"; + size = <0x0>; + }; + + picdec_cma_reserved:linux,picdec { + compatible = "shared-dma-pool"; + reusable; + size = <0x0>; + alignment = <0x0>; + linux,contiguous-region; + }; + + /* codec shared reserved */ + codec_mm_reserved:linux,codec_mm_reserved { + compatible = "amlogic, codec-mm-reserved"; + size = <0x0>; + alignment = <0x100000>; + //no-map; + }; + + demod_cma_reserved:linux,demod_cma { + compatible = "shared-dma-pool"; + reusable; + /* 5M */ + size = <0x0800000>; + alignment = <0x400000>; + alloc-ranges = <0x0 0x30000000>; + }; + + /* vdin1 CMA pool */ + vdin1_cma_reserved:linux,vdin1_cma { + compatible = "shared-dma-pool"; + linux,phandle = <5>; + reusable; + /* 1920x1080x2x4 =16+4 M */ + size = <0x01400000>; + alignment = <0x400000>; + alloc-ranges = <0x0 0x30000000>; + }; + + /*vbi reserved mem*/ + vbi_reserved:linux,vbi { + compatible = "amlogic, vbi-mem"; + size = <0x100000>; + alloc-ranges = <0x0e000000 0x800000>; + }; + }; + + amlogic_battery:dummy-battery { + compatible = "amlogic, dummy-battery"; + status = "disabled"; + }; + + amlogic_charger:dummy-charger { + compatible = "amlogic, dummy-charger"; + status = "disabled"; + }; + + /* for external keypad */ + adc_keypad { + compatible = "amlogic, adc_keypad"; + status = "okay"; + key_name = "power","up","down","enter","left","right","home"; + key_num = <7>; + io-channels = <&saradc SARADC_CH2>, + <&saradc SARADC_CH3>; + io-channel-names = "key-chan-2", "key-chan-3"; + key_chan = ; + key_code = <116 103 108 28 105 106 102>; + key_val = <0 143 266 389 512 143 266>; //val=voltage/1800mV*1023 + key_tolerance = <40 40 40 40 40 40 40>; + }; + + gpioleds { + compatible = "gpio-leds"; + status = "okay"; + + sys { + label = "sysled"; + gpios = <&gpio_ao GPIOAO_3 GPIO_ACTIVE_HIGH>; + default-state = "on"; /* keep/on/off */ + linux,default-trigger = "none"; + }; + + }; + + pwmleds { + compatible = "pwm-leds"; + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&pwmleds_pins>; + + sys { + active-low; + label = "sysled"; + max-brightness = <255>; + pwms = <&pwm_AO_ab 0 50000 0>; + }; + }; + + ethmac: ethernet@0xff3f0000 { + compatible = "amlogic, gxbb-eth-dwmac"; + status = "okay"; + reg = <0xff3f0000 0x10000 + 0xff634540 0x8 + 0xff634558 0xc + 0xffd01084 0x4>; + interrupts = <0 8 1 + 0 9 1>; + + phy-mode= "rmii"; + mc_val_internal_phy = <0x1804>; + mc_val_external_phy = <0x1621>; + interrupt-names = "macirq", + "phyirq"; + clocks = <&clkc CLKID_ETH_CORE>; + clock-names = "ethclk81"; + internal_phy = <1>; + }; + + vout { + compatible = "amlogic, vout"; + dev_name = "vout"; + status = "okay"; + fr_auto_policy = <0>; + }; + + meson-fb { + compatible = "amlogic, meson-txlx"; + memory-region = <&logo_reserved>; + dev_name = "meson-fb"; + status = "okay"; + interrupts = <0 3 1 + 0 89 1>; + interrupt-names = "viu-vsync", "rdma"; + mem_size = <0x00800000 0x01800000 0x00100000>; + /* uboot logo,fb0/fb1 memory size,if afbcd fb0=0x01851000*/ + display_mode_default = "1080p60hz"; + /* 0:VPU free scale 1:OSD free scale 2:OSD super scale */ + scale_mode = <1>; + /* 1920*1080*4*3 = 0x17BB000 */ + display_size_default = <1920 1080 1920 3240 32>; + pxp_mode = <0>; /** 0:normal mode 1:pxp mode */ + logo_addr = "0x5f800000"; + }; + + ge2d { + compatible = "amlogic, ge2d-txlx"; + dev_name = "ge2d"; + status = "okay"; + interrupts = <0 150 1>; + interrupt-names = "ge2d"; + clocks = <&clkc CLKID_VAPB_MUX>, + <&clkc CLKID_G2D>, + <&clkc CLKID_GE2D_GATE>; + clock-names = "clk_vapb_0", + "clk_ge2d", + "clk_ge2d_gate"; + reg = <0xff940000 0x10000>; + }; + + codec_io { + compatible = "amlogic, codec_io"; + status = "okay"; + #address-cells=<1>; + #size-cells=<1>; + ranges; + io_cbus_base{ + reg = <0xffd00000 0x100000>; + }; + io_dos_base{ + reg = <0xff620000 0x10000>; + }; + io_hiubus_base{ + reg = <0xff63c000 0x2000>; + }; + io_aobus_base{ + reg = <0xff800000 0x10000>; + }; + io_vcbus_base{ + reg = <0xff900000 0x40000>; + }; + io_dmc_base{ + reg = <0xff638000 0x2000>; + }; + }; + + codec_mm { + compatible = "amlogic, codec, mm"; + memory-region = <&codec_mm_cma &codec_mm_reserved>; + dev_name = "codec_mm"; + status = "okay"; + }; + + mesonstream { + compatible = "amlogic, codec, streambuf"; + dev_name = "mesonstream"; + status = "okay"; + clocks = <&clkc CLKID_DOS_PARSER + &clkc CLKID_DEMUX + &clkc CLKID_DOS + &clkc CLKID_CLK81 + &clkc CLKID_VDEC_MUX + &clkc CLKID_HCODEC_MUX + &clkc CLKID_HEVC_MUX>; + clock-names = "parser_top", + "demux", + "vdec", + "clk_81", + "clk_vdec_mux", + "clk_hcodec_mux", + "clk_hevc_mux"; + }; + + vdec { + compatible = "amlogic, vdec"; + dev_name = "vdec.0"; + status = "okay"; + interrupts = <0 3 1 + 0 23 1 + 0 32 1 + 0 43 1 + 0 44 1 + 0 45 1>; + interrupt-names = "vsync", + "demux", + "parser", + "mailbox_0", + "mailbox_1", + "mailbox_2"; + }; + + meson-amvideom { + compatible = "amlogic, amvideom"; + dev_name = "amvideom"; + status = "okay"; + interrupts = <0 3 1>; + interrupt-names = "vsync"; + }; + + + + amvideocap { + compatible = "amlogic, amvideocap"; + dev_name = "amvideocap.0"; + status = "disabled"; + max_size = <8>;//8M + }; + + picdec { + compatible = "amlogic, picdec"; + memory-region = <&picdec_cma_reserved>; + dev_name = "picdec"; + status = "okay"; + }; + + ppmgr { + compatible = "amlogic, ppmgr"; + memory-region = <&ppmgr_reserved>; + dev_name = "ppmgr"; + status = "okay"; + }; + + deinterlace { + compatible = "amlogic, deinterlace"; + status = "okay"; + /* 0:use reserved; 1:use cma; 2:use cma as reserved */ + flag_cma = <1>; + //memory-region = <&di_reserved>; + memory-region = <&di_cma_reserved>; + interrupts = <0 46 1 + 0 6 1>; + interrupt-names = "de_irq"; + clocks = <&clkc CLKID_VPU_MUX>, + <&clkc CLKID_FCLK_DIV4>, + <&clkc CLKID_VPU_CLKB_TMP_COMP>, + <&clkc CLKID_VPU_CLKB_COMP>; + clock-names = "vpu_mux", + "fclk_div4", + "vpu_clkb_tmp_composite", + "vpu_clkb_composite"; + clock-range = <250 500>; + /* buffer-size = <3621952>;(yuv422 8bit) */ + buffer-size = <4179008>;/*yuv422 fullpack*/ + /* reserve-iomap = "true"; */ + /* if enable nr10bit, set nr10bit-support to 1 */ + nr10bit-support = <1>; + }; + ionvideo { + compatible = "amlogic, ionvideo"; + dev_name = "ionvideo"; + status = "okay"; + }; + + amlvideo { + compatible = "amlogic, amlvideo"; + dev_name = "amlvideo"; + status = "okay"; + }; + + amlvideo2_0 { + compatible = "amlogic, amlvideo2"; + dev_name = "amlvideo2"; + status = "okay"; + amlvideo2_id = <0>; + cma_mode = <1>; + }; + + amlvideo2_1 { + compatible = "amlogic, amlvideo2"; + dev_name = "amlvideo2"; + status = "okay"; + amlvideo2_id = <1>; + cma_mode = <1>; + }; + + hdmirx { + compatible = "amlogic, hdmirx_txlx"; + #address-cells=<1>; + #size-cells=<1>; + dev_name = "hdmirx"; + status = "okay"; + pinctrl-names = "hdmirx_pins"; + pinctrl-0 = <&hdmirx_a_mux &hdmirx_b_mux + &hdmirx_c_mux &hdmirx_d_mux>; + repeat = <0>; + interrupts = <0 56 1>; + clocks = <&clkc CLKID_HDMIRX_MODET_COMP>, + <&clkc CLKID_HDMIRX_CFG_COMP>, + <&clkc CLKID_HDMIRX_ACR_COMP>, + <&clkc CLKID_HDMIRX_AUDMEAS_COMP>, + <&xtal>, + <&clkc CLKID_FCLK_DIV5>, + <&clkc CLKID_FCLK_DIV7>, + <&clkc CLKID_HDCP22_SKP_COMP>, + <&clkc CLKID_HDCP22_ESM_COMP>; + // <&clkc CLK_AUD_PLL2FS>, + // <&clkc CLK_AUD_PLL4FS>, + // <&clkc CLK_AUD_OUT>; + clock-names = "hdmirx_modet_clk", + "hdmirx_cfg_clk", + "hdmirx_acr_ref_clk", + "hdmirx_audmeas_clk", + "xtal", + "fclk_div5", + "fclk_div7", + "hdcp_rx22_skp", + "hdcp_rx22_esm"; + // "hdmirx_aud_pll2fs", + // "hdmirx_aud_pll4f", + // "clk_aud_out"; + hdmirx_id = <0>; + en_4k_2_2k = <0>; + hpd_low_cec_off = <1>; + /* bit4: enable feature, bit3~0: port number */ + disable_port = <0x0>; + reg = <0xffd26000 0xa00000 + 0xff63C000 0x2000 + 0xffe0d000 0x2000 + 0xff63e000 0x2000 + 0x0 0x0 + 0xff634400 0x2000 + 0xff646000 0x2000>; + }; + + vdin0 { + compatible = "amlogic, vdin"; + /*memory-region = <&vdin0_cma_reserved>;*/ + dev_name = "vdin0"; + status = "okay"; + reserve-iomap = "true"; + /*bit0:(1:share with codec_mm;0:cma alone)*/ + /*bit8:(1:alloc in discontinus way;0:alone in continuous way)*/ + flag_cma = <0x101>; + /* MByte, if 10bit disable: 64M(YUV422), + * if 10bit enable: 64*1.5 = 96M(YUV422) + * if support 4K2K-YUV444-10bit-WR:3840*2160*4*4 ~= 128M + * if support 4K2K-YUV444-10bit-WR:3840*2160*4*6 ~= 190M + * if support 4K2K-YUV422-10bit-wr:3840*2160*3*4 ~= 96M + * if support 4K2K-YUV422-8BIT-WR:3840*2160*2*4 ~= 64M + * if support 1080p-YUV422-8BIT-WR:1920*1080*2*4 ~= 16M + */ + cma_size = <190>; + interrupts = <0 83 1>; + rdma-irq = <2>; + clocks = <&clkc CLKID_FCLK_DIV5>, + <&clkc CLKID_VDIN_MEAS_COMP>; + clock-names = "fclk_div5", "cts_vdin_meas_clk"; + vdin_id = <0>; + /* vdin write mem color depth support: + * bit0:support 8bit + * bit1:support 9bit + * bit2:support 10bit + * bit3:support 12bit + * bit4:support yuv422 10bit full pack mode (from txl new add) + * bit8:use 8bit at 4k_50/60hz_10bit + * bit9:use 10bit at 4k_50/60hz_10bit + */ + tv_bit_mode = <0x215>; + }; + + vdin1 { + compatible = "amlogic, vdin"; + memory-region = <&vdin1_cma_reserved>; + dev_name = "vdin1"; + status = "okay"; + reserve-iomap = "true"; + flag_cma = <0>;/*1:share with codec_mm;0:cma alone*/ + interrupts = <0 85 1>; + rdma-irq = <4>; + clocks = <&clkc CLKID_FCLK_DIV5>, + <&clkc CLKID_VDIN_MEAS_COMP>; + clock-names = "fclk_div5", "cts_vdin_meas_clk"; + vdin_id = <1>; + /* vdin write mem color depth support: + * bit0:support 8bit + * bit1:support 9bit + * bit2:support 10bit + * bit3:support 12bit + */ + tv_bit_mode = <1>; + }; + + tvafe { + compatible = "amlogic, tvafe-txlx"; + /*memory-region = <&tvafe_cma_reserved>;*/ + dev_name = "tvafe"; + status = "okay"; + flag_cma = <1>;/*1:share with codec_mm;0:cma alone*/ + cma_size = <5>;/*MByte*/ + reg = <0xff642000 0x2000>;/*tvafe reg base*/ + reserve-iomap = "true"; + tvafe_id = <0>; + //pinctrl-names = "default"; + /*!!particular sequence, no more and no less!!!*/ + tvafe_pin_mux = < + 3 /* TVAFE_CVBS_IN2, CVBS_IN0 = 0 */ + 1 /* TVAFE_CVBS_IN0, CVBS_IN1 */ + 2 /* TVAFE_CVBS_IN1, CVBS_IN2 */ + 4 /* TVAFE_CVBS_IN3, CVBS_IN3 */ + >; + clocks = <&clkc CLKID_DAC_CLK>; + clock-names = "vdac_clk_gate"; + }; + + vbi { + compatible = "amlogic, vbi"; + memory-region = <&vbi_reserved>; + dev_name = "vbi"; + status = "okay"; + interrupts = <0 83 1>; + reserve-iomap = "true"; + }; + + tvafe_avin_detect { + compatible = "amlogic, tvafe_avin_detect"; + dev_name = "tvafe_avin_detect"; + status = "okay"; + device_mask = <1>;/*bit0:ch1;bit1:ch2*/ + interrupts = <0 12 1>, + <0 13 1>; + }; + + amlvecm { + compatible = "amlogic, vecm"; + dev_name = "aml_vecm"; + status = "okay"; + gamma_en = <1>;/*1:enabel ;0:disable*/ + wb_en = <1>;/*1:enabel ;0:disable*/ + cm_en = <1>;/*1:enabel ;0:disable*/ + wb_sel = <1>;/*1:mtx ;0:gainoff*/ + vlock_en = <1>;/*1:enable;0:disable*/ + vlock_mode = <0x4>; + /* vlock work mode: + *bit0:auto ENC + *bit1:auto PLL + *bit2:manual PLL + *bit3:manual ENC + *bit4:manual soft ENC + *bit5:manual MIX PLL ENC + */ + vlock_pll_m_limit = <1>; + vlock_line_limit = <3>; + }; + amdolby_vision { + compatible = "amlogic, dolby_vision_txlx"; + dev_name = "aml_amdolby_vision_driver"; + status = "okay"; + tv_mode = <1>;/*1:enabel ;0:disable*/ + }; + amvenc_avc { + compatible = "amlogic, amvenc_avc"; + //memory-region = <&amvenc_avc_reserved>; + //memory-region = <&avc_cma_reserved>; + dev_name = "amvenc_avc"; + status = "okay"; + interrupts = <0 45 1>; + interrupt-names = "mailbox_2"; + }; + + tuner: tuner { + status = "okay"; + tuner_name = "mxl661_tuner"; + tuner_i2c_adap = <&i2c1>; + tuner_i2c_addr = <0x60>; + tuner_xtal = <0>; /* 0: 16MHz, 1: 24MHz */ + tuner_xtal_mode = <0>; + /* NO_SHARE_XTAL(0) + * SLAVE_XTAL_SHARE(1) + */ + tuner_xtal_cap = <30>; /* when tuner_xtal_mode = 1, set 25 */ + }; + + atv-demod { + compatible = "amlogic, atv-demod"; + status = "okay"; + tuner = <&tuner>; + btsc_sap_mode = <1>; + /* pinctrl-names="atvdemod_agc_pins"; */ + /* pinctrl-0=<&atvdemod_agc_pins>; */ + reg = <0xff640000 0x2000 /* demod reg */ + 0xff63c000 0x2000 /* hiu reg */ + 0xff634000 0x2000 /* periphs reg */ + 0xff648000 0x2000>; /* audio reg */ + reg_23cf = <0x88188832>; + /*default:0x88188832;r840 on haier:0x48188832*/ + }; + + bt-dev { + compatible = "amlogic, bt-dev"; + dev_name = "bt-dev"; + status = "okay"; + power_down_disable = <1>; + gpio_reset = <&gpio_ao GPIOAO_8 GPIO_ACTIVE_HIGH>; + //gpio_en = <&gpio_ao GPIOAO_5 GPIO_ACTIVE_HIGH>; + }; + + rtc { + compatible = "amlogic, aml_vrtc"; + alarm_reg_addr = <0xff8000a8>; + timer_e_addr = <0xffd0f188>; + init_date = "2015/01/01"; + status = "okay"; + }; + + wifi { + compatible = "amlogic, aml_wifi"; + dev_name = "aml_wifi"; + status = "okay"; + interrupt_pin = <&gpio_ao GPIOAO_4 GPIO_ACTIVE_HIGH>; + interrupts = <0 68 4>; + irq_trigger_type = "GPIO_IRQ_HIGH"; + dhd_static_buf; + power_on_pin = <&gpio_ao GPIOAO_5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_32k_pins>; + pwm_config = <&wifi_pwm_conf>; + }; + + wifi_pwm_conf: wifi_pwm_conf { + pwm_channel1_conf { + pwms = <&pwm_cd MESON_PWM_1 30040 0>; + duty-cycle = <15020>; + times = <10>; + }; + pwm_channel2_conf { + pwms = <&pwm_cd MESON_PWM_3 30030 0>; + duty-cycle = <15015>; + times = <12>; + }; + }; + + sd_emmc_c: emmc@ffe07000 { + status = "okay"; + compatible = "amlogic, meson-mmc-txlx"; + reg = <0xffe07000 0x2000>; + interrupts = <0 218 1>; + pinctrl-names = "emmc_clk_cmd_pins", "emmc_all_pins"; + pinctrl-0 = <&emmc_clk_cmd_pins>; + pinctrl-1 = <&emmc_conf_pull_up &emmc_conf_pull_done>; + clocks = <&clkc CLKID_SD_EMMC_C>, + <&clkc CLKID_SD_EMMC_C_P0_COMP>, + <&clkc CLKID_FCLK_DIV2>, + <&clkc CLKID_FCLK_DIV5>, + <&xtal>; + clock-names = "core", "clkin0", "clkin1", "clkin2", "xtal"; + + bus-width = <8>; + cap-sd-highspeed; + cap-mmc-highspeed; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + + max-frequency = <200000000>; + non-removable; + disable-wp; + emmc { + status = "disabled"; + pinname = "emmc"; + ocr_avail = <0x200080>; /**VDD voltage 3.3 ~ 3.4 */ + caps = "MMC_CAP_8_BIT_DATA", + "MMC_CAP_MMC_HIGHSPEED", + "MMC_CAP_SD_HIGHSPEED", + "MMC_CAP_NONREMOVABLE", + "MMC_CAP_1_8V_DDR", + "MMC_CAP_HW_RESET", + "MMC_CAP_ERASE", + "MMC_CAP_CMD23"; + caps2 = "MMC_CAP2_HS200", "MMC_CAP2_HS400"; + f_min = <400000>; + f_max = <200000000>; + max_req_size = <0x20000>; /**128KB*/ + gpio_dat3 = <&gpio BOOT_3 GPIO_ACTIVE_HIGH>; + hw_reset = <&gpio BOOT_9 GPIO_ACTIVE_HIGH>; + card_type = <1>; + /* 1:mmc card(include eMMC), + * 2:sd card(include tSD) + */ + }; + }; + + sd_emmc_b: sd@ffe05000 { + status = "okay"; + compatible = "amlogic, meson-mmc-txlx"; + reg = <0xffe05000 0x2000>; + interrupts = <0 217 1>; + pinctrl-names = "sd_all_pins", + "sd_clk_cmd_pins", + "sd_1bit_pins", + "sd_clk_cmd_uart_pins", + "sd_1bit_uart_pins", + "sd_to_ao_uart_pins", + "ao_to_sd_uart_pins", + "ao_to_sd_jtag_pins", + "sd_to_ao_jtag_pins"; + pinctrl-0 = <&sd_all_pins>; + pinctrl-1 = <&sd_clk_cmd_pins>; + pinctrl-2 = <&sd_1bit_pins>; + pinctrl-3 = <&sd_to_ao_uart_clr_pins + &sd_clk_cmd_pins &ao_to_sd_uart_pins>; + pinctrl-4 = <&sd_to_ao_uart_clr_pins + &sd_1bit_pins &ao_to_sd_uart_pins>; + pinctrl-5 = <&sd_all_pins &sd_to_ao_uart_pins>; + pinctrl-6 = <&sd_to_ao_uart_clr_pins &ao_to_sd_uart_pins>; + pinctrl-7 = <&sd_to_ao_uart_clr_pins &ao_to_sd_uart_pins>; + pinctrl-8 = <&sd_all_pins &sd_to_ao_uart_pins>; + clocks = <&clkc CLKID_SD_EMMC_B>, + <&clkc CLKID_SD_EMMC_B_P0_COMP>, + <&clkc CLKID_FCLK_DIV2>, + <&clkc CLKID_FCLK_DIV5>, + <&xtal>; + clock-names = "core", "clkin0", "clkin1", "clkin2", "xtal"; + + bus-width = <4>; + cap-sd-highspeed; + max-frequency = <100000000>; + disable-wp; + sd { + status = "disabled"; + pinname = "sd"; + ocr_avail = <0x200080>; /**VDD voltage 3.3 ~ 3.4 */ + caps = "MMC_CAP_4_BIT_DATA", + "MMC_CAP_MMC_HIGHSPEED", + "MMC_CAP_SD_HIGHSPEED"; + /* "MMC_CAP_UHS_SDR12", + * "MMC_CAP_UHS_SDR25", + * "MMC_CAP_UHS_SDR50", + * "MMC_CAP_UHS_SDR104"; + */ + f_min = <400000>; + f_max = <200000000>; + max_req_size = <0x20000>; /**128KB*/ + gpio_dat3 = <&gpio GPIOC_4 GPIO_ACTIVE_HIGH>; + jtag_pin = <&gpio GPIOC_0 GPIO_ACTIVE_HIGH>; + gpio_cd = <&gpio GPIOH_10 GPIO_ACTIVE_HIGH>; + card_type = <5>; + /* 3:sdio device(ie:sdio-wifi), + * 4:SD combo (IO+mem) card + * 5:NON sdio device(means sd/mmc card) + */ + }; + }; + + unifykey { + compatible = "amlogic, unifykey"; + status = "okay"; + + unifykey-num = <20>; + unifykey-index-0 = <&keysn_0>; + unifykey-index-1 = <&keysn_1>; + unifykey-index-2 = <&keysn_2>; + unifykey-index-3 = <&keysn_3>; + unifykey-index-4 = <&keysn_4>; + unifykey-index-5 = <&keysn_5>; + unifykey-index-6 = <&keysn_6>; + unifykey-index-7 = <&keysn_7>; + unifykey-index-8 = <&keysn_8>; + unifykey-index-9 = <&keysn_9>; + unifykey-index-10= <&keysn_10>; + unifykey-index-11 = <&keysn_11>; + unifykey-index-12 = <&keysn_12>; + unifykey-index-13 = <&keysn_13>; + unifykey-index-14 = <&keysn_14>; + unifykey-index-15 = <&keysn_15>; + unifykey-index-16 = <&keysn_16>; + unifykey-index-17 = <&keysn_17>; + unifykey-index-18 = <&keysn_18>; + unifykey-index-19 = <&keysn_19>; + + keysn_0: key_0{ + key-name = "usid"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_1:key_1{ + key-name = "mac"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_2:key_2{ + key-name = "hdcp"; + key-device = "secure"; + key-type = "sha1"; + key-permit = "read","write","del"; + }; + keysn_3:key_3{ + key-name = "secure_boot_set"; + key-device = "efuse"; + key-permit = "write"; + }; + keysn_4:key_4{ + key-name = "mac_bt"; + key-device = "normal"; + key-permit = "read","write","del"; + key-type = "mac"; + }; + keysn_5:key_5{ + key-name = "mac_wifi"; + key-device = "normal"; + key-permit = "read","write","del"; + key-type = "mac"; + }; + keysn_6:key_6{ + key-name = "hdcp2_tx"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_7:key_7{ + key-name = "hdcp2_rx"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_8:key_8{ + key-name = "widevinekeybox"; + key-device = "secure"; + key-type = "sha1"; + key-permit = "read","write","del"; + }; + keysn_9:key_9{ + key-name = "deviceid"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_10:key_10{ + key-name = "hdcp22_fw_private"; + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_11:key_11{ + key-name = "hdcp22_rx_private"; + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_12:key_12{ + key-name = "hdcp22_rx_fw"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_13:key_13{ + key-name = "hdcp14_rx"; + key-device = "normal"; + key-type = "sha1"; + key-permit = "read","write","del"; + }; + keysn_14:key_14{ + key-name = "prpubkeybox";// PlayReady + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_15:key_15{ + key-name = "prprivkeybox";// PlayReady + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_16:key_16{ + key-name = "lcd"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_17:key_17{ + key-name = "lcd_extern"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_18:key_18{ + key-name = "backlight"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_19:key_19{ + key-name = "attestationkeybox";// attestation key + key-device = "secure"; + key-permit = "read","write","del"; + }; + }; /* End unifykey */ + + cvbsout { + compatible = "amlogic, cvbsout-txlx"; + dev_name = "cvbsout"; + status = "disabled"; + clocks = <&clkc CLKID_VCLK2_ENCI + &clkc CLKID_VCLK2_VENCI0 + &clkc CLKID_VCLK2_VENCI1 + &clkc CLKID_DAC_CLK>; + clock-names = "venci_top_gate", + "venci_0_gate", + "venci_1_gate", + "vdac_clk_gate"; + + /* performance: reg_address, reg_value */ + performance = <0x1b56 0x343 + 0x1b05 0xf4 + 0x1c59 0xfc48 + 0x1b12 0x8c00 + 0xffff 0x0>; /* ending flag */ + }; + + amhdmitx: amhdmitx { + compatible = "amlogic, amhdmitx"; + dev_name = "amhdmitx"; + status = "disabled"; + pinctrl-names="default", "hdmitx_i2c"; + pinctrl-0=<&hdmitx_hpd &hdmitx_ddc>; + pinctrl-1=<&hdmitx_hpd_gpio &i2c2_h_pins>; + /* HPD, 57 + 32 = 89; CEC, 151 + 32 = 183*/ + interrupts = <0 57 1>; + interrupt-names = "hdmitx_hpd"; + /* 0:M8B 1:GXBB 2:GXTVBB 3:GXL 4:GXM + * 5:TXL 6:TXLX 7:AXG 8:GXLX 9:TXHD + */ + ic_type = <6>; + //gpio_i2c_en = <0>; + //repeater_tx = <0x1>; + //#address-cells = <2>; + //#size-cells = <2>; + //ranges; + }; + + i2c_gpio: i2c_gpio { + compatible = "i2c-gpio"; + dev_name = "i2c-gpio"; + status = "disabled"; + i2c-gpio,delay-us = <10>; /* 50 kHz */ + gpios = <&gpio GPIOH_2 0 + &gpio GPIOH_3 0>; + #address-cells = <2>; + #size-cells = <2>; + i2c-gpio,timeout-ms = <10>; + i2c_gpio_edid: i2c_gpio_edid { + compatible = "i2c-gpio"; + reg = <0x50 0x0 0x0 0x0>; + }; + }; + + aocec: aocec { + compatible = "amlogic, aocec-txlx"; + device_name = "aocec"; + status = "okay"; + vendor_name = "Amlogic"; /* Max Chars: 8 */ + /* Refer to the following URL at: + * http://standards.ieee.org/develop/regauth/oui/oui.txt + */ + vendor_id = <0x000000>; + product_desc = "TXLX"; /* Max Chars: 16 */ + cec_osd_string = "AML_TV"; /* Max Chars: 14 */ + port_num = <4>; + /*ee_cec;*/ + arc_port_mask = <0x2>; + interrupts = <0 205 1 + 0 199 1>; + interrupt-names = "hdmi_aocecb","hdmi_aocec"; + pinctrl-names = "default","hdmitx_aocecb","cec_pin_sleep"; + pinctrl-0=<&hdmitx_aocec>; + pinctrl-1=<&hdmitx_aocecb>; + pinctrl-2=<&hdmitx_aocecb>; + reg = <0xFF80023c 0x4 + 0xFF800000 0x400>; + reg-names = "ao_exit","ao"; + }; + + + canvas { + compatible = "amlogic, meson, canvas"; + dev_name = "amlogic-canvas"; + status = "okay"; + reg = <0xff638000 0x2000>; + }; + + rdma { + compatible = "amlogic, meson, rdma"; + dev_name = "amlogic-rdma"; + status = "okay"; + interrupts = <0 89 1>; + interrupt-names = "rdma"; + }; + + dwc3: dwc3@ff500000 { + compatible = "synopsys, dwc3"; + status = "okay"; + reg = <0xff500000 0x100000>; + interrupts = <0 30 4>; + usb-phy = <&usb2_phy>, <&usb3_phy>; + cpu-type = "gxl"; + clock-src = "usb3.0"; + }; + + usb2_phy: usb2phy@ffe09000 { + compatible = "amlogic, amlogic-new-usb2"; + status = "okay"; + portnum = <4>; + reg = <0xffe09000 0x80 + 0xffd01008 0x4>; + }; + + usb3_phy: usb3phy@ffe09080 { + compatible = "amlogic, amlogic-new-usb3"; + status = "okay"; + portnum = <0>; + reg = <0xffe09080 0x20>; + }; + + dwc2_a { + compatible = "amlogic, dwc2"; + device_name = "dwc2_a"; + reg = <0xff400000 0x40000>; + status = "okay"; + interrupts = <0 31 4>; + pl-periph-id = <0>; /** lm name */ + clock-src = "usb0"; /** clock src */ + port-id = <0>; /** ref to mach/usb.h */ + port-type = <2>; /** 0: otg, 1: host, 2: slave */ + port-speed = <0>; /** 0: default, high, 1: full */ + port-config = <0>; /** 0: default */ + /*0:default,1:single,2:incr,3:incr4,4:incr8,5:incr16,6:disable*/ + port-dma = <0>; + port-id-mode = <0>; /** 0: hardware, 1: sw_host, 2: sw_slave*/ + usb-fifo = <728>; + cpu-type = "gxl"; + /** 0: normal, 1: otg+dwc3 host only, 2: otg+dwc3 device only*/ + controller-type = <1>; + phy-reg = <0xffe09000>; + phy-reg-size = <0xa0>; + clocks = <&clkc CLKID_USB_GENERAL + &clkc CLKID_USB1_TO_DDR>; + clock-names = "usb_general", + "usb1"; + }; + + /* Sound iomap */ + aml_snd_iomap { + compatible = "amlogic, meson-snd-iomap"; + status = "okay"; + #address-cells=<1>; + #size-cells=<1>; + ranges; + io_audin_base { + reg = <0xffd03000 0x100000>; + }; + io_aiu_base { + reg = <0xFFCFFC00 0x100000>; + }; + io_eqdrc_base { + reg = <0xFFCFF000 0x100000>; + }; + io_hiu_reset_base { + reg = <0xFFCFCC00 0x100000>; + }; + io_isa_base { + reg = <0xFFD05800 0x100000>; + }; + }; + + /* AUDIO DEVICES */ + i2s_dai: I2S { + #sound-dai-cells = <0>; + /* config mpll whether same with audin */ + clocks = <&clkc CLKID_MPLL3>, + <&clkc CLKID_AMCLK_COMP>, + <&clkc CLKID_AIU_GLUE>, + <&clkc CLKID_I2S_OUT>, + <&clkc CLKID_AMCLK_MEASURE>, + <&clkc CLKID_AIFIFO2>, + <&clkc CLKID_MIXER>, + <&clkc CLKID_MIXER_IFACE>, + <&clkc CLKID_ADC>, + <&clkc CLKID_AIU_TOP>, + <&clkc CLKID_AOCLK_GATE>, + <&clkc CLKID_I2S_SPDIF>, + <&clkc CLKID_DAC_CLK>; + clock-names = "mpll", + "mclk", + "top_glue", + "i2s_out", + "amclk_measure", + "aififo2", + "aud_mixer", + "mixer_reg", + "adc", + "top_level", + "aoclk", + "aud_in", + "vdac_clk"; + compatible = "amlogic, aml-i2s-dai"; + }; + + i2s2_dai: I2S2 { + #sound-dai-cells = <0>; + /* config mpll whether same with aiu */ + clocks = <&clkc CLKID_MPLL2>, + <&clkc CLKID_AUDIN_MCLK_COMP>, + <&clkc CLKID_AUDIN_SCLK_COMP>, + <&clkc CLKID_AUDIN_LRCLK_COMP>; + clock-names = "audin_mpll", + "audin_mclk", + "audin_sclk", + "audin_lrclk"; + compatible = "amlogic, aml-i2s2-dai"; + }; + + spdif_dai: SPDIF { + #sound-dai-cells = <0>; + compatible = "amlogic, aml-spdif-dai"; + clocks = <&clkc CLKID_MPLL1>, + <&clkc CLKID_IEC958_INT_COMP>, + <&clkc CLKID_AMCLK_COMP>, + <&clkc CLKID_IEC958_MUX>, + <&clkc CLKID_CLK81>, + <&clkc CLKID_IEC958>, + <&clkc CLKID_IEC958_GATE>; + clock-names = + "mpll1", + "i958", + "mclk", + "spdif", + "clk_81", + "iec958", + "iec958_amclk"; + }; + + pcm_dai: PCM { + #sound-dai-cells = <0>; + compatible = "amlogic, aml-pcm-dai"; + pinctrl-names = "audio_pcm"; + /* disable pcm pin mux temporary, enable it if necessary */ + /*pinctrl-0 = <&aml_audio_pcm>;*/ + clocks = <&clkc CLKID_MPLL0>, + <&clkc CLKID_PCM_MCLK_COMP>, + <&clkc CLKID_PCM_SCLK_COMP>; + clock-names = "mpll0", "pcm_mclk", "pcm_sclk"; + pcm_mode = <1>; /* 0=slave mode, 1=master mode */ + }; + + i2s_plat: i2s_platform { + compatible = "amlogic, aml-i2s"; + interrupts = <0 29 1>; + }; + + pcm_plat: pcm_platform { + compatible = "amlogic, aml-pcm"; + }; + + spdif_codec: spdif_codec{ + #sound-dai-cells = <0>; + compatible = "amlogic, aml-spdif-codec"; + pinctrl-names = "audio_spdif_out", "audio_spdif_out_mute"; + pinctrl-0 = <&audio_spdif_out_pins>; + pinctrl-1 = <&audio_spdif_out_mute_pins>; + }; + + pcm_codec: pcm_codec{ + #sound-dai-cells = <0>; + compatible = "amlogic, pcm2BT-codec"; + }; + /* end of AUDIO DEVICES */ + + /* AUDIO board specific */ + dummy_codec:dummy{ + #sound-dai-cells = <0>; + compatible = "amlogic, aml_dummy_codec"; + status = "okay"; + }; + + amlogic_codec:txlx_acodec{ + #sound-dai-cells = <0>; + compatible = "amlogic, txlx_acodec"; + reg = <0xFF632000 0x1c>; + status = "okay"; + }; + + aml_snd_tv { + compatible = "amlogic, txlx-snd-tv"; + status = "okay"; + aml-sound-card,format = "i2s"; + aml_sound_card,name = "AML-TVAUDIO"; + pinctrl-names = "audio_i2s"; + pinctrl-0 = <&aml_audio_i2s>; + /*avout mute gpio*/ + mute_gpio-gpios = <&gpio GPIODV_5 GPIO_ACTIVE_HIGH>; + /*analog amp mute*/ + /*amp_mute_gpio-gpios = <&gpio GPIOZ_18 GPIO_ACTIVE_LOW>;*/ + aux_dev = <&tas5707>; + cpu_list = <&cpudai0 &cpudai1 &cpudai2 &cpudai3>; + codec_list = <&codec0 &codec1 &codec2 &codec3>; + plat_list = <&i2s_plat &i2s_plat &pcm_plat &i2s_plat>; + cpudai0: cpudai0 { + sound-dai = <&i2s_dai>; + }; + cpudai1: cpudai1 { + sound-dai = <&spdif_dai>; + }; + cpudai2: cpudai2 { + sound-dai = <&pcm_dai>; + }; + cpudai3: cpudai3 { + sound-dai = <&i2s2_dai>; + }; + codec0: codec0 { + sound-dai = <&amlogic_codec>; + }; + codec1: codec1 { + sound-dai = <&spdif_codec>; + }; + codec2: codec2 { + sound-dai = <&pcm_codec>; + }; + codec3: codec3 { + sound-dai = <&dummy_codec>; + }; + Channel_Mask { + /*i2s has 4 pins, 8channel, mux output*/ + Speaker0_Channel_Mask = "i2s_2/3"; + DAC0_Channel_Mask = "i2s_2/3"; + DAC1_Channel_Mask = "i2s_2/3"; + EQ_DRC_Channel_Mask = "i2s_2/3"; + Spdif_samesource_Channel_Mask = "i2s_0/1"; + }; + }; + + amaudio2 { + compatible = "amlogic, aml_amaudio2"; + status = "okay"; + interrupts = <0 48 1>; + }; + /* end of AUDIO board specific */ + + + aml_sensor0: aml-sensor@0 { + compatible = "amlogic, aml-thermal"; + device_name = "thermal"; + status = "okay"; + #thermal-sensor-cells = <1>; + cooling_devices { + cpufreq_cool_cluster0 { + min_state = <1000000>; + dyn_coeff = <140>; + cluster_id = <0>; + node_name = "cpus"; + device_type = "cpufreq"; + }; + cpucore_cool_cluster0 { + min_state = <1>; + dyn_coeff = <0>; + cluster_id = <0>; + node_name = "cpu_core_cluster0"; + device_type = "cpucore"; + }; + gpufreq_cool { + min_state = <400>; + dyn_coeff = <437>; + cluster_id = <0>; + node_name = "mali"; + device_type = "gpufreq"; + }; + gpucore_cool { + min_state = <1>; + dyn_coeff = <0>; + cluster_id = <0>; + node_name = "thermal_gpu_cores"; + device_type = "gpucore"; + }; + }; + cpu_cluster0:cpu_core_cluster0 { + #cooling-cells = <2>; /* min followed by max */ + }; + gpucore:thermal_gpu_cores { + #cooling-cells = <2>; /* min followed by max */ + }; + }; + + dvb { + compatible = "amlogic, dvb"; + dev_name = "dvb"; + status = "okay"; + fe0_mode = "internal"; + fe0_tuner = <&tuner>; + /*"parallel","serial","disable"*/ + ts2 = "parallel"; + ts2_control = <0>; + ts2_invert = <0>; + interrupts = <0 23 1 + 0 5 1 + 0 53 1 + 0 19 1 + 0 25 1 + 0 18 1 + 0 24 1>; + interrupt-names = "demux0_irq", + "demux1_irq", + "demux2_irq", + "dvr0_irq", + "dvr1_irq", + "dvrfill0_fill", + "dvrfill1_flush"; + clocks = <&clkc CLKID_DEMUX + &clkc CLKID_ASYNC_FIFO + &clkc CLKID_AHB_ARB0 + &clkc CLKID_DOS_PARSER>; + clock-names = "demux", "asyncfifo", "ahbarb0", "uparsertop"; + }; + aml_dtv_demod { + compatible = "amlogic, ddemod-txlx"; + dev_name = "aml_dtv_demod"; + status = "okay"; + + //pinctrl-names="dtvdemod_agc"; + //pinctrl-0=<&dtvdemod_agc>; + + + clocks = <&clkc CLKID_DAC_CLK>; + clock-names = "vdac_clk_gate"; + + + reg = <0xff644000 0x2000 /*dtv demod base*/ + 0xff63c000 0x2000 /*hiu reg base*/ + 0xff800000 0x1000 /*io_aobus_base*/ + 0xffd01000 0x1000 /*reset*/ + >; + /*move from dvbfe*/ + dtv_demod0_mem = <0>; // need move to aml_dtv_demod ? + spectrum = <1>; + cma_flag = <1>; + cma_mem_size = <8>; + memory-region = <&demod_cma_reserved>;//<&demod_reserved>; + }; + dvbfe { + compatible = "amlogic, dvbfe"; + dev_name = "dvbfe"; + status = "disabled"; + dtv_demod0 = "AMLDEMOD"; + fe0_dtv_demod = <0>; + fe0_ts = <2>; + fe0_dev = <0>; + dtv_demod0_mem = <0>; + dtv_demod0_spectrum = <1>; + dtv_demod0_cma_flag = <1>; + dtv_demod0_cma_mem_size = <8>; + memory-region = <&demod_cma_reserved>;//<&demod_reserved>; + tuner0 = "si2151_tuner"; + tuner0_i2c_adap_id = <2>; + tuner0_i2c_addr = <0x60>; + //tuner0_reset_value = <0>; + //tuner0_reset_gpio = "GPIOY_10" ; /*GPIOX_8 76*/ + fe0_tuner = <0>; + atv_demod0 = "aml_atv_demod"; + fe0_atv_demod = <0>; + }; + + thermal-zones { + soc_thermal { + polling-delay = <1000>; + polling-delay-passive = <100>; + sustainable-power = <2150>; + + thermal-sensors = <&aml_sensor0 3>; + + trips { + switch_on: trip-point@0 { + temperature = <70000>; + hysteresis = <1000>; + type = "passive"; + }; + control: trip-point@1 { + temperature = <80000>; + hysteresis = <1000>; + type = "passive"; + }; + hot: trip-point@2 { + temperature = <85000>; + hysteresis = <5000>; + type = "hot"; + }; + critical: trip-point@3 { + temperature = <260000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + + cooling-maps { + cpufreq_cooling_map { + trip = <&control>; + cooling-device = <&cpus 0 4>; + contribution = <1024>; + }; + cpucore_cooling_map { + trip = <&control>; + cooling-device = <&cpu_cluster0 0 3>; + contribution = <1024>; + }; + gpufreq_cooling_map { + trip = <&control>; + cooling-device = <&gpu 0 4>; + contribution = <1024>; + }; + gpucore_cooling_map { + trip = <&control>; + cooling-device = <&gpucore 0 2>; + contribution = <1024>; + }; + }; + }; + }; + +}; /* end of / */ + +&i2c2 { + status = "okay"; + pinctrl-names="default"; + pinctrl-0=<&i2c2_h_pins>; + + tas5707: tas5707@36 { + compatible = "ti,tas5707"; + #sound-dai-cells = <0>; + codec_name = "tas5707"; + reg = <0x1B>; + reset_pin = <&gpio GPIODV_4 GPIO_ACTIVE_LOW>; + eq_enable = <0>; + drc_enable = <0>; + status = "okay"; + }; + + lcd_extern_i2c0: lcd_extern_i2c@0 { + compatible = "lcd_ext, i2c"; + dev_name = "i2c_T5800Q"; + reg = <0x1c>; + status = "okay"; + }; + + lcd_extern_i2c1: lcd_extern_i2c@1 { + compatible = "lcd_ext, i2c"; + dev_name = "i2c_ANX6862"; + reg = <0x20>; + status = "okay"; + }; + + lcd_extern_i2c2: lcd_extern_i2c@2 { + compatible = "lcd_ext, i2c"; + dev_name = "i2c_ANX7911"; + reg = <0x74>; + status = "okay"; + }; +}; + +&i2c1 { + status = "okay"; + clock-frequency = <300000>; + pinctrl-names="default"; + pinctrl-0=<&i2c1_dv_pins>; +}; + +&pinctrl_periphs { + /*i2s*/ + aml_audio_i2s: aml_audio_i2s { + mux { + groups = "i2s_mclk_h", + "i2s_sclk_h", + "i2s_lrclk_h", + "i2s_dout01_h6"; + function = "i2s"; + }; + }; + /*spdif*/ + audio_spdif_out_pins: audio_spdif_out_pins { + mux { + groups = "spdif_out_dv"; + function = "spdif_out"; + }; + }; + audio_spdif_out_mute_pins: audio_spdif_out_mute_pins { + mux { + groups = "GPIODV_6"; + function = "gpio_periphs"; + }; + }; + /*pcm*/ + aml_audio_pcm: aml_audio_pcm { + mux { + groups = + "pcm_clk_a_dv", + "pcm_fs_a_dv", + "pcm_in_a_dv", + "pcm_out_a_dv"; + function = "pcm_a"; + }; + }; + + /*lcd_extern*/ + lcd_extern_off_pins:lcd_extern_off_pin { + mux { + pins = "GPIOH_2", + "GPIOH_3"; + function = "gpio_periphs"; + /*output-high;*/ + output-low; + /*input-enable;*/ + }; + }; + + /*backlight*/ + bl_pwm_on_pins:bl_pwm_on_pin { + mux { + pins = "pwm_b"; + function = "pwm_b"; + }; + }; + bl_pwm_vs_on_pins:bl_pwm_vs_on_pin { + mux { + pins = "pwm_vs_z6"; + function = "pwm_vs"; + }; + }; + bl_pwm_off_pins:bl_pwm_off_pin { + mux { + pins = "GPIOZ_6"; + function = "gpio_periphs"; + output-low; + }; + }; + bl_pwm_combo_0_on_pins:bl_pwm_combo_0_on_pin { + mux { + pins = "pwm_b"; + function = "pwm_b"; + }; + }; + bl_pwm_combo_1_on_pins:bl_pwm_combo_1_on_pin { + mux { + pins = "pwm_c_z"; + function = "pwm_c"; + }; + }; + bl_pwm_combo_0_vs_on_pins:bl_pwm_combo_0_vs_on_pin { + mux { + pins = "pwm_vs_z6"; + function = "pwm_vs"; + }; + }; + bl_pwm_combo_1_vs_on_pins:bl_pwm_combo_1_vs_on_pin { + mux { + pins = "pwm_vs_z7"; + function = "pwm_vs"; + }; + }; + bl_pwm_combo_off_pins:bl_pwm_combo_off_pin { + mux { + pins = "GPIOZ_6", + "GPIOZ_7"; + function = "gpio_periphs"; + output-low; + }; + }; +}; + +&uart_A { + status = "okay"; +}; + +&audio_data{ + status = "okay"; +}; + +&pwm_AO_ab { + status = "okay"; +}; + +&pwm_ab { + status = "okay"; +}; + +&pwm_cd { + status = "okay"; +}; + +&spicc0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&spi_a_pins>; + cs-gpios = <&gpio GPIOZ_3 0>; +}; diff --git a/arch/arm/configs/meson64_a32_defconfig b/arch/arm/configs/meson64_a32_defconfig index fc40c3f2b1aa..db75074efec6 100644 --- a/arch/arm/configs/meson64_a32_defconfig +++ b/arch/arm/configs/meson64_a32_defconfig @@ -361,10 +361,12 @@ CONFIG_AMLOGIC_SARADC=y CONFIG_AMLOGIC_DDR_TOOL=y CONFIG_AMLOGIC_DDR_BANDWIDTH=y CONFIG_AMLOGIC_TEE=y +CONFIG_AMLOGIC_RAMDUMP=y CONFIG_AMLOGIC_GPIO_IRQ=y CONFIG_AMLOGIC_ATV_DEMOD=y CONFIG_AMLOGIC_DEBUG=y CONFIG_AMLOGIC_DEBUG_LOCKUP=y +CONFIG_AMLOGIC_DEFENDKEY=y CONFIG_AMLOGIC_BATTERY_DUMMY=y CONFIG_AMLOGIC_CHARGER_DUMMY=y CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" @@ -458,8 +460,12 @@ CONFIG_REGULATOR_PWM=y CONFIG_MEDIA_SUPPORT=y CONFIG_MEDIA_CAMERA_SUPPORT=y CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y +CONFIG_MEDIA_RC_SUPPORT=y CONFIG_MEDIA_USB_SUPPORT=y CONFIG_USB_VIDEO_CLASS=y +CONFIG_VIDEO_CX231XX=y +# CONFIG_VIDEO_CX231XX_RC is not set +CONFIG_VIDEO_CX231XX_DVB=y CONFIG_FB=y CONFIG_BACKLIGHT_LCD_SUPPORT=y CONFIG_BACKLIGHT_CLASS_DEVICE=y @@ -474,6 +480,7 @@ CONFIG_AMLOGIC_SND_CODEC_PDM_DUMMY_CODEC=y CONFIG_AMLOGIC_SND_CODEC_AMLT9015=y CONFIG_AMLOGIC_SND_CODEC_AMLT9015S=y CONFIG_AMLOGIC_SND_CODEC_TXLX_ACODEC=y +CONFIG_AMLOGIC_SND_CODEC_TL1_ACODEC=y CONFIG_AMLOGIC_SND_SOC_TAS5707=y CONFIG_AMLOGIC_SND_SOC_TLV320ADC3101=y CONFIG_AMLOGIC_SND_SOC_PCM186X=y @@ -617,5 +624,10 @@ CONFIG_CRYPTO_USER_API_SKCIPHER=y CONFIG_ASYMMETRIC_KEY_TYPE=y CONFIG_ASYMMETRIC_PUBLIC_KEY_SUBTYPE=y CONFIG_X509_CERTIFICATE_PARSER=y +CONFIG_ARM_CRYPTO=y +CONFIG_CRYPTO_SHA1_ARM_CE=y +CONFIG_CRYPTO_SHA2_ARM_CE=y +CONFIG_CRYPTO_AES_ARM_CE=y +CONFIG_CRYPTO_GHASH_ARM_CE=y CONFIG_CRC_T10DIF=y CONFIG_CRC7=y diff --git a/arch/arm/include/uapi/asm/setup.h b/arch/arm/include/uapi/asm/setup.h index 979ff4016404..b4d1bea21a2d 100644 --- a/arch/arm/include/uapi/asm/setup.h +++ b/arch/arm/include/uapi/asm/setup.h @@ -16,7 +16,7 @@ #include -#define COMMAND_LINE_SIZE 1024 +#define COMMAND_LINE_SIZE 2048 /* The list ends with an ATAG_NONE node. */ #define ATAG_NONE 0x00000000 diff --git a/arch/arm64/Makefile b/arch/arm64/Makefile index 88fdf46de644..1412c114b413 100644 --- a/arch/arm64/Makefile +++ b/arch/arm64/Makefile @@ -145,7 +145,11 @@ zinstall install: $(Q)$(MAKE) $(build)=$(boot) $@ %.dtb: scripts - $(Q)$(MAKE) $(build)=$(boot)/dts $(boot)/dts/$@ + $(Q)$(MAKE) $(build)=$(boot)/dts/amlogic $(boot)/dts/amlogic/$@ +ifeq ($(CONFIG_AMLOGIC_MODIFY),y) +%.dtbo: scripts + $(Q)$(MAKE) $(build)=$(boot)/dts/amlogic $(boot)/dts/amlogic/$@ +endif PHONY += dtbs dtbs_install diff --git a/arch/arm64/boot/dts/amlogic/android_p_overlay_dt.dts b/arch/arm64/boot/dts/amlogic/android_p_overlay_dt.dts new file mode 100644 index 000000000000..42efa870557c --- /dev/null +++ b/arch/arm64/boot/dts/amlogic/android_p_overlay_dt.dts @@ -0,0 +1,43 @@ +/* + * arch/arm64/boot/dts/amlogic/android_p_overlay_dt.dts + * + * Copyright (C) 2017 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +/dts-v1/; +/plugin/; + +/ { + fragment@0 { + //target = <&some_node>; + target-path="/"; + __overlay__ { + dummy-battery { + compatible = "amlogic, dummy-battery"; + status = "okay"; + }; + }; + }; + + fragment@1 { + //target = <&some_node>; + target-path="/"; + __overlay__ { + dummy-charger { + compatible = "amlogic, dummy-charger"; + status = "okay"; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/amlogic/atom.dts b/arch/arm64/boot/dts/amlogic/atom.dts index d347fe800f93..1a17056270e4 100644 --- a/arch/arm64/boot/dts/amlogic/atom.dts +++ b/arch/arm64/boot/dts/amlogic/atom.dts @@ -775,7 +775,7 @@ compatible = "amlogic, unifykey"; status = "okay"; - unifykey-num = <18>; + unifykey-num = <21>; unifykey-index-0 = <&keysn_0>; unifykey-index-1 = <&keysn_1>; unifykey-index-2 = <&keysn_2>; @@ -794,6 +794,9 @@ unifykey-index-15 = <&keysn_15>; unifykey-index-16 = <&keysn_16>; unifykey-index-17 = <&keysn_17>; + unifykey-index-18 = <&keysn_18>; + unifykey-index-19 = <&keysn_19>; + unifykey-index-20 = <&keysn_20>; keysn_0: key_0{ key-name = "usid"; @@ -890,6 +893,21 @@ key-device = "secure"; key-permit = "read","write","del"; }; + keysn_18:key_18{ + key-name = "hdcp22_rprx_fw"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_19:key_19{ + key-name = "hdcp22_rprp_fw"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_20:key_20{ + key-name = "hdcp22_rp_private"; + key-device = "secure"; + key-permit = "read","write","del"; + }; }; /* End unifykey */ @@ -974,15 +992,16 @@ cec_osd_string = "AML_TV"; /* Max Chars: 14 */ port_num = <4>; /*all port number*/ /*ee_cec;*/ + cec_sel = <2>; output = <1>; arc_port_mask = <0x8>; interrupts = <0 205 1 0 199 1>; interrupt-names = "hdmi_aocecb","hdmi_aocec"; pinctrl-names = "default","hdmitx_aocecb","cec_pin_sleep"; - pinctrl-0=<&hdmitx_aocec>; - pinctrl-1=<&hdmitx_aocecb>; - pinctrl-2=<&hdmitx_aocecb>; + pinctrl-0=<&hdmitx_aocec &hdmitx_aocecb1>; + pinctrl-1=<&hdmitx_aocec &hdmitx_aocecb1>; + pinctrl-2=<&hdmitx_aocec &hdmitx_aocecb1>; reg = <0x0 0xFF80023c 0x0 0x4 0x0 0xFF800000 0x0 0x400>; reg-names = "ao_exit","ao"; diff --git a/arch/arm64/boot/dts/amlogic/axg_s400_v03.dts b/arch/arm64/boot/dts/amlogic/axg_s400_v03.dts index 5625611be3a3..9eb474a08714 100644 --- a/arch/arm64/boot/dts/amlogic/axg_s400_v03.dts +++ b/arch/arm64/boot/dts/amlogic/axg_s400_v03.dts @@ -663,6 +663,7 @@ f_max = <200000000>; max_req_size = <0x20000>; /**128KB*/ gpio_dat3 = <&gpio BOOT_3 GPIO_ACTIVE_HIGH>; + tx_delay = <4>; hw_reset = <&gpio BOOT_9 GPIO_ACTIVE_HIGH>; card_type = <1>; /* 1:mmc card(include eMMC), diff --git a/arch/arm64/boot/dts/amlogic/axg_s400_v03gva.dts b/arch/arm64/boot/dts/amlogic/axg_s400_v03gva.dts index e2e68c014e4a..945d4fb5b223 100644 --- a/arch/arm64/boot/dts/amlogic/axg_s400_v03gva.dts +++ b/arch/arm64/boot/dts/amlogic/axg_s400_v03gva.dts @@ -1150,8 +1150,8 @@ * 4: pdmin; */ datain_src = <4>; - datain_chnum = <8>; - datain_chmask = <0x7f>; + datain_chnum = <4>; + datain_chmask = <0x3>; /* tdmin_lb src * 0: tdmoutA @@ -1167,7 +1167,7 @@ datalb_chnum = <2>; /*config which data pin as loopback*/ /*datalb-lane-mask-in = <0 0 0 1>;*/ - datalb_chmask = <0x1>; + datalb_chmask = <0x3>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/amlogic/axg_s420_v03gva.dts b/arch/arm64/boot/dts/amlogic/axg_s420_v03gva.dts index 90e16bf91051..80262564dac6 100644 --- a/arch/arm64/boot/dts/amlogic/axg_s420_v03gva.dts +++ b/arch/arm64/boot/dts/amlogic/axg_s420_v03gva.dts @@ -971,8 +971,8 @@ * 4: pdmin; */ datain_src = <4>; - datain_chnum = <8>; - datain_chmask = <0x7f>; + datain_chnum = <4>; + datain_chmask = <0x3>; /* tdmin_lb src * 0: tdmoutA @@ -988,7 +988,7 @@ datalb_chnum = <2>; /*config which data pin as loopback*/ /*datalb-lane-mask-in = <0 1>;*/ - datalb_chmask = <0x1>; + datalb_chmask = <0x3>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/amlogic/firmware_ab.dtsi b/arch/arm64/boot/dts/amlogic/firmware_ab.dtsi new file mode 100644 index 000000000000..328b7f1abab0 --- /dev/null +++ b/arch/arm64/boot/dts/amlogic/firmware_ab.dtsi @@ -0,0 +1,54 @@ +/* + * arch/arm64/boot/dts/amlogic/firmware_ab.dtsi + * + * Copyright (C) 2017 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +/ { +firmware { + android { + compatible = "android,firmware"; + vbmeta { + compatible = "android,vbmeta"; + parts = "vbmeta,boot,system,vendor"; + by_name_prefix="/dev/block"; + }; + fstab { + compatible = "android,fstab"; + + vendor { + compatible = "android,vendor"; + dev = "/dev/block/vendor"; + type = "ext4"; + mnt_flags = "ro,barrier=1,inode_readahead_blks=8"; + fsmgr_flags = "wait,slotselect"; + }; + product { + compatible = "android,product"; + dev = "/dev/block/product"; + type = "ext4"; + mnt_flags = "ro,barrier=1,inode_readahead_blks=8"; + fsmgr_flags = "wait,slotselect"; + }; + odm { + compatible = "android,odm"; + dev = "/dev/block/odm"; + type = "ext4"; + mnt_flags = "ro,barrier=1,inode_readahead_blks=8"; + fsmgr_flags = "wait,slotselect"; + }; + }; + }; +}; +};/* end of / */ diff --git a/arch/arm64/boot/dts/amlogic/firmware_avb_ab.dtsi b/arch/arm64/boot/dts/amlogic/firmware_avb_ab.dtsi new file mode 100644 index 000000000000..0ec3f8cf1c82 --- /dev/null +++ b/arch/arm64/boot/dts/amlogic/firmware_avb_ab.dtsi @@ -0,0 +1,54 @@ +/* + * arch/arm64/boot/dts/amlogic/firmware_avb_ab.dtsi + * + * Copyright (C) 2017 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +/ { +firmware { + android { + compatible = "android,firmware"; + vbmeta { + compatible = "android,vbmeta"; + parts = "vbmeta,boot,system,vendor"; + by_name_prefix="/dev/block"; + }; + fstab { + compatible = "android,fstab"; + + vendor { + compatible = "android,vendor"; + dev = "/dev/block/vendor"; + type = "ext4"; + mnt_flags = "ro,barrier=1,inode_readahead_blks=8"; + fsmgr_flags = "wait,slotselect,avb"; + }; + product { + compatible = "android,product"; + dev = "/dev/block/product"; + type = "ext4"; + mnt_flags = "ro,barrier=1,inode_readahead_blks=8"; + fsmgr_flags = "wait,slotselect"; + }; + odm { + compatible = "android,odm"; + dev = "/dev/block/odm"; + type = "ext4"; + mnt_flags = "ro,barrier=1,inode_readahead_blks=8"; + fsmgr_flags = "wait,slotselect"; + }; + }; + }; +}; +};/* end of / */ diff --git a/arch/arm64/boot/dts/amlogic/g12a_s905d2_skt.dts b/arch/arm64/boot/dts/amlogic/g12a_s905d2_skt.dts index ccf02f082b45..e3e4c2f3fc65 100644 --- a/arch/arm64/boot/dts/amlogic/g12a_s905d2_skt.dts +++ b/arch/arm64/boot/dts/amlogic/g12a_s905d2_skt.dts @@ -195,7 +195,7 @@ bt-dev{ compatible = "amlogic, bt-dev"; dev_name = "bt-dev"; - status = "okay"; + status = "disable"; gpio_reset = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>; gpio_hostwake = <&gpio GPIOX_19 GPIO_ACTIVE_HIGH>; }; @@ -203,7 +203,7 @@ wifi{ compatible = "amlogic, aml_wifi"; dev_name = "aml_wifi"; - status = "okay"; + status = "disable"; interrupt_pin = <&gpio GPIOX_7 GPIO_ACTIVE_HIGH>; irq_trigger_type = "GPIO_IRQ_LOW"; power_on_pin = <&gpio GPIOX_6 GPIO_ACTIVE_HIGH>; @@ -639,23 +639,23 @@ }; opp05 { opp-hz = /bits/ 64 <1200000000>; - opp-microvolt = <731000>; + opp-microvolt = <761000>; }; opp06 { opp-hz = /bits/ 64 <1398000000>; - opp-microvolt = <761000>; + opp-microvolt = <791000>; }; opp07 { opp-hz = /bits/ 64 <1512000000>; - opp-microvolt = <791000>; + opp-microvolt = <831000>; }; opp08 { opp-hz = /bits/ 64 <1608000000>; - opp-microvolt = <831000>; + opp-microvolt = <871000>; }; opp09 { opp-hz = /bits/ 64 <1704000000>; - opp-microvolt = <861000>; + opp-microvolt = <921000>; }; opp10 { opp-hz = /bits/ 64 <1800000000>; diff --git a/arch/arm64/boot/dts/amlogic/g12a_s905d2_skt_buildroot.dts b/arch/arm64/boot/dts/amlogic/g12a_s905d2_skt_buildroot.dts index dd942baf97e7..acb0a415ae5d 100644 --- a/arch/arm64/boot/dts/amlogic/g12a_s905d2_skt_buildroot.dts +++ b/arch/arm64/boot/dts/amlogic/g12a_s905d2_skt_buildroot.dts @@ -182,7 +182,7 @@ bt-dev{ compatible = "amlogic, bt-dev"; dev_name = "bt-dev"; - status = "okay"; + status = "disable"; gpio_reset = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>; gpio_hostwake = <&gpio GPIOX_19 GPIO_ACTIVE_HIGH>; }; @@ -190,7 +190,7 @@ wifi{ compatible = "amlogic, aml_wifi"; dev_name = "aml_wifi"; - status = "okay"; + status = "disable"; interrupt_pin = <&gpio GPIOX_7 GPIO_ACTIVE_HIGH>; irq_trigger_type = "GPIO_IRQ_LOW"; power_on_pin = <&gpio GPIOX_6 GPIO_ACTIVE_HIGH>; @@ -600,23 +600,23 @@ }; opp05 { opp-hz = /bits/ 64 <1200000000>; - opp-microvolt = <731000>; + opp-microvolt = <761000>; }; opp06 { opp-hz = /bits/ 64 <1398000000>; - opp-microvolt = <761000>; + opp-microvolt = <791000>; }; opp07 { opp-hz = /bits/ 64 <1512000000>; - opp-microvolt = <791000>; + opp-microvolt = <831000>; }; opp08 { opp-hz = /bits/ 64 <1608000000>; - opp-microvolt = <831000>; + opp-microvolt = <871000>; }; opp09 { opp-hz = /bits/ 64 <1704000000>; - opp-microvolt = <861000>; + opp-microvolt = <921000>; }; opp10 { opp-hz = /bits/ 64 <1800000000>; diff --git a/arch/arm64/boot/dts/amlogic/g12a_s905d2_u200_buildroot_vccktest.dts b/arch/arm64/boot/dts/amlogic/g12a_s905d2_u200_buildroot_vccktest.dts new file mode 100644 index 000000000000..a17f04e32db3 --- /dev/null +++ b/arch/arm64/boot/dts/amlogic/g12a_s905d2_u200_buildroot_vccktest.dts @@ -0,0 +1,1393 @@ +/* + * arch/arm64/boot/dts/amlogic/g12a_s905d2_u200.dts + * + * Copyright (C) 2017 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +/dts-v1/; + +#include "mesong12a.dtsi" +#include "mesong12a_skt-panel.dtsi" + +/ { + model = "Amlogic"; + compatible = "amlogic, g12a"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + serial0 = &uart_AO; + serial1 = &uart_A; + serial2 = &uart_B; + serial3 = &uart_C; + serial4 = &uart_AO_B; + tsensor0 = &p_tsensor; + tsensor1 = &d_tsensor; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c_AO; + }; + + memory@00000000 { + device_type = "memory"; + linux,usable-memory = <0x0 0x100000 0x0 0x7ff00000>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + /* global autoconfigured region for contiguous allocations */ + secmon_reserved:linux,secmon { + compatible = "shared-dma-pool"; + reusable; + size = <0x0 0x400000>; + alignment = <0x0 0x400000>; + alloc-ranges = <0x0 0x05000000 0x0 0x400000>; + }; + secos_reserved:linux,secos { + status = "disable"; + compatible = "amlogic, aml_secos_memory"; + reg = <0x0 0x05300000 0x0 0x2000000>; + no-map; + }; + logo_reserved:linux,meson-fb { + compatible = "shared-dma-pool"; + reusable; + size = <0x0 0x800000>; + alignment = <0x0 0x400000>; + alloc-ranges = <0x0 0x7f800000 0x0 0x800000>; + }; + ion_cma_reserved:linux,ion-dev { + compatible = "shared-dma-pool"; + reusable; + size = <0x0 0x8000000>; + alignment = <0x0 0x400000>; + }; + //di_reserved:linux,di { + //compatible = "amlogic, di-mem"; + /* buffer_size = 3621952(yuv422 8bit) */ + /* 4179008(yuv422 10bit full pack mode) */ + /** 10x3621952=34.6M(0x23) support 8bit **/ + /** 10x4736064=45.2M(0x2e) support 12bit **/ + /** 10x4179008=40M(0x28) support 10bit **/ + //size = <0x0 0x2800000>; + //no-map; + //}; + /*di CMA pool */ + di_cma_reserved:linux,di_cma { + compatible = "shared-dma-pool"; + reusable; + /* buffer_size = 3621952(yuv422 8bit) + * | 4736064(yuv422 10bit) + * | 4074560(yuv422 10bit full pack mode) + * 10x3621952=34.6M(0x23) support 8bit + * 10x4736064=45.2M(0x2e) support 12bit + * 10x4074560=40M(0x28) support 10bit + */ + size = <0x0 0x02800000>; + alignment = <0x0 0x400000>; + }; + /* POST PROCESS MANAGER */ + ppmgr_reserved:linux,ppmgr { + compatible = "shared-dma-pool"; + size = <0x0 0x0>; + }; + + codec_mm_cma:linux,codec_mm_cma { + compatible = "shared-dma-pool"; + reusable; + /* ion_codec_mm max can alloc size 80M*/ + size = <0x0 0x13400000>; + sustainable-power = <1460>; + alignment = <0x0 0x400000>; + linux,contiguous-region; + }; + /* codec shared reserved */ + codec_mm_reserved:linux,codec_mm_reserved { + compatible = "amlogic, codec-mm-reserved"; + size = <0x0 0x0>; + alignment = <0x0 0x100000>; + //no-map; + }; + /* vdin0 CMA pool */ + vdin0_cma_reserved:linux,vdin0_cma { + compatible = "shared-dma-pool"; + reusable; + /* 1920x1080x2x4 =16+4 M */ + size = <0x0 0x04000000>; + alignment = <0x0 0x400000>; + }; + /* vdin1 CMA pool */ + vdin1_cma_reserved:linux,vdin1_cma { + compatible = "shared-dma-pool"; + reusable; + /* 1920x1080x2x4 =16 M */ + size = <0x0 0x04000000>; + alignment = <0x0 0x400000>; + }; + }; + + gpioleds { + compatible = "gpio-leds"; + status = "okay"; + + sys_led { + label="sys_led"; + gpios=<&gpio_ao GPIOAO_11 GPIO_ACTIVE_HIGH>; + default-state ="on"; + retain-state-suspended; + linux,default-trigger="cpu0"; + }; + }; + + cvbsout { + compatible = "amlogic, cvbsout-g12a"; + dev_name = "cvbsout"; + status = "okay"; + clocks = <&clkc CLKID_VCLK2_ENCI + &clkc CLKID_VCLK2_VENCI0 + &clkc CLKID_VCLK2_VENCI1 + &clkc CLKID_DAC_CLK>; + clock-names = "venci_top_gate", + "venci_0_gate", + "venci_1_gate", + "vdac_clk_gate"; + clk_path = <0>; + + /* performance: reg_address, reg_value */ + /* g12a */ + performance = <0x1bf0 0x9 + 0x1b56 0x333 + 0x1b12 0x8080 + 0x1b05 0xfd + 0x1c59 0xf850 + 0xffff 0x0>; /* ending flag */ + performance_sarft = <0x1bf0 0x9 + 0x1b56 0x333 + 0x1b12 0x0 + 0x1b05 0x9 + 0x1c59 0xfc48 + 0xffff 0x0>; /* ending flag */ + performance_revB_telecom = <0x1bf0 0x9 + 0x1b56 0x546 + 0x1b12 0x8080 + 0x1b05 0x9 + 0x1c59 0xf850 + 0xffff 0x0>; /* ending flag */ + }; + + bt-dev{ + compatible = "amlogic, bt-dev"; + dev_name = "bt-dev"; + status = "okay"; + gpio_reset = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>; + gpio_hostwake = <&gpio GPIOX_19 GPIO_ACTIVE_HIGH>; + }; + + wifi{ + compatible = "amlogic, aml_wifi"; + dev_name = "aml_wifi"; + status = "okay"; + interrupt_pin = <&gpio GPIOX_7 GPIO_ACTIVE_HIGH>; + irq_trigger_type = "GPIO_IRQ_LOW"; + power_on_pin = <&gpio GPIOX_6 GPIO_ACTIVE_HIGH>; + dhd_static_buf; //if use bcm wifi, config dhd_static_buf + pinctrl-names = "default"; + pinctrl-0 = <&pwm_e_pins>; + pwm_config = <&wifi_pwm_conf>; + }; + + wifi_pwm_conf:wifi_pwm_conf{ + pwm_channel1_conf { + pwms = <&pwm_ef MESON_PWM_0 30040 0>; + duty-cycle = <15020>; + times = <10>; + }; + pwm_channel2_conf { + pwms = <&pwm_ef MESON_PWM_2 30030 0>; + duty-cycle = <15015>; + times = <12>; + }; + }; + + codec_mm { + compatible = "amlogic, codec, mm"; + memory-region = <&codec_mm_cma &codec_mm_reserved>; + dev_name = "codec_mm"; + status = "okay"; + }; + + ppmgr { + compatible = "amlogic, ppmgr"; + memory-region = <&ppmgr_reserved>; + dev_name = "ppmgr"; + status = "okay"; + }; + + deinterlace { + compatible = "amlogic, deinterlace"; + status = "okay"; + /* 0:use reserved; 1:use cma; 2:use cma as reserved */ + flag_cma = <1>; + //memory-region = <&di_reserved>; + memory-region = <&di_cma_reserved>; + interrupts = <0 46 1 + 0 40 1>; + interrupt-names = "pre_irq", "post_irq"; + clocks = <&clkc CLKID_VPU_CLKB_TMP_COMP>, + <&clkc CLKID_VPU_CLKB_COMP>; + clock-names = "vpu_clkb_tmp_composite", + "vpu_clkb_composite"; + clock-range = <334 667>; + /* buffer-size = <3621952>;(yuv422 8bit) */ + buffer-size = <4074560>;/*yuv422 fullpack*/ + /* reserve-iomap = "true"; */ + /* if enable nr10bit, set nr10bit-support to 1 */ + post-wr-support = <1>; + nr10bit-support = <1>; + nrds-enable = <1>; + pps-enable = <1>; + }; + ionvideo { + compatible = "amlogic, ionvideo"; + dev_name = "ionvideo"; + status = "okay"; + }; + + gpio_keypad{ + compatible = "amlogic, gpio_keypad"; + status = "okay"; + scan_period = <20>; + key_num = <1>; + key_name = "power"; + key_code = <116>; + key-gpios = <&gpio_ao GPIOAO_3 GPIO_ACTIVE_HIGH>; + detect_mode = <0>;/*0:polling mode, 1:irq mode*/ + }; + + adc_keypad { + compatible = "amlogic, adc_keypad"; + status = "okay"; + key_name = "vol-", "vol+", "enter"; + key_num = <3>; + io-channels = <&saradc SARADC_CH2>; + io-channel-names = "key-chan-2"; + key_chan = ; + key_code = <114 115 28>; + key_val = <143 266 389>; //val=voltage/1800mV*1023 + key_tolerance = <40 40 40>; + }; + + partitions: partitions{ + parts = <14>; + part-0 = <&logo>; + part-1 = <&recovery>; + part-2 = <&misc>; + part-3 = <&dto>; + part-4 = <&cri_data>; + part-5 = <¶m>; + part-6 = <&boot>; + part-7 = <&rsv>; + part-8 = <&tee>; + part-9 = <&vendor>; + part-10 = <&odm>; + part-11 = <&system>; + part-12 = <&cache>; + part-13 = <&data>; + + logo:logo{ + pname = "logo"; + size = <0x0 0x800000>; + mask = <1>; + }; + recovery:recovery{ + pname = "recovery"; + size = <0x0 0x1800000>; + mask = <1>; + }; + misc:misc{ + pname = "misc"; + size = <0x0 0x800000>; + mask = <1>; + }; + dto:dto{ + pname = "dto"; + size = <0x0 0x800000>; + mask = <1>; + }; + cri_data:cri_data{ + pname = "cri_data"; + size = <0x0 0x800000>; + mask = <2>; + }; + rsv:rsv{ + pname = "rsv"; + size = <0x0 0x1000000>; + mask = <1>; + }; + param:param{ + pname = "param"; + size = <0x0 0x1000000>; + mask = <2>; + }; + boot:boot{ + pname = "boot"; + size = <0x0 0x1000000>; + mask = <1>; + }; + tee:tee{ + pname = "tee"; + size = <0x0 0x2000000>; + mask = <1>; + }; + vendor:vendor{ + pname = "vendor"; + size = <0x0 0x10000000>; + mask = <1>; + }; + odm:odm{ + pname = "odm"; + size = <0x0 0x10000000>; + mask = <1>; + }; + system:system{ + pname = "system"; + size = <0x0 0x80000000>; + mask = <1>; + }; + cache:cache{ + pname = "cache"; + size = <0x0 0x46000000>; + mask = <2>; + }; + data:data{ + pname = "data"; + size = <0xffffffff 0xffffffff>; + mask = <4>; + }; + }; + unifykey{ + compatible = "amlogic, unifykey"; + status = "ok"; + unifykey-num = <14>; + unifykey-index-0 = <&keysn_0>; + unifykey-index-1 = <&keysn_1>; + unifykey-index-2 = <&keysn_2>; + unifykey-index-3 = <&keysn_3>; + unifykey-index-4 = <&keysn_4>; + unifykey-index-5 = <&keysn_5>; + unifykey-index-6 = <&keysn_6>; + unifykey-index-7 = <&keysn_7>; + unifykey-index-8 = <&keysn_8>; + unifykey-index-9 = <&keysn_9>; + unifykey-index-10= <&keysn_10>; + unifykey-index-11= <&keysn_11>; + unifykey-index-12= <&keysn_12>; + unifykey-index-13= <&keysn_13>; + + keysn_0: key_0{ + key-name = "usid"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_1:key_1{ + key-name = "mac"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_2:key_2{ + key-name = "hdcp"; + key-device = "secure"; + key-type = "sha1"; + key-permit = "read","write","del"; + }; + keysn_3:key_3{ + key-name = "secure_boot_set"; + key-device = "efuse"; + key-permit = "write"; + }; + keysn_4:key_4{ + key-name = "mac_bt"; + key-device = "normal"; + key-permit = "read","write","del"; + key-type = "mac"; + }; + keysn_5:key_5{ + key-name = "mac_wifi"; + key-device = "normal"; + key-permit = "read","write","del"; + key-type = "mac"; + }; + keysn_6:key_6{ + key-name = "hdcp2_tx"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_7:key_7{ + key-name = "hdcp2_rx"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_8:key_8{ + key-name = "widevinekeybox"; + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_9:key_9{ + key-name = "deviceid"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_10:key_10{ + key-name = "hdcp22_fw_private"; + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_11:key_11{ + key-name = "PlayReadykeybox25"; + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_12:key_12{ + key-name = "prpubkeybox";// PlayReady + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_13:key_13{ + key-name = "prprivkeybox";// PlayReady + key-device = "secure"; + key-permit = "read","write","del"; + }; + };//End unifykey + + efusekey:efusekey{ + keynum = <4>; + key0 = <&key_0>; + key1 = <&key_1>; + key2 = <&key_2>; + key3 = <&key_3>; + key_0:key_0{ + keyname = "mac"; + offset = <0>; + size = <6>; + }; + key_1:key_1{ + keyname = "mac_bt"; + offset = <6>; + size = <6>; + }; + key_2:key_2{ + keyname = "mac_wifi"; + offset = <12>; + size = <6>; + }; + key_3:key_3{ + keyname = "usid"; + offset = <18>; + size = <16>; + }; + };//End efusekey + + amlvecm { + compatible = "amlogic, vecm"; + dev_name = "aml_vecm"; + status = "okay"; + gamma_en = <0>;/*1:enabel ;0:disable*/ + wb_en = <0>;/*1:enabel ;0:disable*/ + cm_en = <0>;/*1:enabel ;0:disable*/ + /*0: 709/601 1: bt2020*/ + tx_op_color_primary = <0>; + }; + + amdolby_vision { + compatible = "amlogic, dolby_vision_g12a"; + dev_name = "aml_amdolby_vision_driver"; + status = "okay"; + tv_mode = <0>;/*1:enabel ;0:disable*/ + }; + + /* Audio Related start */ + pdm_codec:dummy{ + #sound-dai-cells = <0>; + compatible = "amlogic, pdm_dummy_codec"; + status = "okay"; + }; + dummy_codec:dummy{ + #sound-dai-cells = <0>; + compatible = "amlogic, aml_dummy_codec"; + status = "okay"; + }; + amlogic_codec:t9015{ + #sound-dai-cells = <0>; + compatible = "amlogic, aml_codec_T9015"; + reg = <0x0 0xFF632000 0x0 0x2000>; + is_auge_used = <1>; /* meson or auge chipset used */ + tdmout_index = <1>; + status = "okay"; + }; + audio_effect:eqdrc{ + /*eq_enable = <1>;*/ + /*drc_enable = <1>;*/ + /* + * 0:tdmout_a + * 1:tdmout_b + * 2:tdmout_c + * 3:spdifout + * 4:spdifout_b + */ + eqdrc_module = <1>; + /* max 0xf, each bit for one lane, usually one lane */ + lane_mask = <0x1>; + /* max 0xff, each bit for one channel */ + channel_mask = <0x3>; + }; + auge_sound { + compatible = "amlogic, g12a-sound-card"; + aml-audio-card,name = "AML-AUGESOUND"; + + aml-audio-card,loopback = <&aml_loopback>; + aml-audio-card,aux-devs = <&amlogic_codec>; + /*avout mute gpio*/ + avout_mute-gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_HIGH>; + /*for audio effect ,eqdrc */ + aml-audio-card,effect = <&audio_effect>; + + aml-audio-card,dai-link@0 { + format = "dsp_a"; + mclk-fs = <512>; + //continuous-clock; + //bitclock-inversion; + //frame-inversion; + //bitclock-master = <&tdmacodec>; + //frame-master = <&tdmacodec>; + /* suffix-name, sync with android audio hal + * what's the dai link used for + */ + suffix-name = "alsaPORT-pcm"; + tdmacpu: cpu { + sound-dai = <&aml_tdma>; + dai-tdm-slot-tx-mask = + <1 1 1 1 1 1 1 1>; + dai-tdm-slot-rx-mask = + <1 1 1 1 1 1 1 1>; + dai-tdm-slot-num = <8>; + dai-tdm-slot-width = <32>; + system-clock-frequency = <24576000>; + }; + tdmacodec: codec { + sound-dai = <&dummy_codec &dummy_codec>; + }; + }; + + aml-audio-card,dai-link@1 { + format = "i2s";// "dsp_a"; + mclk-fs = <256>; + //continuous-clock; + //bitclock-inversion; + //frame-inversion; + bitclock-master = <&aml_tdmb>; + frame-master = <&aml_tdmb>; + //bitclock-master = <&tdmbcodec>; + //frame-master = <&tdmbcodec>; + /* suffix-name, sync with android audio hal + * what's the dai link used for + */ + suffix-name = "alsaPORT-i2s"; + cpu { + sound-dai = <&aml_tdmb>; + dai-tdm-slot-tx-mask = <1 1>; + dai-tdm-slot-rx-mask = <1 1>; + dai-tdm-slot-num = <2>; + /* + * dai-tdm-slot-tx-mask = + * <1 1 1 1 1 1 1 1>; + * dai-tdm-slot-rx-mask = + * <1 1 1 1 1 1 1 1>; + * dai-tdm-slot-num = <8>; + */ + dai-tdm-slot-width = <32>; + system-clock-frequency = <12288000>; + }; + tdmbcodec: codec { + sound-dai = <&dummy_codec &dummy_codec + &amlogic_codec &ad82584f_62>; + }; + }; + + aml-audio-card,dai-link@2 { + format = "i2s"; + mclk-fs = <256>; + //continuous-clock; + //bitclock-inversion; + //frame-inversion; + bitclock-master = <&aml_tdmc>; + frame-master = <&aml_tdmc>; + /* suffix-name, sync with android audio hal + * what's the dai link used for + */ + //suffix-name = "alsaPORT-tdm"; + cpu { + sound-dai = <&aml_tdmc>; + dai-tdm-slot-tx-mask = <1 1>; + dai-tdm-slot-rx-mask = <1 1>; + dai-tdm-slot-num = <2>; + dai-tdm-slot-width = <32>; + system-clock-frequency = <12288000>; + }; + codec { + sound-dai = <&tlv320adc3101_32 &dummy_codec>; + }; + }; + + aml-audio-card,dai-link@3 { + mclk-fs = <64>; + /* suffix-name, sync with android audio hal + * what's the dai link used for + */ + suffix-name = "alsaPORT-pdm"; + cpu { + sound-dai = <&aml_pdm>; + }; + codec { + sound-dai = <&pdm_codec>; + }; + }; + + aml-audio-card,dai-link@4 { + mclk-fs = <128>; + /* suffix-name, sync with android audio hal + * what's the dai link used for + */ + suffix-name = "alsaPORT-spdif"; + cpu { + sound-dai = <&aml_spdif>; + system-clock-frequency = <6144000>; + }; + codec { + sound-dai = <&dummy_codec>; + }; + }; + /* spdif_b to hdmi, only playback */ + aml-audio-card,dai-link@5 { + mclk-fs = <128>; + continuous-clock; + /* suffix-name, sync with android audio hal + * what's the dai link used for + */ + suffix-name = "alsaPORT-spdifb2hdmi"; + cpu { + sound-dai = <&aml_spdif_b>; + system-clock-frequency = <6144000>; + }; + codec { + sound-dai = <&dummy_codec>; + }; + }; + }; + audiolocker: locker { + compatible = "amlogic, audiolocker"; + clocks = <&clkaudio CLKID_AUDIO_LOCKER_OUT + &clkaudio CLKID_AUDIO_LOCKER_IN + &clkaudio CLKID_AUDIO_MCLK_D + &clkaudio CLKID_AUDIO_MCLK_E + &clkc CLKID_MPLL1 + &clkc CLKID_MPLL2>; + clock-names = "lock_out", "lock_in", "out_src", + "in_src", "out_calc", "in_ref"; + interrupts = ; + interrupt-names = "irq"; + frequency = <49000000>; /* pll */ + dividor = <49>; /* locker's parent */ + status = "okay"; + }; + /* Audio Related end */ + + /*DCDC for MP8756GD*/ + cpu_opp_table0: cpu_opp_table0 { + compatible = "operating-points-v2"; + opp-shared; + + opp00 { + opp-hz = /bits/ 64 <100000000>; + opp-microvolt = <731000>; + }; + opp01 { + opp-hz = /bits/ 64 <250000000>; + opp-microvolt = <731000>; + }; + opp02 { + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <731000>; + }; + opp03 { + opp-hz = /bits/ 64 <667000000>; + opp-microvolt = <731000>; + }; + opp04 { + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <731000>; + }; + opp05 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <731000>; + }; + opp06 { + opp-hz = /bits/ 64 <1398000000>; + opp-microvolt = <761000>; + }; + opp07 { + opp-hz = /bits/ 64 <1512000000>; + opp-microvolt = <791000>; + }; + opp08 { + opp-hz = /bits/ 64 <1608000000>; + opp-microvolt = <831000>; + }; + opp09 { + opp-hz = /bits/ 64 <1704000000>; + opp-microvolt = <861000>; + }; + opp10 { + opp-hz = /bits/ 64 <1800000000>; + opp-microvolt = <981000>; + }; + opp11 { + opp-hz = /bits/ 64 <1908000000>; + opp-microvolt = <1010000>; + }; + opp12 { + opp-hz = /bits/ 64 <2016000000>; + opp-microvolt = <1010000>; + }; + opp13 { + opp-hz = /bits/ 64 <2100000000>; + opp-microvolt = <1010000>; + }; + }; + + cpufreq-meson { + compatible = "amlogic, cpufreq-meson"; + pinctrl-names = "default"; + pinctrl-0 = <&pwm_ao_d_pins3>; + status = "okay"; + }; + +}; /* end of / */ + +&meson_fb { + status = "okay"; + display_size_default = <1920 1080 1920 2160 32>; + mem_size = <0x00800000 0x1980000 0x100000 0x100000 0x800000>; + logo_addr = "0x7f800000"; + mem_alloc = <1>; + pxp_mode = <0>; /** 0:normal mode 1:pxp mode */ +}; + +&pwm_AO_cd { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + pinctrl-names="default"; + pinctrl-0=<&i2c0_master_pins2>; + clock-frequency = <400000>; + + gt9xx@5d { + compatible = "goodix,gt9xx"; + status = "disabled"; + reg = <0x5d>; + reset-gpio = <&gpio GPIOZ_9 0x00>; + irq-gpio = <&gpio GPIOZ_3 0x00>; + }; + + ftxx@38 { + compatible = "focaltech,fts"; + status = "disabled"; + reg = <0x38>; + reset-gpio = <&gpio GPIOZ_9 0x00>; + irq-gpio = <&gpio GPIOZ_3 0x00>; + x_max = <600>; + y_max = <1024>; + max-touch-number = <10>; + }; +}; + +&i2c3 { + status = "okay"; + pinctrl-names="default"; + pinctrl-0=<&i2c3_master_pins2>; + clock-frequency = <100000>; /* default 100k */ + + /* for ref board */ + ad82584f_62: ad82584f_62@62 { + compatible = "ESMT, ad82584f"; + #sound-dai-cells = <0>; + reg = <0x31>; + status = "okay"; + reset_pin = <&gpio GPIOA_5 0>; + }; + + tlv320adc3101_32: tlv320adc3101_32@32 { + compatible = "ti,tlv320adc3101"; + #sound-dai-cells = <0>; + reg = <0x19>; + differential_pair = <1>; + status = "okay"; + }; + + tas5707_36: tas5707_36@36 { + compatible = "ti,tas5707"; + #sound-dai-cells = <0>; + reg = <0x1b>; + status = "disabled"; + reset_pin = <&gpio GPIOA_5 0>; + }; + + bl_extern_i2c { + compatible = "amlogic, bl_extern_i2c"; + status = "disabled"; + reg = <0x2c>; /*reg_address for lp8556*/ + dev_name = "lp8556"; + }; + lcd_extern_i2c { + compatible = "amlogic, lcd_i2c_T5800Q"; + status = "disabled"; + reg = <0x1c>; /*reg_address for i2c_T5800Q*/ + dev_name = "i2c_T5800Q"; + }; +}; + +&audiobus { + aml_tdma: tdma { + compatible = "amlogic, g12a-snd-tdma"; + #sound-dai-cells = <0>; + dai-tdm-lane-slot-mask-in = <0 1>; + dai-tdm-oe-lane-slot-mask-out = <1 0>; + dai-tdm-clk-sel = <0>; + clocks = <&clkaudio CLKID_AUDIO_MCLK_A + &clkc CLKID_MPLL0>; + clock-names = "mclk", "clk_srcpll"; + pinctrl-names = "tdm_pins"; + pinctrl-0 = <&tdmout_a &tdmin_a>; + }; + + aml_tdmb: tdmb { + compatible = "amlogic, g12a-snd-tdmb"; + #sound-dai-cells = <0>; + dai-tdm-lane-slot-mask-in = <0 1 0 0>; + dai-tdm-lane-slot-mask-out = <1 0 0 0>; + dai-tdm-clk-sel = <1>; + clocks = <&clkaudio CLKID_AUDIO_MCLK_B + &clkc CLKID_MPLL1 + &clkc CLKID_MPLL0>; + clock-names = "mclk", "clk_srcpll", "samesource_sysclk"; + pinctrl-names = "tdm_pins"; + pinctrl-0 = <&tdmb_mclk &tdmout_b &tdmin_b>; + /* + * 0: tdmout_a; + * 1: tdmout_b; + * 2: tdmout_c; + * 3: spdifout; + * 4: spdifout_b; + */ + samesource_sel = <3>; + }; + + aml_tdmc: tdmc { + compatible = "amlogic, g12a-snd-tdmc"; + #sound-dai-cells = <0>; + dai-tdm-lane-slot-mask-in = <1 0 0 0>; + #dai-tdm-lane-slot-mask-out = <1 0 1 1>; + #dai-tdm-lane-oe-slot-mask-in = <0 0 0 0>; + #dai-tdm-lane-oe-slot-mask-out = <1 0 0 0>; + dai-tdm-clk-sel = <2>; + clocks = <&clkaudio CLKID_AUDIO_MCLK_C + &clkc CLKID_MPLL2>; + clock-names = "mclk", "clk_srcpll"; + pinctrl-names = "tdm_pins"; + pinctrl-0 = <&tdmc_mclk &tdmout_c &tdmin_c>; + }; + + + aml_spdif: spdif { + compatible = "amlogic, g12a-snd-spdif-a"; + #sound-dai-cells = <0>; + clocks = <&clkc CLKID_MPLL0 + &clkc CLKID_FCLK_DIV4 + &clkaudio CLKID_AUDIO_SPDIFIN + &clkaudio CLKID_AUDIO_SPDIFOUT + &clkaudio CLKID_AUDIO_SPDIFIN_CTRL + &clkaudio CLKID_AUDIO_SPDIFOUT_CTRL>; + clock-names = "sysclk", "fixed_clk", "gate_spdifin", + "gate_spdifout", "clk_spdifin", "clk_spdifout"; + interrupts = + ; + + interrupt-names = "irq_spdifin"; + pinctrl-names = "spdif_pins"; + pinctrl-0 = <&spdifout &spdifin>; + status = "okay"; + }; + aml_spdif_b: spdif_b { + compatible = "amlogic, g12a-snd-spdif-b"; + #sound-dai-cells = <0>; + clocks = <&clkc CLKID_MPLL0 /*CLKID_HIFI_PLL*/ + &clkaudio CLKID_AUDIO_SPDIFOUTB + &clkaudio CLKID_AUDIO_SPDIFOUTB_CTRL>; + clock-names = "sysclk", + "gate_spdifout", "clk_spdifout"; + status = "okay"; + }; + aml_pdm: pdm { + compatible = "amlogic, g12a-snd-pdm"; + #sound-dai-cells = <0>; + clocks = <&clkaudio CLKID_AUDIO_PDM + &clkc CLKID_FCLK_DIV3 + &clkc CLKID_MPLL3 + &clkaudio CLKID_AUDIO_PDMIN0 + &clkaudio CLKID_AUDIO_PDMIN1>; + clock-names = "gate", + "sysclk_srcpll", + "dclk_srcpll", + "pdm_dclk", + "pdm_sysclk"; + pinctrl-names = "pdm_pins"; + pinctrl-0 = <&pdmin>; + filter_mode = <1>; /* mode 0~4, defalut:1 */ + status = "okay"; + }; + aml_loopback: loopback { + compatible = "amlogic, snd-loopback"; + /* + * 0: out rate = in data rate; + * 1: out rate = loopback data rate; + */ + lb_mode = <0>; + + /* datain src + * 0: tdmin_a; + * 1: tdmin_b; + * 2: tdmin_c; + * 3: spdifin; + * 4: pdmin; + */ + datain_src = <4>; + datain_chnum = <8>; + datain_chmask = <0x3f>; + + /* tdmin_lb src + * 0: tdmoutA + * 1: tdmoutB + * 2: tdmoutC + * 3: PAD_tdminA + * 4: PAD_tdminB + * 5: PAD_tdminC + */ + datalb_src = <2>; + datalb_chnum = <8>; + datalb_chmask = <0x3>; + + status = "okay"; + }; + + audioresample: resample { + compatible = "amlogic, g12a-resample"; + clocks = <&clkc CLKID_MPLL3 + &clkaudio CLKID_AUDIO_MCLK_F + &clkaudio CLKID_AUDIO_RESAMPLE_CTRL>; + clock-names = "resample_pll", "resample_src", "resample_clk"; + /*same with toddr_src + * TDMIN_A, 0 + * TDMIN_B, 1 + * TDMIN_C, 2 + * SPDIFIN, 3 + * PDMIN, 4 + * NONE, + * TDMIN_LB, 6 + * LOOPBACK, 7 + */ + resample_module = <4>; + status = "okay"; + }; + aml_pwrdet: pwrdet { + compatible = "amlogic, g12a-power-detect"; + + interrupts = ; + interrupt-names = "pwrdet_irq"; + + /* pwrdet source sel + * 7: loopback; + * 6: tdmin_lb; + * 5: reserved; + * 4: pdmin; + * 3: spdifin; + * 2: tdmin_c; + * 1: tdmin_b; + * 0: tdmin_a; + */ + pwrdet_src = <4>; + + hi_th = <0x70000>; + lo_th = <0x16000>; + + status = "okay"; + }; +}; /* end of audiobus */ + +&pinctrl_periphs { + tdmout_a: tdmout_a { + mux { /* GPIOX_11, GPIOX_10, GPIOX_9 */ + groups = "tdma_sclk", + "tdma_fs", + "tdma_dout0"; + function = "tdma_out"; + }; + }; + + tdmin_a: tdmin_a { + mux { /* GPIOX_8 */ + groups = "tdma_din1"; + function = "tdma_in"; + }; + }; + + tdmb_mclk: tdmb_mclk { + mux { + groups = "mclk0_a"; + function = "mclk0"; + drive-strength = <2>; + }; + }; + tdmout_b: tdmout_b { + mux { /* GPIOA_1, GPIOA_2, GPIOA_3 */ + groups = "tdmb_sclk", + "tdmb_fs", + "tdmb_dout0"; + function = "tdmb_out"; + drive-strength = <2>; + }; + }; + + tdmin_b:tdmin_b { + mux { /* GPIOA_4 */ + groups = "tdmb_din1" + /*,"tdmb_slv_sclk", "tdmb_slv_fs"*/; + function = "tdmb_in"; + drive-strength = <2>; + }; + }; + + tdmc_mclk: tdmc_mclk { + mux { /* GPIOA_11 */ + groups = "mclk1_a"; + function = "mclk1"; + }; + }; + + tdmout_c:tdmout_c { + mux { /* GPIOA_12, GPIOA_13, GPIOA_8, GPIOA_7*/ + groups = "tdmc_sclk_a", + "tdmc_fs_a", + "tdmc_dout0_a" + /*, "tdmc_dout2", + * "tdmc_dout3" + */; + function = "tdmc_out"; + }; + }; + + tdmin_c:tdmin_c { + mux { /* GPIOA_10 */ + groups = "tdmc_din0_a"; + function = "tdmc_in"; + }; + }; + + spdifin: spdifin { + mux {/* GPIOH_5 */ + groups = "spdif_in_h"; + function = "spdif_in"; + }; + }; + + /* GPIOH_4 */ + /* + * spdifout: spdifout { + * mux { + * groups = "spdif_out_h"; + * function = "spdif_out"; + * }; + *}; + */ + + pdmin: pdmin { + mux { /* gpioa_5, gpioa_6, gpioa_7, gpioa_8, gpioa_9*/ + groups = "pdm_din0_a", + /*"pdm_din1_a",*/ + "pdm_din2_a", + /*"pdm_din3_a",*/ + "pdm_dclk_a"; + function = "pdm"; + }; + }; + + bl_pwm_off_pins:bl_pwm_off_pin { + mux { + pins = "GPIOH_5"; + function = "gpio_periphs"; + output-high; + }; + }; + + +}; /* end of pinctrl_periphs */ +&pinctrl_aobus { + spdifout: spdifout { + mux { /* gpiao_10 */ + groups = "spdif_out_ao"; + function = "spdif_out_ao"; + }; + }; +}; /* end of pinctrl_aobus */ + +&audio_data { + status = "okay"; +}; + +/* Audio Related End */ + +&pwm_ef { + status = "okay"; +}; + +&dwc3 { + status = "okay"; +}; + +&usb2_phy_v2 { + status = "okay"; + portnum = <2>; +}; + +&usb3_phy_v2 { + status = "okay"; + portnum = <1>; + otg = <1>; + gpio-vbus-power = "GPIOH_6"; + gpios = <&gpio GPIOH_6 GPIO_ACTIVE_HIGH>; +}; + +&dwc2_a { + status = "okay"; + /** 0: normal, 1: otg+dwc3 host only, 2: otg+dwc3 device only*/ + controller-type = <3>; +}; +ðmac { + status = "okay"; + pinctrl-names = "internal_eth_pins"; + pinctrl-0 = <&internal_eth_pins>; + mc_val = <0x4be04>; + + internal_phy=<1>; +}; + +&uart_A { + status = "okay"; +}; + +/*if you want to use vdin just modify status to "ok"*/ +&vdin0 { + memory-region = <&vdin0_cma_reserved>; + status = "okay"; + /*vdin write mem color depth support: + *bit0:support 8bit + *bit1:support 9bit + *bit2:support 10bit + *bit3:support 12bit + *bit4:support yuv422 10bit full pack mode (from txl new add) + */ + tv_bit_mode = <0x15>; +}; +&vdin1 { + memory-region = <&vdin1_cma_reserved>; + status = "okay"; + /*vdin write mem color depth support: + *bit0:support 8bit + *bit1:support 9bit + *bit2:support 10bit + *bit3:support 12bit + */ + tv_bit_mode = <1>; +}; + + +&sd_emmc_c { + status = "okay"; + emmc { + caps = "MMC_CAP_8_BIT_DATA", + "MMC_CAP_MMC_HIGHSPEED", + "MMC_CAP_SD_HIGHSPEED", + "MMC_CAP_NONREMOVABLE", + /* "MMC_CAP_1_8V_DDR", */ + "MMC_CAP_HW_RESET", + "MMC_CAP_ERASE", + "MMC_CAP_CMD23"; + caps2 = "MMC_CAP2_HS200"; + /* "MMC_CAP2_HS400";*/ + f_min = <400000>; + f_max = <200000000>; + }; +}; + +&sd_emmc_b1 { + status = "disabled"; + sd { + caps = "MMC_CAP_4_BIT_DATA", + "MMC_CAP_MMC_HIGHSPEED", + "MMC_CAP_SD_HIGHSPEED"; + f_min = <400000>; + f_max = <50000000>; + }; +}; + +&sd_emmc_b2 { + status = "disabled"; + sd { + caps = "MMC_CAP_4_BIT_DATA", + "MMC_CAP_MMC_HIGHSPEED", + "MMC_CAP_SD_HIGHSPEED"; + f_min = <400000>; + f_max = <50000000>; + }; + + sdio { + caps = "MMC_CAP_4_BIT_DATA", + "MMC_CAP_MMC_HIGHSPEED", + "MMC_CAP_SD_HIGHSPEED", + "MMC_CAP_NONREMOVABLE", + "MMC_CAP_UHS_SDR12", + "MMC_CAP_UHS_SDR25", + "MMC_CAP_UHS_SDR50", + "MMC_CAP_UHS_SDR104", + "MMC_PM_KEEP_POWER", + "MMC_CAP_SDIO_IRQ"; + + f_min = <400000>; + f_max = <200000000>; + }; +}; + +&sd_emmc_a { + status = "disabled"; + sdio { + caps = "MMC_CAP_4_BIT_DATA", + "MMC_CAP_MMC_HIGHSPEED", + "MMC_CAP_SD_HIGHSPEED", + "MMC_CAP_NONREMOVABLE", + "MMC_CAP_UHS_SDR12", + "MMC_CAP_UHS_SDR25", + "MMC_CAP_UHS_SDR50", + "MMC_CAP_UHS_SDR104", + "MMC_PM_KEEP_POWER", + "MMC_CAP_SDIO_IRQ"; + f_min = <400000>; + f_max = <200000000>; + }; +}; + +&nand { + status = "disabled"; + plat-names = "bootloader","nandnormal"; + plat-num = <2>; + plat-part-0 = <&bootloader>; + plat-part-1 = <&nandnormal>; + bootloader: bootloader{ + enable_pad ="ce0"; + busy_pad = "rb0"; + timming_mode = "mode5"; + bch_mode = "bch8_1k"; + t_rea = <20>; + t_rhoh = <15>; + chip_num = <1>; + part_num = <0>; + rb_detect = <1>; + }; + nandnormal: nandnormal{ + enable_pad ="ce0"; + busy_pad = "rb0"; + timming_mode = "mode5"; + bch_mode = "bch8_1k"; + plane_mode = "twoplane"; + t_rea = <20>; + t_rhoh = <15>; + chip_num = <2>; + part_num = <3>; + partition = <&nand_partitions>; + rb_detect = <1>; + }; + nand_partitions:nand_partition{ + /* + * if bl_mode is 1, tpl size was generate by + * fip_copies * fip_size which + * will not skip bad when calculating + * the partition size; + * + * if bl_mode is 0, + * tpl partition must be comment out. + */ + tpl{ + offset=<0x0 0x0>; + size=<0x0 0x0>; + }; + logo{ + offset=<0x0 0x0>; + size=<0x0 0x200000>; + }; + recovery{ + offset=<0x0 0x0>; + size=<0x0 0x1000000>; + }; + boot{ + offset=<0x0 0x0>; + size=<0x0 0x1000000>; + }; + system{ + offset=<0x0 0x0>; + size=<0x0 0x4000000>; + }; + data{ + offset=<0xffffffff 0xffffffff>; + size=<0x0 0x0>; + }; + }; +}; + +&pcie_A { + reset-gpio = <&gpio GPIOX_7 GPIO_ACTIVE_HIGH>; + status = "disable"; +}; + +&meson_cooldev { + status = "disbaled"; +}; + +&defendkey { + status = "okay"; +}; + diff --git a/arch/arm64/boot/dts/amlogic/g12a_s905x2_u211.dts b/arch/arm64/boot/dts/amlogic/g12a_s905x2_u211.dts index b252a14d4be8..6d415887c84e 100644 --- a/arch/arm64/boot/dts/amlogic/g12a_s905x2_u211.dts +++ b/arch/arm64/boot/dts/amlogic/g12a_s905x2_u211.dts @@ -151,14 +151,14 @@ }; }; - dummy-battery { + amlogic_battery:dummy-battery { compatible = "amlogic, dummy-battery"; - status = "okay"; + status = "disabled"; }; - dummy-charger { + amlogic_charger:dummy-charger { compatible = "amlogic, dummy-charger"; - status = "okay"; + status = "disabled"; }; gpioleds { diff --git a/arch/arm64/boot/dts/amlogic/g12a_s905x2_u211_1g.dts b/arch/arm64/boot/dts/amlogic/g12a_s905x2_u211_1g.dts index 5e9028e87807..e0564dd2943f 100644 --- a/arch/arm64/boot/dts/amlogic/g12a_s905x2_u211_1g.dts +++ b/arch/arm64/boot/dts/amlogic/g12a_s905x2_u211_1g.dts @@ -152,14 +152,14 @@ }; }; - dummy-battery { + amlogic_battery:dummy-battery { compatible = "amlogic, dummy-battery"; - status = "okay"; + status = "disabled"; }; - dummy-charger { + amlogc_charger:dummy-charger { compatible = "amlogic, dummy-charger"; - status = "okay"; + status = "disabled"; }; gpioleds { diff --git a/arch/arm64/boot/dts/amlogic/g12a_s905x2_u211_buildroot.dts b/arch/arm64/boot/dts/amlogic/g12a_s905x2_u211_buildroot.dts index 6a5b13c4e392..84330840e39d 100644 --- a/arch/arm64/boot/dts/amlogic/g12a_s905x2_u211_buildroot.dts +++ b/arch/arm64/boot/dts/amlogic/g12a_s905x2_u211_buildroot.dts @@ -761,23 +761,23 @@ }; opp05 { opp-hz = /bits/ 64 <1200000000>; - opp-microvolt = <731000>; + opp-microvolt = <761000>; }; opp06 { opp-hz = /bits/ 64 <1398000000>; - opp-microvolt = <761000>; + opp-microvolt = <791000>; }; opp07 { opp-hz = /bits/ 64 <1512000000>; - opp-microvolt = <791000>; + opp-microvolt = <831000>; }; opp08 { opp-hz = /bits/ 64 <1608000000>; - opp-microvolt = <831000>; + opp-microvolt = <871000>; }; opp09 { opp-hz = /bits/ 64 <1704000000>; - opp-microvolt = <861000>; + opp-microvolt = <921000>; }; opp10 { opp-hz = /bits/ 64 <1800000000>; diff --git a/arch/arm64/boot/dts/amlogic/g12a_s905x2_u212.dts b/arch/arm64/boot/dts/amlogic/g12a_s905x2_u212.dts index 5204c3568269..bcd08a225109 100644 --- a/arch/arm64/boot/dts/amlogic/g12a_s905x2_u212.dts +++ b/arch/arm64/boot/dts/amlogic/g12a_s905x2_u212.dts @@ -151,14 +151,14 @@ }; }; - dummy-battery { + amlogic_battery:dummy-battery { compatible = "amlogic, dummy-battery"; - status = "okay"; + status = "disabled"; }; - dummy-charger { + amlogic_charger:dummy-charger { compatible = "amlogic, dummy-charger"; - status = "okay"; + status = "disabled"; }; gpioleds { diff --git a/arch/arm64/boot/dts/amlogic/g12a_s905x2_u212_1g.dts b/arch/arm64/boot/dts/amlogic/g12a_s905x2_u212_1g.dts index f528968ed8b6..6f414af19619 100644 --- a/arch/arm64/boot/dts/amlogic/g12a_s905x2_u212_1g.dts +++ b/arch/arm64/boot/dts/amlogic/g12a_s905x2_u212_1g.dts @@ -152,14 +152,14 @@ }; }; - dummy-battery { + amlogic_battery:dummy-battery { compatible = "amlogic, dummy-battery"; - status = "okay"; + status = "disabled"; }; - dummy-charger { + amlogic_charger:dummy-charger { compatible = "amlogic, dummy-charger"; - status = "okay"; + status = "disabled"; }; gpioleds { diff --git a/arch/arm64/boot/dts/amlogic/g12a_s905x2_u212_buildroot.dts b/arch/arm64/boot/dts/amlogic/g12a_s905x2_u212_buildroot.dts index a06367072f85..c78baf374f49 100644 --- a/arch/arm64/boot/dts/amlogic/g12a_s905x2_u212_buildroot.dts +++ b/arch/arm64/boot/dts/amlogic/g12a_s905x2_u212_buildroot.dts @@ -761,23 +761,23 @@ }; opp05 { opp-hz = /bits/ 64 <1200000000>; - opp-microvolt = <731000>; + opp-microvolt = <761000>; }; opp06 { opp-hz = /bits/ 64 <1398000000>; - opp-microvolt = <761000>; + opp-microvolt = <791000>; }; opp07 { opp-hz = /bits/ 64 <1512000000>; - opp-microvolt = <791000>; + opp-microvolt = <831000>; }; opp08 { opp-hz = /bits/ 64 <1608000000>; - opp-microvolt = <831000>; + opp-microvolt = <871000>; }; opp09 { opp-hz = /bits/ 64 <1704000000>; - opp-microvolt = <861000>; + opp-microvolt = <921000>; }; opp10 { opp-hz = /bits/ 64 <1800000000>; diff --git a/arch/arm64/boot/dts/amlogic/g12a_s905y2_u220.dts b/arch/arm64/boot/dts/amlogic/g12a_s905y2_u220.dts index b3037bd9df7d..13f8bc2ce316 100644 --- a/arch/arm64/boot/dts/amlogic/g12a_s905y2_u220.dts +++ b/arch/arm64/boot/dts/amlogic/g12a_s905y2_u220.dts @@ -189,7 +189,7 @@ bt-dev{ compatible = "amlogic, bt-dev"; dev_name = "bt-dev"; - status = "okay"; + status = "disable"; gpio_reset = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>; gpio_hostwake = <&gpio GPIOX_19 GPIO_ACTIVE_HIGH>; }; @@ -197,7 +197,7 @@ wifi{ compatible = "amlogic, aml_wifi"; dev_name = "aml_wifi"; - status = "okay"; + status = "disable"; interrupt_pin = <&gpio GPIOX_7 GPIO_ACTIVE_HIGH>; irq_trigger_type = "GPIO_IRQ_LOW"; power_on_pin = <&gpio GPIOX_6 GPIO_ACTIVE_HIGH>; @@ -1222,7 +1222,7 @@ }; &sd_emmc_a { - status = "okay"; + status = "disabled"; sdio { caps = "MMC_CAP_4_BIT_DATA", "MMC_CAP_MMC_HIGHSPEED", diff --git a/arch/arm64/boot/dts/amlogic/g12a_s905y2_u221.dts b/arch/arm64/boot/dts/amlogic/g12a_s905y2_u221.dts index a4fbc61c8a3c..270c6b9e540d 100644 --- a/arch/arm64/boot/dts/amlogic/g12a_s905y2_u221.dts +++ b/arch/arm64/boot/dts/amlogic/g12a_s905y2_u221.dts @@ -651,23 +651,23 @@ }; opp05 { opp-hz = /bits/ 64 <1200000000>; - opp-microvolt = <731000>; + opp-microvolt = <761000>; }; opp06 { opp-hz = /bits/ 64 <1398000000>; - opp-microvolt = <761000>; + opp-microvolt = <791000>; }; opp07 { opp-hz = /bits/ 64 <1512000000>; - opp-microvolt = <791000>; + opp-microvolt = <831000>; }; opp08 { opp-hz = /bits/ 64 <1608000000>; - opp-microvolt = <831000>; + opp-microvolt = <871000>; }; opp09 { opp-hz = /bits/ 64 <1704000000>; - opp-microvolt = <861000>; + opp-microvolt = <921000>; }; opp10 { opp-hz = /bits/ 64 <1800000000>; diff --git a/arch/arm64/boot/dts/amlogic/g12b_a311d_skt.dts b/arch/arm64/boot/dts/amlogic/g12b_a311d_skt.dts index fb4e32ce0e5f..4786033940b4 100644 --- a/arch/arm64/boot/dts/amlogic/g12b_a311d_skt.dts +++ b/arch/arm64/boot/dts/amlogic/g12b_a311d_skt.dts @@ -68,6 +68,7 @@ size = <0x0 0x400000>; alignment = <0x0 0x400000>; alloc-ranges = <0x0 0x05000000 0x0 0x400000>; + clear-map; }; secos_reserved:linux,secos { @@ -745,6 +746,8 @@ clocks = <&clkc CLKID_24M>; clock-names = "g12a_24m"; reset = <&gpio GPIOZ_12 GPIO_ACTIVE_HIGH>; + ir_cut_gpio = <&gpio GPIOZ_11 GPIO_ACTIVE_HIGH + &gpio GPIOZ_7 GPIO_ACTIVE_HIGH>; }; iq: iq { @@ -803,7 +806,7 @@ display_size_default = <1920 1080 1920 2160 32>; mem_size = <0x00800000 0x1980000 0x100000 0x100000 0x800000>; logo_addr = "0x7f800000"; - mem_alloc = <0>; + mem_alloc = <1>; pxp_mode = <0>; /** 0:normal mode 1:pxp mode */ }; diff --git a/arch/arm64/boot/dts/amlogic/g12b_a311d_w400.dts b/arch/arm64/boot/dts/amlogic/g12b_a311d_w400.dts index 7a6e8d3f047c..089b9bb11aa3 100644 --- a/arch/arm64/boot/dts/amlogic/g12b_a311d_w400.dts +++ b/arch/arm64/boot/dts/amlogic/g12b_a311d_w400.dts @@ -68,6 +68,7 @@ size = <0x0 0x400000>; alignment = <0x0 0x400000>; alloc-ranges = <0x0 0x05000000 0x0 0x400000>; + clear-map; }; secos_reserved:linux,secos { @@ -121,6 +122,7 @@ size = <0x0 0x13400000>; alignment = <0x0 0x400000>; linux,contiguous-region; + clear-map; }; /* codec shared reserved */ codec_mm_reserved:linux,codec_mm_reserved { diff --git a/arch/arm64/boot/dts/amlogic/g12b_a311d_w400_buildroot.dts b/arch/arm64/boot/dts/amlogic/g12b_a311d_w400_buildroot.dts index 826673e91429..68f596fea553 100644 --- a/arch/arm64/boot/dts/amlogic/g12b_a311d_w400_buildroot.dts +++ b/arch/arm64/boot/dts/amlogic/g12b_a311d_w400_buildroot.dts @@ -67,6 +67,7 @@ size = <0x0 0x400000>; alignment = <0x0 0x400000>; alloc-ranges = <0x0 0x05000000 0x0 0x400000>; + clear-map; }; secos_reserved:linux,secos { @@ -149,8 +150,41 @@ size = <0x0 0x04000000>; alignment = <0x0 0x400000>; }; - }; + galcore_reserved:linux,galcore { + compatible = "shared-dma-pool"; + reusable; + size = <0x0 0x1000000>; + alignment = <0x0 0x400000>; + linux,contiguous-region; + }; + isp_cma_reserved:linux,isp_cma { + compatible = "shared-dma-pool"; + reusable; + status = "okay"; + size = <0x0 0x1f000000>; + alignment = <0x0 0x400000>; + }; + + adapt_cma_reserved:linux,adapt_cma { + compatible = "shared-dma-pool"; + reusable; + status = "okay"; + size = <0x0 0x03000000>; + alignment = <0x0 0x400000>; + }; + gdc_cma_reserved:linux,gdc_cma { + compatible = "shared-dma-pool"; + reusable; + status = "okay"; + size = <0x0 0x04000000>; + alignment = <0x0 0x400000>; + }; + }; + galcore { + status = "okay"; + memory-region = <&galcore_reserved>; + }; gpioleds { compatible = "gpio-leds"; status = "okay"; @@ -768,9 +802,55 @@ status = "okay"; }; + sensor: sensor { + compatible = "soc, sensor"; + status = "okay"; + sensor-name = "imx290"; /*imx290;os08a10;imx227*/ + pinctrl-names="default"; + pinctrl-0=<&clk12_24_z_pins>; + clocks = <&clkc CLKID_24M>; + clock-names = "g12a_24m"; + reset = <&gpio GPIOZ_12 GPIO_ACTIVE_HIGH>; + }; + iq: iq { + compatible = "soc, iq"; + status = "okay"; + sensor-name = "imx290"; /*imx290;os08a10;imx227*/ + }; }; /* end of / */ +&i2c2 { + status = "okay"; + pinctrl-names="default"; + pinctrl-0=<&i2c2_master_pins2>; + clock-frequency = <100000>; /* default 100k */ + sensor-i2c@6c { + compatible = "arm, i2c-sensor"; + reg = <0x6c>; + reg-names = "i2c-sensor"; + slave-addr = <0x6c>; + reg-type = <2>; + reg-data-type = <1>; + link-device = <&phycsi>; + }; +}; + +&isp { + status = "okay"; + memory-region = <&isp_cma_reserved>; +}; + +&adapter { + status = "okay"; + memory-region = <&adapt_cma_reserved>; +}; + +&gdc { + status = "okay"; + memory-region = <&gdc_cma_reserved>; +}; + &meson_fb { status = "okay"; display_size_default = <1920 1080 1920 2160 32>; @@ -792,6 +872,24 @@ status = "okay"; }; +&i2c0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_master_pins2>; + clock-frequency = <400000>; + + touchscreen@38 { + compatible = "focaltech,fts"; + status = "disabled"; + reg = <0x38>; + reset-gpio = <&gpio GPIOZ_9 GPIO_ACTIVE_HIGH>; + irq-gpio = <&gpio GPIOZ_3 GPIO_ACTIVE_HIGH>; + x_max = <720>; + y_max = <1280>; + max-touch-number = <10>; + }; +}; + &i2c3 { status = "okay"; pinctrl-names="default"; @@ -1064,6 +1162,14 @@ }; }; + clk12_24_z_pins:clk12_24_z_pins { + mux { + groups = "clk12_24_z"; + function = "clk12_24_ee"; + drive-strength = <3>; + }; + }; + tdmout_c:tdmout_c { mux { /* GPIOA_12, GPIOA_13, GPIOA_8, GPIOA_7*/ groups = "tdmc_sclk_a", @@ -1300,8 +1406,10 @@ }; ðmac { status = "okay"; +/* //conflict with isp i2c pinctrl-names = "internal_eth_pins"; pinctrl-0 = <&internal_eth_pins>; +*/ mc_val = <0x4be04>; internal_phy=<1>; @@ -1319,3 +1427,10 @@ &saradc { status = "okay"; }; + +&spicc1 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&spicc1_pins>; + cs-gpios = <&gpio GPIOH_6 0>; +}; diff --git a/arch/arm64/boot/dts/amlogic/g12b_a311d_w400_buildroot_vccktest.dts b/arch/arm64/boot/dts/amlogic/g12b_a311d_w400_buildroot_vccktest.dts new file mode 100644 index 000000000000..e2bc49b9e71b --- /dev/null +++ b/arch/arm64/boot/dts/amlogic/g12b_a311d_w400_buildroot_vccktest.dts @@ -0,0 +1,1334 @@ +/* + * arch/arm64/boot/dts/amlogic/g12b_a311d_w400_buildroot.dts + * + * Copyright (C) 2017 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +/dts-v1/; + +#include "mesong12b.dtsi" +#include "mesong12b_skt-panel.dtsi" + +/ { + model = "Amlogic"; + compatible = "amlogic, g12b"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + serial0 = &uart_AO; + serial1 = &uart_A; + serial2 = &uart_B; + serial3 = &uart_C; + serial4 = &uart_AO_B; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c_AO; + tsensor0 = &p_tsensor; + tsensor1 = &d_tsensor; + }; + + memory@00000000 { + device_type = "memory"; + linux,usable-memory = <0x0 0x100000 0x0 0x7ff00000>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + /* global autoconfigured region for contiguous allocations */ + ramoops@0x07400000 { + compatible = "ramoops"; + reg = <0x0 0x07400000 0x0 0x00100000>; + record-size = <0x8000>; + console-size = <0x8000>; + ftrace-size = <0x0>; + pmsg-size = <0x8000>; + }; + + secmon_reserved:linux,secmon { + compatible = "shared-dma-pool"; + reusable; + size = <0x0 0x400000>; + alignment = <0x0 0x400000>; + alloc-ranges = <0x0 0x05000000 0x0 0x400000>; + }; + + secos_reserved:linux,secos { + status = "disable"; + compatible = "amlogic, aml_secos_memory"; + reg = <0x0 0x05300000 0x0 0x2000000>; + no-map; + }; + logo_reserved:linux,meson-fb { + compatible = "shared-dma-pool"; + reusable; + size = <0x0 0x800000>; + alignment = <0x0 0x400000>; + alloc-ranges = <0x0 0x7f800000 0x0 0x800000>; + }; + ion_cma_reserved:linux,ion-dev { + compatible = "shared-dma-pool"; + reusable; + size = <0x0 0x8000000>; + alignment = <0x0 0x400000>; + }; + + //di_reserved:linux,di { + //compatible = "amlogic, di-mem"; + /* buffer_size = 3621952(yuv422 8bit) */ + /* 4179008(yuv422 10bit full pack mode) */ + /** 10x3621952=34.6M(0x23) support 8bit **/ + /** 10x4736064=45.2M(0x2e) support 12bit **/ + /** 10x4179008=40M(0x28) support 10bit **/ + //size = <0x0 0x2800000>; + //no-map; + //}; + /*di CMA pool */ + di_cma_reserved:linux,di_cma { + compatible = "shared-dma-pool"; + reusable; + /* buffer_size = 3621952(yuv422 8bit) + * | 4736064(yuv422 10bit) + * | 4074560(yuv422 10bit full pack mode) + * 10x3621952=34.6M(0x23) support 8bit + * 10x4736064=45.2M(0x2e) support 12bit + * 10x4074560=40M(0x28) support 10bit + */ + size = <0x0 0x02800000>; + alignment = <0x0 0x400000>; + }; + /* POST PROCESS MANAGER */ + ppmgr_reserved:linux,ppmgr { + compatible = "shared-dma-pool"; + size = <0x0 0x0>; + }; + codec_mm_cma:linux,codec_mm_cma { + compatible = "shared-dma-pool"; + reusable; + /* ion_codec_mm max can alloc size 80M*/ + size = <0x0 0x13400000>; + alignment = <0x0 0x400000>; + linux,contiguous-region; + }; + /* codec shared reserved */ + codec_mm_reserved:linux,codec_mm_reserved { + compatible = "amlogic, codec-mm-reserved"; + size = <0x0 0x0>; + alignment = <0x0 0x100000>; + //no-map; + }; + /* vdin0 CMA pool */ + vdin0_cma_reserved:linux,vdin0_cma { + compatible = "shared-dma-pool"; + reusable; + /* 1920x1080x2x4 =16+4 M */ + size = <0x0 0x04000000>; + alignment = <0x0 0x400000>; + }; + /* vdin1 CMA pool */ + vdin1_cma_reserved:linux,vdin1_cma { + compatible = "shared-dma-pool"; + reusable; + /* 1920x1080x2x4 =16 M */ + size = <0x0 0x04000000>; + alignment = <0x0 0x400000>; + }; + }; + + gpioleds { + compatible = "gpio-leds"; + status = "okay"; + + sys_led { + label="sys_led"; + gpios=<&gpio_ao GPIOAO_11 GPIO_ACTIVE_HIGH>; + default-state ="on"; + retain-state-suspended; + linux,default-trigger="cpu0"; + }; + }; + + cvbsout { + compatible = "amlogic, cvbsout-g12b"; + dev_name = "cvbsout"; + status = "okay"; + clocks = <&clkc CLKID_VCLK2_ENCI + &clkc CLKID_VCLK2_VENCI0 + &clkc CLKID_VCLK2_VENCI1 + &clkc CLKID_DAC_CLK>; + clock-names = "venci_top_gate", + "venci_0_gate", + "venci_1_gate", + "vdac_clk_gate"; + + /* performance: reg_address, reg_value */ + /* g12b */ + performance = <0x1bf0 0x9 + 0x1b56 0x333 + 0x1b12 0x8080 + 0x1b05 0xfd + 0x1c59 0xf850 + 0xffff 0x0>; /* ending flag */ + performance_sarft = <0x1bf0 0x9 + 0x1b56 0x333 + 0x1b12 0x0 + 0x1b05 0x9 + 0x1c59 0xfc48 + 0xffff 0x0>; /* ending flag */ + }; + + bt-dev{ + compatible = "amlogic, bt-dev"; + dev_name = "bt-dev"; + status = "okay"; + gpio_reset = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>; + gpio_hostwake = <&gpio GPIOX_19 GPIO_ACTIVE_HIGH>; + }; + + wifi{ + compatible = "amlogic, aml_wifi"; + dev_name = "aml_wifi"; + status = "okay"; + interrupt_pin = <&gpio GPIOX_7 GPIO_ACTIVE_HIGH>; + irq_trigger_type = "GPIO_IRQ_LOW"; + power_on_pin = <&gpio GPIOX_6 GPIO_ACTIVE_HIGH>; + dhd_static_buf; //if use bcm wifi, config dhd_static_buf + pinctrl-names = "default"; + pinctrl-0 = <&pwm_e_pins>; + pwm_config = <&wifi_pwm_conf>; + }; + + wifi_pwm_conf:wifi_pwm_conf{ + pwm_channel1_conf { + pwms = <&pwm_ef MESON_PWM_0 30040 0>; + duty-cycle = <15020>; + times = <10>; + }; + pwm_channel2_conf { + pwms = <&pwm_ef MESON_PWM_2 30030 0>; + duty-cycle = <15015>; + times = <12>; + }; + }; + + codec_mm { + compatible = "amlogic, codec, mm"; + memory-region = <&codec_mm_cma &codec_mm_reserved>; + dev_name = "codec_mm"; + status = "okay"; + }; + + ppmgr { + compatible = "amlogic, ppmgr"; + memory-region = <&ppmgr_reserved>; + dev_name = "ppmgr"; + status = "okay"; + }; + + deinterlace { + compatible = "amlogic, deinterlace"; + status = "okay"; + /* 0:use reserved; 1:use cma; 2:use cma as reserved */ + flag_cma = <1>; + //memory-region = <&di_reserved>; + memory-region = <&di_cma_reserved>; + interrupts = <0 46 1 + 0 40 1>; + interrupt-names = "pre_irq", "post_irq"; + clocks = <&clkc CLKID_VPU_CLKB_TMP_COMP>, + <&clkc CLKID_VPU_CLKB_COMP>; + clock-names = "vpu_clkb_tmp_composite", + "vpu_clkb_composite"; + clock-range = <334 667>; + /* buffer-size = <3621952>;(yuv422 8bit) */ + buffer-size = <4074560>;/*yuv422 fullpack*/ + /* reserve-iomap = "true"; */ + /* if enable nr10bit, set nr10bit-support to 1 */ + post-wr-support = <1>; + nr10bit-support = <1>; + nrds-enable = <1>; + pps-enable = <1>; + }; + ionvideo { + compatible = "amlogic, ionvideo"; + dev_name = "ionvideo"; + status = "okay"; + }; + + + partitions: partitions{ + parts = <14>; + part-0 = <&logo>; + part-1 = <&recovery>; + part-2 = <&misc>; + part-3 = <&dto>; + part-4 = <&cri_data>; + part-5 = <¶m>; + part-6 = <&boot>; + part-7 = <&rsv>; + part-8 = <&tee>; + part-9 = <&vendor>; + part-10 = <&odm>; + part-11 = <&system>; + part-12 = <&cache>; + part-13 = <&data>; + + logo:logo{ + pname = "logo"; + size = <0x0 0x800000>; + mask = <1>; + }; + recovery:recovery{ + pname = "recovery"; + size = <0x0 0x1800000>; + mask = <1>; + }; + misc:misc{ + pname = "misc"; + size = <0x0 0x800000>; + mask = <1>; + }; + dto:dto{ + pname = "dto"; + size = <0x0 0x800000>; + mask = <1>; + }; + cri_data:cri_data{ + pname = "cri_data"; + size = <0x0 0x800000>; + mask = <2>; + }; + rsv:rsv{ + pname = "rsv"; + size = <0x0 0x1000000>; + mask = <1>; + }; + param:param{ + pname = "param"; + size = <0x0 0x1000000>; + mask = <2>; + }; + boot:boot{ + pname = "boot"; + size = <0x0 0x1000000>; + mask = <1>; + }; + tee:tee{ + pname = "tee"; + size = <0x0 0x2000000>; + mask = <1>; + }; + vendor:vendor{ + pname = "vendor"; + size = <0x0 0x10000000>; + mask = <1>; + }; + odm:odm{ + pname = "odm"; + size = <0x0 0x10000000>; + mask = <1>; + }; + system:system{ + pname = "system"; + size = <0x0 0x80000000>; + mask = <1>; + }; + cache:cache{ + pname = "cache"; + size = <0x0 0x46000000>; + mask = <2>; + }; + data:data{ + pname = "data"; + size = <0xffffffff 0xffffffff>; + mask = <4>; + }; + }; + + gpio_keypad { + compatible = "amlogic, gpio_keypad"; + status = "okay"; + scan_period = <20>; + key_num = <1>; + key_name = "power"; + key_code = <116>; + key-gpios = <&gpio_ao GPIOAO_3 GPIO_ACTIVE_HIGH>; + detect_mode = <0>;/*0:polling mode, 1:irq mode*/ + }; + + adc_keypad { + compatible = "amlogic, adc_keypad"; + status = "okay"; + key_name = "vol-", "vol+", "enter"; + key_num = <3>; + io-channels = <&saradc SARADC_CH2>; + io-channel-names = "key-chan-2"; + key_chan = ; + key_code = <114 115 28>; + key_val = <143 266 389>; //val=voltage/1800mV*1023 + key_tolerance = <40 40 40>; + }; + + unifykey{ + compatible = "amlogic, unifykey"; + status = "ok"; + unifykey-num = <14>; + unifykey-index-0 = <&keysn_0>; + unifykey-index-1 = <&keysn_1>; + unifykey-index-2 = <&keysn_2>; + unifykey-index-3 = <&keysn_3>; + unifykey-index-4 = <&keysn_4>; + unifykey-index-5 = <&keysn_5>; + unifykey-index-6 = <&keysn_6>; + unifykey-index-7 = <&keysn_7>; + unifykey-index-8 = <&keysn_8>; + unifykey-index-9 = <&keysn_9>; + unifykey-index-10= <&keysn_10>; + unifykey-index-11= <&keysn_11>; + unifykey-index-12= <&keysn_12>; + unifykey-index-13= <&keysn_13>; + + keysn_0: key_0{ + key-name = "usid"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_1:key_1{ + key-name = "mac"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_2:key_2{ + key-name = "hdcp"; + key-device = "secure"; + key-type = "sha1"; + key-permit = "read","write","del"; + }; + keysn_3:key_3{ + key-name = "secure_boot_set"; + key-device = "efuse"; + key-permit = "write"; + }; + keysn_4:key_4{ + key-name = "mac_bt"; + key-device = "normal"; + key-permit = "read","write","del"; + key-type = "mac"; + }; + keysn_5:key_5{ + key-name = "mac_wifi"; + key-device = "normal"; + key-permit = "read","write","del"; + key-type = "mac"; + }; + keysn_6:key_6{ + key-name = "hdcp2_tx"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_7:key_7{ + key-name = "hdcp2_rx"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_8:key_8{ + key-name = "widevinekeybox"; + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_9:key_9{ + key-name = "deviceid"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_10:key_10{ + key-name = "hdcp22_fw_private"; + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_11:key_11{ + key-name = "PlayReadykeybox25"; + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_12:key_12{ + key-name = "prpubkeybox";// PlayReady + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_13:key_13{ + key-name = "prprivkeybox";// PlayReady + key-device = "secure"; + key-permit = "read","write","del"; + }; + };//End unifykey + + amlvecm { + compatible = "amlogic, vecm"; + dev_name = "aml_vecm"; + status = "okay"; + gamma_en = <0>;/*1:enabel ;0:disable*/ + wb_en = <0>;/*1:enabel ;0:disable*/ + cm_en = <0>;/*1:enabel ;0:disable*/ + }; + amdolby_vision { + compatible = "amlogic, dolby_vision_g12a"; + dev_name = "aml_amdolby_vision_driver"; + status = "okay"; + tv_mode = <0>;/*1:enabel ;0:disable*/ + }; + + /* Audio Related start */ + pdm_codec:dummy{ + #sound-dai-cells = <0>; + compatible = "amlogic, pdm_dummy_codec"; + status = "okay"; + }; + dummy_codec:dummy{ + #sound-dai-cells = <0>; + compatible = "amlogic, aml_dummy_codec"; + status = "okay"; + }; + amlogic_codec:t9015{ + #sound-dai-cells = <0>; + compatible = "amlogic, aml_codec_T9015"; + reg = <0x0 0xFF632000 0x0 0x2000>; + is_auge_used = <1>; /* meson or auge chipset used */ + tdmout_index = <1>; + status = "okay"; + }; + audio_effect:eqdrc{ + /*eq_enable = <1>;*/ + /*drc_enable = <1>;*/ + /* + * 0:tdmout_a + * 1:tdmout_b + * 2:tdmout_c + * 3:spdifout + * 4:spdifout_b + */ + eqdrc_module = <1>; + /* max 0xf, each bit for one lane, usually one lane */ + lane_mask = <0x1>; + /* max 0xff, each bit for one channel */ + channel_mask = <0x3>; + }; + auge_sound { + compatible = "amlogic, g12a-sound-card"; + aml-audio-card,name = "AML-AUGESOUND"; + + //aml-audio-card,loopback = <&aml_loopback>; + //aml-audio-card,aux-devs = <&amlogic_codec>; + /*avout mute gpio*/ + avout_mute-gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_HIGH>; + /*for audio effect ,eqdrc */ + aml-audio-card,effect = <&audio_effect>; + + aml-audio-card,dai-link@0 { + format = "dsp_a"; + mclk-fs = <512>; + //continuous-clock; + //bitclock-inversion; + //frame-inversion; + //bitclock-master = <&tdmacodec>; + //frame-master = <&tdmacodec>; + /* suffix-name, sync with android audio hal + * what's the dai link used for + */ + suffix-name = "alsaPORT-pcm"; + tdmacpu: cpu { + sound-dai = <&aml_tdma>; + dai-tdm-slot-tx-mask = + <1 1 1 1 1 1 1 1>; + dai-tdm-slot-rx-mask = + <1 1 1 1 1 1 1 1>; + dai-tdm-slot-num = <8>; + dai-tdm-slot-width = <32>; + system-clock-frequency = <24576000>; + }; + tdmacodec: codec { + sound-dai = <&dummy_codec &dummy_codec>; + }; + }; + + aml-audio-card,dai-link@1 { + format = "i2s"; + mclk-fs = <256>; + //continuous-clock; + //bitclock-inversion; + //frame-inversion; + bitclock-master = <&aml_tdmb>; + frame-master = <&aml_tdmb>; + //bitclock-master = <&tdmbcodec>; + //frame-master = <&tdmbcodec>; + /* suffix-name, sync with android audio hal + * what's the dai link used for + */ + suffix-name = "alsaPORT-i2s"; + cpu { + sound-dai = <&aml_tdmb>; + dai-tdm-slot-tx-mask = <1 1>; + dai-tdm-slot-rx-mask = <1 1>; + dai-tdm-slot-num = <2>; + dai-tdm-slot-width = <32>; + system-clock-frequency = <12288000>; + }; + tdmbcodec: codec { + sound-dai = <&dummy_codec &dummy_codec + &amlogic_codec &ad82584f_62>; + }; + }; + + aml-audio-card,dai-link@2 { + format = "i2s"; + mclk-fs = <256>; + //continuous-clock; + //bitclock-inversion; + //frame-inversion; + bitclock-master = <&aml_tdmc>; + frame-master = <&aml_tdmc>; + /* suffix-name, sync with android audio hal + * what's the dai link used for + */ + //suffix-name = "alsaPORT-tdm"; + cpu { + sound-dai = <&aml_tdmc>; + dai-tdm-slot-tx-mask = <1 1>; + dai-tdm-slot-rx-mask = <1 1>; + dai-tdm-slot-num = <2>; + dai-tdm-slot-width = <32>; + system-clock-frequency = <12288000>; + }; + codec { + sound-dai = <&dummy_codec &dummy_codec>; + }; + }; + + aml-audio-card,dai-link@3 { + mclk-fs = <64>; + /* suffix-name, sync with android audio hal + * what's the dai link used for + */ + suffix-name = "alsaPORT-pdm"; + cpu { + sound-dai = <&aml_pdm>; + }; + codec { + sound-dai = <&pdm_codec>; + }; + }; + + aml-audio-card,dai-link@4 { + mclk-fs = <128>; + /* suffix-name, sync with android audio hal + * what's the dai link used for + */ + suffix-name = "alsaPORT-spdif"; + cpu { + sound-dai = <&aml_spdif>; + system-clock-frequency = <6144000>; + }; + codec { + sound-dai = <&dummy_codec>; + }; + }; + }; + audiolocker: locker { + compatible = "amlogic, audiolocker"; + clocks = <&clkaudio CLKID_AUDIO_LOCKER_OUT + &clkaudio CLKID_AUDIO_LOCKER_IN + &clkaudio CLKID_AUDIO_MCLK_D + &clkaudio CLKID_AUDIO_MCLK_E + &clkc CLKID_MPLL1 + &clkc CLKID_MPLL2>; + clock-names = "lock_out", "lock_in", "out_src", + "in_src", "out_calc", "in_ref"; + interrupts = ; + interrupt-names = "irq"; + frequency = <49000000>; /* pll */ + dividor = <49>; /* locker's parent */ + status = "okay"; + }; + /* Audio Related end */ + + cpu_opp_table0: cpu_opp_table0 { + compatible = "operating-points-v2"; + opp-shared; + + opp00 { + opp-hz = /bits/ 64 <100000000>; + opp-microvolt = <731000>; + }; + opp01 { + opp-hz = /bits/ 64 <250000000>; + opp-microvolt = <731000>; + }; + opp02 { + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <731000>; + }; + opp03 { + opp-hz = /bits/ 64 <667000000>; + opp-microvolt = <731000>; + }; + opp04 { + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <731000>; + }; + opp05 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <731000>; + }; + opp06 { + opp-hz = /bits/ 64 <1398000000>; + opp-microvolt = <761000>; + }; + opp07 { + opp-hz = /bits/ 64 <1512000000>; + opp-microvolt = <791000>; + }; + opp08 { + opp-hz = /bits/ 64 <1608000000>; + opp-microvolt = <831000>; + }; + opp09 { + opp-hz = /bits/ 64 <1704000000>; + opp-microvolt = <861000>; + }; + opp10 { + opp-hz = /bits/ 64 <1896000000>; + opp-microvolt = <981000>; + }; + opp11 { + opp-hz = /bits/ 64 <2016000000>; + opp-microvolt = <1011000>; + }; + opp12 { + opp-hz = /bits/ 64 <2100000000>; + opp-microvolt = <1011000>; + }; + }; + + cpu_opp_table1: cpu_opp_table1 { + compatible = "operating-points-v2"; + opp-shared; + + opp00 { + opp-hz = /bits/ 64 <100000000>; + opp-microvolt = <751000>; + }; + opp01 { + opp-hz = /bits/ 64 <250000000>; + opp-microvolt = <751000>; + }; + opp02 { + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <751000>; + }; + opp03 { + opp-hz = /bits/ 64 <667000000>; + opp-microvolt = <751000>; + }; + opp04 { + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <771000>; + }; + opp05 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <771000>; + }; + opp06 { + opp-hz = /bits/ 64 <1398000000>; + opp-microvolt = <791000>; + }; + opp07 { + opp-hz = /bits/ 64 <1512000000>; + opp-microvolt = <821000>; + }; + opp08 { + opp-hz = /bits/ 64 <1608000000>; + opp-microvolt = <861000>; + }; + opp09 { + opp-hz = /bits/ 64 <1704000000>; + opp-microvolt = <891000>; + }; + opp10 { + opp-hz = /bits/ 64 <1800000000>; + opp-microvolt = <1011000>; + }; + opp11 { + opp-hz = /bits/ 64 <1908000000>; + opp-microvolt = <1011000>; + }; + opp12 { + opp-hz = /bits/ 64 <2016000000>; + opp-microvolt = <1011000>; + }; + }; + + cpufreq-meson { + compatible = "amlogic, cpufreq-meson"; + status = "okay"; + }; + + +}; /* end of / */ + +&meson_fb { + status = "okay"; + display_size_default = <1920 1080 1920 2160 32>; + mem_size = <0x00800000 0x1980000 0x100000 0x100000 0x800000>; + logo_addr = "0x7f800000"; + mem_alloc = <1>; + pxp_mode = <0>; /** 0:normal mode 1:pxp mode */ +}; + +&pwm_ab { + status = "okay"; + }; + +&pwm_ef { + status = "okay"; + }; + +&pwm_AO_cd { + status = "okay"; + }; + +&i2c3 { + status = "okay"; + pinctrl-names="default"; + pinctrl-0=<&i2c3_master_pins2>; + clock-frequency = <100000>; /* default 100k */ + + /* for ref board */ + ad82584f_62: ad82584f_62@62 { + compatible = "ESMT, ad82584f"; + #sound-dai-cells = <0>; + reg = <0x31>; + status = "okay"; + reset_pin = <&gpio GPIOA_5 0>; + }; + + tlv320adc3101_32: tlv320adc3101_32@32 { + compatible = "ti,tlv320adc3101"; + #sound-dai-cells = <0>; + reg = <0x19>; + differential_pair = <1>; + status = "disabled"; + }; +}; + +&audiobus { + aml_tdma: tdma { + compatible = "amlogic, g12a-snd-tdma"; + #sound-dai-cells = <0>; + dai-tdm-lane-slot-mask-in = <0 1>; + dai-tdm-oe-lane-slot-mask-out = <1 0>; + dai-tdm-clk-sel = <0>; + clocks = <&clkaudio CLKID_AUDIO_MCLK_A + &clkc CLKID_MPLL0>; + clock-names = "mclk", "clk_srcpll"; + pinctrl-names = "tdm_pins"; + pinctrl-0 = <&tdmout_a &tdmin_a>; + }; + + aml_tdmb: tdmb { + compatible = "amlogic, g12a-snd-tdmb"; + #sound-dai-cells = <0>; + dai-tdm-lane-slot-mask-in = <0 1 0 0>; + dai-tdm-lane-slot-mask-out = <1 0 0 0>; + dai-tdm-clk-sel = <1>; + clocks = <&clkaudio CLKID_AUDIO_MCLK_B + &clkc CLKID_MPLL1 + &clkc CLKID_MPLL0>; + clock-names = "mclk", "clk_srcpll", "samesource_sysclk"; + pinctrl-names = "tdm_pins"; + pinctrl-0 = <&tdmb_mclk &tdmout_b &tdmin_b>; + /* + * 0: tdmout_a; + * 1: tdmout_b; + * 2: tdmout_c; + * 3: spdifout; + * 4: spdifout_b; + */ + samesource_sel = <3>; + }; + + aml_tdmc: tdmc { + compatible = "amlogic, g12a-snd-tdmc"; + #sound-dai-cells = <0>; + dai-tdm-lane-slot-mask-in = <1 0 0 0>; + #dai-tdm-lane-slot-mask-out = <1 0 1 1>; + #dai-tdm-lane-oe-slot-mask-in = <0 0 0 0>; + #dai-tdm-lane-oe-slot-mask-out = <1 0 0 0>; + dai-tdm-clk-sel = <2>; + clocks = <&clkaudio CLKID_AUDIO_MCLK_C + &clkc CLKID_MPLL2>; + clock-names = "mclk", "clk_srcpll"; + pinctrl-names = "tdm_pins"; + pinctrl-0 = <&tdmc_mclk &tdmout_c &tdmin_c>; + }; + + /* copy a useless tdm to output for hdmi, no pinmux */ + aml_i2s2hdmi: i2s2hdmi { + compatible = "amlogic, g12a-snd-tdmc"; + #sound-dai-cells = <0>; + dai-tdm-lane-slot-mask-out = <1 1 1 1>; + dai-tdm-clk-sel = <2>; + clocks = <&clkaudio CLKID_AUDIO_MCLK_C + &clkc CLKID_MPLL2>; + clock-names = "mclk", "clk_srcpll"; + + i2s2hdmi = <1>; + + status = "okay"; + }; + + aml_spdif: spdif { + compatible = "amlogic, g12a-snd-spdif-a"; + #sound-dai-cells = <0>; + clocks = <&clkc CLKID_MPLL0 + &clkc CLKID_FCLK_DIV4 + &clkaudio CLKID_AUDIO_SPDIFIN + &clkaudio CLKID_AUDIO_SPDIFOUT + &clkaudio CLKID_AUDIO_SPDIFIN_CTRL + &clkaudio CLKID_AUDIO_SPDIFOUT_CTRL>; + clock-names = "sysclk", "fixed_clk", "gate_spdifin", + "gate_spdifout", "clk_spdifin", "clk_spdifout"; + interrupts = + ; + + interrupt-names = "irq_spdifin"; + pinctrl-names = "spdif_pins"; + pinctrl-0 = <&spdifout &spdifin>; + status = "okay"; + }; + aml_spdif_b: spdif_b { + compatible = "amlogic, g12a-snd-spdif-b"; + #sound-dai-cells = <0>; + clocks = <&clkc CLKID_MPLL0 /*CLKID_HIFI_PLL*/ + &clkaudio CLKID_AUDIO_SPDIFOUTB + &clkaudio CLKID_AUDIO_SPDIFOUTB_CTRL>; + clock-names = "sysclk", + "gate_spdifout", "clk_spdifout"; + status = "disabled"; + }; + aml_pdm: pdm { + compatible = "amlogic, g12a-snd-pdm"; + #sound-dai-cells = <0>; + clocks = <&clkaudio CLKID_AUDIO_PDM + &clkc CLKID_FCLK_DIV3 + &clkc CLKID_MPLL3 + &clkaudio CLKID_AUDIO_PDMIN0 + &clkaudio CLKID_AUDIO_PDMIN1>; + clock-names = "gate", + "sysclk_srcpll", + "dclk_srcpll", + "pdm_dclk", + "pdm_sysclk"; + pinctrl-names = "pdm_pins"; + pinctrl-0 = <&pdmin>; + filter_mode = <1>; /* mode 0~4, defalut:1 */ + status = "okay"; + }; + aml_loopback: loopback { + compatible = "amlogic, snd-loopback"; + /* + * 0: out rate = in data rate; + * 1: out rate = loopback data rate; + */ + lb_mode = <0>; + + /* datain src + * 0: tdmin_a; + * 1: tdmin_b; + * 2: tdmin_c; + * 3: spdifin; + * 4: pdmin; + */ + datain_src = <4>; + datain_chnum = <8>; + datain_chmask = <0x3f>; + + /* tdmin_lb src + * 0: tdmoutA + * 1: tdmoutB + * 2: tdmoutC + * 3: PAD_tdminA + * 4: PAD_tdminB + * 5: PAD_tdminC + */ + datalb_src = <2>; + datalb_chnum = <8>; + datalb_chmask = <0x3>; + + status = "disabled"; + }; + + audioresample: resample { + compatible = "amlogic, g12a-resample"; + clocks = <&clkc CLKID_MPLL3 + &clkaudio CLKID_AUDIO_MCLK_F + &clkaudio CLKID_AUDIO_RESAMPLE_CTRL>; + clock-names = "resample_pll", "resample_src", "resample_clk"; + /*same with toddr_src + * TDMIN_A, 0 + * TDMIN_B, 1 + * TDMIN_C, 2 + * SPDIFIN, 3 + * PDMIN, 4 + * NONE, + * TDMIN_LB, 6 + * LOOPBACK, 7 + */ + resample_module = <4>; + status = "disabled"; + }; + aml_pwrdet: pwrdet { + compatible = "amlogic, g12a-power-detect"; + + interrupts = ; + interrupt-names = "pwrdet_irq"; + + /* pwrdet source sel + * 7: loopback; + * 6: tdmin_lb; + * 5: reserved; + * 4: pdmin; + * 3: spdifin; + * 2: tdmin_c; + * 1: tdmin_b; + * 0: tdmin_a; + */ + pwrdet_src = <4>; + + hi_th = <0x70000>; + lo_th = <0x16000>; + + status = "disabled"; + }; +}; /* end of audiobus */ + +&pinctrl_periphs { + tdmout_a: tdmout_a { + mux { /* GPIOX_11, GPIOX_10, GPIOX_9 */ + groups = "tdma_sclk", + "tdma_fs", + "tdma_dout0"; + function = "tdma_out"; + }; + }; + + tdmin_a: tdmin_a { + mux { /* GPIOX_8 */ + groups = "tdma_din1"; + function = "tdma_in"; + }; + }; + + tdmb_mclk: tdmb_mclk { + mux { + groups = "mclk0_a"; + function = "mclk0"; + drive-strength = <2>; + }; + }; + tdmout_b: tdmout_b { + mux { /* GPIOA_1, GPIOA_2, GPIOA_3 */ + groups = "tdmb_sclk", + "tdmb_fs", + "tdmb_dout0"; + function = "tdmb_out"; + drive-strength = <2>; + }; + }; + + tdmin_b:tdmin_b { + mux { /* GPIOA_4 */ + groups = "tdmb_din1" + /*,"tdmb_slv_sclk", "tdmb_slv_fs"*/; + function = "tdmb_in"; + drive-strength = <2>; + }; + }; + + tdmc_mclk: tdmc_mclk { + mux { /* GPIOA_11 */ + groups = "mclk1_a"; + function = "mclk1"; + }; + }; + + tdmout_c:tdmout_c { + mux { /* GPIOA_12, GPIOA_13, GPIOA_8, GPIOA_7*/ + groups = "tdmc_sclk_a", + "tdmc_fs_a", + "tdmc_dout0_a" + /*, "tdmc_dout2", + * "tdmc_dout3" + */; + function = "tdmc_out"; + }; + }; + + tdmin_c:tdmin_c { + mux { /* GPIOA_10 */ + groups = "tdmc_din0_a"; + function = "tdmc_in"; + }; + }; + + spdifin: spdifin { + mux {/* GPIOH_5 */ + groups = "spdif_in_h"; + function = "spdif_in"; + }; + }; + + /* GPIOH_4 */ + /* + * spdifout: spdifout { + * mux { + * groups = "spdif_out_h"; + * function = "spdif_out"; + * }; + *}; + */ + + pdmin: pdmin { + mux { /* gpioa_5, gpioa_6, gpioa_7, gpioa_8, gpioa_9*/ + groups = "pdm_din0_a", + /*"pdm_din1_a",*/ + "pdm_din2_a", + /*"pdm_din3_a",*/ + "pdm_dclk_a"; + function = "pdm"; + }; + }; + + bl_pwm_off_pins:bl_pwm_off_pin { + mux { + pins = "GPIOH_5"; + function = "gpio_periphs"; + output-high; + }; + }; + +}; /* end of pinctrl_periphs */ + +&pinctrl_aobus { + spdifout: spdifout { + mux { /* gpiao_10 */ + groups = "spdif_out_ao"; + function = "spdif_out_ao"; + }; + }; +}; /* end of pinctrl_aobus */ + +&irblaster { + status = "disabled"; +}; + +&audio_data { + status = "okay"; +}; + +/*if you want to use vdin just modify status to "ok"*/ +&vdin0 { + memory-region = <&vdin0_cma_reserved>; + status = "okay"; + /*vdin write mem color depth support: + *bit0:support 8bit + *bit1:support 9bit + *bit2:support 10bit + *bit3:support 12bit + *bit4:support yuv422 10bit full pack mode (from txl new add) + */ + tv_bit_mode = <0x15>; +}; +&vdin1 { + memory-region = <&vdin1_cma_reserved>; + status = "okay"; + /*vdin write mem color depth support: + *bit0:support 8bit + *bit1:support 9bit + *bit2:support 10bit + *bit3:support 12bit + */ + tv_bit_mode = <1>; +}; + +&sd_emmc_c { + status = "okay"; + emmc { + caps = "MMC_CAP_8_BIT_DATA", + "MMC_CAP_MMC_HIGHSPEED", + "MMC_CAP_SD_HIGHSPEED", + "MMC_CAP_NONREMOVABLE", + /* "MMC_CAP_1_8V_DDR", */ + "MMC_CAP_HW_RESET", + "MMC_CAP_ERASE", + "MMC_CAP_CMD23"; + caps2 = "MMC_CAP2_HS200"; + /* "MMC_CAP2_HS400";*/ + f_min = <400000>; + f_max = <200000000>; + }; +}; + +&sd_emmc_b { + status = "okay"; + sd { + caps = "MMC_CAP_4_BIT_DATA", + "MMC_CAP_MMC_HIGHSPEED", + "MMC_CAP_SD_HIGHSPEED"; + f_min = <400000>; + f_max = <50000000>; + }; +}; + +&sd_emmc_a { + status = "okay"; + sdio { + caps = "MMC_CAP_4_BIT_DATA", + "MMC_CAP_MMC_HIGHSPEED", + "MMC_CAP_SD_HIGHSPEED", + "MMC_CAP_NONREMOVABLE", + "MMC_CAP_UHS_SDR12", + "MMC_CAP_UHS_SDR25", + "MMC_CAP_UHS_SDR50", + "MMC_CAP_UHS_SDR104", + "MMC_PM_KEEP_POWER", + "MMC_CAP_SDIO_IRQ"; + f_min = <400000>; + f_max = <200000000>; + }; +}; + +&nand { + status = "disabled"; + plat-names = "bootloader","nandnormal"; + plat-num = <2>; + plat-part-0 = <&bootloader>; + plat-part-1 = <&nandnormal>; + bootloader: bootloader{ + enable_pad ="ce0"; + busy_pad = "rb0"; + timming_mode = "mode5"; + bch_mode = "bch8_1k"; + t_rea = <20>; + t_rhoh = <15>; + chip_num = <1>; + part_num = <0>; + rb_detect = <1>; + }; + nandnormal: nandnormal{ + enable_pad ="ce0"; + busy_pad = "rb0"; + timming_mode = "mode5"; + bch_mode = "bch8_1k"; + plane_mode = "twoplane"; + t_rea = <20>; + t_rhoh = <15>; + chip_num = <2>; + part_num = <3>; + partition = <&nand_partitions>; + rb_detect = <1>; + }; + nand_partitions:nand_partition{ + /* + * if bl_mode is 1, tpl size was generate by + * fip_copies * fip_size which + * will not skip bad when calculating + * the partition size; + * + * if bl_mode is 0, + * tpl partition must be comment out. + */ + tpl{ + offset=<0x0 0x0>; + size=<0x0 0x0>; + }; + logo{ + offset=<0x0 0x0>; + size=<0x0 0x200000>; + }; + recovery{ + offset=<0x0 0x0>; + size=<0x0 0x1000000>; + }; + boot{ + offset=<0x0 0x0>; + size=<0x0 0x1000000>; + }; + system{ + offset=<0x0 0x0>; + size=<0x0 0x4000000>; + }; + data{ + offset=<0xffffffff 0xffffffff>; + size=<0x0 0x0>; + }; + }; +}; +&dwc3 { + status = "okay"; +}; + +&usb2_phy_v2 { + status = "okay"; + portnum = <2>; +}; + +&usb3_phy_v2 { + status = "okay"; + portnum = <0>; + otg = <1>; + gpio-vbus-power = "GPIOH_6"; + gpios = <&gpio GPIOH_6 GPIO_ACTIVE_HIGH>; +}; + +&dwc2_a { + status = "okay"; + /** 0: normal, 1: otg+dwc3 host only, 2: otg+dwc3 device only*/ + controller-type = <3>; +}; +ðmac { + status = "okay"; + pinctrl-names = "internal_eth_pins"; + pinctrl-0 = <&internal_eth_pins>; + mc_val = <0x4be04>; + + internal_phy=<1>; +}; + +&uart_A { + status = "okay"; +}; + +&pcie_A { + reset-gpio = <&gpio GPIOX_7 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&saradc { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/amlogic/gxl_p212_1g.dts b/arch/arm64/boot/dts/amlogic/gxl_p212_1g.dts index 5fa4dbce65df..d26cd2bb3bf3 100644 --- a/arch/arm64/boot/dts/amlogic/gxl_p212_1g.dts +++ b/arch/arm64/boot/dts/amlogic/gxl_p212_1g.dts @@ -139,14 +139,14 @@ }; }; - dummy-battery { + amlogic_battery:dummy-battery { compatible = "amlogic, dummy-battery"; - status = "okay"; + status = "disabled"; }; - dummy-charger { + amlogic_charger:dummy-charger { compatible = "amlogic, dummy-charger"; - status = "okay"; + status = "disabled"; }; bt-dev{ @@ -683,6 +683,7 @@ compatible = "amlogic, codec, mm"; memory-region = <&codec_mm_cma &codec_mm_reserved>; dev_name = "codec_mm"; + /*no-cmatvp;*/ status = "okay"; }; @@ -1220,3 +1221,4 @@ delay_control = <0x15>; ssctl = <0>; }; + diff --git a/arch/arm64/boot/dts/amlogic/gxl_p212_1g_buildroot.dts b/arch/arm64/boot/dts/amlogic/gxl_p212_1g_buildroot.dts index c2d3b9251a4b..edac4180ab4e 100644 --- a/arch/arm64/boot/dts/amlogic/gxl_p212_1g_buildroot.dts +++ b/arch/arm64/boot/dts/amlogic/gxl_p212_1g_buildroot.dts @@ -1260,3 +1260,4 @@ delay_control = <0x15>; ssctl = <0>; }; + diff --git a/arch/arm64/boot/dts/amlogic/gxl_p212_1g_hd.dts b/arch/arm64/boot/dts/amlogic/gxl_p212_1g_hd.dts index 6a064bbcfac0..b43f41ae6066 100644 --- a/arch/arm64/boot/dts/amlogic/gxl_p212_1g_hd.dts +++ b/arch/arm64/boot/dts/amlogic/gxl_p212_1g_hd.dts @@ -1204,3 +1204,4 @@ delay_control = <0x15>; ssctl = <0>; }; + diff --git a/arch/arm64/boot/dts/amlogic/gxl_p212_2g.dts b/arch/arm64/boot/dts/amlogic/gxl_p212_2g.dts index 2ffd2de29b11..cb0d7e1433d0 100644 --- a/arch/arm64/boot/dts/amlogic/gxl_p212_2g.dts +++ b/arch/arm64/boot/dts/amlogic/gxl_p212_2g.dts @@ -148,14 +148,14 @@ }; }; - dummy-battery { + amlogic_battery:dummy-battery { compatible = "amlogic, dummy-battery"; - status = "okay"; + status = "disabled"; }; - dummy-charger { + amlogic_charger:dummy-charger { compatible = "amlogic, dummy-charger"; - status = "okay"; + status = "disabled"; }; bt-dev{ @@ -1214,3 +1214,4 @@ &audio_data{ status = "okay"; }; + diff --git a/arch/arm64/boot/dts/amlogic/gxl_p230_2g.dts b/arch/arm64/boot/dts/amlogic/gxl_p230_2g.dts index bbb6ab864abf..b2c34e74162f 100644 --- a/arch/arm64/boot/dts/amlogic/gxl_p230_2g.dts +++ b/arch/arm64/boot/dts/amlogic/gxl_p230_2g.dts @@ -868,8 +868,8 @@ spdif_codec: spdif_codec{ #sound-dai-cells = <0>; compatible = "amlogic, aml-spdif-codec"; - pinctrl-names = "audio_spdif"; - pinctrl-0 = <&audio_spdif_pins>; + pinctrl-names = "audio_spdif_out"; + pinctrl-0 = <&audio_spdif_out_pins>; }; pcm_codec: pcm_codec{ #sound-dai-cells = <0>; @@ -1338,4 +1338,13 @@ function = "dvp"; }; }; + + /*spdif*/ + audio_spdif_out_pins: audio_spdif_out_pins { + mux { + groups = "spdif_out"; + function = "spdif_out"; + }; + }; }; /* end of pinctrl_periphs */ + diff --git a/arch/arm64/boot/dts/amlogic/gxl_p230_2g_buildroot.dts b/arch/arm64/boot/dts/amlogic/gxl_p230_2g_buildroot.dts index bbea7f6ae66e..bb8c58114048 100644 --- a/arch/arm64/boot/dts/amlogic/gxl_p230_2g_buildroot.dts +++ b/arch/arm64/boot/dts/amlogic/gxl_p230_2g_buildroot.dts @@ -855,8 +855,8 @@ spdif_codec: spdif_codec{ #sound-dai-cells = <0>; compatible = "amlogic, aml-spdif-codec"; - pinctrl-names = "audio_spdif"; - pinctrl-0 = <&audio_spdif_pins>; + pinctrl-names = "audio_spdif_out"; + pinctrl-0 = <&audio_spdif_out_pins>; }; pcm_codec: pcm_codec{ #sound-dai-cells = <0>; @@ -1284,6 +1284,44 @@ key-permit = "read","write","del"; }; };//End unifykey + dvb { + compatible = "amlogic, dvb"; + dev_name = "dvb"; + + fe0_mode = "external"; + fe0_demod = "Atbm8881"; + fe0_i2c_adap_id = <&i2c1>; + fe0_demod_i2c_addr = <0xc0>; + fe0_ts = <0>; + fe0_reset_value = <0>; + fe0_reset_gpio = <&gpio GPIODV_14 GPIO_ACTIVE_HIGH>; + + ts0 = "parallel"; + ts0_control = <0>; + ts0_invert = <0>; + interrupts = <0 23 1 + 0 5 1 + 0 21 1 + 0 19 1 + 0 25 1 + 0 18 1 + 0 24 1>; + interrupt-names = "demux0_irq", + "demux1_irq", + "demux2_irq", + "dvr0_irq", + "dvr1_irq", + "dvrfill0_fill", + "dvrfill1_flush"; + pinctrl-names = "p_ts0", "s_ts0"; + pinctrl-0 = <&dvb_p_ts0_pins>; + pinctrl-1 = <&dvb_s_ts0_pins>; + clocks = <&clkc CLKID_DEMUX + &clkc CLKID_ASYNC_FIFO + &clkc CLKID_AHB_ARB0 + &clkc CLKID_HIU_IFACE>; + clock-names = "demux", "asyncfifo", "ahbarb0", "uparsertop"; + }; }; &efuse { status = "ok"; @@ -1297,6 +1335,13 @@ status = "okay"; }; +&i2c1 { + status = "okay"; + clock-frequency = <300000>; + pinctrl-names="default"; + pinctrl-0=<&b_i2c_master>; +}; + &pinctrl_periphs { hdmirx_ext_pins: hdmirx_ext_pins { mux { @@ -1307,4 +1352,13 @@ function = "dvp"; }; }; -}; + + /*spdif*/ + audio_spdif_out_pins: audio_spdif_out_pins { + mux { + groups = "spdif_out"; + function = "spdif_out"; + }; + }; +}; /* end of pinctrl_periphs */ + diff --git a/arch/arm64/boot/dts/amlogic/gxl_p231_1g.dts b/arch/arm64/boot/dts/amlogic/gxl_p231_1g.dts index 0d924c2e9857..d054fa4b35e4 100644 --- a/arch/arm64/boot/dts/amlogic/gxl_p231_1g.dts +++ b/arch/arm64/boot/dts/amlogic/gxl_p231_1g.dts @@ -1119,3 +1119,4 @@ &pwm_ef { status = "okay"; }; + diff --git a/arch/arm64/boot/dts/amlogic/gxl_p231_2g.dts b/arch/arm64/boot/dts/amlogic/gxl_p231_2g.dts index e66d3e4a856a..b5702a6db52b 100644 --- a/arch/arm64/boot/dts/amlogic/gxl_p231_2g.dts +++ b/arch/arm64/boot/dts/amlogic/gxl_p231_2g.dts @@ -1119,3 +1119,4 @@ &pwm_ef { status = "okay"; }; + diff --git a/arch/arm64/boot/dts/amlogic/gxl_p231_2g_buildroot.dts b/arch/arm64/boot/dts/amlogic/gxl_p231_2g_buildroot.dts index f77ec383d642..800114c56de8 100644 --- a/arch/arm64/boot/dts/amlogic/gxl_p231_2g_buildroot.dts +++ b/arch/arm64/boot/dts/amlogic/gxl_p231_2g_buildroot.dts @@ -1188,3 +1188,4 @@ &pwm_ef { status = "okay"; }; + diff --git a/arch/arm64/boot/dts/amlogic/gxl_p241_1g.dts b/arch/arm64/boot/dts/amlogic/gxl_p241_1g.dts index e0ba54e7edae..078e772e2391 100644 --- a/arch/arm64/boot/dts/amlogic/gxl_p241_1g.dts +++ b/arch/arm64/boot/dts/amlogic/gxl_p241_1g.dts @@ -152,14 +152,14 @@ }; }; - dummy-battery { + amlogic_battery:dummy-battery { compatible = "amlogic, dummy-battery"; - status = "okay"; + status = "disabled"; }; - dummy-charger { + amlogic_charger:dummy-charger { compatible = "amlogic, dummy-charger"; - status = "okay"; + status = "disabled"; }; vpu { @@ -1299,3 +1299,4 @@ delay_control = <0x15>; ssctl = <0>; }; + diff --git a/arch/arm64/boot/dts/amlogic/gxl_p241_1g_buildroot.dts b/arch/arm64/boot/dts/amlogic/gxl_p241_1g_buildroot.dts index b7104b56c91e..def676aa8249 100644 --- a/arch/arm64/boot/dts/amlogic/gxl_p241_1g_buildroot.dts +++ b/arch/arm64/boot/dts/amlogic/gxl_p241_1g_buildroot.dts @@ -1354,3 +1354,4 @@ delay_control = <0x15>; ssctl = <0>; }; + diff --git a/arch/arm64/boot/dts/amlogic/gxl_p241_v2-1g.dts b/arch/arm64/boot/dts/amlogic/gxl_p241_v2-1g.dts index e5073d5f3e5f..71f920896bbd 100644 --- a/arch/arm64/boot/dts/amlogic/gxl_p241_v2-1g.dts +++ b/arch/arm64/boot/dts/amlogic/gxl_p241_v2-1g.dts @@ -153,14 +153,14 @@ }; }; - dummy-battery { + amlogic_battery:dummy-battery { compatible = "amlogic, dummy-battery"; - status = "okay"; + status = "disabled"; }; - dummy-charger { + amlogic_charger:dummy-charger { compatible = "amlogic, dummy-charger"; - status = "okay"; + status = "disabled"; }; vpu { @@ -1300,3 +1300,4 @@ delay_control = <0x15>; ssctl = <0>; }; + diff --git a/arch/arm64/boot/dts/amlogic/gxl_p241_v2_1g_buildroot.dts b/arch/arm64/boot/dts/amlogic/gxl_p241_v2_1g_buildroot.dts index 8118feb732cf..0e68cccd5139 100644 --- a/arch/arm64/boot/dts/amlogic/gxl_p241_v2_1g_buildroot.dts +++ b/arch/arm64/boot/dts/amlogic/gxl_p241_v2_1g_buildroot.dts @@ -1353,3 +1353,4 @@ delay_control = <0x15>; ssctl = <0>; }; + diff --git a/arch/arm64/boot/dts/amlogic/gxl_p400_2g.dts b/arch/arm64/boot/dts/amlogic/gxl_p400_2g.dts index 55434909251e..ab695abaef22 100644 --- a/arch/arm64/boot/dts/amlogic/gxl_p400_2g.dts +++ b/arch/arm64/boot/dts/amlogic/gxl_p400_2g.dts @@ -75,8 +75,6 @@ alignment = <0x0 0x400000>; alloc-ranges = <0x0 0x7dc00000 0x0 0x2400000>; }; - - }; wifi{ @@ -872,3 +870,4 @@ status = "okay"; }; }; + diff --git a/arch/arm64/boot/dts/amlogic/gxl_p401_2g.dts b/arch/arm64/boot/dts/amlogic/gxl_p401_2g.dts index bcaced491bf1..593c77612282 100644 --- a/arch/arm64/boot/dts/amlogic/gxl_p401_2g.dts +++ b/arch/arm64/boot/dts/amlogic/gxl_p401_2g.dts @@ -75,8 +75,6 @@ alignment = <0x0 0x400000>; alloc-ranges = <0x0 0x7dc00000 0x0 0x2400000>; }; - - }; wifi{ @@ -960,3 +958,4 @@ status = "okay"; }; }; + diff --git a/arch/arm64/boot/dts/amlogic/gxl_sei210_1g.dts b/arch/arm64/boot/dts/amlogic/gxl_sei210_1g.dts index 2c2f3f89d38b..d3086aa44071 100644 --- a/arch/arm64/boot/dts/amlogic/gxl_sei210_1g.dts +++ b/arch/arm64/boot/dts/amlogic/gxl_sei210_1g.dts @@ -1204,3 +1204,4 @@ delay_control = <0x15>; ssctl = <0>; }; + diff --git a/arch/arm64/boot/dts/amlogic/gxl_sei210_2g.dts b/arch/arm64/boot/dts/amlogic/gxl_sei210_2g.dts index 565b84002c4b..41e52477e181 100644 --- a/arch/arm64/boot/dts/amlogic/gxl_sei210_2g.dts +++ b/arch/arm64/boot/dts/amlogic/gxl_sei210_2g.dts @@ -1199,3 +1199,4 @@ &audio_data{ status = "okay"; }; + diff --git a/arch/arm64/boot/dts/amlogic/gxl_skt.dts b/arch/arm64/boot/dts/amlogic/gxl_skt.dts index 1ab1a077796f..56ecf91888ef 100644 --- a/arch/arm64/boot/dts/amlogic/gxl_skt.dts +++ b/arch/arm64/boot/dts/amlogic/gxl_skt.dts @@ -140,14 +140,14 @@ }; }; - dummy-battery { + amlogic_battery:dummy-battery { compatible = "amlogic, dummy-battery"; - status = "okay"; + status = "disabled"; }; - dummy-charger { + amlogic_charger:dummy-charger { compatible = "amlogic, dummy-charger"; - status = "okay"; + status = "disabled"; }; bt-dev{ @@ -1210,3 +1210,4 @@ delay_control = <0x15>; ssctl = <0>; }; + diff --git a/arch/arm64/boot/dts/amlogic/mesong12a.dtsi b/arch/arm64/boot/dts/amlogic/mesong12a.dtsi index 378950d3e413..d55ca6cc5b73 100644 --- a/arch/arm64/boot/dts/amlogic/mesong12a.dtsi +++ b/arch/arm64/boot/dts/amlogic/mesong12a.dtsi @@ -430,8 +430,14 @@ }; wdt: watchdog@0xffd0f0d0 { - compatible = "amlogic,meson-g12a-wdt"; + compatible = "amlogic, meson-wdt"; status = "okay"; + default_timeout=<10>; + reset_watchdog_method=<1>; /* 0:sysfs,1:kernel */ + reset_watchdog_time=<2>; + shutdown_timeout=<10>; + firmware_timeout=<6>; + suspend_timeout=<6>; reg = <0x0 0xffd0f0d0 0x0 0x10>; clock-names = "xtal"; clocks = <&xtal>; @@ -1361,6 +1367,7 @@ /*caps defined in dts*/ tx_delay = <0>; co_phase = <3>; + calc_f = <1>; max_req_size = <0x20000>; /**128KB*/ gpio_dat3 = <&gpio BOOT_3 GPIO_ACTIVE_HIGH>; hw_reset = <&gpio BOOT_9 GPIO_ACTIVE_HIGH>; @@ -1789,10 +1796,10 @@ }; defendkey: defendkey { - compatible = "amlogic, defendkey"; - reg = <0x0 0xff630218 0x0 0x4>; /*RNG_USR_DATA*/ - mem_size = <0x0 0x1000>; - status = "disabled"; + compatible = "amlogic, defendkey"; + reg = <0x0 0xff630218 0x0 0x4>; /*RNG_USR_DATA*/ + mem_size = <0x0 0x100000>; + status = "okay"; }; aml_dma { diff --git a/arch/arm64/boot/dts/amlogic/mesong12b.dtsi b/arch/arm64/boot/dts/amlogic/mesong12b.dtsi index b33d73778824..7e4ba928b65b 100644 --- a/arch/arm64/boot/dts/amlogic/mesong12b.dtsi +++ b/arch/arm64/boot/dts/amlogic/mesong12b.dtsi @@ -249,6 +249,7 @@ in_base_func = <0x82000020>; out_base_func = <0x82000021>; reserve_mem_size = <0x00300000>; + clear_range = <0x05100000 0x200000>; }; securitykey { @@ -470,8 +471,14 @@ }; wdt: watchdog@0xffd0f0d0 { - compatible = "amlogic,meson-g12a-wdt"; + compatible = "amlogic, meson-wdt"; status = "okay"; + default_timeout=<10>; + reset_watchdog_method=<1>; /* 0:sysfs,1:kernel */ + reset_watchdog_time=<2>; + shutdown_timeout=<10>; + firmware_timeout=<6>; + suspend_timeout=<6>; reg = <0x0 0xffd0f0d0 0x0 0x10>; clock-names = "xtal"; clocks = <&xtal>; @@ -1884,6 +1891,13 @@ "csi-host1-intr1"; link-device = <&adapter>; }; + + defendkey: defendkey { + compatible = "amlogic, defendkey"; + reg = <0x0 0xff630218 0x0 0x4>; /*RNG_USR_DATA*/ + mem_size = <0x0 0x100000>; + status = "okay"; + }; };/* end of / */ &pinctrl_aobus { diff --git a/arch/arm64/boot/dts/amlogic/mesongxl.dtsi b/arch/arm64/boot/dts/amlogic/mesongxl.dtsi index 42fdd83123ca..643a922dd599 100644 --- a/arch/arm64/boot/dts/amlogic/mesongxl.dtsi +++ b/arch/arm64/boot/dts/amlogic/mesongxl.dtsi @@ -554,6 +554,13 @@ compatible = "amlogic, vdac-gxl"; status = "okay"; }; + + defendkey: defendkey { + compatible = "amlogic, defendkey"; + reg = <0x0 0xc8834500 0x0 0x4>; /*RNG_USR_DATA*/ + mem_size = <0x0 0x100000>; + status = "okay"; + }; }; /* end of root */ &pinctrl_aobus { diff --git a/arch/arm64/boot/dts/amlogic/mesongxl_sei210.dtsi b/arch/arm64/boot/dts/amlogic/mesongxl_sei210.dtsi index b2e72ec2f32f..a66605342869 100644 --- a/arch/arm64/boot/dts/amlogic/mesongxl_sei210.dtsi +++ b/arch/arm64/boot/dts/amlogic/mesongxl_sei210.dtsi @@ -544,6 +544,13 @@ compatible = "amlogic, vdac-gxl"; status = "okay"; }; + + defendkey: defendkey { + compatible = "amlogic, defendkey"; + reg = <0x0 0xc8834500 0x0 0x4>; /*RNG_USR_DATA*/ + mem_size = <0x0 0x100000>; + status = "okay"; + }; }; /* end of root */ &pinctrl_aobus { diff --git a/arch/arm64/boot/dts/amlogic/mesontxl.dtsi b/arch/arm64/boot/dts/amlogic/mesontxl.dtsi index 43885b0e5554..10332dfbbe35 100644 --- a/arch/arm64/boot/dts/amlogic/mesontxl.dtsi +++ b/arch/arm64/boot/dts/amlogic/mesontxl.dtsi @@ -388,6 +388,14 @@ sys_poweroff = <0x84000008>; }; + rtc { + compatible = "amlogic, aml_vrtc"; + alarm_reg_addr = <0xc81000a8>; + timer_e_addr = <0xc1109988>; + init_date = "2018/01/01"; + status = "okay"; + }; + soc { compatible = "simple-bus"; #address-cells = <2>; @@ -552,8 +560,14 @@ }; wdt_ee: watchdog@98d0 { - compatible = "amlogic,meson-txl-wdt"; + compatible = "amlogic, meson-wdt"; status = "okay"; + default_timeout=<10>; + reset_watchdog_method=<1>;/*0:sysfs,1:kernel*/ + reset_watchdog_time=<2>; + shutdown_timeout=<10>; + firmware_timeout=<6>; + suspend_timeout=<6>; reg = <0x0 0x98d0 0x0 0x10>; clock-names = "xtal"; clocks = <&xtal>; diff --git a/arch/arm64/boot/dts/amlogic/partition_mbox_ab_P_32.dtsi b/arch/arm64/boot/dts/amlogic/partition_mbox_ab_P_32.dtsi new file mode 100644 index 000000000000..fc5a9b7490f6 --- /dev/null +++ b/arch/arm64/boot/dts/amlogic/partition_mbox_ab_P_32.dtsi @@ -0,0 +1,173 @@ +/* + * arch/arm64/boot/dts/amlogic/partition_mbox_ab_P_32.dtsi + * + * Copyright (C) 2017 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +#include "firmware_ab.dtsi" + +/ { + partitions: partitions{ + parts = <23>; + part-0 = <&logo>; + part-1 = <&boot_a>; + part-2 = <&misc>; + part-3 = <&dtbo_a>; + part-4 = <&dtbo_b>; + part-5 = <&cri_data>; + part-6 = <¶m>; + part-7 = <&boot_b>; + part-8 = <&rsv>; + part-9 = <&metadata_a>; + part-10 = <&metadata_b>; + part-11 = <&vbmeta_a>; + part-12 = <&vbmeta_b>; + part-13 = <&tee>; + part-14 = <&vendor_a>; + part-15 = <&vendor_b>; + part-16 = <&odm_a>; + part-17 = <&odm_b>; + part-18 = <&system_a>; + part-19 = <&system_b>; + part-20 = <&product_a>; + part-21 = <&product_b>; + part-22 = <&data>; + + logo:logo{ + pname = "logo"; + size = <0x0 0x800000>; + mask = <1>; + }; + boot_a:boot_a + { + pname = "boot_a"; + size = <0x0 0x1000000>; + mask = <1>; + }; + misc:misc{ + pname = "misc"; + size = <0x0 0x800000>; + mask = <1>; + }; + dtbo_a:dtbo_a{ + pname = "dtbo_a"; + size = <0x0 0x800000>; + mask = <1>; + }; + dtbo_b:dtbo_b{ + pname = "dtbo_b"; + size = <0x0 0x800000>; + mask = <1>; + }; + cri_data:cri_data + { + pname = "cri_data"; + size = <0x0 0x800000>; + mask = <2>; + }; + rsv:rsv{ + pname = "rsv"; + size = <0x0 0x1000000>; + mask = <1>; + }; + metadata_a:metadata_a{ + pname = "metadata_a"; + size = <0x0 0x1000000>; + mask = <1>; + }; + metadata_b:metadata_b{ + pname = "metadata_b"; + size = <0x0 0x1000000>; + mask = <1>; + }; + vbmeta_a:vbmeta_a{ + pname = "vbmeta_a"; + size = <0x0 0x200000>; + mask = <1>; + }; + vbmeta_b:vbmeta_b{ + pname = "vbmeta_b"; + size = <0x0 0x200000>; + mask = <1>; + }; + param:param{ + pname = "param"; + size = <0x0 0x1000000>; + mask = <2>; + }; + boot_b:boot_b + { + pname = "boot_b"; + size = <0x0 0x1000000>; + mask = <1>; + }; + tee:tee{ + pname = "tee"; + size = <0x0 0x2000000>; + mask = <1>; + }; + vendor_a:vendor_a + { + pname = "vendor_a"; + size = <0x0 0x10000000>; + mask = <1>; + }; + vendor_b:vendor_b + { + pname = "vendor_b"; + size = <0x0 0x10000000>; + mask = <1>; + }; + odm_a:odm_a + { + pname = "odm_a"; + size = <0x0 0x8000000>; + mask = <1>; + }; + odm_b:odm_b + { + pname = "odm_b"; + size = <0x0 0x8000000>; + mask = <1>; + }; + system_a:system_a + { + pname = "system_a"; + size = <0x0 0x50000000>; + mask = <1>; + }; + system_b:system_b + { + pname = "system_b"; + size = <0x0 0x50000000>; + mask = <1>; + }; + product_a:product_a{ + pname = "product_a"; + size = <0x0 0x8000000>; + mask = <1>; + }; + product_b:product_b{ + pname = "product_b"; + size = <0x0 0x8000000>; + mask = <1>; + }; + data:data + { + pname = "data"; + size = <0xffffffff 0xffffffff>; + mask = <4>; + }; + }; +};/* end of / */ diff --git a/arch/arm64/boot/dts/amlogic/txl_t950_p341.dts b/arch/arm64/boot/dts/amlogic/txl_t950_p341.dts index ebdb3510b2d9..c3ad02ce19b3 100644 --- a/arch/arm64/boot/dts/amlogic/txl_t950_p341.dts +++ b/arch/arm64/boot/dts/amlogic/txl_t950_p341.dts @@ -53,8 +53,13 @@ #address-cells = <2>; #size-cells = <2>; ranges; - /* global autoconfigured region for contiguous allocations */ + + defendkey_reserved:linux,defendkey { + compatible = "amlogic, defendkey"; + reg = <0x0 0x08300000 0x0 0x100000>; + }; + secmon_reserved:linux,secmon { compatible = "shared-dma-pool"; reusable; @@ -361,6 +366,7 @@ * bit9:use 10bit at 4k_50/60hz_10bit */ tv_bit_mode = <0x215>; + urgent_en = <1>; }; vdin@1 { diff --git a/arch/arm64/boot/dts/amlogic/txl_t960_p346.dts b/arch/arm64/boot/dts/amlogic/txl_t960_p346.dts index fa832cc89a7a..1d3a079c0a09 100644 --- a/arch/arm64/boot/dts/amlogic/txl_t960_p346.dts +++ b/arch/arm64/boot/dts/amlogic/txl_t960_p346.dts @@ -53,8 +53,13 @@ #address-cells = <2>; #size-cells = <2>; ranges; - /* global autoconfigured region for contiguous allocations */ + + defendkey_reserved:linux,defendkey { + compatible = "amlogic, defendkey"; + reg = <0x0 0x08300000 0x0 0x100000>; + }; + secmon_reserved:linux,secmon { compatible = "shared-dma-pool"; reusable; diff --git a/arch/arm64/boot/dts/amlogic/txl_t962_p320.dts b/arch/arm64/boot/dts/amlogic/txl_t962_p320.dts index 48b6360c5c54..b87e7e04187d 100644 --- a/arch/arm64/boot/dts/amlogic/txl_t962_p320.dts +++ b/arch/arm64/boot/dts/amlogic/txl_t962_p320.dts @@ -53,8 +53,13 @@ #address-cells = <2>; #size-cells = <2>; ranges; - /* global autoconfigured region for contiguous allocations */ + + defendkey_reserved:linux,defendkey { + compatible = "amlogic, defendkey"; + reg = <0x0 0x08300000 0x0 0x100000>; + }; + secmon_reserved:linux,secmon { compatible = "shared-dma-pool"; reusable; diff --git a/arch/arm64/boot/dts/amlogic/txl_t962_p321.dts b/arch/arm64/boot/dts/amlogic/txl_t962_p321.dts index 8af1f38cbdb7..446bf37091e4 100644 --- a/arch/arm64/boot/dts/amlogic/txl_t962_p321.dts +++ b/arch/arm64/boot/dts/amlogic/txl_t962_p321.dts @@ -53,8 +53,13 @@ #address-cells = <2>; #size-cells = <2>; ranges; - /* global autoconfigured region for contiguous allocations */ + + defendkey_reserved:linux,defendkey { + compatible = "amlogic, defendkey"; + reg = <0x0 0x08300000 0x0 0x100000>; + }; + secmon_reserved:linux,secmon { compatible = "shared-dma-pool"; reusable; @@ -149,14 +154,14 @@ }; }; /* end of reserved-memory */ - dummy-battery { + amlogic_battery:dummy-battery { compatible = "amlogic, dummy-battery"; - status = "okay"; + status = "disabled"; }; - dummy-charger { + amlogic_charger:dummy-charger { compatible = "amlogic, dummy-charger"; - status = "okay"; + status = "disabled"; }; secmon { diff --git a/arch/arm64/boot/dts/amlogic/txl_t962_p321_720p.dts b/arch/arm64/boot/dts/amlogic/txl_t962_p321_720p.dts new file mode 100644 index 000000000000..8e154af23a53 --- /dev/null +++ b/arch/arm64/boot/dts/amlogic/txl_t962_p321_720p.dts @@ -0,0 +1,1173 @@ +/* + * arch/arm64/boot/dts/amlogic/txl_t962_321.dts + * + * Copyright (C) 2018 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +/dts-v1/; + +#include "mesontxl.dtsi" +#include "partition_mbox_normal.dtsi" +#include "mesontxl_p321-panel.dtsi" + +/ { + model = "Amlogic TXL T962 P321 Reference Board"; + compatible = "amlogic, txl_t962_p321"; + amlogic-dt-id = "txl_p321_v1_720p"; + + aliases { + serial0 = &uart_AO; + serial1 = &uart_A; + serial2 = &uart_B; + serial3 = &uart_C; + serial4 = &uart_AO_B; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c_AO; + }; + + ion_dev { + compatible = "amlogic, ion_dev"; + memory-region = <&ion_reserved>; + }; + + memory@00000000 { + device_type = "memory"; + linux,usable-memory = <0x0 0x100000 0x0 0x3ff00000>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + /* global autoconfigured region for contiguous allocations */ + + defendkey_reserved:linux,defendkey { + compatible = "amlogic, defendkey"; + reg = <0x0 0x08300000 0x0 0x100000>; + }; + + secmon_reserved:linux,secmon { + compatible = "shared-dma-pool"; + reusable; + size = <0x0 0x400000>; + alignment = <0x0 0x400000>; + alloc-ranges = <0x0 0x05000000 0x0 0x400000>; + }; + + //secos_reserved:linux,secos { + // status = "disabled"; + // compatible = "amlogic, aml_secos_memory"; + // reg = <0x0 0x05300000 0x0 0x2000000>; + // no-map; + //}; + + logo_reserved:linux,meson-fb { + compatible = "shared-dma-pool"; + reusable; + size = <0x0 0x400000>; + alignment = <0x0 0x400000>; + alloc-ranges = <0x0 0x3fc00000 0x0 0x400000>; + }; + + ion_reserved:linux,ion-dev { + compatible = "shared-dma-pool"; + reusable; + size = <0x0 0x4C00000>; + alignment = <0x0 0x400000>; + }; + + /*di CMA pool */ + di_cma_reserved:linux,di_cma { + compatible = "shared-dma-pool"; + reusable; + /* buffer_size = 3621952(yuv422 8bit) + * | 4736064(yuv422 10bit) + * | 4179008(yuv422 10bit full pack mode) + * 10x3621952=34.6M(0x23) support 8bit + * 10x4736064=45.2M(0x2e) support 12bit + * 10x4179008=40M(0x28) support 10bit + */ + size = <0x0 0x02800000>; + alignment = <0x0 0x400000>; + }; + + /* POST PROCESS MANAGER */ + ppmgr_reserved:linux,ppmgr { + compatible = "amlogic, ppmgr_memory"; + size = <0x0 0x0>; + }; + + codec_mm_cma:linux,codec_mm_cma { + compatible = "shared-dma-pool"; + reusable; + /* ion_codec_mm max can alloc size 80M*/ + size = <0x0 0xd000000>; + alignment = <0x0 0x400000>; + linux,contiguous-region; + }; + + picdec_cma_reserved:linux,picdec { + compatible = "shared-dma-pool"; + reusable; + size = <0x0 0x0>; + alignment = <0x0 0x0>; + linux,contiguous-region; + }; + + /* codec shared reserved */ + codec_mm_reserved:linux,codec_mm_reserved { + compatible = "amlogic, codec-mm-reserved"; + size = <0x0 0x0>; + alignment = <0x0 0x100000>; + //no-map; + }; + + demod_cma_reserved:linux,demod_cma { + compatible = "shared-dma-pool"; + reusable; + /* 5M */ + size = <0x0 0x0800000>; + alignment = <0x0 0x400000>; + }; + + /* vdin1 CMA pool */ + vdin1_cma_reserved:linux,vdin1_cma { + compatible = "shared-dma-pool"; + reusable; + /* 1920x1080x2x4 =16 M */ + size = <0x0 0x01000000>; + alignment = <0x0 0x400000>; + }; + }; /* end of reserved-memory */ + + amlogic_battery:dummy-battery { + compatible = "amlogic, dummy-battery"; + status = "disabled"; + }; + + amlogic_charger:dummy-charger { + compatible = "amlogic, dummy-charger"; + status = "disabled"; + }; + + secmon { + compatible = "amlogic, secmon"; + memory-region = <&secmon_reserved>; + in_base_func = <0x82000020>; + out_base_func = <0x82000021>; + reserve_mem_size = <0x00300000>; + }; + + gpioleds { + compatible = "gpio-leds"; + status = "disabled"; + + sys_led { + label = "sys_led"; + gpios = <&gpio_ao GPIOAO_3 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + }; + + /*for external keypad*/ + adc-keypad { + compatible = "amlogic, adc_keypad"; + status = "okay"; + key_name = "power","up", "down","enter","left","right","home"; + key_num = <7>; + io-channels = <&saradc SARADC_CH2>, + <&saradc SARADC_CH3>; + io-channel-names = "key-chan-2", "key-chan-3"; + key_chan = ; + key_code = <116 103 108 28 105 106 102>; + key_val = <0 143 266 389 512 143 266>; //val=voltage/1800mV*1023 + key_tolerance = <40 40 40 40 40 40 40>; + }; + + avin_detect { + compatible = "amlogic, avin_detect"; + status = "okay"; + avin_device_num = <1>; + gpios = <&gpio GPIODV_8 GPIO_ACTIVE_HIGH>; + detect_interval_length = <100>; + set_detect_times = <5>; + set_fault_tolerance = <1>; + }; + + meson-fb { + compatible = "amlogic, meson-txl"; + memory-region = <&logo_reserved>; + dev_name = "meson-fb"; + status = "okay"; + interrupts = <0 3 1 + 0 89 1>; + interrupt-names = "viu-vsync", "rdma"; + mem_size = <0x00400000 0x00b00000 0x00100000>; + /* uboot logo,fb0/fb1 memory size,if afbcd fb0=0x0b51000*/ + display_mode_default = "720p60hz"; + /* 0:VPU free scale 1:OSD free scale 2:OSD super scale */ + scale_mode = <1>; + /* 1920*1080*4*3 = 0x17BB000 */ + display_size_default = <1280 720 1280 2160 32>; + pxp_mode = <0>; /** 0:normal mode 1:pxp mode */ + logo_addr = "0x3fc00000"; + }; + + picdec { + compatible = "amlogic, picdec"; + status = "okay"; + memory-region = <&picdec_cma_reserved>; + }; + + ppmgr { + compatible = "amlogic, ppmgr"; + status = "okay"; + memory-region = <&ppmgr_reserved>; + }; + + deinterlace { + compatible = "amlogic, deinterlace"; + status = "okay"; + /* 0:use reserved; 1:use cma; 2:use cma as reserved */ + flag_cma = <1>; + //memory-region = <&di_reserved>; + memory-region = <&di_cma_reserved>; + interrupts = <0 46 1 + 0 6 1>; + interrupt-names = "de_irq"; + clocks = <&clkc CLKID_VPU_MUX>, + <&clkc CLKID_FCLK_DIV4>, + <&clkc CLKID_VPU_CLKB_TMP_COMP>, + <&clkc CLKID_VPU_CLKB_COMP>; + clock-names = "vpu_mux", + "fclk_div4", + "vpu_clkb_tmp_composite", + "vpu_clkb_composite"; + clock-range = <333 333>; + /* buffer-size = <3621952>;(yuv422 8bit) */ + buffer-size = <4179008>;/*yuv422 fullpack*/ + /* reserve-iomap = "true"; */ + /* if enable nr10bit, set nr10bit-support to 1 */ + nr10bit-support = <1>; + }; + + ionvideo { + compatible = "amlogic, ionvideo"; + dev_name = "ionvideo"; + status = "okay"; + }; + + hdmirx { + compatible = "amlogic, hdmirx-txl"; + status = "okay"; + #address-cells=<1>; + #size-cells=<1>; + dev_name = "hdmirx"; + pinctrl-names = "hdmirx_pins"; + pinctrl-0 = <&hdmirx_a_mux &hdmirx_b_mux + &hdmirx_c_mux>; + repeat = <0>; + interrupts = <0 56 1>; + clocks = <&clkc CLKID_HDMIRX_MODET_COMP>, + <&clkc CLKID_HDMIRX_CFG_COMP>, + <&clkc CLKID_HDMIRX_ACR_COMP>, + <&clkc CLKID_HDMIRX_AUDMEAS_COMP>, + <&xtal>, + <&clkc CLKID_FCLK_DIV5>, + <&clkc CLKID_FCLK_DIV7>, + <&clkc CLKID_HDCP22_SKP_COMP>, + <&clkc CLKID_HDCP22_ESM_COMP>; + //<&clkc CLK_AUD_PLL2FS>, + //<&clkc CLK_AUD_PLL4FS>, + //<&clkc CLK_AUD_OUT>; + clock-names = "hdmirx_modet_clk", + "hdmirx_cfg_clk", + "hdmirx_acr_ref_clk", + "hdmirx_audmeas_clk", + "xtal", + "fclk_div5", + "fclk_div7", + "hdcp_rx22_skp", + "hdcp_rx22_esm"; + //"hdmirx_aud_pll2fs", + //"hdmirx_aud_pll4f", + //"clk_aud_out"; + hdmirx_id = <0>; + en_4k_2_2k = <0>; + hpd_low_cec_off = <1>; + /* bit4: enable feature, bit3~0: port number */ + disable_port = <0x0>; + reg = <0x0 0xc0800000 0x0 0xa00000 + 0x0 0xC883C000 0x0 0x2000 + 0x0 0xd0076000 0x0 0x2000 + 0x0 0xc883e000 0x0 0x2000 + 0x0 0xda83e000 0x0 0x2000 + 0x0 0xc8834000 0x0 0x2000 + 0x0 0xda846000 0x0 0x2000>; + }; + + vdin@0 { + compatible = "amlogic, vdin"; + /*memory-region = <&vdin0_cma_reserved>;*/ + dev_name = "vdin0"; + status = "okay"; + reserve-iomap = "true"; + /*bit0:(1:share with codec_mm;0:cma alone)*/ + /*bit8:(1:alloc in discontinus way;0:alone in continuous way)*/ + flag_cma = <0x101>; + /* MByte, if 10bit disable: 64M(YUV422), + * if 10bit enable: 64*1.5 = 96M(YUV422) + * if support 4K2K-YUV444-10bit-WR:3840*2160*4*4 ~= 128M + * if support 4K2K-YUV444-10bit-WR:3840*2160*4*6 ~= 190M + * if support 4K2K-YUV422-10bit-wr:3840*2160*3*4 ~= 96M + * if support 4K2K-YUV422-8BIT-WR:3840*2160*2*4 ~= 64M + * if support 1080p-YUV422-8BIT-WR:1920*1080*2*4 ~= 16M + */ + cma_size = <190>; + interrupts = <0 83 1>; + rdma-irq = <2>; + clocks = <&clkc CLKID_FCLK_DIV5>, + <&clkc CLKID_VDIN_MEAS_COMP>; + clock-names = "fclk_div5", "cts_vdin_meas_clk"; + vdin_id = <0>; + /* vdin write mem color depth support: + * bit0:support 8bit + * bit1:support 9bit + * bit2:support 10bit + * bit3:support 12bit + * bit4:support yuv422 10bit full pack mode (from txl new add) + * bit8:use 8bit at 4k_50/60hz_10bit + * bit9:use 10bit at 4k_50/60hz_10bit + */ + tv_bit_mode = <0x215>; + }; + + vdin@1 { + compatible = "amlogic, vdin"; + memory-region = <&vdin1_cma_reserved>; + dev_name = "vdin1"; + status = "okay"; + reserve-iomap = "true"; + flag_cma = <0>;/*1:share with codec_mm;0:cma alone*/ + interrupts = <0 85 1>; + rdma-irq = <4>; + clocks = <&clkc CLKID_FCLK_DIV5>, + <&clkc CLKID_VDIN_MEAS_COMP>; + clock-names = "fclk_div5", "cts_vdin_meas_clk"; + vdin_id = <1>; + /* vdin write mem color depth support: + * bit0:support 8bit + * bit1:support 9bit + * bit2:support 10bit + * bit3:support 12bit + */ + tv_bit_mode = <21>; + }; + + tvafe:tvafe@c8842000 { + compatible = "amlogic, tvafe-txl"; + status = "okay"; + /*memory-region = <&tvafe_cma_reserved>;*/ + dev_name = "tvafe"; + flag_cma = <1>;/*1:share with codec_mm;0:cma alone*/ + cma_size = <5>;/*MByte*/ + reg = <0x0 0xc8842000 0x0 0x2000>;/*tvafe reg base*/ + reserve-iomap = "true"; + tvafe_id = <0>; + //pinctrl-names = "default"; + /*!!particular sequence, no more and no less!!!*/ + tvafe_pin_mux = < + 3 /* TVAFE_CVBS_IN2, CVBS_IN0 = 0 */ + 1 /* TVAFE_CVBS_IN0, CVBS_IN1 */ + 2 /* TVAFE_CVBS_IN1, CVBS_IN2 */ + 4 /* TVAFE_CVBS_IN3, CVBS_IN3 */ + >; + clocks = <&clkc CLKID_DAC_CLK>; + clock-names = "vdac_clk_gate"; + }; + + vecm { + compatible = "amlogic, vecm"; + dev_name = "aml_vecm"; + status = "okay"; + gamma_en = <1>;/*1:enabel ;0:disable*/ + wb_en = <1>;/*1:enabel ;0:disable*/ + cm_en = <1>;/*1:enabel ;0:disable*/ + wb_sel = <1>;/*1:mtx ;0:gainoff*/ + vlock_en = <1>;/*1:enable;0:disable*/ + vlock_mode = <0x4>; + /* vlock work mode: + *bit0:auto ENC + *bit1:auto PLL + *bit2:manual PLL + *bit3:manual ENC + *bit4:manual soft ENC + *bit5:manual MIX PLL ENC + */ + vlock_pll_m_limit = <1>; + vlock_line_limit = <3>; + }; + + tuner: tuner { + status = "okay"; + tuner_name = "r842_tuner"; + tuner_i2c_adap = <&i2c1>; + tuner_i2c_addr = <0xf6>; + tuner_xtal = <1>; /* 0: 16MHz, 1: 24MHz, 3: 27MHz */ + tuner_xtal_mode = <0>; + /* NO_SHARE_XTAL(0) + * MASTER_TO_SLAVE_XTAL_IN(1) + * MASTER_TO_SLAVE_XTAL_OUT(2) + * SLAVE_XTAL_OUT(3) + */ + tuner_xtal_cap = <38>; /* 0 ~ 41 (pf) */ + }; + + atv-demod { + compatible = "amlogic, atv-demod"; + status = "okay"; + tuner = <&tuner>; + btsc_sap_mode = <1>; + pinctrl-names = "atvdemod_agc_pins"; + pinctrl-0 = <&atvdemod_agc_pins>; + reg = <0x0 0xc8840000 0x0 0x2000 /* demod reg */ + 0x0 0xc883c000 0x0 0x2000 /* hiu reg */ + 0x0 0xc8834000 0x0 0x2000>; /* periphs reg */ + reg_23cf = <0x88188832>; + /*default:0x88188832;r840 on haier:0x48188832*/ + }; + + sd_emmc_c: emmc@d0074000 { + compatible = "amlogic, meson-mmc-txl"; + status = "okay"; + reg = <0x0 0xd0074000 0x0 0x2000>; + interrupts = <0 218 1>; + pinctrl-names = "emmc_clk_cmd_pins", "emmc_all_pins"; + pinctrl-0 = <&emmc_clk_cmd_pins>; + pinctrl-1 = <&emmc_conf_pull_up &emmc_conf_pull_done>; + clocks = <&clkc CLKID_SD_EMMC_C>, + <&clkc CLKID_SD_EMMC_C_COMP>, + <&clkc CLKID_FCLK_DIV2>; + clock-names = "core", "clkin0", "clkin1"; + + bus-width = <8>; + cap-sd-highspeed; + cap-mmc-highspeed; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + + max-frequency = <200000000>; + non-removable; + disable-wp; + emmc { + pinname = "emmc"; + ocr_avail = <0x200080>; /**VDD voltage 3.3 ~ 3.4 */ + caps = "MMC_CAP_8_BIT_DATA", + "MMC_CAP_MMC_HIGHSPEED", + "MMC_CAP_SD_HIGHSPEED", + "MMC_CAP_NONREMOVABLE", + "MMC_CAP_1_8V_DDR", + "MMC_CAP_HW_RESET", + "MMC_CAP_ERASE", + "MMC_CAP_CMD23"; + caps2 = "MMC_CAP2_HS200"; + f_min = <400000>; + f_max = <100000000>; + max_req_size = <0x20000>; /**128KB*/ + gpio_dat3 = <&gpio BOOT_3 GPIO_ACTIVE_HIGH>; + hw_reset = <&gpio BOOT_9 GPIO_ACTIVE_HIGH>; + tx_phase = <3>; + card_type = <1>; + /* 1:mmc card(include eMMC), + * 2:sd card(include tSD) + */ + }; + }; + + sd_emmc_b:sd@d0072000 { + compatible = "amlogic, meson-mmc-txl"; + status = "okay"; + reg = <0x0 0xd0072000 0x0 0x2000>; + interrupts = <0 217 1>; + pinctrl-names = "sd_all_pins", + "sd_clk_cmd_pins", + "sd_1bit_pins", + "sd_clk_cmd_uart_pins", + "sd_1bit_uart_pins", + "sd_to_ao_uart_pins", + "ao_to_sd_uart_pins", + "ao_to_sd_jtag_pins", + "sd_to_ao_jtag_pins"; + pinctrl-0 = <&sd_all_pins>; + pinctrl-1 = <&sd_clk_cmd_pins>; + pinctrl-2 = <&sd_1bit_pins>; + pinctrl-3 = <&sd_to_ao_uart_clr_pins + &sd_clk_cmd_pins &ao_to_sd_uart_pins>; + pinctrl-4 = <&sd_to_ao_uart_clr_pins + &sd_1bit_pins &ao_to_sd_uart_pins>; + pinctrl-5 = <&sd_all_pins &sd_to_ao_uart_pins>; + pinctrl-6 = <&sd_to_ao_uart_clr_pins &ao_to_sd_uart_pins>; + pinctrl-7 = <&sd_to_ao_uart_clr_pins &ao_to_sd_uart_pins>; + pinctrl-8 = <&sd_all_pins &sd_to_ao_uart_pins>; + clocks = <&clkc CLKID_SD_EMMC_B>, + <&clkc CLKID_SD_EMMC_B_COMP>, + <&clkc CLKID_FCLK_DIV2>; + clock-names = "core", "clkin0", "clkin1"; + + bus-width = <4>; + cap-sd-highspeed; + max-frequency = <100000000>; + disable-wp; + sd { + pinname = "sd"; + ocr_avail = <0x200080>; /**VDD voltage 3.3 ~ 3.4 */ + caps = "MMC_CAP_4_BIT_DATA", + "MMC_CAP_MMC_HIGHSPEED", + "MMC_CAP_SD_HIGHSPEED"; + /* "MMC_CAP_UHS_SDR12", + * "MMC_CAP_UHS_SDR25", + * "MMC_CAP_UHS_SDR50", + * "MMC_CAP_UHS_SDR104"; + */ + f_min = <400000>; + f_max = <100000000>; + max_req_size = <0x20000>; /**128KB*/ + gpio_dat3 = <&gpio CARD_4 GPIO_ACTIVE_HIGH>; + jtag_pin = <&gpio CARD_0 GPIO_ACTIVE_HIGH>; + gpio_cd = <&gpio CARD_6 GPIO_ACTIVE_HIGH>; + card_type = <5>; + /* 0:unknown, + * 1:mmc card(include eMMC), + * 2:sd card(include tSD), + * 3:sdio device(ie:sdio-wifi), + * 4:SD combo (IO+mem) card, + * 5:NON sdio device(means sd/mmc card), + * other:reserved + */ + }; + }; + + spifc: spifc@c1108c80 { + status = "disabled"; + compatible = "amlogic,aml-spi-nor"; + reg = <0x0 0xc1108c80 0x0 0x80>; + pinctrl-names = "default"; + pinctrl-0 = <&spifc_all_pins>; + clocks = <&clkc CLKID_CLK81>; + clock-names = "core"; + spi-nor@0 { + compatible = "jedec,spi-nor"; + spifc-frequency = <40000000>; + read-capability = <2>;/* dual read 1_1_2 */ + spifc-io-width = <2>;/* txl only support 2 io */ + cs_gpios = <&gpio BOOT_11 GPIO_ACTIVE_HIGH>; + }; + }; + + unifykey { + compatible = "amlogic, unifykey"; + status = "okay"; + + unifykey-num = <19>; + unifykey-index-0 = <&keysn_0>; + unifykey-index-1 = <&keysn_1>; + unifykey-index-2 = <&keysn_2>; + unifykey-index-3 = <&keysn_3>; + unifykey-index-4 = <&keysn_4>; + unifykey-index-5 = <&keysn_5>; + unifykey-index-6 = <&keysn_6>; + unifykey-index-7 = <&keysn_7>; + unifykey-index-8 = <&keysn_8>; + unifykey-index-9 = <&keysn_9>; + unifykey-index-10= <&keysn_10>; + unifykey-index-11 = <&keysn_11>; + unifykey-index-12 = <&keysn_12>; + unifykey-index-13 = <&keysn_13>; + unifykey-index-14 = <&keysn_14>; + unifykey-index-15 = <&keysn_15>; + unifykey-index-16 = <&keysn_16>; + unifykey-index-17 = <&keysn_17>; + unifykey-index-18 = <&keysn_18>; + + keysn_0: key_0{ + key-name = "usid"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_1:key_1{ + key-name = "mac"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_2:key_2{ + key-name = "hdcp"; + key-device = "secure"; + key-type = "sha1"; + key-permit = "read","write","del"; + }; + keysn_3:key_3{ + key-name = "secure_boot_set"; + key-device = "efuse"; + key-permit = "write"; + }; + keysn_4:key_4{ + key-name = "mac_bt"; + key-device = "normal"; + key-permit = "read","write","del"; + key-type = "mac"; + }; + keysn_5:key_5{ + key-name = "mac_wifi"; + key-device = "normal"; + key-permit = "read","write","del"; + key-type = "mac"; + }; + keysn_6:key_6{ + key-name = "hdcp2_tx"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_7:key_7{ + key-name = "hdcp2_rx"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_8:key_8{ + key-name = "widevinekeybox"; + key-device = "secure"; + key-type = "sha1"; + key-permit = "read","write","del"; + }; + keysn_9:key_9{ + key-name = "deviceid"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_10:key_10{ + key-name = "hdcp22_fw_private"; + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_11:key_11{ + key-name = "hdcp22_rx_private"; + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_12:key_12{ + key-name = "hdcp22_rx_fw"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_13:key_13{ + key-name = "hdcp14_rx"; + key-device = "normal"; + key-type = "sha1"; + key-permit = "read","write","del"; + }; + keysn_14:key_14{ + key-name = "prpubkeybox";// PlayReady + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_15:key_15{ + key-name = "prprivkeybox";// PlayReady + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_16:key_16{ + key-name = "lcd"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_17:key_17{ + key-name = "lcd_extern"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_18:key_18{ + key-name = "backlight"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + }; /* End unifykey */ + + vout { + compatible = "amlogic, vout"; + dev_name = "vout"; + status = "okay"; + fr_auto_policy = <0>; + }; + + dvb { + compatible = "amlogic, dvb"; + dev_name = "dvb"; + status = "okay"; + fe0_mode = "internal"; + fe0_tuner = <&tuner>; + + /*"parallel","serial","disable"*/ + ts2 = "parallel"; + ts2_control = <0>; + ts2_invert = <0>; + interrupts = <0 23 1 + 0 5 1 + 0 53 1 + 0 19 1 + 0 25 1 + 0 18 1 + 0 24 1>; + interrupt-names = "demux0_irq", + "demux1_irq", + "demux2_irq", + "dvr0_irq", + "dvr1_irq", + "dvrfill0_fill", + "dvrfill1_flush"; + clocks = <&clkc CLKID_DEMUX + &clkc CLKID_ASYNC_FIFO + &clkc CLKID_AHB_ARB0 + &clkc CLKID_DOS_PARSER>; + clock-names = "demux", "asyncfifo", "ahbarb0", "uparsertop"; + }; + + meson_sensor: sensor@0 { + compatible = "amlogic, aml-thermal"; + #thermal-sensor-cells = <1>; + cooling_devices { + cpufreq_cool_cluster0 { + min_state = <1000000>; + dyn_coeff = <140>; + cluster_id = <0>; + node_name = "cpus"; + device_type = "cpufreq"; + }; + cpucore_cool_cluster0 { + min_state = <1>; + dyn_coeff = <0>; + cluster_id = <0>; + node_name = "cpu_core_cluster0"; + device_type = "cpucore"; + }; + gpufreq_cool { + min_state = <400>; + dyn_coeff = <437>; + cluster_id = <0>; + node_name = "mali"; + device_type = "gpufreq"; + }; + gpucore_cool { + min_state = <1>; + dyn_coeff = <0>; + cluster_id = <0>; + node_name = "thermal_gpu_cores"; + device_type = "gpucore"; + }; + }; + cpu_cluster0:cpu_core_cluster0 { + #cooling-cells = <2>; /* min followed by max */ + }; + gpucore:thermal_gpu_cores { + #cooling-cells = <2>; /* min followed by max */ + }; + }; + + dtv-demod { + compatible = "amlogic, ddemod-txl"; + status = "okay"; + + pinctrl-names = "dtvdemod_agc_pins"; + pinctrl-0 = <&dtvdemod_agc_pins>; + + clocks = <&clkc CLKID_DAC_CLK>; + clock-names = "vdac_clk_gate"; + + reg = <0x0 0xc8844000 0x0 0x2000 /*dtv demod base*/ + 0x0 0xc883c000 0x0 0x2000 /*hiu reg base*/ + 0x0 0xc8100000 0x0 0x1000 /*io_aobus_base*/ + 0x0 0xc1104400 0x0 0x1000 /*reset*/ + >; + /*move from dvbfe*/ + dtv_demod0_mem = <0>; // need move to aml_dtv_demod ? + spectrum = <1>; + cma_flag = <1>; + cma_mem_size = <8>; + memory-region = <&demod_cma_reserved>;//<&demod_reserved>; + }; + + thermal-zones { + soc_thermal { + polling-delay = <1000>; + polling-delay-passive = <100>; + sustainable-power = <2150>; + thermal-sensors = <&meson_sensor 3>; + + trips { + switch_on: trip-point@0 { + temperature = <70000>; + hysteresis = <1000>; + type = "passive"; + }; + control: trip-point@1 { + temperature = <80000>; + hysteresis = <1000>; + type = "passive"; + }; + hot: trip-point@2 { + temperature = <85000>; + hysteresis = <5000>; + type = "hot"; + }; + critical: trip-point@3 { + temperature = <260000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + + cooling-maps { + cpufreq_cooling_map { + trip = <&control>; + cooling-device = <&cpus 0 4>; + contribution = <1024>; + }; + cpucore_cooling_map { + trip = <&control>; + cooling-device = <&cpu_cluster0 0 3>; + contribution = <1024>; + }; + gpufreq_cooling_map { + trip = <&control>; + cooling-device = <&gpu 0 4>; + contribution = <1024>; + }; + gpucore_cooling_map { + trip = <&control>; + cooling-device = <&gpucore 0 2>; + contribution = <1024>; + }; + }; + }; + }; + + /* start AUDIO_RELATED */ + i2s_dai: I2S { + #sound-dai-cells = <0>; + compatible = "amlogic, aml-i2s-dai"; + clocks = < + &clkc CLKID_MPLL3 + &clkc CLKID_AMCLK_COMP + &clkc CLKID_AIU_GLUE + &clkc CLKID_I2S_OUT + &clkc CLKID_AMCLK_MEASURE + &clkc CLKID_AIFIFO2 + &clkc CLKID_MIXER + &clkc CLKID_MIXER_IFACE + &clkc CLKID_ADC + &clkc CLKID_AIU_TOP + &clkc CLKID_AOCLK_GATE + &clkc CLKID_I2S_SPDIF + >; + clock-names = + "mpll", + "mclk", + "top_glue", + "i2s_out", + "amclk_measure", + "aififo2", + "aud_mixer", + "mixer_reg", + "adc", + "top_level", + "aoclk", + "aud_in"; + }; + + spdif_dai: SPDIF { + #sound-dai-cells = <0>; + compatible = "amlogic, aml-spdif-dai"; + clocks = < + &clkc CLKID_MPLL1 + &clkc CLKID_IEC958_INT_COMP + &clkc CLKID_AMCLK_COMP + &clkc CLKID_IEC958_MUX + &clkc CLKID_CLK81 + &clkc CLKID_IEC958 + &clkc CLKID_IEC958_GATE + >; + clock-names = + "mpll1", + "i958", + "mclk", + "spdif", + "clk_81", + "iec958", + "iec958_amclk"; + }; + + pcm_dai: PCM { + #sound-dai-cells = <0>; + compatible = "amlogic, aml-pcm-dai"; + pinctrl-names = "audio_pcm"; + /* disable pcm pin mux temporary, enable it if necessary */ + /*pinctrl-0 = <&aml_audio_pcm>;*/ + clocks = < + &clkc CLKID_MPLL0 + &clkc CLKID_PCM_MCLK_COMP + &clkc CLKID_PCM_SCLK_COMP + >; + clock-names = "mpll0", "pcm_mclk", "pcm_sclk"; + pcm_mode = <1>; /* 0=slave mode, 1=master mode */ + }; + + i2s_plat: i2s_platform { + compatible = "amlogic, aml-i2s"; + interrupts = <0 29 1>; + }; + + pcm_plat: pcm_platform { + compatible = "amlogic, aml-pcm"; + }; + + spdif_codec: spdif_codec { + #sound-dai-cells = <0>; + compatible = "amlogic, aml-spdif-codec"; + status = "okay"; + pinctrl-names = "audio_spdif_out"; + pinctrl-0 = <&audio_spdif_out_pins>; + }; + + pcm_codec: pcm_codec { + #sound-dai-cells = <0>; + compatible = "amlogic, pcm2BT-codec"; + status = "okay"; + }; + /* endof AUDIO MESON8 DEVICES */ + + /* AUDIO board specific */ + dummy_codec:dummy { + #sound-dai-cells = <0>; + compatible = "amlogic, aml_dummy_codec"; + status = "disabled"; + }; + + amlogic_codec:t9015S { + #sound-dai-cells = <0>; + compatible = "amlogic, aml_codec_T9015S"; + status = "okay"; + reg = <0x0 0xc8832000 0x0 0x14>; + }; + + aml_snd_tv { + compatible = "amlogic, txl-snd-tv"; + status = "okay"; + aml-sound-card,format = "i2s"; + aml_sound_card,name = "AML-TVAUDIO"; + pinctrl-names = "audio_i2s"; + pinctrl-0 = <&aml_audio_i2s>; + /*avout mute gpio*/ + mute_gpio-gpios = <&gpio GPIODV_11 GPIO_ACTIVE_HIGH>; + sleep_time = <20>; + aux_dev = <&tas5707>; + cpu_list = <&cpudai0 &cpudai1 &cpudai2>; + codec_list = <&codec0 &codec1 &codec2>; + plat_list = <&i2s_plat &i2s_plat &pcm_plat>; + cpudai0: cpudai0 { + sound-dai = <&i2s_dai>; + }; + cpudai1: cpudai1 { + sound-dai = <&spdif_dai>; + }; + cpudai2: cpudai2 { + sound-dai = <&pcm_dai>; + }; + codec0: codec0 { + sound-dai = <&amlogic_codec>; + }; + codec1: codec1 { + sound-dai = <&spdif_codec>; + }; + codec2: codec2 { + sound-dai = <&pcm_codec>; + }; + Channel_Mask { + /*i2s has 4 pins, 8channel, mux output*/ + Speaker1_Channel_Mask = "i2s_2/3"; + DAC0_Channel_Mask = "i2s_0/1"; + }; + }; + + amaudio2 { + compatible = "amlogic, aml_amaudio2"; + status = "okay"; + interrupts = <0 48 1>; + }; + /* end of AUDIO_RELATED */ + + wifi { + compatible = "amlogic, aml_wifi"; + status = "okay"; + power_on_pin = <&gpio_ao GPIOAO_5 GPIO_ACTIVE_HIGH>; + }; +}; /* end of / */ + +&pinctrl_periphs { + /* start AUDIO_RELATED */ + /*i2s*/ + aml_audio_i2s: aml_audio_i2s { + mux { + groups = "i2s_amclk_z", + "i2s_aoclk_out_z", + "i2s_lrclk_out_z" + /*,"i2s_out_ch01_z"*/ + ,"i2s_out_ch23" + ; + function = "i2s"; + }; + }; + + /*spdif*/ + audio_spdif_out_pins: audio_spdif_out_pins { + mux { + groups = "spdif_out"; + function = "spdif_out"; + }; + }; + + /*pcm*/ + aml_audio_pcm: aml_audio_pcm { + mux { + groups = + "pcm_clk_a", + "pcm_fs_a", + "pcm_in_a", + "pcm_out_a"; + function = "pcm_a"; + }; + }; + /* end AUDIO_RELATED */ + + /*lcd_extern*/ + lcd_extern_off_pins:lcd_extern_off_pin { + mux { + pins = "GPIOH_2", + "GPIOH_3"; + function = "gpio_periphs"; + /*output-high;*/ + output-low; + /*input-enable;*/ + }; + }; + + /*backlight*/ + bl_pwm_off_pins:bl_pwm_off_pin { + mux { + pins = "GPIOZ_6"; + function = "gpio_periphs"; + output-low; + }; + }; + bl_pwm_combo_off_pins:bl_pwm_combo_off_pin { + mux { + pins = "GPIOZ_6", + "GPIOZ_7"; + function = "gpio_periphs"; + output-low; + }; + }; +}; + +&i2c0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_z_pins>; + + /* start AUDIO_RELATED */ + tas5707: tas5707@36 { + #sound-dai-cells = <0>; + compatible = "ti,tas5707"; + status = "okay"; + codec_name = "tas5707"; + reg = <0x1B>; + reset_pin = <&gpio GPIOZ_13 GPIO_ACTIVE_LOW>; + eq_enable = <0>; + drc_enable = <0>; + }; + /* end AUDIO_RELATED */ +}; + + +&i2c1 { + status = "okay"; + clock-frequency = <300000>; + pinctrl-names="default"; + pinctrl-0=<&i2c1_dv_pins>; +}; + +&i2c2 { + status = "okay"; + pinctrl-names="default"; + pinctrl-0=<&i2c2_h_pins>; + + lcd_extern_i2c0: lcd_extern_i2c@0 { + compatible = "lcd_ext, i2c"; + dev_name = "i2c_T5800Q"; + reg = <0x1c>; + status = "okay"; + }; +}; + +&dwc3 { + status = "okay"; +}; + +&usb2_phy { + status = "okay"; +}; + +&usb3_phy { + status = "okay"; +}; + +&dwc2_a { + status = "okay"; + /** 0: normal, 1: otg+dwc3 host only, 2: otg+dwc3 device only*/ + controller-type = <1>; +}; + +&audio_data{ + status = "okay"; +}; + +&pwm_ab { + status = "okay"; +}; + +&pwm_cd { + status = "okay"; +}; + +ðmac { + status = "okay"; +}; + +&spicc { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&spicc_pins>; + cs-gpios = <&gpio GPIOZ_3 0>; +}; diff --git a/arch/arm64/boot/dts/amlogic/txlx_t962e_r321.dts b/arch/arm64/boot/dts/amlogic/txlx_t962e_r321.dts index 4b5bfa958e20..752a88c61a29 100644 --- a/arch/arm64/boot/dts/amlogic/txlx_t962e_r321.dts +++ b/arch/arm64/boot/dts/amlogic/txlx_t962e_r321.dts @@ -212,13 +212,13 @@ }; }; - dummy-battery { + amlogic_battery:dummy-battery { compatible = "amlogic, dummy-battery"; - status = "okay"; + status = "disabled"; }; - dummy-charger { + amlogic_charger:dummy-charger { compatible = "amlogic, dummy-charger"; - status = "okay"; + status = "disabled"; }; ethmac: ethernet@0xff3f0000 { @@ -791,7 +791,7 @@ compatible = "amlogic, unifykey"; status = "okay"; - unifykey-num = <18>; + unifykey-num = <21>; unifykey-index-0 = <&keysn_0>; unifykey-index-1 = <&keysn_1>; unifykey-index-2 = <&keysn_2>; @@ -810,6 +810,9 @@ unifykey-index-15 = <&keysn_15>; unifykey-index-16 = <&keysn_16>; unifykey-index-17 = <&keysn_17>; + unifykey-index-18 = <&keysn_18>; + unifykey-index-19 = <&keysn_19>; + unifykey-index-20 = <&keysn_20>; keysn_0: key_0{ key-name = "usid"; @@ -906,6 +909,21 @@ key-device = "normal"; key-permit = "read","write","del"; }; + keysn_18:key_18{ + key-name = "hdcp22_rprx_fw"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_19:key_19{ + key-name = "hdcp22_rprp_fw"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_20:key_20{ + key-name = "hdcp22_rp_private"; + key-device = "secure"; + key-permit = "read","write","del"; + }; }; /* End unifykey */ cvbsout { @@ -948,7 +966,7 @@ */ ic_type = <6>; //gpio_i2c_en = <0>; - //repeater_tx = <0x1>; + repeater_tx = <0x1>; //#address-cells = <2>; //#size-cells = <2>; //ranges; @@ -983,6 +1001,7 @@ cec_osd_string = "AML_TV"; /* Max Chars: 14 */ port_num = <4>; /*all port number*/ /*ee_cec;*/ + cec_sel = <2>; output = <1>; /*output port number*/ /*arc support port:bit 0-3, according to portmap*/ arc_port_mask = <0x8>; @@ -990,9 +1009,9 @@ 0 199 1>; interrupt-names = "hdmi_aocecb","hdmi_aocec"; pinctrl-names = "default","hdmitx_aocecb","cec_pin_sleep"; - pinctrl-0=<&hdmitx_aocec>; - pinctrl-1=<&hdmitx_aocecb>; - pinctrl-2=<&hdmitx_aocecb>; + pinctrl-0=<&hdmitx_aocec &hdmitx_aocecb1>; + pinctrl-1=<&hdmitx_aocec &hdmitx_aocecb1>; + pinctrl-2=<&hdmitx_aocec &hdmitx_aocecb1>; reg = <0x0 0xFF80023c 0x0 0x4 0x0 0xFF800000 0x0 0x400>; reg-names = "ao_exit","ao"; diff --git a/arch/arm64/boot/dts/amlogic/txlx_t962x_r311_1g.dts b/arch/arm64/boot/dts/amlogic/txlx_t962x_r311_1g.dts index 5c07b358ea20..c3f97d50c934 100644 --- a/arch/arm64/boot/dts/amlogic/txlx_t962x_r311_1g.dts +++ b/arch/arm64/boot/dts/amlogic/txlx_t962x_r311_1g.dts @@ -37,6 +37,8 @@ serial2 = &uart_B; serial3 = &uart_C; serial4 = &uart_AO_B; + spi0 = &spicc0; + spi1 = &spicc1; }; ion_dev { @@ -170,14 +172,14 @@ }; }; - dummy-battery { + amlogic_battery:dummy-battery { compatible = "amlogic, dummy-battery"; - status = "okay"; + status = "disabled"; }; - dummy-charger { + amlogic_charger:dummy-charger { compatible = "amlogic, dummy-charger"; - status = "okay"; + status = "disabled"; }; /* for external keypad */ @@ -1274,8 +1276,8 @@ Channel_Mask { /*i2s has 4 pins, 8channel, mux output*/ Speaker0_Channel_Mask = "i2s_2/3"; - DAC0_Channel_Mask = "i2s_2/3"; - DAC1_Channel_Mask = "i2s_2/3"; + DAC0_Channel_Mask = "i2s_4/5"; + DAC1_Channel_Mask = "i2s_4/5"; EQ_DRC_Channel_Mask = "i2s_2/3"; Spdif_samesource_Channel_Mask = "i2s_0/1"; }; diff --git a/arch/arm64/boot/dts/amlogic/txlx_t962x_r311_2g.dts b/arch/arm64/boot/dts/amlogic/txlx_t962x_r311_2g.dts index 52653e25751e..f1aa69e21e45 100644 --- a/arch/arm64/boot/dts/amlogic/txlx_t962x_r311_2g.dts +++ b/arch/arm64/boot/dts/amlogic/txlx_t962x_r311_2g.dts @@ -37,6 +37,8 @@ serial2 = &uart_B; serial3 = &uart_C; serial4 = &uart_AO_B; + spi0 = &spicc0; + spi1 = &spicc1; }; ion_dev { @@ -170,14 +172,14 @@ }; }; - dummy-battery { + amlogic_battery:dummy-battery { compatible = "amlogic, dummy-battery"; - status = "okay"; + status = "disabled"; }; - dummy-charger { + amlogic_charger:dummy-charger { compatible = "amlogic, dummy-charger"; - status = "okay"; + status = "disabled"; }; /* for external keypad */ @@ -1280,8 +1282,8 @@ Channel_Mask { /*i2s has 4 pins, 8channel, mux output*/ Speaker0_Channel_Mask = "i2s_2/3"; - DAC0_Channel_Mask = "i2s_2/3"; - DAC1_Channel_Mask = "i2s_2/3"; + DAC0_Channel_Mask = "i2s_4/5"; + DAC1_Channel_Mask = "i2s_4/5"; EQ_DRC_Channel_Mask = "i2s_2/3"; Spdif_samesource_Channel_Mask = "i2s_0/1"; }; diff --git a/arch/arm64/boot/dts/amlogic/txlx_t962x_r311_720p.dts b/arch/arm64/boot/dts/amlogic/txlx_t962x_r311_720p.dts index d27582906915..f1ab9ec83930 100644 --- a/arch/arm64/boot/dts/amlogic/txlx_t962x_r311_720p.dts +++ b/arch/arm64/boot/dts/amlogic/txlx_t962x_r311_720p.dts @@ -37,6 +37,8 @@ serial2 = &uart_B; serial3 = &uart_C; serial4 = &uart_AO_B; + spi0 = &spicc0; + spi1 = &spicc1; }; ion_dev { @@ -170,14 +172,14 @@ }; }; - dummy-battery { + amlogic_battery:dummy-battery { compatible = "amlogic, dummy-battery"; - status = "okay"; + status = "disabled"; }; - dummy-charger { + amlogic_charger:dummy-charger { compatible = "amlogic, dummy-charger"; - status = "okay"; + status = "disabled"; }; /* for external keypad */ @@ -1273,8 +1275,8 @@ Channel_Mask { /*i2s has 4 pins, 8channel, mux output*/ Speaker0_Channel_Mask = "i2s_2/3"; - DAC0_Channel_Mask = "i2s_2/3"; - DAC1_Channel_Mask = "i2s_2/3"; + DAC0_Channel_Mask = "i2s_4/5"; + DAC1_Channel_Mask = "i2s_4/5"; EQ_DRC_Channel_Mask = "i2s_2/3"; Spdif_samesource_Channel_Mask = "i2s_0/1"; }; diff --git a/arch/arm64/boot/dts/amlogic/txlx_t962x_r314.dts b/arch/arm64/boot/dts/amlogic/txlx_t962x_r314.dts new file mode 100644 index 000000000000..efc13a566b46 --- /dev/null +++ b/arch/arm64/boot/dts/amlogic/txlx_t962x_r314.dts @@ -0,0 +1,1646 @@ +/* + * arch/arm64/boot/dts/amlogic/txlx_t962x_r311_1g.dts + * + * Copyright (C) 2017 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +/dts-v1/; +#include +#include + +#include "mesontxlx.dtsi" +#include "partition_mbox_normal.dtsi" +#include "mesontxlx_r311-panel.dtsi" + +/ { + model = "Amlogic"; + amlogic-dt-id = "txlx_t962x_r314"; + compatible = "amlogic, txlx"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + serial0 = &uart_AO; + serial1 = &uart_A; + serial2 = &uart_B; + serial3 = &uart_C; + serial4 = &uart_AO_B; + spi0 = &spicc0; + spi1 = &spicc1; + }; + + ion_dev { + compatible = "amlogic, ion_dev"; + memory-region = <&ion_reserved>; + }; + + memory@00000000 { + device_type = "memory"; + linux,usable-memory = <0x0 0x100000 0x0 0x5ff00000>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + /* global autoconfigured region for contiguous allocations */ + ramoops@0x07400000 { + compatible = "ramoops"; + reg = <0x0 0x07400000 0x0 0x00100000>; + record-size = <0x8000>; + console-size = <0x8000>; + ftrace-size = <0x0>; + pmsg-size = <0x8000>; + }; + secmon_reserved:linux,secmon { + compatible = "shared-dma-pool"; + reusable; + size = <0x0 0x400000>; + alignment = <0x0 0x400000>; + alloc-ranges = <0x0 0x05000000 0x0 0x400000>; + }; + + //secos_reserved:linux,secos { + // status = "disabled"; + // compatible = "amlogic, aml_secos_memory"; + // reg = <0x0 0x05300000 0x0 0x2000000>; + // no-map; + //}; + + + + logo_reserved:linux,meson-fb { + compatible = "shared-dma-pool"; + reusable; + size = <0x0 0x800000>; + alignment = <0x0 0x400000>; + alloc-ranges = <0x0 0x5f800000 0x0 0x800000>; + }; + + //carveout_reserved:linux,carveout-reserve { + // compatible = "amlogic, idev-mem"; + // size = <0x0 0x1000>; + //}; + + ion_reserved:linux,ion-dev { + compatible = "shared-dma-pool"; + reusable; + size = <0x0 0x4C00000>; + alignment = <0x0 0x400000>; + }; + + + /*di CMA pool */ + di_cma_reserved:linux,di_cma { + compatible = "shared-dma-pool"; + reusable; + /* buffer_size = 3621952(yuv422 8bit) + * | 4736064(yuv422 10bit) + * | 4179008(yuv422 10bit full pack mode) + * 10x3621952=34.6M(0x23) support 8bit + * 10x4736064=45.2M(0x2e) support 12bit + * 10x4179008=40M(0x28) support 10bit + */ + size = <0x0 0x02800000>; + alignment = <0x0 0x400000>; + }; + + /* POST PROCESS MANAGER */ + ppmgr_reserved:linux,ppmgr { + compatible = "amlogic, ppmgr_memory"; + size = <0x0 0x0>; + }; + + codec_mm_cma:linux,codec_mm_cma { + compatible = "shared-dma-pool"; + reusable; + /* ion_codec_mm max can alloc size 80M*/ + size = <0x0 0xd000000>; + alignment = <0x0 0x400000>; + linux,contiguous-region; + }; + + picdec_cma_reserved:linux,picdec { + compatible = "shared-dma-pool"; + reusable; + size = <0x0 0x0>; + alignment = <0x0 0x0>; + linux,contiguous-region; + }; + + /* codec shared reserved */ + codec_mm_reserved:linux,codec_mm_reserved { + compatible = "amlogic, codec-mm-reserved"; + size = <0x0 0x0>; + alignment = <0x0 0x100000>; + //no-map; + }; + + demod_cma_reserved:linux,demod_cma { + compatible = "shared-dma-pool"; + reusable; + /* 5M */ + size = <0x0 0x0800000>; + alignment = <0x0 0x400000>; + }; + + /* vdin1 CMA pool */ + vdin1_cma_reserved:linux,vdin1_cma { + compatible = "shared-dma-pool"; + linux,phandle = <5>; + reusable; + /* 1920x1080x2x4 =16+4 M */ + size = <0x0 0x01400000>; + alignment = <0x0 0x400000>; + }; + + /*vbi reserved mem*/ + vbi_reserved:linux,vbi { + compatible = "amlogic, vbi-mem"; + size = <0x0 0x100000>; + }; + }; + + amlogic_battery:dummy-battery { + compatible = "amlogic, dummy-battery"; + status = "disabled"; + }; + + amlogic_charger:dummy-charger { + compatible = "amlogic, dummy-charger"; + status = "disabled"; + }; + + /* for external keypad */ + adc_keypad { + compatible = "amlogic, adc_keypad"; + status = "okay"; + key_name = "power","up","down","enter","left","right","home"; + key_num = <7>; + io-channels = <&saradc SARADC_CH2>, + <&saradc SARADC_CH3>; + io-channel-names = "key-chan-2", "key-chan-3"; + key_chan = ; + key_code = <116 103 108 28 105 106 102>; + key_val = <0 143 266 389 512 143 266>; //val=voltage/1800mV*1023 + key_tolerance = <40 40 40 40 40 40 40>; + }; + + gpioleds { + compatible = "gpio-leds"; + status = "okay"; + + sys { + label = "sysled"; + gpios = <&gpio_ao GPIOAO_3 GPIO_ACTIVE_HIGH>; + default-state = "on"; /* keep/on/off */ + linux,default-trigger = "none"; + }; + + }; + + pwmleds { + compatible = "pwm-leds"; + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&pwmleds_pins>; + + sys { + active-low; + label = "sysled"; + max-brightness = <255>; + pwms = <&pwm_AO_ab 0 50000 0>; + }; + }; + + ethmac: ethernet@0xff3f0000 { + compatible = "amlogic, gxbb-eth-dwmac"; + status = "okay"; + reg = <0x0 0xff3f0000 0x0 0x10000 + 0x0 0xff634540 0x0 0x8 + 0x0 0xff634558 0x0 0xc + 0x0 0xffd01084 0x0 0x4>; + interrupts = <0 8 1 + 0 9 1>; + + phy-mode= "rmii"; + mc_val_internal_phy = <0x1804>; + mc_val_external_phy = <0x1621>; + interrupt-names = "macirq", + "phyirq"; + clocks = <&clkc CLKID_ETH_CORE>; + clock-names = "ethclk81"; + internal_phy = <1>; + }; + + vout { + compatible = "amlogic, vout"; + dev_name = "vout"; + status = "okay"; + fr_auto_policy = <0>; + }; + + meson-fb { + compatible = "amlogic, meson-txlx"; + memory-region = <&logo_reserved>; + dev_name = "meson-fb"; + status = "okay"; + interrupts = <0 3 1 + 0 89 1>; + interrupt-names = "viu-vsync", "rdma"; + mem_size = <0x00800000 0x01800000 0x00100000>; + /* uboot logo,fb0/fb1 memory size,if afbcd fb0=0x01851000*/ + display_mode_default = "1080p60hz"; + /* 0:VPU free scale 1:OSD free scale 2:OSD super scale */ + scale_mode = <1>; + /* 1920*1080*4*3 = 0x17BB000 */ + display_size_default = <1920 1080 1920 3240 32>; + pxp_mode = <0>; /** 0:normal mode 1:pxp mode */ + logo_addr = "0x5f800000"; + }; + + ge2d { + compatible = "amlogic, ge2d-txlx"; + dev_name = "ge2d"; + status = "okay"; + interrupts = <0 150 1>; + interrupt-names = "ge2d"; + clocks = <&clkc CLKID_VAPB_MUX>, + <&clkc CLKID_G2D>, + <&clkc CLKID_GE2D_GATE>; + clock-names = "clk_vapb_0", + "clk_ge2d", + "clk_ge2d_gate"; + reg = <0x0 0xff940000 0x0 0x10000>; + }; + + codec_io { + compatible = "amlogic, codec_io"; + status = "okay"; + #address-cells=<2>; + #size-cells=<2>; + ranges; + io_cbus_base{ + reg = <0x0 0xffd00000 0x0 0x100000>; + }; + io_dos_base{ + reg = <0x0 0xff620000 0x0 0x10000>; + }; + io_hiubus_base{ + reg = <0x0 0xff63c000 0x0 0x2000>; + }; + io_aobus_base{ + reg = <0x0 0xff800000 0x0 0x10000>; + }; + io_vcbus_base{ + reg = <0x0 0xff900000 0x0 0x40000>; + }; + io_dmc_base{ + reg = <0x0 0xff638000 0x0 0x2000>; + }; + }; + + codec_mm { + compatible = "amlogic, codec, mm"; + memory-region = <&codec_mm_cma &codec_mm_reserved>; + dev_name = "codec_mm"; + status = "okay"; + }; + + mesonstream { + compatible = "amlogic, codec, streambuf"; + dev_name = "mesonstream"; + status = "okay"; + clocks = <&clkc CLKID_DOS_PARSER + &clkc CLKID_DEMUX + &clkc CLKID_DOS + &clkc CLKID_CLK81 + &clkc CLKID_VDEC_MUX + &clkc CLKID_HCODEC_MUX + &clkc CLKID_HEVC_MUX>; + clock-names = "parser_top", + "demux", + "vdec", + "clk_81", + "clk_vdec_mux", + "clk_hcodec_mux", + "clk_hevc_mux"; + }; + + vdec { + compatible = "amlogic, vdec"; + dev_name = "vdec.0"; + status = "okay"; + interrupts = <0 3 1 + 0 23 1 + 0 32 1 + 0 43 1 + 0 44 1 + 0 45 1>; + interrupt-names = "vsync", + "demux", + "parser", + "mailbox_0", + "mailbox_1", + "mailbox_2"; + }; + + meson-amvideom { + compatible = "amlogic, amvideom"; + dev_name = "amvideom"; + status = "okay"; + interrupts = <0 3 1>; + interrupt-names = "vsync"; + }; + + + + amvideocap { + compatible = "amlogic, amvideocap"; + dev_name = "amvideocap.0"; + status = "disabled"; + max_size = <8>;//8M + }; + + picdec { + compatible = "amlogic, picdec"; + memory-region = <&picdec_cma_reserved>; + dev_name = "picdec"; + status = "okay"; + }; + + ppmgr { + compatible = "amlogic, ppmgr"; + memory-region = <&ppmgr_reserved>; + dev_name = "ppmgr"; + status = "okay"; + }; + + deinterlace { + compatible = "amlogic, deinterlace"; + status = "okay"; + /* 0:use reserved; 1:use cma; 2:use cma as reserved */ + flag_cma = <1>; + //memory-region = <&di_reserved>; + memory-region = <&di_cma_reserved>; + interrupts = <0 46 1 + 0 6 1>; + interrupt-names = "de_irq"; + clocks = <&clkc CLKID_VPU_MUX>, + <&clkc CLKID_FCLK_DIV4>, + <&clkc CLKID_VPU_CLKB_TMP_COMP>, + <&clkc CLKID_VPU_CLKB_COMP>; + clock-names = "vpu_mux", + "fclk_div4", + "vpu_clkb_tmp_composite", + "vpu_clkb_composite"; + clock-range = <250 500>; + /* buffer-size = <3621952>;(yuv422 8bit) */ + buffer-size = <4179008>;/*yuv422 fullpack*/ + /* reserve-iomap = "true"; */ + /* if enable nr10bit, set nr10bit-support to 1 */ + nr10bit-support = <1>; + }; + ionvideo { + compatible = "amlogic, ionvideo"; + dev_name = "ionvideo"; + status = "okay"; + }; + + amlvideo { + compatible = "amlogic, amlvideo"; + dev_name = "amlvideo"; + status = "okay"; + }; + + amlvideo2_0 { + compatible = "amlogic, amlvideo2"; + dev_name = "amlvideo2"; + status = "okay"; + amlvideo2_id = <0>; + cma_mode = <1>; + }; + + amlvideo2_1 { + compatible = "amlogic, amlvideo2"; + dev_name = "amlvideo2"; + status = "okay"; + amlvideo2_id = <1>; + cma_mode = <1>; + }; + + hdmirx { + compatible = "amlogic, hdmirx_txlx"; + #address-cells=<1>; + #size-cells=<1>; + dev_name = "hdmirx"; + status = "okay"; + pinctrl-names = "hdmirx_pins"; + pinctrl-0 = <&hdmirx_a_mux &hdmirx_b_mux + &hdmirx_c_mux &hdmirx_d_mux>; + repeat = <0>; + interrupts = <0 56 1>; + clocks = <&clkc CLKID_HDMIRX_MODET_COMP>, + <&clkc CLKID_HDMIRX_CFG_COMP>, + <&clkc CLKID_HDMIRX_ACR_COMP>, + <&clkc CLKID_HDMIRX_AUDMEAS_COMP>, + <&xtal>, + <&clkc CLKID_FCLK_DIV5>, + <&clkc CLKID_FCLK_DIV7>, + <&clkc CLKID_HDCP22_SKP_COMP>, + <&clkc CLKID_HDCP22_ESM_COMP>; + // <&clkc CLK_AUD_PLL2FS>, + // <&clkc CLK_AUD_PLL4FS>, + // <&clkc CLK_AUD_OUT>; + clock-names = "hdmirx_modet_clk", + "hdmirx_cfg_clk", + "hdmirx_acr_ref_clk", + "hdmirx_audmeas_clk", + "xtal", + "fclk_div5", + "fclk_div7", + "hdcp_rx22_skp", + "hdcp_rx22_esm"; + // "hdmirx_aud_pll2fs", + // "hdmirx_aud_pll4f", + // "clk_aud_out"; + hdmirx_id = <0>; + en_4k_2_2k = <0>; + hpd_low_cec_off = <1>; + /* bit4: enable feature, bit3~0: port number */ + disable_port = <0x0>; + reg = <0x0 0xffd26000 0x0 0xa00000 + 0x0 0xff63C000 0x0 0x2000 + 0x0 0xffe0d000 0x0 0x2000 + 0x0 0xff63e000 0x0 0x2000 + 0x0 0x0 0x0 0x0 + 0x0 0xff634400 0x0 0x2000 + 0x0 0xff646000 0x0 0x2000>; + }; + + vdin0 { + compatible = "amlogic, vdin"; + /*memory-region = <&vdin0_cma_reserved>;*/ + dev_name = "vdin0"; + status = "okay"; + reserve-iomap = "true"; + /*bit0:(1:share with codec_mm;0:cma alone)*/ + /*bit8:(1:alloc in discontinus way;0:alone in continuous way)*/ + flag_cma = <0x101>; + /* MByte, if 10bit disable: 64M(YUV422), + * if 10bit enable: 64*1.5 = 96M(YUV422) + * if support 4K2K-YUV444-10bit-WR:3840*2160*4*4 ~= 128M + * if support 4K2K-YUV444-10bit-WR:3840*2160*4*6 ~= 190M + * if support 4K2K-YUV422-10bit-wr:3840*2160*3*4 ~= 96M + * if support 4K2K-YUV422-8BIT-WR:3840*2160*2*4 ~= 64M + * if support 1080p-YUV422-8BIT-WR:1920*1080*2*4 ~= 16M + */ + cma_size = <190>; + interrupts = <0 83 1>; + rdma-irq = <2>; + clocks = <&clkc CLKID_FCLK_DIV5>, + <&clkc CLKID_VDIN_MEAS_COMP>; + clock-names = "fclk_div5", "cts_vdin_meas_clk"; + vdin_id = <0>; + /* vdin write mem color depth support: + * bit0:support 8bit + * bit1:support 9bit + * bit2:support 10bit + * bit3:support 12bit + * bit4:support yuv422 10bit full pack mode (from txl new add) + * bit8:use 8bit at 4k_50/60hz_10bit + * bit9:use 10bit at 4k_50/60hz_10bit + */ + tv_bit_mode = <0x215>; + }; + + vdin1 { + compatible = "amlogic, vdin"; + memory-region = <&vdin1_cma_reserved>; + dev_name = "vdin1"; + status = "okay"; + reserve-iomap = "true"; + flag_cma = <0>;/*1:share with codec_mm;0:cma alone*/ + interrupts = <0 85 1>; + rdma-irq = <4>; + clocks = <&clkc CLKID_FCLK_DIV5>, + <&clkc CLKID_VDIN_MEAS_COMP>; + clock-names = "fclk_div5", "cts_vdin_meas_clk"; + vdin_id = <1>; + /* vdin write mem color depth support: + * bit0:support 8bit + * bit1:support 9bit + * bit2:support 10bit + * bit3:support 12bit + */ + tv_bit_mode = <1>; + }; + + tvafe { + compatible = "amlogic, tvafe-txlx"; + /*memory-region = <&tvafe_cma_reserved>;*/ + dev_name = "tvafe"; + status = "okay"; + flag_cma = <1>;/*1:share with codec_mm;0:cma alone*/ + cma_size = <5>;/*MByte*/ + reg = <0x0 0xff642000 0x0 0x2000>;/*tvafe reg base*/ + reserve-iomap = "true"; + tvafe_id = <0>; + //pinctrl-names = "default"; + /*!!particular sequence, no more and no less!!!*/ + tvafe_pin_mux = < + 3 /* TVAFE_CVBS_IN2, CVBS_IN0 = 0 */ + 1 /* TVAFE_CVBS_IN0, CVBS_IN1 */ + 2 /* TVAFE_CVBS_IN1, CVBS_IN2 */ + 4 /* TVAFE_CVBS_IN3, CVBS_IN3 */ + >; + clocks = <&clkc CLKID_DAC_CLK>; + clock-names = "vdac_clk_gate"; + }; + + vbi { + compatible = "amlogic, vbi"; + memory-region = <&vbi_reserved>; + dev_name = "vbi"; + status = "okay"; + interrupts = <0 83 1>; + reserve-iomap = "true"; + }; + + tvafe_avin_detect { + compatible = "amlogic, tvafe_avin_detect"; + dev_name = "tvafe_avin_detect"; + status = "okay"; + device_mask = <1>;/*bit0:ch1;bit1:ch2*/ + interrupts = <0 12 1>, + <0 13 1>; + }; + + amlvecm { + compatible = "amlogic, vecm"; + dev_name = "aml_vecm"; + status = "okay"; + gamma_en = <1>;/*1:enabel ;0:disable*/ + wb_en = <1>;/*1:enabel ;0:disable*/ + cm_en = <1>;/*1:enabel ;0:disable*/ + wb_sel = <1>;/*1:mtx ;0:gainoff*/ + vlock_en = <1>;/*1:enable;0:disable*/ + vlock_mode = <0x4>; + /* vlock work mode: + *bit0:auto ENC + *bit1:auto PLL + *bit2:manual PLL + *bit3:manual ENC + *bit4:manual soft ENC + *bit5:manual MIX PLL ENC + */ + vlock_pll_m_limit = <1>; + vlock_line_limit = <3>; + }; + amdolby_vision { + compatible = "amlogic, dolby_vision_txlx"; + dev_name = "aml_amdolby_vision_driver"; + status = "okay"; + tv_mode = <1>;/*1:enabel ;0:disable*/ + }; + amvenc_avc { + compatible = "amlogic, amvenc_avc"; + //memory-region = <&amvenc_avc_reserved>; + //memory-region = <&avc_cma_reserved>; + dev_name = "amvenc_avc"; + status = "okay"; + interrupts = <0 45 1>; + interrupt-names = "mailbox_2"; + }; + + tuner: tuner { + status = "okay"; + tuner_name = "mxl661_tuner"; + tuner_i2c_adap = <&i2c1>; + tuner_i2c_addr = <0x60>; + tuner_xtal = <0>; /* 0: 16MHz, 1: 24MHz */ + tuner_xtal_mode = <0>; + /* NO_SHARE_XTAL(0) + * SLAVE_XTAL_SHARE(1) + */ + tuner_xtal_cap = <30>; /* when tuner_xtal_mode = 1, set 25 */ + }; + + atv-demod { + compatible = "amlogic, atv-demod"; + status = "okay"; + tuner = <&tuner>; + btsc_sap_mode = <1>; + /* pinctrl-names="atvdemod_agc_pins"; */ + /* pinctrl-0=<&atvdemod_agc_pins>; */ + reg = <0x0 0xff640000 0x0 0x2000 /* demod reg */ + 0x0 0xff63c000 0x0 0x2000 /* hiu reg */ + 0x0 0xff634000 0x0 0x2000 /* periphs reg */ + 0x0 0xff648000 0x0 0x2000>; /* audio reg */ + reg_23cf = <0x88188832>; + /*default:0x88188832;r840 on haier:0x48188832*/ + }; + + bt-dev { + compatible = "amlogic, bt-dev"; + dev_name = "bt-dev"; + status = "okay"; + power_down_disable = <1>; + gpio_reset = <&gpio_ao GPIOAO_8 GPIO_ACTIVE_HIGH>; + //gpio_en = <&gpio_ao GPIOAO_5 GPIO_ACTIVE_HIGH>; + }; + + rtc { + compatible = "amlogic, aml_vrtc"; + alarm_reg_addr = <0xff8000a8>; + timer_e_addr = <0xffd0f188>; + init_date = "2015/01/01"; + status = "okay"; + }; + + wifi { + compatible = "amlogic, aml_wifi"; + dev_name = "aml_wifi"; + status = "okay"; + interrupt_pin = <&gpio_ao GPIOAO_4 GPIO_ACTIVE_HIGH>; + interrupts = <0 68 4>; + irq_trigger_type = "GPIO_IRQ_HIGH"; + dhd_static_buf; + power_on_pin = <&gpio_ao GPIOAO_5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_32k_pins>; + pwm_config = <&wifi_pwm_conf>; + }; + + wifi_pwm_conf: wifi_pwm_conf { + pwm_channel1_conf { + pwms = <&pwm_cd MESON_PWM_1 30040 0>; + duty-cycle = <15020>; + times = <10>; + }; + pwm_channel2_conf { + pwms = <&pwm_cd MESON_PWM_3 30030 0>; + duty-cycle = <15015>; + times = <12>; + }; + }; + + sd_emmc_c: emmc@ffe07000 { + status = "okay"; + compatible = "amlogic, meson-mmc-txlx"; + reg = <0x0 0xffe07000 0x0 0x2000>; + interrupts = <0 218 1>; + pinctrl-names = "emmc_clk_cmd_pins", "emmc_all_pins"; + pinctrl-0 = <&emmc_clk_cmd_pins>; + pinctrl-1 = <&emmc_conf_pull_up &emmc_conf_pull_done>; + clocks = <&clkc CLKID_SD_EMMC_C>, + <&clkc CLKID_SD_EMMC_C_P0_COMP>, + <&clkc CLKID_FCLK_DIV2>, + <&clkc CLKID_FCLK_DIV5>, + <&xtal>; + clock-names = "core", "clkin0", "clkin1", "clkin2", "xtal"; + + bus-width = <8>; + cap-sd-highspeed; + cap-mmc-highspeed; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + + max-frequency = <200000000>; + non-removable; + disable-wp; + emmc { + status = "disabled"; + pinname = "emmc"; + ocr_avail = <0x200080>; /**VDD voltage 3.3 ~ 3.4 */ + caps = "MMC_CAP_8_BIT_DATA", + "MMC_CAP_MMC_HIGHSPEED", + "MMC_CAP_SD_HIGHSPEED", + "MMC_CAP_NONREMOVABLE", + "MMC_CAP_1_8V_DDR", + "MMC_CAP_HW_RESET", + "MMC_CAP_ERASE", + "MMC_CAP_CMD23"; + caps2 = "MMC_CAP2_HS200", "MMC_CAP2_HS400"; + f_min = <400000>; + f_max = <200000000>; + max_req_size = <0x20000>; /**128KB*/ + gpio_dat3 = <&gpio BOOT_3 GPIO_ACTIVE_HIGH>; + hw_reset = <&gpio BOOT_9 GPIO_ACTIVE_HIGH>; + card_type = <1>; + /* 1:mmc card(include eMMC), + * 2:sd card(include tSD) + */ + }; + }; + + sd_emmc_b: sd@ffe05000 { + status = "okay"; + compatible = "amlogic, meson-mmc-txlx"; + reg = <0x0 0xffe05000 0x0 0x2000>; + interrupts = <0 217 1>; + pinctrl-names = "sd_all_pins", + "sd_clk_cmd_pins", + "sd_1bit_pins", + "sd_clk_cmd_uart_pins", + "sd_1bit_uart_pins", + "sd_to_ao_uart_pins", + "ao_to_sd_uart_pins", + "ao_to_sd_jtag_pins", + "sd_to_ao_jtag_pins"; + pinctrl-0 = <&sd_all_pins>; + pinctrl-1 = <&sd_clk_cmd_pins>; + pinctrl-2 = <&sd_1bit_pins>; + pinctrl-3 = <&sd_to_ao_uart_clr_pins + &sd_clk_cmd_pins &ao_to_sd_uart_pins>; + pinctrl-4 = <&sd_to_ao_uart_clr_pins + &sd_1bit_pins &ao_to_sd_uart_pins>; + pinctrl-5 = <&sd_all_pins &sd_to_ao_uart_pins>; + pinctrl-6 = <&sd_to_ao_uart_clr_pins &ao_to_sd_uart_pins>; + pinctrl-7 = <&sd_to_ao_uart_clr_pins &ao_to_sd_uart_pins>; + pinctrl-8 = <&sd_all_pins &sd_to_ao_uart_pins>; + clocks = <&clkc CLKID_SD_EMMC_B>, + <&clkc CLKID_SD_EMMC_B_P0_COMP>, + <&clkc CLKID_FCLK_DIV2>, + <&clkc CLKID_FCLK_DIV5>, + <&xtal>; + clock-names = "core", "clkin0", "clkin1", "clkin2", "xtal"; + + bus-width = <4>; + cap-sd-highspeed; + max-frequency = <100000000>; + disable-wp; + sd { + status = "disabled"; + pinname = "sd"; + ocr_avail = <0x200080>; /**VDD voltage 3.3 ~ 3.4 */ + caps = "MMC_CAP_4_BIT_DATA", + "MMC_CAP_MMC_HIGHSPEED", + "MMC_CAP_SD_HIGHSPEED"; + /* "MMC_CAP_UHS_SDR12", + * "MMC_CAP_UHS_SDR25", + * "MMC_CAP_UHS_SDR50", + * "MMC_CAP_UHS_SDR104"; + */ + f_min = <400000>; + f_max = <200000000>; + max_req_size = <0x20000>; /**128KB*/ + gpio_dat3 = <&gpio GPIOC_4 GPIO_ACTIVE_HIGH>; + jtag_pin = <&gpio GPIOC_0 GPIO_ACTIVE_HIGH>; + gpio_cd = <&gpio GPIOH_10 GPIO_ACTIVE_HIGH>; + card_type = <5>; + /* 3:sdio device(ie:sdio-wifi), + * 4:SD combo (IO+mem) card + * 5:NON sdio device(means sd/mmc card) + */ + }; + }; + + unifykey { + compatible = "amlogic, unifykey"; + status = "okay"; + + unifykey-num = <20>; + unifykey-index-0 = <&keysn_0>; + unifykey-index-1 = <&keysn_1>; + unifykey-index-2 = <&keysn_2>; + unifykey-index-3 = <&keysn_3>; + unifykey-index-4 = <&keysn_4>; + unifykey-index-5 = <&keysn_5>; + unifykey-index-6 = <&keysn_6>; + unifykey-index-7 = <&keysn_7>; + unifykey-index-8 = <&keysn_8>; + unifykey-index-9 = <&keysn_9>; + unifykey-index-10= <&keysn_10>; + unifykey-index-11 = <&keysn_11>; + unifykey-index-12 = <&keysn_12>; + unifykey-index-13 = <&keysn_13>; + unifykey-index-14 = <&keysn_14>; + unifykey-index-15 = <&keysn_15>; + unifykey-index-16 = <&keysn_16>; + unifykey-index-17 = <&keysn_17>; + unifykey-index-18 = <&keysn_18>; + unifykey-index-19 = <&keysn_19>; + + keysn_0: key_0{ + key-name = "usid"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_1:key_1{ + key-name = "mac"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_2:key_2{ + key-name = "hdcp"; + key-device = "secure"; + key-type = "sha1"; + key-permit = "read","write","del"; + }; + keysn_3:key_3{ + key-name = "secure_boot_set"; + key-device = "efuse"; + key-permit = "write"; + }; + keysn_4:key_4{ + key-name = "mac_bt"; + key-device = "normal"; + key-permit = "read","write","del"; + key-type = "mac"; + }; + keysn_5:key_5{ + key-name = "mac_wifi"; + key-device = "normal"; + key-permit = "read","write","del"; + key-type = "mac"; + }; + keysn_6:key_6{ + key-name = "hdcp2_tx"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_7:key_7{ + key-name = "hdcp2_rx"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_8:key_8{ + key-name = "widevinekeybox"; + key-device = "secure"; + key-type = "sha1"; + key-permit = "read","write","del"; + }; + keysn_9:key_9{ + key-name = "deviceid"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_10:key_10{ + key-name = "hdcp22_fw_private"; + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_11:key_11{ + key-name = "hdcp22_rx_private"; + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_12:key_12{ + key-name = "hdcp22_rx_fw"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_13:key_13{ + key-name = "hdcp14_rx"; + key-device = "normal"; + key-type = "sha1"; + key-permit = "read","write","del"; + }; + keysn_14:key_14{ + key-name = "prpubkeybox";// PlayReady + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_15:key_15{ + key-name = "prprivkeybox";// PlayReady + key-device = "secure"; + key-permit = "read","write","del"; + }; + keysn_16:key_16{ + key-name = "lcd"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_17:key_17{ + key-name = "lcd_extern"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_18:key_18{ + key-name = "backlight"; + key-device = "normal"; + key-permit = "read","write","del"; + }; + keysn_19:key_19{ + key-name = "attestationkeybox";// attestation key + key-device = "secure"; + key-permit = "read","write","del"; + }; + }; /* End unifykey */ + + cvbsout { + compatible = "amlogic, cvbsout-txlx"; + dev_name = "cvbsout"; + status = "disabled"; + clocks = <&clkc CLKID_VCLK2_ENCI + &clkc CLKID_VCLK2_VENCI0 + &clkc CLKID_VCLK2_VENCI1 + &clkc CLKID_DAC_CLK>; + clock-names = "venci_top_gate", + "venci_0_gate", + "venci_1_gate", + "vdac_clk_gate"; + + /* performance: reg_address, reg_value */ + performance = <0x1b56 0x343 + 0x1b05 0xf4 + 0x1c59 0xfc48 + 0x1b12 0x8c00 + 0xffff 0x0>; /* ending flag */ + }; + + amhdmitx: amhdmitx { + compatible = "amlogic, amhdmitx"; + dev_name = "amhdmitx"; + status = "disabled"; + pinctrl-names="default", "hdmitx_i2c"; + pinctrl-0=<&hdmitx_hpd &hdmitx_ddc>; + pinctrl-1=<&hdmitx_hpd_gpio &i2c2_h_pins>; + /* HPD, 57 + 32 = 89; CEC, 151 + 32 = 183*/ + interrupts = <0 57 1>; + interrupt-names = "hdmitx_hpd"; + /* 0:M8B 1:GXBB 2:GXTVBB 3:GXL 4:GXM + * 5:TXL 6:TXLX 7:AXG 8:GXLX 9:TXHD + */ + ic_type = <6>; + //gpio_i2c_en = <0>; + //repeater_tx = <0x1>; + //#address-cells = <2>; + //#size-cells = <2>; + //ranges; + }; + + i2c_gpio: i2c_gpio { + compatible = "i2c-gpio"; + dev_name = "i2c-gpio"; + status = "disabled"; + i2c-gpio,delay-us = <10>; /* 50 kHz */ + gpios = <&gpio GPIOH_2 0 + &gpio GPIOH_3 0>; + #address-cells = <2>; + #size-cells = <2>; + i2c-gpio,timeout-ms = <10>; + i2c_gpio_edid: i2c_gpio_edid { + compatible = "i2c-gpio"; + reg = <0x50 0x0 0x0 0x0>; + }; + }; + + aocec: aocec { + compatible = "amlogic, aocec-txlx"; + device_name = "aocec"; + status = "okay"; + vendor_name = "Amlogic"; /* Max Chars: 8 */ + /* Refer to the following URL at: + * http://standards.ieee.org/develop/regauth/oui/oui.txt + */ + vendor_id = <0x000000>; + product_desc = "TXLX"; /* Max Chars: 16 */ + cec_osd_string = "AML_TV"; /* Max Chars: 14 */ + port_num = <4>; + /*ee_cec;*/ + arc_port_mask = <0x2>; + interrupts = <0 205 1 + 0 199 1>; + interrupt-names = "hdmi_aocecb","hdmi_aocec"; + pinctrl-names = "default","hdmitx_aocecb","cec_pin_sleep"; + pinctrl-0=<&hdmitx_aocec>; + pinctrl-1=<&hdmitx_aocecb>; + pinctrl-2=<&hdmitx_aocecb>; + reg = <0x0 0xFF80023c 0x0 0x4 + 0x0 0xFF800000 0x0 0x400>; + reg-names = "ao_exit","ao"; + }; + + + canvas { + compatible = "amlogic, meson, canvas"; + dev_name = "amlogic-canvas"; + status = "okay"; + reg = <0x0 0xff638000 0x0 0x2000>; + }; + + rdma { + compatible = "amlogic, meson, rdma"; + dev_name = "amlogic-rdma"; + status = "okay"; + interrupts = <0 89 1>; + interrupt-names = "rdma"; + }; + + dwc3: dwc3@ff500000 { + compatible = "synopsys, dwc3"; + status = "okay"; + reg = <0x0 0xff500000 0x0 0x100000>; + interrupts = <0 30 4>; + usb-phy = <&usb2_phy>, <&usb3_phy>; + cpu-type = "gxl"; + clock-src = "usb3.0"; + }; + + usb2_phy: usb2phy@ffe09000 { + compatible = "amlogic, amlogic-new-usb2"; + status = "okay"; + portnum = <4>; + reg = <0x0 0xffe09000 0x0 0x80 + 0x0 0xffd01008 0x0 0x4>; + }; + + usb3_phy: usb3phy@ffe09080 { + compatible = "amlogic, amlogic-new-usb3"; + status = "okay"; + portnum = <0>; + reg = <0x0 0xffe09080 0x0 0x20>; + }; + + dwc2_a { + compatible = "amlogic, dwc2"; + device_name = "dwc2_a"; + reg = <0x0 0xff400000 0x0 0x40000>; + status = "okay"; + interrupts = <0 31 4>; + pl-periph-id = <0>; /** lm name */ + clock-src = "usb0"; /** clock src */ + port-id = <0>; /** ref to mach/usb.h */ + port-type = <2>; /** 0: otg, 1: host, 2: slave */ + port-speed = <0>; /** 0: default, high, 1: full */ + port-config = <0>; /** 0: default */ + /*0:default,1:single,2:incr,3:incr4,4:incr8,5:incr16,6:disable*/ + port-dma = <0>; + port-id-mode = <0>; /** 0: hardware, 1: sw_host, 2: sw_slave*/ + usb-fifo = <728>; + cpu-type = "gxl"; + /** 0: normal, 1: otg+dwc3 host only, 2: otg+dwc3 device only*/ + controller-type = <1>; + phy-reg = <0xffe09000>; + phy-reg-size = <0xa0>; + clocks = <&clkc CLKID_USB_GENERAL + &clkc CLKID_USB1_TO_DDR>; + clock-names = "usb_general", + "usb1"; + }; + + /* Sound iomap */ + aml_snd_iomap { + compatible = "amlogic, meson-snd-iomap"; + status = "okay"; + #address-cells=<2>; + #size-cells=<2>; + ranges; + io_audin_base { + reg = <0x0 0xffd03000 0x0 0x100000>; + }; + io_aiu_base { + reg = <0x0 0xFFCFFC00 0x0 0x100000>; + }; + io_eqdrc_base { + reg = <0x0 0xFFCFF000 0x0 0x100000>; + }; + io_hiu_reset_base { + reg = <0x0 0xFFCFCC00 0x0 0x100000>; + }; + io_isa_base { + reg = <0x0 0xFFD05800 0x0 0x100000>; + }; + }; + + /* AUDIO DEVICES */ + i2s_dai: I2S { + #sound-dai-cells = <0>; + /* config mpll whether same with audin */ + clocks = <&clkc CLKID_MPLL3>, + <&clkc CLKID_AMCLK_COMP>, + <&clkc CLKID_AIU_GLUE>, + <&clkc CLKID_I2S_OUT>, + <&clkc CLKID_AMCLK_MEASURE>, + <&clkc CLKID_AIFIFO2>, + <&clkc CLKID_MIXER>, + <&clkc CLKID_MIXER_IFACE>, + <&clkc CLKID_ADC>, + <&clkc CLKID_AIU_TOP>, + <&clkc CLKID_AOCLK_GATE>, + <&clkc CLKID_I2S_SPDIF>, + <&clkc CLKID_DAC_CLK>; + clock-names = "mpll", + "mclk", + "top_glue", + "i2s_out", + "amclk_measure", + "aififo2", + "aud_mixer", + "mixer_reg", + "adc", + "top_level", + "aoclk", + "aud_in", + "vdac_clk"; + compatible = "amlogic, aml-i2s-dai"; + }; + + i2s2_dai: I2S2 { + #sound-dai-cells = <0>; + /* config mpll whether same with aiu */ + clocks = <&clkc CLKID_MPLL2>, + <&clkc CLKID_AUDIN_MCLK_COMP>, + <&clkc CLKID_AUDIN_SCLK_COMP>, + <&clkc CLKID_AUDIN_LRCLK_COMP>; + clock-names = "audin_mpll", + "audin_mclk", + "audin_sclk", + "audin_lrclk"; + compatible = "amlogic, aml-i2s2-dai"; + }; + + spdif_dai: SPDIF { + #sound-dai-cells = <0>; + compatible = "amlogic, aml-spdif-dai"; + clocks = <&clkc CLKID_MPLL1>, + <&clkc CLKID_IEC958_INT_COMP>, + <&clkc CLKID_AMCLK_COMP>, + <&clkc CLKID_IEC958_MUX>, + <&clkc CLKID_CLK81>, + <&clkc CLKID_IEC958>, + <&clkc CLKID_IEC958_GATE>; + clock-names = + "mpll1", + "i958", + "mclk", + "spdif", + "clk_81", + "iec958", + "iec958_amclk"; + }; + + pcm_dai: PCM { + #sound-dai-cells = <0>; + compatible = "amlogic, aml-pcm-dai"; + pinctrl-names = "audio_pcm"; + /* disable pcm pin mux temporary, enable it if necessary */ + /*pinctrl-0 = <&aml_audio_pcm>;*/ + clocks = <&clkc CLKID_MPLL0>, + <&clkc CLKID_PCM_MCLK_COMP>, + <&clkc CLKID_PCM_SCLK_COMP>; + clock-names = "mpll0", "pcm_mclk", "pcm_sclk"; + pcm_mode = <1>; /* 0=slave mode, 1=master mode */ + }; + + i2s_plat: i2s_platform { + compatible = "amlogic, aml-i2s"; + interrupts = <0 29 1>; + }; + + pcm_plat: pcm_platform { + compatible = "amlogic, aml-pcm"; + }; + + spdif_codec: spdif_codec{ + #sound-dai-cells = <0>; + compatible = "amlogic, aml-spdif-codec"; + pinctrl-names = "audio_spdif_out", "audio_spdif_out_mute"; + pinctrl-0 = <&audio_spdif_out_pins>; + pinctrl-1 = <&audio_spdif_out_mute_pins>; + }; + + pcm_codec: pcm_codec{ + #sound-dai-cells = <0>; + compatible = "amlogic, pcm2BT-codec"; + }; + /* end of AUDIO DEVICES */ + + /* AUDIO board specific */ + dummy_codec:dummy{ + #sound-dai-cells = <0>; + compatible = "amlogic, aml_dummy_codec"; + status = "okay"; + }; + + amlogic_codec:txlx_acodec{ + #sound-dai-cells = <0>; + compatible = "amlogic, txlx_acodec"; + reg = <0x0 0xFF632000 0x0 0x1c>; + status = "okay"; + }; + + aml_snd_tv { + compatible = "amlogic, txlx-snd-tv"; + status = "okay"; + aml-sound-card,format = "i2s"; + aml_sound_card,name = "AML-TVAUDIO"; + pinctrl-names = "audio_i2s"; + pinctrl-0 = <&aml_audio_i2s>; + /*avout mute gpio*/ + mute_gpio-gpios = <&gpio GPIODV_5 GPIO_ACTIVE_HIGH>; + /*analog amp mute*/ + /*amp_mute_gpio-gpios = <&gpio GPIOZ_18 GPIO_ACTIVE_LOW>;*/ + aux_dev = <&tas5707>; + cpu_list = <&cpudai0 &cpudai1 &cpudai2 &cpudai3>; + codec_list = <&codec0 &codec1 &codec2 &codec3>; + plat_list = <&i2s_plat &i2s_plat &pcm_plat &i2s_plat>; + cpudai0: cpudai0 { + sound-dai = <&i2s_dai>; + }; + cpudai1: cpudai1 { + sound-dai = <&spdif_dai>; + }; + cpudai2: cpudai2 { + sound-dai = <&pcm_dai>; + }; + cpudai3: cpudai3 { + sound-dai = <&i2s2_dai>; + }; + codec0: codec0 { + sound-dai = <&amlogic_codec>; + }; + codec1: codec1 { + sound-dai = <&spdif_codec>; + }; + codec2: codec2 { + sound-dai = <&pcm_codec>; + }; + codec3: codec3 { + sound-dai = <&dummy_codec>; + }; + Channel_Mask { + /*i2s has 4 pins, 8channel, mux output*/ + Speaker0_Channel_Mask = "i2s_2/3"; + DAC0_Channel_Mask = "i2s_2/3"; + DAC1_Channel_Mask = "i2s_2/3"; + EQ_DRC_Channel_Mask = "i2s_2/3"; + Spdif_samesource_Channel_Mask = "i2s_0/1"; + }; + }; + + amaudio2 { + compatible = "amlogic, aml_amaudio2"; + status = "okay"; + interrupts = <0 48 1>; + }; + /* end of AUDIO board specific */ + + + aml_sensor0: aml-sensor@0 { + compatible = "amlogic, aml-thermal"; + device_name = "thermal"; + status = "okay"; + #thermal-sensor-cells = <1>; + cooling_devices { + cpufreq_cool_cluster0 { + min_state = <1000000>; + dyn_coeff = <140>; + cluster_id = <0>; + node_name = "cpus"; + device_type = "cpufreq"; + }; + cpucore_cool_cluster0 { + min_state = <1>; + dyn_coeff = <0>; + cluster_id = <0>; + node_name = "cpu_core_cluster0"; + device_type = "cpucore"; + }; + gpufreq_cool { + min_state = <400>; + dyn_coeff = <437>; + cluster_id = <0>; + node_name = "mali"; + device_type = "gpufreq"; + }; + gpucore_cool { + min_state = <1>; + dyn_coeff = <0>; + cluster_id = <0>; + node_name = "thermal_gpu_cores"; + device_type = "gpucore"; + }; + }; + cpu_cluster0:cpu_core_cluster0 { + #cooling-cells = <2>; /* min followed by max */ + }; + gpucore:thermal_gpu_cores { + #cooling-cells = <2>; /* min followed by max */ + }; + }; + + dvb { + compatible = "amlogic, dvb"; + dev_name = "dvb"; + status = "okay"; + fe0_mode = "internal"; + fe0_tuner = <&tuner>; + /*"parallel","serial","disable"*/ + ts2 = "parallel"; + ts2_control = <0>; + ts2_invert = <0>; + interrupts = <0 23 1 + 0 5 1 + 0 53 1 + 0 19 1 + 0 25 1 + 0 18 1 + 0 24 1>; + interrupt-names = "demux0_irq", + "demux1_irq", + "demux2_irq", + "dvr0_irq", + "dvr1_irq", + "dvrfill0_fill", + "dvrfill1_flush"; + clocks = <&clkc CLKID_DEMUX + &clkc CLKID_ASYNC_FIFO + &clkc CLKID_AHB_ARB0 + &clkc CLKID_DOS_PARSER>; + clock-names = "demux", "asyncfifo", "ahbarb0", "uparsertop"; + }; + aml_dtv_demod { + compatible = "amlogic, ddemod-txlx"; + dev_name = "aml_dtv_demod"; + status = "okay"; + + //pinctrl-names="dtvdemod_agc"; + //pinctrl-0=<&dtvdemod_agc>; + + + clocks = <&clkc CLKID_DAC_CLK>; + clock-names = "vdac_clk_gate"; + + + reg = <0x0 0xff644000 0x0 0x2000 /*dtv demod base*/ + 0x0 0xff63c000 0x0 0x2000 /*hiu reg base*/ + 0x0 0xff800000 0x0 0x1000 /*io_aobus_base*/ + 0x0 0xffd01000 0x0 0x1000 /*reset*/ + >; + /*move from dvbfe*/ + dtv_demod0_mem = <0>; // need move to aml_dtv_demod ? + spectrum = <1>; + cma_flag = <1>; + cma_mem_size = <8>; + memory-region = <&demod_cma_reserved>;//<&demod_reserved>; + }; + dvbfe { + compatible = "amlogic, dvbfe"; + dev_name = "dvbfe"; + status = "disabled"; + dtv_demod0 = "AMLDEMOD"; + fe0_dtv_demod = <0>; + fe0_ts = <2>; + fe0_dev = <0>; + dtv_demod0_mem = <0>; + dtv_demod0_spectrum = <1>; + dtv_demod0_cma_flag = <1>; + dtv_demod0_cma_mem_size = <8>; + memory-region = <&demod_cma_reserved>;//<&demod_reserved>; + tuner0 = "si2151_tuner"; + tuner0_i2c_adap_id = <2>; + tuner0_i2c_addr = <0x60>; + //tuner0_reset_value = <0>; + //tuner0_reset_gpio = "GPIOY_10" ; /*GPIOX_8 76*/ + fe0_tuner = <0>; + atv_demod0 = "aml_atv_demod"; + fe0_atv_demod = <0>; + }; + + thermal-zones { + soc_thermal { + polling-delay = <1000>; + polling-delay-passive = <100>; + sustainable-power = <2150>; + + thermal-sensors = <&aml_sensor0 3>; + + trips { + switch_on: trip-point@0 { + temperature = <70000>; + hysteresis = <1000>; + type = "passive"; + }; + control: trip-point@1 { + temperature = <80000>; + hysteresis = <1000>; + type = "passive"; + }; + hot: trip-point@2 { + temperature = <85000>; + hysteresis = <5000>; + type = "hot"; + }; + critical: trip-point@3 { + temperature = <260000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + + cooling-maps { + cpufreq_cooling_map { + trip = <&control>; + cooling-device = <&cpus 0 4>; + contribution = <1024>; + }; + cpucore_cooling_map { + trip = <&control>; + cooling-device = <&cpu_cluster0 0 3>; + contribution = <1024>; + }; + gpufreq_cooling_map { + trip = <&control>; + cooling-device = <&gpu 0 4>; + contribution = <1024>; + }; + gpucore_cooling_map { + trip = <&control>; + cooling-device = <&gpucore 0 2>; + contribution = <1024>; + }; + }; + }; + }; + +}; /* end of / */ + +&i2c2 { + status = "okay"; + pinctrl-names="default"; + pinctrl-0=<&i2c2_h_pins>; + + tas5707: tas5707@36 { + compatible = "ti,tas5707"; + #sound-dai-cells = <0>; + codec_name = "tas5707"; + reg = <0x1B>; + reset_pin = <&gpio GPIODV_4 GPIO_ACTIVE_LOW>; + eq_enable = <0>; + drc_enable = <0>; + status = "okay"; + }; + + lcd_extern_i2c0: lcd_extern_i2c@0 { + compatible = "lcd_ext, i2c"; + dev_name = "i2c_T5800Q"; + reg = <0x1c>; + status = "okay"; + }; + + lcd_extern_i2c1: lcd_extern_i2c@1 { + compatible = "lcd_ext, i2c"; + dev_name = "i2c_ANX6862"; + reg = <0x20>; + status = "okay"; + }; + + lcd_extern_i2c2: lcd_extern_i2c@2 { + compatible = "lcd_ext, i2c"; + dev_name = "i2c_ANX7911"; + reg = <0x74>; + status = "okay"; + }; +}; + +&i2c1 { + status = "okay"; + clock-frequency = <300000>; + pinctrl-names="default"; + pinctrl-0=<&i2c1_dv_pins>; +}; + +&pinctrl_periphs { + /*i2s*/ + aml_audio_i2s: aml_audio_i2s { + mux { + groups = "i2s_mclk_h", + "i2s_sclk_h", + "i2s_lrclk_h", + "i2s_dout01_h6"; + function = "i2s"; + }; + }; + /*spdif*/ + audio_spdif_out_pins: audio_spdif_out_pins { + mux { + groups = "spdif_out_dv"; + function = "spdif_out"; + }; + }; + audio_spdif_out_mute_pins: audio_spdif_out_mute_pins { + mux { + groups = "GPIODV_6"; + function = "gpio_periphs"; + }; + }; + /*pcm*/ + aml_audio_pcm: aml_audio_pcm { + mux { + groups = + "pcm_clk_a_dv", + "pcm_fs_a_dv", + "pcm_in_a_dv", + "pcm_out_a_dv"; + function = "pcm_a"; + }; + }; + + /*lcd_extern*/ + lcd_extern_off_pins:lcd_extern_off_pin { + mux { + pins = "GPIOH_2", + "GPIOH_3"; + function = "gpio_periphs"; + /*output-high;*/ + output-low; + /*input-enable;*/ + }; + }; + + /*backlight*/ + bl_pwm_on_pins:bl_pwm_on_pin { + mux { + pins = "pwm_b"; + function = "pwm_b"; + }; + }; + bl_pwm_vs_on_pins:bl_pwm_vs_on_pin { + mux { + pins = "pwm_vs_z6"; + function = "pwm_vs"; + }; + }; + bl_pwm_off_pins:bl_pwm_off_pin { + mux { + pins = "GPIOZ_6"; + function = "gpio_periphs"; + output-low; + }; + }; + bl_pwm_combo_0_on_pins:bl_pwm_combo_0_on_pin { + mux { + pins = "pwm_b"; + function = "pwm_b"; + }; + }; + bl_pwm_combo_1_on_pins:bl_pwm_combo_1_on_pin { + mux { + pins = "pwm_c_z"; + function = "pwm_c"; + }; + }; + bl_pwm_combo_0_vs_on_pins:bl_pwm_combo_0_vs_on_pin { + mux { + pins = "pwm_vs_z6"; + function = "pwm_vs"; + }; + }; + bl_pwm_combo_1_vs_on_pins:bl_pwm_combo_1_vs_on_pin { + mux { + pins = "pwm_vs_z7"; + function = "pwm_vs"; + }; + }; + bl_pwm_combo_off_pins:bl_pwm_combo_off_pin { + mux { + pins = "GPIOZ_6", + "GPIOZ_7"; + function = "gpio_periphs"; + output-low; + }; + }; +}; + +&uart_A { + status = "okay"; +}; + +&audio_data{ + status = "okay"; +}; + +&pwm_AO_ab { + status = "okay"; +}; + +&pwm_ab { + status = "okay"; +}; + +&pwm_cd { + status = "okay"; +}; + +&spicc0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&spi_a_pins>; + cs-gpios = <&gpio GPIOZ_3 0>; +}; diff --git a/arch/arm64/configs/meson64_defconfig b/arch/arm64/configs/meson64_defconfig index afb3dd592a47..3ba9dd16e0fa 100644 --- a/arch/arm64/configs/meson64_defconfig +++ b/arch/arm64/configs/meson64_defconfig @@ -454,8 +454,12 @@ CONFIG_REGULATOR_PWM=y CONFIG_MEDIA_SUPPORT=y CONFIG_MEDIA_CAMERA_SUPPORT=y CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y +CONFIG_MEDIA_RC_SUPPORT=y CONFIG_MEDIA_USB_SUPPORT=y CONFIG_USB_VIDEO_CLASS=y +CONFIG_VIDEO_CX231XX=y +# CONFIG_VIDEO_CX231XX_RC is not set +CONFIG_VIDEO_CX231XX_DVB=y CONFIG_FB=y CONFIG_BACKLIGHT_LCD_SUPPORT=y CONFIG_BACKLIGHT_CLASS_DEVICE=y diff --git a/arch/arm64/kernel/armv8_deprecated.c b/arch/arm64/kernel/armv8_deprecated.c index 29d2ad8844a5..6499b24aed33 100644 --- a/arch/arm64/kernel/armv8_deprecated.c +++ b/arch/arm64/kernel/armv8_deprecated.c @@ -454,7 +454,11 @@ static struct undef_hook swp_hooks[] = { static struct insn_emulation_ops swp_ops = { .name = "swp", +#ifdef CONFIG_AMLOGIC_MODIFY + .status = INSN_DEPRECATED, +#else .status = INSN_OBSOLETE, +#endif .hooks = swp_hooks, .set_hw_mode = NULL, }; diff --git a/arch/arm64/mm/mmu.c b/arch/arm64/mm/mmu.c index 6645653a67a2..5a463e22ab71 100644 --- a/arch/arm64/mm/mmu.c +++ b/arch/arm64/mm/mmu.c @@ -181,6 +181,10 @@ static void alloc_init_pmd(pud_t *pud, unsigned long addr, unsigned long end, static inline bool use_1G_block(unsigned long addr, unsigned long next, unsigned long phys) { +#ifdef CONFIG_AMLOGIC_CMA + /* we need create full 2nd page table */ + return false; +#else if (PAGE_SHIFT != 12) return false; @@ -188,6 +192,7 @@ static inline bool use_1G_block(unsigned long addr, unsigned long next, return false; return true; +#endif } static void alloc_init_pud(pgd_t *pgd, unsigned long addr, unsigned long end, diff --git a/block/partition-generic.c b/block/partition-generic.c index d2582d88ebfe..736f5b979a21 100644 --- a/block/partition-generic.c +++ b/block/partition-generic.c @@ -25,7 +25,6 @@ extern void md_autodetect_dev(dev_t dev); #endif -#define AMLOGIC_ADD_PARTITION /* * disk_name() is used by partition check code and the genhd driver. * It formats the devicename of the indicated disk into @@ -290,10 +289,9 @@ struct hd_struct *add_partition(struct gendisk *disk, int partno, struct disk_part_tbl *ptbl; const char *dname; int err; -#ifdef AMLOGIC_ADD_PARTITION - char *info_name = NULL; -#endif + err = disk_expand_part_tbl(disk, partno); + if (err) return ERR_PTR(err); ptbl = disk->part_tbl; @@ -334,24 +332,10 @@ struct hd_struct *add_partition(struct gendisk *disk, int partno, dname = dev_name(ddev); -#ifdef AMLOGIC_ADD_PARTITION - if (info) { - info_name = (char *)info->volname; - } - - if (info_name && (strlen(info_name) > 1)) { - dname = (char *)info->volname; - dev_set_name(pdev, "%s", dname); - } else if (isdigit(dname[strlen(dname) - 1])) - dev_set_name(pdev, "%sp%d", dname, partno); - else - dev_set_name(pdev, "%s%d", dname, partno); -#else if (isdigit(dname[strlen(dname) - 1])) dev_set_name(pdev, "%sp%d", dname, partno); else dev_set_name(pdev, "%s%d", dname, partno); -#endif device_initialize(pdev); pdev->class = &block_class; diff --git a/drivers/amlogic/atv_demod/atv_demod_access.c b/drivers/amlogic/atv_demod/atv_demod_access.c index 0b6243be3f23..390c5d02cf91 100644 --- a/drivers/amlogic/atv_demod/atv_demod_access.c +++ b/drivers/amlogic/atv_demod/atv_demod_access.c @@ -29,6 +29,7 @@ int amlatvdemod_reg_read(unsigned int reg, unsigned int *val) { +#if 0 /* Don't need to check the CLK and PLL states, it's done in init */ int ret = 0; if (is_meson_txlx_cpu() || is_meson_txhd_cpu()) { @@ -41,13 +42,16 @@ int amlatvdemod_reg_read(unsigned int reg, unsigned int *val) /* pr_dbg("%s atv demod pll not init\n", __func__); */ return 0; } +#endif *val = readl(amlatvdemod_devp->demod_reg_base + reg); + return 0; } int amlatvdemod_reg_write(unsigned int reg, unsigned int val) { +#if 0 /* Don't need to check the CLK and PLL states, it's done in init */ int ret = 0; if (is_meson_txlx_cpu() || is_meson_txhd_cpu()) { @@ -60,8 +64,10 @@ int amlatvdemod_reg_write(unsigned int reg, unsigned int val) /* pr_dbg("%s atv demod pll not init\n", __func__); */ return 0; } +#endif writel(val, (amlatvdemod_devp->demod_reg_base + reg)); + return 0; } diff --git a/drivers/amlogic/atv_demod/atv_demod_ops.c b/drivers/amlogic/atv_demod/atv_demod_ops.c index 12ead9f2d425..029d65229e3a 100644 --- a/drivers/amlogic/atv_demod/atv_demod_ops.c +++ b/drivers/amlogic/atv_demod/atv_demod_ops.c @@ -52,6 +52,11 @@ unsigned int btsc_sap_mode = 1; /*0: off 1:monitor 2:auto */ */ void aml_fe_get_atvaudio_state(int *state) { +#if 0 /* delay notification stable */ + static unsigned int count; + static bool mute = true; +#endif + int av_status = 0; int power = 0; int vpll_lock = 0; int line_lock = 0; @@ -64,12 +69,16 @@ void aml_fe_get_atvaudio_state(int *state) return; } + av_status = tvin_get_av_status(); /* scan mode need mute */ - if (priv->state == ATVDEMOD_STATE_WORK && !priv->scanning) { + if (priv->state == ATVDEMOD_STATE_WORK + && !priv->scanning + && !priv->standby + && av_status) { retrieve_vpll_carrier_lock(&vpll_lock); retrieve_vpll_carrier_line_lock(&line_lock); if ((vpll_lock == 0) && (line_lock == 0)) { - retrieve_vpll_carrier_audio_power(&power); + /* retrieve_vpll_carrier_audio_power(&power); */ *state = 1; } else { *state = 0; @@ -78,8 +87,9 @@ void aml_fe_get_atvaudio_state(int *state) } } else { *state = 0; - pr_audio("%s, atv is not work, atv_state: %d.\n", - __func__, priv->state); + pr_audio("ATV state[%d], scan[%d], standby[%d], av[%d].\n", + priv->state, priv->scanning, + priv->standby, av_status); } /* If the atv signal is locked, it means there is audio data, @@ -91,7 +101,23 @@ void aml_fe_get_atvaudio_state(int *state) else *state = 0; #endif - pr_audio("aml_fe_get_atvaudio_state: %d, power = %d.\n", +#if 0 /* delay notification stable */ + if (*state) { + if (mute) { + count++; + if (count > 100) { + count = 0; + mute = false; + } else + *state = 0; + } else + count = 0; + } else { + count = 0; + mute = true; + } +#endif + pr_audio("aml_fe_get_atvaudio_state: %d, power = %d\n", *state, power); } @@ -114,7 +140,7 @@ int atv_demod_enter_mode(struct dvb_frontend *fe) } } - adc_set_pll_cntl(1, ADC_EN_ATV_DEMOD, NULL); + err_code = adc_set_pll_cntl(1, ADC_EN_ATV_DEMOD, NULL); vdac_enable(1, 1); usleep_range(2000, 2100); atvdemod_clk_init(); @@ -124,9 +150,10 @@ int atv_demod_enter_mode(struct dvb_frontend *fe) aud_demod_clk_gate(1); /* atvauddemod_init(); */ } + if (err_code) { - pr_dbg("[amlatvdemod..]%s init atvdemod error.\n", __func__); - return err_code; + pr_dbg("%s: init atvdemod error %d.\n", __func__, err_code); + return -1; } /* aml_afc_timer_enable(fe); */ @@ -145,6 +172,9 @@ int atv_demod_leave_mode(struct dvb_frontend *fe) { struct atv_demod_priv *priv = fe->analog_demod_priv; + priv->state = ATVDEMOD_STATE_IDEL; + priv->standby = true; + if (priv->afc.disable) priv->afc.disable(&priv->afc); @@ -166,8 +196,6 @@ int atv_demod_leave_mode(struct dvb_frontend *fe) amlatvdemod_devp->audmode = 0; amlatvdemod_devp->soundsys = 0xFF; - priv->state = ATVDEMOD_STATE_IDEL; - pr_info("%s: OK.\n", __func__); return 0; @@ -182,7 +210,7 @@ static void atv_demod_set_params(struct dvb_frontend *fe, struct aml_atvdemod_parameters *p = &priv->atvdemod_param; bool reconfig = false; - priv->standby = false; + priv->standby = true; /* afc tune disable,must cancel wq before set tuner freq*/ if (priv->afc.disable) @@ -252,6 +280,9 @@ static void atv_demod_set_params(struct dvb_frontend *fe, if (priv->monitor.enable) priv->monitor.enable(&priv->monitor); + + /* for searching mute audio */ + priv->standby = false; } } @@ -285,6 +316,7 @@ static void atv_demod_standby(struct dvb_frontend *fe) if (priv->state != ATVDEMOD_STATE_IDEL) { atv_demod_leave_mode(fe); priv->state = ATVDEMOD_STATE_SLEEP; + priv->standby = true; } pr_info("%s: OK.\n", __func__); @@ -337,10 +369,11 @@ static int atv_demod_set_config(struct dvb_frontend *fe, void *priv_cfg) switch (*state) { case AML_ATVDEMOD_INIT: if (priv->state != ATVDEMOD_STATE_WORK) { + priv->standby = true; if (fe->ops.tuner_ops.set_config) fe->ops.tuner_ops.set_config(fe, NULL); - atv_demod_enter_mode(fe); - priv->state = ATVDEMOD_STATE_WORK; + if (!atv_demod_enter_mode(fe)) + priv->state = ATVDEMOD_STATE_WORK; } break; @@ -354,8 +387,10 @@ static int atv_demod_set_config(struct dvb_frontend *fe, void *priv_cfg) case AML_ATVDEMOD_RESUME: if (priv->state == ATVDEMOD_STATE_SLEEP) { - atv_demod_enter_mode(fe); - priv->state = ATVDEMOD_STATE_WORK; + if (!atv_demod_enter_mode(fe)) { + priv->state = ATVDEMOD_STATE_WORK; + priv->standby = false; + } } break; diff --git a/drivers/amlogic/atv_demod/atv_demod_ops.h b/drivers/amlogic/atv_demod/atv_demod_ops.h index d6a091e3f532..775c5ecf686b 100644 --- a/drivers/amlogic/atv_demod/atv_demod_ops.h +++ b/drivers/amlogic/atv_demod/atv_demod_ops.h @@ -70,6 +70,7 @@ struct atv_demod_priv { extern int atv_demod_enter_mode(struct dvb_frontend *fe); +extern int tvin_get_av_status(void); struct dvb_frontend *aml_atvdemod_attach(struct dvb_frontend *fe, struct v4l2_frontend *v4l2_fe, diff --git a/drivers/amlogic/atv_demod/atv_demod_v4l2.c b/drivers/amlogic/atv_demod/atv_demod_v4l2.c index 76413a94dbec..beaad44f9670 100644 --- a/drivers/amlogic/atv_demod/atv_demod_v4l2.c +++ b/drivers/amlogic/atv_demod/atv_demod_v4l2.c @@ -331,6 +331,14 @@ static int v4l2_frontend_start(struct v4l2_frontend *v4l2_fe) } +static int v4l2_frontend_check_mode(struct v4l2_frontend *v4l2_fe) +{ + if (v4l2_fe->mode != V4L2_TUNER_ANALOG_TV) + return -EINVAL; + + return 0; +} + static int v4l2_set_frontend(struct v4l2_frontend *v4l2_fe, struct v4l2_analog_parameters *params) { @@ -343,6 +351,9 @@ static int v4l2_set_frontend(struct v4l2_frontend *v4l2_fe, pr_dbg("%s.\n", __func__); + if (v4l2_frontend_check_mode(v4l2_fe) < 0) + return -EINVAL; + freq_min = fe->ops.tuner_ops.info.frequency_min; freq_max = fe->ops.tuner_ops.info.frequency_max; @@ -419,10 +430,13 @@ static int v4l2_frontend_set_mode(struct v4l2_frontend *v4l2_fe, analog_ops = &v4l2_fe->fe.ops.analog_ops; - if (params) + if (params) { priv_cfg = AML_ATVDEMOD_INIT; - else + v4l2_fe->mode = V4L2_TUNER_ANALOG_TV; + } else { priv_cfg = AML_ATVDEMOD_UNINIT; + v4l2_fe->mode = V4L2_TUNER_RF; + } if (analog_ops && analog_ops->set_config) ret = analog_ops->set_config(&v4l2_fe->fe, &priv_cfg); diff --git a/drivers/amlogic/atv_demod/atv_demod_v4l2.h b/drivers/amlogic/atv_demod/atv_demod_v4l2.h index 0b2c9cda9827..0683c94878ec 100644 --- a/drivers/amlogic/atv_demod/atv_demod_v4l2.h +++ b/drivers/amlogic/atv_demod/atv_demod_v4l2.h @@ -199,6 +199,8 @@ struct v4l2_frontend { unsigned int tuner_id; struct i2c_client i2c; + enum v4l2_tuner_type mode; + void *frontend_priv; void *tuner_priv; void *analog_demod_priv; diff --git a/drivers/amlogic/atv_demod/atvdemod_func.c b/drivers/amlogic/atv_demod/atvdemod_func.c index 854f13286533..286c16185e54 100644 --- a/drivers/amlogic/atv_demod/atvdemod_func.c +++ b/drivers/amlogic/atv_demod/atvdemod_func.c @@ -1746,12 +1746,9 @@ int atvdemod_init(void) pr_err("%s do atv_dmd_soft_reset ...\n", __func__); /*4.software reset*/ atv_dmd_soft_reset(); - atv_dmd_soft_reset(); - atv_dmd_soft_reset(); - atv_dmd_soft_reset(); - /* ????? - * while (!all_lock) { + /* check the PLL, line lock status, don't need to check. */ + /* while (!all_lock) { * data32 = atv_dmd_rd_long(APB_BLOCK_ADDR_VDAGC,0x13<<2); * if ((data32 & 0x1c) == 0x0) { * all_lock = 1; @@ -1769,6 +1766,10 @@ int atvdemod_init(void) void atvdemod_uninit(void) { + /* mute atv audio output */ + if (is_meson_txl_cpu()) + atv_dmd_wr_long(APB_BLOCK_ADDR_MONO_PROC, 0x50, 0); + atv_dmd_non_std_set(false); } diff --git a/drivers/amlogic/audioinfo/audio_data.c b/drivers/amlogic/audioinfo/audio_data.c index c50076cda9c1..f5494c3eb2ce 100644 --- a/drivers/amlogic/audioinfo/audio_data.c +++ b/drivers/amlogic/audioinfo/audio_data.c @@ -114,7 +114,7 @@ unsigned long audio_info_get(char *buf, unsigned long count, unsigned long pos) { struct efuse_hal_api_arg arg; - unsigned int retcnt; + unsigned long retcnt; int ret; arg.cmd = efuse_query_licence_cmd; diff --git a/drivers/amlogic/cec/ee_cec_reg.h b/drivers/amlogic/cec/ee_cec_reg.h index 2561374be283..2978a24ba6b6 100644 --- a/drivers/amlogic/cec/ee_cec_reg.h +++ b/drivers/amlogic/cec/ee_cec_reg.h @@ -41,7 +41,7 @@ /*---- registers for EE CEC ----*/ #define DWC_CEC_CTRL 0x1F00 -#define DWC_CEC_STAT 0x1F04 +#define DWC_CEC_CTRL2 0x1F04/*tl1 later*/ #define DWC_CEC_MASK 0x1F08 #define DWC_CEC_POLARITY 0x1F0C #define DWC_CEC_INT 0x1F10 diff --git a/drivers/amlogic/cec/hdmi_ao_cec.c b/drivers/amlogic/cec/hdmi_ao_cec.c index 9722df761056..68a27b512fb9 100644 --- a/drivers/amlogic/cec/hdmi_ao_cec.c +++ b/drivers/amlogic/cec/hdmi_ao_cec.c @@ -76,11 +76,15 @@ static struct early_suspend aocec_suspend_handler; #define MAX_INT 0x7ffffff struct cec_platform_data_s { + /*unsigned int chip_id;*/ unsigned char line_reg;/*cec gpio_i reg:0 ao;1 periph*/ unsigned int line_bit;/*cec gpio position in reg*/ bool ee_to_ao;/*ee cec hw module mv to ao;ao cec delete*/ + bool ceca_sts_reg;/*add new internal status register*/ + enum cecbver cecb_ver;/* detail discription ref enum cecbver */ }; + struct cec_wakeup_t { unsigned int wk_logic_addr:8; unsigned int wk_phy_addr:16; @@ -92,13 +96,15 @@ struct ao_cec_dev { unsigned long dev_type; struct device_node *node; unsigned int port_num; /*total input hdmi port number*/ + unsigned int cec_num; unsigned int arc_port; unsigned int output; unsigned int hal_flag; unsigned int phy_addr; unsigned int port_seq; unsigned int cpu_type; - unsigned long irq_cec; + unsigned long irq_ceca; + unsigned long irq_cecb; void __iomem *exit_reg; void __iomem *cec_reg; void __iomem *hdmi_rxreg; @@ -181,7 +187,7 @@ static unsigned char msg_log_buf[128] = { 0 }; while (readl(cec_dev->cec_reg + r) & (1<<23)) {\ if (cnt++ == 3500) { \ pr_info("waiting aocec %x free time out\n", r);\ - cec_hw_reset();\ + cec_hw_reset(CEC_A);\ break;\ } \ } \ @@ -237,6 +243,7 @@ static unsigned int aocecb_rd_reg(unsigned long addr) { unsigned int data32; unsigned long flags; + unsigned int timeout = 0; spin_lock_irqsave(&cec_dev->cec_reg_lock, flags); data32 = 0; @@ -244,8 +251,17 @@ static unsigned int aocecb_rd_reg(unsigned long addr) data32 |= 0 << 8; /* [15:8] cec_reg_wrdata */ data32 |= addr << 0; /* [7:0] cec_reg_addr */ writel(data32, cec_dev->cec_reg + AO_CECB_RW_REG); - - data32 = ((readl(cec_dev->cec_reg + AO_CECB_RW_REG)) >> 24) & 0xff; + /* add for check access busy */ + data32 = readl(cec_dev->cec_reg + AO_CECB_RW_REG); + while (data32 & (1 << 23)) { + if (timeout++ > 200) { + CEC_ERR("cecb access reg 0x%x fail\n", + (unsigned int)addr); + break; + } + data32 = readl(cec_dev->cec_reg + AO_CECB_RW_REG); + } + data32 = (data32 >> 24) & 0xff; spin_unlock_irqrestore(&cec_dev->cec_reg_lock, flags); return data32; } /* aocecb_rd_reg */ @@ -315,7 +331,7 @@ void cec_dbg_init(void) stdbgflg.hal_cmd_bypass = 0; } -void cecrx_hw_reset(void) +void cecb_hw_reset(void) { /* cec disable */ if (!cec_dev->plat_data->ee_to_ao) @@ -341,7 +357,7 @@ static void cecrx_check_irq_enable(void) } } -static int cecrx_trigle_tx(const unsigned char *msg, unsigned char len) +static int cecb_trigle_tx(const unsigned char *msg, unsigned char len) { int i = 0, size = 0; int lock; @@ -352,7 +368,7 @@ static int cecrx_trigle_tx(const unsigned char *msg, unsigned char len) lock = hdmirx_cec_read(DWC_CEC_LOCK); if (lock) { CEC_ERR("recevie msg in tx\n"); - cecrx_irq_handle(); + cecb_irq_handle(); return -1; } if (hdmirx_cec_read(DWC_CEC_CTRL) & 0x01) @@ -400,13 +416,10 @@ static inline void cecrx_clear_irq(unsigned int flags) writel(flags, cec_dev->cec_reg + AO_CECB_INTR_CLR); } -static int cec_pick_msg(unsigned char *msg, unsigned char *out_len) +static int cecb_pick_msg(unsigned char *msg, unsigned char *out_len) { int i, size; int len; - struct delayed_work *dwork; - - dwork = &cec_dev->cec_work; len = hdmirx_cec_read(DWC_CEC_RX_CNT); size = sprintf(msg_log_buf, "CEC RX len %d:", len); @@ -418,7 +431,6 @@ static int cec_pick_msg(unsigned char *msg, unsigned char *out_len) msg_log_buf[size] = '\0'; /* clr CEC lock bit */ hdmirx_cec_write(DWC_CEC_LOCK, 0); - mod_delayed_work(cec_dev->cec_thread, dwork, 0); CEC_INFO("%s", msg_log_buf); if (((msg[0] & 0xf0) >> 4) == cec_dev->cec_info.log_addr) { *out_len = 0; @@ -429,11 +441,12 @@ static int cec_pick_msg(unsigned char *msg, unsigned char *out_len) return 0; } -void cecrx_irq_handle(void) +void cecb_irq_handle(void) { uint32_t intr_cec; uint32_t lock; int shift = 0; + struct delayed_work *dwork; intr_cec = cec_has_irq(); @@ -441,8 +454,6 @@ void cecrx_irq_handle(void) if (intr_cec != 0) cecrx_clear_irq(intr_cec); - if (!ee_cec) - return; if (cec_dev->plat_data->ee_to_ao) shift = 16; /* TX DONE irq, increase tx buffer pointer */ @@ -453,8 +464,11 @@ void cecrx_irq_handle(void) lock = hdmirx_cec_read(DWC_CEC_LOCK); /* EOM irq, message is coming */ if ((intr_cec & CEC_IRQ_RX_EOM) || lock) { - cec_pick_msg(rx_msg, &rx_len); + cecb_pick_msg(rx_msg, &rx_len); complete(&cec_dev->rx_ok); + new_msg = 1; + dwork = &cec_dev->cec_work; + mod_delayed_work(cec_dev->cec_thread, dwork, 0); } /* TX error irq flags */ @@ -493,9 +507,10 @@ void cecrx_irq_handle(void) } } -static irqreturn_t cecb_rx_isr(int irq, void *dev_instance) +static irqreturn_t cecb_isr(int irq, void *dev_instance) { - cecrx_irq_handle(); + /*CEC_INFO("cecb_isr\n");*/ + cecb_irq_handle(); return IRQ_HANDLED; } @@ -504,99 +519,8 @@ static void ao_cecb_init(void) unsigned long data32; unsigned int reg; - if (!cec_dev->plat_data->ee_to_ao) - return; + cecb_hw_reset(); - reg = (0 << 31) | - (0 << 30) | - (1 << 28) | /* clk_div0/clk_div1 in turn */ - ((732-1) << 12) | /* Div_tcnt1 */ - ((733-1) << 0); /* Div_tcnt0 */ - writel(reg, cec_dev->cec_reg + AO_CECB_CLK_CNTL_REG0); - reg = (0 << 13) | - ((11-1) << 12) | - ((8-1) << 0); - writel(reg, cec_dev->cec_reg + AO_CECB_CLK_CNTL_REG1); - - reg = readl(cec_dev->cec_reg + AO_CECB_CLK_CNTL_REG0); - reg |= (1 << 31); - writel(reg, cec_dev->cec_reg + AO_CECB_CLK_CNTL_REG0); - - udelay(200); - reg |= (1 << 30); - writel(reg, cec_dev->cec_reg + AO_CECB_CLK_CNTL_REG0); - - reg = readl(cec_dev->cec_reg + AO_RTI_PWR_CNTL_REG0); - reg |= (0x01 << 14); /* xtal gate */ - writel(reg, cec_dev->cec_reg + AO_RTI_PWR_CNTL_REG0); - - data32 = 0; - data32 |= (7 << 12); /* filter_del */ - data32 |= (1 << 8); /* filter_tick: 1us */ - data32 |= (1 << 3); /* enable system clock */ - data32 |= 0 << 1; /* [2:1] cntl_clk: */ - /* 0=Disable clk (Power-off mode); */ - /* 1=Enable gated clock (Normal mode); */ - /* 2=Enable free-run clk (Debug mode). */ - data32 |= 1 << 0; /* [0] sw_reset: 1=Reset */ - writel(data32, cec_dev->cec_reg + AO_CECB_GEN_CNTL); - /* Enable gated clock (Normal mode). */ - cec_set_reg_bits(AO_CECB_GEN_CNTL, 1, 1, 1); - /* Release SW reset */ - cec_set_reg_bits(AO_CECB_GEN_CNTL, 0, 0, 1); - - /* Enable all AO_CECB interrupt sources */ - cec_irq_enable(true); - hdmirx_cec_write(DWC_CEC_WKUPCTRL, WAKEUP_EN_MASK); -} - -void eecec_irq_enable(bool enable) -{ - if (cec_dev->cpu_type < MESON_CPU_MAJOR_ID_TXLX) { - if (enable) - hdmirx_cec_write(DWC_AUD_CEC_IEN_SET, - EE_CEC_IRQ_EN_MASK); - else { - hdmirx_cec_write(DWC_AUD_CEC_ICLR, - (~(hdmirx_cec_read(DWC_AUD_CEC_IEN)) | - EE_CEC_IRQ_EN_MASK)); - hdmirx_cec_write(DWC_AUD_CEC_IEN_SET, - hdmirx_cec_read(DWC_AUD_CEC_IEN) & - ~EE_CEC_IRQ_EN_MASK); - hdmirx_cec_write(DWC_AUD_CEC_IEN_CLR, - (~(hdmirx_cec_read(DWC_AUD_CEC_IEN)) | - EE_CEC_IRQ_EN_MASK)); - } - CEC_INFO("ee enable:int mask:0x%x\n", - hdmirx_cec_read(DWC_AUD_CEC_IEN)); - } else { - if (enable) - writel(CECB_IRQ_EN_MASK, - cec_dev->cec_reg + AO_CECB_INTR_MASKN); - else - writel(readl(cec_dev->cec_reg + AO_CECB_INTR_MASKN) - & ~CECB_IRQ_EN_MASK, - cec_dev->cec_reg + AO_CECB_INTR_MASKN); - CEC_INFO("ao move enable:int mask:0x%x\n", - readl(cec_dev->cec_reg + AO_CECB_INTR_MASKN)); - } -} - -void cec_irq_enable(bool enable) -{ - if (ee_cec) - eecec_irq_enable(enable); - else - aocec_irq_enable(enable); -} - -int cecrx_hw_init(void) -{ - unsigned int data32; - - if (!ee_cec) - return -1; - cecrx_hw_reset(); if (!cec_dev->plat_data->ee_to_ao) { /* set cec clk 32768k */ data32 = readl(cec_dev->hhi_reg + HHI_32K_CLK_CNTL); @@ -618,18 +542,125 @@ int cecrx_hw_init(void) hdmirx_set_bits_top(TOP_EDID_GEN_CNTL, EDID_AUTO_CEC_EN, 11, 1); /* enable all cec irq */ - cec_irq_enable(true); + /*cec_irq_enable(true);*/ /* clear all wake up source */ hdmirx_cec_write(DWC_CEC_WKUPCTRL, 0); /* cec enable */ hdmirx_set_bits_dwc(DWC_DMI_DISABLE_IF, 1, 5, 1); - } else - ao_cecb_init(); + } else { + reg = (0 << 31) | + (0 << 30) | + (1 << 28) | /* clk_div0/clk_div1 in turn */ + ((732-1) << 12) |/* Div_tcnt1 */ + ((733-1) << 0); /* Div_tcnt0 */ + writel(reg, cec_dev->cec_reg + AO_CECB_CLK_CNTL_REG0); + reg = (0 << 13) | + ((11-1) << 12) | + ((8-1) << 0); + writel(reg, cec_dev->cec_reg + AO_CECB_CLK_CNTL_REG1); + + reg = readl(cec_dev->cec_reg + AO_CECB_CLK_CNTL_REG0); + reg |= (1 << 31); + writel(reg, cec_dev->cec_reg + AO_CECB_CLK_CNTL_REG0); + + udelay(200); + reg |= (1 << 30); + writel(reg, cec_dev->cec_reg + AO_CECB_CLK_CNTL_REG0); + + reg = readl(cec_dev->cec_reg + AO_RTI_PWR_CNTL_REG0); + reg |= (0x01 << 14); /* xtal gate */ + writel(reg, cec_dev->cec_reg + AO_RTI_PWR_CNTL_REG0); + + data32 = 0; + data32 |= (7 << 12); /* filter_del */ + data32 |= (1 << 8); /* filter_tick: 1us */ + data32 |= (1 << 3); /* enable system clock */ + data32 |= 0 << 1; /* [2:1] cntl_clk: */ + /* 0=Disable clk (Power-off mode); */ + /* 1=Enable gated clock (Normal mode); */ + /* 2=Enable free-run clk (Debug mode). */ + data32 |= 1 << 0; /* [0] sw_reset: 1=Reset */ + writel(data32, cec_dev->cec_reg + AO_CECB_GEN_CNTL); + /* Enable gated clock (Normal mode). */ + cec_set_reg_bits(AO_CECB_GEN_CNTL, 1, 1, 1); + /* Release SW reset */ + cec_set_reg_bits(AO_CECB_GEN_CNTL, 0, 0, 1); + + if (cec_dev->plat_data->cecb_ver >= CECB_VER_2) { + reg = 0; + reg |= (0 << 6);/*curb_err_init*/ + reg |= (0 << 5);/*en_chk_sbitlow*/ + reg |= (2 << 0);/*rise_del_max*/ + hdmirx_cec_write(DWC_CEC_CTRL2, reg); + } + + /* Enable all AO_CECB interrupt sources */ + /*cec_irq_enable(true);*/ + hdmirx_cec_write(DWC_CEC_WKUPCTRL, WAKEUP_EN_MASK); + } +} + +void eecec_irq_enable(bool enable) +{ + if (cec_dev->cpu_type < MESON_CPU_MAJOR_ID_TXLX) { + if (enable) + hdmirx_cec_write(DWC_AUD_CEC_IEN_SET, + EE_CEC_IRQ_EN_MASK); + else { + hdmirx_cec_write(DWC_AUD_CEC_ICLR, + (~(hdmirx_cec_read(DWC_AUD_CEC_IEN)) | + EE_CEC_IRQ_EN_MASK)); + hdmirx_cec_write(DWC_AUD_CEC_IEN_SET, + hdmirx_cec_read(DWC_AUD_CEC_IEN) & + ~EE_CEC_IRQ_EN_MASK); + hdmirx_cec_write(DWC_AUD_CEC_IEN_CLR, + (~(hdmirx_cec_read(DWC_AUD_CEC_IEN)) | + EE_CEC_IRQ_EN_MASK)); + } + CEC_INFO("cecb enable:int mask:0x%x\n", + hdmirx_cec_read(DWC_AUD_CEC_IEN)); + } else { + if (enable) + writel(CECB_IRQ_EN_MASK, + cec_dev->cec_reg + AO_CECB_INTR_MASKN); + else + writel(readl(cec_dev->cec_reg + AO_CECB_INTR_MASKN) + & ~CECB_IRQ_EN_MASK, + cec_dev->cec_reg + AO_CECB_INTR_MASKN); + CEC_INFO("cecb enable:int mask:0x%x\n", + readl(cec_dev->cec_reg + AO_CECB_INTR_MASKN)); + } +} + +void cec_irq_enable(bool enable) +{ + if (cec_dev->cec_num > 1) { + eecec_irq_enable(enable); + aocec_irq_enable(enable); + } else { + if (ee_cec == CEC_B) + eecec_irq_enable(enable); + else + aocec_irq_enable(enable); + } +} + +/* +int cecrx_hw_init(void) +{ + unsigned int data32; + + if (ee_cec == CEC_A) + return -1; + + cecb_hw_reset(); + + ao_cecb_init(); cec_logicaddr_set(cec_dev->cec_info.log_addr); return 0; } - +*/ static int dump_cecrx_reg(char *b) { int i = 0, s = 0; @@ -668,11 +699,17 @@ static int dump_cecrx_reg(char *b) s += sprintf(b + s, "CEC MODULE REGS:\n"); s += sprintf(b + s, "CEC_CTRL = 0x%02x\n", hdmirx_cec_read(0x1f00)); + if (cec_dev->plat_data->cecb_ver >= CECB_VER_2) + s += sprintf(b + s, "CEC_CTRL2 = 0x%02x\n", + hdmirx_cec_read(0x1f04)); s += sprintf(b + s, "CEC_MASK = 0x%02x\n", hdmirx_cec_read(0x1f08)); s += sprintf(b + s, "CEC_ADDR_L = 0x%02x\n", hdmirx_cec_read(0x1f14)); s += sprintf(b + s, "CEC_ADDR_H = 0x%02x\n", hdmirx_cec_read(0x1f18)); s += sprintf(b + s, "CEC_TX_CNT = 0x%02x\n", hdmirx_cec_read(0x1f1c)); s += sprintf(b + s, "CEC_RX_CNT = 0x%02x\n", hdmirx_cec_read(0x1f20)); + if (cec_dev->plat_data->cecb_ver >= CECB_VER_2) + s += sprintf(b + s, "CEC_STAT0 = 0x%02x\n", + hdmirx_cec_read(0x1f24)); s += sprintf(b + s, "CEC_LOCK = 0x%02x\n", hdmirx_cec_read(0x1fc0)); s += sprintf(b + s, "CEC_WKUPCTRL = 0x%02x\n", hdmirx_cec_read(0x1fc4)); @@ -722,33 +759,139 @@ void cec_logicaddr_set(int l_add) { /* save logical address for suspend/wake up */ cec_set_reg_bits(AO_DEBUG_REG1, l_add, 16, 4); - if (ee_cec) { + cec_dev->cec_info.addr_enable = (1 << l_add); + if (ee_cec == CEC_B) { /* set ee_cec logical addr */ if (l_add < 8) hdmirx_cec_write(DWC_CEC_ADDR_L, 1 << l_add); else - hdmirx_cec_write(DWC_CEC_ADDR_H, 1 << (l_add - 8)|0x80); + hdmirx_cec_write(DWC_CEC_ADDR_H, 1 << (l_add - 8)); CEC_INFO("set cecb logical addr:0x%x\n", l_add); - return; + } else { + /*clear all logical address*/ + aocec_wr_reg(CEC_LOGICAL_ADDR0, 0); + aocec_wr_reg(CEC_LOGICAL_ADDR1, 0); + aocec_wr_reg(CEC_LOGICAL_ADDR2, 0); + aocec_wr_reg(CEC_LOGICAL_ADDR3, 0); + aocec_wr_reg(CEC_LOGICAL_ADDR4, 0); + + cec_hw_buf_clear(); + aocec_wr_reg(CEC_LOGICAL_ADDR0, (l_add & 0xf)); + udelay(100); + aocec_wr_reg(CEC_LOGICAL_ADDR0, (0x1 << 4) | (l_add & 0xf)); + if (cec_msg_dbg_en) + CEC_INFO("set cec alogical addr:0x%x\n", + aocec_rd_reg(CEC_LOGICAL_ADDR0)); } - aocec_wr_reg(CEC_LOGICAL_ADDR0, 0); - cec_hw_buf_clear(); - aocec_wr_reg(CEC_LOGICAL_ADDR0, (l_add & 0xf)); - udelay(100); - aocec_wr_reg(CEC_LOGICAL_ADDR0, (0x1 << 4) | (l_add & 0xf)); - if (cec_msg_dbg_en) - CEC_INFO("set cec alogical addr:0x%x\n", - aocec_rd_reg(CEC_LOGICAL_ADDR0)); } -void cec_hw_reset(void) +void ceca_addr_add(unsigned int l_add) { - if (ee_cec) { - cecrx_hw_init(); - return; + unsigned int addr; + unsigned int i; + + /* check if the logical addr is exist ? */ + for (i = CEC_LOGICAL_ADDR0; i <= CEC_LOGICAL_ADDR4; i++) { + addr = aocec_rd_reg(i); + if ((addr & 0x10) && ((addr & 0xf) == (l_add & 0xf))) { + CEC_INFO("add 0x%x exist\n", l_add); + return; + } } + /* find a empty place */ + for (i = CEC_LOGICAL_ADDR0; i <= CEC_LOGICAL_ADDR4; i++) { + addr = aocec_rd_reg(i); + if (addr & 0x10) { + CEC_INFO(" skip 0x%x ,val=0x%x\n", i, addr); + continue; + } else { + cec_hw_buf_clear(); + aocec_wr_reg(i, (l_add & 0xf)); + udelay(100); + aocec_wr_reg(i, (l_add & 0xf)|0x10); + CEC_INFO("cec a add addr %d at 0x%x\n", + l_add, i); + break; + } + } +} + +void cecb_addr_add(unsigned int l_add) +{ + unsigned int addr; + + if (l_add < 8) { + addr = hdmirx_cec_read(DWC_CEC_ADDR_L); + addr |= (1 << l_add); + hdmirx_cec_write(DWC_CEC_ADDR_L, addr); + } else { + addr = hdmirx_cec_read(DWC_CEC_ADDR_H); + addr |= (1 << (l_add - 8)); + hdmirx_cec_write(DWC_CEC_ADDR_H, addr); + } + CEC_INFO("cec b add addr %d\n", l_add); +} + +void cec_logicaddr_add(unsigned int cec_sel, unsigned int l_add) +{ + /* save logical address for suspend/wake up */ + cec_set_reg_bits(AO_DEBUG_REG1, l_add, 16, 4); + + if (cec_sel == CEC_B) + cecb_addr_add(l_add); + else + ceca_addr_add(l_add); +} + +void cec_logicaddr_remove(unsigned int cec_sel, unsigned int l_add) +{ + unsigned int addr; + unsigned int i; + + if (cec_sel == CEC_B) { + if (l_add < 8) { + addr = hdmirx_cec_read(DWC_CEC_ADDR_L); + addr &= ~(1 << l_add); + hdmirx_cec_write(DWC_CEC_ADDR_L, addr); + } else { + addr = hdmirx_cec_read(DWC_CEC_ADDR_H); + addr &= ~(1 << (l_add - 8)); + hdmirx_cec_write(DWC_CEC_ADDR_H, addr); + } + CEC_INFO("cec b remove addr %d\n", l_add); + } else { + for (i = CEC_LOGICAL_ADDR0; i <= CEC_LOGICAL_ADDR4; i++) { + addr = aocec_rd_reg(i); + if ((addr & 0xf) == (l_add & 0xf)) { + aocec_wr_reg(i, (addr & 0xf)); + udelay(100); + aocec_wr_reg(i, 0); + cec_hw_buf_clear(); + CEC_INFO("cec a rm addr %d at 0x%x\n", + l_add, i); + } + } + } +} + +void cec_restore_logical_addr(unsigned int cec_sel, unsigned int addr_en) +{ + unsigned int i; + unsigned int addr_enable = addr_en; + + cec_clear_all_logical_addr(cec_sel); + for (i = 0; i < 15; i++) { + if (addr_enable & 0x1) + cec_logicaddr_add(cec_sel, i); + + addr_enable = addr_enable >> 1; + } +} + +void ceca_hw_reset(void) +{ writel(0x1, cec_dev->cec_reg + AO_CEC_GEN_CNTL); /* Enable gated clock (Normal mode). */ cec_set_reg_bits(AO_CEC_GEN_CNTL, 1, 1, 1); @@ -757,17 +900,26 @@ void cec_hw_reset(void) cec_set_reg_bits(AO_CEC_GEN_CNTL, 0, 0, 1); /* Enable all AO_CEC interrupt sources */ - cec_irq_enable(true); + /*cec_irq_enable(true);*/ - cec_logicaddr_set(cec_dev->cec_info.log_addr); + /* cec_logicaddr_set(cec_dev->cec_info.log_addr); */ /* Cec arbitration 3/5/7 bit time set. */ cec_arbit_bit_time_set(3, 0x118, 0); cec_arbit_bit_time_set(5, 0x000, 0); cec_arbit_bit_time_set(7, 0x2aa, 0); +} - CEC_INFO("hw reset :logical addr:0x%x\n", - aocec_rd_reg(CEC_LOGICAL_ADDR0)); +void cec_hw_reset(unsigned int cec_sel) +{ + if (cec_sel == CEC_B) { + ao_cecb_init(); + /* cec_logicaddr_set(cec_dev->cec_info.log_addr); */ + } else { + ceca_hw_reset(); + } + /* cec_logicaddr_set(cec_dev->cec_info.log_addr); */ + cec_restore_logical_addr(cec_sel, cec_dev->cec_info.addr_enable); } void cec_rx_buf_clear(void) @@ -815,48 +967,64 @@ static bool need_nack_repeat_msg(const unsigned char *msg, int len, int t) return false; } -static void cec_clear_logical_addr(void) +void cec_clear_all_logical_addr(unsigned int cec_sel) { - CEC_INFO("clear logical addr\n"); + CEC_INFO("clear all logical addr\n"); - if (ee_cec) { + if (cec_sel == CEC_B) { hdmirx_cec_write(DWC_CEC_ADDR_L, 0); - hdmirx_cec_write(DWC_CEC_ADDR_H, 0x80); - } else + hdmirx_cec_write(DWC_CEC_ADDR_H, 0); + } else { aocec_wr_reg(CEC_LOGICAL_ADDR0, 0); - udelay(100); + aocec_wr_reg(CEC_LOGICAL_ADDR1, 0); + aocec_wr_reg(CEC_LOGICAL_ADDR2, 0); + aocec_wr_reg(CEC_LOGICAL_ADDR3, 0); + aocec_wr_reg(CEC_LOGICAL_ADDR4, 0); + } + /*udelay(100);*/ } void cec_enable_arc_pin(bool enable) { - /* select arc according arg */ - if (enable) - hdmirx_wr_top(TOP_ARCTX_CNTL, 0x01); - else - hdmirx_wr_top(TOP_ARCTX_CNTL, 0x00); - CEC_INFO("set arc en:%d, reg:%lx\n", - enable, hdmirx_rd_top(TOP_ARCTX_CNTL)); + unsigned int data; + + if (cec_dev->plat_data->cecb_ver >= CECB_VER_2) { + data = rd_reg_hhi(HHI_HDMIRX_ARC_CNTL); + /* enable bit 1:1 bit 0: 0*/ + if (enable) + data |= 0x02; + else + data &= 0xfffffffd; + wr_reg_hhi(HHI_HDMIRX_ARC_CNTL, data); + CEC_INFO("set arc en:%d, reg:%x\n", enable, data); + } else { + /* select arc according arg */ + if (enable) + hdmirx_wr_top(TOP_ARCTX_CNTL, 0x01); + else + hdmirx_wr_top(TOP_ARCTX_CNTL, 0x00); + CEC_INFO("set arc en:%d, reg:%lx\n", + enable, hdmirx_rd_top(TOP_ARCTX_CNTL)); + } } EXPORT_SYMBOL(cec_enable_arc_pin); int cec_rx_buf_check(void) { - unsigned int rx_num_msg; + unsigned int rx_num_msg = 0; - if (ee_cec) { + if (ee_cec == CEC_B) { cecrx_check_irq_enable(); - cecrx_irq_handle(); - return 0; + cecb_irq_handle(); + } else { + rx_num_msg = aocec_rd_reg(CEC_RX_NUM_MSG); + if (rx_num_msg) + CEC_INFO("rx msg num:0x%02x\n", rx_num_msg); } - - rx_num_msg = aocec_rd_reg(CEC_RX_NUM_MSG); - if (rx_num_msg) - CEC_INFO("rx msg num:0x%02x\n", rx_num_msg); - return rx_num_msg; } -int cec_ll_rx(unsigned char *msg, unsigned char *len) +int ceca_rx_irq_handle(unsigned char *msg, unsigned char *len) { int i; int ret = -1; @@ -873,6 +1041,16 @@ int cec_ll_rx(unsigned char *msg, unsigned char *len) return ret; } + /* when use two cec ip, cec a only send msg, discard all rx msg */ + if (cec_dev->cec_num > 1) { + writel((1 << 2), cec_dev->cec_reg + AO_CEC_INTR_CLR); + aocec_wr_reg(CEC_RX_MSG_CMD, RX_ACK_CURRENT); + aocec_wr_reg(CEC_RX_MSG_CMD, RX_NO_OP); + cec_rx_buf_clear(); + CEC_INFO("discard msg\n"); + return ret; + } + *len = aocec_rd_reg(CEC_RX_MSG_LENGTH) + 1; for (i = 0; i < (*len) && i < MAX_MSG; i++) @@ -884,7 +1062,7 @@ int cec_ll_rx(unsigned char *msg, unsigned char *len) if (cec_msg_dbg_en && *len > 1) { pos = 0; pos += sprintf(msg_log_buf + pos, - "CEC: rx msg len: %d dat: ", *len); + "cec: rx len: %d dat: ", *len); for (i = 0; i < (*len); i++) pos += sprintf(msg_log_buf + pos, "%02x ", msg[i]); pos += sprintf(msg_log_buf + pos, "\n"); @@ -904,7 +1082,7 @@ int cec_ll_rx(unsigned char *msg, unsigned char *len) /* using the cec pin as fiq gpi to assist the bus arbitration */ /* return value: 1: successful 0: error */ -static int cec_ll_trigle_tx(const unsigned char *msg, int len) +static int ceca_trigle_tx(const unsigned char *msg, int len) { int i; unsigned int n; @@ -920,11 +1098,11 @@ static int cec_ll_trigle_tx(const unsigned char *msg, int len) break; if (!(j--)) { - CEC_INFO("waiting busy timeout\n"); + CEC_INFO("ceca waiting busy timeout\n"); aocec_wr_reg(CEC_TX_MSG_CMD, TX_ABORT); cec_timeout_cnt++; if (cec_timeout_cnt > 0x08) - cec_hw_reset(); + cec_hw_reset(CEC_A); break; } msleep(20); @@ -941,7 +1119,7 @@ static int cec_ll_trigle_tx(const unsigned char *msg, int len) if (cec_msg_dbg_en) { pos = 0; pos += sprintf(msg_log_buf + pos, - "CEC: tx msg len: %d dat: ", len); + "cec: tx len: %d dat: ", len); for (n = 0; n < len; n++) { pos += sprintf(msg_log_buf + pos, "%02x ", msg[n]); @@ -959,7 +1137,7 @@ static int cec_ll_trigle_tx(const unsigned char *msg, int len) return -1; } -void tx_irq_handle(void) +void ceca_tx_irq_handle(void) { unsigned int tx_status = aocec_rd_reg(CEC_TX_MSG_STATUS); @@ -977,9 +1155,12 @@ void tx_irq_handle(void) case TX_ERROR: if (cec_msg_dbg_en) - CEC_ERR("TX ERROR!!!\n"); + CEC_ERR("TX ERROR!\n"); aocec_wr_reg(CEC_TX_MSG_CMD, TX_ABORT); - cec_hw_reset(); + ceca_hw_reset(); + if (cec_dev->cec_num <= 1) + cec_restore_logical_addr(CEC_A, + cec_dev->cec_info.addr_enable); cec_tx_result = CEC_FAIL_NACK; break; @@ -1060,14 +1241,27 @@ static bool check_physical_addr_valid(int timeout) int cec_ll_tx(const unsigned char *msg, unsigned char len) { int ret = -1; - int t = msecs_to_jiffies(ee_cec ? 2000 : 5000); + int t; int retry = 2; + unsigned int cec_sel; + + /* only use cec a send msg */ + if (cec_dev->cec_num > 1) + cec_sel = CEC_A; + else + cec_sel = ee_cec; + + t = msecs_to_jiffies((cec_sel == CEC_B) ? 2000 : 5000); if (len == 0) return CEC_FAIL_NONE; + /* + * AO CEC controller will ack poll message itself if logical + * address already set. Must clear it before poll again + */ if (is_poll_message(msg[0])) - cec_clear_logical_addr(); + cec_clear_all_logical_addr(cec_sel); /* * for CEC CTS 9.3. Android will try 3 poll message if got NACK @@ -1076,7 +1270,7 @@ int cec_ll_tx(const unsigned char *msg, unsigned char len) * waveform seen on CEC bus. And did not pass CTS * specification of 9.3 */ - if (!ee_cec && need_nack_repeat_msg(msg, len, t)) { + if ((cec_sel == CEC_A) && need_nack_repeat_msg(msg, len, t)) { if (!memcmp(msg, last_cec_msg->msg, len)) { CEC_INFO("NACK repeat message:%x\n", len); return CEC_FAIL_NACK; @@ -1102,10 +1296,10 @@ try_again: return CEC_FAIL_BUSY; } - if (ee_cec) - ret = cecrx_trigle_tx(msg, len); + if (cec_sel == CEC_B) + ret = cecb_trigle_tx(msg, len); else - ret = cec_ll_trigle_tx(msg, len); + ret = ceca_trigle_tx(msg, len); if (ret < 0) { /* we should increase send idx if busy */ CEC_INFO("tx busy\n"); @@ -1123,7 +1317,7 @@ try_again: /* timeout or interrupt */ if (ret == 0) { CEC_ERR("tx timeout\n"); - cec_hw_reset(); + cec_hw_reset(cec_sel); } ret = CEC_FAIL_OTHER; } else { @@ -1138,7 +1332,7 @@ try_again: } mutex_unlock(&cec_dev->cec_mutex); - if (!ee_cec) { + if (cec_sel == CEC_A) { last_cec_msg->last_result = ret; if (ret == CEC_FAIL_NACK) { memcpy(last_cec_msg->msg, msg, len); @@ -1159,7 +1353,6 @@ static void ao_ceca_init(void) unsigned int chiptype; chiptype = get_meson_cpu_version(MESON_CPU_VERSION_LVL_MAJOR); - /*CEC_INFO("chiptype=0x%x\n", chiptype);*/ if (chiptype >= MESON_CPU_MAJOR_ID_GXBB) { if (cec_dev->plat_data->ee_to_ao) { @@ -1245,7 +1438,11 @@ static void ao_ceca_init(void) cec_set_reg_bits(AO_CEC_GEN_CNTL, 0, 0, 1); /* Enable all AO_CEC interrupt sources */ - cec_irq_enable(true); + /*cec_irq_enable(true);*/ + + cec_arbit_bit_time_set(3, 0x118, 0); + cec_arbit_bit_time_set(5, 0x000, 0); + cec_arbit_bit_time_set(7, 0x2aa, 0); } void cec_arbit_bit_time_set(unsigned int bit_set, @@ -1341,13 +1538,16 @@ unsigned int cec_phyaddr_config(unsigned int value, bool wr_flag) return readl(cec_dev->cec_reg + AO_DEBUG_REG1); } +/* void cec_keep_reset(void) { - if (ee_cec) - cecrx_hw_reset(); + if (ee_cec == CEC_B) + cecb_hw_reset(); else writel(0x1, cec_dev->cec_reg + AO_CEC_GEN_CNTL); } +*/ + /* * cec hw module init before allocate logical address */ @@ -1360,15 +1560,21 @@ static void cec_pre_init(void) wake_ok = 0; pr_info("cec: wake up flag:%x\n", reg); - if (ee_cec) { - cecrx_hw_init(); - } else { + if (cec_dev->cec_num > 1) { ao_ceca_init(); - - cec_arbit_bit_time_set(3, 0x118, 0); - cec_arbit_bit_time_set(5, 0x000, 0); - cec_arbit_bit_time_set(7, 0x2aa, 0); + ao_cecb_init(); + } else { + if (ee_cec == CEC_B) + ao_cecb_init(); + else + ao_ceca_init(); } + + //need restore all logical address + if (cec_dev->cec_num > 1) + cec_restore_logical_addr(CEC_B, cec_dev->cec_info.addr_enable); + else + cec_restore_logical_addr(ee_cec, cec_dev->cec_info.addr_enable); } static int cec_late_check_rx_buffer(void) @@ -1382,7 +1588,7 @@ static int cec_late_check_rx_buffer(void) /* * start another check if rx buffer is full */ - if ((-1) == cec_ll_rx(rx_msg, &rx_len)) { + if ((-1) == ceca_rx_irq_handle(rx_msg, &rx_len)) { CEC_INFO("buffer got unrecorgnized msg\n"); cec_rx_buf_clear(); return 0; @@ -1627,7 +1833,7 @@ static void cec_rx_process(void) case CEC_OC_SET_STREAM_PATH: cec_set_stream_path(msg); /* wake up if in early suspend */ - if (cec_dev->cec_suspend == CEC_EARLY_SUSPEND) + if (cec_dev->cec_suspend != CEC_POWER_ON) cec_key_report(0); break; @@ -1649,7 +1855,7 @@ static void cec_rx_process(void) case CEC_OC_USER_CONTROL_PRESSED: /* wake up by key function */ - if (cec_dev->cec_suspend == CEC_EARLY_SUSPEND) { + if (cec_dev->cec_suspend != CEC_POWER_ON) { if (msg[2] == 0x40 || msg[2] == 0x6d) cec_key_report(0); } @@ -1717,18 +1923,19 @@ static void cec_task(struct work_struct *work) queue_delayed_work(cec_dev->cec_thread, dwork, CEC_FRAME_DELAY); } -static irqreturn_t ceca_isr_handler(int irq, void *dev_instance) +static irqreturn_t ceca_isr(int irq, void *dev_instance) { unsigned int intr_stat = 0; struct delayed_work *dwork; + /*CEC_INFO("ceca_isr\n");*/ dwork = &cec_dev->cec_work; intr_stat = cec_intr_stat(); if (intr_stat & (1<<1)) { /* aocec tx intr */ - tx_irq_handle(); + ceca_tx_irq_handle(); return IRQ_HANDLED; } - if ((-1) == cec_ll_rx(rx_msg, &rx_len)) + if ((-1) == ceca_rx_irq_handle(rx_msg, &rx_len)) return IRQ_HANDLED; complete(&cec_dev->rx_ok); @@ -1835,12 +2042,23 @@ static const char * const cec_reg_name2[] = { "CEC_TX_NUM_MSG" }; +static const char * const ceca_reg_name3[] = { + "STAT_0_0", + "STAT_0_1", + "STAT_0_2", + "STAT_0_3", + "STAT_1_0", + "STAT_1_1", + "STAT_1_2" +}; + + static ssize_t dump_reg_show(struct class *cla, struct class_attribute *attr, char *b) { int i, s = 0; - if (ee_cec) + if (ee_cec == CEC_B) return dump_cecrx_reg(b); s += sprintf(b + s, "TX buffer:\n"); @@ -1860,6 +2078,14 @@ static ssize_t dump_reg_show(struct class *cla, s += sprintf(b + s, "%s:%2x\n", cec_reg_name2[i], aocec_rd_reg(i + 0x90)); } + + if (cec_dev->plat_data->ceca_sts_reg) { + for (i = 0; i < ARRAY_SIZE(ceca_reg_name3); i++) { + s += sprintf(b + s, "%s:%2x\n", + ceca_reg_name3[i], aocec_rd_reg(i + 0xA0)); + } + } + return s; } @@ -2028,7 +2254,7 @@ static ssize_t fun_cfg_store(struct class *cla, struct class_attribute *attr, return -EINVAL; cec_config(val, 1); if (val == 0) - cec_clear_logical_addr();/*cec_keep_reset();*/ + cec_clear_all_logical_addr(ee_cec);/*cec_keep_reset();*/ else cec_pre_init(); return count; @@ -2167,6 +2393,40 @@ static ssize_t dbg_store(struct class *cla, struct class_attribute *attr, CEC_ERR("wao addr:0x%x, val:0x%x", val, addr); } else if (token && strncmp(token, "preinit", 7) == 0) { cec_pre_init(); + } else if (token && strncmp(token, "setaddr", 7) == 0) { + token = strsep(&cur, delim); + /*string to int*/ + if (!token || kstrtouint(token, 16, &addr) < 0) + return count; + + cec_logicaddr_set(addr); + } else if (token && strncmp(token, "clraddr", 7) == 0) { + cec_dev->cec_info.addr_enable = 0; + cec_clear_all_logical_addr(ee_cec); + } else if (token && strncmp(token, "clralladdr", 10) == 0) { + cec_dev->cec_info.addr_enable = 0; + cec_clear_all_logical_addr(0); + cec_clear_all_logical_addr(1); + } else if (token && strncmp(token, "addaddr", 7) == 0) { + token = strsep(&cur, delim); + /*string to int*/ + if (!token || kstrtouint(token, 16, &addr) < 0) + return count; + cec_dev->cec_info.addr_enable |= (1 << (addr & 0xf)); + if (cec_dev->cec_num > 1) + cec_logicaddr_add(CEC_B, addr); + else + cec_logicaddr_add(ee_cec, addr); + } else if (token && strncmp(token, "rmaddr", 6) == 0) { + token = strsep(&cur, delim); + /*string to int*/ + if (!token || kstrtouint(token, 16, &addr) < 0) + return count; + cec_dev->cec_info.addr_enable &= ~(1 << (addr & 0xf)); + if (cec_dev->cec_num > 1) + cec_logicaddr_remove(CEC_B, addr); + else + cec_logicaddr_remove(ee_cec, addr); } else { if (token) CEC_ERR("no cmd:%s\n", token); @@ -2230,12 +2490,19 @@ static ssize_t hdmitx_cec_read(struct file *f, char __user *buf, if ((cec_dev->hal_flag & (1 << HDMI_OPTION_SYSTEM_CEC_CONTROL))) rx_len = 0; + /*CEC_ERR("read msg start\n");*/ ret = wait_for_completion_timeout(&cec_dev->rx_ok, CEC_FRAME_DELAY); - if (ret <= 0) + if (ret <= 0) { + /*CEC_ERR("read msg ret=0\n");*/ return ret; - if (rx_len == 0) - return 0; + } + if (rx_len == 0) { + /*CEC_ERR("read msg rx_len=0\n");*/ + return 0; + } + + /*CEC_ERR("read msg end\n");*/ if (copy_to_user(buf, rx_msg, rx_len)) return -EINVAL; return rx_len; @@ -2348,6 +2615,9 @@ void cec_dump_info(void) { struct hdmi_port_info *port; + CEC_ERR("driver date:%s\n", CEC_DRIVER_VERSION); + CEC_ERR("cec sel:%d\n", ee_cec); + CEC_ERR("cec_num:%d\n", cec_dev->cec_num); CEC_ERR("dev_type:%d\n", (unsigned int)cec_dev->dev_type); CEC_ERR("wk_logic_addr:0x%x\n", cec_dev->wakup_data.wk_logic_addr); CEC_ERR("wk_phy_addr:0x%x\n", cec_dev->wakup_data.wk_phy_addr); @@ -2372,6 +2642,36 @@ void cec_dump_info(void) init_cec_port_info(port, cec_dev); kfree(port); } + + if (cec_dev->cec_num > 1) { + CEC_ERR("addrL 0x%x\n", hdmirx_cec_read(DWC_CEC_ADDR_L)); + CEC_ERR("addrH 0x%x\n", hdmirx_cec_read(DWC_CEC_ADDR_H)); + + CEC_ERR("addr0 0x%x\n", aocec_rd_reg(CEC_LOGICAL_ADDR0)); + CEC_ERR("addr1 0x%x\n", aocec_rd_reg(CEC_LOGICAL_ADDR1)); + CEC_ERR("addr2 0x%x\n", aocec_rd_reg(CEC_LOGICAL_ADDR2)); + CEC_ERR("addr3 0x%x\n", aocec_rd_reg(CEC_LOGICAL_ADDR3)); + CEC_ERR("addr4 0x%x\n", aocec_rd_reg(CEC_LOGICAL_ADDR4)); + } else { + if (ee_cec == CEC_B) { + CEC_ERR("addrL 0x%x\n", + hdmirx_cec_read(DWC_CEC_ADDR_L)); + CEC_ERR("addrH 0x%x\n", + hdmirx_cec_read(DWC_CEC_ADDR_H)); + } else { + CEC_ERR("addr0 0x%x\n", + aocec_rd_reg(CEC_LOGICAL_ADDR0)); + CEC_ERR("addr1 0x%x\n", + aocec_rd_reg(CEC_LOGICAL_ADDR1)); + CEC_ERR("addr2 0x%x\n", + aocec_rd_reg(CEC_LOGICAL_ADDR2)); + CEC_ERR("addr3 0x%x\n", + aocec_rd_reg(CEC_LOGICAL_ADDR3)); + CEC_ERR("addr4 0x%x\n", + aocec_rd_reg(CEC_LOGICAL_ADDR4)); + } + } + CEC_ERR("addr_enable:0x%x\n", cec_dev->cec_info.addr_enable); } static long hdmitx_cec_ioctl(struct file *f, @@ -2488,7 +2788,7 @@ static long hdmitx_cec_ioctl(struct file *f, cec_dev->hal_flag &= ~(tmp); CEC_INFO("disable CEC\n"); /*cec_keep_reset();*/ - cec_clear_logical_addr(); + cec_clear_all_logical_addr(ee_cec); } break; @@ -2532,18 +2832,28 @@ static long hdmitx_cec_ioctl(struct file *f, case CEC_IOC_ADD_LOGICAL_ADDR: tmp = arg & 0xf; - cec_logicaddr_set(tmp); + /*cec_logicaddr_set(tmp);*/ + /*cec_logicaddr_add(ee_cec, tmp);*/ + if (cec_dev->cec_num > 1) + cec_logicaddr_add(CEC_B, tmp); + else + cec_logicaddr_add(ee_cec, tmp); + cec_dev->cec_info.addr_enable |= (1 << tmp); + /* add by hal, to init some data structure */ cec_dev->cec_info.log_addr = tmp; cec_dev->cec_info.power_status = POWER_ON; - cec_dev->cec_info.vendor_id = cec_dev->v_data.vendor_id; strncpy(cec_dev->cec_info.osd_name, cec_dev->v_data.cec_osd_string, 14); break; case CEC_IOC_CLR_LOGICAL_ADDR: - cec_clear_logical_addr(); + if (cec_dev->cec_num > 1) + cec_clear_all_logical_addr(CEC_B); + else + cec_clear_all_logical_addr(ee_cec); + cec_dev->cec_info.addr_enable = 0; break; case CEC_IOC_SET_DEV_TYPE: @@ -2642,26 +2952,43 @@ static const struct cec_platform_data_s cec_gxl_data = { .line_reg = 0, .line_bit = 8, .ee_to_ao = 0, + .ceca_sts_reg = 0, + .cecb_ver = CECB_VER_0, }; static const struct cec_platform_data_s cec_txlx_data = { .line_reg = 0, .line_bit = 7, .ee_to_ao = 1, + .ceca_sts_reg = 0, + .cecb_ver = CECB_VER_1, }; static const struct cec_platform_data_s cec_g12a_data = { .line_reg = 1, .line_bit = 3, .ee_to_ao = 1, + .ceca_sts_reg = 0, + .cecb_ver = CECB_VER_1, }; static const struct cec_platform_data_s cec_txl_data = { .line_reg = 0, .line_bit = 7, .ee_to_ao = 0, + .ceca_sts_reg = 0, + .cecb_ver = CECB_VER_0, }; +static const struct cec_platform_data_s cec_tl1_data = { + .line_reg = 0, + .line_bit = 10, + .ee_to_ao = 1, + .ceca_sts_reg = 1, + .cecb_ver = CECB_VER_2, +}; + + static const struct of_device_id aml_cec_dt_match[] = { { .compatible = "amlogic, amlogic-aocec", @@ -2679,10 +3006,23 @@ static const struct of_device_id aml_cec_dt_match[] = { .compatible = "amlogic, aocec-txl", .data = &cec_txl_data, }, + { + .compatible = "amlogic, aocec-tl1", + .data = &cec_tl1_data, + }, {} }; #endif +static void cec_node_val_init(void) +{ + /* initial main logical address */ + cec_dev->cec_info.log_addr = 0; + /* all logical address disable */ + cec_dev->cec_info.addr_enable = 0; + cec_dev->cec_info.open_count.counter = 0; +} + static int aml_cec_probe(struct platform_device *pdev) { struct device *cdev; @@ -2690,7 +3030,7 @@ static int aml_cec_probe(struct platform_device *pdev) const struct of_device_id *of_id; #ifdef CONFIG_OF struct device_node *node = pdev->dev.of_node; - int irq_idx = 0, r; + int r; const char *irq_name = NULL; struct pinctrl *pin; struct vendor_info_data *vend; @@ -2748,19 +3088,12 @@ static int aml_cec_probe(struct platform_device *pdev) else CEC_ERR("unable to get matched device\n"); - cec_dev->cec_info.open_count.counter = 0; + cec_node_val_init(); init_completion(&cec_dev->rx_ok); init_completion(&cec_dev->tx_ok); mutex_init(&cec_dev->cec_mutex); mutex_init(&cec_dev->cec_ioctl_mutex); spin_lock_init(&cec_dev->cec_reg_lock); - cec_dev->cec_thread = create_workqueue("cec_work"); - if (cec_dev->cec_thread == NULL) { - CEC_INFO("create work queue failed\n"); - ret = -EFAULT; - goto tag_cec_threat_err; - } - INIT_DELAYED_WORK(&cec_dev->cec_work, cec_task); cec_dev->cec_info.remote_cec_dev = input_allocate_device(); if (!cec_dev->cec_info.remote_cec_dev) { CEC_INFO("No enough memory\n"); @@ -2785,12 +3118,20 @@ static int aml_cec_probe(struct platform_device *pdev) input_free_device(cec_dev->cec_info.remote_cec_dev); } -#ifdef CONFIG_OF + /* config: read from dts */ + r = of_property_read_u32(node, "cec_sel", &(cec_dev->cec_num)); + if (r) { + CEC_ERR("not find 'port_num'\n"); + cec_dev->cec_num = 0; + } else { + CEC_ERR("use two cec ip\n"); + } + /* if using EE CEC */ if (of_property_read_bool(node, "ee_cec")) - ee_cec = 1; + ee_cec = CEC_B; else - ee_cec = 0; + ee_cec = CEC_A; CEC_ERR("using cec:%d\n", ee_cec); /* pinmux set */ if (of_get_property(node, "pinctrl-names", NULL)) { @@ -2801,7 +3142,7 @@ static int aml_cec_probe(struct platform_device *pdev) if (IS_ERR(cec_dev->dbg_dev->pins->sleep_state)) CEC_ERR("get sleep state error!\n"); /*get active state*/ - if (ee_cec) { + if (ee_cec == CEC_B) { cec_dev->dbg_dev->pins->default_state = pinctrl_lookup_state(pin, "hdmitx_aocecb"); if (IS_ERR(cec_dev->dbg_dev->pins->default_state)) { @@ -2813,7 +3154,7 @@ static int aml_cec_probe(struct platform_device *pdev) CEC_ERR("get default error0\n"); CEC_ERR("use default cec\n"); /*force use default*/ - ee_cec = 0; + ee_cec = CEC_A; } } else { cec_dev->dbg_dev->pins->default_state = @@ -2826,6 +3167,7 @@ static int aml_cec_probe(struct platform_device *pdev) if (ret > 0) CEC_ERR("select state error:0x%x\n", ret); } + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ao_exit"); if (res) { base = devm_ioremap(&pdev->dev, res->start, @@ -2836,7 +3178,8 @@ static int aml_cec_probe(struct platform_device *pdev) } cec_dev->exit_reg = (void *)base; } else - CEC_ERR("no ao_exit regs\n") + CEC_ERR("no ao_exit regs\n"); + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ao"); if (res) { base = devm_ioremap(&pdev->dev, res->start, @@ -2860,7 +3203,8 @@ static int aml_cec_probe(struct platform_device *pdev) } cec_dev->hdmi_rxreg = (void *)base; } else - CEC_ERR("no hdmirx regs\n") + CEC_ERR("no hdmirx regs\n"); + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hhi"); if (res) { base = devm_ioremap(&pdev->dev, res->start, @@ -2882,7 +3226,8 @@ static int aml_cec_probe(struct platform_device *pdev) } cec_dev->periphs_reg = (void *)base; } else - CEC_ERR("no periphs regs\n") + CEC_ERR("no periphs regs\n"); + r = of_property_read_u32(node, "port_num", &(cec_dev->port_num)); if (r) { CEC_ERR("not find 'port_num'\n"); @@ -2929,41 +3274,65 @@ static int aml_cec_probe(struct platform_device *pdev) /* irq set */ cec_irq_enable(false); - if (of_irq_count(node) > 1) { - if (ee_cec) - irq_idx = of_irq_get(node, 0); - else - irq_idx = of_irq_get(node, 1); + /* default enable all function*/ + cec_config(CEC_FUNC_CFG_ALL, 1); + /* for init */ + cec_pre_init(); + /* cec hw module reset */ + if (cec_dev->cec_num > 1) { + cec_hw_reset(CEC_A); + cec_hw_reset(CEC_B); } else { - irq_idx = of_irq_get(node, 0); + cec_hw_reset(ee_cec); } - cec_dev->irq_cec = irq_idx; - CEC_ERR("irq cnt:%d,cur no:%d\n", of_irq_count(node), irq_idx); + + if (of_irq_count(node) > 1) { + /* need enable two irq */ + cec_dev->irq_cecb = of_irq_get(node, 0);/*cecb int*/ + cec_dev->irq_ceca = of_irq_get(node, 1);/*ceca int*/ + } else { + cec_dev->irq_cecb = of_irq_get(node, 0); + cec_dev->irq_ceca = cec_dev->irq_cecb; + } + + CEC_ERR("irq cnt:%d\n", of_irq_count(node)); if (of_get_property(node, "interrupt-names", NULL)) { r = of_property_read_string(node, "interrupt-names", &irq_name); - if (!r && !ee_cec) { - r = request_irq(irq_idx, &ceca_isr_handler, IRQF_SHARED, - irq_name, (void *)cec_dev); + if (cec_dev->cec_num > 1) { + /* request two int source */ + CEC_ERR("request_irq two irq src\n"); + r = request_irq(cec_dev->irq_ceca, &ceca_isr, + IRQF_SHARED, irq_name, (void *)cec_dev); if (r < 0) CEC_INFO("aocec irq request fail\n"); - } - if (!r && ee_cec) { - r = request_irq(irq_idx, &cecb_rx_isr, IRQF_SHARED, - irq_name, (void *)cec_dev); + + r = request_irq(cec_dev->irq_cecb, &cecb_isr, + IRQF_SHARED, irq_name, (void *)cec_dev); if (r < 0) CEC_INFO("cecb irq request fail\n"); + } else { + if (!r && (ee_cec == CEC_A)) { + r = request_irq(cec_dev->irq_ceca, &ceca_isr, + IRQF_SHARED, irq_name, (void *)cec_dev); + if (r < 0) + CEC_INFO("aocec irq request fail\n"); + } + + if (!r && (ee_cec == CEC_B)) { + r = request_irq(cec_dev->irq_cecb, &cecb_isr, + IRQF_SHARED, irq_name, (void *)cec_dev); + if (r < 0) + CEC_INFO("cecb irq request fail\n"); + } } } -#endif - if (!ee_cec) { - last_cec_msg = devm_kzalloc(&pdev->dev, - sizeof(*last_cec_msg), GFP_KERNEL); - if (!last_cec_msg) { - CEC_ERR("allocate last_cec_msg failed\n"); - ret = -ENOMEM; - goto tag_cec_msg_alloc_err; - } + last_cec_msg = devm_kzalloc(&pdev->dev, + sizeof(*last_cec_msg), GFP_KERNEL); + if (!last_cec_msg) { + CEC_ERR("allocate last_cec_msg failed\n"); + ret = -ENOMEM; + goto tag_cec_msg_alloc_err; } #ifdef CONFIG_HAS_EARLYSUSPEND @@ -2975,11 +3344,15 @@ static int aml_cec_probe(struct platform_device *pdev) #endif hrtimer_init(&start_bit_check, CLOCK_MONOTONIC, HRTIMER_MODE_REL); start_bit_check.function = cec_line_check; - /* for init */ - cec_pre_init(); - /* default enable all function*/ - cec_config(CEC_FUNC_CFG_ALL, 1); + cec_dev->cec_thread = create_workqueue("cec_work"); + if (cec_dev->cec_thread == NULL) { + CEC_INFO("create work queue failed\n"); + ret = -EFAULT; + goto tag_cec_threat_err; + } + INIT_DELAYED_WORK(&cec_dev->cec_work, cec_task); queue_delayed_work(cec_dev->cec_thread, &cec_dev->cec_work, 0); + scpi_get_wakeup_reason(&cec_dev->wakeup_reason); CEC_ERR("wakeup_reason:0x%x\n", cec_dev->wakeup_reason); scpi_get_cec_val(SCPI_CMD_GET_CEC1, @@ -2987,11 +3360,21 @@ static int aml_cec_probe(struct platform_device *pdev) scpi_get_cec_val(SCPI_CMD_GET_CEC2, &r); CEC_ERR("cev val1: %#x;val2: %#x\n", *((unsigned int *)&cec_dev->wakup_data), r); + + cec_irq_enable(true); CEC_ERR("%s success end\n", __func__); return 0; tag_cec_msg_alloc_err: - free_irq(cec_dev->irq_cec, (void *)cec_dev); + if (cec_dev->cec_num > 1) { + free_irq(cec_dev->irq_ceca, (void *)cec_dev); + free_irq(cec_dev->irq_cecb, (void *)cec_dev); + } else { + if (ee_cec == CEC_B) + free_irq(cec_dev->irq_cecb, (void *)cec_dev); + else + free_irq(cec_dev->irq_ceca, (void *)cec_dev); + } tag_cec_reg_map_err: input_free_device(cec_dev->cec_info.remote_cec_dev); tag_cec_alloc_input_err: @@ -3012,7 +3395,15 @@ tag_cec_devm_err: static int aml_cec_remove(struct platform_device *pdev) { CEC_INFO("cec uninit!\n"); - free_irq(cec_dev->irq_cec, (void *)cec_dev); + if (cec_dev->cec_num > 1) { + free_irq(cec_dev->irq_ceca, (void *)cec_dev); + free_irq(cec_dev->irq_cecb, (void *)cec_dev); + } else { + if (ee_cec == CEC_B) + free_irq(cec_dev->irq_cecb, (void *)cec_dev); + else + free_irq(cec_dev->irq_ceca, (void *)cec_dev); + } kfree(last_cec_msg); if (cec_dev->cec_thread) { @@ -3051,6 +3442,11 @@ static int aml_cec_suspend_noirq(struct device *dev) int ret = 0; CEC_INFO("cec suspend noirq\n"); + if (cec_dev->cec_num > 1) + cec_clear_all_logical_addr(CEC_B); + else + cec_clear_all_logical_addr(ee_cec); + if (!IS_ERR(cec_dev->dbg_dev->pins->sleep_state)) ret = pinctrl_pm_select_sleep_state(cec_dev->dbg_dev); else diff --git a/drivers/amlogic/cec/hdmi_ao_cec.h b/drivers/amlogic/cec/hdmi_ao_cec.h index dbfab7d70836..e256b617b017 100644 --- a/drivers/amlogic/cec/hdmi_ao_cec.h +++ b/drivers/amlogic/cec/hdmi_ao_cec.h @@ -18,7 +18,8 @@ #ifndef __AO_CEC_H__ #define __AO_CEC_H__ -#define CEC_DRIVER_VERSION "Ver 2018/09/2\n" + +#define CEC_DRIVER_VERSION "Ver 2018/11/21\n" #define CEC_FRAME_DELAY msecs_to_jiffies(400) #define CEC_DEV_NAME "cec" @@ -28,9 +29,29 @@ #define HR_DELAY(n) (ktime_set(0, n * 1000 * 1000)) +enum cecbver { + /*first version*/ + CECB_VER_0 = 0, + /*ee to ao */ + CECB_VER_1 = 1, + /* + * 1.fix bug: cts 7-1 + * 2.fix bug: Do not signal initiator error, when it's + * myself who pulled down the line when functioning as a follower + * 3.fix bug: Receive messages are ignored and not acknowledge + * 4.add status reg + */ + CECB_VER_2 = 2, +}; + + #define L_1 1 #define L_2 2 #define L_3 3 + +#define CEC_A 0 +#define CEC_B 1 + /* #define CEC_FUNC_MASK 0 #define ONE_TOUCH_PLAY_MASK 1 @@ -81,7 +102,7 @@ #define AO_CEC_STICKY_DATA7 ((0xd1 << 2)) /* - * AOCEC_B + * AOCEC_B register */ #define AO_CECB_CLK_CNTL_REG0 ((0xa0 << 2)) #define AO_CECB_CLK_CNTL_REG1 ((0xa1 << 2)) @@ -91,7 +112,10 @@ #define AO_CECB_INTR_CLR ((0xa5 << 2)) #define AO_CECB_INTR_STAT ((0xa6 << 2)) -/* read/write */ +/* + * AOCEC_A internal register + * read/write tx register list + */ #define CEC_TX_MSG_0_HEADER 0x00 #define CEC_TX_MSG_1_OPCODE 0x01 #define CEC_TX_MSG_2_OP1 0x02 @@ -108,8 +132,6 @@ #define CEC_TX_MSG_D_OP12 0x0D #define CEC_TX_MSG_E_OP13 0x0E #define CEC_TX_MSG_F_OP14 0x0F - -/* read/write */ #define CEC_TX_MSG_LENGTH 0x10 #define CEC_TX_MSG_CMD 0x11 #define CEC_TX_WRITE_BUF 0x12 @@ -124,7 +146,9 @@ #define CEC_CLOCK_DIV_H 0x1B #define CEC_CLOCK_DIV_L 0x1C -/* The following registers are for fine tuning CEC bit timing parameters. +/* + * AOCEC_A internal register + * The following registers are for fine tuning CEC bit timing parameters. * They are only valid in AO CEC, NOT valid in HDMITX CEC. * The AO CEC's timing parameters are already set default to work with * 32768Hz clock, so hopefully SW never need to program these registers. @@ -186,11 +210,13 @@ #define AO_CEC_NOMSMPACKPOINT_0MS45 0x58 #define AO_CEC_ACK0NOML2H_1MS5_BIT7_0 0x5A #define AO_CEC_ACK0NOML2H_1MS5_BIT8 0x5B - #define AO_CEC_BUGFIX_DISABLE_0 0x60 #define AO_CEC_BUGFIX_DISABLE_1 0x61 -/* read only */ +/* + * AOCEC_A internal register + * read only register list + */ #define CEC_RX_MSG_0_HEADER 0x80 #define CEC_RX_MSG_1_OPCODE 0x81 #define CEC_RX_MSG_2_OP1 0x82 @@ -207,13 +233,22 @@ #define CEC_RX_MSG_D_OP12 0x8D #define CEC_RX_MSG_E_OP13 0x8E #define CEC_RX_MSG_F_OP14 0x8F - -/* read only */ #define CEC_RX_MSG_LENGTH 0x90 #define CEC_RX_MSG_STATUS 0x91 #define CEC_RX_NUM_MSG 0x92 #define CEC_TX_MSG_STATUS 0x93 #define CEC_TX_NUM_MSG 0x94 +/* + * AOCEC_A internal register + * read only (tl1 later) + */ +#define CEC_STAT_0_0 0xA0 +#define CEC_STAT_0_1 0xA1 +#define CEC_STAT_0_2 0xA2 +#define CEC_STAT_0_3 0xA3 +#define CEC_STAT_1_0 0xA4 +#define CEC_STAT_1_1 0xA5 +#define CEC_STAT_1_2 0xA6 /* tx_msg_cmd definition */ #define TX_NO_OP 0 /* No transaction */ @@ -263,9 +298,12 @@ /** Register address: DMI disable interface */ #define DWC_DMI_DISABLE_IF (0xFF4UL) -/*---- registers for EE CEC ----*/ +/* + * AOCEC_B internal register + * for EE CEC + */ #define DWC_CEC_CTRL 0x1F00 -#define DWC_CEC_STAT 0x1F04 +#define DWC_CEC_CTRL2 0x1F04/*tl1 later*/ #define DWC_CEC_MASK 0x1F08 #define DWC_CEC_POLARITY 0x1F0C #define DWC_CEC_INT 0x1F10 @@ -273,6 +311,7 @@ #define DWC_CEC_ADDR_H 0x1F18 #define DWC_CEC_TX_CNT 0x1F1C #define DWC_CEC_RX_CNT 0x1F20 +#define DWC_CEC_STAT0 0x1F24/*tl1 later*/ #define DWC_CEC_TX_DATA0 0x1F40 #define DWC_CEC_TX_DATA1 0x1F44 #define DWC_CEC_TX_DATA2 0x1F48 @@ -308,13 +347,19 @@ #define DWC_CEC_LOCK 0x1FC0 #define DWC_CEC_WKUPCTRL 0x1FC4 -/* FOR AO_CECB */ +/* + * AOCEC_B internal register + * for EE CEC + */ +/* #define AO_CECB_CTRL_ADDR 0x00 +#define AO_CECB_CTRL2_ADDR 0x01 #define AO_CECB_INTR_MASK_ADDR 0x02 #define AO_CECB_LADD_LOW_ADDR 0x05 #define AO_CECB_LADD_HIGH_ADDR 0x06 #define AO_CECB_TX_CNT_ADDR 0x07 #define AO_CECB_RX_CNT_ADDR 0x08 +#define AO_CECB_STAT0_ADDR 0x09 #define AO_CECB_TX_DATA00_ADDR 0x10 #define AO_CECB_TX_DATA01_ADDR 0x11 #define AO_CECB_TX_DATA02_ADDR 0x12 @@ -349,6 +394,34 @@ #define AO_CECB_RX_DATA15_ADDR 0x2F #define AO_CECB_LOCK_BUF_ADDR 0x30 #define AO_CECB_WAKEUPCTRL_ADDR 0x31 +*/ + + +/* + * AOCEC B CEC_STAT0 + */ +enum { + CECB_STAT0_S2P_IDLE = 0, + CECB_STAT0_S2P_SBITLOWER = 1, + CECB_STAT0_S2P_SBH = 2, + CECB_STAT0_S2P_L1LOWER = 5, + CECB_STAT0_S2P_SMP1 = 6, + CECB_STAT0_S2P_SMP0 = 7, + CECB_STAT0_S2P_L0H = 8, + CECB_STAT0_S2P_ERRLMIN = 9, + CECB_STAT0_S2P_ERRLMAX = 0xe, +}; + +enum { + CECB_STAT0_P2S_TIDLE = 0, + CECB_STAT0_P2S_SEND_SBIT = 1, + CECB_STAT0_P2S_SEND_DBIT = 2, + CECB_STAT0_P2S_SEND_EOM = 3, + CECB_STAT0_P2S_SEND_ACK = 4, + CECB_STAT0_P2S_FBACK_ACK = 5, + CECB_STAT0_P2S_FBACK_RX_ERR = 6, +}; + /* cec ip irq flags bit discription */ #define EECEC_IRQ_TX_DONE (1 << 16) @@ -397,6 +470,8 @@ #define EDID_AUTO_CEC_EN 0 #define HHI_32K_CLK_CNTL (0x89 << 2) +#define HHI_HDMIRX_ARC_CNTL (0xe8 << 2) + struct dbgflg { unsigned int hal_cmd_bypass:1; @@ -408,6 +483,9 @@ extern unsigned long hdmirx_rd_top(unsigned long addr); extern void hdmirx_wr_top(unsigned long addr, unsigned long data); extern uint32_t hdmirx_rd_dwc(uint16_t addr); extern void hdmirx_wr_dwc(uint16_t addr, uint32_t data); +extern unsigned int rd_reg_hhi(unsigned int offset); +extern void wr_reg_hhi(unsigned int offset, unsigned int val); + #else static inline unsigned long hdmirx_rd_top(unsigned long addr) { @@ -425,6 +503,16 @@ static inline uint32_t hdmirx_rd_dwc(uint16_t addr) static inline void hdmirx_wr_dwc(uint16_t addr, uint32_t data) { } + +unsigned int rd_reg_hhi(unsigned int offset) +{ + return 0; +} + +void wr_reg_hhi(unsigned int offset, unsigned int val) +{ +} + #endif extern int hdmirx_get_connect_info(void); @@ -436,7 +524,7 @@ int __attribute__((weak))hdmirx_get_connect_info(void) #ifdef CONFIG_AMLOGIC_AO_CEC unsigned int aocec_rd_reg(unsigned long addr); void aocec_wr_reg(unsigned long addr, unsigned long data); -void cecrx_irq_handle(void); +void cecb_irq_handle(void); void cec_logicaddr_set(int l_add); void cec_arbit_bit_time_set(unsigned int bit_set, unsigned int time_set, unsigned int flag); @@ -445,6 +533,9 @@ void aocec_irq_enable(bool enable); extern void dump_reg(void); #endif extern void cec_dump_info(void); -extern void cec_hw_reset(void); - +extern void cec_hw_reset(unsigned int cec_sel); +extern void cec_restore_logical_addr(unsigned int cec_sel, + unsigned int addr_en); +extern void cec_logicaddr_add(unsigned int cec_sel, unsigned int l_add); +extern void cec_clear_all_logical_addr(unsigned int cec_sel); #endif /* __AO_CEC_H__ */ diff --git a/drivers/amlogic/clk/g12a/g12a_clk-mpll.c b/drivers/amlogic/clk/g12a/g12a_clk-mpll.c index 1d62f34f20fa..abd74ea5c51e 100644 --- a/drivers/amlogic/clk/g12a/g12a_clk-mpll.c +++ b/drivers/amlogic/clk/g12a/g12a_clk-mpll.c @@ -28,7 +28,7 @@ #include "../clkc.h" /* #undef pr_debug */ /* #define pr_debug pr_info */ -#define SDM_MAX 16384 +#define SDM_MAX 16384ULL #define MAX_RATE 500000000 #define MIN_RATE 3920000 @@ -87,6 +87,7 @@ static int mpll_set_rate(struct clk_hw *hw, unsigned long rate, struct parm *p; unsigned long reg, sdm, n2; unsigned long flags = 0; + uint64_t rate64 = parent_rate; if ((rate > MAX_RATE) || (rate < MIN_RATE)) { pr_err("Err: can not set rate to %lu!\n", rate); @@ -98,8 +99,12 @@ static int mpll_set_rate(struct clk_hw *hw, unsigned long rate, spin_lock_irqsave(mpll->lock, flags); /* calculate new n2 and sdm */ - n2 = parent_rate / rate; - sdm = DIV_ROUND_UP((parent_rate - n2 * rate) * SDM_MAX, rate); + do_div(rate64, rate); + n2 = rate64; + + rate64 = (parent_rate - n2 * rate) * SDM_MAX + rate - 1; + do_div(rate64, rate); + sdm = rate64; if (sdm >= SDM_MAX) sdm = SDM_MAX - 1; diff --git a/drivers/amlogic/crypto/aml-aes-dma.c b/drivers/amlogic/crypto/aml-aes-dma.c index c265790b2fed..b7ff8056ea37 100644 --- a/drivers/amlogic/crypto/aml-aes-dma.c +++ b/drivers/amlogic/crypto/aml-aes-dma.c @@ -58,6 +58,7 @@ #define AML_AES_QUEUE_LENGTH 50 #define AML_AES_DMA_THRESHOLD 16 +#define SUPPORT_FAST_DMA 0 struct aml_aes_dev; struct aml_aes_ctx { @@ -223,7 +224,7 @@ static size_t aml_aes_sg_copy(struct scatterlist **sg, size_t *offset, return off; } - +#if SUPPORT_FAST_DMA static size_t aml_aes_sg_dma(struct aml_aes_dev *dd, struct dma_dsc *dsc, uint32_t *nents, size_t total) { @@ -243,23 +244,36 @@ static size_t aml_aes_sg_dma(struct aml_aes_dev *dd, struct dma_dsc *dsc, process = min_t(unsigned int, total, in_sg->length); count += process; *nents += 1; + if (process != in_sg->length) + dd->out_offset = dd->in_offset = in_sg->length; total -= process; in_sg = sg_next(in_sg); out_sg = sg_next(out_sg); } - err = dma_map_sg(dd->dev, dd->in_sg, *nents, DMA_TO_DEVICE); - if (!err) { - dev_err(dd->dev, "dma_map_sg() error\n"); - return 0; - } + if (dd->in_sg != dd->out_sg) { + err = dma_map_sg(dd->dev, dd->in_sg, *nents, DMA_TO_DEVICE); + if (!err) { + dev_err(dd->dev, "dma_map_sg() error\n"); + return 0; + } - err = dma_map_sg(dd->dev, dd->out_sg, *nents, - DMA_FROM_DEVICE); - if (!err) { - dev_err(dd->dev, "dma_map_sg() error\n"); - dma_unmap_sg(dd->dev, dd->in_sg, *nents, - DMA_TO_DEVICE); - return 0; + err = dma_map_sg(dd->dev, dd->out_sg, *nents, + DMA_FROM_DEVICE); + if (!err) { + dev_err(dd->dev, "dma_map_sg() error\n"); + dma_unmap_sg(dd->dev, dd->in_sg, *nents, + DMA_TO_DEVICE); + return 0; + } + } else { + err = dma_map_sg(dd->dev, dd->in_sg, *nents, + DMA_BIDIRECTIONAL); + if (!err) { + dev_err(dd->dev, "dma_map_sg() error\n"); + return 0; + } + dma_sync_sg_for_device(dd->dev, dd->in_sg, + *nents, DMA_TO_DEVICE); } in_sg = dd->in_sg; @@ -280,7 +294,7 @@ static size_t aml_aes_sg_dma(struct aml_aes_dev *dd, struct dma_dsc *dsc, } return count; } - +#endif static struct aml_aes_dev *aml_aes_find_dev(struct aml_aes_ctx *ctx) { struct aml_aes_dev *aes_dd = NULL; @@ -385,7 +399,8 @@ static int aml_aes_crypt_dma_start(struct aml_aes_dev *dd) dd->fast_nents = 0; } - //fast = 0; +#if SUPPORT_FAST_DMA + // fast = 0; if (fast) { count = aml_aes_sg_dma(dd, dsc, &dd->fast_nents, dd->total); dd->flags |= AES_FLAGS_FAST; @@ -393,7 +408,9 @@ static int aml_aes_crypt_dma_start(struct aml_aes_dev *dd) dd->fast_total = count; dbgp(1, "use fast dma: n:%u, t:%zd\n", dd->fast_nents, dd->fast_total); - } else { + } else +#endif + { /* slow dma */ /* use cache buffers */ count = aml_aes_sg_copy(&dd->in_sg, &dd->in_offset, @@ -523,10 +540,17 @@ static int aml_aes_crypt_dma_stop(struct aml_aes_dev *dd) dma_sync_single_for_cpu(dd->dev, dd->dma_descript_tab, PAGE_SIZE, DMA_FROM_DEVICE); if (dd->flags & AES_FLAGS_FAST) { - dma_unmap_sg(dd->dev, dd->out_sg, + if (dd->in_sg != dd->out_sg) { + dma_unmap_sg(dd->dev, dd->out_sg, dd->fast_nents, DMA_FROM_DEVICE); - dma_unmap_sg(dd->dev, dd->in_sg, + dma_unmap_sg(dd->dev, dd->in_sg, dd->fast_nents, DMA_TO_DEVICE); + } else { + dma_sync_sg_for_cpu(dd->dev, dd->in_sg, + dd->fast_nents, DMA_FROM_DEVICE); + dma_unmap_sg(dd->dev, dd->in_sg, + dd->fast_nents, DMA_BIDIRECTIONAL); + } if (dd->flags & AES_FLAGS_CBC) scatterwalk_map_and_copy(dd->req->info, dd->out_sg, dd->fast_total - 16, @@ -980,7 +1004,7 @@ static void aml_aes_done_task(unsigned long data) aml_dma_debug(dd->descriptor, dd->fast_nents ? dd->fast_nents : 1, __func__, dd->thread, dd->status); - err = dd->err ? : err; + err = dd->err ? dd->err : err; if (dd->total && !err) { if (dd->flags & AES_FLAGS_FAST) { diff --git a/drivers/amlogic/ddr_tool/ddr_bandwidth.c b/drivers/amlogic/ddr_tool/ddr_bandwidth.c index 132773ca5ed0..d15b0ebd8727 100644 --- a/drivers/amlogic/ddr_tool/ddr_bandwidth.c +++ b/drivers/amlogic/ddr_tool/ddr_bandwidth.c @@ -30,27 +30,65 @@ #include #include #include +#include +#include static struct ddr_bandwidth *aml_db; +struct extcon_dev *ddr_extcon_bandwidth; +static const unsigned int bandwidth_cable[] = { + EXTCON_TYPE_DISP, + EXTCON_NONE, +}; static void cal_ddr_usage(struct ddr_bandwidth *db, struct ddr_grant *dg) { u64 mul; /* avoid overflow */ unsigned long i, cnt, freq = 0; + if (db->mode == MODE_AUTODETECT) { /* ignore mali bandwidth */ + static int count; + unsigned int grant = dg->all_grant; + + if (db->mali_port[0] >= 0) + grant -= dg->channel_grant[0]; + if (db->mali_port[1] >= 0) + grant -= dg->channel_grant[1]; + if (grant > db->threshold) { + if (count >= 2) { + if (db->busy == 0) { + db->busy = 1; + schedule_work(&db->work_bandwidth); + } + } else + count++; + } else if (count > 0) { + if (count >= 2) { + db->busy = 0; + schedule_work(&db->work_bandwidth); + } + count = 0; + } + return; + } if (db->ops && db->ops->get_freq) freq = db->ops->get_freq(db); - mul = (dg->all_grant * 10000ULL) / 16; /* scale up to keep precision*/ + mul = dg->all_grant; + mul *= 10000ULL; + mul /= 16; cnt = db->clock_count; do_div(mul, cnt); db->total_usage = mul; if (freq) { /* calculate in KB */ - mul = (dg->all_grant * freq) / 1024; + mul = dg->all_grant; + mul *= freq; + mul /= 1024; do_div(mul, cnt); db->total_bandwidth = mul; for (i = 0; i < db->channels; i++) { - mul = (dg->channel_grant[i] * freq) / 1024; + mul = dg->channel_grant[i]; + mul *= freq; + mul /= 1024; do_div(mul, cnt); db->bandwidth[i] = mul; } @@ -133,6 +171,91 @@ static ssize_t ddr_channel_store(struct class *cla, return count; } +static ssize_t busy_show(struct class *cla, + struct class_attribute *attr, char *buf) +{ + return sprintf(buf, "%d\n", aml_db->busy); +} + +static ssize_t threshold_show(struct class *cla, + struct class_attribute *attr, char *buf) +{ + return sprintf(buf, "%d\n", + aml_db->threshold / 16 / (aml_db->clock_count / 10000)); +} + +static ssize_t threshold_store(struct class *cla, + struct class_attribute *attr, const char *buf, size_t count) +{ + long val = 0; + + if (kstrtoul(buf, 10, &val)) { + pr_info("invalid input:%s\n", buf); + return 0; + } + + if (val > 10000) + val = 10000; + aml_db->threshold = val * 16 * (aml_db->clock_count / 10000); + return count; +} + +static ssize_t mode_show(struct class *cla, + struct class_attribute *attr, char *buf) +{ + if (aml_db->mode == MODE_DISABLE) + return sprintf(buf, "0: disable\n"); + else if (aml_db->mode == MODE_ENABLE) + return sprintf(buf, "1: enable\n"); + else if (aml_db->mode == MODE_AUTODETECT) + return sprintf(buf, "2: auto detect\n"); + return sprintf(buf, "\n"); +} + +static ssize_t mode_store(struct class *cla, + struct class_attribute *attr, const char *buf, size_t count) +{ + long val = 0; + + if (kstrtoul(buf, 10, &val)) { + pr_info("invalid input:%s\n", buf); + return 0; + } + if ((val > MODE_AUTODETECT) || (val < MODE_DISABLE)) + val = MODE_AUTODETECT; + + if (val == MODE_AUTODETECT && aml_db->ops && aml_db->ops->config_port) { + if (aml_db->mali_port[0] >= 0) { + aml_db->port[0] = aml_db->mali_port[0]; + aml_db->ops->config_port(aml_db, 0, aml_db->port[0]); + } + if (aml_db->mali_port[1] >= 0) { + aml_db->port[1] = aml_db->mali_port[1]; + aml_db->ops->config_port(aml_db, 1, aml_db->port[1]); + } + } + if ((aml_db->mode == MODE_DISABLE) && (val != MODE_DISABLE)) { + int r = request_irq(aml_db->irq_num, dmc_irq_handler, + IRQF_SHARED, "ddr_bandwidth", (void *)aml_db); + if (r < 0) { + pr_info("ddrbandwidth request irq failed\n"); + return count; + } + + if (aml_db->ops->init) + aml_db->ops->init(aml_db); + } else if ((aml_db->mode != MODE_DISABLE) && (val == MODE_DISABLE)) { + free_irq(aml_db->irq_num, (void *)aml_db); + aml_db->total_usage = 0; + aml_db->total_bandwidth = 0; + aml_db->busy = 0; + } + aml_db->mode = val; + + return count; +} + + static ssize_t clock_count_show(struct class *cla, struct class_attribute *attr, char *buf) { @@ -148,10 +271,11 @@ static ssize_t clock_count_store(struct class *cla, pr_info("invalid input:%s\n", buf); return 0; } + aml_db->threshold /= (aml_db->clock_count / 10000); + aml_db->threshold *= (val / 10000); aml_db->clock_count = val; if (aml_db->ops && aml_db->ops->init) aml_db->ops->init(aml_db); - return count; } @@ -160,7 +284,10 @@ static ssize_t bandwidth_show(struct class *cla, { size_t s = 0, i; int percent, rem; -#define BANDWIDTH_PREFIX "Total bandwidth:%8d KB/s, usage:%2d.%02d%%\n" +#define BANDWIDTH_PREFIX "Total bandwidth: %8d KB/s, usage: %2d.%02d%%\n" + + if (aml_db->mode != MODE_ENABLE) + return sprintf(buf, "set mode to enable(1) first.\n"); percent = aml_db->total_usage / 100; rem = aml_db->total_usage % 100; @@ -168,8 +295,8 @@ static ssize_t bandwidth_show(struct class *cla, aml_db->total_bandwidth, percent, rem); for (i = 0; i < aml_db->channels; i++) { - s += sprintf(buf + s, "Channel %zu, bandwidth:%8d KB/s\n", - i, aml_db->bandwidth[i]); + s += sprintf(buf + s, "port%d: %8d KB/s\n", + aml_db->port[i], aml_db->bandwidth[i]); } return s; } @@ -184,6 +311,94 @@ static ssize_t freq_show(struct class *cla, return sprintf(buf, "%ld MHz\n", clk / 1000000); } +void dmc_set_urgent(unsigned int port, unsigned int type) +{ + unsigned int val = 0, addr = 0; + + if (aml_db->cpu_type < MESON_CPU_MAJOR_ID_G12A) { + unsigned int port_reg[16] = { + DMC_AXI0_CHAN_CTRL, DMC_AXI1_CHAN_CTRL, + DMC_AXI2_CHAN_CTRL, DMC_AXI3_CHAN_CTRL, + DMC_AXI4_CHAN_CTRL, DMC_AXI5_CHAN_CTRL, + DMC_AXI6_CHAN_CTRL, DMC_AXI7_CHAN_CTRL, + DMC_AM0_CHAN_CTRL, DMC_AM1_CHAN_CTRL, + DMC_AM2_CHAN_CTRL, DMC_AM3_CHAN_CTRL, + DMC_AM4_CHAN_CTRL, DMC_AM5_CHAN_CTRL, + DMC_AM6_CHAN_CTRL, DMC_AM7_CHAN_CTRL,}; + + if (port >= 16) + return; + addr = port_reg[port]; + } else { + unsigned int port_reg[24] = { + DMC_AXI0_G12_CHAN_CTRL, DMC_AXI1_G12_CHAN_CTRL, + DMC_AXI2_G12_CHAN_CTRL, DMC_AXI3_G12_CHAN_CTRL, + DMC_AXI4_G12_CHAN_CTRL, DMC_AXI5_G12_CHAN_CTRL, + DMC_AXI6_G12_CHAN_CTRL, DMC_AXI7_G12_CHAN_CTRL, + DMC_AXI8_G12_CHAN_CTRL, DMC_AXI9_G12_CHAN_CTRL, + DMC_AXI10_G12_CHAN_CTRL, DMC_AXI1_G12_CHAN_CTRL, + DMC_AXI12_G12_CHAN_CTRL, 0, 0, 0, + DMC_AM0_G12_CHAN_CTRL, DMC_AM1_G12_CHAN_CTRL, + DMC_AM2_G12_CHAN_CTRL, DMC_AM3_G12_CHAN_CTRL, + DMC_AM4_G12_CHAN_CTRL, DMC_AM5_G12_CHAN_CTRL, + DMC_AM6_G12_CHAN_CTRL, DMC_AM7_G12_CHAN_CTRL,}; + + if ((port >= 24) || (port_reg[port] == 0)) + return; + addr = port_reg[port]; + } + + /** + *bit 18. force this channel all request to be super urgent request. + *bit 17. force this channel all request to be urgent request. + *bit 16. force this channel all request to be non urgent request. + */ + val = readl(aml_db->ddr_reg + addr); + val &= (~(0x7 << 16)); + val |= ((type & 0x7) << 16); + writel(val, aml_db->ddr_reg + addr); +} +EXPORT_SYMBOL(dmc_set_urgent); + +static ssize_t urgent_show(struct class *cla, + struct class_attribute *attr, char *buf) +{ + int i, s = 0; + + if (!aml_db->real_ports || !aml_db->port_desc) + return -EINVAL; + + s += sprintf(buf + s, "echo port val > /sys/class/aml_ddr/urgent\n" + "val:\n\t1: non urgent;\n\t2: urgent;\n\t4: super urgent;\n" + "port: (hex integer)\n"); + for (i = 0; i < aml_db->real_ports; i++) { + if (aml_db->port_desc[i].port_id >= 24) + break; + s += sprintf(buf + s, "\tbit%d: %s\n", + aml_db->port_desc[i].port_id, + aml_db->port_desc[i].port_name); + } + + return s; +} + +static ssize_t urgent_store(struct class *cla, + struct class_attribute *attr, const char *buf, size_t count) +{ + unsigned int port = 0, val, i; + + if (sscanf(buf, "%x %d", &port, &val) != 2) { + pr_info("invalid input:%s\n", buf); + return -EINVAL; + } + for (i = 0; i < 24; i++) { + if (port & 1) + dmc_set_urgent(i, val); + port >>= 1; + } + return count; +} + #if DDR_BANDWIDTH_DEBUG static ssize_t dump_reg_show(struct class *cla, struct class_attribute *attr, char *buf) @@ -226,6 +441,10 @@ static ssize_t name_of_ports_show(struct class *cla, static struct class_attribute aml_ddr_tool_attr[] = { __ATTR(port, 0664, ddr_channel_show, ddr_channel_store), __ATTR(irq_clock, 0664, clock_count_show, clock_count_store), + __ATTR(urgent, 0664, urgent_show, urgent_store), + __ATTR(threshold, 0664, threshold_show, threshold_store), + __ATTR(mode, 0664, mode_show, mode_store), + __ATTR_RO(busy), __ATTR_RO(bandwidth), __ATTR_RO(freq), __ATTR_RO(cpu_type), @@ -241,6 +460,41 @@ static struct class aml_ddr_class = { .class_attrs = aml_ddr_tool_attr, }; +static void bandwidth_work_func(struct work_struct *work) +{ + extcon_set_state_sync(ddr_extcon_bandwidth, EXTCON_TYPE_DISP, + (aml_db->busy == 1) ? true : false); +} + +void ddr_extcon_register(struct platform_device *pdev) +{ + struct extcon_dev *edev; + int ret; + + edev = extcon_dev_allocate(bandwidth_cable); + if (IS_ERR(edev)) { + pr_info("failed to allocate ddr extcon bandwidth\n"); + return; + } + edev->dev.parent = &pdev->dev; + edev->name = "ddr_extcon_bandwidth"; + dev_set_name(&edev->dev, "bandwidth"); + ret = extcon_dev_register(edev); + if (ret < 0) { + pr_info("failed to register ddr extcon bandwidth\n"); + return; + } + ddr_extcon_bandwidth = edev; + + INIT_WORK(&aml_db->work_bandwidth, bandwidth_work_func); +} + +static void ddr_extcon_free(void) +{ + extcon_dev_free(ddr_extcon_bandwidth); + ddr_extcon_bandwidth = NULL; +} + /* * ddr_bandwidth_probe only executes before the init process starts * to run, so add __ref to indicate it is okay to call __init function @@ -251,7 +505,6 @@ static int __ref ddr_bandwidth_probe(struct platform_device *pdev) int r = 0; #ifdef CONFIG_OF struct device_node *node = pdev->dev.of_node; - const char *irq_name = NULL; /*struct pinctrl *p;*/ struct resource *res; resource_size_t *base; @@ -271,10 +524,24 @@ static int __ref ddr_bandwidth_probe(struct platform_device *pdev) } /* set channel */ - if (aml_db->cpu_type < MESON_CPU_MAJOR_ID_GXTVBB) + if (aml_db->cpu_type < MESON_CPU_MAJOR_ID_GXTVBB) { aml_db->channels = 1; - else + aml_db->mali_port[0] = 2; + aml_db->mali_port[1] = -1; + } else { aml_db->channels = 4; + if ((aml_db->cpu_type == MESON_CPU_MAJOR_ID_GXM) + || (aml_db->cpu_type >= MESON_CPU_MAJOR_ID_G12A)) { + aml_db->mali_port[0] = 1; /* port1: mali */ + aml_db->mali_port[1] = -1; + } else if (aml_db->cpu_type == MESON_CPU_MAJOR_ID_AXG) { + aml_db->mali_port[0] = -1; /* no mali */ + aml_db->mali_port[1] = -1; + } else { + aml_db->mali_port[0] = 1; /* port1: mali0 */ + aml_db->mali_port[1] = 2; /* port2: mali1 */ + } + } /* find and configure port description */ pcnt = ddr_find_port_desc(aml_db->cpu_type, &desc); @@ -307,19 +574,11 @@ static int __ref ddr_bandwidth_probe(struct platform_device *pdev) } aml_db->irq_num = of_irq_get(node, 0); - if (of_get_property(node, "interrupt-names", NULL)) { - r = of_property_read_string(node, "interrupt-names", &irq_name); - if (!r) { - r = request_irq(aml_db->irq_num, dmc_irq_handler, - IRQF_SHARED, irq_name, (void *)aml_db); - } - } - if (r < 0) { - pr_info("request irq failed:%d\n", aml_db->irq_num); - goto inval; - } #endif aml_db->clock_count = DEFAULT_CLK_CNT; + aml_db->mode = MODE_DISABLE; + aml_db->threshold = DEFAULT_THRESHOLD * 16 * + (aml_db->clock_count / 10000); if (aml_db->cpu_type <= MESON_CPU_MAJOR_ID_GXTVBB) aml_db->ops = &gx_ddr_bw_ops; else if ((aml_db->cpu_type <= MESON_CPU_MAJOR_ID_TXHD) && @@ -333,11 +592,11 @@ static int __ref ddr_bandwidth_probe(struct platform_device *pdev) goto inval; } - if (aml_db->ops->init) - aml_db->ops->init(aml_db); r = class_register(&aml_ddr_class); if (r) pr_info("%s, class regist failed\n", __func__); + + ddr_extcon_register(pdev); return 0; inval: kfree(aml_db->port_desc); @@ -358,6 +617,7 @@ static int ddr_bandwidth_remove(struct platform_device *pdev) kfree(aml_db); aml_db = NULL; } + ddr_extcon_free(); return 0; } diff --git a/drivers/amlogic/ddr_tool/dmc_g12.c b/drivers/amlogic/ddr_tool/dmc_g12.c index 5fe7197e4eed..8276e157f4f6 100644 --- a/drivers/amlogic/ddr_tool/dmc_g12.c +++ b/drivers/amlogic/ddr_tool/dmc_g12.c @@ -83,10 +83,17 @@ static void check_violation(struct dmc_monitor *mon) struct page *page; unsigned long *p; char id_str[4]; + char off1 = 21, off2 = 10; + + if (mon->chip == MESON_CPU_MAJOR_ID_G12B) { + /* bit fix for G12B */ + off1 = 24; + off2 = 13; + } for (i = 1; i < 4; i += 2) { status = dmc_rw(DMC_VIO_ADDR0 + (i << 2), 0, DMC_READ); - if (!(status & DMC_VIO_PROT_RANGE0)) + if (!(status & (1 << off1))) continue; addr = dmc_rw(DMC_VIO_ADDR0 + ((i - 1) << 2), 0, DMC_READ); @@ -100,7 +107,7 @@ static void check_violation(struct dmc_monitor *mon) continue; } - port = (status >> 13) & 0x1f; + port = (status >> off2) & 0x1f; subport = (status >> 6) & 0xf; pr_info(DMC_TAG", addr:%08lx, s:%08lx, ID:%s, sub:%s, c:%ld\n", addr, status, to_ports(port), diff --git a/drivers/amlogic/ddr_tool/dmc_monitor.c b/drivers/amlogic/ddr_tool/dmc_monitor.c index 58c940085b99..17086aa83a80 100644 --- a/drivers/amlogic/ddr_tool/dmc_monitor.c +++ b/drivers/amlogic/ddr_tool/dmc_monitor.c @@ -66,7 +66,7 @@ static int dev_name_to_id(const char *dev_name) } if (i >= dmc_mon->port_num) return -1; - return i; + return dmc_mon->port[i].port_id; } char *to_ports(int id) diff --git a/drivers/amlogic/defendkey/defendkey.c b/drivers/amlogic/defendkey/defendkey.c index 8bf3c460514c..1a7162326793 100644 --- a/drivers/amlogic/defendkey/defendkey.c +++ b/drivers/amlogic/defendkey/defendkey.c @@ -35,6 +35,7 @@ #include #include #include "securekey.h" +#include #define DEFENDKEY_DEVICE_NAME "defendkey" #define DEFENDKEY_CLASS_NAME "defendkey" @@ -42,6 +43,16 @@ void __iomem *mem_base_virt; unsigned long mem_size; unsigned long random_virt; +struct defendkey_mem { + unsigned long base; + unsigned long size; +}; + +struct defendkey_mem defendkey_rmem; + +#define CMD_SECURE_CHECK _IO('d', 0x01) +#define CMD_DECRYPT_DTB _IO('d', 0x02) + enum e_defendkey_type { e_upgrade_check = 0, e_decrypt_dtb = 1, @@ -83,7 +94,27 @@ static loff_t defendkey_llseek(struct file *filp, loff_t off, int whence) static long defendkey_unlocked_ioctl(struct file *file, unsigned int cmd, unsigned long arg) { - return 0; + unsigned long ret = 0; + + switch (cmd) { + case CMD_SECURE_CHECK: + ret = aml_is_secure_set(); + break; + case CMD_DECRYPT_DTB: + if (arg == 1) + decrypt_dtb = 1; + else if (arg == 0) + decrypt_dtb = 0; + else { + return -EINVAL; + pr_info("set defendkey decrypt_dtb fail,invalid value\n"); + } + break; + default: + return -EINVAL; + } + + return ret; } #ifdef CONFIG_COMPAT @@ -124,7 +155,7 @@ static ssize_t defendkey_read(struct file *file, __func__, ret); return ret_fail; } - __dma_flush_area((const void *)mem_base_virt, copy_size); + //__dma_flush_area((const void *)mem_base_virt, copy_size); } if (!ret) { pr_info("%s: copy data to user successfully!\n", @@ -143,11 +174,15 @@ static ssize_t defendkey_write(struct file *file, ssize_t ret_value = ret_error; int ret = -EINVAL; - unsigned long mem_base_phy, copy_base, copy_size, random; - unsigned long option = 0; + unsigned long mem_base_phy, copy_base, copy_size; + uint64_t option = 0, random = 0, option_random = 0; int i; + struct cpumask task_cpumask; - mem_base_phy = get_sharemem_info(GET_SHARE_MEM_INPUT_BASE); + cpumask_copy(&task_cpumask, ¤t->cpus_allowed); + set_cpus_allowed_ptr(current, cpumask_of(0)); + + mem_base_phy = defendkey_rmem.base; mem_base_virt = phys_to_virt(mem_base_phy); if (!mem_base_phy || !mem_size) { @@ -161,6 +196,12 @@ static ssize_t defendkey_write(struct file *file, random = readl((void *)random_virt); +#ifdef CONFIG_ARM64_A32 + option_random = (random << 8); +#endif + + option_random |= (random << 32); + for (i = 0; i <= count/mem_size; i++) { copy_size = mem_size; copy_base = (unsigned long)buf+i*mem_size; @@ -173,7 +214,7 @@ static ssize_t defendkey_write(struct file *file, ret = -EFAULT; goto exit; } - __dma_flush_area((const void *)mem_base_virt, copy_size); + //__dma_flush_area((const void *)mem_base_virt, copy_size); if (i == 0) { option = 1; @@ -181,19 +222,19 @@ static ssize_t defendkey_write(struct file *file, /*just transfer data to BL31 one time*/ option = 1|2|4; } - option |= (random<<32); + option |= option_random; } else if ((i > 0) && (i < (count/mem_size))) { - option = 2|(random<<32); + option = 2|option_random; if ((count%mem_size == 0) && (i == (count/mem_size - 1))) - option = 4|(random<<32); + option = 4|option_random; } else if (i == (count/mem_size)) { if (count%mem_size != 0) - option = 4|(random<<32); + option = 4|option_random; else break; } - pr_info("defendkey:%d: copy_size:0x%lx, option:0x%lx\n", + pr_info("defendkey:%d: copy_size:0x%lx, option:0x%llx\n", __LINE__, copy_size, option); pr_info("decrypt_dtb: %d\n", decrypt_dtb); if (e_decrypt_dtb == decrypt_dtb) @@ -226,6 +267,7 @@ static ssize_t defendkey_write(struct file *file, ret_value = ret_success; } exit: + set_cpus_allowed_ptr(current, &task_cpumask); return ret_value; } @@ -277,8 +319,7 @@ static ssize_t decrypt_dtb_store(struct class *cla, len = count; if (!strncmp(buf, "1", len)) { - //decrypt_dtb = 1; - pr_info("current BL31 share memory size not support decrypt_dtb\n"); + decrypt_dtb = 1; } else if (!strncmp(buf, "0", len)) decrypt_dtb = 0; else { @@ -313,6 +354,36 @@ static struct class defendkey_class = { .class_attrs = defendkey_class_attrs, }; +static int __init early_defendkey_para(char *buf) +{ + int ret; + + if (!buf) + return -EINVAL; + + ret = sscanf(buf, "%lx,%lx", + &defendkey_rmem.base, &defendkey_rmem.size); + if (ret != 2) { + pr_err("invalid boot args \"defendkey\"\n"); + return -EINVAL; + } + + pr_info("%s, base:%lx, size:%lx\n", + __func__, defendkey_rmem.base, defendkey_rmem.size); + + ret = memblock_reserve(defendkey_rmem.base, + PAGE_ALIGN(defendkey_rmem.size)); + if (ret < 0) { + pr_info("reserve memblock %lx - %lx failed\n", + defendkey_rmem.base, + defendkey_rmem.base + PAGE_ALIGN(defendkey_rmem.size)); + return -EINVAL; + } + + return 0; +} +early_param("defendkey", early_defendkey_para); + static int aml_defendkey_probe(struct platform_device *pdev) { int ret = -1; @@ -334,7 +405,12 @@ static int aml_defendkey_probe(struct platform_device *pdev) dev_err(&pdev->dev, "please config mem_size in dts\n"); goto error1; } + mem_size = val64; + if (mem_size > defendkey_rmem.size) { + dev_err(&pdev->dev, "Reserved memory is not enough!\n"); + return -EINVAL; + } res = platform_get_resource(pdev, IORESOURCE_MEM, 0); if (IS_ERR(res)) { diff --git a/drivers/amlogic/drm/am_meson_vpu.c b/drivers/amlogic/drm/am_meson_vpu.c index 69372bfeb1fe..fccfdc20a88a 100644 --- a/drivers/amlogic/drm/am_meson_vpu.c +++ b/drivers/amlogic/drm/am_meson_vpu.c @@ -34,6 +34,7 @@ /* Amlogic Headers */ #include +#include #include "osd.h" #include "osd_drm.h" @@ -255,7 +256,6 @@ int am_meson_crtc_dts_info_set(const void *dt_match_data) return 0; } - static const struct drm_plane_funcs am_osd_plane_funs = { .update_plane = drm_atomic_helper_update_plane, .disable_plane = drm_atomic_helper_disable_plane, @@ -667,6 +667,26 @@ void am_meson_crtc_atomic_begin(struct drm_crtc *crtc, void am_meson_crtc_atomic_flush(struct drm_crtc *crtc, struct drm_crtc_state *old_crtc_state) { + struct drm_color_ctm *ctm; + struct drm_color_lut *lut; + int gamma_lut_size = 0; + + if (crtc->state->color_mgmt_changed) { + DRM_INFO("%s color_mgmt_changed!\n", __func__); + if (crtc->state->ctm) { + DRM_INFO("%s color_mgmt_changed 1!\n", __func__); + ctm = (struct drm_color_ctm *) + crtc->state->ctm->data; + am_meson_ctm_set(0, ctm); + } + if (crtc->state->gamma_lut) { + DRM_INFO("%s color_mgmt_changed 2!\n", __func__); + lut = (struct drm_color_lut *) + crtc->state->gamma_lut->data; + gamma_lut_size = amvecm_drm_get_gamma_size(0); + amvecm_drm_gamma_set(0, lut, gamma_lut_size); + } + } } static const struct drm_crtc_helper_funcs am_crtc_helper_funcs = { @@ -682,6 +702,7 @@ int am_meson_crtc_create(struct am_meson_crtc *amcrtc) { struct meson_drm *priv = amcrtc->priv; struct drm_crtc *crtc = &amcrtc->base; + int gamma_lut_size = 0; int ret; DRM_INFO("%s\n", __func__); @@ -696,6 +717,12 @@ int am_meson_crtc_create(struct am_meson_crtc *amcrtc) drm_crtc_helper_add(crtc, &am_crtc_helper_funcs); osd_drm_init(&osd_meson_dev); + amvecm_drm_init(0); + amvecm_drm_gamma_enable(0); + gamma_lut_size = amvecm_drm_get_gamma_size(0); + drm_mode_crtc_set_gamma_size(crtc, gamma_lut_size); + drm_crtc_enable_color_mgmt(crtc, 0, true, gamma_lut_size); + priv->crtc = crtc; return 0; } @@ -830,6 +857,8 @@ static void am_meson_vpu_unbind(struct device *dev, struct meson_drm *private = drm_dev->dev_private; am_meson_unregister_crtc_funcs(private->crtc); + amvecm_drm_gamma_disable(0); + am_meson_ctm_disable(); osd_drm_debugfs_exit(); } diff --git a/drivers/amlogic/esm/hdcp_main.c b/drivers/amlogic/esm/hdcp_main.c index cbddd87f6d94..f7d8ecbe2522 100644 --- a/drivers/amlogic/esm/hdcp_main.c +++ b/drivers/amlogic/esm/hdcp_main.c @@ -63,6 +63,8 @@ struct esm_device { dma_addr_t data_base; uint32_t data_size; uint8_t *data; + + struct dentry *esm_blob; struct debugfs_blob_wrapper blob; struct resource *hpi_resource; uint8_t __iomem *hpi; @@ -106,7 +108,7 @@ static long load_code(struct esm_device *esm, struct esm_ioc_code __user *arg) if (copy_from_user(esm->code, &arg->data, head.len) != 0) return -EFAULT; - esm->code_loaded = 1; + /* esm->code_loaded = 1; */ return 0; } @@ -233,7 +235,7 @@ static struct esm_device *alloc_esm_slot(const struct esm_ioc_meminfo *info) } static struct dentry *esm_debugfs; -static struct dentry *esm_blob; +/*static struct dentry *esm_blob;*/ static void free_dma_areas(struct esm_device *esm) { @@ -255,6 +257,8 @@ static void free_dma_areas(struct esm_device *esm) static int alloc_dma_areas(struct esm_device *esm, const struct esm_ioc_meminfo *info) { + char blobname[32]; + esm->code_size = info->code_size; esm->code_is_phys_mem = (info->code_base != 0); @@ -289,20 +293,24 @@ static int alloc_dma_areas(struct esm_device *esm, return -ENOMEM; } } - /* add blob note to show esm feature and debug*/ - esm_debugfs = debugfs_create_dir("esm", NULL); - if (!esm_debugfs) - return -ENOENT; - - esm->blob.data = (void *)esm->code; - esm->blob.size = esm->code_size; - esm_blob = debugfs_create_blob("blob", 0644, esm_debugfs, &esm->blob); if (randomize_mem) { prandom_bytes(esm->code, esm->code_size); prandom_bytes(esm->data, esm->data_size); } + if (!esm_debugfs) { + esm_debugfs = debugfs_create_dir("esm", NULL); + if (!esm_debugfs) + return -ENOENT; + } + memset(blobname, 0, sizeof(blobname)); + sprintf(blobname, "blob.%x", info->hpi_base); + esm->blob.data = (void *)esm->data; + esm->blob.size = esm->data_size; + esm->esm_blob = debugfs_create_blob(blobname, 0644, esm_debugfs, + &esm->blob); + return 0; } @@ -312,6 +320,7 @@ static long init(struct file *f, void __user *arg) struct resource *hpi_mem; struct esm_ioc_meminfo info; struct esm_device *esm; + char region_name[20]; int rc; if (copy_from_user(&info, arg, sizeof(info)) != 0) @@ -325,8 +334,15 @@ static long init(struct file *f, void __user *arg) rc = alloc_dma_areas(esm, &info); if (rc < 0) goto err_free; - pr_info("info.hpi_base = 0x%x\n", info.hpi_base); - hpi_mem = request_mem_region(info.hpi_base, 128, "esm-hpi"); + /* pr_info("info.hpi_base = 0x%x\n", info.hpi_base); */ + /* hpi_mem = + * request_mem_region(info.hpi_base, 128, "esm-hpi"); + */ + sprintf(region_name, "ESM-%X", info.hpi_base); + pr_info("info.hpi_base = 0x%x region_name:%s\n", + info.hpi_base, region_name); + hpi_mem = request_mem_region(info.hpi_base, 0x100, region_name); + if (!hpi_mem) { rc = -EADDRNOTAVAIL; goto err_free; @@ -342,6 +358,12 @@ static long init(struct file *f, void __user *arg) esm->initialized = 1; } + /*every time clear the data buff*/ + if (esm->data) + memset(esm->data, 0, esm->data_size); + pr_info("esm data = %p size:%d\n", + esm->data, esm->data_size); + f->private_data = esm; return 0; diff --git a/drivers/amlogic/input/keyboard/adc_keypad.c b/drivers/amlogic/input/keyboard/adc_keypad.c index a9f5ff9d5141..7182e595ab89 100644 --- a/drivers/amlogic/input/keyboard/adc_keypad.c +++ b/drivers/amlogic/input/keyboard/adc_keypad.c @@ -100,25 +100,6 @@ static void meson_adc_kp_poll(struct input_polled_dev *dev) } -#ifdef CONFIG_AMLOGIC_LEGACY_EARLY_SUSPEND -static void meson_adc_kp_early_suspend(struct early_suspend *h) -{ - struct meson_adc_kp *kp = container_of(h, - struct meson_adc_kp, early_suspend); - - cancel_delayed_work_sync(&kp->poll_dev->work); -} - -static void meson_adc_kp_late_resume(struct early_suspend *h) -{ - struct meson_adc_kp *kp = container_of(h, - struct meson_adc_kp, early_suspend); - - queue_delayed_work(system_freezable_wq, &kp->poll_dev->work, - msecs_to_jiffies(kp->poll_dev->poll_interval)); -} -#endif - static void send_data_to_bl301(void) { u32 val; @@ -553,13 +534,6 @@ static int meson_adc_kp_probe(struct platform_device *pdev) input->keycodesize = sizeof(unsigned short); input->keycodemax = 0x1ff; -#ifdef CONFIG_AMLOGIC_LEGACY_EARLY_SUSPEND - kp->early_suspend.level = EARLY_SUSPEND_LEVEL_BLANK_SCREEN; - kp->early_suspend.suspend = meson_adc_kp_early_suspend; - kp->early_suspend.resume = meson_adc_kp_late_resume; - register_early_suspend(&kp->early_suspend); -#endif - /*init class*/ kp->kp_class.name = DRIVE_NAME; kp->kp_class.owner = THIS_MODULE; @@ -593,9 +567,7 @@ static int meson_adc_kp_remove(struct platform_device *pdev) struct meson_adc_kp *kp = platform_get_drvdata(pdev); class_unregister(&kp->kp_class); -#ifdef CONFIG_AMLOGIC_LEGACY_EARLY_SUSPEND - unregister_early_suspend(&kp->early_suspend); -#endif + cancel_delayed_work(&kp->poll_dev->work); meson_adc_kp_list_free(kp); kfree(kp); return 0; diff --git a/drivers/amlogic/irblaster/meson-irblaster.c b/drivers/amlogic/irblaster/meson-irblaster.c index 0ec658e3e49e..f0c7e38df083 100644 --- a/drivers/amlogic/irblaster/meson-irblaster.c +++ b/drivers/amlogic/irblaster/meson-irblaster.c @@ -118,7 +118,7 @@ static void send_all_data(struct aml_irblaster_dev *dev) } if (dev->count >= dev->buffer_size) { irblaster_dbg("The all datas finished!\n"); - complete(&dev->blaster_completion); + //complete(&dev->blaster_completion); } } @@ -127,6 +127,7 @@ static irqreturn_t meson_blaster_interrupt(int irq, void *dev_id) struct aml_irblaster_dev *dev = dev_id; irblaster_dbg("meson_blaster_interrupt !!\n"); + complete(&dev->blaster_completion); /*clear pending bit*/ writel(readl(dev->reg_base + AO_IR_BLASTER_ADDR3) & (~BLASTER_FIFO_THD_PENDING), @@ -400,6 +401,7 @@ static ssize_t store_send(struct device *dev, irblaster_dbg("%d\n", irblaster_dev->buffer[i]); irblaster_dbg("sum_time = %d\n", sum_time); irblaster_dev->count = 0; + init_completion(&irblaster_dev->blaster_completion); send_all_data(irblaster_dev); ret = wait_for_completion_interruptible_timeout( &irblaster_dev->blaster_completion, diff --git a/drivers/amlogic/irqchip/Makefile b/drivers/amlogic/irqchip/Makefile index d11b37a50f88..ef4b22efe98c 100644 --- a/drivers/amlogic/irqchip/Makefile +++ b/drivers/amlogic/irqchip/Makefile @@ -1 +1,2 @@ - obj-$(CONFIG_AMLOGIC_GPIO_IRQ) += irq-meson-gpio.o + obj-$(CONFIG_AMLOGIC_GPIO_IRQ) += irq-meson-gpio.o \ + irq-meson-gpio-double-edge.o diff --git a/drivers/amlogic/irqchip/irq-meson-gpio-double-edge.c b/drivers/amlogic/irqchip/irq-meson-gpio-double-edge.c new file mode 100644 index 000000000000..41cf4eebd582 --- /dev/null +++ b/drivers/amlogic/irqchip/irq-meson-gpio-double-edge.c @@ -0,0 +1,489 @@ +/* + * drivers/amlogic/irqchip/irq-meson-gpio-double-edge.c + * + * Copyright (C) 2017 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +#include +#include +#include +#include +#include +#include + +#ifndef NO_IRQ +#define NO_IRQ ((unsigned int)(-1)) +#endif + +#define DRIVER_NAME "GPIO-INTC" +#define MESON_GPIO_BIND_PARENT_IRQ_NUM_MAX 2 + +#define REG_EDGE_POL 0x0 +#define REG_PIN_03_SEL 0x4 +#define REG_PIN_47_SEL 0x8 +#define REG_FILTER_SEL 0xc + +#define REG_EDGE_POL_MASK(x) (BIT(x) | BIT(16 + x)) +#define REG_EDGE_SET(x) BIT(x) +#define REG_POL_SET(x) BIT(16+x) +/** + * struct gpio_parent_irq - describe the parent irq for gpio + * + * @virq: virtual interrupt number of parent irq + * @owner: hwirq for gpio + */ +struct gpio_parent_irq { + int virq; + unsigned int owner; +}; + +struct meson_gpio_irq_data { + unsigned int nr_hwirq; +}; + +struct meson_gpio_intc { + unsigned char nr_gicirq; + spinlock_t lock; + void __iomem *base; + struct irq_domain *irqdomain; + struct gpio_parent_irq *parent_irqs; + const struct meson_gpio_irq_data *data; +}; + +static const struct meson_gpio_irq_data meson8_data = { + .nr_hwirq = 134, +}; + +static const struct meson_gpio_irq_data meson8b_data = { + .nr_hwirq = 119, +}; + +static const struct meson_gpio_irq_data gxbb_data = { + .nr_hwirq = 133, +}; + +static const struct meson_gpio_irq_data gxl_data = { + .nr_hwirq = 110, +}; + +static const struct meson_gpio_irq_data axg_data = { + .nr_hwirq = 100, +}; + +static const struct meson_gpio_irq_data txlx_data = { + .nr_hwirq = 119, +}; + +static const struct meson_gpio_irq_data g12a_data = { + .nr_hwirq = 100, +}; + +static const struct meson_gpio_irq_data txl_data = { + .nr_hwirq = 93, +}; + +static const struct meson_gpio_irq_data tl1_data = { + .nr_hwirq = 102, +}; + +static const struct of_device_id meson_gpio_irq_matches[] = { + { .compatible = "amlogic,meson8-gpio-intc", .data = &meson8_data }, + { .compatible = "amlogic,meson8b-gpio-intc", .data = &meson8b_data }, + { .compatible = "amlogic,meson-gxbb-gpio-intc", .data = &gxbb_data }, + { .compatible = "amlogic,meson-gxl-gpio-intc", .data = &gxl_data }, + { .compatible = "amlogic,meson-axg-gpio-intc", .data = &axg_data }, + { .compatible = "amlogic,meson-txlx-gpio-intc", .data = &txlx_data }, + { .compatible = "amlogic,meson-g12a-gpio-intc", .data = &g12a_data }, + { .compatible = "amlogic,meson-txl-gpio-intc", .data = &txl_data }, + { .compatible = "amlogic,meson-tl1-gpio-intc", .data = &tl1_data }, + { } +}; + +static void meson_reg_update_bits(void __iomem *base, unsigned int regoff, + unsigned int mask, const unsigned int val) +{ + unsigned int orig; + + orig = readl_relaxed(base + regoff); + orig = orig & (~mask); + orig |= val; + writel_relaxed(orig, base + regoff); +} + +static int meson_gpio_irq_find_by_parent_virq(struct irq_data *irqd) +{ + struct irq_desc *desc = irq_data_to_desc(irqd); + struct meson_gpio_intc *intc = irq_desc_get_handler_data(desc); + int idx; + + for (idx = 0; idx < intc->nr_gicirq; idx++) + if (intc->parent_irqs[idx].virq == irqd->irq) + return idx; + + return -EINVAL; +} + +static int meson_gpio_parent_irq_find_by_hwirq(struct irq_data *irqd, + int *data, int dlen) +{ + struct meson_gpio_intc *intc = irq_data_get_irq_chip_data(irqd); + int nr = 0; + int idx; + + for (idx = 0; idx < intc->nr_gicirq; idx++) { + if (nr >= dlen) + break; + + if (intc->parent_irqs[idx].owner == irqd->hwirq) + data[nr++] = idx; + } + + return nr; +} + +/* + * NOP functions + */ +static void noop(struct irq_data *irqd) { } + +static void meson_gpio_parent_irq_unmask(int virq) +{ + struct irq_data *parent_data; + + parent_data = irq_get_irq_data(virq); + + /*enable the interrupt line of gpio in GIC controller*/ + parent_data->chip->irq_unmask(parent_data); +} +static void meson_gpio_parent_irq_mask(int virq) +{ + struct irq_data *parent_data; + + parent_data = irq_get_irq_data(virq); + + /*disable the interrupt line of gpio in GIC controller*/ + parent_data->chip->irq_mask(parent_data); +} + +static int meson_gpio_parent_irq_request(struct irq_data *irqd, + unsigned int type) +{ + struct meson_gpio_intc *intc = irq_data_get_irq_chip_data(irqd); + struct irq_data *parent_data; + unsigned int idx; + + for (idx = 0; idx < intc->nr_gicirq; idx++) { + if (intc->parent_irqs[idx].owner == NO_IRQ) { + intc->parent_irqs[idx].owner = irqd->hwirq; + break; + } + } + + if (idx == intc->nr_gicirq) { + pr_warn("%s: no more gpio irqs available\n", DRIVER_NAME); + return -EINVAL; + } + + parent_data = irq_get_irq_data(intc->parent_irqs[idx].virq); + + /*set trigger type of gpio in GIC controller*/ + if (type & IRQ_TYPE_EDGE_BOTH) + parent_data->chip->irq_set_type(parent_data, + IRQ_TYPE_EDGE_RISING); + else + parent_data->chip->irq_set_type(parent_data, + IRQ_TYPE_LEVEL_HIGH); + + pr_info("%s: gpio virq[%d] connect to GIC hwirq[%ld]\n", DRIVER_NAME, + irqd->irq, parent_data->hwirq); + + return idx; +} + +static int meson_gpio_parent_irq_release(struct irq_data *irqd) +{ + struct meson_gpio_intc *intc = irq_data_get_irq_chip_data(irqd); + int idx[MESON_GPIO_BIND_PARENT_IRQ_NUM_MAX]; + int nr; + + nr = meson_gpio_parent_irq_find_by_hwirq(irqd, idx, ARRAY_SIZE(idx)); + while (nr--) + intc->parent_irqs[idx[nr]].owner = NO_IRQ; + + return 0; +} + +static void meson_gpio_irq_regs_config(struct irq_data *irqd, + int idx, unsigned int type) +{ + struct meson_gpio_intc *intc = irq_data_get_irq_chip_data(irqd); + unsigned int val = 0; + unsigned long flags; + int regoff; + int shift; + + spin_lock_irqsave(&intc->lock, flags); + + if (type & IRQ_TYPE_EDGE_BOTH) + val |= REG_EDGE_SET(idx); + + if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW)) + val |= REG_POL_SET(idx); + + meson_reg_update_bits(intc->base, REG_EDGE_POL, + REG_EDGE_POL_MASK(idx), val); + + /*set the filter registers*/ + shift = idx << 2; + meson_reg_update_bits(intc->base, REG_FILTER_SEL, + 0x7 << shift, 0x7 << shift); + + /*set pin select register*/ + shift = (idx << 3) % 32; + regoff = (idx < 4) ? REG_PIN_03_SEL : REG_PIN_47_SEL; + meson_reg_update_bits(intc->base, regoff, + 0xff << shift, irqd->hwirq << shift); + + spin_unlock_irqrestore(&intc->lock, flags); +} + +static void meson_gpio_irq_enable(struct irq_data *irqd) +{ + struct meson_gpio_intc *intc = irq_data_get_irq_chip_data(irqd); + int idx[MESON_GPIO_BIND_PARENT_IRQ_NUM_MAX]; + unsigned long flags; + int nr; + + spin_lock_irqsave(&intc->lock, flags); + + nr = meson_gpio_parent_irq_find_by_hwirq(irqd, + idx, ARRAY_SIZE(idx)); + + while (nr--) + meson_gpio_parent_irq_unmask(intc->parent_irqs[idx[nr]].virq); + + spin_unlock_irqrestore(&intc->lock, flags); +} + +static void meson_gpio_irq_disable(struct irq_data *irqd) +{ + struct meson_gpio_intc *intc = irq_data_get_irq_chip_data(irqd); + int idx[MESON_GPIO_BIND_PARENT_IRQ_NUM_MAX]; + unsigned long flags; + int nr; + + spin_lock_irqsave(&intc->lock, flags); + + nr = meson_gpio_parent_irq_find_by_hwirq(irqd, idx, ARRAY_SIZE(idx)); + while (nr--) + meson_gpio_parent_irq_mask(intc->parent_irqs[idx[nr]].virq); + + spin_unlock_irqrestore(&intc->lock, flags); +} + +/** + *free gpio irq when free_irq() is called, and another pin can use it again. + */ +static void meson_gpio_irq_shutdown(struct irq_data *irqd) +{ + struct meson_gpio_intc *intc = irq_data_get_irq_chip_data(irqd); + unsigned long flags; + + spin_lock_irqsave(&intc->lock, flags); + meson_gpio_parent_irq_release(irqd); + spin_unlock_irqrestore(&intc->lock, flags); + + meson_gpio_irq_disable(irqd); +} + +static int meson_gpio_irq_type(struct irq_data *irqd, unsigned int type) +{ + struct meson_gpio_intc *intc = irq_data_get_irq_chip_data(irqd); + unsigned long flags; + int nr_parent_irq; + int idx; + + type = type & IRQ_TYPE_SENSE_MASK; + nr_parent_irq = (type == IRQ_TYPE_EDGE_BOTH) ? 2 : 1; + + while (nr_parent_irq--) { + if (type == IRQ_TYPE_EDGE_BOTH) + type = IRQ_TYPE_EDGE_FALLING; + + spin_lock_irqsave(&intc->lock, flags); + idx = meson_gpio_parent_irq_request(irqd, type); + spin_unlock_irqrestore(&intc->lock, flags); + if (idx < 0) { + meson_gpio_irq_shutdown(irqd); + return -EINVAL; + } + + meson_gpio_irq_regs_config(irqd, idx, type); + + if (nr_parent_irq > 0) + type = IRQ_TYPE_EDGE_RISING; + } + + return 0; +} + +static struct irq_chip meson_gpio_intc_chip = { + .name = "meson-gpio-irqchip", + .irq_enable = meson_gpio_irq_enable, + .irq_disable = meson_gpio_irq_disable, + .irq_set_type = meson_gpio_irq_type, + .irq_mask = noop, + .irq_unmask = noop, + .irq_shutdown = meson_gpio_irq_shutdown, +}; + +static int meson_gpio_intc_domain_map(struct irq_domain *d, unsigned int virq, + irq_hw_number_t hwirq) +{ + struct meson_gpio_intc *intc = d->host_data; + + irq_set_chip_and_handler(virq, + &meson_gpio_intc_chip, handle_simple_irq); + irq_set_chip_data(virq, intc); + + return 0; +} + +static const struct irq_domain_ops meson_gpio_intc_domain_ops = { + .map = meson_gpio_intc_domain_map, + .xlate = irq_domain_xlate_twocell, +}; + +static void meson_gpio_irq_handler(struct irq_desc *desc) +{ + struct irq_chip *chip = irq_desc_get_chip(desc); + struct irq_data *parent_data = irq_desc_get_irq_data(desc); + struct meson_gpio_intc *intc = irq_desc_get_handler_data(desc); + int idx; + + chained_irq_enter(chip, desc); + + idx = meson_gpio_irq_find_by_parent_virq(parent_data); + if (idx >= 0 && intc->parent_irqs[idx].owner != NO_IRQ) + generic_handle_irq(irq_find_mapping(intc->irqdomain, + intc->parent_irqs[idx].owner)); + + chained_irq_exit(chip, desc); +} + +static int __init meson_gpio_intc_init(struct device_node *node, + struct device_node *parent) +{ + struct meson_gpio_intc *intc; + const struct of_device_id *match; + struct irq_fwspec fwspec; + int parent_hwirq; + int parent_virq; + int ret; + int idx; + + intc = kzalloc(sizeof(struct meson_gpio_intc), GFP_KERNEL); + if (!intc) + return -ENOMEM; + + match = of_match_node(meson_gpio_irq_matches, node); + if (!match) { + ret = -ENODEV; + pr_err("%s: fail to match device node\n", DRIVER_NAME); + goto alloc_err1; + } + intc->data = match->data; + + ret = of_property_count_elems_of_size(node, + "amlogic,channel-interrupts", sizeof(u32)); + if (ret <= 0) { + pr_err("%s: fail to get the number of elements\n", DRIVER_NAME); + ret = -EINVAL; + goto alloc_err1; + } + intc->nr_gicirq = ret; + + intc->parent_irqs = kcalloc(intc->nr_gicirq, + sizeof(struct gpio_parent_irq), GFP_KERNEL); + if (!intc->parent_irqs) { + ret = -ENOMEM; + goto alloc_err1; + } + + spin_lock_init(&intc->lock); + + intc->base = of_iomap(node, 0); + if (IS_ERR_OR_NULL(intc->base)) { + ret = -ENOMEM; + goto alloc_err2; + } + + intc->irqdomain = irq_domain_add_linear(node, intc->data->nr_hwirq, + &meson_gpio_intc_domain_ops, intc); + if (IS_ERR_OR_NULL(intc->irqdomain)) { + ret = -ENOMEM; + goto iomap_err; + } + + for (idx = 0; idx < intc->nr_gicirq; idx++) { + ret = of_property_read_u32_index(node, + "amlogic,channel-interrupts", idx, + &parent_hwirq); + if (ret < 0) { + pr_err("%s: fail to read property value\n", + DRIVER_NAME); + goto iomap_err; + } + + fwspec.fwnode = of_node_to_fwnode(parent); + fwspec.param_count = 3; + fwspec.param[0] = 0; + fwspec.param[1] = parent_hwirq; + fwspec.param[2] = IRQ_TYPE_EDGE_RISING; + + parent_virq = irq_create_fwspec_mapping(&fwspec); + + intc->parent_irqs[idx].virq = parent_virq; + intc->parent_irqs[idx].owner = NO_IRQ; + irq_set_handler_data(parent_virq, intc); + irq_set_chained_handler(parent_virq, meson_gpio_irq_handler); + + /*disable the interrupt line of gpio in GIC controller*/ + meson_gpio_parent_irq_mask(parent_virq); + } + + pr_info("%s: support to detect double-edge trigger signal\n", + DRIVER_NAME); + + return 0; + +iomap_err: + iounmap(intc->base); + +alloc_err2: + kfree(intc->parent_irqs); + +alloc_err1: + kfree(intc); + + return ret; +} + +/* + * if you want to use the Meson GPIO IRQ which support the + * double-edge detection, please set the compatible property + * to "amlogic,meson-gpio-intc-ext" in dts + */ +IRQCHIP_DECLARE(meson_gpio, "amlogic,meson-gpio-intc-ext", + meson_gpio_intc_init); diff --git a/drivers/amlogic/ledring/aml-is31fl32xx.c b/drivers/amlogic/ledring/aml-is31fl32xx.c index 8badc17f6aca..f21127f07d9e 100644 --- a/drivers/amlogic/ledring/aml-is31fl32xx.c +++ b/drivers/amlogic/ledring/aml-is31fl32xx.c @@ -831,7 +831,7 @@ static const struct dev_pm_ops is31fl32xx_pm = { static struct i2c_driver is31fl32xx_driver = { .driver = { - .name = "is31fl32xx", + .name = "is31fl32xx,aml", .owner = THIS_MODULE, .of_match_table = of_is31fl32xx_match, .pm = &is31fl32xx_pm, diff --git a/drivers/amlogic/media/common/arch/registers/register_ops_m8.c b/drivers/amlogic/media/common/arch/registers/register_ops_m8.c index 8e81c099d343..2d51a44ba976 100644 --- a/drivers/amlogic/media/common/arch/registers/register_ops_m8.c +++ b/drivers/amlogic/media/common/arch/registers/register_ops_m8.c @@ -31,6 +31,7 @@ MESON_CPU_MAJOR_ID_AXG, \ MESON_CPU_MAJOR_ID_G12A, \ MESON_CPU_MAJOR_ID_G12B, \ + MESON_CPU_MAJOR_ID_TL1, \ 0} #define REGISTER_FOR_GXCPU {\ MESON_CPU_MAJOR_ID_GXBB, \ @@ -42,6 +43,7 @@ MESON_CPU_MAJOR_ID_AXG, \ MESON_CPU_MAJOR_ID_G12A, \ MESON_CPU_MAJOR_ID_G12B, \ + MESON_CPU_MAJOR_ID_TL1, \ 0} int codec_apb_read(unsigned int reg) { diff --git a/drivers/amlogic/media/common/codec_mm/codec_mm.c b/drivers/amlogic/media/common/codec_mm/codec_mm.c index 4cb18537ea8c..f613c06c5b2d 100644 --- a/drivers/amlogic/media/common/codec_mm/codec_mm.c +++ b/drivers/amlogic/media/common/codec_mm/codec_mm.c @@ -44,6 +44,9 @@ #include "codec_mm_priv.h" #include "codec_mm_scatter_priv.h" #include "codec_mm_keeper_priv.h" +#include +#include +#include #define TVP_POOL_NAME "TVP_POOL" #define CMA_RES_POOL_NAME "CMA_RES" @@ -51,7 +54,6 @@ #define CONFIG_PATH "media.codec_mm" #define CONFIG_PREFIX "media" - #define MM_ALIGN_DOWN(addr, size) ((addr) & (~((size) - 1))) #define MM_ALIGN_UP2N(addr, alg2n) ((addr+(1<lock, flags); + + list_for_each_entry(mem, &mgt->mem_list, list) { + if (phy_addr >= mem->phy_addr && + phy_addr < mem->phy_addr + mem->buffer_size) { + + if (mem->vbuffer) + vaddr = mem->vbuffer + + (phy_addr - mem->phy_addr); + break; + } + } + + spin_unlock_irqrestore(&mgt->lock, flags); + + return vaddr; +} + +u8 *codec_mm_vmap(ulong addr, u32 size) +{ + u8 *vaddr = NULL; + ulong phys = addr; + u32 offset = phys & ~PAGE_MASK; + u32 npages = PAGE_ALIGN(size) / PAGE_SIZE; + struct page **pages = NULL; + pgprot_t pgprot; + int i; + + if (!PageHighMem(phys_to_page(phys))) + return phys_to_virt(phys); + + if (offset) + npages++; + + pages = vmalloc(sizeof(struct page *) * npages); + if (!pages) + return NULL; + + for (i = 0; i < npages; i++) { + pages[i] = phys_to_page(phys); + phys += PAGE_SIZE; + } + + /*nocache*/ + pgprot = pgprot_writecombine(PAGE_KERNEL); + + vaddr = vmap(pages, npages, VM_MAP, pgprot); + if (!vaddr) { + pr_err("the phy(%lx) vmaped fail, size: %d\n", + addr - offset, npages << PAGE_SHIFT); + vfree(pages); + return NULL; + } + + vfree(pages); + + if (debug_mode & 0x20) { + pr_info("[HIGH-MEM-MAP] %s, pa(%lx) to va(%p), size: %d\n", + __func__, addr, vaddr + offset, npages << PAGE_SHIFT); + } + + return vaddr + offset; +} +EXPORT_SYMBOL(codec_mm_vmap); + +void codec_mm_unmap_phyaddr(u8 *vaddr) +{ + void *addr = (void *)(PAGE_MASK & (ulong)vaddr); + + vunmap(addr); +} +EXPORT_SYMBOL(codec_mm_unmap_phyaddr); + +static void *codec_mm_map_phyaddr(struct codec_mm_s *mem) +{ + void *vaddr = NULL; + unsigned int phys = mem->phy_addr; + unsigned int size = mem->buffer_size; + + if (!PageHighMem(phys_to_page(phys))) + return phys_to_virt(phys); + + vaddr = codec_mm_vmap(phys, size); + /*vaddr = ioremap_nocache(phy_addr, size);*/ + + mem->flags |= CODEC_MM_FLAGS_FOR_PHYS_VMAPED; + + return vaddr; +} + static int codec_mm_alloc_in( struct codec_mm_mgt_s *mgt, struct codec_mm_s *mem) { @@ -417,9 +520,13 @@ static int codec_mm_alloc_in( align_2n - PAGE_SHIFT); mem->from_flags = AMPORTS_MEM_FLAGS_FROM_GET_FROM_CMA; if (mem->mem_handle) { - mem->vbuffer = mem->mem_handle; mem->phy_addr = - page_to_phys((struct page *)mem->mem_handle); + page_to_phys((struct page *) + mem->mem_handle); + + if (mem->flags & CODEC_MM_FLAGS_CPU) + mem->vbuffer = + codec_mm_map_phyaddr(mem); #ifdef CONFIG_ARM64 if (mem->flags & CODEC_MM_FLAGS_CMA_CLEAR) { /*dma_clear_buffer((struct page *)*/ @@ -495,6 +602,9 @@ static void codec_mm_free_in(struct codec_mm_mgt_s *mgt, { unsigned long flags; if (mem->from_flags == AMPORTS_MEM_FLAGS_FROM_GET_FROM_CMA) { + if (mem->flags & CODEC_MM_FLAGS_FOR_PHYS_VMAPED) + codec_mm_unmap_phyaddr(mem->vbuffer); + dma_release_from_contiguous(mgt->dev, mem->mem_handle, mem->page_count); } else if (mem->from_flags == @@ -522,6 +632,10 @@ static void codec_mm_free_in(struct codec_mm_mgt_s *mgt, mgt->alloced_for_sc_size -= mem->buffer_size; mgt->alloced_for_sc_cnt--; } + + if (mem->flags & CODEC_MM_FLAGS_FOR_PHYS_VMAPED) + mgt->phys_vmaped_page_cnt -= mem->page_count; + if (mem->from_flags == AMPORTS_MEM_FLAGS_FROM_GET_FROM_CMA) { mgt->alloced_cma_size -= mem->buffer_size; } else if (mem->from_flags == @@ -534,6 +648,7 @@ static void codec_mm_free_in(struct codec_mm_mgt_s *mgt, } else if (mem->from_flags == AMPORTS_MEM_FLAGS_FROM_GET_FROM_CMA_RES) { mgt->cma_res_pool.alloced_size -= mem->buffer_size; } + spin_unlock_irqrestore(&mgt->lock, flags); return; @@ -634,6 +749,10 @@ struct codec_mm_s *codec_mm_alloc(const char *owner, int size, mgt->alloced_for_sc_size += mem->buffer_size; mgt->alloced_for_sc_cnt++; } + + if (mem->flags & CODEC_MM_FLAGS_FOR_PHYS_VMAPED) + mgt->phys_vmaped_page_cnt += mem->page_count; + spin_unlock_irqrestore(&mgt->lock, flags); mem->alloced_jiffies = get_jiffies_64(); if (debug_mode & 0x20) @@ -729,6 +848,38 @@ void codec_mm_dma_flush(void *vaddr, } EXPORT_SYMBOL(codec_mm_dma_flush); +int codec_mm_has_owner(struct codec_mm_s *mem, const char *owner) +{ + int index; + int i; + unsigned long flags; + int is_owner = 0; + + struct codec_mm_mgt_s *mgt = get_mem_mgt(); + + if (mem) { + spin_lock_irqsave(&mgt->lock, flags); + if (!codec_mm_valid_mm_locked(mem)) { + spin_unlock_irqrestore(&mgt->lock, flags); + pr_err("codec mm %p not valied!\n", mem); + return 0; + } + + index = atomic_read(&mem->use_cnt); + + for (i = 0; i < index; i++) { + if (mem->owner[i] && + strcmp(owner, mem->owner[i]) == 0) { + is_owner = 1; + break; + } + } + spin_unlock_irqrestore(&mgt->lock, flags); + } + + return is_owner; +} + int codec_mm_request_shared_mem(struct codec_mm_s *mem, const char *owner) { struct codec_mm_mgt_s *mgt = get_mem_mgt(); @@ -911,10 +1062,20 @@ int codec_mm_extpool_pool_alloc( CODEC_MM_FLAGS_FOR_LOCAL_MGR | CODEC_MM_FLAGS_CMA); if (mem) { + if (for_tvp) { + cma_mmu_op(mem->mem_handle, + mem->page_count, + 0); + } ret = codec_mm_init_tvp_pool( tvp_pool, mem); if (ret < 0) { + if (for_tvp) { + cma_mmu_op(mem->mem_handle, + mem->page_count, + 1); + } codec_mm_release(mem, TVP_POOL_NAME); } else { alloced_size += try_alloced_size; @@ -962,6 +1123,9 @@ static int codec_mm_extpool_pool_release(struct extpool_mgt_s *tvp_pool) slot_mem_size = gen_pool_size(gpool); gen_pool_destroy(tvp_pool->gen_pool[i]); if (tvp_pool->mm[i]) { + cma_mmu_op(tvp_pool->mm[i]->mem_handle, + tvp_pool->mm[i]->page_count, + 1); codec_mm_release(tvp_pool->mm[i], TVP_POOL_NAME); } @@ -1055,11 +1219,11 @@ void *codec_mm_phys_to_virt(unsigned long phy_addr) if (phy_addr >= mgt->rmem.base && phy_addr < mgt->rmem.base + mgt->rmem.size) { if (mgt->res_mem_flags & RES_MEM_FLAGS_HAVE_MAPED) - return phys_to_virt(phy_addr); + return codec_mm_search_vaddr(phy_addr); return NULL; /* no virt for reserved memory; */ } - return phys_to_virt(phy_addr); + return codec_mm_search_vaddr(phy_addr); } EXPORT_SYMBOL(codec_mm_phys_to_virt); @@ -1144,11 +1308,12 @@ static int dump_mem_infos(void *buf, int size) pbuf += s; s = snprintf(pbuf, size - tsize, - "\tCMA:%d,RES:%d,TVP:%d,SYS:%d MB\n", + "\tCMA:%d,RES:%d,TVP:%d,SYS:%d,VMAPED:%d MB\n", mgt->alloced_cma_size / SZ_1M, mgt->alloced_res_size / SZ_1M, mgt->tvp_pool.alloced_size / SZ_1M, - mgt->alloced_sys_size / SZ_1M); + mgt->alloced_sys_size / SZ_1M, + (mgt->phys_vmaped_page_cnt << PAGE_SHIFT) / SZ_1M); tsize += s; pbuf += s; @@ -1595,7 +1760,10 @@ static ssize_t tvp_enable_help_show(struct class *class, { ssize_t size = 0; - size += sprintf(buf, "tvp enable help:\n"); + struct codec_mm_mgt_s *mgt = get_mem_mgt(); + + size += sprintf(buf, "tvp_flag=%d\n", mgt->tvp_enable); + size += sprintf(buf + size, "tvp enable help:\n"); size += sprintf(buf + size, "echo n > tvp_enable\n"); size += sprintf(buf + size, "0: disable tvp(tvp size to 0)\n"); size += sprintf(buf + size, diff --git a/drivers/amlogic/media/common/codec_mm/codec_mm_keeper.c b/drivers/amlogic/media/common/codec_mm/codec_mm_keeper.c index 9b9884562cca..114ef6fa7914 100644 --- a/drivers/amlogic/media/common/codec_mm/codec_mm_keeper.c +++ b/drivers/amlogic/media/common/codec_mm/codec_mm_keeper.c @@ -56,6 +56,11 @@ static struct codec_mm_keeper_mgr *get_codec_mm_keeper_mgr(void) return &codec_keeper_mgr_private; } +int is_codec_mm_keeped(void *mem_handle) +{ + return codec_mm_has_owner(mem_handle, KEEP_NAME); +} +EXPORT_SYMBOL(is_codec_mm_keeped); /* *not call in interrupt; */ diff --git a/drivers/amlogic/media/common/codec_mm/codec_mm_scatter.c b/drivers/amlogic/media/common/codec_mm/codec_mm_scatter.c index 5cac20b940bd..7976d837b8a4 100644 --- a/drivers/amlogic/media/common/codec_mm/codec_mm_scatter.c +++ b/drivers/amlogic/media/common/codec_mm/codec_mm_scatter.c @@ -1156,8 +1156,10 @@ static int codec_mm_scatter_free_page_id_locked( ulong phy_addr = PAGE_ADDR_OF_MMS(mms, id); free_page((unsigned long)phys_to_virt(phy_addr)); + codec_mm_list_lock(smgt); smgt->one_page_cnt--; smgt->total_page_num--; + codec_mm_list_unlock(smgt); if (id == mms->page_tail) mms->page_tail--; mms->page_cnt--; @@ -1263,7 +1265,9 @@ static int codec_mm_scatter_free_tail_pages_in( return -1; } smgt = (struct codec_mm_scatter_mgt *)mms->manager; + codec_mm_list_lock(smgt); mms->page_used = start_free_id; + codec_mm_list_unlock(smgt); if (fast_mode == 1) { codec_mm_scatter_unlock(mms); @@ -1710,7 +1714,9 @@ static int codec_mm_scatter_alloc_want_pages_in( if (want_pages > mms->page_max_cnt) return CODEC_MM_S_ERR(100); codec_mm_scatter_lock(mms); + codec_mm_list_lock(smgt); mms->page_used = want_pages; + codec_mm_list_unlock(smgt); if (want_pages > mms->page_cnt) { ret = codec_mm_page_alloc_all_locked( smgt, @@ -2207,6 +2213,7 @@ int codec_mm_scatter_mgt_delay_free_swith( int is_tvp) { struct codec_mm_scatter_mgt *smgt; + unsigned long ret = 0; smgt = codec_mm_get_scatter_mgt(is_tvp); codec_mm_list_lock(smgt); @@ -2243,9 +2250,12 @@ int codec_mm_scatter_mgt_delay_free_swith( start_time + HZ)) { break; } - wait_for_completion_timeout( + ret = wait_for_completion_timeout( &smgt->complete, HZ/10); + + if (ret == 0) + pr_debug("codec_mm_scatter_mgt_delay_free_swith time out\n"); } pr_info("end: cached pages: %d, speed %d ms\n", smgt->cached_pages, diff --git a/drivers/amlogic/media/common/rdma/rdma_mgr.c b/drivers/amlogic/media/common/rdma/rdma_mgr.c index bc562a8b19a9..c9502de22142 100644 --- a/drivers/amlogic/media/common/rdma/rdma_mgr.c +++ b/drivers/amlogic/media/common/rdma/rdma_mgr.c @@ -36,6 +36,8 @@ #include #include #include +#include +#include #include #include @@ -107,6 +109,7 @@ struct rdma_device_info { struct rdma_instance_s rdma_ins[RDMA_NUM]; }; +static struct rdma_device_data_s rdma_meson_dev; static DEFINE_SPINLOCK(rdma_lock); static struct rdma_device_info rdma_info; @@ -170,6 +173,65 @@ static struct rdma_regadr_s rdma_regadr[RDMA_NUM] = { } }; +static struct rdma_regadr_s rdma_regadr_tl1[RDMA_NUM] = { + {RDMA_AHB_START_ADDR_MAN, + RDMA_AHB_END_ADDR_MAN, + 0, 0, + RDMA_ACCESS_MAN, 1, + RDMA_ACCESS_MAN, 2, + 24, 24 + }, + {RDMA_AHB_START_ADDR_1, + RDMA_AHB_END_ADDR_1, + RDMA_AUTO_SRC1_SEL, 0, + RDMA_ACCESS_AUTO, 1, + RDMA_ACCESS_AUTO, 5, + 25, 25 + }, + {RDMA_AHB_START_ADDR_2, + RDMA_AHB_END_ADDR_2, + RDMA_AUTO_SRC2_SEL, 0, + RDMA_ACCESS_AUTO, 2, + RDMA_ACCESS_AUTO, 6, + 26, 26 + }, + {RDMA_AHB_START_ADDR_3, + RDMA_AHB_END_ADDR_3, + RDMA_AUTO_SRC3_SEL, 0, + RDMA_ACCESS_AUTO, 3, + RDMA_ACCESS_AUTO, 7, + 27, 27 + }, + {RDMA_AHB_START_ADDR_4, + RDMA_AHB_END_ADDR_4, + RDMA_AUTO_SRC4_SEL, 0, + RDMA_ACCESS_AUTO2, 0, + RDMA_ACCESS_AUTO2, 4, + 28, 28 + }, + {RDMA_AHB_START_ADDR_5, + RDMA_AHB_END_ADDR_5, + RDMA_AUTO_SRC5_SEL, 0, + RDMA_ACCESS_AUTO2, 1, + RDMA_ACCESS_AUTO2, 5, + 29, 29 + }, + {RDMA_AHB_START_ADDR_6, + RDMA_AHB_END_ADDR_6, + RDMA_AUTO_SRC6_SEL, 0, + RDMA_ACCESS_AUTO2, 2, + RDMA_ACCESS_AUTO2, 6, + 30, 30 + }, + {RDMA_AHB_START_ADDR_7, + RDMA_AHB_END_ADDR_7, + RDMA_AUTO_SRC7_SEL, 0, + RDMA_ACCESS_AUTO2, 3, + RDMA_ACCESS_AUTO2, 7, + 31, 31 + } +}; + int rdma_register(struct rdma_op_s *rdma_op, void *op_arg, int table_size) { int i; @@ -381,7 +443,7 @@ int rdma_config(int handle, int trigger_type) ins->rdma_regadr->trigger_mask_reg, 0, ins->rdma_regadr->trigger_mask_reg_bitpos, - 8); + rdma_meson_dev.trigger_mask_len); WRITE_VCBUS_REG_BITS( ins->rdma_regadr->addr_inc_reg, @@ -397,7 +459,7 @@ int rdma_config(int handle, int trigger_type) ins->rdma_regadr->trigger_mask_reg, trigger_type, ins->rdma_regadr->trigger_mask_reg_bitpos, - 8); + rdma_meson_dev.trigger_mask_len); ret = 1; ins->rdma_write_count = 0; } else if (ins->rdma_item_count <= 0 || trigger_type == 0) { @@ -410,7 +472,8 @@ int rdma_config(int handle, int trigger_type) } WRITE_VCBUS_REG_BITS( ins->rdma_regadr->trigger_mask_reg, - 0, ins->rdma_regadr->trigger_mask_reg_bitpos, 8); + 0, ins->rdma_regadr->trigger_mask_reg_bitpos, + rdma_meson_dev.trigger_mask_len); ins->rdma_write_count = 0; ret = 0; } else { @@ -460,7 +523,7 @@ int rdma_config(int handle, int trigger_type) ins->rdma_regadr->trigger_mask_reg, 0, ins->rdma_regadr->trigger_mask_reg_bitpos, - 8); + rdma_meson_dev.trigger_mask_len); WRITE_VCBUS_REG( ins->rdma_regadr->rdma_ahb_start_addr, @@ -484,7 +547,7 @@ int rdma_config(int handle, int trigger_type) ins->rdma_regadr->trigger_mask_reg, trigger_type, ins->rdma_regadr->trigger_mask_reg_bitpos, - 8); + rdma_meson_dev.trigger_mask_len); } } else if (trigger_type == 0x101) { /* debug mode */ int i; @@ -541,7 +604,8 @@ int rdma_clear(int handle) } WRITE_VCBUS_REG_BITS( ins->rdma_regadr->trigger_mask_reg, - 0, ins->rdma_regadr->trigger_mask_reg_bitpos, 8); + 0, ins->rdma_regadr->trigger_mask_reg_bitpos, + rdma_meson_dev.trigger_mask_len); ins->rdma_write_count = 0; spin_unlock_irqrestore(&rdma_lock, flags); return ret; @@ -760,6 +824,28 @@ module_param(ctrl_ahb_wr_burst_size, uint, 0664); MODULE_PARM_DESC(trace_reg, "\n trace_addr\n"); module_param(trace_reg, ushort, 0664); +static struct rdma_device_data_s rdma_meson = { + .rdma_ver = RDMA_VER_1, + .trigger_mask_len = 8, +}; + +static struct rdma_device_data_s rdma_tl1 = { + .rdma_ver = RDMA_VER_2, + .trigger_mask_len = 16, +}; + +static const struct of_device_id rdma_dt_match[] = { + { + .compatible = "amlogic, meson, rdma", + .data = &rdma_meson, + }, + { + .compatible = "amlogic, meson-tl1, rdma", + .data = &rdma_tl1, + }, + {}, +}; + /* static int __devinit rdma_probe(struct platform_device *pdev) */ static int rdma_probe(struct platform_device *pdev) { @@ -771,7 +857,31 @@ static int rdma_probe(struct platform_device *pdev) int_rdma = platform_get_irq_byname(pdev, "rdma"); - pr_info("%s\n", __func__); + if (pdev->dev.of_node) { + const struct of_device_id *match; + struct rdma_device_data_s *rdma_meson; + struct device_node *of_node = pdev->dev.of_node; + + match = of_match_node(rdma_dt_match, of_node); + if (match) { + rdma_meson = (struct rdma_device_data_s *)match->data; + if (rdma_meson) + memcpy(&rdma_meson_dev, rdma_meson, + sizeof(struct rdma_device_data_s)); + else { + pr_err("%s data NOT match\n", __func__); + return -ENODEV; + } + } else { + pr_err("%s NOT match\n", __func__); + return -ENODEV; + } + } else { + pr_err("dev %s NOT found\n", __func__); + return -ENODEV; + } + pr_info("%s,ver:%d, len:%d\n", __func__, + rdma_meson_dev.rdma_ver, rdma_meson_dev.trigger_mask_len); switch_vpu_mem_pd_vmod(VPU_RDMA, VPU_MEM_POWER_ON); @@ -783,7 +893,12 @@ static int rdma_probe(struct platform_device *pdev) for (i = 0; i < RDMA_NUM; i++) { info->rdma_ins[i].rdma_table_size = 0; - info->rdma_ins[i].rdma_regadr = &rdma_regadr[i]; + if (rdma_meson_dev.rdma_ver == RDMA_VER_1) + info->rdma_ins[i].rdma_regadr = &rdma_regadr[i]; + else if (rdma_meson_dev.rdma_ver == RDMA_VER_2) + info->rdma_ins[i].rdma_regadr = &rdma_regadr_tl1[i]; + else + info->rdma_ins[i].rdma_regadr = &rdma_regadr[i]; info->rdma_ins[i].keep_buf = 1; /*do not change it in normal case */ info->rdma_ins[i].used = 0; @@ -833,13 +948,6 @@ static int rdma_remove(struct platform_device *pdev) return 0; } -static const struct of_device_id rdma_dt_match[] = { - { - .compatible = "amlogic, meson, rdma", - }, - {}, -}; - static struct platform_driver rdma_driver = { .probe = rdma_probe, .remove = rdma_remove, diff --git a/drivers/amlogic/media/common/vfm/vframe_provider.c b/drivers/amlogic/media/common/vfm/vframe_provider.c index a8c8c32add45..e20806043cb4 100644 --- a/drivers/amlogic/media/common/vfm/vframe_provider.c +++ b/drivers/amlogic/media/common/vfm/vframe_provider.c @@ -162,7 +162,7 @@ static inline int use_provider(struct vframe_provider_s *prov) if (prov) { ret = atomic_inc_return(&prov->use_cnt); if (ret <= 0) { - atomic_dec_return(&prov->use_cnt); + atomic_dec(&prov->use_cnt); pr_err("%s: Error, provider error-%d\n", prov->name, atomic_read(&prov->use_cnt)); } @@ -172,7 +172,7 @@ static inline int use_provider(struct vframe_provider_s *prov) static inline void unuse_provider(struct vframe_provider_s *prov) { if (prov) - atomic_dec_return(&prov->use_cnt); + atomic_dec(&prov->use_cnt); } #define CLOSED_CNT -100000 static int vf_provider_close(struct vframe_provider_s *prov) diff --git a/drivers/amlogic/media/common/vpu/vpu.c b/drivers/amlogic/media/common/vpu/vpu.c index 2a10da6e8650..d7f3cffa5a4a 100644 --- a/drivers/amlogic/media/common/vpu/vpu.c +++ b/drivers/amlogic/media/common/vpu/vpu.c @@ -38,7 +38,8 @@ /* v03: add txlx support */ /* v04: add g12a support */ /* v05: add txl support */ -#define VPU_VERION "v05" +/* v20180925: add tl1 support */ +#define VPU_VERION "v20180925" int vpu_debug_print_flag; static spinlock_t vpu_mem_lock; @@ -489,7 +490,7 @@ void switch_vpu_mem_pd_vmod(unsigned int vmod, int flag) unsigned long flags = 0; unsigned int _val, _reg, _bit, _len; struct vpu_ctrl_s *table; - int i = 0, ret = 0, cnt; + int i = 0, ret = 0, done = 0, cnt; ret = vpu_chip_valid_check(); if (ret) @@ -504,23 +505,29 @@ void switch_vpu_mem_pd_vmod(unsigned int vmod, int flag) cnt = vpu_conf.data->mem_pd_table_cnt; table = vpu_conf.data->mem_pd_table; while (i < cnt) { - if (table[i].vmod == vmod) - break; if (table[i].vmod == VPU_MOD_MAX) break; + if (table[i].vmod == vmod) { + _reg = table[i].reg; + _bit = table[i].bit; + _len = table[i].len; + if (flag == VPU_MEM_POWER_ON) { + _val = 0x0; + } else { + if (_len == 32) + _val = 0xffffffff; + else + _val = (1 << _len) - 1; + } + vpu_hiu_setb(_reg, _val, _bit, _len); + done++; + } i++; } - if (table[i].vmod < VPU_MOD_MAX) { - _val = (flag == VPU_MEM_POWER_ON) ? 0x0 : 0x3; - _reg = table[i].reg; - _bit = table[i].bit; - _len = table[i].len; - vpu_hiu_setb(_reg, _val, _bit, _len); - } spin_unlock_irqrestore(&vpu_mem_lock, flags); - if (table[i].vmod == VPU_MOD_MAX) + if (done == 0) VPUPR("switch_vpu_mem_pd: unsupport vpu mod: %d\n", vmod); if (vpu_debug_print_flag) { if (vmod < VPU_MOD_MAX) { @@ -548,13 +555,11 @@ void switch_vpu_mem_pd_vmod(unsigned int vmod, int flag) * ret = get_vpu_mem_pd_vmod(VPU_VIU_OSD1); * */ -#define VPU_MEM_PD_ERR 0xffff - int get_vpu_mem_pd_vmod(unsigned int vmod) { unsigned int _reg, _bit, _len; struct vpu_ctrl_s *table; - int i = 0, ret = 0, cnt; + int i = 0, ret = 0, done = 0, cnt; ret = vpu_chip_valid_check(); if (ret) @@ -566,29 +571,28 @@ int get_vpu_mem_pd_vmod(unsigned int vmod) cnt = vpu_conf.data->mem_pd_table_cnt; table = vpu_conf.data->mem_pd_table; + ret = 0; while (i < cnt) { - if (table[i].vmod == vmod) - break; if (table[i].vmod == VPU_MOD_MAX) break; + if (table[i].vmod == vmod) { + _reg = table[i].reg; + _bit = table[i].bit; + _len = table[i].len; + ret += vpu_hiu_getb(_reg, _bit, _len); + done++; + } i++; } - if (table[i].vmod == VPU_MOD_MAX) { + if (done == 0) { VPUPR("get_vpu_mem_pd: unsupport vpu mod: %d\n", vmod); return -1; } - _reg = table[i].reg; - _bit = table[i].bit; - _len = table[i].len; - ret = vpu_hiu_getb(_reg, _bit, _len); - if (ret == 0) return VPU_MEM_POWER_ON; - else if ((ret == 0x3) || (ret == 0xf)) - return VPU_MEM_POWER_DOWN; else - return -1; + return VPU_MEM_POWER_DOWN; } /* *********************************************** */ @@ -614,7 +618,7 @@ void switch_vpu_clk_gate_vmod(unsigned int vmod, int flag) { unsigned int _val, _reg, _bit, _len; struct vpu_ctrl_s *table; - int i = 0, ret = 0, m = 0, cnt; + int i = 0, ret = 0, done = 0, cnt; unsigned long flags = 0; ret = vpu_chip_valid_check(); @@ -630,26 +634,30 @@ void switch_vpu_clk_gate_vmod(unsigned int vmod, int flag) cnt = vpu_conf.data->clk_gate_table_cnt; table = vpu_conf.data->clk_gate_table; while (i < cnt) { + if (table[i].vmod == VPU_MAX) + break; if (table[i].vmod == vmod) { _reg = table[i].reg; _bit = table[i].bit; _len = table[i].len; - if (flag == VPU_CLK_GATE_ON) - _val = (1 << _len) - 1; - else + if (flag == VPU_CLK_GATE_ON) { + if (_len == 32) + _val = 0xffffffff; + else + _val = (1 << _len) - 1; + } else { _val = 0; + } vpu_vcbus_setb(_reg, _val, _bit, _len); - m++; - } else if (table[i].vmod == VPU_MAX) - break; + done++; + } i++; } spin_unlock_irqrestore(&vpu_clk_gate_lock, flags); - if (m == 0) + if (done == 0) VPUPR("switch_vpu_clk_gate: unsupport vpu mod: %d\n", vmod); - if (vpu_debug_print_flag) { if (vmod < VPU_MAX) { VPUPR("switch_vpu_clk_gate: %s %s\n", @@ -774,13 +782,15 @@ static ssize_t vpu_clk_debug(struct class *class, struct class_attribute *attr, static ssize_t vpu_mem_debug(struct class *class, struct class_attribute *attr, const char *buf, size_t count) { - unsigned int tmp[2]; - unsigned int _reg0, _reg1, _reg2; + unsigned int tmp[2], val; + unsigned int _reg0, _reg1, _reg2, _reg3, _reg4; int ret = 0, i; _reg0 = HHI_VPU_MEM_PD_REG0; _reg1 = HHI_VPU_MEM_PD_REG1; _reg2 = HHI_VPU_MEM_PD_REG2; + _reg3 = HHI_VPU_MEM_PD_REG3; + _reg4 = HHI_VPU_MEM_PD_REG4; switch (buf[0]) { case 'r': VPUPR("mem_pd0: 0x%08x\n", vpu_hiu_read(_reg0)); @@ -788,6 +798,10 @@ static ssize_t vpu_mem_debug(struct class *class, struct class_attribute *attr, VPUPR("mem_pd1: 0x%08x\n", vpu_hiu_read(_reg1)); if (vpu_conf.data->mem_pd_reg2_valid) VPUPR("mem_pd2: 0x%08x\n", vpu_hiu_read(_reg2)); + if (vpu_conf.data->mem_pd_reg3_valid) + VPUPR("mem_pd2: 0x%08x\n", vpu_hiu_read(_reg3)); + if (vpu_conf.data->mem_pd_reg4_valid) + VPUPR("mem_pd2: 0x%08x\n", vpu_hiu_read(_reg4)); break; case 'w': ret = sscanf(buf, "w %u %u", &tmp[0], &tmp[1]); @@ -804,8 +818,13 @@ static ssize_t vpu_mem_debug(struct class *class, struct class_attribute *attr, break; case 'i': VPUPR("vpu modules:\n"); - for (i = VPU_VIU_OSD1; i < VPU_MOD_MAX; i++) - pr_info(" [%02d] %s\n", i, vpu_mod_table[i]); + for (i = VPU_VIU_OSD1; i < VPU_MOD_MAX; i++) { + val = get_vpu_mem_pd_vmod(i); + pr_info(" [%02d] %s %s(%d)\n", + i, vpu_mod_table[i], + (val == VPU_MEM_POWER_ON) ? "ON" : "OFF", + val); + } break; default: VPUERR("wrong mem_pd command\n"); @@ -961,6 +980,14 @@ static ssize_t vpu_debug_info(struct class *class, len += sprintf(buf+len, " mem_pd2: 0x%08x\n", vpu_hiu_read(HHI_VPU_MEM_PD_REG2)); } + if (vpu_conf.data->mem_pd_reg3_valid) { + len += sprintf(buf+len, " mem_pd3: 0x%08x\n", + vpu_hiu_read(HHI_VPU_MEM_PD_REG3)); + } + if (vpu_conf.data->mem_pd_reg4_valid) { + len += sprintf(buf+len, " mem_pd4: 0x%08x\n", + vpu_hiu_read(HHI_VPU_MEM_PD_REG4)); + } #ifdef CONFIG_VPU_DYNAMIC_ADJ if (vpu_conf.clk_vmod) { @@ -1161,13 +1188,11 @@ static int vpu_power_init_check(void) int ret = 0; val = vpu_hiu_getb(HHI_VPU_CLK_CNTL, 31, 1); - if (val) { - if (vpu_hiu_getb(HHI_VPU_CLK_CNTL, 24, 1) == 0) - ret = 1; - } else { - if (vpu_hiu_getb(HHI_VPU_CLK_CNTL, 8, 1) == 0) - ret = 1; - } + if (val) + val = vpu_hiu_getb(HHI_VPU_CLK_CNTL, 24, 1); + else + val = vpu_hiu_getb(HHI_VPU_CLK_CNTL, 8, 1); + ret = (val == 0) ? 1 : 0; return ret; } @@ -1180,9 +1205,8 @@ static void vpu_power_init(void) if (ret) return; - vpu_conf.data->power_on(); + vpu_power_on(); vpu_mem_pd_init_off(); - vpu_clk_gate_init_off(); vpu_module_init_config(); } @@ -1196,6 +1220,8 @@ static struct vpu_data_s vpu_data_gxb = { .gp_pll_valid = 1, .mem_pd_reg1_valid = 1, .mem_pd_reg2_valid = 0, + .mem_pd_reg3_valid = 0, + .mem_pd_reg4_valid = 0, .mem_pd_table_cnt = sizeof(vpu_mem_pd_gxb) / sizeof(struct vpu_ctrl_s), @@ -1204,12 +1230,13 @@ static struct vpu_data_s vpu_data_gxb = { .mem_pd_table = vpu_mem_pd_gxb, .clk_gate_table = vpu_clk_gate_gxb, - .power_on = vpu_power_on_gx, - .power_off = vpu_power_off_gx, + .module_init_table_cnt = 0, + .module_init_table = NULL, + .reset_table = vpu_reset_gx, }; static struct vpu_data_s vpu_data_gxtvbb = { - .chip_type = VPU_CHIP_GXBB, + .chip_type = VPU_CHIP_GXTVBB, .chip_name = "gxtvbb", .clk_level_dft = CLK_LEVEL_DFT_GXTVBB, .clk_level_max = CLK_LEVEL_MAX_GXTVBB, @@ -1218,6 +1245,8 @@ static struct vpu_data_s vpu_data_gxtvbb = { .gp_pll_valid = 1, .mem_pd_reg1_valid = 1, .mem_pd_reg2_valid = 0, + .mem_pd_reg3_valid = 0, + .mem_pd_reg4_valid = 0, .mem_pd_table_cnt = sizeof(vpu_mem_pd_gxtvbb) / sizeof(struct vpu_ctrl_s), @@ -1226,8 +1255,9 @@ static struct vpu_data_s vpu_data_gxtvbb = { .mem_pd_table = vpu_mem_pd_gxtvbb, .clk_gate_table = vpu_clk_gate_gxl, - .power_on = vpu_power_on_gx, - .power_off = vpu_power_off_gx, + .module_init_table_cnt = 0, + .module_init_table = NULL, + .reset_table = vpu_reset_gx, }; static struct vpu_data_s vpu_data_gxl = { @@ -1240,6 +1270,8 @@ static struct vpu_data_s vpu_data_gxl = { .gp_pll_valid = 1, .mem_pd_reg1_valid = 1, .mem_pd_reg2_valid = 1, + .mem_pd_reg3_valid = 0, + .mem_pd_reg4_valid = 0, .mem_pd_table_cnt = sizeof(vpu_mem_pd_gxl) / sizeof(struct vpu_ctrl_s), @@ -1248,8 +1280,9 @@ static struct vpu_data_s vpu_data_gxl = { .mem_pd_table = vpu_mem_pd_gxl, .clk_gate_table = vpu_clk_gate_gxl, - .power_on = vpu_power_on_gx, - .power_off = vpu_power_off_gx, + .module_init_table_cnt = 0, + .module_init_table = NULL, + .reset_table = vpu_reset_gx, }; static struct vpu_data_s vpu_data_gxm = { @@ -1262,6 +1295,8 @@ static struct vpu_data_s vpu_data_gxm = { .gp_pll_valid = 1, .mem_pd_reg1_valid = 1, .mem_pd_reg2_valid = 1, + .mem_pd_reg3_valid = 0, + .mem_pd_reg4_valid = 0, .mem_pd_table_cnt = sizeof(vpu_mem_pd_gxl) / sizeof(struct vpu_ctrl_s), @@ -1270,8 +1305,10 @@ static struct vpu_data_s vpu_data_gxm = { .mem_pd_table = vpu_mem_pd_gxl, .clk_gate_table = vpu_clk_gate_gxl, - .power_on = vpu_power_on_gx, - .power_off = vpu_power_off_gx, + .module_init_table_cnt = + sizeof(vpu_module_init_gxm) / sizeof(struct vpu_ctrl_s), + .module_init_table = vpu_module_init_gxm, + .reset_table = vpu_reset_gx, }; static struct vpu_data_s vpu_data_txl = { @@ -1284,6 +1321,8 @@ static struct vpu_data_s vpu_data_txl = { .gp_pll_valid = 0, .mem_pd_reg1_valid = 1, .mem_pd_reg2_valid = 0, + .mem_pd_reg3_valid = 0, + .mem_pd_reg4_valid = 0, .mem_pd_table_cnt = sizeof(vpu_mem_pd_txl) / sizeof(struct vpu_ctrl_s), @@ -1292,8 +1331,9 @@ static struct vpu_data_s vpu_data_txl = { .mem_pd_table = vpu_mem_pd_txl, .clk_gate_table = vpu_clk_gate_txl, - .power_on = vpu_power_on_txlx, - .power_off = vpu_power_off_txlx, + .module_init_table_cnt = 0, + .module_init_table = NULL, + .reset_table = vpu_reset_gx, }; static struct vpu_data_s vpu_data_txlx = { @@ -1306,6 +1346,8 @@ static struct vpu_data_s vpu_data_txlx = { .gp_pll_valid = 1, .mem_pd_reg1_valid = 1, .mem_pd_reg2_valid = 1, + .mem_pd_reg3_valid = 0, + .mem_pd_reg4_valid = 0, .mem_pd_table_cnt = sizeof(vpu_mem_pd_txlx) / sizeof(struct vpu_ctrl_s), @@ -1314,8 +1356,10 @@ static struct vpu_data_s vpu_data_txlx = { .mem_pd_table = vpu_mem_pd_txlx, .clk_gate_table = vpu_clk_gate_txlx, - .power_on = vpu_power_on_txlx, - .power_off = vpu_power_off_txlx, + .module_init_table_cnt = + sizeof(vpu_module_init_txlx) / sizeof(struct vpu_ctrl_s), + .module_init_table = vpu_module_init_txlx, + .reset_table = vpu_reset_txlx, }; static struct vpu_data_s vpu_data_axg = { @@ -1328,6 +1372,8 @@ static struct vpu_data_s vpu_data_axg = { .gp_pll_valid = 0, .mem_pd_reg1_valid = 0, .mem_pd_reg2_valid = 0, + .mem_pd_reg3_valid = 0, + .mem_pd_reg4_valid = 0, .mem_pd_table_cnt = sizeof(vpu_mem_pd_axg) / sizeof(struct vpu_ctrl_s), @@ -1336,8 +1382,9 @@ static struct vpu_data_s vpu_data_axg = { .mem_pd_table = vpu_mem_pd_axg, .clk_gate_table = vpu_clk_gate_axg, - .power_on = vpu_power_on_txlx, - .power_off = vpu_power_off_txlx, + .module_init_table_cnt = 0, + .module_init_table = NULL, + .reset_table = vpu_reset_txlx, }; static struct vpu_data_s vpu_data_g12a = { @@ -1350,16 +1397,19 @@ static struct vpu_data_s vpu_data_g12a = { .gp_pll_valid = 0, .mem_pd_reg1_valid = 1, .mem_pd_reg2_valid = 1, + .mem_pd_reg3_valid = 0, + .mem_pd_reg4_valid = 0, .mem_pd_table_cnt = - sizeof(vpu_mem_pd_g12b) / sizeof(struct vpu_ctrl_s), + sizeof(vpu_mem_pd_g12a) / sizeof(struct vpu_ctrl_s), .clk_gate_table_cnt = sizeof(vpu_clk_gate_g12a) / sizeof(struct vpu_ctrl_s), - .mem_pd_table = vpu_mem_pd_g12b, + .mem_pd_table = vpu_mem_pd_g12a, .clk_gate_table = vpu_clk_gate_g12a, - .power_on = vpu_power_on_txlx, - .power_off = vpu_power_off_txlx, + .module_init_table_cnt = 0, + .module_init_table = NULL, + .reset_table = vpu_reset_txlx, }; static struct vpu_data_s vpu_data_g12b = { @@ -1372,16 +1422,44 @@ static struct vpu_data_s vpu_data_g12b = { .gp_pll_valid = 0, .mem_pd_reg1_valid = 1, .mem_pd_reg2_valid = 1, + .mem_pd_reg3_valid = 0, + .mem_pd_reg4_valid = 0, .mem_pd_table_cnt = - sizeof(vpu_mem_pd_g12a) / sizeof(struct vpu_ctrl_s), + sizeof(vpu_mem_pd_g12b) / sizeof(struct vpu_ctrl_s), .clk_gate_table_cnt = sizeof(vpu_clk_gate_g12a) / sizeof(struct vpu_ctrl_s), - .mem_pd_table = vpu_mem_pd_g12a, + .mem_pd_table = vpu_mem_pd_g12b, .clk_gate_table = vpu_clk_gate_g12a, - .power_on = vpu_power_on_txlx, - .power_off = vpu_power_off_txlx, + .module_init_table_cnt = 0, + .module_init_table = NULL, + .reset_table = vpu_reset_txlx, +}; + +static struct vpu_data_s vpu_data_tl1 = { + .chip_type = VPU_CHIP_TL1, + .chip_name = "tl1", + .clk_level_dft = CLK_LEVEL_DFT_G12A, + .clk_level_max = CLK_LEVEL_MAX_G12A, + .fclk_div_table = fclk_div_table_g12a, + + .gp_pll_valid = 0, + .mem_pd_reg1_valid = 1, + .mem_pd_reg2_valid = 1, + .mem_pd_reg3_valid = 1, + .mem_pd_reg4_valid = 1, + + .mem_pd_table_cnt = + sizeof(vpu_mem_pd_tl1) / sizeof(struct vpu_ctrl_s), + .clk_gate_table_cnt = + sizeof(vpu_clk_gate_g12a) / sizeof(struct vpu_ctrl_s), + .mem_pd_table = vpu_mem_pd_tl1, + .clk_gate_table = vpu_clk_gate_g12a, + + .module_init_table_cnt = 0, + .module_init_table = NULL, + .reset_table = vpu_reset_tl1, }; static const struct of_device_id vpu_of_table[] = { @@ -1421,6 +1499,10 @@ static const struct of_device_id vpu_of_table[] = { .compatible = "amlogic, vpu-g12b", .data = &vpu_data_g12b, }, + { + .compatible = "amlogic, vpu-tl1", + .data = &vpu_data_tl1, + }, {}, }; diff --git a/drivers/amlogic/media/common/vpu/vpu.h b/drivers/amlogic/media/common/vpu/vpu.h index 77e494efce30..997f96c9c8ea 100644 --- a/drivers/amlogic/media/common/vpu/vpu.h +++ b/drivers/amlogic/media/common/vpu/vpu.h @@ -35,9 +35,13 @@ enum vpu_chip_e { VPU_CHIP_AXG, VPU_CHIP_G12A, VPU_CHIP_G12B, + VPU_CHIP_TL1, VPU_CHIP_MAX, }; +#define VPU_REG_END 0xffff +#define VPU_RESET_CNT_MAX 10 + struct fclk_div_s { unsigned int fclk_id; unsigned int fclk_mux; @@ -53,10 +57,16 @@ struct vpu_clk_s { struct vpu_ctrl_s { unsigned int vmod; unsigned int reg; + unsigned int val; unsigned int bit; unsigned int len; }; +struct vpu_reset_s { + unsigned int reg; + unsigned int mask; +}; + struct vpu_data_s { enum vpu_chip_e chip_type; const char *chip_name; @@ -67,14 +77,17 @@ struct vpu_data_s { unsigned char gp_pll_valid; unsigned char mem_pd_reg1_valid; unsigned char mem_pd_reg2_valid; + unsigned char mem_pd_reg3_valid; + unsigned char mem_pd_reg4_valid; unsigned int mem_pd_table_cnt; unsigned int clk_gate_table_cnt; struct vpu_ctrl_s *mem_pd_table; struct vpu_ctrl_s *clk_gate_table; - void (*power_on)(void); - void (*power_off)(void); + unsigned int module_init_table_cnt; + struct vpu_ctrl_s *module_init_table; + struct vpu_reset_s *reset_table; }; struct vpu_conf_s { @@ -102,11 +115,8 @@ extern int vpu_chip_valid_check(void); extern void vpu_ctrl_probe(void); extern void vpu_mem_pd_init_off(void); -extern void vpu_clk_gate_init_off(void); extern void vpu_module_init_config(void); -extern void vpu_power_on_gx(void); -extern void vpu_power_off_gx(void); -extern void vpu_power_on_txlx(void); -extern void vpu_power_off_txlx(void); +extern void vpu_power_on(void); +extern void vpu_power_off(void); #endif diff --git a/drivers/amlogic/media/common/vpu/vpu_ctrl.h b/drivers/amlogic/media/common/vpu/vpu_ctrl.h index a38758d44bfb..ca0eb494511b 100644 --- a/drivers/amlogic/media/common/vpu/vpu_ctrl.h +++ b/drivers/amlogic/media/common/vpu/vpu_ctrl.h @@ -18,12 +18,11 @@ #ifndef __VPU_CTRL_H__ #define __VPU_CTRL_H__ #include +#include "vpu_reg.h" #include "vpu.h" /* #define LIMIT_VPU_CLK_LOW */ -#define VPU_REG_END 0xffff - /* ************************************************ */ /* VPU frequency table, important. DO NOT modify!! */ /* ************************************************ */ @@ -118,411 +117,526 @@ static struct vpu_clk_s vpu_clk_table[] = { /* VPU memory power down table */ /* ******************************************************* */ static struct vpu_ctrl_s vpu_mem_pd_gxb[] = { - /* vpu module, reg, bit, len */ - {VPU_VIU_OSD1, HHI_VPU_MEM_PD_REG0, 0, 2}, - {VPU_VIU_OSD2, HHI_VPU_MEM_PD_REG0, 2, 2}, - {VPU_VIU_VD1, HHI_VPU_MEM_PD_REG0, 4, 2}, - {VPU_VIU_VD2, HHI_VPU_MEM_PD_REG0, 6, 2}, - {VPU_VIU_CHROMA, HHI_VPU_MEM_PD_REG0, 8, 2}, - {VPU_VIU_OFIFO, HHI_VPU_MEM_PD_REG0, 10, 2}, - {VPU_VIU_SCALE, HHI_VPU_MEM_PD_REG0, 12, 2}, - {VPU_VIU_OSD_SCALE, HHI_VPU_MEM_PD_REG0, 14, 2}, - {VPU_VIU_VDIN0, HHI_VPU_MEM_PD_REG0, 16, 2}, - {VPU_VIU_VDIN1, HHI_VPU_MEM_PD_REG0, 18, 2}, - {VPU_VIU_SRSCL, HHI_VPU_MEM_PD_REG0, 20, 2}, - {VPU_VIU_OSDSR, HHI_VPU_MEM_PD_REG0, 22, 2}, - {VPU_DI_PRE, HHI_VPU_MEM_PD_REG0, 26, 2}, - {VPU_DI_POST, HHI_VPU_MEM_PD_REG0, 28, 2}, - {VPU_SHARP, HHI_VPU_MEM_PD_REG0, 30, 2}, - {VPU_VPU_ARB, HHI_VPU_MEM_PD_REG1, 14, 2}, - {VPU_AFBC_DEC, HHI_VPU_MEM_PD_REG1, 16, 2}, - {VPU_VENCP, HHI_VPU_MEM_PD_REG1, 20, 2}, - {VPU_VENCL, HHI_VPU_MEM_PD_REG1, 22, 2}, - {VPU_VENCI, HHI_VPU_MEM_PD_REG1, 24, 2}, - {VPU_MOD_MAX, VPU_REG_END, 0, 0}, + /* vpu module, reg, val, bit, len */ + {VPU_VIU_OSD1, HHI_VPU_MEM_PD_REG0, 0x3, 0, 2}, + {VPU_VIU_OSD2, HHI_VPU_MEM_PD_REG0, 0x3, 2, 2}, + {VPU_VIU_VD1, HHI_VPU_MEM_PD_REG0, 0x3, 4, 2}, + {VPU_VIU_VD2, HHI_VPU_MEM_PD_REG0, 0x3, 6, 2}, + {VPU_VIU_CHROMA, HHI_VPU_MEM_PD_REG0, 0x3, 8, 2}, + {VPU_VIU_OFIFO, HHI_VPU_MEM_PD_REG0, 0x3, 10, 2}, + {VPU_VIU_SCALE, HHI_VPU_MEM_PD_REG0, 0x3, 12, 2}, + {VPU_VIU_OSD_SCALE, HHI_VPU_MEM_PD_REG0, 0x3, 14, 2}, + {VPU_VIU_VDIN0, HHI_VPU_MEM_PD_REG0, 0x3, 16, 2}, + {VPU_VIU_VDIN1, HHI_VPU_MEM_PD_REG0, 0x3, 18, 2}, + {VPU_VIU_SRSCL, HHI_VPU_MEM_PD_REG0, 0x3, 20, 2}, + {VPU_VIU_OSDSR, HHI_VPU_MEM_PD_REG0, 0x3, 22, 2}, + {VPU_DI_PRE, HHI_VPU_MEM_PD_REG0, 0x3, 26, 2}, + {VPU_DI_POST, HHI_VPU_MEM_PD_REG0, 0x3, 28, 2}, + {VPU_SHARP, HHI_VPU_MEM_PD_REG0, 0x3, 30, 2}, + {VPU_VPU_ARB, HHI_VPU_MEM_PD_REG1, 0x3, 14, 2}, + {VPU_AFBC_DEC, HHI_VPU_MEM_PD_REG1, 0x3, 16, 2}, + {VPU_VENCP, HHI_VPU_MEM_PD_REG1, 0x3, 20, 2}, + {VPU_VENCL, HHI_VPU_MEM_PD_REG1, 0x3, 22, 2}, + {VPU_VENCI, HHI_VPU_MEM_PD_REG1, 0x3, 24, 2}, + {VPU_MOD_MAX, VPU_REG_END, 0, 0, 0}, }; static struct vpu_ctrl_s vpu_mem_pd_gxtvbb[] = { - /* vpu module, reg, bit, len */ - {VPU_VIU_OSD1, HHI_VPU_MEM_PD_REG0, 0, 2}, - {VPU_VIU_OSD2, HHI_VPU_MEM_PD_REG0, 2, 2}, - {VPU_VIU_VD1, HHI_VPU_MEM_PD_REG0, 4, 2}, - {VPU_VIU_VD2, HHI_VPU_MEM_PD_REG0, 6, 2}, - {VPU_VIU_CHROMA, HHI_VPU_MEM_PD_REG0, 8, 2}, - {VPU_VIU_OFIFO, HHI_VPU_MEM_PD_REG0, 10, 2}, - {VPU_VIU_SCALE, HHI_VPU_MEM_PD_REG0, 12, 2}, - {VPU_VIU_OSD_SCALE, HHI_VPU_MEM_PD_REG0, 14, 2}, - {VPU_VIU_VDIN0, HHI_VPU_MEM_PD_REG0, 16, 2}, - {VPU_VIU_VDIN1, HHI_VPU_MEM_PD_REG0, 18, 2}, - {VPU_VIU_SRSCL, HHI_VPU_MEM_PD_REG0, 20, 2}, - {VPU_AFBC_DEC1, HHI_VPU_MEM_PD_REG0, 22, 2}, - {VPU_DI_PRE, HHI_VPU_MEM_PD_REG0, 26, 2}, - {VPU_DI_POST, HHI_VPU_MEM_PD_REG0, 28, 2}, - {VPU_SHARP, HHI_VPU_MEM_PD_REG0, 30, 2}, - {VPU_VPU_ARB, HHI_VPU_MEM_PD_REG1, 14, 2}, - {VPU_AFBC_DEC, HHI_VPU_MEM_PD_REG1, 16, 2}, - {VPU_VENCP, HHI_VPU_MEM_PD_REG1, 20, 2}, - {VPU_VENCL, HHI_VPU_MEM_PD_REG1, 22, 2}, - {VPU_VENCI, HHI_VPU_MEM_PD_REG1, 24, 2}, - {VPU_LDIM_STTS, HHI_VPU_MEM_PD_REG1, 28, 2}, - {VPU_XVYCC_LUT, HHI_VPU_MEM_PD_REG1, 30, 2}, - {VPU_MOD_MAX, VPU_REG_END, 0, 0}, + /* vpu module, reg, val, bit, len */ + {VPU_VIU_OSD1, HHI_VPU_MEM_PD_REG0, 0x3, 0, 2}, + {VPU_VIU_OSD2, HHI_VPU_MEM_PD_REG0, 0x3, 2, 2}, + {VPU_VIU_VD1, HHI_VPU_MEM_PD_REG0, 0x3, 4, 2}, + {VPU_VIU_VD2, HHI_VPU_MEM_PD_REG0, 0x3, 6, 2}, + {VPU_VIU_CHROMA, HHI_VPU_MEM_PD_REG0, 0x3, 8, 2}, + {VPU_VIU_OFIFO, HHI_VPU_MEM_PD_REG0, 0x3, 10, 2}, + {VPU_VIU_SCALE, HHI_VPU_MEM_PD_REG0, 0x3, 12, 2}, + {VPU_VIU_OSD_SCALE, HHI_VPU_MEM_PD_REG0, 0x3, 14, 2}, + {VPU_VIU_VDIN0, HHI_VPU_MEM_PD_REG0, 0x3, 16, 2}, + {VPU_VIU_VDIN1, HHI_VPU_MEM_PD_REG0, 0x3, 18, 2}, + {VPU_VIU_SRSCL, HHI_VPU_MEM_PD_REG0, 0x3, 20, 2}, + {VPU_AFBC_DEC1, HHI_VPU_MEM_PD_REG0, 0x3, 22, 2}, + {VPU_DI_PRE, HHI_VPU_MEM_PD_REG0, 0x3, 26, 2}, + {VPU_DI_POST, HHI_VPU_MEM_PD_REG0, 0x3, 28, 2}, + {VPU_SHARP, HHI_VPU_MEM_PD_REG0, 0x3, 30, 2}, + {VPU_VPU_ARB, HHI_VPU_MEM_PD_REG1, 0x3, 14, 2}, + {VPU_AFBC_DEC, HHI_VPU_MEM_PD_REG1, 0x3, 16, 2}, + {VPU_VENCP, HHI_VPU_MEM_PD_REG1, 0x3, 20, 2}, + {VPU_VENCL, HHI_VPU_MEM_PD_REG1, 0x3, 22, 2}, + {VPU_VENCI, HHI_VPU_MEM_PD_REG1, 0x3, 24, 2}, + {VPU_LDIM_STTS, HHI_VPU_MEM_PD_REG1, 0x3, 28, 2}, + {VPU_XVYCC_LUT, HHI_VPU_MEM_PD_REG1, 0x3, 30, 2}, + {VPU_MOD_MAX, VPU_REG_END, 0, 0, 0}, }; static struct vpu_ctrl_s vpu_mem_pd_gxl[] = { - /* vpu module, reg, bit, len */ - {VPU_VIU_OSD1, HHI_VPU_MEM_PD_REG0, 0, 2}, - {VPU_VIU_OSD2, HHI_VPU_MEM_PD_REG0, 2, 2}, - {VPU_VIU_VD1, HHI_VPU_MEM_PD_REG0, 4, 2}, - {VPU_VIU_VD2, HHI_VPU_MEM_PD_REG0, 6, 2}, - {VPU_VIU_CHROMA, HHI_VPU_MEM_PD_REG0, 8, 2}, - {VPU_VIU_OFIFO, HHI_VPU_MEM_PD_REG0, 10, 2}, - {VPU_VIU_SCALE, HHI_VPU_MEM_PD_REG0, 12, 2}, - {VPU_VIU_OSD_SCALE, HHI_VPU_MEM_PD_REG0, 14, 2}, - {VPU_VIU_VDIN0, HHI_VPU_MEM_PD_REG0, 16, 2}, - {VPU_VIU_VDIN1, HHI_VPU_MEM_PD_REG0, 18, 2}, - {VPU_DI_PRE, HHI_VPU_MEM_PD_REG0, 26, 2}, - {VPU_DI_POST, HHI_VPU_MEM_PD_REG0, 28, 2}, - {VPU_SHARP, HHI_VPU_MEM_PD_REG0, 30, 2}, - {VPU_VPU_ARB, HHI_VPU_MEM_PD_REG1, 14, 2}, - {VPU_AFBC_DEC, HHI_VPU_MEM_PD_REG1, 16, 2}, - {VPU_VENCP, HHI_VPU_MEM_PD_REG1, 20, 2}, - {VPU_VENCL, HHI_VPU_MEM_PD_REG1, 22, 2}, - {VPU_VENCI, HHI_VPU_MEM_PD_REG1, 24, 2}, - {VPU_VIU_WM, HHI_VPU_MEM_PD_REG2, 0, 2}, - {VPU_MOD_MAX, VPU_REG_END, 0, 0}, + /* vpu module, reg, val, bit, len */ + {VPU_VIU_OSD1, HHI_VPU_MEM_PD_REG0, 0x3, 0, 2}, + {VPU_VIU_OSD2, HHI_VPU_MEM_PD_REG0, 0x3, 2, 2}, + {VPU_VIU_VD1, HHI_VPU_MEM_PD_REG0, 0x3, 4, 2}, + {VPU_VIU_VD2, HHI_VPU_MEM_PD_REG0, 0x3, 6, 2}, + {VPU_VIU_CHROMA, HHI_VPU_MEM_PD_REG0, 0x3, 8, 2}, + {VPU_VIU_OFIFO, HHI_VPU_MEM_PD_REG0, 0x3, 10, 2}, + {VPU_VIU_SCALE, HHI_VPU_MEM_PD_REG0, 0x3, 12, 2}, + {VPU_VIU_OSD_SCALE, HHI_VPU_MEM_PD_REG0, 0x3, 14, 2}, + {VPU_VIU_VDIN0, HHI_VPU_MEM_PD_REG0, 0x3, 16, 2}, + {VPU_VIU_VDIN1, HHI_VPU_MEM_PD_REG0, 0x3, 18, 2}, + {VPU_DI_PRE, HHI_VPU_MEM_PD_REG0, 0x3, 26, 2}, + {VPU_DI_POST, HHI_VPU_MEM_PD_REG0, 0x3, 28, 2}, + {VPU_SHARP, HHI_VPU_MEM_PD_REG0, 0x3, 30, 2}, + {VPU_VPU_ARB, HHI_VPU_MEM_PD_REG1, 0x3, 14, 2}, + {VPU_AFBC_DEC, HHI_VPU_MEM_PD_REG1, 0x3, 16, 2}, + {VPU_VENCP, HHI_VPU_MEM_PD_REG1, 0x3, 20, 2}, + {VPU_VENCL, HHI_VPU_MEM_PD_REG1, 0x3, 22, 2}, + {VPU_VENCI, HHI_VPU_MEM_PD_REG1, 0x3, 24, 2}, + {VPU_VIU_WM, HHI_VPU_MEM_PD_REG2, 0x3, 0, 2}, + {VPU_MOD_MAX, VPU_REG_END, 0, 0, 0}, }; static struct vpu_ctrl_s vpu_mem_pd_txl[] = { - /* vpu module, reg, bit, len */ - {VPU_VIU_OSD1, HHI_VPU_MEM_PD_REG0, 0, 2}, - {VPU_VIU_OSD2, HHI_VPU_MEM_PD_REG0, 2, 2}, - {VPU_VIU_VD1, HHI_VPU_MEM_PD_REG0, 4, 2}, - {VPU_VIU_VD2, HHI_VPU_MEM_PD_REG0, 6, 2}, - {VPU_VIU_CHROMA, HHI_VPU_MEM_PD_REG0, 8, 2}, - {VPU_VIU_OFIFO, HHI_VPU_MEM_PD_REG0, 10, 2}, - {VPU_VIU_SCALE, HHI_VPU_MEM_PD_REG0, 12, 2}, - {VPU_VIU_OSD_SCALE, HHI_VPU_MEM_PD_REG0, 14, 2}, - {VPU_VIU_VDIN0, HHI_VPU_MEM_PD_REG0, 16, 2}, - {VPU_VIU_VDIN1, HHI_VPU_MEM_PD_REG0, 18, 2}, - {VPU_DI_PRE, HHI_VPU_MEM_PD_REG0, 26, 2}, - {VPU_DI_POST, HHI_VPU_MEM_PD_REG0, 28, 2}, - {VPU_SHARP, HHI_VPU_MEM_PD_REG0, 30, 2}, - {VPU_VPU_ARB, HHI_VPU_MEM_PD_REG1, 14, 2}, - {VPU_AFBC_DEC, HHI_VPU_MEM_PD_REG1, 16, 2}, - {VPU_VENCP, HHI_VPU_MEM_PD_REG1, 20, 2}, - {VPU_VENCL, HHI_VPU_MEM_PD_REG1, 22, 2}, - {VPU_VENCI, HHI_VPU_MEM_PD_REG1, 24, 2}, - {VPU_MOD_MAX, VPU_REG_END, 0, 0}, + /* vpu module, reg, val, bit, len */ + {VPU_VIU_OSD1, HHI_VPU_MEM_PD_REG0, 0x3, 0, 2}, + {VPU_VIU_OSD2, HHI_VPU_MEM_PD_REG0, 0x3, 2, 2}, + {VPU_VIU_VD1, HHI_VPU_MEM_PD_REG0, 0x3, 4, 2}, + {VPU_VIU_VD2, HHI_VPU_MEM_PD_REG0, 0x3, 6, 2}, + {VPU_VIU_CHROMA, HHI_VPU_MEM_PD_REG0, 0x3, 8, 2}, + {VPU_VIU_OFIFO, HHI_VPU_MEM_PD_REG0, 0x3, 10, 2}, + {VPU_VIU_SCALE, HHI_VPU_MEM_PD_REG0, 0x3, 12, 2}, + {VPU_VIU_OSD_SCALE, HHI_VPU_MEM_PD_REG0, 0x3, 14, 2}, + {VPU_VIU_VDIN0, HHI_VPU_MEM_PD_REG0, 0x3, 16, 2}, + {VPU_VIU_VDIN1, HHI_VPU_MEM_PD_REG0, 0x3, 18, 2}, + {VPU_DI_PRE, HHI_VPU_MEM_PD_REG0, 0x3, 26, 2}, + {VPU_DI_POST, HHI_VPU_MEM_PD_REG0, 0x3, 28, 2}, + {VPU_SHARP, HHI_VPU_MEM_PD_REG0, 0x3, 30, 2}, + {VPU_VPU_ARB, HHI_VPU_MEM_PD_REG1, 0x3, 14, 2}, + {VPU_AFBC_DEC, HHI_VPU_MEM_PD_REG1, 0x3, 16, 2}, + {VPU_VENCP, HHI_VPU_MEM_PD_REG1, 0x3, 20, 2}, + {VPU_VENCL, HHI_VPU_MEM_PD_REG1, 0x3, 22, 2}, + {VPU_VENCI, HHI_VPU_MEM_PD_REG1, 0x3, 24, 2}, + {VPU_MOD_MAX, VPU_REG_END, 0, 0, 0}, }; static struct vpu_ctrl_s vpu_mem_pd_txlx[] = { - /* vpu module, reg, bit, len */ - {VPU_VIU_OSD1, HHI_VPU_MEM_PD_REG0, 0, 2}, - {VPU_VIU_OSD2, HHI_VPU_MEM_PD_REG0, 2, 2}, - {VPU_VIU_VD1, HHI_VPU_MEM_PD_REG0, 4, 2}, - {VPU_VIU_VD2, HHI_VPU_MEM_PD_REG0, 6, 2}, - {VPU_VIU_CHROMA, HHI_VPU_MEM_PD_REG0, 8, 2}, - {VPU_VIU_OFIFO, HHI_VPU_MEM_PD_REG0, 10, 2}, - {VPU_VIU_SCALE, HHI_VPU_MEM_PD_REG0, 12, 2}, - {VPU_VIU_OSD_SCALE, HHI_VPU_MEM_PD_REG0, 14, 2}, - {VPU_VIU_VDIN0, HHI_VPU_MEM_PD_REG0, 16, 2}, - {VPU_VIU_VDIN1, HHI_VPU_MEM_PD_REG0, 18, 2}, - {VPU_VIU_SRSCL, HHI_VPU_MEM_PD_REG0, 20, 2}, - {VPU_AFBC_DEC1, HHI_VPU_MEM_PD_REG0, 22, 2}, - {VPU_DI_PRE, HHI_VPU_MEM_PD_REG0, 26, 2}, - {VPU_DI_POST, HHI_VPU_MEM_PD_REG0, 28, 2}, - {VPU_SHARP, HHI_VPU_MEM_PD_REG0, 30, 2}, - {VPU_VKSTONE, HHI_VPU_MEM_PD_REG1, 4, 2}, - {VPU_DOLBY_CORE3, HHI_VPU_MEM_PD_REG1, 6, 2}, - {VPU_DOLBY0, HHI_VPU_MEM_PD_REG1, 8, 2}, - {VPU_DOLBY1A, HHI_VPU_MEM_PD_REG1, 10, 2}, - {VPU_DOLBY1B, HHI_VPU_MEM_PD_REG1, 12, 2}, - {VPU_VPU_ARB, HHI_VPU_MEM_PD_REG1, 14, 2}, - {VPU_AFBC_DEC, HHI_VPU_MEM_PD_REG1, 16, 2}, - {VPU_OSD_AFBCD, HHI_VPU_MEM_PD_REG1, 18, 2}, - {VPU_VENCP, HHI_VPU_MEM_PD_REG1, 20, 2}, - {VPU_VENCL, HHI_VPU_MEM_PD_REG1, 22, 2}, - {VPU_VENCI, HHI_VPU_MEM_PD_REG1, 24, 2}, - {VPU_LDIM_STTS, HHI_VPU_MEM_PD_REG1, 28, 2}, - {VPU_XVYCC_LUT, HHI_VPU_MEM_PD_REG1, 30, 2}, - {VPU_VIU_WM, HHI_VPU_MEM_PD_REG2, 0, 2}, - {VPU_MOD_MAX, VPU_REG_END, 0, 0}, + /* vpu module, reg, val, bit, len */ + {VPU_VIU_OSD1, HHI_VPU_MEM_PD_REG0, 0x3, 0, 2}, + {VPU_VIU_OSD2, HHI_VPU_MEM_PD_REG0, 0x3, 2, 2}, + {VPU_VIU_VD1, HHI_VPU_MEM_PD_REG0, 0x3, 4, 2}, + {VPU_VIU_VD2, HHI_VPU_MEM_PD_REG0, 0x3, 6, 2}, + {VPU_VIU_CHROMA, HHI_VPU_MEM_PD_REG0, 0x3, 8, 2}, + {VPU_VIU_OFIFO, HHI_VPU_MEM_PD_REG0, 0x3, 10, 2}, + {VPU_VIU_SCALE, HHI_VPU_MEM_PD_REG0, 0x3, 12, 2}, + {VPU_VIU_OSD_SCALE, HHI_VPU_MEM_PD_REG0, 0x3, 14, 2}, + {VPU_VIU_VDIN0, HHI_VPU_MEM_PD_REG0, 0x3, 16, 2}, + {VPU_VIU_VDIN1, HHI_VPU_MEM_PD_REG0, 0x3, 18, 2}, + {VPU_VIU_SRSCL, HHI_VPU_MEM_PD_REG0, 0x3, 20, 2}, + {VPU_AFBC_DEC1, HHI_VPU_MEM_PD_REG0, 0x3, 22, 2}, + {VPU_DI_PRE, HHI_VPU_MEM_PD_REG0, 0x3, 26, 2}, + {VPU_DI_POST, HHI_VPU_MEM_PD_REG0, 0x3, 28, 2}, + {VPU_SHARP, HHI_VPU_MEM_PD_REG0, 0x3, 30, 2}, + {VPU_VKSTONE, HHI_VPU_MEM_PD_REG1, 0x3, 4, 2}, + {VPU_DOLBY_CORE3, HHI_VPU_MEM_PD_REG1, 0x3, 6, 2}, + {VPU_DOLBY0, HHI_VPU_MEM_PD_REG1, 0x3, 8, 2}, + {VPU_DOLBY1A, HHI_VPU_MEM_PD_REG1, 0x3, 10, 2}, + {VPU_DOLBY1B, HHI_VPU_MEM_PD_REG1, 0x3, 12, 2}, + {VPU_VPU_ARB, HHI_VPU_MEM_PD_REG1, 0x3, 14, 2}, + {VPU_AFBC_DEC, HHI_VPU_MEM_PD_REG1, 0x3, 16, 2}, + {VPU_OSD_AFBCD, HHI_VPU_MEM_PD_REG1, 0x3, 18, 2}, + {VPU_VENCP, HHI_VPU_MEM_PD_REG1, 0x3, 20, 2}, + {VPU_VENCL, HHI_VPU_MEM_PD_REG1, 0x3, 22, 2}, + {VPU_VENCI, HHI_VPU_MEM_PD_REG1, 0x3, 24, 2}, + {VPU_LDIM_STTS, HHI_VPU_MEM_PD_REG1, 0x3, 28, 2}, + {VPU_XVYCC_LUT, HHI_VPU_MEM_PD_REG1, 0x3, 30, 2}, + {VPU_VIU_WM, HHI_VPU_MEM_PD_REG2, 0x3, 0, 2}, + {VPU_MOD_MAX, VPU_REG_END, 0, 0, 0}, }; static struct vpu_ctrl_s vpu_mem_pd_axg[] = { - /* vpu module, reg, bit, len */ - {VPU_VIU_OSD1, HHI_VPU_MEM_PD_REG0, 0, 2}, - {VPU_VIU_OFIFO, HHI_VPU_MEM_PD_REG0, 2, 2}, - {VPU_VPU_ARB, HHI_VPU_MEM_PD_REG0, 4, 2}, - {VPU_VENCL, HHI_VPU_MEM_PD_REG0, 6, 2}, - {VPU_MOD_MAX, VPU_REG_END, 0, 0}, + /* vpu module, reg, val, bit, len */ + {VPU_VIU_OSD1, HHI_VPU_MEM_PD_REG0, 0x3, 0, 2}, + {VPU_VIU_OFIFO, HHI_VPU_MEM_PD_REG0, 0x3, 2, 2}, + {VPU_VPU_ARB, HHI_VPU_MEM_PD_REG0, 0x3, 4, 2}, + {VPU_VENCL, HHI_VPU_MEM_PD_REG0, 0x3, 6, 2}, + {VPU_MOD_MAX, VPU_REG_END, 0, 0, 0}, }; static struct vpu_ctrl_s vpu_mem_pd_g12a[] = { - /* vpu module, reg, bit, len */ - {VPU_VIU_OSD1, HHI_VPU_MEM_PD_REG0, 0, 2}, - {VPU_VIU_OSD2, HHI_VPU_MEM_PD_REG0, 2, 2}, - {VPU_VIU_VD1, HHI_VPU_MEM_PD_REG0, 4, 2}, - {VPU_VIU_VD2, HHI_VPU_MEM_PD_REG0, 6, 2}, - {VPU_VIU_CHROMA, HHI_VPU_MEM_PD_REG0, 8, 2}, - {VPU_VIU_OFIFO, HHI_VPU_MEM_PD_REG0, 10, 2}, - {VPU_VIU_SCALE, HHI_VPU_MEM_PD_REG0, 12, 2}, - {VPU_VIU_OSD_SCALE, HHI_VPU_MEM_PD_REG0, 14, 2}, - {VPU_VIU_VDIN0, HHI_VPU_MEM_PD_REG0, 16, 2}, - {VPU_VIU_VDIN1, HHI_VPU_MEM_PD_REG0, 18, 2}, - {VPU_VIU_SRSCL, HHI_VPU_MEM_PD_REG0, 20, 2}, - {VPU_AFBC_DEC1, HHI_VPU_MEM_PD_REG0, 22, 2}, - {VPU_VIU_DI_SCALE, HHI_VPU_MEM_PD_REG0, 24, 2}, - {VPU_DI_PRE, HHI_VPU_MEM_PD_REG0, 26, 2}, - {VPU_DI_POST, HHI_VPU_MEM_PD_REG0, 28, 2}, - {VPU_SHARP, HHI_VPU_MEM_PD_REG0, 30, 2}, - {VPU_VIU2_OSD1, HHI_VPU_MEM_PD_REG1, 0, 2}, - {VPU_VIU2_OFIFO, HHI_VPU_MEM_PD_REG1, 2, 2}, - {VPU_VKSTONE, HHI_VPU_MEM_PD_REG1, 4, 2}, - {VPU_DOLBY_CORE3, HHI_VPU_MEM_PD_REG1, 6, 2}, - {VPU_DOLBY0, HHI_VPU_MEM_PD_REG1, 8, 2}, - {VPU_DOLBY1A, HHI_VPU_MEM_PD_REG1, 10, 2}, - {VPU_DOLBY1B, HHI_VPU_MEM_PD_REG1, 12, 2}, - {VPU_VPU_ARB, HHI_VPU_MEM_PD_REG1, 14, 2}, - {VPU_AFBC_DEC, HHI_VPU_MEM_PD_REG1, 16, 2}, - {VPU_VD2_SCALE, HHI_VPU_MEM_PD_REG1, 18, 2}, - {VPU_VENCP, HHI_VPU_MEM_PD_REG1, 20, 2}, - {VPU_VENCL, HHI_VPU_MEM_PD_REG1, 22, 2}, - {VPU_VENCI, HHI_VPU_MEM_PD_REG1, 24, 2}, - {VPU_VD2_OSD2_SCALE, HHI_VPU_MEM_PD_REG1, 30, 2}, - {VPU_VIU_WM, HHI_VPU_MEM_PD_REG2, 0, 2}, - {VPU_VIU_OSD3, HHI_VPU_MEM_PD_REG2, 4, 2}, - {VPU_VIU_OSD4, HHI_VPU_MEM_PD_REG2, 6, 2}, - {VPU_MAIL_AFBCD, HHI_VPU_MEM_PD_REG2, 8, 2}, - {VPU_VD1_SCALE, HHI_VPU_MEM_PD_REG2, 10, 2}, - {VPU_OSD_BLD34, HHI_VPU_MEM_PD_REG2, 12, 2}, - {VPU_PRIME_DOLBY_RAM, HHI_VPU_MEM_PD_REG2, 14, 2}, - {VPU_VD2_OFIFO, HHI_VPU_MEM_PD_REG2, 16, 2}, - {VPU_RDMA, HHI_VPU_MEM_PD_REG2, 30, 2}, - {VPU_MOD_MAX, VPU_REG_END, 0, 0}, + /* vpu module, reg, val, bit, len */ + {VPU_VIU_OSD1, HHI_VPU_MEM_PD_REG0, 0x3, 0, 2}, + {VPU_VIU_OSD2, HHI_VPU_MEM_PD_REG0, 0x3, 2, 2}, + {VPU_VIU_VD1, HHI_VPU_MEM_PD_REG0, 0x3, 4, 2}, + {VPU_VIU_VD2, HHI_VPU_MEM_PD_REG0, 0x3, 6, 2}, + {VPU_VIU_CHROMA, HHI_VPU_MEM_PD_REG0, 0x3, 8, 2}, + {VPU_VIU_OFIFO, HHI_VPU_MEM_PD_REG0, 0x3, 10, 2}, + {VPU_VIU_SCALE, HHI_VPU_MEM_PD_REG0, 0x3, 12, 2}, + {VPU_VIU_OSD_SCALE, HHI_VPU_MEM_PD_REG0, 0x3, 14, 2}, + {VPU_VIU_VDIN0, HHI_VPU_MEM_PD_REG0, 0x3, 16, 2}, + {VPU_VIU_VDIN1, HHI_VPU_MEM_PD_REG0, 0x3, 18, 2}, + {VPU_VIU_SRSCL, HHI_VPU_MEM_PD_REG0, 0x3, 20, 2}, + {VPU_AFBC_DEC1, HHI_VPU_MEM_PD_REG0, 0x3, 22, 2}, + {VPU_VIU_DI_SCALE, HHI_VPU_MEM_PD_REG0, 0x3, 24, 2}, + {VPU_DI_PRE, HHI_VPU_MEM_PD_REG0, 0x3, 26, 2}, + {VPU_DI_POST, HHI_VPU_MEM_PD_REG0, 0x3, 28, 2}, + {VPU_SHARP, HHI_VPU_MEM_PD_REG0, 0x3, 30, 2}, + {VPU_VIU2_OSD1, HHI_VPU_MEM_PD_REG1, 0x3, 0, 2}, + {VPU_VIU2_OFIFO, HHI_VPU_MEM_PD_REG1, 0x3, 2, 2}, + {VPU_VKSTONE, HHI_VPU_MEM_PD_REG1, 0x3, 4, 2}, + {VPU_DOLBY_CORE3, HHI_VPU_MEM_PD_REG1, 0x3, 6, 2}, + {VPU_DOLBY0, HHI_VPU_MEM_PD_REG1, 0x3, 8, 2}, + {VPU_DOLBY1A, HHI_VPU_MEM_PD_REG1, 0x3, 10, 2}, + {VPU_DOLBY1B, HHI_VPU_MEM_PD_REG1, 0x3, 12, 2}, + {VPU_VPU_ARB, HHI_VPU_MEM_PD_REG1, 0x3, 14, 2}, + {VPU_AFBC_DEC, HHI_VPU_MEM_PD_REG1, 0x3, 16, 2}, + {VPU_VD2_SCALE, HHI_VPU_MEM_PD_REG1, 0x3, 18, 2}, + {VPU_VENCP, HHI_VPU_MEM_PD_REG1, 0x3, 20, 2}, + {VPU_VENCL, HHI_VPU_MEM_PD_REG1, 0x3, 22, 2}, + {VPU_VENCI, HHI_VPU_MEM_PD_REG1, 0x3, 24, 2}, + {VPU_VD2_OSD2_SCALE, HHI_VPU_MEM_PD_REG1, 0x3, 30, 2}, + {VPU_VIU_WM, HHI_VPU_MEM_PD_REG2, 0x3, 0, 2}, + {VPU_VIU_OSD3, HHI_VPU_MEM_PD_REG2, 0x3, 4, 2}, + {VPU_VIU_OSD4, HHI_VPU_MEM_PD_REG2, 0x3, 6, 2}, + {VPU_MAIL_AFBCD, HHI_VPU_MEM_PD_REG2, 0x3, 8, 2}, + {VPU_VD1_SCALE, HHI_VPU_MEM_PD_REG2, 0x3, 10, 2}, + {VPU_OSD_BLD34, HHI_VPU_MEM_PD_REG2, 0x3, 12, 2}, + {VPU_PRIME_DOLBY_RAM, HHI_VPU_MEM_PD_REG2, 0x3, 14, 2}, + {VPU_VD2_OFIFO, HHI_VPU_MEM_PD_REG2, 0x3, 16, 2}, + {VPU_RDMA, HHI_VPU_MEM_PD_REG2, 0x3, 30, 2}, + {VPU_MOD_MAX, VPU_REG_END, 0, 0, 0}, }; static struct vpu_ctrl_s vpu_mem_pd_g12b[] = { - /* vpu module, reg, bit, len */ - {VPU_VIU_OSD1, HHI_VPU_MEM_PD_REG0, 0, 2}, - {VPU_VIU_OSD2, HHI_VPU_MEM_PD_REG0, 2, 2}, - {VPU_VIU_VD1, HHI_VPU_MEM_PD_REG0, 4, 2}, - {VPU_VIU_VD2, HHI_VPU_MEM_PD_REG0, 6, 2}, - {VPU_VIU_CHROMA, HHI_VPU_MEM_PD_REG0, 8, 2}, - {VPU_VIU_OFIFO, HHI_VPU_MEM_PD_REG0, 10, 2}, - {VPU_VIU_SCALE, HHI_VPU_MEM_PD_REG0, 12, 2}, - {VPU_VIU_OSD_SCALE, HHI_VPU_MEM_PD_REG0, 14, 2}, - {VPU_VIU_VDIN0, HHI_VPU_MEM_PD_REG0, 16, 2}, - {VPU_VIU_VDIN1, HHI_VPU_MEM_PD_REG0, 18, 2}, - {VPU_VIU_SRSCL, HHI_VPU_MEM_PD_REG0, 20, 2}, - {VPU_AFBC_DEC1, HHI_VPU_MEM_PD_REG0, 22, 2}, - {VPU_VIU_DI_SCALE, HHI_VPU_MEM_PD_REG0, 24, 2}, - {VPU_DI_PRE, HHI_VPU_MEM_PD_REG0, 26, 2}, - {VPU_DI_POST, HHI_VPU_MEM_PD_REG0, 28, 2}, - {VPU_SHARP, HHI_VPU_MEM_PD_REG0, 30, 2}, - {VPU_VIU2_OSD1, HHI_VPU_MEM_PD_REG1, 0, 2}, - {VPU_VIU2_OFIFO, HHI_VPU_MEM_PD_REG1, 2, 2}, - {VPU_VKSTONE, HHI_VPU_MEM_PD_REG1, 4, 2}, - {VPU_DOLBY_CORE3, HHI_VPU_MEM_PD_REG1, 6, 2}, - {VPU_DOLBY0, HHI_VPU_MEM_PD_REG1, 8, 2}, - {VPU_DOLBY1A, HHI_VPU_MEM_PD_REG1, 10, 2}, - {VPU_DOLBY1B, HHI_VPU_MEM_PD_REG1, 12, 2}, - {VPU_VPU_ARB, HHI_VPU_MEM_PD_REG1, 14, 2}, - {VPU_AFBC_DEC, HHI_VPU_MEM_PD_REG1, 16, 2}, - {VPU_VD2_SCALE, HHI_VPU_MEM_PD_REG1, 18, 2}, - {VPU_VENCP, HHI_VPU_MEM_PD_REG1, 20, 2}, - {VPU_VENCL, HHI_VPU_MEM_PD_REG1, 22, 2}, - {VPU_VENCI, HHI_VPU_MEM_PD_REG1, 24, 2}, - {VPU_VD2_OSD2_SCALE, HHI_VPU_MEM_PD_REG1, 30, 2}, - {VPU_VIU_WM, HHI_VPU_MEM_PD_REG2, 0, 2}, - {VPU_VIU_OSD3, HHI_VPU_MEM_PD_REG2, 4, 2}, - {VPU_VIU_OSD4, HHI_VPU_MEM_PD_REG2, 6, 2}, - {VPU_MAIL_AFBCD, HHI_VPU_MEM_PD_REG2, 8, 2}, - {VPU_VD1_SCALE, HHI_VPU_MEM_PD_REG2, 10, 2}, - {VPU_OSD_BLD34, HHI_VPU_MEM_PD_REG2, 12, 2}, - {VPU_PRIME_DOLBY_RAM, HHI_VPU_MEM_PD_REG2, 14, 2}, - {VPU_VD2_OFIFO, HHI_VPU_MEM_PD_REG2, 16, 2}, - {VPU_LUT3D, HHI_VPU_MEM_PD_REG2, 20, 2}, - {VPU_VIU2_OSD_ROT, HHI_VPU_MEM_PD_REG2, 22, 2}, - {VPU_RDMA, HHI_VPU_MEM_PD_REG2, 30, 2}, - {VPU_MOD_MAX, VPU_REG_END, 0, 0}, + /* vpu module, reg, val, bit, len */ + {VPU_VIU_OSD1, HHI_VPU_MEM_PD_REG0, 0x3, 0, 2}, + {VPU_VIU_OSD2, HHI_VPU_MEM_PD_REG0, 0x3, 2, 2}, + {VPU_VIU_VD1, HHI_VPU_MEM_PD_REG0, 0x3, 4, 2}, + {VPU_VIU_VD2, HHI_VPU_MEM_PD_REG0, 0x3, 6, 2}, + {VPU_VIU_CHROMA, HHI_VPU_MEM_PD_REG0, 0x3, 8, 2}, + {VPU_VIU_OFIFO, HHI_VPU_MEM_PD_REG0, 0x3, 10, 2}, + {VPU_VIU_SCALE, HHI_VPU_MEM_PD_REG0, 0x3, 12, 2}, + {VPU_VIU_OSD_SCALE, HHI_VPU_MEM_PD_REG0, 0x3, 14, 2}, + {VPU_VIU_VDIN0, HHI_VPU_MEM_PD_REG0, 0x3, 16, 2}, + {VPU_VIU_VDIN1, HHI_VPU_MEM_PD_REG0, 0x3, 18, 2}, + {VPU_VIU_SRSCL, HHI_VPU_MEM_PD_REG0, 0x3, 20, 2}, + {VPU_AFBC_DEC1, HHI_VPU_MEM_PD_REG0, 0x3, 22, 2}, + {VPU_VIU_DI_SCALE, HHI_VPU_MEM_PD_REG0, 0x3, 24, 2}, + {VPU_DI_PRE, HHI_VPU_MEM_PD_REG0, 0x3, 26, 2}, + {VPU_DI_POST, HHI_VPU_MEM_PD_REG0, 0x3, 28, 2}, + {VPU_SHARP, HHI_VPU_MEM_PD_REG0, 0x3, 30, 2}, + {VPU_VIU2_OSD1, HHI_VPU_MEM_PD_REG1, 0x3, 0, 2}, + {VPU_VIU2_OFIFO, HHI_VPU_MEM_PD_REG1, 0x3, 2, 2}, + {VPU_VKSTONE, HHI_VPU_MEM_PD_REG1, 0x3, 4, 2}, + {VPU_DOLBY_CORE3, HHI_VPU_MEM_PD_REG1, 0x3, 6, 2}, + {VPU_DOLBY0, HHI_VPU_MEM_PD_REG1, 0x3, 8, 2}, + {VPU_DOLBY1A, HHI_VPU_MEM_PD_REG1, 0x3, 10, 2}, + {VPU_DOLBY1B, HHI_VPU_MEM_PD_REG1, 0x3, 12, 2}, + {VPU_VPU_ARB, HHI_VPU_MEM_PD_REG1, 0x3, 14, 2}, + {VPU_AFBC_DEC, HHI_VPU_MEM_PD_REG1, 0x3, 16, 2}, + {VPU_VD2_SCALE, HHI_VPU_MEM_PD_REG1, 0x3, 18, 2}, + {VPU_VENCP, HHI_VPU_MEM_PD_REG1, 0x3, 20, 2}, + {VPU_VENCL, HHI_VPU_MEM_PD_REG1, 0x3, 22, 2}, + {VPU_VENCI, HHI_VPU_MEM_PD_REG1, 0x3, 24, 2}, + {VPU_VD2_OSD2_SCALE, HHI_VPU_MEM_PD_REG1, 0x3, 30, 2}, + {VPU_VIU_WM, HHI_VPU_MEM_PD_REG2, 0x3, 0, 2}, + {VPU_VIU_OSD3, HHI_VPU_MEM_PD_REG2, 0x3, 4, 2}, + {VPU_VIU_OSD4, HHI_VPU_MEM_PD_REG2, 0x3, 6, 2}, + {VPU_MAIL_AFBCD, HHI_VPU_MEM_PD_REG2, 0x3, 8, 2}, + {VPU_VD1_SCALE, HHI_VPU_MEM_PD_REG2, 0x3, 10, 2}, + {VPU_OSD_BLD34, HHI_VPU_MEM_PD_REG2, 0x3, 12, 2}, + {VPU_PRIME_DOLBY_RAM, HHI_VPU_MEM_PD_REG2, 0x3, 14, 2}, + {VPU_VD2_OFIFO, HHI_VPU_MEM_PD_REG2, 0x3, 16, 2}, + {VPU_LUT3D, HHI_VPU_MEM_PD_REG2, 0x3, 20, 2}, + {VPU_VIU2_OSD_ROT, HHI_VPU_MEM_PD_REG2, 0x3, 22, 2}, + {VPU_RDMA, HHI_VPU_MEM_PD_REG2, 0x3, 30, 2}, + {VPU_MOD_MAX, VPU_REG_END, 0, 0, 0}, +}; + +static struct vpu_ctrl_s vpu_mem_pd_tl1[] = { + /* vpu module, reg, val, bit, len */ + {VPU_VIU_OSD1, HHI_VPU_MEM_PD_REG0, 0x3, 0, 2}, + {VPU_VIU_OSD2, HHI_VPU_MEM_PD_REG0, 0x3, 2, 2}, + {VPU_VIU_VD1, HHI_VPU_MEM_PD_REG0, 0x3, 4, 2}, + {VPU_VIU_VD2, HHI_VPU_MEM_PD_REG0, 0x3, 6, 2}, + {VPU_VIU_CHROMA, HHI_VPU_MEM_PD_REG0, 0x3, 8, 2}, + {VPU_VIU_OFIFO, HHI_VPU_MEM_PD_REG0, 0x3, 10, 2}, + {VPU_VIU_SCALE, HHI_VPU_MEM_PD_REG0, 0x3, 12, 2}, + {VPU_VIU_OSD_SCALE, HHI_VPU_MEM_PD_REG0, 0x3, 14, 2}, + {VPU_VIU_VDIN0, HHI_VPU_MEM_PD_REG0, 0x3, 16, 2}, + {VPU_VIU_VDIN1, HHI_VPU_MEM_PD_REG0, 0x3, 18, 2}, + {VPU_VIU_SRSCL, HHI_VPU_MEM_PD_REG0, 0x3, 20, 2}, + {VPU_AFBC_DEC1, HHI_VPU_MEM_PD_REG0, 0x3, 22, 2}, + {VPU_VIU_DI_SCALE, HHI_VPU_MEM_PD_REG0, 0x3, 24, 2}, + {VPU_DI_PRE, HHI_VPU_MEM_PD_REG0, 0x3, 26, 2}, + {VPU_DI_POST, HHI_VPU_MEM_PD_REG0, 0x3, 28, 2}, + {VPU_SHARP, HHI_VPU_MEM_PD_REG0, 0x3, 30, 2}, + {VPU_VIU2_OSD1, HHI_VPU_MEM_PD_REG1, 0x3, 0, 2}, + {VPU_VIU2_OFIFO, HHI_VPU_MEM_PD_REG1, 0x3, 2, 2}, + {VPU_VKSTONE, HHI_VPU_MEM_PD_REG1, 0x3, 4, 2}, + {VPU_DOLBY_CORE3, HHI_VPU_MEM_PD_REG1, 0x3, 6, 2}, + {VPU_DOLBY0, HHI_VPU_MEM_PD_REG1, 0x3, 8, 2}, + {VPU_DOLBY1A, HHI_VPU_MEM_PD_REG1, 0x3, 10, 2}, + {VPU_DOLBY1B, HHI_VPU_MEM_PD_REG1, 0x3, 12, 2}, + {VPU_VPU_ARB, HHI_VPU_MEM_PD_REG1, 0x3, 14, 2}, + {VPU_AFBC_DEC, HHI_VPU_MEM_PD_REG1, 0x3, 16, 2}, + {VPU_VD2_SCALE, HHI_VPU_MEM_PD_REG1, 0x3, 18, 2}, + {VPU_VENCP, HHI_VPU_MEM_PD_REG1, 0x3, 20, 2}, + {VPU_VENCL, HHI_VPU_MEM_PD_REG1, 0x3, 22, 2}, + {VPU_VENCI, HHI_VPU_MEM_PD_REG1, 0x3, 24, 2}, + {VPU_LS_STTS, HHI_VPU_MEM_PD_REG1, 0x3, 26, 2}, + {VPU_LDIM_STTS, HHI_VPU_MEM_PD_REG1, 0x3, 28, 2}, + {VPU_VD2_OSD2_SCALE, HHI_VPU_MEM_PD_REG1, 0x3, 30, 2}, + {VPU_VIU_WM, HHI_VPU_MEM_PD_REG2, 0x3, 0, 2}, + {VPU_TCON, HHI_VPU_MEM_PD_REG2, 0x3, 2, 2}, + {VPU_VIU_OSD3, HHI_VPU_MEM_PD_REG2, 0x3, 4, 2}, + {VPU_VIU_OSD4, HHI_VPU_MEM_PD_REG2, 0x3, 6, 2}, + {VPU_MAIL_AFBCD, HHI_VPU_MEM_PD_REG2, 0x3, 8, 2}, + {VPU_VD1_SCALE, HHI_VPU_MEM_PD_REG2, 0x3, 10, 2}, + {VPU_OSD_BLD34, HHI_VPU_MEM_PD_REG2, 0x3, 12, 2}, + {VPU_PRIME_DOLBY_RAM, HHI_VPU_MEM_PD_REG2, 0x3, 14, 2}, + {VPU_VD2_OFIFO, HHI_VPU_MEM_PD_REG2, 0x3, 16, 2}, + {VPU_DS, HHI_VPU_MEM_PD_REG2, 0x3, 18, 2}, + {VPU_LUT3D, HHI_VPU_MEM_PD_REG2, 0x3, 20, 2}, + {VPU_VIU2_OSD_ROT, HHI_VPU_MEM_PD_REG2, 0x3, 22, 2}, + {VPU_VI_DIPRE, HHI_VPU_MEM_PD_REG2, 0xf, 24, 4}, + {VPU_RDMA, HHI_VPU_MEM_PD_REG2, 0x3, 30, 2}, + {VPU_TCON, HHI_VPU_MEM_PD_REG3, 0x3, 0, 16}, + {VPU_TCON, HHI_VPU_MEM_PD_REG3, 0x3, 16, 16}, + {VPU_AXI_WR1, HHI_VPU_MEM_PD_REG4, 0x3, 0, 2}, + {VPU_AXI_WR0, HHI_VPU_MEM_PD_REG4, 0x3, 2, 2}, + {VPU_AFBCE, HHI_VPU_MEM_PD_REG4, 0x3, 4, 2}, + {VPU_MOD_MAX, VPU_REG_END, 0, 0, 0}, }; /* ******************************************************* */ /* VPU clock gate table */ /* ******************************************************* */ static struct vpu_ctrl_s vpu_clk_gate_gxb[] = { - /* vpu module, reg, bit, len */ - {VPU_VPU_TOP, VPU_CLK_GATE, 1, 1}, /* vpu_system_clk */ - {VPU_VPU_CLKB, VPU_CLK_GATE, 16, 1}, - {VPU_RDMA, VPU_CLK_GATE, 15, 1}, /* rdma_clk */ - {VPU_VLOCK, VPU_CLK_GATE, 14, 1}, - {VPU_MISC, VPU_CLK_GATE, 6, 1}, /* hs,vs interrupt*/ - {VPU_VENCP, VPU_CLK_GATE, 3, 1}, - {VPU_VENCP, VPU_CLK_GATE, 0, 1}, - {VPU_VENCL, VPU_CLK_GATE, 4, 2}, - {VPU_VENCI, VPU_CLK_GATE, 10, 2}, - {VPU_VIU_VDIN0, VDIN0_COM_GCLK_CTRL, 24, 6}, - {VPU_VIU_VDIN0, VDIN0_COM_GCLK_CTRL, 4, 18}, - {VPU_VIU_VDIN0, VDIN0_COM_GCLK_CTRL, 1, 1}, - {VPU_VIU_VDIN0, VDIN0_COM_GCLK_CTRL2, 0, 4}, - {VPU_VIU_VDIN1, VDIN1_COM_GCLK_CTRL, 24, 6}, - {VPU_VIU_VDIN1, VDIN1_COM_GCLK_CTRL, 4, 18}, - {VPU_VIU_VDIN1, VDIN1_COM_GCLK_CTRL, 1, 1}, - {VPU_VIU_VDIN1, VDIN1_COM_GCLK_CTRL2, 0, 4}, - {VPU_DI, DI_CLKG_CTRL, 26, 3}, - {VPU_DI, DI_CLKG_CTRL, 24, 1}, - {VPU_DI, DI_CLKG_CTRL, 17, 4}, - {VPU_DI, DI_CLKG_CTRL, 0, 2}, - {VPU_VPP, VPP_GCLK_CTRL0, 16, 16}, - {VPU_VPP, VPP_GCLK_CTRL0, 6, 8}, - {VPU_VPP, VPP_GCLK_CTRL0, 2, 2}, - {VPU_VPP, VPP_GCLK_CTRL1, 0, 12}, - {VPU_VPP, VPP_SC_GCLK_CTRL, 18, 8}, - {VPU_VPP, VPP_SC_GCLK_CTRL, 2, 10}, - {VPU_VPP, VPP_XVYCC_GCLK_CTRL, 0, 18}, - {VPU_MAX, VPU_REG_END, 0, 0}, + /* vpu module, reg, val, bit, len */ + {VPU_VPU_TOP, VPU_CLK_GATE, 1, 1, 1}, /*vpu_sys_clk*/ + {VPU_VPU_CLKB, VPU_CLK_GATE, 1, 16, 1}, + {VPU_RDMA, VPU_CLK_GATE, 1, 15, 1}, /*rdma_clk*/ + {VPU_VLOCK, VPU_CLK_GATE, 1, 14, 1}, + {VPU_MISC, VPU_CLK_GATE, 1, 6, 1}, /*hs,vs intr*/ + {VPU_VENCP, VPU_CLK_GATE, 1, 3, 1}, + {VPU_VENCP, VPU_CLK_GATE, 1, 0, 1}, + {VPU_VENCL, VPU_CLK_GATE, 1, 4, 2}, + {VPU_VENCI, VPU_CLK_GATE, 1, 10, 2}, + {VPU_VIU_VDIN0, VDIN0_COM_GCLK_CTRL, 1, 24, 6}, + {VPU_VIU_VDIN0, VDIN0_COM_GCLK_CTRL, 1, 4, 18}, + {VPU_VIU_VDIN0, VDIN0_COM_GCLK_CTRL, 1, 1, 1}, + {VPU_VIU_VDIN0, VDIN0_COM_GCLK_CTRL2, 1, 0, 4}, + {VPU_VIU_VDIN1, VDIN1_COM_GCLK_CTRL, 1, 24, 6}, + {VPU_VIU_VDIN1, VDIN1_COM_GCLK_CTRL, 1, 4, 18}, + {VPU_VIU_VDIN1, VDIN1_COM_GCLK_CTRL, 1, 1, 1}, + {VPU_VIU_VDIN1, VDIN1_COM_GCLK_CTRL2, 1, 0, 4}, + {VPU_DI, DI_CLKG_CTRL, 1, 26, 3}, + {VPU_DI, DI_CLKG_CTRL, 1, 24, 1}, + {VPU_DI, DI_CLKG_CTRL, 1, 17, 4}, + {VPU_DI, DI_CLKG_CTRL, 1, 0, 2}, + {VPU_VPP, VPP_GCLK_CTRL0, 1, 16, 16}, + {VPU_VPP, VPP_GCLK_CTRL0, 1, 6, 8}, + {VPU_VPP, VPP_GCLK_CTRL0, 1, 2, 2}, + {VPU_VPP, VPP_GCLK_CTRL1, 1, 0, 12}, + {VPU_VPP, VPP_SC_GCLK_CTRL, 1, 18, 8}, + {VPU_VPP, VPP_SC_GCLK_CTRL, 1, 2, 10}, + {VPU_VPP, VPP_XVYCC_GCLK_CTRL, 1, 0, 18}, + {VPU_MAX, VPU_REG_END, 0, 0, 0}, }; static struct vpu_ctrl_s vpu_clk_gate_gxl[] = { - /* vpu module, reg, bit, len */ - {VPU_VPU_TOP, VPU_CLK_GATE, 1, 1}, /* vpu_system_clk */ - {VPU_VPU_CLKB, VPU_CLK_GATE, 16, 2}, - {VPU_RDMA, VPU_CLK_GATE, 15, 1}, /* rdma_clk */ - {VPU_VLOCK, VPU_CLK_GATE, 14, 1}, - {VPU_MISC, VPU_CLK_GATE, 6, 1}, /* hs,vs interrupt*/ - {VPU_VENCP, VPU_CLK_GATE, 3, 1}, - {VPU_VENCP, VPU_CLK_GATE, 0, 1}, - {VPU_VENCL, VPU_CLK_GATE, 4, 2}, - {VPU_VENCI, VPU_CLK_GATE, 10, 2}, - {VPU_VIU_VDIN0, VDIN0_COM_GCLK_CTRL, 24, 6}, - {VPU_VIU_VDIN0, VDIN0_COM_GCLK_CTRL, 4, 18}, - {VPU_VIU_VDIN0, VDIN0_COM_GCLK_CTRL, 1, 1}, - {VPU_VIU_VDIN0, VDIN0_COM_GCLK_CTRL2, 0, 4}, - {VPU_VIU_VDIN1, VDIN1_COM_GCLK_CTRL, 24, 6}, - {VPU_VIU_VDIN1, VDIN1_COM_GCLK_CTRL, 4, 18}, - {VPU_VIU_VDIN1, VDIN1_COM_GCLK_CTRL, 1, 1}, - {VPU_VIU_VDIN1, VDIN1_COM_GCLK_CTRL2, 0, 4}, - {VPU_DI, DI_CLKG_CTRL, 26, 5}, - {VPU_DI, DI_CLKG_CTRL, 24, 1}, - {VPU_DI, DI_CLKG_CTRL, 17, 5}, - {VPU_DI, DI_CLKG_CTRL, 0, 2}, - {VPU_VPP, VPP_GCLK_CTRL0, 2, 30}, - {VPU_VPP, VPP_GCLK_CTRL1, 0, 12}, - {VPU_VPP, VPP_SC_GCLK_CTRL, 18, 8}, - {VPU_VPP, VPP_SC_GCLK_CTRL, 2, 10}, - {VPU_VPP, VPP_XVYCC_GCLK_CTRL, 0, 18}, - {VPU_MAX, VPU_REG_END, 0, 0}, + /* vpu module, reg, val, bit, len */ + {VPU_VPU_TOP, VPU_CLK_GATE, 1, 1, 1}, /*vpu_sys_clk*/ + {VPU_VPU_CLKB, VPU_CLK_GATE, 1, 16, 2}, + {VPU_RDMA, VPU_CLK_GATE, 1, 15, 1}, /*rdma_clk*/ + {VPU_VLOCK, VPU_CLK_GATE, 1, 14, 1}, + {VPU_MISC, VPU_CLK_GATE, 1, 6, 1}, /*hs,vs intr*/ + {VPU_VENCP, VPU_CLK_GATE, 1, 3, 1}, + {VPU_VENCP, VPU_CLK_GATE, 1, 0, 1}, + {VPU_VENCL, VPU_CLK_GATE, 1, 4, 2}, + {VPU_VENCI, VPU_CLK_GATE, 1, 10, 2}, + {VPU_VIU_VDIN0, VDIN0_COM_GCLK_CTRL, 1, 24, 6}, + {VPU_VIU_VDIN0, VDIN0_COM_GCLK_CTRL, 1, 4, 18}, + {VPU_VIU_VDIN0, VDIN0_COM_GCLK_CTRL, 1, 1, 1}, + {VPU_VIU_VDIN0, VDIN0_COM_GCLK_CTRL2, 1, 0, 4}, + {VPU_VIU_VDIN1, VDIN1_COM_GCLK_CTRL, 1, 24, 6}, + {VPU_VIU_VDIN1, VDIN1_COM_GCLK_CTRL, 1, 4, 18}, + {VPU_VIU_VDIN1, VDIN1_COM_GCLK_CTRL, 1, 1, 1}, + {VPU_VIU_VDIN1, VDIN1_COM_GCLK_CTRL2, 1, 0, 4}, + {VPU_DI, DI_CLKG_CTRL, 1, 26, 5}, + {VPU_DI, DI_CLKG_CTRL, 1, 24, 1}, + {VPU_DI, DI_CLKG_CTRL, 1, 17, 5}, + {VPU_DI, DI_CLKG_CTRL, 1, 0, 2}, + {VPU_VPP, VPP_GCLK_CTRL0, 1, 2, 30}, + {VPU_VPP, VPP_GCLK_CTRL1, 1, 0, 12}, + {VPU_VPP, VPP_SC_GCLK_CTRL, 1, 18, 8}, + {VPU_VPP, VPP_SC_GCLK_CTRL, 1, 2, 10}, + {VPU_VPP, VPP_XVYCC_GCLK_CTRL, 1, 0, 18}, + {VPU_MAX, VPU_REG_END, 0, 0, 0}, }; static struct vpu_ctrl_s vpu_clk_gate_txl[] = { - /* vpu module, reg, bit, len */ - {VPU_VPU_TOP, VPU_CLK_GATE, 1, 1}, /* vpu_system_clk */ - {VPU_VPU_CLKB, VPU_CLK_GATE, 16, 1}, - {VPU_RDMA, VPU_CLK_GATE, 15, 1}, /* rdma_clk */ - {VPU_VLOCK, VPU_CLK_GATE, 14, 1}, - {VPU_MISC, VPU_CLK_GATE, 6, 1}, /* hs,vs interrupt*/ - {VPU_VENCP, VPU_CLK_GATE, 3, 1}, - {VPU_VENCP, VPU_CLK_GATE, 0, 1}, - {VPU_VENCL, VPU_CLK_GATE, 4, 2}, - {VPU_VENCI, VPU_CLK_GATE, 10, 2}, - {VPU_VIU_VDIN0, VDIN0_COM_GCLK_CTRL, 24, 6}, - {VPU_VIU_VDIN0, VDIN0_COM_GCLK_CTRL, 4, 18}, - {VPU_VIU_VDIN0, VDIN0_COM_GCLK_CTRL, 1, 1}, - {VPU_VIU_VDIN0, VDIN0_COM_GCLK_CTRL2, 0, 4}, - {VPU_VIU_VDIN1, VDIN1_COM_GCLK_CTRL, 24, 6}, - {VPU_VIU_VDIN1, VDIN1_COM_GCLK_CTRL, 4, 18}, - {VPU_VIU_VDIN1, VDIN1_COM_GCLK_CTRL, 1, 1}, - {VPU_VIU_VDIN1, VDIN1_COM_GCLK_CTRL2, 0, 4}, - {VPU_DI, DI_CLKG_CTRL, 26, 5}, - {VPU_DI, DI_CLKG_CTRL, 24, 1}, - {VPU_DI, DI_CLKG_CTRL, 17, 5}, - {VPU_DI, DI_CLKG_CTRL, 0, 2}, - {VPU_VPP, VPP_GCLK_CTRL0, 2, 30}, - {VPU_VPP, VPP_GCLK_CTRL1, 0, 12}, - {VPU_VPP, VPP_SC_GCLK_CTRL, 18, 8}, - {VPU_VPP, VPP_SC_GCLK_CTRL, 2, 10}, - {VPU_VPP, VPP_XVYCC_GCLK_CTRL, 0, 18}, - {VPU_MAX, VPU_REG_END, 0, 0}, + /* vpu module, reg, val, bit, len */ + {VPU_VPU_TOP, VPU_CLK_GATE, 1, 1, 1}, /*vpu_sys_clk*/ + {VPU_VPU_CLKB, VPU_CLK_GATE, 1, 16, 1}, + {VPU_RDMA, VPU_CLK_GATE, 1, 15, 1}, /*rdma_clk*/ + {VPU_VLOCK, VPU_CLK_GATE, 1, 14, 1}, + {VPU_MISC, VPU_CLK_GATE, 1, 6, 1}, /*hs,vs intr*/ + {VPU_VENCP, VPU_CLK_GATE, 1, 3, 1}, + {VPU_VENCP, VPU_CLK_GATE, 1, 0, 1}, + {VPU_VENCL, VPU_CLK_GATE, 1, 4, 2}, + {VPU_VENCI, VPU_CLK_GATE, 1, 10, 2}, + {VPU_VIU_VDIN0, VDIN0_COM_GCLK_CTRL, 1, 24, 6}, + {VPU_VIU_VDIN0, VDIN0_COM_GCLK_CTRL, 1, 4, 18}, + {VPU_VIU_VDIN0, VDIN0_COM_GCLK_CTRL, 1, 1, 1}, + {VPU_VIU_VDIN0, VDIN0_COM_GCLK_CTRL2, 1, 0, 4}, + {VPU_VIU_VDIN1, VDIN1_COM_GCLK_CTRL, 1, 24, 6}, + {VPU_VIU_VDIN1, VDIN1_COM_GCLK_CTRL, 1, 4, 18}, + {VPU_VIU_VDIN1, VDIN1_COM_GCLK_CTRL, 1, 1, 1}, + {VPU_VIU_VDIN1, VDIN1_COM_GCLK_CTRL2, 1, 0, 4}, + {VPU_DI, DI_CLKG_CTRL, 1, 26, 5}, + {VPU_DI, DI_CLKG_CTRL, 1, 24, 1}, + {VPU_DI, DI_CLKG_CTRL, 1, 17, 5}, + {VPU_DI, DI_CLKG_CTRL, 1, 0, 2}, + {VPU_VPP, VPP_GCLK_CTRL0, 1, 2, 30}, + {VPU_VPP, VPP_GCLK_CTRL1, 1, 0, 12}, + {VPU_VPP, VPP_SC_GCLK_CTRL, 1, 18, 8}, + {VPU_VPP, VPP_SC_GCLK_CTRL, 1, 2, 10}, + {VPU_VPP, VPP_XVYCC_GCLK_CTRL, 1, 0, 18}, + {VPU_MAX, VPU_REG_END, 0, 0, 0}, }; static struct vpu_ctrl_s vpu_clk_gate_txlx[] = { - /* vpu module, reg, bit, len */ - {VPU_VPU_TOP, VPU_CLK_GATE, 1, 1}, /* vpu_system_clk */ - {VPU_VPU_CLKB, VPU_CLK_GATE, 16, 1}, - {VPU_RDMA, VPU_CLK_GATE, 15, 1}, /* rdma_clk */ - {VPU_VLOCK, VPU_CLK_GATE, 14, 1}, - {VPU_MISC, VPU_CLK_GATE, 6, 1}, /* hs,vs interrupt*/ - {VPU_VENCP, VPU_CLK_GATE, 3, 1}, - {VPU_VENCP, VPU_CLK_GATE, 0, 1}, - {VPU_VENCL, VPU_CLK_GATE, 4, 2}, - {VPU_VENCI, VPU_CLK_GATE, 10, 2}, - {VPU_VIU_VDIN0, VDIN0_COM_GCLK_CTRL, 24, 6}, - {VPU_VIU_VDIN0, VDIN0_COM_GCLK_CTRL, 4, 18}, - {VPU_VIU_VDIN0, VDIN0_COM_GCLK_CTRL, 1, 1}, - {VPU_VIU_VDIN0, VDIN0_COM_GCLK_CTRL2, 0, 4}, - {VPU_VIU_VDIN1, VDIN1_COM_GCLK_CTRL, 24, 6}, - {VPU_VIU_VDIN1, VDIN1_COM_GCLK_CTRL, 4, 18}, - {VPU_VIU_VDIN1, VDIN1_COM_GCLK_CTRL, 1, 1}, - {VPU_VIU_VDIN1, VDIN1_COM_GCLK_CTRL2, 0, 4}, - {VPU_VPP, VPP_GCLK_CTRL0, 2, 30}, - {VPU_VPP, VPP_GCLK_CTRL1, 0, 12}, - {VPU_VPP, VPP_SC_GCLK_CTRL, 18, 8}, - {VPU_VPP, VPP_SC_GCLK_CTRL, 2, 10}, - {VPU_VPP, VPP_XVYCC_GCLK_CTRL, 0, 18}, - {VPU_MAX, VPU_REG_END, 0, 0}, + /* vpu module, reg, val, bit, len */ + {VPU_VPU_TOP, VPU_CLK_GATE, 1, 1, 1}, /*vpu_sys_clk*/ + {VPU_VPU_CLKB, VPU_CLK_GATE, 1, 16, 1}, + {VPU_RDMA, VPU_CLK_GATE, 1, 15, 1}, /*rdma_clk*/ + {VPU_VLOCK, VPU_CLK_GATE, 1, 14, 1}, + {VPU_MISC, VPU_CLK_GATE, 1, 6, 1}, /*hs,vs intr*/ + {VPU_VENCP, VPU_CLK_GATE, 1, 3, 1}, + {VPU_VENCP, VPU_CLK_GATE, 1, 0, 1}, + {VPU_VENCL, VPU_CLK_GATE, 1, 4, 2}, + {VPU_VENCI, VPU_CLK_GATE, 1, 10, 2}, + {VPU_VIU_VDIN0, VDIN0_COM_GCLK_CTRL, 1, 24, 6}, + {VPU_VIU_VDIN0, VDIN0_COM_GCLK_CTRL, 1, 4, 18}, + {VPU_VIU_VDIN0, VDIN0_COM_GCLK_CTRL, 1, 1, 1}, + {VPU_VIU_VDIN0, VDIN0_COM_GCLK_CTRL2, 1, 0, 4}, + {VPU_VIU_VDIN1, VDIN1_COM_GCLK_CTRL, 1, 24, 6}, + {VPU_VIU_VDIN1, VDIN1_COM_GCLK_CTRL, 1, 4, 18}, + {VPU_VIU_VDIN1, VDIN1_COM_GCLK_CTRL, 1, 1, 1}, + {VPU_VIU_VDIN1, VDIN1_COM_GCLK_CTRL2, 1, 0, 4}, + {VPU_VPP, VPP_GCLK_CTRL0, 1, 2, 30}, + {VPU_VPP, VPP_GCLK_CTRL1, 1, 0, 12}, + {VPU_VPP, VPP_SC_GCLK_CTRL, 1, 18, 8}, + {VPU_VPP, VPP_SC_GCLK_CTRL, 1, 2, 10}, + {VPU_VPP, VPP_XVYCC_GCLK_CTRL, 1, 0, 18}, + {VPU_MAX, VPU_REG_END, 0, 0, 0}, }; static struct vpu_ctrl_s vpu_clk_gate_axg[] = { - /* vpu module, reg, bit, len */ - {VPU_VPU_TOP, VPU_CLK_GATE, 1, 1}, - {VPU_VLOCK, VPU_CLK_GATE, 14, 1}, - {VPU_MISC, VPU_CLK_GATE, 6, 1}, - {VPU_VENCL, VPU_CLK_GATE, 4, 2}, - {VPU_VPP, VPP_GCLK_CTRL0, 16, 16}, - {VPU_VPP, VPP_GCLK_CTRL0, 6, 8}, - {VPU_VPP, VPP_GCLK_CTRL0, 2, 2}, - {VPU_VPP, VPP_GCLK_CTRL1, 0, 12}, - {VPU_VPP, VPP_SC_GCLK_CTRL, 18, 8}, - {VPU_VPP, VPP_SC_GCLK_CTRL, 2, 10}, - {VPU_VPP, VPP_XVYCC_GCLK_CTRL, 0, 18}, - {VPU_MAX, VPU_REG_END, 0, 0}, + /* vpu module, reg, val, bit, len */ + {VPU_VPU_TOP, VPU_CLK_GATE, 1, 1, 1}, + {VPU_VLOCK, VPU_CLK_GATE, 1, 14, 1}, + {VPU_MISC, VPU_CLK_GATE, 1, 6, 1}, + {VPU_VENCL, VPU_CLK_GATE, 1, 4, 2}, + {VPU_VPP, VPP_GCLK_CTRL0, 1, 16, 16}, + {VPU_VPP, VPP_GCLK_CTRL0, 1, 6, 8}, + {VPU_VPP, VPP_GCLK_CTRL0, 1, 2, 2}, + {VPU_VPP, VPP_GCLK_CTRL1, 1, 0, 12}, + {VPU_VPP, VPP_SC_GCLK_CTRL, 1, 18, 8}, + {VPU_VPP, VPP_SC_GCLK_CTRL, 1, 2, 10}, + {VPU_VPP, VPP_XVYCC_GCLK_CTRL, 1, 0, 18}, + {VPU_MAX, VPU_REG_END, 0, 0, 0}, }; static struct vpu_ctrl_s vpu_clk_gate_g12a[] = { - /* vpu module, reg, bit, len */ - {VPU_VPU_TOP, VPU_CLK_GATE, 1, 1}, /* vpu_system_clk */ - {VPU_VPU_CLKB, VPU_CLK_GATE, 18, 1}, - {VPU_CLK_B_REG_LATCH, VPU_CLK_GATE, 17, 1}, - {VPU_CLK_VIB, VPU_CLK_GATE, 16, 1}, - {VPU_RDMA, VPU_CLK_GATE, 15, 1}, /* rdma_clk */ - {VPU_VLOCK, VPU_CLK_GATE, 14, 1}, - {VPU_MISC, VPU_CLK_GATE, 6, 1}, /* hs,vs interrupt*/ - {VPU_VENCP, VPU_CLK_GATE, 3, 1}, - {VPU_VENCP, VPU_CLK_GATE, 0, 1}, - {VPU_VENCL, VPU_CLK_GATE, 4, 2}, - {VPU_VENCI, VPU_CLK_GATE, 10, 2}, - {VPU_VIU_VDIN0, VDIN0_COM_GCLK_CTRL, 24, 6}, - {VPU_VIU_VDIN0, VDIN0_COM_GCLK_CTRL, 4, 18}, - {VPU_VIU_VDIN0, VDIN0_COM_GCLK_CTRL, 1, 1}, - {VPU_VIU_VDIN0, VDIN0_COM_GCLK_CTRL2, 0, 4}, - {VPU_VIU_VDIN1, VDIN1_COM_GCLK_CTRL, 24, 6}, - {VPU_VIU_VDIN1, VDIN1_COM_GCLK_CTRL, 4, 18}, - {VPU_VIU_VDIN1, VDIN1_COM_GCLK_CTRL, 1, 1}, - {VPU_VIU_VDIN1, VDIN1_COM_GCLK_CTRL2, 0, 4}, - {VPU_DI, DI_CLKG_CTRL, 26, 5}, - {VPU_DI, DI_CLKG_CTRL, 24, 1}, - {VPU_DI, DI_CLKG_CTRL, 17, 5}, - {VPU_DI, DI_CLKG_CTRL, 0, 2}, - {VPU_VPP, VPP_GCLK_CTRL0, 2, 30}, - {VPU_VPP, VPP_GCLK_CTRL1, 0, 12}, - {VPU_VPP, VPP_SC_GCLK_CTRL, 18, 8}, - {VPU_VPP, VPP_SC_GCLK_CTRL, 2, 10}, - {VPU_VPP, VPP_XVYCC_GCLK_CTRL, 0, 18}, - {VPU_MAX, VPU_REG_END, 0, 0}, + /* vpu module, reg, val, bit, len */ + {VPU_VPU_TOP, VPU_CLK_GATE, 1, 1, 1}, /*vpu_sys_clk*/ + {VPU_VPU_CLKB, VPU_CLK_GATE, 1, 18, 1}, + {VPU_CLK_B_REG_LATCH, VPU_CLK_GATE, 1, 17, 1}, + {VPU_CLK_VIB, VPU_CLK_GATE, 1, 16, 1}, + {VPU_RDMA, VPU_CLK_GATE, 1, 15, 1}, /*rdma_clk*/ + {VPU_VLOCK, VPU_CLK_GATE, 1, 14, 1}, + {VPU_MISC, VPU_CLK_GATE, 1, 6, 1}, /*hs,vs intr*/ + {VPU_VENCP, VPU_CLK_GATE, 1, 3, 1}, + {VPU_VENCP, VPU_CLK_GATE, 1, 0, 1}, + {VPU_VENCL, VPU_CLK_GATE, 1, 4, 2}, + {VPU_VENCI, VPU_CLK_GATE, 1, 10, 2}, + {VPU_VIU_VDIN0, VDIN0_COM_GCLK_CTRL, 1, 24, 6}, + {VPU_VIU_VDIN0, VDIN0_COM_GCLK_CTRL, 1, 4, 18}, + {VPU_VIU_VDIN0, VDIN0_COM_GCLK_CTRL, 1, 1, 1}, + {VPU_VIU_VDIN0, VDIN0_COM_GCLK_CTRL2, 1, 0, 4}, + {VPU_VIU_VDIN1, VDIN1_COM_GCLK_CTRL, 1, 24, 6}, + {VPU_VIU_VDIN1, VDIN1_COM_GCLK_CTRL, 1, 4, 18}, + {VPU_VIU_VDIN1, VDIN1_COM_GCLK_CTRL, 1, 1, 1}, + {VPU_VIU_VDIN1, VDIN1_COM_GCLK_CTRL2, 1, 0, 4}, + {VPU_DI, DI_CLKG_CTRL, 1, 26, 5}, + {VPU_DI, DI_CLKG_CTRL, 1, 24, 1}, + {VPU_DI, DI_CLKG_CTRL, 1, 17, 5}, + {VPU_DI, DI_CLKG_CTRL, 1, 0, 2}, + {VPU_VPP, VPP_GCLK_CTRL0, 1, 2, 30}, + {VPU_VPP, VPP_GCLK_CTRL1, 1, 0, 12}, + {VPU_VPP, VPP_SC_GCLK_CTRL, 1, 18, 8}, + {VPU_VPP, VPP_SC_GCLK_CTRL, 1, 2, 10}, + {VPU_VPP, VPP_XVYCC_GCLK_CTRL, 1, 0, 18}, + {VPU_MAX, VPU_REG_END, 0, 0, 0}, +}; + +/* ******************************************************* */ +/* VPU module init table */ +/* ******************************************************* */ +static struct vpu_ctrl_s vpu_module_init_gxm[] = { + /* 0, reg, val, bit, len */ + {0, DOLBY_CORE1_CLKGATE_CTRL, 0x55555555, 0, 32}, + {0, DOLBY_CORE2A_CLKGATE_CTRL, 0x55555555, 0, 32}, + {0, DOLBY_CORE3_CLKGATE_CTRL, 0x55555555, 0, 32}, + {0, VPU_REG_END, 0, 0, 0}, +}; + +static struct vpu_ctrl_s vpu_module_init_txlx[] = { + /* 0, reg, val, bit, len */ + {0, DOLBY_TV_CLKGATE_CTRL, 1, 10, 2}, + {0, DOLBY_TV_CLKGATE_CTRL, 1, 2, 2}, + {0, DOLBY_TV_CLKGATE_CTRL, 1, 4, 2}, + {0, DOLBY_CORE2A_CLKGATE_CTRL, 1, 10, 2}, + {0, DOLBY_CORE2A_CLKGATE_CTRL, 1, 2, 2}, + {0, DOLBY_CORE2A_CLKGATE_CTRL, 1, 4, 2}, + {0, DOLBY_CORE3_CLKGATE_CTRL, 0, 1, 1}, + {0, DOLBY_CORE3_CLKGATE_CTRL, 1, 2, 2}, + {0, VPU_REG_END, 0, 0, 0}, +}; + +/* ******************************************************* */ +/* VPU reset table */ +/* ******************************************************* */ +static struct vpu_reset_s vpu_reset_gx[] = { + /* reg, mask */ + {RESET0_LEVEL, ((1<<5) | (1<<10) | (1<<19) | (1<<13))}, + {RESET1_LEVEL, (1<<5)}, + {RESET2_LEVEL, (1<<15)}, + {RESET4_LEVEL, ((1<<6) | (1<<7) | (1<<13) | (1<<5) | + (1<<9) | (1<<4) | (1<<12))}, + {RESET7_LEVEL, (1<<7)}, + {VPU_REG_END, 0}, +}; + +static struct vpu_reset_s vpu_reset_txlx[] = { + /* reg, mask */ + {RESET0_LEVEL_TXLX, ((1<<5) | (1<<10) | (1<<19) | (1<<13))}, + {RESET1_LEVEL_TXLX, (1<<5)}, + {RESET2_LEVEL_TXLX, (1<<15)}, + {RESET3_LEVEL_TXLX, ((1<<6) | (1<<7) | (1<<13) | (1<<5) | + (1<<9) | (1<<4) | (1<<12))}, + {RESET7_LEVEL_TXLX, (1<<7)}, + {VPU_REG_END, 0}, +}; + +static struct vpu_reset_s vpu_reset_tl1[] = { + /* reg, mask */ + {RESET0_LEVEL_TXLX, ((1<<5) | (1<<10) | (1<<19) | (1<<13))}, + {RESET1_LEVEL_TXLX, ((1<<5) | (1<<4))}, + {RESET2_LEVEL_TXLX, (1<<15)}, + {RESET4_LEVEL_TXLX, ((1<<6) | (1<<7) | (1<<13) | (1<<5) | + (1<<9) | (1<<4) | (1<<12))}, + {RESET7_LEVEL_TXLX, (1<<7)}, + {VPU_REG_END, 0}, }; -/* ************************************************ */ #endif diff --git a/drivers/amlogic/media/common/vpu/vpu_module.h b/drivers/amlogic/media/common/vpu/vpu_module.h index 85f6efd3dc68..30f0cd9b0401 100644 --- a/drivers/amlogic/media/common/vpu/vpu_module.h +++ b/drivers/amlogic/media/common/vpu/vpu_module.h @@ -59,6 +59,7 @@ static char *vpu_mod_table[] = { "vencp", "vencl", "venci", + "ls_stts", "ldim_stts", "tv_decoder_cvd2", "xvycc_lut", @@ -73,10 +74,16 @@ static char *vpu_mod_table[] = { "osd_bld34", "prime_dolby_ram", "vd2_ofifo", + "ds", "lut3d", "viu2_osd_rotation", + "vi_dipre", "rdma", + "axi_wr1", + "axi_wr0", + "afbce", + "vpu_mod_max", /* for clk_gate */ diff --git a/drivers/amlogic/media/common/vpu/vpu_power_init.c b/drivers/amlogic/media/common/vpu/vpu_power_init.c index c59aa6cab34e..07c5c848e638 100644 --- a/drivers/amlogic/media/common/vpu/vpu_power_init.c +++ b/drivers/amlogic/media/common/vpu/vpu_power_init.c @@ -18,15 +18,9 @@ #include #include #include -#include #include #include -#include -#include #include -#include -#include -#include #include #include "vpu_reg.h" #include "vpu.h" @@ -38,41 +32,30 @@ void vpu_mem_pd_init_off(void) VPUPR("%s\n", __func__); } -void vpu_clk_gate_init_off(void) -{ - VPUPR("%s\n", __func__); - - switch (vpu_conf.data->chip_type) { - case VPU_CHIP_TXLX: - /* dolby core1 */ - vpu_vcbus_setb(DOLBY_TV_CLKGATE_CTRL, 1, 10, 2); - vpu_vcbus_setb(DOLBY_TV_CLKGATE_CTRL, 1, 2, 2); - vpu_vcbus_setb(DOLBY_TV_CLKGATE_CTRL, 1, 4, 2); - /* dolby core2 */ - vpu_vcbus_setb(DOLBY_CORE2A_CLKGATE_CTRL, 1, 10, 2); - vpu_vcbus_setb(DOLBY_CORE2A_CLKGATE_CTRL, 1, 2, 2); - vpu_vcbus_setb(DOLBY_CORE2A_CLKGATE_CTRL, 1, 4, 2); - /* dolby core3 */ - vpu_vcbus_setb(DOLBY_CORE3_CLKGATE_CTRL, 0, 1, 1); - vpu_vcbus_setb(DOLBY_CORE3_CLKGATE_CTRL, 1, 2, 2); - break; - case VPU_CHIP_GXM: - vpu_vcbus_write(DOLBY_CORE1_CLKGATE_CTRL, 0x55555555); - vpu_vcbus_write(DOLBY_CORE2A_CLKGATE_CTRL, 0x55555555); - vpu_vcbus_write(DOLBY_CORE3_CLKGATE_CTRL, 0x55555555); - break; - default: - break; - } - - if (vpu_debug_print_flag) - VPUPR("%s finish\n", __func__); -} - void vpu_module_init_config(void) { + struct vpu_ctrl_s *ctrl_table; + unsigned int _reg, _val, _bit, _len; + int i = 0, cnt; + VPUPR("%s\n", __func__); + /* vpu clk gate init off */ + cnt = vpu_conf.data->module_init_table_cnt; + ctrl_table = vpu_conf.data->module_init_table; + if (ctrl_table) { + while (i < cnt) { + if (ctrl_table[i].reg == VPU_REG_END) + break; + _reg = ctrl_table[i].reg; + _val = ctrl_table[i].val; + _bit = ctrl_table[i].bit; + _len = ctrl_table[i].len; + vpu_vcbus_setb(_reg, _val, _bit, _len); + i++; + } + } + /* dmc_arb_config */ vpu_vcbus_write(VPU_RDARB_MODE_L1C1, 0x210000); vpu_vcbus_write(VPU_RDARB_MODE_L1C2, 0x10000); @@ -83,10 +66,11 @@ void vpu_module_init_config(void) VPUPR("%s finish\n", __func__); } -void vpu_power_on_gx(void) +void vpu_power_on(void) { - struct vpu_ctrl_s *table; - unsigned int _reg, _bit, _len; + struct vpu_ctrl_s *ctrl_table; + struct vpu_reset_s *reset_table; + unsigned int _reg, _bit, _len, mask; int i = 0, cnt; VPUPR("vpu_power_on\n"); @@ -96,13 +80,13 @@ void vpu_power_on_gx(void) /* power up memories */ cnt = vpu_conf.data->mem_pd_table_cnt; - table = vpu_conf.data->mem_pd_table; + ctrl_table = vpu_conf.data->mem_pd_table; while (i < cnt) { - if (table[i].vmod == VPU_MOD_MAX) + if (ctrl_table[i].vmod == VPU_MOD_MAX) break; - _reg = table[i].reg; - _bit = table[i].bit; - _len = table[i].len; + _reg = ctrl_table[i].reg; + _bit = ctrl_table[i].bit; + _len = ctrl_table[i].len; vpu_hiu_setb(_reg, 0x0, _bit, _len); udelay(5); i++; @@ -116,33 +100,39 @@ void vpu_power_on_gx(void) /* Reset VIU + VENC */ /* Reset VENCI + VENCP + VADC + VENCL */ /* Reset HDMI-APB + HDMI-SYS + HDMI-TX + HDMI-CEC */ - vpu_cbus_clr_mask(RESET0_LEVEL, ((1<<5) | (1<<10) | (1<<19) | (1<<13))); - vpu_cbus_clr_mask(RESET1_LEVEL, (1<<5)); - vpu_cbus_clr_mask(RESET2_LEVEL, (1<<15)); - vpu_cbus_clr_mask(RESET4_LEVEL, ((1<<6) | (1<<7) | (1<<13) | (1<<5) | - (1<<9) | (1<<4) | (1<<12))); - vpu_cbus_clr_mask(RESET7_LEVEL, (1<<7)); + reset_table = vpu_conf.data->reset_table; + i = 0; + while (i < VPU_RESET_CNT_MAX) { + if (reset_table[i].reg == VPU_REG_END) + break; + _reg = reset_table[i].reg; + mask = reset_table[i].mask; + vpu_cbus_clr_mask(_reg, mask); + i++; + } + udelay(5); + /* release Reset */ + i = 0; + while (i < VPU_RESET_CNT_MAX) { + if (reset_table[i].reg == VPU_REG_END) + break; + _reg = reset_table[i].reg; + mask = reset_table[i].mask; + vpu_cbus_set_mask(_reg, mask); + i++; + } /* Remove VPU_HDMI ISO */ vpu_ao_setb(AO_RTI_GEN_PWR_SLEEP0, 0, 9, 1); /* [9] VPU_HDMI */ - /* release Reset */ - vpu_cbus_set_mask(RESET0_LEVEL, ((1 << 5) | (1<<10) | (1<<19) | - (1<<13))); - vpu_cbus_set_mask(RESET1_LEVEL, (1<<5)); - vpu_cbus_set_mask(RESET2_LEVEL, (1<<15)); - vpu_cbus_set_mask(RESET4_LEVEL, ((1<<6) | (1<<7) | (1<<13) | (1<<5) | - (1<<9) | (1<<4) | (1<<12))); - vpu_cbus_set_mask(RESET7_LEVEL, (1<<7)); - if (vpu_debug_print_flag) VPUPR("%s finish\n", __func__); } -void vpu_power_off_gx(void) +void vpu_power_off(void) { - struct vpu_ctrl_s *table; - unsigned int _reg, _bit, _len; + struct vpu_ctrl_s *ctrl_table; + unsigned int _val, _reg, _bit, _len; int i = 0, cnt; VPUPR("vpu_power_off\n"); @@ -154,113 +144,18 @@ void vpu_power_off_gx(void) /* power down memories */ cnt = vpu_conf.data->mem_pd_table_cnt; - table = vpu_conf.data->mem_pd_table; + ctrl_table = vpu_conf.data->mem_pd_table; while (i < cnt) { - if (table[i].vmod == VPU_MOD_MAX) + if (ctrl_table[i].vmod == VPU_MOD_MAX) break; - _reg = table[i].reg; - _bit = table[i].bit; - _len = table[i].len; - vpu_hiu_setb(_reg, 0x3, _bit, _len); - udelay(5); - i++; - } - for (i = 8; i < 16; i++) { - vpu_hiu_setb(HHI_MEM_PD_REG0, 0x1, i, 1); - udelay(5); - } - udelay(20); - - /* Power down VPU domain */ - vpu_ao_setb(AO_RTI_GEN_PWR_SLEEP0, 1, 8, 1); /* PDN */ - - vpu_hiu_setb(HHI_VAPBCLK_CNTL, 0, 8, 1); - vpu_hiu_setb(HHI_VPU_CLK_CNTL, 0, 8, 1); - - if (vpu_debug_print_flag) - VPUPR("%s finish\n", __func__); -} - -void vpu_power_on_txlx(void) -{ - struct vpu_ctrl_s *table; - unsigned int _reg, _bit, _len; - int i = 0, cnt; - - VPUPR("vpu_power_on\n"); - - vpu_ao_setb(AO_RTI_GEN_PWR_SLEEP0, 0, 8, 1); /* [8] power on */ - udelay(20); - - /* power up memories */ - cnt = vpu_conf.data->mem_pd_table_cnt; - table = vpu_conf.data->mem_pd_table; - while (i < cnt) { - if (table[i].vmod == VPU_MOD_MAX) - break; - _reg = table[i].reg; - _bit = table[i].bit; - _len = table[i].len; - vpu_hiu_setb(_reg, 0x0, _bit, _len); - udelay(5); - i++; - } - for (i = 8; i < 16; i++) { - vpu_hiu_setb(HHI_MEM_PD_REG0, 0, i, 1); - udelay(5); - } - udelay(20); - - /* Reset VIU + VENC */ - /* Reset VENCI + VENCP + VADC + VENCL */ - /* Reset HDMI-APB + HDMI-SYS + HDMI-TX + HDMI-CEC */ - vpu_cbus_clr_mask(RESET0_LEVEL_TXLX, ((1<<5) | (1<<10) | (1<<19) | - (1<<13))); - vpu_cbus_clr_mask(RESET1_LEVEL_TXLX, (1<<5)); - vpu_cbus_clr_mask(RESET2_LEVEL_TXLX, (1<<15)); - vpu_cbus_clr_mask(RESET4_LEVEL_TXLX, ((1<<6) | (1<<7) | (1<<13) | - (1<<5) | (1<<9) | (1<<4) | (1<<12))); - vpu_cbus_clr_mask(RESET7_LEVEL_TXLX, (1<<7)); - - /* Remove VPU_HDMI ISO */ - vpu_ao_setb(AO_RTI_GEN_PWR_SLEEP0, 0, 9, 1); /* [9] VPU_HDMI */ - - /* release Reset */ - vpu_cbus_set_mask(RESET0_LEVEL_TXLX, ((1 << 5) | (1<<10) | (1<<19) | - (1<<13))); - vpu_cbus_set_mask(RESET1_LEVEL_TXLX, (1<<5)); - vpu_cbus_set_mask(RESET2_LEVEL_TXLX, (1<<15)); - vpu_cbus_set_mask(RESET4_LEVEL_TXLX, ((1<<6) | (1<<7) | (1<<13) | - (1<<5) | (1<<9) | (1<<4) | (1<<12))); - vpu_cbus_set_mask(RESET7_LEVEL_TXLX, (1<<7)); - - if (vpu_debug_print_flag) - VPUPR("%s finish\n", __func__); -} - -void vpu_power_off_txlx(void) -{ - struct vpu_ctrl_s *table; - unsigned int _reg, _bit, _len; - int i = 0, cnt; - - VPUPR("vpu_power_off\n"); - - /* Power down VPU_HDMI */ - /* Enable Isolation */ - vpu_ao_setb(AO_RTI_GEN_PWR_SLEEP0, 1, 9, 1); /* ISO */ - udelay(20); - - /* power down memories */ - cnt = vpu_conf.data->mem_pd_table_cnt; - table = vpu_conf.data->mem_pd_table; - while (i < cnt) { - if (table[i].vmod == VPU_MOD_MAX) - break; - _reg = table[i].reg; - _bit = table[i].bit; - _len = table[i].len; - vpu_hiu_setb(_reg, 0x3, _bit, _len); + _reg = ctrl_table[i].reg; + _bit = ctrl_table[i].bit; + _len = ctrl_table[i].len; + if (_len == 32) + _val = 0xffffffff; + else + _val = (1 << _len) - 1; + vpu_hiu_setb(_reg, _val, _bit, _len); udelay(5); i++; } diff --git a/drivers/amlogic/media/common/vpu/vpu_reg.h b/drivers/amlogic/media/common/vpu/vpu_reg.h index 7fb946e0df81..4bac30b96647 100644 --- a/drivers/amlogic/media/common/vpu/vpu_reg.h +++ b/drivers/amlogic/media/common/vpu/vpu_reg.h @@ -40,6 +40,8 @@ #define HHI_VPU_MEM_PD_REG0 0x41 #define HHI_VPU_MEM_PD_REG1 0x42 #define HHI_VPU_MEM_PD_REG2 0x4d +#define HHI_VPU_MEM_PD_REG3 0x4e +#define HHI_VPU_MEM_PD_REG4 0x4c #define HHI_VPU_CLKC_CNTL 0x6d #define HHI_VPU_CLK_CNTL 0x6f diff --git a/drivers/amlogic/media/deinterlace/deinterlace.c b/drivers/amlogic/media/deinterlace/deinterlace.c index bd94f3a8c691..bfb137868b30 100644 --- a/drivers/amlogic/media/deinterlace/deinterlace.c +++ b/drivers/amlogic/media/deinterlace/deinterlace.c @@ -73,6 +73,12 @@ #include /*2018-07-18 -----------*/ +#undef TRACE_INCLUDE_PATH +#undef TRACE_INCLUDE_FILE +#define TRACE_INCLUDE_PATH . +#define TRACE_INCLUDE_FILE deinterlace_trace +#include + #ifdef DET3D #include "detect3d.h" #endif @@ -123,7 +129,7 @@ static di_dev_t *de_devp; static dev_t di_devno; static struct class *di_clsp; -static const char version_s[] = "2018-09-28a"; +static const char version_s[] = "2018-11-28b"; static int bypass_state = 1; static int bypass_all; @@ -1237,7 +1243,61 @@ static bool is_in_queue(struct di_buf_s *di_buf, int queue_idx) } return ret; } +//--------------------------- +u8 *di_vmap(ulong addr, u32 size, bool *bflg) +{ + u8 *vaddr = NULL; + ulong phys = addr; + u32 offset = phys & ~PAGE_MASK; + u32 npages = PAGE_ALIGN(size) / PAGE_SIZE; + struct page **pages = NULL; + pgprot_t pgprot; + int i; + if (!PageHighMem(phys_to_page(phys))) + return phys_to_virt(phys); + + if (offset) + npages++; + + pages = vmalloc(sizeof(struct page *) * npages); + if (!pages) + return NULL; + + for (i = 0; i < npages; i++) { + pages[i] = phys_to_page(phys); + phys += PAGE_SIZE; + } + + /*nocache*/ + pgprot = pgprot_writecombine(PAGE_KERNEL); + + vaddr = vmap(pages, npages, VM_MAP, pgprot); + if (!vaddr) { + pr_err("the phy(%lx) vmaped fail, size: %d\n", + addr - offset, npages << PAGE_SHIFT); + vfree(pages); + return NULL; + } + + vfree(pages); + +// if (debug_mode & 0x20) { +// di_print("[HIGH-MEM-MAP] %s, pa(%lx) to va(%p), size: %d\n", +// __func__, addr, vaddr + offset, npages << PAGE_SHIFT); +// } + *bflg = true; + + return vaddr + offset; +} + +void di_unmap_phyaddr(u8 *vaddr) +{ + void *addr = (void *)(PAGE_MASK & (ulong)vaddr); + + vunmap(addr); +} +//------------------------- static ssize_t store_dump_mem(struct device *dev, struct device_attribute *attr, const char *buf, size_t len) @@ -1254,6 +1314,7 @@ store_dump_mem(struct device *dev, struct device_attribute *attr, loff_t pos = 0; void *buff = NULL; mm_segment_t old_fs; + bool bflg_vmap = false; buf_orig = kstrdup(buf, GFP_KERNEL); ps = buf_orig; @@ -1300,10 +1361,18 @@ store_dump_mem(struct device *dev, struct device_attribute *attr, return len; } dump_state_flag = 1; - if (de_devp->flags & DI_MAP_FLAG) - buff = (void *)phys_to_virt(dump_adr); - else + if (de_devp->flags & DI_MAP_FLAG) { + //buff = (void *)phys_to_virt(dump_adr); + buff = di_vmap(dump_adr, nr_size, &bflg_vmap); + if (buff == NULL) { + pr_info("di_vap err\n"); + filp_close(filp, NULL); + return len; + + } + } else { buff = ioremap(dump_adr, nr_size); + } if (IS_ERR_OR_NULL(buff)) pr_err("%s: ioremap error.\n", __func__); vfs_write(filp, buff, nr_size, &pos); @@ -1327,6 +1396,10 @@ store_dump_mem(struct device *dev, struct device_attribute *attr, */ vfs_fsync(filp, 0); pr_info("write buffer 0x%lx to %s.\n", dump_adr, parm[1]); + if (bflg_vmap) + di_unmap_phyaddr(buff); + + if (!(de_devp->flags & DI_MAP_FLAG)) iounmap(buff); dump_state_flag = 0; @@ -4194,7 +4267,8 @@ static irqreturn_t de_irq(int irq, void *dev_instance) is_meson_txhd_cpu()) mc_pre_mv_irq(); calc_lmv_base_mcinfo((di_pre_stru.cur_height>>1), - di_pre_stru.di_wr_buf->mcinfo_adr); + di_pre_stru.di_wr_buf->mcinfo_adr, + di_pre_stru.mcinfo_size); } nr_process_in_irq(); if ((data32&0x200) && de_devp->nrds_enable) @@ -5973,11 +6047,14 @@ static bool need_bypass(struct vframe_s *vf) if (vf->type & VIDTYPE_PIC) return true; -#if 1 +#if 0 if (vf->type & VIDTYPE_COMPRESS) return true; #else + /*support G12A and TXLX platform*/ if (vf->type & VIDTYPE_COMPRESS) { + if (!afbc_is_supported()) + return true; if ((vf->compHeight > (default_height + 8)) || (vf->compWidth > default_width)) return true; @@ -6313,7 +6390,7 @@ static int di_task_handle(void *data) di_pre_stru.reg_req_flag_irq = 0; } #ifdef CONFIG_CMA - mutex_lock(&de_devp->cma_mutex); + /* mutex_lock(&de_devp->cma_mutex);*/ if (di_pre_stru.cma_release_req) { atomic_set(&devp->mem_flag, 0); di_cma_release(devp); @@ -6328,7 +6405,7 @@ static int di_task_handle(void *data) di_pre_stru.cma_alloc_req = 0; di_pre_stru.cma_alloc_done = 1; } - mutex_unlock(&de_devp->cma_mutex); + /* mutex_unlock(&de_devp->cma_mutex); */ #endif } if (de_devp->flags & DI_VPU_CLKB_SET) { @@ -6451,6 +6528,13 @@ static int di_receiver_event_fun(int type, void *data, void *arg) di_blocking = 1; pr_dbg("%s: VFRAME_EVENT_PROVIDER_RESET\n", __func__); + if (is_bypass(NULL) + || bypass_state + || di_pre_stru.bypass_flag) { + vf_notify_receiver(VFM_NAME, + VFRAME_EVENT_PROVIDER_RESET, + NULL); + } goto light_unreg; } else if (type == VFRAME_EVENT_PROVIDER_LIGHT_UNREG) { @@ -7435,7 +7519,7 @@ static int di_probe(struct platform_device *pdev) } else { atomic_set(&di_devp->mem_flag, 1); } - mutex_init(&di_devp->cma_mutex); + /* mutex_init(&di_devp->cma_mutex); */ INIT_LIST_HEAD(&di_devp->pq_table_list); atomic_set(&di_devp->pq_flag, 0); @@ -7562,8 +7646,9 @@ static int di_remove(struct platform_device *pdev) di_devp->di_event = 0xff; kthread_stop(di_devp->task); hrtimer_cancel(&di_pre_hrtimer); + tasklet_kill(&di_pre_tasklet); //ary.sui tasklet_disable(&di_pre_tasklet); - tasklet_kill(&di_pre_tasklet); + #ifdef CONFIG_AMLOGIC_MEDIA_RDMA /* rdma handle */ if (di_devp->rdma_handle > 0) @@ -7619,8 +7704,9 @@ static void di_shutdown(struct platform_device *pdev) di_devp = platform_get_drvdata(pdev); ret = hrtimer_cancel(&di_pre_hrtimer); pr_info("di pre hrtimer canel %d.\n", ret); - tasklet_disable(&di_pre_tasklet); tasklet_kill(&di_pre_tasklet); + tasklet_disable(&di_pre_tasklet); + init_flag = 0; if (is_meson_txlx_cpu()) di_top_gate_control(true, true); diff --git a/drivers/amlogic/media/deinterlace/deinterlace.h b/drivers/amlogic/media/deinterlace/deinterlace.h index ed2442e4ea36..0e38fdd681de 100644 --- a/drivers/amlogic/media/deinterlace/deinterlace.h +++ b/drivers/amlogic/media/deinterlace/deinterlace.h @@ -235,7 +235,7 @@ struct di_dev_s { unsigned int post_wr_support; unsigned int nrds_enable; unsigned int pps_enable; - struct mutex cma_mutex; + /*struct mutex cma_mutex;*/ unsigned int flag_cma; struct page *total_pages; atomic_t mem_flag; @@ -419,6 +419,8 @@ struct di_buf_s *get_di_recovery_log_di_buf(void); int get_di_video_peek_cnt(void); unsigned long get_di_reg_unreg_timeout_cnt(void); struct vframe_s **get_di_vframe_in(void); + + /*---------------------*/ struct di_buf_s *get_di_buf(int queue_idx, int *start_pos); diff --git a/drivers/amlogic/media/deinterlace/deinterlace_dbg.c b/drivers/amlogic/media/deinterlace/deinterlace_dbg.c index 74fbd321b97d..5f5c7fdb2b18 100644 --- a/drivers/amlogic/media/deinterlace/deinterlace_dbg.c +++ b/drivers/amlogic/media/deinterlace/deinterlace_dbg.c @@ -519,9 +519,9 @@ static int dump_di_pre_stru_seq(struct seq_file *seq, void *v) seq_puts(seq, "di_pre_stru:\n"); seq_printf(seq, "%-25s = 0x%p\n", "di_mem_buf_dup_p", - &di_pre_stru_p->di_mem_buf_dup_p); + di_pre_stru_p->di_mem_buf_dup_p); seq_printf(seq, "%-25s = 0x%p\n", "di_chan2_buf_dup_p", - &di_pre_stru_p->di_chan2_buf_dup_p); + di_pre_stru_p->di_chan2_buf_dup_p); seq_printf(seq, "%-25s = %d\n", "in_seq", di_pre_stru_p->in_seq); seq_printf(seq, "%-25s = %d\n", "recycle_seq", @@ -559,7 +559,7 @@ static int dump_di_pre_stru_seq(struct seq_file *seq, void *v) seq_printf(seq, "%-25s = %d\n", "source_change_flag", di_pre_stru_p->source_change_flag); seq_printf(seq, "%-25s = %s\n", "bypass_flag", - &di_pre_stru_p->bypass_flag?"true":"false"); + di_pre_stru_p->bypass_flag?"true":"false"); seq_printf(seq, "%-25s = %d\n", "prog_proc_type", di_pre_stru_p->prog_proc_type); seq_printf(seq, "%-25s = %d\n", "madi_enable", @@ -568,18 +568,18 @@ static int dump_di_pre_stru_seq(struct seq_file *seq, void *v) di_pre_stru_p->mcdi_enable); #ifdef DET3D seq_printf(seq, "%-25s = %d\n", "vframe_interleave_flag", - &di_pre_stru_p->vframe_interleave_flag); + di_pre_stru_p->vframe_interleave_flag); #endif seq_printf(seq, "%-25s = %d\n", "left_right", di_pre_stru_p->left_right); seq_printf(seq, "%-25s = %s\n", "force_interlace", - &di_pre_stru_p->force_interlace ? "true" : "false"); + di_pre_stru_p->force_interlace ? "true" : "false"); seq_printf(seq, "%-25s = %d\n", "vdin2nr", di_pre_stru_p->vdin2nr); seq_printf(seq, "%-25s = %s\n", "bypass_pre", - &di_pre_stru_p->bypass_pre ? "true" : "false"); + di_pre_stru_p->bypass_pre ? "true" : "false"); seq_printf(seq, "%-25s = %s\n", "invert_flag", - &di_pre_stru_p->invert_flag ? "true" : "false"); + di_pre_stru_p->invert_flag ? "true" : "false"); return 0; } @@ -617,7 +617,7 @@ static int dump_di_post_stru_seq(struct seq_file *seq, void *v) seq_printf(seq, "de_post_process_done = %d\n", di_post_stru_p->de_post_process_done); seq_printf(seq, "cur_post_buf = 0x%p\n", - &di_post_stru_p->cur_post_buf); + di_post_stru_p->cur_post_buf); seq_printf(seq, "post_peek_underflow = %u\n", di_post_stru_p->post_peek_underflow); @@ -918,15 +918,13 @@ static void print_di_buf_seq(struct di_buf_s *di_buf, int format, return; if (format == 1) { seq_printf(seq, - "\t+index %d, 0x%p, type %d, vframetype 0x%x\n", + "\t+index %d, 0x%p, type %d, vframetype 0x%x, trans_fmt %u,bitdepath %d\n", di_buf->index, di_buf, di_buf->type, - di_buf->vframe->type); - seq_printf(seq, "\t+trans_fmt %u,bitdepath %d pages %p\n", + di_buf->vframe->type, di_buf->vframe->trans_fmt, - di_buf->vframe->bitdepth, - di_buf->pages); + di_buf->vframe->bitdepth); if (di_buf->di_wr_linked_buf) { seq_printf(seq, "\tlinked +index %d, 0x%p, type %d\n", di_buf->di_wr_linked_buf->index, @@ -934,9 +932,9 @@ static void print_di_buf_seq(struct di_buf_s *di_buf, int format, di_buf->di_wr_linked_buf->type); } } else if (format == 2) { - seq_printf(seq, "index %d, 0x%p(vframe 0x%p), type %d pages %p\n", + seq_printf(seq, "index %d, 0x%p(vframe 0x%p), type %d\n", di_buf->index, di_buf, - di_buf->vframe, di_buf->type, di_buf->pages); + di_buf->vframe, di_buf->type); seq_printf(seq, "vframetype 0x%x, trans_fmt %u,duration %d pts %d,bitdepth %d\n", di_buf->vframe->type, di_buf->vframe->trans_fmt, diff --git a/drivers/amlogic/media/deinterlace/deinterlace_hw.c b/drivers/amlogic/media/deinterlace/deinterlace_hw.c index 42724dc36038..c59725886348 100644 --- a/drivers/amlogic/media/deinterlace/deinterlace_hw.c +++ b/drivers/amlogic/media/deinterlace/deinterlace_hw.c @@ -314,17 +314,29 @@ static struct mcinfo_lmv_s lines_mv[540]; static short offset_lmv = 100; module_param_named(offset_lmv, offset_lmv, short, 0644); -void calc_lmv_base_mcinfo(unsigned int vf_height, unsigned long mcinfo_adr) +void calc_lmv_base_mcinfo(unsigned int vf_height, unsigned long mcinfo_adr, + unsigned int mcinfo_size) { unsigned short i, top_str, bot_str, top_end, bot_end, j = 0; unsigned short *mcinfo_vadr = NULL, lck_num; unsigned short flg_m1 = 0, flg_i = 0, nLmvLckSt = 0; unsigned short lmv_lckstext[3] = {0, 0, 0}, nLmvLckEd; unsigned short lmv_lckedext[3] = {0, 0, 0}, nLmvLckNum; + bool bflg_vmap = false; + u8 *tmp; + + //mcinfo_vadr = (unsigned short *)phys_to_virt(mcinfo_adr); - mcinfo_vadr = (unsigned short *)phys_to_virt(mcinfo_adr); if (!lmv_lock_win_en) return; + + tmp = di_vmap(mcinfo_adr, mcinfo_size, &bflg_vmap); + if (tmp == NULL) { + di_print("err:di_vmap failed\n"); + return; + } + mcinfo_vadr = (unsigned short *)tmp; + for (i = 0; i < (vf_height>>1); i++) { lmvs_init(&lines_mv[i], *(mcinfo_vadr+i)); j = i + (vf_height>>1); @@ -337,6 +349,9 @@ void calc_lmv_base_mcinfo(unsigned int vf_height, unsigned long mcinfo_adr) pr_info("\n"); } } + if (bflg_vmap) + di_unmap_phyaddr(tmp); + pr_mcinfo_cnt ? pr_mcinfo_cnt-- : (pr_mcinfo_cnt = 0); top_str = 0; top_end = offset_lmv; @@ -939,7 +954,7 @@ static enum eAFBC_DEC afbc_get_decnub(void) sel_dec = eAFBC_DEC0; else if (is_meson_txlx_cpu()) sel_dec = eAFBC_DEC1; - else if (cpu_after_eq(MESON_CPU_MAJOR_ID_G12A)) + else if (is_meson_g12a_cpu()) sel_dec = AFBC_DEC_SEL; @@ -951,13 +966,13 @@ static const unsigned int *afbc_get_regbase(void) return ®_AFBC[afbc_get_decnub()][0]; } -static bool afbc_is_supported(void) +bool afbc_is_supported(void) { bool ret = false; - if (is_meson_gxl_cpu() - || is_meson_txlx_cpu() - || cpu_after_eq(MESON_CPU_MAJOR_ID_G12A)) + /*currently support txlx and g12a*/ + if (is_meson_txlx_cpu() + || is_meson_g12a_cpu()) ret = true; return ret; @@ -2466,10 +2481,11 @@ void initial_di_post_2(int hsize_post, int vsize_post, if (post_write_en) { DI_VSYNC_WR_MPEG_REG(DI_POST_GL_CTRL, 0x80000000|line_num_post_frst); + /*di if0 mif to di post*/ + DI_VSYNC_WR_MPEG_REG_BITS(VIUB_MISC_CTRL0, 0, 4, 1); + /*di_mif0_en:select mif to di*/ DI_VSYNC_WR_MPEG_REG_BITS(VD1_AFBCD0_MISC_CTRL, - 0, 20, 1); - DI_VSYNC_WR_MPEG_REG_BITS(VD1_AFBCD0_MISC_CTRL, - 0, 8, 9); + 1, 8, 1); } else { DI_VSYNC_WR_MPEG_REG_BITS(VD1_AFBCD0_MISC_CTRL, 1, 8, 1); diff --git a/drivers/amlogic/media/deinterlace/deinterlace_hw.h b/drivers/amlogic/media/deinterlace/deinterlace_hw.h index 4a9582f3e757..8d8b95d66a73 100644 --- a/drivers/amlogic/media/deinterlace/deinterlace_hw.h +++ b/drivers/amlogic/media/deinterlace/deinterlace_hw.h @@ -165,7 +165,8 @@ void enable_di_post_mif(enum gate_mode_e mode); void di_hw_uninit(void); void combing_pd22_window_config(unsigned int width, unsigned int height); void calc_lmv_init(void); -void calc_lmv_base_mcinfo(unsigned int vf_height, unsigned long mcinfo_adr); +void calc_lmv_base_mcinfo(unsigned int vf_height, unsigned long mcinfo_adr, + unsigned int mcinfo_size); void init_field_mode(unsigned short height); void film_mode_win_config(unsigned int width, unsigned int height); void pulldown_vof_win_config(struct pulldown_detected_s *wins); @@ -176,10 +177,14 @@ void di_interrupt_ctrl(unsigned char ma_en, unsigned char det3d_en, unsigned char nrds_en, unsigned char post_wr, unsigned char mc_en); void di_txl_patch_prog(int prog_flg, unsigned int cnt, bool mc_en); +bool afbc_is_supported(void); //extern void afbc_power_sw(bool on); extern void afbc_reg_sw(bool on); extern void afbc_sw_trig(bool on); extern void dump_vd2_afbc(void); +extern u8 *di_vmap(ulong addr, u32 size, bool *bflg); +extern void di_unmap_phyaddr(u8 *vaddr); +extern int di_print(const char *fmt, ...); #endif diff --git a/drivers/amlogic/media/deinterlace/deinterlace_trace.h b/drivers/amlogic/media/deinterlace/deinterlace_trace.h index bee3411fad68..d309dedd2090 100644 --- a/drivers/amlogic/media/deinterlace/deinterlace_trace.h +++ b/drivers/amlogic/media/deinterlace/deinterlace_trace.h @@ -50,8 +50,10 @@ DEFINE_DI_EVENT(di_pre); DEFINE_DI_EVENT(di_post); #endif /* _VDEC_TRACE_H */ +#if 0 #undef TRACE_INCLUDE_PATH #undef TRACE_INCLUDE_FILE #define TRACE_INCLUDE_PATH . #define TRACE_INCLUDE_FILE deinterlace_trace #include +#endif diff --git a/drivers/amlogic/media/dtv_demod/amlfrontend.c b/drivers/amlogic/media/dtv_demod/amlfrontend.c index 53fc0b620a9f..8337e0b04734 100644 --- a/drivers/amlogic/media/dtv_demod/amlfrontend.c +++ b/drivers/amlogic/media/dtv_demod/amlfrontend.c @@ -2468,24 +2468,30 @@ static int gxtv_demod_dtmb_tune(struct dvb_frontend *fe, bool re_tune, #ifdef CONFIG_CMA /*void dtmb_cma_alloc(struct aml_fe_dev *devp)*/ -void dtmb_cma_alloc(struct amldtvdemod_device_s *devp) +bool dtmb_cma_alloc(struct amldtvdemod_device_s *devp) { + bool ret; + unsigned int mem_size = devp->cma_mem_size; /* dma_alloc_from_contiguous*/ devp->venc_pages = dma_alloc_from_contiguous(&(devp->this_pdev->dev), mem_size >> PAGE_SHIFT, 0); - PR_DBG("[cma]mem_size is %d,%d\n", - mem_size, mem_size >> PAGE_SHIFT); - if (devp->venc_pages) { - devp->mem_start = page_to_phys(devp->venc_pages); - devp->mem_size = mem_size; - PR_DBG("demod mem_start = 0x%x, mem_size = 0x%x\n", - devp->mem_start, devp->mem_size); - PR_DBG("demod cma alloc ok!\n"); - } else { - PR_DBG("demod cma mem undefined2.\n"); - } + PR_DBG("[cma]mem_size is %d,%d\n", + mem_size, mem_size >> PAGE_SHIFT); + if (devp->venc_pages) { + devp->mem_start = page_to_phys(devp->venc_pages); + devp->mem_size = mem_size; + devp->flg_cma_allc = true; + PR_DBG("demod mem_start = 0x%x, mem_size = 0x%x\n", + devp->mem_start, devp->mem_size); + PR_DBG("demod cma alloc ok!\n"); + ret = true; + } else { + PR_DBG("demod cma mem undefined2.\n"); + ret = false; + } + return ret; } /*void dtmb_cma_release(struct aml_fe_dev *devp)*/ @@ -2501,11 +2507,12 @@ void dtmb_cma_release(struct amldtvdemod_device_s *devp) } #endif -static int enter_mode(int mode) +static bool enter_mode(int mode) { /*struct aml_fe_dev *dev = fe->dtv_demod;*/ struct amldtvdemod_device_s *devn = dtvdd_devp; int memstart_dtmb; + bool ret = true; PR_INFO("%s:%d\n", __func__, mode); @@ -2529,12 +2536,18 @@ static int enter_mode(int mode) if (devn->cma_flag == 1) { PR_DBG("CMA MODE, cma flag is %d,mem size is %d", devn->cma_flag, devn->cma_mem_size); - dtmb_cma_alloc(devn); - memstart_dtmb = devn->mem_start; + if (dtmb_cma_alloc(devn)) { + memstart_dtmb = devn->mem_start; + } else { + ret = false; + return ret; + + } + } else { memstart_dtmb = devn->mem_start;/*??*/ } - + devn->act_dtmb = true; dtmb_set_mem_st(memstart_dtmb); demod_write_reg(DEMOD_REG4, 0x8); @@ -2557,8 +2570,13 @@ static int enter_mode(int mode) PR_DBG("CMA MODE, cma flag is %d,mem size is %d", devn->cma_flag, devn->cma_mem_size); - dtmb_cma_alloc(devn); - memstart_dtmb = devn->mem_start; + if (dtmb_cma_alloc(devn)) { + memstart_dtmb = devn->mem_start; + } else { + ret = false; + return ret; + + } } else { memstart_dtmb = devn->mem_start;/*??*/ } @@ -2566,7 +2584,7 @@ static int enter_mode(int mode) dvbt_write_reg((0x10 << 2), memstart_dtmb); } - return 0; + return ret; } @@ -2583,6 +2601,7 @@ static int leave_mode(int mode) /*dvbc_timer_exit();*/ if (cci_thread) dvbc_kill_cci_task(); + #if 0 if (mode == AM_FE_DTMB_N) { dtmb_poll_stop(); /*polling mode*/ /* close arbit */ @@ -2591,7 +2610,18 @@ static int leave_mode(int mode) if (devn->cma_flag == 1) dtmb_cma_release(devn); } - + #else + if (dtvdd_devp->act_dtmb) { + dtmb_poll_stop(); /*polling mode*/ + /* close arbit */ + demod_write_reg(DEMOD_REG4, 0x0); + dtvdd_devp->act_dtmb = false; + } + if ((devn->cma_flag == 1) && dtvdd_devp->flg_cma_allc) { + dtmb_cma_release(devn); + dtvdd_devp->flg_cma_allc = false; + } + #endif adc_set_pll_cntl(0, 0x04, NULL); demod_mode_para = UNKNOWN; @@ -3169,7 +3199,8 @@ static int aml_dtvdemod_probe(struct platform_device *pdev) dtvdd_devp->state = DTVDEMOD_ST_IDLE; dtvdemod_version(dtvdd_devp); - + dtvdd_devp->flg_cma_allc = false; + dtvdd_devp->act_dtmb = false; //ary temp: aml_demod_init(); @@ -3503,8 +3534,17 @@ static int delsys_set(struct dvb_frontend *fe, unsigned int delsys) return 0; } - if (mode != AM_FE_UNKNOWN_N) - enter_mode(mode); + if (mode != AM_FE_UNKNOWN_N) { + if (!enter_mode(mode)) { + PR_INFO("enter_mode failed,leave!\n"); + leave_mode(mode); + if (fe->ops.tuner_ops.release) + fe->ops.tuner_ops.release(fe); + dtvdd_devp->last_delsys = SYS_UNDEFINED; + dtvdd_devp->n_mode = AM_FE_UNKNOWN_N; + return 0; + } + } if (!get_dtvpll_init_flag()) { PR_INFO("pll is not set!\n"); diff --git a/drivers/amlogic/media/dtv_demod/include/amlfrontend.h b/drivers/amlogic/media/dtv_demod/include/amlfrontend.h index ea7dae3393c1..e5708856d028 100644 --- a/drivers/amlogic/media/dtv_demod/include/amlfrontend.h +++ b/drivers/amlogic/media/dtv_demod/include/amlfrontend.h @@ -221,7 +221,8 @@ struct amldtvdemod_device_s { struct ddemod_reg_off ireg; struct meson_ddemod_data *data; - + bool flg_cma_allc; + bool act_dtmb; struct poll_machie_s poll_machie; diff --git a/drivers/amlogic/media/enhancement/amdolby_vision/amdolby_vision.c b/drivers/amlogic/media/enhancement/amdolby_vision/amdolby_vision.c index c422c9882e81..f95d7170cc06 100644 --- a/drivers/amlogic/media/enhancement/amdolby_vision/amdolby_vision.c +++ b/drivers/amlogic/media/enhancement/amdolby_vision/amdolby_vision.c @@ -292,6 +292,10 @@ MODULE_PARM_DESC(dolby_vision_graphic_min, "\n dolby_vision_graphic_min\n"); module_param(dolby_vision_graphic_max, uint, 0664); MODULE_PARM_DESC(dolby_vision_graphic_max, "\n dolby_vision_graphic_max\n"); +/*these two parameters form OSD*/ +static unsigned int osd_graphic_width = 1920; +static unsigned int osd_graphic_height = 1080; + static unsigned int dv_cert_graphic_width = 1920; static unsigned int dv_cert_graphic_height = 1080; module_param(dv_cert_graphic_width, uint, 0664); @@ -1556,8 +1560,7 @@ static int dolby_core1_set( /* vd2 to core1 */ 0, 17, 1); } else { - if (get_cpu_type() == - MESON_CPU_MAJOR_ID_G12A) + if (is_meson_g12()) VSYNC_WR_MPEG_REG_BITS( DOLBY_PATH_CTRL, /* vd2 to core1 */ @@ -1764,8 +1767,7 @@ static int dolby_core2_set( VSYNC_WR_MPEG_REG(DOLBY_CORE2A_CLKGATE_CTRL, 0); VSYNC_WR_MPEG_REG(DOLBY_CORE2A_SWAP_CTRL0, 0); - if (is_meson_gxm() || - is_meson_g12() || reset) { + if (is_meson_gxm() || is_meson_g12() || reset) { VSYNC_WR_MPEG_REG(DOLBY_CORE2A_SWAP_CTRL1, ((hsize + g_htotal_add) << 16) | (vsize + g_vtotal_add + g_vsize_add)); @@ -1944,9 +1946,14 @@ static int dolby_core3_set( } if (new_dovi_setting.dovi_ll_enable && new_dovi_setting.diagnostic_enable == 0) { - /* bypass gainoff to vks */ + /*bypass gainoff to vks */ + /*enable wn tp vks*/ VSYNC_WR_MPEG_REG_BITS( VPP_DOLBY_CTRL, 0, 2, 1); + VSYNC_WR_MPEG_REG_BITS( + VPP_DOLBY_CTRL, 1, 1, 1); + VSYNC_WR_MPEG_REG( + VPP_DAT_CONV_PARA1, 0x8000800); VSYNC_WR_MPEG_REG_BITS( VPP_MATRIX_CTRL, 1, 0, 1); /* post matrix */ @@ -1954,6 +1961,10 @@ static int dolby_core3_set( /* bypass wm tp vks*/ VSYNC_WR_MPEG_REG_BITS( VPP_DOLBY_CTRL, 1, 2, 1); + VSYNC_WR_MPEG_REG_BITS( + VPP_DOLBY_CTRL, 0, 1, 1); + VSYNC_WR_MPEG_REG( + VPP_DAT_CONV_PARA1, 0x20002000); if (is_meson_txlx_tvmode()) enable_rgb_to_yuv_matrix_for_dvll( 0, NULL, 12); @@ -2050,6 +2061,13 @@ static int dolby_core3_set( return 0; } +void update_graphic_width_height(unsigned int width, + unsigned int height) +{ + osd_graphic_width = width; + osd_graphic_height = height; +} + static void apply_stb_core_settings( int enable, unsigned int mask, bool reset, u32 frame_size, u8 pps_state) @@ -2062,15 +2080,15 @@ static void apply_stb_core_settings( #else u32 core1_dm_count = 24; #endif - u32 graphics_w = 1920; - u32 graphics_h = 1080; + u32 graphics_w = osd_graphic_width; + u32 graphics_h = osd_graphic_height; if (is_dolby_vision_stb_mode() && (dolby_vision_flags & FLAG_CERTIFICAION)) { graphics_w = dv_cert_graphic_width; graphics_h = dv_cert_graphic_height; } - if (is_meson_txlx_package_962E() + if (is_meson_txlx_stbmode() || force_stb_mode) { if ((vinfo->width >= 1920) && (vinfo->height >= 1080) && @@ -2088,7 +2106,7 @@ static void apply_stb_core_settings( g_vpotch = 0x20; } if (mask & 1) { - if (is_meson_txlx_package_962E() + if (is_meson_txlx_stbmode() || force_stb_mode) { stb_dolby_core1_set( 27, 173, 256 * 5, @@ -2594,6 +2612,10 @@ void enable_dolby_vision(int enable) 0, 3, 1); /* bypass core3 */ VSYNC_WR_MPEG_REG(VPP_WRAP_OSD1_MATRIX_EN_CTRL, 0x0); + VSYNC_WR_MPEG_REG(VPP_WRAP_OSD2_MATRIX_EN_CTRL, + 0x0); + VSYNC_WR_MPEG_REG(VPP_WRAP_OSD3_MATRIX_EN_CTRL, + 0x0); if (dolby_vision_mask & 2) VSYNC_WR_MPEG_REG_BITS( DOLBY_PATH_CTRL, @@ -2843,6 +2865,10 @@ void enable_dolby_vision(int enable) } else if (is_meson_g12()) { VSYNC_WR_MPEG_REG(VPP_WRAP_OSD1_MATRIX_EN_CTRL, 0x1); + VSYNC_WR_MPEG_REG(VPP_WRAP_OSD2_MATRIX_EN_CTRL, + 0x1); + VSYNC_WR_MPEG_REG(VPP_WRAP_OSD3_MATRIX_EN_CTRL, + 0x1); VSYNC_WR_MPEG_REG_BITS( DOLBY_PATH_CTRL, (1 << 2) | /* core2 bypass */ @@ -5935,9 +5961,15 @@ int register_dv_functions(const struct dolby_vision_func_s *func) ("efuse_mode=%d reg_value = 0x%x\n", efuse_mode, reg_value); - if (is_meson_gxm() || - is_meson_g12()) + /* r321 stb core doesn't need run mode*/ + /*TV core need run mode and the value is 2*/ + if (is_meson_gxm() || is_meson_g12()) dolby_vision_run_mode_delay = 3; + else if (force_stb_mode || is_meson_txlx_stbmode()) + dolby_vision_run_mode_delay = 0; + else + dolby_vision_run_mode_delay = RUN_MODE_DELAY; + pq_config = vmalloc(sizeof(struct pq_config_s)); if (pq_config == NULL) { pr_info("[amdolby_vision] vmalloc failed for pq_config_s error!\n"); diff --git a/drivers/amlogic/media/enhancement/amvecm/Makefile b/drivers/amlogic/media/enhancement/amvecm/Makefile index 604487938597..894e0577cf94 100644 --- a/drivers/amlogic/media/enhancement/amvecm/Makefile +++ b/drivers/amlogic/media/enhancement/amvecm/Makefile @@ -3,5 +3,16 @@ # obj-$(CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_VECM) += am_vecm.o -am_vecm-objs := amve.o amcm.o amcsc.o amvecm.o keystone_correction.o bitdepth.o set_hdr2_v0.o dnlp_cal.o cm2_adj.o vlock.o - +am_vecm-objs := amve.o +am_vecm-objs += amcm.o +am_vecm-objs += amcsc.o +am_vecm-objs += amvecm.o +am_vecm-objs += keystone_correction.o +am_vecm-objs += bitdepth.o +am_vecm-objs += set_hdr2_v0.o +am_vecm-objs += dnlp_cal.o +am_vecm-objs += cm2_adj.o +am_vecm-objs += vlock.o +am_vecm-objs += hdr/am_hdr10_plus.o +am_vecm-objs += local_contrast.o +am_vecm-objs += amvecm_drm.o diff --git a/drivers/amlogic/media/enhancement/amvecm/amcm.c b/drivers/amlogic/media/enhancement/amvecm/amcm.c index 93337a942f6f..7a8ad4cf9f35 100644 --- a/drivers/amlogic/media/enhancement/amvecm/amcm.c +++ b/drivers/amlogic/media/enhancement/amvecm/amcm.c @@ -160,9 +160,15 @@ void am_set_regmap(struct am_regs_s *p) } if (!cm_en) { - if (p->am_reg[i].addr == 0x208) - p->am_reg[i].val = + if (p->am_reg[i].addr == 0x208) { + if (get_cpu_type() == + MESON_CPU_MAJOR_ID_TL1) + p->am_reg[i].val = + p->am_reg[i].val & 0xfffffffe; + else + p->am_reg[i].val = p->am_reg[i].val & 0xfffffffd; + } pr_amcm_dbg("[amcm]:%s REG_TYPE_INDEX_VPPCHROMA addr:0x%x", __func__, p->am_reg[i].addr); } else if (p->am_reg[i].addr == 0x208) { @@ -264,9 +270,20 @@ void amcm_disable(void) WRITE_VPP_REG(VPP_CHROMA_ADDR_PORT, 0x208); temp = READ_VPP_REG(VPP_CHROMA_DATA_PORT); - if (temp & 0x2) { - WRITE_VPP_REG(VPP_CHROMA_ADDR_PORT, 0x208); - WRITE_VPP_REG(VPP_CHROMA_DATA_PORT, temp & 0xfffffffd); + if (get_cpu_type() == MESON_CPU_MAJOR_ID_TL1) { + if (temp & 0x1) { + WRITE_VPP_REG(VPP_CHROMA_ADDR_PORT, + 0x208); + WRITE_VPP_REG(VPP_CHROMA_DATA_PORT, + temp & 0xfffffffe); + } + } else { + if (temp & 0x2) { + WRITE_VPP_REG(VPP_CHROMA_ADDR_PORT, + 0x208); + WRITE_VPP_REG(VPP_CHROMA_DATA_PORT, + temp & 0xfffffffd); + } } cm_en_flag = false; } @@ -279,9 +296,20 @@ void amcm_enable(void) WRITE_VPP_REG_BITS(VPP_MISC, 1, 28, 1); WRITE_VPP_REG(VPP_CHROMA_ADDR_PORT, 0x208); temp = READ_VPP_REG(VPP_CHROMA_DATA_PORT); - if (!(temp & 0x2)) { - WRITE_VPP_REG(VPP_CHROMA_ADDR_PORT, 0x208); - WRITE_VPP_REG(VPP_CHROMA_DATA_PORT, temp | 0x2); + if (get_cpu_type() == MESON_CPU_MAJOR_ID_TL1) { + if (!(temp & 0x1)) { + WRITE_VPP_REG(VPP_CHROMA_ADDR_PORT, + 0x208); + WRITE_VPP_REG(VPP_CHROMA_DATA_PORT, + temp | 0x1); + } + } else { + if (!(temp & 0x2)) { + WRITE_VPP_REG(VPP_CHROMA_ADDR_PORT, + 0x208); + WRITE_VPP_REG(VPP_CHROMA_DATA_PORT, + temp | 0x2); + } } cm_en_flag = true; } diff --git a/drivers/amlogic/media/enhancement/amvecm/amcsc.c b/drivers/amlogic/media/enhancement/amvecm/amcsc.c index b43eca609418..4b3792173d44 100644 --- a/drivers/amlogic/media/enhancement/amvecm/amcsc.c +++ b/drivers/amlogic/media/enhancement/amvecm/amcsc.c @@ -39,6 +39,7 @@ #include "amcsc.h" #include "set_hdr2_v0.h" #include +#include "hdr/am_hdr10_plus.h" #define pr_csc(fmt, args...)\ do {\ @@ -64,15 +65,15 @@ int is_hdr_cfg_osd_100(void) if (phdr) { if (phdr->hdr_cfg.en_osd_lut_100) - ret = 1; + ret = phdr->hdr_cfg.en_osd_lut_100; } return ret; } void hdr_set_cfg_osd_100(int val) { - if (val == 1) - phdr->hdr_cfg.en_osd_lut_100 = 1; + if (val > 0) + phdr->hdr_cfg.en_osd_lut_100 = val; else phdr->hdr_cfg.en_osd_lut_100 = 0; } @@ -323,6 +324,12 @@ static uint cur_hdr_process_mode = 2; /* 0: hdr->hdr, 1:hdr->sdr */ module_param(hdr_process_mode, uint, 0444); MODULE_PARM_DESC(hdr_process_mode, "\n current hdr_process_mode\n"); +static uint hdr10_plus_process_mode; /* 0: bypass, 1:hdr10p->sdr */ +static uint cur_hdr10_plus_process_mode = 2; /* 0: bypass, 1:hdr10p->sdr */ + +/* 0: tx don't support hdr10+, 1: tx support hdr10+*/ +static uint tx_hdr10_plus_support; + /* 0: hlg->hlg, 1:hlg->hdr*/ static uint hlg_process_mode = 1; /* 0: hdr->hdr, 1:hdr->sdr 2:hlg->hdr*/ @@ -1586,6 +1593,24 @@ static unsigned int osd_oetf_41_2084_mapping_100[OSD_OETF_LUT_SIZE] = { 523 }; +static unsigned int osd_eotf_33_709_mapping_290[EOTF_LUT_SIZE] = { + 0, 8, 37, 90, 169, 276, 412, 579, + 776, 1006, 1268, 1564, 1894, 2258, 2658, 3094, + 3566, 4075, 4621, 5204, 5826, 6486, 7185, 7923, + 8701, 9518, 10376, 11274, 12213, 13194, 14215, 15279, + 16384 +}; + +/* osd oetf lut: 2084 from baozheng */ +static unsigned int osd_oetf_41_2084_mapping_290[OSD_OETF_LUT_SIZE] = { + 0, 141, 178, 203, 221, 236, 249, 260, + 270, 325, 360, 386, 406, 423, 438, 451, + 462, 473, 482, 491, 499, 507, 514, 520, + 527, 532, 538, 543, 548, 553, 558, 562, + 567, 571, 575, 579, 583, 586, 590, 593, + 596 +}; + /* osd eotf lut: sdr->hlg */ static unsigned int osd_eotf_33_sdr2hlg_mapping[EOTF_LUT_SIZE] = { 0, 512, 1024, 1536, 2048, 2560, 3072, 3584, @@ -3361,6 +3386,7 @@ static struct vframe_master_display_colour_s cur_master_display_colour = { #define SIG_HLG_SUPPORT 0x100 #define SIG_OP_CHG 0x200 #define SIG_SRC_OUTPUT_CHG 0x400/*for box*/ +#define SIG_HDR10_PLUS_MODE 0x800 unsigned int pre_vd1_mtx_sel = VPP_MATRIX_NULL; module_param(pre_vd1_mtx_sel, uint, 0664); @@ -3606,6 +3632,12 @@ int signal_type_changed(struct vframe_s *vf, struct vinfo_s *vinfo) cur_hlg_support = vinfo->hdr_info.hdr_support & 0x8; } + if (cur_hdr10_plus_process_mode != hdr10_plus_process_mode) { + pr_csc("HDR10 plus mode changed.\n"); + change_flag |= SIG_HDR10_PLUS_MODE; + cur_hdr10_plus_process_mode = hdr10_plus_process_mode; + } + if ((cur_eye_protect_mode != wb_val[0]) || (cur_eye_protect_mode == 1)) { pr_csc(" eye protect mode changed.\n"); @@ -3638,7 +3670,7 @@ enum vpp_matrix_csc_e get_csc_type(void) else csc_type = VPP_MATRIX_YUV601F_RGB; } else if ((signal_color_primaries == 9) || - (signal_transfer_characteristic == 16)) { + (signal_transfer_characteristic >= 14)) { if (signal_transfer_characteristic == 16) { /* smpte st-2084 */ if (signal_color_primaries != 9) @@ -3659,6 +3691,9 @@ enum vpp_matrix_csc_e get_csc_type(void) /* bt2020-12 */ pr_csc("\tWARNING: HLG!!!\n"); csc_type = VPP_MATRIX_BT2020YUV_BT2020RGB; + } else if (signal_transfer_characteristic == 0x30) { + pr_csc("\tWARNING: HDR10 PLUS!!!\n"); + csc_type = VPP_MATRIX_BT2020YUV_BT2020RGB_DYNAMIC; } else { /* unknown transfer characteristic */ pr_csc("\tWARNING: unknown HDR!!!\n"); @@ -4390,13 +4425,18 @@ static int hdr_process( /*(VIU_OSD1_BLK0_CFG_W0,0, 7, 1); */ /* eotf lut 709 */ - if (is_hdr_cfg_osd_100()) { + if (is_hdr_cfg_osd_100() == 1) { set_vpp_lut(VPP_LUT_OSD_EOTF, osd_eotf_33_709_mapping_100, /* R */ osd_eotf_33_709_mapping_100, /* G */ osd_eotf_33_709_mapping_100, /* B */ CSC_ON); - + } else if ((is_hdr_cfg_osd_100() == 2)) { + set_vpp_lut(VPP_LUT_OSD_EOTF, + osd_eotf_33_709_mapping_290, /* R */ + osd_eotf_33_709_mapping_290, /* G */ + osd_eotf_33_709_mapping_290, /* B */ + CSC_ON); } else { set_vpp_lut(VPP_LUT_OSD_EOTF, osd_eotf_33_709_mapping, /* R */ @@ -4419,12 +4459,18 @@ static int hdr_process( CSC_ON); /* oetf lut 2084 */ - if (is_hdr_cfg_osd_100()) { + if (is_hdr_cfg_osd_100() == 1) { set_vpp_lut(VPP_LUT_OSD_OETF, osd_oetf_41_2084_mapping_100, /* R */ osd_oetf_41_2084_mapping_100, /* G */ osd_oetf_41_2084_mapping_100, /* B */ CSC_ON); + } else if (is_hdr_cfg_osd_100() == 2) { + set_vpp_lut(VPP_LUT_OSD_OETF, + osd_oetf_41_2084_mapping_290, /* R */ + osd_oetf_41_2084_mapping_290, /* G */ + osd_oetf_41_2084_mapping_290, /* B */ + CSC_ON); } else { set_vpp_lut(VPP_LUT_OSD_OETF, osd_oetf_41_2084_mapping, /* R */ @@ -4828,12 +4874,18 @@ static void bypass_hdr_process( osd_eotf_33_sdr2hlg_mapping, /* B */ CSC_ON); } else { - if (is_hdr_cfg_osd_100()) { + if (is_hdr_cfg_osd_100() == 1) { set_vpp_lut(VPP_LUT_OSD_EOTF, osd_eotf_33_709_mapping_100, osd_eotf_33_709_mapping_100, osd_eotf_33_709_mapping_100, CSC_ON); + } else if (is_hdr_cfg_osd_100() == 2) { + set_vpp_lut(VPP_LUT_OSD_EOTF, + osd_eotf_33_709_mapping_290, + osd_eotf_33_709_mapping_290, + osd_eotf_33_709_mapping_290, + CSC_ON); } else { set_vpp_lut(VPP_LUT_OSD_EOTF, osd_eotf_33_709_mapping, /*R*/ @@ -4881,12 +4933,18 @@ static void bypass_hdr_process( osd_oetf_41_sdr2hlg_mapping, /* B */ CSC_ON); } else { - if (is_hdr_cfg_osd_100()) { + if (is_hdr_cfg_osd_100() == 1) { set_vpp_lut(VPP_LUT_OSD_OETF, osd_oetf_41_2084_mapping_100, osd_oetf_41_2084_mapping_100, osd_oetf_41_2084_mapping_100, CSC_ON); + } else if (is_hdr_cfg_osd_100() == 2) { + set_vpp_lut(VPP_LUT_OSD_OETF, + osd_oetf_41_2084_mapping_290, + osd_oetf_41_2084_mapping_290, + osd_oetf_41_2084_mapping_290, + CSC_ON); } else { set_vpp_lut(VPP_LUT_OSD_OETF, osd_oetf_41_2084_mapping, @@ -5831,24 +5889,16 @@ static int vpp_eye_protection_process( return 0; } -static int vpp_matrix_update( - struct vframe_s *vf, struct vinfo_s *vinfo, int flags) +static void hdr_support_process(struct vinfo_s *vinfo) { - enum vpp_matrix_csc_e csc_type = VPP_MATRIX_NULL; - int signal_change_flag = 0; - struct vframe_master_display_colour_s *p = &cur_master_display_colour; - struct master_display_info_s send_info; - int need_adjust_contrast_saturation = 0; - int hdmi_scs_type_changed = 0; - struct vout_device_s *vdev = NULL; - - if (vinfo == NULL) - return 0; - if (vinfo->vout_device) - vdev = vinfo->vout_device; - /* Tx hdr information */ - memcpy(&receiver_hdr_info, &vinfo->hdr_info, - sizeof(struct hdr_info)); + /*check if hdmitx support hdr10+*/ + if ((vinfo->hdr_info.hdr10plus_info.ieeeoui + == HDR_PLUS_IEEE_OUI) && + (vinfo->hdr_info.hdr10plus_info.application_version + == 1)) + tx_hdr10_plus_support = 1; + else + tx_hdr10_plus_support = 0; /* check hdr support info from Tx or Panel */ if (hdr_mode == 2) { /* auto */ @@ -5873,9 +5923,15 @@ static int vpp_matrix_update( hdr_process_mode = 1; hlg_process_mode = 1; } + + if (tx_hdr10_plus_support) + hdr10_plus_process_mode = 0; + else + hdr10_plus_process_mode = 1; } else if (hdr_mode == 1) { hdr_process_mode = 1; hlg_process_mode = 1; + hdr10_plus_process_mode = 1; } else { hdr_process_mode = 0; if (vinfo->hdr_info.hdr_support & HDR_SUPPORT) { @@ -5886,6 +5942,8 @@ static int vpp_matrix_update( hlg_process_mode = 1; } else hlg_process_mode = 0; + + hdr10_plus_process_mode = 0; } if (sdr_mode == 2) { /* auto */ @@ -5904,18 +5962,44 @@ static int vpp_matrix_update( } else sdr_process_mode = sdr_mode; /* force sdr->hdr */ - if (vf && vinfo) - signal_change_flag = signal_type_changed(vf, vinfo); +} - if (force_csc_type != 0xff) - csc_type = force_csc_type; - else - csc_type = get_csc_type(); +static void hdr10_plus_metadata_update(struct vframe_s *vf, + enum vpp_matrix_csc_e csc_type, + struct hdr10plus_para *hdmitx_hdr10plus_param) +{ + if (!vf) + return; + if (csc_type != VPP_MATRIX_BT2020YUV_BT2020RGB_DYNAMIC) + return; + + hdr10_plus_parser_metadata(vf); + + if (tx_hdr10_plus_support) + hdr10_plus_hdmitx_vsif_parser(hdmitx_hdr10plus_param); +} + +static void hdr_tx_pkt_cb( + struct vinfo_s *vinfo, + int signal_change_flag, + enum vpp_matrix_csc_e csc_type, + struct vframe_master_display_colour_s *p, + int *hdmi_scs_type_changed, + struct hdr10plus_para *hdmitx_hdr10plus_param) +{ + struct vout_device_s *vdev = NULL; + struct master_display_info_s send_info; + + if (vinfo->vout_device) + vdev = vinfo->vout_device; if ((vinfo->viu_color_fmt != COLOR_FMT_RGB444) && ((vinfo->hdr_info.hdr_support & 0xc) || (signal_change_flag & SIG_HDR_SUPPORT) || - (signal_change_flag & SIG_HLG_SUPPORT))) { + (signal_change_flag & SIG_HLG_SUPPORT) || + /*hdr10 plus*/ + (tx_hdr10_plus_support) || + (signal_change_flag & SIG_HDR10_PLUS_MODE))) { if (sdr_process_mode && (csc_type < VPP_MATRIX_BT2020YUV_BT2020RGB)) { /* sdr source convert to hdr */ @@ -5937,11 +6021,11 @@ static int vpp_matrix_update( } if (hdmi_csc_type != VPP_MATRIX_BT2020YUV_BT2020RGB) { hdmi_csc_type = VPP_MATRIX_BT2020YUV_BT2020RGB; - hdmi_scs_type_changed = 1; + *hdmi_scs_type_changed = 1; } } else if ((hdr_process_mode == 0) && (hlg_process_mode == 0) && - (csc_type >= VPP_MATRIX_BT2020YUV_BT2020RGB)) { + (csc_type == VPP_MATRIX_BT2020YUV_BT2020RGB)) { /* source is hdr, send hdr info */ /* use the features to discribe source info */ send_info.features = @@ -5962,11 +6046,11 @@ static int vpp_matrix_update( } if (hdmi_csc_type != VPP_MATRIX_BT2020YUV_BT2020RGB) { hdmi_csc_type = VPP_MATRIX_BT2020YUV_BT2020RGB; - hdmi_scs_type_changed = 1; + *hdmi_scs_type_changed = 1; } } else if ((hdr_process_mode == 0) && (hlg_process_mode == 1) && - (csc_type >= VPP_MATRIX_BT2020YUV_BT2020RGB)) { + (csc_type == VPP_MATRIX_BT2020YUV_BT2020RGB)) { /* source is hdr, send hdr info */ /* use the features to discribe source info */ if (get_hdr_type() & HLG_FLAG) @@ -6000,11 +6084,11 @@ static int vpp_matrix_update( } if (hdmi_csc_type != VPP_MATRIX_BT2020YUV_BT2020RGB) { hdmi_csc_type = VPP_MATRIX_BT2020YUV_BT2020RGB; - hdmi_scs_type_changed = 1; + *hdmi_scs_type_changed = 1; } } else if ((hdr_process_mode == 1) && (hlg_process_mode == 0) && - (csc_type >= VPP_MATRIX_BT2020YUV_BT2020RGB)) { + (csc_type == VPP_MATRIX_BT2020YUV_BT2020RGB)) { /* source is hdr, send hdr info */ /* use the features to discribe source info */ if (get_hdr_type() & HLG_FLAG) @@ -6037,7 +6121,15 @@ static int vpp_matrix_update( } if (hdmi_csc_type != VPP_MATRIX_BT2020YUV_BT2020RGB) { hdmi_csc_type = VPP_MATRIX_BT2020YUV_BT2020RGB; - hdmi_scs_type_changed = 1; + *hdmi_scs_type_changed = 1; + } + } else if ((hdr10_plus_process_mode == 0) && + (csc_type == VPP_MATRIX_BT2020YUV_BT2020RGB_DYNAMIC)) { + /*source is hdr10 plus, send hdr10 plus info*/ + if (vdev) { + if (vdev->fresh_tx_hdr10plus_pkt) + vdev->fresh_tx_hdr10plus_pkt(1, + hdmitx_hdr10plus_param); } } else { /* sdr source send normal info*/ @@ -6068,16 +6160,255 @@ static int vpp_matrix_update( | (1 << 8) /* bt709 */ | (1 << 0); /* bt709 */ amvecm_cp_hdr_info(&send_info, p); - if (vdev) { - if (vdev->fresh_tx_hdr_pkt) - vdev->fresh_tx_hdr_pkt(&send_info); + if (cur_csc_type <= VPP_MATRIX_BT2020YUV_BT2020RGB) { + if (vdev) { + if (vdev->fresh_tx_hdr_pkt) + vdev->fresh_tx_hdr_pkt( + &send_info); + } + } else if (cur_csc_type == + VPP_MATRIX_BT2020YUV_BT2020RGB_DYNAMIC) + if (vdev) { + if (vdev->fresh_tx_hdr10plus_pkt) + vdev->fresh_tx_hdr10plus_pkt(0, + hdmitx_hdr10plus_param); } + if (hdmi_csc_type != VPP_MATRIX_YUV709_RGB) { hdmi_csc_type = VPP_MATRIX_YUV709_RGB; - hdmi_scs_type_changed = 1; + *hdmi_scs_type_changed = 1; } } } +} + +static void video_process( + struct vframe_s *vf, + enum vpp_matrix_csc_e csc_type, + int signal_change_flag, + struct vinfo_s *vinfo, + struct vframe_master_display_colour_s *p) +{ + int need_adjust_contrast_saturation = 0; + + /* decided by edid or panel info or user setting */ + if ((csc_type == VPP_MATRIX_BT2020YUV_BT2020RGB) && + (hdr_process_mode == 1) && + (hlg_process_mode == 1)) { + /* hdr->sdr hlg->sdr */ + if ((signal_change_flag & + (SIG_CS_CHG | + SIG_PRI_INFO | + SIG_KNEE_FACTOR | + SIG_HDR_MODE | + SIG_HDR_SUPPORT | + SIG_HLG_MODE) + ) || + (cur_csc_type < + VPP_MATRIX_BT2020YUV_BT2020RGB)) { + if (get_hdr_type() & HLG_FLAG) + need_adjust_contrast_saturation = + hlg_process(csc_type, vinfo, p); + else + need_adjust_contrast_saturation + = hdr_process(csc_type, vinfo, p); + pr_csc("hdr_process_mode = 0x%x\n" + "hlg_process_mode = 0x%x.\n", + hdr_process_mode, hlg_process_mode); + } + } else if ((csc_type == VPP_MATRIX_BT2020YUV_BT2020RGB) && + (hdr_process_mode == 0) && + (hlg_process_mode == 1)) { + /* hdr->hdr hlg->hlg*/ + if ((signal_change_flag & + (SIG_CS_CHG | + SIG_PRI_INFO | + SIG_KNEE_FACTOR | + SIG_HDR_MODE | + SIG_HDR_SUPPORT | + SIG_HLG_MODE) + ) || + (cur_csc_type < + VPP_MATRIX_BT2020YUV_BT2020RGB)) { + if (get_hdr_type() & HLG_FLAG) + hlg_hdr_process(csc_type, vinfo, p); + else + bypass_hdr_process(csc_type, vinfo, p); + pr_csc("hdr_process_mode = 0x%x\n" + "hlg_process_mode = 0x%x.\n", + hdr_process_mode, hlg_process_mode); + } + } else if ((csc_type == VPP_MATRIX_BT2020YUV_BT2020RGB) && + (hdr_process_mode == 1) && (hlg_process_mode == 0)) { + /* hdr->sdr hlg->hlg*/ + if ((signal_change_flag & + (SIG_CS_CHG | + SIG_PRI_INFO | + SIG_KNEE_FACTOR | + SIG_HDR_MODE | + SIG_HDR_SUPPORT | + SIG_HLG_MODE) + ) || + (cur_csc_type < + VPP_MATRIX_BT2020YUV_BT2020RGB)) { + if (get_hdr_type() & HLG_FLAG) + bypass_hdr_process(csc_type, vinfo, p); + else + need_adjust_contrast_saturation = + hdr_process(csc_type, vinfo, p); + pr_csc("hdr_process_mode = 0x%x\n" + "hlg_process_mode = 0x%x.\n", + hdr_process_mode, hlg_process_mode); + } + } else if ((csc_type == VPP_MATRIX_BT2020YUV_BT2020RGB) && + (hdr_process_mode == 0) && (hlg_process_mode == 0)) { + /* hdr->hdr hlg->hlg*/ + if ((signal_change_flag & + (SIG_CS_CHG | + SIG_PRI_INFO | + SIG_KNEE_FACTOR | + SIG_HDR_MODE | + SIG_HDR_SUPPORT | + SIG_HLG_MODE)) || + (cur_csc_type < + VPP_MATRIX_BT2020YUV_BT2020RGB)) { + bypass_hdr_process(csc_type, vinfo, p); + pr_csc("bypass_hdr_process: 0x%x, 0x%x.\n", + hdr_process_mode, hlg_process_mode); + } + } else if ((csc_type == VPP_MATRIX_BT2020YUV_BT2020RGB_DYNAMIC) && + (hdr10_plus_process_mode == 1)) { + if ((signal_change_flag & SIG_HDR10_PLUS_MODE) || + (cur_csc_type != + VPP_MATRIX_BT2020YUV_BT2020RGB_DYNAMIC)) + hdr10_plus_process(vf); + pr_csc("hdr10_plus_process.\n"); + } else { + if ((csc_type < VPP_MATRIX_BT2020YUV_BT2020RGB) && + sdr_process_mode) + /* for gxl and gxm SDR to HDR process */ + sdr_hdr_process(csc_type, vinfo, p); + else { + /* for gxtvbb and gxl HDR bypass process */ + if (((vinfo->hdr_info.hdr_support & + HDR_SUPPORT) || + (vinfo->hdr_info.hdr_support & + HLG_SUPPORT)) && + (csc_type < + VPP_MATRIX_BT2020YUV_BT2020RGB) + && tx_op_color_primary) + set_bt2020csc_process(csc_type, + vinfo, p); + else + bypass_hdr_process(csc_type, + vinfo, p); + pr_csc("csc_type = 0x%x\n" + "sdr_process_mode = 0x%x.\n", + csc_type, sdr_process_mode); + } + } + + if (get_cpu_type() >= MESON_CPU_MAJOR_ID_G12A) { + if (vinfo->viu_color_fmt != COLOR_FMT_RGB444) + mtx_setting(POST2_MTX, MATRIX_NULL, MTX_OFF); + else + mtx_setting(POST2_MTX, + MATRIX_YUV709_RGB, MTX_ON); + } + + if (cur_hdr_process_mode != hdr_process_mode) { + cur_hdr_process_mode = hdr_process_mode; + pr_csc("hdr_process_mode changed to %d", + hdr_process_mode); + } + if (cur_sdr_process_mode != sdr_process_mode) { + cur_sdr_process_mode = sdr_process_mode; + pr_csc("sdr_process_mode changed to %d", + sdr_process_mode); + } + if (cur_hlg_process_mode != hlg_process_mode) { + cur_hlg_process_mode = hlg_process_mode; + pr_csc("hlg_process_mode changed to %d", + hlg_process_mode); + } + if (need_adjust_contrast_saturation & 1) { + if (lut_289_en && + (get_cpu_type() <= MESON_CPU_MAJOR_ID_GXTVBB)) + vd1_contrast_offset = 0; + else + vd1_contrast_offset = + calculate_contrast_adj(p->luminance[0] / 10000); + vecm_latch_flag |= FLAG_VADJ1_CON; + } else { + vd1_contrast_offset = 0; + vecm_latch_flag |= FLAG_VADJ1_CON; + } + if (need_adjust_contrast_saturation & 2) { + vecm_latch_flag |= FLAG_VADJ1_COLOR; + } else { + if (((get_cpu_type() == MESON_CPU_MAJOR_ID_GXTVBB) || + (get_cpu_type() == MESON_CPU_MAJOR_ID_TXL)) && + (sdr_process_mode == 1)) + saturation_offset = sdr_saturation_offset; + else + saturation_offset = 0; + vecm_latch_flag |= FLAG_VADJ1_COLOR; + } + if (cur_csc_type != csc_type) { + pr_csc("CSC from 0x%x to 0x%x.\n", + cur_csc_type, csc_type); + pr_csc("contrast offset = %d.\n", + vd1_contrast_offset); + pr_csc("saturation offset = %d.\n", + saturation_offset); + cur_csc_type = csc_type; + + if (vf) { + if ((cur_csc_type == VPP_MATRIX_BT2020YUV_BT2020RGB) && + (cur_csc_type != 0xffff) && + (vf->source_type == VFRAME_SOURCE_TYPE_HDMI)) { + amvecm_wakeup_queue(); + pr_csc("wake up hdr status queue.\n"); + } + } + } +} + +static int vpp_matrix_update( + struct vframe_s *vf, struct vinfo_s *vinfo, int flags) +{ + enum vpp_matrix_csc_e csc_type = VPP_MATRIX_NULL; + int signal_change_flag = 0; + struct vframe_master_display_colour_s *p = &cur_master_display_colour; + int hdmi_scs_type_changed = 0; + struct hdr10plus_para hdmitx_hdr10plus_param; + + if (vinfo == NULL) + return 0; + + /* Tx hdr information */ + memcpy(&receiver_hdr_info, &vinfo->hdr_info, + sizeof(struct hdr_info)); + + hdr_support_process(vinfo); + + if (vf && vinfo) + signal_change_flag = signal_type_changed(vf, vinfo); + + if (force_csc_type != 0xff) + csc_type = force_csc_type; + else + csc_type = get_csc_type(); + + hdr10_plus_metadata_update(vf, csc_type, + &hdmitx_hdr10plus_param); + + hdr_tx_pkt_cb(vinfo, + signal_change_flag, + csc_type, + p, + &hdmi_scs_type_changed, + &hdmitx_hdr10plus_param); if (hdmi_scs_type_changed && (flags & CSC_FLAG_CHECK_OUTPUT) && @@ -6088,192 +6419,17 @@ static int vpp_matrix_update( && ((flags & CSC_FLAG_TOGGLE_FRAME) == 0)) return 0; - vecm_latch_flag |= FLAG_MATRIX_UPDATE; - if ((cur_csc_type != csc_type) || (signal_change_flag & (SIG_CS_CHG | SIG_PRI_INFO | SIG_KNEE_FACTOR | SIG_HDR_MODE | SIG_HDR_SUPPORT | SIG_HLG_MODE | SIG_OP_CHG | - SIG_SRC_OUTPUT_CHG))) { - /* decided by edid or panel info or user setting */ - if ((csc_type == VPP_MATRIX_BT2020YUV_BT2020RGB) && - (hdr_process_mode == 1) && - (hlg_process_mode == 1)) { - /* hdr->sdr hlg->sdr */ - if ((signal_change_flag & - (SIG_CS_CHG | - SIG_PRI_INFO | - SIG_KNEE_FACTOR | - SIG_HDR_MODE | - SIG_HDR_SUPPORT | - SIG_HLG_MODE) - ) || - (cur_csc_type < - VPP_MATRIX_BT2020YUV_BT2020RGB)) { - if (get_hdr_type() & HLG_FLAG) - need_adjust_contrast_saturation = - hlg_process(csc_type, vinfo, p); - else - need_adjust_contrast_saturation - = hdr_process(csc_type, vinfo, p); - pr_csc("hdr_process_mode = 0x%x\n" - "hlg_process_mode = 0x%x.\n", - hdr_process_mode, hlg_process_mode); - } - } else if ((csc_type == VPP_MATRIX_BT2020YUV_BT2020RGB) && - (hdr_process_mode == 0) && - (hlg_process_mode == 1)) { - /* hdr->hdr hlg->hlg*/ - if ((signal_change_flag & - (SIG_CS_CHG | - SIG_PRI_INFO | - SIG_KNEE_FACTOR | - SIG_HDR_MODE | - SIG_HDR_SUPPORT | - SIG_HLG_MODE) - ) || - (cur_csc_type < - VPP_MATRIX_BT2020YUV_BT2020RGB)) { - if (get_hdr_type() & HLG_FLAG) - hlg_hdr_process(csc_type, vinfo, p); - else - bypass_hdr_process(csc_type, vinfo, p); - pr_csc("hdr_process_mode = 0x%x\n" - "hlg_process_mode = 0x%x.\n", - hdr_process_mode, hlg_process_mode); - } - } else if ((csc_type == VPP_MATRIX_BT2020YUV_BT2020RGB) && - (hdr_process_mode == 1) && (hlg_process_mode == 0)) { - /* hdr->sdr hlg->hlg*/ - if ((signal_change_flag & - (SIG_CS_CHG | - SIG_PRI_INFO | - SIG_KNEE_FACTOR | - SIG_HDR_MODE | - SIG_HDR_SUPPORT | - SIG_HLG_MODE) - ) || - (cur_csc_type < - VPP_MATRIX_BT2020YUV_BT2020RGB)) { - if (get_hdr_type() & HLG_FLAG) - bypass_hdr_process(csc_type, vinfo, p); - else - need_adjust_contrast_saturation = - hdr_process(csc_type, vinfo, p); - pr_csc("hdr_process_mode = 0x%x\n" - "hlg_process_mode = 0x%x.\n", - hdr_process_mode, hlg_process_mode); - } - } else if ((csc_type == VPP_MATRIX_BT2020YUV_BT2020RGB) && - (hdr_process_mode == 0) && (hlg_process_mode == 0)) { - /* hdr->hdr hlg->hlg*/ - if ((signal_change_flag & - (SIG_CS_CHG | - SIG_PRI_INFO | - SIG_KNEE_FACTOR | - SIG_HDR_MODE | - SIG_HDR_SUPPORT | - SIG_HLG_MODE)) || - (cur_csc_type < - VPP_MATRIX_BT2020YUV_BT2020RGB)) { - bypass_hdr_process(csc_type, vinfo, p); - pr_csc("bypass_hdr_process: 0x%x, 0x%x.\n", - hdr_process_mode, hlg_process_mode); - } - } else { - if ((csc_type < VPP_MATRIX_BT2020YUV_BT2020RGB) && - sdr_process_mode) - /* for gxl and gxm SDR to HDR process */ - sdr_hdr_process(csc_type, vinfo, p); - else { - /* for gxtvbb and gxl HDR bypass process */ - if (((vinfo->hdr_info.hdr_support & - HDR_SUPPORT) || - (vinfo->hdr_info.hdr_support & - HLG_SUPPORT)) && - (csc_type < - VPP_MATRIX_BT2020YUV_BT2020RGB) - && tx_op_color_primary) - set_bt2020csc_process(csc_type, - vinfo, p); - else - bypass_hdr_process(csc_type, - vinfo, p); - pr_csc("csc_type = 0x%x\n" - "sdr_process_mode = 0x%x.\n", - csc_type, sdr_process_mode); - } - } - - if (get_cpu_type() >= MESON_CPU_MAJOR_ID_G12A) { - if (vinfo->viu_color_fmt != COLOR_FMT_RGB444) - mtx_setting(POST2_MTX, MATRIX_NULL, MTX_OFF); - else - mtx_setting(POST2_MTX, - MATRIX_YUV709_RGB, MTX_ON); - } - - if (cur_hdr_process_mode != hdr_process_mode) { - cur_hdr_process_mode = hdr_process_mode; - pr_csc("hdr_process_mode changed to %d", - hdr_process_mode); - } - if (cur_sdr_process_mode != sdr_process_mode) { - cur_sdr_process_mode = sdr_process_mode; - pr_csc("sdr_process_mode changed to %d", - sdr_process_mode); - } - if (cur_hlg_process_mode != hlg_process_mode) { - cur_hlg_process_mode = hlg_process_mode; - pr_csc("hlg_process_mode changed to %d", - hlg_process_mode); - } - if (need_adjust_contrast_saturation & 1) { - if (lut_289_en && - (get_cpu_type() <= MESON_CPU_MAJOR_ID_GXTVBB)) - vd1_contrast_offset = 0; - else - vd1_contrast_offset = - calculate_contrast_adj(p->luminance[0] / 10000); - vecm_latch_flag |= FLAG_VADJ1_CON; - } else { - vd1_contrast_offset = 0; - vecm_latch_flag |= FLAG_VADJ1_CON; - } - if (need_adjust_contrast_saturation & 2) { - vecm_latch_flag |= FLAG_VADJ1_COLOR; - } else { - if (((get_cpu_type() == MESON_CPU_MAJOR_ID_GXTVBB) || - (get_cpu_type() == MESON_CPU_MAJOR_ID_TXL)) && - (sdr_process_mode == 1)) - saturation_offset = sdr_saturation_offset; - else - saturation_offset = 0; - vecm_latch_flag |= FLAG_VADJ1_COLOR; - } - if (cur_csc_type != csc_type) { - pr_csc("CSC from 0x%x to 0x%x.\n", - cur_csc_type, csc_type); - pr_csc("contrast offset = %d.\n", - vd1_contrast_offset); - pr_csc("saturation offset = %d.\n", - saturation_offset); - cur_csc_type = csc_type; - - if ((cur_csc_type >= VPP_MATRIX_BT2020YUV_BT2020RGB) && - (cur_csc_type != 0xffff) && - (vf->source_type == VFRAME_SOURCE_TYPE_HDMI)) { - amvecm_wakeup_queue(); - pr_csc("wake up hdr status queue.\n"); - } - } - } + SIG_SRC_OUTPUT_CHG | SIG_HDR10_PLUS_MODE))) + video_process(vf, csc_type, signal_change_flag, vinfo, p); /* eye protection mode */ if (signal_change_flag & SIG_WB_CHG) vpp_eye_protection_process(csc_type, vinfo); - vecm_latch_flag &= ~FLAG_MATRIX_UPDATE; return 0; } @@ -6534,6 +6690,13 @@ hdr_dump: pr_err("knee_lut_on:0x%x,knee_interpolation_mode:0x%x,cur_knee_factor:0x%x\n", knee_lut_on, knee_interpolation_mode, cur_knee_factor); + pr_err("tx_hdr10_plus_support = 0x%x\n", tx_hdr10_plus_support); + pr_err("hdr10_plus_process_mode = 0x%x\n", hdr10_plus_process_mode); + + //if (signal_transfer_characteristic == 0x30) + if (cur_csc_type == VPP_MATRIX_BT2020YUV_BT2020RGB_DYNAMIC) + hdr10_plus_debug(); + if ((receiver_hdr_info.hdr_support & 0xc) == 0) goto dbg_end; pr_err("----TV EDID info----\n"); diff --git a/drivers/amlogic/media/enhancement/amvecm/amve.c b/drivers/amlogic/media/enhancement/amvecm/amve.c index 469c692d92b0..e87b26a6f059 100644 --- a/drivers/amlogic/media/enhancement/amvecm/amve.c +++ b/drivers/amlogic/media/enhancement/amvecm/amve.c @@ -76,6 +76,8 @@ struct tcon_gamma_table_s video_gamma_table_b; struct tcon_gamma_table_s video_gamma_table_r_adj; struct tcon_gamma_table_s video_gamma_table_g_adj; struct tcon_gamma_table_s video_gamma_table_b_adj; +struct tcon_gamma_table_s video_gamma_table_ioctl_set; + struct tcon_rgb_ogo_s video_rgb_ogo = { 0, /* wb enable */ 0, /* -1024~1023, r_pre_offset */ @@ -174,118 +176,52 @@ void ve_hist_gamma_reset(void) void ve_dnlp_load_reg(void) { + int i; + if (dnlp_sel == NEW_DNLP_IN_SHARPNESS) { if (is_meson_gxlx_cpu() || is_meson_txlx_cpu()) { - WRITE_VPP_REG(SRSHARP1_DNLP_00, ve_dnlp_reg[0]); - WRITE_VPP_REG(SRSHARP1_DNLP_01, ve_dnlp_reg[1]); - WRITE_VPP_REG(SRSHARP1_DNLP_02, ve_dnlp_reg[2]); - WRITE_VPP_REG(SRSHARP1_DNLP_03, ve_dnlp_reg[3]); - WRITE_VPP_REG(SRSHARP1_DNLP_04, ve_dnlp_reg[4]); - WRITE_VPP_REG(SRSHARP1_DNLP_05, ve_dnlp_reg[5]); - WRITE_VPP_REG(SRSHARP1_DNLP_06, ve_dnlp_reg[6]); - WRITE_VPP_REG(SRSHARP1_DNLP_07, ve_dnlp_reg[7]); - WRITE_VPP_REG(SRSHARP1_DNLP_08, ve_dnlp_reg[8]); - WRITE_VPP_REG(SRSHARP1_DNLP_09, ve_dnlp_reg[9]); - WRITE_VPP_REG(SRSHARP1_DNLP_10, ve_dnlp_reg[10]); - WRITE_VPP_REG(SRSHARP1_DNLP_11, ve_dnlp_reg[11]); - WRITE_VPP_REG(SRSHARP1_DNLP_12, ve_dnlp_reg[12]); - WRITE_VPP_REG(SRSHARP1_DNLP_13, ve_dnlp_reg[13]); - WRITE_VPP_REG(SRSHARP1_DNLP_14, ve_dnlp_reg[14]); - WRITE_VPP_REG(SRSHARP1_DNLP_15, ve_dnlp_reg[15]); + for (i = 0; i < 16; i++) + WRITE_VPP_REG(SRSHARP1_DNLP_00 + i, + ve_dnlp_reg[i]); + } else if (is_meson_tl1_cpu()) { + for (i = 0; i < 32; i++) + WRITE_VPP_REG(SHARP1_DNLP_00 + i, + ve_dnlp_reg_v2[i]); } else { - WRITE_VPP_REG(SRSHARP0_DNLP_00, ve_dnlp_reg[0]); - WRITE_VPP_REG(SRSHARP0_DNLP_01, ve_dnlp_reg[1]); - WRITE_VPP_REG(SRSHARP0_DNLP_02, ve_dnlp_reg[2]); - WRITE_VPP_REG(SRSHARP0_DNLP_03, ve_dnlp_reg[3]); - WRITE_VPP_REG(SRSHARP0_DNLP_04, ve_dnlp_reg[4]); - WRITE_VPP_REG(SRSHARP0_DNLP_05, ve_dnlp_reg[5]); - WRITE_VPP_REG(SRSHARP0_DNLP_06, ve_dnlp_reg[6]); - WRITE_VPP_REG(SRSHARP0_DNLP_07, ve_dnlp_reg[7]); - WRITE_VPP_REG(SRSHARP0_DNLP_08, ve_dnlp_reg[8]); - WRITE_VPP_REG(SRSHARP0_DNLP_09, ve_dnlp_reg[9]); - WRITE_VPP_REG(SRSHARP0_DNLP_10, ve_dnlp_reg[10]); - WRITE_VPP_REG(SRSHARP0_DNLP_11, ve_dnlp_reg[11]); - WRITE_VPP_REG(SRSHARP0_DNLP_12, ve_dnlp_reg[12]); - WRITE_VPP_REG(SRSHARP0_DNLP_13, ve_dnlp_reg[13]); - WRITE_VPP_REG(SRSHARP0_DNLP_14, ve_dnlp_reg[14]); - WRITE_VPP_REG(SRSHARP0_DNLP_15, ve_dnlp_reg[15]); + for (i = 0; i < 16; i++) + WRITE_VPP_REG(SRSHARP0_DNLP_00 + i, + ve_dnlp_reg[i]); } } else { - /* #endif */ - WRITE_VPP_REG(VPP_DNLP_CTRL_00, ve_dnlp_reg[0]); - WRITE_VPP_REG(VPP_DNLP_CTRL_01, ve_dnlp_reg[1]); - WRITE_VPP_REG(VPP_DNLP_CTRL_02, ve_dnlp_reg[2]); - WRITE_VPP_REG(VPP_DNLP_CTRL_03, ve_dnlp_reg[3]); - WRITE_VPP_REG(VPP_DNLP_CTRL_04, ve_dnlp_reg[4]); - WRITE_VPP_REG(VPP_DNLP_CTRL_05, ve_dnlp_reg[5]); - WRITE_VPP_REG(VPP_DNLP_CTRL_06, ve_dnlp_reg[6]); - WRITE_VPP_REG(VPP_DNLP_CTRL_07, ve_dnlp_reg[7]); - WRITE_VPP_REG(VPP_DNLP_CTRL_08, ve_dnlp_reg[8]); - WRITE_VPP_REG(VPP_DNLP_CTRL_09, ve_dnlp_reg[9]); - WRITE_VPP_REG(VPP_DNLP_CTRL_10, ve_dnlp_reg[10]); - WRITE_VPP_REG(VPP_DNLP_CTRL_11, ve_dnlp_reg[11]); - WRITE_VPP_REG(VPP_DNLP_CTRL_12, ve_dnlp_reg[12]); - WRITE_VPP_REG(VPP_DNLP_CTRL_13, ve_dnlp_reg[13]); - WRITE_VPP_REG(VPP_DNLP_CTRL_14, ve_dnlp_reg[14]); - WRITE_VPP_REG(VPP_DNLP_CTRL_15, ve_dnlp_reg[15]); + for (i = 0; i < 16; i++) + WRITE_VPP_REG(VPP_DNLP_CTRL_00 + i, + ve_dnlp_reg[i]); } + } static void ve_dnlp_load_def_reg(void) { + int i; + if (dnlp_sel == NEW_DNLP_IN_SHARPNESS) { if (is_meson_gxlx_cpu() || is_meson_txlx_cpu()) { - WRITE_VPP_REG(SRSHARP1_DNLP_00, ve_dnlp_reg[0]); - WRITE_VPP_REG(SRSHARP1_DNLP_01, ve_dnlp_reg[1]); - WRITE_VPP_REG(SRSHARP1_DNLP_02, ve_dnlp_reg[2]); - WRITE_VPP_REG(SRSHARP1_DNLP_03, ve_dnlp_reg[3]); - WRITE_VPP_REG(SRSHARP1_DNLP_04, ve_dnlp_reg[4]); - WRITE_VPP_REG(SRSHARP1_DNLP_05, ve_dnlp_reg[5]); - WRITE_VPP_REG(SRSHARP1_DNLP_06, ve_dnlp_reg[6]); - WRITE_VPP_REG(SRSHARP1_DNLP_07, ve_dnlp_reg[7]); - WRITE_VPP_REG(SRSHARP1_DNLP_08, ve_dnlp_reg[8]); - WRITE_VPP_REG(SRSHARP1_DNLP_09, ve_dnlp_reg[9]); - WRITE_VPP_REG(SRSHARP1_DNLP_10, ve_dnlp_reg[10]); - WRITE_VPP_REG(SRSHARP1_DNLP_11, ve_dnlp_reg[11]); - WRITE_VPP_REG(SRSHARP1_DNLP_12, ve_dnlp_reg[12]); - WRITE_VPP_REG(SRSHARP1_DNLP_13, ve_dnlp_reg[13]); - WRITE_VPP_REG(SRSHARP1_DNLP_14, ve_dnlp_reg[14]); - WRITE_VPP_REG(SRSHARP1_DNLP_15, ve_dnlp_reg[15]); + for (i = 0; i < 16; i++) + WRITE_VPP_REG(SRSHARP1_DNLP_00 + i, + ve_dnlp_reg[i]); + } else if (is_meson_tl1_cpu()) { + for (i = 0; i < 32; i++) + WRITE_VPP_REG(SHARP1_DNLP_00 + i, + ve_dnlp_reg_v2[i]); } else { - WRITE_VPP_REG(SRSHARP0_DNLP_00, ve_dnlp_reg[0]); - WRITE_VPP_REG(SRSHARP0_DNLP_01, ve_dnlp_reg[1]); - WRITE_VPP_REG(SRSHARP0_DNLP_02, ve_dnlp_reg[2]); - WRITE_VPP_REG(SRSHARP0_DNLP_03, ve_dnlp_reg[3]); - WRITE_VPP_REG(SRSHARP0_DNLP_04, ve_dnlp_reg[4]); - WRITE_VPP_REG(SRSHARP0_DNLP_05, ve_dnlp_reg[5]); - WRITE_VPP_REG(SRSHARP0_DNLP_06, ve_dnlp_reg[6]); - WRITE_VPP_REG(SRSHARP0_DNLP_07, ve_dnlp_reg[7]); - WRITE_VPP_REG(SRSHARP0_DNLP_08, ve_dnlp_reg[8]); - WRITE_VPP_REG(SRSHARP0_DNLP_09, ve_dnlp_reg[9]); - WRITE_VPP_REG(SRSHARP0_DNLP_10, ve_dnlp_reg[10]); - WRITE_VPP_REG(SRSHARP0_DNLP_11, ve_dnlp_reg[11]); - WRITE_VPP_REG(SRSHARP0_DNLP_12, ve_dnlp_reg[12]); - WRITE_VPP_REG(SRSHARP0_DNLP_13, ve_dnlp_reg[13]); - WRITE_VPP_REG(SRSHARP0_DNLP_14, ve_dnlp_reg[14]); - WRITE_VPP_REG(SRSHARP0_DNLP_15, ve_dnlp_reg[15]); + for (i = 0; i < 16; i++) + WRITE_VPP_REG(SRSHARP0_DNLP_00 + i, + ve_dnlp_reg[i]); } } else { - WRITE_VPP_REG(VPP_DNLP_CTRL_00, ve_dnlp_reg_def[0]); - WRITE_VPP_REG(VPP_DNLP_CTRL_01, ve_dnlp_reg_def[1]); - WRITE_VPP_REG(VPP_DNLP_CTRL_02, ve_dnlp_reg_def[2]); - WRITE_VPP_REG(VPP_DNLP_CTRL_03, ve_dnlp_reg_def[3]); - WRITE_VPP_REG(VPP_DNLP_CTRL_04, ve_dnlp_reg_def[4]); - WRITE_VPP_REG(VPP_DNLP_CTRL_05, ve_dnlp_reg_def[5]); - WRITE_VPP_REG(VPP_DNLP_CTRL_06, ve_dnlp_reg_def[6]); - WRITE_VPP_REG(VPP_DNLP_CTRL_07, ve_dnlp_reg_def[7]); - WRITE_VPP_REG(VPP_DNLP_CTRL_08, ve_dnlp_reg_def[8]); - WRITE_VPP_REG(VPP_DNLP_CTRL_09, ve_dnlp_reg_def[9]); - WRITE_VPP_REG(VPP_DNLP_CTRL_10, ve_dnlp_reg_def[10]); - WRITE_VPP_REG(VPP_DNLP_CTRL_11, ve_dnlp_reg_def[11]); - WRITE_VPP_REG(VPP_DNLP_CTRL_12, ve_dnlp_reg_def[12]); - WRITE_VPP_REG(VPP_DNLP_CTRL_13, ve_dnlp_reg_def[13]); - WRITE_VPP_REG(VPP_DNLP_CTRL_14, ve_dnlp_reg_def[14]); - WRITE_VPP_REG(VPP_DNLP_CTRL_15, ve_dnlp_reg_def[15]); + for (i = 0; i < 16; i++) + WRITE_VPP_REG(VPP_DNLP_CTRL_00 + i, + ve_dnlp_reg_def[i]); } } @@ -336,12 +272,12 @@ void ve_on_vs(struct vframe_s *vf) void vpp_enable_lcd_gamma_table(void) { - WRITE_VPP_REG_BITS(L_GAMMA_CNTL_PORT, 1, GAMMA_EN, 1); + VSYNC_WR_MPEG_REG_BITS(L_GAMMA_CNTL_PORT, 1, GAMMA_EN, 1); } void vpp_disable_lcd_gamma_table(void) { - WRITE_VPP_REG_BITS(L_GAMMA_CNTL_PORT, 0, GAMMA_EN, 1); + VSYNC_WR_MPEG_REG_BITS(L_GAMMA_CNTL_PORT, 0, GAMMA_EN, 1); } void vpp_set_lcd_gamma_table(u16 *data, u32 rgb_mask) @@ -385,7 +321,7 @@ void vpp_set_lcd_gamma_table(u16 *data, u32 rgb_mask) (0x1 << rgb_mask) | (0x23 << HADR)); - WRITE_VPP_REG_BITS(L_GAMMA_CNTL_PORT, + VSYNC_WR_MPEG_REG_BITS(L_GAMMA_CNTL_PORT, gamma_en, GAMMA_EN, 1); spin_unlock_irqrestore(&vpp_lcd_gamma_lock, flags); @@ -550,7 +486,7 @@ void vpp_set_rgb_ogo(struct tcon_rgb_ogo_s *p) m[i] = -1024; } - if (get_cpu_type() == MESON_CPU_MAJOR_ID_G12A) { + if (get_cpu_type() >= MESON_CPU_MAJOR_ID_G12A) { WRITE_VPP_REG_BITS(VPP_POST_MATRIX_EN_CTRL, p->en, 0, 1); WRITE_VPP_REG(VPP_POST_MATRIX_PRE_OFFSET0_1, @@ -656,6 +592,7 @@ void vpp_set_rgb_ogo(struct tcon_rgb_ogo_s *p) WRITE_VPP_REG(VPP_GAINOFF_CTRL4, ((p->b_pre_offset << 0) & 0x00001fff)); } else { + /*txl and before txl, and tl1 10bit path offset is 11bit*/ WRITE_VPP_REG(VPP_GAINOFF_CTRL0, ((p->en << 31) & 0x80000000) | ((p->r_gain << 16) & 0x07ff0000) | @@ -683,6 +620,8 @@ void ve_enable_dnlp(void) if (dnlp_sel == NEW_DNLP_IN_SHARPNESS) { if (is_meson_gxlx_cpu() || is_meson_txlx_cpu()) WRITE_VPP_REG_BITS(SRSHARP1_DNLP_EN, 1, 0, 1); + else if (is_meson_tl1_cpu()) + WRITE_VPP_REG_BITS(SHARP1_DNLP_EN, 1, 0, 1); else WRITE_VPP_REG_BITS(SRSHARP0_DNLP_EN, 1, 0, 1); } else @@ -697,6 +636,8 @@ void ve_disable_dnlp(void) if (dnlp_sel == NEW_DNLP_IN_SHARPNESS) if (is_meson_gxlx_cpu() || is_meson_txlx_cpu()) WRITE_VPP_REG_BITS(SRSHARP1_DNLP_EN, 0, 0, 1); + else if (is_meson_tl1_cpu()) + WRITE_VPP_REG_BITS(SHARP1_DNLP_EN, 0, 0, 1); else WRITE_VPP_REG_BITS(SRSHARP0_DNLP_EN, 0, 0, 1); else @@ -1092,7 +1033,12 @@ void vpp_vd_adj1_contrast(signed int cont_val, struct vframe_s *vf) WRITE_VPP_REG_BITS(VPP_VADJ_CTRL, 0, 1, 1); } } - if (get_cpu_type() > MESON_CPU_MAJOR_ID_GXTVBB) { + if (get_cpu_type() == MESON_CPU_MAJOR_ID_TL1) { + vd1_contrast = (READ_VPP_REG(VPP_VADJ1_Y_2) & 0x7ff00) | + (cont_val << 0); + WRITE_VPP_REG(VPP_VADJ1_Y_2, vd1_contrast); + return; + } else if (get_cpu_type() > MESON_CPU_MAJOR_ID_GXTVBB) { vd1_contrast = (READ_VPP_REG(VPP_VADJ1_Y) & 0x3ff00) | (cont_val << 0); } else { @@ -1119,7 +1065,12 @@ void vpp_vd_adj1_brightness(signed int bri_val, struct vframe_s *vf) if (bri_val > 1023 || bri_val < -1024) return; - if (get_cpu_type() > MESON_CPU_MAJOR_ID_GXTVBB) { + if (get_cpu_type() == MESON_CPU_MAJOR_ID_TL1) { + vd1_brightness = (READ_VPP_REG(VPP_VADJ1_Y_2) & 0xff) | + (bri_val << 8); + + WRITE_VPP_REG(VPP_VADJ1_Y_2, vd1_brightness); + } else if (get_cpu_type() > MESON_CPU_MAJOR_ID_GXTVBB) { bri_val = bri_val >> 1; vd1_brightness = (READ_VPP_REG(VPP_VADJ1_Y) & 0xff) | (bri_val << 8); @@ -1461,15 +1412,19 @@ void amvecm_fresh_overscan(struct vframe_s *vf) else cur_overscan_timing = TIMING_UHD; - overscan_timing = cur_overscan_timing; overscan_screen_mode = overscan_table[overscan_timing].screen_mode; vf->pic_mode.AFD_enable = overscan_table[overscan_timing].afd_enable; - vf->pic_mode.screen_mode = - overscan_table[overscan_timing].screen_mode; + /*local play screen mode set by decoder*/ + if (overscan_table[0].source == SOURCE_MPEG) + vf->pic_mode.screen_mode = 0xff; + else + vf->pic_mode.screen_mode = + overscan_table[overscan_timing].screen_mode; + vf->pic_mode.hs = overscan_table[overscan_timing].hs; vf->pic_mode.he = overscan_table[overscan_timing].he; vf->pic_mode.vs = overscan_table[overscan_timing].vs; @@ -1593,15 +1548,15 @@ static void ycbcr2rgbpc_nb(int *R, int *G, int *B, } /*table: use for yuv->rgb*/ -void vpp_lut3d_table_init(int *pLut3D) +void vpp_lut3d_table_init(int *pLut3D, int bitdepth) { int d0, d1, d2, ncmp; unsigned int i; int step[3]; /*steps of each input components lut-nodes*/ - int max_val = (1<<12) - 1; + int max_val = (1 << bitdepth) - 1; /*step*/ for (ncmp = 0; ncmp < 3; ncmp++) - step[ncmp] = (1<<(12-4)); + step[ncmp] = (1 << (bitdepth - 4)); /*initialize the lut3d ad same input and output;*/ for (d0 = 0; d0 < 17; d0++) { @@ -1623,7 +1578,7 @@ void vpp_lut3d_table_init(int *pLut3D) pLut3D[d0*17*17*3+d1*17*3+d2*3+0], pLut3D[d0*17*17*3+d1*17*3+d2*3+1], pLut3D[d0*17*17*3+d1*17*3+d2*3+2], - 12); + bitdepth); } } } diff --git a/drivers/amlogic/media/enhancement/amvecm/amve.h b/drivers/amlogic/media/enhancement/amvecm/amve.h index 2b089f66099b..d90c1e059d68 100644 --- a/drivers/amlogic/media/enhancement/amvecm/amve.h +++ b/drivers/amlogic/media/enhancement/amvecm/amve.h @@ -64,6 +64,7 @@ extern struct ve_dnlp_s am_ve_dnlp; extern struct tcon_gamma_table_s video_gamma_table_r; extern struct tcon_gamma_table_s video_gamma_table_g; extern struct tcon_gamma_table_s video_gamma_table_b; +extern struct tcon_gamma_table_s video_gamma_table_ioctl_set; extern struct tcon_gamma_table_s video_gamma_table_r_adj; extern struct tcon_gamma_table_s video_gamma_table_g_adj; extern struct tcon_gamma_table_s video_gamma_table_b_adj; @@ -142,6 +143,9 @@ extern int VSYNC_WR_MPEG_REG(u32 adr, u32 val); /* unsigned long long ve_get_vs_cnt(void); */ /* #endif */ extern int video_rgb_ogo_xvy_mtx; + +#define GAMMA_SIZE 256 + extern unsigned int dnlp_sel; extern void ve_dnlp_load_reg(void); @@ -157,8 +161,11 @@ extern void amvecm_fresh_overscan(struct vframe_s *vf); extern void amvecm_reset_overscan(void); extern int vpp_set_lut3d(int enable, int bLut3DLoad, int *pLut3D, int bLut3DCheck); -extern void vpp_lut3d_table_init(int *pLut3D); +extern void vpp_lut3d_table_init(int *pLut3D, int bitdepth); extern void dump_plut3d_table(void); extern void dump_plut3d_reg_table(void); + +extern void amvecm_gamma_init(bool en); + #endif diff --git a/drivers/amlogic/media/enhancement/amvecm/amvecm.c b/drivers/amlogic/media/enhancement/amvecm/amvecm.c index 11f966bbdc72..2b9c3c2b93ae 100644 --- a/drivers/amlogic/media/enhancement/amvecm/amvecm.c +++ b/drivers/amlogic/media/enhancement/amvecm/amvecm.c @@ -59,6 +59,8 @@ #include #include "dnlp_cal.h" #include "vlock.h" +#include "hdr/am_hdr10_plus.h" +#include "local_contrast.h" #define pr_amvecm_dbg(fmt, args...)\ do {\ @@ -73,7 +75,7 @@ #define AMVECM_MODULE_NAME "amvecm" #define AMVECM_DEVICE_NAME "amvecm" #define AMVECM_CLASS_NAME "amvecm" -#define AMVECM_VER "Ref.2018/09/03" +#define AMVECM_VER "Ref.2018/11/20" struct amvecm_dev_s { @@ -180,6 +182,10 @@ MODULE_PARM_DESC(debug_game_mode_1, "\n debug_game_mode_1\n"); unsigned int pq_user_value; unsigned int hdr_source_type = 0x1; +#define SR0_OFFSET 0xc00 +#define SR1_OFFSET 0xc80 +unsigned int sr_offset[2] = {0, 0}; + static int wb_init_bypass_coef[24] = { 0, 0, 0, /* pre offset */ 1024, 0, 0, @@ -230,9 +236,16 @@ __setup("pq=", amvecm_load_pq_val); static int amvecm_set_contrast2(int val) { val += 0x80; - WRITE_VPP_REG_BITS(VPP_VADJ2_Y, - val, 0, 8); - WRITE_VPP_REG_BITS(VPP_VADJ_CTRL, 1, 2, 1); + if (get_cpu_type() == MESON_CPU_MAJOR_ID_TL1) { + WRITE_VPP_REG_BITS(VPP_VADJ2_Y_2, + val, 0, 8); + WRITE_VPP_REG_BITS(VPP_VADJ2_MISC, 1, 0, 1); + + } else { + WRITE_VPP_REG_BITS(VPP_VADJ2_Y, + val, 0, 8); + WRITE_VPP_REG_BITS(VPP_VADJ_CTRL, 1, 2, 1); + } return 0; } @@ -241,10 +254,17 @@ static int amvecm_set_brightness2(int val) if (get_cpu_type() <= MESON_CPU_MAJOR_ID_GXTVBB) WRITE_VPP_REG_BITS(VPP_VADJ2_Y, vdj_mode_s.brightness2, 8, 9); + else if (get_cpu_type() == MESON_CPU_MAJOR_ID_TL1) + WRITE_VPP_REG_BITS(VPP_VADJ2_Y_2, + vdj_mode_s.brightness2, 8, 11); else WRITE_VPP_REG_BITS(VPP_VADJ2_Y, - vdj_mode_s.brightness2 << 1, 8, 10); - WRITE_VPP_REG_BITS(VPP_VADJ_CTRL, 1, 2, 1); + vdj_mode_s.brightness2 >> 1, 8, 10); + + if (get_cpu_type() == MESON_CPU_MAJOR_ID_TL1) + WRITE_VPP_REG_BITS(VPP_VADJ2_MISC, 1, 0, 1); + else + WRITE_VPP_REG_BITS(VPP_VADJ_CTRL, 1, 2, 1); return 0; } @@ -269,12 +289,17 @@ static ssize_t video_adj1_brightness_show(struct class *cla, val = (READ_VPP_REG(VPP_VADJ1_Y) >> 8) & 0x1ff; val = (val << 23) >> 23; + return sprintf(buf, "%d\n", val); + } else if (get_cpu_type() == MESON_CPU_MAJOR_ID_TL1) { + val = (READ_VPP_REG(VPP_VADJ1_Y_2) >> 8) & 0x7ff; + val = (val << 21) >> 21; + return sprintf(buf, "%d\n", val); } val = (READ_VPP_REG(VPP_VADJ1_Y) >> 8) & 0x3ff; - val = (val << 23) >> 23; + val = (val << 22) >> 22; - return sprintf(buf, "%d\n", val >> 1); + return sprintf(buf, "%d\n", val << 1); } static ssize_t video_adj1_brightness_store(struct class *cla, @@ -285,15 +310,20 @@ static ssize_t video_adj1_brightness_store(struct class *cla, int val; r = sscanf(buf, "%d\n", &val); - if ((r != 1) || (val < -255) || (val > 255)) + if ((r != 1) || (val < -1024) || (val > 1023)) return -EINVAL; if (get_cpu_type() <= MESON_CPU_MAJOR_ID_GXTVBB) WRITE_VPP_REG_BITS(VPP_VADJ1_Y, val, 8, 9); + else if (get_cpu_type() == MESON_CPU_MAJOR_ID_TL1) + WRITE_VPP_REG_BITS(VPP_VADJ1_Y_2, val, 8, 11); else - WRITE_VPP_REG_BITS(VPP_VADJ1_Y, val << 1, 8, 10); + WRITE_VPP_REG_BITS(VPP_VADJ1_Y, val >> 1, 8, 10); - WRITE_VPP_REG_BITS(VPP_VADJ_CTRL, 1, 0, 1); + if (get_cpu_type() == MESON_CPU_MAJOR_ID_TL1) + WRITE_VPP_REG_BITS(VPP_VADJ1_MISC, 1, 0, 1); + else + WRITE_VPP_REG_BITS(VPP_VADJ_CTRL, 1, 0, 1); return count; } @@ -301,7 +331,11 @@ static ssize_t video_adj1_brightness_store(struct class *cla, static ssize_t video_adj1_contrast_show(struct class *cla, struct class_attribute *attr, char *buf) { - return sprintf(buf, "%d\n", + if (get_cpu_type() == MESON_CPU_MAJOR_ID_TL1) + return sprintf(buf, "%d\n", + (int)(READ_VPP_REG(VPP_VADJ1_Y_2) & 0xff) - 0x80); + else + return sprintf(buf, "%d\n", (int)(READ_VPP_REG(VPP_VADJ1_Y) & 0xff) - 0x80); } @@ -318,8 +352,13 @@ static ssize_t video_adj1_contrast_store(struct class *cla, val += 0x80; - WRITE_VPP_REG_BITS(VPP_VADJ1_Y, val, 0, 8); - WRITE_VPP_REG_BITS(VPP_VADJ_CTRL, 1, 0, 1); + if (get_cpu_type() == MESON_CPU_MAJOR_ID_TL1) { + WRITE_VPP_REG_BITS(VPP_VADJ1_Y_2, val, 0, 8); + WRITE_VPP_REG_BITS(VPP_VADJ1_MISC, 1, 0, 1); + } else { + WRITE_VPP_REG_BITS(VPP_VADJ1_Y, val, 0, 8); + WRITE_VPP_REG_BITS(VPP_VADJ_CTRL, 1, 0, 1); + } return count; } @@ -334,12 +373,17 @@ static ssize_t video_adj2_brightness_show(struct class *cla, val = (READ_VPP_REG(VPP_VADJ2_Y) >> 8) & 0x1ff; val = (val << 23) >> 23; + return sprintf(buf, "%d\n", val); + } else if (get_cpu_type() == MESON_CPU_MAJOR_ID_TL1) { + val = (READ_VPP_REG(VPP_VADJ2_Y_2) >> 8) & 0x7ff; + val = (val << 21) >> 21; + return sprintf(buf, "%d\n", val); } val = (READ_VPP_REG(VPP_VADJ2_Y) >> 8) & 0x3ff; - val = (val << 23) >> 23; + val = (val << 22) >> 22; - return sprintf(buf, "%d\n", val >> 1); + return sprintf(buf, "%d\n", val << 1); } static ssize_t video_adj2_brightness_store(struct class *cla, @@ -350,7 +394,7 @@ static ssize_t video_adj2_brightness_store(struct class *cla, int val; r = sscanf(buf, "%d\n", &val); - if ((r != 1) || (val < -255) || (val > 255)) + if ((r != 1) || (val < -1024) || (val > 1023)) return -EINVAL; amvecm_set_brightness2(val); return count; @@ -359,7 +403,11 @@ static ssize_t video_adj2_brightness_store(struct class *cla, static ssize_t video_adj2_contrast_show(struct class *cla, struct class_attribute *attr, char *buf) { - return sprintf(buf, "%d\n", + if (get_cpu_type() == MESON_CPU_MAJOR_ID_TL1) + return sprintf(buf, "%d\n", + (int)(READ_VPP_REG(VPP_VADJ2_Y_2) & 0xff) - 0x80); + else + return sprintf(buf, "%d\n", (int)(READ_VPP_REG(VPP_VADJ2_Y) & 0xff) - 0x80); } @@ -567,6 +615,8 @@ static ssize_t amvecm_vlock_show(struct class *cla, "echo vlock_dis_cnt_no_vf_limit val(D) > /sys/class/amvecm/vlock\n"); len += sprintf(buf+len, "echo vlock_line_limit val(D) > /sys/class/amvecm/vlock\n"); + len += sprintf(buf+len, + "echo vlock_support val(D) > /sys/class/amvecm/vlock\n"); len += sprintf(buf+len, "echo enable > /sys/class/amvecm/vlock\n"); len += sprintf(buf+len, @@ -664,6 +714,11 @@ static ssize_t amvecm_vlock_store(struct class *cla, return -EINVAL; temp_val = val; sel = VLOCK_LINE_LIMIT; + } else if (!strncmp(parm[0], "vlock_support", 13)) { + if (kstrtol(parm[1], 10, &val) < 0) + return -EINVAL; + temp_val = val; + sel = VLOCK_SUPPORT; } else if (!strncmp(parm[0], "enable", 6)) { vecm_latch_flag |= FLAG_VLOCK_EN; } else if (!strncmp(parm[0], "disable", 7)) { @@ -1001,10 +1056,14 @@ int amvecm_on_vs( result = amvecm_matrix_process(toggle_vf, vf, flags); if (toggle_vf) ioctrl_get_hdr_metadata(toggle_vf); + + if (toggle_vf) + lc_process(toggle_vf, sps_h_en, sps_v_en); } else { amvecm_reset_overscan(); result = amvecm_matrix_process(NULL, NULL, flags); ve_hist_gamma_reset(); + lc_process(NULL, sps_h_en, sps_v_en); } if (!is_dolby_vision_on()) @@ -1131,7 +1190,12 @@ static int amvecm_set_saturation_hue(int mab) if (mb < -512) mb = -512; mab = ((ma & 0x3ff) << 16) | (mb & 0x3ff); - WRITE_VPP_REG(VPP_VADJ1_MA_MB, mab); + + if (get_cpu_type() == MESON_CPU_MAJOR_ID_TL1) + WRITE_VPP_REG(VPP_VADJ1_MA_MB_2, mab); + else + WRITE_VPP_REG(VPP_VADJ1_MA_MB, mab); + mc = (s16)((mab<<22)>>22); /* mc = -mb */ mc = 0 - mc; if (mc > 511) @@ -1140,8 +1204,14 @@ static int amvecm_set_saturation_hue(int mab) mc = -512; md = (s16)((mab<<6)>>22); /* md = ma; */ mab = ((mc&0x3ff)<<16)|(md&0x3ff); - WRITE_VPP_REG(VPP_VADJ1_MC_MD, mab); - WRITE_VPP_REG_BITS(VPP_VADJ_CTRL, 1, 0, 1); + + if (get_cpu_type() == MESON_CPU_MAJOR_ID_TL1) { + WRITE_VPP_REG(VPP_VADJ1_MC_MD_2, mab); + WRITE_VPP_REG_BITS(VPP_VADJ1_MISC, 1, 0, 1); + } else { + WRITE_VPP_REG(VPP_VADJ1_MC_MD, mab); + WRITE_VPP_REG_BITS(VPP_VADJ_CTRL, 1, 0, 1); + } pr_amvecm_dbg("%s set video_saturation_hue OK!!!\n", __func__); return 0; } @@ -1190,7 +1260,10 @@ static int amvecm_set_saturation_hue_post(int val1, mab = ((ma & 0x3ff) << 16) | (mb & 0x3ff); pr_info("\n[amvideo..] saturation_post:%d hue_post:%d mab:%x\n", saturation_post, hue_post, mab); - WRITE_VPP_REG(VPP_VADJ2_MA_MB, mab); + if (get_cpu_type() == MESON_CPU_MAJOR_ID_TL1) + WRITE_VPP_REG(VPP_VADJ2_MA_MB_2, mab); + else + WRITE_VPP_REG(VPP_VADJ2_MA_MB, mab); mc = (s16)((mab<<22)>>22); /* mc = -mb */ mc = 0 - mc; if (mc > 511) @@ -1199,11 +1272,30 @@ static int amvecm_set_saturation_hue_post(int val1, mc = -512; md = (s16)((mab<<6)>>22); /* md = ma; */ mab = ((mc&0x3ff)<<16)|(md&0x3ff); - WRITE_VPP_REG(VPP_VADJ2_MC_MD, mab); - WRITE_VPP_REG_BITS(VPP_VADJ_CTRL, 1, 2, 1); + if (get_cpu_type() == MESON_CPU_MAJOR_ID_TL1) { + WRITE_VPP_REG(VPP_VADJ2_MC_MD_2, mab); + WRITE_VPP_REG_BITS(VPP_VADJ2_MISC, 1, 0, 1); + } else { + WRITE_VPP_REG(VPP_VADJ2_MC_MD, mab); + WRITE_VPP_REG_BITS(VPP_VADJ_CTRL, 1, 2, 1); + } return 0; } +static int gamma_table_compare(struct tcon_gamma_table_s *table1, + struct tcon_gamma_table_s *table2) +{ + int i = 0, flag = 0; + + for (i = 0; i < 256; i++) + if (table1->data[i] != table2->data[i]) { + flag = 1; + break; + } + + return flag; +} + static long amvecm_ioctl(struct file *file, unsigned int cmd, unsigned long arg) { @@ -1299,34 +1391,52 @@ static long amvecm_ioctl(struct file *file, if (!gamma_en) return -EINVAL; - if (copy_from_user(&video_gamma_table_r, + if (copy_from_user(&video_gamma_table_ioctl_set, (void __user *)arg, sizeof(struct tcon_gamma_table_s))) ret = -EFAULT; - else + else if (gamma_table_compare(&video_gamma_table_ioctl_set, + &video_gamma_table_r)) { + memcpy(&video_gamma_table_r, + &video_gamma_table_ioctl_set, + sizeof(struct tcon_gamma_table_s)); vecm_latch_flag |= FLAG_GAMMA_TABLE_R; + } else + pr_amvecm_dbg("load same gamma_r table,no need to change\n"); break; case AMVECM_IOC_GAMMA_TABLE_G: if (!gamma_en) return -EINVAL; - if (copy_from_user(&video_gamma_table_g, + if (copy_from_user(&video_gamma_table_ioctl_set, (void __user *)arg, sizeof(struct tcon_gamma_table_s))) ret = -EFAULT; - else + else if (gamma_table_compare(&video_gamma_table_ioctl_set, + &video_gamma_table_g)) { + memcpy(&video_gamma_table_g, + &video_gamma_table_ioctl_set, + sizeof(struct tcon_gamma_table_s)); vecm_latch_flag |= FLAG_GAMMA_TABLE_G; + } else + pr_amvecm_dbg("load same gamma_g table,no need to change\n"); break; case AMVECM_IOC_GAMMA_TABLE_B: if (!gamma_en) return -EINVAL; - if (copy_from_user(&video_gamma_table_b, + if (copy_from_user(&video_gamma_table_ioctl_set, (void __user *)arg, sizeof(struct tcon_gamma_table_s))) ret = -EFAULT; - else + else if (gamma_table_compare(&video_gamma_table_ioctl_set, + &video_gamma_table_b)) { + memcpy(&video_gamma_table_b, + &video_gamma_table_ioctl_set, + sizeof(struct tcon_gamma_table_s)); vecm_latch_flag |= FLAG_GAMMA_TABLE_B; + } else + pr_amvecm_dbg("load same gamma_b table,no need to change\n"); break; case AMVECM_IOC_S_RGB_OGO: if (!wb_en) @@ -2091,7 +2201,12 @@ static ssize_t amvecm_contrast_store(struct class *cla, static ssize_t amvecm_saturation_hue_show(struct class *cla, struct class_attribute *attr, char *buf) { - return sprintf(buf, "0x%x\n", READ_VPP_REG(VPP_VADJ1_MA_MB)); + if (get_cpu_type() == MESON_CPU_MAJOR_ID_TL1) + return sprintf(buf, "0x%x\n", + READ_VPP_REG(VPP_VADJ1_MA_MB_2)); + else + return sprintf(buf, "0x%x\n", + READ_VPP_REG(VPP_VADJ1_MA_MB)); } static ssize_t amvecm_saturation_hue_store(struct class *cla, @@ -2149,7 +2264,10 @@ void vpp_vd_adj1_saturation_hue(signed int sat_val, mab = ((ma & 0x3ff) << 16) | (mb & 0x3ff); pr_info("\n[amvideo..] saturation_pre:%d hue_pre:%d mab:%x\n", sat_val, hue_val, mab); - WRITE_VPP_REG(VPP_VADJ1_MA_MB, mab); + if (get_cpu_type() == MESON_CPU_MAJOR_ID_TL1) + WRITE_VPP_REG(VPP_VADJ1_MA_MB_2, mab); + else + WRITE_VPP_REG(VPP_VADJ1_MA_MB, mab); mc = (s16)((mab<<22)>>22); /* mc = -mb */ mc = 0 - mc; if (mc > 511) @@ -2158,8 +2276,14 @@ void vpp_vd_adj1_saturation_hue(signed int sat_val, mc = -512; md = (s16)((mab<<6)>>22); /* md = ma; */ mab = ((mc&0x3ff)<<16)|(md&0x3ff); - WRITE_VPP_REG(VPP_VADJ1_MC_MD, mab); - WRITE_VPP_REG_BITS(VPP_VADJ_CTRL, 1, 0, 1); + + if (get_cpu_type() == MESON_CPU_MAJOR_ID_TL1) { + WRITE_VPP_REG(VPP_VADJ1_MC_MD_2, mab); + WRITE_VPP_REG_BITS(VPP_VADJ1_MISC, 1, 0, 1); + } else { + WRITE_VPP_REG(VPP_VADJ1_MC_MD, mab); + WRITE_VPP_REG_BITS(VPP_VADJ_CTRL, 1, 0, 1); + } }; static ssize_t amvecm_saturation_hue_pre_show(struct class *cla, @@ -3239,7 +3363,26 @@ static ssize_t amvecm_hdr_dbg_store(struct class *cla, struct class_attribute *attr, const char *buf, size_t count) { - return 0; + long val = 0; + char *buf_orig, *parm[5] = {NULL}; + + if (!buf) + return count; + buf_orig = kstrdup(buf, GFP_KERNEL); + parse_param_amvecm(buf_orig, (char **)&parm); + + if (!strncmp(parm[0], "hdr_dbg", 10)) { + if (kstrtoul(parm[1], 16, &val) < 0) { + kfree(buf_orig); + return -EINVAL; + } + debug_hdr = val; + pr_info("debug_hdr=0x%x\n", debug_hdr); + } else + pr_info("error cmd\n"); + + kfree(buf_orig); + return count; } static ssize_t amvecm_hdr_reg_show(struct class *cla, @@ -3302,45 +3445,53 @@ void pc_mode_process(void) cm_en = 1; /* sharpness on */ VSYNC_WR_MPEG_REG_BITS( - SRSHARP0_PK_NR_ENABLE, + SRSHARP0_PK_NR_ENABLE + sr_offset[0], 1, 1, 1); VSYNC_WR_MPEG_REG_BITS( - SRSHARP1_PK_NR_ENABLE, + SRSHARP1_PK_NR_ENABLE + sr_offset[1], 1, 1, 1); - reg_val = VSYNC_RD_MPEG_REG(SRSHARP0_HCTI_FLT_CLP_DC); - VSYNC_WR_MPEG_REG(SRSHARP0_HCTI_FLT_CLP_DC, + reg_val = VSYNC_RD_MPEG_REG(SRSHARP0_HCTI_FLT_CLP_DC + + sr_offset[0]); + VSYNC_WR_MPEG_REG(SRSHARP0_HCTI_FLT_CLP_DC + sr_offset[0], reg_val | 0x10000000); - VSYNC_WR_MPEG_REG(SRSHARP1_HCTI_FLT_CLP_DC, + VSYNC_WR_MPEG_REG(SRSHARP1_HCTI_FLT_CLP_DC + sr_offset[1], reg_val | 0x10000000); - reg_val = VSYNC_RD_MPEG_REG(SRSHARP0_HLTI_FLT_CLP_DC); - VSYNC_WR_MPEG_REG(SRSHARP0_HLTI_FLT_CLP_DC, + reg_val = VSYNC_RD_MPEG_REG(SRSHARP0_HLTI_FLT_CLP_DC + + sr_offset[0]); + VSYNC_WR_MPEG_REG(SRSHARP0_HLTI_FLT_CLP_DC + sr_offset[0], reg_val | 0x10000000); - VSYNC_WR_MPEG_REG(SRSHARP1_HLTI_FLT_CLP_DC, + VSYNC_WR_MPEG_REG(SRSHARP1_HLTI_FLT_CLP_DC + sr_offset[1], reg_val | 0x10000000); - reg_val = VSYNC_RD_MPEG_REG(SRSHARP0_VLTI_FLT_CON_CLP); - VSYNC_WR_MPEG_REG(SRSHARP0_VLTI_FLT_CON_CLP, + reg_val = VSYNC_RD_MPEG_REG(SRSHARP0_VLTI_FLT_CON_CLP + + sr_offset[0]); + VSYNC_WR_MPEG_REG(SRSHARP0_VLTI_FLT_CON_CLP + sr_offset[0], reg_val | 0x4000); - VSYNC_WR_MPEG_REG(SRSHARP1_VLTI_FLT_CON_CLP, + VSYNC_WR_MPEG_REG(SRSHARP1_VLTI_FLT_CON_CLP + sr_offset[1], reg_val | 0x4000); - reg_val = VSYNC_RD_MPEG_REG(SRSHARP0_VCTI_FLT_CON_CLP); - VSYNC_WR_MPEG_REG(SRSHARP0_VCTI_FLT_CON_CLP, + reg_val = VSYNC_RD_MPEG_REG(SRSHARP0_VCTI_FLT_CON_CLP + + sr_offset[0]); + VSYNC_WR_MPEG_REG(SRSHARP0_VCTI_FLT_CON_CLP + sr_offset[0], reg_val | 0x4000); - VSYNC_WR_MPEG_REG(SRSHARP1_VCTI_FLT_CON_CLP, + VSYNC_WR_MPEG_REG(SRSHARP1_VCTI_FLT_CON_CLP + sr_offset[1], reg_val | 0x4000); if (cpu_after_eq(MESON_CPU_MAJOR_ID_TXL)) { - VSYNC_WR_MPEG_REG_BITS(SRSHARP0_DEJ_CTRL, 1, 0, 1); - VSYNC_WR_MPEG_REG_BITS(SRSHARP0_SR3_DRTLPF_EN, 7, 0, 3); - VSYNC_WR_MPEG_REG_BITS(SRSHARP0_SR3_DERING_CTRL, - 1, 28, 3); + VSYNC_WR_MPEG_REG_BITS(SRSHARP0_DEJ_CTRL + sr_offset[0], + 1, 0, 1); + VSYNC_WR_MPEG_REG_BITS(SRSHARP0_SR3_DRTLPF_EN + + sr_offset[0], 7, 0, 3); + VSYNC_WR_MPEG_REG_BITS(SRSHARP0_SR3_DERING_CTRL + + sr_offset[0], 1, 28, 3); - VSYNC_WR_MPEG_REG_BITS(SRSHARP1_DEJ_CTRL, 1, 0, 1); - VSYNC_WR_MPEG_REG_BITS(SRSHARP1_SR3_DRTLPF_EN, 7, 0, 3); - VSYNC_WR_MPEG_REG_BITS(SRSHARP1_SR3_DERING_CTRL, - 1, 28, 3); + VSYNC_WR_MPEG_REG_BITS(SRSHARP1_DEJ_CTRL + sr_offset[1], + 1, 0, 1); + VSYNC_WR_MPEG_REG_BITS(SRSHARP1_SR3_DRTLPF_EN + + sr_offset[1], 7, 0, 3); + VSYNC_WR_MPEG_REG_BITS(SRSHARP1_SR3_DERING_CTRL + + sr_offset[1], 1, 28, 3); } VSYNC_WR_MPEG_REG(VPP_VADJ_CTRL, 0xd); pc_mode_last = pc_mode; @@ -3350,45 +3501,53 @@ void pc_mode_process(void) cm_en = 0; VSYNC_WR_MPEG_REG_BITS( - SRSHARP0_PK_NR_ENABLE, + SRSHARP0_PK_NR_ENABLE + sr_offset[0], 0, 1, 1); VSYNC_WR_MPEG_REG_BITS( - SRSHARP1_PK_NR_ENABLE, + SRSHARP1_PK_NR_ENABLE + sr_offset[1], 0, 1, 1); - reg_val = VSYNC_RD_MPEG_REG(SRSHARP0_HCTI_FLT_CLP_DC); - VSYNC_WR_MPEG_REG(SRSHARP0_HCTI_FLT_CLP_DC, + reg_val = VSYNC_RD_MPEG_REG(SRSHARP0_HCTI_FLT_CLP_DC + + sr_offset[0]); + VSYNC_WR_MPEG_REG(SRSHARP0_HCTI_FLT_CLP_DC + sr_offset[0], reg_val & 0xefffffff); - VSYNC_WR_MPEG_REG(SRSHARP1_HCTI_FLT_CLP_DC, + VSYNC_WR_MPEG_REG(SRSHARP1_HCTI_FLT_CLP_DC + sr_offset[1], reg_val & 0xefffffff); - reg_val = VSYNC_RD_MPEG_REG(SRSHARP0_HLTI_FLT_CLP_DC); - VSYNC_WR_MPEG_REG(SRSHARP0_HLTI_FLT_CLP_DC, + reg_val = VSYNC_RD_MPEG_REG(SRSHARP0_HLTI_FLT_CLP_DC + + sr_offset[0]); + VSYNC_WR_MPEG_REG(SRSHARP0_HLTI_FLT_CLP_DC + sr_offset[0], reg_val & 0xefffffff); - VSYNC_WR_MPEG_REG(SRSHARP1_HLTI_FLT_CLP_DC, + VSYNC_WR_MPEG_REG(SRSHARP1_HLTI_FLT_CLP_DC + sr_offset[1], reg_val & 0xefffffff); - reg_val = VSYNC_RD_MPEG_REG(SRSHARP0_VLTI_FLT_CON_CLP); - VSYNC_WR_MPEG_REG(SRSHARP0_VLTI_FLT_CON_CLP, + reg_val = VSYNC_RD_MPEG_REG(SRSHARP0_VLTI_FLT_CON_CLP + + sr_offset[0]); + VSYNC_WR_MPEG_REG(SRSHARP0_VLTI_FLT_CON_CLP + sr_offset[0], reg_val & 0xffffbfff); - VSYNC_WR_MPEG_REG(SRSHARP1_VLTI_FLT_CON_CLP, + VSYNC_WR_MPEG_REG(SRSHARP1_VLTI_FLT_CON_CLP + sr_offset[1], reg_val & 0xffffbfff); - reg_val = VSYNC_RD_MPEG_REG(SRSHARP0_VCTI_FLT_CON_CLP); - VSYNC_WR_MPEG_REG(SRSHARP0_VCTI_FLT_CON_CLP, + reg_val = VSYNC_RD_MPEG_REG(SRSHARP0_VCTI_FLT_CON_CLP + + sr_offset[0]); + VSYNC_WR_MPEG_REG(SRSHARP0_VCTI_FLT_CON_CLP + sr_offset[0], reg_val & 0xffffbfff); - VSYNC_WR_MPEG_REG(SRSHARP1_VCTI_FLT_CON_CLP, + VSYNC_WR_MPEG_REG(SRSHARP1_VCTI_FLT_CON_CLP + sr_offset[1], reg_val & 0xffffbfff); if (cpu_after_eq(MESON_CPU_MAJOR_ID_TXL)) { - VSYNC_WR_MPEG_REG_BITS(SRSHARP0_DEJ_CTRL, 0, 0, 1); - VSYNC_WR_MPEG_REG_BITS(SRSHARP0_SR3_DRTLPF_EN, 0, 0, 3); - VSYNC_WR_MPEG_REG_BITS(SRSHARP0_SR3_DERING_CTRL, - 0, 28, 3); + VSYNC_WR_MPEG_REG_BITS(SRSHARP0_DEJ_CTRL + sr_offset[0], + 0, 0, 1); + VSYNC_WR_MPEG_REG_BITS(SRSHARP0_SR3_DRTLPF_EN + + sr_offset[0], 0, 0, 3); + VSYNC_WR_MPEG_REG_BITS(SRSHARP0_SR3_DERING_CTRL + + sr_offset[0], 0, 28, 3); - VSYNC_WR_MPEG_REG_BITS(SRSHARP1_DEJ_CTRL, 0, 0, 1); - VSYNC_WR_MPEG_REG_BITS(SRSHARP1_SR3_DRTLPF_EN, 0, 0, 3); - VSYNC_WR_MPEG_REG_BITS(SRSHARP1_SR3_DERING_CTRL, - 0, 28, 3); + VSYNC_WR_MPEG_REG_BITS(SRSHARP1_DEJ_CTRL + sr_offset[1], + 0, 0, 1); + VSYNC_WR_MPEG_REG_BITS(SRSHARP1_SR3_DRTLPF_EN + + sr_offset[1], 0, 0, 3); + VSYNC_WR_MPEG_REG_BITS(SRSHARP1_SR3_DERING_CTRL + + sr_offset[1], 0, 28, 3); } VSYNC_WR_MPEG_REG(VPP_VADJ_CTRL, 0x0); pc_mode_last = pc_mode; @@ -3420,65 +3579,81 @@ void amvecm_black_ext_slope_adj(unsigned int value) void amvecm_sr0_pk_enable(unsigned int enable) { if (enable) - WRITE_VPP_REG_BITS(SRSHARP0_PK_NR_ENABLE, 1, 1, 1); + WRITE_VPP_REG_BITS(SRSHARP0_PK_NR_ENABLE + sr_offset[0], + 1, 1, 1); else - WRITE_VPP_REG_BITS(SRSHARP0_PK_NR_ENABLE, 0, 1, 1); + WRITE_VPP_REG_BITS(SRSHARP0_PK_NR_ENABLE + sr_offset[0], + 0, 1, 1); } void amvecm_sr1_pk_enable(unsigned int enable) { if (enable) - WRITE_VPP_REG_BITS(SRSHARP1_PK_NR_ENABLE, 1, 1, 1); + WRITE_VPP_REG_BITS(SRSHARP1_PK_NR_ENABLE + sr_offset[1], + 1, 1, 1); else - WRITE_VPP_REG_BITS(SRSHARP1_PK_NR_ENABLE, 0, 1, 1); + WRITE_VPP_REG_BITS(SRSHARP1_PK_NR_ENABLE + sr_offset[1], + 0, 1, 1); } void amvecm_sr0_dering_enable(unsigned int enable) { if (enable) - WRITE_VPP_REG_BITS(SRSHARP0_SR3_DERING_CTRL, 1, 28, 3); + WRITE_VPP_REG_BITS(SRSHARP0_SR3_DERING_CTRL + sr_offset[0], + 1, 28, 3); else - WRITE_VPP_REG_BITS(SRSHARP0_SR3_DERING_CTRL, 0, 28, 3); + WRITE_VPP_REG_BITS(SRSHARP0_SR3_DERING_CTRL + sr_offset[0], + 0, 28, 3); } void amvecm_sr1_dering_enable(unsigned int enable) { if (enable) - WRITE_VPP_REG_BITS(SRSHARP1_SR3_DERING_CTRL, 1, 28, 3); + WRITE_VPP_REG_BITS(SRSHARP1_SR3_DERING_CTRL + sr_offset[1], + 1, 28, 3); else - WRITE_VPP_REG_BITS(SRSHARP1_SR3_DERING_CTRL, 0, 28, 3); + WRITE_VPP_REG_BITS(SRSHARP1_SR3_DERING_CTRL + sr_offset[1], + 0, 28, 3); } void amvecm_sr0_dejaggy_enable(unsigned int enable) { if (enable) - WRITE_VPP_REG_BITS(SRSHARP0_DEJ_CTRL, 1, 0, 1); + WRITE_VPP_REG_BITS(SRSHARP0_DEJ_CTRL + sr_offset[0], + 1, 0, 1); else - WRITE_VPP_REG_BITS(SRSHARP0_DEJ_CTRL, 0, 0, 1); + WRITE_VPP_REG_BITS(SRSHARP0_DEJ_CTRL + sr_offset[0], + 0, 0, 1); } void amvecm_sr1_dejaggy_enable(unsigned int enable) { if (enable) - WRITE_VPP_REG_BITS(SRSHARP1_DEJ_CTRL, 1, 0, 1); + WRITE_VPP_REG_BITS(SRSHARP1_DEJ_CTRL + sr_offset[1], + 1, 0, 1); else - WRITE_VPP_REG_BITS(SRSHARP1_DEJ_CTRL, 0, 0, 1); + WRITE_VPP_REG_BITS(SRSHARP1_DEJ_CTRL + sr_offset[1], + 0, 0, 1); } void amvecm_sr0_derection_enable(unsigned int enable) { if (enable) - WRITE_VPP_REG_BITS(SRSHARP0_SR3_DRTLPF_EN, 7, 0, 3); + WRITE_VPP_REG_BITS(SRSHARP0_SR3_DRTLPF_EN + sr_offset[0], + 7, 0, 3); else - WRITE_VPP_REG_BITS(SRSHARP0_SR3_DRTLPF_EN, 0, 0, 3); + WRITE_VPP_REG_BITS(SRSHARP0_SR3_DRTLPF_EN + sr_offset[0], + 0, 0, 3); } void amvecm_sr1_derection_enable(unsigned int enable) { if (enable) - WRITE_VPP_REG_BITS(SRSHARP1_SR3_DRTLPF_EN, 7, 0, 3); + WRITE_VPP_REG_BITS(SRSHARP1_SR3_DRTLPF_EN + sr_offset[1], + 7, 0, 3); else - WRITE_VPP_REG_BITS(SRSHARP1_SR3_DRTLPF_EN, 0, 0, 3); + WRITE_VPP_REG_BITS(SRSHARP1_SR3_DRTLPF_EN + sr_offset[1], + 0, 0, 3); } void pq_user_latch_process(void) @@ -3812,93 +3987,145 @@ void amvecm_sharpness_enable(int sel) /*2:lti/cti enable 3:lti/cti disable*/ switch (sel) { case 0: - WRITE_VPP_REG_BITS(SRSHARP0_PK_NR_ENABLE, 1, 1, 1); - WRITE_VPP_REG_BITS(SRSHARP1_PK_NR_ENABLE, 1, 1, 1); + WRITE_VPP_REG_BITS(SRSHARP0_PK_NR_ENABLE + sr_offset[0], + 1, 1, 1); + WRITE_VPP_REG_BITS(SRSHARP1_PK_NR_ENABLE + sr_offset[1], + 1, 1, 1); break; case 1: - WRITE_VPP_REG_BITS(SRSHARP0_PK_NR_ENABLE, 0, 1, 1); - WRITE_VPP_REG_BITS(SRSHARP1_PK_NR_ENABLE, 0, 1, 1); + WRITE_VPP_REG_BITS(SRSHARP0_PK_NR_ENABLE + sr_offset[0], + 0, 1, 1); + WRITE_VPP_REG_BITS(SRSHARP1_PK_NR_ENABLE + sr_offset[1], + 0, 1, 1); break; case 2: - WRITE_VPP_REG_BITS(SRSHARP0_HCTI_FLT_CLP_DC, 1, 28, 1); - WRITE_VPP_REG_BITS(SRSHARP0_HLTI_FLT_CLP_DC, 1, 28, 1); - WRITE_VPP_REG_BITS(SRSHARP0_VLTI_FLT_CON_CLP, 1, 14, 1); - WRITE_VPP_REG_BITS(SRSHARP0_VCTI_FLT_CON_CLP, 1, 14, 1); + WRITE_VPP_REG_BITS(SRSHARP0_HCTI_FLT_CLP_DC + sr_offset[0], + 1, 28, 1); + WRITE_VPP_REG_BITS(SRSHARP0_HLTI_FLT_CLP_DC + sr_offset[0], + 1, 28, 1); + WRITE_VPP_REG_BITS(SRSHARP0_VLTI_FLT_CON_CLP + sr_offset[0], + 1, 14, 1); + WRITE_VPP_REG_BITS(SRSHARP0_VCTI_FLT_CON_CLP + sr_offset[0], + 1, 14, 1); - WRITE_VPP_REG_BITS(SRSHARP1_HCTI_FLT_CLP_DC, 1, 28, 1); - WRITE_VPP_REG_BITS(SRSHARP1_HLTI_FLT_CLP_DC, 1, 28, 1); - WRITE_VPP_REG_BITS(SRSHARP1_VLTI_FLT_CON_CLP, 1, 14, 1); - WRITE_VPP_REG_BITS(SRSHARP1_VCTI_FLT_CON_CLP, 1, 14, 1); + WRITE_VPP_REG_BITS(SRSHARP1_HCTI_FLT_CLP_DC + sr_offset[1], + 1, 28, 1); + WRITE_VPP_REG_BITS(SRSHARP1_HLTI_FLT_CLP_DC + sr_offset[1], + 1, 28, 1); + WRITE_VPP_REG_BITS(SRSHARP1_VLTI_FLT_CON_CLP + sr_offset[1], + 1, 14, 1); + WRITE_VPP_REG_BITS(SRSHARP1_VCTI_FLT_CON_CLP + sr_offset[1], + 1, 14, 1); break; case 3: - WRITE_VPP_REG_BITS(SRSHARP0_HCTI_FLT_CLP_DC, 0, 28, 1); - WRITE_VPP_REG_BITS(SRSHARP0_HLTI_FLT_CLP_DC, 0, 28, 1); - WRITE_VPP_REG_BITS(SRSHARP0_VLTI_FLT_CON_CLP, 0, 14, 1); - WRITE_VPP_REG_BITS(SRSHARP0_VCTI_FLT_CON_CLP, 0, 14, 1); + WRITE_VPP_REG_BITS(SRSHARP0_HCTI_FLT_CLP_DC + sr_offset[0], + 0, 28, 1); + WRITE_VPP_REG_BITS(SRSHARP0_HLTI_FLT_CLP_DC + sr_offset[0], + 0, 28, 1); + WRITE_VPP_REG_BITS(SRSHARP0_VLTI_FLT_CON_CLP + sr_offset[0], + 0, 14, 1); + WRITE_VPP_REG_BITS(SRSHARP0_VCTI_FLT_CON_CLP + sr_offset[0], + 0, 14, 1); - WRITE_VPP_REG_BITS(SRSHARP1_HCTI_FLT_CLP_DC, 0, 28, 1); - WRITE_VPP_REG_BITS(SRSHARP1_HLTI_FLT_CLP_DC, 0, 28, 1); - WRITE_VPP_REG_BITS(SRSHARP1_VLTI_FLT_CON_CLP, 0, 14, 1); - WRITE_VPP_REG_BITS(SRSHARP1_VCTI_FLT_CON_CLP, 0, 14, 1); + WRITE_VPP_REG_BITS(SRSHARP1_HCTI_FLT_CLP_DC + sr_offset[1], + 0, 28, 1); + WRITE_VPP_REG_BITS(SRSHARP1_HLTI_FLT_CLP_DC + sr_offset[1], + 0, 28, 1); + WRITE_VPP_REG_BITS(SRSHARP1_VLTI_FLT_CON_CLP + sr_offset[1], + 0, 14, 1); + WRITE_VPP_REG_BITS(SRSHARP1_VCTI_FLT_CON_CLP + sr_offset[1], + 0, 14, 1); break; /*sr4 drtlpf theta en*/ case 4: - WRITE_VPP_REG_BITS(SRSHARP0_SR3_DRTLPF_EN, 7, 4, 3); - WRITE_VPP_REG_BITS(SRSHARP1_SR3_DRTLPF_EN, 7, 3, 3); + WRITE_VPP_REG_BITS(SRSHARP0_SR3_DRTLPF_EN + sr_offset[0], + 7, 4, 3); + WRITE_VPP_REG_BITS(SRSHARP1_SR3_DRTLPF_EN + sr_offset[1], + 7, 3, 3); break; case 5: - WRITE_VPP_REG_BITS(SRSHARP0_SR3_DRTLPF_EN, 0, 4, 3); - WRITE_VPP_REG_BITS(SRSHARP1_SR3_DRTLPF_EN, 0, 3, 3); + WRITE_VPP_REG_BITS(SRSHARP0_SR3_DRTLPF_EN + sr_offset[0], + 0, 4, 3); + WRITE_VPP_REG_BITS(SRSHARP1_SR3_DRTLPF_EN + sr_offset[1], + 0, 3, 3); break; /*sr4 debanding en*/ case 6: - WRITE_VPP_REG_BITS(SRSHARP0_DB_FLT_CTRL, 1, 4, 1); - WRITE_VPP_REG_BITS(SRSHARP0_DB_FLT_CTRL, 1, 5, 1); - WRITE_VPP_REG_BITS(SRSHARP0_DB_FLT_CTRL, 1, 22, 1); - WRITE_VPP_REG_BITS(SRSHARP0_DB_FLT_CTRL, 1, 23, 1); + WRITE_VPP_REG_BITS(SRSHARP0_DB_FLT_CTRL + sr_offset[0], + 1, 4, 1); + WRITE_VPP_REG_BITS(SRSHARP0_DB_FLT_CTRL + sr_offset[0], + 1, 5, 1); + WRITE_VPP_REG_BITS(SRSHARP0_DB_FLT_CTRL + sr_offset[0], + 1, 22, 1); + WRITE_VPP_REG_BITS(SRSHARP0_DB_FLT_CTRL + sr_offset[0], + 1, 23, 1); - WRITE_VPP_REG_BITS(SRSHARP1_DB_FLT_CTRL, 1, 4, 1); - WRITE_VPP_REG_BITS(SRSHARP1_DB_FLT_CTRL, 1, 5, 1); - WRITE_VPP_REG_BITS(SRSHARP1_DB_FLT_CTRL, 1, 22, 1); - WRITE_VPP_REG_BITS(SRSHARP1_DB_FLT_CTRL, 1, 23, 1); + WRITE_VPP_REG_BITS(SRSHARP1_DB_FLT_CTRL + sr_offset[1], + 1, 4, 1); + WRITE_VPP_REG_BITS(SRSHARP1_DB_FLT_CTRL + sr_offset[1], + 1, 5, 1); + WRITE_VPP_REG_BITS(SRSHARP1_DB_FLT_CTRL + sr_offset[1], + 1, 22, 1); + WRITE_VPP_REG_BITS(SRSHARP1_DB_FLT_CTRL + sr_offset[1], + 1, 23, 1); break; case 7: - WRITE_VPP_REG_BITS(SRSHARP0_DB_FLT_CTRL, 0, 4, 1); - WRITE_VPP_REG_BITS(SRSHARP0_DB_FLT_CTRL, 0, 5, 1); - WRITE_VPP_REG_BITS(SRSHARP0_DB_FLT_CTRL, 0, 22, 1); - WRITE_VPP_REG_BITS(SRSHARP0_DB_FLT_CTRL, 0, 23, 1); + WRITE_VPP_REG_BITS(SRSHARP0_DB_FLT_CTRL + sr_offset[0], + 0, 4, 1); + WRITE_VPP_REG_BITS(SRSHARP0_DB_FLT_CTRL + sr_offset[0], + 0, 5, 1); + WRITE_VPP_REG_BITS(SRSHARP0_DB_FLT_CTRL + sr_offset[0], + 0, 22, 1); + WRITE_VPP_REG_BITS(SRSHARP0_DB_FLT_CTRL + sr_offset[0], + 0, 23, 1); - WRITE_VPP_REG_BITS(SRSHARP1_DB_FLT_CTRL, 0, 4, 1); - WRITE_VPP_REG_BITS(SRSHARP1_DB_FLT_CTRL, 0, 5, 1); - WRITE_VPP_REG_BITS(SRSHARP1_DB_FLT_CTRL, 0, 22, 1); - WRITE_VPP_REG_BITS(SRSHARP1_DB_FLT_CTRL, 0, 23, 1); + WRITE_VPP_REG_BITS(SRSHARP1_DB_FLT_CTRL + sr_offset[1], + 0, 4, 1); + WRITE_VPP_REG_BITS(SRSHARP1_DB_FLT_CTRL + sr_offset[1], + 0, 5, 1); + WRITE_VPP_REG_BITS(SRSHARP1_DB_FLT_CTRL + sr_offset[1], + 0, 22, 1); + WRITE_VPP_REG_BITS(SRSHARP1_DB_FLT_CTRL + sr_offset[1], + 0, 23, 1); break; /*sr3 dejaggy en*/ case 8: - WRITE_VPP_REG_BITS(SRSHARP0_DEJ_CTRL, 1, 0, 1); - WRITE_VPP_REG_BITS(SRSHARP1_DEJ_CTRL, 1, 0, 1); + WRITE_VPP_REG_BITS(SRSHARP0_DEJ_CTRL + sr_offset[0], + 1, 0, 1); + WRITE_VPP_REG_BITS(SRSHARP1_DEJ_CTRL + sr_offset[1], + 1, 0, 1); break; case 9: - WRITE_VPP_REG_BITS(SRSHARP0_DEJ_CTRL, 0, 0, 1); - WRITE_VPP_REG_BITS(SRSHARP1_DEJ_CTRL, 0, 0, 1); + WRITE_VPP_REG_BITS(SRSHARP0_DEJ_CTRL + sr_offset[0], + 0, 0, 1); + WRITE_VPP_REG_BITS(SRSHARP1_DEJ_CTRL + sr_offset[1], + 0, 0, 1); break; /*sr3 dering en*/ case 10: - WRITE_VPP_REG_BITS(SRSHARP0_SR3_DERING_CTRL, 1, 28, 3); - WRITE_VPP_REG_BITS(SRSHARP1_SR3_DERING_CTRL, 1, 28, 3); + WRITE_VPP_REG_BITS(SRSHARP0_SR3_DERING_CTRL + sr_offset[0], + 1, 28, 3); + WRITE_VPP_REG_BITS(SRSHARP1_SR3_DERING_CTRL + sr_offset[1], + 1, 28, 3); break; case 11: - WRITE_VPP_REG_BITS(SRSHARP0_SR3_DERING_CTRL, 0, 28, 3); - WRITE_VPP_REG_BITS(SRSHARP1_SR3_DERING_CTRL, 0, 28, 3); + WRITE_VPP_REG_BITS(SRSHARP0_SR3_DERING_CTRL + sr_offset[0], + 0, 28, 3); + WRITE_VPP_REG_BITS(SRSHARP1_SR3_DERING_CTRL + sr_offset[1], + 0, 28, 3); break; /*sr3 derection lpf en*/ case 12: - WRITE_VPP_REG_BITS(SRSHARP0_SR3_DRTLPF_EN, 7, 0, 3); - WRITE_VPP_REG_BITS(SRSHARP1_SR3_DRTLPF_EN, 7, 0, 3); + WRITE_VPP_REG_BITS(SRSHARP0_SR3_DRTLPF_EN + sr_offset[0], + 7, 0, 3); + WRITE_VPP_REG_BITS(SRSHARP1_SR3_DRTLPF_EN + sr_offset[1], + 7, 0, 3); break; case 13: - WRITE_VPP_REG_BITS(SRSHARP0_SR3_DRTLPF_EN, 0, 0, 3); - WRITE_VPP_REG_BITS(SRSHARP1_SR3_DRTLPF_EN, 0, 0, 3); + WRITE_VPP_REG_BITS(SRSHARP0_SR3_DRTLPF_EN + sr_offset[0], + 0, 0, 3); + WRITE_VPP_REG_BITS(SRSHARP1_SR3_DRTLPF_EN + sr_offset[1], + 0, 0, 3); break; default: @@ -3906,6 +4133,21 @@ void amvecm_sharpness_enable(int sel) } } +void amvecm_clip_range_limit(bool limit_en) +{ + /*fix mbox av out flicker black dot*/ + if (limit_en) { + /*cvbs output 16-235 16-240 16-240*/ + WRITE_VPP_REG(VPP_CLIP_MISC0, 0x3acf03c0); + WRITE_VPP_REG(VPP_CLIP_MISC1, 0x4010040); + } else { + /*retore for other mode*/ + WRITE_VPP_REG(VPP_CLIP_MISC0, 0x3fffffff); + WRITE_VPP_REG(VPP_CLIP_MISC1, 0x0); + } +} +EXPORT_SYMBOL(amvecm_clip_range_limit); + static void amvecm_pq_enable(int enable) { if (enable) { @@ -3914,40 +4156,65 @@ static void amvecm_pq_enable(int enable) if (!is_dolby_vision_enable()) #endif amcm_enable(); - WRITE_VPP_REG_BITS(SRSHARP0_PK_NR_ENABLE, 1, 1, 1); - WRITE_VPP_REG_BITS(SRSHARP1_PK_NR_ENABLE, 1, 1, 1); + WRITE_VPP_REG_BITS(SRSHARP0_PK_NR_ENABLE + sr_offset[0], + 1, 1, 1); + WRITE_VPP_REG_BITS(SRSHARP1_PK_NR_ENABLE + sr_offset[1], + 1, 1, 1); - WRITE_VPP_REG_BITS(SRSHARP0_HCTI_FLT_CLP_DC, 1, 28, 1); - WRITE_VPP_REG_BITS(SRSHARP0_HLTI_FLT_CLP_DC, 1, 28, 1); - WRITE_VPP_REG_BITS(SRSHARP0_VLTI_FLT_CON_CLP, 1, 14, 1); - WRITE_VPP_REG_BITS(SRSHARP0_VCTI_FLT_CON_CLP, 1, 14, 1); - WRITE_VPP_REG_BITS(SRSHARP1_HCTI_FLT_CLP_DC, 1, 28, 1); - WRITE_VPP_REG_BITS(SRSHARP1_HLTI_FLT_CLP_DC, 1, 28, 1); - WRITE_VPP_REG_BITS(SRSHARP1_VLTI_FLT_CON_CLP, 1, 14, 1); - WRITE_VPP_REG_BITS(SRSHARP1_VCTI_FLT_CON_CLP, 1, 14, 1); + WRITE_VPP_REG_BITS(SRSHARP0_HCTI_FLT_CLP_DC + sr_offset[0], + 1, 28, 1); + WRITE_VPP_REG_BITS(SRSHARP0_HLTI_FLT_CLP_DC + sr_offset[0], + 1, 28, 1); + WRITE_VPP_REG_BITS(SRSHARP0_VLTI_FLT_CON_CLP + sr_offset[0], + 1, 14, 1); + WRITE_VPP_REG_BITS(SRSHARP0_VCTI_FLT_CON_CLP + sr_offset[0], + 1, 14, 1); + WRITE_VPP_REG_BITS(SRSHARP1_HCTI_FLT_CLP_DC + sr_offset[1], + 1, 28, 1); + WRITE_VPP_REG_BITS(SRSHARP1_HLTI_FLT_CLP_DC + sr_offset[1], + 1, 28, 1); + WRITE_VPP_REG_BITS(SRSHARP1_VLTI_FLT_CON_CLP + sr_offset[1], + 1, 14, 1); + WRITE_VPP_REG_BITS(SRSHARP1_VCTI_FLT_CON_CLP + sr_offset[1], + 1, 14, 1); if (cpu_after_eq(MESON_CPU_MAJOR_ID_TXL)) { - WRITE_VPP_REG_BITS(SRSHARP0_DEJ_CTRL, 1, 0, 1); - WRITE_VPP_REG_BITS(SRSHARP0_SR3_DRTLPF_EN, 7, 0, 3); - WRITE_VPP_REG_BITS(SRSHARP0_SR3_DERING_CTRL, 1, 28, 3); + WRITE_VPP_REG_BITS(SRSHARP0_DEJ_CTRL + sr_offset[0], + 1, 0, 1); + WRITE_VPP_REG_BITS(SRSHARP0_SR3_DRTLPF_EN + + sr_offset[0], 7, 0, 3); + WRITE_VPP_REG_BITS(SRSHARP0_SR3_DERING_CTRL + + sr_offset[0], 1, 28, 3); - WRITE_VPP_REG_BITS(SRSHARP1_DEJ_CTRL, 1, 0, 1); - WRITE_VPP_REG_BITS(SRSHARP1_SR3_DRTLPF_EN, 7, 0, 3); - WRITE_VPP_REG_BITS(SRSHARP1_SR3_DERING_CTRL, 1, 28, 3); + WRITE_VPP_REG_BITS(SRSHARP1_DEJ_CTRL + sr_offset[1], + 1, 0, 1); + WRITE_VPP_REG_BITS(SRSHARP1_SR3_DRTLPF_EN + + sr_offset[1], 7, 0, 3); + WRITE_VPP_REG_BITS(SRSHARP1_SR3_DERING_CTRL + + sr_offset[1], 1, 28, 3); } /*sr4 drtlpf theta/ debanding en*/ if (is_meson_txlx_cpu() || is_meson_txhd_cpu()) { - WRITE_VPP_REG_BITS(SRSHARP0_SR3_DRTLPF_EN, 7, 4, 3); + WRITE_VPP_REG_BITS(SRSHARP0_SR3_DRTLPF_EN + + sr_offset[0], 7, 4, 3); - WRITE_VPP_REG_BITS(SRSHARP0_DB_FLT_CTRL, 1, 4, 1); - WRITE_VPP_REG_BITS(SRSHARP0_DB_FLT_CTRL, 1, 5, 1); - WRITE_VPP_REG_BITS(SRSHARP0_DB_FLT_CTRL, 1, 22, 1); - WRITE_VPP_REG_BITS(SRSHARP0_DB_FLT_CTRL, 1, 23, 1); + WRITE_VPP_REG_BITS(SRSHARP0_DB_FLT_CTRL + sr_offset[0], + 1, 4, 1); + WRITE_VPP_REG_BITS(SRSHARP0_DB_FLT_CTRL + sr_offset[0], + 1, 5, 1); + WRITE_VPP_REG_BITS(SRSHARP0_DB_FLT_CTRL + sr_offset[0], + 1, 22, 1); + WRITE_VPP_REG_BITS(SRSHARP0_DB_FLT_CTRL + sr_offset[0], + 1, 23, 1); - WRITE_VPP_REG_BITS(SRSHARP1_DB_FLT_CTRL, 1, 4, 1); - WRITE_VPP_REG_BITS(SRSHARP1_DB_FLT_CTRL, 1, 5, 1); - WRITE_VPP_REG_BITS(SRSHARP1_DB_FLT_CTRL, 1, 22, 1); - WRITE_VPP_REG_BITS(SRSHARP1_DB_FLT_CTRL, 1, 23, 1); + WRITE_VPP_REG_BITS(SRSHARP1_DB_FLT_CTRL + sr_offset[1], + 1, 4, 1); + WRITE_VPP_REG_BITS(SRSHARP1_DB_FLT_CTRL + sr_offset[1], + 1, 5, 1); + WRITE_VPP_REG_BITS(SRSHARP1_DB_FLT_CTRL + sr_offset[1], + 1, 22, 1); + WRITE_VPP_REG_BITS(SRSHARP1_DB_FLT_CTRL + sr_offset[1], + 1, 23, 1); } amvecm_wb_enable(true); @@ -3960,40 +4227,65 @@ static void amvecm_pq_enable(int enable) amcm_disable(); - WRITE_VPP_REG_BITS(SRSHARP0_PK_NR_ENABLE, 0, 1, 1); - WRITE_VPP_REG_BITS(SRSHARP1_PK_NR_ENABLE, 0, 1, 1); + WRITE_VPP_REG_BITS(SRSHARP0_PK_NR_ENABLE + sr_offset[0], + 0, 1, 1); + WRITE_VPP_REG_BITS(SRSHARP1_PK_NR_ENABLE + sr_offset[1], + 0, 1, 1); - WRITE_VPP_REG_BITS(SRSHARP0_HCTI_FLT_CLP_DC, 0, 28, 1); - WRITE_VPP_REG_BITS(SRSHARP0_HLTI_FLT_CLP_DC, 0, 28, 1); - WRITE_VPP_REG_BITS(SRSHARP0_VLTI_FLT_CON_CLP, 0, 14, 1); - WRITE_VPP_REG_BITS(SRSHARP0_VCTI_FLT_CON_CLP, 0, 14, 1); - WRITE_VPP_REG_BITS(SRSHARP1_HCTI_FLT_CLP_DC, 0, 28, 1); - WRITE_VPP_REG_BITS(SRSHARP1_HLTI_FLT_CLP_DC, 0, 28, 1); - WRITE_VPP_REG_BITS(SRSHARP1_VLTI_FLT_CON_CLP, 0, 14, 1); - WRITE_VPP_REG_BITS(SRSHARP1_VCTI_FLT_CON_CLP, 0, 14, 1); + WRITE_VPP_REG_BITS(SRSHARP0_HCTI_FLT_CLP_DC + sr_offset[0], + 0, 28, 1); + WRITE_VPP_REG_BITS(SRSHARP0_HLTI_FLT_CLP_DC + sr_offset[0], + 0, 28, 1); + WRITE_VPP_REG_BITS(SRSHARP0_VLTI_FLT_CON_CLP + sr_offset[0], + 0, 14, 1); + WRITE_VPP_REG_BITS(SRSHARP0_VCTI_FLT_CON_CLP + sr_offset[0], + 0, 14, 1); + WRITE_VPP_REG_BITS(SRSHARP1_HCTI_FLT_CLP_DC + sr_offset[1], + 0, 28, 1); + WRITE_VPP_REG_BITS(SRSHARP1_HLTI_FLT_CLP_DC + sr_offset[1], + 0, 28, 1); + WRITE_VPP_REG_BITS(SRSHARP1_VLTI_FLT_CON_CLP + sr_offset[1], + 0, 14, 1); + WRITE_VPP_REG_BITS(SRSHARP1_VCTI_FLT_CON_CLP + sr_offset[1], + 0, 14, 1); if (cpu_after_eq(MESON_CPU_MAJOR_ID_TXL)) { - WRITE_VPP_REG_BITS(SRSHARP0_DEJ_CTRL, 0, 0, 1); - WRITE_VPP_REG_BITS(SRSHARP0_SR3_DRTLPF_EN, 0, 0, 3); - WRITE_VPP_REG_BITS(SRSHARP0_SR3_DERING_CTRL, 0, 28, 3); + WRITE_VPP_REG_BITS(SRSHARP0_DEJ_CTRL + sr_offset[0], + 0, 0, 1); + WRITE_VPP_REG_BITS(SRSHARP0_SR3_DRTLPF_EN + + sr_offset[0], 0, 0, 3); + WRITE_VPP_REG_BITS(SRSHARP0_SR3_DERING_CTRL + + sr_offset[0], 0, 28, 3); - WRITE_VPP_REG_BITS(SRSHARP1_DEJ_CTRL, 0, 0, 1); - WRITE_VPP_REG_BITS(SRSHARP1_SR3_DRTLPF_EN, 0, 0, 3); - WRITE_VPP_REG_BITS(SRSHARP1_SR3_DERING_CTRL, 0, 28, 3); + WRITE_VPP_REG_BITS(SRSHARP1_DEJ_CTRL + sr_offset[1], + 0, 0, 1); + WRITE_VPP_REG_BITS(SRSHARP1_SR3_DRTLPF_EN + + sr_offset[1], 0, 0, 3); + WRITE_VPP_REG_BITS(SRSHARP1_SR3_DERING_CTRL + + sr_offset[1], 0, 28, 3); } /*sr4 drtlpf theta/ debanding en*/ if (is_meson_txlx_cpu()) { - WRITE_VPP_REG_BITS(SRSHARP0_SR3_DRTLPF_EN, 0, 4, 3); + WRITE_VPP_REG_BITS(SRSHARP0_SR3_DRTLPF_EN + + sr_offset[0], 0, 4, 3); - WRITE_VPP_REG_BITS(SRSHARP0_DB_FLT_CTRL, 0, 4, 1); - WRITE_VPP_REG_BITS(SRSHARP0_DB_FLT_CTRL, 0, 5, 1); - WRITE_VPP_REG_BITS(SRSHARP0_DB_FLT_CTRL, 0, 22, 1); - WRITE_VPP_REG_BITS(SRSHARP0_DB_FLT_CTRL, 0, 23, 1); + WRITE_VPP_REG_BITS(SRSHARP0_DB_FLT_CTRL + sr_offset[0], + 0, 4, 1); + WRITE_VPP_REG_BITS(SRSHARP0_DB_FLT_CTRL + sr_offset[0], + 0, 5, 1); + WRITE_VPP_REG_BITS(SRSHARP0_DB_FLT_CTRL + sr_offset[0], + 0, 22, 1); + WRITE_VPP_REG_BITS(SRSHARP0_DB_FLT_CTRL + sr_offset[0], + 0, 23, 1); - WRITE_VPP_REG_BITS(SRSHARP1_DB_FLT_CTRL, 0, 4, 1); - WRITE_VPP_REG_BITS(SRSHARP1_DB_FLT_CTRL, 0, 5, 1); - WRITE_VPP_REG_BITS(SRSHARP1_DB_FLT_CTRL, 0, 22, 1); - WRITE_VPP_REG_BITS(SRSHARP1_DB_FLT_CTRL, 0, 23, 1); + WRITE_VPP_REG_BITS(SRSHARP1_DB_FLT_CTRL + sr_offset[1], + 0, 4, 1); + WRITE_VPP_REG_BITS(SRSHARP1_DB_FLT_CTRL + sr_offset[1], + 0, 5, 1); + WRITE_VPP_REG_BITS(SRSHARP1_DB_FLT_CTRL + sr_offset[1], + 0, 22, 1); + WRITE_VPP_REG_BITS(SRSHARP1_DB_FLT_CTRL + sr_offset[1], + 0, 23, 1); } amvecm_wb_enable(false); @@ -4350,6 +4642,120 @@ kfree_buf: return -EINVAL; } +static void cm_hist_config(unsigned int en, unsigned int mode, + unsigned int wd0, unsigned int wd1, + unsigned int wd2, unsigned int wd3) +{ + unsigned int value; + + WRITE_VPP_REG(VPP_CHROMA_ADDR_PORT, STA_CFG_REG); + value = READ_VPP_REG(VPP_CHROMA_DATA_PORT); + value = (value & (~0xc0000000)) | (en << 30); + WRITE_VPP_REG(VPP_CHROMA_ADDR_PORT, STA_CFG_REG); + WRITE_VPP_REG(VPP_CHROMA_DATA_PORT, value); + + WRITE_VPP_REG(VPP_CHROMA_ADDR_PORT, LUMA_ADJ1_REG); + value = READ_VPP_REG(VPP_CHROMA_DATA_PORT); + value = (value & (~(0x1fff0000))) | (mode << 16); + WRITE_VPP_REG(VPP_CHROMA_ADDR_PORT, LUMA_ADJ1_REG); + WRITE_VPP_REG(VPP_CHROMA_DATA_PORT, value); + + WRITE_VPP_REG(VPP_CHROMA_ADDR_PORT, STA_WIN_XYXY0_REG); + WRITE_VPP_REG(VPP_CHROMA_DATA_PORT, wd0 | (wd1 << 16)); + + WRITE_VPP_REG(VPP_CHROMA_ADDR_PORT, STA_WIN_XYXY1_REG); + WRITE_VPP_REG(VPP_CHROMA_DATA_PORT, wd2 | (wd3 << 16)); +} + +static void cm_sta_hist_range_thrd(int r, int ro_frame, + int thrd0, int thrd1) +{ + unsigned int value0, value1; + + if (r) { + WRITE_VPP_REG(VPP_CHROMA_ADDR_PORT, STA_SAT_HIST0_REG); + value0 = READ_VPP_REG(VPP_CHROMA_DATA_PORT); + WRITE_VPP_REG(VPP_CHROMA_ADDR_PORT, STA_SAT_HIST1_REG); + value1 = READ_VPP_REG(VPP_CHROMA_DATA_PORT); + pr_info("thrd0 = 0x%x, thrd0 = 0x%x\n", value0, value1); + } else { + WRITE_VPP_REG(VPP_CHROMA_ADDR_PORT, STA_SAT_HIST0_REG); + WRITE_VPP_REG(VPP_CHROMA_DATA_PORT, thrd0 | (ro_frame << 24)); + + WRITE_VPP_REG(VPP_CHROMA_ADDR_PORT, STA_SAT_HIST1_REG); + WRITE_VPP_REG(VPP_CHROMA_DATA_PORT, thrd1); + } +} + +static void cm_luma_bri_con(int r, int brightness, int contrast, + int blk_lel) +{ + int value; + + if (r) { + WRITE_VPP_REG(VPP_CHROMA_ADDR_PORT, LUMA_ADJ0_REG); + value = READ_VPP_REG(VPP_CHROMA_DATA_PORT); + pr_info("contrast = 0x%x, blklel = 0x%x\n", + value & 0xfff, (value >> 12) & 0x3ff); + WRITE_VPP_REG(VPP_CHROMA_ADDR_PORT, LUMA_ADJ1_REG); + value = READ_VPP_REG(VPP_CHROMA_DATA_PORT); + pr_info("bright = 0x%x, hist_mode = 0x%x\n", + value & 0x1fff, (value >> 16) & 0x1fff); + } else { + WRITE_VPP_REG(VPP_CHROMA_ADDR_PORT, LUMA_ADJ0_REG); + WRITE_VPP_REG(VPP_CHROMA_DATA_PORT, + (blk_lel << 12) | contrast); + + WRITE_VPP_REG(VPP_CHROMA_ADDR_PORT, LUMA_ADJ1_REG); + value = READ_VPP_REG(VPP_CHROMA_DATA_PORT); + WRITE_VPP_REG(VPP_CHROMA_ADDR_PORT, LUMA_ADJ1_REG); + WRITE_VPP_REG(VPP_CHROMA_DATA_PORT, + (value & (~(0x1fff))) | brightness); + } +} +static void get_cm_hist(enum cm_hist_e hist_sel) +{ + unsigned int *hist; + unsigned int i; + + hist = kmalloc(64 * sizeof(unsigned int), GFP_KERNEL); + memset(hist, 0, 64 * sizeof(unsigned int)); + + switch (hist_sel) { + case CM_HUE_HIST: + for (i = 0; i < 64; i++) { + WRITE_VPP_REG(VPP_CHROMA_ADDR_PORT, + RO_CM_HUE_HIST_BIN0 + i); + hist[i] = READ_VPP_REG(VPP_CHROMA_DATA_PORT); + pr_info("hist[%d] = 0x%8x\n", i, hist[i]); + } + break; + case CM_SAT_HIST: + for (i = 0; i < 64; i++) { + WRITE_VPP_REG(VPP_CHROMA_ADDR_PORT, + RO_CM_SAT_HIST_BIN0 + i); + hist[i] = READ_VPP_REG(VPP_CHROMA_DATA_PORT); + pr_info("hist[%d] = 0x%8x\n", i, hist[i]); + } + break; + default: + break; + } + kfree(hist); +} + +static void cm_init_config(void) +{ + WRITE_VPP_REG(VPP_CHROMA_ADDR_PORT, XVYCC_YSCP_REG); + WRITE_VPP_REG(VPP_CHROMA_DATA_PORT, 0x3ff0000); + WRITE_VPP_REG(VPP_CHROMA_ADDR_PORT, XVYCC_USCP_REG); + WRITE_VPP_REG(VPP_CHROMA_DATA_PORT, 0x3ff0000); + WRITE_VPP_REG(VPP_CHROMA_ADDR_PORT, XVYCC_VSCP_REG); + WRITE_VPP_REG(VPP_CHROMA_DATA_PORT, 0x3ff0000); + WRITE_VPP_REG(VPP_CHROMA_ADDR_PORT, LUMA_ADJ0_REG); + WRITE_VPP_REG(VPP_CHROMA_DATA_PORT, 0x40400); +} + static const char *amvecm_debug_usage_str = { "Usage:\n" "echo vpp_size > /sys/class/amvecm/debug; get vpp size config\n" @@ -4604,13 +5010,13 @@ static ssize_t amvecm_debug_store(struct class *cla, if (!parm[2]) { pr_info("misss param\n"); - return -EINVAL; + goto free_buf; } if (kstrtoul(parm[1], 10, &val) < 0) - return -EINVAL; + goto free_buf; vks_param = val; if (kstrtoul(parm[2], 10, &val) < 0) - return -EINVAL; + goto free_buf; vks_param_val = val; keystone_correction_config(vks_param, vks_param_val); } else if (!strcmp(parm[0], "bitdepth")) { @@ -4618,10 +5024,10 @@ static ssize_t amvecm_debug_store(struct class *cla, if (!parm[1]) { pr_info("misss param1\n"); - return -EINVAL; + goto free_buf; } if (kstrtoul(parm[1], 10, &val) < 0) - return -EINVAL; + goto free_buf; bitdepth = val; vpp_bitdepth_config(bitdepth); } else if (!strcmp(parm[0], "datapath_config")) { @@ -4629,18 +5035,18 @@ static ssize_t amvecm_debug_store(struct class *cla, if (!parm[1]) { pr_info("misss param1\n"); - return -EINVAL; + goto free_buf; } if (kstrtoul(parm[1], 10, &val) < 0) - return -EINVAL; + goto free_buf; node = val; if (!parm[2]) { pr_info("misss param2\n"); - return -EINVAL; + goto free_buf; } if (kstrtoul(parm[2], 10, &val) < 0) - return -EINVAL; + goto free_buf; param1 = val; if (!parm[3]) { @@ -4648,33 +5054,27 @@ static ssize_t amvecm_debug_store(struct class *cla, param2 = 0; } if (kstrtoul(parm[3], 10, &val) < 0) - return -EINVAL; + goto free_buf; param2 = val; vpp_datapath_config(node, param1, param2); } else if (!strcmp(parm[0], "datapath_status")) { vpp_datapath_status(); } else if (!strcmp(parm[0], "clip_config")) { if (parm[1]) { - if (kstrtoul(parm[1], 16, &val) < 0) { - kfree(buf_orig); - return -EINVAL; - } + if (kstrtoul(parm[1], 16, &val) < 0) + goto free_buf; mode_sel = val; } else mode_sel = 0; if (parm[2]) { - if (kstrtoul(parm[2], 16, &val) < 0) { - kfree(buf_orig); - return -EINVAL; - } + if (kstrtoul(parm[2], 16, &val) < 0) + goto free_buf; color = val; } else color = 0; if (parm[3]) { - if (kstrtoul(parm[3], 16, &val) < 0) { - kfree(buf_orig); - return -EINVAL; - } + if (kstrtoul(parm[3], 16, &val) < 0) + goto free_buf; color_mode = val; } else color_mode = 0; @@ -4682,16 +5082,29 @@ static ssize_t amvecm_debug_store(struct class *cla, pr_info("vpp_clip_config done!\n"); } else if (!strcmp(parm[0], "3dlut_set")) { int *PLut3D; + unsigned int bitdepth; - PLut3D = kzalloc(14739 * sizeof(int), GFP_KERNEL); + PLut3D = kmalloc(14739 * sizeof(int), GFP_KERNEL); if (PLut3D == NULL) { - kfree(buf_orig); - return -EINVAL; + kfree(PLut3D); + goto free_buf; } - vpp_lut3d_table_init(PLut3D); - if (!strcmp(parm[1], "enable")) + if (parm[1]) { + if (kstrtoul(parm[1], 10, &val) < 0) { + kfree(PLut3D); + goto free_buf; + } + bitdepth = val; + } else { + pr_info("unsupport cmd\n"); + kfree(PLut3D); + goto free_buf; + } + + vpp_lut3d_table_init(PLut3D, bitdepth); + if (!strcmp(parm[2], "enable")) vpp_set_lut3d(1, 1, PLut3D, 1); - else if (!strcmp(parm[1], "disable")) + else if (!strcmp(parm[2], "disable")) vpp_set_lut3d(0, 0, PLut3D, 0); else pr_info("unsupprt cmd!\n"); @@ -4703,12 +5116,115 @@ static ssize_t amvecm_debug_store(struct class *cla, dump_plut3d_reg_table(); else pr_info("unsupprt cmd!\n"); + } else if (!strcmp(parm[0], "cm_hist")) { + if (!parm[1]) { + pr_info("miss param1\n"); + goto free_buf; + } + if (!strcmp(parm[1], "hue")) + get_cm_hist(CM_HUE_HIST); + else if (!strcmp(parm[1], "sat")) + get_cm_hist(CM_SAT_HIST); + else + pr_info("unsupport cmd\n"); + } else if (!strcmp(parm[0], "cm_hist_config")) { + unsigned int en, mode, wd0, wd1, wd2, wd3; + + if (!parm[6]) { + pr_info("miss param1\n"); + goto free_buf; + } + if (kstrtoul(parm[1], 10, &val) < 0) + goto free_buf; + en = val; + if (kstrtoul(parm[2], 10, &val) < 0) + goto free_buf; + mode = val; + if (kstrtoul(parm[3], 10, &val) < 0) + goto free_buf; + wd0 = val; + if (kstrtoul(parm[4], 10, &val) < 0) + goto free_buf; + wd1 = val; + if (kstrtoul(parm[5], 10, &val) < 0) + goto free_buf; + wd2 = val; + if (kstrtoul(parm[6], 10, &val) < 0) + goto free_buf; + wd3 = val; + cm_hist_config(en, mode, wd0, wd1, wd2, wd3); + pr_info("cm hist config success\n"); + } else if (!strcmp(parm[0], "cm_hist_thrd")) { + int rd, ro_frame, thrd0, thrd1; + + if (parm[1]) { + if (kstrtoul(parm[1], 16, &val) < 0) + goto free_buf; + rd = val; + } else { + pr_info("unsupport cmd\n"); + goto free_buf; + } + if (rd) + cm_sta_hist_range_thrd(rd, 0, 0, 0); + else { + if (!parm[3]) { + pr_info("miss param1\n"); + goto free_buf; + } + if (kstrtoul(parm[1], 16, &val) < 0) + goto free_buf; + ro_frame = val; + if (kstrtoul(parm[2], 16, &val) < 0) + goto free_buf; + thrd0 = val; + if (kstrtoul(parm[3], 16, &val) < 0) + goto free_buf; + thrd1 = val; + cm_sta_hist_range_thrd(rd, ro_frame, thrd0, thrd1); + pr_info("cm hist thrd set success\n"); + } + } else if (!strcmp(parm[0], "cm_bri_con")) { + int rd, bri, con, blk_lel; + + if (parm[1]) { + if (kstrtoul(parm[1], 16, &val) < 0) + goto free_buf; + rd = val; + } else { + pr_info("unsupport cmd\n"); + goto free_buf; + } + + if (rd) + cm_luma_bri_con(rd, 0, 0, 0); + else { + if (!parm[3]) { + pr_info("miss param1\n"); + goto free_buf; + } + if (kstrtoul(parm[1], 16, &val) < 0) + goto free_buf; + bri = val; + if (kstrtoul(parm[2], 16, &val) < 0) + goto free_buf; + con = val; + if (kstrtoul(parm[3], 16, &val) < 0) + goto free_buf; + blk_lel = val; + cm_luma_bri_con(rd, bri, con, blk_lel); + pr_info("cm hist bri_con set success\n"); + } } else { pr_info("unsupport cmd\n"); } kfree(buf_orig); return count; + +free_buf: + kfree(buf_orig); + return -EINVAL; } static const char *amvecm_reg_usage_str = { @@ -4717,8 +5233,8 @@ static const char *amvecm_reg_usage_str = { "echo rc addr(H) > /sys/class/amvecm/reg;\n" "echo rh addr(H) > /sys/class/amvecm/reg; read hiu reg\n" "echo wv addr(H) value(H) > /sys/class/amvecm/reg; write vpu reg\n" - "echo wc addr(H) value(H) > /sys/class/amvecm/re; write cbus reg\n" - "echo wh addr(H) value(H) > /sys/class/amvecm/re; write hiu reg\n" + "echo wc addr(H) value(H) > /sys/class/amvecm/reg; write cbus reg\n" + "echo wh addr(H) value(H) > /sys/class/amvecm/reg; write hiu reg\n" "echo dv|c|h addr(H) num > /sys/class/amvecm/reg; dump reg from addr\n" }; static ssize_t amvecm_reg_show(struct class *cla, @@ -4843,25 +5359,89 @@ static ssize_t amvecm_get_hdr_type_store(struct class *cls, return count; } +static ssize_t amvecm_lc_show(struct class *cla, + struct class_attribute *attr, char *buf) +{ + ssize_t len = 0; + + len += sprintf(buf+len, + "echo lc enable > /sys/class/amvecm/lc\n"); + len += sprintf(buf+len, + "echo lc disable > /sys/class/amvecm/lc\n"); + len += sprintf(buf+len, + "echo lc_dbg value > /sys/class/amvecm/lc\n"); + return len; +} + +static ssize_t amvecm_lc_store(struct class *cls, + struct class_attribute *attr, + const char *buf, size_t count) +{ + char *buf_orig, *parm[8] = {NULL}; + long val = 0; + + if (!buf) + return count; + + buf_orig = kstrdup(buf, GFP_KERNEL); + parse_param_amvecm(buf_orig, (char **)&parm); + + if (!strcmp(parm[0], "lc")) { + if (!strcmp(parm[1], "enable")) + lc_en = 1; + else if (!strcmp(parm[1], "disable")) + lc_en = 0; + else + pr_info("unsupprt cmd!\n"); + } else if (!strcmp(parm[0], "lc_dbg")) { + if (kstrtoul(parm[1], 16, &val) < 0) { + kfree(buf_orig); + return -EINVAL; + } + amlc_debug = val; + } else + pr_info("unsupprt cmd!\n"); + + kfree(buf_orig); + return count; +} + + /* #if (MESON_CPU_TYPE == MESON_CPU_TYPE_MESONG9TV) */ void init_pq_setting(void) { + if (get_cpu_type() == MESON_CPU_MAJOR_ID_TL1) { + /*sr0 & sr1 register shfit*/ + sr_offset[0] = SR0_OFFSET; + sr_offset[1] = SR1_OFFSET; + /*cm register init*/ + cm_init_config(); + /*lc init*/ + lc_init(); + } /*probe close sr0 peaking for switch on video*/ WRITE_VPP_REG_BITS(VPP_SRSHARP0_CTRL, 1, 0, 1); - WRITE_VPP_REG_BITS(VPP_SRSHARP1_CTRL, 1, 0, 1); + WRITE_VPP_REG_BITS(VPP_SRSHARP1_CTRL, 0, 0, 1); /*default dnlp off*/ - WRITE_VPP_REG_BITS(SRSHARP0_PK_NR_ENABLE, 0, 1, 1); - WRITE_VPP_REG_BITS(SRSHARP1_PK_NR_ENABLE, 0, 1, 1); + WRITE_VPP_REG_BITS(SRSHARP0_PK_NR_ENABLE + sr_offset[0], + 0, 1, 1); + WRITE_VPP_REG_BITS(SRSHARP1_PK_NR_ENABLE + sr_offset[1], + 0, 1, 1); WRITE_VPP_REG_BITS(VPP_VE_ENABLE_CTRL, 0, DNLP_EN_BIT, DNLP_EN_WID); /*end*/ if (cpu_after_eq(MESON_CPU_MAJOR_ID_TXL)) { - WRITE_VPP_REG_BITS(SRSHARP1_PK_FINALGAIN_HP_BP, 2, 16, 2); + WRITE_VPP_REG_BITS(SRSHARP1_PK_FINALGAIN_HP_BP + sr_offset[1], + 2, 16, 2); /*sr0 sr1 chroma filter bypass*/ - WRITE_VPP_REG(SRSHARP0_SHARP_SR2_CBIC_HCOEF0, 0x4000); - WRITE_VPP_REG(SRSHARP0_SHARP_SR2_CBIC_VCOEF0, 0x4000); - WRITE_VPP_REG(SRSHARP1_SHARP_SR2_CBIC_HCOEF0, 0x4000); - WRITE_VPP_REG(SRSHARP1_SHARP_SR2_CBIC_VCOEF0, 0x4000); + WRITE_VPP_REG(SRSHARP0_SHARP_SR2_CBIC_HCOEF0 + sr_offset[0], + 0x4000); + WRITE_VPP_REG(SRSHARP0_SHARP_SR2_CBIC_VCOEF0 + sr_offset[0], + 0x4000); + WRITE_VPP_REG(SRSHARP1_SHARP_SR2_CBIC_HCOEF0 + sr_offset[1], + 0x4000); + WRITE_VPP_REG(SRSHARP1_SHARP_SR2_CBIC_VCOEF0 + sr_offset[1], + 0x4000); } if (is_meson_gxlx_cpu()) amve_sharpness_init(); @@ -4871,7 +5451,7 @@ void init_pq_setting(void) } /* #endif*/ -static void amvecm_gamma_init(bool en) +void amvecm_gamma_init(bool en) { unsigned int i; unsigned short data[256]; @@ -5056,6 +5636,9 @@ static struct class_attribute amvecm_class_attrs[] = { amvecm_get_hdr_type_show, amvecm_get_hdr_type_store), __ATTR(dnlp_insmod, 0644, amvecm_dnlp_insmod_show, amvecm_dnlp_insmod_store), + __ATTR(lc, 0644, + amvecm_lc_show, + amvecm_lc_store), __ATTR_NULL }; @@ -5227,8 +5810,9 @@ static int aml_vecm_probe(struct platform_device *pdev) vout_register_client(&vlock_notifier_nb); /* #if (MESON_CPU_TYPE == MESON_CPU_TYPE_MESONG9TV) */ - if (is_meson_gxtvbb_cpu() || is_meson_txl_cpu() - || is_meson_txlx_cpu() || is_meson_txhd_cpu()) + if (is_meson_gxtvbb_cpu() || is_meson_txl_cpu() || + is_meson_txlx_cpu() || is_meson_txhd_cpu() || + is_meson_tl1_cpu()) init_pq_setting(); /* #endif */ vpp_get_hist_en(); diff --git a/drivers/amlogic/media/enhancement/amvecm/amvecm_drm.c b/drivers/amlogic/media/enhancement/amvecm/amvecm_drm.c new file mode 100644 index 000000000000..602ca965630e --- /dev/null +++ b/drivers/amlogic/media/enhancement/amvecm/amvecm_drm.c @@ -0,0 +1,133 @@ +/* + * drivers/amlogic/media/enhancement/amvecm/amvecm_drm.c + * + * Copyright (C) 2017 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +#include +#include +#include +#include +#include "arch/ve_regs.h" +#include "arch/vpp_regs.h" +#include "amve.h" + +void amvecm_drm_init(u32 index) +{ + amvecm_gamma_init(1); +} +EXPORT_SYMBOL(amvecm_drm_init); + +/*gamam size*/ +int amvecm_drm_get_gamma_size(u32 index) +{ + return GAMMA_SIZE; +} +EXPORT_SYMBOL(amvecm_drm_get_gamma_size); + +/*get gamma table*/ +int amvecm_drm_gamma_get(u32 index, u16 *red, u16 *green, u16 *blue) +{ + int i = 0; + + for (i = 0; i < GAMMA_SIZE; i++) { + red[i] = video_gamma_table_r.data[i] << 6; + green[i] = video_gamma_table_g.data[i] << 6; + blue[i] = video_gamma_table_b.data[i] << 6; + } + return 0; +} +EXPORT_SYMBOL(amvecm_drm_gamma_get); + +/*set gamma table*/ +int amvecm_drm_gamma_set(u32 index, struct drm_color_lut *lut, int lut_size) +{ + + int i = 0; + + if (lut_size != GAMMA_SIZE) { + pr_info("AMGAMMA_DRM: %s: lutsize is unsuitable\n", __func__); + return -1; + } + + for (i = 0; i < GAMMA_SIZE; i++) { + video_gamma_table_r.data[i] = ((lut[i].red >> 6) & 0x3ff); + video_gamma_table_g.data[i] = ((lut[i].green >> 6) & 0x3ff); + video_gamma_table_b.data[i] = ((lut[i].blue >> 6) & 0x3ff); + } + + vecm_latch_flag |= FLAG_GAMMA_TABLE_R; + vecm_latch_flag |= FLAG_GAMMA_TABLE_G; + vecm_latch_flag |= FLAG_GAMMA_TABLE_B; + + return 0; +} +EXPORT_SYMBOL(amvecm_drm_gamma_set); + +/*gamma enable*/ +int amvecm_drm_gamma_enable(u32 index) +{ + vecm_latch_flag |= FLAG_GAMMA_TABLE_EN; + return 0; +} +EXPORT_SYMBOL(amvecm_drm_gamma_enable); + +/*gamma disable*/ +int amvecm_drm_gamma_disable(u32 index) +{ + vecm_latch_flag |= FLAG_GAMMA_TABLE_DIS; + return 0; +} +EXPORT_SYMBOL(amvecm_drm_gamma_disable); + +int am_meson_ctm_set(u32 index, struct drm_color_ctm *ctm) +{ + int64_t m[9]; + int i = 0; + + for (i = 0; i < 9; i++) { + m[i] = ctm->matrix[i]; + // DRM uses signed 32.32 fixed point while Meson expects signed + // 3.10 fixed point. The following operations are performed to + // transform the numbers: + // - shift the sign bit from bit 63 to bit 12, + // - shift the 2 integer bits from from starting bit 21 to 10, + // - shift the fractional part and take the 10 significant bits. + m[i] = ((m[i] >> 51) & 0x1000) | ((m[i] >> 22) & 0xfff); + } + VSYNC_WR_MPEG_REG_BITS(VPP_POST_MATRIX_EN_CTRL, 1, 0, 1); + + VSYNC_WR_MPEG_REG(VPP_POST_MATRIX_COEF00_01, ((m[0] & 0xfff) << 16) + | (m[1] & 0xfff)); + VSYNC_WR_MPEG_REG(VPP_POST_MATRIX_COEF02_10, ((m[2] & 0xfff) << 16) + | (m[3] & 0xfff)); + VSYNC_WR_MPEG_REG(VPP_POST_MATRIX_COEF11_12, ((m[4] & 0xfff) << 16) + | (m[5] & 0xfff)); + VSYNC_WR_MPEG_REG(VPP_POST_MATRIX_COEF20_21, ((m[6] & 0xfff) << 16) + | (m[7] & 0xfff)); + VSYNC_WR_MPEG_REG(VPP_POST_MATRIX_COEF22, (m[8] & 0xfff)); + VSYNC_WR_MPEG_REG(VPP_POST_MATRIX_OFFSET0_1, 0x0); + VSYNC_WR_MPEG_REG(VPP_POST_MATRIX_OFFSET2, 0x0); + VSYNC_WR_MPEG_REG(VPP_POST_MATRIX_PRE_OFFSET0_1, 0x0); + VSYNC_WR_MPEG_REG(VPP_POST_MATRIX_PRE_OFFSET2, 0x0); + return 0; +} +EXPORT_SYMBOL(am_meson_ctm_set); + +int am_meson_ctm_disable(void) +{ + VSYNC_WR_MPEG_REG_BITS(VPP_POST_MATRIX_EN_CTRL, 0, 0, 1); + return 0; +} +EXPORT_SYMBOL(am_meson_ctm_disable); diff --git a/drivers/amlogic/media/enhancement/amvecm/arch/vpp_dolbyvision_regs.h b/drivers/amlogic/media/enhancement/amvecm/arch/vpp_dolbyvision_regs.h index 9edbc21b8b70..0651c43e527e 100644 --- a/drivers/amlogic/media/enhancement/amvecm/arch/vpp_dolbyvision_regs.h +++ b/drivers/amlogic/media/enhancement/amvecm/arch/vpp_dolbyvision_regs.h @@ -66,6 +66,8 @@ #define DOLBY_CORE3_INPUT_CSC_CRC 0x36fc #define DOLBY_CORE3_OUTPUT_CSC_CRC 0x36fd #define VPP_WRAP_OSD1_MATRIX_EN_CTRL 0x3d6d +#define VPP_WRAP_OSD2_MATRIX_EN_CTRL 0x3d7d +#define VPP_WRAP_OSD3_MATRIX_EN_CTRL 0x3dbd #define DOLBY_PATH_CTRL 0x1a0c #define VIU_MISC_CTRL1 0x1a07 diff --git a/drivers/amlogic/media/enhancement/amvecm/arch/vpp_regs.h b/drivers/amlogic/media/enhancement/amvecm/arch/vpp_regs.h index 8787e9014d0d..ec7f6397a9ea 100644 --- a/drivers/amlogic/media/enhancement/amvecm/arch/vpp_regs.h +++ b/drivers/amlogic/media/enhancement/amvecm/arch/vpp_regs.h @@ -834,6 +834,8 @@ #define VPP_POST_MATRIX_PRE_OFFSET2 0x32bc #define VPP_POST_MATRIX_EN_CTRL 0x32bd +#define VPP_POST_MATRIX_SAT 0x32c1 + #define VPP_POST2_MATRIX_COEF00_01 0x39a0 #define VPP_POST2_MATRIX_COEF02_10 0x39a1 #define VPP_POST2_MATRIX_COEF11_12 0x39a2 @@ -855,5 +857,523 @@ #define VPP_LUT3D_RAM_DATA 0x39d3 #define ENCL_VIDEO_EN 0x1ca0 + +/*TL1 VADJ1&VADJ2*/ +#define VPP_VADJ1_MISC 0x3280 +#define VPP_VADJ1_BLACK_VAL 0x3281 +#define VPP_VADJ1_Y_2 0x3282 +#define VPP_VADJ1_MA_MB_2 0x3283 +#define VPP_VADJ1_MC_MD_2 0x3284 + +#define VPP_VADJ2_MISC 0x32a0 +#define VPP_VADJ2_BLACK_VAL 0x32a1 +#define VPP_VADJ2_Y_2 0x32a2 +#define VPP_VADJ2_MA_MB_2 0x32a3 +#define VPP_VADJ2_MC_MD_2 0x32a4 + +/*TL1 add cm hist reg*/ +#define XVYCC_YSCP_REG 0x21c +#define XVYCC_USCP_REG 0x21d +#define XVYCC_VSCP_REG 0x21e +#define LUMA_ADJ0_REG 0x21f +#define LUMA_ADJ1_REG 0x220 +#define STA_WIN_XYXY0_REG 0x221 +#define STA_WIN_XYXY1_REG 0x222 +#define STA_CFG_REG 0x223 +#define STA_SAT_HIST0_REG 0x224 +#define STA_SAT_HIST1_REG 0x225 + +#define RO_CM_HUE_HIST_BIN0 0x226 +#define RO_CM_HUE_HIST_BIN1 0x227 +#define RO_CM_HUE_HIST_BIN2 0x228 +#define RO_CM_HUE_HIST_BIN3 0x229 +#define RO_CM_HUE_HIST_BIN4 0x22a +#define RO_CM_HUE_HIST_BIN5 0x22b +#define RO_CM_HUE_HIST_BIN6 0x22c +#define RO_CM_HUE_HIST_BIN7 0x22d +#define RO_CM_HUE_HIST_BIN8 0x22e +#define RO_CM_HUE_HIST_BIN9 0x22f +#define RO_CM_HUE_HIST_BIN10 0x230 +#define RO_CM_HUE_HIST_BIN11 0x231 +#define RO_CM_HUE_HIST_BIN12 0x232 +#define RO_CM_HUE_HIST_BIN13 0x233 +#define RO_CM_HUE_HIST_BIN14 0x234 +#define RO_CM_HUE_HIST_BIN15 0x235 +#define RO_CM_HUE_HIST_BIN16 0x236 +#define RO_CM_HUE_HIST_BIN17 0x237 +#define RO_CM_HUE_HIST_BIN18 0x238 +#define RO_CM_HUE_HIST_BIN19 0x239 +#define RO_CM_HUE_HIST_BIN20 0x23a +#define RO_CM_HUE_HIST_BIN21 0x23b +#define RO_CM_HUE_HIST_BIN22 0x23c +#define RO_CM_HUE_HIST_BIN23 0x23d +#define RO_CM_HUE_HIST_BIN24 0x23e +#define RO_CM_HUE_HIST_BIN25 0x23f +#define RO_CM_HUE_HIST_BIN26 0x240 +#define RO_CM_HUE_HIST_BIN27 0x241 +#define RO_CM_HUE_HIST_BIN28 0x242 +#define RO_CM_HUE_HIST_BIN29 0x243 +#define RO_CM_HUE_HIST_BIN30 0x244 +#define RO_CM_HUE_HIST_BIN31 0x245 + +#define RO_CM_SAT_HIST_BIN0 0x246 +#define RO_CM_SAT_HIST_BIN1 0x247 +#define RO_CM_SAT_HIST_BIN2 0x248 +#define RO_CM_SAT_HIST_BIN3 0x249 +#define RO_CM_SAT_HIST_BIN4 0x24a +#define RO_CM_SAT_HIST_BIN5 0x24b +#define RO_CM_SAT_HIST_BIN6 0x24c +#define RO_CM_SAT_HIST_BIN7 0x24d +#define RO_CM_SAT_HIST_BIN8 0x24e +#define RO_CM_SAT_HIST_BIN9 0x24f +#define RO_CM_SAT_HIST_BIN10 0x250 +#define RO_CM_SAT_HIST_BIN11 0x251 +#define RO_CM_SAT_HIST_BIN12 0x252 +#define RO_CM_SAT_HIST_BIN13 0x253 +#define RO_CM_SAT_HIST_BIN14 0x254 +#define RO_CM_SAT_HIST_BIN15 0x255 +#define RO_CM_SAT_HIST_BIN16 0x256 +#define RO_CM_SAT_HIST_BIN17 0x257 +#define RO_CM_SAT_HIST_BIN18 0x258 +#define RO_CM_SAT_HIST_BIN19 0x259 +#define RO_CM_SAT_HIST_BIN20 0x25a +#define RO_CM_SAT_HIST_BIN21 0x25b +#define RO_CM_SAT_HIST_BIN22 0x25c +#define RO_CM_SAT_HIST_BIN23 0x25d +#define RO_CM_SAT_HIST_BIN24 0x25e +#define RO_CM_SAT_HIST_BIN25 0x25f +#define RO_CM_SAT_HIST_BIN26 0x260 +#define RO_CM_SAT_HIST_BIN27 0x261 +#define RO_CM_SAT_HIST_BIN28 0x262 +#define RO_CM_SAT_HIST_BIN29 0x263 +#define RO_CM_SAT_HIST_BIN30 0x264 +#define RO_CM_SAT_HIST_BIN31 0x265 + +#define RO_CM_BLK_BIN 0x266 +#define RO_CM_BRT_BIN 0x267 +/*TL1 cm HIST reg end*/ + +/*TL1 SHARPNESS REG*/ +#define SHARP0_SHARP_HVSIZE 0x3e00 +#define SHARP0_SHARP_HVBLANK_NUM 0x3e01 +#define SHARP0_NR_GAUSSIAN_MODE 0x3e02 +#define SHARP0_PK_CON_2CIRHPGAIN_TH_RATE 0x3e05 +#define SHARP0_PK_CON_2CIRHPGAIN_LIMIT 0x3e06 +#define SHARP0_PK_CON_2CIRBPGAIN_TH_RATE 0x3e07 +#define SHARP0_PK_CON_2CIRBPGAIN_LIMIT 0x3e08 +#define SHARP0_PK_CON_2DRTHPGAIN_TH_RATE 0x3e09 +#define SHARP0_PK_CON_2DRTHPGAIN_LIMIT 0x3e0a +#define SHARP0_PK_CON_2DRTBPGAIN_TH_RATE 0x3e0b +#define SHARP0_PK_CON_2DRTBPGAIN_LIMIT 0x3e0c +#define SHARP0_PK_CIRFB_LPF_MODE 0x3e0d +#define SHARP0_PK_DRTFB_LPF_MODE 0x3e0e +#define SHARP0_PK_CIRFB_HP_CORING 0x3e0f +#define SHARP0_PK_CIRFB_BP_CORING 0x3e10 +#define SHARP0_PK_DRTFB_HP_CORING 0x3e11 +#define SHARP0_PK_DRTFB_BP_CORING 0x3e12 +#define SHARP0_PK_CIRFB_BLEND_GAIN 0x3e13 +#define SHARP0_NR_ALPY_SSD_GAIN_OFST 0x3e14 +#define SHARP0_NR_ALP0Y_ERR2CURV_TH_RATE 0x3e15 +#define SHARP0_NR_ALP0Y_ERR2CURV_LIMIT 0x3e16 +#define SHARP0_NR_ALP0C_ERR2CURV_TH_RATE 0x3e17 +#define SHARP0_NR_ALP0C_ERR2CURV_LIMIT 0x3e18 +#define SHARP0_NR_ALP0_MIN_MAX 0x3e19 +#define SHARP0_NR_ALP1_MIERR_CORING 0x3e1a +#define SHARP0_NR_ALP1_ERR2CURV_TH_RATE 0x3e1b +#define SHARP0_NR_ALP1_ERR2CURV_LIMIT 0x3e1c +#define SHARP0_NR_ALP1_MIN_MAX 0x3e1d +#define SHARP0_PK_ALP2_MIERR_CORING 0x3e1e +#define SHARP0_PK_ALP2_ERR2CURV_TH_RATE 0x3e1f +#define SHARP0_PK_ALP2_ERR2CURV_LIMIT 0x3e20 +#define SHARP0_PK_ALP2_MIN_MAX 0x3e21 +#define SHARP0_PK_FINALGAIN_HP_BP 0x3e22 +#define SHARP0_PK_OS_HORZ_CORE_GAIN 0x3e23 +#define SHARP0_PK_OS_VERT_CORE_GAIN 0x3e24 +#define SHARP0_PK_OS_ADPT_MISC 0x3e25 +#define SHARP0_PK_OS_STATIC 0x3e26 +#define SHARP0_PK_NR_ENABLE 0x3e27 +#define SHARP0_PK_DRT_SAD_MISC 0x3e28 +#define SHARP0_NR_TI_DNLP_BLEND 0x3e29 +#define SHARP0_TI_DIR_CORE_ALPHA 0x3e2a +#define SHARP0_CTI_DIR_ALPHA 0x3e2b +#define SHARP0_LTI_CTI_DF_GAIN 0x3e2c +#define SHARP0_LTI_CTI_DIR_AC_DBG 0x3e2d +#define SHARP0_HCTI_FLT_CLP_DC 0x3e2e +#define SHARP0_HCTI_BST_GAIN 0x3e2f +#define SHARP0_HCTI_BST_CORE 0x3e30 +#define SHARP0_HCTI_CON_2_GAIN_0 0x3e31 +#define SHARP0_HCTI_CON_2_GAIN_1 0x3e32 +#define SHARP0_HCTI_OS_MARGIN 0x3e33 +#define SHARP0_HLTI_FLT_CLP_DC 0x3e34 +#define SHARP0_HLTI_BST_GAIN 0x3e35 +#define SHARP0_HLTI_BST_CORE 0x3e36 +#define SHARP0_HLTI_CON_2_GAIN_0 0x3e37 +#define SHARP0_HLTI_CON_2_GAIN_1 0x3e38 +#define SHARP0_HLTI_OS_MARGIN 0x3e39 +#define SHARP0_VLTI_FLT_CON_CLP 0x3e3a +#define SHARP0_VLTI_BST_GAIN 0x3e3b +#define SHARP0_VLTI_BST_CORE 0x3e3c +#define SHARP0_VLTI_CON_2_GAIN_0 0x3e3d +#define SHARP0_VLTI_CON_2_GAIN_1 0x3e3e +#define SHARP0_VCTI_FLT_CON_CLP 0x3e3f +#define SHARP0_VCTI_BST_GAIN 0x3e40 +#define SHARP0_VCTI_BST_CORE 0x3e41 +#define SHARP0_VCTI_CON_2_GAIN_0 0x3e42 +#define SHARP0_VCTI_CON_2_GAIN_1 0x3e43 +#define SHARP0_SHARP_3DLIMIT 0x3e44 +#define SHARP0_DNLP_EN 0x3e45 +#define SHARP0_DEMO_CRTL 0x3e56 +#define SHARP0_SHARP_SR2_CTRL 0x3e57 +#define SHARP0_SHARP_SR2_YBIC_HCOEF0 0x3e58 +#define SHARP0_SHARP_SR2_YBIC_HCOEF1 0x3e59 +#define SHARP0_SHARP_SR2_CBIC_HCOEF0 0x3e5a +#define SHARP0_SHARP_SR2_CBIC_HCOEF1 0x3e5b +#define SHARP0_SHARP_SR2_YBIC_VCOEF0 0x3e5c +#define SHARP0_SHARP_SR2_YBIC_VCOEF1 0x3e5d +#define SHARP0_SHARP_SR2_CBIC_VCOEF0 0x3e5e +#define SHARP0_SHARP_SR2_CBIC_VCOEF1 0x3e5f +#define SHARP0_SHARP_SR2_MISC 0x3e60 +#define SHARP0_SR3_SAD_CTRL 0x3e61 +#define SHARP0_SR3_PK_CTRL0 0x3e62 +#define SHARP0_SR3_PK_CTRL1 0x3e63 +#define SHARP0_DEJ_CTRL 0x3e64 +#define SHARP0_DEJ_ALPHA 0x3e65 +#define SHARP0_SR3_DRTLPF_EN 0x3e66 +#define SHARP0_SR3_DRTLPF_ALPHA_0 0x3e67 +#define SHARP0_SR3_DRTLPF_ALPHA_1 0x3e68 +#define SHARP0_SR3_DRTLPF_ALPHA_2 0x3e69 +#define SHARP0_SR3_DRTLPF_ALPHA_OFST 0x3e6a +#define SHARP0_SR3_DERING_CTRL 0x3e6b +#define SHARP0_SR3_DERING_LUMA2PKGAIN_0TO3 0x3e6c +#define SHARP0_SR3_DERING_LUMA2PKGAIN_4TO6 0x3e6d +#define SHARP0_SR3_DERING_LUMA2PKOS_0TO3 0x3e6e +#define SHARP0_SR3_DERING_LUMA2PKOS_4TO6 0x3e6f +#define SHARP0_SR3_DERING_GAINVS_MADSAD 0x3e70 +#define SHARP0_SR3_DERING_GAINVS_VR2MAX 0x3e71 +#define SHARP0_SR3_DERING_PARAM0 0x3e72 +#define SHARP0_SR3_DRTLPF_THETA 0x3e73 +#define SHARP0_SATPRT_CTRL 0x3e74 +#define SHARP0_SATPRT_DIVM 0x3e75 +#define SHARP0_DB_FLT_CTRL 0x3e77 +#define SHARP0_DB_FLT_YC_THRD 0x3e78 +#define SHARP0_DB_FLT_RANDLUT 0x3e79 +#define SHARP0_DB_FLT_PXI_THRD 0x3e7a +#define SHARP0_DB_FLT_SEED_Y 0x3e7b +#define SHARP0_DB_FLT_SEED_U 0x3e7c +#define SHARP0_DB_FLT_SEED_V 0x3e7d +#define SHARP0_PKGAIN_VSLUMA_LUT_L 0x3e7e +#define SHARP0_PKGAIN_VSLUMA_LUT_H 0x3e7f +#define SHARP0_PKOSHT_VSLUMA_LUT_L 0x3e80 +#define SHARP0_PKOSHT_VSLUMA_LUT_H 0x3e81 +#define SHARP0_SATPRT_LMT_RGB1 0x3e82 +#define SHARP0_SATPRT_LMT_RGB2 0x3e83 +#define SHARP0_SHARP_GATE_CLK_CTRL_0 0x3e84 +#define SHARP0_SHARP_GATE_CLK_CTRL_1 0x3e85 +#define SHARP0_SHARP_GATE_CLK_CTRL_2 0x3e86 +#define SHARP0_SHARP_GATE_CLK_CTRL_3 0x3e87 +#define SHARP0_SHARP_DPS_CTRL 0x3e88 +#define SHARP0_DNLP_00 0x3e90 +#define SHARP0_DNLP_01 0x3e91 +#define SHARP0_DNLP_02 0x3e92 +#define SHARP0_DNLP_03 0x3e93 +#define SHARP0_DNLP_04 0x3e94 +#define SHARP0_DNLP_05 0x3e95 +#define SHARP0_DNLP_06 0x3e96 +#define SHARP0_DNLP_07 0x3e97 +#define SHARP0_DNLP_08 0x3e98 +#define SHARP0_DNLP_09 0x3e99 +#define SHARP0_DNLP_10 0x3e9a +#define SHARP0_DNLP_11 0x3e9b +#define SHARP0_DNLP_12 0x3e9c +#define SHARP0_DNLP_13 0x3e9d +#define SHARP0_DNLP_14 0x3e9e +#define SHARP0_DNLP_15 0x3e9f +#define SHARP0_DNLP_16 0x3ea0 +#define SHARP0_DNLP_17 0x3ea1 +#define SHARP0_DNLP_18 0x3ea2 +#define SHARP0_DNLP_19 0x3ea3 +#define SHARP0_DNLP_20 0x3ea4 +#define SHARP0_DNLP_21 0x3ea5 +#define SHARP0_DNLP_22 0x3ea6 +#define SHARP0_DNLP_23 0x3ea7 +#define SHARP0_DNLP_24 0x3ea8 +#define SHARP0_DNLP_25 0x3ea9 +#define SHARP0_DNLP_26 0x3eaa +#define SHARP0_DNLP_27 0x3eab +#define SHARP0_DNLP_28 0x3eac +#define SHARP0_DNLP_29 0x3ead +#define SHARP0_DNLP_30 0x3eae +#define SHARP0_DNLP_31 0x3eaf +#define SHARP0_SHARP_SYNC_CTRL 0x3eb0 +#define SHARP1_SHARP_HVSIZE 0x3f00 +#define SHARP1_SHARP_HVBLANK_NUM 0x3f01 +#define SHARP1_NR_GAUSSIAN_MODE 0x3f02 +#define SHARP1_PK_CON_2CIRHPGAIN_TH_RATE 0x3f05 +#define SHARP1_PK_CON_2CIRHPGAIN_LIMIT 0x3f06 +#define SHARP1_PK_CON_2CIRBPGAIN_TH_RATE 0x3f07 +#define SHARP1_PK_CON_2CIRBPGAIN_LIMIT 0x3f08 +#define SHARP1_PK_CON_2DRTHPGAIN_TH_RATE 0x3f09 +#define SHARP1_PK_CON_2DRTHPGAIN_LIMIT 0x3f0a +#define SHARP1_PK_CON_2DRTBPGAIN_TH_RATE 0x3f0b +#define SHARP1_PK_CON_2DRTBPGAIN_LIMIT 0x3f0c +#define SHARP1_PK_CIRFB_LPF_MODE 0x3f0d +#define SHARP1_PK_DRTFB_LPF_MODE 0x3f0e +#define SHARP1_PK_CIRFB_HP_CORING 0x3f0f +#define SHARP1_PK_CIRFB_BP_CORING 0x3f10 +#define SHARP1_PK_DRTFB_HP_CORING 0x3f11 +#define SHARP1_PK_DRTFB_BP_CORING 0x3f12 +#define SHARP1_PK_CIRFB_BLEND_GAIN 0x3f13 +#define SHARP1_NR_ALPY_SSD_GAIN_OFST 0x3f14 +#define SHARP1_NR_ALP0Y_ERR2CURV_TH_RATE 0x3f15 +#define SHARP1_NR_ALP0Y_ERR2CURV_LIMIT 0x3f16 +#define SHARP1_NR_ALP0C_ERR2CURV_TH_RATE 0x3f17 +#define SHARP1_NR_ALP0C_ERR2CURV_LIMIT 0x3f18 +#define SHARP1_NR_ALP0_MIN_MAX 0x3f19 +#define SHARP1_NR_ALP1_MIERR_CORING 0x3f1a +#define SHARP1_NR_ALP1_ERR2CURV_TH_RATE 0x3f1b +#define SHARP1_NR_ALP1_ERR2CURV_LIMIT 0x3f1c +#define SHARP1_NR_ALP1_MIN_MAX 0x3f1d +#define SHARP1_PK_ALP2_MIERR_CORING 0x3f1e +#define SHARP1_PK_ALP2_ERR2CURV_TH_RATE 0x3f1f +#define SHARP1_PK_ALP2_ERR2CURV_LIMIT 0x3f20 +#define SHARP1_PK_ALP2_MIN_MAX 0x3f21 +#define SHARP1_PK_FINALGAIN_HP_BP 0x3f22 +#define SHARP1_PK_OS_HORZ_CORE_GAIN 0x3f23 +#define SHARP1_PK_OS_VERT_CORE_GAIN 0x3f24 +#define SHARP1_PK_OS_ADPT_MISC 0x3f25 +#define SHARP1_PK_OS_STATIC 0x3f26 +#define SHARP1_PK_NR_ENABLE 0x3f27 +#define SHARP1_PK_DRT_SAD_MISC 0x3f28 +#define SHARP1_NR_TI_DNLP_BLEND 0x3f29 +#define SHARP1_TI_DIR_CORE_ALPHA 0x3f2a +#define SHARP1_CTI_DIR_ALPHA 0x3f2b +#define SHARP1_LTI_CTI_DF_GAIN 0x3f2c +#define SHARP1_LTI_CTI_DIR_AC_DBG 0x3f2d +#define SHARP1_HCTI_FLT_CLP_DC 0x3f2e +#define SHARP1_HCTI_BST_GAIN 0x3f2f +#define SHARP1_HCTI_BST_CORE 0x3f30 +#define SHARP1_HCTI_CON_2_GAIN_0 0x3f31 +#define SHARP1_HCTI_CON_2_GAIN_1 0x3f32 +#define SHARP1_HCTI_OS_MARGIN 0x3f33 +#define SHARP1_HLTI_FLT_CLP_DC 0x3f34 +#define SHARP1_HLTI_BST_GAIN 0x3f35 +#define SHARP1_HLTI_BST_CORE 0x3f36 +#define SHARP1_HLTI_CON_2_GAIN_0 0x3f37 +#define SHARP1_HLTI_CON_2_GAIN_1 0x3f38 +#define SHARP1_HLTI_OS_MARGIN 0x3f39 +#define SHARP1_VLTI_FLT_CON_CLP 0x3f3a +#define SHARP1_VLTI_BST_GAIN 0x3f3b +#define SHARP1_VLTI_BST_CORE 0x3f3c +#define SHARP1_VLTI_CON_2_GAIN_0 0x3f3d +#define SHARP1_VLTI_CON_2_GAIN_1 0x3f3e +#define SHARP1_VCTI_FLT_CON_CLP 0x3f3f +#define SHARP1_VCTI_BST_GAIN 0x3f40 +#define SHARP1_VCTI_BST_CORE 0x3f41 +#define SHARP1_VCTI_CON_2_GAIN_0 0x3f42 +#define SHARP1_VCTI_CON_2_GAIN_1 0x3f43 +#define SHARP1_SHARP_3DLIMIT 0x3f44 +#define SHARP1_DNLP_EN 0x3f45 +#define SHARP1_DEMO_CRTL 0x3f56 +#define SHARP1_SHARP_SR2_CTRL 0x3f57 +#define SHARP1_SHARP_SR2_YBIC_HCOEF0 0x3f58 +#define SHARP1_SHARP_SR2_YBIC_HCOEF1 0x3f59 +#define SHARP1_SHARP_SR2_CBIC_HCOEF0 0x3f5a +#define SHARP1_SHARP_SR2_CBIC_HCOEF1 0x3f5b +#define SHARP1_SHARP_SR2_YBIC_VCOEF0 0x3f5c +#define SHARP1_SHARP_SR2_YBIC_VCOEF1 0x3f5d +#define SHARP1_SHARP_SR2_CBIC_VCOEF0 0x3f5e +#define SHARP1_SHARP_SR2_CBIC_VCOEF1 0x3f5f +#define SHARP1_SHARP_SR2_MISC 0x3f60 +#define SHARP1_SR3_SAD_CTRL 0x3f61 +#define SHARP1_SR3_PK_CTRL0 0x3f62 +#define SHARP1_SR3_PK_CTRL1 0x3f63 +#define SHARP1_DEJ_CTRL 0x3f64 +#define SHARP1_DEJ_ALPHA 0x3f65 +#define SHARP1_SR3_DRTLPF_EN 0x3f66 +#define SHARP1_SR3_DRTLPF_ALPHA_0 0x3f67 +#define SHARP1_SR3_DRTLPF_ALPHA_1 0x3f68 +#define SHARP1_SR3_DRTLPF_ALPHA_2 0x3f69 +#define SHARP1_SR3_DRTLPF_ALPHA_OFST 0x3f6a +#define SHARP1_SR3_DERING_CTRL 0x3f6b +#define SHARP1_SR3_DERING_LUMA2PKGAIN_0TO3 0x3f6c +#define SHARP1_SR3_DERING_LUMA2PKGAIN_4TO6 0x3f6d +#define SHARP1_SR3_DERING_LUMA2PKOS_0TO3 0x3f6e +#define SHARP1_SR3_DERING_LUMA2PKOS_4TO6 0x3f6f +#define SHARP1_SR3_DERING_GAINVS_MADSAD 0x3f70 +#define SHARP1_SR3_DERING_GAINVS_VR2MAX 0x3f71 +#define SHARP1_SR3_DERING_PARAM0 0x3f72 +#define SHARP1_SR3_DRTLPF_THETA 0x3f73 +#define SHARP1_SATPRT_CTRL 0x3f74 +#define SHARP1_SATPRT_DIVM 0x3f75 +#define SHARP1_DB_FLT_CTRL 0x3f77 +#define SHARP1_DB_FLT_YC_THRD 0x3f78 +#define SHARP1_DB_FLT_RANDLUT 0x3f79 +#define SHARP1_DB_FLT_PXI_THRD 0x3f7a +#define SHARP1_DB_FLT_SEED_Y 0x3f7b +#define SHARP1_DB_FLT_SEED_U 0x3f7c +#define SHARP1_DB_FLT_SEED_V 0x3f7d +#define SHARP1_PKGAIN_VSLUMA_LUT_L 0x3f7e +#define SHARP1_PKGAIN_VSLUMA_LUT_H 0x3f7f +#define SHARP1_PKOSHT_VSLUMA_LUT_L 0x3f80 +#define SHARP1_PKOSHT_VSLUMA_LUT_H 0x3f81 +#define SHARP1_SATPRT_LMT_RGB1 0x3f82 +#define SHARP1_SATPRT_LMT_RGB2 0x3f83 +#define SHARP1_SHARP_GATE_CLK_CTRL_0 0x3f84 +#define SHARP1_SHARP_GATE_CLK_CTRL_1 0x3f85 +#define SHARP1_SHARP_GATE_CLK_CTRL_2 0x3f86 +#define SHARP1_SHARP_GATE_CLK_CTRL_3 0x3f87 +#define SHARP1_SHARP_DPS_CTRL 0x3f88 +#define SHARP1_DNLP_00 0x3f90 +#define SHARP1_DNLP_01 0x3f91 +#define SHARP1_DNLP_02 0x3f92 +#define SHARP1_DNLP_03 0x3f93 +#define SHARP1_DNLP_04 0x3f94 +#define SHARP1_DNLP_05 0x3f95 +#define SHARP1_DNLP_06 0x3f96 +#define SHARP1_DNLP_07 0x3f97 +#define SHARP1_DNLP_08 0x3f98 +#define SHARP1_DNLP_09 0x3f99 +#define SHARP1_DNLP_10 0x3f9a +#define SHARP1_DNLP_11 0x3f9b +#define SHARP1_DNLP_12 0x3f9c +#define SHARP1_DNLP_13 0x3f9d +#define SHARP1_DNLP_14 0x3f9e +#define SHARP1_DNLP_15 0x3f9f +#define SHARP1_DNLP_16 0x3fa0 +#define SHARP1_DNLP_17 0x3fa1 +#define SHARP1_DNLP_18 0x3fa2 +#define SHARP1_DNLP_19 0x3fa3 +#define SHARP1_DNLP_20 0x3fa4 +#define SHARP1_DNLP_21 0x3fa5 +#define SHARP1_DNLP_22 0x3fa6 +#define SHARP1_DNLP_23 0x3fa7 +#define SHARP1_DNLP_24 0x3fa8 +#define SHARP1_DNLP_25 0x3fa9 +#define SHARP1_DNLP_26 0x3faa +#define SHARP1_DNLP_27 0x3fab +#define SHARP1_DNLP_28 0x3fac +#define SHARP1_DNLP_29 0x3fad +#define SHARP1_DNLP_30 0x3fae +#define SHARP1_DNLP_31 0x3faf +#define SHARP1_SHARP_SYNC_CTRL 0x3fb0 +/*TL1 SHARPNESS REG END*/ + +/*LC register begin*/ +#define SRSHARP1_LC_INPUT_MUX 0x3fb1 +#define SRSHARP1_LC_TOP_CTRL 0x3fc0 +#define SRSHARP1_LC_HV_NUM 0x3fc1 +#define SRSHARP1_LC_SAT_LUT_0_1 0x3fc2 +#define SRSHARP1_LC_SAT_LUT_2_3 0x3fc3 +#define SRSHARP1_LC_SAT_LUT_4_5 0x3fc4 +#define SRSHARP1_LC_SAT_LUT_6_7 0x3fc5 +#define SRSHARP1_LC_SAT_LUT_8_9 0x3fc6 +#define SRSHARP1_LC_SAT_LUT_10_11 0x3fc7 +#define SRSHARP1_LC_SAT_LUT_12_13 0x3fc8 +#define SRSHARP1_LC_SAT_LUT_14_15 0x3fc9 +#define SRSHARP1_LC_SAT_LUT_16_17 0x3fca +#define SRSHARP1_LC_SAT_LUT_18_19 0x3fcb +#define SRSHARP1_LC_SAT_LUT_20_21 0x3fcc +#define SRSHARP1_LC_SAT_LUT_22_23 0x3fcd +#define SRSHARP1_LC_SAT_LUT_24_25 0x3fce +#define SRSHARP1_LC_SAT_LUT_26_27 0x3fcf +#define SRSHARP1_LC_SAT_LUT_28_29 0x3fd0 +#define SRSHARP1_LC_SAT_LUT_30_31 0x3fd1 +#define SRSHARP1_LC_SAT_LUT_32_33 0x3fd2 +#define SRSHARP1_LC_SAT_LUT_34_35 0x3fd3 +#define SRSHARP1_LC_SAT_LUT_36_37 0x3fd4 +#define SRSHARP1_LC_SAT_LUT_38_39 0x3fd5 +#define SRSHARP1_LC_SAT_LUT_40_41 0x3fd6 +#define SRSHARP1_LC_SAT_LUT_42_43 0x3fd7 +#define SRSHARP1_LC_SAT_LUT_44_45 0x3fd8 +#define SRSHARP1_LC_SAT_LUT_46_47 0x3fd9 +#define SRSHARP1_LC_SAT_LUT_48_49 0x3fda +#define SRSHARP1_LC_SAT_LUT_50_51 0x3fdb +#define SRSHARP1_LC_SAT_LUT_52_53 0x3fdc +#define SRSHARP1_LC_SAT_LUT_54_55 0x3fdd +#define SRSHARP1_LC_SAT_LUT_56_57 0x3fde +#define SRSHARP1_LC_SAT_LUT_58_59 0x3fdf +#define SRSHARP1_LC_SAT_LUT_60_61 0x3fe0 +#define SRSHARP1_LC_SAT_LUT_62 0x3fe1 +#define SRSHARP1_LC_CURVE_BLK_HIDX_0_1 0x3fe2 +#define SRSHARP1_LC_CURVE_BLK_HIDX_2_3 0x3fe3 +#define SRSHARP1_LC_CURVE_BLK_HIDX_4_5 0x3fe4 +#define SRSHARP1_LC_CURVE_BLK_HIDX_6_7 0x3fe5 +#define SRSHARP1_LC_CURVE_BLK_HIDX_8_9 0x3fe6 +#define SRSHARP1_LC_CURVE_BLK_HIDX_10_11 0x3fe7 +#define SRSHARP1_LC_CURVE_BLK_HIDX_12 0x3fe8 +#define SRSHARP1_LC_CURVE_BLK_VIDX_0_1 0x3fe9 +#define SRSHARP1_LC_CURVE_BLK_VIDX_2_3 0x3fea +#define SRSHARP1_LC_CURVE_BLK_VIDX_4_5 0x3feb +#define SRSHARP1_LC_CURVE_BLK_VIDX_6_7 0x3fec +#define SRSHARP1_LC_CURVE_BLK_VIDX_8 0x3fed +#define SRSHARP1_LC_YUV2RGB_MAT_0_1 0x3fee +#define SRSHARP1_LC_YUV2RGB_MAT_2_3 0x3fef +#define SRSHARP1_LC_YUV2RGB_MAT_4_5 0x3ff0 +#define SRSHARP1_LC_YUV2RGB_MAT_6_7 0x3ff1 +#define SRSHARP1_LC_YUV2RGB_MAT_8 0x3ff2 +#define SRSHARP1_LC_RGB2YUV_MAT_0_1 0x3ff3 +#define SRSHARP1_LC_RGB2YUV_MAT_2_3 0x3ff4 +#define SRSHARP1_LC_RGB2YUV_MAT_4_5 0x3ff5 +#define SRSHARP1_LC_RGB2YUV_MAT_6_7 0x3ff6 +#define SRSHARP1_LC_RGB2YUV_MAT_8 0x3ff7 +#define SRSHARP1_LC_YUV2RGB_OFST 0x3ff8 +#define SRSHARP1_LC_YUV2RGB_CLIP 0x3ff9 +#define SRSHARP1_LC_RGB2YUV_OFST 0x3ffa +#define SRSHARP1_LC_RGB2YUV_CLIP 0x3ffb +#define SRSHARP1_LC_MAP_RAM_CTRL 0x3ffc +#define SRSHARP1_LC_MAP_RAM_ADDR 0x3ffd +#define SRSHARP1_LC_MAP_RAM_DATA 0x3ffe + +#define LC_CURVE_CTRL 0x4000 +#define LC_CURVE_HV_NUM 0x4001 +#define LC_CURVE_LMT_RAT 0x4002 +#define LC_CURVE_CONTRAST_LH 0x4003 +#define LC_CURVE_CONTRAST__LMT_LH 0x4004 +#define LC_CURVE_CONTRAST_SCL_LH 0x4005 +#define LC_CURVE_CONTRAST_BVN_LH 0x4006 +#define LC_CURVE_MISC0 0x4007 +#define LC_CURVE_YPKBV_RAT 0x4008 +#define LC_CURVE_YPKBV_SLP_LMT 0x4009 +#define LC_CURVE_YMINVAL_LMT_0_1 0x400a +#define LC_CURVE_YMINVAL_LMT_2_3 0x400b +#define LC_CURVE_YMINVAL_LMT_4_5 0x400c +#define LC_CURVE_YMINVAL_LMT_6_7 0x400d +#define LC_CURVE_YMINVAL_LMT_8_9 0x400e +#define LC_CURVE_YMINVAL_LMT_10_11 0x400f +#define LC_CURVE_YPKBV_YMAXVAL_LMT_0_1 0x4010 +#define LC_CURVE_YPKBV_YMAXVAL_LMT_2_3 0x4011 +#define LC_CURVE_YPKBV_YMAXVAL_LMT_4_5 0x4012 +#define LC_CURVE_YPKBV_YMAXVAL_LMT_6_7 0x4013 +#define LC_CURVE_YPKBV_YMAXVAL_LMT_8_9 0x4014 +#define LC_CURVE_YPKBV_YMAXVAL_LMT_10_11 0x4015 +#define LC_CURVE_HISTVLD_THRD 0x4016 +#define LC_CURVE_BB_MUTE_THRD 0x4017 +#define LC_CURVE_INT_STATUS 0x4018 +#define LC_CURVE_RAM_CTRL 0x4020 +#define LC_CURVE_RAM_ADDR 0x4021 +#define LC_CURVE_RAM_DATA 0x4022 + +#define LC_STTS_GCLK_CTRL0 0x4028 +#define LC_STTS_CTRL0 0x4029 +#define LC_STTS_WIDTHM1_HEIGHTM1 0x402a +#define LC_STTS_MATRIX_COEF00_01 0x402b +#define LC_STTS_MATRIX_COEF02_10 0x402c +#define LC_STTS_MATRIX_COEF11_12 0x402d +#define LC_STTS_MATRIX_COEF20_21 0x402e +#define LC_STTS_MATRIX_COEF22 0x402f +#define LC_STTS_MATRIX_OFFSET0_1 0x4030 +#define LC_STTS_MATRIX_OFFSET2 0x4031 +#define LC_STTS_MATRIX_PRE_OFFSET0_1 0x4032 +#define LC_STTS_MATRIX_PRE_OFFSET2 0x4033 +#define LC_STTS_MATRIX_HL_COLOR 0x4034 +#define LC_STTS_MATRIX_PROBE_POS 0x4035 +#define LC_STTS_MATRIX_PROBE_COLOR 0x4036 +#define LC_STTS_HIST_REGION_IDX 0x4037 +#define LC_STTS_HIST_SET_REGION 0x4038 +#define LC_STTS_HIST_READ_REGION 0x4039 +#define LC_STTS_HIST_START_RD_REGION 0x403a +#define LC_STTS_WHITE_INFO 0x403b +#define LC_STTS_BLACK_INFO 0x403c +/*LC register end*/ #endif diff --git a/drivers/amlogic/media/enhancement/amvecm/bitdepth.c b/drivers/amlogic/media/enhancement/amvecm/bitdepth.c index 0b9e159cec86..558fffb092fa 100644 --- a/drivers/amlogic/media/enhancement/amvecm/bitdepth.c +++ b/drivers/amlogic/media/enhancement/amvecm/bitdepth.c @@ -396,13 +396,13 @@ void vpp_set_12bit_datapath_g12a(void) vpp_set_vd1_preblend_mux(0); vpp_set_vd1_postblend_mux(0); vpp_set_vd1_postblend_en(1); - vpp_set_vd1_gate(0x55); + vpp_set_vd1_gate(0x0); vpp_set_vd2_preblend_mux(0); vpp_set_vd2_postblend_mux(0); vpp_set_vd2_postblend_en(0); vpp_set_vd2_ext_mod(0); vpp_set_vd2_bypass_dolby(1); - vpp_set_vd2_gate(0x55); + vpp_set_vd2_gate(0x0); } } diff --git a/drivers/amlogic/media/enhancement/amvecm/dnlp_cal.c b/drivers/amlogic/media/enhancement/amvecm/dnlp_cal.c index f2346d3e1ecf..299e4f4083c8 100644 --- a/drivers/amlogic/media/enhancement/amvecm/dnlp_cal.c +++ b/drivers/amlogic/media/enhancement/amvecm/dnlp_cal.c @@ -11,10 +11,12 @@ #include "arch/vpp_regs.h" #include #include "dnlp_algorithm/dnlp_alg.h" +#include bool ve_en; unsigned int ve_dnlp_rt; ulong ve_dnlp_lpf[64], ve_dnlp_reg[16]; +ulong ve_dnlp_reg_v2[32]; ulong ve_dnlp_reg_def[16] = { 0x0b070400, 0x1915120e, 0x2723201c, 0x35312e2a, 0x47423d38, 0x5b56514c, 0x6f6a6560, 0x837e7974, @@ -448,14 +450,28 @@ void ve_dnlp_calculate_reg(void) { ulong i = 0, j = 0, cur = 0, data = 0, offset = ve_dnlp_rt ? (1 << (ve_dnlp_rt - 1)) : 0; - for (i = 0; i < 16; i++) { - ve_dnlp_reg[i] = 0; - cur = i << 2; - for (j = 0; j < 4; j++) { - data = (ve_dnlp_lpf[cur + j] + offset) >> ve_dnlp_rt; - if (data > 255) - data = 255; - ve_dnlp_reg[i] |= data << (j << 3); + if (is_meson_tl1_cpu()) { + for (i = 0; i < 32; i++) { + ve_dnlp_reg_v2[i] = 0; + cur = i << 1; + for (j = 0; j < 2; j++) { + data = ve_dnlp_lpf[cur + j] << 2; + if (data > 1023) + data = 1023; + ve_dnlp_reg_v2[i] |= data << (j << 4); + } + } + } else { + for (i = 0; i < 16; i++) { + ve_dnlp_reg[i] = 0; + cur = i << 2; + for (j = 0; j < 4; j++) { + data = (ve_dnlp_lpf[cur + j] + offset) >> + ve_dnlp_rt; + if (data > 255) + data = 255; + ve_dnlp_reg[i] |= data << (j << 3); + } } } } diff --git a/drivers/amlogic/media/enhancement/amvecm/dnlp_cal.h b/drivers/amlogic/media/enhancement/amvecm/dnlp_cal.h index 15f938502fff..6c3a99e9c6cd 100644 --- a/drivers/amlogic/media/enhancement/amvecm/dnlp_cal.h +++ b/drivers/amlogic/media/enhancement/amvecm/dnlp_cal.h @@ -75,6 +75,7 @@ extern unsigned int ve_dnlp_rt; extern unsigned int ve_dnlp_luma_sum; extern ulong ve_dnlp_lpf[64]; extern ulong ve_dnlp_reg[16]; +extern ulong ve_dnlp_reg_v2[32]; extern ulong ve_dnlp_reg_def[16]; extern struct dnlp_parse_cmd_s dnlp_parse_cmd[]; diff --git a/drivers/amlogic/media/enhancement/amvecm/hdr/am_hdr10_plus.c b/drivers/amlogic/media/enhancement/amvecm/hdr/am_hdr10_plus.c new file mode 100644 index 000000000000..ec9fbebc9cd6 --- /dev/null +++ b/drivers/amlogic/media/enhancement/amvecm/hdr/am_hdr10_plus.c @@ -0,0 +1,785 @@ +/* + * drivers/amlogic/media/enhancement/amvecm/amcsc.c + * + * Copyright (C) 2017 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +/* Standard Linux headers */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "am_hdr10_plus.h" + +uint debug_hdr; +#define pr_hdr(fmt, args...)\ + do {\ + if (debug_hdr)\ + pr_info(fmt, ## args);\ + } while (0) + +#define HDR10_PLUS_VERSION "hdr10_plus v1_20181024" + +struct hdr_plus_bits_s sei_md_bits = { + .len_itu_t_t35_country_code = 8, + .len_itu_t_t35_terminal_provider_code = 16, + .len_itu_t_t35_terminal_provider_oriented_code = 16, + .len_application_identifier = 8, + .len_application_version = 8, + .len_num_windows = 2, + .len_window_upper_left_corner_x = 16, + .len_window_upper_left_corner_y = 16, + .len_window_lower_right_corner_x = 16, + .len_window_lower_right_corner_y = 16, + .len_center_of_ellipse_x = 16, + .len_center_of_ellipse_y = 16, + .len_rotation_angle = 8, + .len_semimajor_axis_internal_ellipse = 16, + .len_semimajor_axis_external_ellipse = 16, + .len_semiminor_axis_external_ellipse = 16, + .len_overlap_process_option = 1, + .len_tgt_sys_disp_max_lumi = 27, + .len_tgt_sys_disp_act_pk_lumi_flag = 1, + .len_num_rows_tgt_sys_disp_act_pk_lumi = 5, + .len_num_cols_tgt_sys_disp_act_pk_lumi = 5, + .len_tgt_sys_disp_act_pk_lumi = 4, + .len_maxscl = 17, + .len_average_maxrgb = 17, + .len_num_distribution_maxrgb_percentiles = 4, + .len_distribution_maxrgb_percentages = 7, + .len_distribution_maxrgb_percentiles = 17, + .len_fraction_bright_pixels = 10, + .len_mast_disp_act_pk_lumi_flag = 1, + .len_num_rows_mast_disp_act_pk_lumi = 5, + .len_num_cols_mast_disp_act_pk_lumi = 5, + .len_mast_disp_act_pk_lumi = 4, + .len_tone_mapping_flag = 1, + .len_knee_point_x = 12, + .len_knee_point_y = 12, + .len_num_bezier_curve_anchors = 4, + .len_bezier_curve_anchors = 10, + .len_color_saturation_mapping_flag = 1, + .len_color_saturation_weight = 6 +}; + +struct vframe_hdr_plus_sei_s hdr_plus_sei; +#define NAL_UNIT_SEI 39 +#define NAL_UNIT_SEI_SUFFIX 40 + +int GetBits(char buffer[], int totbitoffset, int *info, int bytecount, + int numbits) +{ + int inf; + int bitoffset = (totbitoffset & 0x07);/*bit from start of byte*/ + long byteoffset = (totbitoffset >> 3);/*byte from start of buffer*/ + int bitcounter = numbits; + static char *curbyte; + + if ((byteoffset) + ((numbits + bitoffset) >> 3) > bytecount) + return -1; + + curbyte = &(buffer[byteoffset]); + bitoffset = 7 - bitoffset; + inf = 0; + + while (numbits--) { + inf <<= 1; + inf |= ((*curbyte) >> (bitoffset--)) & 0x01; + + if (bitoffset < 0) { + curbyte++; + bitoffset = 7; + } + /*curbyte -= (bitoffset >> 3);*/ + /*bitoffset &= 0x07;*/ + /*curbyte += (bitoffset == 7);*/ + } + + *info = inf; + return bitcounter; +} + +void parser_hdr10_plus_medata(char *metadata, uint32_t size) +{ + int totbitoffset = 0; + int value = 0; + int i = 0; + int j = 0; + int num_win; + unsigned int num_col_tsdapl = 0, num_row_tsdapl = 0; + unsigned int tar_sys_disp_act_pk_lumi_flag = 0; + unsigned int num_d_m_p = 0; + unsigned int m_d_a_p_l_flag = 0; + unsigned int num_row_m_d_a_p_l = 0, num_col_m_d_a_p_l = 0; + unsigned int tone_mapping_flag = 0; + unsigned int num_bezier_curve_anchors = 0; + unsigned int color_saturation_mapping_flag = 0; + + GetBits(metadata, totbitoffset, + &value, size, sei_md_bits.len_itu_t_t35_country_code); + hdr_plus_sei.itu_t_t35_country_code = (u16)value; + totbitoffset += sei_md_bits.len_itu_t_t35_country_code; + + GetBits(metadata, totbitoffset, + &value, size, sei_md_bits.len_itu_t_t35_terminal_provider_code); + hdr_plus_sei.itu_t_t35_terminal_provider_code = (u16)value; + totbitoffset += sei_md_bits.len_itu_t_t35_terminal_provider_code; + + GetBits(metadata, totbitoffset, + &value, size, + sei_md_bits.len_itu_t_t35_terminal_provider_oriented_code); + hdr_plus_sei.itu_t_t35_terminal_provider_oriented_code = + (u16)value; + totbitoffset += + sei_md_bits.len_itu_t_t35_terminal_provider_oriented_code; + + GetBits(metadata, totbitoffset, + &value, size, + sei_md_bits.len_application_identifier); + hdr_plus_sei.application_identifier = (u16)value; + totbitoffset += sei_md_bits.len_application_identifier; + + GetBits(metadata, totbitoffset, + &value, size, + sei_md_bits.len_application_version); + hdr_plus_sei.application_version = (u16)value; + totbitoffset += sei_md_bits.len_application_version; + + GetBits(metadata, totbitoffset, + &value, size, + sei_md_bits.len_num_windows); + hdr_plus_sei.num_windows = (u16)value; + totbitoffset += sei_md_bits.len_num_windows; + + num_win = value; + + if (value > 1) { + for (i = 1; i < num_win; i++) { + GetBits(metadata, totbitoffset, + &value, size, + sei_md_bits.len_window_upper_left_corner_x); + hdr_plus_sei.window_upper_left_corner_x[i] = (u16)value; + totbitoffset += + sei_md_bits.len_window_upper_left_corner_x; + + GetBits(metadata, totbitoffset, + &value, size, + sei_md_bits.len_window_upper_left_corner_y); + hdr_plus_sei.window_upper_left_corner_y[i] = (u16)value; + totbitoffset += + sei_md_bits.len_window_upper_left_corner_y; + + GetBits(metadata, totbitoffset, + &value, size, + sei_md_bits.len_window_lower_right_corner_x); + hdr_plus_sei.window_lower_right_corner_x[i] + = (u16)value; + totbitoffset += + sei_md_bits.len_window_lower_right_corner_x; + + GetBits(metadata, totbitoffset, + &value, size, + sei_md_bits.len_window_lower_right_corner_y); + hdr_plus_sei.window_lower_right_corner_y[i] + = (u16)value; + totbitoffset += + sei_md_bits.len_window_lower_right_corner_y; + + GetBits(metadata, totbitoffset, + &value, size, + sei_md_bits.len_center_of_ellipse_x); + hdr_plus_sei.center_of_ellipse_x[i] = (u16)value; + totbitoffset += sei_md_bits.len_center_of_ellipse_x; + + GetBits(metadata, totbitoffset, + &value, size, + sei_md_bits.len_center_of_ellipse_y); + hdr_plus_sei.center_of_ellipse_y[i] = (u16)value; + totbitoffset += sei_md_bits.len_center_of_ellipse_y; + + GetBits(metadata, totbitoffset, + &value, size, + sei_md_bits.len_rotation_angle); + hdr_plus_sei.rotation_angle[i] = (u16)value; + totbitoffset += sei_md_bits.len_rotation_angle; + + GetBits(metadata, totbitoffset, + &value, size, + sei_md_bits.len_semimajor_axis_internal_ellipse); + hdr_plus_sei.semimajor_axis_internal_ellipse[i] + = (u16)value; + totbitoffset += + sei_md_bits.len_semimajor_axis_internal_ellipse; + + GetBits(metadata, totbitoffset, + &value, size, + sei_md_bits.len_semimajor_axis_external_ellipse); + hdr_plus_sei.semimajor_axis_external_ellipse[i] + = (u16)value; + totbitoffset += + sei_md_bits.len_semimajor_axis_external_ellipse; + + GetBits(metadata, totbitoffset, + &value, size, + sei_md_bits.len_semiminor_axis_external_ellipse); + hdr_plus_sei.semiminor_axis_external_ellipse[i] + = (u16)value; + totbitoffset += + sei_md_bits.len_semiminor_axis_external_ellipse; + + GetBits(metadata, totbitoffset, + &value, size, + sei_md_bits.len_overlap_process_option); + hdr_plus_sei.overlap_process_option[i] = (u16)value; + totbitoffset += sei_md_bits.len_overlap_process_option; + } + } + + GetBits(metadata, totbitoffset, + &value, size, + sei_md_bits.len_tgt_sys_disp_max_lumi); + hdr_plus_sei.tgt_sys_disp_max_lumi = value; + totbitoffset += + sei_md_bits.len_tgt_sys_disp_max_lumi; + + GetBits(metadata, totbitoffset, + &value, size, + sei_md_bits.len_tgt_sys_disp_act_pk_lumi_flag); + hdr_plus_sei.tgt_sys_disp_act_pk_lumi_flag + = (u16)value; + totbitoffset += + sei_md_bits.len_tgt_sys_disp_act_pk_lumi_flag; + + tar_sys_disp_act_pk_lumi_flag = value; + + if (tar_sys_disp_act_pk_lumi_flag) { + GetBits(metadata, totbitoffset, + &value, size, + sei_md_bits.len_num_rows_tgt_sys_disp_act_pk_lumi); + hdr_plus_sei.num_rows_tgt_sys_disp_act_pk_lumi + = (u16)value; + totbitoffset += + sei_md_bits.len_num_rows_tgt_sys_disp_act_pk_lumi; + + num_row_tsdapl = value; + + GetBits(metadata, totbitoffset, + &value, size, + sei_md_bits.len_num_cols_tgt_sys_disp_act_pk_lumi); + hdr_plus_sei.num_cols_tgt_sys_disp_act_pk_lumi + = (u16)value; + totbitoffset += + sei_md_bits.len_num_cols_tgt_sys_disp_act_pk_lumi; + + num_col_tsdapl = value; + + for (i = 0; i < num_row_tsdapl; i++) { + for (j = 0; j < num_col_tsdapl; j++) { + GetBits(metadata, totbitoffset, + &value, size, + sei_md_bits.len_tgt_sys_disp_act_pk_lumi); + hdr_plus_sei.tgt_sys_disp_act_pk_lumi[i][j] + = (u16)value; + totbitoffset += + sei_md_bits.len_tgt_sys_disp_act_pk_lumi; + } + } + } + for (i = 0; i < num_win; i++) { + for (j = 0; j < 3; j++) { + GetBits(metadata, totbitoffset, + &value, size, + sei_md_bits.len_maxscl); + hdr_plus_sei.maxscl[i][j] = value; + totbitoffset += sei_md_bits.len_maxscl; + } + GetBits(metadata, totbitoffset, + &value, size, + sei_md_bits.len_average_maxrgb); + hdr_plus_sei.average_maxrgb[i] = value; + totbitoffset += sei_md_bits.len_average_maxrgb; + + GetBits(metadata, totbitoffset, + &value, size, + sei_md_bits.len_num_distribution_maxrgb_percentiles); + hdr_plus_sei.num_distribution_maxrgb_percentiles[i] + = (u16)value; + totbitoffset += + sei_md_bits.len_num_distribution_maxrgb_percentiles; + + num_d_m_p = value; + for (j = 0; j < num_d_m_p; j++) { + GetBits(metadata, totbitoffset, + &value, size, + sei_md_bits.len_distribution_maxrgb_percentages); + hdr_plus_sei.distribution_maxrgb_percentages[i][j] + = (u16)value; + totbitoffset += + sei_md_bits.len_distribution_maxrgb_percentages; + + GetBits(metadata, totbitoffset, + &value, size, + sei_md_bits.len_distribution_maxrgb_percentiles); + hdr_plus_sei.distribution_maxrgb_percentiles[i][j] + = value; + totbitoffset += + sei_md_bits.len_distribution_maxrgb_percentiles; + } + + GetBits(metadata, totbitoffset, + &value, size, + sei_md_bits.len_fraction_bright_pixels); + hdr_plus_sei.fraction_bright_pixels[i] = (u16)value; + totbitoffset += sei_md_bits.len_fraction_bright_pixels; + } + + GetBits(metadata, totbitoffset, + &value, size, + sei_md_bits.len_mast_disp_act_pk_lumi_flag); + hdr_plus_sei.mast_disp_act_pk_lumi_flag + = (u16)value; + totbitoffset += + sei_md_bits.len_mast_disp_act_pk_lumi_flag; + + m_d_a_p_l_flag = value; + if (m_d_a_p_l_flag) { + GetBits(metadata, totbitoffset, + &value, size, + sei_md_bits.len_num_rows_mast_disp_act_pk_lumi); + hdr_plus_sei.num_rows_mast_disp_act_pk_lumi + = (u16)value; + totbitoffset += + sei_md_bits.len_num_rows_mast_disp_act_pk_lumi; + + num_row_m_d_a_p_l = value; + + GetBits(metadata, totbitoffset, + &value, size, + sei_md_bits.len_num_cols_mast_disp_act_pk_lumi); + hdr_plus_sei.num_cols_mast_disp_act_pk_lumi + = (u16)value; + totbitoffset += + sei_md_bits.len_num_cols_mast_disp_act_pk_lumi; + + num_col_m_d_a_p_l = value; + + for (i = 0; i < num_row_m_d_a_p_l; i++) { + for (j = 0; j < num_col_m_d_a_p_l; j++) { + GetBits(metadata, totbitoffset, + &value, size, + sei_md_bits.len_mast_disp_act_pk_lumi); + hdr_plus_sei.mast_disp_act_pk_lumi[i][j] + = (u16)value; + totbitoffset += + sei_md_bits.len_mast_disp_act_pk_lumi; + } + } + } + + for (i = 0; i < num_win; i++) { + GetBits(metadata, totbitoffset, + &value, size, + sei_md_bits.len_tone_mapping_flag); + hdr_plus_sei.tone_mapping_flag[i] = (u16)value; + totbitoffset += sei_md_bits.len_tone_mapping_flag; + + tone_mapping_flag = value; + + if (tone_mapping_flag) { + GetBits(metadata, totbitoffset, + &value, size, + sei_md_bits.len_knee_point_x); + hdr_plus_sei.knee_point_x[i] = (u16)value; + totbitoffset += sei_md_bits.len_knee_point_x; + + GetBits(metadata, totbitoffset, + &value, size, + sei_md_bits.len_knee_point_y); + hdr_plus_sei.knee_point_y[i] = (u16)value; + totbitoffset += sei_md_bits.len_knee_point_y; + + GetBits(metadata, totbitoffset, + &value, size, + sei_md_bits.len_num_bezier_curve_anchors); + hdr_plus_sei.num_bezier_curve_anchors[i] = + (u16)value; + totbitoffset += + sei_md_bits.len_num_bezier_curve_anchors; + + num_bezier_curve_anchors = value; + + for (j = 0; j < num_bezier_curve_anchors; j++) { + GetBits(metadata, totbitoffset, + &value, size, + sei_md_bits.len_bezier_curve_anchors); + hdr_plus_sei.bezier_curve_anchors[i][j] = + (u16)value; + totbitoffset += + sei_md_bits.len_bezier_curve_anchors; + } + } + + GetBits(metadata, totbitoffset, + &value, size, + sei_md_bits.len_color_saturation_mapping_flag); + hdr_plus_sei.color_saturation_mapping_flag[i] = + (u16)value; + totbitoffset += + sei_md_bits.len_color_saturation_mapping_flag; + + color_saturation_mapping_flag = value; + if (color_saturation_mapping_flag) { + GetBits(metadata, totbitoffset, + &value, size, + sei_md_bits.len_color_saturation_weight); + hdr_plus_sei.color_saturation_weight[i] = + (u16)value; + totbitoffset += + sei_md_bits.len_color_saturation_weight; + } + } +} + +static int parse_sei(char *sei_buf, uint32_t size) +{ + char *p = sei_buf; + char *p_sei; + uint16_t header; + uint8_t nal_unit_type; + uint8_t payload_type, payload_size; + + if (size < 2) + return 0; + header = *p++; + header <<= 8; + header += *p++; + nal_unit_type = header >> 9; + if ((nal_unit_type != NAL_UNIT_SEI) + && (nal_unit_type != NAL_UNIT_SEI_SUFFIX)) + return 0; + while (p+2 <= sei_buf+size) { + payload_type = *p++; + payload_size = *p++; + if (p + payload_size <= sei_buf + size) { + switch (payload_type) { + case SEI_Syntax: + p_sei = p; + parser_hdr10_plus_medata(p_sei, payload_size); + break; + default: + break; + } + } + p += payload_size; + } + return 0; +} + +void hdr10_plus_parser_metadata(struct vframe_s *vf) +{ + struct provider_aux_req_s req; + char *p; + unsigned int size = 0; + unsigned int type = 0; + + req.vf = vf; + req.bot_flag = 0; + req.aux_buf = NULL; + req.aux_size = 0; + req.dv_enhance_exist = 0; + req.low_latency = 0; + + vf_notify_provider_by_name("vdec.h265.00", + VFRAME_EVENT_RECEIVER_GET_AUX_DATA, + (void *)&req); + + if (req.aux_buf && req.aux_size) { + p = req.aux_buf; + while (p < req.aux_buf + + req.aux_size - 8) { + size = *p++; + size = (size << 8) | *p++; + size = (size << 8) | *p++; + size = (size << 8) | *p++; + type = *p++; + type = (type << 8) | *p++; + type = (type << 8) | *p++; + type = (type << 8) | *p++; + if (type == 0x02000000) + parse_sei(p, size); + + p += size; + } + + } +} + +struct hdr10plus_para dbg_hdr10plus_pkt; + +void hdr10_plus_hdmitx_vsif_parser( + struct hdr10plus_para *hdmitx_hdr10plus_param) +{ + int vsif_tds_max_l; + int ave_maxrgb; + int distribution_values[9]; + int i; + int kpx, kpy; + int bz_cur_anchors[9]; + + hdmitx_hdr10plus_param->application_version = + (u8)hdr_plus_sei.application_version; + + if (hdr_plus_sei.tgt_sys_disp_max_lumi < 1024) { + vsif_tds_max_l = + (hdr_plus_sei.tgt_sys_disp_max_lumi + (1 << 4)) >> 5; + if (vsif_tds_max_l > 31) + vsif_tds_max_l = 31; + } else + vsif_tds_max_l = 31; + hdmitx_hdr10plus_param->targeted_max_lum = (u8)vsif_tds_max_l; + + ave_maxrgb = hdr_plus_sei.average_maxrgb[0] / 10; + if (ave_maxrgb < (1 << 12)) { + ave_maxrgb = (ave_maxrgb + (1 << 3)) >> 4; + if (ave_maxrgb > 255) + ave_maxrgb = 255; + } else + ave_maxrgb = 255; + hdmitx_hdr10plus_param->average_maxrgb = (u8)ave_maxrgb; + + for (i = 0; i < 9; i++) { + if (i == 2) { + distribution_values[i] = + hdr_plus_sei.distribution_maxrgb_percentiles[0][i]; + hdmitx_hdr10plus_param->distribution_values[i] = + (u8)distribution_values[i]; + continue; + } + distribution_values[i] = + hdr_plus_sei.distribution_maxrgb_percentiles[0][i]; + if (distribution_values[i] < (1 << 12)) { + distribution_values[i] = + (distribution_values[i] + (1 << 3)) >> 4; + if (distribution_values[i] > 255) + distribution_values[i] = 255; + } else + distribution_values[i] = 255; + hdmitx_hdr10plus_param->distribution_values[i] = + (u8)distribution_values[i]; + } + + if (hdr_plus_sei.tone_mapping_flag[0] == 0) { + hdmitx_hdr10plus_param->num_bezier_curve_anchors = 0; + hdmitx_hdr10plus_param->knee_point_x = 0; + hdmitx_hdr10plus_param->knee_point_y = 0; + for (i = 0; i < 9; i++) + hdmitx_hdr10plus_param->bezier_curve_anchors[0] = 0; + } else { + hdmitx_hdr10plus_param->num_bezier_curve_anchors = + (u8)hdr_plus_sei.num_bezier_curve_anchors[0]; + + kpx = hdr_plus_sei.knee_point_x[0]; + kpx = (kpx + (1 << 1)) >> 2; + if (kpx > 1023) + kpx = 1023; + hdmitx_hdr10plus_param->knee_point_x = kpx; + + kpy = hdr_plus_sei.knee_point_y[0]; + kpy = (kpy + (1 << 1)) >> 2; + if (kpy > 1023) + kpy = 1023; + hdmitx_hdr10plus_param->knee_point_y = kpy; + + for (i = 0; i < 9; i++) { + bz_cur_anchors[i] = + hdr_plus_sei.bezier_curve_anchors[0][i]; + + bz_cur_anchors[i] = (bz_cur_anchors[i] + (1 << 1)) >> 2; + if (bz_cur_anchors[i] > 255) + bz_cur_anchors[i] = 255; + hdmitx_hdr10plus_param->bezier_curve_anchors[i] = + (u8)bz_cur_anchors[i]; + } + } + /*only video, don't include graphic*/ + hdmitx_hdr10plus_param->graphics_overlay_flag = 0; + /*metadata and video have no delay*/ + hdmitx_hdr10plus_param->no_delay_flag = 1; + + memcpy(&dbg_hdr10plus_pkt, hdmitx_hdr10plus_param, + sizeof(struct hdr10plus_para)); +} + +void hdr10_plus_process(struct vframe_s *vf) +{ + if (!vf) + return; +} + +void hdr10_plus_debug(void) +{ + int i = 0; + int j = 0; + + pr_hdr("itu_t_t35_country_code = 0x%x\n", + hdr_plus_sei.itu_t_t35_country_code); + pr_hdr("itu_t_t35_terminal_provider_code = 0x%x\n", + hdr_plus_sei.itu_t_t35_terminal_provider_code); + pr_hdr("itu_t_t35_terminal_provider_oriented_code = 0x%x\n", + hdr_plus_sei.itu_t_t35_terminal_provider_oriented_code); + pr_hdr("application_identifier = 0x%x\n", + hdr_plus_sei.application_identifier); + pr_hdr("application_version = 0x%x\n", + hdr_plus_sei.application_version); + pr_hdr("num_windows = 0x%x\n", + hdr_plus_sei.num_windows); + for (i = 1; i < hdr_plus_sei.num_windows; i++) { + pr_hdr("window_upper_left_corner_x[%d] = 0x%x\n", + i, hdr_plus_sei.window_upper_left_corner_x[i]); + pr_hdr("window_upper_left_corner_y[%d] = 0x%x\n", + i, hdr_plus_sei.window_upper_left_corner_y[i]); + pr_hdr("window_lower_right_corner_x[%d] = 0x%x\n", + i, hdr_plus_sei.window_lower_right_corner_x[i]); + pr_hdr("window_lower_right_corner_y[%d] = 0x%x\n", + i, hdr_plus_sei.window_lower_right_corner_y[i]); + pr_hdr("center_of_ellipse_x[%d] = 0x%x\n", + i, hdr_plus_sei.center_of_ellipse_x[i]); + pr_hdr("center_of_ellipse_y[%d] = 0x%x\n", + i, hdr_plus_sei.center_of_ellipse_y[i]); + pr_hdr("rotation_angle[%d] = 0x%x\n", + i, hdr_plus_sei.rotation_angle[i]); + pr_hdr("semimajor_axis_internal_ellipse[%d] = 0x%x\n", + i, hdr_plus_sei.semimajor_axis_internal_ellipse[i]); + pr_hdr("semimajor_axis_external_ellipse[%d] = 0x%x\n", + i, hdr_plus_sei.semimajor_axis_external_ellipse[i]); + pr_hdr("semiminor_axis_external_ellipse[%d] = 0x%x\n", + i, hdr_plus_sei.semiminor_axis_external_ellipse[i]); + pr_hdr("overlap_process_option[%d] = 0x%x\n", + i, hdr_plus_sei.overlap_process_option[i]); + } + pr_hdr("targeted_system_display_maximum_luminance = 0x%x\n", + hdr_plus_sei.tgt_sys_disp_max_lumi); + pr_hdr("targeted_system_display_actual_peak_luminance_flag = 0x%x\n", + hdr_plus_sei.tgt_sys_disp_act_pk_lumi_flag); + if (hdr_plus_sei.tgt_sys_disp_act_pk_lumi_flag) { + for (i = 0; + i < hdr_plus_sei.num_rows_tgt_sys_disp_act_pk_lumi; + i++) { + for (j = 0; + j < hdr_plus_sei.num_cols_tgt_sys_disp_act_pk_lumi; + j++) { + pr_hdr("tgt_sys_disp_act_pk_lumi"); + pr_hdr("[%d][%d] = 0x%x\n", + i, j, + hdr_plus_sei.tgt_sys_disp_act_pk_lumi[i][j]); + } + } + } + + for (i = 0; i < hdr_plus_sei.num_windows; i++) { + for (j = 0; j < 3; j++) + pr_hdr("maxscl[%d][%d] = 0x%x\n", + i, j, hdr_plus_sei.maxscl[i][j]); + + pr_hdr("average_maxrgb[%d] = 0x%x\n", + i, hdr_plus_sei.average_maxrgb[i]); + pr_hdr("num_distribution_maxrgb_percentiles[%d] = 0x%x\n", + i, hdr_plus_sei.num_distribution_maxrgb_percentiles[i]); + for (j = 0; + j < hdr_plus_sei.num_distribution_maxrgb_percentiles[i]; + j++) { + pr_hdr("distribution_maxrgb_pcntages[%d][%d] = 0x%x\n", + i, j, + hdr_plus_sei.distribution_maxrgb_percentages[i][j]); + pr_hdr("distribution_maxrgb_pcntiles[%d][%d] = 0x%x\n", + i, j, + hdr_plus_sei.distribution_maxrgb_percentiles[i][j]); + } + pr_hdr("fraction_bright_pixels[%d] = 0x%x\n", + i, hdr_plus_sei.fraction_bright_pixels[i]); + } + + pr_hdr("mast_disp_act_pk_lumi_flag = 0x%x\n", + hdr_plus_sei.mast_disp_act_pk_lumi_flag); + if (hdr_plus_sei.mast_disp_act_pk_lumi_flag) { + pr_hdr("num_rows_mast_disp_act_pk_lumi = 0x%x\n", + hdr_plus_sei.num_rows_mast_disp_act_pk_lumi); + pr_hdr("num_cols_mast_disp_act_pk_lumi = 0x%x\n", + hdr_plus_sei.num_cols_mast_disp_act_pk_lumi); + for (i = 0; + i < hdr_plus_sei.num_rows_mast_disp_act_pk_lumi; + i++) { + for (j = 0; + j < hdr_plus_sei.num_cols_mast_disp_act_pk_lumi; + j++) + pr_hdr("mast_disp_act_pk_lumi[%d][%d] = 0x%x\n", + i, j, hdr_plus_sei.mast_disp_act_pk_lumi[i][j]); + } + } + + for (i = 0; i < hdr_plus_sei.num_windows; i++) { + pr_hdr("tone_mapping_flag[%d] = 0x%x\n", + i, hdr_plus_sei.tone_mapping_flag[i]); + pr_hdr("knee_point_x[%d] = 0x%x\n", + i, hdr_plus_sei.knee_point_x[i]); + pr_hdr("knee_point_y[%d] = 0x%x\n", + i, hdr_plus_sei.knee_point_y[i]); + pr_hdr("num_bezier_curve_anchors[%d] = 0x%x\n", + i, hdr_plus_sei.num_bezier_curve_anchors[i]); + for (j = 0; j < hdr_plus_sei.num_bezier_curve_anchors[i]; j++) + pr_hdr("bezier_curve_anchors[%d][%d] = 0x%x\n", + i, j, hdr_plus_sei.bezier_curve_anchors[i][j]); + + pr_hdr("color_saturation_mapping_flag[%d] = 0x%x\n", + i, hdr_plus_sei.color_saturation_mapping_flag[i]); + pr_hdr("color_saturation_weight[%d] = 0x%x\n", + i, hdr_plus_sei.color_saturation_weight[i]); + } + + pr_hdr("\ntx vsif packet data print begin\n"); + pr_hdr("application_version = 0x%x\n", + dbg_hdr10plus_pkt.application_version); + pr_hdr("targeted_max_lum = 0x%x\n", + dbg_hdr10plus_pkt.targeted_max_lum); + pr_hdr("average_maxrgb = 0x%x\n", + dbg_hdr10plus_pkt.average_maxrgb); + for (i = 0; i < 9; i++) + pr_hdr("distribution_values[%d] = 0x%x\n", + i, dbg_hdr10plus_pkt.distribution_values[i]); + pr_hdr("num_bezier_curve_anchors = 0x%x\n", + dbg_hdr10plus_pkt.num_bezier_curve_anchors); + pr_hdr("knee_point_x = 0x%x\n", + dbg_hdr10plus_pkt.knee_point_x); + pr_hdr("knee_point_y = 0x%x\n", + dbg_hdr10plus_pkt.knee_point_y); + + for (i = 0; i < 9; i++) + pr_hdr("bezier_curve_anchors[%d] = 0x%x\n", + i, dbg_hdr10plus_pkt.bezier_curve_anchors[i]); + pr_hdr("graphics_overlay_flag = 0x%x\n", + dbg_hdr10plus_pkt.graphics_overlay_flag); + pr_hdr("no_delay_flag = 0x%x\n", + dbg_hdr10plus_pkt.no_delay_flag); + pr_hdr("\ntx vsif packet data print end\n"); + + pr_hdr(HDR10_PLUS_VERSION); +} + diff --git a/drivers/amlogic/media/enhancement/amvecm/hdr/am_hdr10_plus.h b/drivers/amlogic/media/enhancement/amvecm/hdr/am_hdr10_plus.h new file mode 100644 index 000000000000..79c73568e8af --- /dev/null +++ b/drivers/amlogic/media/enhancement/amvecm/hdr/am_hdr10_plus.h @@ -0,0 +1,78 @@ +/* + * drivers/amlogic/media/enhancement/amvecm/hdr/am_hdr.h + * + * Copyright (C) 2017 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +#ifndef AM_HDR_H +#define AM_HDR_H +struct hdr_plus_bits_s { + u16 len_itu_t_t35_country_code; + u16 len_itu_t_t35_terminal_provider_code; + u16 len_itu_t_t35_terminal_provider_oriented_code; + u16 len_application_identifier; + u16 len_application_version; + /*num_windows max is 3*/ + u16 len_num_windows; + /*windows xy*/ + u16 len_window_upper_left_corner_x; + u16 len_window_upper_left_corner_y; + u16 len_window_lower_right_corner_x; + u16 len_window_lower_right_corner_y; + u16 len_center_of_ellipse_x; + u16 len_center_of_ellipse_y; + u16 len_rotation_angle; + u16 len_semimajor_axis_internal_ellipse; + u16 len_semimajor_axis_external_ellipse; + u16 len_semiminor_axis_external_ellipse; + u16 len_overlap_process_option; + /*target luminance*/ + u16 len_tgt_sys_disp_max_lumi; + u16 len_tgt_sys_disp_act_pk_lumi_flag; + u16 len_num_rows_tgt_sys_disp_act_pk_lumi; + u16 len_num_cols_tgt_sys_disp_act_pk_lumi; + u16 len_tgt_sys_disp_act_pk_lumi; + + /*num_windows max is 3, e.g maxscl[num_windows][i];*/ + u16 len_maxscl; + u16 len_average_maxrgb; + u16 len_num_distribution_maxrgb_percentiles; + u16 len_distribution_maxrgb_percentages; + u16 len_distribution_maxrgb_percentiles; + u16 len_fraction_bright_pixels; + + u16 len_mast_disp_act_pk_lumi_flag; + u16 len_num_rows_mast_disp_act_pk_lumi; + u16 len_num_cols_mast_disp_act_pk_lumi; + u16 len_mast_disp_act_pk_lumi; + /*num_windows max is 3, e.g knee_point_x[num_windows]*/ + u16 len_tone_mapping_flag; + u16 len_knee_point_x; + u16 len_knee_point_y; + u16 len_num_bezier_curve_anchors; + u16 len_bezier_curve_anchors; + u16 len_color_saturation_mapping_flag; + u16 len_color_saturation_weight; +}; + +extern uint debug_hdr; +#define HDR_PLUS_IEEE_OUI 0x90848B +#define SEI_Syntax 0x4 +extern void hdr10_plus_hdmitx_vsif_parser( + struct hdr10plus_para *hdmitx_hdr10plus_param); +extern void hdr10_plus_parser_metadata(struct vframe_s *vf); +extern void hdr10_plus_process(struct vframe_s *vf); +extern void hdr10_plus_debug(void); +#endif /* AM_HDR_H */ + diff --git a/drivers/amlogic/media/enhancement/amvecm/local_contrast.c b/drivers/amlogic/media/enhancement/amvecm/local_contrast.c new file mode 100644 index 000000000000..5f110182a041 --- /dev/null +++ b/drivers/amlogic/media/enhancement/amvecm/local_contrast.c @@ -0,0 +1,514 @@ + +/* #include */ +#include +#include +#include +#include +#include +#include +#include +#include "arch/vpp_regs.h" +#include "local_contrast.h" + +int amlc_debug; +#define pr_amlc_dbg(fmt, args...)\ + do {\ + if (amlc_debug&0x1)\ + pr_info("AMVE: " fmt, ## args);\ + } while (0) + +int lc_en; +static int lc_flag = 0xff; + +/*local contrast begin*/ +static void lc_mtx_set(enum lc_mtx_sel_e mtx_sel, + enum lc_mtx_csc_e mtx_csc, + int mtx_en) +{ + unsigned int matrix_coef00_01 = 0; + unsigned int matrix_coef02_10 = 0; + unsigned int matrix_coef11_12 = 0; + unsigned int matrix_coef20_21 = 0; + unsigned int matrix_coef22 = 0; + unsigned int matrix_clip = 0; + unsigned int matrix_offset0_1 = 0; + unsigned int matrix_offset2 = 0; + unsigned int matrix_pre_offset0_1 = 0; + unsigned int matrix_pre_offset2 = 0; + unsigned int matrix_en_ctrl = 0; + + switch (mtx_sel) { + case INP_MTX: + matrix_coef00_01 = SRSHARP1_LC_YUV2RGB_MAT_0_1; + matrix_coef02_10 = SRSHARP1_LC_YUV2RGB_MAT_2_3; + matrix_coef11_12 = SRSHARP1_LC_YUV2RGB_MAT_4_5; + matrix_coef20_21 = SRSHARP1_LC_YUV2RGB_MAT_6_7; + matrix_coef22 = SRSHARP1_LC_YUV2RGB_MAT_8; + matrix_pre_offset0_1 = SRSHARP1_LC_YUV2RGB_OFST; + matrix_clip = SRSHARP1_LC_YUV2RGB_CLIP; + break; + case OUTP_MTX: + matrix_coef00_01 = SRSHARP1_LC_RGB2YUV_MAT_0_1; + matrix_coef02_10 = SRSHARP1_LC_RGB2YUV_MAT_2_3; + matrix_coef11_12 = SRSHARP1_LC_RGB2YUV_MAT_4_5; + matrix_coef20_21 = SRSHARP1_LC_RGB2YUV_MAT_6_7; + matrix_coef22 = SRSHARP1_LC_RGB2YUV_MAT_8; + matrix_offset0_1 = SRSHARP1_LC_RGB2YUV_OFST; + matrix_clip = SRSHARP1_LC_RGB2YUV_CLIP; + break; + case STAT_MTX: + matrix_coef00_01 = LC_STTS_MATRIX_COEF00_01; + matrix_coef02_10 = LC_STTS_MATRIX_COEF02_10; + matrix_coef11_12 = LC_STTS_MATRIX_COEF11_12; + matrix_coef20_21 = LC_STTS_MATRIX_COEF20_21; + matrix_coef22 = LC_STTS_MATRIX_COEF22; + matrix_offset0_1 = LC_STTS_MATRIX_OFFSET0_1; + matrix_offset2 = LC_STTS_MATRIX_OFFSET2; + matrix_pre_offset0_1 = LC_STTS_MATRIX_PRE_OFFSET0_1; + matrix_pre_offset2 = LC_STTS_MATRIX_PRE_OFFSET2; + matrix_en_ctrl = LC_STTS_CTRL0; + break; + default: + break; + } + + if (mtx_sel & STAT_MTX) + WRITE_VPP_REG_BITS(matrix_en_ctrl, mtx_en, 2, 1); + + if (!mtx_en) + return; + + switch (mtx_csc) { + case LC_MTX_RGB_YUV709L: + if (mtx_sel & (INP_MTX | OUTP_MTX)) { + WRITE_VPP_REG(matrix_coef00_01, 0x00bb0275); + WRITE_VPP_REG(matrix_coef02_10, 0x003f1f99); + WRITE_VPP_REG(matrix_coef11_12, 0x1ea601c2); + WRITE_VPP_REG(matrix_coef20_21, 0x01c21e67); + WRITE_VPP_REG(matrix_coef22, 0x00001fd7); + WRITE_VPP_REG(matrix_offset0_1, 0x00400200); + } else if (mtx_sel & STAT_MTX) { + WRITE_VPP_REG(matrix_coef00_01, 0x00bb0275); + WRITE_VPP_REG(matrix_coef02_10, 0x003f1f99); + WRITE_VPP_REG(matrix_coef11_12, 0x1ea601c2); + WRITE_VPP_REG(matrix_coef20_21, 0x01c21e67); + WRITE_VPP_REG(matrix_coef22, 0x00001fd7); + WRITE_VPP_REG(matrix_offset0_1, 0x00400200); + WRITE_VPP_REG(matrix_offset2, 0x00000200); + WRITE_VPP_REG(matrix_pre_offset0_1, 0x0); + WRITE_VPP_REG(matrix_pre_offset2, 0x0); + } + break; + case LC_MTX_YUV709L_RGB: + if (mtx_sel & (INP_MTX | OUTP_MTX)) { + WRITE_VPP_REG(matrix_coef00_01, 0x04A80000); + WRITE_VPP_REG(matrix_coef02_10, 0x072C04A8); + WRITE_VPP_REG(matrix_coef11_12, 0x1F261DDD); + WRITE_VPP_REG(matrix_coef20_21, 0x04A80876); + WRITE_VPP_REG(matrix_coef22, 0x0); + WRITE_VPP_REG(matrix_pre_offset0_1, 0x00400200); + } else if (mtx_sel & STAT_MTX) { + WRITE_VPP_REG(matrix_coef00_01, 0x04A80000); + WRITE_VPP_REG(matrix_coef02_10, 0x072C04A8); + WRITE_VPP_REG(matrix_coef11_12, 0x1F261DDD); + WRITE_VPP_REG(matrix_coef20_21, 0x04A80876); + WRITE_VPP_REG(matrix_coef22, 0x0); + WRITE_VPP_REG(matrix_offset0_1, 0x0); + WRITE_VPP_REG(matrix_offset2, 0x0); + WRITE_VPP_REG(matrix_pre_offset0_1, 0x7c00600); + WRITE_VPP_REG(matrix_pre_offset2, 0x00000600); + } + break; + case LC_MTX_NULL: + if (mtx_sel & (INP_MTX | OUTP_MTX)) { + WRITE_VPP_REG(matrix_coef00_01, 0x04000000); + WRITE_VPP_REG(matrix_coef02_10, 0x0); + WRITE_VPP_REG(matrix_coef11_12, 0x04000000); + WRITE_VPP_REG(matrix_coef20_21, 0x0); + WRITE_VPP_REG(matrix_coef22, 0x400); + WRITE_VPP_REG(matrix_offset0_1, 0x0); + } else if (mtx_sel & STAT_MTX) { + + } + break; + default: + break; + } +} + +static void lc_stts_blk_config(int enable, + unsigned int height, unsigned int width) +{ + int h_num, v_num; + int blk_height, blk_width; + int row_start, col_start; + int data32; + int hend0, hend1, hend2, hend3, hend4, hend5, hend6; + int hend7, hend8, hend9, hend10, hend11; + int vend0, vend1, vend2, vend3, vend4, vend5, vend6, vend7; + + row_start = 0; + col_start = 0; + h_num = 12; + v_num = 8; + blk_height = height / h_num; + blk_width = width / v_num; + + hend0 = col_start + blk_width - 1; + hend1 = hend0 + blk_width; + hend2 = hend1 + blk_width; + hend3 = hend2 + blk_width; + hend4 = hend3 + blk_width; + hend5 = hend4 + blk_width; + hend6 = hend5 + blk_width; + hend7 = hend6 + blk_width; + hend8 = hend7 + blk_width; + hend9 = hend8 + blk_width; + hend10 = hend9 + blk_width; + hend11 = width - 1; + + vend0 = row_start + blk_height - 1; + vend1 = vend0 + blk_height; + vend2 = vend1 + blk_height; + vend3 = vend2 + blk_height; + vend4 = vend3 + blk_height; + vend5 = vend4 + blk_height; + vend6 = vend5 + blk_height; + vend7 = height - 1; + + data32 = READ_VPP_REG(LC_STTS_HIST_REGION_IDX); + WRITE_VPP_REG(LC_STTS_HIST_REGION_IDX, 0xffe0ffff & data32); + WRITE_VPP_REG(LC_STTS_HIST_SET_REGION, + ((((row_start & 0x1fff) << 16) & 0xffff0000) | + (col_start & 0x1fff))); + WRITE_VPP_REG(LC_STTS_HIST_SET_REGION, + (hend1 & 0x1fff) | (hend0 & 0x1fff)); + WRITE_VPP_REG(LC_STTS_HIST_SET_REGION, + (vend1 & 0x1fff) | (vend0 & 0x1fff)); + WRITE_VPP_REG(LC_STTS_HIST_SET_REGION, + (hend3 & 0x1fff) | (hend2 & 0x1fff)); + WRITE_VPP_REG(LC_STTS_HIST_SET_REGION, + (vend3 & 0x1fff) | (vend2 & 0x1fff)); + WRITE_VPP_REG(LC_STTS_HIST_SET_REGION, + (hend5 & 0x1fff) | (hend4 & 0x1fff)); + WRITE_VPP_REG(LC_STTS_HIST_SET_REGION, + (vend5 & 0x1fff) | (vend4 & 0x1fff)); + + WRITE_VPP_REG(LC_STTS_HIST_SET_REGION, + (hend7 & 0x1fff) | (hend6 & 0x1fff)); + WRITE_VPP_REG(LC_STTS_HIST_SET_REGION, + (vend7 & 0x1fff) | (vend6 & 0x1fff)); + WRITE_VPP_REG(LC_STTS_HIST_SET_REGION, + (hend9 & 0x1fff) | (hend8 & 0x1fff)); + WRITE_VPP_REG(LC_STTS_HIST_SET_REGION, + (hend11 & 0x1fff) | (hend10 & 0x1fff)); + WRITE_VPP_REG(LC_STTS_HIST_SET_REGION, h_num); +} + +static void lc_stts_en(int enable, + unsigned int height, + unsigned int width, + int pix_drop_mode, + int eol_en, + int hist_mode, + int lpf_en, + int din_sel) +{ + int data32; + + WRITE_VPP_REG(LC_STTS_GCLK_CTRL0, 0x0); + WRITE_VPP_REG(LC_STTS_WIDTHM1_HEIGHTM1, + ((width - 1) << 16) | (height - 1)); + data32 = 0x80000000 | ((pix_drop_mode & 0x3) << 29); + data32 = data32 | ((eol_en & 0x1) << 28); + data32 = data32 | ((hist_mode & 0x3) << 22); + data32 = data32 | ((lpf_en & 0x1) << 21); + WRITE_VPP_REG(LC_STTS_HIST_REGION_IDX, data32); + + lc_mtx_set(STAT_MTX, LC_MTX_YUV709L_RGB, enable); + + WRITE_VPP_REG_BITS(LC_STTS_CTRL0, din_sel, 3, 3); + /*lc hist stts enable*/ + WRITE_VPP_REG_BITS(LC_STTS_HIST_REGION_IDX, enable, 31, 1); +} + +static void lc_curve_ctrl_config(int enable, + unsigned int height, unsigned int width) +{ + unsigned int lc_histvld_thrd; + unsigned int lc_blackbar_mute_thrd; + unsigned int lmtrat_minmax; + int h_num, v_num; + + h_num = 12; + v_num = 8; + + lmtrat_minmax = (READ_VPP_REG(LC_CURVE_LMT_RAT) >> 8) & 0xff; + lc_histvld_thrd = ((height * width) / + (h_num * v_num) * lmtrat_minmax) >> 10; + lc_blackbar_mute_thrd = ((height * width) / (h_num * v_num)) >> 3; + + if (!enable) + WRITE_VPP_REG_BITS(LC_CURVE_CTRL, enable, 0, 1); + else { + WRITE_VPP_REG(LC_CURVE_HV_NUM, (h_num << 8) | v_num); + WRITE_VPP_REG(LC_CURVE_HISTVLD_THRD, lc_histvld_thrd); + WRITE_VPP_REG(LC_CURVE_BB_MUTE_THRD, lc_blackbar_mute_thrd); + + WRITE_VPP_REG_BITS(LC_CURVE_CTRL, enable, 0, 1); + WRITE_VPP_REG_BITS(LC_CURVE_CTRL, enable, 31, 1); + } +} + +static void lc_blk_bdry_config(unsigned int height, unsigned int width) +{ + width /= 12; + height /= 8; + + /*lc curve mapping block IDX default 4k panel*/ + WRITE_VPP_REG_BITS(SRSHARP1_LC_CURVE_BLK_HIDX_0_1, + 0, 16, 14); + WRITE_VPP_REG_BITS(SRSHARP1_LC_CURVE_BLK_HIDX_0_1, + width, 0, 14); + WRITE_VPP_REG_BITS(SRSHARP1_LC_CURVE_BLK_HIDX_2_3, + width * 2, 16, 14); + WRITE_VPP_REG_BITS(SRSHARP1_LC_CURVE_BLK_HIDX_2_3, + width * 3, 0, 14); + WRITE_VPP_REG_BITS(SRSHARP1_LC_CURVE_BLK_HIDX_4_5, + width * 4, 16, 14); + WRITE_VPP_REG_BITS(SRSHARP1_LC_CURVE_BLK_HIDX_4_5, + width * 5, 0, 14); + WRITE_VPP_REG_BITS(SRSHARP1_LC_CURVE_BLK_HIDX_6_7, + width * 6, 16, 14); + WRITE_VPP_REG_BITS(SRSHARP1_LC_CURVE_BLK_HIDX_6_7, + width * 7, 0, 14); + WRITE_VPP_REG_BITS(SRSHARP1_LC_CURVE_BLK_HIDX_8_9, + width * 8, 16, 14); + WRITE_VPP_REG_BITS(SRSHARP1_LC_CURVE_BLK_HIDX_8_9, + width * 9, 0, 14); + WRITE_VPP_REG_BITS(SRSHARP1_LC_CURVE_BLK_HIDX_10_11, + width * 10, 16, 14); + WRITE_VPP_REG_BITS(SRSHARP1_LC_CURVE_BLK_HIDX_10_11, + width * 11, 0, 14); + WRITE_VPP_REG_BITS(SRSHARP1_LC_CURVE_BLK_HIDX_12, + width, 0, 14); + + WRITE_VPP_REG_BITS(SRSHARP1_LC_CURVE_BLK_VIDX_0_1, + 0, 16, 14); + WRITE_VPP_REG_BITS(SRSHARP1_LC_CURVE_BLK_VIDX_0_1, + height, 0, 14); + WRITE_VPP_REG_BITS(SRSHARP1_LC_CURVE_BLK_VIDX_2_3, + height * 2, 16, 14); + WRITE_VPP_REG_BITS(SRSHARP1_LC_CURVE_BLK_VIDX_2_3, + height * 3, 0, 14); + WRITE_VPP_REG_BITS(SRSHARP1_LC_CURVE_BLK_VIDX_4_5, + height * 4, 16, 14); + WRITE_VPP_REG_BITS(SRSHARP1_LC_CURVE_BLK_VIDX_4_5, + height * 5, 0, 14); + WRITE_VPP_REG_BITS(SRSHARP1_LC_CURVE_BLK_VIDX_6_7, + height * 6, 16, 14); + WRITE_VPP_REG_BITS(SRSHARP1_LC_CURVE_BLK_VIDX_6_7, + height * 7, 0, 14); + WRITE_VPP_REG_BITS(SRSHARP1_LC_CURVE_BLK_VIDX_8, + height, 0, 14); +} + +static void lc_top_config(int enable, int h_num, int v_num, + unsigned int height, unsigned int width) +{ + /*lcinput_ysel*/ + WRITE_VPP_REG_BITS(SRSHARP1_LC_INPUT_MUX, 5, 4, 3); + /*lcinput_csel*/ + WRITE_VPP_REG_BITS(SRSHARP1_LC_INPUT_MUX, 5, 0, 3); + + /*lc ram write h num*/ + WRITE_VPP_REG_BITS(SRSHARP1_LC_HV_NUM, h_num, 8, 5); + /*lc ram write v num*/ + WRITE_VPP_REG_BITS(SRSHARP1_LC_HV_NUM, v_num, 0, 5); + + /*lc hblank*/ + WRITE_VPP_REG_BITS(SRSHARP1_LC_TOP_CTRL, 8, 8, 8); + /*lc blend mode*/ + WRITE_VPP_REG_BITS(SRSHARP1_LC_TOP_CTRL, 0, 0, 1); + /*lc curve mapping config*/ + lc_blk_bdry_config(height, width); + /*LC sync ctl*/ + WRITE_VPP_REG_BITS(SRSHARP1_LC_TOP_CTRL, 0, 16, 1); + /*lc enable need set at last*/ + WRITE_VPP_REG_BITS(SRSHARP1_LC_TOP_CTRL, enable, 4, 1); +} + +static void lc_disable(void) +{ + /*lc enable need set at last*/ + WRITE_VPP_REG_BITS(SRSHARP1_LC_TOP_CTRL, 0, 4, 1); + WRITE_VPP_REG_BITS(LC_CURVE_CTRL, 0, 0, 1); + /*lc hist stts enable*/ + WRITE_VPP_REG_BITS(LC_STTS_HIST_REGION_IDX, 0, 31, 1); +} + +static void lc_config(int enable, + struct vframe_s *vf, + unsigned int sps_h_en, + unsigned int sps_v_en) +{ + int h_num, v_num; + unsigned int height, width; + static unsigned int vf_height, vf_width; + const struct vinfo_s *vinfo = get_current_vinfo(); + + height = vinfo->height; + width = vinfo->width; + h_num = 12; + v_num = 8; + + if (vf == NULL) + return; + + if ((vf_height == vf->height) || + (vf_width == vf->width)) + return; + + vf_height = vf->height; + vf_width = vf->width; + + lc_top_config(enable, h_num, v_num, height, width); + + if (sps_h_en == 1) + width /= 2; + if (sps_v_en == 1) + height /= 2; + + lc_curve_ctrl_config(enable, height, width); + lc_stts_blk_config(enable, height, width); + lc_stts_en(enable, height, width, 0, 0, 1, 1, 4); +} + +static void read_lc_curve(int *szCurveInfo) +{ + int blk_hnum; + int blk_vnum; + int i; + unsigned int dwTemp; + + dwTemp = READ_VPP_REG(LC_CURVE_HV_NUM); + blk_hnum = (dwTemp >> 8) & 0x1f; + blk_vnum = (dwTemp) & 0x1f; + WRITE_VPP_REG(LC_CURVE_RAM_CTRL, 1); + WRITE_VPP_REG(LC_CURVE_RAM_ADDR, 0); + for (i = 0; i < blk_hnum * blk_vnum; i++) { + szCurveInfo[i*2+0] = READ_VPP_REG(LC_CURVE_RAM_DATA); + szCurveInfo[i*2+1] = READ_VPP_REG(LC_CURVE_RAM_DATA); + } +} + +static int set_lc_curve(int *szCurveInfo, int binit, int bcheck) +{ + int i, h_num, v_num; + unsigned int hvTemp; + int rflag; + int temp; + + rflag = 0; + hvTemp = READ_VPP_REG(SRSHARP1_LC_HV_NUM); + h_num = (hvTemp >> 8) & 0x1f; + v_num = hvTemp & 0x1f; + WRITE_VPP_REG_BITS(SRSHARP1_LC_MAP_RAM_CTRL, 1, 0, 1); + /*data sequence: ymin/minBv/pkBv/maxBv/ymaxv/ypkBv*/ + if (binit) { + WRITE_VPP_REG(SRSHARP1_LC_MAP_RAM_ADDR, 0); + for (i = 0; i < h_num * v_num; i++) { + WRITE_VPP_REG(SRSHARP1_LC_MAP_RAM_DATA, + (0|(0<<10)|(512<<20))); + WRITE_VPP_REG(SRSHARP1_LC_MAP_RAM_DATA, + (1023|(1023<<10)|(512<<20))); + } + } else { + WRITE_VPP_REG(SRSHARP1_LC_MAP_RAM_ADDR, 0); + for (i = 0; i < h_num * v_num; i++) { + WRITE_VPP_REG(SRSHARP1_LC_MAP_RAM_DATA, + szCurveInfo[2 * i + 0]); + WRITE_VPP_REG(SRSHARP1_LC_MAP_RAM_DATA, + szCurveInfo[2 * i + 1]); + } + } + WRITE_VPP_REG_BITS(SRSHARP1_LC_MAP_RAM_CTRL, 0, 0, 1); + + if (bcheck) { + WRITE_VPP_REG_BITS(SRSHARP1_LC_MAP_RAM_CTRL, 1, 0, 1); + WRITE_VPP_REG(SRSHARP1_LC_MAP_RAM_ADDR, 0 | (1 << 31)); + for (i = 0; i < h_num * v_num; i++) { + temp = READ_VPP_REG(SRSHARP1_LC_MAP_RAM_DATA); + if (temp != szCurveInfo[2 * i + 0]) + rflag = (2 * i + 0) | (1 << 31); + temp = READ_VPP_REG(SRSHARP1_LC_MAP_RAM_DATA); + if (temp != szCurveInfo[2 * i + 1]) + rflag = (2 * i + 1) | (1 << 31); + } + WRITE_VPP_REG_BITS(SRSHARP1_LC_MAP_RAM_CTRL, 0, 0, 1); + } + + return rflag; +} + +static void lc_fw_curve_iir(struct vframe_s *vf) +{ + if (!vf) + return; +} + +void lc_init(void) +{ + int h_num, v_num; + unsigned int height, width; + const struct vinfo_s *vinfo = get_current_vinfo(); + + height = vinfo->height; + width = vinfo->width; + h_num = 12; + v_num = 8; + + if (!lc_en) + return; + + lc_top_config(0, h_num, v_num, height, width); + lc_mtx_set(INP_MTX, LC_MTX_YUV709L_RGB, 1); + lc_mtx_set(OUTP_MTX, LC_MTX_RGB_YUV709L, 1); + + if (set_lc_curve(NULL, 1, 0)) + pr_amlc_dbg("%s: init fail", __func__); +} + +void lc_process(struct vframe_s *vf, + unsigned int sps_h_en, + unsigned int sps_v_en) +{ + int *szCurveInfo; + + if (get_cpu_type() < MESON_CPU_MAJOR_ID_TL1) + return; + + if (!lc_en) { + lc_disable(); + return; + } + + if ((vf == NULL) && (lc_flag == 0xff)) { + lc_disable(); + lc_flag = 0x0; + return; + } + + szCurveInfo = kmalloc(12 * 8 * 2 * sizeof(int), GFP_KERNEL); + + lc_config(lc_en, vf, sps_h_en, sps_v_en); + + read_lc_curve(szCurveInfo); + lc_fw_curve_iir(vf); + if (set_lc_curve(szCurveInfo, 0, 1)) + pr_amlc_dbg("%s: set lc curve fail", __func__); + + lc_flag = 0xff; + kfree(szCurveInfo); +} + diff --git a/drivers/amlogic/media/enhancement/amvecm/local_contrast.h b/drivers/amlogic/media/enhancement/amvecm/local_contrast.h new file mode 100644 index 000000000000..ad742c8a583d --- /dev/null +++ b/drivers/amlogic/media/enhancement/amvecm/local_contrast.h @@ -0,0 +1,45 @@ +/* + * drivers/amlogic/media/enhancement/amvecm/amcm.h + * + * Copyright (C) 2017 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +#ifndef __AM_LC_H +#define __AM_LC_H + + +#include + +enum lc_mtx_sel_e { + INP_MTX = 0x1, + OUTP_MTX = 0x2, + STAT_MTX = 0x4, + MAX_MTX +}; + +enum lc_mtx_csc_e { + LC_MTX_NULL = 0, + LC_MTX_YUV709L_RGB = 0x1, + LC_MTX_RGB_YUV709L = 0x2, + LC_MTX_MAX +}; + +extern int amlc_debug; +extern int lc_en; +extern void lc_init(void); +extern void lc_process(struct vframe_s *vf, + unsigned int sps_h_en, + unsigned int sps_v_en); +#endif + diff --git a/drivers/amlogic/media/enhancement/amvecm/set_hdr2_v0.c b/drivers/amlogic/media/enhancement/amvecm/set_hdr2_v0.c index 3c21df4c3204..0ede3980fdab 100644 --- a/drivers/amlogic/media/enhancement/amvecm/set_hdr2_v0.c +++ b/drivers/amlogic/media/enhancement/amvecm/set_hdr2_v0.c @@ -1153,8 +1153,7 @@ void set_hdr_matrix( } else adpscl_shift[i] = adp_scal_shift; - if (hdr_mtx_param->mtx_ogain) - adpscl_ys_coef[i] = + adpscl_ys_coef[i] = 1 << adp_scal_shift; adpscl_beta_s[i] = 0; adpscl_beta[i] = 0; @@ -1476,6 +1475,9 @@ void hdr_func(enum hdr_module_sel module_sel, else return; + if (is_meson_tl1_cpu()) + bit_depth = 10; + #ifdef HDR2_MODULE MenuFun fun[] = {pq_eotf, pq_oetf, gm_eotf, gm_oetf, sld_eotf, sld_oetf, hlg_eotf, hlg_oetf, ootf_gain, diff --git a/drivers/amlogic/media/enhancement/amvecm/vlock.c b/drivers/amlogic/media/enhancement/amvecm/vlock.c index 09b9ad7beb1d..8ce8c0c088b7 100644 --- a/drivers/amlogic/media/enhancement/amvecm/vlock.c +++ b/drivers/amlogic/media/enhancement/amvecm/vlock.c @@ -52,10 +52,10 @@ static unsigned int vlock_delta_limit = 2; static unsigned int vlock_pll_m_limit = 1; /*for 24MHZ clock, 50hz input, delta value (10) of(0x3011-0x3012) == 0.001HZ */ static unsigned int vlock_delta_cnt_limit = 10; -static unsigned int vlock_pll_stable_flag; +/*hdmi support enable default,cvbs support not good,need debug with vlsi*/ +static unsigned int vlock_support = (VLOCK_SUPPORT_HDMI | VLOCK_SUPPORT_CVBS); static unsigned int vlock_enc_stable_flag; static unsigned int vlock_pll_stable_cnt; -static unsigned int vlock_pll_stable_limit = 600;/*10s for 60hz input*/ static unsigned int vlock_pll_adj_limit; static unsigned int vlock_pll_val_last; static unsigned int vlock_intput_type; @@ -171,10 +171,12 @@ static unsigned int vlock_check_input_hz(struct vframe_s *vf) if ((vf->source_type != VFRAME_SOURCE_TYPE_CVBS) && (vf->source_type != VFRAME_SOURCE_TYPE_HDMI)) ret_hz = 0; - else if (vf->source_type == VFRAME_SOURCE_TYPE_HDMI) { + else if ((vf->source_type == VFRAME_SOURCE_TYPE_HDMI) && + (vlock_support & VLOCK_SUPPORT_HDMI)) { if (duration != 0) ret_hz = (96000 + duration/2)/duration; - } else if (vf->source_type == VFRAME_SOURCE_TYPE_CVBS) { + } else if ((vf->source_type == VFRAME_SOURCE_TYPE_CVBS) && + (vlock_support & VLOCK_SUPPORT_CVBS)) { if (vf->source_mode == VFRAME_SOURCE_MODE_NTSC) ret_hz = 60; else if ((vf->source_mode == VFRAME_SOURCE_MODE_PAL) || @@ -417,7 +419,8 @@ void vlock_vmode_check(void) hiu_reg_addr = HHI_HDMI_PLL_CNTL2; vinfo = get_current_vinfo(); vlock_vmode_changed = 0; - if (vlock_vmode_change_status == VOUT_EVENT_MODE_CHANGE) { + if ((vlock_vmode_change_status == VOUT_EVENT_MODE_CHANGE) || + (pre_hiu_reg_m == 0)) { if (vlock_mode & (VLOCK_MODE_MANUAL_PLL | VLOCK_MODE_AUTO_PLL)) { amvecm_hiu_reg_read(hiu_reg_addr, &t0); @@ -533,7 +536,6 @@ static void vlock_disable_step1(void) vlock_mode |= VLOCK_MODE_MANUAL_PLL; } vlock_pll_stable_cnt = 0; - vlock_pll_stable_flag = 0; vlock_enc_stable_flag = 0; } @@ -585,7 +587,6 @@ static void vlock_enable_step1(struct vframe_s *vf, struct vinfo_s *vinfo, vlock_state = VLOCK_STATE_ENABLE_STEP1_DONE; vlock_pll_stable_cnt = 0; vlock_log_cnt = 0; - vlock_pll_stable_flag = 0; vlock_enc_stable_flag = 0; } @@ -929,6 +930,11 @@ static void vlock_enable_step3_pll(void) ia = READ_VPP_REG(VPU_VLOCK_RO_VS_I_DIST); oa = READ_VPP_REG(VPU_VLOCK_RO_VS_O_DIST); abs_cnt = abs(ia - oa); + if (abs_cnt > (oa / 3)) { + if (vlock_debug & VLOCK_DEBUG_INFO) + pr_info("%s:vlock input cnt abnormal!!\n", __func__); + return; + } /*frac*/ amvecm_hiu_reg_read(hiu_reg_addr, &tmp_value); abs_val = abs(((m_reg_value & 0xfff) >> 2) - (tmp_value & 0xfff)); @@ -950,8 +956,6 @@ static void vlock_enable_step3_pll(void) vlock_pll_stable_cnt++; else vlock_pll_stable_cnt = 0; - if (vlock_pll_stable_flag++ > VLOCK_PLL_STABLE_CNT) - vlock_pll_stable_flag = VLOCK_PLL_STABLE_CNT; /*m*/ amvecm_hiu_reg_read(HHI_HDMI_PLL_CNTL, &tmp_value); abs_val = abs(((m_reg_value >> 16) & 0x1ff) - (pre_hiu_reg_m & 0x1ff)); @@ -973,7 +977,7 @@ static void vlock_enable_step3_pll(void) vlock_pll_stable_cnt = 0; } /* won't change this function internal seqence, - * if really need change,please be carefull + * if really need change,please be carefull and check with vlsi */ void amve_vlock_process(struct vframe_s *vf) { @@ -1088,7 +1092,7 @@ void amve_vlock_process(struct vframe_s *vf) (vlock_mode & VLOCK_MODE_MANUAL_MIX_PLL_ENC) && (vlock_pll_stable_cnt > - vlock_pll_stable_limit)) { + VLOCK_PLL_STABLE_LIMIT)) { vlock_mode &= ~VLOCK_MODE_MANUAL_MIX_PLL_ENC; vlock_mode |= VLOCK_MODE_MANUAL_SOFT_ENC; vlock_state = VLOCK_STATE_ENABLE_FORCE_RESET; @@ -1201,6 +1205,9 @@ void vlock_param_set(unsigned int val, enum vlock_param_e sel) case VLOCK_LINE_LIMIT: vlock_line_limit = val; break; + case VLOCK_SUPPORT: + vlock_support = val; + break; default: pr_info("%s:unknown vlock param:%d\n", __func__, sel); break; @@ -1235,9 +1242,8 @@ void vlock_status(void) pr_info("vlock_capture_limit:0x%x\n", vlock_capture_limit); pr_info("vlock_line_limit:%d\n", vlock_line_limit); pr_info("vlock_pll_stable_cnt:%d\n", vlock_pll_stable_cnt); - pr_info("vlock_pll_stable_limit:%d\n", vlock_pll_stable_limit); pr_info("vlock_enc_adj_limit:%d\n", vlock_enc_adj_limit); - pr_info("vlock_pll_stable_flag:%d\n", vlock_pll_stable_flag); + pr_info("vlock_support:%d\n", vlock_support); pr_info("vlock_enc_stable_flag:%d\n", vlock_enc_stable_flag); pr_info("vlock_intput_type:%d\n", vlock_intput_type); pr_info("vlock_pll_adj_limit:%d\n", vlock_pll_adj_limit); diff --git a/drivers/amlogic/media/enhancement/amvecm/vlock.h b/drivers/amlogic/media/enhancement/amvecm/vlock.h index 513c266c404a..96784fb753f8 100644 --- a/drivers/amlogic/media/enhancement/amvecm/vlock.h +++ b/drivers/amlogic/media/enhancement/amvecm/vlock.h @@ -23,7 +23,7 @@ #include #include "linux/amlogic/media/amvecm/ve.h" -#define VLOCK_VER "Ref.2018/10/16a" +#define VLOCK_VER "Ref.2018/11/07a" #define VLOCK_REG_NUM 33 @@ -55,6 +55,7 @@ enum vlock_param_e { VLOCK_SYNC_LIMIT_FLAG, VLOCK_DIS_CNT_NO_VF_LIMIT, VLOCK_LINE_LIMIT, + VLOCK_SUPPORT, VLOCK_PARAM_MAX, }; @@ -85,7 +86,11 @@ extern void vlock_log_print(void); #define XTAL_VLOCK_CLOCK 24000000/*vlock use xtal clock*/ -#define VLOCK_PLL_STABLE_CNT 180/*vlock pll stabel cnt limit*/ +#define VLOCK_SUPPORT_HDMI (1 << 0) +#define VLOCK_SUPPORT_CVBS (1 << 1) + +/*10s for 60hz input,vlock pll stabel cnt limit*/ +#define VLOCK_PLL_STABLE_LIMIT 600 #define VLOCK_ENC_STABLE_CNT 180/*vlock enc stabel cnt limit*/ #define VLOCK_PLL_ADJ_LIMIT 9/*vlock pll adj limit(0x300a default)*/ diff --git a/drivers/amlogic/media/frame_sync/ptsserv.c b/drivers/amlogic/media/frame_sync/ptsserv.c index 206e50d12f8b..dde139fb99eb 100644 --- a/drivers/amlogic/media/frame_sync/ptsserv.c +++ b/drivers/amlogic/media/frame_sync/ptsserv.c @@ -455,6 +455,7 @@ static int pts_checkin_offset_inline(u8 type, u32 offset, u32 val, u64 uS64) } if (type == PTS_TYPE_AUDIO && pTable->first_checkin_pts == -1) { pTable->first_checkin_pts = val; + timestamp_checkin_firstapts_set(val); /* *if (tsync_get_debug_pts_checkin() && * tsync_get_debug_apts()) { @@ -855,7 +856,7 @@ static int pts_lookup_offset_inline_locked(u8 type, u32 offset, u32 *val, && (VAL_DIFF(p->val, p2->val) >= 0)) { /* do interpolation between [p2, p] */ *val = - div_u64(((p->val - p2->val) * + div_u64((((u64)p->val - p2->val) * (offset - p2->offset)), (p->offset - p2->offset)) + p2->val; diff --git a/drivers/amlogic/media/frame_sync/timestamp.c b/drivers/amlogic/media/frame_sync/timestamp.c index c5bcf050501c..472be72c92b2 100644 --- a/drivers/amlogic/media/frame_sync/timestamp.c +++ b/drivers/amlogic/media/frame_sync/timestamp.c @@ -36,6 +36,7 @@ static u32 audio_pts_up; static u32 audio_pts_started; static u32 first_vpts; static u32 first_checkin_vpts; +static u32 first_checkin_apts; static u32 first_apts; static u32 pcrscr_lantcy = 200*90; static u32 video_pts; @@ -134,8 +135,18 @@ u32 timestamp_pcrscr_get(void) } EXPORT_SYMBOL(timestamp_pcrscr_get); +u32 timestamp_tsdemux_pcr_get(void) +{ + if (tsdemux_pcrscr_get_cb) + return tsdemux_pcrscr_get_cb(); + + return (u32)-1; +} +EXPORT_SYMBOL(timestamp_tsdemux_pcr_get); + void timestamp_pcrscr_set(u32 pts) { + /*pr_info("timestamp_pcrscr_set system time = %x\n", pts);*/ system_time = pts; } EXPORT_SYMBOL(timestamp_pcrscr_set); @@ -160,12 +171,25 @@ void timestamp_checkin_firstvpts_set(u32 pts) } EXPORT_SYMBOL(timestamp_checkin_firstvpts_set); +void timestamp_checkin_firstapts_set(u32 pts) +{ + first_checkin_apts = pts; + pr_info("audio first checkin pts =%x\n", first_checkin_apts); +} +EXPORT_SYMBOL(timestamp_checkin_firstapts_set); + u32 timestamp_checkin_firstvpts_get(void) { return first_checkin_vpts; } EXPORT_SYMBOL(timestamp_checkin_firstvpts_get); +u32 timestamp_checkin_firstapts_get(void) +{ + return first_checkin_apts; +} +EXPORT_SYMBOL(timestamp_checkin_firstapts_get); + void timestamp_firstapts_set(u32 pts) { first_apts = pts; diff --git a/drivers/amlogic/media/frame_sync/tsync.c b/drivers/amlogic/media/frame_sync/tsync.c index cb2fc32d7cf0..df091fe34171 100644 --- a/drivers/amlogic/media/frame_sync/tsync.c +++ b/drivers/amlogic/media/frame_sync/tsync.c @@ -745,17 +745,18 @@ void tsync_avevent_locked(enum avevent_e event, u32 param) switch (event) { case VIDEO_START: tsync_video_started = 1; - /* - *set tsync mode to vmaster to avoid video block caused - *by avpts-diff too much - *threshold 120s is an arbitrary value - */ + + //set tsync mode to vmaster to avoid video block caused + // by avpts-diff too much + //threshold 120s is an arbitrary value + if (tsync_enable && !get_vsync_pts_inc_mode()) tsync_mode = TSYNC_MODE_AMASTER; - else { + else{ tsync_mode = TSYNC_MODE_VMASTER; if (get_vsync_pts_inc_mode()) tsync_stat = TSYNC_STAT_PCRSCR_SETUP_NONE; + } if (tsync_dec_reset_flag) @@ -786,6 +787,8 @@ void tsync_avevent_locked(enum avevent_e event, u32 param) if (abs(param - t) > tsync_av_threshold_max) { /* if this happens, then play */ tsync_stat = TSYNC_STAT_PCRSCR_SETUP_VIDEO; + tsync_mode = TSYNC_MODE_VMASTER; + tsync_enable = 0; timestamp_pcrscr_set(param); set_pts_realign(); } @@ -822,7 +825,6 @@ void tsync_avevent_locked(enum avevent_e event, u32 param) case VIDEO_TSTAMP_DISCONTINUITY: { unsigned int oldpts = timestamp_vpts_get(); int oldmod = tsync_mode; - if (tsync_mode == TSYNC_MODE_VMASTER) t = timestamp_apts_get(); else @@ -838,6 +840,7 @@ void tsync_avevent_locked(enum avevent_e event, u32 param) tsync_mode_switch('V', abs(param - t), param - oldpts); } + timestamp_vpts_set(param); if (tsync_mode == TSYNC_MODE_VMASTER) { timestamp_pcrscr_set(param); @@ -866,7 +869,6 @@ void tsync_avevent_locked(enum avevent_e event, u32 param) t = timestamp_vpts_get(); else t = timestamp_pcrscr_get(); - amlog_level(LOG_LEVEL_ATTENTION, "AUDIO_TSTAMP_DISCONTINUITY, 0x%x, 0x%x\n", t, param); @@ -1441,7 +1443,7 @@ static ssize_t store_vpts(struct class *class, ssize_t r; /*r = sscanf(buf, "0x%x", &pts);*/ - r = kstrtoint(buf, 0, &pts); + r = kstrtouint(buf, 0, &pts); if (r != 0) return -EINVAL; @@ -1450,6 +1452,12 @@ static ssize_t store_vpts(struct class *class, return size; } +static ssize_t show_demux_pcr(struct class *class, + struct class_attribute *attr, char *buf) +{ + return sprintf(buf, "0x%x\n", timestamp_tsdemux_pcr_get()); +} + static ssize_t show_apts(struct class *class, struct class_attribute *attr, char *buf) { @@ -1462,9 +1470,7 @@ static ssize_t store_apts(struct class *class, { unsigned int pts; ssize_t r; - - /*r = sscanf(buf, "0x%x", &pts);*/ - r = kstrtoint(buf, 0, &pts); + r = kstrtouint(buf, 0, &pts); if (r != 0) return -EINVAL; @@ -1868,6 +1874,12 @@ static ssize_t show_checkin_firstvpts(struct class *class, return sprintf(buf, "0x%x\n", timestamp_checkin_firstvpts_get()); } +static ssize_t show_checkin_firstapts(struct class *class, + struct class_attribute *attr, char *buf) +{ + return sprintf(buf, "0x%x\n", timestamp_checkin_firstapts_get()); +} + static ssize_t show_vpause_flag(struct class *class, struct class_attribute *attr, char *buf) { @@ -2002,7 +2014,11 @@ static struct class_attribute tsync_class_attrs[] = { __ATTR(checkin_firstvpts, 0644, show_checkin_firstvpts, NULL), __ATTR(apts_lookup, 0644, show_apts_lookup, - store_apts_lookup), + store_apts_lookup), + __ATTR(demux_pcr, 0644, show_demux_pcr, + NULL), + __ATTR(checkin_firstapts, 0644, show_checkin_firstapts, + NULL), __ATTR_NULL }; diff --git a/drivers/amlogic/media/osd/osd.h b/drivers/amlogic/media/osd/osd.h index 57004bf2e83e..161e504bac8b 100644 --- a/drivers/amlogic/media/osd/osd.h +++ b/drivers/amlogic/media/osd/osd.h @@ -276,6 +276,7 @@ enum cpuid_type_e { __MESON_CPU_MAJOR_ID_TXHD, __MESON_CPU_MAJOR_ID_G12A, __MESON_CPU_MAJOR_ID_G12B, + __MESON_CPU_MAJOR_ID_TL1, __MESON_CPU_MAJOR_ID_UNKNOWN, }; @@ -360,6 +361,12 @@ enum viu_type { VIU2, }; +enum render_cmd_type { + LAYER_SYNC, + BLANK_CMD, + PAGE_FLIP, +}; + struct pandata_s { s32 x_start; s32 x_end; @@ -464,6 +471,8 @@ struct layer_fence_map_s { struct osd_layers_fence_map_s { struct list_head list; int out_fd; + unsigned char hdr_mode; + unsigned char cmd; struct display_flip_info_s disp_info; struct layer_fence_map_s layer_map[HW_OSD_COUNT]; }; @@ -494,6 +503,8 @@ struct osd_device_data_s { u32 vpp_fifo_len; u32 dummy_data; u32 has_viu2; + u32 viu1_osd_count; + u32 viu2_index; struct clk *vpu_clkc; }; @@ -579,32 +590,24 @@ struct layer_blend_s { struct dispdata_s input1_data; struct dispdata_s input2_data; struct dispdata_s output_data; - u32 background_w; - u32 background_h; u32 blend_core1_bypass; }; struct hw_osd_blending_s { u8 osd_blend_mode; u8 osd_to_bdin_table[OSD_BLEND_LAYERS]; u8 reorder[HW_OSD_COUNT]; + u8 blend_din; u32 din_reoder_sel; u32 layer_cnt; - bool change_order; bool b_exchange_din; bool b_exchange_blend_in; bool osd1_freescale_used; bool osd1_freescale_disable; - bool bscaler_down[HW_OSD_COUNT]; - u32 background_w; - u32 background_h; u32 vinfo_width; u32 vinfo_height; - u32 screen1_ratio_w; - u32 screen1_ratio_h; - u32 screen2_ratio_w; - u32 screen2_ratio_h; - u32 pic_w_ratio; - u32 pic_h_ratio; + u32 screen_ratio_w; + u32 screen_ratio_h; + struct dispdata_s dst_data; struct layer_blend_reg_s blend_reg; struct layer_blend_s layer_blend; }; @@ -734,7 +737,6 @@ struct hw_para_s { u32 osd_clear[HW_OSD_COUNT]; u32 vinfo_width; u32 vinfo_height; - u32 b_interlaced; u32 fb_drvier_probe; u32 afbc_force_reset; u32 afbc_regs_backup; @@ -746,8 +748,6 @@ struct hw_para_s { u32 hw_rdma_en; u32 blend_bypass; u32 hdr_used; - u32 workaround_hdr; - u32 workaround_not_hdr; u32 basic_urgent; u32 two_ports; u32 afbc_err_cnt; diff --git a/drivers/amlogic/media/osd/osd_antiflicker.c b/drivers/amlogic/media/osd/osd_antiflicker.c index 37d0a02c1c7c..cdcd26f8292e 100644 --- a/drivers/amlogic/media/osd/osd_antiflicker.c +++ b/drivers/amlogic/media/osd/osd_antiflicker.c @@ -81,7 +81,7 @@ static int osd_antiflicker_process(void) mutex_lock(&osd_antiflicker_mutex); #ifdef CONFIG_AMLOGIC_MEDIA_CANVAS - if (get_cpu_type() != MESON_CPU_MAJOR_ID_AXG) { + if (osd_hw.osd_meson_dev.cpu_id != MESON_CPU_MAJOR_ID_AXG) { canvas_read(OSD1_CANVAS_INDEX, &cs); canvas_read(OSD1_CANVAS_INDEX, &cd); cs_addr = cs.addr; diff --git a/drivers/amlogic/media/osd/osd_backup.c b/drivers/amlogic/media/osd/osd_backup.c index 1bef58937217..64d9cd965f87 100644 --- a/drivers/amlogic/media/osd/osd_backup.c +++ b/drivers/amlogic/media/osd/osd_backup.c @@ -173,7 +173,7 @@ u32 is_backup(void) /* recovery section */ #define INVAILD_REG_ITEM {0xffff, 0x0, 0x0, 0x0} -#define REG_RECOVERY_TABLE 11 +#define REG_RECOVERY_TABLE 12 static struct reg_recovery_table gRecovery[REG_RECOVERY_TABLE]; static u32 recovery_enable; @@ -409,7 +409,7 @@ static struct reg_item osd1_sc_recovery_table_g12a[] = { {VPP_OSD_SCALE_COEF, 0x0, 0xffffffff, 0} }; -static struct reg_item osd23_sc_recovery_table_g12a[] = { +static struct reg_item osd2_sc_recovery_table_g12a[] = { {OSD2_VSC_PHASE_STEP, 0x0, 0x0fffffff, 1}, {OSD2_VSC_INI_PHASE, 0x0, 0xffffffff, 1}, {OSD2_VSC_CTRL0, 0x0, 0x01fb7b7f, 1}, @@ -436,10 +436,9 @@ static struct reg_item osd23_sc_recovery_table_g12a[] = { INVAILD_REG_ITEM, /* 0x3d17 */ {OSD2_SCALE_COEF_IDX, 0x0, 0x0000c37f, 0}, {OSD2_SCALE_COEF, 0x0, 0xffffffff, 0}, - INVAILD_REG_ITEM, /* 0x3d1a */ - INVAILD_REG_ITEM, /* 0x3d1b */ - INVAILD_REG_ITEM, /* 0x3d1c */ - INVAILD_REG_ITEM, /* 0x3d1d */ +}; + +static struct reg_item osd3_sc_recovery_table_g12a[] = { {OSD34_SCALE_COEF_IDX, 0x0, 0x0000c37f, 0}, {OSD34_SCALE_COEF, 0x0, 0xffffffff, 0}, {OSD34_VSC_PHASE_STEP, 0x0, 0x0fffffff, 1}, @@ -765,12 +764,14 @@ static void recovery_regs_init_g12a(void) gRecovery[i].table = (struct reg_item *)&osd12_recovery_table_g12a[0]; - i++; - gRecovery[i].base_addr = VIU_OSD3_CTRL_STAT; - gRecovery[i].size = sizeof(osd3_recovery_table_g12a) - / sizeof(struct reg_item); - gRecovery[i].table = - (struct reg_item *)&osd3_recovery_table_g12a[0]; + if ((osd_hw.osd_meson_dev.viu1_osd_count - 1) == DEV_OSD3) { + i++; + gRecovery[i].base_addr = VIU_OSD3_CTRL_STAT; + gRecovery[i].size = sizeof(osd3_recovery_table_g12a) + / sizeof(struct reg_item); + gRecovery[i].table = + (struct reg_item *)&osd3_recovery_table_g12a[0]; + } i++; gRecovery[i].base_addr = VPP_OSD_VSC_PHASE_STEP; @@ -781,10 +782,19 @@ static void recovery_regs_init_g12a(void) i++; gRecovery[i].base_addr = OSD2_VSC_PHASE_STEP; - gRecovery[i].size = sizeof(osd23_sc_recovery_table_g12a) + gRecovery[i].size = sizeof(osd2_sc_recovery_table_g12a) / sizeof(struct reg_item); gRecovery[i].table = - (struct reg_item *)&osd23_sc_recovery_table_g12a[0]; + (struct reg_item *)&osd2_sc_recovery_table_g12a[0]; + + if ((osd_hw.osd_meson_dev.viu1_osd_count - 1) == DEV_OSD3) { + i++; + gRecovery[i].base_addr = OSD34_SCALE_COEF_IDX; + gRecovery[i].size = sizeof(osd3_sc_recovery_table_g12a) + / sizeof(struct reg_item); + gRecovery[i].table = + (struct reg_item *)&osd3_sc_recovery_table_g12a[0]; + } i++; gRecovery[i].base_addr = VPU_MAFBC_BLOCK_ID; @@ -844,8 +854,7 @@ void recovery_regs_init(void) return; memset(gRecovery, 0, sizeof(gRecovery)); - if ((cpu_id == __MESON_CPU_MAJOR_ID_G12A) || - (cpu_id == __MESON_CPU_MAJOR_ID_G12B)) + if (cpu_id >= __MESON_CPU_MAJOR_ID_G12A) recovery_regs_init_g12a(); else recovery_regs_init_old(); @@ -1168,8 +1177,6 @@ static int update_recovery_item_g12a(u32 addr, u32 value) } break; case OSD2_VSC_PHASE_STEP: - case 0x3d10: - case OSD34_VSC_PHASE_STEP: /* osd2 osd 3 sc */ base = gRecovery[3].base_addr; size = gRecovery[3].size; @@ -1182,13 +1189,8 @@ static int update_recovery_item_g12a(u32 addr, u32 value) ret = 0; } break; - case VPU_MAFBC_BLOCK_ID: - /* vpu mali common */ - if (backup_enable & - HW_RESET_MALI_AFBCD_REGS) { - ret = 1; - break; - } + case OSD34_VSC_PHASE_STEP: + /* osd2 osd 3 sc */ base = gRecovery[4].base_addr; size = gRecovery[4].size; table = gRecovery[4].table; @@ -1200,8 +1202,8 @@ static int update_recovery_item_g12a(u32 addr, u32 value) ret = 0; } break; - case VPU_MAFBC_HEADER_BUF_ADDR_LOW_S0: - /* vpu mali src0 */ + case VPU_MAFBC_BLOCK_ID: + /* vpu mali common */ if (backup_enable & HW_RESET_MALI_AFBCD_REGS) { ret = 1; @@ -1218,8 +1220,8 @@ static int update_recovery_item_g12a(u32 addr, u32 value) ret = 0; } break; - case VPU_MAFBC_HEADER_BUF_ADDR_LOW_S1: - /* vpu mali src1 */ + case VPU_MAFBC_HEADER_BUF_ADDR_LOW_S0: + /* vpu mali src0 */ if (backup_enable & HW_RESET_MALI_AFBCD_REGS) { ret = 1; @@ -1236,8 +1238,8 @@ static int update_recovery_item_g12a(u32 addr, u32 value) ret = 0; } break; - case VPU_MAFBC_HEADER_BUF_ADDR_LOW_S2: - /* vpu mali src2 */ + case VPU_MAFBC_HEADER_BUF_ADDR_LOW_S1: + /* vpu mali src1 */ if (backup_enable & HW_RESET_MALI_AFBCD_REGS) { ret = 1; @@ -1254,9 +1256,13 @@ static int update_recovery_item_g12a(u32 addr, u32 value) ret = 0; } break; - case VIU_OSD_BLEND_CTRL: - case VIU_OSD_BLEND_CTRL1: - /* osd blend ctrl */ + case VPU_MAFBC_HEADER_BUF_ADDR_LOW_S2: + /* vpu mali src2 */ + if (backup_enable & + HW_RESET_MALI_AFBCD_REGS) { + ret = 1; + break; + } base = gRecovery[8].base_addr; size = gRecovery[8].size; table = gRecovery[8].table; @@ -1268,8 +1274,9 @@ static int update_recovery_item_g12a(u32 addr, u32 value) ret = 0; } break; - case VPP_VD2_HDR_IN_SIZE: - /* vpp blend ctrl */ + case VIU_OSD_BLEND_CTRL: + case VIU_OSD_BLEND_CTRL1: + /* osd blend ctrl */ base = gRecovery[9].base_addr; size = gRecovery[9].size; table = gRecovery[9].table; @@ -1281,6 +1288,19 @@ static int update_recovery_item_g12a(u32 addr, u32 value) ret = 0; } break; + case VPP_VD2_HDR_IN_SIZE: + /* vpp blend ctrl */ + base = gRecovery[10].base_addr; + size = gRecovery[10].size; + table = gRecovery[10].table; + if ((addr >= base) && + (addr < base + size)) { + table[addr - base].val = value; + if (table[addr - base].recovery) + table[addr - base].recovery = 1; + ret = 0; + } + break; default: break; } @@ -1294,8 +1314,8 @@ static int update_recovery_item_g12a(u32 addr, u32 value) (addr == VIU_OSD2_MALI_UNPACK_CTRL) || (addr == DOLBY_CORE2A_SWAP_CTRL1) || (addr == DOLBY_CORE2A_SWAP_CTRL2)) { - table = gRecovery[10].table; - for (i = 0; i < gRecovery[10].size; i++) { + table = gRecovery[11].table; + for (i = 0; i < gRecovery[11].size; i++) { if (addr == table[i].addr) { table[i].val = value; if (table[i].recovery) @@ -1383,9 +1403,7 @@ static s32 get_recovery_item_g12a(u32 addr, u32 *value, u32 *mask) } break; case OSD2_VSC_PHASE_STEP: - case 0x3d10: - case OSD34_VSC_PHASE_STEP: - /* osd2 osd 3 sc */ + /* osd2 */ base = gRecovery[3].base_addr; size = gRecovery[3].size; table = gRecovery[3].table; @@ -1395,13 +1413,8 @@ static s32 get_recovery_item_g12a(u32 addr, u32 *value, u32 *mask) ret = 0; } break; - case VPU_MAFBC_BLOCK_ID: - /* vpu mali common */ - if (backup_enable & - HW_RESET_MALI_AFBCD_REGS) { - ret = 2; - break; - } + case OSD34_VSC_PHASE_STEP: + /* osd3 sc */ base = gRecovery[4].base_addr; size = gRecovery[4].size; table = gRecovery[4].table; @@ -1411,8 +1424,8 @@ static s32 get_recovery_item_g12a(u32 addr, u32 *value, u32 *mask) ret = 0; } break; - case VPU_MAFBC_HEADER_BUF_ADDR_LOW_S0: - /* vpu mali src0 */ + case VPU_MAFBC_BLOCK_ID: + /* vpu mali common */ if (backup_enable & HW_RESET_MALI_AFBCD_REGS) { ret = 2; @@ -1427,8 +1440,8 @@ static s32 get_recovery_item_g12a(u32 addr, u32 *value, u32 *mask) ret = 0; } break; - case VPU_MAFBC_HEADER_BUF_ADDR_LOW_S1: - /* vpu mali src1 */ + case VPU_MAFBC_HEADER_BUF_ADDR_LOW_S0: + /* vpu mali src0 */ if (backup_enable & HW_RESET_MALI_AFBCD_REGS) { ret = 2; @@ -1443,8 +1456,8 @@ static s32 get_recovery_item_g12a(u32 addr, u32 *value, u32 *mask) ret = 0; } break; - case VPU_MAFBC_HEADER_BUF_ADDR_LOW_S2: - /* vpu mali src2 */ + case VPU_MAFBC_HEADER_BUF_ADDR_LOW_S1: + /* vpu mali src1 */ if (backup_enable & HW_RESET_MALI_AFBCD_REGS) { ret = 2; @@ -1459,9 +1472,13 @@ static s32 get_recovery_item_g12a(u32 addr, u32 *value, u32 *mask) ret = 0; } break; - case VIU_OSD_BLEND_CTRL: - case VIU_OSD_BLEND_CTRL1: - /* osd blend ctrl */ + case VPU_MAFBC_HEADER_BUF_ADDR_LOW_S2: + /* vpu mali src2 */ + if (backup_enable & + HW_RESET_MALI_AFBCD_REGS) { + ret = 2; + break; + } base = gRecovery[8].base_addr; size = gRecovery[8].size; table = gRecovery[8].table; @@ -1471,8 +1488,9 @@ static s32 get_recovery_item_g12a(u32 addr, u32 *value, u32 *mask) ret = 0; } break; - case VPP_VD2_HDR_IN_SIZE: - /* vpp blend ctrl */ + case VIU_OSD_BLEND_CTRL: + case VIU_OSD_BLEND_CTRL1: + /* osd blend ctrl */ base = gRecovery[9].base_addr; size = gRecovery[9].size; table = gRecovery[9].table; @@ -1482,6 +1500,17 @@ static s32 get_recovery_item_g12a(u32 addr, u32 *value, u32 *mask) ret = 0; } break; + case VPP_VD2_HDR_IN_SIZE: + /* vpp blend ctrl */ + base = gRecovery[10].base_addr; + size = gRecovery[10].size; + table = gRecovery[10].table; + if ((addr >= base) && + (addr < base + size)) { + table += (addr - base); + ret = 0; + } + break; default: break; } @@ -1495,8 +1524,8 @@ static s32 get_recovery_item_g12a(u32 addr, u32 *value, u32 *mask) (addr == VIU_OSD2_MALI_UNPACK_CTRL) || (addr == DOLBY_CORE2A_SWAP_CTRL1) || (addr == DOLBY_CORE2A_SWAP_CTRL2)) { - table = gRecovery[10].table; - for (i = 0; i < gRecovery[10].size; i++) { + table = gRecovery[11].table; + for (i = 0; i < gRecovery[11].size; i++) { if (addr == table[i].addr) { table += i; ret = 0; @@ -1540,8 +1569,7 @@ int update_recovery_item(u32 addr, u32 value) if (!recovery_enable) return ret; - if ((cpu_id == __MESON_CPU_MAJOR_ID_G12A) || - (cpu_id == __MESON_CPU_MAJOR_ID_G12B)) + if (cpu_id >= __MESON_CPU_MAJOR_ID_G12A) ret = update_recovery_item_g12a(addr, value); else ret = update_recovery_item_old(addr, value); @@ -1557,8 +1585,7 @@ s32 get_recovery_item(u32 addr, u32 *value, u32 *mask) if (!recovery_enable) return ret; - if ((cpu_id == __MESON_CPU_MAJOR_ID_G12A) || - (cpu_id == __MESON_CPU_MAJOR_ID_G12B)) + if (cpu_id >= __MESON_CPU_MAJOR_ID_G12A) ret = get_recovery_item_g12a(addr, value, mask); else ret = get_recovery_item_old(addr, value, mask); diff --git a/drivers/amlogic/media/osd/osd_clone.c b/drivers/amlogic/media/osd/osd_clone.c index b9cbfc375686..533f8cd8a75b 100644 --- a/drivers/amlogic/media/osd/osd_clone.c +++ b/drivers/amlogic/media/osd/osd_clone.c @@ -73,7 +73,7 @@ static void osd_clone_process(void) struct config_para_ex_s *ge2d_config = &s_osd_clone.ge2d_config; struct ge2d_context_s *context = s_osd_clone.ge2d_context; #ifdef CONFIG_AMLOGIC_MEDIA_CANVAS - if (get_cpu_type() != MESON_CPU_MAJOR_ID_AXG) { + if (osd_hw.osd_meson_dev.cpu_id != MESON_CPU_MAJOR_ID_AXG) { canvas_read(OSD1_CANVAS_INDEX, &cs); canvas_read(OSD2_CANVAS_INDEX, &cd); cs_addr = cs.addr; diff --git a/drivers/amlogic/media/osd/osd_debug.c b/drivers/amlogic/media/osd/osd_debug.c index 9666960ed9a6..58d8261b8edf 100644 --- a/drivers/amlogic/media/osd/osd_debug.c +++ b/drivers/amlogic/media/osd/osd_debug.c @@ -74,9 +74,6 @@ static void osd_debug_dump_value(void) osd_get_blending_para(&blend_para); if (blend_para != NULL) { osd_log_info("OSD LAYER: %d\n", blend_para->layer_cnt); - osd_log_info("OSD background size: %d, %d\n", - blend_para->background_w, - blend_para->background_h); osd_log_info("|index\t|order\t|src axis\t|dst axis\n"); for (index = 0; index < HW_OSD_COUNT; index++) { osd_log_info("%2d\t%2d\t(%4d,%4d,%4d,%4d)\t(%4d,%4d,%4d,%4d)\n", @@ -199,10 +196,16 @@ static void osd_debug_dump_register_all(void) osd_log_info("reg[0x%x]: 0x%08x\n", reg, osd_reg_read(reg)); reg = VPP_OSD2_BLD_V_SCOPE; osd_log_info("reg[0x%x]: 0x%08x\n", reg, osd_reg_read(reg)); + reg = VD1_BLEND_SRC_CTRL; + osd_log_info("reg[0x%x]: 0x%08x\n", reg, osd_reg_read(reg)); + reg = VD2_BLEND_SRC_CTRL; + osd_log_info("reg[0x%x]: 0x%08x\n", reg, osd_reg_read(reg)); reg = OSD1_BLEND_SRC_CTRL; osd_log_info("reg[0x%x]: 0x%08x\n", reg, osd_reg_read(reg)); reg = OSD2_BLEND_SRC_CTRL; osd_log_info("reg[0x%x]: 0x%08x\n", reg, osd_reg_read(reg)); + reg = VIU_OSD_BLEND_CTRL1; + osd_log_info("reg[0x%x]: 0x%08x\n", reg, osd_reg_read(reg)); reg = VPP_POSTBLEND_H_SIZE; osd_log_info("reg[0x%x]: 0x%08x\n", reg, osd_reg_read(reg)); reg = VPP_OUT_H_V_SIZE; diff --git a/drivers/amlogic/media/osd/osd_drm.c b/drivers/amlogic/media/osd/osd_drm.c index ecf02eb5a7e3..86083a85535c 100644 --- a/drivers/amlogic/media/osd/osd_drm.c +++ b/drivers/amlogic/media/osd/osd_drm.c @@ -61,27 +61,27 @@ static int parse_para(const char *para, int para_num, int *result) params = kstrdup(para, GFP_KERNEL); params_base = params; token = params; - if (!token) - return 0; - len = strlen(token); - do { - token = strsep(¶ms, " "); - while (token && (isspace(*token) - || !isgraph(*token)) && len) { - token++; - len--; - } - if (len == 0) - break; - ret = kstrtoint(token, 0, &res); - if (ret < 0) - break; - if (!token) - return 0; + if (token) { len = strlen(token); - *out++ = res; - count++; - } while ((token) && (count < para_num) && (len > 0)); + do { + token = strsep(¶ms, " "); + if (!token) + break; + while (token && (isspace(*token) + || !isgraph(*token)) && len) { + token++; + len--; + } + if (len == 0) + break; + ret = kstrtoint(token, 0, &res); + if (ret < 0) + break; + len = strlen(token); + *out++ = res; + count++; + } while ((count < para_num) && (len > 0)); + } kfree(params_base); return count; @@ -745,7 +745,7 @@ void osd_drm_vsync_isr_handler(void) osd_update_vsync_hit(); osd_hw_reset(); } else { - if (get_cpu_type() != __MESON_CPU_MAJOR_ID_AXG) + if (osd_hw.osd_meson_dev.cpu_id != __MESON_CPU_MAJOR_ID_AXG) osd_rdma_interrupt_done_clear(); else { osd_update_scan_mode(); diff --git a/drivers/amlogic/media/osd/osd_fb.c b/drivers/amlogic/media/osd/osd_fb.c index 6fd66093b2d7..2454dc3d20fd 100644 --- a/drivers/amlogic/media/osd/osd_fb.c +++ b/drivers/amlogic/media/osd/osd_fb.c @@ -1425,11 +1425,9 @@ static int malloc_osd_memory(struct fb_info *info) /* clear osd buffer if not logo layer */ if (((logo_index < 0) || (logo_index != fb_index)) || (osd_meson_dev.cpu_id == __MESON_CPU_MAJOR_ID_AXG) || - (osd_meson_dev.cpu_id == __MESON_CPU_MAJOR_ID_G12A) || - ((osd_meson_dev.cpu_id == __MESON_CPU_MAJOR_ID_G12B))) { + (osd_meson_dev.cpu_id >= __MESON_CPU_MAJOR_ID_G12A)) { osd_log_info("---------------clear fb%d memory %p\n", fb_index, fbdev->fb_mem_vaddr); - set_logo_loaded(); if (fbdev->fb_mem_vaddr) memset(fbdev->fb_mem_vaddr, 0x0, fbdev->fb_len); if (osd_meson_dev.afbc_type && osd_get_afbc(fb_index)) { @@ -1461,7 +1459,6 @@ static int malloc_osd_memory(struct fb_info *info) static int osd_open(struct fb_info *info, int arg) { u32 fb_index; - int logo_index; struct osd_fb_dev_s *fbdev; struct fb_fix_screeninfo *fix = NULL; int ret = 0; @@ -1509,13 +1506,14 @@ static int osd_open(struct fb_info *info, int arg) if (!fb_ion_client) fb_ion_client = meson_ion_client_create(-1, "meson-fb"); } - logo_index = osd_get_logo_index(); - /* clear osd buffer if not logo layer */ - if (((logo_index < 0) || (logo_index != fb_index)) || - (osd_meson_dev.cpu_id == __MESON_CPU_MAJOR_ID_AXG) || - (osd_meson_dev.cpu_id >= __MESON_CPU_MAJOR_ID_G12A)) { - osd_log_info("set logo loaded\n"); - set_logo_loaded(); + if (get_logo_loaded()) { + u32 logo_index; + + logo_index = osd_get_logo_index(); + if (logo_index < 0) { + osd_log_info("set logo loaded\n"); + set_logo_loaded(); + } } return 0; } @@ -1695,10 +1693,120 @@ int osd_notify_callback(struct notifier_block *block, unsigned long cmd, return -1; osd_hw.vinfo_width = vinfo->width; osd_hw.vinfo_height = vinfo->field_height; + osd_hw.field_out_en = is_interlaced(vinfo); switch (cmd) { case VOUT_EVENT_MODE_CHANGE: set_osd_logo_freescaler(); - for (i = 0; i < osd_meson_dev.osd_count; i++) { + if ((osd_meson_dev.osd_ver == OSD_NORMAL) + || (osd_meson_dev.osd_ver == OSD_SIMPLE) + || (osd_hw.hwc_enable == 0)) { + for (i = 0; i < osd_meson_dev.viu1_osd_count; i++) { + fb_dev = gp_fbdev_list[i]; + if (fb_dev == NULL) + continue; + set_default_display_axis(&fb_dev->fb_info->var, + &fb_dev->osd_ctl, vinfo); + console_lock(); + osddev_update_disp_axis(fb_dev, 1); + + osd_set_antiflicker_hw(DEV_OSD1, vinfo, + gp_fbdev_list[DEV_OSD1]->fb_info->var.yres); + osd_reg_write(VPP_POSTBLEND_H_SIZE, vinfo->width); + console_unlock(); + } + } + break; + case VOUT_EVENT_OSD_BLANK: + blank = *(int *)para; + for (i = 0; i < osd_meson_dev.viu1_osd_count; i++) { + fb_dev = gp_fbdev_list[i]; + if (fb_dev == NULL) + continue; + console_lock(); + osd_blank(blank, fb_dev->fb_info); + console_unlock(); + } + break; + case VOUT_EVENT_OSD_DISP_AXIS: + if ((osd_meson_dev.osd_ver == OSD_NORMAL) + || (osd_meson_dev.osd_ver == OSD_SIMPLE) + || (osd_hw.hwc_enable == 0)) { + + disp_rect = (struct disp_rect_s *)para; + for (i = 0; i < osd_meson_dev.viu1_osd_count; i++) { + if (!disp_rect) + break; + + /* vout serve send only two layer axis */ + if (i >= 2) + break; + + fb_dev = gp_fbdev_list[i]; + /* + * if osd layer preblend, + * it's position is controlled by vpp. + if (fb_dev->preblend_enable) + break; + */ + fb_dev->osd_ctl.disp_start_x = disp_rect->x; + fb_dev->osd_ctl.disp_start_y = disp_rect->y; + osd_log_dbg("set disp axis: x:%d y:%d w:%d h:%d\n", + disp_rect->x, disp_rect->y, + disp_rect->w, disp_rect->h); + if (disp_rect->x + disp_rect->w > vinfo->width) + fb_dev->osd_ctl.disp_end_x = vinfo->width - 1; + else + fb_dev->osd_ctl.disp_end_x = + fb_dev->osd_ctl.disp_start_x + + disp_rect->w - 1; + if (disp_rect->y + disp_rect->h > vinfo->height) + fb_dev->osd_ctl.disp_end_y = vinfo->height - 1; + else + fb_dev->osd_ctl.disp_end_y = + fb_dev->osd_ctl.disp_start_y + + disp_rect->h - 1; + disp_rect++; + osd_log_dbg("new disp axis: x0:%d y0:%d x1:%d y1:%d\n", + fb_dev->osd_ctl.disp_start_x, + fb_dev->osd_ctl.disp_start_y, + fb_dev->osd_ctl.disp_end_x, + fb_dev->osd_ctl.disp_end_y); + console_lock(); + osddev_update_disp_axis(fb_dev, 0); + console_unlock(); + } + } + break; + } + return 0; +} + +#if 0 +int osd_notify_callback(struct notifier_block *block, unsigned long cmd, + void *para) +{ + struct vinfo_s *vinfo; + struct osd_fb_dev_s *fb_dev; + int i, blank; + struct disp_rect_s *disp_rect; + + vinfo = get_current_vinfo(); + if (!vinfo) { + osd_log_err("current vinfo NULL\n"); + return -1; + } + osd_log_info("current vmode=%s, cmd: 0x%lx\n", + vinfo->name, cmd); + if ((!strcmp(vinfo->name, "invalid")) || + (!strcmp(vinfo->name, "null"))) + return -1; + osd_hw.vinfo_width = vinfo->width; + osd_hw.vinfo_height = vinfo->field_height; + osd_hw.field_out_en = is_interlaced(vinfo); + switch (cmd) { + case VOUT_EVENT_MODE_CHANGE: + set_osd_logo_freescaler(); + for (i = 0; i < osd_meson_dev.viu1_osd_count; i++) { fb_dev = gp_fbdev_list[i]; if (fb_dev == NULL) continue; @@ -1720,7 +1828,7 @@ int osd_notify_callback(struct notifier_block *block, unsigned long cmd, break; case VOUT_EVENT_OSD_BLANK: blank = *(int *)para; - for (i = 0; i < osd_meson_dev.osd_count; i++) { + for (i = 0; i < osd_meson_dev.viu1_osd_count; i++) { fb_dev = gp_fbdev_list[i]; if (fb_dev == NULL) continue; @@ -1731,7 +1839,7 @@ int osd_notify_callback(struct notifier_block *block, unsigned long cmd, break; case VOUT_EVENT_OSD_DISP_AXIS: disp_rect = (struct disp_rect_s *)para; - for (i = 0; i < osd_meson_dev.osd_count; i++) { + for (i = 0; i < osd_meson_dev.viu1_osd_count; i++) { if (!disp_rect) break; @@ -1777,7 +1885,7 @@ int osd_notify_callback(struct notifier_block *block, unsigned long cmd, } return 0; } - +#endif int osd_notify_callback_viu2(struct notifier_block *block, unsigned long cmd, void *para) { @@ -1798,7 +1906,7 @@ int osd_notify_callback_viu2(struct notifier_block *block, unsigned long cmd, vinfo->name, cmd); if (!strcmp(vinfo->name, "invalid")) return -1; - i = osd_meson_dev.osd_count - 1; + i = osd_meson_dev.viu2_index; switch (cmd) { case VOUT_EVENT_MODE_CHANGE: fb_dev = gp_fbdev_list[i]; @@ -3313,11 +3421,19 @@ static void mem_free_work(struct work_struct *work) osd_page[0], fb_memsize[0] >> PAGE_SHIFT); #else +#ifdef CONFIG_ARM64 long r = -EINVAL; +#elif defined(CONFIG_ARM) && defined(CONFIG_HIGHMEM) + unsigned long r; +#endif unsigned long start_addr; unsigned long end_addr; +#ifdef CONFIG_ARM64 if (fb_rmem.base && fb_map_flag) { +#elif defined(CONFIG_ARM) && defined(CONFIG_HIGHMEM) + if (fb_rmem.base) { +#endif if (fb_rmem.size >= (fb_memsize[0] + fb_memsize[1] + fb_memsize[2])) { /* logo memory before fb0/fb1 memory, free it*/ @@ -3330,8 +3446,16 @@ static void mem_free_work(struct work_struct *work) } osd_log_info("%s, free memory: addr:%lx\n", __func__, start_addr); +#ifdef CONFIG_ARM64 r = free_reserved_area(__va(start_addr), __va(end_addr), 0, "fb-memory"); +#elif defined(CONFIG_ARM) && defined(CONFIG_HIGHMEM) + for (r = start_addr; r < end_addr; ) { + free_highmem_page(phys_to_page(r)); + r += PAGE_SIZE; + } +#endif + } #endif } @@ -3473,6 +3597,21 @@ static struct osd_device_data_s osd_g12b = { .has_viu2 = 1, }; +static struct osd_device_data_s osd_tl1 = { + .cpu_id = __MESON_CPU_MAJOR_ID_TL1, + .osd_ver = OSD_HIGH_ONE, + .afbc_type = MALI_AFBC, + .osd_count = 3, + .has_deband = 1, + .has_lut = 1, + .has_rdma = 1, + .has_dolby_vision = 0, + .osd_fifo_len = 64, /* fifo len 64*8 = 512 */ + .vpp_fifo_len = 0xfff,/* 2048 */ + .dummy_data = 0x00808000, + .has_viu2 = 1, +}; + static const struct of_device_id meson_fb_dt_match[] = { { .compatible = "amlogic, meson-gxbb", @@ -3515,6 +3654,10 @@ static const struct of_device_id meson_fb_dt_match[] = { .compatible = "amlogic, meson-g12b", .data = &osd_g12b, }, + { + .compatible = "amlogic, meson-tl1", + .data = &osd_tl1, + }, {}, }; @@ -3589,6 +3732,12 @@ static int osd_probe(struct platform_device *pdev) goto failed1; } } + osd_meson_dev.viu1_osd_count = osd_meson_dev.osd_count; + if (osd_meson_dev.has_viu2) { + /* set viu1 osd count */ + osd_meson_dev.viu1_osd_count--; + osd_meson_dev.viu2_index = osd_meson_dev.viu1_osd_count; + } ret = osd_io_remap(osd_meson_dev.osd_ver == OSD_SIMPLE); if (!ret) { @@ -3784,12 +3933,12 @@ static int osd_probe(struct platform_device *pdev) /* register frame buffer */ register_framebuffer(fbi); /* create device attribute files */ - if (index <= DEV_OSD2) { + if (index <= (osd_meson_dev.viu1_osd_count - 1)) { for (i = 0; i < ARRAY_SIZE(osd_attrs); i++) ret = device_create_file( fbi->dev, &osd_attrs[i]); - } else if ((osd_meson_dev.osd_ver == OSD_HIGH_ONE) && - (index == DEV_OSD3)) { + } else if ((osd_meson_dev.has_viu2) && + (index == osd_meson_dev.viu2_index)) { for (i = 0; i < ARRAY_SIZE(osd_attrs_viu2); i++) ret = device_create_file(fbi->dev, &osd_attrs_viu2[i]); } @@ -3803,12 +3952,12 @@ static int osd_probe(struct platform_device *pdev) /* init osd reverse */ if (osd_info.index == DEV_ALL) { - for (i = 0; i < osd_meson_dev.osd_count - 1; i++) + for (i = 0; i < osd_meson_dev.viu1_osd_count; i++) osd_set_reverse_hw(i, osd_info.osd_reverse, 1); osd_set_reverse_hw(i, osd_info.osd_reverse, 0); - } else if (osd_info.index <= DEV_OSD2) + } else if (osd_info.index <= osd_meson_dev.viu1_osd_count - 1) osd_set_reverse_hw(osd_info.index, osd_info.osd_reverse, 1); - else if (osd_info.index == DEV_OSD3) + else if (osd_info.index == osd_meson_dev.viu2_index) osd_set_reverse_hw(osd_info.index, osd_info.osd_reverse, 0); /* register vout client */ vout_register_client(&osd_notifier_nb); @@ -3853,12 +4002,12 @@ static int osd_remove(struct platform_device *pdev) struct osd_fb_dev_s *fbdev = gp_fbdev_list[i]; fbi = fbdev->fb_info; - if (i <= DEV_OSD2) { + if (i <= osd_meson_dev.viu1_osd_count - 1) { for (j = 0; j < ARRAY_SIZE(osd_attrs); j++) device_remove_file( fbi->dev, &osd_attrs[j]); - } else if ((osd_meson_dev.osd_ver == OSD_HIGH_ONE) && - (i == DEV_OSD3)) { + } else if ((osd_meson_dev.has_viu2) && + (i == osd_meson_dev.viu2_index)) { for (j = 0; j < ARRAY_SIZE(osd_attrs_viu2); j++) device_remove_file( fbi->dev, &osd_attrs_viu2[j]); diff --git a/drivers/amlogic/media/osd/osd_hw.c b/drivers/amlogic/media/osd/osd_hw.c index cfc69d6b0fcc..c3e4a1c5385b 100644 --- a/drivers/amlogic/media/osd/osd_hw.c +++ b/drivers/amlogic/media/osd/osd_hw.c @@ -53,6 +53,10 @@ #ifdef CONFIG_AMLOGIC_MEDIA_VIDEO #include #endif +#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION +#include +#endif + /* Local Headers */ #include "osd_canvas.h" #include "osd_prot.h" @@ -78,6 +82,7 @@ #define OSD_TYPE_BOT_FIELD 1 #define OSD_DISP_DEBUG 1 +#define ENCP_LINE_VSYNC 15 #define ENCP_LINE 16 #define OSD_OLD_HWC (0x01 << 0) #define OSD_OTHER_NEW_HWC (0x01 << 1) @@ -88,7 +93,8 @@ #define osd_tprintk(...) -#define OSD_CALC 10 +#define OSD_CALC 14 +#define FREE_SCALE_MAX_WIDTH 1920 struct hw_para_s osd_hw; static DEFINE_MUTEX(osd_mutex); static DECLARE_WAIT_QUEUE_HEAD(osd_vsync_wq); @@ -1046,6 +1052,7 @@ static int sync_render_layers_fence(u32 index, u32 yres, in_fence_fd = request->in_fen_fd; mutex_lock(&post_fence_list_lock); fence_map = &map_layers; + fence_map->cmd = LAYER_SYNC; fence_map->layer_map[index].fb_index = index; /* layer_map[index].enable will update if have blank ioctl */ fence_map->layer_map[index].enable = 1; @@ -1159,6 +1166,7 @@ int osd_sync_do_hwc(struct do_hwc_cmd_s *hwc_cmd) hwc_cmd->disp_info.position_w; fence_map->disp_info.position_h = hwc_cmd->disp_info.position_h; + fence_map->hdr_mode = hwc_cmd->hdr_mode; /* other info set via add_sync and blank ioctl */ list_add_tail(&fence_map->list, &post_fence_list); /* after do_hwc, clear osd_hw.out_fence_fd */ @@ -1166,7 +1174,15 @@ int osd_sync_do_hwc(struct do_hwc_cmd_s *hwc_cmd) osd_hw.out_fence_fd = -1; mutex_unlock(&post_fence_list_lock); kthread_queue_work(&buffer_toggle_worker, &buffer_toggle_work); + if (get_logo_loaded()) { + int logo_index; + logo_index = osd_get_logo_index(); + if (logo_index < 0) { + osd_log_info("set logo loaded\n"); + set_logo_loaded(); + } + } osd_log_dbg("osd_sync_do_hwc :out_fence_fd=%d\n", out_fence_fd); return out_fence_fd; @@ -1243,17 +1259,18 @@ void osd_set_enable_hw(u32 index, u32 enable) if (osd_hw.hwc_enable) { if (index > OSD_MAX) return; - if (osd_hw.osd_meson_dev.osd_ver < OSD_HIGH_ONE) + if ((osd_hw.osd_meson_dev.osd_ver < OSD_HIGH_ONE) + && (index == OSD2)) osd_enable_hw(index, enable); else { - /* Todo: */ #ifdef CONFIG_AMLOGIC_MEDIA_FB_OSD_SYNC_FENCE - mutex_lock(&post_fence_list_lock); - map_layers.layer_map[index].fb_index = index; - map_layers.layer_map[index].enable = enable; - mutex_unlock(&post_fence_list_lock); - osd_log_dbg("osd_set_enable_hw: osd%d,enable=%d\n", - index, enable); + mutex_lock(&post_fence_list_lock); + map_layers.layer_map[index].fb_index = index; + map_layers.layer_map[index].enable = enable; + map_layers.cmd = BLANK_CMD; + mutex_unlock(&post_fence_list_lock); + osd_log_dbg("osd_set_enable_hw: osd%d,enable=%d\n", + index, enable); #endif } } else @@ -1554,7 +1571,7 @@ void osd_update_scan_mode(void) } else { int i; - for (i = 0; i < osd_hw.osd_meson_dev.osd_count; i++) { + for (i = 0; i < osd_hw.osd_meson_dev.viu1_osd_count; i++) { if (osd_hw.free_scale_enable[i]) osd_hw.scan_mode[i] = SCAN_MODE_PROGRESSIVE; if (osd_hw.osd_afbcd[i].enable) @@ -1631,9 +1648,10 @@ static u32 osd_get_hw_reset_flag(void) } #endif break; -#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_VECM case __MESON_CPU_MAJOR_ID_GXL: case __MESON_CPU_MAJOR_ID_TXL: +#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_VECM + if (((hdr_osd_reg.viu_osd1_matrix_ctrl & 0x00000001) != 0x0) || ((hdr_osd_reg.viu_osd1_eotf_ctl & 0x80000000) @@ -1646,10 +1664,11 @@ static u32 osd_get_hw_reset_flag(void) hw_reset_flag |= HW_RESET_OSD1_REGS; osd_hdr_on = false; } - break; #endif + break; case __MESON_CPU_MAJOR_ID_G12A: case __MESON_CPU_MAJOR_ID_G12B: + case __MESON_CPU_MAJOR_ID_TL1: { int i, afbc_enable = 0; @@ -1893,7 +1912,7 @@ s64 osd_wait_vsync_event(void) return timestamp; } -static int is_interlaced(struct vinfo_s *vinfo) +int is_interlaced(struct vinfo_s *vinfo) { if (vinfo->mode == VMODE_CVBS) return 1; @@ -3139,11 +3158,6 @@ void osd_set_background_size(struct display_flip_info_s *disp_info) { memcpy(&osd_hw.disp_info, disp_info, sizeof(struct display_flip_info_s)); - #if 0 - if (osd_hw.hwc_enable && - (osd_hw.osd_display_debug == OSD_DISP_DEBUG)) - osd_setting_blend(); - #endif } void osd_get_hdr_used(u32 *val) @@ -4086,10 +4100,10 @@ static void osd_pan_display_update_info(struct layer_fence_map_s *layer_map) osd_hw.premult_en[index] = 0; break; } - osd_hw.src_data[index].x = layer_map->dst_x; - osd_hw.src_data[index].y = layer_map->dst_y; - osd_hw.src_data[index].w = layer_map->dst_w; - osd_hw.src_data[index].h = layer_map->dst_h; + osd_hw.src_data[index].x = 0; + osd_hw.src_data[index].y = 0; + osd_hw.src_data[index].w = 64; + osd_hw.src_data[index].h = 64; osd_hw.dst_data[index].x = layer_map->dst_x; osd_hw.dst_data[index].y = layer_map->dst_y; osd_hw.dst_data[index].w = layer_map->dst_w; @@ -4211,8 +4225,16 @@ static void osd_pan_display_update_info(struct layer_fence_map_s *layer_map) layer_map->dst_x + layer_map->dst_w - 1; osd_hw.free_dst_data[index].y_end = layer_map->dst_y + layer_map->dst_h - 1; + if (osd_hw.field_out_en) { + osd_hw.free_dst_data[index].y_start /= 2; + osd_hw.free_dst_data[index].y_end /= 2; + } } } + #if 0 + osd_hw.dst_data[index].x -= osd_hw.disp_info.position_x; + osd_hw.dst_data[index].y -= osd_hw.disp_info.position_y; + #endif } static void osd_pan_display_layers_fence( @@ -4225,35 +4247,20 @@ static void osd_pan_display_layers_fence( struct layer_fence_map_s *layer_map = NULL; struct vinfo_s *vinfo; + if (osd_hw.osd_meson_dev.osd_ver <= OSD_NORMAL) + osd_count = 1; vinfo = get_current_vinfo(); if (vinfo && (strcmp(vinfo->name, "invalid") && strcmp(vinfo->name, "null"))) { osd_hw.vinfo_width = vinfo->width; osd_hw.vinfo_height = vinfo->field_height; - osd_hw.b_interlaced = is_interlaced(vinfo); - if ((vinfo->width == fence_map->disp_info.fullscreen_w) && - (vinfo->field_height == - fence_map->disp_info.fullscreen_h)) { - osd_set_background_size(&(fence_map->disp_info)); - } else { - osd_hw.disp_info.position_x *= - osd_hw.vinfo_width / - osd_hw.disp_info.fullscreen_w; - osd_hw.disp_info.position_w *= - osd_hw.vinfo_width / - osd_hw.disp_info.fullscreen_w; - osd_hw.disp_info.position_y *= - osd_hw.vinfo_height / - osd_hw.disp_info.fullscreen_h; - osd_hw.disp_info.position_h *= - osd_hw.vinfo_height / - osd_hw.disp_info.fullscreen_h; - - } } + osd_set_background_size(&(fence_map->disp_info)); + if (osd_hw.osd_fps_start) osd_hw.osd_fps++; clear_backup_info(); + osd_hw.hdr_used = fence_map->hdr_mode; for (i = 0; i < osd_count; i++) { layer_map = &fence_map->layer_map[i]; index = layer_map->fb_index; @@ -4264,7 +4271,8 @@ static void osd_pan_display_layers_fence( continue; } /* wait in fence */ - if (timeline_created && layer_map->enable) { + if (timeline_created && layer_map->enable + && (fence_map->cmd == LAYER_SYNC)) { ret = osd_wait_buf_ready_combine(layer_map); if (ret < 0) osd_log_dbg("fence wait ret %d\n", ret); @@ -4402,6 +4410,7 @@ static void osd_update_disp_freescale_enable(u32 index) int vf_bank_len = 4; struct hw_osd_reg_s *osd_reg = &hw_osd_reg_array[index]; u32 data32 = 0x0; + u32 shift_workaround = 0; if (osd_hw.osd_meson_dev.osd_ver != OSD_HIGH_ONE) osd_reg = &hw_osd_reg_array[0]; @@ -4411,6 +4420,13 @@ static void osd_update_disp_freescale_enable(u32 index) else vf_bank_len = 4; + if (osd_hw.hwc_enable && (index == OSD1) + && ((osd_hw.osd_meson_dev.cpu_id == + __MESON_CPU_MAJOR_ID_G12A) || + (osd_hw.osd_meson_dev.cpu_id == + __MESON_CPU_MAJOR_ID_G12B))) + shift_workaround = 1; + #ifndef NEW_PPS_PHASE if (osd_hw.bot_type == 1) { vsc_bot_rcv_num = 4; @@ -4460,7 +4476,10 @@ static void osd_update_disp_freescale_enable(u32 index) hf_phase_step = (src_w << 18) / dst_w; hf_phase_step = (hf_phase_step << 6); - vf_phase_step = (src_h << 20) / dst_h; + if (shift_workaround) + vf_phase_step = ((src_h - 1) << 20) / dst_h; + else + vf_phase_step = (src_h << 20) / dst_h; #ifdef NEW_PPS_PHASE if (osd_hw.field_out_en) { @@ -4504,6 +4523,13 @@ static void osd_update_disp_freescale_enable(u32 index) vf_phase_step = (vf_phase_step << 4); /* config osd scaler in/out hv size */ data32 = 0x0; + if (shift_workaround) { + vsc_ini_rcv_num++; + if (osd_hw.field_out_en) + vsc_bot_rcv_num++; + } + + if (osd_hw.free_scale_enable[index]) { data32 = (((src_h - 1) & 0x1fff) | ((src_w - 1) & 0x1fff) << 16); @@ -5226,14 +5252,13 @@ static int get_available_layers(void) int i; int available_layer = 0; - for (i = 0 ; i < osd_hw.osd_meson_dev.osd_count - 1; i++) { + for (i = 0 ; i < osd_hw.osd_meson_dev.viu1_osd_count; i++) { if (osd_hw.enable[i]) available_layer++; } return available_layer; } - static u32 blend_din_to_osd( u32 blend_din_index, struct hw_osd_blending_s *blending) { @@ -5329,8 +5354,10 @@ static void exchange_din0_din2(struct hw_osd_blending_s *blending) blending->din_reoder_sel &= ~0x0f0f; blending->din_reoder_sel |= temp1 << 8; blending->din_reoder_sel |= temp2 >> 8; - blending->osd_to_bdin_table[2] = OSD1; - blending->osd_to_bdin_table[0] = OSD2; + temp1 = blending->osd_to_bdin_table[0]; + temp2 = blending->osd_to_bdin_table[2]; + blending->osd_to_bdin_table[2] = temp1; + blending->osd_to_bdin_table[0] = temp2; osd_log_dbg("din_reoder_sel%x\n", blending->din_reoder_sel); } @@ -5345,8 +5372,10 @@ static void exchange_din2_din3(struct hw_osd_blending_s *blending) blending->din_reoder_sel &= ~0xff00; blending->din_reoder_sel |= temp1 << 4; blending->din_reoder_sel |= temp2 >> 4; - blending->osd_to_bdin_table[3] = OSD2; - blending->osd_to_bdin_table[2] = OSD3; + temp1 = blending->osd_to_bdin_table[2]; + temp2 = blending->osd_to_bdin_table[3]; + blending->osd_to_bdin_table[3] = temp1; + blending->osd_to_bdin_table[2] = temp2; osd_log_dbg("din_reoder_sel%x\n", blending->din_reoder_sel); } @@ -5360,9 +5389,8 @@ static void exchange_vpp_order(struct hw_osd_blending_s *blending) static void generate_blend_din_table(struct hw_osd_blending_s *blending) { int i = 0; - int osd_count = osd_hw.osd_meson_dev.osd_count - 1; int temp1 = 0, temp2 = 0; - u32 max_order = 0, min_order = 0; + int osd_count = osd_hw.osd_meson_dev.viu1_osd_count; /* reorder[i] = osd[i]'s display layer */ for (i = 0; i < OSD_BLEND_LAYERS; i++) @@ -5458,52 +5486,41 @@ static void generate_blend_din_table(struct hw_osd_blending_s *blending) blending->din_reoder_sel |= 1 << 0; /* blend_din1 -- osd1 */ blending->osd_to_bdin_table[0] = OSD1; - /* blend_din4 */ - blending->din_reoder_sel |= (OSD3 + 1) << 12; - /* blend_din4 -- osd3 */ - blending->osd_to_bdin_table[3] = OSD3; /* blend_din3 */ blending->din_reoder_sel |= (OSD2 + 1) << 8; /* blend_din3 -- osd2 */ blending->osd_to_bdin_table[2] = OSD2; - max_order = get_max_order(blending->reorder[OSD2], - blending->reorder[OSD3]); - min_order = get_min_order(blending->reorder[OSD2], - blending->reorder[OSD3]); - if (min_order > blending->reorder[OSD1]) { - /* osd1 is top layer */ - osd_log_dbg("osd1 is top.\n"); - if (blending->reorder[OSD3] > - blending->reorder[OSD2]) { - /* din3 is bottom, need exchange - * din0 and din2 and exchange vpp - */ - osd_log_dbg("osd3 is bottom\n"); - exchange_din0_din2(blending); - exchange_vpp_order(blending); - } else { - osd_log_dbg("osd3 is middle\n"); - exchange_din2_din3(blending); - exchange_din0_din2(blending); - exchange_vpp_order(blending); - } - } else if ((min_order < blending->reorder[OSD1]) && - (max_order < blending->reorder[OSD1])) { - /* osd1 is bottom , min is din3, max is din2 */ - if (min_order == blending->reorder[OSD2]) { - osd_log_dbg("osd2 is top\n"); - /* need exchange din2 and din3*/ - exchange_din2_din3(blending); - } else if (min_order == blending->reorder[OSD3]) - osd_log_dbg("osd3 is top, do not need exchange\n"); - } else if ((min_order < blending->reorder[OSD1]) && - (max_order > blending->reorder[OSD1])) { - /* osd1 is middle */ - osd_log_dbg("osd1 is middle\n"); - if (min_order == blending->reorder[OSD2]) - exchange_vpp_order(blending); - else if (min_order == blending->reorder[OSD3]) - exchange_din0_din2(blending); + /* blend_din4 */ + blending->din_reoder_sel |= (OSD3 + 1) << 12; + /* blend_din4 -- osd3 */ + blending->osd_to_bdin_table[3] = OSD3; + if ((blending->reorder[OSD1] == LAYER_3) + && (blending->reorder[OSD2] == LAYER_2) + && (blending->reorder[OSD3] == LAYER_1)) { + osd_log_dbg2("use default order\n"); + } else if ((blending->reorder[OSD1] == LAYER_2) + && (blending->reorder[OSD2] == LAYER_3) + && (blending->reorder[OSD3] == LAYER_1)) { + exchange_din0_din2(blending); + } else if ((blending->reorder[OSD1] == LAYER_2) + && (blending->reorder[OSD2] == LAYER_1) + && (blending->reorder[OSD3] == LAYER_3)) { + exchange_vpp_order(blending); + } else if ((blending->reorder[OSD1] == LAYER_1) + && (blending->reorder[OSD2] == LAYER_2) + && (blending->reorder[OSD3] == LAYER_3)) { + exchange_din0_din2(blending); + exchange_vpp_order(blending); + } else if ((blending->reorder[OSD1] == LAYER_3) + && (blending->reorder[OSD2] == LAYER_1) + && (blending->reorder[OSD3] == LAYER_2)) { + exchange_din2_din3(blending); + } else if ((blending->reorder[OSD1] == LAYER_1) + && (blending->reorder[OSD2] == LAYER_3) + && (blending->reorder[OSD3] == LAYER_2)) { + exchange_din2_din3(blending); + exchange_din0_din2(blending); + exchange_vpp_order(blending); } } else if (blending->osd_blend_mode == OSD_BLEND_ABC) { u32 osd_index = 0; @@ -5814,7 +5831,7 @@ static void set_blend_order(struct hw_osd_blending_s *blending) { u32 org_order[HW_OSD_COUNT]; int i = 0, j = 0; - u32 osd_count = osd_hw.osd_meson_dev.osd_count - 1; + u32 osd_count = osd_hw.osd_meson_dev.viu1_osd_count; if (!blending) return; @@ -6033,15 +6050,19 @@ static void osd_setting_blend1(struct hw_osd_blending_s *blending) u32 blend_hsize, blend_vsize; u32 bld_osd_h_start = 0, bld_osd_h_end = 0; u32 bld_osd_v_start = 0, bld_osd_v_end = 0; - u32 workaround_line = 1; + u32 workaround_line = 0; /* for g12a blend shift issue */ if (!blending) return; if (osd_hw.hdr_used) - workaround_line = osd_hw.workaround_hdr; - else - workaround_line = osd_hw.workaround_not_hdr; + workaround_line = 1; + else { + if (blending->layer_cnt == 2) + workaround_line = 0; + else + workaround_line = 1; + } layer_blend = &(blending->layer_blend); blend_reg = &(blending->blend_reg); #ifdef OSD_BLEND_SHIFT_WORKAROUND @@ -6070,10 +6091,6 @@ static void osd_setting_blend1(struct hw_osd_blending_s *blending) if (index >= OSD_MAX) return; /* calculate osd blend din scope */ - layer_blend->input1_data.y += - workaround_line; - layer_blend->input1_data.h -= - workaround_line; bld_osd_h_start = layer_blend->input1_data.x; bld_osd_h_end = @@ -6099,10 +6116,6 @@ static void osd_setting_blend1(struct hw_osd_blending_s *blending) index = blend_din_to_osd(layer_blend->input2, blending); if (index >= OSD_MAX) return; - layer_blend->input2_data.y += - workaround_line; - layer_blend->input2_data.h -= - workaround_line; /* calculate osd blend din scope */ bld_osd_h_start = layer_blend->input2_data.x; @@ -6127,14 +6140,16 @@ static void osd_setting_blend1(struct hw_osd_blending_s *blending) if (blend_reg->din3_osd_sel || layer_blend->input1 == BLEND_NO_DIN) { /* blend din3 bypass,output == input */ #ifdef OSD_BLEND_SHIFT_WORKAROUND - if (layer_blend->input2 == BLEND_NO_DIN) + if (layer_blend->input2 == BLEND_NO_DIN) { memcpy(&layer_blend->output_data, &layer_blend->input1_data, sizeof(struct dispdata_s)); - else + } else { memcpy(&layer_blend->output_data, &layer_blend->input2_data, sizeof(struct dispdata_s)); + } + layer_blend->output_data.h += workaround_line; #else layer_blend->output_data.x = 0; layer_blend->output_data.y = 0; @@ -6157,8 +6172,6 @@ static void osd_setting_blend1(struct hw_osd_blending_s *blending) layer_blend->output_data.y, layer_blend->output_data.w, layer_blend->output_data.h); - osd_log_dbg2("osd_blend_blend1_size=%x", - blend_reg->osd_blend_blend1_size); } static void osd_setting_blend2(struct hw_osd_blending_s *blending) @@ -6334,7 +6347,8 @@ static void osd_set_freescale(u32 index, struct layer_blend_s *layer_blend; struct layer_blend_reg_s *blend_reg; u32 width, height; - u32 src_width, src_height; + u32 src_height; + u32 workaround_line = 1; layer_blend = &(blending->layer_blend); blend_reg = &(blending->blend_reg); @@ -6359,75 +6373,14 @@ static void osd_set_freescale(u32 index, layer_blend->output_data.y + layer_blend->output_data.h - 1; - if ((blending->osd_blend_mode == OSD_BLEND_AC) || - (blending->osd_blend_mode == OSD_BLEND_ABC)) { - osd_hw.free_dst_data[index].x_start = - ((osd_hw.free_src_data[index].x_start * - blending->screen1_ratio_w >> OSD_CALC) * - blending->screen2_ratio_w >> OSD_CALC) * - osd_hw.dst_data[index].w / - osd_hw.src_data[index].w; - osd_hw.free_dst_data[index].y_start = - ((osd_hw.free_src_data[index].y_start * - blending->screen1_ratio_h >> OSD_CALC) * - blending->screen2_ratio_h >> OSD_CALC) * - osd_hw.dst_data[index].h / - osd_hw.src_data[index].h; - src_width = osd_hw.free_src_data[index].x_end - - osd_hw.free_src_data[index].x_start + 1; - src_height = osd_hw.free_src_data[index].y_end - - osd_hw.free_src_data[index].y_start + 1; - width = ((src_width* - blending->screen1_ratio_w >> OSD_CALC) * - blending->screen2_ratio_w >> OSD_CALC) * - osd_hw.dst_data[index].w / - osd_hw.src_data[index].w; - height = ((src_height * - blending->screen1_ratio_h >> OSD_CALC) * - blending->screen2_ratio_h >> OSD_CALC) * - osd_hw.dst_data[index].h / - osd_hw.src_data[index].h; - } -#ifdef OSD_BLEND_SHIFT_WORKAROUND - else if (blending->osd_blend_mode == OSD_BLEND_AB_C) { - osd_hw.free_dst_data[index].x_start = - (osd_hw.free_src_data[index].x_start * - blending->screen1_ratio_w >> OSD_CALC) * - blending->screen2_ratio_w >> OSD_CALC; - osd_hw.free_dst_data[index].y_start = - (osd_hw.free_src_data[index].y_start * - blending->screen1_ratio_h >> OSD_CALC) * - blending->screen2_ratio_h >> OSD_CALC; - width = (layer_blend->output_data.w * - blending->screen1_ratio_w >> OSD_CALC) * - blending->screen2_ratio_w >> OSD_CALC; - height = (layer_blend->output_data.h * - blending->screen1_ratio_h >> OSD_CALC) * - blending->screen2_ratio_h >> OSD_CALC; - } -#endif - else { - osd_hw.free_dst_data[index].x_start = - (osd_hw.dst_data[index].x * - blending->screen1_ratio_w >> OSD_CALC) * - blending->screen2_ratio_w >> OSD_CALC; - osd_hw.free_dst_data[index].y_start = - (osd_hw.dst_data[index].y * - blending->screen1_ratio_h >> OSD_CALC) * - blending->screen2_ratio_h >> OSD_CALC; - width = (osd_hw.dst_data[index].w * - blending->screen1_ratio_w >> OSD_CALC) * - blending->screen2_ratio_w >> OSD_CALC; - height = (osd_hw.dst_data[index].h * - blending->screen1_ratio_h >> OSD_CALC) * - blending->screen2_ratio_h >> OSD_CALC; - } - osd_hw.free_dst_data[index].x_end = - osd_hw.free_dst_data[index].x_start + - width - 1; - osd_hw.free_dst_data[index].y_end = - osd_hw.free_dst_data[index].y_start + - height - 1; + osd_hw.free_dst_data[index].x_start = 0; + osd_hw.free_dst_data[index].y_start = 0; + width = layer_blend->output_data.w + * blending->screen_ratio_w >> OSD_CALC; + height = (layer_blend->output_data.h - workaround_line) + * blending->screen_ratio_h >> OSD_CALC; + if (osd_hw.field_out_en) + height = height >> 1; } else { osd_hw.free_src_data[index].x_start = osd_hw.src_data[index].x; @@ -6442,74 +6395,77 @@ static void osd_set_freescale(u32 index, if ((blending->osd_blend_mode == OSD_BLEND_AC) || (blending->osd_blend_mode == OSD_BLEND_ABC)) { - if (blending->pic_w_ratio > (1 << OSD_CALC)) - osd_log_err("!!!osd not support!!!\n"); - if (blending->pic_w_ratio > (1 << OSD_CALC)) - osd_log_err("!!!osd not support!!!\n"); + /* combine mode, need uniformization */ osd_hw.free_dst_data[index].x_start = - osd_hw.dst_data[index].x * - blending->pic_w_ratio >> OSD_CALC; + (osd_hw.dst_data[index].x << OSD_CALC) / + blending->screen_ratio_w; osd_hw.free_dst_data[index].y_start = - osd_hw.dst_data[index].y * - blending->pic_h_ratio >> OSD_CALC; - width = osd_hw.dst_data[index].w * - blending->pic_w_ratio >> OSD_CALC; - height = osd_hw.dst_data[index].h * - blending->pic_h_ratio >> OSD_CALC; - osd_hw.free_dst_data[index].x_end = - osd_hw.free_dst_data[index].x_start + - width - 1; - osd_hw.free_dst_data[index].y_end = - osd_hw.free_dst_data[index].y_start + - height - 1; - } -#ifdef OSD_BLEND_SHIFT_WORKAROUND - else if ((blending->osd_blend_mode == OSD_BLEND_AB_C) - && (index == blend_din_to_osd(BLEND_DIN3, blending))) { + (osd_hw.dst_data[index].y << OSD_CALC) / + blending->screen_ratio_h; + width = (osd_hw.dst_data[index].w << OSD_CALC) / + blending->screen_ratio_w; + height = (osd_hw.dst_data[index].h << OSD_CALC) / + blending->screen_ratio_h; + if (width > FREE_SCALE_MAX_WIDTH) + width = FREE_SCALE_MAX_WIDTH; + } else if (blending->osd_blend_mode == OSD_BLEND_AB_C) { + osd_log_dbg("blending->blend_din=%d\n", + blending->blend_din); + if (blending->blend_din != BLEND_DIN4) { + /* combine mode, need uniformization */ + osd_hw.free_dst_data[index].x_start = + (osd_hw.dst_data[index].x << OSD_CALC) / + blending->screen_ratio_w; + osd_hw.free_dst_data[index].y_start = + (osd_hw.dst_data[index].y << OSD_CALC) / + blending->screen_ratio_h; + width = (osd_hw.dst_data[index].w + << OSD_CALC) / + blending->screen_ratio_w; + height = (osd_hw.dst_data[index].h + << OSD_CALC) / + blending->screen_ratio_h; + } else { + /* direct used dst as freescale dst */ + osd_hw.free_dst_data[index].x_start = + osd_hw.dst_data[index].x; + osd_hw.free_dst_data[index].y_start = + osd_hw.dst_data[index].y; + width = osd_hw.dst_data[index].w; + height = osd_hw.dst_data[index].h; + /* interleaced case */ + if (osd_hw.field_out_en) { + height = height >> 1; + osd_hw.free_dst_data[index].y_start + >>= 1; + } + } + } else { + /* direct used dst as freescale dst */ osd_hw.free_dst_data[index].x_start = osd_hw.dst_data[index].x; osd_hw.free_dst_data[index].y_start = osd_hw.dst_data[index].y; width = osd_hw.dst_data[index].w; height = osd_hw.dst_data[index].h; - osd_hw.free_dst_data[index].x_end = - osd_hw.free_dst_data[index].x_start + - width - 1; - osd_hw.free_dst_data[index].y_end = - osd_hw.free_dst_data[index].y_start + - height - 1; - } -#endif - else { - osd_hw.free_dst_data[index].x_start = - (osd_hw.dst_data[index].x * - blending->screen1_ratio_w >> OSD_CALC) * - blending->screen2_ratio_w >> OSD_CALC; - osd_hw.free_dst_data[index].y_start = - (osd_hw.dst_data[index].y * - blending->screen1_ratio_h >> OSD_CALC) * - blending->screen2_ratio_h >> OSD_CALC; - width = (osd_hw.dst_data[index].w * - blending->screen1_ratio_w >> OSD_CALC) * - blending->screen2_ratio_w >> OSD_CALC; - height = (osd_hw.dst_data[index].h * - blending->screen1_ratio_h >> OSD_CALC) * - blending->screen2_ratio_h >> OSD_CALC; - osd_hw.free_dst_data[index].x_end = - osd_hw.free_dst_data[index].x_start + - width - 1; - osd_hw.free_dst_data[index].y_end = - osd_hw.free_dst_data[index].y_start + - height - 1; + if (osd_hw.field_out_en) { + height = height >> 1; + osd_hw.free_dst_data[index].y_start >>= 1; + } } } + osd_hw.free_dst_data[index].x_end = + osd_hw.free_dst_data[index].x_start + + width - 1; + osd_hw.free_dst_data[index].y_end = + osd_hw.free_dst_data[index].y_start + + height - 1; + src_height = osd_hw.free_src_data[index].x_end - osd_hw.free_src_data[index].x_start + 1; if ((osd_hw.osd_meson_dev.cpu_id == __MESON_CPU_MAJOR_ID_G12A) && - (height != src_height) && - (osd_hw.disp_info.position_h == - osd_hw.disp_info.fullscreen_h)) { + (height != src_height)) { osd_hw.osd_meson_dev.dummy_data = 0x000000; osd_set_dummy_data(index, 0); } else { @@ -6533,59 +6489,22 @@ static void osd_set_freescale(u32 index, static void osd_setting_blend0_input(u32 index, struct hw_osd_blending_s *blending) { - u32 background_w = 0, background_h = 0; struct layer_blend_s *layer_blend; u32 workaround_line = 1; /* for g12a blend shift issue */ - if (osd_hw.hdr_used) - workaround_line = osd_hw.workaround_hdr; - else - workaround_line = osd_hw.workaround_not_hdr; layer_blend = &(blending->layer_blend); if (index == OSD1) { - blending->pic_w_ratio = - (osd_hw.src_data[index].w << OSD_CALC) / - osd_hw.dst_data[index].w; - blending->pic_h_ratio = - (osd_hw.src_data[index].h << OSD_CALC) / - osd_hw.dst_data[index].h; - if ((blending->osd_blend_mode == OSD_BLEND_AC) - || (blending->osd_blend_mode == OSD_BLEND_ABC) -#ifdef OSD_BLEND_SHIFT_WORKAROUND - || (blending->osd_blend_mode == OSD_BLEND_AB_C) -#endif - ) { + layer_blend->input1_data.x = - osd_hw.dst_data[index].x * - blending->pic_w_ratio >> OSD_CALC; + blending->dst_data.x; layer_blend->input1_data.y = - (osd_hw.dst_data[index].y * - blending->pic_h_ratio >> OSD_CALC) + blending->dst_data.y + workaround_line; layer_blend->input1_data.w = - osd_hw.src_data[index].w; + blending->dst_data.w; layer_blend->input1_data.h = - osd_hw.src_data[index].h - - workaround_line; - } else { -#ifdef OSD_BLEND_SHIFT_WORKAROUND - layer_blend->input1_data.x = 0; - layer_blend->input1_data.y = workaround_line; -#else - layer_blend->input1_data.x = osd_hw.src_data[index].x; - layer_blend->input1_data.y = osd_hw.src_data[index].y - + workaround_line; -#endif - layer_blend->input1_data.w = osd_hw.src_data[index].w; - layer_blend->input1_data.h = osd_hw.src_data[index].h - - workaround_line; - } - background_w = (osd_hw.disp_info.position_w * - blending->pic_w_ratio) >> OSD_CALC; - background_h = (osd_hw.disp_info.position_h * - blending->pic_h_ratio >> OSD_CALC) - - workaround_line; + blending->dst_data.h; } else { layer_blend->input1_data.x = osd_hw.free_dst_data[index].x_start; @@ -6597,22 +6516,66 @@ static void osd_setting_blend0_input(u32 index, osd_hw.free_dst_data[index].x_start + 1; layer_blend->input1_data.h = osd_hw.free_dst_data[index].y_end - - osd_hw.free_dst_data[index].y_start + - 1 - workaround_line; - background_w = layer_blend->input1_data.w; - background_h = layer_blend->input1_data.h; + osd_hw.free_dst_data[index].y_start + 1; } - layer_blend->background_w = background_w; - layer_blend->background_h = background_h; - osd_log_dbg2("index=%d,src_data: x=%d,y=%d,w=%d,h=%d\n", - index, osd_hw.src_data[index].x, osd_hw.src_data[index].y, - osd_hw.src_data[index].w, osd_hw.src_data[index].h); - osd_log_dbg2("dst_data: x=%d,y=%d,w=%d,h=%d\n", - osd_hw.dst_data[index].x, osd_hw.dst_data[index].y, - osd_hw.dst_data[index].w, osd_hw.dst_data[index].h); - osd_log_dbg2("bk size:%d, %d\n", - layer_blend->background_w, - layer_blend->background_h); + osd_log_dbg2("blend0_input:input0_data[osd%d]:%d,%d,%d,%d\n", + index, + layer_blend->input1_data.x, + layer_blend->input1_data.y, + layer_blend->input1_data.w, + layer_blend->input1_data.h); +} + +static void osd_setting_blend1_input(u32 index, + struct hw_osd_blending_s *blending) +{ + struct layer_blend_s *layer_blend; + u32 workaround_line = 0; + /* for g12a blend shift issue */ + + if (osd_hw.hdr_used) + workaround_line = 1; + else { + if (blending->layer_cnt == 2) + workaround_line = 0; + else + workaround_line = 1; + } + + layer_blend = &(blending->layer_blend); + if (index == OSD1) { + if ((blending->osd_blend_mode == OSD_BLEND_AC) + || (blending->osd_blend_mode == OSD_BLEND_ABC) + || (blending->osd_blend_mode == OSD_BLEND_AB_C)) { + layer_blend->output_data.x = + blending->dst_data.x; + layer_blend->output_data.y = + blending->dst_data.y + + workaround_line; + layer_blend->output_data.w = + blending->dst_data.w; + layer_blend->output_data.h = + blending->dst_data.h; + } + } else { + layer_blend->output_data.x = + osd_hw.free_dst_data[index].x_start; + layer_blend->output_data.y = + osd_hw.free_dst_data[index].y_start + + workaround_line; + layer_blend->output_data.w = + osd_hw.free_dst_data[index].x_end - + osd_hw.free_dst_data[index].x_start + 1; + layer_blend->output_data.h = + osd_hw.free_dst_data[index].y_end - + osd_hw.free_dst_data[index].y_start + 1; + } + osd_log_dbg2("blend1_input:input_data[osd%d]:%d,%d,%d,%d\n", + index, + layer_blend->output_data.x, + layer_blend->output_data.y, + layer_blend->output_data.w, + layer_blend->output_data.h); } /* every output is next path input */ @@ -6623,9 +6586,6 @@ static void set_blend_path(struct hw_osd_blending_s *blending) struct dispdata_s output1_data; u32 index = 0; u8 input1 = 0, input2 = 0; -#ifdef OSD_BLEND_SHIFT_WORKAROUND - u32 workaround_line = 1; -#endif if (!blending) return; @@ -6687,7 +6647,6 @@ static void set_blend_path(struct hw_osd_blending_s *blending) } else { osd_log_dbg2("first: set osd%d freescale\n", index); osd_set_freescale(index, blending); - osd_hw.free_dst_data[index].x_start += osd_hw.disp_info.position_x; osd_hw.free_dst_data[index].x_end += @@ -6696,6 +6655,7 @@ static void set_blend_path(struct hw_osd_blending_s *blending) osd_hw.disp_info.position_y; osd_hw.free_dst_data[index].y_end += osd_hw.disp_info.position_y; + osd_setting_blend0_input(index, blending); osd_setting_blend0(blending); if (!blend_reg->din0_byp_blend) { @@ -6770,6 +6730,7 @@ static void set_blend_path(struct hw_osd_blending_s *blending) if (osd_hw.blend_bypass) layer_blend->input2 |= BYPASS_DIN; #endif +#if 0 layer_blend->input2_data.x = osd_hw.free_dst_data[index].x_start; layer_blend->input2_data.w = @@ -6780,6 +6741,12 @@ static void set_blend_path(struct hw_osd_blending_s *blending) layer_blend->input2_data.h = osd_hw.free_dst_data[index].y_end - osd_hw.free_dst_data[index].y_start + 1; +#endif + osd_setting_blend1_input(index, blending); + memcpy(&layer_blend->input2_data, + &layer_blend->output_data, + sizeof(struct dispdata_s)); + osd_setting_blend1(blending); layer_blend->input1 = BLEND0_DIN; @@ -6787,10 +6754,6 @@ static void set_blend_path(struct hw_osd_blending_s *blending) /* always used input1_data */ memcpy(&layer_blend->input1_data, &output1_data, sizeof(struct dispdata_s)); - //memcpy(&layer_blend->input2_data, - // &(layer_blend->output_data), - // sizeof(struct dispdata_s)); - osd_setting_blend2(blending); /* used osd0 freescale */ @@ -6838,7 +6801,7 @@ static void set_blend_path(struct hw_osd_blending_s *blending) osd_setting_blend2(blending); } /* here freescale osd0 used */ - osd_log_dbg2("after blend2: set osd%d freescale\n", index); + osd_log_dbg2("after blend: set osd%d freescale\n", index); osd_set_freescale(index, blending); /* save freescale output */ output1_data.x = @@ -6876,6 +6839,7 @@ static void set_blend_path(struct hw_osd_blending_s *blending) if (osd_hw.blend_bypass) layer_blend->input2 |= BYPASS_DIN; #endif + #if 0 layer_blend->input2_data.x = osd_hw.free_dst_data[index].x_start + osd_hw.disp_info.position_x; @@ -6888,6 +6852,17 @@ static void set_blend_path(struct hw_osd_blending_s *blending) layer_blend->input2_data.h = osd_hw.free_dst_data[index].y_end - osd_hw.free_dst_data[index].y_start + 1; + #endif + osd_setting_blend1_input(index, blending); + memcpy(&layer_blend->input2_data, + &layer_blend->output_data, + sizeof(struct dispdata_s)); + /* adjust offset*/ + layer_blend->input2_data.x += + osd_hw.disp_info.position_x; + layer_blend->input2_data.y += + osd_hw.disp_info.position_y; + osd_setting_blend1(blending); if (!blending->b_exchange_blend_in) { @@ -6912,18 +6887,17 @@ static void set_blend_path(struct hw_osd_blending_s *blending) case OSD_BLEND_ABC: /* blend0 -->blend2-->sc-->vpp_osd1 */ /* sc-->blend1 -->blend2 */ - if (!blending->b_exchange_din) { - input1 = BLEND_DIN1; - input2 = BLEND_DIN4; - } else { - input1 = BLEND_DIN4; - input2 = BLEND_DIN1; - } + input1 = BLEND_DIN1; + input2 = BLEND_DIN4; layer_blend->input1 = input1; layer_blend->input2 = BLEND_NO_DIN; index = blend_din_to_osd(input1, blending); if (index >= OSD_MAX) return; + if (index != OSD1) { + osd_log_dbg2("index=%d, need set freescale\n", index); + osd_set_freescale(index, blending); + } osd_setting_blend0_input(index, blending); osd_setting_blend0(blending); memcpy(&output1_data, &(layer_blend->output_data), @@ -6933,38 +6907,27 @@ static void set_blend_path(struct hw_osd_blending_s *blending) layer_blend->input2 = input2; index = blend_din_to_osd(layer_blend->input1, blending); if (index != OSD1) { - osd_log_dbg2("before blend1: set osd%d freescale\n", + osd_log_dbg2("blend1 input1: set osd%d freescale\n", index); osd_set_freescale(index, blending); } - layer_blend->input1_data.x = - osd_hw.free_dst_data[index].x_start; - layer_blend->input1_data.w = - osd_hw.free_dst_data[index].x_end - - osd_hw.free_dst_data[index].x_start + 1; - layer_blend->input1_data.y = - osd_hw.free_dst_data[index].y_start; - layer_blend->input1_data.h = - osd_hw.free_dst_data[index].y_end - - osd_hw.free_dst_data[index].y_start + 1; + osd_setting_blend1_input(index, blending); + memcpy(&layer_blend->input1_data, + &layer_blend->output_data, + sizeof(struct dispdata_s)); + index = blend_din_to_osd(layer_blend->input2, blending); if (index >= OSD_MAX) return; if (index != OSD1) { - osd_log_dbg2("before blend1: set osd%d freescale\n", + osd_log_dbg2("blend1 input2: set osd%d freescale\n", index); osd_set_freescale(index, blending); } - layer_blend->input2_data.x = - osd_hw.free_dst_data[index].x_start; - layer_blend->input2_data.w = - osd_hw.free_dst_data[index].x_end - - osd_hw.free_dst_data[index].x_start + 1; - layer_blend->input2_data.y = - osd_hw.free_dst_data[index].y_start; - layer_blend->input2_data.h = - osd_hw.free_dst_data[index].y_end - - osd_hw.free_dst_data[index].y_start + 1; + osd_setting_blend1_input(index, blending); + memcpy(&layer_blend->input2_data, + &layer_blend->output_data, + sizeof(struct dispdata_s)); osd_setting_blend1(blending); layer_blend->input1 = BLEND0_DIN; @@ -7033,7 +6996,6 @@ static void set_blend_path(struct hw_osd_blending_s *blending) output1_data.h = osd_hw.free_dst_data[index].y_end - osd_hw.free_dst_data[index].y_start + 1; - index = blend_din_to_osd(BLEND_DIN3, blending); if (index >= OSD_MAX) return; @@ -7052,7 +7014,6 @@ static void set_blend_path(struct hw_osd_blending_s *blending) osd_hw.free_dst_data[index].y_end - osd_hw.free_dst_data[index].y_start + 1; - index = blend_din_to_osd(BLEND_DIN4, blending); if (index >= OSD_MAX) return; @@ -7104,7 +7065,12 @@ static void set_blend_path(struct hw_osd_blending_s *blending) /* sc -->vpp_osd2 */ layer_blend->input1 = BLEND_DIN1; layer_blend->input2 = BLEND_NO_DIN; + blending->blend_din = BLEND_DIN1; index = blend_din_to_osd(BLEND_DIN1, blending); + if (index != OSD1) { + osd_log_info("index=%d, need set freescale\n", index); + osd_set_freescale(index, blending); + } osd_setting_blend0_input(index, blending); osd_setting_blend0(blending); /* save blend0 output */ @@ -7115,26 +7081,17 @@ static void set_blend_path(struct hw_osd_blending_s *blending) layer_blend->input1 = BLEND_DIN3; layer_blend->input2 = BLEND_NO_DIN | BYPASS_DIN; layer_blend->blend_core1_bypass = 1; + blending->blend_din = BLEND_DIN3; index = blend_din_to_osd(BLEND_DIN3, blending); if (index != OSD1) { osd_log_dbg2("before blend1: set osd%d freescale\n", index); osd_set_freescale(index, blending); - layer_blend->input1_data.x = - osd_hw.free_dst_data[index].x_start; - layer_blend->input1_data.w = - osd_hw.free_dst_data[index].x_end - - osd_hw.free_dst_data[index].x_start + 1; - layer_blend->input1_data.y = - osd_hw.free_dst_data[index].y_start; - layer_blend->input1_data.h = - osd_hw.free_dst_data[index].y_end - - osd_hw.free_dst_data[index].y_start + 1; - } else { - memcpy(&layer_blend->input1_data, - &osd_hw.src_data[index], - sizeof(struct dispdata_s)); } + osd_setting_blend1_input(index, blending); + memcpy(&layer_blend->input1_data, + &layer_blend->output_data, + sizeof(struct dispdata_s)); osd_setting_blend1(blending); /* din1=>blend0 & din3-> blend1 ==> blend2 */ @@ -7166,10 +7123,13 @@ static void set_blend_path(struct hw_osd_blending_s *blending) output1_data.y, output1_data.h); + /* din4 ==> vpp */ index = blend_din_to_osd(BLEND_DIN4, blending); - osd_log_dbg2("before blend1: set osd%d freescale\n", index); + blending->blend_din = BLEND_DIN4; + osd_log_dbg2("bypass blend1: set osd%d freescale\n", index); osd_set_freescale(index, blending); + layer_blend->input2_data.x = osd_hw.free_dst_data[index].x_start + osd_hw.disp_info.position_x; @@ -7189,8 +7149,6 @@ static void set_blend_path(struct hw_osd_blending_s *blending) layer_blend->input2 = BLEND1_DIN; memcpy(&layer_blend->input1_data, &output1_data, sizeof(struct dispdata_s)); - layer_blend->input2_data.y += workaround_line; - layer_blend->input2_data.h -= workaround_line; } else { layer_blend->input1 = BLEND1_DIN; layer_blend->input2 = BLEND2_DIN; @@ -7200,11 +7158,8 @@ static void set_blend_path(struct hw_osd_blending_s *blending) memcpy(&layer_blend->input2_data, &output1_data, sizeof(struct dispdata_s)); - layer_blend->input1_data.y += workaround_line; - layer_blend->input1_data.h -= workaround_line; } vpp_setting_blend(blending); - break; #endif } @@ -7214,11 +7169,15 @@ static void set_blend_reg(struct layer_blend_reg_s *blend_reg) { int i; u32 reg_offset = 2; + u32 osd1_alpha_div = 0, osd2_alpha_div = 0; #ifdef OSD_BLEND_SHIFT_WORKAROUND - u32 osd_count = osd_hw.osd_meson_dev.osd_count; + u32 osd_count = OSD_BLEND_LAYERS; #else - u32 osd_count = osd_hw.osd_meson_dev.osd_count - 1; + u32 osd_count = osd_hw.osd_meson_dev.viu1_osd_count; #endif + u32 dv_core2_hsize; + u32 dv_core2_vsize; + if (!blend_reg) return; /* osd blend ctrl */ @@ -7231,19 +7190,29 @@ static void set_blend_reg(struct layer_blend_reg_s *blend_reg) blend_reg->blend_din_en << 20| blend_reg->din_premult_en << 16| blend_reg->din_reoder_sel); + if (blend_reg->postbld_osd1_premult) + osd1_alpha_div = 1; + if (blend_reg->postbld_osd2_premult) + osd2_alpha_div = 1; + /* VIU_OSD_BLEND_CTRL1 */ + VSYNCOSD_WR_MPEG_REG(VIU_OSD_BLEND_CTRL1, + (osd1_alpha_div & 0x1) | + (3 << 4) | + ((osd2_alpha_div & 0x1) << 12) | + (3 << 16)); /* vpp osd1 blend ctrl */ VSYNCOSD_WR_MPEG_REG(OSD1_BLEND_SRC_CTRL, (0 & 0xf) << 0 | (0 & 0x1) << 4 | (blend_reg->postbld_src3_sel & 0xf) << 8 | - (blend_reg->postbld_osd1_premult & 0x1) << 16| + (0 << 16) | (1 & 0x1) << 20); /* vpp osd2 blend ctrl */ VSYNCOSD_WR_MPEG_REG(OSD2_BLEND_SRC_CTRL, (0 & 0xf) << 0 | (0 & 0x1) << 4 | (blend_reg->postbld_src4_sel & 0xf) << 8 | - (blend_reg->postbld_osd2_premult & 0x1) << 16 | + (0 << 16) | (1 & 0x1) << 20); VSYNCOSD_WR_MPEG_REG(VIU_OSD_BLEND_BLEND0_SIZE, @@ -7279,6 +7248,80 @@ static void set_blend_reg(struct layer_blend_reg_s *blend_reg) } #endif } + dv_core2_vsize = (blend_reg->vpp_osd1_blend_v_scope & 0xfff) + - ((blend_reg->vpp_osd1_blend_v_scope >> 16) & 0xfff) + 1; + dv_core2_hsize = (blend_reg->vpp_osd1_blend_h_scope & 0xfff) + - ((blend_reg->vpp_osd1_blend_h_scope >> 16) & 0xfff) + 1; + if (osd_hw.osd_meson_dev.has_dolby_vision) { + VSYNCOSD_WR_MPEG_REG( + DOLBY_CORE2A_SWAP_CTRL1, + ((dv_core2_vsize + 0x40) << 16) + | (dv_core2_hsize + 0x80 + 0)); + VSYNCOSD_WR_MPEG_REG( + DOLBY_CORE2A_SWAP_CTRL2, + (dv_core2_vsize << 16) | (dv_core2_hsize + 0)); +#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION + update_graphic_width_height(dv_core2_vsize, dv_core2_hsize); +#endif + } + +} + +static void uniformization_fb(u32 index, + struct hw_osd_blending_s *blending) +{ + blending->dst_data.x = (osd_hw.dst_data[index].x << OSD_CALC) / + blending->screen_ratio_w; + blending->dst_data.y = (osd_hw.dst_data[index].y << OSD_CALC) / + blending->screen_ratio_h; + blending->dst_data.w = (osd_hw.dst_data[index].w << OSD_CALC) / + blending->screen_ratio_w; + blending->dst_data.h = (osd_hw.dst_data[index].h << OSD_CALC) / + blending->screen_ratio_h; + if (osd_hw.dst_data[index].w < osd_hw.disp_info.position_w) + osd_log_err("base dispframe w(%d) must >= position_w(%d)\n", + osd_hw.dst_data[index].w, osd_hw.disp_info.position_w); + if ((blending->dst_data.w + blending->dst_data.x) > + osd_hw.disp_info.background_w) { + blending->dst_data.w = osd_hw.disp_info.background_w + - blending->dst_data.x; + osd_log_info("blending w(%d) must < base fb w(%d)\n", + blending->dst_data.w + blending->dst_data.x, + osd_hw.disp_info.background_w); + } + osd_log_dbg2("uniformization:osd%d:dst_data:%d,%d,%d,%d\n", + index, + blending->dst_data.x, + blending->dst_data.y, + blending->dst_data.w, + blending->dst_data.h); +} + +static void adjust_dst_position(void) +{ + int i = 0; + int osd_count = osd_hw.osd_meson_dev.viu1_osd_count; + + for (i = 0; i < osd_count; i++) { + if (osd_hw.enable[i]) { + osd_hw.dst_data[i].x -= + osd_hw.disp_info.position_x; + osd_hw.dst_data[i].y -= + osd_hw.disp_info.position_y; + if (osd_hw.dst_data[i].x < 0) + osd_hw.dst_data[i].x = 0; + if (osd_hw.dst_data[i].y < 0) + osd_hw.dst_data[i].y = 0; + osd_log_dbg2("adjust dst_data:osd%d:%d,%d,%d,%d\n", + i, + osd_hw.dst_data[i].x, + osd_hw.dst_data[i].y, + osd_hw.dst_data[i].w, + osd_hw.dst_data[i].h); + } + } + if (osd_hw.field_out_en) + osd_hw.disp_info.position_y /= 2; } static int osd_setting_order(void) @@ -7286,7 +7329,7 @@ static int osd_setting_order(void) int i; struct layer_blend_reg_s *blend_reg; struct hw_osd_blending_s *blending; - u32 osd_count = osd_hw.osd_meson_dev.osd_count - 1; + u32 osd_count = osd_hw.osd_meson_dev.viu1_osd_count; bool update = false; int line1; int line2; @@ -7295,25 +7338,14 @@ static int osd_setting_order(void) blending = &osd_blending; blend_reg = &(blending->blend_reg); - blending->background_w = - osd_hw.disp_info.background_w; - blending->background_h = - osd_hw.disp_info.background_h; blending->vinfo_width = osd_hw.vinfo_width; blending->vinfo_height = osd_hw.vinfo_height; - blending->screen1_ratio_w = (osd_hw.vinfo_width << OSD_CALC) - / osd_hw.disp_info.background_w; - blending->screen1_ratio_h = (osd_hw.vinfo_height << OSD_CALC) - / osd_hw.disp_info.background_h; - blending->screen2_ratio_w = + blending->screen_ratio_w = (osd_hw.disp_info.position_w << OSD_CALC) - / osd_hw.vinfo_width; - blending->screen2_ratio_h = + / osd_hw.disp_info.background_w; + blending->screen_ratio_h = (osd_hw.disp_info.position_h << OSD_CALC) - / osd_hw.vinfo_height; - blending->pic_w_ratio = 1 << OSD_CALC; - blending->pic_h_ratio = 1 << OSD_CALC; - + / osd_hw.disp_info.background_h; blending->layer_cnt = get_available_layers(); set_blend_order(blending); @@ -7322,6 +7354,8 @@ static int osd_setting_order(void) blending->b_exchange_din = false; blending->b_exchange_blend_in = false; blending->osd1_freescale_disable = false; + adjust_dst_position(); + uniformization_fb(OSD1, blending); /* set blend mode */ set_blend_mode(blending); @@ -7332,12 +7366,13 @@ static int osd_setting_order(void) /* set blend path */ set_blend_path(blending); line1 = get_enter_encp_line(); - vinfo_height = osd_hw.b_interlaced ? + vinfo_height = osd_hw.field_out_en ? (osd_hw.vinfo_height * 2) : osd_hw.vinfo_height; - if (line1 >= (vinfo_height * 3 / 4)) { - osd_log_info( - "enter osd_setting_order:cnt=%d,encp line=%d\n", - cnt, line1); + if (line1 >= vinfo_height) { + if (osd_hw.osd_display_debug == ENCP_LINE_VSYNC) + osd_log_info( + "enter osd_setting_order:cnt=%d,encp line=%d\n", + cnt, line1); osd_wait_vsync_hw(); line1 = get_enter_encp_line(); } @@ -7461,9 +7496,9 @@ static void osd_setting_default_hwc(void) /* Do later: different format select different dummy_data */ /* used default dummy data */ VSYNCOSD_WR_MPEG_REG(VIU_OSD_BLEND_DUMMY_DATA0, - 0x0 << 16 | - 0x0 << 8 | - 0x0); + 0x80 << 16 | + 0x80 << 8 | + 0x80); /* used default dummy alpha data */ VSYNCOSD_WR_MPEG_REG(VIU_OSD_BLEND_DUMMY_ALPHA, 0x0 << 20 | @@ -7483,29 +7518,88 @@ static void osd_setting_default_hwc(void) 0x3, 2, 2); } +static bool set_old_hwc_freescale(u32 index) +{ + u32 x_start, x_end, y_start, y_end, height_dst, height_src; + + if (osd_hw.osd_reverse[index] == REVERSE_TRUE) { + x_start = osd_hw.vinfo_width + - osd_hw.free_dst_data[index].x_end - 1; + y_start = osd_hw.vinfo_height + - osd_hw.free_dst_data[index].y_end - 1; + x_end = osd_hw.vinfo_width + - osd_hw.free_dst_data[index].x_start - 1; + y_end = osd_hw.vinfo_height + - osd_hw.free_dst_data[index].y_start - 1; + osd_hw.free_dst_data[index].x_start = x_start; + osd_hw.free_dst_data[index].y_start = y_start; + osd_hw.free_dst_data[index].x_end = x_end; + osd_hw.free_dst_data[index].y_end = y_end; + } else if (osd_hw.osd_reverse[index] == REVERSE_X) { + x_start = osd_hw.vinfo_width + - osd_hw.free_dst_data[index].x_end - 1; + x_end = osd_hw.vinfo_width + - osd_hw.free_dst_data[index].x_start - 1; + osd_hw.free_dst_data[index].x_start = x_start; + osd_hw.free_dst_data[index].x_end = x_end; + } else if (osd_hw.osd_reverse[index] == REVERSE_Y) { + y_start = osd_hw.vinfo_height + - osd_hw.free_dst_data[index].y_end - 1; + y_end = osd_hw.vinfo_height + - osd_hw.free_dst_data[index].y_start - 1; + osd_hw.free_dst_data[index].y_start = y_start; + osd_hw.free_dst_data[index].y_end = y_end; + } + osd_log_dbg("free_dst_data: %x,%x,%x,%x\n", + osd_hw.free_dst_data[index].x_start, + osd_hw.free_dst_data[index].x_end, + osd_hw.free_dst_data[index].y_start, + osd_hw.free_dst_data[index].y_end); + + /* set dummy_data alpha */ + height_dst = osd_hw.free_dst_data[index].y_end - + osd_hw.free_dst_data[index].y_start + 1; + height_src = osd_hw.free_src_data[index].y_end - + osd_hw.free_src_data[index].y_start + 1; + if (height_dst != height_src) + osd_set_dummy_data(index, 0); + else + osd_set_dummy_data(index, 0xff); + + if ((memcmp(&(osd_hw.free_src_data[index]), + &osd_hw.free_src_data_backup[index], + sizeof(struct pandata_s)) != 0) || + (memcmp(&(osd_hw.free_dst_data[index]), + &osd_hw.free_dst_data_backup[index], + sizeof(struct pandata_s)) != 0)) { + memcpy(&osd_hw.free_src_data_backup[index], + &osd_hw.free_src_data[index], + sizeof(struct pandata_s)); + memcpy(&osd_hw.free_dst_data_backup[index], + &osd_hw.free_dst_data[index], + sizeof(struct pandata_s)); + return true; + } else + return false; +} + +#if 0 static bool set_old_hwc_freescale(u32 index) { u32 x_start, x_end, y_start, y_end; u32 width_src = 0, width_dst = 0, height_src = 0, height_dst = 0; u32 width, height; - u32 screen1_ratio_w, screen1_ratio_h; - u32 screen2_ratio_w, screen2_ratio_h; + u32 screen_ratio_w, screen_ratio_h; width_src = osd_hw.disp_info.background_w; height_src = osd_hw.disp_info.background_h; width_dst = osd_hw.vinfo_width; height_dst = osd_hw.vinfo_height; - screen1_ratio_w = (osd_hw.vinfo_width << OSD_CALC) + screen_ratio_w = (osd_hw.disp_info.position_w << OSD_CALC) / osd_hw.disp_info.background_w; - screen1_ratio_h = (osd_hw.vinfo_height << OSD_CALC) + screen_ratio_h = (osd_hw.disp_info.position_h << OSD_CALC) / osd_hw.disp_info.background_h; - screen2_ratio_w = - (osd_hw.disp_info.position_w << OSD_CALC) - / osd_hw.vinfo_width; - screen2_ratio_h = - (osd_hw.disp_info.position_h << OSD_CALC) - / osd_hw.vinfo_height; osd_log_dbg("width_src:%d,%d\n", width_src, height_src); osd_log_dbg("width_src:%d,%d\n", @@ -7517,16 +7611,12 @@ static bool set_old_hwc_freescale(u32 index) osd_hw.free_dst_data[index].y_start; osd_hw.free_dst_data[index].x_start = (osd_hw.free_dst_data[index].x_start - * screen1_ratio_w >> OSD_CALC) - * screen2_ratio_w >> OSD_CALC; + * screen_ratio_w >> OSD_CALC); osd_hw.free_dst_data[index].y_start = (osd_hw.free_dst_data[index].y_start - * screen1_ratio_h >> OSD_CALC) - * screen2_ratio_h >> OSD_CALC; - width = (width * screen1_ratio_w >> OSD_CALC) - * screen2_ratio_w >> OSD_CALC; - height = (height * screen1_ratio_h >> OSD_CALC) - * screen2_ratio_h >> OSD_CALC; + * screen_ratio_h >> OSD_CALC); + width = (width * screen_ratio_w >> OSD_CALC); + height = (height * screen_ratio_h >> OSD_CALC); osd_hw.free_dst_data[index].x_start += osd_hw.disp_info.position_x; @@ -7586,11 +7676,13 @@ static bool set_old_hwc_freescale(u32 index) } else return false; } +#endif static void osd_setting_old_hwc(void) { int index = OSD1; bool freescale_update = false; + static u32 osd_enable; spin_lock_irqsave(&osd_lock, lock_flags); osd_hw.reg[OSD_COLOR_MODE].update_func(index); @@ -7609,10 +7701,13 @@ static void osd_setting_old_hwc(void) } osd_update_window_axis = false; } - if (!osd_hw.osd_display_debug - && (suspend_flag == false)) + if (osd_enable != osd_hw.enable[index] + && (!osd_hw.osd_display_debug) + && (suspend_flag == false)) { osd_hw.reg[OSD_ENABLE] .update_func(index); + osd_enable = osd_hw.enable[index]; + } spin_unlock_irqrestore(&osd_lock, lock_flags); osd_wait_vsync_hw(); } @@ -7806,15 +7901,6 @@ static void osd_basic_update_disp_geometry(u32 index) osd_hw.src_data[index].h - 1) & 0x1fff) << 16; VSYNCOSD_WR_MPEG_REG(osd_reg->osd_blk0_cfg_w2, data32); buffer_h = ((data32 >> 16) & 0x1fff) - (data32 & 0x1fff) + 1; - if (osd_hw.osd_meson_dev.has_dolby_vision) { - VSYNCOSD_WR_MPEG_REG( - DOLBY_CORE2A_SWAP_CTRL1, - ((buffer_w + 0x40) << 16) - | (buffer_h + 0x80 + 0)); - VSYNCOSD_WR_MPEG_REG( - DOLBY_CORE2A_SWAP_CTRL2, - (buffer_w << 16) | (buffer_h + 0)); - } data32 = VSYNCOSD_RD_MPEG_REG(osd_reg->osd_ctrl_stat); data32 &= ~0x1ff008;//0x1ff00e; data32 |= osd_hw.gbl_alpha[index] << 12; @@ -7938,6 +8024,9 @@ static void osd1_basic_update_disp_geometry(void) VSYNCOSD_WR_MPEG_REG( DOLBY_CORE2A_SWAP_CTRL2, (buffer_w << 16) | (buffer_h + 0)); +#ifdef CONFIG_AMLOGIC_MEDIA_ENHANCEMENT_DOLBYVISION + update_graphic_width_height(buffer_w, buffer_h); +#endif } if (osd_hw.osd_afbcd[OSD1].enable && !osd_afbc_dec_enable && @@ -8171,8 +8260,7 @@ void osd_init_hw(u32 logo_loaded, u32 osd_probe, else if ((osd_meson->cpu_id >= __MESON_CPU_MAJOR_ID_GXL) && (osd_meson->cpu_id <= __MESON_CPU_MAJOR_ID_TXL)) backup_regs_init(HW_RESET_OSD1_REGS); - else if ((osd_meson->cpu_id == __MESON_CPU_MAJOR_ID_G12A) - || (osd_meson->cpu_id == __MESON_CPU_MAJOR_ID_G12B)) + else if (osd_meson->cpu_id >= __MESON_CPU_MAJOR_ID_G12A) backup_regs_init(HW_RESET_MALI_AFBCD_REGS); else backup_regs_init(HW_RESET_NONE); @@ -8237,7 +8325,7 @@ void osd_init_hw(u32 logo_loaded, u32 osd_probe, /* fifo_depth_val: 32 or 64 *8 = 256 or 512 */ data32 |= (osd_hw.osd_meson_dev.osd_fifo_len & 0xfffffff) << 12; - for (idx = 0; idx < osd_hw.osd_meson_dev.osd_count - 1; idx++) + for (idx = 0; idx < osd_hw.osd_meson_dev.viu1_osd_count; idx++) osd_reg_write( hw_osd_reg_array[idx].osd_fifo_ctrl_stat, data32); /* osd_reg_write(VIU_OSD2_FIFO_CTRL_STAT, data32_); */ @@ -8256,7 +8344,7 @@ void osd_init_hw(u32 logo_loaded, u32 osd_probe, /* just disable osd to avoid booting hang up */ data32 = 0x1 << 0; data32 |= OSD_GLOBAL_ALPHA_DEF << 12; - for (idx = 0; idx < osd_hw.osd_meson_dev.osd_count - 1; idx++) + for (idx = 0; idx < osd_hw.osd_meson_dev.viu1_osd_count; idx++) osd_reg_write( hw_osd_reg_array[idx].osd_ctrl_stat, data32); } @@ -8291,8 +8379,6 @@ void osd_init_hw(u32 logo_loaded, u32 osd_probe, osd_hw.disp_info.background_h = 1080; osd_hw.vinfo_width = 1920; osd_hw.vinfo_height = 1080; - osd_hw.workaround_not_hdr = 1; - osd_hw.workaround_hdr = 1; for (idx = 0; idx < osd_hw.osd_meson_dev.osd_count; idx++) { osd_hw.premult_en[idx] = 0; osd_hw.osd_afbcd[idx].format = COLOR_INDEX_32_ABGR; @@ -8314,7 +8400,7 @@ void osd_init_hw(u32 logo_loaded, u32 osd_probe, data32 | 0x800000); } - if (idx < osd_hw.osd_meson_dev.osd_count - 1) { + if (idx < osd_hw.osd_meson_dev.viu1_osd_count) { /* TODO: temp set at here, * need move it to uboot */ @@ -8519,7 +8605,7 @@ void osd_init_viu2(void) /* fifo_depth_val: 32 or 64 *8 = 256 or 512 */ data32 |= (osd_hw.osd_meson_dev.osd_fifo_len & 0xfffffff) << 12; - idx = osd_hw.osd_meson_dev.osd_count - 1; + idx = osd_hw.osd_meson_dev.viu2_index; osd_reg_write( hw_osd_reg_array[idx].osd_fifo_ctrl_stat, data32); /* osd_reg_write(VIU_OSD2_FIFO_CTRL_STAT, data32_); */ diff --git a/drivers/amlogic/media/osd/osd_hw.h b/drivers/amlogic/media/osd/osd_hw.h index 3c578c300cff..4b2680fd288b 100644 --- a/drivers/amlogic/media/osd/osd_hw.h +++ b/drivers/amlogic/media/osd/osd_hw.h @@ -170,8 +170,10 @@ void osd_update_vsync_hit(void); void osd_hw_reset(void); void osd_mali_afbc_start(void); int logo_work_init(void); +int get_logo_loaded(void); void set_logo_loaded(void); int set_osd_logo_freescaler(void); +int is_interlaced(struct vinfo_s *vinfo); void osd_get_display_debug(u32 *osd_display_debug_enable); void osd_set_display_debug(u32 osd_display_debug_enable); void osd_get_background_size(struct display_flip_info_s *disp_info); diff --git a/drivers/amlogic/media/osd/osd_logo.c b/drivers/amlogic/media/osd/osd_logo.c index 3bff38ccedeb..c48d644cdd0e 100644 --- a/drivers/amlogic/media/osd/osd_logo.c +++ b/drivers/amlogic/media/osd/osd_logo.c @@ -250,6 +250,10 @@ int set_osd_logo_freescaler(void) return 0; } +int get_logo_loaded(void) +{ + return logo_info.loaded; +} void set_logo_loaded(void) { diff --git a/drivers/amlogic/media/osd/osd_sync.h b/drivers/amlogic/media/osd/osd_sync.h index b38c1855add5..77f754ca68c5 100644 --- a/drivers/amlogic/media/osd/osd_sync.h +++ b/drivers/amlogic/media/osd/osd_sync.h @@ -111,6 +111,7 @@ struct display_flip_info_s { }; struct do_hwc_cmd_s { int out_fen_fd; + unsigned char hdr_mode; struct display_flip_info_s disp_info; }; #endif diff --git a/drivers/amlogic/media/video_processor/ionvideo/ionvideo.c b/drivers/amlogic/media/video_processor/ionvideo/ionvideo.c index cd3ad7a324bf..c89143c2d546 100644 --- a/drivers/amlogic/media/video_processor/ionvideo/ionvideo.c +++ b/drivers/amlogic/media/video_processor/ionvideo/ionvideo.c @@ -575,6 +575,11 @@ static int vidioc_close(struct file *file) { struct ionvideo_dev *dev = video_drvdata(file); + struct ionvideo_dmaqueue *dma_q = &dev->vidq; + + if (dma_q->kthread) + vidioc_streamoff(file, NULL, 0); + IONVID_DBG("vidioc_close!!!!\n"); ppmgr2_release(&(dev->ppmgr2_dev)); //dprintk(dev, 2, "vidioc_close\n"); diff --git a/drivers/amlogic/media/video_processor/ppmgr/ppmgr_vpp.c b/drivers/amlogic/media/video_processor/ppmgr/ppmgr_vpp.c index 47d73ccd377d..4f7e0665273f 100644 --- a/drivers/amlogic/media/video_processor/ppmgr/ppmgr_vpp.c +++ b/drivers/amlogic/media/video_processor/ppmgr/ppmgr_vpp.c @@ -530,6 +530,10 @@ static int ppmgr_receiver_event_fun(int type, void *data, void *private_data) break; case VFRAME_EVENT_PROVIDER_RESET: vf_ppmgr_reset(0); + vf_notify_receiver( + PROVIDER_NAME, + VFRAME_EVENT_PROVIDER_RESET, + NULL); break; case VFRAME_EVENT_PROVIDER_FR_HINT: case VFRAME_EVENT_PROVIDER_FR_END_HINT: @@ -3293,7 +3297,7 @@ int ppmgr_buffer_init(int vout_mode) int buf_size; struct vinfo_s vinfo = {.width = 1280, .height = 720, }; /* int flags = CODEC_MM_FLAGS_DMA; */ - int flags = CODEC_MM_FLAGS_DMA_CPU|CODEC_MM_FLAGS_CMA_CLEAR; + int flags = CODEC_MM_FLAGS_DMA | CODEC_MM_FLAGS_CMA_CLEAR; #ifdef INTERLACE_DROP_MODE mycount = 0; #endif diff --git a/drivers/amlogic/media/video_processor/video_dev/amlvideo.c b/drivers/amlogic/media/video_processor/video_dev/amlvideo.c index c857498ff6a7..252fa95fed95 100644 --- a/drivers/amlogic/media/video_processor/video_dev/amlvideo.c +++ b/drivers/amlogic/media/video_processor/video_dev/amlvideo.c @@ -282,6 +282,13 @@ static int video_receiver_event_fun(int type, void *data, void *private_data) } else if (type == VFRAME_EVENT_PROVIDER_FR_END_HINT) { vf_notify_receiver(dev->vf_provider_name, VFRAME_EVENT_PROVIDER_FR_END_HINT, data); + } else if (type == VFRAME_EVENT_PROVIDER_RESET) { + dev->first_frame = 0; + vfq_init(&dev->q_ready, AMLVIDEO_POOL_SIZE + 1, + &dev->amlvideo_pool_ready[0]); + + vf_notify_receiver(dev->vf_provider_name, + VFRAME_EVENT_PROVIDER_RESET, data); } return 0; } @@ -541,6 +548,12 @@ static int vidioc_dqbuf(struct file *file, void *priv, struct v4l2_buffer *p) mutex_unlock(&dev->vfpMutex); return -EAGAIN; } + + if (dev->vf->index == 0xFFFFFFFF) { + pr_info("vidioc_dqbuf: Invalid vf\n"); + return -EAGAIN; + } + dev->vf->omx_index = dev->frame_num; dev->am_parm.signal_type = dev->vf->signal_type; dev->am_parm.master_display_colour diff --git a/drivers/amlogic/media/video_processor/video_dev/amlvideo2.c b/drivers/amlogic/media/video_processor/video_dev/amlvideo2.c index cc8127aed8dc..8a582116cbd5 100644 --- a/drivers/amlogic/media/video_processor/video_dev/amlvideo2.c +++ b/drivers/amlogic/media/video_processor/video_dev/amlvideo2.c @@ -5353,7 +5353,7 @@ int amlvideo2_cma_buf_init(struct amlvideo2_device *vid_dev, int node_id) return -1; } } else { - flags = CODEC_MM_FLAGS_DMA_CPU| + flags = CODEC_MM_FLAGS_DMA | CODEC_MM_FLAGS_CMA_CLEAR; if (node_id == 0) { if (vid_dev->node[node_id]-> diff --git a/drivers/amlogic/media/video_sink/video.c b/drivers/amlogic/media/video_sink/video.c index a0e5167fb018..08b1fca43bf3 100644 --- a/drivers/amlogic/media/video_sink/video.c +++ b/drivers/amlogic/media/video_sink/video.c @@ -219,6 +219,7 @@ static u32 next_peek_underflow; static DEFINE_SPINLOCK(video_onoff_lock); static int video_onoff_state = VIDEO_ENABLE_STATE_IDLE; +static u32 video_onoff_time; static DEFINE_SPINLOCK(video2_onoff_lock); static int video2_onoff_state = VIDEO_ENABLE_STATE_IDLE; static u32 hdmiin_frame_check; @@ -2968,6 +2969,13 @@ static inline void vd1_path_select(bool afbc) /* afbc0 gclk ctrl */ (0 << 0), 0, 22); + if (cpu_after_eq(MESON_CPU_MAJOR_ID_TL1)) + VSYNC_WR_MPEG_REG_BITS( + VD1_AFBCD0_MISC_CTRL, + /* Vd1_afbc0_mem_sel */ + (afbc ? 1 : 0), + 22, 1); + #ifdef CONFIG_AMLOGIC_MEDIA_DEINTERLACE if (!cpu_after_eq(MESON_CPU_MAJOR_ID_G12A)) return; @@ -3025,6 +3033,12 @@ static inline void vd2_path_select(bool afbc) /* afbc1 gclk ctrl */ (0 << 0), 0, 22); + if (cpu_after_eq(MESON_CPU_MAJOR_ID_TL1)) + VSYNC_WR_MPEG_REG_BITS( + VD2_AFBCD1_MISC_CTRL, + /* Vd2_afbc0_mem_sel */ + (afbc ? 1 : 0), + 22, 1); } else { VSYNC_WR_MPEG_REG_BITS( VIU_MISC_CTRL1 + misc_off, @@ -3073,7 +3087,14 @@ static void viu_set_dcu(struct vpp_frame_par_s *frame_par, struct vframe_s *vf) r |= (1<<29); VSYNC_WR_MPEG_REG(AFBC_MODE, r); VSYNC_WR_MPEG_REG(AFBC_ENABLE, 0x1700); - VSYNC_WR_MPEG_REG(AFBC_CONV_CTRL, 0x100); + + r = 0x100; + /* need check the vf->type 444/422/420 */ + /* current use 420 as default for tl1 */ + if (cpu_after_eq(MESON_CPU_MAJOR_ID_TL1)) + r |= (2 << 12); + VSYNC_WR_MPEG_REG(AFBC_CONV_CTRL, r); + u = (vf->bitdepth >> (BITDEPTH_U_SHIFT)) & 0x3; v = (vf->bitdepth >> (BITDEPTH_V_SHIFT)) & 0x3; VSYNC_WR_MPEG_REG(AFBC_DEC_DEF_COLOR, @@ -3633,7 +3654,14 @@ static void vd2_set_dcu(struct vpp_frame_par_s *frame_par, struct vframe_s *vf) r |= (1<<29); VSYNC_WR_MPEG_REG(VD2_AFBC_MODE, r); VSYNC_WR_MPEG_REG(VD2_AFBC_ENABLE, 0x1700); - VSYNC_WR_MPEG_REG(VD2_AFBC_CONV_CTRL, 0x100); + + r = 0x100; + /* need check the vf->type 444/422/420 */ + /* current use 420 as default for tl1 */ + if (cpu_after_eq(MESON_CPU_MAJOR_ID_TL1)) + r |= (2 << 12); + VSYNC_WR_MPEG_REG(VD2_AFBC_CONV_CTRL, r); + u = (vf->bitdepth >> (BITDEPTH_U_SHIFT)) & 0x3; v = (vf->bitdepth >> (BITDEPTH_V_SHIFT)) & 0x3; VSYNC_WR_MPEG_REG(VD2_AFBC_DEC_DEF_COLOR, @@ -6264,6 +6292,7 @@ SET_FILTER: VPP_POSTBLEND_EN; video_onoff_state = VIDEO_ENABLE_STATE_IDLE; + video_onoff_time = jiffies_to_msecs(jiffies); if (debug_flag & DEBUG_FLAG_BLACKOUT) pr_info("VsyncEnableVideoLayer\n"); @@ -6279,6 +6308,7 @@ SET_FILTER: VSYNC_WR_MPEG_REG(VPP_SRSHARP0_CTRL, 0); VSYNC_WR_MPEG_REG(VPP_SRSHARP1_CTRL, 0); video_onoff_state = VIDEO_ENABLE_STATE_IDLE; + video_onoff_time = jiffies_to_msecs(jiffies); vpu_delay_work_flag |= VPU_VIDEO_LAYER1_CHANGED; if (debug_flag & DEBUG_FLAG_BLACKOUT) @@ -6322,6 +6352,7 @@ SET_FILTER: else vpp_misc_set |= (0x1ff << VPP_VD2_ALPHA_BIT); video2_onoff_state = VIDEO_ENABLE_STATE_IDLE; + video_onoff_time = jiffies_to_msecs(jiffies); if (debug_flag & DEBUG_FLAG_BLACKOUT) pr_info("VsyncEnableVideoLayer2\n"); @@ -6329,6 +6360,7 @@ SET_FILTER: vpp_misc_set &= ~(VPP_VD2_PREBLEND | VPP_VD2_POSTBLEND | VPP_PREBLEND_EN); video2_onoff_state = VIDEO_ENABLE_STATE_IDLE; + video_onoff_time = jiffies_to_msecs(jiffies); if (debug_flag & DEBUG_FLAG_BLACKOUT) pr_info("VsyncDisableVideoLayer2\n"); @@ -6348,6 +6380,14 @@ SET_FILTER: video_enabled = video_status_saved; } + if (!video_enabled && + (vpp_misc_set & VPP_VD1_POSTBLEND)) + vpp_misc_set &= ~(VPP_VD1_PREBLEND | + VPP_VD2_PREBLEND | + VPP_VD2_POSTBLEND | + VPP_VD1_POSTBLEND | + VPP_PREBLEND_EN); + if (!legacy_vpp) { u32 set_value = 0; @@ -6753,10 +6793,17 @@ static void video_vf_unreg_provider(void) #endif } -static void video_vf_light_unreg_provider(void) +static void video_vf_light_unreg_provider(int need_keep_frame) { ulong flags; + if (need_keep_frame) { + /* wait for the end of the last toggled frame*/ + atomic_set(&video_unreg_flag, 1); + while (atomic_read(&video_inirq_flag) > 0) + schedule(); + } + spin_lock_irqsave(&lock, flags); #ifdef CONFIG_AMLOGIC_MEDIA_VSYNC_RDMA dispbuf_to_put_num = DISPBUF_TO_PUT_MAX; @@ -6772,6 +6819,19 @@ static void video_vf_light_unreg_provider(void) cur_dispbuf = &vf_local; } spin_unlock_irqrestore(&lock, flags); + + if (need_keep_frame) { + /* keep the last toggled frame*/ + if (cur_dispbuf) { + unsigned int result; + + result = vf_keep_current(cur_dispbuf, NULL); + if (result == 0) + pr_info("%s: keep cur_disbuf failed\n", + __func__); + } + atomic_set(&video_unreg_flag, 0); + } } static int get_display_info(void *data) @@ -6837,9 +6897,9 @@ static int video_receiver_event_fun(int type, void *data, void *private_data) //init_hdr_info(); } else if (type == VFRAME_EVENT_PROVIDER_RESET) { - video_vf_light_unreg_provider(); + video_vf_light_unreg_provider(1); } else if (type == VFRAME_EVENT_PROVIDER_LIGHT_UNREG) - video_vf_light_unreg_provider(); + video_vf_light_unreg_provider(0); else if (type == VFRAME_EVENT_PROVIDER_REG) { enable_video_discontinue_report = 1; drop_frame_count = 0; @@ -6873,7 +6933,7 @@ static int video_receiver_event_fun(int type, void *data, void *private_data) (void *)1); } - video_vf_light_unreg_provider(); + video_vf_light_unreg_provider(0); } else if (type == VFRAME_EVENT_PROVIDER_FORCE_BLACKOUT) { force_blackout = 1; if (debug_flag & DEBUG_FLAG_BLACKOUT) { @@ -7553,9 +7613,23 @@ static long amvideo_ioctl(struct file *file, unsigned int cmd, ulong arg) put_user(video_global_output, (u32 __user *)argp); break; - case AMSTREAM_IOC_GET_VIDEO_LAYER1_ON: - put_user(video_onoff_state, (u32 __user *)argp); - break; + case AMSTREAM_IOC_GET_VIDEO_LAYER1_ON: { + u32 vsync_duration; + u32 video_onoff_diff = 0; + + vsync_duration = vsync_pts_inc / 90; + video_onoff_diff = + jiffies_to_msecs(jiffies) - video_onoff_time; + + if (video_onoff_state == VIDEO_ENABLE_STATE_IDLE) { + /* wait until 5ms after next vsync */ + msleep(video_onoff_diff < vsync_duration + ? vsync_duration - video_onoff_diff + 5 + : 0); + } + put_user(video_onoff_state, (u32 __user *)argp); + break; + } case AMSTREAM_IOC_SET_VIDEOPEEK: videopeek = true; @@ -10020,10 +10094,6 @@ static int __init video_early_init(void) VD2_IF0_LUMA_FIFO_SIZE + cur_dev->viu_off, 0x180); } - /*fix S905 av out flicker black dot*/ - if (is_meson_gxbb_cpu()) - SET_VCBUS_REG_MASK(VPP_MISC, VPP_OUT_SATURATE); - #if 0 /* if (0 >= VMODE_MAX) //DEBUG_TMP */ CLEAR_VCBUS_REG_MASK(VPP_VSC_PHASE_CTRL, VPP_PHASECTL_TYPE_INTERLACE); @@ -10090,6 +10160,11 @@ static int __init video_early_init(void) WRITE_DMCREG( DMC_AM0_CHAN_CTRL, 0x8ff403cf); + + /* force bypass dolby for TL1. There is no dolby function */ + if (is_meson_tl1_cpu()) + WRITE_VCBUS_REG_BITS( + DOLBY_PATH_CTRL, 0xf, 0, 6); return 0; } @@ -10221,7 +10296,8 @@ static int __init video_init(void) } #endif - if (is_meson_g12a_cpu() || is_meson_g12b_cpu()) { + if (is_meson_g12a_cpu() || is_meson_g12b_cpu() + || is_meson_tl1_cpu()) { cur_dev->viu_off = 0x3200 - 0x1a50; legacy_vpp = false; } diff --git a/drivers/amlogic/media/video_sink/video_keeper.c b/drivers/amlogic/media/video_sink/video_keeper.c index 72d442fc5317..1dbfcd4ba6b8 100644 --- a/drivers/amlogic/media/video_sink/video_keeper.c +++ b/drivers/amlogic/media/video_sink/video_keeper.c @@ -633,8 +633,7 @@ static int alloc_keep_buffer(void) * if not used ge2d. * need CPU access. */ - flags = CODEC_MM_FLAGS_DMA_CPU | - CODEC_MM_FLAGS_FOR_VDECODER; + flags = CODEC_MM_FLAGS_DMA | CODEC_MM_FLAGS_FOR_VDECODER; #endif if ((flags & CODEC_MM_FLAGS_FOR_VDECODER) && codec_mm_video_tvp_enabled())/*TVP TODO for MULTI*/ @@ -835,6 +834,7 @@ static unsigned int vf_keep_current_locked( cur_dispbuf_el); if (ret) { /*keeped ok with codec keeper!*/ + keep_video_on = 1; return 1; } #ifdef CONFIG_AMLOGIC_MEDIA_MULTI_DEC diff --git a/drivers/amlogic/media/video_sink/vpp.c b/drivers/amlogic/media/video_sink/vpp.c index c7e108dce6b1..b663469a5593 100644 --- a/drivers/amlogic/media/video_sink/vpp.c +++ b/drivers/amlogic/media/video_sink/vpp.c @@ -2436,7 +2436,8 @@ vpp_set_filters(u32 process_3d_type, u32 wide_mode, if ((vf->ratio_control & DISP_RATIO_ADAPTED_PICMODE) && !disable_adapted) { - wide_mode = vf->pic_mode.screen_mode; + if (vf->pic_mode.screen_mode != 0xff) + wide_mode = vf->pic_mode.screen_mode; if (vf->pic_mode.provider == PIC_MODE_PROVIDER_WSS) { /* from wss, need add global setting */ video_source_crop_top += vf->pic_mode.vs; @@ -2674,7 +2675,8 @@ void vpp_super_scaler_support(void) sr_support &= ~SUPER_CORE1_SUPPORT; } scaler_path_sel = SCALER_PATH_MAX; - if (is_meson_g12a_cpu() || is_meson_g12b_cpu()) + if (is_meson_g12a_cpu() || is_meson_g12b_cpu() + || is_meson_tl1_cpu()) sr_reg_offt = 0xc00; else sr_reg_offt = 0; diff --git a/drivers/amlogic/media/vin/tvin/hdmirx/Makefile b/drivers/amlogic/media/vin/tvin/hdmirx/Makefile index 6b55e98cd9e1..b19edee1f893 100644 --- a/drivers/amlogic/media/vin/tvin/hdmirx/Makefile +++ b/drivers/amlogic/media/vin/tvin/hdmirx/Makefile @@ -3,5 +3,6 @@ # obj-$(CONFIG_AMLOGIC_MEDIA_TVIN_HDMI) += tvin_hdmirx.o -tvin_hdmirx-objs := hdmi_rx_wrapper.o hdmi_rx_hw.o hdmi_rx_drv.o hdcp_rx_main.o hdmi_rx_eq.o \ - hdmi_rx_repeater.o hdmi_rx_pktinfo.o hdmi_rx_edid.o +tvin_hdmirx-objs := hdmi_rx_wrapper.o hdmi_rx_hw.o hdmi_rx_drv.o \ + hdcp_rx_main.o hdmi_rx_eq.o \ + hdmi_rx_repeater.o hdmi_rx_pktinfo.o hdmi_rx_edid.o \ No newline at end of file diff --git a/drivers/amlogic/media/vin/tvin/hdmirx/hdcp_rx_main.c b/drivers/amlogic/media/vin/tvin/hdmirx/hdcp_rx_main.c index d52b9f6d377f..dbd19a6f96c8 100644 --- a/drivers/amlogic/media/vin/tvin/hdmirx/hdcp_rx_main.c +++ b/drivers/amlogic/media/vin/tvin/hdmirx/hdcp_rx_main.c @@ -32,6 +32,7 @@ #include #include #include "hdcp_rx_main.h" +#include "hdmi_rx_repeater.h" #include "hdmi_rx_drv.h" #include "hdmi_rx_hw.h" diff --git a/drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_drv.c b/drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_drv.c index 25ed70254fe3..2e99da3573fb 100644 --- a/drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_drv.c +++ b/drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_drv.c @@ -39,6 +39,8 @@ /* #include */ #include #include +#include + /* Amlogic headers */ /*#include */ @@ -51,6 +53,7 @@ #endif /* Local include */ +#include "hdmi_rx_repeater.h" #include "hdmi_rx_drv.h" #include "hdmi_rx_wrapper.h" #include "hdmi_rx_hw.h" @@ -110,9 +113,9 @@ int hdmi_yuv444_enable; module_param(hdmi_yuv444_enable, int, 0664); MODULE_PARM_DESC(hdmi_yuv444_enable, "hdmi_yuv444_enable"); -static int force_color_range; -MODULE_PARM_DESC(force_color_range, "\n force_color_range\n"); -module_param(force_color_range, int, 0664); +bool downstream_repeat_support; +MODULE_PARM_DESC(downstream_repeat_support, "\n downstream_repeat_support\n"); +module_param(downstream_repeat_support, bool, 0664); int pc_mode_en; MODULE_PARM_DESC(pc_mode_en, "\n pc_mode_en\n"); @@ -146,27 +149,41 @@ static bool early_suspend_flag; struct reg_map reg_maps[MAP_ADDR_MODULE_NUM]; + static struct notifier_block aml_hdcp22_pm_notifier = { .notifier_call = aml_hdcp22_pm_notify, }; +static struct meson_hdmirx_data rx_tl1_data = { + .chip_id = CHIP_ID_TL1, + .phy_ver = PHY_VER_TL1, +}; + static struct meson_hdmirx_data rx_txhd_data = { .chip_id = CHIP_ID_TXHD, + .phy_ver = PHY_VER_ORG, }; static struct meson_hdmirx_data rx_txlx_data = { .chip_id = CHIP_ID_TXLX, + .phy_ver = PHY_VER_ORG, }; static struct meson_hdmirx_data rx_txl_data = { .chip_id = CHIP_ID_TXL, + .phy_ver = PHY_VER_ORG, }; static struct meson_hdmirx_data rx_gxtvbb_data = { .chip_id = CHIP_ID_GXTVBB, + .phy_ver = PHY_VER_ORG, }; static const struct of_device_id hdmirx_dt_match[] = { + { + .compatible = "amlogic, hdmirx_tl1", + .data = &rx_tl1_data + }, { .compatible = "amlogic, hdmirx_txhd", .data = &rx_txhd_data @@ -210,8 +227,9 @@ int rx_init_reg_map(struct platform_device *pdev) reg_maps[i].phy_addr = res->start; reg_maps[i].p = devm_ioremap_nocache(&pdev->dev, res->start, size); - /* rx_pr("phy_addr = 0x%x, size = 0x%x, maped:%p\n", */ - /* reg_maps[i].phy_addr, size, reg_maps[i].p); */ + reg_maps[i].size = size; + rx_pr("phy_addr = 0x%x, size = 0x%x, maped:%p\n", + reg_maps[i].phy_addr, size, reg_maps[i].p); } return ret; } @@ -245,6 +263,11 @@ unsigned int rx_set_bits(unsigned int data, return ((value << first_bit_set(mask)) & mask) | (data & ~mask); } +bool hdmirx_repeat_support(void) +{ + return downstream_repeat_support; +} + /* * hdmirx_dec_support - check if given port is supported * @fe: frontend device of tvin interface @@ -333,9 +356,9 @@ void hdmirx_dec_close(struct tvin_frontend_s *fe) * txlx:dont disable the adc ref signal for audio pll(not * reset the vdac) to avoid noise issue */ - if (rx.chip_id == CHIP_ID_TXL) - vdac_enable(0, 0x10); - + /* For txl,also need to keep bandgap always on:SWPL-1224 */ + /* if (rx.hdmirxdev->data->chip_id == CHIP_ID_TXL) */ + /* vdac_enable(0, 0x10); */ /* open_flage = 0; */ rx.open_fg = 0; devp = container_of(fe, struct hdmirx_dev_s, frontend); @@ -925,14 +948,13 @@ static long hdmirx_ioctl(struct file *file, unsigned int cmd, case HDMI_IOC_HDCP_ON: hdcp_enable = 1; rx_set_cur_hpd(0); - fsm_restart(); + /*fsm_restart();*/ break; case HDMI_IOC_HDCP_OFF: hdcp_enable = 0; rx_set_cur_hpd(0); hdmirx_hw_config(); - hdmi_rx_top_edid_update(); - fsm_restart(); + /*fsm_restart();*/ break; case HDMI_IOC_EDID_UPDATE: if (rx.open_fg) { @@ -1341,11 +1363,100 @@ static ssize_t cec_get_state(struct device *dev, return 0; } -/* +static ssize_t hdcp_version_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + return sprintf(buf, "%x\n", rx.hdcp.hdcp_version); +} + +static ssize_t hdcp_version_store(struct device *dev, + struct device_attribute *attr, + const char *buf, + size_t count) +{ + return count; +} + +static ssize_t hw_info_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct hdcp_hw_info_s info; + + memset(&info, 0, sizeof(info)); + info.cur_5v = rx.cur_5v_sts; + info.open = rx.open_fg; + info.frame_rate = rx.pre.frame_rate/100; + info.signal_stable = ((rx.state == FSM_SIG_READY)?1:0); + return sprintf(buf, "%x\n", *((unsigned int *)&info)); +} + +static ssize_t hw_info_store(struct device *dev, + struct device_attribute *attr, + const char *buf, + size_t count) +{ + return count; +} + +static ssize_t edid_dw_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + return 0; +} + +static ssize_t edid_dw_store(struct device *dev, + struct device_attribute *attr, + const char *buf, + size_t count) +{ + int cnt = count; + + rx_pr("edid store len: %d\n", cnt); + rx_set_receiver_edid(buf, cnt); + + return count; +} + +static ssize_t ksvlist_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + return 0; +} + +static ssize_t ksvlist_store(struct device *dev, + struct device_attribute *attr, + const char *buf, + size_t count) +{ + int cnt; + /* unsigned long tmp; */ + unsigned char *hdcp = rx_get_dw_hdcp_addr(); + /* unsigned char t_tmp[3]; */ + cnt = count; + /* t_tmp[2] = '\0'; */ + rx_pr("dw hdcp %d,%d\n", cnt, sizeof(struct hdcp14_topo_s)); + /*for(i = 0;i < count/2;i++) { + * memcpy(t_tmp, buf + i*2, 2); + * if (kstrtoul(t_tmp, 16, &tmp)) + * rx_pr("ksvlist %s:\n", t_tmp); + * *(hdcp + i) = (unsigned char)tmp; + * rx_pr("%#x ", *(hdcp + i)); + *} + */ + memcpy(hdcp, buf, cnt); + rx_pr("\n"); + return count; +} + +/************************************* * val == 0 : cec disable * val == 1 : cec on * val == 2 : cec on && system startup - */ + **************************************/ static ssize_t cec_set_state(struct device *dev, struct device_attribute *attr, const char *buf, @@ -1445,6 +1556,25 @@ static ssize_t get_arc_aud_type(struct device *dev, return 0; } +static ssize_t set_reset_hdcp22(struct device *dev, + struct device_attribute *attr, + const char *buf, + size_t count) +{ + int reset; + + memcpy(&reset, buf, sizeof(reset)); + rx_pr("%s:%d\n", __func__, reset); + rx_reload_firm_reset(reset); + return count; +} + +static ssize_t get_reset_hdcp22(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + return 0; +} static DEVICE_ATTR(debug, 0644, hdmirx_debug_show, hdmirx_debug_store); static DEVICE_ATTR(edid, 0644, hdmirx_edid_show, hdmirx_edid_store); static DEVICE_ATTR(key, 0644, hdmirx_key_show, hdmirx_key_store); @@ -1455,7 +1585,11 @@ static DEVICE_ATTR(param, 0644, param_get_value, param_set_value); static DEVICE_ATTR(esm_base, 0644, esm_get_base, esm_set_base); static DEVICE_ATTR(info, 0644, show_info, store_info); static DEVICE_ATTR(arc_aud_type, 0644, get_arc_aud_type, set_arc_aud_type); - +static DEVICE_ATTR(reset22, 0644, get_reset_hdcp22, set_reset_hdcp22); +static DEVICE_ATTR(hdcp_version, 0644, hdcp_version_show, hdcp_version_store); +static DEVICE_ATTR(hw_info, 0644, hw_info_show, hw_info_store); +static DEVICE_ATTR(edid_dw, 0644, edid_dw_show, edid_dw_store); +static DEVICE_ATTR(ksvlist, 0644, ksvlist_show, ksvlist_store); static int hdmirx_add_cdev(struct cdev *cdevp, const struct file_operations *fops, @@ -1550,14 +1684,11 @@ static void rx_phy_suspend(void) if (hdmi_cec_en != 0) { if (suspend_pddq_sel == 2) { /* set rxsense pulse */ - hdmirx_phy_pddq(1); - mdelay(10); - hdmirx_phy_pddq(0); - mdelay(10); + rx_phy_rxsense_pulse(10, 10); } } /* phy powerdown */ - hdmirx_phy_pddq(1); + rx_phy_power_on(0); } } @@ -1569,10 +1700,7 @@ static void rx_phy_resume(void) * rxsense pulse and phy_int shottern than * 50ms, SDA may be pulled low 800ms on MTK box */ - hdmirx_phy_pddq(0); - msleep(20); - hdmirx_phy_pddq(1); - msleep(50); + rx_phy_rxsense_pulse(20, 50); } } hdmirx_phy_init(); @@ -1580,6 +1708,68 @@ static void rx_phy_resume(void) rx.boot_flag = true; } +void rx_emp_resource_allocate(struct device *dev) +{ + if (rx.hdmirxdev->data->chip_id == CHIP_ID_TL1) { + /* allocate buffer */ + rx.empbuff.storeA = kmalloc(EMP_BUFFER_SIZE, GFP_KERNEL); + if (rx.empbuff.storeA) + rx.empbuff.storeB = + rx.empbuff.storeA + (EMP_BUFFER_SIZE >> 1); + else + rx_pr("emp buff err-0\n"); + rx_pr("pktbuffa=0x%p\n", rx.empbuff.storeA); + rx_pr("pktbuffb=0x%p\n", rx.empbuff.storeB); + rx.empbuff.dump_mode = DUMP_MODE_EMP; + /* allocate buffer for hw access*/ + rx.empbuff.pg_addr = + dma_alloc_from_contiguous(dev, + EMP_BUFFER_SIZE >> PAGE_SHIFT, 0); + if (rx.empbuff.pg_addr) { + /* hw access */ + /* page to real address*/ + rx.empbuff.p_addr_a = + page_to_phys(rx.empbuff.pg_addr); + rx.empbuff.p_addr_b = + rx.empbuff.p_addr_a + (EMP_BUFFER_SIZE >> 1); + rx_pr("buffa paddr=0x%x\n", rx.empbuff.p_addr_a); + rx_pr("buffb paddr=0x%x\n", rx.empbuff.p_addr_b); + } else { + rx_pr("emp buff err-1\n"); + } + rx.empbuff.emppktcnt = 0; + } +} + +void rx_tmds_resource_allocate(struct device *dev) +{ + if (rx.hdmirxdev->data->chip_id == CHIP_ID_TL1) { + if (rx.empbuff.dump_mode == DUMP_MODE_EMP) { + if (rx.empbuff.pg_addr) { + dma_release_from_contiguous(dev, + rx.empbuff.pg_addr, + EMP_BUFFER_SIZE >> PAGE_SHIFT); + rx.empbuff.pg_addr = 0; + } + } else { + dma_release_from_contiguous(dev, rx.empbuff.pg_addr, + TMDS_BUFFER_SIZE >> PAGE_SHIFT); + rx.empbuff.pg_addr = 0; + } + + /* allocate buffer for tmds to ddr */ + rx.empbuff.pg_addr = + dma_alloc_from_contiguous(dev, + TMDS_BUFFER_SIZE >> PAGE_SHIFT, 0); + if (rx.empbuff.pg_addr) + rx.empbuff.p_addr_a = + page_to_phys(rx.empbuff.pg_addr); + + rx.empbuff.dump_mode = DUMP_MODE_TMDS; + rx_pr("buffa paddr=0x%x\n", rx.empbuff.p_addr_a); + } +} + #ifdef CONFIG_AMLOGIC_LEGACY_EARLY_SUSPEND static void hdmirx_early_suspend(struct early_suspend *h) { @@ -1640,11 +1830,17 @@ static int hdmirx_probe(struct platform_device *pdev) } memset(hdevp, 0, sizeof(struct hdmirx_dev_s)); hdevp->data = of_id->data; - if (hdevp->data) + rx.hdmirxdev = hdevp; + + if (hdevp->data) { rx.chip_id = hdevp->data->chip_id; - else + rx_pr("chip id:%d\n", rx.hdmirxdev->data->chip_id); + rx_pr("phy ver:%d\n", rx.hdmirxdev->data->phy_ver); + } else { /*txlx chip for default*/ rx.chip_id = CHIP_ID_TXLX; + rx_pr("err: hdevp->data null\n"); + } ret = rx_init_reg_map(pdev); if (ret < 0) { @@ -1731,6 +1927,32 @@ static int hdmirx_probe(struct platform_device *pdev) rx_pr("hdmirx: fail to create arc_aud_type file\n"); goto fail_create_arc_aud_type_file; } + ret = device_create_file(hdevp->dev, &dev_attr_reset22); + if (ret < 0) { + rx_pr("hdmirx: fail to create reset22 file\n"); + goto fail_create_reset22; + } + ret = device_create_file(hdevp->dev, &dev_attr_hdcp_version); + if (ret < 0) { + rx_pr("hdmirx: fail to create hdcp version file\n"); + goto fail_create_hdcp_version; + } + ret = device_create_file(hdevp->dev, &dev_attr_hw_info); + if (ret < 0) { + rx_pr("hdmirx: fail to create cur 5v file\n"); + goto fail_create_hw_info; + } + ret = device_create_file(hdevp->dev, &dev_attr_edid_dw); + if (ret < 0) { + rx_pr("hdmirx: fail to create edid_dw file\n"); + goto fail_create_edid_dw; + } + ret = device_create_file(hdevp->dev, &dev_attr_ksvlist); + if (ret < 0) { + rx_pr("hdmirx: fail to create ksvlist file\n"); + goto fail_create_ksvlist; + } + res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); if (!res) { rx_pr("%s: can't get irq resource\n", __func__); @@ -1816,8 +2038,8 @@ static int hdmirx_probe(struct platform_device *pdev) clk_rate = clk_get_rate(hdevp->skp_clk); } } - if ((rx.chip_id == CHIP_ID_TXLX) || - (rx.chip_id == CHIP_ID_TXHD)) { + if ((rx.hdmirxdev->data->chip_id == CHIP_ID_TXLX) || + (rx.hdmirxdev->data->chip_id == CHIP_ID_TXHD)) { tmds_clk_fs = clk_get(&pdev->dev, "hdmirx_aud_pll2fs"); if (IS_ERR(tmds_clk_fs)) rx_pr("get tmds_clk_fs err\n"); @@ -1869,8 +2091,8 @@ static int hdmirx_probe(struct platform_device *pdev) INIT_DELAYED_WORK(&esm_dwork, rx_hpd_to_esm_handle); /* queue_delayed_work(eq_wq, &eq_dwork, msecs_to_jiffies(5)); */ - repeater_wq = create_singlethread_workqueue(hdevp->frontend.name); - INIT_DELAYED_WORK(&repeater_dwork, repeater_dwork_handle); + /*repeater_wq = create_singlethread_workqueue(hdevp->frontend.name);*/ + /*INIT_DELAYED_WORK(&repeater_dwork, repeater_dwork_handle);*/ ret = of_property_read_u32(pdev->dev.of_node, "en_4k_2_2k", &en_4k_2_2k); @@ -1898,6 +2120,8 @@ static int hdmirx_probe(struct platform_device *pdev) disable_port_en = (disable_port >> 4) & 0x1; disable_port_num = disable_port & 0xF; } + + rx_emp_resource_allocate(&(pdev->dev)); hdmirx_hw_probe(); hdmirx_switch_pinmux(&(pdev->dev)); #ifdef CONFIG_AMLOGIC_LEGACY_EARLY_SUSPEND @@ -1919,6 +2143,16 @@ fail_kmalloc_pd_fifo: return ret; fail_get_resource_irq: return ret; +fail_create_ksvlist: + device_remove_file(hdevp->dev, &dev_attr_ksvlist); +fail_create_edid_dw: + device_remove_file(hdevp->dev, &dev_attr_edid_dw); +fail_create_hw_info: + device_remove_file(hdevp->dev, &dev_attr_hw_info); +fail_create_hdcp_version: + device_remove_file(hdevp->dev, &dev_attr_hdcp_version); +fail_create_reset22: + device_remove_file(hdevp->dev, &dev_attr_reset22); fail_create_arc_aud_type_file: device_remove_file(hdevp->dev, &dev_attr_arc_aud_type); fail_create_cec_file: @@ -1976,6 +2210,11 @@ static int hdmirx_remove(struct platform_device *pdev) device_remove_file(hdevp->dev, &dev_attr_esm_base); device_remove_file(hdevp->dev, &dev_attr_info); device_remove_file(hdevp->dev, &dev_attr_arc_aud_type); + device_remove_file(hdevp->dev, &dev_attr_ksvlist); + device_remove_file(hdevp->dev, &dev_attr_edid_dw); + device_remove_file(hdevp->dev, &dev_attr_hw_info); + device_remove_file(hdevp->dev, &dev_attr_hdcp_version); + device_remove_file(hdevp->dev, &dev_attr_reset22); tvin_unreg_frontend(&hdevp->frontend); hdmirx_delete_device(hdevp->index); tasklet_kill(&rx_tasklet); @@ -1992,7 +2231,8 @@ static int aml_hdcp22_pm_notify(struct notifier_block *nb, { int delay = 0; - if (event == PM_SUSPEND_PREPARE && hdcp22_on) { + if ((event == PM_SUSPEND_PREPARE) && hdcp22_on) { + rx_pr("PM_SUSPEND_PREPARE\n"); hdcp22_kill_esm = 1; /*wait time out ESM_KILL_WAIT_TIMES*20 ms*/ while (delay++ < ESM_KILL_WAIT_TIMES) { @@ -2000,10 +2240,15 @@ static int aml_hdcp22_pm_notify(struct notifier_block *nb, break; msleep(20); } - if (delay < ESM_KILL_WAIT_TIMES) + if (!hdcp22_kill_esm) rx_pr("hdcp22 kill ok!\n"); else rx_pr("hdcp22 kill timeout!\n"); + hdcp22_kill_esm = 0; + hdcp22_suspend(); + } else if ((event == PM_POST_SUSPEND) && hdcp22_on) { + rx_pr("PM_POST_SUSPEND\n"); + hdcp22_resume(); } return NOTIFY_OK; } @@ -2020,8 +2265,6 @@ static int hdmirx_suspend(struct platform_device *pdev, pm_message_t state) if (!early_suspend_flag) #endif rx_phy_suspend(); - if (hdcp22_on) - hdcp22_suspend(); rx_pr("hdmirx: suspend success\n"); return 0; } @@ -2037,8 +2280,7 @@ static int hdmirx_resume(struct platform_device *pdev) if (!early_suspend_flag) #endif rx_phy_resume(); - if (hdcp22_on) - hdcp22_resume(); + rx_pr("hdmirx: resume\n"); return 0; } @@ -2055,7 +2297,7 @@ static void hdmirx_shutdown(struct platform_device *pdev) if (!hdmi_cec_en) rx_set_port_hpd(ALL_PORTS, 0); /* phy powerdown */ - hdmirx_phy_pddq(1); + rx_phy_power_on(0); if (hdcp22_on) hdcp22_clk_en(0); rx_pr("[hdmirx]: shutdown success\n"); diff --git a/drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_drv.h b/drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_drv.h index be8cd8975647..b51798c975f8 100644 --- a/drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_drv.h +++ b/drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_drv.h @@ -34,19 +34,19 @@ #include "hdmi_rx_edid.h" -#define RX_VER0 "ver.2018-10-15" +#define RX_VER0 "ver.2018-11-8" /* * * * * */ -#define RX_VER1 "ver.2018/08/22" +#define RX_VER1 "ver.2018/10/22" /* * * */ -#define RX_VER2 "ver.2018/09/06" +#define RX_VER2 "ver.2018/10/30" /*print type*/ #define LOG_EN 0x01 @@ -85,10 +85,18 @@ enum chip_id_e { CHIP_ID_TXL, CHIP_ID_TXLX, CHIP_ID_TXHD, + CHIP_ID_TL1, +}; + +enum phy_ver_e { + PHY_VER_ORG, + PHY_VER_TL1, }; struct meson_hdmirx_data { enum chip_id_e chip_id; + enum phy_ver_e phy_ver; + struct ctrl *phyctrl; }; struct hdmirx_dev_s { @@ -250,10 +258,21 @@ struct rx_video_info { /** Encrypted keys size - 40 bits x 40 keys */ #define HDCP_KEYS_SIZE (2 * 40) +/*emp buffer config*/ +#define DUMP_MODE_EMP 0 +#define DUMP_MODE_TMDS 1 +#define TMDS_BUFFER_SIZE 0x1e00000 /*30M*/ +#define EMP_BUFFER_SIZE 0x200000 /*2M*/ +#define EMP_BUFF_MAC_PKT_CNT ((EMP_BUFFER_SIZE/2)/32 - 200) +#define TMDS_DATA_BUFFER_SIZE 0x200000 + + /** * @short HDMI RX controller HDCP configuration */ struct hdmi_rx_hdcp { + /*hdcp auth state*/ + enum repeater_state_e state; /** Repeater mode else receiver only */ bool repeat; bool cascade_exceed; @@ -335,8 +354,32 @@ struct aud_info_s { int real_sr; }; +struct phy_sts { + uint32_t cable_clk; + uint32_t tmds_clk; + uint32_t aud_div; + uint32_t pll_rate; + uint32_t clk_rate; + uint32_t phy_bw; +}; + +struct emp_buff { + unsigned int dump_mode; + struct page *pg_addr; + phys_addr_t p_addr_a; + phys_addr_t p_addr_b; + /*void __iomem *v_addr_a;*/ + /*void __iomem *v_addr_b;*/ + void __iomem *storeA; + void __iomem *storeB; + void __iomem *ready; + unsigned int emppktcnt; + unsigned long irqcnt; +}; + struct rx_s { enum chip_id_e chip_id; + struct hdmirx_dev_s *hdmirxdev; /** HDMI RX received signal changed */ uint8_t skip; /*avmute*/ @@ -353,6 +396,7 @@ struct rx_s { bool boot_flag; bool open_fg; uint8_t irq_flag; + bool firm_change;/*hdcp2.2 rp/rx switch time*/ /** HDMI RX controller HDCP configuration */ struct hdmi_rx_hdcp hdcp; /*report hpd status to app*/ @@ -384,6 +428,8 @@ struct rx_s { unsigned int pwr_sts; /* for debug */ /*struct pd_infoframe_s dbg_info;*/ + struct phy_sts physts; + struct emp_buff empbuff; }; struct _hdcp_ksv { @@ -409,6 +455,7 @@ extern struct tasklet_struct rx_tasklet; extern struct device *hdmirx_dev; extern struct rx_s rx; extern struct reg_map reg_maps[MAP_ADDR_MODULE_NUM]; +extern bool downstream_repeat_support; extern void rx_tasklet_handler(unsigned long arg); extern void skip_frame(unsigned int cnt); @@ -425,7 +472,7 @@ extern void rx_send_hpd_pulse(void); /* irq */ extern void rx_irq_en(bool enable); extern irqreturn_t irq_handler(int irq, void *params); -extern void cecrx_irq_handle(void); +extern void cecb_irq_handle(void); /* user interface */ extern int pc_mode_en; @@ -466,6 +513,7 @@ bool hdmirx_repeat_support(void); /* edid-hdcp14 */ extern unsigned int edid_update_flag; +extern unsigned int downstream_hpd_flag; extern void hdmirx_fill_edid_buf(const char *buf, int size); extern unsigned int hdmirx_read_edid_buf(char *buf, int max_size); diff --git a/drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_edid.c b/drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_edid.c index f689ee34a604..c94ee5bbea0a 100644 --- a/drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_edid.c +++ b/drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_edid.c @@ -30,9 +30,9 @@ #include /* Local include */ +#include "hdmi_rx_repeater.h" #include "hdmi_rx_drv.h" #include "hdmi_rx_edid.h" -#include "hdmi_rx_repeater.h" #include "hdmi_rx_hw.h" static unsigned char edid_temp[EDID_SIZE]; @@ -810,7 +810,7 @@ void rx_edid_update_audio_info(unsigned char *p_edid, { if (p_edid == NULL) return; - rx_modify_edid(p_edid, len, rx_get_receiver_edid()); + rx_modify_edid(p_edid, len, rx_get_dw_edid_addr()); } unsigned int rx_edid_cal_phy_addr( @@ -948,7 +948,7 @@ void rx_edid_fill_to_register( /* fill first edid buffer */ hdmirx_wr_top(TOP_EDID_OFFSET + i, pedid[i]); /* fill second edid buffer */ - hdmirx_wr_top(0x100+TOP_EDID_OFFSET + i, pedid[i]); + hdmirx_wr_top(TOP_EDID_OFFSET + 0x100 + i, pedid[i]); } /* caculate 4 port check sum */ if (brepeat) { @@ -1056,7 +1056,7 @@ unsigned char rx_parse_arc_aud_type(const unsigned char *buff) break; } if ((i < aud_length) && - ((aud_data & 0xff) == 1)) { + ((aud_data & 0x1) == 0x1)) { if (!need_support_atmos_bit) { need_support_atmos_bit = true; hdmi_rx_top_edid_update(); diff --git a/drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_eq.c b/drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_eq.c index 7b130b3106d5..31bbcd307ac0 100644 --- a/drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_eq.c +++ b/drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_eq.c @@ -36,6 +36,7 @@ #include #include /* Local include */ +#include "hdmi_rx_repeater.h" #include "hdmi_rx_eq.h" #include "hdmi_rx_drv.h" #include "hdmi_rx_hw.h" @@ -178,6 +179,12 @@ void eq_dwork_handler(struct work_struct *work) unsigned int i; cancel_delayed_work(&eq_dwork); + + /* for tl1 no SW eq */ + if (rx.hdmirxdev->data->chip_id == CHIP_ID_TL1) { + return; + } + for (i = 0; i < NTRYS; i++) { if (SettingFinder() == 1) { rx_pr("EQ-%d-%d-%d-", @@ -481,6 +488,12 @@ int rx_eq_algorithm(void) static uint8_t pre_eq_freq = 0xff; uint8_t pll_rate = hdmirx_rd_phy(PHY_MAINFSM_STATUS1) >> 9 & 3; + /* for tl1 no SW eq */ + if (rx.hdmirxdev->data->chip_id == CHIP_ID_TL1) { + eq_sts = E_EQ_FINISH; + return 1; + } + if (is_6g_mode()) pll_rate = E_EQ_6G; diff --git a/drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_hw.c b/drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_hw.c index f54f5a524d09..c36f4994326a 100644 --- a/drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_hw.c +++ b/drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_hw.c @@ -1,19 +1,19 @@ /* - * drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_hw.c - * - * Copyright (C) 2017 Amlogic, Inc. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - */ +* drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_hw.c +* +* Copyright (C) 2017 Amlogic, Inc. All rights reserved. +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License as published by +* the Free Software Foundation; either version 2 of the License, or +* (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, but WITHOUT +* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +* more details. +* +*/ #include #include @@ -38,6 +38,7 @@ #include /* Local include */ +#include "hdmi_rx_repeater.h" #include "hdmi_rx_drv.h" #include "hdmi_rx_hw.h" #include "hdmi_rx_edid.h" @@ -61,11 +62,11 @@ static bool phy_fsm_enhancement = true; unsigned int last_clk_rate; /* SNPS suggest to use the previous setting 0x3f when handle eq issues to - * make clk_stable bit more stable(=1),but 0x3f may misjudge 46.25~92.5 - * TMDSCLK as 25~46.25M TMDSCLK,pll_rate&REQUESTCLK will become - * not correct. so revert the setting to the default value 0x6 - * according to the PHY spec - */ +* make clk_stable bit more stable(=1),but 0x3f may misjudge 46.25~92.5 +* TMDSCLK as 25~46.25M TMDSCLK,pll_rate&REQUESTCLK will become +* not correct. so revert the setting to the default value 0x6 +* according to the PHY spec +*/ static uint8_t phy_lock_thres = 0x6; static uint32_t phy_cfg_clk = 24000; static uint32_t modet_clk = 24000; @@ -89,511 +90,611 @@ MODULE_PARM_DESC(hdcp22_on, "\n hdcp22_on\n"); module_param(hdcp22_on, int, 0664); /* - * hdcp14_key_mode:hdcp1.4 key handle method select - * NORMAL_MODE:systemcontrol path - * SECURE_MODE:secure OS path - */ +* hdcp14_key_mode:hdcp1.4 key handle method select +* NORMAL_MODE:systemcontrol path +* SECURE_MODE:secure OS path +*/ int hdcp14_key_mode = NORMAL_MODE; int aud_ch_map; - +int ignore_sscp_charerr = 1; +int ignore_sscp_tmds = 1; /*------------------------variable define end------------------------------*/ static int check_regmap_flag(unsigned int addr) { - return 1; +return 1; } /* - * hdmirx_rd_dwc - Read data from HDMI RX CTRL - * @addr: register address - * - * return data read value - */ +* hdmirx_rd_dwc - Read data from HDMI RX CTRL +* @addr: register address +* +* return data read value +*/ unsigned int hdmirx_rd_dwc(unsigned int addr) { - ulong flags; - int data; - unsigned long dev_offset = 0x10; +ulong flags; +int data; +unsigned long dev_offset = 0x10; +if (rx.hdmirxdev->data->chip_id == CHIP_ID_TL1) { + data = rd_reg(MAP_ADDR_MODULE_TOP, + addr + reg_maps[MAP_ADDR_MODULE_TOP].phy_addr); +} else { spin_lock_irqsave(®_rw_lock, flags); - wr_reg(MAP_ADDR_MODULE_TOP, hdmirx_addr_port | dev_offset, addr); - data = rd_reg(MAP_ADDR_MODULE_TOP, hdmirx_data_port | dev_offset); + wr_reg(MAP_ADDR_MODULE_TOP, + hdmirx_addr_port | dev_offset, addr); + data = rd_reg(MAP_ADDR_MODULE_TOP, + hdmirx_data_port | dev_offset); spin_unlock_irqrestore(®_rw_lock, flags); - return data; +} +return data; } /* - * hdmirx_rd_bits_dwc - read specfied bits of HDMI RX CTRL reg - * @addr: register address - * @mask: bits mask - * - * return masked bits of register value - */ +* hdmirx_rd_bits_dwc - read specfied bits of HDMI RX CTRL reg +* @addr: register address +* @mask: bits mask +* +* return masked bits of register value +*/ unsigned int hdmirx_rd_bits_dwc(unsigned int addr, unsigned int mask) { - return rx_get_bits(hdmirx_rd_dwc(addr), mask); +return rx_get_bits(hdmirx_rd_dwc(addr), mask); } /* - * hdmirx_wr_dwc - Write data to HDMI RX CTRL - * @addr: register address - * @data: new register value - */ +* hdmirx_wr_dwc - Write data to HDMI RX CTRL +* @addr: register address +* @data: new register value +*/ void hdmirx_wr_dwc(unsigned int addr, unsigned int data) { - ulong flags; - unsigned int dev_offset = 0x10; +ulong flags; +unsigned int dev_offset = 0x10; +if (rx.hdmirxdev->data->chip_id == CHIP_ID_TL1) { + wr_reg(MAP_ADDR_MODULE_TOP, + addr + reg_maps[MAP_ADDR_MODULE_TOP].phy_addr, data); +} else { spin_lock_irqsave(®_rw_lock, flags); - wr_reg(MAP_ADDR_MODULE_TOP, hdmirx_addr_port | dev_offset, addr); - wr_reg(MAP_ADDR_MODULE_TOP, hdmirx_data_port | dev_offset, data); + wr_reg(MAP_ADDR_MODULE_TOP, + hdmirx_addr_port | dev_offset, addr); + wr_reg(MAP_ADDR_MODULE_TOP, + hdmirx_data_port | dev_offset, data); spin_unlock_irqrestore(®_rw_lock, flags); } - -/* - * hdmirx_wr_bits_dwc - write specfied bits of HDMI RX CTRL reg - * @addr: register address - * @mask: bits mask - * @value: new register value - */ -void hdmirx_wr_bits_dwc(unsigned int addr, - unsigned int mask, unsigned int value) -{ - hdmirx_wr_dwc(addr, rx_set_bits(hdmirx_rd_dwc(addr), mask, value)); } /* - * hdmirx_rd_phy - Read data from HDMI RX phy - * @addr: register address - * - * return data read value - */ +* hdmirx_wr_bits_dwc - write specfied bits of HDMI RX CTRL reg +* @addr: register address +* @mask: bits mask +* @value: new register value +*/ +void hdmirx_wr_bits_dwc(unsigned int addr, +unsigned int mask, unsigned int value) +{ +hdmirx_wr_dwc(addr, rx_set_bits(hdmirx_rd_dwc(addr), mask, value)); +} + +/* +* hdmirx_rd_phy - Read data from HDMI RX phy +* @addr: register address +* +* return data read value +*/ unsigned int hdmirx_rd_phy(unsigned int reg_address) { - int cnt = 0; +int cnt = 0; - /* hdmirx_wr_dwc(DWC_I2CM_PHYG3_SLAVE, 0x39); */ - hdmirx_wr_dwc(DWC_I2CM_PHYG3_ADDRESS, reg_address); - hdmirx_wr_dwc(DWC_I2CM_PHYG3_OPERATION, 0x02); - do { - if ((cnt % 10) == 0) { - /* wait i2cmpdone */ - if (hdmirx_rd_dwc(DWC_HDMI_ISTS)&(1<<28)) { - hdmirx_wr_dwc(DWC_HDMI_ICLR, 1<<28); - break; - } - } - cnt++; - if (cnt > 50000) { - rx_pr("[HDMIRX err]: %s(%x,%x) timeout\n", - __func__, 0x39, reg_address); +/* hdmirx_wr_dwc(DWC_I2CM_PHYG3_SLAVE, 0x39); */ +hdmirx_wr_dwc(DWC_I2CM_PHYG3_ADDRESS, reg_address); +hdmirx_wr_dwc(DWC_I2CM_PHYG3_OPERATION, 0x02); +do { + if ((cnt % 10) == 0) { + /* wait i2cmpdone */ + if (hdmirx_rd_dwc(DWC_HDMI_ISTS)&(1<<28)) { + hdmirx_wr_dwc(DWC_HDMI_ICLR, 1<<28); break; } - } while (1); + } + cnt++; + if (cnt > 50000) { + rx_pr("[HDMIRX err]: %s(%x,%x) timeout\n", + __func__, 0x39, reg_address); + break; + } +} while (1); - return (unsigned int)(hdmirx_rd_dwc(DWC_I2CM_PHYG3_DATAI)); +return (unsigned int)(hdmirx_rd_dwc(DWC_I2CM_PHYG3_DATAI)); } /* - * hdmirx_rd_bits_phy - read specfied bits of HDMI RX phy reg - * @addr: register address - * @mask: bits mask - * - * return masked bits of register value - */ +* hdmirx_rd_bits_phy - read specfied bits of HDMI RX phy reg +* @addr: register address +* @mask: bits mask +* +* return masked bits of register value +*/ unsigned int hdmirx_rd_bits_phy(unsigned int addr, unsigned int mask) { - return rx_get_bits(hdmirx_rd_phy(addr), mask); +return rx_get_bits(hdmirx_rd_phy(addr), mask); } /* - * hdmirx_wr_phy - Write data to HDMI RX phy - * @addr: register address - * @data: new register value - * - * return 0 on write succeed, return -1 otherwise. - */ +* hdmirx_wr_phy - Write data to HDMI RX phy +* @addr: register address +* @data: new register value +* +* return 0 on write succeed, return -1 otherwise. +*/ unsigned int hdmirx_wr_phy(unsigned int reg_address, unsigned int data) { - int error = 0; - int cnt = 0; +int error = 0; +int cnt = 0; - /* hdmirx_wr_dwc(DWC_I2CM_PHYG3_SLAVE, 0x39); */ - hdmirx_wr_dwc(DWC_I2CM_PHYG3_ADDRESS, reg_address); - hdmirx_wr_dwc(DWC_I2CM_PHYG3_DATAO, data); - hdmirx_wr_dwc(DWC_I2CM_PHYG3_OPERATION, 0x01); +/* hdmirx_wr_dwc(DWC_I2CM_PHYG3_SLAVE, 0x39); */ +hdmirx_wr_dwc(DWC_I2CM_PHYG3_ADDRESS, reg_address); +hdmirx_wr_dwc(DWC_I2CM_PHYG3_DATAO, data); +hdmirx_wr_dwc(DWC_I2CM_PHYG3_OPERATION, 0x01); - do { - /* wait i2cmpdone */ - if ((cnt % 10) == 0) { - if (hdmirx_rd_dwc(DWC_HDMI_ISTS)&(1<<28)) { - hdmirx_wr_dwc(DWC_HDMI_ICLR, 1<<28); - break; - } - } - cnt++; - if (cnt > 50000) { - error = -1; - rx_pr("[err-%s]:(%x,%x)timeout\n", - __func__, reg_address, data); +do { + /* wait i2cmpdone */ + if ((cnt % 10) == 0) { + if (hdmirx_rd_dwc(DWC_HDMI_ISTS)&(1<<28)) { + hdmirx_wr_dwc(DWC_HDMI_ICLR, 1<<28); break; } - } while (1); - return error; + } + cnt++; + if (cnt > 50000) { + error = -1; + rx_pr("[err-%s]:(%x,%x)timeout\n", + __func__, reg_address, data); + break; + } +} while (1); +return error; } /* - * hdmirx_wr_bits_phy - write specfied bits of HDMI RX phy reg - * @addr: register address - * @mask: bits mask - * @value: new register value - * - * return 0 on write succeed, return -1 otherwise. - */ +* hdmirx_wr_bits_phy - write specfied bits of HDMI RX phy reg +* @addr: register address +* @mask: bits mask +* @value: new register value +* +* return 0 on write succeed, return -1 otherwise. +*/ int hdmirx_wr_bits_phy(uint16_t addr, uint32_t mask, uint32_t value) { - return hdmirx_wr_phy(addr, rx_set_bits(hdmirx_rd_phy(addr), - mask, value)); +return hdmirx_wr_phy(addr, rx_set_bits(hdmirx_rd_phy(addr), + mask, value)); } /* - * hdmirx_rd_top - read hdmirx top reg - * @addr: register address - * - * return data read value - */ +* hdmirx_rd_top - read hdmirx top reg +* @addr: register address +* +* return data read value +*/ unsigned int hdmirx_rd_top(unsigned int addr) { - ulong flags; - int data; - unsigned int dev_offset = 0; +ulong flags; +int data; +unsigned int dev_offset = 0; +unsigned int tempaddr = 0; +if (rx.hdmirxdev->data->chip_id == CHIP_ID_TL1) { + dev_offset = TOP_DWC_BASE_OFFSET + + reg_maps[MAP_ADDR_MODULE_TOP].phy_addr; + if ((addr >= TOP_EDID_OFFSET) && + (addr <= (TOP_EDID_OFFSET + 0x1ff))) { + /*edid address range*/ + tempaddr = TOP_EDID_ADDR_S + (addr - 0x200); + data = rd_reg_b(MAP_ADDR_MODULE_TOP, + dev_offset + tempaddr); + } else { + data = rd_reg(MAP_ADDR_MODULE_TOP, + dev_offset + (addr<<2)); + } +} else { spin_lock_irqsave(®_rw_lock, flags); - wr_reg(MAP_ADDR_MODULE_TOP, hdmirx_addr_port | dev_offset, addr); - wr_reg(MAP_ADDR_MODULE_TOP, hdmirx_addr_port | dev_offset, addr); - data = rd_reg(MAP_ADDR_MODULE_TOP, hdmirx_data_port | dev_offset); + wr_reg(MAP_ADDR_MODULE_TOP, + hdmirx_addr_port | dev_offset, addr); + data = rd_reg(MAP_ADDR_MODULE_TOP, + hdmirx_data_port | dev_offset); spin_unlock_irqrestore(®_rw_lock, flags); - return data; +} +return data; } /* - * hdmirx_rd_bits_top - read specified bits of hdmirx top reg - * @addr: register address - * @mask: bits mask - * - * return masked bits of register value - */ +* hdmirx_rd_bits_top - read specified bits of hdmirx top reg +* @addr: register address +* @mask: bits mask +* +* return masked bits of register value +*/ uint32_t hdmirx_rd_bits_top(uint16_t addr, uint32_t mask) { - return rx_get_bits(hdmirx_rd_top(addr), mask); +return rx_get_bits(hdmirx_rd_top(addr), mask); } /* - * hdmirx_wr_top - Write data to hdmirx top reg - * @addr: register address - * @data: new register value - */ +* hdmirx_wr_top - Write data to hdmirx top reg +* @addr: register address +* @data: new register value +*/ void hdmirx_wr_top(unsigned int addr, unsigned int data) { - ulong flags; - unsigned long dev_offset = 0; +ulong flags; +unsigned long dev_offset = 0; +unsigned int tempaddr = 0; +if (rx.hdmirxdev->data->chip_id == CHIP_ID_TL1) { + dev_offset = TOP_DWC_BASE_OFFSET + + reg_maps[MAP_ADDR_MODULE_TOP].phy_addr; + if ((addr >= TOP_EDID_OFFSET) && + (addr <= (TOP_EDID_OFFSET + 0x1ff))) { + /*edid address range*/ + tempaddr = TOP_EDID_ADDR_S + (addr - 0x200); + wr_reg_b(MAP_ADDR_MODULE_TOP, + dev_offset + tempaddr, (unsigned char)data); + } else { + wr_reg(MAP_ADDR_MODULE_TOP, + dev_offset + (addr<<2), data); + } +} else { spin_lock_irqsave(®_rw_lock, flags); - wr_reg(MAP_ADDR_MODULE_TOP, hdmirx_addr_port | dev_offset, addr); - wr_reg(MAP_ADDR_MODULE_TOP, hdmirx_data_port | dev_offset, data); + wr_reg(MAP_ADDR_MODULE_TOP, + hdmirx_addr_port | dev_offset, addr); + wr_reg(MAP_ADDR_MODULE_TOP, + hdmirx_data_port | dev_offset, data); spin_unlock_irqrestore(®_rw_lock, flags); } - -/* - * hdmirx_wr_bits_top - write specified bits of hdmirx top reg - * @addr: register address - * @mask: bits mask - * @value: new register value - */ -void hdmirx_wr_bits_top(unsigned int addr, - unsigned int mask, unsigned int value) -{ - hdmirx_wr_top(addr, rx_set_bits(hdmirx_rd_top(addr), mask, value)); } - /* - * rd_reg_hhi - * @offset: offset address of hhi physical addr - * - * returns unsigned int bytes read from the addr - */ - unsigned int rd_reg_hhi(unsigned int offset) - { - unsigned int addr = offset + - reg_maps[MAP_ADDR_MODULE_HIU].phy_addr; - - return rd_reg(MAP_ADDR_MODULE_HIU, addr); - } - - /* - * wr_reg_hhi - * @offset: offset address of hhi physical addr - * @val: value being written - */ - void wr_reg_hhi(unsigned int offset, unsigned int val) - { - unsigned int addr = offset + - reg_maps[MAP_ADDR_MODULE_HIU].phy_addr; - wr_reg(MAP_ADDR_MODULE_HIU, addr, val); - } - - /* - * rd_reg - regisger read - * @module: module index of the reg_map table - * @reg_addr: offset address of specified phy addr - * - * returns unsigned int bytes read from the addr - */ - unsigned int rd_reg(enum map_addr_module_e module, - unsigned int reg_addr) - { - unsigned int val = 0; - - if ((module < MAP_ADDR_MODULE_NUM) - && check_regmap_flag(reg_addr)) - val = readl(reg_maps[module].p + - (reg_addr - reg_maps[module].phy_addr)); - else - rx_pr("rd reg %x error\n", reg_addr); - return val; - } - - /* - * wr_reg - regisger write - * @module: module index of the reg_map table - * @reg_addr: offset address of specified phy addr - * @val: value being written - */ - void wr_reg(enum map_addr_module_e module, - unsigned int reg_addr, unsigned int val) - { - if ((module < MAP_ADDR_MODULE_NUM) - && check_regmap_flag(reg_addr)) - writel(val, reg_maps[module].p + - (reg_addr - reg_maps[module].phy_addr)); - else - rx_pr("wr reg %x err\n", reg_addr); - } +/* +* hdmirx_wr_bits_top - write specified bits of hdmirx top reg +* @addr: register address +* @mask: bits mask +* @value: new register value +*/ +void hdmirx_wr_bits_top(unsigned int addr, +unsigned int mask, unsigned int value) +{ +hdmirx_wr_top(addr, rx_set_bits(hdmirx_rd_top(addr), mask, value)); +} /* - * rx_hdcp22_wr_only - */ +* rd_reg_hhi +* @offset: offset address of hhi physical addr +* +* returns unsigned int bytes read from the addr +*/ +unsigned int rd_reg_hhi(unsigned int offset) +{ +unsigned int addr = offset + + reg_maps[MAP_ADDR_MODULE_HIU].phy_addr; + +return rd_reg(MAP_ADDR_MODULE_HIU, addr); +} + +/* +* wr_reg_hhi +* @offset: offset address of hhi physical addr +* @val: value being written +*/ +void wr_reg_hhi(unsigned int offset, unsigned int val) +{ +unsigned int addr = offset + + reg_maps[MAP_ADDR_MODULE_HIU].phy_addr; +wr_reg(MAP_ADDR_MODULE_HIU, addr, val); +} + +/* +* rd_reg - regisger read +* @module: module index of the reg_map table +* @reg_addr: offset address of specified phy addr +* +* returns unsigned int bytes read from the addr +*/ +unsigned int rd_reg(enum map_addr_module_e module, +unsigned int reg_addr) +{ +unsigned int val = 0; + +if ((module < MAP_ADDR_MODULE_NUM) + && check_regmap_flag(reg_addr)) + val = readl(reg_maps[module].p + + (reg_addr - reg_maps[module].phy_addr)); +else + rx_pr("rd reg %x error,md %d\n", reg_addr, module); +return val; +} + +/* +* wr_reg - regisger write +* @module: module index of the reg_map table +* @reg_addr: offset address of specified phy addr +* @val: value being written +*/ +void wr_reg(enum map_addr_module_e module, + unsigned int reg_addr, unsigned int val) +{ +if ((module < MAP_ADDR_MODULE_NUM) + && check_regmap_flag(reg_addr)) + writel(val, reg_maps[module].p + + (reg_addr - reg_maps[module].phy_addr)); +else + rx_pr("wr reg %x err\n", reg_addr); +} + +/* +* rd_reg_b - regisger read byte mode +* @module: module index of the reg_map table +* @reg_addr: offset address of specified phy addr +* +* returns unsigned char bytes read from the addr +*/ +unsigned char rd_reg_b(enum map_addr_module_e module, +unsigned char reg_addr) +{ +unsigned char val = 0; + +if ((module < MAP_ADDR_MODULE_NUM) + && check_regmap_flag(reg_addr)) + val = readb(reg_maps[module].p + + (reg_addr - reg_maps[module].phy_addr)); +else + rx_pr("rd reg %x error,md %d\n", reg_addr, module); +return val; +} + +/* +* wr_reg_b - regisger write byte mode +* @module: module index of the reg_map table +* @reg_addr: offset address of specified phy addr +* @val: value being written +*/ +void wr_reg_b(enum map_addr_module_e module, + unsigned int reg_addr, unsigned char val) +{ +if ((module < MAP_ADDR_MODULE_NUM) + && check_regmap_flag(reg_addr)) + writeb(val, reg_maps[module].p + + (reg_addr - reg_maps[module].phy_addr)); +else + rx_pr("wr reg %x err\n", reg_addr); +} + + +/* +* rx_hdcp22_wr_only +*/ void rx_hdcp22_wr_only(unsigned int addr, unsigned int data) { - unsigned long flags; +unsigned long flags; - spin_lock_irqsave(®_rw_lock, flags); - wr_reg(MAP_ADDR_MODULE_HDMIRX_CAPB3, - reg_maps[MAP_ADDR_MODULE_HDMIRX_CAPB3].phy_addr | addr, - data); - spin_unlock_irqrestore(®_rw_lock, flags); +spin_lock_irqsave(®_rw_lock, flags); +wr_reg(MAP_ADDR_MODULE_HDMIRX_CAPB3, +reg_maps[MAP_ADDR_MODULE_HDMIRX_CAPB3].phy_addr | addr, +data); +spin_unlock_irqrestore(®_rw_lock, flags); } unsigned int rx_hdcp22_rd(unsigned int addr) { - unsigned int data; - unsigned long flags; +unsigned int data; +unsigned long flags; - spin_lock_irqsave(®_rw_lock, flags); - data = rd_reg(MAP_ADDR_MODULE_HDMIRX_CAPB3, - reg_maps[MAP_ADDR_MODULE_HDMIRX_CAPB3].phy_addr | addr); - spin_unlock_irqrestore(®_rw_lock, flags); - return data; +spin_lock_irqsave(®_rw_lock, flags); +data = rd_reg(MAP_ADDR_MODULE_HDMIRX_CAPB3, +reg_maps[MAP_ADDR_MODULE_HDMIRX_CAPB3].phy_addr | addr); +spin_unlock_irqrestore(®_rw_lock, flags); +return data; } void rx_hdcp22_rd_check(unsigned int addr, - unsigned int exp_data, unsigned int mask) +unsigned int exp_data, unsigned int mask) { - unsigned int rd_data; +unsigned int rd_data; - rd_data = rx_hdcp22_rd(addr); - if ((rd_data | mask) != (exp_data | mask)) - rx_pr("addr=0x%02x rd_data=0x%08x\n", addr, rd_data); +rd_data = rx_hdcp22_rd(addr); +if ((rd_data | mask) != (exp_data | mask)) + rx_pr("addr=0x%02x rd_data=0x%08x\n", addr, rd_data); } void rx_hdcp22_wr(unsigned int addr, unsigned int data) { - rx_hdcp22_wr_only(addr, data); - rx_hdcp22_rd_check(addr, data, 0); +rx_hdcp22_wr_only(addr, data); +rx_hdcp22_rd_check(addr, data, 0); } /* - * rx_hdcp22_rd_reg - hdcp2.2 reg write - * @addr: register address - * @value: new register value - */ +* rx_hdcp22_rd_reg - hdcp2.2 reg write +* @addr: register address +* @value: new register value +*/ void rx_hdcp22_wr_reg(unsigned int addr, unsigned int data) { - rx_sec_reg_write((unsigned int *)(unsigned long) - (reg_maps[MAP_ADDR_MODULE_HDMIRX_CAPB3].phy_addr + addr), - data); +rx_sec_reg_write((unsigned int *)(unsigned long) +(reg_maps[MAP_ADDR_MODULE_HDMIRX_CAPB3].phy_addr + addr), +data); } /* - * rx_hdcp22_rd_reg - hdcp2.2 reg read - * @addr: register address - */ +* rx_hdcp22_rd_reg - hdcp2.2 reg read +* @addr: register address +*/ unsigned int rx_hdcp22_rd_reg(unsigned int addr) { - return (uint32_t)rx_sec_reg_read((unsigned int *)(unsigned long) - (reg_maps[MAP_ADDR_MODULE_HDMIRX_CAPB3].phy_addr + addr)); +return (uint32_t)rx_sec_reg_read((unsigned int *)(unsigned long) +(reg_maps[MAP_ADDR_MODULE_HDMIRX_CAPB3].phy_addr + addr)); } /* - * rx_hdcp22_rd_reg_bits - hdcp2.2 reg masked bits read - * @addr: register address - * @mask: bits mask - */ +* rx_hdcp22_rd_reg_bits - hdcp2.2 reg masked bits read +* @addr: register address +* @mask: bits mask +*/ unsigned int rx_hdcp22_rd_reg_bits(unsigned int addr, unsigned int mask) { - return rx_get_bits(rx_hdcp22_rd_reg(addr), mask); +return rx_get_bits(rx_hdcp22_rd_reg(addr), mask); } /* - * rx_hdcp22_wr_reg_bits - hdcp2.2 reg masked bits write - * @addr: register address - * @mask: bits mask - * @value: new register value - */ +* rx_hdcp22_wr_reg_bits - hdcp2.2 reg masked bits write +* @addr: register address +* @mask: bits mask +* @value: new register value +*/ void rx_hdcp22_wr_reg_bits(unsigned int addr, - unsigned int mask, unsigned int value) +unsigned int mask, unsigned int value) { - rx_hdcp22_wr_reg(addr, rx_set_bits(rx_hdcp22_rd_reg(addr), - mask, value)); +rx_hdcp22_wr_reg(addr, rx_set_bits(rx_hdcp22_rd_reg(addr), + mask, value)); } /* - * hdcp22_wr_top - hdcp2.2 top reg write - * @addr: register address - * @data: new register value - */ +* hdcp22_wr_top - hdcp2.2 top reg write +* @addr: register address +* @data: new register value +*/ void rx_hdcp22_wr_top(unsigned int addr, unsigned int data) { - sec_top_write((unsigned int *)(unsigned long)addr, data); +sec_top_write((unsigned int *)(unsigned long)addr, data); } /* - * hdcp22_rd_top - hdcp2.2 top reg read - * @addr: register address - */ +* hdcp22_rd_top - hdcp2.2 top reg read +* @addr: register address +*/ unsigned int rx_hdcp22_rd_top(uint32_t addr) { - return (unsigned int)sec_top_read((unsigned int *)(unsigned long)addr); +return (unsigned int)sec_top_read((unsigned int *)(unsigned long)addr); } /* - * sec_top_write - secure top write - */ +* sec_top_write - secure top write +*/ void sec_top_write(unsigned int *addr, unsigned int value) { - struct arm_smccc_res res; +struct arm_smccc_res res; - arm_smccc_smc(HDMIRX_WR_SEC_TOP, (unsigned long)(uintptr_t)addr, - value, 0, 0, 0, 0, 0, &res); -} - -/* - * sec_top_read - secure top read - */ -unsigned int sec_top_read(unsigned int *addr) -{ - struct arm_smccc_res res; - - arm_smccc_smc(HDMIRX_RD_SEC_TOP, (unsigned long)(uintptr_t)addr, - 0, 0, 0, 0, 0, 0, &res); - - return (unsigned int)((res.a0)&0xffffffff); -} - -/* - * rx_sec_reg_write - secure region write - */ -void rx_sec_reg_write(unsigned int *addr, unsigned int value) -{ - struct arm_smccc_res res; - - arm_smccc_smc(HDCP22_RX_ESM_WRITE, (unsigned long)(uintptr_t)addr, +arm_smccc_smc(HDMIRX_WR_SEC_TOP, (unsigned long)(uintptr_t)addr, value, 0, 0, 0, 0, 0, &res); } /* - * rx_sec_reg_read - secure region read - */ +* sec_top_read - secure top read +*/ +unsigned int sec_top_read(unsigned int *addr) +{ +struct arm_smccc_res res; + +arm_smccc_smc(HDMIRX_RD_SEC_TOP, (unsigned long)(uintptr_t)addr, + 0, 0, 0, 0, 0, 0, &res); + +return (unsigned int)((res.a0)&0xffffffff); +} + +/* +* rx_sec_reg_write - secure region write +*/ +void rx_sec_reg_write(unsigned int *addr, unsigned int value) +{ +struct arm_smccc_res res; + +arm_smccc_smc(HDCP22_RX_ESM_WRITE, (unsigned long)(uintptr_t)addr, + value, 0, 0, 0, 0, 0, &res); +} + +/* +* rx_sec_reg_read - secure region read +*/ unsigned int rx_sec_reg_read(unsigned int *addr) { - struct arm_smccc_res res; +struct arm_smccc_res res; - arm_smccc_smc(HDCP22_RX_ESM_READ, (unsigned long)(uintptr_t)addr, - 0, 0, 0, 0, 0, 0, &res); +arm_smccc_smc(HDCP22_RX_ESM_READ, (unsigned long)(uintptr_t)addr, + 0, 0, 0, 0, 0, 0, &res); - return (unsigned int)((res.a0)&0xffffffff); +return (unsigned int)((res.a0)&0xffffffff); } /* * rx_sec_set_duk */ -unsigned int rx_sec_set_duk(void) +unsigned int rx_sec_set_duk(bool repeater) { - struct arm_smccc_res res; +struct arm_smccc_res res; - arm_smccc_smc(HDCP22_RX_SET_DUK_KEY, 0, 0, 0, 0, 0, 0, 0, &res); + if (repeater) + arm_smccc_smc(HDCP22_RP_SET_DUK_KEY, 0, 0, 0, 0, 0, 0, 0, &res); + else + arm_smccc_smc(HDCP22_RX_SET_DUK_KEY, 0, 0, 0, 0, 0, 0, 0, &res); return (unsigned int)((res.a0)&0xffffffff); } /* - * rx_set_hdcp14_secure_key - */ +* rx_set_hdcp14_secure_key +*/ unsigned int rx_set_hdcp14_secure_key(void) { - struct arm_smccc_res res; +struct arm_smccc_res res; - /* 0x8200002d is the SMC cmd defined in BL31,this CMD - * will call set hdcp1.4 key function - */ - arm_smccc_smc(HDCP14_RX_SETKEY, 0, 0, 0, 0, 0, 0, 0, &res); +/* 0x8200002d is the SMC cmd defined in BL31,this CMD + * will call set hdcp1.4 key function + */ +arm_smccc_smc(HDCP14_RX_SETKEY, 0, 0, 0, 0, 0, 0, 0, &res); - return (unsigned int)((res.a0)&0xffffffff); +return (unsigned int)((res.a0)&0xffffffff); } /* - * hdmirx_phy_pddq - phy pddq config - * @enable: enable phy pddq up - */ +* hdmirx_phy_pddq - phy pddq config +* @enable: enable phy pddq up +*/ void hdmirx_phy_pddq(unsigned int enable) { - hdmirx_wr_bits_dwc(DWC_SNPS_PHYG3_CTRL, - MSK(1, 1), enable); +hdmirx_wr_bits_dwc(DWC_SNPS_PHYG3_CTRL, + MSK(1, 1), enable); } /* - * hdmirx_wr_ctl_port - */ +* hdmirx_wr_ctl_port +*/ void hdmirx_wr_ctl_port(unsigned int offset, unsigned int data) { - unsigned long flags; - +unsigned long flags; +if (rx.hdmirxdev->data->chip_id == CHIP_ID_TL1) { + /* ??? */ +} else { spin_lock_irqsave(®_rw_lock, flags); wr_reg(MAP_ADDR_MODULE_TOP, hdmirx_ctrl_port+offset, data); spin_unlock_irqrestore(®_rw_lock, flags); } +} /* - * hdmirx_top_sw_reset - */ +* hdmirx_top_sw_reset +*/ void hdmirx_top_sw_reset(void) { - ulong flags; - unsigned long dev_offset = 0; +ulong flags; +unsigned long dev_offset = 0; - spin_lock_irqsave(®_rw_lock, flags); +spin_lock_irqsave(®_rw_lock, flags); +if (rx.hdmirxdev->data->chip_id == CHIP_ID_TL1) { + hdmirx_wr_top(TOP_SW_RESET, 1); + udelay(1); + hdmirx_wr_top(TOP_SW_RESET, 0); +} else { wr_reg(MAP_ADDR_MODULE_TOP, hdmirx_addr_port | dev_offset, TOP_SW_RESET); wr_reg(MAP_ADDR_MODULE_TOP, @@ -601,614 +702,675 @@ void hdmirx_top_sw_reset(void) udelay(1); wr_reg(MAP_ADDR_MODULE_TOP, hdmirx_addr_port | dev_offset, TOP_SW_RESET); - wr_reg(MAP_ADDR_MODULE_TOP, hdmirx_data_port | dev_offset, 0); - spin_unlock_irqrestore(®_rw_lock, flags); + wr_reg(MAP_ADDR_MODULE_TOP, + hdmirx_data_port | dev_offset, 0); +} +spin_unlock_irqrestore(®_rw_lock, flags); } /* - * rx_irq_en - hdmirx controller irq config - * @enable - irq set or clear - */ +* rx_irq_en - hdmirx controller irq config +* @enable - irq set or clear +*/ void rx_irq_en(bool enable) { - unsigned int data32 = 0; +unsigned int data32 = 0; - if (enable) { - if (rx.chip_id == CHIP_ID_TXLX) { - data32 |= 1 << 31; /* DRC_CKS_CHG */ - data32 |= 1 << 30; /* DRC_RCV */ - data32 |= 0 << 29; /* AUD_TYPE_CHG */ - data32 |= 0 << 28; /* DVI_DET */ - data32 |= 1 << 27; /* VSI_CKS_CHG */ - data32 |= 0 << 26; /* GMD_CKS_CHG */ - data32 |= 0 << 25; /* AIF_CKS_CHG */ - data32 |= 1 << 24; /* AVI_CKS_CHG */ - data32 |= 0 << 23; /* ACR_N_CHG */ - data32 |= 0 << 22; /* ACR_CTS_CHG */ - data32 |= 1 << 21; /* GCP_AV_MUTE_CHG */ - data32 |= 0 << 20; /* GMD_RCV */ - data32 |= 0 << 19; /* AIF_RCV */ - data32 |= 0 << 18; /* AVI_RCV */ - data32 |= 0 << 17; /* ACR_RCV */ - data32 |= 0 << 16; /* GCP_RCV */ - data32 |= 1 << 15; /* VSI_RCV */ - data32 |= 0 << 14; /* AMP_RCV */ - data32 |= 0 << 13; /* AMP_CHG */ - data32 |= 0 << 8; /* PD_FIFO_NEW_ENTRY */ - data32 |= 0 << 4; /* PD_FIFO_OVERFL */ - data32 |= 0 << 3; /* PD_FIFO_UNDERFL */ - data32 |= 0 << 2; /* PD_FIFO_TH_START_PASS */ - data32 |= 0 << 1; /* PD_FIFO_TH_MAX_PASS */ - data32 |= 0 << 0; /* PD_FIFO_TH_MIN_PASS */ - data32 |= pdec_ists_en; - } else if (rx.chip_id == CHIP_ID_TXHD) { - /* data32 |= 1 << 31; DRC_CKS_CHG */ - /* data32 |= 1 << 30; DRC_RCV */ - data32 |= 0 << 29; /* AUD_TYPE_CHG */ - data32 |= 0 << 28; /* DVI_DET */ - data32 |= 1 << 27; /* VSI_CKS_CHG */ - data32 |= 0 << 26; /* GMD_CKS_CHG */ - data32 |= 0 << 25; /* AIF_CKS_CHG */ - data32 |= 1 << 24; /* AVI_CKS_CHG */ - data32 |= 0 << 23; /* ACR_N_CHG */ - data32 |= 0 << 22; /* ACR_CTS_CHG */ - data32 |= 1 << 21; /* GCP_AV_MUTE_CHG */ - data32 |= 0 << 20; /* GMD_RCV */ - data32 |= 0 << 19; /* AIF_RCV */ - data32 |= 0 << 18; /* AVI_RCV */ - data32 |= 0 << 17; /* ACR_RCV */ - data32 |= 0 << 16; /* GCP_RCV */ - data32 |= 1 << 15; /* VSI_RCV */ - /* data32 |= 0 << 14; AMP_RCV */ - /* data32 |= 0 << 13; AMP_CHG */ - data32 |= 0 << 8; /* PD_FIFO_NEW_ENTRY */ - data32 |= 0 << 4; /* PD_FIFO_OVERFL */ - data32 |= 0 << 3; /* PD_FIFO_UNDERFL */ - data32 |= 0 << 2; /* PD_FIFO_TH_START_PASS */ - data32 |= 0 << 1; /* PD_FIFO_TH_MAX_PASS */ - data32 |= 0 << 0; /* PD_FIFO_TH_MIN_PASS */ - data32 |= pdec_ists_en; - } else { /* TXL and previous Chip */ - data32 = 0; - data32 |= 0 << 29; /* AUD_TYPE_CHG */ - data32 |= 0 << 28; /* DVI_DET */ - data32 |= 1 << 27; /* VSI_CKS_CHG */ - data32 |= 0 << 26; /* GMD_CKS_CHG */ - data32 |= 0 << 25; /* AIF_CKS_CHG */ - data32 |= 1 << 24; /* AVI_CKS_CHG */ - data32 |= 0 << 23; /* ACR_N_CHG */ - data32 |= 0 << 22; /* ACR_CTS_CHG */ - data32 |= 1 << 21; /* GCP_AV_MUTE_CHG */ - data32 |= 0 << 20; /* GMD_RCV */ - data32 |= 0 << 19; /* AIF_RCV */ - data32 |= 0 << 18; /* AVI_RCV */ - data32 |= 0 << 17; /* ACR_RCV */ - data32 |= 0 << 16; /* GCP_RCV */ - data32 |= 0 << 15; /* VSI_RCV */ - data32 |= 0 << 14; /* AMP_RCV */ - data32 |= 0 << 13; /* AMP_CHG */ - /* diff */ - data32 |= 1 << 10; /* DRC_CKS_CHG */ - data32 |= 1 << 9; /* DRC_RCV */ - /* diff */ - data32 |= 0 << 8; /* PD_FIFO_NEW_ENTRY */ - data32 |= 0 << 4; /* PD_FIFO_OVERFL */ - data32 |= 0 << 3; /* PD_FIFO_UNDERFL */ - data32 |= 0 << 2; /* PD_FIFO_TH_START_PASS */ - data32 |= 0 << 1; /* PD_FIFO_TH_MAX_PASS */ - data32 |= 0 << 0; /* PD_FIFO_TH_MIN_PASS */ - data32 |= pdec_ists_en; - } - hdmirx_wr_dwc(DWC_PDEC_IEN_SET, data32); - hdmirx_wr_dwc(DWC_AUD_FIFO_IEN_SET, OVERFL|UNDERFL); - } else { - /* clear enable */ - hdmirx_wr_dwc(DWC_PDEC_IEN_CLR, ~0); - hdmirx_wr_dwc(DWC_AUD_CEC_IEN_CLR, ~0); - hdmirx_wr_dwc(DWC_AUD_FIFO_IEN_CLR, ~0); - hdmirx_wr_dwc(DWC_MD_IEN_CLR, ~0); - /* clear status */ - hdmirx_wr_dwc(DWC_PDEC_ICLR, ~0); - hdmirx_wr_dwc(DWC_AUD_CEC_ICLR, ~0); - hdmirx_wr_dwc(DWC_AUD_FIFO_ICLR, ~0); - hdmirx_wr_dwc(DWC_MD_ICLR, ~0); +if (enable) { + if (rx.chip_id == CHIP_ID_TL1) { + data32 |= 1 << 31; /* DRC_CKS_CHG */ + data32 |= 1 << 30; /* DRC_RCV */ + data32 |= 0 << 29; /* AUD_TYPE_CHG */ + data32 |= 0 << 28; /* DVI_DET */ + data32 |= 1 << 27; /* VSI_CKS_CHG */ + data32 |= 0 << 26; /* GMD_CKS_CHG */ + data32 |= 0 << 25; /* AIF_CKS_CHG */ + data32 |= 1 << 24; /* AVI_CKS_CHG */ + data32 |= 0 << 23; /* ACR_N_CHG */ + data32 |= 0 << 22; /* ACR_CTS_CHG */ + data32 |= 1 << 21; /* GCP_AV_MUTE_CHG */ + data32 |= 0 << 20; /* GMD_RCV */ + data32 |= 0 << 19; /* AIF_RCV */ + data32 |= 0 << 18; /* AVI_RCV */ + data32 |= 0 << 17; /* ACR_RCV */ + data32 |= 0 << 16; /* GCP_RCV */ + data32 |= 1 << 15; /* VSI_RCV */ + data32 |= 0 << 14; /* AMP_RCV */ + data32 |= 0 << 13; /* AMP_CHG */ + data32 |= 1 << 9; /* EMP_RCV*/ + data32 |= 0 << 8; /* PD_FIFO_NEW_ENTRY */ + data32 |= 0 << 4; /* PD_FIFO_OVERFL */ + data32 |= 0 << 3; /* PD_FIFO_UNDERFL */ + data32 |= 0 << 2; /* PD_FIFO_TH_START_PASS */ + data32 |= 0 << 1; /* PD_FIFO_TH_MAX_PASS */ + data32 |= 0 << 0; /* PD_FIFO_TH_MIN_PASS */ + data32 |= pdec_ists_en; + } else if (rx.chip_id == CHIP_ID_TXLX) { + data32 |= 1 << 31; /* DRC_CKS_CHG */ + data32 |= 1 << 30; /* DRC_RCV */ + data32 |= 0 << 29; /* AUD_TYPE_CHG */ + data32 |= 0 << 28; /* DVI_DET */ + data32 |= 1 << 27; /* VSI_CKS_CHG */ + data32 |= 0 << 26; /* GMD_CKS_CHG */ + data32 |= 0 << 25; /* AIF_CKS_CHG */ + data32 |= 1 << 24; /* AVI_CKS_CHG */ + data32 |= 0 << 23; /* ACR_N_CHG */ + data32 |= 0 << 22; /* ACR_CTS_CHG */ + data32 |= 1 << 21; /* GCP_AV_MUTE_CHG */ + data32 |= 0 << 20; /* GMD_RCV */ + data32 |= 0 << 19; /* AIF_RCV */ + data32 |= 0 << 18; /* AVI_RCV */ + data32 |= 0 << 17; /* ACR_RCV */ + data32 |= 0 << 16; /* GCP_RCV */ + data32 |= 1 << 15; /* VSI_RCV */ + data32 |= 0 << 14; /* AMP_RCV */ + data32 |= 0 << 13; /* AMP_CHG */ + data32 |= 0 << 8; /* PD_FIFO_NEW_ENTRY */ + data32 |= 0 << 4; /* PD_FIFO_OVERFL */ + data32 |= 0 << 3; /* PD_FIFO_UNDERFL */ + data32 |= 0 << 2; /* PD_FIFO_TH_START_PASS */ + data32 |= 0 << 1; /* PD_FIFO_TH_MAX_PASS */ + data32 |= 0 << 0; /* PD_FIFO_TH_MIN_PASS */ + data32 |= pdec_ists_en; + } else if (rx.chip_id == CHIP_ID_TXHD) { + /* data32 |= 1 << 31; DRC_CKS_CHG */ + /* data32 |= 1 << 30; DRC_RCV */ + data32 |= 0 << 29; /* AUD_TYPE_CHG */ + data32 |= 0 << 28; /* DVI_DET */ + data32 |= 1 << 27; /* VSI_CKS_CHG */ + data32 |= 0 << 26; /* GMD_CKS_CHG */ + data32 |= 0 << 25; /* AIF_CKS_CHG */ + data32 |= 1 << 24; /* AVI_CKS_CHG */ + data32 |= 0 << 23; /* ACR_N_CHG */ + data32 |= 0 << 22; /* ACR_CTS_CHG */ + data32 |= 1 << 21; /* GCP_AV_MUTE_CHG */ + data32 |= 0 << 20; /* GMD_RCV */ + data32 |= 0 << 19; /* AIF_RCV */ + data32 |= 0 << 18; /* AVI_RCV */ + data32 |= 0 << 17; /* ACR_RCV */ + data32 |= 0 << 16; /* GCP_RCV */ + data32 |= 1 << 15; /* VSI_RCV */ + /* data32 |= 0 << 14; AMP_RCV */ + /* data32 |= 0 << 13; AMP_CHG */ + data32 |= 0 << 8; /* PD_FIFO_NEW_ENTRY */ + data32 |= 0 << 4; /* PD_FIFO_OVERFL */ + data32 |= 0 << 3; /* PD_FIFO_UNDERFL */ + data32 |= 0 << 2; /* PD_FIFO_TH_START_PASS */ + data32 |= 0 << 1; /* PD_FIFO_TH_MAX_PASS */ + data32 |= 0 << 0; /* PD_FIFO_TH_MIN_PASS */ + data32 |= pdec_ists_en; + } else { /* TXL and previous Chip */ + data32 = 0; + data32 |= 0 << 29; /* AUD_TYPE_CHG */ + data32 |= 0 << 28; /* DVI_DET */ + data32 |= 1 << 27; /* VSI_CKS_CHG */ + data32 |= 0 << 26; /* GMD_CKS_CHG */ + data32 |= 0 << 25; /* AIF_CKS_CHG */ + data32 |= 1 << 24; /* AVI_CKS_CHG */ + data32 |= 0 << 23; /* ACR_N_CHG */ + data32 |= 0 << 22; /* ACR_CTS_CHG */ + data32 |= 1 << 21; /* GCP_AV_MUTE_CHG */ + data32 |= 0 << 20; /* GMD_RCV */ + data32 |= 0 << 19; /* AIF_RCV */ + data32 |= 0 << 18; /* AVI_RCV */ + data32 |= 0 << 17; /* ACR_RCV */ + data32 |= 0 << 16; /* GCP_RCV */ + data32 |= 0 << 15; /* VSI_RCV */ + data32 |= 0 << 14; /* AMP_RCV */ + data32 |= 0 << 13; /* AMP_CHG */ + /* diff */ + data32 |= 1 << 10; /* DRC_CKS_CHG */ + data32 |= 1 << 9; /* DRC_RCV */ + /* diff */ + data32 |= 0 << 8; /* PD_FIFO_NEW_ENTRY */ + data32 |= 0 << 4; /* PD_FIFO_OVERFL */ + data32 |= 0 << 3; /* PD_FIFO_UNDERFL */ + data32 |= 0 << 2; /* PD_FIFO_TH_START_PASS */ + data32 |= 0 << 1; /* PD_FIFO_TH_MAX_PASS */ + data32 |= 0 << 0; /* PD_FIFO_TH_MIN_PASS */ + data32 |= pdec_ists_en; } + hdmirx_wr_dwc(DWC_PDEC_IEN_SET, data32); + hdmirx_wr_dwc(DWC_AUD_FIFO_IEN_SET, OVERFL|UNDERFL); +} else { + /* clear enable */ + hdmirx_wr_dwc(DWC_PDEC_IEN_CLR, ~0); + hdmirx_wr_dwc(DWC_AUD_CEC_IEN_CLR, ~0); + hdmirx_wr_dwc(DWC_AUD_FIFO_IEN_CLR, ~0); + hdmirx_wr_dwc(DWC_MD_IEN_CLR, ~0); + /* clear status */ + hdmirx_wr_dwc(DWC_PDEC_ICLR, ~0); + hdmirx_wr_dwc(DWC_AUD_CEC_ICLR, ~0); + hdmirx_wr_dwc(DWC_AUD_FIFO_ICLR, ~0); + hdmirx_wr_dwc(DWC_MD_ICLR, ~0); +} } /* - * hdmirx_irq_hdcp_enable - hdcp irq enalbe - */ +* hdmirx_irq_hdcp_enable - hdcp irq enalbe +*/ void hdmirx_irq_hdcp_enable(bool enable) { - if (enable) { - /* hdcp2.2 */ - if (hdcp22_on) - hdmirx_wr_dwc(DWC_HDMI2_IEN_SET, 0x1f); - /* hdcp1.4 */ - hdmirx_wr_dwc(DWC_HDMI_IEN_SET, AKSV_RCV); - } else { - /* hdcp2.2 */ - if (hdcp22_on) { - /* clear enable */ - hdmirx_wr_dwc(DWC_HDMI2_IEN_CLR, ~0); - /* clear status */ - hdmirx_wr_dwc(DWC_HDMI2_ICLR, ~0); - } - /* hdcp1.4 */ +if (enable) { + /* hdcp2.2 */ + if (hdcp22_on) + hdmirx_wr_dwc(DWC_HDMI2_IEN_SET, 0x1f); + /* hdcp1.4 */ + hdmirx_wr_dwc(DWC_HDMI_IEN_SET, AKSV_RCV); +} else { + /* hdcp2.2 */ + if (hdcp22_on) { /* clear enable */ - hdmirx_wr_dwc(DWC_HDMI_IEN_CLR, ~0); + hdmirx_wr_dwc(DWC_HDMI2_IEN_CLR, ~0); /* clear status */ - hdmirx_wr_dwc(DWC_HDMI_ICLR, ~0); + hdmirx_wr_dwc(DWC_HDMI2_ICLR, ~0); } + /* hdcp1.4 */ + /* clear enable */ + hdmirx_wr_dwc(DWC_HDMI_IEN_CLR, ~0); + /* clear status */ + hdmirx_wr_dwc(DWC_HDMI_ICLR, ~0); +} } /* - * rx_get_audinfo - get aduio info - */ +* rx_get_audinfo - get aduio info +*/ void rx_get_audinfo(struct aud_info_s *audio_info) { - audio_info->coding_type = - hdmirx_rd_bits_dwc(DWC_PDEC_AIF_PB0, CODING_TYPE); - audio_info->channel_count = - hdmirx_rd_bits_dwc(DWC_PDEC_AIF_PB0, CHANNEL_COUNT); +audio_info->coding_type = + hdmirx_rd_bits_dwc(DWC_PDEC_AIF_PB0, CODING_TYPE); +audio_info->channel_count = + hdmirx_rd_bits_dwc(DWC_PDEC_AIF_PB0, CHANNEL_COUNT); - audio_info->sample_frequency = - hdmirx_rd_bits_dwc(DWC_PDEC_AIF_PB0, SAMPLE_FREQ); - audio_info->sample_size = - hdmirx_rd_bits_dwc(DWC_PDEC_AIF_PB0, SAMPLE_SIZE); - audio_info->coding_extension = - hdmirx_rd_bits_dwc(DWC_PDEC_AIF_PB0, AIF_DATA_BYTE_3); - audio_info->auds_ch_alloc = - hdmirx_rd_bits_dwc(DWC_PDEC_AIF_PB0, CH_SPEAK_ALLOC); - audio_info->auds_layout = - hdmirx_rd_bits_dwc(DWC_PDEC_STS, PD_AUD_LAYOUT); +audio_info->sample_frequency = + hdmirx_rd_bits_dwc(DWC_PDEC_AIF_PB0, SAMPLE_FREQ); +audio_info->sample_size = + hdmirx_rd_bits_dwc(DWC_PDEC_AIF_PB0, SAMPLE_SIZE); +audio_info->coding_extension = + hdmirx_rd_bits_dwc(DWC_PDEC_AIF_PB0, AIF_DATA_BYTE_3); +audio_info->auds_ch_alloc = + hdmirx_rd_bits_dwc(DWC_PDEC_AIF_PB0, CH_SPEAK_ALLOC); +audio_info->auds_layout = + hdmirx_rd_bits_dwc(DWC_PDEC_STS, PD_AUD_LAYOUT); - audio_info->aud_packet_received = - hdmirx_rd_dwc(DWC_PDEC_AUD_STS) & - (AUDS_RCV | AUDS_HBR_RCV); - audio_info->cts = hdmirx_rd_dwc(DWC_PDEC_ACR_CTS); +audio_info->aud_packet_received = + hdmirx_rd_dwc(DWC_PDEC_AUD_STS) & + (AUDS_RCV | AUDS_HBR_RCV); +audio_info->cts = hdmirx_rd_dwc(DWC_PDEC_ACR_CTS); - audio_info->n = hdmirx_rd_dwc(DWC_PDEC_ACR_N); - if (audio_info->cts != 0) { - audio_info->arc = (hdmirx_get_tmds_clock()/audio_info->cts)* - audio_info->n/128; - } else - audio_info->arc = 0; +audio_info->n = hdmirx_rd_dwc(DWC_PDEC_ACR_N); +if (audio_info->cts != 0) { + audio_info->arc = + (rx_measure_clock(MEASURE_CLK_TMDS)/audio_info->cts)* + audio_info->n/128; +} else + audio_info->arc = 0; } /* - * rx_get_audio_status - interface for audio module - */ +* rx_get_audio_status - interface for audio module +*/ void rx_get_audio_status(struct rx_audio_stat_s *aud_sts) { - if ((rx.state == FSM_SIG_READY) && - (rx.pre.sw_vic != HDMI_UNKNOWN) && - (rx.pre.sw_vic != HDMI_UNSUPPORT) && - (rx.avmute_skip == 0)) { - aud_sts->aud_rcv_flag = - (rx.aud_info.aud_packet_received == 0) ? false : true; - aud_sts->aud_stb_flag = true; - aud_sts->aud_sr = rx.aud_info.real_sr; - aud_sts->aud_channel_cnt = rx.aud_info.channel_count; - aud_sts->aud_type = rx.aud_info.coding_type; - aud_sts->afifo_thres_pass = - ((hdmirx_rd_dwc(DWC_AUD_FIFO_STS) & - THS_PASS_STS) == 0) ? false : true; - } else { - memset(aud_sts, 0, - sizeof(struct rx_audio_stat_s)); - } +if ((rx.state == FSM_SIG_READY) && + (rx.pre.sw_vic != HDMI_UNKNOWN) && + (rx.pre.sw_vic != HDMI_UNSUPPORT) && + (rx.avmute_skip == 0)) { + aud_sts->aud_rcv_flag = + (rx.aud_info.aud_packet_received == 0) ? false : true; + aud_sts->aud_stb_flag = true; + aud_sts->aud_sr = rx.aud_info.real_sr; + aud_sts->aud_channel_cnt = rx.aud_info.channel_count; + aud_sts->aud_type = rx.aud_info.coding_type; + aud_sts->afifo_thres_pass = + ((hdmirx_rd_dwc(DWC_AUD_FIFO_STS) & + THS_PASS_STS) == 0) ? false : true; +} else { + memset(aud_sts, 0, + sizeof(struct rx_audio_stat_s)); +} } EXPORT_SYMBOL(rx_get_audio_status); /* - * rx_get_hdmi5v_sts - get current pwr5v status on all ports - */ +* rx_get_hdmi5v_sts - get current pwr5v status on all ports +*/ unsigned int rx_get_hdmi5v_sts(void) { - return (hdmirx_rd_top(TOP_HPD_PWR5V) >> 20) & 0xf; +return (hdmirx_rd_top(TOP_HPD_PWR5V) >> 20) & 0xf; } /* - * rx_get_hpd_sts - get current hpd status on all ports - */ +* rx_get_hpd_sts - get current hpd status on all ports +*/ unsigned int rx_get_hpd_sts(void) { - return hdmirx_rd_top(TOP_HPD_PWR5V) & 0xf; +return hdmirx_rd_top(TOP_HPD_PWR5V) & 0xf; } /* - * rx_get_scdc_clkrate_sts - get tmds clk ratio - */ +* rx_get_scdc_clkrate_sts - get tmds clk ratio +*/ unsigned int rx_get_scdc_clkrate_sts(void) { - if (rx.chip_id == CHIP_ID_TXHD) - return 0; - else - return (hdmirx_rd_dwc(DWC_SCDC_REGS0) >> 17) & 1; +if (rx.chip_id == CHIP_ID_TXHD) + return 0; +else + return (hdmirx_rd_dwc(DWC_SCDC_REGS0) >> 17) & 1; } /* - * rx_get_pll_lock_sts - tmds pll lock indication - * return true if tmds pll locked, false otherwise. - */ +* rx_get_pll_lock_sts - tmds pll lock indication +* return true if tmds pll locked, false otherwise. +*/ unsigned int rx_get_pll_lock_sts(void) { - return hdmirx_rd_dwc(DWC_HDMI_PLL_LCK_STS) & 1; +return hdmirx_rd_dwc(DWC_HDMI_PLL_LCK_STS) & 1; } /* - * rx_get_aud_pll_lock_sts - audio pll lock indication - * no use - */ +* rx_get_aud_pll_lock_sts - audio pll lock indication +* no use +*/ bool rx_get_aud_pll_lock_sts(void) { - /* if ((hdmirx_rd_dwc(DWC_AUD_PLL_CTRL) & (1 << 31)) == 0) */ - if ((rd_reg_hhi(HHI_AUD_PLL_CNTL_I) & (1 << 31)) == 0) - return false; - else - return true; +/* if ((hdmirx_rd_dwc(DWC_AUD_PLL_CTRL) & (1 << 31)) == 0) */ +if ((rd_reg_hhi(HHI_AUD_PLL_CNTL_I) & (1 << 31)) == 0) + return false; +else + return true; } /* - * is_clk_stable - phy clock stable detection - */ +* is_clk_stable - phy clock stable detection +*/ bool is_clk_stable(void) { - int clk; +int clk = false; - clk = hdmirx_rd_phy(PHY_MAINFSM_STATUS1); - clk = (clk >> 8) & 1; - if (clk == 1) - return true; - else - return false; +if (rx.hdmirxdev->data->chip_id == CHIP_ID_TL1) { + /* sqofclk */ + clk = rd_reg_hhi(HHI_HDMIRX_PHY_MISC_STAT) & 0x80000000; +} else { + /* phy clk */ + clk = hdmirx_rd_phy(PHY_MAINFSM_STATUS1) & 0x100; +} + +if (clk) + return true; +else + return false; } /* - * hdmirx_audio_fifo_rst - reset afifo - */ +* hdmirx_audio_fifo_rst - reset afifo +*/ unsigned int hdmirx_audio_fifo_rst(void) { - int error = 0; +int error = 0; - hdmirx_wr_bits_dwc(DWC_AUD_FIFO_CTRL, AFIF_INIT, 1); - udelay(20); - hdmirx_wr_bits_dwc(DWC_AUD_FIFO_CTRL, AFIF_INIT, 0); - hdmirx_wr_dwc(DWC_DMI_SW_RST, 0x10); - if (log_level & AUDIO_LOG) - rx_pr("%s\n", __func__); - return error; +hdmirx_wr_bits_dwc(DWC_AUD_FIFO_CTRL, AFIF_INIT, 1); +udelay(20); +hdmirx_wr_bits_dwc(DWC_AUD_FIFO_CTRL, AFIF_INIT, 0); +hdmirx_wr_dwc(DWC_DMI_SW_RST, 0x10); +if (log_level & AUDIO_LOG) + rx_pr("%s\n", __func__); +return error; } /* - * hdmirx_control_clk_range - */ +* hdmirx_control_clk_range +*/ int hdmirx_control_clk_range(unsigned long min, unsigned long max) { - int error = 0; - unsigned int evaltime = 0; - unsigned long ref_clk; +int error = 0; +unsigned int evaltime = 0; +unsigned long ref_clk; - ref_clk = modet_clk; - evaltime = (ref_clk * 4095) / 158000; - min = (min * evaltime) / ref_clk; - max = (max * evaltime) / ref_clk; - hdmirx_wr_bits_dwc(DWC_HDMI_CKM_F, MINFREQ, min); - hdmirx_wr_bits_dwc(DWC_HDMI_CKM_F, CKM_MAXFREQ, max); - return error; +ref_clk = modet_clk; +evaltime = (ref_clk * 4095) / 158000; +min = (min * evaltime) / ref_clk; +max = (max * evaltime) / ref_clk; +hdmirx_wr_bits_dwc(DWC_HDMI_CKM_F, MINFREQ, min); +hdmirx_wr_bits_dwc(DWC_HDMI_CKM_F, CKM_MAXFREQ, max); +return error; } /* - * set_scdc_cfg - */ +* set_scdc_cfg +*/ void set_scdc_cfg(int hpdlow, int pwrprovided) { - if (rx.chip_id == CHIP_ID_TXHD) - return; +if (rx.chip_id == CHIP_ID_TXHD) + return; - hdmirx_wr_dwc(DWC_SCDC_CONFIG, - (hpdlow << 1) | (pwrprovided << 0)); +hdmirx_wr_dwc(DWC_SCDC_CONFIG, + (hpdlow << 1) | (pwrprovided << 0)); } /* - * packet_init - packet receiving config - */ +* packet_init - packet receiving config +*/ int packet_init(void) { - int error = 0; - int data32 = 0; +int error = 0; +int data32 = 0; - data32 |= 1 << 9; /* amp_err_filter */ - data32 |= 1 << 8; /* isrc_err_filter */ - data32 |= 1 << 7; /* gmd_err_filter */ - data32 |= 1 << 6; /* aif_err_filter */ - data32 |= 1 << 5; /* avi_err_filter */ - data32 |= 1 << 4; /* vsi_err_filter */ - data32 |= 1 << 3; /* gcp_err_filter */ - data32 |= 1 << 2; /* acrp_err_filter */ - data32 |= 1 << 1; /* ph_err_filter */ - data32 |= 0 << 0; /* checksum_err_filter */ - hdmirx_wr_dwc(DWC_PDEC_ERR_FILTER, data32); +data32 |= 1 << 9; /* amp_err_filter */ +data32 |= 1 << 8; /* isrc_err_filter */ +data32 |= 1 << 7; /* gmd_err_filter */ +data32 |= 1 << 6; /* aif_err_filter */ +data32 |= 1 << 5; /* avi_err_filter */ +data32 |= 1 << 4; /* vsi_err_filter */ +data32 |= 1 << 3; /* gcp_err_filter */ +data32 |= 1 << 2; /* acrp_err_filter */ +data32 |= 1 << 1; /* ph_err_filter */ +data32 |= 0 << 0; /* checksum_err_filter */ +hdmirx_wr_dwc(DWC_PDEC_ERR_FILTER, data32); - data32 = hdmirx_rd_dwc(DWC_PDEC_CTRL); - data32 |= 1 << 31; /* PFIFO_STORE_FILTER_EN */ - data32 |= 1 << 4; /* PD_FIFO_WE */ - data32 |= 1 << 0; /* PDEC_BCH_EN */ - data32 &= (~GCP_GLOBAVMUTE); - data32 |= GCP_GLOBAVMUTE_EN << 15; - data32 |= packet_fifo_cfg; - hdmirx_wr_dwc(DWC_PDEC_CTRL, data32); +data32 = hdmirx_rd_dwc(DWC_PDEC_CTRL); +data32 |= 1 << 31; /* PFIFO_STORE_FILTER_EN */ +data32 |= 0 << 30; /* Enable packet FIFO to store EMP */ +data32 |= 1 << 4; /* PD_FIFO_WE */ +data32 |= 1 << 0; /* PDEC_BCH_EN */ +data32 &= (~GCP_GLOBAVMUTE); +data32 |= GCP_GLOBAVMUTE_EN << 15; +data32 |= packet_fifo_cfg; +hdmirx_wr_dwc(DWC_PDEC_CTRL, data32); - data32 = 0; - data32 |= pd_fifo_start_cnt << 20; /* PD_start */ - data32 |= 640 << 10; /* PD_max */ - data32 |= 8 << 0; /* PD_min */ - hdmirx_wr_dwc(DWC_PDEC_FIFO_CFG, data32); +data32 = 0; +data32 |= pd_fifo_start_cnt << 20; /* PD_start */ +data32 |= 640 << 10; /* PD_max */ +data32 |= 8 << 0; /* PD_min */ +hdmirx_wr_dwc(DWC_PDEC_FIFO_CFG, data32); - return error; +return error; } /* - * pd_fifo_irq_ctl - */ +* pd_fifo_irq_ctl +*/ void pd_fifo_irq_ctl(bool en) { - int i = hdmirx_rd_dwc(DWC_PDEC_IEN); +int i = hdmirx_rd_dwc(DWC_PDEC_IEN); - if (en == 0) - hdmirx_wr_bits_dwc(DWC_PDEC_IEN_CLR, _BIT(2), 1); - else - hdmirx_wr_dwc(DWC_PDEC_IEN_SET, (_BIT(2) | i)); +if (en == 0) + hdmirx_wr_bits_dwc(DWC_PDEC_IEN_CLR, _BIT(2), 1); +else + hdmirx_wr_dwc(DWC_PDEC_IEN_SET, (_BIT(2) | i)); } /* - * hdmirx_packet_fifo_rst - reset packet fifo - */ +* hdmirx_packet_fifo_rst - reset packet fifo +*/ unsigned int hdmirx_packet_fifo_rst(void) { - int error = 0; +int error = 0; - hdmirx_wr_bits_dwc(DWC_PDEC_CTRL, - PD_FIFO_FILL_INFO_CLR|PD_FIFO_CLR, ~0); - hdmirx_wr_bits_dwc(DWC_PDEC_CTRL, - PD_FIFO_FILL_INFO_CLR|PD_FIFO_CLR, 0); - return error; +hdmirx_wr_bits_dwc(DWC_PDEC_CTRL, + PD_FIFO_FILL_INFO_CLR|PD_FIFO_CLR, ~0); +hdmirx_wr_bits_dwc(DWC_PDEC_CTRL, + PD_FIFO_FILL_INFO_CLR|PD_FIFO_CLR, 0); +return error; } /* - * TOP_init - hdmirx top initialization - */ +* TOP_init - hdmirx top initialization +*/ static int TOP_init(void) { - int err = 0; - int data32 = 0; +int err = 0; +int data32 = 0; - data32 |= (0xf << 13); /* bit[16:13] */ - data32 |= 0 << 11; - data32 |= 0 << 10; - data32 |= 0 << 9; - data32 |= 0 << 8; - data32 |= EDID_CLK_DIV << 0; - hdmirx_wr_top(TOP_EDID_GEN_CNTL, data32); +data32 |= (0xf << 13); /* bit[16:13] */ +data32 |= 0 << 11; +data32 |= 0 << 10; +data32 |= 0 << 9; +data32 |= 0 << 8; +data32 |= EDID_CLK_DIV << 0; +hdmirx_wr_top(TOP_EDID_GEN_CNTL, data32); +data32 = 0; +/* SDA filter internal clk div */ +data32 |= 1 << 29; +/* SDA sampling clk div */ +data32 |= 1 << 16; +/* SCL filter internal clk div */ +data32 |= 1 << 13; +/* SCL sampling clk div */ +data32 |= 1 << 0; +hdmirx_wr_top(TOP_INFILTER_HDCP, data32); +hdmirx_wr_top(TOP_INFILTER_I2C0, data32); +hdmirx_wr_top(TOP_INFILTER_I2C1, data32); +hdmirx_wr_top(TOP_INFILTER_I2C2, data32); +hdmirx_wr_top(TOP_INFILTER_I2C3, data32); + +data32 = 0; +/* conversion mode of 422 to 444 */ +data32 |= 0 << 19; +/* !!!!dolby vision 422 to 444 ctl bit */ +data32 |= 0 << 0; +hdmirx_wr_top(TOP_VID_CNTL, data32); + +if (rx.chip_id != CHIP_ID_TXHD) { data32 = 0; - /* SDA filter internal clk div */ - data32 |= 1 << 29; - /* SDA sampling clk div */ - data32 |= 1 << 16; - /* SCL filter internal clk div */ - data32 |= 1 << 13; - /* SCL sampling clk div */ - data32 |= 1 << 0; - hdmirx_wr_top(TOP_INFILTER_HDCP, data32); - hdmirx_wr_top(TOP_INFILTER_I2C0, data32); - hdmirx_wr_top(TOP_INFILTER_I2C1, data32); - hdmirx_wr_top(TOP_INFILTER_I2C2, data32); - hdmirx_wr_top(TOP_INFILTER_I2C3, data32); - - data32 = 0; - /* conversion mode of 422 to 444 */ - data32 |= 0 << 19; - /* !!!!dolby vision 422 to 444 ctl bit */ - data32 |= 0 << 0; - hdmirx_wr_top(TOP_VID_CNTL, data32); - - if (rx.chip_id != CHIP_ID_TXHD) { - data32 = 0; - data32 |= 0 << 20; - data32 |= 0 << 8; - data32 |= 0x0a << 0; - hdmirx_wr_top(TOP_VID_CNTL2, data32); - } - data32 = 0; - /* delay cycles before n/cts update pulse */ - data32 |= 7 << 0; + data32 |= 0 << 20; + data32 |= 0 << 8; + data32 |= 0x0a << 0; + hdmirx_wr_top(TOP_VID_CNTL2, data32); +} +data32 = 0; +if (rx.hdmirxdev->data->chip_id == CHIP_ID_TL1) { + /* n_cts_auto_mode: */ + /* 0-every ACR packet */ + /* 1-on N or CTS value change */ + data32 |= 0 << 4; +} +/* delay cycles before n/cts update pulse */ +data32 |= 7 << 0; +if (rx.hdmirxdev->data->chip_id == CHIP_ID_TL1) + hdmirx_wr_top(TOP_TL1_ACR_CNTL2, data32); +else hdmirx_wr_top(TOP_ACR_CNTL2, data32); - data32 = 0; - /* bit4: hpd override, bit5: hpd reverse */ - data32 |= 1 << 4; - if (rx.chip_id == CHIP_ID_GXTVBB) - data32 |= 0 << 5; - else - data32 |= 1 << 5; - /* pull down all the hpd */ - hdmirx_wr_top(TOP_HPD_PWR5V, data32); - return err; +data32 = 0; +/* bit4: hpd override, bit5: hpd reverse */ +data32 |= 1 << 4; +if (rx.chip_id == CHIP_ID_GXTVBB) + data32 |= 0 << 5; +else + data32 |= 1 << 5; +/* pull down all the hpd */ +hdmirx_wr_top(TOP_HPD_PWR5V, data32); +if (rx.hdmirxdev->data->chip_id == CHIP_ID_TL1) { + data32 = hdmirx_rd_dwc(DWC_HDCP_CTRL); + /* 0: Original behaviour */ + /* 1: Balance path delay between non-HDCP and HDCP */ + data32 |= 1 << 27; /* none & hdcp */ + /* 0: Original behaviour */ + /* 1: Balance path delay between HDCP14 and HDCP22. */ + data32 |= 1 << 26; /* 1.4 & 2.2 */ + hdmirx_wr_dwc(DWC_HDCP_CTRL, data32); +} +return err; } /* - * DWC_init - DWC controller initialization - */ +* DWC_init - DWC controller initialization +*/ static int DWC_init(void) { - int err = 0; - unsigned long data32; - unsigned int evaltime = 0; +int err = 0; +unsigned long data32; +unsigned int evaltime = 0; - evaltime = (modet_clk * 4095) / 158000; - /* enable all */ - hdmirx_wr_dwc(DWC_HDMI_OVR_CTRL, ~0); - /* recover to default value.*/ - /* remain code for some time.*/ - /* if no side effect then remove it */ - /*hdmirx_wr_bits_dwc(DWC_HDMI_SYNC_CTRL,*/ - /* VS_POL_ADJ_MODE, VS_POL_ADJ_AUTO);*/ - /*hdmirx_wr_bits_dwc(DWC_HDMI_SYNC_CTRL,*/ - /* HS_POL_ADJ_MODE, HS_POL_ADJ_AUTO);*/ +evaltime = (modet_clk * 4095) / 158000; +/* enable all */ +hdmirx_wr_dwc(DWC_HDMI_OVR_CTRL, ~0); +/* recover to default value.*/ +/* remain code for some time.*/ +/* if no side effect then remove it */ +/*hdmirx_wr_bits_dwc(DWC_HDMI_SYNC_CTRL,*/ +/* VS_POL_ADJ_MODE, VS_POL_ADJ_AUTO);*/ +/*hdmirx_wr_bits_dwc(DWC_HDMI_SYNC_CTRL,*/ +/* HS_POL_ADJ_MODE, HS_POL_ADJ_AUTO);*/ - hdmirx_wr_bits_dwc(DWC_HDMI_CKM_EVLTM, - EVAL_TIME, evaltime); - hdmirx_control_clk_range(TMDS_CLK_MIN, - TMDS_CLK_MAX); +hdmirx_wr_bits_dwc(DWC_HDMI_CKM_EVLTM, + EVAL_TIME, evaltime); +hdmirx_control_clk_range(TMDS_CLK_MIN, + TMDS_CLK_MAX); - /* hdmirx_wr_bits_dwc(DWC_SNPS_PHYG3_CTRL,*/ - /*((1 << 2) - 1) << 2, port); */ +/* hdmirx_wr_bits_dwc(DWC_SNPS_PHYG3_CTRL,*/ + /*((1 << 2) - 1) << 2, port); */ - data32 = 0; - data32 |= 0 << 20; - data32 |= 1 << 19; - data32 |= 5 << 16; /* [18:16] valid_mode */ - data32 |= 0 << 12; /* [13:12] ctrl_filt_sens */ - data32 |= 3 << 10; /* [11:10] vs_filt_sens */ - data32 |= 0 << 8; /* [9:8] hs_filt_sens */ - data32 |= 2 << 6; /* [7:6] de_measure_mode */ - data32 |= 0 << 5; /* [5] de_regen */ - data32 |= 3 << 3; /* [4:3] de_filter_sens */ - hdmirx_wr_dwc(DWC_HDMI_ERROR_PROTECT, data32); +data32 = 0; +data32 |= 0 << 20; +data32 |= 1 << 19; +data32 |= 5 << 16; /* [18:16] valid_mode */ +data32 |= 0 << 12; /* [13:12] ctrl_filt_sens */ +data32 |= 3 << 10; /* [11:10] vs_filt_sens */ +data32 |= 0 << 8; /* [9:8] hs_filt_sens */ +data32 |= 2 << 6; /* [7:6] de_measure_mode */ +data32 |= 0 << 5; /* [5] de_regen */ +data32 |= 3 << 3; /* [4:3] de_filter_sens */ +hdmirx_wr_dwc(DWC_HDMI_ERROR_PROTECT, data32); - data32 = 0; - data32 |= 0 << 8; /* [10:8] hact_pix_ith */ - data32 |= 0 << 5; /* [5] hact_pix_src */ - data32 |= 1 << 4; /* [4] htot_pix_src */ - hdmirx_wr_dwc(DWC_MD_HCTRL1, data32); +data32 = 0; +data32 |= 0 << 8; /* [10:8] hact_pix_ith */ +data32 |= 0 << 5; /* [5] hact_pix_src */ +data32 |= 1 << 4; /* [4] htot_pix_src */ +hdmirx_wr_dwc(DWC_MD_HCTRL1, data32); - data32 = 0; - data32 |= 1 << 12; /* [14:12] hs_clk_ith */ - data32 |= 7 << 8; /* [10:8] htot32_clk_ith */ - data32 |= 1 << 5; /* [5] vs_act_time */ - data32 |= 3 << 3; /* [4:3] hs_act_time */ - data32 |= 0 << 0; /* [1:0] h_start_pos */ - hdmirx_wr_dwc(DWC_MD_HCTRL2, data32); +data32 = 0; +data32 |= 1 << 12; /* [14:12] hs_clk_ith */ +data32 |= 7 << 8; /* [10:8] htot32_clk_ith */ +data32 |= 1 << 5; /* [5] vs_act_time */ +data32 |= 3 << 3; /* [4:3] hs_act_time */ +data32 |= 0 << 0; /* [1:0] h_start_pos */ +hdmirx_wr_dwc(DWC_MD_HCTRL2, data32); - data32 = 0; - data32 |= 1 << 4; /* [4] v_offs_lin_mode */ - data32 |= 1 << 1; /* [1] v_edge */ - data32 |= 0 << 0; /* [0] v_mode */ - hdmirx_wr_dwc(DWC_MD_VCTRL, data32); +data32 = 0; +data32 |= 1 << 4; /* [4] v_offs_lin_mode */ +data32 |= 1 << 1; /* [1] v_edge */ +data32 |= 0 << 0; /* [0] v_mode */ +hdmirx_wr_dwc(DWC_MD_VCTRL, data32); - data32 = 0; - data32 |= 1 << 10; /* [11:10] vofs_lin_ith */ - data32 |= 3 << 8; /* [9:8] vact_lin_ith */ - data32 |= 0 << 6; /* [7:6] vtot_lin_ith */ - data32 |= 7 << 3; /* [5:3] vs_clk_ith */ - data32 |= 2 << 0; /* [2:0] vtot_clk_ith */ - hdmirx_wr_dwc(DWC_MD_VTH, data32); +data32 = 0; +data32 |= 1 << 10; /* [11:10] vofs_lin_ith */ +data32 |= 3 << 8; /* [9:8] vact_lin_ith */ +data32 |= 0 << 6; /* [7:6] vtot_lin_ith */ +data32 |= 7 << 3; /* [5:3] vs_clk_ith */ +data32 |= 2 << 0; /* [2:0] vtot_clk_ith */ +hdmirx_wr_dwc(DWC_MD_VTH, data32); - data32 = 0; - data32 |= 1 << 2; /* [2] fafielddet_en */ - data32 |= 0 << 0; /* [1:0] field_pol_mode */ - hdmirx_wr_dwc(DWC_MD_IL_POL, data32); +data32 = 0; +data32 |= 1 << 2; /* [2] fafielddet_en */ +data32 |= 0 << 0; /* [1:0] field_pol_mode */ +hdmirx_wr_dwc(DWC_MD_IL_POL, data32); - data32 = 0; - data32 |= 0 << 1; - data32 |= 1 << 0; - hdmirx_wr_dwc(DWC_HDMI_RESMPL_CTRL, data32); +data32 = 0; +data32 |= 0 << 1; +data32 |= 1 << 0; +hdmirx_wr_dwc(DWC_HDMI_RESMPL_CTRL, data32); - data32 = 0; - data32 |= (hdmirx_rd_dwc(DWC_HDMI_MODE_RECOVER) & 0xf8000000); - data32 |= (0 << 24); - data32 |= (0 << 18); - data32 |= (HYST_HDMI_TO_DVI << 13); - data32 |= (HYST_DVI_TO_HDMI << 8); - data32 |= (0 << 6); - data32 |= (0 << 4); - /* Force OESS mode to fix Google Chromecast box black screen issue */ - data32 |= (1 << 2); - data32 |= (0 << 0); - hdmirx_wr_dwc(DWC_HDMI_MODE_RECOVER, data32); +data32 = 0; +data32 |= (hdmirx_rd_dwc(DWC_HDMI_MODE_RECOVER) & 0xf8000000); +data32 |= (0 << 24); +data32 |= (0 << 18); +data32 |= (HYST_HDMI_TO_DVI << 13); +data32 |= (HYST_DVI_TO_HDMI << 8); +data32 |= (0 << 6); +data32 |= (0 << 4); +/* Force OESS mode to fix Google Chromecast box black screen issue */ +data32 |= (1 << 2); +data32 |= (0 << 0); +hdmirx_wr_dwc(DWC_HDMI_MODE_RECOVER, data32); - return err; +return err; } void rx_hdcp14_set_normal_key(const struct hdmi_rx_hdcp *hdcp) { - unsigned int i = 0; - unsigned int k = 0; - int error = 0; +unsigned int i = 0; +unsigned int k = 0; +int error = 0; - for (i = 0; i < HDCP_KEYS_SIZE; i += 2) { - for (k = 0; k < HDCP_KEY_WR_TRIES; k++) { - if (hdmirx_rd_bits_dwc(DWC_HDCP_STS, - HDCP_KEY_WR_OK_STS) != 0) { - break; - } - } - if (k < HDCP_KEY_WR_TRIES) { - hdmirx_wr_dwc(DWC_HDCP_KEY1, hdcp->keys[i + 0]); - hdmirx_wr_dwc(DWC_HDCP_KEY0, hdcp->keys[i + 1]); - } else { - error = -EAGAIN; +for (i = 0; i < HDCP_KEYS_SIZE; i += 2) { + for (k = 0; k < HDCP_KEY_WR_TRIES; k++) { + if (hdmirx_rd_bits_dwc(DWC_HDCP_STS, + HDCP_KEY_WR_OK_STS) != 0) { break; } } - hdmirx_wr_dwc(DWC_HDCP_BKSV1, hdcp->bksv[0]); - hdmirx_wr_dwc(DWC_HDCP_BKSV0, hdcp->bksv[1]); + if (k < HDCP_KEY_WR_TRIES) { + hdmirx_wr_dwc(DWC_HDCP_KEY1, hdcp->keys[i + 0]); + hdmirx_wr_dwc(DWC_HDCP_KEY0, hdcp->keys[i + 1]); + } else { + error = -EAGAIN; + break; + } +} +hdmirx_wr_dwc(DWC_HDCP_BKSV1, hdcp->bksv[0]); +hdmirx_wr_dwc(DWC_HDCP_BKSV0, hdcp->bksv[1]); } /* - * hdmi_rx_ctrl_hdcp_config - config hdcp1.4 keys - */ +* hdmi_rx_ctrl_hdcp_config - config hdcp1.4 keys +*/ void rx_hdcp14_config(const struct hdmi_rx_hdcp *hdcp) { - unsigned int data32 = 0; +unsigned int data32 = 0; - /* I2C_SPIKE_SUPPR */ - data32 |= 1 << 16; - /* FAST_I2C */ - data32 |= 0 << 12; - /* ONE_DOT_ONE */ - data32 |= 0 << 9; - /* FAST_REAUTH */ - data32 |= 0 << 8; - /* DDC_ADDR */ - data32 |= 0x3a << 1; - hdmirx_wr_dwc(DWC_HDCP_SETTINGS, data32); - /* hdmirx_wr_bits_dwc(DWC_HDCP_SETTINGS, HDCP_FAST_MODE, 0); */ - /* Enable hdcp bcaps bit(bit7). In hdcp1.4 spec: Use of - * this bit is reserved, hdcp Receivers not capable of - * supporting HDMI must clear this bit to 0. For YAMAHA - * RX-V377 amplifier, enable this bit is needed, in case - * the amplifier won't do hdcp1.4 interaction occasionally. - */ - hdmirx_wr_bits_dwc(DWC_HDCP_SETTINGS, HDCP_BCAPS, 1); - hdmirx_wr_bits_dwc(DWC_HDCP_CTRL, ENCRIPTION_ENABLE, 0); - /* hdmirx_wr_bits_dwc(ctx, DWC_HDCP_CTRL, KEY_DECRYPT_ENABLE, 1); */ - hdmirx_wr_bits_dwc(DWC_HDCP_CTRL, KEY_DECRYPT_ENABLE, 0); - hdmirx_wr_dwc(DWC_HDCP_SEED, hdcp->seed); - if (hdcp14_key_mode == SECURE_MODE) { - rx_set_hdcp14_secure_key(); - rx_pr("hdcp1.4 secure mode\n"); - } else { - rx_hdcp14_set_normal_key(&rx.hdcp); - rx_pr("hdcp1.4 normal mode\n"); - } - if (rx.chip_id != CHIP_ID_TXHD) { - hdmirx_wr_bits_dwc(DWC_HDCP_RPT_CTRL, - REPEATER, hdcp->repeat ? 1 : 0); - /* nothing attached downstream */ - hdmirx_wr_dwc(DWC_HDCP_RPT_BSTATUS, 0); - } - hdmirx_wr_bits_dwc(DWC_HDCP_CTRL, ENCRIPTION_ENABLE, 1); +/* I2C_SPIKE_SUPPR */ +data32 |= 1 << 16; +/* FAST_I2C */ +data32 |= 0 << 12; +/* ONE_DOT_ONE */ +data32 |= 0 << 9; +/* FAST_REAUTH */ +data32 |= 0 << 8; +/* DDC_ADDR */ +data32 |= 0x3a << 1; +hdmirx_wr_dwc(DWC_HDCP_SETTINGS, data32); +/* hdmirx_wr_bits_dwc(DWC_HDCP_SETTINGS, HDCP_FAST_MODE, 0); */ +/* Enable hdcp bcaps bit(bit7). In hdcp1.4 spec: Use of + * this bit is reserved, hdcp Receivers not capable of + * supporting HDMI must clear this bit to 0. For YAMAHA + * RX-V377 amplifier, enable this bit is needed, in case + * the amplifier won't do hdcp1.4 interaction occasionally. + */ +hdmirx_wr_bits_dwc(DWC_HDCP_SETTINGS, HDCP_BCAPS, 1); +hdmirx_wr_bits_dwc(DWC_HDCP_CTRL, ENCRIPTION_ENABLE, 0); +/* hdmirx_wr_bits_dwc(ctx, DWC_HDCP_CTRL, KEY_DECRYPT_ENABLE, 1); */ +hdmirx_wr_bits_dwc(DWC_HDCP_CTRL, KEY_DECRYPT_ENABLE, 0); +hdmirx_wr_dwc(DWC_HDCP_SEED, hdcp->seed); +if (hdcp14_key_mode == SECURE_MODE) { + rx_set_hdcp14_secure_key(); + rx_pr("hdcp1.4 secure mode\n"); +} else { + rx_hdcp14_set_normal_key(&rx.hdcp); + rx_pr("hdcp1.4 normal mode\n"); +} +if (rx.chip_id != CHIP_ID_TXHD) { + hdmirx_wr_bits_dwc(DWC_HDCP_RPT_CTRL, + REPEATER, hdcp->repeat ? 1 : 0); + /* nothing attached downstream */ + hdmirx_wr_dwc(DWC_HDCP_RPT_BSTATUS, 0); +} +hdmirx_wr_bits_dwc(DWC_HDCP_CTRL, ENCRIPTION_ENABLE, 1); } void rx_set_term_enable(bool enable) { - hdmirx_wr_bits_phy(PHY_MAIN_FSM_OVERRIDE1, PHY_TERM_OVERRIDE, enable); +hdmirx_wr_bits_phy(PHY_MAIN_FSM_OVERRIDE1, PHY_TERM_OVERRIDE, enable); } void rx_set_term_value(unsigned char port, bool value) { +if (rx.hdmirxdev->data->chip_id == CHIP_ID_TL1) { + /* need to do : for tl1 */ + +} else { if (port < E_PORT_NUM) { if (value) hdmirx_wr_bits_phy(PHY_MAIN_FSM_OVERRIDE1, @@ -1225,72 +1387,77 @@ void rx_set_term_value(unsigned char port, bool value) PHY_TERM_OV_VALUE, 0); } else rx_pr("%s port num overflow\n", __func__); - +} } int rx_set_port_hpd(uint8_t port_id, bool val) { - if (port_id < E_PORT_NUM) { - if (val) { - hdmirx_wr_bits_top(TOP_HPD_PWR5V, _BIT(port_id), 1); - rx_set_term_value(port_id, 1); - } else { - hdmirx_wr_bits_top(TOP_HPD_PWR5V, _BIT(port_id), 0); - rx_set_term_value(port_id, 0); - } - } else if (port_id == ALL_PORTS) { - if (val) { - hdmirx_wr_bits_top(TOP_HPD_PWR5V, MSK(4, 0), 0xF); - rx_set_term_value(port_id, 1); - } else { - hdmirx_wr_bits_top(TOP_HPD_PWR5V, MSK(4, 0), 0x0); - rx_set_term_value(port_id, 0); - } - } else - return -1; +if (port_id < E_PORT_NUM) { + if (val) { + hdmirx_wr_bits_top(TOP_HPD_PWR5V, _BIT(port_id), 1); + rx_set_term_value(port_id, 1); + } else { + hdmirx_wr_bits_top(TOP_HPD_PWR5V, _BIT(port_id), 0); + rx_set_term_value(port_id, 0); + } +} else if (port_id == ALL_PORTS) { + if (val) { + hdmirx_wr_bits_top(TOP_HPD_PWR5V, MSK(4, 0), 0xF); + rx_set_term_value(port_id, 1); + } else { + hdmirx_wr_bits_top(TOP_HPD_PWR5V, MSK(4, 0), 0x0); + rx_set_term_value(port_id, 0); + } +} else + return -1; - if (log_level & LOG_EN) - rx_pr("%s, port:%d, val:%d\n", __func__, - port_id, val); - return 0; +if (log_level & LOG_EN) + rx_pr("%s, port:%d, val:%d\n", __func__, + port_id, val); +return 0; } void rx_set_cur_hpd(uint8_t val) { - rx_set_port_hpd(rx.port, val); +rx_set_port_hpd(rx.port, val); } /* - * rx_force_hpd_config - force config hpd level on all ports - * @hpd_level: hpd level - */ +* rx_force_hpd_config - force config hpd level on all ports +* @hpd_level: hpd level +*/ void rx_force_hpd_cfg(uint8_t hpd_level) { - unsigned int hpd_value; +unsigned int hpd_value; - if (hpd_level) { - if (disable_port_en) - hpd_value = (~(1 << disable_port_num)) & 0xF; - else - hpd_value = 0xF; +if (hpd_level) { + if (disable_port_en) + hpd_value = (~(1 << disable_port_num)) & 0xF; + else + hpd_value = 0xF; - hdmirx_wr_bits_top(TOP_HPD_PWR5V, - MSK(4, 0), hpd_value); - } else - hdmirx_wr_bits_top(TOP_HPD_PWR5V, MSK(4, 0), 0x0); + hdmirx_wr_bits_top(TOP_HPD_PWR5V, + MSK(4, 0), hpd_value); +} else + hdmirx_wr_bits_top(TOP_HPD_PWR5V, MSK(4, 0), 0x0); } /* - * rx_force_rxsense_cfg - force config rxsense level on all ports - * @level: rxsense level - */ +* rx_force_rxsense_cfg - force config rxsense level on all ports +* @level: rxsense level +*/ void rx_force_rxsense_cfg(uint8_t level) { - unsigned int term_ovr_value; +unsigned int term_ovr_value; +if (rx.hdmirxdev->data->chip_id == CHIP_ID_TL1) { + /* need to do: for tl1 ...*/ + +} else { if (level) { if (disable_port_en) - term_ovr_value = (~(1 << disable_port_num)) & 0xF; + term_ovr_value = + (~(1 << disable_port_num)) & 0xF; else term_ovr_value = 0xF; @@ -1300,99 +1467,105 @@ void rx_force_rxsense_cfg(uint8_t level) hdmirx_wr_bits_phy(PHY_MAIN_FSM_OVERRIDE1, PHY_TERM_OV_VALUE, 0x0); } - -/* - * rx_force_hpd_rxsense_cfg - force config - * hpd & rxsense level on all ports - * @level: hpd & rxsense level - */ -void rx_force_hpd_rxsense_cfg(uint8_t level) -{ - rx_force_hpd_cfg(level); - rx_force_rxsense_cfg(level); - if (log_level & LOG_EN) - rx_pr("hpd & rxsense force val:%d\n", level); } /* - * control_reset - hdmirx controller reset - */ +* rx_force_hpd_rxsense_cfg - force config +* hpd & rxsense level on all ports +* @level: hpd & rxsense level +*/ +void rx_force_hpd_rxsense_cfg(uint8_t level) +{ +rx_force_hpd_cfg(level); +rx_force_rxsense_cfg(level); +if (log_level & LOG_EN) + rx_pr("hpd & rxsense force val:%d\n", level); +} + +/* +* control_reset - hdmirx controller reset +*/ void control_reset(void) { - unsigned long data32; +unsigned long data32; - /* disable functional modules */ - hdmirx_top_sw_reset(); +/* disable functional modules */ +hdmirx_top_sw_reset(); - /* Enable functional modules */ - data32 = 0; - data32 |= 1 << 5; /* [5] cec_enable */ - data32 |= 1 << 4; /* [4] aud_enable */ - data32 |= 1 << 3; /* [3] bus_enable */ - data32 |= 1 << 2; /* [2] hdmi_enable */ - data32 |= 1 << 1; /* [1] modet_enable */ - data32 |= 1 << 0; /* [0] cfg_enable */ - hdmirx_wr_dwc(DWC_DMI_DISABLE_IF, data32); - mdelay(1); - hdmirx_wr_dwc(DWC_DMI_SW_RST, 0x0000001F); +/* Enable functional modules */ +data32 = 0; +data32 |= 1 << 5; /* [5] cec_enable */ +data32 |= 1 << 4; /* [4] aud_enable */ +data32 |= 1 << 3; /* [3] bus_enable */ +data32 |= 1 << 2; /* [2] hdmi_enable */ +data32 |= 1 << 1; /* [1] modet_enable */ +data32 |= 1 << 0; /* [0] cfg_enable */ +hdmirx_wr_dwc(DWC_DMI_DISABLE_IF, data32); +mdelay(1); +hdmirx_wr_dwc(DWC_DMI_SW_RST, 0x0000001F); } void rx_esm_tmdsclk_en(bool en) { - hdmirx_wr_bits_top(TOP_CLK_CNTL, HDCP22_TMDSCLK_EN, en); +hdmirx_wr_bits_top(TOP_CLK_CNTL, HDCP22_TMDSCLK_EN, en); - if (log_level & HDCP_LOG) - rx_pr("%s:%d\n", __func__, en); +if (log_level & HDCP_LOG) + rx_pr("%s:%d\n", __func__, en); } /* - * hdcp22_clk_en - clock gating for hdcp2.2 - * @en: enable or disable clock - */ +* hdcp22_clk_en - clock gating for hdcp2.2 +* @en: enable or disable clock +*/ void hdcp22_clk_en(bool en) { - if (en) { - wr_reg_hhi(HHI_HDCP22_CLK_CNTL, - (rd_reg_hhi(HHI_HDCP22_CLK_CNTL) & 0xffff0000) | - /* [10: 9] fclk_div7=2000/7=285.71 MHz */ - ((0 << 9) | - /* [ 8] clk_en. Enable gated clock */ - (1 << 8) | - /* [ 6: 0] Divide by 1. = 285.71/1 = 285.71 MHz */ - (0 << 0))); +if (en) { + wr_reg_hhi(HHI_HDCP22_CLK_CNTL, + (rd_reg_hhi(HHI_HDCP22_CLK_CNTL) & 0xffff0000) | + /* [10: 9] fclk_div7=2000/7=285.71 MHz */ + ((0 << 9) | + /* [ 8] clk_en. Enable gated clock */ + (1 << 8) | + /* [ 6: 0] Divide by 1. = 285.71/1 = 285.71 MHz */ + (0 << 0))); - wr_reg_hhi(HHI_HDCP22_CLK_CNTL, - (rd_reg_hhi(HHI_HDCP22_CLK_CNTL) & 0x0000ffff) | - /* [26:25] select cts_oscin_clk=24 MHz */ - ((0 << 25) | - (1 << 24) | /* [ 24] Enable gated clock */ - (0 << 16))); + wr_reg_hhi(HHI_HDCP22_CLK_CNTL, + (rd_reg_hhi(HHI_HDCP22_CLK_CNTL) & 0x0000ffff) | + /* [26:25] select cts_oscin_clk=24 MHz */ + ((0 << 25) | + (1 << 24) | /* [ 24] Enable gated clock */ + (0 << 16))); + if (rx.hdmirxdev->data->chip_id == CHIP_ID_TL1) + /* TL1:esm related clk bit9-11 */ + hdmirx_wr_bits_top(TOP_CLK_CNTL, MSK(3, 9), 0x7); + else + /* TL1:esm related clk bit3-5 */ hdmirx_wr_bits_top(TOP_CLK_CNTL, MSK(3, 3), 0x7); - } else { - hdmirx_wr_bits_top(TOP_CLK_CNTL, MSK(3, 3), 0x0); - wr_reg_hhi(HHI_HDCP22_CLK_CNTL, 0); - } +} else { + hdmirx_wr_bits_top(TOP_CLK_CNTL, MSK(3, 3), 0x0); + wr_reg_hhi(HHI_HDCP22_CLK_CNTL, 0); +} } /* - * hdmirx_hdcp22_esm_rst - software reset esm - */ +* hdmirx_hdcp22_esm_rst - software reset esm +*/ void hdmirx_hdcp22_esm_rst(void) { - hdmirx_wr_top(TOP_SW_RESET, 0x100); - mdelay(1); - hdmirx_wr_top(TOP_SW_RESET, 0x0); - rx_pr("esm rst\n"); +hdmirx_wr_top(TOP_SW_RESET, 0x100); +mdelay(1); +hdmirx_wr_top(TOP_SW_RESET, 0x0); +rx_pr("esm rst\n"); } /* - * hdmirx_hdcp22_init - hdcp2.2 initialization - */ +* hdmirx_hdcp22_init - hdcp2.2 initialization +*/ int rx_is_hdcp22_support(void) { int ret = 0; - if (rx_sec_set_duk() == 1) { + if (rx_sec_set_duk(hdmirx_repeat_support()) == 1) { rx_hdcp22_wr_top(TOP_SKP_CNTL_STAT, 7); ret = 1; } else @@ -1403,437 +1576,485 @@ int rx_is_hdcp22_support(void) } /* - * hdmirx_hdcp22_hpd - set hpd level for hdcp2.2 - * @value: whether to set hpd high - */ +* hdmirx_hdcp22_hpd - set hpd level for hdcp2.2 +* @value: whether to set hpd high +*/ void hdmirx_hdcp22_hpd(bool value) { - unsigned long data32 = hdmirx_rd_dwc(DWC_HDCP22_CONTROL); +unsigned long data32 = hdmirx_rd_dwc(DWC_HDCP22_CONTROL); - if (value) - data32 |= 0x1000; - else - data32 &= (~0x1000); - hdmirx_wr_dwc(DWC_HDCP22_CONTROL, data32); +if (value) + data32 |= 0x1000; +else + data32 &= (~0x1000); +hdmirx_wr_dwc(DWC_HDCP22_CONTROL, data32); } /* - * hdcp22_suspend - suspend flow of hdcp2.2 - */ +* hdcp22_suspend - suspend flow of hdcp2.2 +*/ void hdcp22_suspend(void) { - hdcp22_clk_en(0); - /* note: can't pull down hpd before enter suspend */ - /* it will stop cec wake up func if EE domain still working */ - /* rx_set_cur_hpd(0); */ - hpd_to_esm = 0; - hdmirx_wr_dwc(DWC_HDCP22_CONTROL, - 0x0); - if (hdcp22_kill_esm == 0) - /* rx_pr("kill = 1\n"); */ - hdmirx_hdcp22_esm_rst(); - /* msleep(20); */ - rx_pr("hdcp22 off\n"); +hdcp22_clk_en(0); +/* note: can't pull down hpd before enter suspend */ +/* it will stop cec wake up func if EE domain still working */ +/* rx_set_cur_hpd(0); */ +hpd_to_esm = 0; +hdmirx_wr_dwc(DWC_HDCP22_CONTROL, + 0x0); +if (hdcp22_kill_esm == 0) + /* rx_pr("kill = 1\n"); */ + hdmirx_hdcp22_esm_rst(); + /* msleep(20); */ +rx_pr("hdcp22 off\n"); } /* - * hdcp22_resume - resume flow of hdcp2.2 - */ +* hdcp22_resume - resume flow of hdcp2.2 +*/ void hdcp22_resume(void) { - hdcp22_kill_esm = 0; - /* switch_set_state(&rx.hpd_sdev, 0x0); */ - extcon_set_state_sync(rx.rx_excton_rx22, EXTCON_DISP_HDMI, 0); - hdcp22_clk_en(1); - hdmirx_wr_dwc(DWC_HDCP22_CONTROL, - 0x1000); - /* rx_hdcp22_wr_top(TOP_SKP_CNTL_STAT, 0x1); */ - /* hdmirx_hw_config(); */ - /* switch_set_state(&rx.hpd_sdev, 0x1); */ - extcon_set_state_sync(rx.rx_excton_rx22, EXTCON_DISP_HDMI, 1); - hpd_to_esm = 1; - /* dont need to delay 900ms to wait sysctl start hdcp_rx22,*/ - /*sysctl is userspace it wakes up later than driver */ - /* mdelay(900); */ - /* rx_set_cur_hpd(1); */ - rx_pr("hdcp22 on\n"); +hdcp22_kill_esm = 0; +/* switch_set_state(&rx.hpd_sdev, 0x0); */ +extcon_set_state_sync(rx.rx_excton_rx22, EXTCON_DISP_HDMI, 0); +hdcp22_clk_en(1); +hdmirx_wr_dwc(DWC_HDCP22_CONTROL, + 0x1000); +/* rx_hdcp22_wr_top(TOP_SKP_CNTL_STAT, 0x1); */ +/* hdmirx_hw_config(); */ +/* switch_set_state(&rx.hpd_sdev, 0x1); */ +extcon_set_state_sync(rx.rx_excton_rx22, EXTCON_DISP_HDMI, 1); +hpd_to_esm = 1; +/* dont need to delay 900ms to wait sysctl start hdcp_rx22,*/ +/*sysctl is userspace it wakes up later than driver */ +/* mdelay(900); */ +/* rx_set_cur_hpd(1); */ +rx_pr("hdcp22 on\n"); } /* - * clk_init - clock initialization - * config clock for hdmirx module - */ +* clk_init - clock initialization +* config clock for hdmirx module +*/ void clk_init(void) { - unsigned int data32; +unsigned int data32; - /* DWC clock enable */ - /* Turn on clk_hdmirx_pclk, also = sysclk */ - wr_reg_hhi(HHI_GCLK_MPEG0, - rd_reg_hhi(HHI_GCLK_MPEG0) | (1 << 21)); +/* DWC clock enable */ +/* Turn on clk_hdmirx_pclk, also = sysclk */ +wr_reg_hhi(HHI_GCLK_MPEG0, +rd_reg_hhi(HHI_GCLK_MPEG0) | (1 << 21)); - /* Enable APB3 fail on error */ - /* APB3 to HDMIRX-TOP err_en */ - /* default 0x3ff, | bit15 = 1 | bit12 = 1 */ - hdmirx_wr_ctl_port(0, 0x93ff); - hdmirx_wr_ctl_port(0x10, 0x93ff); +/* Enable APB3 fail on error */ +/* APB3 to HDMIRX-TOP err_en */ +/* default 0x3ff, | bit15 = 1 | bit12 = 1 */ - /* turn on clocks: md, cfg... */ - /* G9 clk tree */ - /* fclk_div5 400M ----- mux sel = 3 */ - /* fclk_div3 850M ----- mux sel = 2 */ - /* fclk_div4 637M ----- mux sel = 1 */ - /* XTAL 24M ----- mux sel = 0 */ - /* [26:25] HDMIRX mode detection clock mux select: osc_clk */ - /* [24] HDMIRX mode detection clock enable */ - /* [22:16] HDMIRX mode detection clock divider */ - /* [10: 9] HDMIRX config clock mux select: */ - /* [ 8] HDMIRX config clock enable */ - /* [ 6: 0] HDMIRX config clock divider: */ - #if 0 +hdmirx_wr_ctl_port(0, 0x93ff); +hdmirx_wr_ctl_port(0x10, 0x93ff); + +/* turn on clocks: md, cfg... */ +/* G9 clk tree */ +/* fclk_div5 400M ----- mux sel = 3 */ +/* fclk_div3 850M ----- mux sel = 2 */ +/* fclk_div4 637M ----- mux sel = 1 */ +/* XTAL 24M ----- mux sel = 0 */ +/* [26:25] HDMIRX mode detection clock mux select: osc_clk */ +/* [24] HDMIRX mode detection clock enable */ +/* [22:16] HDMIRX mode detection clock divider */ +/* [10: 9] HDMIRX config clock mux select: */ +/* [ 8] HDMIRX config clock enable */ +/* [ 6: 0] HDMIRX config clock divider: */ +#if 0 +data32 = 0; +data32 |= 0 << 25; +data32 |= 1 << 24; +data32 |= 0 << 16; +data32 |= 3 << 9; +data32 |= 1 << 8; +data32 |= 2 << 0; +wr_reg_hhi(HHI_HDMIRX_CLK_CNTL, data32); + +data32 = 0; +data32 |= 2 << 25; +data32 |= acr_mode << 24; +data32 |= 0 << 16; +data32 |= 2 << 9; +data32 |= 1 << 8; +data32 |= 2 << 0; +wr_reg_hhi(HHI_HDMIRX_AUD_CLK_CNTL, data32); +#endif +if ((rx.chip_id == CHIP_ID_TXLX) || + (rx.chip_id == CHIP_ID_TXHD) || + (rx.chip_id == CHIP_ID_TL1)) { + /* [15] hdmirx_aud_pll4x_en override enable */ + /* [14] hdmirx_aud_pll4x_en override value */ + /* [6:5] clk_sel for cts_hdmirx_aud_pll_clk: */ + /* 0=hdmirx_aud_pll_clk */ + /* [4] clk_en for cts_hdmirx_aud_pll_clk */ + /* [2:0] clk_div for cts_hdmirx_aud_pll_clk */ data32 = 0; - data32 |= 0 << 25; - data32 |= 1 << 24; - data32 |= 0 << 16; - data32 |= 3 << 9; - data32 |= 1 << 8; - data32 |= 2 << 0; - wr_reg_hhi(HHI_HDMIRX_CLK_CNTL, data32); + data32 |= (0 << 15); + data32 |= (1 << 14); + data32 |= (0 << 5); + data32 |= (0 << 4); + data32 |= (0 << 0); + wr_reg_hhi(HHI_AUDPLL_CLK_OUT_CNTL, data32); + data32 |= (1 << 4); + wr_reg_hhi(HHI_AUDPLL_CLK_OUT_CNTL, data32); +} - data32 = 0; - data32 |= 2 << 25; - data32 |= acr_mode << 24; - data32 |= 0 << 16; - data32 |= 2 << 9; - data32 |= 1 << 8; - data32 |= 2 << 0; - wr_reg_hhi(HHI_HDMIRX_AUD_CLK_CNTL, data32); - #endif - if ((rx.chip_id == CHIP_ID_TXLX) || - (rx.chip_id == CHIP_ID_TXHD)) { - /* [15] hdmirx_aud_pll4x_en override enable */ - /* [14] hdmirx_aud_pll4x_en override value */ - /* [6:5] clk_sel for cts_hdmirx_aud_pll_clk: */ - /* 0=hdmirx_aud_pll_clk */ - /* [4] clk_en for cts_hdmirx_aud_pll_clk */ - /* [2:0] clk_div for cts_hdmirx_aud_pll_clk */ - data32 = 0; - data32 |= (0 << 15); - data32 |= (1 << 14); - data32 |= (0 << 5); - data32 |= (0 << 4); - data32 |= (0 << 0); - wr_reg_hhi(HHI_AUDPLL_CLK_OUT_CNTL, data32); - data32 |= (1 << 4); - wr_reg_hhi(HHI_AUDPLL_CLK_OUT_CNTL, data32); - } - - data32 = hdmirx_rd_top(TOP_CLK_CNTL); - data32 |= 0 << 31; /* [31] disable clkgating */ - data32 |= 1 << 17; /* [17] audfifo_rd_en */ - data32 |= 1 << 16; /* [16] pktfifo_rd_en */ +data32 = hdmirx_rd_top(TOP_CLK_CNTL); +data32 |= 0 << 31; /* [31] disable clkgating */ +data32 |= 1 << 17; /* [17] audfifo_rd_en */ +data32 |= 1 << 16; /* [16] pktfifo_rd_en */ +if (rx.hdmirxdev->data->chip_id == CHIP_ID_TL1) { + data32 |= 0 << 8; /* [8] tmds_ch2_clk_inv */ + data32 |= 0 << 7; /* [7] tmds_ch1_clk_inv */ + data32 |= 0 << 6; /* [6] tmds_ch0_clk_inv */ + data32 |= 0 << 5; /* [5] pll4x_cfg */ + /* force_pll4x: + * 1=Force pll4x_en value to be pll4x_cfg. + * 0=Use auto detect. + */ + data32 |= 0 << 4; /* [4] force_pll4x */ + data32 |= 0 << 3; /* [3] phy_clk_inv: 1-invert */ +} else { data32 |= 1 << 2; /* [2] hdmirx_cecclk_en */ data32 |= 0 << 1; /* [1] bus_clk_inv */ data32 |= 0 << 0; /* [0] hdmi_clk_inv */ - hdmirx_wr_top(TOP_CLK_CNTL, data32); /* DEFAULT: {32'h0} */ +} +hdmirx_wr_top(TOP_CLK_CNTL, data32); /* DEFAULT: {32'h0} */ } /* - * hdmirx_20_init - hdmi2.0 config - */ +* hdmirx_20_init - hdmi2.0 config +*/ void hdmirx_20_init(void) { - unsigned long data32; +unsigned long data32; - data32 = 0; - data32 |= 1 << 12; /* [12] vid_data_checken */ - data32 |= 1 << 11; /* [11] data_island_checken */ - data32 |= 1 << 10; /* [10] gb_checken */ - data32 |= 1 << 9; /* [9] preamb_checken */ - data32 |= 1 << 8; /* [8] ctrl_checken */ - data32 |= 1 << 4; /* [4] scdc_enable */ - data32 |= SCRAMBLE_SEL << 0; /* [1:0] scramble_sel */ - hdmirx_wr_dwc(DWC_HDMI20_CONTROL, data32); +data32 = 0; +data32 |= 1 << 12; /* [12] vid_data_checken */ +data32 |= 1 << 11; /* [11] data_island_checken */ +data32 |= 1 << 10; /* [10] gb_checken */ +data32 |= 1 << 9; /* [9] preamb_checken */ +data32 |= 1 << 8; /* [8] ctrl_checken */ +data32 |= 1 << 4; /* [4] scdc_enable */ +/* To support some TX that sends out SSCP even when not scrambling: + * 0: Original behaviour + * 1: During TMDS character error detection, treat SSCP character + * as normal TMDS character. + * Note: If scramble is turned on, this bit will not take effect, + * revert to original IP behaviour. + */ +data32 |= ignore_sscp_charerr << 3; /* [3]ignore sscp character err */ +/* To support some TX that sends out SSCP even when not scrambling: + * 0: Original behaviour + * 1: During TMDS decoding, treat SSCP character + * as normal TMDS character + * Note: If scramble is turned on, this bit will not take effect, + * revert to original IP behaviour. + */ +data32 |= ignore_sscp_tmds << 2; /* [2] ignore sscp tmds */ +data32 |= SCRAMBLE_SEL << 0; /* [1:0] scramble_sel */ +hdmirx_wr_dwc(DWC_HDMI20_CONTROL, data32); - data32 = 0; - data32 |= 1 << 24; /* [25:24] i2c_spike_suppr */ - data32 |= 0 << 20; /* [20] i2c_timeout_en */ - data32 |= 0 << 0; /* [19:0] i2c_timeout_cnt */ - hdmirx_wr_dwc(DWC_SCDC_I2CCONFIG, data32); +data32 = 0; +data32 |= 1 << 24; /* [25:24] i2c_spike_suppr */ +data32 |= 0 << 20; /* [20] i2c_timeout_en */ +data32 |= 0 << 0; /* [19:0] i2c_timeout_cnt */ +hdmirx_wr_dwc(DWC_SCDC_I2CCONFIG, data32); - data32 = 0; - data32 |= 0 << 1; /* [1] hpd_low */ - data32 |= 1 << 0; /* [0] power_provided */ - hdmirx_wr_dwc(DWC_SCDC_CONFIG, data32); +data32 = 0; +data32 |= 0 << 1; /* [1] hpd_low */ +data32 |= 1 << 0; /* [0] power_provided */ +hdmirx_wr_dwc(DWC_SCDC_CONFIG, data32); - data32 = 0; - data32 |= 0xabcdef << 8; /* [31:8] manufacture_oui */ - data32 |= 1 << 0; /* [7:0] sink_version */ - hdmirx_wr_dwc(DWC_SCDC_WRDATA0, data32); +data32 = 0; +data32 |= 0xabcdef << 8; /* [31:8] manufacture_oui */ +data32 |= 1 << 0; /* [7:0] sink_version */ +hdmirx_wr_dwc(DWC_SCDC_WRDATA0, data32); - data32 = 0; - data32 |= 10 << 20; /* [29:20] chlock_max_err */ - data32 |= 24000 << 0; /* [15:0] milisec_timer_limit */ - hdmirx_wr_dwc(DWC_CHLOCK_CONFIG, data32); +data32 = 0; +data32 |= 10 << 20; /* [29:20] chlock_max_err */ +data32 |= 24000 << 0; /* [15:0] milisec_timer_limit */ +hdmirx_wr_dwc(DWC_CHLOCK_CONFIG, data32); - /* hdcp2.2 ctl */ - if (hdcp22_on) - hdmirx_wr_dwc(DWC_HDCP22_CONTROL, 0x1000); - else - hdmirx_wr_dwc(DWC_HDCP22_CONTROL, 2); +/* hdcp2.2 ctl */ +if (hdcp22_on) + hdmirx_wr_dwc(DWC_HDCP22_CONTROL, 0x1000); +else + hdmirx_wr_dwc(DWC_HDCP22_CONTROL, 2); } /* - * hdmirx_audio_init - audio initialization - */ +* hdmirx_audio_init - audio initialization +*/ int hdmirx_audio_init(void) { - /* 0=I2S 2-channel; 1=I2S 4 x 2-channel. */ - int err = 0; - unsigned long data32 = 0; +/* 0=I2S 2-channel; 1=I2S 4 x 2-channel. */ +int err = 0; +unsigned long data32 = 0; - data32 |= 7 << 13; - data32 |= 0 << 12; - data32 |= 1 << 11; - data32 |= 0 << 10; +data32 |= 7 << 13; +data32 |= 0 << 12; +data32 |= 1 << 11; +data32 |= 0 << 10; - data32 |= 0 << 9; - data32 |= 1 << 8; - data32 |= 1 << 6; - data32 |= 3 << 4; - data32 |= 0 << 3; - data32 |= acr_mode << 2; - data32 |= acr_mode << 1; - data32 |= acr_mode << 0; - hdmirx_wr_top(TOP_ACR_CNTL_STAT, data32); +data32 |= 0 << 9; +data32 |= 1 << 8; +data32 |= 1 << 6; +data32 |= 3 << 4; +data32 |= 0 << 3; +data32 |= acr_mode << 2; +data32 |= acr_mode << 1; +data32 |= acr_mode << 0; +hdmirx_wr_top(TOP_ACR_CNTL_STAT, data32); - /* - *recover to default value, bit[27:24] - *set aud_pll_lock filter - *data32 = 0; - *data32 |= 0 << 28; - *data32 |= 0 << 24; - *hdmirx_wr_dwc(DWC_AUD_PLL_CTRL, data32); - */ +/* + *recover to default value, bit[27:24] + *set aud_pll_lock filter + *data32 = 0; + *data32 |= 0 << 28; + *data32 |= 0 << 24; + *hdmirx_wr_dwc(DWC_AUD_PLL_CTRL, data32); + */ - /* AFIFO depth 1536word.*/ - /*increase start threshold to middle position */ - data32 = 0; - data32 |= 160 << 18; /* start */ - data32 |= 200 << 9; /* max */ - data32 |= 8 << 0; /* min */ - hdmirx_wr_dwc(DWC_AUD_FIFO_TH, data32); +/* AFIFO depth 1536word.*/ +/*increase start threshold to middle position */ +data32 = 0; +data32 |= 160 << 18; /* start */ +data32 |= 200 << 9; /* max */ +data32 |= 8 << 0; /* min */ +hdmirx_wr_dwc(DWC_AUD_FIFO_TH, data32); - /* recover to default value.*/ - /*remain code for some time.*/ - /*if no side effect then remove it */ - /* - *data32 = 0; - *data32 |= 1 << 16; - *data32 |= 0 << 0; - *hdmirx_wr_dwc(DWC_AUD_FIFO_CTRL, data32); - */ +/* recover to default value.*/ +/*remain code for some time.*/ +/*if no side effect then remove it */ +/* + *data32 = 0; + *data32 |= 1 << 16; + *data32 |= 0 << 0; + *hdmirx_wr_dwc(DWC_AUD_FIFO_CTRL, data32); + */ - data32 = 0; - data32 |= 0 << 8; - data32 |= 1 << 7; - data32 |= aud_ch_map << 2; - data32 |= 1 << 0; - hdmirx_wr_dwc(DWC_AUD_CHEXTR_CTRL, data32); +data32 = 0; +data32 |= 0 << 8; +data32 |= 1 << 7; +data32 |= aud_ch_map << 2; +data32 |= 1 << 0; +hdmirx_wr_dwc(DWC_AUD_CHEXTR_CTRL, data32); - data32 = 0; - /* [22:21] aport_shdw_ctrl */ - data32 |= 3 << 21; - /* [20:19] auto_aclk_mute */ - data32 |= auto_aclk_mute << 19; - /* [16:10] aud_mute_speed */ - data32 |= 1 << 10; - /* [7] aud_avmute_en */ - data32 |= aud_avmute_en << 7; - /* [6:5] aud_mute_sel */ - data32 |= aud_mute_sel << 5; - /* [4:3] aud_mute_mode */ - data32 |= 1 << 3; - /* [2:1] aud_ttone_fs_sel */ - data32 |= 0 << 1; - /* [0] testtone_en */ - data32 |= 0 << 0; - hdmirx_wr_dwc(DWC_AUD_MUTE_CTRL, data32); +data32 = 0; +/* [22:21] aport_shdw_ctrl */ +data32 |= 3 << 21; +/* [20:19] auto_aclk_mute */ +data32 |= auto_aclk_mute << 19; +/* [16:10] aud_mute_speed */ +data32 |= 1 << 10; +/* [7] aud_avmute_en */ +data32 |= aud_avmute_en << 7; +/* [6:5] aud_mute_sel */ +data32 |= aud_mute_sel << 5; +/* [4:3] aud_mute_mode */ +data32 |= 1 << 3; +/* [2:1] aud_ttone_fs_sel */ +data32 |= 0 << 1; +/* [0] testtone_en */ +data32 |= 0 << 0; +hdmirx_wr_dwc(DWC_AUD_MUTE_CTRL, data32); - /* recover to default value.*/ - /*remain code for some time.*/ - /*if no side effect then remove it */ - /* - *data32 = 0; - *data32 |= 0 << 16; - *data32 |= 0 << 12; - *data32 |= 0 << 4; - *data32 |= 0 << 1; - *data32 |= 0 << 0; - *hdmirx_wr_dwc(DWC_AUD_PAO_CTRL, data32); - */ +/* recover to default value.*/ +/*remain code for some time.*/ +/*if no side effect then remove it */ +/* + *data32 = 0; + *data32 |= 0 << 16; + *data32 |= 0 << 12; + *data32 |= 0 << 4; + *data32 |= 0 << 1; + *data32 |= 0 << 0; + *hdmirx_wr_dwc(DWC_AUD_PAO_CTRL, data32); + */ - /* recover to default value.*/ - /*remain code for some time.*/ - /*if no side effect then remove it */ - /* - *data32 = 0; - *data32 |= 0 << 8; - *hdmirx_wr_dwc(DWC_PDEC_AIF_CTRL, data32); - */ +/* recover to default value.*/ +/*remain code for some time.*/ +/*if no side effect then remove it */ +/* + *data32 = 0; + *data32 |= 0 << 8; + *hdmirx_wr_dwc(DWC_PDEC_AIF_CTRL, data32); + */ - data32 = 0; - /* [4:2] deltacts_irqtrig */ - data32 |= 0 << 2; - /* [1:0] cts_n_meas_mode */ - data32 |= 0 << 0; - /* DEFAULT: {27'd0, 3'd0, 2'd1} */ - hdmirx_wr_dwc(DWC_PDEC_ACRM_CTRL, data32); +data32 = 0; +/* [4:2] deltacts_irqtrig */ +data32 |= 0 << 2; +/* [1:0] cts_n_meas_mode */ +data32 |= 0 << 0; +/* DEFAULT: {27'd0, 3'd0, 2'd1} */ +hdmirx_wr_dwc(DWC_PDEC_ACRM_CTRL, data32); - hdmirx_wr_bits_dwc(DWC_AUD_CTRL, DWC_AUD_HBR_ENABLE, 1); +hdmirx_wr_bits_dwc(DWC_AUD_CTRL, DWC_AUD_HBR_ENABLE, 1); - /* SAO cfg, disable I2S output, no use */ - data32 = 0; - data32 |= 1 << 10; - data32 |= 0 << 9; - data32 |= 0x0f << 5; - data32 |= 0 << 1; - data32 |= 1 << 0; - hdmirx_wr_dwc(DWC_AUD_SAO_CTRL, data32); +/* SAO cfg, disable I2S output, no use */ +data32 = 0; +data32 |= 1 << 10; +data32 |= 0 << 9; +data32 |= 0x0f << 5; +data32 |= 0 << 1; +data32 |= 1 << 0; +hdmirx_wr_dwc(DWC_AUD_SAO_CTRL, data32); - data32 = 0; - data32 |= 1 << 6; - data32 |= 0xf << 2; - hdmirx_wr_dwc(DWC_PDEC_ASP_CTRL, data32); +data32 = 0; +data32 |= 1 << 6; +data32 |= 0xf << 2; +hdmirx_wr_dwc(DWC_PDEC_ASP_CTRL, data32); - return err; +return err; } /* - * hdmirx_phy_init - hdmirx phy initialization - */ +* snps phy g3 initial +*/ +void snps_phyg3_init(void) +{ +unsigned int data32; +unsigned int term_value = + hdmirx_rd_top(TOP_HPD_PWR5V); + +data32 = 0; +data32 |= 1 << 6; +data32 |= 1 << 4; +data32 |= rx.port << 2; +data32 |= 1 << 1; +data32 |= 1 << 0; +hdmirx_wr_dwc(DWC_SNPS_PHYG3_CTRL, data32); +mdelay(1); + +data32 = 0; +data32 |= 1 << 6; +data32 |= 1 << 4; +data32 |= rx.port << 2; +data32 |= 1 << 1; +data32 |= 0 << 0; +hdmirx_wr_dwc(DWC_SNPS_PHYG3_CTRL, data32); + +data32 = 0; +data32 |= phy_lock_thres << 10; +data32 |= 1 << 9; +data32 |= ((phy_cfg_clk * 4) / 1000); +hdmirx_wr_phy(PHY_CMU_CONFIG, data32); + +hdmirx_wr_phy(PHY_VOLTAGE_LEVEL, eq_ref_voltage); + +data32 = 0; +data32 |= 0 << 15; +data32 |= 0 << 13; +data32 |= 0 << 12; +data32 |= phy_fast_switching << 11; +data32 |= 0 << 10; +data32 |= phy_fsm_enhancement << 9; +data32 |= 0 << 8; +data32 |= 0 << 7; +data32 |= 0 << 5; +data32 |= 0 << 3; +data32 |= 0 << 2; +data32 |= 0 << 0; +hdmirx_wr_phy(PHY_SYSTEM_CONFIG, data32); + +hdmirx_wr_phy(MPLL_PARAMETERS2, 0x1c94); +hdmirx_wr_phy(MPLL_PARAMETERS3, 0x3713); +/*default 0x24da , EQ optimizing for kaiboer box */ +hdmirx_wr_phy(MPLL_PARAMETERS4, 0x24dc); +hdmirx_wr_phy(MPLL_PARAMETERS5, 0x5492); +hdmirx_wr_phy(MPLL_PARAMETERS6, 0x4b0d); +hdmirx_wr_phy(MPLL_PARAMETERS7, 0x4760); +hdmirx_wr_phy(MPLL_PARAMETERS8, 0x008c); +hdmirx_wr_phy(MPLL_PARAMETERS9, 0x0010); +hdmirx_wr_phy(MPLL_PARAMETERS10, 0x2d20); +hdmirx_wr_phy(MPLL_PARAMETERS11, 0x2e31); +hdmirx_wr_phy(MPLL_PARAMETERS12, 0x4b64); +hdmirx_wr_phy(MPLL_PARAMETERS13, 0x2493); +hdmirx_wr_phy(MPLL_PARAMETERS14, 0x676d); +hdmirx_wr_phy(MPLL_PARAMETERS15, 0x23e0); +hdmirx_wr_phy(MPLL_PARAMETERS16, 0x001b); +hdmirx_wr_phy(MPLL_PARAMETERS17, 0x2218); +hdmirx_wr_phy(MPLL_PARAMETERS18, 0x1b25); +hdmirx_wr_phy(MPLL_PARAMETERS19, 0x2492); +hdmirx_wr_phy(MPLL_PARAMETERS20, 0x48ea); +hdmirx_wr_phy(MPLL_PARAMETERS21, 0x0011); +hdmirx_wr_phy(MPLL_PARAMETERS22, 0x04d2); +hdmirx_wr_phy(MPLL_PARAMETERS23, 0x0414); + +/* Configuring I2C to work in fastmode */ +hdmirx_wr_dwc(DWC_I2CM_PHYG3_MODE, 0x1); +/* disable overload protect for Philips DVD */ +/* NOTE!!!!! don't remove below setting */ +hdmirx_wr_phy(OVL_PROT_CTRL, 0xa); + +/* clear clkrate cfg */ +hdmirx_wr_bits_phy(PHY_CDR_CTRL_CNT, CLK_RATE_BIT, 0); +last_clk_rate = 0; + +/* enable all ports's termination */ +data32 = 0; +data32 |= 1 << 8; +data32 |= ((term_value & 0xF) << 4); +hdmirx_wr_phy(PHY_MAIN_FSM_OVERRIDE1, data32); + +data32 = 0; +data32 |= 1 << 6; +data32 |= 1 << 4; +data32 |= rx.port << 2; +data32 |= 0 << 1; +data32 |= 0 << 0; +hdmirx_wr_dwc(DWC_SNPS_PHYG3_CTRL, data32); + +} + +/* +* hdmirx_phy_init - hdmirx phy initialization +*/ void hdmirx_phy_init(void) { - unsigned int data32; - unsigned int term_value = - hdmirx_rd_top(TOP_HPD_PWR5V); - - data32 = 0; - data32 |= 1 << 6; - data32 |= 1 << 4; - data32 |= rx.port << 2; - data32 |= 1 << 1; - data32 |= 1 << 0; - hdmirx_wr_dwc(DWC_SNPS_PHYG3_CTRL, data32); - mdelay(1); - - data32 = 0; - data32 |= 1 << 6; - data32 |= 1 << 4; - data32 |= rx.port << 2; - data32 |= 1 << 1; - data32 |= 0 << 0; - hdmirx_wr_dwc(DWC_SNPS_PHYG3_CTRL, data32); - - data32 = 0; - data32 |= phy_lock_thres << 10; - data32 |= 1 << 9; - data32 |= ((phy_cfg_clk * 4) / 1000); - hdmirx_wr_phy(PHY_CMU_CONFIG, data32); - - hdmirx_wr_phy(PHY_VOLTAGE_LEVEL, eq_ref_voltage); - - data32 = 0; - data32 |= 0 << 15; - data32 |= 0 << 13; - data32 |= 0 << 12; - data32 |= phy_fast_switching << 11; - data32 |= 0 << 10; - data32 |= phy_fsm_enhancement << 9; - data32 |= 0 << 8; - data32 |= 0 << 7; - data32 |= 0 << 5; - data32 |= 0 << 3; - data32 |= 0 << 2; - data32 |= 0 << 0; - hdmirx_wr_phy(PHY_SYSTEM_CONFIG, data32); - - hdmirx_wr_phy(MPLL_PARAMETERS2, 0x1c94); - hdmirx_wr_phy(MPLL_PARAMETERS3, 0x3713); - /*default 0x24da , EQ optimizing for kaiboer box */ - hdmirx_wr_phy(MPLL_PARAMETERS4, 0x24dc); - hdmirx_wr_phy(MPLL_PARAMETERS5, 0x5492); - hdmirx_wr_phy(MPLL_PARAMETERS6, 0x4b0d); - hdmirx_wr_phy(MPLL_PARAMETERS7, 0x4760); - hdmirx_wr_phy(MPLL_PARAMETERS8, 0x008c); - hdmirx_wr_phy(MPLL_PARAMETERS9, 0x0010); - hdmirx_wr_phy(MPLL_PARAMETERS10, 0x2d20); - hdmirx_wr_phy(MPLL_PARAMETERS11, 0x2e31); - hdmirx_wr_phy(MPLL_PARAMETERS12, 0x4b64); - hdmirx_wr_phy(MPLL_PARAMETERS13, 0x2493); - hdmirx_wr_phy(MPLL_PARAMETERS14, 0x676d); - hdmirx_wr_phy(MPLL_PARAMETERS15, 0x23e0); - hdmirx_wr_phy(MPLL_PARAMETERS16, 0x001b); - hdmirx_wr_phy(MPLL_PARAMETERS17, 0x2218); - hdmirx_wr_phy(MPLL_PARAMETERS18, 0x1b25); - hdmirx_wr_phy(MPLL_PARAMETERS19, 0x2492); - hdmirx_wr_phy(MPLL_PARAMETERS20, 0x48ea); - hdmirx_wr_phy(MPLL_PARAMETERS21, 0x0011); - hdmirx_wr_phy(MPLL_PARAMETERS22, 0x04d2); - hdmirx_wr_phy(MPLL_PARAMETERS23, 0x0414); - - /* Configuring I2C to work in fastmode */ - hdmirx_wr_dwc(DWC_I2CM_PHYG3_MODE, 0x1); - /* disable overload protect for Philips DVD */ - /* NOTE!!!!! don't remove below setting */ - hdmirx_wr_phy(OVL_PROT_CTRL, 0xa); - - /* clear clkrate cfg */ - hdmirx_wr_bits_phy(PHY_CDR_CTRL_CNT, CLK_RATE_BIT, 0); - last_clk_rate = 0; - - #if 1 - /* enable all ports's termination */ - data32 = 0; - data32 |= 1 << 8; - data32 |= ((term_value & 0xF) << 4); - hdmirx_wr_phy(PHY_MAIN_FSM_OVERRIDE1, data32); +if (rx.hdmirxdev->data->chip_id == CHIP_ID_TL1) { + #ifdef K_BRINGUP_PTM + return; #endif + /* give default value */ + aml_phy_bw_switch(100000, 0); +} else { + snps_phyg3_init(); +} - data32 = 0; - data32 |= 1 << 6; - data32 |= 1 << 4; - data32 |= rx.port << 2; - data32 |= 0 << 1; - data32 |= 0 << 0; - hdmirx_wr_dwc(DWC_SNPS_PHYG3_CTRL, data32); - rx_pr("%s Done!\n", __func__); +rx_pr("%s Done!\n", __func__); } /* - * rx_clkrate_monitor - clock ratio monitor - * detect SCDC tmds clk ratio changes and - * update phy setting - */ +* rx_clkrate_monitor - clock ratio monitor +* detect SCDC tmds clk ratio changes and +* update phy setting +*/ bool rx_clkrate_monitor(void) { - unsigned int clk_rate; - bool changed = false; - int i; - int error = 0; +unsigned int clk_rate; +bool changed = false; +int i; +int error = 0; - if (rx.chip_id == CHIP_ID_TXHD) - return false; +if (rx.chip_id == CHIP_ID_TXHD) + return false; - if (force_clk_rate & 0x10) - clk_rate = force_clk_rate & 1; - else - clk_rate = (hdmirx_rd_dwc(DWC_SCDC_REGS0) >> 17) & 1; +if (force_clk_rate & 0x10) + clk_rate = force_clk_rate & 1; +else + clk_rate = (hdmirx_rd_dwc(DWC_SCDC_REGS0) >> 17) & 1; - if (clk_rate != last_clk_rate) { - changed = true; +if (clk_rate != last_clk_rate) { + changed = true; + if (rx.chip_id != CHIP_ID_TL1) { for (i = 0; i < 3; i++) { error = hdmirx_wr_bits_phy(PHY_CDR_CTRL_CNT, CLK_RATE_BIT, clk_rate); @@ -1841,63 +2062,105 @@ bool rx_clkrate_monitor(void) if (error == 0) break; } - if (log_level & VIDEO_LOG) - rx_pr("clk_rate:%d, last_clk_rate: %d\n", - clk_rate, last_clk_rate); - last_clk_rate = clk_rate; - if (rx.state >= FSM_WAIT_CLK_STABLE) - rx.state = FSM_WAIT_CLK_STABLE; } - return changed; + if (log_level & VIDEO_LOG) + rx_pr("clk_rate:%d, last_clk_rate: %d\n", + clk_rate, last_clk_rate); + last_clk_rate = clk_rate; + if (rx.state >= FSM_WAIT_CLK_STABLE) + rx.state = FSM_WAIT_CLK_STABLE; +} +return changed; } /* - * rx_hdcp_init - hdcp1.4 init and enable - */ +* rx_hdcp_init - hdcp1.4 init and enable +*/ void rx_hdcp_init(void) { - if (hdcp_enable) - rx_hdcp14_config(&rx.hdcp); +if (hdcp_enable) + rx_hdcp14_config(&rx.hdcp); +else + hdmirx_wr_bits_dwc(DWC_HDCP_CTRL, ENCRIPTION_ENABLE, 0); +} + +/*type 1 pull down hpd,reset hdcp2.2 + *type 2 only pull down hpd + */ +void hdmirx_load_firm_reset(int type) +{ + int ret = 0; + + rx_pr("%s\n", __func__); + rx_pr("3firm_change:%d,repeat_plug:%d,repeat:%d\n", + rx.firm_change, repeat_plug, rx.hdcp.repeat); + /*wait the fsm end*/ + rx.firm_change = 1; + msleep(20); + /*External_Mute(1);rx_aud_pll_ctl(0);*/ + rx_set_cur_hpd(0); + /*type 2 only pull down hpd*/ + if (type == 2) { + downstream_hpd_flag = 0; + fsm_restart(); + return; + } + if (!repeat_plug) + downstream_hpd_flag = 1; else - hdmirx_wr_bits_dwc(DWC_HDCP_CTRL, ENCRIPTION_ENABLE, 0); + downstream_hpd_flag = 0; + ret = rx_sec_set_duk(hdmirx_repeat_support()); + rx_pr("ret = %d\n", ret); + if (ret == 1) { + hdmirx_wr_dwc(DWC_HDCP22_CONTROL, 0x0); + hdmirx_hdcp22_esm_rst(); + mdelay(100); + hdmirx_wr_dwc(DWC_HDCP22_CONTROL, + 0x1000); + rx_hdcp22_wr_top(TOP_SKP_CNTL_STAT, 0x1); + fsm_restart(); + rx_is_hdcp22_support(); + } + rx_pr("4firm_change:%d,repeat_plug:%d,repeat:%d\n", + rx.firm_change, repeat_plug, rx.hdcp.repeat); } /* need reset bandgap when - * aud_clk=0 & req_clk!=0 - * according to analog team's request - */ +* aud_clk=0 & req_clk!=0 +* according to analog team's request +*/ void rx_audio_bandgap_rst(void) { - vdac_enable(0, 0x10); - udelay(20); - vdac_enable(1, 0x10); - if (log_level & AUDIO_LOG) - rx_pr("%s\n", __func__); +vdac_enable(0, 0x10); +udelay(20); +vdac_enable(1, 0x10); +if (log_level & AUDIO_LOG) + rx_pr("%s\n", __func__); } void rx_sw_reset(int level) { - unsigned long data32 = 0; +unsigned long data32 = 0; - if (level == 1) { - data32 |= 0 << 7; /* [7]vid_enable */ - data32 |= 0 << 5; /* [5]cec_enable */ - data32 |= 0 << 4; /* [4]aud_enable */ - data32 |= 0 << 3; /* [3]bus_enable */ - data32 |= 0 << 2; /* [2]hdmi_enable */ - data32 |= 1 << 1; /* [1]modet_enable */ - data32 |= 0 << 0; /* [0]cfg_enable */ +if (level == 1) { + data32 |= 0 << 7; /* [7]vid_enable */ + data32 |= 0 << 5; /* [5]cec_enable */ + data32 |= 0 << 4; /* [4]aud_enable */ + data32 |= 0 << 3; /* [3]bus_enable */ + data32 |= 0 << 2; /* [2]hdmi_enable */ + data32 |= 1 << 1; /* [1]modet_enable */ + data32 |= 0 << 0; /* [0]cfg_enable */ - } else if (level == 2) { - data32 |= 0 << 7; /* [7]vid_enable */ - data32 |= 0 << 5; /* [5]cec_enable */ - data32 |= 1 << 4; /* [4]aud_enable */ - data32 |= 0 << 3; /* [3]bus_enable */ - data32 |= 1 << 2; /* [2]hdmi_enable */ - data32 |= 1 << 1; /* [1]modet_enable */ - data32 |= 0 << 0; /* [0]cfg_enable */ - } - hdmirx_wr_dwc(DWC_DMI_SW_RST, data32); +} else if (level == 2) { + data32 |= 0 << 7; /* [7]vid_enable */ + data32 |= 0 << 5; /* [5]cec_enable */ + data32 |= 1 << 4; /* [4]aud_enable */ + data32 |= 0 << 3; /* [3]bus_enable */ + data32 |= 1 << 2; /* [2]hdmi_enable */ + data32 |= 1 << 1; /* [1]modet_enable */ + data32 |= 0 << 0; /* [0]cfg_enable */ +} +hdmirx_wr_dwc(DWC_DMI_SW_RST, data32); } void hdmirx_hw_config(void) @@ -1915,8 +2178,10 @@ void hdmirx_hw_config(void) hdmirx_phy_init(); hdmirx_wr_top(TOP_INTR_MASKN, top_intr_maskn_value); rx_pr("%s %d Done!\n", __func__, rx.port); + /* hdmi reset will cause cec not working*/ + /* cec modult need reset */ if (rx.chip_id <= CHIP_ID_TXL) - cec_hw_reset(); + cec_hw_reset(1);/*1:snps cec*/ } /* @@ -1924,124 +2189,145 @@ void hdmirx_hw_config(void) */ void hdmirx_hw_probe(void) { - hdmirx_wr_top(TOP_MEM_PD, 0); - hdmirx_wr_top(TOP_INTR_MASKN, 0); - hdmirx_wr_top(TOP_SW_RESET, 0); - clk_init(); - TOP_init(); - control_reset(); - DWC_init(); - hdmi_rx_top_edid_update(); - /*hdmirx_irq_enable(FALSE);*/ - /*hdmirx_irq_hdcp22_enable(FALSE);*/ - hdcp22_clk_en(1); - hdmirx_audio_init(); - packet_init(); - if (rx.chip_id != CHIP_ID_TXHD) - hdmirx_20_init(); - hdmirx_phy_init(); - hdmirx_wr_top(TOP_PORT_SEL, 0x10); - hdmirx_wr_top(TOP_INTR_STAT_CLR, ~0); - hdmirx_wr_top(TOP_INTR_MASKN, top_intr_maskn_value); - /* rx_pr("%s Done!\n", __func__); */ +hdmirx_wr_top(TOP_MEM_PD, 0); +hdmirx_wr_top(TOP_INTR_MASKN, 0); +hdmirx_wr_top(TOP_SW_RESET, 0); +clk_init(); +TOP_init(); +control_reset(); +DWC_init(); +rx_emp_to_ddr_init(); +hdmi_rx_top_edid_update(); +/*hdmirx_irq_enable(FALSE);*/ +/*hdmirx_irq_hdcp22_enable(FALSE);*/ +hdcp22_clk_en(1); +hdmirx_audio_init(); +packet_init(); +if (rx.chip_id != CHIP_ID_TXHD) + hdmirx_20_init(); +hdmirx_phy_init(); +hdmirx_wr_top(TOP_PORT_SEL, 0x10); +hdmirx_wr_top(TOP_INTR_STAT_CLR, ~0); +hdmirx_wr_top(TOP_INTR_MASKN, top_intr_maskn_value); +/* rx_pr("%s Done!\n", __func__); */ } /* - * rx_audio_pll_sw_update - * Sent an update pulse to audio pll module. - * Indicate the ACR info is changed. - */ +* rx_audio_pll_sw_update +* Sent an update pulse to audio pll module. +* Indicate the ACR info is changed. +*/ void rx_audio_pll_sw_update(void) { - hdmirx_wr_bits_top(TOP_ACR_CNTL_STAT, _BIT(11), 1); +hdmirx_wr_bits_top(TOP_ACR_CNTL_STAT, _BIT(11), 1); } /* - * func: rx_acr_info_update - * refresh aud_pll by manual N/CTS changing - */ +* func: rx_acr_info_update +* refresh aud_pll by manual N/CTS changing +*/ void rx_acr_info_sw_update(void) { - hdmirx_wr_dwc(DWC_AUD_CLK_CTRL, 0x10); - udelay(100); - hdmirx_wr_dwc(DWC_AUD_CLK_CTRL, 0x0); +hdmirx_wr_dwc(DWC_AUD_CLK_CTRL, 0x10); +udelay(100); +hdmirx_wr_dwc(DWC_AUD_CLK_CTRL, 0x0); } /* - * is_afifo_error - audio fifo unnormal detection - * check if afifo block or not - * bit4: indicate FIFO is overflow - * bit3: indicate FIFO is underflow - * bit2: start threshold pass - * bit1: wr point above max threshold - * bit0: wr point below mix threshold - * - * return true if afifo under/over flow, false otherwise. - */ +* is_afifo_error - audio fifo unnormal detection +* check if afifo block or not +* bit4: indicate FIFO is overflow +* bit3: indicate FIFO is underflow +* bit2: start threshold pass +* bit1: wr point above max threshold +* bit0: wr point below mix threshold +* +* return true if afifo under/over flow, false otherwise. +*/ bool is_afifo_error(void) { - bool ret = false; +bool ret = false; - if ((hdmirx_rd_dwc(DWC_AUD_FIFO_STS) & - (OVERFL_STS | UNDERFL_STS)) != 0) { - ret = true; - if (log_level & AUDIO_LOG) - rx_pr("afifo err\n"); - } - return ret; +if ((hdmirx_rd_dwc(DWC_AUD_FIFO_STS) & + (OVERFL_STS | UNDERFL_STS)) != 0) { + ret = true; + if (log_level & AUDIO_LOG) + rx_pr("afifo err\n"); +} +return ret; } /* - * is_aud_pll_error - audio clock range detection - * noraml mode: aud_pll = aud_sample_rate * 128 - * HBR: aud_pll = aud_sample_rate * 128 * 4 - * - * return true if audio clock is in range, false otherwise. - */ +* is_aud_pll_error - audio clock range detection +* noraml mode: aud_pll = aud_sample_rate * 128 +* HBR: aud_pll = aud_sample_rate * 128 * 4 +* +* return true if audio clock is in range, false otherwise. +*/ bool is_aud_pll_error(void) { - bool ret = true; - int32_t clk = hdmirx_get_audio_clock(); - int32_t aud_128fs = rx.aud_info.real_sr * 128; - int32_t aud_512fs = rx.aud_info.real_sr * 512; +bool ret = true; +int32_t clk = rx_measure_clock(MEASURE_CLK_AUD_PLL); +int32_t aud_128fs = rx.aud_info.real_sr * 128; +int32_t aud_512fs = rx.aud_info.real_sr * 512; - if (rx.aud_info.real_sr == 0) - return false; - if ((abs(clk - aud_128fs) < AUD_PLL_THRESHOLD) || - (abs(clk - aud_512fs) < AUD_PLL_THRESHOLD)) { - ret = false; - } - if ((ret) && (log_level & AUDIO_LOG)) - rx_pr("clk:%d,128fs:%d,512fs:%d,\n", clk, aud_128fs, aud_512fs); - return ret; +if (rx.aud_info.real_sr == 0) + return false; +if ((abs(clk - aud_128fs) < AUD_PLL_THRESHOLD) || + (abs(clk - aud_512fs) < AUD_PLL_THRESHOLD)) { + ret = false; +} +if ((ret) && (log_level & AUDIO_LOG)) + rx_pr("clk:%d,128fs:%d,512fs:%d,\n", clk, aud_128fs, aud_512fs); +return ret; } /* - * rx_aud_pll_ctl - audio pll config - */ +* rx_aud_pll_ctl - audio pll config +*/ void rx_aud_pll_ctl(bool en) { int tmp = 0; + /*unsigned int od, od2;*/ - if (en) { - tmp = hdmirx_rd_phy(PHY_MAINFSM_STATUS1); - wr_reg_hhi(HHI_AUD_PLL_CNTL, 0x20000000); - /* audio pll div depends on input freq */ - wr_reg_hhi(HHI_AUD_PLL_CNTL6, (tmp >> 9 & 3) << 28); - /* audio pll div fixed to N/CTS as below*/ - /* wr_reg_hhi(HHI_AUD_PLL_CNTL6, 0x40000000); */ - wr_reg_hhi(HHI_AUD_PLL_CNTL5, 0x0000002e); - wr_reg_hhi(HHI_AUD_PLL_CNTL4, 0x30000000); - wr_reg_hhi(HHI_AUD_PLL_CNTL3, 0x00000000); - wr_reg_hhi(HHI_AUD_PLL_CNTL, 0x40000000); - wr_reg_hhi(HHI_ADC_PLL_CNTL4, 0x805); - rx_audio_pll_sw_update(); - /*External_Mute(0);*/ - } else{ - /* disable pll, into reset mode */ -#ifdef CONFIG_AMLOGIC_AMAUDIO2 - External_Mute(1); -#endif - wr_reg_hhi(HHI_AUD_PLL_CNTL, 0x20000000); + if (rx.hdmirxdev->data->chip_id == CHIP_ID_TL1) { + if (en) { + /* AUD_CLK=N/CTS*TMDS_CLK */ + /* bandgap enable */ + tmp = rd_reg_hhi(HHI_VDAC_CNTL1); + wr_reg_hhi(HHI_VDAC_CNTL1, tmp|0x80); + wr_reg_hhi(HHI_AUD_PLL_CNTL, 0x40000540); + wr_reg_hhi(HHI_AUD_PLL_CNTL2, 0x00000000); + /* cntl3 2:0 000=1*cts 001=2*cts 010=4*cts 011=8*cts */ + wr_reg_hhi(HHI_AUD_PLL_CNTL3, rx.physts.aud_div); + rx_pr("aud div=%d\n", rd_reg_hhi(HHI_AUD_PLL_CNTL3)); + wr_reg_hhi(HHI_AUD_PLL_CNTL, 0x60000540); + rx_pr("audio pll lock:0x%x\n", + rd_reg_hhi(HHI_AUD_PLL_CNTL_I)); + } else { + /* disable pll, into reset mode */ + External_Mute(1); + wr_reg_hhi(HHI_AUD_PLL_CNTL, 0x0); + } + } else { + if (en) { + tmp = hdmirx_rd_phy(PHY_MAINFSM_STATUS1); + wr_reg_hhi(HHI_AUD_PLL_CNTL, 0x20000000); + /* audio pll div depends on input freq */ + wr_reg_hhi(HHI_AUD_PLL_CNTL6, (tmp >> 9 & 3) << 28); + /* audio pll div fixed to N/CTS as below*/ + /* wr_reg_hhi(HHI_AUD_PLL_CNTL6, 0x40000000); */ + wr_reg_hhi(HHI_AUD_PLL_CNTL5, 0x0000002e); + wr_reg_hhi(HHI_AUD_PLL_CNTL4, 0x30000000); + wr_reg_hhi(HHI_AUD_PLL_CNTL3, 0x00000000); + wr_reg_hhi(HHI_AUD_PLL_CNTL, 0x40000000); + wr_reg_hhi(HHI_ADC_PLL_CNTL4, 0x805); + rx_audio_pll_sw_update(); + /*External_Mute(0);*/ + } else{ + /* disable pll, into reset mode */ + External_Mute(1); + wr_reg_hhi(HHI_AUD_PLL_CNTL, 0x20000000); + } } } @@ -2165,7 +2451,7 @@ void rx_get_video_info(void) break; } /* pixel clock */ - rx.cur.pixel_clk = hdmirx_get_pixel_clock() / divider; + rx.cur.pixel_clk = rx_measure_clock(MEASURE_CLK_PIXEL) / divider; /* image parameters */ rx.cur.interlaced = hdmirx_rd_bits_dwc(DWC_MD_STS, ILACE) != 0; rx.cur.voffset = hdmirx_rd_bits_dwc(DWC_MD_VOL, VOFS_LIN); @@ -2229,10 +2515,43 @@ void hdmirx_config_audio(void) } } +/* + * rx_get_clock: git clock from hdmi top + * tl1: have hdmi, cable clock + * other: have hdmi clock + */ +unsigned int rx_get_clock(unsigned int clk_src) +{ + uint32_t clock = 0; + uint32_t tmp_data = 0; + uint32_t meas_cycles = 0; + + if (clk_src == K_MEASURE_SRC_HDMI_TMDSCLK) + tmp_data = hdmirx_rd_top(TOP_METER_HDMI_STAT); + else if (clk_src == K_MEASURE_SRC_HDMI_CABLECLK) { + if (rx.hdmirxdev->data->chip_id == CHIP_ID_TL1) + tmp_data = hdmirx_rd_top(TOP_METER_CABLE_STAT); + } else + tmp_data = 0; + + /* measure stable */ + if (tmp_data & 0x80000000) { + meas_cycles = tmp_data & 0xffffff; + clock = (2930 * meas_cycles); + /*clock = (24000000 * meas_cycles) / 8192;*/ + /*rx_pr("hdmi_clk cycle cnt=%d,frq=%d\n",cycle_cnt,clock);*/ + } + + hdmirx_wr_top(TOP_SW_RESET, 0x6); + hdmirx_wr_top(TOP_SW_RESET, 0x0); + return clock; +} + +#if 0 /* * clk_util_clk_msr */ -static unsigned int clk_util_clk_msr(unsigned int clk_mux) +unsigned int clk_util_clk_msr(unsigned int clk_mux) { return meson_clk_measure(clk_mux); } @@ -2246,6 +2565,7 @@ unsigned int hdmirx_get_clock(int index) return clk_util_clk_msr(index); } + /* * hdmirx_get_tmds_clock - get tmds clock */ @@ -2293,6 +2613,74 @@ unsigned int hdmirx_get_esm_clock(void) { return clk_util_clk_msr(68); } +#endif +/* + * function - get clk related with hdmirx + */ +unsigned int rx_measure_clock(enum measure_clk_src clksrc) +{ + unsigned int clock = 0; + + /* from clock measure: txlx_clk_measure + * cable [x] need read from hdmitop + * tmds clock [25] Hdmirx_tmds_clk + * pixel clock [29] Hdmirx_pix_clk + * audio clock [24] Hdmirx_aud_pll_clk + * cts audio [98] cts_hdmirx_aud_pll_clk + * mpll clock [27] Hdmirx_mpll_div_clk + * esm clock [68] Cts_hdcp22_esm + */ + + /* from clock measure: tl1_table + * cable clock [30] hdmirx_cable_clk + * tmds clock [63] hdmirx_tmds_clk + * pixel clock [29] hdmirx_apll_clk_out_div + * audio clock [74] hdmirx_aud_pll_clk + * cts audio [60] cts_hdmirx_aud_pll_clk + * mpll clock [67] hdmirx_apll_clk_audio + * esm clock [68] Cts_hdcp22_esm + */ + + if (clksrc == MEASURE_CLK_CABLE) { + if (rx.hdmirxdev->data->chip_id == CHIP_ID_TL1) { + clock = meson_clk_measure(30); + /*clock = rx_get_clock(K_MEASURE_SRC_HDMI_CABLECLK);*/ + } + } else if (clksrc == MEASURE_CLK_TMDS) { + if (rx.hdmirxdev->data->chip_id == CHIP_ID_TL1) + clock = meson_clk_measure(63); + else { + clock = meson_clk_measure(25); + if (clock == 0) { + clock = + hdmirx_rd_dwc(DWC_HDMI_CKM_RESULT) & 0xffff; + clock = clock * 158000 / 4095 * 1000; + } + } + } else if (clksrc == MEASURE_CLK_PIXEL) { + clock = meson_clk_measure(29); + } else if (clksrc == MEASURE_CLK_AUD_PLL) { + if (rx.hdmirxdev->data->chip_id == CHIP_ID_TL1) + clock = meson_clk_measure(74); + else + clock = meson_clk_measure(24); + } else if (clksrc == MEASURE_CLK_AUD_DIV) { + if (rx.hdmirxdev->data->chip_id == CHIP_ID_TL1) + clock = meson_clk_measure(60); + else + clock = meson_clk_measure(98); + + } else if (clksrc == MEASURE_CLK_MPLL) { + if (rx.hdmirxdev->data->chip_id == CHIP_ID_TL1) + clock = meson_clk_measure(67);/*apll_clk_audio*/ + else + clock = meson_clk_measure(27); + } else if (clksrc == MEASURE_CLK_ESM) { + clock = meson_clk_measure(68); + } + + return clock; +} static const unsigned int wr_only_register[] = { 0x0c, 0x3c, 0x60, 0x64, 0x68, 0x6c, 0x70, 0x74, 0x78, 0x7c, 0x8c, 0xa0, @@ -2329,7 +2717,7 @@ void rx_debug_load22key(void) int ret = 0; int wait_kill_done_cnt = 0; - ret = rx_sec_set_duk(); + ret = rx_sec_set_duk(hdmirx_repeat_support()); rx_pr("22 = %d\n", ret); if (ret == 1) { rx_pr("load 2.2 key\n"); @@ -2461,6 +2849,7 @@ void dump_edid_reg(void) rx_pr("0x4 1.4 edid with 420 video data\n"); rx_pr("0x5 2.0 edid with HDR,DV,420\n"); rx_pr("********************************\n"); + for (i = 0; i < 16; i++) { rx_pr("[%2d] ", i); for (j = 0; j < 16; j++) { @@ -2547,27 +2936,609 @@ int rx_debug_rd_reg(const char *buf, char *tmpbuf) int rx_get_aud_pll_err_sts(void) { int ret = E_AUDPLL_OK; - int32_t req_clk = hdmirx_get_mpll_div_clk(); - int32_t aud_clk = hdmirx_get_audio_clock(); + int32_t req_clk = rx_measure_clock(MEASURE_CLK_MPLL); + int32_t aud_clk = rx_measure_clock(MEASURE_CLK_AUD_PLL); uint32_t phy_pll_rate = (hdmirx_rd_phy(PHY_MAINFSM_STATUS1)>>9)&0x3; uint32_t aud_pll_cntl = (rd_reg_hhi(HHI_AUD_PLL_CNTL6)>>28)&0x3; - if (req_clk > PHY_REQUEST_CLK_MAX || - req_clk < PHY_REQUEST_CLK_MIN) { - ret = E_REQUESTCLK_ERR; - if (log_level & AUDIO_LOG) - rx_pr("request clk err:%d\n", req_clk); - } else if (phy_pll_rate != aud_pll_cntl) { - ret = E_PLLRATE_CHG; - if (log_level & AUDIO_LOG) - rx_pr("pll rate chg,phy=%d,pll=%d\n", - phy_pll_rate, aud_pll_cntl); - } else if (aud_clk == 0) { - ret = E_AUDCLK_ERR; - if (log_level & AUDIO_LOG) - rx_pr("aud_clk=0\n"); + if (rx.hdmirxdev->data->chip_id == CHIP_ID_TL1) { + /* need to do something ...*/ + } else { + if (req_clk > PHY_REQUEST_CLK_MAX || + req_clk < PHY_REQUEST_CLK_MIN) { + ret = E_REQUESTCLK_ERR; + if (log_level & AUDIO_LOG) + rx_pr("request clk err:%d\n", req_clk); + } else if (phy_pll_rate != aud_pll_cntl) { + ret = E_PLLRATE_CHG; + if (log_level & AUDIO_LOG) + rx_pr("pll rate chg,phy=%d,pll=%d\n", + phy_pll_rate, aud_pll_cntl); + } else if (aud_clk == 0) { + ret = E_AUDCLK_ERR; + if (log_level & AUDIO_LOG) + rx_pr("aud_clk=0\n"); + } } - return ret; } +/* + * for tl1 phy function + */ +struct apll_param apll_tab[] = { + /* bw M, N, od, div, od2, od2_div */ + {apll_bw_24_40, 160, 1, 0x5, 32, 0x4, 16}, + {apll_bw_40_80, 80, 1, 0x4, 16, 0x3, 8}, + {apll_bw_80_150, 40, 1, 0x3, 8, 0x2, 4}, + {apll_bw_150_300, 0, 2, 0x2, 4, 0x1, 2}, + {apll_bw_300_600, 40, 1, 0x1, 2, 0x0, 1}, + {apll_bw_null, 40, 1, 0x3, 8, 0x2, 4}, +}; + +unsigned int aml_check_clk_bandwidth(unsigned int cableclk, + unsigned int clkrate) +{ + unsigned int bw; + unsigned int cab_clk = cableclk; + + /* 1:40 */ + if (clkrate) + cab_clk = cableclk << 2; + + /* 1:10 */ + if (cab_clk < 40000000) + bw = apll_bw_24_40; + else if (cab_clk < 80000000) + bw = apll_bw_40_80; + else if (cab_clk < 150000000) + bw = apll_bw_80_150; + else if (cab_clk < 300000000) + bw = apll_bw_150_300; + else if (cab_clk < 600000000) + bw = apll_bw_300_600; + else { + bw = apll_bw_80_150; + rx_pr("phy err: bw clk=%d\n", cableclk); + } + return bw; +} + +void aml_phy_init(unsigned int bw) +{ + unsigned int data32; + static unsigned int cnt; + + rx_pr("init phy port %d, bw:%d\n", rx.port, bw); + if (bw == apll_bw_null) { + return; + } else if (bw <= apll_bw_24_40) { + /* set port number and enable terminal connect */ + data32 = 0x30034078; + data32 |= (1 << rx.port); + wr_reg_hhi(HHI_HDMIRX_PHY_MISC_CNTL0, data32); + /* channel reset */ + data32 = 0x300347f8; + data32 |= (1 << rx.port); + wr_reg_hhi(HHI_HDMIRX_PHY_MISC_CNTL0, data32); + rx_pr("MISC_CNTL0=0x%x\n", data32); + wr_reg_hhi(HHI_HDMIRX_PHY_MISC_CNTL1, 0x00000080); + wr_reg_hhi(HHI_HDMIRX_PHY_MISC_CNTL2, 0x02200000); + /* reset and select data port */ + data32 = 0x00000010; + data32 |= ((1 << rx.port) << 6); + wr_reg_hhi(HHI_HDMIRX_PHY_MISC_CNTL3, data32); + /* release reset */ + data32 |= (1 << 11); + wr_reg_hhi(HHI_HDMIRX_PHY_MISC_CNTL3, data32); + rx_pr("MISC_CNTL3=0x%x\n", data32); + udelay(5); + wr_reg_hhi(HHI_HDMIRX_PHY_DCHA_CNTL0, 0x00000182); + wr_reg_hhi(HHI_HDMIRX_PHY_DCHA_CNTL1, 0x2800c202); + wr_reg_hhi(HHI_HDMIRX_PHY_DCHA_CNTL2, 0x010088a2); + wr_reg_hhi(HHI_HDMIRX_PHY_DCHD_CNTL0, 0x002c733a); + wr_reg_hhi(HHI_HDMIRX_PHY_DCHD_CNTL2, 0x00018000); + wr_reg_hhi(HHI_HDMIRX_PHY_DCHD_CNTL1, 0x1e013130); + } else if (bw <= apll_bw_40_80) { + /* set port number and enable terminal connect */ + data32 = 0x30034078; + data32 |= (1 << rx.port); + wr_reg_hhi(HHI_HDMIRX_PHY_MISC_CNTL0, data32); + /* channel reset */ + data32 = 0x300347f8; + data32 |= (1 << rx.port); + wr_reg_hhi(HHI_HDMIRX_PHY_MISC_CNTL0, data32); + rx_pr("MISC_CNTL0=0x%x\n", data32); + wr_reg_hhi(HHI_HDMIRX_PHY_MISC_CNTL1, 0x00000080); + wr_reg_hhi(HHI_HDMIRX_PHY_MISC_CNTL2, 0x02200000); + /* reset and select data port */ + data32 = 0x00000010; + data32 |= ((1 << rx.port) << 6); + wr_reg_hhi(HHI_HDMIRX_PHY_MISC_CNTL3, data32); + /* release reset */ + data32 |= (1 << 11); + wr_reg_hhi(HHI_HDMIRX_PHY_MISC_CNTL3, data32); + rx_pr("MISC_CNTL3=0x%x\n", data32); + udelay(5); + wr_reg_hhi(HHI_HDMIRX_PHY_DCHA_CNTL0, 0x00000182); + wr_reg_hhi(HHI_HDMIRX_PHY_DCHA_CNTL1, 0x4800c202); + wr_reg_hhi(HHI_HDMIRX_PHY_DCHA_CNTL2, 0x01009126); + wr_reg_hhi(HHI_HDMIRX_PHY_DCHD_CNTL0, 0x002c733a); + if (cnt & 0x1) { + wr_reg_hhi(HHI_HDMIRX_PHY_DCHD_CNTL2, 0x00018000); + wr_reg_hhi(HHI_HDMIRX_PHY_DCHD_CNTL1, 0x1e020200); + wr_reg_hhi(HHI_HDMIRX_PHY_DCHD_CNTL1, 0x1e420200); + } else { + wr_reg_hhi(HHI_HDMIRX_PHY_DCHD_CNTL2, 0x00028000); + wr_reg_hhi(HHI_HDMIRX_PHY_DCHD_CNTL1, 0x1e060600); + wr_reg_hhi(HHI_HDMIRX_PHY_DCHD_CNTL1, 0x1e460600); + } + } else if (bw <= apll_bw_80_150) { + //phy default setting + /* set port number and enable terminal connect */ + data32 = 0x30034078 | (1 << rx.port); + wr_reg_hhi(HHI_HDMIRX_PHY_MISC_CNTL0, data32); + /* channel reset */ + data32 = 0x300347f8 | (1 << rx.port); + wr_reg_hhi(HHI_HDMIRX_PHY_MISC_CNTL0, data32); + rx_pr("MISC_CNTL0=0x%x\n", data32); + wr_reg_hhi(HHI_HDMIRX_PHY_MISC_CNTL1, 0x00000080); + wr_reg_hhi(HHI_HDMIRX_PHY_MISC_CNTL2, 0x02200000); + /* reset and select data port */ + data32 = 0x00000010; + data32 |= ((1 << rx.port) << 6); + wr_reg_hhi(HHI_HDMIRX_PHY_MISC_CNTL3, data32); + /* release reset */ + data32 |= (1 << 11); + wr_reg_hhi(HHI_HDMIRX_PHY_MISC_CNTL3, data32); + udelay(5); + wr_reg_hhi(HHI_HDMIRX_PHY_DCHA_CNTL0, 0x00000222); + wr_reg_hhi(HHI_HDMIRX_PHY_DCHA_CNTL1, 0x4800c202); + wr_reg_hhi(HHI_HDMIRX_PHY_DCHA_CNTL2, 0x01009126); + wr_reg_hhi(HHI_HDMIRX_PHY_DCHD_CNTL0, 0x002c733a); + wr_reg_hhi(HHI_HDMIRX_PHY_DCHD_CNTL2, 0x00018000); + if (cnt & 0x1) { + wr_reg_hhi(HHI_HDMIRX_PHY_DCHD_CNTL2, 0x00018000); + wr_reg_hhi(HHI_HDMIRX_PHY_DCHD_CNTL1, 0x1e020200); + wr_reg_hhi(HHI_HDMIRX_PHY_DCHD_CNTL1, 0x1e420200); + } else { + wr_reg_hhi(HHI_HDMIRX_PHY_DCHD_CNTL2, 0x00028000); + wr_reg_hhi(HHI_HDMIRX_PHY_DCHD_CNTL1, 0x1e060600); + wr_reg_hhi(HHI_HDMIRX_PHY_DCHD_CNTL1, 0x1e460600); + } + } else if (bw <= apll_bw_150_300) { + /* 3G */ + /* set port number and enable terminal connect */ + data32 = 0x30034078 | (1 << rx.port); + wr_reg_hhi(HHI_HDMIRX_PHY_MISC_CNTL0, data32); + /* channel reset */ + data32 = 0x300347f8 | (1 << rx.port); + wr_reg_hhi(HHI_HDMIRX_PHY_MISC_CNTL0, data32); + rx_pr("MISC_CNTL0=0x%x\n", data32); + wr_reg_hhi(HHI_HDMIRX_PHY_MISC_CNTL1, 0x00000080); + wr_reg_hhi(HHI_HDMIRX_PHY_MISC_CNTL2, 0x02200000); + /* reset and select data port */ + data32 = 0x00000010; + data32 |= ((1 << rx.port) << 6); + wr_reg_hhi(HHI_HDMIRX_PHY_MISC_CNTL3, data32); + /* release reset */ + data32 |= (1 << 11); + wr_reg_hhi(HHI_HDMIRX_PHY_MISC_CNTL3, data32); + udelay(5); + wr_reg_hhi(HHI_HDMIRX_PHY_DCHA_CNTL0, 0x00000242); + wr_reg_hhi(HHI_HDMIRX_PHY_DCHA_CNTL1, 0x0800c202); + wr_reg_hhi(HHI_HDMIRX_PHY_DCHA_CNTL2, 0x0100fc31); + wr_reg_hhi(HHI_HDMIRX_PHY_DCHD_CNTL0, 0x002c733a); + + wr_reg_hhi(HHI_HDMIRX_PHY_DCHD_CNTL2, 0x000a0000); + udelay(5); + wr_reg_hhi(HHI_HDMIRX_PHY_DCHD_CNTL1, 0x1e040410); + udelay(5); + wr_reg_hhi(HHI_HDMIRX_PHY_DCHD_CNTL1, 0x1e440410); + udelay(1); + wr_reg_hhi(HHI_HDMIRX_PHY_DCHD_CNTL2, 0x00120000); + udelay(1); + wr_reg_hhi(HHI_HDMIRX_PHY_DCHD_CNTL2, 0x00020000); + } else { + /*6G*/ + } + cnt++; +} + +void aml_eq_setting(unsigned int bw) +{ + unsigned int data32; + + if (bw == apll_bw_null) { + return; + } else if (bw <= apll_bw_24_40) { + wr_reg_hhi(HHI_HDMIRX_PHY_DCHA_CNTL0, 0x00000182); + wr_reg_hhi(HHI_HDMIRX_PHY_DCHA_CNTL1, 0x2800c202); + wr_reg_hhi(HHI_HDMIRX_PHY_DCHA_CNTL2, 0x010088a2); + wr_reg_hhi(HHI_HDMIRX_PHY_DCHD_CNTL0, 0x002c733a); + wr_reg_hhi(HHI_HDMIRX_PHY_DCHD_CNTL2, 0x00018000); + wr_reg_hhi(HHI_HDMIRX_PHY_DCHD_CNTL1, 0x1e013130); + } else if (bw <= apll_bw_80_150) { + data32 = rd_reg_hhi(HHI_HDMIRX_PHY_DCHD_CNTL2); + wr_reg_hhi(HHI_HDMIRX_PHY_DCHD_CNTL2, data32); + /*reset*/ + data32 = rd_reg_hhi(HHI_HDMIRX_PHY_DCHD_CNTL1); + data32 &= (~(1 << 24)); + wr_reg_hhi(HHI_HDMIRX_PHY_DCHD_CNTL1, data32); + /*eq reset*/ + data32 |= (1 << 24); + wr_reg_hhi(HHI_HDMIRX_PHY_DCHD_CNTL1, data32); + } else { + /* 3G , 6G */ + wr_reg_hhi(HHI_HDMIRX_PHY_DCHD_CNTL2, 0x000a0000); + udelay(5); + wr_reg_hhi(HHI_HDMIRX_PHY_DCHD_CNTL1, 0x1e040410); + udelay(5); + /*eq reset*/ + wr_reg_hhi(HHI_HDMIRX_PHY_DCHD_CNTL1, 0x1e440410); + udelay(5); + wr_reg_hhi(HHI_HDMIRX_PHY_DCHD_CNTL2, 0x00120000); + udelay(5); + wr_reg_hhi(HHI_HDMIRX_PHY_DCHD_CNTL2, 0x00020000); + } +} + +void aml_phy_pll_setting(unsigned int bandwidth, unsigned int cableclk) +{ + unsigned int M, N; + unsigned int od, od_div; + unsigned int od2, od2_div; + unsigned int bw = bandwidth; + unsigned int vco_clk; + unsigned int apll_out; + unsigned int aud_pll_out; + unsigned int data, data2; + unsigned int aud_div; + + rx_pr("bw:%d, clkrate:%d\n", bandwidth, cableclk); + od_div = apll_tab[bw].od_div; + od = apll_tab[bw].od; + M = apll_tab[bw].M; + N = apll_tab[bw].N; + od2_div = apll_tab[bw].od2_div; + od2 = apll_tab[bw].od2; + + vco_clk = (cableclk * M) / N; + if ((vco_clk < 2970000) || (vco_clk > 6000000)) + rx_pr("err: M=%d,N=%d,vco_clk=%d\n", M, N, vco_clk); + + apll_out = (((cableclk * M)/N)/od_div)/5; + rx_pr("M=%d,N=%d,od=%d,od_div=%d\n", M, N, od, od_div); + rx_pr("apll_out=%d, vco_clk=%d\n", apll_out, vco_clk); + rx_pr("od2=%d, od2_div=%d\n", od2, od2_div); + + aud_pll_out = ((vco_clk/od2_div)/5); + rx_pr("aud pll out=%d\n", aud_pll_out); + + /*cntl0 M <7:0> N<14:10>*/ + data = 0x00090400 & 0xffff8300; + data |= M; + data |= (N << 10); + wr_reg_hhi(HHI_HDMIRX_APLL_CNTL0, data|0x20000000); + udelay(2); + wr_reg_hhi(HHI_HDMIRX_APLL_CNTL0, data|0x30000000); + rx_pr("APLL_CNTL0 4c:0x%x\n", rd_reg_hhi(HHI_HDMIRX_APLL_CNTL0)); + wr_reg_hhi(HHI_HDMIRX_APLL_CNTL1, 0x00000000); + wr_reg_hhi(HHI_HDMIRX_APLL_CNTL2, 0x00001108); + data2 = 0x10058f30|od2; + wr_reg_hhi(HHI_HDMIRX_APLL_CNTL3, data2); + + data2 = 0x000100c0 /*& 0xf8ffffff*/; + data2 |= (od << 24); + wr_reg_hhi(HHI_HDMIRX_APLL_CNTL4, data2); + udelay(2); + /*apll_vctrl_mon_en*/ + wr_reg_hhi(HHI_HDMIRX_APLL_CNTL4, data2|0x00800000); + rx_pr("APLL_CNTL4 50:0x%x\n", rd_reg_hhi(HHI_HDMIRX_APLL_CNTL4)); + + wr_reg_hhi(HHI_HDMIRX_APLL_CNTL0, data|0x34000000); + udelay(2); + wr_reg_hhi(HHI_HDMIRX_APLL_CNTL0, data|0x14000000); + rx_pr("APLL_CNTL0 4c:0x%x\n", rd_reg_hhi(HHI_HDMIRX_APLL_CNTL0)); + wr_reg_hhi(HHI_HDMIRX_APLL_CNTL2, 0x00003008); + + + /*wr_reg_hhi(HHI_HDMIRX_PHY_DCHD_CNTL2, 0x00018000);*/ + /*wr_reg_hhi(HHI_HDMIRX_PHY_DCHD_CNTL1, 0x1e040400);*/ + /*udelay(2);*/ + /*wr_reg_hhi(HHI_HDMIRX_PHY_DCHD_CNTL1, 0x1e440400);*/ + + /* common block release reset */ + data = rd_reg_hhi(HHI_HDMIRX_PHY_MISC_CNTL0); + data &= ~(0x7 << 7); + wr_reg_hhi(HHI_HDMIRX_PHY_MISC_CNTL0, data); + udelay(2); + /* data channel release reset */ + data |= (0x7 << 7); + wr_reg_hhi(HHI_HDMIRX_PHY_MISC_CNTL0, data); + + /*set audio pll divider*/ + aud_div = aud_pll_out/apll_out; + rx_pr("aud div=%d\n", aud_div); + if (aud_div == 1) + data = 0; + else if (aud_div == 2) + data = 1; + else if (aud_div == 4) + data = 2; + else if (aud_div == 8) + data = 3; + else if (aud_div == 16) + data = 4; + rx.physts.aud_div = data; +} + +void aml_phy_pw_onoff(unsigned int onoff) +{ + unsigned int data = rd_reg_hhi(HHI_HDMIRX_APLL_CNTL0); + + if (onoff) { + /* apll power down */ + data &= ~(1 << 26); + data &= ~(1 << 28); + data |= (1 << 29); + wr_reg_hhi(HHI_HDMIRX_APLL_CNTL0, data); + + /*phy */ + data = rd_reg_hhi(HHI_HDMIRX_PHY_MISC_CNTL0); + data &= ~(1 << 7); + data &= ~(1 << 8); + data &= ~(1 << 9); + wr_reg_hhi(HHI_HDMIRX_PHY_MISC_CNTL0, data); + } else { + aml_phy_init(apll_bw_80_150); + /*tl1_apll_setting(apll_bw_80_150);*/ + } +} + +/* + * aml phy initial + */ +void aml_phy_bw_switch(unsigned int cableclk, unsigned int clkrate) +{ + unsigned int bw = aml_check_clk_bandwidth(cableclk, clkrate); + + aml_phy_init(bw); + udelay(1); + aml_phy_pll_setting(bw, cableclk); + udelay(1); + aml_eq_setting(bw); +} + +unsigned int aml_phy_pll_lock(void) +{ + if (rd_reg_hhi(HHI_HDMIRX_APLL_CNTL0) & 0x80000000) + return true; + else + return false; +} + +unsigned int aml_phy_tmds_valid(void) +{ + unsigned int tmvds_valid; + unsigned int sqofclk; + unsigned int pll_lock; + unsigned int tmds_align; + + tmvds_valid = hdmirx_rd_dwc(DWC_HDMI_PLL_LCK_STS) & 0x01; + sqofclk = rd_reg_hhi(HHI_HDMIRX_PHY_MISC_STAT) & 0x80000000; + pll_lock = rd_reg_hhi(HHI_HDMIRX_APLL_CNTL0) & 0x80000000; + tmds_align = hdmirx_rd_top(TOP_TMDS_ALIGN_STAT) & 0x3f000000; + if (tmvds_valid && sqofclk && pll_lock && + (tmds_align == 0x3f000000)) + return true; + else + return false; +} + +void rx_phy_rxsense_pulse(unsigned int t1, unsigned int t2) +{ + /* for tl1 no SW eq */ + if (rx.hdmirxdev->data->chip_id == CHIP_ID_TL1) { + /* ... */ + } else { + /* set rxsense pulse */ + hdmirx_phy_pddq(1); + mdelay(t1); + hdmirx_phy_pddq(0); + mdelay(t2); + } +} + +void rx_phy_power_on(unsigned int onoff) +{ + if (rx.hdmirxdev->data->chip_id == CHIP_ID_TL1) { + /* ... */ + + } else { + if (onoff) + hdmirx_phy_pddq(0); + else + hdmirx_phy_pddq(1); + } +} + +void rx_emp_to_ddr_init(void) +{ + unsigned int data; + + if (rx.hdmirxdev->data->chip_id != CHIP_ID_TL1) + return; + + if (rx.empbuff.pg_addr) { + rx_pr("rx_emp_to_ddr_init\n"); + /* emp int enable */ + /* config ddr buffer */ + hdmirx_wr_top(TOP_EMP_DDR_START_A, + rx.empbuff.p_addr_a); + hdmirx_wr_top(TOP_EMP_DDR_START_B, + rx.empbuff.p_addr_b); + + /* enable store EMP pkt type */ + hdmirx_wr_top(TOP_EMP_DDR_FILTER, _BIT(15)); + /* max pkt count */ + hdmirx_wr_top(TOP_EMP_CNTMAX, EMP_BUFF_MAC_PKT_CNT); + + data = 0; + data |= 0xf << 16;/*[23:16] hs_beat_rate=0xf */ + /*[14] buffer_info_mode=0 */ + data |= 0x1 << 13;/*[13] reset_on_de=1 */ + data |= 0x1 << 12;/*[12] burst_end_on_last_emp=1 */ + /*[11:2] de_rise_delay=0 */ + /*[1:0] Endian = 0 */ + hdmirx_wr_top(TOP_EMP_CNTL_0, data); + + data = 0; + data |= 0 << 1;/*ddr_mode[1] 0: emp 1: tmds*/ + hdmirx_wr_top(TOP_EMP_CNTL_1, data); + + data |= 1; /*ddr_en[0] 1:enable*/ + hdmirx_wr_top(TOP_EMP_CNTL_1, data); + + /* emp int enable TOP_INTR_MASKN*/ + /* emp field end done at DE rist bit[25]*/ + /* emp last EMP pkt recv done bit[26]*/ + top_intr_maskn_value |= _BIT(25); + /*hdmirx_wr_top(TOP_INTR_MASKN, top_intr_maskn_value);*/ + } + + rx.empbuff.ready = 0; + rx.empbuff.irqcnt = 0; +} + +void rx_emp_field_done_irq(void) +{ + phys_addr_t p_addr; + unsigned int recv_pkt_cnt, emp_pkt_cnt; + unsigned char *src_addr; + unsigned char *dts_addr; + unsigned int i, j; + unsigned int datacnt = 0; + + /*emp data start p address*/ + p_addr = hdmirx_rd_top(TOP_EMP_DDR_PTR_S_BUF); + /*buffer number*/ + recv_pkt_cnt = hdmirx_rd_top(TOP_EMP_RCV_CNT_BUF); + /* p addr to v addr for cpu access */ + src_addr = phys_to_virt(p_addr); + + if (rx.empbuff.irqcnt & 0x1) + dts_addr = rx.empbuff.storeB; + else + dts_addr = rx.empbuff.storeA; + emp_pkt_cnt = 0; + if (recv_pkt_cnt < EMP_BUFF_MAC_PKT_CNT) { + for (i = 0; i < recv_pkt_cnt; i++) { + /*check PKT_TYPE_EMP = 0x7f*/ + if (src_addr[i] == 0x7f) { + emp_pkt_cnt++; + /*32 bytes per emp pkt*/ + for (j = 0; j < 32; j++) { + dts_addr[datacnt] = src_addr[i]; + datacnt++; + } + } + + } + } else { + rx_pr("pkt cnt err:%d\n", recv_pkt_cnt); + } + /*ready address*/ + rx.empbuff.ready = dts_addr; + /*ready pkt cnt*/ + rx.empbuff.emppktcnt = emp_pkt_cnt; + /*emp field dont irq counter*/ + rx.empbuff.irqcnt++; +} + +void rx_emp_status(void) +{ + unsigned int i, j; + unsigned char *pdata; + + rx_pr("p_addr_a=0x%x\n", rx.empbuff.p_addr_a); + rx_pr("p_addr_b=0x%x\n", rx.empbuff.p_addr_b); + rx_pr("irq cnt =0x%x\n", rx.empbuff.irqcnt); + rx_pr("p_addr_b=0x%p\n", rx.empbuff.ready); + rx_pr("recv pkt cnt=0x%x\n", rx.empbuff.emppktcnt); + + pdata = rx.empbuff.ready; + for (i = 0; i < rx.empbuff.emppktcnt; i++) { + for (j = 0; j < 32; j++) + rx_pr("0x%02lx, ", pdata[i*32 + j]); + rx_pr("\n"); + } +} + + +void rx_tmds_to_ddr_init(void) +{ + unsigned int data, data2; + unsigned int i = 0; + + if (rx.hdmirxdev->data->chip_id != CHIP_ID_TL1) + return; + + if (rx.empbuff.pg_addr) { + rx_pr("rx_emp_to_ddr_init\n"); + /* disable emp rev */ + data = hdmirx_rd_top(TOP_EMP_CNTL_1); + data &= ~0x1; + hdmirx_wr_top(TOP_EMP_CNTL_1, data); + /* wait until emp finish */ + data2 = hdmirx_rd_top(TOP_EMP_STAT_0) & 0x7fffffff; + data = hdmirx_rd_top(TOP_EMP_STAT_1); + while (data2 || data) { + mdelay(1); + data2 = hdmirx_rd_top(TOP_EMP_STAT_0) & 0x7fffffff; + data = hdmirx_rd_top(TOP_EMP_STAT_1); + if (i++ > 100) { + rx_pr("warning: wait emp finish\n"); + break; + } + } + + /* config ddr buffer */ + hdmirx_wr_top(TOP_EMP_DDR_START_A, + rx.empbuff.p_addr_a); + + /* max pkt count */ + /* one frame size: HxVx3x1.25 bytes */ + data = ((rx.empbuff.emppktcnt/8) * 8) - 1; + hdmirx_wr_top(TOP_EMP_CNTMAX, data); + rx_pr("cnt max=0x%x\n", data); + + data = 0; + data |= 0xf << 16;/*[23:16] hs_beat_rate=0xf */ + /*[14] buffer_info_mode=0 */ + data |= 0x1 << 13;/*[13] reset_on_de=1 */ + data |= 0x0 << 12;/*[12] burst_end_on_last_emp=1 */ + data |= 0x0 << 2;/*[11:2] de_rise_delay=0 */ + data |= 0x0 << 0;/*[1:0] Endian = 0 */ + hdmirx_wr_top(TOP_EMP_CNTL_0, data); + + data = 0; + data |= 1 << 1;/*ddr_mode[1] 0: emp 1: tmds*/ + hdmirx_wr_top(TOP_EMP_CNTL_1, data); + + data |= 1; /*ddr_en[0] 1:enable*/ + hdmirx_wr_top(TOP_EMP_CNTL_1, data); + + /* emp int enable TOP_INTR_MASKN*/ + /* emp field end done at DE rist bit[25]*/ + /* emp last EMP pkt recv done bit[26]*/ + top_intr_maskn_value |= _BIT(26); + hdmirx_wr_top(TOP_INTR_MASKN, top_intr_maskn_value); + } +} + +void rx_emp_lastpkt_done_irq(void) +{ + /* need to do ...*/ +} + diff --git a/drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_hw.h b/drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_hw.h index b906ad296e0c..8c64f4ed22ee 100644 --- a/drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_hw.h +++ b/drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_hw.h @@ -19,6 +19,8 @@ #define __HDMI_RX_HW_H__ +/*#define K_BRINGUP_PTM*/ + /** * Bit field mask * @param m width @@ -31,10 +33,12 @@ */ #define _BIT(n) MSK(1, (n)) +#define diff(a, b) ((a > b) ? (a - b) : (b - a)) #define HHI_GCLK_MPEG0 (0x50 << 2) /* (0xC883C000 + 0x140) */ #define HHI_HDMIRX_CLK_CNTL 0x200 /* (0xC883C000 + 0x200) */ #define HHI_HDMIRX_AUD_CLK_CNTL 0x204 /* 0x1081 */ +#define HHI_VDAC_CNTL1 (0xbc * 4) #define HHI_AUD_PLL_CNTL (0xf8 * 4) #define HHI_AUD_PLL_CNTL2 (0xf9 * 4) #define HHI_AUD_PLL_CNTL3 (0xfa * 4) @@ -196,6 +200,13 @@ #define TOP_EDID_GEN_STAT_B 0x025 #define TOP_EDID_GEN_STAT_C 0x026 #define TOP_EDID_GEN_STAT_D 0x027 +/* tl1 */ +#define TOP_CHAN_SWITCH_0 0x028 +#define TOP_TMDS_ALIGN_CNTL0 0x029 +#define TOP_TMDS_ALIGN_CNTL1 0x02a +#define TOP_TMDS_ALIGN_STAT 0x02b + +/* GXTVBB/TXL/TXLX */ #define TOP_ACR_CNTL2 0x02a /* Gxtvbb */ #define TOP_INFILTER_GXTVBB 0x02b @@ -206,28 +217,79 @@ #define TOP_INFILTER_I2C1 0x02E #define TOP_INFILTER_I2C2 0x02F #define TOP_INFILTER_I2C3 0x030 +/* tl1 */ +#define TOP_PRBS_GEN 0x033 +#define TOP_PRBS_ANA_0 0x034 +#define TOP_PRBS_ANA_1 0x035 +#define TOP_PRBS_ANA_STAT 0x036 +#define TOP_PRBS_ANA_BER_CH0 0x037 +#define TOP_PRBS_ANA_BER_CH1 0x038 +#define TOP_PRBS_ANA_BER_CH2 0x039 +#define TOP_METER_CABLE_CNTL 0x03a +#define TOP_METER_CABLE_STAT 0x03b +#define TOP_CHAN_SWITCH_1 0x03c +/* tl1 */ +#define TOP_AUDPLL_LOCK_FILTER 0x040 + +/* tl1 */ +#define TOP_CHAN01_ERRCNT 0x041 +#define TOP_CHAN2_ERRCNT 0x042 +#define TOP_TL1_ACR_CNTL2 0x043 +#define TOP_ACR_N_STAT 0x044 +#define TOP_ACR_CTS_STAT 0x045 +#define TOP_AUDMEAS_CTRL 0x046 +#define TOP_AUDMEAS_CYCLES_M1 0x047 +#define TOP_AUDMEAS_INTR_MASKN 0x048 +#define TOP_AUDMEAS_INTR_STAT 0x049 +#define TOP_AUDMEAS_REF_CYCLES_STAT0 0x04a +#define TOP_AUDMEAS_REF_CYCLES_STAT1 0x04b +#define TOP_HDCP22_BSOD 0x060 + + +#define TOP_SKP_CNTL_STAT 0x061 +#define TOP_NONCE_0 0x062 +#define TOP_NONCE_1 0x063 +#define TOP_NONCE_2 0x064 +#define TOP_NONCE_3 0x065 +#define TOP_PKF_0 0x066 +#define TOP_PKF_1 0x067 +#define TOP_PKF_2 0x068 +#define TOP_PKF_3 0x069 +#define TOP_DUK_0 0x06a +#define TOP_DUK_1 0x06b +#define TOP_DUK_2 0x06c +#define TOP_DUK_3 0x06d +#define TOP_NSEC_SCRATCH 0x06e +#define TOP_SEC_SCRATCH 0x06f +/* TL1 */ +#define TOP_EMP_DDR_START_A 0x070 +#define TOP_EMP_DDR_START_B 0x071 +#define TOP_EMP_DDR_FILTER 0x072 +#define TOP_EMP_CNTL_0 0x073 +#define TOP_EMP_CNTL_1 0x074 +#define TOP_EMP_CNTMAX 0x075 +#define TOP_EMP_ERR_STAT 0x076 +#define TOP_EMP_RCV_CNT_CUR 0x077 +#define TOP_EMP_RCV_CNT_BUF 0x078 +#define TOP_EMP_DDR_ADDR_CUR 0x079 +#define TOP_EMP_DDR_PTR_S_BUF 0x07a +#define TOP_EMP_STAT_0 0x07b +#define TOP_EMP_STAT_1 0x07c +#define TOP_AXI_CNTL_0 0x080 +#define TOP_AXI_ASYNC_HOLD_ESM 0x081 +#define TOP_AXI_ASYNC_HOLD_EMP 0x082 +#define TOP_AXI_STAT_0 0x083 +#define TOP_MISC_STAT0 0x084 +#define TOP_EDID_ADDR_S 0x1000 +#define TOP_EDID_ADDR_E 0x11ff +#define TOP_DWC_BASE_OFFSET 0x8000 + -#define TOP_SKP_CNTL_STAT 0x061 -#define TOP_NONCE_0 0x062 -#define TOP_NONCE_1 0x063 -#define TOP_NONCE_2 0x064 -#define TOP_NONCE_3 0x065 -#define TOP_PKF_0 0x066 -#define TOP_PKF_1 0x067 -#define TOP_PKF_2 0x068 -#define TOP_PKF_3 0x069 -#define TOP_DUK_0 0x06a -#define TOP_DUK_1 0x06b -#define TOP_DUK_2 0x06c -#define TOP_DUK_3 0x06d -#define TOP_NSEC_SCRATCH 0x06e -#define TOP_SEC_SCRATCH 0x06f #define TOP_DONT_TOUCH0 0x0fe #define TOP_DONT_TOUCH1 0x0ff - /* hdmi2.0 new end */ -#define TOP_EDID_OFFSET 0x200 +#define TOP_EDID_OFFSET 0x200 /* * HDMI registers @@ -564,6 +626,8 @@ #define PFIFO_ACP_EN _BIT(18)/*type:0x04*/ #define PFIFO_GCP_EN _BIT(17)/*type:0x03*/ #define PFIFO_ACR_EN _BIT(16)/*type:0x01*/ +/*tl1*/ +#define PFIFO_EMP_EN _BIT(9)/*type:0x7f*/ #define GCP_GLOBAVMUTE _BIT(15) /** Packet FIFO clear min/max information */ @@ -977,6 +1041,29 @@ #define EXCEPTION_CODE MSK(8, 1) #define AUD_PLL_THRESHOLD 1000000 +/* tl1 HIU apll register */ +#define HHI_HDMIRX_APLL_CNTL0 (0xd2<<2)/* 0x4C */ +#define HHI_HDMIRX_APLL_CNTL1 (0xd3<<2)/* 0x4D */ +#define HHI_HDMIRX_APLL_CNTL2 (0xd4<<2)/* 0x4E */ +#define HHI_HDMIRX_APLL_CNTL3 (0xd5<<2)/* 0x4F */ +#define HHI_HDMIRX_APLL_CNTL4 (0xd6<<2)/* 0x50 */ + +/* tl1 HIU PHY register */ +#define HHI_HDMIRX_PHY_MISC_CNTL0 (0xd7<<2)/*0x040*/ +#define HHI_HDMIRX_PHY_MISC_CNTL1 (0xd8<<2)/*0x041*/ +#define HHI_HDMIRX_PHY_MISC_CNTL2 (0xe0<<2)/*0x042*/ +#define HHI_HDMIRX_PHY_MISC_CNTL3 (0xe1<<2)/*0x043*/ +#define HHI_HDMIRX_PHY_MISC_STAT (0xee<<2)/*0x044*/ +#define HHI_HDMIRX_PHY_DCHA_CNTL0 (0xe2<<2)/*0x045*/ +#define HHI_HDMIRX_PHY_DCHA_CNTL1 (0xe3<<2)/*0x046*/ +#define HHI_HDMIRX_PHY_DCHA_CNTL2 (0xe4<<2)/*0x047*/ +#define HHI_HDMIRX_PHY_DCHD_CNTL0 (0xe5<<2)/*0x048*/ +#define HHI_HDMIRX_PHY_DCHD_CNTL1 (0xe6<<2)/*0x049*/ +#define HHI_HDMIRX_PHY_DCHD_CNTL2 (0xe7<<2)/*0x04A*/ +#define HHI_HDMIRX_PHY_DCHD_STAT (0xef<<2)/*0x04B*/ + + + #define TMDS_CLK_MIN (24000UL) #define TMDS_CLK_MAX (340000UL) @@ -989,6 +1076,7 @@ #define HDCP22_RX_ESM_READ 0x8200001f #define HDCP22_RX_ESM_WRITE 0x8200002f #define HDCP22_RX_SET_DUK_KEY 0x8200002e +#define HDCP22_RP_SET_DUK_KEY 0x8200002c #define HDCP14_RX_SETKEY 0x8200002d enum hdcp14_key_mode_e { @@ -1010,6 +1098,8 @@ extern int md_ists_en; extern int eq_ref_voltage; extern int aud_ch_map; extern int hdcp14_key_mode; +extern int ignore_sscp_charerr; +extern int ignore_sscp_tmds; extern void wr_reg_hhi(unsigned int offset, unsigned int val); extern unsigned int rd_reg_hhi(unsigned int offset); @@ -1018,6 +1108,10 @@ extern unsigned int rd_reg(enum map_addr_module_e module, extern void wr_reg(enum map_addr_module_e module, unsigned int reg_addr, unsigned int val); +extern unsigned char rd_reg_b(enum map_addr_module_e module, + unsigned char reg_addr); +extern void wr_reg_b(enum map_addr_module_e module, + unsigned int reg_addr, unsigned char val); extern void hdmirx_wr_top(unsigned int addr, unsigned int data); extern unsigned int hdmirx_rd_top(unsigned int addr); extern void hdmirx_wr_dwc(unsigned int addr, unsigned int data); @@ -1035,12 +1129,13 @@ extern unsigned int rx_get_bits(unsigned int data, unsigned int mask); extern unsigned int rx_set_bits(unsigned int data, unsigned int mask, unsigned int value); -extern unsigned int hdmirx_get_tmds_clock(void); -extern unsigned int hdmirx_get_pixel_clock(void); -extern unsigned int hdmirx_get_audio_clock(void); -extern unsigned int hdmirx_get_esm_clock(void); -extern unsigned int hdmirx_get_mpll_div_clk(void); -extern unsigned int hdmirx_get_clock(int index); +/*extern unsigned int hdmirx_get_tmds_clock(void);*/ +/*extern unsigned int hdmirx_get_pixel_clock(void);*/ +/*extern unsigned int hdmirx_get_audio_clock(void);*/ +/*extern unsigned int hdmirx_get_esm_clock(void);*/ +/*extern unsigned int hdmirx_get_cable_clock(void);*/ +/*extern unsigned int hdmirx_get_mpll_div_clk(void);*/ +/*extern unsigned int hdmirx_get_clock(int index);*/ extern unsigned int meson_clk_measure(unsigned int clk_mux); /* hdcp22 */ @@ -1060,11 +1155,12 @@ extern unsigned int sec_top_read(unsigned int *addr); extern void sec_top_write(unsigned int *addr, unsigned int value); extern void rx_esm_tmdsclk_en(bool en); extern int hdcp22_on; +extern int hdcp14_on; extern bool hdcp22_kill_esm; extern bool hpd_to_esm; extern void hdcp22_clk_en(bool en); extern void hdmirx_hdcp22_esm_rst(void); -extern unsigned int rx_sec_set_duk(void); +extern unsigned int rx_sec_set_duk(bool repeater); extern void hdmirx_hdcp22_init(void); extern void hdcp22_suspend(void); extern void hdcp22_resume(void); @@ -1072,8 +1168,8 @@ extern void hdmirx_hdcp22_hpd(bool value); extern void esm_set_reset(bool reset); extern void esm_set_stable(bool stable); extern void rx_hpd_to_esm_handle(struct work_struct *work); - - +extern void rx_hdcp14_resume(void); +extern void hdmirx_load_firm_reset(int type); extern unsigned int hdmirx_packet_fifo_rst(void); extern unsigned int hdmirx_audio_fifo_rst(void); extern void hdmirx_phy_init(void); @@ -1097,11 +1193,65 @@ extern void rx_set_cur_hpd(uint8_t val); extern unsigned int rx_get_hdmi5v_sts(void); extern unsigned int rx_get_hpd_sts(void); -extern void cec_hw_reset(void); +extern void cec_hw_reset(unsigned int cec_sel); extern void rx_force_hpd_cfg(uint8_t hpd_level); extern void rx_force_rxsense_cfg(uint8_t level); extern void rx_force_hpd_rxsense_cfg(uint8_t level); extern void rx_audio_bandgap_rst(void); +extern void rx_audio_bandgap_rst(void); +extern void rx_phy_rxsense_pulse(unsigned int t1, unsigned int t2); +extern void rx_phy_power_on(unsigned int onoff); + + +#define K_MEASURE_SRC_HDMI_TMDSCLK 0 +#define K_MEASURE_SRC_HDMI_CABLECLK 1 + +enum measure_clk_src { + MEASURE_CLK_CABLE, + MEASURE_CLK_TMDS, + MEASURE_CLK_PIXEL, + MEASURE_CLK_MPLL, + MEASURE_CLK_AUD_PLL, + MEASURE_CLK_AUD_DIV, + MEASURE_CLK_ESM, +}; + +enum apllbw { + apll_bw_24_40 = 0, + apll_bw_40_80, + apll_bw_80_150, + apll_bw_150_300, + apll_bw_300_600, + apll_bw_null = 0xf, +}; + + +struct apll_param { + unsigned int bw; + unsigned int M; + unsigned int N; + unsigned int od; + unsigned int od_div; + unsigned int od2; + unsigned int od2_div; +}; + +extern unsigned int rx_get_clock(unsigned int clk_src); +extern unsigned int clk_util_clk_msr(unsigned int clk_mux); +extern unsigned int rx_measure_clock(enum measure_clk_src clksrc); +extern void aml_phy_init(unsigned int bw); +extern void aml_phy_pw_onoff(unsigned int onoff); +extern unsigned int aml_check_clk_bandwidth(unsigned int cableclk, + unsigned int clkrate); +extern void aml_sw_apll(unsigned int bandwidth, unsigned int cableclk); +extern void aml_phy_bw_switch(unsigned int cableclk, unsigned int clkrate); +extern unsigned int aml_phy_pll_lock(void); +extern unsigned int aml_phy_tmds_valid(void); +extern void rx_emp_to_ddr_init(void); +extern void rx_emp_field_done_irq(void); +extern void rx_emp_status(void); +extern void rx_emp_lastpkt_done_irq(void); + #endif diff --git a/drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_pktinfo.c b/drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_pktinfo.c index a78d4543ede7..d0ba34c96908 100644 --- a/drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_pktinfo.c +++ b/drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_pktinfo.c @@ -30,6 +30,7 @@ #include /* Local include */ +#include "hdmi_rx_repeater.h" #include "hdmi_rx_pktinfo.h" #include "hdmi_rx_drv.h" #include "hdmi_rx_hw.h" @@ -63,6 +64,8 @@ static struct pkt_typeregmap_st pktmaping[] = { {PKT_TYPE_ISRC2, PFIFO_ISRC2_EN}, {PKT_TYPE_GAMUT_META, PFIFO_GMT_EN}, {PKT_TYPE_AUD_META, PFIFO_AMP_EN}, + {PKT_TYPE_EMP, PFIFO_EMP_EN}, + /*end of the table*/ {K_FLAG_TAB_END, K_FLAG_TAB_END}, }; @@ -99,6 +102,7 @@ void rx_pkt_status(void) rx_pr("pkt_cnt_isrc2=%d\n", rxpktsts.pkt_cnt_isrc2); rx_pr("pkt_cnt_gameta=%d\n", rxpktsts.pkt_cnt_gameta); rx_pr("pkt_cnt_amp=%d\n", rxpktsts.pkt_cnt_amp); + rx_pr("pkt_cnt_emp=%d\n", rxpktsts.pkt_cnt_emp); rx_pr("pkt_cnt_vsi_ex=%d\n", rxpktsts.pkt_cnt_vsi_ex); rx_pr("pkt_cnt_drm_ex=%d\n", rxpktsts.pkt_cnt_drm_ex); @@ -109,6 +113,7 @@ void rx_pkt_status(void) rx_pr("pkt_cnt_gcp_ex=%d\n", rxpktsts.pkt_cnt_gcp_ex); rx_pr("pkt_cnt_amp_ex=%d\n", rxpktsts.pkt_cnt_amp_ex); rx_pr("pkt_cnt_nvbi_ex=%d\n", rxpktsts.pkt_cnt_nvbi_ex); + rx_pr("pkt_cnt_nvbi_ex=%d\n", rxpktsts.pkt_cnt_emp_ex); rx_pr("pkt_chk_flg=%d\n", rxpktsts.pkt_chk_flg); @@ -133,8 +138,8 @@ void rx_pkt_debug(void) rx_pr("vbi_infoframe_st size=%d\n", sizeof(struct vbi_infoframe_st)); rx_pr("drm_infoframe_st size=%d\n", sizeof(struct drm_infoframe_st)); - rx_pr("acr_ptk_st size=%d\n", - sizeof(struct acr_ptk_st)); + rx_pr("acr_pkt_st size=%d\n", + sizeof(struct acr_pkt_st)); rx_pr("aud_sample_pkt_st size=%d\n", sizeof(struct aud_sample_pkt_st)); rx_pr("gcp_pkt_st size=%d\n", sizeof(struct gcp_pkt_st)); @@ -158,7 +163,8 @@ void rx_pkt_debug(void) sizeof(struct msaudsmp_pkt_st)); rx_pr("onebmtstr_smaud_pkt_st size=%d\n", sizeof(struct obmaudsmp_pkt_st)); - + rx_pr("emp size=%d\n", + sizeof(struct emp_pkt_st)); memset(&rxpktsts, 0, sizeof(struct rxpkt_st)); data32 = hdmirx_rd_dwc(DWC_PDEC_CTRL); @@ -179,6 +185,9 @@ void rx_pkt_debug(void) data32 |= (rx_pkt_type_mapping(PKT_TYPE_ISRC1)); data32 |= (rx_pkt_type_mapping(PKT_TYPE_ISRC2)); data32 |= (rx_pkt_type_mapping(PKT_TYPE_GAMUT_META)); + if (rx.chip_id == CHIP_ID_TL1) + data32 |= (rx_pkt_type_mapping(PKT_TYPE_EMP)); + hdmirx_wr_dwc(DWC_PDEC_CTRL, data32); rx_pr("enable fifo\n"); @@ -342,6 +351,8 @@ void rx_debug_pktinfo(char input[][20]) enable |= _BIT(30);/* DRC_RCV*/ else enable |= _BIT(9);/* DRC_RCV*/ + if (rx.chip_id == CHIP_ID_TL1) + enable |= _BIT(9);/* EMP_RCV*/ enable |= _BIT(20);/* GMD_RCV */ enable |= _BIT(19);/* AIF_RCV */ enable |= _BIT(18);/* AVI_RCV */ @@ -382,7 +393,12 @@ void rx_debug_pktinfo(char input[][20]) sts = VSI_RCV; else if (strncmp(input[2], "amp", 3) == 0) sts = _BIT(14); - + else if (strncmp(input[2], "emp", 3) == 0) { + if (rx.chip_id == CHIP_ID_TL1) + sts = _BIT(9); + else + rx_pr("no emp function\n"); + } pdec_ists_en &= ~sts; rx_pr("pdec_ists_en=0x%x\n", pdec_ists_en); /*disable irq*/ @@ -411,6 +427,12 @@ void rx_debug_pktinfo(char input[][20]) enable |= VSI_RCV; else if (strncmp(input[2], "amp", 3) == 0) enable |= _BIT(14); + else if (strncmp(input[2], "emp", 3) == 0) { + if (rx.chip_id == CHIP_ID_TL1) + enable |= _BIT(9); + else + rx_pr("no emp function\n"); + } pdec_ists_en = enable|sts; rx_pr("pdec_ists_en=0x%x\n", pdec_ists_en); /*open irq*/ @@ -675,7 +697,7 @@ static void rx_pktdump_drm(void *pdata) static void rx_pktdump_acr(void *pdata) { - struct acr_ptk_st *pktdata = pdata; + struct acr_pkt_st *pktdata = pdata; uint32_t CTS; uint32_t N; @@ -729,6 +751,25 @@ static void rx_pktdump_acr(void *pdata) rx_pr(">------------------>end\n"); } +static void rx_pktdump_emp(void *pdata) +{ + struct emp_pkt_st *pktdata = pdata; + + rx_pr("pkttype=0x%x\n", pktdata->pkttype); + rx_pr("first=0x%x\n", pktdata->first); + rx_pr("last=0x%x\n", pktdata->last); + rx_pr("sequence_idx=0x%x\n", pktdata->sequence_idx); + rx_pr("cnt.new=0x%x\n", pktdata->cnt.new); + rx_pr("cnt.end=0x%x\n", pktdata->cnt.end); + rx_pr("cnt.ds_type=0x%x\n", pktdata->cnt.ds_type); + rx_pr("cnt.afr=0x%x\n", pktdata->cnt.afr); + rx_pr("cnt.vfr=0x%x\n", pktdata->cnt.vfr); + rx_pr("cnt.sync=0x%x\n", pktdata->cnt.sync); + rx_pr("cnt.or_id=0x%x\n", pktdata->cnt.organization_id); + rx_pr("cnt.tag=0x%x\n", pktdata->cnt.data_set_tag); + rx_pr("cnt.length=0x%x\n", pktdata->cnt.data_set_length); +} + void rx_pkt_dump(enum pkt_type_e typeID) { struct packet_info_s *prx = &rx_pkt; @@ -818,7 +859,10 @@ void rx_pkt_dump(enum pkt_type_e typeID) rx_pkt_get_amp_ex(&pktdata); rx_pktdump_raw(&pktdata); break; - + case PKT_TYPE_EMP: + rx_pktdump_emp(&prx->emp_info); + rx_pktdump_raw(&prx->emp_info); + break; default: rx_pr("warning: not support\n"); rx_pr("vsi->0x81:Vendor-Specific infoframe\n"); @@ -835,7 +879,7 @@ void rx_pkt_dump(enum pkt_type_e typeID) rx_pr("isrc2->0x06\n"); rx_pr("gmd->0x0a\n"); rx_pr("amp->0x0d\n"); - /*rx_pktdump_raw(&prx->dbg_info);*/ + rx_pr("emp->0x7f:EMP\n"); break; } @@ -895,6 +939,7 @@ void rx_pkt_initial(void) memset(&rx_pkt.mpegs_info, 0, sizeof(struct pd_infoframe_s)); memset(&rx_pkt.ntscvbi_info, 0, sizeof(struct pd_infoframe_s)); memset(&rx_pkt.drm_info, 0, sizeof(struct pd_infoframe_s)); + memset(&rx_pkt.emp_info, 0, sizeof(struct pd_infoframe_s)); memset(&rx_pkt.acr_info, 0, sizeof(struct pd_infoframe_s)); memset(&rx_pkt.gcp_info, 0, sizeof(struct pd_infoframe_s)); @@ -950,7 +995,7 @@ void rx_pkt_get_audif_ex(void *pktinfo) void rx_pkt_get_acr_ex(void *pktinfo) { - struct acr_ptk_st *pkt = pktinfo; + struct acr_pkt_st *pkt = pktinfo; uint32_t N, CTS; if (pktinfo == NULL) { @@ -958,7 +1003,7 @@ void rx_pkt_get_acr_ex(void *pktinfo) return; } - /*memset(pkt, 0, sizeof(struct acr_ptk_st));*/ + /*memset(pkt, 0, sizeof(struct acr_pkt_st));*/ pkt->pkttype = PKT_TYPE_ACR; pkt->zero0 = 0x0; @@ -1426,6 +1471,8 @@ void rx_pkt_buffclear(enum pkt_type_e pkt_type) pktinfo = &prx->ntscvbi_info; else if (pkt_type == PKT_TYPE_INFOFRAME_DRM) pktinfo = &prx->drm_info; + else if (pkt_type == PKT_TYPE_EMP) + pktinfo = &prx->emp_info; else if (pkt_type == PKT_TYPE_ACR) pktinfo = &prx->acr_info; else if (pkt_type == PKT_TYPE_GCP) @@ -1909,6 +1956,14 @@ int rx_pkt_fifodecode(struct packet_info_s *prx, pktdata, sizeof(struct pd_infoframe_s)); pktsts->pkt_op_flag &= ~PKT_OP_AMP; break; + case PKT_TYPE_EMP: + pktsts->pkt_cnt_emp++; + pktsts->pkt_op_flag |= PKT_OP_EMP; + memcpy(&prx->emp_info, + pktdata, sizeof(struct pd_infoframe_s)); + pktsts->pkt_op_flag &= ~PKT_OP_EMP; + break; + default: break; } @@ -2018,6 +2073,9 @@ readpkt: rx_pkt_get_ntscvbi_ex(&prx->ntscvbi_info); rxpktsts.pkt_op_flag &= ~PKT_OP_NVBI; rxpktsts.pkt_cnt_nvbi_ex++; + } else if (pkt_int_src == PKT_BUFF_SET_EMP) { + rxpktsts.pkt_op_flag &= ~PKT_OP_EMP; + rxpktsts.pkt_cnt_emp_ex++; } /*t2 = sched_clock();*/ diff --git a/drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_pktinfo.h b/drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_pktinfo.h index 68f79d970baa..c9fcc1a6bec2 100644 --- a/drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_pktinfo.h +++ b/drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_pktinfo.h @@ -46,6 +46,7 @@ enum pkt_decode_type { PKT_BUFF_SET_AMP = 0x80, PKT_BUFF_SET_DRM = 0x100, PKT_BUFF_SET_NVBI = 0x200, + PKT_BUFF_SET_EMP = 0x400, PKT_BUFF_SET_UNKNOWN = 0xffff, }; @@ -76,6 +77,7 @@ enum pkt_type_e { PKT_TYPE_INFOFRAME_MPEGSRC = 0x85, PKT_TYPE_INFOFRAME_NVBI = 0x86, PKT_TYPE_INFOFRAME_DRM = 0x87, + PKT_TYPE_EMP = 0x7f, PKT_TYPE_UNKNOWN, }; @@ -90,6 +92,7 @@ enum pkt_op_flag { PKT_OP_MPEGS = 0x10, PKT_OP_NVBI = 0x20, PKT_OP_DRM = 0x40, + PKT_OP_EMP = 0x80, PKT_OP_ACR = 0x100, PKT_OP_GCP = 0x200, @@ -107,7 +110,7 @@ struct pkt_typeregmap_st { }; /* audio clock regeneration pkt - 0x1 */ -struct acr_ptk_st { +struct acr_pkt_st { /*packet header*/ uint8_t pkttype; uint8_t zero0; @@ -512,6 +515,37 @@ struct obmaudsmp_pkt_st { } __packed sbpkt; } __packed; + +/* EMP pkt - 0x7f */ +struct emp_pkt_st { + /*packet header*/ + uint8_t pkttype; + /*hb1*/ + uint8_t first:1; + uint8_t last:1; + uint8_t hb1_rsvd:6; + /*hb2*/ + uint8_t sequence_idx; + + uint8_t rsvd; + /*content*/ + struct content_st { + uint8_t new:1; + uint8_t end:1; + uint8_t ds_type:2; + uint8_t afr:1; + uint8_t vfr:1; + uint8_t sync:1; + uint8_t rev_0:1; + uint8_t rev_1; + uint8_t organization_id; + uint16_t data_set_tag; + uint16_t data_set_length; + uint8_t md[21]; + } __packed cnt; +} __packed; + + /* fifo raw data type - 0x8x */ struct fifo_rawdata_st { /*packet header*/ @@ -773,7 +807,7 @@ struct drm_infoframe_st { union pktinfo { /*normal packet 0x0-0xf*/ - struct acr_ptk_st audclkgen_ptk; + struct acr_pkt_st audclkgen_ptk; struct aud_sample_pkt_st audsmp_pkt; struct gcp_pkt_st gcp_pkt; struct acp_pkt_st acp_pkt; @@ -787,6 +821,7 @@ union pktinfo { struct audmtdata_pkt_st audmeta_pkt; struct msaudsmp_pkt_st mulstraudsamp_pkt; struct obmaudsmp_pkt_st obmasmpaud_pkt; + struct emp_pkt_st emp_pkt; }; union infoframe_u { @@ -825,6 +860,7 @@ struct rxpkt_st { uint32_t pkt_cnt_isrc2; uint32_t pkt_cnt_gameta; uint32_t pkt_cnt_amp; + uint32_t pkt_cnt_emp; uint32_t pkt_cnt_vsi_ex; uint32_t pkt_cnt_drm_ex; @@ -835,6 +871,7 @@ struct rxpkt_st { uint32_t pkt_cnt_gcp_ex; uint32_t pkt_cnt_amp_ex; uint32_t pkt_cnt_nvbi_ex; + uint32_t pkt_cnt_emp_ex; uint32_t pkt_op_flag; @@ -888,6 +925,9 @@ struct packet_info_s { struct pd_infoframe_s gameta_info; /* packet type 0x0d audio metadata data */ struct pd_infoframe_s amp_info; + + /* packet type 0x7f emp */ + struct pd_infoframe_s emp_info; }; struct st_pkt_test_buff { @@ -921,6 +961,9 @@ struct st_pkt_test_buff { /* packet type 0x0d audio metadata data */ struct pd_infoframe_s amp_info; + /* packet type 0x7f EMP */ + struct pd_infoframe_s emp_info; + /*externl set*/ struct pd_infoframe_s ex_vsi; struct pd_infoframe_s ex_avi; diff --git a/drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_repeater.c b/drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_repeater.c index 47bff53d66d4..e3a1e3d765f9 100644 --- a/drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_repeater.c +++ b/drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_repeater.c @@ -37,9 +37,9 @@ #include /* Local include */ +#include "hdmi_rx_repeater.h" #include "hdmi_rx_drv.h" #include "hdmi_rx_hw.h" -#include "hdmi_rx_repeater.h" #include "hdmi_rx_wrapper.h" #include "hdmi_rx_edid.h" /*edid original data from device*/ @@ -47,6 +47,9 @@ static unsigned char receive_edid[MAX_RECEIVE_EDID]; int receive_edid_len = MAX_RECEIVE_EDID; MODULE_PARM_DESC(receive_edid, "\n receive_edid\n"); module_param_array(receive_edid, byte, &receive_edid_len, 0664); +int edid_len; +MODULE_PARM_DESC(edid_len, "\n edid_len\n"); +module_param(edid_len, int, 0664); bool new_edid; /*original bksv from device*/ static unsigned char receive_hdcp[MAX_KSV_LIST_SIZE]; @@ -56,77 +59,79 @@ module_param_array(receive_hdcp, byte, &hdcp_array_len, 0664); int hdcp_len; int hdcp_repeat_depth; bool new_hdcp; +bool start_auth_14; +MODULE_PARM_DESC(start_auth_14, "\n start_auth_14\n"); +module_param(start_auth_14, bool, 0664); + bool repeat_plug; +MODULE_PARM_DESC(repeat_plug, "\n repeat_plug\n"); +module_param(repeat_plug, bool, 0664); + int up_phy_addr;/*d c b a 4bit*/ +MODULE_PARM_DESC(up_phy_addr, "\n up_phy_addr\n"); +module_param(up_phy_addr, int, 0664); +int hdcp22_firm_switch_timeout; -bool downstream_rp_en; - -enum repeater_state_e rpt_state; - -bool hdmirx_repeat_support(void) +unsigned char *rx_get_dw_hdcp_addr(void) { - return downstream_rp_en; + return receive_hdcp; } void rx_start_repeater_auth(void) { - rpt_state = REPEATER_STATE_START; + rx.hdcp.state = REPEATER_STATE_START; + start_auth_14 = 1; rx.hdcp.delay = 0; hdcp_len = 0; hdcp_repeat_depth = 0; rx.hdcp.dev_exceed = 0; rx.hdcp.cascade_exceed = 0; + rx.hdcp.depth = 0; + rx.hdcp.count = 0; memset(&receive_hdcp, 0, sizeof(receive_hdcp)); } -void repeater_dwork_handle(struct work_struct *work) -{ - if (hdmirx_repeat_support()) { - if (rx.hdcp.hdcp_version && hdmirx_is_key_write() - && rx.open_fg) { - extcon_set_state_sync(rx.hdcp.rx_excton_auth, - EXTCON_DISP_HDMI, 0); - extcon_set_state_sync(rx.hdcp.rx_excton_auth, - EXTCON_DISP_HDMI, rx.hdcp.hdcp_version); - } - } -} - -bool hdmirx_is_key_write(void) -{ - if (hdmirx_rd_dwc(DWC_HDCP_BKSV0) != 0) - return 1; - else - return 0; -} - void rx_check_repeat(void) { + struct hdcp14_topo_s *topo_data = (struct hdcp14_topo_s *)receive_hdcp; + if (!hdmirx_repeat_support()) return; if (rx.hdcp.repeat != repeat_plug) { + /*pull down hpd if downstream plug low*/ + rx_set_cur_hpd(0); + rx_pr("firm_change:%d,repeat_plug:%d,repeat:%d\n", + rx.firm_change, repeat_plug, rx.hdcp.repeat); rx_set_repeat_signal(repeat_plug); if (!repeat_plug) { - hdcp_len = 0; - hdcp_repeat_depth = 0; + edid_len = 0; rx.hdcp.dev_exceed = 0; rx.hdcp.cascade_exceed = 0; memset(&receive_hdcp, 0, sizeof(receive_hdcp)); - new_edid = true; memset(&receive_edid, 0, sizeof(receive_edid)); - rx_send_hpd_pulse(); + up_phy_addr = 0; + /*new_edid = true;*/ + /* rx_set_cur_hpd(1); */ + /*rx.firm_change = 0;*/ + rx_pr("1firm_change:%d,repeat_plug:%d,repeat:%d\n", + rx.firm_change, repeat_plug, rx.hdcp.repeat); } } - if (new_edid) { + + /*this is addition for the downstream edid too late*/ + if (new_edid && rx.hdcp.repeat && (!rx.firm_change)) { /*check downstream plug when new plug occur*/ /*check receive change*/ + /*it's contained in hwconfig*/ hdmi_rx_top_edid_update(); + hdcp22_firm_switch_timeout = 0; new_edid = false; rx_send_hpd_pulse(); } + if (repeat_plug) { - switch (rpt_state) { + switch (rx.hdcp.state) { case REPEATER_STATE_START: rx_pr("[RX] receive aksv\n"); hdmirx_wr_bits_dwc(DWC_HDCP_RPT_CTRL, @@ -135,12 +140,16 @@ void rx_check_repeat(void) KSVLIST_LOSTAUTH, 0); hdmirx_wr_bits_dwc(DWC_HDCP_RPT_CTRL, KSVLIST_READY, 0); - rpt_state = REPEATER_STATE_WAIT_KSV; + hdmirx_wr_bits_dwc(DWC_HDCP_RPT_BSTATUS, + MAX_CASCADE_EXCEEDED, 0); + hdmirx_wr_bits_dwc(DWC_HDCP_RPT_BSTATUS, + MAX_DEVS_EXCEEDED, 0); + rx.hdcp.state = REPEATER_STATE_WAIT_KSV; break; case REPEATER_STATE_WAIT_KSV: if (!rx.cur_5v_sts) { - rpt_state = REPEATER_STATE_IDLE; + rx.hdcp.state = REPEATER_STATE_IDLE; break; } if (hdmirx_rd_bits_dwc(DWC_HDCP_RPT_CTRL, WAITING_KSV)) { @@ -152,13 +161,14 @@ void rx_check_repeat(void) } else if (rx.hdcp.delay >= KSV_LIST_WAIT_DELAY) { hdmirx_wr_bits_dwc(DWC_HDCP_RPT_CTRL, KSVLIST_TIMEOUT, 1); - rpt_state = REPEATER_STATE_IDLE; + rx.hdcp.state = REPEATER_STATE_IDLE; rx_pr("[RX] receive ksv wait timeout\n"); } - if (rx_set_repeat_aksv(receive_hdcp, hdcp_len, - hdcp_repeat_depth, rx.hdcp.dev_exceed, - rx.hdcp.cascade_exceed)) { - rpt_state = REPEATER_STATE_IDLE; + if (rx_set_repeat_aksv(topo_data->ksv_list, + topo_data->device_count, + topo_data->depth, topo_data->max_devs_exceeded, + topo_data->max_cascade_exceeded)) { + rx.hdcp.state = REPEATER_STATE_IDLE; } } /*if support hdcp2.2 jump to wait_ack else to idle*/ @@ -184,27 +194,58 @@ void rx_check_repeat(void) /*}*/ } -unsigned char *rx_get_receiver_edid(void) +void rx_reload_firm_reset(int reset) +{ + if (reset) + hdmirx_load_firm_reset(reset); + else + rx_firm_reset_end(); +} + +void rx_firm_reset_end(void) +{ + rx_pr("%s new_edid:%d\n", __func__, new_edid); + if (new_edid) { + new_edid = 0; + hdmi_rx_top_edid_update(); + } + rx.firm_change = 0; +} +unsigned char *rx_get_dw_edid_addr(void) { return receive_edid; } -int rx_set_receiver_edid(unsigned char *data, int len) +int rx_set_receiver_edid(const char *data, int len) { - if ((data == NULL) || (len == 0) || (len > MAX_RECEIVE_EDID)) + if ((data == NULL) || (len == 0)) return false; - memset(receive_edid, 0, sizeof(receive_edid)); - if ((len > 0) && (*data != 0)) + if ((len > MAX_RECEIVE_EDID) || (len < 3)) { + memset(receive_edid, 0, sizeof(receive_edid)); + edid_len = 0; + } else { memcpy(receive_edid, data, len); + edid_len = len; + } new_edid = true; return true; } -EXPORT_SYMBOL(rx_set_receiver_edid); + +void rx_hdcp14_resume(void) +{ + hdcp22_kill_esm = 0; + extcon_set_state_sync(rx.rx_excton_rx22, EXTCON_DISP_HDMI, 0); + hdmirx_wr_dwc(DWC_HDCP22_CONTROL, + 0x1000); + extcon_set_state_sync(rx.rx_excton_rx22, EXTCON_DISP_HDMI, 1); + hpd_to_esm = 1; + rx_pr("hdcp14 on\n"); +} void rx_set_repeater_support(bool enable) { - downstream_rp_en = enable; + downstream_repeat_support = enable; } EXPORT_SYMBOL(rx_set_repeater_support); @@ -224,7 +265,8 @@ bool rx_poll_dwc(uint16_t addr, uint32_t exp_data, rd_data = hdmirx_rd_dwc(addr); } } - rx_pr("poll dwc cnt :%d\n", cnt); + if (log_level & VIDEO_LOG) + rx_pr("poll dwc cnt :%d\n", cnt); if (done == 0) { /* if(log_level & ERR_LOG) */ rx_pr("poll dwc%x time-out!\n", addr); @@ -237,9 +279,13 @@ bool rx_set_repeat_aksv(unsigned char *data, int len, int depth, bool dev_exceed, bool cascade_exceed) { int i; - /*rx_pr("set ksv list len:%d,depth:%d\n", len, depth);*/ - if ((len == 0) || (data == 0) || (depth == 0)) + bool ksvlist_ready = 0; + + if ((data == 0) || (((depth == 0) || (len == 0)) + && (!dev_exceed) && (!cascade_exceed))) return false; + rx_pr("set ksv list len:%d,depth:%d, exceed count:%d,cascade:%d\n", + len, depth, dev_exceed, cascade_exceed); /*set repeat depth*/ if ((depth <= MAX_REPEAT_DEPTH) && (!cascade_exceed)) { hdmirx_wr_bits_dwc(DWC_HDCP_RPT_BSTATUS, MAX_CASCADE_EXCEEDED, @@ -249,9 +295,10 @@ bool rx_set_repeat_aksv(unsigned char *data, int len, int depth, } else { hdmirx_wr_bits_dwc(DWC_HDCP_RPT_BSTATUS, MAX_CASCADE_EXCEEDED, 1); + rx.hdcp.depth = 0; } /*set repeat count*/ - if ((len <= MAX_REPEAT_COUNT) && (!dev_exceed)) { + if ((len <= HDCP14_KSV_MAX_COUNT) && (!dev_exceed)) { hdmirx_wr_bits_dwc(DWC_HDCP_RPT_BSTATUS, MAX_DEVS_EXCEEDED, 0); rx.hdcp.count = len; @@ -260,15 +307,19 @@ bool rx_set_repeat_aksv(unsigned char *data, int len, int depth, } else { hdmirx_wr_bits_dwc(DWC_HDCP_RPT_BSTATUS, MAX_DEVS_EXCEEDED, 1); + rx.hdcp.count = 0; } /*set repeat status*/ - if (rx.hdcp.count > 0) { - rx.hdcp.repeat = true; - hdmirx_wr_bits_dwc(DWC_HDCP_RPT_CTRL, REPEATER, 1); - } else { - rx.hdcp.repeat = false; - hdmirx_wr_bits_dwc(DWC_HDCP_RPT_CTRL, REPEATER, 0); - } + /* if (rx.hdcp.count > 0) { + * rx.hdcp.repeat = true; + * hdmirx_wr_bits_dwc(DWC_HDCP_RPT_CTRL, REPEATER, 1); + *} else { + * rx.hdcp.repeat = false; + * hdmirx_wr_bits_dwc(DWC_HDCP_RPT_CTRL, REPEATER, 0); + *} + */ + ksvlist_ready = ((rx.hdcp.count > 0) && (rx.hdcp.depth > 0)); + rx_pr("[RX]write ksv list count:%d\n", rx.hdcp.count); /*write ksv list to fifo*/ for (i = 0; i < rx.hdcp.count; i++) { if (rx_poll_dwc(DWC_HDCP_RPT_CTRL, ~KSV_HOLD, KSV_HOLD, @@ -279,10 +330,11 @@ bool rx_set_repeat_aksv(unsigned char *data, int len, int depth, *(data + i*MAX_KSV_SIZE + 4)); hdmirx_wr_dwc(DWC_HDCP_RPT_KSVFIFO0, *((uint32_t *)(data + i*MAX_KSV_SIZE))); - rx_pr( - "[RX]write ksv list index:%d, ksv hi:%#x, low:%#x\n", + if (log_level & VIDEO_LOG) + rx_pr( + "[RX]write ksv list index:%d, ksv hi:%#x, low:%#x\n", i, *(data + i*MAX_KSV_SIZE + - 4), *((uint32_t *)(data + i*MAX_KSV_SIZE))); + 4), *((uint32_t *)(data + i*MAX_KSV_SIZE))); } else { return false; } @@ -290,11 +342,12 @@ bool rx_set_repeat_aksv(unsigned char *data, int len, int depth, /* Wait for ksv_hold=0*/ rx_poll_dwc(DWC_HDCP_RPT_CTRL, ~KSV_HOLD, KSV_HOLD, KSV_LIST_WR_TH); /*set ksv list ready*/ - hdmirx_wr_bits_dwc(DWC_HDCP_RPT_CTRL, KSVLIST_READY, - (rx.hdcp.count > 0)); + hdmirx_wr_bits_dwc(DWC_HDCP_RPT_CTRL, KSVLIST_READY, ksvlist_ready); /* Wait for HW completion of V value*/ - rx_poll_dwc(DWC_HDCP_RPT_CTRL, FIFO_READY, FIFO_READY, KSV_V_WR_TH); - rx_pr("[RX]write Ready signal!\n"); + if (ksvlist_ready) + rx_poll_dwc(DWC_HDCP_RPT_CTRL, FIFO_READY, + FIFO_READY, KSV_V_WR_TH); + rx_pr("[RX]write Ready signal!\n", ksvlist_ready); return true; } @@ -308,35 +361,17 @@ void rx_set_repeat_signal(bool repeat) bool rx_set_receive_hdcp(unsigned char *data, int len, int depth, bool cas_exceed, bool devs_exceed) { - if ((data != 0) && (len != 0) && (len <= MAX_REPEAT_COUNT)) - memcpy(receive_hdcp, data, len*MAX_KSV_SIZE); - rx_pr("receive ksv list len:%d,depth:%d,cas:%d,dev:%d\n", len, - depth, cas_exceed, devs_exceed); - hdcp_len = len; - hdcp_repeat_depth = depth; - rx.hdcp.cascade_exceed = cas_exceed; - rx.hdcp.dev_exceed = devs_exceed; - return true; } EXPORT_SYMBOL(rx_set_receive_hdcp); void rx_repeat_hpd_state(bool plug) { - repeat_plug = plug; } EXPORT_SYMBOL(rx_repeat_hpd_state); -void rx_repeat_hdcp_ver(int version) -{ - -} -EXPORT_SYMBOL(rx_repeat_hdcp_ver); - void rx_edid_physical_addr(int a, int b, int c, int d) { - up_phy_addr = ((d & 0xf) << 12) | ((c & 0xf) << 8) | ((b & - 0xf) << 4) | (a & 0xf); } EXPORT_SYMBOL(rx_edid_physical_addr); diff --git a/drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_repeater.h b/drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_repeater.h index 82340b4dc63a..da190fb404e2 100644 --- a/drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_repeater.h +++ b/drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_repeater.h @@ -19,11 +19,12 @@ #define __HDMIRX_REPEATER__ /* EDID */ -#define MAX_RECEIVE_EDID 33 +#define MAX_RECEIVE_EDID 40/*33*/ +#define MAX_HDR_LUMI 3 #define MAX_KSV_SIZE 5 -#define MAX_REPEAT_COUNT 127 #define MAX_REPEAT_DEPTH 7 -#define MAX_KSV_LIST_SIZE (MAX_KSV_SIZE*MAX_REPEAT_COUNT) +#define MAX_KSV_LIST_SIZE sizeof(struct hdcp14_topo_s) +#define HDCP14_KSV_MAX_COUNT 127 #define DETAILED_TIMING_LEN 18 /*size of one format in edid*/ #define FORMAT_SIZE sizeof(struct edid_audio_block_t) @@ -45,6 +46,22 @@ enum repeater_state_e { REPEATER_STATE_START, }; +struct hdcp14_topo_s { + unsigned char max_cascade_exceeded:1; + unsigned char depth:3; + unsigned char max_devs_exceeded:1; + unsigned char device_count:7; /* 1 ~ 127 */ + unsigned char ksv_list[HDCP14_KSV_MAX_COUNT * 5]; +}; + +struct hdcp_hw_info_s { + unsigned int cur_5v:4; + unsigned int open:4; + unsigned int frame_rate:8; + unsigned int signal_stable:1; + unsigned int reseved:15; +}; + extern int receive_edid_len; extern bool new_edid; extern int hdcp_array_len; @@ -53,15 +70,14 @@ extern int hdcp_repeat_depth; extern bool new_hdcp; extern bool repeat_plug; extern int up_phy_addr;/*d c b a 4bit*/ -extern bool downstream_rp_en; -void rx_set_repeater_support(bool enable); -extern int rx_set_receiver_edid(unsigned char *data, int len); +extern void rx_set_repeater_support(bool enable); +extern int rx_set_receiver_edid(const char *data, int len); extern void rx_start_repeater_auth(void); extern void rx_set_repeat_signal(bool repeat); extern bool rx_set_repeat_aksv(unsigned char *data, int len, int depth, bool dev_exceed, bool cascade_exceed); -extern unsigned char *rx_get_receiver_edid(void); +extern unsigned char *rx_get_dw_edid_addr(void); extern void repeater_dwork_handle(struct work_struct *work); bool rx_set_receive_hdcp(unsigned char *data, int len, int depth, bool cas_exceed, bool devs_exceed); @@ -69,7 +85,10 @@ void rx_repeat_hpd_state(bool plug); void rx_repeat_hdcp_ver(int version); void rx_check_repeat(void); extern bool hdmirx_is_key_write(void); - +extern void rx_reload_firm_reset(int reset); +extern void rx_firm_reset_end(void); +extern unsigned char *rx_get_dw_hdcp_addr(void); +extern unsigned char *rx_get_dw_edid_addr(void); #endif diff --git a/drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_wrapper.c b/drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_wrapper.c index 97aacda460fe..8cb5cc3c78b0 100644 --- a/drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_wrapper.c +++ b/drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_wrapper.c @@ -37,12 +37,12 @@ #include /* Local include */ +#include "hdmi_rx_repeater.h" #include "hdmi_rx_drv.h" #include "hdmi_rx_hw.h" #include "hdmi_rx_eq.h" #include "hdmi_rx_wrapper.h" #include "hdmi_rx_pktinfo.h" -#include "hdmi_rx_repeater.h" #include "hdmi_rx_edid.h" static int pll_unlock_cnt; @@ -171,6 +171,10 @@ static bool mute_kill_en; MODULE_PARM_DESC(mute_kill_en, "\n mute_kill_en\n"); module_param(mute_kill_en, bool, 0664); +int hdcp14_on; +MODULE_PARM_DESC(hdcp14_on, "\n hdcp14_on\n"); +module_param(hdcp14_on, int, 0664); + /*esm recovery mode for changing resolution & hdmi2.0*/ static int esm_recovery_mode = ESM_REC_MODE_TMDS; module_param(esm_recovery_mode, int, 0664); @@ -190,6 +194,7 @@ static int edid_update_delay = 150; int skip_frame_cnt = 1; static bool hdcp22_reauth_enable; unsigned int edid_update_flag; +unsigned int downstream_hpd_flag; static bool hdcp22_stop_auth_enable; static bool hdcp22_esm_reset2_enable; int sm_pause; @@ -266,6 +271,7 @@ static int hdmi_rx_ctrl_irq_handler(void) uint32_t intr_hdcp22 = 0; bool vsi_handle_flag = false; bool drm_handle_flag = false; + bool emp_handle_flag = false; uint32_t rx_top_intr_stat = 0; bool irq_need_clr = 0; @@ -305,7 +311,7 @@ static int hdmi_rx_ctrl_irq_handler(void) hdmirx_rd_dwc(DWC_AUD_CEC_ISTS) & hdmirx_rd_dwc(DWC_AUD_CEC_IEN); if (intr_aud_cec != 0) { - cecrx_irq_handle(); + cecb_irq_handle(); hdmirx_wr_dwc(DWC_AUD_CEC_ICLR, intr_aud_cec); } } @@ -354,11 +360,8 @@ static int hdmi_rx_ctrl_irq_handler(void) /*if (log_level & HDCP_LOG)*/ rx_pr("[*aksv*\n"); rx.hdcp.hdcp_version = HDCP_VER_14; - if (hdmirx_repeat_support()) { - queue_delayed_work(repeater_wq, &repeater_dwork, - msecs_to_jiffies(5)); + if (hdmirx_repeat_support()) rx_start_repeater_auth(); - } } } @@ -396,9 +399,18 @@ static int hdmi_rx_ctrl_irq_handler(void) if (log_level & 0x200) rx_pr("[irq] FIFO MIN\n"); } - if (rx.chip_id != CHIP_ID_TXLX) { + + if (rx.chip_id == CHIP_ID_TL1) { if (rx_get_bits(intr_pedc, - DRM_RCV_EN) != 0) { + _BIT(9)) != 0) { + if (log_level & 0x400) + rx_pr("[irq] EMP_RCV %#x\n", + intr_pedc); + emp_handle_flag = true; + } + } else if (rx.chip_id == CHIP_ID_TXLX) { + if (rx_get_bits(intr_pedc, + DRM_RCV_EN_TXLX) != 0) { if (log_level & 0x400) rx_pr("[irq] DRM_RCV_EN %#x\n", intr_pedc); @@ -406,7 +418,7 @@ static int hdmi_rx_ctrl_irq_handler(void) } } else { if (rx_get_bits(intr_pedc, - DRM_RCV_EN_TXLX) != 0) { + DRM_RCV_EN) != 0) { if (log_level & 0x400) rx_pr("[irq] DRM_RCV_EN %#x\n", intr_pedc); @@ -449,6 +461,9 @@ static int hdmi_rx_ctrl_irq_handler(void) if (drm_handle_flag) rx_pkt_handler(PKT_BUFF_SET_DRM); + if (emp_handle_flag) + rx_pkt_handler(PKT_BUFF_SET_EMP); + if (rx.irq_flag) tasklet_schedule(&rx_tasklet); @@ -474,6 +489,33 @@ reisr:hdmirx_top_intr_stat = hdmirx_rd_top(TOP_INTR_STAT); hdmirx_wr_top(TOP_INTR_STAT_CLR, hdmirx_top_intr_stat); /* modify interrupt flow for isr loading */ /* top interrupt handler */ + if (rx.hdmirxdev->data->chip_id == CHIP_ID_TL1) { + if (hdmirx_top_intr_stat & (1 << 29)) + if (log_level & 0x100) + rx_pr("[isr] sqofclk_fall\n"); + if (hdmirx_top_intr_stat & (1 << 28)) + if (log_level & 0x100) + rx_pr("[isr] sqofclk_rise\n"); + if (hdmirx_top_intr_stat & (1 << 27)) + if (log_level & 0x400) + rx_pr("[isr] DE rise edge.\n"); + if (hdmirx_top_intr_stat & (1 << 26)) { + rx_emp_lastpkt_done_irq(); + if (log_level & 0x400) + rx_pr("[isr] last_emp_done\n"); + } + if (hdmirx_top_intr_stat & (1 << 25)) { + rx_emp_field_done_irq(); + if (log_level & 0x400) + rx_pr("[isr] emp_field_done\n"); + } + if (hdmirx_top_intr_stat & (1 << 24)) + if (log_level & 0x100) + rx_pr("[isr] tmds_align_stable_chg\n"); + if (hdmirx_top_intr_stat & (1 << 23)) + if (log_level & 0x100) + rx_pr("[isr] meter_stable_chg_cable\n"); + } if (hdmirx_top_intr_stat & (1 << 13)) rx_pr("[isr] auth rise\n"); if (hdmirx_top_intr_stat & (1 << 14)) @@ -1188,7 +1230,10 @@ bool is_tmds_valid(void) if (force_vic) return true; - return (rx_get_pll_lock_sts() == 1) ? true : false; + if (rx.hdmirxdev->data->chip_id == CHIP_ID_TL1) + return (aml_phy_tmds_valid() == 1) ? true : false; + else + return (rx_get_pll_lock_sts() == 1) ? true : false; } void esm_set_reset(bool reset) @@ -1378,8 +1423,9 @@ void dump_unnormal_info(void) void rx_send_hpd_pulse(void) { - rx_set_cur_hpd(0); - fsm_restart(); + /*rx_set_cur_hpd(0);*/ + /*fsm_restart();*/ + rx.state = FSM_HPD_LOW; } static void set_hdcp(struct hdmi_rx_hdcp *hdcp, const unsigned char *b_key) @@ -1427,6 +1473,8 @@ void hdmirx_fill_key_buf(const char *buf, int size) //key_size = size; //rx_pr("HDMIRX: fill key buf, size %d\n", size); } + hdcp14_on = 1; + rx_pr("HDMIRX: fill key buf, hdcp14_on %d\n", hdcp14_on); } /* @@ -1629,8 +1677,8 @@ int rx_set_global_variable(const char *buf, int size) return pr_var(dv_nopacket_timeout, index); if (set_pr_var(tmpbuf, delay_ms_cnt, value, &index, ret)) return pr_var(delay_ms_cnt, index); - if (set_pr_var(tmpbuf, downstream_rp_en, value, &index, ret)) - return pr_var(downstream_rp_en, index); + if (set_pr_var(tmpbuf, downstream_repeat_support, value, &index, ret)) + return pr_var(downstream_repeat_support, index); if (set_pr_var(tmpbuf, eq_max_setting, value, &index, ret)) return pr_var(eq_max_setting, index); if (set_pr_var(tmpbuf, eq_dbg_ch0, value, &index, ret)) @@ -1671,6 +1719,10 @@ int rx_set_global_variable(const char *buf, int size) return pr_var(pll_unlock_max, index); if (set_pr_var(tmpbuf, esd_phy_rst_max, value, &index, ret)) return pr_var(esd_phy_rst_max, index); + if (set_pr_var(tmpbuf, ignore_sscp_charerr, value, &index, ret)) + return pr_var(ignore_sscp_charerr, index); + if (set_pr_var(tmpbuf, ignore_sscp_tmds, value, &index, ret)) + return pr_var(ignore_sscp_tmds, index); return 0; } @@ -1751,7 +1803,7 @@ void rx_get_global_variable(const char *buf) pr_var(hdcp22_on, i++); pr_var(dv_nopacket_timeout, i++); pr_var(delay_ms_cnt, i++); - pr_var(downstream_rp_en, i++); + pr_var(downstream_repeat_support, i++); pr_var(eq_max_setting, i++); pr_var(eq_dbg_ch0, i++); pr_var(eq_dbg_ch1, i++); @@ -1773,6 +1825,8 @@ void rx_get_global_variable(const char *buf) pr_var(hdcp_none_wait_max, i++); pr_var(pll_unlock_max, i++); pr_var(esd_phy_rst_max, i++); + pr_var(ignore_sscp_charerr, i++); + pr_var(ignore_sscp_tmds, i++); } void skip_frame(unsigned int cnt) @@ -1903,6 +1957,7 @@ void rx_5v_monitor(void) rx.cur_5v_sts = (pwr_sts >> rx.port) & 1; hotplug_wait_query(); if (rx.cur_5v_sts == 0) { + /*External_Mute(1);*/ #ifdef USE_NEW_FSM_METHODE set_fsm_state(FSM_5V_LOST); rx.err_code = ERR_5V_LOST; @@ -1916,6 +1971,52 @@ void rx_5v_monitor(void) rx.cur_5v_sts = (pwr_sts >> rx.port) & 1; } +/* + * func : check hdmi cable clk and clk rate + * + * note : tl1 phy, need change phy setting manually + * + */ +void rx_clk_rate_monitor(void) +{ + unsigned int cur_cable_clk; + unsigned int clk_diff; + unsigned int cur_phy_bw, i = 0; + static unsigned int phy_bw_cnt; + unsigned int cur_clk_rate; + +#ifdef K_BRINGUP_PTM + return; +#endif + + cur_cable_clk = rx_measure_clock(MEASURE_CLK_CABLE); + clk_diff = diff(rx.physts.cable_clk, cur_cable_clk); + + cur_clk_rate = rx_get_scdc_clkrate_sts(); + cur_phy_bw = aml_check_clk_bandwidth(cur_cable_clk, cur_clk_rate); + + if ((rx.cur_5v_sts) && (cur_cable_clk > 20000) && + ((rx.physts.phy_bw != cur_phy_bw) || + (rx.physts.clk_rate != cur_clk_rate) || + (clk_diff > 700))) { + + if (phy_bw_cnt++ > 1) { + phy_bw_cnt = 0; + while (i++ < 3) { + rx_pr("chg phy i=%d, cable clk:%d\n", + i, cur_cable_clk); + aml_phy_bw_switch(cur_cable_clk, cur_clk_rate); + if ((cur_cable_clk < 20000) || + aml_phy_pll_lock()) + break; + } + rx.physts.cable_clk = cur_cable_clk; + rx.physts.clk_rate = cur_clk_rate; + rx.physts.phy_bw = cur_phy_bw; + } + } +} + #ifdef USE_NEW_FSM_METHODE void rx_err_monitor(void) { @@ -1985,6 +2086,9 @@ void rx_main_state_machine(void) { int pre_auds_ch_alloc; + if (rx.hdmirxdev->data->chip_id == CHIP_ID_TL1) + rx_clk_rate_monitor(); + switch (rx.state) { case FSM_5V_LOST: if (rx.cur_5v_sts) @@ -2003,12 +2107,18 @@ void rx_main_state_machine(void) case FSM_HPD_HIGH: hpd_wait_cnt++; if (rx_get_cur_hpd_sts() == 0) { - if (hpd_wait_cnt <= hpd_wait_max) - break; + if (downstream_hpd_flag) { + if (hpd_wait_cnt <= hpd_wait_max*5) + break; + } else { + if (hpd_wait_cnt <= hpd_wait_max) + break; + } } hpd_wait_cnt = 0; clk_unstable_cnt = 0; esd_phy_rst_cnt = 0; + downstream_hpd_flag = 0; pre_port = rx.port; rx_set_cur_hpd(1); set_scdc_cfg(0, 1); @@ -2241,6 +2351,7 @@ void rx_main_state_machine(void) rx.aud_sr_unstable_cnt++; if (rx.aud_sr_unstable_cnt > aud_sr_stb_max) { unsigned int aud_sts = rx_get_aud_pll_err_sts(); + if (aud_sts == E_REQUESTCLK_ERR) { hdmirx_phy_init(); rx.state = FSM_WAIT_CLK_STABLE; @@ -2283,9 +2394,6 @@ void rx_main_state_machine(void) if (log_level & VIDEO_LOG) rx_esm_exception_monitor();/* only for debug */ - if ((hdcp22_on) && (rx.state > FSM_SIG_UNSTABLE)) { - /*monitor_hdcp22_sts();*/ - } switch (rx.state) { case FSM_HPD_LOW: @@ -2664,9 +2772,9 @@ unsigned int hdmirx_show_info(unsigned char *buf, int size) pos += snprintf(buf+pos, size-pos, "avmute skip: %d\n", rx.avmute_skip); pos += snprintf(buf+pos, size-pos, - "TMDS clock: %d\n", hdmirx_get_tmds_clock()); + "TMDS clock: %d\n", rx_measure_clock(MEASURE_CLK_TMDS)); pos += snprintf(buf+pos, size-pos, - "Pixel clock: %d\n", hdmirx_get_pixel_clock()); + "Pixel clock: %d\n", rx_measure_clock(MEASURE_CLK_PIXEL)); if (drmpkt->des_u.tp1.eotf == EOTF_SDR) pos += snprintf(buf+pos, size-pos, "HDR EOTF: %s\n", "SDR"); @@ -2694,9 +2802,9 @@ unsigned int hdmirx_show_info(unsigned char *buf, int size) pos += snprintf(buf+pos, size-pos, "audio receive data: %d\n", auds_rcv_sts); pos += snprintf(buf+pos, size-pos, - "Audio PLL clock: %d\n", hdmirx_get_audio_clock()); + "Audio PLL clock: %d\n", rx_measure_clock(MEASURE_CLK_AUD_PLL)); pos += snprintf(buf+pos, size-pos, - "mpll_div_clk: %d\n", hdmirx_get_mpll_div_clk()); + "mpll_div_clk: %d\n", rx_measure_clock(MEASURE_CLK_MPLL)); pos += snprintf(buf+pos, size-pos, "\n\nHDCP info\n\n"); @@ -2765,30 +2873,34 @@ void dump_state(unsigned char enable) rx_pr("repetition %d\n", rx.cur.repeat); rx_pr("colordepth %d", rx.cur.colordepth); rx_pr("frame_rate %d\n", rx.cur.frame_rate); - rx_pr("TMDS clock = %d\n,", - hdmirx_get_tmds_clock()); - rx_pr("Pixel clock = %d\n", - hdmirx_get_pixel_clock()); - rx_pr("rx.no_signal=%d,rx.state=%d,", - rx.no_signal, - rx.state); rx_pr("fmt=0x%x,", hdmirx_hw_get_fmt()); + rx_pr("rx.no_signal=%d,rx.state=%d,", + rx.no_signal, rx.state); + rx_pr("TMDS clock = %d\n,", + rx_measure_clock(MEASURE_CLK_TMDS)); + rx_pr("Pixel clock = %d\n", + rx_measure_clock(MEASURE_CLK_PIXEL)); + rx_pr("cable clock = %d\n", + rx_measure_clock(MEASURE_CLK_CABLE)); + rx_pr("audio clock = %d\n", + rx_measure_clock(MEASURE_CLK_AUD_PLL)); + rx_pr("aud div clock = %d\n", + rx_measure_clock(MEASURE_CLK_AUD_DIV)); + rx_pr("mpll clock = %d\n", + rx_measure_clock(MEASURE_CLK_MPLL)); + rx_pr("esm clock = %d\n", + rx_measure_clock(MEASURE_CLK_ESM)); } if (enable & 2) { rx_get_audinfo(&a); rx_pr("AudioInfo:"); - rx_pr(" CT=%u CC=%u", - a.coding_type, + rx_pr(" CT=%u CC=%u", a.coding_type, a.channel_count); - rx_pr(" SF=%u SS=%u", - a.sample_frequency, + rx_pr(" SF=%u SS=%u", a.sample_frequency, a.sample_size); - rx_pr(" CA=%u", - a.auds_ch_alloc); - rx_pr(" CTS=%d, N=%d,", - a.cts, a.n); - rx_pr("recovery clock is %d\n", - a.arc); + rx_pr(" CA=%u", a.auds_ch_alloc); + rx_pr(" CTS=%d, N=%d,", a.cts, a.n); + rx_pr("recovery clock is %d\n", a.arc); } if (enable & 4) { /***************hdcp*****************/ @@ -2814,7 +2926,7 @@ void dump_state(unsigned char enable) if (enable & 8) { rx_pr("hw_vic %d,", rx.cur.hw_vic); rx_pr("ESM clock = %d\n", - hdmirx_get_esm_clock()); + rx_measure_clock(MEASURE_CLK_ESM)); rx_pr("HDCP debug value=0x%x\n", hdmirx_rd_dwc(DWC_HDCP_DBG)); rx_pr("HDCP14 state:%d\n", @@ -2826,7 +2938,7 @@ void dump_state(unsigned char enable) rx_pr("skip frame=%d\n", rx.skip); rx_pr("avmute_skip:0x%x\n", rx.avmute_skip); rx_pr("Audio PLL clock = %d\n", - hdmirx_get_audio_clock()); + rx_measure_clock(MEASURE_CLK_AUD_PLL)); } dump_hdcp_data(); @@ -2923,7 +3035,7 @@ int hdmirx_debug(const char *buf, int size) } else if (strncmp(tmpbuf, "reg", 3) == 0) { dump_reg(); } else if (strncmp(tmpbuf, "duk", 3) == 0) { - rx_pr("hdcp22=%d\n", rx_sec_set_duk()); + rx_pr("hdcp22=%d\n", rx_sec_set_duk(hdmirx_repeat_support())); } else if (strncmp(tmpbuf, "edid", 4) == 0) { dump_edid_reg(); } else if (strncmp(tmpbuf, "load14key", 7) == 0) { @@ -2967,7 +3079,21 @@ int hdmirx_debug(const char *buf, int size) } else if (strncmp(input[0], "port3", 5) == 0) { hdmirx_open_port(TVIN_PORT_HDMI3); rx.open_fg = 1; + } else if (strncmp(input[0], "empsts", 6) == 0) { + rx_emp_status(); + } else if (strncmp(input[0], "dumpemp", 7) == 0) { + rx_emp_resource_allocate(hdmirx_dev); + } else if (strncmp(input[0], "dumptmds", 8) == 0) { + rx_tmds_resource_allocate(hdmirx_dev); + } else if (strncmp(input[0], "empbuff", 7) == 0) { + if (kstrtol(input[1], 16, &value) < 0) + rx_pr("error input Value\n"); + rx_pr("set pkt cnt:0x%x\n", value); + rx.empbuff.emppktcnt = value; + } else if (strncmp(tmpbuf, "audio", 5) == 0) { + hdmirx_audio_fifo_rst(); } + return 0; } @@ -2978,14 +3104,16 @@ void hdmirx_timer_handler(unsigned long arg) rx_5v_monitor(); rx_check_repeat(); if (rx.open_fg) { - if (!sm_pause) - rx_main_state_machine(); rx_nosig_monitor(); - rx_pkt_check_content(); - #ifdef USE_NEW_FSM_METHODE - rx_err_monitor(); - rx_clkrate_monitor(); - #endif + if (!hdmirx_repeat_support() || !rx.firm_change) { + if (!sm_pause) + rx_main_state_machine(); + rx_pkt_check_content(); + #ifdef USE_NEW_FSM_METHODE + rx_err_monitor(); + rx_clkrate_monitor(); + #endif + } } devp->timer.expires = jiffies + TIMER_STATE_CHECK; add_timer(&devp->timer); diff --git a/drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_wrapper.h b/drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_wrapper.h index df77607f65fd..85dc099c537e 100644 --- a/drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_wrapper.h +++ b/drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_wrapper.h @@ -123,8 +123,8 @@ extern void rx_acr_info_sw_update(void); extern void rx_sw_reset(int level); extern void rx_aud_pll_ctl(bool en); extern void hdmirx_timer_handler(unsigned long arg); - - +extern void rx_tmds_resource_allocate(struct device *dev); +extern void rx_emp_resource_allocate(struct device *dev); #endif diff --git a/drivers/amlogic/media/vin/tvin/tvafe/tvafe_avin_detect.c b/drivers/amlogic/media/vin/tvin/tvafe/tvafe_avin_detect.c index ebca5bacb875..60759b13e39e 100644 --- a/drivers/amlogic/media/vin/tvin/tvafe/tvafe_avin_detect.c +++ b/drivers/amlogic/media/vin/tvin/tvafe/tvafe_avin_detect.c @@ -25,6 +25,7 @@ #include #include #include +#include #include #include #include @@ -51,6 +52,12 @@ #define TVAFE_AVIN_NAME_CH1 "tvafe_avin_detect_ch1" #define TVAFE_AVIN_NAME_CH2 "tvafe_avin_detect_ch2" +/*0:670mv; 1:727mv; 2:777mv; 3:823mv; 4:865mv; 5:904mv; 6:940mv; 7:972mv*/ +static unsigned int dc_level_adj = 4; + +/*0:635mv; 1:686mv; 2:733mv; 3:776mv; 4:816mv; 5:853mv; 6:887mv; 7:919mv*/ +static unsigned int comp_level_adj = 5; + /*0:use internal VDC to bias CVBS_in*/ /*1:use ground to bias CVBS_in*/ static unsigned int detect_mode; @@ -113,6 +120,7 @@ static unsigned int s_irq_counter1_time; static unsigned int s_counter0_last_state; static unsigned int s_counter1_last_state; +static struct meson_avin_data *meson_data; static DECLARE_WAIT_QUEUE_HEAD(tvafe_avin_waitq); static int tvafe_avin_dts_parse(struct platform_device *pdev) @@ -189,6 +197,7 @@ fail_get_resource_irq: void tvafe_avin_detect_ch1_anlog_enable(bool enable) { + /*txlx,txhd,tl1 the same bit:0 for ch1 en detect*/ if (enable) W_HIU_BIT(HHI_CVBS_DETECT_CNTL, 1, AFE_CH1_EN_DETECT_BIT, AFE_CH1_EN_DETECT_WIDTH); @@ -199,12 +208,21 @@ void tvafe_avin_detect_ch1_anlog_enable(bool enable) void tvafe_avin_detect_ch2_anlog_enable(bool enable) { - if (enable) - W_HIU_BIT(HHI_CVBS_DETECT_CNTL, 1, + if (enable) { + if (meson_data) + W_HIU_BIT(HHI_CVBS_DETECT_CNTL, 1, + AFE_TL_CH2_EN_DETECT_BIT, AFE_TL_CH2_EN_DETECT_WIDTH); + else + W_HIU_BIT(HHI_CVBS_DETECT_CNTL, 1, AFE_CH2_EN_DETECT_BIT, AFE_CH2_EN_DETECT_WIDTH); - else - W_HIU_BIT(HHI_CVBS_DETECT_CNTL, 0, + } else { + if (meson_data) + W_HIU_BIT(HHI_CVBS_DETECT_CNTL, 0, + AFE_TL_CH2_EN_DETECT_BIT, AFE_TL_CH2_EN_DETECT_WIDTH); + else + W_HIU_BIT(HHI_CVBS_DETECT_CNTL, 0, AFE_CH2_EN_DETECT_BIT, AFE_CH2_EN_DETECT_WIDTH); + } } static void tvafe_avin_detect_enable(struct tvafe_avin_det_s *avin_data) @@ -321,82 +339,124 @@ static int tvafe_register_avin_dev(struct tvafe_avin_det_s *avin_data) /*after adc and afe is enable,this TIP bit must be set to "0"*/ void tvafe_cha1_SYNCTIP_close_config(void) { - W_HIU_BIT(HHI_CVBS_DETECT_CNTL, 0, AFE_CH1_EN_SYNC_TIP_BIT, - AFE_CH1_EN_SYNC_TIP_WIDTH); - W_HIU_BIT(HHI_CVBS_DETECT_CNTL, avplay_sync_level, + if (meson_data) { + W_HIU_BIT(HHI_CVBS_DETECT_CNTL, 0, AFE_CH1_EN_DC_BIAS_BIT, + AFE_CH1_EN_DC_BIAS_WIDTH); + } else { + W_HIU_BIT(HHI_CVBS_DETECT_CNTL, 0, AFE_CH1_EN_SYNC_TIP_BIT, + AFE_CH1_EN_SYNC_TIP_WIDTH); + W_HIU_BIT(HHI_CVBS_DETECT_CNTL, avplay_sync_level, AFE_CH1_SYNC_LEVEL_ADJ_BIT, AFE_CH1_SYNC_LEVEL_ADJ_WIDTH); - W_HIU_BIT(HHI_CVBS_DETECT_CNTL, 1, - AFE_CH1_SYNC_HYS_ADJ_BIT, AFE_CH1_SYNC_HYS_ADJ_WIDTH); + W_HIU_BIT(HHI_CVBS_DETECT_CNTL, 1, + AFE_CH1_SYNC_HYS_ADJ_BIT, AFE_CH1_SYNC_HYS_ADJ_WIDTH); + } } void tvafe_cha2_SYNCTIP_close_config(void) { - W_HIU_BIT(HHI_CVBS_DETECT_CNTL, 0, AFE_CH2_EN_SYNC_TIP_BIT, - AFE_CH2_EN_SYNC_TIP_WIDTH); - W_HIU_BIT(HHI_CVBS_DETECT_CNTL, avplay_sync_level, + if (meson_data) { + W_HIU_BIT(HHI_CVBS_DETECT_CNTL, 0, AFE_CH2_EN_DC_BIAS_BIT, + AFE_CH2_EN_DC_BIAS_WIDTH); + } else { + W_HIU_BIT(HHI_CVBS_DETECT_CNTL, 0, AFE_CH2_EN_SYNC_TIP_BIT, + AFE_CH2_EN_SYNC_TIP_WIDTH); + W_HIU_BIT(HHI_CVBS_DETECT_CNTL, avplay_sync_level, AFE_CH2_SYNC_LEVEL_ADJ_BIT, AFE_CH2_SYNC_LEVEL_ADJ_WIDTH); - W_HIU_BIT(HHI_CVBS_DETECT_CNTL, 0, - AFE_CH2_SYNC_HYS_ADJ_BIT, AFE_CH2_SYNC_HYS_ADJ_WIDTH); + W_HIU_BIT(HHI_CVBS_DETECT_CNTL, 0, + AFE_CH2_SYNC_HYS_ADJ_BIT, AFE_CH2_SYNC_HYS_ADJ_WIDTH); + } } /*After the CVBS is unplug,the EN_SYNC_TIP need be set to "1"*/ /*to sense the plug in operation*/ void tvafe_cha1_detect_restart_config(void) { - W_HIU_BIT(HHI_CVBS_DETECT_CNTL, 1, AFE_CH1_EN_SYNC_TIP_BIT, - AFE_CH1_EN_SYNC_TIP_WIDTH); - W_HIU_BIT(HHI_CVBS_DETECT_CNTL, sync_level, + if (meson_data) { + W_HIU_BIT(HHI_CVBS_DETECT_CNTL, 1, AFE_CH1_EN_DC_BIAS_BIT, + AFE_CH1_EN_DC_BIAS_WIDTH); + } else { + W_HIU_BIT(HHI_CVBS_DETECT_CNTL, 1, AFE_CH1_EN_SYNC_TIP_BIT, + AFE_CH1_EN_SYNC_TIP_WIDTH); + W_HIU_BIT(HHI_CVBS_DETECT_CNTL, sync_level, AFE_CH1_SYNC_LEVEL_ADJ_BIT, AFE_CH1_SYNC_LEVEL_ADJ_WIDTH); - W_HIU_BIT(HHI_CVBS_DETECT_CNTL, sync_hys_adj, - AFE_CH1_SYNC_HYS_ADJ_BIT, AFE_CH1_SYNC_HYS_ADJ_WIDTH); + W_HIU_BIT(HHI_CVBS_DETECT_CNTL, sync_hys_adj, + AFE_CH1_SYNC_HYS_ADJ_BIT, AFE_CH1_SYNC_HYS_ADJ_WIDTH); + } } void tvafe_cha2_detect_restart_config(void) { - W_HIU_BIT(HHI_CVBS_DETECT_CNTL, 1, AFE_CH2_EN_SYNC_TIP_BIT, - AFE_CH2_EN_SYNC_TIP_WIDTH); - W_HIU_BIT(HHI_CVBS_DETECT_CNTL, sync_level, + if (meson_data) { + W_HIU_BIT(HHI_CVBS_DETECT_CNTL, 1, AFE_CH2_EN_DC_BIAS_BIT, + AFE_CH2_EN_DC_BIAS_WIDTH); + } else { + W_HIU_BIT(HHI_CVBS_DETECT_CNTL, 1, AFE_CH2_EN_SYNC_TIP_BIT, + AFE_CH2_EN_SYNC_TIP_WIDTH); + W_HIU_BIT(HHI_CVBS_DETECT_CNTL, sync_level, AFE_CH2_SYNC_LEVEL_ADJ_BIT, AFE_CH2_SYNC_LEVEL_ADJ_WIDTH); - W_HIU_BIT(HHI_CVBS_DETECT_CNTL, sync_hys_adj, - AFE_CH2_SYNC_HYS_ADJ_BIT, AFE_CH2_SYNC_HYS_ADJ_WIDTH); + W_HIU_BIT(HHI_CVBS_DETECT_CNTL, sync_hys_adj, + AFE_CH2_SYNC_HYS_ADJ_BIT, AFE_CH2_SYNC_HYS_ADJ_WIDTH); + } } void tvafe_avin_detect_anlog_config(void) { - if (detect_mode == 0) { - /*for ch1*/ + if (meson_data) { + /*ch1 config*/ + W_HIU_BIT(HHI_CVBS_DETECT_CNTL, dc_level_adj, + AFE_CH1_DC_LEVEL_ADJ_BIT, AFE_CH1_DC_LEVEL_ADJ_WIDTH); + W_HIU_BIT(HHI_CVBS_DETECT_CNTL, comp_level_adj, + AFE_CH1_COMP_LEVEL_ADJ_BIT, AFE_CH1_COMP_LEVEL_ADJ_WIDTH); W_HIU_BIT(HHI_CVBS_DETECT_CNTL, 0, - AFE_DETECT_RSV1_BIT, AFE_DETECT_RSV1_WIDTH); - /*for ch2*/ + AFE_CH1_COMP_HYS_ADJ_BIT, AFE_CH1_COMP_HYS_ADJ_WIDTH); + W_HIU_BIT(HHI_CVBS_DETECT_CNTL, 1, AFE_CH1_EN_DC_BIAS_BIT, + AFE_CH1_EN_DC_BIAS_WIDTH); + + /*ch2 config*/ + W_HIU_BIT(HHI_CVBS_DETECT_CNTL, dc_level_adj, + AFE_CH2_DC_LEVEL_ADJ_BIT, AFE_CH2_DC_LEVEL_ADJ_WIDTH); + W_HIU_BIT(HHI_CVBS_DETECT_CNTL, comp_level_adj, + AFE_CH2_COMP_LEVEL_ADJ_BIT, AFE_CH2_COMP_LEVEL_ADJ_WIDTH); W_HIU_BIT(HHI_CVBS_DETECT_CNTL, 0, - AFE_DETECT_RSV3_BIT, AFE_DETECT_RSV3_WIDTH); + AFE_CH2_COMP_HYS_ADJ_BIT, AFE_CH2_COMP_HYS_ADJ_WIDTH); + W_HIU_BIT(HHI_CVBS_DETECT_CNTL, 1, AFE_CH2_EN_DC_BIAS_BIT, + AFE_CH2_EN_DC_BIAS_WIDTH); } else { - W_HIU_BIT(HHI_CVBS_DETECT_CNTL, 1, - AFE_DETECT_RSV1_BIT, AFE_DETECT_RSV1_WIDTH); - W_HIU_BIT(HHI_CVBS_DETECT_CNTL, 1, - AFE_DETECT_RSV3_BIT, AFE_DETECT_RSV3_WIDTH); - } + if (detect_mode == 0) { + /*for ch1*/ + W_HIU_BIT(HHI_CVBS_DETECT_CNTL, 0, + AFE_DETECT_RSV1_BIT, AFE_DETECT_RSV1_WIDTH); + /*for ch2*/ + W_HIU_BIT(HHI_CVBS_DETECT_CNTL, 0, + AFE_DETECT_RSV3_BIT, AFE_DETECT_RSV3_WIDTH); + } else { + W_HIU_BIT(HHI_CVBS_DETECT_CNTL, 1, + AFE_DETECT_RSV1_BIT, AFE_DETECT_RSV1_WIDTH); + W_HIU_BIT(HHI_CVBS_DETECT_CNTL, 1, + AFE_DETECT_RSV3_BIT, AFE_DETECT_RSV3_WIDTH); + } - /*ch1 config*/ - W_HIU_BIT(HHI_CVBS_DETECT_CNTL, sync_level, + /*ch1 config*/ + W_HIU_BIT(HHI_CVBS_DETECT_CNTL, sync_level, AFE_CH1_SYNC_LEVEL_ADJ_BIT, AFE_CH1_SYNC_LEVEL_ADJ_WIDTH); - W_HIU_BIT(HHI_CVBS_DETECT_CNTL, sync_hys_adj, - AFE_CH1_SYNC_HYS_ADJ_BIT, AFE_CH1_SYNC_HYS_ADJ_WIDTH); - W_HIU_BIT(HHI_CVBS_DETECT_CNTL, vdc_level, - AFE_DETECT_RSV0_BIT, AFE_DETECT_RSV0_WIDTH); - /*after adc and afe is enable,this bit must be set to "0"*/ - W_HIU_BIT(HHI_CVBS_DETECT_CNTL, 1, AFE_CH1_EN_SYNC_TIP_BIT, - AFE_CH1_EN_SYNC_TIP_WIDTH); + W_HIU_BIT(HHI_CVBS_DETECT_CNTL, sync_hys_adj, + AFE_CH1_SYNC_HYS_ADJ_BIT, AFE_CH1_SYNC_HYS_ADJ_WIDTH); + W_HIU_BIT(HHI_CVBS_DETECT_CNTL, vdc_level, + AFE_DETECT_RSV0_BIT, AFE_DETECT_RSV0_WIDTH); + /*after adc and afe is enable,this bit must be set to "0"*/ + W_HIU_BIT(HHI_CVBS_DETECT_CNTL, 1, AFE_CH1_EN_SYNC_TIP_BIT, + AFE_CH1_EN_SYNC_TIP_WIDTH); - /***ch2 config***/ - W_HIU_BIT(HHI_CVBS_DETECT_CNTL, sync_level, + /***ch2 config***/ + W_HIU_BIT(HHI_CVBS_DETECT_CNTL, sync_level, AFE_CH2_SYNC_LEVEL_ADJ_BIT, AFE_CH2_SYNC_LEVEL_ADJ_WIDTH); - W_HIU_BIT(HHI_CVBS_DETECT_CNTL, sync_hys_adj, - AFE_CH2_SYNC_HYS_ADJ_BIT, AFE_CH2_SYNC_HYS_ADJ_WIDTH); - W_HIU_BIT(HHI_CVBS_DETECT_CNTL, vdc_level, - AFE_DETECT_RSV2_BIT, AFE_DETECT_RSV2_WIDTH); - W_HIU_BIT(HHI_CVBS_DETECT_CNTL, 1, AFE_CH2_EN_SYNC_TIP_BIT, - AFE_CH2_EN_SYNC_TIP_WIDTH); + W_HIU_BIT(HHI_CVBS_DETECT_CNTL, sync_hys_adj, + AFE_CH2_SYNC_HYS_ADJ_BIT, AFE_CH2_SYNC_HYS_ADJ_WIDTH); + W_HIU_BIT(HHI_CVBS_DETECT_CNTL, vdc_level, + AFE_DETECT_RSV2_BIT, AFE_DETECT_RSV2_WIDTH); + W_HIU_BIT(HHI_CVBS_DETECT_CNTL, 1, AFE_CH2_EN_SYNC_TIP_BIT, + AFE_CH2_EN_SYNC_TIP_WIDTH); + } } void tvafe_avin_detect_digital_config(void) @@ -435,6 +495,8 @@ static void tvafe_avin_detect_state(struct tvafe_avin_det_s *avdev) avdev->report_data_s[1].channel, avdev->report_data_s[1].status); tvafe_pr_info("\t*****global param*****\n"); + tvafe_pr_info("dc_level_adj: %d\n", dc_level_adj); + tvafe_pr_info("comp_level_adj: %d\n", comp_level_adj); tvafe_pr_info("detect_mode: %d\n", detect_mode); tvafe_pr_info("vdc_level: %d\n", vdc_level); tvafe_pr_info("sync_level: %d\n", sync_level); @@ -472,6 +534,10 @@ static ssize_t tvafe_avin_detect_show(struct device *dev, len += sprintf(buf+len, "\t*****usage:*****\n"); + len += sprintf(buf+len, + "echo dc_level_adj val(D) > debug\n"); + len += sprintf(buf+len, + "echo comp_level_adj val(D) > debug\n"); len += sprintf(buf+len, "echo detect_mode val(D) > debug\n"); len += sprintf(buf+len, @@ -518,7 +584,15 @@ static ssize_t tvafe_avin_detect_store(struct device *dev, tvafe_avin_detect_parse_param(buf_orig, (char **)&parm); tvafe_pr_info("[%s]:param0:%s.\n", __func__, parm[0]); - if (!strcmp(parm[0], "detect_mode")) { + if (!strcmp(parm[0], "dc_level_adj")) { + if (kstrtoul(parm[1], 10, &val) < 0) + return -EINVAL; + dc_level_adj = val; + } else if (!strcmp(parm[0], "comp_level_adj")) { + if (kstrtoul(parm[1], 10, &val) < 0) + return -EINVAL; + comp_level_adj = val; + } else if (!strcmp(parm[0], "detect_mode")) { if (kstrtoul(parm[1], 10, &val) < 0) return -EINVAL; detect_mode = val; @@ -594,17 +668,31 @@ static void tvafe_avin_detect_timer_handler(unsigned long arg) } } else if (avdev->dts_param.device_mask == TVAFE_AVIN_CH2_MASK) { avdev->irq_counter[0] = aml_read_cbus(CVBS_IRQ1_COUNTER); - if (!R_HIU_BIT(HHI_CVBS_DETECT_CNTL, - AFE_CH2_EN_DETECT_BIT, AFE_CH2_EN_DETECT_WIDTH)) - goto TIMER; + if (meson_data) { + if (!R_HIU_BIT(HHI_CVBS_DETECT_CNTL, + AFE_TL_CH2_EN_DETECT_BIT, AFE_TL_CH2_EN_DETECT_WIDTH)) + goto TIMER; + } else { + if (!R_HIU_BIT(HHI_CVBS_DETECT_CNTL, + AFE_CH2_EN_DETECT_BIT, AFE_CH2_EN_DETECT_WIDTH)) + goto TIMER; + } } else if (avdev->dts_param.device_mask == TVAFE_AVIN_MASK) { avdev->irq_counter[0] = aml_read_cbus(CVBS_IRQ0_COUNTER); avdev->irq_counter[1] = aml_read_cbus(CVBS_IRQ1_COUNTER); - if (!R_HIU_BIT(HHI_CVBS_DETECT_CNTL, + if (meson_data) { + if (!R_HIU_BIT(HHI_CVBS_DETECT_CNTL, AFE_CH1_EN_DETECT_BIT, AFE_CH1_EN_DETECT_WIDTH) || - !R_HIU_BIT(HHI_CVBS_DETECT_CNTL, - AFE_CH2_EN_DETECT_BIT, AFE_CH2_EN_DETECT_WIDTH)) - goto TIMER; + !R_HIU_BIT(HHI_CVBS_DETECT_CNTL, + AFE_TL_CH2_EN_DETECT_BIT, AFE_TL_CH2_EN_DETECT_WIDTH)) + goto TIMER; + } else { + if (!R_HIU_BIT(HHI_CVBS_DETECT_CNTL, + AFE_CH1_EN_DETECT_BIT, AFE_CH1_EN_DETECT_WIDTH) || + !R_HIU_BIT(HHI_CVBS_DETECT_CNTL, + AFE_CH2_EN_DETECT_BIT, AFE_CH2_EN_DETECT_WIDTH)) + goto TIMER; + } if (avdev->irq_counter[1] != s_irq_counter1) { if (s_counter1_last_state != 1) s_irq_counter1_time = 0; @@ -739,6 +827,12 @@ int tvafe_avin_detect_probe(struct platform_device *pdev) int state = 0; struct tvafe_avin_det_s *avdev = NULL; + meson_data = (struct meson_avin_data *) + of_device_get_match_data(&pdev->dev); + if (meson_data) + tvafe_pr_info("tvafe_avin_detect_probe cpuid:%d,%s.\n", + meson_data->cpu_id, meson_data->name); + avdev = kzalloc(sizeof(struct tvafe_avin_det_s), GFP_KERNEL); if (!avdev) { state = -ENOMEM; @@ -834,9 +928,17 @@ int tvafe_avin_detect_remove(struct platform_device *pdev) } #ifdef CONFIG_OF +struct meson_avin_data tl1_data = { + .cpu_id = AVIN_CPU_TYPE_TL1, + .name = "meson-tl1-avin-detect", +}; + static const struct of_device_id tvafe_avin_dt_match[] = { { .compatible = "amlogic, tvafe_avin_detect", }, + { .compatible = "amlogic, tl1_tvafe_avin_detect", + .data = &tl1_data, + }, {}, }; #else diff --git a/drivers/amlogic/media/vin/tvin/tvafe/tvafe_avin_detect.h b/drivers/amlogic/media/vin/tvin/tvafe/tvafe_avin_detect.h index 51cc7b330e42..f95f06e92138 100644 --- a/drivers/amlogic/media/vin/tvin/tvafe/tvafe_avin_detect.h +++ b/drivers/amlogic/media/vin/tvin/tvafe/tvafe_avin_detect.h @@ -49,6 +49,31 @@ #define AFE_CH1_EN_DETECT_BIT 0 #define AFE_CH1_EN_DETECT_WIDTH 1 +#define AFE_DETECT_RSV_BIT 28 +#define AFE_DETECT_RSV_WIDTH 4 +#define AFE_CH2_DC_LEVEL_ADJ_BIT 22 +#define AFE_CH2_DC_LEVEL_ADJ_WIDTH 3 +#define AFE_CH2_COMP_LEVEL_ADJ_BIT 19 +#define AFE_CH2_COMP_LEVEL_ADJ_WIDTH 3 +#define AFE_CH2_EN_DC_BIAS_BIT 18 +#define AFE_CH2_EN_DC_BIAS_WIDTH 1 +#define AFE_CH2_DETECT_MODE_SELECT_BIT 17 +#define AFE_CH2_DETECT_MODE_SELECT_WIDTH 1 +#define AFE_CH2_COMP_HYS_ADJ_BIT 16 +#define AFE_CH2_COMP_HYS_ADJ_WIDTH 1 +#define AFE_TL_CH2_EN_DETECT_BIT 15 +#define AFE_TL_CH2_EN_DETECT_WIDTH 1 +#define AFE_CH1_DC_LEVEL_ADJ_BIT 7 +#define AFE_CH1_DC_LEVEL_ADJ_WIDTH 3 +#define AFE_CH1_COMP_LEVEL_ADJ_BIT 4 +#define AFE_CH1_COMP_LEVEL_ADJ_WIDTH 3 +#define AFE_CH1_EN_DC_BIAS_BIT 3 +#define AFE_CH1_EN_DC_BIAS_WIDTH 1 +#define AFE_CH1_DETECT_MODE_SELECT_BIT 2 +#define AFE_CH1_DETECT_MODE_SELECT_WIDTH 1 +#define AFE_CH1_COMP_HYS_ADJ_BIT 1 +#define AFE_CH1_COMP_HYS_ADJ_WIDTH 1 + #define CVBS_IRQ0_CNTL 0x3c24 #define CVBS_IRQ_MODE_BIT 6 #define CVBS_IRQ_MODE_WIDTH 3 @@ -106,6 +131,19 @@ struct tvafe_avin_det_s { unsigned int device_num; }; +enum avin_cpu_type { + AVIN_CPU_TYPE_TXL = 0, + AVIN_CPU_TYPE_TXLX = 1, + AVIN_CPU_TYPE_TXHD = 2, + AVIN_CPU_TYPE_TL1 = 3, + AVIN_CPU_TYPE_MAX, +}; + +struct meson_avin_data { + enum avin_cpu_type cpu_id; + const char *name; +}; + void tvafe_cha1_SYNCTIP_close_config(void); void tvafe_cha2_SYNCTIP_close_config(void); void tvafe_cha1_detect_restart_config(void); diff --git a/drivers/amlogic/media/vin/tvin/tvafe/tvafe_general.c b/drivers/amlogic/media/vin/tvin/tvafe/tvafe_general.c index a4439a2620bb..363d252222d2 100644 --- a/drivers/amlogic/media/vin/tvin/tvafe/tvafe_general.c +++ b/drivers/amlogic/media/vin/tvin/tvafe/tvafe_general.c @@ -810,8 +810,10 @@ int tvafe_adc_get_pll_flag(void) { unsigned int ret = 0; - if (!mutex_trylock(&pll_mutex)) + if (!mutex_trylock(&pll_mutex)) { + tvafe_pr_info("%s trylock pll_mutex fail.\n", __func__); return 0; + } ret = adc_pll_chg; mutex_unlock(&pll_mutex); return ret; diff --git a/drivers/amlogic/media/vin/tvin/vdin/Makefile b/drivers/amlogic/media/vin/tvin/vdin/Makefile index ee325b597442..7f0c556e4178 100644 --- a/drivers/amlogic/media/vin/tvin/vdin/Makefile +++ b/drivers/amlogic/media/vin/tvin/vdin/Makefile @@ -9,3 +9,5 @@ tvin_vdin-objs += vdin_drv.o tvin_vdin-objs += vdin_ctl.o tvin_vdin-objs += vdin_sm.o tvin_vdin-objs += vdin_canvas.o +tvin_vdin-objs += vdin_afbce.o + diff --git a/drivers/amlogic/media/vin/tvin/vdin/vdin_afbce.c b/drivers/amlogic/media/vin/tvin/vdin/vdin_afbce.c new file mode 100644 index 000000000000..eaa9d734e4bb --- /dev/null +++ b/drivers/amlogic/media/vin/tvin/vdin/vdin_afbce.c @@ -0,0 +1,590 @@ +/* + * drivers/amlogic/media/vin/tvin/vdin/vdin_afbce.c + * + * Copyright (C) 2017 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +/******************** READ ME ************************ + * + * at afbce mode, 1 block = 32 * 4 pixel + * there is a header in one block. + * for example at 1080p, + * header nembers = block nembers = 1920 * 1080 / (32 * 4) + * + * table map(only at non-mmu mode): + * afbce data was saved at "body" region, + * body region has been divided for every 4K(4096 bytes) and 4K unit, + * table map contents is : (body addr >> 12) + * + * at non-mmu mode(just vdin non-mmu mode): + * ------------------------------ + * header + * (can analysis body addr) + * ------------------------------ + * table map + * (save body addr) + * ------------------------------ + * body + * (save afbce data) + * ------------------------------ + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "../tvin_global.h" +#include "../tvin_format_table.h" +#include "vdin_ctl.h" +#include "vdin_regs.h" +#include "vdin_drv.h" +#include "vdin_vf.h" +#include "vdin_canvas.h" +#include "vdin_afbce.h" + +static unsigned int max_buf_num = VDIN_CANVAS_MAX_CNT; +static unsigned int min_buf_num = 4; +static unsigned int max_buf_width = VDIN_CANVAS_MAX_WIDTH_HD; +static unsigned int max_buf_height = VDIN_CANVAS_MAX_HEIGH; +/* one frame max metadata size:32x280 bits = 1120bytes(0x460) */ +unsigned int dolby_size_bytes = PAGE_SIZE; + +unsigned int vdin_afbce_cma_alloc(struct vdin_dev_s *devp) +{ + char vdin_name[6]; + unsigned int mem_size, h_size, v_size; + int flags = CODEC_MM_FLAGS_CMA_FIRST|CODEC_MM_FLAGS_CMA_CLEAR| + CODEC_MM_FLAGS_CPU; + unsigned int max_buffer_num = min_buf_num; + unsigned int i; + /*afbce head need 1036800 byte at most*/ + unsigned int afbce_head_size_byte = PAGE_SIZE * 300;/*1.2M*/ + /*afbce map_table need 218700 byte at most*/ + unsigned int afbce_table_size_byte = PAGE_SIZE * 60;/*0.3M*/ + unsigned int afbce_mem_used; + unsigned int frame_head_size; + unsigned int mmu_used; + //unsigned long afbce_head_phy_addr; + //unsigned long afbce_table_phy_addr; + unsigned long body_start_paddr; + + if (devp->rdma_enable) + max_buffer_num++; + /*todo: need update if vf_skip_cnt used by other port*/ + if (devp->vfp->skip_vf_num && + (((devp->parm.port >= TVIN_PORT_HDMI0) && + (devp->parm.port <= TVIN_PORT_HDMI7)) || + ((devp->parm.port >= TVIN_PORT_CVBS0) && + (devp->parm.port <= TVIN_PORT_CVBS3)))) + max_buffer_num += devp->vfp->skip_vf_num; + if (max_buffer_num > max_buf_num) + max_buffer_num = max_buf_num; + devp->vfmem_max_cnt = max_buffer_num; + devp->canvas_max_num = max_buffer_num; + + if ((devp->cma_config_en == 0) || + (devp->cma_mem_alloc == 1)) { + pr_info("\nvdin%d %s use_reserved mem or cma already alloced (%d,%d)!!!\n", + devp->index, __func__, devp->cma_config_en, + devp->cma_mem_alloc); + return 0; + } + h_size = devp->h_active; + v_size = devp->v_active; + if (devp->canvas_config_mode == 1) { + h_size = max_buf_width; + v_size = max_buf_height; + } + if ((devp->format_convert == VDIN_FORMAT_CONVERT_YUV_YUV444) || + (devp->format_convert == VDIN_FORMAT_CONVERT_YUV_RGB) || + (devp->format_convert == VDIN_FORMAT_CONVERT_RGB_YUV444) || + (devp->format_convert == VDIN_FORMAT_CONVERT_RGB_RGB) || + (devp->format_convert == VDIN_FORMAT_CONVERT_YUV_GBR) || + (devp->format_convert == VDIN_FORMAT_CONVERT_YUV_BRG) || + (devp->force_yuv444_malloc == 1)) { + if ((devp->source_bitdepth > VDIN_MIN_SOURCE_BITDEPTH) && + (devp->color_depth_mode != 1)) { + h_size = roundup(h_size * + VDIN_YUV444_10BIT_PER_PIXEL_BYTE, + devp->canvas_align); + devp->canvas_alin_w = h_size / + VDIN_YUV444_10BIT_PER_PIXEL_BYTE; + } else { + h_size = roundup(h_size * + VDIN_YUV444_8BIT_PER_PIXEL_BYTE, + devp->canvas_align); + devp->canvas_alin_w = h_size / + VDIN_YUV444_8BIT_PER_PIXEL_BYTE; + } + } else if ((devp->format_convert == VDIN_FORMAT_CONVERT_YUV_NV12) || + (devp->format_convert == VDIN_FORMAT_CONVERT_YUV_NV21) || + (devp->format_convert == VDIN_FORMAT_CONVERT_RGB_NV12) || + (devp->format_convert == VDIN_FORMAT_CONVERT_RGB_NV21)) { + h_size = roundup(h_size, devp->canvas_align); + devp->canvas_alin_w = h_size; + /*todo change with canvas alloc!!*/ + /* nv21/nv12 only have 8bit mode */ + } else { + /* txl new add mode yuv422 pack mode:canvas-w=h*2*10/8 + *canvas_w must ensure divided exact by 256bit(32byte + */ + if ((devp->source_bitdepth > VDIN_MIN_SOURCE_BITDEPTH) && + ((devp->format_convert == VDIN_FORMAT_CONVERT_YUV_YUV422) || + (devp->format_convert == VDIN_FORMAT_CONVERT_RGB_YUV422) || + (devp->format_convert == VDIN_FORMAT_CONVERT_GBR_YUV422) || + (devp->format_convert == VDIN_FORMAT_CONVERT_BRG_YUV422)) && + (devp->color_depth_mode == 1)) { + h_size = roundup((h_size * 5)/2, devp->canvas_align); + devp->canvas_alin_w = (h_size * 2) / 5; + } else if ((devp->source_bitdepth > VDIN_MIN_SOURCE_BITDEPTH) && + (devp->color_depth_mode == 0)) { + h_size = roundup(h_size * + VDIN_YUV422_10BIT_PER_PIXEL_BYTE, + devp->canvas_align); + devp->canvas_alin_w = h_size / + VDIN_YUV422_10BIT_PER_PIXEL_BYTE; + } else { + h_size = roundup(h_size * + VDIN_YUV422_8BIT_PER_PIXEL_BYTE, + devp->canvas_align); + devp->canvas_alin_w = h_size / + VDIN_YUV422_8BIT_PER_PIXEL_BYTE; + } + } + mem_size = h_size * v_size; + if ((devp->format_convert >= VDIN_FORMAT_CONVERT_YUV_NV12) && + (devp->format_convert <= VDIN_FORMAT_CONVERT_RGB_NV21)) + mem_size = (mem_size * 3)/2; + devp->vfmem_size = PAGE_ALIGN(mem_size) + dolby_size_bytes; + devp->vfmem_size = (devp->vfmem_size/PAGE_SIZE + 1)*PAGE_SIZE; + + mem_size = PAGE_ALIGN(mem_size) * max_buffer_num + + dolby_size_bytes * max_buffer_num; + mem_size = (mem_size/PAGE_SIZE + 1)*PAGE_SIZE; + if (mem_size > devp->cma_mem_size) + mem_size = devp->cma_mem_size; + if (devp->index == 0) + strcpy(vdin_name, "vdin0"); + else if (devp->index == 1) + strcpy(vdin_name, "vdin1"); + + + if (devp->cma_config_flag == 0x101) { + devp->afbce_info->head_paddr = codec_mm_alloc_for_dma( + vdin_name, afbce_head_size_byte/PAGE_SIZE, 0, flags); + devp->afbce_info->table_paddr = codec_mm_alloc_for_dma( + vdin_name, afbce_table_size_byte/PAGE_SIZE, 0, flags); + devp->afbce_info->head_size = afbce_head_size_byte; + devp->afbce_info->table_size = afbce_table_size_byte; + devp->afbce_info->frame_body_size = devp->vfmem_size; + + pr_info("vdin%d head_start = 0x%lx, head_size = 0x%x\n", + devp->index, devp->afbce_info->head_paddr, + devp->afbce_info->head_size); + pr_info("vdin%d table_start = 0x%lx, table_size = 0x%x\n", + devp->index, devp->afbce_info->table_paddr, + devp->afbce_info->table_size); + + /* set fm_body_paddr */ + for (i = 0; i < max_buffer_num; i++) { + devp->afbce_info->fm_body_paddr[i] = + codec_mm_alloc_for_dma(vdin_name, + devp->vfmem_size/PAGE_SIZE, 0, flags); + if (devp->afbce_info->fm_body_paddr[i] == 0) { + pr_err("\nvdin%d-afbce buf[%d]codec alloc fail!!!\n", + devp->index, i); + devp->cma_mem_alloc = 0; + } else { + devp->cma_mem_alloc = 1; + pr_info("vdin%d fm_body_paddr[%d] = 0x%lx, body_size = 0x%x\n", + devp->index, i, + devp->afbce_info->fm_body_paddr[i], + devp->afbce_info->frame_body_size); + } + + if (devp->cma_mem_alloc == 0) + return 1; + } + pr_info("vdin%d-afbce codec cma alloc ok!\n", devp->index); + devp->mem_size = mem_size; + } else if (devp->cma_config_flag == 0) { + devp->venc_pages = dma_alloc_from_contiguous( + &(devp->this_pdev->dev), + devp->cma_mem_size >> PAGE_SHIFT, 0); + if (devp->venc_pages) { + devp->mem_start = + page_to_phys(devp->venc_pages); + devp->mem_size = mem_size; + devp->cma_mem_alloc = 1; + + devp->afbce_info->head_paddr = devp->mem_start; + devp->afbce_info->head_size = 2*SZ_1M;/*2M*/ + devp->afbce_info->table_paddr = + devp->mem_start + devp->afbce_info->head_paddr; + devp->afbce_info->table_size = 2*SZ_1M;/*2M*/ + devp->afbce_info->frame_body_size = devp->vfmem_size; + + body_start_paddr = devp->afbce_info->table_paddr + + devp->afbce_info->table_size; + + pr_info("vdin%d head_start = 0x%lx, head_size = 0x%x\n", + devp->index, devp->afbce_info->head_paddr, + devp->afbce_info->head_size); + pr_info("vdin%d table_start = 0x%lx, table_size = 0x%x\n", + devp->index, devp->afbce_info->table_paddr, + devp->afbce_info->table_size); + + /* set fm_body_paddr */ + for (i = 0; i < max_buffer_num; i++) { + devp->afbce_info->fm_body_paddr[i] = + body_start_paddr + (devp->vfmem_size * i); + + pr_info("vdin%d body[%d]_start = 0x%lx, body_size = 0x%x\n", + devp->index, i, + devp->afbce_info->fm_body_paddr[i], + devp->afbce_info->frame_body_size); + } + + /*check memory over the boundary*/ + afbce_mem_used = + devp->afbce_info->fm_body_paddr[max_buffer_num] + + devp->afbce_info->frame_body_size - + devp->afbce_info->head_paddr; + if (afbce_mem_used > devp->cma_mem_size) { + pr_info("afbce mem: afbce_mem_used(%d) > cma_mem_size(%d)\n", + afbce_mem_used, devp->cma_mem_size); + return 1; + } + devp->cma_mem_alloc = 1; + pr_info("vdin%d cma alloc ok!\n", devp->index); + } else { + devp->cma_mem_alloc = 0; + pr_err("\nvdin%d-afbce cma mem undefined2.\n", + devp->index); + return 1; + } + } + + /* 1 block = 32 * 4 pixle = 128 pixel */ + /* there is a header in one block, a header has 4 bytes */ + /* set fm_head_paddr start */ + frame_head_size = roundup(devp->h_active * devp->v_active, 128); + /*h_active * v_active / 128 * 4 = frame_head_size*/ + frame_head_size = devp->h_active * devp->v_active / 32; + frame_head_size = PAGE_ALIGN(frame_head_size); + + devp->afbce_info->frame_head_size = frame_head_size; + + for (i = 0; i < max_buffer_num; i++) { + devp->afbce_info->fm_head_paddr[i] = + devp->afbce_info->head_paddr + (frame_head_size*i); + + pr_info("vdin%d fm_head_paddr[%d] = 0x%lx, frame_head_size = 0x%x\n", + devp->index, i, + devp->afbce_info->fm_head_paddr[i], + frame_head_size); + } + /* set fm_head_paddr end */ + + /* set fm_table_paddr start */ + mmu_used = devp->afbce_info->frame_body_size >> 12; + mmu_used = mmu_used * 4; + mmu_used = PAGE_ALIGN(mmu_used); + devp->afbce_info->frame_table_size = mmu_used; + + for (i = 0; i < max_buffer_num; i++) { + devp->afbce_info->fm_table_paddr[i] = + devp->afbce_info->table_paddr + (mmu_used*i); + + pr_info("vdin%d fm_table_paddr[%d]=0x%lx, frame_table_size = 0x%x\n", + devp->index, i, + devp->afbce_info->fm_table_paddr[i], + devp->afbce_info->frame_table_size); + } + /* set fm_table_paddr end */ + + return 0; +} + +void vdin_afbce_cma_release(struct vdin_dev_s *devp) +{ + char vdin_name[6]; + unsigned int i; + + if ((devp->cma_config_en == 0) || + (devp->cma_mem_alloc == 0)) { + pr_err("\nvdin%d %s fail for (%d,%d)!!!\n", + devp->index, __func__, devp->cma_config_en, + devp->cma_mem_alloc); + return; + } + if (devp->index == 0) + strcpy(vdin_name, "vdin0"); + else if (devp->index == 1) + strcpy(vdin_name, "vdin1"); + + if (devp->cma_config_flag == 0x101) { + codec_mm_free_for_dma(vdin_name, devp->afbce_info->head_paddr); + codec_mm_free_for_dma(vdin_name, devp->afbce_info->table_paddr); + for (i = 0; i < devp->vfmem_max_cnt; i++) + codec_mm_free_for_dma(vdin_name, + devp->afbce_info->fm_body_paddr[i]); + pr_info("vdin%d-afbce codec cma release ok!\n", devp->index); + } else if (devp->venc_pages + && devp->cma_mem_size + && (devp->cma_config_flag == 0)) { + dma_release_from_contiguous( + &(devp->this_pdev->dev), + devp->venc_pages, + devp->cma_mem_size >> PAGE_SHIFT); + pr_info("vdin%d-afbce cma release ok!\n", devp->index); + } else { + pr_err("\nvdin%d %s fail for (%d,0x%x,0x%lx)!!!\n", + devp->index, __func__, devp->cma_mem_size, + devp->cma_config_flag, devp->mem_start); + } + devp->mem_start = 0; + devp->mem_size = 0; + devp->cma_mem_alloc = 0; +} + +void vdin_write_mif_or_afbce(struct vdin_dev_s *devp, + enum vdin_output_mif_e sel) +{ + unsigned int offset = devp->addr_offset; + + if (offset == 0) { + if (sel == VDIN_OUTPUT_TO_MIF) { + W_VCBUS_BIT(VDIN_MISC_CTRL, 1, VDIN0_MIF_ENABLE_BIT, 1); + W_VCBUS_BIT(VDIN_MISC_CTRL, 1, VDIN0_OUT_MIF_BIT, 1); + W_VCBUS_BIT(VDIN_MISC_CTRL, 0, VDIN0_OUT_AFBCE_BIT, 1); + } else if (sel == VDIN_OUTPUT_TO_AFBCE) { + W_VCBUS_BIT(VDIN_MISC_CTRL, 1, VDIN0_MIF_ENABLE_BIT, 1); + W_VCBUS_BIT(VDIN_MISC_CTRL, 0, VDIN0_OUT_MIF_BIT, 1); + W_VCBUS_BIT(VDIN_MISC_CTRL, 1, VDIN0_OUT_AFBCE_BIT, 1); + } + } else { + if (sel == VDIN_OUTPUT_TO_MIF) { + W_VCBUS_BIT(VDIN_MISC_CTRL, 1, VDIN1_MIF_ENABLE_BIT, 1); + W_VCBUS_BIT(VDIN_MISC_CTRL, 1, VDIN1_OUT_MIF_BIT, 1); + W_VCBUS_BIT(VDIN_MISC_CTRL, 0, VDIN1_OUT_AFBCE_BIT, 1); + } else if (sel == VDIN_OUTPUT_TO_AFBCE) { + /*sel vdin1 afbce: not support in sw now, + *just reserved interface + */ + W_VCBUS_BIT(VDIN_MISC_CTRL, 1, VDIN1_MIF_ENABLE_BIT, 1); + W_VCBUS_BIT(VDIN_MISC_CTRL, 0, VDIN1_OUT_MIF_BIT, 1); + W_VCBUS_BIT(VDIN_MISC_CTRL, 1, VDIN1_OUT_AFBCE_BIT, 1); + } + } +} + +static void afbce_wr(uint32_t reg, const uint32_t val) +{ + wr(0, reg, val); +} + +void vdin_afbce_config(struct vdin_dev_s *devp) +{ + unsigned int offset = devp->addr_offset; + int hold_line_num = 4; + int lbuf_depth = 256; + int lossy_luma_en = 0; + int lossy_chrm_en = 0; + int cur_mmu_used = 0; + int reg_format_mode;//0:444 1:422 2:420 + int reg_fmt444_comb; + int sblk_num; + int uncmp_bits; + int uncmp_size; + int def_color_0 = 0; + int def_color_1 = 0; + int def_color_2 = 0; + int def_color_3 = 0; + int hblksize_out = (devp->h_active + 31) >> 5; + int vblksize_out = (devp->v_active + 3) >> 2; + int blk_out_end_h;//output blk scope + int blk_out_bgn_h;//output blk scope + int blk_out_end_v;//output blk scope + int blk_out_bgn_v;//output blk scope + int enc_win_bgn_h;//input scope + int enc_win_end_h;//input scope + int enc_win_bgn_v;//input scope + int enc_win_end_v;//input scope + + if (offset != 0) { + pr_info("cat not use afbce on vdin1 at the moment\n"); + return; + } + + enc_win_bgn_h = 0; + enc_win_end_h = devp->h_active - 1; + enc_win_bgn_v = 0; + enc_win_end_v = devp->v_active - 1; + + blk_out_end_h = enc_win_bgn_h >> 5 ;//output blk scope + blk_out_bgn_h = (enc_win_end_h+31) >> 5 ;//output blk scope + blk_out_end_v = enc_win_bgn_v >> 2 ;//output blk scope + blk_out_bgn_v = (enc_win_end_v + 3) >> 2 ;//output blk scope + + if ((devp->prop.dest_cfmt == TVIN_YUV444) && (devp->h_active > 2048)) + reg_fmt444_comb = 1; + else + reg_fmt444_comb = 0; + + if ((devp->prop.dest_cfmt == TVIN_NV12) || + (devp->prop.dest_cfmt == TVIN_NV21)) { + reg_format_mode = 2; + sblk_num = 12; + } else if ((devp->prop.dest_cfmt == TVIN_YUV422) || + (devp->prop.dest_cfmt == TVIN_YUYV422) || + (devp->prop.dest_cfmt == TVIN_YVYU422) || + (devp->prop.dest_cfmt == TVIN_UYVY422) || + (devp->prop.dest_cfmt == TVIN_VYUY422)) { + reg_format_mode = 1; + sblk_num = 16; + } else { + reg_format_mode = 0; + sblk_num = 24; + } + uncmp_bits = devp->source_bitdepth; + + //bit size of uncompression mode + uncmp_size = (((((16*uncmp_bits*sblk_num)+7)>>3)+31)/32)<<1; + + W_VCBUS_BIT(VDIN_WRARB_REQEN_SLV, 0x1, 3, 1);//vpu arb axi_enable + W_VCBUS_BIT(VDIN_WRARB_REQEN_SLV, 0x1, 7, 1);//vpu arb axi_enable + + afbce_wr(AFBCE_MODE, + (0 & 0x7) << 29 | (0 & 0x3) << 26 | (3 & 0x3) << 24 | + (hold_line_num & 0x7f) << 16 | + (2 & 0x3) << 14 | (reg_fmt444_comb & 0x1)); + + W_VCBUS_BIT(AFBCE_QUANT_ENABLE, (lossy_luma_en & 0x1), 0, 1);//loosy + W_VCBUS_BIT(AFBCE_QUANT_ENABLE, (lossy_chrm_en & 0x1), 4, 1);//loosy + + afbce_wr(AFBCE_SIZE_IN, + ((devp->h_active & 0x1fff) << 16) | // hsize_in of afbc input + ((devp->v_active & 0x1fff) << 0) // vsize_in of afbc input + ); + + afbce_wr(AFBCE_BLK_SIZE_IN, + ((hblksize_out & 0x1fff) << 16) | // out blk hsize + ((vblksize_out & 0x1fff) << 0) // out blk vsize + ); + + //head addr of compressed data + afbce_wr(AFBCE_HEAD_BADDR, devp->afbce_info->fm_head_paddr[0]); + + W_VCBUS_BIT(AFBCE_MIF_SIZE, (uncmp_size & 0x1fff), 16, 5);//uncmp_size + + /* how to set reg when we use crop ? */ + // scope of hsize_in ,should be a integer multipe of 32 + // scope of vsize_in ,should be a integer multipe of 4 + afbce_wr(AFBCE_PIXEL_IN_HOR_SCOPE, + ((enc_win_end_h & 0x1fff) << 16) | + ((enc_win_bgn_h & 0x1fff) << 0)); + + // scope of hsize_in ,should be a integer multipe of 32 + // scope of vsize_in ,should be a integer multipe of 4 + afbce_wr(AFBCE_PIXEL_IN_VER_SCOPE, + ((enc_win_end_v & 0x1fff) << 16) | + ((enc_win_bgn_v & 0x1fff) << 0)); + + afbce_wr(AFBCE_CONV_CTRL, lbuf_depth);//fix 256 + + afbce_wr(AFBCE_MIF_HOR_SCOPE, + ((blk_out_bgn_h & 0x3ff) << 16) | // scope of out blk hsize + ((blk_out_end_h & 0xfff) << 0) // scope of out blk vsize + ); + + afbce_wr(AFBCE_MIF_VER_SCOPE, + ((blk_out_bgn_v & 0x3ff) << 16) | // scope of out blk hsize + ((blk_out_end_v & 0xfff) << 0) // scope of out blk vsize + ); + + afbce_wr(AFBCE_FORMAT, + (reg_format_mode & 0x3) << 8 | + (uncmp_bits & 0xf) << 4 | + (uncmp_bits & 0xf)); + + afbce_wr(AFBCE_DEFCOLOR_1, + ((def_color_3 & 0xfff) << 12) | // def_color_a + ((def_color_0 & 0xfff) << 0) // def_color_y + ); + + afbce_wr(AFBCE_DEFCOLOR_2, + ((def_color_2 & 0xfff) << 12) | // def_color_v + ((def_color_1 & 0xfff) << 0) // def_color_u + ); + + //cur_mmu_used += Rd(AFBCE_MMU_NUM); //4k addr have used in every frame; + + W_VCBUS_BIT(AFBCE_MMU_RMIF_CTRL4, devp->afbce_info->table_paddr, 0, 32); + W_VCBUS_BIT(AFBCE_MMU_RMIF_SCOPE_X, cur_mmu_used, 0, 12); + + W_VCBUS_BIT(AFBCE_ENABLE, 1, 8, 1);//enable afbce +} + +void vdin_afbce_maptable_init(struct vdin_dev_s *devp) +{ + unsigned int i, j; + unsigned int *ptable = NULL; + unsigned int *vtable = NULL; + unsigned int body; + unsigned int size; + + size = roundup(devp->afbce_info->frame_body_size, 4096); + + for (i = 0; i < devp->vfmem_max_cnt; i++) { + ptable = (unsigned int *) + (devp->afbce_info->fm_table_paddr[i]&0xffffffff); + if (devp->cma_config_flag == 0x101) + vtable = codec_mm_phys_to_virt((unsigned long)ptable); + else if (devp->cma_config_flag == 0) + vtable = phys_to_virt((unsigned long)ptable); + + body = devp->afbce_info->fm_body_paddr[i]&0xffffffff; + for (j = 0; j < size; j += 4096) { + *vtable = ((j + body) >> 12) & 0x000fffff; + vtable++; + } + } +} + +void vdin_afbce_set_next_frame(struct vdin_dev_s *devp, + unsigned int rdma_enable, struct vf_entry *vfe) +{ + unsigned char i; + unsigned int cur_mmu_used; + + i = vfe->af_num; + cur_mmu_used = devp->afbce_info->fm_table_paddr[i] / 4; + +#ifdef CONFIG_AML_RDMA + if (rdma_enable) + rdma_write_reg_bits(devp->rdma_handle, + AFBCE_HEAD_BADDR, devp->afbce_info->fm_head_paddr[i]); + rdma_write_reg(devp->rdma_handle, + AFBCE_MMU_RMIF_SCOPE_X, cur_mmu_used, 0, 12); + else +#endif + afbce_wr(AFBCE_HEAD_BADDR, devp->afbce_info->fm_head_paddr[i]); + W_VCBUS_BIT(AFBCE_MMU_RMIF_SCOPE_X, cur_mmu_used, 0, 12); +} + diff --git a/drivers/amlogic/media/vin/tvin/vdin/vdin_afbce.h b/drivers/amlogic/media/vin/tvin/vdin/vdin_afbce.h new file mode 100644 index 000000000000..feb2d086eca4 --- /dev/null +++ b/drivers/amlogic/media/vin/tvin/vdin/vdin_afbce.h @@ -0,0 +1,313 @@ +/* + * drivers/amlogic/media/vin/tvin/vdin/vdin_afbce.h + * + * Copyright (C) 2017 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +#ifndef __VDIN_AFBCE_H__ +#define __VDIN_AFBCE_H__ +#include "vdin_drv.h" +#include "vdin_ctl.h" + +#define AFBCE_ENABLE 0x41a0 +//Bit 31:13, reserved +//Bit 12 , reg_clk_en default = 1, +//Bit 11:9, reserved +//Bit 8, enc_enable default = 0 +//Bit 7:1, reserved +//Bit 0, enc_frm_start default = 0, + +#define AFBCE_MODE 0x41a1 +//Bit 31:29, soft_rst default = 0 ,the use as go_field +//Bit 28, reserved +//Bit 27:26, rev_mode default = 0 , reverse mode +//Bit 25:24, mif_urgent default = 3 , info mif and data mif urgent +//Bit 23, reserved +//Bit 22:16, hold_line_num default = 4, 0: burst1 1:burst2 2:burst4 +//Bit 15:14, burst_mode default = 1, 0: burst1 1:burst2 2:burst4 +//Bit 13:0, reserved + +#define AFBCE_SIZE_IN 0x41a2 +//Bit 31:29, reserved +//Bit 28:16 hsize_in default = 1920,pic horz size in.unit: pixel +//Bit 15:13, reserved +//Bit 12:0, vsize_in default = 1080,pic vert size in.unit: pixel + +#define AFBCE_BLK_SIZE_IN 0x41a3 +//Bit 31:29, reserved +//Bit 28:16 hblk_size default = 60 , pic horz size in.unit: pixel +//Bit 15:13, reserved +//Bit 12:0, vblk_size default = 270, pic vert size in.unit: pixel + +#define AFBCE_HEAD_BADDR 0x41a4 +//Bit 31:0, head_baddr unsigned, default = 32'h00; + +#define AFBCE_MIF_SIZE 0x41a5 +//Bit 31:30, reserved +//Bit 29:28, ddr_blk_size unsigned, default = 32'h128; +//Bit 27, reserved +//Bit 26:24, cmd_blk_size unsigned, default = 32'h128; +//Bit 23:21, reserved +//Bit 20:16, uncmp_size unsigned, default = 32'h128; +//Bit 15:13, reserved +//Bit 12:0, mmu_page_size unsigned, default = 32'h4096; + +#define AFBCE_PIXEL_IN_HOR_SCOPE 0x41a6 +//Bit 31:29, reserved +//Bit 28:16, enc_win_end_h unsigned, default = 1919 +//Bit 15:13, reserved +//Bit 12:0, enc_win_bgn_h unsigned, default = 0 + +#define AFBCE_PIXEL_IN_VER_SCOPE 0x41a7 +//Bit 31:29, reserved +//Bit 28:16, enc_win_end_v unsigned, default = 1079 +//Bit 15:13, reserved +//Bit 12:0, enc_win_bgn_v unsigned, default = 0 + +#define AFBCE_CONV_CTRL 0x41a8 +//Bit 31:12, reserved +//Bit 11: 0, lbuf_depth default = 256, unit=16 pixel need to set = 2^n + +#define AFBCE_MIF_HOR_SCOPE 0x41a9 +//Bit 31:26, reserved +//Bit 25:16, blk_end_h unsigned, default = 0 +//Bit 15:10, reserved +//Bit 9:0, blk_bgn_h unsigned, default = 59 + +#define AFBCE_MIF_VER_SCOPE 0x41aa +//Bit 31:28, reserved +//Bit 27:16, blk_end_v unsigned, default = 0 +//Bit 15:12, reserved +//Bit 11:0, blk_bgn_v unsigned, default = 269 + +#define AFBCE_STAT1 0x41ab +//Bit 31, ro_frm_end_pulse1 unsigned, default = 0;frame end status +//Bit 30:0, ro_dbg_top_info1 unsigned, default = 0; + +#define AFBCE_STAT2 0x41ac +//Bit 31, reserved unsigned, default = 0;frame end status +//Bit 30:0, ro_dbg_top_info2 unsigned, default = 0 + +#define AFBCE_FORMAT 0x41ad +//Bit 31:12 reserved +//Bit 11 reserved +//Bit 10 reg_inp_yuv default = 1 +// input is with yuv instead of rgb: 0: rgb, 1:yuv +//Bit 9 reg_inp_422 default = 0 +// input is with yuv422 instead of 444. 0: yuv444/yuv420; 1:yuv422 +//Bit 8 reg_inp_420 default = 1 +// input is with yuv420 instead of 444. 0: yuv444/yuv422; 1:yuv420 +//Bit 7: 4 reg_bly default = 10 luma bitwidth +//Bit 3: 0 reg_blc default = 10 chroma bitwidth + +#define AFBCE_MODE_EN 0x41ae +//Bit 31:28 reserved +//Bit 27:26 reserved +//Bit 25 reg_adpt_interleave_ymode +// RW, default = 0 force 0 to disable it: no HW implementation +//Bit 24 reg_adpt_interleave_cmode +// RW, default = 0 force 0 to disable it: not HW implementation +//Bit 23 reg_adpt_yinterleave_luma_ride +// RW, default = 1 vertical interleave piece luma reorder ride; +// 0: no reorder ride; 1: w/4 as ride +//Bit 22 reg_adpt_yinterleave_chrm_ride +// RW, default = 1 vertical interleave piece chroma reorder ride; +// 0: no reorder ride; 1: w/2 as ride +//Bit 21 reg_adpt_xinterleave_luma_ride +// RW, default = 1 vertical interleave piece luma reorder ride; +// 0: no reorder ride; 1: w/4 as ride +//Bit 20 reg_adpt_xinterleave_chrm_ride +// RW, default = 1 vertical interleave piece chroma reorder ride; +// 0: no reorder ride; 1: w/2 as ride +//Bit 19 reserved +//Bit 18 reg_disable_order_mode_i_6 +// RW, default = 0 disable order mode0~6: each mode with one +// disable bit: 0: no disable, 1: disable +//Bit 17 reg_disable_order_mode_i_5 +// RW, default = 0 disable order mode0~6: each mode with one +// disable bit: 0: no disable, 1: disable +//Bit 16 reg_disable_order_mode_i_4 +// RW, default = 0 disable order mode0~6: each mode with one +// disable bit: 0: no disable, 1: disable +//Bit 15 reg_disable_order_mode_i_3 +// RW, default = 0 disable order mode0~6: each mode with one +// disable bit: 0: no disable, 1: disable +//Bit 14 reg_disable_order_mode_i_2 +// RW, default = 0 disable order mode0~6: each mode with one +// disable bit: 0: no disable, 1: disable +//Bit 13 reg_disable_order_mode_i_1 +// RW, default = 0 disable order mode0~6: each mode with one +// disable bit: 0: no disable, 1: disable +//Bit 12 reg_disable_order_mode_i_0 +// RW, default = 0 disable order mode0~6: each mode with one +// disable bit: 0: no disable, 1: disable +//Bit 11 reserved +//Bit 10 reg_minval_yenc_en +// RW, default = 0 force disable, +// final decision to remove this ws 1% performance loss +//Bit 9 reg_16x4block_enable +// RW, default = 0 block as mission, but permit 16x4 block +//Bit 8 reg_uncompress_split_mode +// RW, default = 0 0: no split; 1: split +//Bit 7: 6 reserved +//Bit 5 reg_input_padding_uv128 +// RW, default = 0 input picture 32x4 +// block gap mode: 0: pad uv=0; 1: pad uv=128 +//Bit 4 reg_dwds_padding_uv128 +// RW, default = 0 downsampled image for double write 32x gap mode +// 0: pad uv=0; 1: pad uv=128 +//Bit 3: 1 reg_force_order_mode_value +// RW, default = 0 force order mode 0~7 +//Bit 0 reg_force_order_mode_en +// RW, default = 0 force order mode enable +// 0: no force; 1: forced to force_value + +#define AFBCE_DWSCALAR 0x41af +//Bit 31: 8 reserved +//Bit 7: 6 reg_dwscalar_w0 +// RW, default = 3 horizontal 1st step scalar mode +// 0: 1:1 no scalar; 1: 2:1 data drop (0,2,4, 6) +// pixel kept; 2: 2:1 data drop (1, 3, 5,7..) pixels kept; 3: avg +//Bit 5: 4 reg_dwscalar_w1 +// RW, default = 0 horizontal 2nd step scalar mode +// 0: 1:1 no scalar; 1: 2:1 data drop (0,2,4, 6) pixel kept; +// 2: 2:1 data drop (1, 3, 5,7..) pixels kept; 3: avg +//Bit 3: 2 reg_dwscalar_h0 +// RW, default = 2 vertical 1st step scalar mode +// 0: 1:1 no scalar; 1: 2:1 data drop (0,2,4, 6) pixel kept +// 2: 2:1 data drop (1, 3, 5,7..) pixels kept; 3: avg +//Bit 1: 0 reg_dwscalar_h1 +// RW, default = 3 vertical 2nd step scalar mode +// 0: 1:1 no scalar; 1: 2:1 data drop (0,2,4, 6) pixel kept +// 2: 2:1 data drop (1, 3, 5,7..) pixels kept; 3: avg + +#define AFBCE_DEFCOLOR_1 0x41b0 +//Bit 31:24 reserved +//Bit 23:12 reg_enc_defalutcolor_3 +// RW, default = 4095 Picture wise default color value in [Y Cb Cr] +//Bit 11: 0 reg_enc_defalutcolor_0 +// RW, default = 4095 Picture wise default color value in [Y Cb Cr] + +#define AFBCE_DEFCOLOR_2 0x41b1 +//Bit 31:24 reserved +//Bit 23:12 reg_enc_defalutcolor_2 +// RW, default = 2048 wise default color value in [Y Cb Cr] +//Bit 11: 0 reg_enc_defalutcolor_1 +// RW, default = 2048 wise default color value in [Y Cb Cr] + +#define AFBCE_QUANT_ENABLE 0x41b2 +//Bit 31:10 reserved +//Bit 9: 8 reg_bcleav_ofst +// RW, default = 0 bcleave ofset to get lower range, +// especially under lossy, for v1/v2, x=0 is equivalent, default = -1; +//Bit 7: 5 reserved +//Bit 4 reg_quant_enable_1 +// RW, default = 0 enable for quant to get some lossy +//Bit 3: 1 reserved +//Bit 0 reg_quant_enable_0 +// RW, default = 0 enable for quant to get some lossy + +#define AFBCE_IQUANT_LUT_1 0x41b3 +#define AFBCE_IQUANT_LUT_2 0x41b4 +#define AFBCE_IQUANT_LUT_3 0x41b5 +#define AFBCE_IQUANT_LUT_4 0x41b6 +#define AFBCE_RQUANT_LUT_1 0x41b7 +#define AFBCE_RQUANT_LUT_2 0x41b8 +#define AFBCE_RQUANT_LUT_3 0x41b9 +#define AFBCE_RQUANT_LUT_4 0x41ba + +#define AFBCE_YUV_FORMAT_CONV_MODE 0x41bb +//Bit 31: 8 reserved +//Bit 7 reserved +//Bit 6: 4 reg_444to422_mode RW, default = 0 +//Bit 3 reserved +//Bit 2: 0 reg_422to420_mode RW, default = 0 + +#define AFBCE_DUMMY_DATA 0x41bc +//Bit 31:30 reserved +//Bit 29: 0 reg_dummy_data RW, default = 0x00080200 + +#define AFBCE_CLR_FLAG 0x41bd +//Bit 31:0 reg_afbce_clr_flag default = 0 + +#define AFBCE_STA_FLAGT 0x41be +//Bit 31:0 ro_afbce_sta_flag default = 0 + +#define AFBCE_MMU_NUM 0x41bf +//Bit 31:16 reserved +//Bit 15: 0 ro_frm_mmu_num default = 0 + +#define AFBCE_MMU_RMIF_CTRL1 0x41c0 +//Bit 31:26 reserved +//Bit 25:24 reg_sync_sel default = 0, axi canvas id sync with frm rst +//Bit 23:16 reg_canvas_id default = 0, axi canvas id num +//Bit 15 reserved +//Bit 14:12 reg_cmd_intr_len +// default = 1, interrupt send cmd when how many series axi cmd +//Bit 11:10 reg_cmd_req_size +// default = 1, how many room fifo have, +// then axi send series req, 0=16 1=32 2=24 3=64 +//Bit 9:8 reg_burst_len +// default = 2, burst type: 0-single 1-bst2 2-bst4 +//Bit 7 reg_swap_64bit +// default = 0, 64bits of 128bit swap enable +//Bit 6 reg_little_endian +// default = 0, big endian enable +//Bit 5 reg_y_rev default = 0, vertical reverse enable +//Bit 4 reg_x_rev default = 0, horizontal reverse enable +//Bit 3 reserved +//Bit 2:0 reg_pack_mode +// default = 3, 0:4bit 1:8bit 2:16bit 3:32bit 4:64bit 5:128bit + +#define AFBCE_MMU_RMIF_CTRL2 0x41c1 +//Bit 31:30 reg_sw_rst // unsigned , default = 0, +//Bit 29:24 reserved +//Bit 23:18 reg_gclk_ctrl +//Bit 17 reserved +//Bit 16:0 reg_urgent_ctrl // unsigned , default = 0, urgent control reg + +#define AFBCE_MMU_RMIF_CTRL3 0x41c2 +//Bit 31:17 reserved +//Bit 16 reg_acc_mode // unsigned , default = 1 +//Bit 15:13 reserved +//Bit 12:0 reg_stride // unsigned , default = 4096 + +#define AFBCE_MMU_RMIF_CTRL4 0x41c3 +//Bit 31:0 reg_baddr // unsigned , default = 0 + +#define AFBCE_MMU_RMIF_SCOPE_X 0x41c4 +//Bit 31:29 reserved +//Bit 28:16 reg_x_end default = 4095, the canvas hor end pixel position +//Bit 15:13 reserved +//Bit 12: 0 reg_x_start default = 0, the canvas hor start pixel position + +#define AFBCE_MMU_RMIF_SCOPE_Y 0x41c5 +//Bit 31:29 reserved +//Bit 28:16 reg_y_end default = 0, the canvas ver end pixel position +//Bit 15:13 reserved +//Bit 12: 0 reg_y_start default = 0, the canvas ver start pixel positio + +#define AFBCE_MMU_RMIF_RO_STAT 0x41c6 + +extern void vdin_write_mif_or_afbce(struct vdin_dev_s *devp, + enum vdin_output_mif_e sel); +extern unsigned int vdin_afbce_cma_alloc(struct vdin_dev_s *devp); +extern void vdin_afbce_cma_release(struct vdin_dev_s *devp); +extern void vdin_afbce_config(struct vdin_dev_s *devp); +extern void vdin_afbce_maptable_init(struct vdin_dev_s *devp); +extern void vdin_afbce_set_next_frame(struct vdin_dev_s *devp, +unsigned int rdma_enable, struct vf_entry *vfe); + +#endif + diff --git a/drivers/amlogic/media/vin/tvin/vdin/vdin_canvas.c b/drivers/amlogic/media/vin/tvin/vdin/vdin_canvas.c index 5ae4c2da33ea..edfa775f5594 100644 --- a/drivers/amlogic/media/vin/tvin/vdin/vdin_canvas.c +++ b/drivers/amlogic/media/vin/tvin/vdin/vdin_canvas.c @@ -397,7 +397,7 @@ unsigned int vdin_cma_alloc(struct vdin_dev_s *devp) { unsigned int mem_size, h_size, v_size; int flags = CODEC_MM_FLAGS_CMA_FIRST|CODEC_MM_FLAGS_CMA_CLEAR| - CODEC_MM_FLAGS_CPU; + CODEC_MM_FLAGS_DMA; unsigned int max_buffer_num = min_buf_num; unsigned int i; diff --git a/drivers/amlogic/media/vin/tvin/vdin/vdin_ctl.c b/drivers/amlogic/media/vin/tvin/vdin/vdin_ctl.c index 421d3d92a3d5..97d58d375a3d 100644 --- a/drivers/amlogic/media/vin/tvin/vdin/vdin_ctl.c +++ b/drivers/amlogic/media/vin/tvin/vdin/vdin_ctl.c @@ -585,8 +585,8 @@ static void vdin_set_meas_mux(unsigned int offset, enum tvin_port_e port_, (bt_path == BT_PATH_GPIO_B)) meas_mux = MEAS_MUX_656_B; else if ((is_meson_gxl_cpu() || is_meson_gxm_cpu() || - is_meson_g12a_cpu() || is_meson_g12b_cpu()) && - (bt_path == BT_PATH_GPIO)) + is_meson_g12a_cpu() || is_meson_g12b_cpu() || + is_meson_tl1_cpu()) && (bt_path == BT_PATH_GPIO)) meas_mux = MEAS_MUX_656; else pr_info("cpu not define or do not support bt656"); @@ -696,8 +696,8 @@ void vdin_set_top(unsigned int offset, wr_bits(offset, VDIN_ASFIFO_CTRL3, 0xe4, VDI9_ASFIFO_CTRL_BIT, VDI9_ASFIFO_CTRL_WID); } else if ((is_meson_gxm_cpu() || is_meson_gxl_cpu() || - is_meson_g12a_cpu() || is_meson_g12b_cpu()) && - (bt_path == BT_PATH_GPIO)) { + is_meson_g12a_cpu() || is_meson_g12b_cpu() || + is_meson_tl1_cpu()) && (bt_path == BT_PATH_GPIO)) { vdin_mux = VDIN_MUX_656; wr_bits(offset, VDIN_ASFIFO_CTRL0, 0xe4, VDI1_ASFIFO_CTRL_BIT, VDI1_ASFIFO_CTRL_WID); @@ -2614,7 +2614,7 @@ void vdin_set_default_regmap(unsigned int offset) /* [11: 0] write.lfifo_buf_size = 0x100 */ if (is_meson_m8b_cpu() || is_meson_gxtvbb_cpu() || is_meson_txl_cpu() || - is_meson_txlx_cpu()) + is_meson_txlx_cpu() || is_meson_tl1_cpu()) wr(offset, VDIN_LFIFO_CTRL, 0x00000f00); else wr(offset, VDIN_LFIFO_CTRL, 0x00000780); @@ -4326,3 +4326,5 @@ void vdin_clk_onoff(struct vdin_dev_s *devp, bool onoff) wr(offset, VDIN_COM_GCLK_CTRL2, 0x55555555); } } + + diff --git a/drivers/amlogic/media/vin/tvin/vdin/vdin_ctl.h b/drivers/amlogic/media/vin/tvin/vdin/vdin_ctl.h index 4d127ae64558..178c74a0a387 100644 --- a/drivers/amlogic/media/vin/tvin/vdin/vdin_ctl.h +++ b/drivers/amlogic/media/vin/tvin/vdin/vdin_ctl.h @@ -28,6 +28,11 @@ #define DV_READ_MODE_AXI (1 << 6) #define DV_CRC_CHECK (1 << 7) +enum vdin_output_mif_e { + VDIN_OUTPUT_TO_MIF = 0, + VDIN_OUTPUT_TO_AFBCE = 1, +}; + /* *********************************************************************** */ /* *** enum definitions ********************************************* */ /* *********************************************************************** */ @@ -202,5 +207,7 @@ extern enum tvin_force_color_range_e color_range_force; extern void vdin_vlock_input_sel(unsigned int type, enum vframe_source_type_e source_type); + + #endif diff --git a/drivers/amlogic/media/vin/tvin/vdin/vdin_debug.c b/drivers/amlogic/media/vin/tvin/vdin/vdin_debug.c index 14e9bc375b4b..cf16fb1f027e 100644 --- a/drivers/amlogic/media/vin/tvin/vdin/vdin_debug.c +++ b/drivers/amlogic/media/vin/tvin/vdin/vdin_debug.c @@ -263,6 +263,8 @@ static ssize_t vdin_attr_show(struct device *dev, "echo rdma_irq_cnt >/sys/class/vdin/vdinx/attr.\n"); len += sprintf(buf+len, "echo skip_vf_num 0/1/2 /sys/class/vdin/vdinx/attr.\n"); + len += sprintf(buf+len, + "echo dump_afbce storage/xxx.bin >/sys/class/vdin/vdinx/attr\n"); return len; } static void vdin_dump_one_buf_mem(char *path, struct vdin_dev_s *devp, @@ -368,6 +370,217 @@ static void vdin_dump_mem(char *path, struct vdin_dev_s *devp) set_fs(old_fs); } +static void vdin_dump_one_afbce_mem(char *path, struct vdin_dev_s *devp, + unsigned int buf_num) +{ + struct file *filp = NULL; + loff_t pos = 0; + void *buf_head = NULL; + void *buf_table = NULL; + void *buf_body = NULL; + unsigned char buff[100]; + mm_segment_t old_fs = get_fs(); + + if (buf_num >= devp->canvas_max_num) { + pr_info("%s: param error", __func__); + return; + } + + if ((devp->cma_config_flag & 0x1) && + (devp->cma_mem_alloc == 0)) { + pr_info("%s:no cma alloc mem!!!\n", __func__); + return; + } + + if (devp->cma_config_flag == 0x101) { + buf_head = codec_mm_phys_to_virt( + devp->afbce_info->fm_head_paddr[buf_num]); + buf_table = codec_mm_phys_to_virt( + devp->afbce_info->fm_table_paddr[buf_num]); + buf_body = codec_mm_phys_to_virt( + devp->afbce_info->fm_body_paddr[buf_num]); + + pr_info(".head_paddr=0x%lx,table_paddr=0x%lx,body_paddr=0x%lx\n", + devp->afbce_info->fm_head_paddr[buf_num], + (devp->afbce_info->fm_table_paddr[buf_num]), + devp->afbce_info->fm_body_paddr[buf_num]); + } else if (devp->cma_config_flag == 0) { + buf_head = phys_to_virt( + devp->afbce_info->fm_head_paddr[buf_num]); + buf_table = phys_to_virt( + devp->afbce_info->fm_table_paddr[buf_num]); + buf_body = phys_to_virt( + devp->afbce_info->fm_body_paddr[buf_num]); + + pr_info("head_paddr=0x%lx,table_paddr=0x%lx,body_paddr=0x%lx\n", + devp->afbce_info->fm_head_paddr[buf_num], + (devp->afbce_info->fm_table_paddr[buf_num]), + devp->afbce_info->fm_body_paddr[buf_num]); + } + + set_fs(KERNEL_DS); + + /*write header bin*/ + strcpy(buff, path); + strcat(buff, "_1header.bin"); + filp = filp_open(buff, O_RDWR|O_CREAT, 0666); + if (IS_ERR(filp)) { + pr_info("create %s header error.\n", buff); + return; + } + + vfs_write(filp, buf_head, devp->afbce_info->frame_head_size, &pos); + pr_info("write buffer %2d of %2u head to %s.\n", + buf_num, devp->canvas_max_num, buff); + vfs_fsync(filp, 0); + filp_close(filp, NULL); + + /*write table bin*/ + pos = 0; + strcpy(buff, path); + strcat(buff, "_1table.bin"); + filp = filp_open(buff, O_RDWR|O_CREAT, 0666); + if (IS_ERR(filp)) { + pr_info("create %s table error.\n", buff); + return; + } + vfs_write(filp, buf_table, devp->afbce_info->frame_table_size, &pos); + pr_info("write buffer %2d of %2u table to %s.\n", + buf_num, devp->canvas_max_num, buff); + vfs_fsync(filp, 0); + filp_close(filp, NULL); + + /*write body bin*/ + pos = 0; + strcpy(buff, path); + strcat(buff, "_1body.bin"); + filp = filp_open(buff, O_RDWR|O_CREAT, 0666); + if (IS_ERR(filp)) { + pr_info("create %s body error.\n", buff); + return; + } + vfs_write(filp, buf_body, devp->afbce_info->frame_body_size, &pos); + pr_info("write buffer %2d of %2u body to %s.\n", + buf_num, devp->canvas_max_num, buff); + vfs_fsync(filp, 0); + filp_close(filp, NULL); + + set_fs(old_fs); +} + +static void vdin_dump_afbce_mem(char *path, struct vdin_dev_s *devp) +{ + struct file *filp = NULL; + loff_t pos = 0; + void *buf_head = NULL; + void *buf_table = NULL; + void *buf_body = NULL; + unsigned char buff[100]; + unsigned int i; + mm_segment_t old_fs = get_fs(); + + if ((devp->cma_config_flag & 0x1) && + (devp->cma_mem_alloc == 0)) { + pr_info("%s:no cma alloc mem!!!\n", __func__); + return; + } + + if (devp->cma_config_flag == 0x101) { + buf_head = codec_mm_phys_to_virt( + devp->afbce_info->head_paddr); + buf_table = codec_mm_phys_to_virt( + devp->afbce_info->table_paddr); + buf_body = codec_mm_phys_to_virt( + devp->afbce_info->fm_body_paddr[0]); + + pr_info(".head_paddr=0x%lx,table_paddr=0x%lx,body_paddr=0x%lx\n", + devp->afbce_info->head_paddr, + (devp->afbce_info->table_paddr), + devp->afbce_info->fm_body_paddr[0]); + } else if (devp->cma_config_flag == 0) { + buf_head = phys_to_virt( + devp->afbce_info->head_paddr); + buf_table = phys_to_virt( + devp->afbce_info->table_paddr); + buf_body = phys_to_virt( + devp->afbce_info->fm_body_paddr[0]); + + pr_info("head_paddr=0x%lx,table_paddr=0x%lx,body_paddr=0x%lx\n", + devp->afbce_info->head_paddr, + (devp->afbce_info->table_paddr), + devp->afbce_info->fm_body_paddr[0]); + } + + set_fs(KERNEL_DS); + + /* write header bin start */ + strcpy(buff, path); + strcat(buff, "_header.bin"); + filp = filp_open(buff, O_RDWR|O_CREAT, 0666); + if (IS_ERR(filp)) { + pr_info("create %s header error.\n", buff); + return; + } + + for (i = 0; i < devp->vfmem_max_cnt; i++) { + vfs_write(filp, buf_head, + devp->afbce_info->frame_head_size, &pos); + buf_head += devp->afbce_info->frame_head_size; + pr_info("write buffer %2d(0x%x bytes) of %2u head to %s.\n", + i, devp->afbce_info->frame_head_size, + devp->canvas_max_num, buff); + } + vfs_fsync(filp, 0); + filp_close(filp, NULL); + /* write header bin end */ + + /* write table bin start */ + pos = 0; + strcpy(buff, path); + strcat(buff, "_table.bin"); + filp = filp_open(buff, O_RDWR|O_CREAT, 0666); + if (IS_ERR(filp)) { + pr_info("create %s table error.\n", buff); + return; + } + + for (i = 0; i < devp->vfmem_max_cnt; i++) { + vfs_write(filp, buf_table, + devp->afbce_info->frame_table_size, &pos); + buf_table += devp->afbce_info->frame_table_size; + pr_info("write buffer %2d(0x%x bytes) of %2u table to %s.\n", + i, devp->afbce_info->frame_table_size, + devp->canvas_max_num, buff); + } + vfs_fsync(filp, 0); + filp_close(filp, NULL); + /* write table bin end */ + + /* write body bin start */ + pos = 0; + strcpy(buff, path); + strcat(buff, "_body.bin"); + filp = filp_open(buff, O_RDWR|O_CREAT, 0666); + if (IS_ERR(filp)) { + pr_info("create %s body error.\n", buff); + return; + } + + for (i = 0; i < devp->vfmem_max_cnt; i++) { + vfs_write(filp, buf_body, + devp->afbce_info->frame_body_size, &pos); + buf_body += devp->afbce_info->frame_body_size; + pr_info("write buffer %2d(0x%x bytes) of %2u body to %s.\n", + i, devp->afbce_info->frame_body_size, + devp->canvas_max_num, buff); + } + vfs_fsync(filp, 0); + filp_close(filp, NULL); + /* write body bin end */ + + set_fs(old_fs); +} + static void dump_other_mem(char *path, unsigned int start, unsigned int offset) { @@ -552,6 +765,31 @@ static void vdin_dump_state(struct vdin_dev_s *devp) pr_info("dv_flag:%d;dv_config:%d,dolby_vision:%d\n", devp->dv.dv_flag, devp->dv.dv_config, devp->prop.dolby_vision); pr_info("size of struct vdin_dev_s: %d\n", devp->vdin_dev_ssize); + + if (devp->afbce_mode == 1) { + for (i = 0; i < devp->vfmem_max_cnt; i++) { + pr_info("head(%d) addr:0x%lx, size:0x%x\n", + i, devp->afbce_info->fm_head_paddr[i], + devp->afbce_info->frame_head_size); + } + pr_info("all head size: 0x%x\n", + devp->afbce_info->head_size); + + for (i = 0; i < devp->vfmem_max_cnt; i++) { + pr_info("table(%d) addr:0x%lx, size:0x%x\n", + i, devp->afbce_info->fm_table_paddr[i], + devp->afbce_info->frame_table_size); + } + pr_info("all table size: 0x%x\n", + devp->afbce_info->table_size); + + for (i = 0; i < devp->vfmem_max_cnt; i++) { + pr_info("body(%d) addr:0x%lx, size:0x%x\n", + i, devp->afbce_info->fm_body_paddr[i], + devp->afbce_info->frame_body_size); + } + } + pr_info("Vdin driver version : %s\n", VDIN_VER); } @@ -1629,6 +1867,16 @@ start_chk: pr_info("vframe_skip(%d):%d\n\n", devp->index, devp->vfp->skip_vf_num); } + } else if (!strcmp(parm[0], "dump_afbce")) { + if (parm[2] != NULL) { + unsigned int buf_num = 0; + + if (kstrtol(parm[2], 10, &val) == 0) + buf_num = val; + vdin_dump_one_afbce_mem(parm[1], devp, buf_num); + } else if (parm[1] != NULL) { + vdin_dump_afbce_mem(parm[1], devp); + } } else { pr_info("unknown command\n"); } diff --git a/drivers/amlogic/media/vin/tvin/vdin/vdin_drv.c b/drivers/amlogic/media/vin/tvin/vdin/vdin_drv.c index 70f4ab366431..74993dc3c561 100644 --- a/drivers/amlogic/media/vin/tvin/vdin/vdin_drv.c +++ b/drivers/amlogic/media/vin/tvin/vdin/vdin_drv.c @@ -63,6 +63,7 @@ #include "vdin_sm.h" #include "vdin_vf.h" #include "vdin_canvas.h" +#include "vdin_afbce.h" #define VDIN_DRV_NAME "vdin" #define VDIN_DEV_NAME "vdin" @@ -466,17 +467,30 @@ void vdin_start_dec(struct vdin_dev_s *devp) devp->parm.v_reverse); #ifdef CONFIG_CMA vdin_cma_malloc_mode(devp); - if (vdin_cma_alloc(devp)) { - pr_err("\nvdin%d %s fail for cma alloc fail!!!\n", - devp->index, __func__); - return; + if (devp->afbce_mode == 1) { + if (vdin_afbce_cma_alloc(devp)) { + pr_err("\nvdin%d-afbce %s fail for cma alloc fail!!!\n", + devp->index, __func__); + return; + } + } else if (devp->afbce_mode == 0) { + if (vdin_cma_alloc(devp)) { + pr_err("\nvdin%d %s fail for cma alloc fail!!!\n", + devp->index, __func__); + return; + } } #endif /* h_active/v_active will be used by bellow calling */ - if (canvas_config_mode == 1) - vdin_canvas_start_config(devp); - else if (canvas_config_mode == 2) - vdin_canvas_auto_config(devp); + if (devp->afbce_mode == 0) { + if (canvas_config_mode == 1) + vdin_canvas_start_config(devp); + else if (canvas_config_mode == 2) + vdin_canvas_auto_config(devp); + } else if (devp->afbce_mode == 1) { + vdin_afbce_maptable_init(devp); + vdin_afbce_config(devp); + } #if 0 if ((devp->prop.dest_cfmt == TVIN_NV12) || (devp->prop.dest_cfmt == TVIN_NV21)) @@ -523,6 +537,14 @@ void vdin_start_dec(struct vdin_dev_s *devp) vdin_hw_enable(devp->addr_offset); vdin_set_all_regs(devp); + + if (is_meson_tl1_cpu()) { + if (devp->afbce_mode == 0) + vdin_write_mif_or_afbce(devp, VDIN_OUTPUT_TO_MIF); + else if (devp->afbce_mode == 1) + vdin_write_mif_or_afbce(devp, VDIN_OUTPUT_TO_AFBCE); + } + if (!(devp->parm.flag & TVIN_PARM_FLAG_CAP) && (devp->frontend) && devp->frontend->dec_ops && @@ -628,7 +650,10 @@ void vdin_stop_dec(struct vdin_dev_s *devp) vf_unreg_provider(&devp->vprov); devp->dv.dv_config = 0; #ifdef CONFIG_CMA - vdin_cma_release(devp); + if (devp->afbce_mode == 1) + vdin_afbce_cma_release(devp); + else if (devp->afbce_mode == 0) + vdin_cma_release(devp); #endif vdin_dolby_addr_release(devp, devp->vfp->size); @@ -1170,6 +1195,7 @@ irqreturn_t vdin_isr(int irq, void *dev_id) enum tvin_trans_fmt trans_fmt; struct tvin_sig_property_s *prop, *pre_prop; long long *clk_array; + long long vlock_delay_jiffies, vlock_t1; /* debug interrupt interval time * @@ -1288,8 +1314,14 @@ irqreturn_t vdin_isr(int irq, void *dev_id) last_field_type = devp->curr_field_type; devp->curr_field_type = vdin_get_curr_field_type(devp); - vdin_vlock_input_sel(devp->curr_field_type, - devp->curr_wr_vfe->vf.source_type); + + if (devp->duration) { + vlock_delay_jiffies = func_div(96000, devp->duration); + vlock_t1 = func_div(HZ, vlock_delay_jiffies); + vlock_delay_jiffies = func_div(vlock_t1, 4); + } else + vlock_delay_jiffies = msecs_to_jiffies(5); + schedule_delayed_work(&devp->vlock_dwork, vlock_delay_jiffies); /* ignore the unstable signal */ state = tvin_get_sm_status(devp->index); @@ -1506,8 +1538,13 @@ irqreturn_t vdin_isr(int irq, void *dev_id) } /* prepare for next input data */ next_wr_vfe = provider_vf_get(devp->vfp); - vdin_set_canvas_id(devp, (devp->flags&VDIN_FLAG_RDMA_ENABLE), - (next_wr_vfe->vf.canvas0Addr&0xff)); + if (devp->afbce_mode == 0) + vdin_set_canvas_id(devp, (devp->flags&VDIN_FLAG_RDMA_ENABLE), + (next_wr_vfe->vf.canvas0Addr&0xff)); + else if (devp->afbce_mode == 1) + vdin_afbce_set_next_frame(devp, + (devp->flags&VDIN_FLAG_RDMA_ENABLE), next_wr_vfe); + /* prepare for chroma canvas*/ if ((devp->prop.dest_cfmt == TVIN_NV12) || (devp->prop.dest_cfmt == TVIN_NV21)) @@ -1698,8 +1735,13 @@ irqreturn_t vdin_v4l2_isr(int irq, void *dev_id) /* prepare for next input data */ next_wr_vfe = provider_vf_get(devp->vfp); - vdin_set_canvas_id(devp, (devp->flags&VDIN_FLAG_RDMA_ENABLE), - (next_wr_vfe->vf.canvas0Addr&0xff)); + if (devp->afbce_mode == 0) + vdin_set_canvas_id(devp, (devp->flags&VDIN_FLAG_RDMA_ENABLE), + (next_wr_vfe->vf.canvas0Addr&0xff)); + else if (devp->afbce_mode == 1) + vdin_afbce_set_next_frame(devp, + (devp->flags&VDIN_FLAG_RDMA_ENABLE), next_wr_vfe); + if ((devp->prop.dest_cfmt == TVIN_NV12) || (devp->prop.dest_cfmt == TVIN_NV21)) vdin_set_chma_canvas_id(devp, @@ -1742,6 +1784,23 @@ static void vdin_dv_dwork(struct work_struct *work) cancel_delayed_work(&devp->dv.dv_dwork); } +/*ensure vlock mux swith avoid vlock vsync region*/ +static void vdin_vlock_dwork(struct work_struct *work) +{ + struct delayed_work *dwork = to_delayed_work(work); + struct vdin_dev_s *devp = + container_of(dwork, struct vdin_dev_s, vlock_dwork); + + if (!devp || !devp->frontend || !devp->curr_wr_vfe) { + pr_info("%s, dwork error !!!\n", __func__); + return; + } + vdin_vlock_input_sel(devp->curr_field_type, + devp->curr_wr_vfe->vf.source_type); + + cancel_delayed_work(&devp->vlock_dwork); +} + /*function:open device * 1.request irq to open device configure vdinx * 2.disable irq until vdin is configured completely @@ -2469,6 +2528,25 @@ static int vdin_drv_probe(struct platform_device *pdev) else vdevp->color_depth_mode = 0; + /*set afbce mode*/ + ret = of_property_read_u32(pdev->dev.of_node, + "afbce_bit_mode", &vdevp->afbce_mode); + if (ret) { + vdevp->afbce_mode = 0; + pr_info("no afbce mode found, use normal mode\n"); + } else { + if ((is_meson_tl1_cpu()) && (vdevp->index == 0)) { + /* just use afbce at vdin0 */ + pr_info("afbce mode = %d\n", vdevp->afbce_mode); + vdevp->afbce_info = devm_kzalloc(vdevp->dev, + sizeof(struct vdin_afbce_s), GFP_KERNEL); + if (!vdevp->afbce_info) + goto fail_kzalloc_vdev; + } else { + vdevp->afbce_mode = 0; + pr_info("get afbce from dts, but chip cannot support\n"); + } + } /*vdin urgent en*/ ret = of_property_read_u32(pdev->dev.of_node, "urgent_en", &urgent_en); @@ -2487,12 +2565,13 @@ static int vdin_drv_probe(struct platform_device *pdev) /* @todo vdin_addr_offset */ if (is_meson_gxbb_cpu() && vdevp->index) vdin_addr_offset[vdevp->index] = 0x70; - else if ((is_meson_g12a_cpu() || is_meson_g12b_cpu()) && vdevp->index) + else if ((is_meson_g12a_cpu() || is_meson_g12b_cpu() || + is_meson_tl1_cpu()) && vdevp->index) vdin_addr_offset[vdevp->index] = 0x100; vdevp->addr_offset = vdin_addr_offset[vdevp->index]; vdevp->flags = 0; /*canvas align number*/ - if (is_meson_g12a_cpu() || is_meson_g12b_cpu()) + if (is_meson_g12a_cpu() || is_meson_g12b_cpu() || is_meson_tl1_cpu()) vdevp->canvas_align = 64; else vdevp->canvas_align = 32; @@ -2594,6 +2673,7 @@ static int vdin_drv_probe(struct platform_device *pdev) vdevp->vdin_dev_ssize = sizeof(struct vdin_dev_s); vdevp->canvas_config_mode = canvas_config_mode; INIT_DELAYED_WORK(&vdevp->dv.dv_dwork, vdin_dv_dwork); + INIT_DELAYED_WORK(&vdevp->vlock_dwork, vdin_vlock_dwork); vdin_debugfs_init(vdevp);/*2018-07-18 add debugfs*/ pr_info("%s: driver initialized ok\n", __func__); @@ -2619,9 +2699,12 @@ fail_kzalloc_vdev: */ static int vdin_drv_remove(struct platform_device *pdev) { + int ret; + struct vdin_dev_s *vdevp; vdevp = platform_get_drvdata(pdev); + ret = cancel_delayed_work(&vdevp->vlock_dwork); #ifdef CONFIG_AML_RDMA rdma_unregister(vdevp->rdma_handle); #endif diff --git a/drivers/amlogic/media/vin/tvin/vdin/vdin_drv.h b/drivers/amlogic/media/vin/tvin/vdin/vdin_drv.h index 4438f8d34859..43e719ef8576 100644 --- a/drivers/amlogic/media/vin/tvin/vdin/vdin_drv.h +++ b/drivers/amlogic/media/vin/tvin/vdin/vdin_drv.h @@ -45,7 +45,7 @@ #include "vdin_vf.h" #include "vdin_regs.h" -#define VDIN_VER "Ref.2018/04/28" +#define VDIN_VER "Ref.2018/11/07a" /*the counter of vdin*/ #define VDIN_MAX_DEVS 2 @@ -161,6 +161,25 @@ struct vdin_dv_s { bool dv_config; bool dv_crc_check;/*0:fail;1:ok*/ }; + +struct vdin_afbce_s { + unsigned int head_size;/*all head size*/ + unsigned int table_size;/*all table size*/ + unsigned int frame_head_size;/*1 frame head size*/ + unsigned int frame_table_size;/*1 frame table size*/ + unsigned int frame_body_size;/*1 frame body size*/ + unsigned long head_paddr; + unsigned long table_paddr; + /*every frame head addr*/ + unsigned long fm_head_paddr[VDIN_CANVAS_MAX_CNT]; + /*every frame tab addr*/ + unsigned long fm_table_paddr[VDIN_CANVAS_MAX_CNT]; + /*every body head addr*/ + unsigned long fm_body_paddr[VDIN_CANVAS_MAX_CNT]; + //unsigned int cur_af;/*current afbce number*/ + //unsigned int last_af;/*last afbce number*/ +}; + struct vdin_dev_s { struct cdev cdev; struct device *dev; @@ -172,6 +191,8 @@ struct vdin_dev_s { struct tvin_sig_property_s prop; struct vframe_provider_s vprov; struct vdin_dv_s dv; + struct delayed_work vlock_dwork; + struct vdin_afbce_s *afbce_info; /* 0:from gpio A,1:from csi2 , 2:gpio B*/ enum bt_path_e bt_path; @@ -294,6 +315,12 @@ struct vdin_dev_s { */ unsigned int game_mode; unsigned int rdma_enable; + /* afbce_mode: (amlogic frame buff compression encoder) + * 0: normal mode, not use afbce + * 1: use afbce non-mmu mode: head/body addr set by code + * 2: use afbce mmu mode: head set by code, body addr assigning by hw + */ + unsigned int afbce_mode; unsigned int canvas_config_mode; bool prehsc_en; bool vshrk_en; diff --git a/drivers/amlogic/media/vin/tvin/vdin/vdin_regs.h b/drivers/amlogic/media/vin/tvin/vdin/vdin_regs.h index ac49237b5459..aaf417348077 100644 --- a/drivers/amlogic/media/vin/tvin/vdin/vdin_regs.h +++ b/drivers/amlogic/media/vin/tvin/vdin/vdin_regs.h @@ -33,6 +33,12 @@ #define VDIN0_REQ_EN_BIT 0 #define VDIN1_REQ_EN_BIT 1 #define VDIN_MISC_CTRL 0x2782 +#define VDIN0_OUT_AFBCE_BIT 21 +#define VDIN0_OUT_MIF_BIT 20 +#define VDIN0_MIF_ENABLE_BIT 19 +#define VDIN1_OUT_AFBCE_BIT 18 +#define VDIN1_OUT_MIF_BIT 17 +#define VDIN1_MIF_ENABLE_BIT 16 #define VDIN0_MIF_RST_BIT 3 #define VDIN1_MIF_RST_BIT 4 #define VDIN_MIF_RST_W 1 @@ -711,6 +717,7 @@ /*g12a new add end*/ +#define VDIN_WRARB_REQEN_SLV 0x12c1 /* #define VDIN_SCALE_COEF_IDX 0x1200 */ /* #define VDIN_SCALE_COEF 0x1201 */ diff --git a/drivers/amlogic/media/vin/tvin/vdin/vdin_vf.c b/drivers/amlogic/media/vin/tvin/vdin/vdin_vf.c index 6204a837c6ce..afd3446df7f0 100644 --- a/drivers/amlogic/media/vin/tvin/vdin/vdin_vf.c +++ b/drivers/amlogic/media/vin/tvin/vdin/vdin_vf.c @@ -387,6 +387,7 @@ int vf_pool_init(struct vf_pool *p, int size) log_state = false; break; } + master->af_num = i; master->status = VF_STATUS_WL; master->flag |= VF_FLAG_NORMAL_FRAME; master->flag &= (~VF_FLAG_FREEZED_FRAME); diff --git a/drivers/amlogic/media/vin/tvin/vdin/vdin_vf.h b/drivers/amlogic/media/vin/tvin/vdin/vdin_vf.h index 75a1a7738b4d..02b3756ee7fa 100644 --- a/drivers/amlogic/media/vin/tvin/vdin/vdin_vf.h +++ b/drivers/amlogic/media/vin/tvin/vdin/vdin_vf.h @@ -106,6 +106,7 @@ struct vf_entry { enum vf_status_e status; struct list_head list; unsigned int flag; + unsigned char af_num;/*afbce num*/ }; struct vf_pool { diff --git a/drivers/amlogic/media/vin/tvin/viu/viuin.c b/drivers/amlogic/media/vin/tvin/viu/viuin.c index 8a7922b49b73..3fe16a66aaae 100644 --- a/drivers/amlogic/media/vin/tvin/viu/viuin.c +++ b/drivers/amlogic/media/vin/tvin/viu/viuin.c @@ -178,7 +178,8 @@ static int viuin_open(struct tvin_frontend_s *fe, enum tvin_port_e port) /*open the venc to vdin path*/ switch (rd_bits_viu(VPU_VIU_VENC_MUX_CTRL, 0, 2)) { case 0: - if (is_meson_g12a_cpu() || is_meson_g12b_cpu()) + if (is_meson_g12a_cpu() || is_meson_g12b_cpu() + || is_meson_tl1_cpu()) viu_mux = 0x4; else viu_mux = 0x8; @@ -212,7 +213,7 @@ static int viuin_open(struct tvin_frontend_s *fe, enum tvin_port_e port) wr_viu(VPU_VIU2VDIN_HDN_CTRL, 0x40f00); } else wr_bits_viu(VPU_VIU2VDIN_HDN_CTRL, devp->parm.h_active, 0, 14); - if (is_meson_g12a_cpu() || is_meson_g12b_cpu()) { + if (is_meson_g12a_cpu() || is_meson_g12b_cpu() || is_meson_tl1_cpu()) { if (((port >= TVIN_PORT_VIU1_WB0_VD1) && (port <= TVIN_PORT_VIU1_WB0_POST_BLEND)) || ((port >= TVIN_PORT_VIU2_WB0_VD1) && @@ -307,7 +308,8 @@ static void viuin_close(struct tvin_frontend_s *fe) if (open_cnt) open_cnt--; if (open_cnt == 0) { - if (is_meson_g12a_cpu() || is_meson_g12b_cpu()) { + if (is_meson_g12a_cpu() || is_meson_g12b_cpu() + || is_meson_tl1_cpu()) { wr_viu(VPU_VIU_VDIN_IF_MUX_CTRL, 0); wr_viu(VPP_WRBAK_CTRL, 0); diff --git a/drivers/amlogic/media/vout/backlight/aml_bl.c b/drivers/amlogic/media/vout/backlight/aml_bl.c index fe21e9ce8785..a7286d475260 100644 --- a/drivers/amlogic/media/vout/backlight/aml_bl.c +++ b/drivers/amlogic/media/vout/backlight/aml_bl.c @@ -3183,12 +3183,6 @@ static int aml_bl_resume(struct platform_device *pdev) #endif #ifdef CONFIG_OF -static struct bl_data_s bl_data_gxtvbb = { - .chip_type = BL_CHIP_GXTVBB, - .chip_name = "gxtvbb", - .pwm_reg = pwm_reg_txl, -}; - static struct bl_data_s bl_data_gxl = { .chip_type = BL_CHIP_GXL, .chip_name = "gxl", @@ -3231,11 +3225,13 @@ static struct bl_data_s bl_data_g12b = { .pwm_reg = pwm_reg_txlx, }; +static struct bl_data_s bl_data_tl1 = { + .chip_type = BL_CHIP_TL1, + .chip_name = "tl1", + .pwm_reg = pwm_reg_txlx, +}; + static const struct of_device_id bl_dt_match_table[] = { - { - .compatible = "amlogic, backlight-gxtvbb", - .data = &bl_data_gxtvbb, - }, { .compatible = "amlogic, backlight-gxl", .data = &bl_data_gxl, @@ -3264,6 +3260,10 @@ static const struct of_device_id bl_dt_match_table[] = { .compatible = "amlogic, backlight-g12b", .data = &bl_data_g12b, }, + { + .compatible = "amlogic, backlight-tl1", + .data = &bl_data_tl1, + }, {}, }; #endif diff --git a/drivers/amlogic/media/vout/backlight/aml_ldim/Makefile b/drivers/amlogic/media/vout/backlight/aml_ldim/Makefile index 5da46625dd0d..bc2132eb8332 100644 --- a/drivers/amlogic/media/vout/backlight/aml_ldim/Makefile +++ b/drivers/amlogic/media/vout/backlight/aml_ldim/Makefile @@ -1,7 +1,8 @@ # # Makefile for LDIM. # -obj-$(CONFIG_AMLOGIC_LOCAL_DIMMING) = aml_ldim.o ldim_dev_drv.o ob3350_bl.o global_bl.o iw7027_bl.o +obj-$(CONFIG_AMLOGIC_LOCAL_DIMMING) = aml_ldim.o ldim_dev_drv.o ldim_spi.o \ + ob3350_bl.o global_bl.o iw7027_bl.o aml_ldim-objs := ldim_drv.o ldim_func.o diff --git a/drivers/amlogic/media/vout/backlight/aml_ldim/global_bl.c b/drivers/amlogic/media/vout/backlight/aml_ldim/global_bl.c index 9009dee83116..d2dcd99745b5 100644 --- a/drivers/amlogic/media/vout/backlight/aml_ldim/global_bl.c +++ b/drivers/amlogic/media/vout/backlight/aml_ldim/global_bl.c @@ -148,10 +148,8 @@ static struct class_attribute global_class_attrs[] = { __ATTR_NULL }; -static int global_ldim_driver_update(void) +static int global_ldim_driver_update(struct aml_ldim_driver_s *ldim_drv) { - struct aml_ldim_driver_s *ldim_drv = aml_ldim_get_driver(); - ldim_drv->device_power_on = global_power_on; ldim_drv->device_power_off = global_power_off; ldim_drv->device_bri_update = global_smr; @@ -159,7 +157,7 @@ static int global_ldim_driver_update(void) return 0; } -int ldim_dev_global_probe(void) +int ldim_dev_global_probe(struct aml_ldim_driver_s *ldim_drv) { int ret; @@ -170,7 +168,7 @@ int ldim_dev_global_probe(void) return -1; } - global_ldim_driver_update(); + global_ldim_driver_update(ldim_drv); bl_global->cls.name = kzalloc(10, GFP_KERNEL); if (bl_global->cls.name == NULL) { @@ -189,7 +187,7 @@ int ldim_dev_global_probe(void) return ret; } -int ldim_dev_global_remove(void) +int ldim_dev_global_remove(struct aml_ldim_driver_s *ldim_drv) { kfree(bl_global); bl_global = NULL; diff --git a/drivers/amlogic/media/vout/backlight/aml_ldim/iw7027_bl.c b/drivers/amlogic/media/vout/backlight/aml_ldim/iw7027_bl.c index 84cd7a77fed7..187b7233316c 100644 --- a/drivers/amlogic/media/vout/backlight/aml_ldim/iw7027_bl.c +++ b/drivers/amlogic/media/vout/backlight/aml_ldim/iw7027_bl.c @@ -49,7 +49,6 @@ #define IW7027_POWER_ON 0 #define IW7027_POWER_RESET 1 static int iw7027_on_flag; -static int iw7027_spi_op_flag; static DEFINE_MUTEX(iw7027_spi_mutex); @@ -68,82 +67,49 @@ struct iw7027_s *bl_iw7027; static unsigned short *test_brightness; static unsigned char *val_brightness; -static int iw7027_wreg(struct spi_device *spi, u8 addr, u8 val) +static int iw7027_wreg(struct spi_device *spi, unsigned char addr, + unsigned char val) { - u8 tbuf[3]; + unsigned char tbuf[3]; int ret; - mutex_lock(&iw7027_spi_mutex); - - if (bl_iw7027->cs_hold_delay) - udelay(bl_iw7027->cs_hold_delay); - dirspi_start(spi); - if (bl_iw7027->cs_clk_delay) - udelay(bl_iw7027->cs_clk_delay); tbuf[0] = NORMAL_MSG | SINGLE_DATA | IW7027_DEV_ADDR; tbuf[1] = addr & 0x7f; tbuf[2] = val; - ret = dirspi_write(spi, tbuf, 3); - if (bl_iw7027->cs_clk_delay) - udelay(bl_iw7027->cs_clk_delay); - dirspi_stop(spi); - mutex_unlock(&iw7027_spi_mutex); + ret = ldim_spi_write(spi, tbuf, 3); return ret; } -static int iw7027_rreg(struct spi_device *spi, u8 addr, u8 *val) +static int iw7027_rreg(struct spi_device *spi, unsigned char addr, + unsigned char *val) { - u8 tbuf[3], temp; + unsigned char tbuf[3], temp; int ret; /* page select */ temp = (addr >= 0x80) ? 0x80 : 0x0; iw7027_wreg(spi, 0x78, temp); - mutex_lock(&iw7027_spi_mutex); - - if (bl_iw7027->cs_hold_delay) - udelay(bl_iw7027->cs_hold_delay); - dirspi_start(spi); - if (bl_iw7027->cs_clk_delay) - udelay(bl_iw7027->cs_clk_delay); tbuf[0] = NORMAL_MSG | SINGLE_DATA | IW7027_DEV_ADDR; tbuf[1] = addr | 0x80; tbuf[2] = 0; - ret = dirspi_write(spi, tbuf, 3); - ret = dirspi_read(spi, val, 1); - if (bl_iw7027->cs_clk_delay) - udelay(bl_iw7027->cs_clk_delay); - dirspi_stop(spi); - - mutex_unlock(&iw7027_spi_mutex); + ret = ldim_spi_read(spi, tbuf, 3, val, 1); return ret; } -static int iw7027_wregs(struct spi_device *spi, u8 addr, u8 *val, int len) +static int iw7027_wregs(struct spi_device *spi, unsigned char addr, + unsigned char *val, int len) { - u8 tbuf[30]; + unsigned char tbuf[30]; int ret; - mutex_lock(&iw7027_spi_mutex); - - if (bl_iw7027->cs_hold_delay) - udelay(bl_iw7027->cs_hold_delay); - dirspi_start(spi); - if (bl_iw7027->cs_clk_delay) - udelay(bl_iw7027->cs_clk_delay); tbuf[0] = NORMAL_MSG | BLOCK_DATA | IW7027_DEV_ADDR; tbuf[1] = len; tbuf[2] = addr & 0x7f; memcpy(&tbuf[3], val, len); - ret = dirspi_write(spi, tbuf, len+3); - if (bl_iw7027->cs_clk_delay) - udelay(bl_iw7027->cs_clk_delay); - dirspi_stop(spi); - - mutex_unlock(&iw7027_spi_mutex); + ret = ldim_spi_write(spi, tbuf, (len+3)); return ret; } @@ -253,42 +219,25 @@ static int ldim_power_cmd_fixed_size(void) return ret; } -static int iw7027_power_on_init(int flag) +static int iw7027_power_on_init(void) { - unsigned char cmd_size; - int i, ret = 0; + int ret = 0; - LDIMPR("%s: spi_op_flag=%d\n", __func__, iw7027_spi_op_flag); - - if (flag == IW7027_POWER_RESET) - goto iw7027_power_reset_p; - i = 1000; - while ((iw7027_spi_op_flag) && (i > 0)) { - i--; - udelay(10); - } - if (iw7027_spi_op_flag == 1) { - LDIMERR("%s: wait spi idle state failed\n", __func__); - return 0; - } - - iw7027_spi_op_flag = 1; - -iw7027_power_reset_p: - cmd_size = bl_iw7027->cmd_size; - if (cmd_size < 1) { - LDIMERR("%s: cmd_size %d is invalid\n", __func__, cmd_size); + if (bl_iw7027->cmd_size < 1) { + LDIMERR("%s: cmd_size %d is invalid\n", + __func__, bl_iw7027->cmd_size); return -1; } - if (cmd_size == LCD_EXT_CMD_SIZE_DYNAMIC) + if (bl_iw7027->init_data == NULL) { + LDIMERR("%s: init_data is null\n", __func__); + return -1; + } + + if (bl_iw7027->cmd_size == LCD_EXT_CMD_SIZE_DYNAMIC) ret = ldim_power_cmd_dynamic_size(); else ret = ldim_power_cmd_fixed_size(); - if (flag == IW7027_POWER_RESET) - return ret; - - iw7027_spi_op_flag = 0; return ret; } @@ -298,6 +247,8 @@ static int iw7027_hw_init_on(void) unsigned char reg_chk, reg_duty_chk; struct aml_ldim_driver_s *ldim_drv = aml_ldim_get_driver(); + mutex_lock(&iw7027_spi_mutex); + /* step 1: system power_on */ ldim_gpio_set(ldim_drv->ldev_conf->en_gpio, ldim_drv->ldev_conf->en_gpio_on); @@ -319,7 +270,7 @@ static int iw7027_hw_init_on(void) } /* step 4: configure initial registers */ - iw7027_power_on_init(IW7027_POWER_ON); + iw7027_power_on_init(); /* step 5: supply stable vsync */ ldim_set_duty_pwm(&(ldim_drv->ldev_conf->pwm_config)); @@ -344,7 +295,7 @@ static int iw7027_hw_init_on(void) } LDIMPR("%s: calibration done: [%d] = %x\n", __func__, i, reg_duty_chk); - iw7027_spi_op_flag = 0; + mutex_unlock(&iw7027_spi_mutex); return 0; } @@ -352,20 +303,16 @@ static int iw7027_hw_init_on(void) static int iw7027_hw_init_off(void) { struct aml_ldim_driver_s *ldim_drv = aml_ldim_get_driver(); - int i = 1000; - while ((iw7027_spi_op_flag) && (i > 0)) { - i--; - udelay(10); - } - if (iw7027_spi_op_flag == 1) - LDIMERR("%s: wait spi idle state failed\n", __func__); + mutex_lock(&iw7027_spi_mutex); ldim_gpio_set(ldim_drv->ldev_conf->en_gpio, ldim_drv->ldev_conf->en_gpio_off); ldim_drv->pinmux_ctrl(0); ldim_pwm_off(&(ldim_drv->ldev_conf->pwm_config)); + mutex_unlock(&iw7027_spi_mutex); + return 0; } @@ -378,6 +325,8 @@ static int iw7027_spi_dump_low(char *buf) if (buf == NULL) return len; + mutex_lock(&iw7027_spi_mutex); + len += sprintf(buf, "iw7027 reg low:\n"); for (i = 0; i <= 0x7f; i++) { iw7027_rreg(bl_iw7027->spi, i, &val); @@ -385,6 +334,8 @@ static int iw7027_spi_dump_low(char *buf) } len += sprintf(buf+len, "\n"); + mutex_unlock(&iw7027_spi_mutex); + return len; } @@ -397,6 +348,8 @@ static int iw7027_spi_dump_high(char *buf) if (buf == NULL) return len; + mutex_lock(&iw7027_spi_mutex); + len += sprintf(buf, "iw7027 reg high:\n"); for (i = 0x80; i <= 0xff; i++) { iw7027_rreg(bl_iw7027->spi, i, &val); @@ -404,6 +357,8 @@ static int iw7027_spi_dump_high(char *buf) } len += sprintf(buf+len, "\n"); + mutex_unlock(&iw7027_spi_mutex); + return len; } @@ -417,6 +372,8 @@ static int iw7027_spi_dump_dim(char *buf) if (buf == NULL) return len; + mutex_lock(&iw7027_spi_mutex); + len += sprintf(buf, "iw7027 reg dimming:\n"); num = ldim_drv->ldev_conf->bl_regnum; for (i = 0x40; i <= (0x40 + (num * 2)); i++) { @@ -425,6 +382,8 @@ static int iw7027_spi_dump_dim(char *buf) } len += sprintf(buf+len, "\n"); + mutex_unlock(&iw7027_spi_mutex); + return len; } @@ -465,15 +424,8 @@ static int iw7027_smr(unsigned short *buf, unsigned char len) LDIMERR("%s: val_brightness is null\n", __func__); return -1; } - if (iw7027_spi_op_flag) { - if (smr_cnt == 0) { - LDIMPR("%s: spi_op_flag=%d\n", - __func__, iw7027_spi_op_flag); - } - return 0; - } - iw7027_spi_op_flag = 1; + mutex_lock(&iw7027_spi_mutex); mapping = &ldim_drv->ldev_conf->bl_mapping[0]; dim_max = ldim_drv->ldev_conf->dim_max; @@ -506,7 +458,7 @@ static int iw7027_smr(unsigned short *buf, unsigned char len) iw7027_wregs(bl_iw7027->spi, 0x40, val_brightness, (num * 2)); - iw7027_spi_op_flag = 0; + mutex_unlock(&iw7027_spi_mutex); return 0; } @@ -563,7 +515,6 @@ static ssize_t iw7027_show(struct class *class, "en_off = %d\n" "cs_hold_delay = %d\n" "cs_clk_delay = %d\n" - "spi_op_flag = %d\n" "dim_max = 0x%03x\n" "dim_min = 0x%03x\n", ldim_drv->dev_index, iw7027_on_flag, @@ -571,48 +522,14 @@ static ssize_t iw7027_show(struct class *class, ldim_drv->ldev_conf->en_gpio_off, ldim_drv->ldev_conf->cs_hold_delay, ldim_drv->ldev_conf->cs_clk_delay, - iw7027_spi_op_flag, ldim_drv->ldev_conf->dim_max, ldim_drv->ldev_conf->dim_min); } else if (!strcmp(attr->attr.name, "dump_low")) { - i = 1000; - while ((iw7027_spi_op_flag) && (i > 0)) { - i--; - udelay(10); - } - if (iw7027_spi_op_flag == 0) { - iw7027_spi_op_flag = 1; - ret = iw7027_spi_dump_low(buf); - iw7027_spi_op_flag = 0; - } else { - LDIMERR("%s: wait spi idle state failed\n", __func__); - } + ret = iw7027_spi_dump_low(buf); } else if (!strcmp(attr->attr.name, "dump_high")) { - i = 1000; - while ((iw7027_spi_op_flag) && (i > 0)) { - i--; - udelay(10); - } - if (iw7027_spi_op_flag == 0) { - iw7027_spi_op_flag = 1; - ret = iw7027_spi_dump_high(buf); - iw7027_spi_op_flag = 0; - } else { - LDIMERR("%s: wait spi idle state failed\n", __func__); - } + ret = iw7027_spi_dump_high(buf); } else if (!strcmp(attr->attr.name, "dump_dim")) { - i = 1000; - while ((iw7027_spi_op_flag) && (i > 0)) { - i--; - udelay(10); - } - if (iw7027_spi_op_flag == 0) { - iw7027_spi_op_flag = 1; - ret = iw7027_spi_dump_dim(buf); - iw7027_spi_op_flag = 0; - } else { - LDIMERR("%s: wait spi idle state failed\n", __func__); - } + ret = iw7027_spi_dump_dim(buf); } return ret; @@ -646,19 +563,23 @@ static ssize_t iw7027_store(struct class *class, if (buf[0] == 'w') { i = sscanf(buf, "w %x %x", &val, &val2); if (i == 2) { + mutex_lock(&iw7027_spi_mutex); reg_addr = (unsigned char)val; reg_val = (unsigned char)val2; iw7027_wreg(bl->spi, reg_addr, reg_val); + mutex_unlock(&iw7027_spi_mutex); } else { LDIMERR("%s: invalid args\n", __func__); } } else if (buf[0] == 'r') { i = sscanf(buf, "r %x", &val); if (i == 1) { + mutex_lock(&iw7027_spi_mutex); reg_addr = (unsigned char)val; iw7027_rreg(bl->spi, reg_addr, ®_val); pr_info("reg 0x%02x = 0x%02x\n", reg_addr, reg_val); + mutex_unlock(&iw7027_spi_mutex); } else { LDIMERR("%s: invalid args\n", __func__); } @@ -697,57 +618,24 @@ static struct class_attribute iw7027_class_attrs[] = { __ATTR_NULL }; -static int iw7027_ldim_driver_update(void) +static int iw7027_ldim_driver_update(struct aml_ldim_driver_s *ldim_drv) { - struct aml_ldim_driver_s *ldim_drv = aml_ldim_get_driver(); - ldim_drv->device_power_on = iw7027_power_on; ldim_drv->device_power_off = iw7027_power_off; ldim_drv->device_bri_update = iw7027_smr; return 0; } -static int ldim_spi_dev_probe(struct spi_device *spi) +int ldim_dev_iw7027_probe(struct aml_ldim_driver_s *ldim_drv) { - struct aml_ldim_driver_s *ldim_drv = aml_ldim_get_driver(); - int ret; - - ldim_drv->spi = spi; - - dev_set_drvdata(&spi->dev, ldim_drv->ldev_conf); - spi->bits_per_word = 8; - ret = spi_setup(spi); - if (ret) - LDIMERR("spi setup failed\n"); - - LDIMPR("%s ok\n", __func__); - return ret; -} - -static int ldim_spi_dev_remove(struct spi_device *spi) -{ - struct aml_ldim_driver_s *ldim_drv = aml_ldim_get_driver(); - - ldim_drv->spi = NULL; - return 0; -} - -static struct spi_driver ldim_spi_dev_driver = { - .probe = ldim_spi_dev_probe, - .remove = ldim_spi_dev_remove, - .driver = { - .name = "ldim_dev", - .owner = THIS_MODULE, - }, -}; - -int ldim_dev_iw7027_probe(void) -{ - struct aml_ldim_driver_s *ldim_drv = aml_ldim_get_driver(); int ret, i; + if (ldim_drv->spi_dev == NULL) { + LDIMERR("%s: spi_dev is null\n", __func__); + return -1; + } + iw7027_on_flag = 0; - iw7027_spi_op_flag = 0; bl_iw7027 = kzalloc(sizeof(struct iw7027_s), GFP_KERNEL); if (bl_iw7027 == NULL) { @@ -755,16 +643,8 @@ int ldim_dev_iw7027_probe(void) return -1; } - spi_register_board_info(ldim_drv->spi_dev, 1); - ret = spi_register_driver(&ldim_spi_dev_driver); - if (ret) { - LDIMERR("register ldim_dev spi driver failed\n"); - kfree(bl_iw7027); - return -1; - } - bl_iw7027->test_mode = 0; - bl_iw7027->spi = ldim_drv->spi; + bl_iw7027->spi = ldim_drv->spi_dev; bl_iw7027->cs_hold_delay = ldim_drv->ldev_conf->cs_hold_delay; bl_iw7027->cs_clk_delay = ldim_drv->ldev_conf->cs_clk_delay; bl_iw7027->cmd_size = ldim_drv->ldev_conf->cmd_size; @@ -787,7 +667,7 @@ int ldim_dev_iw7027_probe(void) test_brightness[i] = 0xfff; } - iw7027_ldim_driver_update(); + iw7027_ldim_driver_update(ldim_drv); bl_iw7027->cls.name = kzalloc(10, GFP_KERNEL); sprintf((char *)bl_iw7027->cls.name, "iw7027"); @@ -802,14 +682,13 @@ int ldim_dev_iw7027_probe(void) return ret; } -int ldim_dev_iw7027_remove(void) +int ldim_dev_iw7027_remove(struct aml_ldim_driver_s *ldim_drv) { kfree(val_brightness); val_brightness = NULL; kfree(test_brightness); test_brightness = NULL; - spi_unregister_driver(&ldim_spi_dev_driver); kfree(bl_iw7027); bl_iw7027 = NULL; diff --git a/drivers/amlogic/media/vout/backlight/aml_ldim/ldim_dev_drv.c b/drivers/amlogic/media/vout/backlight/aml_ldim/ldim_dev_drv.c index 0f8db690d95b..b2c02250cf71 100644 --- a/drivers/amlogic/media/vout/backlight/aml_ldim/ldim_dev_drv.c +++ b/drivers/amlogic/media/vout/backlight/aml_ldim/ldim_dev_drv.c @@ -46,7 +46,7 @@ struct bl_gpio_s ldim_gpio[BL_GPIO_NUM_MAX] = { {.probe_flag = 0, .register_flag = 0,}, }; -static struct spi_board_info ldim_spi_dev = { +static struct spi_board_info ldim_spi_info = { .modalias = "ldim_dev", .mode = SPI_MODE_0, .max_speed_hz = 1000000, /* 1MHz */ @@ -57,6 +57,7 @@ static struct spi_board_info ldim_spi_dev = { static unsigned char *table_init_on_dft; static unsigned char *table_init_off_dft; +static int ldim_dev_probe_flag; struct ldim_dev_config_s ldim_dev_config = { .type = LDIM_DEV_TYPE_NORMAL, @@ -254,7 +255,7 @@ void ldim_set_duty_pwm(struct bl_pwm_config_s *bl_pwm) temp = (((temp * bl_pwm->pwm_duty) + 50) / 100); bl_pwm->pwm_level = (unsigned int)temp; - if (ldim_debug_print) { + if (ldim_debug_print == 2) { LDIMPR( "pwm port %d: duty=%d%%, pwm_max=%d, pwm_min=%d, pwm_level=%d\n", bl_pwm->pwm_port, bl_pwm->pwm_duty, @@ -310,7 +311,7 @@ static int ldim_pwm_pinmux_ctrl(int status) if (IS_ERR(ldim_drv->pin)) { LDIMERR("set pinmux %s error\n", ldim_pinmux_str[index]); } else { - LDIMPR("set pinmux %s: %p\n", + LDIMPR("set pinmux %s: 0x%p\n", ldim_pinmux_str[index], ldim_drv->pin); } ldim_drv->pinmux_flag = index; @@ -347,7 +348,7 @@ static void ldim_dev_init_table_dynamic_size_print( if (flag) { pr_info("power on:\n"); table = econf->init_on; - max_len = econf->init_off_cnt; + max_len = econf->init_on_cnt; } else { pr_info("power off:\n"); table = econf->init_off; @@ -468,148 +469,148 @@ static void ldim_dev_config_print(void) "dev_index = %d\n", ldim_drv->valid_flag, ldim_drv->dev_index); - if (ldim_drv->ldev_conf) { - bl_pwm = &ldim_drv->ldev_conf->pwm_config; - pr_info("dev_name = %s\n" - "type = %d\n" - "en_gpio = %d\n" - "en_gpio_on = %d\n" - "en_gpio_off = %d\n" - "dim_min = 0x%03x\n" - "dim_max = 0x%03x\n", - ldim_drv->ldev_conf->name, - ldim_drv->ldev_conf->type, - ldim_drv->ldev_conf->en_gpio, - ldim_drv->ldev_conf->en_gpio_on, - ldim_drv->ldev_conf->en_gpio_off, - ldim_drv->ldev_conf->dim_min, - ldim_drv->ldev_conf->dim_max); - pr_info("region_num = %d\n", - ldim_drv->ldev_conf->bl_regnum); - n = ldim_drv->ldev_conf->bl_regnum; - len = (n * 4) + 50; - str = kcalloc(len, sizeof(char), GFP_KERNEL); - if (str == NULL) { - pr_info("%s: buf malloc error\n", __func__); - } else { - len = sprintf(str, "region_mapping:\n "); - for (i = 0; i < n; i++) { - len += sprintf(str+len, "%d,", - ldim_drv->ldev_conf->bl_mapping[i]); - } - pr_info("%s\n\n", str); - kfree(str); - } + if (ldim_drv->ldev_conf == NULL) { + LDIMERR("%s: device config is null\n", __func__); + return; + } - switch (ldim_drv->ldev_conf->type) { - case LDIM_DEV_TYPE_SPI: - pr_info("spi_modalias = %s\n" - "spi_mode = %d\n" - "spi_max_speed_hz = %d\n" - "spi_bus_num = %d\n" - "spi_chip_select = %d\n" - "cs_hold_delay = %d\n" - "cs_clk_delay = %d\n" - "lamp_err_gpio = %d\n" - "fault_check = %d\n" - "write_check = %d\n\n", - ldim_drv->spi_dev->modalias, - ldim_drv->spi_dev->mode, - ldim_drv->spi_dev->max_speed_hz, - ldim_drv->spi_dev->bus_num, - ldim_drv->spi_dev->chip_select, - ldim_drv->ldev_conf->cs_hold_delay, - ldim_drv->ldev_conf->cs_clk_delay, - ldim_drv->ldev_conf->lamp_err_gpio, - ldim_drv->ldev_conf->fault_check, - ldim_drv->ldev_conf->write_check); + bl_pwm = &ldim_drv->ldev_conf->pwm_config; + pr_info("dev_name = %s\n" + "type = %d\n" + "en_gpio = %d\n" + "en_gpio_on = %d\n" + "en_gpio_off = %d\n" + "dim_min = 0x%03x\n" + "dim_max = 0x%03x\n" + "region_num = %d\n", + ldim_drv->ldev_conf->name, + ldim_drv->ldev_conf->type, + ldim_drv->ldev_conf->en_gpio, + ldim_drv->ldev_conf->en_gpio_on, + ldim_drv->ldev_conf->en_gpio_off, + ldim_drv->ldev_conf->dim_min, + ldim_drv->ldev_conf->dim_max, + ldim_drv->ldev_conf->bl_regnum); + n = ldim_drv->ldev_conf->bl_regnum; + len = (n * 4) + 50; + str = kcalloc(len, sizeof(char), GFP_KERNEL); + if (str == NULL) { + pr_info("%s: buf malloc error\n", __func__); + } else { + len = sprintf(str, "region_mapping:\n "); + for (i = 0; i < n; i++) { + len += sprintf(str+len, "%d,", + ldim_drv->ldev_conf->bl_mapping[i]); + } + pr_info("%s\n\n", str); + kfree(str); + } + + switch (ldim_drv->ldev_conf->type) { + case LDIM_DEV_TYPE_SPI: + pr_info("spi_pointer = 0x%p\n" + "spi_modalias = %s\n" + "spi_mode = %d\n" + "spi_max_speed_hz = %d\n" + "spi_bus_num = %d\n" + "spi_chip_select = %d\n" + "cs_hold_delay = %d\n" + "cs_clk_delay = %d\n" + "lamp_err_gpio = %d\n" + "fault_check = %d\n" + "write_check = %d\n\n", + ldim_drv->spi_dev, + ldim_drv->spi_info->modalias, + ldim_drv->spi_info->mode, + ldim_drv->spi_info->max_speed_hz, + ldim_drv->spi_info->bus_num, + ldim_drv->spi_info->chip_select, + ldim_drv->ldev_conf->cs_hold_delay, + ldim_drv->ldev_conf->cs_clk_delay, + ldim_drv->ldev_conf->lamp_err_gpio, + ldim_drv->ldev_conf->fault_check, + ldim_drv->ldev_conf->write_check); + break; + case LDIM_DEV_TYPE_I2C: + break; + case LDIM_DEV_TYPE_NORMAL: + default: + break; + } + if (bl_pwm->pwm_port < BL_PWM_MAX) { + pr_info("pwm_port: %d\n" + "pwm_pol: %d\n" + "pwm_freq: %d\n" + "pwm_cnt: %d\n" + "pwm_level: %d\n" + "pwm_duty: %d%%\n", + bl_pwm->pwm_port, bl_pwm->pwm_method, + bl_pwm->pwm_freq, bl_pwm->pwm_cnt, + bl_pwm->pwm_level, bl_pwm->pwm_duty); + switch (bl_pwm->pwm_port) { + case BL_PWM_A: + case BL_PWM_B: + case BL_PWM_C: + case BL_PWM_D: + case BL_PWM_E: + case BL_PWM_F: + if (IS_ERR_OR_NULL(bl_pwm->pwm_data.pwm)) { + pr_info("pwm invalid\n"); + break; + } + pr_info("pwm_pointer: %p\n", + bl_pwm->pwm_data.pwm); + pwm_get_state(bl_pwm->pwm_data.pwm, &pstate); + pr_info("pwm state:\n" + " period: %d\n" + " duty_cycle: %d\n" + " polarity: %d\n" + " enabled: %d\n", + pstate.period, pstate.duty_cycle, + pstate.polarity, pstate.enabled); + value = bl_cbus_read( + bl_drv->data->pwm_reg[bl_pwm->pwm_port]); + pr_info("pwm_reg: 0x%08x\n", value); break; - case LDIM_DEV_TYPE_I2C: - break; - case LDIM_DEV_TYPE_NORMAL: + case BL_PWM_VS: + pr_info("pwm_reg0: 0x%08x\n" + "pwm_reg1: 0x%08x\n" + "pwm_reg2: 0x%08x\n" + "pwm_reg3: 0x%08x\n", + bl_vcbus_read(VPU_VPU_PWM_V0), + bl_vcbus_read(VPU_VPU_PWM_V1), + bl_vcbus_read(VPU_VPU_PWM_V2), + bl_vcbus_read(VPU_VPU_PWM_V3)); break; default: break; } - if (bl_pwm->pwm_port < BL_PWM_MAX) { - pr_info("pwm_port: %d\n" - "pwm_pol: %d\n" - "pwm_freq: %d\n" - "pwm_cnt: %d\n" - "pwm_level: %d\n" - "pwm_duty: %d%%\n", - bl_pwm->pwm_port, bl_pwm->pwm_method, - bl_pwm->pwm_freq, bl_pwm->pwm_cnt, - bl_pwm->pwm_level, bl_pwm->pwm_duty); - switch (bl_pwm->pwm_port) { - case BL_PWM_A: - case BL_PWM_B: - case BL_PWM_C: - case BL_PWM_D: - case BL_PWM_E: - case BL_PWM_F: - if (IS_ERR_OR_NULL(bl_pwm->pwm_data.pwm)) { - pr_info("pwm invalid\n"); - break; - } - pr_info("pwm_pointer: %p\n", - bl_pwm->pwm_data.pwm); - pwm_get_state(bl_pwm->pwm_data.pwm, &pstate); - pr_info("pwm state:\n" - " period: %d\n" - " duty_cycle: %d\n" - " polarity: %d\n" - " enabled: %d\n", - pstate.period, pstate.duty_cycle, - pstate.polarity, pstate.enabled); - value = bl_cbus_read(bl_drv->data->pwm_reg[ - bl_pwm->pwm_port]); - pr_info("pwm_reg: 0x%08x\n", - value); - break; - case BL_PWM_VS: - pr_info("pwm_reg0: 0x%08x\n" - "pwm_reg1: 0x%08x\n" - "pwm_reg2: 0x%08x\n" - "pwm_reg3: 0x%08x\n", - bl_vcbus_read(VPU_VPU_PWM_V0), - bl_vcbus_read(VPU_VPU_PWM_V1), - bl_vcbus_read(VPU_VPU_PWM_V2), - bl_vcbus_read(VPU_VPU_PWM_V3)); - break; - default: - break; - } - } - pr_info("pinmux_flag: %d\n" - "pinmux_pointer: 0x%p\n\n", - ldim_drv->pinmux_flag, - ldim_drv->pin); + } + pr_info("pinmux_flag: %d\n" + "pinmux_pointer: 0x%p\n\n", + ldim_drv->pinmux_flag, + ldim_drv->pin); - if (ldim_drv->ldev_conf->cmd_size > 0) { - pr_info("table_loaded: %d\n" - "cmd_size: %d\n" - "init_on_cnt: %d\n" - "init_off_cnt: %d\n", - ldim_drv->ldev_conf->init_loaded, - ldim_drv->ldev_conf->cmd_size, - ldim_drv->ldev_conf->init_on_cnt, - ldim_drv->ldev_conf->init_off_cnt); - if (ldim_drv->ldev_conf->cmd_size == - LCD_EXT_CMD_SIZE_DYNAMIC) { - ldim_dev_init_table_dynamic_size_print( - ldim_drv->ldev_conf, 1); - ldim_dev_init_table_dynamic_size_print( - ldim_drv->ldev_conf, 0); - } else { - ldim_dev_init_table_fixed_size_print( - ldim_drv->ldev_conf, 1); - ldim_dev_init_table_fixed_size_print( - ldim_drv->ldev_conf, 0); - } + if (ldim_drv->ldev_conf->cmd_size > 0) { + pr_info("table_loaded: %d\n" + "cmd_size: %d\n" + "init_on_cnt: %d\n" + "init_off_cnt: %d\n", + ldim_drv->ldev_conf->init_loaded, + ldim_drv->ldev_conf->cmd_size, + ldim_drv->ldev_conf->init_on_cnt, + ldim_drv->ldev_conf->init_off_cnt); + if (ldim_drv->ldev_conf->cmd_size == LCD_EXT_CMD_SIZE_DYNAMIC) { + ldim_dev_init_table_dynamic_size_print( + ldim_drv->ldev_conf, 1); + ldim_dev_init_table_dynamic_size_print( + ldim_drv->ldev_conf, 0); + } else { + ldim_dev_init_table_fixed_size_print( + ldim_drv->ldev_conf, 1); + ldim_dev_init_table_fixed_size_print( + ldim_drv->ldev_conf, 0); } - } else { - pr_info("device config is null\n"); } } @@ -1008,16 +1009,16 @@ static int ldim_dev_get_config_from_dts(struct device_node *np, int index) switch (ldim_dev_config.type) { case LDIM_DEV_TYPE_SPI: /* get spi config */ - ldim_drv->spi_dev = &ldim_spi_dev; + ldim_drv->spi_info = &ldim_spi_info; ret = of_property_read_u32(child, "spi_bus_num", &val); if (ret) { LDIMERR("failed to get spi_bus_num\n"); } else { - ldim_spi_dev.bus_num = val; + ldim_spi_info.bus_num = val; if (ldim_debug_print) { LDIMPR("spi bus_num: %d\n", - ldim_spi_dev.bus_num); + ldim_spi_info.bus_num); } } @@ -1025,10 +1026,10 @@ static int ldim_dev_get_config_from_dts(struct device_node *np, int index) if (ret) { LDIMERR("failed to get spi_chip_select\n"); } else { - ldim_spi_dev.chip_select = val; + ldim_spi_info.chip_select = val; if (ldim_debug_print) { LDIMPR("spi chip_select: %d\n", - ldim_spi_dev.chip_select); + ldim_spi_info.chip_select); } } @@ -1036,10 +1037,10 @@ static int ldim_dev_get_config_from_dts(struct device_node *np, int index) if (ret) { LDIMERR("failed to get spi_chip_select\n"); } else { - ldim_spi_dev.max_speed_hz = val; + ldim_spi_info.max_speed_hz = val; if (ldim_debug_print) { LDIMPR("spi max_speed_hz: %d\n", - ldim_spi_dev.max_speed_hz); + ldim_spi_info.max_speed_hz); } } @@ -1047,9 +1048,9 @@ static int ldim_dev_get_config_from_dts(struct device_node *np, int index) if (ret) { LDIMERR("failed to get spi_mode\n"); } else { - ldim_spi_dev.mode = val; + ldim_spi_info.mode = val; if (ldim_debug_print) - LDIMPR("spi mode: %d\n", ldim_spi_dev.mode); + LDIMPR("spi mode: %d\n", ldim_spi_info.mode); } ret = of_property_read_u32_array(child, "spi_cs_delay", @@ -1108,14 +1109,14 @@ static int ldim_dev_get_config_from_dts(struct device_node *np, int index) child, &ldim_dev_config, 1); if (ret) break; - ret = ldim_dev_init_table_dynamic_size_load_dts( + ldim_dev_init_table_dynamic_size_load_dts( child, &ldim_dev_config, 0); } else { ret = ldim_dev_init_table_fixed_size_load_dts( child, &ldim_dev_config, 1); if (ret) break; - ret = ldim_dev_init_table_fixed_size_load_dts( + ldim_dev_init_table_fixed_size_load_dts( child, &ldim_dev_config, 0); } if (ret == 0) @@ -1147,60 +1148,81 @@ ldim_get_config_err: return -1; } -static int ldim_dev_add_driver(struct ldim_dev_config_s *ldev_conf, int index) +static int ldim_dev_add_driver(struct aml_ldim_driver_s *ldim_drv) { - int ret = 0; + struct ldim_dev_config_s *ldev_conf = ldim_drv->ldev_conf; + int index = ldim_drv->dev_index; + int ret = -1; - if (strcmp(ldev_conf->name, "iw7027") == 0) { - ret = ldim_dev_iw7027_probe(); - goto ldim_dev_add_driver_next; - } else if (strcmp(ldev_conf->name, "ob3350") == 0) { - ret = ldim_dev_ob3350_probe(); - goto ldim_dev_add_driver_next; - } else if (strcmp(ldev_conf->name, "global") == 0) { - ret = ldim_dev_global_probe(); - goto ldim_dev_add_driver_next; - } else { - LDIMERR("invalid device name: %s\n", ldev_conf->name); - ret = -1; + switch (ldim_dev_config.type) { + case LDIM_DEV_TYPE_SPI: + ret = ldim_spi_driver_add(ldim_drv); + break; + case LDIM_DEV_TYPE_I2C: + break; + case LDIM_DEV_TYPE_NORMAL: + default: + break; } + if (ret) + return ret; + + ret = -1; + if (strcmp(ldev_conf->name, "iw7027") == 0) + ret = ldim_dev_iw7027_probe(ldim_drv); + else if (strcmp(ldev_conf->name, "ob3350") == 0) + ret = ldim_dev_ob3350_probe(ldim_drv); + else if (strcmp(ldev_conf->name, "global") == 0) + ret = ldim_dev_global_probe(ldim_drv); + else + LDIMERR("invalid device name: %s\n", ldev_conf->name); -ldim_dev_add_driver_next: if (ret) { - LDIMERR("add device driver failed %s(%d)\n", + LDIMERR("add device driver failed: %s(%d)\n", ldev_conf->name, index); } else { - LDIMPR("add device driver %s(%d)\n", ldev_conf->name, index); + ldim_dev_probe_flag = 1; + LDIMPR("add device driver: %s(%d)\n", ldev_conf->name, index); } return ret; } -static int ldim_dev_remove_driver(struct ldim_dev_config_s *ldev_conf, - int index) +static int ldim_dev_remove_driver(struct aml_ldim_driver_s *ldim_drv) { - int ret = 0; + struct ldim_dev_config_s *ldev_conf = ldim_drv->ldev_conf; + int index = ldim_drv->dev_index; + int ret = -1; - if (strcmp(ldev_conf->name, "iw7027") == 0) { - ret = ldim_dev_iw7027_remove(); - goto ldim_dev_remove_driver_next; - } else if (strcmp(ldev_conf->name, "ob3350") == 0) { - ret = ldim_dev_ob3350_remove(); - goto ldim_dev_remove_driver_next; - } else if (strcmp(ldev_conf->name, "global") == 0) { - ret = ldim_dev_global_remove(); - goto ldim_dev_remove_driver_next; - } else { - LDIMERR("invalid device name: %s\n", ldev_conf->name); - ret = -1; + if (ldim_dev_probe_flag) { + if (strcmp(ldev_conf->name, "iw7027") == 0) + ret = ldim_dev_iw7027_remove(ldim_drv); + else if (strcmp(ldev_conf->name, "ob3350") == 0) + ret = ldim_dev_ob3350_remove(ldim_drv); + else if (strcmp(ldev_conf->name, "global") == 0) + ret = ldim_dev_global_remove(ldim_drv); + else + LDIMERR("invalid device name: %s\n", ldev_conf->name); + + if (ret) { + LDIMERR("remove device driver failed: %s(%d)\n", + ldev_conf->name, index); + } else { + ldim_dev_probe_flag = 0; + LDIMPR("remove device driver: %s(%d)\n", + ldev_conf->name, index); + } } -ldim_dev_remove_driver_next: - if (ret) { - LDIMERR("remove device driver failed %s(%d)\n", - ldev_conf->name, index); - } else { - LDIMPR("remove device driver %s(%d)\n", ldev_conf->name, index); + switch (ldim_dev_config.type) { + case LDIM_DEV_TYPE_SPI: + ldim_spi_driver_remove(ldim_drv); + break; + case LDIM_DEV_TYPE_I2C: + break; + case LDIM_DEV_TYPE_NORMAL: + default: + break; } return ret; @@ -1209,8 +1231,8 @@ ldim_dev_remove_driver_next: static int ldim_dev_probe(struct platform_device *pdev) { struct aml_ldim_driver_s *ldim_drv = aml_ldim_get_driver(); - int ret = 0; + ldim_dev_probe_flag = 0; if (ldim_drv->dev_index != 0xff) { /* get configs */ ldim_drv->dev = &pdev->dev; @@ -1221,27 +1243,25 @@ static int ldim_dev_probe(struct platform_device *pdev) ldim_dev_get_config_from_dts(pdev->dev.of_node, ldim_drv->dev_index); - ldim_dev_add_driver(ldim_drv->ldev_conf, ldim_drv->dev_index); + ldim_dev_add_driver(ldim_drv); } /* init ldim function */ if (ldim_drv->valid_flag) ldim_drv->init(); LDIMPR("%s OK\n", __func__); - return ret; + return 0; } static int __exit ldim_dev_remove(struct platform_device *pdev) { - int ret = 0; struct aml_ldim_driver_s *ldim_drv = aml_ldim_get_driver(); - if (ldim_drv->dev_index != 0xff) { - ldim_dev_remove_driver(ldim_drv->ldev_conf, - ldim_drv->dev_index); - } + if (ldim_drv->dev_index != 0xff) + ldim_dev_remove_driver(ldim_drv); + LDIMPR("%s OK\n", __func__); - return ret; + return 0; } #ifdef CONFIG_OF diff --git a/drivers/amlogic/media/vout/backlight/aml_ldim/ldim_dev_drv.h b/drivers/amlogic/media/vout/backlight/aml_ldim/ldim_dev_drv.h index 6d5a111757df..901ebc05cea3 100644 --- a/drivers/amlogic/media/vout/backlight/aml_ldim/ldim_dev_drv.h +++ b/drivers/amlogic/media/vout/backlight/aml_ldim/ldim_dev_drv.h @@ -17,6 +17,16 @@ #ifndef __LDIM_DEV_DRV_H #define __LDIM_DEV_DRV_H +#include +#include + +/* ldim spi api*/ +extern int ldim_spi_write(struct spi_device *spi, unsigned char *tbuf, + int wlen); +extern int ldim_spi_read(struct spi_device *spi, unsigned char *tbuf, int wlen, + unsigned char *rbuf, int rlen); +extern int ldim_spi_driver_add(struct aml_ldim_driver_s *ldim_drv); +extern int ldim_spi_driver_remove(struct aml_ldim_driver_s *ldim_drv); /* ldim global api */ extern void ldim_gpio_set(int index, int value); @@ -25,14 +35,14 @@ extern void ldim_set_duty_pwm(struct bl_pwm_config_s *ld_pwm); extern void ldim_pwm_off(struct bl_pwm_config_s *ld_pwm); /* ldim dev api */ -extern int ldim_dev_iw7027_probe(void); -extern int ldim_dev_iw7027_remove(void); +extern int ldim_dev_iw7027_probe(struct aml_ldim_driver_s *ldim_drv); +extern int ldim_dev_iw7027_remove(struct aml_ldim_driver_s *ldim_drv); -extern int ldim_dev_ob3350_probe(void); -extern int ldim_dev_ob3350_remove(void); +extern int ldim_dev_ob3350_probe(struct aml_ldim_driver_s *ldim_drv); +extern int ldim_dev_ob3350_remove(struct aml_ldim_driver_s *ldim_drv); -extern int ldim_dev_global_probe(void); -extern int ldim_dev_global_remove(void); +extern int ldim_dev_global_probe(struct aml_ldim_driver_s *ldim_drv); +extern int ldim_dev_global_remove(struct aml_ldim_driver_s *ldim_drv); #endif /* __LDIM_DEV_DRV_H */ diff --git a/drivers/amlogic/media/vout/backlight/aml_ldim/ldim_drv.c b/drivers/amlogic/media/vout/backlight/aml_ldim/ldim_drv.c index e4d4b679d826..bb5e4e6cb46e 100644 --- a/drivers/amlogic/media/vout/backlight/aml_ldim/ldim_drv.c +++ b/drivers/amlogic/media/vout/backlight/aml_ldim/ldim_drv.c @@ -59,6 +59,9 @@ const char ldim_dev_id[] = "ldim-dev"; unsigned char ldim_debug_print; struct ldim_dev_s { + struct ldim_operate_func_s *ldim_op_func; + struct ldim_param_s *ldim_db_para; + struct cdev cdev; struct device *dev; dev_t aml_ldim_devno; @@ -66,7 +69,6 @@ struct ldim_dev_s { struct cdev *aml_ldim_cdevp; }; static struct ldim_dev_s ldim_dev; -static struct ldim_param_s *ldim_db_para; static struct LDReg_s nPRM; static struct FW_DAT_s FDat; static struct ldim_fw_para_s ldim_fw_para; @@ -96,7 +98,7 @@ static struct work_struct ldim_on_vs_work; static struct work_struct ldim_off_vs_work; static unsigned int ldim_irq_cnt; -static unsigned int rdma_ldim_irq_cnt; +static unsigned int brightness_vs_cnt; /*BL_matrix remap curve*/ static unsigned int bl_remap_curve[16] = { @@ -128,9 +130,6 @@ static unsigned int ldim_top_en; module_param(ldim_top_en, uint, 0664); MODULE_PARM_DESC(ldim_top_en, "ldim_top_en"); -static void ldim_on_vs_brightness(void); -static void ldim_off_vs_brightness(void); -static void ldim_on_vs_arithmetic(void); static void ldim_dump_histgram(void); static void ldim_get_matrix_info_max_rgb(void); @@ -144,18 +143,6 @@ static struct ldim_config_s ldim_config = { .hvcnt_bypass = 0, }; -static void ldim_on_update_brightness(struct work_struct *work) -{ - ldim_stts_read_region(ldim_hist_row, ldim_hist_col); - ldim_on_vs_arithmetic(); - ldim_on_vs_brightness(); -} - -static void ldim_off_update_brightness(struct work_struct *work) -{ - ldim_off_vs_brightness(); -} - static void ldim_db_para_print(struct LDReg_s *mLDReg) { int i, len; @@ -276,58 +263,64 @@ static void ldim_db_para_print(struct LDReg_s *mLDReg) } static void ldim_db_load_update(struct LDReg_s *mLDReg, - struct ldim_param_s *db_pare) + struct ldim_param_s *db_para) { int i; - if (db_pare == NULL) + if (db_para == NULL) return; LDIMPR("ldim_db_load_update\n"); /* beam model */ - ldim_fw_para.rgb_base = db_pare->rgb_base; - ldim_fw_para.boost_gain = db_pare->boost_gain; - ldim_fw_para.lpf_res = db_pare->lpf_res; - ldim_fw_para.fw_LD_ThSF_l = db_pare->fw_ld_th_sf; + ldim_fw_para.rgb_base = db_para->rgb_base; + ldim_fw_para.boost_gain = db_para->boost_gain; + ldim_fw_para.lpf_res = db_para->lpf_res; + ldim_fw_para.fw_LD_ThSF_l = db_para->fw_ld_th_sf; /* beam curve */ - mLDReg->reg_LD_Vgain = db_pare->ld_vgain; - mLDReg->reg_LD_Hgain = db_pare->ld_hgain; - mLDReg->reg_LD_Litgain = db_pare->ld_litgain; + mLDReg->reg_LD_Vgain = db_para->ld_vgain; + mLDReg->reg_LD_Hgain = db_para->ld_hgain; + mLDReg->reg_LD_Litgain = db_para->ld_litgain; - mLDReg->reg_LD_LUT_Vdg_LEXT = db_pare->ld_lut_vdg_lext; - mLDReg->reg_LD_LUT_Hdg_LEXT = db_pare->ld_lut_hdg_lext; - mLDReg->reg_LD_LUT_VHk_LEXT = db_pare->ld_lut_vhk_lext; + mLDReg->reg_LD_LUT_Vdg_LEXT = db_para->ld_lut_vdg_lext; + mLDReg->reg_LD_LUT_Hdg_LEXT = db_para->ld_lut_hdg_lext; + mLDReg->reg_LD_LUT_VHk_LEXT = db_para->ld_lut_vhk_lext; for (i = 0; i < 32; i++) { - mLDReg->reg_LD_LUT_Hdg[i] = db_pare->ld_lut_hdg[i]; - mLDReg->reg_LD_LUT_Vdg[i] = db_pare->ld_lut_vdg[i]; - mLDReg->reg_LD_LUT_VHk[i] = db_pare->ld_lut_vhk[i]; + mLDReg->reg_LD_LUT_Hdg[i] = db_para->ld_lut_hdg[i]; + mLDReg->reg_LD_LUT_Vdg[i] = db_para->ld_lut_vdg[i]; + mLDReg->reg_LD_LUT_VHk[i] = db_para->ld_lut_vhk[i]; } /* beam shape minor adjustment */ for (i = 0; i < 32; i++) { - mLDReg->reg_LD_LUT_VHk_pos[i] = db_pare->ld_lut_vhk_pos[i]; - mLDReg->reg_LD_LUT_VHk_neg[i] = db_pare->ld_lut_vhk_neg[i]; - mLDReg->reg_LD_LUT_HHk[i] = db_pare->ld_lut_hhk[i]; - mLDReg->reg_LD_LUT_VHo_pos[i] = db_pare->ld_lut_vho_pos[i]; - mLDReg->reg_LD_LUT_VHo_neg[i] = db_pare->ld_lut_vho_neg[i]; + mLDReg->reg_LD_LUT_VHk_pos[i] = db_para->ld_lut_vhk_pos[i]; + mLDReg->reg_LD_LUT_VHk_neg[i] = db_para->ld_lut_vhk_neg[i]; + mLDReg->reg_LD_LUT_HHk[i] = db_para->ld_lut_hhk[i]; + mLDReg->reg_LD_LUT_VHo_pos[i] = db_para->ld_lut_vho_pos[i]; + mLDReg->reg_LD_LUT_VHo_neg[i] = db_para->ld_lut_vho_neg[i]; } /* remapping */ - /*db_pare->lit_idx_th;*/ - /*db_pare->comp_gain;*/ + /*db_para->lit_idx_th;*/ + /*db_para->comp_gain;*/ if (db_print_flag == 1) ldim_db_para_print(mLDReg); } +static void ldim_stts_initial_txlx(unsigned int resolution) +{ + Wr_reg(LDIM_STTS_CTRL0, 7 << 2); + ldim_set_matrix_ycbcr2rgb(); + ldim_stts_en(resolution, 0, 0, 1, 1, 1, 0); +} + static void ldim_stts_initial(unsigned int pic_h, unsigned int pic_v, unsigned int BLK_Vnum, unsigned int BLK_Hnum) { unsigned int resolution, resolution_region, blk_height, blk_width; unsigned int row_start, col_start; - struct aml_bl_drv_s *bl_drv = aml_bl_get_driver(); BLK_Vnum = (BLK_Vnum == 0) ? 1 : BLK_Vnum; BLK_Hnum = (BLK_Hnum == 0) ? 1 : BLK_Hnum; @@ -339,21 +332,12 @@ static void ldim_stts_initial(unsigned int pic_h, unsigned int pic_v, resolution = (((pic_h - 1) & 0xffff) << 16) | ((pic_v - 1) & 0xffff); /*Wr_reg(VDIN0_HIST_CTRL, 0x10d);*/ - switch (bl_drv->data->chip_type) { - case BL_CHIP_TXLX: - Wr_reg(LDIM_STTS_CTRL0, 7 << 2); - ldim_set_matrix_ycbcr2rgb(); - ldim_stts_en(resolution, 0, 0, 1, 1, 1, 0); - break; - case BL_CHIP_GXTVBB: - Wr_reg(LDIM_STTS_CTRL0, 3 << 3);/*4 mux to vpp_dout*/ - ldim_set_matrix_ycbcr2rgb(); - /*ldim_set_matrix_rgb2ycbcr(0);*/ - ldim_stts_en(resolution, 0, 0, 1, 1, 1, 0); - break; - default: - break; + if (ldim_dev.ldim_op_func == NULL) { + LDIMERR("%s: invalid ldim_op_func\n", __func__); + return; } + if (ldim_dev.ldim_op_func->stts_init) + ldim_dev.ldim_op_func->stts_init(resolution); resolution_region = 0; @@ -365,155 +349,6 @@ static void ldim_stts_initial(unsigned int pic_h, unsigned int pic_v, row_start, col_start, BLK_Hnum); } -static void LDIM_Initial_GXTVBB(unsigned int ldim_bl_en, - unsigned int ldim_hvcnt_bypass) -{ - unsigned int i, j, k; - unsigned int data; - unsigned int *arrayTmp; - - arrayTmp = kcalloc(1536, sizeof(unsigned int), GFP_KERNEL); - if (arrayTmp == NULL) { - LDIMERR("%s malloc error\n", __func__); - return; - } - - data = LDIM_RD_32Bits(REG_LD_MISC_CTRL0); - data = data & (~(3<<4)); - LDIM_WR_32Bits(REG_LD_MISC_CTRL0, data); - /*change here: gBLK_Hidx_LUT: s14*19 */ - LDIM_WR_BASE_LUT(REG_LD_BLK_HIDX_BASE, - nPRM.reg_LD_BLK_Hidx, 16, LD_BLK_LEN_H); - /* change here: gBLK_Vidx_LUT: s14*19 */ - LDIM_WR_BASE_LUT(REG_LD_BLK_VIDX_BASE, - nPRM.reg_LD_BLK_Vidx, 16, LD_BLK_LEN_V); - /* change here: gHDG_LUT: u10*32 */ - LDIM_WR_BASE_LUT(REG_LD_LUT_HDG_BASE, - nPRM.reg_LD_LUT_Hdg, 16, LD_LUT_LEN); - /* change here: gVDG_LUT: u10*32 */ - LDIM_WR_BASE_LUT(REG_LD_LUT_VDG_BASE, - nPRM.reg_LD_LUT_Vdg, 16, LD_LUT_LEN); - /* change here: gVHk_LUT: u10*32 */ - LDIM_WR_BASE_LUT(REG_LD_LUT_VHK_BASE, - nPRM.reg_LD_LUT_VHk, 16, LD_LUT_LEN); - /* reg_LD_LUT_VHk_pos[32]/reg_LD_LUT_VHk_neg[32]: u8 */ - for (i = 0; i < 32; i++) - arrayTmp[i] = nPRM.reg_LD_LUT_VHk_pos[i]; - for (i = 0; i < 32; i++) - arrayTmp[32+i] = nPRM.reg_LD_LUT_VHk_neg[i]; - LDIM_WR_BASE_LUT(REG_LD_LUT_VHK_NEGPOS_BASE, arrayTmp, 8, 64); - /* reg_LD_LUT_VHo_pos[32]/reg_LD_LUT_VHo_neg[32]: s8 */ - for (i = 0; i < 32; i++) - arrayTmp[i] = nPRM.reg_LD_LUT_VHo_pos[i]; - for (i = 0; i < 32; i++) - arrayTmp[32+i] = nPRM.reg_LD_LUT_VHo_neg[i]; - LDIM_WR_BASE_LUT(REG_LD_LUT_VHO_NEGPOS_BASE, arrayTmp, 8, 64); - /* reg_LD_LUT_HHk[32]:u8 */ - LDIM_WR_BASE_LUT(REG_LD_LUT_HHK_BASE, nPRM.reg_LD_LUT_HHk, 8, 32); - /*gLD_REFLECT_DGR_LUT: u6 * (20+20+4) */ - for (i = 0; i < 20; i++) - arrayTmp[i] = nPRM.reg_LD_Reflect_Hdgr[i]; - for (i = 0; i < 20; i++) - arrayTmp[20+i] = nPRM.reg_LD_Reflect_Vdgr[i]; - for (i = 0; i < 4; i++) - arrayTmp[40+i] = nPRM.reg_LD_Reflect_Xdgr[i]; - LDIM_WR_BASE_LUT(REG_LD_REFLECT_DGR_BASE, arrayTmp, 8, 44); - /* X_lut: 12 * 3*16*32 */ - for (i = 0; i < 3; i++) - for (j = 0; j < 16; j++) - for (k = 0; k < 32; k++) - arrayTmp[16*32*i+32*j+k] = nPRM.X_lut[i][j][k]; - LDIM_WR_BASE_LUT(REG_LD_RGB_LUT_BASE, arrayTmp, 16, 32*16*3); - /* X_nrm: 4 * 16 */ - LDIM_WR_BASE_LUT(REG_LD_RGB_NRMW_BASE, nPRM.X_nrm[0], 4, 16); - /* X_idx: 12*16 */ - /*LDIM_WR_BASE_LUT(REG_LD_RGB_IDX_BASE, nPRM.X_idx[0], 12, 16);*/ - LDIM_WR_BASE_LUT(REG_LD_RGB_IDX_BASE, nPRM.X_idx[0], 16, 16); - /* gMatrix_LUT: u12*LD_BLKREGNUM */ - LDIM_WR_BASE_LUT_DRT(REG_LD_MATRIX_BASE, nPRM.BL_matrix, LD_BLKREGNUM); - /* LD_FRM_SIZE */ - data = ((nPRM.reg_LD_pic_RowMax&0xfff)<<16) | - (nPRM.reg_LD_pic_ColMax&0xfff); - LDIM_WR_32Bits(REG_LD_FRM_SIZE, data); - /* LD_RGB_MOD */ - data = ((nPRM.reg_LD_RGBmapping_demo & 0x1) << 19) | - ((nPRM.reg_LD_X_LUT_interp_mode[2] & 0x1) << 18) | - ((nPRM.reg_LD_X_LUT_interp_mode[1] & 0x1) << 17) | - ((nPRM.reg_LD_X_LUT_interp_mode[0] & 0x1) << 16) | - ((nPRM.reg_LD_BkLit_LPFmod & 0x7) << 12) | - ((nPRM.reg_LD_Litshft & 0x7) << 8) | - ((nPRM.reg_LD_BackLit_Xtlk & 0x1) << 7) | - ((nPRM.reg_LD_BkLit_Intmod & 0x1) << 6) | - ((nPRM.reg_LD_BkLUT_Intmod & 0x1) << 5) | - ((nPRM.reg_LD_BkLit_curmod & 0x1) << 4) | - ((nPRM.reg_LD_BackLit_mode & 0x3)); - LDIM_WR_32Bits(REG_LD_RGB_MOD, data); - /* LD_BLK_HVNUM */ - data = ((nPRM.reg_LD_Reflect_Vnum & 0x7) << 20) | - ((nPRM.reg_LD_Reflect_Hnum & 0x7) << 16) | - ((nPRM.reg_LD_BLK_Vnum & 0x3f) << 8) | - ((nPRM.reg_LD_BLK_Hnum & 0x3f)); - LDIM_WR_32Bits(REG_LD_BLK_HVNUM, data); - /* REG_LD_FRM_HBLAN_VHOLS */ - data = ((nPRM.reg_LD_LUT_VHo_LS & 0x7) << 16) | - ((6 & 0x1fff)) ; /*frm_hblank_num */ - LDIM_WR_32Bits(REG_LD_FRM_HBLAN_VHOLS, data); - /* LD_HVGAIN */ - data = ((nPRM.reg_LD_Vgain & 0xfff) << 16) | - (nPRM.reg_LD_Hgain & 0xfff); - LDIM_WR_32Bits(REG_LD_HVGAIN, data); - /* LD_LIT_GAIN_COMP */ - data = ((nPRM.reg_LD_Litgain & 0xfff) << 16) | - (nPRM.reg_BL_matrix_Compensate & 0xfff); - LDIM_WR_32Bits(REG_LD_LIT_GAIN_COMP, data); - /* LD_BKLIT_VLD */ - data = 0; - for (i = 0; i < 32; i++) - if (nPRM.reg_LD_BkLit_valid[i]) - data = data | (1<data->chip_type) { - case BL_CHIP_TXLX: - LDIM_Initial_TXLX(ldim_bl_en, ldim_hvcnt_bypass); - break; - case BL_CHIP_GXTVBB: - LDIM_Initial_GXTVBB(ldim_bl_en, ldim_hvcnt_bypass); - break; - default: - break; + if (ldim_dev.ldim_op_func == NULL) { + LDIMERR("%s: invalid ldim_op_func\n", __func__); + return; } + if (ldim_dev.ldim_op_func->ldim_init) + ldim_dev.ldim_op_func->ldim_init(ldim_bl_en, ldim_hvcnt_bypass); } static void ldim_update_matrix(unsigned int mode) @@ -830,44 +659,6 @@ static void ldim_update_matrix(unsigned int mode) LDIM_WR_32Bits(REG_LD_MISC_CTRL0, data); } -static void ldim_update_gxtvbb(void) -{ - unsigned int data; - - if (ldim_avg_update_en) { - /* LD_BKLIT_PARAM */ - data = LDIM_RD_32Bits(REG_LD_BKLIT_PARAM); - data = (data&(~0xfff)) | (nPRM.reg_BL_matrix_AVG&0xfff); - LDIM_WR_32Bits(REG_LD_BKLIT_PARAM, data); - - /* compensate */ - data = LDIM_RD_32Bits(REG_LD_LIT_GAIN_COMP); - data = (data&(~0xfff)) | - (nPRM.reg_BL_matrix_Compensate & 0xfff); - LDIM_WR_32Bits(REG_LD_LIT_GAIN_COMP, data); - } - if (ldim_matrix_update_en) { - data = LDIM_RD_32Bits(REG_LD_MISC_CTRL0); - data = data & (~(3<<4)); - data = data | (1<<2); - LDIM_WR_32Bits(REG_LD_MISC_CTRL0, data); - - /* gMatrix_LUT: s12*100 ==> max to 8*8 enum ##r/w ram method*/ - LDIM_WR_BASE_LUT_DRT(REG_LD_MATRIX_BASE, - &(nPRM.BL_matrix[0]), ldim_blk_row*ldim_blk_col); - - /*data = LDIM_RD_32Bits(REG_LD_MISC_CTRL0);*/ - data = data | (3<<4); - LDIM_WR_32Bits(REG_LD_MISC_CTRL0, data); - } else { - data = LDIM_RD_32Bits(REG_LD_MISC_CTRL0); - data = data & (~(1<<2)); - LDIM_WR_32Bits(REG_LD_MISC_CTRL0, data); - } - /* disable the CBUS configure the RAM */ - -} - static void ldim_update_txlx(void) { unsigned int data; @@ -892,64 +683,34 @@ static void ldim_update_txlx(void) static void ldim_update_setting(void) { - struct aml_bl_drv_s *bl_drv = aml_bl_get_driver(); - - switch (bl_drv->data->chip_type) { - case BL_CHIP_TXLX: - ldim_update_txlx(); - break; - case BL_CHIP_GXTVBB: - ldim_update_gxtvbb(); - break; - default: - break; + if (ldim_dev.ldim_op_func == NULL) { + if (brightness_vs_cnt == 0) + LDIMERR("%s: invalid ldim_op_func\n", __func__); + return; } -} - -static irqreturn_t rdma_ldim_intr(int irq, void *dev_id) -{ - ulong flags; - - /*LDIMPR("*********rdma_ldim_intr start*********\n");*/ - spin_lock_irqsave(&rdma_ldim_isr_lock, flags); - - if (ldim_hist_en) { - /*schedule_work(&ldim_on_vs_work);*/ - queue_work(ldim_queue, &ldim_on_vs_work); - } - rdma_ldim_irq_cnt++; - if (rdma_ldim_irq_cnt > 0xfffffff) - rdma_ldim_irq_cnt = 0; - spin_unlock_irqrestore(&rdma_ldim_isr_lock, flags); - /*LDIMPR("*********rdma_ldim_intr end*********\n");*/ - return IRQ_HANDLED; + if (ldim_dev.ldim_op_func->update_setting) + ldim_dev.ldim_op_func->update_setting(); } static irqreturn_t ldim_vsync_isr(int irq, void *dev_id) { - ulong flags; - struct aml_bl_drv_s *bl_drv = aml_bl_get_driver(); + unsigned long flags; if (ldim_on_flag == 0) return IRQ_HANDLED; spin_lock_irqsave(&ldim_isr_lock, flags); + if (brightness_vs_cnt++ >= 30) /* for debug print */ + brightness_vs_cnt = 0; + if (ldim_func_en) { if (ldim_avg_update_en) ldim_update_setting(); - switch (bl_drv->data->chip_type) { - case BL_CHIP_TXLX: - if (ldim_hist_en) { - /*schedule_work(&ldim_on_vs_work);*/ - queue_work(ldim_queue, &ldim_on_vs_work); - } - break; - case BL_CHIP_GXTVBB: - break; - default: - break; + if (ldim_hist_en) { + /*schedule_work(&ldim_on_vs_work);*/ + queue_work(ldim_queue, &ldim_on_vs_work); } } else { /*schedule_work(&ldim_off_vs_work);*/ @@ -965,7 +726,6 @@ static irqreturn_t ldim_vsync_isr(int irq, void *dev_id) return IRQ_HANDLED; } -static int brightness_vs_cnt; static void ldim_on_vs_brightness(void) { unsigned int size; @@ -974,9 +734,6 @@ static void ldim_on_vs_brightness(void) if (ldim_on_flag == 0) return; - if (brightness_vs_cnt++ >= 30) - brightness_vs_cnt = 0; - if (ldim_func_bypass) return; @@ -1030,9 +787,6 @@ static void ldim_off_vs_brightness(void) if (ldim_on_flag == 0) return; - if (brightness_vs_cnt++ >= 30) - brightness_vs_cnt = 0; - size = ldim_blk_row * ldim_blk_col; if (ldim_level_update) { @@ -1126,6 +880,18 @@ static void ldim_on_vs_arithmetic(void) kfree(local_ldim_max_rgb); } +static void ldim_on_update_brightness(struct work_struct *work) +{ + ldim_stts_read_region(ldim_hist_row, ldim_hist_col); + ldim_on_vs_arithmetic(); + ldim_on_vs_brightness(); +} + +static void ldim_off_update_brightness(struct work_struct *work) +{ + ldim_off_vs_brightness(); +} + static void ldim_bl_remap_curve_print(void) { int i = 0, len; @@ -1999,6 +1765,8 @@ static struct aml_ldim_driver_s ldim_driver = { .device_power_off = NULL, .device_bri_update = NULL, .device_bri_check = NULL, + .spi_dev = NULL, + .spi_info = NULL, }; struct aml_ldim_driver_s *aml_ldim_get_driver(void) @@ -2036,10 +1804,10 @@ static long ldim_ioctl(struct file *file, unsigned int cmd, unsigned long arg) LDIMERR("db_para malloc error\n"); return -EINVAL; } - ldim_db_para = db_para; - if (copy_from_user(ldim_db_para, (void __user *)arg, + ldim_dev.ldim_db_para = db_para; + if (copy_from_user(ldim_dev.ldim_db_para, (void __user *)arg, sizeof(struct ldim_param_s))) { - ldim_db_para = NULL; + ldim_dev.ldim_db_para = NULL; kfree(db_para); return -EINVAL; } @@ -2047,7 +1815,7 @@ static long ldim_ioctl(struct file *file, unsigned int cmd, unsigned long arg) LDIM_Initial(ldim_config.hsize, ldim_config.vsize, ldim_blk_row, ldim_blk_col, ldim_config.bl_mode, 1, 0); - ldim_db_para = NULL; + ldim_dev.ldim_db_para = NULL; kfree(db_para); break; @@ -3422,14 +3190,28 @@ ldim_malloc_err0: return -1; } +static struct ldim_operate_func_s ldim_op_func_txlx = { + .update_setting = ldim_update_txlx, + .stts_init = ldim_stts_initial_txlx, + .ldim_init = ldim_initial_txlx, +}; + +static struct ldim_operate_func_s ldim_op_func_tl1 = { + .update_setting = NULL, + .stts_init = NULL, + .ldim_init = NULL, +}; + int aml_ldim_probe(struct platform_device *pdev) { int ret = 0; unsigned int i; - unsigned int ldim_vsync_irq = 0, ldim_rdma_irq = 0; + unsigned int ldim_vsync_irq = 0; struct ldim_dev_s *devp = &ldim_dev; struct aml_bl_drv_s *bl_drv = aml_bl_get_driver(); + memset(devp, 0, (sizeof(struct ldim_dev_s))); + #ifdef LDIM_DEBUG_INFO ldim_debug_print = 1; #endif @@ -3454,7 +3236,19 @@ int aml_ldim_probe(struct platform_device *pdev) /* db para */ LDIM_DATA_FROM_DB = 0; - ldim_db_para = NULL; + devp->ldim_db_para = NULL; + /* ldim_op_func */ + switch (bl_drv->data->chip_type) { + case BL_CHIP_TL1: + devp->ldim_op_func = &ldim_op_func_tl1; + break; + case BL_CHIP_TXLX: + devp->ldim_op_func = &ldim_op_func_txlx; + break; + default: + devp->ldim_op_func = NULL; + break; + } ret = aml_ldim_malloc(ldim_blk_row, ldim_blk_col); if (ret) { @@ -3462,8 +3256,6 @@ int aml_ldim_probe(struct platform_device *pdev) goto err; } - memset(devp, 0, (sizeof(struct ldim_dev_s))); - ret = alloc_chrdev_region(&devp->aml_ldim_devno, 0, 1, AML_LDIM_DEVICE_NAME); if (ret < 0) { @@ -3534,27 +3326,6 @@ int aml_ldim_probe(struct platform_device *pdev) else LDIMPR("request ldim_vsync_irq successful\n"); - switch (bl_drv->data->chip_type) { - case BL_CHIP_GXTVBB: - bl_drv->res_ldim_rdma_irq = platform_get_resource(pdev, - IORESOURCE_IRQ, 1); - if (!bl_drv->res_ldim_rdma_irq) { - ret = -ENODEV; - LDIMERR("ldim_rdma_irq resource error\n"); - goto err; - } - ldim_rdma_irq = bl_drv->res_ldim_rdma_irq->start; - LDIMPR("ldim_rdma_irq: %d\n", ldim_rdma_irq); - if (request_irq(ldim_rdma_irq, rdma_ldim_intr, IRQF_SHARED, - "ldim_rdma", (void *)"ldim_rdma")) - LDIMERR("can't request ldim_rdma_irq\n"); - else - LDIMPR("request ldim_rdma_irq successful\n"); - break; - default: - break; - } - ldim_driver.valid_flag = 1; LDIMPR("%s ok\n", __func__); @@ -3594,16 +3365,6 @@ int aml_ldim_remove(void) kfree(ldim_driver.local_ldim_matrix); free_irq(bl_drv->res_ldim_vsync_irq->start, (void *)"ldim_vsync"); - switch (bl_drv->data->chip_type) { - case BL_CHIP_GXTVBB: - if (bl_drv->res_ldim_rdma_irq) { - free_irq(bl_drv->res_ldim_rdma_irq->start, - (void *)"ldim_rdma"); - } - break; - default: - break; - } cdev_del(devp->aml_ldim_cdevp); kfree(devp->aml_ldim_cdevp); diff --git a/drivers/amlogic/media/vout/backlight/aml_ldim/ldim_drv.h b/drivers/amlogic/media/vout/backlight/aml_ldim/ldim_drv.h index 6200d25a728d..dfd58f785a62 100644 --- a/drivers/amlogic/media/vout/backlight/aml_ldim/ldim_drv.h +++ b/drivers/amlogic/media/vout/backlight/aml_ldim/ldim_drv.h @@ -23,7 +23,8 @@ /*20180725: new pwm control flow support */ /*20180730: algorithm clear up */ /*20180820: pq tooling support, espically optimize some alg parameters */ -#define LDIM_DRV_VER "20180820" +/*20181101: fix ldim_op_func null mistake, add new spi api support */ +#define LDIM_DRV_VER "20181101" extern unsigned char ldim_debug_print; @@ -36,6 +37,13 @@ extern int LD_remap_lut[16][32]; /*========================================*/ +struct ldim_operate_func_s { + void (*update_setting)(void); + void (*stts_init)(unsigned int resolution); + void (*ldim_init)(unsigned int bl_en, unsigned int hvcnt_bypass); +}; + +/*========================================*/ extern int ldim_round(int ix, int ib); extern void ldim_stts_en(unsigned int resolution, unsigned int pix_drop_mode, diff --git a/drivers/amlogic/media/vout/backlight/aml_ldim/ldim_func.c b/drivers/amlogic/media/vout/backlight/aml_ldim/ldim_func.c index 46b4a9a8ae2c..606cd542e203 100644 --- a/drivers/amlogic/media/vout/backlight/aml_ldim/ldim_func.c +++ b/drivers/amlogic/media/vout/backlight/aml_ldim/ldim_func.c @@ -41,51 +41,6 @@ #define Wr(reg, val) Wr_reg(reg, val) #define Rd(reg) Rd_reg(reg) -static int LD_STA1max_Hidx[25] = { - /* U12* 25 */ - 0, 480, 960, 1440, 1920, 2400, 2880, - 3360, 3840, 4095, 4095, 4095, 4095, - 4095, 4095, 4095, 4095, 4095, 4095, - 4095, 4095, 4095, 4095, 4095, 4095 -}; - -static int LD_STA1max_Vidx[17] = { - /* u12x 17 */ - 0, 2160, 4095, 4095, 4095, 4095, - 4095, 4095, 4095, 4095, 4095, 4095, - 4095, 4095, 4095, 4095, 4095 -}; - -static int LD_STA2max_Hidx[25] = { - /* U12* 25 */ - 0, 480, 960, 1440, 1920, 2400, 2880, - 3360, 3840, 4095, 4095, 4095, 4095, - 4095, 4095, 4095, 4095, 4095, 4095, - 4095, 4095, 4095, 4095, 4095, 4095 -}; - -static int LD_STA2max_Vidx[17] = { - /* u12x 17 */ - 0, 2160, 4095, 4095, 4095, 4095, - 4095, 4095, 4095, 4095, 4095, 4095, - 4095, 4095, 4095, 4095, 4095 -}; - -static int LD_STAhist_Hidx[25] = { - /* U12* 25 */ - 0, 480, 960, 1440, 1920, 2400, 2880, - 3360, 3840, 4095, 4095, 4095, 4095, - 4095, 4095, 4095, 4095, 4095, 4095, - 4095, 4095, 4095, 4095, 4095, 4095 -}; - -static int LD_STAhist_Vidx[17] = { - /* u12x 17 */ - 0, 2160, 4095, 4095, 4095, 4095, - 4095, 4095, 4095, 4095, 4095, 4095, - 4095, 4095, 4095, 4095, 4095 -}; - static int LD_BLK_Hidx[33] = { /* S14* 33 */ -1920, -1440, -960, -480, 0, 480, @@ -104,27 +59,6 @@ static int LD_BLK_Vidx[25] = { 8191, 8191, 8191, 8191, 8191, 8191, 8191 }; -static int LD_LUT_Hdg[32] = { - /* u10 */ - 503, 501, 494, 481, 465, 447, 430, 409, 388, 369, 354, - 343, 334, 326, 318, 311, 305, 299, 293, 286, 279, 272, - 266, 261, 257, 252, 245, 235, 226, 218, 214, 213 -}; - -static int LD_LUT_Vdg[32] = { - /* u10 */ - 373, 371, 367, 364, 359, 353, 346, 337, 328, 318, 308, - 297, 286, 274, 261, 247, 232, 218, 204, 191, 180, 169, - 158, 148, 138, 130, 122, 115, 108, 104, 100, 97 -}; - -static int LD_LUT_VHk[32] = { - /* u10 */ - 492, 492, 492, 492, 427, 356, 328, 298, 272, 251, 229, - 206, 191, 175, 162, 151, 144, 139, 131, 127, 119, 110, - 105, 101, 99, 98, 94, 85, 83, 77, 74, 73 -}; - static int LD_LUT_Hdg1[32] = { /* u10 */ 503, 501, 494, 481, 465, 447, 430, 409, 388, 369, 354, @@ -162,17 +96,20 @@ static int LD_LUT_Hdg1_TXLX[32] = { 455, 487, 498, 505, 506, 509, 503, 494, 493, 483, 484, 480, 478, 476, 472, 472, 468, 465, 459, 449, 448, 439, 436, 432, - 430, 413, 402, 386, 361, 343, 317, 307}; + 430, 413, 402, 386, 361, 343, 317, 307 +}; static int LD_LUT_Vdg1_TXLX[32] = { 485, 483, 474, 465, 451, 435, 406, 381, 350, 320, 283, 251, 211, 178, 147, 113, 88, 65, 52, 37, 27, 20, 16, 8, - 3, 2, 0, 0, 0, 0, 0, 0}; + 3, 2, 0, 0, 0, 0, 0, 0 +}; static int LD_LUT_VHk1_TXLX[32] = { 490, 410, 356, 317, 288, 272, 266, 260, 258, 253, 249, 246, 242, 240, 236, 236, 232, 229, 226, 224, 224, 222, 221, 221, - 221, 219, 219, 221, 219, 225, 228, 237}; + 221, 219, 219, 221, 219, 225, 228, 237 +}; static int reg_LD_LUT_Hdg_TXLX[8][32] = { {254, 248, 239, 226, 211, 194, 176, 156, 137, 119, 101, 85, 70, 57, 45, 36, @@ -275,18 +212,23 @@ static int reg_LD_LUT_VHk_TXLX[8][32] = { 128, 128, 128, 128, 128, 128, 128, 128, 128, 128, 128, 128, 128, 128, 128, 128}, }; -static int reg_LD_LUT_VHo_pos_TXLX[32] = {0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; -static int reg_LD_LUT_VHo_neg_TXLX[32] = {0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; +static int reg_LD_LUT_VHo_pos_TXLX[32] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; +static int reg_LD_LUT_VHo_neg_TXLX[32] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; static int reg_LD_LUT_Hdg_LEXT_TXLX[8] = { - 260, 260, 260, 260, 260, 260, 260, 260}; + 260, 260, 260, 260, 260, 260, 260, 260 +}; static int reg_LD_LUT_Vdg_LEXT_TXLX[8] = { - 260, 260, 260, 260, 260, 260, 260, 260}; + 260, 260, 260, 260, 260, 260, 260, 260 +}; static int reg_LD_LUT_VHk_LEXT_TXLX[8] = { - 128, 128, 128, 128, 128, 128, 128, 128}; + 128, 128, 128, 128, 128, 128, 128, 128 +}; /* public function */ @@ -873,269 +815,11 @@ void LD_LUTInit(struct LDReg_s *Reg) } } break; - case BL_CHIP_GXTVBB: - /* Emulate the FW to set the LUTs */ - for (k = 0; k < 16; k++) { - /*set the LUT to be inverse of the Lit_value,*/ - /* lit_idx distribute equal space, set by FW */ - Reg->X_idx[0][k] = 4095 - 256 * k; - Reg->X_nrm[0][k] = 8; - for (t = 0; t < 32; t++) { - Reg->X_lut[0][k][t] = LD_remap_lut[k][t]; - Reg->X_lut[1][k][t] = LD_remap_lut[k][t]; - Reg->X_lut[2][k][t] = LD_remap_lut[k][t]; - } - } - break; default: break; } } -static void ConLDReg_GXTVBB(struct LDReg_s *Reg) -{ - unsigned int T = 0; - unsigned int Vnum = 0; - unsigned int Hnum = 0; - unsigned int BSIZE = 0; - - /* General registers; */ - Reg->reg_LD_pic_RowMax = 2160;/* setting default */ - Reg->reg_LD_pic_ColMax = 3840; - LD_IntialData(Reg->reg_LD_pic_YUVsum, 3, 0); - /* only output u16*3, (internal ACC will be u32x3)*/ - LD_IntialData(Reg->reg_LD_pic_RGBsum, 3, 0); - - /* set same region division for statistics */ - Reg->reg_LD_STA_Vnum = 8; - Reg->reg_LD_STA_Hnum = 8; - - /*Image Statistic options */ - Reg->reg_LD_BLK_Vnum = 1;/*u5: Maximum to BLKVMAX */ - Reg->reg_LD_BLK_Hnum = 8;/*u5: Maximum to BLKHMAX */ - - Reg->reg_LD_STA1max_LPF = 1; - /*u1: STA1max statistics on [1 2 1]/4 filtered results */ - Reg->reg_LD_STA2max_LPF = 1; - /*u1: STA2max statistics on [1 2 1]/4 filtered results*/ - Reg->reg_LD_STAhist_LPF = 1; - /*u1: STAhist statistics on [1 2 1]/4 filtered results*/ - Reg->reg_LD_STA1max_Hdlt = 0; - /*u2: (2^x) extra pixels into Max calculation*/ - Reg->reg_LD_STA1max_Vdlt = 0; - /*u4: extra pixels into Max calculation vertically*/ - Reg->reg_LD_STA2max_Hdlt = 0; - /*u2: (2^x) extra pixels into Max calculation*/ - Reg->reg_LD_STA2max_Vdlt = 0; - /*u4: extra pixels into Max calculation vertically*/ - Reg->reg_LD_STAhist_mode = 3; - /*u3: histogram statistics on XX separately 20bits*16bins: - * 0:R-only,1:G-only 2:B-only 3:Y-only; 4:MAX(R,G,B),5/6/7:R&G&B - */ - Reg->reg_LD_STAhist_pix_drop_mode = 0;/*u2 */ - for (T = 0; T < LD_STA_LEN_H; T++) { - Reg->reg_LD_STA1max_Hidx[T] = LD_STA1max_Hidx[T];/*U12* 25*/ - Reg->reg_LD_STA2max_Hidx[T] = LD_STA2max_Hidx[T];/*U12* 25*/ - Reg->reg_LD_STAhist_Hidx[T] = LD_STAhist_Hidx[T];/*U12* 25*/ - } - for (T = 0; T < LD_STA_LEN_V; T++) { - Reg->reg_LD_STA1max_Vidx[T] = LD_STA1max_Vidx[T];/*u12x 17*/ - Reg->reg_LD_STA2max_Vidx[T] = LD_STA2max_Vidx[T];/*u12x 17*/ - Reg->reg_LD_STAhist_Vidx[T] = LD_STAhist_Vidx[T];/*u12x 17*/ - } - - /****** FBC3 fw_hw_alg_frm *******/ - Reg->reg_ldfw_BLmax = 4095; /*maximum BL value*/ - Reg->reg_ldfw_blk_norm = 128; - /*u8: normalization gain for blk number, - * 1/blk_num= norm>>(rs+8), norm = (1<<(rs+8))/blk_num - */ - - Reg->reg_ldfw_blk_norm_rs = 2; - /*u3: 0~7, 1/blk_num= norm>>(rs+8)*/ - - for (T = 0; T < 8; T++) - Reg->reg_ldfw_sta_hdg_weight[T] = 64; - - Reg->reg_ldfw_sta_max_mode = 3; - /* u2: maximum selection for components: - * 0: r_max, 1: g_max, 2: b_max; 3: max(r,g,b) - */ - - Reg->reg_ldfw_sta_max_hist_mode = 0; - /* u2: mode of reference max/hist mode: - * 0: MIN(max, hist), 1: MAX(max, hist) 2: (max+hist)/2, - * 3: (max(a,b)*3 + min(a,b))/4 - */ - - Reg->reg_ldfw_hist_valid_rate = 64; - /* u8, norm to 512 as "1", if hist_matrix[i]>(rate*histavg)>>9 */ - - Reg->reg_ldfw_hist_valid_ofst = 63;/* u8, hist valid bin upward offset*/ - Reg->reg_ldfw_sedglit_RL = 1;/*u1: single edge lit right/bottom mode*/ - - Reg->reg_ldfw_sf_thrd = 1600; - /*u12: threshold of difference to enable the sf;*/ - - Reg->reg_ldfw_boost_gain = 64; - /* u8: boost gain for the region that is - * larger than the average, norm to 16 as "1" - */ - - Reg->reg_ldfw_tf_alpha_rate = 16; - /*u8: rate to SFB_BL_matrix from last frame difference;*/ - - Reg->reg_ldfw_tf_alpha_ofst = 32; - /* u8: ofset to alpha SFB_BL_matrix from last frame difference;*/ - - Reg->reg_ldfw_tf_disable_th = 255; - /* u8: 4x is the threshod to disable tf to the alpha - * (SFB_BL_matrix from last frame difference; - */ - - Reg->reg_ldfw_blest_acmode = 1; - /* u3: 0: est on BLmatrix; 1: est on (BL-DC); - * 2: est on (BL-MIN); 3: est on (BL-MAX) 4: 2048; 5:1024 - */ - - Reg->reg_ldfw_sf_enable = 0; - /* u1: enable signal for spatial filter on the tbl_matrix */ - - Reg->reg_ldfw_boost_enable = 0; - /* u1: enable signal for Boost filter on the tbl_matrix */ - - Reg->ro_ldfw_bl_matrix_avg = 0; - /* u12: read-only register for bl_matrix */ - - /*---------------------Setting BL_matrix initial value - * (will be updated frame to frame in FW) - */ - Vnum = Reg->reg_LD_BLK_Vnum; - Hnum = Reg->reg_LD_BLK_Hnum; - BSIZE = Vnum*Hnum; - /*Initialization */ - LD_IntialData(Reg->BL_matrix, BSIZE, 4095); - - /* BackLight Modeling control register setting*/ - Reg->reg_LD_BackLit_Xtlk = 1; - /* u1: 0 no block to block Xtalk model needed; 1: Xtalk model needed*/ - Reg->reg_LD_BackLit_mode = 1; - /*u2: 0- LEFT/RIGHT Edge Lit; 1- Top/Bot Edge Lit; 2 - DirectLit modeled - * H/V independent; 3- DirectLit modeled HV Circle distribution - */ - Reg->reg_LD_Reflect_Hnum = 3; - /*u3: numbers of band reflection considered in Horizontal - * direction; 0~4 - */ - Reg->reg_LD_Reflect_Vnum = 0; - /*u3: numbers of band reflection considered in Horizontal - * direction; 0~4 - */ - Reg->reg_LD_BkLit_curmod = 0; - /*u1: 0: H/V separately, 1 Circle distribution*/ - Reg->reg_LD_BkLUT_Intmod = 1; - /*u1: 0: linear interpolation, 1 cubical interpolation*/ - Reg->reg_LD_BkLit_Intmod = 1; - /*u1: 0: linear interpolation, 1 cubical interpolation*/ - Reg->reg_LD_BkLit_LPFmod = 7; - /* u3: 0: no LPF, 1:[1 14 1]/16;2:[1 6 1]/8; 3: [1 2 1]/4; - * 4:[9 14 9]/32 5/6/7: [5 6 5]/16; - */ - Reg->reg_LD_BkLit_Celnum = 121; - /*u8:0:1920~61####((Reg->reg_LD_pic_ColMax+1)/32)+1;*/ - Reg->reg_BL_matrix_AVG = 4095; - /* u12: DC of whole picture BL to be subtract from BL_matrix - * during modeling (Set by FW daynamically) - */ - Reg->reg_BL_matrix_Compensate = 4095; - /* u12: DC of whole picture BL to be compensated back to - * Litfull after the model (Set by FW dynamically); - */ - LD_IntialData(Reg->reg_LD_Reflect_Hdgr, 20, 32); - /*20*u6: cells 1~20 for H Gains of different dist of Left/Right;*/ - LD_IntialData(Reg->reg_LD_Reflect_Vdgr, 20, 32); - /*20*u6: cells 1~20 for V Gains of different dist of Top/Bot; */ - LD_IntialData(Reg->reg_LD_Reflect_Xdgr, 4, 32);/* 4*u6: */ - - Reg->reg_LD_Vgain = 256;/* u12 */ - Reg->reg_LD_Hgain = 242;/* u12 */ - Reg->reg_LD_Litgain = 256;/* u12 */ - Reg->reg_LD_Litshft = 3; - /* u3 right shif of bits for the all Lit's sum */ - LD_IntialData(Reg->reg_LD_BkLit_valid, 32, 1); - /*u1x32: valid bits for the 32 cell Bklit to contribut to current - * position (refer to the backlit padding pattern) - * region division index 1 2 3 4 5(0) 6(1) 7(2) 8(3) 9(4) - * 10(5)11(6)12(7)13(8) 14(9)15(10) 16 17 18 19 - */ - for (T = 0; T < LD_BLK_LEN_H; T++) - Reg->reg_LD_BLK_Hidx[T] = LD_BLK_Hidx[T];/* S14* BLK_LEN_H */ - for (T = 0; T < LD_BLK_LEN_V; T++) - Reg->reg_LD_BLK_Vidx[T] = LD_BLK_Vidx[T];/* S14x BLK_LEN_V */ - for (T = 0; T < LD_LUT_LEN; T++) { - Reg->reg_LD_LUT_Hdg[T] = LD_LUT_Hdg[T]; - Reg->reg_LD_LUT_Vdg[T] = LD_LUT_Vdg[T]; - Reg->reg_LD_LUT_VHk[T] = LD_LUT_VHk[T]; - } - /* set the VHk_pos and VHk_neg value ,normalized to - * 128 as "1" 20150428 - */ - for (T = 0; T < 32; T++) { - Reg->reg_LD_LUT_VHk_pos[T] = 128;/* vdist>=0 */ - Reg->reg_LD_LUT_VHk_neg[T] = 128;/* vdist<0 */ - Reg->reg_LD_LUT_HHk[T] = 128;/* hdist gain */ - Reg->reg_LD_LUT_VHo_pos[T] = 0;/* vdist>=0 */ - Reg->reg_LD_LUT_VHo_neg[T] = 0;/* vdist<0 */ - } - Reg->reg_LD_LUT_VHo_LS = 0; - Reg->reg_LD_LUT_Hdg_LEXT = 505; - /* 2*(nPRM->reg_LD_LUT_Hdg[0]) - (nPRM->reg_LD_LUT_Hdg[1]); */ - Reg->reg_LD_LUT_Vdg_LEXT = 372; - /* 2*(nPRM->reg_LD_LUT_Vdg[0]) - (nPRM->reg_LD_LUT_Vdg[1]); */ - Reg->reg_LD_LUT_VHk_LEXT = 492; - /* 2*(nPRM->reg_LD_LUT_VHk[0]) - (nPRM->reg_LD_LUT_VHk[1]); */ - /* set the demo window */ - Reg->reg_LD_xlut_demo_roi_xstart = (Reg->reg_LD_pic_ColMax/4); - /* u14 start col index of the region of interest */ - Reg->reg_LD_xlut_demo_roi_xend = (Reg->reg_LD_pic_ColMax*3/4); - /* u14 end col index of the region of interest */ - Reg->reg_LD_xlut_demo_roi_ystart = (Reg->reg_LD_pic_RowMax/4); - /* u14 start row index of the region of interest */ - Reg->reg_LD_xlut_demo_roi_yend = (Reg->reg_LD_pic_RowMax*3/4); - /* u14 end row index of the region of interest */ - Reg->reg_LD_xlut_iroi_enable = 1; - /* u1: enable rgb LUT remapping inside regon of interest: - * 0: no rgb remapping; 1: enable rgb remapping - */ - Reg->reg_LD_xlut_oroi_enable = 1; - /* u1: enable rgb LUT remapping outside regon of interest: - * 0: no rgb remapping; 1: enable rgb remapping - */ - - /* Registers used in LD_RGB_LUT for RGB remaping */ - Reg->reg_LD_RGBmapping_demo = 0; - /* u2: 0 no demo mode 1: display BL_fulpel on RGB */ - Reg->reg_LD_X_LUT_interp_mode[0] = 1; - /* U1 0: using linear interpolation between to neighbour LUT; - * 1: use the nearest LUT results - */ - Reg->reg_LD_X_LUT_interp_mode[1] = 1; - /* U1 0: using linear interpolation between to neighbour LUT; - * 1: use the nearest LUT results - */ - Reg->reg_LD_X_LUT_interp_mode[2] = 1; - /* U1 0: using linear interpolation between to neighbour LUT; - * 1: use the nearest LUT results - */ - LD_LUTInit(Reg); - /* only do the Lit modleing on the AC part */ - Reg->fw_LD_BLEst_ACmode = 0; - /* u2: 0: est on BLmatrix; 1: est on (BL-DC); - * 2: est on (BL-MIN); 3: est on (BL-MAX) - */ -} - - static void ConLDReg_TXLX(struct LDReg_s *Reg) { int i, j; @@ -1399,9 +1083,6 @@ void LD_ConLDReg(struct LDReg_s *Reg) case BL_CHIP_TXLX: ConLDReg_TXLX(Reg); break; - case BL_CHIP_GXTVBB: - ConLDReg_GXTVBB(Reg); - break; default: break; } diff --git a/drivers/amlogic/media/vout/backlight/aml_ldim/ldim_spi.c b/drivers/amlogic/media/vout/backlight/aml_ldim/ldim_spi.c new file mode 100644 index 000000000000..5a687c9c811b --- /dev/null +++ b/drivers/amlogic/media/vout/backlight/aml_ldim/ldim_spi.c @@ -0,0 +1,155 @@ +/* + * drivers/amlogic/media/vout/backlight/aml_ldim/ldim_spi.c + * + * Copyright (C) 2017 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "ldim_drv.h" +#include "ldim_dev_drv.h" + +static unsigned int cs_hold_delay; +static unsigned int cs_clk_delay; + +int ldim_spi_write(struct spi_device *spi, unsigned char *tbuf, int tlen) +{ + struct spi_transfer xfer; + struct spi_message msg; + int ret; + + if (cs_hold_delay) + udelay(cs_hold_delay); + + spi_message_init(&msg); + memset(&xfer, 0, sizeof(xfer)); + xfer.tx_buf = (void *)tbuf; + xfer.rx_buf = NULL; + xfer.len = tlen; + spi_message_add_tail(&xfer, &msg); + ret = spi_sync(spi, &msg); + + return ret; +} + +int ldim_spi_read(struct spi_device *spi, unsigned char *tbuf, int tlen, + unsigned char *rbuf, int rlen) +{ + struct spi_transfer xfer[2]; + struct spi_message msg; + int ret; + + if (cs_hold_delay) + udelay(cs_hold_delay); + + spi_message_init(&msg); + memset(&xfer, 0, sizeof(xfer)); + xfer[0].tx_buf = (void *)tbuf; + xfer[0].rx_buf = NULL; + xfer[0].len = tlen; + spi_message_add_tail(&xfer[0], &msg); + xfer[1].tx_buf = NULL; + xfer[1].rx_buf = (void *)rbuf; + xfer[1].len = rlen; + spi_message_add_tail(&xfer[1], &msg); + ret = spi_sync(spi, &msg); + + return ret; +} + +static int ldim_spi_dev_probe(struct spi_device *spi) +{ + struct aml_ldim_driver_s *ldim_drv = aml_ldim_get_driver(); + int ret; + + if (ldim_debug_print) + LDIMPR("%s\n", __func__); + + ldim_drv->spi_dev = spi; + + dev_set_drvdata(&spi->dev, ldim_drv->ldev_conf); + spi->bits_per_word = 8; + cs_hold_delay = ldim_drv->ldev_conf->cs_hold_delay; + cs_clk_delay = ldim_drv->ldev_conf->cs_clk_delay; + + ret = spi_setup(spi); + if (ret) + LDIMERR("spi setup failed\n"); + + return ret; +} + +static int ldim_spi_dev_remove(struct spi_device *spi) +{ + struct aml_ldim_driver_s *ldim_drv = aml_ldim_get_driver(); + + if (ldim_debug_print) + LDIMPR("%s\n", __func__); + + ldim_drv->spi_dev = NULL; + return 0; +} + +static struct spi_driver ldim_spi_dev_driver = { + .probe = ldim_spi_dev_probe, + .remove = ldim_spi_dev_remove, + .driver = { + .name = "ldim_dev", + .owner = THIS_MODULE, + }, +}; + +int ldim_spi_driver_add(struct aml_ldim_driver_s *ldim_drv) +{ + int ret; + + if (ldim_drv->spi_info == NULL) { + LDIMERR("%s: spi_info is null\n", __func__); + return -1; + } + + spi_register_board_info(ldim_drv->spi_info, 1); + ret = spi_register_driver(&ldim_spi_dev_driver); + if (ret) { + LDIMERR("%s failed\n", __func__); + return -1; + } + if (ldim_drv->spi_dev == NULL) { + LDIMERR("%s failed\n", __func__); + return -1; + } + + LDIMPR("%s ok\n", __func__); + return 0; +} + +int ldim_spi_driver_remove(struct aml_ldim_driver_s *ldim_drv) +{ + if (ldim_drv->spi_dev) + spi_unregister_driver(&ldim_spi_dev_driver); + + LDIMPR("%s ok\n", __func__); + + return 0; +} + diff --git a/drivers/amlogic/media/vout/backlight/aml_ldim/ob3350_bl.c b/drivers/amlogic/media/vout/backlight/aml_ldim/ob3350_bl.c index 0c38412d54aa..4348321adf17 100644 --- a/drivers/amlogic/media/vout/backlight/aml_ldim/ob3350_bl.c +++ b/drivers/amlogic/media/vout/backlight/aml_ldim/ob3350_bl.c @@ -149,10 +149,8 @@ static struct class_attribute ob3350_class_attrs[] = { __ATTR_NULL }; -static int ob3350_ldim_driver_update(void) +static int ob3350_ldim_driver_update(struct aml_ldim_driver_s *ldim_drv) { - struct aml_ldim_driver_s *ldim_drv = aml_ldim_get_driver(); - ldim_drv->device_power_on = ob3350_power_on; ldim_drv->device_power_off = ob3350_power_off; ldim_drv->device_bri_update = ob3350_smr; @@ -160,7 +158,7 @@ static int ob3350_ldim_driver_update(void) return 0; } -int ldim_dev_ob3350_probe(void) +int ldim_dev_ob3350_probe(struct aml_ldim_driver_s *ldim_drv) { int ret; @@ -171,7 +169,7 @@ int ldim_dev_ob3350_probe(void) return -1; } - ob3350_ldim_driver_update(); + ob3350_ldim_driver_update(ldim_drv); bl_ob3350->cls.name = kzalloc(10, GFP_KERNEL); sprintf((char *)bl_ob3350->cls.name, "ob3350"); @@ -186,7 +184,7 @@ int ldim_dev_ob3350_probe(void) return ret; } -int ldim_dev_ob3350_remove(void) +int ldim_dev_ob3350_remove(struct aml_ldim_driver_s *ldim_drv) { kfree(bl_ob3350); bl_ob3350 = NULL; diff --git a/drivers/amlogic/media/vout/cvbs/cvbs_out.c b/drivers/amlogic/media/vout/cvbs/cvbs_out.c index 455934e5c5c6..7cda8b29fca2 100644 --- a/drivers/amlogic/media/vout/cvbs/cvbs_out.c +++ b/drivers/amlogic/media/vout/cvbs/cvbs_out.c @@ -148,8 +148,6 @@ static int cvbs_vdac_power_level; static void vdac_power_level_store(char *para); SET_CVBS_CLASS_ATTR(vdac_power_level, vdac_power_level_store); -static void bist_test_store(char *para); - static void cvbs_debug_store(char *para); SET_CVBS_CLASS_ATTR(debug, cvbs_debug_store); @@ -594,6 +592,8 @@ static int cvbs_set_current_vmode(enum vmode_e mode) tvmode, info->vinfo->sync_duration_den, info->vinfo->sync_duration_num); + /*set limit range for enci*/ + amvecm_clip_range_limit(1); if (mode & VMODE_INIT_BIT_MASK) { cvbs_out_vpu_power_ctrl(1); cvbs_out_clk_gate_ctrl(1); @@ -626,6 +626,9 @@ static int cvbs_module_disable(enum vmode_e cur_vmod) info->dwork_flag = 0; cvbs_cntl_output(0); + /*restore full range for encp/encl*/ + amvecm_clip_range_limit(0); + cvbs_out_vpu_power_ctrl(0); cvbs_out_clk_gate_ctrl(0); @@ -650,6 +653,102 @@ static int cvbs_vout_get_state(void) return cvbs_vout_state; } +static char *cvbs_out_bist_str[] = { + "OFF", /* 0 */ + "Color Bar", /* 1 */ + "Thin Line", /* 2 */ + "Dot Grid", /* 3 */ + "White", + "Red", + "Green", + "Blue", + "Black", +}; + +static void cvbs_bist_test(unsigned int bist) +{ + switch (bist) { + case 1: + case 2: + case 3: + cvbs_out_reg_write(ENCI_TST_CLRBAR_STRT, 0x112); + cvbs_out_reg_write(ENCI_TST_CLRBAR_WIDTH, 0xb4); + cvbs_out_reg_write(ENCI_TST_MDSEL, bist); + cvbs_out_reg_write(ENCI_TST_Y, 0x200); + cvbs_out_reg_write(ENCI_TST_CB, 0x200); + cvbs_out_reg_write(ENCI_TST_CR, 0x200); + cvbs_out_reg_write(ENCI_TST_EN, 1); + pr_info("show bist pattern %d: %s\n", + bist, cvbs_out_bist_str[bist]); + break; + case 4: + cvbs_out_reg_write(ENCI_TST_CLRBAR_STRT, 0x112); + cvbs_out_reg_write(ENCI_TST_CLRBAR_WIDTH, 0xb4); + cvbs_out_reg_write(ENCI_TST_MDSEL, 0); + cvbs_out_reg_write(ENCI_TST_Y, 0x3ff); + cvbs_out_reg_write(ENCI_TST_CB, 0x200); + cvbs_out_reg_write(ENCI_TST_CR, 0x200); + cvbs_out_reg_write(ENCI_TST_EN, 1); + pr_info("show bist pattern %d: %s\n", + bist, cvbs_out_bist_str[bist]); + break; + case 5: + cvbs_out_reg_write(ENCI_TST_CLRBAR_STRT, 0x112); + cvbs_out_reg_write(ENCI_TST_CLRBAR_WIDTH, 0xb4); + cvbs_out_reg_write(ENCI_TST_MDSEL, 0); + cvbs_out_reg_write(ENCI_TST_Y, 0x200); + cvbs_out_reg_write(ENCI_TST_CB, 0x0); + cvbs_out_reg_write(ENCI_TST_CR, 0x3ff); + cvbs_out_reg_write(ENCI_TST_EN, 1); + pr_info("show bist pattern %d: %s\n", + bist, cvbs_out_bist_str[bist]); + break; + case 6: + cvbs_out_reg_write(ENCI_TST_CLRBAR_STRT, 0x112); + cvbs_out_reg_write(ENCI_TST_CLRBAR_WIDTH, 0xb4); + cvbs_out_reg_write(ENCI_TST_MDSEL, 0); + cvbs_out_reg_write(ENCI_TST_Y, 0x200); + cvbs_out_reg_write(ENCI_TST_CB, 0x0); + cvbs_out_reg_write(ENCI_TST_CR, 0x0); + cvbs_out_reg_write(ENCI_TST_EN, 1); + pr_info("show bist pattern %d: %s\n", + bist, cvbs_out_bist_str[bist]); + break; + case 7: + cvbs_out_reg_write(ENCI_TST_CLRBAR_STRT, 0x112); + cvbs_out_reg_write(ENCI_TST_CLRBAR_WIDTH, 0xb4); + cvbs_out_reg_write(ENCI_TST_MDSEL, 0); + cvbs_out_reg_write(ENCI_TST_Y, 0x200); + cvbs_out_reg_write(ENCI_TST_CB, 0x3ff); + cvbs_out_reg_write(ENCI_TST_CR, 0x0); + cvbs_out_reg_write(ENCI_TST_EN, 1); + pr_info("show bist pattern %d: %s\n", + bist, cvbs_out_bist_str[bist]); + break; + case 8: + cvbs_out_reg_write(ENCI_TST_CLRBAR_STRT, 0x112); + cvbs_out_reg_write(ENCI_TST_CLRBAR_WIDTH, 0xb4); + cvbs_out_reg_write(ENCI_TST_MDSEL, 0); + cvbs_out_reg_write(ENCI_TST_Y, 0x0); + cvbs_out_reg_write(ENCI_TST_CB, 0x200); + cvbs_out_reg_write(ENCI_TST_CR, 0x200); + cvbs_out_reg_write(ENCI_TST_EN, 1); + pr_info("show bist pattern %d: %s\n", + bist, cvbs_out_bist_str[bist]); + break; + case 0: + default: + cvbs_out_reg_write(ENCI_TST_MDSEL, 1); + cvbs_out_reg_write(ENCI_TST_Y, 0x200); + cvbs_out_reg_write(ENCI_TST_CB, 0x200); + cvbs_out_reg_write(ENCI_TST_CR, 0x200); + cvbs_out_reg_write(ENCI_TST_EN, 0); + pr_info("show bist pattern %d: %s\n", + bist, cvbs_out_bist_str[0]); + break; + } +} + #ifdef CONFIG_PM static int cvbs_suspend(void) { @@ -684,6 +783,7 @@ static struct vout_server_s cvbs_vout_server = { .set_vframe_rate_end_hint = NULL, .set_vframe_rate_policy = NULL, .get_vframe_rate_policy = NULL, + .set_bist = cvbs_bist_test, #ifdef CONFIG_PM .vout_suspend = cvbs_suspend, .vout_resume = cvbs_resume, @@ -707,6 +807,7 @@ static struct vout_server_s cvbs_vout2_server = { .set_vframe_rate_end_hint = NULL, .set_vframe_rate_policy = NULL, .get_vframe_rate_policy = NULL, + .set_bist = cvbs_bist_test, #ifdef CONFIG_PM .vout_suspend = cvbs_suspend, .vout_resume = cvbs_resume, @@ -732,67 +833,6 @@ static void cvbs_init_vout(void) #endif } -/* **************************************************** */ -static char *cvbs_out_bist_str[] = { - "Fix Value", /* 0 */ - "Color Bar", /* 1 */ - "Thin Line", /* 2 */ - "Dot Grid", /* 3 */ -}; - -static void bist_test_store(char *para) -{ - unsigned long num; - enum vmode_e mode; - unsigned int start, width; - int ret; - - mode = info->vinfo->mode; - if (mode != VMODE_CVBS) { - pr_info("NOT VMODE_CVBS,RETURN\n"); - return; - } - ret = kstrtoul(para, 10, (unsigned long *)&num); - if (num > 3) { - switch (local_cvbs_mode) { - case MODE_480CVBS: - case MODE_576CVBS: - case MODE_PAL_M: - case MODE_PAL_N: - cvbs_out_reg_write(ENCI_TST_EN, 0); - break; - default: - cvbs_out_reg_setb(ENCP_VIDEO_MODE_ADV, 1, 3, 1); - cvbs_out_reg_write(VENC_VIDEO_TST_EN, 0); - break; - } - pr_info("disable bist pattern\n"); - } else { - switch (local_cvbs_mode) { - case MODE_480CVBS: - case MODE_576CVBS: - case MODE_PAL_M: - case MODE_PAL_N: - cvbs_out_reg_write(ENCI_TST_CLRBAR_STRT, 0x112); - cvbs_out_reg_write(ENCI_TST_CLRBAR_WIDTH, 0xb4); - cvbs_out_reg_write(ENCI_TST_MDSEL, (unsigned int)num); - cvbs_out_reg_write(ENCI_TST_EN, 1); - break; - default: - start = cvbs_out_reg_read(ENCP_VIDEO_HAVON_BEGIN); - width = info->vinfo->width / 9; - cvbs_out_reg_write(VENC_VIDEO_TST_CLRBAR_STRT, start); - cvbs_out_reg_write(VENC_VIDEO_TST_CLRBAR_WIDTH, width); - cvbs_out_reg_write(VENC_VIDEO_TST_MDSEL, 1); - cvbs_out_reg_setb(ENCP_VIDEO_MODE_ADV, 0, 3, 1); - cvbs_out_reg_write(VENC_VIDEO_TST_EN, 1); - break; - } - pr_info("show bist pattern %ld: %s\n", - num, cvbs_out_bist_str[num]); - } -} - static void vdac_power_level_store(char *para) { unsigned long level = 0; @@ -956,7 +996,7 @@ static void cvbs_debug_store(char *buf) { unsigned int ret = 0; unsigned long addr, start, end, value, length, old; - unsigned int argc; + unsigned int argc, bist; char *p = NULL, *para = NULL, *argv[6] = {NULL, NULL, NULL, NULL, NULL, NULL}; char *str_type = NULL; @@ -1129,11 +1169,16 @@ static void cvbs_debug_store(char *buf) case CMD_BIST: if (argc != 2) { print_info("[%s] cmd_bist format:\n" - "\tbist 0/1/2/3/off\n", __func__); + "\tbist 1/2/3/4/5/6/7/8/0\n", __func__); goto DEBUG_END; } + ret = kstrtouint(argv[1], 10, &bist); + if (ret) { + print_info("cvbs: invalid bist\n"); + goto DEBUG_END; + } + cvbs_bist_test(bist); - bist_test_store(argv[1]); break; case CMD_VP_SET: diff --git a/drivers/amlogic/media/vout/cvbs/cvbs_out.h b/drivers/amlogic/media/vout/cvbs/cvbs_out.h index 2e8e32c5e6ab..79f803caedaf 100644 --- a/drivers/amlogic/media/vout/cvbs/cvbs_out.h +++ b/drivers/amlogic/media/vout/cvbs/cvbs_out.h @@ -25,7 +25,7 @@ #include #include "cvbs_mode.h" -#define CVBSOUT_VER "Ref.2018/07/02" +#define CVBSOUT_VER "Ref.2018/11/07" #define CVBS_CLASS_NAME "cvbs" #define CVBS_NAME "cvbs" @@ -97,5 +97,6 @@ struct cvbsregs_set_t { const struct reg_s *enc_reg_setting; }; +extern void amvecm_clip_range_limit(bool limit_en); #endif diff --git a/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hdmi_tx_edid.c b/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hdmi_tx_edid.c index a77e7f85a85c..4c58c3e1039d 100644 --- a/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hdmi_tx_edid.c +++ b/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hdmi_tx_edid.c @@ -305,14 +305,16 @@ int Edid_Parse_check_HDMI_VSDB(struct hdmitx_dev *hdev, } set_vsdb_phy_addr(hdev, &info->vsdb_phy_addr, &buff[BlockAddr]); - if ((check_fbc_special(&hdev->EDID_buf[0])) || - (check_fbc_special(&hdev->EDID_buf1[0]))) - rx_edid_physical_addr(0, 0, 0, 0); - else - rx_edid_physical_addr(info->vsdb_phy_addr.a, - info->vsdb_phy_addr.b, - info->vsdb_phy_addr.c, - info->vsdb_phy_addr.d); + if (hdev->repeater_tx) { + if ((check_fbc_special(&hdev->EDID_buf[0])) || + (check_fbc_special(&hdev->EDID_buf1[0]))) + rx_edid_physical_addr(0, 0, 0, 0); + else + rx_edid_physical_addr(info->vsdb_phy_addr.a, + info->vsdb_phy_addr.b, + info->vsdb_phy_addr.c, + info->vsdb_phy_addr.d); + } if (temp_addr >= VSpecificBoundary) ret = -1; @@ -797,11 +799,15 @@ static void Edid_ParsingVendSpec(struct rx_cap *pRXCap, } if (ieeeoui != DV_IEEE_OUI) { - dv->block_flag = ERROR_LENGTH; + dv->block_flag = ERROR_OUI; return; } dv->ieeeoui = ieeeoui; dv->ver = (dat[pos] >> 5) & 0x7; + if ((dv->ver) > 2) { + dv->block_flag = ERROR_VER; + return; + } /* Refer to DV 2.9 Page 27 */ if (dv->ver == 0) { if (dv->length == 0x19) { @@ -1203,18 +1209,15 @@ static void Edid_Y420CMDB_Reset(struct hdmitx_info *info) memset(info->y420cmdb_bitmap, 0x00, Y420CMDB_MAX); } -static char *rptx_edid_aud; -static char rptx_edid_buf[512]; -MODULE_PARM_DESC(rptx_edid_aud, "\n receive_edid\n"); -module_param(rptx_edid_aud, charp, 0444); - /* ----------------------------------------------------------- */ int Edid_ParsingCEADataBlockCollection(struct hdmitx_dev *hdmitx_device, unsigned char *buff) { unsigned char AddrTag, D, Addr, Data; - int temp_addr, i, len, pos; + int temp_addr; + int len; struct hdmitx_info *info = &(hdmitx_device->hdmi_info); + struct rx_cap *pRXCap = &hdmitx_device->RXCap; /* Byte number offset d where Detailed Timing data begins */ D = buff[2]; @@ -1225,22 +1228,29 @@ int Edid_ParsingCEADataBlockCollection(struct hdmitx_dev *hdmitx_device, Data = buff[AddrTag]; switch (Data&0xE0) { case VIDEO_TAG: - if ((Addr + (Data&0x1f)) < D) + if ((Addr + (Data&0x1f)) < D) { Edid_ParsingVideoDATABlock(info, buff, Addr + 1, (Data & 0x1F)); + len = (Data & 0x1f) + 1; + if ((pRXCap->vsd.len + len) > MAX_RAW_LEN) + break; + memcpy(&pRXCap->vsd.raw[pRXCap->vsd.len], + &buff[AddrTag], len); + pRXCap->vsd.len += len; + } break; case AUDIO_TAG: - len = (Data & 0x1f) + 1; - if (hdmitx_device->repeater_tx) - rx_set_receiver_edid(&buff[AddrTag], len); - for (pos = 0, i = 0; i < len; i++) - pos += sprintf(rptx_edid_buf+pos, "%02x", - buff[AddrTag + i]); - rptx_edid_buf[pos + 1] = 0; + /* rx_set_receiver_edid(&buff[AddrTag], len); */ if ((Addr + (Data&0x1f)) < D) Edid_ParsingAudioDATABlock(info, buff, Addr + 1, (Data & 0x1F)); + len = (Data & 0x1f) + 1; + if ((pRXCap->asd.len + len) > MAX_RAW_LEN) + break; + memcpy(&pRXCap->asd.raw[pRXCap->asd.len], + &buff[AddrTag], len); + pRXCap->asd.len += len; break; case SPEAKER_TAG: @@ -1965,10 +1975,12 @@ int hdmitx_edid_parse(struct hdmitx_dev *hdmitx_device) EDID_MAX_BLOCK * 128); } else EDID_buf = hdmitx_device->EDID_buf1; + + if (check_dvi_hdmi_edid_valid(hdmitx_device->EDID_buf1)) + hdmitx_device->edid_parsing = 1; + hdmitx_device->edid_ptr = EDID_buf; pr_info(EDID "EDID Parser:\n"); - memset(rptx_edid_buf, 0, sizeof(rptx_edid_buf)); - rptx_edid_aud = &rptx_edid_buf[0]; /* Calculate the EDID hash for special use */ memset(hdmitx_device->EDID_hash, 0, ARRAY_SIZE(hdmitx_device->EDID_hash)); @@ -2293,9 +2305,6 @@ bool hdmitx_edid_check_valid_mode(struct hdmitx_dev *hdev, (para->cs == COLORSPACE_YUV444)) if (para->cd != COLORDEPTH_24B) return 0; - if (para->cs == COLORSPACE_YUV422) - if (para->cd != COLORDEPTH_48B) - return 0; break; case HDMI_720x480i60_16x9: case HDMI_720x576i50_16x9: diff --git a/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hdmi_tx_hdcp.h b/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hdmi_tx_hdcp.h index ae39f444eff9..88c2b6ff42b1 100644 --- a/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hdmi_tx_hdcp.h +++ b/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hdmi_tx_hdcp.h @@ -27,7 +27,6 @@ * other devices */ extern int hdcp_ksv_valid(unsigned char *dat); -extern unsigned int hdcp_get_downstream_ver(void); #endif diff --git a/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hdmi_tx_main.c b/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hdmi_tx_main.c index 756ce6c3056c..e9e142d98c8c 100644 --- a/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hdmi_tx_main.c +++ b/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hdmi_tx_main.c @@ -47,6 +47,7 @@ #include #include +#include #include #include #ifdef CONFIG_AMLOGIC_SND_SOC @@ -118,13 +119,9 @@ static inline void hdmitx_notify_hpd(int hpd) #include static void hdmitx_early_suspend(struct early_suspend *h) { - const struct vinfo_s *info = hdmitx_get_current_vinfo(); struct hdmitx_dev *phdmi = (struct hdmitx_dev *)h->param; - if (info && (strncmp(info->name, "panel", 5) == 0 - || strncmp(info->name, "null", 4) == 0)) - return; - + phdmi->ready = 0; phdmi->hpd_lock = 1; msleep(20); phdmi->HWOp.CntlMisc(phdmi, MISC_AVMUTE_OP, SET_AVMUTE); @@ -168,48 +165,36 @@ static void hdmitx_late_resume(struct early_suspend *h) if (phdmi->hdmitx_clk_tree.hdmi_clk_vpu != NULL) clk_prepare_enable(phdmi->hdmitx_clk_tree.hdmi_clk_vpu); - if ((info == NULL) || (info->name == NULL)) { - pr_info(SYS "vinfo is NULL\n"); - return; - } + if (info && (hdmitx_is_hdmi_vmode(info->name) == 1)) + phdmi->HWOp.CntlMisc(&hdmitx_device, MISC_HPLL_FAKE, 0); - if (strncmp(info->name, "panel", 5) == 0 || - strncmp(info->name, "null", 4) == 0) { - ; - } else { - if (hdmitx_is_hdmi_vmode(info->name) == 1) - phdmi->HWOp.CntlMisc(&hdmitx_device, MISC_HPLL_FAKE, 0); + phdmi->hpd_lock = 0; - phdmi->hpd_lock = 0; - - /* update status for hpd and switch/state */ - hdmitx_device.hpd_state = - !!(hdmitx_device.HWOp.CntlMisc(&hdmitx_device, + /* update status for hpd and switch/state */ + hdmitx_device.hpd_state = !!(hdmitx_device.HWOp.CntlMisc(&hdmitx_device, MISC_HPD_GPI_ST, 0)); - pr_info("hdmitx hpd state: %d\n", hdmitx_device.hpd_state); - hdmitx_notify_hpd(hdmitx_device.hpd_state); + pr_info("hdmitx hpd state: %d\n", hdmitx_device.hpd_state); + hdmitx_notify_hpd(hdmitx_device.hpd_state); - /*force to get EDID after resume for Amplifer Power case*/ - if (hdmitx_device.hpd_state) - hdmitx_get_edid(phdmi); + /*force to get EDID after resume for Amplifer Power case*/ + if (hdmitx_device.hpd_state) + hdmitx_get_edid(phdmi); - hdmitx_device.HWOp.CntlConfig(&hdmitx_device, - CONF_AUDIO_MUTE_OP, AUDIO_MUTE); - set_disp_mode_auto(); + hdmitx_device.HWOp.CntlConfig(&hdmitx_device, + CONF_AUDIO_MUTE_OP, AUDIO_MUTE); + set_disp_mode_auto(); - extcon_set_state_sync(hdmitx_extcon_hdmi, EXTCON_DISP_HDMI, - hdmitx_device.hpd_state); - extcon_set_state_sync(hdmitx_extcon_power, EXTCON_DISP_HDMI, - hdmitx_device.hpd_state); - extcon_set_state_sync(hdmitx_extcon_audio, EXTCON_DISP_HDMI, - hdmitx_device.hpd_state); + extcon_set_state_sync(hdmitx_extcon_hdmi, EXTCON_DISP_HDMI, + hdmitx_device.hpd_state); + extcon_set_state_sync(hdmitx_extcon_power, EXTCON_DISP_HDMI, 1); + extcon_set_state_sync(hdmitx_extcon_audio, EXTCON_DISP_HDMI, + hdmitx_device.hpd_state); - pr_info("amhdmitx: late resume module %d\n", __LINE__); - phdmi->HWOp.Cntl((struct hdmitx_dev *)h->param, - HDMITX_EARLY_SUSPEND_RESUME_CNTL, HDMITX_LATE_RESUME); - pr_info(SYS "late resume\n"); - } + pr_info("amhdmitx: late resume module %d\n", __LINE__); + phdmi->HWOp.Cntl((struct hdmitx_dev *)h->param, + HDMITX_EARLY_SUSPEND_RESUME_CNTL, HDMITX_LATE_RESUME); + pr_info(SYS "late resume\n"); } /* Set avmute_set signal to HDMIRX */ @@ -218,6 +203,7 @@ static int hdmitx_reboot_notifier(struct notifier_block *nb, { struct hdmitx_dev *hdev = container_of(nb, struct hdmitx_dev, nb); + hdev->ready = 0; hdev->HWOp.CntlMisc(hdev, MISC_AVMUTE_OP, SET_AVMUTE); mdelay(100); hdev->HWOp.CntlMisc(hdev, MISC_TMDS_PHY_OP, TMDS_PHY_DISABLE); @@ -447,6 +433,7 @@ static int set_disp_mode_auto(void) hdev, STAT_VIDEO_VIC, 0); memset(mode, 0, sizeof(mode)); + hdev->ready = 0; /* get current vinfo */ info = hdmitx_get_current_vinfo(); @@ -633,6 +620,83 @@ void setup_attr(const char *buf) } EXPORT_SYMBOL(setup_attr); + +/* for android application data exchange / swap */ +static char *tmp_swap; +static DEFINE_MUTEX(mutex_swap); + +static ssize_t store_swap(struct device *dev, + struct device_attribute *attr, const char *buf, size_t count) +{ + pr_info("store_swap: %s\n", buf); + mutex_lock(&mutex_swap); + + kfree(tmp_swap); + tmp_swap = kzalloc(count + 1, GFP_KERNEL); + if (!tmp_swap) { + mutex_unlock(&mutex_swap); + return count; + } + memcpy(tmp_swap, buf, count); + tmp_swap[count] = '\0'; /* padding end string */ + mutex_unlock(&mutex_swap); + return count; +} + +static ssize_t show_swap(struct device *dev, + struct device_attribute *attr, char *buf) +{ + int i = 0; + int n = 0; + struct hdmitx_dev *hdev = &hdmitx_device; + struct rx_cap *pRXCap = &hdev->RXCap; + struct hdcprp14_topo *topo14 = &hdev->topo_info->topo.topo14; + + mutex_lock(&mutex_swap); + + if (!tmp_swap || + (!hdev->edid_parsing && !strstr(tmp_swap, "hdcp.topo"))) { + mutex_unlock(&mutex_swap); + return n; + } + + /* VSD: Video Short Descriptor */ + if (strstr(tmp_swap, "edid.vsd")) + for (i = 0; i < pRXCap->vsd.len; i++) + n += snprintf(buf + n, PAGE_SIZE - n, "%02x", + pRXCap->vsd.raw[i]); + /* ASD: Audio Short Descriptor */ + if (strstr(tmp_swap, "edid.asd")) + for (i = 0; i < pRXCap->asd.len; i++) + n += snprintf(buf + n, PAGE_SIZE - n, "%02x", + pRXCap->asd.raw[i]); + /* CEC: Physical Address */ + if (strstr(tmp_swap, "edid.cec")) + n += snprintf(buf + n, PAGE_SIZE - n, "%x%x%x%x", + hdev->hdmi_info.vsdb_phy_addr.a, + hdev->hdmi_info.vsdb_phy_addr.b, + hdev->hdmi_info.vsdb_phy_addr.c, + hdev->hdmi_info.vsdb_phy_addr.d); + /* HDCP TOPO */ + if (strstr(tmp_swap, "hdcp.topo")) { + char *tmp = (char *)topo14; + + pr_info("max_cascade_exceeded %d\n", + topo14->max_cascade_exceeded); + pr_info("depth %d\n", topo14->depth); + pr_info("max_devs_exceeded %d\n", topo14->max_devs_exceeded); + pr_info("device_count %d\n", topo14->device_count); + for (i = 0; i < sizeof(struct hdcprp14_topo); i++) + n += snprintf(buf + n, PAGE_SIZE - n, "%02x", tmp[i]); + } + + kfree(tmp_swap); + tmp_swap = NULL; + + mutex_unlock(&mutex_swap); + return n; +} + static ssize_t show_aud_mode(struct device *dev, struct device_attribute *attr, char *buf) { @@ -1268,6 +1332,9 @@ static void hdmitx_set_drm_pkt(struct master_display_info_s *data) hdev->hdmi_current_hdr_mode = 3; } + hdev->HWOp.CntlConfig(hdev, CONF_AVI_Q01, + RGB_RANGE_LIM); + switch (hdev->hdmi_current_hdr_mode) { case 1: /*standard HDR*/ @@ -2102,7 +2169,7 @@ static int is_4k50_fmt(char *mode) "2160p50hz", "2160p60hz", "smpte50hz", - "smpte50hz", + "smpte60hz", NULL }; @@ -2113,6 +2180,33 @@ static int is_4k50_fmt(char *mode) return 0; } +static int is_4k_fmt(char *mode) +{ + int i; + static char const *hdmi4k[] = { + "2160p", + "smpte", + NULL + }; + + for (i = 0; hdmi4k[i]; i++) { + if (strstr(mode, hdmi4k[i])) + return 1; + } + return 0; +} + +/* below items has feature limited, may need extra judgement */ +static bool hdmitx_limited_1080p(void) +{ + if (is_meson_gxl_package_805X()) + return 1; + else if (is_meson_gxl_package_805Y()) + return 1; + else + return 0; +} + /**/ static ssize_t show_disp_cap(struct device *dev, struct device_attribute *attr, char *buf) @@ -2129,6 +2223,8 @@ static ssize_t show_disp_cap(struct device *dev, for (i = 0; disp_mode_t[i]; i++) { memset(mode_tmp, 0, sizeof(mode_tmp)); strncpy(mode_tmp, disp_mode_t[i], 31); + if (hdmitx_limited_1080p() && is_4k_fmt(mode_tmp)) + continue; vic = hdmitx_edid_get_VIC(&hdmitx_device, mode_tmp, 0); /* Handling only 4k420 mode */ if (vic == HDMI_Unknown) { @@ -2596,24 +2692,53 @@ static ssize_t store_avmute(struct device *dev, struct device_attribute *attr, const char *buf, size_t count) { int cmd = OFF_AVMUTE; + static int mask0; + static int mask1; + static DEFINE_MUTEX(avmute_mutex); - if (strncmp(buf, "-1", 2) == 0) + pr_info("store_avmute %s\n", buf); + mutex_lock(&avmute_mutex); + if (strncmp(buf, "-1", 2) == 0) { cmd = CLR_AVMUTE; - else if (strncmp(buf, "0", 1) == 0) + mask0 = -1; + } else if (strncmp(buf, "0", 1) == 0) { cmd = OFF_AVMUTE; - else if (strncmp(buf, "1", 1) == 0) + mask0 = 0; + } else if (strncmp(buf, "1", 1) == 0) { cmd = SET_AVMUTE; - else - pr_info(SYS "set avmute wrong: %s\n", buf); - + mask0 = 1; + } + if (strncmp(buf, "r-1", 3) == 0) { + cmd = CLR_AVMUTE; + mask1 = -1; + } else if (strncmp(buf, "r0", 2) == 0) { + cmd = OFF_AVMUTE; + mask1 = 0; + } else if (strncmp(buf, "r1", 2) == 0) { + cmd = SET_AVMUTE; + mask1 = 1; + } + if ((mask0 == 1) || (mask1 == 1)) + cmd = SET_AVMUTE; + else if ((mask0 == -1) && (mask1 == -1)) + cmd = CLR_AVMUTE; hdmitx_device.HWOp.CntlMisc(&hdmitx_device, MISC_AVMUTE_OP, cmd); + mutex_unlock(&avmute_mutex); + return count; } static ssize_t show_avmute(struct device *dev, struct device_attribute *attr, char *buf) { - return 0; + struct hdmitx_dev *hdev = &hdmitx_device; + int ret = 0; + int pos = 0; + + ret = hdev->HWOp.CntlMisc(hdev, MISC_READ_AVMUTE_OP, 0); + pos += snprintf(buf + pos, PAGE_SIZE, "%d", ret); + + return pos; } /* @@ -2819,6 +2944,13 @@ static ssize_t show_hdcp_lstore(struct device *dev, { int pos = 0; + /* if current TX is RP-TX, then return lstore as 00 */ + /* hdcp_lstore is used under only TX */ + if (hdmitx_device.repeater_tx == 1) { + pos += snprintf(buf + pos, PAGE_SIZE, "00\n"); + return pos; + } + if (hdmitx_device.lstore < 0x10) { hdmitx_device.lstore = 0; if (hdmitx_device.HWOp.CntlDDC(&hdmitx_device, @@ -2853,6 +2985,53 @@ static ssize_t store_hdcp_lstore(struct device *dev, return count; } +static int rptxlstore; +static ssize_t show_hdcp_rptxlstore(struct device *dev, + struct device_attribute *attr, char *buf) +{ + int pos = 0; + + /* if current TX is not RP-TX, then return rptxlstore as 00 */ + /* hdcp_rptxlstore is used under only RP-TX */ + if (hdmitx_device.repeater_tx == 0) { + pos += snprintf(buf + pos, PAGE_SIZE, "00\n"); + return pos; + } + + if (rptxlstore < 0x10) { + rptxlstore = 0; + if (hdmitx_device.HWOp.CntlDDC(&hdmitx_device, + DDC_HDCP_14_LSTORE, 0)) + rptxlstore += 1; + if (hdmitx_device.HWOp.CntlDDC(&hdmitx_device, + DDC_HDCP_22_LSTORE, 0)) + rptxlstore += 2; + } + if (rptxlstore & 0x1) + pos += snprintf(buf + pos, PAGE_SIZE, "14\n"); + if (rptxlstore & 0x2) + pos += snprintf(buf + pos, PAGE_SIZE, "22\n"); + if ((rptxlstore & 0xf) == 0) + pos += snprintf(buf + pos, PAGE_SIZE, "00\n"); + return pos; +} + +static ssize_t store_hdcp_rptxlstore(struct device *dev, + struct device_attribute *attr, const char *buf, size_t count) +{ + pr_info("hdcp: set lstore as %s\n", buf); + if (strncmp(buf, "0", 1) == 0) + rptxlstore = 0x10; + if (strncmp(buf, "11", 2) == 0) + rptxlstore = 0x11; + if (strncmp(buf, "12", 2) == 0) + rptxlstore = 0x12; + if (strncmp(buf, "13", 2) == 0) + rptxlstore = 0x13; + + return count; +} + static ssize_t show_div40(struct device *dev, struct device_attribute *attr, char *buf) { @@ -2931,39 +3110,119 @@ static ssize_t store_hdcp_mode(struct device *dev, return count; } -void direct_hdcptx14_start(void) +static bool hdcp_sticky_mode; +static ssize_t show_hdcp_stickmode(struct device *dev, + struct device_attribute *attr, char *buf) { - pr_info("%s[%d]", __func__, __LINE__); - hdmitx_device.hdcp_mode = 1; - hdmitx_device.HWOp.CntlDDC(&hdmitx_device, - DDC_HDCP_OP, HDCP14_ON); -} -EXPORT_SYMBOL(direct_hdcptx14_start); + int pos = 0; -void direct_hdcptx14_stop(void) -{ - pr_info("%s[%d]", __func__, __LINE__); - hdmitx_device.HWOp.CntlDDC(&hdmitx_device, - DDC_HDCP_OP, HDCP14_OFF); + pos += snprintf(buf+pos, PAGE_SIZE, "%d\n", hdcp_sticky_mode); + + return pos; } -EXPORT_SYMBOL(direct_hdcptx14_stop); + +static ssize_t store_hdcp_stickmode(struct device *dev, + struct device_attribute *attr, const char *buf, size_t count) +{ + if (buf[0] == '0') + hdcp_sticky_mode = 0; + if (buf[0] == '1') + hdcp_sticky_mode = 1; + + return count; +} + +static unsigned char hdcp_sticky_step; +static ssize_t show_hdcp_stickstep(struct device *dev, + struct device_attribute *attr, char *buf) +{ + int pos = 0; + + pos += snprintf(buf+pos, PAGE_SIZE, "%x\n", hdcp_sticky_step); + if (hdcp_sticky_step) + hdcp_sticky_step = 0; + + return pos; +} + +static ssize_t store_hdcp_stickstep(struct device *dev, + struct device_attribute *attr, const char *buf, size_t count) +{ + if (isdigit(buf[0])) + hdcp_sticky_step = buf[0] - '0'; + + return count; +} + +/* Indicate whether a rptx under repeater */ +static ssize_t show_repeater_tx(struct device *dev, + struct device_attribute *attr, char *buf) +{ + int pos = 0; + + pos += snprintf(buf+pos, PAGE_SIZE, "%d\n", + !!hdmitx_device.repeater_tx); + + return pos; +} + +#include + +void direct_hdcptx14_opr(enum rptx_hdcp14_cmd cmd, void *args) +{ + int rst; + struct hdmitx_dev *hdev = &hdmitx_device; + + pr_info("%s[%d] cmd: %d\n", __func__, __LINE__, cmd); + switch (cmd) { + case RPTX_HDCP14_OFF: + hdev->hdcp_mode = 0; + hdev->HWOp.CntlDDC(hdev, DDC_HDCP_OP, HDCP14_OFF); + break; + case RPTX_HDCP14_ON: + hdev->hdcp_mode = 1; + hdev->HWOp.CntlDDC(hdev, DDC_HDCP_OP, HDCP14_ON); + break; + case RPTX_HDCP14_GET_AUTHST: + rst = hdev->HWOp.CntlDDC(hdev, DDC_HDCP_GET_AUTH, 0); + *(int *)args = rst; + break; + } +} +EXPORT_SYMBOL(direct_hdcptx14_opr); static ssize_t store_hdcp_ctrl(struct device *dev, struct device_attribute *attr, const char *buf, size_t count) { - if (hdmitx_device.HWOp.CntlDDC(&hdmitx_device, DDC_HDCP_14_LSTORE, - 0) == 0) + struct hdmitx_dev *hdev = &hdmitx_device; + + if (hdev->HWOp.CntlDDC(hdev, DDC_HDCP_14_LSTORE, 0) == 0) return count; - dev_warn(dev, "hdmitx20: %s\n", buf); + + /* for repeater */ + if (hdev->repeater_tx) { + dev_warn(dev, "hdmitx20: %s\n", buf); + if (strncmp(buf, "rstop", 5) == 0) { + if (strncmp(buf+5, "14", 2) == 0) + hdev->HWOp.CntlDDC(hdev, DDC_HDCP_OP, + HDCP14_OFF); + if (strncmp(buf+5, "22", 2) == 0) + hdev->HWOp.CntlDDC(hdev, DDC_HDCP_OP, + HDCP22_OFF); + hdev->hdcp_mode = 0; + hdmitx_hdcp_do_work(hdev); + } + return count; + } + /* for non repeater */ if (strncmp(buf, "stop", 4) == 0) { + dev_warn(dev, "hdmitx20: %s\n", buf); if (strncmp(buf+4, "14", 2) == 0) - hdmitx_device.HWOp.CntlDDC(&hdmitx_device, - DDC_HDCP_OP, HDCP14_OFF); + hdev->HWOp.CntlDDC(hdev, DDC_HDCP_OP, HDCP14_OFF); if (strncmp(buf+4, "22", 2) == 0) - hdmitx_device.HWOp.CntlDDC(&hdmitx_device, - DDC_HDCP_OP, HDCP22_OFF); - hdmitx_device.hdcp_mode = 0; - hdmitx_hdcp_do_work(&hdmitx_device); + hdev->HWOp.CntlDDC(hdev, DDC_HDCP_OP, HDCP22_OFF); + hdev->hdcp_mode = 0; + hdmitx_hdcp_do_work(hdev); } return count; @@ -3047,6 +3306,26 @@ static ssize_t show_hpd_state(struct device *dev, return pos; } + +static ssize_t show_rhpd_state(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct hdmitx_dev *hdev = &hdmitx_device; + int st; + + st = hdev->HWOp.CntlMisc(hdev, MISC_HPD_GPI_ST, 0); + + return snprintf(buf, PAGE_SIZE, "%d", hdev->rhpd_state); +} + +static ssize_t show_max_exceed_state(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct hdmitx_dev *hdev = &hdmitx_device; + + return snprintf(buf, PAGE_SIZE, "%d", hdev->hdcp_max_exceed_state); +} + static ssize_t show_hdmi_init(struct device *dev, struct device_attribute *attr, char *buf) { @@ -3105,6 +3384,7 @@ static DEVICE_ATTR(dc_cap, 0444, show_dc_cap, NULL); static DEVICE_ATTR(valid_mode, 0664, show_valid_mode, store_valid_mode); static DEVICE_ATTR(aud_ch, 0664, show_aud_ch, store_aud_ch); static DEVICE_ATTR(avmute, 0664, show_avmute, store_avmute); +static DEVICE_ATTR(swap, 0644, show_swap, store_swap); static DEVICE_ATTR(vic, 0664, show_vic, store_vic); static DEVICE_ATTR(phy, 0664, show_phy, store_phy); static DEVICE_ATTR(sspll, 0664, show_sspll, store_sspll); @@ -3116,11 +3396,18 @@ static DEVICE_ATTR(hdcp_pwr, 0664, show_hdcp_pwr, store_hdcp_pwr); static DEVICE_ATTR(hdcp_byp, 0200, NULL, store_hdcp_byp); static DEVICE_ATTR(hdcp_mode, 0664, show_hdcp_mode, store_hdcp_mode); static DEVICE_ATTR(hdcp_lstore, 0664, show_hdcp_lstore, store_hdcp_lstore); +static DEVICE_ATTR(hdcp_rptxlstore, 0664, show_hdcp_rptxlstore, + store_hdcp_rptxlstore); static DEVICE_ATTR(hdcp_repeater, 0644, show_hdcp_repeater, store_hdcp_repeater); static DEVICE_ATTR(hdcp_topo_info, 0644, show_hdcp_topo_info, store_hdcp_topo_info); static DEVICE_ATTR(hdcp22_type, 0644, show_hdcp22_type, store_hdcp22_type); +static DEVICE_ATTR(hdcp_stickmode, 0664, show_hdcp_stickmode, + store_hdcp_stickmode); +static DEVICE_ATTR(hdcp_stickstep, 0664, show_hdcp_stickstep, + store_hdcp_stickstep); +static DEVICE_ATTR(hdmi_repeater_tx, 0444, show_repeater_tx, NULL); static DEVICE_ATTR(hdcp22_base, 0444, show_hdcp22_base, NULL); static DEVICE_ATTR(div40, 0664, show_div40, store_div40); static DEVICE_ATTR(hdcp_ctrl, 0664, show_hdcp_ctrl, store_hdcp_ctrl); @@ -3128,6 +3415,8 @@ static DEVICE_ATTR(disp_cap_3d, 0444, show_disp_cap_3d, NULL); static DEVICE_ATTR(hdcp_ksv_info, 0444, show_hdcp_ksv_info, NULL); static DEVICE_ATTR(hdcp_ver, 0444, show_hdcp_ver, NULL); static DEVICE_ATTR(hpd_state, 0444, show_hpd_state, NULL); +static DEVICE_ATTR(rhpd_state, 0444, show_rhpd_state, NULL); +static DEVICE_ATTR(max_exceed, 0444, show_max_exceed_state, NULL); static DEVICE_ATTR(hdmi_init, 0444, show_hdmi_init, NULL); static DEVICE_ATTR(ready, 0664, show_ready, store_ready); static DEVICE_ATTR(support_3d, 0444, show_support_3d, NULL); @@ -3221,6 +3510,7 @@ static struct vout_server_s hdmitx_vout_server = { .set_state = hdmitx_vout_set_state, .clr_state = hdmitx_vout_clr_state, .get_state = hdmitx_vout_get_state, + .set_bist = NULL, #ifdef CONFIG_PM .vout_suspend = NULL, .vout_resume = NULL, @@ -3240,6 +3530,7 @@ static struct vout_server_s hdmitx_vout2_server = { .set_state = hdmitx_vout_set_state, .clr_state = hdmitx_vout_clr_state, .get_state = hdmitx_vout_get_state, + .set_bist = NULL, #ifdef CONFIG_PM .vout_suspend = NULL, .vout_resume = NULL, @@ -3451,9 +3742,11 @@ static void hdmitx_hpd_plugin_handler(struct work_struct *work) } mutex_lock(&setclk_mutex); pr_info(SYS "plugin\n"); + hdev->HWOp.CntlMisc(hdev, MISC_I2C_REACTIVE, 0); hdev->hdmitx_event &= ~HDMI_TX_HPD_PLUGIN; /* start reading E-EDID */ - rx_repeat_hpd_state(1); + if (hdev->repeater_tx) + rx_repeat_hpd_state(1); hdmitx_get_edid(hdev); hdmi_physcial_size_update(hdev); @@ -3478,7 +3771,6 @@ static void hdmitx_hpd_plugin_handler(struct work_struct *work) } mutex_lock(&getedid_mutex); - hdev->HWOp.CntlMisc(hdev, MISC_I2C_REACTIVE, 0); mutex_unlock(&getedid_mutex); if (hdev->repeater_tx) { if (check_fbc_special(&hdev->EDID_buf[0]) @@ -3486,7 +3778,6 @@ static void hdmitx_hpd_plugin_handler(struct work_struct *work) rx_set_repeater_support(0); else rx_set_repeater_support(1); - rx_repeat_hdcp_ver(hdcp_get_downstream_ver()); hdev->HWOp.CntlDDC(hdev, DDC_HDCP_GET_BKSV, (unsigned long int)bksv_buf); rx_set_receive_hdcp(bksv_buf, 1, 1, 0, 0); @@ -3539,7 +3830,8 @@ static void hdmitx_hpd_plugout_handler(struct work_struct *work) return; hdev->hdcp_mode = 0; hdev->hdcp_bcaps_repeater = 0; - + hdev->HWOp.CntlDDC(hdev, DDC_HDCP_MUX_INIT, 1); + hdev->HWOp.CntlDDC(hdev, DDC_HDCP_OP, HDCP14_OFF); mutex_lock(&setclk_mutex); pr_info(SYS "plugout\n"); if (!!(hdev->HWOp.CntlMisc(hdev, MISC_HPD_GPI_ST, 0))) { @@ -4011,6 +4303,14 @@ static int amhdmitx_get_dt_info(struct platform_device *pdev) pr_info(SYS "hdmitx_device.chip_type : %d\n", hdmitx_device.chip_type); + ret = of_property_read_u32(pdev->dev.of_node, + "repeater_tx", &val); + if (!ret) + hdmitx_device.repeater_tx = val; + if (hdmitx_device.repeater_tx == 1) + hdmitx_device.topo_info = kzalloc( + sizeof(*hdmitx_device.topo_info), GFP_KERNEL); + /* Get vendor information */ ret = of_property_read_u32(pdev->dev.of_node, "vend-data", &val); @@ -4202,6 +4502,7 @@ static int amhdmitx_probe(struct platform_device *pdev) ret = device_create_file(dev, &dev_attr_dv_cap); ret = device_create_file(dev, &dev_attr_aud_ch); ret = device_create_file(dev, &dev_attr_avmute); + ret = device_create_file(dev, &dev_attr_swap); ret = device_create_file(dev, &dev_attr_vic); ret = device_create_file(dev, &dev_attr_phy); ret = device_create_file(dev, &dev_attr_frac_rate_policy); @@ -4216,11 +4517,17 @@ static int amhdmitx_probe(struct platform_device *pdev) ret = device_create_file(dev, &dev_attr_hdcp_repeater); ret = device_create_file(dev, &dev_attr_hdcp_topo_info); ret = device_create_file(dev, &dev_attr_hdcp22_type); + ret = device_create_file(dev, &dev_attr_hdcp_stickmode); + ret = device_create_file(dev, &dev_attr_hdcp_stickstep); + ret = device_create_file(dev, &dev_attr_hdmi_repeater_tx); ret = device_create_file(dev, &dev_attr_hdcp22_base); ret = device_create_file(dev, &dev_attr_hdcp_lstore); + ret = device_create_file(dev, &dev_attr_hdcp_rptxlstore); ret = device_create_file(dev, &dev_attr_div40); ret = device_create_file(dev, &dev_attr_hdcp_ctrl); ret = device_create_file(dev, &dev_attr_hpd_state); + ret = device_create_file(dev, &dev_attr_rhpd_state); + ret = device_create_file(dev, &dev_attr_max_exceed); ret = device_create_file(dev, &dev_attr_hdmi_init); ret = device_create_file(dev, &dev_attr_ready); ret = device_create_file(dev, &dev_attr_support_3d); @@ -4296,6 +4603,8 @@ static int amhdmitx_remove(struct platform_device *pdev) device_remove_file(dev, &dev_attr_dc_cap); device_remove_file(dev, &dev_attr_valid_mode); device_remove_file(dev, &dev_attr_hpd_state); + device_remove_file(dev, &dev_attr_rhpd_state); + device_remove_file(dev, &dev_attr_max_exceed); device_remove_file(dev, &dev_attr_hdmi_init); device_remove_file(dev, &dev_attr_ready); device_remove_file(dev, &dev_attr_support_3d); @@ -4309,7 +4618,11 @@ static int amhdmitx_remove(struct platform_device *pdev) device_remove_file(dev, &dev_attr_hdcp_repeater); device_remove_file(dev, &dev_attr_hdcp_topo_info); device_remove_file(dev, &dev_attr_hdcp22_type); + device_remove_file(dev, &dev_attr_hdcp_stickmode); + device_remove_file(dev, &dev_attr_hdcp_stickstep); + device_remove_file(dev, &dev_attr_hdmi_repeater_tx); device_remove_file(dev, &dev_attr_hdcp22_base); + device_remove_file(dev, &dev_attr_swap); cdev_del(&hdmitx_device.cdev); diff --git a/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hdmi_tx_hw.c b/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hdmi_tx_hw.c index b3268c6a7d83..7a1a44b475c1 100644 --- a/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hdmi_tx_hw.c +++ b/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hdmi_tx_hw.c @@ -59,6 +59,14 @@ static void hdmitx_csc_config(unsigned char input_color_format, static int hdmitx_hdmi_dvi_config(struct hdmitx_dev *hdev, unsigned int dvi_mode); static void hdmitx_set_avi_colorimetry(struct hdmi_format_para *para); + +struct ksv_lists_ { + unsigned char valid; + unsigned int no; + unsigned char lists[MAX_KSV_LISTS * 5]; +}; +static struct ksv_lists_ tmp_ksv_lists; + static void hdmitx_set_packet(int type, unsigned char *DB, unsigned char *HB); static void hdmitx_setaudioinfoframe(unsigned char *AUD_DB, unsigned char *CHAN_STAT_BUF); @@ -269,6 +277,31 @@ static void config_avmute(unsigned int val) } } +static int read_avmute(void) +{ + int val; + int ret = 0; + + val = hdmitx_rd_reg(HDMITX_DWC_FC_GCP) & 0x3; + + switch (val) { + case 2: + ret = 1; + break; + case 1: + ret = -1; + break; + case 0: + ret = 0; + break; + default: + ret = 3; + break; + } + + return ret; +} + static void config_video_mapping(enum hdmi_color_space cs, enum hdmi_color_depth cd) { @@ -463,6 +496,8 @@ static void hdmi_hwp_init(struct hdmitx_dev *hdev) /* assign phy_clk_en = control[1]; */ /* Bring HDMITX MEM output of power down */ hd_set_reg_bits(P_HHI_MEM_PD_REG0, 0, 8, 8); + /* enable CLK_TO_DIG */ + hd_set_reg_bits(P_HHI_HDMI_PHY_CNTL3, 0x3, 0, 2); if (hdmitx_uboot_already_display()) { hdev->ready = 1; /* Get uboot output color space from AVI */ @@ -580,6 +615,10 @@ static void hdmi_hwi_init(struct hdmitx_dev *hdev) hdmitx_wr_reg(HDMITX_DWC_I2CM_SS_SCL_HCNT_0, 0xcf); hdmitx_wr_reg(HDMITX_DWC_I2CM_SS_SCL_LCNT_1, 0); hdmitx_wr_reg(HDMITX_DWC_I2CM_SS_SCL_LCNT_0, 0xff); + if (hdev->repeater_tx == 1) { + hdmitx_wr_reg(HDMITX_DWC_I2CM_SS_SCL_HCNT_0, 0x67); + hdmitx_wr_reg(HDMITX_DWC_I2CM_SS_SCL_LCNT_0, 0x78); + } hdmitx_wr_reg(HDMITX_DWC_I2CM_FS_SCL_HCNT_1, 0); hdmitx_wr_reg(HDMITX_DWC_I2CM_FS_SCL_HCNT_0, 0x0f); hdmitx_wr_reg(HDMITX_DWC_I2CM_FS_SCL_LCNT_1, 0); @@ -612,60 +651,63 @@ void HDMITX_Meson_Init(struct hdmitx_dev *hdev) hdmi_hwp_init(hdev); hdmi_hwi_init(hdev); hdev->HWOp.CntlMisc(hdev, MISC_AVMUTE_OP, CLR_AVMUTE); - rptx_ksvs = &rptx_ksv_prbuf[0]; } static irqreturn_t intr_handler(int irq, void *dev) { - unsigned int data32 = 0; + /* get interrupt status */ + unsigned int dat_top = hdmitx_rd_reg(HDMITX_TOP_INTR_STAT); + unsigned int dat_dwc = hdmitx_rd_reg(HDMITX_DWC_HDCP22REG_STAT); struct hdmitx_dev *hdev = (struct hdmitx_dev *)dev; - /* get interrupt status */ - data32 = hdmitx_rd_reg(HDMITX_TOP_INTR_STAT); - pr_info(HW "irq %x\n", data32); + /* ack INTERNAL_INTR or else we stuck with no interrupts at all */ + hdmitx_wr_reg(HDMITX_TOP_INTR_STAT_CLR, ~0); + hdmitx_wr_reg(HDMITX_DWC_HDCP22REG_STAT, 0xff); + + pr_info(SYS "irq %x\n", dat_top); + if (dat_dwc) + pr_info(SYS "irq %x\n", dat_dwc); if (hdev->hpd_lock == 1) { - hdmitx_wr_reg(HDMITX_TOP_INTR_STAT_CLR, 0xf); pr_info(HW "HDMI hpd locked\n"); goto next; } /* check HPD status */ - if ((data32 & (1 << 1)) && (data32 & (1 << 2))) { + if ((dat_top & (1 << 1)) && (dat_top & (1 << 2))) { if (hdmitx_hpd_hw_op(HPD_READ_HPD_GPIO)) - data32 &= ~(1 << 2); + dat_top &= ~(1 << 2); else - data32 &= ~(1 << 1); + dat_top &= ~(1 << 1); } /* HPD rising */ - if (data32 & (1 << 1)) { + if (dat_top & (1 << 1)) { hdev->hdmitx_event |= HDMI_TX_HPD_PLUGIN; hdev->hdmitx_event &= ~HDMI_TX_HPD_PLUGOUT; + hdev->rhpd_state = 1; queue_delayed_work(hdev->hdmi_wq, &hdev->work_hpd_plugin, HZ / 2); } /* HPD falling */ - if (data32 & (1 << 2)) { + if (dat_top & (1 << 2)) { queue_delayed_work(hdev->hdmi_wq, &hdev->work_aud_hpd_plug, 2 * HZ); hdev->hdmitx_event |= HDMI_TX_HPD_PLUGOUT; hdev->hdmitx_event &= ~HDMI_TX_HPD_PLUGIN; + hdev->rhpd_state = 0; queue_delayed_work(hdev->hdmi_wq, &hdev->work_hpd_plugout, HZ / 20); } -next: /* internal interrupt */ - if (data32 & (1 << 0)) { + if (dat_top & (1 << 0)) { hdev->hdmitx_event |= HDMI_TX_INTERNAL_INTR; queue_work(hdev->hdmi_wq, &hdev->work_internal_intr); } - if (data32 & (1 << 3)) { + if (dat_top & (1 << 3)) { unsigned int rd_nonce_mode = hdmitx_rd_reg(HDMITX_TOP_SKP_CNTL_STAT) & 0x1; pr_info(HW "hdcp22: Nonce %s Vld: %d\n", rd_nonce_mode ? "HW" : "SW", ((hdmitx_rd_reg(HDMITX_TOP_SKP_CNTL_STAT) >> 31) & 1)); - if (rd_nonce_mode) - hdmitx_wr_reg(HDMITX_TOP_INTR_STAT_CLR, (1 << 3)); - else { + if (!rd_nonce_mode) { hdmitx_wr_reg(HDMITX_TOP_NONCE_0, 0x32107654); hdmitx_wr_reg(HDMITX_TOP_NONCE_1, 0xba98fedc); hdmitx_wr_reg(HDMITX_TOP_NONCE_2, 0xcdef89ab); @@ -676,13 +718,10 @@ next: hdmitx_wr_reg(HDMITX_TOP_NONCE_3, 0x01234567); } } - if (data32 & (1 << 30)) { - pr_info(HW "hdcp22: reg stat: 0x%x\n", - hdmitx_rd_reg(HDMITX_DWC_HDCP22REG_STAT)); - hdmitx_wr_reg(HDMITX_DWC_HDCP22REG_STAT, 0xff); - } - /* ack INTERNAL_INTR or else we stuck with no interrupts at all */ - hdmitx_wr_reg(HDMITX_TOP_INTR_STAT_CLR, data32 | 0x7); + if (dat_top & (1 << 30)) + pr_info("hdcp22: reg stat: 0x%x\n", dat_dwc); + +next: return IRQ_HANDLED; } @@ -2628,8 +2667,14 @@ static void set_aud_samp_pkt(struct hdmitx_dev *hdev, } } +static int amute_flag = -1; static void audio_mute_op(bool flag) { + if (amute_flag != flag) + amute_flag = flag; + else + return; + if (flag == 0) { hdmitx_set_reg_bits(HDMITX_TOP_CLK_CNTL, 0, 2, 2); hdmitx_set_reg_bits(HDMITX_DWC_FC_PACKET_TX_EN, 0, 0, 1); @@ -4403,8 +4448,6 @@ static void hdmitx_read_edid(unsigned char *rx_edid) } } /* hdmi20_tx_read_edid */ -#define HDCP_NMOOFDEVICES 127 - static int get_hdcp_depth(void) { int ret; @@ -4453,68 +4496,54 @@ static int get_hdcp_device_count(void) return ret; } -static void get_hdcp_bstatus(void) +static void get_hdcp_bstatus(int *ret1, int *ret2) { - int ret1 = 0; - int ret2 = 0; - hdmitx_set_reg_bits(HDMITX_DWC_A_KSVMEMCTRL, 1, 0, 1); hdmitx_poll_reg(HDMITX_DWC_A_KSVMEMCTRL, (1<<1), 2 * HZ); - ret1 = hdmitx_rd_reg(HDMITX_DWC_HDCP_BSTATUS_0); - ret2 = hdmitx_rd_reg(HDMITX_DWC_HDCP_BSTATUS_1); + *ret1 = hdmitx_rd_reg(HDMITX_DWC_HDCP_BSTATUS_0); + *ret2 = hdmitx_rd_reg(HDMITX_DWC_HDCP_BSTATUS_1); hdmitx_set_reg_bits(HDMITX_DWC_A_KSVMEMCTRL, 0, 0, 1); - pr_info("BSTATUS0 = 0x%x BSTATUS1 = 0x%x\n", ret1, ret2); } -static void hdcp_ksv_store(unsigned char *dat, int no) +static void hdcp_ksv_store(struct hdcprp_topo *topo, + unsigned char *dat, int no) { int i; + int pos; - for (i = 0; i < no; i++) { - rptx_ksv_buf[rptx_ksv_no] = dat[i]; - rptx_ksv_no++; - } -} - -static void hdcp_ksv_print(void) -{ - unsigned int i, pos; - unsigned char *tmp_buf = NULL; - - tmp_buf = kmalloc(2000, GFP_ATOMIC); - if (!tmp_buf) + if (!topo) + return; + if (topo->hdcp_ver != 1) + return; + /* must check ksv num to prevent leak */ + if (topo->topo.topo14.device_count >= MAX_KSV_LISTS) return; - pos = 0; - memset(tmp_buf, 0, sizeof(2000)); - pos += sprintf(tmp_buf + pos, "Dump ksv test START\n"); - for (i = 0; (i < rptx_ksv_no) && (i < 635); i++) { - pos += sprintf(tmp_buf + pos, "%02x", rptx_ksv_buf[i]); - if (((i+1) % 40) == 0) /* print 40bytes a line */ - pos += sprintf(tmp_buf + pos, "\n"); - } - pos += sprintf(tmp_buf + pos, "\n"); - pos += sprintf(tmp_buf + pos, "Dump ksv test END\n"); - pr_info("%s\n", tmp_buf); - kfree(tmp_buf); + pos = topo->topo.topo14.device_count * 5; + for (i = 0; (i < no) && (i < MAX_KSV_LISTS * 5); i++) + topo->topo.topo14.ksv_list[pos++] = dat[i]; + topo->topo.topo14.device_count += no / 5; } static uint8_t *hdcp_mKsvListBuf; +static int ksv_sha_matched; static void hdcp_ksv_sha1_calc(struct hdmitx_dev *hdev) { size_t list = 0; size_t size = 0; size_t i = 0; int valid = HDCP_NULL; - unsigned char ksvs[635] = {0}; /* Max 127 * 5 */ + char temp[MAX_KSV_LISTS * 5]; int j = 0; /* 0x165e: Page 95 */ + memset(&tmp_ksv_lists, 0, sizeof(tmp_ksv_lists)); + memset(&temp[0], 0, sizeof(temp)); hdcp_mKsvListBuf = kmalloc(0x1660, GFP_ATOMIC); if (hdcp_mKsvListBuf) { /* KSV_SIZE; */ list = hdmitx_rd_reg(HDMITX_DWC_HDCP_BSTATUS_0) & KSV_MASK; - if (list <= HDCP_NMOOFDEVICES) { + if (list <= MAX_KSV_LISTS) { size = (list * KSV_SIZE) + HDCP_HEAD + SHA_MAX_SIZE; for (i = 0; i < size; i++) { if (i < HDCP_HEAD) { /* BSTATUS & M0 */ @@ -4527,9 +4556,11 @@ static void hdcp_ksv_sha1_calc(struct hdmitx_dev *hdev) hdcp_mKsvListBuf[i - HDCP_HEAD] = hdmitx_rd_reg( HDMITX_DWC_HDCP_BSTATUS_0 + i); - ksvs[j] = + tmp_ksv_lists.lists[tmp_ksv_lists.no++] + = hdcp_mKsvListBuf[i - + HDCP_HEAD]; + temp[j++] = hdcp_mKsvListBuf[i - HDCP_HEAD]; - j++; } else { /* SHA */ hdcp_mKsvListBuf[i] = hdmitx_rd_reg( HDMITX_DWC_HDCP_BSTATUS_0 + i); @@ -4539,12 +4570,18 @@ static void hdcp_ksv_sha1_calc(struct hdmitx_dev *hdev) valid = HDCP_KSVLIST_VALID; else valid = HDCP_KSVLIST_INVALID; + ksv_sha_matched = valid; } hdmitx_set_reg_bits(HDMITX_DWC_A_KSVMEMCTRL, 0, 0, 1); hdmitx_set_reg_bits(HDMITX_DWC_A_KSVMEMCTRL, (valid == HDCP_KSVLIST_VALID) ? 0 : 1, 3, 1); - if (valid == HDCP_KSVLIST_VALID) - hdcp_ksv_store(ksvs, j); + if (valid == HDCP_KSVLIST_VALID) { + tmp_ksv_lists.valid = 1; + for (i = 0; (i < j) && + (tmp_ksv_lists.no < MAX_KSV_LISTS * 5); i++) + tmp_ksv_lists.lists[tmp_ksv_lists.no++] + = temp[i]; + } hdmitx_set_reg_bits(HDMITX_DWC_A_KSVMEMCTRL, 1, 2, 1); hdmitx_set_reg_bits(HDMITX_DWC_A_KSVMEMCTRL, 0, 2, 1); kfree(hdcp_mKsvListBuf); @@ -4552,43 +4589,98 @@ static void hdcp_ksv_sha1_calc(struct hdmitx_dev *hdev) pr_info("hdcptx14: KSV List memory not valid\n"); } +static int max_exceed = 200; +MODULE_PARM_DESC(max_exceed, "\nmax_exceed\n"); +module_param(max_exceed, int, 0664); + static void hdcptx_events_handle(unsigned long arg) { struct hdmitx_dev *hdev = (struct hdmitx_dev *)arg; unsigned char ksv[5] = {0}; - int pos, i; + int i; unsigned int bcaps_6_rp; + static unsigned int bcaps_5_ksvfifoready; static unsigned int st_flag = -1; + static unsigned int hdcpobs3_1; + unsigned int hdcpobs3_2; + struct hdcprp14_topo *topo14 = &hdev->topo_info->topo.topo14; + int bstatus0 = 0; + int bstatus1 = 0; + + if (hdev->hdcp_max_exceed_cnt == 0) { + hdcpobs3_1 = 0; + bcaps_5_ksvfifoready = 0; + } + + hdcpobs3_2 = hdmitx_rd_reg(HDMITX_DWC_A_HDCPOBS3); + if (hdcpobs3_1 != hdcpobs3_2) + hdcpobs3_1 = hdcpobs3_2; + + bcaps_6_rp = !!(hdcpobs3_1 & (1 << 6)); + bcaps_5_ksvfifoready = !!(hdcpobs3_1 & (1 << 5)); + + if (bcaps_6_rp && bcaps_5_ksvfifoready + && (hdev->hdcp_max_exceed_cnt == 0)) + hdev->hdcp_max_exceed_cnt++; + if (hdev->hdcp_max_exceed_cnt) + hdev->hdcp_max_exceed_cnt++; + if (bcaps_6_rp && bcaps_5_ksvfifoready) { + if ((hdev->hdcp_max_exceed_cnt > max_exceed) + && !ksv_sha_matched) { + topo14->max_devs_exceeded = 1; + topo14->max_cascade_exceeded = 1; + hdev->hdcp_max_exceed_state = 1; + } + } - bcaps_6_rp = !!(hdmitx_rd_reg(HDMITX_DWC_A_HDCPOBS3) & (1 << 6)); if (st_flag != hdmitx_rd_reg(HDMITX_DWC_A_APIINTSTAT)) { st_flag = hdmitx_rd_reg(HDMITX_DWC_A_APIINTSTAT); pr_info("hdcp14: instat: 0x%x\n", st_flag); } + + if (st_flag & (1 << 6)) { + hdmitx_set_reg_bits(HDMITX_DWC_A_HDCPCFG1, 1, 1, 1); + } if (st_flag & (1 << 7)) { hdmitx_wr_reg(HDMITX_DWC_A_APIINTCLR, 1 << 7); hdmitx_hdcp_opr(3); + if (bcaps_6_rp) + get_hdcp_bstatus(&bstatus0, &bstatus1); for (i = 0; i < 5; i++) ksv[i] = (unsigned char) hdmitx_rd_reg(HDMITX_DWC_HDCPREG_BKSV0 + i); - hdcp_ksv_store(ksv, 5); - get_hdcp_bstatus(); - if (hdev->repeater_tx) { - rx_set_receive_hdcp(rptx_ksv_buf, (rptx_ksv_no + 1) / 5, - (bcaps_6_rp ? get_hdcp_depth() : 0) + 1, - bcaps_6_rp ? get_hdcp_max_cascade() : 0, - bcaps_6_rp ? get_hdcp_max_devs() : 0); - pr_info("%s[%d] ksvs Num = %d device_count = %d\n", - __func__, __LINE__, - (rptx_ksv_no + 1) / 5, - bcaps_6_rp ? get_hdcp_device_count() : 0); - memset(rptx_ksv_prbuf, 0, sizeof(rptx_ksv_prbuf)); - for (pos = 0, i = 0; i < rptx_ksv_no; i++) - pos += sprintf(rptx_ksv_prbuf + pos, - "%02x", rptx_ksv_buf[i]); - rptx_ksv_prbuf[pos + 1] = '\0'; - if (1) - hdcp_ksv_print(); + /* if downstream is only RX */ + if ((hdev->repeater_tx == 1) && hdev->topo_info) { + hdcp_ksv_store(hdev->topo_info, ksv, 5); + if (tmp_ksv_lists.valid) { + int cnt = get_hdcp_device_count(); + int devs = get_hdcp_max_devs(); + int cascade = get_hdcp_max_cascade(); + int depth = get_hdcp_depth(); + + hdcp_ksv_store(hdev->topo_info, + tmp_ksv_lists.lists, tmp_ksv_lists.no); + if (cnt >= 127) { + topo14->device_count = 127; + topo14->max_devs_exceeded = 1; + } else { + topo14->device_count = cnt + 1; + topo14->max_devs_exceeded = devs; + } + + if (depth >= 7) { + topo14->depth = 7; + topo14->max_cascade_exceeded = 1; + } else { + topo14->depth = depth + 1; + topo14->max_cascade_exceeded = cascade; + } + } else { + topo14->device_count = 1; + topo14->max_devs_exceeded = 0; + topo14->max_cascade_exceeded = 0; + topo14->depth = 1; + } } } if (st_flag & (1 << 1)) { @@ -4602,30 +4694,8 @@ static void hdcptx_events_handle(unsigned long arg) return; } hdmitx_wr_reg(HDMITX_DWC_A_KSVMEMCTRL, 0x4); - if (hdev->repeater_tx) { - rptx_ksvlist_retry++; - if (rptx_ksvlist_retry % 4 == 0) { - for (i = 0; i < 5; i++) - ksv[i] = (unsigned char) hdmitx_rd_reg( - HDMITX_DWC_HDCPREG_BKSV0 + i); - hdcp_ksv_store(ksv, 5); - rx_set_receive_hdcp(&ksv[0], 1, 127, 1, 1); - } - } } - if (hdev->repeater_tx && bcaps_6_rp && (get_hdcp_max_devs() || - get_hdcp_max_cascade())) { - for (i = 0; i < 5; i++) - ksv[i] = (unsigned char) - hdmitx_rd_reg(HDMITX_DWC_HDCPREG_BKSV0 + i); - hdcp_ksv_store(ksv, 5); - rx_set_receive_hdcp(&ksv[0], 1, 127, 1, 1); - } - if (hdev->hdcp_try_times) - mod_timer(&hdev->hdcp_timer, jiffies + HZ / 100); - else - return; - hdev->hdcp_try_times--; + mod_timer(&hdev->hdcp_timer, jiffies + HZ / 100); } static void hdcp_start_timer(struct hdmitx_dev *hdev) @@ -4639,10 +4709,8 @@ static void hdcp_start_timer(struct hdmitx_dev *hdev) hdev->hdcp_timer.function = hdcptx_events_handle; hdev->hdcp_timer.expires = jiffies + HZ / 100; add_timer(&hdev->hdcp_timer); - hdev->hdcp_try_times = 500; return; } - hdev->hdcp_try_times = 500; hdev->hdcp_timer.expires = jiffies + HZ / 100; mod_timer(&hdev->hdcp_timer, jiffies + HZ / 100); } @@ -4672,6 +4740,20 @@ static void set_pkf_duk_nonce(void) udelay(10); } +static void check_read_ksv_list_st(void) +{ + int cnt = 0; + + for (cnt = 0; cnt < 5; cnt++) { + if (((hdmitx_rd_reg(HDMITX_DWC_A_HDCPOBS1) & 0x7) == 5) || + ((hdmitx_rd_reg(HDMITX_DWC_A_HDCPOBS1) & 0x7) == 6)) + msleep(20); + else + return; + } + pr_info("hdcp14: FSM: A9 read ksv list\n"); +} + static int hdmitx_cntl_ddc(struct hdmitx_dev *hdev, unsigned int cmd, unsigned long argv) { @@ -4731,22 +4813,34 @@ static int hdmitx_cntl_ddc(struct hdmitx_dev *hdev, unsigned int cmd, } if (argv == 1) hdmitx_hdcp_opr(6); + if (argv == 3) + hdmitx_set_reg_bits(HDMITX_DWC_HDCP22REG_CTRL, 1, 2, 1); break; case DDC_HDCP_OP: + hdev->hdcp_max_exceed_state = 0; + hdev->hdcp_max_exceed_cnt = 0; + ksv_sha_matched = 0; + memset(&tmp_ksv_lists, 0, sizeof(tmp_ksv_lists)); + del_timer(&hdev->hdcp_timer); + if (hdev->topo_info) + memset(hdev->topo_info, 0, sizeof(*hdev->topo_info)); + if (argv == HDCP14_ON) { - rptx_ksvlist_retry = 0; - rptx_ksv_no = 0; - memset(rptx_ksv_buf, 0, sizeof(rptx_ksv_buf)); + check_read_ksv_list_st(); + if (hdev->topo_info) + hdev->topo_info->hdcp_ver = HDCPVER_14; hdmitx_ddc_hw_op(DDC_MUX_DDC); + hdmitx_set_reg_bits(HDMITX_TOP_SKP_CNTL_STAT, 0, 3, 1); + hdmitx_set_reg_bits(HDMITX_TOP_CLK_CNTL, 1, 31, 1); hdmitx_hdcp_opr(6); hdmitx_hdcp_opr(1); hdcp_start_timer(hdev); } - if (argv == HDCP14_OFF) { - rptx_ksvlist_retry = 0; + if (argv == HDCP14_OFF) hdmitx_hdcp_opr(4); - } if (argv == HDCP22_ON) { + if (hdev->topo_info) + hdev->topo_info->hdcp_ver = 2; hdmitx_ddc_hw_op(DDC_MUX_DDC); hdmitx_hdcp_opr(5); /* wait for start hdcp22app */ @@ -4754,6 +4848,9 @@ static int hdmitx_cntl_ddc(struct hdmitx_dev *hdev, unsigned int cmd, if (argv == HDCP22_OFF) hdmitx_hdcp_opr(6); break; + case DDC_IS_HDCP_ON: +/* argv = !!((hdmitx_rd_reg(TX_HDCP_MODE)) & (1 << 7)); */ + break; case DDC_HDCP_GET_BKSV: tmp_char = (unsigned char *) argv; for (i = 0; i < 5; i++) @@ -4962,6 +5059,8 @@ static int hdmitx_tmds_rxsense(void) static int hdmitx_cntl_misc(struct hdmitx_dev *hdev, unsigned int cmd, unsigned int argv) { + static int st; + if ((cmd & CMD_MISC_OFFSET) != CMD_MISC_OFFSET) { pr_err(HW "misc: w: invalid cmd 0x%x\n", cmd); return -1; @@ -5002,16 +5101,24 @@ static int hdmitx_cntl_misc(struct hdmitx_dev *hdev, unsigned int cmd, case MISC_AVMUTE_OP: config_avmute(argv); break; + case MISC_READ_AVMUTE_OP: + return read_avmute(); case MISC_HDCP_CLKDIS: + if (st != !!argv) { + st = !!argv; + pr_info("set hdcp clkdis: %d\n", !!argv); + } hdmitx_set_reg_bits(HDMITX_DWC_MC_CLKDIS, !!argv, 6, 1); break; case MISC_I2C_REACTIVE: + hdmitx_hdcp_opr(4); hdmitx_set_reg_bits(HDMITX_DWC_A_HDCPCFG1, 0, 0, 1); hdmitx_set_reg_bits(HDMITX_DWC_HDCP22REG_CTRL, 0, 2, 1); hdmitx_wr_reg(HDMITX_DWC_I2CM_SS_SCL_HCNT_1, 0xff); hdmitx_wr_reg(HDMITX_DWC_I2CM_SS_SCL_HCNT_0, 0xf6); edid_read_head_8bytes(); hdmi_hwi_init(hdev); + mdelay(5); break; default: break; @@ -5087,7 +5194,10 @@ static int hdmitx_get_state(struct hdmitx_dev *hdev, unsigned int cmd, static void hdmi_phy_suspend(void) { hd_write_reg(P_HHI_HDMI_PHY_CNTL0, 0x0); - hd_write_reg(P_HHI_HDMI_PHY_CNTL3, 0x0); + /* keep PHY_CNTL3 bit[1:0] as 0b11, + * otherwise may cause HDCP22 boot failed + */ + hd_write_reg(P_HHI_HDMI_PHY_CNTL3, 0x3); hd_write_reg(P_HHI_HDMI_PHY_CNTL5, 0x800); } @@ -5504,7 +5614,8 @@ static void config_hdmi20_tx(enum hdmi_vic vic, data32 |= (default_phase << 2); data32 |= (0 << 1); data32 |= (0 << 0); - hdmitx_wr_reg(HDMITX_DWC_FC_GCP, data32); + if (!hdev->repeater_tx) + hdmitx_wr_reg(HDMITX_DWC_FC_GCP, data32); /* write AVI Infoframe packet configuration */ data32 = 0; diff --git a/drivers/amlogic/media/vout/lcd/Makefile b/drivers/amlogic/media/vout/lcd/Makefile index 8018bfd471aa..c5dab0196ad2 100644 --- a/drivers/amlogic/media/vout/lcd/Makefile +++ b/drivers/amlogic/media/vout/lcd/Makefile @@ -1,4 +1,6 @@ -obj-$(CONFIG_AMLOGIC_LCD) += lcd_vout.o lcd_reg.o lcd_common.o lcd_notify.o lcd_debug.o lcd_clk_config.o lcd_unifykey.o +obj-$(CONFIG_AMLOGIC_LCD) += lcd_vout.o lcd_reg.o lcd_common.o lcd_notify.o \ + lcd_debug.o lcd_clk_config.o lcd_unifykey.o \ + lcd_tcon.o obj-$(CONFIG_AMLOGIC_LCD_TV) += lcd_tv/ obj-$(CONFIG_AMLOGIC_LCD_TABLET) += lcd_tablet/ obj-$(CONFIG_AMLOGIC_LCD_EXTERN) += lcd_extern/ diff --git a/drivers/amlogic/media/vout/lcd/lcd_clk_config.c b/drivers/amlogic/media/vout/lcd/lcd_clk_config.c index 2eea34cb6b63..98e693320662 100644 --- a/drivers/amlogic/media/vout/lcd/lcd_clk_config.c +++ b/drivers/amlogic/media/vout/lcd/lcd_clk_config.c @@ -24,70 +24,16 @@ #include #include #include -#include "lcd_reg.h" -#include "lcd_clk_config.h" #include #ifdef CONFIG_AMLOGIC_VPU #include #endif - +#include "lcd_reg.h" +#include "lcd_clk_config.h" +#include "lcd_clk_ctrl.h" static spinlock_t lcd_clk_lock; -static const unsigned int od_fb_table[2] = {1, 2}; - -static const unsigned int od_table[6] = { - 1, 2, 4, 8, 16, 32 -}; - -static const unsigned int div_pre_table[6] = { - 1, 2, 3, 4, 5, 6 -}; - -static char *lcd_clk_div_sel_table[] = { - "1", - "2", - "3", - "3.5", - "3.75", - "4", - "5", - "6", - "6.25", - "7", - "7.5", - "12", - "14", - "15", - "2.5", - "invalid", -}; - -static char *lcd_pll_ss_table_gxtvbb[] = { - "0, disable", - "1, +/-0.3%", - "2, +/-0.5%", - "3, +/-0.9%", - "4, +/-1.2%", -}; - -static char *lcd_pll_ss_table_txl[] = { - "0, disable", - "1, +/-0.3%", - "2, +/-0.4%", - "3, +/-0.9%", - "4, +/-1.2%", -}; - -static char *lcd_pll_ss_table_txlx[] = { - "0, disable", - "1, +/-0.3%", - "2, +/-0.5%", - "3, +/-1.0%", - "4, +/-1.6%", - "5, +/-3.0%", -}; - static struct lcd_clk_config_s clk_conf = { /* unit: kHz */ /* IN-OUT parameters */ .fin = FIN_FREQ, @@ -95,12 +41,13 @@ static struct lcd_clk_config_s clk_conf = { /* unit: kHz */ /* pll parameters */ .pll_mode = 0, /* txl */ - .od_fb = 0, + .pll_od_fb = 0, .pll_m = 0, .pll_n = 0, .pll_od1_sel = 0, .pll_od2_sel = 0, .pll_od3_sel = 0, + .pll_pi_div_sel = 0, /* for tcon */ .pll_level = 0, .ss_level = 0, .div_sel = 0, @@ -108,24 +55,26 @@ static struct lcd_clk_config_s clk_conf = { /* unit: kHz */ .pll_fout = 0, /* clk path node parameters */ - .pll_m_max = 0, - .pll_m_min = 0, - .pll_n_max = 0, - .pll_n_min = 0, - .pll_frac_range = 0, - .pll_od_sel_max = 0, - .ss_level_max = 0, .div_sel_max = 0, .xd_max = 0, - .pll_ref_fmax = 0, - .pll_ref_fmin = 0, - .pll_vco_fmax = 0, - .pll_vco_fmin = 0, - .pll_out_fmax = 0, - .pll_out_fmin = 0, - .div_in_fmax = 0, - .div_out_fmax = 0, - .xd_out_fmax = 0, + + .data = NULL, +}; + +static struct lcd_clktree_s lcd_clktree = { + .clk_gate_state = 0, + + .encl_top_gate = NULL, + .encl_int_gate = NULL, + + .dsi_host_gate = NULL, + .dsi_phy_gate = NULL, + .dsi_meas = NULL, + .mipi_enable_gate = NULL, + .mipi_bandgap_gate = NULL, + .gp0_pll = NULL, + .tcon_gate = NULL, + .tcon_clk = NULL, }; struct lcd_clk_config_s *get_lcd_clk_config(void) @@ -133,366 +82,10 @@ struct lcd_clk_config_s *get_lcd_clk_config(void) return &clk_conf; } -static void lcd_clk_config_init_print(void) -{ - struct aml_lcd_drv_s *lcd_drv = aml_lcd_get_driver(); - - switch (lcd_drv->data->chip_type) { - case LCD_CHIP_AXG: - case LCD_CHIP_G12A: - case LCD_CHIP_G12B: - LCDPR("lcd clk config init:\n" - "pll_m_max: %d\n" - "pll_m_min: %d\n" - "pll_n_max: %d\n" - "pll_n_min: %d\n" - "pll_frac_range: %d\n" - "pll_od_sel_max: %d\n" - "ss_level_max: %d\n" - "pll_ref_fmax: %d\n" - "pll_ref_fmin: %d\n" - "pll_vco_fmax: %d\n" - "pll_vco_fmin: %d\n" - "pll_out_fmax: %d\n" - "pll_out_fmin: %d\n" - "xd_out_fmax: %d\n\n", - clk_conf.pll_m_max, clk_conf.pll_m_min, - clk_conf.pll_n_max, clk_conf.pll_n_min, - clk_conf.pll_frac_range, - clk_conf.pll_od_sel_max, clk_conf.ss_level_max, - clk_conf.pll_ref_fmax, clk_conf.pll_ref_fmin, - clk_conf.pll_vco_fmax, clk_conf.pll_vco_fmin, - clk_conf.pll_out_fmax, clk_conf.pll_out_fmin, - clk_conf.xd_out_fmax); - break; - default: - LCDPR("lcd clk config:\n" - "pll_m_max: %d\n" - "pll_m_min: %d\n" - "pll_n_max: %d\n" - "pll_n_min: %d\n" - "pll_frac_range: %d\n" - "pll_od_sel_max: %d\n" - "ss_level_max: %d\n" - "pll_ref_fmax: %d\n" - "pll_ref_fmin: %d\n" - "pll_vco_fmax: %d\n" - "pll_vco_fmin: %d\n" - "pll_out_fmax: %d\n" - "pll_out_fmin: %d\n" - "div_in_fmax: %d\n" - "div_out_fmax: %d\n" - "xd_out_fmax: %d\n\n", - clk_conf.pll_m_max, clk_conf.pll_m_min, - clk_conf.pll_n_max, clk_conf.pll_n_min, - clk_conf.pll_frac_range, - clk_conf.pll_od_sel_max, clk_conf.ss_level_max, - clk_conf.pll_ref_fmax, clk_conf.pll_ref_fmin, - clk_conf.pll_vco_fmax, clk_conf.pll_vco_fmin, - clk_conf.pll_out_fmax, clk_conf.pll_out_fmin, - clk_conf.div_in_fmax, clk_conf.div_out_fmax, - clk_conf.xd_out_fmax); - break; - } -} - -int lcd_clk_config_print(char *buf, int offset) -{ - struct aml_lcd_drv_s *lcd_drv = aml_lcd_get_driver(); - int n, len = 0; - - n = lcd_debug_info_len(len + offset); - switch (lcd_drv->data->chip_type) { - case LCD_CHIP_G12A: - case LCD_CHIP_G12B: - if (lcd_drv->lcd_clk_path) { - len += snprintf((buf+len), n, - "lcd clk config:\n" - "clk_path %d\n" - "pll_m: %d\n" - "pll_n: %d\n" - "pll_frac: 0x%03x\n" - "pll_fvco: %dkHz\n" - "pll_od: %d\n" - "pll_out: %dkHz\n" - "xd: %d\n" - "fout: %dkHz\n" - "ss_level: %d\n\n", - lcd_drv->lcd_clk_path, - clk_conf.pll_m, clk_conf.pll_n, - clk_conf.pll_frac, clk_conf.pll_fvco, - clk_conf.pll_od1_sel, clk_conf.pll_fout, - clk_conf.xd, clk_conf.fout, clk_conf.ss_level); - } else { - len += snprintf((buf+len), n, - "lcd clk config:\n" - "clk_path %d\n" - "pll_m: %d\n" - "pll_n: %d\n" - "pll_frac: 0x%03x\n" - "pll_fvco: %dkHz\n" - "pll_od1: %d\n" - "pll_od2: %d\n" - "pll_od3: %d\n" - "pll_out: %dkHz\n" - "div_sel: %s(index %d)\n" - "xd: %d\n" - "fout: %dkHz\n" - "ss_level: %d\n\n", - lcd_drv->lcd_clk_path, - clk_conf.pll_m, clk_conf.pll_n, - clk_conf.pll_frac, clk_conf.pll_fvco, - clk_conf.pll_od1_sel, clk_conf.pll_od2_sel, - clk_conf.pll_od3_sel, clk_conf.pll_fout, - lcd_clk_div_sel_table[clk_conf.div_sel], - clk_conf.div_sel, clk_conf.xd, - clk_conf.fout, clk_conf.ss_level); - } - break; - case LCD_CHIP_AXG: - len += snprintf((buf+len), n, - "lcd clk config:\n" - "pll_m: %d\n" - "pll_n: %d\n" - "pll_frac: 0x%03x\n" - "pll_fvco: %dkHz\n" - "pll_od: %d\n" - "pll_out: %dkHz\n" - "xd: %d\n" - "fout: %dkHz\n" - "ss_level: %d\n\n", - clk_conf.pll_m, clk_conf.pll_n, - clk_conf.pll_frac, clk_conf.pll_fvco, - clk_conf.pll_od1_sel, clk_conf.pll_fout, - clk_conf.xd, clk_conf.fout, clk_conf.ss_level); - break; - default: - len += snprintf((buf+len), n, - "lcd clk config:\n" - "pll_mode: %d\n" - "pll_m: %d\n" - "pll_n: %d\n" - "pll_frac: 0x%03x\n" - "pll_fvco: %dkHz\n" - "pll_od1: %d\n" - "pll_od2: %d\n" - "pll_od3: %d\n" - "pll_out: %dkHz\n" - "div_sel: %s(index %d)\n" - "xd: %d\n" - "fout: %dkHz\n" - "ss_level: %d\n\n", - clk_conf.pll_mode, clk_conf.pll_m, clk_conf.pll_n, - clk_conf.pll_frac, clk_conf.pll_fvco, - clk_conf.pll_od1_sel, clk_conf.pll_od2_sel, - clk_conf.pll_od3_sel, clk_conf.pll_fout, - lcd_clk_div_sel_table[clk_conf.div_sel], - clk_conf.div_sel, clk_conf.xd, - clk_conf.fout, clk_conf.ss_level); - break; - } - - return len; -} - -static void lcd_clk_config_chip_init(void) -{ - struct lcd_clk_config_s *cConf; - struct aml_lcd_drv_s *lcd_drv = aml_lcd_get_driver(); - - cConf = get_lcd_clk_config(); - switch (lcd_drv->data->chip_type) { - case LCD_CHIP_GXTVBB: - cConf->od_fb = PLL_FRAC_OD_FB_GXTVBB; - cConf->ss_level_max = SS_LEVEL_MAX_GXTVBB; - cConf->pll_m_max = PLL_M_MAX_GXTVBB; - cConf->pll_m_min = PLL_M_MIN_GXTVBB; - cConf->pll_n_max = PLL_N_MAX_GXTVBB; - cConf->pll_n_min = PLL_N_MIN_GXTVBB; - cConf->pll_frac_range = PLL_FRAC_RANGE_GXTVBB; - cConf->pll_od_sel_max = PLL_OD_SEL_MAX_GXTVBB; - cConf->pll_ref_fmax = PLL_FREF_MAX_GXTVBB; - cConf->pll_ref_fmin = PLL_FREF_MIN_GXTVBB; - cConf->pll_vco_fmax = PLL_VCO_MAX_GXTVBB; - cConf->pll_vco_fmin = PLL_VCO_MIN_GXTVBB; - cConf->pll_out_fmax = CLK_DIV_IN_MAX_GXTVBB; - cConf->pll_out_fmin = cConf->pll_vco_fmin / 16; - cConf->div_in_fmax = CLK_DIV_IN_MAX_GXTVBB; - cConf->div_out_fmax = CRT_VID_CLK_IN_MAX_GXTVBB; - cConf->xd_out_fmax = ENCL_CLK_IN_MAX_GXTVBB; - break; - case LCD_CHIP_GXL: - cConf->od_fb = PLL_FRAC_OD_FB_GXL; - cConf->ss_level_max = SS_LEVEL_MAX_GXL; - cConf->pll_m_max = PLL_M_MAX_GXL; - cConf->pll_m_min = PLL_M_MIN_GXL; - cConf->pll_n_max = PLL_N_MAX_GXL; - cConf->pll_n_min = PLL_N_MIN_GXL; - cConf->pll_frac_range = PLL_FRAC_RANGE_GXL; - cConf->pll_od_sel_max = PLL_OD_SEL_MAX_GXL; - cConf->pll_ref_fmax = PLL_FREF_MAX_GXL; - cConf->pll_ref_fmin = PLL_FREF_MIN_GXL; - cConf->pll_vco_fmax = PLL_VCO_MAX_GXL; - cConf->pll_vco_fmin = PLL_VCO_MIN_GXL; - cConf->pll_out_fmax = CLK_DIV_IN_MAX_GXL; - cConf->pll_out_fmin = cConf->pll_vco_fmin / 16; - cConf->div_in_fmax = CLK_DIV_IN_MAX_GXL; - cConf->div_out_fmax = CRT_VID_CLK_IN_MAX_GXL; - cConf->xd_out_fmax = ENCL_CLK_IN_MAX_GXL; - break; - case LCD_CHIP_GXM: - cConf->od_fb = PLL_FRAC_OD_FB_GXM; - cConf->ss_level_max = SS_LEVEL_MAX_GXM; - cConf->pll_m_max = PLL_M_MAX_GXM; - cConf->pll_m_min = PLL_M_MIN_GXM; - cConf->pll_n_max = PLL_N_MAX_GXM; - cConf->pll_n_min = PLL_N_MIN_GXM; - cConf->pll_frac_range = PLL_FRAC_RANGE_GXM; - cConf->pll_od_sel_max = PLL_OD_SEL_MAX_GXM; - cConf->pll_ref_fmax = PLL_FREF_MAX_GXM; - cConf->pll_ref_fmin = PLL_FREF_MIN_GXM; - cConf->pll_vco_fmax = PLL_VCO_MAX_GXM; - cConf->pll_vco_fmin = PLL_VCO_MIN_GXM; - cConf->pll_out_fmax = CLK_DIV_IN_MAX_GXM; - cConf->pll_out_fmin = cConf->pll_vco_fmin / 16; - cConf->div_in_fmax = CLK_DIV_IN_MAX_GXM; - cConf->div_out_fmax = CRT_VID_CLK_IN_MAX_GXM; - cConf->xd_out_fmax = ENCL_CLK_IN_MAX_GXM; - break; - case LCD_CHIP_TXL: - cConf->od_fb = PLL_FRAC_OD_FB_TXL; - cConf->ss_level_max = SS_LEVEL_MAX_TXL; - cConf->pll_m_max = PLL_M_MAX_TXL; - cConf->pll_m_min = PLL_M_MIN_TXL; - cConf->pll_n_max = PLL_N_MAX_TXL; - cConf->pll_n_min = PLL_N_MIN_TXL; - cConf->pll_frac_range = PLL_FRAC_RANGE_TXL; - cConf->pll_od_sel_max = PLL_OD_SEL_MAX_TXL; - cConf->pll_ref_fmax = PLL_FREF_MAX_TXL; - cConf->pll_ref_fmin = PLL_FREF_MIN_TXL; - cConf->pll_vco_fmax = PLL_VCO_MAX_TXL; - cConf->pll_vco_fmin = PLL_VCO_MIN_TXL; - cConf->pll_out_fmax = CLK_DIV_IN_MAX_TXL; - cConf->pll_out_fmin = cConf->pll_vco_fmin / 16; - cConf->div_in_fmax = CLK_DIV_IN_MAX_TXL; - cConf->div_out_fmax = CRT_VID_CLK_IN_MAX_TXL; - cConf->xd_out_fmax = ENCL_CLK_IN_MAX_TXL; - break; - case LCD_CHIP_TXLX: - cConf->od_fb = PLL_FRAC_OD_FB_TXLX; - cConf->ss_level_max = SS_LEVEL_MAX_TXLX; - cConf->pll_m_max = PLL_M_MAX_TXLX; - cConf->pll_m_min = PLL_M_MIN_TXLX; - cConf->pll_n_max = PLL_N_MAX_TXLX; - cConf->pll_n_min = PLL_N_MIN_TXLX; - cConf->pll_frac_range = PLL_FRAC_RANGE_TXLX; - cConf->pll_od_sel_max = PLL_OD_SEL_MAX_TXLX; - cConf->pll_ref_fmax = PLL_FREF_MAX_TXLX; - cConf->pll_ref_fmin = PLL_FREF_MIN_TXLX; - cConf->pll_vco_fmax = PLL_VCO_MAX_TXLX; - cConf->pll_vco_fmin = PLL_VCO_MIN_TXLX; - cConf->pll_out_fmax = CLK_DIV_IN_MAX_TXLX; - cConf->pll_out_fmin = cConf->pll_vco_fmin / 16; - cConf->div_in_fmax = CLK_DIV_IN_MAX_TXLX; - cConf->div_out_fmax = CRT_VID_CLK_IN_MAX_TXLX; - cConf->xd_out_fmax = ENCL_CLK_IN_MAX_TXLX; - break; - case LCD_CHIP_AXG: - cConf->od_fb = PLL_FRAC_OD_FB_AXG; - cConf->ss_level_max = SS_LEVEL_MAX_AXG; - cConf->pll_m_max = PLL_M_MAX_AXG; - cConf->pll_m_min = PLL_M_MIN_AXG; - cConf->pll_n_max = PLL_N_MAX_AXG; - cConf->pll_n_min = PLL_N_MIN_AXG; - cConf->pll_frac_range = PLL_FRAC_RANGE_AXG; - cConf->pll_od_sel_max = PLL_OD_SEL_MAX_AXG; - cConf->pll_ref_fmax = PLL_FREF_MAX_AXG; - cConf->pll_ref_fmin = PLL_FREF_MIN_AXG; - cConf->pll_vco_fmax = PLL_VCO_MAX_AXG; - cConf->pll_vco_fmin = PLL_VCO_MIN_AXG; - cConf->pll_out_fmax = CRT_VID_CLK_IN_MAX_AXG; - cConf->pll_out_fmin = cConf->pll_vco_fmin / - od_table[cConf->pll_od_sel_max - 1]; - cConf->div_out_fmax = CRT_VID_CLK_IN_MAX_AXG; - cConf->xd_out_fmax = ENCL_CLK_IN_MAX_AXG; - break; - case LCD_CHIP_G12A: - case LCD_CHIP_G12B: - if (lcd_drv->lcd_clk_path) { - cConf->od_fb = PLL_FRAC_OD_FB_GP0_G12A; - cConf->ss_level_max = SS_LEVEL_MAX_GP0_G12A; - cConf->pll_frac_range = PLL_FRAC_RANGE_GP0_G12A; - cConf->pll_od_sel_max = PLL_OD_SEL_MAX_GP0_G12A; - cConf->pll_vco_fmax = PLL_VCO_MAX_GP0_G12A; - cConf->pll_vco_fmin = PLL_VCO_MIN_GP0_G12A; - } else { - cConf->od_fb = PLL_FRAC_OD_FB_HPLL_G12A; - cConf->ss_level_max = SS_LEVEL_MAX_HPLL_G12A; - cConf->pll_frac_range = PLL_FRAC_RANGE_HPLL_G12A; - cConf->pll_od_sel_max = PLL_OD_SEL_MAX_HPLL_G12A; - cConf->pll_vco_fmax = PLL_VCO_MAX_HPLL_G12A; - cConf->pll_vco_fmin = PLL_VCO_MIN_HPLL_G12A; - } - cConf->pll_m_max = PLL_M_MAX_G12A; - cConf->pll_m_min = PLL_M_MIN_G12A; - cConf->pll_n_max = PLL_N_MAX_G12A; - cConf->pll_n_min = PLL_N_MIN_G12A; - cConf->pll_ref_fmax = PLL_FREF_MAX_G12A; - cConf->pll_ref_fmin = PLL_FREF_MIN_G12A; - cConf->pll_out_fmax = CRT_VID_CLK_IN_MAX_G12A; - cConf->pll_out_fmin = cConf->pll_vco_fmin / 16; - cConf->div_out_fmax = CRT_VID_CLK_IN_MAX_G12A; - cConf->xd_out_fmax = ENCL_CLK_IN_MAX_G12A; - break; - default: - LCDPR("%s invalid chip type\n", __func__); - break; - } - if (lcd_debug_print_flag > 0) - lcd_clk_config_init_print(); -} - -int lcd_clk_path_change(int sel) -{ - struct lcd_clk_config_s *cConf = get_lcd_clk_config(); - struct aml_lcd_drv_s *lcd_drv = aml_lcd_get_driver(); - int ret = 0; - - switch (lcd_drv->data->chip_type) { - case LCD_CHIP_G12A: - case LCD_CHIP_G12B: - if (sel) { - lcd_drv->lcd_clk_path = 1; - cConf->od_fb = PLL_FRAC_OD_FB_GP0_G12A; - cConf->ss_level_max = SS_LEVEL_MAX_GP0_G12A; - cConf->pll_frac_range = PLL_FRAC_RANGE_GP0_G12A; - cConf->pll_od_sel_max = PLL_OD_SEL_MAX_GP0_G12A; - cConf->pll_vco_fmax = PLL_VCO_MAX_GP0_G12A; - cConf->pll_vco_fmin = PLL_VCO_MIN_GP0_G12A; - } else { - lcd_drv->lcd_clk_path = 0; - cConf->od_fb = PLL_FRAC_OD_FB_HPLL_G12A; - cConf->ss_level_max = SS_LEVEL_MAX_HPLL_G12A; - cConf->pll_frac_range = PLL_FRAC_RANGE_HPLL_G12A; - cConf->pll_od_sel_max = PLL_OD_SEL_MAX_HPLL_G12A; - cConf->pll_vco_fmax = PLL_VCO_MAX_HPLL_G12A; - cConf->pll_vco_fmin = PLL_VCO_MIN_HPLL_G12A; - } - cConf->pll_out_fmax = CRT_VID_CLK_IN_MAX_G12A; - cConf->pll_out_fmin = cConf->pll_vco_fmin / 16; - break; - default: - ret = -1; - LCDPR("%s: current chip not support\n", __func__); - break; - } - if (lcd_debug_print_flag > 0) - lcd_clk_config_init_print(); - - return ret; -} - -/* lcd controller operation */ +/* **************************************************** + * lcd pll & clk operation + * **************************************************** + */ static int lcd_pll_wait_lock(unsigned int reg, unsigned int lock_bit) { unsigned int pll_lock; @@ -569,182 +162,24 @@ pll_lock_end_g12a: return ret; } -static void lcd_set_pll_ss_gxtvbb(struct lcd_clk_config_s *cConf) -{ - if ((cConf->pll_fvco >= 5500000) && (cConf->pll_fvco <= 6000000)) { - switch (cConf->ss_level) { - case 1: /* +/- 0.3% */ - lcd_hiu_write(HHI_HDMI_PLL_CNTL3, 0x12dc5080); - lcd_hiu_write(HHI_HDMI_PLL_CNTL4, 0xb01da72c); - lcd_hiu_write(HHI_HDMI_PLL_CNTL5, 0x51486980); - lcd_hiu_write(HHI_HDMI_PLL_CNTL6, 0x00082a55); - break; - case 2: /* +/- 0.5% */ - lcd_hiu_write(HHI_HDMI_PLL_CNTL3, 0x12dc5080); - lcd_hiu_write(HHI_HDMI_PLL_CNTL4, 0xa85da72c); - lcd_hiu_write(HHI_HDMI_PLL_CNTL5, 0x51486980); - lcd_hiu_write(HHI_HDMI_PLL_CNTL6, 0x00082a55); - break; - case 3: /* +/- 0.9% */ - lcd_hiu_write(HHI_HDMI_PLL_CNTL3, 0x12dc5080); - lcd_hiu_write(HHI_HDMI_PLL_CNTL4, 0xb09da72c); - lcd_hiu_write(HHI_HDMI_PLL_CNTL5, 0x51486980); - lcd_hiu_write(HHI_HDMI_PLL_CNTL6, 0x00082a55); - break; - case 4: /* +/- 1.2% */ - lcd_hiu_write(HHI_HDMI_PLL_CNTL3, 0x12dc5080); - lcd_hiu_write(HHI_HDMI_PLL_CNTL4, 0xb0dda72c); - lcd_hiu_write(HHI_HDMI_PLL_CNTL5, 0x51486980); - lcd_hiu_write(HHI_HDMI_PLL_CNTL6, 0x00082a55); - break; - default: /* disable */ - lcd_hiu_write(HHI_HDMI_PLL_CNTL3, 0x12dc5081); - lcd_hiu_write(HHI_HDMI_PLL_CNTL4, 0x801da72c); - lcd_hiu_write(HHI_HDMI_PLL_CNTL5, 0x71486980); - lcd_hiu_write(HHI_HDMI_PLL_CNTL6, 0x00002a55); - break; - } - } else { - switch (cConf->ss_level) { - case 1: /* +/- 0.3% */ - lcd_hiu_write(HHI_HDMI_PLL_CNTL3, 0x0d1c5090); - lcd_hiu_write(HHI_HDMI_PLL_CNTL4, 0xb01da72c); - lcd_hiu_write(HHI_HDMI_PLL_CNTL5, 0x51486980); - lcd_hiu_write(HHI_HDMI_PLL_CNTL6, 0x00082a55); - break; - case 2: /* +/- 0.5% */ - lcd_hiu_write(HHI_HDMI_PLL_CNTL3, 0x0d1c5090); - lcd_hiu_write(HHI_HDMI_PLL_CNTL4, 0xa85da72c); - lcd_hiu_write(HHI_HDMI_PLL_CNTL5, 0x51486980); - lcd_hiu_write(HHI_HDMI_PLL_CNTL6, 0x00082a55); - break; - case 3: /* +/- 0.9% */ - lcd_hiu_write(HHI_HDMI_PLL_CNTL3, 0x0d1c5090); - lcd_hiu_write(HHI_HDMI_PLL_CNTL4, 0xb09da72c); - lcd_hiu_write(HHI_HDMI_PLL_CNTL5, 0x51486980); - lcd_hiu_write(HHI_HDMI_PLL_CNTL6, 0x00082a55); - break; - case 4: /* +/- 1.2% */ - lcd_hiu_write(HHI_HDMI_PLL_CNTL3, 0x0d1c5090); - lcd_hiu_write(HHI_HDMI_PLL_CNTL4, 0xb0dda72c); - lcd_hiu_write(HHI_HDMI_PLL_CNTL5, 0x51486980); - lcd_hiu_write(HHI_HDMI_PLL_CNTL6, 0x00082a55); - break; - default: /* disable */ - lcd_hiu_write(HHI_HDMI_PLL_CNTL3, 0x0d5c5091); - lcd_hiu_write(HHI_HDMI_PLL_CNTL4, 0x801da72c); - lcd_hiu_write(HHI_HDMI_PLL_CNTL5, 0x71486980); - lcd_hiu_write(HHI_HDMI_PLL_CNTL6, 0x00002a55); - break; - } - } - LCDPR("set pll spread spectrum: %s\n", - lcd_pll_ss_table_gxtvbb[cConf->ss_level]); -} - -static void lcd_pll_reset_gxtvbb(void) -{ - lcd_hiu_setb(HHI_HDMI_PLL_CNTL, 1, LCD_PLL_RST_GXTVBB, 1); - udelay(10); - lcd_hiu_setb(HHI_HDMI_PLL_CNTL, 0, LCD_PLL_RST_GXTVBB, 1); -} - -static void lcd_set_pll_gxtvbb(struct lcd_clk_config_s *cConf) -{ - unsigned int pll_ctrl, pll_ctrl2; - int ret; - - if (lcd_debug_print_flag == 2) - LCDPR("%s\n", __func__); - pll_ctrl = ((1 << LCD_PLL_EN_GXTVBB) | - (1 << 27) | /* DPLL_BGP_EN */ - (cConf->pll_n << LCD_PLL_N_GXTVBB) | - (cConf->pll_m << LCD_PLL_M_GXTVBB)); - - pll_ctrl2 = ((cConf->pll_od3_sel << LCD_PLL_OD3_GXTVBB) | - (cConf->pll_od2_sel << LCD_PLL_OD2_GXTVBB) | - (cConf->pll_od1_sel << LCD_PLL_OD1_GXTVBB)); - pll_ctrl2 |= ((1 << 14) | (cConf->pll_frac << 0)); - - lcd_hiu_write(HHI_HDMI_PLL_CNTL, pll_ctrl | (1 << LCD_PLL_RST_GXTVBB)); - lcd_hiu_write(HHI_HDMI_PLL_CNTL2, pll_ctrl2); - if ((cConf->pll_fvco >= 5500000) && (cConf->pll_fvco <= 6000000)) { - lcd_hiu_write(HHI_HDMI_PLL_CNTL3, 0x12dc5081); - lcd_hiu_write(HHI_HDMI_PLL_CNTL4, 0x801da72c); - lcd_hiu_write(HHI_HDMI_PLL_CNTL5, 0x71486980); - lcd_hiu_write(HHI_HDMI_PLL_CNTL6, 0x00002a55); - } else { - lcd_hiu_write(HHI_HDMI_PLL_CNTL3, 0x0d5c5091); - lcd_hiu_write(HHI_HDMI_PLL_CNTL4, 0x801da72c); - lcd_hiu_write(HHI_HDMI_PLL_CNTL5, 0x71486980); - lcd_hiu_write(HHI_HDMI_PLL_CNTL6, 0x00002a55); - } - lcd_hiu_write(HHI_HDMI_PLL_CNTL, pll_ctrl); - - ret = lcd_pll_wait_lock(HHI_HDMI_PLL_CNTL, LCD_PLL_LOCK_GXTVBB); - if (ret) - LCDERR("hpll lock failed\n"); - - if (cConf->ss_level > 0) - lcd_set_pll_ss_gxtvbb(cConf); -} - -static void lcd_update_pll_frac_gxtvbb(struct lcd_clk_config_s *cConf) -{ - if (lcd_debug_print_flag == 2) - LCDPR("%s\n", __func__); - - lcd_hiu_setb(HHI_HDMI_PLL_CNTL2, cConf->pll_frac, 0, 12); -} - -static void lcd_set_pll_ss_txl(struct lcd_clk_config_s *cConf) +static void lcd_set_pll_ss_txl(unsigned int ss_level) { unsigned int pll_ctrl3, pll_ctrl4; pll_ctrl3 = lcd_hiu_read(HHI_HDMI_PLL_CNTL3); pll_ctrl4 = lcd_hiu_read(HHI_HDMI_PLL_CNTL4); + pll_ctrl3 &= ~((0xf << 10) | (1 << 14)); + pll_ctrl4 &= ~(0x3 << 2); + + ss_level = (ss_level >= SS_LEVEL_MAX_TXL) ? 0 : ss_level; + pll_ctrl3 |= pll_ss_reg_txl[ss_level][0]; + pll_ctrl4 |= pll_ss_reg_txl[ss_level][1]; - switch (cConf->ss_level) { - case 1: /* +/- 0.3% */ - pll_ctrl3 &= ~(0xf << 10); - pll_ctrl3 |= ((1 << 14) | (0xc << 10)); - pll_ctrl4 &= ~(0x3 << 2); - break; - case 2: /* +/- 0.4% */ - pll_ctrl3 &= ~(0xf << 10); - pll_ctrl3 |= ((1 << 14) | (0x8 << 10)); - pll_ctrl4 &= ~(0x3 << 2); - pll_ctrl4 |= (0x1 << 2); - break; - case 3: /* +/- 0.9% */ - pll_ctrl3 &= ~(0xf << 10); - pll_ctrl3 |= ((1 << 14) | (0xc << 10)); - pll_ctrl4 &= ~(0x3 << 2); - pll_ctrl4 |= (0x2 << 2); - break; - case 4: /* +/- 1.2% */ - pll_ctrl3 &= ~(0xf << 10); - pll_ctrl3 |= ((1 << 14) | (0xc << 10)); - pll_ctrl4 &= ~(0x3 << 2); - pll_ctrl4 |= (0x3 << 2); - break; - default: /* disable */ - pll_ctrl3 &= ~((0xf << 10) | (1 << 14)); - pll_ctrl4 &= ~(0x3 << 2); - break; - } lcd_hiu_write(HHI_HDMI_PLL_CNTL3, pll_ctrl3); lcd_hiu_write(HHI_HDMI_PLL_CNTL4, pll_ctrl4); LCDPR("set pll spread spectrum: %s\n", - lcd_pll_ss_table_txl[cConf->ss_level]); -} - -static void lcd_pll_reset_txl(void) -{ - lcd_hiu_setb(HHI_HDMI_PLL_CNTL, 1, LCD_PLL_RST_TXL, 1); - udelay(10); - lcd_hiu_setb(HHI_HDMI_PLL_CNTL, 0, LCD_PLL_RST_TXL, 1); + lcd_pll_ss_table_txl[ss_level]); } static void lcd_set_pll_txl(struct lcd_clk_config_s *cConf) @@ -759,7 +194,7 @@ static void lcd_set_pll_txl(struct lcd_clk_config_s *cConf) (cConf->pll_m << LCD_PLL_M_TXL)); pll_ctrl2 = 0x800ca000; pll_ctrl2 |= ((1 << 12) | (cConf->pll_frac << 0)); - pll_ctrl3 = 0x860330c4 | (cConf->od_fb << 30); + pll_ctrl3 = 0x860330c4 | (cConf->pll_od_fb << 30); pll_ctrl3 |= ((cConf->pll_od3_sel << LCD_PLL_OD3_TXL) | (cConf->pll_od2_sel << LCD_PLL_OD2_TXL) | (cConf->pll_od1_sel << LCD_PLL_OD1_TXL)); @@ -781,75 +216,31 @@ static void lcd_set_pll_txl(struct lcd_clk_config_s *cConf) LCDERR("hpll lock failed\n"); if (cConf->ss_level > 0) - lcd_set_pll_ss_txl(cConf); + lcd_set_pll_ss_txl(cConf->ss_level); } -static void lcd_update_pll_frac_txl(struct lcd_clk_config_s *cConf) -{ - if (lcd_debug_print_flag == 2) - LCDPR("%s\n", __func__); - - lcd_hiu_setb(HHI_HDMI_PLL_CNTL2, cConf->pll_frac, 0, 12); -} - -static void lcd_set_pll_ss_txlx(struct lcd_clk_config_s *cConf) +static void lcd_set_pll_ss_txlx(unsigned int ss_level) { unsigned int pll_ctrl3, pll_ctrl4, pll_ctrl5; pll_ctrl3 = lcd_hiu_read(HHI_HDMI_PLL_CNTL3); pll_ctrl4 = lcd_hiu_read(HHI_HDMI_PLL_CNTL4); pll_ctrl5 = lcd_hiu_read(HHI_HDMI_PLL_CNTL5); + pll_ctrl3 &= ~((0xf << 10) | (1 << 14)); + pll_ctrl4 &= ~(0x3 << 2); + pll_ctrl5 &= ~(0x3 << 30); + + ss_level = (ss_level >= SS_LEVEL_MAX_TXLX) ? 0 : ss_level; + pll_ctrl3 |= pll_ss_reg_txlx[ss_level][0]; + pll_ctrl4 |= pll_ss_reg_txlx[ss_level][1]; + pll_ctrl5 |= pll_ss_reg_txlx[ss_level][2]; - switch (cConf->ss_level) { - case 1: /* +/- 0.3% */ - pll_ctrl3 &= ~(0xf << 10); - pll_ctrl3 |= ((1 << 14) | (0x6 << 10)); - pll_ctrl4 &= ~(0x3 << 2); - pll_ctrl4 |= (0x1 << 2); - pll_ctrl5 &= ~(0x3 << 30); - break; - case 2: /* +/- 0.5% */ - pll_ctrl3 &= ~(0xf << 10); - pll_ctrl3 |= ((1 << 14) | (0xa << 10)); - pll_ctrl4 &= ~(0x3 << 2); - pll_ctrl4 |= (0x1 << 2); - pll_ctrl5 &= ~(0x3 << 30); - break; - case 3: /* +/- 1.0% */ - pll_ctrl3 &= ~(0xf << 10); - pll_ctrl3 |= ((1 << 14) | (0xa << 10)); - pll_ctrl4 &= ~(0x3 << 2); - pll_ctrl4 |= (0x3 << 2); - pll_ctrl5 &= ~(0x3 << 30); - break; - case 4: /* +/- 1.6% */ - pll_ctrl3 &= ~(0xf << 10); - pll_ctrl3 |= ((1 << 14) | (0x8 << 10)); - pll_ctrl4 &= ~(0x3 << 2); - pll_ctrl4 |= (0x3 << 2); - pll_ctrl5 &= ~(0x3 << 30); - pll_ctrl5 |= (0x1 << 30); - break; - case 5: /* +/- 3.0% */ - pll_ctrl3 &= ~(0xf << 10); - pll_ctrl3 |= ((1 << 14) | (0xa << 10)); - pll_ctrl4 &= ~(0x3 << 2); - pll_ctrl4 |= (0x3 << 2); - pll_ctrl5 &= ~(0x3 << 30); - pll_ctrl5 |= (0x2 << 30); - break; - default: /* disable */ - pll_ctrl3 &= ~((0xf << 10) | (1 << 14)); - pll_ctrl4 &= ~(0x3 << 2); - pll_ctrl5 &= ~(0x3 << 30); - break; - } lcd_hiu_write(HHI_HDMI_PLL_CNTL3, pll_ctrl3); lcd_hiu_write(HHI_HDMI_PLL_CNTL4, pll_ctrl4); lcd_hiu_write(HHI_HDMI_PLL_CNTL5, pll_ctrl5); LCDPR("set pll spread spectrum: %s\n", - lcd_pll_ss_table_txlx[cConf->ss_level]); + lcd_pll_ss_table_txlx[ss_level]); } static void lcd_set_pll_txlx(struct lcd_clk_config_s *cConf) @@ -864,7 +255,7 @@ static void lcd_set_pll_txlx(struct lcd_clk_config_s *cConf) (cConf->pll_m << LCD_PLL_M_TXL)); pll_ctrl2 = 0x800ca000; pll_ctrl2 |= ((1 << 12) | (cConf->pll_frac << 0)); - pll_ctrl3 = 0x860030c4 | (cConf->od_fb << 30); + pll_ctrl3 = 0x860030c4 | (cConf->pll_od_fb << 30); pll_ctrl3 |= ((cConf->pll_od3_sel << LCD_PLL_OD3_TXL) | (cConf->pll_od2_sel << LCD_PLL_OD2_TXL) | (cConf->pll_od1_sel << LCD_PLL_OD1_TXL)); @@ -883,14 +274,7 @@ static void lcd_set_pll_txlx(struct lcd_clk_config_s *cConf) LCDERR("hpll lock failed\n"); if (cConf->ss_level > 0) - lcd_set_pll_ss_txlx(cConf); -} - -static void lcd_pll_reset_axg(void) -{ - lcd_hiu_setb(HHI_GP0_PLL_CNTL_AXG, 1, LCD_PLL_RST_AXG, 1); - udelay(10); - lcd_hiu_setb(HHI_GP0_PLL_CNTL_AXG, 0, LCD_PLL_RST_AXG, 1); + lcd_set_pll_ss_txlx(cConf->ss_level); } static void lcd_set_pll_axg(struct lcd_clk_config_s *cConf) @@ -907,7 +291,7 @@ static void lcd_set_pll_axg(struct lcd_clk_config_s *cConf) (cConf->pll_od1_sel << LCD_PLL_OD_AXG)); pll_ctrl1 = 0xc084a000; pll_ctrl1 |= ((1 << 12) | (cConf->pll_frac << 0)); - pll_ctrl2 = 0xb75020be | (cConf->od_fb << 19); + pll_ctrl2 = 0xb75020be | (cConf->pll_od_fb << 19); lcd_hiu_write(HHI_GP0_PLL_CNTL_AXG, pll_ctrl); lcd_hiu_write(HHI_GP0_PLL_CNTL1_AXG, pll_ctrl1); @@ -924,22 +308,6 @@ static void lcd_set_pll_axg(struct lcd_clk_config_s *cConf) ret = lcd_pll_wait_lock(HHI_GP0_PLL_CNTL_AXG, LCD_PLL_LOCK_AXG); if (ret) LCDERR("gp0_pll lock failed\n"); - -} - -static void lcd_update_pll_frac_axg(struct lcd_clk_config_s *cConf) -{ - if (lcd_debug_print_flag == 2) - LCDPR("%s\n", __func__); - - lcd_hiu_setb(HHI_GP0_PLL_CNTL1_AXG, cConf->pll_frac, 0, 12); -} - -static void lcd_gp0_pll_reset_g12a(void) -{ - lcd_hiu_setb(HHI_GP0_PLL_CNTL0_G12A, 1, LCD_PLL_RST_GP0_G12A, 1); - udelay(10); - lcd_hiu_setb(HHI_GP0_PLL_CNTL0_G12A, 0, LCD_PLL_RST_GP0_G12A, 1); } static void lcd_set_gp0_pll_g12a(struct lcd_clk_config_s *cConf) @@ -980,22 +348,6 @@ static void lcd_set_gp0_pll_g12a(struct lcd_clk_config_s *cConf) ret = lcd_pll_wait_lock_g12a(1); if (ret) LCDERR("gp0_pll lock failed\n"); - -} - -static void lcd_update_gp0_pll_frac_g12a(struct lcd_clk_config_s *cConf) -{ - if (lcd_debug_print_flag == 2) - LCDPR("%s\n", __func__); - - lcd_hiu_setb(HHI_GP0_PLL_CNTL1_G12A, cConf->pll_frac, 0, 19); -} - -static void lcd_hpll_reset_g12a(void) -{ - lcd_hiu_setb(HHI_HDMI_PLL_CNTL, 1, LCD_PLL_RST_HPLL_G12A, 1); - udelay(10); - lcd_hiu_setb(HHI_HDMI_PLL_CNTL, 0, LCD_PLL_RST_HPLL_G12A, 1); } static void lcd_set_hpll_g12a(struct lcd_clk_config_s *cConf) @@ -1039,15 +391,6 @@ static void lcd_set_hpll_g12a(struct lcd_clk_config_s *cConf) ret = lcd_pll_wait_lock_g12a(0); if (ret) LCDERR("hpll lock failed\n"); - -} - -static void lcd_update_hpll_frac_g12a(struct lcd_clk_config_s *cConf) -{ - if (lcd_debug_print_flag == 2) - LCDPR("%s\n", __func__); - - lcd_hiu_setb(HHI_HDMI_PLL_CNTL2, cConf->pll_frac, 0, 19); } static void lcd_set_gp0_pll_g12b(struct lcd_clk_config_s *cConf) @@ -1088,7 +431,6 @@ static void lcd_set_gp0_pll_g12b(struct lcd_clk_config_s *cConf) ret = lcd_pll_wait_lock(HHI_GP0_PLL_CNTL0_G12A, LCD_PLL_LOCK_GP0_G12A); if (ret) LCDERR("gp0_pll lock failed\n"); - } static void lcd_set_hpll_g12b(struct lcd_clk_config_s *cConf) @@ -1132,28 +474,49 @@ static void lcd_set_hpll_g12b(struct lcd_clk_config_s *cConf) ret = lcd_pll_wait_lock(HHI_HDMI_PLL_CNTL, LCD_PLL_LOCK_HPLL_G12A); if (ret) LCDERR("hpll lock failed\n"); - } -static unsigned int lcd_clk_div_g9_gxtvbb[][3] = { - /* divider, shift_val, shift_sel */ - {CLK_DIV_SEL_1, 0xffff, 0,}, - {CLK_DIV_SEL_2, 0x0aaa, 0,}, - {CLK_DIV_SEL_3, 0x0db6, 0,}, - {CLK_DIV_SEL_3p5, 0x36cc, 1,}, - {CLK_DIV_SEL_3p75, 0x6666, 2,}, - {CLK_DIV_SEL_4, 0x0ccc, 0,}, - {CLK_DIV_SEL_5, 0x739c, 2,}, - {CLK_DIV_SEL_6, 0x0e38, 0,}, - {CLK_DIV_SEL_6p25, 0x0000, 3,}, - {CLK_DIV_SEL_7, 0x3c78, 1,}, - {CLK_DIV_SEL_7p5, 0x78f0, 2,}, - {CLK_DIV_SEL_12, 0x0fc0, 0,}, - {CLK_DIV_SEL_14, 0x3f80, 1,}, - {CLK_DIV_SEL_15, 0x7f80, 2,}, - {CLK_DIV_SEL_2p5, 0x5294, 2,}, - {CLK_DIV_SEL_MAX, 0xffff, 0,}, -}; +static void lcd_set_pll_ss_tl1(unsigned int ss_level) +{ + LCDPR("%s: todo\n", __func__); +} + +static void lcd_set_pll_tl1(struct lcd_clk_config_s *cConf) +{ + unsigned int pll_ctrl, pll_ctrl1; + int ret; + + if (lcd_debug_print_flag == 2) + LCDPR("%s\n", __func__); + pll_ctrl = ((0x3 << 17) | /* gate ctrl */ + (1 << LCD_PLL_RST_TL1) | + (cConf->pll_n << LCD_PLL_N_TL1) | + (cConf->pll_m << LCD_PLL_M_TL1) | + (cConf->pll_od3_sel << LCD_PLL_OD3_TL1) | + (cConf->pll_od2_sel << LCD_PLL_OD2_TL1) | + (cConf->pll_od1_sel << LCD_PLL_OD1_TL1)); + pll_ctrl1 = (1 << 28) | (1 << 23) | + ((1 << 20) | (cConf->pll_frac << 0)); + + lcd_hiu_write(HHI_TCON_PLL_CNTL0, pll_ctrl); + lcd_hiu_setb(HHI_TCON_PLL_CNTL0, 1, LCD_PLL_EN_TL1, 1); + lcd_hiu_write(HHI_TCON_PLL_CNTL1, pll_ctrl1); + lcd_hiu_write(HHI_TCON_PLL_CNTL2, 0x00001108); + lcd_hiu_write(HHI_TCON_PLL_CNTL3, 0x10058f30); + lcd_hiu_write(HHI_TCON_PLL_CNTL4, 0x010100c0); + lcd_hiu_write(HHI_TCON_PLL_CNTL4, 0x038300c0); + lcd_hiu_setb(HHI_TCON_PLL_CNTL0, 1, 26, 1); + lcd_hiu_setb(HHI_TCON_PLL_CNTL0, 0, LCD_PLL_RST_TL1, 1); + lcd_hiu_write(HHI_TCON_PLL_CNTL2, 0x00003008); + lcd_hiu_write(HHI_TCON_PLL_CNTL4, 0x0b8300c0); + + ret = lcd_pll_wait_lock(HHI_TCON_PLL_CNTL0, LCD_PLL_LOCK_TL1); + if (ret) + LCDERR("hpll lock failed\n"); + + if (cConf->ss_level > 0) + lcd_set_pll_ss_tl1(cConf->ss_level); +} static void lcd_set_vid_pll_div(struct lcd_clk_config_s *cConf) { @@ -1171,15 +534,15 @@ static void lcd_set_vid_pll_div(struct lcd_clk_config_s *cConf) lcd_hiu_setb(HHI_VID_PLL_CLK_DIV, 0, 15, 1); i = 0; - while (lcd_clk_div_g9_gxtvbb[i][0] != CLK_DIV_SEL_MAX) { - if (cConf->div_sel == lcd_clk_div_g9_gxtvbb[i][0]) + while (lcd_clk_div_table[i][0] != CLK_DIV_SEL_MAX) { + if (cConf->div_sel == lcd_clk_div_table[i][0]) break; i++; } - if (lcd_clk_div_g9_gxtvbb[i][0] == CLK_DIV_SEL_MAX) + if (lcd_clk_div_table[i][0] == CLK_DIV_SEL_MAX) LCDERR("invalid clk divider\n"); - shift_val = lcd_clk_div_g9_gxtvbb[i][1]; - shift_sel = lcd_clk_div_g9_gxtvbb[i][2]; + shift_val = lcd_clk_div_table[i][1]; + shift_sel = lcd_clk_div_table[i][2]; if (shift_val == 0xffff) { /* if divide by 1 */ lcd_hiu_setb(HHI_VID_PLL_CLK_DIV, 1, 18, 1); @@ -1200,7 +563,6 @@ static void lcd_set_vid_pll_div(struct lcd_clk_config_s *cConf) static void lcd_set_vclk_crt(int lcd_type, struct lcd_clk_config_s *cConf) { - struct aml_lcd_drv_s *lcd_drv = aml_lcd_get_driver(); if (lcd_debug_print_flag == 2) LCDPR("%s\n", __func__); @@ -1209,18 +571,8 @@ static void lcd_set_vclk_crt(int lcd_type, struct lcd_clk_config_s *cConf) udelay(5); /* select vid_pll_clk */ - switch (lcd_drv->data->chip_type) { - case LCD_CHIP_G12A: - case LCD_CHIP_G12B: - if (lcd_drv->lcd_clk_path) - lcd_hiu_setb(HHI_VIID_CLK_CNTL, 1, VCLK2_CLK_IN_SEL, 3); - else - lcd_hiu_setb(HHI_VIID_CLK_CNTL, 0, VCLK2_CLK_IN_SEL, 3); - break; - default: - lcd_hiu_setb(HHI_VIID_CLK_CNTL, 0, VCLK2_CLK_IN_SEL, 3); - break; - } + lcd_hiu_setb(HHI_VIID_CLK_CNTL, cConf->data->vclk_sel, + VCLK2_CLK_IN_SEL, 3); lcd_hiu_setb(HHI_VIID_CLK_CNTL, 1, VCLK2_EN, 1); udelay(2); @@ -1250,6 +602,58 @@ static void lcd_set_dsi_phy_clk(int sel) lcd_hiu_setb(HHI_MIPIDSI_PHY_CLK_CNTL, 0, 0, 7); } +static void lcd_set_tcon_clk(struct lcd_config_s *pconf) +{ +#if 0 + unsigned int val; + + if (lcd_debug_print_flag == 2) + LCDPR("%s\n", __func__); + + switch (pconf->lcd_basic.lcd_type) { + case LCD_LVDS: + lcd_hiu_write(HHI_DIF_TCON_CNTL0, 0x0); + lcd_hiu_write(HHI_DIF_TCON_CNTL0, 0x80000000); + lcd_hiu_write(HHI_DIF_TCON_CNTL1, 0x0); + lcd_hiu_write(HHI_DIF_TCON_CNTL2, 0x0); + break; + case LCD_MLVDS: + val = pconf->lcd_control.mlvds_config->pi_clk_sel; + /*val = (~val) & 0x3ff;*/ + lcd_hiu_write(HHI_DIF_TCON_CNTL0, (val << 12)); + lcd_hiu_write(HHI_DIF_TCON_CNTL0, ((1 << 31) | (val << 12))); + + val = pconf->lcd_control.mlvds_config->clk_phase & 0xfff; + lcd_hiu_write(HHI_DIF_TCON_CNTL1, val); + lcd_hiu_write(HHI_DIF_TCON_CNTL2, 0x0); + + /* tcon_clk 50M */ + /*lcd_hiu_write(HHI_TCON_CLK_CNTL, + * (1 << 7) | (1 << 6) | (7 << 0)); + */ + if (!IS_ERR(lcd_clktree.tcon_clk)) { + clk_set_rate(lcd_clktree.tcon_clk, 50000000); + clk_prepare_enable(lcd_clktree.tcon_clk); + } + break; + default: + break; + } +#endif +} + +/* **************************************************** + * lcd clk parameters calculate + * **************************************************** + */ +static int error_abs(int a, int b) +{ + if (a >= b) + return (a - b); + else + return (b - a); +} + static unsigned int clk_vid_pll_div_calc(unsigned int clk, unsigned int div_sel, int dir) { @@ -1377,294 +781,11 @@ static unsigned int clk_vid_pll_div_get(unsigned int clk_div) return div_sel; } -static int check_pll_gxtvbb(struct lcd_clk_config_s *cConf, - unsigned int pll_fout) -{ - unsigned int m, n; - unsigned int od1_sel, od2_sel, od3_sel, od1, od2, od3; - unsigned int pll_fod2_in, pll_fod3_in, pll_fvco; - unsigned int od_fb = 0, pll_frac; - int done; - - done = 0; - if ((pll_fout > cConf->pll_out_fmax) || - (pll_fout < cConf->pll_out_fmin)) { - return done; - } - for (od3_sel = cConf->pll_od_sel_max; od3_sel > 0; od3_sel--) { - od3 = od_table[od3_sel - 1]; - pll_fod3_in = pll_fout * od3; - for (od2_sel = od3_sel; od2_sel > 0; od2_sel--) { - od2 = od_table[od2_sel - 1]; - pll_fod2_in = pll_fod3_in * od2; - for (od1_sel = od2_sel; od1_sel > 0; od1_sel--) { - od1 = od_table[od1_sel - 1]; - pll_fvco = pll_fod2_in * od1; - if ((pll_fvco < cConf->pll_vco_fmin) || - (pll_fvco > cConf->pll_vco_fmax)) { - continue; - } - cConf->pll_od1_sel = od1_sel - 1; - cConf->pll_od2_sel = od2_sel - 1; - cConf->pll_od3_sel = od3_sel - 1; - cConf->pll_fout = pll_fout; - if (lcd_debug_print_flag == 2) { - LCDPR("od1=%d, od2=%d, od3=%d\n", - (od1_sel - 1), (od2_sel - 1), - (od3_sel - 1)); - LCDPR("pll_fvco=%d\n", pll_fvco); - } - cConf->pll_fvco = pll_fvco; - n = 1; - od_fb = cConf->od_fb; /* pll default */ - pll_fvco = pll_fvco / od_fb_table[od_fb + 1]; - m = pll_fvco / cConf->fin; - pll_frac = (pll_fvco % cConf->fin) * - cConf->pll_frac_range / cConf->fin; - cConf->pll_m = m; - cConf->pll_n = n; - cConf->pll_frac = pll_frac; - if (lcd_debug_print_flag == 2) { - LCDPR("m=%d, n=%d, frac=0x%x\n", - m, n, pll_frac); - } - done = 1; - break; - } - } - } - return done; -} - -static void lcd_clk_generate_gxtvbb(struct lcd_config_s *pconf) -{ - unsigned int pll_fout; - unsigned int clk_div_in, clk_div_out; - unsigned int clk_div_sel, xd; - struct lcd_clk_config_s *cConf; - int done; - - done = 0; - cConf = get_lcd_clk_config(); - cConf->fout = pconf->lcd_timing.lcd_clk / 1000; /* kHz */ - cConf->err_fmin = MAX_ERROR; - - if (cConf->fout > cConf->xd_out_fmax) { - LCDERR("%s: wrong lcd_clk value %dkHz\n", - __func__, cConf->fout); - goto generate_clk_done_gxtvbb; - } - - switch (pconf->lcd_basic.lcd_type) { - case LCD_TTL: - clk_div_sel = CLK_DIV_SEL_1; - cConf->xd_max = CRT_VID_DIV_MAX; - for (xd = 1; xd <= cConf->xd_max; xd++) { - clk_div_out = cConf->fout * xd; - if (clk_div_out > cConf->div_out_fmax) - continue; - if (lcd_debug_print_flag == 2) { - LCDPR("fout=%d, xd=%d, clk_div_out=%d\n", - cConf->fout, xd, clk_div_out); - } - clk_div_in = clk_vid_pll_div_calc(clk_div_out, - clk_div_sel, CLK_DIV_O2I); - if (clk_div_in > cConf->div_in_fmax) - continue; - cConf->xd = xd; - cConf->div_sel = clk_div_sel; - pll_fout = clk_div_in; - if (lcd_debug_print_flag == 2) { - LCDPR("clk_div_sel=%s(index %d), pll_fout=%d\n", - lcd_clk_div_sel_table[clk_div_sel], - clk_div_sel, pll_fout); - } - done = check_pll_gxtvbb(cConf, pll_fout); - if (done) - goto generate_clk_done_gxtvbb; - } - break; - case LCD_LVDS: - clk_div_sel = CLK_DIV_SEL_7; - xd = 1; - clk_div_out = cConf->fout * xd; - if (clk_div_out > cConf->div_out_fmax) - goto generate_clk_done_gxtvbb; - if (lcd_debug_print_flag == 2) { - LCDPR("fout=%d, xd=%d, clk_div_out=%d\n", - cConf->fout, xd, clk_div_out); - } - clk_div_in = clk_vid_pll_div_calc(clk_div_out, - clk_div_sel, CLK_DIV_O2I); - if (clk_div_in > cConf->div_in_fmax) - goto generate_clk_done_gxtvbb; - cConf->xd = xd; - cConf->div_sel = clk_div_sel; - pll_fout = clk_div_in; - if (lcd_debug_print_flag == 2) { - LCDPR("clk_div_sel=%s(index %d), pll_fout=%d\n", - lcd_clk_div_sel_table[clk_div_sel], - clk_div_sel, pll_fout); - } - done = check_pll_gxtvbb(cConf, pll_fout); - if (done) - goto generate_clk_done_gxtvbb; - break; - case LCD_VBYONE: - cConf->div_sel_max = CLK_DIV_SEL_MAX; - cConf->xd_max = CRT_VID_DIV_MAX; - pll_fout = pconf->lcd_control.vbyone_config->bit_rate / 1000; - clk_div_in = pll_fout; - if (clk_div_in > cConf->div_in_fmax) - goto generate_clk_done_gxtvbb; - if (lcd_debug_print_flag == 2) - LCDPR("pll_fout=%d\n", pll_fout); - if ((clk_div_in / cConf->fout) > 15) - cConf->xd = 4; - else - cConf->xd = 1; - clk_div_out = cConf->fout * cConf->xd; - if (lcd_debug_print_flag == 2) { - LCDPR("clk_div_in=%d, fout=%d, xd=%d, clk_div_out=%d\n", - clk_div_in, cConf->fout, - clk_div_out, cConf->xd); - } - if (clk_div_out > cConf->div_out_fmax) - goto generate_clk_done_gxtvbb; - clk_div_sel = clk_vid_pll_div_get( - clk_div_in * 100 / clk_div_out); - cConf->div_sel = clk_div_sel; - if (lcd_debug_print_flag == 2) { - LCDPR("clk_div_sel=%s(index %d)\n", - lcd_clk_div_sel_table[clk_div_sel], - cConf->div_sel); - } - done = check_pll_gxtvbb(cConf, pll_fout); - break; - default: - break; - } - -generate_clk_done_gxtvbb: - if (done) { - pconf->lcd_timing.pll_ctrl = - (cConf->pll_od1_sel << PLL_CTRL_OD1) | - (cConf->pll_od2_sel << PLL_CTRL_OD2) | - (cConf->pll_od3_sel << PLL_CTRL_OD3) | - (cConf->pll_n << PLL_CTRL_N) | - (cConf->pll_m << PLL_CTRL_M); - pconf->lcd_timing.div_ctrl = - (cConf->div_sel << DIV_CTRL_DIV_SEL) | - (cConf->xd << DIV_CTRL_XD); - pconf->lcd_timing.clk_ctrl = - (cConf->pll_frac << CLK_CTRL_FRAC); - } else { - pconf->lcd_timing.pll_ctrl = - (1 << PLL_CTRL_OD1) | - (1 << PLL_CTRL_OD2) | - (1 << PLL_CTRL_OD3) | - (1 << PLL_CTRL_N) | - (50 << PLL_CTRL_M); - pconf->lcd_timing.div_ctrl = - (CLK_DIV_SEL_1 << DIV_CTRL_DIV_SEL) | - (7 << DIV_CTRL_XD); - pconf->lcd_timing.clk_ctrl = (0 << CLK_CTRL_FRAC); - LCDERR("Out of clock range, reset to default setting\n"); - } -} - -static void lcd_pll_frac_generate_gxtvbb(struct lcd_config_s *pconf) -{ - unsigned int pll_fout; - unsigned int clk_div_in, clk_div_out, clk_div_sel; - unsigned int od1, od2, od3, pll_fvco; - unsigned int m, n, od_fb, frac, offset, temp; - struct lcd_clk_config_s *cConf; - - cConf = get_lcd_clk_config(); - cConf->fout = pconf->lcd_timing.lcd_clk / 1000; /* kHz */ - clk_div_sel = cConf->div_sel; - od1 = od_table[cConf->pll_od1_sel]; - od2 = od_table[cConf->pll_od2_sel]; - od3 = od_table[cConf->pll_od3_sel]; - m = cConf->pll_m; - n = cConf->pll_n; - - if (lcd_debug_print_flag == 2) { - LCDPR("m=%d, n=%d, od1=%d, od2=%d, od3=%d\n", - m, n, cConf->pll_od1_sel, cConf->pll_od2_sel, - cConf->pll_od3_sel); - LCDPR("clk_div_sel=%s(index %d), xd=%d\n", - lcd_clk_div_sel_table[clk_div_sel], - clk_div_sel, cConf->xd); - } - if (cConf->fout > cConf->xd_out_fmax) { - LCDERR("%s: wrong lcd_clk value %dkHz\n", - __func__, cConf->fout); - return; - } - if (lcd_debug_print_flag == 2) - LCDPR("%s pclk=%d\n", __func__, cConf->fout); - - clk_div_out = cConf->fout * cConf->xd; - if (clk_div_out > cConf->div_out_fmax) { - LCDERR("%s: wrong clk_div_out value %dkHz\n", - __func__, clk_div_out); - return; - } - - clk_div_in = - clk_vid_pll_div_calc(clk_div_out, clk_div_sel, CLK_DIV_O2I); - if (clk_div_in > cConf->div_in_fmax) { - LCDERR("%s: wrong clk_div_in value %dkHz\n", - __func__, clk_div_in); - return; - } - - pll_fout = clk_div_in; - if ((pll_fout > cConf->pll_out_fmax) || - (pll_fout < cConf->pll_out_fmin)) { - LCDERR("%s: wrong pll_fout value %dkHz\n", __func__, pll_fout); - return; - } - if (lcd_debug_print_flag == 2) - LCDPR("%s pll_fout=%d\n", __func__, pll_fout); - - pll_fvco = pll_fout * od1 * od2 * od3; - if ((pll_fvco < cConf->pll_vco_fmin) || - (pll_fvco > cConf->pll_vco_fmax)) { - LCDERR("%s: wrong pll_fvco value %dkHz\n", __func__, pll_fvco); - return; - } - if (lcd_debug_print_flag == 2) - LCDPR("%s pll_fvco=%d\n", __func__, pll_fvco); - - cConf->pll_fvco = pll_fvco; - od_fb = cConf->od_fb; /* pll default */ - pll_fvco = pll_fvco / od_fb_table[od_fb + 1]; - temp = cConf->fin * m / n; - if (pll_fvco >= temp) { - temp = pll_fvco - temp; - offset = 0; - } else { - temp = temp - pll_fvco; - offset = 1; - } - if (temp >= (2 * cConf->fin)) { - LCDERR("%s: pll changing %dkHz is too much\n", - __func__, temp); - return; - } - frac = temp * cConf->pll_frac_range * n / cConf->fin; - cConf->pll_frac = frac | (offset << 11); - if (lcd_debug_print_flag) - LCDPR("lcd_pll_frac_generate frac=%d\n", frac); -} - static int check_pll_txl(struct lcd_clk_config_s *cConf, unsigned int pll_fout) { struct aml_lcd_drv_s *lcd_drv = aml_lcd_get_driver(); + struct lcd_clk_data_s *data = cConf->data; unsigned int m, n; unsigned int od1_sel, od2_sel, od3_sel, od1, od2, od3; unsigned int pll_fod2_in, pll_fod3_in, pll_fvco; @@ -1672,11 +793,11 @@ static int check_pll_txl(struct lcd_clk_config_s *cConf, int done; done = 0; - if ((pll_fout > cConf->pll_out_fmax) || - (pll_fout < cConf->pll_out_fmin)) { + if ((pll_fout > data->pll_out_fmax) || + (pll_fout < data->pll_out_fmin)) { return done; } - for (od3_sel = cConf->pll_od_sel_max; od3_sel > 0; od3_sel--) { + for (od3_sel = data->pll_od_sel_max; od3_sel > 0; od3_sel--) { od3 = od_table[od3_sel - 1]; pll_fod3_in = pll_fout * od3; for (od2_sel = od3_sel; od2_sel > 0; od2_sel--) { @@ -1685,8 +806,8 @@ static int check_pll_txl(struct lcd_clk_config_s *cConf, for (od1_sel = od2_sel; od1_sel > 0; od1_sel--) { od1 = od_table[od1_sel - 1]; pll_fvco = pll_fod2_in * od1; - if ((pll_fvco < cConf->pll_vco_fmin) || - (pll_fvco > cConf->pll_vco_fmax)) { + if ((pll_fvco < data->pll_vco_fmin) || + (pll_fvco > data->pll_vco_fmax)) { continue; } cConf->pll_od1_sel = od1_sel - 1; @@ -1706,14 +827,14 @@ static int check_pll_txl(struct lcd_clk_config_s *cConf, od_fb = 0; else od_fb = 1; - cConf->od_fb = od_fb; + cConf->pll_od_fb = od_fb; } else { - od_fb = cConf->od_fb; + od_fb = cConf->pll_od_fb; } pll_fvco = pll_fvco / od_fb_table[od_fb]; m = pll_fvco / cConf->fin; pll_frac = (pll_fvco % cConf->fin) * - cConf->pll_frac_range / cConf->fin; + data->pll_frac_range / cConf->fin; cConf->pll_m = m; cConf->pll_n = n; cConf->pll_frac = pll_frac; @@ -1729,20 +850,101 @@ static int check_pll_txl(struct lcd_clk_config_s *cConf, return done; } +static int check_pll_tl1_mlvds(struct lcd_clk_config_s *cConf, + unsigned int pll_fvco) +{ + struct lcd_clk_data_s *data = cConf->data; + unsigned int m, n; + unsigned int od_fb = 0, pll_frac; + int done = 0; + + if ((pll_fvco < data->pll_vco_fmin) || + (pll_fvco > data->pll_vco_fmax)) { + if (lcd_debug_print_flag == 2) + LCDPR("pll_fvco %d is out of range\n", pll_fvco); + return done; + } + + cConf->pll_fvco = pll_fvco; + n = 1; + od_fb = cConf->pll_od_fb; + pll_fvco = pll_fvco / od_fb_table[od_fb]; + m = pll_fvco / cConf->fin; + pll_frac = (pll_fvco % cConf->fin) * data->pll_frac_range / cConf->fin; + cConf->pll_m = m; + cConf->pll_n = n; + cConf->pll_frac = pll_frac; + if (lcd_debug_print_flag == 2) { + LCDPR("m=%d, n=%d, frac=0x%x, pll_fvco=%d\n", + m, n, pll_frac, pll_fvco); + } + done = 1; + + return done; +} + +#define PLL_FVCO_ERR_MAX 2 /* kHz */ +static int check_pll_od_tl1_mlvds(struct lcd_clk_config_s *cConf, + unsigned int pll_fout) +{ + struct lcd_clk_data_s *data = cConf->data; + unsigned int od1_sel, od2_sel, od3_sel, od1, od2, od3; + unsigned int pll_fod2_in, pll_fod3_in, pll_fvco; + int done = 0; + + if ((pll_fout > data->pll_out_fmax) || + (pll_fout < data->pll_out_fmin)) { + return done; + } + for (od3_sel = data->pll_od_sel_max; od3_sel > 0; od3_sel--) { + od3 = od_table[od3_sel - 1]; + pll_fod3_in = pll_fout * od3; + for (od2_sel = od3_sel; od2_sel > 0; od2_sel--) { + od2 = od_table[od2_sel - 1]; + pll_fod2_in = pll_fod3_in * od2; + for (od1_sel = od2_sel; od1_sel > 0; od1_sel--) { + od1 = od_table[od1_sel - 1]; + pll_fvco = pll_fod2_in * od1; + if ((pll_fvco < data->pll_vco_fmin) || + (pll_fvco > data->pll_vco_fmax)) { + continue; + } + if (error_abs(pll_fvco, cConf->pll_fvco) < + PLL_FVCO_ERR_MAX) { + cConf->pll_od1_sel = od1_sel - 1; + cConf->pll_od2_sel = od2_sel - 1; + cConf->pll_od3_sel = od3_sel - 1; + cConf->pll_fout = pll_fout; + + if (lcd_debug_print_flag == 2) { + LCDPR( + "od1=%d, od2=%d, od3=%d\n", + (od1_sel - 1), + (od2_sel - 1), + (od3_sel - 1)); + } + done = 1; + break; + } + } + } + } + return done; +} + static void lcd_clk_generate_txl(struct lcd_config_s *pconf) { - unsigned int pll_fout; + unsigned int pll_fout, pll_fvco, bit_rate; unsigned int clk_div_in, clk_div_out; - unsigned int clk_div_sel, xd; - struct lcd_clk_config_s *cConf; + unsigned int clk_div_sel, xd, pi_div_sel; + struct lcd_clk_config_s *cConf = get_lcd_clk_config(); int done; done = 0; - cConf = get_lcd_clk_config(); cConf->fout = pconf->lcd_timing.lcd_clk / 1000; /* kHz */ cConf->err_fmin = MAX_ERROR; - if (cConf->fout > cConf->xd_out_fmax) { + if (cConf->fout > cConf->data->xd_out_fmax) { LCDERR("%s: wrong lcd_clk value %dkHz\n", __func__, cConf->fout); goto generate_clk_done_txl; @@ -1759,7 +961,7 @@ static void lcd_clk_generate_txl(struct lcd_config_s *pconf) cConf->xd_max = CRT_VID_DIV_MAX; for (xd = 1; xd <= cConf->xd_max; xd++) { clk_div_out = cConf->fout * xd; - if (clk_div_out > cConf->div_out_fmax) + if (clk_div_out > cConf->data->div_out_fmax) continue; if (lcd_debug_print_flag == 2) { LCDPR("fout=%d, xd=%d, clk_div_out=%d\n", @@ -1767,7 +969,7 @@ static void lcd_clk_generate_txl(struct lcd_config_s *pconf) } clk_div_in = clk_vid_pll_div_calc(clk_div_out, clk_div_sel, CLK_DIV_O2I); - if (clk_div_in > cConf->div_in_fmax) + if (clk_div_in > cConf->data->div_in_fmax) continue; cConf->xd = xd; cConf->div_sel = clk_div_sel; @@ -1786,7 +988,7 @@ static void lcd_clk_generate_txl(struct lcd_config_s *pconf) clk_div_sel = CLK_DIV_SEL_7; xd = 1; clk_div_out = cConf->fout * xd; - if (clk_div_out > cConf->div_out_fmax) + if (clk_div_out > cConf->data->div_out_fmax) goto generate_clk_done_txl; if (lcd_debug_print_flag == 2) { LCDPR("fout=%d, xd=%d, clk_div_out=%d\n", @@ -1794,7 +996,7 @@ static void lcd_clk_generate_txl(struct lcd_config_s *pconf) } clk_div_in = clk_vid_pll_div_calc(clk_div_out, clk_div_sel, CLK_DIV_O2I); - if (clk_div_in > cConf->div_in_fmax) + if (clk_div_in > cConf->data->div_in_fmax) goto generate_clk_done_txl; cConf->xd = xd; cConf->div_sel = clk_div_sel; @@ -1813,7 +1015,7 @@ static void lcd_clk_generate_txl(struct lcd_config_s *pconf) cConf->xd_max = CRT_VID_DIV_MAX; pll_fout = pconf->lcd_control.vbyone_config->bit_rate / 1000; clk_div_in = pll_fout; - if (clk_div_in > cConf->div_in_fmax) + if (clk_div_in > cConf->data->div_in_fmax) goto generate_clk_done_txl; if (lcd_debug_print_flag == 2) LCDPR("pll_fout=%d\n", pll_fout); @@ -1827,7 +1029,7 @@ static void lcd_clk_generate_txl(struct lcd_config_s *pconf) clk_div_in, cConf->fout, clk_div_out, cConf->xd); } - if (clk_div_out > cConf->div_out_fmax) + if (clk_div_out > cConf->data->div_out_fmax) goto generate_clk_done_txl; clk_div_sel = clk_vid_pll_div_get( clk_div_in * 100 / clk_div_out); @@ -1839,6 +1041,53 @@ static void lcd_clk_generate_txl(struct lcd_config_s *pconf) } done = check_pll_txl(cConf, pll_fout); break; + case LCD_MLVDS: + bit_rate = pconf->lcd_control.mlvds_config->bit_rate / 1000; + for (pi_div_sel = 0; pi_div_sel < 2; pi_div_sel++) { + pll_fvco = bit_rate * pi_div_table[pi_div_sel] * 4; + done = check_pll_tl1_mlvds(cConf, pll_fvco); + if (done) { + clk_div_sel = CLK_DIV_SEL_1; + cConf->xd_max = CRT_VID_DIV_MAX; + for (xd = 1; xd <= cConf->xd_max; xd++) { + clk_div_out = cConf->fout * xd; + if (clk_div_out > + cConf->data->div_out_fmax) + continue; + if (lcd_debug_print_flag == 2) { + LCDPR("fout=%d, xd=%d\n", + cConf->fout, xd); + LCDPR("clk_div_out=%d\n", + clk_div_out); + } + clk_div_in = clk_vid_pll_div_calc( + clk_div_out, + clk_div_sel, CLK_DIV_O2I); + if (clk_div_in > + cConf->data->div_in_fmax) + continue; + cConf->xd = xd; + cConf->div_sel = clk_div_sel; + cConf->pll_pi_div_sel = pi_div_sel; + pll_fout = clk_div_in; + if (lcd_debug_print_flag == 2) { + LCDPR("clk_div_sel=%s(%d)\n", + lcd_clk_div_sel_table[ + clk_div_sel], + clk_div_sel); + LCDPR("pll_fout=%d\n", + pll_fout); + LCDPR("pi_clk_sel=%d\n", + pi_div_sel); + } + done = check_pll_od_tl1_mlvds( + cConf, pll_fout); + if (done) + goto generate_clk_done_txl; + } + } + } + break; default: break; } @@ -1876,9 +1125,8 @@ static void lcd_pll_frac_generate_txl(struct lcd_config_s *pconf) unsigned int clk_div_in, clk_div_out, clk_div_sel; unsigned int od1, od2, od3, pll_fvco; unsigned int m, n, od_fb, frac, offset, temp; - struct lcd_clk_config_s *cConf; + struct lcd_clk_config_s *cConf = get_lcd_clk_config(); - cConf = get_lcd_clk_config(); cConf->fout = pconf->lcd_timing.lcd_clk / 1000; /* kHz */ clk_div_sel = cConf->div_sel; od1 = od_table[cConf->pll_od1_sel]; @@ -1886,7 +1134,7 @@ static void lcd_pll_frac_generate_txl(struct lcd_config_s *pconf) od3 = od_table[cConf->pll_od3_sel]; m = cConf->pll_m; n = cConf->pll_n; - od_fb = cConf->od_fb; + od_fb = cConf->pll_od_fb; if (lcd_debug_print_flag == 2) { LCDPR("m=%d, n=%d, od1=%d, od2=%d, od3=%d\n", @@ -1896,7 +1144,7 @@ static void lcd_pll_frac_generate_txl(struct lcd_config_s *pconf) lcd_clk_div_sel_table[clk_div_sel], clk_div_sel, cConf->xd); } - if (cConf->fout > cConf->xd_out_fmax) { + if (cConf->fout > cConf->data->xd_out_fmax) { LCDERR("%s: wrong lcd_clk value %dkHz\n", __func__, cConf->fout); return; @@ -1905,7 +1153,7 @@ static void lcd_pll_frac_generate_txl(struct lcd_config_s *pconf) LCDPR("%s pclk=%d\n", __func__, cConf->fout); clk_div_out = cConf->fout * cConf->xd; - if (clk_div_out > cConf->div_out_fmax) { + if (clk_div_out > cConf->data->div_out_fmax) { LCDERR("%s: wrong clk_div_out value %dkHz\n", __func__, clk_div_out); return; @@ -1913,15 +1161,15 @@ static void lcd_pll_frac_generate_txl(struct lcd_config_s *pconf) clk_div_in = clk_vid_pll_div_calc(clk_div_out, clk_div_sel, CLK_DIV_O2I); - if (clk_div_in > cConf->div_in_fmax) { + if (clk_div_in > cConf->data->div_in_fmax) { LCDERR("%s: wrong clk_div_in value %dkHz\n", __func__, clk_div_in); return; } pll_fout = clk_div_in; - if ((pll_fout > cConf->pll_out_fmax) || - (pll_fout < cConf->pll_out_fmin)) { + if ((pll_fout > cConf->data->pll_out_fmax) || + (pll_fout < cConf->data->pll_out_fmin)) { LCDERR("%s: wrong pll_fout value %dkHz\n", __func__, pll_fout); return; } @@ -1929,8 +1177,8 @@ static void lcd_pll_frac_generate_txl(struct lcd_config_s *pconf) LCDPR("%s pll_fout=%d\n", __func__, pll_fout); pll_fvco = pll_fout * od1 * od2 * od3; - if ((pll_fvco < cConf->pll_vco_fmin) || - (pll_fvco > cConf->pll_vco_fmax)) { + if ((pll_fvco < cConf->data->pll_vco_fmin) || + (pll_fvco > cConf->data->pll_vco_fmax)) { LCDERR("%s: wrong pll_fvco value %dkHz\n", __func__, pll_fvco); return; } @@ -1952,7 +1200,7 @@ static void lcd_pll_frac_generate_txl(struct lcd_config_s *pconf) __func__, temp); return; } - frac = temp * cConf->pll_frac_range * n / cConf->fin; + frac = temp * cConf->data->pll_frac_range * n / cConf->fin; cConf->pll_frac = frac | (offset << 11); if (lcd_debug_print_flag) LCDPR("lcd_pll_frac_generate: frac=0x%x\n", frac); @@ -1961,20 +1209,21 @@ static void lcd_pll_frac_generate_txl(struct lcd_config_s *pconf) static int check_pll_axg(struct lcd_clk_config_s *cConf, unsigned int pll_fout) { + struct lcd_clk_data_s *data = cConf->data; unsigned int m, n, od_sel, od; unsigned int pll_fvco; unsigned int od_fb = 0, pll_frac; int done = 0; - if ((pll_fout > cConf->pll_out_fmax) || - (pll_fout < cConf->pll_out_fmin)) { + if ((pll_fout > data->pll_out_fmax) || + (pll_fout < data->pll_out_fmin)) { return done; } - for (od_sel = cConf->pll_od_sel_max; od_sel > 0; od_sel--) { + for (od_sel = data->pll_od_sel_max; od_sel > 0; od_sel--) { od = od_table[od_sel - 1]; pll_fvco = pll_fout * od; - if ((pll_fvco < cConf->pll_vco_fmin) || - (pll_fvco > cConf->pll_vco_fmax)) { + if ((pll_fvco < data->pll_vco_fmin) || + (pll_fvco > data->pll_vco_fmax)) { continue; } cConf->pll_od1_sel = od_sel - 1; @@ -1986,11 +1235,11 @@ static int check_pll_axg(struct lcd_clk_config_s *cConf, cConf->pll_fvco = pll_fvco; n = 1; - od_fb = cConf->od_fb; + od_fb = cConf->pll_od_fb; pll_fvco = pll_fvco / od_fb_table[od_fb]; m = pll_fvco / cConf->fin; pll_frac = (pll_fvco % cConf->fin) * - cConf->pll_frac_range / cConf->fin; + data->pll_frac_range / cConf->fin; cConf->pll_m = m; cConf->pll_n = n; cConf->pll_frac = pll_frac; @@ -2010,15 +1259,14 @@ static void lcd_clk_generate_axg(struct lcd_config_s *pconf) unsigned int xd; unsigned int dsi_bit_rate_max = 0, dsi_bit_rate_min = 0; unsigned int tmp; - struct lcd_clk_config_s *cConf; + struct lcd_clk_config_s *cConf = get_lcd_clk_config(); int done; done = 0; - cConf = get_lcd_clk_config(); cConf->fout = pconf->lcd_timing.lcd_clk / 1000; /* kHz */ cConf->err_fmin = MAX_ERROR; - if (cConf->fout > cConf->xd_out_fmax) { + if (cConf->fout > cConf->data->xd_out_fmax) { LCDERR("%s: wrong lcd_clk value %dkHz\n", __func__, cConf->fout); goto generate_clk_done_axg; @@ -2040,7 +1288,8 @@ static void lcd_clk_generate_axg(struct lcd_config_s *pconf) if (lcd_debug_print_flag == 2) LCDPR("fout=%d, xd=%d\n", cConf->fout, xd); - pconf->lcd_control.mipi_config->bit_rate = pll_fout * 1000; + pconf->lcd_control.mipi_config->bit_rate = + pll_fout * 1000; pconf->lcd_control.mipi_config->clk_factor = xd; cConf->xd = xd; done = check_pll_axg(cConf, pll_fout); @@ -2080,19 +1329,19 @@ static void lcd_pll_frac_generate_axg(struct lcd_config_s *pconf) unsigned int pll_fout; unsigned int od, pll_fvco; unsigned int m, n, od_fb, frac, offset, temp; - struct lcd_clk_config_s *cConf; + struct lcd_clk_config_s *cConf = get_lcd_clk_config(); - cConf = get_lcd_clk_config(); cConf->fout = pconf->lcd_timing.lcd_clk / 1000; /* kHz */ od = od_table[cConf->pll_od1_sel]; m = cConf->pll_m; n = cConf->pll_n; + od_fb = cConf->pll_od_fb; if (lcd_debug_print_flag == 2) { LCDPR("m=%d, n=%d, od=%d, xd=%d\n", m, n, cConf->pll_od1_sel, cConf->xd); } - if (cConf->fout > cConf->xd_out_fmax) { + if (cConf->fout > cConf->data->xd_out_fmax) { LCDERR("%s: wrong lcd_clk value %dkHz\n", __func__, cConf->fout); return; @@ -2101,8 +1350,8 @@ static void lcd_pll_frac_generate_axg(struct lcd_config_s *pconf) LCDPR("%s pclk=%d\n", __func__, cConf->fout); pll_fout = cConf->fout * cConf->xd; - if ((pll_fout > cConf->pll_out_fmax) || - (pll_fout < cConf->pll_out_fmin)) { + if ((pll_fout > cConf->data->pll_out_fmax) || + (pll_fout < cConf->data->pll_out_fmin)) { LCDERR("%s: wrong pll_fout value %dkHz\n", __func__, pll_fout); return; } @@ -2110,8 +1359,8 @@ static void lcd_pll_frac_generate_axg(struct lcd_config_s *pconf) LCDPR("%s pll_fout=%d\n", __func__, pll_fout); pll_fvco = pll_fout * od; - if ((pll_fvco < cConf->pll_vco_fmin) || - (pll_fvco > cConf->pll_vco_fmax)) { + if ((pll_fvco < cConf->data->pll_vco_fmin) || + (pll_fvco > cConf->data->pll_vco_fmax)) { LCDERR("%s: wrong pll_fvco value %dkHz\n", __func__, pll_fvco); return; } @@ -2119,7 +1368,6 @@ static void lcd_pll_frac_generate_axg(struct lcd_config_s *pconf) LCDPR("%s pll_fvco=%d\n", __func__, pll_fvco); cConf->pll_fvco = pll_fvco; - od_fb = cConf->od_fb; /* pll default */ pll_fvco = pll_fvco / od_fb_table[od_fb]; temp = cConf->fin * m / n; if (pll_fvco >= temp) { @@ -2134,7 +1382,7 @@ static void lcd_pll_frac_generate_axg(struct lcd_config_s *pconf) __func__, temp); return; } - frac = temp * cConf->pll_frac_range * n / cConf->fin; + frac = temp * cConf->data->pll_frac_range * n / cConf->fin; cConf->pll_frac = frac | (offset << 11); if (lcd_debug_print_flag) LCDPR("lcd_pll_frac_generate: frac=0x%x\n", frac); @@ -2153,7 +1401,7 @@ static void lcd_clk_generate_hpll_g12a(struct lcd_config_s *pconf) cConf->fout = pconf->lcd_timing.lcd_clk / 1000; /* kHz */ cConf->err_fmin = MAX_ERROR; - if (cConf->fout > cConf->xd_out_fmax) { + if (cConf->fout > cConf->data->xd_out_fmax) { LCDERR("%s: wrong lcd_clk value %dkHz\n", __func__, cConf->fout); } @@ -2216,91 +1464,673 @@ generate_clk_done_g12a: } } -void lcd_clk_generate_parameter(struct lcd_config_s *pconf) +/* **************************************************** + * lcd clk match function + * **************************************************** + */ +void lcd_clk_set_txl(struct lcd_config_s *pconf) +{ + lcd_set_pll_txl(&clk_conf); + lcd_set_vid_pll_div(&clk_conf); +} + +static void lcd_clk_set_txlx(struct lcd_config_s *pconf) +{ + lcd_set_pll_txlx(&clk_conf); + lcd_set_vid_pll_div(&clk_conf); +} + +static void lcd_clk_set_axg(struct lcd_config_s *pconf) +{ + lcd_set_pll_axg(&clk_conf); +} + +static void lcd_clk_set_g12a_path0(struct lcd_config_s *pconf) +{ + /* hpll */ + lcd_set_hpll_g12a(&clk_conf); + lcd_set_vid_pll_div(&clk_conf); + lcd_set_dsi_phy_clk(0); +} + +static void lcd_clk_set_g12a_path1(struct lcd_config_s *pconf) +{ + /* gp0_pll */ + lcd_set_gp0_pll_g12a(&clk_conf); + lcd_set_dsi_phy_clk(1); +} + +static void lcd_clk_set_g12b_path0(struct lcd_config_s *pconf) +{ + /* hpll */ + lcd_set_hpll_g12b(&clk_conf); + lcd_set_vid_pll_div(&clk_conf); + lcd_set_dsi_phy_clk(0); +} + +static void lcd_clk_set_g12b_path1(struct lcd_config_s *pconf) +{ + /* gp0_pll */ + lcd_set_gp0_pll_g12b(&clk_conf); + lcd_set_dsi_phy_clk(1); +} + +static void lcd_clk_set_tl1(struct lcd_config_s *pconf) +{ + lcd_set_tcon_clk(pconf); + lcd_set_pll_tl1(&clk_conf); + lcd_set_vid_pll_div(&clk_conf); +} + +static void lcd_clk_gate_switch_dft(struct aml_lcd_drv_s *lcd_drv, int status) +{ + if (status) { + if (IS_ERR(lcd_clktree.encl_top_gate)) + LCDERR("%s: encl_top_gate\n", __func__); + else + clk_prepare_enable(lcd_clktree.encl_top_gate); + if (IS_ERR(lcd_clktree.encl_int_gate)) + LCDERR("%s: encl_int_gata\n", __func__); + else + clk_prepare_enable(lcd_clktree.encl_int_gate); + } else { + if (IS_ERR(lcd_clktree.encl_int_gate)) + LCDERR("%s: encl_int_gata\n", __func__); + else + clk_disable_unprepare(lcd_clktree.encl_int_gate); + if (IS_ERR(lcd_clktree.encl_top_gate)) + LCDERR("%s: encl_top_gata\n", __func__); + else + clk_disable_unprepare(lcd_clktree.encl_top_gate); + } +} + +static void lcd_clk_gate_switch_axg(struct aml_lcd_drv_s *lcd_drv, int status) +{ + if (status) { + if (IS_ERR(lcd_clktree.dsi_host_gate)) + LCDERR("%s: dsi_host_gate\n", __func__); + else + clk_prepare_enable(lcd_clktree.dsi_host_gate); + if (IS_ERR(lcd_clktree.dsi_phy_gate)) + LCDERR("%s: dsi_phy_gate\n", __func__); + else + clk_prepare_enable(lcd_clktree.dsi_phy_gate); + if (IS_ERR(lcd_clktree.dsi_meas)) + LCDERR("%s: dsi_meas\n", __func__); + else + clk_prepare_enable(lcd_clktree.dsi_meas); + if (IS_ERR(lcd_clktree.mipi_enable_gate)) + LCDERR("%s: mipi_enable_gate\n", __func__); + else + clk_prepare_enable(lcd_clktree.mipi_enable_gate); + if (IS_ERR(lcd_clktree.mipi_bandgap_gate)) + LCDERR("%s: mipi_bandgap_gate\n", __func__); + else + clk_prepare_enable(lcd_clktree.mipi_bandgap_gate); + } else { + if (IS_ERR(lcd_clktree.dsi_host_gate)) + LCDERR("%s: dsi_host_gate\n", __func__); + else + clk_disable_unprepare(lcd_clktree.dsi_host_gate); + if (IS_ERR(lcd_clktree.dsi_phy_gate)) + LCDERR("%s: dsi_phy_gate\n", __func__); + else + clk_disable_unprepare(lcd_clktree.dsi_phy_gate); + if (IS_ERR(lcd_clktree.dsi_meas)) + LCDERR("%s: dsi_meas\n", __func__); + else + clk_disable_unprepare(lcd_clktree.dsi_meas); + if (IS_ERR(lcd_clktree.mipi_enable_gate)) + LCDERR("%s: mipi_enable_gate\n", __func__); + else + clk_disable_unprepare(lcd_clktree.mipi_enable_gate); + if (IS_ERR(lcd_clktree.mipi_bandgap_gate)) + LCDERR("%s: mipi_bandgap_gate\n", __func__); + else + clk_disable_unprepare(lcd_clktree.mipi_bandgap_gate); + } +} + +static void lcd_clk_gate_switch_g12a(struct aml_lcd_drv_s *lcd_drv, int status) +{ + if (status) { + if (clk_conf.data->vclk_sel) { + if (IS_ERR(lcd_clktree.gp0_pll)) + LCDERR("%s: gp0_pll\n", __func__); + else + clk_prepare_enable(lcd_clktree.gp0_pll); + } + + if (IS_ERR(lcd_clktree.dsi_host_gate)) + LCDERR("%s: dsi_host_gate\n", __func__); + else + clk_prepare_enable(lcd_clktree.dsi_host_gate); + if (IS_ERR(lcd_clktree.dsi_phy_gate)) + LCDERR("%s: dsi_phy_gate\n", __func__); + else + clk_prepare_enable(lcd_clktree.dsi_phy_gate); + if (IS_ERR(lcd_clktree.dsi_meas)) + LCDERR("%s: dsi_meas\n", __func__); + else + clk_prepare_enable(lcd_clktree.dsi_meas); + if (IS_ERR(lcd_clktree.encl_top_gate)) + LCDERR("%s: encl_top_gate\n", __func__); + else + clk_prepare_enable(lcd_clktree.encl_top_gate); + if (IS_ERR(lcd_clktree.encl_int_gate)) + LCDERR("%s: encl_int_gata\n", __func__); + else + clk_prepare_enable(lcd_clktree.encl_int_gate); + } else { + if (IS_ERR(lcd_clktree.dsi_host_gate)) + LCDERR("%s: dsi_host_gate\n", __func__); + else + clk_disable_unprepare(lcd_clktree.dsi_host_gate); + if (IS_ERR(lcd_clktree.dsi_phy_gate)) + LCDERR("%s: dsi_phy_gate\n", __func__); + else + clk_disable_unprepare(lcd_clktree.dsi_phy_gate); + if (IS_ERR(lcd_clktree.dsi_meas)) + LCDERR("%s: dsi_meas\n", __func__); + else + clk_disable_unprepare(lcd_clktree.dsi_meas); + if (IS_ERR(lcd_clktree.encl_int_gate)) + LCDERR("%s: encl_int_gate\n", __func__); + else + clk_disable_unprepare(lcd_clktree.encl_int_gate); + if (IS_ERR(lcd_clktree.encl_top_gate)) + LCDERR("%s: encl_top_gate\n", __func__); + else + clk_disable_unprepare(lcd_clktree.encl_top_gate); + + if (clk_conf.data->vclk_sel) { + if (IS_ERR(lcd_clktree.gp0_pll)) + LCDERR("%s: gp0_pll\n", __func__); + else + clk_disable_unprepare(lcd_clktree.gp0_pll); + } + } +} + +static void lcd_clk_gate_switch_tl1(struct aml_lcd_drv_s *lcd_drv, int status) +{ + if (status) { + if (IS_ERR(lcd_clktree.encl_top_gate)) + LCDERR("%s: encl_top_gate\n", __func__); + else + clk_prepare_enable(lcd_clktree.encl_top_gate); + if (IS_ERR(lcd_clktree.encl_int_gate)) + LCDERR("%s: encl_int_gata\n", __func__); + else + clk_prepare_enable(lcd_clktree.encl_int_gate); + switch (lcd_drv->lcd_config->lcd_basic.lcd_type) { + case LCD_MLVDS: + case LCD_P2P: + if (IS_ERR(lcd_clktree.tcon_gate)) + LCDERR("%s: tcon_gate\n", __func__); + else + clk_prepare_enable(lcd_clktree.tcon_gate); + if (IS_ERR(lcd_clktree.tcon_clk)) + LCDERR("%s: tcon_clk\n", __func__); + else + clk_prepare_enable(lcd_clktree.tcon_clk); + break; + default: + break; + } + } else { + switch (lcd_drv->lcd_config->lcd_basic.lcd_type) { + case LCD_MLVDS: + case LCD_P2P: + if (IS_ERR(lcd_clktree.tcon_clk)) + LCDERR("%s: tcon_clk\n", __func__); + else + clk_disable_unprepare(lcd_clktree.tcon_clk); + if (IS_ERR(lcd_clktree.tcon_gate)) + LCDERR("%s: tcon_gate\n", __func__); + else + clk_disable_unprepare(lcd_clktree.tcon_gate); + break; + default: + break; + } + if (IS_ERR(lcd_clktree.encl_int_gate)) + LCDERR("%s: encl_int_gate\n", __func__); + else + clk_disable_unprepare(lcd_clktree.encl_int_gate); + if (IS_ERR(lcd_clktree.encl_top_gate)) + LCDERR("%s: encl_top_gate\n", __func__); + else + clk_disable_unprepare(lcd_clktree.encl_top_gate); + } +} + +static void lcd_clktree_probe_dft(void) { struct aml_lcd_drv_s *lcd_drv = aml_lcd_get_driver(); - switch (lcd_drv->data->chip_type) { - case LCD_CHIP_GXTVBB: - lcd_clk_generate_gxtvbb(pconf); - break; - case LCD_CHIP_GXL: - case LCD_CHIP_GXM: - case LCD_CHIP_TXL: - case LCD_CHIP_TXLX: - lcd_clk_generate_txl(pconf); - break; - case LCD_CHIP_AXG: - lcd_clk_generate_axg(pconf); - break; - case LCD_CHIP_G12A: - case LCD_CHIP_G12B: - if (lcd_drv->lcd_clk_path) - lcd_clk_generate_axg(pconf); + lcd_clktree.clk_gate_state = 0; + + lcd_clktree.encl_top_gate = devm_clk_get(lcd_drv->dev, "encl_top_gate"); + if (IS_ERR(lcd_clktree.encl_top_gate)) + LCDERR("%s: get encl_top_gate error\n", __func__); + + lcd_clktree.encl_int_gate = devm_clk_get(lcd_drv->dev, "encl_int_gate"); + if (IS_ERR(lcd_clktree.encl_int_gate)) + LCDERR("%s: get encl_int_gate error\n", __func__); + + LCDPR("lcd_clktree_probe\n"); +} + +static void lcd_clktree_probe_axg(void) +{ + struct aml_lcd_drv_s *lcd_drv = aml_lcd_get_driver(); + + lcd_clktree.clk_gate_state = 0; + + lcd_clktree.dsi_host_gate = devm_clk_get(lcd_drv->dev, "dsi_host_gate"); + if (IS_ERR(lcd_clktree.dsi_host_gate)) + LCDERR("%s: clk dsi_host_gate\n", __func__); + + lcd_clktree.dsi_phy_gate = devm_clk_get(lcd_drv->dev, "dsi_phy_gate"); + if (IS_ERR(lcd_clktree.dsi_phy_gate)) + LCDERR("%s: clk dsi_phy_gate\n", __func__); + + lcd_clktree.dsi_meas = devm_clk_get(lcd_drv->dev, "dsi_meas"); + if (IS_ERR(lcd_clktree.dsi_meas)) + LCDERR("%s: clk dsi_meas\n", __func__); + + lcd_clktree.mipi_enable_gate = devm_clk_get(lcd_drv->dev, + "mipi_enable_gate"); + if (IS_ERR(lcd_clktree.mipi_enable_gate)) + LCDERR("%s: clk mipi_enable_gate\n", __func__); + + lcd_clktree.mipi_bandgap_gate = devm_clk_get(lcd_drv->dev, + "mipi_bandgap_gate"); + if (IS_ERR(lcd_clktree.mipi_bandgap_gate)) + LCDERR("%s: clk mipi_bandgap_gate\n", __func__); + + LCDPR("lcd_clktree_probe\n"); +} + +static void lcd_clktree_probe_g12a(void) +{ + struct aml_lcd_drv_s *lcd_drv = aml_lcd_get_driver(); + + lcd_clktree.clk_gate_state = 0; + + lcd_clktree.dsi_host_gate = devm_clk_get(lcd_drv->dev, "dsi_host_gate"); + if (IS_ERR(lcd_clktree.dsi_host_gate)) + LCDERR("%s: clk dsi_host_gate\n", __func__); + + lcd_clktree.dsi_phy_gate = devm_clk_get(lcd_drv->dev, "dsi_phy_gate"); + if (IS_ERR(lcd_clktree.dsi_phy_gate)) + LCDERR("%s: clk dsi_phy_gate\n", __func__); + + lcd_clktree.dsi_meas = devm_clk_get(lcd_drv->dev, "dsi_meas"); + if (IS_ERR(lcd_clktree.dsi_meas)) + LCDERR("%s: clk dsi_meas\n", __func__); + + lcd_clktree.encl_top_gate = devm_clk_get(lcd_drv->dev, "encl_top_gate"); + if (IS_ERR(lcd_clktree.encl_top_gate)) + LCDERR("%s: clk encl_top_gate\n", __func__); + + lcd_clktree.encl_int_gate = devm_clk_get(lcd_drv->dev, "encl_int_gate"); + if (IS_ERR(lcd_clktree.encl_int_gate)) + LCDERR("%s: clk encl_int_gate\n", __func__); + + lcd_clktree.gp0_pll = devm_clk_get(lcd_drv->dev, "gp0_pll"); + if (IS_ERR(lcd_clktree.gp0_pll)) + LCDERR("%s: clk gp0_pll\n", __func__); + + LCDPR("lcd_clktree_probe\n"); +} + +static void lcd_clktree_probe_tl1(void) +{ + struct aml_lcd_drv_s *lcd_drv = aml_lcd_get_driver(); + struct clk *temp_clk; + + lcd_clktree.clk_gate_state = 0; + + lcd_clktree.encl_top_gate = devm_clk_get(lcd_drv->dev, "encl_top_gate"); + if (IS_ERR(lcd_clktree.encl_top_gate)) + LCDERR("%s: get encl_top_gate error\n", __func__); + + lcd_clktree.encl_int_gate = devm_clk_get(lcd_drv->dev, "encl_int_gate"); + if (IS_ERR(lcd_clktree.encl_int_gate)) + LCDERR("%s: get encl_int_gate error\n", __func__); + + switch (lcd_drv->lcd_config->lcd_basic.lcd_type) { + case LCD_MLVDS: + case LCD_P2P: + lcd_clktree.tcon_gate = devm_clk_get(lcd_drv->dev, "tcon_gate"); + if (IS_ERR(lcd_clktree.tcon_gate)) + LCDERR("%s: get tcon_gate error\n", __func__); + + temp_clk = devm_clk_get(lcd_drv->dev, "fclk_div5"); + if (IS_ERR(temp_clk)) { + LCDERR("%s: clk fclk_div5\n", __func__); + return; + } + lcd_clktree.tcon_clk = devm_clk_get(lcd_drv->dev, "clk_tcon"); + if (IS_ERR(lcd_clktree.tcon_clk)) + LCDERR("%s: clk clk_tcon\n", __func__); else - lcd_clk_generate_hpll_g12a(pconf); + clk_set_parent(lcd_clktree.tcon_clk, temp_clk); + break; + default: + break; + } + + LCDPR("lcd_clktree_probe\n"); +} + +static void lcd_clktree_remove_dft(void) +{ + struct aml_lcd_drv_s *lcd_drv = aml_lcd_get_driver(); + + if (lcd_debug_print_flag) + LCDPR("lcd_clktree_remove\n"); + + if (!IS_ERR(lcd_clktree.encl_top_gate)) + devm_clk_put(lcd_drv->dev, lcd_clktree.encl_top_gate); + if (!IS_ERR(lcd_clktree.encl_int_gate)) + devm_clk_put(lcd_drv->dev, lcd_clktree.encl_int_gate); +} + +static void lcd_clktree_remove_axg(void) +{ + struct aml_lcd_drv_s *lcd_drv = aml_lcd_get_driver(); + + if (lcd_debug_print_flag) + LCDPR("lcd_clktree_remove\n"); + + if (!IS_ERR(lcd_clktree.mipi_bandgap_gate)) + devm_clk_put(lcd_drv->dev, lcd_clktree.mipi_bandgap_gate); + if (!IS_ERR(lcd_clktree.mipi_enable_gate)) + devm_clk_put(lcd_drv->dev, lcd_clktree.mipi_enable_gate); + if (!IS_ERR(lcd_clktree.dsi_meas)) + devm_clk_put(lcd_drv->dev, lcd_clktree.dsi_meas); + if (!IS_ERR(lcd_clktree.dsi_phy_gate)) + devm_clk_put(lcd_drv->dev, lcd_clktree.dsi_phy_gate); + if (!IS_ERR(lcd_clktree.dsi_host_gate)) + devm_clk_put(lcd_drv->dev, lcd_clktree.dsi_host_gate); + if (!IS_ERR(lcd_clktree.gp0_pll)) + devm_clk_put(lcd_drv->dev, lcd_clktree.gp0_pll); +} + +static void lcd_clktree_remove_g12a(void) +{ + struct aml_lcd_drv_s *lcd_drv = aml_lcd_get_driver(); + + if (lcd_debug_print_flag) + LCDPR("lcd_clktree_remove\n"); + + if (!IS_ERR(lcd_clktree.dsi_host_gate)) + devm_clk_put(lcd_drv->dev, lcd_clktree.dsi_host_gate); + if (!IS_ERR(lcd_clktree.dsi_phy_gate)) + devm_clk_put(lcd_drv->dev, lcd_clktree.dsi_phy_gate); + if (!IS_ERR(lcd_clktree.dsi_meas)) + devm_clk_put(lcd_drv->dev, lcd_clktree.dsi_meas); + if (!IS_ERR(lcd_clktree.encl_top_gate)) + devm_clk_put(lcd_drv->dev, lcd_clktree.encl_top_gate); + if (!IS_ERR(lcd_clktree.encl_int_gate)) + devm_clk_put(lcd_drv->dev, lcd_clktree.encl_int_gate); +} + +static void lcd_clktree_remove_tl1(void) +{ + struct aml_lcd_drv_s *lcd_drv = aml_lcd_get_driver(); + + if (lcd_debug_print_flag) + LCDPR("lcd_clktree_remove\n"); + + if (!IS_ERR(lcd_clktree.encl_top_gate)) + devm_clk_put(lcd_drv->dev, lcd_clktree.encl_top_gate); + if (!IS_ERR(lcd_clktree.encl_int_gate)) + devm_clk_put(lcd_drv->dev, lcd_clktree.encl_int_gate); + + switch (lcd_drv->lcd_config->lcd_basic.lcd_type) { + case LCD_MLVDS: + case LCD_P2P: + if (!IS_ERR(lcd_clktree.tcon_clk)) + devm_clk_put(lcd_drv->dev, lcd_clktree.tcon_clk); + if (IS_ERR(lcd_clktree.tcon_gate)) + devm_clk_put(lcd_drv->dev, lcd_clktree.tcon_gate); break; default: break; } } -static char lcd_ss_str[10] = { - 'u', 'n', 'k', 'n', 'o', 'w', 'n', '\0', -}; +static void lcd_clk_config_init_print_dft(void) +{ + struct lcd_clk_data_s *data = clk_conf.data; + + LCDPR("lcd clk config data init:\n" + "pll_m_max: %d\n" + "pll_m_min: %d\n" + "pll_n_max: %d\n" + "pll_n_min: %d\n" + "pll_od_fb: %d\n" + "pll_frac_range: %d\n" + "pll_od_sel_max: %d\n" + "pll_ref_fmax: %d\n" + "pll_ref_fmin: %d\n" + "pll_vco_fmax: %d\n" + "pll_vco_fmin: %d\n" + "pll_out_fmax: %d\n" + "pll_out_fmin: %d\n" + "div_in_fmax: %d\n" + "div_out_fmax: %d\n" + "xd_out_fmax: %d\n" + "ss_level_max: %d\n\n", + data->pll_m_max, data->pll_m_min, + data->pll_n_max, data->pll_n_min, + data->pll_od_fb, data->pll_frac_range, + data->pll_od_sel_max, + data->pll_ref_fmax, data->pll_ref_fmin, + data->pll_vco_fmax, data->pll_vco_fmin, + data->pll_out_fmax, data->pll_out_fmin, + data->div_in_fmax, data->div_out_fmax, + data->xd_out_fmax, data->ss_level_max); +} + +static void lcd_clk_config_init_print_axg(void) +{ + struct lcd_clk_data_s *data = clk_conf.data; + + LCDPR("lcd clk config data init:\n" + "vclk_sel: %d\n" + "pll_m_max: %d\n" + "pll_m_min: %d\n" + "pll_n_max: %d\n" + "pll_n_min: %d\n" + "pll_od_fb: %d\n" + "pll_frac_range: %d\n" + "pll_od_sel_max: %d\n" + "pll_ref_fmax: %d\n" + "pll_ref_fmin: %d\n" + "pll_vco_fmax: %d\n" + "pll_vco_fmin: %d\n" + "pll_out_fmax: %d\n" + "pll_out_fmin: %d\n" + "xd_out_fmax: %d\n" + "ss_level_max: %d\n\n", + data->vclk_sel, + data->pll_m_max, data->pll_m_min, + data->pll_n_max, data->pll_n_min, + data->pll_od_fb, data->pll_frac_range, + data->pll_od_sel_max, + data->pll_ref_fmax, data->pll_ref_fmin, + data->pll_vco_fmax, data->pll_vco_fmin, + data->pll_out_fmax, data->pll_out_fmin, + data->xd_out_fmax, data->ss_level_max); +} + +static int lcd_clk_config_print_dft(char *buf, int offset) +{ + int n, len = 0; + + n = lcd_debug_info_len(len + offset); + len += snprintf((buf+len), n, + "lcd clk config:\n" + "pll_mode: %d\n" + "pll_m: %d\n" + "pll_n: %d\n" + "pll_frac: 0x%03x\n" + "pll_fvco: %dkHz\n" + "pll_od1: %d\n" + "pll_od2: %d\n" + "pll_od3: %d\n" + "pll_pi_div_sel: %d\n" + "pll_out: %dkHz\n" + "div_sel: %s(index %d)\n" + "xd: %d\n" + "fout: %dkHz\n" + "ss_level: %d\n\n", + clk_conf.pll_mode, clk_conf.pll_m, clk_conf.pll_n, + clk_conf.pll_frac, clk_conf.pll_fvco, + clk_conf.pll_od1_sel, clk_conf.pll_od2_sel, + clk_conf.pll_od3_sel, clk_conf.pll_pi_div_sel, + clk_conf.pll_fout, + lcd_clk_div_sel_table[clk_conf.div_sel], + clk_conf.div_sel, clk_conf.xd, + clk_conf.fout, clk_conf.ss_level); + + return len; +} + +static int lcd_clk_config_print_axg(char *buf, int offset) +{ + int n, len = 0; + + n = lcd_debug_info_len(len + offset); + len += snprintf((buf+len), n, + "lcd clk config:\n" + "pll_m: %d\n" + "pll_n: %d\n" + "pll_frac: 0x%03x\n" + "pll_fvco: %dkHz\n" + "pll_od: %d\n" + "pll_out: %dkHz\n" + "xd: %d\n" + "fout: %dkHz\n" + "ss_level: %d\n\n", + clk_conf.pll_m, clk_conf.pll_n, + clk_conf.pll_frac, clk_conf.pll_fvco, + clk_conf.pll_od1_sel, clk_conf.pll_fout, + clk_conf.xd, clk_conf.fout, clk_conf.ss_level); + + return len; +} + +static int lcd_clk_config_print_g12a(char *buf, int offset) +{ + int n, len = 0; + + n = lcd_debug_info_len(len + offset); + if (clk_conf.data->vclk_sel) { + len += snprintf((buf+len), n, + "lcd clk config:\n" + "vclk_sel %d\n" + "pll_m: %d\n" + "pll_n: %d\n" + "pll_frac: 0x%03x\n" + "pll_fvco: %dkHz\n" + "pll_od: %d\n" + "pll_out: %dkHz\n" + "xd: %d\n" + "fout: %dkHz\n" + "ss_level: %d\n\n", + clk_conf.data->vclk_sel, + clk_conf.pll_m, clk_conf.pll_n, + clk_conf.pll_frac, clk_conf.pll_fvco, + clk_conf.pll_od1_sel, clk_conf.pll_fout, + clk_conf.xd, clk_conf.fout, clk_conf.ss_level); + } else { + len += snprintf((buf+len), n, + "lcd clk config:\n" + "vclk_sel %d\n" + "pll_m: %d\n" + "pll_n: %d\n" + "pll_frac: 0x%03x\n" + "pll_fvco: %dkHz\n" + "pll_od1: %d\n" + "pll_od2: %d\n" + "pll_od3: %d\n" + "pll_out: %dkHz\n" + "div_sel: %s(index %d)\n" + "xd: %d\n" + "fout: %dkHz\n" + "ss_level: %d\n\n", + clk_conf.data->vclk_sel, + clk_conf.pll_m, clk_conf.pll_n, + clk_conf.pll_frac, clk_conf.pll_fvco, + clk_conf.pll_od1_sel, clk_conf.pll_od2_sel, + clk_conf.pll_od3_sel, clk_conf.pll_fout, + lcd_clk_div_sel_table[clk_conf.div_sel], + clk_conf.div_sel, clk_conf.xd, + clk_conf.fout, clk_conf.ss_level); + } + + return len; +} + +/* **************************************************** + * lcd clk function api + * **************************************************** + */ +void lcd_clk_generate_parameter(struct lcd_config_s *pconf) +{ + if (clk_conf.data == NULL) { + LCDERR("%s: clk config data is null\n", __func__); + return; + } + + if (clk_conf.data->clk_generate_parameter) + clk_conf.data->clk_generate_parameter(pconf); +} + +static char lcd_ss_invalid_str[10] = {'i', 'n', 'v', 'a', 'l', 'i', 'd', '\0',}; char *lcd_get_spread_spectrum(void) { - char *ss_str; - unsigned int ss_level; - struct aml_lcd_drv_s *lcd_drv = aml_lcd_get_driver(); + char *ss_str = lcd_ss_invalid_str; + unsigned int level; - ss_level = lcd_drv->lcd_config->lcd_timing.ss_level; - ss_level = (ss_level >= clk_conf.ss_level_max) ? 0 : ss_level; - switch (lcd_drv->data->chip_type) { - case LCD_CHIP_GXTVBB: - ss_str = lcd_pll_ss_table_gxtvbb[ss_level]; - break; - case LCD_CHIP_TXL: - ss_str = lcd_pll_ss_table_txl[ss_level]; - break; - case LCD_CHIP_TXLX: - ss_str = lcd_pll_ss_table_txlx[ss_level]; - break; - default: - ss_str = lcd_ss_str; - break; + level = clk_conf.ss_level; + if (clk_conf.data) { + level = (level >= clk_conf.data->ss_level_max) ? 0 : level; + if (clk_conf.data->pll_ss_table) + ss_str = clk_conf.data->pll_ss_table[level]; } return ss_str; } -void lcd_set_spread_spectrum(void) +void lcd_set_spread_spectrum(unsigned int ss_level) { unsigned long flags = 0; - int ss_level; - struct aml_lcd_drv_s *lcd_drv = aml_lcd_get_driver(); spin_lock_irqsave(&lcd_clk_lock, flags); + if (clk_conf.data == NULL) { + LCDERR("%s: clk config data is null\n", __func__); + goto lcd_set_spread_spectrum_end; + } + + clk_conf.ss_level = (ss_level >= clk_conf.data->ss_level_max) ? + 0 : ss_level; + if (clk_conf.data->set_spread_spectrum) + clk_conf.data->set_spread_spectrum(clk_conf.ss_level); + +lcd_set_spread_spectrum_end: + spin_unlock_irqrestore(&lcd_clk_lock, flags); + if (lcd_debug_print_flag) LCDPR("%s\n", __func__); - - ss_level = lcd_drv->lcd_config->lcd_timing.ss_level; - clk_conf.ss_level = (ss_level >= clk_conf.ss_level_max) ? 0 : ss_level; - switch (lcd_drv->data->chip_type) { - case LCD_CHIP_GXTVBB: - lcd_set_pll_ss_gxtvbb(&clk_conf); - break; - case LCD_CHIP_TXL: - lcd_set_pll_ss_txl(&clk_conf); - break; - case LCD_CHIP_TXLX: - lcd_set_pll_ss_txlx(&clk_conf); - break; - default: - break; - } - spin_unlock_irqrestore(&lcd_clk_lock, flags); } int lcd_encl_clk_msr(void) @@ -2316,144 +2146,99 @@ int lcd_encl_clk_msr(void) void lcd_pll_reset(void) { + struct lcd_clk_ctrl_s *table; + int i = 0; unsigned long flags = 0; - struct aml_lcd_drv_s *lcd_drv = aml_lcd_get_driver(); spin_lock_irqsave(&lcd_clk_lock, flags); - LCDPR("%s\n", __func__); - switch (lcd_drv->data->chip_type) { - case LCD_CHIP_GXTVBB: - lcd_pll_reset_gxtvbb(); - break; - case LCD_CHIP_GXL: - case LCD_CHIP_GXM: - case LCD_CHIP_TXL: - case LCD_CHIP_TXLX: - lcd_pll_reset_txl(); - break; - case LCD_CHIP_AXG: - lcd_pll_reset_axg(); - break; - case LCD_CHIP_G12A: - case LCD_CHIP_G12B: - if (lcd_drv->lcd_clk_path) - lcd_gp0_pll_reset_g12a(); - else - lcd_hpll_reset_g12a(); - break; - default: - break; + if (clk_conf.data == NULL) { + LCDERR("%s: clk config data is null\n", __func__); + goto lcd_pll_reset_end; + } + if (clk_conf.data->pll_ctrl_table == NULL) + goto lcd_pll_reset_end; + + table = clk_conf.data->pll_ctrl_table; + while (i < LCD_CLK_CTRL_CNT_MAX) { + if (table[i].flag == LCD_CLK_CTRL_END) + break; + if (table[i].flag == LCD_CLK_CTRL_RST) { + lcd_hiu_setb(table[i].reg, 1, + table[i].bit, table[i].len); + udelay(10); + lcd_hiu_setb(table[i].reg, 0, + table[i].bit, table[i].len); + } + i++; } +lcd_pll_reset_end: spin_unlock_irqrestore(&lcd_clk_lock, flags); + LCDPR("%s\n", __func__); } /* for frame rate change */ void lcd_clk_update(struct lcd_config_s *pconf) { + struct lcd_clk_ctrl_s *table; + int i = 0; unsigned long flags = 0; - struct aml_lcd_drv_s *lcd_drv = aml_lcd_get_driver(); spin_lock_irqsave(&lcd_clk_lock, flags); - LCDPR("%s\n", __func__); - switch (lcd_drv->data->chip_type) { - case LCD_CHIP_GXTVBB: - lcd_pll_frac_generate_gxtvbb(pconf); - lcd_update_pll_frac_gxtvbb(&clk_conf); - break; - case LCD_CHIP_GXL: - case LCD_CHIP_GXM: - case LCD_CHIP_TXL: - case LCD_CHIP_TXLX: - lcd_pll_frac_generate_txl(pconf); - lcd_update_pll_frac_txl(&clk_conf); - break; - case LCD_CHIP_AXG: - lcd_pll_frac_generate_axg(pconf); - lcd_update_pll_frac_axg(&clk_conf); - break; - case LCD_CHIP_G12A: - case LCD_CHIP_G12B: - if (lcd_drv->lcd_clk_path) { - lcd_pll_frac_generate_axg(pconf); - lcd_update_gp0_pll_frac_g12a(&clk_conf); - } else { - lcd_pll_frac_generate_txl(pconf); - lcd_update_hpll_frac_g12a(&clk_conf); - } - break; - default: - break; + if (clk_conf.data == NULL) { + LCDERR("%s: clk config data is null\n", __func__); + goto lcd_clk_update_end; } + if (clk_conf.data->pll_frac_generate) + clk_conf.data->pll_frac_generate(pconf); + + if (clk_conf.data->pll_ctrl_table == NULL) + goto lcd_clk_update_end; + table = clk_conf.data->pll_ctrl_table; + while (i < LCD_CLK_CTRL_CNT_MAX) { + if (table[i].flag == LCD_CLK_CTRL_END) + break; + if (table[i].flag == LCD_CLK_CTRL_FRAC) { + lcd_hiu_setb(table[i].reg, clk_conf.pll_frac, + table[i].bit, table[i].len); + } + i++; + } + +lcd_clk_update_end: spin_unlock_irqrestore(&lcd_clk_lock, flags); + LCDPR("%s\n", __func__); } /* for timing change */ void lcd_clk_set(struct lcd_config_s *pconf) { unsigned long flags = 0; - struct aml_lcd_drv_s *lcd_drv = aml_lcd_get_driver(); + + if (clk_conf.data == NULL) { + LCDERR("%s: clk config data is null\n", __func__); + return; + } spin_lock_irqsave(&lcd_clk_lock, flags); + if (clk_conf.data->clk_set) + clk_conf.data->clk_set(pconf); - if (lcd_debug_print_flag) - LCDPR("%s\n", __func__); - - switch (lcd_drv->data->chip_type) { - case LCD_CHIP_GXTVBB: - lcd_set_pll_gxtvbb(&clk_conf); - lcd_set_vid_pll_div(&clk_conf); - break; - case LCD_CHIP_GXL: - case LCD_CHIP_GXM: - case LCD_CHIP_TXL: - lcd_set_pll_txl(&clk_conf); - lcd_set_vid_pll_div(&clk_conf); - break; - case LCD_CHIP_TXLX: - lcd_set_pll_txlx(&clk_conf); - lcd_set_vid_pll_div(&clk_conf); - break; - case LCD_CHIP_AXG: - lcd_set_pll_axg(&clk_conf); - break; - case LCD_CHIP_G12A: - if (lcd_drv->lcd_clk_path) { /* gp0_pll */ - lcd_set_gp0_pll_g12a(&clk_conf); - lcd_set_dsi_phy_clk(1); - } else { /* hpll */ - lcd_set_hpll_g12a(&clk_conf); - lcd_set_vid_pll_div(&clk_conf); - lcd_set_dsi_phy_clk(0); - } - break; - case LCD_CHIP_G12B: - if (lcd_drv->lcd_clk_path) { /* gp0_pll */ - lcd_set_gp0_pll_g12b(&clk_conf); - lcd_set_dsi_phy_clk(1); - } else { /* hpll */ - lcd_set_hpll_g12b(&clk_conf); - lcd_set_vid_pll_div(&clk_conf); - lcd_set_dsi_phy_clk(0); - } - break; - default: - break; - } lcd_set_vclk_crt(pconf->lcd_basic.lcd_type, &clk_conf); mdelay(10); spin_unlock_irqrestore(&lcd_clk_lock, flags); + + if (lcd_debug_print_flag) + LCDPR("%s\n", __func__); } void lcd_clk_disable(void) { - struct aml_lcd_drv_s *lcd_drv = aml_lcd_get_driver(); - - if (lcd_debug_print_flag) - LCDPR("%s\n", __func__); + struct lcd_clk_ctrl_s *table; + int i = 0; lcd_hiu_setb(HHI_VID_CLK_CNTL2, 0, ENCL_GATE_VCLK, 1); @@ -2461,38 +2246,23 @@ void lcd_clk_disable(void) lcd_hiu_setb(HHI_VIID_CLK_CNTL, 0, 0, 5); lcd_hiu_setb(HHI_VIID_CLK_CNTL, 0, VCLK2_EN, 1); - /* disable pll */ - switch (lcd_drv->data->chip_type) { - case LCD_CHIP_GXTVBB: - /* disable hdmi_pll: 0x10c8[30] */ - lcd_hiu_setb(HHI_HDMI_PLL_CNTL, 0, LCD_PLL_EN_GXTVBB, 1); - lcd_hiu_setb(HHI_HDMI_PLL_CNTL5, 0, 30, 1); /* bandgap */ - break; - case LCD_CHIP_GXL: - case LCD_CHIP_GXM: - case LCD_CHIP_TXL: - case LCD_CHIP_TXLX: - /* disable hdmi_pll: 0x10c8[30] */ - lcd_hiu_setb(HHI_HDMI_PLL_CNTL, 0, LCD_PLL_EN_TXL, 1); - break; - case LCD_CHIP_AXG: - /* disable hdmi_pll: 0x10c8[30] */ - lcd_hiu_setb(HHI_GP0_PLL_CNTL_AXG, 0, LCD_PLL_EN_AXG, 1); - break; - case LCD_CHIP_G12A: - case LCD_CHIP_G12B: - if (lcd_drv->lcd_clk_path) { - lcd_hiu_setb(HHI_GP0_PLL_CNTL0_G12A, - 0, LCD_PLL_EN_GP0_G12A, 1); - } else { - /* disable hdmi_pll: 0x10c8[28] */ - lcd_hiu_setb(HHI_HDMI_PLL_CNTL, - 0, LCD_PLL_EN_HPLL_G12A, 1); + if (clk_conf.data == NULL) + return; + if (clk_conf.data->pll_ctrl_table == NULL) + return; + table = clk_conf.data->pll_ctrl_table; + while (i < LCD_CLK_CTRL_CNT_MAX) { + if (table[i].flag == LCD_CLK_CTRL_END) + break; + if (table[i].flag == LCD_CLK_CTRL_EN) { + lcd_hiu_setb(table[i].reg, 0, + table[i].bit, table[i].len); } - break; - default: - break; + i++; } + + if (lcd_debug_print_flag) + LCDPR("%s\n", __func__); } void lcd_clk_gate_switch(int status) @@ -2500,298 +2270,479 @@ void lcd_clk_gate_switch(int status) struct aml_lcd_drv_s *lcd_drv = aml_lcd_get_driver(); if (status) { - if (lcd_drv->clk_gate_state) { + if (lcd_clktree.clk_gate_state) { LCDPR("clk gate is already on\n"); return; } - #ifdef CONFIG_AMLOGIC_VPU switch_vpu_clk_gate_vmod(VPU_VENCL, VPU_CLK_GATE_ON); #endif - switch (lcd_drv->data->chip_type) { - case LCD_CHIP_AXG: - if (IS_ERR(lcd_drv->dsi_host_gate)) - LCDERR("%s: dsi_host_gate\n", __func__); - else - clk_prepare_enable(lcd_drv->dsi_host_gate); - if (IS_ERR(lcd_drv->dsi_phy_gate)) - LCDERR("%s: dsi_phy_gate\n", __func__); - else - clk_prepare_enable(lcd_drv->dsi_phy_gate); - if (IS_ERR(lcd_drv->dsi_meas)) - LCDERR("%s: dsi_meas\n", __func__); - else - clk_prepare_enable(lcd_drv->dsi_meas); - if (IS_ERR(lcd_drv->mipi_enable_gate)) - LCDERR("%s: mipi_enable_gate\n", __func__); - else - clk_prepare_enable(lcd_drv->mipi_enable_gate); - if (IS_ERR(lcd_drv->mipi_bandgap_gate)) - LCDERR("%s: mipi_bandgap_gate\n", __func__); - else - clk_prepare_enable(lcd_drv->mipi_bandgap_gate); - break; - case LCD_CHIP_G12A: - case LCD_CHIP_G12B: - if (lcd_drv->lcd_clk_path) { - if (IS_ERR(lcd_drv->gp0_pll)) - LCDERR("%s: gp0_pll\n", __func__); - else - clk_prepare_enable(lcd_drv->gp0_pll); - } - - if (IS_ERR(lcd_drv->dsi_host_gate)) - LCDERR("%s: dsi_host_gate\n", __func__); - else - clk_prepare_enable(lcd_drv->dsi_host_gate); - if (IS_ERR(lcd_drv->dsi_phy_gate)) - LCDERR("%s: dsi_phy_gate\n", __func__); - else - clk_prepare_enable(lcd_drv->dsi_phy_gate); - if (IS_ERR(lcd_drv->dsi_meas)) - LCDERR("%s: dsi_meas\n", __func__); - else - clk_prepare_enable(lcd_drv->dsi_meas); - if (IS_ERR(lcd_drv->encl_top_gate)) - LCDERR("%s: encl_top_gate\n", __func__); - else - clk_prepare_enable(lcd_drv->encl_top_gate); - if (IS_ERR(lcd_drv->encl_int_gate)) - LCDERR("%s: encl_int_gata\n", __func__); - else - clk_prepare_enable(lcd_drv->encl_int_gate); - break; - default: - if (IS_ERR(lcd_drv->encl_top_gate)) - LCDERR("%s: encl_top_gate\n", __func__); - else - clk_prepare_enable(lcd_drv->encl_top_gate); - if (IS_ERR(lcd_drv->encl_int_gate)) - LCDERR("%s: encl_int_gata\n", __func__); - else - clk_prepare_enable(lcd_drv->encl_int_gate); - break; + if (clk_conf.data) { + if (clk_conf.data->clk_gate_switch) + clk_conf.data->clk_gate_switch(lcd_drv, 1); } - lcd_drv->clk_gate_state = 1; + lcd_clktree.clk_gate_state = 1; } else { - if (lcd_drv->clk_gate_state == 0) { + if (lcd_clktree.clk_gate_state == 0) { LCDPR("clk gate is already off\n"); return; } - switch (lcd_drv->data->chip_type) { - case LCD_CHIP_AXG: - if (IS_ERR(lcd_drv->dsi_host_gate)) - LCDERR("%s: dsi_host_gate\n", __func__); - else - clk_disable_unprepare( - lcd_drv->dsi_host_gate); - if (IS_ERR(lcd_drv->dsi_phy_gate)) - LCDERR("%s: dsi_phy_gate\n", __func__); - else - clk_disable_unprepare( - lcd_drv->dsi_phy_gate); - if (IS_ERR(lcd_drv->dsi_meas)) - LCDERR("%s: dsi_meas\n", __func__); - else - clk_disable_unprepare( - lcd_drv->dsi_meas); - if (IS_ERR(lcd_drv->mipi_enable_gate)) - LCDERR("%s: mipi_enable_gate\n", __func__); - else - clk_disable_unprepare( - lcd_drv->mipi_enable_gate); - if (IS_ERR(lcd_drv->mipi_bandgap_gate)) - LCDERR("%s: mipi_bandgap_gate\n", __func__); - else - clk_disable_unprepare( - lcd_drv->mipi_bandgap_gate); - break; - case LCD_CHIP_G12A: - case LCD_CHIP_G12B: - if (IS_ERR(lcd_drv->dsi_host_gate)) - LCDERR("%s: dsi_host_gate\n", __func__); - else - clk_disable_unprepare( - lcd_drv->dsi_host_gate); - if (IS_ERR(lcd_drv->dsi_phy_gate)) - LCDERR("%s: dsi_phy_gate\n", __func__); - else - clk_disable_unprepare( - lcd_drv->dsi_phy_gate); - if (IS_ERR(lcd_drv->dsi_meas)) - LCDERR("%s: dsi_meas\n", __func__); - else - clk_disable_unprepare( - lcd_drv->dsi_meas); - if (IS_ERR(lcd_drv->encl_int_gate)) - LCDERR("%s: encl_int_gate\n", __func__); - else - clk_disable_unprepare( - lcd_drv->encl_int_gate); - if (IS_ERR(lcd_drv->encl_top_gate)) - LCDERR("%s: encl_top_gate\n", __func__); - else - clk_disable_unprepare( - lcd_drv->encl_top_gate); - - if (lcd_drv->lcd_clk_path) { - if (IS_ERR(lcd_drv->gp0_pll)) - LCDERR("%s: gp0_pll\n", __func__); - else - clk_disable_unprepare(lcd_drv->gp0_pll); - } - break; - default: - if (IS_ERR(lcd_drv->encl_int_gate)) - LCDERR("%s: encl_int_gata\n", __func__); - else - clk_disable_unprepare(lcd_drv->encl_int_gate); - if (IS_ERR(lcd_drv->encl_top_gate)) - LCDERR("%s: encl_top_gata\n", __func__); - else - clk_disable_unprepare(lcd_drv->encl_top_gate); - break; + if (clk_conf.data) { + if (clk_conf.data->clk_gate_switch) + clk_conf.data->clk_gate_switch(lcd_drv, 0); } #ifdef CONFIG_AMLOGIC_VPU switch_vpu_clk_gate_vmod(VPU_VENCL, VPU_CLK_GATE_OFF); #endif - lcd_drv->clk_gate_state = 0; + lcd_clktree.clk_gate_state = 0; } } -static void lcd_clktree_probe(void) +static void lcd_clk_config_init_print(void) { - struct aml_lcd_drv_s *lcd_drv = aml_lcd_get_driver(); - - lcd_drv->clk_gate_state = 0; - switch (lcd_drv->data->chip_type) { - case LCD_CHIP_AXG: - lcd_drv->dsi_host_gate = devm_clk_get(lcd_drv->dev, - "dsi_host_gate"); - if (IS_ERR(lcd_drv->dsi_host_gate)) - LCDERR("%s: clk dsi_host_gate\n", __func__); - - lcd_drv->dsi_phy_gate = devm_clk_get(lcd_drv->dev, - "dsi_phy_gate"); - if (IS_ERR(lcd_drv->dsi_phy_gate)) - LCDERR("%s: clk dsi_phy_gate\n", __func__); - - lcd_drv->dsi_meas = devm_clk_get(lcd_drv->dev, - "dsi_meas"); - if (IS_ERR(lcd_drv->dsi_meas)) - LCDERR("%s: clk dsi_meas\n", __func__); - - lcd_drv->mipi_enable_gate = devm_clk_get( - lcd_drv->dev, "mipi_enable_gate"); - if (IS_ERR(lcd_drv->mipi_enable_gate)) - LCDERR("%s: clk mipi_enable_gate\n", __func__); - - lcd_drv->mipi_bandgap_gate = devm_clk_get( - lcd_drv->dev, "mipi_bandgap_gate"); - if (IS_ERR(lcd_drv->mipi_bandgap_gate)) - LCDERR("%s: clk mipi_bandgap_gate\n", __func__); - break; - case LCD_CHIP_G12A: - case LCD_CHIP_G12B: - lcd_drv->dsi_host_gate = devm_clk_get(lcd_drv->dev, - "dsi_host_gate"); - if (IS_ERR(lcd_drv->dsi_host_gate)) - LCDERR("%s: clk dsi_host_gate\n", __func__); - - lcd_drv->dsi_phy_gate = devm_clk_get(lcd_drv->dev, - "dsi_phy_gate"); - if (IS_ERR(lcd_drv->dsi_phy_gate)) - LCDERR("%s: clk dsi_phy_gate\n", __func__); - - lcd_drv->dsi_meas = devm_clk_get(lcd_drv->dev, - "dsi_meas"); - if (IS_ERR(lcd_drv->dsi_meas)) - LCDERR("%s: clk dsi_meas\n", __func__); - - lcd_drv->encl_top_gate = devm_clk_get( - lcd_drv->dev, "encl_top_gate"); - if (IS_ERR(lcd_drv->encl_top_gate)) - LCDERR("%s: clk encl_top_gate\n", __func__); - - lcd_drv->encl_int_gate = devm_clk_get( - lcd_drv->dev, "encl_int_gate"); - if (IS_ERR(lcd_drv->encl_int_gate)) - LCDERR("%s: clk encl_int_gate\n", __func__); - - lcd_drv->gp0_pll = devm_clk_get(lcd_drv->dev, "gp0_pll"); - if (IS_ERR(lcd_drv->gp0_pll)) - LCDERR("%s: clk gp0_pll\n", __func__); - break; - default: - lcd_drv->encl_top_gate = devm_clk_get(lcd_drv->dev, - "encl_top_gate"); - if (IS_ERR(lcd_drv->encl_top_gate)) - LCDERR("%s: get encl_top_gate error\n", __func__); - - lcd_drv->encl_int_gate = devm_clk_get(lcd_drv->dev, - "encl_int_gate"); - if (IS_ERR(lcd_drv->encl_int_gate)) - LCDERR("%s: get encl_int_gate error\n", __func__); - break; + if (clk_conf.data == NULL) { + LCDERR("%s: clk config data is null\n", __func__); + return; } - LCDPR("%s\n", __func__); + if (clk_conf.data->clk_config_init_print) + clk_conf.data->clk_config_init_print(); } -static void lcd_clktree_remove(void) +int lcd_clk_config_print(char *buf, int offset) +{ + int n, len = 0; + + if (clk_conf.data == NULL) { + n = lcd_debug_info_len(len + offset); + len += snprintf((buf+len), n, + "%s: clk config data is null\n", + __func__); + return len; + } + + if (clk_conf.data->clk_config_print) + len = clk_conf.data->clk_config_print(buf, offset); + + return len; +} + +/* **************************************************** + * lcd clk config + * **************************************************** + */ +static struct lcd_clk_data_s lcd_clk_data_gxl = { + .pll_od_fb = PLL_OD_FB_GXL, + .pll_m_max = PLL_M_MAX_GXL, + .pll_m_min = PLL_M_MIN_GXL, + .pll_n_max = PLL_N_MAX_GXL, + .pll_n_min = PLL_N_MIN_GXL, + .pll_frac_range = PLL_FRAC_RANGE_GXL, + .pll_od_sel_max = PLL_OD_SEL_MAX_GXL, + .pll_ref_fmax = PLL_FREF_MAX_GXL, + .pll_ref_fmin = PLL_FREF_MIN_GXL, + .pll_vco_fmax = PLL_VCO_MAX_GXL, + .pll_vco_fmin = PLL_VCO_MIN_GXL, + .pll_out_fmax = CLK_DIV_IN_MAX_GXL, + .pll_out_fmin = PLL_VCO_MIN_GXL / 16, + .div_in_fmax = CLK_DIV_IN_MAX_GXL, + .div_out_fmax = CRT_VID_CLK_IN_MAX_GXL, + .xd_out_fmax = ENCL_CLK_IN_MAX_GXL, + .ss_level_max = SS_LEVEL_MAX_GXL, + + .clk_path_valid = 0, + .vclk_sel = 0, + .pll_ctrl_table = pll_ctrl_table_txl, + .pll_ss_table = NULL, + + .clk_generate_parameter = lcd_clk_generate_txl, + .pll_frac_generate = lcd_pll_frac_generate_txl, + .set_spread_spectrum = NULL, + .clk_set = lcd_clk_set_txl, + .clk_gate_switch = lcd_clk_gate_switch_dft, + .clktree_probe = lcd_clktree_probe_dft, + .clktree_remove = lcd_clktree_remove_dft, + .clk_config_init_print = lcd_clk_config_init_print_dft, + .clk_config_print = lcd_clk_config_print_dft, +}; + +static struct lcd_clk_data_s lcd_clk_data_txl = { + .pll_od_fb = PLL_OD_FB_TXL, + .pll_m_max = PLL_M_MAX_TXL, + .pll_m_min = PLL_M_MIN_TXL, + .pll_n_max = PLL_N_MAX_TXL, + .pll_n_min = PLL_N_MIN_TXL, + .pll_frac_range = PLL_FRAC_RANGE_TXL, + .pll_od_sel_max = PLL_OD_SEL_MAX_TXL, + .pll_ref_fmax = PLL_FREF_MAX_TXL, + .pll_ref_fmin = PLL_FREF_MIN_TXL, + .pll_vco_fmax = PLL_VCO_MAX_TXL, + .pll_vco_fmin = PLL_VCO_MIN_TXL, + .pll_out_fmax = CLK_DIV_IN_MAX_TXL, + .pll_out_fmin = PLL_VCO_MIN_TXL / 16, + .div_in_fmax = CLK_DIV_IN_MAX_TXL, + .div_out_fmax = CRT_VID_CLK_IN_MAX_TXL, + .xd_out_fmax = ENCL_CLK_IN_MAX_TXL, + .ss_level_max = SS_LEVEL_MAX_TXL, + + .clk_path_valid = 0, + .vclk_sel = 0, + .pll_ctrl_table = pll_ctrl_table_txl, + .pll_ss_table = lcd_pll_ss_table_txl, + + .clk_generate_parameter = lcd_clk_generate_txl, + .pll_frac_generate = lcd_pll_frac_generate_txl, + .set_spread_spectrum = lcd_set_pll_ss_txl, + .clk_set = lcd_clk_set_txl, + .clk_gate_switch = lcd_clk_gate_switch_dft, + .clktree_probe = lcd_clktree_probe_dft, + .clktree_remove = lcd_clktree_remove_dft, + .clk_config_init_print = lcd_clk_config_init_print_dft, + .clk_config_print = lcd_clk_config_print_dft, +}; + +static struct lcd_clk_data_s lcd_clk_data_txlx = { + .pll_od_fb = PLL_OD_FB_TXLX, + .pll_m_max = PLL_M_MAX_TXLX, + .pll_m_min = PLL_M_MIN_TXLX, + .pll_n_max = PLL_N_MAX_TXLX, + .pll_n_min = PLL_N_MIN_TXLX, + .pll_frac_range = PLL_FRAC_RANGE_TXLX, + .pll_od_sel_max = PLL_OD_SEL_MAX_TXLX, + .pll_ref_fmax = PLL_FREF_MAX_TXLX, + .pll_ref_fmin = PLL_FREF_MIN_TXLX, + .pll_vco_fmax = PLL_VCO_MAX_TXLX, + .pll_vco_fmin = PLL_VCO_MIN_TXLX, + .pll_out_fmax = CLK_DIV_IN_MAX_TXLX, + .pll_out_fmin = PLL_VCO_MIN_TXLX / 16, + .div_in_fmax = CLK_DIV_IN_MAX_TXLX, + .div_out_fmax = CRT_VID_CLK_IN_MAX_TXLX, + .xd_out_fmax = ENCL_CLK_IN_MAX_TXLX, + .ss_level_max = SS_LEVEL_MAX_TXLX, + + .clk_path_valid = 0, + .vclk_sel = 0, + .pll_ctrl_table = pll_ctrl_table_txl, + .pll_ss_table = lcd_pll_ss_table_txlx, + + .clk_generate_parameter = lcd_clk_generate_txl, + .pll_frac_generate = lcd_pll_frac_generate_txl, + .set_spread_spectrum = lcd_set_pll_ss_txlx, + .clk_set = lcd_clk_set_txlx, + .clk_gate_switch = lcd_clk_gate_switch_dft, + .clktree_probe = lcd_clktree_probe_dft, + .clktree_remove = lcd_clktree_remove_dft, + .clk_config_init_print = lcd_clk_config_init_print_dft, + .clk_config_print = lcd_clk_config_print_dft, +}; + +static struct lcd_clk_data_s lcd_clk_data_axg = { + .pll_od_fb = PLL_OD_FB_AXG, + .pll_m_max = PLL_M_MAX_AXG, + .pll_m_min = PLL_M_MIN_AXG, + .pll_n_max = PLL_N_MAX_AXG, + .pll_n_min = PLL_N_MIN_AXG, + .pll_frac_range = PLL_FRAC_RANGE_AXG, + .pll_od_sel_max = PLL_OD_SEL_MAX_AXG, + .pll_ref_fmax = PLL_FREF_MAX_AXG, + .pll_ref_fmin = PLL_FREF_MIN_AXG, + .pll_vco_fmax = PLL_VCO_MAX_AXG, + .pll_vco_fmin = PLL_VCO_MIN_AXG, + .pll_out_fmax = CRT_VID_CLK_IN_MAX_AXG, + .pll_out_fmin = PLL_VCO_MIN_AXG / 4, + .div_in_fmax = 0, + .div_out_fmax = CRT_VID_CLK_IN_MAX_AXG, + .xd_out_fmax = ENCL_CLK_IN_MAX_AXG, + .ss_level_max = SS_LEVEL_MAX_AXG, + + .clk_path_valid = 0, + .vclk_sel = 0, + .pll_ctrl_table = pll_ctrl_table_axg, + .pll_ss_table = NULL, + + .clk_generate_parameter = lcd_clk_generate_axg, + .pll_frac_generate = lcd_pll_frac_generate_axg, + .set_spread_spectrum = NULL, + .clk_set = lcd_clk_set_axg, + .clk_gate_switch = lcd_clk_gate_switch_axg, + .clktree_probe = lcd_clktree_probe_axg, + .clktree_remove = lcd_clktree_remove_axg, + .clk_config_init_print = lcd_clk_config_init_print_axg, + .clk_config_print = lcd_clk_config_print_axg, +}; + +static struct lcd_clk_data_s lcd_clk_data_g12a_path0 = { + .pll_od_fb = PLL_OD_FB_HPLL_G12A, + .pll_m_max = PLL_M_MAX_G12A, + .pll_m_min = PLL_M_MIN_G12A, + .pll_n_max = PLL_N_MAX_G12A, + .pll_n_min = PLL_N_MIN_G12A, + .pll_frac_range = PLL_FRAC_RANGE_HPLL_G12A, + .pll_od_sel_max = PLL_OD_SEL_MAX_HPLL_G12A, + .pll_ref_fmax = PLL_FREF_MAX_G12A, + .pll_ref_fmin = PLL_FREF_MIN_G12A, + .pll_vco_fmax = PLL_VCO_MAX_HPLL_G12A, + .pll_vco_fmin = PLL_VCO_MIN_HPLL_G12A, + .pll_out_fmax = CRT_VID_CLK_IN_MAX_G12A, + .pll_out_fmin = PLL_VCO_MIN_HPLL_G12A / 16, + .div_in_fmax = 0, + .div_out_fmax = CRT_VID_CLK_IN_MAX_G12A, + .xd_out_fmax = ENCL_CLK_IN_MAX_G12A, + .ss_level_max = SS_LEVEL_MAX_HPLL_G12A, + + .clk_path_valid = 1, + .vclk_sel = 0, + .pll_ctrl_table = pll_ctrl_table_g12a_path0, + .pll_ss_table = NULL, + + .clk_generate_parameter = lcd_clk_generate_hpll_g12a, + .pll_frac_generate = lcd_pll_frac_generate_txl, + .set_spread_spectrum = NULL, + .clk_set = lcd_clk_set_g12a_path0, + .clk_gate_switch = lcd_clk_gate_switch_g12a, + .clktree_probe = lcd_clktree_probe_g12a, + .clktree_remove = lcd_clktree_remove_g12a, + .clk_config_init_print = lcd_clk_config_init_print_axg, + .clk_config_print = lcd_clk_config_print_g12a, +}; + +static struct lcd_clk_data_s lcd_clk_data_g12a_path1 = { + .pll_od_fb = PLL_OD_FB_GP0_G12A, + .pll_m_max = PLL_M_MAX_G12A, + .pll_m_min = PLL_M_MIN_G12A, + .pll_n_max = PLL_N_MAX_G12A, + .pll_n_min = PLL_N_MIN_G12A, + .pll_frac_range = PLL_FRAC_RANGE_GP0_G12A, + .pll_od_sel_max = PLL_OD_SEL_MAX_GP0_G12A, + .pll_ref_fmax = PLL_FREF_MAX_G12A, + .pll_ref_fmin = PLL_FREF_MIN_G12A, + .pll_vco_fmax = PLL_VCO_MAX_GP0_G12A, + .pll_vco_fmin = PLL_VCO_MIN_GP0_G12A, + .pll_out_fmax = CRT_VID_CLK_IN_MAX_G12A, + .pll_out_fmin = PLL_VCO_MIN_GP0_G12A / 16, + .div_in_fmax = 0, + .div_out_fmax = CRT_VID_CLK_IN_MAX_G12A, + .xd_out_fmax = ENCL_CLK_IN_MAX_G12A, + .ss_level_max = SS_LEVEL_MAX_GP0_G12A, + + .clk_path_valid = 1, + .vclk_sel = 1, + .pll_ctrl_table = pll_ctrl_table_g12a_path1, + .pll_ss_table = NULL, + + .clk_generate_parameter = lcd_clk_generate_axg, + .pll_frac_generate = lcd_pll_frac_generate_axg, + .set_spread_spectrum = NULL, + .clk_set = lcd_clk_set_g12a_path1, + .clk_gate_switch = lcd_clk_gate_switch_g12a, + .clktree_probe = lcd_clktree_probe_g12a, + .clktree_remove = lcd_clktree_remove_g12a, + .clk_config_init_print = lcd_clk_config_init_print_axg, + .clk_config_print = lcd_clk_config_print_g12a, +}; + +static struct lcd_clk_data_s lcd_clk_data_g12b_path0 = { + .pll_od_fb = PLL_OD_FB_HPLL_G12A, + .pll_m_max = PLL_M_MAX_G12A, + .pll_m_min = PLL_M_MIN_G12A, + .pll_n_max = PLL_N_MAX_G12A, + .pll_n_min = PLL_N_MIN_G12A, + .pll_frac_range = PLL_FRAC_RANGE_HPLL_G12A, + .pll_od_sel_max = PLL_OD_SEL_MAX_HPLL_G12A, + .pll_ref_fmax = PLL_FREF_MAX_G12A, + .pll_ref_fmin = PLL_FREF_MIN_G12A, + .pll_vco_fmax = PLL_VCO_MAX_HPLL_G12A, + .pll_vco_fmin = PLL_VCO_MIN_HPLL_G12A, + .pll_out_fmax = CRT_VID_CLK_IN_MAX_G12A, + .pll_out_fmin = PLL_VCO_MIN_HPLL_G12A / 16, + .div_in_fmax = 0, + .div_out_fmax = CRT_VID_CLK_IN_MAX_G12A, + .xd_out_fmax = ENCL_CLK_IN_MAX_G12A, + .ss_level_max = SS_LEVEL_MAX_HPLL_G12A, + + .clk_path_valid = 1, + .vclk_sel = 0, + .pll_ctrl_table = pll_ctrl_table_g12a_path0, + .pll_ss_table = NULL, + + .clk_generate_parameter = lcd_clk_generate_hpll_g12a, + .pll_frac_generate = lcd_pll_frac_generate_txl, + .set_spread_spectrum = NULL, + .clk_set = lcd_clk_set_g12b_path0, + .clk_gate_switch = lcd_clk_gate_switch_g12a, + .clktree_probe = lcd_clktree_probe_g12a, + .clktree_remove = lcd_clktree_remove_g12a, + .clk_config_init_print = lcd_clk_config_init_print_axg, + .clk_config_print = lcd_clk_config_print_g12a, +}; + +static struct lcd_clk_data_s lcd_clk_data_g12b_path1 = { + .pll_od_fb = PLL_OD_FB_GP0_G12A, + .pll_m_max = PLL_M_MAX_G12A, + .pll_m_min = PLL_M_MIN_G12A, + .pll_n_max = PLL_N_MAX_G12A, + .pll_n_min = PLL_N_MIN_G12A, + .pll_frac_range = PLL_FRAC_RANGE_GP0_G12A, + .pll_od_sel_max = PLL_OD_SEL_MAX_GP0_G12A, + .pll_ref_fmax = PLL_FREF_MAX_G12A, + .pll_ref_fmin = PLL_FREF_MIN_G12A, + .pll_vco_fmax = PLL_VCO_MAX_GP0_G12A, + .pll_vco_fmin = PLL_VCO_MIN_GP0_G12A, + .pll_out_fmax = CRT_VID_CLK_IN_MAX_G12A, + .pll_out_fmin = PLL_VCO_MIN_GP0_G12A / 16, + .div_in_fmax = 0, + .div_out_fmax = CRT_VID_CLK_IN_MAX_G12A, + .xd_out_fmax = ENCL_CLK_IN_MAX_G12A, + .ss_level_max = SS_LEVEL_MAX_GP0_G12A, + + .clk_path_valid = 1, + .vclk_sel = 1, + .pll_ctrl_table = pll_ctrl_table_g12a_path1, + .pll_ss_table = NULL, + + .clk_generate_parameter = lcd_clk_generate_axg, + .pll_frac_generate = lcd_pll_frac_generate_axg, + .set_spread_spectrum = NULL, + .clk_set = lcd_clk_set_g12b_path1, + .clk_gate_switch = lcd_clk_gate_switch_g12a, + .clktree_probe = lcd_clktree_probe_g12a, + .clktree_remove = lcd_clktree_remove_g12a, + .clk_config_init_print = lcd_clk_config_init_print_axg, + .clk_config_print = lcd_clk_config_print_g12a, +}; + +static struct lcd_clk_data_s lcd_clk_data_tl1 = { + .pll_od_fb = PLL_OD_FB_TL1, + .pll_m_max = PLL_M_MAX_TL1, + .pll_m_min = PLL_M_MIN_TL1, + .pll_n_max = PLL_N_MAX_TL1, + .pll_n_min = PLL_N_MIN_TL1, + .pll_frac_range = PLL_FRAC_RANGE_TL1, + .pll_od_sel_max = PLL_OD_SEL_MAX_TL1, + .pll_ref_fmax = PLL_FREF_MAX_TL1, + .pll_ref_fmin = PLL_FREF_MIN_TL1, + .pll_vco_fmax = PLL_VCO_MAX_TL1, + .pll_vco_fmin = PLL_VCO_MIN_TL1, + .pll_out_fmax = CLK_DIV_IN_MAX_TL1, + .pll_out_fmin = PLL_VCO_MIN_TL1 / 16, + .div_in_fmax = CLK_DIV_IN_MAX_TL1, + .div_out_fmax = CRT_VID_CLK_IN_MAX_TL1, + .xd_out_fmax = ENCL_CLK_IN_MAX_TL1, + .ss_level_max = SS_LEVEL_MAX_TL1, + + .clk_path_valid = 0, + .vclk_sel = 0, + .pll_ctrl_table = pll_ctrl_table_tl1, + .pll_ss_table = NULL, + + .clk_generate_parameter = lcd_clk_generate_txl, + .pll_frac_generate = lcd_pll_frac_generate_txl, + .set_spread_spectrum = NULL, + .clk_set = lcd_clk_set_tl1, + .clk_gate_switch = lcd_clk_gate_switch_tl1, + .clktree_probe = lcd_clktree_probe_tl1, + .clktree_remove = lcd_clktree_remove_tl1, + .clk_config_init_print = lcd_clk_config_init_print_dft, + .clk_config_print = lcd_clk_config_print_dft, +}; + +static void lcd_clk_config_chip_init(struct lcd_clk_config_s *cConf) { struct aml_lcd_drv_s *lcd_drv = aml_lcd_get_driver(); - if (lcd_debug_print_flag) - LCDPR("%s\n", __func__); - switch (lcd_drv->data->chip_type) { + case LCD_CHIP_GXL: + case LCD_CHIP_GXM: + cConf->data = &lcd_clk_data_gxl; + break; + case LCD_CHIP_TXL: + cConf->data = &lcd_clk_data_txl; + break; + case LCD_CHIP_TXLX: + cConf->data = &lcd_clk_data_txlx; + break; case LCD_CHIP_AXG: - if (!IS_ERR(lcd_drv->mipi_bandgap_gate)) - devm_clk_put(lcd_drv->dev, lcd_drv->mipi_bandgap_gate); - if (!IS_ERR(lcd_drv->mipi_enable_gate)) - devm_clk_put(lcd_drv->dev, lcd_drv->mipi_enable_gate); - if (!IS_ERR(lcd_drv->dsi_meas)) - devm_clk_put(lcd_drv->dev, lcd_drv->dsi_meas); - if (!IS_ERR(lcd_drv->dsi_phy_gate)) - devm_clk_put(lcd_drv->dev, lcd_drv->dsi_phy_gate); - if (!IS_ERR(lcd_drv->dsi_host_gate)) - devm_clk_put(lcd_drv->dev, lcd_drv->dsi_host_gate); - if (!IS_ERR(lcd_drv->gp0_pll)) - devm_clk_put(lcd_drv->dev, lcd_drv->gp0_pll); + cConf->data = &lcd_clk_data_axg; break; case LCD_CHIP_G12A: + if (lcd_drv->lcd_clk_path) + cConf->data = &lcd_clk_data_g12a_path1; + else + cConf->data = &lcd_clk_data_g12a_path0; + break; case LCD_CHIP_G12B: - if (!IS_ERR(lcd_drv->dsi_host_gate)) - devm_clk_put(lcd_drv->dev, lcd_drv->dsi_host_gate); - if (!IS_ERR(lcd_drv->dsi_phy_gate)) - devm_clk_put(lcd_drv->dev, lcd_drv->dsi_phy_gate); - if (!IS_ERR(lcd_drv->dsi_meas)) - devm_clk_put(lcd_drv->dev, lcd_drv->dsi_meas); - if (!IS_ERR(lcd_drv->encl_top_gate)) - devm_clk_put(lcd_drv->dev, lcd_drv->encl_top_gate); - if (!IS_ERR(lcd_drv->encl_int_gate)) - devm_clk_put(lcd_drv->dev, lcd_drv->encl_int_gate); + if (lcd_drv->lcd_clk_path) + cConf->data = &lcd_clk_data_g12b_path1; + else + cConf->data = &lcd_clk_data_g12b_path0; + break; + case LCD_CHIP_TL1: + cConf->data = &lcd_clk_data_tl1; break; default: - if (!IS_ERR(lcd_drv->encl_top_gate)) - devm_clk_put(lcd_drv->dev, lcd_drv->encl_top_gate); - if (!IS_ERR(lcd_drv->encl_int_gate)) - devm_clk_put(lcd_drv->dev, lcd_drv->encl_int_gate); + LCDPR("%s: invalid chip type\n", __func__); break; } + + if (cConf->data) + cConf->pll_od_fb = cConf->data->pll_od_fb; + if (lcd_debug_print_flag > 0) + lcd_clk_config_init_print(); +} + +int lcd_clk_path_change(int sel) +{ + struct lcd_clk_config_s *cConf = get_lcd_clk_config(); + struct aml_lcd_drv_s *lcd_drv = aml_lcd_get_driver(); + + if (cConf->data == NULL) { + LCDERR("%s: clk config data is null\n", __func__); + return -1; + } + + if (cConf->data->clk_path_valid == 0) { + LCDPR("%s: current chip not support\n", __func__); + return -1; + } + + switch (lcd_drv->data->chip_type) { + case LCD_CHIP_G12A: + case LCD_CHIP_G12B: + if (sel) + cConf->data = &lcd_clk_data_g12a_path1; + else + cConf->data = &lcd_clk_data_g12a_path0; + cConf->pll_od_fb = cConf->data->pll_od_fb; + + if (lcd_debug_print_flag > 0) + lcd_clk_config_init_print(); + break; + default: + LCDERR("%s: current chip not support\n", __func__); + return -1; + } + + return 0; } void lcd_clk_config_probe(void) { spin_lock_init(&lcd_clk_lock); - lcd_clk_config_chip_init(); - lcd_clktree_probe(); + lcd_clk_config_chip_init(&clk_conf); + if (clk_conf.data == NULL) + return; + + if (clk_conf.data->clktree_probe) + clk_conf.data->clktree_probe(); } void lcd_clk_config_remove(void) { - lcd_clktree_remove(); + if (clk_conf.data == NULL) + return; + + if (clk_conf.data->clktree_remove) + clk_conf.data->clktree_remove(); } diff --git a/drivers/amlogic/media/vout/lcd/lcd_clk_config.h b/drivers/amlogic/media/vout/lcd/lcd_clk_config.h index b2ab734b5703..8a52cdaaa407 100644 --- a/drivers/amlogic/media/vout/lcd/lcd_clk_config.h +++ b/drivers/amlogic/media/vout/lcd/lcd_clk_config.h @@ -25,37 +25,29 @@ * clk config * ********************************** */ -struct lcd_clk_config_s { /* unit: kHz */ - /* IN-OUT parameters */ - unsigned int fin; - unsigned int fout; +#define LCD_CLK_CTRL_EN 0 +#define LCD_CLK_CTRL_RST 1 +#define LCD_CLK_CTRL_FRAC 2 +#define LCD_CLK_CTRL_END 0xffff - /* pll parameters */ - unsigned int pll_mode; /* txl */ - unsigned int od_fb; - unsigned int pll_m; - unsigned int pll_n; - unsigned int pll_fvco; - unsigned int pll_od1_sel; - unsigned int pll_od2_sel; - unsigned int pll_od3_sel; - unsigned int pll_level; - unsigned int pll_frac; - unsigned int pll_fout; - unsigned int ss_level; - unsigned int div_sel; - unsigned int xd; +#define LCD_CLK_REG_END 0xffff +#define LCD_CLK_CTRL_CNT_MAX 10 +struct lcd_clk_ctrl_s { + unsigned int flag; + unsigned int reg; + unsigned int bit; + unsigned int len; +}; +struct lcd_clk_data_s { /* clk path node parameters */ - unsigned int ss_level_max; + unsigned int pll_od_fb; unsigned int pll_m_max; unsigned int pll_m_min; unsigned int pll_n_max; unsigned int pll_n_min; unsigned int pll_frac_range; unsigned int pll_od_sel_max; - unsigned int div_sel_max; - unsigned int xd_max; unsigned int pll_ref_fmax; unsigned int pll_ref_fmin; unsigned int pll_vco_fmax; @@ -65,322 +57,85 @@ struct lcd_clk_config_s { /* unit: kHz */ unsigned int div_in_fmax; unsigned int div_out_fmax; unsigned int xd_out_fmax; + unsigned int ss_level_max; + + unsigned char clk_path_valid; + unsigned char vclk_sel; + struct lcd_clk_ctrl_s *pll_ctrl_table; + char **pll_ss_table; + + void (*clk_generate_parameter)(struct lcd_config_s *pconf); + void (*pll_frac_generate)(struct lcd_config_s *pconf); + void (*set_spread_spectrum)(unsigned int ss_level); + void (*clk_set)(struct lcd_config_s *pconf); + void (*clk_gate_switch)(struct aml_lcd_drv_s *lcd_drv, int status); + void (*clktree_probe)(void); + void (*clktree_remove)(void); + void (*clk_config_init_print)(void); + int (*clk_config_print)(char *buf, int offset); +}; + +struct lcd_clk_config_s { /* unit: kHz */ + /* IN-OUT parameters */ + unsigned int fin; + unsigned int fout; + + /* pll parameters */ + unsigned int pll_mode; /* txl */ + unsigned int pll_od_fb; + unsigned int pll_m; + unsigned int pll_n; + unsigned int pll_fvco; + unsigned int pll_od1_sel; + unsigned int pll_od2_sel; + unsigned int pll_od3_sel; + unsigned int pll_pi_div_sel; /* for tcon */ + unsigned int pll_level; + unsigned int pll_frac; + unsigned int pll_fout; + unsigned int ss_level; + unsigned int div_sel; + unsigned int xd; + unsigned int div_sel_max; + unsigned int xd_max; unsigned int err_fmin; + + struct lcd_clk_data_s *data; }; -/* ********************************** - * pll & clk parameter - * ********************************** - */ -/* ******** clk calculation ******** */ -#define PLL_WAIT_LOCK_CNT 200 - /* frequency unit: kHz */ -#define FIN_FREQ (24 * 1000) -/* clk max error */ -#define MAX_ERROR (2 * 1000) +struct lcd_clktree_s { + unsigned char clk_gate_state; -/* ******** register bit ******** */ -/* divider */ -#define CRT_VID_DIV_MAX 255 + struct clk *encl_top_gate; + struct clk *encl_int_gate; -#define DIV_PRE_SEL_MAX 6 -#define EDP_DIV0_SEL_MAX 15 -#define EDP_DIV1_SEL_MAX 8 - -/* g9tv, g9bb, gxbb divider */ -#define CLK_DIV_I2O 0 -#define CLK_DIV_O2I 1 -enum div_sel_e { - CLK_DIV_SEL_1 = 0, - CLK_DIV_SEL_2, /* 1 */ - CLK_DIV_SEL_3, /* 2 */ - CLK_DIV_SEL_3p5, /* 3 */ - CLK_DIV_SEL_3p75, /* 4 */ - CLK_DIV_SEL_4, /* 5 */ - CLK_DIV_SEL_5, /* 6 */ - CLK_DIV_SEL_6, /* 7 */ - CLK_DIV_SEL_6p25, /* 8 */ - CLK_DIV_SEL_7, /* 9 */ - CLK_DIV_SEL_7p5, /* 10 */ - CLK_DIV_SEL_12, /* 11 */ - CLK_DIV_SEL_14, /* 12 */ - CLK_DIV_SEL_15, /* 13 */ - CLK_DIV_SEL_2p5, /* 14 */ - CLK_DIV_SEL_MAX, + struct clk *dsi_host_gate; + struct clk *dsi_phy_gate; + struct clk *dsi_meas; + struct clk *mipi_enable_gate; + struct clk *mipi_bandgap_gate; + struct clk *gp0_pll; + struct clk *tcon_gate; + struct clk *tcon_clk; }; - -/* ********************************** - * GXTVBB - * ********************************** - */ -/* ******** register bit ******** */ -/* PLL_CNTL 0x10c8 */ -#define LCD_PLL_LOCK_GXTVBB 31 -#define LCD_PLL_EN_GXTVBB 30 -#define LCD_PLL_RST_GXTVBB 28 -#define LCD_PLL_N_GXTVBB 9 -#define LCD_PLL_M_GXTVBB 0 - -#define LCD_PLL_OD3_GXTVBB 18 -#define LCD_PLL_OD2_GXTVBB 22 -#define LCD_PLL_OD1_GXTVBB 16 - -/* ******** frequency limit (unit: kHz) ******** */ -#define PLL_FRAC_OD_FB_GXTVBB 0 -#define SS_LEVEL_MAX_GXTVBB 5 -#define PLL_M_MIN_GXTVBB 2 -#define PLL_M_MAX_GXTVBB 511 -#define PLL_N_MIN_GXTVBB 1 -#define PLL_N_MAX_GXTVBB 1 -#define PLL_FRAC_RANGE_GXTVBB (1 << 10) -#define PLL_OD_SEL_MAX_GXTVBB 3 -#define PLL_FREF_MIN_GXTVBB (5 * 1000) -#define PLL_FREF_MAX_GXTVBB (25 * 1000) -#define PLL_VCO_MIN_GXTVBB (3000 * 1000) -#define PLL_VCO_MAX_GXTVBB (6000 * 1000) - -/* video */ -#define CLK_DIV_IN_MAX_GXTVBB (3100 * 1000) -#define CRT_VID_CLK_IN_MAX_GXTVBB (3100 * 1000) -#define ENCL_CLK_IN_MAX_GXTVBB (620 * 1000) - -/* ********************************** - * GXL - * ********************************** - */ -/* ******** register bit ******** */ -/* PLL_CNTL 0x10c8 */ -#define LCD_PLL_LOCK_GXL 31 -#define LCD_PLL_EN_GXL 30 -#define LCD_PLL_RST_GXL 28 -#define LCD_PLL_N_GXL 9 -#define LCD_PLL_M_GXL 0 - -#define LCD_PLL_OD3_GXL 19 -#define LCD_PLL_OD2_GXL 23 -#define LCD_PLL_OD1_GXL 21 - -/* ******** frequency limit (unit: kHz) ******** */ -#define PLL_FRAC_OD_FB_GXL 1 -#define SS_LEVEL_MAX_GXL 5 -#define PLL_M_MIN_GXL 2 -#define PLL_M_MAX_GXL 511 -#define PLL_N_MIN_GXL 1 -#define PLL_N_MAX_GXL 1 -#define PLL_FRAC_RANGE_GXL (1 << 10) -#define PLL_OD_SEL_MAX_GXL 3 -#define PLL_FREF_MIN_GXL (5 * 1000) -#define PLL_FREF_MAX_GXL (25 * 1000) -#define PLL_VCO_MIN_GXL (3000 * 1000) -#define PLL_VCO_MAX_GXL (6000 * 1000) - -/* video */ -#define CLK_DIV_IN_MAX_GXL (3100 * 1000) -#define CRT_VID_CLK_IN_MAX_GXL (3100 * 1000) -#define ENCL_CLK_IN_MAX_GXL (620 * 1000) - -/* ********************************** - * GXM - * ********************************** - */ -/* ******** register bit ******** */ -/* PLL_CNTL 0x10c8 */ -#define LCD_PLL_LOCK_GXM 31 -#define LCD_PLL_EN_GXM 30 -#define LCD_PLL_RST_GXM 28 -#define LCD_PLL_N_GXM 9 -#define LCD_PLL_M_GXM 0 - -#define LCD_PLL_OD3_GXM 19 -#define LCD_PLL_OD2_GXM 23 -#define LCD_PLL_OD1_GXM 21 - -/* ******** frequency limit (unit: kHz) ******** */ -#define PLL_FRAC_OD_FB_GXM 1 -#define SS_LEVEL_MAX_GXM 5 -#define PLL_M_MIN_GXM 2 -#define PLL_M_MAX_GXM 511 -#define PLL_N_MIN_GXM 1 -#define PLL_N_MAX_GXM 1 -#define PLL_FRAC_RANGE_GXM (1 << 10) -#define PLL_OD_SEL_MAX_GXM 3 -#define PLL_FREF_MIN_GXM (5 * 1000) -#define PLL_FREF_MAX_GXM (25 * 1000) -#define PLL_VCO_MIN_GXM (3000 * 1000) -#define PLL_VCO_MAX_GXM (6000 * 1000) - -/* video */ -#define CLK_DIV_IN_MAX_GXM (3100 * 1000) -#define CRT_VID_CLK_IN_MAX_GXM (3100 * 1000) -#define ENCL_CLK_IN_MAX_GXM (620 * 1000) - -/* ********************************** - * TXL - * ********************************** - */ -/* ******** register bit ******** */ -/* PLL_CNTL 0x10c8 */ -#define LCD_PLL_LOCK_TXL 31 -#define LCD_PLL_EN_TXL 30 -#define LCD_PLL_RST_TXL 28 -#define LCD_PLL_N_TXL 9 -#define LCD_PLL_M_TXL 0 - -#define LCD_PLL_OD3_TXL 19 -#define LCD_PLL_OD2_TXL 23 -#define LCD_PLL_OD1_TXL 21 - -/* ******** frequency limit (unit: kHz) ******** */ -#define PLL_FRAC_OD_FB_TXL 1 /* update od_fb to 1 for ss width */ -#define SS_LEVEL_MAX_TXL 5 -#define PLL_M_MIN_TXL 2 -#define PLL_M_MAX_TXL 511 -#define PLL_N_MIN_TXL 1 -#define PLL_N_MAX_TXL 1 -#define PLL_FRAC_RANGE_TXL (1 << 10) -#define PLL_OD_SEL_MAX_TXL 3 -#define PLL_FREF_MIN_TXL (5 * 1000) -#define PLL_FREF_MAX_TXL (25 * 1000) -#define PLL_VCO_MIN_TXL (2950 * 1000) -#define PLL_VCO_MAX_TXL (5900 * 1000) - -/* video */ -#define CLK_DIV_IN_MAX_TXL (3100 * 1000) -#define CRT_VID_CLK_IN_MAX_TXL (3100 * 1000) -#define ENCL_CLK_IN_MAX_TXL (620 * 1000) - -/* ********************************** - * TXLX - * ********************************** - */ -/* ******** register bit ******** */ -/* PLL_CNTL 0x10c8 */ -#define LCD_PLL_LOCK_TXLX 31 -#define LCD_PLL_EN_TXLX 30 -#define LCD_PLL_RST_TXLX 28 -#define LCD_PLL_N_TXLX 9 -#define LCD_PLL_M_TXLX 0 - -#define LCD_PLL_OD3_TXLX 19 -#define LCD_PLL_OD2_TXLX 23 -#define LCD_PLL_OD1_TXLX 21 - -/* ******** frequency limit (unit: kHz) ******** */ -#define PLL_FRAC_OD_FB_TXLX 0 -#define SS_LEVEL_MAX_TXLX 6 -#define PLL_M_MIN_TXLX 2 -#define PLL_M_MAX_TXLX 511 -#define PLL_N_MIN_TXLX 1 -#define PLL_N_MAX_TXLX 1 -#define PLL_FRAC_RANGE_TXLX (1 << 10) -#define PLL_OD_SEL_MAX_TXLX 3 -#define PLL_FREF_MIN_TXLX (5 * 1000) -#define PLL_FREF_MAX_TXLX (25 * 1000) -#define PLL_VCO_MIN_TXLX (3000 * 1000) -#define PLL_VCO_MAX_TXLX (6000 * 1000) - -/* video */ -#define CLK_DIV_IN_MAX_TXLX (3100 * 1000) -#define CRT_VID_CLK_IN_MAX_TXLX (3100 * 1000) -#define ENCL_CLK_IN_MAX_TXLX (620 * 1000) - -/* ********************************** - * AXG - * ********************************** - */ -/* ******** register bit ******** */ -/* PLL_CNTL */ -#define LCD_PLL_LOCK_AXG 31 -#define LCD_PLL_EN_AXG 30 -#define LCD_PLL_RST_AXG 29 -#define LCD_PLL_OD_AXG 16 -#define LCD_PLL_N_AXG 9 -#define LCD_PLL_M_AXG 0 - -/* ******** frequency limit (unit: kHz) ******** */ -#define PLL_FRAC_OD_FB_AXG 0 -#define SS_LEVEL_MAX_AXG 5 -#define PLL_M_MIN_AXG 2 -#define PLL_M_MAX_AXG 511 -#define PLL_N_MIN_AXG 1 -#define PLL_N_MAX_AXG 1 -#define PLL_FRAC_RANGE_AXG (1 << 10) -#define PLL_OD_SEL_MAX_AXG 3 -#define PLL_FREF_MIN_AXG (5 * 1000) -#define PLL_FREF_MAX_AXG (25 * 1000) -#define PLL_VCO_MIN_AXG (960 * 1000) -#define PLL_VCO_MAX_AXG (1920 * 1000) - -/* video */ -#define CRT_VID_CLK_IN_MAX_AXG (1920 * 1000) -#define ENCL_CLK_IN_MAX_AXG (200 * 1000) - -/* G12A */ -/* ******** register bit ******** */ -/* PLL_CNTL bit: GP0 */ -#define LCD_PLL_LOCK_GP0_G12A 31 -#define LCD_PLL_EN_GP0_G12A 28 -#define LCD_PLL_RST_GP0_G12A 29 -#define LCD_PLL_OD_GP0_G12A 16 -#define LCD_PLL_N_GP0_G12A 10 -#define LCD_PLL_M_GP0_G12A 0 - -/* ******** frequency limit (unit: kHz) ******** */ -#define PLL_FRAC_OD_FB_GP0_G12A 0 -#define SS_LEVEL_MAX_GP0_G12A 1 -#define PLL_FRAC_RANGE_GP0_G12A (1 << 17) -#define PLL_OD_SEL_MAX_GP0_G12A 5 -#define PLL_VCO_MIN_GP0_G12A (3000 * 1000) -#define PLL_VCO_MAX_GP0_G12A (6000 * 1000) - -/* PLL_CNTL bit: hpll */ -#define LCD_PLL_LOCK_HPLL_G12A 31 -#define LCD_PLL_EN_HPLL_G12A 28 -#define LCD_PLL_RST_HPLL_G12A 29 -#define LCD_PLL_N_HPLL_G12A 10 -#define LCD_PLL_M_HPLL_G12A 0 - -#define LCD_PLL_OD3_HPLL_G12A 20 -#define LCD_PLL_OD2_HPLL_G12A 18 -#define LCD_PLL_OD1_HPLL_G12A 16 - -/* ******** frequency limit (unit: kHz) ******** */ -#define PLL_FRAC_OD_FB_HPLL_G12A 0 -#define SS_LEVEL_MAX_HPLL_G12A 1 -#define PLL_FRAC_RANGE_HPLL_G12A (1 << 17) -#define PLL_OD_SEL_MAX_HPLL_G12A 3 -#define PLL_VCO_MIN_HPLL_G12A (3000 * 1000) -#define PLL_VCO_MAX_HPLL_G12A (6000 * 1000) - -/* video */ -#define PLL_M_MIN_G12A 2 -#define PLL_M_MAX_G12A 511 -#define PLL_N_MIN_G12A 1 -#define PLL_N_MAX_G12A 1 -#define PLL_FREF_MIN_G12A (5 * 1000) -#define PLL_FREF_MAX_G12A (25 * 1000) -#define CRT_VID_CLK_IN_MAX_G12A (6000 * 1000) -#define ENCL_CLK_IN_MAX_G12A (200 * 1000) - - /* ******** api ******** */ extern int meson_clk_measure(unsigned int clk_mux); extern int lcd_debug_info_len(int num); extern struct lcd_clk_config_s *get_lcd_clk_config(void); -extern int lcd_clk_path_change(int sel); extern int lcd_clk_config_print(char *buf, int offset); extern int lcd_encl_clk_msr(void); extern void lcd_pll_reset(void); extern char *lcd_get_spread_spectrum(void); -extern void lcd_set_spread_spectrum(void); +extern void lcd_set_spread_spectrum(unsigned int ss_level); extern void lcd_clk_update(struct lcd_config_s *pconf); extern void lcd_clk_set(struct lcd_config_s *pconf); extern void lcd_clk_disable(void); extern void lcd_clk_generate_parameter(struct lcd_config_s *pconf); extern void lcd_clk_gate_switch(int status); +extern int lcd_clk_path_change(int sel); extern void lcd_clk_config_probe(void); extern void lcd_clk_config_remove(void); diff --git a/drivers/amlogic/media/vout/lcd/lcd_clk_ctrl.h b/drivers/amlogic/media/vout/lcd/lcd_clk_ctrl.h new file mode 100644 index 000000000000..928ba65cc68d --- /dev/null +++ b/drivers/amlogic/media/vout/lcd/lcd_clk_ctrl.h @@ -0,0 +1,417 @@ +/* + * drivers/amlogic/media/vout/lcd/lcd_clk_ctrl.h + * + * Copyright (C) 2017 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +#ifndef _LCD_CLK_CONFIG_CTRL_H +#define _LCD_CLK_CONFIG_CTRL_H + +#include "lcd_reg.h" +#include "lcd_clk_config.h" + +/* ********************************** + * GXL + * ********************************** + */ +/* ******** register bit ******** */ +/* PLL_CNTL 0x10c8 */ +#define LCD_PLL_LOCK_GXL 31 +#define LCD_PLL_EN_GXL 30 +#define LCD_PLL_RST_GXL 28 +#define LCD_PLL_N_GXL 9 +#define LCD_PLL_M_GXL 0 + +#define LCD_PLL_OD3_GXL 19 +#define LCD_PLL_OD2_GXL 23 +#define LCD_PLL_OD1_GXL 21 + +/* ******** frequency limit (unit: kHz) ******** */ +#define PLL_OD_FB_GXL 1 +#define PLL_M_MIN_GXL 2 +#define PLL_M_MAX_GXL 511 +#define PLL_N_MIN_GXL 1 +#define PLL_N_MAX_GXL 1 +#define PLL_FRAC_RANGE_GXL (1 << 10) +#define PLL_OD_SEL_MAX_GXL 3 +#define PLL_FREF_MIN_GXL (5 * 1000) +#define PLL_FREF_MAX_GXL (25 * 1000) +#define PLL_VCO_MIN_GXL (3000 * 1000) +#define PLL_VCO_MAX_GXL (6000 * 1000) + +/* video */ +#define CLK_DIV_IN_MAX_GXL (3100 * 1000) +#define CRT_VID_CLK_IN_MAX_GXL (3100 * 1000) +#define ENCL_CLK_IN_MAX_GXL (620 * 1000) + +/* ********************************** + * TXL + * ********************************** + */ +/* ******** register bit ******** */ +/* PLL_CNTL 0x10c8 */ +#define LCD_PLL_LOCK_TXL 31 +#define LCD_PLL_EN_TXL 30 +#define LCD_PLL_RST_TXL 28 +#define LCD_PLL_N_TXL 9 +#define LCD_PLL_M_TXL 0 + +#define LCD_PLL_OD3_TXL 19 +#define LCD_PLL_OD2_TXL 23 +#define LCD_PLL_OD1_TXL 21 + +/* ******** frequency limit (unit: kHz) ******** */ +#define PLL_OD_FB_TXL 1 /* update od_fb to 1 for ss width */ +#define PLL_M_MIN_TXL 2 +#define PLL_M_MAX_TXL 511 +#define PLL_N_MIN_TXL 1 +#define PLL_N_MAX_TXL 1 +#define PLL_FRAC_RANGE_TXL (1 << 10) +#define PLL_OD_SEL_MAX_TXL 3 +#define PLL_FREF_MIN_TXL (5 * 1000) +#define PLL_FREF_MAX_TXL (25 * 1000) +#define PLL_VCO_MIN_TXL (2950 * 1000) +#define PLL_VCO_MAX_TXL (5900 * 1000) + +/* video */ +#define CLK_DIV_IN_MAX_TXL (3100 * 1000) +#define CRT_VID_CLK_IN_MAX_TXL (3100 * 1000) +#define ENCL_CLK_IN_MAX_TXL (620 * 1000) + +/* ********************************** + * TXLX + * ********************************** + */ +/* ******** register bit ******** */ +/* PLL_CNTL 0x10c8 */ +#define LCD_PLL_LOCK_TXLX 31 +#define LCD_PLL_EN_TXLX 30 +#define LCD_PLL_RST_TXLX 28 +#define LCD_PLL_N_TXLX 9 +#define LCD_PLL_M_TXLX 0 + +#define LCD_PLL_OD3_TXLX 19 +#define LCD_PLL_OD2_TXLX 23 +#define LCD_PLL_OD1_TXLX 21 + +/* ******** frequency limit (unit: kHz) ******** */ +#define PLL_OD_FB_TXLX 0 +#define PLL_M_MIN_TXLX 2 +#define PLL_M_MAX_TXLX 511 +#define PLL_N_MIN_TXLX 1 +#define PLL_N_MAX_TXLX 1 +#define PLL_FRAC_RANGE_TXLX (1 << 10) +#define PLL_OD_SEL_MAX_TXLX 3 +#define PLL_FREF_MIN_TXLX (5 * 1000) +#define PLL_FREF_MAX_TXLX (25 * 1000) +#define PLL_VCO_MIN_TXLX (3000 * 1000) +#define PLL_VCO_MAX_TXLX (6000 * 1000) + +/* video */ +#define CLK_DIV_IN_MAX_TXLX (3100 * 1000) +#define CRT_VID_CLK_IN_MAX_TXLX (3100 * 1000) +#define ENCL_CLK_IN_MAX_TXLX (620 * 1000) + +/* ********************************** + * AXG + * ********************************** + */ +/* ******** register bit ******** */ +/* PLL_CNTL */ +#define LCD_PLL_LOCK_AXG 31 +#define LCD_PLL_EN_AXG 30 +#define LCD_PLL_RST_AXG 29 +#define LCD_PLL_OD_AXG 16 +#define LCD_PLL_N_AXG 9 +#define LCD_PLL_M_AXG 0 + +/* ******** frequency limit (unit: kHz) ******** */ +#define PLL_OD_FB_AXG 0 +#define PLL_M_MIN_AXG 2 +#define PLL_M_MAX_AXG 511 +#define PLL_N_MIN_AXG 1 +#define PLL_N_MAX_AXG 1 +#define PLL_FRAC_RANGE_AXG (1 << 10) +#define PLL_OD_SEL_MAX_AXG 3 +#define PLL_FREF_MIN_AXG (5 * 1000) +#define PLL_FREF_MAX_AXG (25 * 1000) +#define PLL_VCO_MIN_AXG (960 * 1000) +#define PLL_VCO_MAX_AXG (1920 * 1000) + +/* video */ +#define CRT_VID_CLK_IN_MAX_AXG (1920 * 1000) +#define ENCL_CLK_IN_MAX_AXG (200 * 1000) + +/* G12A */ +/* ******** register bit ******** */ +/* PLL_CNTL bit: GP0 */ +#define LCD_PLL_LOCK_GP0_G12A 31 +#define LCD_PLL_EN_GP0_G12A 28 +#define LCD_PLL_RST_GP0_G12A 29 +#define LCD_PLL_OD_GP0_G12A 16 +#define LCD_PLL_N_GP0_G12A 10 +#define LCD_PLL_M_GP0_G12A 0 + +/* ******** frequency limit (unit: kHz) ******** */ +#define PLL_OD_FB_GP0_G12A 0 +#define PLL_FRAC_RANGE_GP0_G12A (1 << 17) +#define PLL_OD_SEL_MAX_GP0_G12A 5 +#define PLL_VCO_MIN_GP0_G12A (3000 * 1000) +#define PLL_VCO_MAX_GP0_G12A (6000 * 1000) + +/* PLL_CNTL bit: hpll */ +#define LCD_PLL_LOCK_HPLL_G12A 31 +#define LCD_PLL_EN_HPLL_G12A 28 +#define LCD_PLL_RST_HPLL_G12A 29 +#define LCD_PLL_N_HPLL_G12A 10 +#define LCD_PLL_M_HPLL_G12A 0 + +#define LCD_PLL_OD3_HPLL_G12A 20 +#define LCD_PLL_OD2_HPLL_G12A 18 +#define LCD_PLL_OD1_HPLL_G12A 16 + +/* ******** frequency limit (unit: kHz) ******** */ +#define PLL_OD_FB_HPLL_G12A 0 +#define PLL_FRAC_RANGE_HPLL_G12A (1 << 17) +#define PLL_OD_SEL_MAX_HPLL_G12A 3 +#define PLL_VCO_MIN_HPLL_G12A (3000 * 1000) +#define PLL_VCO_MAX_HPLL_G12A (6000 * 1000) + +/* gp0 & hpll common */ +#define PLL_M_MIN_G12A 2 +#define PLL_M_MAX_G12A 511 +#define PLL_N_MIN_G12A 1 +#define PLL_N_MAX_G12A 1 +#define PLL_FREF_MIN_G12A (5 * 1000) +#define PLL_FREF_MAX_G12A (25 * 1000) + +/* video */ +#define CRT_VID_CLK_IN_MAX_G12A (6000 * 1000) +#define ENCL_CLK_IN_MAX_G12A (200 * 1000) + +/* ********************************** + * TL1 + * ********************************** + */ +/* ******** register bit ******** */ +/* PLL_CNTL 0x20 */ +#define LCD_PLL_LOCK_TL1 31 +#define LCD_PLL_EN_TL1 28 +#define LCD_PLL_RST_TL1 29 +#define LCD_PLL_N_TL1 10 +#define LCD_PLL_M_TL1 0 + +#define LCD_PLL_OD3_TL1 19 +#define LCD_PLL_OD2_TL1 23 +#define LCD_PLL_OD1_TL1 21 + +/* ******** frequency limit (unit: kHz) ******** */ +#define PLL_OD_FB_TL1 0 +#define PLL_M_MIN_TL1 2 +#define PLL_M_MAX_TL1 511 +#define PLL_N_MIN_TL1 1 +#define PLL_N_MAX_TL1 1 +#define PLL_FRAC_RANGE_TL1 (1 << 17) +#define PLL_OD_SEL_MAX_TL1 3 +#define PLL_FREF_MIN_TL1 (5 * 1000) +#define PLL_FREF_MAX_TL1 (25 * 1000) +#define PLL_VCO_MIN_TL1 (3000 * 1000) +#define PLL_VCO_MAX_TL1 (6000 * 1000) + +/* video */ +#define CLK_DIV_IN_MAX_TL1 (3100 * 1000) +#define CRT_VID_CLK_IN_MAX_TL1 (3100 * 1000) +#define ENCL_CLK_IN_MAX_TL1 (400 * 1000) + + +/* ********************************** + * Spread Spectrum + * ********************************** + */ +#define SS_LEVEL_MAX_GXL 0 +#define SS_LEVEL_MAX_AXG 0 +#define SS_LEVEL_MAX_GP0_G12A 0 +#define SS_LEVEL_MAX_HPLL_G12A 0 + +#define SS_LEVEL_MAX_TXL 5 +static char *lcd_pll_ss_table_txl[] = { + "0, disable", + "1, +/-0.3%", + "2, +/-0.4%", + "3, +/-0.9%", + "4, +/-1.2%", +}; + +#define SS_LEVEL_MAX_TXLX 6 +static char *lcd_pll_ss_table_txlx[] = { + "0, disable", + "1, +/-0.3%", + "2, +/-0.5%", + "3, +/-1.0%", + "4, +/-1.6%", + "5, +/-3.0%", +}; + +#define SS_LEVEL_MAX_TL1 0 + + +static unsigned int pll_ss_reg_txl[][2] = { + /* cntl3 cntl4 */ + { 0, 0}, /* disable */ + {((1 << 14) | (0xc << 10)), 0}, /* 1: +/-0.3% */ + {((1 << 14) | (0x8 << 10)), (0x1 << 2)}, /* 2: +/-0.4% */ + {((1 << 14) | (0xc << 10)), (0x2 << 2)}, /* 3: +/-0.9% */ + {((1 << 14) | (0xc << 10)), (0x3 << 2)}, /* 4: +/-1.2% */ +}; + + +static unsigned int pll_ss_reg_txlx[][3] = { + /* cntl3 cntl4 cntl5 */ + { 0, 0, 0}, /* disable */ + {((1 << 14) | (0x6 << 10)), (0x1 << 2), 0}, /* 1: +/-0.3% */ + {((1 << 14) | (0xa << 10)), (0x1 << 2), 0}, /* 2: +/-0.5% */ + {((1 << 14) | (0xa << 10)), (0x3 << 2), 0}, /* 3: +/-1.0% */ + {((1 << 14) | (0x8 << 10)), (0x3 << 2), (0x1 << 30)}, /* 4: +/-1.6% */ + {((1 << 14) | (0xa << 10)), (0x3 << 2), (0x2 << 30)}, /* 5: +/-3.0% */ +}; + +/* ********************************** + * pll control + * ********************************** + */ +struct lcd_clk_ctrl_s pll_ctrl_table_txl[] = { + /* flag reg bit len*/ + {LCD_CLK_CTRL_EN, HHI_HDMI_PLL_CNTL, LCD_PLL_EN_TXL, 1}, + {LCD_CLK_CTRL_RST, HHI_HDMI_PLL_CNTL, LCD_PLL_RST_TXL, 1}, + {LCD_CLK_CTRL_FRAC, HHI_HDMI_PLL_CNTL2, 0, 12}, + {LCD_CLK_CTRL_END, LCD_CLK_REG_END, 0, 0}, +}; + +struct lcd_clk_ctrl_s pll_ctrl_table_axg[] = { + /* flag reg bit len*/ + {LCD_CLK_CTRL_EN, HHI_GP0_PLL_CNTL_AXG, LCD_PLL_EN_AXG, 1}, + {LCD_CLK_CTRL_RST, HHI_GP0_PLL_CNTL_AXG, LCD_PLL_RST_AXG, 1}, + {LCD_CLK_CTRL_FRAC, HHI_GP0_PLL_CNTL1_AXG, 0, 12}, + {LCD_CLK_CTRL_END, LCD_CLK_REG_END, 0, 0}, +}; + +struct lcd_clk_ctrl_s pll_ctrl_table_g12a_path0[] = { + /* flag reg bit len*/ + {LCD_CLK_CTRL_EN, HHI_HDMI_PLL_CNTL, LCD_PLL_EN_HPLL_G12A, 1}, + {LCD_CLK_CTRL_RST, HHI_HDMI_PLL_CNTL, LCD_PLL_RST_HPLL_G12A, 1}, + {LCD_CLK_CTRL_FRAC, HHI_HDMI_PLL_CNTL2, 0, 19}, + {LCD_CLK_CTRL_END, LCD_CLK_REG_END, 0, 0}, +}; + +struct lcd_clk_ctrl_s pll_ctrl_table_g12a_path1[] = { + /* flag reg bit len*/ + {LCD_CLK_CTRL_EN, HHI_GP0_PLL_CNTL0_G12A, LCD_PLL_EN_GP0_G12A, 1}, + {LCD_CLK_CTRL_RST, HHI_GP0_PLL_CNTL0_G12A, LCD_PLL_RST_GP0_G12A, 1}, + {LCD_CLK_CTRL_FRAC, HHI_GP0_PLL_CNTL1_G12A, 0, 19}, + {LCD_CLK_CTRL_END, LCD_CLK_REG_END, 0, 0}, +}; + +struct lcd_clk_ctrl_s pll_ctrl_table_tl1[] = { + /* flag reg bit len*/ + {LCD_CLK_CTRL_EN, HHI_TCON_PLL_CNTL0, LCD_PLL_EN_TL1, 1}, + {LCD_CLK_CTRL_RST, HHI_TCON_PLL_CNTL0, LCD_PLL_RST_TL1, 1}, + {LCD_CLK_CTRL_FRAC, HHI_TCON_PLL_CNTL1, 0, 17}, + {LCD_CLK_CTRL_END, LCD_CLK_REG_END, 0, 0}, +}; + +/* ********************************** + * pll & clk parameter + * ********************************** + */ +/* ******** clk calculation ******** */ +#define PLL_WAIT_LOCK_CNT 200 + /* frequency unit: kHz */ +#define FIN_FREQ (24 * 1000) +/* clk max error */ +#define MAX_ERROR (2 * 1000) + +/* ******** register bit ******** */ +/* divider */ +#define CRT_VID_DIV_MAX 255 + +static const unsigned int od_fb_table[2] = {1, 2}; + +static const unsigned int od_table[6] = { + 1, 2, 4, 8, 16, 32 +}; + +static const unsigned int pi_div_table[2] = {2, 4}; + +static char *lcd_clk_div_sel_table[] = { + "1", + "2", + "3", + "3.5", + "3.75", + "4", + "5", + "6", + "6.25", + "7", + "7.5", + "12", + "14", + "15", + "2.5", + "invalid", +}; + +/* g9tv, g9bb, gxbb divider */ +#define CLK_DIV_I2O 0 +#define CLK_DIV_O2I 1 +enum div_sel_e { + CLK_DIV_SEL_1 = 0, + CLK_DIV_SEL_2, /* 1 */ + CLK_DIV_SEL_3, /* 2 */ + CLK_DIV_SEL_3p5, /* 3 */ + CLK_DIV_SEL_3p75, /* 4 */ + CLK_DIV_SEL_4, /* 5 */ + CLK_DIV_SEL_5, /* 6 */ + CLK_DIV_SEL_6, /* 7 */ + CLK_DIV_SEL_6p25, /* 8 */ + CLK_DIV_SEL_7, /* 9 */ + CLK_DIV_SEL_7p5, /* 10 */ + CLK_DIV_SEL_12, /* 11 */ + CLK_DIV_SEL_14, /* 12 */ + CLK_DIV_SEL_15, /* 13 */ + CLK_DIV_SEL_2p5, /* 14 */ + CLK_DIV_SEL_MAX, +}; + +static unsigned int lcd_clk_div_table[][3] = { + /* divider, shift_val, shift_sel */ + {CLK_DIV_SEL_1, 0xffff, 0,}, + {CLK_DIV_SEL_2, 0x0aaa, 0,}, + {CLK_DIV_SEL_3, 0x0db6, 0,}, + {CLK_DIV_SEL_3p5, 0x36cc, 1,}, + {CLK_DIV_SEL_3p75, 0x6666, 2,}, + {CLK_DIV_SEL_4, 0x0ccc, 0,}, + {CLK_DIV_SEL_5, 0x739c, 2,}, + {CLK_DIV_SEL_6, 0x0e38, 0,}, + {CLK_DIV_SEL_6p25, 0x0000, 3,}, + {CLK_DIV_SEL_7, 0x3c78, 1,}, + {CLK_DIV_SEL_7p5, 0x78f0, 2,}, + {CLK_DIV_SEL_12, 0x0fc0, 0,}, + {CLK_DIV_SEL_14, 0x3f80, 1,}, + {CLK_DIV_SEL_15, 0x7f80, 2,}, + {CLK_DIV_SEL_2p5, 0x5294, 2,}, + {CLK_DIV_SEL_MAX, 0xffff, 0,}, +}; + +#endif diff --git a/drivers/amlogic/media/vout/lcd/lcd_common.c b/drivers/amlogic/media/vout/lcd/lcd_common.c index b8817ea79412..cbbcac6e6236 100644 --- a/drivers/amlogic/media/vout/lcd/lcd_common.c +++ b/drivers/amlogic/media/vout/lcd/lcd_common.c @@ -45,11 +45,13 @@ struct lcd_type_match_s { }; static struct lcd_type_match_s lcd_type_match_table[] = { - {"ttl", LCD_TTL}, - {"lvds", LCD_LVDS}, - {"vbyone", LCD_VBYONE}, - {"mipi", LCD_MIPI}, - {"invalid", LCD_TYPE_MAX}, + {"ttl", LCD_TTL}, + {"lvds", LCD_LVDS}, + {"vbyone", LCD_VBYONE}, + {"mipi", LCD_MIPI}, + {"minilvds", LCD_MLVDS}, + {"p2p", LCD_P2P}, + {"invalid", LCD_TYPE_MAX}, }; int lcd_type_str_to_type(const char *str) @@ -361,6 +363,37 @@ void lcd_vbyone_pinmux_set(int status) pconf->pinmux_flag = index; } +void lcd_tcon_pinmux_set(int status) +{ + struct aml_lcd_drv_s *lcd_drv = aml_lcd_get_driver(); + struct lcd_config_s *pconf; + + if (lcd_debug_print_flag) + LCDPR("%s: %d\n", __func__, status); + + pconf = lcd_drv->lcd_config; + if (status) { + if (pconf->pinmux_flag == 0) { + pconf->pinmux_flag = 1; + /* request pinmux */ + pconf->pin = devm_pinctrl_get_select(lcd_drv->dev, + "tcon"); + if (IS_ERR(pconf->pin)) + LCDERR("set tcon pinmux error\n"); + } else { + LCDPR("tcon pinmux is already selected\n"); + } + } else { + if (pconf->pinmux_flag) { + pconf->pinmux_flag = 0; + /* release pinmux */ + devm_pinctrl_put(pconf->pin); + } else { + LCDPR("tcon pinmux is already released\n"); + } + } +} + unsigned int lcd_lvds_channel_on_value(struct lcd_config_s *pconf) { unsigned int channel_on = 0; diff --git a/drivers/amlogic/media/vout/lcd/lcd_common.h b/drivers/amlogic/media/vout/lcd/lcd_common.h index 968b949d3199..ce93c41ea5e3 100644 --- a/drivers/amlogic/media/vout/lcd/lcd_common.h +++ b/drivers/amlogic/media/vout/lcd/lcd_common.h @@ -31,7 +31,9 @@ /* 20180626: txl suuport */ /* 20180718: mute: wait vsync for display shadow */ /* 20180827: add pinmux off support */ -#define LCD_DRV_VERSION "20180827" +/* 20180928: tl1 support, optimize clk config */ +/* 20181012: tl1 support tcon */ +#define LCD_DRV_VERSION "20181012" #define VPP_OUT_SATURATE (1 << 0) @@ -41,6 +43,10 @@ #define LVDS_PHY_CNTL1_G9TV 0x606cca80 #define LVDS_PHY_CNTL2_G9TV 0x0000006c #define LVDS_PHY_CNTL3_G9TV 0x00000800 + +#define LVDS_PHY_CNTL1_TL1 0x6c60ca80 +#define LVDS_PHY_CNTL2_TL1 0x00000070 +#define LVDS_PHY_CNTL3_TL1 0x03ff0c00 /* -------------------------- */ /* -------------------------- */ @@ -52,6 +58,13 @@ #define VX1_PHY_CNTL3_G9TV 0x00ff0800 /* -------------------------- */ +/* -------------------------- */ +/* minilvds phy parameters define */ +/* -------------------------- */ +#define MLVDS_PHY_CNTL1_TL1 0x6c60ca80 +#define MLVDS_PHY_CNTL2_TL1 0x00000070 +#define MLVDS_PHY_CNTL3_TL1 0x03ff0c00 + /* ******** mipi_dsi_phy ******** */ /* bit[15:11] */ @@ -86,6 +99,7 @@ extern void lcd_cpu_gpio_set(unsigned int index, int value); extern unsigned int lcd_cpu_gpio_get(unsigned int index); extern void lcd_ttl_pinmux_set(int status); extern void lcd_vbyone_pinmux_set(int status); +extern void lcd_tcon_pinmux_set(int status); extern unsigned int lcd_lvds_channel_on_value(struct lcd_config_s *pconf); extern int lcd_power_load_from_dts(struct lcd_config_s *pconf, struct device_node *child); @@ -102,11 +116,27 @@ extern int lcd_vmode_change(struct lcd_config_s *pconf); extern void lcd_venc_change(struct lcd_config_s *pconf); extern void lcd_if_enable_retry(struct lcd_config_s *pconf); +/* lcd tcon */ +extern void lcd_tcon_reg_table_print(void); +extern void lcd_tcon_reg_readback_print(void); +extern int lcd_tcon_info_print(char *buf, int offset); +extern int lcd_tcon_od_set(int flag); +extern int lcd_tcon_od_get(void); +extern int lcd_tcon_reg_table_size_get(void); +extern unsigned char *lcd_tcon_reg_table_get(void); + +extern int lcd_tcon_core_reg_get(unsigned char *buf, unsigned int size); +extern void lcd_tcon_core_reg_update(void); +extern int lcd_tcon_enable(struct lcd_config_s *pconf); +extern void lcd_tcon_disable(void); +extern int lcd_tcon_probe(struct aml_lcd_drv_s *lcd_drv); + /* lcd debug */ +extern int lcd_debug_info_len(int num); extern void lcd_debug_test(unsigned int num); extern void lcd_mute_setting(unsigned char flag); -extern int lcd_class_creat(void); -extern int lcd_class_remove(void); +extern int lcd_debug_probe(void); +extern int lcd_debug_remove(void); /* lcd driver */ #ifdef CONFIG_AMLOGIC_LCD_TV @@ -119,7 +149,7 @@ extern int lcd_tv_probe(struct device *dev); extern int lcd_tv_remove(struct device *dev); #endif #ifdef CONFIG_AMLOGIC_LCD_TABLET -int lcd_mipi_test_read(struct dsi_read_s *dread); +extern int lcd_mipi_test_read(struct dsi_read_s *dread); extern void lcd_tablet_vout_server_init(void); extern void lcd_tablet_vout_server_remove(void); extern void lcd_tablet_clk_config_change(struct lcd_config_s *pconf); diff --git a/drivers/amlogic/media/vout/lcd/lcd_debug.c b/drivers/amlogic/media/vout/lcd/lcd_debug.c index 4e154aac5648..83bf97be80a2 100644 --- a/drivers/amlogic/media/vout/lcd/lcd_debug.c +++ b/drivers/amlogic/media/vout/lcd/lcd_debug.c @@ -24,6 +24,8 @@ #include #include #include +#include +#include #include #include #include @@ -33,6 +35,10 @@ #include #include "lcd_tablet/mipi_dsi_util.h" #endif +#include "lcd_debug.h" + +static struct lcd_debug_info_reg_s *lcd_debug_info_reg; +static struct lcd_debug_info_if_s *lcd_debug_info_if; #define PR_BUF_MAX 2048 @@ -246,12 +252,254 @@ static int lcd_power_step_print(struct lcd_config_s *pconf, int status, return len; } +static int lcd_power_info_print(char *buf, int offset) +{ + struct aml_lcd_drv_s *lcd_drv = aml_lcd_get_driver(); + int len = 0; + + len += lcd_power_step_print(lcd_drv->lcd_config, 1, + (buf+len), (len + offset)); + len += lcd_power_step_print(lcd_drv->lcd_config, 0, + (buf+len), (len + offset)); + len += lcd_cpu_gpio_register_print(lcd_drv->lcd_config, + (buf+len), (len + offset)); + + return len; +} + +static int lcd_info_print_ttl(char *buf, int offset) +{ + struct aml_lcd_drv_s *lcd_drv = aml_lcd_get_driver(); + struct lcd_config_s *pconf; + int n, len = 0; + + pconf = lcd_drv->lcd_config; + + n = lcd_debug_info_len(len + offset); + len += snprintf((buf+len), n, + "clk_pol %u\n" + "hvsync_valid %u\n" + "de_valid %u\n" + "rb_swap %u\n" + "bit_swap %u\n\n", + pconf->lcd_control.ttl_config->clk_pol, + ((pconf->lcd_control.ttl_config->sync_valid >> 0) & 1), + ((pconf->lcd_control.ttl_config->sync_valid >> 1) & 1), + ((pconf->lcd_control.ttl_config->swap_ctrl >> 1) & 1), + ((pconf->lcd_control.ttl_config->swap_ctrl >> 0) & 1)); + + n = lcd_debug_info_len(len + offset); + len += snprintf((buf+len), n, + "pinmux_flag %d\n" + "pinmux_pointer 0x%p\n\n", + pconf->pinmux_flag, + pconf->pin); + + return len; +} + +static int lcd_info_print_lvds(char *buf, int offset) +{ + struct aml_lcd_drv_s *lcd_drv = aml_lcd_get_driver(); + struct lcd_config_s *pconf; + int n, len = 0; + + pconf = lcd_drv->lcd_config; + + n = lcd_debug_info_len(len + offset); + len += snprintf((buf+len), n, + "lvds_repack %u\n" + "dual_port %u\n" + "pn_swap %u\n" + "port_swap %u\n" + "lane_reverse %u\n" + "phy_vswing 0x%x\n" + "phy_preem 0x%x\n" + "phy_clk_vswing 0x%x\n" + "phy_clk_preem 0x%x\n\n", + pconf->lcd_control.lvds_config->lvds_repack, + pconf->lcd_control.lvds_config->dual_port, + pconf->lcd_control.lvds_config->pn_swap, + pconf->lcd_control.lvds_config->port_swap, + pconf->lcd_control.lvds_config->lane_reverse, + pconf->lcd_control.lvds_config->phy_vswing, + pconf->lcd_control.lvds_config->phy_preem, + pconf->lcd_control.lvds_config->phy_clk_vswing, + pconf->lcd_control.lvds_config->phy_clk_preem); + + return len; +} + +static int lcd_info_print_vbyone(char *buf, int offset) +{ + struct aml_lcd_drv_s *lcd_drv = aml_lcd_get_driver(); + struct lcd_config_s *pconf; + struct vbyone_config_s *vx1_conf; + int n, len = 0; + + pconf = lcd_drv->lcd_config; + vx1_conf = pconf->lcd_control.vbyone_config; + + n = lcd_debug_info_len(len + offset); + len += snprintf((buf+len), n, + "lane_count %u\n" + "region_num %u\n" + "byte_mode %u\n" + "color_fmt %u\n" + "bit_rate %u\n" + "phy_vswing 0x%x\n" + "phy_preem 0x%x\n" + "intr_en %u\n" + "vsync_intr_en %u\n" + "ctrl_flag 0x%x\n\n", + vx1_conf->lane_count, + vx1_conf->region_num, + vx1_conf->byte_mode, + vx1_conf->color_fmt, + vx1_conf->bit_rate, + vx1_conf->phy_vswing, + vx1_conf->phy_preem, + vx1_conf->intr_en, + vx1_conf->vsync_intr_en, + vx1_conf->ctrl_flag); + if (vx1_conf->ctrl_flag & 0x1) { + n = lcd_debug_info_len(len + offset); + len += snprintf((buf+len), n, + "power_on_reset_en %u\n" + "power_on_reset_delay %ums\n\n", + (vx1_conf->ctrl_flag & 0x1), + vx1_conf->power_on_reset_delay); + } + if (vx1_conf->ctrl_flag & 0x2) { + n = lcd_debug_info_len(len + offset); + len += snprintf((buf+len), n, + "hpd_data_delay_en %u\n" + "hpd_data_delay %ums\n\n", + ((vx1_conf->ctrl_flag >> 1) & 0x1), + vx1_conf->hpd_data_delay); + } + if (vx1_conf->ctrl_flag & 0x4) { + n = lcd_debug_info_len(len + offset); + len += snprintf((buf+len), n, + "cdr_training_hold_en %u\n" + "cdr_training_hold %ums\n\n", + ((vx1_conf->ctrl_flag >> 2) & 0x1), + vx1_conf->cdr_training_hold); + } + + n = lcd_debug_info_len(len + offset); + len += snprintf((buf+len), n, + "pinmux_flag %d\n" + "pinmux_pointer 0x%p\n\n", + pconf->pinmux_flag, + pconf->pin); + + return len; +} + +static int lcd_info_print_mipi(char *buf, int offset) +{ + struct aml_lcd_drv_s *lcd_drv = aml_lcd_get_driver(); + int len = 0; + +#ifdef CONFIG_AMLOGIC_LCD_TABLET + mipi_dsi_print_info(lcd_drv->lcd_config); +#endif + + return len; +} + +static int lcd_info_print_mlvds(char *buf, int offset) +{ + struct aml_lcd_drv_s *lcd_drv = aml_lcd_get_driver(); + struct lcd_config_s *pconf; + int n, len = 0; + + pconf = lcd_drv->lcd_config; + + n = lcd_debug_info_len(len + offset); + len += snprintf((buf+len), n, + "channel_num %d\n" + "channel_sel1 0x%08x\n" + "channel_sel1 0x%08x\n" + "clk_phase 0x%04x\n" + "pn_swap %u\n" + "bit_swap %u\n" + "phy_vswing 0x%x\n" + "phy_preem 0x%x\n" + "bit_rate %dHz\n" + "pi_clk_sel 0x%03x\n\n", + pconf->lcd_control.mlvds_config->channel_num, + pconf->lcd_control.mlvds_config->channel_sel0, + pconf->lcd_control.mlvds_config->channel_sel1, + pconf->lcd_control.mlvds_config->clk_phase, + pconf->lcd_control.mlvds_config->pn_swap, + pconf->lcd_control.mlvds_config->bit_swap, + pconf->lcd_control.mlvds_config->phy_vswing, + pconf->lcd_control.mlvds_config->phy_preem, + pconf->lcd_control.mlvds_config->bit_rate, + pconf->lcd_control.mlvds_config->pi_clk_sel); + + len += lcd_tcon_info_print((buf+len), (len+offset)); + + n = lcd_debug_info_len(len + offset); + len += snprintf((buf+len), n, + "pinmux_flag %d\n" + "pinmux_pointer 0x%p\n\n", + pconf->pinmux_flag, + pconf->pin); + + return len; +} + +static int lcd_info_print_p2p(char *buf, int offset) +{ + struct aml_lcd_drv_s *lcd_drv = aml_lcd_get_driver(); + struct lcd_config_s *pconf; + int n, len = 0; + + pconf = lcd_drv->lcd_config; + + n = lcd_debug_info_len(len + offset); + len += snprintf((buf+len), n, + "channel_num %d\n" + "channel_sel1 0x%08x\n" + "channel_sel1 0x%08x\n" + "clk_phase 0x%04x\n" + "pn_swap %u\n" + "bit_swap %u\n" + "phy_vswing 0x%x\n" + "phy_preem 0x%x\n" + "bit_rate %dHz\n" + "pi_clk_sel 0x%03x\n\n", + pconf->lcd_control.p2p_config->channel_num, + pconf->lcd_control.p2p_config->channel_sel0, + pconf->lcd_control.p2p_config->channel_sel1, + pconf->lcd_control.p2p_config->clk_phase, + pconf->lcd_control.p2p_config->pn_swap, + pconf->lcd_control.p2p_config->bit_swap, + pconf->lcd_control.p2p_config->phy_vswing, + pconf->lcd_control.p2p_config->phy_preem, + pconf->lcd_control.p2p_config->bit_rate, + pconf->lcd_control.p2p_config->pi_clk_sel); + + len += lcd_tcon_info_print((buf+len), (len+offset)); + + n = lcd_debug_info_len(len + offset); + len += snprintf((buf+len), n, + "pinmux_flag %d\n" + "pinmux_pointer 0x%p\n\n", + pconf->pinmux_flag, + pconf->pin); + + return len; +} + static int lcd_info_print(char *buf, int offset) { unsigned int lcd_clk, sync_duration; struct aml_lcd_drv_s *lcd_drv = aml_lcd_get_driver(); struct lcd_config_s *pconf; - struct vbyone_config_s *vx1_conf; int n, len = 0; pconf = lcd_drv->lcd_config; @@ -329,211 +577,21 @@ static int lcd_info_print(char *buf, int offset) pconf->lcd_timing.video_on_pixel, pconf->lcd_timing.video_on_line); - switch (pconf->lcd_basic.lcd_type) { - case LCD_TTL: - n = lcd_debug_info_len(len + offset); - len += snprintf((buf+len), n, - "clk_pol %u\n" - "hvsync_valid %u\n" - "de_valid %u\n" - "rb_swap %u\n" - "bit_swap %u\n\n", - pconf->lcd_control.ttl_config->clk_pol, - ((pconf->lcd_control.ttl_config->sync_valid >> 0) & 1), - ((pconf->lcd_control.ttl_config->sync_valid >> 1) & 1), - ((pconf->lcd_control.ttl_config->swap_ctrl >> 1) & 1), - ((pconf->lcd_control.ttl_config->swap_ctrl >> 0) & 1)); - - len += snprintf((buf+len), n, - "pinmux_flag %d\n" - "pinmux_pointer 0x%p\n\n", - pconf->pinmux_flag, - pconf->pin); - break; - case LCD_LVDS: - n = lcd_debug_info_len(len + offset); - len += snprintf((buf+len), n, - "lvds_repack %u\n" - "dual_port %u\n" - "pn_swap %u\n" - "port_swap %u\n" - "lane_reverse %u\n" - "phy_vswing 0x%x\n" - "phy_preem 0x%x\n" - "phy_clk_vswing 0x%x\n" - "phy_clk_preem 0x%x\n\n", - pconf->lcd_control.lvds_config->lvds_repack, - pconf->lcd_control.lvds_config->dual_port, - pconf->lcd_control.lvds_config->pn_swap, - pconf->lcd_control.lvds_config->port_swap, - pconf->lcd_control.lvds_config->lane_reverse, - pconf->lcd_control.lvds_config->phy_vswing, - pconf->lcd_control.lvds_config->phy_preem, - pconf->lcd_control.lvds_config->phy_clk_vswing, - pconf->lcd_control.lvds_config->phy_clk_preem); - break; - case LCD_VBYONE: - vx1_conf = pconf->lcd_control.vbyone_config; - n = lcd_debug_info_len(len + offset); - len += snprintf((buf+len), n, - "lane_count %u\n" - "region_num %u\n" - "byte_mode %u\n" - "color_fmt %u\n" - "bit_rate %u\n" - "phy_vswing 0x%x\n" - "phy_preem 0x%x\n" - "intr_en %u\n" - "vsync_intr_en %u\n" - "ctrl_flag 0x%x\n\n", - pconf->lcd_control.vbyone_config->lane_count, - pconf->lcd_control.vbyone_config->region_num, - pconf->lcd_control.vbyone_config->byte_mode, - pconf->lcd_control.vbyone_config->color_fmt, - pconf->lcd_control.vbyone_config->bit_rate, - pconf->lcd_control.vbyone_config->phy_vswing, - pconf->lcd_control.vbyone_config->phy_preem, - pconf->lcd_control.vbyone_config->intr_en, - pconf->lcd_control.vbyone_config->vsync_intr_en, - pconf->lcd_control.vbyone_config->ctrl_flag); - if (vx1_conf->ctrl_flag & 0x1) { - n = lcd_debug_info_len(len + offset); - len += snprintf((buf+len), n, - "power_on_reset_en %u\n" - "power_on_reset_delay %ums\n\n", - (vx1_conf->ctrl_flag & 0x1), - vx1_conf->power_on_reset_delay); + if (lcd_debug_info_if) { + if (lcd_debug_info_if->interface_print) { + len += lcd_debug_info_if->interface_print((buf+len), + (len+offset)); + } else { + LCDERR("%s: interface_print is null\n", __func__); } - if (vx1_conf->ctrl_flag & 0x2) { - n = lcd_debug_info_len(len + offset); - len += snprintf((buf+len), n, - "hpd_data_delay_en %u\n" - "hpd_data_delay %ums\n\n", - ((vx1_conf->ctrl_flag >> 1) & 0x1), - vx1_conf->hpd_data_delay); - } - if (vx1_conf->ctrl_flag & 0x4) { - n = lcd_debug_info_len(len + offset); - len += snprintf((buf+len), n, - "cdr_training_hold_en %u\n" - "cdr_training_hold %ums\n\n", - ((vx1_conf->ctrl_flag >> 2) & 0x1), - vx1_conf->cdr_training_hold); - } - - len += snprintf((buf+len), n, - "pinmux_flag %d\n" - "pinmux_pointer 0x%p\n\n", - pconf->pinmux_flag, - pconf->pin); - break; - case LCD_MIPI: -#ifdef CONFIG_AMLOGIC_LCD_TABLET - mipi_dsi_print_info(pconf); -#endif - break; - default: - break; + } else { + LCDERR("%s: lcd_debug_info_if is null\n", __func__); } return len; } -static int lcd_power_info_print(char *buf, int offset) -{ - struct aml_lcd_drv_s *lcd_drv = aml_lcd_get_driver(); - int len = 0; - - len += lcd_power_step_print(lcd_drv->lcd_config, 1, - (buf+len), (len + offset)); - len += lcd_power_step_print(lcd_drv->lcd_config, 0, - (buf+len), (len + offset)); - len += lcd_cpu_gpio_register_print(lcd_drv->lcd_config, - (buf+len), (len + offset)); - - return len; -} - -static unsigned int lcd_reg_dump_clk[] = { - HHI_HDMI_PLL_CNTL, - HHI_HDMI_PLL_CNTL2, - HHI_HDMI_PLL_CNTL3, - HHI_HDMI_PLL_CNTL4, - HHI_HDMI_PLL_CNTL5, - HHI_HDMI_PLL_CNTL6, - HHI_VID_PLL_CLK_DIV, - HHI_VIID_CLK_DIV, - HHI_VIID_CLK_CNTL, - HHI_VID_CLK_CNTL2, -}; - -static unsigned int lcd_reg_dump_clk_axg[] = { - HHI_GP0_PLL_CNTL_AXG, - HHI_GP0_PLL_CNTL2_AXG, - HHI_GP0_PLL_CNTL3_AXG, - HHI_GP0_PLL_CNTL4_AXG, - HHI_GP0_PLL_CNTL5_AXG, - HHI_GP0_PLL_CNTL1_AXG, - HHI_VIID_CLK_DIV, - HHI_VIID_CLK_CNTL, - HHI_VID_CLK_CNTL2, -}; - -static unsigned int lcd_reg_dump_clk_gp0_g12a[] = { - HHI_GP0_PLL_CNTL0_G12A, - HHI_GP0_PLL_CNTL1_G12A, - HHI_GP0_PLL_CNTL2_G12A, - HHI_GP0_PLL_CNTL3_G12A, - HHI_GP0_PLL_CNTL4_G12A, - HHI_GP0_PLL_CNTL5_G12A, - HHI_GP0_PLL_CNTL6_G12A, - HHI_VIID_CLK_DIV, - HHI_VIID_CLK_CNTL, - HHI_VID_CLK_CNTL2, - HHI_MIPIDSI_PHY_CLK_CNTL, -}; - -static unsigned int lcd_reg_dump_clk_hpll_g12a[] = { - HHI_HDMI_PLL_CNTL, - HHI_HDMI_PLL_CNTL2, - HHI_HDMI_PLL_CNTL3, - HHI_HDMI_PLL_CNTL4, - HHI_HDMI_PLL_CNTL5, - HHI_HDMI_PLL_CNTL6, - HHI_HDMI_PLL_CNTL7, - HHI_VID_PLL_CLK_DIV, - HHI_VIID_CLK_DIV, - HHI_VIID_CLK_CNTL, - HHI_VID_CLK_CNTL2, - HHI_MIPIDSI_PHY_CLK_CNTL, -}; - -static unsigned int lcd_reg_dump_encl[] = { - VPU_VIU_VENC_MUX_CTRL, - ENCL_VIDEO_EN, - ENCL_VIDEO_MODE, - ENCL_VIDEO_MODE_ADV, - ENCL_VIDEO_MAX_PXCNT, - ENCL_VIDEO_MAX_LNCNT, - ENCL_VIDEO_HAVON_BEGIN, - ENCL_VIDEO_HAVON_END, - ENCL_VIDEO_VAVON_BLINE, - ENCL_VIDEO_VAVON_ELINE, - ENCL_VIDEO_HSO_BEGIN, - ENCL_VIDEO_HSO_END, - ENCL_VIDEO_VSO_BEGIN, - ENCL_VIDEO_VSO_END, - ENCL_VIDEO_VSO_BLINE, - ENCL_VIDEO_VSO_ELINE, - ENCL_VIDEO_RGBIN_CTRL, - L_GAMMA_CNTL_PORT, - L_RGB_BASE_ADDR, - L_RGB_COEFF_ADDR, - L_POL_CNTL_ADDR, - L_DITH_CNTL_ADDR, -}; - -static int lcd_ttl_reg_print(char *buf, int offset) +static int lcd_reg_print_ttl(char *buf, int offset) { unsigned int reg; int n, len = 0; @@ -609,7 +667,7 @@ static int lcd_ttl_reg_print(char *buf, int offset) return len; } -static int lcd_lvds_reg_print(char *buf, int offset) +static int lcd_reg_print_lvds(char *buf, int offset) { unsigned int reg; int n, len = 0; @@ -645,53 +703,30 @@ static int lcd_lvds_reg_print(char *buf, int offset) return len; } -static int lcd_vbyone_reg_print(char *buf, int offset) +static int lcd_reg_print_vbyone(char *buf, int offset) { unsigned int reg; - struct aml_lcd_drv_s *lcd_drv = aml_lcd_get_driver(); int n, len = 0; n = lcd_debug_info_len(len + offset); len += snprintf((buf+len), n, "\nvbyone regs:\n"); - switch (lcd_drv->data->chip_type) { - case LCD_CHIP_GXTVBB: - n = lcd_debug_info_len(len + offset); - reg = PERIPHS_PIN_MUX_7; - len += snprintf((buf+len), n, - "VX1_PINMUX [0x%04x] = 0x%08x\n", - reg, lcd_periphs_read(reg)); - break; - case LCD_CHIP_TXLX: - n = lcd_debug_info_len(len + offset); - reg = PERIPHS_PIN_MUX_0; - len += snprintf((buf+len), n, - "VX1_PINMUX [0x%04x] = 0x%08x\n", - reg, lcd_periphs_read(reg)); - break; - default: - break; - } n = lcd_debug_info_len(len + offset); reg = VBO_STATUS_L; len += snprintf((buf+len), n, "VX1_STATUS [0x%04x] = 0x%08x\n", reg, lcd_vcbus_read(reg)); - switch (lcd_drv->data->chip_type) { - case LCD_CHIP_TXLX: - n = lcd_debug_info_len(len + offset); - reg = VBO_INFILTER_CTRL; - len += snprintf((buf+len), n, - "VBO_INFILTER_CTRL [0x%04x] = 0x%08x\n", - reg, lcd_vcbus_read(reg)); - n = lcd_debug_info_len(len + offset); - reg = VBO_INSGN_CTRL; - len += snprintf((buf+len), n, - "VBO_INSGN_CTRL [0x%04x] = 0x%08x\n", - reg, lcd_vcbus_read(reg)); - break; - default: - break; - } + + n = lcd_debug_info_len(len + offset); + reg = VBO_INFILTER_CTRL; + len += snprintf((buf+len), n, + "VBO_INFILTER_CTRL [0x%04x] = 0x%08x\n", + reg, lcd_vcbus_read(reg)); + n = lcd_debug_info_len(len + offset); + reg = VBO_INSGN_CTRL; + len += snprintf((buf+len), n, + "VBO_INSGN_CTRL [0x%04x] = 0x%08x\n", + reg, lcd_vcbus_read(reg)); + n = lcd_debug_info_len(len + offset); reg = VBO_FSM_HOLDER_L; len += snprintf((buf+len), n, @@ -726,7 +761,7 @@ static int lcd_vbyone_reg_print(char *buf, int offset) return len; } -static int lcd_mipi_reg_print(char *buf, int offset) +static int lcd_reg_print_mipi(char *buf, int offset) { unsigned int reg; int n, len = 0; @@ -807,7 +842,229 @@ static int lcd_mipi_reg_print(char *buf, int offset) return len; } -static int lcd_phy_analog_reg_print(char *buf, int offset) +static int lcd_reg_print_mlvds(char *buf, int offset) +{ + unsigned int reg; + int n, len = 0; + + n = lcd_debug_info_len(len + offset); + len += snprintf((buf+len), n, "\nmlvds regs:\n"); + + n = lcd_debug_info_len(len + offset); + reg = HHI_TCON_CLK_CNTL; + len += snprintf((buf+len), n, + "HHI_TCON_CLK_CNTL [0x%04x] = 0x%08x\n", + reg, lcd_hiu_read(reg)); + n = lcd_debug_info_len(len + offset); + reg = HHI_DIF_TCON_CNTL0; + len += snprintf((buf+len), n, + "HHI_DIF_TCON_CNTL0 [0x%04x] = 0x%08x\n", + reg, lcd_hiu_read(reg)); + n = lcd_debug_info_len(len + offset); + reg = HHI_DIF_TCON_CNTL1; + len += snprintf((buf+len), n, + "HHI_DIF_TCON_CNTL1 [0x%04x] = 0x%08x\n", + reg, lcd_hiu_read(reg)); + n = lcd_debug_info_len(len + offset); + reg = HHI_DIF_TCON_CNTL2; + len += snprintf((buf+len), n, + "HHI_DIF_TCON_CNTL2 [0x%04x] = 0x%08x\n", + reg, lcd_hiu_read(reg)); + + n = lcd_debug_info_len(len + offset); + reg = TCON_TOP_CTRL; + len += snprintf((buf+len), n, + "TCON_TOP_CTRL [0x%04x] = 0x%08x\n", + reg, lcd_tcon_read(reg)); + n = lcd_debug_info_len(len + offset); + reg = TCON_RGB_IN_MUX; + len += snprintf((buf+len), n, + "TCON_RGB_IN_MUX [0x%04x] = 0x%08x\n", + reg, lcd_tcon_read(reg)); + n = lcd_debug_info_len(len + offset); + reg = TCON_OUT_CH_SEL0; + len += snprintf((buf+len), n, + "TCON_OUT_CH_SEL0 [0x%04x] = 0x%08x\n", + reg, lcd_tcon_read(reg)); + n = lcd_debug_info_len(len + offset); + reg = TCON_OUT_CH_SEL1; + len += snprintf((buf+len), n, + "TCON_OUT_CH_SEL1 [0x%04x] = 0x%08x\n", + reg, lcd_tcon_read(reg)); + n = lcd_debug_info_len(len + offset); + reg = TCON_STATUS0; + len += snprintf((buf+len), n, + "TCON_STATUS0 [0x%04x] = 0x%08x\n", + reg, lcd_tcon_read(reg)); + n = lcd_debug_info_len(len + offset); + reg = TCON_PLLLOCK_CNTL; + len += snprintf((buf+len), n, + "TCON_PLLLOCK_CNTL [0x%04x] = 0x%08x\n", + reg, lcd_tcon_read(reg)); + n = lcd_debug_info_len(len + offset); + reg = TCON_RST_CTRL; + len += snprintf((buf+len), n, + "TCON_RST_CTRL [0x%04x] = 0x%08x\n", + reg, lcd_tcon_read(reg)); + n = lcd_debug_info_len(len + offset); + reg = TCON_AXI_OFST0; + len += snprintf((buf+len), n, + "TCON_AXI_OFST0 [0x%04x] = 0x%08x\n", + reg, lcd_tcon_read(reg)); + n = lcd_debug_info_len(len + offset); + reg = TCON_AXI_OFST1; + len += snprintf((buf+len), n, + "TCON_AXI_OFST1 [0x%04x] = 0x%08x\n", + reg, lcd_tcon_read(reg)); + n = lcd_debug_info_len(len + offset); + reg = TCON_AXI_OFST2; + len += snprintf((buf+len), n, + "TCON_AXI_OFST2 [0x%04x] = 0x%08x\n", + reg, lcd_tcon_read(reg)); + n = lcd_debug_info_len(len + offset); + reg = TCON_CLK_CTRL; + len += snprintf((buf+len), n, + "TCON_CLK_CTRL [0x%04x] = 0x%08x\n", + reg, lcd_tcon_read(reg)); + n = lcd_debug_info_len(len + offset); + reg = TCON_STATUS1; + len += snprintf((buf+len), n, + "TCON_STATUS1 [0x%04x] = 0x%08x\n", + reg, lcd_tcon_read(reg)); + n = lcd_debug_info_len(len + offset); + reg = TCON_DDRIF_CTRL1; + len += snprintf((buf+len), n, + "TCON_DDRIF_CTRL1 [0x%04x] = 0x%08x\n", + reg, lcd_tcon_read(reg)); + reg = TCON_DDRIF_CTRL2; + len += snprintf((buf+len), n, + "TCON_DDRIF_CTRL2 [0x%04x] = 0x%08x\n", + reg, lcd_tcon_read(reg)); + n = lcd_debug_info_len(len + offset); + reg = TCON_INTR_MASKN; + len += snprintf((buf+len), n, + "TCON_INTR_MASKN [0x%04x] = 0x%08x\n", + reg, lcd_tcon_read(reg)); + reg = TCON_INTR; + len += snprintf((buf+len), n, + "TCON_INTR [0x%04x] = 0x%08x\n", + reg, lcd_tcon_read(reg)); + + return len; +} + +static int lcd_reg_print_p2p(char *buf, int offset) +{ + unsigned int reg; + int n, len = 0; + + n = lcd_debug_info_len(len + offset); + len += snprintf((buf+len), n, "\nmlvds regs:\n"); + + n = lcd_debug_info_len(len + offset); + reg = HHI_TCON_CLK_CNTL; + len += snprintf((buf+len), n, + "HHI_TCON_CLK_CNTL [0x%04x] = 0x%08x\n", + reg, lcd_hiu_read(reg)); + n = lcd_debug_info_len(len + offset); + reg = HHI_DIF_TCON_CNTL0; + len += snprintf((buf+len), n, + "HHI_DIF_TCON_CNTL0 [0x%04x] = 0x%08x\n", + reg, lcd_hiu_read(reg)); + n = lcd_debug_info_len(len + offset); + reg = HHI_DIF_TCON_CNTL1; + len += snprintf((buf+len), n, + "HHI_DIF_TCON_CNTL1 [0x%04x] = 0x%08x\n", + reg, lcd_hiu_read(reg)); + n = lcd_debug_info_len(len + offset); + reg = HHI_DIF_TCON_CNTL2; + len += snprintf((buf+len), n, + "HHI_DIF_TCON_CNTL2 [0x%04x] = 0x%08x\n", + reg, lcd_hiu_read(reg)); + + n = lcd_debug_info_len(len + offset); + reg = TCON_TOP_CTRL; + len += snprintf((buf+len), n, + "TCON_TOP_CTRL [0x%04x] = 0x%08x\n", + reg, lcd_tcon_read(reg)); + n = lcd_debug_info_len(len + offset); + reg = TCON_RGB_IN_MUX; + len += snprintf((buf+len), n, + "TCON_RGB_IN_MUX [0x%04x] = 0x%08x\n", + reg, lcd_tcon_read(reg)); + n = lcd_debug_info_len(len + offset); + reg = TCON_OUT_CH_SEL0; + len += snprintf((buf+len), n, + "TCON_OUT_CH_SEL0 [0x%04x] = 0x%08x\n", + reg, lcd_tcon_read(reg)); + n = lcd_debug_info_len(len + offset); + reg = TCON_OUT_CH_SEL1; + len += snprintf((buf+len), n, + "TCON_OUT_CH_SEL1 [0x%04x] = 0x%08x\n", + reg, lcd_tcon_read(reg)); + n = lcd_debug_info_len(len + offset); + reg = TCON_STATUS0; + len += snprintf((buf+len), n, + "TCON_STATUS0 [0x%04x] = 0x%08x\n", + reg, lcd_tcon_read(reg)); + n = lcd_debug_info_len(len + offset); + reg = TCON_PLLLOCK_CNTL; + len += snprintf((buf+len), n, + "TCON_PLLLOCK_CNTL [0x%04x] = 0x%08x\n", + reg, lcd_tcon_read(reg)); + n = lcd_debug_info_len(len + offset); + reg = TCON_RST_CTRL; + len += snprintf((buf+len), n, + "TCON_RST_CTRL [0x%04x] = 0x%08x\n", + reg, lcd_tcon_read(reg)); + n = lcd_debug_info_len(len + offset); + reg = TCON_AXI_OFST0; + len += snprintf((buf+len), n, + "TCON_AXI_OFST0 [0x%04x] = 0x%08x\n", + reg, lcd_tcon_read(reg)); + n = lcd_debug_info_len(len + offset); + reg = TCON_AXI_OFST1; + len += snprintf((buf+len), n, + "TCON_AXI_OFST1 [0x%04x] = 0x%08x\n", + reg, lcd_tcon_read(reg)); + n = lcd_debug_info_len(len + offset); + reg = TCON_AXI_OFST2; + len += snprintf((buf+len), n, + "TCON_AXI_OFST2 [0x%04x] = 0x%08x\n", + reg, lcd_tcon_read(reg)); + n = lcd_debug_info_len(len + offset); + reg = TCON_CLK_CTRL; + len += snprintf((buf+len), n, + "TCON_CLK_CTRL [0x%04x] = 0x%08x\n", + reg, lcd_tcon_read(reg)); + n = lcd_debug_info_len(len + offset); + reg = TCON_STATUS1; + len += snprintf((buf+len), n, + "TCON_STATUS1 [0x%04x] = 0x%08x\n", + reg, lcd_tcon_read(reg)); + n = lcd_debug_info_len(len + offset); + reg = TCON_DDRIF_CTRL1; + len += snprintf((buf+len), n, + "TCON_DDRIF_CTRL1 [0x%04x] = 0x%08x\n", + reg, lcd_tcon_read(reg)); + reg = TCON_DDRIF_CTRL2; + len += snprintf((buf+len), n, + "TCON_DDRIF_CTRL2 [0x%04x] = 0x%08x\n", + reg, lcd_tcon_read(reg)); + n = lcd_debug_info_len(len + offset); + reg = TCON_INTR_MASKN; + len += snprintf((buf+len), n, + "TCON_INTR_MASKN [0x%04x] = 0x%08x\n", + reg, lcd_tcon_read(reg)); + reg = TCON_INTR; + len += snprintf((buf+len), n, + "TCON_INTR [0x%04x] = 0x%08x\n", + reg, lcd_tcon_read(reg)); + + return len; +} + +static int lcd_reg_print_phy_analog(char *buf, int offset) { unsigned int reg; int n, len = 0; @@ -833,7 +1090,7 @@ static int lcd_phy_analog_reg_print(char *buf, int offset) return len; } -static int lcd_mipi_phy_analog_reg_print(char *buf, int offset) +static int lcd_reg_print_mipi_phy_analog(char *buf, int offset) { unsigned int reg; int n, len = 0; @@ -864,84 +1121,79 @@ static int lcd_reg_print(char *buf, int offset) struct aml_lcd_drv_s *lcd_drv = aml_lcd_get_driver(); int i, n, len = 0; struct lcd_config_s *pconf; + unsigned int *table; pconf = lcd_drv->lcd_config; n = lcd_debug_info_len(len + offset); len += snprintf((buf+len), n, "\nclk regs:\n"); - switch (lcd_drv->data->chip_type) { - case LCD_CHIP_AXG: - for (i = 0; i < ARRAY_SIZE(lcd_reg_dump_clk_axg); i++) { - n = lcd_debug_info_len(len + offset); - len += snprintf((buf+len), n, - "hiu [0x%04x] = 0x%08x\n", - lcd_reg_dump_clk_axg[i], - lcd_hiu_read(lcd_reg_dump_clk_axg[i])); - } - break; - case LCD_CHIP_G12A: - case LCD_CHIP_G12B: - if (lcd_drv->lcd_clk_path) { - for (i = 0; i < ARRAY_SIZE(lcd_reg_dump_clk_gp0_g12a); - i++) { + if (lcd_debug_info_reg) { + if (lcd_debug_info_reg->reg_clk_table) { + table = lcd_debug_info_reg->reg_clk_table; + i = 0; + while (i < LCD_DEBUG_REG_CNT_MAX) { + if (table[i] == LCD_DEBUG_REG_END) + break; n = lcd_debug_info_len(len + offset); len += snprintf((buf+len), n, - "hiu [0x%04x] = 0x%08x\n", - lcd_reg_dump_clk_gp0_g12a[i], - lcd_hiu_read( - lcd_reg_dump_clk_gp0_g12a[i])); + "hiu [0x%08x] = 0x%08x\n", + table[i], lcd_hiu_read(table[i])); + i++; } } else { - for (i = 0; i < ARRAY_SIZE(lcd_reg_dump_clk_hpll_g12a); - i++) { + LCDERR("%s: reg_clk_table is null\n", __func__); + } + + if (lcd_debug_info_reg->reg_encl_table) { + n = lcd_debug_info_len(len + offset); + len += snprintf((buf+len), n, "\nencl regs:\n"); + table = lcd_debug_info_reg->reg_encl_table; + i = 0; + while (i < LCD_DEBUG_REG_CNT_MAX) { + if (table[i] == LCD_DEBUG_REG_END) + break; n = lcd_debug_info_len(len + offset); len += snprintf((buf+len), n, - "hiu [0x%04x] = 0x%08x\n", - lcd_reg_dump_clk_hpll_g12a[i], - lcd_hiu_read( - lcd_reg_dump_clk_hpll_g12a[i])); + "vcbus [0x%04x] = 0x%08x\n", + table[i], lcd_vcbus_read(table[i])); + i++; + } + } else { + LCDERR("%s: reg_encl_table is null\n", __func__); + } + + if (lcd_debug_info_reg->reg_pinmux_table) { + n = lcd_debug_info_len(len + offset); + len += snprintf((buf+len), n, "\npinmux regs:\n"); + table = lcd_debug_info_reg->reg_pinmux_table; + i = 0; + while (i < LCD_DEBUG_REG_CNT_MAX) { + if (table[i] == LCD_DEBUG_REG_END) + break; + len += snprintf((buf+len), n, + "PERIPHS_PIN_MUX [0x%08x] = 0x%08x\n", + table[i], lcd_periphs_read(table[i])); + i++; } } - break; - default: - for (i = 0; i < ARRAY_SIZE(lcd_reg_dump_clk); i++) { - n = lcd_debug_info_len(len + offset); - len += snprintf((buf+len), n, - "hiu [0x%04x] = 0x%08x\n", - lcd_reg_dump_clk[i], - lcd_hiu_read(lcd_reg_dump_clk[i])); + } else { + LCDERR("%s: lcd_debug_info_reg is null\n", __func__); + } + + if (lcd_debug_info_if) { + if (lcd_debug_info_if->reg_dump_interface) { + len += lcd_debug_info_if->reg_dump_interface((buf+len), + (len+offset)); + } else { + LCDERR("%s: reg_dump_interface is null\n", __func__); } - break; - } - n = lcd_debug_info_len(len + offset); - len += snprintf((buf+len), n, "\nencl regs:\n"); - for (i = 0; i < ARRAY_SIZE(lcd_reg_dump_encl); i++) { - n = lcd_debug_info_len(len + offset); - len += snprintf((buf+len), n, - "vcbus [0x%04x] = 0x%08x\n", - lcd_reg_dump_encl[i], - lcd_vcbus_read(lcd_reg_dump_encl[i])); - } - - switch (pconf->lcd_basic.lcd_type) { - case LCD_TTL: - len += lcd_ttl_reg_print((buf+len), (len + offset)); - break; - case LCD_LVDS: - len += lcd_lvds_reg_print((buf+len), (len + offset)); - len += lcd_phy_analog_reg_print((buf+len), (len + offset)); - break; - case LCD_VBYONE: - len += lcd_vbyone_reg_print((buf+len), (len + offset)); - len += lcd_phy_analog_reg_print((buf+len), (len + offset)); - break; - case LCD_MIPI: - len += lcd_mipi_reg_print((buf+len), (len + offset)); - len += lcd_mipi_phy_analog_reg_print((buf+len), (len + offset)); - break; - default: - break; + if (lcd_debug_info_if->reg_dump_phy) { + len += lcd_debug_info_if->reg_dump_phy((buf+len), + (len+offset)); + } + } else { + LCDERR("%s: lcd_debug_info_if is null\n", __func__); } return len; @@ -1464,6 +1716,8 @@ static ssize_t lcd_debug_change_store(struct class *class, struct lvds_config_s *lvds_conf; struct vbyone_config_s *vx1_conf; struct dsi_config_s *dsi_conf; + struct mlvds_config_s *mlvds_conf; + struct p2p_config_s *p2p_conf; pconf = lcd_drv->lcd_config; switch (buf[0]) { @@ -1635,32 +1889,95 @@ static ssize_t lcd_debug_change_store(struct class *class, } break; case 'm': - dsi_conf = pconf->lcd_control.mipi_config; - ret = sscanf(buf, "mipi %d %d %d %d %d %d %d %d", - &val[0], &val[1], &val[2], &val[3], - &val[4], &val[5], &val[6], &val[7]); - if (ret == 8) { - dsi_conf->lane_num = (unsigned char)val[0]; - dsi_conf->bit_rate_max = val[1]; - dsi_conf->factor_numerator = val[2]; - dsi_conf->operation_mode_init = (unsigned char)val[3]; - dsi_conf->operation_mode_display = - (unsigned char)val[4]; - dsi_conf->video_mode_type = (unsigned char)val[5]; - dsi_conf->clk_always_hs = (unsigned char)val[6]; - dsi_conf->phy_switch = (unsigned char)val[7]; - pr_info("change mipi_dsi config:\n" + if (buf[1] == 'i') { + dsi_conf = pconf->lcd_control.mipi_config; + ret = sscanf(buf, "mipi %d %d %d %d %d %d %d %d", + &val[0], &val[1], &val[2], &val[3], + &val[4], &val[5], &val[6], &val[7]); + if (ret == 8) { + dsi_conf->lane_num = (unsigned char)val[0]; + dsi_conf->bit_rate_max = val[1]; + dsi_conf->factor_numerator = val[2]; + dsi_conf->operation_mode_init = + (unsigned char)val[3]; + dsi_conf->operation_mode_display = + (unsigned char)val[4]; + dsi_conf->video_mode_type = + (unsigned char)val[5]; + dsi_conf->clk_always_hs = (unsigned char)val[6]; + dsi_conf->phy_switch = (unsigned char)val[7]; + pr_info("change mipi_dsi config:\n" "lane_num=%d, bit_rate_max=%dMhz, factor_numerator=%d\n" "operation_mode_init=%d, operation_mode_display=%d\n" "video_mode_type=%d, clk_always_hs=%d, phy_switch=%d\n", - dsi_conf->lane_num, - dsi_conf->bit_rate_max, - dsi_conf->factor_numerator, - dsi_conf->operation_mode_init, - dsi_conf->operation_mode_display, - dsi_conf->video_mode_type, - dsi_conf->clk_always_hs, - dsi_conf->phy_switch); + dsi_conf->lane_num, + dsi_conf->bit_rate_max, + dsi_conf->factor_numerator, + dsi_conf->operation_mode_init, + dsi_conf->operation_mode_display, + dsi_conf->video_mode_type, + dsi_conf->clk_always_hs, + dsi_conf->phy_switch); + lcd_debug_change_clk_change( + pconf->lcd_timing.lcd_clk); + pconf->change_flag = 1; + } else { + LCDERR("invalid data\n"); + return -EINVAL; + } + } else if (buf[1] == 'l') { + mlvds_conf = pconf->lcd_control.mlvds_config; + ret = sscanf(buf, "mlvds %d %x %x %x %d %d", + &val[0], &val[1], &val[2], &val[3], + &val[4], &val[5]); + if (ret == 6) { + mlvds_conf->channel_num = val[0]; + mlvds_conf->channel_sel0 = val[1]; + mlvds_conf->channel_sel1 = val[2]; + mlvds_conf->clk_phase = val[3]; + mlvds_conf->pn_swap = val[4]; + mlvds_conf->bit_swap = val[5]; + pr_info("change mlvds config:\n" + "channel_num=%d,\n" + "channel_sel0=0x%08x, channel_sel1=0x%08x,\n" + "clk_phase=0x%04x,\n" + "pn_swap=%d, bit_swap=%d\n", + mlvds_conf->channel_num, + mlvds_conf->channel_sel0, + mlvds_conf->channel_sel1, + mlvds_conf->clk_phase, + mlvds_conf->pn_swap, + mlvds_conf->bit_swap); + lcd_debug_change_clk_change( + pconf->lcd_timing.lcd_clk); + pconf->change_flag = 1; + } else { + LCDERR("invalid data\n"); + return -EINVAL; + } + } + break; + case 'p': + p2p_conf = pconf->lcd_control.p2p_config; + ret = sscanf(buf, "p2p %d %x %x %x %d %d", + &val[0], &val[1], &val[2], &val[3], &val[4], &val[5]); + if (ret == 6) { + p2p_conf->channel_num = val[0]; + p2p_conf->channel_sel0 = val[1]; + p2p_conf->channel_sel1 = val[2]; + p2p_conf->clk_phase = val[3]; + p2p_conf->pn_swap = val[4]; + p2p_conf->bit_swap = val[5]; + pr_info("change mlvds config:\n" + "channel_num=%d,\n" + "channel_sel0=0x%08x, channel_sel1=0x%08x,\n" + "clk_phase=0x%04x,\n" + "pn_swap=%d, bit_swap=%d\n", + p2p_conf->channel_num, + p2p_conf->channel_sel0, + p2p_conf->channel_sel1, + p2p_conf->clk_phase, + p2p_conf->pn_swap, p2p_conf->bit_swap); lcd_debug_change_clk_change(pconf->lcd_timing.lcd_clk); pconf->change_flag = 1; } else { @@ -1912,7 +2229,7 @@ static ssize_t lcd_debug_ss_store(struct class *class, return -EINVAL; } lcd_drv->lcd_config->lcd_timing.ss_level = temp; - lcd_set_spread_spectrum(); + lcd_set_spread_spectrum(temp); return count; } @@ -1950,6 +2267,7 @@ static ssize_t lcd_debug_clk_store(struct class *class, if (ret) { pr_info("change clk_path error\n"); } else { + lcd_drv->lcd_clk_path = temp; lcd_clk_generate_parameter(lcd_drv->lcd_config); pr_info("change clk_path: %d\n", temp); } @@ -2580,17 +2898,6 @@ static const char *lcd_mipi_debug_usage_str = { "\n" }; -static const char *lcd_edp_debug_usage_str = { -"Usage:\n" -" echo > edp ; set edp config\n" -"data format:\n" -" : 0=1.62G, 1=2.7G\n" -" : 1/2/4\n" -" : 0=no use, 1=use, default=0\n" -" : 0=asyncronous, 1=synchronous, default=1\n" -"\n" -}; - static const char *lcd_mipi_cmd_debug_usage_str = { "Usage:\n" " echo ...... > mpcmd ; send mipi cmd\n" @@ -2607,6 +2914,50 @@ static const char *lcd_mipi_cmd_debug_usage_str = { "\n" }; +static const char *lcd_mlvds_debug_usage_str = { +"Usage:\n" +" echo > minilvds ; set minilvds config\n" +"data format:\n" +" : minilvds 8 channels mapping in tx 10 channels\n" +" : bit[13:12]=clk01_pi_sel, bit[11:8]=pi2, bit[7:4]=pi1, bit[3:0]=pi0\n" +" : 0=normal, 1=swap p/n channels\n" +" : 0=normal, 1=swap bit LSB/MSB\n" +"\n" +}; + +static const char *lcd_p2p_debug_usage_str = { +"Usage:\n" +" echo > minilvds ; set minilvds config\n" +"data format:\n" +" : minilvds 8 channels mapping in tx 10 channels\n" +" : bit[13:12]=clk01_pi_sel, bit[11:8]=pi2, bit[7:4]=pi1, bit[3:0]=pi0\n" +" : 0=normal, 1=swap p/n channels\n" +" : 0=normal, 1=swap bit LSB/MSB\n" +"\n" +}; + +static const char *lcd_debug_tcon_usage_str = { + "Usage:\n" + " echo reg > tcon ; print tcon system regs\n" + " echo reg save > tcon ; save tcon system regs to bin file\n" + "\n" + " echo table > tcon ; print tcon reg table\n" + " echo table r > tcon ; read tcon reg table by specified index\n" + " echo table w > tcon ; write tcon reg table by specified index\n" + " echo table d > tcon ; dump tcon reg table\n" + "data format:\n" + " : hex number\n" + " : hex number\n" + " : dec number\n" + "\n" + " echo table update > tcon ; update tcon reg table into tcon system regs\n" + " echo table save > tcon ; save tcon reg table to bin file\n" + "\n" + " echo od > tcon ; tcon over driver control\n" + "data format:\n" + " : 0=disable, 1=enable\n" +}; + static ssize_t lcd_ttl_debug_show(struct class *class, struct class_attribute *attr, char *buf) { @@ -2631,10 +2982,22 @@ static ssize_t lcd_mipi_debug_show(struct class *class, return sprintf(buf, "%s\n", lcd_mipi_debug_usage_str); } -static ssize_t lcd_edp_debug_show(struct class *class, +static ssize_t lcd_mlvds_debug_show(struct class *class, struct class_attribute *attr, char *buf) { - return sprintf(buf, "%s\n", lcd_edp_debug_usage_str); + return sprintf(buf, "%s\n", lcd_mlvds_debug_usage_str); +} + +static ssize_t lcd_p2p_debug_show(struct class *class, + struct class_attribute *attr, char *buf) +{ + return sprintf(buf, "%s\n", lcd_p2p_debug_usage_str); +} + +static ssize_t lcd_tcon_debug_show(struct class *class, + struct class_attribute *attr, char *buf) +{ + return sprintf(buf, "%s\n", lcd_debug_tcon_usage_str); } static ssize_t lcd_ttl_debug_store(struct class *class, @@ -2832,10 +3195,66 @@ static ssize_t lcd_mipi_debug_store(struct class *class, return count; } -static ssize_t lcd_edp_debug_store(struct class *class, +static ssize_t lcd_mlvds_debug_store(struct class *class, struct class_attribute *attr, const char *buf, size_t count) { - pr_info("to do\n"); + int ret = 0; + struct aml_lcd_drv_s *lcd_drv = aml_lcd_get_driver(); + struct mlvds_config_s *mlvds_conf; + + mlvds_conf = lcd_drv->lcd_config->lcd_control.mlvds_config; + ret = sscanf(buf, "%d %x %x %x %d %d", + &mlvds_conf->channel_num, + &mlvds_conf->channel_sel0, &mlvds_conf->channel_sel1, + &mlvds_conf->clk_phase, + &mlvds_conf->pn_swap, &mlvds_conf->bit_swap); + if (ret == 6) { + pr_info("set minilvds config:\n" + "channel_num=%d,\n" + "channel_sel0=0x%08x, channel_sel1=0x%08x,\n" + "clk_phase=0x%04x,\n" + "pn_swap=%d, bit_swap=%d\n", + mlvds_conf->channel_num, + mlvds_conf->channel_sel0, mlvds_conf->channel_sel1, + mlvds_conf->clk_phase, + mlvds_conf->pn_swap, mlvds_conf->bit_swap); + lcd_debug_config_update(); + } else { + pr_info("invalid data\n"); + return -EINVAL; + } + + return count; +} + +static ssize_t lcd_p2p_debug_store(struct class *class, + struct class_attribute *attr, const char *buf, size_t count) +{ + int ret = 0; + struct aml_lcd_drv_s *lcd_drv = aml_lcd_get_driver(); + struct p2p_config_s *p2p_conf; + + p2p_conf = lcd_drv->lcd_config->lcd_control.p2p_config; + ret = sscanf(buf, "%d %x %x %x %d %d", + &p2p_conf->channel_num, + &p2p_conf->channel_sel0, &p2p_conf->channel_sel1, + &p2p_conf->clk_phase, + &p2p_conf->pn_swap, &p2p_conf->bit_swap); + if (ret == 6) { + pr_info("set minilvds config:\n" + "channel_num=%d,\n" + "channel_sel0=0x%08x, channel_sel1=0x%08x,\n" + "clk_phase=0x%04x,\n" + "pn_swap=%d, bit_swap=%d\n", + p2p_conf->channel_num, + p2p_conf->channel_sel0, p2p_conf->channel_sel1, + p2p_conf->clk_phase, + p2p_conf->pn_swap, p2p_conf->bit_swap); + lcd_debug_config_update(); + } else { + pr_info("invalid data\n"); + return -EINVAL; + } return count; } @@ -2944,6 +3363,82 @@ static void lcd_phy_config_update(unsigned int *para, int cnt) __func__, cnt); } break; + case LCD_MLVDS: + if (cnt >= 2) { + if ((para[0] > 7) || (para[1] > 3)) { + LCDERR("%s: wrong value:\n", __func__); + pr_info("vswing=%d, preemphasis=%d\n", + para[0], para[1]); + return; + } + + pconf->lcd_control.mlvds_config->phy_vswing = para[0]; + pconf->lcd_control.mlvds_config->phy_preem = para[1]; + + data32 = lcd_hiu_read(HHI_DIF_CSI_PHY_CNTL1); + data32 &= ~((0x7 << 3) | (0x7 << 0) | (0x3 << 23)); + data32 |= ((para[0] << 3) | (para[0] << 0) | + (para[1] << 23)); + lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL1, data32); + data32 = lcd_hiu_read(HHI_DIF_CSI_PHY_CNTL2); + data32 &= ~((0x3 << 14) | (0x3 << 12) | + (0x3 << 26) | (0x3 << 24)); + data32 |= ((para[1] << 14) | (para[1] << 12) | + (para[1] << 26) | (para[1] << 24)); + lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL2, data32); + data32 = lcd_hiu_read(HHI_DIF_CSI_PHY_CNTL3); + data32 &= ~((0x3 << 6) | (0x3 << 4) | + (0x3 << 2) | (0x3 << 0) | (0x3 << 30)); + data32 |= ((para[1] << 6) | (para[1] << 4) | + (para[1] << 2) | (para[1] << 0) | + (para[1] << 30)); + lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL3, data32); + + LCDPR("%s: vswing=0x%x, preemphasis=0x%x\n", + __func__, para[0], para[1]); + } else { + LCDERR("%s: invalid parameters cnt: %d\n", + __func__, cnt); + } + break; + case LCD_P2P: + if (cnt >= 2) { + if ((para[0] > 7) || (para[1] > 3)) { + LCDERR("%s: wrong value:\n", __func__); + pr_info("vswing=%d, preemphasis=%d\n", + para[0], para[1]); + return; + } + + pconf->lcd_control.p2p_config->phy_vswing = para[0]; + pconf->lcd_control.p2p_config->phy_preem = para[1]; + + data32 = lcd_hiu_read(HHI_DIF_CSI_PHY_CNTL1); + data32 &= ~((0x7 << 3) | (0x7 << 0) | (0x3 << 23)); + data32 |= ((para[0] << 3) | (para[0] << 0) | + (para[1] << 23)); + lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL1, data32); + data32 = lcd_hiu_read(HHI_DIF_CSI_PHY_CNTL2); + data32 &= ~((0x3 << 14) | (0x3 << 12) | + (0x3 << 26) | (0x3 << 24)); + data32 |= ((para[1] << 14) | (para[1] << 12) | + (para[1] << 26) | (para[1] << 24)); + lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL2, data32); + data32 = lcd_hiu_read(HHI_DIF_CSI_PHY_CNTL3); + data32 &= ~((0x3 << 6) | (0x3 << 4) | + (0x3 << 2) | (0x3 << 0) | (0x3 << 30)); + data32 |= ((para[1] << 6) | (para[1] << 4) | + (para[1] << 2) | (para[1] << 0) | + (para[1] << 30)); + lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL3, data32); + + LCDPR("%s: vswing=0x%x, preemphasis=0x%x\n", + __func__, para[0], para[1]); + } else { + LCDERR("%s: invalid parameters cnt: %d\n", + __func__, cnt); + } + break; default: LCDERR("%s: not support lcd_type: %s\n", __func__, lcd_type_type_to_str(type)); @@ -2981,6 +3476,20 @@ static ssize_t lcd_phy_debug_show(struct class *class, len += sprintf(buf+len, "vswing=0x%x, preemphasis=0x%x\n", vswing, preem); break; + case LCD_MLVDS: + vswing = pconf->lcd_control.mlvds_config->phy_vswing; + preem = pconf->lcd_control.mlvds_config->phy_preem; + len += sprintf(buf+len, "%s:\n", __func__); + len += sprintf(buf+len, "vswing=0x%x, preemphasis=0x%x\n", + vswing, preem); + break; + case LCD_P2P: + vswing = pconf->lcd_control.p2p_config->phy_vswing; + preem = pconf->lcd_control.p2p_config->phy_preem; + len += sprintf(buf+len, "%s:\n", __func__); + len += sprintf(buf+len, "vswing=0x%x, preemphasis=0x%x\n", + vswing, preem); + break; default: len = sprintf(buf, "%s: invalid lcd_type: %d\n", __func__, pconf->lcd_basic.lcd_type); @@ -3010,6 +3519,224 @@ static ssize_t lcd_phy_debug_store(struct class *class, return count; } +static void lcd_tcon_reg_table_save(char *path, unsigned char *reg_table, + unsigned int size) +{ + struct file *filp = NULL; + loff_t pos = 0; + void *buf = NULL; + mm_segment_t old_fs = get_fs(); + + set_fs(KERNEL_DS); + filp = filp_open(path, O_RDWR|O_CREAT, 0666); + + if (IS_ERR(filp)) { + LCDERR("%s: create %s error\n", __func__, path); + set_fs(old_fs); + return; + } + + pos = 0; + buf = (void *)reg_table; + vfs_write(filp, buf, size, &pos); + + vfs_fsync(filp, 0); + filp_close(filp, NULL); + set_fs(old_fs); + + LCDPR("save tcon reg table to %s finished\n", path); +} + +static void lcd_tcon_reg_save(char *path, unsigned int size) +{ + struct file *filp = NULL; + loff_t pos = 0; + unsigned char *temp; + void *buf = NULL; + mm_segment_t old_fs = get_fs(); + int ret; + + set_fs(KERNEL_DS); + filp = filp_open(path, O_RDWR|O_CREAT, 0666); + + if (IS_ERR(filp)) { + LCDERR("%s: create %s error\n", __func__, path); + set_fs(old_fs); + return; + } + + temp = kcalloc(size, sizeof(unsigned char), GFP_KERNEL); + if (!temp) { + LCDERR("%s: Not enough memory\n", __func__); + filp_close(filp, NULL); + set_fs(old_fs); + return; + } + ret = lcd_tcon_core_reg_get(temp, size); + if (ret) { + LCDPR("save tcon reg failed\n"); + filp_close(filp, NULL); + set_fs(old_fs); + kfree(temp); + return; + } + + pos = 0; + buf = (void *)temp; + vfs_write(filp, buf, size, &pos); + + vfs_fsync(filp, 0); + filp_close(filp, NULL); + set_fs(old_fs); + kfree(temp); + + LCDPR("save tcon reg to %s success\n", path); +} + +static ssize_t lcd_tcon_debug_store(struct class *class, + struct class_attribute *attr, const char *buf, size_t count) +{ + char *buf_orig; + char *parm[47] = {NULL}; + unsigned int temp = 0, val, i, n, size; + unsigned char data; + unsigned char *table; + int ret = -1; + + size = lcd_tcon_reg_table_size_get(); + if (size <= 0) + return count; + table = lcd_tcon_reg_table_get(); + if (table == NULL) + return count; + + if (!buf) + return count; + buf_orig = kstrdup(buf, GFP_KERNEL); + if (buf_orig == NULL) { + LCDERR("%s: buf malloc error\n", __func__); + return count; + } + lcd_debug_parse_param(buf_orig, (char **)&parm); + + if (strcmp(parm[0], "reg") == 0) { + if (parm[1] == NULL) { + lcd_tcon_reg_readback_print(); + goto lcd_tcon_debug_store_end; + } + if (strcmp(parm[1], "save") == 0) { + if (parm[2] != NULL) + lcd_tcon_reg_save(parm[2], size); + else + pr_info("invalid save path\n"); + } + } else if (strcmp(parm[0], "table") == 0) { + if (parm[1] == NULL) { + lcd_tcon_reg_table_print(); + goto lcd_tcon_debug_store_end; + } + if (strcmp(parm[1], "r") == 0) { + if (parm[2] != NULL) { + ret = kstrtouint(parm[2], 16, &temp); + if (ret) { + pr_info("invalid parameters\n"); + goto lcd_tcon_debug_store_err; + } + if (temp < size) { + data = table[temp]; + pr_info("read tcon table[%d]=0x%02x\n", + temp, data); + } else { + pr_info("invalid table index: %d\n", + temp); + } + } + } else if (strcmp(parm[1], "w") == 0) { + if (parm[3] != NULL) { + ret = kstrtouint(parm[2], 16, &temp); + if (ret) { + pr_info("invalid parameters\n"); + goto lcd_tcon_debug_store_err; + } + ret = kstrtouint(parm[3], 16, &val); + if (ret) { + pr_info("invalid parameters\n"); + goto lcd_tcon_debug_store_err; + } + data = (unsigned char)val; + if (temp < size) { + table[temp] = data; + pr_info("write tcon table[%d]=0x%02x\n", + temp, data); + } else { + pr_info("invalid table index: %d\n", + temp); + } + } + } else if (strcmp(parm[1], "d") == 0) { + if (parm[3] != NULL) { + ret = 0; + if (!kstrtouint(parm[2], 16, &val)) + temp = (unsigned int)val; + else + ret = 1; + if (!kstrtouint(parm[3], 16, &val)) + n = (unsigned char)val; + else + ret = 1; + if (ret) { + pr_info("invalid parameters\n"); + goto lcd_tcon_debug_store_err; + } + pr_info("dump tcon table:\n"); + for (i = temp; i < (temp + n); i++) { + if (i > size) + break; + data = table[i]; + pr_info(" [%d]=0x%02x\n", temp, data); + } + } + } else if (strcmp(parm[1], "update") == 0) { + lcd_tcon_core_reg_update(); + } else if (strcmp(parm[1], "save") == 0) { + if (parm[2] != NULL) + lcd_tcon_reg_table_save(parm[2], table, size); + else + pr_info("invalid save path\n"); + } + } else if (strcmp(parm[0], "od") == 0) { /* over drive */ + if (parm[1] != NULL) { + if (strcmp(parm[1], "status") == 0) { + temp = lcd_tcon_od_get(); + if (temp) { + LCDPR("tcon od is enabled: %d\n", temp); + } else { + LCDPR("tcon od is disabled: %d\n", + temp); + } + } else { + if (!kstrtouint(parm[1], 10, &temp)) { + if (temp) + lcd_tcon_od_set(1); + else + lcd_tcon_od_set(0); + } + } + } + } else { + LCDERR("wrong command\n"); + goto lcd_tcon_debug_store_err; + } + +lcd_tcon_debug_store_end: + kfree(buf_orig); + return count; + +lcd_tcon_debug_store_err: + kfree(buf_orig); + return count; +} + static ssize_t lcd_mipi_cmd_debug_show(struct class *class, struct class_attribute *attr, char *buf) { @@ -3223,25 +3950,51 @@ static ssize_t lcd_mipi_mode_debug_store(struct class *class, return count; } -static struct class_attribute lcd_interface_debug_class_attrs[] = { +static struct class_attribute lcd_debug_class_attrs_ttl[] = { __ATTR(ttl, 0644, lcd_ttl_debug_show, lcd_ttl_debug_store), + __ATTR(null, 0644, NULL, NULL), +}; + +static struct class_attribute lcd_debug_class_attrs_lvds[] = { __ATTR(lvds, 0644, lcd_lvds_debug_show, lcd_lvds_debug_store), - __ATTR(vbyone, 0644, - lcd_vx1_debug_show, lcd_vx1_debug_store), - __ATTR(mipi, 0644, - lcd_mipi_debug_show, lcd_mipi_debug_store), - __ATTR(edp, 0644, - lcd_edp_debug_show, lcd_edp_debug_store), -}; - -static struct class_attribute lcd_phy_debug_class_attrs[] = { __ATTR(phy, 0644, lcd_phy_debug_show, lcd_phy_debug_store), + __ATTR(null, 0644, NULL, NULL), }; -static struct class_attribute lcd_mipi_debug_class_attrs[] = { +static struct class_attribute lcd_debug_class_attrs_vbyone[] = { + __ATTR(vbyone, 0644, + lcd_vx1_debug_show, lcd_vx1_debug_store), + __ATTR(phy, 0644, + lcd_phy_debug_show, lcd_phy_debug_store), + __ATTR(null, 0644, NULL, NULL), +}; + +static struct class_attribute lcd_debug_class_attrs_mlvds[] = { + __ATTR(mlvds, 0644, + lcd_mlvds_debug_show, lcd_mlvds_debug_store), + __ATTR(phy, 0644, + lcd_phy_debug_show, lcd_phy_debug_store), + __ATTR(tcon, 0644, + lcd_tcon_debug_show, lcd_tcon_debug_store), + __ATTR(null, 0644, NULL, NULL), +}; + +static struct class_attribute lcd_debug_class_attrs_p2p[] = { + __ATTR(p2p, 0644, + lcd_p2p_debug_show, lcd_p2p_debug_store), + __ATTR(phy, 0644, + lcd_phy_debug_show, lcd_phy_debug_store), + __ATTR(tcon, 0644, + lcd_tcon_debug_show, lcd_tcon_debug_store), + __ATTR(null, 0644, NULL, NULL), +}; + +static struct class_attribute lcd_debug_class_attrs_mipi[] = { + __ATTR(mipi, 0644, + lcd_mipi_debug_show, lcd_mipi_debug_store), __ATTR(mpcmd, 0644, lcd_mipi_cmd_debug_show, lcd_mipi_cmd_debug_store), __ATTR(mpread, 0644, @@ -3249,13 +4002,16 @@ static struct class_attribute lcd_mipi_debug_class_attrs[] = { __ATTR(mpstate, 0644, lcd_mipi_state_debug_show, NULL), __ATTR(mpmode, 0644, lcd_mipi_mode_debug_show, lcd_mipi_mode_debug_store), + __ATTR(null, 0644, NULL, NULL), }; -int lcd_class_creat(void) +#define LCD_DEBUG_CLASS_ATTRS_IF_MAX 10 +static int lcd_class_creat(void) { - int i; struct aml_lcd_drv_s *lcd_drv = aml_lcd_get_driver(); - int type; + struct class *lcd_class; + struct class_attribute *lcd_attr; + int i; lcd_drv->lcd_screen_restore = lcd_screen_restore; lcd_drv->lcd_screen_black = lcd_screen_black; @@ -3267,76 +4023,60 @@ int lcd_class_creat(void) LCDERR("create lcd debug class fail\n"); return -1; } + lcd_class = lcd_drv->lcd_debug_class; for (i = 0; i < ARRAY_SIZE(lcd_debug_class_attrs); i++) { - if (class_create_file(lcd_drv->lcd_debug_class, - &lcd_debug_class_attrs[i])) { + if (class_create_file(lcd_class, &lcd_debug_class_attrs[i])) { LCDERR("create lcd debug attribute %s fail\n", lcd_debug_class_attrs[i].attr.name); } } - type = lcd_drv->lcd_config->lcd_basic.lcd_type; - for (i = 0; i < ARRAY_SIZE(lcd_interface_debug_class_attrs); i++) { - if (strcmp(lcd_interface_debug_class_attrs[i].attr.name, - lcd_type_type_to_str(type))) - continue; - if (class_create_file(lcd_drv->lcd_debug_class, - &lcd_interface_debug_class_attrs[i])) { - LCDERR("create lcd_interface debug attribute %s fail\n", - lcd_interface_debug_class_attrs[i].attr.name); - } - } - - switch (type) { - case LCD_LVDS: - case LCD_VBYONE: - for (i = 0; i < ARRAY_SIZE(lcd_phy_debug_class_attrs); i++) { - if (class_create_file(lcd_drv->lcd_debug_class, - &lcd_phy_debug_class_attrs[i])) { - LCDERR("create phy debug attribute %s fail\n", - lcd_phy_debug_class_attrs[i].attr.name); + if (lcd_debug_info_if) { + if (lcd_debug_info_if->class_attrs) { + lcd_attr = lcd_debug_info_if->class_attrs; + while (lcd_attr) { + if (strcmp(lcd_attr->attr.name, "null") == 0) + break; + if (class_create_file(lcd_class, lcd_attr)) { + LCDERR( + "create lcd_interface debug attribute %s fail\n", + lcd_attr->attr.name); + } + lcd_attr++; } + } else { + LCDERR("lcd_debug_info_if class_attrs is null\n"); } - break; - case LCD_MIPI: - dread.value = kcalloc(DSI_READ_CNT_MAX, sizeof(unsigned char), - GFP_KERNEL); - lcd_drv->lcd_config->lcd_control.mipi_config->dread = &dread; - for (i = 0; i < ARRAY_SIZE - (lcd_mipi_debug_class_attrs); i++) { - if (class_create_file(lcd_drv->lcd_debug_class, - &lcd_mipi_debug_class_attrs[i])) { - LCDERR("create mipi debug attr %s fail\n", - lcd_mipi_debug_class_attrs[i].attr.name); - } - } - break; - default: - break; + } else { + LCDERR("lcd_debug_info_if is null\n"); } return 0; } -int lcd_class_remove(void) +static int lcd_class_remove(void) { - int i; struct aml_lcd_drv_s *lcd_drv = aml_lcd_get_driver(); - int type; + struct class *lcd_class; + struct class_attribute *lcd_attr; + int i; - for (i = 0; i < ARRAY_SIZE(lcd_debug_class_attrs); i++) { - class_remove_file(lcd_drv->lcd_debug_class, - &lcd_debug_class_attrs[i]); - } + lcd_class = lcd_drv->lcd_debug_class; - type = lcd_drv->lcd_config->lcd_basic.lcd_type; - for (i = 0; i < ARRAY_SIZE(lcd_interface_debug_class_attrs); i++) { - if (strcmp(lcd_interface_debug_class_attrs[i].attr.name, - lcd_type_type_to_str(type))) - continue; - class_remove_file(lcd_drv->lcd_debug_class, - &lcd_interface_debug_class_attrs[i]); + for (i = 0; i < ARRAY_SIZE(lcd_debug_class_attrs); i++) + class_remove_file(lcd_class, &lcd_debug_class_attrs[i]); + + if (lcd_debug_info_if) { + if (lcd_debug_info_if->class_attrs) { + lcd_attr = lcd_debug_info_if->class_attrs; + while (lcd_attr) { + if (strcmp(lcd_attr->attr.name, "null") == 0) + break; + class_remove_file(lcd_class, lcd_attr); + lcd_attr++; + } + } } class_destroy(lcd_drv->lcd_debug_class); @@ -3345,3 +4085,165 @@ int lcd_class_remove(void) return 0; } +/* ********************************** + * lcd debug match data + * ********************************** + */ +/* chip_type data */ +static struct lcd_debug_info_reg_s lcd_debug_info_reg_gxl = { + .reg_clk_table = lcd_reg_dump_clk_dft, + .reg_encl_table = lcd_reg_dump_encl_dft, + .reg_pinmux_table = lcd_reg_dump_pinmux_gxl, +}; + +static struct lcd_debug_info_reg_s lcd_debug_info_reg_txl = { + .reg_clk_table = lcd_reg_dump_clk_dft, + .reg_encl_table = lcd_reg_dump_encl_dft, + .reg_pinmux_table = lcd_reg_dump_pinmux_txl, +}; + +static struct lcd_debug_info_reg_s lcd_debug_info_reg_txlx = { + .reg_clk_table = lcd_reg_dump_clk_dft, + .reg_encl_table = lcd_reg_dump_encl_dft, + .reg_pinmux_table = lcd_reg_dump_pinmux_txlx, +}; + +static struct lcd_debug_info_reg_s lcd_debug_info_reg_axg = { + .reg_clk_table = lcd_reg_dump_clk_axg, + .reg_encl_table = lcd_reg_dump_encl_dft, + .reg_pinmux_table = NULL, +}; + +static struct lcd_debug_info_reg_s lcd_debug_info_reg_g12a_clk_path0 = { + .reg_clk_table = lcd_reg_dump_clk_hpll_g12a, + .reg_encl_table = lcd_reg_dump_encl_dft, + .reg_pinmux_table = NULL, +}; + +static struct lcd_debug_info_reg_s lcd_debug_info_reg_g12a_clk_path1 = { + .reg_clk_table = lcd_reg_dump_clk_gp0_g12a, + .reg_encl_table = lcd_reg_dump_encl_dft, + .reg_pinmux_table = NULL, +}; + +static struct lcd_debug_info_reg_s lcd_debug_info_reg_tl1 = { + .reg_clk_table = lcd_reg_dump_clk_tl1, + .reg_encl_table = lcd_reg_dump_encl_tl1, + .reg_pinmux_table = lcd_reg_dump_pinmux_tl1, +}; + +/* interface data */ +static struct lcd_debug_info_if_s lcd_debug_info_if_ttl = { + .interface_print = lcd_info_print_ttl, + .reg_dump_interface = lcd_reg_print_ttl, + .reg_dump_phy = NULL, + .class_attrs = lcd_debug_class_attrs_ttl, +}; + +static struct lcd_debug_info_if_s lcd_debug_info_if_lvds = { + .interface_print = lcd_info_print_lvds, + .reg_dump_interface = lcd_reg_print_lvds, + .reg_dump_phy = lcd_reg_print_phy_analog, + .class_attrs = lcd_debug_class_attrs_lvds, +}; + +static struct lcd_debug_info_if_s lcd_debug_info_if_vbyone = { + .interface_print = lcd_info_print_vbyone, + .reg_dump_interface = lcd_reg_print_vbyone, + .reg_dump_phy = lcd_reg_print_phy_analog, + .class_attrs = lcd_debug_class_attrs_vbyone, +}; + +static struct lcd_debug_info_if_s lcd_debug_info_if_mipi = { + .interface_print = lcd_info_print_mipi, + .reg_dump_interface = lcd_reg_print_mipi, + .reg_dump_phy = lcd_reg_print_mipi_phy_analog, + .class_attrs = lcd_debug_class_attrs_mipi, +}; + +static struct lcd_debug_info_if_s lcd_debug_info_if_mlvds = { + .interface_print = lcd_info_print_mlvds, + .reg_dump_interface = lcd_reg_print_mlvds, + .reg_dump_phy = lcd_reg_print_phy_analog, + .class_attrs = lcd_debug_class_attrs_mlvds, +}; + +static struct lcd_debug_info_if_s lcd_debug_info_if_p2p = { + .interface_print = lcd_info_print_p2p, + .reg_dump_interface = lcd_reg_print_p2p, + .reg_dump_phy = lcd_reg_print_phy_analog, + .class_attrs = lcd_debug_class_attrs_p2p, +}; + +int lcd_debug_probe(void) +{ + struct aml_lcd_drv_s *lcd_drv = aml_lcd_get_driver(); + int lcd_type, ret; + + lcd_type = lcd_drv->lcd_config->lcd_basic.lcd_type; + + switch (lcd_drv->data->chip_type) { + case LCD_CHIP_TL1: + lcd_debug_info_reg = &lcd_debug_info_reg_tl1; + break; + case LCD_CHIP_G12A: + case LCD_CHIP_G12B: + if (lcd_drv->lcd_clk_path) + lcd_debug_info_reg = &lcd_debug_info_reg_g12a_clk_path1; + else + lcd_debug_info_reg = &lcd_debug_info_reg_g12a_clk_path0; + break; + case LCD_CHIP_AXG: + lcd_debug_info_reg = &lcd_debug_info_reg_axg; + break; + case LCD_CHIP_TXLX: + lcd_debug_info_reg = &lcd_debug_info_reg_txlx; + break; + case LCD_CHIP_TXL: + lcd_debug_info_reg = &lcd_debug_info_reg_txl; + break; + case LCD_CHIP_GXL: + case LCD_CHIP_GXM: + lcd_debug_info_reg = &lcd_debug_info_reg_gxl; + break; + default: + lcd_debug_info_reg = NULL; + break; + } + + switch (lcd_type) { + case LCD_TTL: + lcd_debug_info_if = &lcd_debug_info_if_ttl; + break; + case LCD_LVDS: + lcd_debug_info_if = &lcd_debug_info_if_lvds; + break; + case LCD_VBYONE: + lcd_debug_info_if = &lcd_debug_info_if_vbyone; + break; + case LCD_MIPI: + lcd_debug_info_if = &lcd_debug_info_if_mipi; + break; + case LCD_MLVDS: + lcd_debug_info_if = &lcd_debug_info_if_mlvds; + break; + case LCD_P2P: + lcd_debug_info_if = &lcd_debug_info_if_p2p; + break; + default: + lcd_debug_info_if = NULL; + break; + } + + ret = lcd_class_creat(); + + return ret; +} + +int lcd_debug_remove(void) +{ + int ret; + + ret = lcd_class_remove(); + return ret; +} diff --git a/drivers/amlogic/media/vout/lcd/lcd_debug.h b/drivers/amlogic/media/vout/lcd/lcd_debug.h new file mode 100644 index 000000000000..8c72d7b00ea3 --- /dev/null +++ b/drivers/amlogic/media/vout/lcd/lcd_debug.h @@ -0,0 +1,187 @@ +/* + * drivers/amlogic/media/vout/lcd/lcd_debug.h + * + * Copyright (C) 2017 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +#ifndef __AML_LCD_DEBUG_H__ +#define __AML_LCD_DEBUG_H__ +#include "lcd_reg.h" + +#define LCD_DEBUG_REG_CNT_MAX 30 +#define LCD_DEBUG_REG_END 0xffffffff + +struct lcd_debug_info_reg_s { + unsigned int *reg_clk_table; + unsigned int *reg_encl_table; + unsigned int *reg_pinmux_table; +}; + +struct lcd_debug_info_if_s { + int (*interface_print)(char *buf, int offset); + int (*reg_dump_interface)(char *buf, int offset); + int (*reg_dump_phy)(char *buf, int offset); + struct class_attribute *class_attrs; +}; + +static unsigned int lcd_reg_dump_clk_dft[] = { + HHI_HDMI_PLL_CNTL, + HHI_HDMI_PLL_CNTL2, + HHI_HDMI_PLL_CNTL3, + HHI_HDMI_PLL_CNTL4, + HHI_HDMI_PLL_CNTL5, + HHI_HDMI_PLL_CNTL6, + HHI_VID_PLL_CLK_DIV, + HHI_VIID_CLK_DIV, + HHI_VIID_CLK_CNTL, + HHI_VID_CLK_CNTL2, + LCD_DEBUG_REG_END, +}; + +static unsigned int lcd_reg_dump_clk_axg[] = { + HHI_GP0_PLL_CNTL_AXG, + HHI_GP0_PLL_CNTL2_AXG, + HHI_GP0_PLL_CNTL3_AXG, + HHI_GP0_PLL_CNTL4_AXG, + HHI_GP0_PLL_CNTL5_AXG, + HHI_GP0_PLL_CNTL1_AXG, + HHI_VIID_CLK_DIV, + HHI_VIID_CLK_CNTL, + HHI_VID_CLK_CNTL2, + LCD_DEBUG_REG_END, +}; + +static unsigned int lcd_reg_dump_clk_gp0_g12a[] = { + HHI_GP0_PLL_CNTL0_G12A, + HHI_GP0_PLL_CNTL1_G12A, + HHI_GP0_PLL_CNTL2_G12A, + HHI_GP0_PLL_CNTL3_G12A, + HHI_GP0_PLL_CNTL4_G12A, + HHI_GP0_PLL_CNTL5_G12A, + HHI_GP0_PLL_CNTL6_G12A, + HHI_VIID_CLK_DIV, + HHI_VIID_CLK_CNTL, + HHI_VID_CLK_CNTL2, + HHI_MIPIDSI_PHY_CLK_CNTL, + LCD_DEBUG_REG_END, +}; + +static unsigned int lcd_reg_dump_clk_hpll_g12a[] = { + HHI_HDMI_PLL_CNTL, + HHI_HDMI_PLL_CNTL2, + HHI_HDMI_PLL_CNTL3, + HHI_HDMI_PLL_CNTL4, + HHI_HDMI_PLL_CNTL5, + HHI_HDMI_PLL_CNTL6, + HHI_HDMI_PLL_CNTL7, + HHI_VID_PLL_CLK_DIV, + HHI_VIID_CLK_DIV, + HHI_VIID_CLK_CNTL, + HHI_VID_CLK_CNTL2, + HHI_MIPIDSI_PHY_CLK_CNTL, + LCD_DEBUG_REG_END, +}; + +static unsigned int lcd_reg_dump_clk_tl1[] = { + HHI_TCON_PLL_CNTL0, + HHI_TCON_PLL_CNTL1, + HHI_TCON_PLL_CNTL2, + HHI_TCON_PLL_CNTL3, + HHI_TCON_PLL_CNTL4, + HHI_VID_PLL_CLK_DIV, + HHI_VIID_CLK_DIV, + HHI_VIID_CLK_CNTL, + HHI_VID_CLK_CNTL2, + LCD_DEBUG_REG_END, +}; + +static unsigned int lcd_reg_dump_encl_dft[] = { + VPU_VIU_VENC_MUX_CTRL, + ENCL_VIDEO_EN, + ENCL_VIDEO_MODE, + ENCL_VIDEO_MODE_ADV, + ENCL_VIDEO_MAX_PXCNT, + ENCL_VIDEO_MAX_LNCNT, + ENCL_VIDEO_HAVON_BEGIN, + ENCL_VIDEO_HAVON_END, + ENCL_VIDEO_VAVON_BLINE, + ENCL_VIDEO_VAVON_ELINE, + ENCL_VIDEO_HSO_BEGIN, + ENCL_VIDEO_HSO_END, + ENCL_VIDEO_VSO_BEGIN, + ENCL_VIDEO_VSO_END, + ENCL_VIDEO_VSO_BLINE, + ENCL_VIDEO_VSO_ELINE, + ENCL_VIDEO_RGBIN_CTRL, + L_GAMMA_CNTL_PORT, + L_RGB_BASE_ADDR, + L_RGB_COEFF_ADDR, + L_POL_CNTL_ADDR, + L_DITH_CNTL_ADDR, + LCD_DEBUG_REG_END, +}; + +static unsigned int lcd_reg_dump_encl_tl1[] = { + VPU_VIU_VENC_MUX_CTRL, + ENCL_VIDEO_EN, + ENCL_VIDEO_MODE, + ENCL_VIDEO_MODE_ADV, + ENCL_VIDEO_MAX_PXCNT, + ENCL_VIDEO_MAX_LNCNT, + ENCL_VIDEO_HAVON_BEGIN, + ENCL_VIDEO_HAVON_END, + ENCL_VIDEO_VAVON_BLINE, + ENCL_VIDEO_VAVON_ELINE, + ENCL_VIDEO_HSO_BEGIN, + ENCL_VIDEO_HSO_END, + ENCL_VIDEO_VSO_BEGIN, + ENCL_VIDEO_VSO_END, + ENCL_VIDEO_VSO_BLINE, + ENCL_VIDEO_VSO_ELINE, + ENCL_VIDEO_RGBIN_CTRL, + ENCL_INBUF_CNTL0, + ENCL_INBUF_CNTL1, + L_GAMMA_CNTL_PORT, + L_RGB_BASE_ADDR, + L_RGB_COEFF_ADDR, + L_POL_CNTL_ADDR, + L_DITH_CNTL_ADDR, + LCD_DEBUG_REG_END, +}; + +static unsigned int lcd_reg_dump_pinmux_gxl[] = { + PERIPHS_PIN_MUX_1, + PERIPHS_PIN_MUX_3, + LCD_DEBUG_REG_END, +}; + +static unsigned int lcd_reg_dump_pinmux_txl[] = { + PERIPHS_PIN_MUX_0, + LCD_DEBUG_REG_END, +}; + +static unsigned int lcd_reg_dump_pinmux_txlx[] = { + PERIPHS_PIN_MUX_0, + PERIPHS_PIN_MUX_8, + LCD_DEBUG_REG_END, +}; + +static unsigned int lcd_reg_dump_pinmux_tl1[] = { + PERIPHS_PIN_MUX_7, + PERIPHS_PIN_MUX_8, + PERIPHS_PIN_MUX_9, + LCD_DEBUG_REG_END, +}; + +#endif diff --git a/drivers/amlogic/media/vout/lcd/lcd_extern/lcd_extern.c b/drivers/amlogic/media/vout/lcd/lcd_extern/lcd_extern.c index f84a616d992a..0de4274ad9fc 100644 --- a/drivers/amlogic/media/vout/lcd/lcd_extern/lcd_extern.c +++ b/drivers/amlogic/media/vout/lcd/lcd_extern/lcd_extern.c @@ -86,6 +86,11 @@ static struct lcd_extern_config_s lcd_extern_config = { struct aml_lcd_extern_driver_s *aml_lcd_extern_get_driver(int index) { + if (lcd_ext_driver == NULL) { + EXTERR("invalid driver\n"); + return NULL; + } + if (index >= LCD_EXTERN_INDEX_INVALID) { EXTERR("invalid driver index: %d\n", index); return NULL; diff --git a/drivers/amlogic/media/vout/lcd/lcd_reg.c b/drivers/amlogic/media/vout/lcd/lcd_reg.c index 93c569025269..690bc666d051 100644 --- a/drivers/amlogic/media/vout/lcd/lcd_reg.c +++ b/drivers/amlogic/media/vout/lcd/lcd_reg.c @@ -30,7 +30,8 @@ #define LCD_MAP_PERIPHS 0 #define LCD_MAP_DSI_HOST 1 #define LCD_MAP_DSI_PHY 2 -#define LCD_MAP_MAX 3 +#define LCD_MAP_TCON 3 +#define LCD_MAP_MAX 4 int lcd_reg_gxb[] = { LCD_MAP_PERIPHS, @@ -43,6 +44,12 @@ int lcd_reg_axg[] = { LCD_MAP_MAX, }; +int lcd_reg_tl1[] = { + LCD_MAP_TCON, + LCD_MAP_PERIPHS, + LCD_MAP_MAX, +}; + struct lcd_reg_map_s { unsigned int base_addr; unsigned int size; @@ -55,7 +62,6 @@ static struct lcd_reg_map_s *lcd_reg_map; int lcd_ioremap(struct platform_device *pdev) { int i = 0; - int ret = 0; int *table; struct resource *res; struct aml_lcd_drv_s *lcd_drv = aml_lcd_get_driver(); @@ -63,7 +69,7 @@ int lcd_ioremap(struct platform_device *pdev) lcd_reg_map = kcalloc(LCD_MAP_MAX, sizeof(struct lcd_reg_map_s), GFP_KERNEL); if (lcd_reg_map == NULL) { - LCDPR("lcd_reg_map buf malloc error\n"); + LCDERR("%s: lcd_reg_map buf malloc error\n", __func__); return -1; } table = lcd_drv->data->reg_map_table; @@ -72,19 +78,29 @@ int lcd_ioremap(struct platform_device *pdev) break; res = platform_get_resource(pdev, IORESOURCE_MEM, i); + if (res == NULL) { + LCDERR("%s: lcd_reg resource get error\n", __func__); + kfree(lcd_reg_map); + lcd_reg_map = NULL; + return -1; + } lcd_reg_map[table[i]].base_addr = res->start; lcd_reg_map[table[i]].size = resource_size(res); lcd_reg_map[table[i]].p = devm_ioremap_nocache(&pdev->dev, res->start, lcd_reg_map[table[i]].size); if (lcd_reg_map[table[i]].p == NULL) { lcd_reg_map[table[i]].flag = 0; - LCDERR("reg map failed: 0x%x\n", + LCDERR("%s: reg map failed: 0x%x\n", + __func__, lcd_reg_map[table[i]].base_addr); - ret = -1; + kfree(lcd_reg_map); + lcd_reg_map = NULL; + return -1; } else { lcd_reg_map[table[i]].flag = 1; if (lcd_debug_print_flag) { - LCDPR("reg mapped: 0x%x -> %p\n", + LCDPR("%s: reg mapped: 0x%x -> %p\n", + __func__, lcd_reg_map[table[i]].base_addr, lcd_reg_map[table[i]].p); } @@ -93,7 +109,7 @@ int lcd_ioremap(struct platform_device *pdev) i++; } - return ret; + return 0; } static int check_lcd_ioremap(int n) @@ -167,6 +183,44 @@ static inline void __iomem *check_lcd_dsi_phy_reg(unsigned int _reg) return p; } +static inline void __iomem *check_lcd_tcon_reg(unsigned int _reg) +{ + void __iomem *p; + int reg_bus; + unsigned int reg_offset; + + reg_bus = LCD_MAP_TCON; + if (check_lcd_ioremap(reg_bus)) + return NULL; + + reg_offset = LCD_REG_OFFSET(_reg); + if (reg_offset >= lcd_reg_map[reg_bus].size) { + LCDERR("invalid dsi_phy reg offset: 0x%04x\n", _reg); + return NULL; + } + p = lcd_reg_map[reg_bus].p + reg_offset; + return p; +} + +static inline void __iomem *check_lcd_tcon_reg_byte(unsigned int _reg) +{ + void __iomem *p; + int reg_bus; + unsigned int reg_offset; + + reg_bus = LCD_MAP_TCON; + if (check_lcd_ioremap(reg_bus)) + return NULL; + + reg_offset = LCD_REG_OFFSET_BYTE(_reg); + if (reg_offset >= lcd_reg_map[reg_bus].size) { + LCDERR("invalid dsi_phy reg offset: 0x%04x\n", _reg); + return NULL; + } + p = lcd_reg_map[reg_bus].p + reg_offset; + return p; +} + unsigned int lcd_vcbus_read(unsigned int reg) { return aml_read_vcbus(reg); @@ -357,3 +411,75 @@ void dsi_phy_clr_mask(unsigned int reg, unsigned int _mask) dsi_phy_write(reg, (dsi_phy_read(reg) & (~(_mask)))); } +unsigned int lcd_tcon_read(unsigned int _reg) +{ + void __iomem *p; + + p = check_lcd_tcon_reg(_reg); + if (p) + return readl(p); + else + return -1; +}; +void lcd_tcon_write(unsigned int _reg, unsigned int _value) +{ + void __iomem *p; + + p = check_lcd_tcon_reg(_reg); + if (p) + writel(_value, p); +}; + +void lcd_tcon_setb(unsigned int reg, unsigned int value, + unsigned int _start, unsigned int _len) +{ + lcd_tcon_write(reg, ((lcd_tcon_read(reg) & + (~(((1L << _len)-1) << _start))) | + ((value & ((1L << _len)-1)) << _start))); +} +unsigned int lcd_tcon_getb(unsigned int reg, + unsigned int _start, unsigned int _len) +{ + return (lcd_tcon_read(reg) >> _start) & ((1L << _len)-1); +} + +void lcd_tcon_set_mask(unsigned int reg, unsigned int _mask) +{ + lcd_tcon_write(reg, (lcd_tcon_read(reg) | (_mask))); +} +void lcd_tcon_clr_mask(unsigned int reg, unsigned int _mask) +{ + lcd_tcon_write(reg, (lcd_tcon_read(reg) & (~(_mask)))); +} + +unsigned char lcd_tcon_read_byte(unsigned int _reg) +{ + void __iomem *p; + + p = check_lcd_tcon_reg_byte(_reg); + if (p) + return readb(p); + else + return -1; +}; +void lcd_tcon_write_byte(unsigned int _reg, unsigned char _value) +{ + void __iomem *p; + + p = check_lcd_tcon_reg_byte(_reg); + if (p) + writeb(_value, p); +}; + +void lcd_tcon_setb_byte(unsigned int reg, unsigned char value, + unsigned int _start, unsigned int _len) +{ + lcd_tcon_write_byte(reg, ((lcd_tcon_read_byte(reg) & + (~(((1L << _len)-1) << _start))) | + ((value & ((1L << _len)-1)) << _start))); +} +unsigned char lcd_tcon_getb_byte(unsigned int reg, + unsigned int _start, unsigned int _len) +{ + return (lcd_tcon_read_byte(reg) >> _start) & ((1L << _len)-1); +} diff --git a/drivers/amlogic/media/vout/lcd/lcd_reg.h b/drivers/amlogic/media/vout/lcd/lcd_reg.h index 29f5d7a6d4a3..b09f71d21d36 100644 --- a/drivers/amlogic/media/vout/lcd/lcd_reg.h +++ b/drivers/amlogic/media/vout/lcd/lcd_reg.h @@ -22,8 +22,9 @@ /* register offset address define */ /* base & offset */ -#define LCD_REG_OFFSET(reg) ((reg << 2)) +#define LCD_REG_OFFSET(reg) ((reg << 2)) #define LCD_REG_OFFSET_MIPI_HOST(reg) (((reg & 0xff) << 2)) +#define LCD_REG_OFFSET_BYTE(reg) ((reg)) /* PERIPHS: 0xc8834400 */ @@ -120,13 +121,6 @@ #define HHI_EDP_APB_CLK_CNTL_M8M2 0x82 #define HHI_EDP_TX_PHY_CNTL0 0x9c #define HHI_EDP_TX_PHY_CNTL1 0x9d -/* m8b */ -#define HHI_VID_PLL_CNTL 0xc8 -#define HHI_VID_PLL_CNTL2 0xc9 -#define HHI_VID_PLL_CNTL3 0xca -#define HHI_VID_PLL_CNTL4 0xcb -#define HHI_VID_PLL_CNTL5 0xcc -#define HHI_VID_PLL_CNTL6 0xcd /* g9tv */ #define HHI_HDMI_PLL_CNTL 0xc8 #define HHI_HDMI_PLL_CNTL2 0xc9 @@ -134,8 +128,14 @@ #define HHI_HDMI_PLL_CNTL4 0xcb #define HHI_HDMI_PLL_CNTL5 0xcc #define HHI_HDMI_PLL_CNTL6 0xcd -/*G12A*/ +/* G12A */ #define HHI_HDMI_PLL_CNTL7 0xce +/* TL1 */ +#define HHI_TCON_PLL_CNTL0 0x020 +#define HHI_TCON_PLL_CNTL1 0x021 +#define HHI_TCON_PLL_CNTL2 0x022 +#define HHI_TCON_PLL_CNTL3 0x023 +#define HHI_TCON_PLL_CNTL4 0x0df #define HHI_DSI_LVDS_EDP_CNTL0 0xd1 #define HHI_DSI_LVDS_EDP_CNTL1 0xd2 @@ -179,6 +179,11 @@ #define HHI_MIPI_CNTL1 0x01 #define HHI_MIPI_CNTL2 0x02 +#define HHI_DIF_TCON_CNTL0 0x3c +#define HHI_DIF_TCON_CNTL1 0x3d +#define HHI_DIF_TCON_CNTL2 0x3e +#define HHI_TCON_CLK_CNTL 0xf0 + /* Global control: RESET_CBUS_BASE = 0x11 */ #define VERSION_CTRL 0x1100 #define RESET0_REGISTER 0x1101 @@ -904,85 +909,40 @@ #define ENCL_DACSEL_0 0x1cc9 #define ENCL_DACSEL_1 0x1cca -/* ******************************** - * ENCT: VCBUS_BASE = 0x1c - */ -/* ENCT */ -/* bit 15:8 -- vfifo2vd_vd_sel - * bit 7 -- vfifo2vd_drop - * bit 6:1 -- vfifo2vd_delay - * bit 0 -- vfifo2vd_en - */ -#define ENCT_VFIFO2VD_CTL 0x1c20 -/* bit 12:0 -- vfifo2vd_pixel_start */ -#define ENCT_VFIFO2VD_PIXEL_START 0x1c21 -/* bit 12:00 -- vfifo2vd_pixel_end */ -#define ENCT_VFIFO2VD_PIXEL_END 0x1c22 -/* bit 10:0 -- vfifo2vd_line_top_start */ -#define ENCT_VFIFO2VD_LINE_TOP_START 0x1c23 -/* bit 10:00 -- vfifo2vd_line_top_end */ -#define ENCT_VFIFO2VD_LINE_TOP_END 0x1c24 -/* bit 10:00 -- vfifo2vd_line_bot_start */ -#define ENCT_VFIFO2VD_LINE_BOT_START 0x1c25 -/* bit 10:00 -- vfifo2vd_line_bot_end */ -#define ENCT_VFIFO2VD_LINE_BOT_END 0x1c26 -#define ENCT_VFIFO2VD_CTL2 0x1c27 -#define ENCT_TST_EN 0x1c28 -#define ENCT_TST_MDSEL 0x1c29 -#define ENCT_TST_Y 0x1c2a -#define ENCT_TST_CB 0x1c2b -#define ENCT_TST_CR 0x1c2c -#define ENCT_TST_CLRBAR_STRT 0x1c2d -#define ENCT_TST_CLRBAR_WIDTH 0x1c2e -#define ENCT_TST_VDCNT_STSET 0x1c2f +#define ENCL_INBUF_CNTL0 0x1cd3 +#define ENCL_INBUF_CNTL1 0x1cd4 -/* ENCT registers */ -#define ENCT_VIDEO_EN 0x1c60 -#define ENCT_VIDEO_Y_SCL 0x1c61 -#define ENCT_VIDEO_PB_SCL 0x1c62 -#define ENCT_VIDEO_PR_SCL 0x1c63 -#define ENCT_VIDEO_Y_OFFST 0x1c64 -#define ENCT_VIDEO_PB_OFFST 0x1c65 -#define ENCT_VIDEO_PR_OFFST 0x1c66 -/* ----- Video mode */ -#define ENCT_VIDEO_MODE 0x1c67 -#define ENCT_VIDEO_MODE_ADV 0x1c68 -/* --------------- Debug pins */ -#define ENCT_DBG_PX_RST 0x1c69 -#define ENCT_DBG_LN_RST 0x1c6a -#define ENCT_DBG_PX_INT 0x1c6b -#define ENCT_DBG_LN_INT 0x1c6c -/* ----------- Video Advanced setting */ -#define ENCT_VIDEO_YFP1_HTIME 0x1c6d -#define ENCT_VIDEO_YFP2_HTIME 0x1c6e -#define ENCT_VIDEO_YC_DLY 0x1c6f -#define ENCT_VIDEO_MAX_PXCNT 0x1c70 -#define ENCT_VIDEO_HAVON_END 0x1c71 -#define ENCT_VIDEO_HAVON_BEGIN 0x1c72 -#define ENCT_VIDEO_VAVON_ELINE 0x1c73 -#define ENCT_VIDEO_VAVON_BLINE 0x1c74 -#define ENCT_VIDEO_HSO_BEGIN 0x1c75 -#define ENCT_VIDEO_HSO_END 0x1c76 -#define ENCT_VIDEO_VSO_BEGIN 0x1c77 -#define ENCT_VIDEO_VSO_END 0x1c78 -#define ENCT_VIDEO_VSO_BLINE 0x1c79 -#define ENCT_VIDEO_VSO_ELINE 0x1c7a -#define ENCT_VIDEO_MAX_LNCNT 0x1c7b -#define ENCT_VIDEO_BLANKY_VAL 0x1c7c -#define ENCT_VIDEO_BLANKPB_VAL 0x1c7d -#define ENCT_VIDEO_BLANKPR_VAL 0x1c7e -#define ENCT_VIDEO_HOFFST 0x1c7f -#define ENCT_VIDEO_VOFFST 0x1c80 -#define ENCT_VIDEO_RGB_CTRL 0x1c81 -#define ENCT_VIDEO_FILT_CTRL 0x1c82 -#define ENCT_VIDEO_OFLD_VPEQ_OFST 0x1c83 -#define ENCT_VIDEO_OFLD_VOAV_OFST 0x1c84 -#define ENCT_VIDEO_MATRIX_CB 0x1c85 -#define ENCT_VIDEO_MATRIX_CR 0x1c86 -#define ENCT_VIDEO_RGBIN_CTRL 0x1c87 -#define ENCT_MAX_LINE_SWITCH_POINT 0x1c88 -#define ENCT_DACSEL_0 0x1c89 -#define ENCT_DACSEL_1 0x1c8a +/* ******************************** + * TCON TOP: TCON_TOP_BASE = 0x2000 + * ******************************** + */ +#define TCON_CORE_REG_START 0x0000 + +#define TCON_CTRL_TIMING_BASE 0x01b0 + +#define TCON_TOP_CTRL 0x2000 +#define TCON_RGB_IN_MUX 0x2001 +#define TCON_OUT_CH_SEL0 0x2002 +#define TCON_OUT_CH_SEL1 0x2003 +#define TCON_I2C_DEGLITCH_CNTL 0x2004 +#define TCON_STATUS0 0x2008 /* read only */ +#define TCON_PLLLOCK_CNTL 0x2009 +#define TCON_PLLLCK_RST_CNT 0x200a +#define TCON_RST_CTRL 0x200b +#define TCON_AXI_OFST0 0x200c +#define TCON_DDRIF_CTRL0 0x200d +#define TCON_CLK_CTRL 0x200e +#define TCON_DDRIF_CTRL1 0x200f +#define TCON_STATUS1 0x2010 /* read only */ +#define TCON_DDRIF_CTRL2 0x2011 +#define TCON_STATUS2 0x2012 /* read only */ +#define TCON_AXI_OFST1 0x2013 +#define TCON_AXI_OFST2 0x2014 +#define TCON_GPO_CTRL0 0x2015 +#define TCON_GPO_CTRL1 0x2016 +#define TCON_GPO_CTRL2 0x2017 +#define TCON_INTR_MASKN 0x2022 +#define TCON_INTR 0x2023 /* read only */ /* ******************************** * Video post-processing: VPP_VCBUS_BASE = 0x1d @@ -1497,6 +1457,9 @@ /* *********************************************** * register access api */ +extern int lcd_reg_gxb[]; +extern int lcd_reg_axg[]; +extern int lcd_reg_tl1[]; extern int lcd_ioremap(struct platform_device *pdev); extern unsigned int lcd_vcbus_read(unsigned int _reg); @@ -1530,22 +1493,34 @@ extern void lcd_pinmux_clr_mask(unsigned int _reg, unsigned int _mask); extern unsigned int dsi_host_read(unsigned int _reg); extern void dsi_host_write(unsigned int _reg, unsigned int _value); extern void dsi_host_setb(unsigned int reg, unsigned int value, - unsigned int _start, unsigned int _len); + unsigned int _start, unsigned int _len); extern unsigned int dsi_host_getb(unsigned int reg, - unsigned int _start, unsigned int _len); + unsigned int _start, unsigned int _len); extern void dsi_host_set_mask(unsigned int reg, unsigned int _mask); extern void dsi_host_clr_mask(unsigned int reg, unsigned int _mask); extern unsigned int dsi_phy_read(unsigned int _reg); extern void dsi_phy_write(unsigned int _reg, unsigned int _value); extern void dsi_phy_setb(unsigned int reg, unsigned int value, - unsigned int _start, unsigned int _len); + unsigned int _start, unsigned int _len); extern unsigned int dsi_phy_getb(unsigned int reg, - unsigned int _start, unsigned int _len); + unsigned int _start, unsigned int _len); extern void dsi_phy_set_mask(unsigned int reg, unsigned int _mask); extern void dsi_phy_clr_mask(unsigned int reg, unsigned int _mask); -extern int lcd_reg_gxb[]; -extern int lcd_reg_axg[]; + +extern unsigned int lcd_tcon_read(unsigned int _reg); +extern void lcd_tcon_write(unsigned int _reg, unsigned int _value); +extern void lcd_tcon_setb(unsigned int reg, unsigned int value, + unsigned int _start, unsigned int _len); +extern unsigned int lcd_tcon_getb(unsigned int reg, + unsigned int _start, unsigned int _len); +extern void lcd_tcon_set_mask(unsigned int reg, unsigned int _mask); +extern void lcd_tcon_clr_mask(unsigned int reg, unsigned int _mask); +extern unsigned char lcd_tcon_read_byte(unsigned int _reg); +extern void lcd_tcon_write_byte(unsigned int _reg, unsigned char _value); +extern void lcd_tcon_setb_byte(unsigned int reg, unsigned char value, + unsigned int _start, unsigned int _len); +extern unsigned char lcd_tcon_getb_byte(unsigned int reg, + unsigned int _start, unsigned int _len); #endif - diff --git a/drivers/amlogic/media/vout/lcd/lcd_tablet/lcd_drv.c b/drivers/amlogic/media/vout/lcd/lcd_tablet/lcd_drv.c index fada75b0c44e..d5d69bbde91a 100644 --- a/drivers/amlogic/media/vout/lcd/lcd_tablet/lcd_drv.c +++ b/drivers/amlogic/media/vout/lcd/lcd_tablet/lcd_drv.c @@ -342,6 +342,7 @@ static void lcd_venc_set(struct lcd_config_s *pconf) { unsigned int h_active, v_active; unsigned int video_on_pixel, video_on_line; + struct aml_lcd_drv_s *lcd_drv = aml_lcd_get_driver(); if (lcd_debug_print_flag) LCDPR("%s\n", __func__); @@ -371,6 +372,15 @@ static void lcd_venc_set(struct lcd_config_s *pconf) lcd_vcbus_write(ENCL_VIDEO_VSO_ELINE, pconf->lcd_timing.vs_ve_addr); lcd_vcbus_write(ENCL_VIDEO_RGBIN_CTRL, 3); + switch (lcd_drv->data->chip_type) { + case LCD_CHIP_TL1: + lcd_vcbus_write(ENCL_INBUF_CNTL1, (1 << 14) | (h_active - 1)); + lcd_vcbus_write(ENCL_INBUF_CNTL0, 0x200); + break; + default: + break; + } + /* default black pattern */ lcd_vcbus_write(ENCL_TST_MDSEL, 0); lcd_vcbus_write(ENCL_TST_Y, 0); diff --git a/drivers/amlogic/media/vout/lcd/lcd_tablet/lcd_tablet.c b/drivers/amlogic/media/vout/lcd/lcd_tablet/lcd_tablet.c index 856faa5e8c8b..50814cce5054 100644 --- a/drivers/amlogic/media/vout/lcd/lcd_tablet/lcd_tablet.c +++ b/drivers/amlogic/media/vout/lcd/lcd_tablet/lcd_tablet.c @@ -382,6 +382,7 @@ static struct vout_server_s lcd_vout_server = { .set_vframe_rate_end_hint = lcd_set_vframe_rate_end_hint, .set_vframe_rate_policy = lcd_set_vframe_rate_policy, .get_vframe_rate_policy = lcd_get_vframe_rate_policy, + .set_bist = lcd_debug_test, #ifdef CONFIG_PM .vout_suspend = lcd_suspend, .vout_resume = lcd_resume, @@ -405,6 +406,7 @@ static struct vout_server_s lcd_vout2_server = { .set_vframe_rate_end_hint = lcd_set_vframe_rate_end_hint, .set_vframe_rate_policy = lcd_set_vframe_rate_policy, .get_vframe_rate_policy = lcd_get_vframe_rate_policy, + .set_bist = lcd_debug_test, #ifdef CONFIG_PM .vout_suspend = lcd_suspend, .vout_resume = lcd_resume, @@ -1190,7 +1192,13 @@ static void lcd_config_init(struct lcd_config_s *pconf) lcd_tablet_config_update(pconf); lcd_clk_generate_parameter(pconf); ss_level = pconf->lcd_timing.ss_level; - cconf->ss_level = (ss_level >= cconf->ss_level_max) ? 0 : ss_level; + if (cconf->data) { + cconf->ss_level = (ss_level >= cconf->data->ss_level_max) ? + 0 : ss_level; + } else { + LCDERR("%s: clk config data is null\n", __func__); + cconf->ss_level = 0; + } lcd_tablet_config_post_update(pconf); } diff --git a/drivers/amlogic/media/vout/lcd/lcd_tablet/mipi_dsi_util.c b/drivers/amlogic/media/vout/lcd/lcd_tablet/mipi_dsi_util.c index 9f80de29e76d..b08e16a59bb1 100644 --- a/drivers/amlogic/media/vout/lcd/lcd_tablet/mipi_dsi_util.c +++ b/drivers/amlogic/media/vout/lcd/lcd_tablet/mipi_dsi_util.c @@ -1921,14 +1921,15 @@ void mipi_dsi_link_off(struct lcd_config_s *pconf) void lcd_mipi_dsi_config_set(struct lcd_config_s *pconf) { unsigned int pclk, bit_rate, lcd_bits; - unsigned int bit_rate_max, bit_rate_min, pll_out_fmin; + unsigned int bit_rate_max, bit_rate_min, pll_out_fmin = 0; struct dsi_config_s *dconf = pconf->lcd_control.mipi_config; struct lcd_clk_config_s *cConf = get_lcd_clk_config(); int n; unsigned int temp; /* unit in kHz for calculation */ - pll_out_fmin = cConf->pll_out_fmin; + if (cConf->data) + pll_out_fmin = cConf->data->pll_out_fmin; pclk = pconf->lcd_timing.lcd_clk / 1000; /* data format */ diff --git a/drivers/amlogic/media/vout/lcd/lcd_tcon.c b/drivers/amlogic/media/vout/lcd/lcd_tcon.c new file mode 100644 index 000000000000..b2e26713d24a --- /dev/null +++ b/drivers/amlogic/media/vout/lcd/lcd_tcon.c @@ -0,0 +1,623 @@ +/* + * drivers/amlogic/media/vout/lcd/lcd_tcon.c + * + * Copyright (C) 2017 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "lcd_common.h" +#include "lcd_reg.h" +#include "lcd_tcon.h" + +#define TCON_INTR_MASKN_VAL 0x0 /* default mask all */ + +static struct reserved_mem tcon_fb_rmem = {.base = 0, .size = 0}; + +static struct lcd_tcon_data_s *lcd_tcon_data; + +static int lcd_tcon_valid_check(void) +{ + if (lcd_tcon_data == NULL) { + LCDERR("invalid tcon data\n"); + return -1; + } + if (lcd_tcon_data->tcon_valid == 0) { + LCDERR("invalid tcon\n"); + return -1; + } + + return 0; +} + +static void lcd_tcon_od_check(unsigned char *table) +{ + unsigned int reg, bit; + + if (lcd_tcon_data->reg_core_od == REG_LCD_TCON_MAX) + return; + + reg = lcd_tcon_data->reg_core_od; + bit = lcd_tcon_data->bit_od_en; + if (((table[reg] >> bit) & 1) == 0) + return; + + if (lcd_tcon_data->axi_offset_addr == 0) { + table[reg] &= ~(1 << bit); + LCDPR("%s: invalid fb, disable od function\n", __func__); + } +} + +void lcd_tcon_core_reg_update(void) +{ + unsigned char *table; + unsigned int len, temp; + int i, ret; + + ret = lcd_tcon_valid_check(); + if (ret) + return; + + len = lcd_tcon_data->reg_table_len; + table = lcd_tcon_data->reg_table; + if (table == NULL) { + LCDERR("%s: table is NULL\n", __func__); + return; + } + lcd_tcon_od_check(table); + if (lcd_tcon_data->core_reg_width == 8) { + for (i = 0; i < len; i++) { + lcd_tcon_write_byte((i + TCON_CORE_REG_START), + table[i]); + } + } else { + for (i = 0; i < len; i++) + lcd_tcon_write((i + TCON_CORE_REG_START), table[i]); + } + LCDPR("tcon core regs update\n"); + + if (lcd_tcon_data->reg_core_od != REG_LCD_TCON_MAX) { + i = lcd_tcon_data->reg_core_od; + if (lcd_tcon_data->core_reg_width == 8) + temp = lcd_tcon_read_byte(i + TCON_CORE_REG_START); + else + temp = lcd_tcon_read(i + TCON_CORE_REG_START); + LCDPR("%s: tcon od reg readback: 0x%04x = 0x%04x\n", + __func__, i, temp); + } +} + +static int lcd_tcon_top_set_tl1(void) +{ + unsigned int axi_reg[3] = { + TCON_AXI_OFST0, TCON_AXI_OFST1, TCON_AXI_OFST2 + }; + unsigned int addr[3] = {0, 0, 0}; + unsigned int size[3] = {0, 0, 0}; + int i; + + LCDPR("lcd tcon top set\n"); + + if (lcd_tcon_data->axi_offset_addr == 0) { + LCDERR("%s: invalid axi_offset_addr\n", __func__); + } else { + addr[0] = lcd_tcon_data->axi_offset_addr; + addr[1] = addr[0] + size[0]; + addr[2] = addr[1] + size[1]; + for (i = 0; i < 3; i++) { + lcd_tcon_write(axi_reg[i], addr[i]); + LCDPR("set tcon axi_offset_addr[%d]: 0x%08x\n", + i, addr[i]); + } + } + + lcd_tcon_write(TCON_CLK_CTRL, 0x001f); + lcd_tcon_write(TCON_TOP_CTRL, 0x8999); + lcd_tcon_write(TCON_PLLLOCK_CNTL, 0x0037); + lcd_tcon_write(TCON_RST_CTRL, 0x003f); + lcd_tcon_write(TCON_RST_CTRL, 0x0000); + lcd_tcon_write(TCON_DDRIF_CTRL0, 0x33fff000); + lcd_tcon_write(TCON_DDRIF_CTRL1, 0x300300); + + return 0; +} + +static int lcd_tcon_enable_tl1(struct lcd_config_s *pconf) +{ + int ret; + + ret = lcd_tcon_valid_check(); + if (ret) + return -1; + + /* step 1: tcon top */ + lcd_tcon_top_set_tl1(); + + /* step 2: tcon_core_reg_update */ + lcd_tcon_core_reg_update(); + + /* step 3: tcon_top_output_set */ + lcd_tcon_write(TCON_OUT_CH_SEL1, 0xba98); /* out swap for ch8~11 */ + LCDPR("set tcon ch_sel: 0x%08x, 0x%08x\n", + lcd_tcon_read(TCON_OUT_CH_SEL0), + lcd_tcon_read(TCON_OUT_CH_SEL1)); + + /* step 4: tcon_intr_mask */ + lcd_tcon_write(TCON_INTR_MASKN, TCON_INTR_MASKN_VAL); + + return 0; +} + +static irqreturn_t lcd_tcon_isr(int irq, void *dev_id) +{ + struct aml_lcd_drv_s *lcd_drv = aml_lcd_get_driver(); + unsigned int temp; + + if ((lcd_drv->lcd_status & LCD_STATUS_IF_ON) == 0) + return IRQ_HANDLED; + + temp = lcd_tcon_read(TCON_INTR); + if (temp & 0x2) { + LCDPR("%s: tcon sw_reset triggered\n", __func__); + lcd_tcon_core_reg_update(); + } + if (temp & 0x40) + LCDPR("%s: tcon ddr interface error triggered\n", __func__); + + return IRQ_HANDLED; +} + +static void lcd_tcon_intr_init(struct aml_lcd_drv_s *lcd_drv) +{ + unsigned int tcon_irq = 0; + + if (!lcd_drv->res_tcon_irq) { + LCDERR("res_tcon_irq is null\n"); + return; + } + tcon_irq = lcd_drv->res_tcon_irq->start; + LCDPR("tcon_irq: %d\n", tcon_irq); + + if (request_irq(tcon_irq, lcd_tcon_isr, IRQF_SHARED, + "lcd_tcon", (void *)"lcd_tcon")) + LCDERR("can't request lcd_tcon irq\n"); + else { + LCDPR("request lcd_tcon successful\n"); + } + + lcd_tcon_write(TCON_INTR_MASKN, TCON_INTR_MASKN_VAL); +} + +static int lcd_tcon_config(struct aml_lcd_drv_s *lcd_drv) +{ + int key_len, reg_len, ret; + + /* init reserved memory */ + ret = of_reserved_mem_device_init(lcd_drv->dev); + if ((ret != 0) && ((void *)tcon_fb_rmem.base == NULL)) { + LCDERR("failed to init tcon axi reserved memory\n"); + } else { + lcd_tcon_data->axi_offset_addr = + virt_to_phys((void *)tcon_fb_rmem.base); + } + LCDPR("tcon axi_offset_addr = 0x%08x\n", + lcd_tcon_data->axi_offset_addr); + + /* get reg table from unifykey */ + reg_len = lcd_tcon_data->reg_table_len; + if (lcd_tcon_data->reg_table == NULL) { + lcd_tcon_data->reg_table = + kcalloc(reg_len, sizeof(unsigned char), GFP_KERNEL); + if (!lcd_tcon_data->reg_table) { + LCDERR("%s: Not enough memory\n", __func__); + return -1; + } + } + key_len = reg_len; + ret = lcd_unifykey_get_no_header("lcd_tcon", + lcd_tcon_data->reg_table, &key_len); + if (ret) { + kfree(lcd_tcon_data->reg_table); + lcd_tcon_data->reg_table = NULL; + LCDERR("%s: !!!!!!!!tcon unifykey load error!!!!!!!!\n", + __func__); + return -1; + } + if (key_len != reg_len) { + kfree(lcd_tcon_data->reg_table); + lcd_tcon_data->reg_table = NULL; + LCDERR("%s: !!!!!!!!tcon unifykey load length error!!!!!!!!\n", + __func__); + return -1; + } + LCDPR("tcon: load key len: %d\n", key_len); + + lcd_tcon_intr_init(lcd_drv); + + return 0; +} + +/* ********************************** + * tcon function api + * ********************************** + */ +#define PR_BUF_MAX 200 +void lcd_tcon_reg_table_print(void) +{ + int i, j, n, cnt; + char *buf; + int ret; + + ret = lcd_tcon_valid_check(); + if (ret) + return; + + if (lcd_tcon_data->reg_table == NULL) { + LCDERR("%s: reg_table is null\n", __func__); + return; + } + + buf = kcalloc(PR_BUF_MAX, sizeof(char), GFP_KERNEL); + if (buf == NULL) { + LCDERR("%s: buf malloc error\n", __func__); + return; + } + + LCDPR("%s:\n", __func__); + cnt = lcd_tcon_data->reg_table_len; + for (i = 0; i < cnt; i += 16) { + n = snprintf(buf, PR_BUF_MAX, "0x%04x: ", i); + for (j = 0; j < 16; j++) { + if ((i + j) >= cnt) + break; + n += snprintf(buf+n, PR_BUF_MAX, " 0x%02x", + lcd_tcon_data->reg_table[i+j]); + } + buf[n] = '\0'; + pr_info("%s\n", buf); + } + kfree(buf); +} + +void lcd_tcon_reg_readback_print(void) +{ + int i, j, n, cnt; + char *buf; + int ret; + + ret = lcd_tcon_valid_check(); + if (ret) + return; + + buf = kcalloc(PR_BUF_MAX, sizeof(char), GFP_KERNEL); + if (buf == NULL) { + LCDERR("%s: buf malloc error\n", __func__); + return; + } + + LCDPR("%s:\n", __func__); + cnt = lcd_tcon_data->reg_table_len; + for (i = 0; i < cnt; i += 16) { + n = snprintf(buf, PR_BUF_MAX, "0x%04x: ", i); + for (j = 0; j < 16; j++) { + if ((i + j) >= cnt) + break; + if (lcd_tcon_data->core_reg_width == 8) { + n += snprintf(buf+n, PR_BUF_MAX, " 0x%02x", + lcd_tcon_read_byte(i+j)); + } else { + n += snprintf(buf+n, PR_BUF_MAX, " 0x%02x", + lcd_tcon_read(i+j)); + } + } + buf[n] = '\0'; + pr_info("%s\n", buf); + } + kfree(buf); +} + +int lcd_tcon_info_print(char *buf, int offset) +{ + int len = 0, n, ret; + + ret = lcd_tcon_valid_check(); + if (ret) + return len; + + n = lcd_debug_info_len(len + offset); + len += snprintf((buf+len), n, + "tcon info:\n" + "core_reg_width: %d\n" + "reg_table_len: %d\n" + "axi_offset_addr: 0x%08x\n\n", + lcd_tcon_data->core_reg_width, + lcd_tcon_data->reg_table_len, + lcd_tcon_data->axi_offset_addr); + + return len; +} + +int lcd_tcon_reg_table_size_get(void) +{ + int ret; + + ret = lcd_tcon_valid_check(); + if (ret) + return -1; + + return lcd_tcon_data->reg_table_len; +} + +unsigned char *lcd_tcon_reg_table_get(void) +{ + int ret; + + ret = lcd_tcon_valid_check(); + if (ret) + return NULL; + + return lcd_tcon_data->reg_table; +} + +int lcd_tcon_core_reg_get(unsigned char *buf, unsigned int size) +{ + int i, ret; + + ret = lcd_tcon_valid_check(); + if (ret) + return -1; + + if (size > lcd_tcon_data->reg_table_len) { + LCDERR("%s: size is not enough\n", __func__); + return -1; + } + + if (lcd_tcon_data->core_reg_width == 8) { + for (i = 0; i < size; i++) + buf[i] = lcd_tcon_read_byte(i + TCON_CORE_REG_START); + } else { + for (i = 0; i < size; i++) + buf[i] = lcd_tcon_read(i + TCON_CORE_REG_START); + } + + return 0; +} + +int lcd_tcon_od_set(int flag) +{ + unsigned int reg, bit, temp; + int ret; + + ret = lcd_tcon_valid_check(); + if (ret) + return -1; + + if (lcd_tcon_data->reg_core_od == REG_LCD_TCON_MAX) { + LCDERR("%s: invalid od reg\n", __func__); + return -1; + } + + if (flag) { + if (lcd_tcon_data->axi_offset_addr == 0) { + LCDERR("%s: invalid fb, disable od function\n", + __func__); + return -1; + } + } + + reg = lcd_tcon_data->reg_core_od; + bit = lcd_tcon_data->bit_od_en; + if (lcd_tcon_data->core_reg_width == 8) + temp = lcd_tcon_read_byte(reg + TCON_CORE_REG_START); + else + temp = lcd_tcon_read(reg + TCON_CORE_REG_START); + if (flag) + temp |= (1 << bit); + else + temp &= ~(1 << bit); + temp &= 0xff; + if (lcd_tcon_data->core_reg_width == 8) + lcd_tcon_write_byte((reg + TCON_CORE_REG_START), temp); + else + lcd_tcon_write((reg + TCON_CORE_REG_START), temp); + + msleep(100); + LCDPR("%s: %d\n", __func__, flag); + + return 0; +} + +int lcd_tcon_od_get(void) +{ + unsigned int reg, bit, temp; + int ret = 0; + + ret = lcd_tcon_valid_check(); + if (ret) + return -1; + + if (lcd_tcon_data->reg_core_od == REG_LCD_TCON_MAX) { + LCDERR("%s: invalid od reg\n", __func__); + return -1; + } + + reg = lcd_tcon_data->reg_core_od; + bit = lcd_tcon_data->bit_od_en; + if (lcd_tcon_data->core_reg_width == 8) + temp = lcd_tcon_read_byte(reg + TCON_CORE_REG_START); + else + temp = lcd_tcon_read(reg + TCON_CORE_REG_START); + ret = ((temp >> bit) & 1); + + return ret; +} + +int lcd_tcon_enable(struct lcd_config_s *pconf) +{ + int ret; + + ret = lcd_tcon_valid_check(); + if (ret) + return -1; + + if (lcd_tcon_data->tcon_enable) + lcd_tcon_data->tcon_enable(pconf); + + return 0; +} + +#define TCON_CTRL_TIMING_OFFSET 12 +void lcd_tcon_disable(void) +{ + unsigned int reg, i, cnt, offset, bit; + int ret; + + ret = lcd_tcon_valid_check(); + if (ret) + return; + + LCDPR("%s\n", __func__); + + /* disable tcon intr */ + lcd_tcon_write(TCON_INTR_MASKN, 0); + + /* disable over_drive */ + if (lcd_tcon_data->reg_core_od != REG_LCD_TCON_MAX) { + reg = lcd_tcon_data->reg_core_od + TCON_CORE_REG_START; + if (lcd_tcon_data->core_reg_width == 8) + lcd_tcon_write_byte(reg, 0); + else + lcd_tcon_write(reg, 0); + msleep(100); + } + + /* disable all ctrl signal */ + if (lcd_tcon_data->reg_core_ctrl_timing_base == REG_LCD_TCON_MAX) + goto lcd_tcon_disable_next; + reg = lcd_tcon_data->reg_core_ctrl_timing_base + TCON_CORE_REG_START; + offset = lcd_tcon_data->ctrl_timing_offset; + cnt = lcd_tcon_data->ctrl_timing_cnt; + for (i = 0; i < cnt; i++) { + if (lcd_tcon_data->core_reg_width == 8) + lcd_tcon_setb_byte((reg + (i * offset)), 1, 3, 1); + else + lcd_tcon_setb((reg + (i * offset)), 1, 3, 1); + } + + /* disable top */ +lcd_tcon_disable_next: + if (lcd_tcon_data->reg_top_ctrl != REG_LCD_TCON_MAX) { + reg = lcd_tcon_data->reg_top_ctrl; + bit = lcd_tcon_data->bit_en; + lcd_tcon_setb(reg, 0, bit, 1); + } +} + +/* ********************************** + * tcon match data + * ********************************** + */ +static struct lcd_tcon_data_s tcon_data_tl1 = { + .tcon_valid = 0, + + .core_reg_width = LCD_TCON_CORE_REG_WIDTH_TL1, + .reg_table_len = LCD_TCON_TABLE_LEN_TL1, + + .reg_top_ctrl = TCON_TOP_CTRL, + .bit_en = BIT_TOP_EN_TL1, + + .reg_core_od = REG_LCD_TCON_MAX, + .bit_od_en = BIT_OD_EN_TL1, + + .reg_core_ctrl_timing_base = REG_CORE_CTRL_TIMING_BASE_TL1, + .ctrl_timing_offset = CTRL_TIMING_OFFSET_TL1, + .ctrl_timing_cnt = CTRL_TIMING_CNT_TL1, + + .axi_offset_addr = 0, + .reg_table = NULL, + + .tcon_enable = lcd_tcon_enable_tl1, +}; + +int lcd_tcon_probe(struct aml_lcd_drv_s *lcd_drv) +{ + int ret = 0; + + switch (lcd_drv->data->chip_type) { + case LCD_CHIP_TL1: + lcd_tcon_data = &tcon_data_tl1; + switch (lcd_drv->lcd_config->lcd_basic.lcd_type) { + case LCD_MLVDS: + case LCD_P2P: + lcd_tcon_data->tcon_valid = 1; + break; + default: + break; + } + break; + default: + lcd_tcon_data = NULL; + break; + } + ret = lcd_tcon_valid_check(); + if (ret) + return -1; + + ret = lcd_tcon_config(lcd_drv); + + return ret; +} + +static int rmem_tcon_fb_device_init(struct reserved_mem *rmem, + struct device *dev) +{ + return 0; +} + +static const struct reserved_mem_ops rmem_tcon_fb_ops = { + .device_init = rmem_tcon_fb_device_init, +}; + +static int __init rmem_tcon_fb_setup(struct reserved_mem *rmem) +{ + /* + * phys_addr_t align = PAGE_SIZE; + * phys_addr_t mask = align - 1; + * if ((rmem->base & mask) || (rmem->size & mask)) { + * LCDERR("Reserved memory: incorrect alignment of region\n"); + * return -EINVAL; + * } + */ + tcon_fb_rmem.base = rmem->base; + tcon_fb_rmem.size = rmem->size; + rmem->ops = &rmem_tcon_fb_ops; + LCDPR("tcon: Reserved memory: created fb at 0x%p, size %ld MiB\n", + (void *)rmem->base, (unsigned long)rmem->size / SZ_1M); + return 0; +} +RESERVEDMEM_OF_DECLARE(fb, "amlogic, lcd_tcon-memory", rmem_tcon_fb_setup); + diff --git a/drivers/amlogic/media/vout/lcd/lcd_tcon.h b/drivers/amlogic/media/vout/lcd/lcd_tcon.h new file mode 100644 index 000000000000..8f210e623767 --- /dev/null +++ b/drivers/amlogic/media/vout/lcd/lcd_tcon.h @@ -0,0 +1,63 @@ +/* + * drivers/amlogic/media/vout/lcd/lcd_tcon.h + * + * Copyright (C) 2017 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +#ifndef __AML_LCD_TCON_H__ +#define __AML_LCD_TCON_H__ +#include + +#define REG_LCD_TCON_MAX 0xffff + +struct lcd_tcon_data_s { + unsigned char tcon_valid; + + unsigned int core_reg_width; + unsigned int reg_table_len; + + unsigned int reg_top_ctrl; + unsigned int bit_en; + + unsigned int reg_core_od; + unsigned int bit_od_en; + + unsigned int reg_core_ctrl_timing_base; + unsigned int ctrl_timing_offset; + unsigned int ctrl_timing_cnt; + + unsigned int axi_offset_addr; + unsigned char *reg_table; + + int (*tcon_enable)(struct lcd_config_s *pconf); +}; + +/* ********************************** + * tcon config + * ********************************** + */ +/* TL1 */ +#define LCD_TCON_CORE_REG_WIDTH_TL1 8 +#define LCD_TCON_TABLE_LEN_TL1 24000 +#define LCD_TCON_AXI_BANK_TL1 3 + +#define BIT_TOP_EN_TL1 4 + +#define REG_CORE_OD_TL1 0x5c +#define BIT_OD_EN_TL1 6 +#define REG_CORE_CTRL_TIMING_BASE_TL1 0x1b +#define CTRL_TIMING_OFFSET_TL1 12 +#define CTRL_TIMING_CNT_TL1 0 + +#endif diff --git a/drivers/amlogic/media/vout/lcd/lcd_tcon_ref.h b/drivers/amlogic/media/vout/lcd/lcd_tcon_ref.h new file mode 100644 index 000000000000..fdf5398957a0 --- /dev/null +++ b/drivers/amlogic/media/vout/lcd/lcd_tcon_ref.h @@ -0,0 +1,40993 @@ +/* + * drivers/amlogic/media/vout/lcd/lcd_tcon_ref.h + * + * Copyright (C) 2017 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +#ifndef __LCD_TCON_REF_H__ +#define __LCD_TCON_REF_H__ + +static unsigned char tcon_boe_hd_hsd_n56[] = { + 0x40, + 0x44, + 0x44, + 0x44, + 0x44, + 0x00, + 0x00, + 0x00, + 0x00, + 0x44, + 0x44, + 0x44, + 0x40, + 0x00, + 0x00, + 0x00, + 0xE4, + 0x1B, + 0x00, + 0x00, + 0x0F, + 0xC8, + 0x00, + 0x11, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0xC0, + 0x6F, + 0x00, + 0x88, + 0x2B, + 0x00, + 0x10, + 0x32, + 0x54, + 0x76, + 0x90, + 0x06, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x07, + 0x80, + 0x03, + 0x28, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, /* 0x05c //0x00 --> 0x40 //[6]:od_en */ + 0x00, + 0x04, + 0x00, + 0x80, + 0x0F, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x03, + 0x80, + 0x08, + 0x10, + 0x09, + 0x20, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0xB4, + 0x33, + 0x00, + 0x3B, + 0x00, + 0x06, + 0x01, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0xE8, + 0x01, + 0x5A, + 0x00, + 0x2A, + 0xE8, + 0x00, + 0x02, + 0x00, + 0x02, + 0x3D, + 0xA3, + 0xC2, + 0x33, + 0x82, + 0xCA, + 0x28, + 0xC2, + 0x2D, + 0x22, + 0xB1, + 0xFB, + 0x1F, + 0xA1, + 0x56, + 0x11, + 0x90, + 0xBD, + 0x02, + 0xD0, + 0x14, + 0x00, + 0x20, + 0x56, + 0x55, + 0x6E, + 0xFF, + 0x3F, + 0x00, + 0x12, + 0xF3, + 0xC0, + 0x44, + 0x04, + 0x96, + 0xCC, + 0x01, + 0xFF, + 0x0A, + 0x0A, + 0x0A, + 0x0C, + 0x69, + 0x40, + 0x03, + 0x26, + 0x64, + 0x88, + 0x4C, + 0x00, + 0x11, + 0xC7, + 0x80, + 0x32, + 0x8E, + 0x88, + 0x00, + 0x0A, + 0x00, + 0x08, + 0x05, + 0xDC, + 0x03, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x0A, + 0x00, + 0x00, + 0x20, /* 0x113: 0x00 --> 0x20, bit[5] */ + 0xAB, + 0x42, + 0x00, + 0x00, + 0x00, + 0x01, + 0x0C, + 0x01, + 0x00, + 0x00, + 0xC0, + 0x03, + 0x1E, + 0x0C, + 0x20, + 0x00, + 0x88, + 0x08, + 0x00, + 0x64, + 0xC8, + 0x00, + 0x00, + 0x0A, + 0x20, + 0x00, + 0xCC, + 0x99, + 0x33, + 0x66, + 0x33, + 0x55, + 0xAA, + 0xBB, + 0x77, + 0x66, + 0x33, + 0x55, + 0xAA, + 0xBB, + 0x77, + 0x66, + 0x33, + 0x55, + 0xAA, + 0xBB, + 0x77, + 0x66, + 0x33, + 0x55, + 0xAA, + 0xBB, + 0x77, + 0x10, + 0x88, + 0x8F, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x08, + 0x10, + 0x18, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x30, + 0xE8, + 0xFC, + 0x03, + 0x21, + 0x49, + 0xFF, + 0xFF, + 0xFF, + 0x04, + 0x20, + 0xA0, + 0x86, + 0x01, + 0x03, + 0xA0, + 0x86, + 0x01, + 0xD4, + 0x38, + 0x34, + 0xC0, + 0x38, + 0x74, + 0x01, + 0xF9, + 0xC7, + 0x11, + 0xC7, + 0x73, + 0x3C, + 0x80, + 0xE0, + 0xC7, + 0x1E, + 0x38, + 0x6D, + 0x60, + 0x64, + 0xF9, + 0xC3, + 0x06, + 0x18, + 0x9C, + 0x40, + 0x80, + 0xE0, + 0xC7, + 0x1E, + 0x38, + 0x4A, + 0x38, + 0x64, + 0x2C, + 0x07, + 0x00, + 0x07, + 0x0B, + 0xB8, + 0x80, + 0x70, + 0x07, + 0x00, + 0x07, + 0x05, + 0x14, + 0x80, + 0x3E, + 0xCC, + 0xCC, + 0xCC, + 0xFD, + 0xE8, + 0x80, + 0x20, + 0x89, + 0x85, + 0x22, + 0x03, + 0xE8, + 0x80, + 0x04, + 0x50, + 0xFF, + 0x30, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x01, + 0x00, + 0x01, + 0xF0, + 0xFF, + 0x02, + 0x23, + 0x03, + 0x44, + 0x29, + 0x11, + 0x10, + 0x01, + 0x00, + 0x01, + 0xF0, + 0xFF, + 0xFA, + 0xA0, + 0x0F, + 0x20, + 0x00, + 0x00, + 0x00, + 0x01, + 0x00, + 0x02, + 0xF0, + 0xFF, + 0xBC, + 0xC2, + 0x30, + 0x40, + 0x01, + 0x14, + 0x40, + 0x01, + 0x00, + 0x02, + 0x30, + 0x00, + 0xBC, + 0xC2, + 0x2B, + 0x40, + 0x01, + 0x35, + 0x40, + 0x01, + 0x00, + 0x03, + 0x40, + 0x00, + 0x79, + 0xE2, + 0x19, + 0x00, + 0x00, + 0x00, + 0x00, + 0x01, + 0x00, + 0x05, + 0xF0, + 0xFF, + 0x79, + 0x02, + 0x23, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x01, + 0x00, + 0x02, + 0xF0, + 0xFF, + 0x79, + 0x02, + 0x23, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x70, + 0x50, + 0x31, + 0xF0, + 0xF0, + 0xF4, + 0x20, + 0x00, + 0x10, + 0xF0, + 0xF0, + 0xF0, + 0xF0, + 0xF0, + 0xF0, + 0xF0, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x10, + 0x02, + 0x10, + 0x10, + 0x10, + 0x10, + 0x10, + 0x10, + 0x04, + 0xAA, + 0x55, + 0x00, + 0x00, + 0x00, + 0x60, + 0x08, + 0x80, + 0x00, /* 0x2b1: 0x00 */ + 0x08, /* 0x2b2: 0x08 */ + 0x05, /* 0x2b3: 0x00 --> 0x05 */ + 0x58, /* 0x2b4: 0x08 --> 0x58 */ + 0x05, /* 0x2b5: 0x05 */ + 0x58, + 0x02, + 0x00, + 0x20, + 0x01, + 0x08, + 0x00, + 0x13, + 0x00, + 0x0C, + 0x0D, + 0xB7, + 0x03, + 0x94, + 0x18, + 0x00, + 0x10, + 0xF0, + 0x07, + 0x80, + 0x20, + 0x00, + 0x06, + 0x0B, + 0x0B, + 0x33, + 0x0E, + 0x1C, + 0x2A, + 0x38, + 0x46, + 0x54, + 0x62, + 0x69, + 0x70, + 0x77, + 0x79, + 0x7B, + 0x7D, + 0x7E, + 0x02, + 0x04, + 0x00, + 0x04, + 0x00, + 0x0D, + 0x3E, + 0x0E, + 0x3C, + 0x1F, + 0x3A, + 0x1F, + 0x38, + 0x1F, + 0x78, + 0x18, + 0x78, + 0x19, + 0x76, + 0x1A, + 0x76, + 0x1B, + 0x74, + 0x2C, + 0x74, + 0x2D, + 0x74, + 0x3D, + 0x74, + 0x6F, + 0x00, + 0x08, + 0x11, + 0x1A, + 0x23, + 0x2C, + 0x2D, + 0x3E, + 0x10, + 0x22, + 0x33, + 0x44, + 0x55, + 0x66, + 0x87, + 0x88, + 0x4F, + 0xA5, /* 0x30d: 0xa5 */ + 0xD7, /* 0x30e: 0x09 --> 0xd7 */ + 0x80, /* 0x30f: 0x60 --> 0x80 */ + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 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0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x24, + 0xD5, +};/*end of boe hd hsd n56*/ + +static unsigned char tcon_boe_fhd_goa_n10[] = { + 0x40, + 0x44, + 0x44, + 0x44, + 0x44, + 0x00, + 0x00, + 0x00, + 0x00, + 0x44, + 0x44, + 0x44, + 0x40, + 0x00, + 0x00, + 0x00, + 0xE4, + 0x1B, + 0x00, + 0x20, /* 0x013 //0x00 --> 0x20 */ + 0x0F, + 0xC8, + 0x00, + 0x11, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0xC0, + 0x6F, + 0x00, + 0x88, + 0x2B, + 0x00, + 0x10, + 0x32, + 0x54, + 0x76, + 0x90, + 0x06, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x07, + 0x80, + 0x03, + 0x28, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x40, /* 0x05c //0x00 --> 0x40 //[6]:od_en */ + 0x00, + 0x04, + 0x00, + 0x80, + 0x0F, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x03, + 0x80, + 0x08, + 0x10, + 0x09, + 0x20, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0xB4, + 0x33, + 0x00, + 0x3B, + 0x00, + 0x06, + 0x01, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0xE8, + 0x01, + 0x5A, + 0x00, + 0x2A, + 0xE8, + 0x00, + 0x02, + 0x00, + 0x02, + 0x3D, + 0xA3, + 0xC2, + 0x33, + 0x82, + 0xCA, + 0x28, + 0xC2, + 0x2D, + 0x22, + 0xB1, + 0xFB, + 0x1F, + 0xA1, + 0x56, + 0x11, + 0x90, + 0xBD, + 0x02, + 0xD0, + 0x14, + 0x00, + 0x20, + 0x80, + 0x77, + 0x98, + 0xFF, + 0x4F, + 0x38, + 0x3E, + 0xF4, + 0xC0, + 0x44, + 0x04, + 0x96, + 0xCC, + 0x01, + 0xFF, + 0x0A, + 0x0A, + 0x0A, + 0x0C, + 0x89, + 0x70, + 0x04, + 0x4C, + 0x64, + 0xC0, + 0x6C, + 0x68, + 0x21, + 0xD0, + 0x80, + 0x52, + 0x00, + 0x88, + 0x00, + 0x0A, + 0x00, + 0x08, + 0x05, + 0xDC, + 0x03, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x38, + 0x11, + 0x11, + 0x20, /* 0x113: 0x00 --> 0x20, bit[5] */ + 0x80, + 0x37, + 0x00, + 0x00, + 0x00, + 0x00, + 0x0C, + 0x01, + 0x10, + 0x3C, + 0x82, /* 0x11e //0xc0 --> 0x82 */ + 0x27, /* 0x11f //0x03 --> 0x27 */ + 0x3C, /* 0x120 //0x1e --> 0x3c */ + 0x0C, + 0x20, + 0x00, + 0x18, + 0x0F, /* 0x125 //0x0b --> 0x0f */ + 0x00, + 0x64, + 0xC8, + 0x00, + 0x00, + 0x0A, + 0x20, + 0x00, + 0xCC, + 0x99, + 0x33, + 0xCC, + 0xDD, + 0xEE, + 0xCC, + 0xDD, + 0xEE, + 0xCC, + 0xDD, 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= 0; break; default: @@ -165,6 +167,86 @@ static void lcd_lvds_phy_set(struct lcd_config_s *pconf, int status) } } +static void lcd_mlvds_phy_set(struct lcd_config_s *pconf, int status) +{ + unsigned int vswing, preem; + unsigned int data32; + + if (lcd_debug_print_flag) + LCDPR("%s: %d\n", __func__, status); + + if (status) { + vswing = pconf->lcd_control.mlvds_config->phy_vswing; + preem = pconf->lcd_control.mlvds_config->phy_preem; + if (vswing > 7) { + LCDERR("%s: wrong vswing_level=%d, use default\n", + __func__, vswing); + vswing = LVDS_PHY_VSWING_DFT; + } + if (preem > 3) { + LCDERR("%s: wrong preemphasis_level=%d, use default\n", + __func__, preem); + preem = LVDS_PHY_PREEM_DFT; + } + + data32 = MLVDS_PHY_CNTL1_TL1 | + (vswing << 3) | (vswing << 0) | (preem << 23); + lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL1, data32); + data32 = MLVDS_PHY_CNTL2_TL1 | + (preem << 14) | (preem << 12) | + (preem << 26) | (preem << 24); + lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL2, data32); + data32 = MLVDS_PHY_CNTL3_TL1 | + (preem << 6) | (preem << 4) | + (preem << 2) | (preem << 0) | (preem << 30); + lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL3, data32); + } else { + lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL1, 0x0); + lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL2, 0x0); + lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL3, 0x0); + } +} + +static void lcd_p2p_phy_set(struct lcd_config_s *pconf, int status) +{ + unsigned int vswing, preem; + unsigned int data32; + + if (lcd_debug_print_flag) + LCDPR("%s: %d\n", __func__, status); + + if (status) { + vswing = pconf->lcd_control.p2p_config->phy_vswing; + preem = pconf->lcd_control.p2p_config->phy_preem; + if (vswing > 7) { + LCDERR("%s: wrong vswing_level=%d, use default\n", + __func__, vswing); + vswing = LVDS_PHY_VSWING_DFT; + } + if (preem > 3) { + LCDERR("%s: wrong preemphasis_level=%d, use default\n", + __func__, preem); + preem = LVDS_PHY_PREEM_DFT; + } + + data32 = MLVDS_PHY_CNTL1_TL1 | + (vswing << 3) | (vswing << 0) | (preem << 23); + lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL1, data32); + data32 = MLVDS_PHY_CNTL2_TL1 | + (preem << 14) | (preem << 12) | + (preem << 26) | (preem << 24); + lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL2, data32); + data32 = MLVDS_PHY_CNTL3_TL1 | + (preem << 6) | (preem << 4) | + (preem << 2) | (preem << 0) | (preem << 30); + lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL3, data32); + } else { + lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL1, 0x0); + lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL2, 0x0); + lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL3, 0x0); + } +} + static void lcd_encl_tcon_set(struct lcd_config_s *pconf) { lcd_vcbus_write(L_RGB_BASE_ADDR, 0); @@ -209,6 +291,7 @@ static void lcd_venc_set(struct lcd_config_s *pconf) { unsigned int h_active, v_active; unsigned int video_on_pixel, video_on_line; + struct aml_lcd_drv_s *lcd_drv = aml_lcd_get_driver(); if (lcd_debug_print_flag) LCDPR("%s\n", __func__); @@ -245,6 +328,15 @@ static void lcd_venc_set(struct lcd_config_s *pconf) lcd_vcbus_write(ENCL_VIDEO_RGBIN_CTRL, 3); + switch (lcd_drv->data->chip_type) { + case LCD_CHIP_TL1: + lcd_vcbus_write(ENCL_INBUF_CNTL1, (1 << 14) | (h_active - 1)); + lcd_vcbus_write(ENCL_INBUF_CNTL0, 0x200); + break; + default: + break; + } + /* default black pattern */ lcd_vcbus_write(ENCL_TST_MDSEL, 0); lcd_vcbus_write(ENCL_TST_Y, 0); @@ -347,6 +439,89 @@ static void lcd_lvds_disable(void) lcd_vcbus_setb(LVDS_GEN_CNTL, 0, 3, 1); /* disable lvds fifo */ } +static void lcd_mlvds_clk_util_set(struct lcd_config_s *pconf) +{ + unsigned int lcd_bits, div_sel; + + lcd_bits = pconf->lcd_basic.lcd_bits; + + switch (lcd_bits) { + case 6: + div_sel = 0; + break; + case 8: + div_sel = 2; + break; + default: + div_sel = 2; + break; + } + + /* set fifo_clk_sel */ + lcd_hiu_write(HHI_LVDS_TX_PHY_CNTL0, (div_sel << 6)); + /* set cntl_ser_en: 8-channel to 1 */ + lcd_hiu_setb(HHI_LVDS_TX_PHY_CNTL0, 0xfff, 16, 12); + + /* decoupling fifo enable, gated clock enable */ + lcd_hiu_write(HHI_LVDS_TX_PHY_CNTL1, + (1 << 30) | (0 << 25) | (1 << 24)); + /* decoupling fifo write enable after fifo enable */ + lcd_hiu_setb(HHI_LVDS_TX_PHY_CNTL1, 1, 31, 1); +} + +static void lcd_mlvds_control_set(struct lcd_config_s *pconf) +{ + unsigned int bit_num = 1; + + if (lcd_debug_print_flag) + LCDPR("%s\n", __func__); + + lcd_mlvds_clk_util_set(pconf); + + switch (pconf->lcd_basic.lcd_bits) { + case 10: + bit_num = 0; + break; + case 8: + bit_num = 1; + break; + case 6: + bit_num = 2; + break; + case 4: + bit_num = 3; + break; + default: + bit_num = 1; + break; + } + + lcd_vcbus_write(LVDS_PACK_CNTL_ADDR, + (1 << 0) | // repack //[1:0] + (0 << 3) | // reserve + (0 << 4) | // lsb first + (0 << 5) | // pn swap + (1 << 6) | // dual port + (0 << 7) | // use tcon control + (bit_num << 8) | // 0:10bits, 1:8bits, 2:6bits, 3:4bits. + (0 << 10) | //r_select //0:R, 1:G, 2:B, 3:0 + (1 << 12) | //g_select //0:R, 1:G, 2:B, 3:0 + (2 << 14)); //b_select //0:R, 1:G, 2:B, 3:0; + + lcd_vcbus_write(LVDS_GEN_CNTL, + (lcd_vcbus_read(LVDS_GEN_CNTL) | (1 << 4) | (0x3 << 0))); + lcd_vcbus_setb(LVDS_GEN_CNTL, 1, 3, 1); + + lcd_tcon_enable(pconf); +} + +static void lcd_mlvds_disable(void) +{ + lcd_tcon_disable(); + + lcd_vcbus_setb(LVDS_GEN_CNTL, 0, 3, 1); /* disable lvds fifo */ +} + #if 0 static void lcd_vbyone_ctlbits(int p3d_en, int p3d_lr, int mode) { @@ -623,6 +798,8 @@ static void lcd_vbyone_control_set(struct lcd_config_s *pconf) static void lcd_vbyone_disable(void) { lcd_vcbus_setb(VBO_CTRL_L, 0, 0, 1); + lcd_vcbus_setb(VBO_INSGN_CTRL, 0, 2, 1); + lcd_vcbus_setb(VBO_INSGN_CTRL, 0, 0, 1); } #define VBYONE_INTR_UNMASK 0x2bff /* 0x2a00 */ @@ -1116,6 +1293,23 @@ static irqreturn_t lcd_vbyone_interrupt_handler(int irq, void *dev_id) return IRQ_HANDLED; } +static void lcd_p2p_control_set(struct lcd_config_s *pconf) +{ + if (lcd_debug_print_flag) + LCDPR("%s\n", __func__); + + lcd_vbyone_control_set(pconf); + + lcd_tcon_enable(pconf); +} + +static void lcd_p2p_disable(void) +{ + lcd_tcon_disable(); + + lcd_vbyone_disable(); +} + static unsigned int vbyone_lane_num[] = { 1, 2, @@ -1185,6 +1379,61 @@ static void lcd_vbyone_config_set(struct lcd_config_s *pconf) } } +static void lcd_mlvds_config_set(struct lcd_config_s *pconf) +{ + unsigned int bit_rate, pclk; + unsigned int lcd_bits, channel_num; + unsigned int channel_sel0, channel_sel1, pi_clk_sel; + unsigned int i, temp; + + if (lcd_debug_print_flag) + LCDPR("%s\n", __func__); + + lcd_bits = pconf->lcd_basic.lcd_bits; + channel_num = pconf->lcd_control.mlvds_config->channel_num; + pclk = pconf->lcd_timing.lcd_clk / 1000; + bit_rate = lcd_bits * 3 * pclk / channel_num; + + pconf->lcd_control.mlvds_config->bit_rate = bit_rate * 1000; + + if (lcd_debug_print_flag) { + LCDPR("channel_num=%u, bit_rate=%u.%03uMHz, pclk=%u.%03uMhz\n", + channel_num, (bit_rate / 1000), (bit_rate % 1000), + (pclk / 1000), (pclk % 1000)); + } + + /* pi_clk select */ + /* mlvds channel: //tx 10 channels + * 0: d0_a + * 1: d1_a + * 2: d2_a + * 3: clk_a + * 4: d0_b + * 5: d1_b + * 6: d2_b + * 7: clk_b + */ + channel_sel0 = pconf->lcd_control.mlvds_config->channel_sel0; + channel_sel1 = pconf->lcd_control.mlvds_config->channel_sel1; + pi_clk_sel = 0; + for (i = 0; i < 8; i++) { + temp = (channel_sel0 >> (i*4)) & 0xf; + if ((temp == 3) || (temp == 7)) + pi_clk_sel |= (1 << i); + } + for (i = 0; i < 2; i++) { + temp = (channel_sel1 >> (i*4)) & 0xf; + if ((temp == 3) || (temp == 7)) + pi_clk_sel |= (1 << (i + 8)); + } + pconf->lcd_control.mlvds_config->pi_clk_sel = pi_clk_sel; + if (lcd_debug_print_flag) { + LCDPR( + "channel_sel0=0x%08x, channel_sel1=0x%08x, pi_clk_sel=0x%03x\n", + channel_sel0, channel_sel1, pi_clk_sel); + } +} + void lcd_tv_clk_config_change(struct lcd_config_s *pconf) { #ifdef CONFIG_AMLOGIC_VPU @@ -1194,6 +1443,9 @@ void lcd_tv_clk_config_change(struct lcd_config_s *pconf) case LCD_VBYONE: lcd_vbyone_config_set(pconf); break; + case LCD_MLVDS: + lcd_mlvds_config_set(pconf); + break; default: break; } @@ -1231,6 +1483,9 @@ void lcd_tv_config_update(struct lcd_config_s *pconf) case LCD_VBYONE: lcd_vbyone_config_set(pconf); break; + case LCD_MLVDS: + lcd_mlvds_config_set(pconf); + break; default: break; } @@ -1321,6 +1576,16 @@ int lcd_tv_driver_init(void) msecs_to_jiffies(LCD_VX1_WAIT_STABLE_DELAY)); } break; + case LCD_MLVDS: + lcd_mlvds_control_set(pconf); + lcd_tcon_pinmux_set(1); + lcd_mlvds_phy_set(pconf, 1); + break; + case LCD_P2P: + lcd_p2p_control_set(pconf); + lcd_tcon_pinmux_set(1); + lcd_p2p_phy_set(pconf, 1); + break; default: break; } @@ -1356,6 +1621,16 @@ void lcd_tv_driver_disable(void) lcd_vbyone_pinmux_set(0); lcd_vbyone_disable(); break; + case LCD_MLVDS: + lcd_mlvds_disable(); + lcd_mlvds_phy_set(pconf, 0); + lcd_tcon_pinmux_set(0); + break; + case LCD_P2P: + lcd_p2p_disable(); + lcd_p2p_phy_set(pconf, 0); + lcd_tcon_pinmux_set(0); + break; default: break; } diff --git a/drivers/amlogic/media/vout/lcd/lcd_tv/lcd_tv.c b/drivers/amlogic/media/vout/lcd/lcd_tv/lcd_tv.c index f2e2ab6c5748..f309f02fadff 100644 --- a/drivers/amlogic/media/vout/lcd/lcd_tv/lcd_tv.c +++ b/drivers/amlogic/media/vout/lcd/lcd_tv/lcd_tv.c @@ -657,6 +657,7 @@ static struct vout_server_s lcd_vout_server = { .set_vframe_rate_end_hint = lcd_set_vframe_rate_end_hint, .set_vframe_rate_policy = lcd_set_vframe_rate_policy, .get_vframe_rate_policy = lcd_get_vframe_rate_policy, + .set_bist = lcd_debug_test, #ifdef CONFIG_PM .vout_suspend = lcd_suspend, .vout_resume = lcd_resume, @@ -1290,7 +1291,13 @@ static void lcd_config_init(struct lcd_config_s *pconf) lcd_tv_config_update(pconf); lcd_clk_generate_parameter(pconf); ss_level = pconf->lcd_timing.ss_level; - cconf->ss_level = (ss_level >= cconf->ss_level_max) ? 0 : ss_level; + if (cconf->data) { + cconf->ss_level = (ss_level >= cconf->data->ss_level_max) ? + 0 : ss_level; + } else { + LCDERR("%s: clk config data is null\n", __func__); + cconf->ss_level = 0; + } } static int lcd_get_config(struct lcd_config_s *pconf, struct device *dev) diff --git a/drivers/amlogic/media/vout/lcd/lcd_unifykey.c b/drivers/amlogic/media/vout/lcd/lcd_unifykey.c index 94389138bcd8..015c357bf3f8 100644 --- a/drivers/amlogic/media/vout/lcd/lcd_unifykey.c +++ b/drivers/amlogic/media/vout/lcd/lcd_unifykey.c @@ -204,6 +204,66 @@ int lcd_unifykey_get(char *key_name, unsigned char *buf, int *len) return 0; } +int lcd_unifykey_check_no_header(char *key_name) +{ + unsigned int key_exist, keypermit, key_len; + int ret; + + key_exist = 0; + key_len = 0; + ret = key_unify_query(get_ukdev(), key_name, &key_exist, &keypermit); + if (ret < 0) { + if (lcd_debug_print_flag) + LCDUKEYERR("%s query exist error\n", key_name); + return -1; + } + if (key_exist == 0) { + if (lcd_debug_print_flag) + LCDUKEYERR("%s is not exist\n", key_name); + return -1; + } + + ret = key_unify_size(get_ukdev(), key_name, &key_len); + if (ret < 0) { + LCDUKEYERR("%s query size error\n", key_name); + return -1; + } + if (key_len == 0) { + if (lcd_debug_print_flag) + LCDUKEY("%s size is zero\n", key_name); + return -1; + } + if (lcd_debug_print_flag) + LCDUKEY("%s size: %d\n", key_name, key_len); + + return 0; +} + +int lcd_unifykey_get_no_header(char *key_name, unsigned char *buf, int *len) +{ + int key_len; + int ret; + + key_len = 0; + ret = lcd_unifykey_check_no_header(key_name); + if (ret < 0) + return -1; + ret = key_unify_size(get_ukdev(), key_name, &key_len); + if (key_len > *len) { + LCDUKEYERR("%s size(%d) is bigger than buf_size(%d)\n", + key_name, key_len, *len); + return -1; + } + *len = key_len; + + ret = key_unify_read(get_ukdev(), key_name, buf, key_len, &key_len); + if (ret < 0) { + LCDUKEYERR("%s unify read error\n", key_name); + return -1; + } + return 0; +} + void lcd_unifykey_print(void) { unsigned char *buf; @@ -313,6 +373,18 @@ int lcd_unifykey_get(char *key_name, unsigned char *buf, int *len) return -1; } +int lcd_unifykey_check_no_header(char *key_name) +{ + LCDUKEYERR("Don't support unifykey\n"); + return -1; +} + +int lcd_unifykey_get_no_header(char *key_name, unsigned char *buf, int *len) +{ + LCDUKEYERR("Don't support unifykey\n"); + return -1; +} + void lcd_unifykey_print(void) { LCDUKEYERR("Don't support unifykey\n"); diff --git a/drivers/amlogic/media/vout/lcd/lcd_vout.c b/drivers/amlogic/media/vout/lcd/lcd_vout.c index e726f0eac730..14dce115d894 100644 --- a/drivers/amlogic/media/vout/lcd/lcd_vout.c +++ b/drivers/amlogic/media/vout/lcd/lcd_vout.c @@ -36,7 +36,6 @@ #ifdef CONFIG_OF #include #endif -#include #include #include #include @@ -966,7 +965,7 @@ static int lcd_mode_probe(struct device *dev) break; } - lcd_class_creat(); + lcd_debug_probe(); lcd_fops_create(); lcd_notifier_register(); @@ -1063,6 +1062,7 @@ static int lcd_config_probe(struct platform_device *pdev) lcd_driver->res_vsync_irq = NULL; lcd_driver->res_vsync2_irq = NULL; lcd_driver->res_vx1_irq = NULL; + lcd_driver->res_tcon_irq = NULL; /* lcd driver assign */ ret = of_property_read_string(lcd_driver->dev->of_node, "mode", &str); @@ -1129,6 +1129,12 @@ static int lcd_config_probe(struct platform_device *pdev) platform_get_resource(pdev, IORESOURCE_IRQ, 1); } } + ret = of_property_read_string_index(lcd_driver->dev->of_node, + "interrupt-names", 2, &str); + if (ret == 0) { + lcd_driver->res_tcon_irq = platform_get_resource(pdev, + IORESOURCE_IRQ, 2); + } lcd_driver->lcd_info = &lcd_vinfo; lcd_driver->lcd_config = &lcd_config_dft; @@ -1218,12 +1224,6 @@ static void lcd_vsync_irq_remove(void) #ifdef CONFIG_OF -static struct lcd_data_s lcd_data_gxtvbb = { - .chip_type = LCD_CHIP_GXTVBB, - .chip_name = "gxtvbb", - .reg_map_table = &lcd_reg_gxb[0], -}; - static struct lcd_data_s lcd_data_gxl = { .chip_type = LCD_CHIP_GXL, .chip_name = "gxl", @@ -1266,11 +1266,13 @@ static struct lcd_data_s lcd_data_g12b = { .reg_map_table = &lcd_reg_axg[0], }; +static struct lcd_data_s lcd_data_tl1 = { + .chip_type = LCD_CHIP_TL1, + .chip_name = "tl1", + .reg_map_table = &lcd_reg_tl1[0], +}; + static const struct of_device_id lcd_dt_match_table[] = { - { - .compatible = "amlogic, lcd-gxtvbb", - .data = &lcd_data_gxtvbb, - }, { .compatible = "amlogic, lcd-gxl", .data = &lcd_data_gxl, @@ -1299,6 +1301,10 @@ static const struct of_device_id lcd_dt_match_table[] = { .compatible = "amlogic, lcd-g12b", .data = &lcd_data_g12b, }, + { + .compatible = "amlogic, lcd-tl1", + .data = &lcd_data_tl1, + }, {}, }; #endif @@ -1390,7 +1396,7 @@ static int lcd_remove(struct platform_device *pdev) if (lcd_driver) { lcd_vsync_irq_remove(); lcd_fops_remove(); - lcd_class_remove(); + lcd_debug_remove(); lcd_config_remove(lcd_driver->dev); kfree(lcd_driver); diff --git a/drivers/amlogic/media/vout/vdac/vdac_dev.c b/drivers/amlogic/media/vout/vdac/vdac_dev.c index c1033807e1b6..5f50dc9d4a64 100644 --- a/drivers/amlogic/media/vout/vdac/vdac_dev.c +++ b/drivers/amlogic/media/vout/vdac/vdac_dev.c @@ -128,6 +128,10 @@ void ana_ref_cntl0_bit9(bool on, unsigned int module_sel) { bool enable = 0; + /*tl1:bandgap en, bc[7] default:0 opened*/ + if (s_vdac_data->cpu_id == VDAC_CPU_TL1) + return; + switch (module_sel & 0x1f) { case VDAC_MODULE_ATV_DEMOD: /* dtv demod */ if (on) @@ -368,6 +372,12 @@ void vdac_enable(bool on, unsigned int module_sel) mutex_lock(&vdac_mutex); switch (module_sel) { case VDAC_MODULE_ATV_DEMOD: /* atv demod */ + if ((on && (pri_flag & VDAC_MODULE_ATV_DEMOD)) + || (!on && !(pri_flag & VDAC_MODULE_ATV_DEMOD))) { + pr_info("%s: ATV DEMOD had done!:%d.\n", __func__, on); + break; + } + if (on) { ana_ref_cntl0_bit9(1, VDAC_MODULE_ATV_DEMOD); /*after txlx need reset bandgap after bit9 enabled*/ @@ -564,6 +574,11 @@ struct meson_vdac_data meson_g12ab_vdac_data = { .name = "meson-g12ab-vdac", }; +struct meson_vdac_data meson_tl1_vdac_data = { + .cpu_id = VDAC_CPU_TL1, + .name = "meson-tl1-vdac", +}; + static const struct of_device_id meson_vdac_dt_match[] = { { .compatible = "amlogic, vdac-gxtvbb", @@ -592,6 +607,9 @@ static const struct of_device_id meson_vdac_dt_match[] = { }, { .compatible = "amlogic, vdac-g12b", .data = &meson_g12ab_vdac_data, + }, { + .compatible = "amlogic, vdac-tl1", + .data = &meson_tl1_vdac_data, }, {}, }; @@ -673,6 +691,8 @@ static int __exit aml_vdac_remove(struct platform_device *pdev) static int amvdac_drv_suspend(struct platform_device *pdev, pm_message_t state) { + if (s_vdac_data->cpu_id == VDAC_CPU_TXL) + vdac_hiu_reg_write(HHI_VDAC_CNTL0, 0); pr_info("%s: suspend module\n", __func__); return 0; } diff --git a/drivers/amlogic/media/vout/vout_serve/vout2_notify.c b/drivers/amlogic/media/vout/vout_serve/vout2_notify.c index 2cf1a60d5ef1..029d06a1b9ba 100644 --- a/drivers/amlogic/media/vout/vout_serve/vout2_notify.c +++ b/drivers/amlogic/media/vout/vout_serve/vout2_notify.c @@ -174,6 +174,15 @@ int get_vframe2_rate_policy(void) } EXPORT_SYMBOL(get_vframe2_rate_policy); +/* + * interface export to client who want to set test bist. + */ +void set_vout2_bist(unsigned int bist) +{ + vout_func_set_test_bist(2, bist); +} +EXPORT_SYMBOL(set_vout2_bist); + int vout2_suspend(void) { return vout_func_vout_suspend(2); diff --git a/drivers/amlogic/media/vout/vout_serve/vout2_serve.c b/drivers/amlogic/media/vout/vout_serve/vout2_serve.c index 9fa358279603..64d874700dbc 100644 --- a/drivers/amlogic/media/vout/vout_serve/vout2_serve.c +++ b/drivers/amlogic/media/vout/vout_serve/vout2_serve.c @@ -59,6 +59,7 @@ static struct class *vout2_class; static DEFINE_MUTEX(vout2_serve_mutex); static char vout2_mode[VMODE_NAME_LEN_MAX]; static char local_name[VMODE_NAME_LEN_MAX] = {0}; +static unsigned int bist_mode2; static char vout2_axis[64]; @@ -156,6 +157,7 @@ static struct vout_server_s nulldisp_vout2_server = { .set_state = nulldisp_vout_set_state, .clr_state = nulldisp_vout_clr_state, .get_state = nulldisp_vout_get_state, + .set_bist = NULL, }, }; @@ -355,6 +357,36 @@ static ssize_t vout2_fr_policy_store(struct class *class, return count; } +static ssize_t vout2_bist_show(struct class *class, + struct class_attribute *attr, char *buf) +{ + int ret = 0; + + ret = sprintf(buf, "%d\n", bist_mode2); + + return ret; +} + +static ssize_t vout2_bist_store(struct class *class, + struct class_attribute *attr, const char *buf, size_t count) +{ + int ret = 0; + + mutex_lock(&vout2_serve_mutex); + + ret = kstrtouint(buf, 10, &bist_mode2); + if (ret) { + pr_info("%s: invalid data\n", __func__); + mutex_unlock(&vout2_serve_mutex); + return -EINVAL; + } + set_vout2_bist(bist_mode2); + + mutex_unlock(&vout2_serve_mutex); + + return count; +} + static ssize_t vout2_vinfo_show(struct class *class, struct class_attribute *attr, char *buf) { @@ -448,6 +480,7 @@ static struct class_attribute vout2_class_attrs[] = { __ATTR(axis, 0644, vout2_axis_show, vout2_axis_store), __ATTR(fr_policy, 0644, vout2_fr_policy_show, vout2_fr_policy_store), + __ATTR(bist, 0644, vout2_bist_show, vout2_bist_store), __ATTR(vinfo, 0444, vout2_vinfo_show, NULL), }; diff --git a/drivers/amlogic/media/vout/vout_serve/vout_func.c b/drivers/amlogic/media/vout/vout_serve/vout_func.c index 747cde4473a3..c8661b355196 100644 --- a/drivers/amlogic/media/vout/vout_serve/vout_func.c +++ b/drivers/amlogic/media/vout/vout_serve/vout_func.c @@ -440,6 +440,31 @@ int vout_func_get_vframe_rate_policy(int index) } EXPORT_SYMBOL(vout_func_get_vframe_rate_policy); +/* + * interface export to client who want to set test bist. + */ +void vout_func_set_test_bist(int index, unsigned int bist) +{ + struct vout_server_s *p_server = NULL; + + mutex_lock(&vout_mutex); + + if (index == 1) + p_server = vout_module.curr_vout_server; +#ifdef CONFIG_AMLOGIC_VOUT2_SERVE + else if (index == 2) + p_server = vout2_module.curr_vout_server; +#endif + + if (!IS_ERR_OR_NULL(p_server)) { + if (p_server->op.set_bist) + p_server->op.set_bist(bist); + } + + mutex_unlock(&vout_mutex); +} +EXPORT_SYMBOL(vout_func_set_test_bist); + int vout_func_vout_suspend(int index) { int ret = 0; diff --git a/drivers/amlogic/media/vout/vout_serve/vout_func.h b/drivers/amlogic/media/vout/vout_serve/vout_func.h index 811685dfe32e..524f1e7635f9 100644 --- a/drivers/amlogic/media/vout/vout_serve/vout_func.h +++ b/drivers/amlogic/media/vout/vout_serve/vout_func.h @@ -64,6 +64,7 @@ extern int vout_func_set_vframe_rate_hint(int index, int duration); extern int vout_func_set_vframe_rate_end_hint(int index); extern int vout_func_set_vframe_rate_policy(int index, int policy); extern int vout_func_get_vframe_rate_policy(int index); +extern void vout_func_set_test_bist(int index, unsigned int bist); extern int vout_func_vout_suspend(int index); extern int vout_func_vout_resume(int index); extern int vout_func_vout_shutdown(int index); diff --git a/drivers/amlogic/media/vout/vout_serve/vout_notify.c b/drivers/amlogic/media/vout/vout_serve/vout_notify.c index ab5995c931da..3e2a5f33c1f8 100644 --- a/drivers/amlogic/media/vout/vout_serve/vout_notify.c +++ b/drivers/amlogic/media/vout/vout_serve/vout_notify.c @@ -192,6 +192,15 @@ int get_vframe_rate_policy(void) } EXPORT_SYMBOL(get_vframe_rate_policy); +/* + * interface export to client who want to set test bist. + */ +void set_vout_bist(unsigned int bist) +{ + vout_func_set_test_bist(1, bist); +} +EXPORT_SYMBOL(set_vout_bist); + #ifdef CONFIG_SCREEN_ON_EARLY static int wake_up_flag; void wakeup_early_suspend_proc(void) diff --git a/drivers/amlogic/media/vout/vout_serve/vout_serve.c b/drivers/amlogic/media/vout/vout_serve/vout_serve.c index 9821a41aeab2..6390f3bff1af 100644 --- a/drivers/amlogic/media/vout/vout_serve/vout_serve.c +++ b/drivers/amlogic/media/vout/vout_serve/vout_serve.c @@ -63,6 +63,7 @@ static char vout_mode[VMODE_NAME_LEN_MAX] __nosavedata; static char local_name[VMODE_NAME_LEN_MAX] = {0}; static u32 vout_init_vmode = VMODE_INIT_NULL; static int uboot_display; +static unsigned int bist_mode; static char vout_axis[64] __nosavedata; @@ -204,6 +205,7 @@ static struct vout_server_s nulldisp_vout_server = { .set_state = nulldisp_vout_set_state, .clr_state = nulldisp_vout_clr_state, .get_state = nulldisp_vout_get_state, + .set_bist = NULL, }, }; @@ -429,6 +431,36 @@ static ssize_t vout_fr_policy_store(struct class *class, return count; } +static ssize_t vout_bist_show(struct class *class, + struct class_attribute *attr, char *buf) +{ + int ret = 0; + + ret = sprintf(buf, "%d\n", bist_mode); + + return ret; +} + +static ssize_t vout_bist_store(struct class *class, + struct class_attribute *attr, const char *buf, size_t count) +{ + int ret = 0; + + mutex_lock(&vout_serve_mutex); + + ret = kstrtouint(buf, 10, &bist_mode); + if (ret) { + pr_info("%s: invalid data\n", __func__); + mutex_unlock(&vout_serve_mutex); + return -EINVAL; + } + set_vout_bist(bist_mode); + + mutex_unlock(&vout_serve_mutex); + + return count; +} + static ssize_t vout_vinfo_show(struct class *class, struct class_attribute *attr, char *buf) { @@ -523,6 +555,7 @@ static struct class_attribute vout_class_attrs[] = { __ATTR(axis, 0644, vout_axis_show, vout_axis_store), __ATTR(fr_policy, 0644, vout_fr_policy_show, vout_fr_policy_store), + __ATTR(bist, 0644, vout_bist_show, vout_bist_store), __ATTR(vinfo, 0444, vout_vinfo_show, NULL), }; diff --git a/drivers/amlogic/memory_ext/ram_dump.c b/drivers/amlogic/memory_ext/ram_dump.c index 5f242c11209f..3634ad4fb818 100644 --- a/drivers/amlogic/memory_ext/ram_dump.c +++ b/drivers/amlogic/memory_ext/ram_dump.c @@ -31,6 +31,7 @@ #include #include #include +#include #include static unsigned long ramdump_base __initdata; @@ -38,7 +39,7 @@ static unsigned long ramdump_size __initdata; static bool ramdump_disable __initdata; struct ramdump { - void __iomem *mem_base; + unsigned long mem_base; unsigned long mem_size; struct mutex lock; struct kobject *kobj; @@ -95,14 +96,28 @@ static ssize_t ramdump_bin_read(struct file *filp, struct kobject *kobj, char *buf, loff_t off, size_t count) { void *p = NULL; +#ifndef CONFIG_64BIT + struct page *page, *pages[1]; +#endif if (!ram->mem_base || off >= ram->mem_size) return 0; +#ifndef CONFIG_64BIT + page = phys_to_page(ram->mem_base + off); + pages[0] = page; + p = vmap(pages, 1, VM_MAP, PAGE_KERNEL); + if (!p) { + pr_info("%s, map %lx, %d failed, page:%p, pfn:%lx\n", + __func__, (unsigned long)(ram->mem_base + off), + count, page, page_to_pfn(page)); + return -EINVAL; + } +#else + p = (void *)(ram->mem_base + off); +#endif if (off + count > ram->mem_size) count = ram->mem_size - off; - - p = ram->mem_base + off; mutex_lock(&ram->lock); memcpy(buf, p, count); mutex_unlock(&ram->lock); @@ -111,7 +126,9 @@ static ssize_t ramdump_bin_read(struct file *filp, struct kobject *kobj, if (off + count >= ram->mem_size) pr_info("%s, p=%p %p, off:%lli, c:%zi\n", __func__, buf, p, off, count); - +#ifndef CONFIG_64BIT + vunmap(p); +#endif return count; } @@ -128,6 +145,9 @@ static ssize_t ramdump_bin_write(struct file *filp, struct bin_attribute *bin_attr, char *buf, loff_t off, size_t count) { + if (!ram->mem_size) + return -EINVAL; + if (ram->mem_base && !strncmp("reboot", buf, 6)) kernel_restart("RAM-DUMP finished\n"); @@ -261,7 +281,7 @@ void ramdump_sync_data(void) static int __init ramdump_probe(struct platform_device *pdev) { - void __iomem *p; + void __iomem *p = NULL; ram = kzalloc(sizeof(struct ramdump), GFP_KERNEL); if (!ram) @@ -274,9 +294,14 @@ static int __init ramdump_probe(struct platform_device *pdev) pr_info("NO valid ramdump args:%lx %lx\n", ramdump_base, ramdump_size); } else { + #ifdef CONFIG_64BIT p = ioremap_cache(ramdump_base, ramdump_size); - ram->mem_base = p; + ram->mem_base = (unsigned long)p; ram->mem_size = ramdump_size; + #else + ram->mem_base = ramdump_base; + ram->mem_size = ramdump_size; + #endif pr_info("%s, mem_base:%p, %lx, size:%lx\n", __func__, p, ramdump_base, ramdump_size); } @@ -300,8 +325,9 @@ static int __init ramdump_probe(struct platform_device *pdev) err1: kobject_put(ram->kobj); err: - if (ram->mem_base) - iounmap(ram->mem_base); +#ifdef CONFIG_64BIT + iounmap((void *)ram->mem_base); +#endif kfree(ram); return -EINVAL; @@ -310,7 +336,9 @@ err: static int ramdump_remove(struct platform_device *pdev) { sysfs_remove_bin_file(ram->kobj, &ramdump_attr); - iounmap(ram->mem_base); +#ifdef CONFIG_64BIT + iounmap((void *)ram->mem_base); +#endif kobject_put(ram->kobj); kfree(ram); return 0; diff --git a/drivers/amlogic/mmc/aml_sd_emmc.c b/drivers/amlogic/mmc/aml_sd_emmc.c index 4e6e17864ad8..5145c91ce64b 100644 --- a/drivers/amlogic/mmc/aml_sd_emmc.c +++ b/drivers/amlogic/mmc/aml_sd_emmc.c @@ -1148,6 +1148,7 @@ void aml_sd_emmc_save_host_val(struct mmc_host *mmc) { u32 adj, dly1, dly2, intf3; u32 vconf = 0, vclkc = 0; + struct sd_emmc_clock_v3 *clkc = (struct sd_emmc_clock_v3 *)&(vclkc); struct sd_emmc_config *pconf = (struct sd_emmc_config *)&vconf; struct amlsd_platform *pdata = mmc_priv(mmc); struct amlsd_host *host = pdata->host; @@ -1166,6 +1167,7 @@ void aml_sd_emmc_save_host_val(struct mmc_host *mmc) && (pconf->stop_clk == pdata->stop_clk) && (mmc->actual_clock == clk_ios) && (vclkc == pdata->clkc) + && (clkc->irq_sdio_sleep == pdata->irq_sdio_sleep) && (adj == pdata->adj) && (dly1 == pdata->dly1) && (dly2 == pdata->dly2) @@ -1179,6 +1181,7 @@ void aml_sd_emmc_save_host_val(struct mmc_host *mmc) pconf->bl_len = pdata->bl_len; pconf->stop_clk = pdata->stop_clk; vclkc = pdata->clkc; + clkc->irq_sdio_sleep = pdata->irq_sdio_sleep; adj = pdata->adj; dly1 = pdata->dly1; dly2 = pdata->dly2; @@ -1378,6 +1381,8 @@ static int meson_mmc_clk_init(struct amlsd_host *host) u32 vconf = 0; struct sd_emmc_config *pconf = (struct sd_emmc_config *)&vconf; + writel(0, host->base + SD_EMMC_ADJUST); + writel(0, host->base + SD_EMMC_DELAY); writel(0, host->base + SD_EMMC_CLOCK); ret = aml_emmc_clktree_init(host); if (ret) @@ -1915,7 +1920,7 @@ static void aml_sd_emmc_enable_sdio_irq(struct mmc_host *mmc, int enable) pclock->irq_sdio_sleep_ds = 0; writel(vclkc, host->base + SD_EMMC_CLOCK); } - pdata->clkc = vclkc; + pdata->irq_sdio_sleep = 1; if (enable) spin_unlock_irqrestore(&host->mrq_lock, flags); @@ -1952,6 +1957,7 @@ int meson_mmc_request_done(struct mmc_host *mmc, struct mmc_request *mrq) if (sdio_host) { if (pdata->xfer_pre) pdata->xfer_pre(mmc_priv(sdio_host)); + aml_sd_emmc_save_host_val(sdio_host); virqc = readl(host->base + SD_EMMC_IRQ_EN); if (irqc->irq_sdio != host->sdio_irqen) aml_sd_emmc_enable_sdio_irq(sdio_host, @@ -2611,9 +2617,9 @@ static irqreturn_t meson_mmc_irq(int irq, void *dev_id) pr_err("%s: warning... data crc, vstat:0x%x, virqc:%x", mmc_hostname(host->mmc), vstat, virqc); - pr_err("@ cmd %d with %p; stop %d, status %d\n", - mrq->cmd->opcode, mrq->data, - host->cmd_is_stop, + pr_err("@ cmd %d arg %x with %p; stop %d, status %d\n", + mrq->cmd->opcode, mrq->cmd->arg, + mrq->data, host->cmd_is_stop, host->status); } } else if (ista->desc_err) { @@ -2961,6 +2967,8 @@ static int aml_sd_emmc_card_busy(struct mmc_host *mmc) struct sd_emmc_status *ista = (struct sd_emmc_status *)&vstat; u32 vconf; struct sd_emmc_config *pconf = (struct sd_emmc_config *)&vconf; + u32 virqc = 0; + struct sd_emmc_irq_en *irqc = (struct sd_emmc_irq_en *)&virqc; if ((host->mem->start == host->data->port_b_base) && host->data->tdma_f @@ -2983,6 +2991,21 @@ static int aml_sd_emmc_card_busy(struct mmc_host *mmc) && host->data->tdma_f) host->init_volt = 0; } + + if ((host->mem->start == host->data->port_b_base) + && host->data->tdma_f + && strcmp(host->pinctrl_name, "sdio_")) { + if (sdio_host) { + if (pdata->xfer_pre) + pdata->xfer_pre(mmc_priv(sdio_host)); + aml_sd_emmc_save_host_val(sdio_host); + virqc = readl(host->base + SD_EMMC_IRQ_EN); + if (irqc->irq_sdio != host->sdio_irqen) + aml_sd_emmc_enable_sdio_irq(sdio_host, + host->sdio_irqen); + } + } + if ((host->mem->start == host->data->port_b_base) && host->data->tdma_f && (host->init_volt == 0)) diff --git a/drivers/amlogic/mmc/aml_sd_emmc_v3.c b/drivers/amlogic/mmc/aml_sd_emmc_v3.c index 8aa8e6824a7e..a5e4b2a5dfee 100644 --- a/drivers/amlogic/mmc/aml_sd_emmc_v3.c +++ b/drivers/amlogic/mmc/aml_sd_emmc_v3.c @@ -45,10 +45,11 @@ int aml_fixdiv_calc(unsigned int *fixdiv, struct clock_lay_t *clk) { int ret = 0; - unsigned int full_div, source_cycle; /* in ns*/ - unsigned int sdclk_idx, todly_idx_max, todly_idx_min; - unsigned int inv_idx_min, inv_idx_max; - unsigned int val_idx_min, val_idx_max, val_idx_win, val_idx_sta; + unsigned int full_div = 0, source_cycle = 0; /* in ns*/ + unsigned int sdclk_idx = 0, todly_idx_max = 0, todly_idx_min = 0; + unsigned int inv_idx_min = 0, inv_idx_max = 0; + unsigned int val_idx_min = 0, val_idx_max = 0; + unsigned int val_idx_win = 0, val_idx_sta = 0; if (!fixdiv || !clk) return -EPERM; @@ -115,8 +116,10 @@ int meson_mmc_clk_init_v3(struct amlsd_host *host) u32 vconf = 0; struct sd_emmc_config *pconf = (struct sd_emmc_config *)&vconf; struct mmc_phase *init = &(host->data->sdmmc.init); - struct mmc_phase *calc = &(host->data->sdmmc.calc); + writel(0, host->base + SD_EMMC_ADJUST_V3); + writel(0, host->base + SD_EMMC_DELAY1_V3); + writel(0, host->base + SD_EMMC_DELAY2_V3); writel(0, host->base + SD_EMMC_CLOCK_V3); #ifndef SD_EMMC_CLK_CTRL ret = aml_emmc_clktree_init(host); @@ -130,10 +133,6 @@ int meson_mmc_clk_init_v3(struct amlsd_host *host) pclkc->core_phase = init->core_phase; /* 2: 180 phase */ pclkc->rx_phase = init->rx_phase; pclkc->tx_phase = init->tx_phase; - if (host->data->chip_type >= MMC_CHIP_G12A) { - pclkc->core_phase = calc->core_phase; - pclkc->tx_phase = calc->tx_phase; - } pclkc->always_on = 1; /* Keep clock always on */ writel(vclkc, host->base + SD_EMMC_CLOCK_V3); @@ -216,7 +215,7 @@ static int meson_mmc_clk_set_rate_v3(struct mmc_host *mmc, #else if (clk_ios == mmc->actual_clock) { pr_debug("[%s] clk_ios: %lu, return .............. clock: 0x%x\n", - __func__, clk_ios, + pdata->pinname, clk_ios, readl(host->base + SD_EMMC_CLOCK_V3)); return 0; } @@ -259,13 +258,13 @@ static int meson_mmc_clk_set_rate_v3(struct mmc_host *mmc, } else mmc->actual_clock = clk_ios; - vclkc = readl(host->base + SD_EMMC_CLOCK_V3); - pdata->clk_lay.source = clk_get_rate(host->cfg_div_clk) * clkc->div; - pdata->clk_lay.core = clk_get_rate(host->cfg_div_clk); - - /* (re)start clock, if non-zero */ if (clk_ios) { + vclkc = readl(host->base + SD_EMMC_CLOCK_V3); + pdata->clk_lay.source + = clk_get_rate(host->cfg_div_clk) * clkc->div; + pdata->clk_lay.core = clk_get_rate(host->cfg_div_clk); + vcfg = readl(host->base + SD_EMMC_CFG); conf->stop_clk = 0; writel(vcfg, host->base + SD_EMMC_CFG); @@ -291,7 +290,7 @@ static void aml_sd_emmc_set_timing_v3(struct amlsd_platform *pdata, struct sd_emmc_config *ctrl = (struct sd_emmc_config *)&vctrl; u32 vclkc = readl(host->base + SD_EMMC_CLOCK_V3); struct sd_emmc_clock_v3 *clkc = (struct sd_emmc_clock_v3 *)&vclkc; - u32 adjust; + u32 adjust = 0; struct sd_emmc_adjust_v3 *gadjust = (struct sd_emmc_adjust_v3 *)&adjust; u8 clk_div = 0; struct para_e *para = &(host->data->sdmmc); @@ -334,7 +333,7 @@ static void aml_sd_emmc_set_timing_v3(struct amlsd_platform *pdata, /* overide co-phase by dts */ if (pdata->co_phase) clkc->core_phase = pdata->co_phase; - if (host->data->chip_type >= MMC_CHIP_G12A) { + if (pdata->calc_f) { clkc->core_phase = para->calc.core_phase; clkc->tx_phase = para->calc.tx_phase; } @@ -344,17 +343,23 @@ static void aml_sd_emmc_set_timing_v3(struct amlsd_platform *pdata, } else if (timing == MMC_TIMING_SD_HS) { if (aml_card_type_non_sdio(pdata)) clkc->core_phase = para->sd_hs.core_phase; - if (host->data->chip_type >= MMC_CHIP_G12A) { + if (pdata->calc_f) { clkc->core_phase = para->calc.core_phase; clkc->tx_phase = para->calc.tx_phase; } } else if (timing == MMC_TIMING_UHS_SDR104) { clkc->core_phase = para->sdr104.core_phase; clkc->tx_phase = para->sdr104.tx_phase; - } else + } else { ctrl->ddr = 0; + /* timing == MMC_TIMING_LEGACY */ + if (pdata->calc_f) { + clkc->core_phase = para->calc.core_phase; + clkc->tx_phase = para->calc.tx_phase; + } + } - if (host->data->chip_type >= MMC_CHIP_G12A) { + if (pdata->calc_f) { if (timing <= MMC_TIMING_SD_HS) { ret = aml_fixdiv_calc(&fixdiv, &pdata->clk_lay); if (!ret) { @@ -918,7 +923,7 @@ static unsigned int get_emmc_cmd_win(struct mmc_host *mmc) cur_size = -1; } delay2 &= ~(0x3f << 24); - delay2 |= ((best_start + best_size / 2) << 24); + delay2 |= ((best_start + best_size / 4) << 24); writel(delay2, host->base + SD_EMMC_DELAY2_V3); emmc_eyetest_log(mmc, 9); return max; diff --git a/drivers/amlogic/mmc/amlsd.c b/drivers/amlogic/mmc/amlsd.c index 83c98fa858d4..eea5ccf78985 100644 --- a/drivers/amlogic/mmc/amlsd.c +++ b/drivers/amlogic/mmc/amlsd.c @@ -948,10 +948,6 @@ static int meson_cd_op(void *data) struct amlsd_host *host = pdata->host; int ret = 0; - if ((host->mem->start == host->data->port_b_base) - && host->data->tdma_f) - wait_for_completion(&host->drv_completion); - mutex_lock(&pdata->in_out_lock); if (card_dealed == 1) { card_dealed = 0; @@ -975,10 +971,6 @@ static int meson_cd_op(void *data) card_dealed = 0; - if ((host->mem->start == host->data->port_b_base) - && host->data->tdma_f) - complete(&host->drv_completion); - return 0; } @@ -986,8 +978,13 @@ void meson_mmc_cd_detect(struct work_struct *work) { struct amlsd_platform *pdata = container_of( work, struct amlsd_platform, cd_detect.work); + struct amlsd_host *host = pdata->host; int i = 0, ret = 0; + if ((host->mem->start == host->data->port_b_base) + && host->data->tdma_f) + wait_for_completion(&host->drv_completion); + for (i = 0; i < 5; i++) { ret = gpio_get_value(pdata->gpio_cd); if (pdata->gpio_cd_sta != ret) @@ -996,6 +993,10 @@ void meson_mmc_cd_detect(struct work_struct *work) mdelay(1); } schedule_delayed_work(&pdata->cd_detect, 50); + + if ((host->mem->start == host->data->port_b_base) + && host->data->tdma_f) + complete(&host->drv_completion); } #endif diff --git a/drivers/amlogic/mmc/amlsd_of.c b/drivers/amlogic/mmc/amlsd_of.c index 9e4bee0fae8f..0f943790cf40 100644 --- a/drivers/amlogic/mmc/amlsd_of.c +++ b/drivers/amlogic/mmc/amlsd_of.c @@ -167,6 +167,8 @@ int amlsd_get_platform_data(struct platform_device *pdev, prop, pdata->power_level); SD_PARSE_GPIO_NUM_PROP(child, "gpio_power", str, pdata->gpio_power); + SD_PARSE_U32_PROP_DEC(child, "calc_f", + prop, pdata->calc_f); SD_PARSE_U32_PROP_DEC(child, "gpio_cd_level", prop, pdata->gpio_cd_level); diff --git a/drivers/amlogic/pinctrl/pinctrl-meson-g12a.c b/drivers/amlogic/pinctrl/pinctrl-meson-g12a.c index 1f6841909cfe..177550ada304 100644 --- a/drivers/amlogic/pinctrl/pinctrl-meson-g12a.c +++ b/drivers/amlogic/pinctrl/pinctrl-meson-g12a.c @@ -311,18 +311,18 @@ static const unsigned int jtag_b_tdi_pins[] = {GPIOC_1}; static const unsigned int jtag_b_clk_pins[] = {GPIOC_4}; static const unsigned int jtag_b_tms_pins[] = {GPIOC_5}; -/* bt565 */ -static const unsigned int bt565_a_vs_pins[] = {GPIOZ_0}; -static const unsigned int bt565_a_hs_pins[] = {GPIOZ_1}; -static const unsigned int bt565_a_clk_pins[] = {GPIOZ_3}; -static const unsigned int bt565_a_din0_pins[] = {GPIOZ_4}; -static const unsigned int bt565_a_din1_pins[] = {GPIOZ_5}; -static const unsigned int bt565_a_din2_pins[] = {GPIOZ_6}; -static const unsigned int bt565_a_din3_pins[] = {GPIOZ_7}; -static const unsigned int bt565_a_din4_pins[] = {GPIOZ_8}; -static const unsigned int bt565_a_din5_pins[] = {GPIOZ_9}; -static const unsigned int bt565_a_din6_pins[] = {GPIOZ_10}; -static const unsigned int bt565_a_din7_pins[] = {GPIOZ_11}; +/* bt656 */ +static const unsigned int bt656_a_vs_pins[] = {GPIOZ_0}; +static const unsigned int bt656_a_hs_pins[] = {GPIOZ_1}; +static const unsigned int bt656_a_clk_pins[] = {GPIOZ_3}; +static const unsigned int bt656_a_din0_pins[] = {GPIOZ_4}; +static const unsigned int bt656_a_din1_pins[] = {GPIOZ_5}; +static const unsigned int bt656_a_din2_pins[] = {GPIOZ_6}; +static const unsigned int bt656_a_din3_pins[] = {GPIOZ_7}; +static const unsigned int bt656_a_din4_pins[] = {GPIOZ_8}; +static const unsigned int bt656_a_din5_pins[] = {GPIOZ_9}; +static const unsigned int bt656_a_din6_pins[] = {GPIOZ_10}; +static const unsigned int bt656_a_din7_pins[] = {GPIOZ_11}; /* tsin_a */ static const unsigned int tsin_a_valid_pins[] = {GPIOX_2}; @@ -630,17 +630,17 @@ static struct meson_pmx_group meson_g12a_periphs_groups[] = { GROUP(eth_txd3_rgmii, 1), GROUP(eth_link_led, 1), GROUP(eth_act_led, 1), - GROUP(bt565_a_vs, 2), - GROUP(bt565_a_hs, 2), - GROUP(bt565_a_clk, 2), - GROUP(bt565_a_din0, 2), - GROUP(bt565_a_din1, 2), - GROUP(bt565_a_din2, 2), - GROUP(bt565_a_din3, 2), - GROUP(bt565_a_din4, 2), - GROUP(bt565_a_din5, 2), - GROUP(bt565_a_din6, 2), - GROUP(bt565_a_din7, 2), + GROUP(bt656_a_vs, 2), + GROUP(bt656_a_hs, 2), + GROUP(bt656_a_clk, 2), + GROUP(bt656_a_din0, 2), + GROUP(bt656_a_din1, 2), + GROUP(bt656_a_din2, 2), + GROUP(bt656_a_din3, 2), + GROUP(bt656_a_din4, 2), + GROUP(bt656_a_din5, 2), + GROUP(bt656_a_din6, 2), + GROUP(bt656_a_din7, 2), GROUP(tsin_b_valid_z, 3), GROUP(tsin_b_sop_z, 3), GROUP(tsin_b_din0_z, 3), @@ -1166,11 +1166,11 @@ static const char * const jtag_b_groups[] = { "jtag_b_tdi", "jtag_b_tdo", "jtag_b_clk", "jtag_b_tms", }; -static const char * const bt565_groups[] = { - "bt565_a_vs", "bt565_a_hs", "bt565_a_clk", - "bt565_a_din0", "bt565_a_din1", "bt565_a_din2", - "bt565_a_din3", "bt565_a_din4", "bt565_a_din5", - "bt565_a_din6", "bt565_a_din7", +static const char * const bt656_groups[] = { + "bt656_a_vs", "bt656_a_hs", "bt656_a_clk", + "bt656_a_din0", "bt656_a_din1", "bt656_a_din2", + "bt656_a_din3", "bt656_a_din4", "bt656_a_din5", + "bt656_a_din6", "bt656_a_din7", }; static const char * const tsin_a_groups[] = { @@ -1378,7 +1378,7 @@ static struct meson_pmx_func meson_g12a_periphs_functions[] = { FUNCTION(pwm_f), FUNCTION(cec_ao_ee), FUNCTION(jtag_b), - FUNCTION(bt565), + FUNCTION(bt656), FUNCTION(tsin_a), FUNCTION(tsin_b), FUNCTION(hdmitx), diff --git a/drivers/amlogic/pinctrl/pinctrl-meson.c b/drivers/amlogic/pinctrl/pinctrl-meson.c index a44eae5b5046..8f1afde33a2b 100644 --- a/drivers/amlogic/pinctrl/pinctrl-meson.c +++ b/drivers/amlogic/pinctrl/pinctrl-meson.c @@ -257,6 +257,7 @@ int meson_pinconf_common_set(struct meson_pinctrl *pc, unsigned int pin, BIT(bit), arg ? BIT(bit) : 0); if (ret) return ret; + break; default: return -ENOTSUPP; } @@ -654,6 +655,9 @@ static int meson_pinctrl_parse_dt(struct meson_pinctrl *pc, pc->of_irq = of_find_compatible_node(NULL, NULL, "amlogic,meson-gpio-intc"); + if (!pc->of_irq) + pc->of_irq = of_find_compatible_node(NULL, + NULL, "amlogic,meson-gpio-intc-ext"); pc->reg_mux = meson_map_resource(pc, gpio_np, "mux"); if (IS_ERR(pc->reg_mux)) { diff --git a/drivers/amlogic/pm/gx_pm.c b/drivers/amlogic/pm/gx_pm.c index d012ff1ba8ce..8228001d15b3 100644 --- a/drivers/amlogic/pm/gx_pm.c +++ b/drivers/amlogic/pm/gx_pm.c @@ -41,6 +41,7 @@ #include #include #include <../kernel/power/power.h> +#include typedef unsigned long (psci_fn)(unsigned long, unsigned long, unsigned long, unsigned long); @@ -157,6 +158,8 @@ ssize_t suspend_reason_show(struct device *dev, struct device_attribute *attr, { unsigned int len; + if (scpi_get_wakeup_reason(&suspend_reason)) + return -EPERM; len = sprintf(buf, "%d\n", suspend_reason); return len; diff --git a/drivers/amlogic/reboot/reboot.c b/drivers/amlogic/reboot/reboot.c index 4a1cc9bee42c..6e5cd09ad035 100644 --- a/drivers/amlogic/reboot/reboot.c +++ b/drivers/amlogic/reboot/reboot.c @@ -61,6 +61,14 @@ static u32 parse_reason(const char *cmd) reboot_reason = MESON_CRASH_REBOOT; else if (strcmp(cmd, "uboot_suspend") == 0) reboot_reason = MESON_UBOOT_SUSPEND; + else if (strcmp(cmd, "quiescent") == 0 || + strcmp(cmd, ",quiescent") == 0) + reboot_reason = MESON_QUIESCENT_REBOOT; + else if (strcmp(cmd, "recovery,quiescent") == 0 || + strcmp(cmd, "factory_reset,quiescent") == 0 || + strcmp(cmd, "quiescent,recovery") == 0 || + strcmp(cmd, "quiescent,factory_reset") == 0) + reboot_reason = MESON_RECOVERY_QUIESCENT_REBOOT; } else { if (kernel_panic) { if (strcmp(kernel_panic, "kernel_panic") == 0) { diff --git a/drivers/amlogic/secmon/secmon.c b/drivers/amlogic/secmon/secmon.c index 1eb31cb3da19..624c8e3472ec 100644 --- a/drivers/amlogic/secmon/secmon.c +++ b/drivers/amlogic/secmon/secmon.c @@ -26,6 +26,7 @@ #include #include #include +#include #include #undef pr_fmt #define pr_fmt(fmt) "secmon: " fmt @@ -61,6 +62,7 @@ static int secmon_probe(struct platform_device *pdev) int ret; int mem_size; struct page *page; + unsigned int clear[2] = {}; if (!of_property_read_u32(np, "in_base_func", &id)) phy_in_base = get_sharemem_info(id); @@ -80,6 +82,11 @@ static int secmon_probe(struct platform_device *pdev) return ret; } + if (of_property_read_u32_array(np, "clear_range", clear, 2)) + pr_info("can't fine clear_range\n"); + else + pr_info("clear_range:%x %x\n", clear[0], clear[1]); + page = dma_alloc_from_contiguous(&pdev->dev, mem_size >> PAGE_SHIFT, 0); if (!page) { pr_err("alloc page failed, ret:%p\n", page); @@ -97,6 +104,13 @@ static int secmon_probe(struct platform_device *pdev) return -ENOMEM; } + if (clear[0]) { + struct page *page = phys_to_page(clear[0]); + int cnt = clear[1] / PAGE_SIZE; + + cma_mmu_op(page, cnt, 0); + } + if (pfn_valid(__phys_to_pfn(phy_out_base))) sharemem_out_base = (void __iomem *) __phys_to_virt(phy_out_base); diff --git a/drivers/amlogic/smartcard/smartcard.c b/drivers/amlogic/smartcard/smartcard.c index 8330b97a5cbf..789ba650effa 100644 --- a/drivers/amlogic/smartcard/smartcard.c +++ b/drivers/amlogic/smartcard/smartcard.c @@ -339,7 +339,7 @@ struct smc_dev { #define SMC_ENABLE_5V3V_PIN_NAME "smc:5V3V" int enable_5v3v_level; int (*reset)(void*, int); - u32 irq_num; + int irq_num; int reset_level; u32 pin_clk_pinmux_reg; @@ -1847,8 +1847,12 @@ static int smc_dev_init(struct smc_dev *smc, int id) if (IS_ERR(smc->pinctrl)) return -1; - of_property_read_string(smc->pdev->dev.of_node, + ret = of_property_read_string(smc->pdev->dev.of_node, "smc_need_enable_pin", &dts_str); + if (ret < 0) { + pr_error("failed to get smartcard node.\n"); + return -EINVAL; + } if (strcmp(dts_str, "yes") == 0) smc->use_enable_pin = 1; else diff --git a/drivers/amlogic/spicc/spicc.c b/drivers/amlogic/spicc/spicc.c index 1fcd997eeb5b..e72023a2408b 100644 --- a/drivers/amlogic/spicc/spicc.c +++ b/drivers/amlogic/spicc/spicc.c @@ -401,9 +401,11 @@ static void dma_one_burst(struct spicc *spicc) setb(mem_base, DMA_NUM_WR_BURST, threshold - 1); setb(mem_base, DMA_RX_FIFO_TH, threshold - 1); } - setb(mem_base, CON_XCH, 1); spicc->remain -= bl; spicc->burst_len = bl; + if (spicc->irq) + enable_irq(spicc->irq); + setb(mem_base, CON_XCH, 1); } } @@ -470,8 +472,10 @@ static void pio_one_burst_send(struct spicc *spicc) spicc_set_txfifo(spicc, dat); } setb(mem_base, CON_BURST_LEN, spicc->burst_len - 1); - setb(mem_base, CON_XCH, 1); spicc->remain -= spicc->burst_len; + if (spicc->irq) + enable_irq(spicc->irq); + setb(mem_base, CON_XCH, 1); } } @@ -501,6 +505,7 @@ static irqreturn_t spicc_xfer_complete_isr(int irq, void *dev_id) unsigned long flags; spin_lock_irqsave(&spicc->lock, flags); + disable_irq_nosync(spicc->irq); spicc_wait_complete(spicc, 100); spicc_log(spicc, &spicc->remain, 1, XFER_COMP_ISR); if (!spicc_get_flag(spicc, FLAG_DMA_EN)) @@ -583,11 +588,9 @@ static int spicc_dma_xfer(struct spicc *spicc, struct spi_transfer *t) spicc_log(spicc, &spicc->remain, 1, DMA_BEGIN); if (spicc->irq) { setb(mem_base, INT_XFER_COM_EN, 1); - enable_irq(spicc->irq); dma_one_burst(spicc); ret = wait_for_completion_interruptible_timeout( &spicc->completion, msecs_to_jiffies(2000)); - disable_irq_nosync(spicc->irq); setb(mem_base, INT_XFER_COM_EN, 0); } else { while (spicc->remain) { @@ -624,11 +627,9 @@ static int spicc_hw_xfer(struct spicc *spicc, u8 *txp, u8 *rxp, int len) spicc_log(spicc, &spicc->remain, 1, PIO_BEGIN); if (spicc->irq) { setb(mem_base, INT_XFER_COM_EN, 1); - enable_irq(spicc->irq); pio_one_burst_send(spicc); ret = wait_for_completion_interruptible_timeout( &spicc->completion, msecs_to_jiffies(2000)); - disable_irq_nosync(spicc->irq); setb(mem_base, INT_XFER_COM_EN, 0); } else { while (spicc->remain) { diff --git a/drivers/amlogic/thermal/meson_cooldev.c b/drivers/amlogic/thermal/meson_cooldev.c index 9cabd879060a..db2c9e474f2d 100644 --- a/drivers/amlogic/thermal/meson_cooldev.c +++ b/drivers/amlogic/thermal/meson_cooldev.c @@ -397,7 +397,7 @@ static int meson_cooldev_probe(struct platform_device *pdev) } for_each_possible_cpu(cpu) { - if (mc_capable()) + if (topology_physical_package_id(0) != -1) c_id = topology_physical_package_id(cpu); else c_id = CLUSTER_BIG; /* Always cluster 0 if no mc */ diff --git a/drivers/amlogic/thermal/meson_tsensor.c b/drivers/amlogic/thermal/meson_tsensor.c index ff5d8c0e2413..18699834ccd0 100644 --- a/drivers/amlogic/thermal/meson_tsensor.c +++ b/drivers/amlogic/thermal/meson_tsensor.c @@ -160,6 +160,12 @@ static void meson_report_trigger(struct meson_tsensor_data *p) pr_err("No thermal zone device defined\n"); return; } + /* + *if passive delay and polling delay all is zero + *mean thermal mode disabled, disable update envent + */ + if (0 == (tz->passive_delay || tz->polling_delay)) + return; thermal_zone_device_update(tz, THERMAL_EVENT_UNSPECIFIED); diff --git a/drivers/amlogic/usb/phy/phy-aml-new-usb2-v2.c b/drivers/amlogic/usb/phy/phy-aml-new-usb2-v2.c index 6cc8d0140a0f..46a42249dd14 100644 --- a/drivers/amlogic/usb/phy/phy-aml-new-usb2-v2.c +++ b/drivers/amlogic/usb/phy/phy-aml-new-usb2-v2.c @@ -30,6 +30,7 @@ #include "phy-aml-new-usb-v2.h" struct amlogic_usb_v2 *g_phy2_v2; +#define TUNING_DISCONNECT_THRESHOLD 0x34 void set_usb_phy_host_tuning(int port, int default_val) { @@ -97,6 +98,8 @@ void set_usb_pll(struct amlogic_usb_v2 *phy, void __iomem *reg) /* Recovery analog status */ writel(0, reg + 0x38); writel(phy->pll_setting[5], reg + 0x34); + + writel(TUNING_DISCONNECT_THRESHOLD, reg + 0xC); } static int amlogic_new_usb2_init(struct usb_phy *x) diff --git a/drivers/amlogic/vrtc/aml_vrtc.c b/drivers/amlogic/vrtc/aml_vrtc.c index 063cb4eaddbd..1f102f36fbcd 100644 --- a/drivers/amlogic/vrtc/aml_vrtc.c +++ b/drivers/amlogic/vrtc/aml_vrtc.c @@ -188,8 +188,12 @@ static int aml_vrtc_probe(struct platform_device *pdev) if (!ret) { pr_debug("init_date: %s\n", str); if (!scpi_get_vrtc(&vrtc_val)) { - vrtc_init_date = vrtc_val; - pr_debug("get vrtc: %us\n", vrtc_init_date); + if (!vrtc_val) + parse_init_date(str); + else { + vrtc_init_date = vrtc_val; + pr_debug("get vrtc: %us\n", vrtc_init_date); + } } else parse_init_date(str); } diff --git a/drivers/base/dma-contiguous.c b/drivers/base/dma-contiguous.c index 0085c212fa2f..5fae0197a16a 100644 --- a/drivers/base/dma-contiguous.c +++ b/drivers/base/dma-contiguous.c @@ -268,6 +268,10 @@ static int __init rmem_cma_setup(struct reserved_mem *rmem) } /* Architecture specific contiguous memory fixup. */ dma_contiguous_early_fixup(rmem->base, rmem->size); +#ifdef CONFIG_AMLOGIC_CMA + if (of_get_flat_dt_prop(node, "clear-map", NULL)) + cma_init_clear(cma, 1); +#endif if (of_get_flat_dt_prop(node, "linux,cma-default", NULL)) dma_contiguous_set_default(cma); diff --git a/drivers/media/tuners/Kconfig b/drivers/media/tuners/Kconfig index 05998f0254c6..c1053922b7db 100644 --- a/drivers/media/tuners/Kconfig +++ b/drivers/media/tuners/Kconfig @@ -49,6 +49,13 @@ config MEDIA_TUNER_TDA18271 help A silicon tuner module. Say Y when you want to support this tuner. +config MEDIA_TUNER_TDA18272 + tristate "NXP TDA18272 silicon tuner" + depends on MEDIA_SUPPORT && I2C + default m if !MEDIA_SUBDRV_AUTOSELECT + help + A silicon tuner module. Say Y when you want to support this tuner. + config MEDIA_TUNER_TDA9887 tristate "TDA 9885/6/7 analog IF demodulator" depends on MEDIA_SUPPORT && I2C diff --git a/drivers/media/tuners/Makefile b/drivers/media/tuners/Makefile index 06a9ab65e5fa..3dd7a0494aff 100644 --- a/drivers/media/tuners/Makefile +++ b/drivers/media/tuners/Makefile @@ -15,6 +15,7 @@ obj-$(CONFIG_MEDIA_TUNER_TEA5761) += tea5761.o obj-$(CONFIG_MEDIA_TUNER_TDA9887) += tda9887.o obj-$(CONFIG_MEDIA_TUNER_TDA827X) += tda827x.o obj-$(CONFIG_MEDIA_TUNER_TDA18271) += tda18271.o +obj-$(CONFIG_MEDIA_TUNER_TDA18272) += tda18272.o obj-$(CONFIG_MEDIA_TUNER_XC5000) += xc5000.o obj-$(CONFIG_MEDIA_TUNER_XC4000) += xc4000.o obj-$(CONFIG_MEDIA_TUNER_MSI001) += msi001.o diff --git a/drivers/media/tuners/tda18272.c b/drivers/media/tuners/tda18272.c new file mode 100644 index 000000000000..0db00211963b --- /dev/null +++ b/drivers/media/tuners/tda18272.c @@ -0,0 +1,1598 @@ +/* + TDA18272 Silicon tuner driver + Copyright (C) Manu Abraham + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include + +#include "dvb_frontend.h" + +#include "tda18272.h" +#include "tda18272_reg.h" + +static unsigned int verbose; +module_param(verbose, int, 0644); +MODULE_PARM_DESC(verbose, "Set Verbosity level"); + +#define FE_ERROR 0 +#define FE_NOTICE 1 +#define FE_INFO 2 +#define FE_DEBUG 3 +#define FE_DEBUGREG 4 + +#define dprintk(__y, __z, format, arg...) do { \ + if (__z) { \ + if ((verbose > FE_ERROR) && (verbose > __y)) \ + printk(KERN_ERR "%s: " format "\n", __func__, ##arg); \ + else if ((verbose > FE_NOTICE) && (verbose > __y)) \ + printk(KERN_NOTICE "%s: " format "\n", __func__, ##arg); \ + else if ((verbose > FE_INFO) && (verbose > __y)) \ + printk(KERN_INFO "%s: " format "\n", __func__, ##arg); \ + else if ((verbose > FE_DEBUG) && (verbose > __y)) \ + printk(KERN_DEBUG "%s: " format "\n", __func__, ##arg); \ + } else { \ + if (verbose > __y) \ + printk(format, ##arg); \ + } \ +} while (0) + +#define TDA18272_SETFIELD(mask, bitf, val) \ + (mask = (mask & (~(((1 << TDA18272_WIDTH_##bitf) - 1) << \ + TDA18272_OFFST_##bitf))) | \ + (val << TDA18272_OFFST_##bitf)) + +#define TDA18272_GETFIELD(bitf, val) \ + ((val >> TDA18272_OFFST_##bitf) & \ + ((1 << TDA18272_WIDTH_##bitf) - 1)) + + +enum tda18272_lpf { + TDA18272_LPF_6MHz = 0, + TDA18272_LPF_7MHz, + TDA18272_LPF_8MHz, + TDA18272_LPF_9MHz, + TDA18272_LPF_1_5MHz +}; + +enum tda18272_lpf_offset { + TDA18272_LPFOFFSET_0PC = 0, + TDA18272_LPFOFFSET_4PC, + TDA18272_LPFOFFSET_8PC, + TDA18272_LPFOFFSET_12PC +}; + +enum tda18272_agcgain { + TDA18272_AGCGAIN_2VPP = 0, + TDA18272_AGCGAIN_1_25VPP, + TDA18272_AGCGAIN_1VPP, + TDA18272_AGCGAIN_0_8VPP, + TDA18272_AGCGAIN_0_85VPP, + TDA18272_AGCGAIN_0_7VPP, + TDA18272_AGCGAIN_0_6VPP, + TDA18272_AGCGAIN_0_5VPP +}; + +enum tda18272_notch { + TDA18272_NOTCH_DISABLED = 0, + TDA18272_NOTCH_ENABLED, +}; + +enum tda18272_hpf { + TDA18272_HPF_DISABLED = 0, + TDA18272_HPF_0_4MHz, + TDA18272_HPF_0_85MHz, + TDA18272_HPF_1MHz, + TDA18272_HPF_1_5Mhz +}; + +enum tda18272_lnatop { + TDA18272_LNATOP_95_89 = 0, + TDA18272_LNATOP_95_93, /* unused */ + TDA18272_LNATOP_95_94, /* unused */ + TDA18272_LNATOP_95_95, /* unused */ + TDA18272_LNATOP_99_89, + TDA18272_LNATOP_99_93, + TDA18272_LNATOP_99_94, + TDA18272_LNATOP_99_95, + TDA18272_LNATOP_99_95s, + TDA18272_LNATOP_100_93, + TDA18272_LNATOP_100_94, + TDA18272_LNATOP_100_95, + TDA18272_LNATOP_100_95s, + TDA18272_LNATOP_101_93d, + TDA18272_LNATOP_101_94d, + TDA18272_LNATOP_101_95, + TDA18272_LNATOP_101_95s, +}; + +enum tda18272_rfatttop { + TDA18272_RFATTTOP_89_81 = 0, + TDA18272_RFATTTOP_91_83, + TDA18272_RFATTTOP_93_85, + TDA18272_RFATTTOP_95_87, + TDA18272_RFATTTOP_88_88, + TDA18272_RFATTTOP_89_82, + TDA18272_RFATTTOP_90_83, + TDA18272_RFATTTOP_91_84, + TDA18272_RFATTTOP_92_85, + TDA18272_RFATTTOP_93_86, + TDA18272_RFATTTOP_94_87, + TDA18272_RFATTTOP_95_88, + TDA18272_RFATTTOP_87_81, + TDA18272_RFATTTOP_88_82, + TDA18272_RFATTTOP_89_83, + TDA18272_RFATTTOP_90_84, + TDA18272_RFATTTOP_91_85, + TDA18272_RFATTTOP_92_86, + TDA18272_RFATTTOP_93_87, + TDA18272_RFATTTOP_94_88, + TDA18272_RFATTTOP_95_89, +}; + + +#define TDA18272_AGC3_RF_AGC_TOP_FREQ_LIM 291000000 + +enum tda18272_rfagctop { + TDA18272_RFAGCTOP_94 = 0, + TDA18272_RFAGCTOP_96, + TDA18272_RFAGCTOP_98, + TDA18272_RFAGCTOP_100, + TDA18272_RFAGCTOP_102, + TDA18272_RFAGCTOP_104, + TDA18272_RFAGCTOP_106, + TDA18272_RFAGCTOP_107, +}; + +enum tda18272_irmixtop { + TDA18272_IRMIXTOP_105_99 = 0, + TDA18272_IRMIXTOP_105_100, + TDA18272_IRMIXTOP_105_101, + TDA18272_IRMIXTOP_107_101, + TDA18272_IRMIXTOP_107_102, + TDA18272_IRMIXTOP_107_103, + TDA18272_IRMIXTOP_108_103, + TDA18272_IRMIXTOP_109_103, + TDA18272_IRMIXTOP_109_104, + TDA18272_IRMIXTOP_109_105, + TDA18272_IRMIXTOP_110_104, + TDA18272_IRMIXTOP_110_105, + TDA18272_IRMIXTOP_110_106, + TDA18272_IRMIXTOP_112_106, + TDA18272_IRMIXTOP_112_107, + TDA18272_IRMIXTOP_112_108, +}; + +enum tda18272_ifagctop { + TDA18272_IFAGCTOP_105_99 = 0, + TDA18272_IFAGCTOP_105_100, + TDA18272_IFAGCTOP_105_101, + TDA18272_IFAGCTOP_107_101, + TDA18272_IFAGCTOP_107_102, + TDA18272_IFAGCTOP_107_103, + TDA18272_IFAGCTOP_108_103, + TDA18272_IFAGCTOP_109_103, + TDA18272_IFAGCTOP_109_104, + TDA18272_IFAGCTOP_109_105, + TDA18272_IFAGCTOP_110_104, + TDA18272_IFAGCTOP_110_105, + TDA18272_IFAGCTOP_110_106, + TDA18272_IFAGCTOP_112_106, + TDA18272_IFAGCTOP_112_107, + TDA18272_IFAGCTOP_112_108, +}; + +enum tda18272_dethpf { + TDA18272_DETHPF_DISABLED = 0, + TDA18272_DETHPF_ENABLED +}; + +enum tda18272_agc3adapt { + TDA18272_AGC3ADAPT_ENABLED = 0, + TDA18272_AGC3ADAPT_DISABLED, +}; + +enum tda18272_agc3adapt_top { + TDA18272_AGC3ADAPT_TOP_0 = 0, + TDA18272_AGC3ADAPT_TOP_1, + TDA18272_AGC3ADAPT_TOP_2, + TDA18272_AGC3ADAPT_TOP_3 +}; + +enum tda18272_3dbatt { + TDA18272_3DBATT_DISABLED = 0, + TDA18272_3DBATT_ENABLED, +}; + + +enum tda18272_vhffilt6 { + TDA18272_VHFFILT6_DISABLED = 0, + TDA18272_VHFFILT6_ENABLED, +}; + +enum tda18272_lpfgain { + TDA18272_LPFGAIN_UNKNOWN = 0, + TDA18272_LPFGAIN_FROZEN, + TDA18272_LPFGAIN_FREE +}; + + +enum tda18272_stdmode { + TDA18272_DVBT_6MHz = 0, + TDA18272_DVBT_7MHz, + TDA18272_DVBT_8MHz, + TDA18272_QAM_6MHz, + TDA18272_QAM_8MHz, + TDA18272_ISDBT_6MHz, + TDA18272_ATSC_6MHz, + TDA18272_DMBT_8MHz, + TDA18272_ANLG_MN, + TDA18272_ANLG_B, + TDA18272_ANLG_GH, + TDA18272_ANLG_I, + TDA18272_ANLG_DK, + TDA18272_ANLG_L, + TDA18272_ANLG_LL, + TDA18272_FM_RADIO, + TDA18272_Scanning, + TDA18272_ScanXpress, +}; + +static struct tda18272_coeff { + u8 desc[16]; + u32 if_val; + s32 cf_off; + enum tda18272_lpf lpf; + enum tda18272_lpf_offset lpf_off; + enum tda18272_agcgain if_gain; + enum tda18272_notch if_notch; + enum tda18272_hpf if_hpf; + enum tda18272_notch dc_notch; + enum tda18272_lnatop lna_top; + enum tda18272_rfatttop rfatt_top; + enum tda18272_rfagctop loband_rfagc_top; + enum tda18272_rfagctop hiband_rfagc_top; + enum tda18272_irmixtop irmix_top; + enum tda18272_ifagctop ifagc_top; + enum tda18272_dethpf det_hpf; + enum tda18272_agc3adapt agc3_adapt; + enum tda18272_agc3adapt_top agc3_adapt_top; + + enum tda18272_3dbatt att3db; + u8 gsk; + enum tda18272_vhffilt6 filter; + enum tda18272_lpfgain lpf_gain; + int agc1_freeze; + int ltosto_immune; +} coeft[] = { + { + .desc = "DVB-T 6MHz", + .if_val = 3250000, + .cf_off = 0, + .lpf = TDA18272_LPF_6MHz, + .lpf_off = TDA18272_LPFOFFSET_0PC, + .if_gain = TDA18272_AGCGAIN_1VPP, + .if_notch = TDA18272_NOTCH_ENABLED, + .if_hpf = TDA18272_HPF_0_4MHz, + .dc_notch = TDA18272_NOTCH_ENABLED, + .lna_top = TDA18272_LNATOP_95_89, + .rfatt_top = TDA18272_RFATTTOP_90_84, + .loband_rfagc_top = TDA18272_RFAGCTOP_100, + .hiband_rfagc_top = TDA18272_RFAGCTOP_102, + .irmix_top = TDA18272_IRMIXTOP_110_105, + .ifagc_top = TDA18272_IFAGCTOP_110_105, + .det_hpf = TDA18272_DETHPF_DISABLED, + .agc3_adapt = TDA18272_AGC3ADAPT_ENABLED, + .agc3_adapt_top = TDA18272_AGC3ADAPT_TOP_2, + .att3db = TDA18272_3DBATT_ENABLED, + .gsk = 0x02, + .filter = TDA18272_VHFFILT6_ENABLED, + .lpf_gain = TDA18272_LPFGAIN_FREE, + .agc1_freeze = 0, + .ltosto_immune = 0 + }, { + .desc = "DVB-T 7MHz", + .if_val = 3500000, + .cf_off = 0, + .lpf = TDA18272_LPF_7MHz, + .lpf_off = TDA18272_LPFOFFSET_8PC, + .if_gain = TDA18272_AGCGAIN_1VPP, + .if_notch = TDA18272_NOTCH_ENABLED, + .if_hpf = TDA18272_HPF_DISABLED, + .dc_notch = TDA18272_NOTCH_ENABLED, + .lna_top = TDA18272_LNATOP_95_89, + .rfatt_top = TDA18272_RFATTTOP_90_84, + .loband_rfagc_top = TDA18272_RFAGCTOP_100, + .hiband_rfagc_top = TDA18272_RFAGCTOP_102, + .irmix_top = TDA18272_IRMIXTOP_110_105, + .ifagc_top = TDA18272_IFAGCTOP_110_105, + .det_hpf = TDA18272_DETHPF_DISABLED, + .agc3_adapt = TDA18272_AGC3ADAPT_ENABLED, + .agc3_adapt_top = TDA18272_AGC3ADAPT_TOP_2, + .att3db = TDA18272_3DBATT_ENABLED, + .gsk = 0x02, + .filter = TDA18272_VHFFILT6_ENABLED, + .lpf_gain = TDA18272_LPFGAIN_FREE, + .agc1_freeze = 0, + .ltosto_immune = 0 + }, { + .desc = "DVB-T 8MHz", + .if_val = 4000000, + .cf_off = 0, + .lpf = TDA18272_LPF_8MHz, + .lpf_off = TDA18272_LPFOFFSET_0PC, + .if_gain = TDA18272_AGCGAIN_1VPP, + .if_notch = TDA18272_NOTCH_ENABLED, + .if_hpf = TDA18272_HPF_DISABLED, + .dc_notch = TDA18272_NOTCH_ENABLED, + .lna_top = TDA18272_LNATOP_95_89, + .rfatt_top = TDA18272_RFATTTOP_90_84, + .loband_rfagc_top = TDA18272_RFAGCTOP_100, + .hiband_rfagc_top = TDA18272_RFAGCTOP_102, + .irmix_top = TDA18272_IRMIXTOP_110_105, + .ifagc_top = TDA18272_IFAGCTOP_110_105, + .det_hpf = TDA18272_DETHPF_DISABLED, + .agc3_adapt = TDA18272_AGC3ADAPT_ENABLED, + .agc3_adapt_top = TDA18272_AGC3ADAPT_TOP_2, + .att3db = TDA18272_3DBATT_ENABLED, + .gsk = 0x02, + .filter = TDA18272_VHFFILT6_ENABLED, + .lpf_gain = TDA18272_LPFGAIN_FREE, + .agc1_freeze = 0, + .ltosto_immune = 0 + }, { + .desc = "QAM 6MHz", + .if_val = 3600000, + .cf_off = 0, + .lpf = TDA18272_LPF_6MHz, + .lpf_off = TDA18272_LPFOFFSET_8PC, + .if_gain = TDA18272_AGCGAIN_1VPP, + .if_notch = TDA18272_NOTCH_DISABLED, + .if_hpf = TDA18272_HPF_DISABLED, + .dc_notch = TDA18272_NOTCH_ENABLED, + .lna_top = TDA18272_LNATOP_95_89, + .rfatt_top = TDA18272_RFATTTOP_90_84, + .loband_rfagc_top = TDA18272_RFAGCTOP_100, + .hiband_rfagc_top = TDA18272_RFAGCTOP_100, + .irmix_top = TDA18272_IRMIXTOP_110_105, + .ifagc_top = TDA18272_IFAGCTOP_110_105, + .det_hpf = TDA18272_DETHPF_DISABLED, + .agc3_adapt = TDA18272_AGC3ADAPT_DISABLED, + .agc3_adapt_top = TDA18272_AGC3ADAPT_TOP_0, + .att3db = TDA18272_3DBATT_DISABLED, + .gsk = 0x02, + .filter = TDA18272_VHFFILT6_DISABLED, + .lpf_gain = TDA18272_LPFGAIN_FREE, + .agc1_freeze = 1, + .ltosto_immune = 1 + }, { + .desc = "QAM 8MHz", + .if_val = 5000000, + .cf_off = 0, + .lpf = TDA18272_LPF_9MHz, + .lpf_off = TDA18272_LPFOFFSET_8PC, + .if_gain = TDA18272_AGCGAIN_1VPP, + .if_notch = TDA18272_NOTCH_DISABLED, + .if_hpf = TDA18272_HPF_0_85MHz, + .dc_notch = TDA18272_NOTCH_ENABLED, + .lna_top = TDA18272_LNATOP_95_89, + .rfatt_top = TDA18272_RFATTTOP_90_84, + .loband_rfagc_top = TDA18272_RFAGCTOP_100, + .hiband_rfagc_top = TDA18272_RFAGCTOP_100, + .irmix_top = TDA18272_IRMIXTOP_110_105, + .ifagc_top = TDA18272_IFAGCTOP_110_105, + .det_hpf = TDA18272_DETHPF_DISABLED, + .agc3_adapt = TDA18272_AGC3ADAPT_DISABLED, + .agc3_adapt_top = TDA18272_AGC3ADAPT_TOP_0, + .att3db = TDA18272_3DBATT_DISABLED, + .gsk = 0x02, + .filter = TDA18272_VHFFILT6_DISABLED, + .lpf_gain = TDA18272_LPFGAIN_FREE, + .agc1_freeze = 1, + .ltosto_immune = 1 + }, { + .desc = "ISDB-T 6MHz", + .if_val = 3250000, + .cf_off = 0, + .lpf = TDA18272_LPF_6MHz, + .lpf_off = TDA18272_LPFOFFSET_0PC, + .if_gain = TDA18272_AGCGAIN_0_6VPP, + .if_notch = TDA18272_NOTCH_ENABLED, + .if_hpf = TDA18272_HPF_0_4MHz, + .dc_notch = TDA18272_NOTCH_ENABLED, + .lna_top = TDA18272_LNATOP_95_89, + .rfatt_top = TDA18272_RFATTTOP_90_84, + .loband_rfagc_top = TDA18272_RFAGCTOP_100, + .hiband_rfagc_top = TDA18272_RFAGCTOP_102, + .irmix_top = TDA18272_IRMIXTOP_110_105, + .ifagc_top = TDA18272_IFAGCTOP_110_105, + .det_hpf = TDA18272_DETHPF_DISABLED, + .agc3_adapt = TDA18272_AGC3ADAPT_ENABLED, + .agc3_adapt_top = TDA18272_AGC3ADAPT_TOP_2, + .att3db = TDA18272_3DBATT_ENABLED, + .gsk = 0x02, + .filter = TDA18272_VHFFILT6_ENABLED, + .lpf_gain = TDA18272_LPFGAIN_FREE, + .agc1_freeze = 0, + .ltosto_immune = 0 + }, { + .desc = "ATSC 6MHz", + .if_val = 3250000, + .cf_off = 0, + .lpf = TDA18272_LPF_6MHz, + .lpf_off = TDA18272_LPFOFFSET_0PC, + .if_gain = TDA18272_AGCGAIN_0_6VPP, + .if_notch = TDA18272_NOTCH_ENABLED, + .if_hpf = TDA18272_HPF_0_4MHz, + .dc_notch = TDA18272_NOTCH_ENABLED, + .lna_top = TDA18272_LNATOP_100_94, + .rfatt_top = TDA18272_RFATTTOP_90_84, + .loband_rfagc_top = TDA18272_RFAGCTOP_104, + .hiband_rfagc_top = TDA18272_RFAGCTOP_104, + .irmix_top = TDA18272_IRMIXTOP_112_107, + .ifagc_top = TDA18272_IFAGCTOP_112_107, + .det_hpf = TDA18272_DETHPF_DISABLED, + .agc3_adapt = TDA18272_AGC3ADAPT_ENABLED, + .agc3_adapt_top = TDA18272_AGC3ADAPT_TOP_3, + .att3db = TDA18272_3DBATT_ENABLED, + .gsk = 0x02, + .filter = TDA18272_VHFFILT6_ENABLED, + .lpf_gain = TDA18272_LPFGAIN_FREE, + .agc1_freeze = 0, + .ltosto_immune = 0 + }, { + .desc = "DMB-T 8MHz", + .if_val = 4000000, + .cf_off = 0, + .lpf = TDA18272_LPF_8MHz, + .lpf_off = TDA18272_LPFOFFSET_0PC, + .if_gain = TDA18272_AGCGAIN_1VPP, + .if_notch = TDA18272_NOTCH_ENABLED, + .if_hpf = TDA18272_HPF_DISABLED, + .dc_notch = TDA18272_NOTCH_ENABLED, + .lna_top = TDA18272_LNATOP_95_89, + .rfatt_top = TDA18272_RFATTTOP_90_84, + .loband_rfagc_top = TDA18272_RFAGCTOP_100, + .hiband_rfagc_top = TDA18272_RFAGCTOP_102, + .irmix_top = TDA18272_IRMIXTOP_110_105, + .ifagc_top = TDA18272_IFAGCTOP_110_105, + .det_hpf = TDA18272_DETHPF_DISABLED, + .agc3_adapt = TDA18272_AGC3ADAPT_ENABLED, + .agc3_adapt_top = TDA18272_AGC3ADAPT_TOP_2, + .att3db = TDA18272_3DBATT_ENABLED, + .gsk = 0x02, + .filter = TDA18272_VHFFILT6_ENABLED, + .lpf_gain = TDA18272_LPFGAIN_FREE, + .agc1_freeze = 0, + .ltosto_immune = 0 + }, { + .desc = "ATV M/N", + .if_val = 5400000, + .cf_off = 1750000, + .lpf = TDA18272_LPF_6MHz, + .lpf_off = TDA18272_LPFOFFSET_0PC, + .if_gain = TDA18272_AGCGAIN_0_7VPP, + .if_notch = TDA18272_NOTCH_DISABLED, + .if_hpf = TDA18272_HPF_DISABLED, + .dc_notch = TDA18272_NOTCH_DISABLED, + .lna_top = TDA18272_LNATOP_95_89, + .rfatt_top = TDA18272_RFATTTOP_90_84, + .loband_rfagc_top = TDA18272_RFAGCTOP_96, + .hiband_rfagc_top = TDA18272_RFAGCTOP_96, + .irmix_top = TDA18272_IRMIXTOP_105_100, + .ifagc_top = TDA18272_IFAGCTOP_105_100, + .det_hpf = TDA18272_DETHPF_ENABLED, + .agc3_adapt = TDA18272_AGC3ADAPT_DISABLED, + .agc3_adapt_top = TDA18272_AGC3ADAPT_TOP_0, + .att3db = TDA18272_3DBATT_DISABLED, + .gsk = 0x01, + .filter = TDA18272_VHFFILT6_DISABLED, + .lpf_gain = TDA18272_LPFGAIN_FROZEN, + .agc1_freeze = 0, + .ltosto_immune = 0 + }, { + .desc = "ATV B", + .if_val = 6400000, + .cf_off = 2250000, + .lpf = TDA18272_LPF_7MHz, + .lpf_off = TDA18272_LPFOFFSET_0PC, + .if_gain = TDA18272_AGCGAIN_0_7VPP, + .if_notch = TDA18272_NOTCH_DISABLED, + .if_hpf = TDA18272_HPF_DISABLED, + .dc_notch = TDA18272_NOTCH_DISABLED, + .lna_top = TDA18272_LNATOP_95_89, + .rfatt_top = TDA18272_RFATTTOP_90_84, + .loband_rfagc_top = TDA18272_RFAGCTOP_96, + .hiband_rfagc_top = TDA18272_RFAGCTOP_96, + .irmix_top = TDA18272_IRMIXTOP_105_100, + .ifagc_top = TDA18272_IFAGCTOP_105_100, + .det_hpf = TDA18272_DETHPF_ENABLED, + .agc3_adapt = TDA18272_AGC3ADAPT_DISABLED, + .agc3_adapt_top = TDA18272_AGC3ADAPT_TOP_0, + .att3db = TDA18272_3DBATT_DISABLED, + .gsk = 0x01, + .filter = TDA18272_VHFFILT6_DISABLED, + .lpf_gain = TDA18272_LPFGAIN_FROZEN, + .agc1_freeze = 0, + .ltosto_immune = 0 + }, { + .desc = "ATV G/H", + .if_val = 6750000, + .cf_off = 2750000, + .lpf = TDA18272_LPF_8MHz, + .lpf_off = TDA18272_LPFOFFSET_0PC, + .if_gain = TDA18272_AGCGAIN_0_7VPP, + .if_notch = TDA18272_NOTCH_DISABLED, + .if_hpf = TDA18272_HPF_DISABLED, + .dc_notch = TDA18272_NOTCH_DISABLED, + .lna_top = TDA18272_LNATOP_95_89, + .rfatt_top = TDA18272_RFATTTOP_90_84, + .loband_rfagc_top = TDA18272_RFAGCTOP_96, + .hiband_rfagc_top = TDA18272_RFAGCTOP_96, + .irmix_top = TDA18272_IRMIXTOP_105_100, + .ifagc_top = TDA18272_IFAGCTOP_105_100, + .det_hpf = TDA18272_DETHPF_ENABLED, + .agc3_adapt = TDA18272_AGC3ADAPT_DISABLED, + .agc3_adapt_top = TDA18272_AGC3ADAPT_TOP_0, + .att3db = TDA18272_3DBATT_DISABLED, + .gsk = 0x01, + .filter = TDA18272_VHFFILT6_DISABLED, + .lpf_gain = TDA18272_LPFGAIN_FROZEN, + .agc1_freeze = 0, + .ltosto_immune = 0 + }, { + .desc = "ATV I", + .if_val = 7250000, + .cf_off = 2750000, + .lpf = TDA18272_LPF_8MHz, + .lpf_off = TDA18272_LPFOFFSET_0PC, + .if_gain = TDA18272_AGCGAIN_0_7VPP, + .if_notch = TDA18272_NOTCH_DISABLED, + .if_hpf = TDA18272_HPF_DISABLED, + .dc_notch = TDA18272_NOTCH_DISABLED, + .lna_top = TDA18272_LNATOP_95_89, + .rfatt_top = TDA18272_RFATTTOP_90_84, + .loband_rfagc_top = TDA18272_RFAGCTOP_96, + .hiband_rfagc_top = TDA18272_RFAGCTOP_96, + .irmix_top = TDA18272_IRMIXTOP_105_100, + .ifagc_top = TDA18272_IFAGCTOP_105_100, + .det_hpf = TDA18272_DETHPF_ENABLED, + .agc3_adapt = TDA18272_AGC3ADAPT_DISABLED, + .agc3_adapt_top = TDA18272_AGC3ADAPT_TOP_0, + .att3db = TDA18272_3DBATT_DISABLED, + .gsk = 0x01, + .filter = TDA18272_VHFFILT6_DISABLED, + .lpf_gain = TDA18272_LPFGAIN_FROZEN, + .agc1_freeze = 0, + .ltosto_immune = 0 + }, { + .desc = "ATV DK", + .if_val = 6850000, + .cf_off = 2750000, + .lpf = TDA18272_LPF_8MHz, + .lpf_off = TDA18272_LPFOFFSET_0PC, + .if_gain = TDA18272_AGCGAIN_0_7VPP, + .if_notch = TDA18272_NOTCH_ENABLED, + .if_hpf = TDA18272_HPF_DISABLED, + .dc_notch = TDA18272_NOTCH_DISABLED, + .lna_top = TDA18272_LNATOP_95_89, + .rfatt_top = TDA18272_RFATTTOP_90_84, + .loband_rfagc_top = TDA18272_RFAGCTOP_96, + .hiband_rfagc_top = TDA18272_RFAGCTOP_96, + .irmix_top = TDA18272_IRMIXTOP_105_100, + .ifagc_top = TDA18272_IFAGCTOP_105_100, + .det_hpf = TDA18272_DETHPF_ENABLED, + .agc3_adapt = TDA18272_AGC3ADAPT_DISABLED, + .agc3_adapt_top = TDA18272_AGC3ADAPT_TOP_0, + .att3db = TDA18272_3DBATT_DISABLED, + .gsk = 0x01, + .filter = TDA18272_VHFFILT6_DISABLED, + .lpf_gain = TDA18272_LPFGAIN_FROZEN, + .agc1_freeze = 0, + .ltosto_immune = 0 + }, { + .desc = "ATV L", + .if_val = 6750000, + .cf_off = 2750000, + .lpf = TDA18272_LPF_8MHz, + .lpf_off = TDA18272_LPFOFFSET_0PC, + .if_gain = TDA18272_AGCGAIN_0_7VPP, + .if_notch = TDA18272_NOTCH_ENABLED, + .if_hpf = TDA18272_HPF_DISABLED, + .dc_notch = TDA18272_NOTCH_DISABLED, + .lna_top = TDA18272_LNATOP_95_89, + .rfatt_top = TDA18272_RFATTTOP_90_84, + .loband_rfagc_top = TDA18272_RFAGCTOP_96, + .hiband_rfagc_top = TDA18272_RFAGCTOP_96, + .irmix_top = TDA18272_IRMIXTOP_105_100, + .ifagc_top = TDA18272_IFAGCTOP_105_100, + .det_hpf = TDA18272_DETHPF_ENABLED, + .agc3_adapt = TDA18272_AGC3ADAPT_DISABLED, + .agc3_adapt_top = TDA18272_AGC3ADAPT_TOP_0, + .att3db = TDA18272_3DBATT_DISABLED, + .gsk = 0x01, + .filter = TDA18272_VHFFILT6_DISABLED, + .lpf_gain = TDA18272_LPFGAIN_FROZEN, + .agc1_freeze = 0, + .ltosto_immune = 0 + }, { + .desc = "ATV Lc", + .if_val = 1250000, + .cf_off = -2750000, + .lpf = TDA18272_LPF_8MHz, + .lpf_off = TDA18272_LPFOFFSET_0PC, + .if_gain = TDA18272_AGCGAIN_0_7VPP, + .if_notch = TDA18272_NOTCH_DISABLED, + .if_hpf = TDA18272_HPF_DISABLED, + .dc_notch = TDA18272_NOTCH_DISABLED, + .lna_top = TDA18272_LNATOP_95_89, + .rfatt_top = TDA18272_RFATTTOP_90_84, + .loband_rfagc_top = TDA18272_RFAGCTOP_96, + .hiband_rfagc_top = TDA18272_RFAGCTOP_96, + .irmix_top = TDA18272_IRMIXTOP_105_100, + .ifagc_top = TDA18272_IFAGCTOP_105_100, + .det_hpf = TDA18272_DETHPF_DISABLED, + .agc3_adapt = TDA18272_AGC3ADAPT_DISABLED, + .agc3_adapt_top = TDA18272_AGC3ADAPT_TOP_0, + .att3db = TDA18272_3DBATT_DISABLED, + .gsk = 0x01, + .filter = TDA18272_VHFFILT6_DISABLED, + .lpf_gain = TDA18272_LPFGAIN_FROZEN, + .agc1_freeze = 0, + .ltosto_immune = 0 + }, { + .desc = "FM Radio", + .if_val = 1250000, + .cf_off = 0, + .lpf = TDA18272_LPF_1_5MHz, + .lpf_off = TDA18272_LPFOFFSET_0PC, + .if_gain = TDA18272_AGCGAIN_0_7VPP, + .if_notch = TDA18272_NOTCH_DISABLED, + .if_hpf = TDA18272_HPF_0_85MHz, + .dc_notch = TDA18272_NOTCH_ENABLED, + .lna_top = TDA18272_LNATOP_95_89, + .rfatt_top = TDA18272_RFATTTOP_90_84, + .loband_rfagc_top = TDA18272_RFAGCTOP_96, + .hiband_rfagc_top = TDA18272_RFAGCTOP_96, + .irmix_top = TDA18272_IRMIXTOP_105_100, + .ifagc_top = TDA18272_IFAGCTOP_105_100, + .det_hpf = TDA18272_DETHPF_DISABLED, + .agc3_adapt = TDA18272_AGC3ADAPT_DISABLED, + .agc3_adapt_top = TDA18272_AGC3ADAPT_TOP_0, + .att3db = TDA18272_3DBATT_DISABLED, + .gsk = 0x02, + .filter = TDA18272_VHFFILT6_DISABLED, + .lpf_gain = TDA18272_LPFGAIN_FROZEN, + .agc1_freeze = 0, + .ltosto_immune = 0 + }, { + .desc = "PAL I Blindscan", + .if_val = 7250000, + .cf_off = 2750000, + .lpf = TDA18272_LPF_8MHz, + .lpf_off = TDA18272_LPFOFFSET_0PC, + .if_gain = TDA18272_AGCGAIN_0_7VPP, + .if_notch = TDA18272_NOTCH_DISABLED, + .if_hpf = TDA18272_HPF_DISABLED, + .dc_notch = TDA18272_NOTCH_DISABLED, + .lna_top = TDA18272_LNATOP_95_89, + .rfatt_top = TDA18272_RFATTTOP_90_84, + .loband_rfagc_top = TDA18272_RFAGCTOP_96, + .hiband_rfagc_top = TDA18272_RFAGCTOP_96, + .irmix_top = TDA18272_IRMIXTOP_105_100, + .ifagc_top = TDA18272_IFAGCTOP_105_100, + .det_hpf = TDA18272_DETHPF_ENABLED, + .agc3_adapt = TDA18272_AGC3ADAPT_DISABLED, + .agc3_adapt_top = TDA18272_AGC3ADAPT_TOP_0, + .att3db = TDA18272_3DBATT_DISABLED, + .gsk = 0x01, + .filter = TDA18272_VHFFILT6_DISABLED, + .lpf_gain = TDA18272_LPFGAIN_FROZEN, + .agc1_freeze = 0, + .ltosto_immune = 0 + }, { + .desc = "XpressScan", + .if_val = 5000000, + .cf_off = 0, + .lpf = TDA18272_LPF_9MHz, + .lpf_off = TDA18272_LPFOFFSET_0PC, + .if_gain = TDA18272_AGCGAIN_1VPP, + .if_notch = TDA18272_NOTCH_ENABLED, + .if_hpf = TDA18272_HPF_DISABLED, + .dc_notch = TDA18272_NOTCH_ENABLED, + .lna_top = TDA18272_LNATOP_95_89, + .rfatt_top = TDA18272_RFATTTOP_90_84, + .loband_rfagc_top = TDA18272_RFAGCTOP_100, + .hiband_rfagc_top = TDA18272_RFAGCTOP_102, + .irmix_top = TDA18272_IRMIXTOP_110_105, + .ifagc_top = TDA18272_IFAGCTOP_110_105, + .det_hpf = TDA18272_DETHPF_DISABLED, + .agc3_adapt = TDA18272_AGC3ADAPT_ENABLED, + .agc3_adapt_top = TDA18272_AGC3ADAPT_TOP_2, + .att3db = TDA18272_3DBATT_ENABLED, + .gsk = 0x0e, + .filter = TDA18272_VHFFILT6_ENABLED, + .lpf_gain = TDA18272_LPFGAIN_FREE, + .agc1_freeze = 0, + .ltosto_immune = 0 + }, { } +}; + +#define TDA18272_REGMAPSIZ 68 + +struct tda18272_state { + const struct tda18272_coeff *coe; + u8 lna_top; + u8 psm_agc; + u8 agc1; + u8 mode; + + u8 ms; + + u32 bandwidth; + u32 frequency; + + u8 regs[TDA18272_REGMAPSIZ]; + struct dvb_frontend *fe; + struct i2c_adapter *i2c; + const struct tda18272_config *config; +}; + +static int tda18272_rd_regs(struct tda18272_state *tda18272, u8 reg, u8 *data, int count) +{ + int ret; + const struct tda18272_config *config = tda18272->config; + struct dvb_frontend *fe = tda18272->fe; + struct i2c_msg msg[] = { + { .addr = config->addr, .flags = 0, .buf = ®, .len = 1 }, + { .addr = config->addr, .flags = I2C_M_RD, .buf = data, .len = count } + }; + + BUG_ON(count >= 255); + if (fe->ops.i2c_gate_ctrl) + fe->ops.i2c_gate_ctrl(fe, 1); + + ret = i2c_transfer(tda18272->i2c, msg, 2); + if (ret != 2) { + dprintk(FE_ERROR, 1, "I/O Error"); + ret = -EREMOTEIO; + } else { + ret = 0; + } + + if (fe->ops.i2c_gate_ctrl) + fe->ops.i2c_gate_ctrl(fe, 0); + + return ret; +} + +static int tda18272_wr_regs(struct tda18272_state *tda18272, u8 start, u8 *data, u8 count) +{ + int ret; + const struct tda18272_config *config = tda18272->config; + struct dvb_frontend *fe = tda18272->fe; + u8 buf[0x45]; + struct i2c_msg msg = { .addr = config->addr, .flags = 0, .buf = buf, .len = count + 1 }; + + BUG_ON(count >= 0x44); + BUG_ON(start >= 0x43); + BUG_ON(start + count > 0x44); + + buf[0] = start; + memcpy(&buf[1], data, count); + if (fe->ops.i2c_gate_ctrl) + fe->ops.i2c_gate_ctrl(fe, 1); + + ret = i2c_transfer(tda18272->i2c, &msg, 1); + if (ret != 1) { + dprintk(FE_ERROR, 1, "I/O Error"); + ret = -EREMOTEIO; + } else { + ret = 0; + } + + if (fe->ops.i2c_gate_ctrl) + fe->ops.i2c_gate_ctrl(fe, 0); + + return ret; +} + +static int tda18272_wr(struct tda18272_state *tda18272, u8 reg, u8 data) +{ + return tda18272_wr_regs(tda18272, reg, &data, 1); +} + +static int tda18272_rd(struct tda18272_state *tda18272, u8 reg, u8 *data) +{ + return tda18272_rd_regs(tda18272, reg, data, 1); +} + +static int tda18272_cal_wait(struct tda18272_state *tda18272) +{ + int ret = 0; + u8 xtal_cal, count = 20; + + while (count > 0) { + ret = tda18272_rd(tda18272, TDA18272_IRQ_STATUS, &tda18272->regs[TDA18272_IRQ_STATUS]); + xtal_cal = TDA18272_GETFIELD(IRQ_STATUS_XTALCAL_STATUS, tda18272->regs[TDA18272_IRQ_STATUS]); + if (ret) + break; + + if (xtal_cal) + break; + + msleep(5); + --count; + if (!count) { + ret = -1; + break; + } + } + dprintk(FE_DEBUG, 1, "ret=%d", ret); + return ret; +} + +enum tda18272_power { + TDA18272_NORMAL = 0, + TDA18272_STDBY_1, + TDA18272_STDBY_2, + TDA18272_STDBY +}; + +static int tda18272_pstate(struct tda18272_state *tda18272, enum tda18272_power pstate) +{ + int ret; + + ret = tda18272_rd_regs(tda18272, TDA18272_POWERSTATE_BYTE_2, &tda18272->regs[TDA18272_POWERSTATE_BYTE_2], 15); + if (ret) + goto err; + + if (pstate != TDA18272_NORMAL) { + TDA18272_SETFIELD(tda18272->regs[TDA18272_REFERENCE], REFERENCE_DIGITAL_CLOCK, 0); + ret = tda18272_wr(tda18272, TDA18272_REFERENCE, tda18272->regs[TDA18272_REFERENCE]); + if (ret) + goto err; + } + + switch (pstate) { + case TDA18272_NORMAL: + TDA18272_SETFIELD(tda18272->regs[TDA18272_POWERSTATE_BYTE_2], POWERSTATE_BYTE_2_SM, 0x00); + TDA18272_SETFIELD(tda18272->regs[TDA18272_POWERSTATE_BYTE_2], POWERSTATE_BYTE_2_SM_PLL, 0x00); + TDA18272_SETFIELD(tda18272->regs[TDA18272_POWERSTATE_BYTE_2], POWERSTATE_BYTE_2_SM_LNA, 0x00); + break; + case TDA18272_STDBY_1: + TDA18272_SETFIELD(tda18272->regs[TDA18272_POWERSTATE_BYTE_2], POWERSTATE_BYTE_2_SM, 0x01); + TDA18272_SETFIELD(tda18272->regs[TDA18272_POWERSTATE_BYTE_2], POWERSTATE_BYTE_2_SM_PLL, 0x00); + TDA18272_SETFIELD(tda18272->regs[TDA18272_POWERSTATE_BYTE_2], POWERSTATE_BYTE_2_SM_LNA, 0x00); + break; + case TDA18272_STDBY_2: + TDA18272_SETFIELD(tda18272->regs[TDA18272_POWERSTATE_BYTE_2], POWERSTATE_BYTE_2_SM, 0x01); + TDA18272_SETFIELD(tda18272->regs[TDA18272_POWERSTATE_BYTE_2], POWERSTATE_BYTE_2_SM_PLL, 0x01); + TDA18272_SETFIELD(tda18272->regs[TDA18272_POWERSTATE_BYTE_2], POWERSTATE_BYTE_2_SM_LNA, 0x00); + break; + case TDA18272_STDBY: + TDA18272_SETFIELD(tda18272->regs[TDA18272_POWERSTATE_BYTE_2], POWERSTATE_BYTE_2_SM, 0x01); + TDA18272_SETFIELD(tda18272->regs[TDA18272_POWERSTATE_BYTE_2], POWERSTATE_BYTE_2_SM_PLL, 0x01); + TDA18272_SETFIELD(tda18272->regs[TDA18272_POWERSTATE_BYTE_2], POWERSTATE_BYTE_2_SM_LNA, 0x01); + break; + } + ret = tda18272_wr(tda18272, TDA18272_POWERSTATE_BYTE_2, tda18272->regs[TDA18272_POWERSTATE_BYTE_2]); + if (ret) + goto err; + + if (pstate == TDA18272_NORMAL) { + if (tda18272->ms) + TDA18272_SETFIELD(tda18272->regs[TDA18272_REFERENCE], REFERENCE_XTOUT, 0x03); + + TDA18272_SETFIELD(tda18272->regs[TDA18272_REFERENCE], REFERENCE_DIGITAL_CLOCK, 0x01); + ret = tda18272_wr(tda18272, TDA18272_REFERENCE, tda18272->regs[TDA18272_REFERENCE]); + if (ret) + goto err; + } +err: + dprintk(FE_DEBUG, 1, "ret=%d", ret); + return ret; +} + +static int tda18272_wait_irq(struct tda18272_state *tda18272, u32 timeout, u32 step, u8 status) +{ + int ret; + u8 irq_status; + u32 count = timeout / step; + + BUG_ON(!count); + do { + ret = tda18272_rd(tda18272, TDA18272_IRQ_STATUS, &tda18272->regs[TDA18272_IRQ_STATUS]); + if (ret) + break; + + if (TDA18272_GETFIELD(IRQ_STATUS_IRQ_STATUS, tda18272->regs[TDA18272_IRQ_STATUS])) + break; + + if (status) { + irq_status = tda18272->regs[TDA18272_IRQ_STATUS] & 0x1f; + if (status == irq_status) + break; + } + msleep(step); + --count; + if (!count) { + ret = -1; + break; + } + } while (count); + dprintk(FE_DEBUG, 1, "ret=%d", ret); + return ret; +} + +static int tda18272_reset(struct tda18272_state *tda18272) +{ + int ret; + + ret = tda18272_rd_regs(tda18272, TDA18272_ID_BYTE_1, tda18272->regs, TDA18272_REGMAPSIZ); + if (ret) + goto err; + TDA18272_SETFIELD(tda18272->regs[TDA18272_POWER_BYTE_2], POWER_BYTE_2_RSSI_CK_SPEED, 0x00); + ret = tda18272_wr(tda18272, TDA18272_POWER_BYTE_2, tda18272->regs[TDA18272_POWER_BYTE_2]); + if (ret) + goto err; + TDA18272_SETFIELD(tda18272->regs[TDA18272_AGC1_BYTE_2], AGC1_BYTE_2_AGC1_DO_STEP, 0x02); + ret = tda18272_wr(tda18272, TDA18272_AGC1_BYTE_2, tda18272->regs[TDA18272_AGC1_BYTE_2]); + if (ret) + goto err; + TDA18272_SETFIELD(tda18272->regs[TDA18272_RF_FILTER_BYTE_3], RF_FILTER_BYTE_3_AGC2_DO_STEP, 0x01); + ret = tda18272_wr(tda18272, TDA18272_RF_FILTER_BYTE_3, tda18272->regs[TDA18272_RF_FILTER_BYTE_3]); + if (ret) + goto err; + TDA18272_SETFIELD(tda18272->regs[TDA18272_AGCK_BYTE_1], AGC1_BYTE_1_AGCs_UP_STEP_ASYM, 0x03); + ret = tda18272_wr(tda18272, TDA18272_AGCK_BYTE_1, tda18272->regs[TDA18272_AGCK_BYTE_1]); + if (ret) + goto err; + TDA18272_SETFIELD(tda18272->regs[TDA18272_AGC5_BYTE_1], AGC5_BYTE_1_AGCs_DO_STEP_ASYM, 0x02); + ret = tda18272_wr(tda18272, TDA18272_AGC5_BYTE_1, tda18272->regs[TDA18272_AGC5_BYTE_1]); + if (ret) + goto err; + ret = tda18272_wr(tda18272, TDA18272_IRQ_CLEAR, 0x9f); + if (ret) + goto err; + ret = tda18272_pstate(tda18272, TDA18272_NORMAL); + if (ret) { + dprintk(FE_ERROR, 1, "Power state switch failed, ret=%d", ret); + goto err; + } + tda18272->regs[TDA18272_MSM_BYTE_1] = 0x38; + tda18272->regs[TDA18272_MSM_BYTE_2] = 0x01; + ret = tda18272_wr_regs(tda18272, TDA18272_MSM_BYTE_1, &tda18272->regs[TDA18272_MSM_BYTE_1], 2); + if (ret) + goto err; + + ret = tda18272_wait_irq(tda18272, 1500, 50, 0x1f); + if (ret) + goto err; +err: + dprintk(FE_DEBUG, 1, "ret=%d", ret); + return ret; +} + +static int tda18272_init(struct dvb_frontend *fe) +{ + struct tda18272_state *tda18272 = fe->tuner_priv; + int ret; + + if (tda18272->mode) { + dprintk(FE_DEBUG, 1, "Initializing Master .."); + ret = tda18272_cal_wait(tda18272); + if (ret) + goto err; + } else { + dprintk(FE_DEBUG, 1, "Initializing Slave .."); + TDA18272_SETFIELD(tda18272->regs[TDA18272_FLO_MAX_BYTE], FLO_MAX_BYTE_FMAX_LO, 0x00); + ret = tda18272_wr(tda18272, TDA18272_FLO_MAX_BYTE, tda18272->regs[TDA18272_FLO_MAX_BYTE]); + if (ret) + goto err; + TDA18272_SETFIELD(tda18272->regs[TDA18272_CP_CURRENT], CP_CURRENT_N_CP_CURRENT, 0x68); + ret = tda18272_wr(tda18272, TDA18272_CP_CURRENT, tda18272->regs[TDA18272_CP_CURRENT]); + } + ret = tda18272_reset(tda18272); + if (ret) + goto err; + + TDA18272_SETFIELD(tda18272->regs[TDA18272_FLO_MAX_BYTE], FLO_MAX_BYTE_FMAX_LO, 0x0a); + ret = tda18272_wr(tda18272, TDA18272_FLO_MAX_BYTE, tda18272->regs[TDA18272_FLO_MAX_BYTE]); + if (ret) + goto err; + + TDA18272_SETFIELD(tda18272->regs[TDA18272_AGC1_BYTE_1], AGC1_BYTE_1_LT_ENABLE, tda18272->lna_top); + ret = tda18272_wr(tda18272, TDA18272_AGC1_BYTE_1, tda18272->regs[TDA18272_AGC1_BYTE_1]); + if (ret) + goto err; + + TDA18272_SETFIELD(tda18272->regs[TDA18272_PSM_BYTE_1], PSM_BYTE_1_PSM_AGC1, tda18272->psm_agc); + ret = tda18272_wr(tda18272, TDA18272_PSM_BYTE_1, tda18272->regs[TDA18272_PSM_BYTE_1]); + if (ret) + goto err; + + TDA18272_SETFIELD(tda18272->regs[TDA18272_AGC1_BYTE_1], AGC1_BYTE_1_AGC1_6_15DB, tda18272->agc1); + ret = tda18272_wr(tda18272, TDA18272_AGC1_BYTE_1, tda18272->regs[TDA18272_AGC1_BYTE_1]); + if (ret) + goto err; +err: + dprintk(FE_DEBUG, 1, "ret=%d", ret); + return ret; +} + +static int tda18272_clear_irq(struct tda18272_state *tda18272, u8 status) +{ + tda18272->regs[TDA18272_IRQ_CLEAR] = status & 0x1f; + TDA18272_SETFIELD(tda18272->regs[TDA18272_IRQ_CLEAR], IRQ_CLEAR_IRQ_CLEAR, 0x80); + return tda18272_wr(tda18272, TDA18272_IRQ_CLEAR, tda18272->regs[TDA18272_IRQ_CLEAR]); +} + +static int tda18272_set_rf(struct tda18272_state *tda18272, u32 freq) +{ + u32 tmp; + int ret; + + ret = tda18272_clear_irq(tda18272, 0x0c); + if (ret) + goto err; + + ret = tda18272_pstate(tda18272, TDA18272_NORMAL); + if (ret) + goto err; + + tmp = freq / 1000; + tda18272->regs[TDA18272_RF_FREQUENCY_BYTE_1] = (u8) ((tmp & 0xff0000) >> 16); + tda18272->regs[TDA18272_RF_FREQUENCY_BYTE_2] = (u8) ((tmp & 0x00ff00) >> 8); + tda18272->regs[TDA18272_RF_FREQUENCY_BYTE_3] = (u8) (tmp & 0x0000ff); + ret = tda18272_wr_regs(tda18272, TDA18272_RF_FREQUENCY_BYTE_1, &tda18272->regs[TDA18272_RF_FREQUENCY_BYTE_1], 3); + if (ret) + goto err; + + tda18272->regs[TDA18272_MSM_BYTE_1] = 0x41; + tda18272->regs[TDA18272_MSM_BYTE_2] = 0x01; + ret = tda18272_wr_regs(tda18272, TDA18272_MSM_BYTE_1, &tda18272->regs[TDA18272_MSM_BYTE_1], 2); + if (ret) + goto err; + + ret = tda18272_wait_irq(tda18272, 50, 5, 0x0c); + if (ret) + goto err; +err: + dprintk(FE_DEBUG, 1, "ret=%d", ret); + return ret; +} + +static int tda18272_set_frequency(struct tda18272_state *tda18272, u32 frequency) +{ + int ret; + + u8 ratio_l, ratio_h; + u32 delta_l, delta_h; + u8 loop_off, rffilt_gv = 0; + + u8 g1, count, agc1, agc1_steps, done = 0; + s16 steps_up, steps_down; + + const struct tda18272_coeff *coe = tda18272->coe; + + dprintk(FE_DEBUG, 1, "set freq=%d", frequency); + + TDA18272_SETFIELD(tda18272->regs[TDA18272_IF_BYTE_1], IF_BYTE_1_LP_FC, coe->lpf); /* LPF */ + ret = tda18272_wr(tda18272, TDA18272_IF_BYTE_1, tda18272->regs[TDA18272_IF_BYTE_1]); + if (ret) + goto err; + + TDA18272_SETFIELD(tda18272->regs[TDA18272_IF_BYTE_1], IF_BYTE_1_LP_FC_OFFSET, coe->lpf_off); + ret = tda18272_wr(tda18272, TDA18272_IF_BYTE_1, tda18272->regs[TDA18272_IF_BYTE_1]); + if (ret) + goto err; + + TDA18272_SETFIELD(tda18272->regs[TDA18272_IFAGC], IFAGC_IF_LEVEL, coe->if_gain); + ret = tda18272_wr(tda18272, TDA18272_IFAGC, tda18272->regs[TDA18272_IFAGC]); + if (ret) + goto err; + + TDA18272_SETFIELD(tda18272->regs[TDA18272_IF_BYTE_1], IF_BYTE_1_IF_NOTCH, coe->if_notch); + ret = tda18272_wr(tda18272, TDA18272_IF_BYTE_1, tda18272->regs[TDA18272_IF_BYTE_1]); + if (ret) + goto err; + + if (coe->if_hpf == TDA18272_HPF_DISABLED) { + TDA18272_SETFIELD(tda18272->regs[TDA18272_IRMIXER_BYTE_2], IRMIXER_BYTE_2_HI_PASS, 0x0); + ret = tda18272_wr(tda18272, TDA18272_IRMIXER_BYTE_2, tda18272->regs[TDA18272_IRMIXER_BYTE_2]); + if (ret) + goto err; + } else { + TDA18272_SETFIELD(tda18272->regs[TDA18272_IRMIXER_BYTE_2], IRMIXER_BYTE_2_HI_PASS, 0x1); + ret = tda18272_wr(tda18272, TDA18272_IRMIXER_BYTE_2, tda18272->regs[TDA18272_IRMIXER_BYTE_2]); + if (ret) + goto err; + TDA18272_SETFIELD(tda18272->regs[TDA18272_IF_BYTE_1], IF_BYTE_1_IF_HP_FC, (coe->if_hpf - 1)); + ret = tda18272_wr(tda18272, TDA18272_IF_BYTE_1, tda18272->regs[TDA18272_IF_BYTE_1]); + if (ret) + goto err; + } + + TDA18272_SETFIELD(tda18272->regs[TDA18272_IRMIXER_BYTE_2], IRMIXER_BYTE_2_DC_NOTCH, coe->dc_notch); + ret = tda18272_wr(tda18272, TDA18272_IRMIXER_BYTE_2, tda18272->regs[TDA18272_IRMIXER_BYTE_2]); + if (ret) + goto err; + + TDA18272_SETFIELD(tda18272->regs[TDA18272_AGC1_BYTE_1], AGC1_BYTE_1_AGC1_TOP, coe->lna_top); + ret = tda18272_wr(tda18272, TDA18272_AGC1_BYTE_1, tda18272->regs[TDA18272_AGC1_BYTE_1]); + if (ret) + goto err; + + TDA18272_SETFIELD(tda18272->regs[TDA18272_AGC2_BYTE_1], AGC2_BYTE_1_AGC2_TOP, coe->rfatt_top); + ret = tda18272_wr(tda18272, TDA18272_AGC2_BYTE_1, tda18272->regs[TDA18272_AGC2_BYTE_1]); + if (ret) + goto err; + + if (frequency < TDA18272_AGC3_RF_AGC_TOP_FREQ_LIM) + TDA18272_SETFIELD(tda18272->regs[TDA18272_RFAGC_BYTE_1], RFAGC_BYTE_1_AGC3_TOP, coe->loband_rfagc_top); + else + TDA18272_SETFIELD(tda18272->regs[TDA18272_RFAGC_BYTE_1], RFAGC_BYTE_1_AGC3_TOP, coe->hiband_rfagc_top); + ret = tda18272_wr(tda18272, TDA18272_RFAGC_BYTE_1, tda18272->regs[TDA18272_RFAGC_BYTE_1]); + if (ret) + goto err; + + TDA18272_SETFIELD(tda18272->regs[TDA18272_IRMIXER_BYTE_1], IRMIXER_BYTE_1_AGC4_TOP, coe->irmix_top); + ret = tda18272_wr(tda18272, TDA18272_IRMIXER_BYTE_1, tda18272->regs[TDA18272_IRMIXER_BYTE_1]); + if (ret) + goto err; + + TDA18272_SETFIELD(tda18272->regs[TDA18272_AGC5_BYTE_1], AGC5_BYTE_1_AGC5_TOP, coe->ifagc_top); + ret = tda18272_wr(tda18272, TDA18272_AGC5_BYTE_1, tda18272->regs[TDA18272_AGC5_BYTE_1]); + if (ret) + goto err; + + TDA18272_SETFIELD(tda18272->regs[TDA18272_RFAGC_BYTE_1], RFAGC_BYTE_1_PD_RFAGC_ADAPT, coe->agc3_adapt); + ret = tda18272_wr(tda18272, TDA18272_RFAGC_BYTE_1, tda18272->regs[TDA18272_RFAGC_BYTE_1]); + if (ret) + goto err; + + TDA18272_SETFIELD(tda18272->regs[TDA18272_RFAGC_BYTE_1], RFAGC_BYTE_1_RFAGC_ADAPT_TOP, coe->agc3_adapt_top); + ret = tda18272_wr(tda18272, TDA18272_RFAGC_BYTE_1, tda18272->regs[TDA18272_RFAGC_BYTE_1]); + if (ret) + goto err; + + TDA18272_SETFIELD(tda18272->regs[TDA18272_RFAGC_BYTE_1], RFAGC_BYTE_1_RF_ATTEN_3DB, coe->att3db); + ret = tda18272_wr(tda18272, TDA18272_RFAGC_BYTE_1, tda18272->regs[TDA18272_RFAGC_BYTE_1]); + if (ret) + goto err; + + TDA18272_SETFIELD(tda18272->regs[TDA18272_AGC5_BYTE_1], AGC5_BYTE_1_AGC5_HPF, coe->det_hpf); + ret = tda18272_wr(tda18272, TDA18272_AGC5_BYTE_1, tda18272->regs[TDA18272_AGC5_BYTE_1]); + if (ret) + goto err; + + TDA18272_SETFIELD(tda18272->regs[TDA18272_AGCK_BYTE_1], AGCK_BYTE_1_AGCK_MODE, coe->gsk & 0x03); + ret = tda18272_wr(tda18272, TDA18272_AGCK_BYTE_1, tda18272->regs[TDA18272_AGCK_BYTE_1]); + if (ret) + goto err; + + TDA18272_SETFIELD(tda18272->regs[TDA18272_AGCK_BYTE_1], AGCK_BYTE_1_AGCK_STEP, (coe->gsk & 0x0c) >> 2); + ret = tda18272_wr(tda18272, TDA18272_AGCK_BYTE_1, tda18272->regs[TDA18272_AGCK_BYTE_1]); + if (ret) + goto err; + + TDA18272_SETFIELD(tda18272->regs[TDA18272_PSM_BYTE_1], PSM_BYTE_1_PSM_STOB, coe->filter); + ret = tda18272_wr(tda18272, TDA18272_PSM_BYTE_1, tda18272->regs[TDA18272_PSM_BYTE_1]); + if (ret) + goto err; + + TDA18272_SETFIELD(tda18272->regs[TDA18272_IF_FREQUENCY], IF_FREQUENCY_IF_FREQ, (coe->if_val - coe->cf_off) / 50000); + ret = tda18272_wr(tda18272, TDA18272_IF_FREQUENCY, tda18272->regs[TDA18272_IF_FREQUENCY]); + if (ret) + goto err; + + if (coe->ltosto_immune && tda18272->mode) { + ret = tda18272_rd(tda18272, TDA18272_RF_AGC_GAIN_BYTE_1, &tda18272->regs[TDA18272_RF_AGC_GAIN_BYTE_1]); + if (ret) + goto err; + rffilt_gv = TDA18272_GETFIELD(RF_AGC_GAIN_BYTE_1_RF_FILTER_GAIN, tda18272->regs[TDA18272_RF_AGC_GAIN_BYTE_1]); + + TDA18272_SETFIELD(tda18272->regs[TDA18272_RF_FILTER_BYTE_1], RF_FILTER_BYTE_1_RF_FILTER_GV, rffilt_gv); + ret = tda18272_wr(tda18272, TDA18272_RF_FILTER_BYTE_1, tda18272->regs[TDA18272_RF_FILTER_BYTE_1]); + if (ret) + goto err; + + TDA18272_SETFIELD(tda18272->regs[TDA18272_RF_FILTER_BYTE_1], RF_FILTER_BYTE_1_FORCE_AGC2_GAIN, 0x1); + ret = tda18272_wr(tda18272, TDA18272_RF_FILTER_BYTE_1, tda18272->regs[TDA18272_RF_FILTER_BYTE_1]); + if (ret) + goto err; + + if (rffilt_gv) { + do { + TDA18272_SETFIELD(tda18272->regs[TDA18272_RF_FILTER_BYTE_1], RF_FILTER_BYTE_1_RF_FILTER_GV, (rffilt_gv - 1)); + ret = tda18272_wr(tda18272, TDA18272_RF_FILTER_BYTE_1, tda18272->regs[TDA18272_RF_FILTER_BYTE_1]); + if (ret) + goto err; + + msleep(10); + rffilt_gv -= 1; + } while (rffilt_gv > 0); + } + TDA18272_SETFIELD(tda18272->regs[TDA18272_RFAGC_BYTE_1], RFAGC_BYTE_1_RF_ATTEN_3DB, 0x01); + ret = tda18272_wr(tda18272, TDA18272_RFAGC_BYTE_1, tda18272->regs[TDA18272_RFAGC_BYTE_1]); + if (ret) + goto err; + } + ret = tda18272_set_rf(tda18272, frequency + coe->cf_off); + if (ret) + goto err; + + if (coe->ltosto_immune && tda18272->mode) { + TDA18272_SETFIELD(tda18272->regs[TDA18272_RFAGC_BYTE_1], RFAGC_BYTE_1_RF_ATTEN_3DB, 0x00); + ret = tda18272_wr(tda18272, TDA18272_RFAGC_BYTE_1, tda18272->regs[TDA18272_RFAGC_BYTE_1]); + if (ret) + goto err; + + msleep(50); + TDA18272_SETFIELD(tda18272->regs[TDA18272_RF_FILTER_BYTE_1], RF_FILTER_BYTE_1_FORCE_AGC2_GAIN, 0x1); + ret = tda18272_wr(tda18272, TDA18272_RF_FILTER_BYTE_1, tda18272->regs[TDA18272_RF_FILTER_BYTE_1]); + if (ret) + goto err; + } + ratio_l = (u8)(frequency / 16000000); + ratio_h = (u8)(frequency / 16000000) + 1; + delta_l = (frequency - (ratio_l * 16000000)); + delta_h = ((ratio_h * 16000000) - frequency); + + if (frequency < 72000000) { + TDA18272_SETFIELD(tda18272->regs[TDA18272_REFERENCE], REFERENCE_DIGITAL_CLOCK, 0x1); + } else if (frequency < 104000000) { + TDA18272_SETFIELD(tda18272->regs[TDA18272_REFERENCE], REFERENCE_DIGITAL_CLOCK, 0x0); + } else if (frequency <= 120000000) { + TDA18272_SETFIELD(tda18272->regs[TDA18272_REFERENCE], REFERENCE_DIGITAL_CLOCK, 0x1); + } else { + if (delta_l <= delta_h) { + if (ratio_l & 0x000001) + TDA18272_SETFIELD(tda18272->regs[TDA18272_REFERENCE], REFERENCE_DIGITAL_CLOCK, 0x0); + else + TDA18272_SETFIELD(tda18272->regs[TDA18272_REFERENCE], REFERENCE_DIGITAL_CLOCK, 0x1); + } else { + if (ratio_l & 0x000001) + TDA18272_SETFIELD(tda18272->regs[TDA18272_REFERENCE], REFERENCE_DIGITAL_CLOCK, 0x1); + else + TDA18272_SETFIELD(tda18272->regs[TDA18272_REFERENCE], REFERENCE_DIGITAL_CLOCK, 0x0); + } + } + ret = tda18272_wr(tda18272, TDA18272_REFERENCE, tda18272->regs[TDA18272_REFERENCE]); + if (ret) + goto err; + + if (coe->agc1_freeze) { + tda18272_rd(tda18272, TDA18272_AGC1_BYTE_2, &tda18272->regs[TDA18272_AGC1_BYTE_2]); + loop_off = TDA18272_GETFIELD(AGC1_BYTE_2_AGC1_LOOP_OFF, tda18272->regs[TDA18272_AGC1_BYTE_2]); + if (!loop_off) { + TDA18272_SETFIELD(tda18272->regs[TDA18272_AGC1_BYTE_2], AGC1_BYTE_2_AGC1_LOOP_OFF, 0x1); + ret = tda18272_wr(tda18272, TDA18272_AGC1_BYTE_2, tda18272->regs[TDA18272_AGC1_BYTE_2]); + if (ret) + goto err; + TDA18272_SETFIELD(tda18272->regs[TDA18272_AGC1_BYTE_2], AGC1_BYTE_2_FORCE_AGC1_GAIN, 0x01); + ret = tda18272_wr(tda18272, TDA18272_AGC1_BYTE_2, tda18272->regs[TDA18272_AGC1_BYTE_2]); + if (ret) + goto err; + } + if (!TDA18272_GETFIELD(AGC1_BYTE_1_AGC1_6_15DB, tda18272->regs[TDA18272_AGC1_BYTE_1])) { + agc1 = 0; + agc1_steps = 10; + } else { + agc1 = 6; + agc1_steps = 4; + } + + while (done < agc1_steps) { + count = 0; + steps_up = 0; + steps_down = 0; + done += 1; + + while ((count++) < 40) { + ret = tda18272_rd(tda18272, TDA18272_AGC_DET_OUT, &tda18272->regs[TDA18272_AGC_DET_OUT]); + if (ret) + goto err; + steps_down += (TDA18272_GETFIELD(AGC_DET_OUT_DO_AGC1, tda18272->regs[TDA18272_AGC_DET_OUT]) ? 14 : -1); + steps_up += (TDA18272_GETFIELD(AGC_DET_OUT_UP_AGC1, tda18272->regs[TDA18272_AGC_DET_OUT]) ? 1 : -4); + msleep(1); + } + if (steps_up >= 15 && (TDA18272_GETFIELD(AGC1_BYTE_2_AGC1_GAIN, tda18272->regs[TDA18272_AGC1_BYTE_2]) != 9)) { + g1 = TDA18272_GETFIELD(AGC1_BYTE_2_AGC1_GAIN, tda18272->regs[TDA18272_AGC1_BYTE_2]) + 1; + TDA18272_SETFIELD(tda18272->regs[TDA18272_AGC1_BYTE_2], AGC1_BYTE_2_AGC1_GAIN, g1); + ret = tda18272_wr(tda18272, TDA18272_AGC1_BYTE_2, tda18272->regs[TDA18272_AGC1_BYTE_2]); + if (ret) + goto err; + } else if (steps_down >= 10 && TDA18272_GETFIELD(AGC1_BYTE_2_AGC1_GAIN, tda18272->regs[TDA18272_AGC1_BYTE_2]) != agc1) { + g1 = TDA18272_GETFIELD(AGC1_BYTE_2_AGC1_GAIN, tda18272->regs[TDA18272_AGC1_BYTE_2]) - 1; + TDA18272_SETFIELD(tda18272->regs[TDA18272_AGC1_BYTE_2], AGC1_BYTE_2_AGC1_GAIN, g1); + ret = tda18272_wr(tda18272, TDA18272_AGC1_BYTE_2, tda18272->regs[TDA18272_AGC1_BYTE_2]); + if (ret) + goto err; + } else { + done = agc1_steps; + } + } + } else { + TDA18272_SETFIELD(tda18272->regs[TDA18272_AGC1_BYTE_2], AGC1_BYTE_2_FORCE_AGC1_GAIN, 0x00); + ret = tda18272_wr(tda18272, TDA18272_AGC1_BYTE_2, tda18272->regs[TDA18272_AGC1_BYTE_2]); + if (ret) + goto err; + + TDA18272_SETFIELD(tda18272->regs[TDA18272_AGC1_BYTE_2], AGC1_BYTE_2_AGC1_LOOP_OFF, 0x00); + ret = tda18272_wr(tda18272, TDA18272_AGC1_BYTE_2, tda18272->regs[TDA18272_AGC1_BYTE_2]); + if (ret) + goto err; + } +err: + dprintk(FE_DEBUG, 1, "ret=%d", ret); + return ret; +} + +static int tda18272_get_status(struct dvb_frontend *fe, u32 *status) +{ + struct tda18272_state *tda18272 = fe->tuner_priv; + int ret = 0; + + *status = 0; + + ret = tda18272_wr(tda18272, TDA18272_THERMO_BYTE_2, 0x01); + if (ret) + goto err; + + ret = tda18272_rd(tda18272, TDA18272_THERMO_BYTE_1, &tda18272->regs[TDA18272_THERMO_BYTE_1]); + if (ret) + goto err; + + ret = tda18272_rd_regs(tda18272, TDA18272_POWERSTATE_BYTE_1, &tda18272->regs[TDA18272_POWERSTATE_BYTE_1], 3); + if (ret) + goto err; + + if (TDA18272_GETFIELD(POWERSTATE_BYTE_1_LO_LOCK, tda18272->regs[TDA18272_POWERSTATE_BYTE_1])) { + dprintk(FE_ERROR, 1, "PLL Locked"); + *status |= 0x01; + } + if ((tda18272->regs[TDA18272_POWERSTATE_BYTE_2] >> 1) == 0) + dprintk(FE_ERROR, 1, "Normal MODE"); + if ((tda18272->regs[TDA18272_POWERSTATE_BYTE_2] >> 1) == 7) + dprintk(FE_ERROR, 1, "Standby MODE, LNA=ON, PLL=OFF"); + if ((tda18272->regs[TDA18272_POWERSTATE_BYTE_2] >> 1) == 6) + dprintk(FE_ERROR, 1, "Standby MODE, LNA=ON, PLL=OFF"); + if ((tda18272->regs[TDA18272_POWERSTATE_BYTE_2] >> 1) == 4) + dprintk(FE_ERROR, 1, "Standby MODE, LNA=ON, PLL=ON"); + + dprintk(FE_ERROR, 1, "Junction Temperature:%d Power level:%d", + tda18272->regs[TDA18272_THERMO_BYTE_1], + tda18272->regs[TDA18272_INPUT_POWERLEVEL]); + +err: + dprintk(FE_DEBUG, 1, "ret=%d", ret); + return ret; +} +#if 0 +static int tda18272_set_state(struct dvb_frontend *fe, enum tuner_param param, struct tuner_state *state) +{ + return -EINVAL; +} + +static int tda18272_get_state(struct dvb_frontend *fe, enum tuner_param param, struct tuner_state *state) +{ + struct tda18272_state *tda18272 = fe->tuner_priv; + const struct tda18272_coeff *coe = tda18272->coe; + int ret; + + switch (param) { + case DVBFE_TUNER_FREQUENCY: + state->frequency = tda18272->frequency; + ret = 0; + break; + case DVBFE_TUNER_TUNERSTEP: + state->tunerstep = fe->ops.tuner_ops.info.frequency_step; + ret = 0; + break; + case DVBFE_TUNER_IFFREQ: + state->ifreq = coe->if_val; + ret = 0; + break; + case DVBFE_TUNER_BANDWIDTH: + if (fe->ops.info.type == FE_OFDM) + state->bandwidth = tda18272->bandwidth; + ret = 0; + break; + default: + ret = -EINVAL; + break; + } + return ret; +} +#endif +static int tda18272_set_params(struct dvb_frontend *fe) +{ + struct dtv_frontend_properties *c = &fe->dtv_property_cache; + struct tda18272_state *tda18272 = fe->tuner_priv; + struct tda18272_coeff *coe = NULL; + u32 status; + u32 delsys = c->delivery_system; + u32 bw = c->bandwidth_hz; + u32 freq = c->frequency; + int ret; + + BUG_ON(!tda18272); + + dprintk(FE_DEBUG, 1, "freq=%d, bw=%d", freq, bw); + switch (delsys) { + case SYS_ATSC: + coe = coeft + TDA18272_ATSC_6MHz; + break; + case SYS_DVBT: + case SYS_DVBT2: + switch (bw) { + case 6000000: + coe = coeft + TDA18272_DVBT_6MHz; + break; + case 7000000: + coe = coeft + TDA18272_DVBT_7MHz; + break; + case 8000000: + coe = coeft + TDA18272_DVBT_8MHz; + break; + default: + coe = NULL; + ret = -EINVAL; + goto err; + } + break; + case SYS_DVBC_ANNEX_A: + case SYS_DVBC_ANNEX_C: + coe = coeft + TDA18272_QAM_8MHz; + break; + case SYS_DVBC_ANNEX_B: + coe = coeft + TDA18272_QAM_6MHz; + break; + } + BUG_ON(!coe); + tda18272->coe = coe; + dprintk(FE_DEBUG, 1, "Loading %s coeffecients...", coe->desc); + ret = tda18272_set_frequency(tda18272, freq); + if (ret) + goto err; + msleep(100); + ret = tda18272_get_status(fe, &status); + if (ret) + goto err; + + if (status == 0x01) { + tda18272->frequency = freq; + if (fe->ops.info.type == FE_OFDM) + tda18272->bandwidth = bw; + } +err: + dprintk(FE_DEBUG, 1, "ret=%d", ret); + return ret; +} + +static int tda18272_get_ifreq(struct dvb_frontend *fe, u32 *frequency) +{ + struct tda18272_state *tda18272 = fe->tuner_priv; + const struct tda18272_coeff *coe = tda18272->coe; + + *frequency = coe->if_val; + return 0; +} + +static int tda18272_release(struct dvb_frontend *fe) +{ + struct tda18272_state *tda18272 = fe->tuner_priv; + + BUG_ON(!tda18272); + fe->tuner_priv = NULL; + kfree(tda18272); + return 0; +} + +static struct dvb_tuner_ops tda18272_ops = { + .info = { + .name = "TDA18272 Silicon Tuner", + .frequency_min = 42000000, + .frequency_max = 870000000, + .frequency_step = 50000, + }, + .init = tda18272_init, + .get_status = tda18272_get_status, + .set_params = tda18272_set_params, + //.set_state = tda18272_set_state, + //.get_state = tda18272_get_state, + .get_frequency = tda18272_get_ifreq, + .release = tda18272_release +}; + + +#define TDA18272_CHIP_ID 18272 +#define TDA18272_MAJOR_REV 1 +#define TDA18272_MINOR_REV 1 + +struct dvb_frontend *tda18272_attach(struct dvb_frontend *fe, + struct i2c_adapter *i2c, + const struct tda18272_config *config) +{ + struct tda18272_state *tda18272; + u8 major = 0, minor = 0, mode = 0; + int id = 0, ret; + + tda18272 = kzalloc(sizeof (struct tda18272_state), GFP_KERNEL); + if (!tda18272) + goto err; + + BUG_ON(!i2c); + BUG_ON(!config); + + tda18272->i2c = i2c; + tda18272->config = config; + tda18272->fe = fe; + + fe->tuner_priv = tda18272; + fe->ops.tuner_ops = tda18272_ops; + + ret = tda18272_rd_regs(tda18272, TDA18272_ID_BYTE_1, &tda18272->regs[TDA18272_ID_BYTE_1], 3); + if (ret) + goto err; + + id = (TDA18272_GETFIELD(ID_BYTE_1_IDENT, tda18272->regs[TDA18272_ID_BYTE_1]) << 8) | + TDA18272_GETFIELD(ID_BYTE_2_IDENT, tda18272->regs[TDA18272_ID_BYTE_2]); + + major = TDA18272_GETFIELD(ID_BYTE_3_MAJOR_REV, tda18272->regs[TDA18272_ID_BYTE_3]); + minor = TDA18272_GETFIELD(ID_BYTE_3_MINOR_REV, tda18272->regs[TDA18272_ID_BYTE_3]); + mode = TDA18272_GETFIELD(ID_BYTE_1_MASTER_SLAVE, tda18272->regs[TDA18272_ID_BYTE_1]); + + if (id == TDA18272_CHIP_ID) { + dprintk(FE_ERROR, 1, "Found TDA%d %s Rev:%d.%d", id, mode ? "Master" : "Slave", major, minor); + if ((major != TDA18272_MAJOR_REV) || (minor != TDA18272_MINOR_REV)) + dprintk(FE_ERROR, 1, "Unknown Version:%d.%d, trying anyway ..", major, minor); + + tda18272->mode = mode; + if (config->mode == TDA18272_SLAVE && tda18272->mode == 1) + dprintk(FE_ERROR, 1, "Config as TDA18272 Slave, but TDA18272 Master found ???"); + + if (config->mode == TDA18272_MASTER) + tda18272->ms = 1; + else + tda18272->ms = 0; + + tda18272->lna_top = 0; + tda18272->psm_agc = 1; + tda18272->agc1 = 0; + + ret = tda18272_init(fe); + if (ret) { + dprintk(FE_ERROR, 1, "Error Initializing!"); + goto err1; + } + + dprintk(FE_DEBUG, 1, "Done"); + return tda18272->fe; + } +err: + dprintk(FE_ERROR, 1, "TDA18272 not found!, ID=0x%02x exiting..", id); +err1: + kfree(tda18272); + return NULL; +} +EXPORT_SYMBOL(tda18272_attach); + +MODULE_AUTHOR("Manu Abraham"); +MODULE_DESCRIPTION("TDA18272 Silicon tuner"); +MODULE_LICENSE("GPL"); diff --git a/drivers/media/tuners/tda18272.h b/drivers/media/tuners/tda18272.h new file mode 100644 index 000000000000..48acfe617d05 --- /dev/null +++ b/drivers/media/tuners/tda18272.h @@ -0,0 +1,47 @@ +/* + TDA18272 Silicon tuner driver + Copyright (C) Manu Abraham + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + */ + +#ifndef __TDA18272_H +#define __TDA18272_H + +enum tda18272_mode { + TDA18272_SINGLE = 0, + TDA18272_MASTER, + TDA18272_SLAVE, +}; + +struct tda18272_config { + u8 addr; + enum tda18272_mode mode; +}; + +#if IS_ENABLED(CONFIG_MEDIA_TUNER_TDA18272) + +extern struct dvb_frontend *tda18272_attach(struct dvb_frontend *fe, + struct i2c_adapter *i2c, + const struct tda18272_config *config); + +#else +static inline struct dvb_frontend *tda18272_attach(struct dvb_frontend *fe, + struct i2c_adapter *i2c, + const struct tda18272_config *config) +{ + printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__); + return NULL; +} + +#endif /* CONFIG_MEDIA_TUNER_TDA18272 */ + +#endif /* __TDA18272_H */ diff --git a/drivers/media/tuners/tda18272_reg.h b/drivers/media/tuners/tda18272_reg.h new file mode 100644 index 000000000000..610435acc16d --- /dev/null +++ b/drivers/media/tuners/tda18272_reg.h @@ -0,0 +1,528 @@ +/* + TDA18272 Silicon tuner driver + Copyright (C) Manu Abraham + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + */ + +#ifndef __TDA18272_REG_H +#define __TDA18272_REG_H + +#define TDA18272_ID_BYTE_1 0x00 +#define TDA18272_OFFST_ID_BYTE_1_MASTER_SLAVE 7 +#define TDA18272_WIDTH_ID_BYTE_1_MASTER_SLAVE 1 +#define TDA18272_OFFST_ID_BYTE_1_IDENT 0 +#define TDA18272_WIDTH_ID_BYTE_1_IDENT 7 + +#define TDA18272_ID_BYTE_2 0x01 +#define TDA18272_OFFST_ID_BYTE_2_IDENT 0 +#define TDA18272_WIDTH_ID_BYTE_2_IDENT 8 + +#define TDA18272_ID_BYTE_3 0x02 +#define TDA18272_OFFST_ID_BYTE_3_MAJOR_REV 4 +#define TDA18272_WIDTH_ID_BYTE_3_MAJOR_REV 4 +#define TDA18272_OFFST_ID_BYTE_3_MINOR_REV 0 +#define TDA18272_WIDTH_ID_BYTE_3_MINOR_REV 4 + +#define TDA18272_THERMO_BYTE_1 0x03 +#define TDA18272_OFFST_THERMO_BYTE_1_TM_D 0 +#define TDA18272_WIDTH_THERMO_BYTE_1_TM_D 7 + +#define TDA18272_THERMO_BYTE_2 0x04 +#define TDA18272_OFFST_THERMO_BYTE_2_TM_ON O +#define TDA18272_WIDTH_THERMO_BYTE_2_TM_ON 1 + +#define TDA18272_POWERSTATE_BYTE_1 0x05 +#define TDA18272_OFFST_POWERSTATE_BYTE_1_POR 1 +#define TDA18272_WIDTH_POWERSTATE_BYTE_1_POR 1 +#define TDA18272_OFFST_POWERSTATE_BYTE_1_LO_LOCK 0 +#define TDA18272_WIDTH_POWERSTATE_BYTE_1_LO_LOCK 1 + +#define TDA18272_POWERSTATE_BYTE_2 0x06 +#define TDA18272_OFFST_POWERSTATE_BYTE_2_SM_LNA 1 +#define TDA18272_WIDTH_POWERSTATE_BYTE_2_SM_LNA 1 +#define TDA18272_OFFST_POWERSTATE_BYTE_2_SM_PLL 2 +#define TDA18272_WIDTH_POWERSTATE_BYTE_2_SM_PLL 1 +#define TDA18272_OFFST_POWERSTATE_BYTE_2_SM 3 +#define TDA18272_WIDTH_POWERSTATE_BYTE_2_SM 1 + +#define TDA18272_INPUT_POWERLEVEL 0x07 +#define TDA18272_OFFST_INPUT_POWERLEVEL_POWER_LEVEL 0 +#define TDA18272_WIDTH_INPUT_POWERLEVEL_POWER_LEVEL 7 + +#define TDA18272_IRQ_STATUS 0x08 +#define TDA18272_OFFST_IRQ_STATUS_IRQ_STATUS 7 +#define TDA18272_WIDTH_IRQ_STATUS_IRQ_STATUS 1 +#define TDA18272_OFFST_IRQ_STATUS_XTALCAL_STATUS 5 +#define TDA18272_WIDTH_IRQ_STATUS_XTALCAL_STATUS 1 +#define TDA18272_OFFST_IRQ_STATUS_MSM_RSSI_STATUS 4 +#define TDA18272_WIDTH_IRQ_STATUS_MSM_RSSI_STATUS 1 +#define TDA18272_OFFST_IRQ_STATUS_MSM_LOCALC_STATUS 3 +#define TDA18272_WIDTH_IRQ_STATUS_MSM_LOCALC_STATUS 1 +#define TDA18272_OFFST_IRQ_STATUS_MSM_RFCAL_STATUS 2 +#define TDA18272_WIDTH_IRQ_STATUS_MSM_RFCAL_STATUS 1 +#define TDA18272_OFFST_IRQ_STATUS_MSM_IRCAL_STATUS 1 +#define TDA18272_WIDTH_IRQ_STATUS_MSM_IRCAL_STATUS 1 +#define TDA18272_OFFST_IRQ_STATUS_MSM_RCCAL_STATUS 0 +#define TDA18272_WIDTH_IRQ_STATUS_MSM_RCCAL_STATUS 1 + +#define TDA18272_IRQ_ENABLE 0x09 +#define TDA18272_OFFST_IRQ_ENABLE_IRQ_ENABLE 7 +#define TDA18272_WIDTH_IRQ_ENABLE_IRQ_ENABLE 1 +#define TDA18272_OFFST_IRQ_ENABLE_UNUSED_I0_D0 6 +#define TDA18272_WIDTH_IRQ_ENABLE_UNUSED_I0_D0 1 +#define TDA18272_OFFST_IRQ_ENABLE_XTALCAL_ENABLE 5 +#define TDA18272_WIDTH_IRQ_ENABLE_XTALCAL_ENABLE 1 +#define TDA18272_OFFST_IRQ_ENABLE_MSM_RSSI_ENABLE 4 +#define TDA18272_WIDTH_IRQ_ENABLE_MSM_RSSI_ENABLE 1 +#define TDA18272_OFFST_IRQ_ENABLE_MSM_LOCALC_ENABLE 3 +#define TDA18272_WIDTH_IRQ_ENABLE_MSM_LOCALC_ENABLE 1 +#define TDA18272_OFFST_IRQ_ENABLE_MSM_RFCAL_ENABLE 2 +#define TDA18272_WIDTH_IRQ_ENABLE_MSM_RFCAL_ENABLE 1 +#define TDA18272_OFFST_IRQ_ENABLE_MSM_IRCAL_ENABLE 1 +#define TDA18272_WIDTH_IRQ_ENABLE_MSM_IRCAL_ENABLE 1 +#define TDA18272_OFFST_IRQ_ENABLE_MSM_RCCAL_ENABLE 0 +#define TDA18272_WIDTH_IRQ_ENABLE_MSM_RCCAL_ENABLE 1 + +#define TDA18272_IRQ_CLEAR 0x0a +#define TDA18272_OFFST_IRQ_CLEAR_IRQ_CLEAR 7 +#define TDA18272_WIDTH_IRQ_CLEAR_IRQ_CLEAR 1 + +#define TDA18272_IRQ_SET 0x0b +#define TDA18272_OFFST_IRQ_SET_IRQ_SET 7 +#define TDA18272_WIDTH_IRQ_SET_IRQ_SET 1 +#define TDA18272_OFFST_IRQ_SET_UNUSED_I0_D0 6 +#define TDA18272_WIDTH_IRQ_SET_UNUSED_I0_D0 1 +#define TDA18272_OFFST_IRQ_SET_XTALCAL_SET 5 +#define TDA18272_WIDTH_IRQ_SET_XTALCAL_SET 1 +#define TDA18272_OFFST_IRQ_SET_MSM_RSSI_SET 4 +#define TDA18272_WIDTH_IRQ_SET_MSM_RSSI_SET 1 +#define TDA18272_OFFST_IRQ_SET_MSM_LOCALC_SET 3 +#define TDA18272_WIDTH_IRQ_SET_MSM_LOCALC_SET 1 +#define TDA18272_OFFST_IRQ_SET_MSM_RFCAL_SET 2 +#define TDA18272_WIDTH_IRQ_SET_MSM_RFCAL_SET 1 +#define TDA18272_OFFST_IRQ_SET_MSM_IRCAL_SET 1 +#define TDA18272_WIDTH_IRQ_SET_MSM_IRCAL_SET 1 +#define TDA18272_OFFST_IRQ_SET_MSM_RCCAL_SET 0 +#define TDA18272_WIDTH_IRQ_SET_MSM_RCCAL_SET 1 + +#define TDA18272_AGC1_BYTE_1 0x0c +#define TDA18272_OFFST_AGC1_BYTE_1_LT_ENABLE 7 +#define TDA18272_WIDTH_AGC1_BYTE_1_LT_ENABLE 1 +#define TDA18272_OFFST_AGC1_BYTE_1_AGC1_6_15DB 6 +#define TDA18272_WIDTH_AGC1_BYTE_1_AGC1_6_15DB 1 +#define TDA18272_OFFST_AGC1_BYTE_1_AGC1_TOP 0 +#define TDA18272_WIDTH_AGC1_BYTE_1_AGC1_TOP 4 + +#define TDA18272_AGC2_BYTE_1 0x0d +#define TDA18272_OFFST_AGC2_BYTE_1_UNUSED_I0_D0 5 +#define TDA18272_WIDTH_AGC2_BYTE_1_UNUSED_I0_D0 3 +#define TDA18272_OFFST_AGC2_BYTE_1_AGC2_TOP 0 +#define TDA18272_WIDTH_AGC2_BYTE_1_AGC2_TOP 5 + +#define TDA18272_AGCK_BYTE_1 0x0e +#define TDA18272_OFFST_AGC1_BYTE_1_AGCs_UP_STEP_ASYM 6 +#define TDA18272_WIDTH_AGC1_BYTE_1_AGCs_UP_STEP_ASYM 2 +#define TDA18272_OFFST_AGCK_BYTE_1_AGCs_UP_STEP 5 +#define TDA18272_WIDTH_AGCK_BYTE_1_AGCs_UP_STEP 1 +#define TDA18272_OFFST_AGCK_BYTE_1_PULSE_SHAPER_DISABLE 4 +#define TDA18272_WIDTH_AGCK_BYTE_1_PULSE_SHAPER_DISABLE 1 +#define TDA18272_OFFST_AGCK_BYTE_1_AGCK_STEP 2 +#define TDA18272_WIDTH_AGCK_BYTE_1_AGCK_STEP 2 +#define TDA18272_OFFST_AGCK_BYTE_1_AGCK_MODE 0 +#define TDA18272_WIDTH_AGCK_BYTE_1_AGCK_MODE 2 + +#define TDA18272_RFAGC_BYTE_1 0x0f +#define TDA18272_OFFST_RFAGC_BYTE_1_PD_RFAGC_ADAPT 7 +#define TDA18272_WIDTH_RFAGC_BYTE_1_PD_RFAGC_ADAPT 1 +#define TDA18272_OFFST_RFAGC_BYTE_1_RFAGC_ADAPT_TOP 5 +#define TDA18272_WIDTH_RFAGC_BYTE_1_RFAGC_ADAPT_TOP 2 +#define TDA18272_OFFST_RFAGC_BYTE_1_RF_ATTEN_3DB 3 +#define TDA18272_WIDTH_RFAGC_BYTE_1_RF_ATTEN_3DB 1 +#define TDA18272_OFFST_RFAGC_BYTE_1_AGC3_TOP 0 +#define TDA18272_WIDTH_RFAGC_BYTE_1_AGC3_TOP 3 + +#define TDA18272_IRMIXER_BYTE_1 0x10 +#define TDA18272_OFFST_IRMIXER_BYTE_1_AGC4_TOP 0 +#define TDA18272_WIDTH_IRMIXER_BYTE_1_AGC4_TOP 4 + +#define TDA18272_AGC5_BYTE_1 0x11 +#define TDA18272_OFFST_AGC5_BYTE_1_AGC5_TOP 0 +#define TDA18272_WIDTH_AGC5_BYTE_1_AGC5_TOP 4 +#define TDA18272_OFFST_AGC5_BYTE_1_AGC5_HPF 4 +#define TDA18272_WIDTH_AGC5_BYTE_1_AGC5_HPF 1 +#define TDA18272_OFFST_AGC5_BYTE_1_AGCs_DO_STEP_ASYM 5 +#define TDA18272_WIDTH_AGC5_BYTE_1_AGCs_DO_STEP_ASYM 2 + + +#define TDA18272_IFAGC 0x12 +#define TDA18272_OFFST_IFAGC_IF_LEVEL 0 +#define TDA18272_WIDTH_IFAGC_IF_LEVEL 3 + +#define TDA18272_IF_BYTE_1 0x13 +#define TDA18272_OFFST_IF_BYTE_1_IF_HP_FC 6 +#define TDA18272_WIDTH_IF_BYTE_1_IF_HP_FC 2 +#define TDA18272_OFFST_IF_BYTE_1_IF_NOTCH 5 +#define TDA18272_WIDTH_IF_BYTE_1_IF_NOTCH 1 +#define TDA18272_OFFST_IF_BYTE_1_LP_FC_OFFSET 3 +#define TDA18272_WIDTH_IF_BYTE_1_LP_FC_OFFSET 2 +#define TDA18272_OFFST_IF_BYTE_1_LP_FC 0 +#define TDA18272_WIDTH_IF_BYTE_1_LP_FC 3 + +#define TDA18272_REFERENCE 0x14 +#define TDA18272_OFFST_REFERENCE_XTOUT 0 +#define TDA18272_WIDTH_REFERENCE_XTOUT 2 +#define TDA18272_OFFST_REFERENCE_DIGITAL_CLOCK 6 +#define TDA18272_WIDTH_REFERENCE_DIGITAL_CLOCK 1 + +#define TDA18272_IF_FREQUENCY 0x15 +#define TDA18272_OFFST_IF_FREQUENCY_IF_FREQ 0 +#define TDA18272_WIDTH_IF_FREQUENCY_IF_FREQ 8 + +#define TDA18272_RF_FREQUENCY_BYTE_1 0x16 +#define TDA18272_OFFST_RF_FREQUENCY_BYTE_1_RF_FREQ 0 +#define TDA18272_WIDTH_RF_FREQUENCY_BYTE_1_RF_FREQ 4 + +#define TDA18272_RF_FREQUENCY_BYTE_2 0x17 +#define TDA18272_OFFST_RF_FREQUENCY_BYTE_2_RF_FREQ 0 +#define TDA18272_WIDTH_RF_FREQUENCY_BYTE_2_RF_FREQ 8 + +#define TDA18272_RF_FREQUENCY_BYTE_3 0x18 +#define TDA18272_OFFST_RF_FREQUENCY_BYTE_3_RF_FREQ 0 +#define TDA18272_WIDTH_RF_FREQUENCY_BYTE_3_RF_FREQ 8 + +#define TDA18272_MSM_BYTE_1 0x19 +#define TDA18272_OFFST_MSM_BYTE_1_POWER_MEAS 7 +#define TDA18272_WIDTH_MSM_BYTE_1_POWER_MEAS 1 +#define TDA18272_OFFST_MSM_BYTE_1_RF_CAL_AV 6 +#define TDA18272_WIDTH_MSM_BYTE_1_RF_CAL_AV 1 +#define TDA18272_OFFST_MSM_BYTE_1_RF_CAL 5 +#define TDA18272_WIDTH_MSM_BYTE_1_RF_CAL 1 +#define TDA18272_OFFST_MSM_BYTE_1_IR_CAL 3 +#define TDA18272_WIDTH_MSM_BYTE_1_IR_CAL 2 +#define TDA18272_OFFST_MSM_BYTE_1_RC_CAL 1 +#define TDA18272_WIDTH_MSM_BYTE_1_RC_CAL 1 +#define TDA18272_OFFST_MSM_BYTE_1_CALC_PLL 0 +#define TDA18272_WIDTH_MSM_BYTE_1_CALC_PLL 1 + +#define TDA18272_MSM_BYTE_2 0x1a +#define TDA18272_OFFST_MSM_BYTE_2_MSM_LAUNCH 0 +#define TDA18272_WIDTH_MSM_BYTE_2_MSM_LAUNCH 1 + +#define TDA18272_PSM_BYTE_1 0x1b +#define TDA18272_OFFST_PSM_BYTE_1_PSM_AGC1 6 +#define TDA18272_WIDTH_PSM_BYTE_1_PSM_AGC1 2 +#define TDA18272_OFFST_PSM_BYTE_1_PSM_STOB 5 +#define TDA18272_WIDTH_PSM_BYTE_1_PSM_STOB 1 +#define TDA18272_OFFST_PSM_BYTE_1_PSMRFPOLY 4 +#define TDA18272_WIDTH_PSM_BYTE_1_PSMRFPOLY 1 +#define TDA18272_OFFST_PSM_BYTE_1_PSM_MIXER 3 +#define TDA18272_WIDTH_PSM_BYTE_1_PSM_MIXER 1 +#define TDA18272_OFFST_PSM_BYTE_1_PSM_IFPOLY 2 +#define TDA18272_WIDTH_PSM_BYTE_1_PSM_IFPOLY 1 +#define TDA18272_OFFST_PSM_BYTE_1_PSM_LODRIVER 0 +#define TDA18272_WIDTH_PSM_BYTE_1_PSM_LODRIVER 2 + +#define TDA18272_DCC_BYTE_1 0x1c +#define TDA18272_OFFST_DCC_BYTE_1_DCC_BYPASS 7 +#define TDA18272_WIDTH_DCC_BYTE_1_DCC_BYPASS 1 +#define TDA18272_OFFST_DCC_BYTE_1_DCC_SLOW 6 +#define TDA18272_WIDTH_DCC_BYTE_1_DCC_SLOW 1 +#define TDA18272_OFFST_DCC_BYTE_1_DCC_PSM 5 +#define TDA18272_WIDTH_DCC_BYTE_1_DCC_PSM 1 +#define TDA18272_OFFST_DCC_BYTE_1_UNUSED_I0_D0 0 +#define TDA18272_WIDTH_DCC_BYTE_1_UNUSED_I0_D0 5 + +#define TDA18272_FLO_MAX_BYTE 0x1d +#define TDA18272_OFFST_FLO_MAX_BYTE_UNUSED_I0_D0 6 +#define TDA18272_WIDTH_FLO_MAX_BYTE_UNUSED_I0_D0 2 +#define TDA18272_OFFST_FLO_MAX_BYTE_FMAX_LO 0 +#define TDA18272_WIDTH_FLO_MAX_BYTE_FMAX_LO 6 + +#define TDA18272_IR_CAL_BYTE_1 0x1e +#define TDA18272_OFFST_IR_CAL_BYTE_1_IR_LOOP 6 +#define TDA18272_WIDTH_IR_CAL_BYTE_1_IR_LOOP 2 +#define TDA18272_OFFST_IR_CAL_BYTE_1_IR_TARGET 3 +#define TDA18272_WIDTH_IR_CAL_BYTE_1_IR_TARGET 3 +#define TDA18272_OFFST_IR_CAL_BYTE_1_IR_GSTEP 0 +#define TDA18272_WIDTH_IR_CAL_BYTE_1_IR_GSTEP 3 + +#define TDA18272_IR_CAL_BYTE_2 0x1f +#define TDA18272_OFFST_IR_CAL_BYTE_2_IR_CORR_BOOST 7 +#define TDA18272_WIDTH_IR_CAL_BYTE_2_IR_CORR_BOOST 1 +#define TDA18272_OFFST_IR_CAL_BYTE_2_IR_FREQLOW_SEL 6 +#define TDA18272_WIDTH_IR_CAL_BYTE_2_IR_FREQLOW_SEL 1 +#define TDA18272_OFFST_IR_CAL_BYTE_2_IR_MODE_RAM_STORE 5 +#define TDA18272_WIDTH_IR_CAL_BYTE_2_IR_MODE_RAM_STORE 1 +#define TDA18272_OFFST_IR_CAL_BYTE_2_IR_FREQLOW 0 +#define TDA18272_WIDTH_IR_CAL_BYTE_2_IR_FREQLOW 5 + +#define TDA18272_IR_CAL_BYTE_3 0x20 +#define TDA18272_OFFST_IR_CAL_BYTE_3_UNUSED_I0_D0 5 +#define TDA18272_WIDTH_IR_CAL_BYTE_3_UNUSED_I0_D0 3 +#define TDA18272_OFFST_IR_CAL_BYTE_3_IR_FREQMID 0 +#define TDA18272_WIDTH_IR_CAL_BYTE_3_IR_FREQMID 5 + +#define TDA18272_IR_CAL_BYTE_4 0x21 +#define TDA18272_OFFST_IR_CAL_BYTE_4_UNUSED_I0_D0 6 +#define TDA18272_WIDTH_IR_CAL_BYTE_4_UNUSED_I0_D0 2 +#define TDA18272_OFFST_IR_CAL_BYTE_4_COARSE_IR_FREQHIGH 5 +#define TDA18272_WIDTH_IR_CAL_BYTE_4_COARSE_IR_FREQHIGH 1 +#define TDA18272_OFFST_IR_CAL_BYTE_4_IR_FREQHIGH 0 +#define TDA18272_WIDTH_IR_CAL_BYTE_4_IR_FREQHIGH 5 + +#define TDA18272_VSYNC_MGT 0x22 +#define TDA18272_OFFST_VSYNC_MGT_PD_VSYNC_MGT 7 +#define TDA18272_WIDTH_VSYNC_MGT_PD_VSYNC_MGT 1 +#define TDA18272_OFFST_VSYNC_MGT_PD_OVLD 6 +#define TDA18272_WIDTH_VSYNC_MGT_PD_OVLD 1 +#define TDA18272_OFFST_VSYNC_MGT_PD_UDLD 5 +#define TDA18272_WIDTH_VSYNC_MGT_PD_UDLD 1 +#define TDA18272_OFFST_VSYNC_MGT_AGC_OVLD_TOP 2 +#define TDA18272_WIDTH_VSYNC_MGT_AGC_OVLD_TOP 3 +#define TDA18272_OFFST_VSYNC_MGT_AGC_OVLD_TIMER 0 +#define TDA18272_WIDTH_VSYNC_MGT_AGC_OVLD_TIMER 2 + +#define TDA18272_IRMIXER_BYTE_2 0x23 +#define TDA18272_OFFST_IRMIXER_BYTE_2_HI_PASS 1 +#define TDA18272_WIDTH_IRMIXER_BYTE_2_HI_PASS 1 +#define TDA18272_OFFST_IRMIXER_BYTE_2_DC_NOTCH 0 +#define TDA18272_WIDTH_IRMIXER_BYTE_2_DC_NOTCH 1 + +#define TDA18272_AGC1_BYTE_2 0x24 +#define TDA18272_OFFST_AGC1_BYTE_2_AGC1_LOOP_OFF 7 +#define TDA18272_WIDTH_AGC1_BYTE_2_AGC1_LOOP_OFF 1 +#define TDA18272_OFFST_AGC1_BYTE_2_AGC1_DO_STEP 5 +#define TDA18272_WIDTH_AGC1_BYTE_2_AGC1_DO_STEP 2 +#define TDA18272_OFFST_AGC1_BYTE_2_FORCE_AGC1_GAIN 4 +#define TDA18272_WIDTH_AGC1_BYTE_2_FORCE_AGC1_GAIN 1 +#define TDA18272_OFFST_AGC1_BYTE_2_AGC1_GAIN 0 +#define TDA18272_WIDTH_AGC1_BYTE_2_AGC1_GAIN 4 + +#define TDA18272_AGC5_BYTE_2 0x25 +#define TDA18272_OFFST_AGC5_BYTE_2_AGC5_LOOP_OFF 7 +#define TDA18272_WIDTH_AGC5_BYTE_2_AGC5_LOOP_OFF 1 +#define TDA18272_OFFST_AGC5_BYTE_2_AGC5_DO_STEP 5 +#define TDA18272_WIDTH_AGC5_BYTE_2_AGC5_DO_STEP 2 +#define TDA18272_OFFST_AGC5_BYTE_2_UNUSED_I1_D0 4 +#define TDA18272_WIDTH_AGC5_BYTE_2_UNUSED_I1_D0 1 +#define TDA18272_OFFST_AGC5_BYTE_2_FORCE_AGC5_GAIN 3 +#define TDA18272_WIDTH_AGC5_BYTE_2_FORCE_AGC5_GAIN 1 +#define TDA18272_OFFST_AGC5_BYTE_2_UNUSED_I0_D0 2 +#define TDA18272_WIDTH_AGC5_BYTE_2_UNUSED_I0_D0 1 +#define TDA18272_OFFST_AGC5_BYTE_2_AGC5_GAIN 0 +#define TDA18272_WIDTH_AGC5_BYTE_2_AGC5_GAIN 2 + +#define TDA18272_RF_CAL_BYTE_1 0x26 +#define TDA18272_OFFST_RF_CAL_BYTE_1_RFCAL_OFFSET_CPROG0 6 +#define TDA18272_WIDTH_RF_CAL_BYTE_1_RFCAL_OFFSET_CPROG0 2 +#define TDA18272_OFFST_RF_CAL_BYTE_1_RFCAL_FREQ0 4 +#define TDA18272_WIDTH_RF_CAL_BYTE_1_RFCAL_FREQ0 2 +#define TDA18272_OFFST_RF_CAL_BYTE_1_RFCAL_OFFSET_CPROG1 2 +#define TDA18272_WIDTH_RF_CAL_BYTE_1_RFCAL_OFFSET_CPROG1 2 +#define TDA18272_OFFST_RF_CAL_BYTE_1_RFCAL_FREQ1 0 +#define TDA18272_WIDTH_RF_CAL_BYTE_1_RFCAL_FREQ1 2 + +#define TDA18272_RF_CAL_BYTE_2 0x27 +#define TDA18272_OFFST_RF_CAL_BYTE_2_RFCAL_OFFSET_CPROG2 6 +#define TDA18272_WIDTH_RF_CAL_BYTE_2_RFCAL_OFFSET_CPROG2 2 +#define TDA18272_OFFST_RF_CAL_BYTE_2_RFCAL_FREQ2 4 +#define TDA18272_WIDTH_RF_CAL_BYTE_2_RFCAL_FREQ2 2 +#define TDA18272_OFFST_RF_CAL_BYTE_2_RFCAL_OFFSET_CPROG3 2 +#define TDA18272_WIDTH_RF_CAL_BYTE_2_RFCAL_OFFSET_CPROG3 2 +#define TDA18272_OFFST_RF_CAL_BYTE_2_RFCAL_FREQ3 0 +#define TDA18272_WIDTH_RF_CAL_BYTE_2_RFCAL_FREQ3 2 + +#define TDA18272_RF_CAL_BYTE_3 0x28 +#define TDA18272_OFFST_RF_CAL_BYTE_3_RFCAL_OFFSET_CPROG4 6 +#define TDA18272_WIDTH_RF_CAL_BYTE_3_RFCAL_OFFSET_CPROG4 2 +#define TDA18272_OFFST_RF_CAL_BYTE_3_RFCAL_FREQ4 4 +#define TDA18272_WIDTH_RF_CAL_BYTE_3_RFCAL_FREQ4 2 +#define TDA18272_OFFST_RF_CAL_BYTE_3_RFCAL_OFFSET_CPROG5 2 +#define TDA18272_WIDTH_RF_CAL_BYTE_3_RFCAL_OFFSET_CPROG5 2 +#define TDA18272_OFFST_RF_CAL_BYTE_3_RFCAL_FREQ5 0 +#define TDA18272_WIDTH_RF_CAL_BYTE_3_RFCAL_FREQ5 2 + +#define TDA18272_RF_CAL_BYTE_4 0x29 +#define TDA18272_OFFST_RF_CAL_BYTE_4_RFCAL_OFFSET_CPROG6 6 +#define TDA18272_WIDTH_RF_CAL_BYTE_4_RFCAL_OFFSET_CPROG6 2 +#define TDA18272_OFFST_RF_CAL_BYTE_4_RFCAL_FREQ6 4 +#define TDA18272_WIDTH_RF_CAL_BYTE_4_RFCAL_FREQ6 2 +#define TDA18272_OFFST_RF_CAL_BYTE_4_RFCAL_OFFSET_CPROG7 2 +#define TDA18272_WIDTH_RF_CAL_BYTE_4_RFCAL_OFFSET_CPROG7 2 +#define TDA18272_OFFST_RF_CAL_BYTE_4_RFCAL_FREQ7 0 +#define TDA18272_WIDTH_RF_CAL_BYTE_4_RFCAL_FREQ7 2 + +#define TDA18272_RF_CAL_BYTE_5 0x2a +#define TDA18272_OFFST_RF_CAL_BYTE_5_RFCAL_OFFSET_CPROG 6 +#define TDA18272_WIDTH_RF_CAL_BYTE_5_RFCAL_OFFSET_CPROG8 2 +#define TDA18272_OFFST_RF_CAL_BYTE_5_RFCAL_FREQ8 4 +#define TDA18272_WIDTH_RF_CAL_BYTE_5_RFCAL_FREQ8 2 +#define TDA18272_OFFST_RF_CAL_BYTE_5_RFCAL_OFFSET_CPROG9 2 +#define TDA18272_WIDTH_RF_CAL_BYTE_5_RFCAL_OFFSET_CPROG9 2 +#define TDA18272_OFFST_RF_CAL_BYTE_5_RFCAL_FREQ9 0 +#define TDA18272_WIDTH_RF_CAL_BYTE_5_RFCAL_FREQ9 2 + +#define TDA18272_RF_CAL_BYTE_6 0x2b +#define TDA18272_OFFST_RF_CAL_BYTE_6_RFCAL_OFFSET_CPROG10 6 +#define TDA18272_WIDTH_RF_CAL_BYTE_6_RFCAL_OFFSET_CPROG10 2 +#define TDA18272_OFFST_RF_CAL_BYTE_6_RFCAL_FREQ10 4 +#define TDA18272_WIDTH_RF_CAL_BYTE_6_RFCAL_FREQ10 2 +#define TDA18272_OFFST_RF_CAL_BYTE_6_RFCAL_OFFSET_CPROG11 2 +#define TDA18272_WIDTH_RF_CAL_BYTE_6_RFCAL_OFFSET_CPROG11 2 +#define TDA18272_OFFST_RF_CAL_BYTE_6_RFCAL_FREQ11 0 +#define TDA18272_WIDTH_RF_CAL_BYTE_6_RFCAL_FREQ11 2 + +#define TDA18272_RF_FILTER_BYTE_1 0x2c +#define TDA18272_OFFST_RF_FILTER_BYTE_1_RF_FILTER_BYPASS 7 +#define TDA18272_WIDTH_RF_FILTER_BYTE_1_RF_FILTER_BYPASS 1 +#define TDA18272_OFFST_RF_FILTER_BYTE_1_UNUSED_I0_D0 6 +#define TDA18272_WIDTH_RF_FILTER_BYTE_1_UNUSED_I0_D0 1 +#define TDA18272_OFFST_RF_FILTER_BYTE_1_AGC2_LOOP_OFF 5 +#define TDA18272_WIDTH_RF_FILTER_BYTE_1_AGC2_LOOP_OFF 1 +#define TDA18272_OFFST_RF_FILTER_BYTE_1_FORCE_AGC2_GAIN 4 +#define TDA18272_WIDTH_RF_FILTER_BYTE_1_FORCE_AGC2_GAIN 1 +#define TDA18272_OFFST_RF_FILTER_BYTE_1_RF_FILTER_GV 2 +#define TDA18272_WIDTH_RF_FILTER_BYTE_1_RF_FILTER_GV 2 +#define TDA18272_OFFST_RF_FILTER_BYTE_1_RF_FILTER_BAND 0 +#define TDA18272_WIDTH_RF_FILTER_BYTE_1_RF_FILTER_BAND 2 + +#define TDA18272_RF_FILTER_BYTE_2 0x2d +#define TDA18272_OFFST_RF_FILTER_BYTE_2_RF_FILTER_CAP 0 +#define TDA18272_WIDTH_RF_FILTER_BYTE_2_RF_FILTER_CAP 8 + +#define TDA18272_RF_FILTER_BYTE_3 0x2e +#define TDA18272_OFFST_RF_FILTER_BYTE_3_AGC2_DO_STEP 6 +#define TDA18272_WIDTH_RF_FILTER_BYTE_3_AGC2_DO_STEP 2 +#define TDA18272_OFFST_RF_FILTER_BYTE_3_GAIN_TAPER 0 +#define TDA18272_WIDTH_RF_FILTER_BYTE_3_GAIN_TAPER 6 + +#define TDA18272_RF_BANDPASS_FILTER 0x2f +#define TDA18272_OFFST_RF_BANDPASS_FILTER_RF_BPF_BYPASS 7 +#define TDA18272_WIDTH_RF_BANDPASS_FILTER_RF_BPF_BYPASS 1 +#define TDA18272_OFFST_RF_BANDPASS_FILTER_UNUSED_I0_D0 3 +#define TDA18272_WIDTH_RF_BANDPASS_FILTER_UNUSED_I0_D0 4 +#define TDA18272_OFFST_RF_BANDPASS_FILTER_RF_BPF 0 +#define TDA18272_WIDTH_RF_BANDPASS_FILTER_RF_BPF 3 + +#define TDA18272_CP_CURRENT 0x30 +#define TDA18272_OFFST_CP_CURRENT_UNUSED_I0_D0 7 +#define TDA18272_WIDTH_CP_CURRENT_UNUSED_I0_D0 1 +#define TDA18272_OFFST_CP_CURRENT_N_CP_CURRENT 0 +#define TDA18272_WIDTH_CP_CURRENT_N_CP_CURRENT 7 + +#define TDA18272_AGC_DET_OUT 0x31 +#define TDA18272_OFFST_AGC_DET_OUT_UP_AGC5 7 +#define TDA18272_WIDTH_AGC_DET_OUT_UP_AGC5 1 +#define TDA18272_OFFST_AGC_DET_OUT_DO_AGC5 6 +#define TDA18272_WIDTH_AGC_DET_OUT_DO_AGC5 1 +#define TDA18272_OFFST_AGC_DET_OUT_UP_AGC4 5 +#define TDA18272_WIDTH_AGC_DET_OUT_UP_AGC4 1 +#define TDA18272_OFFST_AGC_DET_OUT_DO_AGC4 4 +#define TDA18272_WIDTH_AGC_DET_OUT_DO_AGC4 1 +#define TDA18272_OFFST_AGC_DET_OUT_UP_AGC2 3 +#define TDA18272_WIDTH_AGC_DET_OUT_UP_AGC2 1 +#define TDA18272_OFFST_AGC_DET_OUT_DO_AGC2 2 +#define TDA18272_WIDTH_AGC_DET_OUT_DO_AGC2 1 +#define TDA18272_OFFST_AGC_DET_OUT_UP_AGC1 1 +#define TDA18272_WIDTH_AGC_DET_OUT_UP_AGC1 1 +#define TDA18272_OFFST_AGC_DET_OUT_DO_AGC1 0 +#define TDA18272_WIDTH_AGC_DET_OUT_DO_AGC1 1 + +#define TDA18272_RF_AGC_GAIN_BYTE_1 0x32 +#define TDA18272_OFFST_RF_AGC_GAIN_BYTE_1_RF_FILTER_GAIN 4 +#define TDA18272_WIDTH_RF_AGC_GAIN_BYTE_1_RF_FILTER_GAIN 2 +#define TDA18272_OFFST_RF_AGC_GAIN_BYTE_1_LNA_GAIN 0 +#define TDA18272_WIDTH_RF_AGC_GAIN_BYTE_1_LNA_GAIN 4 + +#define TDA18272_RF_AGC_GAIN_BYTE_2 0x33 +#define TDA18272_OFFST_RF_AGC_GAIN_BYTE_2_TOP_AGC3_READ 0 +#define TDA18272_WIDTH_RF_AGC_GAIN_BYTE_2_TOP_AGC3_READ 3 + +#define TDA18272_IF_AGC_GAIN 0x34 +#define TDA18272_OFFST_IF_AGC_GAIN_LPF_GAIN 3 +#define TDA18272_WIDTH_IF_AGC_GAIN_LPF_GAIN 2 +#define TDA18272_OFFST_IF_AGC_GAIN_IR_MIXER 0 +#define TDA18272_WIDTH_IF_AGC_GAIN_IR_MIXER 3 + +#define TDA18272_POWER_BYTE_1 0x35 +#define TDA18272_OFFST_POWER_BYTE_1_RSSI 0 +#define TDA18272_WIDTH_POWER_BYTE_1_RSSI 8 + +#define TDA18272_POWER_BYTE_2 0x36 +#define TDA18272_OFFST_POWER_BYTE_2_UNUSED_I1_D0 6 +#define TDA18272_WIDTH_POWER_BYTE_2_UNUSED_I1_D0 2 +#define TDA18272_OFFST_POWER_BYTE_2_RSSI_AV 5 +#define TDA18272_WIDTH_POWER_BYTE_2_RSSI_AV 1 +#define TDA18272_OFFST_POWER_BYTE_2_UNUSED_I0_D0 4 +#define TDA18272_WIDTH_POWER_BYTE_2_UNUSED_I0_D0 1 +#define TDA18272_OFFST_POWER_BYTE_2_RSSI_CAP_RESET_EN 3 +#define TDA18272_WIDTH_POWER_BYTE_2_RSSI_CAP_RESET_EN 1 +#define TDA18272_OFFST_POWER_BYTE_2_RSSI_CAP_VAL 2 +#define TDA18272_WIDTH_POWER_BYTE_2_RSSI_CAP_VAL 1 +#define TDA18272_OFFST_POWER_BYTE_2_RSSI_CK_SPEED 1 +#define TDA18272_WIDTH_POWER_BYTE_2_RSSI_CK_SPEED 1 +#define TDA18272_OFFST_POWER_BYTE_2_RSSI_DICHO_NOT 0 +#define TDA18272_WIDTH_POWER_BYTE_2_RSSI_DICHO_NOT 1 + +#define TDA18272_MISC_BYTE_1 0x37 +#define TDA18272_OFFST_MISC_BYTE_1_IRQ_POLARITY 0 +#define TDA18272_WIDTH_MISC_BYTE_1_IRQ_POLARITY 1 + +#define TDA18272_RF_CAL_LOG_1 0x38 +#define TDA18272_OFFST_RF_CAL_LOG_1 0 +#define TDA18272_WIDTH_RF_CAL_LOG_1 8 + +#define TDA18272_RF_CAL_LOG_2 0x39 +#define TDA18272_OFFST_RF_CAL_LOG_2 0 +#define TDA18272_WIDTH_RF_CAL_LOG_2 8 + +#define TDA18272_RF_CAL_LOG_3 0x3a +#define TDA18272_OFFST_RF_CAL_LOG_3 0 +#define TDA18272_WIDTH_RF_CAL_LOG_3 8 + +#define TDA18272_RF_CAL_LOG_4 0x3b +#define TDA18272_OFFST_RF_CAL_LOG_4 0 +#define TDA18272_WIDTH_RF_CAL_LOG_4 8 + +#define TDA18272_RF_CAL_LOG_5 0x3c +#define TDA18272_OFFST_RF_CAL_LOG_5 0 +#define TDA18272_WIDTH_RF_CAL_LOG_5 8 + +#define TDA18272_RF_CAL_LOG_6 0x3d +#define TDA18272_OFFST_RF_CAL_LOG_6 0 +#define TDA18272_WIDTH_RF_CAL_LOG_6 8 + +#define TDA18272_RF_CAL_LOG_7 0x3e +#define TDA18272_OFFST_RF_CAL_LOG_7 0 +#define TDA18272_WIDTH_RF_CAL_LOG_7 8 + +#define TDA18272_RF_CAL_LOG_8 0x3f +#define TDA18272_OFFST_RF_CAL_LOG_8 0 +#define TDA18272_WIDTH_RF_CAL_LOG_8 8 + +#define TDA18272_RF_CAL_LOG_9 0x40 +#define TDA18272_OFFST_RF_CAL_LOG_9 0 +#define TDA18272_WIDTH_RF_CAL_LOG_9 8 + +#define TDA18272_RF_CAL_LOG_10 0x41 +#define TDA18272_OFFST_RF_CAL_LOG_10 0 +#define TDA18272_WIDTH_RF_CAL_LOG_10 8 + +#define TDA18272_RF_CAL_LOG_11 0x42 +#define TDA18272_OFFST_RF_CAL_LOG_11 0 +#define TDA18272_WIDTH_RF_CAL_LOG_11 8 + +#define TDA18272_RF_CAL_LOG_12 0x43 +#define TDA18272_OFFST_RF_CAL_LOG_12 0 +#define TDA18272_WIDTH_RF_CAL_LOG_12 8 + +#endif /* __TDA18272_REG_H */ diff --git a/drivers/media/usb/cx231xx/Kconfig b/drivers/media/usb/cx231xx/Kconfig index 0cced3e5b040..f08f85a61e9b 100644 --- a/drivers/media/usb/cx231xx/Kconfig +++ b/drivers/media/usb/cx231xx/Kconfig @@ -45,6 +45,7 @@ config VIDEO_CX231XX_DVB select VIDEOBUF_DVB select MEDIA_TUNER_XC5000 if MEDIA_SUBDRV_AUTOSELECT select MEDIA_TUNER_TDA18271 if MEDIA_SUBDRV_AUTOSELECT + select MEDIA_TUNER_TDA18272 if MEDIA_SUBDRV_AUTOSELECT select DVB_MB86A20S if MEDIA_SUBDRV_AUTOSELECT select DVB_LGDT3305 if MEDIA_SUBDRV_AUTOSELECT select DVB_LGDT3306A if MEDIA_SUBDRV_AUTOSELECT diff --git a/drivers/media/usb/cx231xx/cx231xx-avcore.c b/drivers/media/usb/cx231xx/cx231xx-avcore.c index 2f52d66b4dae..4914521446e7 100644 --- a/drivers/media/usb/cx231xx/cx231xx-avcore.c +++ b/drivers/media/usb/cx231xx/cx231xx-avcore.c @@ -2293,6 +2293,8 @@ int cx231xx_set_power_mode(struct cx231xx *dev, enum AV_MODE mode) case POLARIS_AVMODE_ANALOGT_TV: tmp |= PWR_DEMOD_EN; + if (CX231XX_BOARD_AVERMEDIA_H837B == dev->model) + tmp &= ~PWR_DEMOD_EN; value[0] = (u8) tmp; value[1] = (u8) (tmp >> 8); value[2] = (u8) (tmp >> 16); @@ -2396,8 +2398,19 @@ int cx231xx_set_power_mode(struct cx231xx *dev, enum AV_MODE mode) status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, PWR_CTL_EN, value, 4); msleep(PWR_SLEEP_INTERVAL); - - if (!(tmp & PWR_DEMOD_EN)) { + if (is_model_avermedia_h837_series(dev->model)) { + if (CX231XX_BOARD_AVERMEDIA_H837B == dev->model) + tmp |= PWR_DEMOD_EN; + else + tmp &= ~PWR_DEMOD_EN; + value[0] = (u8) tmp; + value[1] = (u8) (tmp >> 8); + value[2] = (u8) (tmp >> 16); + value[3] = (u8) (tmp >> 24); + status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, + PWR_CTL_EN, value, 4); + msleep(5 * PWR_SLEEP_INTERVAL); + } else if (!(tmp & PWR_DEMOD_EN)) { tmp |= PWR_DEMOD_EN; value[0] = (u8) tmp; value[1] = (u8) (tmp >> 8); @@ -2418,6 +2431,21 @@ int cx231xx_set_power_mode(struct cx231xx *dev, enum AV_MODE mode) } break; + case POLARIS_AVMODE_DEFAULT: + if (is_model_avermedia_h837_series(dev->model)) { + tmp &= ~PWR_MODE_MASK; + if (CX231XX_BOARD_AVERMEDIA_H837A == dev->model || + CX231XX_BOARD_AVERMEDIA_H837M == dev->model) + tmp |= PWR_DEMOD_EN; + value[0] = (u8) tmp; + value[1] = (u8) (tmp >> 8); + value[2] = (u8) (tmp >> 16); + value[3] = (u8) (tmp >> 24); + cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, PWR_CTL_EN, value, 4); + msleep(PWR_SLEEP_INTERVAL); + return 0; + } + default: break; } @@ -2592,8 +2620,11 @@ int cx231xx_initialize_stream_xfer(struct cx231xx *dev, u32 media_type) dev_dbg(dev->dev, "%s: BDA\n", __func__); status = cx231xx_mode_register(dev, TS_MODE_REG, 0x101); - status = cx231xx_mode_register(dev, - TS1_CFG_REG, 0x010); + if (is_model_avermedia_h837_series(dev->model)) { + status = cx231xx_mode_register(dev, TS1_CFG_REG, 0x408); + } else { + status = cx231xx_mode_register(dev, TS1_CFG_REG, 0x010); + } } break; diff --git a/drivers/media/usb/cx231xx/cx231xx-cards.c b/drivers/media/usb/cx231xx/cx231xx-cards.c index 69156affd0ae..73d9689eb3ec 100644 --- a/drivers/media/usb/cx231xx/cx231xx-cards.c +++ b/drivers/media/usb/cx231xx/cx231xx-cards.c @@ -841,6 +841,109 @@ struct cx231xx_board cx231xx_boards[] = { .gpio = NULL, } }, }, + [CX231XX_BOARD_AVERMEDIA_H837A] = { + .name = "AVerMedia H837-A USB Hybrid ATSC/QAM", + .tuner_type = TUNER_ABSENT, + .tuner_addr = 0x60, + .tuner_sif_gpio = 0x05, + .demod_xfer_mode = 0, + .ctl_pin_status_mask = 0xFFFFFFC4, + .agc_analog_digital_select_gpio = 0x1c, + .gpio_pin_status_mask = 0x4001000, + .tuner_i2c_master = 2, + .demod_i2c_master = 1, + .has_dvb = 1, + .norm = V4L2_STD_NTSC, + + .input = {{ + .type = CX231XX_VMUX_TELEVISION, + .vmux = CX231XX_VIN_3_1, + .amux = CX231XX_AMUX_VIDEO, + .gpio = 0, + }, { + .type = CX231XX_VMUX_COMPOSITE1, + .vmux = CX231XX_VIN_2_1, + .amux = CX231XX_AMUX_LINE_IN, + .gpio = 0, + }, { + .type = CX231XX_VMUX_SVIDEO, + .vmux = CX231XX_VIN_1_1 | + (CX231XX_VIN_1_2 << 8) | + CX25840_SVIDEO_ON, + .amux = CX231XX_AMUX_LINE_IN, + .gpio = 0, + } + }, + }, + [CX231XX_BOARD_AVERMEDIA_H837B] = { + .name = "AVerMedia H837-B USB Hybrid ATSC/QAM", + .tuner_type = TUNER_ABSENT, + .tuner_addr = 0x60, + .tuner_sif_gpio = 0x05, + .demod_xfer_mode = 0, + .ctl_pin_status_mask = 0xFFFFFFC4, + .agc_analog_digital_select_gpio = 0x1c, + .gpio_pin_status_mask = 0x4001000, + .tuner_i2c_master = 2, + .demod_i2c_master = 1, + .has_dvb = 1, + .norm = V4L2_STD_NTSC, + + .input = {{ + .type = CX231XX_VMUX_TELEVISION, + .vmux = CX231XX_VIN_3_1, + .amux = CX231XX_AMUX_VIDEO, + .gpio = 0, + }, { + .type = CX231XX_VMUX_COMPOSITE1, + .vmux = CX231XX_VIN_2_1, + .amux = CX231XX_AMUX_LINE_IN, + .gpio = 0, + }, { + .type = CX231XX_VMUX_SVIDEO, + .vmux = CX231XX_VIN_1_1 | + (CX231XX_VIN_1_2 << 8) | + CX25840_SVIDEO_ON, + .amux = CX231XX_AMUX_LINE_IN, + .gpio = 0, + } + }, + }, + [CX231XX_BOARD_AVERMEDIA_H837M] = { + .name = "AVerMedia H837-M USB Hybrid ATSC/QAM", + .tuner_type = TUNER_ABSENT, + .tuner_addr = 0x60, + .tuner_sif_gpio = 0x05, + .demod_xfer_mode = 0, + .ctl_pin_status_mask = 0xFFFFFFC4, + .agc_analog_digital_select_gpio = 0x1c, + .gpio_pin_status_mask = 0x4001000, + .tuner_i2c_master = 2, + .demod_i2c_master = 1, + .has_dvb = 1, + .norm = V4L2_STD_NTSC, + + .input = {{ + .type = CX231XX_VMUX_TELEVISION, + .vmux = CX231XX_VIN_3_1, + .amux = CX231XX_AMUX_VIDEO, + .gpio = 0, + }, { + .type = CX231XX_VMUX_COMPOSITE1, + .vmux = CX231XX_VIN_2_1, + .amux = CX231XX_AMUX_LINE_IN, + .gpio = 0, + }, { + .type = CX231XX_VMUX_SVIDEO, + .vmux = CX231XX_VIN_1_1 | + (CX231XX_VIN_1_2 << 8) | + CX25840_SVIDEO_ON, + .amux = CX231XX_AMUX_LINE_IN, + .gpio = 0, + } + }, + }, + }; const unsigned int cx231xx_bcount = ARRAY_SIZE(cx231xx_boards); @@ -911,6 +1014,12 @@ struct usb_device_id cx231xx_id_table[] = { .driver_info = CX231XX_BOARD_OTG102}, {USB_DEVICE(USB_VID_TERRATEC, 0x00a6), .driver_info = CX231XX_BOARD_TERRATEC_GRABBY}, + {USB_DEVICE(0x07ca, 0x0837), + .driver_info = CX231XX_BOARD_AVERMEDIA_H837A}, + {USB_DEVICE(0x07ca, 0x0837), + .driver_info = CX231XX_BOARD_AVERMEDIA_H837B}, + {USB_DEVICE(0x07ca, 0x1837), + .driver_info = CX231XX_BOARD_AVERMEDIA_H837M}, {}, }; @@ -1577,7 +1686,9 @@ static int cx231xx_usb_probe(struct usb_interface *interface, dev->gpio_dir = 0; dev->gpio_val = 0; dev->xc_fw_load_done = 0; + if (!is_model_avermedia_h837_series(dev->model)) { dev->has_alsa_audio = 1; + } dev->power_mode = -1; atomic_set(&dev->devlist_count, 0); diff --git a/drivers/media/usb/cx231xx/cx231xx-core.c b/drivers/media/usb/cx231xx/cx231xx-core.c index 71b65ab573ac..df3351ec1e3f 100644 --- a/drivers/media/usb/cx231xx/cx231xx-core.c +++ b/drivers/media/usb/cx231xx/cx231xx-core.c @@ -331,6 +331,76 @@ int cx231xx_read_ctrl_reg(struct cx231xx *dev, u8 req, u16 reg, return ret; } +int cx231xx_send_h837_vendor_cmd(struct cx231xx *dev, + struct VENDOR_REQUEST_IN *ven_req) +{ + int ret; + int pipe = 0; + int unsend_size = 0; + u8 *pdata; + + if (dev->state & DEV_DISCONNECTED) + return -ENODEV; + + if ((ven_req->wLength > URB_MAX_CTRL_SIZE)) + return -EINVAL; + + if (ven_req->direction) + pipe = usb_rcvctrlpipe(dev->udev, 0); + else + pipe = usb_sndctrlpipe(dev->udev, 0); + + /* + * If the cx23102 read more than 4 bytes with i2c bus, + * need chop to 4 byte per request + */ + if ((ven_req->wLength > 4) && (ven_req->bRequest <= VRT_GET_I2C2)) { + unsend_size = 0; + pdata = ven_req->pBuff; + + + unsend_size = ven_req->wLength; + + /* the first package */ + ven_req->wValue = ven_req->wValue & 0xFFFB; + ven_req->wValue = (ven_req->wValue & 0xFFBD) | 0x2; + ret = __usb_control_msg(dev, pipe, ven_req->bRequest, + ven_req->direction | USB_TYPE_VENDOR | USB_RECIP_DEVICE, + ven_req->wValue, ven_req->wIndex, pdata, + 0x0004, HZ); + unsend_size = unsend_size - 4; + + /* the middle package */ + ven_req->wValue = (ven_req->wValue & 0xFFBD) | 0x42; + while (unsend_size - 4 > 0) { + pdata = pdata + 4; + ret = __usb_control_msg(dev, pipe, + ven_req->bRequest, + ven_req->direction | USB_TYPE_VENDOR | USB_RECIP_DEVICE, + ven_req->wValue, ven_req->wIndex, pdata, + 0x0004, HZ); + unsend_size = unsend_size - 4; + } + + /* the last package */ + ven_req->wValue = (ven_req->wValue & 0xFFBD) | 0x40; + pdata = pdata + 4; + ret = __usb_control_msg(dev, pipe, ven_req->bRequest, + ven_req->direction | USB_TYPE_VENDOR | USB_RECIP_DEVICE, + ven_req->wValue, ven_req->wIndex, pdata, + unsend_size, HZ); + } else { + if (ven_req->bRequest <= VRT_GET_I2C2) + ven_req->wValue &= ~0x42; + ret = __usb_control_msg(dev, pipe, ven_req->bRequest, + ven_req->direction | USB_TYPE_VENDOR | USB_RECIP_DEVICE, + ven_req->wValue, ven_req->wIndex, + ven_req->pBuff, ven_req->wLength, HZ); + } + + return ret; +} + int cx231xx_send_vendor_cmd(struct cx231xx *dev, struct VENDOR_REQUEST_IN *ven_req) { @@ -339,6 +409,9 @@ int cx231xx_send_vendor_cmd(struct cx231xx *dev, int unsend_size = 0; u8 *pdata; + if (is_model_avermedia_h837_series(dev->model)) + return cx231xx_send_h837_vendor_cmd(dev, ven_req); + if (dev->state & DEV_DISCONNECTED) return -ENODEV; @@ -715,6 +788,18 @@ int cx231xx_set_mode(struct cx231xx *dev, enum cx231xx_mode set_mode) case CX231XX_BOARD_CNXT_RDU_250: errCode = cx231xx_set_agc_analog_digital_mux_select(dev, 0); break; + case CX231XX_BOARD_AVERMEDIA_H837M: + case CX231XX_BOARD_AVERMEDIA_H837B: + case CX231XX_BOARD_AVERMEDIA_H837A: { + cx231xx_set_power_mode(dev, POLARIS_AVMODE_DEFAULT); + msleep(20); + cx231xx_set_agc_analog_digital_mux_select(dev, 0); + cx231xx_set_power_mode(dev, POLARIS_AVMODE_DIGITAL); + msleep(50); + cx231xx_set_gpio_value(dev, AVERMEDIA_H837_LED_PIN, 0); + return 0; + } + break; case CX231XX_BOARD_CNXT_RDE_253S: case CX231XX_BOARD_CNXT_RDU_253S: case CX231XX_BOARD_PV_PLAYTV_USB_HYBRID: @@ -731,6 +816,13 @@ int cx231xx_set_mode(struct cx231xx *dev, enum cx231xx_mode set_mode) } else/* Set Analog Power mode */ { /* set AGC mode to Analog */ switch (dev->model) { + case CX231XX_BOARD_AVERMEDIA_H837A: + case CX231XX_BOARD_AVERMEDIA_H837B: + case CX231XX_BOARD_AVERMEDIA_H837M: + cx231xx_set_agc_analog_digital_mux_select(dev, 1); + cx231xx_set_power_mode(dev, POLARIS_AVMODE_DEFAULT); + cx231xx_set_gpio_value(dev, AVERMEDIA_H837_LED_PIN, 1); + return 0; case CX231XX_BOARD_CNXT_CARRAERA: case CX231XX_BOARD_CNXT_RDE_250: case CX231XX_BOARD_CNXT_SHELBY: @@ -1301,6 +1393,47 @@ void cx231xx_start_TS1(struct cx231xx *dev) /***************************************************************** * Device Init/UnInit functions * ******************************************************************/ +static void cx231xx_check_model(struct cx231xx *dev) +{ + if (is_model_avermedia_h837_series(dev->model)) { + struct i2c_msg msg[2]; + unsigned char offset = 255, value = 0; + + dev->i2c_bus[0].i2c_period = + dev->i2c_bus[1].i2c_period = + dev->i2c_bus[2].i2c_period = I2C_SPEED_400K; + /* first a write message to write EE offset*/ + msg[0].addr = 0x50; + msg[0].flags = 0; + msg[0].len = 1; + msg[0].buf = &offset; + + /* then a read message to read EE content, maximum read length is 4 bytes*/ + msg[1].addr = 0x50; + msg[1].flags = I2C_M_RD; + msg[1].len = 1; + msg[1].buf = &value; + + if (i2c_transfer(&dev->i2c_bus[1].i2c_adap, msg, 2) < 0) { + dev_err(dev->dev, "Failed to check EEPROM"); + return; + } + + if (0x01 == value) { + if (CX231XX_BOARD_AVERMEDIA_H837B == dev->model) + return; + dev->model = CX231XX_BOARD_AVERMEDIA_H837B; + } else { + if (CX231XX_BOARD_AVERMEDIA_H837A == dev->model || + CX231XX_BOARD_AVERMEDIA_H837M == dev->model) + return; + dev->model = CX231XX_BOARD_AVERMEDIA_H837A; + } + dev->board = cx231xx_boards[dev->model]; + dev_info(dev->dev, "Correct device model as %s\n", dev->board.name); + } +} + int cx231xx_dev_init(struct cx231xx *dev) { int errCode = 0; @@ -1359,6 +1492,9 @@ int cx231xx_dev_init(struct cx231xx *dev) cx231xx_do_i2c_scan(dev, I2C_2); cx231xx_do_i2c_scan(dev, I2C_1_MUX_3); + /* model check */ + cx231xx_check_model(dev); + /* init hardware */ /* Note : with out calling set power mode function, afe can not be set up correctly */ diff --git a/drivers/media/usb/cx231xx/cx231xx-dvb.c b/drivers/media/usb/cx231xx/cx231xx-dvb.c index 1417515d30eb..d2fca6509f54 100644 --- a/drivers/media/usb/cx231xx/cx231xx-dvb.c +++ b/drivers/media/usb/cx231xx/cx231xx-dvb.c @@ -67,6 +67,13 @@ struct cx231xx_dvb { struct dvb_net net; struct i2c_client *i2c_client_demod; struct i2c_client *i2c_client_tuner; + int power_on; +}; + +#include "tda18272.h" +static struct tda18272_config h837_tda18272_config = { + 0x60 /* dev->board.tuner_addr*/ + , TDA18272_SINGLE }; static struct s5h1432_config dvico_s5h1432_config = { @@ -128,6 +135,17 @@ static struct lgdt3305_config hcw_lgdt3305_config = { .vsb_if_khz = 3250, }; +static struct lgdt3305_config h837_lgdt3305_config = { + .i2c_addr = 0xB2 >> 1, + .mpeg_mode = LGDT3305_MPEG_SERIAL, + .tpclk_edge = LGDT3305_TPCLK_FALLING_EDGE, + .tpvalid_polarity = LGDT3305_TP_VALID_HIGH, + .deny_i2c_rptr = 1, + .spectral_inversion = 1, + .qam_if_khz = 3600, + .vsb_if_khz = 3250, +}; + static struct tda18271_std_map hauppauge_tda18271_std_map = { .atsc_6 = { .if_freq = 3250, .agc_mode = 3, .std = 4, .if_lvl = 1, .rfagc_top = 0x58, }, @@ -265,7 +283,14 @@ static int start_streaming(struct cx231xx_dvb *dvb) if (dev->USE_ISO) { dev_dbg(dev->dev, "DVB transfer mode is ISO.\n"); - cx231xx_set_alt_setting(dev, INDEX_TS1, 4); + mutex_lock(&dev->i2c_lock); + if (is_model_avermedia_h837_series(dev->model)) { + cx231xx_set_alt_setting(dev, INDEX_TS1, 4); + ++dvb->power_on; + } else { + cx231xx_set_alt_setting(dev, INDEX_TS1, 4); + } + mutex_unlock(&dev->i2c_lock); rc = cx231xx_set_mode(dev, CX231XX_DIGITAL_MODE); if (rc < 0) return rc; @@ -280,6 +305,9 @@ static int start_streaming(struct cx231xx_dvb *dvb) rc = cx231xx_set_mode(dev, CX231XX_DIGITAL_MODE); if (rc < 0) return rc; + if (is_model_avermedia_h837_series(dev->model)) { + ++dvb->power_on; + } dev->mode_tv = 1; return cx231xx_init_bulk(dev, CX231XX_DVB_MAX_PACKETS, CX231XX_DVB_NUM_BUFS, @@ -298,6 +326,11 @@ static int stop_streaming(struct cx231xx_dvb *dvb) else cx231xx_uninit_bulk(dev); + if (-1 != dvb->power_on) { + --dvb->power_on; + if (dvb->power_on) + return 0; + } cx231xx_set_mode(dev, CX231XX_SUSPEND); return 0; @@ -346,12 +379,21 @@ static int stop_feed(struct dvb_demux_feed *feed) static int cx231xx_dvb_bus_ctrl(struct dvb_frontend *fe, int acquire) { struct cx231xx *dev = fe->dvb->priv; + struct cx231xx_dvb *dvb = dev->dvb; - if (acquire) + if (acquire) { + if (dvb != NULL && -1 != dvb->power_on) + ++dvb->power_on; return cx231xx_set_mode(dev, CX231XX_DIGITAL_MODE); - else + } else { + if (dvb != NULL && -1 != dvb->power_on) { + --dvb->power_on; + if (dvb->power_on) + return 0; + } return cx231xx_set_mode(dev, CX231XX_SUSPEND); } +} /* ------------------------------------------------------------------ */ @@ -612,14 +654,21 @@ static int dvb_init(struct cx231xx *dev) return -ENOMEM; } dev->dvb = dvb; + dvb->power_on = -1; dev->cx231xx_set_analog_freq = cx231xx_set_analog_freq; dev->cx231xx_reset_analog_tuner = cx231xx_reset_analog_tuner; tuner_i2c = cx231xx_get_i2c_adap(dev, dev->board.tuner_i2c_master); demod_i2c = cx231xx_get_i2c_adap(dev, dev->board.demod_i2c_master); mutex_lock(&dev->lock); + if (is_model_avermedia_h837_series(dev->model)) { + cx231xx_set_mode(dev, CX231XX_SUSPEND); + cx231xx_set_mode(dev, CX231XX_DIGITAL_MODE); + dvb->power_on = 0; + } else { cx231xx_set_mode(dev, CX231XX_DIGITAL_MODE); cx231xx_demod_reset(dev); + } /* init frontend */ switch (dev->model) { case CX231XX_BOARD_CNXT_CARRAERA: @@ -864,6 +913,7 @@ static int dvb_init(struct cx231xx *dev) dev->dvb->i2c_client_tuner = client; break; } + case CX231XX_BOARD_HAUPPAUGE_955Q: { struct i2c_client *client; @@ -948,6 +998,28 @@ static int dvb_init(struct cx231xx *dev) 0x60, tuner_i2c, &pv_tda18271_config); break; + case CX231XX_BOARD_AVERMEDIA_H837A: + case CX231XX_BOARD_AVERMEDIA_H837B: + case CX231XX_BOARD_AVERMEDIA_H837M: + dev->dvb->frontend = dvb_attach(lgdt3305_attach, + &h837_lgdt3305_config, + &dev->i2c_bus[dev->board.demod_i2c_master].i2c_adap); + + if (dev->dvb->frontend == NULL) { + printk(DRIVER_NAME + ": Failed to attach LG3305 front end\n"); + result = -EINVAL; + goto out_free; + } + + /* define general-purpose callback pointer */ + dvb->frontend->callback = cx231xx_tuner_callback; + { + dvb_attach(tda18272_attach, dev->dvb->frontend, + &dev->i2c_bus[dev->board.tuner_i2c_master].i2c_adap, + &h837_tda18272_config); + } + break; default: dev_err(dev->dev, diff --git a/drivers/media/usb/cx231xx/cx231xx-video.c b/drivers/media/usb/cx231xx/cx231xx-video.c index 6414188ffdfa..a763d5ea43e0 100644 --- a/drivers/media/usb/cx231xx/cx231xx-video.c +++ b/drivers/media/usb/cx231xx/cx231xx-video.c @@ -870,6 +870,8 @@ static struct videobuf_queue_ops cx231xx_video_qops = { void video_mux(struct cx231xx *dev, int index) { + if (is_model_avermedia_h837_series(dev->model)) + return; dev->video_input = index; dev->ctl_ainput = INPUT(index)->amux; diff --git a/drivers/media/usb/cx231xx/cx231xx.h b/drivers/media/usb/cx231xx/cx231xx.h index 90c867683076..c027cef2d700 100644 --- a/drivers/media/usb/cx231xx/cx231xx.h +++ b/drivers/media/usb/cx231xx/cx231xx.h @@ -78,6 +78,9 @@ #define CX231XX_BOARD_HAUPPAUGE_930C_HD_1114xx 20 #define CX231XX_BOARD_HAUPPAUGE_955Q 21 #define CX231XX_BOARD_TERRATEC_GRABBY 22 +#define CX231XX_BOARD_AVERMEDIA_H837A 23 +#define CX231XX_BOARD_AVERMEDIA_H837B 24 +#define CX231XX_BOARD_AVERMEDIA_H837M 25 /* Limits minimum and default number of buffers */ #define CX231XX_MIN_BUF 4 @@ -127,6 +130,7 @@ #define SLEEP_S5H1432 30 #define CX23417_OSC_EN 8 #define CX23417_RESET 9 +#define AVERMEDIA_H837_LED_PIN 27 struct cx23417_fmt { char *name; @@ -1005,4 +1009,16 @@ static inline unsigned int norm_maxh(struct cx231xx *dev) else return (dev->norm & V4L2_STD_625_50) ? 576 : 480; } + +static inline bool is_model_avermedia_h837_series(int model) +{ + switch (model) { + case CX231XX_BOARD_AVERMEDIA_H837A: + case CX231XX_BOARD_AVERMEDIA_H837B: + case CX231XX_BOARD_AVERMEDIA_H837M: + return true; + } + return false; +} + #endif diff --git a/drivers/mmc/card/block.c b/drivers/mmc/card/block.c index c0fb2c35f059..fcd27b8d748d 100644 --- a/drivers/mmc/card/block.c +++ b/drivers/mmc/card/block.c @@ -86,6 +86,9 @@ static int perdev_minors = CONFIG_MMC_BLOCK_MINORS; * limited by the MAX_DEVICES below. */ static int max_devices; +#ifdef CONFIG_AMLOGIC_MMC +static int ffu_mode; +#endif #define MAX_DEVICES 256 @@ -584,6 +587,9 @@ static struct mmc_blk_ioc_data *mmc_blk_ioctl_copy_from_user( { struct mmc_blk_ioc_data *idata; int err; +#ifdef CONFIG_AMLOGIC_MMC + unsigned long mmc_io_max; +#endif idata = kmalloc(sizeof(*idata), GFP_KERNEL); if (!idata) { @@ -596,8 +602,25 @@ static struct mmc_blk_ioc_data *mmc_blk_ioctl_copy_from_user( goto idata_err; } +#ifdef CONFIG_AMLOGIC_MMC + if ((idata->ic.opcode == MMC_SWITCH) + && (((idata->ic.arg >> 8) & 0xff) == 1)) + ffu_mode = 1; + else if ((idata->ic.opcode == MMC_SWITCH) + && (((idata->ic.arg >> 8) & 0xff) == 0)) + ffu_mode = 0; + if (ffu_mode) + mmc_io_max = (512L * 1024); + else + mmc_io_max = MMC_IOC_MAX_BYTES; +#endif + idata->buf_bytes = (u64) idata->ic.blksz * idata->ic.blocks; +#ifdef CONFIG_AMLOGIC_MMC + if (idata->buf_bytes > mmc_io_max) { +#else if (idata->buf_bytes > MMC_IOC_MAX_BYTES) { +#endif err = -EOVERFLOW; goto idata_err; } @@ -718,6 +741,55 @@ static void aml_mmc_set_blockcount(struct mmc_request *p_mrq, p_sbc->flags = MMC_RSP_SPI_R1 | MMC_RSP_R1 | MMC_CMD_AC; p_mrq->sbc = p_sbc; } + +/* + * Map memory into a scatterlist so that no pages are contiguous. Allow the + * same memory to be mapped more than once. + */ +static int mmc_ffu_map_sg_max_scatter(void *mem, + unsigned long sz, + struct scatterlist *sglist, + unsigned int max_segs, + unsigned int max_seg_sz, + struct mmc_blk_ioc_data *idata, + unsigned int *sg_len) +{ + struct scatterlist *sg = NULL; + unsigned long len; + void *addr = NULL; + unsigned int segs = 0; + + segs = sz / max_seg_sz; + if (sz % max_seg_sz) + segs++; + if (segs > max_segs) + segs = max_segs; + + sg_init_table(sglist, segs); + + *sg_len = 0; + addr = mem; + while (sz) { + len = max_seg_sz; + if (len > sz) + len = sz; + if (sg) + sg = sg_next(sg); + else + sg = sglist; + if (!sg) + return -EINVAL; + sg_set_buf(sg, addr, len); + sz -= len; + addr += len; + *sg_len += 1; + } + + if (sg) + sg_mark_end(sg); + + return 0; +} #endif static int __mmc_blk_ioctl_cmd(struct mmc_card *card, struct mmc_blk_data *md, @@ -730,6 +802,7 @@ static int __mmc_blk_ioctl_cmd(struct mmc_card *card, struct mmc_blk_data *md, #endif struct mmc_request mrq = {NULL}; struct scatterlist sg; + struct scatterlist *ffu_sg = NULL; int err; int is_rpmb = false; u32 status = 0; @@ -745,12 +818,38 @@ static int __mmc_blk_ioctl_cmd(struct mmc_card *card, struct mmc_blk_data *md, cmd.flags = idata->ic.flags; if (idata->buf_bytes) { - data.sg = &sg; - data.sg_len = 1; - data.blksz = idata->ic.blksz; - data.blocks = idata->ic.blocks; +#ifdef CONFIG_AMLOGIC_MMC + if (ffu_mode && (cmd.opcode == 25)) { + sbc.opcode = MMC_SET_BLOCK_COUNT; + sbc.arg = idata->ic.blocks; + sbc.flags = MMC_RSP_R1 | MMC_CMD_AC; + mrq.sbc = &sbc; - sg_init_one(data.sg, idata->buf, idata->buf_bytes); + ffu_sg = kmalloc(sizeof(struct scatterlist) * 512, + GFP_KERNEL); + if (!ffu_sg) + return -ENOMEM; + + data.sg = ffu_sg; + mmc_ffu_map_sg_max_scatter(idata->buf, idata->buf_bytes, + data.sg, 511, (512 * 256), + idata, &data.sg_len); + + if (data.sg_len > 1) + data.blocks = 256; + else + data.blocks = idata->ic.blocks; + data.blksz = idata->ic.blksz; + } else { +#endif + data.sg = &sg; + data.sg_len = 1; + data.blksz = idata->ic.blksz; + data.blocks = idata->ic.blocks; + sg_init_one(data.sg, idata->buf, idata->buf_bytes); +#ifdef CONFIG_AMLOGIC_MMC + } +#endif if (idata->ic.write_flag) data.flags = MMC_DATA_WRITE; @@ -956,7 +1055,19 @@ static int mmc_blk_ioctl_multi_cmd(struct block_device *bdev, mmc_get_card(card); for (i = 0; i < num_of_cmds && !ioc_err; i++) +#ifdef CONFIG_AMLOGIC_MMC + { + if ((idata[i]->ic.opcode == MMC_SWITCH) + && (((idata[i]->ic.arg >> 8) & 0xff) == 1)) + ffu_mode = 1; + else if ((idata[i]->ic.opcode == MMC_SWITCH) + && (((idata[i]->ic.arg >> 8) & 0xff) == 0)) + ffu_mode = 0; +#endif ioc_err = __mmc_blk_ioctl_cmd(card, md, idata[i]); +#ifdef CONFIG_AMLOGIC_MMC + } +#endif /* Always switch back to main area after RPMB access */ if (md->area_type & MMC_BLK_DATA_AREA_RPMB) @@ -2887,6 +2998,13 @@ static const struct mmc_fixup blk_fixups[] = MMC_FIXUP("VZL00M", CID_MANFID_SAMSUNG, CID_OEMID_ANY, add_quirk_mmc, MMC_QUIRK_SEC_ERASE_TRIM_BROKEN), + /* + * On these Toshiba eMMC, performing secure erase or + * secure trim will cost more than 5 minutes. + */ + MMC_FIXUP("004GA0", CID_MANFID_TOSHIBA, CID_OEMID_ANY, add_quirk_mmc, + MMC_QUIRK_SEC_ERASE_TRIM_BROKEN), + /* * On Some Kingston eMMCs, performing trim can result in * unrecoverable data conrruption occasionally due to a firmware bug. diff --git a/drivers/spi/spi-meson-spicc.c b/drivers/spi/spi-meson-spicc.c index d5d858981c87..ea3528414962 100644 --- a/drivers/spi/spi-meson-spicc.c +++ b/drivers/spi/spi-meson-spicc.c @@ -207,6 +207,7 @@ struct meson_spicc_device { u8 *tx_buf; u8 *rx_buf; unsigned int bytes_per_word; + unsigned int speed_hz; unsigned long tx_remain; unsigned long txb_remain; unsigned long rx_remain; @@ -294,7 +295,9 @@ static void meson_spicc_auto_io_delay(struct meson_spicc_device *spicc) cap_delay = SPICC_CAP_AHEAD_2_CYCLE; hz = clk_get_rate(spicc->clk); - if (hz >= 100000000) + if (spicc->message->spi->mode & SPI_LOOP) + cap_delay = SPICC_CAP_AHEAD_1_CYCLE; + else if (hz >= 100000000) cap_delay = SPICC_CAP_DELAY_1_CYCLE; else if (hz >= 80000000) cap_delay = SPICC_CAP_NO_DELAY; @@ -545,7 +548,10 @@ static void meson_spicc_setup_xfer(struct meson_spicc_device *spicc, if (conf != conf_orig) writel_relaxed(conf, spicc->base + SPICC_CONREG); - clk_set_rate(spicc->clk, xfer->speed_hz); + if (spicc->speed_hz != xfer->speed_hz) { + spicc->speed_hz = xfer->speed_hz; + clk_set_rate(spicc->clk, xfer->speed_hz); + } meson_spicc_auto_io_delay(spicc); spicc->using_dma = 0; diff --git a/drivers/staging/android/ion/ion_codec_mm_heap.c b/drivers/staging/android/ion/ion_codec_mm_heap.c index 074992f8c7c2..3e1ca5ee1437 100644 --- a/drivers/staging/android/ion/ion_codec_mm_heap.c +++ b/drivers/staging/android/ion/ion_codec_mm_heap.c @@ -54,7 +54,7 @@ ion_phys_addr_t ion_codec_mm_allocate(struct ion_heap *heap, CODEC_MM_ION, size / PAGE_SIZE, 0, - CODEC_MM_FLAGS_DMA_CPU); + CODEC_MM_FLAGS_DMA); if (!offset) { pr_err("ion_codec_mm_allocate failed out size %d\n", (int)size); diff --git a/drivers/staging/android/ion/ion_system_heap.c b/drivers/staging/android/ion/ion_system_heap.c index 4364072b2e1b..86fd2fce0a2f 100644 --- a/drivers/staging/android/ion/ion_system_heap.c +++ b/drivers/staging/android/ion/ion_system_heap.c @@ -318,6 +318,10 @@ static int ion_system_heap_create_pools(struct ion_page_pool **pools, if (orders[i] > 4) gfp_flags = high_order_gfp_flags; +#ifdef CONFIG_AMLOGIC_MODIFY + else if (!orders[i]) + gfp_flags = low_order_gfp_flags; +#endif pool = ion_page_pool_create(gfp_flags, orders[i], cached); if (!pool) diff --git a/drivers/usb/gadget/function/f_fs.c b/drivers/usb/gadget/function/f_fs.c index e439847be51d..d496fc2d3b36 100644 --- a/drivers/usb/gadget/function/f_fs.c +++ b/drivers/usb/gadget/function/f_fs.c @@ -262,11 +262,22 @@ static int ffs_ready(struct ffs_data *ffs); static void ffs_closed(struct ffs_data *ffs); #ifdef CONFIG_AMLOGIC_USB -static int ffs_malloc_buffer(struct ffs_data *ffs) +static int ffs_malloc_buffer_init(struct ffs_data *ffs, int cout) { int i; + pr_info("assign_ffs_buffer FFS_BUFFER_MAX=%d!!!\n", FFS_BUFFER_MAX); for (i = 0; i < FFS_BUFFER_MAX; i++) { + ffs->buffer[i].data_ep = NULL; + ffs->buffer[i].data_state = -1; + } + + for (i = 0; i < cout; i++) { + if (i >= FFS_BUFFER_MAX) { + pr_err("<%s>wait alloc (%d) > define (%d)!!!\n", + __func__, cout, FFS_BUFFER_MAX); + break; + } ffs->buffer[i].data_ep = kzalloc(MAX_PAYLOAD_EPS, GFP_KERNEL); if (!ffs->buffer[i].data_ep) return -ENOMEM; @@ -276,14 +287,38 @@ static int ffs_malloc_buffer(struct ffs_data *ffs) return 0; } +struct ffs_data_buffer *ffs_retry_malloc_buffer(struct ffs_data *ffs) +{ + int i; + + pr_info("ffs_retry_malloc_buffer\n"); + for (i = 0; i < FFS_BUFFER_MAX; i++) { + if (ffs->buffer[i].data_state == -1) { + spin_unlock_irq(&ffs->eps_lock); + ffs->buffer[i].data_ep + = kzalloc(MAX_PAYLOAD_EPS, GFP_KERNEL); + spin_lock_irq(&ffs->eps_lock); + if (!ffs->buffer[i].data_ep) + return NULL; + ffs->buffer[i].data_state = 1; + return &(ffs->buffer[i]); + } + } + pr_info("assign_ffs_buffer failed, FFS_BUFFER_MAX(%d) is too small!!!\n", + FFS_BUFFER_MAX); + return NULL; +} + static void ffs_free_buffer(struct ffs_data *ffs) { int i; for (i = 0; i < FFS_BUFFER_MAX; i++) { - kfree(ffs->buffer[i].data_ep); - ffs->buffer[i].data_ep = NULL; - ffs->buffer[i].data_state = 0; + if (ffs->buffer[i].data_state != -1) { + kfree(ffs->buffer[i].data_ep); + ffs->buffer[i].data_ep = NULL; + ffs->buffer[i].data_state = 0; + } } } @@ -298,8 +333,7 @@ static struct ffs_data_buffer *assign_ffs_buffer(struct ffs_data *ffs) } } - pr_info("assign_ffs_buffer failed!!!\n"); - return NULL; + return ffs_retry_malloc_buffer(ffs); } static void release_ffs_buffer(struct ffs_data *ffs, @@ -829,6 +863,17 @@ static void ffs_user_copy_worker(struct work_struct *work) io_data->req->actual; bool kiocb_has_eventfd = io_data->kiocb->ki_flags & IOCB_EVENTFD; +#ifdef CONFIG_AMLOGIC_USB + int i = 0; + struct ffs_data_buffer *buffer = NULL; + + for (i = 0; i < FFS_BUFFER_MAX; i++) { + buffer = &(io_data->ffs->buffer[i]); + if (io_data->buf == buffer->data_ep) { + break; + } + } +#endif if (io_data->read && ret > 0) { mm_segment_t oldfs = get_fs(); @@ -848,7 +893,15 @@ static void ffs_user_copy_worker(struct work_struct *work) if (io_data->read) kfree(io_data->to_free); + +#ifdef CONFIG_AMLOGIC_USB + if (io_data->aio) { + if (buffer) + release_ffs_buffer(io_data->ffs, buffer); + } +#else kfree(io_data->buf); +#endif kfree(io_data); } @@ -952,7 +1005,7 @@ static ssize_t ffs_epfile_io(struct file *file, struct ffs_io_data *io_data) #ifdef CONFIG_AMLOGIC_USB struct ffs_ep *ep = epfile->ep; struct ffs_data_buffer *buffer = NULL; - int data_flag = -1; + int data_aio_flag = -1; #else struct ffs_ep *ep; #endif @@ -1034,15 +1087,6 @@ static ssize_t ffs_epfile_io(struct file *file, struct ffs_io_data *io_data) goto error_mutex; } #else - if (io_data->aio) { - spin_unlock_irq(&epfile->ffs->eps_lock); - data = kmalloc(data_len, GFP_KERNEL); - data_flag = 1; - if (unlikely(!data)) { - ret = -ENOMEM; - goto error_mutex; - } - } else { /* Fire the request */ /* * Avoid kernel panic caused by race condition. For example, @@ -1060,9 +1104,10 @@ static ssize_t ffs_epfile_io(struct file *file, struct ffs_io_data *io_data) * To avoid this, during FunctionFS mount, we allocated the * data buffer for requests. And the memory resources has * been released in kill_sb. + *reboot adb disconnect,so buffer aways used assign_ffs_buffer. */ buffer = assign_ffs_buffer(epfile->ffs); - data_flag = -1; + data_aio_flag = 1; if (unlikely(!buffer)) { ret = -ENOMEM; spin_unlock_irq(&epfile->ffs->eps_lock); @@ -1071,7 +1116,6 @@ static ssize_t ffs_epfile_io(struct file *file, struct ffs_io_data *io_data) data = buffer->data_ep; spin_unlock_irq(&epfile->ffs->eps_lock); - } #endif if (!io_data->read && @@ -1110,6 +1154,9 @@ static ssize_t ffs_epfile_io(struct file *file, struct ffs_io_data *io_data) DECLARE_COMPLETION_ONSTACK(done); #endif bool interrupted = false; +#ifdef CONFIG_AMLOGIC_USB + data_aio_flag = 1; +#endif req = ep->req; req->buf = data; req->length = data_len; @@ -1146,6 +1193,9 @@ static ssize_t ffs_epfile_io(struct file *file, struct ffs_io_data *io_data) } else if (!(req = usb_ep_alloc_request(ep->ep, GFP_ATOMIC))) { ret = -ENOMEM; } else { +#ifdef CONFIG_AMLOGIC_USB + data_aio_flag = -1; +#endif req->buf = data; req->length = data_len; @@ -1177,10 +1227,7 @@ error_mutex: mutex_unlock(&epfile->mutex); error: #ifdef CONFIG_AMLOGIC_USB - if (data_flag > 0) { - kfree(data); - data = NULL; - } else { + if (data_aio_flag > 0) { if (buffer) release_ffs_buffer(epfile->ffs, buffer); } @@ -1640,7 +1687,7 @@ ffs_fs_mount(struct file_system_type *t, int flags, if (unlikely(!ffs->data_ep0)) return ERR_PTR(-ENOMEM); - ret = ffs_malloc_buffer(ffs); + ret = ffs_malloc_buffer_init(ffs, 10); if (ret < 0) return ERR_PTR(ret); diff --git a/drivers/usb/gadget/function/u_fs.h b/drivers/usb/gadget/function/u_fs.h index 1ddb96353579..f9fea063ccac 100644 --- a/drivers/usb/gadget/function/u_fs.h +++ b/drivers/usb/gadget/function/u_fs.h @@ -147,10 +147,10 @@ enum ffs_setup_state { FFS_SETUP_CANCELLED }; -#define FFS_BUFFER_MAX 10 +#define FFS_BUFFER_MAX 100 struct ffs_data_buffer { char *data_ep; - bool data_state; + int data_state; }; struct ffs_data { diff --git a/drivers/video/fbdev/core/fbmem.c b/drivers/video/fbdev/core/fbmem.c index 74273bc7ca9a..3c3e23c6042b 100644 --- a/drivers/video/fbdev/core/fbmem.c +++ b/drivers/video/fbdev/core/fbmem.c @@ -1212,14 +1212,23 @@ static long do_fb_ioctl(struct fb_info *info, unsigned int cmd, console_unlock(); break; default: + #ifndef CONFIG_AMLOGIC_MODIFY + /* + * display may have several command passed to fbdev + * at the same time. do as the compat ioctl, + * let hw driver to take care of lock. + */ if (!lock_fb_info(info)) return -ENODEV; + #endif fb = info->fbops; if (fb->fb_ioctl) ret = fb->fb_ioctl(info, cmd, arg); else ret = -ENOTTY; + #ifndef CONFIG_AMLOGIC_MODIFY unlock_fb_info(info); + #endif } return ret; } diff --git a/include/dt-bindings/clock/amlogic,tl1-audio-clk.h b/include/dt-bindings/clock/amlogic,tl1-audio-clk.h new file mode 100644 index 000000000000..a000dee9c4e3 --- /dev/null +++ b/include/dt-bindings/clock/amlogic,tl1-audio-clk.h @@ -0,0 +1,76 @@ +/* + * include/dt-bindings/clock/amlogic,tl1-audio-clk.h + * + * Copyright (C) 2018 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +#ifndef __TL1_AUDIO_CLK_H +#define __TL1_AUDIO_CLK_H + +/* + * CLKID audio index values + */ + +#define CLKID_AUDIO_DDR_ARB 0 +#define CLKID_AUDIO_PDM 1 +#define CLKID_AUDIO_TDMINA 2 +#define CLKID_AUDIO_TDMINB 3 +#define CLKID_AUDIO_TDMINC 4 +#define CLKID_AUDIO_TDMINLB 5 +#define CLKID_AUDIO_TDMOUTA 6 +#define CLKID_AUDIO_TDMOUTB 7 +#define CLKID_AUDIO_TDMOUTC 8 +#define CLKID_AUDIO_FRDDRA 9 +#define CLKID_AUDIO_FRDDRB 10 +#define CLKID_AUDIO_FRDDRC 11 +#define CLKID_AUDIO_TODDRA 12 +#define CLKID_AUDIO_TODDRB 13 +#define CLKID_AUDIO_TODDRC 14 +#define CLKID_AUDIO_LOOPBACKA 15 +#define CLKID_AUDIO_SPDIFIN 16 +#define CLKID_AUDIO_SPDIFOUT 17 +#define CLKID_AUDIO_RESAMPLEA 18 +#define CLKID_AUDIO_RESERVED0 19 +#define CLKID_AUDIO_RESERVED1 20 +#define CLKID_AUDIO_SPDIFOUTB 21 +#define CLKID_AUDIO_EQDRC 22 +#define CLKID_AUDIO_RESAMPLEB 23 +#define CLKID_AUDIO_TOVAD 24 +#define CLKID_AUDIO_AUDIOLOCKER 25 +#define CLKID_AUDIO_SPDIFIN_LB 26 +#define CLKID_AUDIO_FRATV 27 +#define CLKID_AUDIO_FRHDMIRX 28 +#define CLKID_AUDIO_FRDDRD 29 +#define CLKID_AUDIO_TODDRD 30 +#define CLKID_AUDIO_LOOPBACKB 31 + +#define MCLK_BASE 32 +#define CLKID_AUDIO_MCLK_A (MCLK_BASE + 0) +#define CLKID_AUDIO_MCLK_B (MCLK_BASE + 1) +#define CLKID_AUDIO_MCLK_C (MCLK_BASE + 2) +#define CLKID_AUDIO_MCLK_D (MCLK_BASE + 3) +#define CLKID_AUDIO_MCLK_E (MCLK_BASE + 4) +#define CLKID_AUDIO_MCLK_F (MCLK_BASE + 5) + +#define CLKID_AUDIO_SPDIFIN_CTRL (MCLK_BASE + 6) +#define CLKID_AUDIO_SPDIFOUT_CTRL (MCLK_BASE + 7) +#define CLKID_AUDIO_PDMIN0 (MCLK_BASE + 8) +#define CLKID_AUDIO_PDMIN1 (MCLK_BASE + 9) +#define CLKID_AUDIO_SPDIFOUTB_CTRL (MCLK_BASE + 10) +#define CLKID_AUDIO_LOCKER_OUT (MCLK_BASE + 11) +#define CLKID_AUDIO_LOCKER_IN (MCLK_BASE + 12) +#define CLKID_AUDIO_RESAMPLE_CTRL (MCLK_BASE + 13) + +#define NUM_AUDIO_CLKS (MCLK_BASE + 14) +#endif /* __G12A_AUDIO_CLK_H */ diff --git a/include/linux/amlogic/aml_cma.h b/include/linux/amlogic/aml_cma.h index 947fd0aecb1e..4acb96ffb455 100644 --- a/include/linux/amlogic/aml_cma.h +++ b/include/linux/amlogic/aml_cma.h @@ -50,6 +50,7 @@ struct compact_control { const int classzone_idx; /* zone index of a direct compactor */ struct zone *zone; bool contended; /* Signal lock or sched contention */ + bool forbid_to_cma; /* Forbit to migrate to cma */ }; static inline bool cma_forbidden_mask(gfp_t gfp_flags) diff --git a/include/linux/amlogic/aml_ddr_bandwidth.h b/include/linux/amlogic/aml_ddr_bandwidth.h index 5e3113b58775..1235d1ee0a9c 100644 --- a/include/linux/amlogic/aml_ddr_bandwidth.h +++ b/include/linux/amlogic/aml_ddr_bandwidth.h @@ -18,8 +18,13 @@ #ifndef __AML_DDR_BANDWIDTH_H__ #define __AML_DDR_BANDWIDTH_H__ +#define MODE_DISABLE 0 +#define MODE_ENABLE 1 +#define MODE_AUTODETECT 2 -#define DEFAULT_CLK_CNT 12000000 +#define DEFAULT_THRESHOLD 5000 + +#define DEFAULT_CLK_CNT 48000000 #define DEFAULT_XTAL_FREQ 24000000UL #define DMC_QOS_IRQ (1 << 30) @@ -43,6 +48,23 @@ #define DMC_MON_CTRL5 (0x19 << 2) #define DMC_MON_CTRL6 (0x1a << 2) +#define DMC_AM0_CHAN_CTRL (0x60 << 2) +#define DMC_AM1_CHAN_CTRL (0x6a << 2) +#define DMC_AM2_CHAN_CTRL (0x74 << 2) +#define DMC_AM3_CHAN_CTRL (0x7e << 2) +#define DMC_AM4_CHAN_CTRL (0x88 << 2) +#define DMC_AM5_CHAN_CTRL (0x92 << 2) +#define DMC_AM6_CHAN_CTRL (0x9c << 2) +#define DMC_AM7_CHAN_CTRL (0xa6 << 2) +#define DMC_AXI0_CHAN_CTRL (0xb0 << 2) +#define DMC_AXI1_CHAN_CTRL (0xba << 2) +#define DMC_AXI2_CHAN_CTRL (0xc4 << 2) +#define DMC_AXI3_CHAN_CTRL (0xce << 2) +#define DMC_AXI4_CHAN_CTRL (0xd8 << 2) +#define DMC_AXI5_CHAN_CTRL (0xe2 << 2) +#define DMC_AXI6_CHAN_CTRL (0xec << 2) +#define DMC_AXI7_CHAN_CTRL (0xf6 << 2) + /* * register offset for g12a */ @@ -64,6 +86,28 @@ #define DMC_MON_G12_FOR_GRANT_CNT (0x2e << 2) #define DMC_MON_G12_TIMER (0x2f << 2) +#define DMC_AM0_G12_CHAN_CTRL (0x60 << 2) +#define DMC_AM1_G12_CHAN_CTRL (0x64 << 2) +#define DMC_AM2_G12_CHAN_CTRL (0x68 << 2) +#define DMC_AM3_G12_CHAN_CTRL (0x6c << 2) +#define DMC_AM4_G12_CHAN_CTRL (0x70 << 2) +#define DMC_AM5_G12_CHAN_CTRL (0x74 << 2) +#define DMC_AM6_G12_CHAN_CTRL (0x78 << 2) +#define DMC_AM7_G12_CHAN_CTRL (0x7c << 2) +#define DMC_AXI0_G12_CHAN_CTRL (0x80 << 2) +#define DMC_AXI1_G12_CHAN_CTRL (0x84 << 2) +#define DMC_AXI2_G12_CHAN_CTRL (0x88 << 2) +#define DMC_AXI3_G12_CHAN_CTRL (0x8c << 2) +#define DMC_AXI4_G12_CHAN_CTRL (0x90 << 2) +#define DMC_AXI5_G12_CHAN_CTRL (0x94 << 2) +#define DMC_AXI6_G12_CHAN_CTRL (0x98 << 2) +#define DMC_AXI7_G12_CHAN_CTRL (0x9c << 2) +#define DMC_AXI8_G12_CHAN_CTRL (0xa0 << 2) +#define DMC_AXI9_G12_CHAN_CTRL (0xa4 << 2) +#define DMC_AXI10_G12_CHAN_CTRL (0xa8 << 2) +#define DMC_AXI11_G12_CHAN_CTRL (0xac << 2) +#define DMC_AXI12_G12_CHAN_CTRL (0xb0 << 2) + /* data structure */ #define DDR_BANDWIDTH_DEBUG 1 @@ -91,6 +135,11 @@ struct ddr_bandwidth { struct class *class; unsigned short cpu_type; unsigned short real_ports; + char busy; + char mode; + int mali_port[2]; + unsigned int threshold; + struct work_struct work_bandwidth; unsigned int irq_num; unsigned int clock_count; unsigned int channels; diff --git a/include/linux/amlogic/aml_dmc.h b/include/linux/amlogic/aml_dmc.h new file mode 100644 index 000000000000..09258489e608 --- /dev/null +++ b/include/linux/amlogic/aml_dmc.h @@ -0,0 +1,24 @@ +/* + * include/linux/amlogic/aml_dmc.h + * + * Copyright (C) 2017 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +#ifndef AML_DMC_HEADERS +#define AML_DMC_HEADERS + +extern void dmc_set_urgent(unsigned int port, unsigned int type); + +#endif + diff --git a/include/linux/amlogic/cpu_version.h b/include/linux/amlogic/cpu_version.h index 74eaaaa6ca8b..3aef138e0a6a 100644 --- a/include/linux/amlogic/cpu_version.h +++ b/include/linux/amlogic/cpu_version.h @@ -135,6 +135,11 @@ static inline bool is_meson_gxl_package_805X(void) return is_meson_gxl_cpu() && package_id_is(0x30); } +static inline bool is_meson_gxl_package_805Y(void) +{ + return is_meson_gxl_cpu() && package_id_is(0xb0); +} + static inline bool is_meson_gxm_cpu(void) { return get_cpu_type() == MESON_CPU_MAJOR_ID_GXM; diff --git a/include/linux/amlogic/media/amdolbyvision/dolby_vision.h b/include/linux/amlogic/media/amdolbyvision/dolby_vision.h index bdb5638a9009..370c01000bf2 100644 --- a/include/linux/amlogic/media/amdolbyvision/dolby_vision.h +++ b/include/linux/amlogic/media/amdolbyvision/dolby_vision.h @@ -51,5 +51,7 @@ extern int enable_rgb_to_yuv_matrix_for_dvll( int32_t on, uint32_t *coeff_orig, uint32_t bits); extern bool is_dovi_frame(struct vframe_s *vf); +extern void update_graphic_width_height(unsigned int width, + unsigned int height); #endif diff --git a/include/linux/amlogic/media/amvecm/amvecm.h b/include/linux/amlogic/media/amvecm/amvecm.h index b5b1912d8540..59e88fe6c5e2 100644 --- a/include/linux/amlogic/media/amvecm/amvecm.h +++ b/include/linux/amlogic/media/amvecm/amvecm.h @@ -23,6 +23,8 @@ #include #include #include +#include + /* struct ve_dnlp_s video_ve_dnlp; */ @@ -99,6 +101,12 @@ #define HDR10_SOURCE (1 << 1) #define HLG_SOURCE (1 << 2) +enum cm_hist_e { + CM_HUE_HIST = 0, + CM_SAT_HIST, + CM_MAX_HIST +}; + enum pq_table_name_e { TABLE_NAME_SHARPNESS0 = 0x1,/*in vpp*/ TABLE_NAME_SHARPNESS1 = 0x2,/*in vpp*/ @@ -243,9 +251,16 @@ enum vpp_matrix_csc_e { VPP_MATRIX_BT2020YUV_BT2020RGB = 0x40, VPP_MATRIX_BT2020RGB_709RGB, VPP_MATRIX_BT2020RGB_CUSRGB, + VPP_MATRIX_BT2020YUV_BT2020RGB_DYNAMIC = 0x50, VPP_MATRIX_DEFAULT_CSCTYPE = 0xffff, }; +enum vpp_transfer_characteristic_e { + VPP_ST_NULL = 0, + VPP_ST709 = 0x1, + VPP_ST2084 = 0x2, + VPP_ST2094_40 = 0x4, +}; enum ve_source_input_e { SOURCE_INVALID = -1, @@ -416,5 +431,15 @@ extern int VSYNC_WR_MPEG_REG_BITS(u32 adr, u32 val, u32 start, u32 len); extern u32 VSYNC_RD_MPEG_REG(u32 adr); extern int VSYNC_WR_MPEG_REG(u32 adr, u32 val); #endif +extern int amvecm_drm_get_gamma_size(u32 index); +extern void amvecm_drm_init(u32 index); +extern int amvecm_drm_gamma_set(u32 index, + struct drm_color_lut *lut, int lut_size); +extern int amvecm_drm_gamma_get(u32 index, u16 *red, u16 *green, u16 *blue); +extern int amvecm_drm_gamma_enable(u32 index); +extern int amvecm_drm_gamma_disable(u32 index); +extern int am_meson_ctm_set(u32 index, struct drm_color_ctm *ctm); +extern int am_meson_ctm_disable(void); + #endif /* AMVECM_H */ diff --git a/include/linux/amlogic/media/codec_mm/codec_mm.h b/include/linux/amlogic/media/codec_mm/codec_mm.h index 8f71042a1307..7108cb4a79d0 100644 --- a/include/linux/amlogic/media/codec_mm/codec_mm.h +++ b/include/linux/amlogic/media/codec_mm/codec_mm.h @@ -61,6 +61,9 @@ /*used scatter manager*/ #define CODEC_MM_FLAGS_FOR_SCATTER 0x10000000 +/*used for cnt phys vmaped*/ +#define CODEC_MM_FLAGS_FOR_PHYS_VMAPED 0x20000000 + #define CODEC_MM_FLAGS_FROM_MASK \ (CODEC_MM_FLAGS_DMA |\ CODEC_MM_FLAGS_CPU |\ @@ -121,6 +124,7 @@ unsigned long codec_mm_alloc_for_dma_ex( int buffer_id); void codec_mm_release(struct codec_mm_s *mem, const char *owner); +int codec_mm_has_owner(struct codec_mm_s *mem, const char *owner); int codec_mm_request_shared_mem(struct codec_mm_s *mem, const char *owner); /*call if not make sure valid data.*/ void codec_mm_release_with_check(struct codec_mm_s *mem, const char *owner); @@ -135,6 +139,8 @@ int codec_mm_free_for_dma(const char *owner, unsigned long phy_addr); void *codec_mm_phys_to_virt(unsigned long phy_addr); unsigned long codec_mm_virt_to_phys(void *vaddr); +u8 *codec_mm_vmap(ulong addr, u32 size); +void codec_mm_unmap_phyaddr(u8 *vaddr); void codec_mm_dma_flush(void *vaddr, int size, diff --git a/include/linux/amlogic/media/codec_mm/codec_mm_keeper.h b/include/linux/amlogic/media/codec_mm/codec_mm_keeper.h index 34a0ab83fbf3..5714def23bd5 100644 --- a/include/linux/amlogic/media/codec_mm/codec_mm_keeper.h +++ b/include/linux/amlogic/media/codec_mm/codec_mm_keeper.h @@ -26,6 +26,7 @@ */ int codec_mm_keeper_mask_keep_mem(void *mem_handle, int type); +int is_codec_mm_keeped(void *mem_handle); /* *can call in irq */ diff --git a/include/linux/amlogic/media/frame_sync/timestamp.h b/include/linux/amlogic/media/frame_sync/timestamp.h index e653bfa57233..6e27c9ca434c 100644 --- a/include/linux/amlogic/media/frame_sync/timestamp.h +++ b/include/linux/amlogic/media/frame_sync/timestamp.h @@ -64,8 +64,14 @@ extern void timestamp_checkin_firstvpts_set(u32 pts); extern u32 timestamp_checkin_firstvpts_get(void); +extern void timestamp_checkin_firstapts_set(u32 pts); + +extern u32 timestamp_checkin_firstapts_get(void); + extern void timestamp_firstapts_set(u32 pts); extern u32 timestamp_firstapts_get(void); +extern u32 timestamp_tsdemux_pcr_get(void); + #endif /* TIMESTAMP_H */ diff --git a/include/linux/amlogic/media/rdma/rdma_mgr.h b/include/linux/amlogic/media/rdma/rdma_mgr.h index a724a011f71d..20207501aeee 100644 --- a/include/linux/amlogic/media/rdma/rdma_mgr.h +++ b/include/linux/amlogic/media/rdma/rdma_mgr.h @@ -29,6 +29,16 @@ struct rdma_op_s { #define RDMA_TRIGGER_DEBUG2 0x102 #define RDMA_AUTO_START_MASK 0x80000 +enum rdma_ver_e { + RDMA_VER_1, + RDMA_VER_2, +}; + +struct rdma_device_data_s { + enum rdma_ver_e rdma_ver; + u32 trigger_mask_len; +}; + /* * rdma_read_reg(), rdma_write_reg(), rdma_clear() can only be called * after rdma_register() is called and diff --git a/include/linux/amlogic/media/registers/regs/rdma_regs.h b/include/linux/amlogic/media/registers/regs/rdma_regs.h index 0090e49d994c..202a2bbfccc2 100644 --- a/include/linux/amlogic/media/registers/regs/rdma_regs.h +++ b/include/linux/amlogic/media/registers/regs/rdma_regs.h @@ -45,6 +45,14 @@ #define RDMA_STATUS 0x1115 #define RDMA_STATUS2 0x1116 #define RDMA_STATUS3 0x1117 + +#define RDMA_AUTO_SRC1_SEL 0x1123 +#define RDMA_AUTO_SRC2_SEL 0x1124 +#define RDMA_AUTO_SRC3_SEL 0x1125 +#define RDMA_AUTO_SRC4_SEL 0x1126 +#define RDMA_AUTO_SRC5_SEL 0x1127 +#define RDMA_AUTO_SRC6_SEL 0x1128 +#define RDMA_AUTO_SRC7_SEL 0x1129 #endif #endif diff --git a/include/linux/amlogic/media/registers/regs/vpp_regs.h b/include/linux/amlogic/media/registers/regs/vpp_regs.h index 447a1ef6fb44..c82b4bad29fe 100644 --- a/include/linux/amlogic/media/registers/regs/vpp_regs.h +++ b/include/linux/amlogic/media/registers/regs/vpp_regs.h @@ -190,6 +190,9 @@ #define VPP_OSD_SCALE_COEF 0x1dcd #define VPP_INT_LINE_NUM 0x1dce +#define VPP_CLIP_MISC0 0x1dd9 +#define VPP_CLIP_MISC1 0x1dda + #define VPP2_MISC 0x1e26 #define VPP2_OFIFO_SIZE 0x1e27 #define VPP2_INT_LINE_NUM 0x1e20 @@ -206,6 +209,8 @@ #define SRSHARP1_SHARP_DNLP_EN 0x32c5 #define SRSHARP1_SHARP_SR2_CTRL 0x32d7 +#define VPP_POST_MATRIX_SAT 0x32c1 + /* g12a vd2 pps */ #define VD2_SCALE_COEF_IDX 0x3943 #define VD2_SCALE_COEF 0x3944 diff --git a/include/linux/amlogic/media/vfm/vframe.h b/include/linux/amlogic/media/vfm/vframe.h index 59cb9b600e8f..c2936f3f3eca 100644 --- a/include/linux/amlogic/media/vfm/vframe.h +++ b/include/linux/amlogic/media/vfm/vframe.h @@ -159,6 +159,55 @@ struct vframe_master_display_colour_s { content_light_level; }; /* master_display_colour_info_volume from SEI */ +struct vframe_hdr_plus_sei_s { + u16 present_flag; + u16 itu_t_t35_country_code; + u16 itu_t_t35_terminal_provider_code; + u16 itu_t_t35_terminal_provider_oriented_code; + u16 application_identifier; + u16 application_version; + /*num_windows max is 3*/ + u16 num_windows; + /*windows xy*/ + u16 window_upper_left_corner_x[3]; + u16 window_upper_left_corner_y[3]; + u16 window_lower_right_corner_x[3]; + u16 window_lower_right_corner_y[3]; + u16 center_of_ellipse_x[3]; + u16 center_of_ellipse_y[3]; + u16 rotation_angle[3]; + u16 semimajor_axis_internal_ellipse[3]; + u16 semimajor_axis_external_ellipse[3]; + u16 semiminor_axis_external_ellipse[3]; + u16 overlap_process_option[3]; + /*target luminance*/ + u32 tgt_sys_disp_max_lumi; + u16 tgt_sys_disp_act_pk_lumi_flag; + u16 num_rows_tgt_sys_disp_act_pk_lumi; + u16 num_cols_tgt_sys_disp_act_pk_lumi; + u16 tgt_sys_disp_act_pk_lumi[25][25]; + + /*num_windows max is 3, e.g maxscl[num_windows][i];*/ + u32 maxscl[3][3]; + u32 average_maxrgb[3]; + u16 num_distribution_maxrgb_percentiles[3]; + u16 distribution_maxrgb_percentages[3][15]; + u32 distribution_maxrgb_percentiles[3][15]; + u16 fraction_bright_pixels[3]; + + u16 mast_disp_act_pk_lumi_flag; + u16 num_rows_mast_disp_act_pk_lumi; + u16 num_cols_mast_disp_act_pk_lumi; + u16 mast_disp_act_pk_lumi[25][25]; + /*num_windows max is 3, e.g knee_point_x[num_windows]*/ + u16 tone_mapping_flag[3]; + u16 knee_point_x[3]; + u16 knee_point_y[3]; + u16 num_bezier_curve_anchors[3]; + u16 bezier_curve_anchors[3][15]; + u16 color_saturation_mapping_flag[3]; + u16 color_saturation_weight[3]; +}; /* vframe properties */ struct vframe_prop_s { struct vframe_hist_s hist; diff --git a/include/linux/amlogic/media/vout/hdmi_tx/hdmi_info_global.h b/include/linux/amlogic/media/vout/hdmi_tx/hdmi_info_global.h index 4bc17773871c..ca037ef68284 100644 --- a/include/linux/amlogic/media/vout/hdmi_tx/hdmi_info_global.h +++ b/include/linux/amlogic/media/vout/hdmi_tx/hdmi_info_global.h @@ -131,42 +131,6 @@ enum hdcp_authstate { HDCP_MAX }; -enum hdcp_ver_e { - HDCPVER_NONE = 0, - HDCPVER_14, - HDCPVER_22, -}; - -#define HDCP14_MAX_KSV_LISTS 127 -struct hdcprp14_topo { - unsigned char max_cascade_exceeded:1; - unsigned char depth:3; - unsigned char max_devs_exceeded:1; - unsigned char device_count:7; /* 1 ~ 127 */ - unsigned char ksv_list[HDCP14_MAX_KSV_LISTS * 5]; -}; - -#define HDCP22_MAX_KSV_LISTS 31 -struct hdcprp22_topo { - int depth; - int device_count; - int v1_X_device_down; - int v2_0_repeater_down; - int max_devs_exceeded; - int max_cascade_exceeded; - unsigned char id_num; - unsigned char id_lists[HDCP22_MAX_KSV_LISTS * 5]; -}; - -struct hdcprp_topo { - /* hdcp_ver currently used */ - enum hdcp_ver_e hdcp_ver; - union { - struct hdcprp14_topo topo14; - struct hdcprp22_topo topo22; - } topo; -}; - /* -----------------------HDCP END---------------------------------------- */ /* -----------------------HDMI TX---------------------------------- */ diff --git a/include/linux/amlogic/media/vout/hdmi_tx/hdmi_rptx.h b/include/linux/amlogic/media/vout/hdmi_tx/hdmi_rptx.h new file mode 100644 index 000000000000..3b1d9813bcb0 --- /dev/null +++ b/include/linux/amlogic/media/vout/hdmi_tx/hdmi_rptx.h @@ -0,0 +1,29 @@ +/* + * include/linux/amlogic/media/vout/hdmi_tx/hdmi_rptx.h + * + * Copyright (C) 2017 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ + +#ifndef _HDMI_RPTX_H_ +#define _HDMI_RPTX_H_ + +enum rptx_hdcp14_cmd { + RPTX_HDCP14_OFF, + RPTX_HDCP14_ON, + RPTX_HDCP14_GET_AUTHST, +}; + +extern void direct_hdcptx14_opr(enum rptx_hdcp14_cmd cmd, void *args); + +#endif diff --git a/include/linux/amlogic/media/vout/hdmi_tx/hdmi_tx_cec_20.h b/include/linux/amlogic/media/vout/hdmi_tx/hdmi_tx_cec_20.h index 8689c9849a60..2e46deb17d8e 100644 --- a/include/linux/amlogic/media/vout/hdmi_tx/hdmi_tx_cec_20.h +++ b/include/linux/amlogic/media/vout/hdmi_tx/hdmi_tx_cec_20.h @@ -314,6 +314,7 @@ struct cec_global_info_t { unsigned int cec_version; unsigned char power_status; unsigned char log_addr; + unsigned int addr_enable; unsigned char menu_status; unsigned char osd_name[16]; struct input_dev *remote_cec_dev; /* cec input device */ diff --git a/include/linux/amlogic/media/vout/hdmi_tx/hdmi_tx_module.h b/include/linux/amlogic/media/vout/hdmi_tx/hdmi_tx_module.h index 366e2049398c..5ef3d54b0b54 100644 --- a/include/linux/amlogic/media/vout/hdmi_tx/hdmi_tx_module.h +++ b/include/linux/amlogic/media/vout/hdmi_tx/hdmi_tx_module.h @@ -65,6 +65,12 @@ struct rx_audiocap { unsigned char cc3; }; +#define MAX_RAW_LEN 64 +struct raw_block { + int len; + char raw[MAX_RAW_LEN]; +}; + enum hd_ctrl { VID_EN, VID_DIS, AUD_EN, AUD_DIS, EDID_EN, EDID_DIS, HDCP_EN, HDCP_DIS, }; @@ -145,6 +151,8 @@ struct rx_cap { unsigned char dtd_idx; unsigned char flag_vfpdb; unsigned char number_of_dtd; + struct raw_block asd; + struct raw_block vsd; /*blk0 check sum*/ unsigned char blk0_chksum; }; @@ -232,6 +240,48 @@ struct hdmitx_clk_tree_s { struct clk *venci_1_gate; }; +/* 2kB should be enough to record */ +#define HDCP_LOG_SIZE (1024 * 2) +struct hdcplog_buf { + int idx; + unsigned char buf[HDCP_LOG_SIZE + 64]; /* padding 8 bytes */ +}; + +enum hdcp_ver_e { + HDCPVER_NONE = 0, + HDCPVER_14, + HDCPVER_22, +}; + +#define MAX_KSV_LISTS 127 +struct hdcprp14_topo { + unsigned char max_cascade_exceeded:1; + unsigned char depth:3; + unsigned char max_devs_exceeded:1; + unsigned char device_count:7; /* 1 ~ 127 */ + unsigned char ksv_list[MAX_KSV_LISTS * 5]; +}; + +struct hdcprp22_topo { + unsigned int depth; + unsigned int device_count; + unsigned int v1_X_device_down; + unsigned int v2_0_repeater_down; + unsigned int max_devs_exceeded; + unsigned int max_cascade_exceeded; + unsigned char id_num; + unsigned char id_lists[MAX_KSV_LISTS * 5]; +}; + +struct hdcprp_topo { + /* hdcp_ver currently used */ + enum hdcp_ver_e hdcp_ver; + union { + struct hdcprp14_topo topo14; + struct hdcprp22_topo topo22; + } topo; +}; + #define EDID_MAX_BLOCK 4 #define HDMI_TMP_BUF_SIZE 1024 struct hdmitx_dev { @@ -259,7 +309,6 @@ struct hdmitx_dev { struct delayed_work cec_work; #endif struct timer_list hdcp_timer; - int hdcp_try_times; int chip_type; int hdmi_init; int hpdmode; @@ -269,7 +318,6 @@ struct hdmitx_dev { int ready; /* 1, hdmi stable output, others are 0 */ int hdcp_hpd_stick; /* 1 not init & reset at plugout */ int hdcp_tst_sig; - bool hdcp22_type; unsigned int div40; unsigned int lstore; struct { @@ -335,6 +383,9 @@ struct hdmitx_dev { /**/ unsigned char hpd_event; /* 1, plugin; 2, plugout */ unsigned char hpd_state; /* 1, connect; 0, disconnect */ + unsigned char rhpd_state; /* For repeater use only, no delay */ + unsigned char hdcp_max_exceed_state; + unsigned int hdcp_max_exceed_cnt; unsigned char force_audio_flag; unsigned char mux_hpd_if_pin_high_flag; int auth_process_timer; @@ -352,6 +403,7 @@ struct hdmitx_dev { unsigned int output_blank_flag; unsigned int audio_notify_flag; unsigned int audio_step; + bool hdcp22_type; unsigned int repeater_tx; struct hdcprp_topo *topo_info; /* 0.1% clock shift, 1080p60hz->59.94hz */ @@ -401,6 +453,7 @@ struct hdmitx_dev { #define HDCP14_OFF 0x2 #define HDCP22_ON 0x3 #define HDCP22_OFF 0x4 +#define DDC_IS_HDCP_ON (CMD_DDC_OFFSET + 0x04) #define DDC_HDCP_GET_AKSV (CMD_DDC_OFFSET + 0x05) #define DDC_HDCP_GET_BKSV (CMD_DDC_OFFSET + 0x06) #define DDC_HDCP_GET_AUTH (CMD_DDC_OFFSET + 0x07) @@ -408,6 +461,7 @@ struct hdmitx_dev { #define PIN_MUX 0x1 #define PIN_UNMUX 0x2 #define DDC_EDID_READ_DATA (CMD_DDC_OFFSET + 0x0a) +#define DDC_IS_EDID_DATA_READY (CMD_DDC_OFFSET + 0x0b) #define DDC_EDID_GET_DATA (CMD_DDC_OFFSET + 0x0c) #define DDC_EDID_CLEAR_RAM (CMD_DDC_OFFSET + 0x0d) #define DDC_HDCP_MUX_INIT (CMD_DDC_OFFSET + 0x0e) @@ -417,6 +471,7 @@ struct hdmitx_dev { #define DDC_HDCP14_GET_BCAPS_RP (CMD_DDC_OFFSET + 0x30) #define DDC_HDCP14_GET_TOPO_INFO (CMD_DDC_OFFSET + 0x31) #define DDC_HDCP_SET_TOPO_INFO (CMD_DDC_OFFSET + 0x32) +#define DDC_HDCP14_SAVE_OBS (CMD_DDC_OFFSET + 0x40) /*********************************************************************** * CONFIG CONTROL //CntlConfig @@ -487,6 +542,7 @@ struct hdmitx_dev { #define MISC_HDCP_CLKDIS (CMD_MISC_OFFSET + 0x0e) #define MISC_TMDS_RXSENSE (CMD_MISC_OFFSET + 0x0f) #define MISC_I2C_REACTIVE (CMD_MISC_OFFSET + 0x10) +#define MISC_READ_AVMUTE_OP (CMD_MISC_OFFSET + 0x11) /*********************************************************************** * Get State //GetState @@ -574,16 +630,6 @@ void __attribute__((weak))rx_set_receiver_edid(unsigned char *data, int len) { } -/* - * ver = 22 means downstream supports HDCP22 - * ver = 14 means support HDCP14 - * ver = 0 means support NO HDCP - */ -extern void rx_repeat_hdcp_ver(unsigned int ver); -void __attribute__((weak))rx_repeat_hdcp_ver(unsigned int ver) -{ -} - extern void rx_set_receive_hdcp(unsigned char *data, int len, int depth, bool max_cascade, bool max_devs); void __attribute__((weak))rx_set_receive_hdcp(unsigned char *data, int len, diff --git a/include/linux/amlogic/media/vout/lcd/aml_bl.h b/include/linux/amlogic/media/vout/lcd/aml_bl.h index a83f80ebb7d3..67b65e1072ce 100644 --- a/include/linux/amlogic/media/vout/lcd/aml_bl.h +++ b/include/linux/amlogic/media/vout/lcd/aml_bl.h @@ -24,7 +24,7 @@ #include #define BLPR(fmt, args...) pr_info("bl: "fmt"", ## args) -#define BLERR(fmt, args...) pr_err("bl error: "fmt"", ## args) +#define BLERR(fmt, args...) pr_err("bl error: "fmt"", ## args) #define AML_BL_NAME "aml-bl" #define BL_LEVEL_MAX 255 @@ -42,7 +42,6 @@ #define BL_FREQ_VS_DEFAULT 2 /* multiple 2 of vfreq */ enum bl_chip_type_e { - BL_CHIP_GXTVBB, BL_CHIP_GXL, BL_CHIP_GXM, BL_CHIP_TXL, @@ -50,6 +49,7 @@ enum bl_chip_type_e { BL_CHIP_AXG, BL_CHIP_G12A, BL_CHIP_G12B, + BL_CHIP_TL1, BL_CHIP_MAX, }; @@ -183,7 +183,7 @@ struct aml_bl_drv_s { struct workqueue_struct *workqueue; struct delayed_work bl_delayed_work; struct resource *res_ldim_vsync_irq; - struct resource *res_ldim_rdma_irq; + /*struct resource *res_ldim_rdma_irq;*/ }; extern struct aml_bl_drv_s *aml_bl_get_driver(void); diff --git a/include/linux/amlogic/media/vout/lcd/aml_ldim.h b/include/linux/amlogic/media/vout/lcd/aml_ldim.h index b864623f2d12..72cf7efd8ca8 100644 --- a/include/linux/amlogic/media/vout/lcd/aml_ldim.h +++ b/include/linux/amlogic/media/vout/lcd/aml_ldim.h @@ -34,11 +34,6 @@ #define LD_DATA_MIN 10 #define LD_DATA_MAX 0xfff -extern int dirspi_write(struct spi_device *spi, u8 *buf, int len); -extern int dirspi_read(struct spi_device *spi, u8 *buf, int len); -extern void dirspi_start(struct spi_device *spi); -extern void dirspi_stop(struct spi_device *spi); - #define _VE_LDIM 'C' /* VPP.ldim IOCTL command list */ @@ -120,8 +115,8 @@ struct aml_ldim_driver_s { void (*test_ctrl)(int flag); struct pinctrl *pin; struct device *dev; - struct spi_device *spi; - struct spi_board_info *spi_dev; + struct spi_device *spi_dev; + struct spi_board_info *spi_info; }; struct ldim_param_s { diff --git a/include/linux/amlogic/media/vout/lcd/lcd_unifykey.h b/include/linux/amlogic/media/vout/lcd/lcd_unifykey.h index 70e2efbcca1f..2204c6c2f10b 100644 --- a/include/linux/amlogic/media/vout/lcd/lcd_unifykey.h +++ b/include/linux/amlogic/media/vout/lcd/lcd_unifykey.h @@ -253,6 +253,9 @@ extern int lcd_unifykey_header_check(unsigned char *buf, struct aml_lcd_unifykey_header_s *header); extern int lcd_unifykey_get(char *key_name, unsigned char *buf, int *len); +extern int lcd_unifykey_check_no_header(char *key_name); +extern int lcd_unifykey_get_no_header(char *key_name, + unsigned char *buf, int *len); extern void lcd_unifykey_print(void); #endif diff --git a/include/linux/amlogic/media/vout/lcd/lcd_vout.h b/include/linux/amlogic/media/vout/lcd/lcd_vout.h index 7348da45f505..ebf689fd44db 100644 --- a/include/linux/amlogic/media/vout/lcd/lcd_vout.h +++ b/include/linux/amlogic/media/vout/lcd/lcd_vout.h @@ -81,14 +81,14 @@ enum lcd_mode_e { enum lcd_chip_e { - LCD_CHIP_GXTVBB = 0, - LCD_CHIP_GXL, /* 1 */ - LCD_CHIP_GXM, /* 2 */ - LCD_CHIP_TXL, /* 3 */ - LCD_CHIP_TXLX, /* 4 */ - LCD_CHIP_AXG, /* 5 */ - LCD_CHIP_G12A, /* 6 */ - LCD_CHIP_G12B, /* 7 */ + LCD_CHIP_GXL = 0, + LCD_CHIP_GXM, /* 1 */ + LCD_CHIP_TXL, /* 2 */ + LCD_CHIP_TXLX, /* 3 */ + LCD_CHIP_AXG, /* 4 */ + LCD_CHIP_G12A, /* 5 */ + LCD_CHIP_G12B, /* 6 */ + LCD_CHIP_TL1, /* 7 */ LCD_CHIP_MAX, }; @@ -103,6 +103,8 @@ enum lcd_type_e { LCD_LVDS, LCD_VBYONE, LCD_MIPI, + LCD_MLVDS, + LCD_P2P, LCD_TYPE_MAX, }; @@ -316,11 +318,47 @@ struct dsi_config_s { struct dsi_read_s *dread; }; +struct mlvds_config_s { + unsigned int channel_num; + unsigned int channel_sel0; + unsigned int channel_sel1; + unsigned int clk_phase; /* [13:12]=clk01_pi_sel, + * [11:8]=pi2, [7:4]=pi1, [3:0]=pi0 + */ + unsigned int pn_swap; + unsigned int bit_swap; /* MSB/LSB reverse */ + unsigned int phy_vswing; + unsigned int phy_preem; + + /* internal used */ + unsigned int pi_clk_sel; /* bit[9:0] */ + unsigned int bit_rate; /* Hz */ +}; + +struct p2p_config_s { + unsigned int channel_num; + unsigned int channel_sel0; + unsigned int channel_sel1; + unsigned int clk_phase; /* [13:12]=clk01_pi_sel, + * [11:8]=pi2, [7:4]=pi1, [3:0]=pi0 + */ + unsigned int pn_swap; + unsigned int bit_swap; /* MSB/LSB reverse */ + unsigned int phy_vswing; + unsigned int phy_preem; + + /* internal used */ + unsigned int pi_clk_sel; /* bit[9:0] */ + unsigned int bit_rate; /* Hz */ +}; + struct lcd_control_config_s { struct ttl_config_s *ttl_config; struct lvds_config_s *lvds_config; struct vbyone_config_s *vbyone_config; struct dsi_config_s *mipi_config; + struct mlvds_config_s *mlvds_config; + struct p2p_config_s *p2p_config; unsigned int *vlock_param; }; @@ -382,11 +420,6 @@ struct lcd_power_ctrl_s { int power_off_step_max; /* internal use for debug */ }; -struct lcd_clk_gate_ctrl_s { - struct reset_control *encl; - struct reset_control *vencl; -}; - #define LCD_ENABLE_RETRY_MAX 3 struct lcd_config_s { char *lcd_propname; @@ -402,7 +435,6 @@ struct lcd_config_s { unsigned char change_flag; unsigned char retry_enable_flag; unsigned char retry_enable_cnt; - struct lcd_clk_gate_ctrl_s rstc; }; struct lcd_duration_s { @@ -436,17 +468,6 @@ struct aml_lcd_drv_s { unsigned char viu_sel; unsigned char vsync_none_timer_flag; - unsigned char clk_gate_state; - struct clk *encl_top_gate; - struct clk *encl_int_gate; - - struct clk *dsi_host_gate; - struct clk *dsi_phy_gate; - struct clk *dsi_meas; - struct clk *mipi_enable_gate; - struct clk *mipi_bandgap_gate; - struct clk *gp0_pll; - struct device *dev; struct lcd_config_s *lcd_config; struct vinfo_s *lcd_info; @@ -472,6 +493,7 @@ struct aml_lcd_drv_s { struct resource *res_vsync_irq; struct resource *res_vsync2_irq; struct resource *res_vx1_irq; + struct resource *res_tcon_irq; struct mutex power_mutex; }; diff --git a/include/linux/amlogic/media/vout/vinfo.h b/include/linux/amlogic/media/vout/vinfo.h index 871d9bb248bc..dfafcaf6d2a6 100644 --- a/include/linux/amlogic/media/vout/vinfo.h +++ b/include/linux/amlogic/media/vout/vinfo.h @@ -168,6 +168,7 @@ enum block_type { ERROR_NULL = 0, ERROR_LENGTH, ERROR_OUI, + ERROR_VER, CORRECT, }; diff --git a/include/linux/amlogic/media/vout/vout_notify.h b/include/linux/amlogic/media/vout/vout_notify.h index c19e2fde61ea..9f31155f5d60 100644 --- a/include/linux/amlogic/media/vout/vout_notify.h +++ b/include/linux/amlogic/media/vout/vout_notify.h @@ -46,6 +46,7 @@ struct vout_op_s { int (*set_vframe_rate_end_hint)(void); int (*set_vframe_rate_policy)(int); int (*get_vframe_rate_policy)(void); + void (*set_bist)(unsigned int); int (*vout_suspend)(void); int (*vout_resume)(void); int (*vout_shutdown)(void); @@ -74,6 +75,7 @@ extern int set_vframe_rate_hint(int duration); extern int set_vframe_rate_end_hint(void); extern int set_vframe_rate_policy(int pol); extern int get_vframe_rate_policy(void); +extern void set_vout_bist(unsigned int bist); #ifdef CONFIG_AMLOGIC_VOUT2_SERVE extern int vout2_register_client(struct notifier_block *p); @@ -88,6 +90,7 @@ extern int set_vframe2_rate_hint(int duration); extern int set_vframe2_rate_end_hint(void); extern int set_vframe2_rate_policy(int pol); extern int get_vframe2_rate_policy(void); +extern void set_vout2_bist(unsigned int bist); #endif diff --git a/include/linux/amlogic/media/vpu/vpu.h b/include/linux/amlogic/media/vpu/vpu.h index dac73eeab268..674b44bacb5f 100644 --- a/include/linux/amlogic/media/vpu/vpu.h +++ b/include/linux/amlogic/media/vpu/vpu.h @@ -59,13 +59,14 @@ enum vpu_mod_e { VPU_VENCP, /* reg1[21:20] //common */ VPU_VENCL, /* reg1[23:22] //common */ VPU_VENCI, /* reg1[25:24] //common */ + VPU_LS_STTS, /* reg1[27:26] //tl1 */ VPU_LDIM_STTS, /* reg1[29:28] //GXTVBB, GXL, TXL, TXLX */ VPU_TV_DEC_CVD2, /* reg1[29:28] */ VPU_XVYCC_LUT, /* reg1[31:30] //GXTVBB, GXL, TXL, TXLX */ VPU_VD2_OSD2_SCALE, /* reg1[31:30] //G12A */ VPU_VIU_WM, /* reg2[1:0] //GXL, TXL, TXLX */ - VPU_TCON, /* reg2[3:2] //TXHD */ + VPU_TCON, /* reg2[3:2] //TXHD, TL1 */ VPU_VIU_OSD3, /* reg2[5:4] //G12A */ VPU_VIU_OSD4, /* reg2[7:6] //G12A */ VPU_MAIL_AFBCD, /* reg2[9:8] //G12A */ @@ -73,10 +74,16 @@ enum vpu_mod_e { VPU_OSD_BLD34, /* reg2[13:12] //G12A */ VPU_PRIME_DOLBY_RAM, /* reg2[15:14] //G12A */ VPU_VD2_OFIFO, /* reg2[17:16] //G12A */ + VPU_DS, /* reg2[19:18] //TL1 */ VPU_LUT3D, /* reg2[21:20] //G12B */ VPU_VIU2_OSD_ROT, /* reg2[23:22] //G12B */ + VPU_VI_DIPRE, /* reg2[27:24] //TL1 */ VPU_RDMA, /* reg2[31:30] //G12A */ + VPU_AXI_WR1, /* reg4[1:0] //TL1 */ + VPU_AXI_WR0, /* reg4[3:2] //TL1 */ + VPU_AFBCE, /* reg4[5:4] //TL1 */ + VPU_MOD_MAX, /* for clk_gate */ diff --git a/include/linux/amlogic/reboot.h b/include/linux/amlogic/reboot.h index de8c6902202d..bf502233d76a 100644 --- a/include/linux/amlogic/reboot.h +++ b/include/linux/amlogic/reboot.h @@ -25,5 +25,7 @@ #define MESON_HIBERNATE 6 #define MESON_BOOTLOADER_REBOOT 7 #define MESON_RPMBP_REBOOT 9 +#define MESON_QUIESCENT_REBOOT 10 #define MESON_CRASH_REBOOT 11 #define MESON_KERNEL_PANIC 12 +#define MESON_RECOVERY_QUIESCENT_REBOOT 14 diff --git a/include/linux/amlogic/sd.h b/include/linux/amlogic/sd.h index 0282f8675fff..0d4e24ddb05f 100644 --- a/include/linux/amlogic/sd.h +++ b/include/linux/amlogic/sd.h @@ -278,6 +278,7 @@ struct amlsd_platform { unsigned int dly1; unsigned int dly2; unsigned int intf3; + unsigned int irq_sdio_sleep; unsigned int clock; /* signalling voltage (1.8V or 3.3V) */ unsigned char signal_voltage; @@ -294,6 +295,7 @@ struct amlsd_platform { unsigned int gpio_cd_sta; unsigned int gpio_power; unsigned int power_level; + unsigned int calc_f; unsigned int auto_clk_close; unsigned int vol_switch; diff --git a/include/linux/cma.h b/include/linux/cma.h index 29f9e774ab76..1c93d65d14cc 100644 --- a/include/linux/cma.h +++ b/include/linux/cma.h @@ -28,4 +28,10 @@ extern int cma_init_reserved_mem(phys_addr_t base, phys_addr_t size, struct cma **res_cma); extern struct page *cma_alloc(struct cma *cma, size_t count, unsigned int align); extern bool cma_release(struct cma *cma, const struct page *pages, unsigned int count); +#ifdef CONFIG_AMLOGIC_CMA +extern void cma_init_clear(struct cma *cma, bool clear); +extern int setup_cma_full_pagemap(struct cma *cma); +extern int cma_mmu_op(struct page *page, int count, bool set); +#endif + #endif diff --git a/include/uapi/linux/dvb/frontend.h b/include/uapi/linux/dvb/frontend.h index cf8df3d6ed7c..e851a304aee6 100644 --- a/include/uapi/linux/dvb/frontend.h +++ b/include/uapi/linux/dvb/frontend.h @@ -541,6 +541,7 @@ struct dtv_property { __u32 reserved1[3]; void *reserved2; } buffer; +#if 0 #ifdef CONFIG_AMLOGIC_DVB_COMPAT struct { __u8 data[32]; @@ -548,6 +549,7 @@ struct dtv_property { __u32 reserved1[3]; __u64 reserved; } reserved; +#endif #endif } u; int result; @@ -558,7 +560,7 @@ struct dtv_property { struct dtv_properties { __u32 num; -#ifdef CONFIG_AMLOGIC_DVB_COMPAT +#if 0 && defined(CONFIG_AMLOGIC_DVB_COMPAT) union { struct dtv_property *props; __u64 reserved; @@ -661,7 +663,7 @@ struct dvb_frontend_parameters { struct dvb_qam_parameters qam; /* DVB-C */ struct dvb_ofdm_parameters ofdm; /* DVB-T */ struct dvb_vsb_parameters vsb; /* ATSC */ -#ifdef CONFIG_AMLOGIC_DVB_COMPAT +#if 0 && defined(CONFIG_AMLOGIC_DVB_COMPAT) struct dvb_analog_parameters analog; #endif } u; @@ -683,10 +685,12 @@ struct dvb_frontend_parameters_ex { } u; }; +/* static char dvb_check_frontend_parameters_size[ (sizeof(struct dvb_frontend_parameters_ex) == sizeof(struct dvb_frontend_parameters)) ? 1 : -1] __attribute__((__unused__)); +*/ #endif /*CONFIG_AMLOGIC_DVB_COMPAT*/ diff --git a/mm/cma.c b/mm/cma.c index 5c2c466adadb..23d978dbbe16 100644 --- a/mm/cma.c +++ b/mm/cma.c @@ -37,6 +37,7 @@ #include #include #ifdef CONFIG_AMLOGIC_CMA +#include #include #endif /* CONFIG_AMLOGIC_CMA */ @@ -46,6 +47,127 @@ struct cma cma_areas[MAX_CMA_AREAS]; unsigned cma_area_count; static DEFINE_MUTEX(cma_mutex); +#ifdef CONFIG_AMLOGIC_CMA +void cma_init_clear(struct cma *cma, bool clear) +{ + cma->clear_map = clear; +} + +#ifdef CONFIG_ARM64 +static int clear_cma_pagemap2(struct cma *cma) +{ + pgd_t *pgd; + pud_t *pud; + pmd_t *pmd; + unsigned long addr, end; + struct mm_struct *mm; + + addr = (unsigned long)pfn_to_kaddr(cma->base_pfn); + end = addr + cma->count * PAGE_SIZE; + mm = &init_mm; + for (; addr < end; addr += SECTION_SIZE) { + pgd = pgd_offset(mm, addr); + if (pgd_none(*pgd) || pgd_bad(*pgd)) + break; + + pud = pud_offset(pgd, addr); + if (pud_none(*pud) || pud_bad(*pud)) + break; + + pmd = pmd_offset(pud, addr); + if (pmd_none(*pmd)) + break; + + pr_debug("%s, addr:%lx, pgd:%p %llx, pmd:%p %llx\n", + __func__, addr, pgd, pgd_val(*pgd), pmd, pmd_val(*pmd)); + pmd_clear(pmd); + } + + return 0; +} +#endif + +int setup_cma_full_pagemap(struct cma *cma) +{ +#ifdef CONFIG_ARM + /* + * arm already create level 3 mmu mapping for lowmem cma. + * And if high mem cma, there is no mapping. So nothing to + * do for arch arm. + */ + return 0; +#elif defined(CONFIG_ARM64) + struct vm_area_struct vma = {}; + unsigned long addr, size; + int ret; + + clear_cma_pagemap2(cma); + addr = (unsigned long)pfn_to_kaddr(cma->base_pfn); + size = cma->count * PAGE_SIZE; + vma.vm_mm = &init_mm; + vma.vm_start = addr; + vma.vm_end = addr + size; + vma.vm_page_prot = PAGE_KERNEL; + ret = remap_pfn_range(&vma, addr, cma->base_pfn, + size, vma.vm_page_prot); + if (ret < 0) + pr_info("%s, remap pte failed:%d, cma:%lx\n", + __func__, ret, cma->base_pfn); + return 0; +#else + #error "NOT supported ARCH" +#endif +} + +int cma_mmu_op(struct page *page, int count, bool set) +{ + pgd_t *pgd; + pud_t *pud; + pmd_t *pmd; + pte_t *pte; + unsigned long addr, end; + struct mm_struct *mm; + + if (!page || PageHighMem(page)) + return -EINVAL; + + addr = (unsigned long)page_address(page); + end = addr + count * PAGE_SIZE; + mm = &init_mm; + for (; addr < end; addr += PAGE_SIZE) { + pgd = pgd_offset(mm, addr); + if (pgd_none(*pgd) || pgd_bad(*pgd)) + break; + + pud = pud_offset(pgd, addr); + if (pud_none(*pud) || pud_bad(*pud)) + break; + + pmd = pmd_offset(pud, addr); + if (pmd_none(*pmd)) + break; + + pte = pte_offset_map(pmd, addr); + if (set) + set_pte_at(mm, addr, pte, mk_pte(page, PAGE_KERNEL)); + else + pte_clear(mm, addr, pte); + pte_unmap(pte); + #ifdef CONFIG_ARM + pr_debug("%s, add:%lx, pgd:%p %x, pmd:%p %x, pte:%p %x\n", + __func__, addr, pgd, (int)pgd_val(*pgd), + pmd, (int)pmd_val(*pmd), pte, (int)pte_val(*pte)); + #elif defined(CONFIG_ARM64) + pr_debug("%s, add:%lx, pgd:%p %llx, pmd:%p %llx, pte:%p %llx\n", + __func__, addr, pgd, pgd_val(*pgd), + pmd, pmd_val(*pmd), pte, pte_val(*pte)); + #endif + page++; + } + return 0; +} +#endif + phys_addr_t cma_get_base(const struct cma *cma) { return PFN_PHYS(cma->base_pfn); @@ -129,6 +251,11 @@ static int __init cma_activate_area(struct cma *cma) mutex_init(&cma->lock); +#ifdef CONFIG_AMLOGIC_CMA + if (cma->clear_map) + setup_cma_full_pagemap(cma); +#endif + #ifdef CONFIG_CMA_DEBUGFS INIT_HLIST_HEAD(&cma->mem_head); spin_lock_init(&cma->mem_head_lock); diff --git a/mm/cma.h b/mm/cma.h index 17c75a4246c8..bd5a7a55cb45 100644 --- a/mm/cma.h +++ b/mm/cma.h @@ -11,6 +11,11 @@ struct cma { struct hlist_head mem_head; spinlock_t mem_head_lock; #endif + +#ifdef CONFIG_AMLOGIC_CMA /* clear kernel space mapping after driver it */ + bool clear_map; +#endif + }; extern struct cma cma_areas[MAX_CMA_AREAS]; diff --git a/mm/compaction.c b/mm/compaction.c index b24f499431fc..2d9ee59ff2b1 100644 --- a/mm/compaction.c +++ b/mm/compaction.c @@ -648,6 +648,25 @@ static bool too_many_isolated(struct zone *zone) return isolated > (inactive + active) / 2; } +#ifdef CONFIG_AMLOGIC_CMA +static void check_page_to_cma(struct compact_control *cc, struct page *page) +{ + struct address_space *mapping; + + if (cc->forbid_to_cma) /* no need check once it is true */ + return; + + mapping = page_mapping(page); + if ((unsigned long)mapping & PAGE_MAPPING_ANON) + mapping = NULL; + + if (PageKsm(page) && !PageSlab(page)) + cc->forbid_to_cma = true; + + if (mapping && cma_forbidden_mask(mapping_gfp_mask(mapping))) + cc->forbid_to_cma = true; +} +#endif /** * isolate_migratepages_block() - isolate all migrate-able pages within @@ -746,6 +765,9 @@ isolate_migratepages_block(struct compact_control *cc, unsigned long low_pfn, page = pfn_to_page(low_pfn); + #ifdef CONFIG_AMLOGIC_CMA + check_page_to_cma(cc, page); + #endif if (!valid_page) valid_page = page; @@ -1098,7 +1120,7 @@ static void isolate_freepages(struct compact_control *cc) migrate_type = get_pageblock_migratetype(page); if (is_migrate_isolate(migrate_type)) continue; - if (is_migrate_cma(migrate_type) && cma_alloc_ref()) + if (is_migrate_cma(migrate_type) && cc->forbid_to_cma) continue; #endif /* CONFIG_AMLOGIC_CMA */ /* Found a block suitable for isolating free pages from. */ @@ -1151,16 +1173,6 @@ static struct page *compaction_alloc(struct page *migratepage, { struct compact_control *cc = (struct compact_control *)data; struct page *freepage; -#ifdef CONFIG_AMLOGIC_CMA - struct address_space *mapping; - - mapping = page_mapping(migratepage); - if ((unsigned long)mapping & PAGE_MAPPING_ANON) - mapping = NULL; - - if (mapping && !can_use_cma(mapping_gfp_mask(mapping))) - return alloc_page(mapping_gfp_mask(mapping) | __GFP_BDEV); -#endif /* * Isolate free pages if necessary, and if we are not aborting due to @@ -1558,6 +1570,9 @@ static enum compact_result compact_zone(struct zone *zone, struct compact_contro migrate_prep_local(); +#ifdef CONFIG_AMLOGIC_CMA + cc->forbid_to_cma = false; +#endif while ((ret = compact_finished(zone, cc, migratetype)) == COMPACT_CONTINUE) { int err; diff --git a/mm/page_alloc.c b/mm/page_alloc.c index e79dba92409a..a361ce219f48 100644 --- a/mm/page_alloc.c +++ b/mm/page_alloc.c @@ -2996,7 +2996,9 @@ bool __zone_watermark_ok(struct zone *z, unsigned int order, unsigned long mark, #ifdef CONFIG_CMA /* If allocation can't use CMA areas don't use free CMA pages */ +#ifndef CONFIG_AMLOGIC_CMA /* always sub cma pages to avoid wm all CMA */ if (!(alloc_flags & ALLOC_CMA)) +#endif free_pages -= zone_page_state(z, NR_FREE_CMA_PAGES); #endif diff --git a/scripts/Makefile.lib b/scripts/Makefile.lib index 3029610207b5..c469f4b9115e 100644 --- a/scripts/Makefile.lib +++ b/scripts/Makefile.lib @@ -325,6 +325,11 @@ cmd_dtc = mkdir -p $(dir ${dtc-tmp}) ; \ $(obj)/%.dtb: $(src)/%.dts FORCE $(call if_changed_dep,dtc) +ifeq ($(CONFIG_AMLOGIC_MODIFY),y) +$(obj)/%.dtbo: $(src)/%.dts FORCE + $(call if_changed_dep,dtc) +endif + dtc-tmp = $(subst $(comma),_,$(dot-target).dts.tmp) # cat diff --git a/scripts/amlogic/merge_pre_check.pl b/scripts/amlogic/merge_pre_check.pl index cb3f8b670459..73ce86a1f00e 100755 --- a/scripts/amlogic/merge_pre_check.pl +++ b/scripts/amlogic/merge_pre_check.pl @@ -132,38 +132,69 @@ sub check_msg_49_2 { my $msg = `git cat-file commit HEAD~0 | sed '1,/\^\$/d'`; my @str = split /[\n][\n]/, $msg; + my $i = 0; + my $len = @str; - if( $str[0] !~ /^([\w]+:\s){1,2}.+(\s)\[[\d]\/[\d]\]$/ ) + if( $len < 4 ) + { + $err_cnt += 5; + $err_msg .= " module: message [n/m]\n\n"; + $err_msg .= " PD#XXXX\n\n"; + $err_msg .= " Problem:\n detailed description\n\n"; + $err_msg .= " Solution:\n detailed description\n\n"; + $err_msg .= " Verify:\n detailed description\n\n"; + return -1; + } + + if( $str[$i] !~ /^([\w]+:\s){1,2}.+(\s)\[[\d]\/[\d]\]$/ ) { $err_cnt += 1; - $err_msg .= " $err_cnt: \n"; + $err_msg .= " $err_cnt: module: message\n"; } - elsif( $str[0] =~ /(kernel)/i ) + elsif( $str[$i] =~ /(kernel)/i ) { $err_cnt += 1; $err_msg .= " $err_cnt: Should be no 'kernel' in kernel commit message\n"; } - if( $str[1] !~ /^PD\#.+(\S)$/ ) + if( $str[++ $i] !~ /^PD\#.+(\d)$/ ) { $err_cnt += 1; - $err_msg .= " $err_cnt: \n"; + $err_msg .= " $err_cnt: PD#XXXX\n"; } - if( $str[2] !~ /^Problem:[\n].+/ ) + if( $str[++ $i] !~ /^Problem:[\n].+/ ) { $err_cnt += 1; $err_msg .= " $err_cnt: Problem:\n detailed description\n"; } - if( $str[3] !~ /^Solution:[\n].+/ ) + $i += 1; + while( $str[$i] !~ /^Solution:[\n].+/ && $str[$i] !~ /^Change-Id:/ && $str[$i] !~ /^Verify:[\n].+/ ) + { + $i = $i + 1; + } + + if( $str[$i] !~ /^Solution:[\n].+/ ) { $err_cnt += 1; $err_msg .= " $err_cnt: Solution:\n detailed description\n"; } - if( $str[4] !~ /^Verify:[\n].+/ ) + if( $str[$i] =~ /^Change-Id:/ ) + { + $err_cnt += 1; + $err_msg .= " $err_cnt: Verify:\n detailed description\n"; + return -1; + } + + while( $str[$i] !~ /^Verify:[\n].+/ && $str[$i] !~ /^Change-Id:/ ) + { + $i += 1; + } + + if( $str[$i] !~ /^Verify:[\n].+/ ) { $err_cnt += 1; $err_msg .= " $err_cnt: Verify:\n detailed description\n"; diff --git a/scripts/dtc/checks.c b/scripts/dtc/checks.c index 62ea8f83d4a0..08a3a29edae3 100644 --- a/scripts/dtc/checks.c +++ b/scripts/dtc/checks.c @@ -873,7 +873,7 @@ static void check_simple_bus_reg(struct check *c, struct dt_info *dti, struct no while (size--) reg = (reg << 32) | fdt32_to_cpu(*(cells++)); - snprintf(unit_addr, sizeof(unit_addr), "%llx", (unsigned long long)reg); + snprintf(unit_addr, sizeof(unit_addr), "%"PRIx64, reg); if (!streq(unitname, unit_addr)) FAIL(c, dti, "Node %s simple-bus unit address format error, expected \"%s\"", node->fullpath, unit_addr); @@ -956,6 +956,265 @@ static void check_obsolete_chosen_interrupt_controller(struct check *c, WARNING(obsolete_chosen_interrupt_controller, check_obsolete_chosen_interrupt_controller, NULL); +struct provider { + const char *prop_name; + const char *cell_name; + bool optional; +}; + +static void check_property_phandle_args(struct check *c, + struct dt_info *dti, + struct node *node, + struct property *prop, + const struct provider *provider) +{ + struct node *root = dti->dt; + int cell, cellsize = 0; + + if (prop->val.len % sizeof(cell_t)) { + FAIL(c, dti, "property '%s' size (%d) is invalid, expected multiple of %zu in node %s", + prop->name, prop->val.len, sizeof(cell_t), node->fullpath); + return; + } + + for (cell = 0; cell < prop->val.len / sizeof(cell_t); cell += cellsize + 1) { + struct node *provider_node; + struct property *cellprop; + int phandle; + + phandle = propval_cell_n(prop, cell); + /* + * Some bindings use a cell value 0 or -1 to skip over optional + * entries when each index position has a specific definition. + */ + if (phandle == 0 || phandle == -1) { + cellsize = 0; + continue; + } + + /* If we have markers, verify the current cell is a phandle */ + if (prop->val.markers) { + struct marker *m = prop->val.markers; + for_each_marker_of_type(m, REF_PHANDLE) { + if (m->offset == (cell * sizeof(cell_t))) + break; + } + if (!m) + FAIL(c, dti, "Property '%s', cell %d is not a phandle reference in %s", + prop->name, cell, node->fullpath); + } + + provider_node = get_node_by_phandle(root, phandle); + if (!provider_node) { + FAIL(c, dti, "Could not get phandle node for %s:%s(cell %d)", + node->fullpath, prop->name, cell); + break; + } + + cellprop = get_property(provider_node, provider->cell_name); + if (cellprop) { + cellsize = propval_cell(cellprop); + } else if (provider->optional) { + cellsize = 0; + } else { + FAIL(c, dti, "Missing property '%s' in node %s or bad phandle (referred from %s:%s[%d])", + provider->cell_name, + provider_node->fullpath, + node->fullpath, prop->name, cell); + break; + } + + if (prop->val.len < ((cell + cellsize + 1) * sizeof(cell_t))) { + FAIL(c, dti, "%s property size (%d) too small for cell size %d in %s", + prop->name, prop->val.len, cellsize, node->fullpath); + } + } +} + +static void check_provider_cells_property(struct check *c, + struct dt_info *dti, + struct node *node) +{ + struct provider *provider = c->data; + struct property *prop; + + prop = get_property(node, provider->prop_name); + if (!prop) + return; + + check_property_phandle_args(c, dti, node, prop, provider); +} +#define WARNING_PROPERTY_PHANDLE_CELLS(nm, propname, cells_name, ...) \ + static struct provider nm##_provider = { (propname), (cells_name), __VA_ARGS__ }; \ + WARNING(nm##_property, check_provider_cells_property, &nm##_provider, &phandle_references); + +WARNING_PROPERTY_PHANDLE_CELLS(clocks, "clocks", "#clock-cells"); +WARNING_PROPERTY_PHANDLE_CELLS(cooling_device, "cooling-device", "#cooling-cells"); +WARNING_PROPERTY_PHANDLE_CELLS(dmas, "dmas", "#dma-cells"); +WARNING_PROPERTY_PHANDLE_CELLS(hwlocks, "hwlocks", "#hwlock-cells"); +WARNING_PROPERTY_PHANDLE_CELLS(interrupts_extended, "interrupts-extended", "#interrupt-cells"); +WARNING_PROPERTY_PHANDLE_CELLS(io_channels, "io-channels", "#io-channel-cells"); +WARNING_PROPERTY_PHANDLE_CELLS(iommus, "iommus", "#iommu-cells"); +WARNING_PROPERTY_PHANDLE_CELLS(mboxes, "mboxes", "#mbox-cells"); +WARNING_PROPERTY_PHANDLE_CELLS(msi_parent, "msi-parent", "#msi-cells", true); +WARNING_PROPERTY_PHANDLE_CELLS(mux_controls, "mux-controls", "#mux-control-cells"); +WARNING_PROPERTY_PHANDLE_CELLS(phys, "phys", "#phy-cells"); +WARNING_PROPERTY_PHANDLE_CELLS(power_domains, "power-domains", "#power-domain-cells"); +WARNING_PROPERTY_PHANDLE_CELLS(pwms, "pwms", "#pwm-cells"); +WARNING_PROPERTY_PHANDLE_CELLS(resets, "resets", "#reset-cells"); +WARNING_PROPERTY_PHANDLE_CELLS(sound_dais, "sound-dais", "#sound-dai-cells"); +WARNING_PROPERTY_PHANDLE_CELLS(thermal_sensors, "thermal-sensors", "#thermal-sensor-cells"); + +static bool prop_is_gpio(struct property *prop) +{ + char *str; + + /* + * *-gpios and *-gpio can appear in property names, + * so skip over any false matches (only one known ATM) + */ + if (strstr(prop->name, "nr-gpio")) + return false; + + str = strrchr(prop->name, '-'); + if (str) + str++; + else + str = prop->name; + if (!(streq(str, "gpios") || streq(str, "gpio"))) + return false; + + return true; +} + +static void check_gpios_property(struct check *c, + struct dt_info *dti, + struct node *node) +{ + struct property *prop; + + /* Skip GPIO hog nodes which have 'gpios' property */ + if (get_property(node, "gpio-hog")) + return; + + for_each_property(node, prop) { + struct provider provider; + + if (!prop_is_gpio(prop)) + continue; + + provider.prop_name = prop->name; + provider.cell_name = "#gpio-cells"; + provider.optional = false; + check_property_phandle_args(c, dti, node, prop, &provider); + } + +} +WARNING(gpios_property, check_gpios_property, NULL, &phandle_references); + +static void check_deprecated_gpio_property(struct check *c, + struct dt_info *dti, + struct node *node) +{ + struct property *prop; + + for_each_property(node, prop) { + char *str; + + if (!prop_is_gpio(prop)) + continue; + + str = strstr(prop->name, "gpio"); + if (!streq(str, "gpio")) + continue; + + FAIL(c, dti, "'[*-]gpio' is deprecated, use '[*-]gpios' instead for %s:%s", + node->fullpath, prop->name); + } + +} +CHECK(deprecated_gpio_property, check_deprecated_gpio_property, NULL); + +static bool node_is_interrupt_provider(struct node *node) +{ + struct property *prop; + + prop = get_property(node, "interrupt-controller"); + if (prop) + return true; + + prop = get_property(node, "interrupt-map"); + if (prop) + return true; + + return false; +} +static void check_interrupts_property(struct check *c, + struct dt_info *dti, + struct node *node) +{ + struct node *root = dti->dt; + struct node *irq_node = NULL, *parent = node; + struct property *irq_prop, *prop = NULL; + int irq_cells, phandle; + + irq_prop = get_property(node, "interrupts"); + if (!irq_prop) + return; + + if (irq_prop->val.len % sizeof(cell_t)) + FAIL(c, dti, "property '%s' size (%d) is invalid, expected multiple of %zu in node %s", + irq_prop->name, irq_prop->val.len, sizeof(cell_t), + node->fullpath); + + while (parent && !prop) { + if (parent != node && node_is_interrupt_provider(parent)) { + irq_node = parent; + break; + } + + prop = get_property(parent, "interrupt-parent"); + if (prop) { + phandle = propval_cell(prop); + irq_node = get_node_by_phandle(root, phandle); + if (!irq_node) { + FAIL(c, dti, "Bad interrupt-parent phandle for %s", + node->fullpath); + return; + } + if (!node_is_interrupt_provider(irq_node)) + FAIL(c, dti, + "Missing interrupt-controller or interrupt-map property in %s", + irq_node->fullpath); + + break; + } + + parent = parent->parent; + } + + if (!irq_node) { + FAIL(c, dti, "Missing interrupt-parent for %s", node->fullpath); + return; + } + + prop = get_property(irq_node, "#interrupt-cells"); + if (!prop) { + FAIL(c, dti, "Missing #interrupt-cells in interrupt-parent %s", + irq_node->fullpath); + return; + } + + irq_cells = propval_cell(prop); + if (irq_prop->val.len % (irq_cells * sizeof(cell_t))) { + FAIL(c, dti, + "interrupts size is (%d), expected multiple of %d in %s", + irq_prop->val.len, (int)(irq_cells * sizeof(cell_t)), + node->fullpath); + } +} +WARNING(interrupts_property, check_interrupts_property, &phandle_references); + static struct check *check_table[] = { &duplicate_node_names, &duplicate_property_names, &node_name_chars, &node_name_format, &property_name_chars, @@ -987,6 +1246,27 @@ static struct check *check_table[] = { &avoid_default_addr_size, &obsolete_chosen_interrupt_controller, + &clocks_property, + &cooling_device_property, + &dmas_property, + &hwlocks_property, + &interrupts_extended_property, + &io_channels_property, + &iommus_property, + &mboxes_property, + &msi_parent_property, + &mux_controls_property, + &phys_property, + &power_domains_property, + &pwms_property, + &resets_property, + &sound_dais_property, + &thermal_sensors_property, + + &deprecated_gpio_property, + &gpios_property, + &interrupts_property, + &always_fail, }; diff --git a/scripts/dtc/dtc-lexer.lex.c_shipped b/scripts/dtc/dtc-lexer.lex.c_shipped index 64c243772398..011bb9632ff2 100644 --- a/scripts/dtc/dtc-lexer.lex.c_shipped +++ b/scripts/dtc/dtc-lexer.lex.c_shipped @@ -1397,7 +1397,7 @@ static int yy_get_next_buffer (void) { char *dest = YY_CURRENT_BUFFER_LVALUE->yy_ch_buf; char *source = (yytext_ptr); - yy_size_t number_to_move, i; + int number_to_move, i; int ret_val; if ( (yy_c_buf_p) > &YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[(yy_n_chars) + 1] ) @@ -1426,7 +1426,7 @@ static int yy_get_next_buffer (void) /* Try to read more data. */ /* First move last chars to start of buffer. */ - number_to_move = (yy_size_t) ((yy_c_buf_p) - (yytext_ptr)) - 1; + number_to_move = (int) ((yy_c_buf_p) - (yytext_ptr) - 1); for ( i = 0; i < number_to_move; ++i ) *(dest++) = *(source++); @@ -1508,7 +1508,7 @@ static int yy_get_next_buffer (void) else ret_val = EOB_ACT_CONTINUE_SCAN; - if ((int) ((yy_n_chars) + number_to_move) > YY_CURRENT_BUFFER_LVALUE->yy_buf_size) { + if (((yy_n_chars) + number_to_move) > YY_CURRENT_BUFFER_LVALUE->yy_buf_size) { /* Extend the array by 50%, plus the number we really need. */ int new_size = (yy_n_chars) + number_to_move + ((yy_n_chars) >> 1); YY_CURRENT_BUFFER_LVALUE->yy_ch_buf = (char *) yyrealloc((void *) YY_CURRENT_BUFFER_LVALUE->yy_ch_buf,new_size ); @@ -1987,10 +1987,10 @@ YY_BUFFER_STATE yy_scan_bytes (yyconst char * yybytes, int _yybytes_len ) YY_BUFFER_STATE b; char *buf; yy_size_t n; - yy_size_t i; + int i; /* Get memory for full buffer, including space for trailing EOB's. */ - n = (yy_size_t) _yybytes_len + 2; + n = (yy_size_t) (_yybytes_len + 2); buf = (char *) yyalloc(n ); if ( ! buf ) YY_FATAL_ERROR( "out of dynamic memory in yy_scan_bytes()" ); diff --git a/scripts/dtc/dtc-parser.tab.c_shipped b/scripts/dtc/dtc-parser.tab.c_shipped index 0a7a5ed86f04..aea514fa6928 100644 --- a/scripts/dtc/dtc-parser.tab.c_shipped +++ b/scripts/dtc/dtc-parser.tab.c_shipped @@ -448,7 +448,7 @@ union yyalloc /* YYNNTS -- Number of nonterminals. */ #define YYNNTS 30 /* YYNRULES -- Number of rules. */ -#define YYNRULES 84 +#define YYNRULES 85 /* YYNSTATES -- Number of states. */ #define YYNSTATES 149 @@ -499,14 +499,14 @@ static const yytype_uint8 yytranslate[] = static const yytype_uint16 yyrline[] = { 0, 109, 109, 117, 121, 128, 129, 139, 142, 149, - 153, 161, 165, 170, 181, 191, 206, 214, 217, 224, - 228, 232, 236, 244, 248, 252, 256, 260, 276, 286, - 294, 297, 301, 308, 324, 329, 348, 362, 369, 370, - 371, 378, 382, 383, 387, 388, 392, 393, 397, 398, - 402, 403, 407, 408, 412, 413, 414, 418, 419, 420, - 421, 422, 426, 427, 428, 432, 433, 434, 438, 439, - 448, 457, 461, 462, 463, 464, 469, 472, 476, 484, - 487, 491, 499, 503, 507 + 153, 161, 165, 170, 181, 200, 213, 220, 228, 231, + 238, 242, 246, 250, 258, 262, 266, 270, 274, 290, + 300, 308, 311, 315, 322, 338, 343, 362, 376, 383, + 384, 385, 392, 396, 397, 401, 402, 406, 407, 411, + 412, 416, 417, 421, 422, 426, 427, 428, 432, 433, + 434, 435, 436, 440, 441, 442, 446, 447, 448, 452, + 453, 462, 471, 475, 476, 477, 478, 483, 486, 490, + 498, 501, 505, 513, 517, 521 }; #endif @@ -582,20 +582,20 @@ static const yytype_int8 yypact[] = static const yytype_uint8 yydefact[] = { 0, 0, 0, 5, 7, 3, 1, 6, 0, 0, - 0, 7, 0, 38, 39, 0, 0, 10, 0, 2, - 8, 4, 0, 0, 0, 72, 0, 41, 42, 44, - 46, 48, 50, 52, 54, 57, 64, 67, 71, 0, - 17, 11, 0, 0, 0, 0, 73, 74, 75, 40, + 16, 7, 0, 39, 40, 0, 0, 10, 0, 2, + 8, 4, 0, 0, 0, 73, 0, 42, 43, 45, + 47, 49, 51, 53, 55, 58, 65, 68, 72, 0, + 18, 11, 0, 0, 0, 0, 74, 75, 76, 41, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 9, - 79, 0, 0, 14, 12, 45, 0, 47, 49, 51, - 53, 55, 56, 60, 61, 59, 58, 62, 63, 65, - 66, 69, 68, 70, 0, 0, 0, 0, 18, 0, - 79, 15, 13, 0, 0, 0, 20, 30, 82, 22, - 84, 0, 81, 80, 43, 21, 83, 0, 0, 16, - 29, 19, 31, 0, 23, 32, 26, 0, 76, 34, - 0, 0, 0, 0, 37, 36, 24, 35, 33, 0, - 77, 78, 25, 0, 28, 0, 0, 0, 27 + 80, 0, 0, 14, 12, 46, 0, 48, 50, 52, + 54, 56, 57, 61, 62, 60, 59, 63, 64, 66, + 67, 70, 69, 71, 0, 0, 0, 0, 19, 0, + 80, 15, 13, 0, 0, 0, 21, 31, 83, 23, + 85, 0, 82, 81, 44, 22, 84, 0, 0, 17, + 30, 20, 32, 0, 24, 33, 27, 0, 77, 35, + 0, 0, 0, 0, 38, 37, 25, 36, 34, 0, + 78, 79, 26, 0, 29, 0, 0, 0, 28 }; /* YYPGOTO[NTERM-NUM]. */ @@ -678,28 +678,28 @@ static const yytype_uint8 yystos[] = static const yytype_uint8 yyr1[] = { 0, 48, 49, 50, 50, 51, 51, 52, 52, 53, - 53, 54, 54, 54, 54, 54, 55, 56, 56, 57, - 57, 57, 57, 58, 58, 58, 58, 58, 58, 58, - 59, 59, 59, 60, 60, 60, 60, 60, 61, 61, - 61, 62, 63, 63, 64, 64, 65, 65, 66, 66, - 67, 67, 68, 68, 69, 69, 69, 70, 70, 70, - 70, 70, 71, 71, 71, 72, 72, 72, 73, 73, - 73, 73, 74, 74, 74, 74, 75, 75, 75, 76, - 76, 76, 77, 77, 77 + 53, 54, 54, 54, 54, 54, 54, 55, 56, 56, + 57, 57, 57, 57, 58, 58, 58, 58, 58, 58, + 58, 59, 59, 59, 60, 60, 60, 60, 60, 61, + 61, 61, 62, 63, 63, 64, 64, 65, 65, 66, + 66, 67, 67, 68, 68, 69, 69, 69, 70, 70, + 70, 70, 70, 71, 71, 71, 72, 72, 72, 73, + 73, 73, 73, 74, 74, 74, 74, 75, 75, 75, + 76, 76, 76, 77, 77, 77 }; /* YYR2[YYN] -- Number of symbols on the right hand side of rule YYN. */ static const yytype_uint8 yyr2[] = { 0, 2, 3, 2, 4, 1, 2, 0, 2, 4, - 2, 2, 3, 4, 3, 4, 5, 0, 2, 4, - 2, 3, 2, 2, 3, 4, 2, 9, 5, 2, - 0, 2, 2, 3, 1, 2, 2, 2, 1, 1, - 3, 1, 1, 5, 1, 3, 1, 3, 1, 3, - 1, 3, 1, 3, 1, 3, 3, 1, 3, 3, - 3, 3, 3, 3, 1, 3, 3, 1, 3, 3, - 3, 1, 1, 2, 2, 2, 0, 2, 2, 0, - 2, 2, 2, 3, 2 + 2, 2, 3, 4, 3, 4, 0, 5, 0, 2, + 4, 2, 3, 2, 2, 3, 4, 2, 9, 5, + 2, 0, 2, 2, 3, 1, 2, 2, 2, 1, + 1, 3, 1, 1, 5, 1, 3, 1, 3, 1, + 3, 1, 3, 1, 3, 1, 3, 3, 1, 3, + 3, 3, 3, 3, 3, 1, 3, 3, 1, 3, + 3, 3, 1, 1, 2, 2, 2, 0, 2, 2, + 0, 2, 2, 2, 3, 2 }; @@ -1572,17 +1572,26 @@ yyreduce: { struct node *target = get_node_by_ref((yyvsp[-2].node), (yyvsp[-1].labelref)); - if (target) + if (target) { merge_nodes(target, (yyvsp[0].node)); - else - ERROR(&(yylsp[-1]), "Label or path %s not found", (yyvsp[-1].labelref)); + } else { + /* + * We rely on the rule being always: + * versioninfo plugindecl memreserves devicetree + * so $-1 is what we want (plugindecl) + */ + if ((yyvsp[(-1) - (3)].flags) & DTSF_PLUGIN) + add_orphan_node((yyvsp[-2].node), (yyvsp[0].node), (yyvsp[-1].labelref)); + else + ERROR(&(yylsp[-1]), "Label or path %s not found", (yyvsp[-1].labelref)); + } (yyval.node) = (yyvsp[-2].node); } -#line 1582 "dtc-parser.tab.c" /* yacc.c:1646 */ +#line 1591 "dtc-parser.tab.c" /* yacc.c:1646 */ break; case 15: -#line 192 "dtc-parser.y" /* yacc.c:1646 */ +#line 201 "dtc-parser.y" /* yacc.c:1646 */ { struct node *target = get_node_by_ref((yyvsp[-3].node), (yyvsp[-1].labelref)); @@ -1594,100 +1603,109 @@ yyreduce: (yyval.node) = (yyvsp[-3].node); } -#line 1598 "dtc-parser.tab.c" /* yacc.c:1646 */ +#line 1607 "dtc-parser.tab.c" /* yacc.c:1646 */ break; case 16: -#line 207 "dtc-parser.y" /* yacc.c:1646 */ +#line 213 "dtc-parser.y" /* yacc.c:1646 */ { - (yyval.node) = build_node((yyvsp[-3].proplist), (yyvsp[-2].nodelist)); + /* build empty node */ + (yyval.node) = name_node(build_node(NULL, NULL), ""); } -#line 1606 "dtc-parser.tab.c" /* yacc.c:1646 */ +#line 1616 "dtc-parser.tab.c" /* yacc.c:1646 */ break; case 17: -#line 214 "dtc-parser.y" /* yacc.c:1646 */ +#line 221 "dtc-parser.y" /* yacc.c:1646 */ { - (yyval.proplist) = NULL; + (yyval.node) = build_node((yyvsp[-3].proplist), (yyvsp[-2].nodelist)); } -#line 1614 "dtc-parser.tab.c" /* yacc.c:1646 */ +#line 1624 "dtc-parser.tab.c" /* yacc.c:1646 */ break; case 18: -#line 218 "dtc-parser.y" /* yacc.c:1646 */ +#line 228 "dtc-parser.y" /* yacc.c:1646 */ { - (yyval.proplist) = chain_property((yyvsp[0].prop), (yyvsp[-1].proplist)); + (yyval.proplist) = NULL; } -#line 1622 "dtc-parser.tab.c" /* yacc.c:1646 */ +#line 1632 "dtc-parser.tab.c" /* yacc.c:1646 */ break; case 19: -#line 225 "dtc-parser.y" /* yacc.c:1646 */ +#line 232 "dtc-parser.y" /* yacc.c:1646 */ { - (yyval.prop) = build_property((yyvsp[-3].propnodename), (yyvsp[-1].data)); + (yyval.proplist) = chain_property((yyvsp[0].prop), (yyvsp[-1].proplist)); } -#line 1630 "dtc-parser.tab.c" /* yacc.c:1646 */ +#line 1640 "dtc-parser.tab.c" /* yacc.c:1646 */ break; case 20: -#line 229 "dtc-parser.y" /* yacc.c:1646 */ +#line 239 "dtc-parser.y" /* yacc.c:1646 */ { - (yyval.prop) = build_property((yyvsp[-1].propnodename), empty_data); + (yyval.prop) = build_property((yyvsp[-3].propnodename), (yyvsp[-1].data)); } -#line 1638 "dtc-parser.tab.c" /* yacc.c:1646 */ +#line 1648 "dtc-parser.tab.c" /* yacc.c:1646 */ break; case 21: -#line 233 "dtc-parser.y" /* yacc.c:1646 */ +#line 243 "dtc-parser.y" /* yacc.c:1646 */ { - (yyval.prop) = build_property_delete((yyvsp[-1].propnodename)); + (yyval.prop) = build_property((yyvsp[-1].propnodename), empty_data); } -#line 1646 "dtc-parser.tab.c" /* yacc.c:1646 */ +#line 1656 "dtc-parser.tab.c" /* yacc.c:1646 */ break; case 22: -#line 237 "dtc-parser.y" /* yacc.c:1646 */ +#line 247 "dtc-parser.y" /* yacc.c:1646 */ + { + (yyval.prop) = build_property_delete((yyvsp[-1].propnodename)); + } +#line 1664 "dtc-parser.tab.c" /* yacc.c:1646 */ + break; + + case 23: +#line 251 "dtc-parser.y" /* yacc.c:1646 */ { add_label(&(yyvsp[0].prop)->labels, (yyvsp[-1].labelref)); (yyval.prop) = (yyvsp[0].prop); } -#line 1655 "dtc-parser.tab.c" /* yacc.c:1646 */ - break; - - case 23: -#line 245 "dtc-parser.y" /* yacc.c:1646 */ - { - (yyval.data) = data_merge((yyvsp[-1].data), (yyvsp[0].data)); - } -#line 1663 "dtc-parser.tab.c" /* yacc.c:1646 */ +#line 1673 "dtc-parser.tab.c" /* yacc.c:1646 */ break; case 24: -#line 249 "dtc-parser.y" /* yacc.c:1646 */ +#line 259 "dtc-parser.y" /* yacc.c:1646 */ { - (yyval.data) = data_merge((yyvsp[-2].data), (yyvsp[-1].array).data); + (yyval.data) = data_merge((yyvsp[-1].data), (yyvsp[0].data)); } -#line 1671 "dtc-parser.tab.c" /* yacc.c:1646 */ +#line 1681 "dtc-parser.tab.c" /* yacc.c:1646 */ break; case 25: -#line 253 "dtc-parser.y" /* yacc.c:1646 */ +#line 263 "dtc-parser.y" /* yacc.c:1646 */ { - (yyval.data) = data_merge((yyvsp[-3].data), (yyvsp[-1].data)); + (yyval.data) = data_merge((yyvsp[-2].data), (yyvsp[-1].array).data); } -#line 1679 "dtc-parser.tab.c" /* yacc.c:1646 */ +#line 1689 "dtc-parser.tab.c" /* yacc.c:1646 */ break; case 26: -#line 257 "dtc-parser.y" /* yacc.c:1646 */ +#line 267 "dtc-parser.y" /* yacc.c:1646 */ { - (yyval.data) = data_add_marker((yyvsp[-1].data), REF_PATH, (yyvsp[0].labelref)); + (yyval.data) = data_merge((yyvsp[-3].data), (yyvsp[-1].data)); } -#line 1687 "dtc-parser.tab.c" /* yacc.c:1646 */ +#line 1697 "dtc-parser.tab.c" /* yacc.c:1646 */ break; case 27: -#line 261 "dtc-parser.y" /* yacc.c:1646 */ +#line 271 "dtc-parser.y" /* yacc.c:1646 */ + { + (yyval.data) = data_add_marker((yyvsp[-1].data), REF_PATH, (yyvsp[0].labelref)); + } +#line 1705 "dtc-parser.tab.c" /* yacc.c:1646 */ + break; + + case 28: +#line 275 "dtc-parser.y" /* yacc.c:1646 */ { FILE *f = srcfile_relative_open((yyvsp[-5].data).val, NULL); struct data d; @@ -1703,11 +1721,11 @@ yyreduce: (yyval.data) = data_merge((yyvsp[-8].data), d); fclose(f); } -#line 1707 "dtc-parser.tab.c" /* yacc.c:1646 */ +#line 1725 "dtc-parser.tab.c" /* yacc.c:1646 */ break; - case 28: -#line 277 "dtc-parser.y" /* yacc.c:1646 */ + case 29: +#line 291 "dtc-parser.y" /* yacc.c:1646 */ { FILE *f = srcfile_relative_open((yyvsp[-1].data).val, NULL); struct data d = empty_data; @@ -1717,43 +1735,43 @@ yyreduce: (yyval.data) = data_merge((yyvsp[-4].data), d); fclose(f); } -#line 1721 "dtc-parser.tab.c" /* yacc.c:1646 */ - break; - - case 29: -#line 287 "dtc-parser.y" /* yacc.c:1646 */ - { - (yyval.data) = data_add_marker((yyvsp[-1].data), LABEL, (yyvsp[0].labelref)); - } -#line 1729 "dtc-parser.tab.c" /* yacc.c:1646 */ +#line 1739 "dtc-parser.tab.c" /* yacc.c:1646 */ break; case 30: -#line 294 "dtc-parser.y" /* yacc.c:1646 */ - { - (yyval.data) = empty_data; - } -#line 1737 "dtc-parser.tab.c" /* yacc.c:1646 */ - break; - - case 31: -#line 298 "dtc-parser.y" /* yacc.c:1646 */ - { - (yyval.data) = (yyvsp[-1].data); - } -#line 1745 "dtc-parser.tab.c" /* yacc.c:1646 */ - break; - - case 32: -#line 302 "dtc-parser.y" /* yacc.c:1646 */ +#line 301 "dtc-parser.y" /* yacc.c:1646 */ { (yyval.data) = data_add_marker((yyvsp[-1].data), LABEL, (yyvsp[0].labelref)); } -#line 1753 "dtc-parser.tab.c" /* yacc.c:1646 */ +#line 1747 "dtc-parser.tab.c" /* yacc.c:1646 */ + break; + + case 31: +#line 308 "dtc-parser.y" /* yacc.c:1646 */ + { + (yyval.data) = empty_data; + } +#line 1755 "dtc-parser.tab.c" /* yacc.c:1646 */ + break; + + case 32: +#line 312 "dtc-parser.y" /* yacc.c:1646 */ + { + (yyval.data) = (yyvsp[-1].data); + } +#line 1763 "dtc-parser.tab.c" /* yacc.c:1646 */ break; case 33: -#line 309 "dtc-parser.y" /* yacc.c:1646 */ +#line 316 "dtc-parser.y" /* yacc.c:1646 */ + { + (yyval.data) = data_add_marker((yyvsp[-1].data), LABEL, (yyvsp[0].labelref)); + } +#line 1771 "dtc-parser.tab.c" /* yacc.c:1646 */ + break; + + case 34: +#line 323 "dtc-parser.y" /* yacc.c:1646 */ { unsigned long long bits; @@ -1769,20 +1787,20 @@ yyreduce: (yyval.array).data = empty_data; (yyval.array).bits = bits; } -#line 1773 "dtc-parser.tab.c" /* yacc.c:1646 */ +#line 1791 "dtc-parser.tab.c" /* yacc.c:1646 */ break; - case 34: -#line 325 "dtc-parser.y" /* yacc.c:1646 */ + case 35: +#line 339 "dtc-parser.y" /* yacc.c:1646 */ { (yyval.array).data = empty_data; (yyval.array).bits = 32; } -#line 1782 "dtc-parser.tab.c" /* yacc.c:1646 */ +#line 1800 "dtc-parser.tab.c" /* yacc.c:1646 */ break; - case 35: -#line 330 "dtc-parser.y" /* yacc.c:1646 */ + case 36: +#line 344 "dtc-parser.y" /* yacc.c:1646 */ { if ((yyvsp[-1].array).bits < 64) { uint64_t mask = (1ULL << (yyvsp[-1].array).bits) - 1; @@ -1801,11 +1819,11 @@ yyreduce: (yyval.array).data = data_append_integer((yyvsp[-1].array).data, (yyvsp[0].integer), (yyvsp[-1].array).bits); } -#line 1805 "dtc-parser.tab.c" /* yacc.c:1646 */ +#line 1823 "dtc-parser.tab.c" /* yacc.c:1646 */ break; - case 36: -#line 349 "dtc-parser.y" /* yacc.c:1646 */ + case 37: +#line 363 "dtc-parser.y" /* yacc.c:1646 */ { uint64_t val = ~0ULL >> (64 - (yyvsp[-1].array).bits); @@ -1819,129 +1837,129 @@ yyreduce: (yyval.array).data = data_append_integer((yyvsp[-1].array).data, val, (yyvsp[-1].array).bits); } -#line 1823 "dtc-parser.tab.c" /* yacc.c:1646 */ +#line 1841 "dtc-parser.tab.c" /* yacc.c:1646 */ break; - case 37: -#line 363 "dtc-parser.y" /* yacc.c:1646 */ + case 38: +#line 377 "dtc-parser.y" /* yacc.c:1646 */ { (yyval.array).data = data_add_marker((yyvsp[-1].array).data, LABEL, (yyvsp[0].labelref)); } -#line 1831 "dtc-parser.tab.c" /* yacc.c:1646 */ +#line 1849 "dtc-parser.tab.c" /* yacc.c:1646 */ break; - case 40: -#line 372 "dtc-parser.y" /* yacc.c:1646 */ + case 41: +#line 386 "dtc-parser.y" /* yacc.c:1646 */ { (yyval.integer) = (yyvsp[-1].integer); } -#line 1839 "dtc-parser.tab.c" /* yacc.c:1646 */ - break; - - case 43: -#line 383 "dtc-parser.y" /* yacc.c:1646 */ - { (yyval.integer) = (yyvsp[-4].integer) ? (yyvsp[-2].integer) : (yyvsp[0].integer); } -#line 1845 "dtc-parser.tab.c" /* yacc.c:1646 */ - break; - - case 45: -#line 388 "dtc-parser.y" /* yacc.c:1646 */ - { (yyval.integer) = (yyvsp[-2].integer) || (yyvsp[0].integer); } -#line 1851 "dtc-parser.tab.c" /* yacc.c:1646 */ - break; - - case 47: -#line 393 "dtc-parser.y" /* yacc.c:1646 */ - { (yyval.integer) = (yyvsp[-2].integer) && (yyvsp[0].integer); } #line 1857 "dtc-parser.tab.c" /* yacc.c:1646 */ break; - case 49: -#line 398 "dtc-parser.y" /* yacc.c:1646 */ - { (yyval.integer) = (yyvsp[-2].integer) | (yyvsp[0].integer); } + case 44: +#line 397 "dtc-parser.y" /* yacc.c:1646 */ + { (yyval.integer) = (yyvsp[-4].integer) ? (yyvsp[-2].integer) : (yyvsp[0].integer); } #line 1863 "dtc-parser.tab.c" /* yacc.c:1646 */ break; - case 51: -#line 403 "dtc-parser.y" /* yacc.c:1646 */ - { (yyval.integer) = (yyvsp[-2].integer) ^ (yyvsp[0].integer); } + case 46: +#line 402 "dtc-parser.y" /* yacc.c:1646 */ + { (yyval.integer) = (yyvsp[-2].integer) || (yyvsp[0].integer); } #line 1869 "dtc-parser.tab.c" /* yacc.c:1646 */ break; - case 53: -#line 408 "dtc-parser.y" /* yacc.c:1646 */ - { (yyval.integer) = (yyvsp[-2].integer) & (yyvsp[0].integer); } + case 48: +#line 407 "dtc-parser.y" /* yacc.c:1646 */ + { (yyval.integer) = (yyvsp[-2].integer) && (yyvsp[0].integer); } #line 1875 "dtc-parser.tab.c" /* yacc.c:1646 */ break; - case 55: -#line 413 "dtc-parser.y" /* yacc.c:1646 */ - { (yyval.integer) = (yyvsp[-2].integer) == (yyvsp[0].integer); } + case 50: +#line 412 "dtc-parser.y" /* yacc.c:1646 */ + { (yyval.integer) = (yyvsp[-2].integer) | (yyvsp[0].integer); } #line 1881 "dtc-parser.tab.c" /* yacc.c:1646 */ break; - case 56: -#line 414 "dtc-parser.y" /* yacc.c:1646 */ - { (yyval.integer) = (yyvsp[-2].integer) != (yyvsp[0].integer); } + case 52: +#line 417 "dtc-parser.y" /* yacc.c:1646 */ + { (yyval.integer) = (yyvsp[-2].integer) ^ (yyvsp[0].integer); } #line 1887 "dtc-parser.tab.c" /* yacc.c:1646 */ break; - case 58: -#line 419 "dtc-parser.y" /* yacc.c:1646 */ - { (yyval.integer) = (yyvsp[-2].integer) < (yyvsp[0].integer); } + case 54: +#line 422 "dtc-parser.y" /* yacc.c:1646 */ + { (yyval.integer) = (yyvsp[-2].integer) & (yyvsp[0].integer); } #line 1893 "dtc-parser.tab.c" /* yacc.c:1646 */ break; - case 59: -#line 420 "dtc-parser.y" /* yacc.c:1646 */ - { (yyval.integer) = (yyvsp[-2].integer) > (yyvsp[0].integer); } + case 56: +#line 427 "dtc-parser.y" /* yacc.c:1646 */ + { (yyval.integer) = (yyvsp[-2].integer) == (yyvsp[0].integer); } #line 1899 "dtc-parser.tab.c" /* yacc.c:1646 */ break; - case 60: -#line 421 "dtc-parser.y" /* yacc.c:1646 */ - { (yyval.integer) = (yyvsp[-2].integer) <= (yyvsp[0].integer); } + case 57: +#line 428 "dtc-parser.y" /* yacc.c:1646 */ + { (yyval.integer) = (yyvsp[-2].integer) != (yyvsp[0].integer); } #line 1905 "dtc-parser.tab.c" /* yacc.c:1646 */ break; - case 61: -#line 422 "dtc-parser.y" /* yacc.c:1646 */ - { (yyval.integer) = (yyvsp[-2].integer) >= (yyvsp[0].integer); } + case 59: +#line 433 "dtc-parser.y" /* yacc.c:1646 */ + { (yyval.integer) = (yyvsp[-2].integer) < (yyvsp[0].integer); } #line 1911 "dtc-parser.tab.c" /* yacc.c:1646 */ break; - case 62: -#line 426 "dtc-parser.y" /* yacc.c:1646 */ - { (yyval.integer) = (yyvsp[-2].integer) << (yyvsp[0].integer); } + case 60: +#line 434 "dtc-parser.y" /* yacc.c:1646 */ + { (yyval.integer) = (yyvsp[-2].integer) > (yyvsp[0].integer); } #line 1917 "dtc-parser.tab.c" /* yacc.c:1646 */ break; - case 63: -#line 427 "dtc-parser.y" /* yacc.c:1646 */ - { (yyval.integer) = (yyvsp[-2].integer) >> (yyvsp[0].integer); } + case 61: +#line 435 "dtc-parser.y" /* yacc.c:1646 */ + { (yyval.integer) = (yyvsp[-2].integer) <= (yyvsp[0].integer); } #line 1923 "dtc-parser.tab.c" /* yacc.c:1646 */ break; - case 65: -#line 432 "dtc-parser.y" /* yacc.c:1646 */ - { (yyval.integer) = (yyvsp[-2].integer) + (yyvsp[0].integer); } + case 62: +#line 436 "dtc-parser.y" /* yacc.c:1646 */ + { (yyval.integer) = (yyvsp[-2].integer) >= (yyvsp[0].integer); } #line 1929 "dtc-parser.tab.c" /* yacc.c:1646 */ break; - case 66: -#line 433 "dtc-parser.y" /* yacc.c:1646 */ - { (yyval.integer) = (yyvsp[-2].integer) - (yyvsp[0].integer); } + case 63: +#line 440 "dtc-parser.y" /* yacc.c:1646 */ + { (yyval.integer) = (yyvsp[-2].integer) << (yyvsp[0].integer); } #line 1935 "dtc-parser.tab.c" /* yacc.c:1646 */ break; - case 68: -#line 438 "dtc-parser.y" /* yacc.c:1646 */ - { (yyval.integer) = (yyvsp[-2].integer) * (yyvsp[0].integer); } + case 64: +#line 441 "dtc-parser.y" /* yacc.c:1646 */ + { (yyval.integer) = (yyvsp[-2].integer) >> (yyvsp[0].integer); } #line 1941 "dtc-parser.tab.c" /* yacc.c:1646 */ break; + case 66: +#line 446 "dtc-parser.y" /* yacc.c:1646 */ + { (yyval.integer) = (yyvsp[-2].integer) + (yyvsp[0].integer); } +#line 1947 "dtc-parser.tab.c" /* yacc.c:1646 */ + break; + + case 67: +#line 447 "dtc-parser.y" /* yacc.c:1646 */ + { (yyval.integer) = (yyvsp[-2].integer) - (yyvsp[0].integer); } +#line 1953 "dtc-parser.tab.c" /* yacc.c:1646 */ + break; + case 69: -#line 440 "dtc-parser.y" /* yacc.c:1646 */ +#line 452 "dtc-parser.y" /* yacc.c:1646 */ + { (yyval.integer) = (yyvsp[-2].integer) * (yyvsp[0].integer); } +#line 1959 "dtc-parser.tab.c" /* yacc.c:1646 */ + break; + + case 70: +#line 454 "dtc-parser.y" /* yacc.c:1646 */ { if ((yyvsp[0].integer) != 0) { (yyval.integer) = (yyvsp[-2].integer) / (yyvsp[0].integer); @@ -1950,11 +1968,11 @@ yyreduce: (yyval.integer) = 0; } } -#line 1954 "dtc-parser.tab.c" /* yacc.c:1646 */ +#line 1972 "dtc-parser.tab.c" /* yacc.c:1646 */ break; - case 70: -#line 449 "dtc-parser.y" /* yacc.c:1646 */ + case 71: +#line 463 "dtc-parser.y" /* yacc.c:1646 */ { if ((yyvsp[0].integer) != 0) { (yyval.integer) = (yyvsp[-2].integer) % (yyvsp[0].integer); @@ -1963,103 +1981,103 @@ yyreduce: (yyval.integer) = 0; } } -#line 1967 "dtc-parser.tab.c" /* yacc.c:1646 */ - break; - - case 73: -#line 462 "dtc-parser.y" /* yacc.c:1646 */ - { (yyval.integer) = -(yyvsp[0].integer); } -#line 1973 "dtc-parser.tab.c" /* yacc.c:1646 */ - break; - - case 74: -#line 463 "dtc-parser.y" /* yacc.c:1646 */ - { (yyval.integer) = ~(yyvsp[0].integer); } -#line 1979 "dtc-parser.tab.c" /* yacc.c:1646 */ - break; - - case 75: -#line 464 "dtc-parser.y" /* yacc.c:1646 */ - { (yyval.integer) = !(yyvsp[0].integer); } #line 1985 "dtc-parser.tab.c" /* yacc.c:1646 */ break; + case 74: +#line 476 "dtc-parser.y" /* yacc.c:1646 */ + { (yyval.integer) = -(yyvsp[0].integer); } +#line 1991 "dtc-parser.tab.c" /* yacc.c:1646 */ + break; + + case 75: +#line 477 "dtc-parser.y" /* yacc.c:1646 */ + { (yyval.integer) = ~(yyvsp[0].integer); } +#line 1997 "dtc-parser.tab.c" /* yacc.c:1646 */ + break; + case 76: -#line 469 "dtc-parser.y" /* yacc.c:1646 */ - { - (yyval.data) = empty_data; - } -#line 1993 "dtc-parser.tab.c" /* yacc.c:1646 */ +#line 478 "dtc-parser.y" /* yacc.c:1646 */ + { (yyval.integer) = !(yyvsp[0].integer); } +#line 2003 "dtc-parser.tab.c" /* yacc.c:1646 */ break; case 77: -#line 473 "dtc-parser.y" /* yacc.c:1646 */ +#line 483 "dtc-parser.y" /* yacc.c:1646 */ { - (yyval.data) = data_append_byte((yyvsp[-1].data), (yyvsp[0].byte)); + (yyval.data) = empty_data; } -#line 2001 "dtc-parser.tab.c" /* yacc.c:1646 */ +#line 2011 "dtc-parser.tab.c" /* yacc.c:1646 */ break; case 78: -#line 477 "dtc-parser.y" /* yacc.c:1646 */ +#line 487 "dtc-parser.y" /* yacc.c:1646 */ { - (yyval.data) = data_add_marker((yyvsp[-1].data), LABEL, (yyvsp[0].labelref)); + (yyval.data) = data_append_byte((yyvsp[-1].data), (yyvsp[0].byte)); } -#line 2009 "dtc-parser.tab.c" /* yacc.c:1646 */ +#line 2019 "dtc-parser.tab.c" /* yacc.c:1646 */ break; case 79: -#line 484 "dtc-parser.y" /* yacc.c:1646 */ +#line 491 "dtc-parser.y" /* yacc.c:1646 */ { - (yyval.nodelist) = NULL; + (yyval.data) = data_add_marker((yyvsp[-1].data), LABEL, (yyvsp[0].labelref)); } -#line 2017 "dtc-parser.tab.c" /* yacc.c:1646 */ +#line 2027 "dtc-parser.tab.c" /* yacc.c:1646 */ break; case 80: -#line 488 "dtc-parser.y" /* yacc.c:1646 */ +#line 498 "dtc-parser.y" /* yacc.c:1646 */ { - (yyval.nodelist) = chain_node((yyvsp[-1].node), (yyvsp[0].nodelist)); + (yyval.nodelist) = NULL; } -#line 2025 "dtc-parser.tab.c" /* yacc.c:1646 */ +#line 2035 "dtc-parser.tab.c" /* yacc.c:1646 */ break; case 81: -#line 492 "dtc-parser.y" /* yacc.c:1646 */ +#line 502 "dtc-parser.y" /* yacc.c:1646 */ + { + (yyval.nodelist) = chain_node((yyvsp[-1].node), (yyvsp[0].nodelist)); + } +#line 2043 "dtc-parser.tab.c" /* yacc.c:1646 */ + break; + + case 82: +#line 506 "dtc-parser.y" /* yacc.c:1646 */ { ERROR(&(yylsp[0]), "Properties must precede subnodes"); YYERROR; } -#line 2034 "dtc-parser.tab.c" /* yacc.c:1646 */ - break; - - case 82: -#line 500 "dtc-parser.y" /* yacc.c:1646 */ - { - (yyval.node) = name_node((yyvsp[0].node), (yyvsp[-1].propnodename)); - } -#line 2042 "dtc-parser.tab.c" /* yacc.c:1646 */ +#line 2052 "dtc-parser.tab.c" /* yacc.c:1646 */ break; case 83: -#line 504 "dtc-parser.y" /* yacc.c:1646 */ +#line 514 "dtc-parser.y" /* yacc.c:1646 */ { - (yyval.node) = name_node(build_node_delete(), (yyvsp[-1].propnodename)); + (yyval.node) = name_node((yyvsp[0].node), (yyvsp[-1].propnodename)); } -#line 2050 "dtc-parser.tab.c" /* yacc.c:1646 */ +#line 2060 "dtc-parser.tab.c" /* yacc.c:1646 */ break; case 84: -#line 508 "dtc-parser.y" /* yacc.c:1646 */ +#line 518 "dtc-parser.y" /* yacc.c:1646 */ + { + (yyval.node) = name_node(build_node_delete(), (yyvsp[-1].propnodename)); + } +#line 2068 "dtc-parser.tab.c" /* yacc.c:1646 */ + break; + + case 85: +#line 522 "dtc-parser.y" /* yacc.c:1646 */ { add_label(&(yyvsp[0].node)->labels, (yyvsp[-1].labelref)); (yyval.node) = (yyvsp[0].node); } -#line 2059 "dtc-parser.tab.c" /* yacc.c:1646 */ +#line 2077 "dtc-parser.tab.c" /* yacc.c:1646 */ break; -#line 2063 "dtc-parser.tab.c" /* yacc.c:1646 */ +#line 2081 "dtc-parser.tab.c" /* yacc.c:1646 */ default: break; } /* User semantic actions sometimes alter yychar, and that requires @@ -2294,7 +2312,7 @@ yyreturn: #endif return yyresult; } -#line 514 "dtc-parser.y" /* yacc.c:1906 */ +#line 528 "dtc-parser.y" /* yacc.c:1906 */ void yyerror(char const *s) diff --git a/scripts/dtc/dtc-parser.y b/scripts/dtc/dtc-parser.y index ca3f5003427c..affc81a8f9ab 100644 --- a/scripts/dtc/dtc-parser.y +++ b/scripts/dtc/dtc-parser.y @@ -182,10 +182,19 @@ devicetree: { struct node *target = get_node_by_ref($1, $2); - if (target) + if (target) { merge_nodes(target, $3); - else - ERROR(&@2, "Label or path %s not found", $2); + } else { + /* + * We rely on the rule being always: + * versioninfo plugindecl memreserves devicetree + * so $-1 is what we want (plugindecl) + */ + if ($-1 & DTSF_PLUGIN) + add_orphan_node($1, $3, $2); + else + ERROR(&@2, "Label or path %s not found", $2); + } $$ = $1; } | devicetree DT_DEL_NODE DT_REF ';' @@ -200,6 +209,11 @@ devicetree: $$ = $1; } + | /* empty */ + { + /* build empty node */ + $$ = name_node(build_node(NULL, NULL), ""); + } ; nodedef: diff --git a/scripts/dtc/dtc.c b/scripts/dtc/dtc.c index f5eed9d72c02..5ed873c72ad1 100644 --- a/scripts/dtc/dtc.c +++ b/scripts/dtc/dtc.c @@ -31,7 +31,7 @@ int reservenum; /* Number of memory reservation slots */ int minsize; /* Minimum blob size */ int padsize; /* Additional padding to blob */ int alignsize; /* Additional padding to blob accroding to the alignsize */ -int phandle_format = PHANDLE_BOTH; /* Use linux,phandle or phandle properties */ +int phandle_format = PHANDLE_EPAPR; /* Use linux,phandle or phandle properties */ int generate_symbols; /* enable symbols & fixup support */ int generate_fixups; /* suppress generation of fixups on symbol support */ int auto_label_aliases; /* auto generate labels -> aliases */ diff --git a/scripts/dtc/dtc.h b/scripts/dtc/dtc.h index fc24e17510fd..35cf926cc14a 100644 --- a/scripts/dtc/dtc.h +++ b/scripts/dtc/dtc.h @@ -31,6 +31,7 @@ #include #include #include +#include #include #include @@ -202,6 +203,7 @@ struct node *build_node_delete(void); struct node *name_node(struct node *node, char *name); struct node *chain_node(struct node *first, struct node *list); struct node *merge_nodes(struct node *old_node, struct node *new_node); +void add_orphan_node(struct node *old_node, struct node *new_node, char *ref); void add_property(struct node *node, struct property *prop); void delete_property_by_name(struct node *node, char *name); @@ -215,6 +217,7 @@ void append_to_property(struct node *node, const char *get_unitname(struct node *node); struct property *get_property(struct node *node, const char *propname); cell_t propval_cell(struct property *prop); +cell_t propval_cell_n(struct property *prop, int n); struct property *get_property_by_label(struct node *tree, const char *label, struct node **node); struct marker *get_marker_label(struct node *tree, const char *label, diff --git a/scripts/dtc/libfdt/fdt_addresses.c b/scripts/dtc/libfdt/fdt_addresses.c new file mode 100644 index 000000000000..eff4dbcc729d --- /dev/null +++ b/scripts/dtc/libfdt/fdt_addresses.c @@ -0,0 +1,96 @@ +/* + * libfdt - Flat Device Tree manipulation + * Copyright (C) 2014 David Gibson + * + * libfdt is dual licensed: you can use it either under the terms of + * the GPL, or the BSD license, at your option. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with this library; if not, write to the Free + * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + * + * Alternatively, + * + * b) Redistribution and use in source and binary forms, with or + * without modification, are permitted provided that the following + * conditions are met: + * + * 1. Redistributions of source code must retain the above + * copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials + * provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND + * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#include "libfdt_env.h" + +#include +#include + +#include "libfdt_internal.h" + +int fdt_address_cells(const void *fdt, int nodeoffset) +{ + const fdt32_t *ac; + int val; + int len; + + ac = fdt_getprop(fdt, nodeoffset, "#address-cells", &len); + if (!ac) + return 2; + + if (len != sizeof(*ac)) + return -FDT_ERR_BADNCELLS; + + val = fdt32_to_cpu(*ac); + if ((val <= 0) || (val > FDT_MAX_NCELLS)) + return -FDT_ERR_BADNCELLS; + + return val; +} + +int fdt_size_cells(const void *fdt, int nodeoffset) +{ + const fdt32_t *sc; + int val; + int len; + + sc = fdt_getprop(fdt, nodeoffset, "#size-cells", &len); + if (!sc) + return 2; + + if (len != sizeof(*sc)) + return -FDT_ERR_BADNCELLS; + + val = fdt32_to_cpu(*sc); + if ((val < 0) || (val > FDT_MAX_NCELLS)) + return -FDT_ERR_BADNCELLS; + + return val; +} diff --git a/scripts/dtc/libfdt/fdt_empty_tree.c b/scripts/dtc/libfdt/fdt_empty_tree.c index f72d13b1d19c..f2ae9b77c285 100644 --- a/scripts/dtc/libfdt/fdt_empty_tree.c +++ b/scripts/dtc/libfdt/fdt_empty_tree.c @@ -81,4 +81,3 @@ int fdt_create_empty_tree(void *buf, int bufsize) return fdt_open_into(buf, buf, bufsize); } - diff --git a/scripts/dtc/libfdt/fdt_overlay.c b/scripts/dtc/libfdt/fdt_overlay.c new file mode 100644 index 000000000000..bd81241e6658 --- /dev/null +++ b/scripts/dtc/libfdt/fdt_overlay.c @@ -0,0 +1,861 @@ +#include "libfdt_env.h" + +#include +#include + +#include "libfdt_internal.h" + +/** + * overlay_get_target_phandle - retrieves the target phandle of a fragment + * @fdto: pointer to the device tree overlay blob + * @fragment: node offset of the fragment in the overlay + * + * overlay_get_target_phandle() retrieves the target phandle of an + * overlay fragment when that fragment uses a phandle (target + * property) instead of a path (target-path property). + * + * returns: + * the phandle pointed by the target property + * 0, if the phandle was not found + * -1, if the phandle was malformed + */ +static uint32_t overlay_get_target_phandle(const void *fdto, int fragment) +{ + const fdt32_t *val; + int len; + + val = fdt_getprop(fdto, fragment, "target", &len); + if (!val) + return 0; + + if ((len != sizeof(*val)) || (fdt32_to_cpu(*val) == (uint32_t)-1)) + return (uint32_t)-1; + + return fdt32_to_cpu(*val); +} + +/** + * overlay_get_target - retrieves the offset of a fragment's target + * @fdt: Base device tree blob + * @fdto: Device tree overlay blob + * @fragment: node offset of the fragment in the overlay + * @pathp: pointer which receives the path of the target (or NULL) + * + * overlay_get_target() retrieves the target offset in the base + * device tree of a fragment, no matter how the actual targetting is + * done (through a phandle or a path) + * + * returns: + * the targetted node offset in the base device tree + * Negative error code on error + */ +static int overlay_get_target(const void *fdt, const void *fdto, + int fragment, char const **pathp) +{ + uint32_t phandle; + const char *path = NULL; + int path_len = 0, ret; + + /* Try first to do a phandle based lookup */ + phandle = overlay_get_target_phandle(fdto, fragment); + if (phandle == (uint32_t)-1) + return -FDT_ERR_BADPHANDLE; + + /* no phandle, try path */ + if (!phandle) { + /* And then a path based lookup */ + path = fdt_getprop(fdto, fragment, "target-path", &path_len); + if (path) + ret = fdt_path_offset(fdt, path); + else + ret = path_len; + } else + ret = fdt_node_offset_by_phandle(fdt, phandle); + + /* + * If we haven't found either a target or a + * target-path property in a node that contains a + * __overlay__ subnode (we wouldn't be called + * otherwise), consider it a improperly written + * overlay + */ + if (ret < 0 && path_len == -FDT_ERR_NOTFOUND) + ret = -FDT_ERR_BADOVERLAY; + + /* return on error */ + if (ret < 0) + return ret; + + /* return pointer to path (if available) */ + if (pathp) + *pathp = path ? path : NULL; + + return ret; +} + +/** + * overlay_phandle_add_offset - Increases a phandle by an offset + * @fdt: Base device tree blob + * @node: Device tree overlay blob + * @name: Name of the property to modify (phandle or linux,phandle) + * @delta: offset to apply + * + * overlay_phandle_add_offset() increments a node phandle by a given + * offset. + * + * returns: + * 0 on success. + * Negative error code on error + */ +static int overlay_phandle_add_offset(void *fdt, int node, + const char *name, uint32_t delta) +{ + const fdt32_t *val; + uint32_t adj_val; + int len; + + val = fdt_getprop(fdt, node, name, &len); + if (!val) + return len; + + if (len != sizeof(*val)) + return -FDT_ERR_BADPHANDLE; + + adj_val = fdt32_to_cpu(*val); + if ((adj_val + delta) < adj_val) + return -FDT_ERR_NOPHANDLES; + + adj_val += delta; + if (adj_val == (uint32_t)-1) + return -FDT_ERR_NOPHANDLES; + + return fdt_setprop_inplace_u32(fdt, node, name, adj_val); +} + +/** + * overlay_adjust_node_phandles - Offsets the phandles of a node + * @fdto: Device tree overlay blob + * @node: Offset of the node we want to adjust + * @delta: Offset to shift the phandles of + * + * overlay_adjust_node_phandles() adds a constant to all the phandles + * of a given node. This is mainly use as part of the overlay + * application process, when we want to update all the overlay + * phandles to not conflict with the overlays of the base device tree. + * + * returns: + * 0 on success + * Negative error code on failure + */ +static int overlay_adjust_node_phandles(void *fdto, int node, + uint32_t delta) +{ + int child; + int ret; + + ret = overlay_phandle_add_offset(fdto, node, "phandle", delta); + if (ret && ret != -FDT_ERR_NOTFOUND) + return ret; + + ret = overlay_phandle_add_offset(fdto, node, "linux,phandle", delta); + if (ret && ret != -FDT_ERR_NOTFOUND) + return ret; + + fdt_for_each_subnode(child, fdto, node) { + ret = overlay_adjust_node_phandles(fdto, child, delta); + if (ret) + return ret; + } + + return 0; +} + +/** + * overlay_adjust_local_phandles - Adjust the phandles of a whole overlay + * @fdto: Device tree overlay blob + * @delta: Offset to shift the phandles of + * + * overlay_adjust_local_phandles() adds a constant to all the + * phandles of an overlay. This is mainly use as part of the overlay + * application process, when we want to update all the overlay + * phandles to not conflict with the overlays of the base device tree. + * + * returns: + * 0 on success + * Negative error code on failure + */ +static int overlay_adjust_local_phandles(void *fdto, uint32_t delta) +{ + /* + * Start adjusting the phandles from the overlay root + */ + return overlay_adjust_node_phandles(fdto, 0, delta); +} + +/** + * overlay_update_local_node_references - Adjust the overlay references + * @fdto: Device tree overlay blob + * @tree_node: Node offset of the node to operate on + * @fixup_node: Node offset of the matching local fixups node + * @delta: Offset to shift the phandles of + * + * overlay_update_local_nodes_references() update the phandles + * pointing to a node within the device tree overlay by adding a + * constant delta. + * + * This is mainly used as part of a device tree application process, + * where you want the device tree overlays phandles to not conflict + * with the ones from the base device tree before merging them. + * + * returns: + * 0 on success + * Negative error code on failure + */ +static int overlay_update_local_node_references(void *fdto, + int tree_node, + int fixup_node, + uint32_t delta) +{ + int fixup_prop; + int fixup_child; + int ret; + + fdt_for_each_property_offset(fixup_prop, fdto, fixup_node) { + const fdt32_t *fixup_val; + const char *tree_val; + const char *name; + int fixup_len; + int tree_len; + int i; + + fixup_val = fdt_getprop_by_offset(fdto, fixup_prop, + &name, &fixup_len); + if (!fixup_val) + return fixup_len; + + if (fixup_len % sizeof(uint32_t)) + return -FDT_ERR_BADOVERLAY; + + tree_val = fdt_getprop(fdto, tree_node, name, &tree_len); + if (!tree_val) { + if (tree_len == -FDT_ERR_NOTFOUND) + return -FDT_ERR_BADOVERLAY; + + return tree_len; + } + + for (i = 0; i < (fixup_len / sizeof(uint32_t)); i++) { + fdt32_t adj_val; + uint32_t poffset; + + poffset = fdt32_to_cpu(fixup_val[i]); + + /* + * phandles to fixup can be unaligned. + * + * Use a memcpy for the architectures that do + * not support unaligned accesses. + */ + memcpy(&adj_val, tree_val + poffset, sizeof(adj_val)); + + adj_val = cpu_to_fdt32(fdt32_to_cpu(adj_val) + delta); + + ret = fdt_setprop_inplace_namelen_partial(fdto, + tree_node, + name, + strlen(name), + poffset, + &adj_val, + sizeof(adj_val)); + if (ret == -FDT_ERR_NOSPACE) + return -FDT_ERR_BADOVERLAY; + + if (ret) + return ret; + } + } + + fdt_for_each_subnode(fixup_child, fdto, fixup_node) { + const char *fixup_child_name = fdt_get_name(fdto, fixup_child, + NULL); + int tree_child; + + tree_child = fdt_subnode_offset(fdto, tree_node, + fixup_child_name); + if (tree_child == -FDT_ERR_NOTFOUND) + return -FDT_ERR_BADOVERLAY; + if (tree_child < 0) + return tree_child; + + ret = overlay_update_local_node_references(fdto, + tree_child, + fixup_child, + delta); + if (ret) + return ret; + } + + return 0; +} + +/** + * overlay_update_local_references - Adjust the overlay references + * @fdto: Device tree overlay blob + * @delta: Offset to shift the phandles of + * + * overlay_update_local_references() update all the phandles pointing + * to a node within the device tree overlay by adding a constant + * delta to not conflict with the base overlay. + * + * This is mainly used as part of a device tree application process, + * where you want the device tree overlays phandles to not conflict + * with the ones from the base device tree before merging them. + * + * returns: + * 0 on success + * Negative error code on failure + */ +static int overlay_update_local_references(void *fdto, uint32_t delta) +{ + int fixups; + + fixups = fdt_path_offset(fdto, "/__local_fixups__"); + if (fixups < 0) { + /* There's no local phandles to adjust, bail out */ + if (fixups == -FDT_ERR_NOTFOUND) + return 0; + + return fixups; + } + + /* + * Update our local references from the root of the tree + */ + return overlay_update_local_node_references(fdto, 0, fixups, + delta); +} + +/** + * overlay_fixup_one_phandle - Set an overlay phandle to the base one + * @fdt: Base Device Tree blob + * @fdto: Device tree overlay blob + * @symbols_off: Node offset of the symbols node in the base device tree + * @path: Path to a node holding a phandle in the overlay + * @path_len: number of path characters to consider + * @name: Name of the property holding the phandle reference in the overlay + * @name_len: number of name characters to consider + * @poffset: Offset within the overlay property where the phandle is stored + * @label: Label of the node referenced by the phandle + * + * overlay_fixup_one_phandle() resolves an overlay phandle pointing to + * a node in the base device tree. + * + * This is part of the device tree overlay application process, when + * you want all the phandles in the overlay to point to the actual + * base dt nodes. + * + * returns: + * 0 on success + * Negative error code on failure + */ +static int overlay_fixup_one_phandle(void *fdt, void *fdto, + int symbols_off, + const char *path, uint32_t path_len, + const char *name, uint32_t name_len, + int poffset, const char *label) +{ + const char *symbol_path; + uint32_t phandle; + fdt32_t phandle_prop; + int symbol_off, fixup_off; + int prop_len; + + if (symbols_off < 0) + return symbols_off; + + symbol_path = fdt_getprop(fdt, symbols_off, label, + &prop_len); + if (!symbol_path) + return prop_len; + + symbol_off = fdt_path_offset(fdt, symbol_path); + if (symbol_off < 0) + return symbol_off; + + phandle = fdt_get_phandle(fdt, symbol_off); + if (!phandle) + return -FDT_ERR_NOTFOUND; + + fixup_off = fdt_path_offset_namelen(fdto, path, path_len); + if (fixup_off == -FDT_ERR_NOTFOUND) + return -FDT_ERR_BADOVERLAY; + if (fixup_off < 0) + return fixup_off; + + phandle_prop = cpu_to_fdt32(phandle); + return fdt_setprop_inplace_namelen_partial(fdto, fixup_off, + name, name_len, poffset, + &phandle_prop, + sizeof(phandle_prop)); +}; + +/** + * overlay_fixup_phandle - Set an overlay phandle to the base one + * @fdt: Base Device Tree blob + * @fdto: Device tree overlay blob + * @symbols_off: Node offset of the symbols node in the base device tree + * @property: Property offset in the overlay holding the list of fixups + * + * overlay_fixup_phandle() resolves all the overlay phandles pointed + * to in a __fixups__ property, and updates them to match the phandles + * in use in the base device tree. + * + * This is part of the device tree overlay application process, when + * you want all the phandles in the overlay to point to the actual + * base dt nodes. + * + * returns: + * 0 on success + * Negative error code on failure + */ +static int overlay_fixup_phandle(void *fdt, void *fdto, int symbols_off, + int property) +{ + const char *value; + const char *label; + int len; + + value = fdt_getprop_by_offset(fdto, property, + &label, &len); + if (!value) { + if (len == -FDT_ERR_NOTFOUND) + return -FDT_ERR_INTERNAL; + + return len; + } + + do { + const char *path, *name, *fixup_end; + const char *fixup_str = value; + uint32_t path_len, name_len; + uint32_t fixup_len; + char *sep, *endptr; + int poffset, ret; + + fixup_end = memchr(value, '\0', len); + if (!fixup_end) + return -FDT_ERR_BADOVERLAY; + fixup_len = fixup_end - fixup_str; + + len -= fixup_len + 1; + value += fixup_len + 1; + + path = fixup_str; + sep = memchr(fixup_str, ':', fixup_len); + if (!sep || *sep != ':') + return -FDT_ERR_BADOVERLAY; + + path_len = sep - path; + if (path_len == (fixup_len - 1)) + return -FDT_ERR_BADOVERLAY; + + fixup_len -= path_len + 1; + name = sep + 1; + sep = memchr(name, ':', fixup_len); + if (!sep || *sep != ':') + return -FDT_ERR_BADOVERLAY; + + name_len = sep - name; + if (!name_len) + return -FDT_ERR_BADOVERLAY; + + poffset = strtoul(sep + 1, &endptr, 10); + if ((*endptr != '\0') || (endptr <= (sep + 1))) + return -FDT_ERR_BADOVERLAY; + + ret = overlay_fixup_one_phandle(fdt, fdto, symbols_off, + path, path_len, name, name_len, + poffset, label); + if (ret) + return ret; + } while (len > 0); + + return 0; +} + +/** + * overlay_fixup_phandles - Resolve the overlay phandles to the base + * device tree + * @fdt: Base Device Tree blob + * @fdto: Device tree overlay blob + * + * overlay_fixup_phandles() resolves all the overlay phandles pointing + * to nodes in the base device tree. + * + * This is one of the steps of the device tree overlay application + * process, when you want all the phandles in the overlay to point to + * the actual base dt nodes. + * + * returns: + * 0 on success + * Negative error code on failure + */ +static int overlay_fixup_phandles(void *fdt, void *fdto) +{ + int fixups_off, symbols_off; + int property; + + /* We can have overlays without any fixups */ + fixups_off = fdt_path_offset(fdto, "/__fixups__"); + if (fixups_off == -FDT_ERR_NOTFOUND) + return 0; /* nothing to do */ + if (fixups_off < 0) + return fixups_off; + + /* And base DTs without symbols */ + symbols_off = fdt_path_offset(fdt, "/__symbols__"); + if ((symbols_off < 0 && (symbols_off != -FDT_ERR_NOTFOUND))) + return symbols_off; + + fdt_for_each_property_offset(property, fdto, fixups_off) { + int ret; + + ret = overlay_fixup_phandle(fdt, fdto, symbols_off, property); + if (ret) + return ret; + } + + return 0; +} + +/** + * overlay_apply_node - Merges a node into the base device tree + * @fdt: Base Device Tree blob + * @target: Node offset in the base device tree to apply the fragment to + * @fdto: Device tree overlay blob + * @node: Node offset in the overlay holding the changes to merge + * + * overlay_apply_node() merges a node into a target base device tree + * node pointed. + * + * This is part of the final step in the device tree overlay + * application process, when all the phandles have been adjusted and + * resolved and you just have to merge overlay into the base device + * tree. + * + * returns: + * 0 on success + * Negative error code on failure + */ +static int overlay_apply_node(void *fdt, int target, + void *fdto, int node) +{ + int property; + int subnode; + + fdt_for_each_property_offset(property, fdto, node) { + const char *name; + const void *prop; + int prop_len; + int ret; + + prop = fdt_getprop_by_offset(fdto, property, &name, + &prop_len); + if (prop_len == -FDT_ERR_NOTFOUND) + return -FDT_ERR_INTERNAL; + if (prop_len < 0) + return prop_len; + + ret = fdt_setprop(fdt, target, name, prop, prop_len); + if (ret) + return ret; + } + + fdt_for_each_subnode(subnode, fdto, node) { + const char *name = fdt_get_name(fdto, subnode, NULL); + int nnode; + int ret; + + nnode = fdt_add_subnode(fdt, target, name); + if (nnode == -FDT_ERR_EXISTS) { + nnode = fdt_subnode_offset(fdt, target, name); + if (nnode == -FDT_ERR_NOTFOUND) + return -FDT_ERR_INTERNAL; + } + + if (nnode < 0) + return nnode; + + ret = overlay_apply_node(fdt, nnode, fdto, subnode); + if (ret) + return ret; + } + + return 0; +} + +/** + * overlay_merge - Merge an overlay into its base device tree + * @fdt: Base Device Tree blob + * @fdto: Device tree overlay blob + * + * overlay_merge() merges an overlay into its base device tree. + * + * This is the next to last step in the device tree overlay application + * process, when all the phandles have been adjusted and resolved and + * you just have to merge overlay into the base device tree. + * + * returns: + * 0 on success + * Negative error code on failure + */ +static int overlay_merge(void *fdt, void *fdto) +{ + int fragment; + + fdt_for_each_subnode(fragment, fdto, 0) { + int overlay; + int target; + int ret; + + /* + * Each fragments will have an __overlay__ node. If + * they don't, it's not supposed to be merged + */ + overlay = fdt_subnode_offset(fdto, fragment, "__overlay__"); + if (overlay == -FDT_ERR_NOTFOUND) + continue; + + if (overlay < 0) + return overlay; + + target = overlay_get_target(fdt, fdto, fragment, NULL); + if (target < 0) + return target; + + ret = overlay_apply_node(fdt, target, fdto, overlay); + if (ret) + return ret; + } + + return 0; +} + +static int get_path_len(const void *fdt, int nodeoffset) +{ + int len = 0, namelen; + const char *name; + + FDT_CHECK_HEADER(fdt); + + for (;;) { + name = fdt_get_name(fdt, nodeoffset, &namelen); + if (!name) + return namelen; + + /* root? we're done */ + if (namelen == 0) + break; + + nodeoffset = fdt_parent_offset(fdt, nodeoffset); + if (nodeoffset < 0) + return nodeoffset; + len += namelen + 1; + } + + /* in case of root pretend it's "/" */ + if (len == 0) + len++; + return len; +} + +/** + * overlay_symbol_update - Update the symbols of base tree after a merge + * @fdt: Base Device Tree blob + * @fdto: Device tree overlay blob + * + * overlay_symbol_update() updates the symbols of the base tree with the + * symbols of the applied overlay + * + * This is the last step in the device tree overlay application + * process, allowing the reference of overlay symbols by subsequent + * overlay operations. + * + * returns: + * 0 on success + * Negative error code on failure + */ +static int overlay_symbol_update(void *fdt, void *fdto) +{ + int root_sym, ov_sym, prop, path_len, fragment, target; + int len, frag_name_len, ret, rel_path_len; + const char *s, *e; + const char *path; + const char *name; + const char *frag_name; + const char *rel_path; + const char *target_path; + char *buf; + void *p; + + ov_sym = fdt_subnode_offset(fdto, 0, "__symbols__"); + + /* if no overlay symbols exist no problem */ + if (ov_sym < 0) + return 0; + + root_sym = fdt_subnode_offset(fdt, 0, "__symbols__"); + + /* it no root symbols exist we should create them */ + if (root_sym == -FDT_ERR_NOTFOUND) + root_sym = fdt_add_subnode(fdt, 0, "__symbols__"); + + /* any error is fatal now */ + if (root_sym < 0) + return root_sym; + + /* iterate over each overlay symbol */ + fdt_for_each_property_offset(prop, fdto, ov_sym) { + path = fdt_getprop_by_offset(fdto, prop, &name, &path_len); + if (!path) + return path_len; + + /* verify it's a string property (terminated by a single \0) */ + if (path_len < 1 || memchr(path, '\0', path_len) != &path[path_len - 1]) + return -FDT_ERR_BADVALUE; + + /* keep end marker to avoid strlen() */ + e = path + path_len; + + /* format: //__overlay__/ */ + + if (*path != '/') + return -FDT_ERR_BADVALUE; + + /* get fragment name first */ + s = strchr(path + 1, '/'); + if (!s) + return -FDT_ERR_BADOVERLAY; + + frag_name = path + 1; + frag_name_len = s - path - 1; + + /* verify format; safe since "s" lies in \0 terminated prop */ + len = sizeof("/__overlay__/") - 1; + if ((e - s) < len || memcmp(s, "/__overlay__/", len)) + return -FDT_ERR_BADOVERLAY; + + rel_path = s + len; + rel_path_len = e - rel_path; + + /* find the fragment index in which the symbol lies */ + ret = fdt_subnode_offset_namelen(fdto, 0, frag_name, + frag_name_len); + /* not found? */ + if (ret < 0) + return -FDT_ERR_BADOVERLAY; + fragment = ret; + + /* an __overlay__ subnode must exist */ + ret = fdt_subnode_offset(fdto, fragment, "__overlay__"); + if (ret < 0) + return -FDT_ERR_BADOVERLAY; + + /* get the target of the fragment */ + ret = overlay_get_target(fdt, fdto, fragment, &target_path); + if (ret < 0) + return ret; + target = ret; + + /* if we have a target path use */ + if (!target_path) { + ret = get_path_len(fdt, target); + if (ret < 0) + return ret; + len = ret; + } else { + len = strlen(target_path); + } + + ret = fdt_setprop_placeholder(fdt, root_sym, name, + len + (len > 1) + rel_path_len + 1, &p); + if (ret < 0) + return ret; + + if (!target_path) { + /* again in case setprop_placeholder changed it */ + ret = overlay_get_target(fdt, fdto, fragment, &target_path); + if (ret < 0) + return ret; + target = ret; + } + + buf = p; + if (len > 1) { /* target is not root */ + if (!target_path) { + ret = fdt_get_path(fdt, target, buf, len + 1); + if (ret < 0) + return ret; + } else + memcpy(buf, target_path, len + 1); + + } else + len--; + + buf[len] = '/'; + memcpy(buf + len + 1, rel_path, rel_path_len); + buf[len + 1 + rel_path_len] = '\0'; + } + + return 0; +} + +int fdt_overlay_apply(void *fdt, void *fdto) +{ + uint32_t delta = fdt_get_max_phandle(fdt); + int ret; + + FDT_CHECK_HEADER(fdt); + FDT_CHECK_HEADER(fdto); + + ret = overlay_adjust_local_phandles(fdto, delta); + if (ret) + goto err; + + ret = overlay_update_local_references(fdto, delta); + if (ret) + goto err; + + ret = overlay_fixup_phandles(fdt, fdto); + if (ret) + goto err; + + ret = overlay_merge(fdt, fdto); + if (ret) + goto err; + + ret = overlay_symbol_update(fdt, fdto); + if (ret) + goto err; + + /* + * The overlay has been damaged, erase its magic. + */ + fdt_set_magic(fdto, ~0); + + return 0; + +err: + /* + * The overlay might have been damaged, erase its magic. + */ + fdt_set_magic(fdto, ~0); + + /* + * The base device tree might have been damaged, erase its + * magic. + */ + fdt_set_magic(fdt, ~0); + + return ret; +} diff --git a/scripts/dtc/libfdt/fdt_ro.c b/scripts/dtc/libfdt/fdt_ro.c index 3d00d2eee0e3..08de2cce674d 100644 --- a/scripts/dtc/libfdt/fdt_ro.c +++ b/scripts/dtc/libfdt/fdt_ro.c @@ -60,7 +60,7 @@ static int _fdt_nodename_eq(const void *fdt, int offset, { const char *p = fdt_offset_ptr(fdt, offset + FDT_TAGSIZE, len+1); - if (! p) + if (!p) /* short match */ return 0; @@ -327,7 +327,7 @@ const void *fdt_getprop_namelen(const void *fdt, int nodeoffset, const struct fdt_property *prop; prop = fdt_get_property_namelen(fdt, nodeoffset, name, namelen, lenp); - if (! prop) + if (!prop) return NULL; return prop->data; diff --git a/scripts/dtc/libfdt/fdt_rw.c b/scripts/dtc/libfdt/fdt_rw.c index 3fd5847377c9..5c3a2bb0bc6b 100644 --- a/scripts/dtc/libfdt/fdt_rw.c +++ b/scripts/dtc/libfdt/fdt_rw.c @@ -207,7 +207,7 @@ static int _fdt_resize_property(void *fdt, int nodeoffset, const char *name, int err; *prop = fdt_get_property_w(fdt, nodeoffset, name, &oldlen); - if (! (*prop)) + if (!*prop) return oldlen; if ((err = _fdt_splice_struct(fdt, (*prop)->data, FDT_TAGALIGN(oldlen), @@ -269,8 +269,8 @@ int fdt_set_name(void *fdt, int nodeoffset, const char *name) return 0; } -int fdt_setprop(void *fdt, int nodeoffset, const char *name, - const void *val, int len) +int fdt_setprop_placeholder(void *fdt, int nodeoffset, const char *name, + int len, void **prop_data) { struct fdt_property *prop; int err; @@ -283,8 +283,22 @@ int fdt_setprop(void *fdt, int nodeoffset, const char *name, if (err) return err; + *prop_data = prop->data; + return 0; +} + +int fdt_setprop(void *fdt, int nodeoffset, const char *name, + const void *val, int len) +{ + void *prop_data; + int err; + + err = fdt_setprop_placeholder(fdt, nodeoffset, name, len, &prop_data); + if (err) + return err; + if (len) - memcpy(prop->data, val, len); + memcpy(prop_data, val, len); return 0; } @@ -323,7 +337,7 @@ int fdt_delprop(void *fdt, int nodeoffset, const char *name) FDT_RW_CHECK_HEADER(fdt); prop = fdt_get_property_w(fdt, nodeoffset, name, &len); - if (! prop) + if (!prop) return len; proplen = sizeof(*prop) + FDT_TAGALIGN(len); diff --git a/scripts/dtc/libfdt/fdt_sw.c b/scripts/dtc/libfdt/fdt_sw.c index 6a804859fd0c..2bd15e7aef87 100644 --- a/scripts/dtc/libfdt/fdt_sw.c +++ b/scripts/dtc/libfdt/fdt_sw.c @@ -220,7 +220,7 @@ static int _fdt_find_add_string(void *fdt, const char *s) return offset; } -int fdt_property(void *fdt, const char *name, const void *val, int len) +int fdt_property_placeholder(void *fdt, const char *name, int len, void **valp) { struct fdt_property *prop; int nameoff; @@ -238,7 +238,19 @@ int fdt_property(void *fdt, const char *name, const void *val, int len) prop->tag = cpu_to_fdt32(FDT_PROP); prop->nameoff = cpu_to_fdt32(nameoff); prop->len = cpu_to_fdt32(len); - memcpy(prop->data, val, len); + *valp = prop->data; + return 0; +} + +int fdt_property(void *fdt, const char *name, const void *val, int len) +{ + void *ptr; + int ret; + + ret = fdt_property_placeholder(fdt, name, len, &ptr); + if (ret) + return ret; + memcpy(ptr, val, len); return 0; } diff --git a/scripts/dtc/libfdt/fdt_wip.c b/scripts/dtc/libfdt/fdt_wip.c index 6aaab399929c..5e859198622b 100644 --- a/scripts/dtc/libfdt/fdt_wip.c +++ b/scripts/dtc/libfdt/fdt_wip.c @@ -82,7 +82,7 @@ int fdt_setprop_inplace(void *fdt, int nodeoffset, const char *name, int proplen; propval = fdt_getprop(fdt, nodeoffset, name, &proplen); - if (! propval) + if (!propval) return proplen; if (proplen != len) @@ -107,7 +107,7 @@ int fdt_nop_property(void *fdt, int nodeoffset, const char *name) int len; prop = fdt_get_property_w(fdt, nodeoffset, name, &len); - if (! prop) + if (!prop) return len; _fdt_nop_region(prop, len + sizeof(*prop)); diff --git a/scripts/dtc/libfdt/libfdt.h b/scripts/dtc/libfdt/libfdt.h index ba86caa73d01..7f83023ee109 100644 --- a/scripts/dtc/libfdt/libfdt.h +++ b/scripts/dtc/libfdt/libfdt.h @@ -1314,6 +1314,22 @@ static inline int fdt_property_cell(void *fdt, const char *name, uint32_t val) { return fdt_property_u32(fdt, name, val); } + +/** + * fdt_property_placeholder - add a new property and return a ptr to its value + * + * @fdt: pointer to the device tree blob + * @name: name of property to add + * @len: length of property value in bytes + * @valp: returns a pointer to where where the value should be placed + * + * returns: + * 0, on success + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_NOSPACE, standard meanings + */ +int fdt_property_placeholder(void *fdt, const char *name, int len, void **valp); + #define fdt_property_string(fdt, name, str) \ fdt_property(fdt, name, str, strlen(str)+1) int fdt_end_node(void *fdt); @@ -1432,6 +1448,37 @@ int fdt_set_name(void *fdt, int nodeoffset, const char *name); int fdt_setprop(void *fdt, int nodeoffset, const char *name, const void *val, int len); +/** + * fdt_setprop _placeholder - allocate space for a property + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose property to change + * @name: name of the property to change + * @len: length of the property value + * @prop_data: return pointer to property data + * + * fdt_setprop_placeholer() allocates the named property in the given node. + * If the property exists it is resized. In either case a pointer to the + * property data is returned. + * + * This function may insert or delete data from the blob, and will + * therefore change the offsets of some existing nodes. + * + * returns: + * 0, on success + * -FDT_ERR_NOSPACE, there is insufficient free space in the blob to + * contain the new property value + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_TRUNCATED, standard meanings + */ +int fdt_setprop_placeholder(void *fdt, int nodeoffset, const char *name, + int len, void **prop_data); + /** * fdt_setprop_u32 - set a property to a 32-bit integer * @fdt: pointer to the device tree blob diff --git a/scripts/dtc/livetree.c b/scripts/dtc/livetree.c index 3673de07e4e5..6846ad2fd6d2 100644 --- a/scripts/dtc/livetree.c +++ b/scripts/dtc/livetree.c @@ -216,6 +216,28 @@ struct node *merge_nodes(struct node *old_node, struct node *new_node) return old_node; } +void add_orphan_node(struct node *dt, struct node *new_node, char *ref) +{ + static unsigned int next_orphan_fragment = 0; + struct node *node; + struct property *p; + struct data d = empty_data; + char *name; + + d = data_add_marker(d, REF_PHANDLE, ref); + d = data_append_integer(d, 0xffffffff, 32); + + p = build_property("target", d); + + xasprintf(&name, "fragment@%u", + next_orphan_fragment++); + name_node(new_node, "__overlay__"); + node = build_node(p, new_node); + name_node(node, name); + + add_child(dt, node); +} + struct node *chain_node(struct node *first, struct node *list) { assert(first->next_sibling == NULL); @@ -396,6 +418,12 @@ cell_t propval_cell(struct property *prop) return fdt32_to_cpu(*((fdt32_t *)prop->val.val)); } +cell_t propval_cell_n(struct property *prop, int n) +{ + assert(prop->val.len / sizeof(cell_t) >= n); + return fdt32_to_cpu(*((fdt32_t *)prop->val.val + n)); +} + struct property *get_property_by_label(struct node *tree, const char *label, struct node **node) { @@ -478,7 +506,8 @@ struct node *get_node_by_path(struct node *tree, const char *path) p = strchr(path, '/'); for_each_child(tree, child) { - if (p && strneq(path, child->name, p-path)) + if (p && (strlen(child->name) == p-path) && + strneq(path, child->name, p-path)) return get_node_by_path(child, p+1); else if (!p && streq(path, child->name)) return child; diff --git a/scripts/dtc/version_gen.h b/scripts/dtc/version_gen.h index 1229e07b4912..d88393cab14a 100644 --- a/scripts/dtc/version_gen.h +++ b/scripts/dtc/version_gen.h @@ -1 +1 @@ -#define DTC_VERSION "DTC 1.4.4-g756ffc4f" +#define DTC_VERSION "DTC 1.4.5-gb1a60033" diff --git a/sound/soc/amlogic/auge/Makefile b/sound/soc/amlogic/auge/Makefile index aae985725881..6ebfb6271c83 100644 --- a/sound/soc/amlogic/auge/Makefile +++ b/sound/soc/amlogic/auge/Makefile @@ -3,6 +3,7 @@ obj-$(CONFIG_AMLOGIC_SND_SOC_AUGE) += audio_controller.o \ audio_clks.o \ axg,clocks.o \ g12a,clocks.o \ + tl1,clocks.o \ card.o \ card_utils.o \ tdm.o \ @@ -24,4 +25,6 @@ obj-$(CONFIG_AMLOGIC_SND_SOC_AUGE) += audio_controller.o \ effects_hw.o \ pwrdet.o \ pwrdet_hw.o \ - sharebuffer.o + sharebuffer.o \ + extn.o \ + frhdmirx_hw.o diff --git a/sound/soc/amlogic/auge/audio_clks.c b/sound/soc/amlogic/auge/audio_clks.c index 71be6a437948..1f0dd6fc1b54 100644 --- a/sound/soc/amlogic/auge/audio_clks.c +++ b/sound/soc/amlogic/auge/audio_clks.c @@ -32,6 +32,10 @@ static const struct of_device_id audio_clocks_of_match[] = { .compatible = "amlogic, g12a-audio-clocks", .data = &g12a_audio_clks_init, }, + { + .compatible = "amlogic, tl1-audio-clocks", + .data = &tl1_audio_clks_init, + }, {}, }; MODULE_DEVICE_TABLE(of, audio_clocks_of_match); diff --git a/sound/soc/amlogic/auge/audio_clks.h b/sound/soc/amlogic/auge/audio_clks.h index 06d8a3d0997d..359fbfc5560f 100644 --- a/sound/soc/amlogic/auge/audio_clks.h +++ b/sound/soc/amlogic/auge/audio_clks.h @@ -92,6 +92,7 @@ struct audio_clk_init { extern struct audio_clk_init axg_audio_clks_init; extern struct audio_clk_init g12a_audio_clks_init; +extern struct audio_clk_init tl1_audio_clks_init; struct clk_chipinfo { /* force clock source as oscin(24M) */ diff --git a/sound/soc/amlogic/auge/audio_controller.c b/sound/soc/amlogic/auge/audio_controller.c index b7ab682d2cc3..c625269190e2 100644 --- a/sound/soc/amlogic/auge/audio_controller.c +++ b/sound/soc/amlogic/auge/audio_controller.c @@ -103,7 +103,7 @@ static int register_audio_controller(struct platform_device *pdev, platform_set_drvdata(pdev, actrl); /* gate on all clks on bringup stage, need gate separately */ - aml_audiobus_write(actrl, EE_AUDIO_CLK_GATE_EN, 0xffffff); + aml_audiobus_write(actrl, EE_AUDIO_CLK_GATE_EN0, 0xffffff); return 0; } diff --git a/sound/soc/amlogic/auge/audio_utils.c b/sound/soc/amlogic/auge/audio_utils.c index d0d5dd6a753f..53e8fb98d3d2 100644 --- a/sound/soc/amlogic/auge/audio_utils.c +++ b/sound/soc/amlogic/auge/audio_utils.c @@ -937,6 +937,12 @@ int snd_card_add_kcontrols(struct snd_soc_card *card) return ret; } + ret = card_add_ddr_kcontrols(card); + if (ret < 0) { + pr_err("Failed to add ddr controls\n"); + return ret; + } + return snd_soc_add_card_controls(card, snd_auge_controls, ARRAY_SIZE(snd_auge_controls)); @@ -1123,8 +1129,8 @@ int loopback_hw_params(struct snd_pcm_substream *substream, clk_set_rate(lb_cfg->tdmin_mpll, mpll_freq); pr_info("mpll freq:%d, %lu\n", mpll_freq, clk_get_rate(lb_cfg->tdmin_mpll)); - offset = EE_AUDIO_MCLK_B_CTRL - EE_AUDIO_MCLK_A_CTRL; - reg = EE_AUDIO_MCLK_A_CTRL + offset * clk_id; + offset = EE_AUDIO_MCLK_B_CTRL(0) - EE_AUDIO_MCLK_A_CTRL(0); + reg = EE_AUDIO_MCLK_A_CTRL(0) + offset * clk_id; audiobus_write(reg, 1 << 31 | /*clk enable*/ clk_id << 24 | /*clk src*/ @@ -1472,3 +1478,30 @@ void auge_toacodec_ctrl(int tdmout_id) | tdmout_id << 0 /* mclk */ ); } + +void fratv_enable(bool enable) +{ + /* Need reset firstlry ? */ + if (enable) { + audiobus_update_bits(EE_AUDIO_FRATV_CTRL0, + 0x1 << 29, + 0x1 << 29); + audiobus_update_bits(EE_AUDIO_FRATV_CTRL0, + 0x1 << 28, + 0x1 << 28); + } else + audiobus_update_bits(EE_AUDIO_FRATV_CTRL0, + 0x3 << 28, + 0x0 << 28); + + audiobus_update_bits(EE_AUDIO_FRATV_CTRL0, 0x1 << 31, enable << 31); +} + +/* source select + * 0: select from ATV; + * 1: select from ADEC; + */ +void fratv_src_select(int src) +{ + audiobus_update_bits(EE_AUDIO_FRATV_CTRL0, 0x1 << 20, (bool)src << 20); +} diff --git a/sound/soc/amlogic/auge/audio_utils.h b/sound/soc/amlogic/auge/audio_utils.h index e77a2d2cd212..c08470fe013d 100644 --- a/sound/soc/amlogic/auge/audio_utils.h +++ b/sound/soc/amlogic/auge/audio_utils.h @@ -159,4 +159,7 @@ extern int loopback_trigger( extern void audio_locker_set(int enable); extern int audio_locker_get(void); + +extern void fratv_enable(bool enable); +extern void fratv_src_select(int src); #endif diff --git a/sound/soc/amlogic/auge/axg,clocks.c b/sound/soc/amlogic/auge/axg,clocks.c index 10a951d3fc73..e337ac3c89bf 100644 --- a/sound/soc/amlogic/auge/axg,clocks.c +++ b/sound/soc/amlogic/auge/axg,clocks.c @@ -33,26 +33,26 @@ static const char *const audioclk_parent_names[] = { "i_slv_sclk_d", "i_slv_sclk_e", "i_slv_sclk_f", "i_slv_sclk_g", "i_slv_sclk_h", "i_slv_sclk_i", "i_slv_sclk_j"}; -CLOCK_GATE(audio_ddr_arb, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN), 0); -CLOCK_GATE(audio_pdm, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN), 1); -CLOCK_GATE(audio_tdmina, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN), 2); -CLOCK_GATE(audio_tdminb, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN), 3); -CLOCK_GATE(audio_tdminc, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN), 4); -CLOCK_GATE(audio_tdminlb, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN), 5); -CLOCK_GATE(audio_tdmouta, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN), 6); -CLOCK_GATE(audio_tdmoutb, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN), 7); -CLOCK_GATE(audio_tdmoutc, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN), 8); -CLOCK_GATE(audio_frddra, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN), 9); -CLOCK_GATE(audio_frddrb, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN), 10); -CLOCK_GATE(audio_frddrc, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN), 11); -CLOCK_GATE(audio_toddra, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN), 12); -CLOCK_GATE(audio_toddrb, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN), 13); -CLOCK_GATE(audio_toddrc, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN), 14); -CLOCK_GATE(audio_loopback, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN), 15); -CLOCK_GATE(audio_spdifin, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN), 16); -CLOCK_GATE(audio_spdifout, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN), 17); -CLOCK_GATE(audio_resample, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN), 18); -CLOCK_GATE(audio_power_detect, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN), 19); +CLOCK_GATE(audio_ddr_arb, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN0), 0); +CLOCK_GATE(audio_pdm, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN0), 1); +CLOCK_GATE(audio_tdmina, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN0), 2); +CLOCK_GATE(audio_tdminb, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN0), 3); +CLOCK_GATE(audio_tdminc, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN0), 4); +CLOCK_GATE(audio_tdminlb, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN0), 5); +CLOCK_GATE(audio_tdmouta, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN0), 6); +CLOCK_GATE(audio_tdmoutb, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN0), 7); +CLOCK_GATE(audio_tdmoutc, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN0), 8); +CLOCK_GATE(audio_frddra, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN0), 9); +CLOCK_GATE(audio_frddrb, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN0), 10); +CLOCK_GATE(audio_frddrc, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN0), 11); +CLOCK_GATE(audio_toddra, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN0), 12); +CLOCK_GATE(audio_toddrb, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN0), 13); +CLOCK_GATE(audio_toddrc, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN0), 14); +CLOCK_GATE(audio_loopback, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN0), 15); +CLOCK_GATE(audio_spdifin, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN0), 16); +CLOCK_GATE(audio_spdifout, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN0), 17); +CLOCK_GATE(audio_resample, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN0), 18); +CLOCK_GATE(audio_power_detect, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN0), 19); static struct clk_gate *axg_audio_clk_gates[] = { &audio_ddr_arb, @@ -120,29 +120,29 @@ static int axg_clk_gates_init(struct clk **clks, void __iomem *iobase) } /* mclk_a */ -CLOCK_COM_MUX(mclk_a, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_A_CTRL), 0x7, 24); -CLOCK_COM_DIV(mclk_a, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_A_CTRL), 0, 16); -CLOCK_COM_GATE(mclk_a, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_A_CTRL), 31); +CLOCK_COM_MUX(mclk_a, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_A_CTRL(0)), 0x7, 24); +CLOCK_COM_DIV(mclk_a, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_A_CTRL(0)), 0, 16); +CLOCK_COM_GATE(mclk_a, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_A_CTRL(0)), 31); /* mclk_b */ -CLOCK_COM_MUX(mclk_b, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_B_CTRL), 0x7, 24); -CLOCK_COM_DIV(mclk_b, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_B_CTRL), 0, 16); -CLOCK_COM_GATE(mclk_b, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_B_CTRL), 31); +CLOCK_COM_MUX(mclk_b, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_B_CTRL(0)), 0x7, 24); +CLOCK_COM_DIV(mclk_b, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_B_CTRL(0)), 0, 16); +CLOCK_COM_GATE(mclk_b, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_B_CTRL(0)), 31); /* mclk_c */ -CLOCK_COM_MUX(mclk_c, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_C_CTRL), 0x7, 24); -CLOCK_COM_DIV(mclk_c, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_C_CTRL), 0, 16); -CLOCK_COM_GATE(mclk_c, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_C_CTRL), 31); +CLOCK_COM_MUX(mclk_c, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_C_CTRL(0)), 0x7, 24); +CLOCK_COM_DIV(mclk_c, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_C_CTRL(0)), 0, 16); +CLOCK_COM_GATE(mclk_c, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_C_CTRL(0)), 31); /* mclk_d */ -CLOCK_COM_MUX(mclk_d, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_D_CTRL), 0x7, 24); -CLOCK_COM_DIV(mclk_d, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_D_CTRL), 0, 16); -CLOCK_COM_GATE(mclk_d, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_D_CTRL), 31); +CLOCK_COM_MUX(mclk_d, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_D_CTRL(0)), 0x7, 24); +CLOCK_COM_DIV(mclk_d, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_D_CTRL(0)), 0, 16); +CLOCK_COM_GATE(mclk_d, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_D_CTRL(0)), 31); /* mclk_e */ -CLOCK_COM_MUX(mclk_e, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_E_CTRL), 0x7, 24); -CLOCK_COM_DIV(mclk_e, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_E_CTRL), 0, 16); -CLOCK_COM_GATE(mclk_e, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_E_CTRL), 31); +CLOCK_COM_MUX(mclk_e, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_E_CTRL(0)), 0x7, 24); +CLOCK_COM_DIV(mclk_e, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_E_CTRL(0)), 0, 16); +CLOCK_COM_GATE(mclk_e, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_E_CTRL(0)), 31); /* mclk_f */ -CLOCK_COM_MUX(mclk_f, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_F_CTRL), 0x7, 24); -CLOCK_COM_DIV(mclk_f, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_F_CTRL), 0, 16); -CLOCK_COM_GATE(mclk_f, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_F_CTRL), 31); +CLOCK_COM_MUX(mclk_f, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_F_CTRL(0)), 0x7, 24); +CLOCK_COM_DIV(mclk_f, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_F_CTRL(0)), 0, 16); +CLOCK_COM_GATE(mclk_f, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_F_CTRL(0)), 31); /* spdifin */ CLOCK_COM_MUX(spdifin, AUD_ADDR_OFFSET(EE_AUDIO_CLK_SPDIFIN_CTRL), 0x7, 24); CLOCK_COM_DIV(spdifin, AUD_ADDR_OFFSET(EE_AUDIO_CLK_SPDIFIN_CTRL), 0, 8); @@ -168,10 +168,10 @@ CLOCK_COM_MUX(locker_in, AUD_ADDR_OFFSET(EE_AUDIO_CLK_LOCKER_CTRL), 0xf, 8); CLOCK_COM_DIV(locker_in, AUD_ADDR_OFFSET(EE_AUDIO_CLK_LOCKER_CTRL), 0, 8); CLOCK_COM_GATE(locker_in, AUD_ADDR_OFFSET(EE_AUDIO_CLK_LOCKER_CTRL), 15); /* resample*/ -CLOCK_COM_MUX(resample, AUD_ADDR_OFFSET(EE_AUDIO_CLK_RESAMPLE_CTRL), 0xf, 24); +CLOCK_COM_MUX(resample, AUD_ADDR_OFFSET(EE_AUDIO_CLK_RESAMPLEA_CTRL), 0xf, 24); /* div is fake */ -CLOCK_COM_DIV(resample, AUD_ADDR_OFFSET(EE_AUDIO_CLK_RESAMPLE_CTRL), 0, 0); -CLOCK_COM_GATE(resample, AUD_ADDR_OFFSET(EE_AUDIO_CLK_RESAMPLE_CTRL), 31); +CLOCK_COM_DIV(resample, AUD_ADDR_OFFSET(EE_AUDIO_CLK_RESAMPLEA_CTRL), 0, 0); +CLOCK_COM_GATE(resample, AUD_ADDR_OFFSET(EE_AUDIO_CLK_RESAMPLEA_CTRL), 31); static int axg_clks_init(struct clk **clks, void __iomem *iobase) { diff --git a/sound/soc/amlogic/auge/card.c b/sound/soc/amlogic/auge/card.c index 3db78c76c03d..f69a49c82c12 100644 --- a/sound/soc/amlogic/auge/card.c +++ b/sound/soc/amlogic/auge/card.c @@ -433,12 +433,7 @@ static int aml_card_hw_params(struct snd_pcm_substream *substream, aml_priv_to_props(priv, rtd->num); unsigned int mclk = 0, mclk_fs = 0; int i = 0, ret = 0; - int clk_dir = 0; - - if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) - clk_dir = SND_SOC_CLOCK_OUT; - else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) - clk_dir = SND_SOC_CLOCK_IN; + int clk_idx = substream->stream; if (priv->mclk_fs) mclk_fs = priv->mclk_fs; @@ -454,14 +449,14 @@ static int aml_card_hw_params(struct snd_pcm_substream *substream, for (i = 0; i < rtd->num_codecs; i++) { codec_dai = rtd->codec_dais[i]; ret = snd_soc_dai_set_sysclk(codec_dai, 0, mclk, - clk_dir); + SND_SOC_CLOCK_IN); if (ret && ret != -ENOTSUPP) goto err; } - ret = snd_soc_dai_set_sysclk(cpu_dai, 0, mclk, - clk_dir); + ret = snd_soc_dai_set_sysclk(cpu_dai, clk_idx, mclk, + SND_SOC_CLOCK_OUT); if (ret && ret != -ENOTSUPP) goto err; @@ -863,6 +858,10 @@ static struct aml_chipset_info g12a_chipset_info = { .eqdrc_fn = true, }; +static struct aml_chipset_info tl1_chipset_info = { + .spdif_b = true, +}; + static const struct of_device_id auge_of_match[] = { { .compatible = "amlogic, axg-sound-card", @@ -871,6 +870,10 @@ static const struct of_device_id auge_of_match[] = { .compatible = "amlogic, g12a-sound-card", .data = &g12a_chipset_info, }, + { + .compatible = "amlogic, tl1-sound-card", + .data = &tl1_chipset_info, + }, {}, }; MODULE_DEVICE_TABLE(of, auge_of_match); @@ -991,6 +994,7 @@ static int aml_card_probe(struct platform_device *pdev) if (ret >= 0) return ret; err: + pr_err("%s error ret:%d\n", __func__, ret); aml_card_clean_reference(&priv->snd_card); return ret; diff --git a/sound/soc/amlogic/auge/ddr_mngr.c b/sound/soc/amlogic/auge/ddr_mngr.c index 3410ed8906ef..6d3199fe429e 100644 --- a/sound/soc/amlogic/auge/ddr_mngr.c +++ b/sound/soc/amlogic/auge/ddr_mngr.c @@ -56,14 +56,26 @@ struct ddr_desc { #endif struct ddr_chipinfo { - /* INT and Start address separated */ - bool addr_separated; + /* INT and Start address is same or separated */ + bool int_start_same_addr; /* force finished */ bool force_finished; /* same source */ bool same_src_fn; /* insert channel number */ bool insert_chnum; + /* source sel switch to ctrl1 + * for toddr, 0: source sel is controlled by ctrl0 + * 1: source sel is controlled by ctrl1 + * for frddr, 0: source sel is controlled by ctrl0 + * 1: source sel is controlled by ctrl2 + */ + bool src_sel_ctrl; + /* toddr number max + * 0: default, 3 toddr, axg, g12a, g12b + * 4: 4 toddr, tl1 + */ + int fifo_num; }; struct toddr { @@ -123,7 +135,7 @@ struct frddr { struct ddr_chipinfo *chipinfo; }; -#define DDRMAX 3 +#define DDRMAX 4 static struct frddr frddrs[DDRMAX]; static struct toddr toddrs[DDRMAX]; @@ -303,7 +315,7 @@ int aml_toddr_set_buf(struct toddr *to, unsigned int start, /* int address */ if (to->chipinfo - && to->chipinfo->addr_separated) { + && (!to->chipinfo->int_start_same_addr)) { reg = calc_toddr_address(EE_AUDIO_TODDR_A_INIT_ADDR, reg_base); aml_audiobus_write(actrl, reg, start); } @@ -372,18 +384,36 @@ void aml_toddr_select_src(struct toddr *to, enum toddr_src src) src = LOOPBACK; } - reg = calc_toddr_address(EE_AUDIO_TODDR_A_CTRL0, reg_base); - aml_audiobus_update_bits(actrl, reg, 0x7, src & 0x7); + if (to->chipinfo + && to->chipinfo->src_sel_ctrl) { + reg = calc_toddr_address(EE_AUDIO_TODDR_A_CTRL1, reg_base); + aml_audiobus_update_bits(actrl, reg, + 0xf << 28, + (src & 0xf) << 28); + } else { + reg = calc_toddr_address(EE_AUDIO_TODDR_A_CTRL0, reg_base); + aml_audiobus_update_bits(actrl, reg, 0x7, src & 0x7); + } } void aml_toddr_set_fifos(struct toddr *to, unsigned int thresh) { struct aml_audio_controller *actrl = to->actrl; unsigned int reg_base = to->reg_base; - unsigned int reg; + unsigned int reg, mask, val; reg = calc_toddr_address(EE_AUDIO_TODDR_A_CTRL1, reg_base); - aml_audiobus_write(actrl, reg, (thresh-1)<<16|2<<8); + + if (to->chipinfo + && to->chipinfo->src_sel_ctrl) { + mask = 0xfff << 12 | 0xf << 8; + val = (thresh-1) << 12 | 2 << 8; + } else { + mask = 0xff << 16 | 0xf << 8; + val = (thresh-1) << 16 | 2 << 8; + } + + aml_audiobus_update_bits(actrl, reg, mask, val); } void aml_toddr_set_format(struct toddr *to, struct toddr_fmt *fmt) @@ -806,7 +836,7 @@ int aml_frddr_set_buf(struct frddr *fr, unsigned int start, /* int address */ if (fr->chipinfo - && fr->chipinfo->addr_separated) { + && (!fr->chipinfo->int_start_same_addr)) { reg = calc_frddr_address(EE_AUDIO_FRDDR_A_INIT_ADDR, reg_base); aml_audiobus_write(actrl, reg, start); } @@ -860,17 +890,26 @@ void aml_frddr_select_dst(struct frddr *fr, enum frddr_dest dst) { struct aml_audio_controller *actrl = fr->actrl; unsigned int reg_base = fr->reg_base; - unsigned int reg; + unsigned int reg, src_sel_en; fr->dest = dst; - reg = calc_frddr_address(EE_AUDIO_FRDDR_A_CTRL0, reg_base); - aml_audiobus_update_bits(actrl, reg, 0x7, dst & 0x7); + if (fr->chipinfo + && fr->chipinfo->src_sel_ctrl) { + reg = calc_frddr_address(EE_AUDIO_FRDDR_A_CTRL2, reg_base); + src_sel_en = 4; + } else { + reg = calc_frddr_address(EE_AUDIO_FRDDR_A_CTRL0, reg_base); + src_sel_en = 3; + } + + aml_audiobus_update_bits(actrl, reg, 0x7, dst & 0x7); /* same source en */ if (fr->chipinfo && fr->chipinfo->same_src_fn) { - aml_audiobus_update_bits(actrl, reg, 1 << 3, 1 << 3); + aml_audiobus_update_bits(actrl, reg, + 1 << src_sel_en, 1 << src_sel_en); } } @@ -1057,20 +1096,142 @@ void frddr_deinit_without_mngr(unsigned int frddr_index) audiobus_write(reg, 0x0); } +static int toddr_src_idx = -1; + +static const char *const toddr_src_sel_texts[] = { + "TDMIN_A", "TDMIN_B", "TDMIN_C", "SPDIFIN", + "PDMIN", "FRATV", "TDMIN_LB", "LOOPBACK_A", + "FRHDMIRX", "LOOPBACK_B", "SPDIFIN_LB", + "RESERVED", "RESERVED", "RESERVED", "RESERVED", + "VAD" +}; + +static const struct soc_enum toddr_input_source_enum = + SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, ARRAY_SIZE(toddr_src_sel_texts), + toddr_src_sel_texts); + +int toddr_src_get(void) +{ + return toddr_src_idx; +} + +const char *toddr_src_get_str(int idx) +{ + if (idx < 0 || idx > 15) + return NULL; + + return toddr_src_sel_texts[idx]; +} + +static int toddr_src_enum_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + ucontrol->value.enumerated.item[0] = toddr_src_idx; + + return 0; +} + +static int toddr_src_enum_set(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + toddr_src_idx = ucontrol->value.enumerated.item[0]; + + return 0; +} + +static int frddr_src_idx = -1; + +static const char *const frddr_src_sel_texts[] = { + "TDMOUT_A", "TDMOUT_B", "TDMOUT_C", "SPDIFOUT", "SPDIFOUT_B" +}; + +static const struct soc_enum frddr_output_source_enum = + SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, ARRAY_SIZE(frddr_src_sel_texts), + frddr_src_sel_texts); + +int frddr_src_get(void) +{ + return frddr_src_idx; +} + +const char *frddr_src_get_str(int idx) +{ + if (idx < 0 || idx > 4) + return NULL; + + return frddr_src_sel_texts[idx]; +} + +static int frddr_src_enum_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + ucontrol->value.enumerated.item[0] = frddr_src_idx; + + return 0; +} + +static int frddr_src_enum_set(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + frddr_src_idx = ucontrol->value.enumerated.item[0]; + + return 0; +} + +static const struct snd_kcontrol_new snd_ddr_controls[] = { + SOC_ENUM_EXT("Audio In Source", + toddr_input_source_enum, + toddr_src_enum_get, + toddr_src_enum_set), + SOC_ENUM_EXT("Audio Out Sink", + toddr_input_source_enum, + frddr_src_enum_get, + frddr_src_enum_set), +}; + +int card_add_ddr_kcontrols(struct snd_soc_card *card) +{ + unsigned int idx; + int err; + + for (idx = 0; idx < ARRAY_SIZE(snd_ddr_controls); idx++) { + err = snd_ctl_add(card->snd_card, + snd_ctl_new1(&snd_ddr_controls[idx], + NULL)); + if (err < 0) + return err; + } + + return 0; +} + +static struct ddr_chipinfo axg_ddr_chipinfo = { + .int_start_same_addr = true, +}; + static struct ddr_chipinfo g12a_ddr_chipinfo = { - .addr_separated = true, .same_src_fn = true, }; +static struct ddr_chipinfo tl1_ddr_chipinfo = { + .same_src_fn = true, + .src_sel_ctrl = true, + .fifo_num = 4, +}; static const struct of_device_id aml_ddr_mngr_device_id[] = { { .compatible = "amlogic, axg-audio-ddr-manager", + .data = &axg_ddr_chipinfo, }, { .compatible = "amlogic, g12a-audio-ddr-manager", .data = &g12a_ddr_chipinfo, }, + { + .compatible = "amlogic, tl1-audio-ddr-manager", + .data = &tl1_ddr_chipinfo, + }, {}, }; MODULE_DEVICE_TABLE(of, aml_ddr_mngr_device_id); @@ -1078,6 +1239,7 @@ MODULE_DEVICE_TABLE(of, aml_ddr_mngr_device_id); static int aml_ddr_mngr_platform_probe(struct platform_device *pdev) { struct ddr_chipinfo *p_ddr_chipinfo; + int ddr_num = 3; /* early chipset support max 3 ddr num */ int i; p_ddr_chipinfo = (struct ddr_chipinfo *) @@ -1095,7 +1257,14 @@ static int aml_ddr_mngr_platform_probe(struct platform_device *pdev) frddrs[DDR_B].irq = platform_get_irq_byname(pdev, "frddr_b"); frddrs[DDR_C].irq = platform_get_irq_byname(pdev, "frddr_c"); - for (i = 0; i < DDRMAX; i++) { + if (p_ddr_chipinfo + && (p_ddr_chipinfo->fifo_num == 4)) { + toddrs[DDR_D].irq = platform_get_irq_byname(pdev, "toddr_d"); + frddrs[DDR_D].irq = platform_get_irq_byname(pdev, "frddr_d"); + ddr_num = p_ddr_chipinfo->fifo_num; + } + + for (i = 0; i < ddr_num; i++) { pr_info("%d, irqs toddr %d, frddr %d\n", i, toddrs[i].irq, frddrs[i].irq); if (toddrs[i].irq <= 0 || frddrs[i].irq <= 0) { @@ -1119,13 +1288,22 @@ static int aml_ddr_mngr_platform_probe(struct platform_device *pdev) frddrs[DDR_B].fifo_id = DDR_B; frddrs[DDR_C].fifo_id = DDR_C; - toddrs[DDR_A].chipinfo = p_ddr_chipinfo; - toddrs[DDR_B].chipinfo = p_ddr_chipinfo; - toddrs[DDR_C].chipinfo = p_ddr_chipinfo; - frddrs[DDR_A].chipinfo = p_ddr_chipinfo; - frddrs[DDR_B].chipinfo = p_ddr_chipinfo; - frddrs[DDR_C].chipinfo = p_ddr_chipinfo; + if (p_ddr_chipinfo) { + toddrs[DDR_A].chipinfo = p_ddr_chipinfo; + toddrs[DDR_B].chipinfo = p_ddr_chipinfo; + toddrs[DDR_C].chipinfo = p_ddr_chipinfo; + frddrs[DDR_A].chipinfo = p_ddr_chipinfo; + frddrs[DDR_B].chipinfo = p_ddr_chipinfo; + frddrs[DDR_C].chipinfo = p_ddr_chipinfo; + if (p_ddr_chipinfo->fifo_num == 4) { + toddrs[DDR_D].reg_base = EE_AUDIO_TODDR_D_CTRL0; + toddrs[DDR_D].fifo_id = DDR_D; + + frddrs[DDR_D].reg_base = EE_AUDIO_FRDDR_D_CTRL0; + frddrs[DDR_D].fifo_id = DDR_D; + } + } return 0; } diff --git a/sound/soc/amlogic/auge/ddr_mngr.h b/sound/soc/amlogic/auge/ddr_mngr.h index 5d4aac8fa70b..461ee9f7b978 100644 --- a/sound/soc/amlogic/auge/ddr_mngr.h +++ b/sound/soc/amlogic/auge/ddr_mngr.h @@ -20,12 +20,14 @@ #include #include +#include #include "audio_io.h" enum ddr_num { DDR_A, DDR_B, DDR_C, + DDR_D, }; enum ddr_types { @@ -36,15 +38,22 @@ enum ddr_types { RJ_32BITS, }; +/* + * from tl1, add new source FRATV, FRHDMIRX, LOOPBACK_B, SPDIFIN_LB, VAD + */ enum toddr_src { TDMIN_A, TDMIN_B, TDMIN_C, SPDIFIN, PDMIN, - NONE, + FRATV, /* NONE for axg, g12a, g12b */ TDMIN_LB, LOOPBACK, + FRHDMIRX, /* from tl1 chipset*/ + LOOPBACK_B, + SPDIFIN_LB, + VAD, }; enum frddr_dest { @@ -116,5 +125,13 @@ void aml_aed_enable(bool enable, int aed_module); void frddr_init_without_mngr(unsigned int frddr_index, unsigned int src0_sel); void frddr_deinit_without_mngr(unsigned int frddr_index); + +int toddr_src_get(void); +const char *toddr_src_get_str(int idx); +int frddr_src_get(void); +const char *frddr_src_get_str(int idx); + +int card_add_ddr_kcontrols(struct snd_soc_card *card); + #endif diff --git a/sound/soc/amlogic/auge/effects.c b/sound/soc/amlogic/auge/effects.c index 63c95c5cb4b6..5ce778d820dd 100644 --- a/sound/soc/amlogic/auge/effects.c +++ b/sound/soc/amlogic/auge/effects.c @@ -174,27 +174,27 @@ static const struct snd_kcontrol_new snd_eqdrc_controls[] = { * 1:multiply gain after ng */ SOC_SINGLE_EXT_TLV("EQ Volume Pos", - AED_EQ_VOLUME, 28, 0x1, 0, + AED_EQ_VOLUME_G12X, 28, 0x1, 0, mixer_eqdrc_read, mixer_eqdrc_write, NULL), SOC_SINGLE_EXT_TLV("EQ master volume", - AED_EQ_VOLUME, 16, 0x3FF, 1, + AED_EQ_VOLUME_G12X, 16, 0x3FF, 1, mixer_eqdrc_read, mixer_eqdrc_write, mvol_tlv), SOC_SINGLE_EXT_TLV("EQ ch1 volume", - AED_EQ_VOLUME, 8, 0xFF, 1, + AED_EQ_VOLUME_G12X, 8, 0xFF, 1, mixer_eqdrc_read, mixer_eqdrc_write, chvol_tlv), SOC_SINGLE_EXT_TLV("EQ ch2 volume", - AED_EQ_VOLUME, 0, 0xFF, 1, + AED_EQ_VOLUME_G12X, 0, 0xFF, 1, mixer_eqdrc_read, mixer_eqdrc_write, chvol_tlv), SOC_SINGLE_EXT("EQ master volume mute", - AED_MUTE, 31, 0x1, 0, + AED_MUTE_G12X, 31, 0x1, 0, mixer_eqdrc_read, mixer_eqdrc_write), SOC_SINGLE_EXT("EQ/DRC Channel Mask", @@ -210,7 +210,7 @@ static const struct snd_kcontrol_new snd_eqdrc_controls[] = { mixer_eqdrc_read, mixer_set_AED_req_ctrl), SOC_SINGLE_EXT("EQ enable", - AED_EQ_EN, 0, 0x1, 0, + AED_EQ_EN_G12X, 0, 0x1, 0, mixer_eqdrc_read, mixer_set_EQ), SOC_SINGLE_EXT("DRC enable", diff --git a/sound/soc/amlogic/auge/effects_hw.c b/sound/soc/amlogic/auge/effects_hw.c index 86400682fa56..a2d26770c1ab 100644 --- a/sound/soc/amlogic/auge/effects_hw.c +++ b/sound/soc/amlogic/auge/effects_hw.c @@ -23,11 +23,11 @@ int DRC0_enable(int enable, int thd0, int k0) { if (enable == 1) { - eqdrc_write(AED_DRC_THD0, thd0/*aml_drc_tko_table[2]*/); - eqdrc_write(AED_DRC_K0, k0/*aml_drc_tko_table[4]*/); + eqdrc_write(AED_DRC_THD0_G12X, thd0/*aml_drc_tko_table[2]*/); + eqdrc_write(AED_DRC_K0_G12X, k0/*aml_drc_tko_table[4]*/); } else { - eqdrc_write(AED_DRC_THD0, 0xbf000000); - eqdrc_write(AED_DRC_K0, 0x40000); + eqdrc_write(AED_DRC_THD0_G12X, 0xbf000000); + eqdrc_write(AED_DRC_K0_G12X, 0x40000); } return 0; @@ -49,13 +49,13 @@ int set_internal_EQ_volume( unsigned int channel_1_volume, unsigned int channel_2_volume) { - eqdrc_write(AED_EQ_VOLUME, (0 << 30) /* volume step: 0.125dB*/ + eqdrc_write(AED_EQ_VOLUME_G12X, (0 << 30) /* volume step: 0.125dB*/ | (master_volume << 16) /* master volume: 0dB*/ | (channel_1_volume << 8) /* channel 1 volume: 0dB*/ | (channel_2_volume << 0) /* channel 2 volume: 0dB*/ ); - eqdrc_write(AED_EQ_VOLUME_SLEW_CNT, 0x40); - eqdrc_write(AED_MUTE, 0); + eqdrc_write(AED_EQ_VOLUME_SLEW_CNT_G12X, 0x40); + eqdrc_write(AED_MUTE_G12X, 0); return 0; } @@ -122,7 +122,7 @@ void aed_set_eq(int enable, int params_len, unsigned int *params) } } - eqdrc_update_bits(AED_EQ_EN, 1, enable); + eqdrc_update_bits(AED_EQ_EN_G12X, 1, enable); } void aed_set_drc(int enable, int drc_len, unsigned int *drc_params, diff --git a/sound/soc/amlogic/auge/extn.c b/sound/soc/amlogic/auge/extn.c new file mode 100644 index 000000000000..c437e9f1de78 --- /dev/null +++ b/sound/soc/amlogic/auge/extn.c @@ -0,0 +1,567 @@ +/* + * sound/soc/amlogic/auge/extn.c + * + * Copyright (C) 2017 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * Audio External Input/Out drirver + * such as fratv, frhdmirx + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "ddr_mngr.h" +#include "audio_utils.h" +#include "frhdmirx_hw.h" + +#define DRV_NAME "EXTN" + +struct extn { + struct aml_audio_controller *actrl; + struct device *dev; + unsigned int sysclk_freq; + + int irq_frhdmirx; + + struct toddr *tddr; + struct frddr *fddr; +}; + +#define PREALLOC_BUFFER (32 * 1024) +#define PREALLOC_BUFFER_MAX (256 * 1024) + +#define EXTN_RATES (SNDRV_PCM_RATE_8000_192000) +#define EXTN_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\ + SNDRV_PCM_FMTBIT_S24_LE |\ + SNDRV_PCM_FMTBIT_S32_LE) + +static const struct snd_pcm_hardware extn_hardware = { + .info = + SNDRV_PCM_INFO_MMAP | + SNDRV_PCM_INFO_MMAP_VALID | + SNDRV_PCM_INFO_INTERLEAVED | + SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE, + + .formats = EXTN_FORMATS, + + .period_bytes_min = 64, + .period_bytes_max = 128 * 1024, + .periods_min = 2, + .periods_max = 1024, + .buffer_bytes_max = 256 * 1024, + + .rate_min = 8000, + .rate_max = 192000, + .channels_min = 1, + .channels_max = 32, +}; + +static irqreturn_t extn_ddr_isr(int irq, void *devid) +{ + struct snd_pcm_substream *substream = + (struct snd_pcm_substream *)devid; + + if (!snd_pcm_running(substream)) + return IRQ_HANDLED; + + snd_pcm_period_elapsed(substream); + + return IRQ_HANDLED; +} + +static irqreturn_t frhdmirx_isr(int irq, void *devid) +{ + return IRQ_HANDLED; +} + +static int extn_open(struct snd_pcm_substream *substream) +{ + struct snd_pcm_runtime *runtime = substream->runtime; + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct device *dev = rtd->platform->dev; + struct extn *p_extn; + + pr_info("asoc debug: %s-%d\n", __func__, __LINE__); + + p_extn = (struct extn *)dev_get_drvdata(dev); + + snd_soc_set_runtime_hwparams(substream, &extn_hardware); + + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { + p_extn->fddr = aml_audio_register_frddr(dev, + p_extn->actrl, + extn_ddr_isr, substream); + if (p_extn->fddr == NULL) { + dev_err(dev, "failed to claim from ddr\n"); + return -ENXIO; + } + } else { + p_extn->tddr = aml_audio_register_toddr(dev, + p_extn->actrl, + extn_ddr_isr, substream); + if (p_extn->tddr == NULL) { + dev_err(dev, "failed to claim to ddr\n"); + return -ENXIO; + } + + if (toddr_src_get() == FRHDMIRX) { + int ret = request_irq(p_extn->irq_frhdmirx, + frhdmirx_isr, 0, "irq_frhdmirx", + p_extn); + if (ret) { + dev_err(p_extn->dev, "failed to claim irq_frhdmirx %u\n", + p_extn->irq_frhdmirx); + return -ENXIO; + } + } + } + + runtime->private_data = p_extn; + + return 0; +} + +static int extn_close(struct snd_pcm_substream *substream) +{ + struct snd_pcm_runtime *runtime = substream->runtime; + struct extn *p_extn = runtime->private_data; + + pr_info("asoc debug: %s-%d\n", __func__, __LINE__); + + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) + aml_audio_unregister_frddr(p_extn->dev, substream); + else { + aml_audio_unregister_toddr(p_extn->dev, substream); + + if (toddr_src_get() == FRHDMIRX) + free_irq(p_extn->irq_frhdmirx, p_extn); + } + runtime->private_data = NULL; + + return 0; +} + +static int extn_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *hw_params) +{ + return snd_pcm_lib_malloc_pages(substream, + params_buffer_bytes(hw_params)); +} + +static int extn_hw_free(struct snd_pcm_substream *substream) +{ + snd_pcm_lib_free_pages(substream); + + return 0; +} + +static int extn_trigger(struct snd_pcm_substream *substream, int cmd) +{ + return 0; +} + +static int extn_prepare(struct snd_pcm_substream *substream) +{ + struct snd_pcm_runtime *runtime = substream->runtime; + struct extn *p_extn = runtime->private_data; + unsigned int start_addr, end_addr, int_addr; + + start_addr = runtime->dma_addr; + end_addr = start_addr + runtime->dma_bytes - 8; + int_addr = frames_to_bytes(runtime, runtime->period_size) / 8; + + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { + struct frddr *fr = p_extn->fddr; + + aml_frddr_set_buf(fr, start_addr, end_addr); + aml_frddr_set_intrpt(fr, int_addr); + } else { + struct toddr *to = p_extn->tddr; + + aml_toddr_set_buf(to, start_addr, end_addr); + aml_toddr_set_intrpt(to, int_addr); + } + + return 0; +} + +static snd_pcm_uframes_t extn_pointer(struct snd_pcm_substream *substream) +{ + struct snd_pcm_runtime *runtime = substream->runtime; + struct extn *p_extn = runtime->private_data; + unsigned int addr, start_addr; + snd_pcm_uframes_t frames; + + start_addr = runtime->dma_addr; + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) + addr = aml_frddr_get_position(p_extn->fddr); + else + addr = aml_toddr_get_position(p_extn->tddr); + + frames = bytes_to_frames(runtime, addr - start_addr); + if (frames > runtime->buffer_size) + frames = 0; + + return frames; +} + +int extn_silence(struct snd_pcm_substream *substream, int channel, + snd_pcm_uframes_t pos, snd_pcm_uframes_t count) +{ + struct snd_pcm_runtime *runtime = substream->runtime; + char *ppos; + int n; + + n = frames_to_bytes(runtime, count); + ppos = runtime->dma_area + frames_to_bytes(runtime, pos); + memset(ppos, 0, n); + + return 0; +} + +static int extn_mmap(struct snd_pcm_substream *substream, + struct vm_area_struct *vma) +{ + return snd_pcm_lib_default_mmap(substream, vma); +} + +static struct snd_pcm_ops extn_ops = { + .open = extn_open, + .close = extn_close, + .ioctl = snd_pcm_lib_ioctl, + .hw_params = extn_hw_params, + .hw_free = extn_hw_free, + .prepare = extn_prepare, + .trigger = extn_trigger, + .pointer = extn_pointer, + .silence = extn_silence, + .mmap = extn_mmap, +}; + +static int extn_new(struct snd_soc_pcm_runtime *rtd) +{ + return snd_pcm_lib_preallocate_pages_for_all( + rtd->pcm, SNDRV_DMA_TYPE_DEV, + rtd->card->snd_card->dev, + PREALLOC_BUFFER, PREALLOC_BUFFER_MAX); +} + +struct snd_soc_platform_driver extn_platform = { + .ops = &extn_ops, + .pcm_new = extn_new, +}; + +static int extn_dai_probe(struct snd_soc_dai *cpu_dai) +{ + pr_info("asoc debug: %s-%d\n", __func__, __LINE__); + + return 0; +} + +static int extn_dai_remove(struct snd_soc_dai *cpu_dai) +{ + return 0; +} + +static int extn_dai_startup( + struct snd_pcm_substream *substream, + struct snd_soc_dai *cpu_dai) +{ + return 0; +} + +static void extn_dai_shutdown( + struct snd_pcm_substream *substream, + struct snd_soc_dai *cpu_dai) +{ +} + +static int extn_dai_prepare( + struct snd_pcm_substream *substream, + struct snd_soc_dai *cpu_dai) +{ + struct snd_pcm_runtime *runtime = substream->runtime; + struct extn *p_extn = snd_soc_dai_get_drvdata(cpu_dai); + unsigned int bit_depth = snd_pcm_format_width(runtime->format); + + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { + struct frddr *fr = p_extn->fddr; + enum frddr_dest dst = frddr_src_get(); + + pr_info("%s Expected frddr dst:%s\n", + __func__, + frddr_src_get_str(dst)); + + aml_frddr_select_dst(fr, dst); + aml_frddr_set_fifos(fr, 0x40, 0x20); + } else { + struct toddr *to = p_extn->tddr; + unsigned int msb = 32 - 1; + unsigned int lsb = 32 - bit_depth; + unsigned int toddr_type; + unsigned int src = toddr_src_get(); + struct toddr_fmt fmt; + + switch (bit_depth) { + case 8: + case 16: + case 32: + toddr_type = 0; + break; + case 24: + toddr_type = 4; + break; + default: + pr_err("invalid bit_depth: %d\n", bit_depth); + return -EINVAL; + } + + pr_info("%s Expected toddr src:%s\n", + __func__, + toddr_src_get_str(src)); + + if (src == FRATV) + fratv_src_select(0); + else if (src == FRHDMIRX) { + frhdmirx_ctrl(runtime->channels, 0); + frhdmirx_src_select(0); + } + + fmt.type = toddr_type; + fmt.msb = msb; + fmt.lsb = lsb; + fmt.endian = 0; + fmt.bit_depth = bit_depth; + fmt.ch_num = runtime->channels; + fmt.rate = runtime->rate; + + aml_toddr_select_src(to, src); + aml_toddr_set_format(to, &fmt); + aml_toddr_set_fifos(to, 0x40); + } + + return 0; +} + +static int extn_dai_trigger(struct snd_pcm_substream *substream, int cmd, + struct snd_soc_dai *cpu_dai) +{ + struct extn *p_extn = snd_soc_dai_get_drvdata(cpu_dai); + unsigned int src = toddr_src_get(); + + switch (cmd) { + case SNDRV_PCM_TRIGGER_START: + case SNDRV_PCM_TRIGGER_RESUME: + case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { + dev_info(substream->pcm->card->dev, "External Playback enable\n"); + + aml_frddr_enable(p_extn->fddr, true); + } else { + dev_info(substream->pcm->card->dev, "External Capture enable\n"); + + if (src == FRATV) + fratv_enable(true); + else if (src == FRHDMIRX) + frhdmirx_enable(true); + + aml_toddr_enable(p_extn->tddr, true); + } + break; + case SNDRV_PCM_TRIGGER_STOP: + case SNDRV_PCM_TRIGGER_SUSPEND: + case SNDRV_PCM_TRIGGER_PAUSE_PUSH: + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { + dev_info(substream->pcm->card->dev, "External Playback disable\n"); + + aml_frddr_enable(p_extn->fddr, false); + } else { + dev_info(substream->pcm->card->dev, "External Capture disable\n"); + + if (src == FRATV) + fratv_enable(false); + else if (src == FRHDMIRX) + frhdmirx_enable(false); + + aml_toddr_enable(p_extn->tddr, false); + } + break; + default: + return -EINVAL; + } + + return 0; +} + +static int extn_dai_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params, + struct snd_soc_dai *cpu_dai) +{ + struct extn *p_extn = snd_soc_dai_get_drvdata(cpu_dai); + unsigned int rate = params_rate(params); + int ret = 0; + + pr_info("%s:rate:%d, sysclk:%d\n", + __func__, + rate, + p_extn->sysclk_freq); + + return ret; +} + +static int extn_dai_set_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt) +{ + struct extn *p_extn = snd_soc_dai_get_drvdata(cpu_dai); + + pr_info("asoc extn_dai_set_fmt, %#x, %p\n", fmt, p_extn); + + return 0; +} + +static int extn_dai_set_sysclk(struct snd_soc_dai *cpu_dai, + int clk_id, unsigned int freq, int dir) +{ + struct extn *p_extn = snd_soc_dai_get_drvdata(cpu_dai); + + p_extn->sysclk_freq = freq; + pr_info("extn_dai_set_sysclk, %d, %d, %d\n", + clk_id, freq, dir); + + return 0; +} + +static struct snd_soc_dai_ops extn_dai_ops = { + .startup = extn_dai_startup, + .shutdown = extn_dai_shutdown, + .prepare = extn_dai_prepare, + .trigger = extn_dai_trigger, + .hw_params = extn_dai_hw_params, + .set_fmt = extn_dai_set_fmt, + .set_sysclk = extn_dai_set_sysclk, +}; + +static struct snd_soc_dai_driver extn_dai[] = { + { + .name = "EXTN", + .id = 0, + .probe = extn_dai_probe, + .remove = extn_dai_remove, + .playback = { + .channels_min = 1, + .channels_max = 32, + .rates = EXTN_RATES, + .formats = EXTN_FORMATS, + }, + .capture = { + .channels_min = 1, + .channels_max = 32, + .rates = EXTN_RATES, + .formats = EXTN_FORMATS, + }, + .ops = &extn_dai_ops, + }, +}; + +static const struct snd_soc_component_driver extn_component = { + .name = DRV_NAME, +}; + +static const struct of_device_id extn_device_id[] = { + { + .compatible = "amlogic, snd-extn", + }, + {}, +}; + +MODULE_DEVICE_TABLE(of, extn_device_id); + +static int extn_platform_probe(struct platform_device *pdev) +{ + struct device_node *node = pdev->dev.of_node; + struct device_node *node_prt = NULL; + struct platform_device *pdev_parent; + struct device *dev = &pdev->dev; + struct aml_audio_controller *actrl = NULL; + struct extn *extn = NULL; + int ret = 0; + + + extn = devm_kzalloc(dev, sizeof(struct extn), GFP_KERNEL); + if (!extn) + return -ENOMEM; + + extn->dev = dev; + dev_set_drvdata(dev, extn); + + /* get audio controller */ + node_prt = of_get_parent(node); + if (node_prt == NULL) + return -ENXIO; + + pdev_parent = of_find_device_by_node(node_prt); + of_node_put(node_prt); + actrl = (struct aml_audio_controller *) + platform_get_drvdata(pdev_parent); + extn->actrl = actrl; + + /* irqs */ + extn->irq_frhdmirx = platform_get_irq_byname(pdev, "irq_frhdmirx"); + if (extn->irq_frhdmirx < 0) { + dev_err(dev, "Failed to get irq_frhdmirx:%d\n", + extn->irq_frhdmirx); + return -ENXIO; + } + + ret = snd_soc_register_component(&pdev->dev, + &extn_component, + extn_dai, + ARRAY_SIZE(extn_dai)); + if (ret) { + dev_err(&pdev->dev, + "snd_soc_register_component failed\n"); + return ret; + } + + pr_info("%s, register soc platform\n", __func__); + + return devm_snd_soc_register_platform(dev, &extn_platform); +} + +struct platform_driver extn_driver = { + .driver = { + .name = DRV_NAME, + .of_match_table = extn_device_id, + }, + .probe = extn_platform_probe, +}; +module_platform_driver(extn_driver); + +MODULE_AUTHOR("Amlogic, Inc."); +MODULE_DESCRIPTION("Amlogic External Input/Output ASoc driver"); +MODULE_LICENSE("GPL"); +MODULE_ALIAS("Platform:" DRV_NAME); +MODULE_DEVICE_TABLE(of, extn_device_id); diff --git a/sound/soc/amlogic/auge/frhdmirx_hw.c b/sound/soc/amlogic/auge/frhdmirx_hw.c new file mode 100644 index 000000000000..ca24d6a10006 --- /dev/null +++ b/sound/soc/amlogic/auge/frhdmirx_hw.c @@ -0,0 +1,104 @@ +/* + * sound/soc/amlogic/auge/frhdmirx_hw.c + * + * Copyright (C) 2018 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ +#include + +#include "frhdmirx_hw.h" +#include "regs.h" +#include "iomap.h" + +void frhdmirx_enable(bool enable) +{ + if (enable) { + audiobus_update_bits(EE_AUDIO_FRHDMIRX_CTRL0, + 0x1 << 29, + 0x1 << 29); + audiobus_update_bits(EE_AUDIO_FRHDMIRX_CTRL0, + 0x1 << 28, + 0x1 << 28); + } else + audiobus_update_bits(EE_AUDIO_FRHDMIRX_CTRL0, + 0x3 << 28, + 0x0 << 28); + + audiobus_update_bits(EE_AUDIO_FRHDMIRX_CTRL0, 0x1 << 31, enable << 31); +} + +/* source select + * 0: select spdif lane; + * 1: select PAO mode; + */ +void frhdmirx_src_select(int src) +{ + audiobus_update_bits(EE_AUDIO_FRHDMIRX_CTRL0, + 0x1 << 23, + (bool)src << 23); +} + +void frhdmirx_enable_irq_bits(int channels, int src) +{ + int lane, int_bits = 0, i; + + if (channels % 2) + lane = channels / 2 + 1; + else + lane = channels / 2; + + /* interrupt bits */ + if (src) { /* PAO mode */ + int_bits = (0x1 << 24 | /* PAO data: find papb */ + 0x1 << 16 /* PAO data: find pcpd changed */ + ); + } else { /* SPDIF Lane*/ + int lane_irq_bits = (0x1 << 7 | /* lane: find papb */ + 0x1 << 6 | /* lane: find papb */ + 0x1 << 5 | /* lane: find nonpcm to pcm */ + 0x1 << 4 | /* lane: find pcpd changed */ + 0x1 << 3 | /* lane: find ch status changed */ + 0x1 << 1 /* lane: find parity error */ + ); + + for (i = 0; i < lane; i++) + int_bits |= (lane_irq_bits << i); + } + audiobus_write(EE_AUDIO_FRHDMIRX_CTRL2, int_bits); +} + +void frhdmirx_ctrl(int channels, int src) +{ + int lane, lane_mask = 0, i; + + if (channels % 2) + lane = channels / 2 + 1; + else + lane = channels / 2; + + for (i = 0; i < lane; i++) + lane_mask |= (1 << i); + + audiobus_update_bits(EE_AUDIO_FRHDMIRX_CTRL0, + 0x1 << 30 | 0xf << 24 | 0x3 << 11, + 0x1 << 30 | /* chnum_sel */ + lane_mask << 24 | /* chnum_sel */ + 0x0 << 11 /* req_sel, Sync 4 spdifin by which */ + ); + + /* nonpcm2pcm_th */ + audiobus_write(EE_AUDIO_FRHDMIRX_CTRL1, 0xff << 20); + + /* enable irq bits */ + frhdmirx_enable_irq_bits(channels, src); +} diff --git a/sound/soc/amlogic/auge/frhdmirx_hw.h b/sound/soc/amlogic/auge/frhdmirx_hw.h new file mode 100644 index 000000000000..ce51e13242cd --- /dev/null +++ b/sound/soc/amlogic/auge/frhdmirx_hw.h @@ -0,0 +1,24 @@ +/* + * sound/soc/amlogic/auge/frhdmirx_hw.h + * + * Copyright (C) 2018 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ +#ifndef __FRHDMIRX_HW_H__ +#define __FRHDMIRX_HW_H__ + +extern void frhdmirx_enable(bool enable); +extern void frhdmirx_src_select(int src); +extern void frhdmirx_ctrl(int channels, int src); + +#endif diff --git a/sound/soc/amlogic/auge/g12a,clocks.c b/sound/soc/amlogic/auge/g12a,clocks.c index d16fa0879a19..66131cf05242 100644 --- a/sound/soc/amlogic/auge/g12a,clocks.c +++ b/sound/soc/amlogic/auge/g12a,clocks.c @@ -33,29 +33,29 @@ static const char *const audioclk_parent_names[] = { "i_slv_sclk_d", "i_slv_sclk_e", "i_slv_sclk_f", "i_slv_sclk_g", "i_slv_sclk_h", "i_slv_sclk_i", "i_slv_sclk_j"}; -CLOCK_GATE(audio_ddr_arb, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN), 0); -CLOCK_GATE(audio_pdm, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN), 1); -CLOCK_GATE(audio_tdmina, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN), 2); -CLOCK_GATE(audio_tdminb, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN), 3); -CLOCK_GATE(audio_tdminc, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN), 4); -CLOCK_GATE(audio_tdminlb, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN), 5); -CLOCK_GATE(audio_tdmouta, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN), 6); -CLOCK_GATE(audio_tdmoutb, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN), 7); -CLOCK_GATE(audio_tdmoutc, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN), 8); -CLOCK_GATE(audio_frddra, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN), 9); -CLOCK_GATE(audio_frddrb, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN), 10); -CLOCK_GATE(audio_frddrc, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN), 11); -CLOCK_GATE(audio_toddra, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN), 12); -CLOCK_GATE(audio_toddrb, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN), 13); -CLOCK_GATE(audio_toddrc, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN), 14); -CLOCK_GATE(audio_loopback, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN), 15); -CLOCK_GATE(audio_spdifin, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN), 16); -CLOCK_GATE(audio_spdifout, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN), 17); -CLOCK_GATE(audio_resample, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN), 18); -CLOCK_GATE(audio_power_detect, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN), 19); -CLOCK_GATE(audio_toram, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN), 20); -CLOCK_GATE(audio_spdifoutb, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN), 21); -CLOCK_GATE(audio_eqdrc, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN), 22); +CLOCK_GATE(audio_ddr_arb, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN0), 0); +CLOCK_GATE(audio_pdm, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN0), 1); +CLOCK_GATE(audio_tdmina, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN0), 2); +CLOCK_GATE(audio_tdminb, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN0), 3); +CLOCK_GATE(audio_tdminc, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN0), 4); +CLOCK_GATE(audio_tdminlb, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN0), 5); +CLOCK_GATE(audio_tdmouta, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN0), 6); +CLOCK_GATE(audio_tdmoutb, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN0), 7); +CLOCK_GATE(audio_tdmoutc, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN0), 8); +CLOCK_GATE(audio_frddra, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN0), 9); +CLOCK_GATE(audio_frddrb, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN0), 10); +CLOCK_GATE(audio_frddrc, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN0), 11); +CLOCK_GATE(audio_toddra, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN0), 12); +CLOCK_GATE(audio_toddrb, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN0), 13); +CLOCK_GATE(audio_toddrc, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN0), 14); +CLOCK_GATE(audio_loopback, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN0), 15); +CLOCK_GATE(audio_spdifin, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN0), 16); +CLOCK_GATE(audio_spdifout, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN0), 17); +CLOCK_GATE(audio_resample, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN0), 18); +CLOCK_GATE(audio_power_detect, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN0), 19); +CLOCK_GATE(audio_toram, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN0), 20); +CLOCK_GATE(audio_spdifoutb, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN0), 21); +CLOCK_GATE(audio_eqdrc, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN0), 22); static struct clk_gate *g12a_audio_clk_gates[] = { &audio_ddr_arb, @@ -129,29 +129,29 @@ static int g12a_clk_gates_init(struct clk **clks, void __iomem *iobase) } /* mclk_a */ -CLOCK_COM_MUX(mclk_a, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_A_CTRL), 0x7, 24); -CLOCK_COM_DIV(mclk_a, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_A_CTRL), 0, 16); -CLOCK_COM_GATE(mclk_a, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_A_CTRL), 31); +CLOCK_COM_MUX(mclk_a, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_A_CTRL(0)), 0x7, 24); +CLOCK_COM_DIV(mclk_a, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_A_CTRL(0)), 0, 16); +CLOCK_COM_GATE(mclk_a, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_A_CTRL(0)), 31); /* mclk_b */ -CLOCK_COM_MUX(mclk_b, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_B_CTRL), 0x7, 24); -CLOCK_COM_DIV(mclk_b, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_B_CTRL), 0, 16); -CLOCK_COM_GATE(mclk_b, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_B_CTRL), 31); +CLOCK_COM_MUX(mclk_b, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_B_CTRL(0)), 0x7, 24); +CLOCK_COM_DIV(mclk_b, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_B_CTRL(0)), 0, 16); +CLOCK_COM_GATE(mclk_b, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_B_CTRL(0)), 31); /* mclk_c */ -CLOCK_COM_MUX(mclk_c, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_C_CTRL), 0x7, 24); -CLOCK_COM_DIV(mclk_c, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_C_CTRL), 0, 16); -CLOCK_COM_GATE(mclk_c, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_C_CTRL), 31); +CLOCK_COM_MUX(mclk_c, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_C_CTRL(0)), 0x7, 24); +CLOCK_COM_DIV(mclk_c, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_C_CTRL(0)), 0, 16); +CLOCK_COM_GATE(mclk_c, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_C_CTRL(0)), 31); /* mclk_d */ -CLOCK_COM_MUX(mclk_d, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_D_CTRL), 0x7, 24); -CLOCK_COM_DIV(mclk_d, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_D_CTRL), 0, 16); -CLOCK_COM_GATE(mclk_d, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_D_CTRL), 31); +CLOCK_COM_MUX(mclk_d, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_D_CTRL(0)), 0x7, 24); +CLOCK_COM_DIV(mclk_d, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_D_CTRL(0)), 0, 16); +CLOCK_COM_GATE(mclk_d, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_D_CTRL(0)), 31); /* mclk_e */ -CLOCK_COM_MUX(mclk_e, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_E_CTRL), 0x7, 24); -CLOCK_COM_DIV(mclk_e, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_E_CTRL), 0, 16); -CLOCK_COM_GATE(mclk_e, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_E_CTRL), 31); +CLOCK_COM_MUX(mclk_e, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_E_CTRL(0)), 0x7, 24); +CLOCK_COM_DIV(mclk_e, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_E_CTRL(0)), 0, 16); +CLOCK_COM_GATE(mclk_e, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_E_CTRL(0)), 31); /* mclk_f */ -CLOCK_COM_MUX(mclk_f, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_F_CTRL), 0x7, 24); -CLOCK_COM_DIV(mclk_f, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_F_CTRL), 0, 16); -CLOCK_COM_GATE(mclk_f, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_F_CTRL), 31); +CLOCK_COM_MUX(mclk_f, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_F_CTRL(0)), 0x7, 24); +CLOCK_COM_DIV(mclk_f, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_F_CTRL(0)), 0, 16); +CLOCK_COM_GATE(mclk_f, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_F_CTRL(0)), 31); /* spdifin */ CLOCK_COM_MUX(spdifin, AUD_ADDR_OFFSET(EE_AUDIO_CLK_SPDIFIN_CTRL), 0x7, 24); CLOCK_COM_DIV(spdifin, AUD_ADDR_OFFSET(EE_AUDIO_CLK_SPDIFIN_CTRL), 0, 8); @@ -182,9 +182,9 @@ CLOCK_COM_MUX(locker_in, AUD_ADDR_OFFSET(EE_AUDIO_CLK_LOCKER_CTRL), 0xf, 8); CLOCK_COM_DIV(locker_in, AUD_ADDR_OFFSET(EE_AUDIO_CLK_LOCKER_CTRL), 0, 8); CLOCK_COM_GATE(locker_in, AUD_ADDR_OFFSET(EE_AUDIO_CLK_LOCKER_CTRL), 15); /* audio resample */ -CLOCK_COM_MUX(resample, AUD_ADDR_OFFSET(EE_AUDIO_CLK_RESAMPLE_CTRL), 0xf, 24); -CLOCK_COM_DIV(resample, AUD_ADDR_OFFSET(EE_AUDIO_CLK_RESAMPLE_CTRL), 0, 8); -CLOCK_COM_GATE(resample, AUD_ADDR_OFFSET(EE_AUDIO_CLK_RESAMPLE_CTRL), 31); +CLOCK_COM_MUX(resample, AUD_ADDR_OFFSET(EE_AUDIO_CLK_RESAMPLEA_CTRL), 0xf, 24); +CLOCK_COM_DIV(resample, AUD_ADDR_OFFSET(EE_AUDIO_CLK_RESAMPLEA_CTRL), 0, 8); +CLOCK_COM_GATE(resample, AUD_ADDR_OFFSET(EE_AUDIO_CLK_RESAMPLEA_CTRL), 31); static int g12a_clks_init(struct clk **clks, void __iomem *iobase) { diff --git a/sound/soc/amlogic/auge/iomap.c b/sound/soc/amlogic/auge/iomap.c index f1e3513a23ba..f3aa05e0482d 100644 --- a/sound/soc/amlogic/auge/iomap.c +++ b/sound/soc/amlogic/auge/iomap.c @@ -29,7 +29,7 @@ static void __iomem *aml_snd_reg_map[IO_MAX]; static int aml_snd_read(u32 base_type, unsigned int reg, unsigned int *val) { - if ((base_type >= IO_PDM_BUS) && (base_type < IO_MAX)) { + if (base_type < IO_MAX) { *val = readl((aml_snd_reg_map[base_type] + (reg << 2))); return 0; @@ -41,7 +41,7 @@ static int aml_snd_read(u32 base_type, unsigned int reg, unsigned int *val) static void aml_snd_write(u32 base_type, unsigned int reg, unsigned int val) { - if ((base_type >= IO_PDM_BUS) && (base_type < IO_MAX)) { + if (base_type < IO_MAX) { writel(val, (aml_snd_reg_map[base_type] + (reg << 2))); return; @@ -54,15 +54,16 @@ static void aml_snd_update_bits(u32 base_type, unsigned int reg, unsigned int mask, unsigned int val) { - if ((base_type >= IO_PDM_BUS) && (base_type < IO_MAX)) { + if (base_type < IO_MAX) { unsigned int tmp, orig; - aml_snd_read(base_type, reg, &orig); - tmp = orig & ~mask; - tmp |= val & mask; - aml_snd_write(base_type, reg, tmp); + if (aml_snd_read(base_type, reg, &orig) == 0) { + tmp = orig & ~mask; + tmp |= val & mask; + aml_snd_write(base_type, reg, tmp); - return; + return; + } } pr_err("write snd reg %x error\n", reg); diff --git a/sound/soc/amlogic/auge/pdm.c b/sound/soc/amlogic/auge/pdm.c index 7434b03f8401..e05c24ba8a7c 100644 --- a/sound/soc/amlogic/auge/pdm.c +++ b/sound/soc/amlogic/auge/pdm.c @@ -35,7 +35,7 @@ #include "regs.h" #include "ddr_mngr.h" -/*#define G12A_PTM*/ +/*#define __PTM_PDM_CLK__*/ static struct snd_pcm_hardware aml_pdm_hardware = { .info = @@ -727,8 +727,10 @@ static int aml_pdm_dai_set_sysclk(struct snd_soc_dai *cpu_dai, sysclk_srcpll_freq = clk_get_rate(p_pdm->sysclk_srcpll); dclk_srcpll_freq = clk_get_rate(p_pdm->dclk_srcpll); -#ifdef G12A_PTM - clk_set_rate(p_pdm->dclk_srcpll, 24576000); +#ifdef __PTM_PDM_CLK__ + clk_set_rate(p_pdm->clk_pdm_sysclk, 133333351); + clk_set_rate(p_pdm->dclk_srcpll, 24576000 * 15); /* 350m */ + clk_set_rate(p_pdm->clk_pdm_dclk, 3072000); #else clk_set_rate(p_pdm->clk_pdm_sysclk, 133333351); @@ -866,7 +868,13 @@ static const struct snd_soc_component_driver aml_pdm_component = { }; static struct pdm_chipinfo g12a_pdm_chipinfo = { - .mute_fn = true, + .mute_fn = true, + .truncate_data = false, +}; + +static struct pdm_chipinfo tl1_pdm_chipinfo = { + .mute_fn = true, + .truncate_data = true, }; static const struct of_device_id aml_pdm_device_id[] = { @@ -875,7 +883,11 @@ static const struct of_device_id aml_pdm_device_id[] = { }, { .compatible = "amlogic, g12a-snd-pdm", - .data = &g12a_pdm_chipinfo, + .data = &g12a_pdm_chipinfo, + }, + { + .compatible = "amlogic, tl1-snd-pdm", + .data = &tl1_pdm_chipinfo, }, {} }; diff --git a/sound/soc/amlogic/auge/pdm.h b/sound/soc/amlogic/auge/pdm.h index 72ff145965b0..60a0e1e46689 100644 --- a/sound/soc/amlogic/auge/pdm.h +++ b/sound/soc/amlogic/auge/pdm.h @@ -50,6 +50,8 @@ enum { struct pdm_chipinfo { /* pdm supports mute function */ bool mute_fn; + /* truncate invalid data when filter init */ + bool truncate_data; }; struct aml_pdm { diff --git a/sound/soc/amlogic/auge/regs.h b/sound/soc/amlogic/auge/regs.h index 5f844378cd2b..f3394be11099 100644 --- a/sound/soc/amlogic/auge/regs.h +++ b/sound/soc/amlogic/auge/regs.h @@ -18,515 +18,6 @@ #ifndef __AML_REGS_H_ #define __AML_REGS_H_ -/* - * PDM - Registers - * PDM - * - * BASE_ADR 32'hFF632000 - */ -#define PDM_CTRL 0x00 -#define PDM_HCIC_CTRL1 0x01 -#define PDM_HCIC_CTRL2 0x02 -#define PDM_F1_CTRL 0x03 -#define PDM_F2_CTRL 0x04 -#define PDM_F3_CTRL 0x05 -#define PDM_HPF_CTRL 0x06 -#define PDM_CHAN_CTRL 0x07 -#define PDM_CHAN_CTRL1 0x08 -#define PDM_COEFF_ADDR 0x09 -#define PDM_COEFF_DATA 0x0A -#define PDM_CLKG_CTRL 0x0B -#define PDM_STS 0x0C - - -/** - * AUDIO - Registers - * AUDIO CLOCK, TODDR, FRDDR, TDM, SPDIF, LOOPBACK, RESAMPLE, - * POWER DETECT, SECURITY - * - * BASE_ADR 32'hFF642000 - */ - -/** - * AXG chipset - */ -#define EE_AUDIO_CLK_GATE_EN 0x000 -#define EE_AUDIO_MCLK_A_CTRL 0x001 -#define EE_AUDIO_MCLK_B_CTRL 0x002 -#define EE_AUDIO_MCLK_C_CTRL 0x003 -#define EE_AUDIO_MCLK_D_CTRL 0x004 -#define EE_AUDIO_MCLK_E_CTRL 0x005 -#define EE_AUDIO_MCLK_F_CTRL 0x006 -#define EE_AUDIO_MST_A_SCLK_CTRL0 0x010 -#define EE_AUDIO_MST_A_SCLK_CTRL1 0x011 -#define EE_AUDIO_MST_B_SCLK_CTRL0 0x012 -#define EE_AUDIO_MST_B_SCLK_CTRL1 0x013 -#define EE_AUDIO_MST_C_SCLK_CTRL0 0x014 -#define EE_AUDIO_MST_C_SCLK_CTRL1 0x015 -#define EE_AUDIO_MST_D_SCLK_CTRL0 0x016 -#define EE_AUDIO_MST_D_SCLK_CTRL1 0x017 -#define EE_AUDIO_MST_E_SCLK_CTRL0 0x018 -#define EE_AUDIO_MST_E_SCLK_CTRL1 0x019 -#define EE_AUDIO_MST_F_SCLK_CTRL0 0x01a -#define EE_AUDIO_MST_F_SCLK_CTRL1 0x01b -#define EE_AUDIO_CLK_TDMIN_A_CTRL 0x020 -#define EE_AUDIO_CLK_TDMIN_B_CTRL 0x021 -#define EE_AUDIO_CLK_TDMIN_C_CTRL 0x022 -#define EE_AUDIO_CLK_TDMIN_LB_CTRL 0x023 -#define EE_AUDIO_CLK_TDMOUT_A_CTRL 0x024 -#define EE_AUDIO_CLK_TDMOUT_B_CTRL 0x025 -#define EE_AUDIO_CLK_TDMOUT_C_CTRL 0x026 -#define EE_AUDIO_CLK_SPDIFIN_CTRL 0x027 -#define EE_AUDIO_CLK_SPDIFOUT_CTRL 0x028 -#define EE_AUDIO_CLK_RESAMPLE_CTRL 0x029 -#define EE_AUDIO_CLK_LOCKER_CTRL 0x02a -#define EE_AUDIO_CLK_PDMIN_CTRL0 0x02b -#define EE_AUDIO_CLK_PDMIN_CTRL1 0x02c -#define EE_AUDIO_TODDR_A_CTRL0 0x040 -#define EE_AUDIO_TODDR_A_CTRL1 0x041 -#define EE_AUDIO_TODDR_A_START_ADDR 0x042 -#define EE_AUDIO_TODDR_A_FINISH_ADDR 0x043 -#define EE_AUDIO_TODDR_A_INT_ADDR 0x044 -#define EE_AUDIO_TODDR_A_STATUS1 0x045 -#define EE_AUDIO_TODDR_A_STATUS2 0x046 -#define EE_AUDIO_TODDR_A_START_ADDRB 0x047 -#define EE_AUDIO_TODDR_A_FINISH_ADDRB 0x048 -#define EE_AUDIO_TODDR_B_CTRL0 0x050 -#define EE_AUDIO_TODDR_B_CTRL1 0x051 -#define EE_AUDIO_TODDR_B_START_ADDR 0x052 -#define EE_AUDIO_TODDR_B_FINISH_ADDR 0x053 -#define EE_AUDIO_TODDR_B_INT_ADDR 0x054 -#define EE_AUDIO_TODDR_B_STATUS1 0x055 -#define EE_AUDIO_TODDR_B_STATUS2 0x056 -#define EE_AUDIO_TODDR_B_START_ADDRB 0x057 -#define EE_AUDIO_TODDR_B_FINISH_ADDRB 0x058 -#define EE_AUDIO_TODDR_C_CTRL0 0x060 -#define EE_AUDIO_TODDR_C_CTRL1 0x061 -#define EE_AUDIO_TODDR_C_START_ADDR 0x062 -#define EE_AUDIO_TODDR_C_FINISH_ADDR 0x063 -#define EE_AUDIO_TODDR_C_INT_ADDR 0x064 -#define EE_AUDIO_TODDR_C_STATUS1 0x065 -#define EE_AUDIO_TODDR_C_STATUS2 0x066 -#define EE_AUDIO_TODDR_C_START_ADDRB 0x067 -#define EE_AUDIO_TODDR_C_FINISH_ADDRB 0x068 -#define EE_AUDIO_FRDDR_A_CTRL0 0x070 -#define EE_AUDIO_FRDDR_A_CTRL1 0x071 -#define EE_AUDIO_FRDDR_A_START_ADDR 0x072 -#define EE_AUDIO_FRDDR_A_FINISH_ADDR 0x073 -#define EE_AUDIO_FRDDR_A_INT_ADDR 0x074 -#define EE_AUDIO_FRDDR_A_STATUS1 0x075 -#define EE_AUDIO_FRDDR_A_STATUS2 0x076 -#define EE_AUDIO_FRDDR_A_START_ADDRB 0x077 -#define EE_AUDIO_FRDDR_A_FINISH_ADDRB 0x078 -#define EE_AUDIO_FRDDR_B_CTRL0 0x080 -#define EE_AUDIO_FRDDR_B_CTRL1 0x081 -#define EE_AUDIO_FRDDR_B_START_ADDR 0x082 -#define EE_AUDIO_FRDDR_B_FINISH_ADDR 0x083 -#define EE_AUDIO_FRDDR_B_INT_ADDR 0x084 -#define EE_AUDIO_FRDDR_B_STATUS1 0x085 -#define EE_AUDIO_FRDDR_B_STATUS2 0x086 -#define EE_AUDIO_FRDDR_B_START_ADDRB 0x087 -#define EE_AUDIO_FRDDR_B_FINISH_ADDRB 0x088 -#define EE_AUDIO_FRDDR_C_CTRL0 0x090 -#define EE_AUDIO_FRDDR_C_CTRL1 0x091 -#define EE_AUDIO_FRDDR_C_START_ADDR 0x092 -#define EE_AUDIO_FRDDR_C_FINISH_ADDR 0x093 -#define EE_AUDIO_FRDDR_C_INT_ADDR 0x094 -#define EE_AUDIO_FRDDR_C_STATUS1 0x095 -#define EE_AUDIO_FRDDR_C_STATUS2 0x096 -#define EE_AUDIO_FRDDR_C_START_ADDRB 0x097 -#define EE_AUDIO_FRDDR_C_FINISH_ADDRB 0x098 -#define EE_AUDIO_ARB_CTRL 0x0a0 -#define EE_AUDIO_LB_CTRL0 0x0b0 -#define EE_AUDIO_LB_CTRL1 0x0b1 -#define EE_AUDIO_TDMIN_A_CTRL 0x0c0 -#define EE_AUDIO_TDMIN_A_SWAP 0x0c1 -#define EE_AUDIO_TDMIN_A_MASK0 0x0c2 -#define EE_AUDIO_TDMIN_A_MASK1 0x0c3 -#define EE_AUDIO_TDMIN_A_MASK2 0x0c4 -#define EE_AUDIO_TDMIN_A_MASK3 0x0c5 -#define EE_AUDIO_TDMIN_A_STAT 0x0c6 -#define EE_AUDIO_TDMIN_A_MUTE_VAL 0x0c7 -#define EE_AUDIO_TDMIN_A_MUTE0 0x0c8 -#define EE_AUDIO_TDMIN_A_MUTE1 0x0c9 -#define EE_AUDIO_TDMIN_A_MUTE2 0x0ca -#define EE_AUDIO_TDMIN_A_MUTE3 0x0cb -#define EE_AUDIO_TDMIN_B_CTRL 0x0d0 -#define EE_AUDIO_TDMIN_B_SWAP 0x0d1 -#define EE_AUDIO_TDMIN_B_MASK0 0x0d2 -#define EE_AUDIO_TDMIN_B_MASK1 0x0d3 -#define EE_AUDIO_TDMIN_B_MASK2 0x0d4 -#define EE_AUDIO_TDMIN_B_MASK3 0x0d5 -#define EE_AUDIO_TDMIN_B_STAT 0x0d6 -#define EE_AUDIO_TDMIN_B_MUTE_VAL 0x0d7 -#define EE_AUDIO_TDMIN_B_MUTE0 0x0d8 -#define EE_AUDIO_TDMIN_B_MUTE1 0x0d9 -#define EE_AUDIO_TDMIN_B_MUTE2 0x0da -#define EE_AUDIO_TDMIN_B_MUTE3 0x0db -#define EE_AUDIO_TDMIN_C_CTRL 0x0e0 -#define EE_AUDIO_TDMIN_C_SWAP 0x0e1 -#define EE_AUDIO_TDMIN_C_MASK0 0x0e2 -#define EE_AUDIO_TDMIN_C_MASK1 0x0e3 -#define EE_AUDIO_TDMIN_C_MASK2 0x0e4 -#define EE_AUDIO_TDMIN_C_MASK3 0x0e5 -#define EE_AUDIO_TDMIN_C_STAT 0x0e6 -#define EE_AUDIO_TDMIN_C_MUTE_VAL 0x0e7 -#define EE_AUDIO_TDMIN_C_MUTE0 0x0e8 -#define EE_AUDIO_TDMIN_C_MUTE1 0x0e9 -#define EE_AUDIO_TDMIN_C_MUTE2 0x0ea -#define EE_AUDIO_TDMIN_C_MUTE3 0x0eb -#define EE_AUDIO_TDMIN_LB_CTRL 0x0f0 -#define EE_AUDIO_TDMIN_LB_SWAP 0x0f1 -#define EE_AUDIO_TDMIN_LB_MASK0 0x0f2 -#define EE_AUDIO_TDMIN_LB_MASK1 0x0f3 -#define EE_AUDIO_TDMIN_LB_MASK2 0x0f4 -#define EE_AUDIO_TDMIN_LB_MASK3 0x0f5 -#define EE_AUDIO_TDMIN_LB_STAT 0x0f6 -#define EE_AUDIO_TDMIN_LB_MUTE_VAL 0x0f7 -#define EE_AUDIO_TDMIN_LB_MUTE0 0x0f8 -#define EE_AUDIO_TDMIN_LB_MUTE1 0x0f9 -#define EE_AUDIO_TDMIN_LB_MUTE2 0x0fa -#define EE_AUDIO_TDMIN_LB_MUTE3 0x0fb -#define EE_AUDIO_SPDIFIN_CTRL0 0x100 -#define EE_AUDIO_SPDIFIN_CTRL1 0x101 -#define EE_AUDIO_SPDIFIN_CTRL2 0x102 -#define EE_AUDIO_SPDIFIN_CTRL3 0x103 -#define EE_AUDIO_SPDIFIN_CTRL4 0x104 -#define EE_AUDIO_SPDIFIN_CTRL5 0x105 -#define EE_AUDIO_SPDIFIN_CTRL6 0x106 -#define EE_AUDIO_SPDIFIN_STAT0 0x107 -#define EE_AUDIO_SPDIFIN_STAT1 0x108 -#define EE_AUDIO_SPDIFIN_STAT2 0x109 -#define EE_AUDIO_SPDIFIN_MUTE_VAL 0x10a -#define EE_AUDIO_RESAMPLE_CTRL0 0x110 -#define EE_AUDIO_RESAMPLE_CTRL1 0x111 -#define EE_AUDIO_RESAMPLE_CTRL2 0x112 -#define EE_AUDIO_RESAMPLE_CTRL3 0x113 -#define EE_AUDIO_RESAMPLE_COEF0 0x114 -#define EE_AUDIO_RESAMPLE_COEF1 0x115 -#define EE_AUDIO_RESAMPLE_COEF2 0x116 -#define EE_AUDIO_RESAMPLE_COEF3 0x117 -#define EE_AUDIO_RESAMPLE_COEF4 0x118 -#define EE_AUDIO_RESAMPLE_STATUS1 0x119 -#define EE_AUDIO_SPDIFOUT_STAT 0x120 -#define EE_AUDIO_SPDIFOUT_GAIN0 0x121 -#define EE_AUDIO_SPDIFOUT_GAIN1 0x122 -#define EE_AUDIO_SPDIFOUT_CTRL0 0x123 -#define EE_AUDIO_SPDIFOUT_CTRL1 0x124 -#define EE_AUDIO_SPDIFOUT_PREAMB 0x125 -#define EE_AUDIO_SPDIFOUT_SWAP 0x126 -#define EE_AUDIO_SPDIFOUT_CHSTS0 0x127 -#define EE_AUDIO_SPDIFOUT_CHSTS1 0x128 -#define EE_AUDIO_SPDIFOUT_CHSTS2 0x129 -#define EE_AUDIO_SPDIFOUT_CHSTS3 0x12a -#define EE_AUDIO_SPDIFOUT_CHSTS4 0x12b -#define EE_AUDIO_SPDIFOUT_CHSTS5 0x12c -#define EE_AUDIO_SPDIFOUT_CHSTS6 0x12d -#define EE_AUDIO_SPDIFOUT_CHSTS7 0x12e -#define EE_AUDIO_SPDIFOUT_CHSTS8 0x12f -#define EE_AUDIO_SPDIFOUT_CHSTS9 0x130 -#define EE_AUDIO_SPDIFOUT_CHSTSA 0x131 -#define EE_AUDIO_SPDIFOUT_CHSTSB 0x132 -#define EE_AUDIO_SPDIFOUT_MUTE_VAL 0x133 -#define EE_AUDIO_TDMOUT_A_CTRL0 0x140 -#define EE_AUDIO_TDMOUT_A_CTRL1 0x141 -#define EE_AUDIO_TDMOUT_A_SWAP 0x142 -#define EE_AUDIO_TDMOUT_A_MASK0 0x143 -#define EE_AUDIO_TDMOUT_A_MASK1 0x144 -#define EE_AUDIO_TDMOUT_A_MASK2 0x145 -#define EE_AUDIO_TDMOUT_A_MASK3 0x146 -#define EE_AUDIO_TDMOUT_A_STAT 0x147 -#define EE_AUDIO_TDMOUT_A_GAIN0 0x148 -#define EE_AUDIO_TDMOUT_A_GAIN1 0x149 -#define EE_AUDIO_TDMOUT_A_MUTE_VAL 0x14a -#define EE_AUDIO_TDMOUT_A_MUTE0 0x14b -#define EE_AUDIO_TDMOUT_A_MUTE1 0x14c -#define EE_AUDIO_TDMOUT_A_MUTE2 0x14d -#define EE_AUDIO_TDMOUT_A_MUTE3 0x14e -#define EE_AUDIO_TDMOUT_A_MASK_VAL 0x14f -#define EE_AUDIO_TDMOUT_B_CTRL0 0x150 -#define EE_AUDIO_TDMOUT_B_CTRL1 0x151 -#define EE_AUDIO_TDMOUT_B_SWAP 0x152 -#define EE_AUDIO_TDMOUT_B_MASK0 0x153 -#define EE_AUDIO_TDMOUT_B_MASK1 0x154 -#define EE_AUDIO_TDMOUT_B_MASK2 0x155 -#define EE_AUDIO_TDMOUT_B_MASK3 0x156 -#define EE_AUDIO_TDMOUT_B_STAT 0x157 -#define EE_AUDIO_TDMOUT_B_GAIN0 0x158 -#define EE_AUDIO_TDMOUT_B_GAIN1 0x159 -#define EE_AUDIO_TDMOUT_B_MUTE_VAL 0x15a -#define EE_AUDIO_TDMOUT_B_MUTE0 0x15b -#define EE_AUDIO_TDMOUT_B_MUTE1 0x15c -#define EE_AUDIO_TDMOUT_B_MUTE2 0x15d -#define EE_AUDIO_TDMOUT_B_MUTE3 0x15e -#define EE_AUDIO_TDMOUT_B_MASK_VAL 0x15f -#define EE_AUDIO_TDMOUT_C_CTRL0 0x160 -#define EE_AUDIO_TDMOUT_C_CTRL1 0x161 -#define EE_AUDIO_TDMOUT_C_SWAP 0x162 -#define EE_AUDIO_TDMOUT_C_MASK0 0x163 -#define EE_AUDIO_TDMOUT_C_MASK1 0x164 -#define EE_AUDIO_TDMOUT_C_MASK2 0x165 -#define EE_AUDIO_TDMOUT_C_MASK3 0x166 -#define EE_AUDIO_TDMOUT_C_STAT 0x167 -#define EE_AUDIO_TDMOUT_C_GAIN0 0x168 -#define EE_AUDIO_TDMOUT_C_GAIN1 0x169 -#define EE_AUDIO_TDMOUT_C_MUTE_VAL 0x16a -#define EE_AUDIO_TDMOUT_C_MUTE0 0x16b -#define EE_AUDIO_TDMOUT_C_MUTE1 0x16c -#define EE_AUDIO_TDMOUT_C_MUTE2 0x16d -#define EE_AUDIO_TDMOUT_C_MUTE3 0x16e -#define EE_AUDIO_TDMOUT_C_MASK_VAL 0x16f -#define EE_AUDIO_POW_DET_CTRL0 0x180 -#define EE_AUDIO_POW_DET_TH_HI 0x181 -#define EE_AUDIO_POW_DET_TH_LO 0x182 -#define EE_AUDIO_POW_DET_VALUE 0x183 -#define EE_AUDIO_SECURITY_CTRL 0x193 - -/** - * AUDIO LOCKER - Registers - * - * BASE_ADR 32'hFF64A000 - */ -#define AUD_LOCK_EN 0x000 -#define AUD_LOCK_SW_RESET 0x001 -#define AUD_LOCK_SW_LATCH 0x002 -#define AUD_LOCK_HW_LATCH 0x003 -#define AUD_LOCK_REFCLK_SRC 0x004 -#define AUD_LOCK_REFCLK_LAT_INT 0x005 -#define AUD_LOCK_IMCLK_LAT_INT 0x006 -#define AUD_LOCK_OMCLK_LAT_INT 0x007 -#define AUD_LOCK_REFCLK_DS_INT 0x008 -#define AUD_LOCK_IMCLK_DS_INT 0x009 -#define AUD_LOCK_OMCLK_DS_INT 0x00a -#define AUD_LOCK_INT_CLR 0x00b -#define AUD_LOCK_GCLK_CTRL 0x00c -#define AUD_LOCK_INT_CTRL 0x00d -#define RO_REF2IMCLK_CNT_L 0x010 -#define RO_REF2IMCLK_CNT_H 0x011 -#define RO_REF2OMCLK_CNT_L 0x012 -#define RO_REF2OMCLK_CNT_H 0x013 -#define RO_IMCLK2REF_CNT_L 0x014 -#define RO_IMCLK2REF_CNT_H 0x015 -#define RO_OMCLK2REF_CNT_L 0x016 -#define RO_OMCLK2REF_CNT_H 0x017 -#define RO_REFCLK_PKG_CNT 0x018 -#define RO_IMCLK_PKG_CNT 0x019 -#define RO_OMCLK_PKG_CNT 0x01a -#define RO_AUD_LOCK_INT_STATUS 0x01b - -/** - * G12A chipset, base axg chipset, new registers - */ - -/* pdm mute value, mute channel ctrl in PDM_CTRL */ -#define PDM_MUTE_VALUE 0x00d - -/* clk pad */ -#define EE_AUDIO_MST_PAD_CTRL0 0x007 -#define EE_AUDIO_MST_PAD_CTRL1 0x008 -#define EE_AUDIO_SW_RESET 0x009 -/* spdifout_b clk*/ -#define EE_AUDIO_CLK_SPDIFOUT_B_CTRL 0x02d - -/* toddr, frddr int address */ -#define EE_AUDIO_TODDR_A_INIT_ADDR 0x049 -#define EE_AUDIO_TODDR_B_INIT_ADDR 0x059 -#define EE_AUDIO_TODDR_C_INIT_ADDR 0x069 -#define EE_AUDIO_FRDDR_A_INIT_ADDR 0x079 -#define EE_AUDIO_FRDDR_B_INIT_ADDR 0x089 -#define EE_AUDIO_FRDDR_C_INIT_ADDR 0x099 -/* spdif_b registers */ -#define EE_AUDIO_SPDIFOUT_B_STAT 0x1a0 -#define EE_AUDIO_SPDIFOUT_B_GAIN0 0x1a1 -#define EE_AUDIO_SPDIFOUT_B_GAIN1 0x1a2 -#define EE_AUDIO_SPDIFOUT_B_CTRL0 0x1a3 -#define EE_AUDIO_SPDIFOUT_B_CTRL1 0x1a4 -#define EE_AUDIO_SPDIFOUT_B_PREAMB 0x1a5 -#define EE_AUDIO_SPDIFOUT_B_SWAP 0x1a6 -#define EE_AUDIO_SPDIFOUT_B_CHSTS0 0x1a7 -#define EE_AUDIO_SPDIFOUT_B_CHSTS1 0x1a8 -#define EE_AUDIO_SPDIFOUT_B_CHSTS2 0x1a9 -#define EE_AUDIO_SPDIFOUT_B_CHSTS3 0x1aa -#define EE_AUDIO_SPDIFOUT_B_CHSTS4 0x1ab -#define EE_AUDIO_SPDIFOUT_B_CHSTS5 0x1ac -#define EE_AUDIO_SPDIFOUT_B_CHSTS6 0x1ad -#define EE_AUDIO_SPDIFOUT_B_CHSTS7 0x1ae -#define EE_AUDIO_SPDIFOUT_B_CHSTS8 0x1af -#define EE_AUDIO_SPDIFOUT_B_CHSTS9 0x1b0 -#define EE_AUDIO_SPDIFOUT_B_CHSTSA 0x1b1 -#define EE_AUDIO_SPDIFOUT_B_CHSTSB 0x1b2 -#define EE_AUDIO_SPDIFOUT_B_MUTE_VAL 0x1b3 - -/* data id */ -#define EE_AUDIO_DAT_ID0 0x0b2 -#define EE_AUDIO_DAT_ID1 0x0b3 -/* lb id */ -#define EE_AUDIO_LB_ID0 0x0b4 -#define EE_AUDIO_LB_ID1 0x0b5 -#define EE_AUDIO_LB_STS 0x0b6 - -/* TORAM Registers */ -#define EE_AUDIO_TORAM_CTRL0 0x1c0 -#define EE_AUDIO_TORAM_CTRL1 0x1c1 -#define EE_AUDIO_TORAM_START_ADDR 0x1c2 -#define EE_AUDIO_TORAM_FINISH_ADDR 0x1c3 -#define EE_AUDIO_TORAM_INT_ADDR 0x1c4 -#define EE_AUDIO_TORAM_STATUS1 0x1c5 -#define EE_AUDIO_TORAM_STATUS2 0x1c6 -#define EE_AUDIO_TORAM_INIT_ADDR 0x1c7 -/* TOACODEC Registers */ -#define EE_AUDIO_TOACODEC_CTRL0 0x1d0 -/* TOHDMITX Registers */ -#define EE_AUDIO_TOHDMITX_CTRL0 0x1d1 - -/* acodec reset */ -#define EE_RESET1 0x002 - -/* EQ DRC - * check BASE_ADR according to chipset - */ -#define AED_EQ_CH1_COEF00 0x00 -#define AED_EQ_CH1_COEF01 0x01 -#define AED_EQ_CH1_COEF02 0x02 -#define AED_EQ_CH1_COEF03 0x03 -#define AED_EQ_CH1_COEF04 0x04 -#define AED_EQ_CH1_COEF10 0x05 -#define AED_EQ_CH1_COEF11 0x06 -#define AED_EQ_CH1_COEF12 0x07 -#define AED_EQ_CH1_COEF13 0x08 -#define AED_EQ_CH1_COEF14 0x09 -#define AED_EQ_CH1_COEF20 0x0a -#define AED_EQ_CH1_COEF21 0x0b -#define AED_EQ_CH1_COEF22 0x0c -#define AED_EQ_CH1_COEF23 0x0d -#define AED_EQ_CH1_COEF24 0x0e -#define AED_EQ_CH1_COEF30 0x0f -#define AED_EQ_CH1_COEF31 0x10 -#define AED_EQ_CH1_COEF32 0x11 -#define AED_EQ_CH1_COEF33 0x12 -#define AED_EQ_CH1_COEF34 0x13 -#define AED_EQ_CH1_COEF40 0x14 -#define AED_EQ_CH1_COEF41 0x15 -#define AED_EQ_CH1_COEF42 0x16 -#define AED_EQ_CH1_COEF43 0x17 -#define AED_EQ_CH1_COEF44 0x18 -#define AED_EQ_CH1_COEF50 0x19 -#define AED_EQ_CH1_COEF51 0x1a -#define AED_EQ_CH1_COEF52 0x1b -#define AED_EQ_CH1_COEF53 0x1c -#define AED_EQ_CH1_COEF54 0x1d -#define AED_EQ_CH1_COEF60 0x1e -#define AED_EQ_CH1_COEF61 0x1f -#define AED_EQ_CH1_COEF62 0x20 -#define AED_EQ_CH1_COEF63 0x21 -#define AED_EQ_CH1_COEF64 0x22 -#define AED_EQ_CH1_COEF70 0x23 -#define AED_EQ_CH1_COEF71 0x24 -#define AED_EQ_CH1_COEF72 0x25 -#define AED_EQ_CH1_COEF73 0x26 -#define AED_EQ_CH1_COEF74 0x27 -#define AED_EQ_CH1_COEF80 0x28 -#define AED_EQ_CH1_COEF81 0x29 -#define AED_EQ_CH1_COEF82 0x2a -#define AED_EQ_CH1_COEF83 0x2b -#define AED_EQ_CH1_COEF84 0x2c -#define AED_EQ_CH1_COEF90 0x2d -#define AED_EQ_CH1_COEF91 0x2e -#define AED_EQ_CH1_COEF92 0x2f -#define AED_EQ_CH1_COEF93 0x30 -#define AED_EQ_CH1_COEF94 0x31 -#define AED_EQ_CH2_COEF00 0x32 -#define AED_EQ_CH2_COEF01 0x33 -#define AED_EQ_CH2_COEF02 0x34 -#define AED_EQ_CH2_COEF03 0x35 -#define AED_EQ_CH2_COEF04 0x36 -#define AED_EQ_CH2_COEF10 0x37 -#define AED_EQ_CH2_COEF11 0x38 -#define AED_EQ_CH2_COEF12 0x39 -#define AED_EQ_CH2_COEF13 0x3a -#define AED_EQ_CH2_COEF14 0x3b -#define AED_EQ_CH2_COEF20 0x3c -#define AED_EQ_CH2_COEF21 0x3d -#define AED_EQ_CH2_COEF22 0x3e -#define AED_EQ_CH2_COEF23 0x3f -#define AED_EQ_CH2_COEF24 0x40 -#define AED_EQ_CH2_COEF30 0x41 -#define AED_EQ_CH2_COEF31 0x42 -#define AED_EQ_CH2_COEF32 0x43 -#define AED_EQ_CH2_COEF33 0x44 -#define AED_EQ_CH2_COEF34 0x45 -#define AED_EQ_CH2_COEF40 0x46 -#define AED_EQ_CH2_COEF41 0x47 -#define AED_EQ_CH2_COEF42 0x48 -#define AED_EQ_CH2_COEF43 0x49 -#define AED_EQ_CH2_COEF44 0x4a -#define AED_EQ_CH2_COEF50 0x4b -#define AED_EQ_CH2_COEF51 0x4c -#define AED_EQ_CH2_COEF52 0x4d -#define AED_EQ_CH2_COEF53 0x4e -#define AED_EQ_CH2_COEF54 0x4f -#define AED_EQ_CH2_COEF60 0x50 -#define AED_EQ_CH2_COEF61 0x51 -#define AED_EQ_CH2_COEF62 0x52 -#define AED_EQ_CH2_COEF63 0x53 -#define AED_EQ_CH2_COEF64 0x54 -#define AED_EQ_CH2_COEF70 0x55 -#define AED_EQ_CH2_COEF71 0x56 -#define AED_EQ_CH2_COEF72 0x57 -#define AED_EQ_CH2_COEF73 0x58 -#define AED_EQ_CH2_COEF74 0x59 -#define AED_EQ_CH2_COEF80 0x5a -#define AED_EQ_CH2_COEF81 0x5b -#define AED_EQ_CH2_COEF82 0x5c -#define AED_EQ_CH2_COEF83 0x5d -#define AED_EQ_CH2_COEF84 0x5e -#define AED_EQ_CH2_COEF90 0x5f -#define AED_EQ_CH2_COEF91 0x60 -#define AED_EQ_CH2_COEF92 0x61 -#define AED_EQ_CH2_COEF93 0x62 -#define AED_EQ_CH2_COEF94 0x63 -#define AED_EQ_EN 0x64 -#define AED_EQ_VOLUME 0x65 -#define AED_EQ_VOLUME_SLEW_CNT 0x66 -#define AED_MUTE 0x67 -#define AED_DRC_EN 0x68 -#define AED_DRC_AE 0x69 -#define AED_DRC_AA 0x6a -#define AED_DRC_AD 0x6b -#define AED_DRC_AE_1M 0x6c -#define AED_DRC_AA_1M 0x6d -#define AED_DRC_AD_1M 0x6e -#define AED_DRC_OFFSET0 0x6f -#define AED_DRC_OFFSET1 0x70 -#define AED_DRC_THD0 0x71 -#define AED_DRC_THD1 0x72 -#define AED_DRC_K0 0x73 -#define AED_DRC_K1 0x74 -#define AED_CLIP_THD 0x75 -#define AED_NG_THD0 0x76 -#define AED_NG_THD1 0x77 -#define AED_NG_CNT_THD 0x78 -#define AED_NG_CTL 0x79 -#define AED_ED_CTL 0x7a -#define AED_DEBUG0 0x7b -#define AED_DEBUG1 0x7c -#define AED_DEBUG2 0x7d -#define AED_DEBUG3 0x7e -#define AED_DEBUG4 0x7f -#define AED_DEBUG5 0x80 -#define AED_DEBUG6 0x81 -#define AED_DRC_AA_H 0x82 -#define AED_DRC_AD_H 0x83 -#define AED_DRC_AA_1M_H 0x84 -#define AED_DRC_AD_1M_H 0x85 -#define AED_NG_CNT 0x86 -#define AED_NG_STEP 0x87 -#define AED_TOP_CTL 0x88 -#define AED_TOP_REQ_CTL 0x89 - - -#define AUD_ADDR_OFFSET(addr) ((addr) << 2) - enum clk_sel { MASTER_A, MASTER_B, @@ -546,4 +37,804 @@ enum clk_sel { SLAVE_J }; +#define AUD_ADDR_OFFSET(addr) ((addr) << 2) + +/* + * PDM - Registers + */ +#define PDM_CTRL 0x00 +#define PDM_HCIC_CTRL1 0x01 +#define PDM_HCIC_CTRL2 0x02 +#define PDM_F1_CTRL 0x03 +#define PDM_F2_CTRL 0x04 +#define PDM_F3_CTRL 0x05 +#define PDM_HPF_CTRL 0x06 +#define PDM_CHAN_CTRL 0x07 +#define PDM_CHAN_CTRL1 0x08 +#define PDM_COEFF_ADDR 0x09 +#define PDM_COEFF_DATA 0x0A +#define PDM_CLKG_CTRL 0x0B +#define PDM_STS 0x0C +#define PDM_MUTE_VALUE 0x0D +#define PDM_MASK_NUM 0x0E + +/* + * AUDIO CLOCK, MST PAD, + */ +#define EE_AUDIO_CLK_GATE_EN0 0x000 +#define EE_AUDIO_CLK_GATE_EN1 0x001 +#define EE_AUDIO_MCLK_A_CTRL(offset) (0x001 + offset) +#define EE_AUDIO_MCLK_B_CTRL(offset) (0x002 + offset) +#define EE_AUDIO_MCLK_C_CTRL(offset) (0x003 + offset) +#define EE_AUDIO_MCLK_D_CTRL(offset) (0x004 + offset) +#define EE_AUDIO_MCLK_E_CTRL(offset) (0x005 + offset) +#define EE_AUDIO_MCLK_F_CTRL(offset) (0x006 + offset) +#define EE_AUDIO_MST_PAD_CTRL0(offset) (0x007 + offset) +#define EE_AUDIO_MST_PAD_CTRL1(offset) (0x008 + offset) +#define EE_AUDIO_SW_RESET0(offset) (0x009 + offset) +#define EE_AUDIO_SW_RESET1 0x00b +#define EE_AUDIO_CLK81_CTRL 0x00c +#define EE_AUDIO_CLK81_EN 0x00d + + +#define EE_AUDIO_MST_A_SCLK_CTRL0 0x010 +#define EE_AUDIO_MST_A_SCLK_CTRL1 0x011 +#define EE_AUDIO_MST_B_SCLK_CTRL0 0x012 +#define EE_AUDIO_MST_B_SCLK_CTRL1 0x013 +#define EE_AUDIO_MST_C_SCLK_CTRL0 0x014 +#define EE_AUDIO_MST_C_SCLK_CTRL1 0x015 +#define EE_AUDIO_MST_D_SCLK_CTRL0 0x016 +#define EE_AUDIO_MST_D_SCLK_CTRL1 0x017 +#define EE_AUDIO_MST_E_SCLK_CTRL0 0x018 +#define EE_AUDIO_MST_E_SCLK_CTRL1 0x019 +#define EE_AUDIO_MST_F_SCLK_CTRL0 0x01a +#define EE_AUDIO_MST_F_SCLK_CTRL1 0x01b + +#define EE_AUDIO_CLK_TDMIN_A_CTRL 0x020 +#define EE_AUDIO_CLK_TDMIN_B_CTRL 0x021 +#define EE_AUDIO_CLK_TDMIN_C_CTRL 0x022 +#define EE_AUDIO_CLK_TDMIN_LB_CTRL 0x023 +#define EE_AUDIO_CLK_TDMOUT_A_CTRL 0x024 +#define EE_AUDIO_CLK_TDMOUT_B_CTRL 0x025 +#define EE_AUDIO_CLK_TDMOUT_C_CTRL 0x026 +#define EE_AUDIO_CLK_SPDIFIN_CTRL 0x027 +#define EE_AUDIO_CLK_SPDIFOUT_CTRL 0x028 +#define EE_AUDIO_CLK_RESAMPLEA_CTRL 0x029 +#define EE_AUDIO_CLK_LOCKER_CTRL 0x02a +#define EE_AUDIO_CLK_PDMIN_CTRL0 0x02b +#define EE_AUDIO_CLK_PDMIN_CTRL1 0x02c +#define EE_AUDIO_CLK_SPDIFOUT_B_CTRL 0x02d +#define EE_AUDIO_CLK_RESAMPLEB_CTRL 0x02e +#define EE_AUDIO_CLK_SPDIFIN_LB_CTRL 0x02f +#define EE_AUDIO_CLK_EQDRC_CTRL0 0x030 +#define EE_AUDIO_VAD_CLK_CTRL 0x031 + +/* + * AUDIO TODDR + */ +#define EE_AUDIO_TODDR_A_CTRL0 0x040 +#define EE_AUDIO_TODDR_A_CTRL1 0x041 +#define EE_AUDIO_TODDR_A_START_ADDR 0x042 +#define EE_AUDIO_TODDR_A_FINISH_ADDR 0x043 +#define EE_AUDIO_TODDR_A_INT_ADDR 0x044 +#define EE_AUDIO_TODDR_A_STATUS1 0x045 +#define EE_AUDIO_TODDR_A_STATUS2 0x046 +#define EE_AUDIO_TODDR_A_START_ADDRB 0x047 +#define EE_AUDIO_TODDR_A_FINISH_ADDRB 0x048 +#define EE_AUDIO_TODDR_A_INIT_ADDR 0x049 +#define EE_AUDIO_TODDR_A_CTRL2 0x04a + +#define EE_AUDIO_TODDR_B_CTRL0 0x050 +#define EE_AUDIO_TODDR_B_CTRL1 0x051 +#define EE_AUDIO_TODDR_B_START_ADDR 0x052 +#define EE_AUDIO_TODDR_B_FINISH_ADDR 0x053 +#define EE_AUDIO_TODDR_B_INT_ADDR 0x054 +#define EE_AUDIO_TODDR_B_STATUS1 0x055 +#define EE_AUDIO_TODDR_B_STATUS2 0x056 +#define EE_AUDIO_TODDR_B_START_ADDRB 0x057 +#define EE_AUDIO_TODDR_B_FINISH_ADDRB 0x058 +#define EE_AUDIO_TODDR_B_INIT_ADDR 0x059 +#define EE_AUDIO_TODDR_B_CTRL2 0x05a + +#define EE_AUDIO_TODDR_C_CTRL0 0x060 +#define EE_AUDIO_TODDR_C_CTRL1 0x061 +#define EE_AUDIO_TODDR_C_START_ADDR 0x062 +#define EE_AUDIO_TODDR_C_FINISH_ADDR 0x063 +#define EE_AUDIO_TODDR_C_INT_ADDR 0x064 +#define EE_AUDIO_TODDR_C_STATUS1 0x065 +#define EE_AUDIO_TODDR_C_STATUS2 0x066 +#define EE_AUDIO_TODDR_C_START_ADDRB 0x067 +#define EE_AUDIO_TODDR_C_FINISH_ADDRB 0x068 +#define EE_AUDIO_TODDR_C_INIT_ADDR 0x069 +#define EE_AUDIO_TODDR_C_CTRL2 0x06a + +/* + * AUDIO FRDDR + */ +#define EE_AUDIO_FRDDR_A_CTRL0 0x070 +#define EE_AUDIO_FRDDR_A_CTRL1 0x071 +#define EE_AUDIO_FRDDR_A_START_ADDR 0x072 +#define EE_AUDIO_FRDDR_A_FINISH_ADDR 0x073 +#define EE_AUDIO_FRDDR_A_INT_ADDR 0x074 +#define EE_AUDIO_FRDDR_A_STATUS1 0x075 +#define EE_AUDIO_FRDDR_A_STATUS2 0x076 +#define EE_AUDIO_FRDDR_A_START_ADDRB 0x077 +#define EE_AUDIO_FRDDR_A_FINISH_ADDRB 0x078 +#define EE_AUDIO_FRDDR_A_INIT_ADDR 0x079 +#define EE_AUDIO_FRDDR_A_CTRL2 0x07a + +#define EE_AUDIO_FRDDR_B_CTRL0 0x080 +#define EE_AUDIO_FRDDR_B_CTRL1 0x081 +#define EE_AUDIO_FRDDR_B_START_ADDR 0x082 +#define EE_AUDIO_FRDDR_B_FINISH_ADDR 0x083 +#define EE_AUDIO_FRDDR_B_INT_ADDR 0x084 +#define EE_AUDIO_FRDDR_B_STATUS1 0x085 +#define EE_AUDIO_FRDDR_B_STATUS2 0x086 +#define EE_AUDIO_FRDDR_B_START_ADDRB 0x087 +#define EE_AUDIO_FRDDR_B_FINISH_ADDRB 0x088 +#define EE_AUDIO_FRDDR_B_INIT_ADDR 0x089 +#define EE_AUDIO_FRDDR_B_CTRL2 0x08a + +#define EE_AUDIO_FRDDR_C_CTRL0 0x090 +#define EE_AUDIO_FRDDR_C_CTRL1 0x091 +#define EE_AUDIO_FRDDR_C_START_ADDR 0x092 +#define EE_AUDIO_FRDDR_C_FINISH_ADDR 0x093 +#define EE_AUDIO_FRDDR_C_INT_ADDR 0x094 +#define EE_AUDIO_FRDDR_C_STATUS1 0x095 +#define EE_AUDIO_FRDDR_C_STATUS2 0x096 +#define EE_AUDIO_FRDDR_C_START_ADDRB 0x097 +#define EE_AUDIO_FRDDR_C_FINISH_ADDRB 0x098 +#define EE_AUDIO_FRDDR_C_INIT_ADDR 0x099 +#define EE_AUDIO_FRDDR_C_CTRL2 0x09a + +/* + * AUDIO ARB, + */ +#define EE_AUDIO_ARB_CTRL 0x0a0 + +/* + * AUDIO TDM + */ +#define EE_AUDIO_LB_CTRL0 0x0b0 +#define EE_AUDIO_LB_CTRL1 0x0b1 +#define EE_AUDIO_DAT_ID0 0x0b2 +#define EE_AUDIO_DAT_ID1 0x0b3 +#define EE_AUDIO_LB_ID0 0x0b4 +#define EE_AUDIO_LB_ID1 0x0b5 +#define EE_AUDIO_LB_STS 0x0b6 + +#define EE_AUDIO_TDMIN_A_CTRL 0x0c0 +#define EE_AUDIO_TDMIN_A_SWAP 0x0c1 +#define EE_AUDIO_TDMIN_A_MASK0 0x0c2 +#define EE_AUDIO_TDMIN_A_MASK1 0x0c3 +#define EE_AUDIO_TDMIN_A_MASK2 0x0c4 +#define EE_AUDIO_TDMIN_A_MASK3 0x0c5 +#define EE_AUDIO_TDMIN_A_STAT 0x0c6 +#define EE_AUDIO_TDMIN_A_MUTE_VAL 0x0c7 +#define EE_AUDIO_TDMIN_A_MUTE0 0x0c8 +#define EE_AUDIO_TDMIN_A_MUTE1 0x0c9 +#define EE_AUDIO_TDMIN_A_MUTE2 0x0ca +#define EE_AUDIO_TDMIN_A_MUTE3 0x0cb + +#define EE_AUDIO_TDMIN_B_CTRL 0x0d0 +#define EE_AUDIO_TDMIN_B_SWAP 0x0d1 +#define EE_AUDIO_TDMIN_B_MASK0 0x0d2 +#define EE_AUDIO_TDMIN_B_MASK1 0x0d3 +#define EE_AUDIO_TDMIN_B_MASK2 0x0d4 +#define EE_AUDIO_TDMIN_B_MASK3 0x0d5 +#define EE_AUDIO_TDMIN_B_STAT 0x0d6 +#define EE_AUDIO_TDMIN_B_MUTE_VAL 0x0d7 +#define EE_AUDIO_TDMIN_B_MUTE0 0x0d8 +#define EE_AUDIO_TDMIN_B_MUTE1 0x0d9 +#define EE_AUDIO_TDMIN_B_MUTE2 0x0da +#define EE_AUDIO_TDMIN_B_MUTE3 0x0db + +#define EE_AUDIO_TDMIN_C_CTRL 0x0e0 +#define EE_AUDIO_TDMIN_C_SWAP 0x0e1 +#define EE_AUDIO_TDMIN_C_MASK0 0x0e2 +#define EE_AUDIO_TDMIN_C_MASK1 0x0e3 +#define EE_AUDIO_TDMIN_C_MASK2 0x0e4 +#define EE_AUDIO_TDMIN_C_MASK3 0x0e5 +#define EE_AUDIO_TDMIN_C_STAT 0x0e6 +#define EE_AUDIO_TDMIN_C_MUTE_VAL 0x0e7 +#define EE_AUDIO_TDMIN_C_MUTE0 0x0e8 +#define EE_AUDIO_TDMIN_C_MUTE1 0x0e9 +#define EE_AUDIO_TDMIN_C_MUTE2 0x0ea +#define EE_AUDIO_TDMIN_C_MUTE3 0x0eb + +#define EE_AUDIO_TDMIN_LB_CTRL 0x0f0 +#define EE_AUDIO_TDMIN_LB_SWAP 0x0f1 +#define EE_AUDIO_TDMIN_LB_MASK0 0x0f2 +#define EE_AUDIO_TDMIN_LB_MASK1 0x0f3 +#define EE_AUDIO_TDMIN_LB_MASK2 0x0f4 +#define EE_AUDIO_TDMIN_LB_MASK3 0x0f5 +#define EE_AUDIO_TDMIN_LB_STAT 0x0f6 +#define EE_AUDIO_TDMIN_LB_MUTE_VAL 0x0f7 +#define EE_AUDIO_TDMIN_LB_MUTE0 0x0f8 +#define EE_AUDIO_TDMIN_LB_MUTE1 0x0f9 +#define EE_AUDIO_TDMIN_LB_MUTE2 0x0fa +#define EE_AUDIO_TDMIN_LB_MUTE3 0x0fb + +/* + * AUDIO OUTPUT + */ +#define EE_AUDIO_SPDIFIN_CTRL0 0x100 +#define EE_AUDIO_SPDIFIN_CTRL1 0x101 +#define EE_AUDIO_SPDIFIN_CTRL2 0x102 +#define EE_AUDIO_SPDIFIN_CTRL3 0x103 +#define EE_AUDIO_SPDIFIN_CTRL4 0x104 +#define EE_AUDIO_SPDIFIN_CTRL5 0x105 +#define EE_AUDIO_SPDIFIN_CTRL6 0x106 +#define EE_AUDIO_SPDIFIN_STAT0 0x107 +#define EE_AUDIO_SPDIFIN_STAT1 0x108 +#define EE_AUDIO_SPDIFIN_STAT2 0x109 +#define EE_AUDIO_SPDIFIN_MUTE_VAL 0x10a + +#define EE_AUDIO_RESAMPLE_CTRL0 0x110 +#define EE_AUDIO_RESAMPLE_CTRL1 0x111 +#define EE_AUDIO_RESAMPLE_CTRL2 0x112 +#define EE_AUDIO_RESAMPLE_CTRL3 0x113 +#define EE_AUDIO_RESAMPLE_COEF0 0x114 +#define EE_AUDIO_RESAMPLE_COEF1 0x115 +#define EE_AUDIO_RESAMPLE_COEF2 0x116 +#define EE_AUDIO_RESAMPLE_COEF3 0x117 +#define EE_AUDIO_RESAMPLE_COEF4 0x118 +#define EE_AUDIO_RESAMPLE_STATUS1 0x119 + +#define EE_AUDIO_SPDIFOUT_STAT 0x120 +#define EE_AUDIO_SPDIFOUT_GAIN0 0x121 +#define EE_AUDIO_SPDIFOUT_GAIN1 0x122 +#define EE_AUDIO_SPDIFOUT_CTRL0 0x123 +#define EE_AUDIO_SPDIFOUT_CTRL1 0x124 +#define EE_AUDIO_SPDIFOUT_PREAMB 0x125 +#define EE_AUDIO_SPDIFOUT_SWAP 0x126 +#define EE_AUDIO_SPDIFOUT_CHSTS0 0x127 +#define EE_AUDIO_SPDIFOUT_CHSTS1 0x128 +#define EE_AUDIO_SPDIFOUT_CHSTS2 0x129 +#define EE_AUDIO_SPDIFOUT_CHSTS3 0x12a +#define EE_AUDIO_SPDIFOUT_CHSTS4 0x12b +#define EE_AUDIO_SPDIFOUT_CHSTS5 0x12c +#define EE_AUDIO_SPDIFOUT_CHSTS6 0x12d +#define EE_AUDIO_SPDIFOUT_CHSTS7 0x12e +#define EE_AUDIO_SPDIFOUT_CHSTS8 0x12f +#define EE_AUDIO_SPDIFOUT_CHSTS9 0x130 +#define EE_AUDIO_SPDIFOUT_CHSTSA 0x131 +#define EE_AUDIO_SPDIFOUT_CHSTSB 0x132 +#define EE_AUDIO_SPDIFOUT_MUTE_VAL 0x133 + +#define EE_AUDIO_TDMOUT_A_CTRL0 0x140 +#define EE_AUDIO_TDMOUT_A_CTRL1 0x141 +#define EE_AUDIO_TDMOUT_A_SWAP 0x142 +#define EE_AUDIO_TDMOUT_A_MASK0 0x143 +#define EE_AUDIO_TDMOUT_A_MASK1 0x144 +#define EE_AUDIO_TDMOUT_A_MASK2 0x145 +#define EE_AUDIO_TDMOUT_A_MASK3 0x146 +#define EE_AUDIO_TDMOUT_A_STAT 0x147 +#define EE_AUDIO_TDMOUT_A_GAIN0 0x148 +#define EE_AUDIO_TDMOUT_A_GAIN1 0x149 +#define EE_AUDIO_TDMOUT_A_MUTE_VAL 0x14a +#define EE_AUDIO_TDMOUT_A_MUTE0 0x14b +#define EE_AUDIO_TDMOUT_A_MUTE1 0x14c +#define EE_AUDIO_TDMOUT_A_MUTE2 0x14d +#define EE_AUDIO_TDMOUT_A_MUTE3 0x14e +#define EE_AUDIO_TDMOUT_A_MASK_VAL 0x14f + +#define EE_AUDIO_TDMOUT_B_CTRL0 0x150 +#define EE_AUDIO_TDMOUT_B_CTRL1 0x151 +#define EE_AUDIO_TDMOUT_B_SWAP 0x152 +#define EE_AUDIO_TDMOUT_B_MASK0 0x153 +#define EE_AUDIO_TDMOUT_B_MASK1 0x154 +#define EE_AUDIO_TDMOUT_B_MASK2 0x155 +#define EE_AUDIO_TDMOUT_B_MASK3 0x156 +#define EE_AUDIO_TDMOUT_B_STAT 0x157 +#define EE_AUDIO_TDMOUT_B_GAIN0 0x158 +#define EE_AUDIO_TDMOUT_B_GAIN1 0x159 +#define EE_AUDIO_TDMOUT_B_MUTE_VAL 0x15a +#define EE_AUDIO_TDMOUT_B_MUTE0 0x15b +#define EE_AUDIO_TDMOUT_B_MUTE1 0x15c +#define EE_AUDIO_TDMOUT_B_MUTE2 0x15d +#define EE_AUDIO_TDMOUT_B_MUTE3 0x15e +#define EE_AUDIO_TDMOUT_B_MASK_VAL 0x15f + +#define EE_AUDIO_TDMOUT_C_CTRL0 0x160 +#define EE_AUDIO_TDMOUT_C_CTRL1 0x161 +#define EE_AUDIO_TDMOUT_C_SWAP 0x162 +#define EE_AUDIO_TDMOUT_C_MASK0 0x163 +#define EE_AUDIO_TDMOUT_C_MASK1 0x164 +#define EE_AUDIO_TDMOUT_C_MASK2 0x165 +#define EE_AUDIO_TDMOUT_C_MASK3 0x166 +#define EE_AUDIO_TDMOUT_C_STAT 0x167 +#define EE_AUDIO_TDMOUT_C_GAIN0 0x168 +#define EE_AUDIO_TDMOUT_C_GAIN1 0x169 +#define EE_AUDIO_TDMOUT_C_MUTE_VAL 0x16a +#define EE_AUDIO_TDMOUT_C_MUTE0 0x16b +#define EE_AUDIO_TDMOUT_C_MUTE1 0x16c +#define EE_AUDIO_TDMOUT_C_MUTE2 0x16d +#define EE_AUDIO_TDMOUT_C_MUTE3 0x16e +#define EE_AUDIO_TDMOUT_C_MASK_VAL 0x16f + +/* + * AUDIO POWER DETECT + */ +#define EE_AUDIO_POW_DET_CTRL0 0x180 +#define EE_AUDIO_POW_DET_TH_HI 0x181 +#define EE_AUDIO_POW_DET_TH_LO 0x182 +#define EE_AUDIO_POW_DET_VALUE 0x183 +#define EE_AUDIO_SECURITY_CTRL 0x193 + +/* + * AUDIO SPDIF_B + */ +#define EE_AUDIO_SPDIFOUT_B_STAT 0x1a0 +#define EE_AUDIO_SPDIFOUT_B_GAIN0 0x1a1 +#define EE_AUDIO_SPDIFOUT_B_GAIN1 0x1a2 +#define EE_AUDIO_SPDIFOUT_B_CTRL0 0x1a3 +#define EE_AUDIO_SPDIFOUT_B_CTRL1 0x1a4 +#define EE_AUDIO_SPDIFOUT_B_PREAMB 0x1a5 +#define EE_AUDIO_SPDIFOUT_B_SWAP 0x1a6 +#define EE_AUDIO_SPDIFOUT_B_CHSTS0 0x1a7 +#define EE_AUDIO_SPDIFOUT_B_CHSTS1 0x1a8 +#define EE_AUDIO_SPDIFOUT_B_CHSTS2 0x1a9 +#define EE_AUDIO_SPDIFOUT_B_CHSTS3 0x1aa +#define EE_AUDIO_SPDIFOUT_B_CHSTS4 0x1ab +#define EE_AUDIO_SPDIFOUT_B_CHSTS5 0x1ac +#define EE_AUDIO_SPDIFOUT_B_CHSTS6 0x1ad +#define EE_AUDIO_SPDIFOUT_B_CHSTS7 0x1ae +#define EE_AUDIO_SPDIFOUT_B_CHSTS8 0x1af +#define EE_AUDIO_SPDIFOUT_B_CHSTS9 0x1b0 +#define EE_AUDIO_SPDIFOUT_B_CHSTSA 0x1b1 +#define EE_AUDIO_SPDIFOUT_B_CHSTSB 0x1b2 +#define EE_AUDIO_SPDIFOUT_B_MUTE_VAL 0x1b3 + +/* + * AUDIO LOCKER + */ +#define EE_AUDIO_TORAM_CTRL0 0x1c0 +#define EE_AUDIO_TORAM_CTRL1 0x1c1 +#define EE_AUDIO_TORAM_START_ADDR 0x1c2 +#define EE_AUDIO_TORAM_FINISH_ADDR 0x1c3 +#define EE_AUDIO_TORAM_INT_ADDR 0x1c4 +#define EE_AUDIO_TORAM_STATUS1 0x1c5 +#define EE_AUDIO_TORAM_STATUS2 0x1c6 +#define EE_AUDIO_TORAM_INIT_ADDR 0x1c7 + +/* + * HIU, AUDIO CODEC RESET + */ +#define EE_RESET1 0x002 + +/* + * AUDIO MUX CONTROLS + */ +#define EE_AUDIO_TOACODEC_CTRL0 0x1d0 +#define EE_AUDIO_TOHDMITX_CTRL0 0x1d1 +#define EE_AUDIO_TOVAD_CTRL0 0x1d2 +#define EE_AUDIO_FRATV_CTRL0 0x1d3 + +#define EE_AUDIO_RESAMPLEB_CTRL0 0x1e0 +#define EE_AUDIO_RESAMPLEB_CTRL1 0x1e1 +#define EE_AUDIO_RESAMPLEB_CTRL2 0x1e2 +#define EE_AUDIO_RESAMPLEB_CTRL3 0x1e3 +#define EE_AUDIO_RESAMPLEB_COEF0 0x1e4 +#define EE_AUDIO_RESAMPLEB_COEF1 0x1e5 +#define EE_AUDIO_RESAMPLEB_COEF2 0x1e6 +#define EE_AUDIO_RESAMPLEB_COEF3 0x1e7 +#define EE_AUDIO_RESAMPLEB_COEF4 0x1e8 +#define EE_AUDIO_RESAMPLEB_STATUS1 0x1e9 + +#define EE_AUDIO_SPDIFIN_LB_CTRL0 0x1f0 +#define EE_AUDIO_SPDIFIN_LB_CTRL1 0x1f1 +#define EE_AUDIO_SPDIFIN_LB_CTRL6 0x1f6 +#define EE_AUDIO_SPDIFIN_LB_STAT0 0x1f7 +#define EE_AUDIO_SPDIFIN_LB_STAT1 0x1f8 +#define EE_AUDIO_SPDIFIN_LB_MUTE_VAL 0x1fa + +#define EE_AUDIO_FRHDMIRX_CTRL0 0x200 +#define EE_AUDIO_FRHDMIRX_CTRL1 0x201 +#define EE_AUDIO_FRHDMIRX_CTRL2 0x202 +#define EE_AUDIO_FRHDMIRX_CTRL3 0x203 +#define EE_AUDIO_FRHDMIRX_CTRL4 0x204 +#define EE_AUDIO_FRHDMIRX_CTRL5 0x205 +#define EE_AUDIO_FRHDMIRX_STAT0 0x20a +#define EE_AUDIO_FRHDMIRX_STAT1 0x20b + +#define EE_AUDIO_TODDR_D_CTRL0 0x210 +#define EE_AUDIO_TODDR_D_CTRL1 0x211 +#define EE_AUDIO_TODDR_D_START_ADDR 0x212 +#define EE_AUDIO_TODDR_D_FINISH_ADDR 0x213 +#define EE_AUDIO_TODDR_D_INT_ADDR 0x214 +#define EE_AUDIO_TODDR_D_STATUS1 0x215 +#define EE_AUDIO_TODDR_D_STATUS2 0x216 +#define EE_AUDIO_TODDR_D_START_ADDRB 0x217 +#define EE_AUDIO_TODDR_D_FINISH_ADDRB 0x218 +#define EE_AUDIO_TODDR_D_INIT_ADDR 0x219 +#define EE_AUDIO_TODDR_D_CTRL2 0x21a + +#define EE_AUDIO_FRDDR_D_CTRL0 0x220 +#define EE_AUDIO_FRDDR_D_CTRL1 0x221 +#define EE_AUDIO_FRDDR_D_START_ADDR 0x222 +#define EE_AUDIO_FRDDR_D_FINISH_ADDR 0x223 +#define EE_AUDIO_FRDDR_D_INT_ADDR 0x224 +#define EE_AUDIO_FRDDR_D_STATUS1 0x225 +#define EE_AUDIO_FRDDR_D_STATUS2 0x226 +#define EE_AUDIO_FRDDR_D_START_ADDRB 0x227 +#define EE_AUDIO_FRDDR_D_FINISH_ADDRB 0x228 +#define EE_AUDIO_FRDDR_D_INIT_ADDR 0x229 +#define EE_AUDIO_FRDDR_D_CTRL2 0x22a + +#define EE_AUDIO_LB_B_CTRL0 0x230 +#define EE_AUDIO_LB_B_CTRL1 0x231 +#define EE_AUDIO_LB_B_CTRL2 0x232 +#define EE_AUDIO_LB_B_CTRL3 0x233 +#define EE_AUDIO_LB_B_DAT_CH_ID0 0x234 +#define EE_AUDIO_LB_B_DAT_CH_ID1 0x235 +#define EE_AUDIO_LB_B_DAT_CH_ID2 0x236 +#define EE_AUDIO_LB_B_DAT_CH_ID3 0x237 +#define EE_AUDIO_LB_B_LB_CH_ID0 0x238 +#define EE_AUDIO_LB_B_LB_CH_ID1 0x239 +#define EE_AUDIO_LB_B_LB_CH_ID2 0x23a +#define EE_AUDIO_LB_B_LB_CH_ID3 0x23b +#define EE_AUDIO_LB_B_STS 0x23c + +/* + * AUDIO LOCKER + */ +#define AUD_LOCK_EN 0x000 +#define AUD_LOCK_SW_RESET 0x001 +#define AUD_LOCK_SW_LATCH 0x002 +#define AUD_LOCK_HW_LATCH 0x003 +#define AUD_LOCK_REFCLK_SRC 0x004 +#define AUD_LOCK_REFCLK_LAT_INT 0x005 +#define AUD_LOCK_IMCLK_LAT_INT 0x006 +#define AUD_LOCK_OMCLK_LAT_INT 0x007 +#define AUD_LOCK_REFCLK_DS_INT 0x008 +#define AUD_LOCK_IMCLK_DS_INT 0x009 +#define AUD_LOCK_OMCLK_DS_INT 0x00a +#define AUD_LOCK_INT_CLR 0x00b +#define AUD_LOCK_GCLK_CTRL 0x00c +#define AUD_LOCK_INT_CTRL 0x00d +#define RO_REF2IMCLK_CNT_L 0x010 +#define RO_REF2IMCLK_CNT_H 0x011 +#define RO_REF2OMCLK_CNT_L 0x012 +#define RO_REF2OMCLK_CNT_H 0x013 +#define RO_IMCLK2REF_CNT_L 0x014 +#define RO_IMCLK2REF_CNT_H 0x015 +#define RO_OMCLK2REF_CNT_L 0x016 +#define RO_OMCLK2REF_CNT_H 0x017 +#define RO_REFCLK_PKG_CNT 0x018 +#define RO_IMCLK_PKG_CNT 0x019 +#define RO_OMCLK_PKG_CNT 0x01a +#define RO_AUD_LOCK_INT_STATUS 0x01b + +/* + * EQ DRC, g12a, g12b + */ +#define AED_EQ_CH1_COEF00 0x00 +#define AED_EQ_CH1_COEF01 0x01 +#define AED_EQ_CH1_COEF02 0x02 +#define AED_EQ_CH1_COEF03 0x03 +#define AED_EQ_CH1_COEF04 0x04 +#define AED_EQ_CH1_COEF10 0x05 +#define AED_EQ_CH1_COEF11 0x06 +#define AED_EQ_CH1_COEF12 0x07 +#define AED_EQ_CH1_COEF13 0x08 +#define AED_EQ_CH1_COEF14 0x09 +#define AED_EQ_CH1_COEF20 0x0a +#define AED_EQ_CH1_COEF21 0x0b +#define AED_EQ_CH1_COEF22 0x0c +#define AED_EQ_CH1_COEF23 0x0d +#define AED_EQ_CH1_COEF24 0x0e +#define AED_EQ_CH1_COEF30 0x0f +#define AED_EQ_CH1_COEF31 0x10 +#define AED_EQ_CH1_COEF32 0x11 +#define AED_EQ_CH1_COEF33 0x12 +#define AED_EQ_CH1_COEF34 0x13 +#define AED_EQ_CH1_COEF40 0x14 +#define AED_EQ_CH1_COEF41 0x15 +#define AED_EQ_CH1_COEF42 0x16 +#define AED_EQ_CH1_COEF43 0x17 +#define AED_EQ_CH1_COEF44 0x18 +#define AED_EQ_CH1_COEF50 0x19 +#define AED_EQ_CH1_COEF51 0x1a +#define AED_EQ_CH1_COEF52 0x1b +#define AED_EQ_CH1_COEF53 0x1c +#define AED_EQ_CH1_COEF54 0x1d +#define AED_EQ_CH1_COEF60 0x1e +#define AED_EQ_CH1_COEF61 0x1f +#define AED_EQ_CH1_COEF62 0x20 +#define AED_EQ_CH1_COEF63 0x21 +#define AED_EQ_CH1_COEF64 0x22 +#define AED_EQ_CH1_COEF70 0x23 +#define AED_EQ_CH1_COEF71 0x24 +#define AED_EQ_CH1_COEF72 0x25 +#define AED_EQ_CH1_COEF73 0x26 +#define AED_EQ_CH1_COEF74 0x27 +#define AED_EQ_CH1_COEF80 0x28 +#define AED_EQ_CH1_COEF81 0x29 +#define AED_EQ_CH1_COEF82 0x2a +#define AED_EQ_CH1_COEF83 0x2b +#define AED_EQ_CH1_COEF84 0x2c +#define AED_EQ_CH1_COEF90 0x2d +#define AED_EQ_CH1_COEF91 0x2e +#define AED_EQ_CH1_COEF92 0x2f +#define AED_EQ_CH1_COEF93 0x30 +#define AED_EQ_CH1_COEF94 0x31 +#define AED_EQ_CH2_COEF00 0x32 +#define AED_EQ_CH2_COEF01 0x33 +#define AED_EQ_CH2_COEF02 0x34 +#define AED_EQ_CH2_COEF03 0x35 +#define AED_EQ_CH2_COEF04 0x36 +#define AED_EQ_CH2_COEF10 0x37 +#define AED_EQ_CH2_COEF11 0x38 +#define AED_EQ_CH2_COEF12 0x39 +#define AED_EQ_CH2_COEF13 0x3a +#define AED_EQ_CH2_COEF14 0x3b +#define AED_EQ_CH2_COEF20 0x3c +#define AED_EQ_CH2_COEF21 0x3d +#define AED_EQ_CH2_COEF22 0x3e +#define AED_EQ_CH2_COEF23 0x3f +#define AED_EQ_CH2_COEF24 0x40 +#define AED_EQ_CH2_COEF30 0x41 +#define AED_EQ_CH2_COEF31 0x42 +#define AED_EQ_CH2_COEF32 0x43 +#define AED_EQ_CH2_COEF33 0x44 +#define AED_EQ_CH2_COEF34 0x45 +#define AED_EQ_CH2_COEF40 0x46 +#define AED_EQ_CH2_COEF41 0x47 +#define AED_EQ_CH2_COEF42 0x48 +#define AED_EQ_CH2_COEF43 0x49 +#define AED_EQ_CH2_COEF44 0x4a +#define AED_EQ_CH2_COEF50 0x4b +#define AED_EQ_CH2_COEF51 0x4c +#define AED_EQ_CH2_COEF52 0x4d +#define AED_EQ_CH2_COEF53 0x4e +#define AED_EQ_CH2_COEF54 0x4f +#define AED_EQ_CH2_COEF60 0x50 +#define AED_EQ_CH2_COEF61 0x51 +#define AED_EQ_CH2_COEF62 0x52 +#define AED_EQ_CH2_COEF63 0x53 +#define AED_EQ_CH2_COEF64 0x54 +#define AED_EQ_CH2_COEF70 0x55 +#define AED_EQ_CH2_COEF71 0x56 +#define AED_EQ_CH2_COEF72 0x57 +#define AED_EQ_CH2_COEF73 0x58 +#define AED_EQ_CH2_COEF74 0x59 +#define AED_EQ_CH2_COEF80 0x5a +#define AED_EQ_CH2_COEF81 0x5b +#define AED_EQ_CH2_COEF82 0x5c +#define AED_EQ_CH2_COEF83 0x5d +#define AED_EQ_CH2_COEF84 0x5e +#define AED_EQ_CH2_COEF90 0x5f +#define AED_EQ_CH2_COEF91 0x60 +#define AED_EQ_CH2_COEF92 0x61 +#define AED_EQ_CH2_COEF93 0x62 +#define AED_EQ_CH2_COEF94 0x63 +#define AED_EQ_EN_G12X 0x64 +#define AED_EQ_VOLUME_G12X 0x65 +#define AED_EQ_VOLUME_SLEW_CNT_G12X 0x66 +#define AED_MUTE_G12X 0x67 +#define AED_DRC_EN 0x68 +#define AED_DRC_AE 0x69 +#define AED_DRC_AA 0x6a +#define AED_DRC_AD 0x6b +#define AED_DRC_AE_1M 0x6c +#define AED_DRC_AA_1M 0x6d +#define AED_DRC_AD_1M 0x6e +#define AED_DRC_OFFSET0 0x6f +#define AED_DRC_OFFSET1 0x70 +#define AED_DRC_THD0_G12X 0x71 +#define AED_DRC_THD1_G12X 0x72 +#define AED_DRC_K0_G12X 0x73 +#define AED_DRC_K1_G12X 0x74 +#define AED_CLIP_THD_G12X 0x75 +#define AED_NG_THD0 0x76 +#define AED_NG_THD1 0x77 +#define AED_NG_CNT_THD 0x78 +#define AED_NG_CTL 0x79 +#define AED_ED_CTL 0x7a +#define AED_DEBUG0 0x7b +#define AED_DEBUG1 0x7c +#define AED_DEBUG2 0x7d +#define AED_DEBUG3 0x7e +#define AED_DEBUG4 0x7f +#define AED_DEBUG5 0x80 +#define AED_DEBUG6 0x81 +#define AED_DRC_AA_H 0x82 +#define AED_DRC_AD_H 0x83 +#define AED_DRC_AA_1M_H 0x84 +#define AED_DRC_AD_1M_H 0x85 +#define AED_NG_CNT 0x86 +#define AED_NG_STEP 0x87 +/* + * EQ DRC, New ARCH, from tl1 + */ +#define AED_COEF_RAM_CNTL 0x00 +#define AED_COEF_RAM_DATA 0x01 +#define AED_EQ_EN 0x02 +#define AED_EQ_TAP_CNTL 0x03 +#define AED_EQ_VOLUME 0x04 +#define AED_EQ_VOLUME_SLEW_CNT 0x05 +#define AED_MUTE 0x06 +#define AED_DRC_CNTL 0x07 +#define AED_DRC_RMS_COEF0 0x08 +#define AED_DRC_RMS_COEF1 0x09 +#define AED_DRC_THD0 0x0a +#define AED_DRC_THD1 0x0b +#define AED_DRC_THD2 0x0c +#define AED_DRC_THD3 0x0d +#define AED_DRC_THD4 0x0e +#define AED_DRC_K0 0x0f +#define AED_DRC_K1 0x10 +#define AED_DRC_K2 0x11 +#define AED_DRC_K3 0x12 +#define AED_DRC_K4 0x13 +#define AED_DRC_K5 0x14 +#define AED_DRC_THD_OUT0 0x15 +#define AED_DRC_THD_OUT1 0x16 +#define AED_DRC_THD_OUT2 0x17 +#define AED_DRC_THD_OUT3 0x18 +#define AED_DRC_OFFSET 0x19 +#define AED_DRC_RELEASE_COEF00 0x1a +#define AED_DRC_RELEASE_COEF01 0x1b +#define AED_DRC_RELEASE_COEF10 0x1c +#define AED_DRC_RELEASE_COEF11 0x1d +#define AED_DRC_RELEASE_COEF20 0x1e +#define AED_DRC_RELEASE_COEF21 0x1f +#define AED_DRC_RELEASE_COEF30 0x20 +#define AED_DRC_RELEASE_COEF31 0x21 +#define AED_DRC_RELEASE_COEF40 0x22 +#define AED_DRC_RELEASE_COEF41 0x23 +#define AED_DRC_RELEASE_COEF50 0x24 +#define AED_DRC_RELEASE_COEF51 0x25 +#define AED_DRC_ATTACK_COEF00 0x26 +#define AED_DRC_ATTACK_COEF01 0x27 +#define AED_DRC_ATTACK_COEF10 0x28 +#define AED_DRC_ATTACK_COEF11 0x29 +#define AED_DRC_ATTACK_COEF20 0x2a +#define AED_DRC_ATTACK_COEF21 0x2b +#define AED_DRC_ATTACK_COEF30 0x2c +#define AED_DRC_ATTACK_COEF31 0x2d +#define AED_DRC_ATTACK_COEF40 0x2e +#define AED_DRC_ATTACK_COEF41 0x2f +#define AED_DRC_ATTACK_COEF50 0x30 +#define AED_DRC_ATTACK_COEF51 0x31 +#define AED_DRC_LOOPBACK_CNTL 0x32 +#define AED_MDRC_CNTL 0x33 +#define AED_MDRC_RMS_COEF00 0x34 +#define AED_MDRC_RMS_COEF01 0x35 +#define AED_MDRC_RELEASE_COEF00 0x36 +#define AED_MDRC_RELEASE_COEF01 0x37 +#define AED_MDRC_ATTACK_COEF00 0x38 +#define AED_MDRC_ATTACK_COEF01 0x39 +#define AED_MDRC_THD0 0x3a +#define AED_MDRC_K0 0x3b +#define AED_MDRC_LOW_GAIN 0x3c +#define AED_MDRC_OFFSET0 0x3d +#define AED_MDRC_RMS_COEF10 0x3e +#define AED_MDRC_RMS_COEF11 0x3f +#define AED_MDRC_RELEASE_COEF10 0x40 +#define AED_MDRC_RELEASE_COEF11 0x41 +#define AED_MDRC_ATTACK_COEF10 0x42 +#define AED_MDRC_ATTACK_COEF11 0x43 +#define AED_MDRC_THD1 0x44 +#define AED_MDRC_K1 0x45 +#define AED_MDRC_OFFSET1 0x46 +#define AED_MDRC_MID_GAIN 0x47 +#define AED_MDRC_RMS_COEF20 0x48 +#define AED_MDRC_RMS_COEF21 0x49 +#define AED_MDRC_RELEASE_COEF20 0x4a +#define AED_MDRC_RELEASE_COEF21 0x4b +#define AED_MDRC_ATTACK_COEF20 0x4c +#define AED_MDRC_ATTACK_COEF21 0x4d +#define AED_MDRC_THD2 0x4e +#define AED_MDRC_K2 0x4f +#define AED_MDRC_OFFSET2 0x50 +#define AED_MDRC_HIGH_GAIN 0x51 +#define AED_ED_CNTL 0x52 +#define AED_DC_EN 0x53 +#define AED_ND_LOW_THD 0x54 +#define AED_ND_HIGH_THD 0x55 +#define AED_ND_CNT_THD 0x56 +#define AED_ND_SUM_NUM 0x57 +#define AED_ND_CZ_NUM 0x58 +#define AED_ND_SUM_THD0 0x59 +#define AED_ND_SUM_THD1 0x5a +#define AED_ND_CZ_THD0 0x5b +#define AED_ND_CZ_THD1 0x5c +#define AED_ND_COND_CNTL 0x5d +#define AED_ND_RELEASE_COEF0 0x5e +#define AED_ND_RELEASE_COEF1 0x5f +#define AED_ND_ATTACK_COEF0 0x60 +#define AED_ND_ATTACK_COEF1 0x61 +#define AED_ND_CNTL 0x62 +#define AED_MIX0_LL 0x63 +#define AED_MIX0_RL 0x64 +#define AED_MIX0_LR 0x65 +#define AED_MIX0_RR 0x66 +#define AED_CLIP_THD 0x67 +#define AED_CH1_ND_SUM_OUT 0x68 +#define AED_CH2_ND_SUM_OUT 0x69 +#define AED_CH1_ND_CZ_OUT 0x6a +#define AED_CH2_ND_CZ_OUT 0x6b +#define AED_NOISE_STATUS 0x6c +#define AED_POW_CURRENT_S0 0x6d +#define AED_POW_CURRENT_S1 0x6e +#define AED_POW_CURRENT_S2 0x6f +#define AED_POW_OUT0 0x70 +#define AED_POW_OUT1 0x71 +#define AED_POW_OUT2 0x72 +#define AED_POW_ADJ_INDEX0 0x73 +#define AED_POW_ADJ_INDEX1 0x74 +#define AED_POW_ADJ_INDEX2 0x75 +#define AED_DRC_GAIN_INDEX0 0x76 +#define AED_DRC_GAIN_INDEX1 0x77 +#define AED_DRC_GAIN_INDEX2 0x78 +#define AED_CH1_VOLUME_STATE 0x79 +#define AED_CH2_VOLUME_STATE 0x7a +#define AED_CH1_VOLUME_GAIN 0x7b +#define AED_CH2_VOLUME_GAIN 0x7c +#define AED_FULL_POW_CURRENT 0x7d +#define AED_FULL_POW_OUT 0x7e +#define AED_FULL_POW_ADJ 0x7f +#define AED_FULL_DRC_GAIN 0x80 +#define AED_MASTER_VOLUME_STATE 0x81 +#define AED_MASTER_VOLUME_GAIN 0x82 + +#define AED_TOP_CTL 0x88 +#define AED_TOP_REQ_CTL 0x89 + +/* + * VAD, Voice activity detection + */ +#define VAD_TOP_CTRL0 0x000 +#define VAD_TOP_CTRL1 0x001 +#define VAD_TOP_CTRL2 0x002 +#define VAD_FIR_CTRL 0x003 +#define VAD_FIR_EMP 0x004 +#define VAD_FIR_COEF0 0x005 +#define VAD_FIR_COEF1 0x006 +#define VAD_FIR_COEF2 0x007 +#define VAD_FIR_COEF3 0x008 +#define VAD_FIR_COEF4 0x009 +#define VAD_FIR_COEF5 0x00a +#define VAD_FIR_COEF6 0x00b +#define VAD_FIR_COEF7 0x00c +#define VAD_FIR_COEF8 0x00d +#define VAD_FIR_COEF9 0x00e +#define VAD_FIR_COEF10 0x00f +#define VAD_FIR_COEF11 0x010 +#define VAD_FIR_COEF12 0x011 +#define VAD_FRAME_CTRL0 0x012 +#define VAD_FRAME_CTRL1 0x013 +#define VAD_FRAME_CTRL2 0x014 +#define VAD_CEP_CTRL0 0x015 +#define VAD_CEP_CTRL1 0x016 +#define VAD_CEP_CTRL2 0x017 +#define VAD_CEP_CTRL3 0x018 +#define VAD_CEP_CTRL4 0x019 +#define VAD_CEP_CTRL5 0x01a +#define VAD_DEC_CTRL 0x01b +#define VAD_TOP_STS0 0x01c +#define VAD_TOP_STS1 0x01d +#define VAD_TOP_STS2 0x01e +#define VAD_FIR_STS0 0x01f +#define VAD_FIR_STS1 0x020 +#define VAD_POW_STS0 0x021 +#define VAD_POW_STS1 0x022 +#define VAD_POW_STS2 0x023 +#define VAD_FFT_STS0 0x024 +#define VAD_FFT_STS1 0x025 +#define VAD_SPE_STS0 0x026 +#define VAD_SPE_STS1 0x027 +#define VAD_SPE_STS2 0x028 +#define VAD_SPE_STS3 0x029 +#define VAD_DEC_STS0 0x02a +#define VAD_DEC_STS1 0x02b +#define VAD_LUT_CTRL 0x02c +#define VAD_LUT_WR 0x02d +#define VAD_LUT_RD 0x02e +#define VAD_IN_SEL0 0x02f +#define VAD_IN_SEL1 0x030 +#define VAD_TO_DDR 0x031 + #endif diff --git a/sound/soc/amlogic/auge/spdif.c b/sound/soc/amlogic/auge/spdif.c index 792cfc9a732f..c88aa2938a44 100644 --- a/sound/soc/amlogic/auge/spdif.c +++ b/sound/soc/amlogic/auge/spdif.c @@ -46,7 +46,7 @@ #define SPDIF_B 1 /* Debug by PTM when bringup */ -/* #define G12A_PTM */ +/*#define __PTM_SPDIF_CLK__*/ /* for debug */ /*#define __SPDIFIN_INSERT_CHNUM__*/ @@ -1146,8 +1146,8 @@ static void aml_set_spdifclk(struct aml_spdif *p_spdif) } mpll_freq = p_spdif->sysclk_freq * mul; -#ifdef G12A_PTM - mpll_freq = p_spdif->sysclk_freq * 57; +#ifdef __PTM_SPDIF_CLK__ + mpll_freq = p_spdif->sysclk_freq * 58; #endif pr_info("\t finally sys freq:%d, mpll freq:%d\n", p_spdif->sysclk_freq, @@ -1179,7 +1179,7 @@ static int aml_dai_set_spdif_sysclk(struct snd_soc_dai *cpu_dai, freq, dir); - if (dir == SND_SOC_CLOCK_OUT) { + if (clk_id == 0) { struct aml_spdif *p_spdif = snd_soc_dai_get_drvdata(cpu_dai); p_spdif->sysclk_freq = freq; @@ -1360,18 +1360,40 @@ struct spdif_chipinfo g12a_spdif_b_chipinfo = { .eq_drc_en = true, }; +struct spdif_chipinfo tl1_spdif_a_chipinfo = { + .id = SPDIF_A, + .chnum_en = true, + .hold_start = true, + .eq_drc_en = true, +}; + +struct spdif_chipinfo tl1_spdif_b_chipinfo = { + .id = SPDIF_B, + .chnum_en = true, + .hold_start = true, + .eq_drc_en = true, +}; + static const struct of_device_id aml_spdif_device_id[] = { { .compatible = "amlogic, axg-snd-spdif", - .data = &axg_spdif_chipinfo, + .data = &axg_spdif_chipinfo, }, { .compatible = "amlogic, g12a-snd-spdif-a", - .data = &g12a_spdif_a_chipinfo, + .data = &g12a_spdif_a_chipinfo, }, { .compatible = "amlogic, g12a-snd-spdif-b", - .data = &g12a_spdif_b_chipinfo, + .data = &g12a_spdif_b_chipinfo, + }, + { + .compatible = "amlogic, tl1-snd-spdif-a", + .data = &tl1_spdif_a_chipinfo, + }, + { + .compatible = "amlogic, tl1-snd-spdif-b", + .data = &tl1_spdif_b_chipinfo, }, {}, }; diff --git a/sound/soc/amlogic/auge/spdif_hw.c b/sound/soc/amlogic/auge/spdif_hw.c index a58fff02159a..d34405628d24 100644 --- a/sound/soc/amlogic/auge/spdif_hw.c +++ b/sound/soc/amlogic/auge/spdif_hw.c @@ -24,7 +24,7 @@ #include /*#define G12A_PTM*/ -/*#define G12A_PTM_LB_INTERNAL*/ +/*#define __PTM_SPDIF_INTERNAL_LB__*/ unsigned int aml_spdif_ctrl_read(struct aml_audio_controller *actrl, int stream, int index) @@ -85,7 +85,7 @@ void aml_spdif_enable( } else { aml_audiobus_update_bits(actrl, EE_AUDIO_SPDIFIN_CTRL0, 1<<31, is_enable<<31); -#ifdef G12A_PTM_LB_INTERNAL +#ifdef __PTM_SPDIF_INTERNAL_LB__ if (index == 0) aml_audiobus_update_bits(actrl, EE_AUDIO_SPDIFIN_CTRL0, 0x3<<4, 0x1<<4); diff --git a/sound/soc/amlogic/auge/tdm.c b/sound/soc/amlogic/auge/tdm.c index c0908dfdde55..139a92fe8aeb 100644 --- a/sound/soc/amlogic/auge/tdm.c +++ b/sound/soc/amlogic/auge/tdm.c @@ -39,7 +39,7 @@ #include "ddr_mngr.h" #include "tdm_hw.h" -/*#define G12A_PTM*/ +/*#define __PTM_TDM_CLK__*/ #include "sharebuffer.h" @@ -485,6 +485,16 @@ static int aml_dai_tdm_prepare(struct snd_pcm_substream *substream, return -EINVAL; } + if (toddr_src_get() == FRHDMIRX) { + src = FRHDMIRX; + + tdm_update_slot_in(p_tdm->actrl, p_tdm->id, HDMIRX_I2S); + } + + pr_info("%s Expected toddr src:%s\n", + __func__, + toddr_src_get_str(src)); + fmt.type = toddr_type; fmt.msb = 31; fmt.lsb = lsb; @@ -806,11 +816,11 @@ static int aml_dai_set_tdm_sysclk(struct snd_soc_dai *cpu_dai, p_tdm->setting.sysclk = freq; -#ifdef G12A_PTM +#ifdef __PTM_TDM_CLK__ if (p_tdm->id == 0) ratio = 14; else if (p_tdm->id == 1) - ratio = 18; + ratio = 18 * 2; else if (p_tdm->id == 2) ratio = 20; #endif @@ -1059,23 +1069,23 @@ static struct snd_soc_dai_driver aml_tdm_dai[] = { }; static const struct snd_soc_component_driver aml_tdm_component = { - .name = DRV_NAME, + .name = DRV_NAME, }; struct tdm_chipinfo axg_tdma_chipinfo = { - .id = TDM_A, + .id = TDM_A, }; struct tdm_chipinfo axg_tdmb_chipinfo = { - .id = TDM_B, + .id = TDM_B, }; struct tdm_chipinfo axg_tdmc_chipinfo = { - .id = TDM_C, + .id = TDM_C, }; struct tdm_chipinfo g12a_tdma_chipinfo = { - .id = TDM_A, + .id = TDM_A, .sclk_ws_inv = true, .oe_fn = true, .clk_pad_ctl = true, @@ -1083,7 +1093,7 @@ struct tdm_chipinfo g12a_tdma_chipinfo = { }; struct tdm_chipinfo g12a_tdmb_chipinfo = { - .id = TDM_B, + .id = TDM_B, .sclk_ws_inv = true, .oe_fn = true, .clk_pad_ctl = true, @@ -1091,7 +1101,31 @@ struct tdm_chipinfo g12a_tdmb_chipinfo = { }; struct tdm_chipinfo g12a_tdmc_chipinfo = { - .id = TDM_C, + .id = TDM_C, + .sclk_ws_inv = true, + .oe_fn = true, + .clk_pad_ctl = true, + .same_src_fn = true, +}; + +struct tdm_chipinfo tl1_tdma_chipinfo = { + .id = TDM_A, + .sclk_ws_inv = true, + .oe_fn = true, + .clk_pad_ctl = true, + .same_src_fn = true, +}; + +struct tdm_chipinfo tl1_tdmb_chipinfo = { + .id = TDM_B, + .sclk_ws_inv = true, + .oe_fn = true, + .clk_pad_ctl = true, + .same_src_fn = true, +}; + +struct tdm_chipinfo tl1_tdmc_chipinfo = { + .id = TDM_C, .sclk_ws_inv = true, .oe_fn = true, .clk_pad_ctl = true, @@ -1101,27 +1135,39 @@ struct tdm_chipinfo g12a_tdmc_chipinfo = { static const struct of_device_id aml_tdm_device_id[] = { { .compatible = "amlogic, axg-snd-tdma", - .data = &axg_tdma_chipinfo, + .data = &axg_tdma_chipinfo, }, { .compatible = "amlogic, axg-snd-tdmb", - .data = &axg_tdmb_chipinfo, + .data = &axg_tdmb_chipinfo, }, { .compatible = "amlogic, axg-snd-tdmc", - .data = &axg_tdmc_chipinfo, + .data = &axg_tdmc_chipinfo, }, { .compatible = "amlogic, g12a-snd-tdma", - .data = &g12a_tdma_chipinfo, + .data = &g12a_tdma_chipinfo, }, { .compatible = "amlogic, g12a-snd-tdmb", - .data = &g12a_tdmb_chipinfo, + .data = &g12a_tdmb_chipinfo, }, { .compatible = "amlogic, g12a-snd-tdmc", - .data = &g12a_tdmc_chipinfo, + .data = &g12a_tdmc_chipinfo, + }, + { + .compatible = "amlogic, tl1-snd-tdma", + .data = &tl1_tdma_chipinfo, + }, + { + .compatible = "amlogic, tl1-snd-tdmb", + .data = &tl1_tdmb_chipinfo, + }, + { + .compatible = "amlogic, tl1-snd-tdmc", + .data = &tl1_tdmc_chipinfo, }, {}, }; diff --git a/sound/soc/amlogic/auge/tdm_hw.c b/sound/soc/amlogic/auge/tdm_hw.c index 7eb5482c4cf6..c720947b8c40 100644 --- a/sound/soc/amlogic/auge/tdm_hw.c +++ b/sound/soc/amlogic/auge/tdm_hw.c @@ -26,8 +26,8 @@ #define MST_CLK_INVERT_PH2_TDMOUT_BCLK (1 << 4) #define MST_CLK_INVERT_PH2_TDMOUT_FCLK (1 << 5) -/*#define G12A_PTM*/ /*#define G12A_PTM_LB_INTERNAL*/ +/*#define TL1_PTM_LB_INTERNAL*/ /* without audio handler, it should be improved */ void aml_tdm_enable( @@ -335,9 +335,7 @@ void aml_tdm_set_format( pr_debug("sclk_ph0 (pad) clk ctl set:%x\n", clkctl); /* clk ctrl: delay line and invert clk */ /*clkctl |= 0x88880000;*/ -#ifdef G12A_PTM - clkctl |= 0x77777700; -#endif + if (master_mode) { off_set = EE_AUDIO_MST_B_SCLK_CTRL1 - EE_AUDIO_MST_A_SCLK_CTRL1; reg_out = EE_AUDIO_MST_A_SCLK_CTRL1 + off_set * id; @@ -431,7 +429,7 @@ void aml_tdm_set_slot_in( offset = EE_AUDIO_TDMIN_B_CTRL - EE_AUDIO_TDMIN_A_CTRL; reg = EE_AUDIO_TDMIN_A_CTRL + offset * index; -#ifdef G12A_PTM_LB_INTERNAL +#if defined(G12A_PTM_LB_INTERNAL) if (index == 0) /*TODO: ptm, tdma dsp_a lb*/ aml_audiobus_update_bits(actrl, reg, 0xf<<20|0x1f, 6<<20|(slot_width-1)); @@ -439,11 +437,32 @@ void aml_tdm_set_slot_in( aml_audiobus_update_bits(actrl, reg, 0xf<<20|0x1f, 7<<20|(slot_width-1)); else +#elif defined(TL1_PTM_LB_INTERNAL) +if (index == 0) /*TODO: ptm, tdma dsp_a lb*/ + aml_audiobus_update_bits(actrl, reg, + 0xf<<20|0x1f, 13<<20|(slot_width-1)); +else if (index == 1) /*TODO: ptm, tdmb i2s lb*/ + aml_audiobus_update_bits(actrl, reg, + 0xf<<20|0x1f, 14<<20|(slot_width-1)); +else #endif aml_audiobus_update_bits(actrl, reg, 0xf << 20 | 0x1f, in_src << 20 | (slot_width-1)); } +void tdm_update_slot_in( + struct aml_audio_controller *actrl, + int index, int in_src) +{ + unsigned int reg, offset; + + offset = EE_AUDIO_TDMIN_B_CTRL - EE_AUDIO_TDMIN_A_CTRL; + reg = EE_AUDIO_TDMIN_A_CTRL + offset * index; + + aml_audiobus_update_bits(actrl, reg, + 0xf << 20, in_src << 20); +} + void aml_tdm_set_channel_mask( struct aml_audio_controller *actrl, int stream, int index, int lane, int mask) @@ -561,11 +580,11 @@ void aml_tdm_clk_pad_select( pr_err("unknown tdm mpad:%d\n", mpad); return; } - reg = EE_AUDIO_MST_PAD_CTRL0; + reg = EE_AUDIO_MST_PAD_CTRL0(0); aml_audiobus_update_bits(actrl, reg, mask_offset, val_offset); - reg = EE_AUDIO_MST_PAD_CTRL1; + reg = EE_AUDIO_MST_PAD_CTRL1(0); switch (tdm_index) { case 0: mask_offset = 0x7 << 16 | 0x7 << 0; diff --git a/sound/soc/amlogic/auge/tdm_hw.h b/sound/soc/amlogic/auge/tdm_hw.h index 896bdf2b5e1f..fc5bcabfecf9 100644 --- a/sound/soc/amlogic/auge/tdm_hw.h +++ b/sound/soc/amlogic/auge/tdm_hw.h @@ -21,6 +21,21 @@ #include "audio_io.h" #include "regs.h" +// TODO: fix me, now based by tl1 +enum tdmin_src { + PAD_TDMINA_DIN = 0, + PAD_TDMINB_DIN = 1, + PAD_TDMINC_DIN = 2, + PAD_TDMINA_D = 4, + PAD_TDMINB_D = 5, + PAD_TDMINC_D = 6, + HDMIRX_I2S = 7, + ACODEC_ADC = 8, + TDMOUTA = 13, + TDMOUTB = 14, + TDMOUTC = 15, +}; + struct pcm_setting { unsigned int pcm_mode; unsigned int sysclk; @@ -80,6 +95,10 @@ extern void aml_tdm_set_slot_in( struct aml_audio_controller *actrl, int index, int in_src, int slot_width); +extern void tdm_update_slot_in( + struct aml_audio_controller *actrl, + int index, int in_src); + extern void aml_tdm_set_channel_mask( struct aml_audio_controller *actrl, int stream, int index, int lanes, int mask); diff --git a/sound/soc/amlogic/auge/tl1,clocks.c b/sound/soc/amlogic/auge/tl1,clocks.c new file mode 100644 index 000000000000..c4e9817ff4d2 --- /dev/null +++ b/sound/soc/amlogic/auge/tl1,clocks.c @@ -0,0 +1,283 @@ +/* + * sound/soc/amlogic/auge/tl1,clocks.c + * + * Copyright (C) 2018 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ +#undef pr_fmt +#define pr_fmt(fmt) "tl1_clocks: " fmt + +#include + +#include "audio_clks.h" +#include "regs.h" + +static spinlock_t aclk_lock; + +static const char *const mclk_parent_names[] = {"mpll0", "mpll1", + "mpll2", "mpll3", "hifi_pll", "fclk_div3", "fclk_div4", "gp0_pll"}; + +static const char *const audioclk_parent_names[] = { + "mclk_a", "mclk_b", "mclk_c", "mclk_d", "mclk_e", + "mclk_f", "i_slv_sclk_a", "i_slv_sclk_b", "i_slv_sclk_c", + "i_slv_sclk_d", "i_slv_sclk_e", "i_slv_sclk_f", "i_slv_sclk_g", + "i_slv_sclk_h", "i_slv_sclk_i", "i_slv_sclk_j"}; + +CLOCK_GATE(audio_ddr_arb, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN0), 0); +CLOCK_GATE(audio_pdm, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN0), 1); +CLOCK_GATE(audio_tdmina, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN0), 2); +CLOCK_GATE(audio_tdminb, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN0), 3); +CLOCK_GATE(audio_tdminc, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN0), 4); +CLOCK_GATE(audio_tdminlb, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN0), 5); +CLOCK_GATE(audio_tdmouta, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN0), 6); +CLOCK_GATE(audio_tdmoutb, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN0), 7); +CLOCK_GATE(audio_tdmoutc, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN0), 8); +CLOCK_GATE(audio_frddra, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN0), 9); +CLOCK_GATE(audio_frddrb, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN0), 10); +CLOCK_GATE(audio_frddrc, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN0), 11); +CLOCK_GATE(audio_toddra, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN0), 12); +CLOCK_GATE(audio_toddrb, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN0), 13); +CLOCK_GATE(audio_toddrc, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN0), 14); +CLOCK_GATE(audio_loopbacka, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN0), 15); +CLOCK_GATE(audio_spdifin, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN0), 16); +CLOCK_GATE(audio_spdifout, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN0), 17); +CLOCK_GATE(audio_resamplea, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN0), 18); +CLOCK_GATE(audio_reserved0, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN0), 19); +CLOCK_GATE(audio_reserved1, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN0), 20); +CLOCK_GATE(audio_spdifoutb, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN0), 21); +CLOCK_GATE(audio_eqdrc, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN0), 22); +CLOCK_GATE(audio_resampleb, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN0), 26); +CLOCK_GATE(audio_tovad, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN0), 27); +CLOCK_GATE(audio_audiolocker, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN0), 28); +CLOCK_GATE(audio_spdifin_lb, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN0), 29); +CLOCK_GATE(audio_fratv, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN0), 30); +CLOCK_GATE(audio_frhdmirx, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN0), 31); + +CLOCK_GATE(audio_frddrd, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN1), 0); +CLOCK_GATE(audio_toddrd, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN1), 1); +CLOCK_GATE(audio_loopbackb, AUD_ADDR_OFFSET(EE_AUDIO_CLK_GATE_EN1), 2); + +static struct clk_gate *tl1_audio_clk_gates[] = { + &audio_ddr_arb, + &audio_pdm, + &audio_tdmina, + &audio_tdminb, + &audio_tdminc, + &audio_tdminlb, + &audio_tdmouta, + &audio_tdmoutb, + &audio_tdmoutc, + &audio_frddra, + &audio_frddrb, + &audio_frddrc, + &audio_toddra, + &audio_toddrb, + &audio_toddrc, + &audio_loopbacka, + &audio_spdifin, + &audio_spdifout, + &audio_resamplea, + &audio_reserved0, + &audio_reserved1, + &audio_spdifoutb, + &audio_eqdrc, + &audio_resampleb, + &audio_tovad, + &audio_audiolocker, + &audio_spdifin_lb, + &audio_fratv, + &audio_frhdmirx, + + &audio_frddrd, + &audio_toddrd, + &audio_loopbackb, +}; + +/* Array of all clocks provided by this provider */ +static struct clk_hw *tl1_audio_clk_hws[] = { + [CLKID_AUDIO_DDR_ARB] = &audio_ddr_arb.hw, + [CLKID_AUDIO_PDM] = &audio_pdm.hw, + [CLKID_AUDIO_TDMINA] = &audio_tdmina.hw, + [CLKID_AUDIO_TDMINB] = &audio_tdminb.hw, + [CLKID_AUDIO_TDMINC] = &audio_tdminc.hw, + [CLKID_AUDIO_TDMINLB] = &audio_tdminlb.hw, + [CLKID_AUDIO_TDMOUTA] = &audio_tdmouta.hw, + [CLKID_AUDIO_TDMOUTB] = &audio_tdmoutb.hw, + [CLKID_AUDIO_TDMOUTC] = &audio_tdmoutc.hw, + [CLKID_AUDIO_FRDDRA] = &audio_frddra.hw, + [CLKID_AUDIO_FRDDRB] = &audio_frddrb.hw, + [CLKID_AUDIO_FRDDRC] = &audio_frddrc.hw, + [CLKID_AUDIO_TODDRA] = &audio_toddra.hw, + [CLKID_AUDIO_TODDRB] = &audio_toddrb.hw, + [CLKID_AUDIO_TODDRC] = &audio_toddrc.hw, + [CLKID_AUDIO_LOOPBACKA] = &audio_loopbacka.hw, + [CLKID_AUDIO_SPDIFIN] = &audio_spdifin.hw, + [CLKID_AUDIO_SPDIFOUT] = &audio_spdifout.hw, + [CLKID_AUDIO_RESAMPLEA] = &audio_resamplea.hw, + [CLKID_AUDIO_RESERVED0] = &audio_reserved0.hw, + [CLKID_AUDIO_RESERVED1] = &audio_reserved1.hw, + [CLKID_AUDIO_SPDIFOUTB] = &audio_spdifoutb.hw, + [CLKID_AUDIO_EQDRC] = &audio_eqdrc.hw, + [CLKID_AUDIO_RESAMPLEB] = &audio_resampleb.hw, + [CLKID_AUDIO_TOVAD] = &audio_tovad.hw, + [CLKID_AUDIO_AUDIOLOCKER] = &audio_audiolocker.hw, + [CLKID_AUDIO_SPDIFIN_LB] = &audio_spdifin_lb.hw, + [CLKID_AUDIO_FRATV] = &audio_fratv.hw, + [CLKID_AUDIO_FRHDMIRX] = &audio_frhdmirx.hw, + [CLKID_AUDIO_FRDDRD] = &audio_frddrd.hw, + [CLKID_AUDIO_TODDRD] = &audio_toddrd.hw, + [CLKID_AUDIO_LOOPBACKB] = &audio_loopbackb.hw, +}; + +static int tl1_clk_gates_init(struct clk **clks, void __iomem *iobase) +{ + int clkid; + + if (ARRAY_SIZE(tl1_audio_clk_gates) != MCLK_BASE) { + pr_err("check clk gates number\n"); + return -EINVAL; + } + + for (clkid = 0; clkid < MCLK_BASE; clkid++) { + tl1_audio_clk_gates[clkid]->reg = iobase; + clks[clkid] = clk_register(NULL, tl1_audio_clk_hws[clkid]); + WARN_ON(IS_ERR_OR_NULL(clks[clkid])); + } + + return 0; +} + +/* mclk_a */ +CLOCK_COM_MUX(mclk_a, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_A_CTRL(1)), 0x7, 24); +CLOCK_COM_DIV(mclk_a, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_A_CTRL(1)), 0, 16); +CLOCK_COM_GATE(mclk_a, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_A_CTRL(1)), 31); +/* mclk_b */ +CLOCK_COM_MUX(mclk_b, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_B_CTRL(1)), 0x7, 24); +CLOCK_COM_DIV(mclk_b, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_B_CTRL(1)), 0, 16); +CLOCK_COM_GATE(mclk_b, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_B_CTRL(1)), 31); +/* mclk_c */ +CLOCK_COM_MUX(mclk_c, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_C_CTRL(1)), 0x7, 24); +CLOCK_COM_DIV(mclk_c, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_C_CTRL(1)), 0, 16); +CLOCK_COM_GATE(mclk_c, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_C_CTRL(1)), 31); +/* mclk_d */ +CLOCK_COM_MUX(mclk_d, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_D_CTRL(1)), 0x7, 24); +CLOCK_COM_DIV(mclk_d, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_D_CTRL(1)), 0, 16); +CLOCK_COM_GATE(mclk_d, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_D_CTRL(1)), 31); +/* mclk_e */ +CLOCK_COM_MUX(mclk_e, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_E_CTRL(1)), 0x7, 24); +CLOCK_COM_DIV(mclk_e, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_E_CTRL(1)), 0, 16); +CLOCK_COM_GATE(mclk_e, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_E_CTRL(1)), 31); +/* mclk_f */ +CLOCK_COM_MUX(mclk_f, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_F_CTRL(1)), 0x7, 24); +CLOCK_COM_DIV(mclk_f, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_F_CTRL(1)), 0, 16); +CLOCK_COM_GATE(mclk_f, AUD_ADDR_OFFSET(EE_AUDIO_MCLK_F_CTRL(1)), 31); +/* spdifin */ +CLOCK_COM_MUX(spdifin, AUD_ADDR_OFFSET(EE_AUDIO_CLK_SPDIFIN_CTRL), 0x7, 24); +CLOCK_COM_DIV(spdifin, AUD_ADDR_OFFSET(EE_AUDIO_CLK_SPDIFIN_CTRL), 0, 8); +CLOCK_COM_GATE(spdifin, AUD_ADDR_OFFSET(EE_AUDIO_CLK_SPDIFIN_CTRL), 31); +/* spdifout */ +CLOCK_COM_MUX(spdifout, AUD_ADDR_OFFSET(EE_AUDIO_CLK_SPDIFOUT_CTRL), 0x7, 24); +CLOCK_COM_DIV(spdifout, AUD_ADDR_OFFSET(EE_AUDIO_CLK_SPDIFOUT_CTRL), 0, 10); +CLOCK_COM_GATE(spdifout, AUD_ADDR_OFFSET(EE_AUDIO_CLK_SPDIFOUT_CTRL), 31); +/* pdmin0 */ +CLOCK_COM_MUX(pdmin0, AUD_ADDR_OFFSET(EE_AUDIO_CLK_PDMIN_CTRL0), 0x7, 24); +CLOCK_COM_DIV(pdmin0, AUD_ADDR_OFFSET(EE_AUDIO_CLK_PDMIN_CTRL0), 0, 16); +CLOCK_COM_GATE(pdmin0, AUD_ADDR_OFFSET(EE_AUDIO_CLK_PDMIN_CTRL0), 31); +/* pdmin1 */ +CLOCK_COM_MUX(pdmin1, AUD_ADDR_OFFSET(EE_AUDIO_CLK_PDMIN_CTRL1), 0x7, 24); +CLOCK_COM_DIV(pdmin1, AUD_ADDR_OFFSET(EE_AUDIO_CLK_PDMIN_CTRL1), 0, 16); +CLOCK_COM_GATE(pdmin1, AUD_ADDR_OFFSET(EE_AUDIO_CLK_PDMIN_CTRL1), 31); +/* spdifout b*/ +CLOCK_COM_MUX(spdifout_b, + AUD_ADDR_OFFSET(EE_AUDIO_CLK_SPDIFOUT_B_CTRL), 0x7, 24); +CLOCK_COM_DIV(spdifout_b, AUD_ADDR_OFFSET(EE_AUDIO_CLK_SPDIFOUT_B_CTRL), 0, 10); +CLOCK_COM_GATE(spdifout_b, AUD_ADDR_OFFSET(EE_AUDIO_CLK_SPDIFOUT_B_CTRL), 31); +/* audio locker_out */ +CLOCK_COM_MUX(locker_out, AUD_ADDR_OFFSET(EE_AUDIO_CLK_LOCKER_CTRL), 0xf, 24); +CLOCK_COM_DIV(locker_out, AUD_ADDR_OFFSET(EE_AUDIO_CLK_LOCKER_CTRL), 16, 8); +CLOCK_COM_GATE(locker_out, AUD_ADDR_OFFSET(EE_AUDIO_CLK_LOCKER_CTRL), 31); +/* audio locker_in */ +CLOCK_COM_MUX(locker_in, AUD_ADDR_OFFSET(EE_AUDIO_CLK_LOCKER_CTRL), 0xf, 8); +CLOCK_COM_DIV(locker_in, AUD_ADDR_OFFSET(EE_AUDIO_CLK_LOCKER_CTRL), 0, 8); +CLOCK_COM_GATE(locker_in, AUD_ADDR_OFFSET(EE_AUDIO_CLK_LOCKER_CTRL), 15); +/* audio resample */ +CLOCK_COM_MUX(resample, AUD_ADDR_OFFSET(EE_AUDIO_CLK_RESAMPLEA_CTRL), 0xf, 24); +CLOCK_COM_DIV(resample, AUD_ADDR_OFFSET(EE_AUDIO_CLK_RESAMPLEA_CTRL), 0, 8); +CLOCK_COM_GATE(resample, AUD_ADDR_OFFSET(EE_AUDIO_CLK_RESAMPLEA_CTRL), 31); + +static int tl1_clks_init(struct clk **clks, void __iomem *iobase) +{ + IOMAP_COM_CLK(mclk_a, iobase); + clks[CLKID_AUDIO_MCLK_A] = REGISTER_CLK_COM(mclk_a); + WARN_ON(IS_ERR_OR_NULL(clks[CLKID_AUDIO_MCLK_A])); + + IOMAP_COM_CLK(mclk_b, iobase); + clks[CLKID_AUDIO_MCLK_B] = REGISTER_CLK_COM(mclk_b); + WARN_ON(IS_ERR_OR_NULL(clks[CLKID_AUDIO_MCLK_B])); + + IOMAP_COM_CLK(mclk_c, iobase); + clks[CLKID_AUDIO_MCLK_C] = REGISTER_CLK_COM(mclk_c); + WARN_ON(IS_ERR_OR_NULL(clks[CLKID_AUDIO_MCLK_C])); + + IOMAP_COM_CLK(mclk_d, iobase); + clks[CLKID_AUDIO_MCLK_D] = REGISTER_CLK_COM(mclk_d); + WARN_ON(IS_ERR_OR_NULL(clks[CLKID_AUDIO_MCLK_D])); + + IOMAP_COM_CLK(mclk_e, iobase); + clks[CLKID_AUDIO_MCLK_E] = REGISTER_CLK_COM(mclk_e); + WARN_ON(IS_ERR_OR_NULL(clks[CLKID_AUDIO_MCLK_E])); + + IOMAP_COM_CLK(mclk_f, iobase); + clks[CLKID_AUDIO_MCLK_F] = REGISTER_CLK_COM(mclk_f); + WARN_ON(IS_ERR_OR_NULL(clks[CLKID_AUDIO_MCLK_F])); + + IOMAP_COM_CLK(spdifin, iobase); + clks[CLKID_AUDIO_SPDIFIN_CTRL] = REGISTER_CLK_COM(spdifin); + WARN_ON(IS_ERR_OR_NULL(clks[CLKID_AUDIO_SPDIFIN_CTRL])); + + IOMAP_COM_CLK(spdifout, iobase); + clks[CLKID_AUDIO_SPDIFOUT_CTRL] = REGISTER_CLK_COM(spdifout); + WARN_ON(IS_ERR_OR_NULL(clks[CLKID_AUDIO_SPDIFOUT_CTRL])); + + IOMAP_COM_CLK(pdmin0, iobase); + clks[CLKID_AUDIO_PDMIN0] = REGISTER_CLK_COM(pdmin0); + WARN_ON(IS_ERR_OR_NULL(clks[CLKID_AUDIO_PDMIN0])); + + IOMAP_COM_CLK(pdmin1, iobase); + clks[CLKID_AUDIO_PDMIN1] = REGISTER_CLK_COM(pdmin1); + WARN_ON(IS_ERR_OR_NULL(clks[CLKID_AUDIO_PDMIN1])); + + IOMAP_COM_CLK(spdifout_b, iobase); + clks[CLKID_AUDIO_SPDIFOUTB_CTRL] = REGISTER_CLK_COM(spdifout_b); + WARN_ON(IS_ERR_OR_NULL(clks[CLKID_AUDIO_SPDIFOUTB_CTRL])); + + IOMAP_COM_CLK(locker_out, iobase); + clks[CLKID_AUDIO_LOCKER_OUT] = REGISTER_AUDIOCLK_COM(locker_out); + WARN_ON(IS_ERR_OR_NULL(clks[CLKID_AUDIO_LOCKER_OUT])); + + IOMAP_COM_CLK(locker_in, iobase); + clks[CLKID_AUDIO_LOCKER_IN] = REGISTER_AUDIOCLK_COM(locker_in); + WARN_ON(IS_ERR_OR_NULL(clks[CLKID_AUDIO_LOCKER_IN])); + + IOMAP_COM_CLK(resample, iobase); + clks[CLKID_AUDIO_RESAMPLE_CTRL] = REGISTER_AUDIOCLK_COM(resample); + WARN_ON(IS_ERR_OR_NULL(clks[CLKID_AUDIO_RESAMPLE_CTRL])); + + return 0; +} + +struct audio_clk_init tl1_audio_clks_init = { + .clk_num = NUM_AUDIO_CLKS, + .clk_gates = tl1_clk_gates_init, + .clks = tl1_clks_init, +}; diff --git a/sound/soc/amlogic/meson/i2s.c b/sound/soc/amlogic/meson/i2s.c index 4ee75a061dd7..461fe03e9f4d 100644 --- a/sound/soc/amlogic/meson/i2s.c +++ b/sound/soc/amlogic/meson/i2s.c @@ -412,13 +412,12 @@ static enum hrtimer_restart aml_i2s_hrtimer_callback(struct hrtimer *timer) struct audio_stream *s = &prtd->s; unsigned int last_ptr, size; unsigned long flags = 0; - + spin_lock_irqsave(&prtd->timer_lock, flags); if (prtd->active == 0) { hrtimer_forward_now(timer, prtd->wakeups_per_second); + spin_unlock_irqrestore(&prtd->timer_lock, flags); return HRTIMER_RESTART; } - - spin_lock_irqsave(&prtd->timer_lock, flags); if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { last_ptr = read_i2s_rd_ptr(); if (last_ptr < s->last_ptr) diff --git a/sound/soc/amlogic/meson/meson.c b/sound/soc/amlogic/meson/meson.c index eb32128c4b82..cbb1f1351409 100644 --- a/sound/soc/amlogic/meson/meson.c +++ b/sound/soc/amlogic/meson/meson.c @@ -683,19 +683,19 @@ static int aml_card_dais_parse_of(struct snd_soc_card *card) init = NULL; /* CPU sub-node */ cpu_node = of_parse_phandle(np, "cpu_list", i); - if (cpu_node < 0) { + if (!cpu_node) { dev_err(dev, "parse aml sound card cpu list error\n"); return -EINVAL; } /* CODEC sub-node */ codec_node = of_parse_phandle(np, "codec_list", i); - if (codec_node < 0) { + if (!codec_node) { dev_err(dev, "parse aml sound card codec list error\n"); return ret; } /* Platform sub-node */ plat_node = of_parse_phandle(np, "plat_list", i); - if (plat_node < 0) { + if (!plat_node) { dev_err(dev, "parse aml sound card platform list error\n"); return ret; diff --git a/sound/soc/codecs/amlogic/Kconfig b/sound/soc/codecs/amlogic/Kconfig index 6e7160b0b282..ac0d8467953e 100644 --- a/sound/soc/codecs/amlogic/Kconfig +++ b/sound/soc/codecs/amlogic/Kconfig @@ -78,6 +78,16 @@ config AMLOGIC_SND_CODEC_TXLX_ACODEC AML txlx acodec, this codec is internal +config AMLOGIC_SND_CODEC_TL1_ACODEC + bool "Amlogic Audio tl1 acodec" + depends on AMLOGIC_SND_SOC_CODECS + default n + help + Amlogic Audio codec, + AML tl1 acodec, + AML tl1 acodec, + this codec is internal + #Third part codecs # Amlogic add codecs config AMLOGIC_SND_SOC_TAS5707 diff --git a/sound/soc/codecs/amlogic/Makefile b/sound/soc/codecs/amlogic/Makefile index 1ba930ad73fd..915e6461f554 100644 --- a/sound/soc/codecs/amlogic/Makefile +++ b/sound/soc/codecs/amlogic/Makefile @@ -9,6 +9,7 @@ snd-soc-aml_t9015-objs := aml_codec_t9015.o snd-soc-aml_t9015s-objs := aml_codec_t9015S.o snd-soc-pmu3-objs := aml_pmu3.o snd-soc-aml_codec_txlx_acodec-objs := aml_codec_txlx_acodec.o +snd-soc-aml_codec_tl1_acodec-objs := aml_codec_tl1_acodec.o #Third part codecs snd-soc-tas5707-objs := tas5707.o @@ -26,6 +27,7 @@ obj-$(CONFIG_AMLOGIC_SND_CODEC_AMLT9015) += snd-soc-aml_t9015.o obj-$(CONFIG_AMLOGIC_SND_CODEC_AMLT9015S) += snd-soc-aml_t9015s.o obj-$(CONFIG_AMLOGIC_SND_CODEC_PMU3) += snd-soc-pmu3.o obj-$(CONFIG_AMLOGIC_SND_CODEC_TXLX_ACODEC) += snd-soc-aml_codec_txlx_acodec.o +obj-$(CONFIG_AMLOGIC_SND_CODEC_TL1_ACODEC) += snd-soc-aml_codec_tl1_acodec.o #Third part codecs obj-$(CONFIG_AMLOGIC_SND_SOC_TAS5707) += snd-soc-tas5707.o diff --git a/sound/soc/codecs/amlogic/aml_codec_tl1_acodec.c b/sound/soc/codecs/amlogic/aml_codec_tl1_acodec.c new file mode 100644 index 000000000000..4869c6f645da --- /dev/null +++ b/sound/soc/codecs/amlogic/aml_codec_tl1_acodec.c @@ -0,0 +1,778 @@ +/* + * linux/sound/soc/codecs/aml_codec_tl1_acodec.c + * + * Copyright 2017 AMLogic, Inc. + * + * Author: shuyu.li + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include "aml_codec_tl1_acodec.h" + +struct tl1_acodec_priv { + struct snd_soc_codec *codec; + struct snd_pcm_hw_params *params; + struct regmap *regmap; + + int tdmout_index; +}; + +static const struct reg_default tl1_acodec_init_list[] = { + {ACODEC_0, 0x3403BFCF}, + {ACODEC_1, 0x50502929}, + {ACODEC_2, 0xFBFB0000}, + {ACODEC_3, 0x00002222}, + {ACODEC_4, 0x00010000}, + {ACODEC_5, 0xFBFB0033}, + {ACODEC_6, 0x0}, + {ACODEC_7, 0x0} +}; + +static int tl1_acodec_reg_init(struct snd_soc_codec *codec) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(tl1_acodec_init_list); i++) + snd_soc_write(codec, tl1_acodec_init_list[i].reg, + tl1_acodec_init_list[i].def); + + return 0; +} + +static int aml_DAC_Gain_get_enum( + struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); + struct snd_soc_codec *codec = snd_soc_component_to_codec(component); + + u32 reg_addr = ACODEC_1; + u32 val = snd_soc_read(codec, reg_addr); + u32 val1 = (val & (0x1 << REG_DAC_GAIN_SEL_0)) + >> REG_DAC_GAIN_SEL_0; + u32 val2 = (val & (0x1 << REG_DAC_GAIN_SEL_1)) + >> (REG_DAC_GAIN_SEL_1); + val = val1 | (val2<<1); + + ucontrol->value.enumerated.item[0] = val; + return 0; +} + +static int aml_DAC_Gain_set_enum( + struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); + u32 reg_addr = ACODEC_1; + u32 val = snd_soc_read(codec, reg_addr); + + if (ucontrol->value.enumerated.item[0] == 0) { + val &= ~(0x1 << REG_DAC_GAIN_SEL_1); + val &= ~(0x1 << REG_DAC_GAIN_SEL_0); + } else if (ucontrol->value.enumerated.item[0] == 1) { + val &= ~(0x1 << REG_DAC_GAIN_SEL_1); + val |= (0x1 << REG_DAC_GAIN_SEL_0); + pr_info("It has risk of distortion!\n"); + } else if (ucontrol->value.enumerated.item[0] == 2) { + val |= (0x1 << REG_DAC_GAIN_SEL_1); + val &= ~(0x1 << REG_DAC_GAIN_SEL_0); + pr_info("It has risk of distortion!\n"); + } else if (ucontrol->value.enumerated.item[0] == 3) { + val |= (0x1 << REG_DAC_GAIN_SEL_1); + val |= (0x1 << REG_DAC_GAIN_SEL_0); + pr_info("It has risk of distortion!\n"); + } + + snd_soc_write(codec, val, reg_addr); + return 0; +} + +static int aml_DAC2_Gain_get_enum( + struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); + struct snd_soc_codec *codec = snd_soc_component_to_codec(component); + + u32 reg_addr = ACODEC_7; + u32 val = snd_soc_read(codec, reg_addr); + u32 val1 = (val & (0x1 << REG_DAC2_GAIN_SEL_0)) + >> REG_DAC_GAIN_SEL_0; + u32 val2 = (val & (0x1 << REG_DAC2_GAIN_SEL_1)) + >> (REG_DAC2_GAIN_SEL_1); + val = val1 | (val2<<1); + + ucontrol->value.enumerated.item[0] = val; + return 0; +} + +static int aml_DAC2_Gain_set_enum( + struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); + u32 reg_addr = ACODEC_7; + u32 val = snd_soc_read(codec, reg_addr); + + if (ucontrol->value.enumerated.item[0] == 0) { + val &= ~(0x1 << REG_DAC2_GAIN_SEL_1); + val &= ~(0x1 << REG_DAC2_GAIN_SEL_0); + } else if (ucontrol->value.enumerated.item[0] == 1) { + val &= ~(0x1 << REG_DAC2_GAIN_SEL_1); + val |= (0x1 << REG_DAC2_GAIN_SEL_0); + pr_info("It has risk of distortion!\n"); + } else if (ucontrol->value.enumerated.item[0] == 2) { + val |= (0x1 << REG_DAC2_GAIN_SEL_1); + val &= ~(0x1 << REG_DAC2_GAIN_SEL_0); + pr_info("It has risk of distortion!\n"); + } else if (ucontrol->value.enumerated.item[0] == 3) { + val |= (0x1 << REG_DAC2_GAIN_SEL_1); + val |= (0x1 << REG_DAC2_GAIN_SEL_0); + pr_info("It has risk of distortion!\n"); + } + + snd_soc_write(codec, val, reg_addr); + return 0; +} + + +static const DECLARE_TLV_DB_SCALE(pga_in_tlv, -1200, 250, 1); +static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -29625, 375, 1); +static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -95250, 375, 1); +static const DECLARE_TLV_DB_SCALE(dac2_vol_tlv, -95250, 375, 1); + +static const char *const DAC_Gain_texts[] = { "0dB", "6dB", "12dB", "18dB" }; +static const char *const DAC2_Gain_texts[] = { "0dB", "6dB", "12dB", "18dB" }; + +static const struct soc_enum DAC_Gain_enum = SOC_ENUM_SINGLE( + SND_SOC_NOPM, 0, ARRAY_SIZE(DAC_Gain_texts), + DAC_Gain_texts); +static const struct soc_enum DAC2_Gain_enum = SOC_ENUM_SINGLE( + SND_SOC_NOPM, 0, ARRAY_SIZE(DAC2_Gain_texts), + DAC2_Gain_texts); + +static const struct snd_kcontrol_new tl1_acodec_snd_controls[] = { + /*PGA_IN Gain */ + SOC_DOUBLE_TLV("PGA IN Gain", ACODEC_1, + PGAL_IN_GAIN, PGAR_IN_GAIN, + 0x1f, 0, pga_in_tlv), + + /*ADC Digital Volume control */ + SOC_DOUBLE_TLV("ADC Digital Capture Volume", ACODEC_1, + ADCL_VC, ADCR_VC, + 0x7f, 0, adc_vol_tlv), + + /*DAC Digital Volume control */ + SOC_DOUBLE_TLV("DAC Digital Playback Volume", + ACODEC_2, + DACL_VC, DACR_VC, + 0xff, 0, dac_vol_tlv), + + /*DAC 2 Digital Volume control */ + SOC_DOUBLE_TLV("DAC 2 Digital Playback Volume", + ACODEC_5, + DAC2L_VC, DAC2R_VC, + 0xff, 0, dac2_vol_tlv), + + /*DAC extra Digital Gain control */ + SOC_ENUM_EXT("DAC Extra Digital Gain", + DAC_Gain_enum, + aml_DAC_Gain_get_enum, + aml_DAC_Gain_set_enum), + + /* TODO: DAC 2 extra Digital Gain control */ + SOC_ENUM_EXT("DAC2 Extra Digital Gain", + DAC2_Gain_enum, + aml_DAC2_Gain_get_enum, + aml_DAC2_Gain_set_enum), +}; + +/*pgain Left Channel Input */ +static const char * const linein_left_txt[] = { + "None", "AIL1", "AIL2", "AIL3", "AIL4", +}; + +static const SOC_ENUM_SINGLE_DECL(linein_left_enum, + ACODEC_1, + PGAL_IN_SEL, linein_left_txt); + +static const struct snd_kcontrol_new lil_mux = +SOC_DAPM_ENUM("ROUTE_L", linein_left_enum); + +/*pgain right Channel Input */ +static const char * const linein_right_txt[] = { + "None", "AIR1", "AIR2", "AIR3", "AIR4", +}; + +static const SOC_ENUM_SINGLE_DECL(linein_right_enum, + ACODEC_1, + PGAR_IN_SEL, linein_right_txt); + +static const struct snd_kcontrol_new lir_mux = +SOC_DAPM_ENUM("ROUTE_R", linein_right_enum); + + +/*line out 1 Left mux */ +static const char * const out_lo1l_txt[] = { + "None", "LO1L_SEL_INL", "LO1L_SEL_DACL", "Reserved", "LO1L_SEL_DACR_INV" +}; + +static const SOC_ENUM_SINGLE_DECL(out_lo1l_enum, ACODEC_3, + LO1L_SEL_INL, out_lo1l_txt); + +static const struct snd_kcontrol_new lo1l_mux = +SOC_DAPM_ENUM("LO1L_MUX", out_lo1l_enum); + +/*line out 1 right mux */ +static const char * const out_lo1r_txt[] = { + "None", "LO1R_SEL_INR", "LO1R_SEL_DACR", "Reserved", "LO1R_SEL_DACL_INV" +}; + +static const SOC_ENUM_SINGLE_DECL(out_lo1r_enum, ACODEC_3, + LO1R_SEL_INR, out_lo1r_txt); + +static const struct snd_kcontrol_new lo1r_mux = +SOC_DAPM_ENUM("LO1R_MUX", out_lo1r_enum); + +/*line out 2 left mux */ +static const char * const out_lo2l_txt[] = { + "None", "LO2L_SEL_INL", "LO2L_SEL_DAC2L", "Reserved", + "LO2L_SEL_DAC2R_INV" +}; + +static const SOC_ENUM_SINGLE_DECL(out_lo2l_enum, ACODEC_3, + LO2L_SEL_INL, out_lo2l_txt); + +static const struct snd_kcontrol_new lo2l_mux = +SOC_DAPM_ENUM("LO2L_MUX", out_lo2l_enum); + +/*line out 2 Right mux */ +static const char * const out_lo2r_txt[] = { + "None", "LO2R_SEL_INR", "LO2R_SEL_DAC2R", "Reserved", + "LO2R_SEL_DAC2L_INV" +}; + +static const SOC_ENUM_SINGLE_DECL(out_lo2r_enum, ACODEC_3, + LO2R_SEL_INR, out_lo2r_txt); + +static const struct snd_kcontrol_new lo2r_mux = +SOC_DAPM_ENUM("LO2R_MUX", out_lo2r_enum); + + +static const struct snd_soc_dapm_widget tl1_acodec_dapm_widgets[] = { + + /* Input */ + SND_SOC_DAPM_INPUT("Linein left 1"), + SND_SOC_DAPM_INPUT("Linein left 2"), + SND_SOC_DAPM_INPUT("Linein left 3"), + SND_SOC_DAPM_INPUT("Linein left 4"), + + SND_SOC_DAPM_INPUT("Linein right 1"), + SND_SOC_DAPM_INPUT("Linein right 2"), + SND_SOC_DAPM_INPUT("Linein right 3"), + SND_SOC_DAPM_INPUT("Linein right 4"), + + /*PGA input */ + SND_SOC_DAPM_PGA("PGAL_IN_EN", SND_SOC_NOPM, + 0, 0, NULL, 0), + SND_SOC_DAPM_PGA("PGAR_IN_EN", SND_SOC_NOPM, + 0, 0, NULL, 0), + + /*PGA input source select */ + SND_SOC_DAPM_MUX("Linein left switch", SND_SOC_NOPM, + 0, 0, &lil_mux), + SND_SOC_DAPM_MUX("Linein right switch", SND_SOC_NOPM, + 0, 0, &lir_mux), + + /*ADC capture stream */ + SND_SOC_DAPM_ADC("Left ADC", "Capture", ACODEC_0, + ADCL_EN, 0), + SND_SOC_DAPM_ADC("Right ADC", "Capture", ACODEC_0, + ADCR_EN, 0), + + /*Output */ + SND_SOC_DAPM_OUTPUT("Lineout 1 left"), + SND_SOC_DAPM_OUTPUT("Lineout 1 right"), + SND_SOC_DAPM_OUTPUT("Lineout 2 left"), + SND_SOC_DAPM_OUTPUT("Lineout 2 right"), + + /*DAC playback stream */ + SND_SOC_DAPM_DAC("Left DAC", "Playback", + ACODEC_0, + DACL_EN, 0), + SND_SOC_DAPM_DAC("Right DAC", "Playback", + ACODEC_0, + DACR_EN, 0), + + /*DAC 2 playback stream */ + SND_SOC_DAPM_DAC("Left DAC2", "Playback", + ACODEC_5, + DAC2L_EN, 0), + SND_SOC_DAPM_DAC("Right DAC2", "Playback", + ACODEC_5, + DAC2R_EN, 0), + + /*DRV output */ + SND_SOC_DAPM_OUT_DRV("LO1L_OUT_EN", ACODEC_0, + LO1L_EN, 0, NULL, 0), + SND_SOC_DAPM_OUT_DRV("LO1R_OUT_EN", ACODEC_0, + LO1R_EN, 0, NULL, 0), + SND_SOC_DAPM_OUT_DRV("LO2L_OUT_EN", ACODEC_0, + LO2L_EN, 0, NULL, 0), + SND_SOC_DAPM_OUT_DRV("LO2R_OUT_EN", ACODEC_0, + LO2R_EN, 0, NULL, 0), + + /*MUX output source select */ + SND_SOC_DAPM_MUX("Lineout 1 left switch", SND_SOC_NOPM, + 0, 0, &lo1l_mux), + SND_SOC_DAPM_MUX("Lineout 1 right switch", SND_SOC_NOPM, + 0, 0, &lo1r_mux), + SND_SOC_DAPM_MUX("Lineout 2 left switch", SND_SOC_NOPM, + 0, 0, &lo2l_mux), + SND_SOC_DAPM_MUX("Lineout 2 right switch", SND_SOC_NOPM, + 0, 0, &lo2r_mux), + +}; + +static const struct snd_soc_dapm_route tl1_acodec_dapm_routes[] = { +/* Input path */ + {"Linein left switch", "AIL1", "Linein left 1"}, + {"Linein left switch", "AIL2", "Linein left 2"}, + {"Linein left switch", "AIL3", "Linein left 3"}, + {"Linein left switch", "AIL4", "Linein left 4"}, + + {"Linein right switch", "AIR1", "Linein right 1"}, + {"Linein right switch", "AIR2", "Linein right 2"}, + {"Linein right switch", "AIR3", "Linein right 3"}, + {"Linein right switch", "AIR4", "Linein right 4"}, + + {"PGAL_IN_EN", NULL, "Linein left switch"}, + {"PGAR_IN_EN", NULL, "Linein right switch"}, + + {"Left ADC", NULL, "PGAL_IN_EN"}, + {"Right ADC", NULL, "PGAR_IN_EN"}, + +/*Output path*/ + {"Lineout 1 left switch", NULL, "Left DAC"}, + {"Lineout 1 left switch", NULL, "Right DAC"}, + {"Lineout 1 left switch", NULL, "PGAL_IN_EN"}, + + {"Lineout 1 right switch", NULL, "Right DAC"}, + {"Lineout 1 right switch", NULL, "Left DAC"}, + {"Lineout 1 right switch", NULL, "PGAR_IN_EN"}, + + {"Lineout 2 left switch", NULL, "Left DAC2"}, + {"Lineout 2 left switch", NULL, "Right DAC2"}, + {"Lineout 2 left switch", NULL, "PGAL_IN_EN"}, + + {"Lineout 2 right switch", NULL, "Right DAC2"}, + {"Lineout 2 right switch", NULL, "Left DAC2"}, + {"Lineout 2 right switch", NULL, "PGAR_IN_EN"}, + + {"LO1L_OUT_EN", NULL, "Lineout 1 left switch"}, + {"LO1R_OUT_EN", NULL, "Lineout 1 right switch"}, + {"LO2L_OUT_EN", NULL, "Lineout 2 left switch"}, + {"LO2R_OUT_EN", NULL, "Lineout 2 right switch"}, + + {"Lineout 1 left", NULL, "LO1L_OUT_EN"}, + {"Lineout 1 right", NULL, "LO1R_OUT_EN"}, + {"Lineout 2 left", NULL, "LO2L_OUT_EN"}, + {"Lineout 2 right", NULL, "LO2R_OUT_EN"}, +}; + +static int tl1_acodec_dai_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) +{ + struct snd_soc_codec *codec = dai->codec; + u32 val = snd_soc_read(codec, ACODEC_0); + + pr_debug("%s, format:%x, codec = %p\n", __func__, fmt, codec); + + switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { + case SND_SOC_DAIFMT_CBM_CFM: + val |= (0x1 << I2S_MODE); + break; + case SND_SOC_DAIFMT_CBS_CFS: + val &= ~(0x1 << I2S_MODE); + break; + default: + return -EINVAL; + } + + snd_soc_write(codec, ACODEC_0, val); + + return 0; +} + +static int tl1_acodec_dai_set_sysclk(struct snd_soc_dai *dai, + int clk_id, unsigned int freq, int dir) +{ + return 0; +} + +static int tl1_acodec_dai_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params, + struct snd_soc_dai *dai) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct snd_soc_codec *codec = rtd->codec; + struct tl1_acodec_priv *aml_acodec = + snd_soc_codec_get_drvdata(codec); + + pr_debug("%s!\n", __func__); + + aml_acodec->params = params; + + return 0; +} + +static int tl1_acodec_dai_set_bias_level(struct snd_soc_codec *codec, + enum snd_soc_bias_level level) +{ + switch (level) { + case SND_SOC_BIAS_ON: + + break; + + case SND_SOC_BIAS_PREPARE: + + break; + + case SND_SOC_BIAS_STANDBY: + if (codec->component.dapm.bias_level == SND_SOC_BIAS_OFF) { + snd_soc_cache_sync(codec); + } + break; + + case SND_SOC_BIAS_OFF: + snd_soc_write(codec, ACODEC_0, 0); + break; + + default: + break; + } + codec->component.dapm.bias_level = level; + + return 0; +} + +static int tl1_acodec_dai_prepare(struct snd_pcm_substream *substream, + struct snd_soc_dai *dai) +{ + return 0; +} + +//TODO, need to check +static int tl1_acodec_reset(struct snd_soc_codec *codec) +{ + struct tl1_acodec_priv *tl1_acodec = + snd_soc_codec_get_drvdata(codec); + if (tl1_acodec) + auge_acodec_reset(); + udelay(1000); + return 0; +} +//TODO, need to check +static int tl1_acodec_start_up(struct snd_soc_codec *codec) +{ + snd_soc_write(codec, ACODEC_0, 0xF000); + msleep(200); + snd_soc_write(codec, ACODEC_0, 0xB000); + + return 0; +} + +static int tl1_acodec_dai_mute_stream(struct snd_soc_dai *dai, int mute, + int stream) +{ + struct tl1_acodec_priv *aml_acodec = + snd_soc_codec_get_drvdata(dai->codec); + u32 reg_val; + + pr_debug("%s, mute:%d\n", __func__, mute); + + if (stream == SNDRV_PCM_STREAM_PLAYBACK) { + /* DAC 1 */ + regmap_read(aml_acodec->regmap, + ACODEC_2, + ®_val); + if (mute) + reg_val |= DAC_SOFT_MUTE; + else + reg_val &= ~DAC_SOFT_MUTE; + + regmap_write(aml_acodec->regmap, + ACODEC_2, + reg_val); + + + /* DAC 2 */ + regmap_read(aml_acodec->regmap, + ACODEC_6, + ®_val); + if (mute) + reg_val |= DAC2_SOFT_MUTE; + else + reg_val &= ~DAC2_SOFT_MUTE; + + regmap_write(aml_acodec->regmap, + ACODEC_6, + reg_val); + } + + return 0; +} + +struct snd_soc_dai_ops tl1_acodec_dai_ops = { + .hw_params = tl1_acodec_dai_hw_params, + .prepare = tl1_acodec_dai_prepare, + .set_fmt = tl1_acodec_dai_set_fmt, + .set_sysclk = tl1_acodec_dai_set_sysclk, + .mute_stream = tl1_acodec_dai_mute_stream, +}; + +static int tl1_acodec_probe(struct snd_soc_codec *codec) +{ + struct tl1_acodec_priv *aml_acodec = + snd_soc_codec_get_drvdata(codec); + + if (!aml_acodec) { + pr_err("Failed to get tl1 acodec pri\n"); + return -EINVAL; + } + + /*reset audio codec register*/ + tl1_acodec_reset(codec); + tl1_acodec_start_up(codec); + tl1_acodec_reg_init(codec); + + if (aml_acodec) + auge_toacodec_ctrl(aml_acodec->tdmout_index); + + aml_acodec->codec = codec; + tl1_acodec_dai_set_bias_level(codec, SND_SOC_BIAS_STANDBY); + + return 0; +} + +static int tl1_acodec_remove(struct snd_soc_codec *codec) +{ + pr_info("%s!\n", __func__); + + tl1_acodec_dai_set_bias_level(codec, SND_SOC_BIAS_OFF); + + return 0; +} + +static int tl1_acodec_suspend(struct snd_soc_codec *codec) +{ + pr_info("%s!\n", __func__); + + tl1_acodec_dai_set_bias_level(codec, SND_SOC_BIAS_OFF); + + return 0; +} + +static int tl1_acodec_resume(struct snd_soc_codec *codec) +{ + pr_info("%s!\n", __func__); + + tl1_acodec_reset(codec); + tl1_acodec_start_up(codec); + tl1_acodec_reg_init(codec); + + tl1_acodec_dai_set_bias_level(codec, SND_SOC_BIAS_STANDBY); + + return 0; +} + +static struct snd_soc_codec_driver soc_codec_dev_tl1_acodec = { + .probe = tl1_acodec_probe, + .remove = tl1_acodec_remove, + .suspend = tl1_acodec_suspend, + .resume = tl1_acodec_resume, + .set_bias_level = tl1_acodec_dai_set_bias_level, + .component_driver = { + .controls = tl1_acodec_snd_controls, + .num_controls = ARRAY_SIZE(tl1_acodec_snd_controls), + .dapm_widgets = tl1_acodec_dapm_widgets, + .num_dapm_widgets = ARRAY_SIZE(tl1_acodec_dapm_widgets), + .dapm_routes = tl1_acodec_dapm_routes, + .num_dapm_routes = ARRAY_SIZE(tl1_acodec_dapm_routes), + } +}; + +static const struct regmap_config tl1_acodec_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x1c, + .reg_defaults = tl1_acodec_init_list, + .num_reg_defaults = ARRAY_SIZE(tl1_acodec_init_list), + .cache_type = REGCACHE_RBTREE, +}; + +#define TL1_ACODEC_RATES SNDRV_PCM_RATE_8000_96000 +#define TL1_ACODEC_FORMATS (SNDRV_PCM_FMTBIT_S16_LE \ + | SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S24_LE \ + | SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S32_LE) + +struct snd_soc_dai_driver aml_tl1_acodec_dai = { + .name = "tl1-acodec-hifi", + .id = 0, + .playback = { + .stream_name = "Playback", + .channels_min = 2, + .channels_max = 8, + .rates = TL1_ACODEC_RATES, + .formats = TL1_ACODEC_FORMATS, + }, + .capture = { + .stream_name = "Capture", + .channels_min = 2, + .channels_max = 8, + .rates = TL1_ACODEC_RATES, + .formats = TL1_ACODEC_FORMATS, + }, + .ops = &tl1_acodec_dai_ops, +}; + +static int aml_tl1_acodec_probe(struct platform_device *pdev) +{ + struct tl1_acodec_priv *aml_acodec; + struct resource *res_mem; + struct device_node *np; + void __iomem *regs; + int ret = 0; + + dev_info(&pdev->dev, "%s\n", __func__); + + np = pdev->dev.of_node; + + aml_acodec = devm_kzalloc(&pdev->dev, sizeof(struct tl1_acodec_priv), + GFP_KERNEL); + if (!aml_acodec) + return -ENOMEM; + + res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res_mem) + return -ENODEV; + + regs = devm_ioremap_resource(&pdev->dev, res_mem); + if (IS_ERR(regs)) + return PTR_ERR(regs); + + aml_acodec->regmap = devm_regmap_init_mmio(&pdev->dev, regs, + &tl1_acodec_regmap_config); + + of_property_read_u32( + pdev->dev.of_node, + "tdmout_index", + &aml_acodec->tdmout_index); + + pr_info("aml_tl1_acodec is used by tdmout:%d\n", + aml_acodec->tdmout_index); + + if (IS_ERR(aml_acodec->regmap)) + return PTR_ERR(aml_acodec->regmap); + + platform_set_drvdata(pdev, aml_acodec); + + ret = snd_soc_register_codec(&pdev->dev, + &soc_codec_dev_tl1_acodec, + &aml_tl1_acodec_dai, 1); + + return ret; +} + +static int aml_tl1_acodec_remove(struct platform_device *pdev) +{ + snd_soc_unregister_codec(&pdev->dev); + + return 0; +} + +static void aml_tl1_acodec_shutdown(struct platform_device *pdev) +{ + struct tl1_acodec_priv *aml_acodec; + struct snd_soc_codec *codec; + + aml_acodec = platform_get_drvdata(pdev); + codec = aml_acodec->codec; + if (codec) + tl1_acodec_remove(codec); +} + +static const struct of_device_id aml_tl1_acodec_dt_match[] = { + {.compatible = "amlogic, tl1_codec",}, + {}, +}; + +static struct platform_driver aml_tl1_acodec_platform_driver = { + .driver = { + .name = "tl1_codec", + .owner = THIS_MODULE, + .of_match_table = aml_tl1_acodec_dt_match, + }, + .probe = aml_tl1_acodec_probe, + .remove = aml_tl1_acodec_remove, + .shutdown = aml_tl1_acodec_shutdown, +}; + +static int __init aml_tl1_acodec_modinit(void) +{ + int ret = 0; + + ret = platform_driver_register(&aml_tl1_acodec_platform_driver); + if (ret != 0) { + pr_err( + "Failed to register AML tl1 acodec platform driver: %d\n", + ret); + } + + return ret; +} + +module_init(aml_tl1_acodec_modinit); + +static void __exit aml_tl1_acodec_modexit(void) +{ + platform_driver_unregister(&aml_tl1_acodec_platform_driver); +} + +module_exit(aml_tl1_acodec_modexit); + +MODULE_DESCRIPTION("ASoC AML TL1 audio codec driver"); +MODULE_AUTHOR("AMLogic, Inc."); +MODULE_LICENSE("GPL"); diff --git a/sound/soc/codecs/amlogic/aml_codec_tl1_acodec.h b/sound/soc/codecs/amlogic/aml_codec_tl1_acodec.h new file mode 100644 index 000000000000..c133fb17631f --- /dev/null +++ b/sound/soc/codecs/amlogic/aml_codec_tl1_acodec.h @@ -0,0 +1,138 @@ +/* + * aml_codec_tl1_acodec.h + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef _TL1_ACODEC_H +#define _TL1_ACODEC_H + +#define DEV_NAME "tl1_acodec" + +/* AML TL1 CODEC register space (in decimal to match datasheet) */ +//#define ACODEC_BASE_ADD 0xFF632000 +#define ACODEC_TOP_ADDR(x) (x) + + +/* AML TL1 CODEC register define */ +#define ACODEC_0 ACODEC_TOP_ADDR(0x00) +#define ACODEC_1 ACODEC_TOP_ADDR(0x04) +#define ACODEC_2 ACODEC_TOP_ADDR(0x08) +#define ACODEC_3 ACODEC_TOP_ADDR(0x0c) +#define ACODEC_4 ACODEC_TOP_ADDR(0x10) +#define ACODEC_5 ACODEC_TOP_ADDR(0x14) +#define ACODEC_6 ACODEC_TOP_ADDR(0x18) +#define ACODEC_7 ACODEC_TOP_ADDR(0x1C) + +/* AML TL1 CODEC register-bitfield define */ + +// bitfield def of ACODEC_0 +#define MCLK_FREQ 31 +#define I2S_MODE 30 +#define ADC_HPF_EN 29 +#define ADC_HPF_MODE 28 +#define ADC_OVERLOAD_DET_EN 27 +#define ADC_DEM_EN 26 +#define ADC_CLK_TO_GPIO_EN 25 +#define DAC_CLK_TO_GPIO_EN 24 +#define DACL_DATA_SOURCE 23 +#define DACR_DATA_SOURCE 22 +#define DACL_INV 21 +#define DACR_INV 20 +#define ADCDATL_SOURCE 19 +#define ADCDATR_SOURCE 18 +#define ADCL_INV 17 +#define ADCR_INV 16 +#define VMID_GEN_EN 15 +#define VMID_GEN_FAST 14 +#define BIAS_CURRENT_EN 13 +#define REFP_BUF_EN 12 +#define PGAL_IN_EN 11 +#define PGAR_IN_EN 10 +#define PGAL_IN_ZC_EN 9 +#define PGAR_IN_ZC_EN 8 +#define ADCL_EN 7 +#define ADCR_EN 6 +//#define DACL_EN 5 +//#define DACR_EN 4 +#define LO1L_EN 3 +#define LO1R_EN 2 +#define LO2L_EN 1 +#define LO2R_EN 0 + +// bitfield def of ACODEC_1 +#define REG_DAC_GAIN_SEL_1 31 +#define ADCL_VC 24 /* bit 30-24 */ +#define REG_DAC_GAIN_SEL_0 23 +#define ADCR_VC 16 /* bit 22-16 */ +#define PGAL_IN_SEL 13 /* bit 15-13 */ +#define PGAL_IN_GAIN 8 /* bit 12-8 */ +#define PGAR_IN_SEL 5 /* bit 7-5 */ +#define PGAR_IN_GAIN 0 /* bit 4-0 */ + +// bitfield def of ACODEC_2 +#define DACL_VC 24 /* bit 31-24 */ +#define DACR_VC 16 /* bit 23-16 */ +#define DAC_SOFT_MUTE 15 +#define DAC_UNMUTE_MODE 14 +#define DAC_MUTE_MODE 13 +#define DAC_VC_RAMP_MODE 12 +#define DAC_RAMP_RATE 10 /* bit 11-10 */ +#define DAC_MONO 8 +#define MUTE_DAC_PD_EN 7 + +// bitfield def of ACODEC_3 +#define REG_MICBIAS_EN 31 +#define REG_MICBIAS_SEL 29 /* bit 29, 30 */ +//#define REG_ANA_RESERVED 16 /* bit 16 ~ 28 */ +#define LO1L_SEL_DAC1R_INV 14 +#define LO1L_SEL_DAC1L 13 +#define LO1L_SEL_INL 12 +#define LO1R_SEL_DAC1L_INV 10 +#define LO1R_SEL_DAC1R 9 +#define LO1R_SEL_INR 8 +#define LO2L_SEL_DAC2R_INV 6 +#define LO2L_SEL_DAC2L 5 +#define LO2L_SEL_INL 4 +#define LO2R_SEL_DAC2L_INV 2 +#define LO2R_SEL_DAC2R 1 +#define LO2R_SEL_INR 0 + +// bitfield def of ACODEC_4 +#define MUTE_DAC_WHEN_POWER_DOWN 31 +#define IB_CON 16 /* bit 16, 17 */ +#define REG_ADCL_SAT_SEL 2 /* bit 2, 3 */ +#define REG_ADCR_SAT_SEL 0 /* bit 0, 1 */ + +// bitfield def of ACODEC_5 +#define DAC2L_VC 24 /* bit 24~31 */ +#define DAC2R_VC 16 /* bit 16~23 */ +#define DAC2L_EN 5 +#define DAC2R_EN 4 +#define DACL_EN 1 +#define DACR_EN 0 + + + +// bitfield def of ACODEC_6 +#define DAC2_SOFT_MUTE 31 +#define DAC2_UNMUTE_MODE 30 +#define DAC2_MUTE_MODE 29 +#define DAC2_VC_RAMP_MODE 28 +#define DAC2_RAMP_RATE 26 /* bit 27-26 */ +#define DAC2_MONO 24 +#define MUTE_DAC2_PD_EN 23 +#define DAC2_CLK_TO_GPIO_EN 8 +#define DAC2L_DATA_SOURCE 7 +#define DAC2R_DATA_SOURCE 6 +#define DAC2L_INV 5 +#define DAC2R_INV 4 + +// bitfield def of ACODEC_7 +#define DEBUG_BUS_SEL 16 /* bit 16~18 */ +#define REG_DAC2_GAIN_SEL_1 15 +#define REG_DAC2_GAIN_SEL_0 7 + +#endif /*_TL1_ACODEC_H*/