From 6b993d226ce19a39c1642fda59faab940e3042dc Mon Sep 17 00:00:00 2001
From: Huibin Hong <huibin.hong@rock-chips.com>
Date: Tue, 9 Nov 2021 07:14:39 +0000
Subject: [PATCH] arm64: dts: rockchip: fix uart2 console configuration on
 rk3588-android.dtsi

1. Set earlycon base address 0xfeb50000
2. Set fiq_debugger interrupts id 423

Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com>
Change-Id: I4069d5ec5e6633c903a5e84f099c982d87c4ca36
---
 arch/arm64/boot/dts/rockchip/rk3588-android.dtsi | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/rockchip/rk3588-android.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-android.dtsi
index dc96e81d63a3..703383ee5b2a 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588-android.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588-android.dtsi
@@ -6,7 +6,7 @@
 
 / {
 	chosen: chosen {
-		bootargs = "earlycon=uart8250,mmio32,0xfe660000 console=ttyFIQ0";
+		bootargs = "earlycon=uart8250,mmio32,0xfeb50000 console=ttyFIQ0";
 	};
 
 	fiq_debugger: fiq-debugger {
@@ -16,7 +16,7 @@
 		/* If enable uart uses irq instead of fiq */
 		rockchip,irq-mode-enable = <1>;
 		rockchip,baudrate = <1500000>;  /* Only 115200 and 1500000 */
-		interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_LOW>;
+		interrupts = <GIC_SPI 423 IRQ_TYPE_LEVEL_LOW>;
 		pinctrl-names = "default";
 		pinctrl-0 = <&uart2m0_xfer>;
 		status = "okay";