diff --git a/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c b/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c
index bc8c2cb3cd01..0d1c4973a0ed 100644
--- a/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c
+++ b/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c
@@ -264,6 +264,10 @@ static int rockchip_p3phy_probe(struct platform_device *pdev)
 		return -EINVAL;
 	}
 
+	priv->num_clks = devm_clk_bulk_get_all(dev, &priv->clks);
+	if (priv->num_clks < 1)
+		return -ENODEV;
+
 	priv->phy_grf = syscon_regmap_lookup_by_phandle(np, "rockchip,phy-grf");
 	if (IS_ERR(priv->phy_grf)) {
 		dev_err(dev, "failed to find rockchip,phy_grf regmap\n");
@@ -275,6 +279,13 @@ static int rockchip_p3phy_probe(struct platform_device *pdev)
 	if (IS_ERR(priv->pipe_grf))
 		dev_info(dev, "failed to find rockchip,pipe_grf regmap\n");
 
+	/* Configuring grf with clk enabled. */
+	ret = clk_bulk_prepare_enable(priv->num_clks, priv->clks);
+	if (ret) {
+		pr_err("failed to enable PCIe bulk clks %d\n", ret);
+		return ret;
+	}
+
 	ret = device_property_read_u32(dev, "rockchip,pcie30-phymode", &val);
 	if (!ret) {
 		priv->pcie30_phymode = val;
@@ -294,6 +305,8 @@ static int rockchip_p3phy_probe(struct platform_device *pdev)
 				     (reg << 16) | reg);
 	};
 
+	clk_bulk_disable_unprepare(priv->num_clks, priv->clks);
+
 	priv->phy = devm_phy_create(dev, NULL, &rockchip_p3phy_ops);
 	if (IS_ERR(priv->phy)) {
 		dev_err(dev, "failed to create combphy\n");
@@ -306,10 +319,6 @@ static int rockchip_p3phy_probe(struct platform_device *pdev)
 		priv->p30phy = NULL;
 	}
 
-	priv->num_clks = devm_clk_bulk_get_all(dev, &priv->clks);
-	if (priv->num_clks < 1)
-		return -ENODEV;
-
 	dev_set_drvdata(dev, priv);
 	phy_set_drvdata(priv->phy, priv);
 	phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);