From 6c5208b3ef463819bd53558fea470ab8a87cac02 Mon Sep 17 00:00:00 2001 From: Cai Wenzhong Date: Wed, 23 Aug 2023 15:51:16 +0800 Subject: [PATCH] arm64: dts: rockchip: rk3588-vehicle-maxim-cameras-s66: Enable maxim4c driver 1. max96712@0x29: AVM Camera x 4 1.1 i2c bus = 2, csi2_dphy0_hw = full mode (csi2_dphy0) 1.2 max96715 GSML1 LVDS Camera, 1280*800, 30fps 1.3 gpios: pwdn = gpio1_c4, lock = gpio1_c6, errb = gpio1_d2 2. max96722@0x6b: DMS Camera x1 + OMS Camera x1 2.1 i2c bus = 2, csi2_dphy1_hw = full mode (csi2_dphy3) 2.2 max9295a GMSL2 DVP Camera, 1600*1300, 30fps 2.3 gpios: pwdn = gpio1_c7, lock = gpio1_d5, errb = gpio1_b1 Signed-off-by: Cai Wenzhong Change-Id: I1cdf9eb53b695be102e63c6fb329525d8e03c242 --- .../rk3588-vehicle-maxim-cameras-s66.dtsi | 920 +++++++++++++++++- 1 file changed, 889 insertions(+), 31 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-vehicle-maxim-cameras-s66.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-vehicle-maxim-cameras-s66.dtsi index 566c9d00095b..c4fe0cbcf165 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-vehicle-maxim-cameras-s66.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-vehicle-maxim-cameras-s66.dtsi @@ -3,20 +3,21 @@ * Copyright (c) 2023 Rockchip Electronics Co., Ltd. * */ +#include / { - max96712_osc: max96712-oscillator { + max96712_dphy0_osc0: max96712-dphy0-oscillator@0 { compatible = "fixed-clock"; #clock-cells = <1>; clock-frequency = <25000000>; - clock-output-names = "max96712-osc"; + clock-output-names = "max96712-dphy0-osc0"; }; - max96722_osc: max96722-oscillator { + max96722_dphy3_osc0: max96722-dphy3-oscillator@0 { compatible = "fixed-clock"; #clock-cells = <1>; clock-frequency = <25000000>; - clock-output-names = "max96722-osc"; + clock-output-names = "max96722-dphy3-osc0"; }; }; @@ -43,7 +44,7 @@ mipi_dphy0_in_max96712: endpoint@1 { reg = <1>; - remote-endpoint = <&max96712_out>; + remote-endpoint = <&max96712_dphy0_out>; data-lanes = <1 2 3 4>; }; }; @@ -138,7 +139,7 @@ mipi_dphy3_in_max96722: endpoint@1 { reg = <1>; - remote-endpoint = <&max96722_out>; + remote-endpoint = <&max96722_dphy3_out>; data-lanes = <1 2 3 4>; }; }; @@ -231,88 +232,945 @@ clock-frequency = <400000>; // AVM Camera x4 - max96712: max96712@29 { - compatible = "maxim,max96712"; + max96712_dphy0: max96712@29 { + compatible = "maxim4c,max96712"; status = "okay"; reg = <0x29>; clock-names = "xvclk"; - clocks = <&max96712_osc 0>; + clocks = <&max96712_dphy0_osc0 0>; pinctrl-names = "default"; - pinctrl-0 = <&max96712_power>, <&max96712_errb>, <&max96712_lock>; + pinctrl-0 = <&max96712_dphy0_pwdn>, <&max96712_dphy0_errb>, <&max96712_dphy0_lock>; power-domains = <&power RK3588_PD_VI>; rockchip,grf = <&sys_grf>; - power-gpios = <&gpio1 RK_PC4 GPIO_ACTIVE_HIGH>; + pwdn-gpios = <&gpio1 RK_PC4 GPIO_ACTIVE_HIGH>; lock-gpios = <&gpio1 RK_PC6 GPIO_ACTIVE_HIGH>; - link-mask = <0x0F>; - auto-init-deskew-mask = <0x3>; - frame-sync-period = <0>; - link-rx-rate = <0>; + rockchip,camera-module-index = <0>; rockchip,camera-module-facing = "back"; rockchip,camera-module-name = "max96712"; rockchip,camera-module-lens-name = "max96712"; port { - max96712_out: endpoint { + max96712_dphy0_out: endpoint { remote-endpoint = <&mipi_dphy0_in_max96712>; data-lanes = <1 2 3 4>; }; }; + + /* support mode config start */ + support-mode-config { + status = "okay"; + + bus-format = ; + sensor-width = <1280>; + sensor-height = <800>; + max-fps-numerator = <10000>; + max-fps-denominator = <300000>; + bpp = <16>; + link-freq-idx = <20>; + vc-array = <0x10 0x20 0x40 0x80>; // VC0~3: bit4~7 + }; + /* support mode config end */ + + /* serdes local device start */ + serdes-local-device { + status = "okay"; + + /* GMSL LINK config start */ + gmsl-links { + status = "okay"; + + link-vdd-ldo1-en = <1>; + link-vdd-ldo2-en = <1>; + + // Link A: link-id = 0 + gmsl-link-config-0 { + status = "okay"; + link-id = <0>; // Link ID: 0/1/2/3 + + link-type = <0>; + link-rx-rate = <0>; + link-tx-rate = <0>; + + port { + max96712_dphy0_link0_in: endpoint { + remote-endpoint = <&max96712_dphy0_remote0_out>; + }; + }; + + link-init-sequence { + seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1 + reg-addr-len = <2>; // 1: 8bits, 2: 16bits + reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits + + // reg_addr reg_val val_mask delay + init-sequence = [ + 14 D1 03 00 00 // VGAHiGain + 14 45 00 00 00 // Disable SSC + 0B 06 ef 00 00 // HIM on + 0B 07 84 00 00 // Enable HVEN and DBL + 0B 0F 01 00 00 // Disable processing DE signals + ]; + }; + }; + + // Link B: link-id = 1 + gmsl-link-config-1 { + status = "okay"; + link-id = <1>; // Link ID: 0/1/2/3 + + link-type = <0>; + link-rx-rate = <0>; + link-tx-rate = <0>; + + port { + max96712_dphy0_link1_in: endpoint { + remote-endpoint = <&max96712_dphy0_remote1_out>; + }; + }; + + link-init-sequence { + seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1 + reg-addr-len = <2>; // 1: 8bits, 2: 16bits + reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits + + // reg_addr reg_val val_mask delay + init-sequence = [ + 15 D1 03 00 00 // VGAHiGain + 15 45 00 00 00 // Disable SSC + 0C 06 ef 00 00 // HIM on + 0C 07 84 00 00 // Enable HVEN and DBL + 0C 0F 01 00 00 // Disable processing DE signals + ]; + }; + }; + + // Link C: link-id = 2 + gmsl-link-config-2 { + status = "okay"; + link-id = <2>; // Link ID: 0/1/2/3 + + link-type = <0>; + link-rx-rate = <0>; + link-tx-rate = <0>; + + port { + max96712_dphy0_link2_in: endpoint { + remote-endpoint = <&max96712_dphy0_remote2_out>; + }; + }; + + link-init-sequence { + seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1 + reg-addr-len = <2>; // 1: 8bits, 2: 16bits + reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits + + // reg_addr reg_val val_mask delay + init-sequence = [ + 16 D1 03 00 00 // VGAHiGain + 16 45 00 00 00 // Disable SSC + 0D 06 ef 00 00 // HIM on + 0D 07 84 00 00 // Enable HVEN and DBL + 0D 0F 01 00 00 // Disable processing DE signals + ]; + }; + }; + + // Link D: link-id = 3 + gmsl-link-config-3 { + status = "okay"; + link-id = <3>; // Link ID: 0/1/2/3 + + link-type = <0>; + link-rx-rate = <0>; + link-tx-rate = <0>; + + port { + max96712_dphy0_link3_in: endpoint { + remote-endpoint = <&max96712_dphy0_remote3_out>; + }; + }; + + link-init-sequence { + seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1 + reg-addr-len = <2>; // 1: 8bits, 2: 16bits + reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits + + // reg_addr reg_val val_mask delay + init-sequence = [ + 17 D1 03 00 00 // VGAHiGain + 17 45 00 00 00 // Disable SSC + 0E 06 ef 00 00 // HIM on + 0E 07 84 00 00 // Enable HVEN and DBL + 0E 0F 01 00 00 // Disable processing DE signals + ]; + }; + }; + }; + /* GMSL LINK config end */ + + /* VIDEO PIPE config start */ + video-pipes { + status = "okay"; + + // Video Pipe 0 + video-pipe-config-0 { + status = "okay"; + pipe-id = <0>; // Video Pipe ID: 0/1/2/3/4/5/6/7 + + pipe-idx = <0>; // Video Pipe X/Y/Z/U: 0/1/2/3 + link-idx = <0>; // Link A/B/C/D: 0/1/2/3 + + pipe-init-sequence { + seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1 + reg-addr-len = <2>; // 1: 8bits, 2: 16bits + reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits + + // reg_addr reg_val val_mask delay + init-sequence = [ + // Send YUV422, FS, and FE from Video Pipe 0 to Controller 1 + 09 0B 07 00 00 // Enable 0/1/2 SRC/DST Mappings + 09 2D 15 00 00 // SRC/DST 0/1/2 -> CSI2 Controller 1; + // For the following MSB 2 bits = VC, LSB 6 bits = DT + 09 0D 1e 00 00 // SRC0 VC = 0, DT = YUV422 8bit + 09 0E 1e 00 00 // DST0 VC = 0, DT = YUV422 8bit + 09 0F 00 00 00 // SRC1 VC = 0, DT = Frame Start + 09 10 00 00 00 // DST1 VC = 0, DT = Frame Start + 09 11 01 00 00 // SRC2 VC = 0, DT = Frame End + 09 12 01 00 00 // DST2 VC = 0, DT = Frame End + ]; + }; + }; + + // Video Pipe 1 + video-pipe-config-1 { + status = "okay"; + pipe-id = <1>; // Video Pipe 1: pipe-id = 1 + + pipe-idx = <0>; // Video Pipe X/Y/Z/U: 0/1/2/3 + link-idx = <1>; // Link A/B/C/D: 0/1/2/3 + + pipe-init-sequence { + seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1 + reg-addr-len = <2>; // 1: 8bits, 2: 16bits + reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits + + // reg_addr reg_val val_mask delay + init-sequence = [ + // Send YUV422, FS, and FE from Video Pipe 1 to Controller 1 + 09 4B 07 00 00 // Enable 0/1/2 SRC/DST Mappings + 09 6D 15 00 00 // SRC/DST 0/1/2 -> CSI2 Controller 1; + // For the following MSB 2 bits = VC, LSB 6 bits = DT + 09 4D 1e 00 00 // SRC0 VC = 0, DT = YUV422 8bit + 09 4E 5e 00 00 // DST0 VC = 1, DT = YUV422 8bit + 09 4F 00 00 00 // SRC1 VC = 0, DT = Frame Start + 09 50 40 00 00 // DST1 VC = 1, DT = Frame Start + 09 51 01 00 00 // SRC2 VC = 0, DT = Frame End + 09 52 41 00 00 // DST2 VC = 1, DT = Frame End + ]; + }; + }; + + // Video Pipe 2 + video-pipe-config-2 { + status = "okay"; + pipe-id = <2>; // Video Pipe ID: 0/1/2/3/4/5/6/7 + + pipe-idx = <0>; // Video Pipe X/Y/Z/U: 0/1/2/3 + link-idx = <2>; // Link A/B/C/D: 0/1/2/3 + + pipe-init-sequence { + seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1 + reg-addr-len = <2>; // 1: 8bits, 2: 16bits + reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits + + // reg_addr reg_val val_mask delay + init-sequence = [ + // Send YUV422, FS, and FE from Video Pipe 2 to Controller 1 + 09 8B 07 00 00 // Enable 0/1/2 SRC/DST Mappings + 09 AD 15 00 00 // SRC/DST 0/1/2 -> CSI2 Controller 1; + // For the following MSB 2 bits = VC, LSB 6 bits = DT + 09 8D 1e 00 00 // SRC0 VC = 0, DT = YUV422 8bit + 09 8E 9e 00 00 // DST0 VC = 2, DT = YUV422 8bit + 09 8F 00 00 00 // SRC1 VC = 0, DT = Frame Start + 09 90 80 00 00 // DST1 VC = 2, DT = Frame Start + 09 91 01 00 00 // SRC2 VC = 0, DT = Frame End + 09 92 81 00 00 // DST2 VC = 2, DT = Frame End + ]; + }; + }; + + // Video Pipe 3 + video-pipe-config-3 { + status = "okay"; + pipe-id = <3>; // Video Pipe ID: 0/1/2/3/4/5/6/7 + + pipe-idx = <0>; // Video Pipe X/Y/Z/U: 0/1/2/3 + link-idx = <3>; // Link A/B/C/D: 0/1/2/3 + + pipe-init-sequence { + seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1 + reg-addr-len = <2>; // 1: 8bits, 2: 16bits + reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits + + // reg_addr reg_val val_mask delay + init-sequence = [ + // Send YUV422, FS, and FE from Video Pipe 3 to Controller 1 + 09 CB 07 00 00 // Enable 0/1/2 SRC/DST Mappings + 09 ED 15 00 00 // SRC/DST 0/1/2 -> CSI2 Controller 1; + // For the following MSB 2 bits = VC, LSB 6 bits = DT + 09 CD 1e 00 00 // SRC0 VC = 0, DT = YUV422 8bit + 09 CE de 00 00 // DST0 VC = 3, DT = YUV422 8bit + 09 CF 00 00 00 // SRC1 VC = 0, DT = Frame Start + 09 D0 c0 00 00 // DST1 VC = 3, DT = Frame Start + 09 D1 01 00 00 // SRC2 VC = 0, DT = Frame End + 09 D2 c1 00 00 // DST2 VC = 3, DT = Frame End + ]; + }; + }; + + // Software override for parallel mode + parallel-mode-config { + status = "okay"; + + parallel-init-sequence { + seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1 + reg-addr-len = <2>; // 1: 8bits, 2: 16bits + reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits + + // reg_addr reg_val val_mask delay + init-sequence = [ + // Enable software override for all pipes since GMSL1 data is parallel mode, bpp=8, dt=0x1e(yuv-8) + 04 1A f0 00 00 // pipe 0/1/2/3: Enable YUV8-/10-bit mux mode + 04 0B 40 00 00 // pipe 0 bpp=0x08: Datatypes = 0x2A, 0x10-12, 0x31-37 + 04 0C 00 00 00 // pipe 0 and 1 VC software override: 0x00 + 04 0D 00 00 00 // pipe 2 and 3 VC software override: 0x00 + 04 0E 5e 00 00 // pipe 0 DT=0x1E: YUV422 8-bit + 04 0F 7e 00 00 // pipe 1 DT=0x1E: YUV422 8-bit + 04 10 7a 00 00 // pipe 2 DT=0x1E, pipe 3 DT=0x1E: YUV422 8-bit + 04 11 48 00 00 // pipe 1 bpp=0x08: Datatypes = 0x2A, 0x10-12, 0x31-37 + 04 12 20 00 00 // pipe 2 bpp=0x08, pipe 3 bpp=0x08: Datatypes = 0x2A, 0x10-12, 0x31-37 + 04 15 c0 c0 00 // pipe 0/1 enable software overide + 04 18 c0 c0 00 // pipe 2/3 enable software overide + ]; + }; + }; + }; + /* VIDEO PIPE config end */ + + /* MIPI TXPHY config start */ + mipi-txphys { + status = "okay"; + + phy-mode = <0>; + phy-force-clock-out = <1>; + phy-force-clk0-en = <0>; + phy-force-clk3-en = <0>; + + // MIPI TXPHY A: phy-id = 0 + mipi-txphy-config-0 { + status = "okay"; + phy-id = <0>; // MIPI TXPHY ID: 0/1/2/3 + + phy-type = <0>; + auto-deskew = <0x80>; + data-lane-num = <4>; + data-lane-map = <0x4>; + vc-ext-en = <0>; + }; + + // MIPI TXPHY B: phy-id = 1 + mipi-txphy-config-1 { + status = "okay"; + phy-id = <1>; // MIPI TXPHY ID: 0/1/2/3 + + phy-type = <0>; + auto-deskew = <0x80>; + data-lane-num = <4>; + data-lane-map = <0xe>; + vc-ext-en = <0>; + }; + }; + /* MIPI TXPHY config end */ + + /* local device extra init sequence */ + extra-init-sequence { + status = "disabled"; + + seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1 + reg-addr-len = <2>; // 1: 8bits, 2: 16bits + reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits + + // reg_addr reg_val val_mask delay + init-sequence = [ + // common init sequence such as fsync / gpio and so on + ]; + }; + }; + /* serdes local device end */ + + /* serdes remote device start */ + serdes-remote-device-0 { + compatible = "maxim4c,link0,max96715"; + status = "okay"; + + remote-id = <0>; // Same as Link ID: 0/1/2/3 + + // Serializer i2c 7bit address remap + ser-i2c-addr-def = <0x40>; + ser-i2c-addr-map = <0x41>; // 0: disable remap + + port { + max96712_dphy0_remote0_out: endpoint { + remote-endpoint = <&max96712_dphy0_link0_in>; + }; + }; + + remote-init-sequence { + seq-item-size = <4>; // reg-addr-len + reg-val-len * 2 + 1 + reg-addr-len = <1>; // 1: 8bits, 2: 16bits + reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits + + // reg_addr reg_val val_mask delay + init-sequence = [ + 07 84 00 00 + 67 c4 00 00 + 0F bf 00 00 + 3F 08 00 00 + 40 2d 00 00 + 20 10 00 00 + 21 11 00 00 + 22 12 00 00 + 23 13 00 00 + 24 14 00 00 + 25 15 00 00 + 26 16 00 00 + 27 17 00 00 + 30 00 00 00 + 31 01 00 00 + 32 02 00 00 + 33 03 00 00 + 34 04 00 00 + 35 05 00 00 + 36 06 00 00 + 37 07 00 00 + ]; + }; + }; + + serdes-remote-device-1 { + compatible = "maxim4c,link1,max96715"; + status = "okay"; + + remote-id = <1>; // Same as Link ID: 0/1/2/3 + + // Serializer i2c 7bit address remap + ser-i2c-addr-def = <0x40>; + ser-i2c-addr-map = <0x42>; // 0: disable remap + + port { + max96712_dphy0_remote1_out: endpoint { + remote-endpoint = <&max96712_dphy0_link1_in>; + }; + }; + + remote-init-sequence { + seq-item-size = <4>; // reg-addr-len + reg-val-len * 2 + 1 + reg-addr-len = <1>; // 1: 8bits, 2: 16bits + reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits + + // reg_addr reg_val val_mask delay + init-sequence = [ + 07 84 00 00 + 67 c4 00 00 + 0F bf 00 00 + 3F 08 00 00 + 40 2d 00 00 + 20 10 00 00 + 21 11 00 00 + 22 12 00 00 + 23 13 00 00 + 24 14 00 00 + 25 15 00 00 + 26 16 00 00 + 27 17 00 00 + 30 00 00 00 + 31 01 00 00 + 32 02 00 00 + 33 03 00 00 + 34 04 00 00 + 35 05 00 00 + 36 06 00 00 + 37 07 00 00 + ]; + }; + }; + + serdes-remote-device-2 { + compatible = "maxim4c,link2,max96715"; + status = "okay"; + + remote-id = <2>; // Same as Link ID: 0/1/2/3 + + // Serializer i2c 7bit address remap + ser-i2c-addr-def = <0x40>; + ser-i2c-addr-map = <0x43>; // 0: disable remap + + port { + max96712_dphy0_remote2_out: endpoint { + remote-endpoint = <&max96712_dphy0_link2_in>; + }; + }; + + remote-init-sequence { + seq-item-size = <4>; // reg-addr-len + reg-val-len * 2 + 1 + reg-addr-len = <1>; // 1: 8bits, 2: 16bits + reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits + + // reg_addr reg_val val_mask delay + init-sequence = [ + 07 84 00 00 + 67 c4 00 00 + 0F bf 00 00 + 3F 08 00 00 + 40 2d 00 00 + 20 10 00 00 + 21 11 00 00 + 22 12 00 00 + 23 13 00 00 + 24 14 00 00 + 25 15 00 00 + 26 16 00 00 + 27 17 00 00 + 30 00 00 00 + 31 01 00 00 + 32 02 00 00 + 33 03 00 00 + 34 04 00 00 + 35 05 00 00 + 36 06 00 00 + 37 07 00 00 + ]; + }; + }; + + serdes-remote-device-3 { + compatible = "maxim4c,link3,max96715"; + status = "okay"; + + remote-id = <3>; // Same as Link ID: 0/1/2/3 + + // Serializer i2c 7bit address remap + ser-i2c-addr-def = <0x40>; + ser-i2c-addr-map = <0x44>; // 0: disable remap + + port { + max96712_dphy0_remote3_out: endpoint { + remote-endpoint = <&max96712_dphy0_link3_in>; + }; + }; + + remote-init-sequence { + seq-item-size = <4>; // reg-addr-len + reg-val-len * 2 + 1 + reg-addr-len = <1>; // 1: 8bits, 2: 16bits + reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits + + // reg_addr reg_val val_mask delay + init-sequence = [ + 07 84 00 00 + 67 c4 00 00 + 0F bf 00 00 + 3F 08 00 00 + 40 2d 00 00 + 20 10 00 00 + 21 11 00 00 + 22 12 00 00 + 23 13 00 00 + 24 14 00 00 + 25 15 00 00 + 26 16 00 00 + 27 17 00 00 + 30 00 00 00 + 31 01 00 00 + 32 02 00 00 + 33 03 00 00 + 34 04 00 00 + 35 05 00 00 + 36 06 00 00 + 37 07 00 00 + ]; + }; + }; + /* serdes remote device end */ }; // DMS Camera x1 + OMS Camera x3 - max96722: max96722@6b { - compatible = "maxim,max96722"; + max96722_dphy3: max96722@6b { + compatible = "maxim4c,max96722"; status = "okay"; reg = <0x6b>; clock-names = "xvclk"; - clocks = <&max96722_osc 0>; + clocks = <&max96722_dphy3_osc0 0>; pinctrl-names = "default"; - pinctrl-0 = <&max96722_power>, <&max96722_errb>, <&max96722_lock>; + pinctrl-0 = <&max96722_dphy3_pwdn>, <&max96722_dphy3_errb>, <&max96722_dphy3_lock>; power-domains = <&power RK3588_PD_VI>; rockchip,grf = <&sys_grf>; - power-gpios = <&gpio1 RK_PC7 GPIO_ACTIVE_HIGH>; + pwdn-gpios = <&gpio1 RK_PC7 GPIO_ACTIVE_HIGH>; lock-gpios = <&gpio1 RK_PD5 GPIO_ACTIVE_HIGH>; - link-mask = <0x33>; - auto-init-deskew-mask = <0x3>; - frame-sync-period = <0>; + rockchip,camera-module-index = <0>; rockchip,camera-module-facing = "back"; rockchip,camera-module-name = "max96722"; rockchip,camera-module-lens-name = "max96722"; port { - max96722_out: endpoint { + max96722_dphy3_out: endpoint { remote-endpoint = <&mipi_dphy3_in_max96722>; data-lanes = <1 2 3 4>; }; }; + + /* support mode config start */ + support-mode-config { + status = "okay"; + + bus-format = ; + sensor-width = <1600>; + sensor-height = <1300>; + max-fps-numerator = <10000>; + max-fps-denominator = <300000>; + bpp = <16>; + link-freq-idx = <20>; + vc-array = <0x10 0x20 0x40 0x80>; // VC0~3: bit4~7 + }; + /* support mode config end */ + + /* serdes local device start */ + serdes-local-device { + status = "okay"; + + /* GMSL LINK config start */ + gmsl-links { + status = "okay"; + + link-vdd-ldo1-en = <1>; + link-vdd-ldo2-en = <1>; + + // Link A: link-id = 0 + gmsl-link-config-0 { + status = "okay"; + link-id = <0>; // Link ID: 0/1/2/3 + + link-type = <1>; + link-rx-rate = <0>; + link-tx-rate = <0>; + + port { + max96722_dphy3_link0_in: endpoint { + remote-endpoint = <&max96722_dphy3_remote0_out>; + }; + }; + + link-init-sequence { + seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1 + reg-addr-len = <2>; // 1: 8bits, 2: 16bits + reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits + + // reg_addr reg_val val_mask delay + init-sequence = [ + 14 D1 03 00 00 // VGAHiGain + 14 45 00 00 00 // Disable SSC + ]; + }; + }; + + // Link B: link-id = 1 + gmsl-link-config-1 { + status = "okay"; + link-id = <1>; // Link ID: 0/1/2/3 + + link-type = <1>; + link-rx-rate = <0>; + link-tx-rate = <0>; + + port { + max96722_dphy3_link1_in: endpoint { + remote-endpoint = <&max96722_dphy3_remote1_out>; + }; + }; + + link-init-sequence { + seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1 + reg-addr-len = <2>; // 1: 8bits, 2: 16bits + reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits + + // reg_addr reg_val val_mask delay + init-sequence = [ + 15 D1 03 00 00 // VGAHiGain + 15 45 00 00 00 // Disable SSC + ]; + }; + }; + }; + /* GMSL LINK config end */ + + /* VIDEO PIPE config start */ + video-pipes { + status = "okay"; + + // Video Pipe 0 + video-pipe-config-0 { + status = "okay"; + pipe-id = <0>; // Video Pipe ID: 0/1/2/3/4/5/6/7 + + pipe-idx = <0>; // Video Pipe X/Y/Z/U: 0/1/2/3 + link-idx = <0>; // Link A/B/C/D: 0/1/2/3 + + pipe-init-sequence { + seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1 + reg-addr-len = <2>; // 1: 8bits, 2: 16bits + reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits + + // reg_addr reg_val val_mask delay + init-sequence = [ + // Send YUV422, FS, and FE from Video Pipe 0 to Controller 1 + 09 0B 07 00 00 // Enable 0/1/2 SRC/DST Mappings + 09 2D 15 00 00 // SRC/DST 0/1/2 -> CSI2 Controller 1; + // For the following MSB 2 bits = VC, LSB 6 bits = DT + 09 0D 1e 00 00 // SRC0 VC = 0, DT = YUV422 8bit + 09 0E 1e 00 00 // DST0 VC = 0, DT = YUV422 8bit + 09 0F 00 00 00 // SRC1 VC = 0, DT = Frame Start + 09 10 00 00 00 // DST1 VC = 0, DT = Frame Start + 09 11 01 00 00 // SRC2 VC = 0, DT = Frame End + 09 12 01 00 00 // DST2 VC = 0, DT = Frame End + // pipe Cross + 01 D9 59 00 00 // pipe 0: Inverts Cross VS + ]; + }; + }; + + // Video Pipe 1 + video-pipe-config-1 { + status = "okay"; + pipe-id = <1>; // Video Pipe 1: pipe-id = 1 + + pipe-idx = <0>; // Video Pipe X/Y/Z/U: 0/1/2/3 + link-idx = <1>; // Link A/B/C/D: 0/1/2/3 + + pipe-init-sequence { + seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1 + reg-addr-len = <2>; // 1: 8bits, 2: 16bits + reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits + + // reg_addr reg_val val_mask delay + init-sequence = [ + // Send YUV422, FS, and FE from Video Pipe 1 to Controller 1 + 09 4B 07 00 00 // Enable 0/1/2 SRC/DST Mappings + 09 6D 15 00 00 // SRC/DST 0/1/2 -> CSI2 Controller 1; + // For the following MSB 2 bits = VC, LSB 6 bits = DT + 09 4D 1e 00 00 // SRC0 VC = 0, DT = YUV422 8bit + 09 4E 5e 00 00 // DST0 VC = 1, DT = YUV422 8bit + 09 4F 00 00 00 // SRC1 VC = 0, DT = Frame Start + 09 50 40 00 00 // DST1 VC = 1, DT = Frame Start + 09 51 01 00 00 // SRC2 VC = 0, DT = Frame End + 09 52 41 00 00 // DST2 VC = 1, DT = Frame End + // pipe Cross + 01 F9 59 00 00 // pipe 1: Inverts Cross VS + ]; + }; + }; + + // Software override for parallel mode + parallel-mode-config { + status = "okay"; + + parallel-init-sequence { + seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1 + reg-addr-len = <2>; // 1: 8bits, 2: 16bits + reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits + + // reg_addr reg_val val_mask delay + init-sequence = [ + // Enable software override for all pipes since GMSL1 data is parallel mode, bpp=8, dt=0x1e(yuv-8) + 04 1A f0 00 00 // pipe 0/1/2/3: Enable YUV8-/10-bit mux mode + 04 0B 40 00 00 // pipe 0 bpp=0x08: Datatypes = 0x2A, 0x10-12, 0x31-37 + 04 0C 00 00 00 // pipe 0 and 1 VC software override: 0x00 + 04 0D 00 00 00 // pipe 2 and 3 VC software override: 0x00 + 04 0E 5e 00 00 // pipe 0 DT=0x1E: YUV422 8-bit + 04 0F 7e 00 00 // pipe 1 DT=0x1E: YUV422 8-bit + 04 10 7a 00 00 // pipe 2 DT=0x1E, pipe 3 DT=0x1E: YUV422 8-bit + 04 11 48 00 00 // pipe 1 bpp=0x08: Datatypes = 0x2A, 0x10-12, 0x31-37 + 04 12 20 00 00 // pipe 2 bpp=0x08, pipe 3 bpp=0x08: Datatypes = 0x2A, 0x10-12, 0x31-37 + 04 15 c0 c0 00 // pipe 0/1 enable software overide + 04 18 c0 c0 00 // pipe 2/3 enable software overide + ]; + }; + }; + }; + /* VIDEO PIPE config end */ + + /* MIPI TXPHY config start */ + mipi-txphys { + status = "okay"; + + phy-mode = <0>; + phy-force-clock-out = <1>; + phy-force-clk0-en = <0>; + phy-force-clk3-en = <0>; + + // MIPI TXPHY A: phy-id = 0 + mipi-txphy-config-0 { + status = "okay"; + phy-id = <0>; // MIPI TXPHY ID: 0/1/2/3 + + phy-type = <0>; + auto-deskew = <0x80>; + data-lane-num = <4>; + data-lane-map = <0x4>; + vc-ext-en = <0>; + }; + + // MIPI TXPHY B: phy-id = 1 + mipi-txphy-config-1 { + status = "okay"; + phy-id = <1>; // MIPI TXPHY ID: 0/1/2/3 + + phy-type = <0>; + auto-deskew = <0x80>; + data-lane-num = <4>; + data-lane-map = <0xe>; + vc-ext-en = <0>; + }; + }; + /* MIPI TXPHY config end */ + + /* local device extra init sequence */ + extra-init-sequence { + status = "disabled"; + + seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1 + reg-addr-len = <2>; // 1: 8bits, 2: 16bits + reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits + + // reg_addr reg_val val_mask delay + init-sequence = [ + // common init sequence such as fsync / gpio and so on + ]; + }; + }; + /* serdes local device end */ + + /* serdes remote device start */ + serdes-remote-device-0 { + compatible = "maxim4c,link0,max9295"; + status = "okay"; + + remote-id = <0>; // Same as Link ID: 0/1/2/3 + + // Serializer i2c 7bit address remap + ser-i2c-addr-def = <0x40>; + ser-i2c-addr-map = <0x45>; // 0: disable remap + + port { + max96722_dphy3_remote0_out: endpoint { + remote-endpoint = <&max96722_dphy3_link0_in>; + }; + }; + + remote-init-sequence { + seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1 + reg-addr-len = <2>; // 1: 8bits, 2: 16bits + reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits + + // reg_addr reg_val val_mask delay + init-sequence = [ + 00 01 04 00 00 // RX_RATE: 187.5Mbps, TX_RATE: 3Gbps + 00 11 03 00 00 // Coax Drive + 02 D6 03 00 00 // MFP8: GPIO_OUT_DIS = 1, GPIO_TX_EN = 1 + 03 F0 51 00 00 // RCLK: 27MHz/24MHz (ALT),Enable reference-generation PLL, Enable pre-defined clock setting for reference-generation PLL + 00 03 07 00 00 // RCLK: Enable RCLK output from altermative MFP pin, RCLKOUT clock select reference PLL + 00 06 b1 00 00 // RCLK: GMSL2, Enable RCLK output, i2c selected + 02 C1 10 00 00 // MFP1: GPIO_OUT pin output is driven to 1 when GPIO_RX_EN = 0 + 02 C2 60 00 00 // MFP1: OUT_TYPE = 1: Push-pull, PULL_UPDN_SEL[1:0] = 0b01: Pullup + 00 07 07 00 00 // Enable Parallel video input, Parallel HS and VS Enable + 00 10 05 00 00 // AUTO_LINK = 0, LINK_CFG = 1: LinkA is selected, REG_ENABLE = 1: Regulator enabled + 00 12 14 00 00 // REG_MNL = 1: Enable LDO on/off state controlled by REG_ENABLE + 01 00 62 00 00 // Video X, Line CRC enabled, ENC_MODE = 2: HS, VS, DE encoding on, color bits sent only when DE is high + 01 01 50 00 00 // Video X, BPP = 0x10 + 00 53 10 00 00 // Video X, TX_STR_SEL = 0: Stream ID = 0 for packets from this channel + 00 02 13 00 00 // Video transmit enable for Port X + ]; + }; + }; + + serdes-remote-device-1 { + compatible = "maxim4c,link1,max9295"; + status = "okay"; + + remote-id = <1>; // Same as Link ID: 0/1/2/3 + + // Serializer i2c 7bit address remap + ser-i2c-addr-def = <0x40>; + ser-i2c-addr-map = <0x46>; // 0: disable remap + + port { + max96722_dphy3_remote1_out: endpoint { + remote-endpoint = <&max96722_dphy3_link1_in>; + }; + }; + + remote-init-sequence { + seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1 + reg-addr-len = <2>; // 1: 8bits, 2: 16bits + reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits + + // reg_addr reg_val val_mask delay + init-sequence = [ + 00 01 04 00 00 // RX_RATE: 187.5Mbps, TX_RATE: 3Gbps + 00 11 03 00 00 // Coax Drive + 02 D6 03 00 00 // MFP8: GPIO_OUT_DIS = 1, GPIO_TX_EN = 1 + 03 F0 51 00 00 // RCLK: 27MHz/24MHz (ALT),Enable reference-generation PLL, Enable pre-defined clock setting for reference-generation PLL + 00 03 07 00 00 // RCLK: Enable RCLK output from altermative MFP pin, RCLKOUT clock select reference PLL + 00 06 b1 00 00 // RCLK: GMSL2, Enable RCLK output, i2c selected + 02 C1 10 00 00 // MFP1: GPIO_OUT pin output is driven to 1 when GPIO_RX_EN = 0 + 02 C2 60 00 00 // MFP1: OUT_TYPE = 1: Push-pull, PULL_UPDN_SEL[1:0] = 0b01: Pullup + 00 07 07 00 00 // Enable Parallel video input, Parallel HS and VS Enable + 00 10 05 00 00 // AUTO_LINK = 0, LINK_CFG = 1: LinkA is selected, REG_ENABLE = 1: Regulator enabled + 00 12 14 00 00 // REG_MNL = 1: Enable LDO on/off state controlled by REG_ENABLE + 01 00 62 00 00 // Video X, Line CRC enabled, ENC_MODE = 2: HS, VS, DE encoding on, color bits sent only when DE is high + 01 01 50 00 00 // Video X, BPP = 0x10 + 00 53 10 00 00 // Video X, TX_STR_SEL = 0: Stream ID = 0 for packets from this channel + 00 02 13 00 00 // Video transmit enable for Port X + ]; + }; + }; + /* serdes remote device end */ }; }; &pinctrl { maxim-cameras { - max96712_power: max96712-power { + max96712_dphy0_pwdn: max96712-dphy0-pwdn { rockchip,pins = <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up>; }; - max96712_errb: max96712-errb { + max96712_dphy0_errb: max96712-dphy0-errb { rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_up>; }; - max96712_lock: max96712-lock { + max96712_dphy0_lock: max96712-dphy0-lock { rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>; }; - max96722_power: max96722-power { + max96722_dphy3_pwdn: max96722-dphy3-pwdn { rockchip,pins = <1 RK_PC7 RK_FUNC_GPIO &pcfg_pull_up>; }; - max96722_errb: max96722-errb { + max96722_dphy3_errb: max96722-dphy3-errb { rockchip,pins = <1 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>; }; - max96722_lock: max96722-lock { + max96722_dphy3_lock: max96722-dphy3-lock { rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_up>; }; };