From 25a62f4a64e2be4d57ba465b82cbb87b00c09bd0 Mon Sep 17 00:00:00 2001 From: Liviu Dudau Date: Fri, 29 Jun 2012 17:50:14 +0100 Subject: [PATCH 1/5] ARM: vexpress: Add proper DT support for the dual cluster V2P-CA15_CA7 CoreTile Signed-off-by: Liviu Dudau Signed-off-by: Jon Medhurst --- arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts | 80 ++++++++++++++++++++++ 1 file changed, 80 insertions(+) diff --git a/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts b/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts index d2803be4e1a8..af457d15255e 100644 --- a/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts +++ b/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts @@ -29,6 +29,48 @@ i2c1 = &v2m_i2c_pcie; }; + clusters { + #address-cells = <1>; + #size-cells = <0>; + + cluster0: cluster@0 { + reg = <0>; + cores { + #address-cells = <1>; + #size-cells = <0>; + + core0: core@0 { + reg = <0>; + }; + + core1: core@1 { + reg = <1>; + }; + + }; + }; + + cluster1: cluster@1 { + reg = <1>; + cores { + #address-cells = <1>; + #size-cells = <0>; + + core2: core@0 { + reg = <0>; + }; + + core3: core@1 { + reg = <1>; + }; + + core4: core@2 { + reg = <2>; + }; + }; + }; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -37,30 +79,40 @@ device_type = "cpu"; compatible = "arm,cortex-a15"; reg = <0>; + cluster = <&cluster0>; + core = <&core0>; }; cpu1: cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a15"; reg = <1>; + cluster = <&cluster0>; + core = <&core1>; }; cpu2: cpu@2 { device_type = "cpu"; compatible = "arm,cortex-a7"; reg = <0x100>; + cluster = <&cluster1>; + core = <&core2>; }; cpu3: cpu@3 { device_type = "cpu"; compatible = "arm,cortex-a7"; reg = <0x101>; + cluster = <&cluster1>; + core = <&core3>; }; cpu4: cpu@4 { device_type = "cpu"; compatible = "arm,cortex-a7"; reg = <0x102>; + cluster = <&cluster1>; + core = <&core4>; }; }; @@ -102,6 +154,34 @@ <0 0x2c004000 0 0x2000>, <0 0x2c006000 0 0x2000>; interrupts = <1 9 0xf04>; + + gic-cpuif@0 { + compatible = "arm,gic-cpuif"; + cpuif-id = <0>; + cpu = <&cpu0>; + }; + gic-cpuif@1 { + compatible = "arm,gic-cpuif"; + cpuif-id = <1>; + cpu = <&cpu1>; + }; + gic-cpuif@2 { + compatible = "arm,gic-cpuif"; + cpuif-id = <2>; + cpu = <&cpu2>; + }; + + gic-cpuif@3 { + compatible = "arm,gic-cpuif"; + cpuif-id = <3>; + cpu = <&cpu3>; + }; + + gic-cpuif@4 { + compatible = "arm,gic-cpuif"; + cpuif-id = <4>; + cpu = <&cpu4>; + }; }; memory-controller@7ffd0000 { From fa945c17bfc3068c0ca2e66c9dc47497a357d327 Mon Sep 17 00:00:00 2001 From: Jon Medhurst Date: Tue, 26 Mar 2013 13:04:51 +0000 Subject: [PATCH 2/5] ARM: vexpress: Update TC2 memory to 2GB All TC2 boards 'in the wild' will have 2GB of memory, so lets make it all available. Signed-off-by: Jon Medhurst --- arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts b/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts index af457d15255e..2e720e976599 100644 --- a/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts +++ b/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts @@ -118,7 +118,7 @@ memory@80000000 { device_type = "memory"; - reg = <0 0x80000000 0 0x40000000>; + reg = <0 0x80000000 0 0x80000000>; }; wdt@2a490000 { From 8f15973ef8c3c3c71bfb0f69670827e0d1882042 Mon Sep 17 00:00:00 2001 From: Jon Medhurst Date: Tue, 26 Mar 2013 13:06:53 +0000 Subject: [PATCH 3/5] ARM: vexpress: Add CPU clock-frequencies to TC2 device-tree Signed-off-by: Jon Medhurst --- arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts b/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts index 2e720e976599..9e93597dd530 100644 --- a/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts +++ b/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts @@ -81,6 +81,7 @@ reg = <0>; cluster = <&cluster0>; core = <&core0>; + clock-frequency = <1000000000>; }; cpu1: cpu@1 { @@ -89,6 +90,7 @@ reg = <1>; cluster = <&cluster0>; core = <&core1>; + clock-frequency = <1000000000>; }; cpu2: cpu@2 { @@ -97,6 +99,7 @@ reg = <0x100>; cluster = <&cluster1>; core = <&core2>; + clock-frequency = <800000000>; }; cpu3: cpu@3 { @@ -105,6 +108,7 @@ reg = <0x101>; cluster = <&cluster1>; core = <&core3>; + clock-frequency = <800000000>; }; cpu4: cpu@4 { @@ -113,6 +117,7 @@ reg = <0x102>; cluster = <&cluster1>; core = <&core4>; + clock-frequency = <800000000>; }; }; From 40bb83f11c5881d8455866458522816397dd5836 Mon Sep 17 00:00:00 2001 From: Sudeep KarkadaNagesha Date: Mon, 16 Jul 2012 12:29:43 +0000 Subject: [PATCH 4/5] ARM: vexpress: update TC2 dts to support multiple PMUs This patch adds support for both A15 and A7 PMUs on vexpress TC2 Signed-off-by: Sudeep KarkadaNagesha --- arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts b/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts index 9e93597dd530..446708869c7a 100644 --- a/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts +++ b/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts @@ -218,12 +218,21 @@ <1 10 0xf08>; }; - pmu { + pmu_a15 { compatible = "arm,cortex-a15-pmu"; + cluster = <&cluster0>; interrupts = <0 68 4>, <0 69 4>; }; + pmu_a7 { + compatible = "arm,cortex-a7-pmu"; + cluster = <&cluster1>; + interrupts = <0 128 4>, + <0 129 4>, + <0 130 4>; + }; + oscclk6a: oscclk6a { /* Reference 24MHz clock */ compatible = "fixed-clock"; From 17b821ed0e31bfb55037b124f5c89aad1521ca1d Mon Sep 17 00:00:00 2001 From: Vincent Guittot Date: Fri, 17 May 2013 11:20:19 +0200 Subject: [PATCH 5/5] ARM: bL boot on A7 cluster Ensure that A7 cluster will be mapped on CPU0-2 Suggested-by: Chris Redpath Signed-off-by: Vincent Guittot --- arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts | 37 +++++++++++----------- 1 file changed, 19 insertions(+), 18 deletions(-) diff --git a/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts b/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts index 446708869c7a..f6b4e8471cb6 100644 --- a/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts +++ b/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts @@ -75,24 +75,6 @@ #address-cells = <1>; #size-cells = <0>; - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0>; - cluster = <&cluster0>; - core = <&core0>; - clock-frequency = <1000000000>; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <1>; - cluster = <&cluster0>; - core = <&core1>; - clock-frequency = <1000000000>; - }; - cpu2: cpu@2 { device_type = "cpu"; compatible = "arm,cortex-a7"; @@ -119,6 +101,25 @@ core = <&core4>; clock-frequency = <800000000>; }; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0>; + cluster = <&cluster0>; + core = <&core0>; + clock-frequency = <1000000000>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <1>; + cluster = <&cluster0>; + core = <&core1>; + clock-frequency = <1000000000>; + }; + }; memory@80000000 {