From 6c7d5bdf7b1ddc01d5ba61cf76edccdb4a93e932 Mon Sep 17 00:00:00 2001 From: Sugar Zhang Date: Fri, 2 Sep 2022 15:58:28 +0800 Subject: [PATCH] ASoC: rockchip: spdif: Add support for format S32_LE Treat 32 bit sample width as if it was 24 bits using only the 24 most significant bits. Signed-off-by: Sugar Zhang Change-Id: Ica236069b6f0ccfa8635cd89bf11dc59bc054d8d --- sound/soc/rockchip/rockchip_spdif.c | 11 +++++++++-- sound/soc/rockchip/rockchip_spdif.h | 4 ++++ 2 files changed, 13 insertions(+), 2 deletions(-) diff --git a/sound/soc/rockchip/rockchip_spdif.c b/sound/soc/rockchip/rockchip_spdif.c index 83878933aee1..d87466c23259 100644 --- a/sound/soc/rockchip/rockchip_spdif.c +++ b/sound/soc/rockchip/rockchip_spdif.c @@ -160,6 +160,11 @@ static int rk_spdif_hw_params(struct snd_pcm_substream *substream, break; case SNDRV_PCM_FORMAT_S24_LE: val |= SPDIF_CFGR_VDW_24; + val |= SPDIF_CFGR_ADJ_RIGHT_J; + break; + case SNDRV_PCM_FORMAT_S32_LE: + val |= SPDIF_CFGR_VDW_24; + val |= SPDIF_CFGR_ADJ_LEFT_J; break; default: return -EINVAL; @@ -168,7 +173,8 @@ static int rk_spdif_hw_params(struct snd_pcm_substream *substream, ret = regmap_update_bits(spdif->regmap, SPDIF_CFGR, SPDIF_CFGR_CLK_DIV_MASK | SPDIF_CFGR_HALFWORD_ENABLE | - SDPIF_CFGR_VDW_MASK, val); + SDPIF_CFGR_VDW_MASK | + SPDIF_CFGR_ADJ_MASK, val); return ret; } @@ -262,7 +268,8 @@ static struct snd_soc_dai_driver rk_spdif_dai = { SNDRV_PCM_RATE_192000), .formats = (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | - SNDRV_PCM_FMTBIT_S24_LE), + SNDRV_PCM_FMTBIT_S24_LE | + SNDRV_PCM_FMTBIT_S32_LE), }, .ops = &rk_spdif_dai_ops, }; diff --git a/sound/soc/rockchip/rockchip_spdif.h b/sound/soc/rockchip/rockchip_spdif.h index 1dbac8719cb2..8d4bec97e017 100644 --- a/sound/soc/rockchip/rockchip_spdif.h +++ b/sound/soc/rockchip/rockchip_spdif.h @@ -21,6 +21,10 @@ #define SPDIF_CFGR_CSE_EN BIT(6) #define SPDIF_CFGR_CSE_DIS 0 +#define SPDIF_CFGR_ADJ_MASK BIT(3) +#define SPDIF_CFGR_ADJ_LEFT_J BIT(3) +#define SPDIF_CFGR_ADJ_RIGHT_J 0 + #define SPDIF_CFGR_HALFWORD_SHIFT 2 #define SPDIF_CFGR_HALFWORD_DISABLE (0 << SPDIF_CFGR_HALFWORD_SHIFT) #define SPDIF_CFGR_HALFWORD_ENABLE (1 << SPDIF_CFGR_HALFWORD_SHIFT)