From 6ce3e83a23d7942e6662a0344fa16dfc2bbb3ccd Mon Sep 17 00:00:00 2001 From: Zhihuan He Date: Wed, 30 Oct 2024 17:27:24 +0800 Subject: [PATCH] clk: rockchip: rk3588: add PCLK_DDR_MON_CH for ddr monitor Change-Id: I822ca44539a675cd35c9979fd14654463c80ba3d Signed-off-by: Zhihuan He --- drivers/clk/rockchip/clk-rk3588.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/clk/rockchip/clk-rk3588.c b/drivers/clk/rockchip/clk-rk3588.c index 7f2f11680d3f..cfa4af5de717 100644 --- a/drivers/clk/rockchip/clk-rk3588.c +++ b/drivers/clk/rockchip/clk-rk3588.c @@ -1331,6 +1331,14 @@ static struct rockchip_clk_branch rk3588_clk_branches[] __initdata = { COMPOSITE(CLK_DDR_CM0_RTC, "clk_ddr_cm0_rtc", mux_24m_32k_p, CLK_IS_CRITICAL, RK3588_CLKSEL_CON(166), 5, 1, MFLAGS, 0, 5, DFLAGS, RK3588_CLKGATE_CON(70), 4, GFLAGS), + GATE(PCLK_DDR_MON_CH0, "pclk_ddr_mon_ch0", "pclk_center_root", 0, + RK3588_CLKGATE_CON(20), 1, GFLAGS), + GATE(PCLK_DDR_MON_CH1, "pclk_ddr_mon_ch1", "pclk_center_root", 0, + RK3588_CLKGATE_CON(20), 14, GFLAGS), + GATE(PCLK_DDR_MON_CH2, "pclk_ddr_mon_ch2", "pclk_center_root", 0, + RK3588_CLKGATE_CON(23), 1, GFLAGS), + GATE(PCLK_DDR_MON_CH3, "pclk_ddr_mon_ch3", "pclk_center_root", 0, + RK3588_CLKGATE_CON(23), 14, GFLAGS), GATE(PCLK_WDT, "pclk_wdt", "pclk_center_root", 0, RK3588_CLKGATE_CON(70), 7, GFLAGS), GATE(PCLK_TIMER, "pclk_timer", "pclk_center_root", 0,