From 6dc7ea13ccb17a9a6add52e7427a88a3dc5002b3 Mon Sep 17 00:00:00 2001 From: Nickey Yang Date: Tue, 31 Mar 2020 09:03:50 +0800 Subject: [PATCH] ARM: dts: rv1126-ipc2: add RTL8201F support RTL8201F ethernet working in RMII mode. Signed-off-by: David Wu Signed-off-by: Nickey Yang Change-Id: I15e47711d84f86826aebe1068a340bf293d76569 --- arch/arm/boot/dts/rv1126-ipc2-ddr3-v10.dts | 28 +++++++++++++++++++++- 1 file changed, 27 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/rv1126-ipc2-ddr3-v10.dts b/arch/arm/boot/dts/rv1126-ipc2-ddr3-v10.dts index c8bb0a8e7912..aac20a395353 100644 --- a/arch/arm/boot/dts/rv1126-ipc2-ddr3-v10.dts +++ b/arch/arm/boot/dts/rv1126-ipc2-ddr3-v10.dts @@ -108,6 +108,25 @@ status = "okay"; }; +&gmac { + phy-mode = "rmii"; + clock_in_out = "output"; + + snps,reset-gpio = <&gpio3 RK_PA6 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + snps,reset-delays-us = <0 50000 50000>; + + assigned-clocks = <&cru CLK_GMAC_SRC>, <&cru CLK_GMAC_TX_RX>; + assigned-clock-parents = <&cru CLK_GMAC_SRC_M0>, <&cru RMII_MODE_CLK>; + assigned-clock-rates = <50000000>; + + pinctrl-names = "default"; + pinctrl-0 = <&rmiim0_pins &gmac_clk_m0_drv_level3_pins>; + + phy-handle = <&phy>; + status = "okay"; +}; + &i2c0 { status = "okay"; clock-frequency = <400000>; @@ -368,6 +387,13 @@ &i2s0m0_sdo1_sdi3>; }; +&mdio { + phy: phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x0>; + }; +}; + &mpp_srv { status = "okay"; }; @@ -412,7 +438,7 @@ pmuio1-supply = <&vcc3v3_sys>; vccio4-supply = <&vcc_1v8>; vccio5-supply = <&vcc_3v3>; - vccio6-supply = <&vcc_1v8>; + vccio6-supply = <&vcc_3v3>; vccio7-supply = <&vcc_1v8>; };