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clk: rockchip: rk3288: fix up the 594M pll vco

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Modify VCO within safe limits(600M-3200M).
mark refdiv = 1

Change-Id: I76b69091ee1ff9a0d88f17a1e4dabda6e267caad
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
This commit is contained in:
Elaine Zhang
2018-05-31 15:08:54 +08:00
committed by Tao Huang
parent acc21855ff
commit 6ef83c562e
1 changed files with 10 additions and 8 deletions
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18
drivers/clk/rockchip/clk-rk3288.c
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@@ -69,32 +69,32 @@ static struct rockchip_pll_rate_table rk3288_pll_rates[] = {
RK3066_PLL_RATE(1248000000, 1, 52, 1),
RK3066_PLL_RATE(1224000000, 1, 51, 1),
RK3066_PLL_RATE(1200000000, 1, 50, 1),
RK3066_PLL_RATE(1188000000, 2, 99, 1),
RK3066_PLL_RATE(1188000000, 1, 99, 2),
RK3066_PLL_RATE(1176000000, 1, 49, 1),
RK3066_PLL_RATE(1128000000, 1, 47, 1),
RK3066_PLL_RATE(1104000000, 1, 46, 1),
RK3066_PLL_RATE(1008000000, 1, 84, 2),
RK3066_PLL_RATE( 912000000, 1, 76, 2),
RK3066_PLL_RATE( 891000000, 8, 594, 2),
RK3066_PLL_RATE( 891000000, 2, 297, 4),
RK3066_PLL_RATE( 888000000, 1, 74, 2),
RK3066_PLL_RATE( 816000000, 1, 68, 2),
RK3066_PLL_RATE( 798000000, 2, 133, 2),
RK3066_PLL_RATE( 798000000, 1, 133, 4),
RK3066_PLL_RATE( 792000000, 1, 66, 2),
RK3066_PLL_RATE( 768000000, 1, 64, 2),
RK3066_PLL_RATE( 742500000, 8, 495, 2),
RK3066_PLL_RATE( 742500000, 4, 495, 4),
RK3066_PLL_RATE( 696000000, 1, 58, 2),
RK3066_PLL_RATE_NB(621000000, 1, 207, 8, 1),
RK3066_PLL_RATE( 600000000, 1, 50, 2),
RK3066_PLL_RATE_NB(594000000, 1, 198, 8, 1),
RK3066_PLL_RATE_NB(594000000, 1, 99, 4, 1),
RK3066_PLL_RATE( 552000000, 1, 46, 2),
RK3066_PLL_RATE( 504000000, 1, 84, 4),
RK3066_PLL_RATE( 500000000, 3, 125, 2),
RK3066_PLL_RATE( 500000000, 1, 125, 6),
RK3066_PLL_RATE( 456000000, 1, 76, 4),
RK3066_PLL_RATE( 428000000, 1, 107, 6),
RK3066_PLL_RATE( 408000000, 1, 68, 4),
RK3066_PLL_RATE( 400000000, 3, 100, 2),
RK3066_PLL_RATE( 400000000, 1, 100, 6),
RK3066_PLL_RATE_NB( 394000000, 1, 197, 12, 1),
RK3066_PLL_RATE( 384000000, 2, 128, 4),
RK3066_PLL_RATE( 384000000, 1, 64, 4),
RK3066_PLL_RATE( 360000000, 1, 60, 4),
RK3066_PLL_RATE_NB( 356000000, 1, 178, 12, 1),
RK3066_PLL_RATE_NB( 324000000, 1, 189, 14, 1),
@@ -103,6 +103,7 @@ static struct rockchip_pll_rate_table rk3288_pll_rates[] = {
RK3066_PLL_RATE_NB( 303000000, 1, 202, 16, 1),
RK3066_PLL_RATE( 300000000, 1, 75, 6),
RK3066_PLL_RATE_NB( 297750000, 2, 397, 16, 1),
RK3066_PLL_RATE( 297000000, 1, 99, 8),
RK3066_PLL_RATE_NB( 293250000, 2, 391, 16, 1),
RK3066_PLL_RATE_NB( 292500000, 1, 195, 16, 1),
RK3066_PLL_RATE( 273600000, 1, 114, 10),
@@ -120,6 +121,7 @@ static struct rockchip_pll_rate_table rk3288_pll_rates[] = {
RK3066_PLL_RATE( 195428571, 1, 114, 14),
RK3066_PLL_RATE( 160000000, 1, 80, 12),
RK3066_PLL_RATE( 157500000, 1, 105, 16),
RK3066_PLL_RATE( 148500000, 1, 99, 16),
RK3066_PLL_RATE( 126000000, 1, 84, 16),
{ /* sentinel */ },
};