From 6f83acacb670e23874bfe2ee216211eb28d1b7e6 Mon Sep 17 00:00:00 2001 From: David Wu Date: Fri, 3 Apr 2020 12:39:49 +0800 Subject: [PATCH] ARM: dts: rv1126: Fix RMII TX io drv strength Based on hardware testing, the level3 signal amplitude is too strong, and it is enough to drop to the level0 value. Change-Id: I9ea282f2524449bc81610a45cfd8b1b5e22440e3 Signed-off-by: David Wu --- arch/arm/boot/dts/rv1126-ipc2-ddr3-v10.dts | 2 +- arch/arm/boot/dts/rv1126-pinctrl.dtsi | 30 +++++++++++++------ .../boot/dts/rv1126-sphericalipc-ddr3-v10.dts | 2 +- 3 files changed, 23 insertions(+), 11 deletions(-) diff --git a/arch/arm/boot/dts/rv1126-ipc2-ddr3-v10.dts b/arch/arm/boot/dts/rv1126-ipc2-ddr3-v10.dts index 082b436c6bf1..4abffe687aef 100644 --- a/arch/arm/boot/dts/rv1126-ipc2-ddr3-v10.dts +++ b/arch/arm/boot/dts/rv1126-ipc2-ddr3-v10.dts @@ -121,7 +121,7 @@ assigned-clock-rates = <50000000>; pinctrl-names = "default"; - pinctrl-0 = <&rmiim0_pins &gmac_clk_m0_drv_level3_pins>; + pinctrl-0 = <&rmiim0_pins &gmac_clk_m0_drv_level0_pins>; phy-handle = <&phy>; status = "okay"; diff --git a/arch/arm/boot/dts/rv1126-pinctrl.dtsi b/arch/arm/boot/dts/rv1126-pinctrl.dtsi index 025281c559d7..9bb908c780cc 100644 --- a/arch/arm/boot/dts/rv1126-pinctrl.dtsi +++ b/arch/arm/boot/dts/rv1126-pinctrl.dtsi @@ -1206,7 +1206,7 @@ rmiim0_pins: rmiim0-pins { rockchip,pins = /* rmii_mdc_m0 */ - <3 RK_PC4 2 &pcfg_pull_none>, + <3 RK_PC4 2 &pcfg_pull_none_drv_level_0>, /* rmii_mdio_m0 */ <3 RK_PC3 2 &pcfg_pull_none>, /* rmii_rxd0_m0 */ @@ -1218,17 +1218,17 @@ /* rmii_rxer_m0 */ <3 RK_PC2 2 &pcfg_pull_none>, /* rmii_txd0_m0 */ - <3 RK_PB3 2 &pcfg_pull_none_drv_level_3>, + <3 RK_PB3 2 &pcfg_pull_none_drv_level_0>, /* rmii_txd1_m0 */ - <3 RK_PB4 2 &pcfg_pull_none_drv_level_3>, + <3 RK_PB4 2 &pcfg_pull_none_drv_level_0>, /* rmii_txen_m0 */ - <3 RK_PB5 2 &pcfg_pull_none_drv_level_3>; + <3 RK_PB5 2 &pcfg_pull_none_drv_level_0>; }; /omit-if-no-ref/ rmiim1_pins: rmiim1-pins { rockchip,pins = /* rmii_mdc_m1 */ - <2 RK_PC2 2 &pcfg_pull_none>, + <2 RK_PC2 2 &pcfg_pull_none_drv_level_0>, /* rmii_mdio_m1 */ <2 RK_PC1 2 &pcfg_pull_none>, /* rmii_rxd0_m1 */ @@ -1240,11 +1240,11 @@ /* rmii_rxer_m1 */ <2 RK_PC0 2 &pcfg_pull_none>, /* rmii_txd0_m1 */ - <2 RK_PC3 2 &pcfg_pull_none_drv_level_3>, + <2 RK_PC3 2 &pcfg_pull_none_drv_level_0>, /* rmii_txd1_m1 */ - <2 RK_PC4 2 &pcfg_pull_none_drv_level_3>, + <2 RK_PC4 2 &pcfg_pull_none_drv_level_0>, /* rmii_txen_m1 */ - <2 RK_PC6 2 &pcfg_pull_none_drv_level_3>; + <2 RK_PC6 2 &pcfg_pull_none_drv_level_0>; }; }; gmac_clk { @@ -1255,6 +1255,12 @@ <3 RK_PC0 2 &pcfg_pull_none>; }; /omit-if-no-ref/ + gmac_clk_m0_drv_level0_pins: gmac-clk-m0-drv-level0-pins { + rockchip,pins = + /* rgmii_clk_m0 */ + <3 RK_PC0 2 &pcfg_pull_none_drv_level_0>; + }; + /omit-if-no-ref/ gmac_clk_m0_drv_level3_pins: gmac-clk-m0-drv-level3-pins { rockchip,pins = /* rgmii_clk_m0 */ @@ -1267,7 +1273,13 @@ <2 RK_PB7 2 &pcfg_pull_none>; }; /omit-if-no-ref/ - gmac_clk_m1_level3_pins: gmac-clk-m1-drv-level3-pins { + gmac_clk_m1_drv_level0_pins: gmac-clk-m1-drv-level0-pins { + rockchip,pins = + /* rgmii_clk_m1 */ + <2 RK_PB7 2 &pcfg_pull_none_drv_level_0>; + }; + /omit-if-no-ref/ + gmac_clk_m1_drv_level3_pins: gmac-clk-m1-drv-level3-pins { rockchip,pins = /* rgmii_clk_m1 */ <2 RK_PB7 2 &pcfg_pull_none>; diff --git a/arch/arm/boot/dts/rv1126-sphericalipc-ddr3-v10.dts b/arch/arm/boot/dts/rv1126-sphericalipc-ddr3-v10.dts index a9b21ff6fa1a..d847e1610936 100644 --- a/arch/arm/boot/dts/rv1126-sphericalipc-ddr3-v10.dts +++ b/arch/arm/boot/dts/rv1126-sphericalipc-ddr3-v10.dts @@ -121,7 +121,7 @@ assigned-clock-rates = <50000000>; pinctrl-names = "default"; - pinctrl-0 = <&rmiim0_pins &gmac_clk_m0_drv_level3_pins>; + pinctrl-0 = <&rmiim0_pins &gmac_clk_m0_drv_level0_pins>; phy-handle = <&phy>; status = "okay";