From 6fd905892ea25e477b356fb0f060d9d1efebdd8e Mon Sep 17 00:00:00 2001 From: Elaine Zhang Date: Thu, 20 Dec 2018 15:07:04 +0800 Subject: [PATCH] clk: rockchip: px30: add FRAC_MAX_PRATE limit for uart0 Change-Id: Id4ec1995a8c406a1eb71da05a04699aa869f52b5 Signed-off-by: Elaine Zhang --- drivers/clk/rockchip/clk-px30.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/rockchip/clk-px30.c b/drivers/clk/rockchip/clk-px30.c index 46e2bcf044b5..56e78c22d9fb 100644 --- a/drivers/clk/rockchip/clk-px30.c +++ b/drivers/clk/rockchip/clk-px30.c @@ -951,7 +951,7 @@ static struct rockchip_clk_branch px30_clk_pmu_branches[] __initdata = { COMPOSITE_FRACMUX(0, "clk_uart0_frac", "clk_uart0_pmu_src", CLK_SET_RATE_PARENT, PX30_PMU_CLKSEL_CON(5), 0, PX30_PMU_CLKGATE_CON(1), 2, GFLAGS, - &px30_uart0_pmu_fracmux, 0), + &px30_uart0_pmu_fracmux, PX30_FRAC_MAX_PRATE), GATE(SCLK_UART0_PMU, "clk_uart0_pmu", "clk_uart0_pmu_mux", CLK_SET_RATE_PARENT, PX30_PMU_CLKGATE_CON(1), 3, GFLAGS),