From 302f0dad8c97a11abcf145ff3c7036f8f80e1a1e Mon Sep 17 00:00:00 2001 From: Sandeep Singh Date: Sat, 10 Oct 2020 01:31:35 +0530 Subject: [PATCH 001/799] SFH: Add maintainers and documentation for AMD SFH based on HID framework Add Maintainers for AMD SFH(SENSOR FUSION HUB) Solution and work flow document. Co-developed-by: Nehal Shah Signed-off-by: Nehal Shah Signed-off-by: Sandeep Singh Signed-off-by: Jiri Kosina --- Documentation/hid/index.rst | 1 + MAINTAINERS | 8 ++++++++ 2 files changed, 9 insertions(+) diff --git a/Documentation/hid/index.rst b/Documentation/hid/index.rst index 737d66dc16a1..e50f513c579c 100644 --- a/Documentation/hid/index.rst +++ b/Documentation/hid/index.rst @@ -16,3 +16,4 @@ Human Interface Devices (HID) hid-alps intel-ish-hid + amd-sfh-hid diff --git a/MAINTAINERS b/MAINTAINERS index dd1887c3c5bf..9d12f61d0519 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -950,6 +950,14 @@ S: Supported F: arch/arm64/boot/dts/amd/amd-seattle-xgbe*.dtsi F: drivers/net/ethernet/amd/xgbe/ +AMD SENSOR FUSION HUB DRIVER +M: Nehal Shah +M: Sandeep Singh +L: linux-input@vger.kernel.org +S: Maintained +F: Documentation/hid/amd-sfh* +F: drivers/hid/amd-sfh-hid/ + AMS AS73211 DRIVER M: Christian Eggers L: linux-iio@vger.kernel.org From 4f567b9f8141a86c7d878fadf136e5d1408e3e61 Mon Sep 17 00:00:00 2001 From: Sandeep Singh Date: Sat, 10 Oct 2020 01:31:36 +0530 Subject: [PATCH 002/799] SFH: PCIe driver to add support of AMD sensor fusion hub AMD SFH (Sensor Fusion Hub) is a solution running on MP2 (which is ARM core connected to x86 for processing sensor data). AMD SFH uses HID over PCI bus to form the HID descriptors and talks to HID clients like the monitor-sensor/iio-proxy. MP2 which is exposed as a PCI device to the x86, uses mailboxes to talk to MP2 firmware to send/receive commands. Co-developed-by: Nehal Shah Signed-off-by: Nehal Shah Signed-off-by: Sandeep Singh Signed-off-by: Jiri Kosina --- drivers/hid/Kconfig | 2 + drivers/hid/Makefile | 2 + drivers/hid/amd-sfh-hid/Kconfig | 18 +++ drivers/hid/amd-sfh-hid/Makefile | 13 +++ drivers/hid/amd-sfh-hid/amd_sfh_pcie.c | 152 +++++++++++++++++++++++++ drivers/hid/amd-sfh-hid/amd_sfh_pcie.h | 79 +++++++++++++ 6 files changed, 266 insertions(+) create mode 100644 drivers/hid/amd-sfh-hid/Kconfig create mode 100644 drivers/hid/amd-sfh-hid/Makefile create mode 100644 drivers/hid/amd-sfh-hid/amd_sfh_pcie.c create mode 100644 drivers/hid/amd-sfh-hid/amd_sfh_pcie.h diff --git a/drivers/hid/Kconfig b/drivers/hid/Kconfig index 612629678c84..fff3963ba02b 100644 --- a/drivers/hid/Kconfig +++ b/drivers/hid/Kconfig @@ -1183,4 +1183,6 @@ source "drivers/hid/i2c-hid/Kconfig" source "drivers/hid/intel-ish-hid/Kconfig" +source "drivers/hid/amd-sfh-hid/Kconfig" + endmenu diff --git a/drivers/hid/Makefile b/drivers/hid/Makefile index 4acb583c92a6..014d21fe7dac 100644 --- a/drivers/hid/Makefile +++ b/drivers/hid/Makefile @@ -142,3 +142,5 @@ obj-$(CONFIG_I2C_HID) += i2c-hid/ obj-$(CONFIG_INTEL_ISH_HID) += intel-ish-hid/ obj-$(INTEL_ISH_FIRMWARE_DOWNLOADER) += intel-ish-hid/ + +obj-$(CONFIG_AMD_SFH_HID) += amd-sfh-hid/ diff --git a/drivers/hid/amd-sfh-hid/Kconfig b/drivers/hid/amd-sfh-hid/Kconfig new file mode 100644 index 000000000000..db069a83e9a2 --- /dev/null +++ b/drivers/hid/amd-sfh-hid/Kconfig @@ -0,0 +1,18 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +menu "AMD SFH HID Support" + depends on X86_64 || COMPILE_TEST + depends on PCI + depends on HID + +config AMD_SFH_HID + tristate "AMD Sensor Fusion Hub" + help + If you say yes to this option, support will be included for the + AMD Sensor Fusion Hub. + This driver will enable sensors functionality on AMD platforms + starting from 17h family of RYZEN parts. + + This driver can also be built as a module. If so, the module will + be called amd-sfh. + Say Y or M here if you want to support AMD SFH. If unsure, say N. +endmenu diff --git a/drivers/hid/amd-sfh-hid/Makefile b/drivers/hid/amd-sfh-hid/Makefile new file mode 100644 index 000000000000..35e704da5612 --- /dev/null +++ b/drivers/hid/amd-sfh-hid/Makefile @@ -0,0 +1,13 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# +# Makefile - AMD SFH HID drivers +# Copyright (c) 2019-2020, Advanced Micro Devices, Inc. +# +# +obj-$(CONFIG_AMD_SFH_HID) += amd_sfh.o +amd_sfh-objs := amd_sfh_hid.o +amd_sfh-objs += amd_sfh_client.o +amd_sfh-objs += amd_sfh_pcie.o +amd_sfh-objs += hid_descriptor/amd_sfh_hid_desc.o + +ccflags-y += -I $(srctree)/$(src)/ diff --git a/drivers/hid/amd-sfh-hid/amd_sfh_pcie.c b/drivers/hid/amd-sfh-hid/amd_sfh_pcie.c new file mode 100644 index 000000000000..9c5eb442e1a6 --- /dev/null +++ b/drivers/hid/amd-sfh-hid/amd_sfh_pcie.c @@ -0,0 +1,152 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * AMD MP2 PCIe communication driver + * Copyright 2020 Advanced Micro Devices, Inc. + * + * Authors: Shyam Sundar S K + * Sandeep Singh + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "amd_sfh_pcie.h" + +#define DRIVER_NAME "pcie_mp2_amd" +#define DRIVER_DESC "AMD(R) PCIe MP2 Communication Driver" + +#define ACEL_EN BIT(1) +#define GYRO_EN BIT(2) +#define MAGNO_EN BIT(3) +#define ALS_EN BIT(19) + +void amd_start_sensor(struct amd_mp2_dev *privdata, struct amd_mp2_sensor_info info) +{ + union sfh_cmd_param cmd_param; + union sfh_cmd_base cmd_base; + + /* fill up command register */ + memset(&cmd_base, 0, sizeof(cmd_base)); + cmd_base.s.cmd_id = ENABLE_SENSOR; + cmd_base.s.period = info.period; + cmd_base.s.sensor_id = info.sensor_idx; + + /* fill up command param register */ + memset(&cmd_param, 0, sizeof(cmd_param)); + cmd_param.s.buf_layout = 1; + cmd_param.s.buf_length = 16; + + writeq(info.phys_address, privdata->mmio + AMD_C2P_MSG2); + writel(cmd_param.ul, privdata->mmio + AMD_C2P_MSG1); + writel(cmd_base.ul, privdata->mmio + AMD_C2P_MSG0); +} + +void amd_stop_sensor(struct amd_mp2_dev *privdata, u16 sensor_idx) +{ + union sfh_cmd_base cmd_base; + + /* fill up command register */ + memset(&cmd_base, 0, sizeof(cmd_base)); + cmd_base.s.cmd_id = DISABLE_SENSOR; + cmd_base.s.period = 0; + cmd_base.s.sensor_id = sensor_idx; + + writeq(0x0, privdata->mmio + AMD_C2P_MSG2); + writel(cmd_base.ul, privdata->mmio + AMD_C2P_MSG0); +} + +void amd_stop_all_sensors(struct amd_mp2_dev *privdata) +{ + union sfh_cmd_base cmd_base; + + /* fill up command register */ + memset(&cmd_base, 0, sizeof(cmd_base)); + cmd_base.s.cmd_id = STOP_ALL_SENSORS; + cmd_base.s.period = 0; + cmd_base.s.sensor_id = 0; + + writel(cmd_base.ul, privdata->mmio + AMD_C2P_MSG0); +} + +int amd_mp2_get_sensor_num(struct amd_mp2_dev *privdata, u8 *sensor_id) +{ + int activestatus, num_of_sensors = 0; + + privdata->activecontrolstatus = readl(privdata->mmio + AMD_P2C_MSG3); + activestatus = privdata->activecontrolstatus >> 4; + if (ACEL_EN & activestatus) + sensor_id[num_of_sensors++] = accel_idx; + + if (GYRO_EN & activestatus) + sensor_id[num_of_sensors++] = gyro_idx; + + if (MAGNO_EN & activestatus) + sensor_id[num_of_sensors++] = mag_idx; + + if (ALS_EN & activestatus) + sensor_id[num_of_sensors++] = als_idx; + + return num_of_sensors; +} + +static void amd_mp2_pci_remove(void *privdata) +{ + amd_sfh_hid_client_deinit(privdata); + amd_stop_all_sensors(privdata); +} + +static int amd_mp2_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) +{ + struct amd_mp2_dev *privdata; + int rc; + + privdata = devm_kzalloc(&pdev->dev, sizeof(*privdata), GFP_KERNEL); + if (!privdata) + return -ENOMEM; + + privdata->pdev = pdev; + pci_set_drvdata(pdev, privdata); + rc = pcim_enable_device(pdev); + if (rc) + return rc; + + rc = pcim_iomap_regions(pdev, BIT(2), DRIVER_NAME); + if (rc) + return rc; + + privdata->mmio = pcim_iomap_table(pdev)[2]; + pci_set_master(pdev); + rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)); + if (rc) { + rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); + return rc; + } + rc = devm_add_action_or_reset(&pdev->dev, amd_mp2_pci_remove, privdata); + if (rc) + return rc; + + return amd_sfh_hid_client_init(privdata); +} + +static const struct pci_device_id amd_mp2_pci_tbl[] = { + { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_MP2) }, + { } +}; +MODULE_DEVICE_TABLE(pci, amd_mp2_pci_tbl); + +static struct pci_driver amd_mp2_pci_driver = { + .name = DRIVER_NAME, + .id_table = amd_mp2_pci_tbl, + .probe = amd_mp2_pci_probe, +}; +module_pci_driver(amd_mp2_pci_driver); + +MODULE_DESCRIPTION(DRIVER_DESC); +MODULE_LICENSE("Dual BSD/GPL"); +MODULE_AUTHOR("Shyam Sundar S K "); +MODULE_AUTHOR("Sandeep Singh "); diff --git a/drivers/hid/amd-sfh-hid/amd_sfh_pcie.h b/drivers/hid/amd-sfh-hid/amd_sfh_pcie.h new file mode 100644 index 000000000000..e8be94f935b7 --- /dev/null +++ b/drivers/hid/amd-sfh-hid/amd_sfh_pcie.h @@ -0,0 +1,79 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * AMD MP2 PCIe communication driver + * Copyright 2020 Advanced Micro Devices, Inc. + * Authors: Shyam Sundar S K + * Sandeep Singh + */ + +#ifndef PCIE_MP2_AMD_H +#define PCIE_MP2_AMD_H + +#include + +#define PCI_DEVICE_ID_AMD_MP2 0x15E4 + +#define ENABLE_SENSOR 1 +#define DISABLE_SENSOR 2 +#define STOP_ALL_SENSORS 8 + +/* MP2 C2P Message Registers */ +#define AMD_C2P_MSG0 0x10500 +#define AMD_C2P_MSG1 0x10504 +#define AMD_C2P_MSG2 0x10508 + +/* MP2 P2C Message Registers */ +#define AMD_P2C_MSG3 0x1068C /* Supported Sensors info */ + +/* SFH Command register */ +union sfh_cmd_base { + u32 ul; + struct { + u32 cmd_id : 8; + u32 sensor_id : 8; + u32 period : 16; + } s; +}; + +union sfh_cmd_param { + u32 ul; + struct { + u32 buf_layout : 2; + u32 buf_length : 6; + u32 rsvd : 24; + } s; +}; + +struct sfh_cmd_reg { + union sfh_cmd_base cmd_base; + union sfh_cmd_param cmd_param; + phys_addr_t phys_addr; +}; + +enum sensor_idx { + accel_idx = 0, + gyro_idx = 1, + mag_idx = 2, + als_idx = 19 +}; + +struct amd_mp2_dev { + struct pci_dev *pdev; + struct amdtp_cl_data *cl_data; + void __iomem *mmio; + u32 activecontrolstatus; +}; + +struct amd_mp2_sensor_info { + u8 sensor_idx; + u32 period; + phys_addr_t phys_address; +}; + +void amd_start_sensor(struct amd_mp2_dev *privdata, struct amd_mp2_sensor_info info); +void amd_stop_sensor(struct amd_mp2_dev *privdata, u16 sensor_idx); +void amd_stop_all_sensors(struct amd_mp2_dev *privdata); +int amd_mp2_get_sensor_num(struct amd_mp2_dev *privdata, u8 *sensor_id); +int amd_sfh_hid_client_init(struct amd_mp2_dev *privdata); +int amd_sfh_hid_client_deinit(struct amd_mp2_dev *privdata); +#endif From 4b2c53d93a4bc9d52cc0ec354629cfc9dc217f93 Mon Sep 17 00:00:00 2001 From: Sandeep Singh Date: Sat, 10 Oct 2020 01:31:37 +0530 Subject: [PATCH 003/799] SFH:Transport Driver to add support of AMD Sensor Fusion Hub (SFH) To support AMD Sensor Fusion Hub (SFH) via the HID client's we need to register the client with the HID framework. Here we mostly address on how to register the client with the framework and define the interfaces for communication. Co-developed-by: Nehal Shah Signed-off-by: Nehal Shah Signed-off-by: Sandeep Singh Signed-off-by: Jiri Kosina --- drivers/hid/amd-sfh-hid/amd_sfh_client.c | 246 +++++++++++++++++++++++ drivers/hid/amd-sfh-hid/amd_sfh_hid.c | 174 ++++++++++++++++ drivers/hid/amd-sfh-hid/amd_sfh_hid.h | 67 ++++++ 3 files changed, 487 insertions(+) create mode 100644 drivers/hid/amd-sfh-hid/amd_sfh_client.c create mode 100644 drivers/hid/amd-sfh-hid/amd_sfh_hid.c create mode 100644 drivers/hid/amd-sfh-hid/amd_sfh_hid.h diff --git a/drivers/hid/amd-sfh-hid/amd_sfh_client.c b/drivers/hid/amd-sfh-hid/amd_sfh_client.c new file mode 100644 index 000000000000..3d1ccac5d99a --- /dev/null +++ b/drivers/hid/amd-sfh-hid/amd_sfh_client.c @@ -0,0 +1,246 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * AMD SFH Client Layer + * Copyright 2020 Advanced Micro Devices, Inc. + * Authors: Nehal Bakulchandra Shah + * Sandeep Singh + */ + +#include +#include +#include +#include +#include +#include + +#include "hid_descriptor/amd_sfh_hid_desc.h" +#include "amd_sfh_pcie.h" +#include "amd_sfh_hid.h" + +#define AMD_SFH_IDLE_LOOP 200 + +struct request_list { + struct hid_device *hid; + struct list_head list; + u8 report_id; + u8 sensor_idx; + u8 report_type; + u8 current_index; +}; + +static struct request_list req_list; + +void amd_sfh_set_report(struct hid_device *hid, int report_id, + int report_type) +{ + struct amdtp_hid_data *hid_data = hid->driver_data; + struct amdtp_cl_data *cli_data = hid_data->cli_data; + int i; + + for (i = 0; i < cli_data->num_hid_devices; i++) { + if (cli_data->hid_sensor_hubs[i] == hid) { + cli_data->cur_hid_dev = i; + break; + } + } + amdtp_hid_wakeup(hid); +} + +int amd_sfh_get_report(struct hid_device *hid, int report_id, int report_type) +{ + struct amdtp_hid_data *hid_data = hid->driver_data; + struct amdtp_cl_data *cli_data = hid_data->cli_data; + int i; + + for (i = 0; i < cli_data->num_hid_devices; i++) { + if (cli_data->hid_sensor_hubs[i] == hid) { + struct request_list *new = kzalloc(sizeof(*new), GFP_KERNEL); + + if (!new) + return -ENOMEM; + + new->current_index = i; + new->sensor_idx = cli_data->sensor_idx[i]; + new->hid = hid; + new->report_type = report_type; + new->report_id = report_id; + cli_data->report_id[i] = report_id; + cli_data->request_done[i] = false; + list_add(&new->list, &req_list.list); + break; + } + } + schedule_delayed_work(&cli_data->work, 0); + return 0; +} + +static void amd_sfh_work(struct work_struct *work) +{ + struct amdtp_cl_data *cli_data = container_of(work, struct amdtp_cl_data, work.work); + struct request_list *req_node; + u8 current_index, sensor_index; + u8 report_id, node_type; + u8 report_size = 0; + + req_node = list_last_entry(&req_list.list, struct request_list, list); + list_del(&req_node->list); + current_index = req_node->current_index; + sensor_index = req_node->sensor_idx; + report_id = req_node->report_id; + node_type = req_node->report_type; + + if (node_type == HID_FEATURE_REPORT) { + report_size = get_feature_report(sensor_index, report_id, + cli_data->feature_report[current_index]); + if (report_size) + hid_input_report(cli_data->hid_sensor_hubs[current_index], + cli_data->report_type[current_index], + cli_data->feature_report[current_index], report_size, 0); + else + pr_err("AMDSFH: Invalid report size\n"); + + } else if (node_type == HID_INPUT_REPORT) { + report_size = get_input_report(sensor_index, report_id, + cli_data->input_report[current_index], + cli_data->sensor_virt_addr[current_index]); + if (report_size) + hid_input_report(cli_data->hid_sensor_hubs[current_index], + cli_data->report_type[current_index], + cli_data->input_report[current_index], report_size, 0); + else + pr_err("AMDSFH: Invalid report size\n"); + } + cli_data->cur_hid_dev = current_index; + cli_data->sensor_requested_cnt[current_index] = 0; + amdtp_hid_wakeup(cli_data->hid_sensor_hubs[current_index]); +} + +static void amd_sfh_work_buffer(struct work_struct *work) +{ + struct amdtp_cl_data *cli_data = container_of(work, struct amdtp_cl_data, work_buffer.work); + u8 report_size; + int i; + + for (i = 0; i < cli_data->num_hid_devices; i++) { + report_size = get_input_report(cli_data->sensor_idx[i], cli_data->report_id[i], + cli_data->input_report[i], + cli_data->sensor_virt_addr[i]); + hid_input_report(cli_data->hid_sensor_hubs[i], HID_INPUT_REPORT, + cli_data->input_report[i], report_size, 0); + } + schedule_delayed_work(&cli_data->work_buffer, msecs_to_jiffies(AMD_SFH_IDLE_LOOP)); +} + +int amd_sfh_hid_client_init(struct amd_mp2_dev *privdata) +{ + struct amdtp_cl_data *cl_data = privdata->cl_data; + struct amd_mp2_sensor_info info; + struct device *dev; + u32 feature_report_size; + u32 input_report_size; + u8 cl_idx; + int rc, i; + + dev = &privdata->pdev->dev; + cl_data = kzalloc(sizeof(*cl_data), GFP_KERNEL); + if (!cl_data) + return -ENOMEM; + + cl_data->num_hid_devices = amd_mp2_get_sensor_num(privdata, &cl_data->sensor_idx[0]); + + INIT_DELAYED_WORK(&cl_data->work, amd_sfh_work); + INIT_DELAYED_WORK(&cl_data->work_buffer, amd_sfh_work_buffer); + INIT_LIST_HEAD(&req_list.list); + + for (i = 0; i < cl_data->num_hid_devices; i++) { + cl_data->sensor_virt_addr[i] = dma_alloc_coherent(dev, sizeof(int) * 8, + &cl_data->sensor_phys_addr[i], + GFP_KERNEL); + cl_data->sensor_sts[i] = 0; + cl_data->sensor_requested_cnt[i] = 0; + cl_data->cur_hid_dev = i; + cl_idx = cl_data->sensor_idx[i]; + cl_data->report_descr_sz[i] = get_descr_sz(cl_idx, descr_size); + if (!cl_data->report_descr_sz[i]) { + rc = -EINVAL; + goto cleanup; + } + feature_report_size = get_descr_sz(cl_idx, feature_size); + if (!feature_report_size) { + rc = -EINVAL; + goto cleanup; + } + input_report_size = get_descr_sz(cl_idx, input_size); + if (!input_report_size) { + rc = -EINVAL; + goto cleanup; + } + cl_data->feature_report[i] = kzalloc(feature_report_size, GFP_KERNEL); + if (!cl_data->feature_report[i]) { + rc = -ENOMEM; + goto cleanup; + } + cl_data->input_report[i] = kzalloc(input_report_size, GFP_KERNEL); + if (!cl_data->input_report[i]) { + rc = -ENOMEM; + goto cleanup; + } + info.period = msecs_to_jiffies(AMD_SFH_IDLE_LOOP); + info.sensor_idx = cl_idx; + info.phys_address = cl_data->sensor_phys_addr[i]; + + cl_data->report_descr[i] = kzalloc(cl_data->report_descr_sz[i], GFP_KERNEL); + if (!cl_data->report_descr[i]) { + rc = -ENOMEM; + goto cleanup; + } + rc = get_report_descriptor(cl_idx, cl_data->report_descr[i]); + if (rc) + return rc; + rc = amdtp_hid_probe(cl_data->cur_hid_dev, cl_data); + if (rc) + return rc; + amd_start_sensor(privdata, info); + cl_data->sensor_sts[i] = 1; + } + privdata->cl_data = cl_data; + schedule_delayed_work(&cl_data->work_buffer, msecs_to_jiffies(AMD_SFH_IDLE_LOOP)); + return 0; + +cleanup: + for (i = 0; i < cl_data->num_hid_devices; i++) { + if (cl_data->sensor_virt_addr[i]) { + dma_free_coherent(&privdata->pdev->dev, 8 * sizeof(int), + cl_data->sensor_virt_addr[i], + cl_data->sensor_phys_addr[i]); + } + kfree(cl_data->feature_report[i]); + kfree(cl_data->input_report[i]); + kfree(cl_data->report_descr[i]); + } + kfree(cl_data); + return rc; +} + +int amd_sfh_hid_client_deinit(struct amd_mp2_dev *privdata) +{ + struct amdtp_cl_data *cl_data = privdata->cl_data; + int i; + + for (i = 0; i < cl_data->num_hid_devices; i++) + amd_stop_sensor(privdata, i); + + cancel_delayed_work_sync(&cl_data->work); + cancel_delayed_work_sync(&cl_data->work_buffer); + amdtp_hid_remove(cl_data); + + for (i = 0; i < cl_data->num_hid_devices; i++) { + if (cl_data->sensor_virt_addr[i]) { + dma_free_coherent(&privdata->pdev->dev, 8 * sizeof(int), + cl_data->sensor_virt_addr[i], + cl_data->sensor_phys_addr[i]); + } + } + kfree(cl_data); + return 0; +} diff --git a/drivers/hid/amd-sfh-hid/amd_sfh_hid.c b/drivers/hid/amd-sfh-hid/amd_sfh_hid.c new file mode 100644 index 000000000000..a471079a3bd0 --- /dev/null +++ b/drivers/hid/amd-sfh-hid/amd_sfh_hid.c @@ -0,0 +1,174 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * AMD MP2 Sensors transport driver + * + * Authors: Nehal Bakulchandra Shah + * Sandeep Singh + */ +#include +#include +#include + +#include "amd_sfh_hid.h" + +#define AMD_SFH_RESPONSE_TIMEOUT 1500 + +/** + * amdtp_hid_parse() - hid-core .parse() callback + * @hid: hid device instance + * + * This function gets called during call to hid_add_device + * + * Return: 0 on success and non zero on error + */ +static int amdtp_hid_parse(struct hid_device *hid) +{ + struct amdtp_hid_data *hid_data = hid->driver_data; + struct amdtp_cl_data *cli_data = hid_data->cli_data; + + return hid_parse_report(hid, cli_data->report_descr[hid_data->index], + cli_data->report_descr_sz[hid_data->index]); +} + +/* Empty callbacks with success return code */ +static int amdtp_hid_start(struct hid_device *hid) +{ + return 0; +} + +static void amdtp_hid_stop(struct hid_device *hid) +{ +} + +static int amdtp_hid_open(struct hid_device *hid) +{ + return 0; +} + +static void amdtp_hid_close(struct hid_device *hid) +{ +} + +static int amdtp_raw_request(struct hid_device *hdev, u8 reportnum, + u8 *buf, size_t len, u8 rtype, int reqtype) +{ + return 0; +} + +static void amdtp_hid_request(struct hid_device *hid, struct hid_report *rep, int reqtype) +{ + int rc; + + switch (reqtype) { + case HID_REQ_GET_REPORT: + rc = amd_sfh_get_report(hid, rep->id, rep->type); + if (rc) + dev_err(&hid->dev, "AMDSFH get report error\n"); + break; + case HID_REQ_SET_REPORT: + amd_sfh_set_report(hid, rep->id, reqtype); + break; + default: + break; + } +} + +static int amdtp_wait_for_response(struct hid_device *hid) +{ + struct amdtp_hid_data *hid_data = hid->driver_data; + struct amdtp_cl_data *cli_data = hid_data->cli_data; + int i, ret = 0; + + for (i = 0; i < cli_data->num_hid_devices; i++) { + if (cli_data->hid_sensor_hubs[i] == hid) + break; + } + + if (!cli_data->request_done[i]) + ret = wait_event_interruptible_timeout(hid_data->hid_wait, + cli_data->request_done[i], + msecs_to_jiffies(AMD_SFH_RESPONSE_TIMEOUT)); + if (ret < 0) + return -ETIMEDOUT; + else if (ret == -ERESTARTSYS) + return -ERESTARTSYS; + else + return 0; +} + +void amdtp_hid_wakeup(struct hid_device *hid) +{ + struct amdtp_hid_data *hid_data = hid->driver_data; + struct amdtp_cl_data *cli_data = hid_data->cli_data; + + cli_data->request_done[cli_data->cur_hid_dev] = true; + wake_up_interruptible(&hid_data->hid_wait); +} + +static struct hid_ll_driver amdtp_hid_ll_driver = { + .parse = amdtp_hid_parse, + .start = amdtp_hid_start, + .stop = amdtp_hid_stop, + .open = amdtp_hid_open, + .close = amdtp_hid_close, + .request = amdtp_hid_request, + .wait = amdtp_wait_for_response, + .raw_request = amdtp_raw_request, +}; + +int amdtp_hid_probe(u32 cur_hid_dev, struct amdtp_cl_data *cli_data) +{ + struct hid_device *hid; + struct amdtp_hid_data *hid_data; + int rc; + + hid = hid_allocate_device(); + if (IS_ERR(hid)) + return PTR_ERR(hid); + + hid_data = kzalloc(sizeof(*hid_data), GFP_KERNEL); + if (!hid_data) { + rc = -ENOMEM; + goto err_hid_data; + } + + hid->ll_driver = &amdtp_hid_ll_driver; + hid_data->index = cur_hid_dev; + hid_data->cli_data = cli_data; + init_waitqueue_head(&hid_data->hid_wait); + + hid->driver_data = hid_data; + cli_data->hid_sensor_hubs[cur_hid_dev] = hid; + hid->bus = BUS_AMD_AMDTP; + hid->vendor = AMD_SFH_HID_VENDOR; + hid->product = AMD_SFH_HID_PRODUCT; + snprintf(hid->name, sizeof(hid->name), "%s %04X:%04X", "hid-amdtp", + hid->vendor, hid->product); + + rc = hid_add_device(hid); + if (rc) + goto err_hid_device; + return 0; + +err_hid_device: + kfree(hid_data); +err_hid_data: + hid_destroy_device(hid); + return rc; +} + +void amdtp_hid_remove(struct amdtp_cl_data *cli_data) +{ + int i; + + for (i = 0; i < cli_data->num_hid_devices; ++i) { + kfree(cli_data->feature_report[i]); + kfree(cli_data->input_report[i]); + kfree(cli_data->report_descr[i]); + if (cli_data->hid_sensor_hubs[i]) { + kfree(cli_data->hid_sensor_hubs[i]->driver_data); + hid_destroy_device(cli_data->hid_sensor_hubs[i]); + cli_data->hid_sensor_hubs[i] = NULL; + } + } +} diff --git a/drivers/hid/amd-sfh-hid/amd_sfh_hid.h b/drivers/hid/amd-sfh-hid/amd_sfh_hid.h new file mode 100644 index 000000000000..6be0783d885c --- /dev/null +++ b/drivers/hid/amd-sfh-hid/amd_sfh_hid.h @@ -0,0 +1,67 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * AMD MP2 Sensors transport driver + * + * Authors: Nehal Bakulchandra Shah + * Sandeep Singh + */ + +#ifndef AMDSFH_HID_H +#define AMDSFH_HID_H + +#define MAX_HID_DEVICES 4 +#define BUS_AMD_AMDTP 0x20 +#define AMD_SFH_HID_VENDOR 0x1022 +#define AMD_SFH_HID_PRODUCT 0x0001 + +struct amdtp_cl_data { + u8 init_done; + u32 cur_hid_dev; + u32 hid_dev_count; + u32 num_hid_devices; + struct device_info *hid_devices; + u8 *report_descr[MAX_HID_DEVICES]; + int report_descr_sz[MAX_HID_DEVICES]; + struct hid_device *hid_sensor_hubs[MAX_HID_DEVICES]; + u8 *hid_descr[MAX_HID_DEVICES]; + int hid_descr_size[MAX_HID_DEVICES]; + phys_addr_t phys_addr_base; + u32 *sensor_virt_addr[MAX_HID_DEVICES]; + phys_addr_t sensor_phys_addr[MAX_HID_DEVICES]; + u32 sensor_sts[MAX_HID_DEVICES]; + u32 sensor_requested_cnt[MAX_HID_DEVICES]; + u8 report_type[MAX_HID_DEVICES]; + u8 report_id[MAX_HID_DEVICES]; + u8 sensor_idx[MAX_HID_DEVICES]; + u8 *feature_report[MAX_HID_DEVICES]; + u8 *input_report[MAX_HID_DEVICES]; + u8 request_done[MAX_HID_DEVICES]; + struct delayed_work work; + struct delayed_work work_buffer; +}; + +/** + * struct amdtp_hid_data - Per instance HID data + * @index: Device index in the order of enumeration + * @request_done: Get Feature/Input report complete flag + * used during get/set request from hid core + * @cli_data: Link to the client instance + * @hid_wait: Completion waitq + * + * Used to tie hid->driver data to driver client instance + */ +struct amdtp_hid_data { + int index; + struct amdtp_cl_data *cli_data; + wait_queue_head_t hid_wait; +}; + +/* Interface functions between HID LL driver and AMD SFH client */ +void hid_amdtp_set_feature(struct hid_device *hid, char *buf, u32 len, int report_id); +void hid_amdtp_get_report(struct hid_device *hid, int report_id, int report_type); +int amdtp_hid_probe(u32 cur_hid_dev, struct amdtp_cl_data *cli_data); +void amdtp_hid_remove(struct amdtp_cl_data *cli_data); +int amd_sfh_get_report(struct hid_device *hid, int report_id, int report_type); +void amd_sfh_set_report(struct hid_device *hid, int report_id, int report_type); +void amdtp_hid_wakeup(struct hid_device *hid); +#endif From 1434f9fc0e476362f3f3d153d48c0fc5c940a50a Mon Sep 17 00:00:00 2001 From: Sandeep Singh Date: Sat, 10 Oct 2020 01:31:38 +0530 Subject: [PATCH 004/799] SFH: Create HID report to Enable support of AMD sensor fusion Hub (SFH) Communication between HID devices and HID core is mostly done via HID reports. HID reports are formed based on the data received from the PCI layer into the HID report descriptors. Co-developed-by: Nehal Shah Signed-off-by: Nehal Shah Signed-off-by: Sandeep Singh Signed-off-by: Jiri Kosina --- .../hid_descriptor/amd_sfh_hid_desc.c | 224 ++++++ .../hid_descriptor/amd_sfh_hid_desc.h | 121 ++++ .../hid_descriptor/amd_sfh_hid_report_desc.h | 645 ++++++++++++++++++ 3 files changed, 990 insertions(+) create mode 100644 drivers/hid/amd-sfh-hid/hid_descriptor/amd_sfh_hid_desc.c create mode 100644 drivers/hid/amd-sfh-hid/hid_descriptor/amd_sfh_hid_desc.h create mode 100644 drivers/hid/amd-sfh-hid/hid_descriptor/amd_sfh_hid_report_desc.h diff --git a/drivers/hid/amd-sfh-hid/hid_descriptor/amd_sfh_hid_desc.c b/drivers/hid/amd-sfh-hid/hid_descriptor/amd_sfh_hid_desc.c new file mode 100644 index 000000000000..6e3ad66e57a4 --- /dev/null +++ b/drivers/hid/amd-sfh-hid/hid_descriptor/amd_sfh_hid_desc.c @@ -0,0 +1,224 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * AMD SFH Report Descriptor generator + * Copyright 2020 Advanced Micro Devices, Inc. + * Authors: Nehal Bakulchandra Shah + * Sandeep Singh + */ + +#include +#include +#include +#include "amd_sfh_pcie.h" +#include "amd_sfh_hid_desc.h" +#include "amd_sfh_hid_report_desc.h" + +#define AMD_SFH_FW_MULTIPLIER (1000) +#define HID_USAGE_SENSOR_PROP_REPORTING_STATE_ALL_EVENTS_ENUM 0x41 +#define HID_USAGE_SENSOR_PROP_POWER_STATE_D0_FULL_POWER_ENUM 0x51 +#define HID_DEFAULT_REPORT_INTERVAL 0x50 +#define HID_DEFAULT_MIN_VALUE 0X7F +#define HID_DEFAULT_MAX_VALUE 0x80 +#define HID_DEFAULT_SENSITIVITY 0x7F +#define HID_USAGE_SENSOR_PROPERTY_CONNECTION_TYPE_PC_INTEGRATED_ENUM 0x01 +/* state enums */ +#define HID_USAGE_SENSOR_STATE_READY_ENUM 0x02 +#define HID_USAGE_SENSOR_STATE_INITIALIZING_ENUM 0x05 +#define HID_USAGE_SENSOR_EVENT_DATA_UPDATED_ENUM 0x04 + +int get_report_descriptor(int sensor_idx, u8 *rep_desc) +{ + switch (sensor_idx) { + case accel_idx: /* accel */ + memset(rep_desc, 0, sizeof(accel3_report_descriptor)); + memcpy(rep_desc, accel3_report_descriptor, + sizeof(accel3_report_descriptor)); + break; + case gyro_idx: /* gyro */ + memset(rep_desc, 0, sizeof(gyro3_report_descriptor)); + memcpy(rep_desc, gyro3_report_descriptor, + sizeof(gyro3_report_descriptor)); + break; + case mag_idx: /* Magnetometer */ + memset(rep_desc, 0, sizeof(comp3_report_descriptor)); + memcpy(rep_desc, comp3_report_descriptor, + sizeof(comp3_report_descriptor)); + break; + case als_idx: /* ambient light sensor */ + memset(rep_desc, 0, sizeof(als_report_descriptor)); + memcpy(rep_desc, als_report_descriptor, + sizeof(als_report_descriptor)); + break; + default: + break; + } + return 0; +} + +u32 get_descr_sz(int sensor_idx, int descriptor_name) +{ + switch (sensor_idx) { + case accel_idx: + switch (descriptor_name) { + case descr_size: + return sizeof(accel3_report_descriptor); + case input_size: + return sizeof(struct accel3_input_report); + case feature_size: + return sizeof(struct accel3_feature_report); + } + break; + case gyro_idx: + switch (descriptor_name) { + case descr_size: + return sizeof(gyro3_report_descriptor); + case input_size: + return sizeof(struct gyro_input_report); + case feature_size: + return sizeof(struct gyro_feature_report); + } + break; + case mag_idx: + switch (descriptor_name) { + case descr_size: + return sizeof(comp3_report_descriptor); + case input_size: + return sizeof(struct magno_input_report); + case feature_size: + return sizeof(struct magno_feature_report); + } + break; + case als_idx: + switch (descriptor_name) { + case descr_size: + return sizeof(als_report_descriptor); + case input_size: + return sizeof(struct als_input_report); + case feature_size: + return sizeof(struct als_feature_report); + } + break; + default: + break; + } + return 0; +} + +static void get_common_features(struct common_feature_property *common, int report_id) +{ + common->report_id = report_id; + common->connection_type = HID_USAGE_SENSOR_PROPERTY_CONNECTION_TYPE_PC_INTEGRATED_ENUM; + common->report_state = HID_USAGE_SENSOR_PROP_REPORTING_STATE_ALL_EVENTS_ENUM; + common->power_state = HID_USAGE_SENSOR_PROP_POWER_STATE_D0_FULL_POWER_ENUM; + common->sensor_state = HID_USAGE_SENSOR_STATE_INITIALIZING_ENUM; + common->report_interval = HID_DEFAULT_REPORT_INTERVAL; +} + +u8 get_feature_report(int sensor_idx, int report_id, u8 *feature_report) +{ + struct accel3_feature_report acc_feature; + struct gyro_feature_report gyro_feature; + struct magno_feature_report magno_feature; + struct als_feature_report als_feature; + u8 report_size = 0; + + if (!feature_report) + return report_size; + + switch (sensor_idx) { + case accel_idx: /* accel */ + get_common_features(&acc_feature.common_property, report_id); + acc_feature.accel_change_sesnitivity = HID_DEFAULT_SENSITIVITY; + acc_feature.accel_sensitivity_min = HID_DEFAULT_MIN_VALUE; + acc_feature.accel_sensitivity_max = HID_DEFAULT_MAX_VALUE; + memcpy(feature_report, &acc_feature, sizeof(acc_feature)); + report_size = sizeof(acc_feature); + break; + case gyro_idx: /* gyro */ + get_common_features(&gyro_feature.common_property, report_id); + gyro_feature.gyro_change_sesnitivity = HID_DEFAULT_SENSITIVITY; + gyro_feature.gyro_sensitivity_min = HID_DEFAULT_MIN_VALUE; + gyro_feature.gyro_sensitivity_max = HID_DEFAULT_MAX_VALUE; + memcpy(feature_report, &gyro_feature, sizeof(gyro_feature)); + report_size = sizeof(gyro_feature); + break; + case mag_idx: /* Magnetometer */ + get_common_features(&magno_feature.common_property, report_id); + magno_feature.magno_headingchange_sensitivity = HID_DEFAULT_SENSITIVITY; + magno_feature.heading_min = HID_DEFAULT_MIN_VALUE; + magno_feature.heading_max = HID_DEFAULT_MAX_VALUE; + magno_feature.flux_change_sensitivity = HID_DEFAULT_MIN_VALUE; + magno_feature.flux_min = HID_DEFAULT_MIN_VALUE; + magno_feature.flux_max = HID_DEFAULT_MAX_VALUE; + memcpy(feature_report, &magno_feature, sizeof(magno_feature)); + report_size = sizeof(magno_feature); + break; + case als_idx: /* ambient light sensor */ + get_common_features(&als_feature.common_property, report_id); + als_feature.als_change_sesnitivity = HID_DEFAULT_SENSITIVITY; + als_feature.als_sensitivity_min = HID_DEFAULT_MIN_VALUE; + als_feature.als_sensitivity_max = HID_DEFAULT_MAX_VALUE; + memcpy(feature_report, &als_feature, sizeof(als_feature)); + report_size = sizeof(als_feature); + break; + default: + break; + } + return report_size; +} + +static void get_common_inputs(struct common_input_property *common, int report_id) +{ + common->report_id = report_id; + common->sensor_state = HID_USAGE_SENSOR_STATE_READY_ENUM; + common->event_type = HID_USAGE_SENSOR_EVENT_DATA_UPDATED_ENUM; +} + +u8 get_input_report(int sensor_idx, int report_id, u8 *input_report, u32 *sensor_virt_addr) +{ + struct accel3_input_report acc_input; + struct gyro_input_report gyro_input; + struct magno_input_report magno_input; + struct als_input_report als_input; + u8 report_size = 0; + + if (!sensor_virt_addr || !input_report) + return report_size; + + switch (sensor_idx) { + case accel_idx: /* accel */ + get_common_inputs(&acc_input.common_property, report_id); + acc_input.in_accel_x_value = (int)sensor_virt_addr[0] / AMD_SFH_FW_MULTIPLIER; + acc_input.in_accel_y_value = (int)sensor_virt_addr[1] / AMD_SFH_FW_MULTIPLIER; + acc_input.in_accel_z_value = (int)sensor_virt_addr[2] / AMD_SFH_FW_MULTIPLIER; + memcpy(input_report, &acc_input, sizeof(acc_input)); + report_size = sizeof(acc_input); + break; + case gyro_idx: /* gyro */ + get_common_inputs(&gyro_input.common_property, report_id); + gyro_input.in_angel_x_value = (int)sensor_virt_addr[0] / AMD_SFH_FW_MULTIPLIER; + gyro_input.in_angel_y_value = (int)sensor_virt_addr[1] / AMD_SFH_FW_MULTIPLIER; + gyro_input.in_angel_z_value = (int)sensor_virt_addr[2] / AMD_SFH_FW_MULTIPLIER; + memcpy(input_report, &gyro_input, sizeof(gyro_input)); + report_size = sizeof(gyro_input); + break; + case mag_idx: /* Magnetometer */ + get_common_inputs(&magno_input.common_property, report_id); + magno_input.in_magno_x = (int)sensor_virt_addr[0] / AMD_SFH_FW_MULTIPLIER; + magno_input.in_magno_y = (int)sensor_virt_addr[1] / AMD_SFH_FW_MULTIPLIER; + magno_input.in_magno_z = (int)sensor_virt_addr[2] / AMD_SFH_FW_MULTIPLIER; + magno_input.in_magno_accuracy = (u16)sensor_virt_addr[3] / AMD_SFH_FW_MULTIPLIER; + memcpy(input_report, &magno_input, sizeof(magno_input)); + report_size = sizeof(magno_input); + break; + case als_idx: /* Als */ + get_common_inputs(&als_input.common_property, report_id); + als_input.illuminance_value = (int)sensor_virt_addr[0] / AMD_SFH_FW_MULTIPLIER; + report_size = sizeof(als_input); + memcpy(input_report, &als_input, sizeof(als_input)); + break; + default: + break; + } + return report_size; +} diff --git a/drivers/hid/amd-sfh-hid/hid_descriptor/amd_sfh_hid_desc.h b/drivers/hid/amd-sfh-hid/hid_descriptor/amd_sfh_hid_desc.h new file mode 100644 index 000000000000..ac9a01cc1454 --- /dev/null +++ b/drivers/hid/amd-sfh-hid/hid_descriptor/amd_sfh_hid_desc.h @@ -0,0 +1,121 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * HID report descriptors, structures and routines + * Copyright 2020 Advanced Micro Devices, Inc. + * Authors: Nehal Bakulchandra Shah + * Sandeep Singh + */ + +#ifndef AMD_SFH_HID_DESCRIPTOR_H +#define AMD_SFH_HID_DESCRIPTOR_H + +enum desc_type { + /* Report descriptor name */ + descr_size = 1, + input_size, + feature_size, +}; + +struct _hid_report_descriptor { + u8 bDescriptorType; + u8 wDescriptorLength; +}; + +struct common_feature_property { + /* common properties */ + u8 report_id; + u8 connection_type; + u8 report_state; + u8 power_state; + u8 sensor_state; + u32 report_interval; +} __packed; + +struct common_input_property { + /* common properties */ + u8 report_id; + u8 sensor_state; + u8 event_type; +} __packed; + +struct _hid_device_descriptor { + u8 bLength; + u8 bDescriptorType; + u8 bcdHID[2]; + u8 bCountryCode; + u8 bNumDescriptors; + struct _hid_report_descriptor *reports; +}; + +struct accel3_feature_report { + struct common_feature_property common_property; + /* properties specific to this sensor */ + u16 accel_change_sesnitivity; + s16 accel_sensitivity_max; + s16 accel_sensitivity_min; +} __packed; + +struct accel3_input_report { + struct common_input_property common_property; + /* values specific to this sensor */ + int in_accel_x_value; + int in_accel_y_value; + int in_accel_z_value; + /* include if required to support the "shake" event */ + u8 in_accel_shake_detection; +} __packed; + +struct gyro_feature_report { + struct common_feature_property common_property; + /* properties specific to this sensor */ + u16 gyro_change_sesnitivity; + s16 gyro_sensitivity_max; + s16 gyro_sensitivity_min; +} __packed; + +struct gyro_input_report { + struct common_input_property common_property; + /* values specific to this sensor */ + int in_angel_x_value; + int in_angel_y_value; + int in_angel_z_value; +} __packed; + +struct magno_feature_report { + struct common_feature_property common_property; + /*properties specific to this sensor */ + u16 magno_headingchange_sensitivity; + s16 heading_min; + s16 heading_max; + u16 flux_change_sensitivity; + s16 flux_min; + s16 flux_max; +} __packed; + +struct magno_input_report { + struct common_input_property common_property; + int in_magno_x; + int in_magno_y; + int in_magno_z; + int in_magno_accuracy; +} __packed; + +struct als_feature_report { + struct common_feature_property common_property; + /* properties specific to this sensor */ + u16 als_change_sesnitivity; + s16 als_sensitivity_max; + s16 als_sensitivity_min; +} __packed; + +struct als_input_report { + struct common_input_property common_property; + /* values specific to this sensor */ + int illuminance_value; +} __packed; + +int get_report_descriptor(int sensor_idx, u8 rep_desc[]); +u32 get_descr_sz(int sensor_idx, int descriptor_name); +u8 get_feature_report(int sensor_idx, int report_id, u8 *feature_report); +u8 get_input_report(int sensor_idx, int report_id, u8 *input_report, u32 *sensor_virt_addr); +#endif diff --git a/drivers/hid/amd-sfh-hid/hid_descriptor/amd_sfh_hid_report_desc.h b/drivers/hid/amd-sfh-hid/hid_descriptor/amd_sfh_hid_report_desc.h new file mode 100644 index 000000000000..44271d39b322 --- /dev/null +++ b/drivers/hid/amd-sfh-hid/hid_descriptor/amd_sfh_hid_report_desc.h @@ -0,0 +1,645 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * HID descriptor stuructures + * Copyright 2020 Advanced Micro Devices, Inc. + * Authors: Nehal Bakulchandra Shah + * Sandeep Singh + */ + +#ifndef AMD_SFH_HID_REPORT_DESCRIPTOR_H +#define AMD_SFH_HID_REPORT_DESCRIPTOR_H + +// Accelerometer 3D Sensor +static const u8 accel3_report_descriptor[] = { +0x05, 0x20, /* Usage page */ +0x09, 0x73, /* Motion type Accel 3D */ +0xA1, 0x00, /* HID Collection (Physical) */ + +//feature reports(xmit/receive) +0x85, 1, /* HID Report ID */ +0x05, 0x20, /* HID usage page sensor */ +0x0A, 0x09, 0x03, /* Sensor property and sensor connection type */ +0x15, 0, /* HID logical MIN_8(0) */ +0x25, 2, /* HID logical MAX_8(2) */ +0x75, 8, /* HID report size(8) */ +0x95, 1, /* HID report count(1) */ +0xA1, 0x02, /* HID collection (logical) */ +0x0A, 0x30, 0x08, /* Sensor property connection type intergated sel*/ +0x0A, 0x31, 0x08, /* Sensor property connection type attached sel */ +0x0A, 0x32, 0x08, /* Sensor property connection type external sel */ +0xB1, 0x00, /* HID feature (Data_Arr_Abs) */ +0xC0, /* HID end collection */ +0x0A, 0x16, 0x03, /* HID usage sensor property reporting state */ +0x15, 0, /* HID logical Min_8(0) */ +0x25, 5, /* HID logical Max_8(5) */ +0x75, 8, /* HID report size(8) */ +0x95, 1, /* HID report count(1) */ +0xA1, 0x02, /* HID collection(logical) */ +0x0A, 0x40, 0x08, /* Sensor property report state no events sel */ +0x0A, 0x41, 0x08, /* Sensor property report state all events sel */ +0x0A, 0x42, 0x08, /* Sensor property report state threshold events sel */ +0x0A, 0x43, 0x08, /* Sensor property report state no events wake sel */ +0x0A, 0x44, 0x08, /* Sensor property report state all events wake sel */ +0x0A, 0x45, 0x08, /* Sensor property report state threshold events wake sel */ +0xB1, 0x00, /* HID feature (Data_Arr_Abs) */ +0xC0, /* HID end collection */ +0x0A, 0x19, 0x03, /* HID usage sensor property power state */ +0x15, 0, /* HID logical Min_8(0) */ +0x25, 5, /* HID logical Max_8(5) */ +0x75, 8, /* HID report size(8) */ +0x95, 1, /* HID report count(1) */ +0xA1, 0x02, /* HID collection(logical) */ +0x0A, 0x50, 0x08, /* Sensor property power state undefined sel */ +0x0A, 0x51, 0x08, /* Sensor property power state D0 full power sel */ +0x0A, 0x52, 0x08, /* Sensor property power state D1 low power sel */ +0x0A, 0x53, 0x08, /* Sensor property power state D2 standby with wake sel */ +0x0A, 0x54, 0x08, /* Sensor property power state D3 sleep with wake sel */ +0x0A, 0x55, 0x08, /* Sensor property power state D4 power off sel */ +0xB1, 0x00, /* HID feature (Data_Arr_Abs) */ +0xC0, /* HID end collection */ +0x0A, 0x01, 0x02, /* HID usage sensor state */ +0x15, 0, /* HID logical Min_8(0) */ +0x25, 6, /* HID logical Max_8(6) */ +0x75, 8, /* HID report size(8) */ +0x95, 1, /* HID report count(1) */ +0xA1, 0x02, /* HID collection(logical) */ +0x0A, 0x00, 0x08, /* HID usage sensor state unknown sel */ +0x0A, 0x01, 0x08, /* HID usage sensor state ready sel */ +0x0A, 0x02, 0x08, /* HID usage sensor state not available sel */ +0x0A, 0x03, 0x08, /* HID usage sensor state no data sel */ +0x0A, 0x04, 0x08, /* HID usage sensor state initializing sel */ +0x0A, 0x05, 0x08, /* HID usage sensor state access denied sel */ +0x0A, 0x06, 0x08, /* HID usage sensor state error sel */ +0xB1, 0x00, /* HID feature (Data_Arr_Abs) */ +0xC0, /* HID end collection */ +0x0A, 0x0E, 0x03, /* HID usage sensor property report interval */ +0x15, 0, /* HID logical Min_8(0) */ +0x27, 0xFF, 0xFF, 0xFF, 0xFF, /* HID logical Max_32 */ + +0x75, 32, /* HID report size(32) */ +0x95, 1, /* HID report count(1) */ +0x55, 0, /* HID unit exponent(0) */ +0xB1, 0x02, /* HID feature (Data_Arr_Abs) */ +0x0A, 0x52, 0x14, /* Sensor data motion accel and mod change sensitivity ABS) */ + +0x15, 0, /* HID logical Min_8(0) */ +0x26, 0xFF, 0xFF, /* HID logical Max_16(0xFF,0xFF) */ + +0x75, 16, /* HID report size(16) */ +0x95, 1, /* HID report count(1) */ +0x55, 0x0E, /* HID unit exponent(0x0E) */ +0xB1, 0x02, /* HID feature (Data_Arr_Abs) */ +0x0A, 0x52, 0x24, /* HID usage sensor data (motion accel and mod max) */ + +0x16, 0x01, 0x80, /* HID logical Min_16(0x01,0x80) */ + +0x26, 0xFF, 0x7F, /* HID logical Max_16(0xFF,0x7F) */ + +0x75, 16, /* HID report size(16) */ +0x95, 1, /* HID report count(1) */ +0x55, 0x0E, /* HID unit exponent(0x0E) */ +0xB1, 0x02, /* HID feature (Data_Arr_Abs) */ +0x0A, 0x52, 0x34, /* HID usage sensor data (motion accel and mod min) */ + +0x16, 0x01, 0x80, /* HID logical Min_16(0x01,0x80) */ + +0x26, 0xFF, 0x7F, /* HID logical Max_16(0xFF,0x7F) */ + +0x75, 16, /* HID report size(16) */ +0x95, 1, /* HID report count(1) */ +0x55, 0x0E, /* HID unit exponent(0x0E) */ +0xB1, 0x02, /* HID feature (Data_Arr_Abs) */ + +//input report (transmit) +0x05, 0x20, /* HID usage page sensors */ +0x0A, 0x01, 0x02, /* HID usage sensor state */ +0x15, 0, /* HID logical Min_8(0) */ +0x25, 6, /* HID logical Max_8(6) */ +0x75, 8, /* HID report size(8) */ +0x95, 1, /* HID report count (1) */ +0xA1, 0x02, /* HID end collection (logical) */ +0x0A, 0x00, 0x08, /* HID usage sensor state unknown sel */ +0x0A, 0x01, 0x08, /* HID usage sensor state ready sel */ +0x0A, 0x02, 0x08, /* HID usage sensor state not available sel */ +0x0A, 0x03, 0x08, /* HID usage sensor state no data sel */ +0x0A, 0x04, 0x08, /* HID usage sensor state initializing sel */ +0x0A, 0x05, 0x08, /* HID usage sensor state access denied sel */ +0x0A, 0x06, 0x08, /* HID usage sensor state error sel */ +0X81, 0x00, /* HID Input (Data_Arr_Abs) */ +0xC0, /* HID end collection */ +0x0A, 0x02, 0x02, /* HID usage sensor event */ +0x15, 0, /* HID logical Min_8(0) */ +0x25, 5, /* HID logical Max_8(5) */ +0x75, 8, /* HID report size(8) */ +0x95, 1, /* HID report count (1) */ +0xA1, 0x02, /* HID end collection (logical) */ +0x0A, 0x10, 0x08, /* HID usage sensor event unknown sel */ +0x0A, 0x11, 0x08, /* HID usage sensor event state changed sel */ +0x0A, 0x12, 0x08, /* HID usage sensor event property changed sel */ +0x0A, 0x13, 0x08, /* HID usage sensor event data updated sel */ +0x0A, 0x14, 0x08, /* HID usage sensor event poll response sel */ +0x0A, 0x15, 0x08, /* HID usage sensor event change sensitivity sel */ +0X81, 0x00, /* HID Input (Data_Arr_Abs) */ +0xC0, /* HID end collection */ +0x0A, 0x53, 0x04, /* HID usage sensor data motion Acceleration X axis */ +0x17, 0x00, 0x00, 0x01, 0x80, /* HID logical Min_32 */ + +0x27, 0xFF, 0xff, 0XFF, 0XFF, /* HID logical Max_32 */ + +0x75, 32, /* HID report size(32) */ +0x95, 1, /* HID report count (1) */ +0x55, 0x0E, /* HID unit exponent(0x0E) */ +0X81, 0x02, /* HID Input (Data_Arr_Abs) */ +0x0A, 0x54, 0x04, /* HID usage sensor data motion Acceleration Y axis */ +0x17, 0X00, 0X00, 0x01, 0x80, /* HID logical Min_32 */ + +0x27, 0xFF, 0xFF, 0XFF, 0XFF, /* HID logical Max_32 */ + +0x75, 32, /* HID report size(32) */ +0x95, 1, /* HID report count (1) */ +0x55, 0x0E, /* HID unit exponent(0x0E) */ +0X81, 0x02, /* HID Input (Data_Arr_Abs) */ +0x0A, 0x55, 0x04, /* HID usage sensor data motion Acceleration Z axis */ +0x17, 0X00, 0X00, 0x01, 0x80, /* HID logical Min_32 */ + +0x27, 0XFF, 0XFF, 0xFF, 0x7F, /* HID logical Max_32 */ + +0x75, 32, /* HID report size(32) */ +0x95, 1, /* HID report count (1) */ +0x55, 0x0E, /* HID unit exponent(0x0E) */ +0X81, 0x02, /* HID Input (Data_Arr_Abs) */ + +0x0A, 0x51, 0x04, /* HID usage sensor data motion state */ +0x15, 0, /* HID logical Min_8(0) False = Still*/ +0x25, 1, /* HID logical Min_8(1) True = In motion */ +0x75, 8, /* HID report size(8) */ +0x95, 1, /* HID report count (1) */ +0X81, 0x02, /* HID Input (Data_Arr_Abs) */ +0xC0 /* HID end collection */ +}; + +const u8 gyro3_report_descriptor[] = { +0x05, 0x20, /* Usage page */ +0x09, 0x76, /* Motion type Gyro3D */ +0xA1, 0x00, /* HID Collection (Physical) */ + +0x85, 2, /* HID Report ID */ +0x05, 0x20, /* HID usage page sensor */ +0x0A, 0x09, 0x03, /* Sensor property and sensor connection type */ +0x15, 0, /* HID logical MIN_8(0) */ +0x25, 2, /* HID logical MAX_8(2) */ +0x75, 8, /* HID report size(8) */ +0x95, 1, /* HID report count(1) */ +0xA1, 0x02, /* HID collection (logical) */ +0x0A, 0x30, 0x08, /* Sensor property connection type intergated sel */ +0x0A, 0x31, 0x08, /* Sensor property connection type attached sel */ +0x0A, 0x32, 0x08, /* Sensor property connection type external sel */ +0xB1, 0x00, /* HID feature (Data_Arr_Abs) */ +0xC0, /* HID end collection */ +0x0A, 0x16, 0x03, /* HID usage sensor property reporting state */ +0x15, 0, /* HID logical Min_8(0) */ +0x25, 5, /* HID logical Max_8(5) */ +0x75, 8, /* HID report size(8) */ +0x95, 1, /* HID report count(1) */ +0xA1, 0x02, /* HID collection(logical) */ +0x0A, 0x40, 0x08, /* Sensor reporting state no events sel */ +0x0A, 0x41, 0x08, /* Sensor reporting state all events sel */ +0x0A, 0x42, 0x08, /* Sensor reporting state threshold events sel */ +0x0A, 0x43, 0x08, /* Sensor reporting state no events wake sel */ +0x0A, 0x44, 0x08, /* Sensor reporting state all events wake sel */ +0x0A, 0x45, 0x08, /* Sensor reporting state threshold events wake sel */ +0xB1, 0x00, /* HID feature (Data_Arr_Abs) */ +0xC0, /* HID end collection */ +0x0A, 0x19, 0x03, /* HID usage sensor property power state */ +0x15, 0, /* HID logical Min_8(0) */ +0x25, 5, /* HID logical Max_8(5) */ +0x75, 8, /* HID report size(8) */ +0x95, 1, /* HID report count(1) */ +0xA1, 0x02, /* HID collection(logical) */ +0x0A, 0x50, 0x08, /* Sensor power state undefined sel */ +0x0A, 0x51, 0x08, /* Sensor power state D0 full power sel */ +0x0A, 0x52, 0x08, /* Sensor power state D1 low power sel */ +0x0A, 0x53, 0x08, /* Sensor power state D2 standby with wake sel */ +0x0A, 0x54, 0x08, /* Sensor power state D3 sleep with wake sel */ +0x0A, 0x55, 0x08, /* Sensor power state D4 power off sel */ +0xB1, 0x00, /* HID feature (Data_Arr_Abs) */ +0xC0, /* HID end collection */ +0x0A, 0x01, 0x02, /* HID usage sensor state */ +0x15, 0, /* HID logical Min_8(0) */ +0x25, 6, /* HID logical Max_8(6) */ +0x75, 8, /* HID report size(8) */ +0x95, 1, /* HID report count(1) */ +0xA1, 0x02, /* HID collection(logical) */ +0x0A, 0x00, 0x08, /* HID usage sensor state unknown sel */ +0x0A, 0x01, 0x08, /* HID usage sensor state ready sel */ +0x0A, 0x02, 0x08, /* HID usage sensor state not available sel */ +0x0A, 0x03, 0x08, /* HID usage sensor state no data sel */ +0x0A, 0x04, 0x08, /* HID usage sensor state initializing sel */ +0x0A, 0x05, 0x08, /* HID usage sensor state access denied sel */ +0x0A, 0x06, 0x08, /* HID usage sensor state error sel */ +0xB1, 0x00, /* HID feature (Data_Arr_Abs) */ +0xC0, /* HID end collection */ +0x0A, 0x0E, 0x03, /* HID usage sensor property report interval */ +0x15, 0, /* HID logical Min_8(0) */ +0x27, 0xFF, 0xFF, 0xFF, 0xFF, /* HID logical Max_32 */ + +0x75, 32, /* HID report size(32) */ +0x95, 1, /* HID report count(1) */ +0x55, 0, /* HID unit exponent(0) */ +0xB1, 0x02, /* HID feature (Data_Arr_Abs) */ +0x0A, 0x56, 0x14, /* Angular velocity and mod change sensitivity ABS)*/ + +0x15, 0, /* HID logical Min_8(0) */ +0x26, 0xFF, 0xFF, /* HID logical Max_16(0xFF,0xFF) */ + +0x75, 16, /* HID report size(16) */ +0x95, 1, /* HID report count(1) */ +0x55, 0x0E, /* HID unit exponent(0x0E) */ +0xB1, 0x02, /* HID feature (Data_Arr_Abs) */ +0x0A, 0x56, 0x24, /* Sensor data (motion angular velocity and mod max) */ + +0x16, 0x01, 0x80, /* HID logical Min_16(0x01,0x80) */ + +0x26, 0xFF, 0x7F, /* HID logical Max_16(0xFF,0x7F) */ + +0x75, 16, /* HID report size(16) */ +0x95, 1, /* HID report count(1) */ +0x55, 0x0E, /* HID unit exponent(0x0E) */ +0xB1, 0x02, /* HID feature (Data_Arr_Abs) */ +0x0A, 0x56, 0x34, /* HID usage sensor data (motion accel and mod min) */ + +0x16, 0x01, 0x80, /* HID logical Min_16(0x01,0x80) */ + +0x26, 0xFF, 0x7F, /* HID logical Max_16(0xFF,0x7F) */ + +0x75, 16, /* HID report size(16) */ +0x95, 1, /* HID report count(1) */ +0x55, 0x0E, /* HID unit exponent(0x0E) */ +0xB1, 0x02, /* HID feature (Data_Arr_Abs) */ + +//Input reports(transmit) +0x05, 0x20, /* HID usage page sensors */ +0x0A, 0x01, 0x02, /* HID usage sensor state */ +0x15, 0, /* HID logical Min_8(0) */ +0x25, 6, /* HID logical Max_8(6) */ +0x75, 8, /* HID report size(8) */ +0x95, 1, /* HID report count (1) */ +0xA1, 0x02, /* HID end collection (logical) */ +0x0A, 0x00, 0x08, /* HID usage sensor state unknown sel */ +0x0A, 0x01, 0x08, /* HID usage sensor state ready sel */ +0x0A, 0x02, 0x08, /* HID usage sensor state not available sel */ +0x0A, 0x03, 0x08, /* HID usage sensor state no data sel */ +0x0A, 0x04, 0x08, /* HID usage sensor state initializing sel */ +0x0A, 0x05, 0x08, /* HID usage sensor state access denied sel */ +0x0A, 0x06, 0x08, /* HID usage sensor state error sel */ +0X81, 0x00, /* HID Input (Data_Arr_Abs) */ +0xC0, /* HID end collection */ +0x0A, 0x02, 0x02, /* HID usage sensor event */ +0x15, 0, /* HID logical Min_8(0) */ +0x25, 5, /* HID logical Max_8(5) */ +0x75, 8, /* HID report size(8) */ +0x95, 1, /* HID report count (1) */ +0xA1, 0x02, /* HID end collection (logical) */ +0x0A, 0x10, 0x08, /* HID usage sensor event unknown sel */ +0x0A, 0x11, 0x08, /* HID usage sensor event state changed sel */ +0x0A, 0x12, 0x08, /* HID usage sensor event property changed sel */ +0x0A, 0x13, 0x08, /* HID usage sensor event data updated sel */ +0x0A, 0x14, 0x08, /* HID usage sensor event poll response sel */ +0x0A, 0x15, 0x08, /* HID usage sensor event change sensitivity sel */ +0X81, 0x00, /* HID Input (Data_Arr_Abs) */ +0xC0, /* HID end collection */ +0x0A, 0x57, 0x04, /* Sensor data motion Angular velocity X axis */ +0x17, 0x00, 0x00, 0x01, 0x80, /* HID logical Min_32 */ + +0x27, 0xFF, 0xFF, 0xFF, 0x7F, /* HID logical Max_32 */ + +0x75, 32, /* HID report size(32) */ +0x95, 1, /* HID report count (1) */ +0x55, 0x0E, /* HID unit exponent(0x0E) */ +0X81, 0x02, /* HID Input (Data_Arr_Abs) */ +0x0A, 0x58, 0x04, /* Sensor data motion Angular velocity Y axis */ +0x17, 0x00, 0x00, 0x01, 0x80, /* HID logical Min_32 */ + +0x27, 0xFF, 0xFF, 0xFF, 0x7F, /* HID logical Max_32 */ + +0x75, 32, /* HID report size(32) */ +0x95, 1, /* HID report count (1) */ +0x55, 0x0E, /* HID unit exponent(0x0E) */ +0X81, 0x02, /* HID Input (Data_Arr_Abs) */ +0x0A, 0x59, 0x04, /* Sensor data motion Angular velocity Z axis */ +0x17, 0x00, 0x00, 0x01, 0x80, /* HID logical Min_32 */ + +0x27, 0xFF, 0xFF, 0xFF, 0x7F, /* HID logical Max_32 */ + +0x75, 32, /* HID report size(32) */ +0x95, 1, /* HID report count (1) */ +0x55, 0x0E, /* HID unit exponent(0x0E) */ +0X81, 0x02, /* HID Input (Data_Arr_Abs) */ + +0xC0, /* HID end collection */ +}; + +const u8 comp3_report_descriptor[] = { +0x05, 0x20, /* Usage page */ +0x09, 0x83, /* Motion type Orientation compass 3D */ +0xA1, 0x00, /* HID Collection (Physical) */ + +0x85, 3, /* HID Report ID */ +0x05, 0x20, /* HID usage page sensor */ +0x0A, 0x09, 0x03, /* Sensor property and sensor connection type */ +0x15, 0, /* HID logical MIN_8(0) */ +0x25, 2, /* HID logical MAX_8(2) */ +0x75, 8, /* HID report size(8) */ +0x95, 1, /* HID report count(1) */ +0xA1, 0x02, /* HID collection (logical) */ +0x0A, 0x30, 0x08, /* Sensor property connection type intergated sel */ +0x0A, 0x31, 0x08, /* Sensor property connection type attached sel */ +0x0A, 0x32, 0x08, /* Sensor property connection type external sel */ +0xB1, 0x00, /* HID feature (Data_Arr_Abs) */ +0xC0, /* HID end collection */ +0x0A, 0x16, 0x03, /* HID usage sensor property reporting state */ +0x15, 0, /* HID logical Min_8(0) */ +0x25, 5, /* HID logical Max_8(5) */ +0x75, 8, /* HID report size(8) */ +0x95, 1, /* HID report count(1) */ +0xA1, 0x02, /* HID collection(logical) */ +0x0A, 0x40, 0x08, /* Sensor reporting state no events sel */ +0x0A, 0x41, 0x08, /* Sensor reporting state all events sel */ +0x0A, 0x42, 0x08, /* Sensor reporting state threshold events sel */ +0x0A, 0x43, 0x08, /* Sensor reporting state no events wake sel */ +0x0A, 0x44, 0x08, /* Sensor reporting state all events wake sel */ +0x0A, 0x45, 0x08, /* Sensor reporting state threshold events wake sel */ +0xB1, 0x00, /* HID feature (Data_Arr_Abs) */ +0xC0, /* HID end collection */ +0x0A, 0x19, 0x03, /* HID usage sensor property power state */ +0x15, 0, /* HID logical Min_8(0) */ +0x25, 5, /* HID logical Max_8(5) */ +0x75, 8, /* HID report size(8) */ +0x95, 1, /* HID report count(1) */ +0xA1, 0x02, /* HID collection(logical) */ +0x0A, 0x50, 0x08, /* Sensor power state undefined sel */ +0x0A, 0x51, 0x08, /* Sensor power state D0 full power sel */ +0x0A, 0x52, 0x08, /* Sensor power state D1 low power sel */ +0x0A, 0x53, 0x08, /* Sensor power state D2 standby with wake sel */ +0x0A, 0x54, 0x08, /* Sensor power state D3 sleep with wake sel */ +0x0A, 0x55, 0x08, /* Sensor power state D4 power off sel */ +0xB1, 0x00, /* HID feature (Data_Arr_Abs) */ +0xC0, /* HID end collection */ +0x0A, 0x01, 0x02, /* HID usage sensor state */ +0x15, 0, /* HID logical Min_8(0) */ +0x25, 6, /* HID logical Max_8(6) */ +0x75, 8, /* HID report size(8) */ +0x95, 1, /* HID report count(1) */ +0xA1, 0x02, /* HID collection(logical) */ +0x0A, 0x00, 0x08, /* HID usage sensor state unknown sel */ +0x0A, 0x01, 0x08, /* HID usage sensor state ready sel */ +0x0A, 0x02, 0x08, /* HID usage sensor state not available sel */ +0x0A, 0x03, 0x08, /* HID usage sensor state no data sel */ +0x0A, 0x04, 0x08, /* HID usage sensor state initializing sel */ +0x0A, 0x05, 0x08, /* HID usage sensor state access denied sel */ +0x0A, 0x06, 0x08, /* HID usage sensor state error sel */ +0xB1, 0x00, /* HID feature (Data_Arr_Abs) */ +0xC0, /* HID end collection */ +0x0A, 0x0E, 0x03, /* HID usage sensor property report interval */ +0x15, 0, /* HID logical Min_8(0) */ +0x27, 0xFF, 0xFF, 0xFF, 0xFF, /* HID logical Max_32 */ +0x75, 32, /* HID report size(32) */ +0x95, 1, /* HID report count(1) */ +0x55, 0, /* HID unit exponent(0) */ +0xB1, 0x02, /* HID feature (Data_Arr_Abs) */ +0x0A, 0x71, 0x14, /* Orientation and mod change sensitivity ABS)*/ +0x15, 0, /* HID logical Min_8(0) */ +0x26, 0xFF, 0xFF, /* HID logical Max_16(0xFF,0xFF) */ +0x75, 16, /* HID report size(16) */ +0x95, 1, /* HID report count(1) */ +0x55, 0x0E, /* HID unit exponent(0x0E) */ +0xB1, 0x02, /* HID feature (Data_Arr_Abs) */ +0x0A, 0x71, 0x24, /* Sensor data (motion orientation and mod max) */ +0x16, 0x01, 0x80, /* HID logical Min_16(0x01,0x80) */ +0x26, 0xFF, 0x7F, /* HID logical Max_16(0xFF,0x7F) */ +0x75, 16, /* HID report size(16) */ +0x95, 1, /* HID report count(1) */ +0x55, 0x0F, /* HID unit exponent(0x0F) */ +0xB1, 0x02, /* HID feature (Data_Arr_Abs) */ +0x0A, 0x71, 0x34, /* Sensor data (motion orientation and mod min) */ +0x16, 0x01, 0x80, /* HID logical Min_16(0x01,0x80) */ +0x26, 0xFF, 0x7F, /* HID logical Max_16(0xFF,0x7F) */ +0x75, 16, /* HID report size(16) */ +0x95, 1, /* HID report count(1) */ +0x55, 0x0F, /* HID unit exponent(0x0F) */ +0xB1, 0x02, /* HID feature (Data_Arr_Abs) */ +0x0A, 0x84, 0x14, /* Maganetic flux and change sensitivity ABS) */ +0x15, 0, /* HID logical Min_8(0) */ +0x26, 0xFF, 0xFF, /* HID logical Max_16(0xFF,0xFF) */ +0x75, 16, /* HID report size(16) */ +0x95, 1, /* HID report count(1) */ +0x55, 0x0E, /* HID unit exponent(0x0E) */ +0xB1, 0x02, /* HID feature (Data_Arr_Abs) */ +0x0A, 0x84, 0x24, /* Maganetic flux and mod change sensitivity Max) */ +0x16, 0x01, 0x80, /* HID logical Min_16(0x01,0x80) */ +0x26, 0xFF, 0x7F, /* HID logical Max_16(0xFF,0x7F) */ +0x75, 16, /* HID report size(16) */ +0x95, 1, /* HID report count(1) */ +0x55, 0x0F, /* HID unit exponent(0x0F) */ +0xB1, 0x02, /* HID feature (Data_Arr_Abs) */ +0x0A, 0x84, 0x34, /* Maganetic flux and mod change sensitivity Min */ +0x16, 0x01, 0x80, /* HID logical Min_16(0x01,0x80) */ +0x26, 0xFF, 0x7F, /* HID logical Max_16(0xFF,0x7F) */ +0x75, 16, /* HID report size(16) */ +0x95, 1, /* HID report count(1) */ +0x55, 0x0F, /* HID unit exponent(0x0F) */ +0xB1, 0x02, /* HID feature (Data_Arr_Abs) */ + +//Input reports(transmit) +0x05, 0x20, /* HID usage page sensors */ +0x0A, 0x01, 0x02, /* HID usage sensor state */ +0x15, 0, /* HID logical Min_8(0) */ +0x25, 6, /* HID logical Max_8(6) */ +0x75, 8, /* HID report size(8) */ +0x95, 1, /* HID report count (1) */ +0xA1, 0x02, /* HID end collection (logical) */ +0x0A, 0x00, 0x08, /* HID usage sensor state unknown sel */ +0x0A, 0x01, 0x08, /* HID usage sensor state ready sel */ +0x0A, 0x02, 0x08, /* HID usage sensor state not available sel */ +0x0A, 0x03, 0x08, /* HID usage sensor state no data sel */ +0x0A, 0x04, 0x08, /* HID usage sensor state initializing sel */ +0x0A, 0x05, 0x08, /* HID usage sensor state access denied sel */ +0x0A, 0x06, 0x08, /* HID usage sensor state error sel */ +0X81, 0x00, /* HID Input (Data_Arr_Abs) */ +0xC0, /* HID end collection */ +0x0A, 0x02, 0x02, /* HID usage sensor event */ +0x15, 0, /* HID logical Min_8(0) */ +0x25, 5, /* HID logical Max_8(5) */ +0x75, 8, /* HID report size(8) */ +0x95, 1, /* HID report count (1) */ +0xA1, 0x02, /* HID end collection (logical) */ +0x0A, 0x10, 0x08, /* HID usage sensor event unknown sel */ +0x0A, 0x11, 0x08, /* HID usage sensor event state changed sel */ +0x0A, 0x12, 0x08, /* HID usage sensor event property changed sel */ +0x0A, 0x13, 0x08, /* HID usage sensor event data updated sel */ +0x0A, 0x14, 0x08, /* HID usage sensor event poll response sel */ +0x0A, 0x15, 0x08, /* HID usage sensor event change sensitivity sel */ +0X81, 0x00, /* HID Input (Data_Arr_Abs) */ +0xC0, /* HID end collection */ +0x0A, 0x85, 0x04, /* Sensor data orientation magnetic flux X axis */ +0x17, 0x00, 0x00, 0x01, 0x80, /* HID logical Min_32 */ +0x27, 0xFF, 0xFF, 0xFF, 0x7F, /* HID logical Max_32 */ +0x75, 32, /* HID report size(32) */ +0x95, 1, /* HID report count (1) */ +0x55, 0x0D, /* HID unit exponent(0x0D) */ +0X81, 0x02, /* HID Input (Data_Arr_Abs) */ +0x0A, 0x86, 0x04, /* Sensor data orientation magnetic flux Y axis */ +0x17, 0x00, 0x00, 0x01, 0x80, /* HID logical Min_32 */ +0x27, 0xFF, 0xFF, 0xFF, 0x7F, /* HID logical Max_32 */ +0x75, 32, /* HID report size(32) */ +0x95, 1, /* HID report count (1) */ +0x55, 0x0D, /* HID unit exponent(0x0D) */ +0X81, 0x02, /* HID Input (Data_Arr_Abs) */ +0x0A, 0x87, 0x04, /* Sensor data orientation magnetic flux Z axis */ +0x17, 0x00, 0x00, 0x01, 0x80, /* HID logical Min_32 */ +0x27, 0xFF, 0xFF, 0xFF, 0x7F, /* HID logical Max_32 */ +0x75, 32, /* HID report size(32) */ +0x95, 1, /* HID report count (1) */ +0x55, 0x0D, /* HID unit exponent(0x0D) */ +0X81, 0x02, /* HID Input (Data_Arr_Abs) */ +0x0A, 0x88, 0x04, /* Sensor data orientation magnetometer accuracy */ +0x17, 0x00, 0x00, 0x01, 0x80, /* HID logical Min_32 */ +0x27, 0xFF, 0xFF, 0xFF, 0x7F, /* HID logical Max_32 */ +0x75, 32, /* HID report size(32) */ +0x95, 1, /* HID report count (1) */ +0X81, 0x02, /* HID Input (Data_Arr_Abs) */ +0xC0 /* HID end collection */ +}; + +const u8 als_report_descriptor[] = { +0x05, 0x20, /* HID usage page sensor */ +0x09, 0x41, /* HID usage sensor type Ambientlight */ +0xA1, 0x00, /* HID Collection (Physical) */ + +//feature reports(xmit/receive)// +0x85, 4, /* HID Report ID */ +0x05, 0x20, /* HID usage page sensor */ +0x0A, 0x09, 0x03, /* Sensor property and sensor connection type */ +0x15, 0, /* HID logical MIN_8(0) */ +0x25, 2, /* HID logical MAX_8(2) */ +0x75, 8, /* HID report size(8) */ +0x95, 1, /* HID report count(1) */ +0xA1, 0x02, /* HID collection (logical) */ +0x0A, 0x30, 0x08, /* Sensor property connection type intergated sel */ +0x0A, 0x31, 0x08, /* Sensor property connection type attached sel */ +0x0A, 0x32, 0x08, /* Sensor property connection type external sel */ +0xB1, 0x00, /* HID feature (Data_Arr_Abs) */ +0xC0, /* HID end collection */ +0x0A, 0x16, 0x03, /* HID usage sensor property reporting state */ +0x15, 0, /* HID logical Min_8(0) */ +0x25, 5, /* HID logical Max_8(5) */ +0x75, 8, /* HID report size(8) */ +0x95, 1, /* HID report count(1) */ +0xA1, 0x02, /* HID collection(logical) */ +0x0A, 0x40, 0x08, /* Sensor reporting state no events sel */ +0x0A, 0x41, 0x08, /* Sensor reporting state all events sel */ +0x0A, 0x42, 0x08, /* Sensor reporting state threshold events sel */ +0x0A, 0x43, 0x08, /* Sensor reporting state no events wake sel */ +0x0A, 0x44, 0x08, /* Sensor reporting state all events wake sel */ +0x0A, 0x45, 0x08, /* Sensor reporting state threshold events wake sel */ +0xB1, 0x00, /* HID feature (Data_Arr_Abs) */ +0xC0, /* HID end collection */ +0x0A, 0x19, 0x03, /* HID usage sensor property power state */ +0x15, 0, /* HID logical Min_8(0) */ +0x25, 5, /* HID logical Max_8(5) */ +0x75, 8, /* HID report size(8) */ +0x95, 1, /* HID report count(1) */ +0xA1, 0x02, /* HID collection(logical) */ +0x0A, 0x50, 0x08, /* Sensor power state undefined sel */ +0x0A, 0x51, 0x08, /* Sensor power state D0 full power sel */ +0x0A, 0x52, 0x08, /* Sensor power state D1 low power sel */ +0x0A, 0x53, 0x08, /* Sensor power state D2 standby with wake sel */ +0x0A, 0x54, 0x08, /* Sensor power state D3 sleep with wake sel */ +0x0A, 0x55, 0x08, /* Sensor power state D4 power off sel */ +0xB1, 0x00, /* HID feature (Data_Arr_Abs) */ +0xC0, /* HID end collection */ +0x0A, 0x01, 0x02, /* HID usage sensor state */ +0x15, 0, /* HID logical Min_8(0) */ +0x25, 6, /* HID logical Max_8(6) */ +0x75, 8, /* HID report size(8) */ +0x95, 1, /* HID report count(1) */ +0xA1, 0x02, /* HID collection(logical) */ +0x0A, 0x00, 0x08, /* HID usage sensor state unknown sel */ +0x0A, 0x01, 0x08, /* HID usage sensor state ready sel */ +0x0A, 0x02, 0x08, /* HID usage sensor state not available sel */ +0x0A, 0x03, 0x08, /* HID usage sensor state no data sel */ +0x0A, 0x04, 0x08, /* HID usage sensor state initializing sel */ +0x0A, 0x05, 0x08, /* HID usage sensor state access denied sel */ +0x0A, 0x06, 0x08, /* HID usage sensor state error sel */ +0xB1, 0x00, /* HID feature (Data_Arr_Abs) */ +0xC0, /* HID end collection */ +0x0A, 0x0E, 0x03, /* HID usage sensor property report interval */ +0x15, 0, /* HID logical Min_8(0) */ +0x27, 0xFF, 0xFF, 0xFF, 0xFF, /* HID logical Max_32 */ +0x75, 32, /* HID report size(32) */ +0x95, 1, /* HID report count(1) */ +0x55, 0, /* HID unit exponent(0) */ +0xB1, 0x02, /* HID feature (Data_Arr_Abs) */ +0x0A, 0xD1, 0xE4, /* Light illuminance and sensitivity REL PCT) */ +0x15, 0, /* HID logical Min_8(0) */ +0x26, 0x10, 0x27, /* HID logical Max_16(0x10,0x27) */ +0x75, 16, /* HID report size(16) */ +0x95, 1, /* HID report count(1) */ +0x55, 0x0E, /* HID unit exponent(0x0E) */ +0xB1, 0x02, /* HID feature (Data_Arr_Abs) */ +0x0A, 0xD1, 0x24, /* Sensor data (Light illuminance and mod max) */ +0x15, 0, /* HID logical Min_8(0) */ +0x26, 0xFF, 0xFF, /* HID logical Max_16(0xFF,0xFF) */ +0x75, 16, /* HID report size(16) */ +0x95, 1, /* HID report count(1) */ +0x55, 0x0F, /* HID unit exponent(0x0F) */ +0xB1, 0x02, /* HID feature (Data_Arr_Abs) */ +0x0A, 0xD1, 0x34, /* Sensor data (Light illuminance and mod min) */ +0x15, 0, /* HID logical Min_8(0) */ +0x26, 0xFF, 0xFF, /* HID logical Max_16(0xFF,0xFF) */ +0x75, 16, /* HID report size(16) */ +0x95, 1, /* HID report count(1) */ +0x55, 0x0F, /* HID unit exponent(0x0F) */ +0xB1, 0x02, /* HID feature (Data_Arr_Abs) */ + +//Input reports (transmit) +0x05, 0x20, /* HID usage page sensors */ +0x0A, 0x01, 0x02, /* HID usage sensor state */ +0x15, 0, /* HID logical Min_8(0) */ +0x25, 6, /* HID logical Max_8(6) */ +0x75, 8, /* HID report size(8) */ +0x95, 1, /* HID report count (1) */ +0xA1, 0x02, /* HID end collection (logical) */ +0x0A, 0x00, 0x08, /* HID usage sensor state unknown sel */ +0x0A, 0x01, 0x08, /* HID usage sensor state ready sel */ +0x0A, 0x02, 0x08, /* HID usage sensor state not available sel */ +0x0A, 0x03, 0x08, /* HID usage sensor state no data sel */ +0x0A, 0x04, 0x08, /* HID usage sensor state initializing sel */ +0x0A, 0x05, 0x08, /* HID usage sensor state access denied sel */ +0x0A, 0x06, 0x08, /* HID usage sensor state error sel */ +0X81, 0x00, /* HID Input (Data_Arr_Abs) */ +0xC0, /* HID end collection */ +0x0A, 0x02, 0x02, /* HID usage sensor event */ +0x15, 0, /* HID logical Min_8(0) */ +0x25, 5, /* HID logical Max_8(5) */ +0x75, 8, /* HID report size(8) */ +0x95, 1, /* HID report count (1) */ +0xA1, 0x02, /* HID end collection (logical) */ +0x0A, 0x10, 0x08, /* HID usage sensor event unknown sel */ +0x0A, 0x11, 0x08, /* HID usage sensor event state changed sel */ +0x0A, 0x12, 0x08, /* HID usage sensor event property changed sel */ +0x0A, 0x13, 0x08, /* HID usage sensor event data updated sel */ +0x0A, 0x14, 0x08, /* HID usage sensor event poll response sel */ +0x0A, 0x15, 0x08, /* HID usage sensor event change sensitivity sel */ +0X81, 0x00, /* HID Input (Data_Arr_Abs) */ +0xC0, /* HID end collection */ +0x0A, 0xD1, 0x04, /* HID usage sensor data light illuminance */ +0x17, 0x00, 0x00, 0x01, 0x80, /* HID logical Min_32 */ +0x27, 0xFF, 0xFF, 0xFF, 0x7F, /* HID logical Max_32 */ +0x55, 0x0F, /* HID unit exponent(0x0F) */ +0x75, 32, /* HID report size(32) */ +0x95, 1, /* HID report count (1) */ +0X81, 0x02, /* HID Input (Data_Arr_Abs) */ +0xC0 /* HID end collection */ +}; +#endif From 02f5bea93cdc4f1c7e37a2347ee18053c1af8cf2 Mon Sep 17 00:00:00 2001 From: Dong Aisheng Date: Wed, 29 Jul 2020 16:00:08 +0800 Subject: [PATCH 005/799] dt-bindings: firmware: imx-scu: new binding to parse clocks from device tree There's a few limitations on the original one cell clock binding (#clock-cells = <1>) that we have to define some SW clock IDs for device tree to reference. This may cause troubles if we want to use common clock IDs for multi platforms support when the clock of those platforms are mostly the same. e.g. Current clock IDs name are defined with SS prefix. However the device may reside in different SS across CPUs, that means the SS prefix may not valid anymore for a new SoC. Furthermore, the device availability of those clocks may also vary a bit. For such situation, we want to eliminate the using of SW Clock IDs and change to use a more close to HW one instead. For SCU clocks usage, only two params required: Resource id + Clock Type. Both parameters are platform independent. So we could use two cells binding to pass those parameters, Cc: Sascha Hauer Cc: Michael Turquette Cc: devicetree@vger.kernel.org Acked-by: Shawn Guo Reviewed-by: Rob Herring Reviewed-by: Stephen Boyd Signed-off-by: Dong Aisheng Signed-off-by: Shawn Guo --- .../devicetree/bindings/arm/freescale/fsl,scu.txt | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt b/Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt index 6064d98b1031..395359dc94fd 100644 --- a/Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt +++ b/Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt @@ -89,7 +89,10 @@ Required properties: "fsl,imx8qm-clock" "fsl,imx8qxp-clock" followed by "fsl,scu-clk" -- #clock-cells: Should be 1. Contains the Clock ID value. +- #clock-cells: Should be either + 2: Contains the Resource and Clock ID value. + or + 1: Contains the Clock ID value. (DEPRECATED) - clocks: List of clock specifiers, must contain an entry for each required entry in clock-names - clock-names: Should include entries "xtal_32KHz", "xtal_24MHz" @@ -208,7 +211,7 @@ firmware { clk: clk { compatible = "fsl,imx8qxp-clk", "fsl,scu-clk"; - #clock-cells = <1>; + #clock-cells = <2>; }; iomuxc { @@ -263,8 +266,7 @@ serial@5a060000 { ... pinctrl-names = "default"; pinctrl-0 = <&pinctrl_lpuart0>; - clocks = <&clk IMX8QXP_UART0_CLK>, - <&clk IMX8QXP_UART0_IPG_CLK>; - clock-names = "per", "ipg"; + clocks = <&uart0_clk IMX_SC_R_UART_0 IMX_SC_PM_CLK_PER>; + clock-names = "ipg"; power-domains = <&pd IMX_SC_R_UART_0>; }; From 540742fb109fa4a65f116db9edc28ab1bd2c872d Mon Sep 17 00:00:00 2001 From: Dong Aisheng Date: Wed, 29 Jul 2020 16:00:09 +0800 Subject: [PATCH 006/799] dt-bindings: clock: imx-lpcg: add support to parse clocks from device tree MX8QM and MX8QXP LPCG Clocks are mostly the same except they may reside in different subsystems across CPUs and also vary a bit on the availability. Same as SCU clock, we want to move the clock definition into device tree which can fully decouple the dependency of Clock ID definition from device tree and make us be able to write a fully generic lpcg clock driver. And we can also use the existence of clock nodes in device tree to address the device and clock availability differences across different SoCs. Cc: Sascha Hauer Cc: Michael Turquette Cc: devicetree@vger.kernel.org Cc: Shawn Guo Cc: Rob Herring Cc: Stephen Boyd Signed-off-by: Dong Aisheng Reviewed-by: Rob Herring Reviewed-by: Stephen Boyd Signed-off-by: Shawn Guo --- .../bindings/clock/imx8qxp-lpcg.yaml | 79 ++++++++++++++----- include/dt-bindings/clock/imx8-lpcg.h | 14 ++++ 2 files changed, 74 insertions(+), 19 deletions(-) create mode 100644 include/dt-bindings/clock/imx8-lpcg.h diff --git a/Documentation/devicetree/bindings/clock/imx8qxp-lpcg.yaml b/Documentation/devicetree/bindings/clock/imx8qxp-lpcg.yaml index 33f3010f48c3..e709e530e17a 100644 --- a/Documentation/devicetree/bindings/clock/imx8qxp-lpcg.yaml +++ b/Documentation/devicetree/bindings/clock/imx8qxp-lpcg.yaml @@ -21,27 +21,58 @@ description: | The clock consumer should specify the desired clock by having the clock ID in its "clocks" phandle cell. See the full list of clock IDs from: - include/dt-bindings/clock/imx8-clock.h + include/dt-bindings/clock/imx8-lpcg.h properties: compatible: - enum: - - fsl,imx8qxp-lpcg-adma - - fsl,imx8qxp-lpcg-conn - - fsl,imx8qxp-lpcg-dc - - fsl,imx8qxp-lpcg-dsp - - fsl,imx8qxp-lpcg-gpu - - fsl,imx8qxp-lpcg-hsio - - fsl,imx8qxp-lpcg-img - - fsl,imx8qxp-lpcg-lsio - - fsl,imx8qxp-lpcg-vpu - + oneOf: + - const: fsl,imx8qxp-lpcg + - items: + - enum: + - fsl,imx8qm-lpcg + - const: fsl,imx8qxp-lpcg + - enum: + - fsl,imx8qxp-lpcg-adma + - fsl,imx8qxp-lpcg-conn + - fsl,imx8qxp-lpcg-dc + - fsl,imx8qxp-lpcg-dsp + - fsl,imx8qxp-lpcg-gpu + - fsl,imx8qxp-lpcg-hsio + - fsl,imx8qxp-lpcg-img + - fsl,imx8qxp-lpcg-lsio + - fsl,imx8qxp-lpcg-vpu + deprecated: true reg: maxItems: 1 '#clock-cells': const: 1 + clocks: + description: | + Input parent clocks phandle array for each clock + minItems: 1 + maxItems: 8 + + clock-indices: + description: | + An integer array indicating the bit offset for each clock. + Refer to for the + supported LPCG clock indices. + minItems: 1 + maxItems: 8 + + clock-output-names: + description: | + Shall be the corresponding names of the outputs. + NOTE this property must be specified in the same order + as the clock-indices property. + minItems: 1 + maxItems: 8 + + power-domains: + maxItems: 1 + required: - compatible - reg @@ -51,23 +82,33 @@ additionalProperties: false examples: - | - #include + #include #include #include - clock-controller@5b200000 { - compatible = "fsl,imx8qxp-lpcg-conn"; - reg = <0x5b200000 0xb0000>; + sdhc0_lpcg: clock-controller@5b200000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5b200000 0x10000>; #clock-cells = <1>; + clocks = <&sdhc0_clk IMX_SC_PM_CLK_PER>, + <&conn_ipg_clk>, + <&conn_axi_clk>; + clock-indices = , + , + ; + clock-output-names = "sdhc0_lpcg_per_clk", + "sdhc0_lpcg_ipg_clk", + "sdhc0_lpcg_ahb_clk"; + power-domains = <&pd IMX_SC_R_SDHC_0>; }; mmc@5b010000 { compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc"; interrupts = ; reg = <0x5b010000 0x10000>; - clocks = <&conn_lpcg IMX_CONN_LPCG_SDHC0_IPG_CLK>, - <&conn_lpcg IMX_CONN_LPCG_SDHC0_PER_CLK>, - <&conn_lpcg IMX_CONN_LPCG_SDHC0_HCLK>; + clocks = <&sdhc0_lpcg IMX_LPCG_CLK_4>, + <&sdhc0_lpcg IMX_LPCG_CLK_0>, + <&sdhc0_lpcg IMX_LPCG_CLK_5>; clock-names = "ipg", "per", "ahb"; power-domains = <&pd IMX_SC_R_SDHC_0>; }; diff --git a/include/dt-bindings/clock/imx8-lpcg.h b/include/dt-bindings/clock/imx8-lpcg.h new file mode 100644 index 000000000000..d202715652c3 --- /dev/null +++ b/include/dt-bindings/clock/imx8-lpcg.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2019-2020 NXP + * Dong Aisheng + */ + +#define IMX_LPCG_CLK_0 0 +#define IMX_LPCG_CLK_1 4 +#define IMX_LPCG_CLK_2 8 +#define IMX_LPCG_CLK_3 12 +#define IMX_LPCG_CLK_4 16 +#define IMX_LPCG_CLK_5 20 +#define IMX_LPCG_CLK_6 24 +#define IMX_LPCG_CLK_7 28 From dfedd2ac4725317735bae5f8085d2d4c301959e4 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 20 Sep 2020 21:57:48 +0200 Subject: [PATCH 007/799] arm64: dts: imx8mq-librem5: align GPIO hog names with dtschema dtschema expects GPIO hogs to end with 'hog' suffix. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi b/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi index e3c6d1272198..64fc546b110f 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi @@ -250,7 +250,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pmic_5v>; - pmic-5v { + pmic-5v-hog { gpio-hog; gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>; input; From 79bd11db8ba8046943dddf740d58baac54326f56 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 20 Sep 2020 21:57:49 +0200 Subject: [PATCH 008/799] ARM: dts: imx: align GPIO hog names with dtschema dtschema for GPIO controllers expects GPIO hogs to end with 'hog' suffix. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx51-zii-rdu1.dts | 2 +- arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi | 8 ++++---- arch/arm/boot/dts/imx6ul-ccimx6ulsbcpro.dts | 2 +- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm/boot/dts/imx51-zii-rdu1.dts b/arch/arm/boot/dts/imx51-zii-rdu1.dts index e559ab0c3645..ec8ca3ac2c1c 100644 --- a/arch/arm/boot/dts/imx51-zii-rdu1.dts +++ b/arch/arm/boot/dts/imx51-zii-rdu1.dts @@ -451,7 +451,7 @@ "", "", "", "", "", "", "", ""; - unused-sd3-wp-gpio { + unused-sd3-wp-hog { /* * See pinctrl_esdhc1 below for more details on this */ diff --git a/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi b/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi index 66b15748e287..c0a76202e16b 100644 --- a/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi +++ b/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi @@ -330,28 +330,28 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio3_hog>; - usb-emulation { + usb-emulation-hog { gpio-hog; gpios = <19 GPIO_ACTIVE_HIGH>; output-low; line-name = "usb-emulation"; }; - usb-mode1 { + usb-mode1-hog { gpio-hog; gpios = <20 GPIO_ACTIVE_HIGH>; output-high; line-name = "usb-mode1"; }; - usb-pwr { + usb-pwr-hog { gpio-hog; gpios = <22 GPIO_ACTIVE_LOW>; output-high; line-name = "usb-pwr-ctrl-en-n"; }; - usb-mode2 { + usb-mode2-hog { gpio-hog; gpios = <23 GPIO_ACTIVE_HIGH>; output-high; diff --git a/arch/arm/boot/dts/imx6ul-ccimx6ulsbcpro.dts b/arch/arm/boot/dts/imx6ul-ccimx6ulsbcpro.dts index a0bbec57ddc7..3ec042bfccba 100644 --- a/arch/arm/boot/dts/imx6ul-ccimx6ulsbcpro.dts +++ b/arch/arm/boot/dts/imx6ul-ccimx6ulsbcpro.dts @@ -110,7 +110,7 @@ }; &gpio5 { - emmc-usd-mux { + emmc-usd-mux-hog { gpio-hog; gpios = <1 GPIO_ACTIVE_LOW>; output-high; From 9b533dc8f340f5e9e7f2ed610510b2191d5e447c Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Tue, 29 Sep 2020 15:05:02 +0100 Subject: [PATCH 009/799] ARM: dts: r8a7742-iwg21d-q7: Add LCD support The iwg21d comes with a 7" capacitive touch screen, therefore add support for it. Signed-off-by: Lad Prabhakar Reviewed-by: Marian-Cristian Rotariu Reviewed-by: Laurent Pinchart Link: https://lore.kernel.org/r/20200929140502.16017-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm/boot/dts/r8a7742-iwg21d-q7.dts | 99 +++++++++++++++++++++++++ 1 file changed, 99 insertions(+) diff --git a/arch/arm/boot/dts/r8a7742-iwg21d-q7.dts b/arch/arm/boot/dts/r8a7742-iwg21d-q7.dts index c2c05c9685d1..0063ef92f50e 100644 --- a/arch/arm/boot/dts/r8a7742-iwg21d-q7.dts +++ b/arch/arm/boot/dts/r8a7742-iwg21d-q7.dts @@ -30,6 +30,7 @@ /dts-v1/; #include "r8a7742-iwg21m.dtsi" +#include / { model = "iWave Systems RainboW-G21D-Qseven board based on RZ/G1H"; @@ -52,6 +53,16 @@ clock-frequency = <26000000>; }; + lcd_backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&tpu 2 5000000 0>; + brightness-levels = <0 4 8 16 32 64 128 255>; + pinctrl-0 = <&backlight_pins>; + pinctrl-names = "default"; + default-brightness-level = <7>; + enable-gpios = <&gpio3 11 GPIO_ACTIVE_HIGH>; + }; + leds { compatible = "gpio-leds"; @@ -62,6 +73,41 @@ }; }; + lvds-receiver { + compatible = "ti,ds90cf384a", "lvds-decoder"; + power-supply = <&vcc_3v3_tft1>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + lvds_receiver_in: endpoint { + remote-endpoint = <&lvds0_out>; + }; + }; + port@1 { + reg = <1>; + lvds_receiver_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; + }; + + panel { + compatible = "edt,etm0700g0dh6"; + backlight = <&lcd_backlight>; + power-supply = <&vcc_3v3_tft1>; + + port { + panel_in: endpoint { + remote-endpoint = <&lvds_receiver_out>; + }; + }; + }; + reg_1p5v: 1p5v { compatible = "regulator-fixed"; regulator-name = "1P5V"; @@ -85,6 +131,17 @@ }; }; + vcc_3v3_tft1: regulator-panel { + compatible = "regulator-fixed"; + + regulator-name = "vcc-3v3-tft1"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + startup-delay-us = <500>; + gpio = <&gpio5 28 GPIO_ACTIVE_HIGH>; + }; + vcc_sdhi2: regulator-vcc-sdhi2 { compatible = "regulator-fixed"; @@ -139,6 +196,16 @@ VDDIO-supply = <®_3p3v>; VDDD-supply = <®_1p5v>; }; + + touch: touchpanel@38 { + compatible = "edt,edt-ft5406"; + reg = <0x38>; + interrupt-parent = <&gpio0>; + interrupts = <24 IRQ_TYPE_EDGE_FALLING>; + /* GP1_29 is also shared with audio codec reset pin */ + reset-gpios = <&gpio1 29 GPIO_ACTIVE_LOW>; + vcc-supply = <&vcc_3v3_tft1>; + }; }; &can1 { @@ -152,6 +219,18 @@ status = "okay"; }; +&du { + status = "okay"; +}; + +&gpio0 { + touch-interrupt { + gpio-hog; + gpios = <24 GPIO_ACTIVE_LOW>; + input; + }; +}; + &gpio1 { can-trx-en-gpio{ gpio-hog; @@ -167,6 +246,17 @@ status = "okay"; }; +&lvds0 { + status = "okay"; + ports { + port@1 { + lvds0_out: endpoint { + remote-endpoint = <&lvds_receiver_in>; + }; + }; + }; +}; + &msiof0 { pinctrl-0 = <&msiof0_pins>; pinctrl-names = "default"; @@ -229,6 +319,11 @@ function = "avb"; }; + backlight_pins: backlight { + groups = "tpu0_to2"; + function = "tpu0"; + }; + can1_pins: can1 { groups = "can1_data_b"; function = "can1"; @@ -335,6 +430,10 @@ shared-pin; }; +&tpu { + status = "okay"; +}; + &usbphy { status = "okay"; }; From e8c471588890f9939b23d628e65b7dcb3a856f7a Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 2 Oct 2020 18:39:45 +0200 Subject: [PATCH 010/799] arm64: dts: renesas: Align GPIO hog names with dtschema The convention for node names is to use hyphens, not underscores. dtschema for pca95xx expects GPIO hogs to end with 'hog' suffix. Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20201002163945.7885-1-krzk@kernel.org Signed-off-by: Geert Uytterhoeven --- .../boot/dts/renesas/r8a77951-salvator-xs.dts | 2 +- .../boot/dts/renesas/r8a77965-salvator-xs.dts | 2 +- arch/arm64/boot/dts/renesas/ulcb-kf.dtsi | 14 +++++++------- 3 files changed, 9 insertions(+), 9 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r8a77951-salvator-xs.dts b/arch/arm64/boot/dts/renesas/r8a77951-salvator-xs.dts index cef9da4376a3..e5922329a4b8 100644 --- a/arch/arm64/boot/dts/renesas/r8a77951-salvator-xs.dts +++ b/arch/arm64/boot/dts/renesas/r8a77951-salvator-xs.dts @@ -118,7 +118,7 @@ }; &pca9654 { - pcie_sata_switch { + pcie-sata-switch-hog { gpio-hog; gpios = <7 GPIO_ACTIVE_HIGH>; output-low; /* enable SATA by default */ diff --git a/arch/arm64/boot/dts/renesas/r8a77965-salvator-xs.dts b/arch/arm64/boot/dts/renesas/r8a77965-salvator-xs.dts index 5cef64605464..d7e621101af7 100644 --- a/arch/arm64/boot/dts/renesas/r8a77965-salvator-xs.dts +++ b/arch/arm64/boot/dts/renesas/r8a77965-salvator-xs.dts @@ -55,7 +55,7 @@ }; &pca9654 { - pcie_sata_switch { + pcie-sata-switch-hog { gpio-hog; gpios = <7 GPIO_ACTIVE_HIGH>; output-low; /* enable SATA by default */ diff --git a/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi b/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi index 202177706cde..e9ed2597f1c2 100644 --- a/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi +++ b/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi @@ -143,49 +143,49 @@ interrupt-parent = <&gpio6>; interrupts = <8 IRQ_TYPE_EDGE_FALLING>; - audio_out_off { + audio-out-off-hog { gpio-hog; gpios = <0 GPIO_ACTIVE_HIGH>; /* P00 */ output-high; line-name = "Audio_Out_OFF"; }; - hub_pwen { + hub-pwen-hog { gpio-hog; gpios = <6 GPIO_ACTIVE_HIGH>; output-high; line-name = "HUB pwen"; }; - hub_rst { + hub-rst-hog { gpio-hog; gpios = <7 GPIO_ACTIVE_HIGH>; output-high; line-name = "HUB rst"; }; - otg_extlpn { + otg-extlpn-hog { gpio-hog; gpios = <9 GPIO_ACTIVE_HIGH>; output-high; line-name = "OTG EXTLPn"; }; - otg_offvbusn { + otg-offvbusn-hog { gpio-hog; gpios = <8 GPIO_ACTIVE_HIGH>; output-low; line-name = "OTG OFFVBUSn"; }; - sd-wifi-mux { + sd-wifi-mux-hog { gpio-hog; gpios = <5 GPIO_ACTIVE_HIGH>; output-low; /* Connect WL1837 */ line-name = "SD WiFi mux"; }; - snd_rst { + snd-rst-hog { gpio-hog; gpios = <15 GPIO_ACTIVE_HIGH>; /* P17 */ output-high; From ca3b4330a5437d877e9b0093ba8b746e73695fb0 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Mon, 5 Oct 2020 13:29:51 +0200 Subject: [PATCH 011/799] arm64: dts: renesas: r8a77961: Add MSIOF nodes Add the device nodes for all Clock-Synchronized Serial Interface with FIFO (MSIOF) instances on R-Car M3-W+. Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20201005112951.22532-1-geert+renesas@glider.be --- arch/arm64/boot/dts/renesas/r8a77961.dtsi | 62 +++++++++++++++++++++++ 1 file changed, 62 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a77961.dtsi b/arch/arm64/boot/dts/renesas/r8a77961.dtsi index 1ba30313c8b8..b0c4b8150d37 100644 --- a/arch/arm64/boot/dts/renesas/r8a77961.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77961.dtsi @@ -1187,6 +1187,68 @@ status = "disabled"; }; + msiof0: spi@e6e90000 { + compatible = "renesas,msiof-r8a77961", + "renesas,rcar-gen3-msiof"; + reg = <0 0xe6e90000 0 0x0064>; + interrupts = ; + clocks = <&cpg CPG_MOD 211>; + dmas = <&dmac1 0x41>, <&dmac1 0x40>, + <&dmac2 0x41>, <&dmac2 0x40>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; + resets = <&cpg 211>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + msiof1: spi@e6ea0000 { + compatible = "renesas,msiof-r8a77961", + "renesas,rcar-gen3-msiof"; + reg = <0 0xe6ea0000 0 0x0064>; + interrupts = ; + clocks = <&cpg CPG_MOD 210>; + dmas = <&dmac1 0x43>, <&dmac1 0x42>, + <&dmac2 0x43>, <&dmac2 0x42>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; + resets = <&cpg 210>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + msiof2: spi@e6c00000 { + compatible = "renesas,msiof-r8a77961", + "renesas,rcar-gen3-msiof"; + reg = <0 0xe6c00000 0 0x0064>; + interrupts = ; + clocks = <&cpg CPG_MOD 209>; + dmas = <&dmac0 0x45>, <&dmac0 0x44>; + dma-names = "tx", "rx"; + power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; + resets = <&cpg 209>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + msiof3: spi@e6c10000 { + compatible = "renesas,msiof-r8a77961", + "renesas,rcar-gen3-msiof"; + reg = <0 0xe6c10000 0 0x0064>; + interrupts = ; + clocks = <&cpg CPG_MOD 208>; + dmas = <&dmac0 0x47>, <&dmac0 0x46>; + dma-names = "tx", "rx"; + power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; + resets = <&cpg 208>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + vin0: video@e6ef0000 { reg = <0 0xe6ef0000 0 0x1000>; /* placeholder */ From d311d818fa8cfa791d05de9e03b0d9babfc82dd2 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Wed, 14 Oct 2020 15:55:58 +0100 Subject: [PATCH 012/799] ARM: dts: r8a7742-iwg21d-q7-dbcm-ca: Enable VIN instances Enable VIN instances along with OV5640 as endpoints on the adapter board. Signed-off-by: Lad Prabhakar Reviewed-by: Biju Das Link: https://lore.kernel.org/r/20201014145558.12854-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- .../boot/dts/r8a7742-iwg21d-q7-dbcm-ca.dts | 222 ++++++++++++++++++ 1 file changed, 222 insertions(+) diff --git a/arch/arm/boot/dts/r8a7742-iwg21d-q7-dbcm-ca.dts b/arch/arm/boot/dts/r8a7742-iwg21d-q7-dbcm-ca.dts index 961c0f2eeefb..98c3fbd89fa6 100644 --- a/arch/arm/boot/dts/r8a7742-iwg21d-q7-dbcm-ca.dts +++ b/arch/arm/boot/dts/r8a7742-iwg21d-q7-dbcm-ca.dts @@ -20,6 +20,30 @@ serial5 = &hscif0; ethernet1 = ðer; }; + + mclk_cam1: mclk-cam1 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <26000000>; + }; + + mclk_cam2: mclk-cam2 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <26000000>; + }; + + mclk_cam3: mclk-cam3 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <26000000>; + }; + + mclk_cam4: mclk-cam4 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <26000000>; + }; }; &avb { @@ -47,6 +71,19 @@ }; }; +&gpio0 { + /* Disable hogging GP0_18 to output LOW */ + /delete-node/ qspi_en; + + /* Hog GP0_18 to output HIGH to enable VIN2 */ + vin2_en { + gpio-hog; + gpios = <18 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "VIN2_EN"; + }; +}; + &hscif0 { pinctrl-0 = <&hscif0_pins>; pinctrl-names = "default"; @@ -54,6 +91,94 @@ status = "okay"; }; +&i2c0 { + ov5640@3c { + compatible = "ovti,ov5640"; + reg = <0x3c>; + clocks = <&mclk_cam1>; + clock-names = "xclk"; + + port { + ov5640_0: endpoint { + bus-width = <8>; + data-shift = <2>; + bus-type = <6>; + pclk-sample = <1>; + remote-endpoint = <&vin0ep>; + }; + }; + }; +}; + +&i2c1 { + pinctrl-0 = <&i2c1_pins>; + pinctrl-names = "default"; + + status = "okay"; + clock-frequency = <400000>; + + ov5640@3c { + compatible = "ovti,ov5640"; + reg = <0x3c>; + clocks = <&mclk_cam2>; + clock-names = "xclk"; + + port { + ov5640_1: endpoint { + bus-width = <8>; + data-shift = <2>; + bus-type = <6>; + pclk-sample = <1>; + remote-endpoint = <&vin1ep>; + }; + }; + }; +}; + +&i2c2 { + ov5640@3c { + compatible = "ovti,ov5640"; + reg = <0x3c>; + clocks = <&mclk_cam3>; + clock-names = "xclk"; + + port { + ov5640_2: endpoint { + bus-width = <8>; + data-shift = <2>; + bus-type = <6>; + pclk-sample = <1>; + remote-endpoint = <&vin2ep>; + }; + }; + }; +}; + +&i2c3 { + pinctrl-0 = <&i2c3_pins>; + pinctrl-names = "default"; + + status = "okay"; + clock-frequency = <400000>; + + ov5640@3c { + compatible = "ovti,ov5640"; + reg = <0x3c>; + clocks = <&mclk_cam4>; + clock-names = "xclk"; + + port { + ov5640_3: endpoint { + bus-width = <8>; + data-shift = <2>; + bus-type = <6>; + pclk-sample = <1>; + remote-endpoint = <&vin3ep>; + }; + }; + }; +}; + &pfc { can0_pins: can0 { groups = "can0_data_d"; @@ -70,6 +195,16 @@ function = "hscif0"; }; + i2c1_pins: i2c1 { + groups = "i2c1_c"; + function = "i2c1"; + }; + + i2c3_pins: i2c3 { + groups = "i2c3"; + function = "i2c3"; + }; + scif0_pins: scif0 { groups = "scif0_data"; function = "scif0"; @@ -84,6 +219,31 @@ groups = "scifb1_data"; function = "scifb1"; }; + + vin0_8bit_pins: vin0 { + groups = "vin0_data8", "vin0_clk", "vin0_sync"; + function = "vin0"; + }; + + vin1_8bit_pins: vin1 { + groups = "vin1_data8_b", "vin1_clk_b", "vin1_sync_b"; + function = "vin1"; + }; + + vin2_pins: vin2 { + groups = "vin2_g8", "vin2_clk"; + function = "vin2"; + }; + + vin3_pins: vin3 { + groups = "vin3_data8", "vin3_clk", "vin3_sync"; + function = "vin3"; + }; +}; + +&qspi { + /* Pins shared with VIN2, keep status disabled */ + status = "disabled"; }; &scif0 { @@ -106,3 +266,65 @@ rts-gpios = <&gpio4 21 GPIO_ACTIVE_LOW>; cts-gpios = <&gpio4 17 GPIO_ACTIVE_LOW>; }; + +&vin0 { + /* + * Set SW2 switch on the SOM to 'ON' + * Set SW1 switch on camera board to 'OFF' as we are using 8bit mode + */ + status = "okay"; + pinctrl-0 = <&vin0_8bit_pins>; + pinctrl-names = "default"; + + port { + vin0ep: endpoint { + remote-endpoint = <&ov5640_0>; + bus-width = <8>; + bus-type = <6>; + }; + }; +}; + +&vin1 { + /* Set SW1 switch on the SOM to 'ON' */ + status = "okay"; + pinctrl-0 = <&vin1_8bit_pins>; + pinctrl-names = "default"; + + port { + vin1ep: endpoint { + remote-endpoint = <&ov5640_1>; + bus-width = <8>; + bus-type = <6>; + }; + }; +}; + +&vin2 { + status = "okay"; + pinctrl-0 = <&vin2_pins>; + pinctrl-names = "default"; + + port { + vin2ep: endpoint { + remote-endpoint = <&ov5640_2>; + bus-width = <8>; + data-shift = <8>; + bus-type = <6>; + }; + }; +}; + +&vin3 { + status = "okay"; + pinctrl-0 = <&vin3_pins>; + pinctrl-names = "default"; + + port { + vin3ep: endpoint { + remote-endpoint = <&ov5640_3>; + bus-width = <8>; + bus-type = <6>; + }; + }; +}; From 67d3dcf12a3d245b6fd6ca5672893f7ae4e137ed Mon Sep 17 00:00:00 2001 From: Biju Das Date: Thu, 15 Oct 2020 14:23:49 +0100 Subject: [PATCH 013/799] arm64: dts: renesas: hihope-rzg2-ex: Drop rxc-skew-ps from ethernet-phy node HiHope RZG2[HMN] boards uses Realtek phy and the driver does not support rxc-skew-ps property. So remove rxc-skew-ps from ethernet-phy node. Fixes: 7433f1fb8ec8fe ("arm64: dts: renesas: Add HiHope RZ/G2M sub board support") Signed-off-by: Biju Das Reviewed-by: Lad Prabhakar Link: https://lore.kernel.org/r/20201015132350.8360-1-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/hihope-rzg2-ex.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/renesas/hihope-rzg2-ex.dtsi b/arch/arm64/boot/dts/renesas/hihope-rzg2-ex.dtsi index 178401a34cbf..b9e46aed5336 100644 --- a/arch/arm64/boot/dts/renesas/hihope-rzg2-ex.dtsi +++ b/arch/arm64/boot/dts/renesas/hihope-rzg2-ex.dtsi @@ -23,7 +23,6 @@ status = "okay"; phy0: ethernet-phy@0 { - rxc-skew-ps = <1500>; reg = <0>; interrupt-parent = <&gpio2>; interrupts = <11 IRQ_TYPE_LEVEL_LOW>; From 53e573dc39fba1834f3e4fa002cb754b61a30701 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Thu, 15 Oct 2020 14:23:50 +0100 Subject: [PATCH 014/799] arm64: dts: renesas: cat875: Remove rxc-skew-ps from ethernet-phy node The CAT875 sub board from Silicon Linux uses Realtek phy and the driver does not support rxc-skew-ps property. Fixes: 6b170cd3ed02949f ("arm64: dts: renesas: cat875: Add ethernet support") Signed-off-by: Biju Das Reviewed-by: Lad Prabhakar Link: https://lore.kernel.org/r/20201015132350.8360-2-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/cat875.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/renesas/cat875.dtsi b/arch/arm64/boot/dts/renesas/cat875.dtsi index 33daa9570684..801ea54b027c 100644 --- a/arch/arm64/boot/dts/renesas/cat875.dtsi +++ b/arch/arm64/boot/dts/renesas/cat875.dtsi @@ -21,7 +21,6 @@ status = "okay"; phy0: ethernet-phy@0 { - rxc-skew-ps = <1500>; reg = <0>; interrupt-parent = <&gpio2>; interrupts = <21 IRQ_TYPE_LEVEL_LOW>; From 622007d172fbb1d7556329bafd72dc28c0baf1b8 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Tue, 20 Oct 2020 13:51:31 +0100 Subject: [PATCH 015/799] arm64: dts: renesas: aistarvision-mipi-adapter-2.1: Add parent macro for each sensor For HiHope RZ/G2H the OV5645 sensor is populated on i2c2 whereas the imx219 sensor is populated on i2c3 so add support for handling such cases by adding a parent macro for each sensor. Also update r8a774c0-ek874-mipi-2.1.dts to incorporate the changes. Signed-off-by: Lad Prabhakar Reviewed-by: Biju Das Link: https://lore.kernel.org/r/20201020125134.22625-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- .../arm64/boot/dts/renesas/aistarvision-mipi-adapter-2.1.dtsi | 4 +++- arch/arm64/boot/dts/renesas/r8a774c0-ek874-mipi-2.1.dts | 3 ++- 2 files changed, 5 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/aistarvision-mipi-adapter-2.1.dtsi b/arch/arm64/boot/dts/renesas/aistarvision-mipi-adapter-2.1.dtsi index dac6ff49020f..7ce986f0a06f 100644 --- a/arch/arm64/boot/dts/renesas/aistarvision-mipi-adapter-2.1.dtsi +++ b/arch/arm64/boot/dts/renesas/aistarvision-mipi-adapter-2.1.dtsi @@ -61,7 +61,7 @@ }; }; -&MIPI_PARENT_I2C { +&MIPI_OV5645_PARENT_I2C { ov5645: ov5645@3c { compatible = "ovti,ov5645"; reg = <0x3c>; @@ -77,7 +77,9 @@ }; }; }; +}; +&MIPI_IMX219_PARENT_I2C { imx219: imx219@10 { compatible = "sony,imx219"; reg = <0x10>; diff --git a/arch/arm64/boot/dts/renesas/r8a774c0-ek874-mipi-2.1.dts b/arch/arm64/boot/dts/renesas/r8a774c0-ek874-mipi-2.1.dts index f0829e905506..e7b4a929bb17 100644 --- a/arch/arm64/boot/dts/renesas/r8a774c0-ek874-mipi-2.1.dts +++ b/arch/arm64/boot/dts/renesas/r8a774c0-ek874-mipi-2.1.dts @@ -8,7 +8,8 @@ /dts-v1/; #include "r8a774c0-ek874.dts" -#define MIPI_PARENT_I2C i2c3 +#define MIPI_OV5645_PARENT_I2C i2c3 +#define MIPI_IMX219_PARENT_I2C i2c3 #include "aistarvision-mipi-adapter-2.1.dtsi" / { From 05e6ae33cf9834dd2f0ff35001828ca09fe5af26 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Tue, 20 Oct 2020 13:51:32 +0100 Subject: [PATCH 016/799] arm64: dts: renesas: Add support for MIPI Adapter V2.1 connected to HiHope RZ/G2H MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add support for AISTARVISION MIPI Adapter V2.1 board connected to HiHope RZ/G2H board. Common file hihope-rzg2-ex-aistarvision-mipi-adapter-2.1.dtsi is created which will be used by RZ/G2{HMN}, by default the CSI20 node is tied to ov5645 camera endpoint and the imx219 camera endpoint is tied to CSI40. Signed-off-by: Lad Prabhakar Reviewed-by: Biju Das Acked-by: Niklas Söderlund Link: https://lore.kernel.org/r/20201020125134.22625-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/Makefile | 1 + ...rzg2-ex-aistarvision-mipi-adapter-2.1.dtsi | 109 ++++++++++++++++++ .../r8a774e1-hihope-rzg2h-ex-mipi-2.1.dts | 16 +++ 3 files changed, 126 insertions(+) create mode 100644 arch/arm64/boot/dts/renesas/hihope-rzg2-ex-aistarvision-mipi-adapter-2.1.dtsi create mode 100644 arch/arm64/boot/dts/renesas/r8a774e1-hihope-rzg2h-ex-mipi-2.1.dts diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile index dffefe030a76..f98e9e2e520d 100644 --- a/arch/arm64/boot/dts/renesas/Makefile +++ b/arch/arm64/boot/dts/renesas/Makefile @@ -22,6 +22,7 @@ dtb-$(CONFIG_ARCH_R8A774C0) += r8a774c0-ek874-mipi-2.1.dtb dtb-$(CONFIG_ARCH_R8A774E1) += r8a774e1-hihope-rzg2h.dtb dtb-$(CONFIG_ARCH_R8A774E1) += r8a774e1-hihope-rzg2h-ex.dtb dtb-$(CONFIG_ARCH_R8A774E1) += r8a774e1-hihope-rzg2h-ex-idk-1110wr.dtb +dtb-$(CONFIG_ARCH_R8A774E1) += r8a774e1-hihope-rzg2h-ex-mipi-2.1.dtb dtb-$(CONFIG_ARCH_R8A77950) += r8a77950-salvator-x.dtb dtb-$(CONFIG_ARCH_R8A77950) += r8a77950-ulcb.dtb diff --git a/arch/arm64/boot/dts/renesas/hihope-rzg2-ex-aistarvision-mipi-adapter-2.1.dtsi b/arch/arm64/boot/dts/renesas/hihope-rzg2-ex-aistarvision-mipi-adapter-2.1.dtsi new file mode 100644 index 000000000000..c62ddb9b2ba5 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/hihope-rzg2-ex-aistarvision-mipi-adapter-2.1.dtsi @@ -0,0 +1,109 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the HiHope RZ/G2[HMN] MIPI common parts + * + * Copyright (C) 2020 Renesas Electronics Corp. + */ + +#define MIPI_OV5645_PARENT_I2C i2c2 +#define MIPI_IMX219_PARENT_I2C i2c3 +#include "aistarvision-mipi-adapter-2.1.dtsi" + +&csi20 { + status = "okay"; + + ports { + port@0 { + reg = <0>; + csi20_in: endpoint { + clock-lanes = <0>; + data-lanes = <1 2>; + remote-endpoint = <&ov5645_ep>; + }; + }; + }; +}; + +&csi40 { + status = "okay"; + + ports { + port@0 { + reg = <0>; + csi40_in: endpoint { + clock-lanes = <0>; + data-lanes = <1 2>; + remote-endpoint = <&imx219_ep>; + }; + }; + }; +}; + +&i2c3 { + pinctrl-0 = <&i2c3_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&imx219 { + port { + imx219_ep: endpoint { + clock-lanes = <0>; + data-lanes = <1 2>; + link-frequencies = /bits/ 64 <456000000>; + remote-endpoint = <&csi40_in>; + }; + }; +}; + +&ov5645 { + enable-gpios = <&gpio6 4 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio6 8 GPIO_ACTIVE_LOW>; + + port { + ov5645_ep: endpoint { + clock-lanes = <0>; + data-lanes = <1 2>; + remote-endpoint = <&csi20_in>; + }; + }; +}; + +&pfc { + i2c3_pins: i2c3 { + groups = "i2c3"; + function = "i2c3"; + }; +}; + +&vin0 { + status = "okay"; +}; + +&vin1 { + status = "okay"; +}; + +&vin2 { + status = "okay"; +}; + +&vin3 { + status = "okay"; +}; + +&vin4 { + status = "okay"; +}; + +&vin5 { + status = "okay"; +}; + +&vin6 { + status = "okay"; +}; + +&vin7 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/renesas/r8a774e1-hihope-rzg2h-ex-mipi-2.1.dts b/arch/arm64/boot/dts/renesas/r8a774e1-hihope-rzg2h-ex-mipi-2.1.dts new file mode 100644 index 000000000000..46adb6efb5e6 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r8a774e1-hihope-rzg2h-ex-mipi-2.1.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the HiHope RZ/G2H board + * connected with aistarvision-mipi-v2-adapter board + * + * Copyright (C) 2020 Renesas Electronics Corp. + */ + +/dts-v1/; +#include "r8a774e1-hihope-rzg2h-ex.dts" +#include "hihope-rzg2-ex-aistarvision-mipi-adapter-2.1.dtsi" + +/ { + model = "HopeRun HiHope RZ/G2H with sub board connected with aistarvision-mipi-v2-adapter board"; + compatible = "hoperun,hihope-rzg2h", "renesas,r8a774e1"; +}; From 661495164934e15bc8a192f8eafa1ec9655e74f0 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Tue, 20 Oct 2020 13:51:33 +0100 Subject: [PATCH 017/799] arm64: dts: renesas: Add support for MIPI Adapter V2.1 connected to HiHope RZ/G2M Add support for AISTARVISION MIPI Adapter V2.1 board connected to HiHope RZ/G2M board. Signed-off-by: Lad Prabhakar Reviewed-by: Biju Das Link: https://lore.kernel.org/r/20201020125134.22625-4-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/Makefile | 1 + .../r8a774a1-hihope-rzg2m-ex-mipi-2.1.dts | 29 +++++++++++++++++++ 2 files changed, 30 insertions(+) create mode 100644 arch/arm64/boot/dts/renesas/r8a774a1-hihope-rzg2m-ex-mipi-2.1.dts diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile index f98e9e2e520d..ca095c7e8ee1 100644 --- a/arch/arm64/boot/dts/renesas/Makefile +++ b/arch/arm64/boot/dts/renesas/Makefile @@ -3,6 +3,7 @@ dtb-$(CONFIG_ARCH_R8A774A1) += r8a774a1-beacon-rzg2m-kit.dtb dtb-$(CONFIG_ARCH_R8A774A1) += r8a774a1-hihope-rzg2m.dtb dtb-$(CONFIG_ARCH_R8A774A1) += r8a774a1-hihope-rzg2m-ex.dtb dtb-$(CONFIG_ARCH_R8A774A1) += r8a774a1-hihope-rzg2m-ex-idk-1110wr.dtb +dtb-$(CONFIG_ARCH_R8A774A1) += r8a774a1-hihope-rzg2m-ex-mipi-2.1.dtb dtb-$(CONFIG_ARCH_R8A774A1) += r8a774a1-hihope-rzg2m-rev2.dtb dtb-$(CONFIG_ARCH_R8A774A1) += r8a774a1-hihope-rzg2m-rev2-ex.dtb dtb-$(CONFIG_ARCH_R8A774A1) += r8a774a1-hihope-rzg2m-rev2-ex-idk-1110wr.dtb diff --git a/arch/arm64/boot/dts/renesas/r8a774a1-hihope-rzg2m-ex-mipi-2.1.dts b/arch/arm64/boot/dts/renesas/r8a774a1-hihope-rzg2m-ex-mipi-2.1.dts new file mode 100644 index 000000000000..5c91e0d7e67b --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r8a774a1-hihope-rzg2m-ex-mipi-2.1.dts @@ -0,0 +1,29 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the HiHope RZ/G2M board + * connected with aistarvision-mipi-v2-adapter board + * + * Copyright (C) 2020 Renesas Electronics Corp. + */ + +/dts-v1/; +#include "r8a774a1-hihope-rzg2m-ex.dts" +#include "hihope-rzg2-ex-aistarvision-mipi-adapter-2.1.dtsi" + +/ { + model = "HopeRun HiHope RZ/G2M with sub board connected with aistarvision-mipi-v2-adapter board"; + compatible = "hoperun,hihope-rzg2m", "renesas,r8a774a1"; +}; + +/* + * On RZ/G2M SoC LSI V1.3 CSI40 supports only 4 lane mode. + * HiHope RZ/G2M Rev.4.0 board is based on LSI V1.3 so disable csi40 and + * imx219 as the imx219 endpoint driver supports only 2 lane mode. + */ +&csi40 { + status = "disabled"; +}; + +&imx219 { + status = "disabled"; +}; From bdf0c8ea8c63d9e288ff06fc300e2eb8bd332d1c Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Tue, 20 Oct 2020 13:51:34 +0100 Subject: [PATCH 018/799] arm64: dts: renesas: Add support for MIPI Adapter V2.1 connected to HiHope RZ/G2N Add support for AISTARVISION MIPI Adapter V2.1 board connected to HiHope RZ/G2N board. Signed-off-by: Lad Prabhakar Reviewed-by: Biju Das Link: https://lore.kernel.org/r/20201020125134.22625-5-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/Makefile | 1 + .../r8a774b1-hihope-rzg2n-ex-mipi-2.1.dts | 16 ++++++++++++++++ 2 files changed, 17 insertions(+) create mode 100644 arch/arm64/boot/dts/renesas/r8a774b1-hihope-rzg2n-ex-mipi-2.1.dts diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile index ca095c7e8ee1..2b043b59c669 100644 --- a/arch/arm64/boot/dts/renesas/Makefile +++ b/arch/arm64/boot/dts/renesas/Makefile @@ -11,6 +11,7 @@ dtb-$(CONFIG_ARCH_R8A774A1) += r8a774a1-hihope-rzg2m-rev2-ex-idk-1110wr.dtb dtb-$(CONFIG_ARCH_R8A774B1) += r8a774b1-hihope-rzg2n.dtb dtb-$(CONFIG_ARCH_R8A774B1) += r8a774b1-hihope-rzg2n-ex.dtb dtb-$(CONFIG_ARCH_R8A774B1) += r8a774b1-hihope-rzg2n-ex-idk-1110wr.dtb +dtb-$(CONFIG_ARCH_R8A774B1) += r8a774b1-hihope-rzg2n-ex-mipi-2.1.dtb dtb-$(CONFIG_ARCH_R8A774B1) += r8a774b1-hihope-rzg2n-rev2.dtb dtb-$(CONFIG_ARCH_R8A774B1) += r8a774b1-hihope-rzg2n-rev2-ex.dtb dtb-$(CONFIG_ARCH_R8A774B1) += r8a774b1-hihope-rzg2n-rev2-ex-idk-1110wr.dtb diff --git a/arch/arm64/boot/dts/renesas/r8a774b1-hihope-rzg2n-ex-mipi-2.1.dts b/arch/arm64/boot/dts/renesas/r8a774b1-hihope-rzg2n-ex-mipi-2.1.dts new file mode 100644 index 000000000000..ce8e3bcc7dc9 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r8a774b1-hihope-rzg2n-ex-mipi-2.1.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the HiHope RZ/G2N board + * connected with aistarvision-mipi-v2-adapter board + * + * Copyright (C) 2020 Renesas Electronics Corp. + */ + +/dts-v1/; +#include "r8a774b1-hihope-rzg2n-ex.dts" +#include "hihope-rzg2-ex-aistarvision-mipi-adapter-2.1.dtsi" + +/ { + model = "HopeRun HiHope RZ/G2N with sub board connected with aistarvision-mipi-v2-adapter board"; + compatible = "hoperun,hihope-rzg2n", "renesas,r8a774b1"; +}; From f74cdb1c4e9b25e3e06f8d354371d53b97ae8482 Mon Sep 17 00:00:00 2001 From: Enric Balletbo i Serra Date: Wed, 26 Aug 2020 11:02:17 +0200 Subject: [PATCH 019/799] arm64: dts: mt8173-elm: Remove ddc property from panel The elm and hana devices uses an Embedded DisplayPort (eDP) as interface for its panel, so the DDC channel specified in the binding is useless. Signed-off-by: Enric Balletbo i Serra Tested-by: Bilal Wasim Link: https://lore.kernel.org/r/20200826090218.682931-1-enric.balletbo@collabora.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi b/arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi index 44a0346133cd..21452c51a20a 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi @@ -87,7 +87,6 @@ panel: panel { compatible = "lg,lp120up1"; power-supply = <&panel_fixed_3v3>; - ddc-i2c-bus = <&i2c0>; backlight = <&backlight>; port { From 4c7a6260775d596bb4ded0c0e2b3d317e0b37014 Mon Sep 17 00:00:00 2001 From: Hanks Chen Date: Thu, 30 Jul 2020 21:30:15 +0800 Subject: [PATCH 020/799] arm64: dts: add dts nodes for MT6779 this adds initial MT6779 dts settings for board support, including cpu, gic, timer, ccf, pinctrl, uart, sysirq...etc. Signed-off-by: Hanks Chen Link: https://lore.kernel.org/r/1596115816-11758-3-git-send-email-hanks.chen@mediatek.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/Makefile | 1 + arch/arm64/boot/dts/mediatek/mt6779-evb.dts | 31 +++ arch/arm64/boot/dts/mediatek/mt6779.dtsi | 271 ++++++++++++++++++++ 3 files changed, 303 insertions(+) create mode 100644 arch/arm64/boot/dts/mediatek/mt6779-evb.dts create mode 100644 arch/arm64/boot/dts/mediatek/mt6779.dtsi diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile index 3ee682c266cc..66eeba60acac 100644 --- a/arch/arm64/boot/dts/mediatek/Makefile +++ b/arch/arm64/boot/dts/mediatek/Makefile @@ -1,6 +1,7 @@ # SPDX-License-Identifier: GPL-2.0 dtb-$(CONFIG_ARCH_MEDIATEK) += mt2712-evb.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt6755-evb.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt6779-evb.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt6795-evb.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-evb.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-x20-dev.dtb diff --git a/arch/arm64/boot/dts/mediatek/mt6779-evb.dts b/arch/arm64/boot/dts/mediatek/mt6779-evb.dts new file mode 100644 index 000000000000..164f5cbb3821 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt6779-evb.dts @@ -0,0 +1,31 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2019 MediaTek Inc. + * Author: Mars.C + * + */ + +/dts-v1/; +#include "mt6779.dtsi" + +/ { + model = "MediaTek MT6779 EVB"; + compatible = "mediatek,mt6779-evb", "mediatek,mt6779"; + + aliases { + serial0 = &uart0; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0 0x40000000 0 0x1e800000>; + }; + + chosen { + stdout-path = "serial0:921600n8"; + }; +}; + +&uart0 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt6779.dtsi b/arch/arm64/boot/dts/mediatek/mt6779.dtsi new file mode 100644 index 000000000000..370f309d32de --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt6779.dtsi @@ -0,0 +1,271 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2019 MediaTek Inc. + * Author: Mars.C + * + */ + +#include +#include +#include +#include + +/ { + compatible = "mediatek,mt6779"; + interrupt-parent = <&sysirq>; + #address-cells = <2>; + #size-cells = <2>; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + enable-method = "psci"; + reg = <0x000>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + enable-method = "psci"; + reg = <0x100>; + }; + + cpu2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + enable-method = "psci"; + reg = <0x200>; + }; + + cpu3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + enable-method = "psci"; + reg = <0x300>; + }; + + cpu4: cpu@4 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + enable-method = "psci"; + reg = <0x400>; + }; + + cpu5: cpu@5 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + enable-method = "psci"; + reg = <0x500>; + }; + + cpu6: cpu@6 { + device_type = "cpu"; + compatible = "arm,cortex-a75"; + enable-method = "psci"; + reg = <0x600>; + }; + + cpu7: cpu@7 { + device_type = "cpu"; + compatible = "arm,cortex-a75"; + enable-method = "psci"; + reg = <0x700>; + }; + }; + + pmu { + compatible = "arm,armv8-pmuv3"; + interrupt-parent = <&gic>; + interrupts = ; + }; + + clk26m: oscillator@0 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <26000000>; + clock-output-names = "clk26m"; + }; + + clk32k: oscillator@1 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "clk32k"; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupt-parent = <&gic>; + interrupts = , + , + , + ; + }; + + soc { + #address-cells = <2>; + #size-cells = <2>; + compatible = "simple-bus"; + ranges; + + gic: interrupt-controller@0c000000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <4>; + interrupt-parent = <&gic>; + interrupt-controller; + reg = <0 0x0c000000 0 0x40000>, /* GICD */ + <0 0x0c040000 0 0x200000>; /* GICR */ + interrupts = ; + + ppi-partitions { + ppi_cluster0: interrupt-partition-0 { + affinity = <&cpu0 &cpu1 \ + &cpu2 &cpu3 &cpu4 &cpu5>; + }; + ppi_cluster1: interrupt-partition-1 { + affinity = <&cpu6 &cpu7>; + }; + }; + + }; + + sysirq: intpol-controller@0c53a650 { + compatible = "mediatek,mt6779-sysirq", + "mediatek,mt6577-sysirq"; + interrupt-controller; + #interrupt-cells = <3>; + interrupt-parent = <&gic>; + reg = <0 0x0c53a650 0 0x50>; + }; + + topckgen: clock-controller@10000000 { + compatible = "mediatek,mt6779-topckgen", "syscon"; + reg = <0 0x10000000 0 0x1000>; + #clock-cells = <1>; + }; + + infracfg_ao: clock-controller@10001000 { + compatible = "mediatek,mt6779-infracfg_ao", "syscon"; + reg = <0 0x10001000 0 0x1000>; + #clock-cells = <1>; + }; + + pio: pinctrl@10005000 { + compatible = "mediatek,mt6779-pinctrl", "syscon"; + reg = <0 0x10005000 0 0x1000>, + <0 0x11c20000 0 0x1000>, + <0 0x11d10000 0 0x1000>, + <0 0x11e20000 0 0x1000>, + <0 0x11e70000 0 0x1000>, + <0 0x11ea0000 0 0x1000>, + <0 0x11f20000 0 0x1000>, + <0 0x11f30000 0 0x1000>, + <0 0x1000b000 0 0x1000>; + reg-names = "gpio", "iocfg_rm", + "iocfg_br", "iocfg_lm", + "iocfg_lb", "iocfg_rt", + "iocfg_lt", "iocfg_tl", + "eint"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pio 0 0 210>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = ; + }; + + apmixed: clock-controller@1000c000 { + compatible = "mediatek,mt6779-apmixed", "syscon"; + reg = <0 0x1000c000 0 0xe00>; + #clock-cells = <1>; + }; + + uart0: serial@11002000 { + compatible = "mediatek,mt6779-uart", + "mediatek,mt6577-uart"; + reg = <0 0x11002000 0 0x400>; + interrupts = ; + clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_UART0>; + clock-names = "baud", "bus"; + status = "disabled"; + }; + + uart1: serial@11003000 { + compatible = "mediatek,mt6779-uart", + "mediatek,mt6577-uart"; + reg = <0 0x11003000 0 0x400>; + interrupts = ; + clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_UART1>; + clock-names = "baud", "bus"; + status = "disabled"; + }; + + uart2: serial@11004000 { + compatible = "mediatek,mt6779-uart", + "mediatek,mt6577-uart"; + reg = <0 0x11004000 0 0x400>; + interrupts = ; + clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_UART2>; + clock-names = "baud", "bus"; + status = "disabled"; + }; + + audio: clock-controller@11210000 { + compatible = "mediatek,mt6779-audio", "syscon"; + reg = <0 0x11210000 0 0x1000>; + #clock-cells = <1>; + }; + + mfgcfg: clock-controller@13fbf000 { + compatible = "mediatek,mt6779-mfgcfg", "syscon"; + reg = <0 0x13fbf000 0 0x1000>; + #clock-cells = <1>; + }; + + mmsys: syscon@14000000 { + compatible = "mediatek,mt6779-mmsys", "syscon"; + reg = <0 0x14000000 0 0x1000>; + #clock-cells = <1>; + }; + + imgsys: clock-controller@15020000 { + compatible = "mediatek,mt6779-imgsys", "syscon"; + reg = <0 0x15020000 0 0x1000>; + #clock-cells = <1>; + }; + + vdecsys: clock-controller@16000000 { + compatible = "mediatek,mt6779-vdecsys", "syscon"; + reg = <0 0x16000000 0 0x1000>; + #clock-cells = <1>; + }; + + vencsys: clock-controller@17000000 { + compatible = "mediatek,mt6779-vencsys", "syscon"; + reg = <0 0x17000000 0 0x1000>; + #clock-cells = <1>; + }; + + camsys: clock-controller@1a000000 { + compatible = "mediatek,mt6779-camsys", "syscon"; + reg = <0 0x1a000000 0 0x10000>; + #clock-cells = <1>; + }; + + ipesys: clock-controller@1b000000 { + compatible = "mediatek,mt6779-ipesys", "syscon"; + reg = <0 0x1b000000 0 0x1000>; + #clock-cells = <1>; + }; + + }; +}; From e55c56df43dd11de4a6c08e3ea52ca45b51c8800 Mon Sep 17 00:00:00 2001 From: Fabien Parent Date: Sun, 18 Oct 2020 21:42:25 +0200 Subject: [PATCH 021/799] arm64: dts: mediatek: mt8183: fix gce incorrect mbox-cells value The binding documentation says: - #mbox-cells: Should be 2. <&phandle channel priority> phandle: Label name of a gce node. channel: Channel of mailbox. Be equal to the thread id of GCE. priority: Priority of GCE thread. Fix the value of #mbox-cells. Fixes: d3c306e31bc7 ("arm64: dts: add gce node for mt8183") Signed-off-by: Fabien Parent Link: https://lore.kernel.org/r/20201018194225.3361182-1-fparent@baylibre.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8183.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi index 9cfd961c45eb..08a914d3a643 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi @@ -363,7 +363,7 @@ compatible = "mediatek,mt8183-gce"; reg = <0 0x10238000 0 0x4000>; interrupts = ; - #mbox-cells = <3>; + #mbox-cells = <2>; clocks = <&infracfg CLK_INFRA_GCE>; clock-names = "gce"; }; From 54e9f3633ed1bc22033de27dec733415bd750eda Mon Sep 17 00:00:00 2001 From: Fabien Parent Date: Mon, 12 Oct 2020 22:52:17 +0200 Subject: [PATCH 022/799] dt-bindings: iio: adc: auxadc: add doc for MT8516 SoC Add documentation for the auxadc binding for MT8516 SoC. Signed-off-by: Fabien Parent Reviewed-by: Matthias Brugger Acked-by: Rob Herring Link: https://lore.kernel.org/r/20201012205218.3010868-1-fparent@baylibre.com Signed-off-by: Matthias Brugger --- Documentation/devicetree/bindings/iio/adc/mt6577_auxadc.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/iio/adc/mt6577_auxadc.txt b/Documentation/devicetree/bindings/iio/adc/mt6577_auxadc.txt index 78c06e05c8e5..1b7ff9e5615a 100644 --- a/Documentation/devicetree/bindings/iio/adc/mt6577_auxadc.txt +++ b/Documentation/devicetree/bindings/iio/adc/mt6577_auxadc.txt @@ -17,6 +17,7 @@ Required properties: - "mediatek,mt7622-auxadc": For MT7622 family of SoCs - "mediatek,mt8173-auxadc": For MT8173 family of SoCs - "mediatek,mt8183-auxadc", "mediatek,mt8173-auxadc": For MT8183 family of SoCs + - "mediatek,mt8516-auxadc", "mediatek,mt8173-auxadc": For MT8516 family of SoCs - reg: Address range of the AUXADC unit. - clocks: Should contain a clock specifier for each entry in clock-names - clock-names: Should contain "main". From 204b9cd58f4c27c1b43bfbeab4ad418504a3ae6b Mon Sep 17 00:00:00 2001 From: Fabien Parent Date: Mon, 12 Oct 2020 22:52:18 +0200 Subject: [PATCH 023/799] arm64: dts: mediatek: mt8516: add auxadc node Add node for the auxadc IP. The IP is compatible with the one found in MT8173 SoC. Signed-off-by: Fabien Parent Link: https://lore.kernel.org/r/20201012205218.3010868-2-fparent@baylibre.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8516.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8516.dtsi b/arch/arm64/boot/dts/mediatek/mt8516.dtsi index 89af661e7f63..943c426e9aaf 100644 --- a/arch/arm64/boot/dts/mediatek/mt8516.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8516.dtsi @@ -470,5 +470,15 @@ #phy-cells = <1>; }; }; + + auxadc: adc@11003000 { + compatible = "mediatek,mt8516-auxadc", + "mediatek,mt8173-auxadc"; + reg = <0 0x11003000 0 0x1000>; + clocks = <&topckgen CLK_TOP_AUX_ADC>; + clock-names = "main"; + #io-channel-cells = <1>; + status = "disabled"; + }; }; }; From 5fae271026990f684da7e364ec5abc9df1d0563d Mon Sep 17 00:00:00 2001 From: Fabien Parent Date: Wed, 14 Oct 2020 18:24:03 +0200 Subject: [PATCH 024/799] arm64: dts: mediatek: mt8516: rename usb phy The USB phy node is named usb0_phy but there is only one phy with 2 ports on MT8516. Rename the phy to make it more obvious it can also support the usb1 node. The usb1 node will be added in a follow-up commit. Signed-off-by: Fabien Parent Link: https://lore.kernel.org/r/20201014162404.1312544-1-fparent@baylibre.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8516.dtsi | 2 +- arch/arm64/boot/dts/mediatek/pumpkin-common.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8516.dtsi b/arch/arm64/boot/dts/mediatek/mt8516.dtsi index 943c426e9aaf..50049b6c1ba7 100644 --- a/arch/arm64/boot/dts/mediatek/mt8516.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8516.dtsi @@ -455,7 +455,7 @@ status = "disabled"; }; - usb0_phy: usb@11110000 { + usb_phy: usb@11110000 { compatible = "mediatek,generic-tphy-v1"; reg = <0 0x11110000 0 0x800>; #address-cells = <2>; diff --git a/arch/arm64/boot/dts/mediatek/pumpkin-common.dtsi b/arch/arm64/boot/dts/mediatek/pumpkin-common.dtsi index 29d8cf6df46b..3e5a8dfda0c0 100644 --- a/arch/arm64/boot/dts/mediatek/pumpkin-common.dtsi +++ b/arch/arm64/boot/dts/mediatek/pumpkin-common.dtsi @@ -195,7 +195,7 @@ }; }; -&usb0_phy { +&usb_phy { status = "okay"; }; From 40fe44cab01cb93e124db5d9a9cc290e1ac3f14e Mon Sep 17 00:00:00 2001 From: Fabien Parent Date: Wed, 14 Oct 2020 18:24:04 +0200 Subject: [PATCH 025/799] arm64: dts: mediatek: mt8516: add usb1 node The MT8516 has 2 USB instances. Add support for the second USB instance. usb1 can only work in host mode. Signed-off-by: Fabien Parent Link: https://lore.kernel.org/r/20201014162404.1312544-2-fparent@baylibre.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8516.dtsi | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8516.dtsi b/arch/arm64/boot/dts/mediatek/mt8516.dtsi index 50049b6c1ba7..eca7969e15ab 100644 --- a/arch/arm64/boot/dts/mediatek/mt8516.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8516.dtsi @@ -455,6 +455,20 @@ status = "disabled"; }; + usb1: usb@11190000 { + compatible = "mediatek,mtk-musb"; + reg = <0 0x11190000 0 0x1000>; + interrupts = ; + interrupt-names = "mc"; + phys = <&usb1_port PHY_TYPE_USB2>; + clocks = <&topckgen CLK_TOP_USB>, + <&topckgen CLK_TOP_USBIF>, + <&topckgen CLK_TOP_USB_1P>; + clock-names = "main","mcu","univpll"; + dr_mode = "host"; + status = "disabled"; + }; + usb_phy: usb@11110000 { compatible = "mediatek,generic-tphy-v1"; reg = <0 0x11110000 0 0x800>; @@ -469,6 +483,13 @@ clock-names = "ref"; #phy-cells = <1>; }; + + usb1_port: usb-phy@11110900 { + reg = <0 0x11110900 0 0x100>; + clocks = <&topckgen CLK_TOP_USB_PHY48M>; + clock-names = "ref"; + #phy-cells = <1>; + }; }; auxadc: adc@11003000 { From 2612afd9b97964b67040e7883148ee7251a42776 Mon Sep 17 00:00:00 2001 From: Serge Semin Date: Tue, 20 Oct 2020 14:59:54 +0300 Subject: [PATCH 026/799] arm64: dts: allwinner: h6: Harmonize DWC USB3 DT nodes name In accordance with the DWC USB3 bindings the corresponding node name is suppose to comply with the Generic USB HCD DT schema, which requires the USB nodes to have the name acceptable by the regexp: "^usb(@.*)?" . Make sure the "snps,dwc3"-compatible nodes are correctly named. Signed-off-by: Serge Semin Signed-off-by: Maxime Ripard Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20201020115959.2658-25-Sergey.Semin@baikalelectronics.ru --- arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi index 28c77d6872f6..28c4a79b8a45 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi @@ -680,7 +680,7 @@ status = "disabled"; }; - dwc3: dwc3@5200000 { + dwc3: usb@5200000 { compatible = "snps,dwc3"; reg = <0x05200000 0x10000>; interrupts = ; From 9dcd17be61e4b6343cc612a3f6c30512acee60b9 Mon Sep 17 00:00:00 2001 From: Grygorii Strashko Date: Sat, 29 Aug 2020 21:41:39 +0300 Subject: [PATCH 027/799] arm64: dts: ti: k3-am65: ringacc: drop ti, dma-ring-reset-quirk Remove obsolete "ti,dma-ring-reset-quirk" Ringacc DT property. Signed-off-by: Grygorii Strashko Signed-off-by: Nishanth Menon Link: https://lore.kernel.org/r/20200829184139.15547-4-grygorii.strashko@ti.com --- arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 1 - arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi | 1 - 2 files changed, 2 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi index 533525229a8d..3eeb6e9876db 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi @@ -612,7 +612,6 @@ reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target"; ti,num-rings = <818>; ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */ - ti,dma-ring-reset-quirk; ti,sci = <&dmsc>; ti,sci-dev-id = <187>; msi-parent = <&inta_main_udmass>; diff --git a/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi b/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi index 29aaf8dca6f6..044042b166d9 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi @@ -135,7 +135,6 @@ reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target"; ti,num-rings = <286>; ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */ - ti,dma-ring-reset-quirk; ti,sci = <&dmsc>; ti,sci-dev-id = <195>; msi-parent = <&inta_main_udmass>; From 4af5c6dc255ca64e5263a5254bb7553f05bb682c Mon Sep 17 00:00:00 2001 From: Kathiravan T Date: Wed, 14 Oct 2020 21:16:17 +0530 Subject: [PATCH 028/799] arm64: dts: ipq6018: update the reserved-memory node Memory region reserved for the TZ is changed long back. Let's update the same to align with the corret region. Its size also increased to 4MB from 2MB. Along with that, bump the Q6 region size to 85MB. Fixes: 1e8277854b49 ("arm64: dts: Add ipq6018 SoC and CP01 board support") Signed-off-by: Kathiravan T Link: https://lore.kernel.org/r/1602690377-21304-1-git-send-email-kathirav@codeaurora.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/ipq6018.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi index a94dac76bf3f..973b2c860ec9 100644 --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi @@ -156,8 +156,8 @@ no-map; }; - tz: tz@48500000 { - reg = <0x0 0x48500000 0x0 0x00200000>; + tz: memory@4a600000 { + reg = <0x0 0x4a600000 0x0 0x00400000>; no-map; }; @@ -167,7 +167,7 @@ }; q6_region: memory@4ab00000 { - reg = <0x0 0x4ab00000 0x0 0x02800000>; + reg = <0x0 0x4ab00000 0x0 0x05500000>; no-map; }; }; From 228813aaa71113d7a12313b87c4905a9d3f9df37 Mon Sep 17 00:00:00 2001 From: Douglas Anderson Date: Thu, 1 Oct 2020 14:18:55 -0700 Subject: [PATCH 029/799] arm64: dts: qcom: sc7180: Fix one forgotten interconnect reference In commit e23b1220a246 ("arm64: dts: qcom: sc7180: Increase the number of interconnect cells") we missed increasing the cells on one interconnect. That's no bueno. Fix it. NOTE: it appears that things aren't totally broken without this fix, but clearly something isn't going to be working right. If nothing else, without this fix I see this in the logs: OF: /soc@0/mdss@ae00000: could not get #interconnect-cells for /soc@0/interrupt-controller@17a00000 Fixes: e23b1220a246 ("arm64: dts: qcom: sc7180: Increase the number of interconnect cells") Reviewed-by: Georgi Djakov Reviewed-by: Rob Clark Signed-off-by: Douglas Anderson Link: https://lore.kernel.org/r/20201001141838.1.I08054d1d976eed64ffa1b0e21d568e0dc6040b54@changeid Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc7180.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index 6678f1e8e395..a02776ce77a1 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -2811,7 +2811,7 @@ interrupt-controller; #interrupt-cells = <1>; - interconnects = <&mmss_noc MASTER_MDP0 &mc_virt SLAVE_EBI1>; + interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "mdp0-mem"; iommus = <&apps_smmu 0x800 0x2>; From 486d49914307e4e1ff0f5087f803cfa1e44a13bf Mon Sep 17 00:00:00 2001 From: Iskren Chernev Date: Sun, 20 Sep 2020 17:48:53 +0300 Subject: [PATCH 030/799] ARM: dts: qcom: msm8974-klte: Merge pinctrl nodes commit cd13c72c1853f219e1f ("ARM: dts: qcom: msm8974-klte: Add max77826 pmic node") and commit 8bf7a360a92cc6b2aebc8 ("ARM: dts: qcom: msm8974-klte: Add sdhci1 node") both added pinctrl node. This patch merges the two nodes. Signed-off-by: Iskren Chernev Link: https://lore.kernel.org/r/20200920144859.813032-2-iskren.chernev@gmail.com Signed-off-by: Bjorn Andersson --- .../boot/dts/qcom-msm8974-samsung-klte.dts | 22 +++++++++---------- 1 file changed, 10 insertions(+), 12 deletions(-) diff --git a/arch/arm/boot/dts/qcom-msm8974-samsung-klte.dts b/arch/arm/boot/dts/qcom-msm8974-samsung-klte.dts index d4dc98214225..9520c6e7910c 100644 --- a/arch/arm/boot/dts/qcom-msm8974-samsung-klte.dts +++ b/arch/arm/boot/dts/qcom-msm8974-samsung-klte.dts @@ -258,6 +258,16 @@ bias-pull-up; }; }; + + i2c6_pins: i2c6 { + mux { + pins = "gpio29", "gpio30"; + function = "blsp_i2c6"; + + drive-strength = <2>; + bias-disable; + }; + }; }; sdhci@f9824900 { @@ -298,18 +308,6 @@ }; }; - pinctrl@fd510000 { - i2c6_pins: i2c6 { - mux { - pins = "gpio29", "gpio30"; - function = "blsp_i2c6"; - - drive-strength = <2>; - bias-disable; - }; - }; - }; - i2c@f9928000 { status = "okay"; From a193dc521c97c07098bf0b6345966561a1f0ab9f Mon Sep 17 00:00:00 2001 From: Iskren Chernev Date: Sun, 20 Sep 2020 17:48:54 +0300 Subject: [PATCH 031/799] ARM: dts: qcom: msm8974-klte: Add support for touchkey Add support for the touchkey found on the Samsung Galaxy S5. The touchkey is responsible for handling the application and back buttons found around the home button. Signed-off-by: Iskren Chernev Link: https://lore.kernel.org/r/20200920144859.813032-3-iskren.chernev@gmail.com Signed-off-by: Bjorn Andersson --- .../boot/dts/qcom-msm8974-samsung-klte.dts | 44 ++++++++++++++++++- 1 file changed, 43 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/qcom-msm8974-samsung-klte.dts b/arch/arm/boot/dts/qcom-msm8974-samsung-klte.dts index 9520c6e7910c..750e2f261139 100644 --- a/arch/arm/boot/dts/qcom-msm8974-samsung-klte.dts +++ b/arch/arm/boot/dts/qcom-msm8974-samsung-klte.dts @@ -145,7 +145,7 @@ }; pma8084_l19: l19 { - regulator-min-microvolt = <2900000>; + regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; }; @@ -203,6 +203,31 @@ }; }; + i2c-gpio-touchkey { + compatible = "i2c-gpio"; + #address-cells = <1>; + #size-cells = <0>; + sda-gpios = <&msmgpio 95 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&msmgpio 96 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c_touchkey_pins>; + + touchkey@20 { + compatible = "cypress,tm2-touchkey"; + reg = <0x20>; + + interrupt-parent = <&pma8084_gpios>; + interrupts = <6 IRQ_TYPE_EDGE_FALLING>; + pinctrl-names = "default"; + pinctrl-0 = <&touchkey_pin>; + + vcc-supply = <&max77826_ldo15>; + vdd-supply = <&pma8084_l19>; + + linux,keycodes = ; + }; + }; + /delete-node/ vreg-boost; }; @@ -268,6 +293,15 @@ bias-disable; }; }; + + i2c_touchkey_pins: i2c-touchkey { + mux { + pins = "gpio95", "gpio96"; + function = "gpio"; + input-enable; + bias-pull-up; + }; + }; }; sdhci@f9824900 { @@ -418,6 +452,14 @@ bias-pull-up; power-source = ; }; + + touchkey_pin: touchkey-int-pin { + pins = "gpio6"; + function = "normal"; + bias-disable; + input-enable; + power-source = ; + }; }; }; }; From 972f5a62a698857f4a02a6667f53ca158ce7421d Mon Sep 17 00:00:00 2001 From: Iskren Chernev Date: Sun, 20 Sep 2020 17:48:55 +0300 Subject: [PATCH 032/799] ARM: dts: qcom: msm8974-klte: Add support for touchscreen Add support for the touchscreen found on the Samsung Galaxy S5. Signed-off-by: Iskren Chernev Link: https://lore.kernel.org/r/20200920144859.813032-4-iskren.chernev@gmail.com Signed-off-by: Bjorn Andersson --- .../boot/dts/qcom-msm8974-samsung-klte.dts | 54 +++++++++++++++++++ 1 file changed, 54 insertions(+) diff --git a/arch/arm/boot/dts/qcom-msm8974-samsung-klte.dts b/arch/arm/boot/dts/qcom-msm8974-samsung-klte.dts index 750e2f261139..085636f182d0 100644 --- a/arch/arm/boot/dts/qcom-msm8974-samsung-klte.dts +++ b/arch/arm/boot/dts/qcom-msm8974-samsung-klte.dts @@ -284,6 +284,16 @@ }; }; + i2c2_pins: i2c2 { + mux { + pins = "gpio6", "gpio7"; + function = "blsp_i2c2"; + + drive-strength = <2>; + bias-disable; + }; + }; + i2c6_pins: i2c6 { mux { pins = "gpio29", "gpio30"; @@ -342,6 +352,42 @@ }; }; + i2c@f9924000 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins>; + + touchscreen@20 { + compatible = "syna,rmi4-i2c"; + reg = <0x20>; + + interrupt-parent = <&pma8084_gpios>; + interrupts = <8 IRQ_TYPE_EDGE_FALLING>; + + vdd-supply = <&max77826_ldo13>; + vio-supply = <&pma8084_lvs2>; + + pinctrl-names = "default"; + pinctrl-0 = <&touch_pin>; + + syna,startup-delay-ms = <100>; + + #address-cells = <1>; + #size-cells = <0>; + + rmi4-f01@1 { + reg = <0x1>; + syna,nosleep-mode = <1>; + }; + + rmi4-f12@12 { + reg = <0x12>; + syna,sensor-type = <1>; + }; + }; + }; + i2c@f9928000 { status = "okay"; @@ -460,6 +506,14 @@ input-enable; power-source = ; }; + + touch_pin: touchscreen-int-pin { + pins = "gpio8"; + function = "normal"; + bias-disable; + input-enable; + power-source = ; + }; }; }; }; From 60367221d7d46d623dbef4cd30924e99c97ff2e5 Mon Sep 17 00:00:00 2001 From: Iskren Chernev Date: Sun, 20 Sep 2020 17:48:56 +0300 Subject: [PATCH 033/799] ARM: dts: qcom: msm8974-klte: Add support for led The klte uses a Panasonic AN30259A LED controller for it's indicator led. Signed-off-by: Iskren Chernev Link: https://lore.kernel.org/r/20200920144859.813032-5-iskren.chernev@gmail.com Signed-off-by: Bjorn Andersson --- .../boot/dts/qcom-msm8974-samsung-klte.dts | 48 +++++++++++++++++++ 1 file changed, 48 insertions(+) diff --git a/arch/arm/boot/dts/qcom-msm8974-samsung-klte.dts b/arch/arm/boot/dts/qcom-msm8974-samsung-klte.dts index 085636f182d0..7b398da9b75e 100644 --- a/arch/arm/boot/dts/qcom-msm8974-samsung-klte.dts +++ b/arch/arm/boot/dts/qcom-msm8974-samsung-klte.dts @@ -4,6 +4,7 @@ #include #include #include +#include / { model = "Samsung Galaxy S5"; @@ -228,6 +229,44 @@ }; }; + i2c-gpio-led { + compatible = "i2c-gpio"; + #address-cells = <1>; + #size-cells = <0>; + scl-gpios = <&msmgpio 121 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&msmgpio 120 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c_led_pins>; + + i2c-gpio,delay-us = <2>; + + led-controller@30 { + compatible = "panasonic,an30259a"; + reg = <0x30>; + + #address-cells = <1>; + #size-cells = <0>; + + led@1 { + reg = <1>; + function = LED_FUNCTION_STATUS; + color = ; + }; + + led@2 { + reg = <2>; + function = LED_FUNCTION_STATUS; + color = ; + }; + + led@3 { + reg = <3>; + function = LED_FUNCTION_STATUS; + color = ; + }; + }; + }; + /delete-node/ vreg-boost; }; @@ -312,6 +351,15 @@ bias-pull-up; }; }; + + i2c_led_pins: i2c-led { + mux { + pins = "gpio120", "gpio121"; + function = "gpio"; + input-enable; + bias-pull-down; + }; + }; }; sdhci@f9824900 { From 99128e7503bed5475aadd10fa97b1d7ffc5a35c2 Mon Sep 17 00:00:00 2001 From: Iskren Chernev Date: Sun, 20 Sep 2020 17:48:57 +0300 Subject: [PATCH 034/799] ARM: dts: qcom: msm8974-klte: Add gpio expander chip The Samsung Galaxy S5 has a GPIO Expander chip, the PCAL6416A with 16 ports on a i2c bus. These pins are used for WiFi, NFC, IR among other things. Signed-off-by: Iskren Chernev Link: https://lore.kernel.org/r/20200920144859.813032-6-iskren.chernev@gmail.com Signed-off-by: Bjorn Andersson --- .../boot/dts/qcom-msm8974-samsung-klte.dts | 29 +++++++++++++++++-- 1 file changed, 27 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/qcom-msm8974-samsung-klte.dts b/arch/arm/boot/dts/qcom-msm8974-samsung-klte.dts index 7b398da9b75e..29099b83b231 100644 --- a/arch/arm/boot/dts/qcom-msm8974-samsung-klte.dts +++ b/arch/arm/boot/dts/qcom-msm8974-samsung-klte.dts @@ -236,10 +236,25 @@ scl-gpios = <&msmgpio 121 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; sda-gpios = <&msmgpio 120 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; pinctrl-names = "default"; - pinctrl-0 = <&i2c_led_pins>; + pinctrl-0 = <&i2c_led_gpioex_pins>; i2c-gpio,delay-us = <2>; + gpio_expander: gpio@20 { + compatible = "nxp,pcal6416"; + reg = <0x20>; + + gpio-controller; + #gpio-cells = <2>; + + vcc-supply = <&pma8084_s4>; + + pinctrl-names = "default"; + pinctrl-0 = <&gpioex_pin>; + + reset-gpios = <&msmgpio 145 GPIO_ACTIVE_LOW>; + }; + led-controller@30 { compatible = "panasonic,an30259a"; reg = <0x30>; @@ -352,7 +367,7 @@ }; }; - i2c_led_pins: i2c-led { + i2c_led_gpioex_pins: i2c-led-gpioex { mux { pins = "gpio120", "gpio121"; function = "gpio"; @@ -360,6 +375,16 @@ bias-pull-down; }; }; + + gpioex_pin: gpioex { + res { + pins = "gpio145"; + function = "gpio"; + + bias-pull-up; + drive-strength = <2>; + }; + }; }; sdhci@f9824900 { From 19524d5b1700616d4cfad9922238bd31ad758074 Mon Sep 17 00:00:00 2001 From: Iskren Chernev Date: Sun, 20 Sep 2020 17:48:58 +0300 Subject: [PATCH 035/799] ARM: dts: qcom: msm8974-klte: Add support for wifi The Samsung Galaxy S5 (klte), uses a Broadcom 4354 Chip connected on the SDIO bus. The chip also requires a corresponding firmware + txt file[1]. [1] https://gitlab.com/postmarketOS/pmaports/-/blob/master/firmware/firmware-samsung-klte/APKBUILD Signed-off-by: Iskren Chernev Link: https://lore.kernel.org/r/20200920144859.813032-7-iskren.chernev@gmail.com Signed-off-by: Bjorn Andersson --- .../boot/dts/qcom-msm8974-samsung-klte.dts | 74 +++++++++++++++++++ 1 file changed, 74 insertions(+) diff --git a/arch/arm/boot/dts/qcom-msm8974-samsung-klte.dts b/arch/arm/boot/dts/qcom-msm8974-samsung-klte.dts index 29099b83b231..989447beb431 100644 --- a/arch/arm/boot/dts/qcom-msm8974-samsung-klte.dts +++ b/arch/arm/boot/dts/qcom-msm8974-samsung-klte.dts @@ -282,6 +282,17 @@ }; }; + vreg_wlan: wlan-regulator { + compatible = "regulator-fixed"; + + regulator-name = "wl-reg"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&gpio_expander 8 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + /delete-node/ vreg-boost; }; @@ -338,6 +349,20 @@ }; }; + sdhc3_pin_a: sdhc3-pin-active { + clk { + pins = "sdc2_clk"; + drive-strength = <6>; + bias-disable; + }; + + cmd-data { + pins = "sdc2_cmd", "sdc2_data"; + drive-strength = <6>; + bias-pull-up; + }; + }; + i2c2_pins: i2c2 { mux { pins = "gpio6", "gpio7"; @@ -385,6 +410,16 @@ drive-strength = <2>; }; }; + + wifi_pin: wifi { + int { + pins = "gpio92"; + function = "gpio"; + + input-enable; + bias-pull-down; + }; + }; }; sdhci@f9824900 { @@ -400,6 +435,36 @@ pinctrl-0 = <&sdhc1_pin_a>; }; + sdhci@f98a4900 { + status = "okay"; + + #address-cells = <1>; + #size-cells = <0>; + + max-frequency = <100000000>; + + pinctrl-names = "default"; + pinctrl-0 = <&sdhc3_pin_a>; + + vmmc-supply = <&vreg_wlan>; + vqmmc-supply = <&pma8084_s4>; + + bus-width = <4>; + non-removable; + + wifi@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + + interrupt-parent = <&msmgpio>; + interrupts = <92 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "host-wake"; + + pinctrl-names = "default"; + pinctrl-0 = <&wlan_sleep_clk_pin &wifi_pin>; + }; + }; + usb@f9a55000 { status = "ok"; @@ -587,6 +652,15 @@ input-enable; power-source = ; }; + + wlan_sleep_clk_pin: wlan-sleep-clk-pin { + pins = "gpio16"; + function = "func2"; + + output-high; + power-source = ; + qcom,drive-strength = ; + }; }; }; }; From 5434dcef54964e1f8a293e43b93ba6b45cc477ae Mon Sep 17 00:00:00 2001 From: Iskren Chernev Date: Sun, 20 Sep 2020 17:48:59 +0300 Subject: [PATCH 036/799] ARM: dts: qcom: msm8974-klte: Add support for SD card The Samsung Galaxy S5 (klte), has 3 SDHCI nodes used for internal storage, WiFi, external SD card slot. The external SD card slot is similar to the internal storage. Signed-off-by: Iskren Chernev Link: https://lore.kernel.org/r/20200920144859.813032-8-iskren.chernev@gmail.com Signed-off-by: Bjorn Andersson --- .../boot/dts/qcom-msm8974-samsung-klte.dts | 44 ++++++++++++++++++- 1 file changed, 43 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/qcom-msm8974-samsung-klte.dts b/arch/arm/boot/dts/qcom-msm8974-samsung-klte.dts index 989447beb431..b0899107f3ce 100644 --- a/arch/arm/boot/dts/qcom-msm8974-samsung-klte.dts +++ b/arch/arm/boot/dts/qcom-msm8974-samsung-klte.dts @@ -12,6 +12,8 @@ aliases { serial0 = &blsp1_uart1; + sdhc1 = &sdhc_1; /* SDC1 eMMC slot */ + sdhc2 = &sdhc_2; /* SDC2 SD card slot */ }; chosen { @@ -161,6 +163,9 @@ pma8084_l21: l21 { regulator-min-microvolt = <2950000>; regulator-max-microvolt = <2950000>; + + regulator-allow-set-load; + regulator-system-load = <200000>; }; pma8084_l22: l22 { @@ -349,6 +354,24 @@ }; }; + sdhc2_pin_a: sdhc2-pin-active { + clk-cmd-data { + pins = "gpio35", "gpio36", "gpio37", "gpio38", + "gpio39", "gpio40"; + function = "sdc3"; + drive-strength = <8>; + bias-disable; + }; + }; + + sdhc2_cd_pin: sdhc2-cd { + pins = "gpio62"; + function = "gpio"; + + drive-strength = <2>; + bias-disable; + }; + sdhc3_pin_a: sdhc3-pin-active { clk { pins = "sdc2_clk"; @@ -422,7 +445,7 @@ }; }; - sdhci@f9824900 { + sdhc_1: sdhci@f9824900 { status = "ok"; vmmc-supply = <&pma8084_l20>; @@ -435,6 +458,25 @@ pinctrl-0 = <&sdhc1_pin_a>; }; + sdhc_2: sdhci@f9864900 { + status = "ok"; + + max-frequency = <100000000>; + + vmmc-supply = <&pma8084_l21>; + vqmmc-supply = <&pma8084_l13>; + + bus-width = <4>; + + /* cd-gpio is intentionally disabled. If enabled, an SD card + * present during boot is not initialized correctly. Without + * cd-gpios the driver resorts to polling, so hotplug works. + */ + pinctrl-names = "default"; + pinctrl-0 = <&sdhc2_pin_a /* &sdhc2_cd_pin */>; + // cd-gpios = <&msmgpio 62 GPIO_ACTIVE_LOW>; + }; + sdhci@f98a4900 { status = "okay"; From 2709436ecf38d12b70c7bf4eed4ff65ba5f41f04 Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Wed, 16 Sep 2020 12:41:29 +0200 Subject: [PATCH 037/799] arm64: dts: qcom: msm8916: Add RPM power domains MSM8916 has two RPM power domains: VDDCX and VDDMX. So far we have been managing them by voting for raw voltages through the regulator subsystem, but it's better to manage them with corners as actual power domains. Add the device tree node for rpmpd so we can manage them as real power domains instead of using the regulators. Signed-off-by: Stephan Gerhold Link: https://lore.kernel.org/r/20200916104135.25085-5-stephan@gerhold.net Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8916.dtsi | 29 +++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index aaa21899f1a6..117804f94c35 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -289,6 +289,35 @@ compatible = "qcom,rpmcc-msm8916"; #clock-cells = <1>; }; + + rpmpd: power-controller { + compatible = "qcom,msm8916-rpmpd"; + #power-domain-cells = <1>; + operating-points-v2 = <&rpmpd_opp_table>; + + rpmpd_opp_table: opp-table { + compatible = "operating-points-v2"; + + rpmpd_opp_ret: opp1 { + opp-level = <1>; + }; + rpmpd_opp_svs_krait: opp2 { + opp-level = <2>; + }; + rpmpd_opp_svs_soc: opp3 { + opp-level = <3>; + }; + rpmpd_opp_nom: opp4 { + opp-level = <4>; + }; + rpmpd_opp_turbo: opp5 { + opp-level = <5>; + }; + rpmpd_opp_super_turbo: opp6 { + opp-level = <6>; + }; + }; + }; }; }; }; From 809f299a969873581c832bbcb1b8cccaf8af2eeb Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Wed, 16 Sep 2020 12:41:34 +0200 Subject: [PATCH 038/799] arm64: dts: qcom: msm8916: Use power domains for MSS/WCNSS remoteprocs So far we have been making proxy votes for the remote processors through the regulator interface. Now that we have rpmpd it's better to vote for performance states through the power domain interface. This also allows us to move these supplies back to msm8916.dtsi because the device tree binding for RPMPD is independent of the underlying regulator/PMIC. Signed-off-by: Stephan Gerhold Link: https://lore.kernel.org/r/20200916104135.25085-10-stephan@gerhold.net Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8916-pm8916.dtsi | 3 --- arch/arm64/boot/dts/qcom/msm8916.dtsi | 9 +++++++++ 2 files changed, 9 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8916-pm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916-pm8916.dtsi index cd626e7db599..513e433aa5f3 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-pm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916-pm8916.dtsi @@ -17,13 +17,10 @@ }; &mpss { - cx-supply = <&pm8916_s1>; - mx-supply = <&pm8916_l3>; pll-supply = <&pm8916_l7>; }; &pronto { - vddmx-supply = <&pm8916_l3>; vddpx-supply = <&pm8916_l7>; iris { diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index 117804f94c35..74aa50f3db10 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -8,6 +8,7 @@ #include #include #include +#include #include #include @@ -1292,6 +1293,10 @@ interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack"; + power-domains = <&rpmpd MSM8916_VDDCX>, + <&rpmpd MSM8916_VDDMX>; + power-domain-names = "cx", "mx"; + clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>, <&gcc GCC_BOOT_ROM_AHB_CLK>, @@ -1689,6 +1694,10 @@ <&wcnss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack"; + power-domains = <&rpmpd MSM8916_VDDCX>, + <&rpmpd MSM8916_VDDMX>; + power-domain-names = "cx", "mx"; + qcom,state = <&wcnss_smp2p_out 0>; qcom,state-names = "stop"; From bd1f64bb57f7b6a6f2e8fa9a7b37be55fbc06f73 Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Wed, 16 Sep 2020 12:41:35 +0200 Subject: [PATCH 039/799] arm64: dts: qcom: msm8916-pm8916: Stop using s1/l3 as regulators s1 (VDDCX) and l3 (VDDMX) are now managed by rpmpd as power domains. This allows us to vote for voltage corners instead of voting for raw voltages. But we cannot manage these as regulator and power domain at the same time: The votes by rpmpd would conflict with the ones from the regulator driver. All users of these regulators have been converted to power domains. Make sure that no new users are added by removing s1 and l3 from the regulator definitions. This also allows us to remove the arbitrary voltage constraints we have been using for these regulators. Not all of the voltages listed there would actually have been safe for the boards. Signed-off-by: Stephan Gerhold Link: https://lore.kernel.org/r/20200916104135.25085-11-stephan@gerhold.net Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi | 10 ---------- arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts | 10 ---------- arch/arm64/boot/dts/qcom/msm8916-pm8916.dtsi | 4 ++-- .../boot/dts/qcom/msm8916-samsung-a2015-common.dtsi | 10 ---------- 4 files changed, 2 insertions(+), 32 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi b/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi index 3c7f97539390..3a9538e1ec97 100644 --- a/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi +++ b/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi @@ -417,11 +417,6 @@ vdd_l4_l5_l6-supply = <&pm8916_s4>; vdd_l7-supply = <&pm8916_s4>; - s1 { - regulator-min-microvolt = <375000>; - regulator-max-microvolt = <1562000>; - }; - s3 { regulator-min-microvolt = <375000>; regulator-max-microvolt = <1562000>; @@ -445,11 +440,6 @@ regulator-max-microvolt = <1200000>; }; - l3 { - regulator-min-microvolt = <375000>; - regulator-max-microvolt = <1525000>; - }; - l4 { regulator-min-microvolt = <1750000>; regulator-max-microvolt = <3337000>; diff --git a/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts b/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts index b9d3c5d98dd0..2c204d535d66 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts @@ -98,11 +98,6 @@ vdd_l4_l5_l6-supply = <&pm8916_s4>; vdd_l7-supply = <&pm8916_s4>; - s1 { - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1300000>; - }; - s3 { regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1300000>; @@ -123,11 +118,6 @@ regulator-max-microvolt = <1200000>; }; - l3 { - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1287500>; - }; - l4 { regulator-min-microvolt = <2050000>; regulator-max-microvolt = <2050000>; diff --git a/arch/arm64/boot/dts/qcom/msm8916-pm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916-pm8916.dtsi index 513e433aa5f3..539823b2c36e 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-pm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916-pm8916.dtsi @@ -50,13 +50,13 @@ smd_rpm_regulators: pm8916-regulators { compatible = "qcom,rpm-pm8916-regulators"; - pm8916_s1: s1 {}; + /* pm8916_s1 is managed by rpmpd (MSM8916_VDDCX) */ pm8916_s3: s3 {}; pm8916_s4: s4 {}; pm8916_l1: l1 {}; pm8916_l2: l2 {}; - pm8916_l3: l3 {}; + /* pm8916_l3 is managed by rpmpd (MSM8916_VDDMX) */ pm8916_l4: l4 {}; pm8916_l5: l5 {}; pm8916_l6: l6 {}; diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi b/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi index b18d21e42f59..0b0dfd3059de 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi @@ -164,11 +164,6 @@ vdd_l4_l5_l6-supply = <&pm8916_s4>; vdd_l7-supply = <&pm8916_s4>; - s1 { - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1300000>; - }; - s3 { regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1300000>; @@ -189,11 +184,6 @@ regulator-max-microvolt = <1200000>; }; - l3 { - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1287500>; - }; - l4 { regulator-min-microvolt = <2050000>; regulator-max-microvolt = <2050000>; From 4a6dbc65f6efa76a10ae6b64ad30ea12a991d7f0 Mon Sep 17 00:00:00 2001 From: Alexander Dahl Date: Mon, 5 Oct 2020 22:34:46 +0200 Subject: [PATCH 040/799] ARM: dts: exynos: Fix schema warnings for pwm-leds The node names for devices using the pwm-leds driver follow a certain naming scheme (now). Parent node name is not enforced, but recommended by DT project. arch/arm/boot/dts/exynos5410-odroidxu.dt.yaml: pwmleds: 'blueled', 'greenled' do not match any of the regexes: '^led(-[0-9a-f]+)?$', 'pinctrl-[0-9]+' arch/arm/boot/dts/exynos5422-odroidhc1.dt.yaml: pwmleds: 'blueled' does not match any of the regexes: '^led(-[0-9a-f]+)?$', 'pinctrl-[0-9]+' From schema: Documentation/devicetree/bindings/leds/leds-pwm.yaml Signed-off-by: Alexander Dahl Link: https://lore.kernel.org/r/20201005203451.9985-8-post@lespocky.de Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos5422-odroidhc1.dts | 4 ++-- arch/arm/boot/dts/exynos5422-odroidxu4.dts | 4 ++-- arch/arm/boot/dts/exynos54xx-odroidxu-leds.dtsi | 11 ++++++----- 3 files changed, 10 insertions(+), 9 deletions(-) diff --git a/arch/arm/boot/dts/exynos5422-odroidhc1.dts b/arch/arm/boot/dts/exynos5422-odroidhc1.dts index 812659260278..20c222b33f98 100644 --- a/arch/arm/boot/dts/exynos5422-odroidhc1.dts +++ b/arch/arm/boot/dts/exynos5422-odroidhc1.dts @@ -15,10 +15,10 @@ compatible = "hardkernel,odroid-hc1", "samsung,exynos5800", \ "samsung,exynos5"; - pwmleds { + led-controller { compatible = "pwm-leds"; - blueled { + led-1 { label = "blue:heartbeat"; pwms = <&pwm 2 2000000 0>; pwm-names = "pwm2"; diff --git a/arch/arm/boot/dts/exynos5422-odroidxu4.dts b/arch/arm/boot/dts/exynos5422-odroidxu4.dts index ddd55d3bcadd..ede782257643 100644 --- a/arch/arm/boot/dts/exynos5422-odroidxu4.dts +++ b/arch/arm/boot/dts/exynos5422-odroidxu4.dts @@ -17,10 +17,10 @@ compatible = "hardkernel,odroid-xu4", "samsung,exynos5800", \ "samsung,exynos5"; - pwmleds { + led-controller { compatible = "pwm-leds"; - blueled { + led-1 { label = "blue:heartbeat"; pwms = <&pwm 2 2000000 0>; pwm-names = "pwm2"; diff --git a/arch/arm/boot/dts/exynos54xx-odroidxu-leds.dtsi b/arch/arm/boot/dts/exynos54xx-odroidxu-leds.dtsi index 56acd832f0b3..2fc3e86dc5f7 100644 --- a/arch/arm/boot/dts/exynos54xx-odroidxu-leds.dtsi +++ b/arch/arm/boot/dts/exynos54xx-odroidxu-leds.dtsi @@ -11,10 +11,10 @@ #include / { - pwmleds { + led-controller-1 { compatible = "pwm-leds"; - greenled { + led-1 { label = "green:mmc0"; pwms = <&pwm 1 2000000 0>; pwm-names = "pwm1"; @@ -26,7 +26,7 @@ linux,default-trigger = "mmc0"; }; - blueled { + led-2 { label = "blue:heartbeat"; pwms = <&pwm 2 2000000 0>; pwm-names = "pwm2"; @@ -35,9 +35,10 @@ }; }; - gpioleds { + led-controller-2 { compatible = "gpio-leds"; - redled { + + led-3 { label = "red:microSD"; gpios = <&gpx2 3 GPIO_ACTIVE_HIGH>; default-state = "off"; From 95f075fec383bd15cb0297254d84d3bd880eba9d Mon Sep 17 00:00:00 2001 From: Marek Szyprowski Date: Fri, 9 Oct 2020 15:48:55 +0200 Subject: [PATCH 041/799] ARM: exynos_defconfig: enable sound driver for Midas platform Sound driver for Midas platform (Exnyos4412 SoC based) has been recently merged, so enable it for tests like other sound drivers for Exynos based boards. Signed-off-by: Marek Szyprowski Link: https://lore.kernel.org/r/20201009134855.4520-1-m.szyprowski@samsung.com Signed-off-by: Krzysztof Kozlowski --- arch/arm/configs/exynos_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/configs/exynos_defconfig b/arch/arm/configs/exynos_defconfig index cf82c9d23a08..8c1fd6408108 100644 --- a/arch/arm/configs/exynos_defconfig +++ b/arch/arm/configs/exynos_defconfig @@ -245,6 +245,7 @@ CONFIG_SND_SOC_SMDK_WM8994_PCM=y CONFIG_SND_SOC_SNOW=y CONFIG_SND_SOC_ODROID=y CONFIG_SND_SOC_ARNDALE=y +CONFIG_SND_SOC_SAMSUNG_MIDAS_WM1811=y CONFIG_SND_SIMPLE_CARD=y CONFIG_USB=y CONFIG_USB_ANNOUNCE_NEW_DEVICES=y From c19345ea65a86c0936a3ce04a4035532c77f0187 Mon Sep 17 00:00:00 2001 From: Marek Szyprowski Date: Fri, 9 Oct 2020 15:49:07 +0200 Subject: [PATCH 042/799] ARM: multi_v7_defconfig: enable sound driver for Midas platform Sound driver for Midas platform (Exnyos4412 SoC based) has been recently merged, so enable it for tests like other sound drivers for Exynos based boards. Signed-off-by: Marek Szyprowski Link: https://lore.kernel.org/r/20201009134907.4578-1-m.szyprowski@samsung.com Signed-off-by: Krzysztof Kozlowski --- arch/arm/configs/multi_v7_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig index e731cdf7c88c..138a9e8fe35d 100644 --- a/arch/arm/configs/multi_v7_defconfig +++ b/arch/arm/configs/multi_v7_defconfig @@ -737,6 +737,7 @@ CONFIG_SND_SOC_SMDK_WM8994_PCM=m CONFIG_SND_SOC_SNOW=m CONFIG_SND_SOC_ODROID=m CONFIG_SND_SOC_ARNDALE=m +CONFIG_SND_SOC_SAMSUNG_MIDAS_WM1811=m CONFIG_SND_SOC_SH4_FSI=m CONFIG_SND_SOC_RCAR=m CONFIG_SND_SOC_STI=m From ecc1ff532b499d20304a4f682247137025814c34 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 15 Oct 2020 20:20:41 +0200 Subject: [PATCH 043/799] ARM: dts: exynos: fix roles of USB 3.0 ports on Odroid XU On Odroid XU board the USB3-0 port is a microUSB and USB3-1 port is USB type A (host). The roles were copied from Odroid XU3 (Exynos5422) design which has it reversed. Fixes: 8149afe4dbf9 ("ARM: dts: exynos: Add initial support for Odroid XU board") Signed-off-by: Krzysztof Kozlowski Cc: Link: https://lore.kernel.org/r/20201015182044.480562-1-krzk@kernel.org Tested-by: Gabriel Ribba Esteva --- arch/arm/boot/dts/exynos5410-odroidxu.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/exynos5410-odroidxu.dts b/arch/arm/boot/dts/exynos5410-odroidxu.dts index 75b4150c26d7..f4727a823571 100644 --- a/arch/arm/boot/dts/exynos5410-odroidxu.dts +++ b/arch/arm/boot/dts/exynos5410-odroidxu.dts @@ -637,11 +637,11 @@ }; &usbdrd_dwc3_0 { - dr_mode = "host"; + dr_mode = "peripheral"; }; &usbdrd_dwc3_1 { - dr_mode = "peripheral"; + dr_mode = "host"; }; &usbdrd3_0 { From 3d992fd8f4e0f09c980726308d2f2725587b32d6 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 15 Oct 2020 20:20:42 +0200 Subject: [PATCH 044/799] ARM: dts: exynos: fix USB 3.0 VBUS control and over-current pins on Exynos5410 The VBUS control (PWREN) and over-current pins of USB 3.0 DWC3 controllers are on Exynos5410 regular GPIOs. This is different than for example on Exynos5422 where these are special ETC pins with proper reset values (pulls, functions). Therefore these pins should be configured to enable proper USB 3.0 peripheral and host modes. This also fixes over-current warning: [ 6.024658] usb usb4-port1: over-current condition [ 6.028271] usb usb3-port1: over-current condition Fixes: cb0896562228 ("ARM: dts: exynos: Add USB to Exynos5410") Signed-off-by: Krzysztof Kozlowski Cc: Link: https://lore.kernel.org/r/20201015182044.480562-2-krzk@kernel.org Tested-by: Gabriel Ribba Esteva --- arch/arm/boot/dts/exynos5410-pinctrl.dtsi | 28 +++++++++++++++++++++++ arch/arm/boot/dts/exynos5410.dtsi | 4 ++++ 2 files changed, 32 insertions(+) diff --git a/arch/arm/boot/dts/exynos5410-pinctrl.dtsi b/arch/arm/boot/dts/exynos5410-pinctrl.dtsi index e5d0a2a4f648..d0aa18443a69 100644 --- a/arch/arm/boot/dts/exynos5410-pinctrl.dtsi +++ b/arch/arm/boot/dts/exynos5410-pinctrl.dtsi @@ -560,6 +560,34 @@ interrupt-controller; #interrupt-cells = <2>; }; + + usb3_1_oc: usb3-1-oc { + samsung,pins = "gpk2-4", "gpk2-5"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + usb3_1_vbusctrl: usb3-1-vbusctrl { + samsung,pins = "gpk2-6", "gpk2-7"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + usb3_0_oc: usb3-0-oc { + samsung,pins = "gpk3-0", "gpk3-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + usb3_0_vbusctrl: usb3-0-vbusctrl { + samsung,pins = "gpk3-2", "gpk3-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; }; &pinctrl_2 { diff --git a/arch/arm/boot/dts/exynos5410.dtsi b/arch/arm/boot/dts/exynos5410.dtsi index 60a87684b1af..584ce62361b1 100644 --- a/arch/arm/boot/dts/exynos5410.dtsi +++ b/arch/arm/boot/dts/exynos5410.dtsi @@ -390,6 +390,8 @@ &usbdrd3_0 { clocks = <&clock CLK_USBD300>; clock-names = "usbdrd30"; + pinctrl-names = "default"; + pinctrl-0 = <&usb3_0_oc>, <&usb3_0_vbusctrl>; }; &usbdrd_phy0 { @@ -401,6 +403,8 @@ &usbdrd3_1 { clocks = <&clock CLK_USBD301>; clock-names = "usbdrd30"; + pinctrl-names = "default"; + pinctrl-0 = <&usb3_1_oc>, <&usb3_1_vbusctrl>; }; &usbdrd_dwc3_1 { From bd7e7ff56feea7810df900fb09c9741d259861d9 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 15 Oct 2020 20:20:43 +0200 Subject: [PATCH 045/799] ARM: dts: exynos: fix USB 3.0 pins supply being turned off on Odroid XU On Odroid XU LDO12 and LDO15 supplies the power to USB 3.0 blocks but the GPK GPIO pins are supplied by LDO7 (VDDQ_LCD). LDO7 also supplies GPJ GPIO pins. The Exynos pinctrl driver does not take any supplies, so to have entire GPIO block always available, make the regulator always on. Fixes: 88644b4c750b ("ARM: dts: exynos: Configure PWM, usb3503, PMIC and thermal on Odroid XU board") Signed-off-by: Krzysztof Kozlowski Cc: Link: https://lore.kernel.org/r/20201015182044.480562-3-krzk@kernel.org Tested-by: Gabriel Ribba Esteva --- arch/arm/boot/dts/exynos5410-odroidxu.dts | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/exynos5410-odroidxu.dts b/arch/arm/boot/dts/exynos5410-odroidxu.dts index f4727a823571..bd1d8499a108 100644 --- a/arch/arm/boot/dts/exynos5410-odroidxu.dts +++ b/arch/arm/boot/dts/exynos5410-odroidxu.dts @@ -327,6 +327,8 @@ regulator-name = "vddq_lcd"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; + /* Supplies also GPK and GPJ */ + regulator-always-on; }; ldo8_reg: LDO8 { From 4b6533c04ad97abeb6011f3028005aa62bb7737b Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 15 Oct 2020 20:20:44 +0200 Subject: [PATCH 046/799] ARM: dts: exynos: disable pull up of USB 3.0 over-current on Odroid XU The Odroid XU has external pull ups for USB 3.0 over-current pins, so disable the internal one. Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20201015182044.480562-4-krzk@kernel.org Tested-by: Gabriel Ribba Esteva --- arch/arm/boot/dts/exynos5410-odroidxu.dts | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm/boot/dts/exynos5410-odroidxu.dts b/arch/arm/boot/dts/exynos5410-odroidxu.dts index bd1d8499a108..dd300cea6a20 100644 --- a/arch/arm/boot/dts/exynos5410-odroidxu.dts +++ b/arch/arm/boot/dts/exynos5410-odroidxu.dts @@ -638,6 +638,16 @@ vtmu-supply = <&ldo10_reg>; }; +&usb3_0_oc { + /* External pull up */ + samsung,pin-pud = ; +}; + +&usb3_1_oc { + /* External pull up */ + samsung,pin-pud = ; +}; + &usbdrd_dwc3_0 { dr_mode = "peripheral"; }; From 214a7c874e266f79486f31465077d67957f18010 Mon Sep 17 00:00:00 2001 From: Serge Semin Date: Tue, 20 Oct 2020 14:59:34 +0300 Subject: [PATCH 047/799] ARM: dts: exynos: Correct DWC USB3 compatible string Syonpsys IP cores are supposed to be defined with "snps" vendor-prefix. Use it instead of the deprecated "synopsys" one. Signed-off-by: Serge Semin Link: https://lore.kernel.org/r/20201020115959.2658-5-Sergey.Semin@baikalelectronics.ru Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos5250.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi index bd2d8835dd36..d909ce8cac27 100644 --- a/arch/arm/boot/dts/exynos5250.dtsi +++ b/arch/arm/boot/dts/exynos5250.dtsi @@ -636,7 +636,7 @@ ranges; usbdrd_dwc3: dwc3@12000000 { - compatible = "synopsys,dwc3"; + compatible = "snps,dwc3"; reg = <0x12000000 0x10000>; interrupts = ; phys = <&usbdrd_phy 0>, <&usbdrd_phy 1>; From 3e667f65cdc324be140a99179041a08b33ee61f5 Mon Sep 17 00:00:00 2001 From: Serge Semin Date: Tue, 20 Oct 2020 14:59:49 +0300 Subject: [PATCH 048/799] ARM: dts: exynos: Harmonize DWC USB3 DT nodes name In accordance with the DWC USB3 bindings the corresponding node name is suppose to comply with the Generic USB HCD DT schema, which requires the USB nodes to have the name acceptable by the regexp: "^usb(@.*)?" . Make sure the "snps,dwc3"-compatible nodes are correctly named. Signed-off-by: Serge Semin Link: https://lore.kernel.org/r/20201020115959.2658-20-Sergey.Semin@baikalelectronics.ru Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos5250.dtsi | 2 +- arch/arm/boot/dts/exynos54xx.dtsi | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi index d909ce8cac27..84677332a5a2 100644 --- a/arch/arm/boot/dts/exynos5250.dtsi +++ b/arch/arm/boot/dts/exynos5250.dtsi @@ -635,7 +635,7 @@ #size-cells = <1>; ranges; - usbdrd_dwc3: dwc3@12000000 { + usbdrd_dwc3: usb@12000000 { compatible = "snps,dwc3"; reg = <0x12000000 0x10000>; interrupts = ; diff --git a/arch/arm/boot/dts/exynos54xx.dtsi b/arch/arm/boot/dts/exynos54xx.dtsi index 8aa5117e58ce..339243d19a80 100644 --- a/arch/arm/boot/dts/exynos54xx.dtsi +++ b/arch/arm/boot/dts/exynos54xx.dtsi @@ -148,7 +148,7 @@ #size-cells = <1>; ranges; - usbdrd_dwc3_0: dwc3@12000000 { + usbdrd_dwc3_0: usb@12000000 { compatible = "snps,dwc3"; reg = <0x12000000 0x10000>; interrupts = ; @@ -170,7 +170,7 @@ #size-cells = <1>; ranges; - usbdrd_dwc3_1: dwc3@12400000 { + usbdrd_dwc3_1: usb@12400000 { compatible = "snps,dwc3"; reg = <0x12400000 0x10000>; phys = <&usbdrd_phy1 0>, <&usbdrd_phy1 1>; From e8ea5764bdb144847a44de6113dba8d1ab19179e Mon Sep 17 00:00:00 2001 From: Serge Semin Date: Tue, 20 Oct 2020 14:59:56 +0300 Subject: [PATCH 049/799] arm64: dts: exynos: Harmonize DWC USB3 DT nodes name In accordance with the DWC USB3 bindings the corresponding node name is suppose to comply with the Generic USB HCD DT schema, which requires the USB nodes to have the name acceptable by the regexp: "^usb(@.*)?" . Make sure the "snps,dwc3"-compatible nodes are correctly named. Signed-off-by: Serge Semin Link: https://lore.kernel.org/r/20201020115959.2658-27-Sergey.Semin@baikalelectronics.ru Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/exynos/exynos5433.dtsi | 4 ++-- arch/arm64/boot/dts/exynos/exynos7.dtsi | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi index 8eb4576da8f3..0a886bb6c806 100644 --- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi @@ -1647,7 +1647,7 @@ ranges; status = "disabled"; - usbdrd_dwc3: dwc3@15400000 { + usbdrd_dwc3: usb@15400000 { compatible = "snps,dwc3"; clocks = <&cmu_fsys CLK_SCLK_USBDRD30>, <&cmu_fsys CLK_ACLK_USBDRD30>, @@ -1700,7 +1700,7 @@ ranges; status = "disabled"; - usbhost_dwc3: dwc3@15a00000 { + usbhost_dwc3: usb@15a00000 { compatible = "snps,dwc3"; clocks = <&cmu_fsys CLK_SCLK_USBHOST30>, <&cmu_fsys CLK_ACLK_USBHOST30>, diff --git a/arch/arm64/boot/dts/exynos/exynos7.dtsi b/arch/arm64/boot/dts/exynos/exynos7.dtsi index b9ed6a33e290..48cd3a04fd07 100644 --- a/arch/arm64/boot/dts/exynos/exynos7.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos7.dtsi @@ -654,7 +654,7 @@ #size-cells = <1>; ranges; - dwc3@15400000 { + usb@15400000 { compatible = "snps,dwc3"; reg = <0x15400000 0x10000>; interrupts = ; From b35f80f2e3229ddc59a616ec0f085ef73278c3bf Mon Sep 17 00:00:00 2001 From: Lukasz Luba Date: Wed, 8 Jul 2020 16:34:20 +0100 Subject: [PATCH 050/799] ARM: dts: exynos: Remove interrupts from DMC controller in Exynos5422 The interrupts in Dynamic Memory Controller in Exynos5422 and Odroid XU3-family boards are no longer needed. They have been used in order to workaround some issues in scheduled work in devfreq. Now when the devfreq framework design is improved, remove the interrupt driven approach and rely on devfreq monitoring mechanism with fixed intervals. Reported-by: Willy Wolff Signed-off-by: Lukasz Luba Link: https://lore.kernel.org/r/20200708153420.29484-3-lukasz.luba@arm.com Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos5420.dtsi | 3 --- 1 file changed, 3 deletions(-) diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi index 83580f076a58..23a8fd5c8a6e 100644 --- a/arch/arm/boot/dts/exynos5420.dtsi +++ b/arch/arm/boot/dts/exynos5420.dtsi @@ -240,9 +240,6 @@ dmc: memory-controller@10c20000 { compatible = "samsung,exynos5422-dmc"; reg = <0x10c20000 0x10000>, <0x10c30000 0x10000>; - interrupt-parent = <&combiner>; - interrupts = <16 0>, <16 1>; - interrupt-names = "drex_0", "drex_1"; clocks = <&clock CLK_FOUT_SPLL>, <&clock CLK_MOUT_SCLK_SPLL>, <&clock CLK_FF_DOUT_SPLL2>, From fa769f29f12419db48f4e447e2da9719cc83f3e8 Mon Sep 17 00:00:00 2001 From: Yu-Tung Chang Date: Mon, 26 Oct 2020 15:35:36 +0800 Subject: [PATCH 051/799] ARM: dts: sun8i: add FriendlyArm ZeroPi support The ZeroPi is another fun board developed by FriendlyELEC for makers, hobbyists and fans. ZeroPi key features - Allwinner H3, Quad-core Cortex-A7@1.2GHz - 256MB/512MB DDR3 RAM - microsd slot - 10/100/1000Mbps Ethernet - Debug Serial Port - DC 5V/2A power-supply Signed-off-by: Yu-Tung Chang Signed-off-by: Maxime Ripard Link: https://lore.kernel.org/r/20201026073536.13617-2-mtwget@gmail.com --- .../devicetree/bindings/arm/sunxi.yaml | 5 ++ arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/sun8i-h3-zeropi.dts | 85 +++++++++++++++++++ 3 files changed, 91 insertions(+) create mode 100644 arch/arm/boot/dts/sun8i-h3-zeropi.dts diff --git a/Documentation/devicetree/bindings/arm/sunxi.yaml b/Documentation/devicetree/bindings/arm/sunxi.yaml index afa00268c7db..0f23133672a3 100644 --- a/Documentation/devicetree/bindings/arm/sunxi.yaml +++ b/Documentation/devicetree/bindings/arm/sunxi.yaml @@ -251,6 +251,11 @@ properties: - const: friendlyarm,nanopi-neo-plus2 - const: allwinner,sun50i-h5 + - description: FriendlyARM ZeroPi + items: + - const: friendlyarm,zeropi + - const: allwinner,sun8i-h3 + - description: Gemei G9 Tablet items: - const: gemei,g9 diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index ce66ffd5a1bb..4f0adfead547 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1201,6 +1201,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \ sun8i-h3-orangepi-plus2e.dtb \ sun8i-h3-orangepi-zero-plus2.dtb \ sun8i-h3-rervision-dvk.dtb \ + sun8i-h3-zeropi.dtb \ sun8i-h3-emlid-neutis-n5h3-devboard.dtb \ sun8i-r16-bananapi-m2m.dtb \ sun8i-r16-nintendo-nes-classic.dtb \ diff --git a/arch/arm/boot/dts/sun8i-h3-zeropi.dts b/arch/arm/boot/dts/sun8i-h3-zeropi.dts new file mode 100644 index 000000000000..7d3e7323b661 --- /dev/null +++ b/arch/arm/boot/dts/sun8i-h3-zeropi.dts @@ -0,0 +1,85 @@ +/* + * Copyright (C) 2020 Yu-Tung Chang + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "sun8i-h3-nanopi.dtsi" + +/ { + model = "FriendlyARM ZeroPi"; + compatible = "friendlyarm,zeropi", "allwinner,sun8i-h3"; + + aliases { + ethernet0 = &emac; + }; + + reg_gmac_3v3: gmac-3v3 { + compatible = "regulator-fixed"; + regulator-name = "gmac-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <100000>; + enable-active-high; + gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>; /* PD6 */ + }; +}; + +&external_mdio { + ext_rgmii_phy: ethernet-phy@7 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <7>; + }; +}; + +&emac { + pinctrl-names = "default"; + pinctrl-0 = <&emac_rgmii_pins>; + phy-supply = <®_gmac_3v3>; + phy-handle = <&ext_rgmii_phy>; + phy-mode = "rgmii-id"; + + allwinner,leds-active-low; + status = "okay"; +}; + +&usb_otg { + status = "okay"; + dr_mode = "host"; +}; From 37dd4b7779424cc7e26791c24e9918c52e01e1ee Mon Sep 17 00:00:00 2001 From: Douglas Anderson Date: Mon, 21 Sep 2020 14:27:16 -0700 Subject: [PATCH 052/799] arm64: dts: qcom: sc7180: Provide pinconf for SPI to use GPIO for CS When the chip select line is controlled by the QUP, changing CS is a time consuming operation. We have to send a command over to the geni and wait for it to Ack us every time we want to change (both making it high and low). To send this command we have to make a choice in software when we want to control the chip select, we have to either: A) Wait for the Ack via interrupt which slows down all SPI transfers (and incurrs extra processing associated with interrupts). B) Sit in a loop and poll, waiting for the Ack. Neither A) nor B) is a great option. We can avoid all of this by realizing that, at least on some boards, there is no advantage of considering this line to be a geni line. While it's true that geni _can_ control the line, it's also true that the line can be a GPIO and there is no downside of viewing it that way. Setting a GPIO is a simple MMIO operation. This patch provides definitions so a board can easily select the GPIO mode. NOTE: apparently, it's possible to run the geni in "GSI" mode. In GSI the SPI port is allowed to be controlled by more than one user (like firmware and Linux) and also the port can operate sequences of operations in one go. In GSI mode it _would_ be invalid to look at the chip select as a GPIO because that would prevent other users from using it. In theory GSI mode would also avoid some overhead by allowing us to sequence the chip select better. However, I'll argue GSI is not relevant for all boards (and certainly not any boards supported by mainline today). Why? - Apparently to run a SPI chip in GSI mode you need to initialize it (in the bootloader) with a different firmware and then it will always run in GSI mode. Since there is no support for GSI mode in the current Linux driver, it must be that existing boards don't have firmware that's doing that. Note that the kernel device tree describes hardware but also firmware, so it is legitimate to make the assumption that we don't have GSI firmware in a given dts file. - Some boards with sc7180 have SPI connected to the Chrome OS EC or security chip (Cr50). The protocols for talking to cros_ec and cr50 are extremely complex. Both drivers in Linux fully lock the bus across several distinct SPI transfers. While I am not an expert on GSI mode it feels highly unlikely to me that we'd ever be able to enable GSI mode for these devices. From a testing perspective, running "flashrom -p ec -r /tmp/foo.bin" in a loop after this patch shows almost no reduction in time, but the number of interrupts per command goes from 32357 down to 30611 (about a 5% reduction). Signed-off-by: Douglas Anderson Reviewed-by: Stephen Boyd Reviewed-by: Akash Asthana Link: https://lore.kernel.org/r/20200921142655.v3.1.I997a428f58ef9d48b37a27a028360f34e66c00ec@changeid Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc7180.dtsi | 104 +++++++++++++++++++++++++++ 1 file changed, 104 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index a02776ce77a1..6fcffd588a7d 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -1595,6 +1595,19 @@ }; }; + qup_spi0_cs_gpio: qup-spi0-cs-gpio { + pinmux { + pins = "gpio34", "gpio35", + "gpio36"; + function = "qup00"; + }; + + pinmux-cs { + pins = "gpio37"; + function = "gpio"; + }; + }; + qup_spi1_default: qup-spi1-default { pinmux { pins = "gpio0", "gpio1", @@ -1603,6 +1616,19 @@ }; }; + qup_spi1_cs_gpio: qup-spi1-cs-gpio { + pinmux { + pins = "gpio0", "gpio1", + "gpio2"; + function = "qup01"; + }; + + pinmux-cs { + pins = "gpio3"; + function = "gpio"; + }; + }; + qup_spi3_default: qup-spi3-default { pinmux { pins = "gpio38", "gpio39", @@ -1611,6 +1637,19 @@ }; }; + qup_spi3_cs_gpio: qup-spi3-cs-gpio { + pinmux { + pins = "gpio38", "gpio39", + "gpio40"; + function = "qup03"; + }; + + pinmux-cs { + pins = "gpio41"; + function = "gpio"; + }; + }; + qup_spi5_default: qup-spi5-default { pinmux { pins = "gpio25", "gpio26", @@ -1619,6 +1658,19 @@ }; }; + qup_spi5_cs_gpio: qup-spi5-cs-gpio { + pinmux { + pins = "gpio25", "gpio26", + "gpio27"; + function = "qup05"; + }; + + pinmux-cs { + pins = "gpio28"; + function = "gpio"; + }; + }; + qup_spi6_default: qup-spi6-default { pinmux { pins = "gpio59", "gpio60", @@ -1627,6 +1679,19 @@ }; }; + qup_spi6_cs_gpio: qup-spi6-cs-gpio { + pinmux { + pins = "gpio59", "gpio60", + "gpio61"; + function = "qup10"; + }; + + pinmux-cs { + pins = "gpio62"; + function = "gpio"; + }; + }; + qup_spi8_default: qup-spi8-default { pinmux { pins = "gpio42", "gpio43", @@ -1635,6 +1700,19 @@ }; }; + qup_spi8_cs_gpio: qup-spi8-cs-gpio { + pinmux { + pins = "gpio42", "gpio43", + "gpio44"; + function = "qup12"; + }; + + pinmux-cs { + pins = "gpio45"; + function = "gpio"; + }; + }; + qup_spi10_default: qup-spi10-default { pinmux { pins = "gpio86", "gpio87", @@ -1643,6 +1721,19 @@ }; }; + qup_spi10_cs_gpio: qup-spi10-cs-gpio { + pinmux { + pins = "gpio86", "gpio87", + "gpio88"; + function = "qup14"; + }; + + pinmux-cs { + pins = "gpio89"; + function = "gpio"; + }; + }; + qup_spi11_default: qup-spi11-default { pinmux { pins = "gpio53", "gpio54", @@ -1651,6 +1742,19 @@ }; }; + qup_spi11_cs_gpio: qup-spi11-cs-gpio { + pinmux { + pins = "gpio53", "gpio54", + "gpio55"; + function = "qup15"; + }; + + pinmux-cs { + pins = "gpio56"; + function = "gpio"; + }; + }; + qup_uart0_default: qup-uart0-default { pinmux { pins = "gpio34", "gpio35", From cfbb97fde6941f3ecf19fb303648d4e09be28f42 Mon Sep 17 00:00:00 2001 From: Douglas Anderson Date: Mon, 21 Sep 2020 14:27:17 -0700 Subject: [PATCH 053/799] arm64: dts: qcom: Switch sc7180-trogdor to control SPI CS via GPIO As talked about in the patch ("arm64: dts: qcom: sc7180: Provide pinconf for SPI to use GPIO for CS"), on some boards it makes much more sense (and is much more efficient) to think of the SPI Chip Select as a GPIO. Trogdor is one such board where the SPI parts don't run in GSI mode and we do a lot of SPI traffic. Signed-off-by: Douglas Anderson Reviewed-by: Stephen Boyd Reviewed-by: Akash Asthana Link: https://lore.kernel.org/r/20200921142655.v3.2.I3c57d8b6d83d5bdad73a413eea1e249a98d11973@changeid Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi | 19 ++++++++++++++++--- 1 file changed, 16 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi index bf875589d364..0759896a0df5 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi @@ -776,7 +776,20 @@ hp_i2c: &i2c9 { cd-gpios = <&tlmm 69 GPIO_ACTIVE_LOW>; }; +&spi0 { + pinctrl-0 = <&qup_spi0_cs_gpio>; + cs-gpios = <&tlmm 37 GPIO_ACTIVE_LOW>; +}; + +&spi6 { + pinctrl-0 = <&qup_spi6_cs_gpio>; + cs-gpios = <&tlmm 62 GPIO_ACTIVE_LOW>; +}; + ap_spi_fp: &spi10 { + pinctrl-0 = <&qup_spi10_cs_gpio>; + cs-gpios = <&tlmm 89 GPIO_ACTIVE_LOW>; + cros_ec_fp: ec@0 { compatible = "google,cros-ec-spi"; reg = <0>; @@ -937,7 +950,7 @@ ap_spi_fp: &spi10 { }; }; -&qup_spi0_default { +&qup_spi0_cs_gpio { pinconf { pins = "gpio34", "gpio35", "gpio36", "gpio37"; drive-strength = <2>; @@ -945,7 +958,7 @@ ap_spi_fp: &spi10 { }; }; -&qup_spi6_default { +&qup_spi6_cs_gpio { pinconf { pins = "gpio59", "gpio60", "gpio61", "gpio62"; drive-strength = <2>; @@ -953,7 +966,7 @@ ap_spi_fp: &spi10 { }; }; -&qup_spi10_default { +&qup_spi10_cs_gpio { pinconf { pins = "gpio86", "gpio87", "gpio88", "gpio89"; drive-strength = <2>; From 950d46f7c18a928e17f866a9ce5bf9c1132e5f33 Mon Sep 17 00:00:00 2001 From: Marek Szyprowski Date: Fri, 11 Sep 2020 14:22:20 +0200 Subject: [PATCH 054/799] ARM: dts: exynos: Remove 'opp-shared' from Exynos3 bus OPP-tables Commits 1019fe2c7280 ("ARM: dts: exynos: Adjust bus related OPPs to the values correct for Exynos5422 Odroids") and 9ff416cf45a0 ("ARM: dts: exynos: Disable frequency scaling for FSYS bus on Odroid XU3 family") revealed that 'opp-shared' property for the Exynos bus OPPs was used incorrectly, what had the side-effect of disabling frequency scaling for the second and latter buses sharing given OPP-table. Fix this by removing bogus 'opp-shared' properties from Exynos3 bus OPP-tables. This restores frequency scaling for the following buses: RightBus, LCD0, FSYS and MFC. Signed-off-by: Marek Szyprowski Link: https://lore.kernel.org/r/20200911122220.13698-1-m.szyprowski@samsung.com Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos3250.dtsi | 5 ----- 1 file changed, 5 deletions(-) diff --git a/arch/arm/boot/dts/exynos3250.dtsi b/arch/arm/boot/dts/exynos3250.dtsi index a1e93fb7f694..75ed82600ec8 100644 --- a/arch/arm/boot/dts/exynos3250.dtsi +++ b/arch/arm/boot/dts/exynos3250.dtsi @@ -775,7 +775,6 @@ bus_dmc_opp_table: opp_table1 { compatible = "operating-points-v2"; - opp-shared; opp-50000000 { opp-hz = /bits/ 64 <50000000>; @@ -865,7 +864,6 @@ bus_leftbus_opp_table: opp_table2 { compatible = "operating-points-v2"; - opp-shared; opp-50000000 { opp-hz = /bits/ 64 <50000000>; @@ -891,7 +889,6 @@ bus_mcuisp_opp_table: opp_table3 { compatible = "operating-points-v2"; - opp-shared; opp-50000000 { opp-hz = /bits/ 64 <50000000>; @@ -912,7 +909,6 @@ bus_isp_opp_table: opp_table4 { compatible = "operating-points-v2"; - opp-shared; opp-50000000 { opp-hz = /bits/ 64 <50000000>; @@ -933,7 +929,6 @@ bus_peril_opp_table: opp_table5 { compatible = "operating-points-v2"; - opp-shared; opp-50000000 { opp-hz = /bits/ 64 <50000000>; From a23beead41a18c3be3ca409cb52f35bc02e601b9 Mon Sep 17 00:00:00 2001 From: Marek Szyprowski Date: Fri, 11 Sep 2020 14:22:36 +0200 Subject: [PATCH 055/799] ARM: dts: exynos: Remove 'opp-shared' from Exynos4412 bus OPP-tables Commits 1019fe2c7280 ("ARM: dts: exynos: Adjust bus related OPPs to the values correct for Exynos5422 Odroids") and 9ff416cf45a0 ("ARM: dts: exynos: Disable frequency scaling for FSYS bus on Odroid XU3 family") revealed that 'opp-shared' property for the Exynos bus OPPs was used incorrectly, what had the side-effect of disabling frequency scaling for the second and latter buses sharing given OPP-table. Fix this by removing bogus 'opp-shared' properties from Exynos4412 bus OPP-tables. This restores frequency scaling for the following buses: C2C, RightBus, and MFC. Signed-off-by: Marek Szyprowski Link: https://lore.kernel.org/r/20200911122236.16805-1-m.szyprowski@samsung.com Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos4412.dtsi | 6 ------ 1 file changed, 6 deletions(-) diff --git a/arch/arm/boot/dts/exynos4412.dtsi b/arch/arm/boot/dts/exynos4412.dtsi index e76881dc0014..fa8e8d6bc4d5 100644 --- a/arch/arm/boot/dts/exynos4412.dtsi +++ b/arch/arm/boot/dts/exynos4412.dtsi @@ -404,7 +404,6 @@ bus_dmc_opp_table: opp-table1 { compatible = "operating-points-v2"; - opp-shared; opp-100000000 { opp-hz = /bits/ 64 <100000000>; @@ -431,7 +430,6 @@ bus_acp_opp_table: opp-table2 { compatible = "operating-points-v2"; - opp-shared; opp-100000000 { opp-hz = /bits/ 64 <100000000>; @@ -497,7 +495,6 @@ bus_leftbus_opp_table: opp-table3 { compatible = "operating-points-v2"; - opp-shared; opp-100000000 { opp-hz = /bits/ 64 <100000000>; @@ -520,7 +517,6 @@ bus_display_opp_table: opp-table4 { compatible = "operating-points-v2"; - opp-shared; opp-160000000 { opp-hz = /bits/ 64 <160000000>; @@ -532,7 +528,6 @@ bus_fsys_opp_table: opp-table5 { compatible = "operating-points-v2"; - opp-shared; opp-100000000 { opp-hz = /bits/ 64 <100000000>; @@ -544,7 +539,6 @@ bus_peri_opp_table: opp-table6 { compatible = "operating-points-v2"; - opp-shared; opp-50000000 { opp-hz = /bits/ 64 <50000000>; From 886f82ce9f1f4559c139fdb2d79d158999ca38cd Mon Sep 17 00:00:00 2001 From: Billy Tsai Date: Mon, 12 Oct 2020 11:31:48 +0800 Subject: [PATCH 056/799] ARM: dts: aspeed-g6: Fix the GPIO memory size The GPIO controller is a GPIO controller followed by some SGPIO controllers, which are a different type of device with their own binding and drivers. Make the gpio node cover the only conventional GPIO controller. Fixes: 8dbcb5b709b9 ("ARM: dts: aspeed-g6: Add gpio devices") Signed-off-by: Billy Tsai Reviewed-by: Andrew Jeffery Reviewed-by: Joel Stanley Link: https://lore.kernel.org/r/20201012033150.21056-2-billy_tsai@aspeedtech.com Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-g6.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/aspeed-g6.dtsi b/arch/arm/boot/dts/aspeed-g6.dtsi index b58220a49cbd..bf97aaad7be9 100644 --- a/arch/arm/boot/dts/aspeed-g6.dtsi +++ b/arch/arm/boot/dts/aspeed-g6.dtsi @@ -357,7 +357,7 @@ #gpio-cells = <2>; gpio-controller; compatible = "aspeed,ast2600-gpio"; - reg = <0x1e780000 0x800>; + reg = <0x1e780000 0x400>; interrupts = ; gpio-ranges = <&pinctrl 0 0 208>; ngpios = <208>; From e3b123542cdc324d85a061356fbb6bb849bcb941 Mon Sep 17 00:00:00 2001 From: Konstantin Aladyshev Date: Tue, 27 Oct 2020 15:37:20 +0300 Subject: [PATCH 057/799] ARM: dts: aspeed: amd-ethanolx: Update KCS nodes to use v2 binding KCS nodes compatible property was changed in the dtsi to use v2 binding before ethanolx was merged, making the ethanolx device tree incorrect. Update it to use the new binding so the driver loads. Fixes: fa4c8ec6feaa ("ARM: dts: aspeed: Change KCS nodes to v2 binding") Signed-off-by: Konstantin Aladyshev Reviewed-by: Joel Stanley Link: https://lore.kernel.org/r/20201027123722.2935-1-aladyshev22@gmail.com Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-bmc-amd-ethanolx.dts | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/aspeed-bmc-amd-ethanolx.dts b/arch/arm/boot/dts/aspeed-bmc-amd-ethanolx.dts index 60ba86f3e5bc..89ddc3847222 100644 --- a/arch/arm/boot/dts/aspeed-bmc-amd-ethanolx.dts +++ b/arch/arm/boot/dts/aspeed-bmc-amd-ethanolx.dts @@ -139,17 +139,17 @@ &kcs1 { status = "okay"; - kcs_addr = <0x60>; + aspeed,lpc-io-reg = <0x60>; }; &kcs2 { status = "okay"; - kcs_addr = <0x62>; + aspeed,lpc-io-reg = <0x62>; }; &kcs4 { status = "okay"; - kcs_addr = <0x97DE>; + aspeed,lpc-io-reg = <0x97DE>; }; &lpc_snoop { From 9e1cc9679776f5b9e42481d392b1550753ebd084 Mon Sep 17 00:00:00 2001 From: Joel Stanley Date: Tue, 22 Sep 2020 16:12:34 +0930 Subject: [PATCH 058/799] ARM: dts: aspeed: s2600wf: Fix VGA memory region location The VGA memory region is always from the top of RAM. On this board, that is 0x80000000 + 0x20000000 - 0x01000000 = 0x9f000000. This was not an issue in practice as the region is "reserved" by the vendor's u-boot reducing the amount of available RAM, and the only user is the host VGA device poking at RAM over PCIe. That is, nothing from the ARM touches it. It is worth fixing as developers copy existing device trees when building their machines, and the XDMA driver does use the memory region from the ARM side. Fixes: c4043ecac34a ("ARM: dts: aspeed: Add S2600WF BMC Machine") Reported-by: John Wang Link: https://lore.kernel.org/r/20200922064234.163799-1-joel@jms.id.au Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-bmc-intel-s2600wf.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/aspeed-bmc-intel-s2600wf.dts b/arch/arm/boot/dts/aspeed-bmc-intel-s2600wf.dts index 1deb30ec912c..6e9baf3bba53 100644 --- a/arch/arm/boot/dts/aspeed-bmc-intel-s2600wf.dts +++ b/arch/arm/boot/dts/aspeed-bmc-intel-s2600wf.dts @@ -22,9 +22,9 @@ #size-cells = <1>; ranges; - vga_memory: framebuffer@7f000000 { + vga_memory: framebuffer@9f000000 { no-map; - reg = <0x7f000000 0x01000000>; + reg = <0x9f000000 0x01000000>; /* 16M */ }; }; From e81059a5e4d8a4227b58a2bc7a5041d545a587a3 Mon Sep 17 00:00:00 2001 From: John Wang Date: Tue, 29 Sep 2020 14:39:54 +0800 Subject: [PATCH 059/799] ARM: dts: Add 64MiB OpenBMC flash layout This is an alternate layout used by OpenBMC systems The division of space is as follows: u-boot + env: 0.5MB kernel/FIT: 5MB rofs: 42.5MB rwfs: 16MB Signed-off-by: John Wang Link: https://lore.kernel.org/r/20200929063955.1206-1-wangzhiqiang.bj@bytedance.com Signed-off-by: Joel Stanley --- .../arm/boot/dts/openbmc-flash-layout-64.dtsi | 35 +++++++++++++++++++ 1 file changed, 35 insertions(+) create mode 100644 arch/arm/boot/dts/openbmc-flash-layout-64.dtsi diff --git a/arch/arm/boot/dts/openbmc-flash-layout-64.dtsi b/arch/arm/boot/dts/openbmc-flash-layout-64.dtsi new file mode 100644 index 000000000000..c8e0409d889e --- /dev/null +++ b/arch/arm/boot/dts/openbmc-flash-layout-64.dtsi @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2020 Bytedance. + */ + +partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + u-boot@0 { + reg = <0x0 0x60000>; // 384KB + label = "u-boot"; + }; + + u-boot-env@e0000 { + reg = <0x60000 0x20000>; // 128KB + label = "u-boot-env"; + }; + + kernel@100000 { + reg = <0x80000 0x500000>; // 5MB + label = "kernel"; + }; + + rofs@a00000 { + reg = <0x580000 0x2a80000>; // 42.5MB + label = "rofs"; + }; + + rwfs@6000000 { + reg = <0x3000000 0x1000000>; // 16MB + label = "rwfs"; + }; +}; From b2826bdf910dccee07bede625c2005154bb6f698 Mon Sep 17 00:00:00 2001 From: Lotus Xu Date: Tue, 29 Sep 2020 14:39:55 +0800 Subject: [PATCH 060/799] ARM: dts: aspeed: Add Bytedance g220a BMC machine The g220a is a server platform with an ASPEED AST2500 BMC. Signed-off-by: Lotus Xu Signed-off-by: John Wang Reviewed-by: Joel Stanley Link: https://lore.kernel.org/r/20200929063955.1206-2-wangzhiqiang.bj@bytedance.com Signed-off-by: Joel Stanley --- arch/arm/boot/dts/Makefile | 1 + .../boot/dts/aspeed-bmc-bytedance-g220a.dts | 924 ++++++++++++++++++ 2 files changed, 925 insertions(+) create mode 100644 arch/arm/boot/dts/aspeed-bmc-bytedance-g220a.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index ce66ffd5a1bb..21477ef5c5c9 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1381,6 +1381,7 @@ dtb-$(CONFIG_ARCH_ASPEED) += \ aspeed-bmc-amd-ethanolx.dtb \ aspeed-bmc-arm-centriq2400-rep.dtb \ aspeed-bmc-arm-stardragon4800-rep2.dtb \ + aspeed-bmc-bytedance-g220a.dtb \ aspeed-bmc-facebook-cmm.dtb \ aspeed-bmc-facebook-minipack.dtb \ aspeed-bmc-facebook-tiogapass.dtb \ diff --git a/arch/arm/boot/dts/aspeed-bmc-bytedance-g220a.dts b/arch/arm/boot/dts/aspeed-bmc-bytedance-g220a.dts new file mode 100644 index 000000000000..0aeec7017e43 --- /dev/null +++ b/arch/arm/boot/dts/aspeed-bmc-bytedance-g220a.dts @@ -0,0 +1,924 @@ +// SPDX-License-Identifier: GPL-2.0+ +// Copyright (C) 2020 Bytedance. +/dts-v1/; + +#include "aspeed-g5.dtsi" +#include +#include +#include + +/ { + model = "Bytedance G220A BMC"; + compatible = "bytedance,g220a-bmc", "aspeed,ast2500"; + + aliases { + serial4 = &uart5; + i2c14 = &channel_3_0; + i2c15 = &channel_3_1; + i2c16 = &channel_3_2; + i2c17 = &channel_3_3; + i2c18 = &channel_6_0; + i2c19 = &channel_6_1; + i2c20 = &channel_6_2; + i2c21 = &channel_6_3; + i2c22 = &channel_6_4; + i2c23 = &channel_6_5; + i2c24 = &channel_6_6; + i2c25 = &channel_6_7; + i2c26 = &channel_6_8; + i2c27 = &channel_6_9; + i2c28 = &channel_6_10; + i2c29 = &channel_6_11; + i2c30 = &channel_6_12; + i2c31 = &channel_6_13; + i2c32 = &channel_6_14; + i2c33 = &channel_6_15; + i2c34 = &channel_6_16; + i2c35 = &channel_6_17; + i2c36 = &channel_6_18; + i2c37 = &channel_6_19; + i2c38 = &channel_6_20; + i2c39 = &channel_6_21; + i2c40 = &channel_6_22; + i2c41 = &channel_6_23; + i2c42 = &channel_6_24; + i2c43 = &channel_6_25; + i2c44 = &channel_10_0; + i2c45 = &channel_10_1; + i2c46 = &channel_10_2; + i2c47 = &channel_10_3; + i2c48 = &channel_10_4; + i2c49 = &channel_10_5; + i2c50 = &channel_10_6; + i2c51 = &channel_10_7; + }; + + chosen { + stdout-path = &uart5; + bootargs = "console=ttyS4,115200 earlyprintk"; + }; + + memory@80000000 { + reg = <0x80000000 0x40000000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + vga_memory: framebuffer@bc000000 { + no-map; + reg = <0xbc000000 0x04000000>; /* 64M */ + }; + + video_engine_memory: jpegbuffer { + size = <0x02000000>; /* 32M */ + alignment = <0x01000000>; + compatible = "shared-dma-pool"; + reusable; + }; + }; + + iio-hwmon { + compatible = "iio-hwmon"; + io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>, + <&adc 4>, <&adc 5>, <&adc 6>, <&adc 7>, + <&adc 8>, <&adc 9>, <&adc 10>, <&adc 11>, + <&adc 12>, <&adc 13>, <&adc 14>, <&adc 15>; + }; + + leds { + compatible = "gpio-leds"; + bmc_alive { + label = "bmc_alive"; + gpios = <&gpio ASPEED_GPIO(B, 0) GPIO_ACTIVE_LOW>; + linux,default-trigger = "timer"; + led-pattern = <1000 1000>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + burn-in-signal { + label = "burn-in"; + gpios = <&gpio ASPEED_GPIO(R, 5) GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + gpio-keys-polled { + compatible = "gpio-keys-polled"; + poll-interval = <1000>; + + rear-riser1-presence { + label = "rear-riser1-presence"; + gpios = <&pca0 1 GPIO_ACTIVE_LOW>; + linux,code = <1>; + }; + + alrt-pvddq-cpu0 { + label = "alrt-pvddq-cpu0"; + gpios = <&pca0 8 GPIO_ACTIVE_LOW>; + linux,code = <2>; + }; + + rear-riser0-presence { + label = "rear-riser0-presence"; + gpios = <&pca0 9 GPIO_ACTIVE_LOW>; + linux,code = <3>; + }; + + fault-pvddq-cpu0 { + label = "fault-pvddq-cpu0"; + gpios = <&pca0 10 GPIO_ACTIVE_LOW>; + linux,code = <4>; + }; + + alrt-pvddq-cpu1 { + label = "alrt-pvddq-cpu1"; + gpios = <&pca0 11 GPIO_ACTIVE_LOW>; + linux,code = <5>; + }; + + fault-pvddq-cpu1 { + label = "alrt-pvddq-cpu1"; + gpios = <&pca0 12 GPIO_ACTIVE_LOW>; + linux,code = <6>; + }; + + fault-pvccin-cpu1 { + label = "fault-pvccin-cpuq"; + gpios = <&pca0 13 GPIO_ACTIVE_LOW>; + linux,code = <7>; + }; + + bmc-rom0-wp { + label = "bmc-rom0-wp"; + gpios = <&pca1 0 GPIO_ACTIVE_LOW>; + linux,code = <8>; + }; + + bmc-rom1-wp { + label = "bmc-rom1-wp"; + gpios = <&pca1 1 GPIO_ACTIVE_LOW>; + linux,code = <9>; + }; + + fan0-presence { + label = "fan0-presence"; + gpios = <&pca1 2 GPIO_ACTIVE_LOW>; + linux,code = <10>; + }; + + fan1-presence { + label = "fan1-presence"; + gpios = <&pca1 3 GPIO_ACTIVE_LOW>; + linux,code = <11>; + }; + + fan2-presence { + label = "fan2-presence"; + gpios = <&pca1 4 GPIO_ACTIVE_LOW>; + linux,code = <12>; + }; + + fan3-presence { + label = "fan3-presence"; + gpios = <&pca1 5 GPIO_ACTIVE_LOW>; + linux,code = <13>; + }; + + fan4-presence { + label = "fan4-presence"; + gpios = <&pca1 6 GPIO_ACTIVE_LOW>; + linux,code = <14>; + }; + + fan5-presence { + label = "fan5-presence"; + gpios = <&pca1 7 GPIO_ACTIVE_LOW>; + linux,code = <15>; + }; + + front-bp1-presence { + label = "front-bp1-presence"; + gpios = <&pca1 8 GPIO_ACTIVE_LOW>; + linux,code = <16>; + }; + + rear-bp-presence { + label = "rear-bp-presence"; + gpios = <&pca1 9 GPIO_ACTIVE_LOW>; + linux,code = <17>; + }; + + fault-pvccin-cpu0 { + label = "fault-pvccin-cpu0"; + gpios = <&pca1 10 GPIO_ACTIVE_LOW>; + linux,code = <18>; + }; + + alrt-p1v05-pvcc { + label = "alrt-p1v05-pvcc1"; + gpios = <&pca1 11 GPIO_ACTIVE_LOW>; + linux,code = <19>; + }; + + fault-p1v05-pvccio { + label = "alrt-p1v05-pvcc1"; + gpios = <&pca1 12 GPIO_ACTIVE_LOW>; + linux,code = <20>; + }; + + alrt-p1v8-pvccio { + label = "alrt-p1v8-pvccio"; + gpios = <&pca1 13 GPIO_ACTIVE_LOW>; + linux,code = <21>; + }; + + fault-p1v8-pvccio { + label = "fault-p1v8-pvccio"; + gpios = <&pca1 14 GPIO_ACTIVE_LOW>; + linux,code = <22>; + }; + + front-bp0-presence { + label = "front-bp0-presence"; + gpios = <&pca1 15 GPIO_ACTIVE_LOW>; + linux,code = <23>; + }; + }; +}; + +&fmc { + status = "okay"; + flash@0 { + status = "okay"; + label = "bmc"; + m25p,fast-read; + spi-max-frequency = <50000000>; +#include "openbmc-flash-layout-64.dtsi" + }; +}; + +&spi1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi1_default>; + flash@0 { + status = "okay"; + m25p,fast-read; + label = "bios"; + spi-max-frequency = <100000000>; + }; +}; + +&adc { + status = "okay"; +}; + +&gpio { + status = "okay"; + gpio-line-names = + /*A0-A7*/ "SMRST_OCP_N","MAC2_LINK","BMC_CPLD_SMB_RST_R_N","BMC_CPLD_GPIO0", + "","","","", + /*B0-B7*/ "BMC_INIT_R_OK","FM_BOARD_REV_ID2","FM_PROJECT_ID7","FAULT_P12V_STBY_N", + "","CPU0_PROCHOT_LVT3_N","","BIOS_LOAD_DEFAULT_R_N", + /*C0-C7*/ "","","","","","","","", + /*D0-D7*/ "","","","","","","","", + /*E0-E7*/ "FM_PROJECT_ID0","FM_PROJECT_ID1","FM_PROJECT_ID2","FM_PROJECT_ID3", + "FM_PROJECT_ID4","FM_PROJECT_ID5","","", + /*F0-F7*/ "PSU0_PRSNT_N","PSU1_PRSNT_N","","FAULT_P12V_NVME_N", + "BIOS_DEBUG_MODE_R_N","DISABLE_CPU_DDR_R_SPD","COOLING_STRATEGY", + "PCH_GLB_RST_N", + /*G0-G7*/ "P12V_PMBUS_ALERT_N","CPLD_ALERT_N","BMC_RELOAD_N", + "P12V_PVDDQ_PMBUS_ALERT_N","BMC_JTAG_TCK_MUX_R_SEL","","NMI_OUT", + "NMI_BUTTON", + /*H0-H7*/ "BMC_CPLD_JTAG_TDI","BMC_CPLD_JTAG_TDO","BMC_CPLD_JTAG_TCK", + "BMC_CPLD_JTAG_TMS","FM_PROJECT_ID6","FM_BOARD_REV_ID0", + "PCA9546_U70_RST_N","IRQ_SML0_ALERT_N", + /*I0-I7*/ "FAULT_FRONT_RISER_P12V_N","FAULT_OCP_P12V_N","FM_BMC_PCH_SCI_R_N", + "","","","","", + /*J0-J7*/ "FM_CPU0_SKTOCC_N","FM_CPU1_SKTOCC_N","FM_CPU1_DISABLE_COD_N", + "","","","","", + /*K0-K7*/ "","","","","","","","", + /*L0-L7*/ "P12V_FAULT_N","PWRGD_P12V_PCIE_RISER","","LEAKAGE_DETECT_INPUT_N", + "","IRQ_SML1_PMBUS_ALERT_N","","", + /*M0-M7*/ "","","","","","","","", + /*N0-N7*/ "","","","","","","","", + /*O0-O7*/ "","","","","","","","", + /*P0-P7*/ "","","","","","","","", + /*Q0-Q7*/ "","","","","","","FM_PCH_THERMTRIP_N","INTRUDER_N", + /*R0-R7*/ "","PVCCIN_CPU1_SMBALERT_N","BMC_PREQ_R_N","FAULT_P12V_PCIE_RISER_N", + "ALT_P12V_PCIE_RISER_N","BURN_BOARD_N","PVCCIN_CPU0_SMBALERT_N","", + /*S0-S7*/ "BMC_PRDY_N","SIO_POWER_GOOD","FM_BMC_PWR_DEBUG_R_N", + "FM_BMC_XDP_DEBUG_EN","","","","", + /*T0-T7*/ "","","","","","","","", + /*U0-U7*/ "","","","","","","","", + /*V0-V7*/ "","","","","","","","", + /*W0-W7*/ "","","","","","","","", + /*X0-X7*/ "","","","","","","","", + /*Y0-Y7*/ "","PWRGD_PSU0_PWROK","CPU1_PROCHOT_LVT3_N","IRQ_BMC_PCH_SMI_LPC_N", + "","","","", + /*Z0-Z7*/ "XDP_PRSNT_N","BMC_XDP_SYS_PWROK","BMC_XDP_JTAG_SEL", + "PCH_BMC_SMI_ACTIVE_R_N","","","","", + /*AA0-AA7*/ "PWRGD_P12V_STBY_OCP","PS_PWROK","RST_PLTRST_BMC_R_N","HDA_SDO_R", + "FM_SLPS4_R_N","PWRGD_PSU1_PWROK","POWER_BUTTON","POWER_OUT", + /*AB0-AB7*/ "","RESET_OUT","SPI_BIOS_MODE_SELECT","POST_COMPLETE","","","","", + /*AC0-AC7*/ "","","","","","","","CPLD_PLTRST_B_N"; +}; + +&kcs3 { + aspeed,lpc-io-reg = <0xCA2>; + status = "okay"; +}; + +&kcs4 { + aspeed,lpc-io-reg = <0xCA4>; + status = "okay"; +}; + +&lpc_snoop { + snoop-ports = <0x80>; + status = "okay"; +}; + +&uart1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_txd1_default + &pinctrl_rxd1_default + &pinctrl_nrts1_default + &pinctrl_ndtr1_default + &pinctrl_ndsr1_default + &pinctrl_ncts1_default + &pinctrl_ndcd1_default + &pinctrl_nri1_default>; +}; + +&uart2 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_txd2_default + &pinctrl_rxd2_default + &pinctrl_nrts2_default + &pinctrl_ndtr2_default + &pinctrl_ndsr2_default + &pinctrl_ncts2_default + &pinctrl_ndcd2_default + &pinctrl_nri2_default>; +}; + +&uart3 { + status = "okay"; +}; + +&uart4 { + status = "okay"; +}; + +&uart5 { + status = "okay"; +}; + +&mac0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rmii1_default>; + clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>, + <&syscon ASPEED_CLK_MAC1RCLK>; + clock-names = "MACCLK", "RCLK"; + use-ncsi; +}; + +&mac1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>; +}; + +&i2c0 { + status = "okay"; +}; + +&i2c1 { + status = "okay"; +}; + +&i2c2 { + status = "okay"; +}; + +&i2c3 { + status = "okay"; + i2c-switch@70 { + compatible = "nxp,pca9546"; + reg = <0x70>; + #address-cells = <1>; + #size-cells = <0>; + + channel_3_0: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + channel_3_1: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + channel_3_2: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + channel_3_3: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + }; +}; + +&i2c4 { + status = "okay"; + +}; + +&i2c5 { + status = "okay"; +}; + +&i2c6 { + status = "okay"; + i2c-switch@72 { + compatible = "nxp,pca9548"; + reg = <0x72>; + #address-cells = <1>; + #size-cells = <0>; + channel_6_0: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + channel_6_1: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + channel_6_2: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + channel_6_3: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + channel_6_4: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + + channel_6_5: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + + channel_6_6: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + }; + + channel_6_7: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + }; + }; + + i2c-switch@70 { + compatible = "nxp,pca9546"; + reg = <0x70>; + #address-cells = <1>; + #size-cells = <0>; + channel_6_8: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + i2c-switch@71 { + compatible = "nxp,pca9546"; + reg = <0x71>; + #address-cells = <1>; + #size-cells = <0>; + channel_6_12: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + }; + + channel_6_13: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + channel_6_14: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + channel_6_15: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + }; + }; + + channel_6_9: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + i2c-switch@71 { + compatible = "nxp,pca9546"; + reg = <0x71>; + #address-cells = <1>; + #size-cells = <0>; + channel_6_16: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + }; + + channel_6_17: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + channel_6_18: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + channel_6_19: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + }; + }; + + channel_6_10: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + i2c-switch@71 { + compatible = "nxp,pca9546"; + reg = <0x71>; + #address-cells = <1>; + #size-cells = <0>; + channel_6_20: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + channel_6_21: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + channel_6_22: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + channel_6_23: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + }; + }; + + channel_6_11: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + i2c-switch@71 { + compatible = "nxp,pca9546"; + reg = <0x71>; + #address-cells = <1>; + #size-cells = <0>; + channel_6_24: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + channel_6_25: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + }; + }; + }; +}; + +&i2c7 { + status = "okay"; +}; + +&i2c8 { + status = "okay"; + pca0:pca9555@24 { + compatible = "nxp,pca9555"; + reg = <0x24>; + #address-cells = <1>; + #size-cells = <0>; + + gpio-controller; + #gpio-cells = <2>; + gpio@1 { + reg = <1>; + type = ; + }; + + gpio@8 { + reg = <8>; + type = ; + }; + + gpio@9 { + reg = <9>; + type = ; + }; + + gpio@10 { + reg = <10>; + type = ; + }; + + gpio@11 { + reg = <11>; + type = ; + }; + + gpio@12 { + reg = <12>; + type = ; + }; + + gpio@13 { + reg = <13>; + type = ; + }; + }; + + pca1:pca9555@25 { + compatible = "nxp,pca9555"; + reg = <0x25>; + + #address-cells = <1>; + #size-cells = <0>; + + gpio-controller; + #gpio-cells = <2>; + + gpio@0 { + reg = <0>; + type = ; + }; + + gpio@1 { + reg = <1>; + type = ; + }; + + gpio@2 { + reg = <2>; + type = ; + }; + + gpio@3 { + reg = <3>; + type = ; + }; + + gpio@4 { + reg = <4>; + type = ; + }; + + gpio@5 { + reg = <5>; + type = ; + }; + + gpio@6 { + reg = <6>; + type = ; + }; + + gpio@7 { + reg = <7>; + type = ; + }; + gpio@8 { + reg = <8>; + type = ; + }; + + gpio@9 { + reg = <9>; + type = ; + }; + + gpio@10 { + reg = <10>; + type = ; + }; + + gpio@11 { + reg = <11>; + type = ; + }; + + gpio@12 { + reg = <12>; + type = ; + }; + + gpio@13 { + reg = <13>; + type = ; + }; + + gpio@14 { + reg = <14>; + type = ; + }; + + gpio@15 { + reg = <15>; + type = ; + }; + }; +}; + +&i2c9 { + status = "okay"; +}; + +&i2c10 { + status = "okay"; + i2c-switch@70 { + compatible = "nxp,pca9546"; + reg = <0x70>; + #address-cells = <1>; + #size-cells = <0>; + channel_10_0: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + channel_10_1: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + channel_10_2: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + channel_10_3: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + }; + + i2c-switch@71 { + compatible = "nxp,pca9546"; + reg = <0x71>; + #address-cells = <1>; + #size-cells = <0>; + channel_10_4: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + channel_10_5: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + channel_10_6: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + channel_10_7: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + }; +}; + +&i2c11 { + status = "okay"; +}; + +&i2c12 { + status = "okay"; +}; + +&i2c13 { + status = "okay"; +}; + +&pwm_tacho { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm0_default &pinctrl_pwm1_default + &pinctrl_pwm2_default &pinctrl_pwm3_default + &pinctrl_pwm4_default &pinctrl_pwm5_default>; + + fan@0 { + reg = <0x00>; + aspeed,fan-tach-ch = /bits/ 8 <0x00 0x01>; + }; + fan@1 { + reg = <0x01>; + aspeed,fan-tach-ch = /bits/ 8 <0x02 0x03>; + }; + fan@2 { + reg = <0x02>; + aspeed,fan-tach-ch = /bits/ 8 <0x04 0x05>; + }; + fan@3 { + reg = <0x03>; + aspeed,fan-tach-ch = /bits/ 8 <0x06 0x07>; + }; + fan@4 { + reg = <0x04>; + aspeed,fan-tach-ch = /bits/ 8 <0x08 0x09>; + }; + fan@5 { + reg = <0x05>; + aspeed,fan-tach-ch = /bits/ 8 <0x0a 0x0b>; + }; +}; + +&gpio { + pin_gpio_i3 { + gpio-hog; + gpios = ; + output-low; + line-name = "NCSI_BMC_R_SEL"; + }; + + pin_gpio_b6 { + gpio-hog; + gpios = ; + output-low; + line-name = "EN_NCSI_SWITCH_N"; + }; +}; + +&video { + status = "okay"; + memory-region = <&video_engine_memory>; +}; + +&vhub { + status = "okay"; +}; From abe75295ba70bd1c245977c200ce65575dbaf081 Mon Sep 17 00:00:00 2001 From: John Wang Date: Wed, 14 Oct 2020 16:30:57 +0800 Subject: [PATCH 061/799] ARM: dts: aspeed: g220a: Add some gpios Add GPIO STRAP_BMC_BATTERY_GPIOS5, which is used for battery adc sensor. Change the INTRUDER_N to CHASSIS_INTRUSION, to make it more meaningful. Signed-off-by: John Wang Reviewed-by: Joel Stanley Link: https://lore.kernel.org/r/20201014083057.1026-1-wangzhiqiang.bj@bytedance.com Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-bmc-bytedance-g220a.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/aspeed-bmc-bytedance-g220a.dts b/arch/arm/boot/dts/aspeed-bmc-bytedance-g220a.dts index 0aeec7017e43..2feb25b0e43b 100644 --- a/arch/arm/boot/dts/aspeed-bmc-bytedance-g220a.dts +++ b/arch/arm/boot/dts/aspeed-bmc-bytedance-g220a.dts @@ -309,11 +309,11 @@ /*N0-N7*/ "","","","","","","","", /*O0-O7*/ "","","","","","","","", /*P0-P7*/ "","","","","","","","", - /*Q0-Q7*/ "","","","","","","FM_PCH_THERMTRIP_N","INTRUDER_N", + /*Q0-Q7*/ "","","","","","","FM_PCH_THERMTRIP_N","CHASSIS_INTRUSION", /*R0-R7*/ "","PVCCIN_CPU1_SMBALERT_N","BMC_PREQ_R_N","FAULT_P12V_PCIE_RISER_N", "ALT_P12V_PCIE_RISER_N","BURN_BOARD_N","PVCCIN_CPU0_SMBALERT_N","", /*S0-S7*/ "BMC_PRDY_N","SIO_POWER_GOOD","FM_BMC_PWR_DEBUG_R_N", - "FM_BMC_XDP_DEBUG_EN","","","","", + "FM_BMC_XDP_DEBUG_EN","","STRAP_BMC_BATTERY_GPIOS5","","", /*T0-T7*/ "","","","","","","","", /*U0-U7*/ "","","","","","","","", /*V0-V7*/ "","","","","","","","", From 9e3ed6fa024c7a1be3c41f64da779072c2b85b7f Mon Sep 17 00:00:00 2001 From: George Liu Date: Thu, 22 Oct 2020 16:10:02 +0800 Subject: [PATCH 062/799] ARM: dts: Fix label address for 64MiB OpenBMC flash layout Signed-off-by: George Liu Reviewed-by: John Wang Acked-by: Andrew Jeffery Link: https://lore.kernel.org/r/20201022081002.2665132-1-liuxiwei@inspur.com Signed-off-by: Joel Stanley --- arch/arm/boot/dts/openbmc-flash-layout-64.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/openbmc-flash-layout-64.dtsi b/arch/arm/boot/dts/openbmc-flash-layout-64.dtsi index c8e0409d889e..91163867be34 100644 --- a/arch/arm/boot/dts/openbmc-flash-layout-64.dtsi +++ b/arch/arm/boot/dts/openbmc-flash-layout-64.dtsi @@ -13,22 +13,22 @@ partitions { label = "u-boot"; }; - u-boot-env@e0000 { + u-boot-env@60000 { reg = <0x60000 0x20000>; // 128KB label = "u-boot-env"; }; - kernel@100000 { + kernel@80000 { reg = <0x80000 0x500000>; // 5MB label = "kernel"; }; - rofs@a00000 { + rofs@580000 { reg = <0x580000 0x2a80000>; // 42.5MB label = "rofs"; }; - rwfs@6000000 { + rwfs@3000000 { reg = <0x3000000 0x1000000>; // 16MB label = "rwfs"; }; From faa3b6dfd2527eace517e0cd1b147154c780d582 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Fri, 28 Aug 2020 21:33:02 +0530 Subject: [PATCH 063/799] ARM: dts: imx6q-icore-ofcap10: Use 10.1" Ampire panel compatible Adding display timings directly on device tree files make it difficult to maintain as a same copy of timings may exist on different files or panel-simple driver. We have a panel-simple driver for this particular usage so supporting on this driver will help to use the same timings on any device tree files if the board mounted on a similar vendor display. Engicam C.TOUCH OF 10.1" LCD board uses Ampire 10.1" TFT LCD and it has supported by panel-simple already, so simply use that binding. Signed-off-by: Jagan Teki Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6q-icore-ofcap10.dts | 28 +++++++++++++---------- 1 file changed, 16 insertions(+), 12 deletions(-) diff --git a/arch/arm/boot/dts/imx6q-icore-ofcap10.dts b/arch/arm/boot/dts/imx6q-icore-ofcap10.dts index 81cc346dd149..02aca1e28ce3 100644 --- a/arch/arm/boot/dts/imx6q-icore-ofcap10.dts +++ b/arch/arm/boot/dts/imx6q-icore-ofcap10.dts @@ -12,6 +12,17 @@ / { model = "Engicam i.CoreM6 Quad/Dual OpenFrame Capacitive touch 10.1 Kit"; compatible = "engicam,imx6-icore", "fsl,imx6q"; + + panel { + compatible = "ampire,am-1280800n3tzqw-t00h"; + backlight = <&backlight_lvds>; + + port { + panel_in: endpoint { + remote-endpoint = <&lvds0_out>; + }; + }; + }; }; &ldb { @@ -22,18 +33,11 @@ fsl,data-width = <24>; status = "okay"; - display-timings { - native-mode = <&timing0>; - timing0: timing0 { - clock-frequency = <60000000>; - hactive = <1280>; - vactive = <800>; - hback-porch = <40>; - hfront-porch = <40>; - vback-porch = <10>; - vfront-porch = <3>; - hsync-len = <80>; - vsync-len = <10>; + port@4 { + reg = <4>; + + lvds0_out: endpoint { + remote-endpoint = <&panel_in>; }; }; }; From 7ead9dbb6ff475ec616adbb97dedcb26400fbb0c Mon Sep 17 00:00:00 2001 From: Matthias Schiffer Date: Fri, 18 Sep 2020 13:29:30 +0200 Subject: [PATCH 064/799] dt-bindings: arm: fsl: update TQ-Systems SoMs and boards based on i.MX7 Introduce compatible strings for the TQMa7x SoMs. Signed-off-by: Matthias Schiffer Reviewed-by: Rob Herring Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/arm/fsl.yaml | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index 1ca9dfa8ce9a..b0db3c90914b 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -354,7 +354,12 @@ properties: - toradex,colibri-imx7s # Colibri iMX7 Solo Module - toradex,colibri-imx7s-aster # Colibri iMX7 Solo Module on Aster Carrier Board - toradex,colibri-imx7s-eval-v3 # Colibri iMX7 Solo Module on Colibri Evaluation Board V3 - - tq,imx7s-mba7 # i.MX7S TQ MBa7 with TQMa7S SoM + - const: fsl,imx7s + + - description: TQ-Systems TQMa7S SoM on MBa7x board + items: + - const: tq,imx7s-mba7 + - const: tq,imx7s-tqma7 - const: fsl,imx7s - description: i.MX7D based Boards @@ -376,11 +381,16 @@ properties: # Colibri Evaluation Board V3 - toradex,colibri-imx7d-eval-v3 # Colibri iMX7 Dual Module on # Colibri Evaluation Board V3 - - tq,imx7d-mba7 # i.MX7D TQ MBa7 with TQMa7D SoM - zii,imx7d-rmu2 # ZII RMU2 Board - zii,imx7d-rpu2 # ZII RPU2 Board - const: fsl,imx7d + - description: TQ-Systems TQMa7D SoM on MBa7x board + items: + - const: tq,imx7d-mba7 + - const: tq,imx7d-tqma7 + - const: fsl,imx7d + - description: Compulab SBC-iMX7 is a single board computer based on the Freescale i.MX7 system-on-chip. SBC-iMX7 is implemented with From 68e680c5faddb207ac4ebb50c88bcc88284bcd5f Mon Sep 17 00:00:00 2001 From: Matthias Schiffer Date: Fri, 18 Sep 2020 13:29:32 +0200 Subject: [PATCH 065/799] ARM: dts: imx7-mba7: update compatible strings Include the SoM compatible string. Signed-off-by: Matthias Schiffer Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx7d-mba7.dts | 2 +- arch/arm/boot/dts/imx7s-mba7.dts | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/imx7d-mba7.dts b/arch/arm/boot/dts/imx7d-mba7.dts index 221274c73dbd..9f4f7112e598 100644 --- a/arch/arm/boot/dts/imx7d-mba7.dts +++ b/arch/arm/boot/dts/imx7d-mba7.dts @@ -14,7 +14,7 @@ / { model = "TQ Systems TQMa7D board on MBa7 carrier board"; - compatible = "tq,imx7d-mba7", "fsl,imx7d"; + compatible = "tq,imx7d-mba7", "tq,imx7d-tqma7", "fsl,imx7d"; }; &fec2 { diff --git a/arch/arm/boot/dts/imx7s-mba7.dts b/arch/arm/boot/dts/imx7s-mba7.dts index a143d566a38b..d7d3f530f843 100644 --- a/arch/arm/boot/dts/imx7s-mba7.dts +++ b/arch/arm/boot/dts/imx7s-mba7.dts @@ -14,5 +14,5 @@ / { model = "TQ Systems TQMa7S board on MBa7 carrier board"; - compatible = "tq,imx7s-mba7", "fsl,imx7s"; + compatible = "tq,imx7s-mba7", "tq,imx7s-tqma7", "fsl,imx7s"; }; From f7defed53e35fada087a6bde29810be74576b86e Mon Sep 17 00:00:00 2001 From: Matthias Schiffer Date: Fri, 18 Sep 2020 13:29:33 +0200 Subject: [PATCH 066/799] ARM: dts: imx7-mba7: drop incorrect num-chipselects property This property was never set correctly; it should have been num-cs. As num-cs support is being removed as well, simply drop it. Signed-off-by: Matthias Schiffer Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx7-mba7.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm/boot/dts/imx7-mba7.dtsi b/arch/arm/boot/dts/imx7-mba7.dtsi index 50abf18ad30b..d99912ade947 100644 --- a/arch/arm/boot/dts/imx7-mba7.dtsi +++ b/arch/arm/boot/dts/imx7-mba7.dtsi @@ -179,7 +179,6 @@ &ecspi1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi1>; - num-chipselects = <3>; cs-gpios = <&gpio4 0 GPIO_ACTIVE_LOW>, <&gpio4 1 GPIO_ACTIVE_LOW>, <&gpio4 2 GPIO_ACTIVE_LOW>; status = "okay"; @@ -188,7 +187,6 @@ &ecspi2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi2>; - num-chipselects = <1>; status = "okay"; }; From 2b01d7a1571b8558dcadee84d575ab31bf39efa2 Mon Sep 17 00:00:00 2001 From: Matthias Schiffer Date: Fri, 18 Sep 2020 13:29:34 +0200 Subject: [PATCH 067/799] ARM: dts: imx7-mba7: remove unsupported PHY LED setup These properties were never supported by the DP83867, and a patch implementing them was rejected in favor of a different solution. Remove them. Signed-off-by: Matthias Schiffer Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx7-mba7.dtsi | 4 ---- arch/arm/boot/dts/imx7d-mba7.dts | 4 ---- 2 files changed, 8 deletions(-) diff --git a/arch/arm/boot/dts/imx7-mba7.dtsi b/arch/arm/boot/dts/imx7-mba7.dtsi index d99912ade947..1af40032ab17 100644 --- a/arch/arm/boot/dts/imx7-mba7.dtsi +++ b/arch/arm/boot/dts/imx7-mba7.dtsi @@ -212,10 +212,6 @@ ti,rx-internal-delay = ; ti,tx-internal-delay = ; ti,fifo-depth = ; - /* LED1: Link/Activity, LED2: Error */ - ti,led-function = <0x0db0>; - /* Active low, LED1 and LED2 driven by phy */ - ti,led-ctrl = <0x1001>; }; }; }; diff --git a/arch/arm/boot/dts/imx7d-mba7.dts b/arch/arm/boot/dts/imx7d-mba7.dts index 9f4f7112e598..1101be373ddf 100644 --- a/arch/arm/boot/dts/imx7d-mba7.dts +++ b/arch/arm/boot/dts/imx7d-mba7.dts @@ -39,10 +39,6 @@ ti,rx-internal-delay = ; ti,tx-internal-delay = ; ti,fifo-depth = ; - /* LED1: Link/Activity, LED2: error */ - ti,led-function = <0x0db0>; - /* active low, LED1/2 driven by phy */ - ti,led-ctrl = <0x1001>; }; }; }; From e70f9b9c25eae1b1624a976773817470c51d1e9f Mon Sep 17 00:00:00 2001 From: Matthias Schiffer Date: Fri, 18 Sep 2020 13:29:35 +0200 Subject: [PATCH 068/799] ARM: dts: imx7-mba7: disable ethernet PHY clock outputs The clock outputs are not connected. Disable them to improve EMI behaviour. Signed-off-by: Matthias Schiffer Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx7-mba7.dtsi | 1 + arch/arm/boot/dts/imx7d-mba7.dts | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/imx7-mba7.dtsi b/arch/arm/boot/dts/imx7-mba7.dtsi index 1af40032ab17..9be225bb135a 100644 --- a/arch/arm/boot/dts/imx7-mba7.dtsi +++ b/arch/arm/boot/dts/imx7-mba7.dtsi @@ -212,6 +212,7 @@ ti,rx-internal-delay = ; ti,tx-internal-delay = ; ti,fifo-depth = ; + ti,clk-output-sel = ; }; }; }; diff --git a/arch/arm/boot/dts/imx7d-mba7.dts b/arch/arm/boot/dts/imx7d-mba7.dts index 1101be373ddf..5ef86de53013 100644 --- a/arch/arm/boot/dts/imx7d-mba7.dts +++ b/arch/arm/boot/dts/imx7d-mba7.dts @@ -39,6 +39,7 @@ ti,rx-internal-delay = ; ti,tx-internal-delay = ; ti,fifo-depth = ; + ti,clk-output-sel = ; }; }; }; From d50765205d8e59e4116a9dc512305cef15e70ad2 Mon Sep 17 00:00:00 2001 From: Matthias Schiffer Date: Fri, 18 Sep 2020 13:29:36 +0200 Subject: [PATCH 069/799] ARM: dts: imx7-mba7: configure watchdog The external watchdog reset is necessary, as the internal reset is unreliable on i.MX7. Signed-off-by: Matthias Schiffer Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx7-mba7.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm/boot/dts/imx7-mba7.dtsi b/arch/arm/boot/dts/imx7-mba7.dtsi index 9be225bb135a..84b5809f384c 100644 --- a/arch/arm/boot/dts/imx7-mba7.dtsi +++ b/arch/arm/boot/dts/imx7-mba7.dtsi @@ -467,6 +467,12 @@ MX7D_PAD_LPSR_GPIO1_IO05__GPIO1_IO5 0x59 >; }; + + pinctrl_wdog1: wdog1grp { + fsl,pins = < + MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x30 + >; + }; }; &pwm1 { @@ -543,3 +549,9 @@ no-1-8-v; status = "okay"; }; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog1>; + fsl,ext-reset-output; +}; From ecb5ba9f112424ed43907cd95ddf6a5eb8c0e6fe Mon Sep 17 00:00:00 2001 From: Matthias Schiffer Date: Fri, 18 Sep 2020 13:29:37 +0200 Subject: [PATCH 070/799] ARM: dts: imx7-mba7: update MMC aliases Together with the recently merged support for alias-based MMC host numbering, this makes the MMC devices names match what the bootloader expects. Signed-off-by: Matthias Schiffer Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx7-mba7.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/boot/dts/imx7-mba7.dtsi b/arch/arm/boot/dts/imx7-mba7.dtsi index 84b5809f384c..215730e0453e 100644 --- a/arch/arm/boot/dts/imx7-mba7.dtsi +++ b/arch/arm/boot/dts/imx7-mba7.dtsi @@ -14,6 +14,12 @@ #include / { + aliases { + mmc0 = &usdhc3; + mmc1 = &usdhc1; + /delete-property/ mmc2; + }; + beeper { compatible = "gpio-beeper"; gpios = <&pca9555 0 GPIO_ACTIVE_HIGH>; From 0d5e50cf30d7c6ec56013234595ddefdaba64593 Mon Sep 17 00:00:00 2001 From: Matthias Schiffer Date: Fri, 18 Sep 2020 13:29:38 +0200 Subject: [PATCH 071/799] ARM: dts: imx7-mba7: add audio support The MBa7x is equipped with a TI TLV320AIC3204 audio codec. Signed-off-by: Matthias Schiffer Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx7-mba7.dtsi | 38 +++++++++++++++++++++++++++++++- 1 file changed, 37 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/imx7-mba7.dtsi b/arch/arm/boot/dts/imx7-mba7.dtsi index 215730e0453e..9cfaf0a91100 100644 --- a/arch/arm/boot/dts/imx7-mba7.dtsi +++ b/arch/arm/boot/dts/imx7-mba7.dtsi @@ -170,6 +170,20 @@ regulator-max-microvolt = <3300000>; regulator-always-on; }; + + sound { + compatible = "fsl,imx-audio-tlv320aic32x4"; + model = "imx-audio-tlv320aic32x4"; + ssi-controller = <&sai1>; + audio-codec = <&tlv320aic32x4>; + audio-routing = + "IN3_L", "Mic Jack", + "Mic Jack", "Mic Bias", + "IN1_L", "Line In Jack", + "IN1_R", "Line In Jack", + "Line Out Jack", "LOL", + "Line Out Jack", "LOR"; + }; }; &adc1 { @@ -363,13 +377,25 @@ >; }; - pinctrl_pca9555: pca95550grp { fsl,pins = < MX7D_PAD_ENET1_TX_CLK__GPIO7_IO12 0x78 >; }; + pinctrl_sai1: sai1grp { + fsl,pins = < + MX7D_PAD_SAI1_MCLK__SAI1_MCLK 0x11 + MX7D_PAD_SAI1_RX_BCLK__SAI1_RX_BCLK 0x1c + MX7D_PAD_SAI1_RX_DATA__SAI1_RX_DATA0 0x1c + MX7D_PAD_SAI1_RX_SYNC__SAI2_RX_SYNC 0x1c + + MX7D_PAD_SAI1_TX_BCLK__SAI1_TX_BCLK 0x1c + MX7D_PAD_SAI1_TX_DATA__SAI1_TX_DATA0 0x14 + MX7D_PAD_SAI1_TX_SYNC__SAI1_TX_SYNC 0x14 + >; + }; + pinctrl_uart3: uart3grp { fsl,pins = < MX7D_PAD_UART3_RX_DATA__UART3_DCE_RX 0x7e @@ -487,6 +513,16 @@ status = "okay"; }; +&sai1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai1>; + assigned-clocks = <&clks IMX7D_SAI1_ROOT_SRC>, + <&clks IMX7D_SAI1_ROOT_CLK>; + assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>; + assigned-clock-rates = <0>, <36864000>; + status = "okay"; +}; + &uart3 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart3>; From 9af6702fa1e3ecdbed8c297e3c08103c2ceda112 Mon Sep 17 00:00:00 2001 From: Matthias Schiffer Date: Fri, 18 Sep 2020 13:29:40 +0200 Subject: [PATCH 072/799] ARM: dts: imx7-mba7: enable RS485 on UART7 The UART7 interface is connected to a full-duplex RS485 transceiver. Signed-off-by: Matthias Schiffer Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx7-mba7.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/boot/dts/imx7-mba7.dtsi b/arch/arm/boot/dts/imx7-mba7.dtsi index 9cfaf0a91100..ea9f0a4ac4b5 100644 --- a/arch/arm/boot/dts/imx7-mba7.dtsi +++ b/arch/arm/boot/dts/imx7-mba7.dtsi @@ -561,6 +561,9 @@ assigned-clocks = <&clks IMX7D_UART7_ROOT_SRC>; assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>; uart-has-rtscts; + linux,rs485-enabled-at-boot-time; + rs485-rts-active-low; + rs485-rx-during-tx; status = "okay"; }; From b8a4f64a3277fd30b1ee04bacf03d0dd3f5ade88 Mon Sep 17 00:00:00 2001 From: Matthias Schiffer Date: Fri, 18 Sep 2020 13:29:41 +0200 Subject: [PATCH 073/799] ARM: dts: imx7-mba7: specify USB over-current polarity Add over-current-active-low to usbotg1. Signed-off-by: Matthias Schiffer Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx7-mba7.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/imx7-mba7.dtsi b/arch/arm/boot/dts/imx7-mba7.dtsi index ea9f0a4ac4b5..f9704c354e1d 100644 --- a/arch/arm/boot/dts/imx7-mba7.dtsi +++ b/arch/arm/boot/dts/imx7-mba7.dtsi @@ -578,6 +578,7 @@ srp-disable; hnp-disable; adp-disable; + over-current-active-low; dr_mode = "host"; status = "okay"; }; From 42ab1ba8873d0b144a9417231e7b15a26b6137ad Mon Sep 17 00:00:00 2001 From: Matthias Schiffer Date: Fri, 18 Sep 2020 13:29:42 +0200 Subject: [PATCH 074/799] ARM: dts: imx7-mba7: set dr_mode to otg on usbotg1 USBOTG1 has a Micro-USB port that can be used in host mode (using an OTG cable) or device mode. Signed-off-by: Matthias Schiffer Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx7-mba7.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/imx7-mba7.dtsi b/arch/arm/boot/dts/imx7-mba7.dtsi index f9704c354e1d..c6d1c63f7905 100644 --- a/arch/arm/boot/dts/imx7-mba7.dtsi +++ b/arch/arm/boot/dts/imx7-mba7.dtsi @@ -579,7 +579,7 @@ hnp-disable; adp-disable; over-current-active-low; - dr_mode = "host"; + dr_mode = "otg"; status = "okay"; }; From a8d54a39e95f5cff7ba25b344cbab9b598bbf937 Mon Sep 17 00:00:00 2001 From: Stefan Riedmueller Date: Tue, 22 Sep 2020 11:23:08 +0200 Subject: [PATCH 075/799] ARM: dts: imx6ul: segin: Fix stmpe touchscreen subnode name The touchscreen subnode name needs to be stmpe_touchscreen as mentioned in the dt-bindings. Signed-off-by: Stefan Riedmueller Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6ul-phytec-segin.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/imx6ul-phytec-segin.dtsi b/arch/arm/boot/dts/imx6ul-phytec-segin.dtsi index f1513e676c2f..7367279748f4 100644 --- a/arch/arm/boot/dts/imx6ul-phytec-segin.dtsi +++ b/arch/arm/boot/dts/imx6ul-phytec-segin.dtsi @@ -139,7 +139,7 @@ pinctrl-0 = <&pinctrl_stmpe>; status = "disabled"; - touchscreen { + stmpe_touchscreen { compatible = "st,stmpe-ts"; st,sample-time = <4>; st,mod-12b = <1>; From f0e24ec59076df374d4e8f15a9658e140858afb0 Mon Sep 17 00:00:00 2001 From: Stefan Riedmueller Date: Tue, 22 Sep 2020 11:23:09 +0200 Subject: [PATCH 076/799] ARM: dts: imx6: phytec: Set correct eeprom compatible Set the correct EEPROM compatible for phyCORE-i.MX 6 and phyFLEX-i.MX 6, as stated in the device tree bindings. Signed-off-by: Stefan Riedmueller Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi | 2 +- arch/arm/boot/dts/imx6qdl-phytec-phycore-som.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi b/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi index e361df26a168..d51852857758 100644 --- a/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi +++ b/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi @@ -116,7 +116,7 @@ status = "okay"; som_eeprom: eeprom@50 { - compatible = "atmel,24c32"; + compatible = "catalyst,24c32", "atmel,24c32"; reg = <0x50>; }; diff --git a/arch/arm/boot/dts/imx6qdl-phytec-phycore-som.dtsi b/arch/arm/boot/dts/imx6qdl-phytec-phycore-som.dtsi index 41ebe4599e43..a3f4e8f6cc9e 100644 --- a/arch/arm/boot/dts/imx6qdl-phytec-phycore-som.dtsi +++ b/arch/arm/boot/dts/imx6qdl-phytec-phycore-som.dtsi @@ -84,7 +84,7 @@ status = "okay"; eeprom@50 { - compatible = "atmel,24c32"; + compatible = "st,24c32", "atmel,24c32"; reg = <0x50>; }; From 0d31d5a96b8c6c5914995f4352c2ab50e50a1865 Mon Sep 17 00:00:00 2001 From: Stefan Riedmueller Date: Tue, 22 Sep 2020 11:23:10 +0200 Subject: [PATCH 077/799] ARM: dts: imx6: phytec: Add eeprom pagesize Defining the EEPROM pagesize can increase the write speed significantly. Set it to the pagesize stated in the EEPROM's datasheet for phyCORE-i.MX 6UL, phyCORE-i.MX 6 and phyFLEX-i.MX 6. Signed-off-by: Stefan Riedmueller Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi | 1 + arch/arm/boot/dts/imx6qdl-phytec-phycore-som.dtsi | 1 + arch/arm/boot/dts/imx6ul-phytec-phycore-som.dtsi | 1 + 3 files changed, 3 insertions(+) diff --git a/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi b/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi index d51852857758..7a1e53195785 100644 --- a/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi +++ b/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi @@ -117,6 +117,7 @@ som_eeprom: eeprom@50 { compatible = "catalyst,24c32", "atmel,24c32"; + pagesize = <32>; reg = <0x50>; }; diff --git a/arch/arm/boot/dts/imx6qdl-phytec-phycore-som.dtsi b/arch/arm/boot/dts/imx6qdl-phytec-phycore-som.dtsi index a3f4e8f6cc9e..a80aa08a37cb 100644 --- a/arch/arm/boot/dts/imx6qdl-phytec-phycore-som.dtsi +++ b/arch/arm/boot/dts/imx6qdl-phytec-phycore-som.dtsi @@ -85,6 +85,7 @@ eeprom@50 { compatible = "st,24c32", "atmel,24c32"; + pagesize = <32>; reg = <0x50>; }; diff --git a/arch/arm/boot/dts/imx6ul-phytec-phycore-som.dtsi b/arch/arm/boot/dts/imx6ul-phytec-phycore-som.dtsi index 88f631c8fabb..19a062635ff6 100644 --- a/arch/arm/boot/dts/imx6ul-phytec-phycore-som.dtsi +++ b/arch/arm/boot/dts/imx6ul-phytec-phycore-som.dtsi @@ -75,6 +75,7 @@ eeprom@52 { compatible = "catalyst,24c32", "atmel,24c32"; + pagesize = <32>; reg = <0x52>; }; }; From 04fa4f03e3533f51b4db19cb487435f5862a0514 Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Thu, 1 Oct 2020 11:11:30 +0200 Subject: [PATCH 078/799] arm64: dts: ls1028a: add missing CAN nodes The LS1028A has two FlexCAN controller. These are compatible with the ones from the LX2160A. Add the nodes. The first controller was tested on the Kontron sl28 board. Signed-off-by: Michael Walle Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi index 73e4f9466887..ac17752ab3ec 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi @@ -386,6 +386,24 @@ status = "disabled"; }; + can0: can@2180000 { + compatible = "fsl,ls1028ar1-flexcan", "fsl,lx2160ar1-flexcan"; + reg = <0x0 0x2180000 0x0 0x10000>; + interrupts = ; + clocks = <&sysclk>, <&clockgen 4 1>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + can1: can@2190000 { + compatible = "fsl,ls1028ar1-flexcan", "fsl,lx2160ar1-flexcan"; + reg = <0x0 0x2190000 0x0 0x10000>; + interrupts = ; + clocks = <&sysclk>, <&clockgen 4 1>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + duart0: serial@21c0500 { compatible = "fsl,ns16550", "ns16550a"; reg = <0x00 0x21c0500 0x0 0x100>; From 7e2ac9deb1d66401291d456aa27f081bbb9071de Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Thu, 1 Oct 2020 11:11:31 +0200 Subject: [PATCH 079/799] arm64: dts: freescale: sl28: add CAN node The module supports one CAN controller. Enable it. Signed-off-by: Michael Walle Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28.dts index f46eb47cfa4d..17a2f5dacc3f 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28.dts @@ -60,6 +60,10 @@ }; }; +&can0 { + status = "okay"; +}; + &dspi2 { status = "okay"; }; From 02e46262af5db410da5a27783833d68e2bdfb352 Mon Sep 17 00:00:00 2001 From: Alexander Dahl Date: Mon, 5 Oct 2020 22:34:43 +0200 Subject: [PATCH 080/799] ARM: dts: at91: smartkiz: Reference led node directly Do it the simple way like for the other kizbox boards. This will allow renaming the led controller node name later without breaking things. Signed-off-by: Alexander Dahl Signed-off-by: Alexandre Belloni Link: https://lore.kernel.org/r/20201005203451.9985-5-post@lespocky.de --- arch/arm/boot/dts/at91-smartkiz.dts | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/at91-smartkiz.dts b/arch/arm/boot/dts/at91-smartkiz.dts index 106f23ba4a3b..b76a6b5ac464 100644 --- a/arch/arm/boot/dts/at91-smartkiz.dts +++ b/arch/arm/boot/dts/at91-smartkiz.dts @@ -84,10 +84,8 @@ status = "okay"; }; -&leds { - blue { - status = "okay"; - }; +&led_blue { + status = "okay"; }; &adc0 { From 997ebd64df39f3916c37ca67a6eff58e79a13c73 Mon Sep 17 00:00:00 2001 From: Alexander Dahl Date: Mon, 5 Oct 2020 22:34:44 +0200 Subject: [PATCH 081/799] ARM: dts: at91: Fix schema warnings for pwm-leds The node names for devices using the pwm-leds driver follow a certain naming scheme (now). Parent node name is not enforced, but recommended by DT project. DTC arch/arm/boot/dts/at91-kizbox2-2.dt.yaml CHECK arch/arm/boot/dts/at91-kizbox2-2.dt.yaml /home/alex/build/linux/arch/arm/boot/dts/at91-kizbox2-2.dt.yaml: pwm_leds: 'blue', 'green', 'red' do not match any of the regexes: '^led(-[0-9a-f]+)?$', 'pinctrl-[0-9]+' From schema: /home/alex/src/linux/leds/Documentation/devicetree/bindings/leds/leds-pwm.yaml DTC arch/arm/boot/dts/at91-kizbox3-hs.dt.yaml CHECK arch/arm/boot/dts/at91-kizbox3-hs.dt.yaml /home/alex/build/linux/arch/arm/boot/dts/at91-kizbox3-hs.dt.yaml: pwm_leds: 'blue', 'green', 'red', 'white' do not match any of the regexes: '^led(-[0-9a-f]+)?$', 'pinctrl-[0-9]+' From schema: /home/alex/src/linux/leds/Documentation/devicetree/bindings/leds/leds-pwm.yaml (Warnings above are for armv7 only, armv5 would produce similar warnings.) Signed-off-by: Alexander Dahl Signed-off-by: Alexandre Belloni Link: https://lore.kernel.org/r/20201005203451.9985-6-post@lespocky.de --- arch/arm/boot/dts/at91-kizbox.dts | 10 +++++----- arch/arm/boot/dts/at91-kizbox2-common.dtsi | 8 ++++---- arch/arm/boot/dts/at91-kizbox3-hs.dts | 16 ++++++++-------- arch/arm/boot/dts/at91-kizbox3_common.dtsi | 10 +++++----- arch/arm/boot/dts/at91-kizboxmini-common.dtsi | 8 ++++---- arch/arm/boot/dts/at91sam9m10g45ek.dts | 10 +++++----- arch/arm/boot/dts/at91sam9rlek.dts | 10 +++++----- 7 files changed, 36 insertions(+), 36 deletions(-) diff --git a/arch/arm/boot/dts/at91-kizbox.dts b/arch/arm/boot/dts/at91-kizbox.dts index 7add151f6250..8b33fe5564fe 100644 --- a/arch/arm/boot/dts/at91-kizbox.dts +++ b/arch/arm/boot/dts/at91-kizbox.dts @@ -48,31 +48,31 @@ }; }; - pwm_leds { + led-controller { compatible = "pwm-leds"; - network_green { + led-1 { label = "pwm:green:network"; pwms = <&tcb_pwm 2 10000000 PWM_POLARITY_INVERTED>; max-brightness = <255>; linux,default-trigger = "default-on"; }; - network_red { + led-2 { label = "pwm:red:network"; pwms = <&tcb_pwm 4 10000000 PWM_POLARITY_INVERTED>; max-brightness = <255>; linux,default-trigger = "default-on"; }; - user_green { + led-3 { label = "pwm:green:user"; pwms = <&tcb_pwm 0 10000000 PWM_POLARITY_INVERTED>; max-brightness = <255>; linux,default-trigger = "default-on"; }; - user_red { + led-4 { label = "pwm:red:user"; pwms = <&tcb_pwm 1 10000000 PWM_POLARITY_INVERTED>; max-brightness = <255>; diff --git a/arch/arm/boot/dts/at91-kizbox2-common.dtsi b/arch/arm/boot/dts/at91-kizbox2-common.dtsi index 25f761065106..c08834ddf07b 100644 --- a/arch/arm/boot/dts/at91-kizbox2-common.dtsi +++ b/arch/arm/boot/dts/at91-kizbox2-common.dtsi @@ -58,24 +58,24 @@ }; }; - pwm_leds { + led-controller { compatible = "pwm-leds"; - blue { + led-1 { label = "pwm:blue:user"; pwms = <&pwm0 2 10000000 0>; max-brightness = <255>; linux,default-trigger = "none"; }; - green { + led-2 { label = "pwm:green:user"; pwms = <&pwm0 1 10000000 0>; max-brightness = <255>; linux,default-trigger = "default-on"; }; - red { + led-3 { label = "pwm:red:user"; pwms = <&pwm0 0 10000000 0>; max-brightness = <255>; diff --git a/arch/arm/boot/dts/at91-kizbox3-hs.dts b/arch/arm/boot/dts/at91-kizbox3-hs.dts index 0da1f0557eaf..2799b2a1f4d2 100644 --- a/arch/arm/boot/dts/at91-kizbox3-hs.dts +++ b/arch/arm/boot/dts/at91-kizbox3-hs.dts @@ -15,40 +15,40 @@ model = "Overkiz KIZBOX3-HS"; compatible = "overkiz,kizbox3-hs", "atmel,sama5d2", "atmel,sama5"; - pwm_leds { + led-controller-1 { status = "okay"; - red { + led-1 { status = "okay"; }; - green { + led-2 { status = "okay"; }; - blue { + led-3 { status = "okay"; }; - white { + led-4 { status = "okay"; }; }; - leds { + led-controller-2 { compatible = "gpio-leds"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_led_red &pinctrl_led_white>; status = "okay"; - red { + led-5 { label = "pio:red:user"; gpios = <&pioA PIN_PB1 GPIO_ACTIVE_HIGH>; default-state = "off"; }; - white { + led-6 { label = "pio:white:user"; gpios = <&pioA PIN_PB8 GPIO_ACTIVE_HIGH>; default-state = "off"; diff --git a/arch/arm/boot/dts/at91-kizbox3_common.dtsi b/arch/arm/boot/dts/at91-kizbox3_common.dtsi index 7c3076e245ef..9ce513dd514b 100644 --- a/arch/arm/boot/dts/at91-kizbox3_common.dtsi +++ b/arch/arm/boot/dts/at91-kizbox3_common.dtsi @@ -62,7 +62,7 @@ regulator-always-on; }; - pwm_leds { + led-controller-1 { compatible = "pwm-leds"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm0_pwm_h0 @@ -71,7 +71,7 @@ &pinctrl_pwm0_pwm_h3>; status = "disabled"; - red { + led-1 { label = "pwm:red:user"; pwms = <&pwm0 0 10000000 0>; max-brightness = <255>; @@ -79,7 +79,7 @@ status = "disabled"; }; - green { + led-2 { label = "pwm:green:user"; pwms = <&pwm0 1 10000000 0>; max-brightness = <255>; @@ -87,14 +87,14 @@ status = "disabled"; }; - blue { + led-3 { label = "pwm:blue:user"; pwms = <&pwm0 2 10000000 0>; max-brightness = <255>; status = "disabled"; }; - white { + led-4 { label = "pwm:white:user"; pwms = <&pwm0 3 10000000 0>; max-brightness = <255>; diff --git a/arch/arm/boot/dts/at91-kizboxmini-common.dtsi b/arch/arm/boot/dts/at91-kizboxmini-common.dtsi index d37724c10695..9c622892c692 100644 --- a/arch/arm/boot/dts/at91-kizboxmini-common.dtsi +++ b/arch/arm/boot/dts/at91-kizboxmini-common.dtsi @@ -54,10 +54,10 @@ }; }; - leds: pwm_leds { + leds: led-controller-1 { compatible = "pwm-leds"; - led_blue: pwm_blue { + led_blue: led-1 { label = "pwm:blue:user"; pwms = <&pwm0 2 10000000 0>; max-brightness = <255>; @@ -65,14 +65,14 @@ status = "disabled"; }; - led_green: pwm_green { + led_green: led-2 { label = "pwm:green:user"; pwms = <&pwm0 0 10000000 0>; max-brightness = <255>; linux,default-trigger = "default-on"; }; - led_red: pwm_red { + led_red: led-3 { label = "pwm:red:user"; pwms = <&pwm0 1 10000000 0>; max-brightness = <255>; diff --git a/arch/arm/boot/dts/at91sam9m10g45ek.dts b/arch/arm/boot/dts/at91sam9m10g45ek.dts index 9734667abbfc..b6256a20fbc7 100644 --- a/arch/arm/boot/dts/at91sam9m10g45ek.dts +++ b/arch/arm/boot/dts/at91sam9m10g45ek.dts @@ -315,27 +315,27 @@ }; }; - leds { + led-controller-1 { compatible = "gpio-leds"; - d8 { + led-1 { label = "d8"; gpios = <&pioD 30 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; }; - pwmleds { + led-controller-2 { compatible = "pwm-leds"; - d6 { + led-2 { label = "d6"; pwms = <&pwm0 3 5000 PWM_POLARITY_INVERTED>; max-brightness = <255>; linux,default-trigger = "nand-disk"; }; - d7 { + led-3 { label = "d7"; pwms = <&pwm0 1 5000 PWM_POLARITY_INVERTED>; max-brightness = <255>; diff --git a/arch/arm/boot/dts/at91sam9rlek.dts b/arch/arm/boot/dts/at91sam9rlek.dts index 1590862f16f2..62981b39c815 100644 --- a/arch/arm/boot/dts/at91sam9rlek.dts +++ b/arch/arm/boot/dts/at91sam9rlek.dts @@ -218,26 +218,26 @@ }; }; - pwmleds { + led-controller-1 { compatible = "pwm-leds"; - ds1 { + led-1 { label = "ds1"; pwms = <&pwm0 1 5000 PWM_POLARITY_INVERTED>; max-brightness = <255>; }; - ds2 { + led-2 { label = "ds2"; pwms = <&pwm0 2 5000 PWM_POLARITY_INVERTED>; max-brightness = <255>; }; }; - leds { + led-controller-2 { compatible = "gpio-leds"; - ds3 { + led-3 { label = "ds3"; gpios = <&pioD 14 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; From 132e900a47b89c45f760c82f0d0929903b96eb08 Mon Sep 17 00:00:00 2001 From: Marek Szyprowski Date: Tue, 27 Oct 2020 15:23:28 +0100 Subject: [PATCH 082/799] ARM: dts: exynos: Enable Bluetooth support for Trats board Add a node for the BCM4334 Bluetooth chip on the serial bus #0 on the Exynos4210-based Trats boards. Signed-off-by: Marek Szyprowski Link: https://lore.kernel.org/r/20201027142330.5121-1-m.szyprowski@samsung.com Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos4210-trats.dts | 31 ++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/arch/arm/boot/dts/exynos4210-trats.dts b/arch/arm/boot/dts/exynos4210-trats.dts index a226bec56a45..eb6ca2a74cc0 100644 --- a/arch/arm/boot/dts/exynos4210-trats.dts +++ b/arch/arm/boot/dts/exynos4210-trats.dts @@ -462,6 +462,26 @@ }; }; +&pinctrl_1 { + bt_shutdown: bt-shutdown { + samsung,pins = "gpl1-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + bt_host_wakeup: bt-host-wakeup { + samsung,pins = "gpx2-6"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + bt_device_wakeup: bt-device-wakeup { + samsung,pins = "gpx3-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; +}; + &rtc { status = "okay"; clocks = <&clock CLK_RTC>, <&pmic_ap_clk>; @@ -512,6 +532,17 @@ &serial_0 { status = "okay"; + pinctrl-0 = <&uart0_data &uart0_fctl>; + pinctrl-names = "default"; + + bluetooth { + compatible = "brcm,bcm4330-bt"; + pinctrl-0 = <&bt_shutdown &bt_device_wakeup &bt_host_wakeup>; + pinctrl-names = "default"; + shutdown-gpios = <&gpl1 0 GPIO_ACTIVE_HIGH>; + device-wakeup-gpios = <&gpx3 1 GPIO_ACTIVE_HIGH>; + host-wakeup-gpios = <&gpx2 6 GPIO_ACTIVE_HIGH>; + }; }; &serial_1 { From 4e77879298541bde7271f1e735933d07fa8ae8bf Mon Sep 17 00:00:00 2001 From: Marek Szyprowski Date: Tue, 27 Oct 2020 15:23:29 +0100 Subject: [PATCH 083/799] ARM: dts: exynos: Enable Bluetooth support for Universal C210 board Add a node for the BCM4330 Bluetooth chip on the serial bus #0 on the Exynos4210-based Universal C210 boards. Signed-off-by: Marek Szyprowski Link: https://lore.kernel.org/r/20201027142330.5121-2-m.szyprowski@samsung.com Signed-off-by: Krzysztof Kozlowski --- .../boot/dts/exynos4210-universal_c210.dts | 29 +++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/arch/arm/boot/dts/exynos4210-universal_c210.dts b/arch/arm/boot/dts/exynos4210-universal_c210.dts index 08284e8f3624..dd44ad2c6ad6 100644 --- a/arch/arm/boot/dts/exynos4210-universal_c210.dts +++ b/arch/arm/boot/dts/exynos4210-universal_c210.dts @@ -532,6 +532,24 @@ }; &pinctrl_1 { + bt_shutdown: bt-shutdown { + samsung,pins = "gpe1-4"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + bt_host_wakeup: bt-host-wakeup { + samsung,pins = "gpx2-6"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + bt_device_wakeup: bt-device-wakeup { + samsung,pins = "gpx3-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + lp3974_irq: lp3974-irq { samsung,pins = "gpx0-7", "gpx2-7"; samsung,pin-pud = ; @@ -608,6 +626,17 @@ status = "okay"; /delete-property/dmas; /delete-property/dma-names; + pinctrl-0 = <&uart0_data &uart0_fctl>; + pinctrl-names = "default"; + + bluetooth { + compatible = "brcm,bcm4330-bt"; + pinctrl-0 = <&bt_shutdown &bt_device_wakeup &bt_host_wakeup>; + pinctrl-names = "default"; + shutdown-gpios = <&gpe1 4 GPIO_ACTIVE_HIGH>; + device-wakeup-gpios = <&gpx3 1 GPIO_ACTIVE_HIGH>; + host-wakeup-gpios = <&gpx2 6 GPIO_ACTIVE_HIGH>; + }; }; &serial_1 { From d35cdc833bf415d855261ebe2c4a6349f882b265 Mon Sep 17 00:00:00 2001 From: Marek Szyprowski Date: Tue, 27 Oct 2020 15:23:30 +0100 Subject: [PATCH 084/799] ARM: dts: exynos: Enable Bluetooth support for Midas board family Add a node for the BCM4334 Bluetooth chip on the serial bus #0 on the Exynos4412-based Midas board family. Signed-off-by: Marek Szyprowski Link: https://lore.kernel.org/r/20201027142330.5121-3-m.szyprowski@samsung.com Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos4412-midas.dtsi | 28 +++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/arch/arm/boot/dts/exynos4412-midas.dtsi b/arch/arm/boot/dts/exynos4412-midas.dtsi index 7e7c243ff196..96287c6ff359 100644 --- a/arch/arm/boot/dts/exynos4412-midas.dtsi +++ b/arch/arm/boot/dts/exynos4412-midas.dtsi @@ -1109,6 +1109,21 @@ samsung,pin-pud = ; }; + bt_shutdown: bt-shutdown { + samsung,pins = "gpl0-6"; + samsung,pin-pud = ; + }; + + bt_host_wakeup: bt-host-wakeup { + samsung,pins = "gpx2-6"; + samsung,pin-pud = ; + }; + + bt_device_wakeup: bt-device-wakeup { + samsung,pins = "gpx3-1"; + samsung,pin-pud = ; + }; + max77686_irq: max77686-irq { samsung,pins = "gpx0-7"; samsung,pin-pud = ; @@ -1386,7 +1401,20 @@ }; &serial_0 { + pinctrl-0 = <&uart0_data &uart0_fctl>; + pinctrl-names = "default"; status = "okay"; + + bluetooth { + compatible = "brcm,bcm4330-bt"; + pinctrl-0 = <&bt_shutdown &bt_device_wakeup &bt_host_wakeup>; + pinctrl-names = "default"; + max-speed = <3000000>; + shutdown-gpios = <&gpl0 6 GPIO_ACTIVE_HIGH>; + device-wakeup-gpios = <&gpx3 1 GPIO_ACTIVE_HIGH>; + host-wakeup-gpios = <&gpx2 6 GPIO_ACTIVE_HIGH>; + clocks = <&max77686 MAX77686_CLK_PMIC>; + }; }; &serial_1 { From 970f6cf2e91465c53dbbf9d80d755a7e8139fedb Mon Sep 17 00:00:00 2001 From: Marek Szyprowski Date: Tue, 27 Oct 2020 21:17:16 +0100 Subject: [PATCH 085/799] ARM: exynos: Simplify code in Exynos3250 CPU core restart path exynos_core_restart() is called by secondary CPU boot procedure, used by CPU hotplug and coupled CPU idle. Replace of_machine_is_compatible() call with a simple SoC revision check. of_machine_is_compatible() function performs a dozen of string comparisons during the full device tree walk, while soc_is_exynos3250() is a simple integer check on SoC revision variable. This change also fixes the following warning: ============================= WARNING: suspicious RCU usage 5.10.0-rc1-00001-g6f65599d1f4f-dirty #1800 Not tainted ----------------------------- ./include/trace/events/lock.h:37 suspicious rcu_dereference_check() usage! other info that might help us debug this: rcu_scheduler_active = 2, debug_locks = 1 RCU used illegally from extended quiescent state! no locks held by swapper/0/0. stack backtrace: CPU: 0 PID: 0 Comm: swapper/0 Not tainted 5.10.0-rc1-00001-g6f65599d1f4f-dirty #1800 Hardware name: Samsung Exynos (Flattened Device Tree) [] (unwind_backtrace) from [] (show_stack+0x10/0x14) [] (show_stack) from [] (dump_stack+0xb4/0xd4) [] (dump_stack) from [] (lock_acquire+0x418/0x584) [] (lock_acquire) from [] (_raw_spin_lock_irqsave+0x4c/0x60) [] (_raw_spin_lock_irqsave) from [] (of_device_is_compatible+0x1c/0x4c) [] (of_device_is_compatible) from [] (exynos_core_restart+0x14/0xb0) [] (exynos_core_restart) from [] (exynos_cpu0_enter_aftr+0x1d0/0x1dc) [] (exynos_cpu0_enter_aftr) from [] (exynos_enter_coupled_lowpower+0x44/0x74) [] (exynos_enter_coupled_lowpower) from [] (cpuidle_enter_state+0x178/0x660) [] (cpuidle_enter_state) from [] (cpuidle_enter_state_coupled+0x35c/0x378) [] (cpuidle_enter_state_coupled) from [] (cpuidle_enter+0x50/0x54) [] (cpuidle_enter) from [] (do_idle+0x224/0x2a4) [] (do_idle) from [] (cpu_startup_entry+0x18/0x1c) [] (cpu_startup_entry) from [] (start_kernel+0x640/0x67c) [] (start_kernel) from [<00000000>] (0x0) Signed-off-by: Marek Szyprowski Link: https://lore.kernel.org/r/20201027201716.15745-1-m.szyprowski@samsung.com Signed-off-by: Krzysztof Kozlowski --- arch/arm/mach-exynos/platsmp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c index d7fedbb2eefe..ea0be59f469a 100644 --- a/arch/arm/mach-exynos/platsmp.c +++ b/arch/arm/mach-exynos/platsmp.c @@ -215,7 +215,7 @@ void exynos_core_restart(u32 core_id) unsigned int timeout = 16; u32 val; - if (!of_machine_is_compatible("samsung,exynos3250")) + if (!soc_is_exynos3250()) return; while (timeout && !pmu_raw_readl(S5P_PMU_SPARE2)) { From fb533fc76d341ab73fc7e3cec0ab012bd2881ca7 Mon Sep 17 00:00:00 2001 From: Eugen Hristev Date: Fri, 16 Oct 2020 10:51:09 +0300 Subject: [PATCH 086/799] ARM: configs: at91: sama5: resync with media changes The media tree Kconfig has changed recently, and a lot of modules were built unintentionally, like the dvb frontends and encoders. Resync the defconfig to build the sama5 drivers and tested sensors. Signed-off-by: Eugen Hristev Signed-off-by: Alexandre Belloni Link: https://lore.kernel.org/r/20201016075109.287506-1-eugen.hristev@microchip.com --- arch/arm/configs/sama5_defconfig | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm/configs/sama5_defconfig b/arch/arm/configs/sama5_defconfig index 037d3a718a60..2c8a621a8f1f 100644 --- a/arch/arm/configs/sama5_defconfig +++ b/arch/arm/configs/sama5_defconfig @@ -153,9 +153,18 @@ CONFIG_REGULATOR_ACT8945A=y CONFIG_REGULATOR_MCP16502=m CONFIG_REGULATOR_PWM=m CONFIG_MEDIA_SUPPORT=y +CONFIG_MEDIA_SUPPORT_FILTER=y +# CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set CONFIG_MEDIA_CAMERA_SUPPORT=y +CONFIG_MEDIA_PLATFORM_SUPPORT=y CONFIG_V4L_PLATFORM_DRIVERS=y +CONFIG_VIDEO_ATMEL_ISC=y CONFIG_VIDEO_ATMEL_ISI=y +CONFIG_VIDEO_OV2640=m +CONFIG_VIDEO_OV5640=m +CONFIG_VIDEO_OV7670=m +CONFIG_VIDEO_OV7740=m +CONFIG_VIDEO_MT9V032=m CONFIG_DRM=y CONFIG_DRM_ATMEL_HLCDC=y CONFIG_DRM_PANEL_SIMPLE=y From c9dc33d13c813e20c6dcfd5a9f54122225ca46bb Mon Sep 17 00:00:00 2001 From: Bartosz Golaszewski Date: Mon, 26 Oct 2020 11:46:18 +0100 Subject: [PATCH 087/799] ARM: dts: at91: at91-sama5d27_som1: fix EEPROM compatible AT24 compatibles require a vendor prefix. Use the default "atmel". Signed-off-by: Bartosz Golaszewski Signed-off-by: Alexandre Belloni Link: https://lore.kernel.org/r/20201026104618.23415-1-brgl@bgdev.pl --- arch/arm/boot/dts/at91-sama5d27_som1.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/at91-sama5d27_som1.dtsi b/arch/arm/boot/dts/at91-sama5d27_som1.dtsi index b1f994c0ae79..1b1163858b1d 100644 --- a/arch/arm/boot/dts/at91-sama5d27_som1.dtsi +++ b/arch/arm/boot/dts/at91-sama5d27_som1.dtsi @@ -100,7 +100,7 @@ status = "okay"; at24@50 { - compatible = "24c02"; + compatible = "atmel,24c02"; reg = <0x50>; pagesize = <8>; }; From 157a5697f6f24aacf8017acd387e3fdc1f4c1950 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 27 Oct 2020 18:09:36 +0100 Subject: [PATCH 088/799] ARM: dts: exynos: adjust node names to DT spec in Exynos3250 boards The Devicetree specification expects device node names to have a generic name, representing the class of a device. Also the convention for node names is to use hyphens, not underscores. No functional changes. Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20201027170947.132725-2-krzk@kernel.org --- arch/arm/boot/dts/exynos3250-artik5.dtsi | 2 +- arch/arm/boot/dts/exynos3250-monk.dts | 8 ++++---- arch/arm/boot/dts/exynos3250-rinato.dts | 8 ++++---- 3 files changed, 9 insertions(+), 9 deletions(-) diff --git a/arch/arm/boot/dts/exynos3250-artik5.dtsi b/arch/arm/boot/dts/exynos3250-artik5.dtsi index 12887b3924af..04290ec4583a 100644 --- a/arch/arm/boot/dts/exynos3250-artik5.dtsi +++ b/arch/arm/boot/dts/exynos3250-artik5.dtsi @@ -76,7 +76,7 @@ samsung,i2c-max-bus-freq = <100000>; status = "okay"; - s2mps14_pmic@66 { + pmic@66 { compatible = "samsung,s2mps14-pmic"; interrupt-parent = <&gpx3>; interrupts = <5 IRQ_TYPE_NONE>; diff --git a/arch/arm/boot/dts/exynos3250-monk.dts b/arch/arm/boot/dts/exynos3250-monk.dts index c1a68e612037..69451566945d 100644 --- a/arch/arm/boot/dts/exynos3250-monk.dts +++ b/arch/arm/boot/dts/exynos3250-monk.dts @@ -34,10 +34,10 @@ reg = <0x0205F000 0x1000>; }; - gpio_keys { + gpio-keys { compatible = "gpio-keys"; - power_key { + power-key { gpios = <&gpx2 7 GPIO_ACTIVE_LOW>; linux,code = ; label = "power key"; @@ -62,7 +62,7 @@ #address-cells = <1>; #size-cells = <0>; - max77836: subpmic@25 { + max77836: pmic@25 { compatible = "maxim,max77836"; interrupt-parent = <&gpx1>; interrupts = <5 IRQ_TYPE_NONE>; @@ -197,7 +197,7 @@ samsung,i2c-max-bus-freq = <100000>; status = "okay"; - s2mps14_pmic@66 { + pmic@66 { compatible = "samsung,s2mps14-pmic"; interrupt-parent = <&gpx0>; interrupts = <7 IRQ_TYPE_NONE>; diff --git a/arch/arm/boot/dts/exynos3250-rinato.dts b/arch/arm/boot/dts/exynos3250-rinato.dts index b55afaaa691e..a26e3e582a7e 100644 --- a/arch/arm/boot/dts/exynos3250-rinato.dts +++ b/arch/arm/boot/dts/exynos3250-rinato.dts @@ -38,10 +38,10 @@ reg = <0x0205F000 0x1000>; }; - gpio_keys { + gpio-keys { compatible = "gpio-keys"; - power_key { + power-key { gpios = <&gpx2 7 GPIO_ACTIVE_LOW>; linux,code = ; label = "power key"; @@ -62,7 +62,7 @@ #address-cells = <1>; #size-cells = <0>; - max77836: subpmic@25 { + max77836: pmic@25 { compatible = "maxim,max77836"; interrupt-parent = <&gpx1>; interrupts = <5 IRQ_TYPE_NONE>; @@ -267,7 +267,7 @@ samsung,i2c-max-bus-freq = <100000>; status = "okay"; - s2mps14_pmic@66 { + pmic@66 { compatible = "samsung,s2mps14-pmic"; interrupt-parent = <&gpx0>; interrupts = <7 IRQ_TYPE_NONE>; From d918633c8acbd42afb694a6d859f449f4bf9d3bf Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 27 Oct 2020 18:09:37 +0100 Subject: [PATCH 089/799] ARM: dts: exynos: adjust node names to DT spec in Exynos4210 boards The Devicetree specification expects device node names to have a generic name, representing the class of a device. Also the convention for node names is to use hyphens, not underscores. No functional changes. Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20201027170947.132725-3-krzk@kernel.org --- arch/arm/boot/dts/exynos4210-i9100.dts | 6 +++--- arch/arm/boot/dts/exynos4210-origen.dts | 4 ++-- arch/arm/boot/dts/exynos4210-smdkv310.dts | 22 +++++++++++----------- arch/arm/boot/dts/exynos4210-trats.dts | 4 ++-- 4 files changed, 18 insertions(+), 18 deletions(-) diff --git a/arch/arm/boot/dts/exynos4210-i9100.dts b/arch/arm/boot/dts/exynos4210-i9100.dts index 5370ee477186..a0c3bab382ae 100644 --- a/arch/arm/boot/dts/exynos4210-i9100.dts +++ b/arch/arm/boot/dts/exynos4210-i9100.dts @@ -329,7 +329,7 @@ pinctrl-0 = <&i2c3_bus>; pinctrl-names = "default"; - mxt224-touchscreen@4a { + touchscreen@4a { compatible = "atmel,maxtouch"; reg = <0x4a>; @@ -348,7 +348,7 @@ pinctrl-0 = <&i2c5_bus>; pinctrl-names = "default"; - max8997_pmic@66 { + pmic@66 { compatible = "maxim,max8997-pmic"; reg = <0x66>; @@ -597,7 +597,7 @@ pinctrl-0 = <&i2c7_bus>; pinctrl-names = "default"; - ak8975@c { + magnetometer@c { compatible = "asahi-kasei,ak8975"; reg = <0x0c>; diff --git a/arch/arm/boot/dts/exynos4210-origen.dts b/arch/arm/boot/dts/exynos4210-origen.dts index 7d2cfbafefb2..1c5394152561 100644 --- a/arch/arm/boot/dts/exynos4210-origen.dts +++ b/arch/arm/boot/dts/exynos4210-origen.dts @@ -43,7 +43,7 @@ enable-active-high; }; - gpio_keys { + gpio-keys { compatible = "gpio-keys"; up { @@ -171,7 +171,7 @@ pinctrl-0 = <&i2c0_bus>; pinctrl-names = "default"; - max8997_pmic@66 { + pmic@66 { compatible = "maxim,max8997-pmic"; reg = <0x66>; interrupt-parent = <&gpx0>; diff --git a/arch/arm/boot/dts/exynos4210-smdkv310.dts b/arch/arm/boot/dts/exynos4210-smdkv310.dts index c5609afa6101..d5797a67bf48 100644 --- a/arch/arm/boot/dts/exynos4210-smdkv310.dts +++ b/arch/arm/boot/dts/exynos4210-smdkv310.dts @@ -90,61 +90,61 @@ pinctrl-0 = <&keypad_rows &keypad_cols>; status = "okay"; - key_1 { + key-1 { keypad,row = <0>; keypad,column = <3>; linux,code = <2>; }; - key_2 { + key-2 { keypad,row = <0>; keypad,column = <4>; linux,code = <3>; }; - key_3 { + key-3 { keypad,row = <0>; keypad,column = <5>; linux,code = <4>; }; - key_4 { + key-4 { keypad,row = <0>; keypad,column = <6>; linux,code = <5>; }; - key_5 { + key-5 { keypad,row = <0>; keypad,column = <7>; linux,code = <6>; }; - key_a { + key-a { keypad,row = <1>; keypad,column = <3>; linux,code = <30>; }; - key_b { + key-b { keypad,row = <1>; keypad,column = <4>; linux,code = <48>; }; - key_c { + key-c { keypad,row = <1>; keypad,column = <5>; linux,code = <46>; }; - key_d { + key-d { keypad,row = <1>; keypad,column = <6>; linux,code = <32>; }; - key_e { + key-e { keypad,row = <1>; keypad,column = <7>; linux,code = <18>; @@ -200,7 +200,7 @@ cs-gpios = <&gpc1 2 GPIO_ACTIVE_HIGH>; status = "okay"; - w25x80@0 { + flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "w25x80"; diff --git a/arch/arm/boot/dts/exynos4210-trats.dts b/arch/arm/boot/dts/exynos4210-trats.dts index eb6ca2a74cc0..d2406c9146b8 100644 --- a/arch/arm/boot/dts/exynos4210-trats.dts +++ b/arch/arm/boot/dts/exynos4210-trats.dts @@ -263,7 +263,7 @@ pinctrl-names = "default"; status = "okay"; - mms114-touchscreen@48 { + touchscreen@48 { compatible = "melfas,mms114"; reg = <0x48>; interrupt-parent = <&gpx0>; @@ -283,7 +283,7 @@ pinctrl-names = "default"; status = "okay"; - max8997_pmic@66 { + pmic@66 { compatible = "maxim,max8997-pmic"; reg = <0x66>; From 43552e6d5a6109df05ea038f512a20b45ca5010c Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 27 Oct 2020 18:09:38 +0100 Subject: [PATCH 090/799] ARM: dts: exynos: override GPIO keys node by label in Exynos4412 Odroid family Using full paths to extend or override a device tree node is error prone. If there was a typo error, a new node will be created instead of extending the existing node. This will lead to run-time errors that could be hard to detect. A mistyped label on the other hand, will cause a dtc compile error (during build time). Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20201027170947.132725-4-krzk@kernel.org --- .../boot/dts/exynos4412-odroid-common.dtsi | 2 +- arch/arm/boot/dts/exynos4412-odroidx.dts | 24 +++++++++---------- 2 files changed, 13 insertions(+), 13 deletions(-) diff --git a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi index ab291cec650a..4c77cd4044f2 100644 --- a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi +++ b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi @@ -22,7 +22,7 @@ reg = <0x0204F000 0x1000>; }; - gpio_keys { + gpio_keys: gpio-keys { compatible = "gpio-keys"; pinctrl-names = "default"; pinctrl-0 = <&gpio_power_key>; diff --git a/arch/arm/boot/dts/exynos4412-odroidx.dts b/arch/arm/boot/dts/exynos4412-odroidx.dts index 3ea2a0101e80..68fe88074d1d 100644 --- a/arch/arm/boot/dts/exynos4412-odroidx.dts +++ b/arch/arm/boot/dts/exynos4412-odroidx.dts @@ -36,18 +36,6 @@ }; }; - gpio_keys { - pinctrl-0 = <&gpio_power_key &gpio_home_key>; - - home_key { - gpios = <&gpx2 2 GPIO_ACTIVE_HIGH>; - linux,code = ; - label = "home key"; - debounce-interval = <10>; - wakeup-source; - }; - }; - regulator_p3v3 { compatible = "regulator-fixed"; regulator-name = "p3v3_en"; @@ -76,6 +64,18 @@ phy-names = "hsic0"; }; +&gpio_keys { + pinctrl-0 = <&gpio_power_key &gpio_home_key>; + + home-key { + gpios = <&gpx2 2 GPIO_ACTIVE_HIGH>; + linux,code = ; + label = "home key"; + debounce-interval = <10>; + wakeup-source; + }; +}; + &mshc_0 { vqmmc-supply = <&buck8_reg>; }; From 108463f568135255e1bd4847f66d41a2c1665920 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 27 Oct 2020 18:09:39 +0100 Subject: [PATCH 091/799] ARM: dts: exynos: adjust node names to DT spec in Exynos4412 boards The Devicetree specification expects device node names to have a generic name, representing the class of a device. Also the convention for node names is to use hyphens, not underscores. No functional changes. Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20201027170947.132725-5-krzk@kernel.org --- arch/arm/boot/dts/exynos4412-galaxy-s3.dtsi | 8 ++++---- arch/arm/boot/dts/exynos4412-itop-elite.dts | 2 +- .../boot/dts/exynos4412-itop-scp-core.dtsi | 2 +- arch/arm/boot/dts/exynos4412-midas.dtsi | 14 ++++++------- arch/arm/boot/dts/exynos4412-n710x.dts | 2 +- .../boot/dts/exynos4412-odroid-common.dtsi | 8 ++++---- arch/arm/boot/dts/exynos4412-odroidx.dts | 4 ++-- arch/arm/boot/dts/exynos4412-origen.dts | 14 ++++++------- arch/arm/boot/dts/exynos4412-smdk4412.dts | 20 +++++++++---------- 9 files changed, 37 insertions(+), 37 deletions(-) diff --git a/arch/arm/boot/dts/exynos4412-galaxy-s3.dtsi b/arch/arm/boot/dts/exynos4412-galaxy-s3.dtsi index 89ed81fb348d..912c78e9ce8c 100644 --- a/arch/arm/boot/dts/exynos4412-galaxy-s3.dtsi +++ b/arch/arm/boot/dts/exynos4412-galaxy-s3.dtsi @@ -15,7 +15,7 @@ i2c10 = &i2c_cm36651; }; - aat1290 { + led-controller { compatible = "skyworks,aat1290"; flen-gpios = <&gpj1 1 GPIO_ACTIVE_HIGH>; enset-gpios = <&gpj1 2 GPIO_ACTIVE_HIGH>; @@ -60,7 +60,7 @@ #size-cells = <0>; status = "okay"; - ak8975@c { + magnetometer@c { compatible = "asahi-kasei,ak8975"; reg = <0x0c>; gpios = <&gpj0 7 GPIO_ACTIVE_HIGH>; @@ -75,7 +75,7 @@ #address-cells = <1>; #size-cells = <0>; - cm36651@18 { + light-sensor@18 { compatible = "capella,cm36651"; reg = <0x18>; interrupt-parent = <&gpx0>; @@ -133,7 +133,7 @@ }; &i2c_3 { - mms114-touchscreen@48 { + touchscreen@48 { compatible = "melfas,mms114"; reg = <0x48>; interrupt-parent = <&gpm2>; diff --git a/arch/arm/boot/dts/exynos4412-itop-elite.dts b/arch/arm/boot/dts/exynos4412-itop-elite.dts index f6d0a5f5d339..47431307cb3c 100644 --- a/arch/arm/boot/dts/exynos4412-itop-elite.dts +++ b/arch/arm/boot/dts/exynos4412-itop-elite.dts @@ -175,7 +175,7 @@ pinctrl-names = "default"; status = "okay"; - codec: wm8960@1a { + codec: audio-codec@1a { compatible = "wlf,wm8960"; reg = <0x1a>; clocks = <&pmu_system_controller 0>; diff --git a/arch/arm/boot/dts/exynos4412-itop-scp-core.dtsi b/arch/arm/boot/dts/exynos4412-itop-scp-core.dtsi index dfceb155b3a7..4583d342af39 100644 --- a/arch/arm/boot/dts/exynos4412-itop-scp-core.dtsi +++ b/arch/arm/boot/dts/exynos4412-itop-scp-core.dtsi @@ -134,7 +134,7 @@ pinctrl-names = "default"; status = "okay"; - s5m8767: s5m8767-pmic@66 { + s5m8767: pmic@66 { compatible = "samsung,s5m8767-pmic"; reg = <0x66>; diff --git a/arch/arm/boot/dts/exynos4412-midas.dtsi b/arch/arm/boot/dts/exynos4412-midas.dtsi index 96287c6ff359..1721705c280d 100644 --- a/arch/arm/boot/dts/exynos4412-midas.dtsi +++ b/arch/arm/boot/dts/exynos4412-midas.dtsi @@ -171,7 +171,7 @@ #size-cells = <0>; status = "okay"; - max77693@66 { + pmic@66 { compatible = "maxim,max77693"; interrupt-parent = <&gpx1>; interrupts = <5 IRQ_TYPE_EDGE_FALLING>; @@ -220,7 +220,7 @@ #size-cells = <0>; status = "okay"; - max77693-fuel-gauge@36 { + fuel-gauge@36 { compatible = "maxim,max17047"; interrupt-parent = <&gpx2>; interrupts = <3 IRQ_TYPE_EDGE_FALLING>; @@ -550,7 +550,7 @@ pinctrl-names = "default"; status = "okay"; - s5c73m3: s5c73m3@3c { + s5c73m3: image-sensor@3c { compatible = "samsung,s5c73m3"; reg = <0x3c>; xshutdown-gpios = <&gpf1 3 GPIO_ACTIVE_LOW>; /* ISP_RESET */ @@ -577,7 +577,7 @@ pinctrl-0 = <&fimc_is_i2c1>; pinctrl-names = "default"; - s5k6a3@10 { + image-sensor@10 { compatible = "samsung,s5k6a3"; reg = <0x10>; svdda-supply = <&cam_io_reg>; @@ -616,7 +616,7 @@ pinctrl-names = "default"; status = "okay"; - wm1811: wm1811@1a { + wm1811: audio-codec@1a { compatible = "wlf,wm1811"; reg = <0x1a>; clocks = <&pmu_system_controller 0>, @@ -665,7 +665,7 @@ pinctrl-names = "default"; status = "okay"; - max77686: max77686_pmic@9 { + max77686: pmic@9 { compatible = "maxim,max77686"; interrupt-parent = <&gpx0>; interrupts = <7 IRQ_TYPE_NONE>; @@ -1435,7 +1435,7 @@ cs-gpios = <&gpb 5 GPIO_ACTIVE_HIGH>; status = "okay"; - s5c73m3_spi: s5c73m3@0 { + s5c73m3_spi: image-sensor@0 { compatible = "samsung,s5c73m3"; spi-max-frequency = <50000000>; reg = <0>; diff --git a/arch/arm/boot/dts/exynos4412-n710x.dts b/arch/arm/boot/dts/exynos4412-n710x.dts index a47b7f35fc80..c49dbb7847b8 100644 --- a/arch/arm/boot/dts/exynos4412-n710x.dts +++ b/arch/arm/boot/dts/exynos4412-n710x.dts @@ -45,7 +45,7 @@ pinctrl-names = "default"; status = "okay"; - mms152-touchscreen@48 { + touchscreen@48 { compatible = "melfas,mms152"; reg = <0x48>; interrupt-parent = <&gpm2>; diff --git a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi index 4c77cd4044f2..1ca9d8b5f868 100644 --- a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi +++ b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi @@ -27,7 +27,7 @@ pinctrl-names = "default"; pinctrl-0 = <&gpio_power_key>; - power_key { + power-key { gpios = <&gpx1 3 GPIO_ACTIVE_LOW>; linux,code = ; label = "power key"; @@ -172,7 +172,7 @@ }; &pinctrl_1 { - gpio_power_key: power_key { + gpio_power_key: power-key { samsung,pins = "gpx1-3"; samsung,pin-pud = ; }; @@ -267,7 +267,7 @@ samsung,i2c-max-bus-freq = <400000>; status = "okay"; - usb3503: usb3503@8 { + usb3503: usb-hub@8 { compatible = "smsc,usb3503"; reg = <0x08>; @@ -493,7 +493,7 @@ &i2c_1 { status = "okay"; - max98090: max98090@10 { + max98090: audio-codec@10 { compatible = "maxim,max98090"; reg = <0x10>; interrupt-parent = <&gpx0>; diff --git a/arch/arm/boot/dts/exynos4412-odroidx.dts b/arch/arm/boot/dts/exynos4412-odroidx.dts index 68fe88074d1d..46381e9097f4 100644 --- a/arch/arm/boot/dts/exynos4412-odroidx.dts +++ b/arch/arm/boot/dts/exynos4412-odroidx.dts @@ -36,7 +36,7 @@ }; }; - regulator_p3v3 { + regulator-1 { compatible = "regulator-fixed"; regulator-name = "p3v3_en"; regulator-min-microvolt = <3300000>; @@ -81,7 +81,7 @@ }; &pinctrl_1 { - gpio_home_key: home_key { + gpio_home_key: home-key { samsung,pins = "gpx2-2"; samsung,pin-pud = ; }; diff --git a/arch/arm/boot/dts/exynos4412-origen.dts b/arch/arm/boot/dts/exynos4412-origen.dts index c2e793b69e7d..e1f6de53e20e 100644 --- a/arch/arm/boot/dts/exynos4412-origen.dts +++ b/arch/arm/boot/dts/exynos4412-origen.dts @@ -116,7 +116,7 @@ pinctrl-names = "default"; status = "okay"; - s5m8767_pmic@66 { + pmic@66 { compatible = "samsung,s5m8767-pmic"; reg = <0x66>; @@ -453,37 +453,37 @@ pinctrl-names = "default"; status = "okay"; - key_home { + key-home { keypad,row = <0>; keypad,column = <0>; linux,code = ; }; - key_down { + key-down { keypad,row = <0>; keypad,column = <1>; linux,code = ; }; - key_up { + key-up { keypad,row = <1>; keypad,column = <0>; linux,code = ; }; - key_menu { + key-menu { keypad,row = <1>; keypad,column = <1>; linux,code = ; }; - key_back { + key-back { keypad,row = <2>; keypad,column = <0>; linux,code = ; }; - key_enter { + key-enter { keypad,row = <2>; keypad,column = <1>; linux,code = ; diff --git a/arch/arm/boot/dts/exynos4412-smdk4412.dts b/arch/arm/boot/dts/exynos4412-smdk4412.dts index 49971203a8aa..cc99b955af0c 100644 --- a/arch/arm/boot/dts/exynos4412-smdk4412.dts +++ b/arch/arm/boot/dts/exynos4412-smdk4412.dts @@ -71,61 +71,61 @@ pinctrl-names = "default"; status = "okay"; - key_1 { + key-1 { keypad,row = <1>; keypad,column = <3>; linux,code = <2>; }; - key_2 { + key-2 { keypad,row = <1>; keypad,column = <4>; linux,code = <3>; }; - key_3 { + key-3 { keypad,row = <1>; keypad,column = <5>; linux,code = <4>; }; - key_4 { + key-4 { keypad,row = <1>; keypad,column = <6>; linux,code = <5>; }; - key_5 { + key-5 { keypad,row = <1>; keypad,column = <7>; linux,code = <6>; }; - key_A { + key-A { keypad,row = <2>; keypad,column = <6>; linux,code = <30>; }; - key_B { + key-B { keypad,row = <2>; keypad,column = <7>; linux,code = <48>; }; - key_C { + key-C { keypad,row = <0>; keypad,column = <5>; linux,code = <46>; }; - key_D { + key-D { keypad,row = <2>; keypad,column = <5>; linux,code = <32>; }; - key_E { + key-E { keypad,row = <0>; keypad,column = <7>; linux,code = <18>; From 2d29d03003017a7a556519d2fbcbbffcee0be319 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 27 Oct 2020 18:09:40 +0100 Subject: [PATCH 092/799] ARM: dts: exynos: remove redundant status=okay in Exynos4412 boards New nodes are enabled by default, so status=okay is not needed for them. Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20201027170947.132725-6-krzk@kernel.org --- arch/arm/boot/dts/exynos4412-galaxy-s3.dtsi | 1 - arch/arm/boot/dts/exynos4412-midas.dtsi | 3 --- 2 files changed, 4 deletions(-) diff --git a/arch/arm/boot/dts/exynos4412-galaxy-s3.dtsi b/arch/arm/boot/dts/exynos4412-galaxy-s3.dtsi index 912c78e9ce8c..c14e37dc3a9b 100644 --- a/arch/arm/boot/dts/exynos4412-galaxy-s3.dtsi +++ b/arch/arm/boot/dts/exynos4412-galaxy-s3.dtsi @@ -58,7 +58,6 @@ i2c-gpio,delay-us = <2>; #address-cells = <1>; #size-cells = <0>; - status = "okay"; magnetometer@c { compatible = "asahi-kasei,ak8975"; diff --git a/arch/arm/boot/dts/exynos4412-midas.dtsi b/arch/arm/boot/dts/exynos4412-midas.dtsi index 1721705c280d..2be1db0b2387 100644 --- a/arch/arm/boot/dts/exynos4412-midas.dtsi +++ b/arch/arm/boot/dts/exynos4412-midas.dtsi @@ -169,7 +169,6 @@ i2c-gpio,delay-us = <2>; #address-cells = <1>; #size-cells = <0>; - status = "okay"; pmic@66 { compatible = "maxim,max77693"; @@ -218,7 +217,6 @@ i2c-gpio,delay-us = <2>; #address-cells = <1>; #size-cells = <0>; - status = "okay"; fuel-gauge@36 { compatible = "maxim,max17047"; @@ -262,7 +260,6 @@ pinctrl-0 = <&i2c_mhl_bus>; pinctrl-names = "default"; - status = "okay"; sii9234: hdmi-bridge@39 { compatible = "sil,sii9234"; From 5a1323023fb16c0b04efb24a4c85e5f2663172d8 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 27 Oct 2020 18:09:41 +0100 Subject: [PATCH 093/799] ARM: dts: exynos: adjust node names to DT spec in Exynos5250 boards The Devicetree specification expects device node names to have a generic name, representing the class of a device. Also the convention for node names is to use hyphens, not underscores. No functional changes. Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20201027170947.132725-7-krzk@kernel.org --- arch/arm/boot/dts/exynos5250-arndale.dts | 6 +++--- arch/arm/boot/dts/exynos5250-smdk5250.dts | 4 ++-- arch/arm/boot/dts/exynos5250-snow-common.dtsi | 4 ++-- arch/arm/boot/dts/exynos5250-snow-rev5.dts | 2 +- arch/arm/boot/dts/exynos5250-snow.dts | 2 +- arch/arm/boot/dts/exynos5250-spring.dts | 2 +- 6 files changed, 10 insertions(+), 10 deletions(-) diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts b/arch/arm/boot/dts/exynos5250-arndale.dts index 79546f11af26..a161f6237c7f 100644 --- a/arch/arm/boot/dts/exynos5250-arndale.dts +++ b/arch/arm/boot/dts/exynos5250-arndale.dts @@ -27,7 +27,7 @@ stdout-path = "serial2:115200n8"; }; - gpio_keys { + gpio-keys { compatible = "gpio-keys"; menu { @@ -211,7 +211,7 @@ samsung,i2c-max-bus-freq = <20000>; samsung,i2c-slave-addr = <0x66>; - s5m8767_pmic@66 { + pmic@66 { compatible = "samsung,s5m8767-pmic"; reg = <0x66>; interrupt-parent = <&gpx3>; @@ -511,7 +511,7 @@ &i2c_3 { status = "okay"; - wm1811: codec@1a { + wm1811: audio-codec@1a { compatible = "wlf,wm1811"; reg = <0x1a>; clocks = <&i2s0 CLK_I2S_CDCLK>; diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts b/arch/arm/boot/dts/exynos5250-smdk5250.dts index 186790f39e4d..8b5a79a8720c 100644 --- a/arch/arm/boot/dts/exynos5250-smdk5250.dts +++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts @@ -290,7 +290,7 @@ reg = <0x51>; }; - wm8994: wm8994@1a { + wm8994: audio-codec@1a { compatible = "wlf,wm8994"; reg = <0x1a>; @@ -385,7 +385,7 @@ status = "okay"; cs-gpios = <&gpa2 5 GPIO_ACTIVE_HIGH>; - w25q80bw@0 { + flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "w25x80"; diff --git a/arch/arm/boot/dts/exynos5250-snow-common.dtsi b/arch/arm/boot/dts/exynos5250-snow-common.dtsi index c952a615148e..6635f6184051 100644 --- a/arch/arm/boot/dts/exynos5250-snow-common.dtsi +++ b/arch/arm/boot/dts/exynos5250-snow-common.dtsi @@ -217,7 +217,7 @@ }; }; - mmc3_pwrseq: mmc3_pwrseq { + mmc3_pwrseq: mmc3-pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&gpx0 2 GPIO_ACTIVE_LOW>, /* WIFI_RSTn */ <&gpx0 1 GPIO_ACTIVE_LOW>; /* WIFI_EN */ @@ -289,7 +289,7 @@ samsung,i2c-sda-delay = <100>; samsung,i2c-max-bus-freq = <378000>; - max77686: max77686@9 { + max77686: pmic@9 { compatible = "maxim,max77686"; interrupt-parent = <&gpx3>; interrupts = <2 IRQ_TYPE_NONE>; diff --git a/arch/arm/boot/dts/exynos5250-snow-rev5.dts b/arch/arm/boot/dts/exynos5250-snow-rev5.dts index 7cbfc6f1f4b8..0822b778c035 100644 --- a/arch/arm/boot/dts/exynos5250-snow-rev5.dts +++ b/arch/arm/boot/dts/exynos5250-snow-rev5.dts @@ -32,7 +32,7 @@ }; &i2c_7 { - max98090: codec@10 { + max98090: audio-codec@10 { compatible = "maxim,max98090"; reg = <0x10>; interrupts = <4 IRQ_TYPE_NONE>; diff --git a/arch/arm/boot/dts/exynos5250-snow.dts b/arch/arm/boot/dts/exynos5250-snow.dts index 75fdc5e6d423..9946dce54d74 100644 --- a/arch/arm/boot/dts/exynos5250-snow.dts +++ b/arch/arm/boot/dts/exynos5250-snow.dts @@ -30,7 +30,7 @@ }; &i2c_7 { - max98095: codec@11 { + max98095: audio-codec@11 { compatible = "maxim,max98095"; reg = <0x11>; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/exynos5250-spring.dts b/arch/arm/boot/dts/exynos5250-spring.dts index a92ade33779c..9d2baea62d0d 100644 --- a/arch/arm/boot/dts/exynos5250-spring.dts +++ b/arch/arm/boot/dts/exynos5250-spring.dts @@ -105,7 +105,7 @@ samsung,i2c-sda-delay = <100>; samsung,i2c-max-bus-freq = <378000>; - s5m8767-pmic@66 { + pmic@66 { compatible = "samsung,s5m8767-pmic"; reg = <0x66>; interrupt-parent = <&gpx3>; From e5fbceb07e3e8e81226b22326756649b127aa78c Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 27 Oct 2020 18:09:42 +0100 Subject: [PATCH 094/799] ARM: dts: exynos: adjust node names to DT spec in Odroid XU The Devicetree specification expects device node names to have a generic name, representing the class of a device. Also the convention for node names is to use hyphens, not underscores. No functional changes. Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20201027170947.132725-8-krzk@kernel.org --- arch/arm/boot/dts/exynos5410-odroidxu.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/exynos5410-odroidxu.dts b/arch/arm/boot/dts/exynos5410-odroidxu.dts index dd300cea6a20..40cb0727aea1 100644 --- a/arch/arm/boot/dts/exynos5410-odroidxu.dts +++ b/arch/arm/boot/dts/exynos5410-odroidxu.dts @@ -500,7 +500,7 @@ &i2c_1 { status = "okay"; - max98090: max98090@10 { + max98090: audio-codec@10 { compatible = "maxim,max98090"; reg = <0x10>; interrupt-parent = <&gpj3>; From 77c91853a65f689cf4198644452fed151a83e8fd Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 27 Oct 2020 18:09:43 +0100 Subject: [PATCH 095/799] ARM: dts: exynos: adjust node names to DT spec in Exynos542x boards The Devicetree specification expects device node names to have a generic name, representing the class of a device. Also the convention for node names is to use hyphens, not underscores. No functional changes. Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20201027170947.132725-9-krzk@kernel.org --- arch/arm/boot/dts/exynos5420-arndale-octa.dts | 4 ++-- arch/arm/boot/dts/exynos5420-peach-pit.dts | 6 +++--- arch/arm/boot/dts/exynos5420-smdk5420.dts | 2 +- arch/arm/boot/dts/exynos5422-odroid-core.dtsi | 2 +- arch/arm/boot/dts/exynos5422-odroidxu3-audio.dtsi | 2 +- arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi | 4 ++-- arch/arm/boot/dts/exynos5422-odroidxu3.dts | 8 ++++---- arch/arm/boot/dts/exynos5800-peach-pi.dts | 4 ++-- 8 files changed, 16 insertions(+), 16 deletions(-) diff --git a/arch/arm/boot/dts/exynos5420-arndale-octa.dts b/arch/arm/boot/dts/exynos5420-arndale-octa.dts index dd7f8385d81e..bf457d0c02eb 100644 --- a/arch/arm/boot/dts/exynos5420-arndale-octa.dts +++ b/arch/arm/boot/dts/exynos5420-arndale-octa.dts @@ -39,7 +39,7 @@ }; }; - gpio_keys { + gpio-keys { compatible = "gpio-keys"; wakeup { @@ -344,7 +344,7 @@ &hsi2c_4 { status = "okay"; - s2mps11_pmic@66 { + pmic@66 { compatible = "samsung,s2mps11-pmic"; reg = <0x66>; diff --git a/arch/arm/boot/dts/exynos5420-peach-pit.dts b/arch/arm/boot/dts/exynos5420-peach-pit.dts index 2bcbdf8a39bf..315b3dc9c017 100644 --- a/arch/arm/boot/dts/exynos5420-peach-pit.dts +++ b/arch/arm/boot/dts/exynos5420-peach-pit.dts @@ -138,7 +138,7 @@ }; }; - mmc1_pwrseq: mmc1_pwrseq { + mmc1_pwrseq: mmc1-pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&gpx0 0 GPIO_ACTIVE_LOW>; /* WIFI_EN */ clocks = <&max77802 MAX77802_CLK_32K_CP>; @@ -205,7 +205,7 @@ status = "okay"; clock-frequency = <400000>; - max77802: max77802-pmic@9 { + max77802: pmic@9 { compatible = "maxim,max77802"; interrupt-parent = <&gpx3>; interrupts = <1 IRQ_TYPE_NONE>; @@ -615,7 +615,7 @@ status = "okay"; clock-frequency = <400000>; - max98090: codec@10 { + max98090: audio-codec@10 { compatible = "maxim,max98090"; reg = <0x10>; interrupts = <2 IRQ_TYPE_NONE>; diff --git a/arch/arm/boot/dts/exynos5420-smdk5420.dts b/arch/arm/boot/dts/exynos5420-smdk5420.dts index 4e49d8095b29..d506da9fa661 100644 --- a/arch/arm/boot/dts/exynos5420-smdk5420.dts +++ b/arch/arm/boot/dts/exynos5420-smdk5420.dts @@ -129,7 +129,7 @@ &hsi2c_4 { status = "okay"; - s2mps11_pmic@66 { + pmic@66 { compatible = "samsung,s2mps11-pmic"; reg = <0x66>; diff --git a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi index b1cf9414ce17..25fb6331c75e 100644 --- a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi +++ b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi @@ -503,7 +503,7 @@ &hsi2c_4 { status = "okay"; - s2mps11_pmic@66 { + pmic@66 { compatible = "samsung,s2mps11-pmic"; reg = <0x66>; samsung,s2mps11-acokb-ground; diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3-audio.dtsi b/arch/arm/boot/dts/exynos5422-odroidxu3-audio.dtsi index b5ec4f47eb3a..86b96f9706db 100644 --- a/arch/arm/boot/dts/exynos5422-odroidxu3-audio.dtsi +++ b/arch/arm/boot/dts/exynos5422-odroidxu3-audio.dtsi @@ -40,7 +40,7 @@ &hsi2c_5 { status = "okay"; - max98090: max98090@10 { + max98090: audio-codec@10 { compatible = "maxim,max98090"; reg = <0x10>; interrupt-parent = <&gpx3>; diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi b/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi index 5da2d81e3be2..e35af40a55cb 100644 --- a/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi +++ b/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi @@ -13,12 +13,12 @@ #include "exynos5422-odroid-core.dtsi" / { - gpio_keys { + gpio-keys { compatible = "gpio-keys"; pinctrl-names = "default"; pinctrl-0 = <&power_key>; - power_key { + power-key { /* * The power button (SW2) is connected to the PWRON * pin (active high) of the S2MPS11 PMIC, which acts diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3.dts b/arch/arm/boot/dts/exynos5422-odroidxu3.dts index db0bc17a667b..7c588407f931 100644 --- a/arch/arm/boot/dts/exynos5422-odroidxu3.dts +++ b/arch/arm/boot/dts/exynos5422-odroidxu3.dts @@ -21,28 +21,28 @@ status = "okay"; /* A15 cluster: VDD_ARM */ - ina231@40 { + power-sensor@40 { compatible = "ti,ina231"; reg = <0x40>; shunt-resistor = <10000>; }; /* memory: VDD_MEM */ - ina231@41 { + power-sensor@41 { compatible = "ti,ina231"; reg = <0x41>; shunt-resistor = <10000>; }; /* GPU: VDD_G3D */ - ina231@44 { + power-sensor@44 { compatible = "ti,ina231"; reg = <0x44>; shunt-resistor = <10000>; }; /* A7 cluster: VDD_KFC */ - ina231@45 { + power-sensor@45 { compatible = "ti,ina231"; reg = <0x45>; shunt-resistor = <10000>; diff --git a/arch/arm/boot/dts/exynos5800-peach-pi.dts b/arch/arm/boot/dts/exynos5800-peach-pi.dts index 60ab0effe474..0ce3443d39a8 100644 --- a/arch/arm/boot/dts/exynos5800-peach-pi.dts +++ b/arch/arm/boot/dts/exynos5800-peach-pi.dts @@ -138,7 +138,7 @@ }; }; - mmc1_pwrseq: mmc1_pwrseq { + mmc1_pwrseq: mmc1-pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&gpx0 0 GPIO_ACTIVE_LOW>; /* WIFI_EN */ clocks = <&max77802 MAX77802_CLK_32K_CP>; @@ -214,7 +214,7 @@ status = "okay"; clock-frequency = <400000>; - max77802: max77802-pmic@9 { + max77802: pmic@9 { compatible = "maxim,max77802"; interrupt-parent = <&gpx3>; interrupts = <1 IRQ_TYPE_NONE>; From b04544ac0d1f2a51e0f3234045343aa741d64e7b Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 27 Oct 2020 18:09:44 +0100 Subject: [PATCH 096/799] ARM: dts: s5pv210: adjust node names to DT spec The Devicetree specification expects device node names to have a generic name, representing the class of a device. Also the convention for node names is to use hyphens, not underscores. No functional changes. Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20201027170947.132725-10-krzk@kernel.org --- arch/arm/boot/dts/s5pv210-aquila.dts | 12 ++++++------ arch/arm/boot/dts/s5pv210-aries.dtsi | 4 ++-- arch/arm/boot/dts/s5pv210-goni.dts | 14 +++++++------- arch/arm/boot/dts/s5pv210-smdkv210.dts | 20 ++++++++++---------- 4 files changed, 25 insertions(+), 25 deletions(-) diff --git a/arch/arm/boot/dts/s5pv210-aquila.dts b/arch/arm/boot/dts/s5pv210-aquila.dts index 8e57e5a1f0c5..6423348034b6 100644 --- a/arch/arm/boot/dts/s5pv210-aquila.dts +++ b/arch/arm/boot/dts/s5pv210-aquila.dts @@ -277,37 +277,37 @@ <&keypad_col0>, <&keypad_col1>, <&keypad_col2>; status = "okay"; - key_1 { + key-1 { keypad,row = <0>; keypad,column = <1>; linux,code = ; }; - key_2 { + key-2 { keypad,row = <0>; keypad,column = <2>; linux,code = ; }; - key_3 { + key-3 { keypad,row = <1>; keypad,column = <1>; linux,code = ; }; - key_4 { + key-4 { keypad,row = <1>; keypad,column = <2>; linux,code = ; }; - key_5 { + key-5 { keypad,row = <2>; keypad,column = <1>; linux,code = ; }; - key_6 { + key-6 { keypad,row = <2>; keypad,column = <2>; linux,code = ; diff --git a/arch/arm/boot/dts/s5pv210-aries.dtsi b/arch/arm/boot/dts/s5pv210-aries.dtsi index bd4450dbdcb6..91ecad85abfc 100644 --- a/arch/arm/boot/dts/s5pv210-aries.dtsi +++ b/arch/arm/boot/dts/s5pv210-aries.dtsi @@ -54,7 +54,7 @@ clock-frequency = <32768>; }; - bt_codec: bt_sco { + bt_codec: bt-sco { compatible = "linux,bt-sco"; #sound-dai-cells = <0>; }; @@ -113,7 +113,7 @@ pinctrl-names = "default"; pinctrl-0 = <&sound_i2c_pins>; - wm8994: wm8994@1a { + wm8994: audio-codec@1a { compatible = "wlf,wm8994"; reg = <0x1a>; diff --git a/arch/arm/boot/dts/s5pv210-goni.dts b/arch/arm/boot/dts/s5pv210-goni.dts index ad8d5d2fa32d..5c1e12d39747 100644 --- a/arch/arm/boot/dts/s5pv210-goni.dts +++ b/arch/arm/boot/dts/s5pv210-goni.dts @@ -259,37 +259,37 @@ <&keypad_col0>, <&keypad_col1>, <&keypad_col2>; status = "okay"; - key_1 { + key-1 { keypad,row = <0>; keypad,column = <1>; linux,code = ; }; - key_2 { + key-2 { keypad,row = <0>; keypad,column = <2>; linux,code = ; }; - key_3 { + key-3 { keypad,row = <1>; keypad,column = <1>; linux,code = ; }; - key_4 { + key-4 { keypad,row = <1>; keypad,column = <2>; linux,code = ; }; - key_5 { + key-5 { keypad,row = <2>; keypad,column = <1>; linux,code = ; }; - key_6 { + key-6 { keypad,row = <2>; keypad,column = <2>; linux,code = ; @@ -353,7 +353,7 @@ samsung,i2c-slave-addr = <0x10>; status = "okay"; - tsp@4a { + touchscreen@4a { compatible = "atmel,maxtouch"; reg = <0x4a>; interrupt-parent = <&gpj0>; diff --git a/arch/arm/boot/dts/s5pv210-smdkv210.dts b/arch/arm/boot/dts/s5pv210-smdkv210.dts index 7459e41e8ef1..fbae768d65e2 100644 --- a/arch/arm/boot/dts/s5pv210-smdkv210.dts +++ b/arch/arm/boot/dts/s5pv210-smdkv210.dts @@ -76,61 +76,61 @@ <&keypad_col6>, <&keypad_col7>; status = "okay"; - key_1 { + key-1 { keypad,row = <0>; keypad,column = <3>; linux,code = ; }; - key_2 { + key-2 { keypad,row = <0>; keypad,column = <4>; linux,code = ; }; - key_3 { + key-3 { keypad,row = <0>; keypad,column = <5>; linux,code = ; }; - key_4 { + key-4 { keypad,row = <0>; keypad,column = <6>; linux,code = ; }; - key_5 { + key-5 { keypad,row = <0 >; keypad,column = <7>; linux,code = ; }; - key_6 { + key-6 { keypad,row = <1>; keypad,column = <3>; linux,code = ; }; - key_7 { + key-7 { keypad,row = <1>; keypad,column = <4>; linux,code = ; }; - key_8 { + key-8 { keypad,row = <1>; keypad,column = <5>; linux,code = ; }; - key_9 { + key-9 { keypad,row = <1>; keypad,column = <6>; linux,code = ; }; - key_10 { + key-10 { keypad,row = <1>; keypad,column = <7>; linux,code = ; From a01f7a96a9b0069d1cf9dd1c59d279e497cecdea Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 27 Oct 2020 18:09:45 +0100 Subject: [PATCH 097/799] arm64: dts: exynos: adjust node names to DT spec in Exynos5433 TM2 The Devicetree specification expects device node names to have a generic name, representing the class of a device. Also the convention for node names is to use hyphens, not underscores. No functional changes. Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20201027170947.132725-11-krzk@kernel.org --- arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi b/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi index 829fea23d4ab..01ab886fd3e9 100644 --- a/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi @@ -94,7 +94,7 @@ #size-cells = <0>; status = "okay"; - max98504: max98504@31 { + max98504: amplifier@31 { compatible = "maxim,max98504"; reg = <0x31>; maxim,rx-path = <1>; @@ -386,7 +386,7 @@ status = "okay"; clock-frequency = <2500000>; - s2mps13-pmic@66 { + pmic@66 { compatible = "samsung,s2mps13-pmic"; interrupt-parent = <&gpa0>; interrupts = <7 IRQ_TYPE_NONE>; @@ -817,7 +817,7 @@ status = "okay"; clock-frequency = <1000000>; - sii8620@39 { + bridge@39 { reg = <0x39>; compatible = "sil,sii8620"; cvcc10-supply = <&ldo36_reg>; @@ -852,7 +852,7 @@ &hsi2c_8 { status = "okay"; - max77843@66 { + pmic@66 { compatible = "maxim,max77843"; interrupt-parent = <&gpa1>; interrupts = <5 IRQ_TYPE_EDGE_FALLING>; @@ -1231,7 +1231,7 @@ cs-gpios = <&gpd6 3 GPIO_ACTIVE_HIGH>; status = "okay"; - wm5110: wm5110-codec@0 { + wm5110: audio-codec@0 { compatible = "wlf,wm5110"; reg = <0x0>; spi-max-frequency = <20000000>; From 6c215edbdc7129e258a1158fa3284aaa734a38cb Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 27 Oct 2020 18:09:46 +0100 Subject: [PATCH 098/799] arm64: dts: exynos: adjust node names to DT spec in Exynos7 Espresso The Devicetree specification expects device node names to have a generic name, representing the class of a device. Also the convention for node names is to use hyphens, not underscores. No functional changes. Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20201027170947.132725-12-krzk@kernel.org --- arch/arm64/boot/dts/exynos/exynos7-espresso.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/exynos/exynos7-espresso.dts b/arch/arm64/boot/dts/exynos/exynos7-espresso.dts index 92fecc539c6c..695d4c140646 100644 --- a/arch/arm64/boot/dts/exynos/exynos7-espresso.dts +++ b/arch/arm64/boot/dts/exynos/exynos7-espresso.dts @@ -87,7 +87,7 @@ samsung,i2c-max-bus-freq = <200000>; status = "okay"; - s2mps15_pmic@66 { + pmic@66 { compatible = "samsung,s2mps15-pmic"; reg = <0x66>; interrupts = <2 IRQ_TYPE_NONE>; From 29a7bb71a833e092d0012597a00a15ca84837f0b Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 27 Oct 2020 18:09:47 +0100 Subject: [PATCH 099/799] arm64: dts: exynos: remove redundant status=okay in Exynos5433 TM2 New nodes are enabled by default, so status=okay is not needed for them. Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20201027170947.132725-13-krzk@kernel.org --- arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi b/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi index 01ab886fd3e9..97a2f0c7c0cf 100644 --- a/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi @@ -92,7 +92,6 @@ i2c-gpio,delay-us = <2>; #address-cells = <1>; #size-cells = <0>; - status = "okay"; max98504: amplifier@31 { compatible = "maxim,max98504"; From 036f224ef8f447928bfd3085220c28e158a4e4d6 Mon Sep 17 00:00:00 2001 From: Eugen Hristev Date: Thu, 29 Oct 2020 14:12:23 +0200 Subject: [PATCH 100/799] ARM: configs: at91_dt: resync with media changes The media tree Kconfig has changed recently, and a lot of modules were built unintentionally, like the dvb frontends and encoders. Resync the defconfig to build the ISI drivers and tested sensors. Signed-off-by: Eugen Hristev Signed-off-by: Alexandre Belloni Link: https://lore.kernel.org/r/20201029121223.871531-1-eugen.hristev@microchip.com --- arch/arm/configs/at91_dt_defconfig | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/configs/at91_dt_defconfig b/arch/arm/configs/at91_dt_defconfig index 4a0ba2ae1a25..91f0f2c41841 100644 --- a/arch/arm/configs/at91_dt_defconfig +++ b/arch/arm/configs/at91_dt_defconfig @@ -124,9 +124,14 @@ CONFIG_MFD_ATMEL_HLCDC=y CONFIG_REGULATOR=y CONFIG_REGULATOR_FIXED_VOLTAGE=y CONFIG_MEDIA_SUPPORT=y +CONFIG_MEDIA_SUPPORT_FILTER=y +# CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set CONFIG_MEDIA_CAMERA_SUPPORT=y +CONFIG_MEDIA_PLATFORM_SUPPORT=y CONFIG_V4L_PLATFORM_DRIVERS=y CONFIG_VIDEO_ATMEL_ISI=y +CONFIG_VIDEO_OV2640=m +CONFIG_VIDEO_MT9V032=m CONFIG_DRM=y CONFIG_DRM_ATMEL_HLCDC=y CONFIG_DRM_PANEL_SIMPLE=y From cec12cd8d1861ad9090d0b6c70e14a4b87b1e1b4 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 26 Sep 2020 18:23:01 +0200 Subject: [PATCH 101/799] ARM: dts: imx: align watchdog node name with dtschema The dtschema expects watchdog device node name to be "watchdog": arch/arm/boot/dts/imx31-bug.dt.yaml: wdog@53fdc000: $nodename:0: 'wdog@53fdc000' does not match '^watchdog(@.*|-[0-9a-f])?$' Signed-off-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx25.dtsi | 2 +- arch/arm/boot/dts/imx27.dtsi | 2 +- arch/arm/boot/dts/imx31.dtsi | 3 ++- arch/arm/boot/dts/imx35.dtsi | 2 +- arch/arm/boot/dts/imx50.dtsi | 2 +- arch/arm/boot/dts/imx51.dtsi | 4 ++-- arch/arm/boot/dts/imx53.dtsi | 4 ++-- 7 files changed, 10 insertions(+), 9 deletions(-) diff --git a/arch/arm/boot/dts/imx25.dtsi b/arch/arm/boot/dts/imx25.dtsi index 1ab19f1268f8..fdcca82c9986 100644 --- a/arch/arm/boot/dts/imx25.dtsi +++ b/arch/arm/boot/dts/imx25.dtsi @@ -525,7 +525,7 @@ fsl,sdma-ram-script-name = "imx/sdma/sdma-imx25.bin"; }; - wdog@53fdc000 { + watchdog@53fdc000 { compatible = "fsl,imx25-wdt", "fsl,imx21-wdt"; reg = <0x53fdc000 0x4000>; clocks = <&clks 126>; diff --git a/arch/arm/boot/dts/imx27.dtsi b/arch/arm/boot/dts/imx27.dtsi index 7bc132737a37..fd525c3b16fa 100644 --- a/arch/arm/boot/dts/imx27.dtsi +++ b/arch/arm/boot/dts/imx27.dtsi @@ -99,7 +99,7 @@ #dma-channels = <16>; }; - wdog: wdog@10002000 { + wdog: watchdog@10002000 { compatible = "fsl,imx27-wdt", "fsl,imx21-wdt"; reg = <0x10002000 0x1000>; interrupts = <27>; diff --git a/arch/arm/boot/dts/imx31.dtsi b/arch/arm/boot/dts/imx31.dtsi index 45333f7e10ea..948d2a543f8d 100644 --- a/arch/arm/boot/dts/imx31.dtsi +++ b/arch/arm/boot/dts/imx31.dtsi @@ -315,10 +315,11 @@ clock-names = "ref", "ipg"; }; - wdog: wdog@53fdc000 { + wdog: watchdog@53fdc000 { compatible = "fsl,imx31-wdt", "fsl,imx21-wdt"; reg = <0x53fdc000 0x4000>; clocks = <&clks 41>; + interrupts = <55>; }; pwm: pwm@53fe0000 { diff --git a/arch/arm/boot/dts/imx35.dtsi b/arch/arm/boot/dts/imx35.dtsi index aba16252faab..98ccc81ca6d9 100644 --- a/arch/arm/boot/dts/imx35.dtsi +++ b/arch/arm/boot/dts/imx35.dtsi @@ -294,7 +294,7 @@ fsl,sdma-ram-script-name = "imx/sdma/sdma-imx35.bin"; }; - wdog: wdog@53fdc000 { + wdog: watchdog@53fdc000 { compatible = "fsl,imx35-wdt", "fsl,imx21-wdt"; reg = <0x53fdc000 0x4000>; clocks = <&clks 74>; diff --git a/arch/arm/boot/dts/imx50.dtsi b/arch/arm/boot/dts/imx50.dtsi index b6b2e6af9b96..a969f335b240 100644 --- a/arch/arm/boot/dts/imx50.dtsi +++ b/arch/arm/boot/dts/imx50.dtsi @@ -267,7 +267,7 @@ <&iomuxc 20 140 11>; }; - wdog1: wdog@53f98000 { + wdog1: watchdog@53f98000 { compatible = "fsl,imx50-wdt", "fsl,imx21-wdt"; reg = <0x53f98000 0x4000>; interrupts = <58>; diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi index 985e1be03ad6..7ebb46ce9e36 100644 --- a/arch/arm/boot/dts/imx51.dtsi +++ b/arch/arm/boot/dts/imx51.dtsi @@ -370,14 +370,14 @@ status = "disabled"; }; - wdog1: wdog@73f98000 { + wdog1: watchdog@73f98000 { compatible = "fsl,imx51-wdt", "fsl,imx21-wdt"; reg = <0x73f98000 0x4000>; interrupts = <58>; clocks = <&clks IMX5_CLK_DUMMY>; }; - wdog2: wdog@73f9c000 { + wdog2: watchdog@73f9c000 { compatible = "fsl,imx51-wdt", "fsl,imx21-wdt"; reg = <0x73f9c000 0x4000>; interrupts = <59>; diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi index 500eeaa3a27c..000050aeeabe 100644 --- a/arch/arm/boot/dts/imx53.dtsi +++ b/arch/arm/boot/dts/imx53.dtsi @@ -427,14 +427,14 @@ status = "disabled"; }; - wdog1: wdog@53f98000 { + wdog1: watchdog@53f98000 { compatible = "fsl,imx53-wdt", "fsl,imx21-wdt"; reg = <0x53f98000 0x4000>; interrupts = <58>; clocks = <&clks IMX5_CLK_DUMMY>; }; - wdog2: wdog@53f9c000 { + wdog2: watchdog@53f9c000 { compatible = "fsl,imx53-wdt", "fsl,imx21-wdt"; reg = <0x53f9c000 0x4000>; interrupts = <59>; From a913e88ffb90800d531feba45025382aabf680bb Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 26 Sep 2020 18:23:02 +0200 Subject: [PATCH 102/799] ARM: dts: vf: align watchdog node name with dtschema The dtschema expects watchdog device node name to be "watchdog": arch/arm/boot/dts/vf500-colibri-eval-v3.dt.yaml: wdog@4003e000: $nodename:0: 'wdog@4003e000' does not match '^watchdog(@.*|-[0-9a-f])?$' Signed-off-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- arch/arm/boot/dts/vfxxx.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/vfxxx.dtsi b/arch/arm/boot/dts/vfxxx.dtsi index 2259d11af721..0c8d15fd9253 100644 --- a/arch/arm/boot/dts/vfxxx.dtsi +++ b/arch/arm/boot/dts/vfxxx.dtsi @@ -293,7 +293,7 @@ status = "disabled"; }; - wdoga5: wdog@4003e000 { + wdoga5: watchdog@4003e000 { compatible = "fsl,vf610-wdt", "fsl,imx21-wdt"; reg = <0x4003e000 0x1000>; interrupts = <20 IRQ_TYPE_LEVEL_HIGH>; From 1a002325d1642f6d206563870434dc027546e06e Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 26 Sep 2020 18:28:03 +0200 Subject: [PATCH 103/799] dt-bindings: arm: fsl: document i.MX25 and i.MX27 boards Document and adjust the compatibles for i.MX25 and i.MX27 based boards to fix dtbs_check warnings like: arch/arm/boot/dts/imx27-apf27dev.dt.yaml: /: compatible: ['armadeus,imx27-apf27dev', 'armadeus,imx27-apf27', 'fsl,imx27'] is not valid under any of the given schemas Signed-off-by: Krzysztof Kozlowski Reviewed-by: Rob Herring Signed-off-by: Shawn Guo --- .../devicetree/bindings/arm/fsl.yaml | 45 ++++++++++++++++++- 1 file changed, 43 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index b0db3c90914b..76e1628dbdbb 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -33,16 +33,57 @@ properties: items: - enum: - fsl,imx25-pdk + - karo,imx25-tx25 - const: fsl,imx25 - - description: i.MX27 Product Development Kit + - description: i.MX25 Eukrea CPUIMX25 Boards + items: + - enum: + - eukrea,mbimxsd25-baseboard # Eukrea MBIMXSD25 + - const: eukrea,cpuimx25 + - const: fsl,imx25 + + - description: i.MX25 Eukrea MBIMXSD25 Boards + items: + - enum: + - eukrea,mbimxsd25-baseboard-cmo-qvga + - eukrea,mbimxsd25-baseboard-dvi-svga + - eukrea,mbimxsd25-baseboard-dvi-vga + - const: eukrea,mbimxsd25-baseboard + - const: eukrea,cpuimx25 + - const: fsl,imx25 + + - description: i.MX27 based Boards items: - enum: - armadeus,imx27-apf27 # APF27 SoM - - armadeus,imx27-apf27dev # APF27 SoM on APF27Dev board - fsl,imx27-pdk - const: fsl,imx27 + - description: i.MX27 APF27 SoM Board + items: + - const: armadeus,imx27-apf27dev + - const: armadeus,imx27-apf27 + - const: fsl,imx27 + + - description: i.MX27 Eukrea CPUIMX27 SoM Board + items: + - const: eukrea,mbimxsd27-baseboard + - const: eukrea,cpuimx27 + - const: fsl,imx27 + + - description: i.MX27 Phytec pca100 Board + items: + - const: phytec,imx27-pca100-rdk + - const: phytec,imx27-pca100 + - const: fsl,imx27 + + - description: i.MX27 Phytec pcm970 Board + items: + - const: phytec,imx27-pcm970 + - const: phytec,imx27-pcm038 + - const: fsl,imx27 + - description: i.MX28 based Boards items: - enum: From b92b80246e06269c1407face33fd8a57a763a145 Mon Sep 17 00:00:00 2001 From: Luke D Jones Date: Tue, 27 Oct 2020 10:02:17 +1300 Subject: [PATCH 104/799] HID: asus: Add support for ASUS N-Key keyboard The ASUS N-Key keyboard uses the productId of 0x1866 and is used in almost all modern ASUS gaming laptops with slight changes to the firmware. This patch enables: Fn+key hotkeys, keyboard backlight brightness control. Additionally this keyboard requires the LED interface to be initialized before such things as keyboard backlight control work. Signed-off-by: Luke D Jones Reviewed-by: Hans de Goede Signed-off-by: Jiri Kosina --- drivers/hid/hid-asus.c | 123 ++++++++++++++++++++++++++++++++++++----- drivers/hid/hid-ids.h | 1 + 2 files changed, 110 insertions(+), 14 deletions(-) diff --git a/drivers/hid/hid-asus.c b/drivers/hid/hid-asus.c index c183caf89d49..1dfe184ebf5a 100644 --- a/drivers/hid/hid-asus.c +++ b/drivers/hid/hid-asus.c @@ -48,6 +48,8 @@ MODULE_DESCRIPTION("Asus HID Keyboard and TouchPad"); #define INPUT_REPORT_ID 0x5d #define FEATURE_KBD_REPORT_ID 0x5a #define FEATURE_KBD_REPORT_SIZE 16 +#define FEATURE_KBD_LED_REPORT_ID1 0x5d +#define FEATURE_KBD_LED_REPORT_ID2 0x5e #define SUPPORT_KBD_BACKLIGHT BIT(0) @@ -80,6 +82,7 @@ MODULE_DESCRIPTION("Asus HID Keyboard and TouchPad"); #define QUIRK_T101HA_DOCK BIT(9) #define QUIRK_T90CHI BIT(10) #define QUIRK_MEDION_E1239T BIT(11) +#define QUIRK_ROG_NKEY_KEYBOARD BIT(12) #define I2C_KEYBOARD_QUIRKS (QUIRK_FIX_NOTEBOOK_REPORT | \ QUIRK_NO_INIT_REPORTS | \ @@ -332,6 +335,28 @@ static int asus_raw_event(struct hid_device *hdev, if (drvdata->quirks & QUIRK_MEDION_E1239T) return asus_e1239t_event(drvdata, data, size); + if (drvdata->quirks & QUIRK_ROG_NKEY_KEYBOARD) { + /* + * Skip these report ID, the device emits a continuous stream associated + * with the AURA mode it is in which looks like an 'echo'. + */ + if (report->id == FEATURE_KBD_LED_REPORT_ID1 || + report->id == FEATURE_KBD_LED_REPORT_ID2) { + return -1; + /* Additional report filtering */ + } else if (report->id == FEATURE_KBD_REPORT_ID) { + /* + * G14 and G15 send these codes on some keypresses with no + * discernable reason for doing so. We'll filter them out to avoid + * unmapped warning messages later. + */ + if (data[1] == 0xea || data[1] == 0xec || data[1] == 0x02 || + data[1] == 0x8a || data[1] == 0x9e) { + return -1; + } + } + } + return 0; } @@ -344,7 +369,11 @@ static int asus_kbd_set_report(struct hid_device *hdev, u8 *buf, size_t buf_size if (!dmabuf) return -ENOMEM; - ret = hid_hw_raw_request(hdev, FEATURE_KBD_REPORT_ID, dmabuf, + /* + * The report ID should be set from the incoming buffer due to LED and key + * interfaces having different pages + */ + ret = hid_hw_raw_request(hdev, buf[0], dmabuf, buf_size, HID_FEATURE_REPORT, HID_REQ_SET_REPORT); kfree(dmabuf); @@ -397,6 +426,51 @@ static int asus_kbd_get_functions(struct hid_device *hdev, return ret; } +static int rog_nkey_led_init(struct hid_device *hdev) +{ + u8 buf_init_start[] = { FEATURE_KBD_LED_REPORT_ID1, 0xB9 }; + u8 buf_init2[] = { FEATURE_KBD_LED_REPORT_ID1, 0x41, 0x53, 0x55, 0x53, 0x20, + 0x54, 0x65, 0x63, 0x68, 0x2e, 0x49, 0x6e, 0x63, 0x2e, 0x00 }; + u8 buf_init3[] = { FEATURE_KBD_LED_REPORT_ID1, + 0x05, 0x20, 0x31, 0x00, 0x08 }; + int ret; + + hid_info(hdev, "Asus initialise N-KEY Device"); + /* The first message is an init start */ + ret = asus_kbd_set_report(hdev, buf_init_start, sizeof(buf_init_start)); + if (ret < 0) { + hid_warn(hdev, "Asus failed to send init start command: %d\n", ret); + return ret; + } + /* Followed by a string */ + ret = asus_kbd_set_report(hdev, buf_init2, sizeof(buf_init2)); + if (ret < 0) { + hid_warn(hdev, "Asus failed to send init command 1.0: %d\n", ret); + return ret; + } + /* Followed by a string */ + ret = asus_kbd_set_report(hdev, buf_init3, sizeof(buf_init3)); + if (ret < 0) { + hid_warn(hdev, "Asus failed to send init command 1.1: %d\n", ret); + return ret; + } + + /* begin second report ID with same data */ + buf_init2[0] = FEATURE_KBD_LED_REPORT_ID2; + buf_init3[0] = FEATURE_KBD_LED_REPORT_ID2; + + ret = asus_kbd_set_report(hdev, buf_init2, sizeof(buf_init2)); + if (ret < 0) { + hid_warn(hdev, "Asus failed to send init command 2.0: %d\n", ret); + return ret; + } + ret = asus_kbd_set_report(hdev, buf_init3, sizeof(buf_init3)); + if (ret < 0) + hid_warn(hdev, "Asus failed to send init command 2.1: %d\n", ret); + + return ret; +} + static void asus_kbd_backlight_set(struct led_classdev *led_cdev, enum led_brightness brightness) { @@ -460,19 +534,25 @@ static int asus_kbd_register_leds(struct hid_device *hdev) unsigned char kbd_func; int ret; - /* Initialize keyboard */ - ret = asus_kbd_init(hdev); - if (ret < 0) - return ret; + if (drvdata->quirks & QUIRK_ROG_NKEY_KEYBOARD) { + ret = rog_nkey_led_init(hdev); + if (ret < 0) + return ret; + } else { + /* Initialize keyboard */ + ret = asus_kbd_init(hdev); + if (ret < 0) + return ret; - /* Get keyboard functions */ - ret = asus_kbd_get_functions(hdev, &kbd_func); - if (ret < 0) - return ret; + /* Get keyboard functions */ + ret = asus_kbd_get_functions(hdev, &kbd_func); + if (ret < 0) + return ret; - /* Check for backlight support */ - if (!(kbd_func & SUPPORT_KBD_BACKLIGHT)) - return -ENODEV; + /* Check for backlight support */ + if (!(kbd_func & SUPPORT_KBD_BACKLIGHT)) + return -ENODEV; + } drvdata->kbd_backlight = devm_kzalloc(&hdev->dev, sizeof(struct asus_kbd_leds), @@ -751,8 +831,8 @@ static int asus_input_mapping(struct hid_device *hdev, usage->hid == (HID_UP_GENDEVCTRLS | 0x0026))) return -1; - /* ASUS-specific keyboard hotkeys */ - if ((usage->hid & HID_USAGE_PAGE) == 0xff310000) { + /* ASUS-specific keyboard hotkeys and led backlight */ + if ((usage->hid & HID_USAGE_PAGE) == HID_UP_ASUSVENDOR) { switch (usage->hid & HID_USAGE) { case 0x10: asus_map_key_clear(KEY_BRIGHTNESSDOWN); break; case 0x20: asus_map_key_clear(KEY_BRIGHTNESSUP); break; @@ -780,6 +860,18 @@ static int asus_input_mapping(struct hid_device *hdev, /* Fn+F5 "fan" symbol on FX503VD */ case 0x99: asus_map_key_clear(KEY_PROG4); break; + /* Fn+F5 "fan" symbol on N-Key keyboard */ + case 0xae: asus_map_key_clear(KEY_PROG4); break; + + /* Fn+Ret "Calc" symbol on N-Key keyboard */ + case 0x92: asus_map_key_clear(KEY_CALC); break; + + /* Fn+Left Aura mode previous on N-Key keyboard */ + case 0xb2: asus_map_key_clear(KEY_PROG2); break; + + /* Fn+Right Aura mode next on N-Key keyboard */ + case 0xb3: asus_map_key_clear(KEY_PROG3); break; + default: /* ASUS lazily declares 256 usages, ignore the rest, * as some make the keyboard appear as a pointer device. */ @@ -1126,6 +1218,9 @@ static const struct hid_device_id asus_devices[] = { { HID_USB_DEVICE(USB_VENDOR_ID_ASUSTEK, USB_DEVICE_ID_ASUSTEK_FX503VD_KEYBOARD), QUIRK_USE_KBD_BACKLIGHT }, + { HID_USB_DEVICE(USB_VENDOR_ID_ASUSTEK, + USB_DEVICE_ID_ASUSTEK_ROG_NKEY_KEYBOARD), + QUIRK_USE_KBD_BACKLIGHT | QUIRK_ROG_NKEY_KEYBOARD }, { HID_USB_DEVICE(USB_VENDOR_ID_ASUSTEK, USB_DEVICE_ID_ASUSTEK_T100TA_KEYBOARD), QUIRK_T100_KEYBOARD | QUIRK_NO_CONSUMER_USAGES }, diff --git a/drivers/hid/hid-ids.h b/drivers/hid/hid-ids.h index d69842f79fc6..5077c05fada1 100644 --- a/drivers/hid/hid-ids.h +++ b/drivers/hid/hid-ids.h @@ -190,6 +190,7 @@ #define USB_DEVICE_ID_ASUSTEK_ROG_KEYBOARD1 0x1854 #define USB_DEVICE_ID_ASUSTEK_ROG_KEYBOARD2 0x1837 #define USB_DEVICE_ID_ASUSTEK_ROG_KEYBOARD3 0x1822 +#define USB_DEVICE_ID_ASUSTEK_ROG_NKEY_KEYBOARD 0x1866 #define USB_DEVICE_ID_ASUSTEK_FX503VD_KEYBOARD 0x1869 #define USB_VENDOR_ID_ATEN 0x0557 From 4b393f0f76c8e3ce80b3bd524dc40bd674a29101 Mon Sep 17 00:00:00 2001 From: Sandeep Singh Date: Wed, 28 Oct 2020 14:30:10 +0530 Subject: [PATCH 105/799] AMD_SFH: Fix for incorrect Sensor index It appears like the accelerometer/magnetometer and gyroscope indices were interchanged in the patch series which got into for-5.11/amd-sfh-hid until Mandoli/Richard reported to us. Ideally sensor indices should be 0,1,2 for the accelerometer, Gyroscope, Magnetometer respectively, but this interchanged possibly could be because i was using a test MP2 firmware on my machine. This patch fixes the earlier commit with the right sensor indices and also removing unused structures _hid_report_descriptor, _hid_device_descriptor as reported by Richard. Fixes: 4f567b9f8141 ("SFH: PCIe driver to add support of AMD sensor fusion hub 4f567b9f8141") Reported-by: Mandoli Reported-by: Richard Neumann Signed-off-by: Sandeep Singh Signed-off-by: Jiri Kosina --- drivers/hid/amd-sfh-hid/amd_sfh_pcie.c | 6 +++--- .../amd-sfh-hid/hid_descriptor/amd_sfh_hid_desc.h | 14 -------------- 2 files changed, 3 insertions(+), 17 deletions(-) diff --git a/drivers/hid/amd-sfh-hid/amd_sfh_pcie.c b/drivers/hid/amd-sfh-hid/amd_sfh_pcie.c index 9c5eb442e1a6..a51c7b76283b 100644 --- a/drivers/hid/amd-sfh-hid/amd_sfh_pcie.c +++ b/drivers/hid/amd-sfh-hid/amd_sfh_pcie.c @@ -20,9 +20,9 @@ #define DRIVER_NAME "pcie_mp2_amd" #define DRIVER_DESC "AMD(R) PCIe MP2 Communication Driver" -#define ACEL_EN BIT(1) -#define GYRO_EN BIT(2) -#define MAGNO_EN BIT(3) +#define ACEL_EN BIT(0) +#define GYRO_EN BIT(1) +#define MAGNO_EN BIT(2) #define ALS_EN BIT(19) void amd_start_sensor(struct amd_mp2_dev *privdata, struct amd_mp2_sensor_info info) diff --git a/drivers/hid/amd-sfh-hid/hid_descriptor/amd_sfh_hid_desc.h b/drivers/hid/amd-sfh-hid/hid_descriptor/amd_sfh_hid_desc.h index ac9a01cc1454..095c471d8fd6 100644 --- a/drivers/hid/amd-sfh-hid/hid_descriptor/amd_sfh_hid_desc.h +++ b/drivers/hid/amd-sfh-hid/hid_descriptor/amd_sfh_hid_desc.h @@ -16,11 +16,6 @@ enum desc_type { feature_size, }; -struct _hid_report_descriptor { - u8 bDescriptorType; - u8 wDescriptorLength; -}; - struct common_feature_property { /* common properties */ u8 report_id; @@ -38,15 +33,6 @@ struct common_input_property { u8 event_type; } __packed; -struct _hid_device_descriptor { - u8 bLength; - u8 bDescriptorType; - u8 bcdHID[2]; - u8 bCountryCode; - u8 bNumDescriptors; - struct _hid_report_descriptor *reports; -}; - struct accel3_feature_report { struct common_feature_property common_property; /* properties specific to this sensor */ From afdd34c5fa4028976ee5103ac499edbddedc813e Mon Sep 17 00:00:00 2001 From: Coiby Xu Date: Wed, 21 Oct 2020 22:33:05 +0800 Subject: [PATCH 106/799] HID: i2c-hid: show the error when failing to fetch the HID descriptor MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit i2c_hid_probe() should notify the user of the error of failing to fetch the HID Descriptor instead of silently exiting. Link: https://forum.manjaro.org/t/elan-touchpad-working-in-live-but-not-in-native-os/31860/55 Cc: Barnabás Pőcze Signed-off-by: Coiby Xu Signed-off-by: Jiri Kosina --- drivers/hid/i2c-hid/i2c-hid-core.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/hid/i2c-hid/i2c-hid-core.c b/drivers/hid/i2c-hid/i2c-hid-core.c index 786e3e9af1c9..577d324be16d 100644 --- a/drivers/hid/i2c-hid/i2c-hid-core.c +++ b/drivers/hid/i2c-hid/i2c-hid-core.c @@ -1099,8 +1099,11 @@ static int i2c_hid_probe(struct i2c_client *client, } ret = i2c_hid_fetch_hid_descriptor(ihid); - if (ret < 0) + if (ret < 0) { + dev_err(&client->dev, + "Failed to fetch the HID Descriptor\n"); goto err_regulator; + } ret = i2c_hid_init_irq(client); if (ret < 0) From c6838eeef2fbc7e3e1f83759aa016ae6b70c643e Mon Sep 17 00:00:00 2001 From: "dmitry.torokhov@gmail.com" Date: Wed, 30 Sep 2020 15:47:13 -0700 Subject: [PATCH 107/799] HID: hid-input: occasionally report stylus battery even if not changed There are styluses that only report their battery status when they are touching the touchscreen; additionally we currently suppress battery reports if capacity has not changed. To help userspace recognize how long ago the device reported battery status, let's send the change event through if either capacity has changed, or at least 30 seconds have passed since last report we've let through. Signed-off-by: Dmitry Torokhov Signed-off-by: Jiri Kosina --- drivers/hid/hid-input.c | 5 ++++- include/linux/hid.h | 1 + 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/hid/hid-input.c b/drivers/hid/hid-input.c index 9770db624bfa..b0db2a2ac15a 100644 --- a/drivers/hid/hid-input.c +++ b/drivers/hid/hid-input.c @@ -534,9 +534,12 @@ static void hidinput_update_battery(struct hid_device *dev, int value) capacity = hidinput_scale_battery_capacity(dev, value); if (dev->battery_status != HID_BATTERY_REPORTED || - capacity != dev->battery_capacity) { + capacity != dev->battery_capacity || + ktime_after(ktime_get_coarse(), dev->battery_ratelimit_time)) { dev->battery_capacity = capacity; dev->battery_status = HID_BATTERY_REPORTED; + dev->battery_ratelimit_time = + ktime_add_ms(ktime_get_coarse(), 30 * 1000); power_supply_changed(dev->battery); } } diff --git a/include/linux/hid.h b/include/linux/hid.h index 58684657960b..b079146850e6 100644 --- a/include/linux/hid.h +++ b/include/linux/hid.h @@ -585,6 +585,7 @@ struct hid_device { /* device report descriptor */ __s32 battery_report_id; enum hid_battery_status battery_status; bool battery_avoid_query; + ktime_t battery_ratelimit_time; #endif unsigned long status; /* see STAT flags above */ From 2f4ac2d79eb4c09ee6dbda1d2fc2616f281094f9 Mon Sep 17 00:00:00 2001 From: Anson Huang Date: Sun, 27 Sep 2020 15:03:13 +0800 Subject: [PATCH 108/799] ARM: imx: Add revision support for i.MX7ULP revision 2.2 On i.MX7ULP revision 2.2, the value is 3, so add support for this revision, otherwise, it will use default revision of 1.0 which is incorrect. Signed-off-by: Anson Huang Reviewed-by: Peng Fan Signed-off-by: Shawn Guo --- arch/arm/mach-imx/mach-imx7ulp.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/mach-imx/mach-imx7ulp.c b/arch/arm/mach-imx/mach-imx7ulp.c index 445256e6a4a0..f6032ea7de8b 100644 --- a/arch/arm/mach-imx/mach-imx7ulp.c +++ b/arch/arm/mach-imx/mach-imx7ulp.c @@ -45,6 +45,9 @@ static void __init imx7ulp_set_revision(void) case 2: imx_set_soc_revision(IMX_CHIP_REVISION_2_1); break; + case 3: + imx_set_soc_revision(IMX_CHIP_REVISION_2_2); + break; default: imx_set_soc_revision(IMX_CHIP_REVISION_1_0); break; From 7ecab1f29baf8b8c43d5f7c891aceacc15c19f22 Mon Sep 17 00:00:00 2001 From: Anson Huang Date: Mon, 28 Sep 2020 10:21:43 +0800 Subject: [PATCH 109/799] arm64: dts: imx8mn-evk: Add cpu-supply to enable cpufreq PMIC driver is ready on i.MX8MN EVK board, assign cpu-supply for each A53 and restore the operating points table to enable cpufreq. Signed-off-by: Anson Huang Reviewed-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mn-evk.dts | 32 ++++++++++---------- 1 file changed, 16 insertions(+), 16 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mn-evk.dts b/arch/arm64/boot/dts/freescale/imx8mn-evk.dts index 707d8486b4d8..9e5c0af5f540 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mn-evk.dts @@ -14,6 +14,22 @@ compatible = "fsl,imx8mn-evk", "fsl,imx8mn"; }; +&A53_0 { + cpu-supply = <&buck2>; +}; + +&A53_1 { + cpu-supply = <&buck2>; +}; + +&A53_2 { + cpu-supply = <&buck2>; +}; + +&A53_3 { + cpu-supply = <&buck2>; +}; + &i2c1 { pmic: pmic@25 { compatible = "nxp,pca9450b"; @@ -109,19 +125,3 @@ }; }; }; - -&A53_0 { - /delete-property/operating-points-v2; -}; - -&A53_1 { - /delete-property/operating-points-v2; -}; - -&A53_2 { - /delete-property/operating-points-v2; -}; - -&A53_3 { - /delete-property/operating-points-v2; -}; From d9395d72003365dd2221922ba73a184603848124 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 29 Oct 2020 17:21:32 +0100 Subject: [PATCH 110/799] dt-bindings: watchdog: fsl-imx: document NXP compatibles Document all ARMv5, ARMv6, ARMv7 and ARMv8 NXP (i.MX, Layerscape) compatibles used in DTSes (even though driver binds only to fsl,imx21-wdt) to fix dtbs_check warnings like: arch/arm/boot/dts/imx53-qsb.dt.yaml: gpio@53fe0000: compatible: ['fsl,imx53-gpio', 'fsl,imx35-gpio'] is not valid under any of the given schemas Signed-off-by: Krzysztof Kozlowski Reviewed-by: Rob Herring Signed-off-by: Shawn Guo --- .../bindings/watchdog/fsl-imx-wdt.yaml | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/Documentation/devicetree/bindings/watchdog/fsl-imx-wdt.yaml b/Documentation/devicetree/bindings/watchdog/fsl-imx-wdt.yaml index 991b4e33486e..fb7695515be1 100644 --- a/Documentation/devicetree/bindings/watchdog/fsl-imx-wdt.yaml +++ b/Documentation/devicetree/bindings/watchdog/fsl-imx-wdt.yaml @@ -18,10 +18,26 @@ properties: - const: fsl,imx21-wdt - items: - enum: + - fsl,imx25-wdt + - fsl,imx27-wdt + - fsl,imx31-wdt + - fsl,imx35-wdt + - fsl,imx50-wdt + - fsl,imx51-wdt + - fsl,imx53-wdt + - fsl,imx6q-wdt + - fsl,imx6sl-wdt + - fsl,imx6sll-wdt + - fsl,imx6sx-wdt + - fsl,imx6ul-wdt + - fsl,imx7d-wdt - fsl,imx8mm-wdt - fsl,imx8mn-wdt - fsl,imx8mp-wdt - fsl,imx8mq-wdt + - fsl,ls1012a-wdt + - fsl,ls1043a-wdt + - fsl,vf610-wdt - const: fsl,imx21-wdt reg: From 71011f55b0ab160631a31ea1e4b23f9717e5d072 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 29 Oct 2020 17:21:33 +0100 Subject: [PATCH 111/799] arm64: dts: freescale: align watchdog node name with dtschema The dtschema expects watchdog device node name to be "watchdog": arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dt.yaml: wdog@2ad0000: $nodename:0: 'wdog@2ad0000' does not match '^watchdog(@.*|-[0-9a-f])?$' Signed-off-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi | 2 +- arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi index 6a2c09199047..1393fc7e56bb 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi @@ -401,7 +401,7 @@ #interrupt-cells = <2>; }; - wdog0: wdog@2ad0000 { + wdog0: watchdog@2ad0000 { compatible = "fsl,ls1012a-wdt", "fsl,imx21-wdt"; reg = <0x0 0x2ad0000 0x0 0x10000>; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi index 0464b8aa4bc4..d550f00f1f6a 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi @@ -725,7 +725,7 @@ status = "disabled"; }; - wdog0: wdog@2ad0000 { + wdog0: watchdog@2ad0000 { compatible = "fsl,ls1043a-wdt", "fsl,imx21-wdt"; reg = <0x0 0x2ad0000 0x0 0x10000>; interrupts = <0 83 0x4>; From 5c22a9af414c463b3f47bc56b5bca5d7b7c6d5f0 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 29 Sep 2020 10:40:13 +0200 Subject: [PATCH 112/799] arm64: dts: imx8mm: adjust GIC CPU mask to match number of CPUs i.MX 8M Mini has four Cortex-A CPUs, not six. Using higher value is harmless but adjust it to match real HW. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Jacky Bai Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mm.dtsi | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi index b83f400def8b..ee486597afc0 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi @@ -194,16 +194,16 @@ pmu { compatible = "arm,armv8-pmuv3"; interrupts = ; + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; interrupt-affinity = <&A53_0>, <&A53_1>, <&A53_2>, <&A53_3>; }; timer { compatible = "arm,armv8-timer"; - interrupts = , /* Physical Secure */ - , /* Physical Non-Secure */ - , /* Virtual */ - ; /* Hypervisor */ + interrupts = , /* Physical Secure */ + , /* Physical Non-Secure */ + , /* Virtual */ + ; /* Hypervisor */ clock-frequency = <8000000>; arm,no-tick-in-suspend; }; From 0656e37a8fa87fca12ef255de018a9d80ba23eb8 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 29 Sep 2020 10:40:14 +0200 Subject: [PATCH 113/799] arm64: dts: imx8mn: adjust GIC CPU mask to match number of CPUs i.MX 8M Nano has four Cortex-A CPUs, not six. Using higher value is harmless but adjust it to match real HW. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Jacky Bai Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mn.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi index 746faf1cf2fb..390fbd2bfa7e 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi @@ -225,10 +225,10 @@ timer { compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; + interrupts = , + , + , + ; clock-frequency = <8000000>; arm,no-tick-in-suspend; }; From 061883e690ebf6fc5a17fdf55249a3b8d5c111fe Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 29 Sep 2020 10:40:15 +0200 Subject: [PATCH 114/799] arm64: dts: imx8mp: adjust GIC CPU mask to match number of CPUs i.MX 8M Plus has four Cortex-A CPUs, not six. Using higher value is harmless but adjust it to match real HW. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Jacky Bai Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mp.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index 6038f66aefc1..c69c206068a4 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -202,10 +202,10 @@ timer { compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; + interrupts = , + , + , + ; clock-frequency = <8000000>; arm,no-tick-in-suspend; }; From 0f109a3158297ba774cdd4991b4a145738fe6202 Mon Sep 17 00:00:00 2001 From: Jacky Bai Date: Tue, 29 Sep 2020 17:15:22 +0800 Subject: [PATCH 115/799] arm64: dts: freescale: Add pmu support on imx8mp Add PMU node to enable pmu support on imx8mp. Signed-off-by: Jacky Bai Reviewed-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mp.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index c69c206068a4..479312293036 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -133,6 +133,13 @@ clock-output-names = "clk_ext4"; }; + pmu { + compatible = "arm,cortex-a53-pmu"; + interrupts = ; + interrupt-affinity = <&A53_0>, <&A53_1>, <&A53_2>, <&A53_3>; + }; + psci { compatible = "arm,psci-1.0"; method = "smc"; From c13a7d84c4159e58127dbeac287686620a70b770 Mon Sep 17 00:00:00 2001 From: Jacky Bai Date: Tue, 29 Sep 2020 17:15:23 +0800 Subject: [PATCH 116/799] arm64: dts: freescale: Add pmu support on imx8mn Add PMU node to enable pmu support on imx8mn. Signed-off-by: Jacky Bai Reviewed-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mn.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi index 390fbd2bfa7e..d5cb8abb13e8 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi @@ -186,6 +186,13 @@ clock-output-names = "clk_ext4"; }; + pmu { + compatible = "arm,cortex-a53-pmu"; + interrupts = ; + interrupt-affinity = <&A53_0>, <&A53_1>, <&A53_2>, <&A53_3>; + }; + psci { compatible = "arm,psci-1.0"; method = "smc"; From b01222b9193e40557b5a3bdf833898812ef36dcb Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 30 Sep 2020 21:01:32 +0200 Subject: [PATCH 117/799] dt-bindings: vendor-prefixes: add MicroSys Document vendor prefix for MicroSys Electronics GmbH. Signed-off-by: Krzysztof Kozlowski Acked-by: Rob Herring Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index 2735be1a8470..8e477373211a 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -669,6 +669,8 @@ patternProperties: description: Micron Technology Inc. "^microsoft,.*": description: Microsoft Corporation + "^microsys,.*": + description: MicroSys Electronics GmbH "^mikroe,.*": description: MikroElektronika d.o.o. "^mikrotik,.*": From 1acb40298366b8350d34db47dd9aae72ff18691e Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 30 Sep 2020 21:01:33 +0200 Subject: [PATCH 118/799] dt-bindings: vendor-prefixes: add Revotics Document vendor prefix for Revotics (Revolution Robotics, Inc.). Signed-off-by: Krzysztof Kozlowski Acked-by: Rob Herring Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index 8e477373211a..39f0d7c074fe 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -896,6 +896,8 @@ patternProperties: description: iMX6 Rex Project "^rervision,.*": description: Shenzhen Rervision Technology Co., Ltd. + "^revotics,.*": + description: Revolution Robotics, Inc. (Revotics) "^richtek,.*": description: Richtek Technology Corporation "^ricoh,.*": From 5427f287976c4dd1c1ffb4c0cb94d50d3cd14244 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 30 Sep 2020 21:01:35 +0200 Subject: [PATCH 119/799] dt-bindings: arm: fsl: document i.MX51 boards Document and adjust the compatibles for i.MX51 based boards. Signed-off-by: Krzysztof Kozlowski Acked-by: Rob Herring Signed-off-by: Shawn Guo --- .../devicetree/bindings/arm/fsl.yaml | 26 ++++++++++++++++--- 1 file changed, 23 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index 76e1628dbdbb..c381863116aa 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -129,13 +129,33 @@ properties: - kobo,aura - const: fsl,imx50 - - description: i.MX51 Babbage Board + - description: i.MX51 based Boards items: - enum: - - armadeus,imx51-apf51 # APF51 SoM - - armadeus,imx51-apf51dev # APF51 SoM on APF51Dev board + - armadeus,imx51-apf51 # Armadeus Systems APF51 module - fsl,imx51-babbage - technologic,imx51-ts4800 + - zii,imx51-scu3-esb + - zii,imx51-scu2-mezz + - zii,imx51-rdu1 + - const: fsl,imx51 + + - description: i.MX51 based Armadeus Systems APF51Dev Board + items: + - const: armadeus,imx51-apf51dev + - const: armadeus,imx51-apf51 + - const: fsl,imx51 + + - description: i.MX51 based Digi ConnectCore CC(W)-MX51 JSK Board + items: + - const: digi,connectcore-ccxmx51-jsk + - const: digi,connectcore-ccxmx51-som + - const: fsl,imx51 + + - description: i.MX51 based Eukrea CPUIMX51 Board + items: + - const: eukrea,mbimxsd51 + - const: eukrea,cpuimx51 - const: fsl,imx51 - description: i.MX53 based Boards From be03d03b5cf806548547edff1a9b82ae91f679c6 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 30 Sep 2020 21:01:36 +0200 Subject: [PATCH 120/799] dt-bindings: arm: fsl: document i.MX53 boards Document and adjust the compatibles for i.MX53 based boards. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Rob Herring Signed-off-by: Shawn Guo --- .../devicetree/bindings/arm/fsl.yaml | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index c381863116aa..b049d3c3cc3a 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -165,8 +165,27 @@ properties: - fsl,imx53-ard - fsl,imx53-evk - fsl,imx53-qsb + - fsl,imx53-qsrb # Freescale i.MX53 Quick Start-R Board - fsl,imx53-smd + - ge,imx53-cpuvo # General Electric CS ONE + - inversepath,imx53-usbarmory # Inverse Path USB armory + - karo,tx53 # Ka-Ro electronics TX53 module + - kiebackpeter,imx53-ddc # K+P imx53 DDC + - kiebackpeter,imx53-hsc # K+P imx53 HSC - menlo,m53menlo + - voipac,imx53-dmm-668 # Voipac i.MX53 X53-DMM-668 + - const: fsl,imx53 + + - description: i.MX53 based Aries/DENX M53EVK Board + items: + - const: aries,imx53-m53evk + - const: denx,imx53-m53evk + - const: fsl,imx53 + + - description: i.MX53 based TQ MBa53 Board + items: + - const: tq,mba53 + - const: tq,tqma53 - const: fsl,imx53 - description: i.MX6Q based Boards From 9d808cbfa5e721e8e400a7d7678b9f9c28ff9512 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 30 Sep 2020 21:01:37 +0200 Subject: [PATCH 121/799] dt-bindings: arm: fsl: document VF boards Document and adjust the compatibles for VF500 and VF600 based boards. The Toradex Colibri Evaluation Boards use multiple compatibles. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Rob Herring Signed-off-by: Shawn Guo --- .../devicetree/bindings/arm/fsl.yaml | 24 +++++++++++++++---- 1 file changed, 20 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index b049d3c3cc3a..d7bbcb1f59b6 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -581,10 +581,26 @@ properties: - fsl,vf600 - fsl,vf610 - fsl,vf610m4 - - toradex,vf500-colibri_vf50 # Colibri VF50 Module - - toradex,vf500-colibri_vf50-on-eval # Colibri VF50 Module on Colibri Evaluation Board - - toradex,vf610-colibri_vf61 # Colibri VF61 Module - - toradex,vf610-colibri_vf61-on-eval # Colibri VF61 Module on Colibri Evaluation Board + + - description: Toradex Colibri VF50 Module on Colibri Evaluation Board + items: + - const: toradex,vf500-colibri_vf50-on-eval + - const: toradex,vf500-colibri_vf50 + - const: fsl,vf500 + + - description: VF610 based Boards + items: + - enum: + - lwn,bk4 # Liebherr BK4 controller + - phytec,vf610-cosmic # PHYTEC Cosmic/Cosmic+ Board + - fsl,vf610-twr # VF610 Tower Board + - const: fsl,vf610 + + - description: Toradex Colibri VF61 Module on Colibri Evaluation Board + items: + - const: toradex,vf610-colibri_vf61-on-eval + - const: toradex,vf610-colibri_vf61 + - const: fsl,vf610 - description: ZII's VF610 based Boards items: From c470ce79fe46aa35a6c7922b00ce2be5ba15b2f4 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 30 Sep 2020 21:01:38 +0200 Subject: [PATCH 122/799] dt-bindings: arm: fsl: document i.MX6DL boards Document and adjust the compatibles for i.MX6DL based boards. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Rob Herring Signed-off-by: Shawn Guo --- .../devicetree/bindings/arm/fsl.yaml | 49 ++++++++++++++++--- 1 file changed, 43 insertions(+), 6 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index d7bbcb1f59b6..f45e243916d8 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -269,32 +269,53 @@ properties: - description: i.MX6DL based Boards items: - enum: - - armadeus,imx6dl-apf6 # APF6 (Solo) SoM - - armadeus,imx6dl-apf6dev # APF6 (Solo) SoM on APF6Dev board + - boundary,imx6dl-nit6xlite # Boundary Devices Nitrogen6 Lite + - boundary,imx6dl-nitrogen6x # Boundary Devices Nitrogen6x + - bticino,imx6dl-mamoj # BTicino i.MX6DL Mamoj - eckelmann,imx6dl-ci4x10 - emtrion,emcon-mx6 # emCON-MX6S or emCON-MX6DL SoM - emtrion,emcon-mx6-avari # emCON-MX6S or emCON-MX6DL SoM on Avari Base + - engicam,imx6-icore # Engicam i.CoreM6 Starter Kit + - engicam,imx6-icore-rqs # Engicam i.CoreM6 RQS Starter Kit - fsl,imx6dl-sabreauto # i.MX6 DualLite/Solo SABRE Automotive Board + - fsl,imx6dl-sabrelite # i.MX6 DualLite SABRE Lite Board - fsl,imx6dl-sabresd # i.MX6 DualLite SABRE Smart Device Board + - karo,imx6dl-tx6dl # Ka-Ro electronics TX6U Modules - kontron,imx6dl-samx6i # Kontron i.MX6 Solo SMARC Module + - poslab,imx6dl-savageboard # Poslab SavageBoard Dual - prt,prtrvt # Protonic RVT board - prt,prtvt7 # Protonic VT7 board + - rex,imx6dl-rex-basic # Rex Basic i.MX6 Dual Lite Board + - riot,imx6s-riotboard # RIoTboard i.MX6S + - solidrun,cubox-i/dl # SolidRun Cubox-i Solo/DualLite + - solidrun,hummingboard/dl + - solidrun,hummingboard2/dl # SolidRun HummingBoard2 Solo/DualLite - technexion,imx6dl-pico-dwarf # TechNexion i.MX6DL Pico-Dwarf - technexion,imx6dl-pico-hobbit # TechNexion i.MX6DL Pico-Hobbit - technexion,imx6dl-pico-nymph # TechNexion i.MX6DL Pico-Nymph - technexion,imx6dl-pico-pi # TechNexion i.MX6DL Pico-Pi - technologic,imx6dl-ts4900 - technologic,imx6dl-ts7970 - - toradex,colibri_imx6dl # Colibri iMX6 Module - - toradex,colibri_imx6dl-v1_1 # Colibri iMX6 Module V1.1 - - toradex,colibri_imx6dl-eval-v3 # Colibri iMX6 Module on Colibri Evaluation Board V3 - - toradex,colibri_imx6dl-v1_1-eval-v3 # Colibri iMX6 Module V1.1 on Colibri Evaluation Board V3 + - udoo,imx6dl-udoo # Udoo i.MX6 Dual-lite Board + - wand,imx6dl-wandboard # Wandboard i.MX6 Dual Lite Board - ysoft,imx6dl-yapp4-draco # i.MX6 DualLite Y Soft IOTA Draco board - ysoft,imx6dl-yapp4-hydra # i.MX6 DualLite Y Soft IOTA Hydra board - ysoft,imx6dl-yapp4-orion # i.MX6 DualLite Y Soft IOTA Orion board - ysoft,imx6dl-yapp4-ursa # i.MX6 Solo Y Soft IOTA Ursa board - const: fsl,imx6dl + - description: i.MX6DL based Armadeus AFP6 Board + items: + - const: armadeus,imx6dl-apf6dev + - const: armadeus,imx6dl-apf6 # APF6 (Solo) SoM + - const: fsl,imx6dl + + - description: i.MX6DL based DFI FS700-M60-6DL Board + items: + - const: dfi,fs700-m60-6dl + - const: dfi,fs700e-m60 + - const: fsl,imx6dl + - description: i.MX6DL Gateworks Ventana Boards items: - enum: @@ -330,6 +351,22 @@ properties: - const: phytec,imx6dl-pfla02 # PHYTEC phyFLEX-i.MX6 Quad - const: fsl,imx6dl + - description: i.MX6DL Toradex Colibri iMX6 Module on Colibri + Evaluation Board V3 + items: + - const: toradex,colibri_imx6dl-eval-v3 + - const: toradex,colibri_imx6dl # Colibri iMX6 Module + - const: fsl,imx6dl + + - description: i.MX6DL Toradex Colibri iMX6 Module V1.1 on Colibri + Evaluation Board V3 + items: + - const: toradex,colibri_imx6dl-v1_1-eval-v3 + - const: toradex,colibri_imx6dl-v1_1 # Colibri iMX6 Module V1.1 + - const: toradex,colibri_imx6dl-eval-v3 + - const: toradex,colibri_imx6dl # Colibri iMX6 Module + - const: fsl,imx6dl + - description: i.MX6SL based Boards items: - enum: From 5c32a75e2ed169c01e8af1e7f153e962c08763d8 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 30 Sep 2020 21:01:40 +0200 Subject: [PATCH 123/799] dt-bindings: vendor-prefixes: add ABB Document binding for ABB. Cc: Heiko Schocher Signed-off-by: Krzysztof Kozlowski Reviewed-by: Heiko Schocher Acked-by: Rob Herring Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index 39f0d7c074fe..5b0ec640cf49 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -25,6 +25,8 @@ patternProperties: # Keep list in alphabetical order. "^70mai,.*": description: 70mai Co., Ltd. + "^abb,.*": + description: ABB "^abilis,.*": description: Abilis Systems "^abracon,.*": From 676884326eeac5d6affbe3e13bb90d0de8f49cd2 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 30 Sep 2020 21:01:41 +0200 Subject: [PATCH 124/799] dt-bindings: arm: fsl: document i.MX6DL Aristainetos boards Document and adjust the compatibles for i.MX6DL based Aristainetos boards from ABB. Cc: Heiko Schocher Signed-off-by: Krzysztof Kozlowski Reviewed-by: Heiko Schocher Acked-by: Rob Herring Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/arm/fsl.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index f45e243916d8..05fe39fcdf5f 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -269,6 +269,10 @@ properties: - description: i.MX6DL based Boards items: - enum: + - abb,aristainetos-imx6dl-4 # aristainetos i.MX6 Dual Lite Board 4 + - abb,aristainetos-imx6dl-7 # aristainetos i.MX6 Dual Lite Board 7 + - abb,aristainetos2-imx6dl-4 # aristainetos2 i.MX6 Dual Lite Board 4 + - abb,aristainetos2-imx6dl-7 # aristainetos2 i.MX6 Dual Lite Board 7 - boundary,imx6dl-nit6xlite # Boundary Devices Nitrogen6 Lite - boundary,imx6dl-nitrogen6x # Boundary Devices Nitrogen6x - bticino,imx6dl-mamoj # BTicino i.MX6DL Mamoj From 5cad03883f1b96f4736027a5ee56a14e52cdfbc1 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 30 Sep 2020 21:01:39 +0200 Subject: [PATCH 125/799] ARM: dts: imx6dl-pico: fix board compatibles There are four flavors of TechNexion PICO-IMX6 boards. They have their own DTSes, even though in Dwarf, Nymph and Pi are exactly the same. They also have their own bindings so adjust the compatibles to match the bindings. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6dl-pico-dwarf.dts | 2 +- arch/arm/boot/dts/imx6dl-pico-hobbit.dts | 2 +- arch/arm/boot/dts/imx6dl-pico-nymph.dts | 2 +- arch/arm/boot/dts/imx6dl-pico-pi.dts | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/imx6dl-pico-dwarf.dts b/arch/arm/boot/dts/imx6dl-pico-dwarf.dts index 659a8e8714ea..d85b15a8c127 100644 --- a/arch/arm/boot/dts/imx6dl-pico-dwarf.dts +++ b/arch/arm/boot/dts/imx6dl-pico-dwarf.dts @@ -13,5 +13,5 @@ / { model = "TechNexion PICO-IMX6 DualLite/Solo Board and Dwarf baseboard"; - compatible = "technexion,imx6dl-pico", "fsl,imx6dl"; + compatible = "technexion,imx6dl-pico-dwarf", "fsl,imx6dl"; }; diff --git a/arch/arm/boot/dts/imx6dl-pico-hobbit.dts b/arch/arm/boot/dts/imx6dl-pico-hobbit.dts index d7403c5c4337..08fedcbcc91b 100644 --- a/arch/arm/boot/dts/imx6dl-pico-hobbit.dts +++ b/arch/arm/boot/dts/imx6dl-pico-hobbit.dts @@ -13,5 +13,5 @@ / { model = "TechNexion PICO-IMX6 DualLite/Solo Board and Hobbit baseboard"; - compatible = "technexion,imx6dl-pico", "fsl,imx6dl"; + compatible = "technexion,imx6dl-pico-hobbit", "fsl,imx6dl"; }; diff --git a/arch/arm/boot/dts/imx6dl-pico-nymph.dts b/arch/arm/boot/dts/imx6dl-pico-nymph.dts index b282dbf953aa..32ccfc5d41ce 100644 --- a/arch/arm/boot/dts/imx6dl-pico-nymph.dts +++ b/arch/arm/boot/dts/imx6dl-pico-nymph.dts @@ -13,5 +13,5 @@ / { model = "TechNexion PICO-IMX6 DualLite/Solo Board and Nymph baseboard"; - compatible = "technexion,imx6dl-pico", "fsl,imx6dl"; + compatible = "technexion,imx6dl-pico-nymph", "fsl,imx6dl"; }; diff --git a/arch/arm/boot/dts/imx6dl-pico-pi.dts b/arch/arm/boot/dts/imx6dl-pico-pi.dts index b7b1c07f96f3..4590e8ad9a91 100644 --- a/arch/arm/boot/dts/imx6dl-pico-pi.dts +++ b/arch/arm/boot/dts/imx6dl-pico-pi.dts @@ -13,5 +13,5 @@ / { model = "TechNexion PICO-IMX6 DualLite/Solo Board and PI baseboard"; - compatible = "technexion,imx6dl-pico", "fsl,imx6dl"; + compatible = "technexion,imx6dl-pico-pi", "fsl,imx6dl"; }; From 8fc8e8129e1aab1c7adfdb7c079eb0aa3d6f066b Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 30 Sep 2020 21:01:42 +0200 Subject: [PATCH 126/799] ARM: dts: imx6dl: add compatibles for Aristainetos boards The Aristainetos and Aristainetos2 boards have only SoC compatible. Cc: Heiko Schocher Signed-off-by: Krzysztof Kozlowski Reviewed-by: Heiko Schocher Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6dl-aristainetos2_4.dts | 2 +- arch/arm/boot/dts/imx6dl-aristainetos2_7.dts | 2 +- arch/arm/boot/dts/imx6dl-aristainetos_4.dts | 2 +- arch/arm/boot/dts/imx6dl-aristainetos_7.dts | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/imx6dl-aristainetos2_4.dts b/arch/arm/boot/dts/imx6dl-aristainetos2_4.dts index b16603f27dce..dfa6f64d43cc 100644 --- a/arch/arm/boot/dts/imx6dl-aristainetos2_4.dts +++ b/arch/arm/boot/dts/imx6dl-aristainetos2_4.dts @@ -46,7 +46,7 @@ / { model = "aristainetos2 i.MX6 Dual Lite Board 4"; - compatible = "fsl,imx6dl"; + compatible = "abb,aristainetos2-imx6dl-4", "fsl,imx6dl"; memory@10000000 { device_type = "memory"; diff --git a/arch/arm/boot/dts/imx6dl-aristainetos2_7.dts b/arch/arm/boot/dts/imx6dl-aristainetos2_7.dts index abb2a1b9ce08..5e15212eaf3a 100644 --- a/arch/arm/boot/dts/imx6dl-aristainetos2_7.dts +++ b/arch/arm/boot/dts/imx6dl-aristainetos2_7.dts @@ -46,7 +46,7 @@ / { model = "aristainetos2 i.MX6 Dual Lite Board 7"; - compatible = "fsl,imx6dl"; + compatible = "abb,aristainetos2-imx6dl-7", "fsl,imx6dl"; memory@10000000 { device_type = "memory"; diff --git a/arch/arm/boot/dts/imx6dl-aristainetos_4.dts b/arch/arm/boot/dts/imx6dl-aristainetos_4.dts index 5c7e85300695..cc861a43eb58 100644 --- a/arch/arm/boot/dts/imx6dl-aristainetos_4.dts +++ b/arch/arm/boot/dts/imx6dl-aristainetos_4.dts @@ -10,7 +10,7 @@ / { model = "aristainetos i.MX6 Dual Lite Board 4"; - compatible = "fsl,imx6dl"; + compatible = "abb,aristainetos-imx6dl-4", "fsl,imx6dl"; backlight { compatible = "pwm-backlight"; diff --git a/arch/arm/boot/dts/imx6dl-aristainetos_7.dts b/arch/arm/boot/dts/imx6dl-aristainetos_7.dts index 4d58cb4436d9..b6cb78870cd5 100644 --- a/arch/arm/boot/dts/imx6dl-aristainetos_7.dts +++ b/arch/arm/boot/dts/imx6dl-aristainetos_7.dts @@ -10,7 +10,7 @@ / { model = "aristainetos i.MX6 Dual Lite Board 7"; - compatible = "fsl,imx6dl"; + compatible = "abb,aristainetos-imx6dl-7", "fsl,imx6dl"; memory@10000000 { device_type = "memory"; From a687b55e10e9aaed1b1c9637771938db995cba52 Mon Sep 17 00:00:00 2001 From: Frieder Schrempf Date: Thu, 1 Oct 2020 17:13:38 +0200 Subject: [PATCH 127/799] dt-bindings: arm: fsl: Add Kontron i.MX8M Mini SoMs and boards Add entries for the SoMs and boards based on i.MX8MM from Kontron Electronics GmbH. Signed-off-by: Frieder Schrempf Reviewed-by: Rob Herring Reviewed-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/arm/fsl.yaml | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index 05fe39fcdf5f..25b3f43e3fd1 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -536,9 +536,16 @@ properties: - beacon,imx8mm-beacon-kit # i.MX8MM Beacon Development Kit - fsl,imx8mm-ddr4-evk # i.MX8MM DDR4 EVK Board - fsl,imx8mm-evk # i.MX8MM EVK Board + - kontron,imx8mm-n801x-som # i.MX8MM Kontron SL (N801X) SOM - variscite,var-som-mx8mm # i.MX8MM Variscite VAR-SOM-MX8MM module - const: fsl,imx8mm + - description: Kontron BL i.MX8MM (N801X S) Board + items: + - const: kontron,imx8mm-n801x-s + - const: kontron,imx8mm-n801x-som + - const: fsl,imx8mm + - description: Variscite VAR-SOM-MX8MM based boards items: - const: variscite,var-som-mx8mm-symphony From 8668d8b2e67fe7cf65f02becd5d67c0636689e82 Mon Sep 17 00:00:00 2001 From: Frieder Schrempf Date: Thu, 1 Oct 2020 17:13:37 +0200 Subject: [PATCH 128/799] arm64: dts: Add the Kontron i.MX8M Mini SoMs and baseboards Kontron Electronics GmbH offers small and powerful SoMs based on the i.MX8M Mini SoC including PMIC, LPDDR4-RAM, eMMC and SPI NOR. The matching baseboards have the same form factor and similar interfaces as the other boards from the Kontron "Board-Line" family, including SD card, 1G Ethernet, 100M Ethernet, USB Host/OTG, digital IOs, RS232, RS485, CAN, LVDS or HDMI, RTC and much more. Signed-off-by: Frieder Schrempf Reviewed-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/Makefile | 1 + .../dts/freescale/imx8mm-kontron-n801x-s.dts | 322 ++++++++++++++++++ .../freescale/imx8mm-kontron-n801x-som.dtsi | 294 ++++++++++++++++ 3 files changed, 617 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-s.dts create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-som.dtsi diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index f8d59433af01..e43254f1294d 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -31,6 +31,7 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-rdb.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-beacon-kit.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-ddr4-evk.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mm-kontron-n801x-s.dts dtb-$(CONFIG_ARCH_MXC) += imx8mm-var-som-symphony.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mn-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mn-ddr4-evk.dtb diff --git a/arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-s.dts b/arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-s.dts new file mode 100644 index 000000000000..d17abb515835 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-s.dts @@ -0,0 +1,322 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2019 Kontron Electronics GmbH + */ + +/dts-v1/; + +#include "imx8mm-kontron-n801x-som.dtsi" + +/ { + model = "Kontron i.MX8MM N801X S"; + compatible = "kontron,imx8mm-n801x-s", "kontron,imx8mm-n801x-som", "fsl,imx8mm"; + + aliases { + ethernet1 = &usbnet; + }; + + /* fixed crystal dedicated to mcp2515 */ + osc_can: clock-osc-can { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <16000000>; + clock-output-names = "osc-can"; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_led>; + + led1 { + label = "led1"; + gpios = <&gpio4 17 GPIO_ACTIVE_LOW>; + linux,default-trigger = "heartbeat"; + }; + + led2 { + label = "led2"; + gpios = <&gpio4 19 GPIO_ACTIVE_LOW>; + }; + + led3 { + label = "led3"; + gpios = <&gpio4 18 GPIO_ACTIVE_LOW>; + }; + + led4 { + label = "led4"; + gpios = <&gpio4 8 GPIO_ACTIVE_LOW>; + }; + + led5 { + label = "led5"; + gpios = <&gpio4 9 GPIO_ACTIVE_LOW>; + }; + + led6 { + label = "led6"; + gpios = <&gpio4 7 GPIO_ACTIVE_LOW>; + }; + }; + + pwm-beeper { + compatible = "pwm-beeper"; + pwms = <&pwm2 0 5000 0>; + }; + + reg_rst_eth2: regulator-rst-eth2 { + compatible = "regulator-fixed"; + regulator-name = "rst-usb-eth2"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_eth2>; + gpio = <&gpio3 2 GPIO_ACTIVE_LOW>; + }; + + reg_vdd_5v: regulator-5v { + compatible = "regulator-fixed"; + regulator-name = "vdd-5v"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; +}; + +&ecspi2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi2>; + cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; + status = "okay"; + + can0: can@0 { + compatible = "microchip,mcp2515"; + reg = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can>; + clocks = <&osc_can>; + interrupt-parent = <&gpio4>; + interrupts = <28 IRQ_TYPE_EDGE_FALLING>; + spi-max-frequency = <100000>; + vdd-supply = <®_vdd_3v3>; + xceiver-supply = <®_vdd_5v>; + }; +}; + +&ecspi3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi3>; + cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-connection-type = "rgmii"; + phy-handle = <ðphy>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy: ethernet-phy@0 { + reg = <0>; + reset-assert-us = <100>; + reset-deassert-us = <100>; + reset-gpios = <&gpio4 27 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&i2c4 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c4>; + status = "okay"; + + rtc@32 { + compatible = "epson,rx8900"; + reg = <0x32>; + }; +}; + +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm2>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + uart-has-rtscts; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + linux,rs485-enabled-at-boot-time; + uart-has-rtscts; + status = "okay"; +}; + +&usbotg1 { + dr_mode = "otg"; + over-current-active-low; + status = "okay"; +}; + +&usbotg2 { + dr_mode = "host"; + disable-over-current; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + usb1@1 { + compatible = "usb424,9514"; + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + usbnet: usbether@1 { + compatible = "usb424,ec00"; + reg = <1>; + local-mac-address = [ 00 00 00 00 00 00 ]; + }; + }; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + vmmc-supply = <®_vdd_3v3>; + vqmmc-supply = <®_nvcc_sd>; + cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio>; + + pinctrl_can: cangrp { + fsl,pins = < + MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x19 + >; + }; + + pinctrl_ecspi2: ecspi2grp { + fsl,pins = < + MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x82 + MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x82 + MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x82 + MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x19 + >; + }; + + pinctrl_ecspi3: ecspi3grp { + fsl,pins = < + MX8MM_IOMUXC_UART2_RXD_ECSPI3_MISO 0x82 + MX8MM_IOMUXC_UART1_TXD_ECSPI3_MOSI 0x82 + MX8MM_IOMUXC_UART1_RXD_ECSPI3_SCLK 0x82 + MX8MM_IOMUXC_UART2_TXD_GPIO5_IO25 0x19 + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3 + MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 + MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f + MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f + MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f + MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f + MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 + MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 + MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 + MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 + MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f + MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 + MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 + MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f + MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x19 /* PHY RST */ + MX8MM_IOMUXC_SAI2_TXC_GPIO4_IO25 0x19 /* ETH IRQ */ + >; + }; + + pinctrl_gpio_led: gpioledgrp { + fsl,pins = < + MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19 + MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x19 + MX8MM_IOMUXC_SAI1_RXD6_GPIO4_IO8 0x19 + MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x19 + MX8MM_IOMUXC_SAI1_TXD5_GPIO4_IO17 0x19 + MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x19 + MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x19 + >; + }; + + pinctrl_gpio: gpiogrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x19 + MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x19 + MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19 + MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x19 + MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x19 + MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x19 + MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x19 + MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x19 + >; + }; + + pinctrl_i2c4: i2c4grp { + fsl,pins = < + MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3 + MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3 + >; + }; + + pinctrl_pwm2: pwm2grp { + fsl,pins = < + MX8MM_IOMUXC_SPDIF_RX_PWM2_OUT 0x19 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX 0x140 + MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX 0x140 + MX8MM_IOMUXC_SAI2_RXD0_UART1_DCE_RTS_B 0x140 + MX8MM_IOMUXC_SAI2_TXFS_UART1_DCE_CTS_B 0x140 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x140 + MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x140 + MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x140 + MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x140 + >; + }; + + pinctrl_usb_eth2: usbeth2grp { + fsl,pins = < + MX8MM_IOMUXC_NAND_CE1_B_GPIO3_IO2 0x19 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 + MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x019 + >; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-som.dtsi new file mode 100644 index 000000000000..d0456daefda8 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-som.dtsi @@ -0,0 +1,294 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2019 Kontron Electronics GmbH + */ + +#include "imx8mm.dtsi" + +/ { + model = "Kontron i.MX8MM N801X SoM"; + compatible = "kontron,imx8mm-n801x-som", "fsl,imx8mm"; + + memory@40000000 { + device_type = "memory"; + /* + * There are multiple SoM flavors with different DDR sizes. + * The smallest is 1GB. For larger sizes the bootloader will + * update the reg property. + */ + reg = <0x0 0x40000000 0 0x80000000>; + }; + + chosen { + stdout-path = &uart3; + }; +}; + +&A53_0 { + cpu-supply = <®_vdd_arm>; +}; + +&A53_1 { + cpu-supply = <®_vdd_arm>; +}; + +&A53_2 { + cpu-supply = <®_vdd_arm>; +}; + +&A53_3 { + cpu-supply = <®_vdd_arm>; +}; + +&ddrc { + operating-points-v2 = <&ddrc_opp_table>; + + ddrc_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-25M { + opp-hz = /bits/ 64 <25000000>; + }; + + opp-100M { + opp-hz = /bits/ 64 <100000000>; + }; + + opp-750M { + opp-hz = /bits/ 64 <750000000>; + }; + }; +}; + +&ecspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + cs-gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>; + status = "okay"; + + spi-flash@0 { + compatible = "mxicy,mx25r1635f", "jedec,spi-nor"; + spi-max-frequency = <80000000>; + reg = <0>; + }; +}; + +&i2c1 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + pca9450: pmic@25 { + compatible = "nxp,pca9450a"; + reg = <0x25>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pmic>; + interrupt-parent = <&gpio1>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + + regulators { + reg_vdd_soc: BUCK1 { + regulator-name = "buck1"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <900000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + }; + + reg_vdd_arm: BUCK2 { + regulator-name = "buck2"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <950000>; + regulator-boot-on; + regulator-ramp-delay = <3125>; + nxp,dvs-run-voltage = <950000>; + nxp,dvs-standby-voltage = <850000>; + }; + + reg_vdd_dram: BUCK3 { + regulator-name = "buck3"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <900000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_vdd_3v3: BUCK4 { + regulator-name = "buck4"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_vdd_1v8: BUCK5 { + regulator-name = "buck5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_nvcc_dram: BUCK6 { + regulator-name = "buck6"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_nvcc_snvs: LDO1 { + regulator-name = "ldo1"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_vdd_snvs: LDO2 { + regulator-name = "ldo2"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <900000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_vdda: LDO3 { + regulator-name = "ldo3"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_vdd_phy: LDO4 { + regulator-name = "ldo4"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_nvcc_sd: LDO5 { + regulator-name = "ldo5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + }; + }; +}; + +&uart3 { /* console */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + vmmc-supply = <®_vdd_3v3>; + vqmmc-supply = <®_vdd_1v8>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; + +&iomuxc { + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x82 + MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x82 + MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x82 + MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x19 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 + MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 + >; + }; + + pinctrl_pmic: pmicgrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x141 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140 + MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190 + MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0 + MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0 + MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0 + MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0 + MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0 + MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d0 + MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d0 + MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d0 + MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d0 + MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x019 + MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x190 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { + fsl,pins = < + MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x194 + MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4 + MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4 + MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4 + MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4 + MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4 + MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d4 + MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d4 + MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d4 + MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d4 + MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x019 + MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x194 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { + fsl,pins = < + MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x196 + MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6 + MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6 + MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6 + MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6 + MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6 + MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d6 + MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d6 + MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d6 + MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d6 + MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x019 + MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x196 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 + >; + }; +}; From ea75e63105be661afc2e7fbe7f0af07d216af4cd Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 1 Oct 2020 19:07:48 +0200 Subject: [PATCH 129/799] dt-bindings: vendor-prefixes: add Element14 Document the binding for the Element14, a Premier Farnell company. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Rob Herring Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index 5b0ec640cf49..6f138271f003 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -317,6 +317,8 @@ patternProperties: description: Einfochips "^elan,.*": description: Elan Microelectronic Corp. + "^element14,.*": + description: Element14 (A Premier Farnell Company) "^elgin,.*": description: Elgin S/A. "^elida,.*": From bec0a8cbe303e41f07303d213ae6b70ed6aaa93c Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 1 Oct 2020 19:07:49 +0200 Subject: [PATCH 130/799] dt-bindings: arm: fsl: document i.MX6Q boards Document and adjust the compatibles for i.MX6Q based boards. The Toradex and the Armadeus boards use multiple compatibles. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Rob Herring Signed-off-by: Shawn Guo --- .../devicetree/bindings/arm/fsl.yaml | 83 +++++++++++++++++-- 1 file changed, 77 insertions(+), 6 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index 25b3f43e3fd1..3f0236263b55 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -191,29 +191,85 @@ properties: - description: i.MX6Q based Boards items: - enum: - - armadeus,imx6q-apf6 # APF6 (Quad/Dual) SoM - - armadeus,imx6q-apf6dev # APF6 (Quad/Dual) SoM on APF6Dev board + - auvidea,h100 # Auvidea H100 + - boundary,imx6q-nitrogen6_max + - boundary,imx6q-nitrogen6_som2 + - boundary,imx6q-nitrogen6x + - compulab,cm-fx6 # CompuLab CM-FX6 + - dmo,imx6q-edmqmx6 # Data Modul eDM-QMX6 Board + - embest,imx6q-marsboard # Embest MarS Board i.MX6Dual - emtrion,emcon-mx6 # emCON-MX6D or emCON-MX6Q SoM - emtrion,emcon-mx6-avari # emCON-MX6D or emCON-MX6Q SoM on Avari Base + - engicam,imx6-icore # Engicam i.CoreM6 Starter Kit + - engicam,imx6-icore-rqs # Engicam i.CoreM6 RQS Starter Kit - fsl,imx6q-arm2 - fsl,imx6q-sabreauto - fsl,imx6q-sabrelite - fsl,imx6q-sabresd + - karo,imx6q-tx6q # Ka-Ro electronics TX6Q Modules + - kiebackpeter,imx6q-tpc # K+P i.MX6 Quad TPC Board - kontron,imx6q-samx6i # Kontron i.MX6 Dual/Quad SMARC Module + - kosagi,imx6q-novena # Kosagi Novena Dual/Quad - logicpd,imx6q-logicpd + - lwn,display5 # Liebherr Display5 i.MX6 Quad Board + - lwn,mccmon6 # Liebherr Monitor6 i.MX6 Quad Board + - nutsboard,imx6q-pistachio # NutsBoard i.MX6 Quad Pistachio + - microsys,sbc6x # MicroSys sbc6x board + - poslab,imx6q-savageboard # Poslab SavageBoard Quad - prt,prti6q # Protonic PRTI6Q board - prt,prtwd2 # Protonic WD2 board + - rex,imx6q-rex-pro # Rex Pro i.MX6 Quad Board + - solidrun,cubox-i/q # SolidRun Cubox-i Dual/Quad + - solidrun,hummingboard/q + - solidrun,hummingboard2/q + - tbs,imx6q-tbs2910 # TBS2910 Matrix ARM mini PC - technexion,imx6q-pico-dwarf # TechNexion i.MX6Q Pico-Dwarf - technexion,imx6q-pico-hobbit # TechNexion i.MX6Q Pico-Hobbit - technexion,imx6q-pico-nymph # TechNexion i.MX6Q Pico-Nymph - technexion,imx6q-pico-pi # TechNexion i.MX6Q Pico-Pi - technologic,imx6q-ts4900 - technologic,imx6q-ts7970 - - toradex,apalis_imx6q # Apalis iMX6 Module - - toradex,apalis_imx6q-eval # Apalis iMX6 Module on Apalis Evaluation Board - - toradex,apalis_imx6q-ixora # Apalis iMX6 Module on Ixora - - toradex,apalis_imx6q-ixora-v1.1 # Apalis iMX6 Module on Ixora V1.1 + - toradex,apalis_imx6q # Apalis iMX6 Module + - udoo,imx6q-udoo # Udoo i.MX6 Quad Board + - uniwest,imx6q-evi # Uniwest Evi - variscite,dt6customboard + - wand,imx6q-wandboard # Wandboard i.MX6 Quad Board + - zealz,imx6q-gk802 # Zealz GK802 + - zii,imx6q-zii-rdu2 # ZII RDU2 Board + - const: fsl,imx6q + + - description: i.MX6Q Advantech DMS-BA16 Boards + items: + - enum: + - advantech,imx6q-dms-ba16 # Advantech DMS-BA16 + - ge,imx6q-b450v3 # General Electric B450v3 + - ge,imx6q-b650v3 # General Electric B650v3 + - ge,imx6q-b850v3 # General Electric B850v3 + - const: advantech,imx6q-ba16 + - const: fsl,imx6q + + - description: i.MX6Q Armadeus APF6 Boards + items: + - const: armadeus,imx6q-apf6dev + - const: armadeus,imx6q-apf6 + - const: fsl,imx6q + + - description: i.MX6Q CompuLab Utilite Pro Board + items: + - const: compulab,utilite-pro + - const: compulab,cm-fx6 + - const: fsl,imx6q + + - description: i.MX6Q DFI FS700-M60-6QD Board + items: + - const: dfi,fs700-m60-6qd + - const: dfi,fs700e-m60 + - const: fsl,imx6q + + - description: i.MX6Q DHCOM Premium Developer Kit Board + items: + - const: dh,imx6q-dhcom-pdk2 + - const: dh,imx6q-dhcom-som - const: fsl,imx6q - description: i.MX6Q Gateworks Ventana Boards @@ -252,6 +308,21 @@ properties: - const: phytec,imx6q-pfla02 # PHYTEC phyFLEX-i.MX6 Quad - const: fsl,imx6q + - description: i.MX6Q Boards with Toradex Apalis iMX6Q/D Module + items: + - enum: + - toradex,apalis_imx6q-ixora # Apalis iMX6Q/D Module on Ixora Carrier Board + - toradex,apalis_imx6q-eval # Apalis iMX6Q/D Module on Apalis Evaluation Board + - const: toradex,apalis_imx6q + - const: fsl,imx6q + + - description: i.MX6Q Toradex Apalis iMX6Q/D Module on Ixora Carrier Board V1.1 + items: + - const: toradex,apalis_imx6q-ixora-v1.1 + - const: toradex,apalis_imx6q-ixora + - const: toradex,apalis_imx6q + - const: fsl,imx6q + - description: i.MX6QP based Boards items: - enum: From 691dab655c32e70d1b6d62488d1273a0b196e783 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 1 Oct 2020 19:07:50 +0200 Subject: [PATCH 131/799] dt-bindings: arm: fsl: document i.MX6QP boards Document and adjust the compatibles for i.MX6QP based boards. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Rob Herring Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/arm/fsl.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index 3f0236263b55..0bcc3be4b7c5 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -326,8 +326,13 @@ properties: - description: i.MX6QP based Boards items: - enum: + - boundary,imx6qp-nitrogen6_max + - boundary,imx6qp-nitrogen6_som2 - fsl,imx6qp-sabreauto # i.MX6 Quad Plus SABRE Automotive Board - fsl,imx6qp-sabresd # i.MX6 Quad Plus SABRE Smart Device Board + - karo,imx6qp-tx6qp # Ka-Ro electronics TX6QP-8037 Module + - wand,imx6qp-wandboard # Wandboard i.MX6 QuadPlus Board + - zii,imx6qp-zii-rdu2 # ZII RDU2+ Board - const: fsl,imx6qp - description: i.MX6QP PHYTEC phyBOARD-Mira From 9fa659393ab139705669e14f615cfe665113eb5f Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 1 Oct 2020 19:07:51 +0200 Subject: [PATCH 132/799] dt-bindings: arm: fsl: document i.MX6SL boards Document and adjust the compatibles for i.MX6SL based boards. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Rob Herring Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/arm/fsl.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index 0bcc3be4b7c5..92a72edeb022 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -453,6 +453,7 @@ properties: - fsl,imx6sl-evk # i.MX6 SoloLite EVK Board - kobo,tolino-shine2hd - kobo,tolino-shine3 + - revotics,imx6sl-warp # Revotics WaRP Board - const: fsl,imx6sl - description: i.MX6SLL based Boards From d59dca0dff43a69874e0b4a8c0eb84f136928daf Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 1 Oct 2020 19:07:52 +0200 Subject: [PATCH 133/799] dt-bindings: arm: fsl: document i.MX6SX boards Document and adjust the compatibles for i.MX6SX based boards. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Rob Herring Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/arm/fsl.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index 92a72edeb022..20bbe19aa6a9 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -466,9 +466,14 @@ properties: - description: i.MX6SX based Boards items: - enum: + - boundary,imx6sx-nitrogen6sx - fsl,imx6sx-sabreauto # i.MX6 SoloX Sabre Auto Board - fsl,imx6sx-sdb # i.MX6 SoloX SDB Board - fsl,imx6sx-sdb-reva # i.MX6 SoloX SDB Rev-A Board + - samtec,imx6sx-vining-2000 # Softing VIN|ING 2000 Board + - udoo,neobasic # UDOO Neo Basic Board + - udoo,neoextended # UDOO Neo Extended + - udoo,neofull # UDOO Neo Full - const: fsl,imx6sx - description: i.MX6UL based Boards From f7c7c45d1e0eb7f44c1661e1c80c87e001aaeb60 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 1 Oct 2020 19:07:53 +0200 Subject: [PATCH 134/799] dt-bindings: arm: fsl: document i.MX6UL boards Document and adjust the compatibles for i.MX6UL based boards. The Armadeus boards use multiple compatibles. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Rob Herring Signed-off-by: Shawn Guo --- .../devicetree/bindings/arm/fsl.yaml | 25 +++++++++++++++++-- 1 file changed, 23 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index 20bbe19aa6a9..fcd9c150a715 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -479,9 +479,10 @@ properties: - description: i.MX6UL based Boards items: - enum: - - armadeus,imx6ul-opos6ul # OPOS6UL (i.MX6UL) SoM - - armadeus,imx6ul-opos6uldev # OPOS6UL (i.MX6UL) SoM on OPOS6ULDev board + - engicam,imx6ul-geam # Engicam GEAM6UL Starter Kit + - engicam,imx6ul-isiot # Engicam Is.IoT MX6UL eMMC/NAND Starter kit - fsl,imx6ul-14x14-evk # i.MX6 UltraLite 14x14 EVK Board + - karo,imx6ul-tx6ul # Ka-Ro electronics TXUL-0010 Module - kontron,imx6ul-n6310-som # Kontron N6310 SOM - kontron,imx6ul-n6311-som # Kontron N6311 SOM - technexion,imx6ul-pico-dwarf # TechNexion i.MX6UL Pico-Dwarf @@ -489,6 +490,26 @@ properties: - technexion,imx6ul-pico-pi # TechNexion i.MX6UL Pico-Pi - const: fsl,imx6ul + - description: i.MX6UL Armadeus Systems OPOS6UL SoM Board + items: + - const: armadeus,imx6ul-opos6uldev # OPOS6UL (i.MX6UL) SoM on OPOS6ULDev board + - const: armadeus,imx6ul-opos6ul # OPOS6UL (i.MX6UL) SoM + - const: fsl,imx6ul + + - description: i.MX6UL Digi International ConnectCore 6UL Boards + items: + - enum: + - digi,ccimx6ulsbcexpress # Digi International ConnectCore 6UL SBC Express + - digi,ccimx6ulsbcpro # Digi International ConnectCore 6UL SBC Pro + - const: digi,ccimx6ulsom + - const: fsl,imx6ul + + - description: i.MX6UL Grinn liteBoard + items: + - const: grinn,imx6ul-liteboard + - const: grinn,imx6ul-litesom + - const: fsl,imx6ul + - description: i.MX6UL PHYTEC phyBOARD-Segin items: - enum: From 156b4a654019134c16343dbaaf10e585b42c15ce Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 1 Oct 2020 19:07:54 +0200 Subject: [PATCH 135/799] dt-bindings: arm: fsl: document i.MX6ULL boards Document and adjust the compatibles for i.MX6ULL based boards. The Armadeus boards use multiple compatibles. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Rob Herring Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/arm/fsl.yaml | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index fcd9c150a715..53e389417738 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -541,8 +541,6 @@ properties: - description: i.MX6ULL based Boards items: - enum: - - armadeus,imx6ull-opos6ul # OPOS6UL (i.MX6ULL) SoM - - armadeus,imx6ull-opos6uldev # OPOS6UL (i.MX6ULL) SoM on OPOS6ULDev board - fsl,imx6ull-14x14-evk # i.MX6 UltraLiteLite 14x14 EVK Board - kontron,imx6ull-n6411-som # Kontron N6411 SOM - myir,imx6ull-mys-6ulx-eval # MYiR Tech iMX6ULL Evaluation Board @@ -550,6 +548,12 @@ properties: - toradex,colibri-imx6ull-wifi-eval # Colibri iMX6ULL Wi-Fi / BT Module on Colibri Eval Board - const: fsl,imx6ull + - description: i.MX6ULL Armadeus Systems OPOS6ULDev Board + items: + - const: armadeus,imx6ull-opos6uldev # OPOS6UL (i.MX6ULL) SoM on OPOS6ULDev board + - const: armadeus,imx6ull-opos6ul # OPOS6UL (i.MX6ULL) SoM + - const: fsl,imx6ull + - description: i.MX6ULL PHYTEC phyBOARD-Segin items: - enum: From da2a602c03cd6bb8d0417fb35ae7c26ed04028ea Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 1 Oct 2020 19:07:56 +0200 Subject: [PATCH 136/799] dt-bindings: arm: fsl: document i.MX7D boards Document and adjust the compatibles for i.MX7D based boards. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Rob Herring Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/arm/fsl.yaml | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index 53e389417738..417b5634d3f1 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -593,6 +593,8 @@ properties: - description: i.MX7D based Boards items: - enum: + - boundary,imx7d-nitrogen7 + - compulab,cl-som-imx7 # CompuLab CL-SOM-iMX7 - fsl,imx7d-sdb # i.MX7 SabreSD Board - fsl,imx7d-sdb-reva # i.MX7 SabreSD Rev-A Board - novtech,imx7d-meerkat96 # i.MX7 Meerkat96 Board @@ -630,6 +632,22 @@ properties: - const: compulab,cl-som-imx7 - const: fsl,imx7d + - description: i.MX7D Boards with Toradex Colibri i.MX7D Module + items: + - enum: + - toradex,colibri-imx7d-aster # Module on Aster Carrier Board + - toradex,colibri-imx7d-eval-v3 # Module on Colibri Evaluation Board V3 + - const: toradex,colibri-imx7d + - const: fsl,imx7d + + - description: i.MX7D Boards with Toradex Colibri i.MX7D eMMC Module + items: + - enum: + - toradex,colibri-imx7d-emmc-aster # Module on Aster Carrier Board + - toradex,colibri-imx7d-emmc-eval-v3 # Module on Colibri Evaluation Board V3 + - const: toradex,colibri-imx7d-emmc + - const: fsl,imx7d + - description: i.MX7ULP based Boards items: - enum: From ef8b31051a85773fd4d5c3afb78d5f172affb256 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 1 Oct 2020 19:07:58 +0200 Subject: [PATCH 137/799] ARM: dts: imx6sl-warp: correct vendor in compatible to Revotics The WaRP board (Wearable Development Platform) was apparently made by Revolution Robotics, Inc (brand: Revotics), not by "Warp". Correct the vendor in compatible to reflect this. The compatibles were not documented in the bindings before. Link: https://revotics.com/warp Signed-off-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6sl-warp.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/imx6sl-warp.dts b/arch/arm/boot/dts/imx6sl-warp.dts index 408da704c459..9d7c8884892a 100644 --- a/arch/arm/boot/dts/imx6sl-warp.dts +++ b/arch/arm/boot/dts/imx6sl-warp.dts @@ -51,8 +51,8 @@ #include "imx6sl.dtsi" / { - model = "WaRP Board"; - compatible = "warp,imx6sl-warp", "fsl,imx6sl"; + model = "Revotics WaRP Board"; + compatible = "revotics,imx6sl-warp", "fsl,imx6sl"; memory@80000000 { device_type = "memory"; From a486d18c0a14649bc86052431b9f3eb88bcb0e15 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 1 Oct 2020 19:07:59 +0200 Subject: [PATCH 138/799] ARM: dts: imx7s-warp: correct vendor in compatible to Element14 The WaRP7 board (Wearable Development Platform) was apparently made by Element14, not by "Warp". Correct the vendor in compatible to reflect this. The compatibles were not documented in the bindings before. Link: https://www.element14.com/community/docs/DOC-79058 Signed-off-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx7s-warp.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/imx7s-warp.dts b/arch/arm/boot/dts/imx7s-warp.dts index d6b4888fa686..569bbd84e371 100644 --- a/arch/arm/boot/dts/imx7s-warp.dts +++ b/arch/arm/boot/dts/imx7s-warp.dts @@ -10,8 +10,8 @@ #include "imx7s.dtsi" / { - model = "Warp i.MX7 Board"; - compatible = "warp,imx7s-warp", "fsl,imx7s"; + model = "Element14 Warp i.MX7 Board"; + compatible = "element14,imx7s-warp", "fsl,imx7s"; memory@80000000 { device_type = "memory"; From 97f1dd5ba28f45f1fd41285dc713c7cf391f2cd7 Mon Sep 17 00:00:00 2001 From: Alexander Dahl Date: Mon, 5 Oct 2020 22:34:47 +0200 Subject: [PATCH 139/799] ARM: dts: imx: Fix schema warnings for pwm-leds The node names for devices using the pwm-leds driver follow a certain naming scheme (now). Parent node name is not enforced, but recommended by DT project. DTC arch/arm/boot/dts/imx53-ppd.dt.yaml CHECK arch/arm/boot/dts/imx53-ppd.dt.yaml arch/arm/boot/dts/imx53-ppd.dt.yaml: leds-brightness: 'alarm-brightness' does not match any of the regexes: '^led(-[0-9a-f]+)?$', 'pinctrl-[0-9]+' From schema: Documentation/devicetree/bindings/leds/leds-pwm.yaml DTC arch/arm/boot/dts/imx6dl-cubox-i.dt.yaml CHECK arch/arm/boot/dts/imx6dl-cubox-i.dt.yaml arch/arm/boot/dts/imx6dl-cubox-i.dt.yaml: pwmleds: 'front' does not match any of the regexes: '^led(-[0-9a-f]+)?$', 'pinctrl-[0-9]+' From schema: Documentation/devicetree/bindings/leds/leds-pwm.yaml DTC arch/arm/boot/dts/imx6dl-cubox-i-emmc-som-v15.dt.yaml CHECK arch/arm/boot/dts/imx6dl-cubox-i-emmc-som-v15.dt.yaml arch/arm/boot/dts/imx6dl-cubox-i-emmc-som-v15.dt.yaml: pwmleds: 'front' does not match any of the regexes: '^led(-[0-9a-f]+)?$', 'pinctrl-[0-9]+' From schema: Documentation/devicetree/bindings/leds/leds-pwm.yaml DTC arch/arm/boot/dts/imx6dl-cubox-i-som-v15.dt.yaml CHECK arch/arm/boot/dts/imx6dl-cubox-i-som-v15.dt.yaml arch/arm/boot/dts/imx6dl-cubox-i-som-v15.dt.yaml: pwmleds: 'front' does not match any of the regexes: '^led(-[0-9a-f]+)?$', 'pinctrl-[0-9]+' From schema: Documentation/devicetree/bindings/leds/leds-pwm.yaml DTC arch/arm/boot/dts/imx6sx-softing-vining-2000.dt.yaml CHECK arch/arm/boot/dts/imx6sx-softing-vining-2000.dt.yaml arch/arm/boot/dts/imx6sx-softing-vining-2000.dt.yaml: pwmleds: 'blue', 'green', 'red' do not match any of the regexes: '^led(-[0-9a-f]+)?$', 'pinctrl-[0-9]+' From schema: Documentation/devicetree/bindings/leds/leds-pwm.yaml Signed-off-by: Alexander Dahl Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx53-ppd.dts | 15 ++++++++------- arch/arm/boot/dts/imx6qdl-cubox-i.dtsi | 4 ++-- arch/arm/boot/dts/imx6sx-softing-vining-2000.dts | 8 ++++---- 3 files changed, 14 insertions(+), 13 deletions(-) diff --git a/arch/arm/boot/dts/imx53-ppd.dts b/arch/arm/boot/dts/imx53-ppd.dts index f7dcdf96e5c0..b480614efb30 100644 --- a/arch/arm/boot/dts/imx53-ppd.dts +++ b/arch/arm/boot/dts/imx53-ppd.dts @@ -176,36 +176,37 @@ power-supply = <®_3v3_lcd>; }; - leds-brightness { + led-controller-1 { compatible = "pwm-leds"; - alarm-brightness { + led-1 { + label = "alarm-brightness"; pwms = <&pwm1 0 100000>; max-brightness = <255>; }; }; - leds { + led-controller-2 { compatible = "gpio-leds"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_alarmled_pins>; - alarm1 { + led-2 { label = "alarm:red"; gpios = <&gpio7 3 GPIO_ACTIVE_HIGH>; }; - alarm2 { + led-3 { label = "alarm:yellow"; gpios = <&gpio7 7 GPIO_ACTIVE_HIGH>; }; - alarm3 { + led-4 { label = "alarm:blue"; gpios = <&gpio7 8 GPIO_ACTIVE_HIGH>; }; - alarm4 { + led-5 { label = "alarm:silenced"; gpios = <&gpio7 13 GPIO_ACTIVE_HIGH>; }; diff --git a/arch/arm/boot/dts/imx6qdl-cubox-i.dtsi b/arch/arm/boot/dts/imx6qdl-cubox-i.dtsi index 67042793b0ca..1e530d892b76 100644 --- a/arch/arm/boot/dts/imx6qdl-cubox-i.dtsi +++ b/arch/arm/boot/dts/imx6qdl-cubox-i.dtsi @@ -55,12 +55,12 @@ pinctrl-0 = <&pinctrl_cubox_i_ir>; }; - pwmleds { + led-controller { compatible = "pwm-leds"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_cubox_i_pwm1>; - front { + led-1 { active-low; label = "imx6:red:front"; max-brightness = <248>; diff --git a/arch/arm/boot/dts/imx6sx-softing-vining-2000.dts b/arch/arm/boot/dts/imx6sx-softing-vining-2000.dts index 5547916870c7..b9a1401e6c6d 100644 --- a/arch/arm/boot/dts/imx6sx-softing-vining-2000.dts +++ b/arch/arm/boot/dts/imx6sx-softing-vining-2000.dts @@ -40,22 +40,22 @@ regulator-max-microvolt = <3300000>; }; - pwmleds { + led-controller { compatible = "pwm-leds"; - red { + led-1 { label = "red"; max-brightness = <255>; pwms = <&pwm6 0 50000>; }; - green { + led-2 { label = "green"; max-brightness = <255>; pwms = <&pwm2 0 50000>; }; - blue { + led-3 { label = "blue"; max-brightness = <255>; pwms = <&pwm1 0 50000>; From 56c6b4ddfd503ff4de31462c92a187ee440b796e Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Wed, 7 Oct 2020 09:04:57 -0500 Subject: [PATCH 140/799] arm64: dts: imx8mm-beacon-som: Configure supplies on secondary cpus Each cpu core should have a corresponding supply, but only cpu0 does. This patch adds a supply for each of the secondary cpus. Signed-off-by: Adam Ford Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi index 6de86a4f0ec4..0b8c4e4ad45b 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi @@ -24,6 +24,18 @@ cpu-supply = <&buck2_reg>; }; +&A53_1 { + cpu-supply = <&buck2_reg>; +}; + +&A53_2 { + cpu-supply = <&buck2_reg>; +}; + +&A53_3 { + cpu-supply = <&buck2_reg>; +}; + &ddrc { operating-points-v2 = <&ddrc_opp_table>; From 582b6d8b258d5bdc2dfde133145dc90fb9fea5e0 Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Wed, 7 Oct 2020 09:24:08 -0500 Subject: [PATCH 141/799] arm64: dts: imx8mm-beacon-som: Add QSPI NOR flash support imx8mm-beacon-som has a Quad-SPI NOR flash connected to the FlexSPI bus. This patch enables the FlexSPI bus and configures it to work with the flash part. Signed-off-by: Adam Ford Signed-off-by: Shawn Guo --- .../boot/dts/freescale/imx8mm-beacon-som.dtsi | 27 +++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi index 0b8c4e4ad45b..09ad2d71b8b3 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi @@ -75,6 +75,22 @@ }; }; +&flexspi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi>; + status = "okay"; + + flash@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <80000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + }; +}; + &i2c1 { clock-frequency = <400000>; pinctrl-names = "default"; @@ -302,6 +318,17 @@ >; }; + pinctrl_flexspi: flexspigrp { + fsl,pins = < + MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c2 + MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82 + MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82 + MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82 + MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82 + MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82 + >; + }; + pinctrl_pmic: pmicirqgrp { fsl,pins = < MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x141 From 87e218ae976eeffe660aaae2c90e78d3f514f39a Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 2 Oct 2020 18:39:40 +0200 Subject: [PATCH 142/799] arm64: dts: mediatek: align GPIO hog names with dtschema The convention for node names is to use hyphens, not underscores. dtschema for pca95xx expects GPIO hogs to end with 'hog' suffix. Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20201002163940.7837-1-krzk@kernel.org Signed-off-by: Matthias Brugger --- .../boot/dts/mediatek/pumpkin-common.dtsi | 26 +++++++++---------- 1 file changed, 13 insertions(+), 13 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/pumpkin-common.dtsi b/arch/arm64/boot/dts/mediatek/pumpkin-common.dtsi index 3e5a8dfda0c0..63fd70086bb8 100644 --- a/arch/arm64/boot/dts/mediatek/pumpkin-common.dtsi +++ b/arch/arm64/boot/dts/mediatek/pumpkin-common.dtsi @@ -63,91 +63,91 @@ gpio-controller; #gpio-cells = <2>; - eint20_mux_sel0 { + eint20-mux-sel0-hog { gpio-hog; gpios = <0 0>; input; line-name = "eint20_mux_sel0"; }; - expcon_mux_sel1 { + expcon-mux-sel1-hog { gpio-hog; gpios = <1 0>; input; line-name = "expcon_mux_sel1"; }; - mrg_di_mux_sel2 { + mrg-di-mux-sel2-hog { gpio-hog; gpios = <2 0>; input; line-name = "mrg_di_mux_sel2"; }; - sd_sdio_mux_sel3 { + sd-sdio-mux-sel3-hog { gpio-hog; gpios = <3 0>; input; line-name = "sd_sdio_mux_sel3"; }; - sd_sdio_mux_ctrl7 { + sd-sdio-mux-ctrl7-hog { gpio-hog; gpios = <7 0>; output-low; line-name = "sd_sdio_mux_ctrl7"; }; - hw_id0 { + hw-id0-hog { gpio-hog; gpios = <8 0>; input; line-name = "hw_id0"; }; - hw_id1 { + hw-id1-hog { gpio-hog; gpios = <9 0>; input; line-name = "hw_id1"; }; - hw_id2 { + hw-id2-hog { gpio-hog; gpios = <10 0>; input; line-name = "hw_id2"; }; - fg_int_n { + fg-int-n-hog { gpio-hog; gpios = <11 0>; input; line-name = "fg_int_n"; }; - usba_pwr_en { + usba-pwr-en-hog { gpio-hog; gpios = <12 0>; output-high; line-name = "usba_pwr_en"; }; - wifi_3v3_pg { + wifi-3v3-pg-hog { gpio-hog; gpios = <13 0>; input; line-name = "wifi_3v3_pg"; }; - cam_rst { + cam-rst-hog { gpio-hog; gpios = <14 0>; output-low; line-name = "cam_rst"; }; - cam_pwdn { + cam-pwdn-hog { gpio-hog; gpios = <15 0>; output-low; From b781820927c5fb0dacb2ef986b33e9b3cfc41930 Mon Sep 17 00:00:00 2001 From: Anson Huang Date: Mon, 12 Oct 2020 20:44:00 +0800 Subject: [PATCH 143/799] arm64: dts: imx8mm: Correct WDOG_B pin configuration Different revision of i.MX8MM EVK boards may have different external pull up registor design, some are enabled while some are NOT, to make sure the WDOG_B pin works properly, better to enable internal pull up resistor. Since enabling internal pull up resistor is NOT harmful and having benefit of flexibility on different board design, just enable it for all i.MX8MM boards; And schmitt input is NOT necessary for this WDOG_B output pin, so remove it; Open drain outputs provide more flexibility to a designer as they can be pulled-up to any voltage found in the system, so enable it as well. Signed-off-by: Anson Huang Reviewed-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi | 2 +- arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi | 2 +- arch/arm64/boot/dts/freescale/imx8mm-var-som.dtsi | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi index 09ad2d71b8b3..c74e006ad0e8 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi @@ -437,7 +437,7 @@ pinctrl_wdog: wdoggrp { fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 + MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x166 >; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi index f305a530ff6f..469d5703250b 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi @@ -468,7 +468,7 @@ pinctrl_wdog: wdoggrp { fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 + MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x166 >; }; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-var-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-var-som.dtsi index 4107fe914d08..38e879d32560 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-var-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-var-som.dtsi @@ -555,7 +555,7 @@ pinctrl_wdog: wdoggrp { fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 + MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x166 >; }; }; From fa88e6e406c3c8ae9cd7f3434c6c4e4b103cb19e Mon Sep 17 00:00:00 2001 From: Anson Huang Date: Mon, 12 Oct 2020 20:44:01 +0800 Subject: [PATCH 144/799] arm64: dts: imx8mn: Correct WDOG_B pin configuration Different revision of i.MX8MN EVK boards may have different external pull up registor design, some are enabled while some are NOT, to make sure the WDOG_B pin works properly, better to enable internal pull up resistor. Since enabling internal pull up resistor is NOT harmful and having benefit of flexibility on different board design, just enable it for all i.MX8MN boards; And schmitt input is NOT necessary for this WDOG_B output pin, so remove it; Open drain outputs provide more flexibility to a designer as they can be pulled-up to any voltage found in the system, so enable it as well. Signed-off-by: Anson Huang Reviewed-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi | 2 +- arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi index 4aa0dbd578df..fda890589a09 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi @@ -340,7 +340,7 @@ pinctrl_wdog: wdoggrp { fsl,pins = < - MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 + MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x166 >; }; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi index a2d0190921e4..dde01daab62e 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi @@ -545,7 +545,7 @@ pinctrl_wdog: wdoggrp { fsl,pins = < - MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 + MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x166 >; }; }; From fa15cec9cc319d276dc5f4b89b7f1119ea9d013d Mon Sep 17 00:00:00 2001 From: Anson Huang Date: Mon, 12 Oct 2020 20:44:02 +0800 Subject: [PATCH 145/799] arm64: dts: imx8mp-evk: Correct WDOG_B pin configuration Different revision of i.MX8MP EVK boards may have different external pull up registor design, some are enabled while some are NOT, to make sure the WDOG_B pin works properly, better to enable internal pull up resistor. Since enabling internal pull up resistor is NOT harmful and having benefit of flexibility on different board design, just enable it for all i.MX8MP boards; And schmitt input is NOT necessary for this WDOG_B output pin, so remove it; Open drain outputs provide more flexibility to a designer as they can be pulled-up to any voltage found in the system, so enable it as well. Signed-off-by: Anson Huang Reviewed-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts index ad66f1286d95..908b92bb4dcd 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts @@ -262,7 +262,7 @@ pinctrl_wdog: wdoggrp { fsl,pins = < - MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xc6 + MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x166 >; }; }; From 73db215119963918afe446c6cec76e2d421aa33c Mon Sep 17 00:00:00 2001 From: Oleksij Rempel Date: Fri, 16 Oct 2020 09:51:58 +0200 Subject: [PATCH 146/799] ARM: dts: imx6/7: sync fsl,stop-mode with current flexcan driver After this patch we need 2 arguments less for the fsl,stop-mode property: | commit d9b081e3fc4bdc33e672dcb7bb256394909432fc | Author: Marc Kleine-Budde | Date: Sun Jun 14 21:09:20 2020 +0200 | | can: flexcan: remove ack_grp and ack_bit handling from driver | | Since commit: | | 048e3a34a2e7 can: flexcan: poll MCR_LPM_ACK instead of GPR ACK for stop mode acknowledgment | | the driver polls the IP core's internal bit MCR[LPM_ACK] as stop mode | acknowledge and not the acknowledgment on chip level. | | This means the 4th and 5th value of the property "fsl,stop-mode" isn't used | anymore. This patch removes the used "ack_gpr" and "ack_bit" from the driver. This patch removes the two last arguments, as they are not needed anymore. Signed-off-by: Oleksij Rempel Reviewed-by: Joakim Zhang Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl.dtsi | 4 ++-- arch/arm/boot/dts/imx6sx.dtsi | 4 ++-- arch/arm/boot/dts/imx6ul.dtsi | 4 ++-- arch/arm/boot/dts/imx7s.dtsi | 4 ++-- 4 files changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi index 7a8837cbe21b..bc98b63922b0 100644 --- a/arch/arm/boot/dts/imx6qdl.dtsi +++ b/arch/arm/boot/dts/imx6qdl.dtsi @@ -549,7 +549,7 @@ clocks = <&clks IMX6QDL_CLK_CAN1_IPG>, <&clks IMX6QDL_CLK_CAN1_SERIAL>; clock-names = "ipg", "per"; - fsl,stop-mode = <&gpr 0x34 28 0x10 17>; + fsl,stop-mode = <&gpr 0x34 28>; status = "disabled"; }; @@ -560,7 +560,7 @@ clocks = <&clks IMX6QDL_CLK_CAN2_IPG>, <&clks IMX6QDL_CLK_CAN2_SERIAL>; clock-names = "ipg", "per"; - fsl,stop-mode = <&gpr 0x34 29 0x10 18>; + fsl,stop-mode = <&gpr 0x34 29>; status = "disabled"; }; diff --git a/arch/arm/boot/dts/imx6sx.dtsi b/arch/arm/boot/dts/imx6sx.dtsi index dfdca1804f9f..6c604c38c790 100644 --- a/arch/arm/boot/dts/imx6sx.dtsi +++ b/arch/arm/boot/dts/imx6sx.dtsi @@ -463,7 +463,7 @@ clocks = <&clks IMX6SX_CLK_CAN1_IPG>, <&clks IMX6SX_CLK_CAN1_SERIAL>; clock-names = "ipg", "per"; - fsl,stop-mode = <&gpr 0x10 1 0x10 17>; + fsl,stop-mode = <&gpr 0x10 1>; status = "disabled"; }; @@ -474,7 +474,7 @@ clocks = <&clks IMX6SX_CLK_CAN2_IPG>, <&clks IMX6SX_CLK_CAN2_SERIAL>; clock-names = "ipg", "per"; - fsl,stop-mode = <&gpr 0x10 2 0x10 18>; + fsl,stop-mode = <&gpr 0x10 2>; status = "disabled"; }; diff --git a/arch/arm/boot/dts/imx6ul.dtsi b/arch/arm/boot/dts/imx6ul.dtsi index d7d9f3e46b92..713a4bb341db 100644 --- a/arch/arm/boot/dts/imx6ul.dtsi +++ b/arch/arm/boot/dts/imx6ul.dtsi @@ -430,7 +430,7 @@ clocks = <&clks IMX6UL_CLK_CAN1_IPG>, <&clks IMX6UL_CLK_CAN1_SERIAL>; clock-names = "ipg", "per"; - fsl,stop-mode = <&gpr 0x10 1 0x10 17>; + fsl,stop-mode = <&gpr 0x10 1>; status = "disabled"; }; @@ -441,7 +441,7 @@ clocks = <&clks IMX6UL_CLK_CAN2_IPG>, <&clks IMX6UL_CLK_CAN2_SERIAL>; clock-names = "ipg", "per"; - fsl,stop-mode = <&gpr 0x10 2 0x10 18>; + fsl,stop-mode = <&gpr 0x10 2>; status = "disabled"; }; diff --git a/arch/arm/boot/dts/imx7s.dtsi b/arch/arm/boot/dts/imx7s.dtsi index 84d9cc13afb9..b58262acba11 100644 --- a/arch/arm/boot/dts/imx7s.dtsi +++ b/arch/arm/boot/dts/imx7s.dtsi @@ -971,7 +971,7 @@ clocks = <&clks IMX7D_CLK_DUMMY>, <&clks IMX7D_CAN1_ROOT_CLK>; clock-names = "ipg", "per"; - fsl,stop-mode = <&gpr 0x10 1 0x10 17>; + fsl,stop-mode = <&gpr 0x10 1>; status = "disabled"; }; @@ -982,7 +982,7 @@ clocks = <&clks IMX7D_CLK_DUMMY>, <&clks IMX7D_CAN2_ROOT_CLK>; clock-names = "ipg", "per"; - fsl,stop-mode = <&gpr 0x10 2 0x10 18>; + fsl,stop-mode = <&gpr 0x10 2>; status = "disabled"; }; From 338d3c474b90738ef407bd0efca706118b0e06cc Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Mon, 19 Oct 2020 11:50:38 -0500 Subject: [PATCH 147/799] arm64: defconfig: Enable additional sound drivers on i.MX8M Mini The i.MX8M Mini has micfil and SPDIF support but the drivers are not being loaded. This patch updates the defconfig to add support for these drivers. Signed-off-by: Adam Ford Reviewed-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- arch/arm64/configs/defconfig | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 17a2df6a263e..844d8817e6f4 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -694,6 +694,10 @@ CONFIG_SND_HDA_CODEC_HDMI=m CONFIG_SND_SOC=y CONFIG_SND_BCM2835_SOC_I2S=m CONFIG_SND_SOC_FSL_SAI=m +CONFIG_SND_SOC_FSL_MICFIL=m +CONFIG_SND_IMX_SOC=m +CONFIG_SND_SOC_IMX_SPDIF=m +CONFIG_SND_SOC_IMX_AUDMIX=m CONFIG_SND_MESON_AXG_SOUND_CARD=m CONFIG_SND_MESON_GX_SOUND_CARD=m CONFIG_SND_SOC_QCOM=m From 3bd0788c43d97293a4630e2f36ab31520db16a4a Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Mon, 19 Oct 2020 11:50:36 -0500 Subject: [PATCH 148/799] arm64: dts: imx8mm: Add support for micfil The i.MX8M Mini has supports the MICFIL digital interface. It's a 16-bit audio signal from a PDM microphone bitstream. The driver is already in the kernel, but the node is missing. This patch adds the micfil node. Signed-off-by: Adam Ford Reviewed-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mm.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi index ee486597afc0..7a1b62f0ccc7 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi @@ -339,6 +339,25 @@ status = "disabled"; }; + micfil: audio-controller@30080000 { + compatible = "fsl,imx8mm-micfil"; + reg = <0x30080000 0x10000>; + interrupts = , + , + , + ; + clocks = <&clk IMX8MM_CLK_PDM_IPG>, + <&clk IMX8MM_CLK_PDM_ROOT>, + <&clk IMX8MM_AUDIO_PLL1_OUT>, + <&clk IMX8MM_AUDIO_PLL2_OUT>, + <&clk IMX8MM_CLK_EXT3>; + clock-names = "ipg_clk", "ipg_clk_app", + "pll8k", "pll11k", "clkext3"; + dmas = <&sdma2 24 25 0x80000000>; + dma-names = "rx"; + status = "disabled"; + }; + gpio1: gpio@30200000 { compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio"; reg = <0x30200000 0x10000>; From 57412197faf18683dff057f225c304b2d6dbe129 Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Mon, 19 Oct 2020 11:50:37 -0500 Subject: [PATCH 149/799] arm64: dts: imx8mm: Add node for SPDIF The i.MX8M Mini can support SPDIF which is compatible to the IP used on the i.MX35. Add the node. Signed-off-by: Adam Ford Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mm.dtsi | 24 +++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi index 7a1b62f0ccc7..033fee525982 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi @@ -358,6 +358,30 @@ status = "disabled"; }; + spdif1: spdif@30090000 { + compatible = "fsl,imx35-spdif"; + reg = <0x30090000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MM_CLK_AUDIO_AHB>, /* core */ + <&clk IMX8MM_CLK_24M>, /* rxtx0 */ + <&clk IMX8MM_CLK_SPDIF1>, /* rxtx1 */ + <&clk IMX8MM_CLK_DUMMY>, /* rxtx2 */ + <&clk IMX8MM_CLK_DUMMY>, /* rxtx3 */ + <&clk IMX8MM_CLK_DUMMY>, /* rxtx4 */ + <&clk IMX8MM_CLK_AUDIO_AHB>, /* rxtx5 */ + <&clk IMX8MM_CLK_DUMMY>, /* rxtx6 */ + <&clk IMX8MM_CLK_DUMMY>, /* rxtx7 */ + <&clk IMX8MM_CLK_DUMMY>; /* spba */ + clock-names = "core", "rxtx0", + "rxtx1", "rxtx2", + "rxtx3", "rxtx4", + "rxtx5", "rxtx6", + "rxtx7", "spba"; + dmas = <&sdma2 28 18 0>, <&sdma2 29 18 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + gpio1: gpio@30200000 { compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio"; reg = <0x30200000 0x10000>; From 5a76c474e8b940dc324eed4e10d486405c4110d7 Mon Sep 17 00:00:00 2001 From: Guillaume Tucker Date: Mon, 10 Aug 2020 13:22:08 +0100 Subject: [PATCH 150/799] ARM: exynos: clear prefetch bits in default l2c_aux_val Clear the L310_AUX_CTRL_DATA_PREFETCH and L310_AUX_CTRL_INSTR_PREFETCH bits in the l2c_aux_val defaults for Exynos since they can now be set using the standard l2c2x0 devicetree bindings. Signed-off-by: Guillaume Tucker Link: https://lore.kernel.org/r/e44b5226f3ad1551459830c678ed183762d8e458.1597061474.git.guillaume.tucker@collabora.com Signed-off-by: Krzysztof Kozlowski --- arch/arm/mach-exynos/exynos.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c index 700763e07083..a99d8eba4bb3 100644 --- a/arch/arm/mach-exynos/exynos.c +++ b/arch/arm/mach-exynos/exynos.c @@ -206,8 +206,8 @@ static void __init exynos_dt_fixup(void) } DT_MACHINE_START(EXYNOS_DT, "Samsung Exynos (Flattened Device Tree)") - .l2c_aux_val = 0x38400000, - .l2c_aux_mask = 0xc60fffff, + .l2c_aux_val = 0x08400000, + .l2c_aux_mask = 0xf60fffff, .smp = smp_ops(exynos_smp_ops), .map_io = exynos_init_io, .init_early = exynos_firmware_init, From f1748a1f3d49d85d57ba75065ad79ebecf728cbe Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Mon, 19 Oct 2020 12:45:25 -0500 Subject: [PATCH 151/799] arm64: defconfig: Enable ASRC and EASRC The i.MX8M Nano supports the EASRC driver, and it requires ASRC. Enable both of them as modules. Signed-off-by: Adam Ford Signed-off-by: Shawn Guo --- arch/arm64/configs/defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 844d8817e6f4..270d326d5f28 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -694,7 +694,9 @@ CONFIG_SND_HDA_CODEC_HDMI=m CONFIG_SND_SOC=y CONFIG_SND_BCM2835_SOC_I2S=m CONFIG_SND_SOC_FSL_SAI=m +CONFIG_SND_SOC_FSL_ASRC=m CONFIG_SND_SOC_FSL_MICFIL=m +CONFIG_SND_SOC_FSL_EASRC=m CONFIG_SND_IMX_SOC=m CONFIG_SND_SOC_IMX_SPDIF=m CONFIG_SND_SOC_IMX_AUDMIX=m From da2445049fafff0274d2a596a45e86021b01779b Mon Sep 17 00:00:00 2001 From: Serge Semin Date: Tue, 20 Oct 2020 14:59:57 +0300 Subject: [PATCH 152/799] arm64: dts: layerscape: Harmonize DWC USB3 DT nodes name In accordance with the DWC USB3 bindings the corresponding node name is suppose to comply with the Generic USB HCD DT schema, which requires the USB nodes to have the name acceptable by the regexp: "^usb(@.*)?" . Make sure the "snps,dwc3"-compatible nodes are correctly named. Signed-off-by: Serge Semin Acked-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi | 4 ++-- arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 6 +++--- arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 4 ++-- arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi | 4 ++-- 4 files changed, 9 insertions(+), 9 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi index 1393fc7e56bb..a168e06ac50a 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi @@ -454,7 +454,7 @@ <&clockgen 4 3>; }; - usb0: usb3@2f00000 { + usb0: usb@2f00000 { compatible = "snps,dwc3"; reg = <0x0 0x2f00000 0x0 0x10000>; interrupts = <0 60 0x4>; @@ -475,7 +475,7 @@ status = "disabled"; }; - usb1: usb2@8600000 { + usb1: usb@8600000 { compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr"; reg = <0x0 0x8600000 0x0 0x1000>; interrupts = <0 139 0x4>; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi index d550f00f1f6a..d5d219311161 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi @@ -750,7 +750,7 @@ <&clockgen 4 0>; }; - usb0: usb3@2f00000 { + usb0: usb@2f00000 { compatible = "snps,dwc3"; reg = <0x0 0x2f00000 0x0 0x10000>; interrupts = <0 60 0x4>; @@ -761,7 +761,7 @@ status = "disabled"; }; - usb1: usb3@3000000 { + usb1: usb@3000000 { compatible = "snps,dwc3"; reg = <0x0 0x3000000 0x0 0x10000>; interrupts = <0 61 0x4>; @@ -772,7 +772,7 @@ status = "disabled"; }; - usb2: usb3@3100000 { + usb2: usb@3100000 { compatible = "snps,dwc3"; reg = <0x0 0x3100000 0x0 0x10000>; interrupts = <0 63 0x4>; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi index ff5805206a28..b2c5189e59fa 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi @@ -420,7 +420,7 @@ status = "disabled"; }; - usb0: usb3@3100000 { + usb0: usb@3100000 { compatible = "snps,dwc3"; reg = <0x0 0x3100000 0x0 0x10000>; interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>; @@ -431,7 +431,7 @@ status = "disabled"; }; - usb1: usb3@3110000 { + usb1: usb@3110000 { compatible = "snps,dwc3"; reg = <0x0 0x3110000 0x0 0x10000>; interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi index bf72918fe545..4d3f72d126e7 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi @@ -860,7 +860,7 @@ dma-coherent; }; - usb0: usb3@3100000 { + usb0: usb@3100000 { status = "disabled"; compatible = "snps,dwc3"; reg = <0x0 0x3100000 0x0 0x10000>; @@ -871,7 +871,7 @@ snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; }; - usb1: usb3@3110000 { + usb1: usb@3110000 { status = "disabled"; compatible = "snps,dwc3"; reg = <0x0 0x3110000 0x0 0x10000>; From 7c685a0f809b0ccbc9201ff4395a716db4e43797 Mon Sep 17 00:00:00 2001 From: Oleksij Rempel Date: Thu, 22 Oct 2020 12:27:31 +0200 Subject: [PATCH 153/799] dt-bindings: vendor-prefixes: Add an entry for Van der Laan b.v. Add "vdl" entry for Van der Laan b.v.: https://www.teamvdl.nl/ Signed-off-by: Oleksij Rempel Acked-by: Rob Herring Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index 6f138271f003..31897f127b47 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -1148,6 +1148,8 @@ patternProperties: description: Vamrs Ltd. "^variscite,.*": description: Variscite Ltd. + "^vdl,.*": + description: Van der Laan b.v. "^via,.*": description: VIA Technologies, Inc. "^videostrong,.*": From 225c59b9235a421cdb219be5fbc13126a49714a6 Mon Sep 17 00:00:00 2001 From: Alexandru Stan Date: Wed, 21 Oct 2020 22:04:43 -0700 Subject: [PATCH 154/799] ARM: dts: rockchip: Remove 0 point from brightness-levels on rk3288-veyron The extra 0 only adds one point in the userspace visible range, so this change is almost a noop with the current driver behavior. We don't need the 0% point, userspace seems to handle this just fine because it uses the bl_power property to turn off the display. Furthermore after adding "backlight: pwm_bl: Fix interpolation" patch, the backlight interpolation will work a little differently. So we need to preemptively remove the 0-3 segment since otherwise we would have a 252 long interpolation that would slowly go between 0 and 3, looking really bad in userspace. So it's almost a noop/cleanup now, but it will be required in the future. Signed-off-by: Alexandru Stan Reviewed-by: Douglas Anderson Acked-by: Daniel Thompson Link: https://lore.kernel.org/r/20201021220404.v3.1.I96b8d872ec51171f19274e43e96cadc092881271@changeid Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3288-veyron-jaq.dts | 2 +- arch/arm/boot/dts/rk3288-veyron-minnie.dts | 2 +- arch/arm/boot/dts/rk3288-veyron-tiger.dts | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/rk3288-veyron-jaq.dts b/arch/arm/boot/dts/rk3288-veyron-jaq.dts index af77ab20586d..4a148cf1defc 100644 --- a/arch/arm/boot/dts/rk3288-veyron-jaq.dts +++ b/arch/arm/boot/dts/rk3288-veyron-jaq.dts @@ -20,7 +20,7 @@ &backlight { /* Jaq panel PWM must be >= 3%, so start non-zero brightness at 8 */ - brightness-levels = <0 8 255>; + brightness-levels = <8 255>; num-interpolated-steps = <247>; }; diff --git a/arch/arm/boot/dts/rk3288-veyron-minnie.dts b/arch/arm/boot/dts/rk3288-veyron-minnie.dts index f8b69e0a16a0..82fc6fba9999 100644 --- a/arch/arm/boot/dts/rk3288-veyron-minnie.dts +++ b/arch/arm/boot/dts/rk3288-veyron-minnie.dts @@ -39,7 +39,7 @@ &backlight { /* Minnie panel PWM must be >= 1%, so start non-zero brightness at 3 */ - brightness-levels = <0 3 255>; + brightness-levels = <3 255>; num-interpolated-steps = <252>; }; diff --git a/arch/arm/boot/dts/rk3288-veyron-tiger.dts b/arch/arm/boot/dts/rk3288-veyron-tiger.dts index 069f0c2c1fdf..52a84cbe7a90 100644 --- a/arch/arm/boot/dts/rk3288-veyron-tiger.dts +++ b/arch/arm/boot/dts/rk3288-veyron-tiger.dts @@ -23,7 +23,7 @@ &backlight { /* Tiger panel PWM must be >= 1%, so start non-zero brightness at 3 */ - brightness-levels = <0 3 255>; + brightness-levels = <3 255>; num-interpolated-steps = <252>; }; From 14f100c00f1e35e5890340d4c6a64bda5dff4320 Mon Sep 17 00:00:00 2001 From: Vijay Khemka Date: Thu, 13 Aug 2020 12:04:30 -0700 Subject: [PATCH 155/799] ARM: dts: aspeed: tiogapass: Remove vuart Removed vuart for facebook tiogapass platform as it uses uart2 and uart3 pin with aspeed uart routing feature. Signed-off-by: Vijay Khemka Reviewed-by: Joel Stanley Fixes: ffdbf494821d ("ARM: dts: aspeed: tiogapass: Enable VUART") Link: https://lore.kernel.org/r/20200813190431.3331026-1-vijaykhemka@fb.com Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts | 5 ----- 1 file changed, 5 deletions(-) diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts b/arch/arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts index 2d44d9ad4e40..e6ad821a8635 100644 --- a/arch/arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts +++ b/arch/arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts @@ -82,11 +82,6 @@ status = "okay"; }; -&vuart { - // VUART Host Console - status = "okay"; -}; - &uart1 { // Host Console status = "okay"; From 5649789d9706e864b9a2af2c057da5b1706ff3a0 Mon Sep 17 00:00:00 2001 From: Eugeniu Rosca Date: Fri, 30 Oct 2020 09:30:51 +0100 Subject: [PATCH 156/799] dt-bindings: arm: renesas: Add R-Car M3-W+ ULCB with Kingfisher Document the use of the Kingfisher expansion board with the R-Car Starter Kit Pro equipped with an R-Car M3-W+ (aka M3-ES3.0) SoC. Inspired from v5.5 commit 24169f0a453754 ("dt-bindings: arm: renesas: Add R-Car M3-N ULCB with Kingfisher"). Suggested-by: Geert Uytterhoeven Signed-off-by: Eugeniu Rosca Link: https://lore.kernel.org/r/20201030083051.18752-4-erosca@de.adit-jv.com Signed-off-by: Geert Uytterhoeven --- Documentation/devicetree/bindings/arm/renesas.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/renesas.yaml b/Documentation/devicetree/bindings/arm/renesas.yaml index 01a6d0c571ad..1dd165bece72 100644 --- a/Documentation/devicetree/bindings/arm/renesas.yaml +++ b/Documentation/devicetree/bindings/arm/renesas.yaml @@ -245,6 +245,7 @@ properties: - enum: - renesas,r8a7795 - renesas,r8a7796 + - renesas,r8a77961 - renesas,r8a77965 - description: R-Car M3-N (R8A77965) From ddc36a2da5c88579e58361a222064264efd64f02 Mon Sep 17 00:00:00 2001 From: Matteo Scordino Date: Fri, 30 Oct 2020 23:43:20 +0000 Subject: [PATCH 157/799] dt-bindings: vendors: add Elimo Engineering vendor prefix Add elimo as vendor prefix for dt bindings, since we are adding a dtsi for a SoM and a dts for an SBC Signed-off-by: Matteo Scordino Signed-off-by: Maxime Ripard Link: https://lore.kernel.org/r/20201030234325.5865-2-matteo.scordino@gmail.com --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index 2735be1a8470..b877a3516277 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -319,6 +319,8 @@ patternProperties: description: Elgin S/A. "^elida,.*": description: Shenzhen Elida Technology Co., Ltd. + "^elimo,.*": + description: Elimo Engineering Ltd. "^embest,.*": description: Shenzhen Embest Technology Co., Ltd. "^emlid,.*": From 85f296433e6c417b27c4077ed3f9479596d9c623 Mon Sep 17 00:00:00 2001 From: Matteo Scordino Date: Fri, 30 Oct 2020 23:43:21 +0000 Subject: [PATCH 158/799] ARM: dts: sun8i: V3/S3: Add UART1 pin definitions to the V3/S3 dtsi The Allwinner V3 and S3 can use PG6/7 as RX/TX for UART1. Since no other functions are assigned to those pins, they are a convenient choice for a debugging or application UART. This is specific to V3/S3 as the V3s's non-BGA package did not have those pins. Signed-off-by: Matteo Scordino Signed-off-by: Maxime Ripard Link: https://lore.kernel.org/r/20201030234325.5865-3-matteo.scordino@gmail.com --- arch/arm/boot/dts/sun8i-v3.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/boot/dts/sun8i-v3.dtsi b/arch/arm/boot/dts/sun8i-v3.dtsi index ca4672ed2e02..c279e13583ba 100644 --- a/arch/arm/boot/dts/sun8i-v3.dtsi +++ b/arch/arm/boot/dts/sun8i-v3.dtsi @@ -24,4 +24,9 @@ &pio { compatible = "allwinner,sun8i-v3-pinctrl"; + + uart1_pg_pins: uart1-pg-pins { + pins = "PG6", "PG7"; + function = "uart1"; + }; }; From 52a70e641a1fe6b0dc3ff46a8498d778ce6b99de Mon Sep 17 00:00:00 2001 From: Paul Kocialkowski Date: Sat, 31 Oct 2020 19:21:31 +0100 Subject: [PATCH 159/799] ARM: dts: sun8i-v3s: Add I2C1 PB pins description I2C1 can be exposed through PB pins in addition to PE pins on the V3s. Add the device-tree description for these pins. Signed-off-by: Paul Kocialkowski Signed-off-by: Maxime Ripard Link: https://lore.kernel.org/r/20201031182137.1879521-4-contact@paulk.fr --- arch/arm/boot/dts/sun8i-v3s.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/boot/dts/sun8i-v3s.dtsi b/arch/arm/boot/dts/sun8i-v3s.dtsi index 0c7341676921..7b2d684aeb97 100644 --- a/arch/arm/boot/dts/sun8i-v3s.dtsi +++ b/arch/arm/boot/dts/sun8i-v3s.dtsi @@ -347,6 +347,12 @@ function = "i2c0"; }; + /omit-if-no-ref/ + i2c1_pb_pins: i2c1-pb-pins { + pins = "PB8", "PB9"; + function = "i2c1"; + }; + /omit-if-no-ref/ i2c1_pe_pins: i2c1-pe-pins { pins = "PE21", "PE22"; From d7ffc7d48e437c016a65eff6d156b39884ab2594 Mon Sep 17 00:00:00 2001 From: Jernej Skrabec Date: Fri, 30 Oct 2020 18:25:30 +0100 Subject: [PATCH 160/799] arm64: dts: allwinner: h6: PineH64 model B: Add wifi PineH64 model B contains RTL8723CS wifi+bt combo module. Since bluetooth support is not yet squared away, only wifi is enabled for now. Signed-off-by: Jernej Skrabec Signed-off-by: Maxime Ripard Tested-by: Acked-by: Chen-Yu Tsai Link: https://lore.kernel.org/r/20201030172530.1096394-1-jernej.skrabec@siol.net --- .../dts/allwinner/sun50i-h6-pine-h64-model-b.dts | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64-model-b.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64-model-b.dts index f4c8966a6497..7fea1e4e2d49 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64-model-b.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64-model-b.dts @@ -10,6 +10,12 @@ compatible = "pine64,pine-h64-model-b", "allwinner,sun50i-h6"; /delete-node/ reg_gmac_3v3; + + wifi_pwrseq: wifi_pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&r_pio 1 3 GPIO_ACTIVE_LOW>; /* PM3 */ + post-power-on-delay-ms = <200>; + }; }; &hdmi_connector { @@ -19,3 +25,12 @@ &emac { phy-supply = <®_aldo2>; }; + +&mmc1 { + vmmc-supply = <®_cldo3>; + vqmmc-supply = <®_aldo1>; + mmc-pwrseq = <&wifi_pwrseq>; + bus-width = <4>; + non-removable; + status = "okay"; +}; From efc5dae95a8c272e7737a29fdaecc06d64320717 Mon Sep 17 00:00:00 2001 From: Konstantin Aladyshev Date: Tue, 27 Oct 2020 15:37:21 +0300 Subject: [PATCH 161/799] ARM: dts: aspeed: amd-ethanolx: Enable KCS channel 3 The KCS interface on the LPC channel 3 in the controller is used for the in-band BMC<->BIOS IPMI communication. 0xCA2 is a default host CPU LPC IO address for this interface. Signed-off-by: Konstantin Aladyshev Reviewed-by: Supreeth Venkatesh Reviewed-by: Joel Stanley Link: https://lore.kernel.org/r/20201027123722.2935-2-aladyshev22@gmail.com Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-bmc-amd-ethanolx.dts | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/boot/dts/aspeed-bmc-amd-ethanolx.dts b/arch/arm/boot/dts/aspeed-bmc-amd-ethanolx.dts index 89ddc3847222..2a86bda8afd8 100644 --- a/arch/arm/boot/dts/aspeed-bmc-amd-ethanolx.dts +++ b/arch/arm/boot/dts/aspeed-bmc-amd-ethanolx.dts @@ -147,6 +147,11 @@ aspeed,lpc-io-reg = <0x62>; }; +&kcs3 { + status = "okay"; + aspeed,lpc-io-reg = <0xCA2>; +}; + &kcs4 { status = "okay"; aspeed,lpc-io-reg = <0x97DE>; From f69456d3224aff06820dfc2460780046bb6544b0 Mon Sep 17 00:00:00 2001 From: Konstantin Aladyshev Date: Tue, 27 Oct 2020 15:37:22 +0300 Subject: [PATCH 162/799] ARM: dts: aspeed: amd-ethanolx: Enable devices for the iKVM functionality Enable the USB 2.0 Virtual Hub Controller and the Video Engine with it's reserved memory region for the implementation of the iKVM functionality in the BMC. Signed-off-by: Konstantin Aladyshev Reviewed-by: Supreeth Venkatesh Reviewed-by: Joel Stanley Link: https://lore.kernel.org/r/20201027123722.2935-3-aladyshev22@gmail.com Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-bmc-amd-ethanolx.dts | 22 +++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm/boot/dts/aspeed-bmc-amd-ethanolx.dts b/arch/arm/boot/dts/aspeed-bmc-amd-ethanolx.dts index 2a86bda8afd8..b93ed44eba0c 100644 --- a/arch/arm/boot/dts/aspeed-bmc-amd-ethanolx.dts +++ b/arch/arm/boot/dts/aspeed-bmc-amd-ethanolx.dts @@ -13,6 +13,21 @@ memory@80000000 { reg = <0x80000000 0x20000000>; }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + video_engine_memory: jpegbuffer { + size = <0x02000000>; /* 32M */ + alignment = <0x01000000>; + compatible = "shared-dma-pool"; + reusable; + }; + }; + + aliases { serial0 = &uart1; serial4 = &uart5; @@ -220,5 +235,12 @@ }; }; +&video { + status = "okay"; + memory-region = <&video_engine_memory>; +}; +&vhub { + status = "okay"; +}; From b306d9cec8de054c7ace45dd0e4c9cac4991d65f Mon Sep 17 00:00:00 2001 From: Jernej Skrabec Date: Fri, 30 Oct 2020 15:46:44 +0100 Subject: [PATCH 163/799] arm64: dts: allwinner: h6: Add I2S1 node MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add Allwinner H6 I2S1 node connected to HDMI interface. Signed-off-by: Jernej Skrabec Signed-off-by: Marcus Cooper Signed-off-by: Clément Péron Signed-off-by: Maxime Ripard Acked-by: Chen-Yu Tsai Link: https://lore.kernel.org/r/20201030144648.397824-12-peron.clem@gmail.com --- arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi index 28c4a79b8a45..8a62a9fbe347 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi @@ -609,6 +609,19 @@ }; }; + i2s1: i2s@5091000 { + #sound-dai-cells = <0>; + compatible = "allwinner,sun50i-h6-i2s"; + reg = <0x05091000 0x1000>; + interrupts = ; + clocks = <&ccu CLK_BUS_I2S1>, <&ccu CLK_I2S1>; + clock-names = "apb", "mod"; + dmas = <&dma 4>, <&dma 4>; + resets = <&ccu RST_BUS_I2S1>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + spdif: spdif@5093000 { #sound-dai-cells = <0>; compatible = "allwinner,sun50i-h6-spdif"; From 796c994e0b63400f6450a10e0a75c45e59191304 Mon Sep 17 00:00:00 2001 From: Marcus Cooper Date: Fri, 30 Oct 2020 15:46:45 +0100 Subject: [PATCH 164/799] arm64: dts: allwinner: a64: Add I2S2 node MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add the I2S2 node connected to the HDMI interface. Signed-off-by: Jernej Skrabec Signed-off-by: Marcus Cooper Signed-off-by: Clément Péron Signed-off-by: Maxime Ripard Acked-by: Chen-Yu Tsai Link: https://lore.kernel.org/r/20201030144648.397824-13-peron.clem@gmail.com --- arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi index dc238814013c..51cc30e84e26 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi @@ -846,6 +846,20 @@ status = "disabled"; }; + i2s2: i2s@1c22800 { + #sound-dai-cells = <0>; + compatible = "allwinner,sun50i-a64-i2s", + "allwinner,sun8i-h3-i2s"; + reg = <0x01c22800 0x400>; + interrupts = ; + clocks = <&ccu CLK_BUS_I2S2>, <&ccu CLK_I2S2>; + clock-names = "apb", "mod"; + resets = <&ccu RST_BUS_I2S2>; + dma-names = "rx", "tx"; + dmas = <&dma 27>, <&dma 27>; + status = "disabled"; + }; + dai: dai@1c22c00 { #sound-dai-cells = <0>; compatible = "allwinner,sun50i-a64-codec-i2s"; From cd7c897821a0dd41b10b756601d5707f0096652b Mon Sep 17 00:00:00 2001 From: Marcus Cooper Date: Fri, 30 Oct 2020 15:46:48 +0100 Subject: [PATCH 165/799] arm: dts: sunxi: h3/h5: Add I2S2 node MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add H3/H5 I2S2 node connected to the HDMI interface. Signed-off-by: Jernej Skrabec Signed-off-by: Marcus Cooper Signed-off-by: Clément Péron Signed-off-by: Maxime Ripard Acked-by: Chen-Yu Tsai Link: https://lore.kernel.org/r/20201030144648.397824-16-peron.clem@gmail.com --- arch/arm/boot/dts/sunxi-h3-h5.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/sunxi-h3-h5.dtsi index 22d533d18992..9be13378d4df 100644 --- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi +++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi @@ -662,6 +662,19 @@ status = "disabled"; }; + i2s2: i2s@1c22800 { + #sound-dai-cells = <0>; + compatible = "allwinner,sun8i-h3-i2s"; + reg = <0x01c22800 0x400>; + interrupts = ; + clocks = <&ccu CLK_BUS_I2S2>, <&ccu CLK_I2S2>; + clock-names = "apb", "mod"; + dmas = <&dma 27>; + resets = <&ccu RST_BUS_I2S2>; + dma-names = "tx"; + status = "disabled"; + }; + codec: codec@1c22c00 { #sound-dai-cells = <0>; compatible = "allwinner,sun8i-h3-codec"; From 0536f70989601c64c162107354a03112ab1bb9e6 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Cl=C3=A9ment=20P=C3=A9ron?= Date: Fri, 30 Oct 2020 15:46:46 +0100 Subject: [PATCH 166/799] arm64: defconfig: Enable Allwinner i2s driver MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Enable Allwinner I2S driver for arm64 defconfig. Signed-off-by: Clément Péron Signed-off-by: Maxime Ripard Acked-by: Chen-Yu Tsai Link: https://lore.kernel.org/r/20201030144648.397824-14-peron.clem@gmail.com --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 17a2df6a263e..3f89f427a355 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -706,6 +706,7 @@ CONFIG_SND_SOC_ROCKCHIP_RT5645=m CONFIG_SND_SOC_RK3399_GRU_SOUND=m CONFIG_SND_SOC_SAMSUNG=y CONFIG_SND_SOC_RCAR=m +CONFIG_SND_SUN4I_I2S=m CONFIG_SND_SUN4I_SPDIF=m CONFIG_SND_SOC_TEGRA=m CONFIG_SND_SOC_TEGRA210_AHUB=m From fa67f2817ff2c9bb07472d30e58d904922f1a538 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Wed, 14 Oct 2020 22:00:29 +0200 Subject: [PATCH 167/799] dt-bindings: vendor-prefixes: Add kobol prefix MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The prefix is already used in arm/armada-388-helios4.dts. Signed-off-by: Uwe Kleine-König Acked-by: Rob Herring Link: https://lore.kernel.org/r/20201014200030.845759-2-uwe@kleine-koenig.org Signed-off-by: Heiko Stuebner --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index 2735be1a8470..259faf1b382c 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -553,6 +553,8 @@ patternProperties: description: Kionix, Inc. "^kobo,.*": description: Rakuten Kobo Inc. + "^kobol,.*": + description: Kobol Innovations Pte. Ltd. "^koe,.*": description: Kaohsiung Opto-Electronics Inc. "^kontron,.*": From 09e006cfb43e8ec38afe28278b210dab72e6cac8 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Wed, 14 Oct 2020 22:00:30 +0200 Subject: [PATCH 168/799] arm64: dts: rockchip: Add basic support for Kobol's Helios64 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The hardware is described in detail on Kobol's wiki at https://wiki.kobol.io/helios64/intro/. Up to now the following peripherals are working: - UART - Micro-SD card - eMMC - ethernet port 1 - status LED - temperature sensor on i2c bus 2 Signed-off-by: Uwe Kleine-König Link: https://lore.kernel.org/r/20201014200030.845759-3-uwe@kleine-koenig.org Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/Makefile | 1 + .../dts/rockchip/rk3399-kobol-helios64.dts | 372 ++++++++++++++++++ 2 files changed, 373 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile index 26661c7b736b..28b26a874313 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -26,6 +26,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-hugsun-x99.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-khadas-edge.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-khadas-edge-captain.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-khadas-edge-v.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-kobol-helios64.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-leez-p710.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-nanopc-t4.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-nanopi-m4.dtb diff --git a/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts b/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts new file mode 100644 index 000000000000..2a561be724b2 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts @@ -0,0 +1,372 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Aditya Prayoga + */ + +/* + * The Kobol Helios64 is a board designed to operate as a NAS and optionally + * ships with an enclosing that can host five 2.5" hard disks. + * + * See https://wiki.kobol.io/helios64/intro/ for further details. + */ + +/dts-v1/; +#include "rk3399.dtsi" +#include "rk3399-opp.dtsi" + +/ { + model = "Kobol Helios64"; + compatible = "kobol,helios64", "rockchip,rk3399"; + + avdd_1v8_s0: avdd-1v8-s0 { + compatible = "regulator-fixed"; + regulator-name = "avdd_1v8_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc3v3_sys_s3>; + }; + + clkin_gmac: external-gmac-clock { + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "clkin_gmac"; + #clock-cells = <0>; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&sys_grn_led_on &sys_red_led_on>; + + led-0 { + label = "helios64:green:status"; + gpios = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + + led-1 { + label = "helios64:red:fault"; + gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>; + default-state = "keep"; + }; + }; + + vcc1v8_sys_s0: vcc1v8-sys-s0 { + compatible = "regulator-fixed"; + regulator-name = "vcc1v8_sys_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc1v8_sys_s3>; + }; + + vcc3v0_sd: vcc3v0-sd { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PA1 GPIO_ACTIVE_HIGH>; + regulator-name = "vcc3v0_sd"; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_pwr_h>; + vin-supply = <&vcc3v3_sys_s3>; + }; + + vcc3v3_sys_s3: vcc_lan: vcc3v3-sys-s3 { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc5v0_sys: vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin_bkup>; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc12v_dcin: vcc12v-dcin { + compatible = "regulator-fixed"; + regulator-name = "vcc12v_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + vcc12v_dcin_bkup: vcc12v-dcin-bkup { + compatible = "regulator-fixed"; + regulator-name = "vcc12v_dcin_bkup"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + vin-supply = <&vcc12v_dcin>; + }; +}; + +/* + * The system doesn't run stable with cpu freq enabled, so disallow the lower + * frequencies until this problem is properly understood and resolved. + */ +&cluster0_opp { + /delete-node/ opp00; + /delete-node/ opp01; + /delete-node/ opp02; + /delete-node/ opp03; + /delete-node/ opp04; +}; + +&cluster1_opp { + /delete-node/ opp00; + /delete-node/ opp01; + /delete-node/ opp02; + /delete-node/ opp03; + /delete-node/ opp04; + /delete-node/ opp05; + /delete-node/ opp06; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_b>; +}; + +&cpu_b1 { + cpu-supply = <&vdd_cpu_b>; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l1 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l2 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l3 { + cpu-supply = <&vdd_cpu_l>; +}; + +&emmc_phy { + status = "okay"; +}; + +&gmac { + assigned-clock-parents = <&clkin_gmac>; + assigned-clocks = <&cru SCLK_RMII_SRC>; + clock_in_out = "input"; + phy-mode = "rgmii"; + phy-supply = <&vcc_lan>; + pinctrl-names = "default"; + pinctrl-0 = <&rgmii_pins &gphy_reset>; + rx_delay = <0x20>; + tx_delay = <0x28>; + snps,reset-active-low; + snps,reset-delays-us = <0 10000 50000>; + snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&i2c0 { + clock-frequency = <400000>; + i2c-scl-rising-time-ns = <168>; + i2c-scl-falling-time-ns = <4>; + status = "okay"; + + rk808: pmic@1b { + compatible = "rockchip,rk808"; + reg = <0x1b>; + interrupt-parent = <&gpio0>; + interrupts = <10 IRQ_TYPE_LEVEL_LOW>; + clock-output-names = "xin32k", "rk808-clkout2"; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int_l>; + vcc1-supply = <&vcc5v0_sys>; + vcc2-supply = <&vcc5v0_sys>; + vcc3-supply = <&vcc5v0_sys>; + vcc4-supply = <&vcc5v0_sys>; + vcc6-supply = <&vcc5v0_sys>; + vcc7-supply = <&vcc5v0_sys>; + vcc8-supply = <&vcc3v3_sys_s3>; + vcc9-supply = <&vcc5v0_sys>; + vcc10-supply = <&vcc5v0_sys>; + vcc11-supply = <&vcc5v0_sys>; + vcc12-supply = <&vcc3v3_sys_s3>; + vddio-supply = <&vcc3v0_s3>; + wakeup-source; + #clock-cells = <1>; + + regulators { + vdd_cpu_l: DCDC_REG2 { + regulator-name = "vdd_cpu_l"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc1v8_sys_s3: DCDC_REG4 { + regulator-name = "vcc1v8_sys_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc_sdio_s0: LDO_REG4 { + regulator-name = "vcc_sdio_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3000000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + + vcc3v0_s3: LDO_REG8 { + regulator-name = "vcc3v0_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + }; + }; + + vdd_cpu_b: regulator@40 { + compatible = "silergy,syr827"; + reg = <0x40>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu_b"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1500000>; + regulator-ramp-delay = <1000>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c2 { + clock-frequency = <400000>; + i2c-scl-rising-time-ns = <160>; + i2c-scl-falling-time-ns = <30>; + status = "okay"; + + temp@4c { + compatible = "national,lm75"; + reg = <0x4c>; + }; +}; + +&io_domains { + audio-supply = <&vcc1v8_sys_s0>; + bt656-supply = <&vcc1v8_sys_s0>; + gpio1830-supply = <&vcc3v0_s3>; + sdmmc-supply = <&vcc_sdio_s0>; + status = "okay"; +}; + +&pinctrl { + gmac { + gphy_reset: gphy-reset { + rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_output_low>; + }; + }; + + leds { + sys_grn_led_on: sys-grn-led-on { + rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + sys_red_led_on: sys-red-led-on { + rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + pmic { + pmic_int_l: pmic-int-l { + rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + vcc3v0-sd { + sdmmc0_pwr_h: sdmmc0-pwr-h { + rockchip,pins = <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&pmu_io_domains { + pmu1830-supply = <&vcc3v0_s3>; + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + mmc-hs200-1_8v; + non-removable; + vqmmc-supply = <&vcc1v8_sys_s0>; + status = "okay"; +}; + +&sdmmc { + bus-width = <4>; + cap-sd-highspeed; + cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>; + disable-wp; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>; + vmmc-supply = <&vcc3v0_sd>; + vqmmc-supply = <&vcc_sdio_s0>; + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; From 437145dbcdee5b62f94b6fd846a22a8671c28843 Mon Sep 17 00:00:00 2001 From: Evan Green Date: Wed, 28 Oct 2020 17:28:25 -0700 Subject: [PATCH 169/799] arm64: dts: qcom: sc7180: Add soc-specific qfprom compat string Add the soc-specific compatible string so that it can be matched more specifically now that the driver cares which SoC it's on. Signed-off-by: Evan Green Reviewed-by: Douglas Anderson Link: https://lore.kernel.org/r/20201028172737.v3.2.Ia3b68ac843df93c692627a3a92b947b3a5785863@changeid Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc7180.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index 6fcffd588a7d..f5ef2cb6e68c 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -660,7 +660,7 @@ }; qfprom: efuse@784000 { - compatible = "qcom,qfprom"; + compatible = "qcom,sc7180-qfprom", "qcom,qfprom"; reg = <0 0x00784000 0 0x8ff>, <0 0x00780000 0 0x7a0>, <0 0x00782000 0 0x100>, From fa43c3de5c37f315271662bbc8cd6e110280abee Mon Sep 17 00:00:00 2001 From: Meenakshi Aggarwal Date: Mon, 2 Nov 2020 11:29:40 +0530 Subject: [PATCH 170/799] dt-bindings: fsl: add compatible for LX2162A QDS Board Add support for LX2162A, LX2162A is LX2160A based SoC. Signed-off-by: Meenakshi Aggarwal Acked-by: Rob Herring Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/arm/fsl.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index 417b5634d3f1..85fb24da4a02 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -892,6 +892,7 @@ properties: - enum: - fsl,lx2160a-qds - fsl,lx2160a-rdb + - fsl,lx2162a-qds - const: fsl,lx2160a - description: S32V234 based Boards From 0dbcd49917191c599e33725268892f9a4f006154 Mon Sep 17 00:00:00 2001 From: Ioana Ciornei Date: Fri, 30 Oct 2020 13:35:45 +0200 Subject: [PATCH 171/799] dt-bindings: net: add the DPAA2 MAC DTS definition Add a documentation entry for the DTS bindings needed and supported by the dpaa2-mac driver. Signed-off-by: Ioana Ciornei Reviewed-by: Rob Herring Signed-off-by: Shawn Guo --- .../bindings/net/fsl,qoriq-mc-dpmac.yaml | 60 +++++++++++++++++++ 1 file changed, 60 insertions(+) create mode 100644 Documentation/devicetree/bindings/net/fsl,qoriq-mc-dpmac.yaml diff --git a/Documentation/devicetree/bindings/net/fsl,qoriq-mc-dpmac.yaml b/Documentation/devicetree/bindings/net/fsl,qoriq-mc-dpmac.yaml new file mode 100644 index 000000000000..2159b7d1f537 --- /dev/null +++ b/Documentation/devicetree/bindings/net/fsl,qoriq-mc-dpmac.yaml @@ -0,0 +1,60 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/fsl,qoriq-mc-dpmac.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: DPAA2 MAC bindings + +maintainers: + - Ioana Ciornei + +description: + This binding represents the DPAA2 MAC objects found on the fsl-mc bus and + located under the 'dpmacs' node for the fsl-mc bus DTS node. + +allOf: + - $ref: "ethernet-controller.yaml#" + +properties: + compatible: + const: fsl,qoriq-mc-dpmac + + reg: + maxItems: 1 + description: The DPMAC number + + phy-handle: true + + phy-connection-type: true + + phy-mode: true + + pcs-handle: + $ref: /schemas/types.yaml#definitions/phandle + description: + A reference to a node representing a PCS PHY device found on + the internal MDIO bus. + + managed: true + +required: + - reg + +additionalProperties: false + +examples: + - | + dpmacs { + #address-cells = <1>; + #size-cells = <0>; + + ethernet@4 { + compatible = "fsl,qoriq-mc-dpmac"; + reg = <0x4>; + phy-handle = <&mdio1_phy6>; + phy-connection-type = "qsgmii"; + managed = "in-band-status"; + pcs-handle = <&pcs3_1>; + }; + }; From 39d3f3ffe79eb2ee2a93353113923eb837d92458 Mon Sep 17 00:00:00 2001 From: Ioana Ciornei Date: Fri, 30 Oct 2020 13:35:46 +0200 Subject: [PATCH 172/799] dt-bindings: net: add the 10gbase-r connection type Add 10gbase-r to the list of accepted PHY connection types between an Ethernet device and a physical PHY. This is available as a valid connection type since commit c114574ebfdf ("net: phy: add PHY_INTERFACE_MODE_10GBASER") Signed-off-by: Ioana Ciornei Acked-by: Rob Herring Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/net/ethernet-controller.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/net/ethernet-controller.yaml b/Documentation/devicetree/bindings/net/ethernet-controller.yaml index fdf709817218..cc93063a8f39 100644 --- a/Documentation/devicetree/bindings/net/ethernet-controller.yaml +++ b/Documentation/devicetree/bindings/net/ethernet-controller.yaml @@ -95,6 +95,7 @@ properties: # 10GBASE-KR, XFI, SFI - 10gbase-kr - usxgmii + - 10gbase-r phy-mode: $ref: "#/properties/phy-connection-type" From 5c8b3b8a182cbc1ccdfcdeea9b25dd2c12a8148f Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Sun, 1 Nov 2020 19:29:53 +0800 Subject: [PATCH 173/799] ARM: dts: imx: add usb alias Add usb alias for bootloader searching the controller in correct order. Signed-off-by: Peng Fan Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl.dtsi | 4 ++++ arch/arm/boot/dts/imx6sl.dtsi | 3 +++ arch/arm/boot/dts/imx6sll.dtsi | 2 ++ arch/arm/boot/dts/imx6sx.dtsi | 3 +++ arch/arm/boot/dts/imx6ul.dtsi | 2 ++ arch/arm/boot/dts/imx7d.dtsi | 6 ++++++ arch/arm/boot/dts/imx7s.dtsi | 2 ++ 7 files changed, 22 insertions(+) diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi index bc98b63922b0..cb2a8ef9070c 100644 --- a/arch/arm/boot/dts/imx6qdl.dtsi +++ b/arch/arm/boot/dts/imx6qdl.dtsi @@ -45,6 +45,10 @@ spi1 = &ecspi2; spi2 = &ecspi3; spi3 = &ecspi4; + usb0 = &usbotg; + usb1 = &usbh1; + usb2 = &usbh2; + usb3 = &usbh3; usbphy0 = &usbphy1; usbphy1 = &usbphy2; }; diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi index 91a8c54d5e11..997b96c1c47b 100644 --- a/arch/arm/boot/dts/imx6sl.dtsi +++ b/arch/arm/boot/dts/imx6sl.dtsi @@ -39,6 +39,9 @@ spi1 = &ecspi2; spi2 = &ecspi3; spi3 = &ecspi4; + usb0 = &usbotg1; + usb1 = &usbotg2; + usb2 = &usbh; usbphy0 = &usbphy1; usbphy1 = &usbphy2; }; diff --git a/arch/arm/boot/dts/imx6sll.dtsi b/arch/arm/boot/dts/imx6sll.dtsi index 0b622201a1f3..04f8d637a501 100644 --- a/arch/arm/boot/dts/imx6sll.dtsi +++ b/arch/arm/boot/dts/imx6sll.dtsi @@ -36,6 +36,8 @@ spi1 = &ecspi2; spi3 = &ecspi3; spi4 = &ecspi4; + usb0 = &usbotg1; + usb1 = &usbotg2; usbphy0 = &usbphy1; usbphy1 = &usbphy2; }; diff --git a/arch/arm/boot/dts/imx6sx.dtsi b/arch/arm/boot/dts/imx6sx.dtsi index 6c604c38c790..8516730778df 100644 --- a/arch/arm/boot/dts/imx6sx.dtsi +++ b/arch/arm/boot/dts/imx6sx.dtsi @@ -49,6 +49,9 @@ spi2 = &ecspi3; spi3 = &ecspi4; spi4 = &ecspi5; + usb0 = &usbotg1; + usb1 = &usbotg2; + usb2 = &usbh; usbphy0 = &usbphy1; usbphy1 = &usbphy2; }; diff --git a/arch/arm/boot/dts/imx6ul.dtsi b/arch/arm/boot/dts/imx6ul.dtsi index 713a4bb341db..ccbcbac80663 100644 --- a/arch/arm/boot/dts/imx6ul.dtsi +++ b/arch/arm/boot/dts/imx6ul.dtsi @@ -47,6 +47,8 @@ spi1 = &ecspi2; spi2 = &ecspi3; spi3 = &ecspi4; + usb0 = &usbotg1; + usb1 = &usbotg2; usbphy0 = &usbphy1; usbphy1 = &usbphy2; }; diff --git a/arch/arm/boot/dts/imx7d.dtsi b/arch/arm/boot/dts/imx7d.dtsi index cff875b80b60..b0bcfa9094a3 100644 --- a/arch/arm/boot/dts/imx7d.dtsi +++ b/arch/arm/boot/dts/imx7d.dtsi @@ -7,6 +7,12 @@ #include / { + aliases { + usb0 = &usbotg1; + usb1 = &usbotg2; + usb2 = &usbh; + }; + cpus { cpu0: cpu@0 { clock-frequency = <996000000>; diff --git a/arch/arm/boot/dts/imx7s.dtsi b/arch/arm/boot/dts/imx7s.dtsi index b58262acba11..251007a7b836 100644 --- a/arch/arm/boot/dts/imx7s.dtsi +++ b/arch/arm/boot/dts/imx7s.dtsi @@ -47,6 +47,8 @@ spi1 = &ecspi2; spi2 = &ecspi3; spi3 = &ecspi4; + usb0 = &usbotg1; + usb1 = &usbh; }; cpus { From 907286d1420d28bead47da37b9a081377c070322 Mon Sep 17 00:00:00 2001 From: Jiri Kosina Date: Tue, 3 Nov 2020 11:30:49 +0100 Subject: [PATCH 174/799] HID: SFH: Add documentation Add Documentation/hid/amd-sfh-hid.rst file which was by mistake dropped by me when applying the series. Fixes: 302f0dad8c97a11ab ("SFH: Add maintainers and documentation for AMD SFH based on HID framework") Reported-by: Lukas Bulwahn Originally-by: Sandeep Singh Signed-off-by: Jiri Kosina --- Documentation/hid/amd-sfh-hid.rst | 145 ++++++++++++++++++++++++++++++ 1 file changed, 145 insertions(+) create mode 100644 Documentation/hid/amd-sfh-hid.rst diff --git a/Documentation/hid/amd-sfh-hid.rst b/Documentation/hid/amd-sfh-hid.rst new file mode 100644 index 000000000000..1f2fe29ccd4f --- /dev/null +++ b/Documentation/hid/amd-sfh-hid.rst @@ -0,0 +1,145 @@ +.. SPDX-License-Identifier: GPL-2.0 + + +AMD Sensor Fusion Hub +===================== +AMD Sensor Fusion Hub (SFH) is part of an SOC starting from Ryzen based platforms. +The solution is working well on several OEM products. AMD SFH uses HID over PCIe bus. +In terms of architecture it resembles ISH, however the major difference is all +the HID reports are generated as part of the kernel driver. + +1. Block Diagram +================ + +:: + + --------------------------------- + | HID User Space Applications | + - ------------------------------- + + --------------------------------------------- + --------------------------------- + | HID Core | + --------------------------------- + + --------------------------------- + | AMD HID Transport | + --------------------------------- + + -------------------------------- + | AMD HID Client | + | with HID Report Generator| + -------------------------------- + + -------------------------------- + | AMD MP2 PCIe Driver | + -------------------------------- + OS + --------------------------------------------- + Hardware + Firmware + -------------------------------- + | SFH MP2 Processor | + -------------------------------- + + +AMD HID Transport Layer +----------------------- +AMD SFH transport is also implemented as a bus. Each client application executing in the AMD MP2 is +registered as a device on this bus. Here: MP2 which is an ARM core connected to x86 for processing +sensor data. The layer, which binds each device (AMD SFH HID driver) identifies the device type and +registers with the hid core. Transport layer attach a constant "struct hid_ll_driver" object with +each device. Once a device is registered with HID core, the callbacks provided via this struct are +used by HID core to communicate with the device. AMD HID Transport layer implements the synchronous calls. + +AMD HID Client Layer +-------------------- +This layer is responsible to implement HID request and descriptors. As firmware is OS agnostic, HID +client layer fills the HID request structure and descriptors. HID client layer is complex as it is +interface between MP2 PCIe layer and HID. HID client layer initialized the MP2 PCIe layer and holds +the instance of MP2 layer. It identifies the number of sensors connected using MP2-PCIe layer. Base +on that allocates the DRAM address for each and every sensor and pass it to MP2-PCIe driver.On +enumeration of each the sensor, client layer fills the HID Descriptor structure and HID input repor +structure. HID Feature report structure is optional. The report descriptor structure varies from +sensor to sensor. + +AMD MP2 PCIe layer +------------------ +MP2 PCIe Layer is responsible for making all transactions with the firmware over PCIe. +The connection establishment between firmware and PCIe happens here. + +The communication between X86 and MP2 is split into three parts. +1. Command transfer via the C2P mailbox registers. +2. Data transfer via DRAM. +3. Supported sensor info via P2C registers. + +Commands are sent to MP2 using C2P Mailbox registers. Writing into C2P Message registers generate +interrupt to MP2. The client layer allocates the physical memory and the same is sent to MP2 via +the PCI layer. MP2 firmware writes the command output to the access DRAM memory which the client +layer has allocated. Firmware always writes minimum of 32 bytes into DRAM. So as a protocol driver +shall allocate minimum of 32 bytes DRAM space. + +Enumeration and Probing flow +---------------------------- +:: + + HID AMD AMD AMD -PCIe MP2 + Core Transport Client layer layer FW + | | | | | + | | | on Boot Driver Loaded | + | | | | | + | | | MP2-PCIe Int | + | | | | | + | | |---Get Number of sensors-> | | + | | | Read P2C | + | | | Register | + | | | | | + | | | Loop(for No of Sensors) | | + | | |----------------------| | | + | | | Create HID Descriptor| | | + | | | Create Input report | | | + | | | Descriptor Map | | | + | | | the MP2 FW Index to | | | + | | | HID Index | | | + | | | Allocate the DRAM | Enable | + | | | address | Sensors | + | | |----------------------| | | + | | HID transport| | Enable | + | |<--Probe------| |---Sensor CMD--> | + | | Create the | | | + | | HID device | | | + | | (MFD) | | | + | | by Populating| | | + | | the HID | | | + | | ll_driver | | | + | HID | | | | + | add | | | | + |Device | | | | + |<------------- | | | | + + +Data Flow from Application to the AMD SFH Driver +------------------------------------------------ + +:: + + | | | | | + | | | | | + | | | | | + | | | | | + | | | | | + |HID_req | | | | + |get_report | | | | + |------------->| | | | + | | HID_get_input| | | + | | report | | | + | |------------->|------------------------| | | + | | | Read the DRAM data for| | | + | | | requested sensor and | | | + | | | create the HID input | | | + | | | report | | | + | | |------------------------| | | + | |Data received | | | + | | in HID report| | | + To |<-------------|<-------------| | | + Applications| | | | | + <-------| | | | | From 895387231e54e83bd0779afdea125df4d79c91a4 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jonathan=20Neusch=C3=A4fer?= Date: Sat, 31 Oct 2020 22:07:29 +0100 Subject: [PATCH 175/799] ARM: dts: imx50-kobo-aura: Add 'grp' suffix to pinctrl node names MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit i.MX pinctrl group nodes should have names that ends with 'grp'. Reported-by: Krzysztof Kozlowski Signed-off-by: Jonathan Neuschäfer Reviewed-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx50-kobo-aura.dts | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/arch/arm/boot/dts/imx50-kobo-aura.dts b/arch/arm/boot/dts/imx50-kobo-aura.dts index a0eaf869b913..53b3995d37e7 100644 --- a/arch/arm/boot/dts/imx50-kobo-aura.dts +++ b/arch/arm/boot/dts/imx50-kobo-aura.dts @@ -139,7 +139,7 @@ }; &iomuxc { - pinctrl_gpiokeys: gpiokeys { + pinctrl_gpiokeys: gpiokeysgrp { fsl,pins = < MX50_PAD_CSPI_MISO__GPIO4_10 0x0 MX50_PAD_SD2_D7__GPIO5_15 0x0 @@ -147,34 +147,34 @@ >; }; - pinctrl_i2c1: i2c1 { + pinctrl_i2c1: i2c1grp { fsl,pins = < MX50_PAD_I2C1_SCL__I2C1_SCL 0x400001fd MX50_PAD_I2C1_SDA__I2C1_SDA 0x400001fd >; }; - pinctrl_i2c2: i2c2 { + pinctrl_i2c2: i2c2grp { fsl,pins = < MX50_PAD_I2C2_SCL__I2C2_SCL 0x400001fd MX50_PAD_I2C2_SDA__I2C2_SDA 0x400001fd >; }; - pinctrl_i2c3: i2c3 { + pinctrl_i2c3: i2c3grp { fsl,pins = < MX50_PAD_I2C3_SCL__I2C3_SCL 0x400001fd MX50_PAD_I2C3_SDA__I2C3_SDA 0x400001fd >; }; - pinctrl_leds: leds { + pinctrl_leds: ledsgrp { fsl,pins = < MX50_PAD_PWM1__GPIO6_24 0x0 >; }; - pinctrl_sd1: sd1 { + pinctrl_sd1: sd1grp { fsl,pins = < MX50_PAD_SD1_CMD__ESDHC1_CMD 0x1e4 MX50_PAD_SD1_CLK__ESDHC1_CLK 0xd4 @@ -187,7 +187,7 @@ >; }; - pinctrl_sd2: sd2 { + pinctrl_sd2: sd2grp { fsl,pins = < MX50_PAD_SD2_CMD__ESDHC2_CMD 0x1e4 MX50_PAD_SD2_CLK__ESDHC2_CLK 0xd4 @@ -198,19 +198,19 @@ >; }; - pinctrl_sd2_reset: sd2-reset { + pinctrl_sd2_reset: sd2-resetgrp { fsl,pins = < MX50_PAD_ECSPI2_MOSI__GPIO4_17 0x0 >; }; - pinctrl_sd2_vmmc: sd2-vmmc { + pinctrl_sd2_vmmc: sd2-vmmcgrp { fsl,pins = < MX50_PAD_ECSPI1_SCLK__GPIO4_12 0x0 >; }; - pinctrl_sd3: sd3 { + pinctrl_sd3: sd3grp { fsl,pins = < MX50_PAD_SD3_CMD__ESDHC3_CMD 0x1e4 MX50_PAD_SD3_CLK__ESDHC3_CLK 0xd4 @@ -225,14 +225,14 @@ >; }; - pinctrl_uart2: uart2 { + pinctrl_uart2: uart2grp { fsl,pins = < MX50_PAD_UART2_TXD__UART2_TXD_MUX 0x1e4 MX50_PAD_UART2_RXD__UART2_RXD_MUX 0x1e4 >; }; - pinctrl_usbphy: usbphy { + pinctrl_usbphy: usbphygrp { fsl,pins = < MX50_PAD_ECSPI2_SS0__GPIO4_19 0x0 >; From a60406787e0b757becbf36014fb1b55aadffa76f Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Mon, 2 Nov 2020 17:08:50 -0800 Subject: [PATCH 176/799] arm64: defconfig: Enable Qualcomm Command DB driver The Qualcomm Command DB driver seems to have been indirectly enabled by the Qualcomm DRM driver and up until the introduction of '778279f4f5e4 ("soc: qcom: cmd-db: allow loading as a module")' this resulted in the driver "always" being builtin on arm64. But with the introduction of said change it, and all other RPMH related drivers, becomes =m. The immediate result is that the uart driver fails to probe, which depending on userspace's dependency on the presence of /dev/console might be fatal. For systems getting past this the default timeout of 0 seconds for probe deferral of many subsystems causes the system to be completely useless. So, make Command DB builtin. Reviewed-by: Vinod Koul Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20201103010850.757500-1-bjorn.andersson@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 17a2df6a263e..741c2ebcf443 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -929,6 +929,7 @@ CONFIG_RASPBERRYPI_POWER=y CONFIG_FSL_DPAA=y CONFIG_FSL_MC_DPIO=y CONFIG_QCOM_AOSS_QMP=y +CONFIG_QCOM_COMMAND_DB=y CONFIG_QCOM_GENI_SE=y CONFIG_QCOM_RMTFS_MEM=m CONFIG_QCOM_RPMH=y From 721d10be5ccd7194446db40f1b9534cfe7088d73 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Tue, 3 Nov 2020 03:54:31 +0300 Subject: [PATCH 177/799] arm64: dts: qcom: enable rtc on qrb5165-rb5 board Enable PMIC's RTC device on RB5 board. Signed-off-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20201103005432.1181832-1-dmitry.baryshkov@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/pm8150.dtsi | 2 +- arch/arm64/boot/dts/qcom/qrb5165-rb5.dts | 4 ++++ 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/pm8150.dtsi b/arch/arm64/boot/dts/qcom/pm8150.dtsi index 1b6406927509..a53eccf2b695 100644 --- a/arch/arm64/boot/dts/qcom/pm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8150.dtsi @@ -97,7 +97,7 @@ }; }; - rtc@6000 { + pm8150_rtc: rtc@6000 { compatible = "qcom,pm8941-rtc"; reg = <0x6000>; reg-names = "rtc", "alarm"; diff --git a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts index 1528a865f1f8..fec31655141c 100644 --- a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts +++ b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts @@ -459,6 +459,10 @@ "PM3003A_MODE"; }; +&pm8150_rtc { + status = "okay"; +}; + &qupv3_id_0 { status = "okay"; }; From db5f5da2efd720be29e403fea964599032c542ec Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Tue, 3 Nov 2020 03:54:32 +0300 Subject: [PATCH 178/799] arm64: dts: qcom: enable rtc on sm8250-mtp board Enable PMIC's RTC device on SM8250-MTP board. Signed-off-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20201103005432.1181832-2-dmitry.baryshkov@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8250-mtp.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8250-mtp.dts b/arch/arm64/boot/dts/qcom/sm8250-mtp.dts index fd194ed7fbc8..c85cab9c9b41 100644 --- a/arch/arm64/boot/dts/qcom/sm8250-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8250-mtp.dts @@ -378,6 +378,10 @@ /* rtc6226 @ 64 */ }; +&pm8150_rtc { + status = "okay"; +}; + &qupv3_id_0 { status = "okay"; }; From c422aa82abb75436bc31e0da7970aa1f9248b090 Mon Sep 17 00:00:00 2001 From: Stanimir Varbanov Date: Mon, 2 Nov 2020 13:35:29 +0200 Subject: [PATCH 179/799] arm64: dts: sdm845: Add interconnect properties for Venus Populate Venus DT node with interconnect properties. Reviewed-by: Georgi Djakov Signed-off-by: Stanimir Varbanov Link: https://lore.kernel.org/r/20201102113529.16152-1-stanimir.varbanov@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 40e8c11f23ab..aca7e9c954e0 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -3661,6 +3661,9 @@ iommus = <&apps_smmu 0x10a0 0x8>, <&apps_smmu 0x10b0 0x0>; memory-region = <&venus_mem>; + interconnects = <&mmss_noc MASTER_VIDEO_P0 0 &mem_noc SLAVE_EBI1 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_VENUS_CFG 0>; + interconnect-names = "video-mem", "cpu-cfg"; video-core0 { compatible = "venus-decoder"; From ab8e32da3a39e558d2fa2bc46a25eb2f0e885a16 Mon Sep 17 00:00:00 2001 From: Alexandru Stan Date: Wed, 21 Oct 2020 22:04:44 -0700 Subject: [PATCH 180/799] arm64: dts: qcom: trogdor: Add brightness-levels We want userspace to represent the human perceived brightness. Since the led drivers and the leds themselves don't have a linear response to the value we give them in terms of perceived brightness, we'll bake the curve into the dts. The panel also doesn't have a good response under 5%, so we'll avoid sending it anything lower than that. Note: Ideally this patch should be coupled with the driver change from "backlight: pwm_bl: Fix interpolation", but it can work without it, without looking too ugly. Acked-by: Daniel Thompson Reviewed-by: Douglas Anderson Signed-off-by: Alexandru Stan Link: https://lore.kernel.org/r/20201021220404.v3.2.Ie4d84af5a85e8dcb8f575845518fa39f324a827d@changeid Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi index 0759896a0df5..8653a38a3e42 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi @@ -179,6 +179,15 @@ backlight: backlight { compatible = "pwm-backlight"; + /* The panels don't seem to like anything below ~ 5% */ + brightness-levels = < + 196 256 324 400 484 576 676 784 900 1024 1156 1296 + 1444 1600 1764 1936 2116 2304 2500 2704 2916 3136 + 3364 3600 3844 4096 + >; + num-interpolated-steps = <64>; + default-brightness-level = <951>; + pwms = <&cros_ec_pwm 1>; enable-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>; power-supply = <&ppvar_sys>; From 37f7a7b68004807d230fedcf090b09ea501086a9 Mon Sep 17 00:00:00 2001 From: Samuel Holland Date: Wed, 4 Nov 2020 23:41:30 -0600 Subject: [PATCH 181/799] arm64: dts: allwinner: pinephone: Remove AC power supply The AXP803 in the Pinephone has its ACIN and VBUS pins shorted together. In this configuration, the VBUS control registers take priority over the ACIN control registers, which means the ACIN sysfs knobs have no effect. Remove the AC power supply from the DTS, since VBUS is really the only power supply. Signed-off-by: Samuel Holland Signed-off-by: Maxime Ripard Link: https://lore.kernel.org/r/20201105054135.24860-2-samuel@sholland.org --- arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi | 4 ---- 1 file changed, 4 deletions(-) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi index 5780713b0dba..3776f168d023 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi @@ -251,10 +251,6 @@ #include "axp803.dtsi" -&ac_power_supply { - status = "okay"; -}; - &battery_power_supply { status = "okay"; }; From 3cf9bf3b25505d8e2a0366c35b0af6b48e7a3c40 Mon Sep 17 00:00:00 2001 From: Samuel Holland Date: Wed, 4 Nov 2020 23:41:31 -0600 Subject: [PATCH 182/799] arm64: dts: allwinner: pinephone: Set ALDO3 to exactly 3v0 ALDO3 is used as the power supply for the LRADC keys voltage divider, in addition to supplying AVCC and VCC-PLL. While AVCC and VCC-PLL will accept any voltage between 2v7 and 3v3, LRADC needs a precise 3v0 input to maintain the expected 2:3 ratio between the internal 2v0 reference voltage and the external supply. Signed-off-by: Samuel Holland Signed-off-by: Maxime Ripard Link: https://lore.kernel.org/r/20201105054135.24860-3-samuel@sholland.org --- arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi index 3776f168d023..555837722be2 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi @@ -270,8 +270,8 @@ ®_aldo3 { regulator-always-on; - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; regulator-name = "vcc-pll-avcc"; }; From 085d96b88403edfc0a8ee340b7e6122c34f039c2 Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Wed, 4 Nov 2020 23:41:32 -0600 Subject: [PATCH 183/799] arm64: dts: allwinner: pinephone: Add LED flash All revisions of the PinePhone have an SGM3140 LED flash. The gpios were swapped on v1.0 of the board, but this was fixed in later revisions. Signed-off-by: Luca Weiss Signed-off-by: Samuel Holland Signed-off-by: Maxime Ripard Link: https://lore.kernel.org/r/20201105054135.24860-4-samuel@sholland.org --- .../boot/dts/allwinner/sun50i-a64-pinephone-1.0.dts | 5 +++++ .../boot/dts/allwinner/sun50i-a64-pinephone-1.1.dts | 5 +++++ .../boot/dts/allwinner/sun50i-a64-pinephone-1.2.dts | 5 +++++ .../boot/dts/allwinner/sun50i-a64-pinephone.dtsi | 11 +++++++++++ 4 files changed, 26 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.0.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.0.dts index 0c42272106af..3d5a2ae9aa39 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.0.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.0.dts @@ -9,3 +9,8 @@ model = "Pine64 PinePhone Developer Batch (1.0)"; compatible = "pine64,pinephone-1.0", "allwinner,sun50i-a64"; }; + +&sgm3140 { + enable-gpios = <&pio 2 3 GPIO_ACTIVE_HIGH>; /* PC3 */ + flash-gpios = <&pio 3 24 GPIO_ACTIVE_HIGH>; /* PD24 */ +}; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.1.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.1.dts index 3e99a87e9ce5..c9b9f6e9ee8c 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.1.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.1.dts @@ -28,3 +28,8 @@ num-interpolated-steps = <50>; default-brightness-level = <400>; }; + +&sgm3140 { + enable-gpios = <&pio 3 24 GPIO_ACTIVE_HIGH>; /* PD24 */ + flash-gpios = <&pio 2 3 GPIO_ACTIVE_HIGH>; /* PC3 */ +}; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.2.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.2.dts index a9f5b670c9b8..94e4f11e0215 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.2.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.2.dts @@ -38,3 +38,8 @@ interrupt-parent = <&pio>; interrupts = <1 1 IRQ_TYPE_EDGE_RISING>; /* PB1 */ }; + +&sgm3140 { + enable-gpios = <&pio 3 24 GPIO_ACTIVE_HIGH>; /* PD24 */ + flash-gpios = <&pio 2 3 GPIO_ACTIVE_HIGH>; /* PC3 */ +}; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi index 555837722be2..8285391a0265 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi @@ -49,6 +49,17 @@ }; }; + sgm3140: led-controller { + compatible = "sgmicro,sgm3140"; + vin-supply = <®_dcdc1>; + + sgm3140_flash: led { + function = LED_FUNCTION_FLASH; + color = ; + flash-max-timeout-us = <250000>; + }; + }; + speaker_amp: audio-amplifier { compatible = "simple-audio-amplifier"; enable-gpios = <&pio 2 7 GPIO_ACTIVE_HIGH>; /* PC7 */ From a966ef6297dd6829714ba5f6abd9ab2d67f8a935 Mon Sep 17 00:00:00 2001 From: Ondrej Jirman Date: Wed, 4 Nov 2020 23:41:33 -0600 Subject: [PATCH 184/799] arm64: dts: allwinner: pinephone: Add light/proximity sensor Pinephone has STK3311-X proximity sensor. Add support for it. Signed-off-by: Ondrej Jirman Signed-off-by: Samuel Holland Signed-off-by: Maxime Ripard Link: https://lore.kernel.org/r/20201105054135.24860-5-samuel@sholland.org --- .../arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi index 8285391a0265..8617b79d33e6 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi @@ -160,6 +160,16 @@ vddio-supply = <®_dldo1>; }; + /* Light/proximity sensor */ + stk3311@48 { + compatible = "sensortek,stk3311"; + reg = <0x48>; + interrupt-parent = <&pio>; + interrupts = <1 0 IRQ_TYPE_EDGE_FALLING>; /* PB0 */ + vdd-supply = <®_ldo_io0>; + leda-supply = <®_dldo1>; + }; + /* Accelerometer/gyroscope */ mpu6050@68 { compatible = "invensense,mpu6050"; From 4fcf6f34879908a67454d3cdcf0f6b593947f96d Mon Sep 17 00:00:00 2001 From: Ondrej Jirman Date: Wed, 4 Nov 2020 23:41:34 -0600 Subject: [PATCH 185/799] arm64: dts: allwinner: pinephone: Add WiFi support The PinePhone has a Realtek rtl8723cs WiFi module. On mainboard revisions 1.0 and 1.1, the reset input is always pulled high, so no power sequence is needed. On mainboard revision 1.2, the reset input is connected to PL2. Signed-off-by: Ondrej Jirman Signed-off-by: Samuel Holland Signed-off-by: Maxime Ripard Link: https://lore.kernel.org/r/20201105054135.24860-6-samuel@sholland.org --- .../allwinner/sun50i-a64-pinephone-1.2.dts | 9 ++++++++ .../dts/allwinner/sun50i-a64-pinephone.dtsi | 22 +++++++++++++++++++ 2 files changed, 31 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.2.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.2.dts index 94e4f11e0215..acc0ab53b9c1 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.2.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.2.dts @@ -8,6 +8,11 @@ / { model = "Pine64 PinePhone (1.2)"; compatible = "pine64,pinephone-1.2", "allwinner,sun50i-a64"; + + wifi_pwrseq: wifi-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */ + }; }; &backlight { @@ -39,6 +44,10 @@ interrupts = <1 1 IRQ_TYPE_EDGE_RISING>; /* PB1 */ }; +&mmc1 { + mmc-pwrseq = <&wifi_pwrseq>; +}; + &sgm3140 { enable-gpios = <&pio 3 24 GPIO_ACTIVE_HIGH>; /* PD24 */ flash-gpios = <&pio 2 3 GPIO_ACTIVE_HIGH>; /* PC3 */ diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi index 8617b79d33e6..07f66f4cefac 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi @@ -13,6 +13,7 @@ / { aliases { + ethernet0 = &rtl8723cs; serial0 = &uart0; }; @@ -49,6 +50,13 @@ }; }; + reg_vbat_wifi: vbat-wifi { + compatible = "regulator-fixed"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vbat-wifi"; + }; + sgm3140: led-controller { compatible = "sgmicro,sgm3140"; vin-supply = <®_dcdc1>; @@ -216,6 +224,20 @@ status = "okay"; }; +&mmc1 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins>; + vmmc-supply = <®_vbat_wifi>; + vqmmc-supply = <®_dldo4>; + bus-width = <4>; + non-removable; + status = "okay"; + + rtl8723cs: wifi@1 { + reg = <1>; + }; +}; + &mmc2 { pinctrl-names = "default"; pinctrl-0 = <&mmc2_pins>; From 976843d5e8203829adb99bc40bc6f556997881c8 Mon Sep 17 00:00:00 2001 From: Ondrej Jirman Date: Wed, 4 Nov 2020 23:41:35 -0600 Subject: [PATCH 186/799] arm64: dts: allwinner: pinephone: Add Bluetooth support The PinePhone has a Realtek rtl8723cs Bluetooth controller. Signed-off-by: Ondrej Jirman Signed-off-by: Samuel Holland Signed-off-by: Maxime Ripard Link: https://lore.kernel.org/r/20201105054135.24860-7-samuel@sholland.org --- .../boot/dts/allwinner/sun50i-a64-pinephone.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi index 07f66f4cefac..2da69450eec1 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi @@ -447,6 +447,19 @@ status = "okay"; }; +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>; + status = "okay"; + + bluetooth { + compatible = "realtek,rtl8723cs-bt"; + device-wake-gpios = <&pio 7 6 GPIO_ACTIVE_LOW>; /* PH6 */ + enable-gpios = <&r_pio 0 4 GPIO_ACTIVE_HIGH>; /* PL4 */ + host-wake-gpios = <&r_pio 0 5 GPIO_ACTIVE_HIGH>; /* PL5 */ + }; +}; + /* Connected to the modem (hardware flow control can't be used) */ &uart3 { pinctrl-names = "default"; From 007fda302d771d818347ce85043ae8681b87b6e0 Mon Sep 17 00:00:00 2001 From: Marek Szyprowski Date: Tue, 3 Nov 2020 15:02:14 +0100 Subject: [PATCH 187/799] ARM: dts: exynos: Enable DWC2 dual-role support on OdroidU3+ boards MicroUSB port on OdroidU3+ boards can operate both as peripheral or as host port. Till now it was configured as pheriperal only port, but it turned out that the DWC2 driver code already handles everything needed to support USB role-switch, so switch it to dual-role (OTG) mode. This has no effect on OdroidU3 (without 'plus') and OdroidX2, which doesn't have USB needed ID pin and VBUS wiring. Those will still operate correctly in pheriperal mode only. Signed-off-by: Marek Szyprowski Tested-by: Anand Moon Link: https://lore.kernel.org/r/20201103140214.21690-1-m.szyprowski@samsung.com Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos4412-odroid-common.dtsi | 1 - arch/arm/boot/dts/exynos4412-odroidu3.dts | 14 ++++++++++++++ arch/arm/boot/dts/exynos4412-odroidx.dts | 4 ++++ 3 files changed, 18 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi index 1ca9d8b5f868..4a67390426b6 100644 --- a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi +++ b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi @@ -256,7 +256,6 @@ }; &hsotg { - dr_mode = "peripheral"; status = "okay"; vusb_d-supply = <&ldo15_reg>; vusb_a-supply = <&ldo12_reg>; diff --git a/arch/arm/boot/dts/exynos4412-odroidu3.dts b/arch/arm/boot/dts/exynos4412-odroidu3.dts index b8549d846f86..3bc83d63de6b 100644 --- a/arch/arm/boot/dts/exynos4412-odroidu3.dts +++ b/arch/arm/boot/dts/exynos4412-odroidu3.dts @@ -21,6 +21,15 @@ reg = <0x40000000 0x7FF00000>; }; + vbus_otg_reg: regulator-1 { + compatible = "regulator-fixed"; + regulator-name = "VBUS_VDD_5.0V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpl2 0 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + leds { compatible = "gpio-leds"; led1 { @@ -105,6 +114,11 @@ phy-names = "hsic0", "hsic1"; }; +&hsotg { + dr_mode = "otg"; + vbus-supply = <&vbus_otg_reg>; +}; + &sound { model = "Odroid-U3"; samsung,audio-widgets = diff --git a/arch/arm/boot/dts/exynos4412-odroidx.dts b/arch/arm/boot/dts/exynos4412-odroidx.dts index 46381e9097f4..d6ee62bf336c 100644 --- a/arch/arm/boot/dts/exynos4412-odroidx.dts +++ b/arch/arm/boot/dts/exynos4412-odroidx.dts @@ -76,6 +76,10 @@ }; }; +&hsotg { + dr_mode = "peripheral"; +}; + &mshc_0 { vqmmc-supply = <&buck8_reg>; }; From 8e9c052a483db5f9ae098d9b686ed80e2e98a8c5 Mon Sep 17 00:00:00 2001 From: Christian Hewitt Date: Mon, 26 Oct 2020 13:41:01 +0000 Subject: [PATCH 188/799] arm64: dts: meson: remove empty lines from aml-s905x-cc v2 dts Fixes: 63fafc5a046b ("arm64: dts: meson: initial support for aml-s905x-cc v2") Signed-off-by: Christian Hewitt Reviewed-by: Neil Armstrong Signed-off-by: Kevin Hilman Link: https://lore.kernel.org/r/20201026134101.10594-1-christianshewitt@gmail.com --- .../boot/dts/amlogic/meson-gxl-s905x-libretech-cc-v2.dts | 4 ---- 1 file changed, 4 deletions(-) diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc-v2.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc-v2.dts index 675eaa87963e..9a3c08e6e6cc 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc-v2.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc-v2.dts @@ -84,7 +84,6 @@ regulator-always-on; }; - vcck: regulator-vcck { compatible = "regulator-fixed"; regulator-name = "VCCK"; @@ -124,7 +123,6 @@ regulator-always-on; }; - vddio_card: regulator-vddio-card { compatible = "regulator-gpio"; regulator-name = "VDDIO_CARD"; @@ -195,7 +193,6 @@ }; }; - &aiu { status = "okay"; }; @@ -207,7 +204,6 @@ hdmi-phandle = <&hdmi_tx>; }; - ðmac { status = "okay"; }; From 7bd5175918eb4b294c0979c75056f20fd90a50bf Mon Sep 17 00:00:00 2001 From: Christian Hewitt Date: Sun, 1 Nov 2020 02:10:12 +0000 Subject: [PATCH 189/799] arm64: dts: meson: add watchdog to g12-common dtsi G12 vendor kernels show the watchdog on the same address as AXG so add the node to meson-g12-common.dtsi. GX boards inherit the same from meson-gx.dtsi. v2 fix typo in node name (s/wtd/wdt) Signed-off-by: Christian Hewitt Reviewed-by: Neil Armstrong Tested-by: Neil Armstrong Signed-off-by: Kevin Hilman Link: https://lore.kernel.org/r/20201101021012.24519-1-christianshewitt@gmail.com --- arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi index 1e83ec5b8c91..314095b79a45 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi @@ -2179,6 +2179,12 @@ amlogic,channel-interrupts = <64 65 66 67 68 69 70 71>; }; + watchdog: wdt@f0d0 { + compatible = "amlogic,meson-gxbb-wdt"; + reg = <0x0 0xf0d0 0x0 0x10>; + clocks = <&xtal>; + }; + spicc0: spi@13000 { compatible = "amlogic,meson-g12a-spicc"; reg = <0x0 0x13000 0x0 0x44>; From 9ef3a2c5859e02afc67f71cd31ff5177771b48c1 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C5=81ukasz=20Stelmach?= Date: Tue, 3 Nov 2020 19:44:09 +0100 Subject: [PATCH 190/799] ARM: dts: exynos: Add Ethernet interface description for Odroid XU3 Lite MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add Ethernet interface description for Odroid XU3 Lite. Add an alias to enable bootloaders to find the Ethernet interface and assign a MAC address. Signed-off-by: Łukasz Stelmach Link: https://lore.kernel.org/r/20201103184412.18874-4-l.stelmach@samsung.com Signed-off-by: Krzysztof Kozlowski --- .../boot/dts/exynos5422-odroidxu3-lite.dts | 22 +++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3-lite.dts b/arch/arm/boot/dts/exynos5422-odroidxu3-lite.dts index 98feecad5489..62c5928aa994 100644 --- a/arch/arm/boot/dts/exynos5422-odroidxu3-lite.dts +++ b/arch/arm/boot/dts/exynos5422-odroidxu3-lite.dts @@ -16,6 +16,10 @@ / { model = "Hardkernel Odroid XU3 Lite"; compatible = "hardkernel,odroid-xu3-lite", "samsung,exynos5800", "samsung,exynos5"; + + aliases { + ethernet = ðernet; + }; }; &arm_a7_pmu { @@ -103,3 +107,21 @@ &usbdrd_dwc3_1 { dr_mode = "peripheral"; }; + +&usbhost2 { + #address-cells = <1>; + #size-cells = <0>; + + hub@1 { + compatible = "usb0424,9514"; + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + ethernet: usbether@1 { + compatible = "usb0424,ec00"; + reg = <1>; + local-mac-address = [00 00 00 00 00 00]; /* Filled in by a bootloader */ + }; + }; +}; From dff7ae5c50ebc69929973f948d87de6c661ef42d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C5=81ukasz=20Stelmach?= Date: Tue, 3 Nov 2020 19:44:10 +0100 Subject: [PATCH 191/799] ARM: dts: exynos: Add Ethernet interface description for Odroid XU MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add Ethernet interface description for Odroid XU. Add an alias to enable bootloaders to find the Ethernet interface and assign a MAC address. Signed-off-by: Łukasz Stelmach Link: https://lore.kernel.org/r/20201103184412.18874-5-l.stelmach@samsung.com Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos5410-odroidxu.dts | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm/boot/dts/exynos5410-odroidxu.dts b/arch/arm/boot/dts/exynos5410-odroidxu.dts index 40cb0727aea1..949c0721cdb4 100644 --- a/arch/arm/boot/dts/exynos5410-odroidxu.dts +++ b/arch/arm/boot/dts/exynos5410-odroidxu.dts @@ -19,6 +19,10 @@ model = "Hardkernel Odroid XU"; compatible = "hardkernel,odroid-xu", "samsung,exynos5410", "samsung,exynos5"; + aliases { + ethernet = ðernet; + }; + memory@40000000 { device_type = "memory"; reg = <0x40000000 0x7ea00000>; @@ -665,3 +669,14 @@ vdd33-supply = <&ldo12_reg>; vdd10-supply = <&ldo15_reg>; }; + +&usbhost2 { + #address-cells = <1>; + #size-cells = <0>; + + ethernet: usbether@2 { + compatible = "usb0424,9730"; + reg = <2>; + local-mac-address = [00 00 00 00 00 00]; /* Filled in by a bootloader */ + }; +}; From 6eff260412bdf74ede126016f5e0026b7861db77 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C5=81ukasz=20Stelmach?= Date: Tue, 3 Nov 2020 19:44:11 +0100 Subject: [PATCH 192/799] ARM: dts: exynos: Add Ethernet interface description for Odroid U3 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add Ethernet interface description for Odroid U3. Add an alias to enable bootloaders to find the Ethernet interface and assign a MAC address. Signed-off-by: Łukasz Stelmach Link: https://lore.kernel.org/r/20201103184412.18874-6-l.stelmach@samsung.com Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos4412-odroidu3.dts | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm/boot/dts/exynos4412-odroidu3.dts b/arch/arm/boot/dts/exynos4412-odroidu3.dts index 3bc83d63de6b..efaf7533e84f 100644 --- a/arch/arm/boot/dts/exynos4412-odroidu3.dts +++ b/arch/arm/boot/dts/exynos4412-odroidu3.dts @@ -16,6 +16,10 @@ model = "Hardkernel ODROID-U3 board based on Exynos4412"; compatible = "hardkernel,odroid-u3", "samsung,exynos4412", "samsung,exynos4"; + aliases { + ethernet = ðernet; + }; + memory@40000000 { device_type = "memory"; reg = <0x40000000 0x7FF00000>; @@ -110,8 +114,16 @@ }; &ehci { + #address-cells = <1>; + #size-cells = <0>; phys = <&exynos_usbphy 2>, <&exynos_usbphy 3>; phy-names = "hsic0", "hsic1"; + + ethernet: usbether@2 { + compatible = "usb0424,9730"; + reg = <2>; + local-mac-address = [00 00 00 00 00 00]; /* Filled in by a bootloader */ + }; }; &hsotg { From d9e1af3a13947742cd8bf8007ba22d977a6b170e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C5=81ukasz=20Stelmach?= Date: Tue, 3 Nov 2020 19:44:12 +0100 Subject: [PATCH 193/799] ARM: dts: exynos: Add Ethernet interface description for Odroid X/X2 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add Ethernet interface description for Odroid X/X2. Add an alias to enable bootloaders to find the Ethernet interface and assign a MAC address. Signed-off-by: Łukasz Stelmach Link: https://lore.kernel.org/r/20201103184412.18874-7-l.stelmach@samsung.com Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos4412-odroidx.dts | 26 ++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/arch/arm/boot/dts/exynos4412-odroidx.dts b/arch/arm/boot/dts/exynos4412-odroidx.dts index d6ee62bf336c..0e9d626e740a 100644 --- a/arch/arm/boot/dts/exynos4412-odroidx.dts +++ b/arch/arm/boot/dts/exynos4412-odroidx.dts @@ -15,6 +15,10 @@ model = "Hardkernel ODROID-X board based on Exynos4412"; compatible = "hardkernel,odroid-x", "samsung,exynos4412", "samsung,exynos4"; + aliases { + ethernet = ðernet; + }; + memory@40000000 { device_type = "memory"; reg = <0x40000000 0x3FF00000>; @@ -60,8 +64,30 @@ }; &ehci { + #address-cells = <1>; + #size-cells = <0>; phys = <&exynos_usbphy 2>; phy-names = "hsic0"; + + hub@2 { + compatible = "usb0424,3503"; + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + + hub@1 { + compatible = "usb0424,9514"; + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + ethernet: usbether@1 { + compatible = "usb0424,ec00"; + reg = <1>; + local-mac-address = [00 00 00 00 00 00]; /* Filled in by a bootloader */ + }; + }; + }; }; &gpio_keys { From 8902a6642771616901ea3f5341926602908eaf3a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C5=81ukasz=20Stelmach?= Date: Thu, 1 Oct 2020 15:52:54 +0200 Subject: [PATCH 194/799] ARM: dts: exynos: Add a placeholder for a MAC address MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add a placeholder for a MAC address. A bootloader may fill it to set the MAC address and override EEPROM settings. Signed-off-by: Łukasz Stelmach Link: https://lore.kernel.org/r/20201001135254.28178-1-l.stelmach@samsung.com Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos5422-odroidxu3.dts | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3.dts b/arch/arm/boot/dts/exynos5422-odroidxu3.dts index 7c588407f931..53aee3d56f6a 100644 --- a/arch/arm/boot/dts/exynos5422-odroidxu3.dts +++ b/arch/arm/boot/dts/exynos5422-odroidxu3.dts @@ -70,3 +70,21 @@ &usbdrd_dwc3_1 { dr_mode = "peripheral"; }; + +&usbhost2 { + #address-cells = <1>; + #size-cells = <0>; + + hub@1 { + compatible = "usb8087,0024"; + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + ethernet: usbether@1 { + compatible = "usb0c45,6310"; + reg = <1>; + local-mac-address = [00 00 00 00 00 00]; /* Filled in by a bootloader */ + }; + }; +}; From 98c03b6eef3f9c7d8153f96870968615ab489a6b Mon Sep 17 00:00:00 2001 From: Jaehoon Chung Date: Thu, 29 Oct 2020 14:40:17 +0100 Subject: [PATCH 195/799] arm64: dts: exynos: add the WiFi/PCIe support to TM2(e) boards Add the nodes relevant to PCIe PHY and PCIe support. PCIe is used for the WiFi interface (Broadcom Limited BCM4358 802.11ac Wireless LAN SoC). [mszyprow: rewrote commit message, reworked board/generic dts/dtsi split] Signed-off-by: Jaehoon Chung Signed-off-by: Marek Szyprowski Link: https://lore.kernel.org/r/20201029134017.27400-7-m.szyprowski@samsung.com Signed-off-by: Krzysztof Kozlowski --- .../boot/dts/exynos/exynos5433-pinctrl.dtsi | 2 +- .../dts/exynos/exynos5433-tm2-common.dtsi | 24 ++++++++++++- arch/arm64/boot/dts/exynos/exynos5433.dtsi | 36 +++++++++++++++++++ 3 files changed, 60 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi b/arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi index 9df7c65593a1..32a6518517e5 100644 --- a/arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi @@ -329,7 +329,7 @@ }; pcie_bus: pcie_bus { - samsung,pins = "gpr3-4", "gpr3-5", "gpr3-6", "gpr3-7"; + samsung,pins = "gpr3-4", "gpr3-5", "gpr3-6"; samsung,pin-function = ; samsung,pin-pud = ; }; diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi b/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi index 97a2f0c7c0cf..5ec447f0cf5d 100644 --- a/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi @@ -968,6 +968,25 @@ bus-width = <4>; }; +&pcie { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pcie_bus &pcie_wlanen>; + vdd10-supply = <&ldo6_reg>; + vdd18-supply = <&ldo7_reg>; + assigned-clocks = <&cmu_fsys CLK_MOUT_SCLK_PCIE_100_USER>, + <&cmu_top CLK_MOUT_SCLK_PCIE_100>; + assigned-clock-parents = <&cmu_top CLK_SCLK_PCIE_100_FSYS>, + <&cmu_top CLK_MOUT_BUS_PLL_USER>; + assigned-clock-rates = <0>, <100000000>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>; +}; + +&pcie_phy { + status = "okay"; +}; + &ppmu_d0_general { status = "okay"; events { @@ -1084,8 +1103,11 @@ pinctrl-names = "default"; pinctrl-0 = <&initial_ese>; + pcie_wlanen: pcie-wlanen { + PIN(INPUT, gpj2-0, UP, FAST_SR4); + }; + initial_ese: initial-state { - PIN(INPUT, gpj2-0, DOWN, FAST_SR1); PIN(INPUT, gpj2-1, DOWN, FAST_SR1); PIN(INPUT, gpj2-2, DOWN, FAST_SR1); }; diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi index 0a886bb6c806..7853a908fe39 100644 --- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi @@ -1029,6 +1029,11 @@ reg = <0x145f0000 0x1038>; }; + syscon_fsys: syscon@156f0000 { + compatible = "syscon"; + reg = <0x156f0000 0x1044>; + }; + gsc_0: video-scaler@13c00000 { compatible = "samsung,exynos5433-gsc"; reg = <0x13c00000 0x1000>; @@ -1830,6 +1835,37 @@ status = "disabled"; }; }; + + pcie_phy: pcie-phy@15680000 { + compatible = "samsung,exynos5433-pcie-phy"; + reg = <0x15680000 0x1000>; + samsung,pmu-syscon = <&pmu_system_controller>; + samsung,fsys-sysreg = <&syscon_fsys>; + #phy-cells = <0>; + status = "disabled"; + }; + + pcie: pcie@15700000 { + compatible = "samsung,exynos5433-pcie"; + reg = <0x15700000 0x1000>, <0x156b0000 0x1000>, + <0x0c000000 0x1000>; + reg-names = "dbi", "elbi", "config"; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + device_type = "pci"; + interrupts = ; + clocks = <&cmu_fsys CLK_PCIE>, + <&cmu_fsys CLK_PCLK_PCIE_PHY>; + clock-names = "pcie", "pcie_bus"; + num-lanes = <1>; + num-viewport = <3>; + bus-range = <0x00 0xff>; + phys = <&pcie_phy>; + ranges = <0x81000000 0 0 0x0c001000 0 0x00010000>, + <0x82000000 0 0x0c011000 0x0c011000 0 0x03feefff>; + status = "disabled"; + }; }; timer: timer { From 33958b22f3775ed8ac6594f89fff1ed150bed3fd Mon Sep 17 00:00:00 2001 From: Matteo Scordino Date: Thu, 5 Nov 2020 18:32:29 +0000 Subject: [PATCH 196/799] ARM: dts: sun8i: s3: Add dtsi for the Elimo Impetus SoM The Elimo Engineering Impetus is an Open Source Hardware System-on-Module based on the SoChip S3 SoC. It is meant for integration into carrier boards or, more generally, larger designs, and uses an M2 connector to facilitate that. Interfaces on the M.2/NGFF 42mm connector: WiFi IEEE 802. 11abgn (on-module Realtek) Bluetooth 4.2/BLE (on-module Realtek) RGB LCD Interface (on-module connector) MIPI Camera Interface (on-module connector) IEEE 802. 3u Ethernet MAC (external connecto) USB2.0 (Host, Device, OTG) (external connector) Audio Line In/Out (external connector) Signed-off-by: Matteo Scordino Signed-off-by: Maxime Ripard Link: https://lore.kernel.org/r/20201105183231.12952-2-matteo.scordino@gmail.com --- arch/arm/boot/dts/sun8i-s3-elimo-impetus.dtsi | 44 +++++++++++++++++++ 1 file changed, 44 insertions(+) create mode 100644 arch/arm/boot/dts/sun8i-s3-elimo-impetus.dtsi diff --git a/arch/arm/boot/dts/sun8i-s3-elimo-impetus.dtsi b/arch/arm/boot/dts/sun8i-s3-elimo-impetus.dtsi new file mode 100644 index 000000000000..24d507cdbcf9 --- /dev/null +++ b/arch/arm/boot/dts/sun8i-s3-elimo-impetus.dtsi @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2020 Matteo Scordino + */ + +/dts-v1/; +#include "sun8i-v3.dtsi" +#include "sunxi-common-regulators.dtsi" + +/ { + model = "Elimo Impetus SoM"; + compatible = "elimo,impetus", "sochip,s3", "allwinner,sun8i-v3"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&mmc0 { + broken-cd; + bus-width = <4>; + vmmc-supply = <®_vcc3v3>; + status = "okay"; +}; + +&uart0 { + pinctrl-0 = <&uart0_pb_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&usb_otg { + dr_mode = "otg"; + status = "okay"; +}; + +&usbphy { + usb0_id_det-gpio = <&pio 5 6 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; From c1c5bafd4481b40dfe4a4703702cb95930703426 Mon Sep 17 00:00:00 2001 From: Matteo Scordino Date: Thu, 5 Nov 2020 18:32:30 +0000 Subject: [PATCH 197/799] dt-bindings: arm: sunxi: add Elimo bindings Document board compatible names for Elimo Engineering Impetus and Initium Signed-off-by: Matteo Scordino Signed-off-by: Maxime Ripard Link: https://lore.kernel.org/r/20201105183231.12952-3-matteo.scordino@gmail.com --- Documentation/devicetree/bindings/arm/sunxi.yaml | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/sunxi.yaml b/Documentation/devicetree/bindings/arm/sunxi.yaml index 0f23133672a3..ef2ce3bd2bed 100644 --- a/Documentation/devicetree/bindings/arm/sunxi.yaml +++ b/Documentation/devicetree/bindings/arm/sunxi.yaml @@ -201,6 +201,19 @@ properties: - const: dserve,dsrv9703c - const: allwinner,sun4i-a10 + - description: Elimo Engineering Impetus SoM + items: + - const: elimo,impetus + - const: sochip,s3 + - const: allwinner,sun8i-v3 + + - description: Elimo Engineering Initium + items: + - const: elimo,initium + - const: elimo,impetus + - const: sochip,s3 + - const: allwinner,sun8i-v3 + - description: Empire Electronix D709 Tablet items: - const: empire-electronix,d709 From da42b98d5c7d5a30d963633a964586cb68a5c886 Mon Sep 17 00:00:00 2001 From: Matteo Scordino Date: Thu, 5 Nov 2020 18:32:31 +0000 Subject: [PATCH 198/799] ARM: dts: sun8i: s3: Add dts for the Elimo Initium SBC The Elimo Engineering Initium is an Open Source Hardware Single Board Computer based on the Elimo Impetus SoM. It is meant as the first development platform for the Impetus, providing convenient access to the peripherals on the Impetus. It provides: USB-C power input UART-to-USB bridge on the USB-C connector, connected to UART1 USB-A connector for USB2.0 (Host, Device, OTG) Audio Line In/Out Pin header to access all signals on the M2 connector of the SoM Signed-off-by: Matteo Scordino Signed-off-by: Maxime Ripard Link: https://lore.kernel.org/r/20201105183231.12952-4-matteo.scordino@gmail.com --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/sun8i-s3-elimo-initium.dts | 29 ++++++++++++++++++++ 2 files changed, 30 insertions(+) create mode 100644 arch/arm/boot/dts/sun8i-s3-elimo-initium.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 4f0adfead547..50e438ab8a00 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1208,6 +1208,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \ sun8i-r16-nintendo-super-nes-classic.dtb \ sun8i-r16-parrot.dtb \ sun8i-r40-bananapi-m2-ultra.dtb \ + sun8i-s3-elimo-initium.dtb \ sun8i-s3-lichee-zero-plus.dtb \ sun8i-s3-pinecube.dtb \ sun8i-t3-cqa3t-bv3.dtb \ diff --git a/arch/arm/boot/dts/sun8i-s3-elimo-initium.dts b/arch/arm/boot/dts/sun8i-s3-elimo-initium.dts new file mode 100644 index 000000000000..039677c2cc65 --- /dev/null +++ b/arch/arm/boot/dts/sun8i-s3-elimo-initium.dts @@ -0,0 +1,29 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2020 Matteo Scordino + */ + +/dts-v1/; +#include "sun8i-s3-elimo-impetus.dtsi" + +/ { + model = "Elimo Initium"; + compatible = "elimo,initium", "elimo,impetus", "sochip,s3", + "allwinner,sun8i-v3"; + + aliases { + serial1 = &uart1; + }; +}; + +&uart1 { + pinctrl-0 = <&uart1_pg_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&emac { + phy-handle = <&int_mii_phy>; + phy-mode = "mii"; + status = "okay"; +}; From 030eea2a1127700af0176345b404db943232a908 Mon Sep 17 00:00:00 2001 From: Samuel Holland Date: Thu, 5 Nov 2020 21:20:55 -0600 Subject: [PATCH 199/799] arm64: dts: allwinner: pinephone: Use generic sensor node names Instead of duplicating part of the compatible string in the node name, use generic names as recommended by (and listed in) section 2.2.2 of the Devicetree Specification. Suggested-by: Maxime Ripard Signed-off-by: Samuel Holland Signed-off-by: Maxime Ripard Link: https://lore.kernel.org/r/20201106032055.51530-1-samuel@sholland.org --- arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi index 2da69450eec1..2dfe9bae8c67 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi @@ -161,7 +161,7 @@ status = "okay"; /* Magnetometer */ - lis3mdl: lis3mdl@1e { + lis3mdl: magnetometer@1e { compatible = "st,lis3mdl-magn"; reg = <0x1e>; vdd-supply = <®_dldo1>; @@ -169,7 +169,7 @@ }; /* Light/proximity sensor */ - stk3311@48 { + light-sensor@48 { compatible = "sensortek,stk3311"; reg = <0x48>; interrupt-parent = <&pio>; @@ -179,7 +179,7 @@ }; /* Accelerometer/gyroscope */ - mpu6050@68 { + accelerometer@68 { compatible = "invensense,mpu6050"; reg = <0x68>; interrupt-parent = <&pio>; From 9340c293ebf0687d53a52c710a8e6fe80bfd6b6b Mon Sep 17 00:00:00 2001 From: Yu-Tung Chang Date: Mon, 2 Nov 2020 18:01:57 +0800 Subject: [PATCH 200/799] ARM: dts: sun8i: h3: Add initial NanoPi R1 support The NanoPi R1 is a complete open source board developed by FriendlyElec for makers, hobbyists, fans and etc. NanoPi R1 key features - Allwinner H3, Quad-core Cortex-A7@1.2GHz - 512MB/1GB DDR3 RAM - 8GB eMMC - microSD slot - 10/100/1000M Ethernet x 1 - 10/100 Ethernet x 1 - Wifi 802.11b/g/n - Bluetooth 4.0 - Serial Debug Port - 5V 2A DC power-supply Signed-off-by: Yu-Tung Chang Signed-off-by: Maxime Ripard Link: https://lore.kernel.org/r/20201102100157.85801-2-mtwget@gmail.com --- .../devicetree/bindings/arm/sunxi.yaml | 5 + arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/sun8i-h3-nanopi-r1.dts | 169 ++++++++++++++++++ 3 files changed, 175 insertions(+) create mode 100644 arch/arm/boot/dts/sun8i-h3-nanopi-r1.dts diff --git a/Documentation/devicetree/bindings/arm/sunxi.yaml b/Documentation/devicetree/bindings/arm/sunxi.yaml index ef2ce3bd2bed..93e608aecae2 100644 --- a/Documentation/devicetree/bindings/arm/sunxi.yaml +++ b/Documentation/devicetree/bindings/arm/sunxi.yaml @@ -264,6 +264,11 @@ properties: - const: friendlyarm,nanopi-neo-plus2 - const: allwinner,sun50i-h5 + - description: FriendlyARM NanoPi R1 + items: + - const: friendlyarm,nanopi-r1 + - const: allwinner,sun8i-h3 + - description: FriendlyARM ZeroPi items: - const: friendlyarm,zeropi diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 50e438ab8a00..ad41489e591d 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1192,6 +1192,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \ sun8i-h3-nanopi-m1-plus.dtb \ sun8i-h3-nanopi-neo.dtb \ sun8i-h3-nanopi-neo-air.dtb \ + sun8i-h3-nanopi-r1.dtb \ sun8i-h3-orangepi-2.dtb \ sun8i-h3-orangepi-lite.dtb \ sun8i-h3-orangepi-one.dtb \ diff --git a/arch/arm/boot/dts/sun8i-h3-nanopi-r1.dts b/arch/arm/boot/dts/sun8i-h3-nanopi-r1.dts new file mode 100644 index 000000000000..204a39f93f4e --- /dev/null +++ b/arch/arm/boot/dts/sun8i-h3-nanopi-r1.dts @@ -0,0 +1,169 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2019 Igor Pecovnik + * Copyright (C) 2020 Jayantajit Gogoi + * Copyright (C) 2020 Yu-Tung Chang +*/ + +#include "sun8i-h3-nanopi.dtsi" +#include + +/ { + model = "FriendlyARM NanoPi R1"; + compatible = "friendlyarm,nanopi-r1", "allwinner,sun8i-h3"; + + aliases { + serial1 = &uart1; + ethernet0 = &emac; + ethernet1 = &wifi; + }; + + reg_gmac_3v3: gmac-3v3 { + compatible = "regulator-fixed"; + regulator-name = "gmac-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <100000>; + enable-active-high; + gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>; /* PD6 */ + }; + + reg_vdd_cpux: gpio-regulator { + compatible = "regulator-gpio"; + regulator-name = "vdd-cpux"; + regulator-type = "voltage"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1300000>; + regulator-ramp-delay = <50>; + gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */ + gpios-states = <0x1>; + states = <1100000 0x0 + 1300000 0x1>; + }; + + wifi_pwrseq: wifi_pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */ + clocks = <&rtc 1>; + clock-names = "ext_clock"; + }; + + leds { + led-2 { + function = LED_FUNCTION_WAN; + color = ; + gpios = <&pio 6 11 GPIO_ACTIVE_HIGH>; /* PG11 */ + }; + + led-3 { + function = LED_FUNCTION_LAN; + color = ; + gpios = <&pio 0 9 GPIO_ACTIVE_HIGH>; /* PA9 */ + }; + }; +}; + +&cpu0 { + cpu-supply = <®_vdd_cpux>; +}; + +&ehci1 { + status = "okay"; +}; + +&ehci2 { + status = "okay"; +}; + +&emac { + pinctrl-names = "default"; + pinctrl-0 = <&emac_rgmii_pins>; + phy-supply = <®_gmac_3v3>; + phy-handle = <&ext_rgmii_phy>; + phy-mode = "rgmii-id"; + status = "okay"; +}; + +&external_mdio { + ext_rgmii_phy: ethernet-phy@7 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <7>; + }; +}; + +&mmc1 { + vmmc-supply = <®_vcc3v3>; + vqmmc-supply = <®_vcc3v3>; + mmc-pwrseq = <&wifi_pwrseq>; + bus-width = <4>; + non-removable; + status = "okay"; + + wifi: wifi@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + interrupt-parent = <&pio>; + interrupts = <6 10 IRQ_TYPE_LEVEL_LOW>; /* PG10 / EINT10 */ + interrupt-names = "host-wake"; + }; +}; + +&mmc2 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_8bit_pins>; + vmmc-supply = <®_vcc3v3>; + vqmmc-supply = <®_vcc3v3>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&ohci1 { + status = "okay"; +}; + +&ohci2 { + status = "okay"; +}; + +®_usb0_vbus { + gpio = <&r_pio 0 2 GPIO_ACTIVE_HIGH>; /* PL2 */ + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&uart3_pins>, <&uart3_rts_cts_pins>; + uart-has-rtscts; + status = "okay"; + + bluetooth { + compatible = "brcm,bcm43438-bt"; + clocks = <&rtc 1>; + clock-names = "lpo"; + vbat-supply = <®_vcc3v3>; + vddio-supply = <®_vcc3v3>; + device-wakeup-gpios = <&pio 0 8 GPIO_ACTIVE_HIGH>; /* PA8 */ + host-wakeup-gpios = <&pio 0 7 GPIO_ACTIVE_HIGH>; /* PA7 */ + shutdown-gpios = <&pio 6 13 GPIO_ACTIVE_HIGH>; /* PG13 */ + }; +}; + +&usb_otg { + status = "okay"; + dr_mode = "otg"; +}; + +&usbphy { + usb0_id_det-gpios = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */ + usb0_vbus-supply = <®_usb0_vbus>; + status = "okay"; +}; From 6cbf13e3114c8477021295d338f800282ac0653a Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Wed, 4 Nov 2020 14:37:58 +0100 Subject: [PATCH 201/799] ARM: dts: ux500: Rename DSI controller nodes Rename the DSI controller nodes from "dsi-controller@" to "dsi@" so they match the naming convention in the YAML schema for DSI controllers. Signed-off-by: Linus Walleij Link: https://lore.kernel.org/r/20201104133758.1373298-1-linus.walleij@linaro.org Signed-off-by: Linus Walleij --- arch/arm/boot/dts/ste-ab8500.dtsi | 6 +++--- arch/arm/boot/dts/ste-ab8505.dtsi | 6 +++--- arch/arm/boot/dts/ste-dbx5x0.dtsi | 6 +++--- arch/arm/boot/dts/ste-href-stuib.dtsi | 2 +- arch/arm/boot/dts/ste-href-tvk1281618-r2.dtsi | 2 +- arch/arm/boot/dts/ste-href-tvk1281618-r3.dtsi | 2 +- arch/arm/boot/dts/ste-ux500-samsung-golden.dts | 2 +- arch/arm/boot/dts/ste-ux500-samsung-skomer.dts | 2 +- 8 files changed, 14 insertions(+), 14 deletions(-) diff --git a/arch/arm/boot/dts/ste-ab8500.dtsi b/arch/arm/boot/dts/ste-ab8500.dtsi index aab5719cc1a9..4c16736ea789 100644 --- a/arch/arm/boot/dts/ste-ab8500.dtsi +++ b/arch/arm/boot/dts/ste-ab8500.dtsi @@ -326,13 +326,13 @@ mcde@a0350000 { vana-supply = <&ab8500_ldo_ana_reg>; - dsi-controller@a0351000 { + dsi@a0351000 { vana-supply = <&ab8500_ldo_ana_reg>; }; - dsi-controller@a0352000 { + dsi@a0352000 { vana-supply = <&ab8500_ldo_ana_reg>; }; - dsi-controller@a0353000 { + dsi@a0353000 { vana-supply = <&ab8500_ldo_ana_reg>; }; }; diff --git a/arch/arm/boot/dts/ste-ab8505.dtsi b/arch/arm/boot/dts/ste-ab8505.dtsi index 67bc69e67b33..c72aa250bf6f 100644 --- a/arch/arm/boot/dts/ste-ab8505.dtsi +++ b/arch/arm/boot/dts/ste-ab8505.dtsi @@ -261,13 +261,13 @@ mcde@a0350000 { vana-supply = <&ab8500_ldo_ana_reg>; - dsi-controller@a0351000 { + dsi@a0351000 { vana-supply = <&ab8500_ldo_ana_reg>; }; - dsi-controller@a0352000 { + dsi@a0352000 { vana-supply = <&ab8500_ldo_ana_reg>; }; - dsi-controller@a0353000 { + dsi@a0353000 { vana-supply = <&ab8500_ldo_ana_reg>; }; }; diff --git a/arch/arm/boot/dts/ste-dbx5x0.dtsi b/arch/arm/boot/dts/ste-dbx5x0.dtsi index 05fd544b06c1..404b9c4a5fee 100644 --- a/arch/arm/boot/dts/ste-dbx5x0.dtsi +++ b/arch/arm/boot/dts/ste-dbx5x0.dtsi @@ -1097,7 +1097,7 @@ ranges; status = "disabled"; - dsi0: dsi-controller@a0351000 { + dsi0: dsi@a0351000 { compatible = "ste,mcde-dsi"; reg = <0xa0351000 0x1000>; clocks = <&prcmu_clk PRCMU_DSI0CLK>, <&prcmu_clk PRCMU_DSI0ESCCLK>; @@ -1105,7 +1105,7 @@ #address-cells = <1>; #size-cells = <0>; }; - dsi1: dsi-controller@a0352000 { + dsi1: dsi@a0352000 { compatible = "ste,mcde-dsi"; reg = <0xa0352000 0x1000>; clocks = <&prcmu_clk PRCMU_DSI1CLK>, <&prcmu_clk PRCMU_DSI1ESCCLK>; @@ -1113,7 +1113,7 @@ #address-cells = <1>; #size-cells = <0>; }; - dsi2: dsi-controller@a0353000 { + dsi2: dsi@a0353000 { compatible = "ste,mcde-dsi"; reg = <0xa0353000 0x1000>; /* This DSI port only has the Low Power / Energy Save clock */ diff --git a/arch/arm/boot/dts/ste-href-stuib.dtsi b/arch/arm/boot/dts/ste-href-stuib.dtsi index b8fd8f18ba16..e32d0c36feb8 100644 --- a/arch/arm/boot/dts/ste-href-stuib.dtsi +++ b/arch/arm/boot/dts/ste-href-stuib.dtsi @@ -199,7 +199,7 @@ mcde@a0350000 { status = "okay"; - dsi-controller@a0351000 { + dsi@a0351000 { panel { compatible = "samsung,s6d16d0"; reg = <0>; diff --git a/arch/arm/boot/dts/ste-href-tvk1281618-r2.dtsi b/arch/arm/boot/dts/ste-href-tvk1281618-r2.dtsi index de82b9db956f..e024520f4d47 100644 --- a/arch/arm/boot/dts/ste-href-tvk1281618-r2.dtsi +++ b/arch/arm/boot/dts/ste-href-tvk1281618-r2.dtsi @@ -66,7 +66,7 @@ mcde@a0350000 { status = "okay"; - dsi-controller@a0351000 { + dsi@a0351000 { panel { compatible = "samsung,s6d16d0"; reg = <0>; diff --git a/arch/arm/boot/dts/ste-href-tvk1281618-r3.dtsi b/arch/arm/boot/dts/ste-href-tvk1281618-r3.dtsi index 9f285c7cf914..cb3677f0a1cb 100644 --- a/arch/arm/boot/dts/ste-href-tvk1281618-r3.dtsi +++ b/arch/arm/boot/dts/ste-href-tvk1281618-r3.dtsi @@ -45,7 +45,7 @@ mcde@a0350000 { status = "okay"; - dsi-controller@a0351000 { + dsi@a0351000 { panel { compatible = "sony,acx424akp"; reg = <0>; diff --git a/arch/arm/boot/dts/ste-ux500-samsung-golden.dts b/arch/arm/boot/dts/ste-ux500-samsung-golden.dts index a1093cb37dc7..939360c05713 100644 --- a/arch/arm/boot/dts/ste-ux500-samsung-golden.dts +++ b/arch/arm/boot/dts/ste-ux500-samsung-golden.dts @@ -322,7 +322,7 @@ pinctrl-names = "default"; pinctrl-0 = <&dsi_default_mode>; - dsi-controller@a0351000 { + dsi@a0351000 { panel@0 { compatible = "samsung,s6e63m0"; reg = <0>; diff --git a/arch/arm/boot/dts/ste-ux500-samsung-skomer.dts b/arch/arm/boot/dts/ste-ux500-samsung-skomer.dts index 27722c42b61c..cbae23a1e8b6 100644 --- a/arch/arm/boot/dts/ste-ux500-samsung-skomer.dts +++ b/arch/arm/boot/dts/ste-ux500-samsung-skomer.dts @@ -393,7 +393,7 @@ pinctrl-names = "default"; pinctrl-0 = <&dsi_default_mode>; - dsi-controller@a0351000 { + dsi@a0351000 { panel { /* NT35510-based Hydis HVA40WV1 */ compatible = "hydis,hva40wv1", "novatek,nt35510"; From 2024b130b0c8b09d6086c495910faddbd9c6be02 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C5=81ukasz=20Stelmach?= Date: Tue, 3 Nov 2020 16:15:35 +0100 Subject: [PATCH 202/799] ARM: dts: exynos: Add Ethernet to Artik 5 board MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add node for ax88796c ethernet chip. Signed-off-by: Łukasz Stelmach Link: https://lore.kernel.org/r/20201103151536.26472-5-l.stelmach@samsung.com Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos3250-artik5-eval.dts | 29 ++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/arch/arm/boot/dts/exynos3250-artik5-eval.dts b/arch/arm/boot/dts/exynos3250-artik5-eval.dts index 20446a846a98..5461949d833e 100644 --- a/arch/arm/boot/dts/exynos3250-artik5-eval.dts +++ b/arch/arm/boot/dts/exynos3250-artik5-eval.dts @@ -37,3 +37,32 @@ &serial_2 { status = "okay"; }; + +&spi_0 { + status = "okay"; + cs-gpios = <&gpx3 4 GPIO_ACTIVE_LOW>, <0>; + + assigned-clocks = <&cmu CLK_MOUT_MPLL>, <&cmu CLK_DIV_MPLL_PRE>, + <&cmu CLK_MOUT_SPI0>, <&cmu CLK_DIV_SPI0>, + <&cmu CLK_DIV_SPI0_PRE>, <&cmu CLK_SCLK_SPI0>; + assigned-clock-parents = <&cmu CLK_FOUT_MPLL>, /* for: CLK_MOUT_MPLL */ + <&cmu CLK_MOUT_MPLL>, /* for: CLK_DIV_MPLL_PRE */ + <&cmu CLK_DIV_MPLL_PRE>, /* for: CLK_MOUT_SPI0 */ + <&cmu CLK_MOUT_SPI0>, /* for: CLK_DIV_SPI0 */ + <&cmu CLK_DIV_SPI0>, /* for: CLK_DIV_SPI0_PRE */ + <&cmu CLK_DIV_SPI0_PRE>; /* for: CLK_SCLK_SPI0 */ + + ethernet@0 { + compatible = "asix,ax88796c"; + reg = <0x0>; + local-mac-address = [00 00 00 00 00 00]; /* Filled in by a boot-loader */ + interrupt-parent = <&gpx2>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + spi-max-frequency = <40000000>; + reset-gpios = <&gpe0 2 GPIO_ACTIVE_LOW>; + + controller-data { + samsung,spi-feedback-delay = <2>; + }; + }; +}; From dfe21dcabac001e0a102c1aa3bbaee00041e9e0f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C5=81ukasz=20Stelmach?= Date: Tue, 3 Nov 2020 16:15:36 +0100 Subject: [PATCH 203/799] ARM: defconfig: Enable ax88796c driver for Exynos boards MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Enable ax88796c driver for the Ethernet chip on Exynos3250-based ARTIK5 boards in exynos and multi_v7 defconfigs. Signed-off-by: Łukasz Stelmach Link: https://lore.kernel.org/r/20201103151536.26472-6-l.stelmach@samsung.com Signed-off-by: Krzysztof Kozlowski --- arch/arm/configs/exynos_defconfig | 2 ++ arch/arm/configs/multi_v7_defconfig | 2 ++ 2 files changed, 4 insertions(+) diff --git a/arch/arm/configs/exynos_defconfig b/arch/arm/configs/exynos_defconfig index 8c1fd6408108..f0cef76a3ab9 100644 --- a/arch/arm/configs/exynos_defconfig +++ b/arch/arm/configs/exynos_defconfig @@ -107,6 +107,8 @@ CONFIG_MD=y CONFIG_BLK_DEV_DM=y CONFIG_DM_CRYPT=m CONFIG_NETDEVICES=y +CONFIG_NET_VENDOR_ASIX=y +CONFIG_SPI_AX88796C=y CONFIG_SMSC911X=y CONFIG_USB_RTL8150=m CONFIG_USB_RTL8152=y diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig index 138a9e8fe35d..6ab0945fb27c 100644 --- a/arch/arm/configs/multi_v7_defconfig +++ b/arch/arm/configs/multi_v7_defconfig @@ -243,6 +243,8 @@ CONFIG_SATA_HIGHBANK=y CONFIG_SATA_MV=y CONFIG_SATA_RCAR=y CONFIG_NETDEVICES=y +CONFIG_NET_VENDOR_ASIX=y +CONFIG_SPI_AX88796C=m CONFIG_VIRTIO_NET=y CONFIG_B53_SPI_DRIVER=m CONFIG_B53_MDIO_DRIVER=m From 62dbf80fc581a8eed7288ed7aca24446054eb616 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Mon, 2 Nov 2020 16:06:58 +0100 Subject: [PATCH 204/799] dt-bindings: arm: rockchip: Add Kobol Helios64 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Document the new board by Kobol introduced recently in rockchip/rk3399-kobol-helios64.dts. Signed-off-by: Uwe Kleine-König Acked-by: Rob Herring Link: https://lore.kernel.org/r/20201102150658.167161-1-uwe@kleine-koenig.org Signed-off-by: Heiko Stuebner --- Documentation/devicetree/bindings/arm/rockchip.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml index 65b4cc2c63f7..70fa4d98db56 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml @@ -381,6 +381,11 @@ properties: - khadas,edge-v - const: rockchip,rk3399 + - description: Kobol Helios64 + items: + - const: kobol,helios64 + - const: rockchip,rk3399 + - description: Mecer Xtreme Mini S6 items: - const: mecer,xms6 From c20e6dd9a953d62f14399dabf457dce61dd5611f Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Sat, 4 Jul 2020 00:14:13 +0200 Subject: [PATCH 205/799] arm64: dts: rockchip: add adc joystick to Odroid Go Advance Add the now usable adc-joystick node that describes the analog joystick connected to two saradc channels from the rk3326 soc. Signed-off-by: Heiko Stuebner Link: https://lore.kernel.org/r/20200703221413.269800-1-heiko@sntech.de --- .../boot/dts/rockchip/rk3326-odroid-go2.dts | 24 +++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts b/arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts index 35bd6b904b9c..e21372b8e904 100644 --- a/arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts +++ b/arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts @@ -18,6 +18,30 @@ stdout-path = "serial2:115200n8"; }; + adc-joystick { + compatible = "adc-joystick"; + io-channels = <&saradc 1>, + <&saradc 2>; + #address-cells = <1>; + #size-cells = <0>; + + axis@0 { + reg = <0>; + abs-flat = <10>; + abs-fuzz = <10>; + abs-range = <172 772>; + linux,code = ; + }; + + axis@1 { + reg = <1>; + abs-flat = <10>; + abs-fuzz = <10>; + abs-range = <278 815>; + linux,code = ; + }; + }; + backlight: backlight { compatible = "pwm-backlight"; power-supply = <&vcc_bl>; From 73bc7510ea0dafb4ff1ae6808759627a8ec51f5a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pawe=C5=82=20Chmiel?= Date: Sat, 7 Nov 2020 14:39:25 +0100 Subject: [PATCH 206/799] arm64: dts: exynos: Include common syscon restart/poweroff for Exynos7 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Exynos7 uses the same syscon reboot and poweroff nodes as other Exynos SoCs, so instead of duplicating code we can just include common dtsi file, which already contains definitions of them. After this change, poweroff node will be also available, previously this dts file did contain only reboot node. Fixes: fb026cb65247 ("arm64: dts: Add reboot node for exynos7") Fixes: b9024cbc937d ("arm64: dts: Add initial device tree support for exynos7") Signed-off-by: Paweł Chmiel Link: https://lore.kernel.org/r/20201107133926.37187-1-pawel.mikolaj.chmiel@gmail.com Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/exynos/exynos7.dtsi | 8 +------- 1 file changed, 1 insertion(+), 7 deletions(-) diff --git a/arch/arm64/boot/dts/exynos/exynos7.dtsi b/arch/arm64/boot/dts/exynos/exynos7.dtsi index 48cd3a04fd07..fa3ad6bcf562 100644 --- a/arch/arm64/boot/dts/exynos/exynos7.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos7.dtsi @@ -481,13 +481,6 @@ pmu_system_controller: system-controller@105c0000 { compatible = "samsung,exynos7-pmu", "syscon"; reg = <0x105c0000 0x5000>; - - reboot: syscon-reboot { - compatible = "syscon-reboot"; - regmap = <&pmu_system_controller>; - offset = <0x0400>; - mask = <0x1>; - }; }; rtc: rtc@10590000 { @@ -687,3 +680,4 @@ }; #include "exynos7-pinctrl.dtsi" +#include "arm/exynos-syscon-restart.dtsi" From e1e47fbca668507a81bb388fcae044b89d112ecc Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pawe=C5=82=20Chmiel?= Date: Sat, 7 Nov 2020 14:39:26 +0100 Subject: [PATCH 207/799] arm64: dts: exynos: Correct psci compatible used on Exynos7 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit It's not possible to reboot or poweroff Exynos7420 using PSCI. Instead we need to use syscon reboot/poweroff drivers, like it's done for other Exynos SoCs. This was confirmed by checking vendor source and testing it on Samsung Galaxy S6 device based on this SoC. To be able to use custom restart/poweroff handlers instead of PSCI functions, we need to correct psci compatible. This also requires us to provide function ids for CPU_ON and CPU_OFF. Fixes: fb026cb65247 ("arm64: dts: Add reboot node for exynos7") Fixes: b9024cbc937d ("arm64: dts: Add initial device tree support for exynos7") Signed-off-by: Paweł Chmiel Link: https://lore.kernel.org/r/20201107133926.37187-2-pawel.mikolaj.chmiel@gmail.com Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/exynos/exynos7.dtsi | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/exynos/exynos7.dtsi b/arch/arm64/boot/dts/exynos/exynos7.dtsi index fa3ad6bcf562..661f9c1027e8 100644 --- a/arch/arm64/boot/dts/exynos/exynos7.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos7.dtsi @@ -79,8 +79,10 @@ }; psci { - compatible = "arm,psci-0.2"; + compatible = "arm,psci"; method = "smc"; + cpu_off = <0x84000002>; + cpu_on = <0xC4000003>; }; soc: soc@0 { From f36296e4ddfc003932c435cb16ca26fc87e43001 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Tue, 29 Sep 2020 14:02:11 +0530 Subject: [PATCH 208/799] dt-bindings: arm: rockchip: Add Engicam PX30.Core EDIMM2.2 Starter Kit PX30.Core is an EDIMM SOM based on Rockchip PX30 from Engicam. EDIMM2.2 Starter Kit is an EDIMM 2.2 Form Factor Capacitive Evaluation Board from Engicam. PX30.Core needs to mount on top of this Evaluation board for creating complete PX30.Core EDIMM2.2 Starter Kit. Add bindings for it. Signed-off-by: Jagan Teki Acked-by: Rob Herring Link: https://lore.kernel.org/r/20200929083217.25406-2-jagan@amarulasolutions.com Signed-off-by: Heiko Stuebner --- Documentation/devicetree/bindings/arm/rockchip.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml index 70fa4d98db56..9c5f09147d36 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml @@ -70,6 +70,12 @@ properties: - const: elgin,rv1108-r1 - const: rockchip,rv1108 + - description: Engicam PX30.Core EDIMM2.2 Starter Kit + items: + - const: engicam,px30-core-edimm2.2 + - const: engicam,px30-core + - const: rockchip,px30 + - description: Firefly Firefly-RK3288 items: - enum: From 7a180f56e01443be526061bd8ec8cf6e2c4f988d Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Tue, 29 Sep 2020 14:02:12 +0530 Subject: [PATCH 209/799] arm64: dts: rockchip: Add Engicam EDIMM2.2 Starter Kit Engicam EDIMM2.2 Starter Kit is an EDIMM 2.2 Form Factor Capacitive Evaluation Board. Genaral features: - LCD 7" C.Touch - microSD slot - Ethernet 1Gb - Wifi/BT - 2x LVDS Full HD interfaces - 3x USB 2.0 - 1x USB 3.0 - HDMI Out - Mini PCIe - MIPI CSI - 2x CAN - Audio Out SOM's like PX30.Core needs to mount on top of this Evaluation board for creating complete PX30.Core EDIMM2.2 Starter Kit. Add support for it. Signed-off-by: Jagan Teki Signed-off-by: Michael Trimarchi Link: https://lore.kernel.org/r/20200929083217.25406-3-jagan@amarulasolutions.com Signed-off-by: Heiko Stuebner --- .../dts/rockchip/px30-engicam-common.dtsi | 39 +++++++++++++++++++ .../dts/rockchip/px30-engicam-edimm2.2.dtsi | 7 ++++ 2 files changed, 46 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/px30-engicam-common.dtsi create mode 100644 arch/arm64/boot/dts/rockchip/px30-engicam-edimm2.2.dtsi diff --git a/arch/arm64/boot/dts/rockchip/px30-engicam-common.dtsi b/arch/arm64/boot/dts/rockchip/px30-engicam-common.dtsi new file mode 100644 index 000000000000..bd5bde989e8d --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/px30-engicam-common.dtsi @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Engicam srl + * Copyright (c) 2020 Amarula Solutions + * Copyright (c) 2020 Amarula Solutions(India) + */ + +/ { + vcc5v0_sys: vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; /* +5V */ + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; +}; + +&gmac { + clock_in_out = "output"; + phy-supply = <&vcc_3v3>; /* +3V3_SOM */ + snps,reset-active-low; + snps,reset-delays-us = <0 50000 50000>; + snps,reset-gpio = <&gpio2 RK_PB5 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&sdmmc { + cap-sd-highspeed; + card-detect-delay = <800>; + vmmc-supply = <&vcc_3v3>; /* +3V3_SOM */ + vqmmc-supply = <&vcc_3v3>; + status = "okay"; +}; + +&uart2 { + pinctrl-0 = <&uart2m1_xfer>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/rockchip/px30-engicam-edimm2.2.dtsi b/arch/arm64/boot/dts/rockchip/px30-engicam-edimm2.2.dtsi new file mode 100644 index 000000000000..cb00988953e9 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/px30-engicam-edimm2.2.dtsi @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Engicam srl + * Copyright (c) 2020 Amarula Solutions(India) + */ + +#include "px30-engicam-common.dtsi" From d92a7c331f53ccf6da4e0cb6b49470444cb150ce Mon Sep 17 00:00:00 2001 From: Michael Trimarchi Date: Tue, 29 Sep 2020 14:02:13 +0530 Subject: [PATCH 210/799] arm64: dts: rockchip: Add Engicam PX30.Core SOM PX30.Core is an EDIMM SOM based on Rockchip PX30 from Engicam. General features: - Rockchip PX30 - Up to 2GB DDR4 - eMMC 4 GB expandible - rest of PX30 features PX30.Core needs to mount on top of Engicam baseboards for creating complete platform boards. Possible baseboards are, - EDIMM2.2 - C.TOUCH 2.0 Add support for it. Signed-off-by: Jagan Teki Signed-off-by: Michael Trimarchi Link: https://lore.kernel.org/r/20200929083217.25406-4-jagan@amarulasolutions.com Signed-off-by: Heiko Stuebner --- .../dts/rockchip/px30-engicam-px30-core.dtsi | 232 ++++++++++++++++++ 1 file changed, 232 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/px30-engicam-px30-core.dtsi diff --git a/arch/arm64/boot/dts/rockchip/px30-engicam-px30-core.dtsi b/arch/arm64/boot/dts/rockchip/px30-engicam-px30-core.dtsi new file mode 100644 index 000000000000..db22f776c68f --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/px30-engicam-px30-core.dtsi @@ -0,0 +1,232 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd + * Copyright (c) 2020 Engicam srl + * Copyright (c) 2020 Amarula Solutons + * Copyright (c) 2020 Amarula Solutons(India) + */ + +#include +#include + +/ { + compatible = "engicam,px30-core", "rockchip,px30"; +}; + +&cpu0 { + cpu-supply = <&vdd_arm>; +}; + +&cpu1 { + cpu-supply = <&vdd_arm>; +}; + +&cpu2 { + cpu-supply = <&vdd_arm>; +}; + +&cpu3 { + cpu-supply = <&vdd_arm>; +}; + +&emmc { + cap-mmc-highspeed; + mmc-hs200-1_8v; + non-removable; + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + rk809: pmic@20 { + compatible = "rockchip,rk809"; + reg = <0x20>; + interrupt-parent = <&gpio0>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int>; + rockchip,system-power-controller; + wakeup-source; + #clock-cells = <1>; + clock-output-names = "rk808-clkout1", "rk808-clkout2"; + + vcc1-supply = <&vcc5v0_sys>; + vcc2-supply = <&vcc5v0_sys>; + vcc3-supply = <&vcc5v0_sys>; + vcc4-supply = <&vcc5v0_sys>; + vcc5-supply = <&vcc3v3_sys>; + vcc6-supply = <&vcc3v3_sys>; + vcc7-supply = <&vcc3v3_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc5v0_sys>; + + regulators { + vdd_log: DCDC_REG1 { + regulator-name = "vdd_log"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <950000>; + }; + }; + + vdd_arm: DCDC_REG2 { + regulator-name = "vdd_arm"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <950000>; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_3v3: DCDC_REG4 { + regulator-name = "vcc_3v3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc3v3_sys: DCDC_REG5 { + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc_1v0: LDO_REG1 { + regulator-name = "vcc_1v0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vcc_1v8: LDO_REG2 { + regulator-name = "vcc_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd_1v0: LDO_REG3 { + regulator-name = "vdd_1v0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vcc3v0_pmu: LDO_REG4 { + regulator-name = "vcc3v0_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + + }; + }; + + vccio_sd: LDO_REG5 { + regulator-name = "vccio_sd"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc5v0_host: SWITCH_REG2 { + regulator-name = "vcc5v0_host"; + regulator-always-on; + regulator-boot-on; + }; + }; + }; +}; + +&io_domains { + vccio1-supply = <&vcc_3v3>; + vccio2-supply = <&vcc_3v3>; + vccio3-supply = <&vcc_3v3>; + vccio4-supply = <&vcc_3v3>; + vccio5-supply = <&vcc_3v3>; + vccio6-supply = <&vcc_1v8>; + status = "okay"; +}; + +&pinctrl { + pmic { + pmic_int: pmic_int { + rockchip,pins = <0 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&pmu_io_domains { + pmuio1-supply = <&vcc_3v3>; + pmuio2-supply = <&vcc_3v3>; + status = "okay"; +}; + +&tsadc { + rockchip,hw-tshut-mode = <1>; + rockchip,hw-tshut-polarity = <1>; + status = "okay"; +}; From 0935d7e9b1b26230e01dc5f0ed8d2af3771ced57 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Tue, 29 Sep 2020 14:02:14 +0530 Subject: [PATCH 211/799] arm64: dts: rockchip: Add Engicam PX30.Core EDIMM2.2 Starter Kit PX30.Core is an EDIMM SOM based on Rockchip PX30 from Engicam. EDIMM2.2 Starter Kit is an EDIMM 2.2 Form Factor Capacitive Evaluation Board from Engicam. PX30.Core needs to mount on top of this Evaluation board for creating complete PX30.Core EDIMM2.2 Starter Kit. Add support for it. Signed-off-by: Jagan Teki Link: https://lore.kernel.org/r/20200929083217.25406-5-jagan@amarulasolutions.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/Makefile | 1 + .../px30-engicam-px30-core-edimm2.2.dts | 21 +++++++++++++++++++ 2 files changed, 22 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/px30-engicam-px30-core-edimm2.2.dts diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile index 28b26a874313..abf9dc621314 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -1,5 +1,6 @@ # SPDX-License-Identifier: GPL-2.0 dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-evb.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-engicam-px30-core-edimm2.2.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3308-evb.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3308-roc-cc.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3318-a95x-z2.dtb diff --git a/arch/arm64/boot/dts/rockchip/px30-engicam-px30-core-edimm2.2.dts b/arch/arm64/boot/dts/rockchip/px30-engicam-px30-core-edimm2.2.dts new file mode 100644 index 000000000000..e54d1e480daa --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/px30-engicam-px30-core-edimm2.2.dts @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd + * Copyright (c) 2020 Engicam srl + * Copyright (c) 2020 Amarula Solutions(India) + */ + +/dts-v1/; +#include "px30.dtsi" +#include "px30-engicam-edimm2.2.dtsi" +#include "px30-engicam-px30-core.dtsi" + +/ { + model = "Engicam PX30.Core EDIMM2.2 Starter Kit"; + compatible = "engicam,px30-core-edimm2.2", "engicam,px30-core", + "rockchip,px30"; + + chosen { + stdout-path = "serial2:115200n8"; + }; +}; From 5fccec0cf423aaf90c9c0125ef5af56c9455ba64 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Tue, 29 Sep 2020 14:02:15 +0530 Subject: [PATCH 212/799] dt-bindings: arm: rockchip: Add Engicam PX30.Core C.TOUCH 2.0 PX30.Core is an EDIMM SOM based on Rockchip PX30 from Engicam. C.TOUCH 2.0 is a general purpose carrier board with capacitive touch interface support. PX30.Core needs to mount on top of this Carrier board for creating complete PX30.Core C.TOUCH 2.0 board. Add bindings for it. Signed-off-by: Jagan Teki Acked-by: Rob Herring Link: https://lore.kernel.org/r/20200929083217.25406-6-jagan@amarulasolutions.com Signed-off-by: Heiko Stuebner --- Documentation/devicetree/bindings/arm/rockchip.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml index 9c5f09147d36..798d83d04392 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml @@ -70,6 +70,12 @@ properties: - const: elgin,rv1108-r1 - const: rockchip,rv1108 + - description: Engicam PX30.Core C.TOUCH 2.0 + items: + - const: engicam,px30-core-ctouch2 + - const: engicam,px30-core + - const: rockchip,px30 + - description: Engicam PX30.Core EDIMM2.2 Starter Kit items: - const: engicam,px30-core-edimm2.2 From 746c750a8bc4994638d014834389205c3e3bcc14 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Tue, 29 Sep 2020 14:02:16 +0530 Subject: [PATCH 213/799] arm64: dts: rockchip: Add Engicam C.TOUCH 2.0 Engicam C.TOUCH 2.0 is an EDIMM compliant general purpose carrier board with capacitive touch interface. Genaral features: - TFT 10.1" industrial, 1280x800 LVDS display - Ethernet 10/100 - Wifi/BT - USB Type A/OTG - Audio Out - CAN - LVDS panel connector SOM's like PX30.Core needs to mount on top of this Carrier board for creating complete PX30.Core C.TOUCH 2.0 board. Add support for it. Signed-off-by: Jagan Teki Signed-off-by: Michael Trimarchi Link: https://lore.kernel.org/r/20200929083217.25406-7-jagan@amarulasolutions.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/px30-engicam-ctouch2.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/px30-engicam-ctouch2.dtsi diff --git a/arch/arm64/boot/dts/rockchip/px30-engicam-ctouch2.dtsi b/arch/arm64/boot/dts/rockchip/px30-engicam-ctouch2.dtsi new file mode 100644 index 000000000000..58425b1e559f --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/px30-engicam-ctouch2.dtsi @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Engicam srl + * Copyright (c) 2020 Amarula Solutions + * Copyright (c) 2020 Amarula Solutions(India) + */ + +#include "px30-engicam-common.dtsi" From e786f756d52707f3c36ca0efe949407a8b978493 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Tue, 29 Sep 2020 14:02:17 +0530 Subject: [PATCH 214/799] arm64: dts: rockchip: Add Engicam PX30.Core C.TOUCH 2.0 PX30.Core is an EDIMM SOM based on Rockchip PX30 from Engicam. C.TOUCH 2.0 is a general purpose carrier board with capacitive touch interface support. PX30.Core needs to mount on top of this Carrier board for creating complete PX30.Core C.TOUCH 2.0 board. Add support for it. Signed-off-by: Jagan Teki Signed-off-by: Michael Trimarchi Link: https://lore.kernel.org/r/20200929083217.25406-8-jagan@amarulasolutions.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/Makefile | 1 + .../px30-engicam-px30-core-ctouch2.dts | 22 +++++++++++++++++++ 2 files changed, 23 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/px30-engicam-px30-core-ctouch2.dts diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile index abf9dc621314..5a53979b7057 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -1,5 +1,6 @@ # SPDX-License-Identifier: GPL-2.0 dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-evb.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-engicam-px30-core-ctouch2.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-engicam-px30-core-edimm2.2.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3308-evb.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3308-roc-cc.dtb diff --git a/arch/arm64/boot/dts/rockchip/px30-engicam-px30-core-ctouch2.dts b/arch/arm64/boot/dts/rockchip/px30-engicam-px30-core-ctouch2.dts new file mode 100644 index 000000000000..5a0ecb8faecf --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/px30-engicam-px30-core-ctouch2.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd + * Copyright (c) 2020 Engicam srl + * Copyright (c) 2020 Amarula Solutions + * Copyright (c) 2020 Amarula Solutions(India) + */ + +/dts-v1/; +#include "px30.dtsi" +#include "px30-engicam-ctouch2.dtsi" +#include "px30-engicam-px30-core.dtsi" + +/ { + model = "Engicam PX30.Core C.TOUCH 2.0"; + compatible = "engicam,px30-core-ctouch2", "engicam,px30-core", + "rockchip,px30"; + + chosen { + stdout-path = "serial2:115200n8"; + }; +}; From c5f883d1a6f3f061eb5d1acbbe2f3cbbe985f6a3 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 3 Nov 2020 09:41:36 +0100 Subject: [PATCH 215/799] ARM: shmobile: defconfig: Refresh for v5.10-rc1 Refresh the defconfig for Renesas ARM systems: - Reorder SoC-specific config options (cfr. commit 6d5aded8d57fc032 ("soc: renesas: Sort driver description title")). Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20201103084136.1378875-1-geert+renesas@glider.be --- arch/arm/configs/shmobile_defconfig | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/arch/arm/configs/shmobile_defconfig b/arch/arm/configs/shmobile_defconfig index 4a161b3c35b9..01a6ebdf033a 100644 --- a/arch/arm/configs/shmobile_defconfig +++ b/arch/arm/configs/shmobile_defconfig @@ -179,22 +179,22 @@ CONFIG_STAGING=y CONFIG_STAGING_BOARD=y # CONFIG_IOMMU_SUPPORT is not set CONFIG_ARCH_EMEV2=y +CONFIG_ARCH_R8A7794=y +CONFIG_ARCH_R8A7779=y +CONFIG_ARCH_R8A7790=y +CONFIG_ARCH_R8A7778=y +CONFIG_ARCH_R8A7793=y +CONFIG_ARCH_R8A7791=y +CONFIG_ARCH_R8A7792=y +CONFIG_ARCH_R8A7740=y +CONFIG_ARCH_R8A73A4=y CONFIG_ARCH_R7S72100=y CONFIG_ARCH_R7S9210=y -CONFIG_ARCH_R8A73A4=y -CONFIG_ARCH_R8A7740=y +CONFIG_ARCH_R8A77470=y +CONFIG_ARCH_R8A7745=y CONFIG_ARCH_R8A7742=y CONFIG_ARCH_R8A7743=y CONFIG_ARCH_R8A7744=y -CONFIG_ARCH_R8A7745=y -CONFIG_ARCH_R8A77470=y -CONFIG_ARCH_R8A7778=y -CONFIG_ARCH_R8A7779=y -CONFIG_ARCH_R8A7790=y -CONFIG_ARCH_R8A7791=y -CONFIG_ARCH_R8A7792=y -CONFIG_ARCH_R8A7793=y -CONFIG_ARCH_R8A7794=y CONFIG_ARCH_R9A06G032=y CONFIG_ARCH_SH73A0=y CONFIG_IIO=y From 616fde2dd60f9f956dc77ed7e284129de6dc97d2 Mon Sep 17 00:00:00 2001 From: Ionut-robert Aron Date: Mon, 9 Nov 2020 12:46:34 +0200 Subject: [PATCH 216/799] dt-bindings: misc: convert fsl,dpaa2-console from txt to YAML Convert fsl,dpaa2-console to YAML in order to automate the verification process of dts files. Signed-off-by: Ionut-robert Aron Signed-off-by: Laurentiu Tudor Link: https://lore.kernel.org/r/20201109104635.21116-1-laurentiu.tudor@nxp.com Signed-off-by: Rob Herring --- .../bindings/misc/fsl,dpaa2-console.txt | 11 -------- .../bindings/misc/fsl,dpaa2-console.yaml | 25 +++++++++++++++++++ 2 files changed, 25 insertions(+), 11 deletions(-) delete mode 100644 Documentation/devicetree/bindings/misc/fsl,dpaa2-console.txt create mode 100644 Documentation/devicetree/bindings/misc/fsl,dpaa2-console.yaml diff --git a/Documentation/devicetree/bindings/misc/fsl,dpaa2-console.txt b/Documentation/devicetree/bindings/misc/fsl,dpaa2-console.txt deleted file mode 100644 index 1442ba5d2d98..000000000000 --- a/Documentation/devicetree/bindings/misc/fsl,dpaa2-console.txt +++ /dev/null @@ -1,11 +0,0 @@ -DPAA2 console support - -Required properties: - - - compatible - Value type: - Definition: Must be "fsl,dpaa2-console". - - reg - Value type: - Definition: A standard property. Specifies the region where the MCFBA - (MC firmware base address) register can be found. diff --git a/Documentation/devicetree/bindings/misc/fsl,dpaa2-console.yaml b/Documentation/devicetree/bindings/misc/fsl,dpaa2-console.yaml new file mode 100644 index 000000000000..271a3eafc054 --- /dev/null +++ b/Documentation/devicetree/bindings/misc/fsl,dpaa2-console.yaml @@ -0,0 +1,25 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +# Copyright 2020 NXP +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/misc/fsl,dpaa2-console.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: DPAA2 console support + +maintainers: + - Laurentiu Tudor + +properties: + compatible: + const: "fsl,dpaa2-console" + + reg: + description: A standard property. Specifies the region where the MCFBA + (MC firmware base address) register can be found. + +required: + - compatible + - reg + +additionalProperties: false From ba66a25536dd24b73d36e380c68593e95e4e06a8 Mon Sep 17 00:00:00 2001 From: Jerome Brunet Date: Tue, 20 Oct 2020 09:50:34 +0200 Subject: [PATCH 217/799] arm64: meson: ship only the necessary clock controllers There now the menu entries for the amlogic clock controllers. Do not select these when ARM64 is enabled so it possible to ship only the required. Signed-off-by: Jerome Brunet Reviewed-by: Neil Armstrong Acked-by: Kevin Hilman Signed-off-by: Kevin Hilman Link: https://lore.kernel.org/r/20201020075034.172825-1-jbrunet@baylibre.com --- arch/arm64/Kconfig.platforms | 3 --- 1 file changed, 3 deletions(-) diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms index 6f2494dd6d60..329e22c09cad 100644 --- a/arch/arm64/Kconfig.platforms +++ b/arch/arm64/Kconfig.platforms @@ -153,9 +153,6 @@ config ARCH_MESON bool "Amlogic Platforms" select PINCTRL select PINCTRL_MESON - select COMMON_CLK_GXBB - select COMMON_CLK_AXG - select COMMON_CLK_G12A select MESON_IRQ_GPIO help This enables support for the arm64 based Amlogic SoCs From f4d0fea16ad771f1f3c930251af90f8b33d9fa66 Mon Sep 17 00:00:00 2001 From: Yunus Bas Date: Thu, 29 Oct 2020 08:03:22 +0100 Subject: [PATCH 218/799] ARM: dts: imx6ul: segin: Add phyBOARD-Segin with eMMC phyCORE-i.MX6UL Add a PHYTEC phyBOARD-Segin full featured with phyCORE-i.MX 6UL with eMMC and following features: - i.MX 6UL - 512 MB RAM - eMMC - USB Host/OTG - 2x 100 Mbit/s Ethernet - RS232 - CAN Signed-off-by: Yunus Bas Signed-off-by: Stefan Riedmueller Signed-off-by: Shawn Guo --- arch/arm/boot/dts/Makefile | 1 + .../dts/imx6ul-phytec-segin-ff-rdk-emmc.dts | 93 +++++++++++++++++++ 2 files changed, 94 insertions(+) create mode 100644 arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk-emmc.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index ce66ffd5a1bb..654692919a27 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -622,6 +622,7 @@ dtb-$(CONFIG_SOC_IMX6UL) += \ imx6ul-pico-dwarf.dtb \ imx6ul-pico-hobbit.dtb \ imx6ul-pico-pi.dtb \ + imx6ul-phytec-segin-ff-rdk-emmc.dtb \ imx6ul-phytec-segin-ff-rdk-nand.dtb \ imx6ul-tx6ul-0010.dtb \ imx6ul-tx6ul-0011.dtb \ diff --git a/arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk-emmc.dts b/arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk-emmc.dts new file mode 100644 index 000000000000..4a25122e0da2 --- /dev/null +++ b/arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk-emmc.dts @@ -0,0 +1,93 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright (C) 2020 PHYTEC Messtechnik GmbH + * Author: Yunus Bas + */ + +/dts-v1/; +#include "imx6ul.dtsi" +#include "imx6ul-phytec-phycore-som.dtsi" +#include "imx6ul-phytec-segin.dtsi" +#include "imx6ul-phytec-segin-peb-eval-01.dtsi" + +/ { + model = "PHYTEC phyBOARD-Segin i.MX6 UltraLite Full Featured with eMMC"; + compatible = "phytec,imx6ul-pbacd10-emmc", "phytec,imx6ul-pbacd10", + "phytec,imx6ul-pcl063","fsl,imx6ul"; +}; + +&adc1 { + status = "okay"; +}; + +&can1 { + status = "okay"; +}; + +&ecspi3 { + status = "okay"; +}; + +ðphy1 { + status = "okay"; +}; + +ðphy2 { + status = "okay"; +}; + +&fec1 { + status = "okay"; +}; + +&fec2 { + status = "okay"; +}; + +&i2c_rtc { + status = "okay"; +}; + +®_can1_en { + status = "okay"; +}; + +®_sound_1v8 { + status = "okay"; +}; + +®_sound_3v3 { + status = "okay"; +}; + +&sai2 { + status = "okay"; +}; + +&sound { + status = "okay"; +}; + +&tlv320 { + status = "okay"; +}; + +&uart5 { + status = "okay"; +}; + +&usbotg1 { + status = "okay"; +}; + +&usbotg2 { + status = "okay"; +}; + +&usdhc1 { + status = "okay"; +}; + +&usdhc2 { + status = "okay"; +}; From 6d4e1ff5281996efe6a2b9bc58cdcdd446bb52a4 Mon Sep 17 00:00:00 2001 From: Stefan Riedmueller Date: Thu, 29 Oct 2020 08:03:23 +0100 Subject: [PATCH 219/799] ARM: dts: imx6ul: phytec: Add support for optional PEB-AV-02 LCD adapter The PHYTEC PEB-AV-02 adapter adds the capability to connect a parallel LCD display to the phyBOARD-Segin full featured, either with capacitive or resistive touch. Signed-off-by: Stefan Riedmueller Signed-off-by: Shawn Guo --- .../dts/imx6ul-phytec-segin-ff-rdk-emmc.dts | 1 + .../dts/imx6ul-phytec-segin-ff-rdk-nand.dts | 1 + .../dts/imx6ul-phytec-segin-peb-av-02.dtsi | 150 ++++++++++++++++++ arch/arm/boot/dts/imx6ul-phytec-segin.dtsi | 43 ----- .../dts/imx6ull-phytec-segin-ff-rdk-emmc.dts | 1 + .../dts/imx6ull-phytec-segin-ff-rdk-nand.dts | 1 + .../dts/imx6ull-phytec-segin-peb-av-02.dtsi | 26 +++ arch/arm/boot/dts/imx6ull-phytec-segin.dtsi | 7 - 8 files changed, 180 insertions(+), 50 deletions(-) create mode 100644 arch/arm/boot/dts/imx6ul-phytec-segin-peb-av-02.dtsi create mode 100644 arch/arm/boot/dts/imx6ull-phytec-segin-peb-av-02.dtsi diff --git a/arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk-emmc.dts b/arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk-emmc.dts index 4a25122e0da2..cfc744f8fcad 100644 --- a/arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk-emmc.dts +++ b/arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk-emmc.dts @@ -9,6 +9,7 @@ #include "imx6ul-phytec-phycore-som.dtsi" #include "imx6ul-phytec-segin.dtsi" #include "imx6ul-phytec-segin-peb-eval-01.dtsi" +#include "imx6ul-phytec-segin-peb-av-02.dtsi" / { model = "PHYTEC phyBOARD-Segin i.MX6 UltraLite Full Featured with eMMC"; diff --git a/arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk-nand.dts b/arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk-nand.dts index 699dfcbf9a60..bff98e676980 100644 --- a/arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk-nand.dts +++ b/arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk-nand.dts @@ -9,6 +9,7 @@ #include "imx6ul-phytec-phycore-som.dtsi" #include "imx6ul-phytec-segin.dtsi" #include "imx6ul-phytec-segin-peb-eval-01.dtsi" +#include "imx6ul-phytec-segin-peb-av-02.dtsi" / { model = "PHYTEC phyBOARD-Segin i.MX6 UltraLite Full Featured with NAND"; diff --git a/arch/arm/boot/dts/imx6ul-phytec-segin-peb-av-02.dtsi b/arch/arm/boot/dts/imx6ul-phytec-segin-peb-av-02.dtsi new file mode 100644 index 000000000000..b511c6dec427 --- /dev/null +++ b/arch/arm/boot/dts/imx6ul-phytec-segin-peb-av-02.dtsi @@ -0,0 +1,150 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright (C) 2016, 2020 PHYTEC Messtechnik + * Author: Christian Hemp + * Author: Stefan Riedmueller + */ + +/ { + backlight_lcd: backlight-lcd { + compatible = "pwm-backlight"; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <5>; + power-supply = <®_backlight_en>; + pwms = <&pwm3 0 5000000>; + status = "disabled"; + }; + + lcd_panel: lcd-panel { + compatible = "edt,etm0700g0edh6"; + backlight = <&backlight_lcd>; + status = "disabled"; + + port { + lcd_panel_in: endpoint { + remote-endpoint = <&lcdif_parallel_out>; + }; + }; + }; + + reg_backlight_en: regulator-backlight-en { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_backlight_en>; + regulator-name = "backlight-lcd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio1 18 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; + +&i2c1 { + edt_ft5406: touchscreen@38 { + compatible = "edt,edt-ft5406"; + reg = <0x38>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_edt_ft5406>; + interrupt-parent = <&gpio5>; + interrupts = <5 IRQ_TYPE_EDGE_FALLING>; + wakeup-source; + status = "disabled"; + }; + + stmpe: touchscreen@44 { + compatible = "st,stmpe811"; + reg = <0x44>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_stmpe>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&gpio5>; + status = "disabled"; + + stmpe_touchscreen { + compatible = "st,stmpe-ts"; + st,sample-time = <4>; + st,mod-12b = <1>; + st,ref-sel = <0>; + st,adc-freq = <1>; + st,ave-ctrl = <1>; + st,touch-det-delay = <2>; + st,settling = <2>; + st,fraction-z = <7>; + st,i-drive = <1>; + touchscreen-inverted-x = <1>; + touchscreen-inverted-y = <1>; + }; + }; +}; + +&lcdif { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcdif_dat>; + status = "disabled"; + + port { + lcdif_parallel_out: endpoint { + remote-endpoint = <&lcd_panel_in>; + }; + }; +}; + +&pwm3 { + #pwm-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3>; + status = "disabled"; +}; + +&iomuxc { + pinctrl_edt_ft5406: edtft5406grp { + fsl,pins = < + MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x1b0b0 + >; + }; + + pinctrl_backlight_en: bachlightengrp { + fsl,pins = < + MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x1b0b0 + >; + }; + + pinctrl_lcdif_dat: lcdifdatgrp { + fsl,pins = < + MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x59 + MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x59 + MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x59 + MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x59 + MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x59 + MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x59 + MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x59 + MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x59 + MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x59 + MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x59 + MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x59 + MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x59 + MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x59 + MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x59 + MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x59 + MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x59 + MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x59 + MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x59 + MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x59 + MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x59 + MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x59 + MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x59 + >; + }; + + pinctrl_pwm3: pwm3grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO04__PWM3_OUT 0x0b0b0 + >; + }; + + pinctrl_stmpe: stmpegrp { + fsl,pins = < + MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x17059 + >; + }; +}; diff --git a/arch/arm/boot/dts/imx6ul-phytec-segin.dtsi b/arch/arm/boot/dts/imx6ul-phytec-segin.dtsi index 7367279748f4..95e4080dd0a6 100644 --- a/arch/arm/boot/dts/imx6ul-phytec-segin.dtsi +++ b/arch/arm/boot/dts/imx6ul-phytec-segin.dtsi @@ -130,31 +130,6 @@ status = "disabled"; }; - stmpe: touchscreen@44 { - compatible = "st,stmpe811"; - reg = <0x44>; - interrupts = <3 IRQ_TYPE_LEVEL_LOW>; - interrupt-parent = <&gpio5>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_stmpe>; - status = "disabled"; - - stmpe_touchscreen { - compatible = "st,stmpe-ts"; - st,sample-time = <4>; - st,mod-12b = <1>; - st,ref-sel = <0>; - st,adc-freq = <1>; - st,ave-ctrl = <1>; - st,touch-det-delay = <2>; - st,settling = <2>; - st,fraction-z = <7>; - st,i-drive = <1>; - touchscreen-inverted-x = <1>; - touchscreen-inverted-y = <1>; - }; - }; - i2c_rtc: rtc@68 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_rtc_int>; @@ -176,12 +151,6 @@ }; }; -&pwm3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm3>; - status = "disabled"; -}; - &sai2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sai2>; @@ -267,12 +236,6 @@ >; }; - pinctrl_pwm3: pwm3grp { - fsl,pins = < - MX6UL_PAD_GPIO1_IO04__PWM3_OUT 0x0b0b0 - >; - }; - pinctrl_rtc_int: rtcintgrp { fsl,pins = < MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x17059 @@ -289,12 +252,6 @@ >; }; - pinctrl_stmpe: stmpegrp { - fsl,pins = < - MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x17059 - >; - }; - pinctrl_uart5: uart5grp { fsl,pins = < MX6UL_PAD_UART5_TX_DATA__UART5_DCE_TX 0x1b0b1 diff --git a/arch/arm/boot/dts/imx6ull-phytec-segin-ff-rdk-emmc.dts b/arch/arm/boot/dts/imx6ull-phytec-segin-ff-rdk-emmc.dts index 9648d4ecaf58..8e2a4c5d7765 100644 --- a/arch/arm/boot/dts/imx6ull-phytec-segin-ff-rdk-emmc.dts +++ b/arch/arm/boot/dts/imx6ull-phytec-segin-ff-rdk-emmc.dts @@ -9,6 +9,7 @@ #include "imx6ull-phytec-phycore-som.dtsi" #include "imx6ull-phytec-segin.dtsi" #include "imx6ull-phytec-segin-peb-eval-01.dtsi" +#include "imx6ull-phytec-segin-peb-av-02.dtsi" / { model = "PHYTEC phyBOARD-Segin i.MX6 ULL Full Featured with eMMC"; diff --git a/arch/arm/boot/dts/imx6ull-phytec-segin-ff-rdk-nand.dts b/arch/arm/boot/dts/imx6ull-phytec-segin-ff-rdk-nand.dts index 656baf846453..c8d3eff9ed4b 100644 --- a/arch/arm/boot/dts/imx6ull-phytec-segin-ff-rdk-nand.dts +++ b/arch/arm/boot/dts/imx6ull-phytec-segin-ff-rdk-nand.dts @@ -9,6 +9,7 @@ #include "imx6ull-phytec-phycore-som.dtsi" #include "imx6ull-phytec-segin.dtsi" #include "imx6ull-phytec-segin-peb-eval-01.dtsi" +#include "imx6ull-phytec-segin-peb-av-02.dtsi" / { model = "PHYTEC phyBOARD-Segin i.MX6 ULL Full Featured with NAND"; diff --git a/arch/arm/boot/dts/imx6ull-phytec-segin-peb-av-02.dtsi b/arch/arm/boot/dts/imx6ull-phytec-segin-peb-av-02.dtsi new file mode 100644 index 000000000000..06bb7f327780 --- /dev/null +++ b/arch/arm/boot/dts/imx6ull-phytec-segin-peb-av-02.dtsi @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright (C) 2018 PHYTEC Messtechnik GmbH + * Author: Stefan Riedmueller + */ + +#include "imx6ul-phytec-segin-peb-av-02.dtsi" + +&iomuxc { + /delete-node/ edtft5406grp; + /delete-node/ stmpegrp; +}; + +&iomuxc_snvs { + pinctrl_edt_ft5406: edtft5406grp { + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x1b0b0 + >; + }; + + pinctrl_stmpe: stmpegrp { + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x17059 + >; + }; +}; diff --git a/arch/arm/boot/dts/imx6ull-phytec-segin.dtsi b/arch/arm/boot/dts/imx6ull-phytec-segin.dtsi index c1595fc785f7..e287a0453b5f 100644 --- a/arch/arm/boot/dts/imx6ull-phytec-segin.dtsi +++ b/arch/arm/boot/dts/imx6ull-phytec-segin.dtsi @@ -14,7 +14,6 @@ &iomuxc { /delete-node/ flexcan1engrp; /delete-node/ rtcintgrp; - /delete-node/ stmpegrp; }; &iomuxc_snvs { @@ -29,10 +28,4 @@ MX6ULL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x17059 >; }; - - pinctrl_stmpe: stmpegrp { - fsl,pins = < - MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x17059 - >; - }; }; From 93c0289c11b08467c0c998d35f050e6664bbf99c Mon Sep 17 00:00:00 2001 From: Stefan Riedmueller Date: Thu, 29 Oct 2020 08:03:24 +0100 Subject: [PATCH 220/799] ARM: dts: imx6ul: segin: peb-av-02: Mark stmpe touch as wakeup-source Mark the STMPE resistive touch controller as a wakeup-source. Signed-off-by: Stefan Riedmueller Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6ul-phytec-segin-peb-av-02.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/imx6ul-phytec-segin-peb-av-02.dtsi b/arch/arm/boot/dts/imx6ul-phytec-segin-peb-av-02.dtsi index b511c6dec427..7cda6944501d 100644 --- a/arch/arm/boot/dts/imx6ul-phytec-segin-peb-av-02.dtsi +++ b/arch/arm/boot/dts/imx6ul-phytec-segin-peb-av-02.dtsi @@ -58,6 +58,7 @@ pinctrl-0 = <&pinctrl_stmpe>; interrupts = <3 IRQ_TYPE_LEVEL_LOW>; interrupt-parent = <&gpio5>; + wakeup-source; status = "disabled"; stmpe_touchscreen { From 7fc6622c1a8d0f69be0783245fe38fed17ad8d18 Mon Sep 17 00:00:00 2001 From: Oleksij Rempel Date: Fri, 30 Oct 2020 15:00:27 +0100 Subject: [PATCH 221/799] dt-bindings: vendor-prefixes: Add an entry for Altus-Escon-Company Add "alt" entry for Altus-Escon-Company BV: https://www.altus-escon.com/ Signed-off-by: Oleksij Rempel Acked-by: Rob Herring Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index 31897f127b47..8db0ab3b2012 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -67,6 +67,8 @@ patternProperties: description: AlphaScale Integrated Circuits Systems, Inc. "^alps,.*": description: Alps Electric Co., Ltd. + "^alt,.*": + description: Altus-Escon-Company BV "^altr,.*": description: Altera Corp. "^amarula,.*": From cd49dccbde912ae7e6ee4d4f94f71740c690b520 Mon Sep 17 00:00:00 2001 From: Oleksij Rempel Date: Fri, 30 Oct 2020 15:00:28 +0100 Subject: [PATCH 222/799] dt-bindings: arm: fsl: add Altesco I6P board Add Altus-Escon-Company BV I6P iMX6dl based board Signed-off-by: Oleksij Rempel Acked-by: Rob Herring Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/arm/fsl.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index 85fb24da4a02..4986ffcceab6 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -349,6 +349,7 @@ properties: - abb,aristainetos-imx6dl-7 # aristainetos i.MX6 Dual Lite Board 7 - abb,aristainetos2-imx6dl-4 # aristainetos2 i.MX6 Dual Lite Board 4 - abb,aristainetos2-imx6dl-7 # aristainetos2 i.MX6 Dual Lite Board 7 + - alt,alti6p # Altesco I6P Board - boundary,imx6dl-nit6xlite # Boundary Devices Nitrogen6 Lite - boundary,imx6dl-nitrogen6x # Boundary Devices Nitrogen6x - bticino,imx6dl-mamoj # BTicino i.MX6DL Mamoj From df0852c234d9a73ad2469cd0562ba212a422c374 Mon Sep 17 00:00:00 2001 From: Oleksij Rempel Date: Fri, 30 Oct 2020 15:00:29 +0100 Subject: [PATCH 223/799] ARM: dts: add Altesco I6P board Altesco (Altus-Escon-Company BV) I6P is a part of the diagnostic system for the vehicle inspection stations. Co-developed-by: David Jander Signed-off-by: David Jander Signed-off-by: Oleksij Rempel Signed-off-by: Shawn Guo --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/imx6dl-alti6p.dts | 564 ++++++++++++++++++++++++++++ 2 files changed, 565 insertions(+) create mode 100644 arch/arm/boot/dts/imx6dl-alti6p.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 654692919a27..526e6c237a9c 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -414,6 +414,7 @@ dtb-$(CONFIG_SOC_IMX53) += \ imx53-usbarmory.dtb \ imx53-voipac-bsb.dtb dtb-$(CONFIG_SOC_IMX6Q) += \ + imx6dl-alti6p.dtb \ imx6dl-apf6dev.dtb \ imx6dl-aristainetos_4.dtb \ imx6dl-aristainetos_7.dtb \ diff --git a/arch/arm/boot/dts/imx6dl-alti6p.dts b/arch/arm/boot/dts/imx6dl-alti6p.dts new file mode 100644 index 000000000000..4329b372d8cb --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-alti6p.dts @@ -0,0 +1,564 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) 2016 Protonic Holland + * Copyright (c) 2020 Oleksij Rempel , Pengutronix + */ + +/dts-v1/; +#include +#include +#include +#include "imx6dl.dtsi" + +/ { + model = "Altesco I6P Board"; + compatible = "alt,alti6p", "fsl,imx6dl"; + + chosen { + stdout-path = &uart4; + }; + + clock_ksz8081: clock-ksz8081 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <50000000>; + }; + + i2c2-mux { + compatible = "i2c-mux"; + i2c-parent = <&i2c2>; + mux-controls = <&i2c_mux>; + #address-cells = <1>; + #size-cells = <0>; + + i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + i2c4-mux { + compatible = "i2c-mux"; + i2c-parent = <&i2c4>; + mux-controls = <&i2c_mux>; + #address-cells = <1>; + #size-cells = <0>; + + i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_leds>; + + led-debug0 { + function = LED_FUNCTION_STATUS; + gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + + led-debug1 { + function = LED_FUNCTION_SD; + gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "disk-activity"; + }; + }; + + i2c_mux: mux-controller { + compatible = "gpio-mux"; + #mux-control-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2cmux>; + + mux-gpios = <&gpio5 10 GPIO_ACTIVE_HIGH>, + <&gpio5 11 GPIO_ACTIVE_HIGH>; + }; + + reg_1v8: regulator-1v8 { + compatible = "regulator-fixed"; + regulator-name = "1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + reg_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_5v0: regulator-5v0 { + compatible = "regulator-fixed"; + regulator-name = "5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + reg_h1_vbus: regulator-h1-vbus { + compatible = "regulator-fixed"; + regulator-name = "h1-vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_otg_vbus: regulator-otg-vbus { + compatible = "regulator-fixed"; + regulator-name = "otg-vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "prti6q-sgtl5000"; + simple-audio-card,format = "i2s"; + simple-audio-card,widgets = + "Microphone", "Microphone Jack", + "Line", "Line In Jack", + "Headphone", "Headphone Jack", + "Speaker", "External Speaker"; + simple-audio-card,routing = + "MIC_IN", "Microphone Jack", + "LINE_IN", "Line In Jack", + "Headphone Jack", "HP_OUT", + "External Speaker", "LINE_OUT"; + + simple-audio-card,cpu { + sound-dai = <&ssi1>; + system-clock-frequency = <0>; + }; + + simple-audio-card,codec { + sound-dai = <&sgtl5000>; + bitclock-master; + frame-master; + }; + }; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux>; + status = "okay"; + + mux-ssi1 { + fsl,audmux-port = <0>; + fsl,port-config = < + IMX_AUDMUX_V2_PTCR_SYN 0 + IMX_AUDMUX_V2_PTCR_TFSEL(2) 0 + IMX_AUDMUX_V2_PTCR_TCSEL(2) 0 + IMX_AUDMUX_V2_PTCR_TFSDIR 0 + IMX_AUDMUX_V2_PTCR_TCLKDIR IMX_AUDMUX_V2_PDCR_RXDSEL(2) + >; + }; + + mux-pins3 { + fsl,audmux-port = <2>; + fsl,port-config = < + IMX_AUDMUX_V2_PTCR_SYN IMX_AUDMUX_V2_PDCR_RXDSEL(0) + 0 IMX_AUDMUX_V2_PDCR_TXRXEN + >; + }; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can1>; + xceiver-supply = <®_5v0>; + status = "okay"; +}; + +&ecspi1 { + cs-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <20000000>; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rmii"; + clocks = <&clks IMX6QDL_CLK_ENET>, + <&clks IMX6QDL_CLK_ENET>, + <&clock_ksz8081>; + clock-names = "ipg", "ahb", "ptp"; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + /* Microchip KSZ8081RNA PHY */ + rgmii_phy: ethernet-phy@0 { + reg = <0>; + interrupts-extended = <&gpio4 30 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&gpio4 26 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <300>; + }; + }; +}; + +&gpio1 { + gpio-line-names = + "", "SD1_CD", "", "USB_H1_OC", "", "", "", "", + "DEBUG_0", "DEBUG_1", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&gpio3 { + gpio-line-names = + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "ECSPI1_SS1", "", "USB_EXT1_OC", "USB_EXT1_PWR", "", + "", "", "", "", "", "", "", ""; +}; + +&gpio4 { + gpio-line-names = + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "ETH_RESET", "", "", "BUZZER", "ETH_INTRP", ""; +}; + +&gpio5 { + gpio-line-names = + "", "", "", "", "", "", "", "", + "", "", "I2C_EN13", "I2C_EN24", "", "", "", "", + "", "", "", "", "", "AUDIO_RESET", "", "", + "", "", "", "", "", "", "", ""; +}; + +&hdmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hdmi>; + ddc-i2c-bus = <&i2c1>; + status = "okay"; +}; + +/* DDC */ +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + sgtl5000: audio-codec@a { + compatible = "fsl,sgtl5000"; + reg = <0xa>; + #sound-dai-cells = <0>; + clocks = <&clks 201>; + VDDA-supply = <®_3v3>; + VDDIO-supply = <®_3v3>; + VDDD-supply = <®_1v8>; + }; + + /* additional i2c devices are added automatically by the boot loader */ +}; + +&i2c2 { + clock-frequency = <50000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + /* external interface, device are configured from user space */ +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + rtc@51 { + compatible = "nxp,pcf8563"; + reg = <0x51>; + }; + + temperature-sensor@70 { + compatible = "ti,tmp103"; + reg = <0x70>; + }; +}; + +&i2c4 { + clock-frequency = <50000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c4>; + status = "okay"; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + +&ssi1 { + #sound-dai-cells = <0>; + fsl,mode = "ac97-slave"; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + status = "okay"; +}; + +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + status = "okay"; +}; + +&usbh1 { + vbus-supply = <®_h1_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh1>; + phy_type = "utmi"; + dr_mode = "host"; + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_otg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + phy_type = "utmi"; + dr_mode = "host"; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; + no-1-8-v; + disable-wp; + cap-sd-highspeed; + no-mmc; + no-sdio; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3>; + bus-width = <8>; + no-1-8-v; + non-removable; + no-sd; + no-sdio; + status = "okay"; +}; + +&iomuxc { + pinctrl_audmux: audmuxgrp { + fsl,pins = < + MX6QDL_PAD_CSI0_MCLK__CCM_CLKO1 0x030b0 + MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 + MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 + MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 + MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 + >; + }; + + pinctrl_can1: can1grp { + fsl,pins = < + MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b000 + MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x3008 + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x1b000 + MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x3008 + MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x3008 + /* CS */ + MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x3008 + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + /* MX6QDL_ENET_PINGRP4 */ + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0 + MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0 + MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0 + MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 + MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0 + MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0 + MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0 + + MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x1b0b0 + /* Phy reset */ + MX6QDL_PAD_DISP0_DAT5__GPIO4_IO26 0x1b0b0 + /* nINTRP */ + MX6QDL_PAD_DISP0_DAT9__GPIO4_IO30 0x1b0b0 + >; + }; + + pinctrl_hdmi: hdmigrp { + fsl,pins = < + /* NOTE: DDC is done via I2C2, so DON'T configure DDC + * pins for HDMI! + */ + MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x1f8b0 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001f8b1 + MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001f8b1 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c4: i2c4grp { + fsl,pins = < + MX6QDL_PAD_NANDF_CS3__I2C4_SDA 0x4001f8b1 + MX6QDL_PAD_NANDF_WP_B__I2C4_SCL 0x4001f8b1 + >; + }; + + pinctrl_i2cmux: i2cmuxgrp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT16__GPIO5_IO10 0x1b0b0 + MX6QDL_PAD_DISP0_DAT17__GPIO5_IO11 0x1b0b0 + >; + }; + + pinctrl_leds: ledsgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x1b0b0 + MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0 + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT8__PWM1_OUT 0x8 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_usbh1: usbh1grp { + fsl,pins = < + MX6QDL_PAD_GPIO_3__USB_H1_OC 0x1B058 + MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1B058 + + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x1b0b0 + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__SD1_CMD 0x170f9 + MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100f9 + MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x170f9 + MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x170f9 + MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x170f9 + MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170f9 + MX6QDL_PAD_GPIO_1__GPIO1_IO01 0x1b0b0 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17099 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10099 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17099 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17099 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17099 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17099 + MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17099 + MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17099 + MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17099 + MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17099 + MX6QDL_PAD_SD3_RST__SD3_RESET 0x1b0b1 + >; + }; +}; From 236d454b27c7c17152663426613be274effc19fc Mon Sep 17 00:00:00 2001 From: Oleksij Rempel Date: Mon, 2 Nov 2020 10:02:11 +0100 Subject: [PATCH 224/799] dt-bindings: arm: fsl: add Van der Laan LANMCU board Add Van der Laan LANMCU iMX6dl based board Signed-off-by: Oleksij Rempel Reviewed-by: Krzysztof Kozlowski Acked-by: Rob Herring Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/arm/fsl.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index 4986ffcceab6..c5b8e34a8991 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -378,6 +378,7 @@ properties: - technologic,imx6dl-ts4900 - technologic,imx6dl-ts7970 - udoo,imx6dl-udoo # Udoo i.MX6 Dual-lite Board + - vdl,lanmcu # Van der Laan LANMCU board - wand,imx6dl-wandboard # Wandboard i.MX6 Dual Lite Board - ysoft,imx6dl-yapp4-draco # i.MX6 DualLite Y Soft IOTA Draco board - ysoft,imx6dl-yapp4-hydra # i.MX6 DualLite Y Soft IOTA Hydra board From d1f1858f51be4d7900fe2bac6394c8dfc641f2c4 Mon Sep 17 00:00:00 2001 From: Oleksij Rempel Date: Mon, 2 Nov 2020 10:02:12 +0100 Subject: [PATCH 225/799] ARM: dts: add Van der Laan LANMCU board Van der Laan LANMCU is a module for the food storage rooms to control proper gas composition. Co-developed-by: Robin van der Gracht Signed-off-by: Robin van der Gracht Signed-off-by: Oleksij Rempel Reviewed-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/imx6dl-lanmcu.dts | 470 ++++++++++++++++++++++++++++ 2 files changed, 471 insertions(+) create mode 100644 arch/arm/boot/dts/imx6dl-lanmcu.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 526e6c237a9c..d3275fe3095f 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -451,6 +451,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \ imx6dl-icore.dtb \ imx6dl-icore-mipi.dtb \ imx6dl-icore-rqs.dtb \ + imx6dl-lanmcu.dtb \ imx6dl-mamoj.dtb \ imx6dl-nit6xlite.dtb \ imx6dl-nitrogen6x.dtb \ diff --git a/arch/arm/boot/dts/imx6dl-lanmcu.dts b/arch/arm/boot/dts/imx6dl-lanmcu.dts new file mode 100644 index 000000000000..6b6e6fcdea9c --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-lanmcu.dts @@ -0,0 +1,470 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2019 Protonic Holland + * Copyright (c) 2020 Oleksij Rempel , Pengutronix + */ + +/dts-v1/; +#include +#include +#include "imx6dl.dtsi" + +/ { + model = "Van der Laan LANMCU"; + compatible = "vdl,lanmcu", "fsl,imx6dl"; + + chosen { + stdout-path = &uart4; + }; + + clock_ksz8081: clock-ksz8081 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <50000000>; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm1 0 5000000 0>; + brightness-levels = <0 1000>; + num-interpolated-steps = <20>; + default-brightness-level = <19>; + }; + + display { + compatible = "fsl,imx-parallel-display"; + pinctrl-0 = <&pinctrl_ipu1_disp>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + display_in: endpoint { + remote-endpoint = <&ipu1_di0_disp0>; + }; + }; + + port@1 { + reg = <1>; + + display_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_leds>; + + led-0 { + label = "debug0"; + function = LED_FUNCTION_STATUS; + gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + panel { + compatible = "edt,etm0700g0bdh6"; + backlight = <&backlight>; + + port { + panel_in: endpoint { + remote-endpoint = <&display_out>; + }; + }; + }; + + reg_otg_vbus: regulator-otg-vbus { + compatible = "regulator-fixed"; + regulator-name = "otg-vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + usdhc2_wifi_pwrseq: usdhc2-wifi-pwrseq { + compatible = "mmc-pwrseq-simple"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wifi_npd>; + reset-gpios = <&gpio6 10 GPIO_ACTIVE_LOW>; + }; + +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can1>; + status = "okay"; +}; + +&can2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can2>; + status = "okay"; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rmii"; + clocks = <&clks IMX6QDL_CLK_ENET>, + <&clks IMX6QDL_CLK_ENET>, + <&clock_ksz8081>; + clock-names = "ipg", "ahb", "ptp"; + phy-handle = <&rgmii_phy>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + /* Microchip KSZ8081RNA PHY */ + rgmii_phy: ethernet-phy@0 { + reg = <0>; + interrupts-extended = <&gpio5 23 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&gpio5 22 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <300>; + }; + }; +}; + +&gpio1 { + gpio-line-names = + "", "SD1_CD", "", "", "", "", "", "", + "DEBUG_0", "BL_PWM", "", "", "", "", "", "", + "", "", "", "", "", "", "", "ENET_LED_GREEN", + "", "", "", "", "", "", "", ""; +}; + +&gpio3 { + gpio-line-names = + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "TS_INT", "USB_OTG1_OC", "USB_OTG1_PWR", "", + "", "", "", "", "UART2_CTS", "", "UART3_CTS", ""; +}; + +&gpio5 { + gpio-line-names = + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "ENET_RST", "ENET_INT", + "", "", "I2C1_SDA", "I2C1_SCL", "", "", "", ""; +}; + +&gpio6 { + gpio-line-names = + "", "", "", "", "", "", "", "", + "", "", "WLAN_REG_ON", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&gpio7 { + gpio-line-names = + "", "", "", "", "", "", "", "", + "EMMC_RST", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + /* additional i2c devices are added automatically by the boot loader */ +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + touchscreen@38 { + compatible = "edt,edt-ft5406"; + reg = <0x38>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ts_edt>; + interrupts-extended = <&gpio3 20 IRQ_TYPE_EDGE_FALLING>; + + touchscreen-size-x = <1792>; + touchscreen-size-y = <1024>; + + touchscreen-fuzz-x = <0>; + touchscreen-fuzz-y = <0>; + + /* Touch screen calibration */ + threshold = <50>; + gain = <5>; + offset = <10>; + }; + + rtc@51 { + compatible = "nxp,pcf8563"; + reg = <0x51>; + }; +}; + +&ipu1_di0_disp0 { + remote-endpoint = <&display_in>; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + linux,rs485-enabled-at-boot-time; + uart-has-rtscts; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + linux,rs485-enabled-at-boot-time; + uart-has-rtscts; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_otg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + phy_type = "utmi"; + dr_mode = "host"; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; + no-1-8-v; + disable-wp; + cap-sd-highspeed; + no-mmc; + no-sdio; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + no-1-8-v; + non-removable; + mmc-pwrseq = <&usdhc2_wifi_pwrseq>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + wifi@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + }; +}; + +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3>; + bus-width = <8>; + no-1-8-v; + non-removable; + no-sd; + no-sdio; + status = "okay"; +}; + +&iomuxc { + pinctrl_can1: can1grp { + fsl,pins = < + MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b000 + MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x3008 + >; + }; + + pinctrl_can2: can2grp { + fsl,pins = < + MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b000 + MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x3008 + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + /* MX6QDL_ENET_PINGRP4 */ + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0 + MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0 + MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0 + MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 + MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0 + MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0 + MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0 + + MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x1b0b0 + /* Phy reset */ + MX6QDL_PAD_CSI0_DAT4__GPIO5_IO22 0x1b0b0 + /* nINTRP */ + MX6QDL_PAD_CSI0_DAT5__GPIO5_IO23 0x1b0b0 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001f8b1 + MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001f8b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 + >; + }; + + pinctrl_ipu1_disp: ipudisp1grp { + fsl,pins = < + /* DSE 0x30 => 25 Ohm, 0x20 => 37 Ohm, 0x10 => 75 Ohm */ + MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x30 + MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x30 + MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x30 + MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x30 + MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x30 + MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x30 + MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x30 + MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x30 + MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x30 + MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x30 + MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x30 + MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x30 + MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x30 + MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x30 + MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x30 + MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x30 + MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x30 + MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x30 + MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x30 + MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x30 + MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x30 + MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x30 + >; + }; + + pinctrl_leds: ledsgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x1b0b0 + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX6QDL_PAD_GPIO_9__PWM1_OUT 0x8 + >; + }; + + pinctrl_ts_edt: ts1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x1b0b0 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_EIM_D26__UART2_RX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D27__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D28__UART2_CTS_B 0x130b1 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D30__UART3_CTS_B 0x130b1 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x1b0b0 + /* power enable, high active */ + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__SD1_CMD 0x170f9 + MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100f9 + MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x170f9 + MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x170f9 + MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x170f9 + MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170f9 + MX6QDL_PAD_GPIO_1__SD1_CD_B 0x1b0b0 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170b9 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100b9 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170b9 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170b9 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170b9 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170b9 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17099 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10099 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17099 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17099 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17099 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17099 + MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17099 + MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17099 + MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17099 + MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17099 + MX6QDL_PAD_SD3_RST__SD3_RESET 0x1b0b1 + >; + }; + + pinctrl_wifi_npd: wifigrp { + fsl,pins = < + /* WL_REG_ON */ + MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x13069 + >; + }; +}; From 7544bfc0866f56326e47f8ec8b3f68c6db496125 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Tue, 3 Nov 2020 19:04:54 -0300 Subject: [PATCH 226/799] ARM: imx: imx7ulp: Add a comment explaining the B2 silicon version To help the users to understand the meaning of bits 31-28 of the JTAG_ID_REG register, add a comment explaining the value that is expected from a i.MX7ULP rev B2. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/mach-imx/mach-imx7ulp.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/mach-imx/mach-imx7ulp.c b/arch/arm/mach-imx/mach-imx7ulp.c index f6032ea7de8b..a3c8dadec1c5 100644 --- a/arch/arm/mach-imx/mach-imx7ulp.c +++ b/arch/arm/mach-imx/mach-imx7ulp.c @@ -37,6 +37,7 @@ static void __init imx7ulp_set_revision(void) * bit[31:28] of JTAG_ID register defines revision as below from B0: * 0001 B0 * 0010 B1 + * 0011 B2 */ switch (revision >> 28) { case 1: From 53cc6bc69e536efe6c1cef98edfb7b3f0a14fabe Mon Sep 17 00:00:00 2001 From: Sven Van Asbroeck Date: Wed, 4 Nov 2020 11:54:18 -0500 Subject: [PATCH 227/799] ARM: imx: mach-imx6q: correctly identify i.MX6QP SoCs The i.MX6QP rev 1.1 SoC on my board is mis-identified by Linux: the log (incorrectly) shows "i.MX6Q rev 2.1". Correct this by assuming that every SoC that identifies as i.MX6Q with rev >= 2.0 is really an i.MX6QP. Signed-off-by: Sven Van Asbroeck Reviewed-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/mach-imx/mach-imx6q.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c index 85c084a716ab..703998ebb52e 100644 --- a/arch/arm/mach-imx/mach-imx6q.c +++ b/arch/arm/mach-imx/mach-imx6q.c @@ -245,8 +245,13 @@ static void __init imx6q_axi_init(void) static void __init imx6q_init_machine(void) { - if (cpu_is_imx6q() && imx_get_soc_revision() == IMX_CHIP_REVISION_2_0) - imx_print_silicon_rev("i.MX6QP", IMX_CHIP_REVISION_1_0); + if (cpu_is_imx6q() && imx_get_soc_revision() >= IMX_CHIP_REVISION_2_0) + /* + * SoCs that identify as i.MX6Q >= rev 2.0 are really i.MX6QP. + * Quirk: i.MX6QP revision = i.MX6Q revision - (1, 0), + * e.g. i.MX6QP rev 1.1 identifies as i.MX6Q rev 2.1. + */ + imx_print_silicon_rev("i.MX6QP", imx_get_soc_revision() - 0x10); else imx_print_silicon_rev(cpu_is_imx6dl() ? "i.MX6DL" : "i.MX6Q", imx_get_soc_revision()); From 5fc865f8bfd2cd3b12f5fef3a57f73fcb67e1544 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 5 Nov 2020 19:48:07 +0100 Subject: [PATCH 228/799] dt-bindings: arm: fsl: document LS1012A FRWY board Document the compatible for LS1012A FRWY board. Signed-off-by: Krzysztof Kozlowski Acked-by: Rob Herring Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/arm/fsl.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index c5b8e34a8991..e0bbfa59bfda 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -796,6 +796,7 @@ properties: - ebs-systart,oxalis - fsl,ls1012a-rdb - fsl,ls1012a-frdm + - fsl,ls1012a-frwy - fsl,ls1012a-qds - const: fsl,ls1012a From 608f000f8a32e598ce3d7487889a499c5b5582cb Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 5 Nov 2020 19:48:08 +0100 Subject: [PATCH 229/799] dt-bindings: arm: fsl: document SolidRun LX2160A boards Document the compatible for SolidRun LX2160A based boards. Signed-off-by: Krzysztof Kozlowski Acked-by: Rob Herring Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/arm/fsl.yaml | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index e0bbfa59bfda..f793f90fe2e6 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -898,6 +898,14 @@ properties: - fsl,lx2162a-qds - const: fsl,lx2160a + - description: SolidRun LX2160A based Boards + items: + - enum: + - solidrun,clearfog-cx + - solidrun,honeycomb + - const: solidrun,lx2160a-cex7 + - const: fsl,lx2160a + - description: S32V234 based Boards items: - enum: From bc518da26e3a98d8eaa713b7e51a326eceb3b3fd Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Mon, 9 Nov 2020 12:55:40 +0100 Subject: [PATCH 230/799] arm64: defconfig: Enable R8A779A0 SoC Enable the Renesas R-Car V3U (R8A779A0) SoC in the ARM64 defconfig. Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20201109115540.2415328-1-geert+renesas@glider.be --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 17a2df6a263e..086fdef1fda8 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -953,6 +953,7 @@ CONFIG_ARCH_R8A77970=y CONFIG_ARCH_R8A77980=y CONFIG_ARCH_R8A77990=y CONFIG_ARCH_R8A77995=y +CONFIG_ARCH_R8A779A0=y CONFIG_ROCKCHIP_PM_DOMAINS=y CONFIG_ARCH_TEGRA_132_SOC=y CONFIG_ARCH_TEGRA_210_SOC=y From 92494cea405fd2136033c70abd6abf6739b12a2f Mon Sep 17 00:00:00 2001 From: Fabrizio Castro Date: Wed, 21 Oct 2020 14:53:32 +0100 Subject: [PATCH 231/799] arm64: dts: renesas: r8a77965: Add DRIF support Add the DRIF controller nodes for r8a77965 (a.k.a. R-Car M3-N). Signed-off-by: Fabrizio Castro Reviewed-by: Lad Prabhakar Link: https://lore.kernel.org/r/20201021135332.4928-6-fabrizio.castro.jz@renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a77965.dtsi | 120 ++++++++++++++++++++++ 1 file changed, 120 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi b/arch/arm64/boot/dts/renesas/r8a77965.dtsi index c355460e5f7f..d098eb3ec73a 100644 --- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi @@ -1550,6 +1550,126 @@ }; }; + drif00: rif@e6f40000 { + compatible = "renesas,r8a77965-drif", + "renesas,rcar-gen3-drif"; + reg = <0 0xe6f40000 0 0x84>; + interrupts = ; + clocks = <&cpg CPG_MOD 515>; + clock-names = "fck"; + dmas = <&dmac1 0x20>, <&dmac2 0x20>; + dma-names = "rx", "rx"; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 515>; + renesas,bonding = <&drif01>; + status = "disabled"; + }; + + drif01: rif@e6f50000 { + compatible = "renesas,r8a77965-drif", + "renesas,rcar-gen3-drif"; + reg = <0 0xe6f50000 0 0x84>; + interrupts = ; + clocks = <&cpg CPG_MOD 514>; + clock-names = "fck"; + dmas = <&dmac1 0x22>, <&dmac2 0x22>; + dma-names = "rx", "rx"; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 514>; + renesas,bonding = <&drif00>; + status = "disabled"; + }; + + drif10: rif@e6f60000 { + compatible = "renesas,r8a77965-drif", + "renesas,rcar-gen3-drif"; + reg = <0 0xe6f60000 0 0x84>; + interrupts = ; + clocks = <&cpg CPG_MOD 513>; + clock-names = "fck"; + dmas = <&dmac1 0x24>, <&dmac2 0x24>; + dma-names = "rx", "rx"; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 513>; + renesas,bonding = <&drif11>; + status = "disabled"; + }; + + drif11: rif@e6f70000 { + compatible = "renesas,r8a77965-drif", + "renesas,rcar-gen3-drif"; + reg = <0 0xe6f70000 0 0x84>; + interrupts = ; + clocks = <&cpg CPG_MOD 512>; + clock-names = "fck"; + dmas = <&dmac1 0x26>, <&dmac2 0x26>; + dma-names = "rx", "rx"; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 512>; + renesas,bonding = <&drif10>; + status = "disabled"; + }; + + drif20: rif@e6f80000 { + compatible = "renesas,r8a77965-drif", + "renesas,rcar-gen3-drif"; + reg = <0 0xe6f80000 0 0x84>; + interrupts = ; + clocks = <&cpg CPG_MOD 511>; + clock-names = "fck"; + dmas = <&dmac1 0x28>, <&dmac2 0x28>; + dma-names = "rx", "rx"; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 511>; + renesas,bonding = <&drif21>; + status = "disabled"; + }; + + drif21: rif@e6f90000 { + compatible = "renesas,r8a77965-drif", + "renesas,rcar-gen3-drif"; + reg = <0 0xe6f90000 0 0x84>; + interrupts = ; + clocks = <&cpg CPG_MOD 510>; + clock-names = "fck"; + dmas = <&dmac1 0x2a>, <&dmac2 0x2a>; + dma-names = "rx", "rx"; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 510>; + renesas,bonding = <&drif20>; + status = "disabled"; + }; + + drif30: rif@e6fa0000 { + compatible = "renesas,r8a77965-drif", + "renesas,rcar-gen3-drif"; + reg = <0 0xe6fa0000 0 0x84>; + interrupts = ; + clocks = <&cpg CPG_MOD 509>; + clock-names = "fck"; + dmas = <&dmac1 0x2c>, <&dmac2 0x2c>; + dma-names = "rx", "rx"; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 509>; + renesas,bonding = <&drif31>; + status = "disabled"; + }; + + drif31: rif@e6fb0000 { + compatible = "renesas,r8a77965-drif", + "renesas,rcar-gen3-drif"; + reg = <0 0xe6fb0000 0 0x84>; + interrupts = ; + clocks = <&cpg CPG_MOD 508>; + clock-names = "fck"; + dmas = <&dmac1 0x2e>, <&dmac2 0x2e>; + dma-names = "rx", "rx"; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 508>; + renesas,bonding = <&drif30>; + status = "disabled"; + }; + rcar_sound: sound@ec500000 { /* * #sound-dai-cells is required From 9b81018185965a306158b471db75ba0aca90ec9f Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Wed, 19 Aug 2020 15:43:43 +0200 Subject: [PATCH 232/799] arm64: dts: renesas: rcar-gen3: Convert EtherAVB to explicit delay handling Some EtherAVB variants support internal clock delay configuration, which can add larger delays than the delays that are typically supported by the PHY (using an "rgmii-*id" PHY mode, and/or "[rt]xc-skew-ps" properties). Historically, the EtherAVB driver configured these delays based on the "rgmii-*id" PHY mode. This was wrong, as these are meant solely for the PHY, not for the MAC. Hence properties were introduced for explicit configuration of these delays. Convert the R-Car Gen3 DTS files from the old to the new scheme: - Add default "rx-internal-delay-ps" and "tx-internal-delay-ps" properties to the SoC .dtsi files, to be overridden by board files where needed, - Convert board files from "rgmii-*id" PHY modes to "rgmii", adding the appropriate "rx-internal-delay-ps" and/or "tx-internal-delay-ps" overrides. Notes: - R-Car E3 and D3 do not support TX internal delay handling, - On R-Car D3, TX internal delay handling must always be enabled, hence this fixes a bug on Draak, - On R-Car V3H, RX internal delay handling must always be enabled. Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20200819134344.27813-7-geert+renesas@glider.be --- arch/arm64/boot/dts/renesas/r8a77951.dtsi | 2 ++ arch/arm64/boot/dts/renesas/r8a77960.dtsi | 2 ++ arch/arm64/boot/dts/renesas/r8a77961.dtsi | 2 ++ arch/arm64/boot/dts/renesas/r8a77965.dtsi | 2 ++ arch/arm64/boot/dts/renesas/r8a77970-eagle.dts | 3 ++- arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts | 3 ++- arch/arm64/boot/dts/renesas/r8a77970.dtsi | 2 ++ arch/arm64/boot/dts/renesas/r8a77980.dtsi | 2 ++ arch/arm64/boot/dts/renesas/r8a77990.dtsi | 1 + arch/arm64/boot/dts/renesas/r8a77995.dtsi | 1 + arch/arm64/boot/dts/renesas/salvator-common.dtsi | 2 +- arch/arm64/boot/dts/renesas/ulcb.dtsi | 2 +- 12 files changed, 20 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r8a77951.dtsi b/arch/arm64/boot/dts/renesas/r8a77951.dtsi index 18ce0face72b..644308dd886c 100644 --- a/arch/arm64/boot/dts/renesas/r8a77951.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77951.dtsi @@ -1250,6 +1250,8 @@ power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; resets = <&cpg 812>; phy-mode = "rgmii"; + rx-internal-delay-ps = <0>; + tx-internal-delay-ps = <0>; iommus = <&ipmmu_ds0 16>; #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm64/boot/dts/renesas/r8a77960.dtsi b/arch/arm64/boot/dts/renesas/r8a77960.dtsi index f379c8d1511d..53b9aa26c9b1 100644 --- a/arch/arm64/boot/dts/renesas/r8a77960.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77960.dtsi @@ -1126,6 +1126,8 @@ power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; resets = <&cpg 812>; phy-mode = "rgmii"; + rx-internal-delay-ps = <0>; + tx-internal-delay-ps = <0>; iommus = <&ipmmu_ds0 16>; #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm64/boot/dts/renesas/r8a77961.dtsi b/arch/arm64/boot/dts/renesas/r8a77961.dtsi index b0c4b8150d37..9266c60f21fa 100644 --- a/arch/arm64/boot/dts/renesas/r8a77961.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77961.dtsi @@ -1012,6 +1012,8 @@ power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; resets = <&cpg 812>; phy-mode = "rgmii"; + rx-internal-delay-ps = <0>; + tx-internal-delay-ps = <0>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi b/arch/arm64/boot/dts/renesas/r8a77965.dtsi index d098eb3ec73a..4a913df17b1d 100644 --- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi @@ -988,6 +988,8 @@ power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; resets = <&cpg 812>; phy-mode = "rgmii"; + rx-internal-delay-ps = <0>; + tx-internal-delay-ps = <0>; iommus = <&ipmmu_ds0 16>; #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts b/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts index 5c28f303e911..874a7fc2730b 100644 --- a/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts +++ b/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts @@ -81,7 +81,8 @@ renesas,no-ether-link; phy-handle = <&phy0>; - phy-mode = "rgmii-id"; + rx-internal-delay-ps = <1800>; + tx-internal-delay-ps = <2000>; status = "okay"; phy0: ethernet-phy@0 { diff --git a/arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts b/arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts index 668a1ece9af0..7417cf5fea0f 100644 --- a/arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts +++ b/arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts @@ -102,7 +102,8 @@ renesas,no-ether-link; phy-handle = <&phy0>; - phy-mode = "rgmii-id"; + rx-internal-delay-ps = <1800>; + tx-internal-delay-ps = <2000>; status = "okay"; phy0: ethernet-phy@0 { diff --git a/arch/arm64/boot/dts/renesas/r8a77970.dtsi b/arch/arm64/boot/dts/renesas/r8a77970.dtsi index baf8cc821564..5a5d5649332a 100644 --- a/arch/arm64/boot/dts/renesas/r8a77970.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77970.dtsi @@ -615,6 +615,8 @@ power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; resets = <&cpg 812>; phy-mode = "rgmii"; + rx-internal-delay-ps = <0>; + tx-internal-delay-ps = <0>; iommus = <&ipmmu_rt 3>; #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm64/boot/dts/renesas/r8a77980.dtsi b/arch/arm64/boot/dts/renesas/r8a77980.dtsi index d6cae90d7fd9..ec7ca72399ec 100644 --- a/arch/arm64/boot/dts/renesas/r8a77980.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77980.dtsi @@ -667,6 +667,8 @@ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; resets = <&cpg 812>; phy-mode = "rgmii"; + rx-internal-delay-ps = <0>; + tx-internal-delay-ps = <2000>; iommus = <&ipmmu_ds1 33>; #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm64/boot/dts/renesas/r8a77990.dtsi b/arch/arm64/boot/dts/renesas/r8a77990.dtsi index 33d7e657bd9c..87d41bc076a9 100644 --- a/arch/arm64/boot/dts/renesas/r8a77990.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77990.dtsi @@ -938,6 +938,7 @@ power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; resets = <&cpg 812>; phy-mode = "rgmii"; + rx-internal-delay-ps = <0>; iommus = <&ipmmu_ds0 16>; #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm64/boot/dts/renesas/r8a77995.dtsi b/arch/arm64/boot/dts/renesas/r8a77995.dtsi index cd7ca9774196..e1af7c4782f4 100644 --- a/arch/arm64/boot/dts/renesas/r8a77995.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77995.dtsi @@ -628,6 +628,7 @@ power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; resets = <&cpg 812>; phy-mode = "rgmii"; + rx-internal-delay-ps = <1800>; iommus = <&ipmmu_ds0 16>; #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm64/boot/dts/renesas/salvator-common.dtsi b/arch/arm64/boot/dts/renesas/salvator-common.dtsi index 1bf77957d2c2..6c643ed74fc5 100644 --- a/arch/arm64/boot/dts/renesas/salvator-common.dtsi +++ b/arch/arm64/boot/dts/renesas/salvator-common.dtsi @@ -324,7 +324,7 @@ pinctrl-0 = <&avb_pins>; pinctrl-names = "default"; phy-handle = <&phy0>; - phy-mode = "rgmii-txid"; + tx-internal-delay-ps = <2000>; status = "okay"; phy0: ethernet-phy@0 { diff --git a/arch/arm64/boot/dts/renesas/ulcb.dtsi b/arch/arm64/boot/dts/renesas/ulcb.dtsi index a2e085db87c5..8f8d7371d8e2 100644 --- a/arch/arm64/boot/dts/renesas/ulcb.dtsi +++ b/arch/arm64/boot/dts/renesas/ulcb.dtsi @@ -144,7 +144,7 @@ pinctrl-0 = <&avb_pins>; pinctrl-names = "default"; phy-handle = <&phy0>; - phy-mode = "rgmii-txid"; + tx-internal-delay-ps = <2000>; status = "okay"; phy0: ethernet-phy@0 { From a5200e63af57d05ed8bf0ffd9a6ffefc40e01e89 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Wed, 19 Aug 2020 15:43:44 +0200 Subject: [PATCH 233/799] arm64: dts: renesas: rzg2: Convert EtherAVB to explicit delay handling Some EtherAVB variants support internal clock delay configuration, which can add larger delays than the delays that are typically supported by the PHY (using an "rgmii-*id" PHY mode, and/or "[rt]xc-skew-ps" properties). Historically, the EtherAVB driver configured these delays based on the "rgmii-*id" PHY mode. This was wrong, as these are meant solely for the PHY, not for the MAC. Hence properties were introduced for explicit configuration of these delays. Convert the RZ/G2 DTS files from the old to the new scheme: - Add default "rx-internal-delay-ps" and "tx-internal-delay-ps" properties to the SoC .dtsi files, to be overridden by board files where needed, - Convert board files from "rgmii-*id" PHY modes to "rgmii", adding the appropriate "rx-internal-delay-ps" and/or "tx-internal-delay-ps" overrides. Notes: - RZ/G2E does not support TX internal delay handling. Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20200819134344.27813-8-geert+renesas@glider.be --- arch/arm64/boot/dts/renesas/beacon-renesom-som.dtsi | 3 ++- arch/arm64/boot/dts/renesas/hihope-rzg2-ex.dtsi | 2 +- arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 2 ++ arch/arm64/boot/dts/renesas/r8a774b1.dtsi | 2 ++ arch/arm64/boot/dts/renesas/r8a774c0.dtsi | 1 + arch/arm64/boot/dts/renesas/r8a774e1.dtsi | 2 ++ 6 files changed, 10 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/beacon-renesom-som.dtsi b/arch/arm64/boot/dts/renesas/beacon-renesom-som.dtsi index 97272f5fa0ab..8ac167aa18f0 100644 --- a/arch/arm64/boot/dts/renesas/beacon-renesom-som.dtsi +++ b/arch/arm64/boot/dts/renesas/beacon-renesom-som.dtsi @@ -55,7 +55,8 @@ pinctrl-0 = <&avb_pins>; pinctrl-names = "default"; phy-handle = <&phy0>; - phy-mode = "rgmii-id"; + rx-internal-delay-ps = <1800>; + tx-internal-delay-ps = <2000>; status = "okay"; phy0: ethernet-phy@0 { diff --git a/arch/arm64/boot/dts/renesas/hihope-rzg2-ex.dtsi b/arch/arm64/boot/dts/renesas/hihope-rzg2-ex.dtsi index b9e46aed5336..202c4fc88bd5 100644 --- a/arch/arm64/boot/dts/renesas/hihope-rzg2-ex.dtsi +++ b/arch/arm64/boot/dts/renesas/hihope-rzg2-ex.dtsi @@ -19,7 +19,7 @@ pinctrl-0 = <&avb_pins>; pinctrl-names = "default"; phy-handle = <&phy0>; - phy-mode = "rgmii-txid"; + tx-internal-delay-ps = <2000>; status = "okay"; phy0: ethernet-phy@0 { diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi index c15f1c571eb0..d37ec42a1caa 100644 --- a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi @@ -1115,6 +1115,8 @@ power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 812>; phy-mode = "rgmii"; + rx-internal-delay-ps = <0>; + tx-internal-delay-ps = <0>; iommus = <&ipmmu_ds0 16>; #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi index 39a1a26ffb54..83523916d360 100644 --- a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi @@ -989,6 +989,8 @@ power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; resets = <&cpg 812>; phy-mode = "rgmii"; + rx-internal-delay-ps = <0>; + tx-internal-delay-ps = <0>; iommus = <&ipmmu_ds0 16>; #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi index f27d9b2eb996..e0e54342cd4c 100644 --- a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi @@ -960,6 +960,7 @@ power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; resets = <&cpg 812>; phy-mode = "rgmii"; + rx-internal-delay-ps = <0>; iommus = <&ipmmu_ds0 16>; #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi index 9cbf963aa068..31ae3530cf3d 100644 --- a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi @@ -1212,6 +1212,8 @@ power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; resets = <&cpg 812>; phy-mode = "rgmii"; + rx-internal-delay-ps = <0>; + tx-internal-delay-ps = <0>; iommus = <&ipmmu_ds0 16>; #address-cells = <1>; #size-cells = <0>; From a511d8be4ea4c59b7eb2c65bd787b7bb90350893 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Sun, 20 Sep 2020 14:49:04 +0100 Subject: [PATCH 234/799] arm64: dts: renesas: cat874: Move connector node out of hd3ss3220 device Move connector node out of hd3ss3220 device in order to comply with usb connector bindings. Signed-off-by: Biju Das Reviewed-by: Lad Prabhakar Link: https://lore.kernel.org/r/20200920134905.4370-6-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- .../boot/dts/renesas/r8a774c0-cat874.dts | 67 ++++++++++++++----- 1 file changed, 50 insertions(+), 17 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r8a774c0-cat874.dts b/arch/arm64/boot/dts/renesas/r8a774c0-cat874.dts index 26aee004a44e..ea87cb5a459c 100644 --- a/arch/arm64/boot/dts/renesas/r8a774c0-cat874.dts +++ b/arch/arm64/boot/dts/renesas/r8a774c0-cat874.dts @@ -129,6 +129,29 @@ #clock-cells = <0>; clock-frequency = <74250000>; }; + + connector { + compatible = "usb-c-connector"; + label = "USB-C"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + hs_ep: endpoint { + remote-endpoint = <&usb3_hs_ep>; + }; + }; + port@1 { + reg = <1>; + ss_ep: endpoint { + remote-endpoint = <&hd3ss3220_in_ep>; + }; + }; + }; + }; }; &audio_clk_a { @@ -186,20 +209,19 @@ interrupt-parent = <&gpio6>; interrupts = <3 IRQ_TYPE_LEVEL_LOW>; - connector { - compatible = "usb-c-connector"; - label = "USB-C"; - data-role = "dual"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - reg = <1>; - hd3ss3220_ep: endpoint { - remote-endpoint = <&usb3_role_switch>; - }; + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + hd3ss3220_in_ep: endpoint { + remote-endpoint = <&ss_ep>; + }; + }; + port@1 { + reg = <1>; + hd3ss3220_out_ep: endpoint { + remote-endpoint = <&usb3_role_switch>; }; }; }; @@ -405,9 +427,20 @@ status = "okay"; usb-role-switch; - port { - usb3_role_switch: endpoint { - remote-endpoint = <&hd3ss3220_ep>; + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + usb3_hs_ep: endpoint { + remote-endpoint = <&hs_ep>; + }; + }; + port@1 { + reg = <1>; + usb3_role_switch: endpoint { + remote-endpoint = <&hd3ss3220_out_ep>; + }; }; }; }; From ca8edef172109821aa100763e38d6d8d49bcdf56 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Sun, 20 Sep 2020 14:49:05 +0100 Subject: [PATCH 235/799] arm64: dts: renesas: beacon-renesom-baseboard: Move connector node out of hd3ss3220 device Move connector node out of hd3ss3220 device in order to comply with usb connector bindings. Signed-off-by: Biju Das Reviewed-by: Lad Prabhakar Link: https://lore.kernel.org/r/20200920134905.4370-7-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- .../dts/renesas/beacon-renesom-baseboard.dtsi | 67 ++++++++++++++----- 1 file changed, 50 insertions(+), 17 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/beacon-renesom-baseboard.dtsi b/arch/arm64/boot/dts/renesas/beacon-renesom-baseboard.dtsi index 66c9153b3101..e66b5b36e489 100644 --- a/arch/arm64/boot/dts/renesas/beacon-renesom-baseboard.dtsi +++ b/arch/arm64/boot/dts/renesas/beacon-renesom-baseboard.dtsi @@ -223,6 +223,29 @@ #clock-cells = <0>; clock-frequency = <25000000>; }; + + connector { + compatible = "usb-c-connector"; + label = "USB-C"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + hs_ep: endpoint { + remote-endpoint = <&usb3_hs_ep>; + }; + }; + port@1 { + reg = <1>; + ss_ep: endpoint { + remote-endpoint = <&hd3ss3220_in_ep>; + }; + }; + }; + }; }; &audio_clk_a { @@ -427,20 +450,19 @@ interrupt-parent = <&gpio6>; interrupts = <4 IRQ_TYPE_LEVEL_LOW>; - connector { - compatible = "usb-c-connector"; - label = "USB-C"; - data-role = "dual"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - reg = <1>; - hd3ss3220_ep: endpoint { - remote-endpoint = <&usb3_role_switch>; - }; + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + hd3ss3220_in_ep: endpoint { + remote-endpoint = <&ss_ep>; + }; + }; + port@1 { + reg = <1>; + hd3ss3220_out_ep: endpoint { + remote-endpoint = <&usb3_role_switch>; }; }; }; @@ -714,9 +736,20 @@ status = "okay"; usb-role-switch; - port { - usb3_role_switch: endpoint { - remote-endpoint = <&hd3ss3220_ep>; + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + usb3_hs_ep: endpoint { + remote-endpoint = <&hs_ep>; + }; + }; + port@1 { + reg = <1>; + usb3_role_switch: endpoint { + remote-endpoint = <&hd3ss3220_out_ep>; + }; }; }; }; From f8a1620cb59bbf5d2706290ab2de7021f4eece7c Mon Sep 17 00:00:00 2001 From: Eugeniu Rosca Date: Thu, 29 Oct 2020 14:37:40 +0100 Subject: [PATCH 236/799] arm64: dts: renesas: r8a77961: Add CAN{0,1} placeholder nodes With the same background and purpose as described in v4.20-rc1 commit 92bc66bfce99cd ("arm64: dts: renesas: r8a77965: Add CAN{0,1} placeholder nodes"), add can0 and can1 placeholder nodes. Signed-off-by: Eugeniu Rosca Link: https://lore.kernel.org/r/20201029133741.25721-1-erosca@de.adit-jv.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a77961.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a77961.dtsi b/arch/arm64/boot/dts/renesas/r8a77961.dtsi index 9266c60f21fa..4b737c616257 100644 --- a/arch/arm64/boot/dts/renesas/r8a77961.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77961.dtsi @@ -1019,6 +1019,16 @@ status = "disabled"; }; + can0: can@e6c30000 { + reg = <0 0xe6c30000 0 0x1000>; + /* placeholder */ + }; + + can1: can@e6c38000 { + reg = <0 0xe6c38000 0 0x1000>; + /* placeholder */ + }; + pwm0: pwm@e6e30000 { compatible = "renesas,pwm-r8a77961", "renesas,pwm-rcar"; reg = <0 0xe6e30000 0 8>; From dd8ecc02743cc337ab56014448bacaa763c33074 Mon Sep 17 00:00:00 2001 From: Eugeniu Rosca Date: Thu, 29 Oct 2020 14:37:41 +0100 Subject: [PATCH 237/799] arm64: dts: renesas: r8a77961: ulcb-kf: Initial device tree Create a dedicated DTB for M3-ES3.0 + ULCB + Kingfisher combo. Inspire from the pre-existing ULCB-KF device trees: $ ls -1 arch/arm64/boot/dts/renesas/*ulcb-kf.dts arch/arm64/boot/dts/renesas/r8a77950-ulcb-kf.dts arch/arm64/boot/dts/renesas/r8a77951-ulcb-kf.dts arch/arm64/boot/dts/renesas/r8a77960-ulcb-kf.dts arch/arm64/boot/dts/renesas/r8a77965-ulcb-kf.dts Signed-off-by: Eugeniu Rosca Link: https://lore.kernel.org/r/20201029133741.25721-2-erosca@de.adit-jv.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/Makefile | 1 + arch/arm64/boot/dts/renesas/r8a77961-ulcb-kf.dts | 15 +++++++++++++++ 2 files changed, 16 insertions(+) create mode 100644 arch/arm64/boot/dts/renesas/r8a77961-ulcb-kf.dts diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile index 2b043b59c669..3b8b03705917 100644 --- a/arch/arm64/boot/dts/renesas/Makefile +++ b/arch/arm64/boot/dts/renesas/Makefile @@ -42,6 +42,7 @@ dtb-$(CONFIG_ARCH_R8A77960) += r8a77960-ulcb-kf.dtb dtb-$(CONFIG_ARCH_R8A77961) += r8a77961-salvator-xs.dtb dtb-$(CONFIG_ARCH_R8A77961) += r8a77961-ulcb.dtb +dtb-$(CONFIG_ARCH_R8A77961) += r8a77961-ulcb-kf.dtb dtb-$(CONFIG_ARCH_R8A77965) += r8a77965-salvator-x.dtb dtb-$(CONFIG_ARCH_R8A77965) += r8a77965-salvator-xs.dtb diff --git a/arch/arm64/boot/dts/renesas/r8a77961-ulcb-kf.dts b/arch/arm64/boot/dts/renesas/r8a77961-ulcb-kf.dts new file mode 100644 index 000000000000..6ec958348eb0 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r8a77961-ulcb-kf.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the M3ULCB Kingfisher board + * + * Copyright (C) 2020 Eugeniu Rosca + */ + +#include "r8a77961-ulcb.dts" +#include "ulcb-kf.dtsi" + +/ { + model = "Renesas M3ULCB Kingfisher board based on r8a77961"; + compatible = "shimafuji,kingfisher", "renesas,m3ulcb", + "renesas,r8a77961"; +}; From 43bba65761952f58e850d918ee43b648427609bb Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Thu, 5 Nov 2020 12:11:27 +0000 Subject: [PATCH 238/799] arm64: dts: renesas: hihope-rev4: Add a comment explaining switch SW2404 Switch SW2404 should be at position 1 so that the clock output from CS2000 is connected to AUDIO_CLKB_A. Signed-off-by: Lad Prabhakar Reviewed-by: Chris Paterson Link: https://lore.kernel.org/r/20201105121127.11830-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/hihope-rev4.dtsi | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/renesas/hihope-rev4.dtsi b/arch/arm64/boot/dts/renesas/hihope-rev4.dtsi index 3046c07a288b..929f4a1d3f90 100644 --- a/arch/arm64/boot/dts/renesas/hihope-rev4.dtsi +++ b/arch/arm64/boot/dts/renesas/hihope-rev4.dtsi @@ -91,7 +91,11 @@ #clock-cells = <1>; clock-frequency = <12288000 11289600>; - /* update to */ + /* + * Update to + * Switch SW2404 should be at position 1 so that clock from + * CS2000 is connected to AUDIO_CLKB_A + */ clocks = <&cpg CPG_MOD 1005>, <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, From df9dbaf2c415cd94ad520067a1eccfee62f00a33 Mon Sep 17 00:00:00 2001 From: "H. Nikolaus Schaller" Date: Sat, 3 Oct 2020 16:10:00 +0200 Subject: [PATCH 239/799] ARM: dts: pandaboard: fix pinmux for gpio user button of Pandaboard ES The pinmux control register offset passed to OMAP4_IOPAD is odd. Fixes: ab9a13665e7c ("ARM: dts: pandaboard: add gpio user button") Cc: stable@vger.kernel.org Signed-off-by: H. Nikolaus Schaller Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap4-panda-es.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/omap4-panda-es.dts b/arch/arm/boot/dts/omap4-panda-es.dts index cfa85aa3da08..6afa8fd7c412 100644 --- a/arch/arm/boot/dts/omap4-panda-es.dts +++ b/arch/arm/boot/dts/omap4-panda-es.dts @@ -46,7 +46,7 @@ button_pins: pinmux_button_pins { pinctrl-single,pins = < - OMAP4_IOPAD(0x11b, PIN_INPUT_PULLUP | MUX_MODE3) /* gpio_113 */ + OMAP4_IOPAD(0x0fc, PIN_INPUT_PULLUP | MUX_MODE3) /* gpio_113 */ >; }; }; From b86516452cfd94321900abe7c8ac843c146a8c53 Mon Sep 17 00:00:00 2001 From: "H. Nikolaus Schaller" Date: Sat, 3 Oct 2020 16:10:01 +0200 Subject: [PATCH 240/799] ARM: dts: pandaboard es: add bluetooth uart for HCI The wl271 bluetooth uart is connected to uart2. Setup a serdev uart child and separate bluetooth and uart2 pinmux from wl12xx pinmux to better group the pins and muxes. Signed-off-by: H. Nikolaus Schaller Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap4-panda-es.dts | 32 ++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/arch/arm/boot/dts/omap4-panda-es.dts b/arch/arm/boot/dts/omap4-panda-es.dts index 6afa8fd7c412..7c6886cd738f 100644 --- a/arch/arm/boot/dts/omap4-panda-es.dts +++ b/arch/arm/boot/dts/omap4-panda-es.dts @@ -49,6 +49,22 @@ OMAP4_IOPAD(0x0fc, PIN_INPUT_PULLUP | MUX_MODE3) /* gpio_113 */ >; }; + + bt_pins: pinmux_bt_pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x06c, PIN_OUTPUT | MUX_MODE3) /* gpmc_a22.gpio_46 - BTEN */ + OMAP4_IOPAD(0x072, PIN_OUTPUT_PULLUP | MUX_MODE3) /* gpmc_a25.gpio_49 - BTWAKEUP */ + >; + }; + + uart2_pins: pinmux_uart2_pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x118, PIN_INPUT_PULLUP | MUX_MODE0) /* uart2_cts.uart2_cts - HCI */ + OMAP4_IOPAD(0x11a, PIN_OUTPUT | MUX_MODE0) /* uart2_rts.uart2_rts */ + OMAP4_IOPAD(0x11c, PIN_INPUT_PULLUP | MUX_MODE0) /* uart2_rx.uart2_rx */ + OMAP4_IOPAD(0x11e, PIN_OUTPUT | MUX_MODE0) /* uart2_tx.uart2_tx */ + >; + }; }; &led_wkgpio_pins { @@ -80,3 +96,19 @@ &gpio1_target { ti,no-reset-on-init; }; + +&wl12xx_gpio { + pinctrl-single,pins = < + OMAP4_IOPAD(0x066, PIN_OUTPUT | MUX_MODE3) /* gpmc_a19.gpio_43 */ + OMAP4_IOPAD(0x070, PIN_OUTPUT_PULLUP | MUX_MODE3) /* gpmc_a24.gpio_48 */ + >; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins &bt_pins>; + bluetooth: tiwi { + compatible = "ti,wl1271-st"; + enable-gpios = <&gpio2 14 GPIO_ACTIVE_HIGH>; /* GPIO_46 */ + }; +}; From 35f9a0d32effa3411798c68d7b46f2c7a4d41f9d Mon Sep 17 00:00:00 2001 From: Serge Semin Date: Tue, 20 Oct 2020 14:59:33 +0300 Subject: [PATCH 241/799] ARM: dts: am437x: Correct DWC USB3 compatible string Syonpsys IP cores are supposed to be defined with "snps" vendor-prefix. Use it instead of the deprecated "synopsys" one. Signed-off-by: Serge Semin Reviewed-by: Krzysztof Kozlowski Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am437x-l4.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/am437x-l4.dtsi b/arch/arm/boot/dts/am437x-l4.dtsi index c220dc3c4e0f..700c7650c845 100644 --- a/arch/arm/boot/dts/am437x-l4.dtsi +++ b/arch/arm/boot/dts/am437x-l4.dtsi @@ -2388,7 +2388,7 @@ ranges = <0 0 0x20000>; usb1: usb@10000 { - compatible = "synopsys,dwc3"; + compatible = "snps,dwc3"; reg = <0x10000 0x10000>; interrupts = , , @@ -2468,7 +2468,7 @@ ranges = <0 0 0x20000>; usb2: usb@10000 { - compatible = "synopsys,dwc3"; + compatible = "snps,dwc3"; reg = <0x10000 0x10000>; interrupts = , , From bdb65ec381f5503b257e41669f9998492b6083aa Mon Sep 17 00:00:00 2001 From: Serge Semin Date: Tue, 20 Oct 2020 14:59:52 +0300 Subject: [PATCH 242/799] ARM: dts: omap5: Harmonize DWC USB3 DT nodes name In accordance with the DWC USB3 bindings the corresponding node name is suppose to comply with the Generic USB HCD DT schema, which requires the USB nodes to have the name acceptable by the regexp: "^usb(@.*)?" . Make sure the "snps,dwc3"-compatible nodes are correctly named. Signed-off-by: Serge Semin Acked-by: Krzysztof Kozlowski Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap5-l4.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/omap5-l4.dtsi b/arch/arm/boot/dts/omap5-l4.dtsi index f3d3a16b7c64..887b3359dd5a 100644 --- a/arch/arm/boot/dts/omap5-l4.dtsi +++ b/arch/arm/boot/dts/omap5-l4.dtsi @@ -194,7 +194,7 @@ #size-cells = <1>; utmi-mode = <2>; ranges = <0 0 0x20000>; - dwc3: dwc3@10000 { + dwc3: usb@10000 { compatible = "snps,dwc3"; reg = <0x10000 0x10000>; interrupts = , From f487e6d6c5c6d1adb56d1752ca16b9d6c7c24068 Mon Sep 17 00:00:00 2001 From: Alexander Dahl Date: Mon, 5 Oct 2020 22:34:48 +0200 Subject: [PATCH 243/799] ARM: dts: omap: Fix schema warnings for pwm-leds The node names for devices using the pwm-leds driver follow a certain naming scheme (now). Parent node name is not enforced, but recommended by DT project. DTC arch/arm/boot/dts/omap3-beagle-xm.dt.yaml CHECK arch/arm/boot/dts/omap3-beagle-xm.dt.yaml /home/alex/build/linux/arch/arm/boot/dts/omap3-beagle-xm.dt.yaml: pwmleds: 'pmu_stat' does not match any of the regexes: '^led(-[0-9a-f]+)?$', 'pinctrl-[0-9]+' From schema: /home/alex/src/linux/leds/Documentation/devicetree/bindings/leds/leds-pwm.yaml DTC arch/arm/boot/dts/omap3-beagle-xm-ab.dt.yaml CHECK arch/arm/boot/dts/omap3-beagle-xm-ab.dt.yaml /home/alex/build/linux/arch/arm/boot/dts/omap3-beagle-xm-ab.dt.yaml: pwmleds: 'pmu_stat' does not match any of the regexes: '^led(-[0-9a-f]+)?$', 'pinctrl-[0-9]+' From schema: /home/alex/src/linux/leds/Documentation/devicetree/bindings/leds/leds-pwm.yaml DTC arch/arm/boot/dts/omap3-overo-alto35.dt.yaml CHECK arch/arm/boot/dts/omap3-overo-alto35.dt.yaml /home/alex/build/linux/arch/arm/boot/dts/omap3-overo-alto35.dt.yaml: pwmleds: 'overo' does not match any of the regexes: '^led(-[0-9a-f]+)?$', 'pinctrl-[0-9]+' From schema: /home/alex/src/linux/leds/Documentation/devicetree/bindings/leds/leds-pwm.yaml DTC arch/arm/boot/dts/omap3-overo-chestnut43.dt.yaml CHECK arch/arm/boot/dts/omap3-overo-chestnut43.dt.yaml /home/alex/build/linux/arch/arm/boot/dts/omap3-overo-chestnut43.dt.yaml: pwmleds: 'overo' does not match any of the regexes: '^led(-[0-9a-f]+)?$', 'pinctrl-[0-9]+' From schema: /home/alex/src/linux/leds/Documentation/devicetree/bindings/leds/leds-pwm.yaml DTC arch/arm/boot/dts/omap3-overo-gallop43.dt.yaml CHECK arch/arm/boot/dts/omap3-overo-gallop43.dt.yaml /home/alex/build/linux/arch/arm/boot/dts/omap3-overo-gallop43.dt.yaml: pwmleds: 'overo' does not match any of the regexes: '^led(-[0-9a-f]+)?$', 'pinctrl-[0-9]+' From schema: /home/alex/src/linux/leds/Documentation/devicetree/bindings/leds/leds-pwm.yaml DTC arch/arm/boot/dts/omap3-overo-palo35.dt.yaml CHECK arch/arm/boot/dts/omap3-overo-palo35.dt.yaml /home/alex/build/linux/arch/arm/boot/dts/omap3-overo-palo35.dt.yaml: pwmleds: 'overo' does not match any of the regexes: '^led(-[0-9a-f]+)?$', 'pinctrl-[0-9]+' From schema: /home/alex/src/linux/leds/Documentation/devicetree/bindings/leds/leds-pwm.yaml DTC arch/arm/boot/dts/omap3-overo-palo43.dt.yaml CHECK arch/arm/boot/dts/omap3-overo-palo43.dt.yaml /home/alex/build/linux/arch/arm/boot/dts/omap3-overo-palo43.dt.yaml: pwmleds: 'overo' does not match any of the regexes: '^led(-[0-9a-f]+)?$', 'pinctrl-[0-9]+' From schema: /home/alex/src/linux/leds/Documentation/devicetree/bindings/leds/leds-pwm.yaml DTC arch/arm/boot/dts/omap3-overo-storm-alto35.dt.yaml CHECK arch/arm/boot/dts/omap3-overo-storm-alto35.dt.yaml /home/alex/build/linux/arch/arm/boot/dts/omap3-overo-storm-alto35.dt.yaml: pwmleds: 'overo' does not match any of the regexes: '^led(-[0-9a-f]+)?$', 'pinctrl-[0-9]+' From schema: /home/alex/src/linux/leds/Documentation/devicetree/bindings/leds/leds-pwm.yaml DTC arch/arm/boot/dts/omap3-overo-storm-chestnut43.dt.yaml CHECK arch/arm/boot/dts/omap3-overo-storm-chestnut43.dt.yaml /home/alex/build/linux/arch/arm/boot/dts/omap3-overo-storm-chestnut43.dt.yaml: pwmleds: 'overo' does not match any of the regexes: '^led(-[0-9a-f]+)?$', 'pinctrl-[0-9]+' From schema: /home/alex/src/linux/leds/Documentation/devicetree/bindings/leds/leds-pwm.yaml DTC arch/arm/boot/dts/omap3-overo-storm-gallop43.dt.yaml CHECK arch/arm/boot/dts/omap3-overo-storm-gallop43.dt.yaml /home/alex/build/linux/arch/arm/boot/dts/omap3-overo-storm-gallop43.dt.yaml: pwmleds: 'overo' does not match any of the regexes: '^led(-[0-9a-f]+)?$', 'pinctrl-[0-9]+' From schema: /home/alex/src/linux/leds/Documentation/devicetree/bindings/leds/leds-pwm.yaml DTC arch/arm/boot/dts/omap3-overo-storm-palo35.dt.yaml CHECK arch/arm/boot/dts/omap3-overo-storm-palo35.dt.yaml /home/alex/build/linux/arch/arm/boot/dts/omap3-overo-storm-palo35.dt.yaml: pwmleds: 'overo' does not match any of the regexes: '^led(-[0-9a-f]+)?$', 'pinctrl-[0-9]+' From schema: /home/alex/src/linux/leds/Documentation/devicetree/bindings/leds/leds-pwm.yaml DTC arch/arm/boot/dts/omap3-overo-storm-palo43.dt.yaml CHECK arch/arm/boot/dts/omap3-overo-storm-palo43.dt.yaml /home/alex/build/linux/arch/arm/boot/dts/omap3-overo-storm-palo43.dt.yaml: pwmleds: 'overo' does not match any of the regexes: '^led(-[0-9a-f]+)?$', 'pinctrl-[0-9]+' From schema: /home/alex/src/linux/leds/Documentation/devicetree/bindings/leds/leds-pwm.yaml DTC arch/arm/boot/dts/omap3-overo-storm-summit.dt.yaml CHECK arch/arm/boot/dts/omap3-overo-storm-summit.dt.yaml /home/alex/build/linux/arch/arm/boot/dts/omap3-overo-storm-summit.dt.yaml: pwmleds: 'overo' does not match any of the regexes: '^led(-[0-9a-f]+)?$', 'pinctrl-[0-9]+' From schema: /home/alex/src/linux/leds/Documentation/devicetree/bindings/leds/leds-pwm.yaml DTC arch/arm/boot/dts/omap3-overo-storm-tobi.dt.yaml CHECK arch/arm/boot/dts/omap3-overo-storm-tobi.dt.yaml /home/alex/build/linux/arch/arm/boot/dts/omap3-overo-storm-tobi.dt.yaml: pwmleds: 'overo' does not match any of the regexes: '^led(-[0-9a-f]+)?$', 'pinctrl-[0-9]+' From schema: /home/alex/src/linux/leds/Documentation/devicetree/bindings/leds/leds-pwm.yaml DTC arch/arm/boot/dts/omap3-overo-storm-tobiduo.dt.yaml CHECK arch/arm/boot/dts/omap3-overo-storm-tobiduo.dt.yaml /home/alex/build/linux/arch/arm/boot/dts/omap3-overo-storm-tobiduo.dt.yaml: pwmleds: 'overo' does not match any of the regexes: '^led(-[0-9a-f]+)?$', 'pinctrl-[0-9]+' From schema: /home/alex/src/linux/leds/Documentation/devicetree/bindings/leds/leds-pwm.yaml DTC arch/arm/boot/dts/omap3-overo-summit.dt.yaml CHECK arch/arm/boot/dts/omap3-overo-summit.dt.yaml /home/alex/build/linux/arch/arm/boot/dts/omap3-overo-summit.dt.yaml: pwmleds: 'overo' does not match any of the regexes: '^led(-[0-9a-f]+)?$', 'pinctrl-[0-9]+' From schema: /home/alex/src/linux/leds/Documentation/devicetree/bindings/leds/leds-pwm.yaml DTC arch/arm/boot/dts/omap3-overo-tobi.dt.yaml CHECK arch/arm/boot/dts/omap3-overo-tobi.dt.yaml /home/alex/build/linux/arch/arm/boot/dts/omap3-overo-tobi.dt.yaml: pwmleds: 'overo' does not match any of the regexes: '^led(-[0-9a-f]+)?$', 'pinctrl-[0-9]+' From schema: /home/alex/src/linux/leds/Documentation/devicetree/bindings/leds/leds-pwm.yaml DTC arch/arm/boot/dts/omap3-overo-tobiduo.dt.yaml CHECK arch/arm/boot/dts/omap3-overo-tobiduo.dt.yaml /home/alex/build/linux/arch/arm/boot/dts/omap3-overo-tobiduo.dt.yaml: pwmleds: 'overo' does not match any of the regexes: '^led(-[0-9a-f]+)?$', 'pinctrl-[0-9]+' From schema: /home/alex/src/linux/leds/Documentation/devicetree/bindings/leds/leds-pwm.yaml DTC arch/arm/boot/dts/omap4-kc1.dt.yaml CHECK arch/arm/boot/dts/omap4-kc1.dt.yaml /home/alex/build/linux/arch/arm/boot/dts/omap4-kc1.dt.yaml: pwmleds: 'green', 'orange' do not match any of the regexes: '^led(-[0-9a-f]+)?$', 'pinctrl-[0-9]+' From schema: /home/alex/src/linux/leds/Documentation/devicetree/bindings/leds/leds-pwm.yaml DTC arch/arm/boot/dts/omap4-sdp.dt.yaml CHECK arch/arm/boot/dts/omap4-sdp.dt.yaml /home/alex/build/linux/arch/arm/boot/dts/omap4-sdp.dt.yaml: pwmleds: 'charging', 'kpad' do not match any of the regexes: '^led(-[0-9a-f]+)?$', 'pinctrl-[0-9]+' From schema: /home/alex/src/linux/leds/Documentation/devicetree/bindings/leds/leds-pwm.yaml DTC arch/arm/boot/dts/omap4-sdp-es23plus.dt.yaml CHECK arch/arm/boot/dts/omap4-sdp-es23plus.dt.yaml /home/alex/build/linux/arch/arm/boot/dts/omap4-sdp-es23plus.dt.yaml: pwmleds: 'charging', 'kpad' do not match any of the regexes: '^led(-[0-9a-f]+)?$', 'pinctrl-[0-9]+' From schema: /home/alex/src/linux/leds/Documentation/devicetree/bindings/leds/leds-pwm.yaml Signed-off-by: Alexander Dahl Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap3-beagle-xm.dts | 10 +++++----- arch/arm/boot/dts/omap3-overo-base.dtsi | 4 ++-- arch/arm/boot/dts/omap4-kc1.dts | 6 +++--- arch/arm/boot/dts/omap4-sdp.dts | 26 +++++++++++++------------ 4 files changed, 24 insertions(+), 22 deletions(-) diff --git a/arch/arm/boot/dts/omap3-beagle-xm.dts b/arch/arm/boot/dts/omap3-beagle-xm.dts index 252507cf300b..a858ebfa1500 100644 --- a/arch/arm/boot/dts/omap3-beagle-xm.dts +++ b/arch/arm/boot/dts/omap3-beagle-xm.dts @@ -34,26 +34,26 @@ clock-frequency = <26000000>; }; - leds { + led-controller-1 { compatible = "gpio-leds"; - heartbeat { + led-1 { label = "beagleboard::usr0"; gpios = <&gpio5 22 GPIO_ACTIVE_HIGH>; /* 150 -> D6 LED */ linux,default-trigger = "heartbeat"; }; - mmc { + led-2 { label = "beagleboard::usr1"; gpios = <&gpio5 21 GPIO_ACTIVE_HIGH>; /* 149 -> D7 LED */ linux,default-trigger = "mmc0"; }; }; - pwmleds { + led-controller-2 { compatible = "pwm-leds"; - pmu_stat { + led-3 { label = "beagleboard::pmu_stat"; pwms = <&twl_pwmled 1 7812500>; max-brightness = <127>; diff --git a/arch/arm/boot/dts/omap3-overo-base.dtsi b/arch/arm/boot/dts/omap3-overo-base.dtsi index 971d3e250515..006a6d97231c 100644 --- a/arch/arm/boot/dts/omap3-overo-base.dtsi +++ b/arch/arm/boot/dts/omap3-overo-base.dtsi @@ -14,10 +14,10 @@ reg = <0 0>; }; - pwmleds { + led-controller { compatible = "pwm-leds"; - overo { + led-1 { label = "overo:blue:COM"; pwms = <&twl_pwmled 1 7812500>; max-brightness = <127>; diff --git a/arch/arm/boot/dts/omap4-kc1.dts b/arch/arm/boot/dts/omap4-kc1.dts index 31d856b58f8a..e59d17b25a1d 100644 --- a/arch/arm/boot/dts/omap4-kc1.dts +++ b/arch/arm/boot/dts/omap4-kc1.dts @@ -15,16 +15,16 @@ reg = <0x80000000 0x20000000>; /* 512 MB */ }; - pwmleds { + led-controller { compatible = "pwm-leds"; - green { + led-1 { label = "green"; pwms = <&twl_pwm 0 7812500>; max-brightness = <127>; }; - orange { + led-2 { label = "orange"; pwms = <&twl_pwm 1 7812500>; max-brightness = <127>; diff --git a/arch/arm/boot/dts/omap4-sdp.dts b/arch/arm/boot/dts/omap4-sdp.dts index afb49a2d6963..9e976140f34a 100644 --- a/arch/arm/boot/dts/omap4-sdp.dts +++ b/arch/arm/boot/dts/omap4-sdp.dts @@ -45,58 +45,60 @@ regulator-boot-on; }; - leds { + led-controller-1 { compatible = "gpio-leds"; - debug0 { + + led-1 { label = "omap4:green:debug0"; gpios = <&gpio2 29 GPIO_ACTIVE_HIGH>; /* 61 */ }; - debug1 { + led-2 { label = "omap4:green:debug1"; gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>; /* 30 */ }; - debug2 { + led-3 { label = "omap4:green:debug2"; gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; /* 7 */ }; - debug3 { + led-4 { label = "omap4:green:debug3"; gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; /* 8 */ }; - debug4 { + led-5 { label = "omap4:green:debug4"; gpios = <&gpio2 18 GPIO_ACTIVE_HIGH>; /* 50 */ }; - user1 { + led-6 { label = "omap4:blue:user"; gpios = <&gpio6 9 GPIO_ACTIVE_HIGH>; /* 169 */ }; - user2 { + led-7 { label = "omap4:red:user"; gpios = <&gpio6 10 GPIO_ACTIVE_HIGH>; /* 170 */ }; - user3 { + led-8 { label = "omap4:green:user"; gpios = <&gpio5 11 GPIO_ACTIVE_HIGH>; /* 139 */ }; }; - pwmleds { + led-controller-2 { compatible = "pwm-leds"; - kpad { + + led-9 { label = "omap4::keypad"; pwms = <&twl_pwm 0 7812500>; max-brightness = <127>; }; - charging { + led-10 { label = "omap4:green:chrg"; pwms = <&twl_pwmled 0 7812500>; max-brightness = <255>; From 06607cfa0ffe2e8b2a3cb56fb1c2ef39ba0c22a3 Mon Sep 17 00:00:00 2001 From: Carl Philipp Klemm Date: Sun, 8 Nov 2020 19:49:56 +0100 Subject: [PATCH 244/799] ARM: dts: mapphone: separate out xt894 specific things Remove xt894 specific things from motorola-mapphone-common.dtsi and add them to omap4-droid4-xt894.dts and omap4-droid-bionic-xt875.dts as applicable. Signed-off-by: Carl Philipp Klemm [tony@atomide.com: shortened subject, wrapped description] Signed-off-by: Tony Lindgren --- .../boot/dts/motorola-mapphone-common.dtsi | 141 +---------------- .../arm/boot/dts/omap4-droid-bionic-xt875.dts | 30 ++++ arch/arm/boot/dts/omap4-droid4-xt894.dts | 143 ++++++++++++++++++ 3 files changed, 174 insertions(+), 140 deletions(-) diff --git a/arch/arm/boot/dts/motorola-mapphone-common.dtsi b/arch/arm/boot/dts/motorola-mapphone-common.dtsi index 1990239cc6af..0f020a2f0afc 100644 --- a/arch/arm/boot/dts/motorola-mapphone-common.dtsi +++ b/arch/arm/boot/dts/motorola-mapphone-common.dtsi @@ -113,32 +113,9 @@ enable-active-high; }; - gpio_keys { - compatible = "gpio-keys"; - - volume_down { - label = "Volume Down"; - gpios = <&gpio5 26 GPIO_ACTIVE_LOW>; /* gpio154 */ - linux,code = ; - linux,can-disable; - /* Value above 7.95ms for no GPIO hardware debounce */ - debounce-interval = <10>; - }; - - slider { - label = "Keypad Slide"; - gpios = <&gpio4 26 GPIO_ACTIVE_HIGH>; /* gpio122 */ - linux,input-type = ; - linux,code = ; - linux,can-disable; - /* Value above 7.95ms for no GPIO hardware debounce */ - debounce-interval = <10>; - }; - }; - soundcard { compatible = "audio-graph-card"; - label = "Droid 4 Audio"; + label = "Mapphone Audio"; widgets = "Speaker", "Earpiece", @@ -280,80 +257,6 @@ }; }; -&keypad { - keypad,num-rows = <8>; - keypad,num-columns = <8>; - linux,keymap = < - - /* Row 1 */ - MATRIX_KEY(0, 2, KEY_1) - MATRIX_KEY(0, 6, KEY_2) - MATRIX_KEY(2, 3, KEY_3) - MATRIX_KEY(0, 7, KEY_4) - MATRIX_KEY(0, 4, KEY_5) - MATRIX_KEY(5, 5, KEY_6) - MATRIX_KEY(0, 1, KEY_7) - MATRIX_KEY(0, 5, KEY_8) - MATRIX_KEY(0, 0, KEY_9) - MATRIX_KEY(1, 6, KEY_0) - - /* Row 2 */ - MATRIX_KEY(3, 4, KEY_APOSTROPHE) - MATRIX_KEY(7, 6, KEY_Q) - MATRIX_KEY(7, 7, KEY_W) - MATRIX_KEY(7, 2, KEY_E) - MATRIX_KEY(1, 0, KEY_R) - MATRIX_KEY(4, 4, KEY_T) - MATRIX_KEY(1, 2, KEY_Y) - MATRIX_KEY(6, 7, KEY_U) - MATRIX_KEY(2, 2, KEY_I) - MATRIX_KEY(5, 6, KEY_O) - MATRIX_KEY(3, 7, KEY_P) - MATRIX_KEY(6, 5, KEY_BACKSPACE) - - /* Row 3 */ - MATRIX_KEY(5, 4, KEY_TAB) - MATRIX_KEY(5, 7, KEY_A) - MATRIX_KEY(2, 7, KEY_S) - MATRIX_KEY(7, 0, KEY_D) - MATRIX_KEY(2, 6, KEY_F) - MATRIX_KEY(6, 2, KEY_G) - MATRIX_KEY(6, 6, KEY_H) - MATRIX_KEY(1, 4, KEY_J) - MATRIX_KEY(3, 1, KEY_K) - MATRIX_KEY(2, 1, KEY_L) - MATRIX_KEY(4, 6, KEY_ENTER) - - /* Row 4 */ - MATRIX_KEY(3, 6, KEY_LEFTSHIFT) /* KEY_CAPSLOCK */ - MATRIX_KEY(6, 1, KEY_Z) - MATRIX_KEY(7, 4, KEY_X) - MATRIX_KEY(5, 1, KEY_C) - MATRIX_KEY(1, 7, KEY_V) - MATRIX_KEY(2, 4, KEY_B) - MATRIX_KEY(4, 1, KEY_N) - MATRIX_KEY(1, 1, KEY_M) - MATRIX_KEY(3, 5, KEY_COMMA) - MATRIX_KEY(5, 2, KEY_DOT) - MATRIX_KEY(6, 3, KEY_UP) - MATRIX_KEY(7, 3, KEY_OK) - - /* Row 5 */ - MATRIX_KEY(2, 5, KEY_LEFTCTRL) /* KEY_LEFTSHIFT */ - MATRIX_KEY(4, 5, KEY_LEFTALT) /* SYM */ - MATRIX_KEY(6, 0, KEY_MINUS) - MATRIX_KEY(4, 7, KEY_EQUAL) - MATRIX_KEY(1, 5, KEY_SPACE) - MATRIX_KEY(3, 2, KEY_SLASH) - MATRIX_KEY(4, 3, KEY_LEFT) - MATRIX_KEY(5, 3, KEY_DOWN) - MATRIX_KEY(3, 3, KEY_RIGHT) - - /* Side buttons, KEY_VOLUMEDOWN and KEY_PWER are on CPCAP? */ - MATRIX_KEY(5, 0, KEY_VOLUMEUP) - >; -}; - &mmc1 { vmmc-supply = <&vwlan2>; bus-width = <4>; @@ -393,34 +296,6 @@ }; }; -&i2c1 { - led-controller@38 { - compatible = "ti,lm3532"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x38>; - - enable-gpios = <&gpio6 12 GPIO_ACTIVE_HIGH>; - - ramp-up-us = <1024>; - ramp-down-us = <8193>; - - backlight_led: led@0 { - reg = <0>; - led-sources = <2>; - ti,led-mode = <0>; - label = ":backlight"; - }; - - led@1 { - reg = <1>; - led-sources = <1>; - ti,led-mode = <0>; - label = ":kbd_backlight"; - }; - }; -}; - &i2c2 { touchscreen@4a { compatible = "atmel,maxtouch"; @@ -794,20 +669,6 @@ "0", "0", "-1"; }; - - lis3dh: accelerometer@18 { - compatible = "st,lis3dh-accel"; - reg = <0x18>; - - vdd-supply = <&vhvio>; - - interrupt-parent = <&gpio2>; - interrupts = <2 IRQ_TYPE_EDGE_BOTH>; /* gpio34 */ - - rotation-matrix = "0", "-1", "0", - "1", "0", "0", - "0", "0", "1"; - }; }; &mcbsp2 { diff --git a/arch/arm/boot/dts/omap4-droid-bionic-xt875.dts b/arch/arm/boot/dts/omap4-droid-bionic-xt875.dts index ba5c35b7027d..49b2a8d55356 100644 --- a/arch/arm/boot/dts/omap4-droid-bionic-xt875.dts +++ b/arch/arm/boot/dts/omap4-droid-bionic-xt875.dts @@ -7,3 +7,33 @@ model = "Motorola Droid Bionic XT875"; compatible = "motorola,droid-bionic", "ti,omap4430", "ti,omap4"; }; + +&keypad { + keypad,num-rows = <8>; + keypad,num-columns = <8>; + linux,keymap = < + MATRIX_KEY(5, 0, KEY_VOLUMEUP) + MATRIX_KEY(3, 0, KEY_VOLUMEDOWN) + >; +}; + +&i2c1 { + led-controller@38 { + compatible = "ti,lm3532"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x38>; + + enable-gpios = <&gpio6 12 GPIO_ACTIVE_HIGH>; + + ramp-up-us = <1024>; + ramp-down-us = <8193>; + + backlight_led: led@0 { + reg = <0>; + led-sources = <2>; + ti,led-mode = <0>; + label = ":backlight"; + }; + }; +}; diff --git a/arch/arm/boot/dts/omap4-droid4-xt894.dts b/arch/arm/boot/dts/omap4-droid4-xt894.dts index c0d2fd92aea3..3ea4c5b9fd31 100644 --- a/arch/arm/boot/dts/omap4-droid4-xt894.dts +++ b/arch/arm/boot/dts/omap4-droid4-xt894.dts @@ -3,7 +3,150 @@ #include "motorola-mapphone-common.dtsi" +/ { + gpio_keys { + compatible = "gpio-keys"; + + volume_down { + label = "Volume Down"; + gpios = <&gpio5 26 GPIO_ACTIVE_LOW>; /* gpio154 */ + linux,code = ; + linux,can-disable; + /* Value above 7.95ms for no GPIO hardware debounce */ + debounce-interval = <10>; + }; + + slider { + label = "Keypad Slide"; + gpios = <&gpio4 26 GPIO_ACTIVE_HIGH>; /* gpio122 */ + linux,input-type = ; + linux,code = ; + linux,can-disable; + /* Value above 7.95ms for no GPIO hardware debounce */ + debounce-interval = <10>; + }; + }; +}; + / { model = "Motorola Droid 4 XT894"; compatible = "motorola,droid4", "ti,omap4430", "ti,omap4"; }; + +&keypad { + keypad,num-rows = <8>; + keypad,num-columns = <8>; + linux,keymap = < + + /* Row 1 */ + MATRIX_KEY(0, 2, KEY_1) + MATRIX_KEY(0, 6, KEY_2) + MATRIX_KEY(2, 3, KEY_3) + MATRIX_KEY(0, 7, KEY_4) + MATRIX_KEY(0, 4, KEY_5) + MATRIX_KEY(5, 5, KEY_6) + MATRIX_KEY(0, 1, KEY_7) + MATRIX_KEY(0, 5, KEY_8) + MATRIX_KEY(0, 0, KEY_9) + MATRIX_KEY(1, 6, KEY_0) + + /* Row 2 */ + MATRIX_KEY(3, 4, KEY_APOSTROPHE) + MATRIX_KEY(7, 6, KEY_Q) + MATRIX_KEY(7, 7, KEY_W) + MATRIX_KEY(7, 2, KEY_E) + MATRIX_KEY(1, 0, KEY_R) + MATRIX_KEY(4, 4, KEY_T) + MATRIX_KEY(1, 2, KEY_Y) + MATRIX_KEY(6, 7, KEY_U) + MATRIX_KEY(2, 2, KEY_I) + MATRIX_KEY(5, 6, KEY_O) + MATRIX_KEY(3, 7, KEY_P) + MATRIX_KEY(6, 5, KEY_BACKSPACE) + + /* Row 3 */ + MATRIX_KEY(5, 4, KEY_TAB) + MATRIX_KEY(5, 7, KEY_A) + MATRIX_KEY(2, 7, KEY_S) + MATRIX_KEY(7, 0, KEY_D) + MATRIX_KEY(2, 6, KEY_F) + MATRIX_KEY(6, 2, KEY_G) + MATRIX_KEY(6, 6, KEY_H) + MATRIX_KEY(1, 4, KEY_J) + MATRIX_KEY(3, 1, KEY_K) + MATRIX_KEY(2, 1, KEY_L) + MATRIX_KEY(4, 6, KEY_ENTER) + + /* Row 4 */ + MATRIX_KEY(3, 6, KEY_LEFTSHIFT) /* KEY_CAPSLOCK */ + MATRIX_KEY(6, 1, KEY_Z) + MATRIX_KEY(7, 4, KEY_X) + MATRIX_KEY(5, 1, KEY_C) + MATRIX_KEY(1, 7, KEY_V) + MATRIX_KEY(2, 4, KEY_B) + MATRIX_KEY(4, 1, KEY_N) + MATRIX_KEY(1, 1, KEY_M) + MATRIX_KEY(3, 5, KEY_COMMA) + MATRIX_KEY(5, 2, KEY_DOT) + MATRIX_KEY(6, 3, KEY_UP) + MATRIX_KEY(7, 3, KEY_OK) + + /* Row 5 */ + MATRIX_KEY(2, 5, KEY_LEFTCTRL) /* KEY_LEFTSHIFT */ + MATRIX_KEY(4, 5, KEY_LEFTALT) /* SYM */ + MATRIX_KEY(6, 0, KEY_MINUS) + MATRIX_KEY(4, 7, KEY_EQUAL) + MATRIX_KEY(1, 5, KEY_SPACE) + MATRIX_KEY(3, 2, KEY_SLASH) + MATRIX_KEY(4, 3, KEY_LEFT) + MATRIX_KEY(5, 3, KEY_DOWN) + MATRIX_KEY(3, 3, KEY_RIGHT) + + /* Side buttons, KEY_VOLUMEDOWN and KEY_PWER are on CPCAP? */ + MATRIX_KEY(5, 0, KEY_VOLUMEUP) + >; +}; + +&i2c1 { + led-controller@38 { + compatible = "ti,lm3532"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x38>; + + enable-gpios = <&gpio6 12 GPIO_ACTIVE_HIGH>; + + ramp-up-us = <1024>; + ramp-down-us = <8193>; + + backlight_led: led@0 { + reg = <0>; + led-sources = <2>; + ti,led-mode = <0>; + label = ":backlight"; + }; + + led@1 { + reg = <1>; + led-sources = <1>; + ti,led-mode = <0>; + label = ":kbd_backlight"; + }; + }; +}; + +&i2c4 { + lis3dh: accelerometer@18 { + compatible = "st,lis3dh-accel"; + reg = <0x18>; + + vdd-supply = <&vhvio>; + + interrupt-parent = <&gpio2>; + interrupts = <2 IRQ_TYPE_EDGE_BOTH>; /* gpio34 */ + + rotation-matrix = "0", "-1", "0", + "1", "0", "0", + "0", "0", "1"; + }; +}; From 5a7b624037625adcfd247299aa6f9d9257c97371 Mon Sep 17 00:00:00 2001 From: Carl Philipp Klemm Date: Sun, 8 Nov 2020 19:43:39 +0100 Subject: [PATCH 245/799] ARM: dts: xt875: add section for kionix kxtf9 Add section for kionix kxtf9. Signed-off-by: Carl Philipp Klemm [tony@atomide.com: removed extra header from description] Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap4-droid-bionic-xt875.dts | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm/boot/dts/omap4-droid-bionic-xt875.dts b/arch/arm/boot/dts/omap4-droid-bionic-xt875.dts index 49b2a8d55356..ccf03a743678 100644 --- a/arch/arm/boot/dts/omap4-droid-bionic-xt875.dts +++ b/arch/arm/boot/dts/omap4-droid-bionic-xt875.dts @@ -37,3 +37,19 @@ }; }; }; + +&i2c4 { + kxtf9: accelerometer@f { + compatible = "kionix,kxtf9"; + reg = <0x0f>; + + vdd-supply = <&vhvio>; + + interrupt-parent = <&gpio2>; + interrupts = <2 IRQ_TYPE_EDGE_RISING>; + + rotation-matrix = "0", "-1", "0", + "1", "0", "0", + "0", "0", "1"; + }; +}; From 7e5258b0b79d8be916abd064b5f4aa2715580478 Mon Sep 17 00:00:00 2001 From: Jordan Crouse Date: Mon, 9 Nov 2020 11:47:28 -0700 Subject: [PATCH 246/799] arm: dts: qcom: sm845: Set the compatible string for the GPU SMMU Set the qcom,adreno-smmu compatible string for the GPU SMMU to enable split pagetables and per-instance pagetables for drm/msm. Signed-off-by: Jordan Crouse Signed-off-by: Rob Clark Reviewed-by: Bjorn Andersson Link: https://lore.kernel.org/r/20201109184728.2463097-5-jcrouse@codeaurora.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi | 9 +++++++++ arch/arm64/boot/dts/qcom/sdm845.dtsi | 2 +- 2 files changed, 10 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi b/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi index 64fc1bfd66fa..39f23cdcbd02 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi @@ -633,6 +633,15 @@ ap_ts_i2c: &i2c14 { status = "okay"; }; +/* + * Cheza fw does not properly program the GPU aperture to allow the + * GPU to update the SMMU pagetables for context switches. Work + * around this by dropping the "qcom,adreno-smmu" compat string. + */ +&adreno_smmu { + compatible = "qcom,sdm845-smmu-v2", "qcom,smmu-v2"; +}; + &mss_pil { iommus = <&apps_smmu 0x781 0x0>, <&apps_smmu 0x724 0x3>; diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index aca7e9c954e0..895e7038cdc6 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -4106,7 +4106,7 @@ }; adreno_smmu: iommu@5040000 { - compatible = "qcom,sdm845-smmu-v2", "qcom,smmu-v2"; + compatible = "qcom,sdm845-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2"; reg = <0 0x5040000 0 0x10000>; #iommu-cells = <1>; #global-interrupts = <2>; From c42c3f05faa072d7833fc37b92f3c117128ca98a Mon Sep 17 00:00:00 2001 From: Rob Clark Date: Sat, 5 Sep 2020 13:04:26 -0700 Subject: [PATCH 247/799] arm: dts: qcom: sc7180: Set the compatible string for the GPU SMMU Set the qcom,adreno-smmu compatible string for the GPU SMMU to enable split pagetables and per-instance pagetables for drm/msm. Signed-off-by: Rob Clark Reviewed-by: Bjorn Andersson Link: https://lore.kernel.org/r/20200905200454.240929-21-robdclark@gmail.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc7180.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index f5ef2cb6e68c..861abc399de9 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -2062,7 +2062,7 @@ }; adreno_smmu: iommu@5040000 { - compatible = "qcom,sc7180-smmu-v2", "qcom,smmu-v2"; + compatible = "qcom,sc7180-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2"; reg = <0 0x05040000 0 0x10000>; #iommu-cells = <1>; #global-interrupts = <2>; From 5334df3a4bc50f422684291d045aa2c821d7ff0b Mon Sep 17 00:00:00 2001 From: Sylwester Nawrocki Date: Wed, 4 Nov 2020 11:36:55 +0100 Subject: [PATCH 248/799] ARM: dts: exynos: Add interconnect properties to Exynos4412 bus nodes MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This patch adds the following properties for Exynos4412 interconnect bus nodes: - interconnects: to declare connections between nodes in order to guarantee PM QoS requirements between nodes, - #interconnect-cells: required by the interconnect framework, - samsung,data-clk-ratio: which allows to specify minimum data clock frequency corresponding to requested bandwidth for each bus. Note that #interconnect-cells is always zero and node IDs are not hardcoded anywhere. Signed-off-by: Artur Świgoń Signed-off-by: Sylwester Nawrocki Tested-by: Chanwoo Choi Reviewed-by: Chanwoo Choi Link: https://lore.kernel.org/r/20201104103657.18007-6-s.nawrocki@samsung.com Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos4412.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/boot/dts/exynos4412.dtsi b/arch/arm/boot/dts/exynos4412.dtsi index fa8e8d6bc4d5..05e215621e7b 100644 --- a/arch/arm/boot/dts/exynos4412.dtsi +++ b/arch/arm/boot/dts/exynos4412.dtsi @@ -383,6 +383,8 @@ clocks = <&clock CLK_DIV_DMC>; clock-names = "bus"; operating-points-v2 = <&bus_dmc_opp_table>; + samsung,data-clock-ratio = <4>; + #interconnect-cells = <0>; status = "disabled"; }; @@ -450,6 +452,8 @@ clocks = <&clock CLK_DIV_GDL>; clock-names = "bus"; operating-points-v2 = <&bus_leftbus_opp_table>; + interconnects = <&bus_dmc>; + #interconnect-cells = <0>; status = "disabled"; }; @@ -466,6 +470,8 @@ clocks = <&clock CLK_ACLK160>; clock-names = "bus"; operating-points-v2 = <&bus_display_opp_table>; + interconnects = <&bus_leftbus &bus_dmc>; + #interconnect-cells = <0>; status = "disabled"; }; From 246c1a37f5ff897edec750b6d9325860143cefde Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Artur=20=C5=9Awigo=C5=84?= Date: Wed, 4 Nov 2020 11:36:56 +0100 Subject: [PATCH 249/799] ARM: dts: exynos: Add interconnects to Exynos4412 mixer MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This patch adds an 'interconnects' property to Exynos4412 DTS in order to declare the interconnect path used by the mixer. Please note that the 'interconnect-names' property is not needed when there is only one path in 'interconnects', in which case calling of_icc_get() with a NULL name simply returns the right path. Signed-off-by: Artur Świgoń Signed-off-by: Sylwester Nawrocki Tested-by: Chanwoo Choi Reviewed-by: Chanwoo Choi Link: https://lore.kernel.org/r/20201104103657.18007-7-s.nawrocki@samsung.com Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos4412.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/exynos4412.dtsi b/arch/arm/boot/dts/exynos4412.dtsi index 05e215621e7b..bcb87c5dca88 100644 --- a/arch/arm/boot/dts/exynos4412.dtsi +++ b/arch/arm/boot/dts/exynos4412.dtsi @@ -773,6 +773,7 @@ clock-names = "mixer", "hdmi", "sclk_hdmi", "vp"; clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>, <&clock CLK_VP>; + interconnects = <&bus_display &bus_dmc>; }; &pmu { From b357e6aa41011c003b18637024243bf37a3c7369 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 5 Nov 2020 19:41:08 +0100 Subject: [PATCH 250/799] ARM: dts: exynos: use hyphens in Exynos3250 node names Use hyphens instead of underscores in the Exynos3250 node names which is expected by naming convention, multiple dtschema files and pointed out by dtc W=2 builds. Use also generic "ppmu" node name for PPMU nodes to match Devicetree specification. Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20201105184506.215648-1-krzk@kernel.org --- arch/arm/boot/dts/exynos3250.dtsi | 48 +++++++++++++++---------------- 1 file changed, 24 insertions(+), 24 deletions(-) diff --git a/arch/arm/boot/dts/exynos3250.dtsi b/arch/arm/boot/dts/exynos3250.dtsi index 75ed82600ec8..c5390ca5a87d 100644 --- a/arch/arm/boot/dts/exynos3250.dtsi +++ b/arch/arm/boot/dts/exynos3250.dtsi @@ -691,25 +691,25 @@ status = "disabled"; }; - ppmu_dmc0: ppmu_dmc0@106a0000 { + ppmu_dmc0: ppmu@106a0000 { compatible = "samsung,exynos-ppmu"; reg = <0x106a0000 0x2000>; status = "disabled"; }; - ppmu_dmc1: ppmu_dmc1@106b0000 { + ppmu_dmc1: ppmu@106b0000 { compatible = "samsung,exynos-ppmu"; reg = <0x106b0000 0x2000>; status = "disabled"; }; - ppmu_cpu: ppmu_cpu@106c0000 { + ppmu_cpu: ppmu@106c0000 { compatible = "samsung,exynos-ppmu"; reg = <0x106c0000 0x2000>; status = "disabled"; }; - ppmu_rightbus: ppmu_rightbus@112a0000 { + ppmu_rightbus: ppmu@112a0000 { compatible = "samsung,exynos-ppmu"; reg = <0x112a0000 0x2000>; clocks = <&cmu CLK_PPMURIGHT>; @@ -717,7 +717,7 @@ status = "disabled"; }; - ppmu_leftbus: ppmu_leftbus0@116a0000 { + ppmu_leftbus: ppmu@116a0000 { compatible = "samsung,exynos-ppmu"; reg = <0x116a0000 0x2000>; clocks = <&cmu CLK_PPMULEFT>; @@ -725,7 +725,7 @@ status = "disabled"; }; - ppmu_camif: ppmu_camif@11ac0000 { + ppmu_camif: ppmu@11ac0000 { compatible = "samsung,exynos-ppmu"; reg = <0x11ac0000 0x2000>; clocks = <&cmu CLK_PPMUCAMIF>; @@ -733,7 +733,7 @@ status = "disabled"; }; - ppmu_lcd0: ppmu_lcd0@11e40000 { + ppmu_lcd0: ppmu@11e40000 { compatible = "samsung,exynos-ppmu"; reg = <0x11e40000 0x2000>; clocks = <&cmu CLK_PPMULCD0>; @@ -741,7 +741,7 @@ status = "disabled"; }; - ppmu_fsys: ppmu_fsys@12630000 { + ppmu_fsys: ppmu@12630000 { compatible = "samsung,exynos-ppmu"; reg = <0x12630000 0x2000>; clocks = <&cmu CLK_PPMUFILE>; @@ -749,7 +749,7 @@ status = "disabled"; }; - ppmu_g3d: ppmu_g3d@13220000 { + ppmu_g3d: ppmu@13220000 { compatible = "samsung,exynos-ppmu"; reg = <0x13220000 0x2000>; clocks = <&cmu CLK_PPMUG3D>; @@ -757,7 +757,7 @@ status = "disabled"; }; - ppmu_mfc: ppmu_mfc@13660000 { + ppmu_mfc: ppmu@13660000 { compatible = "samsung,exynos-ppmu"; reg = <0x13660000 0x2000>; clocks = <&cmu CLK_PPMUMFC_L>; @@ -765,7 +765,7 @@ status = "disabled"; }; - bus_dmc: bus_dmc { + bus_dmc: bus-dmc { compatible = "samsung,exynos-bus"; clocks = <&cmu_dmc CLK_DIV_DMC>; clock-names = "bus"; @@ -773,7 +773,7 @@ status = "disabled"; }; - bus_dmc_opp_table: opp_table1 { + bus_dmc_opp_table: opp-table1 { compatible = "operating-points-v2"; opp-50000000 { @@ -798,7 +798,7 @@ }; }; - bus_leftbus: bus_leftbus { + bus_leftbus: bus-leftbus { compatible = "samsung,exynos-bus"; clocks = <&cmu CLK_DIV_GDL>; clock-names = "bus"; @@ -806,7 +806,7 @@ status = "disabled"; }; - bus_rightbus: bus_rightbus { + bus_rightbus: bus-rightbus { compatible = "samsung,exynos-bus"; clocks = <&cmu CLK_DIV_GDR>; clock-names = "bus"; @@ -814,7 +814,7 @@ status = "disabled"; }; - bus_lcd0: bus_lcd0 { + bus_lcd0: bus-lcd0 { compatible = "samsung,exynos-bus"; clocks = <&cmu CLK_DIV_ACLK_160>; clock-names = "bus"; @@ -822,7 +822,7 @@ status = "disabled"; }; - bus_fsys: bus_fsys { + bus_fsys: bus-fsys { compatible = "samsung,exynos-bus"; clocks = <&cmu CLK_DIV_ACLK_200>; clock-names = "bus"; @@ -830,7 +830,7 @@ status = "disabled"; }; - bus_mcuisp: bus_mcuisp { + bus_mcuisp: bus-mcuisp { compatible = "samsung,exynos-bus"; clocks = <&cmu CLK_DIV_ACLK_400_MCUISP>; clock-names = "bus"; @@ -838,7 +838,7 @@ status = "disabled"; }; - bus_isp: bus_isp { + bus_isp: bus-isp { compatible = "samsung,exynos-bus"; clocks = <&cmu CLK_DIV_ACLK_266>; clock-names = "bus"; @@ -846,7 +846,7 @@ status = "disabled"; }; - bus_peril: bus_peril { + bus_peril: bus-peril { compatible = "samsung,exynos-bus"; clocks = <&cmu CLK_DIV_ACLK_100>; clock-names = "bus"; @@ -854,7 +854,7 @@ status = "disabled"; }; - bus_mfc: bus_mfc { + bus_mfc: bus-mfc { compatible = "samsung,exynos-bus"; clocks = <&cmu CLK_SCLK_MFC>; clock-names = "bus"; @@ -862,7 +862,7 @@ status = "disabled"; }; - bus_leftbus_opp_table: opp_table2 { + bus_leftbus_opp_table: opp-table2 { compatible = "operating-points-v2"; opp-50000000 { @@ -887,7 +887,7 @@ }; }; - bus_mcuisp_opp_table: opp_table3 { + bus_mcuisp_opp_table: opp-table3 { compatible = "operating-points-v2"; opp-50000000 { @@ -907,7 +907,7 @@ }; }; - bus_isp_opp_table: opp_table4 { + bus_isp_opp_table: opp-table4 { compatible = "operating-points-v2"; opp-50000000 { @@ -927,7 +927,7 @@ }; }; - bus_peril_opp_table: opp_table5 { + bus_peril_opp_table: opp-table5 { compatible = "operating-points-v2"; opp-50000000 { From 1c6831b472f2e31c42eff579f35a5dd2b5da5435 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 5 Nov 2020 19:45:02 +0100 Subject: [PATCH 251/799] ARM: dts: exynos: use hyphens in Exynos4 node names Use hyphens instead of underscores in the Exynos4210 and Exynos4412 node names which is expected by naming convention, multiple dtschema files and pointed out by dtc W=2 builds. Use also generic "ppmu" node name for PPMU nodes to match Devicetree specification. Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20201105184506.215648-2-krzk@kernel.org --- arch/arm/boot/dts/exynos4.dtsi | 26 +++++++++++----------- arch/arm/boot/dts/exynos4210.dtsi | 36 +++++++++++++++---------------- arch/arm/boot/dts/exynos4412.dtsi | 18 ++++++++-------- 3 files changed, 40 insertions(+), 40 deletions(-) diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi index a1e54449f33f..eab77a66ae8f 100644 --- a/arch/arm/boot/dts/exynos4.dtsi +++ b/arch/arm/boot/dts/exynos4.dtsi @@ -782,7 +782,7 @@ status = "disabled"; }; - ppmu_dmc0: ppmu_dmc0@106a0000 { + ppmu_dmc0: ppmu@106a0000 { compatible = "samsung,exynos-ppmu"; reg = <0x106a0000 0x2000>; clocks = <&clock CLK_PPMUDMC0>; @@ -790,7 +790,7 @@ status = "disabled"; }; - ppmu_dmc1: ppmu_dmc1@106b0000 { + ppmu_dmc1: ppmu@106b0000 { compatible = "samsung,exynos-ppmu"; reg = <0x106b0000 0x2000>; clocks = <&clock CLK_PPMUDMC1>; @@ -798,7 +798,7 @@ status = "disabled"; }; - ppmu_cpu: ppmu_cpu@106c0000 { + ppmu_cpu: ppmu@106c0000 { compatible = "samsung,exynos-ppmu"; reg = <0x106c0000 0x2000>; clocks = <&clock CLK_PPMUCPU>; @@ -806,7 +806,7 @@ status = "disabled"; }; - ppmu_rightbus: ppmu_rightbus@112a0000 { + ppmu_rightbus: ppmu@112a0000 { compatible = "samsung,exynos-ppmu"; reg = <0x112a0000 0x2000>; clocks = <&clock CLK_PPMURIGHT>; @@ -814,7 +814,7 @@ status = "disabled"; }; - ppmu_leftbus: ppmu_leftbus0@116a0000 { + ppmu_leftbus: ppmu@116a0000 { compatible = "samsung,exynos-ppmu"; reg = <0x116a0000 0x2000>; clocks = <&clock CLK_PPMULEFT>; @@ -822,7 +822,7 @@ status = "disabled"; }; - ppmu_camif: ppmu_camif@11ac0000 { + ppmu_camif: ppmu@11ac0000 { compatible = "samsung,exynos-ppmu"; reg = <0x11ac0000 0x2000>; clocks = <&clock CLK_PPMUCAMIF>; @@ -830,7 +830,7 @@ status = "disabled"; }; - ppmu_lcd0: ppmu_lcd0@11e40000 { + ppmu_lcd0: ppmu@11e40000 { compatible = "samsung,exynos-ppmu"; reg = <0x11e40000 0x2000>; clocks = <&clock CLK_PPMULCD0>; @@ -838,13 +838,13 @@ status = "disabled"; }; - ppmu_fsys: ppmu_g3d@12630000 { + ppmu_fsys: ppmu@12630000 { compatible = "samsung,exynos-ppmu"; reg = <0x12630000 0x2000>; status = "disabled"; }; - ppmu_image: ppmu_image@12aa0000 { + ppmu_image: ppmu@12aa0000 { compatible = "samsung,exynos-ppmu"; reg = <0x12aa0000 0x2000>; clocks = <&clock CLK_PPMUIMAGE>; @@ -852,7 +852,7 @@ status = "disabled"; }; - ppmu_tv: ppmu_tv@12e40000 { + ppmu_tv: ppmu@12e40000 { compatible = "samsung,exynos-ppmu"; reg = <0x12e40000 0x2000>; clocks = <&clock CLK_PPMUTV>; @@ -860,7 +860,7 @@ status = "disabled"; }; - ppmu_g3d: ppmu_g3d@13220000 { + ppmu_g3d: ppmu@13220000 { compatible = "samsung,exynos-ppmu"; reg = <0x13220000 0x2000>; clocks = <&clock CLK_PPMUG3D>; @@ -868,7 +868,7 @@ status = "disabled"; }; - ppmu_mfc_left: ppmu_mfc_left@13660000 { + ppmu_mfc_left: ppmu@13660000 { compatible = "samsung,exynos-ppmu"; reg = <0x13660000 0x2000>; clocks = <&clock CLK_PPMUMFC_L>; @@ -876,7 +876,7 @@ status = "disabled"; }; - ppmu_mfc_right: ppmu_mfc_right@13670000 { + ppmu_mfc_right: ppmu@13670000 { compatible = "samsung,exynos-ppmu"; reg = <0x13670000 0x2000>; clocks = <&clock CLK_PPMUMFC_R>; diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi index fddc661ded28..70baad9b11f0 100644 --- a/arch/arm/boot/dts/exynos4210.dtsi +++ b/arch/arm/boot/dts/exynos4210.dtsi @@ -168,13 +168,13 @@ iommus = <&sysmmu_g2d>; }; - ppmu_acp: ppmu_acp@10ae0000 { + ppmu_acp: ppmu@10ae0000 { compatible = "samsung,exynos-ppmu"; reg = <0x10ae0000 0x2000>; status = "disabled"; }; - ppmu_lcd1: ppmu_lcd1@12240000 { + ppmu_lcd1: ppmu@12240000 { compatible = "samsung,exynos-ppmu"; reg = <0x12240000 0x2000>; clocks = <&clock CLK_PPMULCD1>; @@ -204,7 +204,7 @@ #iommu-cells = <0>; }; - bus_dmc: bus_dmc { + bus_dmc: bus-dmc { compatible = "samsung,exynos-bus"; clocks = <&clock CLK_DIV_DMC>; clock-names = "bus"; @@ -212,7 +212,7 @@ status = "disabled"; }; - bus_acp: bus_acp { + bus_acp: bus-acp { compatible = "samsung,exynos-bus"; clocks = <&clock CLK_DIV_ACP>; clock-names = "bus"; @@ -220,7 +220,7 @@ status = "disabled"; }; - bus_peri: bus_peri { + bus_peri: bus-peri { compatible = "samsung,exynos-bus"; clocks = <&clock CLK_ACLK100>; clock-names = "bus"; @@ -228,7 +228,7 @@ status = "disabled"; }; - bus_fsys: bus_fsys { + bus_fsys: bus-fsys { compatible = "samsung,exynos-bus"; clocks = <&clock CLK_ACLK133>; clock-names = "bus"; @@ -236,7 +236,7 @@ status = "disabled"; }; - bus_display: bus_display { + bus_display: bus-display { compatible = "samsung,exynos-bus"; clocks = <&clock CLK_ACLK160>; clock-names = "bus"; @@ -244,7 +244,7 @@ status = "disabled"; }; - bus_lcd0: bus_lcd0 { + bus_lcd0: bus-lcd0 { compatible = "samsung,exynos-bus"; clocks = <&clock CLK_ACLK200>; clock-names = "bus"; @@ -252,7 +252,7 @@ status = "disabled"; }; - bus_leftbus: bus_leftbus { + bus_leftbus: bus-leftbus { compatible = "samsung,exynos-bus"; clocks = <&clock CLK_DIV_GDL>; clock-names = "bus"; @@ -260,7 +260,7 @@ status = "disabled"; }; - bus_rightbus: bus_rightbus { + bus_rightbus: bus-rightbus { compatible = "samsung,exynos-bus"; clocks = <&clock CLK_DIV_GDR>; clock-names = "bus"; @@ -268,7 +268,7 @@ status = "disabled"; }; - bus_mfc: bus_mfc { + bus_mfc: bus-mfc { compatible = "samsung,exynos-bus"; clocks = <&clock CLK_SCLK_MFC>; clock-names = "bus"; @@ -276,7 +276,7 @@ status = "disabled"; }; - bus_dmc_opp_table: opp_table1 { + bus_dmc_opp_table: opp-table1 { compatible = "operating-points-v2"; opp-shared; @@ -295,7 +295,7 @@ }; }; - bus_acp_opp_table: opp_table2 { + bus_acp_opp_table: opp-table2 { compatible = "operating-points-v2"; opp-shared; @@ -310,7 +310,7 @@ }; }; - bus_peri_opp_table: opp_table3 { + bus_peri_opp_table: opp-table3 { compatible = "operating-points-v2"; opp-shared; @@ -322,7 +322,7 @@ }; }; - bus_fsys_opp_table: opp_table4 { + bus_fsys_opp_table: opp-table4 { compatible = "operating-points-v2"; opp-shared; @@ -334,7 +334,7 @@ }; }; - bus_display_opp_table: opp_table5 { + bus_display_opp_table: opp-table5 { compatible = "operating-points-v2"; opp-shared; @@ -349,7 +349,7 @@ }; }; - bus_leftbus_opp_table: opp_table6 { + bus_leftbus_opp_table: opp-table6 { compatible = "operating-points-v2"; opp-shared; @@ -463,7 +463,7 @@ "ppmmu3"; operating-points-v2 = <&gpu_opp_table>; - gpu_opp_table: opp_table { + gpu_opp_table: opp-table { compatible = "operating-points-v2"; opp-160000000 { diff --git a/arch/arm/boot/dts/exynos4412.dtsi b/arch/arm/boot/dts/exynos4412.dtsi index bcb87c5dca88..96a4b01bd71b 100644 --- a/arch/arm/boot/dts/exynos4412.dtsi +++ b/arch/arm/boot/dts/exynos4412.dtsi @@ -378,7 +378,7 @@ #iommu-cells = <0>; }; - bus_dmc: bus_dmc { + bus_dmc: bus-dmc { compatible = "samsung,exynos-bus"; clocks = <&clock CLK_DIV_DMC>; clock-names = "bus"; @@ -388,7 +388,7 @@ status = "disabled"; }; - bus_acp: bus_acp { + bus_acp: bus-acp { compatible = "samsung,exynos-bus"; clocks = <&clock CLK_DIV_ACP>; clock-names = "bus"; @@ -396,7 +396,7 @@ status = "disabled"; }; - bus_c2c: bus_c2c { + bus_c2c: bus-c2c { compatible = "samsung,exynos-bus"; clocks = <&clock CLK_DIV_C2C>; clock-names = "bus"; @@ -447,7 +447,7 @@ }; }; - bus_leftbus: bus_leftbus { + bus_leftbus: bus-leftbus { compatible = "samsung,exynos-bus"; clocks = <&clock CLK_DIV_GDL>; clock-names = "bus"; @@ -457,7 +457,7 @@ status = "disabled"; }; - bus_rightbus: bus_rightbus { + bus_rightbus: bus-rightbus { compatible = "samsung,exynos-bus"; clocks = <&clock CLK_DIV_GDR>; clock-names = "bus"; @@ -465,7 +465,7 @@ status = "disabled"; }; - bus_display: bus_display { + bus_display: bus-display { compatible = "samsung,exynos-bus"; clocks = <&clock CLK_ACLK160>; clock-names = "bus"; @@ -475,7 +475,7 @@ status = "disabled"; }; - bus_fsys: bus_fsys { + bus_fsys: bus-fsys { compatible = "samsung,exynos-bus"; clocks = <&clock CLK_ACLK133>; clock-names = "bus"; @@ -483,7 +483,7 @@ status = "disabled"; }; - bus_peri: bus_peri { + bus_peri: bus-peri { compatible = "samsung,exynos-bus"; clocks = <&clock CLK_ACLK100>; clock-names = "bus"; @@ -491,7 +491,7 @@ status = "disabled"; }; - bus_mfc: bus_mfc { + bus_mfc: bus-mfc { compatible = "samsung,exynos-bus"; clocks = <&clock CLK_SCLK_MFC>; clock-names = "bus"; From 32f9abc326ee21d8fe01c9979d493c7a92dedd59 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 5 Nov 2020 19:45:03 +0100 Subject: [PATCH 252/799] ARM: dts: exynos: use generic name for max77693 motor in Midas Use a generic name for the max77693 motor driver in Exynos4412 Midas boards to align with Devicetree specification naming convention. Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20201105184506.215648-3-krzk@kernel.org --- arch/arm/boot/dts/exynos4412-midas.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/exynos4412-midas.dtsi b/arch/arm/boot/dts/exynos4412-midas.dtsi index 2be1db0b2387..111c32bae02c 100644 --- a/arch/arm/boot/dts/exynos4412-midas.dtsi +++ b/arch/arm/boot/dts/exynos4412-midas.dtsi @@ -192,7 +192,7 @@ }; }; - max77693_haptic { + motor-driver { compatible = "maxim,max77693-haptic"; haptic-supply = <&ldo26_reg>; pwms = <&pwm 0 38022 0>; From 9b846ba7c1d237476267bc2e05d4920691651ca2 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 5 Nov 2020 19:45:04 +0100 Subject: [PATCH 253/799] ARM: dts: exynos: use hyphens in Exynos5 node names Use hyphens instead of underscores in the Exynos5250 and Exynos542x node names which is expected by naming convention, multiple dtschema files and pointed out by dtc W=2 builds. Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20201105184506.215648-4-krzk@kernel.org --- arch/arm/boot/dts/exynos5250.dtsi | 2 +- arch/arm/boot/dts/exynos5420.dtsi | 36 +++++++++---------- arch/arm/boot/dts/exynos5422-odroid-core.dtsi | 32 ++++++++--------- 3 files changed, 35 insertions(+), 35 deletions(-) diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi index 84677332a5a2..1be1841c374f 100644 --- a/arch/arm/boot/dts/exynos5250.dtsi +++ b/arch/arm/boot/dts/exynos5250.dtsi @@ -70,7 +70,7 @@ }; }; - cpu0_opp_table: opp_table0 { + cpu0_opp_table: opp-table0 { compatible = "operating-points-v2"; opp-shared; diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi index 23a8fd5c8a6e..e23e8ffb093f 100644 --- a/arch/arm/boot/dts/exynos5420.dtsi +++ b/arch/arm/boot/dts/exynos5420.dtsi @@ -42,7 +42,7 @@ * by exynos5420-cpus.dtsi or exynos5422-cpus.dtsi. */ - cluster_a15_opp_table: opp_table0 { + cluster_a15_opp_table: opp-table0 { compatible = "operating-points-v2"; opp-shared; @@ -108,7 +108,7 @@ }; }; - cluster_a7_opp_table: opp_table1 { + cluster_a7_opp_table: opp-table1 { compatible = "operating-points-v2"; opp-shared; @@ -1077,112 +1077,112 @@ #iommu-cells = <0>; }; - bus_wcore: bus_wcore { + bus_wcore: bus-wcore { compatible = "samsung,exynos-bus"; clocks = <&clock CLK_DOUT_ACLK400_WCORE>; clock-names = "bus"; status = "disabled"; }; - bus_noc: bus_noc { + bus_noc: bus-noc { compatible = "samsung,exynos-bus"; clocks = <&clock CLK_DOUT_ACLK100_NOC>; clock-names = "bus"; status = "disabled"; }; - bus_fsys_apb: bus_fsys_apb { + bus_fsys_apb: bus-fsys-apb { compatible = "samsung,exynos-bus"; clocks = <&clock CLK_DOUT_PCLK200_FSYS>; clock-names = "bus"; status = "disabled"; }; - bus_fsys: bus_fsys { + bus_fsys: bus-fsys { compatible = "samsung,exynos-bus"; clocks = <&clock CLK_DOUT_ACLK200_FSYS>; clock-names = "bus"; status = "disabled"; }; - bus_fsys2: bus_fsys2 { + bus_fsys2: bus-fsys2 { compatible = "samsung,exynos-bus"; clocks = <&clock CLK_DOUT_ACLK200_FSYS2>; clock-names = "bus"; status = "disabled"; }; - bus_mfc: bus_mfc { + bus_mfc: bus-mfc { compatible = "samsung,exynos-bus"; clocks = <&clock CLK_DOUT_ACLK333>; clock-names = "bus"; status = "disabled"; }; - bus_gen: bus_gen { + bus_gen: bus-gen { compatible = "samsung,exynos-bus"; clocks = <&clock CLK_DOUT_ACLK266>; clock-names = "bus"; status = "disabled"; }; - bus_peri: bus_peri { + bus_peri: bus-peri { compatible = "samsung,exynos-bus"; clocks = <&clock CLK_DOUT_ACLK66>; clock-names = "bus"; status = "disabled"; }; - bus_g2d: bus_g2d { + bus_g2d: bus-g2d { compatible = "samsung,exynos-bus"; clocks = <&clock CLK_DOUT_ACLK333_G2D>; clock-names = "bus"; status = "disabled"; }; - bus_g2d_acp: bus_g2d_acp { + bus_g2d_acp: bus-g2d-acp { compatible = "samsung,exynos-bus"; clocks = <&clock CLK_DOUT_ACLK266_G2D>; clock-names = "bus"; status = "disabled"; }; - bus_jpeg: bus_jpeg { + bus_jpeg: bus-jpeg { compatible = "samsung,exynos-bus"; clocks = <&clock CLK_DOUT_ACLK300_JPEG>; clock-names = "bus"; status = "disabled"; }; - bus_jpeg_apb: bus_jpeg_apb { + bus_jpeg_apb: bus-jpeg-apb { compatible = "samsung,exynos-bus"; clocks = <&clock CLK_DOUT_ACLK166>; clock-names = "bus"; status = "disabled"; }; - bus_disp1_fimd: bus_disp1_fimd { + bus_disp1_fimd: bus-disp1-fimd { compatible = "samsung,exynos-bus"; clocks = <&clock CLK_DOUT_ACLK300_DISP1>; clock-names = "bus"; status = "disabled"; }; - bus_disp1: bus_disp1 { + bus_disp1: bus-disp1 { compatible = "samsung,exynos-bus"; clocks = <&clock CLK_DOUT_ACLK400_DISP1>; clock-names = "bus"; status = "disabled"; }; - bus_gscl_scaler: bus_gscl_scaler { + bus_gscl_scaler: bus-gscl-scaler { compatible = "samsung,exynos-bus"; clocks = <&clock CLK_DOUT_ACLK300_GSCL>; clock-names = "bus"; status = "disabled"; }; - bus_mscl: bus_mscl { + bus_mscl: bus-mscl { compatible = "samsung,exynos-bus"; clocks = <&clock CLK_DOUT_ACLK400_MSCL>; clock-names = "bus"; diff --git a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi index 25fb6331c75e..d0df560eb0db 100644 --- a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi +++ b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi @@ -35,7 +35,7 @@ }; }; - bus_wcore_opp_table: opp_table2 { + bus_wcore_opp_table: opp-table2 { compatible = "operating-points-v2"; /* derived from 532MHz MPLL */ @@ -61,7 +61,7 @@ }; }; - bus_noc_opp_table: opp_table3 { + bus_noc_opp_table: opp-table3 { compatible = "operating-points-v2"; /* derived from 666MHz CPLL */ @@ -79,7 +79,7 @@ }; }; - bus_fsys_apb_opp_table: opp_table4 { + bus_fsys_apb_opp_table: opp-table4 { compatible = "operating-points-v2"; /* derived from 666MHz CPLL */ @@ -91,7 +91,7 @@ }; }; - bus_fsys2_opp_table: opp_table5 { + bus_fsys2_opp_table: opp-table5 { compatible = "operating-points-v2"; /* derived from 600MHz DPLL */ @@ -106,7 +106,7 @@ }; }; - bus_mfc_opp_table: opp_table6 { + bus_mfc_opp_table: opp-table6 { compatible = "operating-points-v2"; /* derived from 666MHz CPLL */ @@ -127,7 +127,7 @@ }; }; - bus_gen_opp_table: opp_table7 { + bus_gen_opp_table: opp-table7 { compatible = "operating-points-v2"; /* derived from 532MHz MPLL */ @@ -145,7 +145,7 @@ }; }; - bus_peri_opp_table: opp_table8 { + bus_peri_opp_table: opp-table8 { compatible = "operating-points-v2"; /* derived from 666MHz CPLL */ @@ -154,7 +154,7 @@ }; }; - bus_g2d_opp_table: opp_table9 { + bus_g2d_opp_table: opp-table9 { compatible = "operating-points-v2"; /* derived from 666MHz CPLL */ @@ -175,7 +175,7 @@ }; }; - bus_g2d_acp_opp_table: opp_table10 { + bus_g2d_acp_opp_table: opp-table10 { compatible = "operating-points-v2"; /* derived from 532MHz MPLL */ @@ -193,7 +193,7 @@ }; }; - bus_jpeg_opp_table: opp_table11 { + bus_jpeg_opp_table: opp-table11 { compatible = "operating-points-v2"; /* derived from 600MHz DPLL */ @@ -211,7 +211,7 @@ }; }; - bus_jpeg_apb_opp_table: opp_table12 { + bus_jpeg_apb_opp_table: opp-table12 { compatible = "operating-points-v2"; /* derived from 666MHz CPLL */ @@ -229,7 +229,7 @@ }; }; - bus_disp1_fimd_opp_table: opp_table13 { + bus_disp1_fimd_opp_table: opp-table13 { compatible = "operating-points-v2"; /* derived from 600MHz DPLL */ @@ -241,7 +241,7 @@ }; }; - bus_disp1_opp_table: opp_table14 { + bus_disp1_opp_table: opp-table14 { compatible = "operating-points-v2"; /* derived from 600MHz DPLL */ @@ -256,7 +256,7 @@ }; }; - bus_gscl_opp_table: opp_table15 { + bus_gscl_opp_table: opp-table15 { compatible = "operating-points-v2"; /* derived from 600MHz DPLL */ @@ -271,7 +271,7 @@ }; }; - bus_mscl_opp_table: opp_table16 { + bus_mscl_opp_table: opp-table16 { compatible = "operating-points-v2"; /* derived from 666MHz CPLL */ @@ -292,7 +292,7 @@ }; }; - dmc_opp_table: opp_table17 { + dmc_opp_table: opp-table17 { compatible = "operating-points-v2"; opp00 { From 73f882a0f3a833d589c1a0b6b83045567244e71e Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 5 Nov 2020 19:45:05 +0100 Subject: [PATCH 254/799] ARM: dts: exynos: use hyphens in MFC reserved memory node names Use hyphens instead of underscores in the MFC reserved memory node names which is expected by naming convention, multiple dtschema files and pointed out by dtc W=2 builds. Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20201105184506.215648-5-krzk@kernel.org --- arch/arm/boot/dts/exynos-mfc-reserved-memory.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/exynos-mfc-reserved-memory.dtsi b/arch/arm/boot/dts/exynos-mfc-reserved-memory.dtsi index 1dbf3bbff8d3..597ade3e252f 100644 --- a/arch/arm/boot/dts/exynos-mfc-reserved-memory.dtsi +++ b/arch/arm/boot/dts/exynos-mfc-reserved-memory.dtsi @@ -11,14 +11,14 @@ #size-cells = <1>; ranges; - mfc_left: region_mfc_left { + mfc_left: region-mfc-left { compatible = "shared-dma-pool"; no-map; size = <0x2400000>; alignment = <0x100000>; }; - mfc_right: region_mfc_right { + mfc_right: region-mfc-right { compatible = "shared-dma-pool"; no-map; size = <0x800000>; From d45d3621d679ce74b555bc79bab9055b6f7edb61 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 5 Nov 2020 19:45:06 +0100 Subject: [PATCH 255/799] arm64: dts: exynos: use hyphens in Exynos5433 node names Use hyphens instead of underscores in the Exynos5433 node names which is expected by naming convention, multiple dtschema files and pointed out by dtc W=2 builds. Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20201105184506.215648-6-krzk@kernel.org --- arch/arm64/boot/dts/exynos/exynos5433-bus.dtsi | 10 +++++----- arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi | 4 ++-- arch/arm64/boot/dts/exynos/exynos5433.dtsi | 8 ++++---- 3 files changed, 11 insertions(+), 11 deletions(-) diff --git a/arch/arm64/boot/dts/exynos/exynos5433-bus.dtsi b/arch/arm64/boot/dts/exynos/exynos5433-bus.dtsi index d77b88af9582..8997f8f2b96c 100644 --- a/arch/arm64/boot/dts/exynos/exynos5433-bus.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos5433-bus.dtsi @@ -87,7 +87,7 @@ status = "disabled"; }; - bus_g2d_400_opp_table: opp_table2 { + bus_g2d_400_opp_table: opp-table2 { compatible = "operating-points-v2"; opp-shared; @@ -117,7 +117,7 @@ }; }; - bus_g2d_266_opp_table: opp_table3 { + bus_g2d_266_opp_table: opp-table3 { compatible = "operating-points-v2"; opp-267000000 { @@ -137,7 +137,7 @@ }; }; - bus_gscl_opp_table: opp_table4 { + bus_gscl_opp_table: opp-table4 { compatible = "operating-points-v2"; opp-333000000 { @@ -151,7 +151,7 @@ }; }; - bus_hevc_opp_table: opp_table5 { + bus_hevc_opp_table: opp-table5 { compatible = "operating-points-v2"; opp-shared; @@ -175,7 +175,7 @@ }; }; - bus_noc2_opp_table: opp_table6 { + bus_noc2_opp_table: opp-table6 { compatible = "operating-points-v2"; opp-400000000 { diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi b/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi index 5ec447f0cf5d..03486a8ffc67 100644 --- a/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi @@ -860,7 +860,7 @@ muic: max77843-muic { compatible = "maxim,max77843-muic"; - musb_con: musb_connector { + musb_con: musb-connector { compatible = "samsung,usb-connector-11pin", "usb-b-connector"; label = "micro-USB"; @@ -1083,7 +1083,7 @@ PIN(INPUT, gpf5-7, DOWN, FAST_SR1); }; - te_irq: te_irq { + te_irq: te-irq { samsung,pins = "gpf1-3"; samsung,pin-function = <0xf>; }; diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi index 7853a908fe39..dae44be09a09 100644 --- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi @@ -23,7 +23,7 @@ interrupt-parent = <&gic>; - arm_a53_pmu { + arm-a53-pmu { compatible = "arm,cortex-a53-pmu"; interrupts = , , @@ -32,7 +32,7 @@ interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; }; - arm_a57_pmu { + arm-a57-pmu { compatible = "arm,cortex-a57-pmu"; interrupts = , , @@ -137,7 +137,7 @@ }; }; - cluster_a53_opp_table: opp_table0 { + cluster_a53_opp_table: opp-table0 { compatible = "operating-points-v2"; opp-shared; @@ -183,7 +183,7 @@ }; }; - cluster_a57_opp_table: opp_table1 { + cluster_a57_opp_table: opp-table1 { compatible = "operating-points-v2"; opp-shared; From 876553576f27506760b44fbd7bb18a9cee650706 Mon Sep 17 00:00:00 2001 From: Taniya Das Date: Sat, 7 Nov 2020 00:08:27 +0530 Subject: [PATCH 256/799] arm64: dts: sc7180: Add camera clock controller node Add the camera clock controller node supported on SC7180. Reviewed-by: Douglas Anderson Signed-off-by: Taniya Das Link: https://lore.kernel.org/r/1604687907-25712-1-git-send-email-tdas@codeaurora.org [bjorn: Dropped camcc include] Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc7180.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index 861abc399de9..3a407d27d0d2 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -2896,6 +2896,18 @@ qcom,bcm-voters = <&apps_bcm_voter>; }; + camcc: clock-controller@ad00000 { + compatible = "qcom,sc7180-camcc"; + reg = <0 0x0ad00000 0 0x10000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_CAMERA_AHB_CLK>, + <&gcc GCC_CAMERA_XO_CLK>; + clock-names = "bi_tcxo", "iface", "xo"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + mdss: mdss@ae00000 { compatible = "qcom,sc7180-mdss"; reg = <0 0x0ae00000 0 0x1000>; From ef9a5d188d663753e73a3c8e8910ceab8e9305c4 Mon Sep 17 00:00:00 2001 From: Sibi Sankar Date: Thu, 15 Oct 2020 23:57:56 +0530 Subject: [PATCH 257/799] arm64: dts: qcom: sc7180-trogdor: Fixup modem memory region The modem firmware memory requirements vary between 32M/140M on no-lte/lte skus respectively, so fixup the modem memory region to reflect the requirements. Reviewed-by: Evan Green Signed-off-by: Sibi Sankar Link: https://lore.kernel.org/r/1602786476-27833-1-git-send-email-sibis@codeaurora.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc7180-trogdor-lte-sku.dtsi | 4 ++++ arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi | 2 +- 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lte-sku.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lte-sku.dtsi index 44956e3165a1..469aad4e5948 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lte-sku.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lte-sku.dtsi @@ -9,6 +9,10 @@ label = "proximity-wifi-lte"; }; +&mpss_mem { + reg = <0x0 0x86000000 0x0 0x8c00000>; +}; + &remoteproc_mpss { firmware-name = "qcom/sc7180-trogdor/modem/mba.mbn", "qcom/sc7180-trogdor/modem/qdsp6sw.mbn"; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi index 8653a38a3e42..781e61ad75a6 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi @@ -39,7 +39,7 @@ }; mpss_mem: memory@86000000 { - reg = <0x0 0x86000000 0x0 0x8c00000>; + reg = <0x0 0x86000000 0x0 0x2000000>; no-map; }; From 77e9c198b1558f51092eaaaed59ec68a552f990e Mon Sep 17 00:00:00 2001 From: Zhen Lei Date: Fri, 16 Oct 2020 17:08:33 +0800 Subject: [PATCH 258/799] arm64: dts: qcom: clear the warnings caused by empty dma-ranges The scripts/dtc/checks.c requires that the node have empty "dma-ranges" property must have the same "#address-cells" and "#size-cells" values as the parent node. Otherwise, the following warnings is reported: arch/arm64/boot/dts/qcom/ipq6018.dtsi:185.3-14: Warning \ (dma_ranges_format): /soc:dma-ranges: empty "dma-ranges" property but \ its #address-cells (1) differs from / (2) arch/arm64/boot/dts/qcom/ipq6018.dtsi:185.3-14: Warning \ (dma_ranges_format): /soc:dma-ranges: empty "dma-ranges" property but \ its #size-cells (1) differs from / (2) Arnd Bergmann figured out why it's necessary: Also note that the #address-cells=<1> means that any device under this bus is assumed to only support 32-bit addressing, and DMA will have to go through a slow swiotlb in the absence of an IOMMU. Suggested-by: Arnd Bergmann Reviewed-by: Bjorn Andersson Signed-off-by: Zhen Lei Link: https://lore.kernel.org/r/20201016090833.1892-3-thunder.leizhen@huawei.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/ipq6018.dtsi | 72 +++++++++++++-------------- 1 file changed, 36 insertions(+), 36 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi index 973b2c860ec9..cdc1e3d60c58 100644 --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi @@ -179,22 +179,22 @@ }; soc: soc { - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0 0xffffffff>; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0 0 0 0 0x0 0xffffffff>; dma-ranges; compatible = "simple-bus"; prng: qrng@e1000 { compatible = "qcom,prng-ee"; - reg = <0xe3000 0x1000>; + reg = <0x0 0xe3000 0x0 0x1000>; clocks = <&gcc GCC_PRNG_AHB_CLK>; clock-names = "core"; }; cryptobam: dma@704000 { compatible = "qcom,bam-v1.7.0"; - reg = <0x00704000 0x20000>; + reg = <0x0 0x00704000 0x0 0x20000>; interrupts = ; clocks = <&gcc GCC_CRYPTO_AHB_CLK>; clock-names = "bam_clk"; @@ -206,7 +206,7 @@ crypto: crypto@73a000 { compatible = "qcom,crypto-v5.1"; - reg = <0x0073a000 0x6000>; + reg = <0x0 0x0073a000 0x0 0x6000>; clocks = <&gcc GCC_CRYPTO_AHB_CLK>, <&gcc GCC_CRYPTO_AXI_CLK>, <&gcc GCC_CRYPTO_CLK>; @@ -217,7 +217,7 @@ tlmm: pinctrl@1000000 { compatible = "qcom,ipq6018-pinctrl"; - reg = <0x01000000 0x300000>; + reg = <0x0 0x01000000 0x0 0x300000>; interrupts = ; gpio-controller; #gpio-cells = <2>; @@ -235,7 +235,7 @@ gcc: gcc@1800000 { compatible = "qcom,gcc-ipq6018"; - reg = <0x01800000 0x80000>; + reg = <0x0 0x01800000 0x0 0x80000>; clocks = <&xo>, <&sleep_clk>; clock-names = "xo", "sleep_clk"; #clock-cells = <1>; @@ -244,17 +244,17 @@ tcsr_mutex_regs: syscon@1905000 { compatible = "syscon"; - reg = <0x01905000 0x8000>; + reg = <0x0 0x01905000 0x0 0x8000>; }; tcsr_q6: syscon@1945000 { compatible = "syscon"; - reg = <0x01945000 0xe000>; + reg = <0x0 0x01945000 0x0 0xe000>; }; blsp_dma: dma@7884000 { compatible = "qcom,bam-v1.7.0"; - reg = <0x07884000 0x2b000>; + reg = <0x0 0x07884000 0x0 0x2b000>; interrupts = ; clocks = <&gcc GCC_BLSP1_AHB_CLK>; clock-names = "bam_clk"; @@ -264,7 +264,7 @@ blsp1_uart3: serial@78b1000 { compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; - reg = <0x078b1000 0x200>; + reg = <0x0 0x078b1000 0x0 0x200>; interrupts = ; clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; @@ -276,7 +276,7 @@ compatible = "qcom,spi-qup-v2.2.1"; #address-cells = <1>; #size-cells = <0>; - reg = <0x078b5000 0x600>; + reg = <0x0 0x078b5000 0x0 0x600>; interrupts = ; spi-max-frequency = <50000000>; clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, @@ -291,7 +291,7 @@ compatible = "qcom,spi-qup-v2.2.1"; #address-cells = <1>; #size-cells = <0>; - reg = <0x078b6000 0x600>; + reg = <0x0 0x078b6000 0x0 0x600>; interrupts = ; spi-max-frequency = <50000000>; clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>, @@ -306,7 +306,7 @@ compatible = "qcom,i2c-qup-v2.2.1"; #address-cells = <1>; #size-cells = <0>; - reg = <0x078b6000 0x600>; + reg = <0x0 0x078b6000 0x0 0x600>; interrupts = ; clocks = <&gcc GCC_BLSP1_AHB_CLK>, <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>; @@ -321,7 +321,7 @@ compatible = "qcom,i2c-qup-v2.2.1"; #address-cells = <1>; #size-cells = <0>; - reg = <0x078b7000 0x600>; + reg = <0x0 0x078b7000 0x0 0x600>; interrupts = ; clocks = <&gcc GCC_BLSP1_AHB_CLK>, <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>; @@ -336,24 +336,24 @@ compatible = "qcom,msm-qgic2"; interrupt-controller; #interrupt-cells = <0x3>; - reg = <0x0b000000 0x1000>, /*GICD*/ - <0x0b002000 0x1000>, /*GICC*/ - <0x0b001000 0x1000>, /*GICH*/ - <0x0b004000 0x1000>; /*GICV*/ + reg = <0x0 0x0b000000 0x0 0x1000>, /*GICD*/ + <0x0 0x0b002000 0x0 0x1000>, /*GICC*/ + <0x0 0x0b001000 0x0 0x1000>, /*GICH*/ + <0x0 0x0b004000 0x0 0x1000>; /*GICV*/ interrupts = ; }; watchdog@b017000 { compatible = "qcom,kpss-wdt"; interrupts = ; - reg = <0x0b017000 0x40>; + reg = <0x0 0x0b017000 0x0 0x40>; clocks = <&sleep_clk>; timeout-sec = <10>; }; apcs_glb: mailbox@b111000 { compatible = "qcom,ipq6018-apcs-apps-global"; - reg = <0x0b111000 0x1000>; + reg = <0x0 0x0b111000 0x0 0x1000>; #clock-cells = <1>; clocks = <&a53pll>, <&xo>; clock-names = "pll", "xo"; @@ -362,7 +362,7 @@ a53pll: clock@b116000 { compatible = "qcom,ipq6018-a53pll"; - reg = <0x0b116000 0x40>; + reg = <0x0 0x0b116000 0x0 0x40>; #clock-cells = <0>; clocks = <&xo>; clock-names = "xo"; @@ -377,68 +377,68 @@ }; timer@b120000 { - #address-cells = <1>; - #size-cells = <1>; + #address-cells = <2>; + #size-cells = <2>; ranges; compatible = "arm,armv7-timer-mem"; - reg = <0x0b120000 0x1000>; + reg = <0x0 0x0b120000 0x0 0x1000>; clock-frequency = <19200000>; frame@b120000 { frame-number = <0>; interrupts = , ; - reg = <0x0b121000 0x1000>, - <0x0b122000 0x1000>; + reg = <0x0 0x0b121000 0x0 0x1000>, + <0x0 0x0b122000 0x0 0x1000>; }; frame@b123000 { frame-number = <1>; interrupts = ; - reg = <0xb123000 0x1000>; + reg = <0x0 0xb123000 0x0 0x1000>; status = "disabled"; }; frame@b124000 { frame-number = <2>; interrupts = ; - reg = <0x0b124000 0x1000>; + reg = <0x0 0x0b124000 0x0 0x1000>; status = "disabled"; }; frame@b125000 { frame-number = <3>; interrupts = ; - reg = <0x0b125000 0x1000>; + reg = <0x0 0x0b125000 0x0 0x1000>; status = "disabled"; }; frame@b126000 { frame-number = <4>; interrupts = ; - reg = <0x0b126000 0x1000>; + reg = <0x0 0x0b126000 0x0 0x1000>; status = "disabled"; }; frame@b127000 { frame-number = <5>; interrupts = ; - reg = <0x0b127000 0x1000>; + reg = <0x0 0x0b127000 0x0 0x1000>; status = "disabled"; }; frame@b128000 { frame-number = <6>; interrupts = ; - reg = <0x0b128000 0x1000>; + reg = <0x0 0x0b128000 0x0 0x1000>; status = "disabled"; }; }; q6v5_wcss: remoteproc@cd00000 { compatible = "qcom,ipq8074-wcss-pil"; - reg = <0x0cd00000 0x4040>, - <0x004ab000 0x20>; + reg = <0x0 0x0cd00000 0x0 0x4040>, + <0x0 0x004ab000 0x0 0x20>; reg-names = "qdsp6", "rmb"; interrupts-extended = <&intc GIC_SPI 325 IRQ_TYPE_EDGE_RISING>, From ba73ce9d9ac581c152be92bf22d08d7b78531583 Mon Sep 17 00:00:00 2001 From: Matthias Kaehlcke Date: Fri, 6 Nov 2020 14:01:32 -0800 Subject: [PATCH 259/799] arm64: dts: qcom: sc7180: Add sc7180-lazor-r2/r3 Add configs for lazor rev2 and rev3. There are no relevant deltas between rev1 and rev2, so just add the rev2 compatible string to the rev1 config. One important delta in rev3 is a switch of the power supply for the onboard USB hub from 'pp3300_l7c' to 'pp3300_a' + a load switch. The actual regulator switch is done by the patch 'arm64: dts: qcom: sc7180-trogdor: Make pp3300_a the default supply for pp3300_hub', since it affects the entire trogdor platform. Here we only add the .dts files for lazor rev3 and replace the generic compatible entries in the rev1 .dts files. Reviewed-by: Douglas Anderson Signed-off-by: Matthias Kaehlcke Link: https://lore.kernel.org/r/20201106140125.v3.1.I5a75056d573808f40fed22ab7d28ea6be5819f84@changeid Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/Makefile | 3 +++ .../dts/qcom/sc7180-trogdor-lazor-r1-kb.dts | 4 ++-- .../dts/qcom/sc7180-trogdor-lazor-r1-lte.dts | 4 ++-- .../boot/dts/qcom/sc7180-trogdor-lazor-r1.dts | 4 ++-- .../dts/qcom/sc7180-trogdor-lazor-r3-kb.dts | 17 +++++++++++++++++ .../dts/qcom/sc7180-trogdor-lazor-r3-lte.dts | 18 ++++++++++++++++++ .../boot/dts/qcom/sc7180-trogdor-lazor-r3.dts | 15 +++++++++++++++ 7 files changed, 59 insertions(+), 6 deletions(-) create mode 100644 arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r3-kb.dts create mode 100644 arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r3-lte.dts create mode 100644 arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r3.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index fb4631f898fd..3573f7a7b762 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -26,6 +26,9 @@ dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-r0.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-r1.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-r1-kb.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-r1-lte.dtb +dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-r3.dtb +dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-r3-kb.dtb +dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-r3-lte.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-r1.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-r1-lte.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm630-sony-xperia-ganges-kirin.dtb diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r1-kb.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r1-kb.dts index c3f426c3c30a..919bfaea6189 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r1-kb.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r1-kb.dts @@ -8,8 +8,8 @@ #include "sc7180-trogdor-lazor-r1.dts" / { - model = "Google Lazor (rev1+) with KB Backlight"; - compatible = "google,lazor-sku2", "qcom,sc7180"; + model = "Google Lazor (rev1 - 2) with KB Backlight"; + compatible = "google,lazor-rev1-sku2", "google,lazor-rev2-sku2", "qcom,sc7180"; }; &keyboard_backlight { diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r1-lte.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r1-lte.dts index 73e59cf7752a..5a67e5baafec 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r1-lte.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r1-lte.dts @@ -9,8 +9,8 @@ #include "sc7180-trogdor-lte-sku.dtsi" / { - model = "Google Lazor (rev1+) with LTE"; - compatible = "google,lazor-sku0", "qcom,sc7180"; + model = "Google Lazor (rev1 - 2) with LTE"; + compatible = "google,lazor-rev1-sku0", "google,lazor-rev2-sku0", "qcom,sc7180"; }; &keyboard_backlight { diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r1.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r1.dts index 3151ae31c1cc..9354d4c5ef7d 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r1.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r1.dts @@ -10,6 +10,6 @@ #include "sc7180-trogdor-lazor.dtsi" / { - model = "Google Lazor (rev1+)"; - compatible = "google,lazor", "qcom,sc7180"; + model = "Google Lazor (rev1 - 2)"; + compatible = "google,lazor-rev1", "google,lazor-rev2", "qcom,sc7180"; }; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r3-kb.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r3-kb.dts new file mode 100644 index 000000000000..6985beb97e53 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r3-kb.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Lazor board device tree source + * + * Copyright 2020 Google LLC. + */ + +#include "sc7180-trogdor-lazor-r3.dts" + +/ { + model = "Google Lazor (rev3+) with KB Backlight"; + compatible = "google,lazor-sku2", "qcom,sc7180"; +}; + +&keyboard_backlight { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r3-lte.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r3-lte.dts new file mode 100644 index 000000000000..43836fc4d403 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r3-lte.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Lazor board device tree source + * + * Copyright 2020 Google LLC. + */ + +#include "sc7180-trogdor-lazor-r3.dts" +#include "sc7180-trogdor-lte-sku.dtsi" + +/ { + model = "Google Lazor (rev3+) with LTE"; + compatible = "google,lazor-sku0", "qcom,sc7180"; +}; + +&keyboard_backlight { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r3.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r3.dts new file mode 100644 index 000000000000..1b9d2f46359e --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r3.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Lazor board device tree source + * + * Copyright 2020 Google LLC. + */ + +/dts-v1/; + +#include "sc7180-trogdor-lazor.dtsi" + +/ { + model = "Google Lazor (rev3+)"; + compatible = "google,lazor", "qcom,sc7180"; +}; From 2315ae70af95589e67d8d119c3b3fcaa8746dae8 Mon Sep 17 00:00:00 2001 From: Akhil P Oommen Date: Fri, 30 Oct 2020 16:17:11 +0530 Subject: [PATCH 260/799] arm64: dts: qcom: sc7180: Add gpu cooling support Add cooling-cells property and the cooling maps for the gpu tzones to support GPU cooling. Signed-off-by: Akhil P Oommen Reviewed-by: Matthias Kaehlcke Link: https://lore.kernel.org/r/1604054832-3114-2-git-send-email-akhilpo@codeaurora.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc7180.dtsi | 30 +++++++++++++++++++++------- 1 file changed, 23 insertions(+), 7 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index 3a407d27d0d2..4e7e58c63285 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -2,7 +2,7 @@ /* * SC7180 SoC device tree source * - * Copyright (c) 2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved. */ #include @@ -2011,6 +2011,8 @@ operating-points-v2 = <&gpu_opp_table>; qcom,gmu = <&gmu>; + #cooling-cells = <2>; + interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "gfx-mem"; @@ -4037,16 +4039,16 @@ }; gpuss0-thermal { - polling-delay-passive = <0>; + polling-delay-passive = <100>; polling-delay = <0>; thermal-sensors = <&tsens0 13>; trips { gpuss0_alert0: trip-point0 { - temperature = <90000>; + temperature = <95000>; hysteresis = <2000>; - type = "hot"; + type = "passive"; }; gpuss0_crit: gpuss0_crit { @@ -4055,19 +4057,26 @@ type = "critical"; }; }; + + cooling-maps { + map0 { + trip = <&gpuss0_alert0>; + cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; }; gpuss1-thermal { - polling-delay-passive = <0>; + polling-delay-passive = <100>; polling-delay = <0>; thermal-sensors = <&tsens0 14>; trips { gpuss1_alert0: trip-point0 { - temperature = <90000>; + temperature = <95000>; hysteresis = <2000>; - type = "hot"; + type = "passive"; }; gpuss1_crit: gpuss1_crit { @@ -4076,6 +4085,13 @@ type = "critical"; }; }; + + cooling-maps { + map0 { + trip = <&gpuss1_alert0>; + cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; }; aoss1-thermal { From 183d4cafa711acd4ca2b1d682c8b867d549f2bc4 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Mon, 5 Oct 2020 17:03:01 +0200 Subject: [PATCH 261/799] arm64: dts: qcom: pm8994: Add VADC node Add VADC note and some of its channels to allow for voltage/temperature reading. Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20201005150313.149754-2-konradybcio@gmail.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/pm8994.dtsi | 36 +++++++++++++++++++++++++++- 1 file changed, 35 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/pm8994.dtsi b/arch/arm64/boot/dts/qcom/pm8994.dtsi index 7e4f777746cb..ea2a3d53f859 100644 --- a/arch/arm64/boot/dts/qcom/pm8994.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8994.dtsi @@ -1,7 +1,8 @@ // SPDX-License-Identifier: GPL-2.0 +#include +#include #include #include -#include &spmi_bus { @@ -35,6 +36,39 @@ }; + pm8994_vadc: adc@3100 { + compatible = "qcom,spmi-vadc"; + reg = <0x3100>; + interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>; + #address-cells = <1>; + #size-cells = <0>; + #io-channel-cells = <1>; + + adc-chan@7 { + reg = ; + qcom,pre-scaling = <1 3>; + label = "vph_pwr"; + }; + adc-chan@8 { + reg = ; + label = "die_temp"; + }; + adc-chan@9 { + reg = ; + label = "ref_625mv"; + }; + adc-chan@a { + reg = ; + label = "ref_1250mv"; + }; + adc-chan@e { + reg = ; + }; + adc-chan@f { + reg = ; + }; + }; + pm8994_gpios: gpios@c000 { compatible = "qcom,pm8994-gpio"; reg = <0xc000>; From 4778b2f1a3f0c97caa184a695b308b874cb2d3cd Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Mon, 5 Oct 2020 17:03:02 +0200 Subject: [PATCH 262/799] arm64: dts: qcom: pm8994: Add temperature alarm node Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20201005150313.149754-3-konradybcio@gmail.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/pm8994.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/pm8994.dtsi b/arch/arm64/boot/dts/qcom/pm8994.dtsi index ea2a3d53f859..7825208b0d8b 100644 --- a/arch/arm64/boot/dts/qcom/pm8994.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8994.dtsi @@ -36,6 +36,15 @@ }; + pm8994_temp: temp-alarm@2400 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0x2400>; + interrupts = <0x0 0x24 0x0 IRQ_TYPE_EDGE_RISING>; + io-channels = <&pm8994_vadc VADC_DIE_TEMP>; + io-channel-names = "thermal"; + #thermal-sensor-cells = <0>; + }; + pm8994_vadc: adc@3100 { compatible = "qcom,spmi-vadc"; reg = <0x3100>; From 0763f58540419874ebeb25eb9869638666d62ed4 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Mon, 5 Oct 2020 17:03:03 +0200 Subject: [PATCH 263/799] arm64: dts: qcom: pm8994: Add thermal-zones for temp alarm This will shut down the platform in case the PMIC overheats. Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20201005150313.149754-4-konradybcio@gmail.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/pm8994.dtsi | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/pm8994.dtsi b/arch/arm64/boot/dts/qcom/pm8994.dtsi index 7825208b0d8b..9ab5657f7d23 100644 --- a/arch/arm64/boot/dts/qcom/pm8994.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8994.dtsi @@ -4,6 +4,30 @@ #include #include +/ { + thermal-zones { + pm8994 { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&pm8994_temp>; + + trips { + pm8994_alert0: pm8994-alert0 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + pm8994_crit: pm8994-crit { + temperature = <125000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + }; +}; + &spmi_bus { pmic@0 { From 8939304880dee9c57b7bd41e4679d4741a85d6e7 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Mon, 5 Oct 2020 17:03:04 +0200 Subject: [PATCH 264/799] arm64: dts: qcom: pm8994: Fix up spmi-gpio node Add a common compatible and switch to gpio-ranges. Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20201005150313.149754-5-konradybcio@gmail.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/pm8994.dtsi | 27 ++++----------------------- 1 file changed, 4 insertions(+), 23 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/pm8994.dtsi b/arch/arm64/boot/dts/qcom/pm8994.dtsi index 9ab5657f7d23..5ffdf37d8e31 100644 --- a/arch/arm64/boot/dts/qcom/pm8994.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8994.dtsi @@ -103,32 +103,13 @@ }; pm8994_gpios: gpios@c000 { - compatible = "qcom,pm8994-gpio"; + compatible = "qcom,pm8994-gpio", "qcom,spmi-gpio"; reg = <0xc000>; gpio-controller; + gpio-ranges = <&pm8994_gpios 0 0 22>; #gpio-cells = <2>; - interrupts = <0 0xc0 0 IRQ_TYPE_NONE>, - <0 0xc1 0 IRQ_TYPE_NONE>, - <0 0xc2 0 IRQ_TYPE_NONE>, - <0 0xc3 0 IRQ_TYPE_NONE>, - <0 0xc4 0 IRQ_TYPE_NONE>, - <0 0xc5 0 IRQ_TYPE_NONE>, - <0 0xc6 0 IRQ_TYPE_NONE>, - <0 0xc7 0 IRQ_TYPE_NONE>, - <0 0xc8 0 IRQ_TYPE_NONE>, - <0 0xc9 0 IRQ_TYPE_NONE>, - <0 0xca 0 IRQ_TYPE_NONE>, - <0 0xcb 0 IRQ_TYPE_NONE>, - <0 0xcc 0 IRQ_TYPE_NONE>, - <0 0xcd 0 IRQ_TYPE_NONE>, - <0 0xce 0 IRQ_TYPE_NONE>, - <0 0xcf 0 IRQ_TYPE_NONE>, - <0 0xd0 0 IRQ_TYPE_NONE>, - <0 0xd1 0 IRQ_TYPE_NONE>, - <0 0xd2 0 IRQ_TYPE_NONE>, - <0 0xd3 0 IRQ_TYPE_NONE>, - <0 0xd4 0 IRQ_TYPE_NONE>, - <0 0xd5 0 IRQ_TYPE_NONE>; + interrupt-controller; + #interrupt-cells = <2>; }; pm8994_mpps: mpps@a000 { From 211ea9b34919bfbab208073a675d15ec68156dc9 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Mon, 5 Oct 2020 17:03:05 +0200 Subject: [PATCH 265/799] arm64: dts: qcom: msm8992: Add support for SDHCI2 This will let us use SD cards on our devices. Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20201005150313.149754-6-konradybcio@gmail.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8992.dtsi | 59 +++++++++++++++++++++++++++ 1 file changed, 59 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8992.dtsi b/arch/arm64/boot/dts/qcom/msm8992.dtsi index 8626b3a50eda..6242c56a2bfa 100644 --- a/arch/arm64/boot/dts/qcom/msm8992.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8992.dtsi @@ -269,6 +269,29 @@ status = "disabled"; }; + sdhc_2: sdhci@f98a4900 { + compatible = "qcom,sdhci-msm-v4"; + reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>; + reg-names = "hc_mem", "core_mem"; + + interrupts = , + ; + interrupt-names = "hc_irq", "pwr_irq"; + + clocks = <&gcc GCC_SDCC2_APPS_CLK>, + <&gcc GCC_SDCC2_AHB_CLK>, + <&xo_board>; + clock-names = "core", "iface", "xo"; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on>; + pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off>; + + cd-gpios = <&tlmm 100 0>; + bus-width = <4>; + status = "disabled"; + }; + blsp1_uart2: serial@f991e000 { compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; reg = <0xf991e000 0x1000>; @@ -573,6 +596,42 @@ drive-strength = <2>; bias-disable; }; + + sdc2_clk_on: sdc2-clk-on { + pins = "sdc2_clk"; + bias-disable; + drive-strength = <16>; + }; + + sdc2_clk_off: sdc2-clk-off { + pins = "sdc2_clk"; + bias-disable; + drive-strength = <2>; + }; + + sdc2_cmd_on: sdc2-cmd-on { + pins = "sdc2_cmd"; + bias-pull-up; + drive-strength = <10>; + }; + + sdc2_cmd_off: sdc2-cmd-off { + pins = "sdc2_cmd"; + bias-pull-up; + drive-strength = <2>; + }; + + sdc2_data_on: sdc2-data-on { + pins = "sdc2_data"; + bias-pull-up; + drive-strength = <10>; + }; + + sdc2_data_off: sdc2-data-off { + pins = "sdc2_data"; + bias-pull-up; + drive-strength = <2>; + }; }; }; From f3d1939f115d696acf61f24d97443b42408d2449 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Mon, 5 Oct 2020 17:03:06 +0200 Subject: [PATCH 266/799] arm64: dts: qcom: msm8994: Add SDHCI2 node Add SDHCI2 to enable use of uSD cards on msm8994. Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20201005150313.149754-7-konradybcio@gmail.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8994.dtsi | 59 +++++++++++++++++++++++++++ 1 file changed, 59 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8994.dtsi b/arch/arm64/boot/dts/qcom/msm8994.dtsi index 6707f898607f..65089d7670f6 100644 --- a/arch/arm64/boot/dts/qcom/msm8994.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8994.dtsi @@ -305,6 +305,29 @@ status = "disabled"; }; + sdhc2: sdhci@f98a4900 { + compatible = "qcom,sdhci-msm-v4"; + reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>; + reg-names = "hc_mem", "core_mem"; + + interrupts = , + ; + interrupt-names = "hc_irq", "pwr_irq"; + + clocks = <&gcc GCC_SDCC2_APPS_CLK>, + <&gcc GCC_SDCC2_AHB_CLK>, + <&xo_board>; + clock-names = "core", "iface", "xo"; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on>; + pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off>; + + cd-gpios = <&tlmm 100 0>; + bus-width = <4>; + status = "disabled"; + }; + blsp1_dma: dma@f9904000 { compatible = "qcom,bam-v1.7.0"; reg = <0xf9904000 0x19000>; @@ -683,6 +706,42 @@ pins = "sdc1_rclk"; bias-pull-down; }; + + sdc2_clk_on: sdc2-clk-on { + pins = "sdc2_clk"; + bias-disable; + drive-strength = <10>; + }; + + sdc2_clk_off: sdc2-clk-off { + pins = "sdc2_clk"; + bias-disable; + drive-strength = <2>; + }; + + sdc2_cmd_on: sdc2-cmd-on { + pins = "sdc2_cmd"; + bias-pull-up; + drive-strength = <10>; + }; + + sdc2_cmd_off: sdc2-cmd-off { + pins = "sdc2_cmd"; + bias-pull-up; + drive-strength = <2>; + }; + + sdc2_data_on: sdc2-data-on { + pins = "sdc2_data"; + bias-pull-up; + drive-strength = <10>; + }; + + sdc2_data_off: sdc2-data-off { + pins = "sdc2_data"; + bias-pull-up; + drive-strength = <2>; + }; }; }; From b97def9c0557a9354c718b13d09a81f26e128129 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Mon, 5 Oct 2020 17:03:07 +0200 Subject: [PATCH 267/799] arm64: dts: qcom: msm8992: Add BLSP_I2C1 support This will be required to support touchscreen on Lumia devices. Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20201005150313.149754-8-konradybcio@gmail.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8992.dtsi | 30 +++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8992.dtsi b/arch/arm64/boot/dts/qcom/msm8992.dtsi index 6242c56a2bfa..81426577f2bd 100644 --- a/arch/arm64/boot/dts/qcom/msm8992.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8992.dtsi @@ -305,6 +305,22 @@ status = "disabled"; }; + blsp_i2c1: i2c@f9923000 { + compatible = "qcom,i2c-qup-v2.2.1"; + reg = <0xf9923000 0x500>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_AHB_CLK>, + <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>; + clock-names = "iface", "core"; + clock-frequency = <400000>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c1_default>; + pinctrl-1 = <&i2c1_sleep>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + blsp_i2c2: i2c@f9924000 { compatible = "qcom,i2c-qup-v2.2.1"; reg = <0xf9924000 0x500>; @@ -525,6 +541,20 @@ bias-pull-down; }; + i2c1_default: i2c1-default { + function = "blsp_i2c1"; + pins = "gpio2", "gpio3"; + drive-strength = <2>; + bias-disable; + }; + + i2c1_sleep: i2c1-sleep { + function = "gpio"; + pins = "gpio2", "gpio3"; + drive-strength = <2>; + bias-disable; + }; + i2c2_default: i2c2-default { function = "blsp_i2c2"; pins = "gpio6", "gpio7"; From a0b3e3629748f1535f4945f213134182fc008160 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Mon, 5 Oct 2020 17:03:08 +0200 Subject: [PATCH 268/799] arm64: dts: qcom: talkman: Add Synaptics RMI4 touchscreen This adds touchscreen capabilities to the Lumia 950. Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20201005150313.149754-9-konradybcio@gmail.com Signed-off-by: Bjorn Andersson --- .../dts/qcom/msm8992-msft-lumia-talkman.dts | 28 +++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8992-msft-lumia-talkman.dts b/arch/arm64/boot/dts/qcom/msm8992-msft-lumia-talkman.dts index 3cc01f02219d..c337a86a5c77 100644 --- a/arch/arm64/boot/dts/qcom/msm8992-msft-lumia-talkman.dts +++ b/arch/arm64/boot/dts/qcom/msm8992-msft-lumia-talkman.dts @@ -32,6 +32,34 @@ }; }; +&blsp_i2c1 { + status = "okay"; + + rmi4-i2c-dev@4b { + compatible = "syna,rmi4-i2c"; + reg = <0x4b>; + #address-cells = <1>; + #size-cells = <0>; + + interrupt-parent = <&tlmm>; + interrupts = <77 IRQ_TYPE_EDGE_FALLING>; + + rmi4-f01@1 { + reg = <0x01>; + syna,nosleep-mode = <1>; + }; + + rmi4-f12@12 { + reg = <0x12>; + syna,sensor-type = <1>; + syna,clip-x-low = <0>; + syna,clip-x-high = <1440>; + syna,clip-y-low = <0>; + syna,clip-y-high = <2560>; + }; + }; +}; + &sdhc_1 { status = "okay"; From d9be0bc95f25d49ae260b9ad8ad9040931758fbd Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Mon, 5 Oct 2020 17:03:09 +0200 Subject: [PATCH 269/799] arm64: dts: qcom: msm8994: Add USB support This is a very basic dwc3 configuration (no PHYs yet), but it works. Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20201005150313.149754-10-konradybcio@gmail.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8994.dtsi | 31 +++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8994.dtsi b/arch/arm64/boot/dts/qcom/msm8994.dtsi index 65089d7670f6..8612a11c3584 100644 --- a/arch/arm64/boot/dts/qcom/msm8994.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8994.dtsi @@ -282,6 +282,37 @@ }; }; + usb3: usb@f92f8800 { + compatible = "qcom,msm8996-dwc3", "qcom,dwc3"; + reg = <0xf92f8800 0x400>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + clocks = <&gcc GCC_USB30_MASTER_CLK>, + <&gcc GCC_SYS_NOC_USB3_AXI_CLK>, + <&gcc GCC_USB30_SLEEP_CLK>, + <&gcc GCC_USB30_MOCK_UTMI_CLK>; + clock-names = "core", "iface", "sleep", "mock_utmi", "ref", "xo"; + + assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_MASTER_CLK>; + assigned-clock-rates = <19200000>, <120000000>; + + power-domains = <&gcc USB30_GDSC>; + qcom,select-utmi-as-pipe-clk; + + dwc3@f9200000 { + compatible = "snps,dwc3"; + reg = <0xf9200000 0xcc00>; + interrupts = <0 131 IRQ_TYPE_LEVEL_HIGH>; + snps,dis_u2_susphy_quirk; + snps,dis_enblslpm_quirk; + maximum-speed = "high-speed"; + dr_mode = "peripheral"; + }; + }; + sdhc1: sdhci@f9824900 { compatible = "qcom,sdhci-msm-v4"; reg = <0xf9824900 0x1a0>, <0xf9824000 0x800>; From 1865bb197843e19e3a0f949a3c88b06a8d7abd94 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Mon, 5 Oct 2020 17:03:10 +0200 Subject: [PATCH 270/799] arm64: dts: qcom: msm8992: Add USB support This is a very basic dwc3 configuration (no PHYs yet), but it works. Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20201005150313.149754-11-konradybcio@gmail.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8992.dtsi | 31 +++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8992.dtsi b/arch/arm64/boot/dts/qcom/msm8992.dtsi index 81426577f2bd..0c422af47917 100644 --- a/arch/arm64/boot/dts/qcom/msm8992.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8992.dtsi @@ -242,6 +242,37 @@ }; }; + usb3: usb@f92f8800 { + compatible = "qcom,msm8996-dwc3", "qcom,dwc3"; + reg = <0xf92f8800 0x400>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + clocks = <&gcc GCC_USB30_MASTER_CLK>, + <&gcc GCC_SYS_NOC_USB3_AXI_CLK>, + <&gcc GCC_USB30_SLEEP_CLK>, + <&gcc GCC_USB30_MOCK_UTMI_CLK>; + clock-names = "core", "iface", "sleep", "mock_utmi", "ref", "xo"; + + assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_MASTER_CLK>; + assigned-clock-rates = <19200000>, <120000000>; + + power-domains = <&gcc USB30_GDSC>; + qcom,select-utmi-as-pipe-clk; + + dwc3@f9200000 { + compatible = "snps,dwc3"; + reg = <0xf9200000 0xcc00>; + interrupts = <0 131 IRQ_TYPE_LEVEL_HIGH>; + snps,dis_u2_susphy_quirk; + snps,dis_enblslpm_quirk; + maximum-speed = "high-speed"; + dr_mode = "peripheral"; + }; + }; + sdhc_1: sdhci@f9824900 { compatible = "qcom,sdhci-msm-v4"; reg = <0xf9824900 0x1a0>, <0xf9824000 0x800>; From 2704ff5f02c884bd4b774da089d139f17f8e32ae Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Mon, 5 Oct 2020 17:03:11 +0200 Subject: [PATCH 271/799] arm64: dts: qcom: Add support for Microsoft Lumia 950 XL (Cityman) Add device tree support for Microsoft Lumia 950 XL smartphone. It is based on the msm8994 chipset and is able to boot Linux using a custom EDK2 implementation. EL2 core startup is possible with spin-table, but for now, we'll stick with PSCI. The board currently supports: * Screen console via EFIFB * SDHCI * I2C * UART * PSCI core bringup Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20201005150313.149754-12-konradybcio@gmail.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/Makefile | 1 + .../dts/qcom/msm8994-msft-lumia-cityman.dts | 73 +++++++++++++++++++ 2 files changed, 74 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/msm8994-msft-lumia-cityman.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 3573f7a7b762..90887aac28e2 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -12,6 +12,7 @@ dtb-$(CONFIG_ARCH_QCOM) += msm8992-bullhead-rev-101.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8992-msft-lumia-talkman.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8992-xiaomi-libra.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8994-angler-rev-101.dtb +dtb-$(CONFIG_ARCH_QCOM) += msm8994-msft-lumia-cityman.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8994-sony-xperia-kitakami-sumire.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8996-mtp.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8998-asus-novago-tp370ql.dtb diff --git a/arch/arm64/boot/dts/qcom/msm8994-msft-lumia-cityman.dts b/arch/arm64/boot/dts/qcom/msm8994-msft-lumia-cityman.dts new file mode 100644 index 000000000000..ed9034b96013 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/msm8994-msft-lumia-cityman.dts @@ -0,0 +1,73 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2020, Konrad Dybcio + */ + +/dts-v1/; + +#include "msm8994.dtsi" +#include "pm8994.dtsi" +#include "pmi8994.dtsi" + +/ { + model = "Microsoft Lumia 950 XL"; + compatible = "microsoft,cityman", "qcom,msm8994"; + + /* + * Most Lumia 950XL users use GRUB to load their kernels, + * hence there is no need for msm-id and friends. + */ + + /* + * This enables graphical output via bootloader-enabled display. + * acpi=no is required due to WP platforms having ACPI support, but + * only for Windows-based OSes. + */ + chosen { + bootargs = "earlycon=efifb console=efifb acpi=no"; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + }; +}; + +&blsp_i2c1 { + status = "okay"; + + rmi4-i2c-dev@4b { + compatible = "syna,rmi4-i2c"; + reg = <0x4b>; + #address-cells = <1>; + #size-cells = <0>; + + interrupt-parent = <&tlmm>; + interrupts = <77 IRQ_TYPE_EDGE_FALLING>; + + rmi4-f01@1 { + reg = <0x01>; + syna,nosleep-mode = <1>; + }; + + rmi4-f12@12 { + reg = <0x12>; + syna,sensor-type = <1>; + syna,clip-x-low = <0>; + syna,clip-x-high = <1440>; + syna,clip-y-low = <0>; + syna,clip-y-high = <2660>; + }; + }; +}; + +&blsp1_uart2 { + status = "okay"; +}; + +&blsp2_uart2 { + status = "okay"; +}; + +&sdhc1 { + status = "okay"; +}; From a8fbc8bd8d1f8d4143c164e5f31704dd37baa386 Mon Sep 17 00:00:00 2001 From: Vinod Koul Date: Tue, 27 Oct 2020 22:15:03 +0530 Subject: [PATCH 272/799] arm64: dts: sdm845: Fix dma node name DMA controller binding describes the node name should be dma-controller and not dma, so fix the node name Signed-off-by: Vinod Koul Link: https://lore.kernel.org/r/20201027164511.476312-2-vkoul@kernel.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 895e7038cdc6..6465a6653ad9 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -4487,7 +4487,7 @@ }; }; - slimbam: dma@17184000 { + slimbam: dma-controller@17184000 { compatible = "qcom,bam-v1.7.0"; qcom,controlled-remotely; reg = <0 0x17184000 0 0x2a000>; From b831fba3b0e184930747761adc9fdaccc3c49ff4 Mon Sep 17 00:00:00 2001 From: Vinod Koul Date: Tue, 27 Oct 2020 22:15:04 +0530 Subject: [PATCH 273/799] arm64: dts: sdm630: Fix dma node name DMA controller binding describes the node name should be dma-controller and not dma, so fix the node name Signed-off-by: Vinod Koul Link: https://lore.kernel.org/r/20201027164511.476312-3-vkoul@kernel.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm630.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm630.dtsi b/arch/arm64/boot/dts/qcom/sdm630.dtsi index deb928d303c2..37d5cc32f6b6 100644 --- a/arch/arm64/boot/dts/qcom/sdm630.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm630.dtsi @@ -830,7 +830,7 @@ status = "disabled"; }; - blsp1_dma: dma@c144000 { + blsp1_dma: dma-controller@c144000 { compatible = "qcom,bam-v1.7.0"; reg = <0x0c144000 0x1f000>; interrupts = ; @@ -944,7 +944,7 @@ status = "disabled"; }; - blsp2_dma: dma@c184000 { + blsp2_dma: dma-controller@c184000 { compatible = "qcom,bam-v1.7.0"; reg = <0x0c184000 0x1f000>; interrupts = ; From 6bd61ef47eaec2775b8444dde80ae672bb797717 Mon Sep 17 00:00:00 2001 From: Vinod Koul Date: Tue, 27 Oct 2020 22:15:05 +0530 Subject: [PATCH 274/799] arm64: dts: qcs404: Fix dma node name DMA controller binding describes the node name should be dma-controller and not dma, so fix the node name Signed-off-by: Vinod Koul Link: https://lore.kernel.org/r/20201027164511.476312-4-vkoul@kernel.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qcs404.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi index b654b802e95c..339790ba585d 100644 --- a/arch/arm64/boot/dts/qcom/qcs404.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi @@ -801,7 +801,7 @@ status = "disabled"; }; - blsp1_dma: dma@7884000 { + blsp1_dma: dma-controller@7884000 { compatible = "qcom,bam-v1.7.0"; reg = <0x07884000 0x25000>; interrupts = ; @@ -1045,7 +1045,7 @@ status = "disabled"; }; - blsp2_dma: dma@7ac4000 { + blsp2_dma: dma-controller@7ac4000 { compatible = "qcom,bam-v1.7.0"; reg = <0x07ac4000 0x17000>; interrupts = ; From eaf61213901d2b9a4040f217498ecbea61f8e0a5 Mon Sep 17 00:00:00 2001 From: Vinod Koul Date: Tue, 27 Oct 2020 22:15:06 +0530 Subject: [PATCH 275/799] arm64: dts: msm8916: Fix dma node name DMA controller binding describes the node name should be dma-controller and not dma, so fix the node name Signed-off-by: Vinod Koul Link: https://lore.kernel.org/r/20201027164511.476312-5-vkoul@kernel.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8916.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index 74aa50f3db10..402e891a84ab 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -1425,7 +1425,7 @@ status = "disabled"; }; - blsp_dma: dma@7884000 { + blsp_dma: dma-controller@7884000 { compatible = "qcom,bam-v1.7.0"; reg = <0x07884000 0x23000>; interrupts = ; From 828896c562339292f5b7c04dc95a9e8ea150544f Mon Sep 17 00:00:00 2001 From: Vinod Koul Date: Tue, 27 Oct 2020 22:15:07 +0530 Subject: [PATCH 276/799] arm64: dts: msm8994: Fix dma node name DMA controller binding describes the node name should be dma-controller and not dma, so fix the node name Signed-off-by: Vinod Koul Link: https://lore.kernel.org/r/20201027164511.476312-6-vkoul@kernel.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8994.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8994.dtsi b/arch/arm64/boot/dts/qcom/msm8994.dtsi index 8612a11c3584..6e083a2f690b 100644 --- a/arch/arm64/boot/dts/qcom/msm8994.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8994.dtsi @@ -359,7 +359,7 @@ status = "disabled"; }; - blsp1_dma: dma@f9904000 { + blsp1_dma: dma-controller@f9904000 { compatible = "qcom,bam-v1.7.0"; reg = <0xf9904000 0x19000>; interrupts = ; @@ -455,7 +455,7 @@ status = "disabled"; }; - blsp2_dma: dma@f9944000 { + blsp2_dma: dma-controller@f9944000 { compatible = "qcom,bam-v1.7.0"; reg = <0xf9944000 0x19000>; interrupts = ; From b5af3036e84c801416b699930b2b578fbe755cd1 Mon Sep 17 00:00:00 2001 From: Vinod Koul Date: Tue, 27 Oct 2020 22:15:08 +0530 Subject: [PATCH 277/799] arm64: dts: msm8996: Fix dma node name DMA controller binding describes the node name should be dma-controller and not dma, so fix the node name Signed-off-by: Vinod Koul Link: https://lore.kernel.org/r/20201027164511.476312-7-vkoul@kernel.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8996.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index fd6ae5464dea..7eef07e73e25 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -1990,7 +1990,7 @@ }; }; - slimbam: dma@9184000 { + slimbam: dma-controller@9184000 { compatible = "qcom,bam-v1.7.0"; qcom,controlled-remotely; reg = <0x09184000 0x32000>; From 94ed1811aff0c4027d877d2ecf66da0d62369d99 Mon Sep 17 00:00:00 2001 From: Vinod Koul Date: Tue, 27 Oct 2020 22:15:09 +0530 Subject: [PATCH 278/799] arm64: dts: msm8998: Fix dma node name DMA controller binding describes the node name should be dma-controller and not dma, so fix the node name Signed-off-by: Vinod Koul Link: https://lore.kernel.org/r/20201027164511.476312-8-vkoul@kernel.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8998.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi index c45870600909..ebdaaf1dfca4 100644 --- a/arch/arm64/boot/dts/qcom/msm8998.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi @@ -1754,7 +1754,7 @@ status = "disabled"; }; - blsp1_dma: dma@c144000 { + blsp1_dma: dma-controller@c144000 { compatible = "qcom,bam-v1.7.0"; reg = <0x0c144000 0x25000>; interrupts = ; From 58acbcdcdc33c9c7b8601b5057a272009e4fe2f6 Mon Sep 17 00:00:00 2001 From: Vinod Koul Date: Tue, 27 Oct 2020 22:15:10 +0530 Subject: [PATCH 279/799] arm64: dts: ipq6018: Fix dma node name DMA controller binding describes the node name should be dma-controller and not dma, so fix the node name Signed-off-by: Vinod Koul Link: https://lore.kernel.org/r/20201027164511.476312-9-vkoul@kernel.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/ipq6018.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi index cdc1e3d60c58..540460457420 100644 --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi @@ -192,7 +192,7 @@ clock-names = "core"; }; - cryptobam: dma@704000 { + cryptobam: dma-controller@704000 { compatible = "qcom,bam-v1.7.0"; reg = <0x0 0x00704000 0x0 0x20000>; interrupts = ; @@ -252,7 +252,7 @@ reg = <0x0 0x01945000 0x0 0xe000>; }; - blsp_dma: dma@7884000 { + blsp_dma: dma-controller@7884000 { compatible = "qcom,bam-v1.7.0"; reg = <0x0 0x07884000 0x0 0x2b000>; interrupts = ; From b7fbf46cb81c2bb432d648f52e4cd591a09593bc Mon Sep 17 00:00:00 2001 From: Vinod Koul Date: Tue, 27 Oct 2020 22:15:11 +0530 Subject: [PATCH 280/799] arm64: dts: ipq8074: Fix dma node name DMA controller binding describes the node name should be dma-controller and not dma, so fix the node name Signed-off-by: Vinod Koul Link: https://lore.kernel.org/r/20201027164511.476312-10-vkoul@kernel.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi index 829e37ac82f6..a32e5e79ab0b 100644 --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi @@ -276,7 +276,7 @@ status = "disabled"; }; - blsp_dma: dma@7884000 { + blsp_dma: dma-controller@7884000 { compatible = "qcom,bam-v1.7.0"; reg = <0x07884000 0x2b000>; interrupts = ; @@ -372,7 +372,7 @@ status = "disabled"; }; - qpic_bam: dma@7984000 { + qpic_bam: dma-controller@7984000 { compatible = "qcom,bam-v1.7.0"; reg = <0x07984000 0x1a000>; interrupts = ; From e77ce5ec8b9d63bd980ca8a2ab9c28222cacb3ba Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Wed, 11 Nov 2020 01:25:13 +0100 Subject: [PATCH 281/799] ARM: dts: ux500: skomer: Pull down SDI2 FBCLK The feedback clock on SDI2 needs to be pulled down on this machine. Link: https://lore.kernel.org/r/20201111002513.2271351-1-linus.walleij@linaro.org Signed-off-by: Linus Walleij --- arch/arm/boot/dts/ste-ux500-samsung-skomer.dts | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm/boot/dts/ste-ux500-samsung-skomer.dts b/arch/arm/boot/dts/ste-ux500-samsung-skomer.dts index cbae23a1e8b6..b50634c81b44 100644 --- a/arch/arm/boot/dts/ste-ux500-samsung-skomer.dts +++ b/arch/arm/boot/dts/ste-ux500-samsung-skomer.dts @@ -433,6 +433,16 @@ }; }; + /* The unused FBCLK needs to be pulled down on this machine */ + sdi2 { + mc2_a_1_default { + default_cfg2 { + pins = "GPIO130_C8"; /* FBCLK */ + ste,config = <&in_pd>; + }; + }; + }; + mcde { dsi_default_mode: dsi_default { default_mux1 { From ead9f7d7ea9e20843e29e688b53859cea20044ee Mon Sep 17 00:00:00 2001 From: Douglas Anderson Date: Wed, 11 Nov 2020 07:37:01 -0800 Subject: [PATCH 282/799] arm64: dts: qcom: sc7180: Assign numbers to eMMC and SD After many years of struggle, commit fa2d0aa96941 ("mmc: core: Allow setting slot index via device tree alias") finally allows the use of aliases to number SD/MMC slots. Let's do that for sc7180 SoCs so that if eMMC and SD are both used they have consistent numbers across boots and kernel changes. Picking numbers can be tricky. Do we call these "1" and "2" to match the name in documentation or "0" and "1" with the assertion that we should always start at 0 and count up? While the "start counting at 0" makes sense if there are not already well-defined numbers for all sd/mmc controllers, in the case of sc7180 there _are_ well defined numbers. IMO it is less confusing to use those and match the docs. Signed-off-by: Douglas Anderson Link: https://lore.kernel.org/r/20201111073652.1.Ia5bccd9eab7d74ea1ea9a7780e3cdbf662f5a464@changeid Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc7180.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index 4e7e58c63285..625e922c273d 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -31,6 +31,8 @@ chosen { }; aliases { + mmc1 = &sdhc_1; + mmc2 = &sdhc_2; i2c0 = &i2c0; i2c1 = &i2c1; i2c2 = &i2c2; From c74da5cf007c49873a502eb7f4554fefb23f3f33 Mon Sep 17 00:00:00 2001 From: Konstantin Aladyshev Date: Wed, 11 Nov 2020 16:21:33 +0300 Subject: [PATCH 283/799] ARM: dts: aspeed: amd-ethanolx: Add GPIO line names Add GPIO line names for AMD EthanolX customer reference board. It populates AST2500 GPIO lines (A0-A7 to AC0-AC7) with AMD EthanolX designated names. Signed-off-by: Konstantin Aladyshev Reviewed-by: Supreeth Venkatesh Link: https://lore.kernel.org/r/20201111132133.1253-1-aladyshev22@gmail.com Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-bmc-amd-ethanolx.dts | 44 +++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/arch/arm/boot/dts/aspeed-bmc-amd-ethanolx.dts b/arch/arm/boot/dts/aspeed-bmc-amd-ethanolx.dts index b93ed44eba0c..96ff0aea64e5 100644 --- a/arch/arm/boot/dts/aspeed-bmc-amd-ethanolx.dts +++ b/arch/arm/boot/dts/aspeed-bmc-amd-ethanolx.dts @@ -97,6 +97,50 @@ &pinctrl_adc4_default>; }; +&gpio { + status = "okay"; + gpio-line-names = + /*A0-A7*/ "","","FAULT_LED","CHASSIS_ID_LED","","","","", + /*B0-B7*/ "","","","","","","","", + /*C0-C7*/ "CHASSIS_ID_BTN","INTRUDER","AC_LOSS","","","","","", + /*D0-D7*/ "HDT_DBREQ","LOCAL_SPI_ROM_SEL","FPGA_SPI_ROM_SEL","JTAG_MUX_S", + "JTAG_MUX_OE","HDT_SEL","ASERT_WARM_RST_BTN","FPGA_RSVD", + /*E0-E7*/ "","","MON_P0_PWR_BTN","MON_P0_RST_BTN","MON_P0_NMI_BTN", + "MON_P0_PWR_GOOD","MON_PWROK","MON_RESET", + /*F0-F7*/ "MON_P0_PROCHOT","MON_P1_PROCHOT","MON_P0_THERMTRIP", + "MON_P1_THERMTRIP","P0_PRESENT","P1_PRESENT","MON_ATX_PWR_OK","", + /*G0-G7*/ "BRD_REV_ID_3","BRD_REV_ID_2","BRD_REV_ID_1","BRD_REV_ID_0", + "P0_APML_ALERT","P1_APML_ALERT","FPGA ALERT","", + /*H0-H7*/ "BRD_ID_0","BRD_ID_1","BRD_ID_2","BRD_ID_3", + "PCIE_DISCONNECTED","USB_DISCONNECTED","SPARE_0","SPARE_1", + /*I0-I7*/ "","","","","","","","", + /*J0-J7*/ "","","","","","","","", + /*K0-K7*/ "","","","","","","","", + /*L0-L7*/ "","","","","","","","", + /*M0-M7*/ "ASSERT_PWR_BTN","ASSERT_RST_BTN","ASSERT_NMI_BTN", + "ASSERT_LOCAL_LOCK","ASSERT_P0_PROCHOT","ASSERT_P1_PROCHOT", + "ASSERT_CLR_CMOS","ASSERT_BMC_READY", + /*N0-N7*/ "","","","","","","","", + /*O0-O7*/ "","","","","","","","", + /*P0-P7*/ "P0_VDD_CORE_RUN_VRHOT","P0_VDD_SOC_RUN_VRHOT", + "P0_VDD_MEM_ABCD_SUS_VRHOT","P0_VDD_MEM_EFGH_SUS_VRHOT", + "P1_VDD_CORE_RUN_VRHOT","P1_VDD_SOC_RUN_VRHOT", + "P1_VDD_MEM_ABCD_SUS_VRHOT","P1_VDD_MEM_EFGH_SUS_VRHOT", + /*Q0-Q7*/ "","","","","","","","", + /*R0-R7*/ "","","","","","","","", + /*S0-S7*/ "","","","","","","","", + /*T0-T7*/ "","","","","","","","", + /*U0-U7*/ "","","","","","","","", + /*V0-V7*/ "","","","","","","","", + /*W0-W7*/ "","","","","","","","", + /*X0-X7*/ "","","","","","","","", + /*Y0-Y7*/ "","","","","","","","", + /*Z0-Z7*/ "","","","","","","","", + /*AA0-AA7*/ "","SENSOR THERM","","","","","","", + /*AB0-AB7*/ "","","","","","","","", + /*AC0-AC7*/ "","","","","","","",""; +}; + //APML for P0 &i2c0 { status = "okay"; From 1ca5f2430c4f9d85b98b8d6e5d93f8d4802faf8e Mon Sep 17 00:00:00 2001 From: Vivek Unune Date: Wed, 14 Oct 2020 15:27:27 -0400 Subject: [PATCH 284/799] ARM: dts: BCM5301X: Linksys EA9500 add port 5 and port 7 Add ports 5 and 7 which are connected to gmac cores 1 & 2. These will be disabled for now. Signed-off-by: Vivek Unune Signed-off-by: Florian Fainelli --- .../boot/dts/bcm47094-linksys-panamera.dts | 24 +++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm/boot/dts/bcm47094-linksys-panamera.dts b/arch/arm/boot/dts/bcm47094-linksys-panamera.dts index 0faae8950375..5d5930edfb9d 100644 --- a/arch/arm/boot/dts/bcm47094-linksys-panamera.dts +++ b/arch/arm/boot/dts/bcm47094-linksys-panamera.dts @@ -242,6 +242,30 @@ label = "wan"; }; + port@5 { + reg = <5>; + ethernet = <&gmac0>; + label = "cpu"; + status = "disabled"; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + + port@7 { + reg = <7>; + ethernet = <&gmac1>; + label = "cpu"; + status = "disabled"; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + port@8 { reg = <8>; ethernet = <&gmac2>; From 74abbfe99f43eb7466d26d9e48fbeb46b8f3d804 Mon Sep 17 00:00:00 2001 From: Serge Semin Date: Tue, 20 Oct 2020 14:59:37 +0300 Subject: [PATCH 285/799] ARM: dts: BCM5301X: Harmonize EHCI/OHCI DT nodes name In accordance with the Generic EHCI/OHCI bindings the corresponding node name is suppose to comply with the Generic USB HCD DT schema, which requires the USB nodes to have the name acceptable by the regexp: "^usb(@.*)?" . Make sure the "generic-ehci" and "generic-ohci"-compatible nodes are correctly named. Signed-off-by: Serge Semin Acked-by: Florian Fainelli Acked-by: Krzysztof Kozlowski Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm5301x.dtsi | 4 ++-- arch/arm/boot/dts/bcm53573.dtsi | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/bcm5301x.dtsi b/arch/arm/boot/dts/bcm5301x.dtsi index ac3a99cf2079..3ec6673f6c1e 100644 --- a/arch/arm/boot/dts/bcm5301x.dtsi +++ b/arch/arm/boot/dts/bcm5301x.dtsi @@ -265,7 +265,7 @@ interrupt-parent = <&gic>; - ehci: ehci@21000 { + ehci: usb@21000 { #usb-cells = <0>; compatible = "generic-ehci"; @@ -287,7 +287,7 @@ }; }; - ohci: ohci@22000 { + ohci: usb@22000 { #usb-cells = <0>; compatible = "generic-ohci"; diff --git a/arch/arm/boot/dts/bcm53573.dtsi b/arch/arm/boot/dts/bcm53573.dtsi index 4af8e3293cff..51546fccc616 100644 --- a/arch/arm/boot/dts/bcm53573.dtsi +++ b/arch/arm/boot/dts/bcm53573.dtsi @@ -135,7 +135,7 @@ #address-cells = <1>; #size-cells = <1>; - ehci: ehci@4000 { + ehci: usb@4000 { compatible = "generic-ehci"; reg = <0x4000 0x1000>; interrupt-parent = <&gic>; @@ -155,7 +155,7 @@ }; }; - ohci: ohci@d000 { + ohci: usb@d000 { #usb-cells = <0>; compatible = "generic-ohci"; From 4b650a20bdb5f9558007dd3055a17a1644a91c3e Mon Sep 17 00:00:00 2001 From: Serge Semin Date: Tue, 20 Oct 2020 14:59:46 +0300 Subject: [PATCH 286/799] ARM: dts: BCM5310X: Harmonize xHCI DT nodes name In accordance with the Generic xHCI bindings the corresponding node name is suppose to comply with the Generic USB HCD DT schema, which requires the USB nodes to have the name acceptable by the regexp: "^usb(@.*)?" . Make sure the "generic-xhci"-compatible nodes are correctly named. Signed-off-by: Serge Semin Acked-by: Krzysztof Kozlowski Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm5301x.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/bcm5301x.dtsi b/arch/arm/boot/dts/bcm5301x.dtsi index 3ec6673f6c1e..fcfaad4ffcb3 100644 --- a/arch/arm/boot/dts/bcm5301x.dtsi +++ b/arch/arm/boot/dts/bcm5301x.dtsi @@ -318,7 +318,7 @@ interrupt-parent = <&gic>; - xhci: xhci@23000 { + xhci: usb@23000 { #usb-cells = <0>; compatible = "generic-xhci"; From bd9a01e28e5d1632528e531480b42d6e2c861d88 Mon Sep 17 00:00:00 2001 From: Vivek Unune Date: Sun, 1 Nov 2020 15:08:03 -0500 Subject: [PATCH 287/799] ARM: dts: BCM5301X: Linksys EA9500 add fixed partitions This router has dual paritions to store trx firmware image and dual partitions for nvram. The second one in each of these cases acts as a backup store. When tested with OpenWrt, the default partition parser causes two issues: 1. It labels both nvram partitions as nvram. In factory, second one is labeled devinfo. 2. It parses second trx image and tries to create second 'linux' partition and fails with - cannot create duplicate 'linux' partition The following patch works around both of these issues. Signed-off-by: Vivek Unune Signed-off-by: Florian Fainelli --- .../boot/dts/bcm47094-linksys-panamera.dts | 41 +++++++++++++++++++ 1 file changed, 41 insertions(+) diff --git a/arch/arm/boot/dts/bcm47094-linksys-panamera.dts b/arch/arm/boot/dts/bcm47094-linksys-panamera.dts index 5d5930edfb9d..507af23e227f 100644 --- a/arch/arm/boot/dts/bcm47094-linksys-panamera.dts +++ b/arch/arm/boot/dts/bcm47094-linksys-panamera.dts @@ -292,3 +292,44 @@ &usb3_phy { status = "okay"; }; + +&nandcs { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "boot"; + reg = <0x0000000 0x0080000>; + read-only; + }; + + partition@80000 { + label = "nvram"; + reg = <0x080000 0x0100000>; + }; + + partition@180000{ + label = "devinfo"; + reg = <0x0180000 0x080000>; + }; + + partition@200000 { + label = "firmware"; + reg = <0x0200000 0x01D00000>; + compatible = "brcm,trx"; + }; + + partition@1F00000 { + label = "failsafe"; + reg = <0x01F00000 0x01D00000>; + read-only; + }; + + partition@5200000 { + label = "system"; + reg = <0x05200000 0x02E00000>; + }; + }; +}; From 2f34ae32f5e74096540cd7ce95bfd467cb74b21a Mon Sep 17 00:00:00 2001 From: Vivek Unune Date: Wed, 4 Nov 2020 15:29:51 -0500 Subject: [PATCH 288/799] ARM: dts: BCM5301X: Use corretc pinctrl compatible for 4709x MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit BCM47094 version of pinmux uses different compatible and supports MDIO pinmux pins. Hence, use the correct compatible string and defines the MDIO pins group. Signed-off-by: Vivek Unune Acked-by: Rafał Miłecki Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm47094.dtsi | 9 +++++++++ arch/arm/boot/dts/bcm5301x.dtsi | 2 +- 2 files changed, 10 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/bcm47094.dtsi b/arch/arm/boot/dts/bcm47094.dtsi index cdc5ff593adb..747ca030435f 100644 --- a/arch/arm/boot/dts/bcm47094.dtsi +++ b/arch/arm/boot/dts/bcm47094.dtsi @@ -8,6 +8,15 @@ / { }; +&pinctrl { + compatible = "brcm,bcm4709-pinmux"; + + pinmux_mdio: mdio { + groups = "mdio_grp"; + function = "mdio"; + }; +}; + &usb3_phy { compatible = "brcm,ns-bx-usb3-phy"; }; diff --git a/arch/arm/boot/dts/bcm5301x.dtsi b/arch/arm/boot/dts/bcm5301x.dtsi index fcfaad4ffcb3..bcb32fc698ab 100644 --- a/arch/arm/boot/dts/bcm5301x.dtsi +++ b/arch/arm/boot/dts/bcm5301x.dtsi @@ -428,7 +428,7 @@ #address-cells = <1>; #size-cells = <1>; - pin-controller@1c0 { + pinctrl: pin-controller@1c0 { compatible = "brcm,bcm4708-pinmux"; reg = <0x1c0 0x24>; reg-names = "cru_gpio_control"; From c862059875cffc013ee27bf9759ac288224e7a14 Mon Sep 17 00:00:00 2001 From: Vivek Unune Date: Wed, 4 Nov 2020 15:29:52 -0500 Subject: [PATCH 289/799] ARM: dts: BCM5301X: Linksys EA9500 make use of pinctrl Now that we have a pin controller, use that instead of manuplating the mdio/mdc pins directly. i.e. we no longer require the mdio-mii-mux Signed-off-by: Vivek Unune Signed-off-by: Florian Fainelli --- .../boot/dts/bcm47094-linksys-panamera.dts | 26 +++---------------- 1 file changed, 4 insertions(+), 22 deletions(-) diff --git a/arch/arm/boot/dts/bcm47094-linksys-panamera.dts b/arch/arm/boot/dts/bcm47094-linksys-panamera.dts index 507af23e227f..3bb3fe5bfbf8 100644 --- a/arch/arm/boot/dts/bcm47094-linksys-panamera.dts +++ b/arch/arm/boot/dts/bcm47094-linksys-panamera.dts @@ -123,33 +123,13 @@ }; }; - mdio-bus-mux { - #address-cells = <1>; - #size-cells = <0>; + mdio-bus-mux@18003000 { /* BIT(9) = 1 => external mdio */ - mdio_ext: mdio@200 { + mdio@200 { reg = <0x200>; #address-cells = <1>; #size-cells = <0>; - }; - }; - - mdio-mii-mux { - compatible = "mdio-mux-mmioreg"; - mdio-parent-bus = <&mdio_ext>; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x1800c1c0 0x4>; - - /* BIT(6) = mdc, BIT(7) = mdio */ - mux-mask = <0xc0>; - - mdio-mii@0 { - /* Enable MII function */ - reg = <0x0>; - #address-cells = <1>; - #size-cells = <0>; switch@0 { compatible = "brcm,bcm53125"; @@ -159,6 +139,8 @@ reset-names = "robo_reset"; reg = <0>; dsa,member = <1 0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinmux_mdio>; ports { #address-cells = <1>; From 776461b1795b4dc4084894cf53399044aafa1d21 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= Date: Wed, 11 Nov 2020 15:55:38 +0100 Subject: [PATCH 290/799] ARM: dts: BCM5301X: Move CRU devices to the CRU node MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Clocks and thermal blocks are part of the CRU ("Clock and Reset Unit" or "Central Resource Unit"). Signed-off-by: Rafał Miłecki Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm5301x.dtsi | 51 +++++++++++++++++---------------- 1 file changed, 26 insertions(+), 25 deletions(-) diff --git a/arch/arm/boot/dts/bcm5301x.dtsi b/arch/arm/boot/dts/bcm5301x.dtsi index bcb32fc698ab..90c09c48721b 100644 --- a/arch/arm/boot/dts/bcm5301x.dtsi +++ b/arch/arm/boot/dts/bcm5301x.dtsi @@ -428,6 +428,26 @@ #address-cells = <1>; #size-cells = <1>; + lcpll0: lcpll0@100 { + #clock-cells = <1>; + compatible = "brcm,nsp-lcpll0"; + reg = <0x100 0x14>; + clocks = <&osc>; + clock-output-names = "lcpll0", "pcie_phy", + "sdio", "ddr_phy"; + }; + + genpll: genpll@140 { + #clock-cells = <1>; + compatible = "brcm,nsp-genpll"; + reg = <0x140 0x24>; + clocks = <&osc>; + clock-output-names = "genpll", "phy", + "ethernetclk", + "usbclk", "iprocfast", + "sata1", "sata2"; + }; + pinctrl: pin-controller@1c0 { compatible = "brcm,bcm4708-pinmux"; reg = <0x1c0 0x24>; @@ -454,34 +474,15 @@ function = "uart1"; }; }; + + thermal: thermal@2c0 { + compatible = "brcm,ns-thermal"; + reg = <0x2c0 0x10>; + #thermal-sensor-cells = <0>; + }; }; }; - lcpll0: lcpll0@1800c100 { - #clock-cells = <1>; - compatible = "brcm,nsp-lcpll0"; - reg = <0x1800c100 0x14>; - clocks = <&osc>; - clock-output-names = "lcpll0", "pcie_phy", "sdio", - "ddr_phy"; - }; - - genpll: genpll@1800c140 { - #clock-cells = <1>; - compatible = "brcm,nsp-genpll"; - reg = <0x1800c140 0x24>; - clocks = <&osc>; - clock-output-names = "genpll", "phy", "ethernetclk", - "usbclk", "iprocfast", "sata1", - "sata2"; - }; - - thermal: thermal@1800c2c0 { - compatible = "brcm,ns-thermal"; - reg = <0x1800c2c0 0x10>; - #thermal-sensor-cells = <0>; - }; - srab: srab@18007000 { compatible = "brcm,bcm5301x-srab"; reg = <0x18007000 0x1000>; From 800b92ef92f3be6f635c31a411802afd29914dd8 Mon Sep 17 00:00:00 2001 From: Tao Ren Date: Wed, 11 Nov 2020 15:23:27 -0800 Subject: [PATCH 291/799] ARM: dts: aspeed: Common dtsi for Facebook AST2400 Network BMCs This common descirption is included by all Facebook AST2400 Network BMC platforms to minimize duplicated device entries across Facebook Network BMC device trees. Signed-off-by: Tao Ren Reviewed-by: Patrick Williams Reviewed-by: Joel Stanley Link: https://lore.kernel.org/r/20201111232330.30843-2-rentao.bupt@gmail.com Signed-off-by: Joel Stanley --- .../dts/ast2400-facebook-netbmc-common.dtsi | 117 ++++++++++++++++++ 1 file changed, 117 insertions(+) create mode 100644 arch/arm/boot/dts/ast2400-facebook-netbmc-common.dtsi diff --git a/arch/arm/boot/dts/ast2400-facebook-netbmc-common.dtsi b/arch/arm/boot/dts/ast2400-facebook-netbmc-common.dtsi new file mode 100644 index 000000000000..73a5503be78c --- /dev/null +++ b/arch/arm/boot/dts/ast2400-facebook-netbmc-common.dtsi @@ -0,0 +1,117 @@ +// SPDX-License-Identifier: GPL-2.0+ +// Copyright (c) 2020 Facebook Inc. +/dts-v1/; + +#include "aspeed-g4.dtsi" + +/ { + aliases { + /* + * Override the default uart aliases to avoid breaking + * the legacy applications. + */ + serial0 = &uart5; + serial1 = &uart1; + serial2 = &uart3; + serial3 = &uart4; + }; + + memory@40000000 { + reg = <0x40000000 0x20000000>; + }; +}; + +&wdt1 { + status = "okay"; + aspeed,reset-type = "system"; +}; + +&fmc { + status = "okay"; + flash@0 { + status = "okay"; + m25p,fast-read; + label = "spi0.0"; +#include "facebook-bmc-flash-layout.dtsi" + }; +}; + +&uart1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_txd1_default + &pinctrl_rxd1_default>; +}; + +&uart3 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_txd3_default + &pinctrl_rxd3_default>; +}; + +&uart4 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_txd4_default + &pinctrl_rxd4_default + &pinctrl_ndts4_default>; +}; + +&uart5 { + status = "okay"; +}; + +&mac1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>; +}; + +&i2c0 { + status = "okay"; +}; + +&i2c1 { + status = "okay"; +}; + +&i2c2 { + status = "okay"; +}; + +&i2c3 { + status = "okay"; +}; + +&i2c4 { + status = "okay"; +}; + +&i2c5 { + status = "okay"; +}; + +&i2c6 { + status = "okay"; +}; + +&i2c7 { + status = "okay"; +}; + +&i2c8 { + status = "okay"; +}; + +&i2c11 { + status = "okay"; +}; + +&i2c12 { + status = "okay"; +}; + +&vhub { + status = "okay"; +}; From e4c1633325fa4dca3b39c260881f9f6b55ca1031 Mon Sep 17 00:00:00 2001 From: Tao Ren Date: Wed, 11 Nov 2020 15:23:28 -0800 Subject: [PATCH 292/799] ARM: dts: aspeed: wedge40: Use common dtsi Simplify the Wedge40 device tree by using the common dtsi. Signed-off-by: Tao Ren Reviewed-by: Patrick Williams Reviewed-by: Joel Stanley Link: https://lore.kernel.org/r/20201111232330.30843-3-rentao.bupt@gmail.com Signed-off-by: Joel Stanley --- .../boot/dts/aspeed-bmc-facebook-wedge40.dts | 112 +----------------- 1 file changed, 1 insertion(+), 111 deletions(-) diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-wedge40.dts b/arch/arm/boot/dts/aspeed-bmc-facebook-wedge40.dts index 8c426ba2f8ab..2dcfeae3c92a 100644 --- a/arch/arm/boot/dts/aspeed-bmc-facebook-wedge40.dts +++ b/arch/arm/boot/dts/aspeed-bmc-facebook-wedge40.dts @@ -2,137 +2,27 @@ // Copyright (c) 2018 Facebook Inc. /dts-v1/; -#include "aspeed-g4.dtsi" +#include "ast2400-facebook-netbmc-common.dtsi" / { model = "Facebook Wedge 40 BMC"; compatible = "facebook,wedge40-bmc", "aspeed,ast2400"; - aliases { - /* - * Override the default uart aliases to avoid breaking - * the legacy applications. - */ - serial0 = &uart5; - serial1 = &uart1; - serial2 = &uart3; - serial3 = &uart4; - }; - chosen { stdout-path = &uart3; bootargs = "console=ttyS2,9600n8 root=/dev/ram rw"; }; - memory@40000000 { - reg = <0x40000000 0x20000000>; - }; - ast-adc-hwmon { compatible = "iio-hwmon"; io-channels = <&adc 5>, <&adc 6>, <&adc 7>, <&adc 8>, <&adc 9>; }; }; -&wdt1 { - status = "okay"; - aspeed,reset-type = "system"; -}; - &wdt2 { status = "disabled"; }; -&fmc { - status = "okay"; - flash@0 { - status = "okay"; - m25p,fast-read; - label = "spi0.0"; -#include "facebook-bmc-flash-layout.dtsi" - }; -}; - -&uart1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_txd1_default - &pinctrl_rxd1_default>; -}; - -&uart3 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_txd3_default - &pinctrl_rxd3_default>; -}; - -&uart4 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_txd4_default - &pinctrl_rxd4_default - &pinctrl_ndts4_default>; -}; - -&uart5 { - status = "okay"; -}; - -&mac1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>; -}; - -&i2c0 { - status = "okay"; -}; - -&i2c1 { - status = "okay"; -}; - -&i2c2 { - status = "okay"; -}; - -&i2c3 { - status = "okay"; -}; - -&i2c4 { - status = "okay"; -}; - -&i2c5 { - status = "okay"; -}; - -&i2c6 { - status = "okay"; -}; - -&i2c7 { - status = "okay"; -}; - -&i2c8 { - status = "okay"; -}; - -&i2c11 { - status = "okay"; -}; - -&i2c12 { - status = "okay"; -}; - -&vhub { - status = "okay"; -}; - &adc { status = "okay"; }; From 41376fb94c6a825674de3de27c6ee3af17065834 Mon Sep 17 00:00:00 2001 From: Tao Ren Date: Wed, 11 Nov 2020 15:23:29 -0800 Subject: [PATCH 293/799] ARM: dts: aspeed: wedge100: Use common dtsi Simplify the Wedge100 device tree by using the common dtsi. In addition this enables the second firmware flash, and turns on the "i2c-mux-idle-disconnect" flag for I2C switch 7-0070. Signed-off-by: Tao Ren Reviewed-by: Patrick Williams Reviewed-by: Joel Stanley Link: https://lore.kernel.org/r/20201111232330.30843-4-rentao.bupt@gmail.com Signed-off-by: Joel Stanley --- .../boot/dts/aspeed-bmc-facebook-wedge100.dts | 120 +++--------------- 1 file changed, 15 insertions(+), 105 deletions(-) diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-wedge100.dts b/arch/arm/boot/dts/aspeed-bmc-facebook-wedge100.dts index 322587b7b67d..39c6be91d53f 100644 --- a/arch/arm/boot/dts/aspeed-bmc-facebook-wedge100.dts +++ b/arch/arm/boot/dts/aspeed-bmc-facebook-wedge100.dts @@ -2,36 +2,16 @@ // Copyright (c) 2018 Facebook Inc. /dts-v1/; -#include "aspeed-g4.dtsi" +#include "ast2400-facebook-netbmc-common.dtsi" / { model = "Facebook Wedge 100 BMC"; compatible = "facebook,wedge100-bmc", "aspeed,ast2400"; - aliases { - /* - * Override the default uart aliases to avoid breaking - * the legacy applications. - */ - serial0 = &uart5; - serial1 = &uart1; - serial2 = &uart3; - serial3 = &uart4; - }; - chosen { stdout-path = &uart3; bootargs = "console=ttyS2,9600n8 root=/dev/ram rw"; }; - - memory@40000000 { - reg = <0x40000000 0x20000000>; - }; -}; - -&wdt1 { - status = "okay"; - aspeed,reset-type = "system"; }; &wdt2 { @@ -40,108 +20,38 @@ }; &fmc { - status = "okay"; - flash@0 { + flash@1 { status = "okay"; m25p,fast-read; - label = "fmc0"; -#include "facebook-bmc-flash-layout.dtsi" + label = "spi0.1"; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + flash1@0 { + reg = <0x0 0x2000000>; + label = "flash1"; + }; + }; }; }; -&uart1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_txd1_default - &pinctrl_rxd1_default>; -}; - -&uart3 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_txd3_default - &pinctrl_rxd3_default>; -}; - -&uart4 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_txd4_default - &pinctrl_rxd4_default>; -}; - -&uart5 { - status = "okay"; -}; - -&mac1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>; -}; - -&i2c0 { - status = "okay"; -}; - -&i2c1 { - status = "okay"; -}; - -&i2c2 { - status = "okay"; -}; - -&i2c3 { - status = "okay"; -}; - -&i2c4 { - status = "okay"; -}; - -&i2c5 { - status = "okay"; -}; - -&i2c6 { - status = "okay"; -}; - &i2c7 { - status = "okay"; - i2c-switch@70 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x70>; + i2c-mux-idle-disconnect; }; }; -&i2c8 { - status = "okay"; -}; - &i2c9 { status = "okay"; }; -&i2c10 { - status = "okay"; -}; - -&i2c11 { - status = "okay"; -}; - -&i2c12 { - status = "okay"; -}; - -&i2c13 { - status = "okay"; -}; &vhub { status = "okay"; From 71b802d2d518d2bdbdc0fa5b661fc1d37b9b50d3 Mon Sep 17 00:00:00 2001 From: Tao Ren Date: Wed, 11 Nov 2020 15:23:30 -0800 Subject: [PATCH 294/799] ARM: dts: aspeed: Add Facebook Galaxy100 (AST2400) BMC Add initial version of device tree for Facebook Galaxy100 (AST2400) BMC. Signed-off-by: Tao Ren Reviewed-by: Patrick Williams Reviewed-by: Joel Stanley Link: https://lore.kernel.org/r/20201111232330.30843-5-rentao.bupt@gmail.com Signed-off-by: Joel Stanley --- arch/arm/boot/dts/Makefile | 1 + .../dts/aspeed-bmc-facebook-galaxy100.dts | 57 +++++++++++++++++++ 2 files changed, 58 insertions(+) create mode 100644 arch/arm/boot/dts/aspeed-bmc-facebook-galaxy100.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 21477ef5c5c9..1917cd47204a 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1383,6 +1383,7 @@ dtb-$(CONFIG_ARCH_ASPEED) += \ aspeed-bmc-arm-stardragon4800-rep2.dtb \ aspeed-bmc-bytedance-g220a.dtb \ aspeed-bmc-facebook-cmm.dtb \ + aspeed-bmc-facebook-galaxy100.dtb \ aspeed-bmc-facebook-minipack.dtb \ aspeed-bmc-facebook-tiogapass.dtb \ aspeed-bmc-facebook-wedge40.dtb \ diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-galaxy100.dts b/arch/arm/boot/dts/aspeed-bmc-facebook-galaxy100.dts new file mode 100644 index 000000000000..dcf213472749 --- /dev/null +++ b/arch/arm/boot/dts/aspeed-bmc-facebook-galaxy100.dts @@ -0,0 +1,57 @@ +// SPDX-License-Identifier: GPL-2.0+ +// Copyright (c) 2020 Facebook Inc. +/dts-v1/; + +#include "ast2400-facebook-netbmc-common.dtsi" + +/ { + model = "Facebook Galaxy 100 BMC"; + compatible = "facebook,galaxy100-bmc", "aspeed,ast2400"; + + chosen { + stdout-path = &uart5; + bootargs = "console=ttyS0,9600n8 root=/dev/ram rw"; + }; + + ast-adc-hwmon { + compatible = "iio-hwmon"; + io-channels = <&adc 3>, <&adc 4>, <&adc 8>, <&adc 9>; + }; +}; + +&wdt2 { + status = "okay"; + aspeed,reset-type = "system"; +}; + +&fmc { + flash@1 { + status = "okay"; + m25p,fast-read; + label = "spi0.1"; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + flash1@0 { + reg = <0x0 0x2000000>; + label = "flash1"; + }; + }; + }; +}; + + +&i2c9 { + status = "okay"; +}; + +&vhub { + status = "okay"; +}; + +&adc { + status = "okay"; +}; From 6e6eae04f5123b7b2f4265f7a702b5200fa5863b Mon Sep 17 00:00:00 2001 From: Colin Ian King Date: Fri, 30 Oct 2020 14:30:02 +0000 Subject: [PATCH 295/799] SFH: fix error return check for -ERESTARTSYS Currently the check for the error return code -ERESTARTSYS is dead code and never executed because a previous check for ret < 0 is catching this and returning -ETIMEDOUT instead. Fix this by checking for -ERESTARTSYS before the more generic negative error code. Addresses-Coverity: ("Logically dead code") Fixes: 4b2c53d93a4b ("SFH:Transport Driver to add support of AMD Sensor Fusion Hub (SFH)") Signed-off-by: Colin Ian King Reviewed-by: Sandeep Singh Signed-off-by: Jiri Kosina --- drivers/hid/amd-sfh-hid/amd_sfh_hid.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/hid/amd-sfh-hid/amd_sfh_hid.c b/drivers/hid/amd-sfh-hid/amd_sfh_hid.c index a471079a3bd0..4f989483aa03 100644 --- a/drivers/hid/amd-sfh-hid/amd_sfh_hid.c +++ b/drivers/hid/amd-sfh-hid/amd_sfh_hid.c @@ -88,10 +88,10 @@ static int amdtp_wait_for_response(struct hid_device *hid) ret = wait_event_interruptible_timeout(hid_data->hid_wait, cli_data->request_done[i], msecs_to_jiffies(AMD_SFH_RESPONSE_TIMEOUT)); - if (ret < 0) - return -ETIMEDOUT; - else if (ret == -ERESTARTSYS) + if (ret == -ERESTARTSYS) return -ERESTARTSYS; + else if (ret < 0) + return -ETIMEDOUT; else return 0; } From 50301e8815c681bc5de8ca7050c4b426923d4e19 Mon Sep 17 00:00:00 2001 From: Tomi Valkeinen Date: Mon, 2 Nov 2020 15:46:50 +0200 Subject: [PATCH 296/799] arm64: dts: ti: k3-am65: mark dss as dma-coherent DSS is IO coherent on AM65, so we should mark it as such with 'dma-coherent' property in the DT file. Fixes: fc539b90eda2 ("arm64: dts: ti: am654: Add DSS node") Signed-off-by: Tomi Valkeinen Signed-off-by: Nishanth Menon Acked-by: Nikhil Devshatwar Cc: stable@vger.kernel.org # v5.8+ Link: https://lore.kernel.org/r/20201102134650.55321-1-tomi.valkeinen@ti.com --- arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi index 3eeb6e9876db..baa3f4c8f91e 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi @@ -866,6 +866,8 @@ status = "disabled"; + dma-coherent; + dss_ports: ports { #address-cells = <1>; #size-cells = <0>; From 5bb9e0f6e8505e31159963150104569d9b8a8911 Mon Sep 17 00:00:00 2001 From: Suman Anna Date: Wed, 28 Oct 2020 22:37:55 -0500 Subject: [PATCH 297/799] arm64: dts: ti: k3-am65-mcu: Add MCU domain R5F cluster node The AM65x SoCs have a single dual-core Arm Cortex-R5F processor (R5FSS) subsystem/cluster. This R5F cluster (MCU_R5FSS0) is present within the MCU domain, and can be configured at boot time to be either run in a LockStep mode or in an Asymmetric Multi Processing (AMP) fashion in Split-mode. This subsystem has 64 KB each Tightly-Coupled Memory (TCM) internal memories for each core split between two banks - TCMA and TCMB (further interleaved into two banks). There are some IP integration differences from standard Arm R5F clusters such as the absence of an ACP port, presence of an additional TI-specific Region Address Translater (RAT) module for translating 32-bit CPU addresses into larger system bus addresses etc. Add the DT node for this R5F cluster/subsystem, the two R5F cores are added as child nodes to the main cluster node. The cluster is configured to run in LockStep mode by default, with the ATCMs enabled to allow the R5 cores to execute code from DDR with boot-strapping code from ATCM. The inter-processor communication between the main A53 cores and these processors is achieved through shared memory and Mailboxes. The following firmware names are used by default for these cores, and can be overridden in a board dts file if needed: am65x-mcu-r5f0_0-fw (LockStep mode and for Core0 in Split mode) am65x-mcu-r5f0_1-fw (Core1 in Split mode) Signed-off-by: Suman Anna Signed-off-by: Nishanth Menon Reviewed-by: Lokesh Vutla Link: https://lore.kernel.org/r/20201029033802.15366-2-s-anna@ti.com --- arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi | 42 ++++++++++++++++++++++++- 1 file changed, 41 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi b/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi index 044042b166d9..7454c8cec0cc 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi @@ -2,7 +2,7 @@ /* * Device Tree Source for AM6 SoC Family MCU Domain peripherals * - * Copyright (C) 2016-2018 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2016-2020 Texas Instruments Incorporated - https://www.ti.com/ */ &cbass_mcu { @@ -268,4 +268,44 @@ }; }; }; + + mcu_r5fss0: r5fss@41000000 { + compatible = "ti,am654-r5fss"; + ti,cluster-mode = <1>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x41000000 0x00 0x41000000 0x20000>, + <0x41400000 0x00 0x41400000 0x20000>; + power-domains = <&k3_pds 129 TI_SCI_PD_EXCLUSIVE>; + + mcu_r5fss0_core0: r5f@41000000 { + compatible = "ti,am654-r5f"; + reg = <0x41000000 0x00008000>, + <0x41010000 0x00008000>; + reg-names = "atcm", "btcm"; + ti,sci = <&dmsc>; + ti,sci-dev-id = <159>; + ti,sci-proc-ids = <0x01 0xff>; + resets = <&k3_reset 159 1>; + firmware-name = "am65x-mcu-r5f0_0-fw"; + ti,atcm-enable = <1>; + ti,btcm-enable = <1>; + ti,loczrama = <1>; + }; + + mcu_r5fss0_core1: r5f@41400000 { + compatible = "ti,am654-r5f"; + reg = <0x41400000 0x00008000>, + <0x41410000 0x00008000>; + reg-names = "atcm", "btcm"; + ti,sci = <&dmsc>; + ti,sci-dev-id = <245>; + ti,sci-proc-ids = <0x02 0xff>; + resets = <&k3_reset 245 1>; + firmware-name = "am65x-mcu-r5f0_1-fw"; + ti,atcm-enable = <1>; + ti,btcm-enable = <1>; + ti,loczrama = <1>; + }; + }; }; From 10332cd6bcf287e22dac875d121b73adb762f96b Mon Sep 17 00:00:00 2001 From: Suman Anna Date: Wed, 28 Oct 2020 22:37:56 -0500 Subject: [PATCH 298/799] arm64: dts: ti: k3-am654-base-board: Add mailboxes to R5Fs Add the required 'mboxes' property to both the R5F processors on all the TI K3 AM65x boards. The mailboxes and some shared memory are required for running the Remote Processor Messaging (RPMsg) stack between the host processor and each of the R5Fs. The chosen sub-mailboxes match the values used in the current firmware images. This can be changed, if needed, as per the system integration needs after making appropriate changes on the firmware side as well. Note that the R5F Core1 resources are needed and used only when the R5F cluster is configured for Split-mode. Signed-off-by: Suman Anna Signed-off-by: Nishanth Menon Reviewed-by: Lokesh Vutla Link: https://lore.kernel.org/r/20201029033802.15366-3-s-anna@ti.com --- arch/arm64/boot/dts/ti/k3-am654-base-board.dts | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts index d12dd89f3405..0cb5b9cb65ba 100644 --- a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts +++ b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Copyright (C) 2016-2018 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2016-2020 Texas Instruments Incorporated - https://www.ti.com/ */ /dts-v1/; @@ -441,6 +441,14 @@ status = "disabled"; }; +&mcu_r5fss0_core0 { + mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; +}; + +&mcu_r5fss0_core1 { + mboxes = <&mailbox0_cluster1 &mbox_mcu_r5fss0_core1>; +}; + &ospi0 { pinctrl-names = "default"; pinctrl-0 = <&mcu_fss0_ospi0_pins_default>; From 954ec5139db091ff51cec4bf57c42f9deebc8747 Mon Sep 17 00:00:00 2001 From: Suman Anna Date: Wed, 28 Oct 2020 22:37:57 -0500 Subject: [PATCH 299/799] arm64: dts: ti: k3-am654-base-board: Add DDR carveout memory nodes for R5Fs The R5F processors do not have an MMU, and as such require the exact memory used by the firmwares to be set-aside. Four carveout reserved memory nodes have been added with two each (1 MB and 15 MB in size) used for each of the MCU R5F remote processor devices on all the TI K3 AM65x boards. These nodes are assigned to the respective rproc device nodes as well. The current carveout addresses and sizes are defined statically for each device. The first region will be used as the DMA pool for the rproc device, and the second region will furnish the static carveout regions for the firmware memory. Note that the R5F1 carveouts are needed only if the corresponding R5F cluster is running in Split (non-LockStep) mode. The corresponding reserved memory nodes can be disabled later on if there is no use-case defined to use the corresponding remote processor. Signed-off-by: Suman Anna Signed-off-by: Nishanth Menon Reviewed-by: Lokesh Vutla Link: https://lore.kernel.org/r/20201029033802.15366-4-s-anna@ti.com --- .../arm64/boot/dts/ti/k3-am654-base-board.dts | 29 +++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts index 0cb5b9cb65ba..23a1f266d1d4 100644 --- a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts +++ b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts @@ -29,11 +29,36 @@ #address-cells = <2>; #size-cells = <2>; ranges; + secure_ddr: secure-ddr@9e800000 { reg = <0 0x9e800000 0 0x01800000>; /* for OP-TEE */ alignment = <0x1000>; no-map; }; + + mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { + compatible = "shared-dma-pool"; + reg = <0 0xa0000000 0 0x100000>; + no-map; + }; + + mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 { + compatible = "shared-dma-pool"; + reg = <0 0xa0100000 0 0xf00000>; + no-map; + }; + + mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 { + compatible = "shared-dma-pool"; + reg = <0 0xa1000000 0 0x100000>; + no-map; + }; + + mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 { + compatible = "shared-dma-pool"; + reg = <0 0xa1100000 0 0xf00000>; + no-map; + }; }; gpio-keys { @@ -442,10 +467,14 @@ }; &mcu_r5fss0_core0 { + memory-region = <&mcu_r5fss0_core0_dma_memory_region>, + <&mcu_r5fss0_core0_memory_region>; mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; }; &mcu_r5fss0_core1 { + memory-region = <&mcu_r5fss0_core1_dma_memory_region>, + <&mcu_r5fss0_core1_memory_region>; mboxes = <&mailbox0_cluster1 &mbox_mcu_r5fss0_core1>; }; From f82c5e0a8bc1311aee140bfed0888fc9a99afde0 Mon Sep 17 00:00:00 2001 From: Suman Anna Date: Wed, 28 Oct 2020 22:37:58 -0500 Subject: [PATCH 300/799] arm64: dts: ti: k3-am654-base-board: Reserve memory for IPC between R5F cores Add a reserved memory node to reserve a portion of the DDR memory to be used for performing inter-processor communication between all the MCU R5F remote processors running RTOS on all the TI AM654 boards. This memory shall be exercised only if the MCU R5FSS cluster is configured for Split mode. A single 1 MB of memory at 0xa2000000 is reserved for this purpose, and this accounts for all the vrings and vring buffers between pair of these R5F remote processors. Signed-off-by: Suman Anna Signed-off-by: Nishanth Menon Reviewed-by: Lokesh Vutla Link: https://lore.kernel.org/r/20201029033802.15366-5-s-anna@ti.com --- arch/arm64/boot/dts/ti/k3-am654-base-board.dts | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts index 23a1f266d1d4..17f3a85360e6 100644 --- a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts +++ b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts @@ -59,6 +59,12 @@ reg = <0 0xa1100000 0 0xf00000>; no-map; }; + + rtos_ipc_memory_region: ipc-memories@a2000000 { + reg = <0x00 0xa2000000 0x00 0x00100000>; + alignment = <0x1000>; + no-map; + }; }; gpio-keys { From dd74c9459cf2c87c3143b4b9005b7c9056fccdb0 Mon Sep 17 00:00:00 2001 From: Suman Anna Date: Wed, 28 Oct 2020 22:37:59 -0500 Subject: [PATCH 301/799] arm64: dts: ti: k3-j721e-mcu: Add MCU domain R5F cluster node The J721E SoCs have 3 dual-core Arm Cortex-R5F processor (R5FSS) subsystems/clusters. One R5F cluster (MCU_R5FSS0) is present within the MCU domain, and the remaining two clusters are present in the MAIN domain (MAIN_R5FSS0 & MAIN_R5FSS1). Each of these can be configured at boot time to be either run in a LockStep mode or in an Asymmetric Multi Processing (AMP) fashion in Split-mode. These subsystems have 64 KB each Tightly-Coupled Memory (TCM) internal memories for each core split between two banks - ATCM and BTCM (further interleaved into two banks). There are some IP integration differences from standard Arm R5 clusters such as the absence of an ACP port, presence of an additional TI-specific Region Address Translater (RAT) module for translating 32-bit CPU addresses into larger system bus addresses etc. Add the DT node for the MCU domain R5F cluster/subsystem, the two R5F cores are added as child nodes to the main cluster/subsystem node. The cluster is configured to run in LockStep mode by default, with the ATCMs enabled to allow the R5 cores to execute code from DDR with boot-strapping code from ATCM. The inter-processor communication between the main A72 cores and these processors is achieved through shared memory and Mailboxes. The following firmware names are used by default for these cores, and can be overridden in a board dts file if needed: MCU R5FSS0 Core0: j7-mcu-r5f0_0-fw (both in LockStep and Split modes) MCU R5FSS0 Core1: j7-mcu-r5f0_1-fw (needed only in Split mode) Signed-off-by: Suman Anna Signed-off-by: Nishanth Menon Reviewed-by: Lokesh Vutla Link: https://lore.kernel.org/r/20201029033802.15366-6-s-anna@ti.com --- .../boot/dts/ti/k3-j721e-mcu-wakeup.dtsi | 42 ++++++++++++++++++- 1 file changed, 41 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi index e581cb1d87ee..6c44afae9187 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi @@ -2,7 +2,7 @@ /* * Device Tree Source for J721E SoC Family MCU/WAKEUP Domain peripherals * - * Copyright (C) 2016-2019 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2016-2020 Texas Instruments Incorporated - https://www.ti.com/ */ &cbass_mcu_wakeup { @@ -353,4 +353,44 @@ ti,cpts-periodic-outputs = <2>; }; }; + + mcu_r5fss0: r5fss@41000000 { + compatible = "ti,j721e-r5fss"; + ti,cluster-mode = <1>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x41000000 0x00 0x41000000 0x20000>, + <0x41400000 0x00 0x41400000 0x20000>; + power-domains = <&k3_pds 249 TI_SCI_PD_EXCLUSIVE>; + + mcu_r5fss0_core0: r5f@41000000 { + compatible = "ti,j721e-r5f"; + reg = <0x41000000 0x00008000>, + <0x41010000 0x00008000>; + reg-names = "atcm", "btcm"; + ti,sci = <&dmsc>; + ti,sci-dev-id = <250>; + ti,sci-proc-ids = <0x01 0xff>; + resets = <&k3_reset 250 1>; + firmware-name = "j7-mcu-r5f0_0-fw"; + ti,atcm-enable = <1>; + ti,btcm-enable = <1>; + ti,loczrama = <1>; + }; + + mcu_r5fss0_core1: r5f@41400000 { + compatible = "ti,j721e-r5f"; + reg = <0x41400000 0x00008000>, + <0x41410000 0x00008000>; + reg-names = "atcm", "btcm"; + ti,sci = <&dmsc>; + ti,sci-dev-id = <251>; + ti,sci-proc-ids = <0x02 0xff>; + resets = <&k3_reset 251 1>; + firmware-name = "j7-mcu-r5f0_1-fw"; + ti,atcm-enable = <1>; + ti,btcm-enable = <1>; + ti,loczrama = <1>; + }; + }; }; From df445ff9de893146107d37e0cd5e542f800d9b39 Mon Sep 17 00:00:00 2001 From: Suman Anna Date: Wed, 28 Oct 2020 22:38:00 -0500 Subject: [PATCH 302/799] arm64: dts: ti: k3-j721e-main: Add MAIN domain R5F cluster nodes The J721E SoCs have 3 dual-core Arm Cortex-R5F processor (R5FSS) subsystems/clusters. One R5F cluster (MCU_R5FSS0) is present within the MCU domain, and the remaining two clusters are present in the MAIN domain (MAIN_R5FSS0 & MAIN_R5FSS1). Each of these can be configured at boot time to be either run in a LockStep mode or in an Asymmetric Multi Processing (AMP) fashion in Split-mode. These subsystems have 64 KB each Tightly-Coupled Memory (TCM) internal memories for each core split between two banks - ATCM and BTCM (further interleaved into two banks). There are some IP integration differences from standard Arm R5 clusters such as the absence of an ACP port, presence of an additional TI-specific Region Address Translater (RAT) module for translating 32-bit CPU addresses into larger system bus addresses etc. Add the DT nodes for these two MAIN domain R5F cluster/subsystems, the two R5F cores are each added as child nodes to the corresponding main cluster node. Both the clusters are configured to run in LockStep mode by default, with the ATCMs enabled to allow the R5 cores to execute code from DDR with boot-strapping code from ATCM. The inter-processor communication between the main A72 cores and these processors is achieved through shared memory and Mailboxes. The following firmware names are used by default for these cores, and can be overridden in a board dts file if needed: MAIN R5FSS0 Core0: j7-main-r5f0_0-fw (both in LockStep and Split modes) MAIN R5FSS0 Core1: j7-main-r5f0_1-fw (needed only in Split mode) MAIN R5FSS1 Core0: j7-main-r5f1_0-fw (both in LockStep and Split modes) MAIN R5FSS1 Core1: j7-main-r5f1_1-fw (needed only in Split mode) Signed-off-by: Suman Anna Signed-off-by: Nishanth Menon Reviewed-by: Lokesh Vutla Link: https://lore.kernel.org/r/20201029033802.15366-7-s-anna@ti.com --- arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 82 ++++++++++++++++++++++- 1 file changed, 81 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi index e2a96b2c423c..b5cae2e03a09 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi @@ -2,7 +2,7 @@ /* * Device Tree Source for J721E SoC Family Main Domain peripherals * - * Copyright (C) 2016-2019 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2016-2020 Texas Instruments Incorporated - https://www.ti.com/ */ #include #include @@ -1581,6 +1581,86 @@ assigned-clock-parents = <&k3_clks 253 5>; }; + main_r5fss0: r5fss@5c00000 { + compatible = "ti,j721e-r5fss"; + ti,cluster-mode = <1>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x5c00000 0x00 0x5c00000 0x20000>, + <0x5d00000 0x00 0x5d00000 0x20000>; + power-domains = <&k3_pds 243 TI_SCI_PD_EXCLUSIVE>; + + main_r5fss0_core0: r5f@5c00000 { + compatible = "ti,j721e-r5f"; + reg = <0x5c00000 0x00008000>, + <0x5c10000 0x00008000>; + reg-names = "atcm", "btcm"; + ti,sci = <&dmsc>; + ti,sci-dev-id = <245>; + ti,sci-proc-ids = <0x06 0xff>; + resets = <&k3_reset 245 1>; + firmware-name = "j7-main-r5f0_0-fw"; + ti,atcm-enable = <1>; + ti,btcm-enable = <1>; + ti,loczrama = <1>; + }; + + main_r5fss0_core1: r5f@5d00000 { + compatible = "ti,j721e-r5f"; + reg = <0x5d00000 0x00008000>, + <0x5d10000 0x00008000>; + reg-names = "atcm", "btcm"; + ti,sci = <&dmsc>; + ti,sci-dev-id = <246>; + ti,sci-proc-ids = <0x07 0xff>; + resets = <&k3_reset 246 1>; + firmware-name = "j7-main-r5f0_1-fw"; + ti,atcm-enable = <1>; + ti,btcm-enable = <1>; + ti,loczrama = <1>; + }; + }; + + main_r5fss1: r5fss@5e00000 { + compatible = "ti,j721e-r5fss"; + ti,cluster-mode = <1>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x5e00000 0x00 0x5e00000 0x20000>, + <0x5f00000 0x00 0x5f00000 0x20000>; + power-domains = <&k3_pds 244 TI_SCI_PD_EXCLUSIVE>; + + main_r5fss1_core0: r5f@5e00000 { + compatible = "ti,j721e-r5f"; + reg = <0x5e00000 0x00008000>, + <0x5e10000 0x00008000>; + reg-names = "atcm", "btcm"; + ti,sci = <&dmsc>; + ti,sci-dev-id = <247>; + ti,sci-proc-ids = <0x08 0xff>; + resets = <&k3_reset 247 1>; + firmware-name = "j7-main-r5f1_0-fw"; + ti,atcm-enable = <1>; + ti,btcm-enable = <1>; + ti,loczrama = <1>; + }; + + main_r5fss1_core1: r5f@5f00000 { + compatible = "ti,j721e-r5f"; + reg = <0x5f00000 0x00008000>, + <0x5f10000 0x00008000>; + reg-names = "atcm", "btcm"; + ti,sci = <&dmsc>; + ti,sci-dev-id = <248>; + ti,sci-proc-ids = <0x09 0xff>; + resets = <&k3_reset 248 1>; + firmware-name = "j7-main-r5f1_1-fw"; + ti,atcm-enable = <1>; + ti,btcm-enable = <1>; + ti,loczrama = <1>; + }; + }; + c66_0: dsp@4d80800000 { compatible = "ti,j721e-c66-dsp"; reg = <0x4d 0x80800000 0x00 0x00048000>, From 2879b593c3784e5eafc67cae915d8b7d680455f3 Mon Sep 17 00:00:00 2001 From: Suman Anna Date: Wed, 28 Oct 2020 22:38:01 -0500 Subject: [PATCH 303/799] arm64: dts: ti: k3-j721e-som-p0: Add mailboxes to R5Fs Add the required 'mboxes' property to all the R5F processors for the TI J721E common processor board. The mailboxes and some shared memory are required for running the Remote Processor Messaging (RPMsg) stack between the host processor and each of the R5Fs. The nodes are therefore added in the common k3-j721e-som-p0.dtsi file so that all of these can be co-located. The chosen sub-mailboxes match the values used in the current firmware images. This can be changed, if needed, as per the system integration needs after making appropriate changes on the firmware side as well. Note that any R5F Core1 resources are needed and used only when that R5F cluster is configured for Split-mode. Signed-off-by: Suman Anna Signed-off-by: Nishanth Menon Reviewed-by: Lokesh Vutla Link: https://lore.kernel.org/r/20201029033802.15366-8-s-anna@ti.com --- arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi | 26 ++++++++++++++++++++- 1 file changed, 25 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi index 5dc3ba739131..c48f4ffd1435 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2019-2020 Texas Instruments Incorporated - https://www.ti.com/ */ /dts-v1/; @@ -208,6 +208,30 @@ status = "disabled"; }; +&mcu_r5fss0_core0 { + mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; +}; + +&mcu_r5fss0_core1 { + mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>; +}; + +&main_r5fss0_core0 { + mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>; +}; + +&main_r5fss0_core1 { + mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>; +}; + +&main_r5fss1_core0 { + mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core0>; +}; + +&main_r5fss1_core1 { + mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core1>; +}; + &c66_0 { mboxes = <&mailbox0_cluster3 &mbox_c66_0>; memory-region = <&c66_0_dma_memory_region>, From 0f191152bcba6758804eed4f6463f9bd32bdbfdb Mon Sep 17 00:00:00 2001 From: Suman Anna Date: Wed, 28 Oct 2020 22:38:02 -0500 Subject: [PATCH 304/799] arm64: dts: ti: k3-j721e-som-p0: Add DDR carveout memory nodes for R5Fs Two carveout reserved memory nodes each have been added for each of the R5F remote processor devices within both the MCU and MAIN domains for the TI J721E EVM boards. These nodes are assigned to the respective rproc device nodes as well. The first region will be used as the DMA pool for the rproc device, and the second region will furnish the static carveout regions for the firmware memory. The current carveout addresses and sizes are defined statically for each device. The R5F processors do not have an MMU, and as such require the exact memory used by the firmwares to be set-aside. The firmware images do not require any RSC_CARVEOUT entries in their resource tables either to allocate the memory for firmware memory segments. Note that the R5F1 carveouts are needed only if the R5F cluster is running in Split (non-LockStep) mode. The reserved memory nodes can be disabled later on if there is no use-case defined to use the corresponding remote processor. Signed-off-by: Suman Anna Signed-off-by: Nishanth Menon Reviewed-by: Lokesh Vutla Link: https://lore.kernel.org/r/20201029033802.15366-9-s-anna@ti.com --- arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi | 84 +++++++++++++++++++++ 1 file changed, 84 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi index c48f4ffd1435..57720e6a04c5 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi @@ -26,6 +26,78 @@ no-map; }; + mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa0000000 0x00 0x100000>; + no-map; + }; + + mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa0100000 0x00 0xf00000>; + no-map; + }; + + mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa1000000 0x00 0x100000>; + no-map; + }; + + mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa1100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa2000000 0x00 0x100000>; + no-map; + }; + + main_r5fss0_core0_memory_region: r5f-memory@a2100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa2100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa3000000 0x00 0x100000>; + no-map; + }; + + main_r5fss0_core1_memory_region: r5f-memory@a3100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa3100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a4000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa4000000 0x00 0x100000>; + no-map; + }; + + main_r5fss1_core0_memory_region: r5f-memory@a4100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa4100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a5000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa5000000 0x00 0x100000>; + no-map; + }; + + main_r5fss1_core1_memory_region: r5f-memory@a5100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa5100000 0x00 0xf00000>; + no-map; + }; + c66_1_dma_memory_region: c66-dma-memory@a6000000 { compatible = "shared-dma-pool"; reg = <0x00 0xa6000000 0x00 0x100000>; @@ -210,26 +282,38 @@ &mcu_r5fss0_core0 { mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; + memory-region = <&mcu_r5fss0_core0_dma_memory_region>, + <&mcu_r5fss0_core0_memory_region>; }; &mcu_r5fss0_core1 { mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>; + memory-region = <&mcu_r5fss0_core1_dma_memory_region>, + <&mcu_r5fss0_core1_memory_region>; }; &main_r5fss0_core0 { mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>; + memory-region = <&main_r5fss0_core0_dma_memory_region>, + <&main_r5fss0_core0_memory_region>; }; &main_r5fss0_core1 { mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>; + memory-region = <&main_r5fss0_core1_dma_memory_region>, + <&main_r5fss0_core1_memory_region>; }; &main_r5fss1_core0 { mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core0>; + memory-region = <&main_r5fss1_core0_dma_memory_region>, + <&main_r5fss1_core0_memory_region>; }; &main_r5fss1_core1 { mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core1>; + memory-region = <&main_r5fss1_core1_dma_memory_region>, + <&main_r5fss1_core1_memory_region>; }; &c66_0 { From cfbf17e69ae82f647c287366b7573e532fc281ee Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Wed, 4 Nov 2020 16:25:19 -0600 Subject: [PATCH 305/799] arm64: dts: ti: k3-am65*/j721e*: Fix unit address format error for dss node Fix the node address to follow the device tree convention. This fixes the dtc warning: : Warning (simple_bus_reg): /bus@100000/dss@04a00000: simple-bus unit address format error, expected "4a00000" Fixes: 76921f15acc0 ("arm64: dts: ti: k3-j721e-main: Add DSS node") Fixes: fc539b90eda2 ("arm64: dts: ti: am654: Add DSS node") Signed-off-by: Nishanth Menon Reviewed-by: Jyri Sarha Reviewed-by: Tomi Valkeinen Cc: Jyri Sarha Cc: Tomi Valkeinen Link: https://lore.kernel.org/r/20201104222519.12308-1-nm@ti.com --- arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 2 +- arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi index baa3f4c8f91e..a664c91675de 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi @@ -833,7 +833,7 @@ }; }; - dss: dss@04a00000 { + dss: dss@4a00000 { compatible = "ti,am65x-dss"; reg = <0x0 0x04a00000 0x0 0x1000>, /* common */ <0x0 0x04a02000 0x0 0x1000>, /* vidl1 */ diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi index b5cae2e03a09..620e69e42974 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi @@ -1278,7 +1278,7 @@ }; }; - dss: dss@04a00000 { + dss: dss@4a00000 { compatible = "ti,j721e-dss"; reg = <0x00 0x04a00000 0x00 0x10000>, /* common_m */ From 6b133f475a97a0839f02e3c0b937886b9adc2933 Mon Sep 17 00:00:00 2001 From: Faiz Abbas Date: Wed, 4 Nov 2020 00:38:21 +0530 Subject: [PATCH 306/799] arm64: defconfig: Enable GPIO and I2C configs for TI's J721e platform Add configs to enable regulators that supply power to the SD card on TI's J721e platform. These regulators are controlled by either SoC gpios or gpios over i2c expander. Changes to vmlinux size: Before: text data bss dec hex filename 20219067 10875634 523924 31618625 1e27641 vmlinux After: text data bss dec hex filename 20228755 10880422 524628 31633805 1e2b18d vmlinux delta: 15180 (dec) Signed-off-by: Faiz Abbas Signed-off-by: Nishanth Menon Acked-by: Tero Kristo Link: https://lore.kernel.org/r/20201103190821.30937-1-faiz_abbas@ti.com --- arch/arm64/configs/defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 17a2df6a263e..b110200988fd 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -438,6 +438,7 @@ CONFIG_I2C_IMX=y CONFIG_I2C_IMX_LPI2C=y CONFIG_I2C_MESON=y CONFIG_I2C_MV64XXX=y +CONFIG_I2C_OMAP=y CONFIG_I2C_OWL=y CONFIG_I2C_PXA=y CONFIG_I2C_QCOM_CCI=m @@ -497,6 +498,7 @@ CONFIG_PINCTRL_SDM845=y CONFIG_PINCTRL_SM8150=y CONFIG_PINCTRL_SM8250=y CONFIG_GPIO_ALTERA=m +CONFIG_GPIO_DAVINCI=y CONFIG_GPIO_DWAPB=y CONFIG_GPIO_MB86S7X=y CONFIG_GPIO_MPC8XXX=y From e6b4516815b61a9e6d27a31edf385d34c8009691 Mon Sep 17 00:00:00 2001 From: Vignesh Raghavendra Date: Thu, 29 Oct 2020 10:39:50 +0530 Subject: [PATCH 307/799] arm64: dts: ti: k3-j7200-mcu-wakeup: Enable ADC support J7200 has a single instance of 8 channel ADC in MCU domain. Add DT node for the same. Signed-off-by: Vignesh Raghavendra Signed-off-by: Nishanth Menon Reviewed-by: Sekhar Nori Link: https://lore.kernel.org/r/20201029050950.4500-1-vigneshr@ti.com --- .../dts/ti/k3-j7200-common-proc-board.dts | 6 ++++++ .../boot/dts/ti/k3-j7200-mcu-wakeup.dtsi | 19 +++++++++++++++++++ 2 files changed, 25 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts index ef03e7636b66..7d2ff1c3b50f 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts @@ -213,3 +213,9 @@ dr_mode = "otg"; maximum-speed = "high-speed"; }; + +&tscadc0 { + adc { + ti,adc-channels = <0 1 2 3 4 5 6 7>; + }; +}; diff --git a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi index eb2a78a53512..bb1fe9c12e44 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi @@ -270,4 +270,23 @@ mux-controls = <&hbmc_mux 0>; }; }; + + tscadc0: tscadc@40200000 { + compatible = "ti,am3359-tscadc"; + reg = <0x00 0x40200000 0x00 0x1000>; + interrupts = ; + power-domains = <&k3_pds 0 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 0 1>; + assigned-clocks = <&k3_clks 0 3>; + assigned-clock-rates = <60000000>; + clock-names = "adc_tsc_fck"; + dmas = <&main_udmap 0x7400>, + <&main_udmap 0x7401>; + dma-names = "fifo0", "fifo1"; + + adc { + #io-channel-cells = <1>; + compatible = "ti,am3359-adc"; + }; + }; }; From 3fccd03a527fa1c9490e528a369d1c9d9c622b01 Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Fri, 13 Nov 2020 08:34:44 -0800 Subject: [PATCH 308/799] arm64: defconfig: Enable Qualcomm OSM L3 driver The OSM L3 interconnect driver is used for scaling the bus to the L3 cache on modern Qualcomm platforms, enable it. Reviewed-by: Georgi Djakov Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20201113163444.3138807-1-bjorn.andersson@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 741c2ebcf443..ed8b7df52abf 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -1042,6 +1042,7 @@ CONFIG_MUX_MMIO=y CONFIG_INTERCONNECT=y CONFIG_INTERCONNECT_QCOM=y CONFIG_INTERCONNECT_QCOM_MSM8916=m +CONFIG_INTERCONNECT_QCOM_OSM_L3=m CONFIG_INTERCONNECT_QCOM_SDM845=m CONFIG_INTERCONNECT_QCOM_SM8150=m CONFIG_INTERCONNECT_QCOM_SM8250=m From 632ddf978565378e7efb9ea77c0ba239ea66bfdc Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= Date: Fri, 13 Nov 2020 11:09:19 +0100 Subject: [PATCH 309/799] ARM: dts: BCM5301X: Disable USB 3 PHY on devices without USB 3 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit It seems pointless to have it enabled. Signed-off-by: Rafał Miłecki Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm4708-luxul-xap-1510.dts | 4 ---- arch/arm/boot/dts/bcm4708-luxul-xwc-1000.dts | 4 ---- arch/arm/boot/dts/bcm47081-buffalo-wzr-600dhp2.dts | 4 ---- arch/arm/boot/dts/bcm47081-luxul-xap-1410.dts | 4 ---- arch/arm/boot/dts/bcm47081-luxul-xwr-1200.dts | 4 ---- arch/arm/boot/dts/bcm47081-tplink-archer-c5-v2.dts | 4 ---- 6 files changed, 24 deletions(-) diff --git a/arch/arm/boot/dts/bcm4708-luxul-xap-1510.dts b/arch/arm/boot/dts/bcm4708-luxul-xap-1510.dts index 810fc32f1895..7f07b78c1ac3 100644 --- a/arch/arm/boot/dts/bcm4708-luxul-xap-1510.dts +++ b/arch/arm/boot/dts/bcm4708-luxul-xap-1510.dts @@ -57,10 +57,6 @@ status = "okay"; }; -&usb3_phy { - status = "okay"; -}; - &srab { status = "okay"; diff --git a/arch/arm/boot/dts/bcm4708-luxul-xwc-1000.dts b/arch/arm/boot/dts/bcm4708-luxul-xwc-1000.dts index 7604b4480bb1..548faa0c44c8 100644 --- a/arch/arm/boot/dts/bcm4708-luxul-xwc-1000.dts +++ b/arch/arm/boot/dts/bcm4708-luxul-xwc-1000.dts @@ -64,10 +64,6 @@ status = "okay"; }; -&usb3_phy { - status = "okay"; -}; - &srab { status = "okay"; diff --git a/arch/arm/boot/dts/bcm47081-buffalo-wzr-600dhp2.dts b/arch/arm/boot/dts/bcm47081-buffalo-wzr-600dhp2.dts index 4dcec6865469..2f2d2b0a6893 100644 --- a/arch/arm/boot/dts/bcm47081-buffalo-wzr-600dhp2.dts +++ b/arch/arm/boot/dts/bcm47081-buffalo-wzr-600dhp2.dts @@ -117,7 +117,3 @@ }; }; }; - -&usb3_phy { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/bcm47081-luxul-xap-1410.dts b/arch/arm/boot/dts/bcm47081-luxul-xap-1410.dts index 1ec655809e57..944e81cab338 100644 --- a/arch/arm/boot/dts/bcm47081-luxul-xap-1410.dts +++ b/arch/arm/boot/dts/bcm47081-luxul-xap-1410.dts @@ -57,10 +57,6 @@ status = "okay"; }; -&usb3_phy { - status = "okay"; -}; - &srab { status = "okay"; diff --git a/arch/arm/boot/dts/bcm47081-luxul-xwr-1200.dts b/arch/arm/boot/dts/bcm47081-luxul-xwr-1200.dts index 04bfd58127fc..d1ae7dc10775 100644 --- a/arch/arm/boot/dts/bcm47081-luxul-xwr-1200.dts +++ b/arch/arm/boot/dts/bcm47081-luxul-xwr-1200.dts @@ -105,10 +105,6 @@ status = "okay"; }; -&usb3_phy { - status = "okay"; -}; - &srab { status = "okay"; diff --git a/arch/arm/boot/dts/bcm47081-tplink-archer-c5-v2.dts b/arch/arm/boot/dts/bcm47081-tplink-archer-c5-v2.dts index 01c390ed48ea..12e34a0439b4 100644 --- a/arch/arm/boot/dts/bcm47081-tplink-archer-c5-v2.dts +++ b/arch/arm/boot/dts/bcm47081-tplink-archer-c5-v2.dts @@ -126,7 +126,3 @@ &usb2 { vcc-gpio = <&chipcommon 9 GPIO_ACTIVE_HIGH>; }; - -&usb3_phy { - status = "okay"; -}; From b2ab5e8697ef6591aeeda23be49e096705dbbda3 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= Date: Fri, 13 Nov 2020 10:50:12 +0100 Subject: [PATCH 310/799] ARM: dts: BCM5301X: Enable USB 3 PHY on Luxul XWR-3150 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This device has a functional USB 3 port so PHY is required. Signed-off-by: Rafał Miłecki Reported-by: kernel test robot Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm47094-luxul-xwr-3150-v1.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/bcm47094-luxul-xwr-3150-v1.dts b/arch/arm/boot/dts/bcm47094-luxul-xwr-3150-v1.dts index 4d5c5aa7dc42..a361aa8627d3 100644 --- a/arch/arm/boot/dts/bcm47094-luxul-xwr-3150-v1.dts +++ b/arch/arm/boot/dts/bcm47094-luxul-xwr-3150-v1.dts @@ -71,6 +71,10 @@ vcc-gpio = <&chipcommon 18 GPIO_ACTIVE_HIGH>; }; +&usb3_phy { + status = "okay"; +}; + &spi_nor { status = "okay"; }; From f949d414fc1a9dfdfc878134629052135bd527db Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C5=81ukasz=20Stelmach?= Date: Tue, 3 Nov 2020 19:44:07 +0100 Subject: [PATCH 311/799] ARM: dts: exynos: Fix Ethernet interface description on Odroid XU3 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Assign appropriate compatible properties matching real USB vendor and product ID. Signed-off-by: Łukasz Stelmach Link: https://lore.kernel.org/r/20201103184412.18874-2-l.stelmach@samsung.com Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos5422-odroidxu3.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3.dts b/arch/arm/boot/dts/exynos5422-odroidxu3.dts index 53aee3d56f6a..cdd3a5fef216 100644 --- a/arch/arm/boot/dts/exynos5422-odroidxu3.dts +++ b/arch/arm/boot/dts/exynos5422-odroidxu3.dts @@ -76,13 +76,13 @@ #size-cells = <0>; hub@1 { - compatible = "usb8087,0024"; + compatible = "usb0424,9514"; reg = <1>; #address-cells = <1>; #size-cells = <0>; ethernet: usbether@1 { - compatible = "usb0c45,6310"; + compatible = "usb0424,ec00"; reg = <1>; local-mac-address = [00 00 00 00 00 00]; /* Filled in by a bootloader */ }; From c0f5d3873bc806f32584558fc1c8c593758c2967 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C5=81ukasz=20Stelmach?= Date: Tue, 3 Nov 2020 19:44:08 +0100 Subject: [PATCH 312/799] ARM: dts: exynos: Add an alias for the Ethernet interface on Odroid XU3 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add an alias to enable bootloaders to find the Ethernet interface and assign a MAC address. Signed-off-by: Łukasz Stelmach Link: https://lore.kernel.org/r/20201103184412.18874-3-l.stelmach@samsung.com Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos5422-odroidxu3.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3.dts b/arch/arm/boot/dts/exynos5422-odroidxu3.dts index cdd3a5fef216..cecaeb69e623 100644 --- a/arch/arm/boot/dts/exynos5422-odroidxu3.dts +++ b/arch/arm/boot/dts/exynos5422-odroidxu3.dts @@ -15,6 +15,10 @@ / { model = "Hardkernel Odroid XU3"; compatible = "hardkernel,odroid-xu3", "samsung,exynos5800", "samsung,exynos5"; + + aliases { + ethernet = ðernet; + }; }; &i2c_0 { From 7f415677420ff97dd7792eab02dd00e25fcd1f15 Mon Sep 17 00:00:00 2001 From: Jonathan Cameron Date: Sun, 15 Nov 2020 19:29:45 +0000 Subject: [PATCH 313/799] ARM: dts: Cygnus: Drop incorrect io-channel-ranges property. This property applies to consumers of io-channels. In this case we have a provider so the property is not used. Recent changes to dt-schema result int his being reported as an error as a dependency is enforced between this property and io-channels. Signed-off-by: Jonathan Cameron Cc: Florian Fainelli Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm-cygnus.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm/boot/dts/bcm-cygnus.dtsi b/arch/arm/boot/dts/bcm-cygnus.dtsi index dacaef2c14ca..0025c88f660c 100644 --- a/arch/arm/boot/dts/bcm-cygnus.dtsi +++ b/arch/arm/boot/dts/bcm-cygnus.dtsi @@ -591,7 +591,6 @@ adc: adc@180a6000 { compatible = "brcm,iproc-static-adc"; #io-channel-cells = <1>; - io-channel-ranges; adc-syscon = <&ts_adc_syscon>; clocks = <&asiu_clks BCM_CYGNUS_ASIU_ADC_CLK>; clock-names = "tsc_clk"; From c9f6aa9d1f50fa1b6429bfa9cb50648379b1c710 Mon Sep 17 00:00:00 2001 From: Tao Ren Date: Mon, 9 Nov 2020 23:21:59 -0800 Subject: [PATCH 314/799] ARM: dts: aspeed: wedge400: Fix FMC flash0 layout Update "data0" partition's size from 8MB to 4MB to fix "partition data0 extends beyond the end of device" warning at bootup time. Signed-off-by: Tao Ren Reviewed-by: Joel Stanley Link: https://lore.kernel.org/r/20201110072159.7941-1-rentao.bupt@gmail.com Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-bmc-facebook-wedge400.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-wedge400.dts b/arch/arm/boot/dts/aspeed-bmc-facebook-wedge400.dts index ad1fcad3676c..63a3dd548f30 100644 --- a/arch/arm/boot/dts/aspeed-bmc-facebook-wedge400.dts +++ b/arch/arm/boot/dts/aspeed-bmc-facebook-wedge400.dts @@ -124,8 +124,8 @@ * "data0" partition (4MB) is reserved for persistent * data store. */ - data0@3800000 { - reg = <0x7c00000 0x800000>; + data0@7c00000 { + reg = <0x7c00000 0x400000>; label = "data0"; }; From 2e7cd913eafcdfa008565d91e9d1f253f89f7c3b Mon Sep 17 00:00:00 2001 From: Tao Ren Date: Mon, 9 Nov 2020 23:24:46 -0800 Subject: [PATCH 315/799] ARM: dts: aspeed: minipack: Fixup I2C tree Create all the i2c switches in device tree and use aliases to assign child channels with consistent bus numbers. Besides, "i2c-mux-idle-disconnect" is set for all the i2c switches to avoid potential conflicts when multiple devices (beind the switches) use the same device address. Signed-off-by: Tao Ren Reviewed-by: Joel Stanley Link: https://lore.kernel.org/r/20201110072446.8218-1-rentao.bupt@gmail.com Signed-off-by: Joel Stanley --- .../boot/dts/aspeed-bmc-facebook-minipack.dts | 888 ++++++++++++++++++ 1 file changed, 888 insertions(+) diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-minipack.dts b/arch/arm/boot/dts/aspeed-bmc-facebook-minipack.dts index c34741dbd268..9eb23e874f19 100644 --- a/arch/arm/boot/dts/aspeed-bmc-facebook-minipack.dts +++ b/arch/arm/boot/dts/aspeed-bmc-facebook-minipack.dts @@ -70,6 +70,162 @@ i2c45 = &imux45; i2c46 = &imux46; i2c47 = &imux47; + + /* + * I2C Switch 24-0071 (channel #0 of 8-0070): 8 channels for + * connecting to left PDB (Power Distribution Board). + */ + i2c48 = &imux48; + i2c49 = &imux49; + i2c50 = &imux50; + i2c51 = &imux51; + i2c52 = &imux52; + i2c53 = &imux53; + i2c54 = &imux54; + i2c55 = &imux55; + + /* + * I2C Switch 25-0072 (channel #1 of 8-0070): 8 channels for + * connecting to right PDB (Power Distribution Board). + */ + i2c56 = &imux56; + i2c57 = &imux57; + i2c58 = &imux58; + i2c59 = &imux59; + i2c60 = &imux60; + i2c61 = &imux61; + i2c62 = &imux62; + i2c63 = &imux63; + + /* + * I2C Switch 26-0076 (channel #2 of 8-0070): 8 channels for + * connecting to top FCM (Fan Control Module). + */ + i2c64 = &imux64; + i2c65 = &imux65; + i2c66 = &imux66; + i2c67 = &imux67; + i2c68 = &imux68; + i2c69 = &imux69; + i2c70 = &imux70; + i2c71 = &imux71; + + /* + * I2C Switch 27-0076 (channel #3 of 8-0070): 8 channels for + * connecting to bottom FCM (Fan Control Module). + */ + i2c72 = &imux72; + i2c73 = &imux73; + i2c74 = &imux74; + i2c75 = &imux75; + i2c76 = &imux76; + i2c77 = &imux77; + i2c78 = &imux78; + i2c79 = &imux79; + + /* + * I2C Switch 40-0073 (channel #0 of 11-0070): connecting + * to PIM (Port Interface Module) #1 (1-based). + */ + i2c80 = &imux80; + i2c81 = &imux81; + i2c82 = &imux82; + i2c83 = &imux83; + i2c84 = &imux84; + i2c85 = &imux85; + i2c86 = &imux86; + i2c87 = &imux87; + + /* + * I2C Switch 41-0073 (channel #1 of 11-0070): connecting + * to PIM (Port Interface Module) #2 (1-based). + */ + i2c88 = &imux88; + i2c89 = &imux89; + i2c90 = &imux90; + i2c91 = &imux91; + i2c92 = &imux92; + i2c93 = &imux93; + i2c94 = &imux94; + i2c95 = &imux95; + + /* + * I2C Switch 42-0073 (channel #2 of 11-0070): connecting + * to PIM (Port Interface Module) #3 (1-based). + */ + i2c96 = &imux96; + i2c97 = &imux97; + i2c98 = &imux98; + i2c99 = &imux99; + i2c100 = &imux100; + i2c101 = &imux101; + i2c102 = &imux102; + i2c103 = &imux103; + + /* + * I2C Switch 43-0073 (channel #3 of 11-0070): connecting + * to PIM (Port Interface Module) #4 (1-based). + */ + i2c104 = &imux104; + i2c105 = &imux105; + i2c106 = &imux106; + i2c107 = &imux107; + i2c108 = &imux108; + i2c109 = &imux109; + i2c110 = &imux110; + i2c111 = &imux111; + + /* + * I2C Switch 44-0073 (channel #4 of 11-0070): connecting + * to PIM (Port Interface Module) #5 (1-based). + */ + i2c112 = &imux112; + i2c113 = &imux113; + i2c114 = &imux114; + i2c115 = &imux115; + i2c116 = &imux116; + i2c117 = &imux117; + i2c118 = &imux118; + i2c119 = &imux119; + + /* + * I2C Switch 45-0073 (channel #5 of 11-0070): connecting + * to PIM (Port Interface Module) #6 (1-based). + */ + i2c120 = &imux120; + i2c121 = &imux121; + i2c122 = &imux122; + i2c123 = &imux123; + i2c124 = &imux124; + i2c125 = &imux125; + i2c126 = &imux126; + i2c127 = &imux127; + + /* + * I2C Switch 46-0073 (channel #6 of 11-0070): connecting + * to PIM (Port Interface Module) #7 (1-based). + */ + i2c128 = &imux128; + i2c129 = &imux129; + i2c130 = &imux130; + i2c131 = &imux131; + i2c132 = &imux132; + i2c133 = &imux133; + i2c134 = &imux134; + i2c135 = &imux135; + + /* + * I2C Switch 47-0073 (channel #7 of 11-0070): connecting + * to PIM (Port Interface Module) #8 (1-based). + */ + i2c136 = &imux136; + i2c137 = &imux137; + i2c138 = &imux138; + i2c139 = &imux139; + i2c140 = &imux140; + i2c141 = &imux141; + i2c142 = &imux142; + i2c143 = &imux143; }; chosen { @@ -184,11 +340,16 @@ &i2c2 { status = "okay"; + /* + * I2C Switch 2-0070 is connecting to SCM (System Controller + * Module). + */ i2c-switch@70 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x70>; + i2c-mux-idle-disconnect; imux16: i2c@0 { #address-cells = <1>; @@ -269,29 +430,270 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x70>; + i2c-mux-idle-disconnect; + /* + * I2C Switch 8-0070 channel #0: connecting to left PDB + * (Power Distribution Board). + */ imux24: i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; + + i2c-switch@71 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x71>; + i2c-mux-idle-disconnect; + + imux48: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + imux49: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + imux50: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + imux51: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + + imux52: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + + imux53: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + + imux54: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + }; + + imux55: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + }; + }; }; + /* + * I2C Switch 8-0070 channel #1: connecting to right PDB + * (Power Distribution Board). + */ imux25: i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; + + i2c-switch@72 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x72>; + i2c-mux-idle-disconnect; + + imux56: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + imux57: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + imux58: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + imux59: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + + imux60: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + + imux61: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + + imux62: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + }; + + imux63: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + }; + }; }; + /* + * I2C Switch 8-0070 channel #2: connecting to top FCM + * (Fan Control Module). + */ imux26: i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; + + i2c-switch@76 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x76>; + i2c-mux-idle-disconnect; + + imux64: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + imux65: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + imux66: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + imux67: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + + imux68: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + + imux69: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + + imux70: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + }; + + imux71: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + }; + }; }; + /* + * I2C Switch 8-0070 channel #3: connecting to bottom + * FCM (Fan Control Module). + */ imux27: i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; + + i2c-switch@76 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x76>; + i2c-mux-idle-disconnect; + + imux72: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + imux73: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + imux74: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + imux75: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + + imux76: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + + imux77: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + + imux78: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + }; + + imux79: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + }; + }; }; imux28: i2c@4 { @@ -323,11 +725,16 @@ &i2c9 { status = "okay"; + /* + * I2C Switch 9-0070 is connecting to MAC/PHY EEPROMs on SMB + * (Switch Main Board). + */ i2c-switch@70 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x70>; + i2c-mux-idle-disconnect; imux32: i2c@0 { #address-cells = <1>; @@ -391,53 +798,534 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x70>; + i2c-mux-idle-disconnect; + /* + * I2C Switch 11-0070 channel #0: connecting to PIM + * (Port Interface Module) #1 (1-based). + */ imux40: i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; + + i2c-switch@73 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x73>; + i2c-mux-idle-disconnect; + + imux80: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + imux81: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + imux82: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + imux83: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + + imux84: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + + imux85: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + + imux86: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + }; + + imux87: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + }; + }; }; + /* + * I2C Switch 11-0070 channel #1: connecting to PIM + * (Port Interface Module) #2 (1-based). + */ imux41: i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; + + i2c-switch@73 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x73>; + i2c-mux-idle-disconnect; + + imux88: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + imux89: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + imux90: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + imux91: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + + imux92: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + + imux93: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + + imux94: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + }; + + imux95: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + }; + }; }; + /* + * I2C Switch 11-0070 channel #2: connecting to PIM + * (Port Interface Module) #3 (1-based). + */ imux42: i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; + + i2c-switch@73 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x73>; + i2c-mux-idle-disconnect; + + imux96: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + imux97: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + imux98: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + imux99: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + + imux100: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + + imux101: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + + imux102: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + }; + + imux103: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + }; + }; }; + /* + * I2C Switch 11-0070 channel #3: connecting to PIM + * (Port Interface Module) #4 (1-based). + */ imux43: i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; + + i2c-switch@73 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x73>; + i2c-mux-idle-disconnect; + + imux104: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + imux105: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + imux106: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + imux107: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + + imux108: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + + imux109: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + + imux110: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + }; + + imux111: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + }; + }; }; + /* + * I2C Switch 11-0070 channel #4: connecting to PIM + * (Port Interface Module) #5 (1-based). + */ imux44: i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; + + i2c-switch@73 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x73>; + i2c-mux-idle-disconnect; + + imux112: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + imux113: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + imux114: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + imux115: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + + imux116: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + + imux117: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + + imux118: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + }; + + imux119: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + }; + }; }; + /* + * I2C Switch 11-0070 channel #5: connecting to PIM + * (Port Interface Module) #6 (1-based). + */ imux45: i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; + + i2c-switch@73 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x73>; + i2c-mux-idle-disconnect; + + imux120: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + imux121: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + imux122: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + imux123: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + + imux124: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + + imux125: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + + imux126: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + }; + + imux127: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + }; + }; }; + /* + * I2C Switch 11-0070 channel #6: connecting to PIM + * (Port Interface Module) #7 (1-based). + */ imux46: i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; + + i2c-switch@73 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x73>; + i2c-mux-idle-disconnect; + + imux128: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + imux129: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + imux130: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + imux131: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + + imux132: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + + imux133: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + + imux134: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + }; + + imux135: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + }; + }; }; + /* + * I2C Switch 11-0070 channel #7: connecting to PIM + * (Port Interface Module) #8 (1-based). + */ imux47: i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; + + i2c-switch@73 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x73>; + i2c-mux-idle-disconnect; + + imux136: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + imux137: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + imux138: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + imux139: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + + imux140: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + + imux141: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + + imux142: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + }; + + imux143: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + }; + }; }; }; }; From 6ff286225d75a1bcb61cf0ff714757a579305beb Mon Sep 17 00:00:00 2001 From: Paul Fertser Date: Wed, 30 Sep 2020 22:25:07 +0300 Subject: [PATCH 316/799] arm: dts: aspeed: tiogapass: Enable second MAC Tioga Pass reference design includes Intel I210 Ethernet controller connected to the BMC with NC/SI. MAC readout is not supported. Signed-off-by: Paul Fertser Reviewed-by: Vijay Khemka Tested-by: Vijay Khemka Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts b/arch/arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts index e6ad821a8635..cd18641d5c23 100644 --- a/arch/arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts +++ b/arch/arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts @@ -191,6 +191,14 @@ use-ncsi; }; +&mac1 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rmii2_default>; + use-ncsi; +}; + &adc { status = "okay"; }; From 716ff4746cc12218cd96368e5b8714096ada0fe9 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 10 Nov 2020 19:50:33 +0100 Subject: [PATCH 317/799] dt-bindings: arm: fsl: document i.MX7S boards Document and adjust the compatibles for i.MX7S based boards. The Toradex boards use multiple compatibles. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Rob Herring Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/arm/fsl.yaml | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index f793f90fe2e6..0cf302867376 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -581,9 +581,15 @@ properties: - description: i.MX7S based Boards items: - enum: - - toradex,colibri-imx7s # Colibri iMX7 Solo Module - - toradex,colibri-imx7s-aster # Colibri iMX7 Solo Module on Aster Carrier Board - - toradex,colibri-imx7s-eval-v3 # Colibri iMX7 Solo Module on Colibri Evaluation Board V3 + - element14,imx7s-warp # Element14 Warp i.MX7 Board + - const: fsl,imx7s + + - description: i.MX7S Boards with Toradex Colibri iMX7S Module + items: + - enum: + - toradex,colibri-imx7s-aster # Module on Aster Carrier Board + - toradex,colibri-imx7s-eval-v3 # Module on Colibri Evaluation Board V3 + - const: toradex,colibri-imx7s - const: fsl,imx7s - description: TQ-Systems TQMa7S SoM on MBa7x board From 1186a522c302e01f1737b28e353bac137c47aca8 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 10 Nov 2020 19:50:34 +0100 Subject: [PATCH 318/799] ARM: dts: imx6q-pico: fix board compatibles There are four flavors of TechNexion PICO-IMX6 boards. They have their own DTSes, even though in Dwarf, Nymph and Pi are exactly the same. They also have their own bindings so adjust the compatibles to match the bindings. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6q-pico-dwarf.dts | 2 +- arch/arm/boot/dts/imx6q-pico-hobbit.dts | 2 +- arch/arm/boot/dts/imx6q-pico-nymph.dts | 2 +- arch/arm/boot/dts/imx6q-pico-pi.dts | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/imx6q-pico-dwarf.dts b/arch/arm/boot/dts/imx6q-pico-dwarf.dts index 618d2743e1e9..479a63ed42af 100644 --- a/arch/arm/boot/dts/imx6q-pico-dwarf.dts +++ b/arch/arm/boot/dts/imx6q-pico-dwarf.dts @@ -13,5 +13,5 @@ / { model = "TechNexion PICO-IMX6 Quad Board and Dwarf baseboard"; - compatible = "technexion,imx6q-pico", "fsl,imx6q"; + compatible = "technexion,imx6q-pico-dwarf", "fsl,imx6q"; }; diff --git a/arch/arm/boot/dts/imx6q-pico-hobbit.dts b/arch/arm/boot/dts/imx6q-pico-hobbit.dts index 7a666507b456..b767131068f5 100644 --- a/arch/arm/boot/dts/imx6q-pico-hobbit.dts +++ b/arch/arm/boot/dts/imx6q-pico-hobbit.dts @@ -13,5 +13,5 @@ / { model = "TechNexion PICO-IMX6 Quad Board and Hobbit baseboard"; - compatible = "technexion,imx6q-pico", "fsl,imx6q"; + compatible = "technexion,imx6q-pico-hobbit", "fsl,imx6q"; }; diff --git a/arch/arm/boot/dts/imx6q-pico-nymph.dts b/arch/arm/boot/dts/imx6q-pico-nymph.dts index fe5a7becc9e5..e8ad4c12b263 100644 --- a/arch/arm/boot/dts/imx6q-pico-nymph.dts +++ b/arch/arm/boot/dts/imx6q-pico-nymph.dts @@ -13,5 +13,5 @@ / { model = "TechNexion PICO-IMX6 Quad Board and Nymph baseboard"; - compatible = "technexion,imx6q-pico", "fsl,imx6q"; + compatible = "technexion,imx6q-pico-nymph", "fsl,imx6q"; }; diff --git a/arch/arm/boot/dts/imx6q-pico-pi.dts b/arch/arm/boot/dts/imx6q-pico-pi.dts index 9413f0a68f54..cc2394ddad6c 100644 --- a/arch/arm/boot/dts/imx6q-pico-pi.dts +++ b/arch/arm/boot/dts/imx6q-pico-pi.dts @@ -13,5 +13,5 @@ / { model = "TechNexion PICO-IMX6 Quad Board and PI baseboard"; - compatible = "technexion,imx6q-pico", "fsl,imx6q"; + compatible = "technexion,imx6q-pico-pi", "fsl,imx6q"; }; From 21658d51cf1ea88c04652a3852a190bb905cd91e Mon Sep 17 00:00:00 2001 From: Marc Kleine-Budde Date: Wed, 11 Nov 2020 14:05:05 +0100 Subject: [PATCH 319/799] ARM: dts: imx: Change flexcan node name to "can" Change i.MX SoCs nand node name from "flexcan" to "can" to be compliant with yaml schema, it requires the nodename to be "can". This fixes the following error found by dtbs_check: arch/arm/boot/dts/imx6dl-apf6dev.dt.yaml: flexcan@2090000: $nodename:0: 'flexcan@2090000' does not match '^can(@.*)?$' From schema: Documentation/devicetree/bindings/net/can/fsl,flexcan.yaml Cc: Shawn Guo Cc: devicetree@vger.kernel.org Signed-off-by: Marc Kleine-Budde Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl.dtsi | 4 ++-- arch/arm/boot/dts/imx6ul.dtsi | 4 ++-- arch/arm/boot/dts/vfxxx.dtsi | 4 ++-- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi index cb2a8ef9070c..6f59a99cbe82 100644 --- a/arch/arm/boot/dts/imx6qdl.dtsi +++ b/arch/arm/boot/dts/imx6qdl.dtsi @@ -546,7 +546,7 @@ status = "disabled"; }; - can1: flexcan@2090000 { + can1: can@2090000 { compatible = "fsl,imx6q-flexcan"; reg = <0x02090000 0x4000>; interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>; @@ -557,7 +557,7 @@ status = "disabled"; }; - can2: flexcan@2094000 { + can2: can@2094000 { compatible = "fsl,imx6q-flexcan"; reg = <0x02094000 0x4000>; interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>; diff --git a/arch/arm/boot/dts/imx6ul.dtsi b/arch/arm/boot/dts/imx6ul.dtsi index ccbcbac80663..9d3411cc597b 100644 --- a/arch/arm/boot/dts/imx6ul.dtsi +++ b/arch/arm/boot/dts/imx6ul.dtsi @@ -425,7 +425,7 @@ status = "disabled"; }; - can1: flexcan@2090000 { + can1: can@2090000 { compatible = "fsl,imx6ul-flexcan", "fsl,imx6q-flexcan"; reg = <0x02090000 0x4000>; interrupts = ; @@ -436,7 +436,7 @@ status = "disabled"; }; - can2: flexcan@2094000 { + can2: can@2094000 { compatible = "fsl,imx6ul-flexcan", "fsl,imx6q-flexcan"; reg = <0x02094000 0x4000>; interrupts = ; diff --git a/arch/arm/boot/dts/vfxxx.dtsi b/arch/arm/boot/dts/vfxxx.dtsi index 0c8d15fd9253..d53f9c9db8bf 100644 --- a/arch/arm/boot/dts/vfxxx.dtsi +++ b/arch/arm/boot/dts/vfxxx.dtsi @@ -95,7 +95,7 @@ status = "disabled"; }; - can0: flexcan@40020000 { + can0: can@40020000 { compatible = "fsl,vf610-flexcan"; reg = <0x40020000 0x4000>; interrupts = <58 IRQ_TYPE_LEVEL_HIGH>; @@ -681,7 +681,7 @@ status = "disabled"; }; - can1: flexcan@400d4000 { + can1: can@400d4000 { compatible = "fsl,vf610-flexcan"; reg = <0x400d4000 0x4000>; interrupts = <59 IRQ_TYPE_LEVEL_HIGH>; From b9639a8b5ef1fa90fc0152db15588a9fe601c4b0 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jonathan=20Neusch=C3=A4fer?= Date: Fri, 13 Nov 2020 00:30:54 +0100 Subject: [PATCH 320/799] ARM: dts: imx50-kobo-aura: Enable eKTF2132 touchscreen MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The Kobo Aura has an eKTF2132 touchscreen controller. Although the vendor kernel toggles a reset pin (GPIO5-12) during the startup sequence, the touchscreen works without it. Signed-off-by: Jonathan Neuschäfer Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx50-kobo-aura.dts | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/imx50-kobo-aura.dts b/arch/arm/boot/dts/imx50-kobo-aura.dts index 53b3995d37e7..97cfd970fe74 100644 --- a/arch/arm/boot/dts/imx50-kobo-aura.dts +++ b/arch/arm/boot/dts/imx50-kobo-aura.dts @@ -6,6 +6,7 @@ /dts-v1/; #include "imx50.dtsi" #include +#include / { model = "Kobo Aura (N514)"; @@ -119,7 +120,14 @@ pinctrl-0 = <&pinctrl_i2c1>; status = "okay"; - /* TODO: ektf2132 touch controller at 0x15 */ + touchscreen@15 { + reg = <0x15>; + compatible = "elan,ektf2132"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ts>; + power-gpios = <&gpio4 9 GPIO_ACTIVE_HIGH>; + interrupts-extended = <&gpio5 13 IRQ_TYPE_EDGE_FALLING>; + }; }; &i2c2 { @@ -225,6 +233,13 @@ >; }; + pinctrl_ts: tsgrp { + fsl,pins = < + MX50_PAD_CSPI_MOSI__GPIO4_9 0x0 + MX50_PAD_SD2_D5__GPIO5_13 0x0 + >; + }; + pinctrl_uart2: uart2grp { fsl,pins = < MX50_PAD_UART2_TXD__UART2_TXD_MUX 0x1e4 From a82820fcd079e38309403f595f005a8cc318a13c Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Fri, 11 Sep 2020 07:31:57 -0500 Subject: [PATCH 321/799] ARM: omap2plus_defconfig: Enable OMAP3_THERMAL With the additional power management options enabled, this patch enables OMAP3_THERMAL by default. Signed-off-by: Adam Ford Signed-off-by: Tony Lindgren --- arch/arm/configs/omap2plus_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/configs/omap2plus_defconfig b/arch/arm/configs/omap2plus_defconfig index 34793aabdb65..4bdaa9dd41fe 100644 --- a/arch/arm/configs/omap2plus_defconfig +++ b/arch/arm/configs/omap2plus_defconfig @@ -314,6 +314,7 @@ CONFIG_THERMAL_GOV_FAIR_SHARE=y CONFIG_THERMAL_GOV_USER_SPACE=y CONFIG_CPU_THERMAL=y CONFIG_TI_THERMAL=y +CONFIG_OMAP3_THERMAL=y CONFIG_OMAP4_THERMAL=y CONFIG_OMAP5_THERMAL=y CONFIG_DRA752_THERMAL=y From a6b2a18060f6b351752fa748a904f46b94edec00 Mon Sep 17 00:00:00 2001 From: Carl Philipp Klemm Date: Sun, 8 Nov 2020 19:53:20 +0100 Subject: [PATCH 322/799] ARM: omap2plus_defconfig: add CONFIG_AK8975=m and CONFIG_KXCJK1013=m ARM: omap2plus_defconfig: add CONFIG_AK8975=m and CONFIG_KXCJK1013=m to support motorola xt894's magnetometer and motorola xt875's accelerometer respectivly Signed-off-by: Carl Philipp Klemm [tony@atomide.com: shortened subject a bit] Signed-off-by: Tony Lindgren --- arch/arm/configs/omap2plus_defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/configs/omap2plus_defconfig b/arch/arm/configs/omap2plus_defconfig index 4bdaa9dd41fe..2ab9024cb6e3 100644 --- a/arch/arm/configs/omap2plus_defconfig +++ b/arch/arm/configs/omap2plus_defconfig @@ -525,6 +525,8 @@ CONFIG_TI_AM335X_ADC=m CONFIG_TWL4030_MADC=m CONFIG_SENSORS_ISL29028=m CONFIG_BMP280=m +CONFIG_KXCJK1013=m +CONFIG_AK8975=m CONFIG_PWM=y CONFIG_PWM_OMAP_DMTIMER=m CONFIG_PWM_TIECAP=m From be5cd39a5e2cfa9cd78ccd00e7886029e21ceaf1 Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Mon, 7 Sep 2020 12:52:46 +0300 Subject: [PATCH 323/799] ARM: dts: dra7: add second SHA instance DRA7 SoC has two SHA instances, add the missing second one under the main dts file. Signed-off-by: Tero Kristo Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/dra7.dtsi | 34 ++++++++++++++++++++++++++++++++-- 1 file changed, 32 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index 4e1bbc0198eb..6ba6a1b50e00 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi @@ -932,7 +932,7 @@ }; }; - sham_target: target-module@4b101000 { + sham1_target: target-module@4b101000 { compatible = "ti,sysc-omap3-sham", "ti,sysc"; reg = <0x4b101100 0x4>, <0x4b101110 0x4>, @@ -951,7 +951,7 @@ #size-cells = <1>; ranges = <0x0 0x4b101000 0x1000>; - sham: sham@0 { + sham1: sham@0 { compatible = "ti,omap5-sham"; reg = <0 0x300>; interrupts = ; @@ -962,6 +962,36 @@ }; }; + sham2_target: target-module@42701000 { + compatible = "ti,sysc-omap3-sham", "ti,sysc"; + reg = <0x42701100 0x4>, + <0x42701110 0x4>, + <0x42701114 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + ; + ti,syss-mask = <1>; + /* Domains (P, C): l4per_pwrdm, l4sec_clkdm */ + clocks = <&l4sec_clkctrl DRA7_L4SEC_SHAM2_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x42701000 0x1000>; + + sham2: sham@0 { + compatible = "ti,omap5-sham"; + reg = <0 0x300>; + interrupts = ; + dmas = <&edma_xbar 165 0>; + dma-names = "rx"; + clocks = <&l3_iclk_div>; + clock-names = "fck"; + }; + }; + opp_supply_mpu: opp-supply@4a003b20 { compatible = "ti,omap5-opp-supply"; reg = <0x4a003b20 0xc>; From 02564e1ad77e5fe1bbae87ed8490dc503c6f9570 Mon Sep 17 00:00:00 2001 From: David Lechner Date: Mon, 12 Oct 2020 16:12:27 -0500 Subject: [PATCH 324/799] ARM: dts: am33xx: Add nodes for eQEP This adds new nodes for the Texas Instruments Enhanced Quadrature Encoder Pulse (eQEP) module in the PWM subsystem on AM33XX. Signed-off-by: David Lechner Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am33xx-l4.dtsi | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/arch/arm/boot/dts/am33xx-l4.dtsi b/arch/arm/boot/dts/am33xx-l4.dtsi index ea20e4bdf040..cb164dfec56d 100644 --- a/arch/arm/boot/dts/am33xx-l4.dtsi +++ b/arch/arm/boot/dts/am33xx-l4.dtsi @@ -1923,6 +1923,15 @@ status = "disabled"; }; + eqep0: counter@180 { + compatible = "ti,am3352-eqep"; + reg = <0x180 0x80>; + clocks = <&l4ls_gclk>; + clock-names = "sysclkout"; + interrupts = <79>; + status = "disabled"; + }; + ehrpwm0: pwm@200 { compatible = "ti,am3352-ehrpwm", "ti,am33xx-ehrpwm"; @@ -1975,6 +1984,15 @@ status = "disabled"; }; + eqep1: counter@180 { + compatible = "ti,am3352-eqep"; + reg = <0x180 0x80>; + clocks = <&l4ls_gclk>; + clock-names = "sysclkout"; + interrupts = <88>; + status = "disabled"; + }; + ehrpwm1: pwm@200 { compatible = "ti,am3352-ehrpwm", "ti,am33xx-ehrpwm"; @@ -2027,6 +2045,15 @@ status = "disabled"; }; + eqep2: counter@180 { + compatible = "ti,am3352-eqep"; + reg = <0x180 0x80>; + clocks = <&l4ls_gclk>; + clock-names = "sysclkout"; + interrupts = <89>; + status = "disabled"; + }; + ehrpwm2: pwm@200 { compatible = "ti,am3352-ehrpwm", "ti,am33xx-ehrpwm"; From 672081b5dd94a4f81e545c79c96e3a1dfdffd2f1 Mon Sep 17 00:00:00 2001 From: David Lechner Date: Mon, 12 Oct 2020 16:12:28 -0500 Subject: [PATCH 325/799] ARM: dts: am335x-boneblue: Enable eQEP This enables the Enhanced Quadrature Encoder Pulse (eQEP) module for connectors E1, E2 and E3 on BeagleBone Blue. Signed-off-by: David Lechner Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am335x-boneblue.dts | 54 +++++++++++++++++++++++++++ 1 file changed, 54 insertions(+) diff --git a/arch/arm/boot/dts/am335x-boneblue.dts b/arch/arm/boot/dts/am335x-boneblue.dts index c696d57cf364..69acaf4ea0f3 100644 --- a/arch/arm/boot/dts/am335x-boneblue.dts +++ b/arch/arm/boot/dts/am335x-boneblue.dts @@ -241,6 +241,30 @@ AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_OUTPUT, MUX_MODE7) /* (M16) gmii1_rxd0.gpio2[21] */ >; }; + + /* E1 */ + eqep0_pins: pinmux_eqep0_pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_MCASP0_AXR0, PIN_INPUT, MUX_MODE1) /* (B12) mcasp0_aclkr.eQEP0A_in */ + AM33XX_PADCONF(AM335X_PIN_MCASP0_FSR, PIN_INPUT, MUX_MODE1) /* (C13) mcasp0_fsr.eQEP0B_in */ + >; + }; + + /* E2 */ + eqep1_pins: pinmux_eqep1_pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_INPUT, MUX_MODE2) /* (V2) lcd_data12.eQEP1A_in */ + AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_INPUT, MUX_MODE2) /* (V3) lcd_data13.eQEP1B_in */ + >; + }; + + /* E3 */ + eqep2_pins: pinmux_eqep2_pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_INPUT, MUX_MODE4) /* (T12) gpmc_ad12.eQEP2A_in */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_INPUT, MUX_MODE4) /* (R12) gpmc_ad13.eQEP2B_in */ + >; + }; }; &uart0 { @@ -419,3 +443,33 @@ line-name = "LS_BUF_EN"; }; }; + +&epwmss0 { + status = "okay"; +}; + +&eqep0 { + pinctrl-names = "default"; + pinctrl-0 = <&eqep0_pins>; + status = "okay"; +}; + +&epwmss1 { + status = "okay"; +}; + +&eqep1 { + pinctrl-names = "default"; + pinctrl-0 = <&eqep1_pins>; + status = "okay"; +}; + +&epwmss2 { + status = "okay"; +}; + +&eqep2 { + pinctrl-names = "default"; + pinctrl-0 = <&eqep2_pins>; + status = "okay"; +}; From d7356a7ab125c3a4fee521b7530f3122bc842ac4 Mon Sep 17 00:00:00 2001 From: Alexander Shiyan Date: Wed, 11 Nov 2020 18:59:10 +0300 Subject: [PATCH 326/799] ARM: dts: am335x: Fix comments for AM335X_PIN_GPMC_WPN pin in GPIO mode According to AM335x datasheet pin AM335X_PIN_GPMC_WPN in MODE7 works as GPIO0[31]. Signed-off-by: Alexander Shiyan Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am335x-baltos.dtsi | 2 +- arch/arm/boot/dts/am335x-cm-t335.dts | 2 +- arch/arm/boot/dts/am335x-evm.dts | 2 +- arch/arm/boot/dts/am335x-igep0033.dtsi | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/am335x-baltos.dtsi b/arch/arm/boot/dts/am335x-baltos.dtsi index b7f64c7ba83d..3ea286180382 100644 --- a/arch/arm/boot/dts/am335x-baltos.dtsi +++ b/arch/arm/boot/dts/am335x-baltos.dtsi @@ -168,7 +168,7 @@ AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */ AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */ AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLUP, MUX_MODE7) /* gpmc_wpn.gpio0_30 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLUP, MUX_MODE7) /* gpmc_wpn.gpio0_31 */ AM33XX_PADCONF(AM335X_PIN_GPMC_CSN0, PIN_OUTPUT, MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */ AM33XX_PADCONF(AM335X_PIN_GPMC_ADVN_ALE, PIN_OUTPUT, MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */ AM33XX_PADCONF(AM335X_PIN_GPMC_OEN_REN, PIN_OUTPUT, MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */ diff --git a/arch/arm/boot/dts/am335x-cm-t335.dts b/arch/arm/boot/dts/am335x-cm-t335.dts index c6fe9db660e2..36d963db4026 100644 --- a/arch/arm/boot/dts/am335x-cm-t335.dts +++ b/arch/arm/boot/dts/am335x-cm-t335.dts @@ -122,7 +122,7 @@ AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE0) - /* gpmc_wpn.gpio0_30 */ + /* gpmc_wpn.gpio0_31 */ AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLUP, MUX_MODE7) AM33XX_PADCONF(AM335X_PIN_GPMC_CSN0, PIN_OUTPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_GPMC_ADVN_ALE, PIN_OUTPUT, MUX_MODE0) diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts index 12dffccd1ffd..7c6f2c11f0e1 100644 --- a/arch/arm/boot/dts/am335x-evm.dts +++ b/arch/arm/boot/dts/am335x-evm.dts @@ -229,7 +229,7 @@ AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLUP, MUX_MODE7) /* gpmc_wpn.gpio0_30 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLUP, MUX_MODE7) /* gpmc_wpn.gpio0_31 */ AM33XX_PADCONF(AM335X_PIN_GPMC_CSN0, PIN_OUTPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_GPMC_ADVN_ALE, PIN_OUTPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_GPMC_OEN_REN, PIN_OUTPUT, MUX_MODE0) diff --git a/arch/arm/boot/dts/am335x-igep0033.dtsi b/arch/arm/boot/dts/am335x-igep0033.dtsi index c9f354fc984a..7ec23d47a429 100644 --- a/arch/arm/boot/dts/am335x-igep0033.dtsi +++ b/arch/arm/boot/dts/am335x-igep0033.dtsi @@ -70,7 +70,7 @@ AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLUP, MUX_MODE7) /* gpmc_wpn.gpio0_30 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLUP, MUX_MODE7) /* gpmc_wpn.gpio0_31 */ AM33XX_PADCONF(AM335X_PIN_GPMC_CSN0, PIN_OUTPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_GPMC_ADVN_ALE, PIN_OUTPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_GPMC_OEN_REN, PIN_OUTPUT, MUX_MODE0) From 38c212c90bf172547dc7df7c11fcaacef2c78696 Mon Sep 17 00:00:00 2001 From: Corentin Labbe Date: Thu, 12 Nov 2020 20:26:52 +0000 Subject: [PATCH 327/799] ARM: configs: sunxi: enable Realtek PHY Lot of sunxi boards has a Realtek PHY, so let's enable it. Signed-off-by: Corentin Labbe Signed-off-by: Maxime Ripard Acked-by: Jernej Skrabec Link: https://lore.kernel.org/r/20201112202652.27676-1-clabbe@baylibre.com --- arch/arm/configs/sunxi_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/configs/sunxi_defconfig b/arch/arm/configs/sunxi_defconfig index 244126172fd6..05f7f4ed8ded 100644 --- a/arch/arm/configs/sunxi_defconfig +++ b/arch/arm/configs/sunxi_defconfig @@ -51,6 +51,7 @@ CONFIG_STMMAC_ETH=y # CONFIG_NET_VENDOR_VIA is not set # CONFIG_NET_VENDOR_WIZNET is not set CONFIG_MICREL_PHY=y +CONFIG_REALTEK_PHY=y # CONFIG_WLAN is not set CONFIG_INPUT_EVDEV=y CONFIG_KEYBOARD_SUN4I_LRADC=y From f9135aaf2767500dee419c03640f7a3784b56559 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20J=C3=BCcker?= Date: Fri, 13 Nov 2020 22:25:26 +0100 Subject: [PATCH 328/799] ARM: exynos: extend cpuidle support to P4 Note boards MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The P4 Note family supports cpuidle, so allow it to make use of this feature. Signed-off-by: Martin Jücker Link: https://lore.kernel.org/r/20201113212525.13455-6-martin.juecker@gmail.com Signed-off-by: Krzysztof Kozlowski --- arch/arm/mach-exynos/exynos.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c index a99d8eba4bb3..25b01da4771b 100644 --- a/arch/arm/mach-exynos/exynos.c +++ b/arch/arm/mach-exynos/exynos.c @@ -177,7 +177,8 @@ static void __init exynos_dt_machine_init(void) if (of_machine_is_compatible("samsung,exynos4210") || (of_machine_is_compatible("samsung,exynos4412") && (of_machine_is_compatible("samsung,trats2") || - of_machine_is_compatible("samsung,midas"))) || + of_machine_is_compatible("samsung,midas") || + of_machine_is_compatible("samsung,p4note"))) || of_machine_is_compatible("samsung,exynos3250") || of_machine_is_compatible("samsung,exynos5250")) platform_device_register(&exynos_cpuidle); From d8f0ddc8387757957c4f696e67b3332695f6525e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20J=C3=BCcker?= Date: Fri, 13 Nov 2020 22:25:24 +0100 Subject: [PATCH 329/799] ARM: defconfig: add STMPE ADC driver for P4 Note MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Enable the STMPE ADC driver for the P4 Note device family in exynos and multi_v7 defconfigs. Signed-off-by: Martin Jücker Link: https://lore.kernel.org/r/20201113212525.13455-4-martin.juecker@gmail.com Signed-off-by: Krzysztof Kozlowski --- arch/arm/configs/exynos_defconfig | 3 +++ arch/arm/configs/multi_v7_defconfig | 2 ++ 2 files changed, 5 insertions(+) diff --git a/arch/arm/configs/exynos_defconfig b/arch/arm/configs/exynos_defconfig index f0cef76a3ab9..ee71bcd247a0 100644 --- a/arch/arm/configs/exynos_defconfig +++ b/arch/arm/configs/exynos_defconfig @@ -177,6 +177,8 @@ CONFIG_MFD_MAX77693=y CONFIG_MFD_MAX8997=y CONFIG_MFD_MAX8998=y CONFIG_MFD_SEC_CORE=y +CONFIG_MFD_STMPE=y +CONFIG_STMPE_I2C=y CONFIG_MFD_TPS65090=y CONFIG_REGULATOR=y CONFIG_REGULATOR_FIXED_VOLTAGE=y @@ -322,6 +324,7 @@ CONFIG_EXTCON_MAX77693=y CONFIG_EXTCON_MAX8997=y CONFIG_IIO=y CONFIG_EXYNOS_ADC=y +CONFIG_STMPE_ADC=y CONFIG_CM36651=y CONFIG_AK8975=y CONFIG_PWM=y diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig index 6ab0945fb27c..a33a0b8eda20 100644 --- a/arch/arm/configs/multi_v7_defconfig +++ b/arch/arm/configs/multi_v7_defconfig @@ -558,6 +558,7 @@ CONFIG_MFD_RK808=y CONFIG_MFD_RN5T618=y CONFIG_MFD_SEC_CORE=y CONFIG_MFD_STMPE=y +CONFIG_STMPE_I2C=y CONFIG_MFD_PALMAS=y CONFIG_MFD_TPS65090=y CONFIG_MFD_TPS65217=y @@ -1026,6 +1027,7 @@ CONFIG_AT91_SAMA5D2_ADC=m CONFIG_BERLIN2_ADC=m CONFIG_CPCAP_ADC=m CONFIG_EXYNOS_ADC=m +CONFIG_STMPE_ADC=m CONFIG_MESON_SARADC=m CONFIG_ROCKCHIP_SARADC=m CONFIG_STM32_ADC_CORE=m From 7e8af057bd9b3d76bd343794e71c20e8dd462372 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20J=C3=BCcker?= Date: Fri, 13 Nov 2020 22:25:25 +0100 Subject: [PATCH 330/799] ARM: exynos_defconfig: compile Atmel MXT touchscreeen as module MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The Atmel MXT touchscreen can load firmware and settings from the /lib/firmware directory, it makes sense to have it as a module to have more control over the loading process. Signed-off-by: Martin Jücker Link: https://lore.kernel.org/r/20201113212525.13455-5-martin.juecker@gmail.com Signed-off-by: Krzysztof Kozlowski --- arch/arm/configs/exynos_defconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/configs/exynos_defconfig b/arch/arm/configs/exynos_defconfig index ee71bcd247a0..513f56b3c059 100644 --- a/arch/arm/configs/exynos_defconfig +++ b/arch/arm/configs/exynos_defconfig @@ -127,7 +127,7 @@ CONFIG_KEYBOARD_CROS_EC=y # CONFIG_MOUSE_PS2 is not set CONFIG_MOUSE_CYAPA=y CONFIG_INPUT_TOUCHSCREEN=y -CONFIG_TOUCHSCREEN_ATMEL_MXT=y +CONFIG_TOUCHSCREEN_ATMEL_MXT=m CONFIG_TOUCHSCREEN_MMS114=y CONFIG_INPUT_MISC=y CONFIG_INPUT_MAX77693_HAPTIC=y From 33baadaee94085fdcfab569eb01501753b074b19 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20J=C3=BCcker?= Date: Fri, 13 Nov 2020 22:25:22 +0100 Subject: [PATCH 331/799] dt-bindings: arm: samsung: document bindings for P4 Note family board MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Document the GT-N8010/GT-N8013 device binding and the P4 Note common binding that it is based on. Signed-off-by: Martin Jücker Reviewed-by: Rob Herring Link: https://lore.kernel.org/r/20201113212525.13455-2-martin.juecker@gmail.com Signed-off-by: Krzysztof Kozlowski --- .../devicetree/bindings/arm/samsung/samsung-boards.yaml | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml b/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml index eb92f9eefaba..dbc401984152 100644 --- a/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml +++ b/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml @@ -83,6 +83,14 @@ properties: - const: samsung,exynos4412 - const: samsung,exynos4 + - description: Samsung p4note family boards + items: + - enum: + - samsung,n8010 # Samsung GT-N8010/GT-N8013 + - const: samsung,p4note + - const: samsung,exynos4412 + - const: samsung,exynos4 + - description: Exynos5250 based boards items: - enum: From f48b5050c301f7235ef61d8cbbbf0410a5e0245f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20J=C3=BCcker?= Date: Fri, 13 Nov 2020 22:25:23 +0100 Subject: [PATCH 332/799] ARM: dts: exynos: add Samsung's Exynos4412-based P4 Note boards MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The P4 Note family contains a couple of variants of the Galaxy Note 10.1 tablet with mainly different modems. The GT-N8010/GT-N8013 is the WiFi only version. Signed-off-by: Martin Jücker Link: https://lore.kernel.org/r/20201113212525.13455-3-martin.juecker@gmail.com Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/exynos4412-p4note-n8010.dts | 17 + arch/arm/boot/dts/exynos4412-p4note.dtsi | 1132 +++++++++++++++++ 3 files changed, 1150 insertions(+) create mode 100644 arch/arm/boot/dts/exynos4412-p4note-n8010.dts create mode 100644 arch/arm/boot/dts/exynos4412-p4note.dtsi diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index ce66ffd5a1bb..55ffee2b20f8 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -197,6 +197,7 @@ dtb-$(CONFIG_ARCH_EXYNOS4) += \ exynos4412-odroidx.dtb \ exynos4412-odroidx2.dtb \ exynos4412-origen.dtb \ + exynos4412-p4note-n8010.dtb \ exynos4412-smdk4412.dtb \ exynos4412-tiny4412.dtb \ exynos4412-trats2.dtb diff --git a/arch/arm/boot/dts/exynos4412-p4note-n8010.dts b/arch/arm/boot/dts/exynos4412-p4note-n8010.dts new file mode 100644 index 000000000000..9f559425bd2c --- /dev/null +++ b/arch/arm/boot/dts/exynos4412-p4note-n8010.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Samsung's Galaxy Note 10.1 - N801x (wifi only version) + * + * Copyright (c) 2013 Samsung Electronics Co., Ltd. + * http://www.samsung.com + */ + +/dts-v1/; +#include "exynos4412-p4note.dtsi" + +/ { + model = "Samsung Galaxy Note 10.1 (GT-N8010/N8013) based on Exynos4412"; + compatible = "samsung,n8010", "samsung,p4note", "samsung,exynos4412", "samsung,exynos4"; + + /* this is the base variant without any kind of modem */ +}; diff --git a/arch/arm/boot/dts/exynos4412-p4note.dtsi b/arch/arm/boot/dts/exynos4412-p4note.dtsi new file mode 100644 index 000000000000..0f8d4164a977 --- /dev/null +++ b/arch/arm/boot/dts/exynos4412-p4note.dtsi @@ -0,0 +1,1132 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Samsung's Exynos4412 based p4note device family base DT. + * Based on exynos4412-midas.dtsi. + * + * Copyright (c) 2013 Samsung Electronics Co., Ltd. + * http://www.samsung.com + */ + +/dts-v1/; +#include "exynos4412.dtsi" +#include "exynos4412-ppmu-common.dtsi" + +#include +#include +#include +#include +#include + +/ { + compatible = "samsung,p4note", "samsung,exynos4412", "samsung,exynos4"; + + memory@40000000 { + device_type = "memory"; + reg = <0x40000000 0x80000000>; + }; + + chosen { + stdout-path = &serial_2; + }; + + firmware@204f000 { + compatible = "samsung,secure-firmware"; + reg = <0x0204F000 0x1000>; + }; + + fixed-rate-clocks { + xxti { + compatible = "samsung,clock-xxti"; + clock-frequency = <0>; + }; + + xusbxti { + compatible = "samsung,clock-xusbxti"; + clock-frequency = <24000000>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&gpio_keys>; + + key-down { + gpios = <&gpx2 2 GPIO_ACTIVE_LOW>; + linux,code = ; + label = "volume down"; + debounce-interval = <10>; + }; + + key-up { + gpios = <&gpx3 3 GPIO_ACTIVE_LOW>; + linux,code = ; + label = "volume up"; + debounce-interval = <10>; + }; + + key-power { + gpios = <&gpx2 7 GPIO_ACTIVE_LOW>; + linux,code = ; + label = "power"; + debounce-interval = <10>; + wakeup-source; + }; + }; + + voltage-regulator-1 { + compatible = "regulator-fixed"; + regulator-name = "TSP_LDO1"; + pinctrl-names = "default"; + pinctrl-0 = <&tsp_reg_gpio_1>; + gpios = <&gpm4 5 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + + voltage-regulator-2 { + compatible = "regulator-fixed"; + regulator-name = "TSP_LDO2"; + pinctrl-names = "default"; + pinctrl-0 = <&tsp_reg_gpio_2>; + gpios = <&gpb 5 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + + voltage-regulator-3 { + compatible = "regulator-fixed"; + regulator-name = "TSP_LDO3"; + pinctrl-names = "default"; + pinctrl-0 = <&tsp_reg_gpio_3>; + gpios = <&gpb 7 GPIO_ACTIVE_HIGH>; + startup-delay-us = <20000>; + enable-active-high; + regulator-always-on; + }; + + wlan_pwrseq: sdhci3-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpm3 5 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&wifi_reset>; + pinctrl-names = "default"; + clocks = <&max77686 MAX77686_CLK_PMIC>; + clock-names = "ext_clock"; + }; + + i2c-gpio-1 { + compatible = "i2c-gpio"; + sda-gpios = <&gpy2 4 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpy2 5 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + i2c-gpio,delay-us = <2>; + #address-cells = <1>; + #size-cells = <0>; + + magnetometer@c { + compatible = "asahi-kasei,ak8975"; + reg = <0x0c>; + pinctrl-0 = <&ak8975_irq>; + pinctrl-names = "default"; + interrupt-parent = <&gpm4>; + interrupts = <7 IRQ_TYPE_EDGE_RISING>; + }; + }; + + i2c-gpio-2 { + compatible = "i2c-gpio"; + sda-gpios = <&gpy0 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpy0 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + i2c-gpio,delay-us = <2>; + #address-cells = <1>; + #size-cells = <0>; + + fuel-gauge@36 { + compatible = "maxim,max17042"; + reg = <0x36>; + pinctrl-0 = <&fuel_alert_irq>; + pinctrl-names = "default"; + interrupt-parent = <&gpx2>; + interrupts = <3 IRQ_TYPE_EDGE_FALLING>; + maxim,rsns-microohm = <10000>; + maxim,over-heat-temp = <600>; + maxim,over-volt = <4300>; + }; + }; + + i2c-gpio-3 { + compatible = "i2c-gpio"; + sda-gpios = <&gpm4 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpm4 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + i2c-gpio,delay-us = <5>; + #address-cells = <1>; + #size-cells = <0>; + + adc@41 { + compatible = "st,stmpe811"; + reg = <0x41>; + pinctrl-0 = <&stmpe_adc_irq>; + pinctrl-names = "default"; + interrupt-parent = <&gpx0>; + interrupts = <1 IRQ_TYPE_LEVEL_LOW>; + interrupt-controller; + irq-trigger = <0x1>; + st,adc-freq = <3>; + st,mod-12b = <1>; + st,ref-sel = <0>; + st,sample-time = <3>; + + stmpe_adc { + compatible = "st,stmpe-adc"; + #io-channel-cells = <1>; + st,norequest-mask = <0x2F>; + }; + }; + }; +}; + +&adc { + vdd-supply = <&ldo3_reg>; + /* not verified */ + status = "okay"; +}; + +&bus_dmc { + devfreq-events = <&ppmu_dmc0_3>, <&ppmu_dmc1_3>; + vdd-supply = <&buck1_reg>; + status = "okay"; +}; + +&bus_acp { + devfreq = <&bus_dmc>; + status = "okay"; +}; + +&bus_c2c { + devfreq = <&bus_dmc>; + status = "okay"; +}; + +&bus_leftbus { + devfreq-events = <&ppmu_leftbus_3>, <&ppmu_rightbus_3>; + vdd-supply = <&buck3_reg>; + status = "okay"; +}; + +&bus_rightbus { + devfreq = <&bus_leftbus>; + status = "okay"; +}; + +&bus_display { + devfreq = <&bus_leftbus>; + status = "okay"; +}; + +&bus_fsys { + devfreq = <&bus_leftbus>; + status = "okay"; +}; + +&bus_peri { + devfreq = <&bus_leftbus>; + status = "okay"; +}; + +&bus_mfc { + devfreq = <&bus_leftbus>; + status = "okay"; +}; + +&cpu0 { + cpu0-supply = <&buck2_reg>; +}; + +&cpu_thermal { + cooling-maps { + map0 { + /* Corresponds to 800MHz at freq_table */ + cooling-device = <&cpu0 7 7>, <&cpu1 7 7>, + <&cpu2 7 7>, <&cpu3 7 7>; + }; + map1 { + /* Corresponds to 200MHz at freq_table */ + cooling-device = <&cpu0 13 13>, <&cpu1 13 13>, + <&cpu2 13 13>, <&cpu3 13 13>; + }; + }; +}; + +&exynos_usbphy { + status = "okay"; +}; + +&fimd { + pinctrl-0 = <&lcd_clk &lcd_data24 &pwm1_out>; + pinctrl-names = "default"; + status = "okay"; + + display-timings { + timing0 { + clock-frequency = <66666666>; + hactive = <1280>; + vactive = <800>; + hfront-porch = <18>; + hback-porch = <36>; + hsync-len = <16>; + vback-porch = <16>; + vfront-porch = <4>; + vsync-len = <3>; + hsync-active = <1>; + }; + }; +}; + +&gpu { + mali-supply = <&buck4_reg>; + status = "okay"; +}; + +&hsotg { + vusb_a-supply = <&ldo12_reg>; + dr_mode = "peripheral"; + status = "okay"; +}; + +&i2c_3 { + samsung,i2c-sda-delay = <100>; + samsung,i2c-slave-addr = <0x10>; + samsung,i2c-max-bus-freq = <400000>; + pinctrl-0 = <&i2c3_bus>; + pinctrl-names = "default"; + status = "okay"; + + touchscreen@4a { + compatible = "atmel,maxtouch"; + reg = <0x4a>; + pinctrl-0 = <&tsp_rst &tsp_irq>; + pinctrl-names = "default"; + interrupt-parent = <&gpm2>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&gpm0 4 GPIO_ACTIVE_HIGH>; + }; +}; + +&i2c_7 { + samsung,i2c-sda-delay = <100>; + samsung,i2c-slave-addr = <0x10>; + samsung,i2c-max-bus-freq = <400000>; + pinctrl-0 = <&i2c7_bus>; + pinctrl-names = "default"; + status = "okay"; + + max77686: pmic@9 { + compatible = "maxim,max77686"; + interrupt-parent = <&gpx0>; + interrupts = <7 IRQ_TYPE_NONE>; + pinctrl-0 = <&max77686_irq>; + pinctrl-names = "default"; + reg = <0x09>; + #clock-cells = <1>; + + voltage-regulators { + ldo1_reg: LDO1 { + regulator-name = "ldo1"; + regulator-always-on; + }; + + ldo2_reg: LDO2 { + regulator-name = "ldo2"; + regulator-always-on; + }; + + /* WM8994 audio */ + ldo3_reg: LDO3 { + regulator-name = "VCC_1.8V_AP"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + ldo4_reg: LDO4 { + regulator-name = "ldo4"; + regulator-always-on; + }; + + ldo5_reg: LDO5 { + regulator-name = "VCC_1.8V_IO"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo6_reg: LDO6 { + regulator-name = "ldo6"; + regulator-always-on; + }; + + ldo7_reg: LDO7 { + regulator-name = "ldo7"; + regulator-always-on; + }; + + /* CSI IP block */ + ldo8_reg: LDO8 { + regulator-name = "VMIPI_1.0V"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + /* IR LED on/off */ + ldo9_reg: LDO9 { + regulator-name = "VLED_IC_1.9V"; + regulator-min-microvolt = <1950000>; + regulator-max-microvolt = <1950000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + /* CSI IP block */ + ldo10_reg: LDO10 { + regulator-name = "VMIPI_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + ldo11_reg: LDO11 { + regulator-name = "VABB1_1.9V"; + regulator-min-microvolt = <1950000>; + regulator-max-microvolt = <1950000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + /* USB OTG */ + ldo12_reg: LDO12 { + regulator-name = "VUOTG_3.0V"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + /* not connected */ + ldo13_reg: LDO13 { + regulator-name = "ldo13"; + }; + + ldo14_reg: LDO14 { + regulator-name = "VABB2_1.9V"; + regulator-min-microvolt = <1950000>; + regulator-max-microvolt = <1950000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo15_reg: LDO15 { + regulator-name = "ldo15"; + regulator-always-on; + }; + + ldo16_reg: LDO16 { + regulator-name = "ldo16"; + regulator-always-on; + }; + + /* not connected */ + ldo17_reg: LDO17 { + regulator-name = "ldo17"; + }; + + /* Camera ISX012 */ + ldo18_reg: LDO18 { + regulator-name = "CAM_IO_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + /* Camera S5K6A3 */ + ldo19_reg: LDO19 { + regulator-name = "VT_CORE_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + /* not connected */ + ldo20_reg: LDO20 { + regulator-name = "ldo20"; + }; + + /* MMC2 */ + ldo21_reg: LDO21 { + regulator-name = "VTF_2.8V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + maxim,ena-gpios = <&gpy2 0 GPIO_ACTIVE_HIGH>; + }; + + /* not connected */ + ldo22_reg: LDO22 { + regulator-name = "ldo22"; + }; + + /* ADC */ + ldo23_reg: LDO23 { + regulator-name = "VDD_ADC_3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + /* Camera S5K6A3 */ + ldo24_reg: LDO24 { + regulator-name = "CAM_A2.8V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo25_reg: LDO25 { + regulator-name = "VLED_3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + /* Camera ISX012 */ + ldo26_reg: LDO26 { + regulator-name = "3MP_AF_2.8V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + buck1_reg: BUCK1 { + regulator-name = "VDD_MIF"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1050000>; + regulator-always-on; + regulator-boot-on; + }; + + buck2_reg: BUCK2 { + regulator-name = "VDD_ARM"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + }; + + buck3_reg: BUCK3 { + regulator-name = "VDD_INT"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + regulator-boot-on; + }; + + buck4_reg: BUCK4 { + regulator-name = "VDD_G3D"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1075000>; + regulator-boot-on; + }; + + buck5_reg: BUCK5 { + regulator-name = "buck5"; + regulator-always-on; + }; + + buck6_reg: BUCK6 { + regulator-name = "buck6"; + regulator-always-on; + }; + + buck7_reg: BUCK7 { + regulator-name = "buck7"; + regulator-always-on; + }; + + /* not connected */ + buck8_reg: BUCK8 { + regulator-name = "buck8"; + }; + + buck9_reg: BUCK9 { + regulator-name = "3MP_CORE_1.2V"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + +&mshc_0 { + broken-cd; + non-removable; + card-detect-delay = <200>; + clock-frequency = <400000000>; + samsung,dw-mshc-ciu-div = <0>; + samsung,dw-mshc-sdr-timing = <2 3>; + samsung,dw-mshc-ddr-timing = <1 2>; + pinctrl-0 = <&sd4_clk &sd4_cmd &sd4_bus4 &sd4_bus8>; + pinctrl-names = "default"; + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + status = "okay"; +}; + +&pinctrl_0 { + pinctrl-names = "default"; + pinctrl-0 = <&sleep0>; + + tsp_reg_gpio_2: tsp-reg-gpio-2 { + samsung,pins = "gpb-5"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + tsp_reg_gpio_3: tsp-reg-gpio-3 { + samsung,pins = "gpb-7"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + sleep0: sleep-states { + PIN_SLP(gpa0-0, INPUT, NONE); + PIN_SLP(gpa0-1, OUT0, NONE); + PIN_SLP(gpa0-2, INPUT, NONE); + PIN_SLP(gpa0-3, INPUT, UP); + PIN_SLP(gpa0-4, INPUT, NONE); + PIN_SLP(gpa0-5, INPUT, DOWN); + PIN_SLP(gpa0-6, INPUT, DOWN); + PIN_SLP(gpa0-7, INPUT, UP); + + PIN_SLP(gpa1-0, INPUT, DOWN); + PIN_SLP(gpa1-1, INPUT, DOWN); + PIN_SLP(gpa1-2, INPUT, DOWN); + PIN_SLP(gpa1-3, INPUT, DOWN); + PIN_SLP(gpa1-4, INPUT, DOWN); + PIN_SLP(gpa1-5, INPUT, DOWN); + + PIN_SLP(gpb-0, INPUT, NONE); + PIN_SLP(gpb-1, INPUT, NONE); + PIN_SLP(gpb-2, INPUT, NONE); + PIN_SLP(gpb-3, INPUT, NONE); + PIN_SLP(gpb-4, INPUT, DOWN); + PIN_SLP(gpb-5, INPUT, DOWN); + PIN_SLP(gpb-6, INPUT, DOWN); + PIN_SLP(gpb-7, INPUT, DOWN); + + PIN_SLP(gpc0-0, INPUT, DOWN); + PIN_SLP(gpc0-1, INPUT, DOWN); + PIN_SLP(gpc0-2, INPUT, DOWN); + PIN_SLP(gpc0-3, INPUT, DOWN); + PIN_SLP(gpc0-4, INPUT, DOWN); + + PIN_SLP(gpc1-0, INPUT, UP); + PIN_SLP(gpc1-1, PREV, NONE); + PIN_SLP(gpc1-2, INPUT, UP); + PIN_SLP(gpc1-3, INPUT, UP); + PIN_SLP(gpc1-4, INPUT, UP); + + PIN_SLP(gpd0-0, INPUT, DOWN); + PIN_SLP(gpd0-1, OUT0, NONE); + PIN_SLP(gpd0-2, INPUT, NONE); + PIN_SLP(gpd0-3, INPUT, NONE); + + PIN_SLP(gpd1-0, INPUT, DOWN); + PIN_SLP(gpd1-1, INPUT, DOWN); + PIN_SLP(gpd1-2, INPUT, NONE); + PIN_SLP(gpd1-3, INPUT, NONE); + + PIN_SLP(gpf0-0, OUT0, NONE); + PIN_SLP(gpf0-1, OUT0, NONE); + PIN_SLP(gpf0-2, OUT0, NONE); + PIN_SLP(gpf0-3, OUT0, NONE); + PIN_SLP(gpf0-4, OUT0, NONE); + PIN_SLP(gpf0-5, OUT0, NONE); + PIN_SLP(gpf0-6, OUT0, NONE); + PIN_SLP(gpf0-7, OUT0, NONE); + + PIN_SLP(gpf1-0, OUT0, NONE); + PIN_SLP(gpf1-1, OUT0, NONE); + PIN_SLP(gpf1-2, OUT0, NONE); + PIN_SLP(gpf1-3, OUT0, NONE); + PIN_SLP(gpf1-4, OUT0, NONE); + PIN_SLP(gpf1-5, OUT0, NONE); + PIN_SLP(gpf1-6, OUT0, NONE); + PIN_SLP(gpf1-7, OUT0, NONE); + + PIN_SLP(gpf2-0, OUT0, NONE); + PIN_SLP(gpf2-1, OUT0, NONE); + PIN_SLP(gpf2-2, OUT0, NONE); + PIN_SLP(gpf2-3, OUT0, NONE); + PIN_SLP(gpf2-4, OUT0, NONE); + PIN_SLP(gpf2-5, OUT0, NONE); + PIN_SLP(gpf2-6, OUT0, NONE); + PIN_SLP(gpf2-7, OUT0, NONE); + + PIN_SLP(gpf3-0, OUT0, NONE); + PIN_SLP(gpf3-1, OUT0, NONE); + PIN_SLP(gpf3-2, OUT0, NONE); + PIN_SLP(gpf3-3, OUT0, NONE); + PIN_SLP(gpf3-4, OUT0, NONE); + PIN_SLP(gpf3-5, OUT0, NONE); + + PIN_SLP(gpj0-0, INPUT, DOWN); + PIN_SLP(gpj0-1, INPUT, DOWN); + PIN_SLP(gpj0-2, INPUT, DOWN); + PIN_SLP(gpj0-3, PREV, NONE); + PIN_SLP(gpj0-4, PREV, NONE); + PIN_SLP(gpj0-5, OUT0, NONE); + PIN_SLP(gpj0-6, OUT0, NONE); + PIN_SLP(gpj0-7, OUT0, NONE); + + PIN_SLP(gpj1-0, OUT0, NONE); + PIN_SLP(gpj1-1, INPUT, DOWN); + PIN_SLP(gpj1-2, PREV, NONE); + PIN_SLP(gpj1-3, OUT0, NONE); + }; +}; + +&pinctrl_1 { + pinctrl-names = "default"; + pinctrl-0 = <&sleep1>; + + sd3_wifi: sd3-wifi { + samsung,pins = "gpk3-3", "gpk3-4", "gpk3-5", "gpk3-6"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + bt_shutdown: bt-shutdown { + samsung,pins = "gpl0-6"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + uart_sel: uart-sel { + samsung,pins = "gpl2-7"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-val = <1>; + /* 0 = CP, 1 = AP (serial output) */ + }; + + tsp_rst: tsp-rst { + samsung,pins = "gpm0-4"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + tsp_irq: tsp-irq { + samsung,pins = "gpm2-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + wifi_reset: wifi-reset { + samsung,pins = "gpm3-5"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + tsp_reg_gpio_1: tsp-reg-gpio-1 { + samsung,pins = "gpm4-5"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + ak8975_irq: ak8975-irq { + samsung,pins = "gpm4-7"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + stmpe_adc_irq: stmpe-adc-irq { + samsung,pins = "gpx0-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + max77686_irq: max77686-irq { + samsung,pins = "gpx0-7"; + samsung,pin-pud = ; + }; + + gpio_keys: gpio-keys { + samsung,pins = "gpx2-2", "gpx2-7", "gpx3-3"; + samsung,pin-pud = ; + }; + + fuel_alert_irq: fuel-alert-irq { + samsung,pins = "gpx2-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + wifi_host_wake: wifi-host-wake { + samsung,pins = "gpx2-5"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + bt_host_wakeup: bt-host-wakeup { + samsung,pins = "gpx2-6"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + bt_device_wakeup: bt-device-wakeup { + samsung,pins = "gpx3-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + sdhci2_cd: sdhci2-cd { + samsung,pins = "gpx3-4"; + samsung,pin-pud = ; + }; + + sleep1: sleep-states { + PIN_SLP(gpk0-0, PREV, NONE); + PIN_SLP(gpk0-1, PREV, NONE); + PIN_SLP(gpk0-2, PREV, NONE); + PIN_SLP(gpk0-3, PREV, NONE); + PIN_SLP(gpk0-4, PREV, NONE); + PIN_SLP(gpk0-5, PREV, NONE); + PIN_SLP(gpk0-6, PREV, NONE); + + PIN_SLP(gpk1-0, INPUT, DOWN); + PIN_SLP(gpk1-1, INPUT, DOWN); + PIN_SLP(gpk1-2, INPUT, DOWN); + PIN_SLP(gpk1-3, PREV, NONE); + PIN_SLP(gpk1-4, PREV, NONE); + PIN_SLP(gpk1-5, PREV, NONE); + PIN_SLP(gpk1-6, PREV, NONE); + + PIN_SLP(gpk2-0, INPUT, DOWN); + PIN_SLP(gpk2-1, INPUT, DOWN); + PIN_SLP(gpk2-2, INPUT, DOWN); + PIN_SLP(gpk2-3, INPUT, DOWN); + PIN_SLP(gpk2-4, INPUT, DOWN); + PIN_SLP(gpk2-5, INPUT, DOWN); + PIN_SLP(gpk2-6, INPUT, DOWN); + + PIN_SLP(gpk3-0, OUT0, NONE); + PIN_SLP(gpk3-1, INPUT, NONE); + PIN_SLP(gpk3-2, INPUT, DOWN); + PIN_SLP(gpk3-3, INPUT, NONE); + PIN_SLP(gpk3-4, INPUT, NONE); + PIN_SLP(gpk3-5, INPUT, NONE); + PIN_SLP(gpk3-6, INPUT, NONE); + + PIN_SLP(gpl0-0, OUT0, NONE); + PIN_SLP(gpl0-1, INPUT, NONE); + PIN_SLP(gpl0-2, INPUT, NONE); + PIN_SLP(gpl0-3, INPUT, DOWN); + PIN_SLP(gpl0-4, PREV, NONE); + PIN_SLP(gpl0-6, PREV, NONE); + + PIN_SLP(gpl1-0, OUT0, NONE); + PIN_SLP(gpl1-1, OUT0, NONE); + + PIN_SLP(gpl2-0, INPUT, DOWN); + PIN_SLP(gpl2-1, INPUT, DOWN); + PIN_SLP(gpl2-2, INPUT, DOWN); + PIN_SLP(gpl2-3, INPUT, DOWN); + PIN_SLP(gpl2-4, OUT0, NONE); + PIN_SLP(gpl2-5, INPUT, DOWN); + PIN_SLP(gpl2-6, PREV, NONE); + PIN_SLP(gpl2-7, PREV, NONE); + + PIN_SLP(gpm0-0, PREV, NONE); + PIN_SLP(gpm0-1, OUT0, NONE); + PIN_SLP(gpm0-2, INPUT, DOWN); + PIN_SLP(gpm0-3, INPUT, NONE); + PIN_SLP(gpm0-4, OUT0, NONE); + PIN_SLP(gpm0-5, OUT0, NONE); + PIN_SLP(gpm0-6, INPUT, DOWN); + PIN_SLP(gpm0-7, OUT0, NONE); + + PIN_SLP(gpm1-0, INPUT, NONE); + PIN_SLP(gpm1-1, INPUT, NONE); + PIN_SLP(gpm1-2, INPUT, NONE); + PIN_SLP(gpm1-3, INPUT, NONE); + PIN_SLP(gpm1-4, INPUT, NONE); + PIN_SLP(gpm1-5, INPUT, NONE); + PIN_SLP(gpm1-6, INPUT, DOWN); + + PIN_SLP(gpm2-0, INPUT, NONE); + PIN_SLP(gpm2-1, INPUT, NONE); + PIN_SLP(gpm2-2, OUT0, NONE); + PIN_SLP(gpm2-3, OUT0, DOWN); + PIN_SLP(gpm2-4, INPUT, DOWN); + + PIN_SLP(gpm3-0, PREV, NONE); + PIN_SLP(gpm3-1, PREV, NONE); + PIN_SLP(gpm3-2, PREV, NONE); + PIN_SLP(gpm3-3, OUT1, NONE); + PIN_SLP(gpm3-4, OUT0, DOWN); + PIN_SLP(gpm3-5, PREV, NONE); + PIN_SLP(gpm3-6, PREV, NONE); + PIN_SLP(gpm3-7, OUT0, NONE); + + PIN_SLP(gpm4-0, INPUT, NONE); + PIN_SLP(gpm4-1, INPUT, NONE); + PIN_SLP(gpm4-2, INPUT, DOWN); + PIN_SLP(gpm4-3, INPUT, DOWN); + PIN_SLP(gpm4-4, PREV, NONE); + PIN_SLP(gpm4-5, OUT0, NONE); + PIN_SLP(gpm4-6, OUT0, NONE); + PIN_SLP(gpm4-7, INPUT, DOWN); + + PIN_SLP(gpy0-0, INPUT, DOWN); + PIN_SLP(gpy0-1, INPUT, DOWN); + PIN_SLP(gpy0-2, INPUT, NONE); + PIN_SLP(gpy0-3, INPUT, NONE); + PIN_SLP(gpy0-4, INPUT, NONE); + PIN_SLP(gpy0-5, INPUT, NONE); + + PIN_SLP(gpy1-0, INPUT, DOWN); + PIN_SLP(gpy1-1, INPUT, DOWN); + PIN_SLP(gpy1-2, INPUT, DOWN); + PIN_SLP(gpy1-3, INPUT, DOWN); + + PIN_SLP(gpy2-0, PREV, NONE); + PIN_SLP(gpy2-1, INPUT, DOWN); + PIN_SLP(gpy2-2, INPUT, NONE); + PIN_SLP(gpy2-3, INPUT, NONE); + PIN_SLP(gpy2-4, INPUT, NONE); + PIN_SLP(gpy2-5, INPUT, NONE); + + PIN_SLP(gpy3-0, INPUT, DOWN); + PIN_SLP(gpy3-1, INPUT, DOWN); + PIN_SLP(gpy3-2, INPUT, DOWN); + PIN_SLP(gpy3-3, INPUT, DOWN); + PIN_SLP(gpy3-4, INPUT, DOWN); + PIN_SLP(gpy3-5, INPUT, DOWN); + PIN_SLP(gpy3-6, INPUT, DOWN); + PIN_SLP(gpy3-7, INPUT, DOWN); + + PIN_SLP(gpy4-0, INPUT, DOWN); + PIN_SLP(gpy4-1, INPUT, DOWN); + PIN_SLP(gpy4-2, INPUT, DOWN); + PIN_SLP(gpy4-3, INPUT, DOWN); + PIN_SLP(gpy4-4, INPUT, DOWN); + PIN_SLP(gpy4-5, INPUT, DOWN); + PIN_SLP(gpy4-6, INPUT, DOWN); + PIN_SLP(gpy4-7, INPUT, DOWN); + + PIN_SLP(gpy5-0, INPUT, DOWN); + PIN_SLP(gpy5-1, INPUT, DOWN); + PIN_SLP(gpy5-2, INPUT, DOWN); + PIN_SLP(gpy5-3, INPUT, DOWN); + PIN_SLP(gpy5-4, INPUT, DOWN); + PIN_SLP(gpy5-5, INPUT, DOWN); + PIN_SLP(gpy5-6, INPUT, DOWN); + PIN_SLP(gpy5-7, INPUT, DOWN); + + PIN_SLP(gpy6-0, INPUT, DOWN); + PIN_SLP(gpy6-1, INPUT, DOWN); + PIN_SLP(gpy6-2, INPUT, DOWN); + PIN_SLP(gpy6-3, INPUT, DOWN); + PIN_SLP(gpy6-4, INPUT, DOWN); + PIN_SLP(gpy6-5, INPUT, DOWN); + PIN_SLP(gpy6-6, INPUT, DOWN); + PIN_SLP(gpy6-7, INPUT, DOWN); + }; +}; + +&pinctrl_2 { + pinctrl-names = "default"; + pinctrl-0 = <&sleep2>; + + sleep2: sleep-states { + PIN_SLP(gpz-0, INPUT, DOWN); + PIN_SLP(gpz-1, INPUT, DOWN); + PIN_SLP(gpz-2, INPUT, DOWN); + PIN_SLP(gpz-3, INPUT, DOWN); + PIN_SLP(gpz-4, INPUT, DOWN); + PIN_SLP(gpz-5, INPUT, DOWN); + PIN_SLP(gpz-6, INPUT, DOWN); + }; +}; + +&pinctrl_3 { + pinctrl-names = "default"; + pinctrl-0 = <&sleep3>; + + sleep3: sleep-states { + PIN_SLP(gpv0-0, INPUT, DOWN); + PIN_SLP(gpv0-1, INPUT, DOWN); + PIN_SLP(gpv0-2, INPUT, DOWN); + PIN_SLP(gpv0-3, INPUT, DOWN); + PIN_SLP(gpv0-4, INPUT, DOWN); + PIN_SLP(gpv0-5, INPUT, DOWN); + PIN_SLP(gpv0-6, INPUT, DOWN); + PIN_SLP(gpv0-7, INPUT, DOWN); + + PIN_SLP(gpv1-0, INPUT, DOWN); + PIN_SLP(gpv1-1, INPUT, DOWN); + PIN_SLP(gpv1-2, INPUT, DOWN); + PIN_SLP(gpv1-3, INPUT, DOWN); + PIN_SLP(gpv1-4, INPUT, DOWN); + PIN_SLP(gpv1-5, INPUT, DOWN); + PIN_SLP(gpv1-6, INPUT, DOWN); + PIN_SLP(gpv1-7, INPUT, DOWN); + + PIN_SLP(gpv2-0, INPUT, DOWN); + PIN_SLP(gpv2-1, INPUT, DOWN); + PIN_SLP(gpv2-2, INPUT, DOWN); + PIN_SLP(gpv2-3, INPUT, DOWN); + PIN_SLP(gpv2-4, INPUT, DOWN); + PIN_SLP(gpv2-5, INPUT, DOWN); + PIN_SLP(gpv2-6, INPUT, DOWN); + PIN_SLP(gpv2-7, INPUT, DOWN); + + PIN_SLP(gpv3-0, INPUT, DOWN); + PIN_SLP(gpv3-1, INPUT, DOWN); + PIN_SLP(gpv3-2, INPUT, DOWN); + PIN_SLP(gpv3-3, INPUT, DOWN); + PIN_SLP(gpv3-4, INPUT, DOWN); + PIN_SLP(gpv3-5, INPUT, DOWN); + PIN_SLP(gpv3-6, INPUT, DOWN); + PIN_SLP(gpv3-7, INPUT, DOWN); + + PIN_SLP(gpv4-0, INPUT, DOWN); + PIN_SLP(gpv4-1, INPUT, DOWN); + }; +}; + +&pmu_system_controller { + assigned-clocks = <&pmu_system_controller 0>; + assigned-clock-parents = <&clock CLK_XUSBXTI>; +}; + +&rtc { + clocks = <&clock CLK_RTC>, <&max77686 MAX77686_CLK_AP>; + clock-names = "rtc", "rtc_src"; + status = "okay"; +}; + +&sdhci_2 { + bus-width = <4>; + cd-gpios = <&gpx3 4 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus4 &sdhci2_cd>; + pinctrl-names = "default"; + vmmc-supply = <&ldo21_reg>; + status = "okay"; +}; + +&sdhci_3 { + #address-cells = <1>; + #size-cells = <0>; + non-removable; + bus-width = <4>; + mmc-pwrseq = <&wlan_pwrseq>; + + pinctrl-names = "default"; + pinctrl-0 = <&sd3_clk &sd3_cmd &sd3_wifi>; + status = "okay"; + + wifi@1 { + compatible = "brcm,bcm4329-fmac"; + reg = <0x1>; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_host_wake>; + interrupt-parent = <&gpx2>; + interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "host-wake"; + }; +}; + +&serial_0 { + pinctrl-0 = <&uart0_data &uart0_fctl>; + pinctrl-names = "default"; + status = "okay"; + + bluetooth { + compatible = "brcm,bcm4330-bt"; + pinctrl-0 = <&bt_shutdown &bt_device_wakeup &bt_host_wakeup>; + pinctrl-names = "default"; + + max-speed = <2000000>; + shutdown-gpios = <&gpl0 6 GPIO_ACTIVE_HIGH>; + device-wakeup-gpios = <&gpx3 1 GPIO_ACTIVE_HIGH>; + host-wakeup-gpios = <&gpx2 6 GPIO_ACTIVE_HIGH>; + clocks = <&max77686 MAX77686_CLK_PMIC>; + clock-names = "lpo"; + }; +}; + +&serial_2 { + pinctrl-0 = <&uart_sel>; + pinctrl-names = "default"; + status = "okay"; +}; + +&tmu { + status = "okay"; +}; From 3e50523fe6f4b0ade2e8e0a1428e23b7503fb85c Mon Sep 17 00:00:00 2001 From: Tomer Maimon Date: Tue, 29 Sep 2020 16:18:03 +0300 Subject: [PATCH 333/799] ARM: dts: nuvoton: Modify clock parameters Modify NPCM7xx device tree clock parameter to clock constants that define at include/dt-bindings/clock/nuvoton,npcm7xx-clock.h file. Signed-off-by: Tomer Maimon Reviewed-by: Joel Stanley Link: https://lore.kernel.org/r/20200929131807.15378-2-tmaimon77@gmail.com Signed-off-by: Joel Stanley --- arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi | 19 ++++++++++--------- arch/arm/boot/dts/nuvoton-npcm750.dtsi | 6 +++--- 2 files changed, 13 insertions(+), 12 deletions(-) diff --git a/arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi b/arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi index d2d0761295a4..16a28c5c4131 100644 --- a/arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi +++ b/arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi @@ -3,6 +3,7 @@ // Copyright 2018 Google, Inc. #include +#include / { #address-cells = <1>; @@ -80,7 +81,7 @@ interrupts = ; cache-unified; cache-level = <2>; - clocks = <&clk 10>; + clocks = <&clk NPCM7XX_CLK_AXI>; arm,shared-override; }; @@ -120,7 +121,7 @@ compatible = "nuvoton,npcm750-timer"; interrupts = ; reg = <0x8000 0x50>; - clocks = <&clk 5>; + clocks = <&clk NPCM7XX_CLK_TIMER>; }; watchdog0: watchdog@801C { @@ -128,7 +129,7 @@ interrupts = ; reg = <0x801C 0x4>; status = "disabled"; - clocks = <&clk 5>; + clocks = <&clk NPCM7XX_CLK_TIMER>; }; watchdog1: watchdog@901C { @@ -136,7 +137,7 @@ interrupts = ; reg = <0x901C 0x4>; status = "disabled"; - clocks = <&clk 5>; + clocks = <&clk NPCM7XX_CLK_TIMER>; }; watchdog2: watchdog@a01C { @@ -144,13 +145,13 @@ interrupts = ; reg = <0xa01C 0x4>; status = "disabled"; - clocks = <&clk 5>; + clocks = <&clk NPCM7XX_CLK_TIMER>; }; serial0: serial@1000 { compatible = "nuvoton,npcm750-uart"; reg = <0x1000 0x1000>; - clocks = <&clk 6>; + clocks = <&clk NPCM7XX_CLK_UART>; interrupts = ; reg-shift = <2>; status = "disabled"; @@ -159,7 +160,7 @@ serial1: serial@2000 { compatible = "nuvoton,npcm750-uart"; reg = <0x2000 0x1000>; - clocks = <&clk 6>; + clocks = <&clk NPCM7XX_CLK_UART>; interrupts = ; reg-shift = <2>; status = "disabled"; @@ -168,7 +169,7 @@ serial2: serial@3000 { compatible = "nuvoton,npcm750-uart"; reg = <0x3000 0x1000>; - clocks = <&clk 6>; + clocks = <&clk NPCM7XX_CLK_UART>; interrupts = ; reg-shift = <2>; status = "disabled"; @@ -177,7 +178,7 @@ serial3: serial@4000 { compatible = "nuvoton,npcm750-uart"; reg = <0x4000 0x1000>; - clocks = <&clk 6>; + clocks = <&clk NPCM7XX_CLK_UART>; interrupts = ; reg-shift = <2>; status = "disabled"; diff --git a/arch/arm/boot/dts/nuvoton-npcm750.dtsi b/arch/arm/boot/dts/nuvoton-npcm750.dtsi index 6ac340533587..a37bb2294b8f 100644 --- a/arch/arm/boot/dts/nuvoton-npcm750.dtsi +++ b/arch/arm/boot/dts/nuvoton-npcm750.dtsi @@ -17,7 +17,7 @@ cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a9"; - clocks = <&clk 0>; + clocks = <&clk NPCM7XX_CLK_CPU>; clock-names = "clk_cpu"; reg = <0>; next-level-cache = <&l2>; @@ -26,7 +26,7 @@ cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a9"; - clocks = <&clk 0>; + clocks = <&clk NPCM7XX_CLK_CPU>; clock-names = "clk_cpu"; reg = <1>; next-level-cache = <&l2>; @@ -38,7 +38,7 @@ reg = <0x3fe600 0x20>; interrupts = ; - clocks = <&clk 5>; + clocks = <&clk NPCM7XX_CLK_AHB>; }; }; }; From 7a28a9957ce7b4ed5cc30560034f54039cd56ed8 Mon Sep 17 00:00:00 2001 From: Tomer Maimon Date: Tue, 29 Sep 2020 16:18:04 +0300 Subject: [PATCH 334/799] ARM: dts: nuvoton: Modify timer register size Modify NPCM7xx device tree timer register size from 0x50 to 0x1C to control only the timer registers and not other hw modules. Signed-off-by: Tomer Maimon Reviewed-by: Joel Stanley Link: https://lore.kernel.org/r/20200929131807.15378-3-tmaimon77@gmail.com Signed-off-by: Joel Stanley --- arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi b/arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi index 16a28c5c4131..72e364054e72 100644 --- a/arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi +++ b/arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi @@ -120,7 +120,7 @@ timer0: timer@8000 { compatible = "nuvoton,npcm750-timer"; interrupts = ; - reg = <0x8000 0x50>; + reg = <0x8000 0x1C>; clocks = <&clk NPCM7XX_CLK_TIMER>; }; From 0153c82b12233012b219b03f911aa242f5fe1e2c Mon Sep 17 00:00:00 2001 From: Tomer Maimon Date: Tue, 29 Sep 2020 16:18:05 +0300 Subject: [PATCH 335/799] ARM: dts: nuvoton: Add pinctrl and GPIO node Add pin controller and GPIO node to NPCM7XX device tree. Signed-off-by: Tomer Maimon Reviewed-by: Joel Stanley Link: https://lore.kernel.org/r/20200929131807.15378-4-tmaimon77@gmail.com Signed-off-by: Joel Stanley --- arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi | 564 ++++++++++++++++++ 1 file changed, 564 insertions(+) diff --git a/arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi b/arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi index 72e364054e72..7755a3de7c53 100644 --- a/arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi +++ b/arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi @@ -185,4 +185,568 @@ }; }; }; + + pinctrl: pinctrl@f0800000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "nuvoton,npcm750-pinctrl", "syscon", "simple-mfd"; + ranges = <0 0xf0010000 0x8000>; + gpio0: gpio@f0010000 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x0 0x80>; + interrupts = ; + gpio-ranges = <&pinctrl 0 0 32>; + }; + gpio1: gpio@f0011000 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x1000 0x80>; + interrupts = ; + gpio-ranges = <&pinctrl 0 32 32>; + }; + gpio2: gpio@f0012000 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x2000 0x80>; + interrupts = ; + gpio-ranges = <&pinctrl 0 64 32>; + }; + gpio3: gpio@f0013000 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x3000 0x80>; + interrupts = ; + gpio-ranges = <&pinctrl 0 96 32>; + }; + gpio4: gpio@f0014000 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x4000 0x80>; + interrupts = ; + gpio-ranges = <&pinctrl 0 128 32>; + }; + gpio5: gpio@f0015000 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x5000 0x80>; + interrupts = ; + gpio-ranges = <&pinctrl 0 160 32>; + }; + gpio6: gpio@f0016000 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x6000 0x80>; + interrupts = ; + gpio-ranges = <&pinctrl 0 192 32>; + }; + gpio7: gpio@f0017000 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x7000 0x80>; + interrupts = ; + gpio-ranges = <&pinctrl 0 224 32>; + }; + + iox1_pins: iox1-pins { + groups = "iox1"; + function = "iox1"; + }; + iox2_pins: iox2-pins { + groups = "iox2"; + function = "iox2"; + }; + smb1d_pins: smb1d-pins { + groups = "smb1d"; + function = "smb1d"; + }; + smb2d_pins: smb2d-pins { + groups = "smb2d"; + function = "smb2d"; + }; + lkgpo1_pins: lkgpo1-pins { + groups = "lkgpo1"; + function = "lkgpo1"; + }; + lkgpo2_pins: lkgpo2-pins { + groups = "lkgpo2"; + function = "lkgpo2"; + }; + ioxh_pins: ioxh-pins { + groups = "ioxh"; + function = "ioxh"; + }; + gspi_pins: gspi-pins { + groups = "gspi"; + function = "gspi"; + }; + smb5b_pins: smb5b-pins { + groups = "smb5b"; + function = "smb5b"; + }; + smb5c_pins: smb5c-pins { + groups = "smb5c"; + function = "smb5c"; + }; + lkgpo0_pins: lkgpo0-pins { + groups = "lkgpo0"; + function = "lkgpo0"; + }; + pspi2_pins: pspi2-pins { + groups = "pspi2"; + function = "pspi2"; + }; + smb4den_pins: smb4den-pins { + groups = "smb4den"; + function = "smb4den"; + }; + smb4b_pins: smb4b-pins { + groups = "smb4b"; + function = "smb4b"; + }; + smb4c_pins: smb4c-pins { + groups = "smb4c"; + function = "smb4c"; + }; + smb15_pins: smb15-pins { + groups = "smb15"; + function = "smb15"; + }; + smb4d_pins: smb4d-pins { + groups = "smb4d"; + function = "smb4d"; + }; + smb14_pins: smb14-pins { + groups = "smb14"; + function = "smb14"; + }; + smb5_pins: smb5-pins { + groups = "smb5"; + function = "smb5"; + }; + smb4_pins: smb4-pins { + groups = "smb4"; + function = "smb4"; + }; + smb3_pins: smb3-pins { + groups = "smb3"; + function = "smb3"; + }; + spi0cs1_pins: spi0cs1-pins { + groups = "spi0cs1"; + function = "spi0cs1"; + }; + spi0cs2_pins: spi0cs2-pins { + groups = "spi0cs2"; + function = "spi0cs2"; + }; + spi0cs3_pins: spi0cs3-pins { + groups = "spi0cs3"; + function = "spi0cs3"; + }; + smb3c_pins: smb3c-pins { + groups = "smb3c"; + function = "smb3c"; + }; + smb3b_pins: smb3b-pins { + groups = "smb3b"; + function = "smb3b"; + }; + bmcuart0a_pins: bmcuart0a-pins { + groups = "bmcuart0a"; + function = "bmcuart0a"; + }; + uart1_pins: uart1-pins { + groups = "uart1"; + function = "uart1"; + }; + jtag2_pins: jtag2-pins { + groups = "jtag2"; + function = "jtag2"; + }; + bmcuart1_pins: bmcuart1-pins { + groups = "bmcuart1"; + function = "bmcuart1"; + }; + uart2_pins: uart2-pins { + groups = "uart2"; + function = "uart2"; + }; + bmcuart0b_pins: bmcuart0b-pins { + groups = "bmcuart0b"; + function = "bmcuart0b"; + }; + r1err_pins: r1err-pins { + groups = "r1err"; + function = "r1err"; + }; + r1md_pins: r1md-pins { + groups = "r1md"; + function = "r1md"; + }; + smb3d_pins: smb3d-pins { + groups = "smb3d"; + function = "smb3d"; + }; + fanin0_pins: fanin0-pins { + groups = "fanin0"; + function = "fanin0"; + }; + fanin1_pins: fanin1-pins { + groups = "fanin1"; + function = "fanin1"; + }; + fanin2_pins: fanin2-pins { + groups = "fanin2"; + function = "fanin2"; + }; + fanin3_pins: fanin3-pins { + groups = "fanin3"; + function = "fanin3"; + }; + fanin4_pins: fanin4-pins { + groups = "fanin4"; + function = "fanin4"; + }; + fanin5_pins: fanin5-pins { + groups = "fanin5"; + function = "fanin5"; + }; + fanin6_pins: fanin6-pins { + groups = "fanin6"; + function = "fanin6"; + }; + fanin7_pins: fanin7-pins { + groups = "fanin7"; + function = "fanin7"; + }; + fanin8_pins: fanin8-pins { + groups = "fanin8"; + function = "fanin8"; + }; + fanin9_pins: fanin9-pins { + groups = "fanin9"; + function = "fanin9"; + }; + fanin10_pins: fanin10-pins { + groups = "fanin10"; + function = "fanin10"; + }; + fanin11_pins: fanin11-pins { + groups = "fanin11"; + function = "fanin11"; + }; + fanin12_pins: fanin12-pins { + groups = "fanin12"; + function = "fanin12"; + }; + fanin13_pins: fanin13-pins { + groups = "fanin13"; + function = "fanin13"; + }; + fanin14_pins: fanin14-pins { + groups = "fanin14"; + function = "fanin14"; + }; + fanin15_pins: fanin15-pins { + groups = "fanin15"; + function = "fanin15"; + }; + pwm0_pins: pwm0-pins { + groups = "pwm0"; + function = "pwm0"; + }; + pwm1_pins: pwm1-pins { + groups = "pwm1"; + function = "pwm1"; + }; + pwm2_pins: pwm2-pins { + groups = "pwm2"; + function = "pwm2"; + }; + pwm3_pins: pwm3-pins { + groups = "pwm3"; + function = "pwm3"; + }; + r2_pins: r2-pins { + groups = "r2"; + function = "r2"; + }; + r2err_pins: r2err-pins { + groups = "r2err"; + function = "r2err"; + }; + r2md_pins: r2md-pins { + groups = "r2md"; + function = "r2md"; + }; + ga20kbc_pins: ga20kbc-pins { + groups = "ga20kbc"; + function = "ga20kbc"; + }; + smb5d_pins: smb5d-pins { + groups = "smb5d"; + function = "smb5d"; + }; + lpc_pins: lpc-pins { + groups = "lpc"; + function = "lpc"; + }; + espi_pins: espi-pins { + groups = "espi"; + function = "espi"; + }; + rg1_pins: rg1-pins { + groups = "rg1"; + function = "rg1"; + }; + rg1mdio_pins: rg1mdio-pins { + groups = "rg1mdio"; + function = "rg1mdio"; + }; + rg2_pins: rg2-pins { + groups = "rg2"; + function = "rg2"; + }; + ddr_pins: ddr-pins { + groups = "ddr"; + function = "ddr"; + }; + smb0_pins: smb0-pins { + groups = "smb0"; + function = "smb0"; + }; + smb1_pins: smb1-pins { + groups = "smb1"; + function = "smb1"; + }; + smb2_pins: smb2-pins { + groups = "smb2"; + function = "smb2"; + }; + smb2c_pins: smb2c-pins { + groups = "smb2c"; + function = "smb2c"; + }; + smb2b_pins: smb2b-pins { + groups = "smb2b"; + function = "smb2b"; + }; + smb1c_pins: smb1c-pins { + groups = "smb1c"; + function = "smb1c"; + }; + smb1b_pins: smb1b-pins { + groups = "smb1b"; + function = "smb1b"; + }; + smb8_pins: smb8-pins { + groups = "smb8"; + function = "smb8"; + }; + smb9_pins: smb9-pins { + groups = "smb9"; + function = "smb9"; + }; + smb10_pins: smb10-pins { + groups = "smb10"; + function = "smb10"; + }; + smb11_pins: smb11-pins { + groups = "smb11"; + function = "smb11"; + }; + sd1_pins: sd1-pins { + groups = "sd1"; + function = "sd1"; + }; + sd1pwr_pins: sd1pwr-pins { + groups = "sd1pwr"; + function = "sd1pwr"; + }; + pwm4_pins: pwm4-pins { + groups = "pwm4"; + function = "pwm4"; + }; + pwm5_pins: pwm5-pins { + groups = "pwm5"; + function = "pwm5"; + }; + pwm6_pins: pwm6-pins { + groups = "pwm6"; + function = "pwm6"; + }; + pwm7_pins: pwm7-pins { + groups = "pwm7"; + function = "pwm7"; + }; + mmc8_pins: mmc8-pins { + groups = "mmc8"; + function = "mmc8"; + }; + mmc_pins: mmc-pins { + groups = "mmc"; + function = "mmc"; + }; + mmcwp_pins: mmcwp-pins { + groups = "mmcwp"; + function = "mmcwp"; + }; + mmccd_pins: mmccd-pins { + groups = "mmccd"; + function = "mmccd"; + }; + mmcrst_pins: mmcrst-pins { + groups = "mmcrst"; + function = "mmcrst"; + }; + clkout_pins: clkout-pins { + groups = "clkout"; + function = "clkout"; + }; + serirq_pins: serirq-pins { + groups = "serirq"; + function = "serirq"; + }; + lpcclk_pins: lpcclk-pins { + groups = "lpcclk"; + function = "lpcclk"; + }; + scipme_pins: scipme-pins { + groups = "scipme"; + function = "scipme"; + }; + sci_pins: sci-pins { + groups = "sci"; + function = "sci"; + }; + smb6_pins: smb6-pins { + groups = "smb6"; + function = "smb6"; + }; + smb7_pins: smb7-pins { + groups = "smb7"; + function = "smb7"; + }; + pspi1_pins: pspi1-pins { + groups = "pspi1"; + function = "pspi1"; + }; + faninx_pins: faninx-pins { + groups = "faninx"; + function = "faninx"; + }; + r1_pins: r1-pins { + groups = "r1"; + function = "r1"; + }; + spi3_pins: spi3-pins { + groups = "spi3"; + function = "spi3"; + }; + spi3cs1_pins: spi3cs1-pins { + groups = "spi3cs1"; + function = "spi3cs1"; + }; + spi3quad_pins: spi3quad-pins { + groups = "spi3quad"; + function = "spi3quad"; + }; + spi3cs2_pins: spi3cs2-pins { + groups = "spi3cs2"; + function = "spi3cs2"; + }; + spi3cs3_pins: spi3cs3-pins { + groups = "spi3cs3"; + function = "spi3cs3"; + }; + nprd_smi_pins: nprd-smi-pins { + groups = "nprd_smi"; + function = "nprd_smi"; + }; + smb0b_pins: smb0b-pins { + groups = "smb0b"; + function = "smb0b"; + }; + smb0c_pins: smb0c-pins { + groups = "smb0c"; + function = "smb0c"; + }; + smb0den_pins: smb0den-pins { + groups = "smb0den"; + function = "smb0den"; + }; + smb0d_pins: smb0d-pins { + groups = "smb0d"; + function = "smb0d"; + }; + ddc_pins: ddc-pins { + groups = "ddc"; + function = "ddc"; + }; + rg2mdio_pins: rg2mdio-pins { + groups = "rg2mdio"; + function = "rg2mdio"; + }; + wdog1_pins: wdog1-pins { + groups = "wdog1"; + function = "wdog1"; + }; + wdog2_pins: wdog2-pins { + groups = "wdog2"; + function = "wdog2"; + }; + smb12_pins: smb12-pins { + groups = "smb12"; + function = "smb12"; + }; + smb13_pins: smb13-pins { + groups = "smb13"; + function = "smb13"; + }; + spix_pins: spix-pins { + groups = "spix"; + function = "spix"; + }; + spixcs1_pins: spixcs1-pins { + groups = "spixcs1"; + function = "spixcs1"; + }; + clkreq_pins: clkreq-pins { + groups = "clkreq"; + function = "clkreq"; + }; + hgpio0_pins: hgpio0-pins { + groups = "hgpio0"; + function = "hgpio0"; + }; + hgpio1_pins: hgpio1-pins { + groups = "hgpio1"; + function = "hgpio1"; + }; + hgpio2_pins: hgpio2-pins { + groups = "hgpio2"; + function = "hgpio2"; + }; + hgpio3_pins: hgpio3-pins { + groups = "hgpio3"; + function = "hgpio3"; + }; + hgpio4_pins: hgpio4-pins { + groups = "hgpio4"; + function = "hgpio4"; + }; + hgpio5_pins: hgpio5-pins { + groups = "hgpio5"; + function = "hgpio5"; + }; + hgpio6_pins: hgpio6-pins { + groups = "hgpio6"; + function = "hgpio6"; + }; + hgpio7_pins: hgpio7-pins { + groups = "hgpio7"; + function = "hgpio7"; + }; + }; }; From 77c72b33f0b3bfc1609d7ad8d20980ba7854e955 Mon Sep 17 00:00:00 2001 From: Tomer Maimon Date: Tue, 29 Sep 2020 16:18:06 +0300 Subject: [PATCH 336/799] ARM: dts: nuvoton: Add new device nodes Add the following new device nodes to NPCM7XX: - NPCM7xx PWM and FAN. - NPCM7xx EHCI USB. - NPCM7xx KCS. - NPCM Reset. - NPCM Peripheral SPI. - NPCM FIU SPI. - NPCM HWRNG. - NPCM I2C. - STMicro STMMAC. Signed-off-by: Tomer Maimon Reviewed-by: Joel Stanley Link: https://lore.kernel.org/r/20200929131807.15378-5-tmaimon77@gmail.com Signed-off-by: Joel Stanley --- arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi | 382 +++++++++++++++++- arch/arm/boot/dts/nuvoton-npcm750.dtsi | 18 + 2 files changed, 394 insertions(+), 6 deletions(-) diff --git a/arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi b/arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi index 7755a3de7c53..3696980a3da1 100644 --- a/arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi +++ b/arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi @@ -4,6 +4,7 @@ #include #include +#include / { #address-cells = <1>; @@ -64,12 +65,6 @@ interrupt-parent = <&gic>; ranges = <0x0 0xf0000000 0x00900000>; - gcr: gcr@800000 { - compatible = "nuvoton,npcm750-gcr", "syscon", - "simple-mfd"; - reg = <0x800000 0x1000>; - }; - scu: scu@3fe000 { compatible = "arm,cortex-a9-scu"; reg = <0x3fe000 0x1000>; @@ -92,6 +87,16 @@ reg = <0x3ff000 0x1000>, <0x3fe100 0x100>; }; + + gcr: gcr@800000 { + compatible = "nuvoton,npcm750-gcr", "syscon", "simple-mfd"; + reg = <0x800000 0x1000>; + }; + + rst: rst@801000 { + compatible = "nuvoton,npcm750-rst", "syscon", "simple-mfd"; + reg = <0x801000 0x6C>; + }; }; ahb { @@ -101,6 +106,12 @@ interrupt-parent = <&gic>; ranges; + rstc: rstc@f0801000 { + compatible = "nuvoton,npcm750-reset"; + reg = <0xf0801000 0x70>; + #reset-cells = <2>; + }; + clk: clock-controller@f0801000 { compatible = "nuvoton,npcm750-clk", "syscon"; #clock-cells = <1>; @@ -110,6 +121,63 @@ clocks = <&clk_refclk>, <&clk_sysbypck>, <&clk_mcbypck>; }; + gmac0: eth@f0802000 { + device_type = "network"; + compatible = "snps,dwmac"; + reg = <0xf0802000 0x2000>; + interrupts = ; + interrupt-names = "macirq"; + ethernet = <0>; + clocks = <&clk_rg1refck>, <&clk NPCM7XX_CLK_AHB>; + clock-names = "stmmaceth", "clk_gmac"; + pinctrl-names = "default"; + pinctrl-0 = <&rg1_pins + &rg1mdio_pins>; + status = "disabled"; + }; + + ehci1: usb@f0806000 { + compatible = "nuvoton,npcm750-ehci"; + reg = <0xf0806000 0x1000>; + interrupts = ; + status = "disabled"; + }; + + fiu0: spi@fb000000 { + compatible = "nuvoton,npcm750-fiu"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xfb000000 0x1000>; + reg-names = "control", "memory"; + clocks = <&clk NPCM7XX_CLK_SPI0>; + clock-names = "clk_spi0"; + status = "disabled"; + }; + + fiu3: spi@c0000000 { + compatible = "nuvoton,npcm750-fiu"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xc0000000 0x1000>; + reg-names = "control", "memory"; + clocks = <&clk NPCM7XX_CLK_SPI3>; + clock-names = "clk_spi3"; + pinctrl-names = "default"; + pinctrl-0 = <&spi3_pins>; + status = "disabled"; + }; + + fiux: spi@fb001000 { + compatible = "nuvoton,npcm750-fiu"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xfb001000 0x1000>; + reg-names = "control", "memory"; + clocks = <&clk NPCM7XX_CLK_SPIX>; + clock-names = "clk_spix"; + status = "disabled"; + }; + apb { #address-cells = <1>; #size-cells = <1>; @@ -117,6 +185,68 @@ interrupt-parent = <&gic>; ranges = <0x0 0xf0000000 0x00300000>; + lpc_kcs: lpc_kcs@7000 { + compatible = "nuvoton,npcm750-lpc-kcs", "simple-mfd", "syscon"; + reg = <0x7000 0x40>; + reg-io-width = <1>; + + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x7000 0x40>; + + kcs1: kcs1@0 { + compatible = "nuvoton,npcm750-kcs-bmc"; + reg = <0x0 0x40>; + interrupts = ; + kcs_chan = <1>; + status = "disabled"; + }; + + kcs2: kcs2@0 { + compatible = "nuvoton,npcm750-kcs-bmc"; + reg = <0x0 0x40>; + interrupts = ; + kcs_chan = <2>; + status = "disabled"; + }; + + kcs3: kcs3@0 { + compatible = "nuvoton,npcm750-kcs-bmc"; + reg = <0x0 0x40>; + interrupts = ; + kcs_chan = <3>; + status = "disabled"; + }; + }; + + spi0: spi@200000 { + compatible = "nuvoton,npcm750-pspi"; + reg = <0x200000 0x1000>; + pinctrl-names = "default"; + pinctrl-0 = <&pspi1_pins>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&clk NPCM7XX_CLK_APB5>; + clock-names = "clk_apb5"; + resets = <&rstc NPCM7XX_RESET_IPSRST2 NPCM7XX_RESET_PSPI1>; + status = "disabled"; + }; + + spi1: spi@201000 { + compatible = "nuvoton,npcm750-pspi"; + reg = <0x201000 0x1000>; + pinctrl-names = "default"; + pinctrl-0 = <&pspi2_pins>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&clk NPCM7XX_CLK_APB5>; + clock-names = "clk_apb5"; + resets = <&rstc NPCM7XX_RESET_IPSRST2 NPCM7XX_RESET_PSPI2>; + status = "disabled"; + }; + timer0: timer@8000 { compatible = "nuvoton,npcm750-timer"; interrupts = ; @@ -183,6 +313,246 @@ reg-shift = <2>; status = "disabled"; }; + + rng: rng@b000 { + compatible = "nuvoton,npcm750-rng"; + reg = <0xb000 0x8>; + status = "disabled"; + }; + + adc: adc@c000 { + compatible = "nuvoton,npcm750-adc"; + reg = <0xc000 0x8>; + interrupts = ; + clocks = <&clk NPCM7XX_CLK_ADC>; + resets = <&rstc NPCM7XX_RESET_IPSRST1 NPCM7XX_RESET_ADC>; + status = "disabled"; + }; + + pwm_fan: pwm-fan-controller@103000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nuvoton,npcm750-pwm-fan"; + reg = <0x103000 0x2000>, <0x180000 0x8000>; + reg-names = "pwm", "fan"; + clocks = <&clk NPCM7XX_CLK_APB3>, + <&clk NPCM7XX_CLK_APB4>; + clock-names = "pwm","fan"; + interrupts = , + , + , + , + , + , + , + ; + pinctrl-names = "default"; + pinctrl-0 = <&pwm0_pins &pwm1_pins + &pwm2_pins &pwm3_pins + &pwm4_pins &pwm5_pins + &pwm6_pins &pwm7_pins + &fanin0_pins &fanin1_pins + &fanin2_pins &fanin3_pins + &fanin4_pins &fanin5_pins + &fanin6_pins &fanin7_pins + &fanin8_pins &fanin9_pins + &fanin10_pins &fanin11_pins + &fanin12_pins &fanin13_pins + &fanin14_pins &fanin15_pins>; + status = "disabled"; + }; + + i2c0: i2c@80000 { + reg = <0x80000 0x1000>; + compatible = "nuvoton,npcm750-i2c"; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clk NPCM7XX_CLK_APB2>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&smb0_pins>; + status = "disabled"; + }; + + i2c1: i2c@81000 { + reg = <0x81000 0x1000>; + compatible = "nuvoton,npcm750-i2c"; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clk NPCM7XX_CLK_APB2>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&smb1_pins>; + status = "disabled"; + }; + + i2c2: i2c@82000 { + reg = <0x82000 0x1000>; + compatible = "nuvoton,npcm750-i2c"; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clk NPCM7XX_CLK_APB2>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&smb2_pins>; + status = "disabled"; + }; + + i2c3: i2c@83000 { + reg = <0x83000 0x1000>; + compatible = "nuvoton,npcm750-i2c"; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clk NPCM7XX_CLK_APB2>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&smb3_pins>; + status = "disabled"; + }; + + i2c4: i2c@84000 { + reg = <0x84000 0x1000>; + compatible = "nuvoton,npcm750-i2c"; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clk NPCM7XX_CLK_APB2>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&smb4_pins>; + status = "disabled"; + }; + + i2c5: i2c@85000 { + reg = <0x85000 0x1000>; + compatible = "nuvoton,npcm750-i2c"; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clk NPCM7XX_CLK_APB2>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&smb5_pins>; + status = "disabled"; + }; + + i2c6: i2c@86000 { + reg = <0x86000 0x1000>; + compatible = "nuvoton,npcm750-i2c"; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clk NPCM7XX_CLK_APB2>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&smb6_pins>; + status = "disabled"; + }; + + i2c7: i2c@87000 { + reg = <0x87000 0x1000>; + compatible = "nuvoton,npcm750-i2c"; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clk NPCM7XX_CLK_APB2>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&smb7_pins>; + status = "disabled"; + }; + + i2c8: i2c@88000 { + reg = <0x88000 0x1000>; + compatible = "nuvoton,npcm750-i2c"; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clk NPCM7XX_CLK_APB2>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&smb8_pins>; + status = "disabled"; + }; + + i2c9: i2c@89000 { + reg = <0x89000 0x1000>; + compatible = "nuvoton,npcm750-i2c"; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clk NPCM7XX_CLK_APB2>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&smb9_pins>; + status = "disabled"; + }; + + i2c10: i2c@8a000 { + reg = <0x8a000 0x1000>; + compatible = "nuvoton,npcm750-i2c"; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clk NPCM7XX_CLK_APB2>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&smb10_pins>; + status = "disabled"; + }; + + i2c11: i2c@8b000 { + reg = <0x8b000 0x1000>; + compatible = "nuvoton,npcm750-i2c"; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clk NPCM7XX_CLK_APB2>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&smb11_pins>; + status = "disabled"; + }; + + i2c12: i2c@8c000 { + reg = <0x8c000 0x1000>; + compatible = "nuvoton,npcm750-i2c"; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clk NPCM7XX_CLK_APB2>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&smb12_pins>; + status = "disabled"; + }; + + i2c13: i2c@8d000 { + reg = <0x8d000 0x1000>; + compatible = "nuvoton,npcm750-i2c"; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clk NPCM7XX_CLK_APB2>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&smb13_pins>; + status = "disabled"; + }; + + i2c14: i2c@8e000 { + reg = <0x8e000 0x1000>; + compatible = "nuvoton,npcm750-i2c"; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clk NPCM7XX_CLK_APB2>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&smb14_pins>; + status = "disabled"; + }; + + i2c15: i2c@8f000 { + reg = <0x8f000 0x1000>; + compatible = "nuvoton,npcm750-i2c"; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clk NPCM7XX_CLK_APB2>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&smb15_pins>; + status = "disabled"; + }; }; }; diff --git a/arch/arm/boot/dts/nuvoton-npcm750.dtsi b/arch/arm/boot/dts/nuvoton-npcm750.dtsi index a37bb2294b8f..13eee0fe5642 100644 --- a/arch/arm/boot/dts/nuvoton-npcm750.dtsi +++ b/arch/arm/boot/dts/nuvoton-npcm750.dtsi @@ -32,6 +32,7 @@ next-level-cache = <&l2>; }; }; + soc { timer@3fe600 { compatible = "arm,cortex-a9-twd-timer"; @@ -41,4 +42,21 @@ clocks = <&clk NPCM7XX_CLK_AHB>; }; }; + + ahb { + gmac1: eth@f0804000 { + device_type = "network"; + compatible = "snps,dwmac"; + reg = <0xf0804000 0x2000>; + interrupts = ; + interrupt-names = "macirq"; + ethernet = <1>; + clocks = <&clk_rg2refck>, <&clk NPCM7XX_CLK_AHB>; + clock-names = "stmmaceth", "clk_gmac"; + pinctrl-names = "default"; + pinctrl-0 = <&rg2_pins + &rg2mdio_pins>; + status = "disabled"; + }; + }; }; From e42b650f828d275840ab6403289249b8029e99e6 Mon Sep 17 00:00:00 2001 From: Tomer Maimon Date: Tue, 29 Sep 2020 16:18:07 +0300 Subject: [PATCH 337/799] ARM: dts: nuvoton: Add new device nodes to NPCM750 EVB Add the following new device nodes to NPCM750 evolution board device tree: - NPCM7xx Pin controller and GPIO - NPCM7xx PWM and FAN - NPCM7xx EHCI USB - NPCM7xx KCS - NPCM Reset - NPCM Peripheral SPI - NPCM FIU SPI - NPCM HWRNG - NPCM I2C - STMicro STMMAC Signed-off-by: Tomer Maimon Reviewed-by: Joel Stanley Link: https://lore.kernel.org/r/20200929131807.15378-6-tmaimon77@gmail.com Signed-off-by: Joel Stanley --- arch/arm/boot/dts/nuvoton-npcm750-evb.dts | 367 +++++++++++++++++- .../boot/dts/nuvoton-npcm750-pincfg-evb.dtsi | 157 ++++++++ 2 files changed, 523 insertions(+), 1 deletion(-) create mode 100644 arch/arm/boot/dts/nuvoton-npcm750-pincfg-evb.dtsi diff --git a/arch/arm/boot/dts/nuvoton-npcm750-evb.dts b/arch/arm/boot/dts/nuvoton-npcm750-evb.dts index 15f744f1beea..9f13d08f5804 100644 --- a/arch/arm/boot/dts/nuvoton-npcm750-evb.dts +++ b/arch/arm/boot/dts/nuvoton-npcm750-evb.dts @@ -4,24 +4,161 @@ /dts-v1/; #include "nuvoton-npcm750.dtsi" +#include "dt-bindings/gpio/gpio.h" +#include "nuvoton-npcm750-pincfg-evb.dtsi" / { model = "Nuvoton npcm750 Development Board (Device Tree)"; compatible = "nuvoton,npcm750"; + aliases { + ethernet2 = &gmac0; + ethernet3 = &gmac1; + serial0 = &serial0; + serial1 = &serial1; + serial2 = &serial2; + serial3 = &serial3; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + i2c5 = &i2c5; + i2c6 = &i2c6; + i2c7 = &i2c7; + i2c8 = &i2c8; + i2c9 = &i2c9; + i2c10 = &i2c10; + i2c11 = &i2c11; + i2c12 = &i2c12; + i2c13 = &i2c13; + i2c14 = &i2c14; + i2c15 = &i2c15; + spi0 = &spi0; + spi1 = &spi1; + fiu0 = &fiu0; + fiu1 = &fiu3; + fiu2 = &fiux; + }; + chosen { stdout-path = &serial3; }; memory { - reg = <0 0x40000000>; + device_type = "memory"; + reg = <0x0 0x20000000>; }; }; +&gmac0 { + phy-mode = "rgmii-id"; + status = "okay"; +}; + +&gmac1 { + phy-mode = "rgmii-id"; + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&fiu0 { + status = "okay"; + spi-nor@0 { + compatible = "jedec,spi-nor"; + #address-cells = <1>; + #size-cells = <1>; + spi-rx-bus-width = <2>; + reg = <0>; + spi-max-frequency = <5000000>; + partitions@80000000 { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + bbuboot1@0 { + label = "bb-uboot-1"; + reg = <0x0000000 0x80000>; + read-only; + }; + bbuboot2@80000 { + label = "bb-uboot-2"; + reg = <0x0080000 0x80000>; + read-only; + }; + envparam@100000 { + label = "env-param"; + reg = <0x0100000 0x40000>; + read-only; + }; + spare@140000 { + label = "spare"; + reg = <0x0140000 0xC0000>; + }; + kernel@200000 { + label = "kernel"; + reg = <0x0200000 0x400000>; + }; + rootfs@600000 { + label = "rootfs"; + reg = <0x0600000 0x700000>; + }; + spare1@D00000 { + label = "spare1"; + reg = <0x0D00000 0x200000>; + }; + spare2@0F00000 { + label = "spare2"; + reg = <0x0F00000 0x200000>; + }; + spare3@1100000 { + label = "spare3"; + reg = <0x1100000 0x200000>; + }; + spare4@1300000 { + label = "spare4"; + reg = <0x1300000 0x0>; + }; + }; + }; +}; + +&fiu3 { + pinctrl-0 = <&spi3_pins>, <&spi3quad_pins>; + status = "okay"; + spi-nor@0 { + compatible = "jedec,spi-nor"; + #address-cells = <1>; + #size-cells = <1>; + spi-rx-bus-width = <2>; + reg = <0>; + spi-max-frequency = <5000000>; + partitions@A0000000 { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + system1@0 { + label = "spi3-system1"; + reg = <0x0 0x0>; + }; + }; + }; +}; + +&fiux { + spix-mode; +}; + &watchdog1 { status = "okay"; }; +&rng { + status = "okay"; +}; + &serial0 { status = "okay"; }; @@ -37,3 +174,231 @@ &serial3 { status = "okay"; }; + +&adc { + status = "okay"; +}; + +&lpc_kcs { + kcs1: kcs1@0 { + status = "okay"; + }; + + kcs2: kcs2@0 { + status = "okay"; + }; + + kcs3: kcs3@0 { + status = "okay"; + }; +}; + +/* lm75 on SVB */ +&i2c0 { + clock-frequency = <100000>; + status = "okay"; + lm75@48 { + compatible = "lm75"; + reg = <0x48>; + status = "okay"; + }; +}; + +/* lm75 on EB */ +&i2c1 { + clock-frequency = <100000>; + status = "okay"; + lm75@48 { + compatible = "lm75"; + reg = <0x48>; + status = "okay"; + }; +}; + +/* tmp100 on EB */ +&i2c2 { + clock-frequency = <100000>; + status = "okay"; + tmp100@48 { + compatible = "tmp100"; + reg = <0x48>; + status = "okay"; + }; +}; + +&i2c3 { + clock-frequency = <100000>; + status = "okay"; +}; + +&i2c5 { + clock-frequency = <100000>; + status = "okay"; +}; + +/* tmp100 on SVB */ +&i2c6 { + clock-frequency = <100000>; + status = "okay"; + tmp100@48 { + compatible = "tmp100"; + reg = <0x48>; + status = "okay"; + }; +}; + +&i2c7 { + clock-frequency = <100000>; + status = "okay"; +}; + +&i2c8 { + clock-frequency = <100000>; + status = "okay"; +}; + +&i2c9 { + clock-frequency = <100000>; + status = "okay"; +}; + +&i2c10 { + clock-frequency = <100000>; + status = "okay"; +}; + +&i2c11 { + clock-frequency = <100000>; + status = "okay"; +}; + +&i2c14 { + clock-frequency = <100000>; + status = "okay"; +}; + +&pwm_fan { + status = "okay"; + fan@0 { + reg = <0x00>; + fan-tach-ch = /bits/ 8 <0x00 0x01>; + cooling-levels = <127 255>; + }; + fan@1 { + reg = <0x01>; + fan-tach-ch = /bits/ 8 <0x02 0x03>; + cooling-levels = /bits/ 8 <127 255>; + }; + fan@2 { + reg = <0x02>; + fan-tach-ch = /bits/ 8 <0x04 0x05>; + cooling-levels = /bits/ 8 <127 255>; + }; + fan@3 { + reg = <0x03>; + fan-tach-ch = /bits/ 8 <0x06 0x07>; + cooling-levels = /bits/ 8 <127 255>; + }; + fan@4 { + reg = <0x04>; + fan-tach-ch = /bits/ 8 <0x08 0x09>; + cooling-levels = /bits/ 8 <127 255>; + }; + fan@5 { + reg = <0x05>; + fan-tach-ch = /bits/ 8 <0x0A 0x0B>; + cooling-levels = /bits/ 8 <127 255>; + }; + fan@6 { + reg = <0x06>; + fan-tach-ch = /bits/ 8 <0x0C 0x0D>; + cooling-levels = /bits/ 8 <127 255>; + }; + fan@7 { + reg = <0x07>; + fan-tach-ch = /bits/ 8 <0x0E 0x0F>; + cooling-levels = /bits/ 8 <127 255>; + }; +}; + +&spi0 { + cs-gpios = <&gpio6 11 GPIO_ACTIVE_LOW>; + status = "okay"; + Flash@0 { + compatible = "winbond,w25q128", + "jedec,spi-nor"; + reg = <0x0>; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <5000000>; + partition@0 { + label = "spi0_spare1"; + reg = <0x0000000 0x800000>; + }; + partition@1 { + label = "spi0_spare2"; + reg = <0x800000 0x0>; + }; + }; +}; + +&spi1 { + cs-gpios = <&gpio0 20 GPIO_ACTIVE_LOW>; + status = "okay"; + Flash@0 { + compatible = "winbond,w25q128fw", + "jedec,spi-nor"; + reg = <0x0>; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <5000000>; + partition@0 { + label = "spi1_spare1"; + reg = <0x0000000 0x800000>; + }; + partition@1 { + label = "spi1_spare2"; + reg = <0x800000 0x0>; + }; + }; +}; + +&pinctrl { + pinctrl-names = "default"; + pinctrl-0 = < &iox1_pins + &pin8_input + &pin9_output_high + &pin10_input + &pin11_output_high + &pin16_input + &pin24_output_high + &pin25_output_low + &pin32_output_high + &jtag2_pins + &pin61_output_high + &pin62_output_high + &pin63_output_high + &lpc_pins + &pin160_input + &pin162_input + &pin168_input + &pin169_input + &pin170_input + &pin187_output_high + &pin190_input + &pin191_output_high + &pin192_output_high + &pin197_output_low + &ddc_pins + &pin218_input + &pin219_output_low + &pin220_output_low + &pin221_output_high + &pin222_input + &pin223_output_low + &spix_pins + &pin228_output_low + &pin231_output_high + &pin255_input>; +}; + diff --git a/arch/arm/boot/dts/nuvoton-npcm750-pincfg-evb.dtsi b/arch/arm/boot/dts/nuvoton-npcm750-pincfg-evb.dtsi new file mode 100644 index 000000000000..3b3806274adf --- /dev/null +++ b/arch/arm/boot/dts/nuvoton-npcm750-pincfg-evb.dtsi @@ -0,0 +1,157 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (c) 2018 Nuvoton Technology + +/ { + pinctrl: pinctrl@f0800000 { + pin8_input: pin8-input { + pins = "GPIO8/LKGPO1"; + bias-disable; + input-enable; + }; + pin9_output_high: pin9-output-high { + pins = "GPIO9/LKGPO2"; + bias-disable; + output-high; + }; + pin10_input: pin10-input { + pins = "GPIO10/IOXHLD"; + bias-disable; + input-enable; + }; + pin11_output_high: pin11-output-high { + pins = "GPIO11/IOXHCK"; + bias-disable; + output-high; + }; + pin16_input: pin16-input { + pins = "GPIO16/LKGPO0"; + bias-disable; + input-enable; + }; + pin24_output_high: pin24-output-high { + pins = "GPIO24/IOXHDO"; + bias-disable; + output-high; + }; + pin25_output_low: pin25-output-low { + pins = "GPIO25/IOXHDI"; + bias-disable; + output-low; + }; + pin32_output_high: pin32-output-high { + pins = "GPIO32/nSPI0CS1"; + bias-disable; + output-high; + }; + pin61_output_high: pin61-output-high { + pins = "GPO61/nDTR1_BOUT1/STRAP6"; + bias-disable; + output-high; + }; + pin62_output_high: pin62-output-high { + pins = "GPO62/nRTST1/STRAP5"; + bias-disable; + output-high; + }; + pin63_output_high: pin63-output-high { + pins = "GPO63/TXD1/STRAP4"; + bias-disable; + output-high; + }; + pin160_input: pin160-input { + pins = "GPIO160/CLKOUT/RNGOSCOUT"; + bias-disable; + input-enable; + }; + pin162_input: pin162-input { + pins = "GPIO162/SERIRQ"; + bias-disable; + input-enable; + }; + pin168_input: pin168-input { + pins = "GPIO168/nCLKRUN/nESPIALERT"; + bias-disable; + input-enable; + }; + pin169_input: pin169-input { + pins = "GPIO169/nSCIPME"; + bias-disable; + input-enable; + }; + pin170_input: pin170-input { + pins = "GPIO170/nSMI"; + bias-disable; + input-enable; + }; + pin187_output_high: pin187-output-high { + pins = "GPIO187/nSPI3CS1"; + bias-disable; + output-high; + }; + pin190_input: pin190-input { + pins = "GPIO190/nPRD_SMI"; + bias-disable; + input-enable; + }; + pin191_output_high: pin191-output-high { + pins = "GPIO191"; + bias-disable; + output-high; + }; + pin192_output_high: pin192-output-high { + pins = "GPIO192"; + bias-disable; + output-high; + }; + pin197_output_low: pin197-output-low { + pins = "GPIO197/SMB0DEN"; + bias-disable; + output-low; + }; + pin218_input: pin218-input { + pins = "GPIO218/nWDO1"; + bias-disable; + input-enable; + }; + pin219_output_low: pin219-output-low { + pins = "GPIO219/nWDO2"; + bias-disable; + output-low; + }; + pin220_output_low: pin220-output-low { + pins = "GPIO220/SMB12SCL"; + bias-disable; + output-low; + }; + pin221_output_high: pin221-output-high { + pins = "GPIO221/SMB12SDA"; + bias-disable; + output-high; + }; + pin222_input: pin222-input { + pins = "GPIO222/SMB13SCL"; + bias-disable; + input-enable; + }; + pin223_output_low: pin223-output-low { + pins = "GPIO223/SMB13SDA"; + bias-disable; + output-low; + }; + pin228_output_low: pin228-output-low { + pins = "GPIO228/nSPIXCS1"; + bias-disable; + output-low; + }; + pin231_output_high: pin231-output-high { + pins = "GPIO230/SPIXD3"; + bias-disable; + output-high; + }; + pin255_input: pin255-input { + pins = "GPI255/DACOSEL"; + bias-disable; + input-enable; + }; + }; +}; From 3e1f79e4311248c8b20f3bc988f898b11aa1a887 Mon Sep 17 00:00:00 2001 From: Hugues Fruchet Date: Thu, 8 Oct 2020 11:09:42 +0200 Subject: [PATCH 338/799] ARM: dts: stm32: fix DCMI DMA features on stm32mp15 family Enable FIFO mode with half-full threshold. Signed-off-by: Hugues Fruchet Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp151.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/stm32mp151.dtsi b/arch/arm/boot/dts/stm32mp151.dtsi index 84757901cd8d..00361d9f0187 100644 --- a/arch/arm/boot/dts/stm32mp151.dtsi +++ b/arch/arm/boot/dts/stm32mp151.dtsi @@ -1098,7 +1098,7 @@ resets = <&rcc CAMITF_R>; clocks = <&rcc DCMI>; clock-names = "mclk"; - dmas = <&dmamux1 75 0x400 0x0d>; + dmas = <&dmamux1 75 0x400 0x01>; dma-names = "tx"; status = "disabled"; }; From 516728273ddfbf51b3d0fcaac05d26e299a7b456 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Thu, 8 Oct 2020 21:36:18 +0200 Subject: [PATCH 339/799] ARM: dts: stm32: Connect PHY IRQ line on DH STM32MP1 SoM On the production DHCOM STM32MP15xx SoM, the PHY IRQ line is connected to the PI11 pin. Describe it in the DT as well, so the PHY IRQ can be used e.g. to detect cable insertion and removal. Signed-off-by: Marek Vasut Cc: Alexandre Torgue Cc: Maxime Coquelin Cc: Patrice Chotard Cc: Patrick Delaunay Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi b/arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi index f796a6150313..e257459c34dc 100644 --- a/arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi +++ b/arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi @@ -127,6 +127,8 @@ phy0: ethernet-phy@1 { reg = <1>; + interrupt-parent = <&gpioi>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; }; }; }; From b0c0c8b400d5047dd0fce13d73cf63f33716641a Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Thu, 8 Oct 2020 21:37:59 +0200 Subject: [PATCH 340/799] ARM: dts: stm32: Add alternate pinmux for FMC EBI bus Add another mux option for FMC EBI bus, this is used on DHCOM SoM for the second ethernet and on the PDK2 devkit for SRAM. Signed-off-by: Marek Vasut Cc: Alexandre Torgue Cc: Maxime Coquelin Cc: Patrice Chotard Cc: Patrick Delaunay Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp15-pinctrl.dtsi | 55 ++++++++++++++++++++++++ 1 file changed, 55 insertions(+) diff --git a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi index d84686e00370..9dbefa77b03e 100644 --- a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi +++ b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi @@ -349,6 +349,61 @@ }; }; + fmc_pins_b: fmc-1 { + pins { + pinmux = , /* FMC_NOE */ + , /* FMC_NWE */ + , /* FMC_NL */ + , /* FMC_D0 */ + , /* FMC_D1 */ + , /* FMC_D2 */ + , /* FMC_D3 */ + , /* FMC_D4 */ + , /* FMC_D5 */ + , /* FMC_D6 */ + , /* FMC_D7 */ + , /* FMC_D8 */ + , /* FMC_D9 */ + , /* FMC_D10 */ + , /* FMC_D11 */ + , /* FMC_D12 */ + , /* FMC_D13 */ + , /* FMC_D14 */ + , /* FMC_D15 */ + , /* FMC_NE2_FMC_NCE */ + ; /* FMC_NE4 */ + bias-disable; + drive-push-pull; + slew-rate = <3>; + }; + }; + + fmc_sleep_pins_b: fmc-sleep-1 { + pins { + pinmux = , /* FMC_NOE */ + , /* FMC_NWE */ + , /* FMC_NL */ + , /* FMC_D0 */ + , /* FMC_D1 */ + , /* FMC_D2 */ + , /* FMC_D3 */ + , /* FMC_D4 */ + , /* FMC_D5 */ + , /* FMC_D6 */ + , /* FMC_D7 */ + , /* FMC_D8 */ + , /* FMC_D9 */ + , /* FMC_D10 */ + , /* FMC_D11 */ + , /* FMC_D12 */ + , /* FMC_D13 */ + , /* FMC_D14 */ + , /* FMC_D15 */ + , /* FMC_NE2_FMC_NCE */ + ; /* FMC_NE4 */ + }; + }; + i2c1_pins_a: i2c1-0 { pins { pinmux = , /* I2C1_SCL */ From b5269b6664515b4de6fd06e22ca9773530c6fc57 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Thu, 8 Oct 2020 21:38:00 +0200 Subject: [PATCH 341/799] ARM: dts: stm32: Add KS8851 on FMC2 to STM32MP1 DHCOM Add bindings for the KS8851 ethernet present on the STM32MP1 DHCOM SoM. Signed-off-by: Marek Vasut Cc: Alexandre Torgue Cc: Maxime Coquelin Cc: Patrice Chotard Cc: Patrick Delaunay Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi | 35 ++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi b/arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi index e257459c34dc..ac46ab363e1b 100644 --- a/arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi +++ b/arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi @@ -11,6 +11,7 @@ / { aliases { ethernet0 = ðernet0; + ethernet1 = &ksz8851; }; memory@c0000000 { @@ -133,6 +134,40 @@ }; }; +&fmc { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&fmc_pins_b>; + pinctrl-1 = <&fmc_sleep_pins_b>; + status = "okay"; + + ksz8851: ks8851mll@1,0 { + compatible = "micrel,ks8851-mll"; + reg = <1 0x0 0x2>, <1 0x2 0x20000>; + interrupt-parent = <&gpioc>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + bank-width = <2>; + + /* Timing values are in nS */ + st,fmc2-ebi-cs-mux-enable; + st,fmc2-ebi-cs-transaction-type = <4>; + st,fmc2-ebi-cs-buswidth = <16>; + st,fmc2-ebi-cs-address-setup-ns = <5>; + st,fmc2-ebi-cs-address-hold-ns = <5>; + st,fmc2-ebi-cs-bus-turnaround-ns = <5>; + st,fmc2-ebi-cs-data-setup-ns = <45>; + st,fmc2-ebi-cs-data-hold-ns = <1>; + st,fmc2-ebi-cs-write-address-setup-ns = <5>; + st,fmc2-ebi-cs-write-address-hold-ns = <5>; + st,fmc2-ebi-cs-write-bus-turnaround-ns = <5>; + st,fmc2-ebi-cs-write-data-setup-ns = <45>; + st,fmc2-ebi-cs-write-data-hold-ns = <1>; + }; +}; + +&gpioc { + status = "okay"; +}; + &i2c4 { pinctrl-names = "default"; pinctrl-0 = <&i2c4_pins_a>; From af03de2b9b908e776c233744b84ce9dbb70dcafb Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Fri, 13 Nov 2020 15:18:22 -0600 Subject: [PATCH 342/799] arm64: dts: ti: k3-am65*: Cleanup disabled nodes at SoC dtsi level The device tree standard states that when the status property is not present under a node, the okay value is assumed. There are many reasons for doing the same, the number of strings in the device tree, default power management functionality, etc. are a few of the reasons. In general, after a few rounds of discussions [1] there are few options one could take when dealing with SoC dtsi and board dts a. SoC dtsi provide nodes as a super-set default (aka enabled) state and to prevent messy board files, when more boards are added per SoC, we optimize and disable commonly un-used nodes in board-common.dtsi b. SoC dtsi disables all hardware dependent nodes by default and board dts files enable nodes based on a need basis. c. Subjectively pick and choose which nodes we will disable by default in SoC dtsi and over the years we can optimize things and change default state depending on the need. While there are pros and cons on each of these approaches, the right thing to do will be to stick with device tree default standards and work within those established rules. So, we choose to go with option (a). Lets cleanup defaults of am654 SoC dtsi before this gets more harder to cleanup later on and new SoCs are added. The dtb generated is identical with the patch and it is just cleanup to ensure we have a clean usage model NOTE: There is a known risk of omission that new board dts developers might miss reviewing both the board schematics in addition to all the DT nodes of the SoC when setting appropriate nodes status to disable or reserved in the board dts. This can expose issues in drivers that may not anticipate an incomplete node (example: missing appropriate board properties) being in an "okay" state. These cases are considered bugs and need to be fixed in the drivers as and when identified. [1] https://lore.kernel.org/linux-arm-kernel/20201027130701.GE5639@atomide.com/ Signed-off-by: Nishanth Menon Reviewed-by: Tomi Valkeinen Reviewed-by: Tony Lindgren Cc: Jyri Sarha Cc: Tomi Valkeinen Cc: Peter Ujfalusi Cc: Tony Lindgren Link: https://lore.kernel.org/r/20201113211826.13087-2-nm@ti.com --- arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 8 -------- arch/arm64/boot/dts/ti/k3-am654-base-board.dts | 16 ++++++++++++++++ 2 files changed, 16 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi index a664c91675de..c842b9803f2d 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi @@ -769,8 +769,6 @@ clocks = <&k3_clks 104 0>; clock-names = "fck"; power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>; - - status = "disabled"; }; mcasp1: mcasp@2b10000 { @@ -788,8 +786,6 @@ clocks = <&k3_clks 105 0>; clock-names = "fck"; power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>; - - status = "disabled"; }; mcasp2: mcasp@2b20000 { @@ -807,8 +803,6 @@ clocks = <&k3_clks 106 0>; clock-names = "fck"; power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>; - - status = "disabled"; }; cal: cal@6f03000 { @@ -864,8 +858,6 @@ interrupts = ; - status = "disabled"; - dma-coherent; dss_ports: ports { diff --git a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts index 17f3a85360e6..0dec781982b1 100644 --- a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts +++ b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts @@ -529,3 +529,19 @@ phy-mode = "rgmii-rxid"; phy-handle = <&phy0>; }; + +&mcasp0 { + status = "disabled"; +}; + +&mcasp1 { + status = "disabled"; +}; + +&mcasp2 { + status = "disabled"; +}; + +&dss { + status = "disabled"; +}; From 5d1bedf252db3ec2becb9f43c55e0f33af1fd7fc Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Fri, 13 Nov 2020 15:18:23 -0600 Subject: [PATCH 343/799] arm64: dts: ti: k3-j721e*: Cleanup disabled nodes at SoC dtsi level The device tree standard states that when the status property is not present under a node, the okay value is assumed. There are many reasons for doing the same, the number of strings in the device tree, default power management functionality, etc. are a few of the reasons. In general, after a few rounds of discussions [1] there are few options one could take when dealing with SoC dtsi and board dts a. SoC dtsi provide nodes as a super-set default (aka enabled) state and to prevent messy board files, when more boards are added per SoC, we optimize and disable commonly un-used nodes in board-common.dtsi b. SoC dtsi disables all hardware dependent nodes by default and board dts files enable nodes based on a need basis. c. Subjectively pick and choose which nodes we will disable by default in SoC dtsi and over the years we can optimize things and change default state depending on the need. While there are pros and cons on each of these approaches, the right thing to do will be to stick with device tree default standards and work within those established rules. So, we choose to go with option (a). Lets cleanup defaults of j721e SoC dtsi before this gets more harder to cleanup later on and new SoCs are added. The only functional difference between the dtb generated is status='okay' is no longer necessary for mcasp10 and depends on the default state. NOTE: There is a known risk of omission that new board dts developers might miss reviewing both the board schematics in addition to all the DT nodes of the SoC when setting appropriate nodes status to disable or reserved in the board dts. This can expose issues in drivers that may not anticipate an incomplete node (example: missing appropriate board properties) being in an "okay" state. These cases are considered bugs and need to be fixed in the drivers as and when identified. [1] https://lore.kernel.org/linux-arm-kernel/20201027130701.GE5639@atomide.com/ Signed-off-by: Nishanth Menon Reviewed-by: Tomi Valkeinen Reviewed-by: Tony Lindgren Cc: Jyri Sarha Cc: Tomi Valkeinen Cc: Peter Ujfalusi Cc: Tony Lindgren Link: https://lore.kernel.org/r/20201113211826.13087-3-nm@ti.com --- .../dts/ti/k3-j721e-common-proc-board.dts | 48 ++++++++++++++++++- arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 26 ---------- 2 files changed, 47 insertions(+), 27 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts index 52e121155563..9416528caa8a 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts @@ -540,6 +540,46 @@ <&k3_clks 152 18>; /* PLL23_HSDIV0 */ }; +&mcasp0 { + status = "disabled"; +}; + +&mcasp1 { + status = "disabled"; +}; + +&mcasp2 { + status = "disabled"; +}; + +&mcasp3 { + status = "disabled"; +}; + +&mcasp4 { + status = "disabled"; +}; + +&mcasp5 { + status = "disabled"; +}; + +&mcasp6 { + status = "disabled"; +}; + +&mcasp7 { + status = "disabled"; +}; + +&mcasp8 { + status = "disabled"; +}; + +&mcasp9 { + status = "disabled"; +}; + &mcasp10 { #sound-dai-cells = <0>; @@ -556,8 +596,10 @@ >; tx-num-evt = <0>; rx-num-evt = <0>; +}; - status = "okay"; +&mcasp11 { + status = "disabled"; }; &serdes0 { @@ -639,3 +681,7 @@ &pcie3_ep { status = "disabled"; }; + +&dss { + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi index 620e69e42974..137966c6be1f 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi @@ -1327,8 +1327,6 @@ "common_s1", "common_s2"; - status = "disabled"; - dss_ports: ports { #address-cells = <1>; #size-cells = <0>; @@ -1350,8 +1348,6 @@ clocks = <&k3_clks 174 1>; clock-names = "fck"; power-domains = <&k3_pds 174 TI_SCI_PD_EXCLUSIVE>; - - status = "disabled"; }; mcasp1: mcasp@2b10000 { @@ -1369,8 +1365,6 @@ clocks = <&k3_clks 175 1>; clock-names = "fck"; power-domains = <&k3_pds 175 TI_SCI_PD_EXCLUSIVE>; - - status = "disabled"; }; mcasp2: mcasp@2b20000 { @@ -1388,8 +1382,6 @@ clocks = <&k3_clks 176 1>; clock-names = "fck"; power-domains = <&k3_pds 176 TI_SCI_PD_EXCLUSIVE>; - - status = "disabled"; }; mcasp3: mcasp@2b30000 { @@ -1407,8 +1399,6 @@ clocks = <&k3_clks 177 1>; clock-names = "fck"; power-domains = <&k3_pds 177 TI_SCI_PD_EXCLUSIVE>; - - status = "disabled"; }; mcasp4: mcasp@2b40000 { @@ -1426,8 +1416,6 @@ clocks = <&k3_clks 178 1>; clock-names = "fck"; power-domains = <&k3_pds 178 TI_SCI_PD_EXCLUSIVE>; - - status = "disabled"; }; mcasp5: mcasp@2b50000 { @@ -1445,8 +1433,6 @@ clocks = <&k3_clks 179 1>; clock-names = "fck"; power-domains = <&k3_pds 179 TI_SCI_PD_EXCLUSIVE>; - - status = "disabled"; }; mcasp6: mcasp@2b60000 { @@ -1464,8 +1450,6 @@ clocks = <&k3_clks 180 1>; clock-names = "fck"; power-domains = <&k3_pds 180 TI_SCI_PD_EXCLUSIVE>; - - status = "disabled"; }; mcasp7: mcasp@2b70000 { @@ -1483,8 +1467,6 @@ clocks = <&k3_clks 181 1>; clock-names = "fck"; power-domains = <&k3_pds 181 TI_SCI_PD_EXCLUSIVE>; - - status = "disabled"; }; mcasp8: mcasp@2b80000 { @@ -1502,8 +1484,6 @@ clocks = <&k3_clks 182 1>; clock-names = "fck"; power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>; - - status = "disabled"; }; mcasp9: mcasp@2b90000 { @@ -1521,8 +1501,6 @@ clocks = <&k3_clks 183 1>; clock-names = "fck"; power-domains = <&k3_pds 183 TI_SCI_PD_EXCLUSIVE>; - - status = "disabled"; }; mcasp10: mcasp@2ba0000 { @@ -1540,8 +1518,6 @@ clocks = <&k3_clks 184 1>; clock-names = "fck"; power-domains = <&k3_pds 184 TI_SCI_PD_EXCLUSIVE>; - - status = "disabled"; }; mcasp11: mcasp@2bb0000 { @@ -1559,8 +1535,6 @@ clocks = <&k3_clks 185 1>; clock-names = "fck"; power-domains = <&k3_pds 185 TI_SCI_PD_EXCLUSIVE>; - - status = "disabled"; }; watchdog0: watchdog@2200000 { From bfbf9be725d8effdbb60eb2ece44c06ae87a54de Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Fri, 13 Nov 2020 15:18:24 -0600 Subject: [PATCH 344/799] arm64: dts: ti: am65/j721e: Fix up un-necessary status set to "okay" for crypto The default state of a device tree node is "okay". There is no specific use of explicitly adding status = "okay" in the SoC dtsi. Signed-off-by: Nishanth Menon Reviewed-by: Tony Lindgren Reviewed-by: Keerthy Acked-by: Tero Kristo Cc: Keerthy Link: https://lore.kernel.org/r/20201113211826.13087-4-nm@ti.com --- arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 1 - arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 2 -- 2 files changed, 3 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi index c842b9803f2d..116818912ba2 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi @@ -119,7 +119,6 @@ #address-cells = <2>; #size-cells = <2>; ranges = <0x0 0x04e00000 0x00 0x04e00000 0x0 0x30000>; - status = "okay"; dmas = <&main_udmap 0xc000>, <&main_udmap 0x4000>, <&main_udmap 0x4001>; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi index 137966c6be1f..19e602afdb05 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi @@ -345,8 +345,6 @@ #size-cells = <2>; ranges = <0x0 0x04e00000 0x00 0x04e00000 0x0 0x30000>; - status = "okay"; - dmas = <&main_udmap 0xc000>, <&main_udmap 0x4000>, <&main_udmap 0x4001>; dma-names = "tx", "rx1", "rx2"; From 90e6c38848f8e86047e0e758c0725b155e2e349b Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Fri, 13 Nov 2020 15:18:25 -0600 Subject: [PATCH 345/799] arm64: dts: ti: k3-am654-base-board: Fix up un-necessary status set to "okay" for USB The default state of a device tree node is "okay". There is no specific use of explicitly adding status = "okay" in the board dts. Signed-off-by: Nishanth Menon Reviewed-by: Tony Lindgren Acked-by: Roger Quadros Cc: Roger Quadros Link: https://lore.kernel.org/r/20201113211826.13087-5-nm@ti.com --- arch/arm64/boot/dts/ti/k3-am654-base-board.dts | 8 -------- 1 file changed, 8 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts index 0dec781982b1..c8c9aa98b561 100644 --- a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts +++ b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts @@ -356,14 +356,6 @@ disable-wp; }; -&dwc3_1 { - status = "okay"; -}; - -&usb1_phy { - status = "okay"; -}; - &usb1 { pinctrl-names = "default"; pinctrl-0 = <&usb1_pins_default>; From 4cc34aa8a208665aa0362a615deefc3db6a5d7bd Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Fri, 13 Nov 2020 15:18:26 -0600 Subject: [PATCH 346/799] arm64: dts: ti: am65/j721e/j7200: Mark firmware used uart as "reserved" Follow the device tree standards that states to set the status="reserved" if an device is operational, but used by a non-linux firmware in the system. Signed-off-by: Nishanth Menon Reviewed-by: Tony Lindgren Acked-by: Vignesh Raghavendra Link: https://lore.kernel.org/r/20201113211826.13087-6-nm@ti.com --- arch/arm64/boot/dts/ti/k3-am654-base-board.dts | 2 +- arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts | 4 ++-- arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts | 2 +- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts index c8c9aa98b561..fe3043943906 100644 --- a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts +++ b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts @@ -242,7 +242,7 @@ &wkup_uart0 { /* Wakeup UART is used by System firmware */ - status = "disabled"; + status = "reserved"; }; &main_uart0 { diff --git a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts index 7d2ff1c3b50f..96fa26365248 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts @@ -79,7 +79,7 @@ &wkup_uart0 { /* Wakeup UART is used by System firmware */ - status = "disabled"; + status = "reserved"; }; &main_uart0 { @@ -89,7 +89,7 @@ &main_uart2 { /* MAIN UART 2 is used by R5F firmware */ - status = "disabled"; + status = "reserved"; }; &main_uart3 { diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts index 9416528caa8a..5754892f8501 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts @@ -221,7 +221,7 @@ &wkup_uart0 { /* Wakeup UART is used by System firmware */ - status = "disabled"; + status = "reserved"; }; &main_uart0 { From 1d7a01c40840d844fb5d353c151f0ee0a7680c2f Mon Sep 17 00:00:00 2001 From: Suman Anna Date: Mon, 26 Oct 2020 18:26:35 -0500 Subject: [PATCH 347/799] arm64: dts: ti: k3-j7200-main: Add hwspinlock node The Main NavSS block on J7200 SoCs contains a HwSpinlock IP instance that is same as the IP on AM65x and J721E SoCs. Add the DT node for this on J7200 SoCs. The node is present within the Main NavSS block, and is added as a child node under the main_navss interconnect node. Signed-off-by: Suman Anna Signed-off-by: Nishanth Menon Reviewed-by: Praneeth Bajjuri Link: https://lore.kernel.org/r/20201026232637.15681-2-s-anna@ti.com --- arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi index 72d6496e88dd..4c53a3036066 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi @@ -115,6 +115,12 @@ interrupts = ; }; + hwspinlock: spinlock@30e00000 { + compatible = "ti,am654-hwspinlock"; + reg = <0x00 0x30e00000 0x00 0x1000>; + #hwlock-cells = <1>; + }; + main_ringacc: ringacc@3c000000 { compatible = "ti,am654-navss-ringacc"; reg = <0x00 0x3c000000 0x00 0x400000>, From d15d1cfbd765b4b2a113b6025e8edc7db4a7800a Mon Sep 17 00:00:00 2001 From: Suman Anna Date: Mon, 26 Oct 2020 18:26:36 -0500 Subject: [PATCH 348/799] arm64: dts: ti: k3-j7200-main: Add mailbox cluster nodes The J7200 Main NavSS block contains a Mailbox IP instance with multiple clusters, and follows the same integration style as on J721E SoCs. Add all the Mailbox clusters as their own nodes under the MAIN NavSS interconnect node instead of creating an almost empty parent node for the new K3 mailbox IP and the clusters as its child nodes. All these nodes are enabled by default in the base dtsi file, but any cluster that does not define any child sub-mailbox nodes should be disabled in the corresponding board dts files. NOTE: The NavSS only has a limited number of interrupts, so none of the interrupts generated by a Mailbox IP are added by default. Only the needed interrupts that are targeted towards the A72 GIC will have to be added later on in the board dts files alongside the corresponding sub-mailbox child nodes. Signed-off-by: Suman Anna Signed-off-by: Nishanth Menon Reviewed-by: Praneeth Bajjuri Link: https://lore.kernel.org/r/20201026232637.15681-3-s-anna@ti.com --- arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 108 ++++++++++++++++++++++ 1 file changed, 108 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi index 4c53a3036066..b0094212aa82 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi @@ -121,6 +121,114 @@ #hwlock-cells = <1>; }; + mailbox0_cluster0: mailbox@31f80000 { + compatible = "ti,am654-mailbox"; + reg = <0x00 0x31f80000 0x00 0x200>; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <16>; + interrupt-parent = <&main_navss_intr>; + }; + + mailbox0_cluster1: mailbox@31f81000 { + compatible = "ti,am654-mailbox"; + reg = <0x00 0x31f81000 0x00 0x200>; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <16>; + interrupt-parent = <&main_navss_intr>; + }; + + mailbox0_cluster2: mailbox@31f82000 { + compatible = "ti,am654-mailbox"; + reg = <0x00 0x31f82000 0x00 0x200>; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <16>; + interrupt-parent = <&main_navss_intr>; + }; + + mailbox0_cluster3: mailbox@31f83000 { + compatible = "ti,am654-mailbox"; + reg = <0x00 0x31f83000 0x00 0x200>; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <16>; + interrupt-parent = <&main_navss_intr>; + }; + + mailbox0_cluster4: mailbox@31f84000 { + compatible = "ti,am654-mailbox"; + reg = <0x00 0x31f84000 0x00 0x200>; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <16>; + interrupt-parent = <&main_navss_intr>; + }; + + mailbox0_cluster5: mailbox@31f85000 { + compatible = "ti,am654-mailbox"; + reg = <0x00 0x31f85000 0x00 0x200>; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <16>; + interrupt-parent = <&main_navss_intr>; + }; + + mailbox0_cluster6: mailbox@31f86000 { + compatible = "ti,am654-mailbox"; + reg = <0x00 0x31f86000 0x00 0x200>; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <16>; + interrupt-parent = <&main_navss_intr>; + }; + + mailbox0_cluster7: mailbox@31f87000 { + compatible = "ti,am654-mailbox"; + reg = <0x00 0x31f87000 0x00 0x200>; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <16>; + interrupt-parent = <&main_navss_intr>; + }; + + mailbox0_cluster8: mailbox@31f88000 { + compatible = "ti,am654-mailbox"; + reg = <0x00 0x31f88000 0x00 0x200>; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <16>; + interrupt-parent = <&main_navss_intr>; + }; + + mailbox0_cluster9: mailbox@31f89000 { + compatible = "ti,am654-mailbox"; + reg = <0x00 0x31f89000 0x00 0x200>; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <16>; + interrupt-parent = <&main_navss_intr>; + }; + + mailbox0_cluster10: mailbox@31f8a000 { + compatible = "ti,am654-mailbox"; + reg = <0x00 0x31f8a000 0x00 0x200>; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <16>; + interrupt-parent = <&main_navss_intr>; + }; + + mailbox0_cluster11: mailbox@31f8b000 { + compatible = "ti,am654-mailbox"; + reg = <0x00 0x31f8b000 0x00 0x200>; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <16>; + interrupt-parent = <&main_navss_intr>; + }; + main_ringacc: ringacc@3c000000 { compatible = "ti,am654-navss-ringacc"; reg = <0x00 0x3c000000 0x00 0x400000>, From 6804a987de733c805675973e3afde128fe7a7cfa Mon Sep 17 00:00:00 2001 From: Suman Anna Date: Mon, 26 Oct 2020 18:26:37 -0500 Subject: [PATCH 349/799] arm64: dts: ti: k3-j7200-som-p0: Add IPC sub-mailbox nodes Add the sub-mailbox nodes that are used to communicate between MPU and various remote processors present in the J7200 SoCs to the J7200 common processor board. These include the R5F remote processors in the dual-R5F clusters in the MCU domain (MCU_R5FSS0) and the MAIN domain (MAIN_R5FSS0). These sub-mailbox nodes utilize the System Mailbox clusters 0 and 1. All the remaining mailbox clusters are currently not used on A72 core, and so are disabled. The nodes are added in the k3-j7200-som-p0.dtsi file to co-locate these alongside future reserved-memory nodes required for remoteprocs. The sub-mailbox nodes added match the hard-coded mailbox configuration used within the TI RTOS IPC software packages. A sub-mailbox node is added for each of the R5F cores to accommodate the R5F processor sub-systems running in Split mode. Only the sub-mailbox node for the first R5F core in each cluster is used in case of Lockstep mode for that R5F cluster. NOTE: The GIC_SPI interrupts to be used are dynamically allocated and managed by the System Firmware through the ti-sci-intr irqchip driver. So, only valid interrupts that are used by the sub-mailbox devices (each cluster's User 0 IRQ output) are enabled. This is done to minimize the number of NavSS Interrupt Router outputs utilized. Signed-off-by: Suman Anna Signed-off-by: Nishanth Menon Reviewed-by: Praneeth Bajjuri Link: https://lore.kernel.org/r/20201026232637.15681-4-s-anna@ti.com --- arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi | 68 +++++++++++++++++++++ 1 file changed, 68 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi index 6a98ba499bc2..fbd17d38f6b6 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi @@ -63,3 +63,71 @@ reg = <0x00 0x00 0x4000000>; }; }; + +&mailbox0_cluster0 { + interrupts = <436>; + + mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; + + mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 { + ti,mbox-rx = <2 0 0>; + ti,mbox-tx = <3 0 0>; + }; +}; + +&mailbox0_cluster1 { + interrupts = <432>; + + mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; + + mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { + ti,mbox-rx = <2 0 0>; + ti,mbox-tx = <3 0 0>; + }; +}; + +&mailbox0_cluster2 { + status = "disabled"; +}; + +&mailbox0_cluster3 { + status = "disabled"; +}; + +&mailbox0_cluster4 { + status = "disabled"; +}; + +&mailbox0_cluster5 { + status = "disabled"; +}; + +&mailbox0_cluster6 { + status = "disabled"; +}; + +&mailbox0_cluster7 { + status = "disabled"; +}; + +&mailbox0_cluster8 { + status = "disabled"; +}; + +&mailbox0_cluster9 { + status = "disabled"; +}; + +&mailbox0_cluster10 { + status = "disabled"; +}; + +&mailbox0_cluster11 { + status = "disabled"; +}; From fd6a1e60a0496be1c903a7fd47482c67cdd5ccd7 Mon Sep 17 00:00:00 2001 From: Eddie James Date: Wed, 28 Oct 2020 13:56:47 -0500 Subject: [PATCH 350/799] ARM: dts: aspeed: rainier: Add 4U device-tree Add a device-tree for the Rainier 4U system. Change the model name on the existing Rainier device-tree to 2U, and remove the two extra power supplies that are only present on the 4U system. Also add labels to the fan nodes for use in the 4U device-tree. Signed-off-by: Eddie James Reviewed-by: Andrew Jeffery Link: https://lore.kernel.org/r/20201028185647.14565-1-eajames@linux.ibm.com Signed-off-by: Joel Stanley --- arch/arm/boot/dts/Makefile | 1 + .../boot/dts/aspeed-bmc-ibm-rainier-4u.dts | 37 +++++++++++++++++++ arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts | 20 +++------- 3 files changed, 43 insertions(+), 15 deletions(-) create mode 100644 arch/arm/boot/dts/aspeed-bmc-ibm-rainier-4u.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 1917cd47204a..ec35977193f1 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1392,6 +1392,7 @@ dtb-$(CONFIG_ARCH_ASPEED) += \ aspeed-bmc-facebook-yamp.dtb \ aspeed-bmc-facebook-yosemitev2.dtb \ aspeed-bmc-ibm-rainier.dtb \ + aspeed-bmc-ibm-rainier-4u.dtb \ aspeed-bmc-intel-s2600wf.dtb \ aspeed-bmc-inspur-fp5280g2.dtb \ aspeed-bmc-lenovo-hr630.dtb \ diff --git a/arch/arm/boot/dts/aspeed-bmc-ibm-rainier-4u.dts b/arch/arm/boot/dts/aspeed-bmc-ibm-rainier-4u.dts new file mode 100644 index 000000000000..291f7d6c9979 --- /dev/null +++ b/arch/arm/boot/dts/aspeed-bmc-ibm-rainier-4u.dts @@ -0,0 +1,37 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +// Copyright 2020 IBM Corp. +/dts-v1/; + +#include "aspeed-bmc-ibm-rainier.dts" + +/ { + model = "Rainier 4U"; +}; + +&i2c3 { + power-supply@6a { + compatible = "ibm,cffps"; + reg = <0x6a>; + }; + + power-supply@6b { + compatible = "ibm,cffps"; + reg = <0x6b>; + }; +}; + +&fan0 { + tach-pulses = <4>; +}; + +&fan1 { + tach-pulses = <4>; +}; + +&fan2 { + tach-pulses = <4>; +}; + +&fan3 { + tach-pulses = <4>; +}; diff --git a/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts b/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts index 21ae880c7530..ac649fde802e 100644 --- a/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts +++ b/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts @@ -8,7 +8,7 @@ #include / { - model = "Rainier"; + model = "Rainier 2U"; compatible = "ibm,rainier-bmc", "aspeed,ast2600"; aliases { @@ -594,16 +594,6 @@ compatible = "ibm,cffps"; reg = <0x69>; }; - - power-supply@6a { - compatible = "ibm,cffps"; - reg = <0x6a>; - }; - - power-supply@6b { - compatible = "ibm,cffps"; - reg = <0x6b>; - }; }; &i2c4 { @@ -723,25 +713,25 @@ #address-cells = <1>; #size-cells = <0>; - fan@0 { + fan0: fan@0 { compatible = "pmbus-fan"; reg = <0>; tach-pulses = <2>; }; - fan@1 { + fan1: fan@1 { compatible = "pmbus-fan"; reg = <1>; tach-pulses = <2>; }; - fan@2 { + fan2: fan@2 { compatible = "pmbus-fan"; reg = <2>; tach-pulses = <2>; }; - fan@3 { + fan3: fan@3 { compatible = "pmbus-fan"; reg = <3>; tach-pulses = <2>; From e73840f316cbf9df00893c0ef9f734196087403d Mon Sep 17 00:00:00 2001 From: Jonathan Cameron Date: Sun, 15 Nov 2020 19:29:46 +0000 Subject: [PATCH 351/799] ARM: dts: exynos: Drop incorrect use of io-channel-ranges This property is only relevant to consumers of io-channels, not providers. All these dtsi files have it alongside #io-channel-cells which indicates they are providers of io-channels, not consumers. Note that dt-schema will now flag this up due to a dependency between this property and io-channels. Signed-off-by: Jonathan Cameron Link: https://lore.kernel.org/r/20201115192951.1073632-5-jic23@kernel.org Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos3250.dtsi | 1 - arch/arm/boot/dts/exynos4412.dtsi | 1 - arch/arm/boot/dts/exynos5250.dtsi | 1 - arch/arm/boot/dts/exynos54xx.dtsi | 1 - 4 files changed, 4 deletions(-) diff --git a/arch/arm/boot/dts/exynos3250.dtsi b/arch/arm/boot/dts/exynos3250.dtsi index c5390ca5a87d..77ab7193b903 100644 --- a/arch/arm/boot/dts/exynos3250.dtsi +++ b/arch/arm/boot/dts/exynos3250.dtsi @@ -439,7 +439,6 @@ clock-names = "adc", "sclk"; clocks = <&cmu CLK_TSADC>, <&cmu CLK_SCLK_TSADC>; #io-channel-cells = <1>; - io-channel-ranges; samsung,syscon-phandle = <&pmu_system_controller>; status = "disabled"; }; diff --git a/arch/arm/boot/dts/exynos4412.dtsi b/arch/arm/boot/dts/exynos4412.dtsi index 96a4b01bd71b..a142fe84010b 100644 --- a/arch/arm/boot/dts/exynos4412.dtsi +++ b/arch/arm/boot/dts/exynos4412.dtsi @@ -274,7 +274,6 @@ clocks = <&clock CLK_TSADC>; clock-names = "adc"; #io-channel-cells = <1>; - io-channel-ranges; samsung,syscon-phandle = <&pmu_system_controller>; status = "disabled"; }; diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi index 1be1841c374f..2ea2caaca4e2 100644 --- a/arch/arm/boot/dts/exynos5250.dtsi +++ b/arch/arm/boot/dts/exynos5250.dtsi @@ -844,7 +844,6 @@ clocks = <&clock CLK_ADC>; clock-names = "adc"; #io-channel-cells = <1>; - io-channel-ranges; samsung,syscon-phandle = <&pmu_system_controller>; status = "disabled"; }; diff --git a/arch/arm/boot/dts/exynos54xx.dtsi b/arch/arm/boot/dts/exynos54xx.dtsi index 339243d19a80..fe9d34c23374 100644 --- a/arch/arm/boot/dts/exynos54xx.dtsi +++ b/arch/arm/boot/dts/exynos54xx.dtsi @@ -101,7 +101,6 @@ reg = <0x12d10000 0x100>; interrupts = ; #io-channel-cells = <1>; - io-channel-ranges; status = "disabled"; }; From 43379417e31cadc7afba5ca549eaa1043f089ce5 Mon Sep 17 00:00:00 2001 From: Jonathan Cameron Date: Sun, 15 Nov 2020 19:29:47 +0000 Subject: [PATCH 352/799] ARM: dts: s5pv210: Drop incorrect use of io-channel-ranges property This property is relevant to consumers of io-channels. Here it is used by a provider. dt-schema will now report and error as this property must be in the same node as io-channels and it is not here. Signed-off-by: Jonathan Cameron Link: https://lore.kernel.org/r/20201115192951.1073632-6-jic23@kernel.org Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/s5pv210.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm/boot/dts/s5pv210.dtsi b/arch/arm/boot/dts/s5pv210.dtsi index 2871351ab907..353ba7b09a0c 100644 --- a/arch/arm/boot/dts/s5pv210.dtsi +++ b/arch/arm/boot/dts/s5pv210.dtsi @@ -149,7 +149,6 @@ clocks = <&clocks CLK_TSADC>; clock-names = "adc"; #io-channel-cells = <1>; - io-channel-ranges; status = "disabled"; }; From 0f8159371c225a7b019b612a5c101e8b839c6c46 Mon Sep 17 00:00:00 2001 From: Jonathan Cameron Date: Sun, 15 Nov 2020 19:29:49 +0000 Subject: [PATCH 353/799] ARM: dts: s5pv210: Drop unneeded io-channel-ranges property in Aries This property is only useful if a node has children as it allows them to then use io-channel properties in the parent. Here there are no children. This is harmless, but we are planning to shortly drop this property as it is rarely used correctly and there is little reason it would ever be needed as we can just provide the io-channels property to any child nodes that need it. Signed-off-by: Jonathan Cameron Link: https://lore.kernel.org/r/20201115192951.1073632-8-jic23@kernel.org Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/s5pv210-aries.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm/boot/dts/s5pv210-aries.dtsi b/arch/arm/boot/dts/s5pv210-aries.dtsi index 91ecad85abfc..97cb7ff2f75f 100644 --- a/arch/arm/boot/dts/s5pv210-aries.dtsi +++ b/arch/arm/boot/dts/s5pv210-aries.dtsi @@ -589,7 +589,6 @@ io-channels = <&adc 9>; shunt-resistor-micro-ohms = <47000000>; /* 47 ohms */ #io-channel-cells = <0>; - io-channel-ranges; }; }; From f74e93032df229a8358617e586ba89f744d5dbcd Mon Sep 17 00:00:00 2001 From: Jonathan Cameron Date: Sun, 15 Nov 2020 19:29:50 +0000 Subject: [PATCH 354/799] arm64: dts: exynos: Drop incorrect use of io-channel-ranges property This property is for consumers of io-channels. Here it is used in providers of those channels. Note dt-schema will currently flag this as an error due to a dependency between this property and io-channels. Signed-off-by: Jonathan Cameron Link: https://lore.kernel.org/r/20201115192951.1073632-9-jic23@kernel.org Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/exynos/exynos5433.dtsi | 1 - arch/arm64/boot/dts/exynos/exynos7.dtsi | 1 - 2 files changed, 2 deletions(-) diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi index dae44be09a09..6433f9ee35e1 100644 --- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi @@ -1450,7 +1450,6 @@ clock-names = "adc"; clocks = <&cmu_peric CLK_PCLK_ADCIF>; #io-channel-cells = <1>; - io-channel-ranges; status = "disabled"; }; diff --git a/arch/arm64/boot/dts/exynos/exynos7.dtsi b/arch/arm64/boot/dts/exynos/exynos7.dtsi index 661f9c1027e8..10244e59d56d 100644 --- a/arch/arm64/boot/dts/exynos/exynos7.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos7.dtsi @@ -562,7 +562,6 @@ clocks = <&clock_peric0 PCLK_ADCIF>; clock-names = "adc"; #io-channel-cells = <1>; - io-channel-ranges; status = "disabled"; }; From 35552c7cb672d2cfd6c4aa2e28b15fdd12315555 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Wed, 18 Nov 2020 11:51:11 +0100 Subject: [PATCH 355/799] arm64: defconfig: Enable Tegra234 support Support for Tegra234 was merged in v5.10-rc1, so we might as well enable it by default. Signed-off-by: Thierry Reding --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 17a2df6a263e..45bbdf00d9e6 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -958,6 +958,7 @@ CONFIG_ARCH_TEGRA_132_SOC=y CONFIG_ARCH_TEGRA_210_SOC=y CONFIG_ARCH_TEGRA_186_SOC=y CONFIG_ARCH_TEGRA_194_SOC=y +CONFIG_ARCH_TEGRA_234_SOC=y CONFIG_ARCH_K3_AM6_SOC=y CONFIG_ARCH_K3_J721E_SOC=y CONFIG_TI_SCI_PM_DOMAINS=y From cbee028da69d31cb927142e2828710de55a49f2a Mon Sep 17 00:00:00 2001 From: Andrew Jeffery Date: Thu, 22 Oct 2020 12:17:26 +1030 Subject: [PATCH 356/799] ARM: dts: tacoma: Fix node vs reg mismatch for flash memory The mismatch lead to a miscalculation of regions in another patch, and shouldn't be mismatched anyway, so make them consistent. Fixes: 575640201e66 ("ARM: dts: aspeed: tacoma: Use 64MB for firmware memory") Signed-off-by: Andrew Jeffery Reviewed-by: Joel Stanley Link: https://lore.kernel.org/r/20201022014731.2035438-2-andrew@aj.id.au Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts b/arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts index 4d070d6ba09f..e86c22ce6d12 100644 --- a/arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts +++ b/arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts @@ -26,7 +26,7 @@ #size-cells = <1>; ranges; - flash_memory: region@ba000000 { + flash_memory: region@b8000000 { no-map; reg = <0xb8000000 0x4000000>; /* 64M */ }; From c7b74131c755bb73eb836bcb46fcc28fbab39717 Mon Sep 17 00:00:00 2001 From: Andrew Jeffery Date: Thu, 22 Oct 2020 12:17:30 +1030 Subject: [PATCH 357/799] ARM: dts: rainier: Add reserved memory for ramoops Reserve a 1.5MiB region of memory to record kmsg dumps, console and userspace message state into 16kiB ring-buffer slots. The sizing allows for up to 16 dumps to be captured and read out. Set max-reason to KMSG_DUMP_EMERG to capture bad-path reboots. Signed-off-by: Andrew Jeffery Reviewed-by: Joel Stanley Link: https://lore.kernel.org/r/20201022014731.2035438-6-andrew@aj.id.au Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts b/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts index ac649fde802e..63123bf137e3 100644 --- a/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts +++ b/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts @@ -52,6 +52,15 @@ reg = <0xB8000000 0x04000000>; /* 64M */ }; + ramoops@bc000000 { + compatible = "ramoops"; + reg = <0xbc000000 0x180000>; /* 16 * (3 * 0x8000) */ + record-size = <0x8000>; + console-size = <0x8000>; + pmsg-size = <0x8000>; + max-reason = <3>; /* KMSG_DUMP_EMERG */ + }; + vga_memory: region@bf000000 { no-map; compatible = "shared-dma-pool"; From c1fc133f5bd06949037192c0a48c3dab85a140fd Mon Sep 17 00:00:00 2001 From: Andrew Jeffery Date: Thu, 22 Oct 2020 12:17:31 +1030 Subject: [PATCH 358/799] ARM: dts: tacoma: Add reserved memory for ramoops Reserve a 1.5MiB region of memory to record kmsg dumps, console and userspace message state into 16kiB ring-buffer slots. The sizing allows for up to 16 dumps to be captured and read out. Set max-reason to KMSG_DUMP_EMERG to capture bad-path reboots. Signed-off-by: Andrew Jeffery Reviewed-by: Joel Stanley Link: https://lore.kernel.org/r/20201022014731.2035438-7-andrew@aj.id.au Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts b/arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts index e86c22ce6d12..c1478d2db602 100644 --- a/arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts +++ b/arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts @@ -31,6 +31,15 @@ reg = <0xb8000000 0x4000000>; /* 64M */ }; + ramoops@bc000000 { + compatible = "ramoops"; + reg = <0xbc000000 0x180000>; /* 16 * (3 * 0x8000) */ + record-size = <0x8000>; + console-size = <0x8000>; + pmsg-size = <0x8000>; + max-reason = <3>; /* KMSG_DUMP_EMERG */ + }; + vga_memory: region@bf000000 { no-map; compatible = "shared-dma-pool"; From 136b2124d7cbc03a3b8fb88336f6bc1ba75b412f Mon Sep 17 00:00:00 2001 From: Tomer Maimon Date: Wed, 18 Nov 2020 12:03:58 +0200 Subject: [PATCH 359/799] ARM: dts: nuvoton: Add Nuvoton NPCM730 device tree The Nuvoton NPCN730 SoC is a part of the Nuvoton NPCM7xx SoCs family. Signed-off-by: Tomer Maimon Signed-off-by: Joel Stanley --- arch/arm/boot/dts/nuvoton-npcm730.dtsi | 44 ++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) create mode 100644 arch/arm/boot/dts/nuvoton-npcm730.dtsi diff --git a/arch/arm/boot/dts/nuvoton-npcm730.dtsi b/arch/arm/boot/dts/nuvoton-npcm730.dtsi new file mode 100644 index 000000000000..86ec12ec2b50 --- /dev/null +++ b/arch/arm/boot/dts/nuvoton-npcm730.dtsi @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (c) 2020 Nuvoton Technology + +#include "nuvoton-common-npcm7xx.dtsi" + +/ { + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&gic>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + enable-method = "nuvoton,npcm750-smp"; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + clocks = <&clk NPCM7XX_CLK_CPU>; + clock-names = "clk_cpu"; + reg = <0>; + next-level-cache = <&l2>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + clocks = <&clk NPCM7XX_CLK_CPU>; + clock-names = "clk_cpu"; + reg = <1>; + next-level-cache = <&l2>; + }; + }; + + soc { + timer@3fe600 { + compatible = "arm,cortex-a9-twd-timer"; + reg = <0x3fe600 0x20>; + interrupts = ; + clocks = <&clk NPCM7XX_CLK_AHB>; + }; + }; +}; From c2a983a7a8861e4d6bfd923ea84c919fd9d5261c Mon Sep 17 00:00:00 2001 From: Fran Hsu Date: Fri, 31 May 2019 21:24:38 +0800 Subject: [PATCH 360/799] ARM: dts: nuvoton: Add Quanta GSJ BMC pinctrl Add pinctrl definition for the Quanta GSJ BMC machine. Signed-off-by: Fran Hsu Reviewed-by: Benjamin Fair Signed-off-by: Joel Stanley --- .../boot/dts/nuvoton-npcm730-gsj-gpio.dtsi | 477 ++++++++++++++++++ 1 file changed, 477 insertions(+) create mode 100644 arch/arm/boot/dts/nuvoton-npcm730-gsj-gpio.dtsi diff --git a/arch/arm/boot/dts/nuvoton-npcm730-gsj-gpio.dtsi b/arch/arm/boot/dts/nuvoton-npcm730-gsj-gpio.dtsi new file mode 100644 index 000000000000..53cfd15fa03f --- /dev/null +++ b/arch/arm/boot/dts/nuvoton-npcm730-gsj-gpio.dtsi @@ -0,0 +1,477 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (c) 2018 Nuvoton Technology tomer.maimon@nuvoton.com + +/ { + pinctrl: pinctrl@f0800000 { + gpio0pp_pins: gpio0pp-pins { + pins = "GPIO0/IOX1DI"; + bias-disable; + drive-push-pull; + }; + gpio1pp_pins: gpio1pp-pins { + pins = "GPIO1/IOX1LD"; + bias-disable; + drive-push-pull; + }; + gpio2pp_pins: gpio2pp-pins { + pins = "GPIO2/IOX1CK"; + bias-disable; + drive-push-pull; + }; + gpio3pp_pins: gpio3pp-pins { + pins = "GPIO3/IOX1D0"; + bias-disable; + drive-push-pull; + }; + gpio4pp_pins: gpio4pp-pins { + pins = "GPIO4/IOX2DI/SMB1DSDA"; + bias-disable; + drive-push-pull; + }; + gpio5pp_pins: gpio5pp-pins { + pins = "GPIO5/IOX2LD/SMB1DSCL"; + bias-disable; + drive-push-pull; + }; + gpio6pp_pins: gpio6pp-pins { + pins = "GPIO6/IOX2CK/SMB2DSDA"; + bias-disable; + drive-push-pull; + }; + gpio7pp_pins: gpio7pp-pins { + pins = "GPIO7/IOX2D0/SMB2DSCL"; + bias-disable; + drive-push-pull; + }; + gpio8_pins: gpio8-pins { + pins = "GPIO8/LKGPO1"; + bias-disable; + input-enable; + }; + gpio9_pins: gpio9-pins { + pins = "GPIO9/LKGPO2"; + bias-disable; + input-enable; + }; + gpio10pp_pins: gpio10pp-pins { + pins = "GPIO10/IOXHLD"; + bias-disable; + drive-push-pull; + }; + gpio11pp_pins: gpio11pp-pins { + pins = "GPIO11/IOXHCK"; + bias-disable; + drive-push-pull; + }; + gpio12_pins: gpio12-pins { + pins = "GPIO12/GSPICK/SMB5BSCL"; + bias-disable; + input-enable; + }; + gpio13_pins: gpio13-pins { + pins = "GPIO13/GSPIDO/SMB5BSDA"; + bias-disable; + input-enable; + }; + gpio14_pins: gpio14-pins { + pins = "GPIO14/GSPIDI/SMB5CSCL"; + bias-disable; + input-enable; + }; + gpio15od_pins: gpio15od-pins { + pins = "GPIO15/GSPICS/SMB5CSDA"; + bias-disable; + drive-open-drain; + }; + gpio17pp_pins: gpio17pp-pins { + pins = "GPIO17/PSPI2DI/SMB4DEN"; + bias-disable; + drive-push-pull; + }; + gpio18pp_pins: gpio18pp-pins { + pins = "GPIO18/PSPI2D0/SMB4BSDA"; + bias-disable; + drive-push-pull; + }; + gpio19pp_pins: gpio19pp-pins { + pins = "GPIO19/PSPI2CK/SMB4BSCL"; + bias-disable; + drive-push-pull; + }; + gpio24pp_pins: gpio24pp-pins { + pins = "GPIO24/IOXHDO"; + bias-disable; + drive-push-pull; + }; + gpio25pp_pins: gpio25pp-pins { + pins = "GPIO25/IOXHDI"; + bias-disable; + drive-push-pull; + }; + gpio37od_pins: gpio37od-pins { + pins = "GPIO37/SMB3CSDA"; + bias-disable; + drive-open-drain; + }; + gpio59pp_pins: gpio59pp-pins { + pins = "GPIO59/SMB3DSDA"; + bias-disable; + drive-push-pull; + }; + gpio60_pins: gpio60-pins { + pins = "GPIO60/SMB3DSCL"; + bias-disable; + input-enable; + }; + gpio72od_pins: gpio72od-pins { + pins = "GPIO72/FANIN8"; + bias-disable; + drive-open-drain; + }; + gpio73od_pins: gpio73od-pins { + pins = "GPIO73/FANIN9"; + bias-disable; + drive-open-drain; + }; + gpio74od_pins: gpio74od-pins { + pins = "GPIO74/FANIN10"; + bias-disable; + drive-open-drain; + }; + gpio75od_pins: gpio75od-pins { + pins = "GPIO75/FANIN11"; + bias-disable; + drive-open-drain; + }; + gpio76od_pins: gpio76od-pins { + pins = "GPIO76/FANIN12"; + bias-disable; + drive-open-drain; + }; + gpio77od_pins: gpio77od-pins { + pins = "GPIO77/FANIN13"; + bias-disable; + drive-open-drain; + }; + gpio78od_pins: gpio78od-pins { + pins = "GPIO78/FANIN14"; + bias-disable; + drive-open-drain; + }; + gpio79od_pins: gpio79od-pins { + pins = "GPIO79/FANIN15"; + bias-disable; + drive-open-drain; + }; + gpio83_pins: gpio83-pins { + pins = "GPIO83/PWM3"; + bias-disable; + input-enable; + }; + gpio84pp_pins: gpio84pp-pins { + pins = "GPIO84/R2TXD0"; + bias-disable; + drive-push-pull; + }; + gpio85pp_pins: gpio85pp-pins { + pins = "GPIO85/R2TXD1"; + bias-disable; + drive-push-pull; + }; + gpio86pp_pins: gpio86pp-pins { + pins = "GPIO86/R2TXEN"; + bias-disable; + drive-push-pull; + }; + gpio87pp_pins: gpio87pp-pins { + pins = "GPIO87/R2RXD0"; + bias-disable; + drive-push-pull; + }; + gpio88pp_pins: gpio88pp-pins { + pins = "GPIO88/R2RXD1"; + bias-disable; + drive-push-pull; + }; + gpio89pp_pins: gpio89pp-pins { + pins = "GPIO89/R2CRSDV"; + bias-disable; + drive-push-pull; + }; + gpio90pp_pins: gpio90pp-pins { + pins = "GPIO90/R2RXERR"; + bias-disable; + drive-push-pull; + }; + gpio91_pins: gpio91-pins { + pins = "GPIO91/R2MDC"; + bias-disable; + input-enable; + }; + gpio92_pins: gpio92-pins { + pins = "GPIO92/R2MDIO"; + bias-disable; + input-enable; + }; + gpio93pp_pins: gpio93pp-pins { + pins = "GPIO93/GA20/SMB5DSCL"; + bias-disable; + drive-push-pull; + }; + gpio94pp_pins: gpio94pp-pins { + pins = "GPIO94/nKBRST/SMB5DSDA"; + bias-disable; + drive-push-pull; + }; + gpio95_pins: gpio95-pins { + pins = "GPIO95/nLRESET/nESPIRST"; + bias-disable; + input-enable; + }; + gpio125pp_pins: gpio125pp-pins { + pins = "GPIO125/SMB1CSCL"; + bias-disable; + drive-push-pull; + }; + gpio126od_pins: gpio126od-pins { + pins = "GPIO126/SMB1BSDA"; + bias-disable; + drive-open-drain; + }; + gpio127od_pins: gpio127od-pins { + pins = "GPIO127/SMB1BSCL"; + bias-disable; + drive-open-drain; + }; + gpio136_pins: gpio136-pins { + pins = "GPIO136/SD1DT0"; + bias-disable; + input-enable; + }; + gpio137_pins: gpio137-pins { + pins = "GPIO137/SD1DT1"; + bias-disable; + input-enable; + }; + gpio141_pins: gpio141-pins { + pins = "GPIO141/SD1WP"; + bias-disable; + input-enable; + }; + gpio142od_pins: gpio142od-pins { + pins = "GPIO142/SD1CMD"; + bias-disable; + drive-open-drain; + }; + gpio143ol_pins: gpio143ol-pins { + pins = "GPIO143/SD1CD/SD1PWR"; + bias-disable; + output-low; + }; + gpio144_pins: gpio144-pins { + pins = "GPIO144/PWM4"; + bias-disable; + input-enable; + }; + gpio145_pins: gpio145-pins { + pins = "GPIO145/PWM5"; + bias-disable; + input-enable; + }; + gpio146_pins: gpio146-pins { + pins = "GPIO146/PWM6"; + bias-disable; + input-enable; + }; + gpio147_pins: gpio147-pins { + pins = "GPIO147/PWM7"; + bias-disable; + input-enable; + }; + gpio148_pins: gpio148-pins { + pins = "GPIO148/MMCDT4"; + bias-disable; + input-enable; + }; + gpio149_pins: gpio149-pins { + pins = "GPIO149/MMCDT5"; + bias-disable; + input-enable; + }; + gpio150_pins: gpio150-pins { + pins = "GPIO150/MMCDT6"; + bias-disable; + input-enable; + }; + gpio151_pins: gpio151-pins { + pins = "GPIO151/MMCDT7"; + bias-disable; + input-enable; + }; + gpio152_pins: gpio152-pins { + pins = "GPIO152/MMCCLK"; + bias-disable; + input-enable; + }; + gpio153_pins: gpio153-pins { + pins = "GPIO153/MMCWP"; + bias-disable; + input-enable; + }; + gpio154_pins: gpio154-pins { + pins = "GPIO154/MMCCMD"; + bias-disable; + input-enable; + }; + gpio155_pins: gpio155-pins { + pins = "GPIO155/nMMCCD/nMMCRST"; + bias-disable; + input-enable; + }; + gpio156_pins: gpio156-pins { + pins = "GPIO156/MMCDT0"; + bias-disable; + input-enable; + }; + gpio157_pins: gpio157-pins { + pins = "GPIO157/MMCDT1"; + bias-disable; + input-enable; + }; + gpio158_pins: gpio158-pins { + pins = "GPIO158/MMCDT2"; + bias-disable; + input-enable; + }; + gpio159_pins: gpio159-pins { + pins = "GPIO159/MMCDT3"; + bias-disable; + input-enable; + }; + gpio161_pins: gpio161-pins { + pins = "GPIO161/nLFRAME/nESPICS"; + bias-disable; + input-enable; + }; + gpio162_pins: gpio162-pins { + pins = "GPIO162/SERIRQ"; + bias-disable; + input-enable; + }; + gpio163_pins: gpio163-pins { + pins = "GPIO163/LCLK/ESPICLK"; + bias-disable; + input-enable; + }; + gpio164_pins: gpio164-pins { + pins = "GPIO164/LAD0/ESPI_IO0"; + bias-disable; + input-enable; + }; + gpio165_pins: gpio165-pins { + pins = "GPIO165/LAD1/ESPI_IO1"; + bias-disable; + input-enable; + }; + gpio166_pins: gpio166-pins { + pins = "GPIO166/LAD2/ESPI_IO2"; + bias-disable; + input-enable; + }; + gpio167_pins: gpio167-pins { + pins = "GPIO167/LAD3/ESPI_IO3"; + bias-disable; + input-enable; + }; + gpio168_pins: gpio168-pins { + pins = "GPIO168/nCLKRUN/nESPIALERT"; + bias-disable; + input-enable; + }; + gpio169_pins: gpio169-pins { + pins = "GPIO169/nSCIPME"; + bias-disable; + input-enable; + }; + gpio170_pins: gpio170-pins { + pins = "GPIO170/nSMI"; + bias-disable; + input-enable; + }; + gpio175od_pins: gpio175od-pins { + pins = "GPIO175/PSPI1CK/FANIN19"; + bias-disable; + drive-open-drain; + }; + gpio176od_pins: gpio176od-pins { + pins = "GPIO176/PSPI1DO/FANIN18"; + bias-disable; + drive-open-drain; + }; + gpio177_pins: gpio177-pins { + pins = "GPIO177/PSPI1DI/FANIN17"; + bias-disable; + input-enable; + }; + gpio190od_pins: gpio190od-pins { + pins = "GPIO190/nPRD_SMI"; + bias-disable; + drive-open-drain; + }; + gpio191_pins: gpio191-pins { + pins = "GPIO191"; + bias-disable; + input-enable; + }; + gpio192_pins: gpio192-pins { + pins = "GPIO192"; + bias-disable; + input-enable; + }; + gpio194pp_pins: gpio194pp-pins { + pins = "GPIO194/SMB0BSCL"; + bias-disable; + drive-push-pull; + }; + gpio195od_pins: gpio195od-pins { + pins = "GPIO195/SMB0BSDA"; + bias-disable; + drive-open-drain; + }; + gpio196od_pins: gpio196od-pins { + pins = "GPIO196/SMB0CSCL"; + bias-disable; + drive-open-drain; + }; + gpio197od_pins: gpio197od-pins { + pins = "GPIO197/SMB0DEN"; + bias-disable; + drive-open-drain; + }; + gpio198od_pins: gpio198od-pins { + pins = "GPIO198/SMB0DSDA"; + bias-disable; + drive-open-drain; + }; + gpio199od_pins: gpio199od-pins { + pins = "GPIO199/SMB0DSCL"; + bias-disable; + drive-open-drain; + }; + gpio200pp_pins: gpio200pp-pins { + pins = "GPIO200/R2CK"; + bias-disable; + drive-push-pull; + }; + gpio202od_pins: gpio202od-pins { + pins = "GPIO202/SMB0CSDA"; + bias-disable; + drive-open-drain; + }; + gpio203_pins: gpio203-pins { + pins = "GPIO203/FANIN16"; + bias-disable; + input-enable; + }; + }; +}; From 59f5abe09f0a7a20be45003706fa1b0d1a916690 Mon Sep 17 00:00:00 2001 From: Fran Hsu Date: Fri, 31 May 2019 21:24:39 +0800 Subject: [PATCH 361/799] ARM: dts: nuvoton: Add Quanta GSJ BMC The Quanta GSJ BMC uses the Nuvoton NPCM730 SoC. Included features: 1. Image partitions 2. PWM fan controller 3. USB device 4. Serial port 5. FIU 6. LEDs and GPIOs Signed-off-by: Fran Hsu Reviewed-by: Benjamin Fair Signed-off-by: Joel Stanley --- arch/arm/boot/dts/Makefile | 3 +- arch/arm/boot/dts/nuvoton-npcm730-gsj.dts | 490 ++++++++++++++++++++++ 2 files changed, 492 insertions(+), 1 deletion(-) create mode 100644 arch/arm/boot/dts/nuvoton-npcm730-gsj.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index ce66ffd5a1bb..30bf4b007513 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -339,7 +339,8 @@ dtb-$(CONFIG_ARCH_LPC32XX) += \ lpc3250-ea3250.dtb \ lpc3250-phy3250.dtb dtb-$(CONFIG_ARCH_NPCM7XX) += \ - nuvoton-npcm750-evb.dtb + nuvoton-npcm750-evb.dtb \ + nuvoton-npcm730-gsj.dtb dtb-$(CONFIG_MACH_MESON6) += \ meson6-atv1200.dtb dtb-$(CONFIG_MACH_MESON8) += \ diff --git a/arch/arm/boot/dts/nuvoton-npcm730-gsj.dts b/arch/arm/boot/dts/nuvoton-npcm730-gsj.dts new file mode 100644 index 000000000000..d4ff49939a3d --- /dev/null +++ b/arch/arm/boot/dts/nuvoton-npcm730-gsj.dts @@ -0,0 +1,490 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (c) 2019 Quanta Computer lnc. Fran.Hsu@quantatw.com + +/dts-v1/; +#include "nuvoton-npcm730.dtsi" +#include "nuvoton-npcm730-gsj-gpio.dtsi" + +#include + +/ { + model = "Quanta GSJ Board (Device Tree v12)"; + compatible = "nuvoton,npcm750"; + + aliases { + ethernet1 = &gmac0; + serial3 = &serial3; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + i2c8 = &i2c8; + i2c9 = &i2c9; + i2c10 = &i2c10; + i2c11 = &i2c11; + i2c12 = &i2c12; + i2c15 = &i2c15; + fiu0 = &fiu0; + }; + + chosen { + stdout-path = &serial3; + }; + + memory { + reg = <0 0x40000000>; + }; + + leds { + compatible = "gpio-leds"; + + led-bmc-live { + gpios = <&gpio4 15 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + + LED_U2_0_LOCATE { + gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + LED_U2_1_LOCATE { + gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + LED_U2_2_LOCATE { + gpios = <&gpio0 2 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + LED_U2_3_LOCATE { + gpios = <&gpio0 3 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + LED_U2_4_LOCATE { + gpios = <&gpio0 10 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + LED_U2_5_LOCATE { + gpios = <&gpio0 11 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + LED_BMC_TRAY_PWRGD { + gpios = <&gpio0 19 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + LED_U2_7_FAULT { + gpios = <&gpio6 8 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + LED_U2_6_LOCATE { + gpios = <&gpio0 24 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + LED_U2_7_LOCATE { + gpios = <&gpio0 25 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + LED_U2_0_FAULT { + gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + LED_U2_1_FAULT { + gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + LED_U2_2_FAULT { + gpios = <&gpio2 22 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + LED_U2_3_FAULT { + gpios = <&gpio2 23 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + LED_U2_4_FAULT { + gpios = <&gpio2 24 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + LED_U2_5_FAULT { + gpios = <&gpio2 25 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + LED_U2_6_FAULT { + gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + }; +}; + +&fiu0 { + pinctrl-names = "default"; + pinctrl-0 = <&spi0cs1_pins>; + status = "okay"; + + spi-nor@0 { + compatible = "jedec,spi-nor"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0>; + spi-rx-bus-width = <2>; + + partitions@80000000 { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + bmc@0{ + label = "bmc"; + reg = <0x000000 0x2000000>; + }; + u-boot@0 { + label = "u-boot"; + reg = <0x0000000 0x80000>; + read-only; + }; + u-boot-env@100000{ + label = "u-boot-env"; + reg = <0x00100000 0x40000>; + }; + kernel@200000 { + label = "kernel"; + reg = <0x0200000 0x600000>; + }; + rofs@800000 { + label = "rofs"; + reg = <0x800000 0x1400000>; + }; + rwfs@1c00000 { + label = "rwfs"; + reg = <0x1c00000 0x300000>; + }; + reserved@1f00000 { + label = "reserved"; + reg = <0x1f00000 0x100000>; + }; + }; + }; +}; + +&gmac0 { + phy-mode = "rgmii-id"; + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&watchdog1 { + status = "okay"; +}; + +&rng { + status = "okay"; +}; + +&serial0 { + status = "okay"; +}; + +&serial1 { + status = "okay"; +}; + +&serial2 { + status = "okay"; +}; + +&serial3 { + status = "okay"; +}; + +&adc { + status = "okay"; +}; + +&i2c1 { + status = "okay"; + + lm75@5c { + compatible = "maxim,max31725"; + reg = <0x5c>; + status = "okay"; + }; +}; + +&i2c2 { + status = "okay"; + + lm75@5c { + compatible = "maxim,max31725"; + reg = <0x5c>; + status = "okay"; + }; +}; + +&i2c3 { + status = "okay"; + + lm75@5c { + compatible = "maxim,max31725"; + reg = <0x5c>; + }; +}; + +&i2c4 { + status = "okay"; + + lm75@5c { + compatible = "maxim,max31725"; + reg = <0x5c>; + }; +}; + +&i2c8 { + status = "okay"; +}; + +&i2c9 { + status = "okay"; + + eeprom@55 { + compatible = "atmel,24c64"; + reg = <0x55>; + }; +}; + +&i2c10 { + status = "okay"; + + eeprom@55 { + compatible = "atmel,24c64"; + reg = <0x55>; + }; +}; + +&i2c11 { + status = "okay"; + + /* P12V Quarter Brick DC/DC Power Module Q54SH12050 @60 */ + power-brick@36 { + compatible = "delta,dps800"; + reg = <0x36>; + }; + + hotswap@15 { + compatible = "ti,lm5066i"; + reg = <0x15>; + }; +}; + +&i2c12 { + status = "okay"; + + ucd90160@6b { + compatible = "ti,ucd90160"; + reg = <0x6b>; + }; +}; + +&i2c15 { + status = "okay"; + + i2c-switch@75 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x75>; + i2c-mux-idle-disconnect; + + i2c_u20: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + i2c_u21: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + i2c_u22: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + i2c_u23: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + + i2c_u24: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + + i2c_u25: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + + i2c_u26: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + }; + + i2c_u27: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + }; + }; +}; + +&pwm_fan { + pinctrl-names = "default"; + pinctrl-0 = <&pwm0_pins &pwm1_pins &pwm2_pins + &fanin0_pins &fanin1_pins + &fanin2_pins &fanin3_pins + &fanin4_pins &fanin5_pins>; + status = "okay"; + + fan@0 { + reg = <0x00>; + fan-tach-ch = /bits/ 8 <0x00 0x01>; + cooling-levels = <127 255>; + }; + + fan@1 { + reg = <0x01>; + fan-tach-ch = /bits/ 8 <0x02 0x03>; + cooling-levels = /bits/ 8 <127 255>; + }; + + fan@2 { + reg = <0x02>; + fan-tach-ch = /bits/ 8 <0x04 0x05>; + cooling-levels = /bits/ 8 <127 255>; + }; +}; + +&pinctrl { + pinctrl-names = "default"; + pinctrl-0 = < + /* GPI pins*/ + &gpio8_pins + &gpio9_pins + &gpio12_pins + &gpio13_pins + &gpio14_pins + &gpio60_pins + &gpio83_pins + &gpio91_pins + &gpio92_pins + &gpio95_pins + &gpio136_pins + &gpio137_pins + &gpio141_pins + &gpio144_pins + &gpio145_pins + &gpio146_pins + &gpio147_pins + &gpio148_pins + &gpio149_pins + &gpio150_pins + &gpio151_pins + &gpio152_pins + &gpio153_pins + &gpio154_pins + &gpio155_pins + &gpio156_pins + &gpio157_pins + &gpio158_pins + &gpio159_pins + &gpio161_pins + &gpio162_pins + &gpio163_pins + &gpio164_pins + &gpio165_pins + &gpio166_pins + &gpio167_pins + &gpio168_pins + &gpio169_pins + &gpio170_pins + &gpio177_pins + &gpio191_pins + &gpio192_pins + &gpio203_pins + /* GPO pins*/ + &gpio0pp_pins + &gpio1pp_pins + &gpio2pp_pins + &gpio3pp_pins + &gpio4pp_pins + &gpio5pp_pins + &gpio6pp_pins + &gpio7pp_pins + &gpio10pp_pins + &gpio11pp_pins + &gpio15od_pins + &gpio17pp_pins + &gpio18pp_pins + &gpio19pp_pins + &gpio24pp_pins + &gpio25pp_pins + &gpio37od_pins + &gpio59pp_pins + &gpio72od_pins + &gpio73od_pins + &gpio74od_pins + &gpio75od_pins + &gpio76od_pins + &gpio77od_pins + &gpio78od_pins + &gpio79od_pins + &gpio84pp_pins + &gpio85pp_pins + &gpio86pp_pins + &gpio87pp_pins + &gpio88pp_pins + &gpio89pp_pins + &gpio90pp_pins + &gpio93pp_pins + &gpio94pp_pins + &gpio125pp_pins + &gpio126od_pins + &gpio127od_pins + &gpio142od_pins + &gpio143ol_pins + &gpio175od_pins + &gpio176od_pins + &gpio190od_pins + &gpio194pp_pins + &gpio195od_pins + &gpio196od_pins + &gpio197od_pins + &gpio198od_pins + &gpio199od_pins + &gpio200pp_pins + &gpio202od_pins + >; +}; From 0e0610d24ee6e661dab5696197f2e68a9b29cd67 Mon Sep 17 00:00:00 2001 From: Tomer Maimon Date: Wed, 25 Sep 2019 15:26:38 +0300 Subject: [PATCH 362/799] ARM: dts: nuvoton: Add NPCM7xx RunBMC Olympus Quanta machine Add Nuvoton NPCM7xx RunBMC Olympus Quanta board device tree. Signed-off-by: Tomer Maimon Signed-off-by: Joel Stanley --- arch/arm/boot/dts/Makefile | 3 +- ...nuvoton-npcm750-runbmc-olympus-pincfg.dtsi | 517 ++++++++ .../dts/nuvoton-npcm750-runbmc-olympus.dts | 1052 +++++++++++++++++ 3 files changed, 1571 insertions(+), 1 deletion(-) create mode 100644 arch/arm/boot/dts/nuvoton-npcm750-runbmc-olympus-pincfg.dtsi create mode 100644 arch/arm/boot/dts/nuvoton-npcm750-runbmc-olympus.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 30bf4b007513..ad2eaf9ed4e4 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -339,8 +339,9 @@ dtb-$(CONFIG_ARCH_LPC32XX) += \ lpc3250-ea3250.dtb \ lpc3250-phy3250.dtb dtb-$(CONFIG_ARCH_NPCM7XX) += \ + nuvoton-npcm730-gsj.dtb \ nuvoton-npcm750-evb.dtb \ - nuvoton-npcm730-gsj.dtb + nuvoton-npcm750-runbmc-olympus.dtb dtb-$(CONFIG_MACH_MESON6) += \ meson6-atv1200.dtb dtb-$(CONFIG_MACH_MESON8) += \ diff --git a/arch/arm/boot/dts/nuvoton-npcm750-runbmc-olympus-pincfg.dtsi b/arch/arm/boot/dts/nuvoton-npcm750-runbmc-olympus-pincfg.dtsi new file mode 100644 index 000000000000..230cb344b2e1 --- /dev/null +++ b/arch/arm/boot/dts/nuvoton-npcm750-runbmc-olympus-pincfg.dtsi @@ -0,0 +1,517 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (c) 2019 Quanta Computer Inc. Samuel.Jiang@quantatw.com + +/ { + pinctrl: pinctrl@f0800000 { + gpio0ol_pins: gpio0ol-pins { + pins = "GPIO0/IOX1DI"; + bias-disable; + output-low; + }; + gpio1ol_pins: gpio1ol-pins { + pins = "GPIO1/IOX1LD"; + bias-disable; + output-low; + }; + gpio2ol_pins: gpio2ol-pins { + pins = "GPIO2/IOX1CK"; + bias-disable; + output-low; + }; + gpio3ol_pins: gpio3ol-pins { + pins = "GPIO3/IOX1D0"; + bias-disable; + output-low; + }; + gpio5_pins: gpio5-pins { + pins = "GPIO5/IOX2LD/SMB1DSCL"; + bias-disable; + input-enable; + }; + gpio6_pins: gpio6-pins { + pins = "GPIO6/IOX2CK/SMB2DSDA"; + bias-disable; + input-enable; + }; + gpio7_pins: gpio7-pins { + pins = "GPIO7/IOX2D0/SMB2DSCL"; + bias-disable; + input-enable; + }; + gpio8o_pins: gpio8o-pins { + pins = "GPIO8/LKGPO1"; + bias-disable; + output-high; + }; + gpio9ol_pins: gpio9ol-pins { + pins = "GPIO9/LKGPO2"; + bias-disable; + output-low; + }; + gpio10_pins: gpio10-pins { + pins = "GPIO10/IOXHLD"; + bias-disable; + input-enable; + }; + gpio11_pins: gpio11-pins { + pins = "GPIO11/IOXHCK"; + bias-disable; + input-enable; + }; + gpio12ol_pins: gpio12ol-pins { + pins = "GPIO12/GSPICK/SMB5BSCL"; + bias-disable; + output-low; + }; + gpio13ol_pins: gpio13ol-pins { + pins = "GPIO13/GSPIDO/SMB5BSDA"; + bias-disable; + output-low; + }; + gpio14ol_pins: gpio14ol-pins { + pins = "GPIO14/GSPIDI/SMB5CSCL"; + bias-disable; + output-low; + }; + gpio15ol_pins: gpio15ol-pins { + pins = "GPIO15/GSPICS/SMB5CSDA"; + bias-disable; + output-low; + }; + gpio20_pins: gpio20-pins { + pins = "GPIO20/SMB4CSDA/SMB15SDA"; + bias-disable; + input-enable; + }; + gpio21_pins: gpio21-pins { + pins = "GPIO21/SMB4CSCL/SMB15SCL"; + bias-disable; + input-enable; + }; + gpio22o_pins: gpio22o-pins { + pins = "GPIO22/SMB4DSDA/SMB14SDA"; + bias-disable; + output-high; + }; + gpio23_pins: gpio23-pins { + pins = "GPIO23/SMB4DSCL/SMB14SCL"; + bias-disable; + input-enable; + }; + gpio24_pins: gpio24-pins { + pins = "GPIO24/IOXHDO"; + bias-disable; + input-enable; + }; + gpio25_pins: gpio25-pins { + pins = "GPIO25/IOXHDI"; + bias-disable; + input-enable; + }; + gpio30_pins: gpio30-pins { + pins = "GPIO30/SMB3SDA"; + bias-disable; + input-enable; + }; + gpio31_pins: gpio31-pins { + pins = "GPIO31/SMB3SCL"; + bias-disable; + input-enable; + }; + gpio37o_pins: gpio37o-pins { + pins = "GPIO37/SMB3CSDA"; + bias-disable; + output-high; + }; + gpio38_pins: gpio38-pins { + pins = "GPIO38/SMB3CSCL"; + bias-disable; + input-enable; + }; + gpio39_pins: gpio39-pins { + pins = "GPIO39/SMB3BSDA"; + bias-disable; + input-enable; + }; + gpio40o_pins: gpio40o-pins { + pins = "GPIO40/SMB3BSCL"; + bias-disable; + output-high; + }; + gpio59_pins: gpio59-pins { + pins = "GPIO59/SMB3DSDA"; + bias-disable; + input-enable; + }; + gpio76_pins: gpio76-pins { + pins = "GPIO76/FANIN12"; + bias-disable; + input-enable; + }; + gpio77_pins: gpio77-pins { + pins = "GPIO77/FANIN13"; + bias-disable; + input-enable; + }; + gpio78o_pins: gpio78o-pins { + pins = "GPIO78/FANIN14"; + bias-disable; + output-high; + }; + gpio79_pins: gpio79-pins { + pins = "GPIO79/FANIN15"; + bias-disable; + input-enable; + }; + gpio82_pins: gpio82-pins { + pins = "GPIO82/PWM2"; + bias-disable; + input-enable; + }; + gpio83_pins: gpio83-pins { + pins = "GPIO83/PWM3"; + bias-disable; + input-enable; + }; + gpio84_pins: gpio84-pins { + pins = "GPIO84/R2TXD0"; + bias-disable; + input-enable; + }; + gpio85o_pins: gpio85o-pins { + pins = "GPIO85/R2TXD1"; + bias-disable; + output-high; + }; + gpio86ol_pins: gpio86ol-pins { + pins = "GPIO86/R2TXEN"; + bias-disable; + output-low; + }; + gpio87_pins: gpio87-pins { + pins = "GPIO87/R2RXD0"; + bias-disable; + input-enable; + }; + gpio88_pins: gpio88-pins { + pins = "GPIO88/R2RXD1"; + bias-disable; + input-enable; + }; + gpio89_pins: gpio89-pins { + pins = "GPIO89/R2CRSDV"; + bias-disable; + input-enable; + }; + gpio90_pins: gpio90-pins { + pins = "GPIO90/R2RXERR"; + bias-disable; + input-enable; + }; + gpio93_pins: gpio93-pins { + pins = "GPIO93/GA20/SMB5DSCL"; + bias-disable; + input-enable; + }; + gpio94ol_pins: gpio94ol-pins { + pins = "GPIO94/nKBRST/SMB5DSDA"; + bias-disable; + output-low; + }; + gpio108ol_pins: gpio108ol-pins { + pins = "GPIO108/RG1MDC"; + bias-disable; + output-low; + }; + gpio109ol_pins: gpio109ol-pins { + pins = "GPIO109/RG1MDIO"; + bias-disable; + output-low; + }; + gpio110ol_pins: gpio110ol-pins { + pins = "GPIO110/RG2TXD0/DDRV0"; + bias-disable; + output-low; + }; + gpio111ol_pins: gpio111ol-pins { + pins = "GPIO111/RG2TXD1/DDRV1"; + bias-disable; + output-low; + }; + gpio112ol_pins: gpio112ol-pins { + pins = "GPIO112/RG2TXD2/DDRV2"; + bias-disable; + output-low; + }; + gpio113ol_pins: gpio113ol-pins { + pins = "GPIO113/RG2TXD3/DDRV3"; + bias-disable; + output-low; + }; + gpio114o_pins: gpio114o-pins { + pins = "GPIO114/SMB0SCL"; + bias-disable; + output-high; + }; + gpio115_pins: gpio115-pins { + pins = "GPIO115/SMB0SDA"; + bias-disable; + input-enable; + }; + gpio120_pins: gpio120-pins { + pins = "GPIO120/SMB2CSDA"; + bias-disable; + input-enable; + }; + gpio121_pins: gpio121-pins { + pins = "GPIO121/SMB2CSCL"; + bias-disable; + input-enable; + }; + gpio122_pins: gpio122-pins { + pins = "GPIO122/SMB2BSDA"; + bias-disable; + input-enable; + }; + gpio123_pins: gpio123-pins { + pins = "GPIO123/SMB2BSCL"; + bias-disable; + input-enable; + }; + gpio124_pins: gpio124-pins { + pins = "GPIO124/SMB1CSDA"; + bias-disable; + input-enable; + }; + gpio125_pins: gpio125-pins { + pins = "GPIO125/SMB1CSCL"; + bias-disable; + input-enable; + }; + gpio126_pins: gpio126-pins { + pins = "GPIO126/SMB1BSDA"; + bias-disable; + input-enable; + }; + gpio127o_pins: gpio127o-pins { + pins = "GPIO127/SMB1BSCL"; + bias-disable; + output-high; + }; + gpio136_pins: gpio136-pins { + pins = "GPIO136/SD1DT0"; + bias-disable; + input-enable; + }; + gpio137_pins: gpio137-pins { + pins = "GPIO137/SD1DT1"; + bias-disable; + input-enable; + }; + gpio138_pins: gpio138-pins { + pins = "GPIO138/SD1DT2"; + bias-disable; + input-enable; + }; + gpio139_pins: gpio139-pins { + pins = "GPIO139/SD1DT3"; + bias-disable; + input-enable; + }; + gpio140_pins: gpio140-pins { + pins = "GPIO140/SD1CLK"; + bias-disable; + input-enable; + }; + gpio141_pins: gpio141-pins { + pins = "GPIO141/SD1WP"; + bias-disable; + input-enable; + }; + gpio142_pins: gpio142-pins { + pins = "GPIO142/SD1CMD"; + bias-disable; + input-enable; + }; + gpio143_pins: gpio143-pins { + pins = "GPIO143/SD1CD/SD1PWR"; + bias-disable; + input-enable; + }; + gpio144_pins: gpio144-pins { + pins = "GPIO144/PWM4"; + bias-disable; + input-enable; + }; + gpio145_pins: gpio145-pins { + pins = "GPIO145/PWM5"; + bias-disable; + input-enable; + }; + gpio146_pins: gpio146-pins { + pins = "GPIO146/PWM6"; + bias-disable; + input-enable; + }; + gpio147_pins: gpio147-pins { + pins = "GPIO147/PWM7"; + bias-disable; + input-enable; + }; + gpio153o_pins: gpio153o-pins { + pins = "GPIO153/MMCWP"; + bias-disable; + output-high; + }; + gpio155_pins: gpio155-pins { + pins = "GPIO155/nMMCCD/nMMCRST"; + bias-disable; + input-enable; + }; + gpio160o_pins: gpio160o-pins { + pins = "GPIO160/CLKOUT/RNGOSCOUT"; + bias-disable; + output-high; + }; + gpio169o_pins: gpio169o-pins { + pins = "GPIO169/nSCIPME"; + bias-disable; + output-high; + }; + gpio188o_pins: gpio188o-pins { + pins = "GPIO188/SPI3D2/nSPI3CS2"; + bias-disable; + output-high; + }; + gpio189_pins: gpio189-pins { + pins = "GPIO189/SPI3D3/nSPI3CS3"; + bias-disable; + input-enable; + }; + gpio196_pins: gpio196-pins { + pins = "GPIO196/SMB0CSCL"; + bias-disable; + input-enable; + }; + gpio197_pins: gpio197-pins { + pins = "GPIO197/SMB0DEN"; + bias-disable; + input-enable; + }; + gpio198o_pins: gpio198o-pins { + pins = "GPIO198/SMB0DSDA"; + bias-disable; + output-high; + }; + gpio199o_pins: gpio199o-pins { + pins = "GPIO199/SMB0DSCL"; + bias-disable; + output-high; + }; + gpio200_pins: gpio200-pins { + pins = "GPIO200/R2CK"; + input-enable; + bias-disable; + }; + gpio202_pins: gpio202-pins { + pins = "GPIO202/SMB0CSDA"; + bias-disable; + input-enable; + }; + gpio203o_pins: gpio203o-pins { + pins = "GPIO203/FANIN16"; + bias-disable; + output-high; + }; + gpio208_pins: gpio208-pins { + pins = "GPIO208/RG2TXC/DVCK"; + bias-disable; + input-enable; + }; + gpio209ol_pins: gpio209ol-pins { + pins = "GPIO209/RG2TXCTL/DDRV4"; + bias-disable; + output-low; + }; + gpio210ol_pins: gpio210ol-pins { + pins = "GPIO210/RG2RXD0/DDRV5"; + bias-disable; + output-low; + }; + gpio211ol_pins: gpio211ol-pins { + pins = "GPIO211/RG2RXD1/DDRV6"; + bias-disable; + output-low; + }; + gpio212ol_pins: gpio212ol-pins { + pins = "GPIO212/RG2RXD2/DDRV7"; + bias-disable; + output-low; + }; + gpio213ol_pins: gpio213ol-pins { + pins = "GPIO213/RG2RXD3/DDRV8"; + bias-disable; + output-low; + }; + gpio214ol_pins: gpio214ol-pins { + pins = "GPIO214/RG2RXC/DDRV9"; + bias-disable; + output-low; + }; + gpio215ol_pins: gpio215ol-pins { + pins = "GPIO215/RG2RXCTL/DDRV10"; + bias-disable; + output-low; + }; + gpio216ol_pins: gpio216ol-pins { + pins = "GPIO216/RG2MDC/DDRV11"; + bias-disable; + output-low; + }; + gpio217ol_pins: gpio217ol-pins { + pins = "GPIO217/RG2MDIO/DVHSYNC"; + bias-disable; + output-low; + }; + gpio224_pins: gpio224-pins { + pins = "GPIO224/SPIXCK"; + bias-disable; + input-enable; + }; + gpio225ol_pins: gpio225ol-pins { + pins = "GPO225/SPIXD0/STRAP12"; + bias-disable; + output-low; + }; + gpio226ol_pins: gpio226ol-pins { + pins = "GPO226/SPIXD1/STRAP13"; + bias-disable; + output-low; + }; + gpio227ol_pins: gpio227ol-pins { + pins = "GPIO227/nSPIXCS0"; + bias-disable; + output-low; + }; + gpio228o_pins: gpio228ol-pins { + pins = "GPIO228/nSPIXCS1"; + bias-disable; + output-high; + }; + gpio229o_pins: gpio229o-pins { + pins = "GPO229/SPIXD2/STRAP3"; + bias-disable; + output-high; + }; + gpio230_pins: gpio230-pins { + pins = "GPIO230/SPIXD3"; + bias-disable; + input-enable; + }; + gpio231o_pins: gpio231o-pins { + pins = "GPIO231/nCLKREQ"; + bias-disable; + output-high; + }; + }; +}; diff --git a/arch/arm/boot/dts/nuvoton-npcm750-runbmc-olympus.dts b/arch/arm/boot/dts/nuvoton-npcm750-runbmc-olympus.dts new file mode 100644 index 000000000000..767e0ac0df7c --- /dev/null +++ b/arch/arm/boot/dts/nuvoton-npcm750-runbmc-olympus.dts @@ -0,0 +1,1052 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (c) 2019 Nuvoton Technology +// Copyright (c) 2019 Quanta Computer Inc. + +/dts-v1/; +#include "nuvoton-npcm750.dtsi" +#include "nuvoton-npcm750-runbmc-olympus-pincfg.dtsi" + +#include +#include + +/ { + model = "Nuvoton npcm750 RunBMC Olympus"; + compatible = "nuvoton,npcm750"; + + aliases { + ethernet1 = &gmac0; + serial0 = &serial0; + serial1 = &serial1; + serial2 = &serial2; + serial3 = &serial3; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + i2c5 = &i2c5; + i2c6 = &i2c6; + i2c7 = &i2c7; + i2c8 = &i2c8; + i2c9 = &i2c9; + i2c10 = &i2c10; + i2c11 = &i2c11; + i2c12 = &i2c12; + i2c13 = &i2c13; + spi0 = &spi0; + spi1 = &spi1; + fiu0 = &fiu0; + fiu1 = &fiu3; + }; + + chosen { + stdout-path = &serial3; + }; + + memory { + reg = <0 0x40000000>; + }; + + iio-hwmon { + compatible = "iio-hwmon"; + io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>, + <&adc 4>, <&adc 5>, <&adc 6>, <&adc 7>; + }; + + leds { + compatible = "gpio-leds"; + heartbeat { + label = "heartbeat"; + gpios = <&gpio3 14 1>; + }; + + identify { + label = "identify"; + gpios = <&gpio3 15 1>; + }; + }; + + jtag { + compatible = "nuvoton,npcm750-jtag"; + enable_pspi_jtag = <1>; + pspi-index = <2>; + tck { + label = "tck"; + gpios = <&gpio0 19 0>; /* gpio19 */ + regbase = <0xf0010000 0x1000>; + }; + + tdi { + label = "tdi"; + gpios = <&gpio0 18 0>; /* gpio18 */ + regbase = <0xf0010000 0x1000>; + }; + + tdo { + label = "tdo"; + gpios = <&gpio0 17 0>; /* gpio17 */ + regbase = <0xf0010000 0x1000>; + }; + tms { + label = "tms"; + gpios = <&gpio0 16 0>; /* gpio16 */ + regbase = <0xf0010000 0x1000>; + }; + }; +}; + +&fiu0 { + pinctrl-names = "default"; + pinctrl-0 = <&spi0cs1_pins>; + status = "okay"; + + spi-nor@0 { + compatible = "jedec,spi-nor"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0>; + spi-rx-bus-width = <2>; + + partitions@80000000 { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + bmc@0{ + label = "bmc"; + reg = <0x000000 0x2000000>; + }; + u-boot@0 { + label = "u-boot"; + reg = <0x0000000 0x80000>; + read-only; + }; + u-boot-env@100000{ + label = "u-boot-env"; + reg = <0x00100000 0x40000>; + }; + kernel@200000 { + label = "kernel"; + reg = <0x0200000 0x600000>; + }; + rofs@800000 { + label = "rofs"; + reg = <0x800000 0x1500000>; + }; + rwfs@1d00000 { + label = "rwfs"; + reg = <0x1d00000 0x300000>; + }; + }; + }; + + spi-nor@1 { + compatible = "jedec,spi-nor"; + #address-cells = <1>; + #size-cells = <1>; + reg = <1>; + npcm,fiu-rx-bus-width = <2>; + + partitions@88000000 { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + spare1@0 { + label = "spi0-cs1-spare1"; + reg = <0x0 0x800000>; + }; + spare2@800000 { + label = "spi0-cs1-spare2"; + reg = <0x800000 0x0>; + }; + }; + }; +}; + +&fiu3 { + pinctrl-0 = <&spi3_pins>; + status = "okay"; + + spi-nor@0 { + compatible = "jedec,spi-nor"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0>; + spi-rx-bus-width = <2>; + + partitions@A0000000 { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + system1@0 { + label = "spi3-system1"; + reg = <0x0 0x800000>; + }; + system2@800000 { + label = "spi3-system2"; + reg = <0x800000 0x0>; + }; + }; + }; +}; + +&gcr { + mux-controller { + compatible = "mmio-mux"; + #mux-control-cells = <1>; + + mux-reg-masks = <0x38 0x07>; + idle-states = <6>; + }; +}; + +&gmac0 { + phy-mode = "rgmii-id"; + snps,eee-force-disable; + status = "okay"; +}; + +&i2c1 { + status = "okay"; + + i2c-switch@70 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x70>; + i2c-mux-idle-disconnect; + + i2c_slot1a: i2c-bus@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + i2c_slot1b: i2c-bus@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + i2c_slot2a: i2c-bus@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + i2c_slot2b: i2c-bus@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + + i2c_slot3: i2c-bus@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + + i2c_slot4: i2c-bus@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + + i2c_slot5: i2c-bus@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + }; + }; + + i2c-switch@71 { + compatible = "nxp,pca9546"; + reg = <0x71>; + #address-cells = <1>; + #size-cells = <0>; + i2c-mux-idle-disconnect; + + i2c_m2_s1: i2c-bus@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + i2c_m2_s2: i2c-bus@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + i2c_m2_s3: i2c-bus@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + i2c_m2_s4: i2c-bus@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + }; +}; + +&i2c2 { + status = "okay"; + + tmp421@4c { + compatible = "ti,tmp421"; + reg = <0x4c>; + }; + + power-supply@58 { + compatible = "delta,dps800"; + reg = <0x58>; + }; +}; + +&i2c3 { + status = "okay"; +}; + +&i2c4 { + status = "okay"; + + eeprom@54 { + compatible = "atmel,24c64"; + reg = <0x54>; + }; +}; + +&i2c5 { + status = "okay"; + + i2c-slave-mqueue@10 { + compatible = "i2c-slave-mqueue"; + reg = <(I2C_OWN_SLAVE_ADDRESS | 0x10)>; + }; +}; + +&i2c6 { + status = "okay"; + + ina219@40 { + compatible = "ti,ina219"; + reg = <0x40>; + }; + ina219@41 { + compatible = "ti,ina219"; + reg = <0x41>; + }; + ina219@44 { + compatible = "ti,ina219"; + reg = <0x44>; + }; + ina219@45 { + compatible = "ti,ina219"; + reg = <0x45>; + }; + tps53679@60 { + compatible = "ti,tps53679"; + reg = <0x60>; + }; + tps53659@62 { + compatible = "ti,tps53659"; + reg = <0x62>; + }; + tps53659@64 { + compatible = "ti,tps53659"; + reg = <0x64>; + }; + tps53622@67 { + compatible = "ti,tps53622"; + reg = <0x67>; + }; + tps53622@69 { + compatible = "ti,tps53622"; + reg = <0x69>; + }; + tps53679@70 { + compatible = "ti,tps53679"; + reg = <0x70>; + }; + tps53659@72 { + compatible = "ti,tps53659"; + reg = <0x72>; + }; + tps53659@74 { + compatible = "ti,tps53659"; + reg = <0x74>; + }; + tps53622@77 { + compatible = "ti,tps53622"; + reg = <0x77>; + }; +}; + +&i2c7 { + status = "okay"; + + tmp421@4c { + compatible = "ti,tmp421"; + reg = <0x4c>; + }; +}; + +&i2c8 { + status = "okay"; + + adm1278@11 { + compatible = "adm1278"; + reg = <0x11>; + Rsense = <500>; + }; +}; + +&i2c9 { + status = "okay"; +}; + +&i2c10 { + status = "okay"; + + gpio: pca9555@27 { + compatible = "nxp,pca9555"; + reg = <0x27>; + + gpio-controller; + #gpio-cells = <2>; + }; +}; + +&i2c11 { + status = "okay"; + + pca9539_g1a: pca9539-g1a@74 { + compatible = "nxp,pca9539"; + reg = <0x74>; + gpio-controller; + #gpio-cells = <2>; + reset-gpios = <&gpio7 4 GPIO_ACTIVE_LOW>; + G1A_P0_0 { + gpio-hog; + gpios = <0 0>; + output-high; + line-name = "TPM_BMC_ALERT_N"; + }; + G1A_P0_1 { + gpio-hog; + gpios = <1 0>; + input; + line-name = "FM_BIOS_TOP_SWAP"; + }; + G1A_P0_2 { + gpio-hog; + gpios = <2 0>; + input; + line-name = "FM_BIOS_PREFRB2_GOOD"; + }; + G1A_P0_3 { + gpio-hog; + gpios = <3 0>; + input; + line-name = "BMC_SATAXPCIE_0TO3_SEL"; + }; + G1A_P0_4 { + gpio-hog; + gpios = <4 0>; + input; + line-name = "BMC_SATAXPCIE_4TO7_SEL"; + }; + G1A_P0_5 { + gpio-hog; + gpios = <5 0>; + output-low; + line-name = "FM_UV_ADR_TRIGGER_EN_N"; + }; + G1A_P0_6 { + gpio-hog; + gpios = <6 0>; + input; + line-name = "RM_THROTTLE_EN_N"; + }; + G1A_P1_0 { + gpio-hog; + gpios = <8 0>; + input; + line-name = "FM_BMC_TPM_PRES_N"; + }; + G1A_P1_1 { + gpio-hog; + gpios = <9 0>; + input; + line-name = "FM_CPU0_SKTOCC_LVT3_N"; + }; + G1A_P1_2 { + gpio-hog; + gpios = <10 0>; + input; + line-name = "FM_CPU1_SKTOCC_LVT3_N"; + }; + G1A_P1_3 { + gpio-hog; + gpios = <11 0>; + input; + line-name = "PSU1_ALERT_N"; + }; + G1A_P1_4 { + gpio-hog; + gpios = <12 0>; + input; + line-name = "PSU2_ALERT_N"; + }; + G1A_P1_5 { + gpio-hog; + gpios = <13 0>; + input; + line-name = "H_CPU0_FAST_WAKE_LVT3_N"; + }; + G1A_P1_6 { + gpio-hog; + gpios = <14 0>; + output-high; + line-name = "I2C_MUX1_RESET_N"; + }; + G1A_P1_7 { + gpio-hog; + gpios = <15 0>; + input; + line-name = "FM_CPU_CATERR_LVT3_N"; + }; + }; + + pca9539_g1b: pca9539-g1b@75 { + compatible = "nxp,pca9539"; + reg = <0x75>; + gpio-controller; + #gpio-cells = <2>; + G1B_P0_0 { + gpio-hog; + gpios = <0 0>; + input; + line-name = "PVDDQ_ABC_PINALERT_N"; + }; + G1B_P0_1 { + gpio-hog; + gpios = <1 0>; + input; + line-name = "PVDDQ_DEF_PINALERT_N"; + }; + G1B_P0_2 { + gpio-hog; + gpios = <2 0>; + input; + line-name = "PVDDQ_GHJ_PINALERT_N"; + }; + G1B_P0_3 { + gpio-hog; + gpios = <3 0>; + input; + line-name = "PVDDQ_KLM_PINALERT_N"; + }; + G1B_P0_5 { + gpio-hog; + gpios = <5 0>; + input; + line-name = "FM_BOARD_REV_ID0"; + }; + G1B_P0_6 { + gpio-hog; + gpios = <6 0>; + input; + line-name = "FM_BOARD_REV_ID1"; + }; + G1B_P0_7 { + gpio-hog; + gpios = <7 0>; + input; + line-name = "FM_BOARD_REV_ID2"; + }; + G1B_P1_0 { + gpio-hog; + gpios = <8 0>; + input; + line-name = "FM_OC_DETECT_EN_N"; + }; + G1B_P1_1 { + gpio-hog; + gpios = <9 0>; + input; + line-name = "FM_FLASH_DESC_OVERRIDE"; + }; + G1B_P1_2 { + gpio-hog; + gpios = <10 0>; + output-low; + line-name = "FP_PWR_ID_LED_N"; + }; + G1B_P1_3 { + gpio-hog; + gpios = <11 0>; + output-low; + line-name = "BMC_LED_PWR_GRN"; + }; + G1B_P1_4 { + gpio-hog; + gpios = <12 0>; + output-low; + line-name = "BMC_LED_PWR_AMBER"; + }; + G1B_P1_5 { + gpio-hog; + gpios = <13 0>; + output-high; + line-name = "FM_BMC_FAULT_LED_N"; + }; + G1B_P1_6 { + gpio-hog; + gpios = <14 0>; + output-high; + line-name = "FM_CPLD_BMC_PWRDN_N"; + }; + G1B_P1_7 { + gpio-hog; + gpios = <15 0>; + output-high; + line-name = "BMC_LED_CATERR_N"; + }; + }; +}; + +&i2c12 { + status = "okay"; + + pca9539_g2a: pca9539-g2a@74 { + compatible = "nxp,pca9539"; + reg = <0x74>; + gpio-controller; + #gpio-cells = <2>; + reset-gpios = <&gpio5 28 GPIO_ACTIVE_LOW>; + G2A_P0_0 { + gpio-hog; + gpios = <0 0>; + output-high; + line-name = "BMC_PON_RST_REQ_N"; + }; + G2A_P0_1 { + gpio-hog; + gpios = <1 0>; + output-high; + line-name = "BMC_RST_IND_REQ_N"; + }; + G2A_P0_2 { + gpio-hog; + gpios = <2 0>; + input; + line-name = "RST_BMC_RTCRST"; + }; + G2A_P0_3 { + gpio-hog; + gpios = <3 0>; + output-high; + line-name = "FM_BMC_PWRBTN_OUT_N"; + }; + G2A_P0_4 { + gpio-hog; + gpios = <4 0>; + output-high; + line-name = "RST_BMC_SYSRST_BTN_OUT_N"; + }; + G2A_P0_5 { + gpio-hog; + gpios = <5 0>; + output-high; + line-name = "FM_BATTERY_SENSE_EN_N"; + }; + G2A_P0_6 { + gpio-hog; + gpios = <6 0>; + output-high; + line-name = "FM_BMC_READY_N"; + }; + G2A_P0_7 { + gpio-hog; + gpios = <7 0>; + input; + line-name = "IRQ_BMC_PCH_SMI_LPC_N"; + }; + G2A_P1_0 { + gpio-hog; + gpios = <8 0>; + input; + line-name = "FM_SLOT4_CFG0"; + }; + G2A_P1_1 { + gpio-hog; + gpios = <9 0>; + input; + line-name = "FM_SLOT4_CFG1"; + }; + G2A_P1_2 { + gpio-hog; + gpios = <10 0>; + input; + line-name = "FM_NVDIMM_EVENT_N"; + }; + G2A_P1_3 { + gpio-hog; + gpios = <11 0>; + input; + line-name = "PSU1_BLADE_EN_N"; + }; + G2A_P1_4 { + gpio-hog; + gpios = <12 0>; + input; + line-name = "BMC_PCH_FNM"; + }; + G2A_P1_5 { + gpio-hog; + gpios = <13 0>; + input; + line-name = "FM_SOL_UART_CH_SEL"; + }; + G2A_P1_6 { + gpio-hog; + gpios = <14 0>; + input; + line-name = "FM_BIOS_POST_CMPLT_N"; + }; + }; + + pca9539_g2b: pca9539-g2b@75 { + compatible = "nxp,pca9539"; + reg = <0x75>; + gpio-controller; + #gpio-cells = <2>; + G2B_P0_0 { + gpio-hog; + gpios = <0 0>; + input; + line-name = "FM_CPU_MSMI_LVT3_N"; + }; + G2B_P0_1 { + gpio-hog; + gpios = <1 0>; + input; + line-name = "FM_BIOS_MRC_DEBUG_MSG_DIS"; + }; + G2B_P0_2 { + gpio-hog; + gpios = <2 0>; + input; + line-name = "FM_CPU1_DISABLE_BMC_N"; + }; + G2B_P0_3 { + gpio-hog; + gpios = <3 0>; + output-low; + line-name = "BMC_JTAG_SELECT"; + }; + G2B_P0_4 { + gpio-hog; + gpios = <4 0>; + output-high; + line-name = "PECI_MUX_SELECT"; + }; + G2B_P0_5 { + gpio-hog; + gpios = <5 0>; + output-high; + line-name = "I2C_MUX2_RESET_N"; + }; + G2B_P0_6 { + gpio-hog; + gpios = <6 0>; + input; + line-name = "FM_BMC_CPLD_PSU2_ON"; + }; + G2B_P0_7 { + gpio-hog; + gpios = <7 0>; + output-high; + line-name = "PSU2_ALERT_EN_N"; + }; + G2B_P1_0 { + gpio-hog; + gpios = <8 0>; + output-high; + line-name = "FM_CPU_BMC_INIT"; + }; + G2B_P1_1 { + gpio-hog; + gpios = <9 0>; + output-high; + line-name = "IRQ_BMC_PCH_SCI_LPC_N"; + }; + G2B_P1_2 { + gpio-hog; + gpios = <10 0>; + output-low; + line-name = "PMB_ALERT_EN_N"; + }; + G2B_P1_3 { + gpio-hog; + gpios = <11 0>; + output-high; + line-name = "FM_FAST_PROCHOT_EN_N"; + }; + G2B_P1_4 { + gpio-hog; + gpios = <12 0>; + output-high; + line-name = "BMC_NVDIMM_PRSNT_N"; + }; + G2B_P1_5 { + gpio-hog; + gpios = <13 0>; + output-low; + line-name = "FM_BACKUP_BIOS_SEL_H_BMC"; + }; + G2B_P1_6 { + gpio-hog; + gpios = <14 0>; + output-high; + line-name = "FM_PWRBRK_N"; + }; + }; +}; + +&i2c13 { + status = "okay"; + + tmp75@4a { + compatible = "ti,tmp75"; + reg = <0x4a>; + status = "okay"; + }; + m24128_fru@51 { + compatible = "atmel,24c128"; + reg = <0x51>; + pagesize = <64>; + status = "okay"; + }; +}; + +&pwm_fan { + pinctrl-names = "default"; + pinctrl-0 = < &pwm0_pins &pwm1_pins + &fanin0_pins &fanin1_pins + &fanin2_pins &fanin3_pins + &fanin4_pins &fanin5_pins + &fanin6_pins &fanin7_pins + &fanin8_pins &fanin9_pins + &fanin10_pins &fanin11_pins>; + status = "okay"; + + fan@0 { + reg = <0x00>; + fan-tach-ch = /bits/ 8 <0x00 0x01>; + cooling-levels = <127 255>; + }; + fan@1 { + reg = <0x01>; + fan-tach-ch = /bits/ 8 <0x02 0x03>; + cooling-levels = /bits/ 8 <127 255>; + }; + fan@2 { + reg = <0x02>; + fan-tach-ch = /bits/ 8 <0x04 0x05>; + cooling-levels = /bits/ 8 <127 255>; + }; + fan@3 { + reg = <0x03>; + fan-tach-ch = /bits/ 8 <0x06 0x07>; + cooling-levels = /bits/ 8 <127 255>; + }; + fan@4 { + reg = <0x04>; + fan-tach-ch = /bits/ 8 <0x08 0x09>; + cooling-levels = /bits/ 8 <127 255>; + }; + fan@5 { + reg = <0x05>; + fan-tach-ch = /bits/ 8 <0x0A 0x0B>; + cooling-levels = /bits/ 8 <127 255>; + }; + fan@6 { + reg = <0x06>; + fan-tach-ch = /bits/ 8 <0x0C 0x0D>; + cooling-levels = /bits/ 8 <127 255>; + }; + fan@7 { + reg = <0x07>; + fan-tach-ch = /bits/ 8 <0x0E 0x0F>; + cooling-levels = /bits/ 8 <127 255>; + }; +}; + +&ehci1 { + status = "okay"; +}; + +&watchdog1 { + status = "okay"; +}; + +&rng { + status = "okay"; +}; + +&serial0 { + status = "okay"; +}; + +&serial1 { + status = "okay"; +}; + +&serial2 { + status = "okay"; +}; + +&serial3 { + status = "okay"; +}; + +&adc { + #io-channel-cells = <1>; + status = "okay"; +}; + +&kcs1 { + status = "okay"; +}; + +&kcs2 { + status = "okay"; +}; + +&kcs3 { + status = "okay"; +}; + +&spi0 { + cs-gpios = <&gpio6 11 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&spi1 { + status = "okay"; +}; + +&pinctrl { + pinctrl-names = "default"; + pinctrl-0 = < + /******* RunBMC inside Module pins *******/ + &gpio0ol_pins + &gpio1ol_pins + &gpio2ol_pins + &gpio3ol_pins + &gpio8o_pins + &gpio9ol_pins + &gpio12ol_pins + &gpio13ol_pins + &gpio14ol_pins + &gpio15ol_pins + &gpio37o_pins + &gpio38_pins + &gpio39_pins + &gpio94ol_pins + &gpio108ol_pins + &gpio109ol_pins + &gpio111ol_pins + &gpio112ol_pins + &gpio113ol_pins + &gpio208_pins + &gpio209ol_pins + &gpio210ol_pins + &gpio211ol_pins + &gpio212ol_pins + &gpio213ol_pins + &gpio214ol_pins + &gpio215ol_pins + &gpio216ol_pins + &gpio217ol_pins + /******* RunBMC outside Connector pins *******/ + &gpio5_pins + &gpio6_pins + &gpio7_pins + &gpio10_pins + &gpio11_pins + &gpio20_pins + &gpio21_pins + &gpio22o_pins + &gpio23_pins + &gpio24_pins + &gpio25_pins + &gpio30_pins + &gpio31_pins + &gpio40o_pins + &gpio59_pins + &gpio76_pins + &gpio77_pins + &gpio78o_pins + &gpio79_pins + &gpio82_pins + &gpio83_pins + &gpio84_pins + &gpio85o_pins + &gpio86ol_pins + &gpio87_pins + &gpio88_pins + &gpio89_pins + &gpio90_pins + &gpio93_pins + &gpio114o_pins + &gpio115_pins + &gpio120_pins + &gpio121_pins + &gpio122_pins + &gpio123_pins + &gpio124_pins + &gpio125_pins + &gpio126_pins + &gpio127o_pins + &gpio136_pins + &gpio137_pins + &gpio138_pins + &gpio139_pins + &gpio140_pins + &gpio141_pins + &gpio142_pins + &gpio143_pins + &gpio144_pins + &gpio146_pins + &gpio145_pins + &gpio147_pins + &gpio153o_pins + &gpio155_pins + &gpio160o_pins + &gpio169o_pins + &gpio188o_pins + &gpio189_pins + &gpio196_pins + &gpio197_pins + &gpio198o_pins + &gpio199o_pins + &gpio200_pins + &gpio202_pins + &gpio203o_pins + &gpio224_pins + &gpio225ol_pins + &gpio226ol_pins + &gpio227ol_pins + &gpio228o_pins + &gpio229o_pins + &gpio230_pins + &gpio231o_pins + &ddc_pins + &wdog1_pins + &wdog2_pins + >; +}; From 14579c76f5ca35dbf119685994aa0a5c5a0d9630 Mon Sep 17 00:00:00 2001 From: Lancelot Kao Date: Mon, 16 Nov 2020 17:21:27 -0600 Subject: [PATCH 363/799] ARM: dts: nuvoton: Add Fii Kudo system Add device tree for the Kudo BMC. Kudo is an Ampere (Altra) server platform manufactured by Fii and is based on a Nuvoton NPCM730 SoC. Signed-off-by: Mustatfa Shehabi Signed-off-by: Mohaimen alsmarai Signed-off-by: Lancelot Kao Reviewed-by: Vivekanand Veeracholan Reviewed-by: Benjamin Fair Reviewed-by: Joel Stanley Link: https://lore.kernel.org/r/20201116232127.7066-1-lancelot.kao@fii-usa.com Signed-off-by: Joel Stanley --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/nuvoton-npcm730-kudo.dts | 826 +++++++++++++++++++++ 2 files changed, 827 insertions(+) create mode 100644 arch/arm/boot/dts/nuvoton-npcm730-kudo.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index ad2eaf9ed4e4..7525d38ea1ab 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -340,6 +340,7 @@ dtb-$(CONFIG_ARCH_LPC32XX) += \ lpc3250-phy3250.dtb dtb-$(CONFIG_ARCH_NPCM7XX) += \ nuvoton-npcm730-gsj.dtb \ + nuvoton-npcm730-kudo.dtb \ nuvoton-npcm750-evb.dtb \ nuvoton-npcm750-runbmc-olympus.dtb dtb-$(CONFIG_MACH_MESON6) += \ diff --git a/arch/arm/boot/dts/nuvoton-npcm730-kudo.dts b/arch/arm/boot/dts/nuvoton-npcm730-kudo.dts new file mode 100644 index 000000000000..82a104b2a65f --- /dev/null +++ b/arch/arm/boot/dts/nuvoton-npcm730-kudo.dts @@ -0,0 +1,826 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (c) 2020 Fii USA Inc. + +/dts-v1/; +#include "nuvoton-npcm730.dtsi" + +#include + +/ { + model = "Fii Kudo Board"; + compatible = "fii,kudo", "nuvoton,npcm730"; + + aliases { + ethernet1 = &gmac0; + serial0 = &serial0; + serial1 = &serial1; + serial2 = &serial2; + serial3 = &serial3; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + i2c5 = &i2c5; + i2c6 = &i2c6; + i2c7 = &i2c7; + i2c8 = &i2c8; + i2c9 = &i2c9; + i2c10 = &i2c10; + i2c11 = &i2c11; + i2c12 = &i2c12; + i2c13 = &i2c13; + i2c14 = &i2c14; + i2c15 = &i2c15; + spi0 = &spi0; + spi1 = &spi1; + fiu0 = &fiu0; + fiu1 = &fiu3; + }; + + chosen { + stdout-path = &serial3; + }; + + memory { + reg = <0 0x40000000>; + }; + + iio-hwmon { + compatible = "iio-hwmon"; + io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>, + <&adc 4>, <&adc 5>, <&adc 6>, <&adc 7>; + }; + + jtag_master { + compatible = "nuvoton,npcm750-jtag-master"; + #address-cells = <1>; + #size-cells = <1>; + + // dev/jtag0 + dev-num = <0>; + // pspi or gpio + mode = "pspi"; + + // pspi2 + pspi-controller = <2>; + reg = <0xf0201000 0x1000>; + interrupts = ; + clocks = <&clk NPCM7XX_CLK_APB5>; + + // TCK, TDI, TDO, TMS + jtag-gpios = <&gpio0 19 GPIO_ACTIVE_HIGH>, + <&gpio0 18 GPIO_ACTIVE_HIGH>, + <&gpio0 17 GPIO_ACTIVE_HIGH>, + <&gpio0 16 GPIO_ACTIVE_HIGH>; + }; + + leds { + compatible = "gpio-leds"; + heartbeat { + label = "heartbeat"; + gpios = <&gpio0 14 1>; + }; + }; + + pinctrl: pinctrl@f0800000 { + gpio61oh_pins: gpio61oh-pins { + pins = "GPO61/nDTR1_BOUT1/STRAP6"; + bias-disable; + output-high; + }; + gpio62oh_pins: gpio62oh-pins { + pins = "GPO62/nRTST1/STRAP5"; + bias-disable; + output-high; + }; + gpio161ol_pins: gpio161ol-pins { + pins = "GPIO161/nLFRAME/nESPICS"; + bias-disable; + output-low; + }; + gpio163i_pins: gpio163i-pins { + pins = "GPIO163/LCLK/ESPICLK"; + bias-disable; + input-enable; + }; + gpio167ol_pins: gpio167ol-pins { + pins = "GPIO167/LAD3/ESPI_IO3"; + bias-disable; + output-low; + }; + gpio95i_pins: gpio95i-pins { + pins = "GPIO95/nLRESET/nESPIRST"; + bias-disable; + input-enable; + }; + gpio65ol_pins: gpio65ol-pins { + pins = "GPIO65/FANIN1"; + bias-disable; + output-low; + }; + gpio66oh_pins: gpio66oh-pins { + pins = "GPIO66/FANIN2"; + bias-disable; + output-high; + }; + gpio67oh_pins: gpio67oh-pins { + pins = "GPIO67/FANIN3"; + bias-disable; + output-high; + }; + gpio68ol_pins: gpio68ol-pins { + pins = "GPIO68/FANIN4"; + bias-disable; + output-low; + }; + gpio69i_pins: gpio69i-pins { + pins = "GPIO69/FANIN5"; + bias-disable; + input-enable; + }; + gpio70ol_pins: gpio70ol-pins { + pins = "GPIO70/FANIN6"; + bias-disable; + output-low; + }; + gpio71i_pins: gpio71i-pins { + pins = "GPIO71/FANIN7"; + bias-disable; + input-enable; + }; + gpio72i_pins: gpio72i-pins { + pins = "GPIO72/FANIN8"; + bias-disable; + input-enable; + }; + gpio73i_pins: gpio73i-pins { + pins = "GPIO73/FANIN9"; + bias-disable; + input-enable; + }; + gpio74i_pins: gpio74i-pins { + pins = "GPIO74/FANIN10"; + bias-disable; + input-enable; + }; + gpio75i_pins: gpio75i-pins { + pins = "GPIO75/FANIN11"; + bias-disable; + input-enable; + }; + gpio76i_pins: gpio76i-pins { + pins = "GPIO76/FANIN12"; + bias-disable; + input-enable; + }; + gpio77i_pins: gpio77i-pins { + pins = "GPIO77/FANIN13"; + bias-disable; + input-enable; + }; + gpio78i_pins: gpio78i-pins { + pins = "GPIO78/FANIN14"; + bias-disable; + input-enable; + }; + gpio79ol_pins: gpio79ol-pins { + pins = "GPIO79/FANIN15"; + bias-disable; + output-low; + }; + gpio80oh_pins: gpio80oh-pins { + pins = "GPIO80/PWM0"; + bias-disable; + output-high; + }; + gpio81i_pins: gpio81i-pins { + pins = "GPIO81/PWM1"; + bias-disable; + input-enable; + }; + gpio82i_pins: gpio82i-pins { + pins = "GPIO82/PWM2"; + bias-disable; + input-enable; + }; + gpio83i_pins: gpio83i-pins { + pins = "GPIO83/PWM3"; + bias-disable; + input-enable; + }; + gpio144i_pins: gpio144i-pins { + pins = "GPIO144/PWM4"; + bias-disable; + input-enable; + }; + gpio145i_pins: gpio145i-pins { + pins = "GPIO145/PWM5"; + bias-disable; + input-enable; + }; + gpio146i_pins: gpio146i-pins { + pins = "GPIO146/PWM6"; + bias-disable; + input-enable; + }; + gpio147oh_pins: gpio147oh-pins { + pins = "GPIO147/PWM7"; + bias-disable; + output-high; + }; + gpio168ol_pins: gpio168ol-pins { + pins = "GPIO168/nCLKRUN/nESPIALERT"; + bias-disable; + output-low; + }; + gpio169oh_pins: gpio169oh-pins { + pins = "GPIO169/nSCIPME"; + bias-disable; + output-high; + }; + gpio170ol_pins: gpio170ol-pins { + pins = "GPIO170/nSMI"; + bias-disable; + output-low; + }; + gpio218oh_pins: gpio218oh-pins { + pins = "GPIO218/nWDO1"; + bias-disable; + output-high; + }; + gpio37i_pins: gpio37i-pins { + pins = "GPIO37/SMB3CSDA"; + bias-disable; + input-enable; + }; + gpio38i_pins: gpio38i-pins { + pins = "GPIO38/SMB3CSCL"; + bias-disable; + input-enable; + }; + gpio39i_pins: gpio39i-pins { + pins = "GPIO39/SMB3BSDA"; + bias-disable; + input-enable; + }; + gpio40i_pins: gpio40i-pins { + pins = "GPIO40/SMB3BSCL"; + bias-disable; + input-enable; + }; + gpio121i_pins: gpio121i-pins { + pins = "GPIO121/SMB2CSCL"; + bias-disable; + input-enable; + }; + gpio122i_pins: gpio122i-pins { + pins = "GPIO122/SMB2BSDA"; + bias-disable; + input-enable; + }; + gpio123i_pins: gpio123i-pins { + pins = "GPIO123/SMB2BSCL"; + bias-disable; + input-enable; + }; + gpio124i_pins: gpio124i-pins { + pins = "GPIO124/SMB1CSDA"; + bias-disable; + input-enable; + }; + gpio125i_pins: gpio125i-pins { + pins = "GPIO125/SMB1CSCL"; + bias-disable; + input-enable; + }; + gpio126i_pins: gpio126i-pins { + pins = "GPIO126/SMB1BSDA"; + bias-disable; + input-enable; + }; + gpio127i_pins: gpio127i-pins { + pins = "GPIO127/SMB1BSCL"; + bias-disable; + input-enable; + }; + gpio136i_pins: gpio136i-pins { + pins = "GPIO136/SD1DT0"; + bias-disable; + input-enable; + }; + gpio137oh_pins: gpio137oh-pins { + pins = "GPIO137/SD1DT1"; + bias-disable; + output-high; + }; + gpio138i_pins: gpio138i-pins { + pins = "GPIO138/SD1DT2"; + bias-disable; + input-enable; + }; + gpio139i_pins: gpio139i-pins { + pins = "GPIO139/SD1DT3"; + bias-disable; + input-enable; + }; + gpio140i_pins: gpio140i-pins { + pins = "GPIO140/SD1CLK"; + bias-disable; + input-enable; + }; + gpio141i_pins: gpio141i-pins { + pins = "GPIO141/SD1WP"; + bias-disable; + input-enable; + }; + gpio190oh_pins: gpio190oh-pins { + pins = "GPIO190/nPRD_SMI"; + bias-disable; + output-high; + }; + gpio191oh_pins: gpio191oh-pins { + pins = "GPIO191"; + bias-disable; + output-high; + }; + gpio195ol_pins: gpio195ol-pins { + pins = "GPIO195/SMB0BSDA"; + bias-disable; + output-low; + }; + gpio196ol_pins: gpio196ol-pins { + pins = "GPIO196/SMB0CSCL"; + bias-disable; + output-low; + }; + gpio199i_pins: gpio199i-pins { + pins = "GPIO199/SMB0DSCL"; + bias-disable; + input-enable; + }; + gpio202ol_pins: gpio202ol-pins { + pins = "GPIO202/SMB0CSDA"; + bias-disable; + output-low; + }; + }; +}; + +&gmac0 { + phy-mode = "rgmii-id"; + snps,eee-force-disable; + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&fiu0 { + pinctrl-names = "default"; + pinctrl-0 = <&spi0cs1_pins>; + status = "okay"; + spi-nor@0 { + compatible = "jedec,spi-nor"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0>; + spi-max-frequency = <5000000>; + spi-rx-bus-width = <2>; + label = "bmc"; + partitions@80000000 { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + u-boot@0 { + label = "u-boot"; + reg = <0x0000000 0xC0000>; + read-only; + }; + u-boot-env@100000{ + label = "u-boot-env"; + reg = <0x00100000 0x40000>; + }; + kernel@200000 { + label = "kernel"; + reg = <0x0200000 0x600000>; + }; + rofs@800000 { + label = "rofs"; + reg = <0x800000 0x3500000>; + }; + rwfs@3d00000 { + label = "rwfs"; + reg = <0x3d00000 0x300000>; + }; + }; + }; + spi-nor@1 { + compatible = "jedec,spi-nor"; + #address-cells = <1>; + #size-cells = <1>; + reg = <1>; + spi-max-frequency = <5000000>; + spi-rx-bus-width = <2>; + partitions@88000000 { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + spare1@0 { + label = "spi0-cs1-spare1"; + reg = <0x0 0x800000>; + }; + spare2@800000 { + label = "spi0-cs1-spare2"; + reg = <0x800000 0x0>; + }; + }; + }; +}; + +&fiu3 { + pinctrl-0 = <&spi3_pins>; + spi-nor@0 { + compatible = "jedec,spi-nor"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0>; + spi-max-frequency = <5000000>; + spi-rx-bus-width = <2>; + partitions@A0000000 { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + system1@0 { + label = "bios"; + reg = <0x0 0x0>; + }; + system2@800000 { + label = "spi3-system2"; + reg = <0x800000 0x0>; + }; + }; + }; +}; + +&watchdog1 { + status = "okay"; +}; + +&rng { + status = "okay"; +}; + +&serial0 { + status = "okay"; +}; + +&serial1 { + status = "okay"; +}; + +&serial2 { + status = "okay"; +}; + +&serial3 { + status = "okay"; +}; + +&adc { + #io-channel-cells = <1>; + status = "okay"; +}; + +&i2c1 { + status = "okay"; + i2c-switch@75 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x75>; + i2c-mux-idle-disconnect; + + i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + + // Rear-Fan + max31790@58 { + compatible = "maxim,max31790"; + reg = <0x58>; + }; + }; + + i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + + // Mid-Fan + max31790@58 { + compatible = "maxim,max31790"; + reg = <0x58>; + }; + }; + + i2c-bus@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + + // INLET1_T + lm75@5c { + compatible = "ti,lm75"; + reg = <0x5c>; + }; + }; + + i2c-bus@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + + // OUTLET1_T + lm75@5c { + compatible = "ti,lm75"; + reg = <0x5c>; + }; + }; + + i2c-bus@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + + // OUTLET2_T + lm75@5c { + compatible = "ti,lm75"; + reg = <0x5c>; + }; + }; + + i2c-bus@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + + // OUTLET3_T + lm75@5c { + compatible = "ti,lm75"; + reg = <0x5c>; + }; + }; + }; + i2c-switch@77 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x77>; + i2c-mux-idle-disconnect; + + i2c-bus@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + + // STB-T + pmbus@74 { + compatible = "pmbus"; + reg = <0x74>; + }; + }; + }; +}; + +&i2c2 { + status = "okay"; + smpro@4f { + compatible = "ampere,smpro"; + reg = <0x4f>; + }; + + smpro@4e { + compatible = "ampere,smpro"; + reg = <0x4e>; + }; +}; + +&i2c3 { + status = "okay"; +}; + +&i2c4 { + status = "okay"; + i2c-switch@77 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x77>; + i2c-mux-idle-disconnect; + + i2c-bus@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + // ADC sensors + adm1266@40 { + compatible = "adi,adm1266"; + reg = <0x40>; + }; + }; + + i2c-bus@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + // ADC sensors + adm1266@41 { + compatible = "adi,adm1266"; + reg = <0x41>; + }; + }; + }; +}; + +&i2c5 { + status = "okay"; +}; + +&i2c6 { + status = "okay"; +}; + +&i2c7 { + status = "okay"; +}; + +&i2c8 { + status = "okay"; +}; + +&i2c9 { + status = "okay"; +}; + +&i2c10 { + status = "okay"; +}; + +&i2c11 { + status = "okay"; +}; + +&i2c12 { + status = "okay"; + ssif-bmc@10 { + compatible = "ssif-bmc"; + reg = <0x10>; + }; +}; + +&i2c13 { + status = "okay"; + i2c-switch@77 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x77>; + i2c-mux-idle-disconnect; + + i2c-bus@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + + // M2_ZONE_T + lm75@28 { + compatible = "ti,lm75"; + reg = <0x28>; + }; + }; + + i2c-bus@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + + // BATT_ZONE_T + lm75@29 { + compatible = "ti,lm75"; + reg = <0x29>; + }; + }; + + i2c-bus@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + + // NBM1_ZONE_T + lm75@28 { + compatible = "ti,lm75"; + reg = <0x28>; + }; + }; + i2c-bus@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + + // NBM2_ZONE_T + lm75@29 { + compatible = "ti,lm75"; + reg = <0x29>; + }; + }; + }; +}; + +&i2c14 { + status = "okay"; +}; + +&i2c15 { + status = "okay"; +}; + +&spi0 { + cs-gpios = <&gpio6 11 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&pinctrl { + pinctrl-names = "default"; + pinctrl-0 = < + &gpio61oh_pins + &gpio62oh_pins + &gpio161ol_pins + &gpio163i_pins + &gpio167ol_pins + &gpio95i_pins + &gpio65ol_pins + &gpio66oh_pins + &gpio67oh_pins + &gpio68ol_pins + &gpio69i_pins + &gpio70ol_pins + &gpio71i_pins + &gpio72i_pins + &gpio73i_pins + &gpio74i_pins + &gpio75i_pins + &gpio76i_pins + &gpio77i_pins + &gpio78i_pins + &gpio79ol_pins + &gpio80oh_pins + &gpio81i_pins + &gpio82i_pins + &gpio83i_pins + &gpio144i_pins + &gpio145i_pins + &gpio146i_pins + &gpio147oh_pins + &gpio168ol_pins + &gpio169oh_pins + &gpio170ol_pins + &gpio218oh_pins + &gpio37i_pins + &gpio38i_pins + &gpio39i_pins + &gpio40i_pins + &gpio121i_pins + &gpio122i_pins + &gpio123i_pins + &gpio124i_pins + &gpio125i_pins + &gpio126i_pins + &gpio127i_pins + &gpio136i_pins + &gpio137oh_pins + &gpio138i_pins + &gpio139i_pins + &gpio140i_pins + &gpio141i_pins + &gpio190oh_pins + &gpio191oh_pins + &gpio195ol_pins + &gpio196ol_pins + &gpio199i_pins + &gpio202ol_pins + >; +}; + +&gcr { + serial_port_mux: mux-controller { + compatible = "mmio-mux"; + #mux-control-cells = <1>; + + mux-reg-masks = <0x38 0x07>; + idle-states = <2>; + }; +}; From 3c5902d270edb6ccc3049acfe5d3e96653c87dcd Mon Sep 17 00:00:00 2001 From: Youling Tang Date: Sat, 14 Nov 2020 12:06:58 +0800 Subject: [PATCH 364/799] ARM: OMAP2+: Fix memleak in omap2xxx_clkt_vps_init If the clk_register fails, we should free hw before function returns to prevent memleak. Signed-off-by: Youling Tang Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c b/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c index 2a3e72286d3a..70892b3da28d 100644 --- a/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c +++ b/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c @@ -244,6 +244,12 @@ void omap2xxx_clkt_vps_init(void) hw->hw.init = &init; clk = clk_register(NULL, &hw->hw); + if (IS_ERR(clk)) { + printk(KERN_ERR "Failed to register clock\n"); + kfree(hw); + return; + } + clkdev_create(clk, "cpufreq_ck", NULL); return; cleanup: From c3f244d5776ecd236657fc1c4b7c5d1d4d01ca7e Mon Sep 17 00:00:00 2001 From: Youling Tang Date: Sat, 14 Nov 2020 12:07:20 +0800 Subject: [PATCH 365/799] ARM: OMAP2+: Fix kfree NULL pointer in omap2xxx_clkt_vps_init The returns pointer is NULL when kzalloc fails to apply for space, so fix kfree NULL pointer. Signed-off-by: Youling Tang Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c b/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c index 70892b3da28d..edf046b470ba 100644 --- a/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c +++ b/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c @@ -235,7 +235,7 @@ void omap2xxx_clkt_vps_init(void) hw = kzalloc(sizeof(*hw), GFP_KERNEL); if (!hw) - goto cleanup; + return; init.name = "virt_prcm_set"; init.ops = &virt_prcm_set_ops; init.parent_names = &parent_name; @@ -251,8 +251,5 @@ void omap2xxx_clkt_vps_init(void) } clkdev_create(clk, "cpufreq_ck", NULL); - return; -cleanup: - kfree(hw); } #endif From 6d9be9376b0e29211b6e6c1775ba6f81fb6c4ea5 Mon Sep 17 00:00:00 2001 From: Jing Xiangfeng Date: Sat, 19 Sep 2020 11:43:31 +0800 Subject: [PATCH 366/799] ARM: OMAP2+: Remove redundant assignment to variable ret The variable ret has been initialized with '-ENOMEM'. The assignment in the if branch is redundant. So remove it. Signed-off-by: Jing Xiangfeng Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/omap_device.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/arch/arm/mach-omap2/omap_device.c b/arch/arm/mach-omap2/omap_device.c index fc7bb2ca1672..f3191704cab9 100644 --- a/arch/arm/mach-omap2/omap_device.c +++ b/arch/arm/mach-omap2/omap_device.c @@ -334,10 +334,9 @@ struct omap_device *omap_device_alloc(struct platform_device *pdev, struct omap_hwmod **hwmods; od = kzalloc(sizeof(struct omap_device), GFP_KERNEL); - if (!od) { - ret = -ENOMEM; + if (!od) goto oda_exit1; - } + od->hwmods_cnt = oh_cnt; hwmods = kmemdup(ohs, sizeof(struct omap_hwmod *) * oh_cnt, GFP_KERNEL); From e106698cbb901d9b74dea4c9a3b5a7e6598ae481 Mon Sep 17 00:00:00 2001 From: Xu Wang Date: Wed, 4 Nov 2020 06:45:05 +0000 Subject: [PATCH 367/799] ARM: OMAP2+: Remove redundant null check before clk_prepare_enable/clk_disable_unprepare Because clk_prepare_enable() and clk_disable_unprepare() already checked NULL clock parameter, so the additional checks are unnecessary, just remove them. Signed-off-by: Xu Wang Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/display.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/arch/arm/mach-omap2/display.c b/arch/arm/mach-omap2/display.c index 2000fca6bd4e..6daaa645ae5d 100644 --- a/arch/arm/mach-omap2/display.c +++ b/arch/arm/mach-omap2/display.c @@ -385,8 +385,7 @@ int omap_dss_reset(struct omap_hwmod *oh) } for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++) - if (oc->_clk) - clk_prepare_enable(oc->_clk); + clk_prepare_enable(oc->_clk); dispc_disable_outputs(); @@ -412,8 +411,7 @@ int omap_dss_reset(struct omap_hwmod *oh) pr_debug("dss_core: softreset done\n"); for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++) - if (oc->_clk) - clk_disable_unprepare(oc->_clk); + clk_disable_unprepare(oc->_clk); r = (c == MAX_MODULE_SOFTRESET_WAIT) ? -ETIMEDOUT : 0; From 2e023b938048c9857af09b96ce672e9a31dbfb38 Mon Sep 17 00:00:00 2001 From: Tang Bin Date: Thu, 10 Sep 2020 19:06:40 +0800 Subject: [PATCH 368/799] ARM: OMAP1: clock: Use IS_ERR_OR_NULL() to clean code Use IS_ERR_OR_NULL() to make the code cleaner. Signed-off-by: Zhang Shengju Signed-off-by: Tang Bin Signed-off-by: Tony Lindgren --- arch/arm/mach-omap1/clock.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/arch/arm/mach-omap1/clock.c b/arch/arm/mach-omap1/clock.c index bd5be82101f3..9d4a0ab50a46 100644 --- a/arch/arm/mach-omap1/clock.c +++ b/arch/arm/mach-omap1/clock.c @@ -612,7 +612,7 @@ int clk_enable(struct clk *clk) unsigned long flags; int ret; - if (clk == NULL || IS_ERR(clk)) + if (IS_ERR_OR_NULL(clk)) return -EINVAL; spin_lock_irqsave(&clockfw_lock, flags); @@ -627,7 +627,7 @@ void clk_disable(struct clk *clk) { unsigned long flags; - if (clk == NULL || IS_ERR(clk)) + if (IS_ERR_OR_NULL(clk)) return; spin_lock_irqsave(&clockfw_lock, flags); @@ -650,7 +650,7 @@ unsigned long clk_get_rate(struct clk *clk) unsigned long flags; unsigned long ret; - if (clk == NULL || IS_ERR(clk)) + if (IS_ERR_OR_NULL(clk)) return 0; spin_lock_irqsave(&clockfw_lock, flags); @@ -670,7 +670,7 @@ long clk_round_rate(struct clk *clk, unsigned long rate) unsigned long flags; long ret; - if (clk == NULL || IS_ERR(clk)) + if (IS_ERR_OR_NULL(clk)) return 0; spin_lock_irqsave(&clockfw_lock, flags); @@ -686,7 +686,7 @@ int clk_set_rate(struct clk *clk, unsigned long rate) unsigned long flags; int ret = -EINVAL; - if (clk == NULL || IS_ERR(clk)) + if (IS_ERR_OR_NULL(clk)) return ret; spin_lock_irqsave(&clockfw_lock, flags); @@ -791,7 +791,7 @@ void clk_preinit(struct clk *clk) int clk_register(struct clk *clk) { - if (clk == NULL || IS_ERR(clk)) + if (IS_ERR_OR_NULL(clk)) return -EINVAL; /* @@ -817,7 +817,7 @@ EXPORT_SYMBOL(clk_register); void clk_unregister(struct clk *clk) { - if (clk == NULL || IS_ERR(clk)) + if (IS_ERR_OR_NULL(clk)) return; mutex_lock(&clocks_mutex); From bb74fdbd8a6c4eb6da18cef9c65da755b4ae5bcb Mon Sep 17 00:00:00 2001 From: Eddie James Date: Mon, 2 Nov 2020 13:47:13 -0600 Subject: [PATCH 369/799] ARM: dts: aspeed: rainier: Mark FSI SPI controllers as restricted Some of the FSI-attached SPI controllers can't use the loop command due to security requirements. Indicate this in the devicetree with the restricted compatible string. Signed-off-by: Eddie James Link: https://lore.kernel.org/r/20201102194713.14812-1-eajames@linux.ibm.com Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts b/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts index 63123bf137e3..4985473a3e2d 100644 --- a/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts +++ b/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts @@ -267,6 +267,7 @@ cfam0_spi2: spi@40 { reg = <0x40>; + compatible = "ibm,fsi2spi-restricted"; #address-cells = <1>; #size-cells = <0>; @@ -283,6 +284,7 @@ cfam0_spi3: spi@60 { reg = <0x60>; + compatible = "ibm,fsi2spi-restricted"; #address-cells = <1>; #size-cells = <0>; @@ -379,6 +381,7 @@ cfam1_spi2: spi@40 { reg = <0x40>; + compatible = "ibm,fsi2spi-restricted"; #address-cells = <1>; #size-cells = <0>; @@ -395,6 +398,7 @@ cfam1_spi3: spi@60 { reg = <0x60>; + compatible = "ibm,fsi2spi-restricted"; #address-cells = <1>; #size-cells = <0>; @@ -489,6 +493,7 @@ cfam2_spi2: spi@40 { reg = <0x40>; + compatible = "ibm,fsi2spi-restricted"; #address-cells = <1>; #size-cells = <0>; @@ -505,6 +510,7 @@ cfam2_spi3: spi@60 { reg = <0x60>; + compatible = "ibm,fsi2spi-restricted"; #address-cells = <1>; #size-cells = <0>; From c680dd4e60456305434bb6babc36804d1301e0ff Mon Sep 17 00:00:00 2001 From: Andrew Jeffery Date: Fri, 2 Oct 2020 16:04:14 +0930 Subject: [PATCH 370/799] ARM: dts: aspeed: rainier: Don't shout addresses Make them lowercase. Signed-off-by: Andrew Jeffery Reviewed-by: Joel Stanley Link: https://lore.kernel.org/r/20201002063414.275161-4-andrew@aj.id.au Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts b/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts index 4985473a3e2d..a4b77aec5424 100644 --- a/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts +++ b/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts @@ -47,9 +47,9 @@ #size-cells = <1>; ranges; - flash_memory: region@B8000000 { + flash_memory: region@b8000000 { no-map; - reg = <0xB8000000 0x04000000>; /* 64M */ + reg = <0xb8000000 0x04000000>; /* 64M */ }; ramoops@bc000000 { From 2ba56f464f0c1a7264160f8675063b3df92e7966 Mon Sep 17 00:00:00 2001 From: Joel Stanley Date: Thu, 11 Jun 2020 11:04:33 +0930 Subject: [PATCH 371/799] ARM: dts: aspeed: ast2600evb: Add MAC0 MAC0 was not functional in the AST2600A0 SoC. This has been resolved with the A1, so allow use of this port on EVBs with the A1 and subsequent revisions. A0 EVBs will still boot with this change, but the first Ethernet device will not be functional. Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-ast2600-evb.dts | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm/boot/dts/aspeed-ast2600-evb.dts b/arch/arm/boot/dts/aspeed-ast2600-evb.dts index 8d0f4656aa05..89be13197780 100644 --- a/arch/arm/boot/dts/aspeed-ast2600-evb.dts +++ b/arch/arm/boot/dts/aspeed-ast2600-evb.dts @@ -23,6 +23,15 @@ }; }; +&mdio0 { + status = "okay"; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + }; +}; + &mdio1 { status = "okay"; @@ -50,6 +59,17 @@ }; }; +&mac0 { + status = "okay"; + + phy-mode = "rgmii"; + phy-handle = <ðphy0>; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rgmii1_default>; +}; + + &mac1 { status = "okay"; From 91ccc45d1ec4d08851de004eb5d68c67e1232694 Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Wed, 18 Nov 2020 08:25:28 -0800 Subject: [PATCH 372/799] arm64: defconfig: Enable QCOM_SCM as builtin The Qualcomm SCM driver was never explicitly enabled in the defconfig. Instead it was (apparently) selected by DRM_MSM and by the recent change to make it tristate now became =m. Unfortunately this removes the ability for PINCTRL_MSM and ARM_SMMU to be =y and with deferred_probe_timeout defaulting to 0 this means that things such as UART, USB, PCIe and SDHCI probes with their dependencies ignored. The lack of pinctrl results in invalid pin configuration and the lack of iommu results in the system locking up as soon as any form of data transfer is attempted from any of the affected peripherals. Mark QCOM_SCM as builtin, to avoid this. Reviewed-by: Vinod Koul Cc: John Stultz Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20201118162528.454729-1-bjorn.andersson@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index ed8b7df52abf..d88803191e7f 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -99,6 +99,7 @@ CONFIG_ARM_SCPI_PROTOCOL=y CONFIG_RASPBERRYPI_FIRMWARE=y CONFIG_INTEL_STRATIX10_SERVICE=y CONFIG_INTEL_STRATIX10_RSU=m +CONFIG_QCOM_SCM=y CONFIG_EFI_CAPSULE_LOADER=y CONFIG_IMX_SCU=y CONFIG_IMX_SCU_PD=y From bb1f7cf68a2d47c5008050177884be9662673537 Mon Sep 17 00:00:00 2001 From: Souradeep Chowdhury Date: Wed, 30 Sep 2020 13:44:14 +0530 Subject: [PATCH 373/799] arm64: dts: qcom: sm8150: Add LLC support for sm8150 Add LLCC system cache controller entry for sm8150 to support sm8150 for LLCC. Signed-off-by: Souradeep Chowdhury Link: https://lore.kernel.org/r/8f0e818485941076d62a8dc9f711b0fb868ba080.1601452132.git.schowdhu@codeaurora.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8150.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi index f0a872e02686..838586140c48 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -490,6 +490,13 @@ qcom,bcm-voters = <&apps_bcm_voter>; }; + system-cache-controller@9200000 { + compatible = "qcom,sm8150-llcc"; + reg = <0 0x09200000 0 0x200000>, <0 0x09600000 0 0x50000>; + reg-names = "llcc_base", "llcc_broadcast_base"; + interrupts = ; + }; + ufs_mem_hc: ufshc@1d84000 { compatible = "qcom,sm8150-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; From 4815623259f533aec4513c72da20a0ac1c80233b Mon Sep 17 00:00:00 2001 From: Jonathan Marek Date: Tue, 9 Jun 2020 15:40:21 -0400 Subject: [PATCH 374/799] arm64: dts: qcom: sm8150: add apps_smmu node Add the apps_smmu node for sm8150. For UFS, now that the kernel initializes the iommu, the stream mappings set by the bootloader are cleared. Adding the iommus property is required so that new mappings are created for UFS. Signed-off-by: Jonathan Marek Reviewed-by: Sai Prakash Ranjan Tested-by: Sai Prakash Ranjan Link: https://lore.kernel.org/r/20200609194030.17756-4-jonathan@marek.ca Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8150.dtsi | 91 ++++++++++++++++++++++++++++ 1 file changed, 91 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi index 838586140c48..0d932c7d5e95 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -509,6 +509,8 @@ resets = <&gcc GCC_UFS_PHY_BCR>; reset-names = "rst"; + iommus = <&apps_smmu 0x300 0>; + clock-names = "core_clk", "bus_aggr_clk", @@ -929,6 +931,7 @@ compatible = "snps,dwc3"; reg = <0 0x0a600000 0 0xcd00>; interrupts = ; + iommus = <&apps_smmu 0x140 0>; snps,dis_u2_susphy_quirk; snps,dis_enblslpm_quirk; phys = <&usb_1_hsphy>, <&usb_1_ssphy>; @@ -994,6 +997,94 @@ cell-index = <0>; }; + apps_smmu: iommu@15000000 { + compatible = "qcom,sm8150-smmu-500", "arm,mmu-500"; + reg = <0 0x15000000 0 0x100000>; + #iommu-cells = <2>; + #global-interrupts = <1>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + remoteproc_adsp: remoteproc@17300000 { compatible = "qcom,sm8150-adsp-pas"; reg = <0x0 0x17300000 0x0 0x4040>; From a89441fcd09d754439ad37c9e804f9232cba8223 Mon Sep 17 00:00:00 2001 From: Jonathan Marek Date: Tue, 9 Jun 2020 15:40:22 -0400 Subject: [PATCH 375/799] arm64: dts: qcom: sm8250: add apps_smmu node Add the apps_smmu node for sm8250. For UFS, now that the kernel initializes the iommu, the stream mappings set by the bootloader are cleared. Adding the iommus property is required so that new mappings are created for UFS. Signed-off-by: Jonathan Marek Link: https://lore.kernel.org/r/20200609194030.17756-5-jonathan@marek.ca Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 107 +++++++++++++++++++++++++++ 1 file changed, 107 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index d057d85a19fb..457c3e65c0b6 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -1172,6 +1172,8 @@ power-domains = <&gcc UFS_PHY_GDSC>; + iommus = <&apps_smmu 0x0e0 0>, <&apps_smmu 0x4e0 0>; + clock-names = "core_clk", "bus_aggr_clk", @@ -2156,6 +2158,111 @@ }; }; + apps_smmu: iommu@15000000 { + compatible = "qcom,sm8250-smmu-500", "arm,mmu-500"; + reg = <0 0x15000000 0 0x100000>; + #iommu-cells = <2>; + #global-interrupts = <2>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + adsp: remoteproc@17300000 { compatible = "qcom,sm8250-adsp-pas"; reg = <0 0x17300000 0 0x100>; From 358afb8b746d4a7ebaeeeaab7a1523895a8572c2 Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Thu, 29 Oct 2020 14:40:18 +0100 Subject: [PATCH 376/799] ARM: dts: rpi-4: disable wifi frequencies The RPi4 WiFi chip and HDMI outputs have some frequency overlap with crosstalk around 2.4GHz. Let's mark it as such so we can use some evasive maneuvers. Signed-off-by: Maxime Ripard Signed-off-by: Nicolas Saenz Julienne Link: https://lore.kernel.org/r/20201029134018.1948636-3-maxime@cerno.tech --- arch/arm/boot/dts/bcm2711-rpi-4-b.dts | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/bcm2711-rpi-4-b.dts b/arch/arm/boot/dts/bcm2711-rpi-4-b.dts index 09a1182c2936..403bacf986eb 100644 --- a/arch/arm/boot/dts/bcm2711-rpi-4-b.dts +++ b/arch/arm/boot/dts/bcm2711-rpi-4-b.dts @@ -181,12 +181,14 @@ &hdmi0 { clocks = <&firmware_clocks 13>, <&firmware_clocks 14>, <&dvp 0>, <&clk_27MHz>; clock-names = "hdmi", "bvb", "audio", "cec"; + wifi-2.4ghz-coexistence; status = "okay"; }; &hdmi1 { clocks = <&firmware_clocks 13>, <&firmware_clocks 14>, <&dvp 1>, <&clk_27MHz>; clock-names = "hdmi", "bvb", "audio", "cec"; + wifi-2.4ghz-coexistence; status = "okay"; }; From 278407a53c3b33fb820332c4d39eb39316c3879a Mon Sep 17 00:00:00 2001 From: Pavel Hofman Date: Fri, 20 Nov 2020 17:39:20 +0100 Subject: [PATCH 377/799] ARM: dts: bcm283x: increase dwc2's RX FIFO size The previous version of the dwc2 overlay set the RX FIFO size to 256 4-byte words. This is not enough for 1024 bytes of the largest isochronous high speed packet allowed, because it doesn't take into account extra space needed by dwc2. RX FIFO's size is calculated based on the following (in 4byte words): - 13 locations for SETUP packets 5*n + 8 for Slave and Buffer DMA mode where n is number of control endpoints which is 1 on the bcm283x core - 1 location for Global OUT NAK - 2 * 257 locations for status information and the received packet. Typically two spaces are recommended so that when the previous packet is being transferred to AHB, the USB can receive the subsequent packet. - 10 * 1 location for transfer complete status for last packet of each endpoint. The bcm283x core has 5 IN and 5 OUT EPs - 10 * 1 additional location for EPDisable status for each endpoint - 5 * 2 additional locations are recommended for each OUT endpoint Total is 558 locations. Signed-off-by: Phil Elwell Signed-off-by: Pavel Hofman Signed-off-by: Nicolas Saenz Julienne Link: https://lore.kernel.org/r/e9e7d070-593c-122f-3a5c-2435bb147ab2@ivitera.com/ --- arch/arm/boot/dts/bcm283x-rpi-usb-otg.dtsi | 2 +- arch/arm/boot/dts/bcm283x-rpi-usb-peripheral.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/bcm283x-rpi-usb-otg.dtsi b/arch/arm/boot/dts/bcm283x-rpi-usb-otg.dtsi index e2fd9610e125..20322de2f8bf 100644 --- a/arch/arm/boot/dts/bcm283x-rpi-usb-otg.dtsi +++ b/arch/arm/boot/dts/bcm283x-rpi-usb-otg.dtsi @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 &usb { dr_mode = "otg"; - g-rx-fifo-size = <256>; + g-rx-fifo-size = <558>; g-np-tx-fifo-size = <32>; /* * According to dwc2 the sum of all device EP diff --git a/arch/arm/boot/dts/bcm283x-rpi-usb-peripheral.dtsi b/arch/arm/boot/dts/bcm283x-rpi-usb-peripheral.dtsi index 0ff0e9e25327..1409d1b559c1 100644 --- a/arch/arm/boot/dts/bcm283x-rpi-usb-peripheral.dtsi +++ b/arch/arm/boot/dts/bcm283x-rpi-usb-peripheral.dtsi @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 &usb { dr_mode = "peripheral"; - g-rx-fifo-size = <256>; + g-rx-fifo-size = <558>; g-np-tx-fifo-size = <32>; g-tx-fifo-size = <256 256 512 512 512 768 768>; }; From 3e95dfb315de27bb6c6d7012659e396eb5b91e5e Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Fri, 20 Nov 2020 15:37:44 -0600 Subject: [PATCH 378/799] dt-bindings: Don't error out on yamllint and dt-doc-validate errors A broken schema file now causes make to exit and 'make -k' no longer works now that dt-doc-validate is called from a single make rule. As yamllint is optional, we shouldn't stop on yamllint errors either. Also, it seems some old versions of yamllint don't work. Signed-off-by: Rob Herring --- Documentation/devicetree/bindings/Makefile | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/Makefile b/Documentation/devicetree/bindings/Makefile index f50420099a55..285d814369db 100644 --- a/Documentation/devicetree/bindings/Makefile +++ b/Documentation/devicetree/bindings/Makefile @@ -27,12 +27,12 @@ find_cmd = find $(srctree)/$(src) \( -name '*.yaml' ! \ -name '*.example.dt.yaml' \) quiet_cmd_yamllint = LINT $(src) - cmd_yamllint = $(find_cmd) | \ - xargs $(DT_SCHEMA_LINT) -f parsable -c $(srctree)/$(src)/.yamllint + cmd_yamllint = ($(find_cmd) | \ + xargs $(DT_SCHEMA_LINT) -f parsable -c $(srctree)/$(src)/.yamllint) || true quiet_cmd_chk_bindings = CHKDT $@ - cmd_chk_bindings = $(find_cmd) | \ - xargs -n200 -P$$(nproc) $(DT_DOC_CHECKER) -u $(srctree)/$(src) + cmd_chk_bindings = ($(find_cmd) | \ + xargs -n200 -P$$(nproc) $(DT_DOC_CHECKER) -u $(srctree)/$(src)) || true quiet_cmd_mk_schema = SCHEMA $@ cmd_mk_schema = f=$$(mktemp) ; \ From 91d1d92a89e0865c5b0cf76605f2f1581f3f0904 Mon Sep 17 00:00:00 2001 From: Florian Fainelli Date: Mon, 9 Nov 2020 11:38:04 -0800 Subject: [PATCH 379/799] dt-bindings: net: dsa: Extend switch nodes pattern Upon discussion with Kurt, Rob and Vladimir it appears that we should be allowing ethernet-switch as a node name, update dsa.yaml accordingly. Reviewed-by: Vladimir Oltean Acked-by: Rob Herring Signed-off-by: Florian Fainelli --- Documentation/devicetree/bindings/net/dsa/dsa.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/net/dsa/dsa.yaml b/Documentation/devicetree/bindings/net/dsa/dsa.yaml index a765ceba28c6..5f8f5177938a 100644 --- a/Documentation/devicetree/bindings/net/dsa/dsa.yaml +++ b/Documentation/devicetree/bindings/net/dsa/dsa.yaml @@ -20,7 +20,7 @@ select: false properties: $nodename: - pattern: "^switch(@.*)?$" + pattern: "^(ethernet-)?switch(@.*)?$" dsa,member: minItems: 2 From d2868fc9335c7ec557fe6ec7e485a32bb610e9dc Mon Sep 17 00:00:00 2001 From: Florian Fainelli Date: Mon, 9 Nov 2020 19:12:26 -0800 Subject: [PATCH 380/799] dt-bindings: net: dsa: Document sfp and managed properties The 'sfp' and 'managed' properties are commonly used to describe Ethernet switch ports connecting to SFP/SFF cages, describe these two properties as valid that we inherit from ethernet-controller.yaml. Acked-by: Rob Herring Signed-off-by: Florian Fainelli --- Documentation/devicetree/bindings/net/dsa/dsa.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/net/dsa/dsa.yaml b/Documentation/devicetree/bindings/net/dsa/dsa.yaml index 5f8f5177938a..8e044631bcf7 100644 --- a/Documentation/devicetree/bindings/net/dsa/dsa.yaml +++ b/Documentation/devicetree/bindings/net/dsa/dsa.yaml @@ -78,6 +78,10 @@ patternProperties: mac-address: true + sfp: true + + managed: true + required: - reg From f527cb6f3345f7faa8e61dd9f3c437437327428c Mon Sep 17 00:00:00 2001 From: Florian Fainelli Date: Mon, 9 Nov 2020 11:41:01 -0800 Subject: [PATCH 381/799] ARM: dts: BCM5301X: Update Ethernet switch node name Update the switch unit name from srab to ethernet-switch, allowing us to fix warnings such as: CHECK arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dt.yaml arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dt.yaml: srab@18007000: $nodename:0: 'srab@18007000' does not match '^(ethernet-)?switch(@.*)?$' From schema: Documentation/devicetree/bindings/net/dsa/b53.yaml Reviewed-by: Vladimir Oltean Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm5301x.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/bcm5301x.dtsi b/arch/arm/boot/dts/bcm5301x.dtsi index 90c09c48721b..b8d2e8d28482 100644 --- a/arch/arm/boot/dts/bcm5301x.dtsi +++ b/arch/arm/boot/dts/bcm5301x.dtsi @@ -483,7 +483,7 @@ }; }; - srab: srab@18007000 { + srab: ethernet-switch@18007000 { compatible = "brcm,bcm5301x-srab"; reg = <0x18007000 0x1000>; From 953efcb0c0234f8c488ebd4090378e949d6ba78b Mon Sep 17 00:00:00 2001 From: Florian Fainelli Date: Mon, 9 Nov 2020 16:42:09 -0800 Subject: [PATCH 382/799] ARM: dts: BCM5301X: Add a default compatible for switch node MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Provide a default compatible string which is based on the 53011 SRAB compatible by default. The 4709 and 47094 default to the 53012 SRAB compatible. This allows us to have sane defaults and silences the following warnings: arch/arm/boot/dts/bcm4708-asus-rt-ac56u.dt.yaml: ethernet-switch@18007000: compatible: 'oneOf' conditional failed, one must be fixed: ['brcm,bcm5301x-srab'] is too short 'brcm,bcm5325' was expected 'brcm,bcm53115' was expected 'brcm,bcm53125' was expected 'brcm,bcm53128' was expected 'brcm,bcm5365' was expected 'brcm,bcm5395' was expected 'brcm,bcm5389' was expected 'brcm,bcm5397' was expected 'brcm,bcm5398' was expected 'brcm,bcm11360-srab' was expected 'brcm,bcm5301x-srab' is not one of ['brcm,bcm53010-srab', 'brcm,bcm53011-srab', 'brcm,bcm53012-srab', 'brcm,bcm53018-srab', 'brcm,bcm53019-srab'] 'brcm,bcm5301x-srab' is not one of ['brcm,bcm11404-srab', 'brcm,bcm11407-srab', 'brcm,bcm11409-srab', 'brcm,bcm58310-srab', 'brcm,bcm58311-srab', 'brcm,bcm58313-srab'] 'brcm,bcm5301x-srab' is not one of ['brcm,bcm58522-srab', 'brcm,bcm58523-srab', 'brcm,bcm58525-srab', 'brcm,bcm58622-srab', 'brcm,bcm58623-srab', 'brcm,bcm58625-srab', 'brcm,bcm88312-srab'] 'brcm,bcm5301x-srab' is not one of ['brcm,bcm3384-switch', 'brcm,bcm6328-switch', 'brcm,bcm6368-switch'] From schema: Documentation/devicetree/bindings/net/dsa/b53.yaml Acked-by: Rafał Miłecki Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm4709.dtsi | 4 ++++ arch/arm/boot/dts/bcm47094.dtsi | 4 ++++ arch/arm/boot/dts/bcm5301x.dtsi | 2 +- 3 files changed, 9 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/bcm4709.dtsi b/arch/arm/boot/dts/bcm4709.dtsi index e1bb8661955f..cba3d910bed8 100644 --- a/arch/arm/boot/dts/bcm4709.dtsi +++ b/arch/arm/boot/dts/bcm4709.dtsi @@ -9,3 +9,7 @@ clock-frequency = <125000000>; status = "okay"; }; + +&srab { + compatible = "brcm,bcm53012-srab", "brcm,bcm5301x-srab"; +}; diff --git a/arch/arm/boot/dts/bcm47094.dtsi b/arch/arm/boot/dts/bcm47094.dtsi index 747ca030435f..2a8f7312d1be 100644 --- a/arch/arm/boot/dts/bcm47094.dtsi +++ b/arch/arm/boot/dts/bcm47094.dtsi @@ -25,3 +25,7 @@ clock-frequency = <125000000>; status = "okay"; }; + +&srab { + compatible = "brcm,bcm53012-srab", "brcm,bcm5301x-srab"; +}; diff --git a/arch/arm/boot/dts/bcm5301x.dtsi b/arch/arm/boot/dts/bcm5301x.dtsi index b8d2e8d28482..a4ab3aabf8b0 100644 --- a/arch/arm/boot/dts/bcm5301x.dtsi +++ b/arch/arm/boot/dts/bcm5301x.dtsi @@ -484,7 +484,7 @@ }; srab: ethernet-switch@18007000 { - compatible = "brcm,bcm5301x-srab"; + compatible = "brcm,bcm53011-srab", "brcm,bcm5301x-srab"; reg = <0x18007000 0x1000>; status = "disabled"; From fd577b41421bc24e2d04cab96d387301b649eb14 Mon Sep 17 00:00:00 2001 From: Florian Fainelli Date: Mon, 9 Nov 2020 17:20:17 -0800 Subject: [PATCH 383/799] ARM: dts: BCM5301X: Provide defaults ports container node MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Provide an empty 'ports' container node with the correct #address-cells and #size-cells properties. This silences the following warning: arch/arm/boot/dts/bcm4708-asus-rt-ac56u.dt.yaml: ethernet-switch@18007000: 'oneOf' conditional failed, one must be fixed: 'ports' is a required property 'ethernet-ports' is a required property From schema: Documentation/devicetree/bindings/net/dsa/b53.yaml Acked-by: Rafał Miłecki Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm4708-luxul-xap-1510.dts | 3 --- arch/arm/boot/dts/bcm4708-luxul-xwc-1000.dts | 3 --- arch/arm/boot/dts/bcm4708-smartrg-sr400ac.dts | 3 --- arch/arm/boot/dts/bcm47081-luxul-xap-1410.dts | 3 --- arch/arm/boot/dts/bcm47081-luxul-xwr-1200.dts | 3 --- arch/arm/boot/dts/bcm47094-linksys-panamera.dts | 3 --- arch/arm/boot/dts/bcm47094-luxul-xap-1610.dts | 3 --- arch/arm/boot/dts/bcm47094-luxul-xwc-2000.dts | 3 --- arch/arm/boot/dts/bcm47094-luxul-xwr-3100.dts | 3 --- arch/arm/boot/dts/bcm47094-luxul-xwr-3150-v1.dts | 3 --- arch/arm/boot/dts/bcm5301x.dtsi | 4 ++++ arch/arm/boot/dts/bcm953012er.dts | 3 --- 12 files changed, 4 insertions(+), 33 deletions(-) diff --git a/arch/arm/boot/dts/bcm4708-luxul-xap-1510.dts b/arch/arm/boot/dts/bcm4708-luxul-xap-1510.dts index 7f07b78c1ac3..5b4a481be4f4 100644 --- a/arch/arm/boot/dts/bcm4708-luxul-xap-1510.dts +++ b/arch/arm/boot/dts/bcm4708-luxul-xap-1510.dts @@ -61,9 +61,6 @@ status = "okay"; ports { - #address-cells = <1>; - #size-cells = <0>; - port@0 { reg = <0>; label = "poe"; diff --git a/arch/arm/boot/dts/bcm4708-luxul-xwc-1000.dts b/arch/arm/boot/dts/bcm4708-luxul-xwc-1000.dts index 548faa0c44c8..8636600385fd 100644 --- a/arch/arm/boot/dts/bcm4708-luxul-xwc-1000.dts +++ b/arch/arm/boot/dts/bcm4708-luxul-xwc-1000.dts @@ -68,9 +68,6 @@ status = "okay"; ports { - #address-cells = <1>; - #size-cells = <0>; - port@4 { reg = <4>; label = "lan"; diff --git a/arch/arm/boot/dts/bcm4708-smartrg-sr400ac.dts b/arch/arm/boot/dts/bcm4708-smartrg-sr400ac.dts index abd35a518046..51c64f0b2560 100644 --- a/arch/arm/boot/dts/bcm4708-smartrg-sr400ac.dts +++ b/arch/arm/boot/dts/bcm4708-smartrg-sr400ac.dts @@ -122,9 +122,6 @@ status = "okay"; ports { - #address-cells = <1>; - #size-cells = <0>; - port@0 { reg = <0>; label = "lan4"; diff --git a/arch/arm/boot/dts/bcm47081-luxul-xap-1410.dts b/arch/arm/boot/dts/bcm47081-luxul-xap-1410.dts index 944e81cab338..68aaf0af3945 100644 --- a/arch/arm/boot/dts/bcm47081-luxul-xap-1410.dts +++ b/arch/arm/boot/dts/bcm47081-luxul-xap-1410.dts @@ -61,9 +61,6 @@ status = "okay"; ports { - #address-cells = <1>; - #size-cells = <0>; - port@4 { reg = <4>; label = "poe"; diff --git a/arch/arm/boot/dts/bcm47081-luxul-xwr-1200.dts b/arch/arm/boot/dts/bcm47081-luxul-xwr-1200.dts index d1ae7dc10775..432254383769 100644 --- a/arch/arm/boot/dts/bcm47081-luxul-xwr-1200.dts +++ b/arch/arm/boot/dts/bcm47081-luxul-xwr-1200.dts @@ -109,9 +109,6 @@ status = "okay"; ports { - #address-cells = <1>; - #size-cells = <0>; - port@0 { reg = <0>; label = "lan4"; diff --git a/arch/arm/boot/dts/bcm47094-linksys-panamera.dts b/arch/arm/boot/dts/bcm47094-linksys-panamera.dts index 3bb3fe5bfbf8..3725f2b0d60b 100644 --- a/arch/arm/boot/dts/bcm47094-linksys-panamera.dts +++ b/arch/arm/boot/dts/bcm47094-linksys-panamera.dts @@ -201,9 +201,6 @@ dsa,member = <0 0>; ports { - #address-cells = <1>; - #size-cells = <0>; - port@1 { reg = <1>; label = "lan7"; diff --git a/arch/arm/boot/dts/bcm47094-luxul-xap-1610.dts b/arch/arm/boot/dts/bcm47094-luxul-xap-1610.dts index 068e384b8ab7..6fa101f0a90d 100644 --- a/arch/arm/boot/dts/bcm47094-luxul-xap-1610.dts +++ b/arch/arm/boot/dts/bcm47094-luxul-xap-1610.dts @@ -59,9 +59,6 @@ status = "okay"; ports { - #address-cells = <1>; - #size-cells = <0>; - port@0 { reg = <0>; label = "poe"; diff --git a/arch/arm/boot/dts/bcm47094-luxul-xwc-2000.dts b/arch/arm/boot/dts/bcm47094-luxul-xwc-2000.dts index 9ae815ddbb4b..4f8d777ae18d 100644 --- a/arch/arm/boot/dts/bcm47094-luxul-xwc-2000.dts +++ b/arch/arm/boot/dts/bcm47094-luxul-xwc-2000.dts @@ -57,9 +57,6 @@ status = "okay"; ports { - #address-cells = <1>; - #size-cells = <0>; - port@0 { reg = <0>; label = "lan"; diff --git a/arch/arm/boot/dts/bcm47094-luxul-xwr-3100.dts b/arch/arm/boot/dts/bcm47094-luxul-xwr-3100.dts index a21b2d185596..e17e9a17fb00 100644 --- a/arch/arm/boot/dts/bcm47094-luxul-xwr-3100.dts +++ b/arch/arm/boot/dts/bcm47094-luxul-xwr-3100.dts @@ -108,9 +108,6 @@ status = "okay"; ports { - #address-cells = <1>; - #size-cells = <0>; - port@0 { reg = <0>; label = "lan4"; diff --git a/arch/arm/boot/dts/bcm47094-luxul-xwr-3150-v1.dts b/arch/arm/boot/dts/bcm47094-luxul-xwr-3150-v1.dts index a361aa8627d3..60cc87ecc7ec 100644 --- a/arch/arm/boot/dts/bcm47094-luxul-xwr-3150-v1.dts +++ b/arch/arm/boot/dts/bcm47094-luxul-xwr-3150-v1.dts @@ -83,9 +83,6 @@ status = "okay"; ports { - #address-cells = <1>; - #size-cells = <0>; - port@0 { reg = <0>; label = "lan4"; diff --git a/arch/arm/boot/dts/bcm5301x.dtsi b/arch/arm/boot/dts/bcm5301x.dtsi index a4ab3aabf8b0..7db72a2f1020 100644 --- a/arch/arm/boot/dts/bcm5301x.dtsi +++ b/arch/arm/boot/dts/bcm5301x.dtsi @@ -490,6 +490,10 @@ status = "disabled"; /* ports are defined in board DTS */ + ports { + #address-cells = <1>; + #size-cells = <0>; + }; }; rng: rng@18004000 { diff --git a/arch/arm/boot/dts/bcm953012er.dts b/arch/arm/boot/dts/bcm953012er.dts index 957468224622..52feca0fb906 100644 --- a/arch/arm/boot/dts/bcm953012er.dts +++ b/arch/arm/boot/dts/bcm953012er.dts @@ -69,9 +69,6 @@ status = "okay"; ports { - #address-cells = <1>; - #size-cells = <0>; - port@0 { reg = <0>; label = "port0"; From fd66cd0d79cb836badecb91fdd19afd32afbb443 Mon Sep 17 00:00:00 2001 From: Florian Fainelli Date: Mon, 9 Nov 2020 12:02:08 -0800 Subject: [PATCH 384/799] ARM: dts: NSP: Update ethernet switch node name Update the switch unit name from srab to ethernet-switch, allowing us to fix warnings such as: CHECK arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dt.yaml arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dt.yaml: srab@18007000: $nodename:0: 'srab@18007000' does not match '^(ethernet-)?switch(@.*)?$' From schema: Documentation/devicetree/bindings/net/dsa/b53.yaml Reviewed-by: Vladimir Oltean Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm-nsp.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/bcm-nsp.dtsi b/arch/arm/boot/dts/bcm-nsp.dtsi index e895f7cb8c9f..e7d08959d5fe 100644 --- a/arch/arm/boot/dts/bcm-nsp.dtsi +++ b/arch/arm/boot/dts/bcm-nsp.dtsi @@ -385,7 +385,7 @@ clock-names = "apb_pclk"; }; - srab: srab@36000 { + srab: ethernet-switch@36000 { compatible = "brcm,nsp-srab"; reg = <0x36000 0x1000>, <0x3f308 0x8>, From 8b0235d1deace8f1bd8cdd149d698fee3974fdf4 Mon Sep 17 00:00:00 2001 From: Florian Fainelli Date: Mon, 9 Nov 2020 12:06:15 -0800 Subject: [PATCH 385/799] ARM: dts: NSP: Fix Ethernet switch SGMII register name The register name should be "sgmii_config", not "sgmii", this is not a functional change since no code is currently looking for that register by name (or at all). Reviewed-by: Vladimir Oltean Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm-nsp.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/bcm-nsp.dtsi b/arch/arm/boot/dts/bcm-nsp.dtsi index e7d08959d5fe..09fd7e55c069 100644 --- a/arch/arm/boot/dts/bcm-nsp.dtsi +++ b/arch/arm/boot/dts/bcm-nsp.dtsi @@ -390,7 +390,7 @@ reg = <0x36000 0x1000>, <0x3f308 0x8>, <0x3f410 0xc>; - reg-names = "srab", "mux_config", "sgmii"; + reg-names = "srab", "mux_config", "sgmii_config"; interrupts = , , , From 42791b317db4cda36751f57bada27857849811d3 Mon Sep 17 00:00:00 2001 From: Florian Fainelli Date: Mon, 9 Nov 2020 17:41:32 -0800 Subject: [PATCH 386/799] ARM: dts: NSP: Add a SRAB compatible string for each board Provide a valid compatible string for the Ethernet switch node based on the board including the switch. This allows us to have sane defaults and silences the following warnings: arch/arm/boot/dts/bcm958522er.dt.yaml: ethernet-switch@36000: compatible: 'oneOf' conditional failed, one must be fixed: ['brcm,bcm5301x-srab'] is too short 'brcm,bcm5325' was expected 'brcm,bcm53115' was expected 'brcm,bcm53125' was expected 'brcm,bcm53128' was expected 'brcm,bcm5365' was expected 'brcm,bcm5395' was expected 'brcm,bcm5389' was expected 'brcm,bcm5397' was expected 'brcm,bcm5398' was expected 'brcm,bcm11360-srab' was expected 'brcm,bcm5301x-srab' is not one of ['brcm,bcm53010-srab', 'brcm,bcm53011-srab', 'brcm,bcm53012-srab', 'brcm,bcm53018-srab', 'brcm,bcm53019-srab'] 'brcm,bcm5301x-srab' is not one of ['brcm,bcm11404-srab', 'brcm,bcm11407-srab', 'brcm,bcm11409-srab', 'brcm,bcm58310-srab', 'brcm,bcm58311-srab', 'brcm,bcm58313-srab'] 'brcm,bcm5301x-srab' is not one of ['brcm,bcm58522-srab', 'brcm,bcm58523-srab', 'brcm,bcm58525-srab', 'brcm,bcm58622-srab', 'brcm,bcm58623-srab', 'brcm,bcm58625-srab', 'brcm,bcm88312-srab'] 'brcm,bcm5301x-srab' is not one of ['brcm,bcm3384-switch', 'brcm,bcm6328-switch', 'brcm,bcm6368-switch'] From schema: Documentation/devicetree/bindings/net/dsa/b53.yaml Reviewed-by: Vladimir Oltean Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm958522er.dts | 4 ++++ arch/arm/boot/dts/bcm958525er.dts | 4 ++++ arch/arm/boot/dts/bcm958525xmc.dts | 4 ++++ 3 files changed, 12 insertions(+) diff --git a/arch/arm/boot/dts/bcm958522er.dts b/arch/arm/boot/dts/bcm958522er.dts index 7be4c4e628e0..5443fc079e6e 100644 --- a/arch/arm/boot/dts/bcm958522er.dts +++ b/arch/arm/boot/dts/bcm958522er.dts @@ -178,3 +178,7 @@ &xhci { status = "okay"; }; + +&srab { + compatible = "brcm,bcm58522-srab", "brcm,nsp-srab"; +}; diff --git a/arch/arm/boot/dts/bcm958525er.dts b/arch/arm/boot/dts/bcm958525er.dts index e58ed7e95346..e1e3c26cef19 100644 --- a/arch/arm/boot/dts/bcm958525er.dts +++ b/arch/arm/boot/dts/bcm958525er.dts @@ -190,3 +190,7 @@ &xhci { status = "okay"; }; + +&srab { + compatible = "brcm,bcm58525-srab", "brcm,nsp-srab"; +}; diff --git a/arch/arm/boot/dts/bcm958525xmc.dts b/arch/arm/boot/dts/bcm958525xmc.dts index 21f922dc6019..f161ba2e7e5e 100644 --- a/arch/arm/boot/dts/bcm958525xmc.dts +++ b/arch/arm/boot/dts/bcm958525xmc.dts @@ -210,3 +210,7 @@ &xhci { status = "okay"; }; + +&srab { + compatible = "brcm,bcm58525-srab", "brcm,nsp-srab"; +}; From 51e40c25aa18d926a8eb1c07289d01611b21123a Mon Sep 17 00:00:00 2001 From: Florian Fainelli Date: Mon, 9 Nov 2020 17:44:33 -0800 Subject: [PATCH 387/799] ARM: dts: NSP: Provide defaults ports container node Provide an empty 'ports' container node with the correct #address-cells and #size-cells properties. This silences the following warning: arch/arm/boot/dts/bcm958522er.dt.yaml: ethernet-switch@36000: 'oneOf' conditional failed, one must be fixed: 'ports' is a required property 'ethernet-ports' is a required property From schema: Documentation/devicetree/bindings/net/dsa/b53.yaml Reviewed-by: Vladimir Oltean Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm-nsp.dtsi | 4 ++++ arch/arm/boot/dts/bcm958622hr.dts | 3 --- arch/arm/boot/dts/bcm958623hr.dts | 3 --- arch/arm/boot/dts/bcm958625hr.dts | 3 --- arch/arm/boot/dts/bcm958625k.dts | 3 --- arch/arm/boot/dts/bcm988312hr.dts | 3 --- 6 files changed, 4 insertions(+), 15 deletions(-) diff --git a/arch/arm/boot/dts/bcm-nsp.dtsi b/arch/arm/boot/dts/bcm-nsp.dtsi index 09fd7e55c069..b4d2cc70afb1 100644 --- a/arch/arm/boot/dts/bcm-nsp.dtsi +++ b/arch/arm/boot/dts/bcm-nsp.dtsi @@ -420,6 +420,10 @@ status = "disabled"; /* ports are defined in board DTS */ + ports { + #address-cells = <1>; + #size-cells = <0>; + }; }; i2c0: i2c@38000 { diff --git a/arch/arm/boot/dts/bcm958622hr.dts b/arch/arm/boot/dts/bcm958622hr.dts index a49c2fd21f4a..83cb877d63db 100644 --- a/arch/arm/boot/dts/bcm958622hr.dts +++ b/arch/arm/boot/dts/bcm958622hr.dts @@ -176,9 +176,6 @@ status = "okay"; ports { - #address-cells = <1>; - #size-cells = <0>; - port@0 { label = "port0"; reg = <0>; diff --git a/arch/arm/boot/dts/bcm958623hr.dts b/arch/arm/boot/dts/bcm958623hr.dts index dd6dff6452b8..4e106ce1384a 100644 --- a/arch/arm/boot/dts/bcm958623hr.dts +++ b/arch/arm/boot/dts/bcm958623hr.dts @@ -180,9 +180,6 @@ status = "okay"; ports { - #address-cells = <1>; - #size-cells = <0>; - port@0 { label = "port0"; reg = <0>; diff --git a/arch/arm/boot/dts/bcm958625hr.dts b/arch/arm/boot/dts/bcm958625hr.dts index a71371b4065e..cda6cc281e18 100644 --- a/arch/arm/boot/dts/bcm958625hr.dts +++ b/arch/arm/boot/dts/bcm958625hr.dts @@ -195,9 +195,6 @@ status = "okay"; ports { - #address-cells = <1>; - #size-cells = <0>; - port@0 { label = "port0"; reg = <0>; diff --git a/arch/arm/boot/dts/bcm958625k.dts b/arch/arm/boot/dts/bcm958625k.dts index 7782b61c51a1..ffbff0014c65 100644 --- a/arch/arm/boot/dts/bcm958625k.dts +++ b/arch/arm/boot/dts/bcm958625k.dts @@ -216,9 +216,6 @@ status = "okay"; ports { - #address-cells = <1>; - #size-cells = <0>; - port@0 { label = "port0"; reg = <0>; diff --git a/arch/arm/boot/dts/bcm988312hr.dts b/arch/arm/boot/dts/bcm988312hr.dts index edd0f630e025..3fd39c479a3c 100644 --- a/arch/arm/boot/dts/bcm988312hr.dts +++ b/arch/arm/boot/dts/bcm988312hr.dts @@ -184,9 +184,6 @@ status = "okay"; ports { - #address-cells = <1>; - #size-cells = <0>; - port@0 { label = "port0"; reg = <0>; From ab7eff24a1e993b649d0383ec831a7fab30fe369 Mon Sep 17 00:00:00 2001 From: Kurt Kanzenbach Date: Sat, 10 Oct 2020 18:46:26 +0200 Subject: [PATCH 388/799] dt-bindings: net: dsa: b53: Add YAML bindings Convert the b53 DSA device tree bindings to YAML in order to allow for automatic checking and such. Reviewed-by: Rob Herring Suggested-by: Florian Fainelli Signed-off-by: Kurt Kanzenbach --- .../devicetree/bindings/net/dsa/b53.txt | 149 ----------- .../devicetree/bindings/net/dsa/brcm,b53.yaml | 249 ++++++++++++++++++ MAINTAINERS | 2 +- 3 files changed, 250 insertions(+), 150 deletions(-) delete mode 100644 Documentation/devicetree/bindings/net/dsa/b53.txt create mode 100644 Documentation/devicetree/bindings/net/dsa/brcm,b53.yaml diff --git a/Documentation/devicetree/bindings/net/dsa/b53.txt b/Documentation/devicetree/bindings/net/dsa/b53.txt deleted file mode 100644 index f1487a751b1a..000000000000 --- a/Documentation/devicetree/bindings/net/dsa/b53.txt +++ /dev/null @@ -1,149 +0,0 @@ -Broadcom BCM53xx Ethernet switches -================================== - -Required properties: - -- compatible: For external switch chips, compatible string must be exactly one - of: "brcm,bcm5325" - "brcm,bcm53115" - "brcm,bcm53125" - "brcm,bcm53128" - "brcm,bcm5365" - "brcm,bcm5395" - "brcm,bcm5389" - "brcm,bcm5397" - "brcm,bcm5398" - - For the BCM11360 SoC, must be: - "brcm,bcm11360-srab" and the mandatory "brcm,cygnus-srab" string - - For the BCM5310x SoCs with an integrated switch, must be one of: - "brcm,bcm53010-srab" - "brcm,bcm53011-srab" - "brcm,bcm53012-srab" - "brcm,bcm53018-srab" - "brcm,bcm53019-srab" and the mandatory "brcm,bcm5301x-srab" string - - For the BCM5831X/BCM1140x SoCs with an integrated switch, must be one of: - "brcm,bcm11404-srab" - "brcm,bcm11407-srab" - "brcm,bcm11409-srab" - "brcm,bcm58310-srab" - "brcm,bcm58311-srab" - "brcm,bcm58313-srab" and the mandatory "brcm,omega-srab" string - - For the BCM585xx/586XX/88312 SoCs with an integrated switch, must be one of: - "brcm,bcm58522-srab" - "brcm,bcm58523-srab" - "brcm,bcm58525-srab" - "brcm,bcm58622-srab" - "brcm,bcm58623-srab" - "brcm,bcm58625-srab" - "brcm,bcm88312-srab" and the mandatory "brcm,nsp-srab string - - For the BCM63xx/33xx SoCs with an integrated switch, must be one of: - "brcm,bcm3384-switch" - "brcm,bcm6328-switch" - "brcm,bcm6368-switch" and the mandatory "brcm,bcm63xx-switch" - -Required properties for BCM585xx/586xx/88312 SoCs: - - - reg: a total of 3 register base addresses, the first one must be the - Switch Register Access block base, the second is the port 5/4 mux - configuration register and the third one is the SGMII configuration - and status register base address. - - - interrupts: a total of 13 interrupts must be specified, in the following - order: port 0-5, 7-8 link status change, then the integrated PHY interrupt, - then the timestamping interrupt and the sleep timer interrupts for ports - 5,7,8. - -Optional properties for BCM585xx/586xx/88312 SoCs: - - - reg-names: a total of 3 names matching the 3 base register address, must - be in the following order: - "srab" - "mux_config" - "sgmii_config" - - - interrupt-names: a total of 13 names matching the 13 interrupts specified - must be in the following order: - "link_state_p0" - "link_state_p1" - "link_state_p2" - "link_state_p3" - "link_state_p4" - "link_state_p5" - "link_state_p7" - "link_state_p8" - "phy" - "ts" - "imp_sleep_timer_p5" - "imp_sleep_timer_p7" - "imp_sleep_timer_p8" - -See Documentation/devicetree/bindings/net/dsa/dsa.txt for a list of additional -required and optional properties. - -Examples: - -Ethernet switch connected via MDIO to the host, CPU port wired to eth0: - - eth0: ethernet@10001000 { - compatible = "brcm,unimac"; - reg = <0x10001000 0x1000>; - - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - - mdio0: mdio@10000000 { - compatible = "brcm,unimac-mdio"; - #address-cells = <1>; - #size-cells = <0>; - - switch0: ethernet-switch@1e { - compatible = "brcm,bcm53125"; - reg = <30>; - #address-cells = <1>; - #size-cells = <0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port0@0 { - reg = <0>; - label = "lan1"; - }; - - port1@1 { - reg = <1>; - label = "lan2"; - }; - - port5@5 { - reg = <5>; - label = "cable-modem"; - fixed-link { - speed = <1000>; - full-duplex; - }; - phy-mode = "rgmii-txid"; - }; - - port8@8 { - reg = <8>; - label = "cpu"; - fixed-link { - speed = <1000>; - full-duplex; - }; - phy-mode = "rgmii-txid"; - ethernet = <ð0>; - }; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/net/dsa/brcm,b53.yaml b/Documentation/devicetree/bindings/net/dsa/brcm,b53.yaml new file mode 100644 index 000000000000..c3c938893ad9 --- /dev/null +++ b/Documentation/devicetree/bindings/net/dsa/brcm,b53.yaml @@ -0,0 +1,249 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/dsa/brcm,b53.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Broadcom BCM53xx Ethernet switches + +allOf: + - $ref: dsa.yaml# + +maintainers: + - Florian Fainelli + +description: + Broadcom BCM53xx Ethernet switches + +properties: + compatible: + oneOf: + - const: brcm,bcm5325 + - const: brcm,bcm53115 + - const: brcm,bcm53125 + - const: brcm,bcm53128 + - const: brcm,bcm5365 + - const: brcm,bcm5395 + - const: brcm,bcm5389 + - const: brcm,bcm5397 + - const: brcm,bcm5398 + - items: + - const: brcm,bcm11360-srab + - const: brcm,cygnus-srab + - items: + - enum: + - brcm,bcm53010-srab + - brcm,bcm53011-srab + - brcm,bcm53012-srab + - brcm,bcm53018-srab + - brcm,bcm53019-srab + - const: brcm,bcm5301x-srab + - items: + - enum: + - brcm,bcm11404-srab + - brcm,bcm11407-srab + - brcm,bcm11409-srab + - brcm,bcm58310-srab + - brcm,bcm58311-srab + - brcm,bcm58313-srab + - const: brcm,omega-srab + - items: + - enum: + - brcm,bcm58522-srab + - brcm,bcm58523-srab + - brcm,bcm58525-srab + - brcm,bcm58622-srab + - brcm,bcm58623-srab + - brcm,bcm58625-srab + - brcm,bcm88312-srab + - const: brcm,nsp-srab + - items: + - enum: + - brcm,bcm3384-switch + - brcm,bcm6328-switch + - brcm,bcm6368-switch + - const: brcm,bcm63xx-switch + +required: + - compatible + - reg + +# BCM585xx/586xx/88312 SoCs +if: + properties: + compatible: + contains: + enum: + - brcm,bcm58522-srab + - brcm,bcm58523-srab + - brcm,bcm58525-srab + - brcm,bcm58622-srab + - brcm,bcm58623-srab + - brcm,bcm58625-srab + - brcm,bcm88312-srab +then: + properties: + reg: + minItems: 3 + maxItems: 3 + reg-names: + items: + - const: srab + - const: mux_config + - const: sgmii_config + interrupts: + minItems: 13 + maxItems: 13 + interrupt-names: + items: + - const: link_state_p0 + - const: link_state_p1 + - const: link_state_p2 + - const: link_state_p3 + - const: link_state_p4 + - const: link_state_p5 + - const: link_state_p7 + - const: link_state_p8 + - const: phy + - const: ts + - const: imp_sleep_timer_p5 + - const: imp_sleep_timer_p7 + - const: imp_sleep_timer_p8 + required: + - interrupts +else: + properties: + reg: + maxItems: 1 + +unevaluatedProperties: false + +examples: + - | + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethernet-switch@1e { + compatible = "brcm,bcm53125"; + reg = <30>; + + ethernet-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "lan1"; + }; + + port@1 { + reg = <1>; + label = "lan2"; + }; + + port@5 { + reg = <5>; + label = "cable-modem"; + phy-mode = "rgmii-txid"; + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + + port@8 { + reg = <8>; + label = "cpu"; + phy-mode = "rgmii-txid"; + ethernet = <ð0>; + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + }; + }; + }; + - | + #include + #include + + axi { + #address-cells = <1>; + #size-cells = <1>; + + switch@36000 { + compatible = "brcm,bcm58623-srab", "brcm,nsp-srab"; + reg = <0x36000 0x1000>, + <0x3f308 0x8>, + <0x3f410 0xc>; + reg-names = "srab", "mux_config", "sgmii_config"; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "link_state_p0", + "link_state_p1", + "link_state_p2", + "link_state_p3", + "link_state_p4", + "link_state_p5", + "link_state_p7", + "link_state_p8", + "phy", + "ts", + "imp_sleep_timer_p5", + "imp_sleep_timer_p7", + "imp_sleep_timer_p8"; + + ethernet-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + label = "port0"; + reg = <0>; + }; + + port@1 { + label = "port1"; + reg = <1>; + }; + + port@2 { + label = "port2"; + reg = <2>; + }; + + port@3 { + label = "port3"; + reg = <3>; + }; + + port@4 { + label = "port4"; + reg = <4>; + }; + + port@8 { + ethernet = <&amac2>; + label = "cpu"; + reg = <8>; + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + }; + }; + }; diff --git a/MAINTAINERS b/MAINTAINERS index e73636b75f29..3786322d0bfb 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -3380,7 +3380,7 @@ M: Florian Fainelli L: netdev@vger.kernel.org L: openwrt-devel@lists.openwrt.org (subscribers-only) S: Supported -F: Documentation/devicetree/bindings/net/dsa/b53.txt +F: Documentation/devicetree/bindings/net/dsa/brcm,b53.yaml F: drivers/net/dsa/b53/* F: include/linux/platform_data/b53.h From d7a3fd7f00ee33fe0035f1a8269ac498010fbc48 Mon Sep 17 00:00:00 2001 From: Cengiz Can Date: Fri, 13 Nov 2020 18:06:19 +0300 Subject: [PATCH 389/799] dt-bindings: fsl-imx-drm: fix example compatible string Example `display-subsystem` has an incorrect compatible string. Required properties section tells that developers should use "fsl,imx-display-subsystem" as "compatible" string but the example misses 'imx-' prefix. Change example to have correct "compatible" string. Signed-off-by: Cengiz Can Link: https://lore.kernel.org/r/20201113150618.417424-1-cengiz@kernel.wtf Signed-off-by: Rob Herring --- Documentation/devicetree/bindings/display/imx/fsl-imx-drm.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/display/imx/fsl-imx-drm.txt b/Documentation/devicetree/bindings/display/imx/fsl-imx-drm.txt index 5a99490c17b9..3c35338a2867 100644 --- a/Documentation/devicetree/bindings/display/imx/fsl-imx-drm.txt +++ b/Documentation/devicetree/bindings/display/imx/fsl-imx-drm.txt @@ -12,7 +12,7 @@ Required properties: example: display-subsystem { - compatible = "fsl,display-subsystem"; + compatible = "fsl,imx-display-subsystem"; ports = <&ipu_di0>; }; From ea270ef71db64715cb46d15b85f30e77775ff88a Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Sat, 21 Nov 2020 19:26:32 -0800 Subject: [PATCH 390/799] ARM: dts: keystone-k2g-evm: add HDMI and analog audio data The board is using McASP2 for both analog (tlv320aic3106) and HDMI (SiI9022) audio. 12.288MHz oscillator provides the MCLK for both aic3106 and SiI9022. Signed-off-by: Peter Ujfalusi Signed-off-by: Santosh Shilimkar --- arch/arm/boot/dts/keystone-k2g-evm.dts | 112 +++++++++++++++++++++++++ 1 file changed, 112 insertions(+) diff --git a/arch/arm/boot/dts/keystone-k2g-evm.dts b/arch/arm/boot/dts/keystone-k2g-evm.dts index 8b3d64c913d8..14e26a4fd62a 100644 --- a/arch/arm/boot/dts/keystone-k2g-evm.dts +++ b/arch/arm/boot/dts/keystone-k2g-evm.dts @@ -46,6 +46,14 @@ regulator-always-on; }; + vcc1v8_ldo2_reg: fixedregulator-vcc1v8-ldo2 { + compatible = "regulator-fixed"; + regulator-name = "ldo2"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + hdmi: connector { compatible = "hdmi-connector"; label = "hdmi"; @@ -58,6 +66,57 @@ }; }; }; + + aud_mclk: aud_mclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <12288000>; + }; + + sound0: sound@0 { + compatible = "simple-audio-card"; + simple-audio-card,name = "K2G-EVM"; + simple-audio-card,widgets = + "Headphone", "Headphone Jack", + "Line", "Line In"; + simple-audio-card,routing = + "Headphone Jack", "HPLOUT", + "Headphone Jack", "HPROUT", + "LINE1L", "Line In", + "LINE1R", "Line In"; + + simple-audio-card,dai-link@0 { + format = "i2s"; + bitclock-master = <&sound0_0_master>; + frame-master = <&sound0_0_master>; + sound0_0_master: cpu { + sound-dai = <&mcasp2>; + clocks = <&k2g_clks 0x6 1>; + system-clock-direction-out; + }; + + codec { + sound-dai = <&tlv320aic3106>; + clocks = <&aud_mclk>; + }; + }; + + simple-audio-card,dai-link@1 { + format = "i2s"; + bitclock-master = <&sound0_1_master>; + frame-master = <&sound0_1_master>; + sound0_1_master: cpu { + sound-dai = <&mcasp2>; + clocks = <&k2g_clks 0x6 1>; + system-clock-direction-out; + }; + + codec { + sound-dai = <&sii9022>; + clocks = <&aud_mclk>; + }; + }; + }; }; &k2g_pinctrl { @@ -214,6 +273,15 @@ K2G_CORE_IOPAD(0x10e8) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssfid.dssfid */ >; }; + + mcasp2_pins: pinmux_mcasp2_pins { + pinctrl-single,pins = < + K2G_CORE_IOPAD(0x1234) (BUFFER_CLASS_B | PIN_PULLDOWN | MUX_MODE4) /* pr0_pru_gpo2.mcasp2_axr2 */ + K2G_CORE_IOPAD(0x1238) (BUFFER_CLASS_B | PIN_PULLDOWN | MUX_MODE4) /* pr0_pru_gpo3.mcasp2_axr3 */ + K2G_CORE_IOPAD(0x1254) (BUFFER_CLASS_B | PIN_PULLDOWN | MUX_MODE4) /* pr0_pru_gpo10.mcasp2_afsx */ + K2G_CORE_IOPAD(0x125c) (BUFFER_CLASS_B | PIN_PULLDOWN | MUX_MODE4) /* pr0_pru_gpo12.mcasp2_aclkx */ + >; + }; }; &uart0 { @@ -423,6 +491,10 @@ compatible = "sil,sii9022"; reg = <0x3b>; + sil,i2s-data-lanes = < 0 >; + clocks = <&aud_mclk>; + clock-names = "mclk"; + ports { #address-cells = <1>; #size-cells = <0>; @@ -444,6 +516,19 @@ }; }; }; + + tlv320aic3106: tlv320aic3106@1b { + #sound-dai-cells = <0>; + compatible = "ti,tlv320aic3106"; + reg = <0x1b>; + status = "okay"; + + /* Regulators */ + AVDD-supply = <&vcc3v3_dcin_reg>; + IOVDD-supply = <&vcc3v3_dcin_reg>; + DRVDD-supply = <&vcc3v3_dcin_reg>; + DVDD-supply = <&vcc1v8_ldo2_reg>; + }; }; &dss { @@ -458,3 +543,30 @@ }; }; }; + +&k2g_clks { + /* on the board 22.5792MHz is connected to AUDOSC_IN */ + assigned-clocks = <&k2g_clks 0x4c 2>; + assigned-clock-rates = <22579200>; +}; + +&mcasp2 { + #sound-dai-cells = <0>; + + pinctrl-names = "default"; + pinctrl-0 = <&mcasp2_pins>; + + assigned-clocks = <&k2g_clks 0x6 1>; + assigned-clock-parents = <&k2g_clks 0x6 2>; + + status = "okay"; + + op-mode = <0>; /* MCASP_IIS_MODE */ + tdm-slots = <2>; + /* 6 serializer */ + serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ + 0 0 1 2 0 0 // AXR2: TX, AXR3: rx + >; + tx-num-evt = <32>; + rx-num-evt = <32>; +}; From afbd0bdebe0d82c4846dbbce53625110889c5de8 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20J=C3=BCcker?= Date: Fri, 20 Nov 2020 17:00:54 +0100 Subject: [PATCH 391/799] ARM: dts: exynos: switch Atmel mxt reset GPIO to active low on P4 Note MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The reset GPIO logic of the Atmel maxtouch driver was changed to be active low at around the same time P4 Note device tree was accepted into the kernel. Adjust the configuration so that the touchscreen is in a usable state. Signed-off-by: Martin Jücker Link: https://lore.kernel.org/r/20201120160053.18942-1-martin.juecker@gmail.com Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos4412-p4note.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/exynos4412-p4note.dtsi b/arch/arm/boot/dts/exynos4412-p4note.dtsi index 0f8d4164a977..b2f9d5448a18 100644 --- a/arch/arm/boot/dts/exynos4412-p4note.dtsi +++ b/arch/arm/boot/dts/exynos4412-p4note.dtsi @@ -307,7 +307,7 @@ pinctrl-names = "default"; interrupt-parent = <&gpm2>; interrupts = <3 IRQ_TYPE_LEVEL_LOW>; - reset-gpios = <&gpm0 4 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpm0 4 GPIO_ACTIVE_LOW>; }; }; From 0c9dde0d201548d2297a8cd8d7eac25c76b875ef Mon Sep 17 00:00:00 2001 From: Jonathan Marek Date: Tue, 9 Jun 2020 15:40:23 -0400 Subject: [PATCH 392/799] arm64: dts: qcom: sm8150: Add secondary USB and PHY nodes Add dts nodes for the secondary USB controller and related PHY nodes. Signed-off-by: Jonathan Marek Link: https://lore.kernel.org/r/20200609194030.17756-6-jonathan@marek.ca Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8150.dtsi | 89 ++++++++++++++++++++++++++++ 1 file changed, 89 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi index 0d932c7d5e95..e40bec6f3623 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -845,6 +845,19 @@ resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; }; + usb_2_hsphy: phy@88e3000 { + compatible = "qcom,sm8150-usb-hs-phy", + "qcom,usb-snps-hs-7nm-phy"; + reg = <0 0x088e3000 0 0x400>; + status = "disabled"; + #phy-cells = <0>; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "ref"; + + resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; + }; + usb_1_qmpphy: phy@88e9000 { compatible = "qcom,sm8150-qmp-usb3-phy"; reg = <0 0x088e9000 0 0x18c>, @@ -894,6 +907,37 @@ qcom,bcm-voters = <&apps_bcm_voter>; }; + usb_2_qmpphy: phy@88eb000 { + compatible = "qcom,sm8150-qmp-usb3-uni-phy"; + reg = <0 0x088eb000 0 0x200>; + status = "disabled"; + #clock-cells = <1>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_USB3_SEC_CLKREF_CLK>, + <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>; + clock-names = "aux", "ref_clk_src", "ref", "com_aux"; + + resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>, + <&gcc GCC_USB3_PHY_SEC_BCR>; + reset-names = "phy", "common"; + + usb_2_ssphy: lane@88eb200 { + reg = <0 0x088eb200 0 0x200>, + <0 0x088eb400 0 0x200>, + <0 0x088eb800 0 0x800>, + <0 0x088eb600 0 0x200>; + #phy-cells = <0>; + clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; + clock-names = "pipe0"; + clock-output-names = "usb3_uni_phy_pipe_clk_src"; + }; + }; + usb_1: usb@a6f8800 { compatible = "qcom,sm8150-dwc3", "qcom,dwc3"; reg = <0 0x0a6f8800 0 0x400>; @@ -946,6 +990,51 @@ qcom,bcm-voters = <&apps_bcm_voter>; }; + usb_2: usb@a8f8800 { + compatible = "qcom,sm8150-dwc3", "qcom,dwc3"; + reg = <0 0x0a8f8800 0 0x400>; + status = "disabled"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + dma-ranges; + + clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, + <&gcc GCC_USB30_SEC_MASTER_CLK>, + <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, + <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_SEC_SLEEP_CLK>, + <&gcc GCC_USB3_SEC_CLKREF_CLK>; + clock-names = "cfg_noc", "core", "iface", "mock_utmi", + "sleep", "xo"; + + assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_SEC_MASTER_CLK>; + assigned-clock-rates = <19200000>, <200000000>; + + interrupts = , + , + , + ; + interrupt-names = "hs_phy_irq", "ss_phy_irq", + "dm_hs_phy_irq", "dp_hs_phy_irq"; + + power-domains = <&gcc USB30_SEC_GDSC>; + + resets = <&gcc GCC_USB30_SEC_BCR>; + + usb_2_dwc3: dwc3@a800000 { + compatible = "snps,dwc3"; + reg = <0 0x0a800000 0 0xcd00>; + interrupts = ; + iommus = <&apps_smmu 0x160 0>; + snps,dis_u2_susphy_quirk; + snps,dis_enblslpm_quirk; + phys = <&usb_2_hsphy>, <&usb_2_ssphy>; + phy-names = "usb2-phy", "usb3-phy"; + }; + }; + aoss_qmp: power-controller@c300000 { compatible = "qcom,sm8150-aoss-qmp"; reg = <0x0 0x0c300000 0x0 0x100000>; From 46a6f297d7dd62ddf03aaf2882f73a6ba20f99d1 Mon Sep 17 00:00:00 2001 From: Jonathan Marek Date: Tue, 9 Jun 2020 15:40:24 -0400 Subject: [PATCH 393/799] arm64: dts: qcom: sm8250: Add USB and PHY device nodes Add device nodes for the USB3 controller, QMP SS PHY and SNPS HS PHY. Signed-off-by: Jonathan Marek Link: https://lore.kernel.org/r/20200609194030.17756-7-jonathan@marek.ca Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 180 +++++++++++++++++++++++++++ 1 file changed, 180 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index 457c3e65c0b6..cd47622e34bb 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -1462,6 +1462,96 @@ }; }; + usb_1_hsphy: phy@88e3000 { + compatible = "qcom,sm8250-usb-hs-phy", + "qcom,usb-snps-hs-7nm-phy"; + reg = <0 0x088e3000 0 0x400>; + status = "disabled"; + #phy-cells = <0>; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "ref"; + + resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; + }; + + usb_2_hsphy: phy@88e4000 { + compatible = "qcom,sm8250-usb-hs-phy", + "qcom,usb-snps-hs-7nm-phy"; + reg = <0 0x088e4000 0 0x400>; + status = "disabled"; + #phy-cells = <0>; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "ref"; + + resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; + }; + + usb_1_qmpphy: phy@88e9000 { + compatible = "qcom,sm8250-qmp-usb3-phy"; + reg = <0 0x088e9000 0 0x200>, + <0 0x088e8000 0 0x20>; + reg-names = "reg-base", "dp_com"; + status = "disabled"; + #clock-cells = <1>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; + clock-names = "aux", "ref_clk_src", "com_aux"; + + resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, + <&gcc GCC_USB3_PHY_PRIM_BCR>; + reset-names = "phy", "common"; + + usb_1_ssphy: lanes@88e9200 { + reg = <0 0x088e9200 0 0x200>, + <0 0x088e9400 0 0x200>, + <0 0x088e9c00 0 0x400>, + <0 0x088e9600 0 0x200>, + <0 0x088e9800 0 0x200>, + <0 0x088e9a00 0 0x100>; + #phy-cells = <0>; + clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; + clock-names = "pipe0"; + clock-output-names = "usb3_phy_pipe_clk_src"; + }; + }; + + usb_2_qmpphy: phy@88eb000 { + compatible = "qcom,sm8250-qmp-usb3-uni-phy"; + reg = <0 0x088eb000 0 0x200>; + status = "disabled"; + #clock-cells = <1>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_USB3_SEC_CLKREF_EN>, + <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>; + clock-names = "aux", "ref_clk_src", "ref", "com_aux"; + + resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>, + <&gcc GCC_USB3_PHY_SEC_BCR>; + reset-names = "phy", "common"; + + usb_2_ssphy: lane@88eb200 { + reg = <0 0x088eb200 0 0x200>, + <0 0x088eb400 0 0x200>, + <0 0x088eb800 0 0x800>; + #phy-cells = <0>; + clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; + clock-names = "pipe0"; + clock-output-names = "usb3_uni_phy_pipe_clk_src"; + }; + }; + dc_noc: interconnect@90c0000 { compatible = "qcom,sm8250-dc-noc"; reg = <0 0x090c0000 0 0x4200>; @@ -1483,6 +1573,96 @@ qcom,bcm-voters = <&apps_bcm_voter>; }; + usb_1: usb@a6f8800 { + compatible = "qcom,sm8250-dwc3", "qcom,dwc3"; + reg = <0 0x0a6f8800 0 0x400>; + status = "disabled"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + dma-ranges; + + clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_MASTER_CLK>, + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_PRIM_SLEEP_CLK>, + <&gcc GCC_USB3_SEC_CLKREF_EN>; + clock-names = "cfg_noc", "core", "iface", "mock_utmi", + "sleep", "xo"; + + assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_PRIM_MASTER_CLK>; + assigned-clock-rates = <19200000>, <200000000>; + + interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 14 IRQ_TYPE_EDGE_BOTH>, + <&pdc 15 IRQ_TYPE_EDGE_BOTH>, + <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "hs_phy_irq", "dp_hs_phy_irq", + "dm_hs_phy_irq", "ss_phy_irq"; + + power-domains = <&gcc USB30_PRIM_GDSC>; + + resets = <&gcc GCC_USB30_PRIM_BCR>; + + usb_1_dwc3: dwc3@a600000 { + compatible = "snps,dwc3"; + reg = <0 0x0a600000 0 0xcd00>; + interrupts = ; + iommus = <&apps_smmu 0x0 0x0>; + snps,dis_u2_susphy_quirk; + snps,dis_enblslpm_quirk; + phys = <&usb_1_hsphy>, <&usb_1_ssphy>; + phy-names = "usb2-phy", "usb3-phy"; + }; + }; + + usb_2: usb@a8f8800 { + compatible = "qcom,sm8250-dwc3", "qcom,dwc3"; + reg = <0 0x0a8f8800 0 0x400>; + status = "disabled"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + dma-ranges; + + clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, + <&gcc GCC_USB30_SEC_MASTER_CLK>, + <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, + <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_SEC_SLEEP_CLK>, + <&gcc GCC_USB3_SEC_CLKREF_EN>; + clock-names = "cfg_noc", "core", "iface", "mock_utmi", + "sleep", "xo"; + + assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_SEC_MASTER_CLK>; + assigned-clock-rates = <19200000>, <200000000>; + + interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 12 IRQ_TYPE_EDGE_BOTH>, + <&pdc 13 IRQ_TYPE_EDGE_BOTH>, + <&pdc 16 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "hs_phy_irq", "dp_hs_phy_irq", + "dm_hs_phy_irq", "ss_phy_irq"; + + power-domains = <&gcc USB30_SEC_GDSC>; + + resets = <&gcc GCC_USB30_SEC_BCR>; + + usb_2_dwc3: dwc3@a800000 { + compatible = "snps,dwc3"; + reg = <0 0x0a800000 0 0xcd00>; + interrupts = ; + iommus = <&apps_smmu 0x20 0>; + snps,dis_u2_susphy_quirk; + snps,dis_enblslpm_quirk; + phys = <&usb_2_hsphy>, <&usb_2_ssphy>; + phy-names = "usb2-phy", "usb3-phy"; + }; + }; + pdc: interrupt-controller@b220000 { compatible = "qcom,sm8250-pdc", "qcom,pdc"; reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>; From 0ab1b2d10afe60178e82cdde3ab7f3d5f458b8f7 Mon Sep 17 00:00:00 2001 From: Jonathan Marek Date: Tue, 9 Jun 2020 15:40:25 -0400 Subject: [PATCH 394/799] arm64: dts: qcom: add sm8150 hdk dts Add initial HDK855 dts, based on sm8150-mtp, with a few changes. Signed-off-by: Jonathan Marek Link: https://lore.kernel.org/r/20200609194030.17756-8-jonathan@marek.ca Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/Makefile | 1 + arch/arm64/boot/dts/qcom/sm8150-hdk.dts | 463 ++++++++++++++++++++++++ 2 files changed, 464 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sm8150-hdk.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 90887aac28e2..acddf4b0699c 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -45,5 +45,6 @@ dtb-$(CONFIG_ARCH_QCOM) += sdm845-db845c.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm845-mtp.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm845-xiaomi-beryllium.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm850-lenovo-yoga-c630.dtb +dtb-$(CONFIG_ARCH_QCOM) += sm8150-hdk.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8150-mtp.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8250-mtp.dtb diff --git a/arch/arm64/boot/dts/qcom/sm8150-hdk.dts b/arch/arm64/boot/dts/qcom/sm8150-hdk.dts new file mode 100644 index 000000000000..fb2cf3d987a1 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sm8150-hdk.dts @@ -0,0 +1,463 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2020, The Linux Foundation. All rights reserved. + */ + +/dts-v1/; + +#include +#include +#include "sm8150.dtsi" +#include "pm8150.dtsi" +#include "pm8150b.dtsi" +#include "pm8150l.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SM8150 HDK"; + compatible = "qcom,sm8150-hdk", "qcom,sm8150"; + + aliases { + serial0 = &uart2; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + vph_pwr: vph-pwr-regulator { + compatible = "regulator-fixed"; + regulator-name = "vph_pwr"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + }; + + vreg_s4a_1p8: pm8150-s4 { + compatible = "regulator-fixed"; + regulator-name = "vreg_s4a_1p8"; + + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-always-on; + regulator-boot-on; + + vin-supply = <&vph_pwr>; + }; + + gpio_keys { + compatible = "gpio-keys"; + + vol-up { + label = "Volume Up"; + linux,code = ; + gpios = <&pm8150_gpios 6 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&apps_rsc { + pm8150-rpmh-regulators { + compatible = "qcom,pm8150-rpmh-regulators"; + qcom,pmic-id = "a"; + + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s3-supply = <&vph_pwr>; + vdd-s4-supply = <&vph_pwr>; + vdd-s5-supply = <&vph_pwr>; + vdd-s6-supply = <&vph_pwr>; + vdd-s7-supply = <&vph_pwr>; + vdd-s8-supply = <&vph_pwr>; + vdd-s9-supply = <&vph_pwr>; + vdd-s10-supply = <&vph_pwr>; + + vdd-l1-l8-l11-supply = <&vreg_s6a_0p9>; + vdd-l2-l10-supply = <&vreg_bob>; + vdd-l3-l4-l5-l18-supply = <&vreg_s6a_0p9>; + vdd-l6-l9-supply = <&vreg_s8c_1p3>; + vdd-l7-l12-l14-l15-supply = <&vreg_s5a_2p0>; + vdd-l13-l16-l17-supply = <&vreg_bob>; + + vreg_s5a_2p0: smps5 { + regulator-min-microvolt = <1904000>; + regulator-max-microvolt = <2000000>; + }; + + vreg_s6a_0p9: smps6 { + regulator-min-microvolt = <920000>; + regulator-max-microvolt = <1128000>; + }; + + vdda_wcss_pll: + vreg_l1a_0p75: ldo1 { + regulator-min-microvolt = <752000>; + regulator-max-microvolt = <752000>; + regulator-initial-mode = ; + }; + + vdd_pdphy: + vdda_usb_hs_3p1: + vreg_l2a_3p1: ldo2 { + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3072000>; + regulator-initial-mode = ; + }; + + vreg_l3a_0p8: ldo3 { + regulator-min-microvolt = <480000>; + regulator-max-microvolt = <932000>; + regulator-initial-mode = ; + }; + + vdd_usb_hs_core: + vdda_csi_0_0p9: + vdda_csi_1_0p9: + vdda_csi_2_0p9: + vdda_csi_3_0p9: + vdda_dsi_0_0p9: + vdda_dsi_1_0p9: + vdda_dsi_0_pll_0p9: + vdda_dsi_1_pll_0p9: + vdda_pcie_1ln_core: + vdda_pcie_2ln_core: + vdda_pll_hv_cc_ebi01: + vdda_pll_hv_cc_ebi23: + vdda_qrefs_0p875_5: + vdda_sp_sensor: + vdda_ufs_2ln_core_1: + vdda_ufs_2ln_core_2: + vdda_usb_ss_dp_core_1: + vdda_usb_ss_dp_core_2: + vdda_qlink_lv: + vdda_qlink_lv_ck: + vreg_l5a_0p875: ldo5 { + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + regulator-initial-mode = ; + }; + + vreg_l6a_1p2: ldo6 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + vreg_l7a_1p8: ldo7 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vddpx_10: + vreg_l9a_1p2: ldo9 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + vreg_l10a_2p5: ldo10 { + regulator-min-microvolt = <2504000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = ; + }; + + vreg_l11a_0p8: ldo11 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + regulator-initial-mode = ; + }; + + vdd_qfprom: + vdd_qfprom_sp: + vdda_apc_cs_1p8: + vdda_gfx_cs_1p8: + vdda_usb_hs_1p8: + vdda_qrefs_vref_1p8: + vddpx_10_a: + vreg_l12a_1p8: ldo12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l13a_2p7: ldo13 { + regulator-min-microvolt = <2704000>; + regulator-max-microvolt = <2704000>; + regulator-initial-mode = ; + }; + + vreg_l14a_1p8: ldo14 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1880000>; + regulator-initial-mode = ; + }; + + vreg_l15a_1p7: ldo15 { + regulator-min-microvolt = <1704000>; + regulator-max-microvolt = <1704000>; + regulator-initial-mode = ; + }; + + vreg_l16a_2p7: ldo16 { + regulator-min-microvolt = <2704000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = ; + }; + + vreg_l17a_3p0: ldo17 { + regulator-min-microvolt = <2856000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = ; + }; + }; + + pm8150l-rpmh-regulators { + compatible = "qcom,pm8150l-rpmh-regulators"; + qcom,pmic-id = "c"; + + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s3-supply = <&vph_pwr>; + vdd-s4-supply = <&vph_pwr>; + vdd-s5-supply = <&vph_pwr>; + vdd-s6-supply = <&vph_pwr>; + vdd-s7-supply = <&vph_pwr>; + vdd-s8-supply = <&vph_pwr>; + + vdd-l1-l8-supply = <&vreg_s4a_1p8>; + vdd-l2-l3-supply = <&vreg_s8c_1p3>; + vdd-l4-l5-l6-supply = <&vreg_bob>; + vdd-l7-l11-supply = <&vreg_bob>; + vdd-l9-l10-supply = <&vreg_bob>; + + vdd-bob-supply = <&vph_pwr>; + vdd-flash-supply = <&vreg_bob>; + vdd-rgb-supply = <&vreg_bob>; + + vreg_bob: bob { + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <4000000>; + regulator-initial-mode = ; + regulator-allow-bypass; + }; + + vreg_s8c_1p3: smps8 { + regulator-min-microvolt = <1352000>; + regulator-max-microvolt = <1352000>; + }; + + vreg_l1c_1p8: ldo1 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vdda_wcss_adcdac_1: + vdda_wcss_adcdac_22: + vreg_l2c_1p3: ldo2 { + regulator-min-microvolt = <1304000>; + regulator-max-microvolt = <1304000>; + regulator-initial-mode = ; + }; + + vdda_hv_ebi0: + vdda_hv_ebi1: + vdda_hv_ebi2: + vdda_hv_ebi3: + vdda_hv_refgen0: + vdda_qlink_hv_ck: + vreg_l3c_1p2: ldo3 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + vddpx_5: + vreg_l4c_1p8: ldo4 { + regulator-min-microvolt = <1704000>; + regulator-max-microvolt = <2928000>; + regulator-initial-mode = ; + }; + + vddpx_6: + vreg_l5c_1p8: ldo5 { + regulator-min-microvolt = <1704000>; + regulator-max-microvolt = <2928000>; + regulator-initial-mode = ; + }; + + vddpx_2: + vreg_l6c_2p9: ldo6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = ; + }; + + vreg_l7c_3p0: ldo7 { + regulator-min-microvolt = <2856000>; + regulator-max-microvolt = <3104000>; + regulator-initial-mode = ; + }; + + vreg_l8c_1p8: ldo8 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l9c_2p9: ldo9 { + regulator-min-microvolt = <2704000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = ; + }; + + vreg_l10c_3p3: ldo10 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3312000>; + regulator-initial-mode = ; + }; + + vreg_l11c_3p3: ldo11 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3312000>; + regulator-initial-mode = ; + }; + }; + + pm8009-rpmh-regulators { + compatible = "qcom,pm8009-rpmh-regulators"; + qcom,pmic-id = "f"; + + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vreg_bob>; + + vdd-l2-supply = <&vreg_s8c_1p3>; + vdd-l5-l6-supply = <&vreg_bob>; + + vreg_l2f_1p2: ldo2 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + vreg_l5f_2p85: ldo5 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-initial-mode = ; + }; + + vreg_l6f_2p85: ldo6 { + regulator-initial-mode = ; + regulator-min-microvolt = <2856000>; + regulator-max-microvolt = <2856000>; + }; + }; +}; + +&qupv3_id_1 { + status = "okay"; +}; + +&pon { + pwrkey { + status = "okay"; + }; + + resin { + compatible = "qcom,pm8941-resin"; + interrupts = <0x0 0x8 0x1 IRQ_TYPE_EDGE_BOTH>; + debounce = <15625>; + bias-pull-up; + linux,code = ; + }; +}; + +&remoteproc_adsp { + status = "okay"; + + firmware-name = "qcom/sm8150/adsp.mbn"; +}; + +&remoteproc_cdsp { + status = "okay"; + + firmware-name = "qcom/sm8150/cdsp.mbn"; +}; + +&remoteproc_slpi { + status = "okay"; + + firmware-name = "qcom/sm8150/slpi.mbn"; +}; + +&tlmm { + gpio-reserved-ranges = <0 4>, <126 4>; +}; + +&uart2 { + status = "okay"; +}; + +&ufs_mem_hc { + status = "okay"; + + reset-gpios = <&tlmm 175 GPIO_ACTIVE_LOW>; + + vcc-supply = <&vreg_l10a_2p5>; + vcc-max-microamp = <750000>; + vccq-supply = <&vreg_l9a_1p2>; + vccq-max-microamp = <700000>; + vccq2-supply = <&vreg_s4a_1p8>; + vccq2-max-microamp = <750000>; +}; + +&ufs_mem_phy { + status = "okay"; + + vdda-phy-supply = <&vdda_ufs_2ln_core_1>; + vdda-max-microamp = <90200>; + vdda-pll-supply = <&vreg_l3c_1p2>; + vdda-pll-max-microamp = <19000>; +}; + +&usb_1_hsphy { + status = "okay"; + vdda-pll-supply = <&vdd_usb_hs_core>; + vdda33-supply = <&vdda_usb_hs_3p1>; + vdda18-supply = <&vdda_usb_hs_1p8>; +}; + +&usb_2_hsphy { + status = "okay"; + vdda-pll-supply = <&vdd_usb_hs_core>; + vdda33-supply = <&vdda_usb_hs_3p1>; + vdda18-supply = <&vdda_usb_hs_1p8>; +}; + +&usb_1_qmpphy { + status = "okay"; + vdda-phy-supply = <&vreg_l3c_1p2>; + vdda-pll-supply = <&vdda_usb_ss_dp_core_1>; +}; + +&usb_2_qmpphy { + status = "okay"; + vdda-phy-supply = <&vreg_l3c_1p2>; + vdda-pll-supply = <&vdda_usb_ss_dp_core_1>; +}; + +&usb_1 { + status = "okay"; +}; + +&usb_2 { + status = "okay"; +}; + +&usb_1_dwc3 { + dr_mode = "peripheral"; +}; + +&usb_2_dwc3 { + dr_mode = "host"; +}; From 91ed0e90fc491b427aa50eaa8efb40090355153a Mon Sep 17 00:00:00 2001 From: Jonathan Marek Date: Tue, 9 Jun 2020 15:40:26 -0400 Subject: [PATCH 395/799] arm64: dts: qcom: add sm8250 hdk dts Add initial HDK865 dts, based on sm8250-mtp, with a few changes. Notably, regulator configs are changed a bit. Signed-off-by: Jonathan Marek Link: https://lore.kernel.org/r/20200609194030.17756-9-jonathan@marek.ca Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/Makefile | 1 + arch/arm64/boot/dts/qcom/sm8250-hdk.dts | 454 ++++++++++++++++++++++++ 2 files changed, 455 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sm8250-hdk.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index acddf4b0699c..5113fac80b7a 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -47,4 +47,5 @@ dtb-$(CONFIG_ARCH_QCOM) += sdm845-xiaomi-beryllium.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm850-lenovo-yoga-c630.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8150-hdk.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8150-mtp.dtb +dtb-$(CONFIG_ARCH_QCOM) += sm8250-hdk.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8250-mtp.dtb diff --git a/arch/arm64/boot/dts/qcom/sm8250-hdk.dts b/arch/arm64/boot/dts/qcom/sm8250-hdk.dts new file mode 100644 index 000000000000..b5026e422aa6 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sm8250-hdk.dts @@ -0,0 +1,454 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2020, The Linux Foundation. All rights reserved. + */ + +/dts-v1/; + +#include +#include +#include "sm8250.dtsi" +#include "pm8150.dtsi" +#include "pm8150b.dtsi" +#include "pm8150l.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SM8250 HDK"; + compatible = "qcom,sm8250-hdk", "qcom,sm8250"; + + aliases { + serial0 = &uart2; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + vph_pwr: vph-pwr-regulator { + compatible = "regulator-fixed"; + regulator-name = "vph_pwr"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + }; + + vreg_s4a_1p8: pm8150-s4 { + compatible = "regulator-fixed"; + regulator-name = "vreg_s4a_1p8"; + + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-always-on; + regulator-boot-on; + + vin-supply = <&vph_pwr>; + }; + + vreg_s6c_0p88: smpc6-regulator { + compatible = "regulator-fixed"; + regulator-name = "vreg_s6c_0p88"; + + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + regulator-always-on; + vin-supply = <&vph_pwr>; + }; + + gpio_keys { + compatible = "gpio-keys"; + + vol-up { + label = "Volume Up"; + linux,code = ; + gpios = <&pm8150_gpios 6 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&apps_rsc { + pm8150-rpmh-regulators { + compatible = "qcom,pm8150-rpmh-regulators"; + qcom,pmic-id = "a"; + + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s3-supply = <&vph_pwr>; + vdd-s4-supply = <&vph_pwr>; + vdd-s5-supply = <&vph_pwr>; + vdd-s6-supply = <&vph_pwr>; + vdd-s7-supply = <&vph_pwr>; + vdd-s8-supply = <&vph_pwr>; + vdd-s9-supply = <&vph_pwr>; + vdd-s10-supply = <&vph_pwr>; + vdd-l1-l8-l11-supply = <&vreg_s6c_0p88>; + vdd-l2-l10-supply = <&vreg_bob>; + vdd-l3-l4-l5-l18-supply = <&vreg_s6a_0p95>; + vdd-l6-l9-supply = <&vreg_s8c_1p3>; + vdd-l7-l12-l14-l15-supply = <&vreg_s5a_1p9>; + vdd-l13-l16-l17-supply = <&vreg_bob>; + + vreg_s5a_1p9: smps5 { + regulator-name = "vreg_s5a_1p9"; + regulator-min-microvolt = <1824000>; + regulator-max-microvolt = <2000000>; + regulator-initial-mode = ; + }; + + vreg_s6a_0p95: smps6 { + regulator-name = "vreg_s6a_0p95"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <1128000>; + regulator-initial-mode = ; + }; + + vreg_l2a_3p1: ldo2 { + regulator-name = "vreg_l2a_3p1"; + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3072000>; + regulator-initial-mode = ; + }; + + vreg_l3a_0p9: ldo3 { + regulator-name = "vreg_l3a_0p9"; + regulator-min-microvolt = <928000>; + regulator-max-microvolt = <932000>; + regulator-initial-mode = ; + }; + + vreg_l5a_0p88: ldo5 { + regulator-name = "vreg_l5a_0p88"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + regulator-initial-mode = ; + }; + + vreg_l6a_1p2: ldo6 { + regulator-name = "vreg_l6a_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + vreg_l7a_1p7: ldo7 { + regulator-name = "vreg_l7a_1p7"; + regulator-min-microvolt = <1704000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l9a_1p2: ldo9 { + regulator-name = "vreg_l9a_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + vreg_l10a_1p8: ldo10 { + regulator-name = "vreg_l10a_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = ; + }; + + vreg_l12a_1p8: ldo12 { + regulator-name = "vreg_l12a_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l13a_ts_3p0: ldo13 { + regulator-name = "vreg_l13a_ts_3p0"; + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = ; + }; + + vreg_l14a_1p8: ldo14 { + regulator-name = "vreg_l14a_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1880000>; + regulator-initial-mode = ; + }; + + vreg_l15a_1p8: ldo15 { + regulator-name = "vreg_l15a_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l16a_3p3: ldo16 { + regulator-name = "vreg_l16a_3p3"; + regulator-min-microvolt = <3024000>; + regulator-max-microvolt = <3304000>; + regulator-initial-mode = ; + }; + + vreg_l17a_2p96: ldo17 { + regulator-name = "vreg_l17a_2p96"; + regulator-min-microvolt = <2496000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = ; + }; + + vreg_l18a_0p92: ldo18 { + regulator-name = "vreg_l18a_0p92"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = ; + }; + }; + + pm8150l-rpmh-regulators { + compatible = "qcom,pm8150l-rpmh-regulators"; + qcom,pmic-id = "c"; + + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s3-supply = <&vph_pwr>; + vdd-s4-supply = <&vph_pwr>; + vdd-s5-supply = <&vph_pwr>; + vdd-s6-supply = <&vph_pwr>; + vdd-s7-supply = <&vph_pwr>; + vdd-s8-supply = <&vph_pwr>; + vdd-l1-l8-supply = <&vreg_s4a_1p8>; + vdd-l2-l3-supply = <&vreg_s8c_1p3>; + vdd-l4-l5-l6-supply = <&vreg_bob>; + vdd-l7-l11-supply = <&vreg_bob>; + vdd-l9-l10-supply = <&vreg_bob>; + vdd-bob-supply = <&vph_pwr>; + + vreg_bob: bob { + regulator-name = "vreg_bob"; + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <3960000>; + regulator-initial-mode = ; + }; + + vreg_s8c_1p3: smps8 { + regulator-name = "vreg_s8c_1p3"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1400000>; + regulator-initial-mode = ; + }; + + vreg_l1c_1p8: ldo1 { + regulator-name = "vreg_l1c_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l2c_1p2: ldo2 { + regulator-name = "vreg_l2c_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1304000>; + regulator-initial-mode = ; + }; + + vreg_l3c_0p8: ldo3 { + regulator-name = "vreg_l3c_0p8"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + vreg_l4c_1p8: ldo4 { + regulator-name = "vreg_l4c_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2800000>; + regulator-initial-mode = ; + }; + + vreg_l5c_1p8: ldo5 { + regulator-name = "vreg_l5c_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2800000>; + regulator-initial-mode = ; + }; + + vreg_l6c_2p96: ldo6 { + regulator-name = "vreg_l6c_2p96"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = ; + }; + + vreg_l7c_cam_vcm0_2p85: ldo7 { + regulator-name = "vreg_l7c_cam_vcm0_2p85"; + regulator-min-microvolt = <2856000>; + regulator-max-microvolt = <3104000>; + regulator-initial-mode = ; + }; + + vreg_l8c_1p8: ldo8 { + regulator-name = "vreg_l8c_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l9c_2p96: ldo9 { + regulator-name = "vreg_l9c_2p96"; + regulator-min-microvolt = <2704000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = ; + }; + + vreg_l10c_3p0: ldo10 { + regulator-name = "vreg_l10c_3p0"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3312000>; + regulator-initial-mode = ; + }; + + vreg_l11c_3p3: ldo11 { + regulator-name = "vreg_l11c_3p3"; + regulator-min-microvolt = <3104000>; + regulator-max-microvolt = <3312000>; + regulator-initial-mode = ; + }; + }; + + pm8009-rpmh-regulators { + compatible = "qcom,pm8009-rpmh-regulators"; + qcom,pmic-id = "f"; + + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vreg_bob>; + vdd-l2-supply = <&vreg_s8c_1p3>; + vdd-l5-l6-supply = <&vreg_bob>; + vdd-l7-supply = <&vreg_s4a_1p8>; + + vreg_l1f_cam_dvdd1_1p1: ldo1 { + regulator-name = "vreg_l1f_cam_dvdd1_1p1"; + regulator-min-microvolt = <1104000>; + regulator-max-microvolt = <1104000>; + regulator-initial-mode = ; + }; + + vreg_l2f_cam_dvdd0_1p2: ldo2 { + regulator-name = "vreg_l2f_cam_dvdd0_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + vreg_l3f_cam_dvdd2_1p05: ldo3 { + regulator-name = "vreg_l3f_cam_dvdd2_1p05"; + regulator-min-microvolt = <1056000>; + regulator-max-microvolt = <1056000>; + regulator-initial-mode = ; + }; + + vreg_l5f_cam_avdd0_2p85: ldo5 { + regulator-name = "vreg_l5f_cam_avdd0_2p85"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <3000000>; + regulator-initial-mode = ; + }; + + vreg_l6f_cam_avdd1_2p8: ldo6 { + regulator-name = "vreg_l6f_cam_avdd1_2p8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <3000000>; + regulator-initial-mode = ; + }; + + vreg_l7f_1p8: ldo7 { + regulator-name = "vreg_l7f_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + }; +}; + +&qupv3_id_1 { + status = "okay"; +}; + +&pon { + pwrkey { + status = "okay"; + }; + + resin { + compatible = "qcom,pm8941-resin"; + interrupts = <0x0 0x8 0x1 IRQ_TYPE_EDGE_BOTH>; + debounce = <15625>; + bias-pull-up; + linux,code = ; + }; +}; + +&tlmm { + gpio-reserved-ranges = <28 4>, <40 4>; +}; + +&uart2 { + status = "okay"; +}; + +&ufs_mem_hc { + status = "okay"; + + vcc-supply = <&vreg_l17a_2p96>; + vcc-max-microamp = <800000>; + vccq-supply = <&vreg_l6a_1p2>; + vccq-max-microamp = <800000>; + vccq2-supply = <&vreg_s4a_1p8>; + vccq2-max-microamp = <800000>; +}; + +&ufs_mem_phy { + status = "okay"; + + vdda-phy-supply = <&vreg_l5a_0p88>; + vdda-max-microamp = <89900>; + vdda-pll-supply = <&vreg_l9a_1p2>; + vdda-pll-max-microamp = <18800>; +}; + +&usb_1_hsphy { + status = "okay"; + vdda-pll-supply = <&vreg_l5a_0p88>; + vdda33-supply = <&vreg_l2a_3p1>; + vdda18-supply = <&vreg_l12a_1p8>; +}; + +&usb_2_hsphy { + status = "okay"; + vdda-pll-supply = <&vreg_l5a_0p88>; + vdda33-supply = <&vreg_l2a_3p1>; + vdda18-supply = <&vreg_l12a_1p8>; +}; + +&usb_1_qmpphy { + status = "okay"; + vdda-phy-supply = <&vreg_l9a_1p2>; + vdda-pll-supply = <&vreg_l18a_0p92>; +}; + +&usb_2_qmpphy { + status = "okay"; + vdda-phy-supply = <&vreg_l9a_1p2>; + vdda-pll-supply = <&vreg_l18a_0p92>; +}; + +&usb_1 { + status = "okay"; +}; + +&usb_2 { + status = "okay"; +}; + +&usb_1_dwc3 { + dr_mode = "peripheral"; +}; + +&usb_2_dwc3 { + dr_mode = "host"; +}; From c4cf0300be84c2233ffa1b7516be66b167bc81f5 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Wed, 28 Oct 2020 22:09:54 +0300 Subject: [PATCH 396/799] arm64: dts: qcom: sm8250: Add support for SDC2 Add support for SDC2 which can be used to interface uSD card. Signed-off-by: Manivannan Sadhasivam [DB: minor fixes: clocks, iommus, opps] Signed-off-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20201028190955.1264526-1-dmitry.baryshkov@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 45 ++++++++++++++++++++++++++++ 1 file changed, 45 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index cd47622e34bb..f4af58f66740 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -1552,6 +1552,51 @@ }; }; + sdhc_2: sdhci@8804000 { + compatible = "qcom,sm8250-sdhci", "qcom,sdhci-msm-v5"; + reg = <0 0x08804000 0 0x1000>; + + interrupts = , + ; + interrupt-names = "hc_irq", "pwr_irq"; + + clocks = <&gcc GCC_SDCC2_AHB_CLK>, + <&gcc GCC_SDCC2_APPS_CLK>, + <&xo_board>; + clock-names = "iface", "core", "xo"; + iommus = <&apps_smmu 0x4a0 0x0>; + qcom,dll-config = <0x0007642c>; + qcom,ddr-config = <0x80040868>; + power-domains = <&rpmhpd SM8250_CX>; + operating-points-v2 = <&sdhc2_opp_table>; + + status = "disabled"; + + sdhc2_opp_table: sdhc2-opp-table { + compatible = "operating-points-v2"; + + opp-19200000 { + opp-hz = /bits/ 64 <19200000>; + required-opps = <&rpmhpd_opp_min_svs>; + }; + + opp-50000000 { + opp-hz = /bits/ 64 <50000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-202000000 { + opp-hz = /bits/ 64 <202000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + }; + }; + dc_noc: interconnect@90c0000 { compatible = "qcom,sm8250-dc-noc"; reg = <0 0x090c0000 0 0x4200>; From 53a8ccf1c7e5c901342f7dcf43bb7ddb6027984b Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Wed, 28 Oct 2020 22:09:55 +0300 Subject: [PATCH 397/799] arm64: dts: qcom: rb5: Add support for uSD card Add support for uSD card on RB5 using the SDHC2 interface. Signed-off-by: Manivannan Sadhasivam [DB: disabled 1.8V support to get SDHC to work] Signed-off-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20201028190955.1264526-2-dmitry.baryshkov@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qrb5165-rb5.dts | 41 ++++++++++++++++++++++++ 1 file changed, 41 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts index fec31655141c..bc8d63a59598 100644 --- a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts +++ b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts @@ -18,6 +18,7 @@ aliases { serial0 = &uart12; + sdhc2 = &sdhc_2; }; chosen { @@ -475,6 +476,20 @@ status = "okay"; }; +&sdhc_2 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&sdc2_default_state &sdc2_card_det_n>; + vmmc-supply = <&vreg_l9c_2p96>; + vqmmc-supply = <&vreg_l6c_2p96>; + cd-gpios = <&tlmm 77 GPIO_ACTIVE_LOW>; + bus-width = <4>; + /* there seem to be issues with HS400-1.8V mode, so disable it */ + no-1-8-v; + no-sdio; + no-emmc; +}; + /* CAN */ &spi0 { status = "okay"; @@ -663,6 +678,32 @@ "HST_BLE_SNS_UART_RX", "HST_WLAN_UART_TX", "HST_WLAN_UART_RX"; + + sdc2_default_state: sdc2-default { + clk { + pins = "sdc2_clk"; + bias-disable; + drive-strength = <16>; + }; + + cmd { + pins = "sdc2_cmd"; + bias-pull-up; + drive-strength = <16>; + }; + + data { + pins = "sdc2_data"; + bias-pull-up; + drive-strength = <16>; + }; + }; + + sdc2_card_det_n: sd-card-det-n { + pins = "gpio77"; + function = "gpio"; + bias-pull-up; + }; }; &uart12 { From 8530939383f5770120cbdb107393012d4239654e Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sat, 10 Oct 2020 16:21:25 +0300 Subject: [PATCH 398/799] arm64: dts: qcom: sm8250: add iommus entry to QUP nodes Enable IOMMUs configuration for QUP nodes to stop SM8250 boards from rebooting when using I2C DMA transfers. Signed-off-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20201010132125.416064-1-dmitry.baryshkov@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index f4af58f66740..fee55fccc67e 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -456,6 +456,7 @@ <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; #address-cells = <2>; #size-cells = <2>; + iommus = <&apps_smmu 0x63 0x0>; ranges; status = "disabled"; @@ -662,6 +663,7 @@ <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; #address-cells = <2>; #size-cells = <2>; + iommus = <&apps_smmu 0x5a3 0x0>; ranges; status = "disabled"; @@ -924,6 +926,7 @@ <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; #address-cells = <2>; #size-cells = <2>; + iommus = <&apps_smmu 0x43 0x0>; ranges; status = "disabled"; From d371a931540bc36fd1199de3ec365a1187b7b282 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Wed, 30 Sep 2020 14:21:33 +0300 Subject: [PATCH 399/799] arm64: dts: qcom: sm8250: correct compatible for sm8250-mtp Qualcomm boards should define two compatible strings: one for board, anoter one for SoC family. sm8250-mtp.dts lists just the board compatible, which makes it incompatible with qcom.yaml schema. Reviewed-by: Vinod Koul Signed-off-by: Dmitry Baryshkov Fixes: 60378f1a171e ("arm64: dts: qcom: sm8250: Add sm8250 dts file") Link: https://lore.kernel.org/r/20200930112133.2091505-1-dmitry.baryshkov@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8250-mtp.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8250-mtp.dts b/arch/arm64/boot/dts/qcom/sm8250-mtp.dts index c85cab9c9b41..dea00f19711d 100644 --- a/arch/arm64/boot/dts/qcom/sm8250-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8250-mtp.dts @@ -14,7 +14,7 @@ / { model = "Qualcomm Technologies, Inc. SM8250 MTP"; - compatible = "qcom,sm8250-mtp"; + compatible = "qcom,sm8250-mtp", "qcom,sm8250"; aliases { serial0 = &uart12; From 65389ce636241c1226fa03b553f32c9ba178d549 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Mon, 21 Sep 2020 12:28:06 +0530 Subject: [PATCH 400/799] arm64: dts: qcom: sm8250: Add support for PRNG EE RNG (Random Number Generator) in SM8250 features PRNG EE (Execution Environment), hence add devicetree support for it. Signed-off-by: Manivannan Sadhasivam Link: https://lore.kernel.org/r/20200921065806.10928-1-manivannan.sadhasivam@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index fee55fccc67e..f1a3138bcbba 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -429,6 +429,13 @@ #mbox-cells = <2>; }; + rng: rng@793000 { + compatible = "qcom,prng-ee"; + reg = <0 0x00793000 0 0x1000>; + clocks = <&gcc GCC_PRNG_AHB_CLK>; + clock-names = "core"; + }; + qup_opp_table: qup-opp-table { compatible = "operating-points-v2"; From 52c90664f122eee2509dee934499b561b1a8959f Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Thu, 17 Sep 2020 13:56:22 +0530 Subject: [PATCH 401/799] arm64: dts: qcom: qrb5165-rb5: Add USB support RB5 makes use of the two USB controllers onboard. USB0 is connected to the Type C port and USB1 is connected to USB3.1 HUB which exposes following downstream ports: * 2 Type A ports * 2 HS/SS ports on the expansion connector * USB to LAN device Hence, enable these two controllers with the required PHYs. Signed-off-by: Manivannan Sadhasivam Link: https://lore.kernel.org/r/20200917082622.6823-4-manivannan.sadhasivam@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qrb5165-rb5.dts | 46 ++++++++++++++++++++++++ 1 file changed, 46 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts index bc8d63a59598..d9f52703ba2a 100644 --- a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts +++ b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts @@ -729,3 +729,49 @@ vdda-pll-supply = <&vreg_l9a_1p2>; vdda-pll-max-microamp = <18800>; }; + +&usb_1 { + status = "okay"; +}; + +&usb_1_dwc3 { + dr_mode = "peripheral"; +}; + +&usb_1_hsphy { + status = "okay"; + + vdda-pll-supply = <&vreg_l5a_0p88>; + vdda33-supply = <&vreg_l2a_3p1>; + vdda18-supply = <&vreg_l12a_1p8>; +}; + +&usb_1_qmpphy { + status = "okay"; + + vdda-phy-supply = <&vreg_l9a_1p2>; + vdda-pll-supply = <&vreg_l18a_0p92>; +}; + +&usb_2 { + status = "okay"; +}; + +&usb_2_dwc3 { + dr_mode = "host"; +}; + +&usb_2_hsphy { + status = "okay"; + + vdda-pll-supply = <&vreg_l5a_0p88>; + vdda33-supply = <&vreg_l2a_3p1>; + vdda18-supply = <&vreg_l12a_1p8>; +}; + +&usb_2_qmpphy { + status = "okay"; + + vdda-phy-supply = <&vreg_l9a_1p2>; + vdda-pll-supply = <&vreg_l18a_0p92>; +}; From 256958086de9f06291042b106b05804a450d5e8e Mon Sep 17 00:00:00 2001 From: Jonathan Marek Date: Tue, 8 Sep 2020 09:15:00 -0400 Subject: [PATCH 402/799] arm64: dts: qcom: add sm8250 fastrpc nodes Add fastrpc nodes for sDSP, cDSP, and aDSP. Signed-off-by: Jonathan Marek Link: https://lore.kernel.org/r/20200908131500.19891-1-jonathan@marek.ca Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 115 ++++++++++++++++++++++++++- 1 file changed, 113 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index f1a3138bcbba..a679f6864065 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -1429,8 +1429,35 @@ mboxes = <&ipcc IPCC_CLIENT_SLPI IPCC_MPROC_SIGNAL_GLINK_QMP>; - label = "lpass"; + label = "slpi"; qcom,remote-pid = <3>; + + fastrpc { + compatible = "qcom,fastrpc"; + qcom,glink-channels = "fastrpcglink-apps-dsp"; + label = "sdsp"; + #address-cells = <1>; + #size-cells = <0>; + + compute-cb@1 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <1>; + iommus = <&apps_smmu 0x0541 0x0>; + }; + + compute-cb@2 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <2>; + iommus = <&apps_smmu 0x0542 0x0>; + }; + + compute-cb@3 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <3>; + iommus = <&apps_smmu 0x0543 0x0>; + /* note: shared-cb = <4> in downstream */ + }; + }; }; }; @@ -1467,8 +1494,66 @@ mboxes = <&ipcc IPCC_CLIENT_CDSP IPCC_MPROC_SIGNAL_GLINK_QMP>; - label = "lpass"; + label = "cdsp"; qcom,remote-pid = <5>; + + fastrpc { + compatible = "qcom,fastrpc"; + qcom,glink-channels = "fastrpcglink-apps-dsp"; + label = "cdsp"; + #address-cells = <1>; + #size-cells = <0>; + + compute-cb@1 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <1>; + iommus = <&apps_smmu 0x1001 0x0460>; + }; + + compute-cb@2 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <2>; + iommus = <&apps_smmu 0x1002 0x0460>; + }; + + compute-cb@3 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <3>; + iommus = <&apps_smmu 0x1003 0x0460>; + }; + + compute-cb@4 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <4>; + iommus = <&apps_smmu 0x1004 0x0460>; + }; + + compute-cb@5 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <5>; + iommus = <&apps_smmu 0x1005 0x0460>; + }; + + compute-cb@6 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <6>; + iommus = <&apps_smmu 0x1006 0x0460>; + }; + + compute-cb@7 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <7>; + iommus = <&apps_smmu 0x1007 0x0460>; + }; + + compute-cb@8 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <8>; + iommus = <&apps_smmu 0x1008 0x0460>; + }; + + /* note: secure cb9 in downstream */ + }; }; }; @@ -2534,6 +2619,32 @@ label = "lpass"; qcom,remote-pid = <2>; + + fastrpc { + compatible = "qcom,fastrpc"; + qcom,glink-channels = "fastrpcglink-apps-dsp"; + label = "adsp"; + #address-cells = <1>; + #size-cells = <0>; + + compute-cb@3 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <3>; + iommus = <&apps_smmu 0x1803 0x0>; + }; + + compute-cb@4 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <4>; + iommus = <&apps_smmu 0x1804 0x0>; + }; + + compute-cb@5 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <5>; + iommus = <&apps_smmu 0x1805 0x0>; + }; + }; }; }; From d5276bfa0ca6af7f65896c222b1b60493d189f27 Mon Sep 17 00:00:00 2001 From: Stephen Boyd Date: Fri, 20 Nov 2020 12:09:13 -0800 Subject: [PATCH 403/799] arm64: dts: qcom: sc7180: Remove double pull-up on p-sensor-int-l This interrupt has an external pull-up so we don't need to pull it up again. Drop the internal pull here. Note I don't think this really changes anything, just noticed while looking at this irq pin. Reviewed-by: Douglas Anderson Cc: Douglas Anderson Signed-off-by: Stephen Boyd Link: https://lore.kernel.org/r/20201120200913.618274-1-swboyd@chromium.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi index 781e61ad75a6..60a478a814d8 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi @@ -1332,7 +1332,8 @@ ap_spi_fp: &spi10 { pinconf { pins = "gpio24"; - bias-pull-up; + /* Has external pullup */ + bias-disable; }; }; From fee5dc31a588fffa543f3dfaaeebed55263b4ad2 Mon Sep 17 00:00:00 2001 From: Stephen Boyd Date: Fri, 20 Nov 2020 10:38:25 -0800 Subject: [PATCH 404/799] arm64: dts: qcom: sc7180: Add prox sensor to LTE sku Lazor boards There's a proximity sensor on Lazor devices, but only for LTE SKUs. Enable it only on the Lazor LTE SKUs and also configure it properly so it works. Cc: Douglas Anderson Cc: Matthias Kaehlcke Reviewed-by: Douglas Anderson Signed-off-by: Stephen Boyd Link: https://lore.kernel.org/r/20201120183825.547310-1-swboyd@chromium.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r1-lte.dts | 8 ++++++++ arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r3-lte.dts | 8 ++++++++ arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor.dtsi | 7 ++++++- arch/arm64/boot/dts/qcom/sc7180-trogdor-r1.dts | 5 ----- arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi | 1 - 5 files changed, 22 insertions(+), 7 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r1-lte.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r1-lte.dts index 5a67e5baafec..e16ba7b01f25 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r1-lte.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r1-lte.dts @@ -13,6 +13,14 @@ compatible = "google,lazor-rev1-sku0", "google,lazor-rev2-sku0", "qcom,sc7180"; }; +&ap_sar_sensor { + status = "okay"; +}; + +&ap_sar_sensor_i2c { + status = "okay"; +}; + &keyboard_backlight { status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r3-lte.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r3-lte.dts index 43836fc4d403..0881f8dd02c9 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r3-lte.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r3-lte.dts @@ -13,6 +13,14 @@ compatible = "google,lazor-sku0", "qcom,sc7180"; }; +&ap_sar_sensor { + status = "okay"; +}; + +&ap_sar_sensor_i2c { + status = "okay"; +}; + &keyboard_backlight { status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor.dtsi index 180ef9e04306..89e5cd29ec09 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor.dtsi @@ -30,7 +30,12 @@ ap_h1_spi: &spi0 {}; }; &ap_sar_sensor { - status = "okay"; + semtech,cs0-ground; + semtech,combined-sensors = <3>; + semtech,resolution = "fine"; + semtech,startup-sensor = <0>; + semtech,proxraw-strength = <8>; + semtech,avg-pos-strength = <64>; }; ap_ts_pen_1v8: &i2c4 { diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-r1.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-r1.dts index 0a281c24841c..59d67fb0efe8 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-r1.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-r1.dts @@ -34,11 +34,6 @@ ap_h1_spi: &spi0 {}; }; }; -&ap_sar_sensor_i2c { - /* Not hooked up */ - status = "disabled"; -}; - ap_ts_pen_1v8: &i2c4 { status = "okay"; clock-frequency = <400000>; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi index 60a478a814d8..3eb1ff2483be 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi @@ -654,7 +654,6 @@ edp_brij_i2c: &i2c2 { }; ap_sar_sensor_i2c: &i2c5 { - status = "okay"; clock-frequency = <400000>; ap_sar_sensor: proximity@28 { From e76be113d4a72573b8d892ca65642e5f171a1f81 Mon Sep 17 00:00:00 2001 From: Michael Srba Date: Sun, 15 Nov 2020 20:50:58 +0100 Subject: [PATCH 405/799] arm64: dts: qcom: msm8916-samsung-a3u: add nodes for touchscreen This patch wires up touchscreen support on Samsung Galaxy A3 2015. Reviewed-by: Stephan Gerhold Signed-off-by: Michael Srba Link: https://lore.kernel.org/r/20201115195058.27097-1-michael.srba@seznam.cz Signed-off-by: Bjorn Andersson --- .../boot/dts/qcom/msm8916-samsung-a3u-eur.dts | 29 +++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-a3u-eur.dts b/arch/arm64/boot/dts/qcom/msm8916-samsung-a3u-eur.dts index 086f07ead5cb..661f41ad978b 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-a3u-eur.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-a3u-eur.dts @@ -28,6 +28,27 @@ "0", "0", "1"; }; +&blsp_i2c5 { + status = "okay"; + + touchscreen@20 { + compatible = "zinitix,bt541"; + + reg = <0x20>; + interrupt-parent = <&msmgpio>; + interrupts = <13 IRQ_TYPE_EDGE_FALLING>; + + touchscreen-size-x = <540>; + touchscreen-size-y = <960>; + + vdd-supply = <®_vdd_tsp>; + vddo-supply = <&pm8916_l6>; + + pinctrl-names = "default"; + pinctrl-0 = <&ts_int_default>; + }; +}; + &dsi0 { panel@0 { reg = <0>; @@ -59,4 +80,12 @@ drive-strength = <2>; bias-disable; }; + + ts_int_default: ts-int-default { + pins = "gpio13"; + function = "gpio"; + + drive-strength = <2>; + bias-disable; + }; }; From 0af8bbdb6bb83b2b3cf0d005f1cfff5afe75c7c1 Mon Sep 17 00:00:00 2001 From: Nikita Travkin Date: Fri, 13 Nov 2020 22:59:12 +0500 Subject: [PATCH 406/799] arm64: dts: qcom: msm8916-longcheer-l8150: Enable PM8916 vibrator L8150 has a vibrator connected to PM8916. Add it to the device tree. Reviewed-by: Stephan Gerhold Signed-off-by: Nikita Travkin Link: https://lore.kernel.org/r/20201113175917.189123-1-nikitos.tr@gmail.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts b/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts index 2c204d535d66..d106bdbfda68 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts @@ -61,6 +61,10 @@ linux,code = ; }; +&pm8916_vib { + status = "okay"; +}; + &pronto { status = "okay"; }; From 6eb815289a3794264eee597c2daa311e051ff6fc Mon Sep 17 00:00:00 2001 From: Nikita Travkin Date: Fri, 13 Nov 2020 22:59:13 +0500 Subject: [PATCH 407/799] arm64: dts: msm8916-longcheer-l8150: Add touchscreen L8150 has RMI4 compatible Synaptics touchscreen on blsp_i2c5. It is powered by fixed regulator. Add both to the device tree. Reviewed-by: Stephan Gerhold Signed-off-by: Nikita Travkin Link: https://lore.kernel.org/r/20201113175917.189123-2-nikitos.tr@gmail.com Signed-off-by: Bjorn Andersson --- .../boot/dts/qcom/msm8916-longcheer-l8150.dts | 63 +++++++++++++++++++ 1 file changed, 63 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts b/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts index d106bdbfda68..21f2e8e0d05e 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts @@ -5,6 +5,7 @@ #include "msm8916-pm8916.dtsi" #include #include +#include / { model = "Longcheer L8150"; @@ -50,6 +51,52 @@ linux,code = ; }; }; + + reg_ctp: regulator-ctp { + compatible = "regulator-fixed"; + regulator-name = "ctp"; + + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + + gpio = <&msmgpio 17 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-names = "default"; + pinctrl-0 = <&ctp_pwr_en_default>; + }; +}; + +&blsp_i2c5 { + status = "okay"; + + rmi4@20 { + compatible = "syna,rmi4-i2c"; + reg = <0x20>; + #address-cells = <1>; + #size-cells = <0>; + + interrupt-parent = <&msmgpio>; + interrupts = <13 IRQ_TYPE_EDGE_FALLING>; + + vdd-supply = <®_ctp>; + vio-supply = <&pm8916_l6>; + + pinctrl-names = "default"; + pinctrl-0 = <&tp_int_default>; + + syna,startup-delay-ms = <10>; + + rmi4-f01@1 { + reg = <0x1>; + syna,nosleep-mode = <1>; // Allow sleeping + }; + + rmi4-f12@12 { + reg = <0x12>; + syna,sensor-type = <1>; // Touchscreen + }; + }; }; &blsp1_uart2 { @@ -201,6 +248,14 @@ }; &msmgpio { + ctp_pwr_en_default: ctp-pwr-en-default { + pins = "gpio17"; + function = "gpio"; + + drive-strength = <2>; + bias-disable; + }; + gpio_keys_default: gpio-keys-default { pins = "gpio107"; function = "gpio"; @@ -209,6 +264,14 @@ bias-pull-up; }; + tp_int_default: tp-int-default { + pins = "gpio13"; + function = "gpio"; + + drive-strength = <2>; + bias-disable; + }; + usb_vbus_default: usb-vbus-default { pins = "gpio62"; function = "gpio"; From 6bd2cae7ddd6e7b454d4d8267d9a8952856f8283 Mon Sep 17 00:00:00 2001 From: Nikita Travkin Date: Fri, 13 Nov 2020 22:59:14 +0500 Subject: [PATCH 408/799] arm64: dts: msm8916-longcheer-l8150: Add position sensors L8150 has: - BMC156 accelerometer and magnetic sensor - BMG160 gyroscope sensor Add them to the device tree. Reviewed-by: Stephan Gerhold Signed-off-by: Nikita Travkin Link: https://lore.kernel.org/r/20201113175917.189123-3-nikitos.tr@gmail.com Signed-off-by: Bjorn Andersson --- .../boot/dts/qcom/msm8916-longcheer-l8150.dts | 46 +++++++++++++++++++ 1 file changed, 46 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts b/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts index 21f2e8e0d05e..79a2475e3cd5 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts @@ -67,6 +67,44 @@ }; }; +&blsp_i2c2 { + status = "okay"; + + accelerometer@10 { + compatible = "bosch,bmc150_accel"; + reg = <0x10>; + + vdd-supply = <&pm8916_l17>; + vddio-supply = <&pm8916_l6>; + + mount-matrix = "0", "1", "0", + "-1", "0", "0", + "0", "0", "1"; + }; + + magnetometer@12 { + compatible = "bosch,bmc150_magn"; + reg = <0x12>; + + vdd-supply = <&pm8916_l17>; + vddio-supply = <&pm8916_l6>; + }; + + gyroscope@68 { + compatible = "bosch,bmg160"; + reg = <0x68>; + + interrupt-parent = <&msmgpio>; + interrupts = <23 IRQ_TYPE_EDGE_RISING>; + + pinctrl-names = "default"; + pinctrl-0 = <&gyro_int_default>; + + vdd-supply = <&pm8916_l17>; + vddio-supply = <&pm8916_l6>; + }; +}; + &blsp_i2c5 { status = "okay"; @@ -264,6 +302,14 @@ bias-pull-up; }; + gyro_int_default: gyro-int-default { + pins = "gpio23"; + function = "gpio"; + + drive-strength = <2>; + bias-disable; + }; + tp_int_default: tp-int-default { pins = "gpio13"; function = "gpio"; From 6b4ad4be646994e7e8c5707c87cc38725fd31e1b Mon Sep 17 00:00:00 2001 From: Nikita Travkin Date: Fri, 13 Nov 2020 22:59:15 +0500 Subject: [PATCH 409/799] arm64: dts: qcom: msm8916-longcheer-l8150: Add flash LED L8150 uses SGM3785 Flash LED driver. It is similar to SGM3140 but can also be controlled with PWM. Since SoC doesn't have PWM, add led to the device tree using sgm3140 driver. Reviewed-by: Stephan Gerhold Signed-off-by: Nikita Travkin Link: https://lore.kernel.org/r/20201113175917.189123-4-nikitos.tr@gmail.com Signed-off-by: Bjorn Andersson --- .../boot/dts/qcom/msm8916-longcheer-l8150.dts | 24 +++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts b/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts index 79a2475e3cd5..2b8670dd4b71 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts @@ -6,6 +6,7 @@ #include #include #include +#include / { model = "Longcheer L8150"; @@ -65,6 +66,21 @@ pinctrl-names = "default"; pinctrl-0 = <&ctp_pwr_en_default>; }; + + flash-led-controller { + compatible = "sgmicro,sgm3140"; + flash-gpios = <&msmgpio 31 GPIO_ACTIVE_HIGH>; + enable-gpios = <&msmgpio 32 GPIO_ACTIVE_HIGH>; + + pinctrl-names = "default"; + pinctrl-0 = <&camera_flash_default>; + + flash_led: led { + function = LED_FUNCTION_FLASH; + color = ; + flash-max-timeout-us = <250000>; + }; + }; }; &blsp_i2c2 { @@ -286,6 +302,14 @@ }; &msmgpio { + camera_flash_default: camera-flash-default { + pins = "gpio31", "gpio32"; + function = "gpio"; + + drive-strength = <2>; + bias-disable; + }; + ctp_pwr_en_default: ctp-pwr-en-default { pins = "gpio17"; function = "gpio"; From 38260b9e6310505f984bf3e026f4a4b6682c3526 Mon Sep 17 00:00:00 2001 From: Nikita Travkin Date: Fri, 13 Nov 2020 22:59:16 +0500 Subject: [PATCH 410/799] arm64: dts: qcom: msm8916-longcheer-l8150: Add notification LED L8150 uses aw2013 LED contriller for notification LED on the front of the device. Add it to the device tree Reviewed-by: Stephan Gerhold Signed-off-by: Nikita Travkin Link: https://lore.kernel.org/r/20201113175917.189123-5-nikitos.tr@gmail.com Signed-off-by: Bjorn Andersson --- .../boot/dts/qcom/msm8916-longcheer-l8150.dts | 34 +++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts b/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts index 2b8670dd4b71..1e893c0b6fbc 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts @@ -83,6 +83,40 @@ }; }; +&blsp_i2c1 { + status = "okay"; + + led-controller@45 { + compatible = "awinic,aw2013"; + reg = <0x45>; + #address-cells = <1>; + #size-cells = <0>; + + vcc-supply = <&pm8916_l17>; + + led@0 { + reg = <0>; + led-max-microamp = <5000>; + function = LED_FUNCTION_INDICATOR; + color = ; + }; + + led@1 { + reg = <1>; + led-max-microamp = <5000>; + function = LED_FUNCTION_INDICATOR; + color = ; + }; + + led@2 { + reg = <2>; + led-max-microamp = <5000>; + function = LED_FUNCTION_INDICATOR; + color = ; + }; + }; +}; + &blsp_i2c2 { status = "okay"; From 4e8692c2ee3d4ac6b669f7e306364d77a574c810 Mon Sep 17 00:00:00 2001 From: Nikita Travkin Date: Fri, 13 Nov 2020 22:59:17 +0500 Subject: [PATCH 411/799] arm64: dts: qcom: msm8916-samsung-a2015: Disable muic i2c pin bias Some versions of the firmware leave i2c gpios in a wrong state. Add pinctrl that disables pin bias since external pull-up resistors are present. Reviewed-by: Stephan Gerhold Fixes: 1329c1ab0730 ("arm64: dts: qcom: Add device tree for Samsung Galaxy A3U/A5U") Signed-off-by: Nikita Travkin Link: https://lore.kernel.org/r/20201113175917.189123-6-nikitos.tr@gmail.com Signed-off-by: Bjorn Andersson --- .../boot/dts/qcom/msm8916-samsung-a2015-common.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi b/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi index 0b0dfd3059de..f91269492d72 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi @@ -78,6 +78,9 @@ sda-gpios = <&msmgpio 105 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; scl-gpios = <&msmgpio 106 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + pinctrl-names = "default"; + pinctrl-0 = <&muic_i2c_default>; + #address-cells = <1>; #size-cells = <0>; @@ -304,6 +307,14 @@ }; }; + muic_i2c_default: muic-i2c-default { + pins = "gpio105", "gpio106"; + function = "gpio"; + + drive-strength = <2>; + bias-disable; + }; + muic_int_default: muic-int-default { pins = "gpio12"; function = "gpio"; From 26664c593adc047da121e9c78f706fefac77b132 Mon Sep 17 00:00:00 2001 From: Matthias Kaehlcke Date: Wed, 11 Nov 2020 12:03:43 -0800 Subject: [PATCH 412/799] arm64: dts: qcom: sc7180: Set 'polling-delay-passive' for thermal zones back to 250 ms Commit 22337b91022d ("arm64: dts: qcom: sc7180: Changed polling mode in Thermal-zones node") sets both 'polling-delay' and 'polling-delay-passive' to zero with the rationale that TSENS interrupts are enabled. A TSENS interrupt fires when the temperature of a thermal zone reaches a trip point, which makes regular polling below the passive trip point temperature unnecessary. However the situation is different when passive cooling is active, regular polling is still needed to trigger a periodic evaluation of the thermal zone by the thermal governor. Change 'polling-delay-passive' back to the original value of 250 ms. Commit 2315ae70af95 ("arm64: dts: qcom: sc7180: Add gpu cooling support") recently changed the value for the GPU thermal zones from zero to 100 ms, also set it to 250 ms for uniformity. If some zones really need different values these can be changed in dedicated patches. Reviewed-by: Douglas Anderson Fixes: 22337b91022d ("arm64: dts: qcom: sc7180: Changed polling mode in Thermal-zones node") Signed-off-by: Matthias Kaehlcke Link: https://lore.kernel.org/r/20201111120334.1.Ifc04ea235c3c370e3b21ec3b4d5dead83cc403b4@changeid Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc7180.dtsi | 50 ++++++++++++++-------------- 1 file changed, 25 insertions(+), 25 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index 625e922c273d..c0efb101b0d6 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -3522,7 +3522,7 @@ thermal-zones { cpu0-thermal { - polling-delay-passive = <0>; + polling-delay-passive = <250>; polling-delay = <0>; thermal-sensors = <&tsens0 1>; @@ -3571,7 +3571,7 @@ }; cpu1-thermal { - polling-delay-passive = <0>; + polling-delay-passive = <250>; polling-delay = <0>; thermal-sensors = <&tsens0 2>; @@ -3620,7 +3620,7 @@ }; cpu2-thermal { - polling-delay-passive = <0>; + polling-delay-passive = <250>; polling-delay = <0>; thermal-sensors = <&tsens0 3>; @@ -3669,7 +3669,7 @@ }; cpu3-thermal { - polling-delay-passive = <0>; + polling-delay-passive = <250>; polling-delay = <0>; thermal-sensors = <&tsens0 4>; @@ -3718,7 +3718,7 @@ }; cpu4-thermal { - polling-delay-passive = <0>; + polling-delay-passive = <250>; polling-delay = <0>; thermal-sensors = <&tsens0 5>; @@ -3767,7 +3767,7 @@ }; cpu5-thermal { - polling-delay-passive = <0>; + polling-delay-passive = <250>; polling-delay = <0>; thermal-sensors = <&tsens0 6>; @@ -3816,7 +3816,7 @@ }; cpu6-thermal { - polling-delay-passive = <0>; + polling-delay-passive = <250>; polling-delay = <0>; thermal-sensors = <&tsens0 9>; @@ -3857,7 +3857,7 @@ }; cpu7-thermal { - polling-delay-passive = <0>; + polling-delay-passive = <250>; polling-delay = <0>; thermal-sensors = <&tsens0 10>; @@ -3898,7 +3898,7 @@ }; cpu8-thermal { - polling-delay-passive = <0>; + polling-delay-passive = <250>; polling-delay = <0>; thermal-sensors = <&tsens0 11>; @@ -3939,7 +3939,7 @@ }; cpu9-thermal { - polling-delay-passive = <0>; + polling-delay-passive = <250>; polling-delay = <0>; thermal-sensors = <&tsens0 12>; @@ -3980,7 +3980,7 @@ }; aoss0-thermal { - polling-delay-passive = <0>; + polling-delay-passive = <250>; polling-delay = <0>; thermal-sensors = <&tsens0 0>; @@ -4001,7 +4001,7 @@ }; cpuss0-thermal { - polling-delay-passive = <0>; + polling-delay-passive = <250>; polling-delay = <0>; thermal-sensors = <&tsens0 7>; @@ -4021,7 +4021,7 @@ }; cpuss1-thermal { - polling-delay-passive = <0>; + polling-delay-passive = <250>; polling-delay = <0>; thermal-sensors = <&tsens0 8>; @@ -4041,7 +4041,7 @@ }; gpuss0-thermal { - polling-delay-passive = <100>; + polling-delay-passive = <250>; polling-delay = <0>; thermal-sensors = <&tsens0 13>; @@ -4069,7 +4069,7 @@ }; gpuss1-thermal { - polling-delay-passive = <100>; + polling-delay-passive = <250>; polling-delay = <0>; thermal-sensors = <&tsens0 14>; @@ -4097,7 +4097,7 @@ }; aoss1-thermal { - polling-delay-passive = <0>; + polling-delay-passive = <250>; polling-delay = <0>; thermal-sensors = <&tsens1 0>; @@ -4118,7 +4118,7 @@ }; cwlan-thermal { - polling-delay-passive = <0>; + polling-delay-passive = <250>; polling-delay = <0>; thermal-sensors = <&tsens1 1>; @@ -4139,7 +4139,7 @@ }; audio-thermal { - polling-delay-passive = <0>; + polling-delay-passive = <250>; polling-delay = <0>; thermal-sensors = <&tsens1 2>; @@ -4160,7 +4160,7 @@ }; ddr-thermal { - polling-delay-passive = <0>; + polling-delay-passive = <250>; polling-delay = <0>; thermal-sensors = <&tsens1 3>; @@ -4181,7 +4181,7 @@ }; q6-hvx-thermal { - polling-delay-passive = <0>; + polling-delay-passive = <250>; polling-delay = <0>; thermal-sensors = <&tsens1 4>; @@ -4202,7 +4202,7 @@ }; camera-thermal { - polling-delay-passive = <0>; + polling-delay-passive = <250>; polling-delay = <0>; thermal-sensors = <&tsens1 5>; @@ -4223,7 +4223,7 @@ }; mdm-core-thermal { - polling-delay-passive = <0>; + polling-delay-passive = <250>; polling-delay = <0>; thermal-sensors = <&tsens1 6>; @@ -4244,7 +4244,7 @@ }; mdm-dsp-thermal { - polling-delay-passive = <0>; + polling-delay-passive = <250>; polling-delay = <0>; thermal-sensors = <&tsens1 7>; @@ -4265,7 +4265,7 @@ }; npu-thermal { - polling-delay-passive = <0>; + polling-delay-passive = <250>; polling-delay = <0>; thermal-sensors = <&tsens1 8>; @@ -4286,7 +4286,7 @@ }; video-thermal { - polling-delay-passive = <0>; + polling-delay-passive = <250>; polling-delay = <0>; thermal-sensors = <&tsens1 9>; From b5330c565e4e481df579f602246073ecee265bc6 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Tue, 15 Sep 2020 14:45:50 +0200 Subject: [PATCH 413/799] dt-bindings: clk: axg-clkc: add Video Clocks Add clock IDs for the video clocks. Signed-off-by: Neil Armstrong Signed-off-by: Jerome Brunet Acked-by: Rob Herring Link: https://lore.kernel.org/r/20200915124553.8056-2-narmstrong@baylibre.com --- include/dt-bindings/clock/axg-clkc.h | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/include/dt-bindings/clock/axg-clkc.h b/include/dt-bindings/clock/axg-clkc.h index fd1f938c38d1..281df3e0f131 100644 --- a/include/dt-bindings/clock/axg-clkc.h +++ b/include/dt-bindings/clock/axg-clkc.h @@ -72,5 +72,29 @@ #define CLKID_PCIE_CML_EN1 80 #define CLKID_MIPI_ENABLE 81 #define CLKID_GEN_CLK 84 +#define CLKID_VPU_0_SEL 92 +#define CLKID_VPU_0 93 +#define CLKID_VPU_1_SEL 95 +#define CLKID_VPU_1 96 +#define CLKID_VPU 97 +#define CLKID_VAPB_0_SEL 99 +#define CLKID_VAPB_0 100 +#define CLKID_VAPB_1_SEL 102 +#define CLKID_VAPB_1 103 +#define CLKID_VAPB_SEL 104 +#define CLKID_VAPB 105 +#define CLKID_VCLK 106 +#define CLKID_VCLK2 107 +#define CLKID_VCLK_DIV1 122 +#define CLKID_VCLK_DIV2 123 +#define CLKID_VCLK_DIV4 124 +#define CLKID_VCLK_DIV6 125 +#define CLKID_VCLK_DIV12 126 +#define CLKID_VCLK2_DIV1 127 +#define CLKID_VCLK2_DIV2 128 +#define CLKID_VCLK2_DIV4 129 +#define CLKID_VCLK2_DIV6 130 +#define CLKID_VCLK2_DIV12 131 +#define CLKID_CTS_ENCL 133 #endif /* __AXG_CLKC_H */ From cd3caa573ebd1f32727962cf7dead43f5144d080 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Tue, 15 Sep 2020 14:45:51 +0200 Subject: [PATCH 414/799] dt-bindings: clk: axg-clkc: add MIPI DSI Host clock binding Add the clock ID for the MIPI DSI Host clock. Signed-off-by: Neil Armstrong Signed-off-by: Jerome Brunet Acked-by: Rob Herring Link: https://lore.kernel.org/r/20200915124553.8056-3-narmstrong@baylibre.com --- include/dt-bindings/clock/axg-clkc.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/dt-bindings/clock/axg-clkc.h b/include/dt-bindings/clock/axg-clkc.h index 281df3e0f131..e2749dbc74b8 100644 --- a/include/dt-bindings/clock/axg-clkc.h +++ b/include/dt-bindings/clock/axg-clkc.h @@ -96,5 +96,6 @@ #define CLKID_VCLK2_DIV6 130 #define CLKID_VCLK2_DIV12 131 #define CLKID_CTS_ENCL 133 +#define CLKID_VDIN_MEAS 136 #endif /* __AXG_CLKC_H */ From ae04aad75b3718b84df559bb0352f27695045fe0 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 17 Nov 2020 11:30:16 +0100 Subject: [PATCH 415/799] ARM: shmobile: r8a7778: Introduce HPBREG_BASE Replace the hardcoded address of the HPB Register block by a macro. Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20201117103022.2136527-2-geert+renesas@glider.be --- arch/arm/mach-shmobile/setup-r8a7778.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-shmobile/setup-r8a7778.c b/arch/arm/mach-shmobile/setup-r8a7778.c index 2bc93f391bcf..819dbda47298 100644 --- a/arch/arm/mach-shmobile/setup-r8a7778.c +++ b/arch/arm/mach-shmobile/setup-r8a7778.c @@ -14,6 +14,8 @@ #include "common.h" +#define HPBREG_BASE 0xfe700000 + #define INT2SMSKCR0 0x82288 /* 0xfe782288 */ #define INT2SMSKCR1 0x8228c /* 0xfe78228c */ @@ -22,7 +24,7 @@ static void __init r8a7778_init_irq_dt(void) { - void __iomem *base = ioremap(0xfe700000, 0x00100000); + void __iomem *base = ioremap(HPBREG_BASE, 0x00100000); BUG_ON(!base); From caf67a935740d7a4e9a7b0a3176237ad22a677e8 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 17 Nov 2020 11:30:17 +0100 Subject: [PATCH 416/799] ARM: shmobile: r8a7779: Use ioremap() to map INTC2 registers Replace using the legacy IOMEM() macro to map various registers related to INTC2 configuration by ioremap(). Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20201117103022.2136527-3-geert+renesas@glider.be --- arch/arm/mach-shmobile/setup-r8a7779.c | 36 +++++++++++++++----------- 1 file changed, 21 insertions(+), 15 deletions(-) diff --git a/arch/arm/mach-shmobile/setup-r8a7779.c b/arch/arm/mach-shmobile/setup-r8a7779.c index 86406e3f9b22..07c1bc96d4d9 100644 --- a/arch/arm/mach-shmobile/setup-r8a7779.c +++ b/arch/arm/mach-shmobile/setup-r8a7779.c @@ -38,30 +38,36 @@ static void __init r8a7779_map_io(void) iotable_init(r8a7779_io_desc, ARRAY_SIZE(r8a7779_io_desc)); } -/* IRQ */ -#define INT2SMSKCR0 IOMEM(0xfe7822a0) -#define INT2SMSKCR1 IOMEM(0xfe7822a4) -#define INT2SMSKCR2 IOMEM(0xfe7822a8) -#define INT2SMSKCR3 IOMEM(0xfe7822ac) -#define INT2SMSKCR4 IOMEM(0xfe7822b0) +#define HPBREG_BASE 0xfe700000 -#define INT2NTSR0 IOMEM(0xfe700060) -#define INT2NTSR1 IOMEM(0xfe700064) +/* IRQ */ +#define INT2SMSKCR0 0x822a0 /* Interrupt Submask Clear Register 0 */ +#define INT2SMSKCR1 0x822a4 /* Interrupt Submask Clear Register 1 */ +#define INT2SMSKCR2 0x822a8 /* Interrupt Submask Clear Register 2 */ +#define INT2SMSKCR3 0x822ac /* Interrupt Submask Clear Register 3 */ +#define INT2SMSKCR4 0x822b0 /* Interrupt Submask Clear Register 4 */ + +#define INT2NTSR0 0x00060 /* Interrupt Notification Select Register 0 */ +#define INT2NTSR1 0x00064 /* Interrupt Notification Select Register 1 */ static void __init r8a7779_init_irq_dt(void) { + void __iomem *base = ioremap(HPBREG_BASE, 0x00100000); + irqchip_init(); /* route all interrupts to ARM */ - __raw_writel(0xffffffff, INT2NTSR0); - __raw_writel(0x3fffffff, INT2NTSR1); + __raw_writel(0xffffffff, base + INT2NTSR0); + __raw_writel(0x3fffffff, base + INT2NTSR1); /* unmask all known interrupts in INTCS2 */ - __raw_writel(0xfffffff0, INT2SMSKCR0); - __raw_writel(0xfff7ffff, INT2SMSKCR1); - __raw_writel(0xfffbffdf, INT2SMSKCR2); - __raw_writel(0xbffffffc, INT2SMSKCR3); - __raw_writel(0x003fee3f, INT2SMSKCR4); + __raw_writel(0xfffffff0, base + INT2SMSKCR0); + __raw_writel(0xfff7ffff, base + INT2SMSKCR1); + __raw_writel(0xfffbffdf, base + INT2SMSKCR2); + __raw_writel(0xbffffffc, base + INT2SMSKCR3); + __raw_writel(0x003fee3f, base + INT2SMSKCR4); + + iounmap(base); } static const char *const r8a7779_compat_dt[] __initconst = { From 617ff9e657c4c4a6ffca325740e36d0d5e1f636e Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 17 Nov 2020 11:30:18 +0100 Subject: [PATCH 417/799] ARM: shmobile: r8a7779: Use ioremap() to map SMP registers Replace using the legacy IOMEM() macro to map the ARM Reset Vector Address Register (AVECR) by ioremap(). Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20201117103022.2136527-4-geert+renesas@glider.be --- arch/arm/mach-shmobile/smp-r8a7779.c | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/arch/arm/mach-shmobile/smp-r8a7779.c b/arch/arm/mach-shmobile/smp-r8a7779.c index 0ed73b650c14..f6713886ee16 100644 --- a/arch/arm/mach-shmobile/smp-r8a7779.c +++ b/arch/arm/mach-shmobile/smp-r8a7779.c @@ -20,8 +20,10 @@ #include "common.h" #include "r8a7779.h" -#define AVECR IOMEM(0xfe700040) -#define R8A7779_SCU_BASE 0xf0000000 +#define HPBREG_BASE 0xfe700000 +#define AVECR 0x0040 /* ARM Reset Vector Address Register */ + +#define R8A7779_SCU_BASE 0xf0000000 static int r8a7779_boot_secondary(unsigned int cpu, struct task_struct *idle) { @@ -36,11 +38,15 @@ static int r8a7779_boot_secondary(unsigned int cpu, struct task_struct *idle) static void __init r8a7779_smp_prepare_cpus(unsigned int max_cpus) { + void __iomem *base = ioremap(HPBREG_BASE, 0x1000); + /* Map the reset vector (in headsmp-scu.S, headsmp.S) */ - __raw_writel(__pa(shmobile_boot_vector), AVECR); + __raw_writel(__pa(shmobile_boot_vector), base + AVECR); /* setup r8a7779 specific SCU bits */ shmobile_smp_scu_prepare_cpus(R8A7779_SCU_BASE, max_cpus); + + iounmap(base); } #ifdef CONFIG_HOTPLUG_CPU From 5b0480f53dbfe58b6aa291f462a708f178c4bd40 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 17 Nov 2020 11:30:19 +0100 Subject: [PATCH 418/799] ARM: shmobile: r8a7779: Remove obsolete static mappings There are no more users of the statically mapped IOMEM regions on R-Car H1. Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20201117103022.2136527-5-geert+renesas@glider.be --- arch/arm/mach-shmobile/setup-r8a7779.c | 24 ------------------------ 1 file changed, 24 deletions(-) diff --git a/arch/arm/mach-shmobile/setup-r8a7779.c b/arch/arm/mach-shmobile/setup-r8a7779.c index 07c1bc96d4d9..446d40b50b7b 100644 --- a/arch/arm/mach-shmobile/setup-r8a7779.c +++ b/arch/arm/mach-shmobile/setup-r8a7779.c @@ -15,29 +15,6 @@ #include "common.h" #include "r8a7779.h" -static struct map_desc r8a7779_io_desc[] __initdata = { - /* 2M identity mapping for 0xf0000000 (MPCORE) */ - { - .virtual = 0xf0000000, - .pfn = __phys_to_pfn(0xf0000000), - .length = SZ_2M, - .type = MT_DEVICE_NONSHARED - }, - /* 16M identity mapping for 0xfexxxxxx (DMAC-S/HPBREG/INTC2/LRAM/DBSC) */ - { - .virtual = 0xfe000000, - .pfn = __phys_to_pfn(0xfe000000), - .length = SZ_16M, - .type = MT_DEVICE_NONSHARED - }, -}; - -static void __init r8a7779_map_io(void) -{ - debug_ll_io_init(); - iotable_init(r8a7779_io_desc, ARRAY_SIZE(r8a7779_io_desc)); -} - #define HPBREG_BASE 0xfe700000 /* IRQ */ @@ -77,7 +54,6 @@ static const char *const r8a7779_compat_dt[] __initconst = { DT_MACHINE_START(R8A7779_DT, "Generic R8A7779 (Flattened Device Tree)") .smp = smp_ops(r8a7779_smp_ops), - .map_io = r8a7779_map_io, .init_irq = r8a7779_init_irq_dt, .init_late = shmobile_init_late, .dt_compat = r8a7779_compat_dt, From cc85e21d6d18ffea52eef061f987978153c2aa0a Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 17 Nov 2020 11:30:20 +0100 Subject: [PATCH 419/799] ARM: shmobile: sh73a0: Use ioremap() to map L2C registers Replace using the legacy IOMEM() macro to map the L2C registers by ioremap(). Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20201117103022.2136527-6-geert+renesas@glider.be --- arch/arm/mach-shmobile/setup-sh73a0.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-shmobile/setup-sh73a0.c b/arch/arm/mach-shmobile/setup-sh73a0.c index eb4a62fa4289..e2fcfe1e4f24 100644 --- a/arch/arm/mach-shmobile/setup-sh73a0.c +++ b/arch/arm/mach-shmobile/setup-sh73a0.c @@ -44,7 +44,7 @@ static void __init sh73a0_generic_init(void) { #ifdef CONFIG_CACHE_L2X0 /* Shared attribute override enable, 64K*8way */ - l2x0_init(IOMEM(0xf0100000), 0x00400000, 0xc20f0fff); + l2x0_init(ioremap(0xf0100000, PAGE_SIZE), 0x00400000, 0xc20f0fff); #endif } From a0a6624dbec851ab5c136efbecd87a49617a5cc9 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 17 Nov 2020 11:30:21 +0100 Subject: [PATCH 420/799] ARM: shmobile: sh73a0: Use ioremap() to map SMP registers Replace using the legacy IOMEM() macro to map various registers related to secondary CPU bringup by ioremap(). Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20201117103022.2136527-7-geert+renesas@glider.be --- arch/arm/mach-shmobile/smp-sh73a0.c | 33 +++++++++++++++++++---------- 1 file changed, 22 insertions(+), 11 deletions(-) diff --git a/arch/arm/mach-shmobile/smp-sh73a0.c b/arch/arm/mach-shmobile/smp-sh73a0.c index 0403aa8629dd..6d892d11d81c 100644 --- a/arch/arm/mach-shmobile/smp-sh73a0.c +++ b/arch/arm/mach-shmobile/smp-sh73a0.c @@ -16,31 +16,42 @@ #include "common.h" #include "sh73a0.h" -#define WUPCR IOMEM(0xe6151010) -#define SRESCR IOMEM(0xe6151018) -#define PSTR IOMEM(0xe6151040) -#define SBAR IOMEM(0xe6180020) -#define APARMBAREA IOMEM(0xe6f10020) +#define CPG_BASE2 0xe6151000 +#define WUPCR 0x10 /* System-CPU Wake Up Control Register */ +#define SRESCR 0x18 /* System-CPU Software Reset Control Register */ +#define PSTR 0x40 /* System-CPU Power Status Register */ + +#define SYSC_BASE 0xe6180000 +#define SBAR 0x20 /* SYS Boot Address Register */ + +#define AP_BASE 0xe6f10000 +#define APARMBAREA 0x20 /* Address Translation Area Register */ #define SH73A0_SCU_BASE 0xf0000000 static int sh73a0_boot_secondary(unsigned int cpu, struct task_struct *idle) { unsigned int lcpu = cpu_logical_map(cpu); + void __iomem *cpg2 = ioremap(CPG_BASE2, PAGE_SIZE); - if (((__raw_readl(PSTR) >> (4 * lcpu)) & 3) == 3) - __raw_writel(1 << lcpu, WUPCR); /* wake up */ + if (((__raw_readl(cpg2 + PSTR) >> (4 * lcpu)) & 3) == 3) + __raw_writel(1 << lcpu, cpg2 + WUPCR); /* wake up */ else - __raw_writel(1 << lcpu, SRESCR); /* reset */ - + __raw_writel(1 << lcpu, cpg2 + SRESCR); /* reset */ + iounmap(cpg2); return 0; } static void __init sh73a0_smp_prepare_cpus(unsigned int max_cpus) { + void __iomem *ap = ioremap(AP_BASE, PAGE_SIZE); + void __iomem *sysc = ioremap(SYSC_BASE, PAGE_SIZE); + /* Map the reset vector (in headsmp.S) */ - __raw_writel(0, APARMBAREA); /* 4k */ - __raw_writel(__pa(shmobile_boot_vector), SBAR); + __raw_writel(0, ap + APARMBAREA); /* 4k */ + __raw_writel(__pa(shmobile_boot_vector), sysc + SBAR); + iounmap(sysc); + iounmap(ap); /* setup sh73a0 specific SCU bits */ shmobile_smp_scu_prepare_cpus(SH73A0_SCU_BASE, max_cpus); From 5705747c0c8f90aee5a433a94f58c9ffad8a5a37 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 17 Nov 2020 11:30:22 +0100 Subject: [PATCH 421/799] ARM: shmobile: sh73a0: Remove obsolete static mapping There are no more users of the statically mapped IOMEM region on SH-Mobile AG5. Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20201117103022.2136527-8-geert+renesas@glider.be --- arch/arm/mach-shmobile/setup-sh73a0.c | 19 ------------------- 1 file changed, 19 deletions(-) diff --git a/arch/arm/mach-shmobile/setup-sh73a0.c b/arch/arm/mach-shmobile/setup-sh73a0.c index e2fcfe1e4f24..890bf537b7de 100644 --- a/arch/arm/mach-shmobile/setup-sh73a0.c +++ b/arch/arm/mach-shmobile/setup-sh73a0.c @@ -22,24 +22,6 @@ #include "common.h" #include "sh73a0.h" -static struct map_desc sh73a0_io_desc[] __initdata = { - /* create a 1:1 identity mapping for 0xe6xxxxxx - * used by CPGA, INTC and PFC. - */ - { - .virtual = 0xe6000000, - .pfn = __phys_to_pfn(0xe6000000), - .length = 256 << 20, - .type = MT_DEVICE_NONSHARED - }, -}; - -static void __init sh73a0_map_io(void) -{ - debug_ll_io_init(); - iotable_init(sh73a0_io_desc, ARRAY_SIZE(sh73a0_io_desc)); -} - static void __init sh73a0_generic_init(void) { #ifdef CONFIG_CACHE_L2X0 @@ -55,7 +37,6 @@ static const char *const sh73a0_boards_compat_dt[] __initconst = { DT_MACHINE_START(SH73A0_DT, "Generic SH73A0 (Flattened Device Tree)") .smp = smp_ops(sh73a0_smp_ops), - .map_io = sh73a0_map_io, .init_machine = sh73a0_generic_init, .init_late = shmobile_init_late, .dt_compat = sh73a0_boards_compat_dt, From d4a617c9bbef94e4a776901cf12c95eafd54504a Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 17 Nov 2020 15:24:47 +0100 Subject: [PATCH 422/799] ARM: shmobile: Stop using __raw_*() I/O accessors MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit There is no reason to keep on using the __raw_{read,write}l() I/O accessors in Renesas ARM platform code. Switch to using the plain {read,write}l() I/O accessors, to have a chance that this works on big-endian. Suggested-by: Arnd Bergmann Signed-off-by: Geert Uytterhoeven Reviewed-by: Niklas Söderlund Link: https://lore.kernel.org/r/20201117142447.2205664-1-geert+renesas@glider.be --- arch/arm/mach-shmobile/platsmp-scu.c | 2 +- arch/arm/mach-shmobile/setup-r8a7778.c | 8 ++++---- arch/arm/mach-shmobile/setup-r8a7779.c | 14 +++++++------- arch/arm/mach-shmobile/smp-r8a7779.c | 2 +- arch/arm/mach-shmobile/smp-sh73a0.c | 10 +++++----- 5 files changed, 18 insertions(+), 18 deletions(-) diff --git a/arch/arm/mach-shmobile/platsmp-scu.c b/arch/arm/mach-shmobile/platsmp-scu.c index fcfcef1d1ae4..3849f71e6e12 100644 --- a/arch/arm/mach-shmobile/platsmp-scu.c +++ b/arch/arm/mach-shmobile/platsmp-scu.c @@ -64,7 +64,7 @@ static int shmobile_smp_scu_psr_core_disabled(int cpu) { unsigned long mask = SCU_PM_POWEROFF << (cpu * 8); - if ((__raw_readl(shmobile_scu_base + 8) & mask) == mask) + if ((readl(shmobile_scu_base + 8) & mask) == mask) return 1; return 0; diff --git a/arch/arm/mach-shmobile/setup-r8a7778.c b/arch/arm/mach-shmobile/setup-r8a7778.c index 819dbda47298..02cda9cada4c 100644 --- a/arch/arm/mach-shmobile/setup-r8a7778.c +++ b/arch/arm/mach-shmobile/setup-r8a7778.c @@ -31,12 +31,12 @@ static void __init r8a7778_init_irq_dt(void) irqchip_init(); /* route all interrupts to ARM */ - __raw_writel(0x73ffffff, base + INT2NTSR0); - __raw_writel(0xffffffff, base + INT2NTSR1); + writel(0x73ffffff, base + INT2NTSR0); + writel(0xffffffff, base + INT2NTSR1); /* unmask all known interrupts in INTCS2 */ - __raw_writel(0x08330773, base + INT2SMSKCR0); - __raw_writel(0x00311110, base + INT2SMSKCR1); + writel(0x08330773, base + INT2SMSKCR0); + writel(0x00311110, base + INT2SMSKCR1); iounmap(base); } diff --git a/arch/arm/mach-shmobile/setup-r8a7779.c b/arch/arm/mach-shmobile/setup-r8a7779.c index 446d40b50b7b..b6e282116d66 100644 --- a/arch/arm/mach-shmobile/setup-r8a7779.c +++ b/arch/arm/mach-shmobile/setup-r8a7779.c @@ -34,15 +34,15 @@ static void __init r8a7779_init_irq_dt(void) irqchip_init(); /* route all interrupts to ARM */ - __raw_writel(0xffffffff, base + INT2NTSR0); - __raw_writel(0x3fffffff, base + INT2NTSR1); + writel(0xffffffff, base + INT2NTSR0); + writel(0x3fffffff, base + INT2NTSR1); /* unmask all known interrupts in INTCS2 */ - __raw_writel(0xfffffff0, base + INT2SMSKCR0); - __raw_writel(0xfff7ffff, base + INT2SMSKCR1); - __raw_writel(0xfffbffdf, base + INT2SMSKCR2); - __raw_writel(0xbffffffc, base + INT2SMSKCR3); - __raw_writel(0x003fee3f, base + INT2SMSKCR4); + writel(0xfffffff0, base + INT2SMSKCR0); + writel(0xfff7ffff, base + INT2SMSKCR1); + writel(0xfffbffdf, base + INT2SMSKCR2); + writel(0xbffffffc, base + INT2SMSKCR3); + writel(0x003fee3f, base + INT2SMSKCR4); iounmap(base); } diff --git a/arch/arm/mach-shmobile/smp-r8a7779.c b/arch/arm/mach-shmobile/smp-r8a7779.c index f6713886ee16..1bc609986c16 100644 --- a/arch/arm/mach-shmobile/smp-r8a7779.c +++ b/arch/arm/mach-shmobile/smp-r8a7779.c @@ -41,7 +41,7 @@ static void __init r8a7779_smp_prepare_cpus(unsigned int max_cpus) void __iomem *base = ioremap(HPBREG_BASE, 0x1000); /* Map the reset vector (in headsmp-scu.S, headsmp.S) */ - __raw_writel(__pa(shmobile_boot_vector), base + AVECR); + writel(__pa(shmobile_boot_vector), base + AVECR); /* setup r8a7779 specific SCU bits */ shmobile_smp_scu_prepare_cpus(R8A7779_SCU_BASE, max_cpus); diff --git a/arch/arm/mach-shmobile/smp-sh73a0.c b/arch/arm/mach-shmobile/smp-sh73a0.c index 6d892d11d81c..453d48865029 100644 --- a/arch/arm/mach-shmobile/smp-sh73a0.c +++ b/arch/arm/mach-shmobile/smp-sh73a0.c @@ -34,10 +34,10 @@ static int sh73a0_boot_secondary(unsigned int cpu, struct task_struct *idle) unsigned int lcpu = cpu_logical_map(cpu); void __iomem *cpg2 = ioremap(CPG_BASE2, PAGE_SIZE); - if (((__raw_readl(cpg2 + PSTR) >> (4 * lcpu)) & 3) == 3) - __raw_writel(1 << lcpu, cpg2 + WUPCR); /* wake up */ + if (((readl(cpg2 + PSTR) >> (4 * lcpu)) & 3) == 3) + writel(1 << lcpu, cpg2 + WUPCR); /* wake up */ else - __raw_writel(1 << lcpu, cpg2 + SRESCR); /* reset */ + writel(1 << lcpu, cpg2 + SRESCR); /* reset */ iounmap(cpg2); return 0; } @@ -48,8 +48,8 @@ static void __init sh73a0_smp_prepare_cpus(unsigned int max_cpus) void __iomem *sysc = ioremap(SYSC_BASE, PAGE_SIZE); /* Map the reset vector (in headsmp.S) */ - __raw_writel(0, ap + APARMBAREA); /* 4k */ - __raw_writel(__pa(shmobile_boot_vector), sysc + SBAR); + writel(0, ap + APARMBAREA); /* 4k */ + writel(__pa(shmobile_boot_vector), sysc + SBAR); iounmap(sysc); iounmap(ap); From ef5704b535194fb98ee1ceb00f6952e2f01e39a6 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Fri, 20 Nov 2020 13:42:12 +0100 Subject: [PATCH 423/799] ARM: dts: ux500-golden: Add proper supplies to touchscreen This sets up the Atmel maXTouch touchscreen to use proper VDDA and VDD supplies as now supported by bindings and driver. Cc: Stephan Gerhold Cc: Nick Reitemeyer Cc: Nick Dyer Link: https://lore.kernel.org/r/20201120124212.1086063-1-linus.walleij@linaro.org Signed-off-by: Linus Walleij --- arch/arm/boot/dts/ste-ux500-samsung-golden.dts | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/ste-ux500-samsung-golden.dts b/arch/arm/boot/dts/ste-ux500-samsung-golden.dts index 939360c05713..496f9d3ba7b7 100644 --- a/arch/arm/boot/dts/ste-ux500-samsung-golden.dts +++ b/arch/arm/boot/dts/ste-ux500-samsung-golden.dts @@ -260,6 +260,11 @@ interrupt-parent = <&gpio6>; interrupts = <26 IRQ_TYPE_EDGE_FALLING>; + /* VDDA is "analog supply", 2.57-3.47 V */ + vdda-supply = <&ab8500_ldo_aux2_reg>; + /* VDD is "digital supply" 1.71-3.47V */ + vdd-supply = <&ab8500_ldo_aux5_reg>; + pinctrl-names = "default"; pinctrl-0 = <&tsp_default>; }; @@ -284,7 +289,6 @@ regulator-name = "vreg_tsp_a3v3"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; - regulator-always-on; /* FIXME */ }; ab8500_ldo_aux3 { @@ -301,7 +305,6 @@ regulator-name = "vreg_tsp_1v8"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; - regulator-always-on; /* FIXME */ }; ab8500_ldo_aux6 { From b2d91953b66c724eaf8d7f84f37c006d966f67ac Mon Sep 17 00:00:00 2001 From: Tomer Maimon Date: Thu, 19 Nov 2020 10:00:02 +0200 Subject: [PATCH 424/799] ARM: dts: add Nuvoton NPCM730 device tree Add Nuvoton NPCM730 SoC device tree. The Nuvoton NPCN730 SoC is a part of the Nuvoton NPCM7xx SoCs family. Signed-off-by: Tomer Maimon Reviewed-by: Benjamin Fair Link: https://lore.kernel.org/r/20201119080002.100342-1-tmaimon77@gmail.com' Signed-off-by: Arnd Bergmann --- arch/arm/boot/dts/nuvoton-npcm730.dtsi | 44 ++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) create mode 100644 arch/arm/boot/dts/nuvoton-npcm730.dtsi diff --git a/arch/arm/boot/dts/nuvoton-npcm730.dtsi b/arch/arm/boot/dts/nuvoton-npcm730.dtsi new file mode 100644 index 000000000000..86ec12ec2b50 --- /dev/null +++ b/arch/arm/boot/dts/nuvoton-npcm730.dtsi @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (c) 2020 Nuvoton Technology + +#include "nuvoton-common-npcm7xx.dtsi" + +/ { + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&gic>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + enable-method = "nuvoton,npcm750-smp"; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + clocks = <&clk NPCM7XX_CLK_CPU>; + clock-names = "clk_cpu"; + reg = <0>; + next-level-cache = <&l2>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + clocks = <&clk NPCM7XX_CLK_CPU>; + clock-names = "clk_cpu"; + reg = <1>; + next-level-cache = <&l2>; + }; + }; + + soc { + timer@3fe600 { + compatible = "arm,cortex-a9-twd-timer"; + reg = <0x3fe600 0x20>; + interrupts = ; + clocks = <&clk NPCM7XX_CLK_AHB>; + }; + }; +}; From a65183ff1535ed15c28c526f6b69ed03c21d34b4 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Thu, 5 Nov 2020 14:45:10 +0100 Subject: [PATCH 425/799] ARM: config: ux500: Update U8500 defconfig This updates the defconfig for the U8500 platform with some of the changes from the v5.9 and v5.10 kernel cycles: - No need to select the schedutil cpufreq governor because it is the default now. - Enable the CY8CTMA140 touchscreen as used on the Samsung Skomer GT-S7710. - Enable the Samsung S6E63M0 DSI panel as used on the Samsung Golden GT-I8810. - Enable the KTD253 backlight as used on the Samsung Skomer GT-S7710. - Drop CONFIG_USB as we only use the gadget mode of the MUSB driver. - Add selection of the CONFIG_LEDS_LP55XX_COMMON lest the LP5521 LEDs will not work. - Move the config entry for CONFIG_DEBUG_FS. Signed-off-by: Linus Walleij Cc: Stephan Gerhold Link: https://lore.kernel.org/r/20201105134510.1417639-1-linus.walleij@linaro.org' Signed-off-by: Arnd Bergmann --- arch/arm/configs/u8500_defconfig | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/arch/arm/configs/u8500_defconfig b/arch/arm/configs/u8500_defconfig index 28dd7cf56048..bcedfe1422aa 100644 --- a/arch/arm/configs/u8500_defconfig +++ b/arch/arm/configs/u8500_defconfig @@ -12,7 +12,6 @@ CONFIG_ARM_APPENDED_DTB=y CONFIG_ARM_ATAG_DTB_COMPAT=y CONFIG_CMDLINE="root=/dev/ram0 console=ttyAMA2,115200n8" CONFIG_CPU_FREQ=y -CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL=y CONFIG_CPU_FREQ_GOV_ONDEMAND=y CONFIG_CPUFREQ_DT=y CONFIG_CPU_IDLE=y @@ -60,6 +59,7 @@ CONFIG_KEYBOARD_TC3589X=y CONFIG_INPUT_TOUCHSCREEN=y CONFIG_TOUCHSCREEN_ATMEL_MXT=y CONFIG_TOUCHSCREEN_BU21013=y +CONFIG_TOUCHSCREEN_CY8CTMA140=y CONFIG_INPUT_MISC=y CONFIG_INPUT_AB8500_PONKEY=y CONFIG_INPUT_GPIO_VIBRA=y @@ -88,11 +88,13 @@ CONFIG_REGULATOR_GPIO=y CONFIG_DRM=y CONFIG_DRM_PANEL_NOVATEK_NT35510=y CONFIG_DRM_PANEL_SAMSUNG_S6D16D0=y +CONFIG_DRM_PANEL_SAMSUNG_S6E63M0=y +CONFIG_DRM_PANEL_SAMSUNG_S6E63M0_DSI=y CONFIG_DRM_PANEL_SONY_ACX424AKP=y CONFIG_DRM_LIMA=y CONFIG_DRM_MCDE=y CONFIG_BACKLIGHT_CLASS_DEVICE=y -CONFIG_BACKLIGHT_GENERIC=m +CONFIG_BACKLIGHT_KTD253=y CONFIG_BACKLIGHT_GPIO=y CONFIG_LOGO=y CONFIG_SOUND=y @@ -100,7 +102,6 @@ CONFIG_SND=y CONFIG_SND_SOC=y CONFIG_SND_SOC_UX500=y CONFIG_SND_SOC_UX500_MACH_MOP500=y -CONFIG_USB=y CONFIG_USB_MUSB_HDRC=y CONFIG_USB_MUSB_UX500=y CONFIG_MUSB_PIO_ONLY=y @@ -113,6 +114,7 @@ CONFIG_NEW_LEDS=y CONFIG_LEDS_CLASS=y CONFIG_LEDS_LM3530=y CONFIG_LEDS_GPIO=y +CONFIG_LEDS_LP55XX_COMMON=y CONFIG_LEDS_LP5521=y CONFIG_LEDS_TRIGGER_HEARTBEAT=y CONFIG_RTC_CLASS=y @@ -153,8 +155,8 @@ CONFIG_CRYPTO_DEV_UX500_HASH=y CONFIG_CRYPTO_DEV_UX500_DEBUG=y CONFIG_PRINTK_TIME=y CONFIG_DEBUG_INFO=y -CONFIG_DEBUG_FS=y CONFIG_MAGIC_SYSRQ=y +CONFIG_DEBUG_FS=y CONFIG_DEBUG_KERNEL=y # CONFIG_SCHED_DEBUG is not set # CONFIG_FTRACE is not set From 8195fceca0316c36c87db25750a5c5db84ded4e7 Mon Sep 17 00:00:00 2001 From: Grygorii Strashko Date: Fri, 30 Oct 2020 14:46:50 +0200 Subject: [PATCH 426/799] ARM: multi_v7_defconfig: ti: Enable networking options for nfs boot Enable networking options required for NFS boot on TI platforms, which is widely for automated test systems. - enable new TI CPSW switch driver and related NET_SWITCHDEV config - enable TI DP83867 phy - explicitly enable PTP clock support to ensure dependent networking drivers will stay built-in. vmlinux size changes: - before: text data bss dec hex filename 14703736 8024602 444976 23173314 16198c2 ./omap-arm/vmlinux - after: text data bss dec hex filename 14727271 8029150 444528 23200949 16204b5 ./omap-arm/vmlinux diff: 27635 (dec) Signed-off-by: Grygorii Strashko Reviewed-by: Nishanth Menon Cc: Tony Lindgren Link: https://lore.kernel.org/r/20201030124650.20349-1-grygorii.strashko@ti.com' Signed-off-by: Arnd Bergmann --- arch/arm/configs/multi_v7_defconfig | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig index a611b0c1e540..48a9cdec474a 100644 --- a/arch/arm/configs/multi_v7_defconfig +++ b/arch/arm/configs/multi_v7_defconfig @@ -154,6 +154,7 @@ CONFIG_INET6_IPCOMP=m CONFIG_IPV6_MIP6=m CONFIG_IPV6_TUNNEL=m CONFIG_IPV6_MULTIPLE_TABLES=y +CONFIG_NET_SWITCHDEV=y CONFIG_NET_DSA=m CONFIG_CAN=y CONFIG_CAN_AT91=m @@ -270,9 +271,12 @@ CONFIG_SNI_AVE=y CONFIG_STMMAC_ETH=y CONFIG_DWMAC_DWC_QOS_ETH=y CONFIG_TI_CPSW=y +CONFIG_TI_CPSW_SWITCHDEV=y +CONFIG_TI_CPTS=y CONFIG_XILINX_EMACLITE=y CONFIG_BROADCOM_PHY=y CONFIG_ICPLUS_PHY=y +CONFIG_DP83867_PHY=y CONFIG_MARVELL_PHY=y CONFIG_MICREL_PHY=y CONFIG_AT803X_PHY=y @@ -436,6 +440,7 @@ CONFIG_SPI_TEGRA20_SLINK=y CONFIG_SPI_XILINX=y CONFIG_SPI_SPIDEV=y CONFIG_SPMI=y +CONFIG_PTP_1588_CLOCK=y CONFIG_PINCTRL_AS3722=y CONFIG_PINCTRL_RZA2=y CONFIG_PINCTRL_STMFX=y From 2802821a66f99955afd75ec76209064bfb678697 Mon Sep 17 00:00:00 2001 From: Jonathan Marek Date: Mon, 23 Nov 2020 09:35:38 -0500 Subject: [PATCH 427/799] arm64: dts: qcom: fix serial output for sm8250-hdk The uart2 node has been renamed, apply the change to sm8250-hdk dts too so that serial output works. Fixes: 91ed0e90fc49 ("arm64: dts: qcom: add sm8250 hdk dts") Signed-off-by: Jonathan Marek Link: https://lore.kernel.org/r/20201123143538.14198-1-jonathan@marek.ca Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8250-hdk.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8250-hdk.dts b/arch/arm64/boot/dts/qcom/sm8250-hdk.dts index b5026e422aa6..c3a2c5aa6fe9 100644 --- a/arch/arm64/boot/dts/qcom/sm8250-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8250-hdk.dts @@ -17,7 +17,7 @@ compatible = "qcom,sm8250-hdk", "qcom,sm8250"; aliases { - serial0 = &uart2; + serial0 = &uart12; }; chosen { @@ -387,7 +387,7 @@ gpio-reserved-ranges = <28 4>, <40 4>; }; -&uart2 { +&uart12 { status = "okay"; }; From eaf7697b6febe2b086503f525f070d8e3ca1ea0f Mon Sep 17 00:00:00 2001 From: David Lechner Date: Mon, 12 Oct 2020 16:12:29 -0500 Subject: [PATCH 428/799] ARM: omap2plus_defconfig: Enable TI eQEP counter driver This enables the TI eQEP counter driver that is used by BeagleBone Blue. Signed-off-by: David Lechner Signed-off-by: Tony Lindgren --- arch/arm/configs/omap2plus_defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/configs/omap2plus_defconfig b/arch/arm/configs/omap2plus_defconfig index 2ab9024cb6e3..77716f500813 100644 --- a/arch/arm/configs/omap2plus_defconfig +++ b/arch/arm/configs/omap2plus_defconfig @@ -539,6 +539,8 @@ CONFIG_PHY_DM816X_USB=m CONFIG_OMAP_USB2=m CONFIG_TI_PIPE3=y CONFIG_TWL4030_USB=m +CONFIG_COUNTER=m +CONFIG_TI_EQEP=m CONFIG_EXT2_FS=y CONFIG_EXT3_FS=y CONFIG_EXT4_FS_SECURITY=y From 5ba6291086d2ae8006be9e0f19bf2001a85c9dc1 Mon Sep 17 00:00:00 2001 From: Cristian Birsan Date: Wed, 18 Nov 2020 14:00:17 +0200 Subject: [PATCH 429/799] ARM: dts: at91: sam9x60: add pincontrol for USB Host The pincontrol node is needed for USB Host since Linux v5.7-rc1. Without it the driver probes but VBus is not powered because of wrong pincontrol configuration. Fixes: 1e5f532c2737 ("ARM: dts: at91: sam9x60: add device tree for soc and board") Signed-off-by: Cristian Birsan Signed-off-by: Alexandre Belloni Acked-by: Ludovic Desroches Link: https://lore.kernel.org/r/20201118120019.1257580-2-cristian.birsan@microchip.com --- arch/arm/boot/dts/at91-sam9x60ek.dts | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm/boot/dts/at91-sam9x60ek.dts b/arch/arm/boot/dts/at91-sam9x60ek.dts index eae28b82c7fd..0e3b6147069f 100644 --- a/arch/arm/boot/dts/at91-sam9x60ek.dts +++ b/arch/arm/boot/dts/at91-sam9x60ek.dts @@ -569,6 +569,13 @@ atmel,pins = ; }; }; + + usb1 { + pinctrl_usb_default: usb_default { + atmel,pins = ; + }; + }; }; /* pinctrl */ &pmc { @@ -684,6 +691,8 @@ atmel,vbus-gpio = <0 &pioD 15 GPIO_ACTIVE_HIGH &pioD 16 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_default>; status = "okay"; }; From be4dd2d448816a27c1446f8f37fce375daf64148 Mon Sep 17 00:00:00 2001 From: Cristian Birsan Date: Wed, 18 Nov 2020 14:00:18 +0200 Subject: [PATCH 430/799] ARM: dts: at91: sama5d4_xplained: add pincontrol for USB Host The pincontrol node is needed for USB Host since Linux v5.7-rc1. Without it the driver probes but VBus is not powered because of wrong pincontrol configuration. Fixes: 38153a017896f ("ARM: at91/dt: sama5d4: add dts for sama5d4 xplained board") Signed-off-by: Cristian Birsan Signed-off-by: Alexandre Belloni Acked-by: Ludovic Desroches Link: https://lore.kernel.org/r/20201118120019.1257580-3-cristian.birsan@microchip.com --- arch/arm/boot/dts/at91-sama5d4_xplained.dts | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/boot/dts/at91-sama5d4_xplained.dts b/arch/arm/boot/dts/at91-sama5d4_xplained.dts index e5974a17374c..0b3ad1b580b8 100644 --- a/arch/arm/boot/dts/at91-sama5d4_xplained.dts +++ b/arch/arm/boot/dts/at91-sama5d4_xplained.dts @@ -134,6 +134,11 @@ atmel,pins = ; }; + pinctrl_usb_default: usb_default { + atmel,pins = + ; + }; pinctrl_key_gpio: key_gpio_0 { atmel,pins = ; @@ -159,6 +164,8 @@ &pioE 11 GPIO_ACTIVE_HIGH &pioE 14 GPIO_ACTIVE_HIGH >; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_default>; status = "okay"; }; From e1062fa7292f1e3744db0a487c4ac0109e09b03d Mon Sep 17 00:00:00 2001 From: Cristian Birsan Date: Wed, 18 Nov 2020 14:00:19 +0200 Subject: [PATCH 431/799] ARM: dts: at91: sama5d3_xplained: add pincontrol for USB Host The pincontrol node is needed for USB Host since Linux v5.7-rc1. Without it the driver probes but VBus is not powered because of wrong pincontrol configuration. Fixes: b7c2b61570798 ("ARM: at91: add Atmel's SAMA5D3 Xplained board") Signed-off-by: Cristian Birsan Signed-off-by: Alexandre Belloni Acked-by: Ludovic Desroches Link: https://lore.kernel.org/r/20201118120019.1257580-4-cristian.birsan@microchip.com --- arch/arm/boot/dts/at91-sama5d3_xplained.dts | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/boot/dts/at91-sama5d3_xplained.dts b/arch/arm/boot/dts/at91-sama5d3_xplained.dts index cf13632edd44..5179258f9247 100644 --- a/arch/arm/boot/dts/at91-sama5d3_xplained.dts +++ b/arch/arm/boot/dts/at91-sama5d3_xplained.dts @@ -242,6 +242,11 @@ atmel,pins = ; /* PE9, conflicts with A9 */ }; + pinctrl_usb_default: usb_default { + atmel,pins = + ; + }; }; }; }; @@ -259,6 +264,8 @@ &pioE 3 GPIO_ACTIVE_LOW &pioE 4 GPIO_ACTIVE_LOW >; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_default>; status = "okay"; }; From 30ea026e33c6dda48849d9fe0d15c1d280a92d53 Mon Sep 17 00:00:00 2001 From: Zhen Lei Date: Mon, 12 Oct 2020 14:12:16 +0800 Subject: [PATCH 432/799] ARM: dts: hisilicon: fix errors detected by snps-dw-apb-uart.yaml 1. Change node name to match '^serial(@[0-9a-f,]+)*$' 2. Change clock-names to "baudclk", "apb_pclk". Both of them use the same clock. Signed-off-by: Zhen Lei Signed-off-by: Wei Xu --- arch/arm/boot/dts/hip01.dtsi | 24 ++++++++++++------------ arch/arm/boot/dts/hip04-d01.dts | 2 +- arch/arm/boot/dts/hip04.dtsi | 6 +++--- 3 files changed, 16 insertions(+), 16 deletions(-) diff --git a/arch/arm/boot/dts/hip01.dtsi b/arch/arm/boot/dts/hip01.dtsi index 975d39828405..fd09e6d9309c 100644 --- a/arch/arm/boot/dts/hip01.dtsi +++ b/arch/arm/boot/dts/hip01.dtsi @@ -41,41 +41,41 @@ compatible = "simple-bus"; ranges; - uart0: uart@10001000 { + uart0: serial@10001000 { compatible = "snps,dw-apb-uart"; reg = <0x10001000 0x1000>; - clocks = <&hisi_refclk144mhz>; - clock-names = "apb_pclk"; + clocks = <&hisi_refclk144mhz>, <&hisi_refclk144mhz>; + clock-names = "baudclk", "apb_pclk"; reg-shift = <2>; interrupts = <0 32 4>; status = "disabled"; }; - uart1: uart@10002000 { + uart1: serial@10002000 { compatible = "snps,dw-apb-uart"; reg = <0x10002000 0x1000>; - clocks = <&hisi_refclk144mhz>; - clock-names = "apb_pclk"; + clocks = <&hisi_refclk144mhz>, <&hisi_refclk144mhz>; + clock-names = "baudclk", "apb_pclk"; reg-shift = <2>; interrupts = <0 33 4>; status = "disabled"; }; - uart2: uart@10003000 { + uart2: serial@10003000 { compatible = "snps,dw-apb-uart"; reg = <0x10003000 0x1000>; - clocks = <&hisi_refclk144mhz>; - clock-names = "apb_pclk"; + clocks = <&hisi_refclk144mhz>, <&hisi_refclk144mhz>; + clock-names = "baudclk", "apb_pclk"; reg-shift = <2>; interrupts = <0 34 4>; status = "disabled"; }; - uart3: uart@10006000 { + uart3: serial@10006000 { compatible = "snps,dw-apb-uart"; reg = <0x10006000 0x1000>; - clocks = <&hisi_refclk144mhz>; - clock-names = "apb_pclk"; + clocks = <&hisi_refclk144mhz>, <&hisi_refclk144mhz>; + clock-names = "baudclk", "apb_pclk"; reg-shift = <2>; interrupts = <0 4 4>; status = "disabled"; diff --git a/arch/arm/boot/dts/hip04-d01.dts b/arch/arm/boot/dts/hip04-d01.dts index 9019e0d2ef60..f5691dbc26d2 100644 --- a/arch/arm/boot/dts/hip04-d01.dts +++ b/arch/arm/boot/dts/hip04-d01.dts @@ -22,7 +22,7 @@ }; soc { - uart0: uart@4007000 { + uart0: serial@4007000 { status = "ok"; }; }; diff --git a/arch/arm/boot/dts/hip04.dtsi b/arch/arm/boot/dts/hip04.dtsi index 555bc6b6720f..bccf5ba3d855 100644 --- a/arch/arm/boot/dts/hip04.dtsi +++ b/arch/arm/boot/dts/hip04.dtsi @@ -250,12 +250,12 @@ <0 79 4>; }; - uart0: uart@4007000 { + uart0: serial@4007000 { compatible = "snps,dw-apb-uart"; reg = <0x4007000 0x1000>; interrupts = <0 381 4>; - clocks = <&clk_168m>; - clock-names = "uartclk"; + clocks = <&clk_168m>, <&clk_168m>; + clock-names = "baudclk", "apb_pclk"; reg-shift = <2>; status = "disabled"; }; From e5e225fd495ef1dffc64b81b2094e427f9cc4016 Mon Sep 17 00:00:00 2001 From: Zhen Lei Date: Mon, 12 Oct 2020 14:12:17 +0800 Subject: [PATCH 433/799] ARM: dts: hisilicon: fix errors detected by pl011.yaml 1. Change node name to match '^serial(@[0-9a-f,]+)*$' 2. Change clock-names to "uartclk", "apb_pclk". Both of them use the same clock. 3. Change pinctrl-names to "default", "sleep". Signed-off-by: Zhen Lei Signed-off-by: Wei Xu --- arch/arm/boot/dts/hi3519.dtsi | 20 +++++++++---------- arch/arm/boot/dts/hi3620-hi4511.dts | 20 +++++++++---------- arch/arm/boot/dts/hi3620.dtsi | 30 ++++++++++++++--------------- arch/arm/boot/dts/hisi-x5hd2.dtsi | 30 ++++++++++++++--------------- 4 files changed, 50 insertions(+), 50 deletions(-) diff --git a/arch/arm/boot/dts/hi3519.dtsi b/arch/arm/boot/dts/hi3519.dtsi index 410409a0ed66..630753c0d704 100644 --- a/arch/arm/boot/dts/hi3519.dtsi +++ b/arch/arm/boot/dts/hi3519.dtsi @@ -52,8 +52,8 @@ compatible = "arm,pl011", "arm,primecell"; reg = <0x12100000 0x1000>; interrupts = ; - clocks = <&crg HI3519_UART0_CLK>; - clock-names = "apb_pclk"; + clocks = <&crg HI3519_UART0_CLK>, <&crg HI3519_UART0_CLK>; + clock-names = "uartclk", "apb_pclk"; status = "disable"; }; @@ -61,8 +61,8 @@ compatible = "arm,pl011", "arm,primecell"; reg = <0x12101000 0x1000>; interrupts = ; - clocks = <&crg HI3519_UART1_CLK>; - clock-names = "apb_pclk"; + clocks = <&crg HI3519_UART1_CLK>, <&crg HI3519_UART1_CLK>; + clock-names = "uartclk", "apb_pclk"; status = "disable"; }; @@ -70,8 +70,8 @@ compatible = "arm,pl011", "arm,primecell"; reg = <0x12102000 0x1000>; interrupts = ; - clocks = <&crg HI3519_UART2_CLK>; - clock-names = "apb_pclk"; + clocks = <&crg HI3519_UART2_CLK>, <&crg HI3519_UART2_CLK>; + clock-names = "uartclk", "apb_pclk"; status = "disable"; }; @@ -79,8 +79,8 @@ compatible = "arm,pl011", "arm,primecell"; reg = <0x12103000 0x1000>; interrupts = ; - clocks = <&crg HI3519_UART3_CLK>; - clock-names = "apb_pclk"; + clocks = <&crg HI3519_UART3_CLK>, <&crg HI3519_UART3_CLK>; + clock-names = "uartclk", "apb_pclk"; status = "disable"; }; @@ -88,8 +88,8 @@ compatible = "arm,pl011", "arm,primecell"; reg = <0x12104000 0x1000>; interrupts = ; - clocks = <&crg HI3519_UART4_CLK>; - clock-names = "apb_pclk"; + clocks = <&crg HI3519_UART4_CLK>, <&crg HI3519_UART4_CLK>; + clock-names = "uartclk", "apb_pclk"; status = "disable"; }; diff --git a/arch/arm/boot/dts/hi3620-hi4511.dts b/arch/arm/boot/dts/hi3620-hi4511.dts index 8c703c3f2fe0..1c62bdcca647 100644 --- a/arch/arm/boot/dts/hi3620-hi4511.dts +++ b/arch/arm/boot/dts/hi3620-hi4511.dts @@ -27,36 +27,36 @@ status = "ok"; }; - uart0: uart@b00000 { /* console */ - pinctrl-names = "default", "idle"; + uart0: serial@b00000 { /* console */ + pinctrl-names = "default", "sleep"; pinctrl-0 = <&uart0_pmx_func &uart0_cfg_func>; pinctrl-1 = <&uart0_pmx_idle &uart0_cfg_idle>; status = "ok"; }; - uart1: uart@b01000 { /* modem */ - pinctrl-names = "default", "idle"; + uart1: serial@b01000 { /* modem */ + pinctrl-names = "default", "sleep"; pinctrl-0 = <&uart1_pmx_func &uart1_cfg_func>; pinctrl-1 = <&uart1_pmx_idle &uart1_cfg_idle>; status = "ok"; }; - uart2: uart@b02000 { /* audience */ - pinctrl-names = "default", "idle"; + uart2: serial@b02000 { /* audience */ + pinctrl-names = "default", "sleep"; pinctrl-0 = <&uart2_pmx_func &uart2_cfg_func>; pinctrl-1 = <&uart2_pmx_idle &uart2_cfg_idle>; status = "ok"; }; - uart3: uart@b03000 { - pinctrl-names = "default", "idle"; + uart3: serial@b03000 { + pinctrl-names = "default", "sleep"; pinctrl-0 = <&uart3_pmx_func &uart3_cfg_func>; pinctrl-1 = <&uart3_pmx_idle &uart3_cfg_idle>; status = "ok"; }; - uart4: uart@b04000 { - pinctrl-names = "default", "idle"; + uart4: serial@b04000 { + pinctrl-names = "default", "sleep"; pinctrl-0 = <&uart4_pmx_func &uart4_cfg_func>; pinctrl-1 = <&uart4_pmx_idle &uart4_cfg_func>; status = "ok"; diff --git a/arch/arm/boot/dts/hi3620.dtsi b/arch/arm/boot/dts/hi3620.dtsi index f683440ee569..d41378391e4c 100644 --- a/arch/arm/boot/dts/hi3620.dtsi +++ b/arch/arm/boot/dts/hi3620.dtsi @@ -172,48 +172,48 @@ interrupts = <1 13 0xf01>; }; - uart0: uart@b00000 { + uart0: serial@b00000 { compatible = "arm,pl011", "arm,primecell"; reg = <0xb00000 0x1000>; interrupts = <0 20 4>; - clocks = <&clock HI3620_UARTCLK0>; - clock-names = "apb_pclk"; + clocks = <&clock HI3620_UARTCLK0>, <&clock HI3620_UARTCLK0>; + clock-names = "uartclk", "apb_pclk"; status = "disabled"; }; - uart1: uart@b01000 { + uart1: serial@b01000 { compatible = "arm,pl011", "arm,primecell"; reg = <0xb01000 0x1000>; interrupts = <0 21 4>; - clocks = <&clock HI3620_UARTCLK1>; - clock-names = "apb_pclk"; + clocks = <&clock HI3620_UARTCLK1>, <&clock HI3620_UARTCLK1>; + clock-names = "uartclk", "apb_pclk"; status = "disabled"; }; - uart2: uart@b02000 { + uart2: serial@b02000 { compatible = "arm,pl011", "arm,primecell"; reg = <0xb02000 0x1000>; interrupts = <0 22 4>; - clocks = <&clock HI3620_UARTCLK2>; - clock-names = "apb_pclk"; + clocks = <&clock HI3620_UARTCLK2>, <&clock HI3620_UARTCLK2>; + clock-names = "uartclk", "apb_pclk"; status = "disabled"; }; - uart3: uart@b03000 { + uart3: serial@b03000 { compatible = "arm,pl011", "arm,primecell"; reg = <0xb03000 0x1000>; interrupts = <0 23 4>; - clocks = <&clock HI3620_UARTCLK3>; - clock-names = "apb_pclk"; + clocks = <&clock HI3620_UARTCLK3>, <&clock HI3620_UARTCLK3>; + clock-names = "uartclk", "apb_pclk"; status = "disabled"; }; - uart4: uart@b04000 { + uart4: serial@b04000 { compatible = "arm,pl011", "arm,primecell"; reg = <0xb04000 0x1000>; interrupts = <0 24 4>; - clocks = <&clock HI3620_UARTCLK4>; - clock-names = "apb_pclk"; + clocks = <&clock HI3620_UARTCLK4>, <&clock HI3620_UARTCLK4>; + clock-names = "uartclk", "apb_pclk"; status = "disabled"; }; diff --git a/arch/arm/boot/dts/hisi-x5hd2.dtsi b/arch/arm/boot/dts/hisi-x5hd2.dtsi index e2dbf1d8a67b..f645487402f6 100644 --- a/arch/arm/boot/dts/hisi-x5hd2.dtsi +++ b/arch/arm/boot/dts/hisi-x5hd2.dtsi @@ -86,48 +86,48 @@ status = "disabled"; }; - uart0: uart@b00000 { + uart0: serial@b00000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x00b00000 0x1000>; interrupts = <0 49 4>; - clocks = <&clock HIX5HD2_FIXED_83M>; - clock-names = "apb_pclk"; + clocks = <&clock HIX5HD2_FIXED_83M>, <&clock HIX5HD2_FIXED_83M>; + clock-names = "uartclk", "apb_pclk"; status = "disabled"; }; - uart1: uart@6000 { + uart1: serial@6000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x00006000 0x1000>; interrupts = <0 50 4>; - clocks = <&clock HIX5HD2_FIXED_83M>; - clock-names = "apb_pclk"; + clocks = <&clock HIX5HD2_FIXED_83M>, <&clock HIX5HD2_FIXED_83M>; + clock-names = "uartclk", "apb_pclk"; status = "disabled"; }; - uart2: uart@b02000 { + uart2: serial@b02000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x00b02000 0x1000>; interrupts = <0 51 4>; - clocks = <&clock HIX5HD2_FIXED_83M>; - clock-names = "apb_pclk"; + clocks = <&clock HIX5HD2_FIXED_83M>, <&clock HIX5HD2_FIXED_83M>; + clock-names = "uartclk", "apb_pclk"; status = "disabled"; }; - uart3: uart@b03000 { + uart3: serial@b03000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x00b03000 0x1000>; interrupts = <0 52 4>; - clocks = <&clock HIX5HD2_FIXED_83M>; - clock-names = "apb_pclk"; + clocks = <&clock HIX5HD2_FIXED_83M>, <&clock HIX5HD2_FIXED_83M>; + clock-names = "uartclk", "apb_pclk"; status = "disabled"; }; - uart4: uart@b04000 { + uart4: serial@b04000 { compatible = "arm,pl011", "arm,primecell"; reg = <0xb04000 0x1000>; interrupts = <0 53 4>; - clocks = <&clock HIX5HD2_FIXED_83M>; - clock-names = "apb_pclk"; + clocks = <&clock HIX5HD2_FIXED_83M>, <&clock HIX5HD2_FIXED_83M>; + clock-names = "uartclk", "apb_pclk"; status = "disabled"; }; From 64f5b52554a1de47a53972a47b9b58d8d66ee5aa Mon Sep 17 00:00:00 2001 From: Zhen Lei Date: Mon, 12 Oct 2020 14:12:18 +0800 Subject: [PATCH 434/799] ARM: dts: hisilicon: fix errors detected by usb yaml 1. Change node name to match '^usb(@.*)?' These errors are detected by generic-ehci.yaml and generic-ohci.yaml. Signed-off-by: Zhen Lei Signed-off-by: Wei Xu --- arch/arm/boot/dts/hisi-x5hd2.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/hisi-x5hd2.dtsi b/arch/arm/boot/dts/hisi-x5hd2.dtsi index f645487402f6..0c1708945813 100644 --- a/arch/arm/boot/dts/hisi-x5hd2.dtsi +++ b/arch/arm/boot/dts/hisi-x5hd2.dtsi @@ -453,14 +453,14 @@ status = "disabled"; }; - usb0: ehci@1890000 { + usb0: usb@1890000 { compatible = "generic-ehci"; reg = <0x1890000 0x1000>; interrupts = <0 66 4>; clocks = <&clock HIX5HD2_USB_CLK>; }; - usb1: ohci@1880000 { + usb1: usb@1880000 { compatible = "generic-ohci"; reg = <0x1880000 0x1000>; interrupts = <0 67 4>; From 8e9e8dd7ce093344a89792deaeb6caedde636dcf Mon Sep 17 00:00:00 2001 From: Zhen Lei Date: Mon, 12 Oct 2020 14:12:19 +0800 Subject: [PATCH 435/799] ARM: dts: hisilicon: fix errors detected by simple-bus.yaml Change bus node name from "amba" to "amba-bus" to match '^([a-z][a-z0-9\\-]+-bus|bus|soc|axi|ahb|apb)(@[0-9a-f]+)?$' Signed-off-by: Zhen Lei Signed-off-by: Wei Xu --- arch/arm/boot/dts/hi3620-hi4511.dts | 2 +- arch/arm/boot/dts/hi3620.dtsi | 2 +- arch/arm/boot/dts/hip01.dtsi | 2 +- arch/arm/boot/dts/hisi-x5hd2.dtsi | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/hi3620-hi4511.dts b/arch/arm/boot/dts/hi3620-hi4511.dts index 1c62bdcca647..29eedc7fef98 100644 --- a/arch/arm/boot/dts/hi3620-hi4511.dts +++ b/arch/arm/boot/dts/hi3620-hi4511.dts @@ -22,7 +22,7 @@ reg = <0x40000000 0x20000000>; }; - amba { + amba-bus { dual_timer0: dual_timer@800000 { status = "ok"; }; diff --git a/arch/arm/boot/dts/hi3620.dtsi b/arch/arm/boot/dts/hi3620.dtsi index d41378391e4c..905900bf3e82 100644 --- a/arch/arm/boot/dts/hi3620.dtsi +++ b/arch/arm/boot/dts/hi3620.dtsi @@ -63,7 +63,7 @@ }; }; - amba { + amba-bus { #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm/boot/dts/hip01.dtsi b/arch/arm/boot/dts/hip01.dtsi index fd09e6d9309c..2a7963605390 100644 --- a/arch/arm/boot/dts/hip01.dtsi +++ b/arch/arm/boot/dts/hip01.dtsi @@ -35,7 +35,7 @@ interrupt-parent = <&gic>; ranges = <0 0x10000000 0x20000000>; - amba { + amba-bus { #address-cells = <1>; #size-cells = <1>; compatible = "simple-bus"; diff --git a/arch/arm/boot/dts/hisi-x5hd2.dtsi b/arch/arm/boot/dts/hisi-x5hd2.dtsi index 0c1708945813..8fdfde492919 100644 --- a/arch/arm/boot/dts/hisi-x5hd2.dtsi +++ b/arch/arm/boot/dts/hisi-x5hd2.dtsi @@ -30,7 +30,7 @@ interrupt-parent = <&gic>; ranges = <0 0xf8000000 0x8000000>; - amba { + amba-bus { #address-cells = <1>; #size-cells = <1>; compatible = "simple-bus"; From e0b09c35ae072be666bdd847dddf9a51bd4d57dc Mon Sep 17 00:00:00 2001 From: Zhen Lei Date: Mon, 12 Oct 2020 14:12:20 +0800 Subject: [PATCH 436/799] ARM: dts: hisilicon: fix errors detected by root-node.yaml Make the memory node name match the regex "^memory(@[0-9a-f]+)?$" which is described in memory.yaml. Otherwise, it will be treated as root node, and misreported by root-node.yaml. Errors misreported by root-node.yaml: /: memory: False schema does not allow {'device_type': ['memory'], 'reg': Signed-off-by: Zhen Lei Signed-off-by: Wei Xu --- arch/arm/boot/dts/hi3519-demb.dts | 2 +- arch/arm/boot/dts/hi3620-hi4511.dts | 2 +- arch/arm/boot/dts/hip01-ca9x2.dts | 2 +- arch/arm/boot/dts/hisi-x5hd2-dkb.dts | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/hi3519-demb.dts b/arch/arm/boot/dts/hi3519-demb.dts index 64f8ed126931..f473fa22e9ce 100644 --- a/arch/arm/boot/dts/hi3519-demb.dts +++ b/arch/arm/boot/dts/hi3519-demb.dts @@ -14,7 +14,7 @@ serial0 = &uart0; }; - memory { + memory@80000000 { device_type = "memory"; reg = <0x80000000 0x40000000>; }; diff --git a/arch/arm/boot/dts/hi3620-hi4511.dts b/arch/arm/boot/dts/hi3620-hi4511.dts index 29eedc7fef98..ce356c469e1e 100644 --- a/arch/arm/boot/dts/hi3620-hi4511.dts +++ b/arch/arm/boot/dts/hi3620-hi4511.dts @@ -17,7 +17,7 @@ stdout-path = "serial0:115200n8"; }; - memory { + memory@40000000 { device_type = "memory"; reg = <0x40000000 0x20000000>; }; diff --git a/arch/arm/boot/dts/hip01-ca9x2.dts b/arch/arm/boot/dts/hip01-ca9x2.dts index f05e74eacfe0..031476304d94 100644 --- a/arch/arm/boot/dts/hip01-ca9x2.dts +++ b/arch/arm/boot/dts/hip01-ca9x2.dts @@ -37,7 +37,7 @@ }; }; - memory { + memory@80000000 { device_type = "memory"; reg = <0x80000000 0x80000000>; }; diff --git a/arch/arm/boot/dts/hisi-x5hd2-dkb.dts b/arch/arm/boot/dts/hisi-x5hd2-dkb.dts index d55e9cd3b12b..22b122d3f514 100644 --- a/arch/arm/boot/dts/hisi-x5hd2-dkb.dts +++ b/arch/arm/boot/dts/hisi-x5hd2-dkb.dts @@ -35,7 +35,7 @@ }; }; - memory { + memory@0 { device_type = "memory"; reg = <0x00000000 0x80000000>; }; From 05484c171d39433daa8b75c0c4c5fb454091e9b7 Mon Sep 17 00:00:00 2001 From: Zhen Lei Date: Mon, 12 Oct 2020 14:12:21 +0800 Subject: [PATCH 437/799] ARM: dts: hisilicon: fix errors detected by synopsys-dw-mshc.yaml Look at the clock-names schema defined in synopsys-dw-mshc.yaml: clock-names: items: - const: biu - const: ciu The "biu" needs to be placed before the "ciu". Signed-off-by: Zhen Lei Signed-off-by: Wei Xu --- arch/arm/boot/dts/hisi-x5hd2.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/hisi-x5hd2.dtsi b/arch/arm/boot/dts/hisi-x5hd2.dtsi index 8fdfde492919..9a513893758b 100644 --- a/arch/arm/boot/dts/hisi-x5hd2.dtsi +++ b/arch/arm/boot/dts/hisi-x5hd2.dtsi @@ -423,7 +423,7 @@ interrupts = <0 35 4>; clocks = <&clock HIX5HD2_MMC_CIU_RST>, <&clock HIX5HD2_MMC_BIU_CLK>; - clock-names = "ciu", "biu"; + clock-names = "biu", "ciu"; }; sd: mmc@1820000 { @@ -432,7 +432,7 @@ interrupts = <0 34 4>; clocks = <&clock HIX5HD2_SD_CIU_RST>, <&clock HIX5HD2_SD_BIU_CLK>; - clock-names = "ciu","biu"; + clock-names = "biu", "ciu"; }; gmac0: ethernet@1840000 { From 4c246408f0bdbc4100c95a5dad9e0688b4a3cfd0 Mon Sep 17 00:00:00 2001 From: Zhen Lei Date: Mon, 12 Oct 2020 14:12:22 +0800 Subject: [PATCH 438/799] ARM: dts: hisilicon: fix errors detected by spi-pl022.yaml 1. Change clock-names to "sspclk", "apb_pclk". Both of them use the same clock. Signed-off-by: Zhen Lei Signed-off-by: Wei Xu --- arch/arm/boot/dts/hi3519.dtsi | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm/boot/dts/hi3519.dtsi b/arch/arm/boot/dts/hi3519.dtsi index 630753c0d704..c524c854d319 100644 --- a/arch/arm/boot/dts/hi3519.dtsi +++ b/arch/arm/boot/dts/hi3519.dtsi @@ -127,8 +127,8 @@ compatible = "arm,pl022", "arm,primecell"; reg = <0x12120000 0x1000>; interrupts = ; - clocks = <&crg HI3519_SPI0_CLK>; - clock-names = "apb_pclk"; + clocks = <&crg HI3519_SPI0_CLK>, <&crg HI3519_SPI0_CLK>; + clock-names = "sspclk", "apb_pclk"; num-cs = <1>; #address-cells = <1>; #size-cells = <0>; @@ -139,8 +139,8 @@ compatible = "arm,pl022", "arm,primecell"; reg = <0x12121000 0x1000>; interrupts = ; - clocks = <&crg HI3519_SPI1_CLK>; - clock-names = "apb_pclk"; + clocks = <&crg HI3519_SPI1_CLK>, <&crg HI3519_SPI1_CLK>; + clock-names = "sspclk", "apb_pclk"; num-cs = <1>; #address-cells = <1>; #size-cells = <0>; @@ -151,8 +151,8 @@ compatible = "arm,pl022", "arm,primecell"; reg = <0x12122000 0x1000>; interrupts = ; - clocks = <&crg HI3519_SPI2_CLK>; - clock-names = "apb_pclk"; + clocks = <&crg HI3519_SPI2_CLK>, <&crg HI3519_SPI2_CLK>; + clock-names = "sspclk", "apb_pclk"; num-cs = <1>; #address-cells = <1>; #size-cells = <0>; From d48b6ef74ab06c5b29bd9ee9e830bdc639b196ee Mon Sep 17 00:00:00 2001 From: Zhen Lei Date: Mon, 12 Oct 2020 14:12:23 +0800 Subject: [PATCH 439/799] ARM: dts: hisilicon: fix errors detected by syscon.yaml The DT binding for system controller is not allowed to contain only the compatible string "syscon", the Hisilicon peripheral subsystem controller should add compatible string "hisilicon,peri-subctrl". Otherwise, the error "compatible: ['syscon'] is too short" will be reported. Signed-off-by: Zhen Lei Signed-off-by: Wei Xu --- arch/arm/boot/dts/hisi-x5hd2.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/hisi-x5hd2.dtsi b/arch/arm/boot/dts/hisi-x5hd2.dtsi index 9a513893758b..97211385dc89 100644 --- a/arch/arm/boot/dts/hisi-x5hd2.dtsi +++ b/arch/arm/boot/dts/hisi-x5hd2.dtsi @@ -468,7 +468,7 @@ }; peripheral_ctrl: syscon@a20000 { - compatible = "syscon"; + compatible = "hisilicon,peri-subctrl", "syscon"; reg = <0xa20000 0x1000>; }; From c25b846425e34929c6201ef0592444147e65fbb3 Mon Sep 17 00:00:00 2001 From: Zhen Lei Date: Mon, 12 Oct 2020 21:17:29 +0800 Subject: [PATCH 440/799] arm64: dts: hisilicon: normalize the node name of the ITS devices Change the node name of the ITS devices to match "^(msi-controller|gic-its|interrupt-controller)@[0-9a-f]+$". Although "interrupt-controller" is allowed, but "msi-controller" is preferred. Otherwise, "interrupt-controller@b7000000: False schema does not allow" will be reported by arm,gic-v3.yaml. Signed-off-by: Zhen Lei Signed-off-by: Wei Xu --- arch/arm64/boot/dts/hisilicon/hip05.dtsi | 8 ++++---- arch/arm64/boot/dts/hisilicon/hip06.dtsi | 2 +- arch/arm64/boot/dts/hisilicon/hip07.dtsi | 16 ++++++++-------- 3 files changed, 13 insertions(+), 13 deletions(-) diff --git a/arch/arm64/boot/dts/hisilicon/hip05.dtsi b/arch/arm64/boot/dts/hisilicon/hip05.dtsi index bc49955360db..f7e3a7af4634 100644 --- a/arch/arm64/boot/dts/hisilicon/hip05.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hip05.dtsi @@ -242,28 +242,28 @@ <0x0 0xfe020000 0 0x10000>; /* GICV */ interrupts = ; - its_peri: interrupt-controller@8c000000 { + its_peri: msi-controller@8c000000 { compatible = "arm,gic-v3-its"; msi-controller; #msi-cells = <1>; reg = <0x0 0x8c000000 0x0 0x40000>; }; - its_m3: interrupt-controller@a3000000 { + its_m3: msi-controller@a3000000 { compatible = "arm,gic-v3-its"; msi-controller; #msi-cells = <1>; reg = <0x0 0xa3000000 0x0 0x40000>; }; - its_pcie: interrupt-controller@b7000000 { + its_pcie: msi-controller@b7000000 { compatible = "arm,gic-v3-its"; msi-controller; #msi-cells = <1>; reg = <0x0 0xb7000000 0x0 0x40000>; }; - its_dsa: interrupt-controller@c6000000 { + its_dsa: msi-controller@c6000000 { compatible = "arm,gic-v3-its"; msi-controller; #msi-cells = <1>; diff --git a/arch/arm64/boot/dts/hisilicon/hip06.dtsi b/arch/arm64/boot/dts/hisilicon/hip06.dtsi index 50ceaa959bdc..a2fba458e047 100644 --- a/arch/arm64/boot/dts/hisilicon/hip06.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hip06.dtsi @@ -242,7 +242,7 @@ <0x0 0xfe020000 0 0x10000>; /* GICV */ interrupts = ; - its_dsa: interrupt-controller@c6000000 { + its_dsa: msi-controller@c6000000 { compatible = "arm,gic-v3-its"; msi-controller; #msi-cells = <1>; diff --git a/arch/arm64/boot/dts/hisilicon/hip07.dtsi b/arch/arm64/boot/dts/hisilicon/hip07.dtsi index 4773a533fce5..892691bb2adb 100644 --- a/arch/arm64/boot/dts/hisilicon/hip07.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hip07.dtsi @@ -924,56 +924,56 @@ <0x0 0xfe020000 0x0 0x10000>; /* GICV */ interrupts = ; - p0_its_peri_a: interrupt-controller@4c000000 { + p0_its_peri_a: msi-controller@4c000000 { compatible = "arm,gic-v3-its"; msi-controller; #msi-cells = <1>; reg = <0x0 0x4c000000 0x0 0x40000>; }; - p0_its_peri_b: interrupt-controller@6c000000 { + p0_its_peri_b: msi-controller@6c000000 { compatible = "arm,gic-v3-its"; msi-controller; #msi-cells = <1>; reg = <0x0 0x6c000000 0x0 0x40000>; }; - p0_its_dsa_a: interrupt-controller@c6000000 { + p0_its_dsa_a: msi-controller@c6000000 { compatible = "arm,gic-v3-its"; msi-controller; #msi-cells = <1>; reg = <0x0 0xc6000000 0x0 0x40000>; }; - p0_its_dsa_b: interrupt-controller@8,c6000000 { + p0_its_dsa_b: msi-controller@8c6000000 { compatible = "arm,gic-v3-its"; msi-controller; #msi-cells = <1>; reg = <0x8 0xc6000000 0x0 0x40000>; }; - p1_its_peri_a: interrupt-controller@400,4c000000 { + p1_its_peri_a: msi-controller@4004c000000 { compatible = "arm,gic-v3-its"; msi-controller; #msi-cells = <1>; reg = <0x400 0x4c000000 0x0 0x40000>; }; - p1_its_peri_b: interrupt-controller@400,6c000000 { + p1_its_peri_b: msi-controller@4006c000000 { compatible = "arm,gic-v3-its"; msi-controller; #msi-cells = <1>; reg = <0x400 0x6c000000 0x0 0x40000>; }; - p1_its_dsa_a: interrupt-controller@400,c6000000 { + p1_its_dsa_a: msi-controller@400c6000000 { compatible = "arm,gic-v3-its"; msi-controller; #msi-cells = <1>; reg = <0x400 0xc6000000 0x0 0x40000>; }; - p1_its_dsa_b: interrupt-controller@408,c6000000 { + p1_its_dsa_b: msi-controller@408c6000000 { compatible = "arm,gic-v3-its"; msi-controller; #msi-cells = <1>; From 24402ce1e26e303ce2049e783a4fc3f6e122e169 Mon Sep 17 00:00:00 2001 From: Zhen Lei Date: Mon, 12 Oct 2020 21:17:30 +0800 Subject: [PATCH 441/799] arm64: dts: hisilicon: separate each group of data in the property "reg" Do not write the "reg" of multiple groups of data into a uint32 array, use <> to separate them. Otherwise, the errors similar to the following will be reported by reg.yaml. soc: dsa@c7000000:reg:0: [0, 3305111552, 0, 8978432, 0, 3338665984, 0, \ 6291456] is too long Signed-off-by: Zhen Lei Signed-off-by: Wei Xu --- arch/arm64/boot/dts/hisilicon/hip06.dtsi | 4 +- arch/arm64/boot/dts/hisilicon/hip07.dtsi | 148 +++++++++++------------ 2 files changed, 76 insertions(+), 76 deletions(-) diff --git a/arch/arm64/boot/dts/hisilicon/hip06.dtsi b/arch/arm64/boot/dts/hisilicon/hip06.dtsi index a2fba458e047..941d527dcb86 100644 --- a/arch/arm64/boot/dts/hisilicon/hip06.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hip06.dtsi @@ -434,8 +434,8 @@ #size-cells = <0>; compatible = "hisilicon,hns-dsaf-v2"; mode = "6port-16rss"; - reg = <0x0 0xc5000000 0x0 0x890000 - 0x0 0xc7000000 0x0 0x600000>; + reg = <0x0 0xc5000000 0x0 0x890000>, + <0x0 0xc7000000 0x0 0x600000>; reg-names = "ppe-base", "dsaf-base"; interrupt-parent = <&mbigen_dsaf0>; subctrl-syscon = <&dsa_subctrl>; diff --git a/arch/arm64/boot/dts/hisilicon/hip07.dtsi b/arch/arm64/boot/dts/hisilicon/hip07.dtsi index 892691bb2adb..36a873d15089 100644 --- a/arch/arm64/boot/dts/hisilicon/hip07.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hip07.dtsi @@ -1321,8 +1321,8 @@ #size-cells = <0>; compatible = "hisilicon,hns-dsaf-v2"; mode = "6port-16rss"; - reg = <0x0 0xc5000000 0x0 0x890000 - 0x0 0xc7000000 0x0 0x600000>; + reg = <0x0 0xc5000000 0x0 0x890000>, + <0x0 0xc7000000 0x0 0x600000>; reg-names = "ppe-base", "dsaf-base"; interrupt-parent = <&mbigen_dsaf0>; subctrl-syscon = <&dsa_subctrl>; @@ -1720,24 +1720,24 @@ }; p0_sec_a: crypto@d2000000 { compatible = "hisilicon,hip07-sec"; - reg = <0x0 0xd0000000 0x0 0x10000 - 0x0 0xd2000000 0x0 0x10000 - 0x0 0xd2010000 0x0 0x10000 - 0x0 0xd2020000 0x0 0x10000 - 0x0 0xd2030000 0x0 0x10000 - 0x0 0xd2040000 0x0 0x10000 - 0x0 0xd2050000 0x0 0x10000 - 0x0 0xd2060000 0x0 0x10000 - 0x0 0xd2070000 0x0 0x10000 - 0x0 0xd2080000 0x0 0x10000 - 0x0 0xd2090000 0x0 0x10000 - 0x0 0xd20a0000 0x0 0x10000 - 0x0 0xd20b0000 0x0 0x10000 - 0x0 0xd20c0000 0x0 0x10000 - 0x0 0xd20d0000 0x0 0x10000 - 0x0 0xd20e0000 0x0 0x10000 - 0x0 0xd20f0000 0x0 0x10000 - 0x0 0xd2100000 0x0 0x10000>; + reg = <0x0 0xd0000000 0x0 0x10000>, + <0x0 0xd2000000 0x0 0x10000>, + <0x0 0xd2010000 0x0 0x10000>, + <0x0 0xd2020000 0x0 0x10000>, + <0x0 0xd2030000 0x0 0x10000>, + <0x0 0xd2040000 0x0 0x10000>, + <0x0 0xd2050000 0x0 0x10000>, + <0x0 0xd2060000 0x0 0x10000>, + <0x0 0xd2070000 0x0 0x10000>, + <0x0 0xd2080000 0x0 0x10000>, + <0x0 0xd2090000 0x0 0x10000>, + <0x0 0xd20a0000 0x0 0x10000>, + <0x0 0xd20b0000 0x0 0x10000>, + <0x0 0xd20c0000 0x0 0x10000>, + <0x0 0xd20d0000 0x0 0x10000>, + <0x0 0xd20e0000 0x0 0x10000>, + <0x0 0xd20f0000 0x0 0x10000>, + <0x0 0xd2100000 0x0 0x10000>; interrupt-parent = <&p0_mbigen_sec_a>; iommus = <&p0_smmu_alg_a 0x600>; dma-coherent; @@ -1761,24 +1761,24 @@ }; p0_sec_b: crypto@8,d2000000 { compatible = "hisilicon,hip07-sec"; - reg = <0x8 0xd0000000 0x0 0x10000 - 0x8 0xd2000000 0x0 0x10000 - 0x8 0xd2010000 0x0 0x10000 - 0x8 0xd2020000 0x0 0x10000 - 0x8 0xd2030000 0x0 0x10000 - 0x8 0xd2040000 0x0 0x10000 - 0x8 0xd2050000 0x0 0x10000 - 0x8 0xd2060000 0x0 0x10000 - 0x8 0xd2070000 0x0 0x10000 - 0x8 0xd2080000 0x0 0x10000 - 0x8 0xd2090000 0x0 0x10000 - 0x8 0xd20a0000 0x0 0x10000 - 0x8 0xd20b0000 0x0 0x10000 - 0x8 0xd20c0000 0x0 0x10000 - 0x8 0xd20d0000 0x0 0x10000 - 0x8 0xd20e0000 0x0 0x10000 - 0x8 0xd20f0000 0x0 0x10000 - 0x8 0xd2100000 0x0 0x10000>; + reg = <0x8 0xd0000000 0x0 0x10000>, + <0x8 0xd2000000 0x0 0x10000>, + <0x8 0xd2010000 0x0 0x10000>, + <0x8 0xd2020000 0x0 0x10000>, + <0x8 0xd2030000 0x0 0x10000>, + <0x8 0xd2040000 0x0 0x10000>, + <0x8 0xd2050000 0x0 0x10000>, + <0x8 0xd2060000 0x0 0x10000>, + <0x8 0xd2070000 0x0 0x10000>, + <0x8 0xd2080000 0x0 0x10000>, + <0x8 0xd2090000 0x0 0x10000>, + <0x8 0xd20a0000 0x0 0x10000>, + <0x8 0xd20b0000 0x0 0x10000>, + <0x8 0xd20c0000 0x0 0x10000>, + <0x8 0xd20d0000 0x0 0x10000>, + <0x8 0xd20e0000 0x0 0x10000>, + <0x8 0xd20f0000 0x0 0x10000>, + <0x8 0xd2100000 0x0 0x10000>; interrupt-parent = <&p0_mbigen_sec_b>; iommus = <&p0_smmu_alg_b 0x600>; dma-coherent; @@ -1802,24 +1802,24 @@ }; p1_sec_a: crypto@400,d2000000 { compatible = "hisilicon,hip07-sec"; - reg = <0x400 0xd0000000 0x0 0x10000 - 0x400 0xd2000000 0x0 0x10000 - 0x400 0xd2010000 0x0 0x10000 - 0x400 0xd2020000 0x0 0x10000 - 0x400 0xd2030000 0x0 0x10000 - 0x400 0xd2040000 0x0 0x10000 - 0x400 0xd2050000 0x0 0x10000 - 0x400 0xd2060000 0x0 0x10000 - 0x400 0xd2070000 0x0 0x10000 - 0x400 0xd2080000 0x0 0x10000 - 0x400 0xd2090000 0x0 0x10000 - 0x400 0xd20a0000 0x0 0x10000 - 0x400 0xd20b0000 0x0 0x10000 - 0x400 0xd20c0000 0x0 0x10000 - 0x400 0xd20d0000 0x0 0x10000 - 0x400 0xd20e0000 0x0 0x10000 - 0x400 0xd20f0000 0x0 0x10000 - 0x400 0xd2100000 0x0 0x10000>; + reg = <0x400 0xd0000000 0x0 0x10000>, + <0x400 0xd2000000 0x0 0x10000>, + <0x400 0xd2010000 0x0 0x10000>, + <0x400 0xd2020000 0x0 0x10000>, + <0x400 0xd2030000 0x0 0x10000>, + <0x400 0xd2040000 0x0 0x10000>, + <0x400 0xd2050000 0x0 0x10000>, + <0x400 0xd2060000 0x0 0x10000>, + <0x400 0xd2070000 0x0 0x10000>, + <0x400 0xd2080000 0x0 0x10000>, + <0x400 0xd2090000 0x0 0x10000>, + <0x400 0xd20a0000 0x0 0x10000>, + <0x400 0xd20b0000 0x0 0x10000>, + <0x400 0xd20c0000 0x0 0x10000>, + <0x400 0xd20d0000 0x0 0x10000>, + <0x400 0xd20e0000 0x0 0x10000>, + <0x400 0xd20f0000 0x0 0x10000>, + <0x400 0xd2100000 0x0 0x10000>; interrupt-parent = <&p1_mbigen_sec_a>; iommus = <&p1_smmu_alg_a 0x600>; dma-coherent; @@ -1843,24 +1843,24 @@ }; p1_sec_b: crypto@408,d2000000 { compatible = "hisilicon,hip07-sec"; - reg = <0x408 0xd0000000 0x0 0x10000 - 0x408 0xd2000000 0x0 0x10000 - 0x408 0xd2010000 0x0 0x10000 - 0x408 0xd2020000 0x0 0x10000 - 0x408 0xd2030000 0x0 0x10000 - 0x408 0xd2040000 0x0 0x10000 - 0x408 0xd2050000 0x0 0x10000 - 0x408 0xd2060000 0x0 0x10000 - 0x408 0xd2070000 0x0 0x10000 - 0x408 0xd2080000 0x0 0x10000 - 0x408 0xd2090000 0x0 0x10000 - 0x408 0xd20a0000 0x0 0x10000 - 0x408 0xd20b0000 0x0 0x10000 - 0x408 0xd20c0000 0x0 0x10000 - 0x408 0xd20d0000 0x0 0x10000 - 0x408 0xd20e0000 0x0 0x10000 - 0x408 0xd20f0000 0x0 0x10000 - 0x408 0xd2100000 0x0 0x10000>; + reg = <0x408 0xd0000000 0x0 0x10000>, + <0x408 0xd2000000 0x0 0x10000>, + <0x408 0xd2010000 0x0 0x10000>, + <0x408 0xd2020000 0x0 0x10000>, + <0x408 0xd2030000 0x0 0x10000>, + <0x408 0xd2040000 0x0 0x10000>, + <0x408 0xd2050000 0x0 0x10000>, + <0x408 0xd2060000 0x0 0x10000>, + <0x408 0xd2070000 0x0 0x10000>, + <0x408 0xd2080000 0x0 0x10000>, + <0x408 0xd2090000 0x0 0x10000>, + <0x408 0xd20a0000 0x0 0x10000>, + <0x408 0xd20b0000 0x0 0x10000>, + <0x408 0xd20c0000 0x0 0x10000>, + <0x408 0xd20d0000 0x0 0x10000>, + <0x408 0xd20e0000 0x0 0x10000>, + <0x408 0xd20f0000 0x0 0x10000>, + <0x408 0xd2100000 0x0 0x10000>; interrupt-parent = <&p1_mbigen_sec_b>; iommus = <&p1_smmu_alg_b 0x600>; dma-coherent; From 8c563f55ee1d0241b834dd4b43be11cf7a47732b Mon Sep 17 00:00:00 2001 From: Zhen Lei Date: Mon, 12 Oct 2020 21:17:31 +0800 Subject: [PATCH 442/799] arm64: dts: hisilicon: write the values of property-units into a uint32 array Use <> to separate the values of property-units will be treated as multiple arrays. The errors similar to the following will be reported by property-units.yaml. ufs@ff3c0000: freq-table-hz: [[0, 0], [0, 0]] is too long Signed-off-by: Zhen Lei Signed-off-by: Wei Xu --- arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 3 ++- arch/arm64/boot/dts/hisilicon/hi3670.dtsi | 3 ++- arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi | 9 ++++----- 3 files changed, 8 insertions(+), 7 deletions(-) diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi index 994140fbc916..3f6b1715835a 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi @@ -1045,7 +1045,8 @@ clocks = <&crg_ctrl HI3660_CLK_GATE_UFSIO_REF>, <&crg_ctrl HI3660_CLK_GATE_UFSPHY_CFG>; clock-names = "ref_clk", "phy_clk"; - freq-table-hz = <0 0>, <0 0>; + freq-table-hz = <0 0 + 0 0>; /* offset: 0x84; bit: 12 */ resets = <&crg_rst 0x84 12>; reset-names = "rst"; diff --git a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi index 2dcffa3ed218..668977d1acba 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi @@ -667,7 +667,8 @@ clocks = <&crg_ctrl HI3670_CLK_GATE_UFSIO_REF>, <&crg_ctrl HI3670_CLK_GATE_UFS_SUBSYS>; clock-names = "ref_clk", "phy_clk"; - freq-table-hz = <0 0>, <0 0>; + freq-table-hz = <0 0 + 0 0>; /* offset: 0x84; bit: 12 */ resets = <&crg_rst 0x84 12>; reset-names = "rst"; diff --git a/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi b/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi index 12bc1d3ed424..993998ac27c5 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi @@ -91,11 +91,10 @@ gmacphyrst: reset-controller { compatible = "ti,syscon-reset"; #reset-cells = <1>; - ti,reset-bits = - <0xcc 12 0xcc 12 0 0 (ASSERT_CLEAR | - DEASSERT_SET|STATUS_NONE)>, - <0xcc 13 0xcc 13 0 0 (ASSERT_CLEAR | - DEASSERT_SET|STATUS_NONE)>; + ti,reset-bits = < + 0xcc 12 0xcc 12 0 0 (ASSERT_CLEAR | DEASSERT_SET | STATUS_NONE) + 0xcc 13 0xcc 13 0 0 (ASSERT_CLEAR | DEASSERT_SET | STATUS_NONE) + >; }; }; From 60780744d959b70fee31c053dbe7ae4a0387a8b2 Mon Sep 17 00:00:00 2001 From: Zhen Lei Date: Mon, 12 Oct 2020 21:17:32 +0800 Subject: [PATCH 443/799] arm64: dts: hisilicon: remove unused property pinctrl-names uart1 and uart5 are not used as pinctrl, so the property "pinctrl-names" can be deleted. In fact, the property "pinctrl-names" depends on the property "pinctrl-0". So the errors similar to the following will be reported by pinctrl-consumer.yaml. serial@fdf00000: 'pinctrl-0' is a dependency of 'pinctrl-names' Signed-off-by: Zhen Lei Signed-off-by: Wei Xu --- arch/arm64/boot/dts/hisilicon/hi3670.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi index 668977d1acba..85b0dfb35d6d 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi @@ -213,7 +213,6 @@ clocks = <&crg_ctrl HI3670_CLK_GATE_UART1>, <&crg_ctrl HI3670_PCLK>; clock-names = "uartclk", "apb_pclk"; - pinctrl-names = "default"; status = "disabled"; }; @@ -260,7 +259,6 @@ clocks = <&crg_ctrl HI3670_CLK_GATE_UART5>, <&crg_ctrl HI3670_PCLK>; clock-names = "uartclk", "apb_pclk"; - pinctrl-names = "default"; status = "disabled"; }; From ee6ff04f7fe93e46b54d0b2782c7642bb1573f77 Mon Sep 17 00:00:00 2001 From: Zhen Lei Date: Mon, 12 Oct 2020 21:17:33 +0800 Subject: [PATCH 444/799] arm64: dts: hisilicon: place clock-names "biu" before "ciu" Look at the clock-names schema defined in synopsys-dw-mshc.yaml: clock-names: items: - const: biu - const: ciu The "biu" needs to be placed before the "ciu". Signed-off-by: Zhen Lei Signed-off-by: Wei Xu --- arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi b/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi index 993998ac27c5..e24969d53c8f 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi @@ -304,7 +304,7 @@ interrupts = ; clocks = <&crg HISTB_SDIO0_CIU_CLK>, <&crg HISTB_SDIO0_BIU_CLK>; - clock-names = "ciu", "biu"; + clock-names = "biu", "ciu"; resets = <&crg 0x9c 4>; reset-names = "reset"; status = "disabled"; From d7d45d5d116739eea6174798a0147b8e51a2e719 Mon Sep 17 00:00:00 2001 From: Zhen Lei Date: Mon, 12 Oct 2020 21:17:34 +0800 Subject: [PATCH 445/799] arm64: dts: hisilicon: normalize the node name of the SMMU devices Change the node name of the SMMU devices to match "^iommu@[0-9a-f]*". Otherwise, the errors similar to the following will be reported by arm,smmu-v3.yaml. smmu_pcie: $nodename:0: 'smmu_pcie' does not match '^iommu@[0-9a-f]*' Signed-off-by: Zhen Lei Signed-off-by: Wei Xu --- arch/arm64/boot/dts/hisilicon/hip06.dtsi | 2 +- arch/arm64/boot/dts/hisilicon/hip07.dtsi | 10 +++++----- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/hisilicon/hip06.dtsi b/arch/arm64/boot/dts/hisilicon/hip06.dtsi index 941d527dcb86..2f1930d4457f 100644 --- a/arch/arm64/boot/dts/hisilicon/hip06.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hip06.dtsi @@ -330,7 +330,7 @@ * when iommu-map entry is used along with the PCIe node. * Refer:https://www.spinics.net/lists/arm-kernel/msg602812.html */ - smmu0: smmu_pcie { + smmu0: iommu@a0040000 { compatible = "arm,smmu-v3"; reg = <0x0 0xa0040000 0x0 0x20000>; #iommu-cells = <1>; diff --git a/arch/arm64/boot/dts/hisilicon/hip07.dtsi b/arch/arm64/boot/dts/hisilicon/hip07.dtsi index 36a873d15089..ba90b2585355 100644 --- a/arch/arm64/boot/dts/hisilicon/hip07.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hip07.dtsi @@ -1161,7 +1161,7 @@ * when iommu-map entry is used along with the PCIe node. * Refer:https://www.spinics.net/lists/arm-kernel/msg602812.html */ - smmu0: smmu_pcie { + smmu0: iommu@a0040000 { compatible = "arm,smmu-v3"; reg = <0x0 0xa0040000 0x0 0x20000>; #iommu-cells = <1>; @@ -1170,7 +1170,7 @@ hisilicon,broken-prefetch-cmd; status = "disabled"; }; - p0_smmu_alg_a: smmu_alg@d0040000 { + p0_smmu_alg_a: iommu@d0040000 { compatible = "arm,smmu-v3"; reg = <0x0 0xd0040000 0x0 0x20000>; interrupt-parent = <&p0_mbigen_smmu_alg_a>; @@ -1183,7 +1183,7 @@ hisilicon,broken-prefetch-cmd; /* smmu-cb-memtype = <0x0 0x1>;*/ }; - p0_smmu_alg_b: smmu_alg@8,d0040000 { + p0_smmu_alg_b: iommu@8d0040000 { compatible = "arm,smmu-v3"; reg = <0x8 0xd0040000 0x0 0x20000>; interrupt-parent = <&p0_mbigen_smmu_alg_b>; @@ -1196,7 +1196,7 @@ hisilicon,broken-prefetch-cmd; /* smmu-cb-memtype = <0x0 0x1>;*/ }; - p1_smmu_alg_a: smmu_alg@400,d0040000 { + p1_smmu_alg_a: iommu@400d0040000 { compatible = "arm,smmu-v3"; reg = <0x400 0xd0040000 0x0 0x20000>; interrupt-parent = <&p1_mbigen_smmu_alg_a>; @@ -1209,7 +1209,7 @@ hisilicon,broken-prefetch-cmd; /* smmu-cb-memtype = <0x0 0x1>;*/ }; - p1_smmu_alg_b: smmu_alg@408,d0040000 { + p1_smmu_alg_b: iommu@408d0040000 { compatible = "arm,smmu-v3"; reg = <0x408 0xd0040000 0x0 0x20000>; interrupt-parent = <&p1_mbigen_smmu_alg_b>; From 4d2b9b98e3265a464445f9bbaa6d24213845a594 Mon Sep 17 00:00:00 2001 From: Zhen Lei Date: Mon, 12 Oct 2020 21:17:35 +0800 Subject: [PATCH 446/799] arm64: dts: hisilicon: normalize the node name of the usb devices Change the node name of the usb devices to match "^usb(@.*)?". These errors are detected by generic-ehci.yaml and generic-ohci.yaml. Signed-off-by: Zhen Lei Signed-off-by: Wei Xu --- arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi | 4 ++-- arch/arm64/boot/dts/hisilicon/hip06.dtsi | 4 ++-- arch/arm64/boot/dts/hisilicon/hip07.dtsi | 4 ++-- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi b/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi index e24969d53c8f..11a72891e2a3 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi @@ -584,7 +584,7 @@ status = "disabled"; }; - ohci: ohci@9880000 { + ohci: usb@9880000 { compatible = "generic-ohci"; reg = <0x9880000 0x10000>; interrupts = ; @@ -599,7 +599,7 @@ status = "disabled"; }; - ehci: ehci@9890000 { + ehci: usb@9890000 { compatible = "generic-ehci"; reg = <0x9890000 0x10000>; interrupts = ; diff --git a/arch/arm64/boot/dts/hisilicon/hip06.dtsi b/arch/arm64/boot/dts/hisilicon/hip06.dtsi index 2f1930d4457f..2d401d74a01f 100644 --- a/arch/arm64/boot/dts/hisilicon/hip06.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hip06.dtsi @@ -373,7 +373,7 @@ #clock-cells = <0>; }; - usb_ohci: ohci@a7030000 { + usb_ohci: usb@a7030000 { compatible = "generic-ohci"; reg = <0x0 0xa7030000 0x0 0x10000>; interrupt-parent = <&mbigen_usb>; @@ -382,7 +382,7 @@ status = "disabled"; }; - usb_ehci: ehci@a7020000 { + usb_ehci: usb@a7020000 { compatible = "generic-ehci"; reg = <0x0 0xa7020000 0x0 0x10000>; interrupt-parent = <&mbigen_usb>; diff --git a/arch/arm64/boot/dts/hisilicon/hip07.dtsi b/arch/arm64/boot/dts/hisilicon/hip07.dtsi index ba90b2585355..7832d9cdec21 100644 --- a/arch/arm64/boot/dts/hisilicon/hip07.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hip07.dtsi @@ -1253,7 +1253,7 @@ status = "disabled"; }; - usb_ohci: ohci@a7030000 { + usb_ohci: usb@a7030000 { compatible = "generic-ohci"; reg = <0x0 0xa7030000 0x0 0x10000>; interrupt-parent = <&mbigen_usb>; @@ -1262,7 +1262,7 @@ status = "disabled"; }; - usb_ehci: ehci@a7020000 { + usb_ehci: usb@a7020000 { compatible = "generic-ehci"; reg = <0x0 0xa7020000 0x0 0x10000>; interrupt-parent = <&mbigen_usb>; From bf69b8622b940feaf61a266e304e90722875b588 Mon Sep 17 00:00:00 2001 From: Zhen Lei Date: Mon, 12 Oct 2020 21:17:36 +0800 Subject: [PATCH 447/799] arm64: dts: hisilicon: normalize the node name of the UART devices Change the node name of the UART devices to match "^serial(@[0-9a-f,]+)*$". Signed-off-by: Zhen Lei Signed-off-by: Wei Xu --- arch/arm64/boot/dts/hisilicon/hip05.dtsi | 4 ++-- arch/arm64/boot/dts/hisilicon/hip06.dtsi | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/hisilicon/hip05.dtsi b/arch/arm64/boot/dts/hisilicon/hip05.dtsi index f7e3a7af4634..26caf09e9511 100644 --- a/arch/arm64/boot/dts/hisilicon/hip05.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hip05.dtsi @@ -296,7 +296,7 @@ clock-frequency = <200000000>; }; - uart0: uart@80300000 { + uart0: serial@80300000 { compatible = "snps,dw-apb-uart"; reg = <0x0 0x80300000 0x0 0x10000>; interrupts = ; @@ -307,7 +307,7 @@ status = "disabled"; }; - uart1: uart@80310000 { + uart1: serial@80310000 { compatible = "snps,dw-apb-uart"; reg = <0x0 0x80310000 0x0 0x10000>; interrupts = ; diff --git a/arch/arm64/boot/dts/hisilicon/hip06.dtsi b/arch/arm64/boot/dts/hisilicon/hip06.dtsi index 2d401d74a01f..7980709e21ff 100644 --- a/arch/arm64/boot/dts/hisilicon/hip06.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hip06.dtsi @@ -359,7 +359,7 @@ status = "disabled"; }; - uart0: lpc-uart@2f8 { + uart0: serial@2f8 { compatible = "ns16550a"; clock-frequency = <1843200>; reg = <0x01 0x2f8 0x08>; From c85731abd6946234c9359212fff1d5f0b3013852 Mon Sep 17 00:00:00 2001 From: Zhen Lei Date: Mon, 12 Oct 2020 21:17:37 +0800 Subject: [PATCH 448/799] arm64: dts: hisilicon: list all clocks required by spi-pl022.yaml The arm,pl022 binding need to specify two clocks: "sspclk", "apb_pclk". But only "apb_pclk" is specified now. Because the driver preferentially matches the first clock. Otherwise, it matches the second clock instead of both clocks. So both of them use the same clock don't change the function. Signed-off-by: Zhen Lei Signed-off-by: Wei Xu --- arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 8 ++++---- arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi | 4 ++-- arch/arm64/boot/dts/hisilicon/hi6220.dtsi | 4 ++-- 3 files changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi index 3f6b1715835a..edb80abf45b3 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi @@ -971,8 +971,8 @@ #address-cells = <1>; #size-cells = <0>; interrupts = ; - clocks = <&crg_ctrl HI3660_CLK_GATE_SPI2>; - clock-names = "apb_pclk"; + clocks = <&crg_ctrl HI3660_CLK_GATE_SPI2>, <&crg_ctrl HI3660_CLK_GATE_SPI2>; + clock-names = "sspclk", "apb_pclk"; pinctrl-names = "default"; pinctrl-0 = <&spi2_pmx_func &spi2_cfg_func>; num-cs = <1>; @@ -986,8 +986,8 @@ #address-cells = <1>; #size-cells = <0>; interrupts = ; - clocks = <&crg_ctrl HI3660_CLK_GATE_SPI3>; - clock-names = "apb_pclk"; + clocks = <&crg_ctrl HI3660_CLK_GATE_SPI3>, <&crg_ctrl HI3660_CLK_GATE_SPI3>; + clock-names = "sspclk", "apb_pclk"; pinctrl-names = "default"; pinctrl-0 = <&spi3_pmx_func &spi3_cfg_func>; num-cs = <1>; diff --git a/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi b/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi index 11a72891e2a3..1c7dda972c92 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi @@ -291,8 +291,8 @@ interrupts = ; num-cs = <1>; cs-gpios = <&gpio7 1 0>; - clocks = <&crg HISTB_SPI0_CLK>; - clock-names = "apb_pclk"; + clocks = <&crg HISTB_SPI0_CLK>, <&crg HISTB_SPI0_CLK>; + clock-names = "sspclk", "apb_pclk"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; diff --git a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi index 014735a9bc73..c6580c9f068e 100644 --- a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi @@ -725,8 +725,8 @@ interrupts = <0 50 4>; bus-id = <0>; enable-dma = <0>; - clocks = <&sys_ctrl HI6220_SPI_CLK>; - clock-names = "apb_pclk"; + clocks = <&sys_ctrl HI6220_SPI_CLK>, <&sys_ctrl HI6220_SPI_CLK>; + clock-names = "sspclk", "apb_pclk"; pinctrl-names = "default"; pinctrl-0 = <&spi0_pmx_func &spi0_cfg_func>; num-cs = <1>; From 58dd4736b8c716984a15a996e432484921e1c1e9 Mon Sep 17 00:00:00 2001 From: Zhen Lei Date: Mon, 12 Oct 2020 21:17:38 +0800 Subject: [PATCH 449/799] arm64: dts: hisilicon: list all clocks required by pl011.yaml The arm,pl011 binding need to specify two clocks: "uartclk", "apb_pclk". But only "apb_pclk" is specified now. Because the driver preferentially matches the first clock. Otherwise, it matches the second clock instead of both clocks. So both of them use the same clock don't change the function. Signed-off-by: Zhen Lei Signed-off-by: Wei Xu --- arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi b/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi index 1c7dda972c92..81d09434c5c6 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi @@ -216,8 +216,8 @@ compatible = "arm,pl011", "arm,primecell"; reg = <0x8b00000 0x1000>; interrupts = ; - clocks = <&sysctrl HISTB_UART0_CLK>; - clock-names = "apb_pclk"; + clocks = <&sysctrl HISTB_UART0_CLK>, <&sysctrl HISTB_UART0_CLK>; + clock-names = "uartclk", "apb_pclk"; status = "disabled"; }; @@ -225,8 +225,8 @@ compatible = "arm,pl011", "arm,primecell"; reg = <0x8b02000 0x1000>; interrupts = ; - clocks = <&crg HISTB_UART2_CLK>; - clock-names = "apb_pclk"; + clocks = <&crg HISTB_UART2_CLK>, <&crg HISTB_UART2_CLK>; + clock-names = "uartclk", "apb_pclk"; status = "disabled"; }; From c4cbd0356c60c71dd717bd0c3825bb0646a6d347 Mon Sep 17 00:00:00 2001 From: Zhen Lei Date: Mon, 12 Oct 2020 21:17:39 +0800 Subject: [PATCH 450/799] arm64: dts: hisilicon: list all clocks required by snps-dw-apb-uart.yaml The snps,dw-apb-uart binding need to specify two clocks: "baudclk", "apb_pclk". But only "apb_pclk" is specified now. Because the driver preferentially matches the first clock. Otherwise, it matches the second clock instead of both clocks. So both of them use the same clock don't change the function. Signed-off-by: Zhen Lei Signed-off-by: Wei Xu --- arch/arm64/boot/dts/hisilicon/hip05.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/hisilicon/hip05.dtsi b/arch/arm64/boot/dts/hisilicon/hip05.dtsi index 26caf09e9511..c073d6d8b55c 100644 --- a/arch/arm64/boot/dts/hisilicon/hip05.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hip05.dtsi @@ -300,8 +300,8 @@ compatible = "snps,dw-apb-uart"; reg = <0x0 0x80300000 0x0 0x10000>; interrupts = ; - clocks = <&refclk200mhz>; - clock-names = "apb_pclk"; + clocks = <&refclk200mhz>, <&refclk200mhz>; + clock-names = "baudclk", "apb_pclk"; reg-shift = <2>; reg-io-width = <4>; status = "disabled"; @@ -311,8 +311,8 @@ compatible = "snps,dw-apb-uart"; reg = <0x0 0x80310000 0x0 0x10000>; interrupts = ; - clocks = <&refclk200mhz>; - clock-names = "apb_pclk"; + clocks = <&refclk200mhz>, <&refclk200mhz>; + clock-names = "baudclk", "apb_pclk"; reg-shift = <2>; reg-io-width = <4>; status = "disabled"; From 4dc5288f5a5a60daaf9fbc56bed9b127f6e7e60f Mon Sep 17 00:00:00 2001 From: Serge Semin Date: Wed, 11 Nov 2020 12:15:50 +0300 Subject: [PATCH 451/799] arm64: dts: hi3660: Harmonize DWC USB3 DT nodes name In accordance with the DWC USB3 bindings the corresponding node name is suppose to comply with the Generic USB HCD DT schema, which requires the USB nodes to have the name acceptable by the regexp: "^usb(@.*)?" . Make sure the "snps,dwc3"-compatible nodes are correctly named. Signed-off-by: Serge Semin Acked-by: Krzysztof Kozlowski Signed-off-by: Wei Xu --- arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi index edb80abf45b3..49c19c6879f9 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi @@ -1169,7 +1169,7 @@ }; }; - dwc3: dwc3@ff100000 { + dwc3: usb@ff100000 { compatible = "snps,dwc3"; reg = <0x0 0xff100000 0x0 0x100000>; From 25df3e1f64f54cfb4b23ff3ed1292c3eba94b22e Mon Sep 17 00:00:00 2001 From: Jisheng Zhang Date: Mon, 9 Nov 2020 17:05:29 +0800 Subject: [PATCH 452/799] arm64: dts: hisilicon: Use generic "ngpios" rather than "snps,nr-gpios" This is to remove similar errors as below: OF: /.../gpio-port@0: could not find phandle Commit 7569486d79ae ("gpio: dwapb: Add ngpios DT-property support") explained the reason of above errors well and added the generic "ngpios" property, let's use it. Signed-off-by: Jisheng Zhang Reviewed-by: Linus Walleij Signed-off-by: Wei Xu --- arch/arm64/boot/dts/hisilicon/hip05.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/hisilicon/hip05.dtsi b/arch/arm64/boot/dts/hisilicon/hip05.dtsi index c073d6d8b55c..405acaa3e9dd 100644 --- a/arch/arm64/boot/dts/hisilicon/hip05.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hip05.dtsi @@ -335,7 +335,7 @@ compatible = "snps,dw-apb-gpio-port"; gpio-controller; #gpio-cells = <2>; - snps,nr-gpios = <32>; + ngpios = <32>; reg = <0>; interrupt-controller; #interrupt-cells = <2>; @@ -354,7 +354,7 @@ compatible = "snps,dw-apb-gpio-port"; gpio-controller; #gpio-cells = <2>; - snps,nr-gpios = <32>; + ngpios = <32>; reg = <0>; interrupt-controller; #interrupt-cells = <2>; From 6acb71fd344adb08633b2b1d8261a876fbd2bb18 Mon Sep 17 00:00:00 2001 From: Jonathan Marek Date: Mon, 23 Nov 2020 23:10:03 -0500 Subject: [PATCH 453/799] arm64: dts: qcom: sort sm8150 usb_2 node Fix an error introduced resolving conflicts with camnoc_virt node. Fixes: 0c9dde0d2015 ("arm64: dts: qcom: sm8150: Add secondary USB and PHY nodes") Signed-off-by: Jonathan Marek Link: https://lore.kernel.org/r/20201124041003.3600-1-jonathan@marek.ca Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8150.dtsi | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi index e40bec6f3623..c06e0adefcf3 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -983,13 +983,6 @@ }; }; - camnoc_virt: interconnect@ac00000 { - compatible = "qcom,sm8150-camnoc-virt"; - reg = <0 0x0ac00000 0 0x1000>; - #interconnect-cells = <1>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - usb_2: usb@a8f8800 { compatible = "qcom,sm8150-dwc3", "qcom,dwc3"; reg = <0 0x0a8f8800 0 0x400>; @@ -1035,6 +1028,13 @@ }; }; + camnoc_virt: interconnect@ac00000 { + compatible = "qcom,sm8150-camnoc-virt"; + reg = <0 0x0ac00000 0 0x1000>; + #interconnect-cells = <1>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + aoss_qmp: power-controller@c300000 { compatible = "qcom,sm8150-aoss-qmp"; reg = <0x0 0x0c300000 0x0 0x100000>; From 4785cff7cb9c8bcbff3891013d2f8eb973d676f3 Mon Sep 17 00:00:00 2001 From: Stephen Boyd Date: Sat, 21 Nov 2020 19:41:49 -0800 Subject: [PATCH 454/799] arm64: dts: sdm845: Add iommus property to qup The SMMU that sits in front of the QUP needs to be programmed properly so that the i2c geni driver can allocate DMA descriptors. Failure to do this leads to faults when using devices such as an i2c touchscreen where the transaction is larger than 32 bytes and we use a DMA buffer. arm-smmu 15000000.iommu: Unexpected global fault, this could be serious arm-smmu 15000000.iommu: GFSR 0x00000002, GFSYNR0 0x00000002, GFSYNR1 0x000006c0, GFSYNR2 0x00000000 Add the right SID and mask so this works. Reviewed-by: Vinod Koul Tested-by: Caleb Connolly Tested-by: Vinod Koul Signed-off-by: Stephen Boyd [bjorn: Define for second QUP as well, be more specific in sdm845.dtsi] Link: https://lore.kernel.org/r/20201122034149.626045-1-bjorn.andersson@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi | 2 ++ arch/arm64/boot/dts/qcom/sdm845.dtsi | 2 ++ 2 files changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi b/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi index 39f23cdcbd02..216a74f0057c 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi @@ -653,10 +653,12 @@ ap_ts_i2c: &i2c14 { &qupv3_id_0 { status = "okay"; + iommus = <&apps_smmu 0x0 0x3>; }; &qupv3_id_1 { status = "okay"; + iommus = <&apps_smmu 0x6c0 0x3>; }; &sdhc_2 { diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 6465a6653ad9..d6b7b1bfa202 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -1120,6 +1120,7 @@ clock-names = "m-ahb", "s-ahb"; clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + iommus = <&apps_smmu 0x3 0x0>; #address-cells = <2>; #size-cells = <2>; ranges; @@ -1460,6 +1461,7 @@ clock-names = "m-ahb", "s-ahb"; clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + iommus = <&apps_smmu 0x6c3 0x0>; #address-cells = <2>; #size-cells = <2>; ranges; From 036b7334ee6dc10115fbaebd8b04c9e4a17eccb2 Mon Sep 17 00:00:00 2001 From: Michael Klein Date: Mon, 23 Nov 2020 12:45:35 +0100 Subject: [PATCH 455/799] ARM: dts: sun8i-h2-plus-bananapi-m2-zero: add gpio-line-names Add gpio-line-names as documented in the Banana Pi wiki [1] and in the schematics [2]. [1]: http://wiki.banana-pi.org/Banana_Pi_BPI-M2_ZERO#GPIO_PIN_define [2]: https://drive.google.com/file/d/0B4PAo2nW2KfnMW5sVkxWSW9qa28/view Signed-off-by: Michael Klein Signed-off-by: Maxime Ripard Link: https://lore.kernel.org/r/20201123114535.1605939-1-michael@fossekall.de --- .../dts/sun8i-h2-plus-bananapi-m2-zero.dts | 64 +++++++++++++++++++ 1 file changed, 64 insertions(+) diff --git a/arch/arm/boot/dts/sun8i-h2-plus-bananapi-m2-zero.dts b/arch/arm/boot/dts/sun8i-h2-plus-bananapi-m2-zero.dts index 4c6704e4c57e..e76d56a3df9c 100644 --- a/arch/arm/boot/dts/sun8i-h2-plus-bananapi-m2-zero.dts +++ b/arch/arm/boot/dts/sun8i-h2-plus-bananapi-m2-zero.dts @@ -136,6 +136,70 @@ }; +&pio { + gpio-line-names = + /* PA */ + "CON2-P13", "CON2-P11", "CON2-P22", "CON2-P15", + "CON3-P03", "CON3-P02", "CON2-P07", "CON2-P29", + "CON2-P31", "CON2-P33", "CON2-P35", "CON2-P05", + "CON2-P03", "CON2-P08", "CON2-P10", "CON2-P16", + "CON2-P12", "CON2-P37", "CON2-P28", "CON2-P27", + "CON2-P40", "CON2-P38", "", "", + "", "", "", "", "", "", "", "", + + /* PB */ + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + + /* PC */ + "CON2-P19", "CON2-P21", "CON2-P23", "CON2-P24", + "CON2-P18", "", "", "CON2-P26", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + + /* PD */ + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "CSI-PWR-EN", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + + /* PE */ + "CN3-P17", "CN3-P13", "CN3-P09", "CN3-P07", + "CN3-P19", "CN3-P21", "CN3-P22", "CN3-P20", + "CN3-P18", "CN3-P16", "CN3-P14", "CN3-P12", + "CN3-P05", "CN3-P03", "CN3-P06", "CN3-P08", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + + /* PF */ + "SDC0-D1", "SDC0-D0", "SDC0-CLK", "SDC0-CMD", "SDC0-D3", + "SDC0-D2", "SDC0-DET", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + + /* PG */ + "WL-SDIO-CLK", "WL-SDIO-CMD", "WL-SDIO-D0", "WL-SDIO-D1", + "WL-SDIO-D2", "WL-SDIO-D3", "BT-UART-TX", "BT-UART-RX", + "BT-UART-RTS", "BT-UART-CTS", "WL-WAKE-AP", "BT-WAKE-AP", + "BT-RST-N", "AP-WAKE-BT", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&r_pio { + gpio-line-names = + /* PL */ + "", "CPUX-SET", "CON2-P32", "POWER-KEY", "CON2-P36", + "VCC-IO-EN", "USB0-ID", "WL-PWR-EN", + "PWR-STB", "PWR-DRAM", "PWR-LED", "IR-RX", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + &usb_otg { dr_mode = "otg"; status = "okay"; From 036e11092599131a10e34150b5b855ea86ccc546 Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Fri, 20 Nov 2020 21:56:03 -0800 Subject: [PATCH 456/799] arm64: dts: qcom: sm8150-mtp: Specify remoteproc firmware Point the various remoteprocs of SM8150 MTP to a place with the platform specific firmware. Reviewed-by: Vinod Koul Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20201121055603.582281-1-bjorn.andersson@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8150-mtp.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8150-mtp.dts b/arch/arm64/boot/dts/qcom/sm8150-mtp.dts index 6c6325c3af59..3719af2207d9 100644 --- a/arch/arm64/boot/dts/qcom/sm8150-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8150-mtp.dts @@ -369,14 +369,22 @@ &remoteproc_adsp { status = "okay"; + firmware-name = "qcom/sm8150/adsp.mdt"; }; &remoteproc_cdsp { status = "okay"; + firmware-name = "qcom/sm8150/cdsp.mdt"; +}; + +&remoteproc_mpss { + status = "okay"; + firmware-name = "qcom/sm8150/modem.mdt"; }; &remoteproc_slpi { status = "okay"; + firmware-name = "qcom/sm8150/slpi.mdt"; }; &tlmm { From 05090bb9e53da0d4e913452c450cb5f55baad45a Mon Sep 17 00:00:00 2001 From: Jonathan Marek Date: Fri, 20 Nov 2020 21:58:07 -0800 Subject: [PATCH 457/799] arm64: dts: qcom: sm8150: Add wifi node Add a node for the WCN3990 WiFi module. Reviewed-by: Vinod Koul Signed-off-by: Jonathan Marek [bjorn: Extracted patch from larger "misc" patch, added qdss clock] Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20201121055808.582401-1-bjorn.andersson@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8150.dtsi | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi index c06e0adefcf3..8dac11c6012e 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -1393,6 +1393,29 @@ #freq-domain-cells = <1>; }; + + wifi: wifi@18800000 { + compatible = "qcom,wcn3990-wifi"; + reg = <0 0x18800000 0 0x800000>; + reg-names = "membase"; + memory-region = <&wlan_mem>; + clock-names = "cxo_ref_clk_pin", "qdss"; + clocks = <&rpmhcc RPMH_RF_CLK2>, <&aoss_qmp>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + ; + iommus = <&apps_smmu 0x0640 0x1>; + status = "disabled"; + }; }; timer { From c5a0609b064ceb5ffdec9c71825d4fc6a001c068 Mon Sep 17 00:00:00 2001 From: Jonathan Marek Date: Fri, 20 Nov 2020 21:58:08 -0800 Subject: [PATCH 458/799] arm64: dts: qcom: sm8150-mtp: Enable WiFi node Enable the WiFi node and specify its supply regulators. Reviewed-by: Vinod Koul Signed-off-by: Jonathan Marek [bjorn: Extracted patch from larger HDK patch] Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20201121055808.582401-2-bjorn.andersson@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8150-mtp.dts | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8150-mtp.dts b/arch/arm64/boot/dts/qcom/sm8150-mtp.dts index 3719af2207d9..3774f8e63416 100644 --- a/arch/arm64/boot/dts/qcom/sm8150-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8150-mtp.dts @@ -437,3 +437,12 @@ &usb_1_dwc3 { dr_mode = "peripheral"; }; + +&wifi { + status = "okay"; + + vdd-0.8-cx-mx-supply = <&vdda_wcss_pll>; + vdd-1.8-xo-supply = <&vreg_l7a_1p8>; + vdd-1.3-rfa-supply = <&vdda_wcss_adcdac_1>; + vdd-3.3-ch0-supply = <&vreg_l11c_3p3>; +}; From e9fd12df325e757b9ab52729260847776b9b2831 Mon Sep 17 00:00:00 2001 From: Jonathan Marek Date: Mon, 23 Nov 2020 09:40:16 -0500 Subject: [PATCH 459/799] arm64: dts: qcom: fix indentation error in sm8250 cpu nodes Use tabs instead of 6 spaces. Signed-off-by: Jonathan Marek Link: https://lore.kernel.org/r/20201123144016.19596-1-jonathan@marek.ca Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 34 ++++++++++++++-------------- 1 file changed, 17 insertions(+), 17 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index a679f6864065..65acd1f381eb 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -93,10 +93,10 @@ qcom,freq-domain = <&cpufreq_hw 0>; #cooling-cells = <2>; L2_0: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; + compatible = "cache"; + next-level-cache = <&L3_0>; L3_0: l3-cache { - compatible = "cache"; + compatible = "cache"; }; }; }; @@ -110,8 +110,8 @@ qcom,freq-domain = <&cpufreq_hw 0>; #cooling-cells = <2>; L2_100: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; + compatible = "cache"; + next-level-cache = <&L3_0>; }; }; @@ -124,8 +124,8 @@ qcom,freq-domain = <&cpufreq_hw 0>; #cooling-cells = <2>; L2_200: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; + compatible = "cache"; + next-level-cache = <&L3_0>; }; }; @@ -138,8 +138,8 @@ qcom,freq-domain = <&cpufreq_hw 0>; #cooling-cells = <2>; L2_300: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; + compatible = "cache"; + next-level-cache = <&L3_0>; }; }; @@ -152,8 +152,8 @@ qcom,freq-domain = <&cpufreq_hw 1>; #cooling-cells = <2>; L2_400: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; + compatible = "cache"; + next-level-cache = <&L3_0>; }; }; @@ -166,8 +166,8 @@ qcom,freq-domain = <&cpufreq_hw 1>; #cooling-cells = <2>; L2_500: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; + compatible = "cache"; + next-level-cache = <&L3_0>; }; }; @@ -181,8 +181,8 @@ qcom,freq-domain = <&cpufreq_hw 1>; #cooling-cells = <2>; L2_600: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; + compatible = "cache"; + next-level-cache = <&L3_0>; }; }; @@ -195,8 +195,8 @@ qcom,freq-domain = <&cpufreq_hw 2>; #cooling-cells = <2>; L2_700: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; + compatible = "cache"; + next-level-cache = <&L3_0>; }; }; }; From 95e6f8467c83c4074a6f6b47bad00653549ff90a Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Sun, 22 Nov 2020 23:23:05 -0600 Subject: [PATCH 460/799] arm64: dts: qcom: sdm845: Limit ipa iommu streams The Android and Windows firmware does not accept the use of 3 as a mask to cover the IPA streams. But with 0x721 being related to WiFi and 0x723 being unsed the mapping can be reduced to just cover 0x720 and 0x722, which is accepted. Acked-by: Alex Elder Tested-by: Alex Elder Fixes: e9e89c45bfeb ("arm64: dts: sdm845: add IPA iommus property") Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20201123052305.157686-1-bjorn.andersson@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index d6b7b1bfa202..957ee80704e7 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -2143,7 +2143,8 @@ ipa: ipa@1e40000 { compatible = "qcom,sdm845-ipa"; - iommus = <&apps_smmu 0x720 0x3>; + iommus = <&apps_smmu 0x720 0x0>, + <&apps_smmu 0x722 0x0>; reg = <0 0x1e40000 0 0x7000>, <0 0x1e47000 0 0x2000>, <0 0x1e04000 0 0x2c000>; From 7ee3eae868335626f83f551daee2fa98735acb74 Mon Sep 17 00:00:00 2001 From: Jishnu Prakash Date: Thu, 8 Oct 2020 18:10:25 +0530 Subject: [PATCH 461/799] arm64: dts: qcom: pm6150x: add ADC_TM definitions Add ADC_TM peripheral definitions for PM6150 and PM6150L. Add ADC peripheral definition for PM6150l, which is needed for ADC_TM. Signed-off-by: Jishnu Prakash Link: https://lore.kernel.org/r/1602160825-10414-2-git-send-email-jprakash@codeaurora.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/pm6150.dtsi | 10 ++++++++++ arch/arm64/boot/dts/qcom/pm6150l.dtsi | 24 ++++++++++++++++++++++++ 2 files changed, 34 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/pm6150.dtsi b/arch/arm64/boot/dts/qcom/pm6150.dtsi index 57af0b4a384d..8ab4f1f78bbf 100644 --- a/arch/arm64/boot/dts/qcom/pm6150.dtsi +++ b/arch/arm64/boot/dts/qcom/pm6150.dtsi @@ -52,6 +52,16 @@ }; }; + pm6150_adc_tm: adc-tm@3500 { + compatible = "qcom,spmi-adc-tm5"; + reg = <0x3500>; + interrupts = <0x0 0x35 0x0 IRQ_TYPE_EDGE_RISING>; + #thermal-sensor-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + pm6150_gpio: gpios@c000 { compatible = "qcom,pm6150-gpio", "qcom,spmi-gpio"; reg = <0xc000>; diff --git a/arch/arm64/boot/dts/qcom/pm6150l.dtsi b/arch/arm64/boot/dts/qcom/pm6150l.dtsi index f84027b505d1..b49860cd1387 100644 --- a/arch/arm64/boot/dts/qcom/pm6150l.dtsi +++ b/arch/arm64/boot/dts/qcom/pm6150l.dtsi @@ -11,6 +11,30 @@ #address-cells = <1>; #size-cells = <0>; + pm6150l_adc: adc@3100 { + compatible = "qcom,spmi-adc5"; + reg = <0x3100>; + interrupts = <0x4 0x31 0x0 IRQ_TYPE_EDGE_RISING>; + #address-cells = <1>; + #size-cells = <0>; + #io-channel-cells = <1>; + + adc-chan@6 { + reg = ; + label = "die_temp"; + }; + }; + + pm6150l_adc_tm: adc-tm@3500 { + compatible = "qcom,spmi-adc-tm5"; + reg = <0x3500>; + interrupts = <0x4 0x35 0x0 IRQ_TYPE_EDGE_RISING>; + #thermal-sensor-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + pm6150l_gpio: gpios@c000 { compatible = "qcom,pm6150l-gpio", "qcom,spmi-gpio"; reg = <0xc000>; From bb06eb3607e97842b3475446069e177ed0e6b26b Mon Sep 17 00:00:00 2001 From: Antony Wang Date: Fri, 30 Oct 2020 08:48:43 -0700 Subject: [PATCH 462/799] arm64: qcom: sc7180: trogdor: Add ADC nodes and thermal zone for charger thermistor Trogdor has a thermistor to monitor the temperature of the charger IC. Add the ADC (monitor) nodes and a thermal zone for this thermistor. Signed-off-by: Antony Wang [mka: tweaked commit message] Signed-off-by: Matthias Kaehlcke Link: https://lore.kernel.org/r/20201030084840.1.If389f211a8532b83095ff8c66ec181424440f8d6@changeid Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi | 36 ++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi index 3eb1ff2483be..e854a12f45f2 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi @@ -13,6 +13,23 @@ #include "pm6150.dtsi" #include "pm6150l.dtsi" +/ { + thermal-zones { + charger-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&pm6150_adc_tm 1>; + + trips { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; +}; + /* * Reserved memory changes * @@ -741,6 +758,25 @@ hp_i2c: &i2c9 { status = "okay"; }; +&pm6150_adc { + charger-thermistor@4f { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; +}; + +&pm6150_adc_tm { + status = "okay"; + + charger-thermistor@1 { + reg = <1>; + io-channels = <&pm6150_adc ADC5_AMUX_THM3_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time-us = <200>; + }; +}; + &pm6150_pwrkey { status = "disabled"; }; From d4b85bc550f49e46cf1d945a342d316c814e94c5 Mon Sep 17 00:00:00 2001 From: Terry Hsiao Date: Mon, 16 Nov 2020 16:30:14 +0800 Subject: [PATCH 463/799] arm64: dts: qcom: sc7180-trogdor: add "pen-insert" label for trogdor Add a label to the "pen-insert" node in sc7180-trogdor.dtsi Reviewed-by: Douglas Anderson Signed-off-by: Terry Hsiao Link: https://lore.kernel.org/r/20201116083014.547-1-terry_hsiao@compal.corp-partner.google.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi index e854a12f45f2..e9b1182b3715 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi @@ -218,7 +218,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pen_pdct_l>; - pen-insert { + pen_insert: pen-insert { label = "Pen Insert"; /* Insert = low, eject = high */ From 8fd01e01fd6f8ba67e4ed8c5be0ab76d06156287 Mon Sep 17 00:00:00 2001 From: Sibi Sankar Date: Tue, 24 Nov 2020 11:51:15 +0530 Subject: [PATCH 464/799] arm64: dts: qcom: sc7180-lite: Tweak DDR/L3 scaling on SC7180-lite Tweak the DDR/L3 bandwidth votes on the lite variant of the SC7180 SoC since the gold cores only support frequencies upto 2.1 GHz. Reviewed-by: Douglas Anderson Signed-off-by: Sibi Sankar Link: https://lore.kernel.org/r/1606198876-3515-1-git-send-email-sibis@codeaurora.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc7180-lite.dtsi | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sc7180-lite.dtsi diff --git a/arch/arm64/boot/dts/qcom/sc7180-lite.dtsi b/arch/arm64/boot/dts/qcom/sc7180-lite.dtsi new file mode 100644 index 000000000000..d8ed1d7b4ec7 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7180-lite.dtsi @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * SC7180 lite device tree source + * + * Copyright (c) 2020, The Linux Foundation. All rights reserved. + */ + +&cpu6_opp10 { + opp-peak-kBps = <7216000 22425600>; +}; + +&cpu6_opp11 { + opp-peak-kBps = <7216000 22425600>; +}; + +&cpu6_opp12 { + opp-peak-kBps = <8532000 23347200>; +}; From 3c9c31c2523ecd5b609a2eecb5ad524ef4fc931c Mon Sep 17 00:00:00 2001 From: Sibi Sankar Date: Tue, 24 Nov 2020 11:51:16 +0530 Subject: [PATCH 465/799] arm64: dts: qcom: sc7180: Add DDR/L3 votes for the pro variant Add DDR/L3 bandwidth votes for the pro variant of SC7180 SoC, as it support frequencies upto 2.5 GHz. Reviewed-by: Douglas Anderson Signed-off-by: Sibi Sankar Link: https://lore.kernel.org/r/1606198876-3515-2-git-send-email-sibis@codeaurora.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc7180.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index c0efb101b0d6..98210fdcbe25 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -527,6 +527,11 @@ opp-hz = /bits/ 64 <2400000000>; opp-peak-kBps = <8532000 23347200>; }; + + cpu6_opp16: opp-2553600000 { + opp-hz = /bits/ 64 <2553600000>; + opp-peak-kBps = <8532000 23347200>; + }; }; memory@80000000 { From cc563f8f769b9fe4bbe18dcd3cbb382a49cf3585 Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Tue, 24 Nov 2020 20:38:31 -0600 Subject: [PATCH 466/799] arm64: defconfig: Enable Qualcomm PON driver The PON block in the PMIC provides, among other things, support for "reboot reason", power key and reset "key" handling. Let's enable the driver for this block. Reviewed-by: Vinod Koul Link: https://lore.kernel.org/r/20201125023831.99774-1-bjorn.andersson@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index d88803191e7f..7c425d0e4960 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -517,6 +517,7 @@ CONFIG_POWER_AVS=y CONFIG_QCOM_CPR=y CONFIG_ROCKCHIP_IODOMAIN=y CONFIG_POWER_RESET_MSM=y +CONFIG_POWER_RESET_QCOM_PON=m CONFIG_POWER_RESET_XGENE=y CONFIG_POWER_RESET_SYSCON=y CONFIG_SYSCON_REBOOT_MODE=y From 74790cf981afd9806939427ad7701f3022ee5c06 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 10 Nov 2020 16:20:46 +0100 Subject: [PATCH 467/799] arm64: zynqmp: Move gic node to axi bus The reason for this change is that after change from amba to axi U-Boot started to show error like: Unable to update property /axi/ethernet@ff0e0000:mac-address, err=FDT_ERR_NOTFOUND Unable to update property /axi/ethernet@ff0e0000:local-mac-address, err=FDT_ERR_NOTFOUND The reason is implementation in fdt_nodename_eq_() which is taken from dtc to the kernel and to the U-Boot. Especially DTC commit d2a9da045897 ("libfdt: Make unit address optional for finding nodes") which is in DTC from 2007. The part of commit description is " This is contrary to traditional OF-like finddevice() behaviour, which allows the unit address to be omitted (which is useful when the device name is unambiguous without the address)." The kernel commit dfff9066e60e ("arm64: dts: zynqmp: Rename buses to be align with simple-bus yaml") changed amba-apu/amba to axi@0/axi but fdt_nodename_eq_() detects /axi/ as match for /axi@0/ because of commit above. That's why it easier to fix one DT inside the kernel by moving GIC node from own bus to generic axi bus as is done by others SoCs. This will avoid incorrect match because the unit address is omitted. Reported-by: Paul Thomas Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/f767fe007e446a2299fda9905e75b723c650a424.1605021644.git.michal.simek@xilinx.com --- arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 31 ++++++++++---------------- 1 file changed, 12 insertions(+), 19 deletions(-) diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi index 771f60e0346d..515b15ed634a 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi @@ -182,25 +182,6 @@ ranges; }; - amba_apu: axi@0 { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <1>; - ranges = <0 0 0 0 0xffffffff>; - - gic: interrupt-controller@f9010000 { - compatible = "arm,gic-400"; - #interrupt-cells = <3>; - reg = <0x0 0xf9010000 0x10000>, - <0x0 0xf9020000 0x20000>, - <0x0 0xf9040000 0x20000>, - <0x0 0xf9060000 0x20000>; - interrupt-controller; - interrupt-parent = <&gic>; - interrupts = <1 9 0xf04>; - }; - }; - amba: axi { compatible = "simple-bus"; #address-cells = <2>; @@ -339,6 +320,18 @@ power-domains = <&zynqmp_firmware PD_GDMA>; }; + gic: interrupt-controller@f9010000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + reg = <0x0 0xf9010000 0x0 0x10000>, + <0x0 0xf9020000 0x0 0x20000>, + <0x0 0xf9040000 0x0 0x20000>, + <0x0 0xf9060000 0x0 0x20000>; + interrupt-controller; + interrupt-parent = <&gic>; + interrupts = <1 9 0xf04>; + }; + /* LPDDMA default allows only secured access. inorder to enable * These dma channels, Users should ensure that these dma * Channels are allowed for non secure access. From 48ab2996f6837aa888ccc0671de7ef3e3185992e Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 29 Sep 2020 13:43:22 +0200 Subject: [PATCH 468/799] arm64: dts: zynqmp: Fix pcie ranges description DT schema is checking tuples which should be properly separated. The patch is doing this separation to avoid the following warning: ..yaml: axi: pcie@fd0e0000:ranges: [[33554432, 0, 3758096384, 0, 3758096384, 0, 268435456, 1124073472, 6, 0, 6, 0, 2, 0]] is not valid under any of the given schemas (Possible causes of the failure): ...dt.yaml: axi: pcie@fd0e0000:ranges: True was expected ...dt.yaml: axi: pcie@fd0e0000:ranges:0: [33554432, 0, 3758096384, 0, 3758096384, 0, 268435456, 1124073472, 6, 0, 6, 0, 2, 0] is too long Signed-off-by: Michal Simek Reviewed-by: Laurent Pinchart Link: https://lore.kernel.org/r/f59a63d8cb941592de6d2dee8afa6f120b2e40c8.1601379794.git.michal.simek@xilinx.com --- arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi index 515b15ed634a..66dad22b8a76 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi @@ -535,8 +535,8 @@ <0x0 0xfd480000 0x0 0x1000>, <0x80 0x00000000 0x0 0x1000000>; reg-names = "breg", "pcireg", "cfg"; - ranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000 /* non-prefetchable memory */ - 0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>;/* prefetchable memory */ + ranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000>,/* non-prefetchable memory */ + <0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>;/* prefetchable memory */ bus-range = <0x00 0xff>; interrupt-map-mask = <0x0 0x0 0x0 0x7>; interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>, From 9854bc7dfa5f7661538b08dc44d5e6c8876832fb Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 12 Nov 2020 13:52:34 +0100 Subject: [PATCH 469/799] arm64: dts: zynqmp: Wire mailbox with zynqmp-power driver The support to driver was added by commit ffdbae28d9d1 ("drivers: soc: xilinx: Use mailbox IPI callback") that's why also enable it via DT by default. It setups communication with firmware via IPI interface. Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/5d3523150890e494df308ee69523d0f0e7b33b22.1605185549.git.michal.simek@xilinx.com --- arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi index 66dad22b8a76..68923fbd0e89 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi @@ -99,6 +99,29 @@ }; }; + zynqmp_ipi { + compatible = "xlnx,zynqmp-ipi-mailbox"; + interrupt-parent = <&gic>; + interrupts = <0 35 4>; + xlnx,ipi-id = <0>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + ipi_mailbox_pmu1: mailbox@ff990400 { + reg = <0x0 0xff9905c0 0x0 0x20>, + <0x0 0xff9905e0 0x0 0x20>, + <0x0 0xff990e80 0x0 0x20>, + <0x0 0xff990ea0 0x0 0x20>; + reg-names = "local_request_region", + "local_response_region", + "remote_request_region", + "remote_response_region"; + #mbox-cells = <1>; + xlnx,ipi-id = <4>; + }; + }; + dcc: dcc { compatible = "arm,dcc"; status = "disabled"; @@ -128,6 +151,8 @@ compatible = "xlnx,zynqmp-power"; interrupt-parent = <&gic>; interrupts = <0 35 4>; + mboxes = <&ipi_mailbox_pmu1 0>, <&ipi_mailbox_pmu1 1>; + mbox-names = "tx", "rx"; }; zynqmp_clk: clock-controller { From a76a6c1893b0806657cb747c3c8949d3103fbc3f Mon Sep 17 00:00:00 2001 From: Roderick Colenbrander Date: Mon, 9 Nov 2020 23:22:27 -0800 Subject: [PATCH 470/799] HID: sony: Report more accurate DS4 power status. This patch moves the power supply status logic to DS3/DS4 parse_report, to allow for more accurate DS4 status reporting. The DS4 power status code was actually incorrect, but reported okay'ish data in most cases. There was a different interpretation of the battery_info values 0-10 or 0-9 depending on cable state. It added +1 to extend the range to 0-10. This is actually incorrect, there is no different range. Values higher than 11 actually indicates 'full' and 14/15 'error' for which we reported 100% and a valid power state. Moving the status logic to parse_report avoids having to pass more state to the generic sony_battery_get_property and simplifies the code. Signed-off-by: Roderick Colenbrander Signed-off-by: Jiri Kosina --- drivers/hid/hid-sony.c | 85 +++++++++++++++++++++++++----------------- 1 file changed, 50 insertions(+), 35 deletions(-) diff --git a/drivers/hid/hid-sony.c b/drivers/hid/hid-sony.c index 2f073f536070..81d526a5d003 100644 --- a/drivers/hid/hid-sony.c +++ b/drivers/hid/hid-sony.c @@ -562,9 +562,8 @@ struct sony_sc { u8 hotplug_worker_initialized; u8 state_worker_initialized; u8 defer_initialization; - u8 cable_state; - u8 battery_charging; u8 battery_capacity; + int battery_status; u8 led_state[MAX_LEDS]; u8 led_delay_on[MAX_LEDS]; u8 led_delay_off[MAX_LEDS]; @@ -892,7 +891,8 @@ static void sixaxis_parse_report(struct sony_sc *sc, u8 *rd, int size) static const u8 sixaxis_battery_capacity[] = { 0, 1, 25, 50, 75, 100 }; unsigned long flags; int offset; - u8 cable_state, battery_capacity, battery_charging; + u8 battery_capacity; + int battery_status; /* * The sixaxis is charging if the battery value is 0xee @@ -904,19 +904,16 @@ static void sixaxis_parse_report(struct sony_sc *sc, u8 *rd, int size) if (rd[offset] >= 0xee) { battery_capacity = 100; - battery_charging = !(rd[offset] & 0x01); - cable_state = 1; + battery_status = (rd[offset] & 0x01) ? POWER_SUPPLY_STATUS_FULL : POWER_SUPPLY_STATUS_CHARGING; } else { u8 index = rd[offset] <= 5 ? rd[offset] : 5; battery_capacity = sixaxis_battery_capacity[index]; - battery_charging = 0; - cable_state = 0; + battery_status = POWER_SUPPLY_STATUS_DISCHARGING; } spin_lock_irqsave(&sc->lock, flags); - sc->cable_state = cable_state; sc->battery_capacity = battery_capacity; - sc->battery_charging = battery_charging; + sc->battery_status = battery_status; spin_unlock_irqrestore(&sc->lock, flags); if (sc->quirks & SIXAXIS_CONTROLLER) { @@ -944,7 +941,8 @@ static void dualshock4_parse_report(struct sony_sc *sc, u8 *rd, int size) struct input_dev *input_dev = hidinput->input; unsigned long flags; int n, m, offset, num_touch_data, max_touch_data; - u8 cable_state, battery_capacity, battery_charging; + u8 cable_state, battery_capacity; + int battery_status; u16 timestamp; /* When using Bluetooth the header is 2 bytes longer, so skip these. */ @@ -1049,29 +1047,52 @@ static void dualshock4_parse_report(struct sony_sc *sc, u8 *rd, int size) */ offset = data_offset + DS4_INPUT_REPORT_BATTERY_OFFSET; cable_state = (rd[offset] >> 4) & 0x01; - battery_capacity = rd[offset] & 0x0F; /* - * When a USB power source is connected the battery level ranges from - * 0 to 10, and when running on battery power it ranges from 0 to 9. - * A battery level above 10 when plugged in means charge completed. + * Interpretation of the battery_capacity data depends on the cable state. + * When no cable is connected (bit4 is 0): + * - 0:10: percentage in units of 10%. + * When a cable is plugged in: + * - 0-10: percentage in units of 10%. + * - 11: battery is full + * - 14: not charging due to Voltage or temperature error + * - 15: charge error */ - if (!cable_state || battery_capacity > 10) - battery_charging = 0; - else - battery_charging = 1; + if (cable_state) { + u8 battery_data = rd[offset] & 0xf; - if (!cable_state) - battery_capacity++; - if (battery_capacity > 10) - battery_capacity = 10; + if (battery_data < 10) { + /* Take the mid-point for each battery capacity value, + * because on the hardware side 0 = 0-9%, 1=10-19%, etc. + * This matches official platform behavior, which does + * the same. + */ + battery_capacity = battery_data * 10 + 5; + battery_status = POWER_SUPPLY_STATUS_CHARGING; + } else if (battery_data == 10) { + battery_capacity = 100; + battery_status = POWER_SUPPLY_STATUS_CHARGING; + } else if (battery_data == 11) { + battery_capacity = 100; + battery_status = POWER_SUPPLY_STATUS_FULL; + } else { /* 14, 15 and undefined values */ + battery_capacity = 0; + battery_status = POWER_SUPPLY_STATUS_UNKNOWN; + } + } else { + u8 battery_data = rd[offset] & 0xf; - battery_capacity *= 10; + if (battery_data < 10) + battery_capacity = battery_data * 10 + 5; + else /* 10 */ + battery_capacity = 100; + + battery_status = POWER_SUPPLY_STATUS_DISCHARGING; + } spin_lock_irqsave(&sc->lock, flags); - sc->cable_state = cable_state; sc->battery_capacity = battery_capacity; - sc->battery_charging = battery_charging; + sc->battery_status = battery_status; spin_unlock_irqrestore(&sc->lock, flags); /* @@ -2300,12 +2321,12 @@ static int sony_battery_get_property(struct power_supply *psy, struct sony_sc *sc = power_supply_get_drvdata(psy); unsigned long flags; int ret = 0; - u8 battery_charging, battery_capacity, cable_state; + u8 battery_capacity; + int battery_status; spin_lock_irqsave(&sc->lock, flags); - battery_charging = sc->battery_charging; battery_capacity = sc->battery_capacity; - cable_state = sc->cable_state; + battery_status = sc->battery_status; spin_unlock_irqrestore(&sc->lock, flags); switch (psp) { @@ -2319,13 +2340,7 @@ static int sony_battery_get_property(struct power_supply *psy, val->intval = battery_capacity; break; case POWER_SUPPLY_PROP_STATUS: - if (battery_charging) - val->intval = POWER_SUPPLY_STATUS_CHARGING; - else - if (battery_capacity == 100 && cable_state) - val->intval = POWER_SUPPLY_STATUS_FULL; - else - val->intval = POWER_SUPPLY_STATUS_DISCHARGING; + val->intval = battery_status; break; default: ret = -EINVAL; From 1a8212e8fd1f50249f30e995460b17c0850c3212 Mon Sep 17 00:00:00 2001 From: Roderick Colenbrander Date: Mon, 9 Nov 2020 23:22:29 -0800 Subject: [PATCH 471/799] HID: sony: Don't use fw_version/hw_version for sysfs cleanup. The DS4 dongle reports fw_version and hw_version as 0 when no actual DS4 is connected to it. This prevents cleaning up sysfs nodes upon device remove. This patch decouples sysfs cleanup from the fw_version and hw_version values by introducing boolean values. Signed-off-by: Roderick Colenbrander Signed-off-by: Jiri Kosina --- drivers/hid/hid-sony.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/hid/hid-sony.c b/drivers/hid/hid-sony.c index 81d526a5d003..485455c300f2 100644 --- a/drivers/hid/hid-sony.c +++ b/drivers/hid/hid-sony.c @@ -550,7 +550,9 @@ struct sony_sc { struct power_supply_desc battery_desc; int device_id; unsigned fw_version; + bool fw_version_created; unsigned hw_version; + bool hw_version_created; u8 *output_report_dmabuf; #ifdef CONFIG_SONY_FF @@ -2738,19 +2740,17 @@ static int sony_input_configured(struct hid_device *hdev, ret = device_create_file(&sc->hdev->dev, &dev_attr_firmware_version); if (ret) { - /* Make zero for cleanup reasons of sysfs entries. */ - sc->fw_version = 0; - sc->hw_version = 0; hid_err(sc->hdev, "can't create sysfs firmware_version attribute err: %d\n", ret); goto err_stop; } + sc->fw_version_created = true; ret = device_create_file(&sc->hdev->dev, &dev_attr_hardware_version); if (ret) { - sc->hw_version = 0; hid_err(sc->hdev, "can't create sysfs hardware_version attribute err: %d\n", ret); goto err_stop; } + sc->hw_version_created = true; /* * The Dualshock 4 touchpad supports 2 touches and has a @@ -2842,9 +2842,9 @@ err_stop: */ if (sc->ds4_bt_poll_interval) device_remove_file(&sc->hdev->dev, &dev_attr_bt_poll_interval); - if (sc->fw_version) + if (sc->fw_version_created) device_remove_file(&sc->hdev->dev, &dev_attr_firmware_version); - if (sc->hw_version) + if (sc->hw_version_created) device_remove_file(&sc->hdev->dev, &dev_attr_hardware_version); sony_cancel_work_sync(sc); sony_remove_dev_list(sc); @@ -2929,10 +2929,10 @@ static void sony_remove(struct hid_device *hdev) if (sc->quirks & DUALSHOCK4_CONTROLLER_BT) device_remove_file(&sc->hdev->dev, &dev_attr_bt_poll_interval); - if (sc->fw_version) + if (sc->fw_version_created) device_remove_file(&sc->hdev->dev, &dev_attr_firmware_version); - if (sc->hw_version) + if (sc->hw_version_created) device_remove_file(&sc->hdev->dev, &dev_attr_hardware_version); sony_cancel_work_sync(sc); From f5dc93b7875bcb8be77baa792cc9432aaf65365b Mon Sep 17 00:00:00 2001 From: Roderick Colenbrander Date: Mon, 9 Nov 2020 23:22:28 -0800 Subject: [PATCH 472/799] HID: sony: Workaround for DS4 dongle hotplug kernel crash. The hid-sony driver has custom DS4 connect/disconnect logic for the DS4 dongle, which is a USB dongle acting as a proxy to Bluetooth connected DS4. The connect/disconnect logic works fine generally, however not in conjunction with Steam. Steam implements its own DS4 driver using hidraw. Both hid-sony and Steam are issuing their own HID requests and are racing each other during DS4 dongle connect/disconnect resulting in a kernel crash in hid-sony. The problem is that upon a DS4 connect to the dongle, hid-sony kicks of 'ds4_get_calibration_data' from within its dongle hotplug code. The calibration code issues raw HID feature report for reportID 0x02. When Steam is running, it issues a feature report for reportID 0x12 typically just prior to hid-sony requesting feature reportID 0x02. The result is that 'ds4_get_calibration_data' receives the data Steam requested as that's the HID report returing first. Currently this results in it processing invalid data, which ultimately results in a divide by zero upon a future 'dualshock4_parse_report'. The solution for now is to check within 'ds4_get_calibration_data' to check if we received data for the feature report we issued and if not retry. This fixes bug 206785. Signed-off-by: Roderick Colenbrander Signed-off-by: Jiri Kosina --- drivers/hid/hid-sony.c | 34 ++++++++++++++++++++++++++++------ 1 file changed, 28 insertions(+), 6 deletions(-) diff --git a/drivers/hid/hid-sony.c b/drivers/hid/hid-sony.c index 2f073f536070..c7baedfc78bd 100644 --- a/drivers/hid/hid-sony.c +++ b/drivers/hid/hid-sony.c @@ -1597,16 +1597,38 @@ static int dualshock4_get_calibration_data(struct sony_sc *sc) * of the controller, so that it sends input reports of type 0x11. */ if (sc->quirks & (DUALSHOCK4_CONTROLLER_USB | DUALSHOCK4_DONGLE)) { + int retries; + buf = kmalloc(DS4_FEATURE_REPORT_0x02_SIZE, GFP_KERNEL); if (!buf) return -ENOMEM; - ret = hid_hw_raw_request(sc->hdev, 0x02, buf, - DS4_FEATURE_REPORT_0x02_SIZE, - HID_FEATURE_REPORT, - HID_REQ_GET_REPORT); - if (ret < 0) - goto err_stop; + /* We should normally receive the feature report data we asked + * for, but hidraw applications such as Steam can issue feature + * reports as well. In particular for Dongle reconnects, Steam + * and this function are competing resulting in often receiving + * data for a different HID report, so retry a few times. + */ + for (retries = 0; retries < 3; retries++) { + ret = hid_hw_raw_request(sc->hdev, 0x02, buf, + DS4_FEATURE_REPORT_0x02_SIZE, + HID_FEATURE_REPORT, + HID_REQ_GET_REPORT); + if (ret < 0) + goto err_stop; + + if (buf[0] != 0x02) { + if (retries < 2) { + hid_warn(sc->hdev, "Retrying DualShock 4 get calibration report (0x02) request\n"); + continue; + } else { + ret = -EILSEQ; + goto err_stop; + } + } else { + break; + } + } } else { u8 bthdr = 0xA3; u32 crc; From 9735d9deb109afaab747fb853b804cb5dc144c0a Mon Sep 17 00:00:00 2001 From: Jing Xiangfeng Date: Tue, 10 Nov 2020 11:20:49 +0800 Subject: [PATCH 473/799] HID: intel-ish-hid: Remove unnecessary assignment to variable rv This assignment to rv is unused in an error path. So remove it. Signed-off-by: Jing Xiangfeng Signed-off-by: Jiri Kosina --- drivers/hid/intel-ish-hid/ishtp-hid.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/hid/intel-ish-hid/ishtp-hid.c b/drivers/hid/intel-ish-hid/ishtp-hid.c index b8aae69ad15d..393bed0abee9 100644 --- a/drivers/hid/intel-ish-hid/ishtp-hid.c +++ b/drivers/hid/intel-ish-hid/ishtp-hid.c @@ -211,10 +211,8 @@ int ishtp_hid_probe(unsigned int cur_hid_dev, struct ishtp_hid_data *hid_data; hid = hid_allocate_device(); - if (IS_ERR(hid)) { - rv = PTR_ERR(hid); - return -ENOMEM; - } + if (IS_ERR(hid)) + return PTR_ERR(hid); hid_data = kzalloc(sizeof(*hid_data), GFP_KERNEL); if (!hid_data) { From ba876cdc6ac9702138000d06613484de3de760db Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Thu, 19 Nov 2020 14:27:27 +0100 Subject: [PATCH 474/799] HID: logitech-hidpp: Add hid_device_id for V470 bluetooth mouse The Logitech V470 bluetooth mouse supports HID++-1.0 over bluetooth, add its id to the hidpp driver so that it handles it. This enables battery monitoring support. Note this mouse does not support hi-resolution scroll-wheel events. Signed-off-by: Hans de Goede Signed-off-by: Jiri Kosina --- drivers/hid/hid-logitech-hidpp.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/hid/hid-logitech-hidpp.c b/drivers/hid/hid-logitech-hidpp.c index 0ca723119547..f85781464807 100644 --- a/drivers/hid/hid-logitech-hidpp.c +++ b/drivers/hid/hid-logitech-hidpp.c @@ -4048,6 +4048,8 @@ static const struct hid_device_id hidpp_devices[] = { { /* MX5500 keyboard over Bluetooth */ HID_BLUETOOTH_DEVICE(USB_VENDOR_ID_LOGITECH, 0xb30b), .driver_data = HIDPP_QUIRK_HIDPP_CONSUMER_VENDOR_KEYS }, + { /* M-RCQ142 V470 Cordless Laser Mouse over Bluetooth */ + HID_BLUETOOTH_DEVICE(USB_VENDOR_ID_LOGITECH, 0xb008) }, { /* MX Master mouse over Bluetooth */ HID_BLUETOOTH_DEVICE(USB_VENDOR_ID_LOGITECH, 0xb012), .driver_data = HIDPP_QUIRK_HI_RES_SCROLL_X2121 }, From cae96a5d2bf38401b0e380f9025c375e99ac5a57 Mon Sep 17 00:00:00 2001 From: "Gustavo A. R. Silva" Date: Fri, 20 Nov 2020 12:33:24 -0600 Subject: [PATCH 475/799] HID: usbhid: Fix fall-through warnings for Clang In preparation to enable -Wimplicit-fallthrough for Clang, fix a couple of warnings by explicitly adding a couple of break statements instead of letting the code fall through to the next case. Link: https://github.com/KSPP/linux/issues/115 Signed-off-by: Gustavo A. R. Silva Signed-off-by: Jiri Kosina --- drivers/hid/usbhid/hid-core.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/hid/usbhid/hid-core.c b/drivers/hid/usbhid/hid-core.c index 17a29ee0ac6c..86257ce6d619 100644 --- a/drivers/hid/usbhid/hid-core.c +++ b/drivers/hid/usbhid/hid-core.c @@ -438,6 +438,7 @@ static void hid_irq_out(struct urb *urb) break; case -ESHUTDOWN: /* unplug */ unplug = 1; + break; case -EILSEQ: /* protocol error or unplug */ case -EPROTO: /* protocol error or unplug */ case -ECONNRESET: /* unlink */ @@ -489,6 +490,7 @@ static void hid_ctrl(struct urb *urb) break; case -ESHUTDOWN: /* unplug */ unplug = 1; + break; case -EILSEQ: /* protocol error or unplug */ case -EPROTO: /* protocol error or unplug */ case -ECONNRESET: /* unlink */ From 6b5542752605ccf2184f495fae518fac1d573226 Mon Sep 17 00:00:00 2001 From: "Gustavo A. R. Silva" Date: Fri, 20 Nov 2020 12:33:29 -0600 Subject: [PATCH 476/799] HID: input: Fix fall-through warnings for Clang In preparation to enable -Wimplicit-fallthrough for Clang, fix a warning by explicitly adding a goto statement instead of letting the code fall through to the next case. Link: https://github.com/KSPP/linux/issues/115 Signed-off-by: Gustavo A. R. Silva Signed-off-by: Jiri Kosina --- drivers/hid/hid-input.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/hid/hid-input.c b/drivers/hid/hid-input.c index b0db2a2ac15a..fb565902a8c3 100644 --- a/drivers/hid/hid-input.c +++ b/drivers/hid/hid-input.c @@ -746,6 +746,7 @@ static void hidinput_configure_usage(struct hid_input *hidinput, struct hid_fiel field->flags |= HID_MAIN_ITEM_RELATIVE; break; } + goto unknown; default: goto unknown; } From 2a6a35a9ecddb2b1d58f4948f471b3be8c506640 Mon Sep 17 00:00:00 2001 From: Rikard Falkeborn Date: Wed, 25 Nov 2020 00:01:09 +0100 Subject: [PATCH 477/799] HID: wacom: Constify attribute_groups These are never modified, so make them const to allow the compiler to put them in read-only memory. It also allows the compiler to shrink the resulting module with ~900 bytes, test-built with gcc 10.2 on x86_64. text data bss dec hex filename 204377 42832 576 247785 3c7e9 drivers/hid/wacom_old.ko 204240 42064 576 246880 3c460 drivers/hid/wacom_new.ko Signed-off-by: Rikard Falkeborn Signed-off-by: Jiri Kosina --- drivers/hid/wacom_sys.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/hid/wacom_sys.c b/drivers/hid/wacom_sys.c index cd71e7133944..045c464228d9 100644 --- a/drivers/hid/wacom_sys.c +++ b/drivers/hid/wacom_sys.c @@ -1173,7 +1173,7 @@ static struct attribute *cintiq_led_attrs[] = { NULL }; -static struct attribute_group cintiq_led_attr_group = { +static const struct attribute_group cintiq_led_attr_group = { .name = "wacom_led", .attrs = cintiq_led_attrs, }; @@ -1194,7 +1194,7 @@ static struct attribute *intuos4_led_attrs[] = { NULL }; -static struct attribute_group intuos4_led_attr_group = { +static const struct attribute_group intuos4_led_attr_group = { .name = "wacom_led", .attrs = intuos4_led_attrs, }; @@ -1205,7 +1205,7 @@ static struct attribute *intuos5_led_attrs[] = { NULL }; -static struct attribute_group intuos5_led_attr_group = { +static const struct attribute_group intuos5_led_attr_group = { .name = "wacom_led", .attrs = intuos5_led_attrs, }; @@ -1216,13 +1216,13 @@ static struct attribute *generic_led_attrs[] = { NULL }; -static struct attribute_group generic_led_attr_group = { +static const struct attribute_group generic_led_attr_group = { .name = "wacom_led", .attrs = generic_led_attrs, }; struct wacom_sysfs_group_devres { - struct attribute_group *group; + const struct attribute_group *group; struct kobject *root; }; @@ -1238,7 +1238,7 @@ static void wacom_devm_sysfs_group_release(struct device *dev, void *res) static int __wacom_devm_sysfs_create_group(struct wacom *wacom, struct kobject *root, - struct attribute_group *group) + const struct attribute_group *group) { struct wacom_sysfs_group_devres *devres; int error; @@ -1264,7 +1264,7 @@ static int __wacom_devm_sysfs_create_group(struct wacom *wacom, } static int wacom_devm_sysfs_create_group(struct wacom *wacom, - struct attribute_group *group) + const struct attribute_group *group) { return __wacom_devm_sysfs_create_group(wacom, &wacom->hdev->dev.kobj, group); @@ -1847,7 +1847,7 @@ static struct attribute *remote##SET_ID##_serial_attrs[] = { \ &remote##SET_ID##_mode_attr.attr, \ NULL \ }; \ -static struct attribute_group remote##SET_ID##_serial_group = { \ +static const struct attribute_group remote##SET_ID##_serial_group = { \ .name = NULL, \ .attrs = remote##SET_ID##_serial_attrs, \ } From 68d09380a62784ee5abd67462d2c04d094f3a4d2 Mon Sep 17 00:00:00 2001 From: YOSHIOKA Takuma Date: Sun, 22 Nov 2020 05:54:37 +0900 Subject: [PATCH 478/799] HID: elecom: rewrite report based on model specific parameters The report descriptor for EX-G wireless mouse (M-XGL20DLBK) is a bit different from that for trackball mice such as DEFT. For such mouse, the current `mouse_button_fixup` cannot be used as is, because it uses hard-coded indices for a report descriptor. Add parameters to `mouse_button_fixup` function, in order to support fixing report descriptors for more models. Signed-off-by: YOSHIOKA Takuma Signed-off-by: Jiri Kosina --- drivers/hid/hid-elecom.c | 41 ++++++++++++++++++++++++++++------------ 1 file changed, 29 insertions(+), 12 deletions(-) diff --git a/drivers/hid/hid-elecom.c b/drivers/hid/hid-elecom.c index 8c712d4bc075..233188100884 100644 --- a/drivers/hid/hid-elecom.c +++ b/drivers/hid/hid-elecom.c @@ -11,6 +11,7 @@ * Copyright (c) 2017 Diego Elio Pettenò * Copyright (c) 2017 Alex Manoussakis * Copyright (c) 2017 Tomasz Kramkowski + * Copyright (c) 2020 YOSHIOKA Takuma */ /* @@ -29,25 +30,26 @@ * report descriptor but it does not appear that these enable software to * control what the extra buttons map to. The only simple and straightforward * solution seems to involve fixing up the report descriptor. - * - * Report descriptor format: - * Positions 13, 15, 21 and 31 store the button bit count, button usage minimum, - * button usage maximum and padding bit count respectively. */ #define MOUSE_BUTTONS_MAX 8 static void mouse_button_fixup(struct hid_device *hdev, __u8 *rdesc, unsigned int rsize, + unsigned int button_bit_count, + unsigned int padding_bit, + unsigned int button_report_size, + unsigned int button_usage_maximum, int nbuttons) { - if (rsize < 32 || rdesc[12] != 0x95 || - rdesc[14] != 0x75 || rdesc[15] != 0x01 || - rdesc[20] != 0x29 || rdesc[30] != 0x75) + if (rsize < 32 || rdesc[button_bit_count] != 0x95 || + rdesc[button_report_size] != 0x75 || + rdesc[button_report_size + 1] != 0x01 || + rdesc[button_usage_maximum] != 0x29 || rdesc[padding_bit] != 0x75) return; hid_info(hdev, "Fixing up Elecom mouse button count\n"); nbuttons = clamp(nbuttons, 0, MOUSE_BUTTONS_MAX); - rdesc[13] = nbuttons; - rdesc[21] = nbuttons; - rdesc[31] = MOUSE_BUTTONS_MAX - nbuttons; + rdesc[button_bit_count + 1] = nbuttons; + rdesc[button_usage_maximum + 1] = nbuttons; + rdesc[padding_bit + 1] = MOUSE_BUTTONS_MAX - nbuttons; } static __u8 *elecom_report_fixup(struct hid_device *hdev, __u8 *rdesc, @@ -65,13 +67,28 @@ static __u8 *elecom_report_fixup(struct hid_device *hdev, __u8 *rdesc, case USB_DEVICE_ID_ELECOM_M_XT3URBK: case USB_DEVICE_ID_ELECOM_M_XT3DRBK: case USB_DEVICE_ID_ELECOM_M_XT4DRBK: - mouse_button_fixup(hdev, rdesc, *rsize, 6); + /* + * Report descriptor format: + * 12: button bit count + * 30: padding bit count + * 14: button report size + * 20: button usage maximum + */ + mouse_button_fixup(hdev, rdesc, *rsize, 12, 30, 14, 20, 6); break; case USB_DEVICE_ID_ELECOM_M_DT1URBK: case USB_DEVICE_ID_ELECOM_M_DT1DRBK: case USB_DEVICE_ID_ELECOM_M_HT1URBK: case USB_DEVICE_ID_ELECOM_M_HT1DRBK: - mouse_button_fixup(hdev, rdesc, *rsize, 8); + /*mouse_button_fixup(hdev, rdesc, *rsize, 13, 15, 21, 31, 8);*/ + /* + * Report descriptor format: + * 12: button bit count + * 30: padding bit count + * 14: button report size + * 20: button usage maximum + */ + mouse_button_fixup(hdev, rdesc, *rsize, 12, 30, 14, 20, 8); break; } return rdesc; From 55633e681afb57c9a8ff8a3b22083d44cbaee9e8 Mon Sep 17 00:00:00 2001 From: YOSHIOKA Takuma Date: Sun, 22 Nov 2020 05:54:38 +0900 Subject: [PATCH 479/799] HID: elecom: add support for EX-G M-XGL20DLBK wireless mouse Enables three buttons (Fn1, Fn2, and Fn3) on the ELECOM M-XGL20DLBK wireless mouse. While this mouse is EX-G brand, report descriptor is a bit different from EX-G trackball mouse. To enable extra buttons, report should be rewritten in a similar way to trackballs, but with different position parameters. Signed-off-by: YOSHIOKA Takuma Signed-off-by: Jiri Kosina --- drivers/hid/hid-elecom.c | 11 +++++++++++ drivers/hid/hid-ids.h | 1 + drivers/hid/hid-quirks.c | 1 + 3 files changed, 13 insertions(+) diff --git a/drivers/hid/hid-elecom.c b/drivers/hid/hid-elecom.c index 233188100884..3bd7207de2e8 100644 --- a/drivers/hid/hid-elecom.c +++ b/drivers/hid/hid-elecom.c @@ -64,6 +64,16 @@ static __u8 *elecom_report_fixup(struct hid_device *hdev, __u8 *rdesc, rdesc[47] = 0x00; } break; + case USB_DEVICE_ID_ELECOM_M_XGL20DLBK: + /* + * Report descriptor format: + * 20: button bit count + * 28: padding bit count + * 22: button report size + * 14: button usage maximum + */ + mouse_button_fixup(hdev, rdesc, *rsize, 20, 28, 22, 14, 8); + break; case USB_DEVICE_ID_ELECOM_M_XT3URBK: case USB_DEVICE_ID_ELECOM_M_XT3DRBK: case USB_DEVICE_ID_ELECOM_M_XT4DRBK: @@ -96,6 +106,7 @@ static __u8 *elecom_report_fixup(struct hid_device *hdev, __u8 *rdesc, static const struct hid_device_id elecom_devices[] = { { HID_BLUETOOTH_DEVICE(USB_VENDOR_ID_ELECOM, USB_DEVICE_ID_ELECOM_BM084) }, + { HID_USB_DEVICE(USB_VENDOR_ID_ELECOM, USB_DEVICE_ID_ELECOM_M_XGL20DLBK) }, { HID_USB_DEVICE(USB_VENDOR_ID_ELECOM, USB_DEVICE_ID_ELECOM_M_XT3URBK) }, { HID_USB_DEVICE(USB_VENDOR_ID_ELECOM, USB_DEVICE_ID_ELECOM_M_XT3DRBK) }, { HID_USB_DEVICE(USB_VENDOR_ID_ELECOM, USB_DEVICE_ID_ELECOM_M_XT4DRBK) }, diff --git a/drivers/hid/hid-ids.h b/drivers/hid/hid-ids.h index f170feaac40b..7fcbd3c02458 100644 --- a/drivers/hid/hid-ids.h +++ b/drivers/hid/hid-ids.h @@ -390,6 +390,7 @@ #define USB_VENDOR_ID_ELECOM 0x056e #define USB_DEVICE_ID_ELECOM_BM084 0x0061 +#define USB_DEVICE_ID_ELECOM_M_XGL20DLBK 0x00e6 #define USB_DEVICE_ID_ELECOM_M_XT3URBK 0x00fb #define USB_DEVICE_ID_ELECOM_M_XT3DRBK 0x00fc #define USB_DEVICE_ID_ELECOM_M_XT4DRBK 0x00fd diff --git a/drivers/hid/hid-quirks.c b/drivers/hid/hid-quirks.c index bf7ecab5d9e5..c94e44d6e652 100644 --- a/drivers/hid/hid-quirks.c +++ b/drivers/hid/hid-quirks.c @@ -366,6 +366,7 @@ static const struct hid_device_id hid_have_special_driver[] = { #endif #if IS_ENABLED(CONFIG_HID_ELECOM) { HID_BLUETOOTH_DEVICE(USB_VENDOR_ID_ELECOM, USB_DEVICE_ID_ELECOM_BM084) }, + { HID_BLUETOOTH_DEVICE(USB_VENDOR_ID_ELECOM, USB_DEVICE_ID_ELECOM_M_XGL20DLBK) }, { HID_USB_DEVICE(USB_VENDOR_ID_ELECOM, USB_DEVICE_ID_ELECOM_M_XT3URBK) }, { HID_USB_DEVICE(USB_VENDOR_ID_ELECOM, USB_DEVICE_ID_ELECOM_M_XT3DRBK) }, { HID_USB_DEVICE(USB_VENDOR_ID_ELECOM, USB_DEVICE_ID_ELECOM_M_XT4DRBK) }, From 1008230f2abeb624f6d71b2e1c424fa4eeebbf84 Mon Sep 17 00:00:00 2001 From: Ethan Warth Date: Tue, 17 Nov 2020 09:48:00 +0100 Subject: [PATCH 480/799] HID: mf: add support for 0079:1846 Mayflash/Dragonrise USB Gamecube Adapter Mayflash/Dragonrise seems to have yet another device ID for one of their Gamecube controller adapters. Previous to this commit, the adapter registered only one /dev/input/js* device, and all controller inputs (from any controller) were mapped to this device. This patch defines the 1846 USB device ID and enables the HID_QUIRK_MULTI_INPUT quirk for it, which fixes that (with the patch, four /dev/input/js* devices are created, one for each of the four controller ports). Signed-off-by: Ethan Warth Tested-by: Wladimir J. van der Laan Signed-off-by: Jiri Kosina --- drivers/hid/hid-ids.h | 1 + drivers/hid/hid-mf.c | 2 ++ drivers/hid/hid-quirks.c | 2 ++ 3 files changed, 5 insertions(+) diff --git a/drivers/hid/hid-ids.h b/drivers/hid/hid-ids.h index f170feaac40b..d1841fece116 100644 --- a/drivers/hid/hid-ids.h +++ b/drivers/hid/hid-ids.h @@ -359,6 +359,7 @@ #define USB_DEVICE_ID_DRAGONRISE_DOLPHINBAR 0x1803 #define USB_DEVICE_ID_DRAGONRISE_GAMECUBE1 0x1843 #define USB_DEVICE_ID_DRAGONRISE_GAMECUBE2 0x1844 +#define USB_DEVICE_ID_DRAGONRISE_GAMECUBE3 0x1846 #define USB_VENDOR_ID_DWAV 0x0eef #define USB_DEVICE_ID_EGALAX_TOUCHCONTROLLER 0x0001 diff --git a/drivers/hid/hid-mf.c b/drivers/hid/hid-mf.c index fc75f30f537c..92d7ecd41a78 100644 --- a/drivers/hid/hid-mf.c +++ b/drivers/hid/hid-mf.c @@ -153,6 +153,8 @@ static const struct hid_device_id mf_devices[] = { .driver_data = HID_QUIRK_MULTI_INPUT }, { HID_USB_DEVICE(USB_VENDOR_ID_DRAGONRISE, USB_DEVICE_ID_DRAGONRISE_GAMECUBE2), .driver_data = 0 }, /* No quirk required */ + { HID_USB_DEVICE(USB_VENDOR_ID_DRAGONRISE, USB_DEVICE_ID_DRAGONRISE_GAMECUBE3), + .driver_data = HID_QUIRK_MULTI_INPUT }, { } }; MODULE_DEVICE_TABLE(hid, mf_devices); diff --git a/drivers/hid/hid-quirks.c b/drivers/hid/hid-quirks.c index bf7ecab5d9e5..2e38340e19df 100644 --- a/drivers/hid/hid-quirks.c +++ b/drivers/hid/hid-quirks.c @@ -72,6 +72,7 @@ static const struct hid_device_id hid_quirks[] = { { HID_USB_DEVICE(USB_VENDOR_ID_DRAGONRISE, USB_DEVICE_ID_REDRAGON_SEYMUR2), HID_QUIRK_INCREMENT_USAGE_ON_DUPLICATE }, { HID_USB_DEVICE(USB_VENDOR_ID_DRAGONRISE, USB_DEVICE_ID_DRAGONRISE_DOLPHINBAR), HID_QUIRK_MULTI_INPUT }, { HID_USB_DEVICE(USB_VENDOR_ID_DRAGONRISE, USB_DEVICE_ID_DRAGONRISE_GAMECUBE1), HID_QUIRK_MULTI_INPUT }, + { HID_USB_DEVICE(USB_VENDOR_ID_DRAGONRISE, USB_DEVICE_ID_DRAGONRISE_GAMECUBE3), HID_QUIRK_MULTI_INPUT }, { HID_USB_DEVICE(USB_VENDOR_ID_DRAGONRISE, USB_DEVICE_ID_DRAGONRISE_PS3), HID_QUIRK_MULTI_INPUT }, { HID_USB_DEVICE(USB_VENDOR_ID_DRAGONRISE, USB_DEVICE_ID_DRAGONRISE_WIIU), HID_QUIRK_MULTI_INPUT }, { HID_USB_DEVICE(USB_VENDOR_ID_DWAV, USB_DEVICE_ID_EGALAX_TOUCHCONTROLLER), HID_QUIRK_MULTI_INPUT | HID_QUIRK_NOGET }, @@ -484,6 +485,7 @@ static const struct hid_device_id hid_have_special_driver[] = { { HID_USB_DEVICE(USB_VENDOR_ID_DRAGONRISE, USB_DEVICE_ID_DRAGONRISE_DOLPHINBAR) }, { HID_USB_DEVICE(USB_VENDOR_ID_DRAGONRISE, USB_DEVICE_ID_DRAGONRISE_GAMECUBE1) }, { HID_USB_DEVICE(USB_VENDOR_ID_DRAGONRISE, USB_DEVICE_ID_DRAGONRISE_GAMECUBE2) }, + { HID_USB_DEVICE(USB_VENDOR_ID_DRAGONRISE, USB_DEVICE_ID_DRAGONRISE_GAMECUBE3) }, #endif #if IS_ENABLED(CONFIG_HID_MICROSOFT) { HID_USB_DEVICE(USB_VENDOR_ID_MICROSOFT, USB_DEVICE_ID_MS_COMFORT_MOUSE_4500) }, From 3b4c137856d94f94231415793f45a104a19c3604 Mon Sep 17 00:00:00 2001 From: Marc Zyngier Date: Tue, 13 Oct 2020 10:58:51 +0100 Subject: [PATCH 481/799] arm64: tegra: Add missing CPU PMUs on Tegra186 Add the description of CPU PMUs for both the Denver and A57 clusters, which enables the perf subsystem. Signed-off-by: Marc Zyngier Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra186.dtsi | 28 +++++++++++++++++++----- 1 file changed, 22 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi index 0c46ab7bbbf3..a55d7ac95323 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi @@ -1534,7 +1534,7 @@ #address-cells = <1>; #size-cells = <0>; - cpu@0 { + denver_0: cpu@0 { compatible = "nvidia,tegra186-denver"; device_type = "cpu"; i-cache-size = <0x20000>; @@ -1547,7 +1547,7 @@ reg = <0x000>; }; - cpu@1 { + denver_1: cpu@1 { compatible = "nvidia,tegra186-denver"; device_type = "cpu"; i-cache-size = <0x20000>; @@ -1560,7 +1560,7 @@ reg = <0x001>; }; - cpu@2 { + ca57_0: cpu@2 { compatible = "arm,cortex-a57"; device_type = "cpu"; i-cache-size = <0xC000>; @@ -1573,7 +1573,7 @@ reg = <0x100>; }; - cpu@3 { + ca57_1: cpu@3 { compatible = "arm,cortex-a57"; device_type = "cpu"; i-cache-size = <0xC000>; @@ -1586,7 +1586,7 @@ reg = <0x101>; }; - cpu@4 { + ca57_2: cpu@4 { compatible = "arm,cortex-a57"; device_type = "cpu"; i-cache-size = <0xC000>; @@ -1599,7 +1599,7 @@ reg = <0x102>; }; - cpu@5 { + ca57_3: cpu@5 { compatible = "arm,cortex-a57"; device_type = "cpu"; i-cache-size = <0xC000>; @@ -1631,6 +1631,22 @@ }; }; + pmu_denver { + compatible = "nvidia,denver-pmu", "arm,armv8-pmuv3"; + interrupts = , + ; + interrupt-affinity = <&denver_0 &denver_1>; + }; + + pmu_a57 { + compatible = "arm,cortex-a57-pmu", "arm,armv8-pmuv3"; + interrupts = , + , + , + ; + interrupt-affinity = <&ca57_0 &ca57_1 &ca57_2 &ca57_3>; + }; + thermal-zones { a57 { polling-delay = <0>; From 776a3c04da9fa144241476f4a0d263899d6cad26 Mon Sep 17 00:00:00 2001 From: Marc Zyngier Date: Mon, 5 Oct 2020 14:32:56 +0100 Subject: [PATCH 482/799] arm64: tegra: Fix GIC400 missing GICH/GICV register regions GIC400 has full support for virtualization, and yet the tegra186 DT doesn't expose the GICH/GICV regions (despite exposing the maintenance interrupt that only makes sense for virtualization). Add the missing regions, based on the hunch that the HW doesn't use the CPU build-in interfaces, but instead the external ones provided by the GIC. KVM's virtual GIC now works with this change. Signed-off-by: Marc Zyngier Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra186.dtsi | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi index a55d7ac95323..98544d16d01b 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi @@ -845,7 +845,9 @@ #interrupt-cells = <3>; interrupt-controller; reg = <0x0 0x03881000 0x0 0x1000>, - <0x0 0x03882000 0x0 0x2000>; + <0x0 0x03882000 0x0 0x2000>, + <0x0 0x03884000 0x0 0x2000>, + <0x0 0x03886000 0x0 0x2000>; interrupts = ; interrupt-parent = <&gic>; From 6b26c1a034885923822f6c4d94f8644d32bc2481 Mon Sep 17 00:00:00 2001 From: Vidya Sagar Date: Mon, 26 Oct 2020 12:09:02 +0530 Subject: [PATCH 483/799] arm64: tegra: Fix DT binding for IO High Voltage entry Fix the device-tree entry that represents I/O High Voltage property by replacing 'nvidia,io-high-voltage' with 'nvidia,io-hv' as the former entry is deprecated. Fixes: dbb72e2c305b ("arm64: tegra: Add configuration for PCIe C5 sideband signals") Signed-off-by: Vidya Sagar Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra194.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index 93438d2b9469..6946fb210e48 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -378,7 +378,7 @@ nvidia,schmitt = ; nvidia,lpdr = ; nvidia,enable-input = ; - nvidia,io-high-voltage = ; + nvidia,io-hv = ; nvidia,tristate = ; nvidia,pull = ; }; @@ -390,7 +390,7 @@ nvidia,schmitt = ; nvidia,lpdr = ; nvidia,enable-input = ; - nvidia,io-high-voltage = ; + nvidia,io-hv = ; nvidia,tristate = ; nvidia,pull = ; }; From 5aaa0de991c7604b94b4765c3f8d054e31363cf1 Mon Sep 17 00:00:00 2001 From: Nicolas Chauvet Date: Sun, 27 Sep 2020 17:09:53 +0200 Subject: [PATCH 484/799] arm64: tegra: Add missing hot temperatures to Tegra132 thermal-zones According to dmesg, thermal-zones for mem and cpu are missing hot temperatures properties. throttrip: pll: missing hot temperature ... throttrip: mem: missing hot temperature ... Adding them will clear the messages. Signed-off-by: Nicolas Chauvet Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra132.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra132.dtsi b/arch/arm64/boot/dts/nvidia/tegra132.dtsi index e40281510c0c..cd913e59ba26 100644 --- a/arch/arm64/boot/dts/nvidia/tegra132.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra132.dtsi @@ -925,6 +925,11 @@ hysteresis = <1000>; type = "critical"; }; + mem_throttle_trip { + temperature = <99000>; + hysteresis = <1000>; + type = "hot"; + }; }; cooling-maps { @@ -975,6 +980,11 @@ hysteresis = <1000>; type = "critical"; }; + pllx_throttle_trip { + temperature = <99000>; + hysteresis = <1000>; + type = "hot"; + }; }; cooling-maps { From 3146cd55b00172c33d04638ee4a9287767d289eb Mon Sep 17 00:00:00 2001 From: Nicolas Chauvet Date: Sun, 27 Sep 2020 17:09:54 +0200 Subject: [PATCH 485/799] arm64: tegra: Add missing gpu-throt-level to Tegra210 soctherm On Jetson TX1 the following message can be seen: tegra_soctherm 700e2000.thermal-sensor: throttle-cfg: heavy: no throt prop or invalid prop This patch will fix the invalid prop issue according to the binding. Signed-off-by: Nicolas Chauvet Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra210.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi index d47c88950d38..a17ffdbba37c 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi @@ -1724,6 +1724,7 @@ throttle_heavy: heavy { nvidia,priority = <100>; nvidia,cpu-throt-percent = <85>; + nvidia,gpu-throt-level = ; #cooling-cells = <2>; }; From fdf278257e6de4a5754f58778efb3dfc3a646b0e Mon Sep 17 00:00:00 2001 From: Nicolas Chauvet Date: Sun, 27 Sep 2020 17:09:55 +0200 Subject: [PATCH 486/799] arm64: tegra: Add missing hot temperatures to Tegra210 thermal-zones According to dmesg, thermal-zones for mem and cpu are missing hot temperatures properties. throttrip: pll: missing hot temperature ... throttrip: mem: missing hot temperature ... Adding them will clear the messages. Signed-off-by: Nicolas Chauvet Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra210.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi index a17ffdbba37c..f31f75d9727d 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi @@ -1781,6 +1781,12 @@ type = "active"; }; + mem-hot-trip { + temperature = <100000>; + hysteresis = <1000>; + type = "hot"; + }; + mem-shutdown-trip { temperature = <103000>; hysteresis = <0>; @@ -1843,6 +1849,12 @@ hysteresis = <0>; type = "critical"; }; + + pllx-throttle-trip { + temperature = <100000>; + hysteresis = <1000>; + type = "hot"; + }; }; cooling-maps { From 1289bd9fec206dd8a854d6dba841e8d8a0d84f3e Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 20 Nov 2020 16:19:29 +0100 Subject: [PATCH 487/799] arm64: tegra: Hook up edp interrupt on Tegra132 SOCTHERM For some reason this was never hooked up. Do it now so that over-current interrupts can be logged. Reported-by: Nicolas Chauvet Suggested-by: Jon Hunter Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra132.dtsi | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra132.dtsi b/arch/arm64/boot/dts/nvidia/tegra132.dtsi index cd913e59ba26..0ce958a4f879 100644 --- a/arch/arm64/boot/dts/nvidia/tegra132.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra132.dtsi @@ -865,7 +865,9 @@ reg = <0x0 0x700e2000 0x0 0x600>, /* 0: SOC_THERM reg_base */ <0x0 0x70040000 0x0 0x200>; /* 2: CCROC reg_base */ reg-names = "soctherm-reg", "ccroc-reg"; - interrupts = ; + interrupts = , + ; + interrupt-names = "thermal", "edp"; clocks = <&tegra_car TEGRA124_CLK_TSENSOR>, <&tegra_car TEGRA124_CLK_SOC_THERM>; clock-names = "tsensor", "soctherm"; From b6e136c7e6ad4e379e58b3838ef3d8a8c669cd6d Mon Sep 17 00:00:00 2001 From: Sameer Pujar Date: Thu, 5 Nov 2020 15:54:03 +0530 Subject: [PATCH 488/799] arm64: tegra: Rename ADMA device nodes for Tegra210 DMA device nodes should follow regex pattern of "^dma-controller(@.*)?$". This is a preparatory patch to use YAML doc format for ADMA. Signed-off-by: Sameer Pujar Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts | 2 +- arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts | 2 +- arch/arm64/boot/dts/nvidia/tegra210-smaug.dts | 2 +- arch/arm64/boot/dts/nvidia/tegra210.dtsi | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts b/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts index 4c9c2a054642..69102dcea8b0 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts +++ b/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts @@ -119,7 +119,7 @@ aconnect@702c0000 { status = "okay"; - dma@702e2000 { + dma-controller@702e2000 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts index 859241db4b4d..6a877decffc1 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts @@ -629,7 +629,7 @@ aconnect@702c0000 { status = "okay"; - dma@702e2000 { + dma-controller@702e2000 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts b/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts index bd78378248a6..131c064d6991 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts +++ b/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts @@ -1717,7 +1717,7 @@ aconnect@702c0000 { status = "okay"; - dma@702e2000 { + dma-controller@702e2000 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi index f31f75d9727d..6d2a9d259319 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi @@ -1344,7 +1344,7 @@ ranges = <0x702c0000 0x0 0x702c0000 0x00040000>; status = "disabled"; - adma: dma@702e2000 { + adma: dma-controller@702e2000 { compatible = "nvidia,tegra210-adma"; reg = <0x702e2000 0x2000>; interrupt-parent = <&agic>; From 82514ecd61435c2d47c235e1343872b38db17be4 Mon Sep 17 00:00:00 2001 From: Jiri Kosina Date: Wed, 25 Nov 2020 17:40:23 +0100 Subject: [PATCH 489/799] HID: elecom: drop stray comment Drop spurious leftover comment. Signed-off-by: Jiri Kosina --- drivers/hid/hid-elecom.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/hid/hid-elecom.c b/drivers/hid/hid-elecom.c index 3bd7207de2e8..e59e9911fc37 100644 --- a/drivers/hid/hid-elecom.c +++ b/drivers/hid/hid-elecom.c @@ -90,7 +90,6 @@ static __u8 *elecom_report_fixup(struct hid_device *hdev, __u8 *rdesc, case USB_DEVICE_ID_ELECOM_M_DT1DRBK: case USB_DEVICE_ID_ELECOM_M_HT1URBK: case USB_DEVICE_ID_ELECOM_M_HT1DRBK: - /*mouse_button_fixup(hdev, rdesc, *rsize, 13, 15, 21, 31, 8);*/ /* * Report descriptor format: * 12: button bit count From 2f8913a7b17efd3a116825160a2d3a6610444587 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= Date: Thu, 12 Nov 2020 16:08:31 +0100 Subject: [PATCH 490/799] dt-bindings: arm: bcm: document BCM4908 bindings MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit BCM4908 is a new family that includes BCM4906, BCM4908 and BCM49408. It's mostly used in home routers and often replaces Northstar in vendors portfolio. Signed-off-by: Rafał Miłecki Signed-off-by: Florian Fainelli --- .../bindings/arm/bcm/brcm,bcm4908.yaml | 38 +++++++++++++++++++ 1 file changed, 38 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/bcm/brcm,bcm4908.yaml diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,bcm4908.yaml b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm4908.yaml new file mode 100644 index 000000000000..5fec063d9a13 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm4908.yaml @@ -0,0 +1,38 @@ +# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/bcm/brcm,bcm4908.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Broadcom BCM4908 device tree bindings + +description: + Broadcom BCM4906 / BCM4908 / BCM49408 Wi-Fi/network SoCs with Brahma CPUs. + +maintainers: + - Rafał Miłecki + +properties: + $nodename: + const: '/' + compatible: + oneOf: + - description: BCM4906 based boards + items: + - const: brcm,bcm4906 + - const: brcm,bcm4908 + + - description: BCM4908 based boards + items: + - enum: + - asus,gt-ac5300 + - const: brcm,bcm4908 + + - description: BCM49408 based boards + items: + - const: brcm,bcm49408 + - const: brcm,bcm4908 + +additionalProperties: true + +... From 2961f69f151c0a6771f55cef46398fe49ca20902 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= Date: Thu, 12 Nov 2020 16:08:32 +0100 Subject: [PATCH 491/799] arm64: dts: broadcom: add BCM4908 and Asus GT-AC5300 early DTS files MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit They don't descibe hardware fully yet but it's enough to boot a system. Some missing blocks: 1. PMC (Power Management Controller?) 2. Ethernet 3. Crypto 4. Thermal Asus DTS is missing defining full NAND partitions layout and buttons. Further changes will fill those gaps as soon as required bindings will be found / tested / added. Signed-off-by: Rafał Miłecki Signed-off-by: Florian Fainelli --- arch/arm64/boot/dts/broadcom/Makefile | 1 + arch/arm64/boot/dts/broadcom/bcm4908/Makefile | 2 + .../bcm4908/bcm4908-asus-gt-ac5300.dts | 66 +++++++ .../boot/dts/broadcom/bcm4908/bcm4908.dtsi | 187 ++++++++++++++++++ 4 files changed, 256 insertions(+) create mode 100644 arch/arm64/boot/dts/broadcom/bcm4908/Makefile create mode 100644 arch/arm64/boot/dts/broadcom/bcm4908/bcm4908-asus-gt-ac5300.dts create mode 100644 arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi diff --git a/arch/arm64/boot/dts/broadcom/Makefile b/arch/arm64/boot/dts/broadcom/Makefile index cb7de8d99223..998e240aa698 100644 --- a/arch/arm64/boot/dts/broadcom/Makefile +++ b/arch/arm64/boot/dts/broadcom/Makefile @@ -5,5 +5,6 @@ dtb-$(CONFIG_ARCH_BCM2835) += bcm2711-rpi-4-b.dtb \ bcm2837-rpi-3-b-plus.dtb \ bcm2837-rpi-cm3-io3.dtb +subdir-y += bcm4908 subdir-y += northstar2 subdir-y += stingray diff --git a/arch/arm64/boot/dts/broadcom/bcm4908/Makefile b/arch/arm64/boot/dts/broadcom/bcm4908/Makefile new file mode 100644 index 000000000000..ef26c23603ce --- /dev/null +++ b/arch/arm64/boot/dts/broadcom/bcm4908/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_BCM4908) += bcm4908-asus-gt-ac5300.dtb diff --git a/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908-asus-gt-ac5300.dts b/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908-asus-gt-ac5300.dts new file mode 100644 index 000000000000..13c6b86eef21 --- /dev/null +++ b/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908-asus-gt-ac5300.dts @@ -0,0 +1,66 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT + +#include +#include + +#include "bcm4908.dtsi" + +/ { + compatible = "asus,gt-ac5300", "brcm,bcm4908"; + model = "Asus GT-AC5300"; + + memory@0 { + device_type = "memory"; + reg = <0x00 0x00 0x00 0x40000000>; + }; + + gpio-keys-polled { + compatible = "gpio-keys-polled"; + poll-interval = <100>; + + wifi { + label = "WiFi"; + linux,code = ; + gpios = <&gpio0 28 GPIO_ACTIVE_LOW>; + }; + + wps { + label = "WPS"; + linux,code = ; + gpios = <&gpio0 29 GPIO_ACTIVE_LOW>; + }; + + restart { + label = "Reset"; + linux,code = ; + gpios = <&gpio0 30 GPIO_ACTIVE_LOW>; + }; + + brightness { + label = "LEDs"; + linux,code = ; + gpios = <&gpio0 31 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&nandcs { + nand-ecc-strength = <4>; + nand-ecc-step-size = <512>; + nand-on-flash-bbt; + brcm,nand-has-wp; + + #address-cells = <1>; + #size-cells = <0>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "cferom"; + reg = <0x0 0x100000>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi b/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi new file mode 100644 index 000000000000..f873dc44ce9c --- /dev/null +++ b/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi @@ -0,0 +1,187 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT + +#include +#include + +/dts-v1/; + +/ { + interrupt-parent = <&gic>; + + #address-cells = <2>; + #size-cells = <2>; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "brcm,brahma-b53"; + reg = <0x0>; + next-level-cache = <&l2>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "brcm,brahma-b53"; + reg = <0x1>; + enable-method = "spin-table"; + cpu-release-addr = <0x0 0xfff8>; + next-level-cache = <&l2>; + }; + + cpu2: cpu@2 { + device_type = "cpu"; + compatible = "brcm,brahma-b53"; + reg = <0x2>; + enable-method = "spin-table"; + cpu-release-addr = <0x0 0xfff8>; + next-level-cache = <&l2>; + }; + + cpu3: cpu@3 { + device_type = "cpu"; + compatible = "brcm,brahma-b53"; + reg = <0x3>; + enable-method = "spin-table"; + cpu-release-addr = <0x0 0xfff8>; + next-level-cache = <&l2>; + }; + + l2: l2-cache0 { + compatible = "cache"; + }; + }; + + axi@81000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00 0x00 0x81000000 0x4000>; + + gic: interrupt-controller@1000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0x1000 0x1000>, + <0x2000 0x2000>; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + }; + + pmu { + compatible = "arm,cortex-a53-pmu"; + interrupts = , + , + , + ; + interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; + }; + + clocks { + periph_clk: periph_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <50000000>; + clock-output-names = "periph"; + }; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00 0x00 0x80000000 0x10000>; + + usb@c300 { + compatible = "generic-ehci"; + reg = <0xc300 0x100>; + interrupts = ; + status = "disabled"; + }; + + usb@c400 { + compatible = "generic-ohci"; + reg = <0xc400 0x100>; + interrupts = ; + status = "disabled"; + }; + + usb@d000 { + compatible = "generic-xhci"; + reg = <0xd000 0x8c8>; + interrupts = ; + status = "disabled"; + }; + }; + + bus@ff800000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00 0x00 0xff800000 0x3000>; + + timer: timer@400 { + compatible = "brcm,bcm6328-timer", "syscon"; + reg = <0x400 0x3c>; + }; + + gpio0: gpio-controller@500 { + compatible = "brcm,bcm6345-gpio"; + reg-names = "dirout", "dat"; + reg = <0x500 0x28>, <0x528 0x28>; + + #gpio-cells = <2>; + gpio-controller; + }; + + uart0: serial@640 { + compatible = "brcm,bcm6345-uart"; + reg = <0x640 0x18>; + interrupts = ; + clocks = <&periph_clk>; + clock-names = "periph"; + status = "okay"; + }; + + nand@1800 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "brcm,brcmnand-v7.1", "brcm,brcmnand"; + reg = <0x1800 0x600>, <0x2000 0x10>; + reg-names = "nand", "nand-int-base"; + interrupts = ; + interrupt-names = "nand"; + status = "okay"; + + nandcs: nandcs@0 { + compatible = "brcm,nandcs"; + reg = <0>; + }; + }; + + reboot { + compatible = "syscon-reboot"; + regmap = <&timer>; + offset = <0x34>; + mask = <1>; + }; + }; +}; From dccb22d078ebd098115e4f66bde1ee2249c8640b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= Date: Thu, 12 Nov 2020 16:08:30 +0100 Subject: [PATCH 492/799] arm64: add config for Broadcom BCM4908 SoCs MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add ARCH_BCM4908 config that can be used for compiling DTS files. Signed-off-by: Rafał Miłecki Signed-off-by: Florian Fainelli --- arch/arm64/Kconfig.platforms | 8 ++++++++ arch/arm64/configs/defconfig | 1 + 2 files changed, 9 insertions(+) diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms index 6f2494dd6d60..ec60d32e8d5f 100644 --- a/arch/arm64/Kconfig.platforms +++ b/arch/arm64/Kconfig.platforms @@ -43,6 +43,14 @@ config ARCH_BCM2835 This enables support for the Broadcom BCM2837 and BCM2711 SoC. These SoCs are used in the Raspberry Pi 3 and 4 devices. +config ARCH_BCM4908 + bool "Broadcom BCM4908 family" + select GPIOLIB + help + This enables support for the Broadcom BCM4906, BCM4908 and + BCM49408 SoCs. These SoCs use Brahma-B53 cores and can be + found in home routers. + config ARCH_BCM_IPROC bool "Broadcom iProc SoC Family" select COMMON_CLK_IPROC diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 17a2df6a263e..ead6fa942994 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -32,6 +32,7 @@ CONFIG_ARCH_AGILEX=y CONFIG_ARCH_SUNXI=y CONFIG_ARCH_ALPINE=y CONFIG_ARCH_BCM2835=y +CONFIG_ARCH_BCM4908=y CONFIG_ARCH_BCM_IPROC=y CONFIG_ARCH_BERLIN=y CONFIG_ARCH_BRCMSTB=y From 225ef3a3e8f48154ca7a4cfe44d3b576aff2f860 Mon Sep 17 00:00:00 2001 From: Marek Szyprowski Date: Tue, 24 Nov 2020 09:33:12 +0100 Subject: [PATCH 493/799] ARM: multi_v7_defconfig: make Samsung Exynos EHCI driver a module Exynos EHCI driver is compiled as kernel built-in, but it requires Samsung USB2 Generic PHY driver to operate properly, which is compiled as module. Make the Exynos EHCI driver also a module, because having it built-in makes no sense. Exynos OHCI, which also uses that PHY driver, is already compiled as a module. Signed-off-by: Marek Szyprowski Link: https://lore.kernel.org/r/20201124083312.12356-1-m.szyprowski@samsung.com Signed-off-by: Krzysztof Kozlowski --- arch/arm/configs/multi_v7_defconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig index a33a0b8eda20..95943da93bd3 100644 --- a/arch/arm/configs/multi_v7_defconfig +++ b/arch/arm/configs/multi_v7_defconfig @@ -773,7 +773,7 @@ CONFIG_USB_XHCI_TEGRA=m CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_HCD_STI=y CONFIG_USB_EHCI_TEGRA=y -CONFIG_USB_EHCI_EXYNOS=y +CONFIG_USB_EHCI_EXYNOS=m CONFIG_USB_EHCI_MV=m CONFIG_USB_OHCI_HCD=y CONFIG_USB_OHCI_HCD_STI=y From 066c2a9448681b5fb1cfe459c5a1b9d817b017fb Mon Sep 17 00:00:00 2001 From: Matthias Kaehlcke Date: Tue, 24 Nov 2020 16:48:13 -0800 Subject: [PATCH 494/799] arm64: dts: qcom: sc7180-trogdor: Make pp3300_a the default supply for pp3300_hub The trogdor design has two options for supplying the 'pp3300_hub' power rail, it can be supplied by 'pp3300_l7c' or 'pp3300_a'. The 'pp3300_a' path includes a load switch that can be controlled through GPIO84. Initially trogdor boards used 'pp3300_l7c' to power the USB hub, newer revisions (will) use 'pp3300_a' as supply for 'pp3300_hub'. Add a DT node for the 'pp3300_a' path and a pinctrl entry for the GPIO. Make this path the default and keep trogdor rev1, lazor rev0 and rev1 on 'pp3300_l7c'. These earlier revisions also allocated the GPIO to the purpose of controlling the power switch, so there is no need to limit the pinctrl config to newer revisions. Remove the platform-wide 'always/boot-on' properties from 'pp3300_l7c' and add them to the boards that use this supply. Also delete the 'always/boot-on' properties of 'pp3300_hub' for these boards. Signed-off-by: Matthias Kaehlcke Reviewed-by: Douglas Anderson Link: https://lore.kernel.org/r/20201124164714.v4.1.I0ed4abdd2b2916fbedf76be254bc3457fb8b9655@changeid Signed-off-by: Bjorn Andersson --- .../boot/dts/qcom/sc7180-trogdor-lazor-r0.dts | 11 ++++++ .../boot/dts/qcom/sc7180-trogdor-lazor-r1.dts | 11 ++++++ .../arm64/boot/dts/qcom/sc7180-trogdor-r1.dts | 11 ++++++ arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi | 34 +++++++++++++++++-- 4 files changed, 64 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r0.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r0.dts index ae4c23a4fe65..30e3e769d2b4 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r0.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r0.dts @@ -14,6 +14,17 @@ compatible = "google,lazor-rev0", "qcom,sc7180"; }; +&pp3300_hub { + /* pp3300_l7c is used to power the USB hub */ + /delete-property/regulator-always-on; + /delete-property/regulator-boot-on; +}; + +&pp3300_l7c { + regulator-always-on; + regulator-boot-on; +}; + &sn65dsi86_out { /* * Lane 0 was incorrectly mapped on the cable, but we've now decided diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r1.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r1.dts index 9354d4c5ef7d..c2ef06367baf 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r1.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r1.dts @@ -13,3 +13,14 @@ model = "Google Lazor (rev1 - 2)"; compatible = "google,lazor-rev1", "google,lazor-rev2", "qcom,sc7180"; }; + +&pp3300_hub { + /* pp3300_l7c is used to power the USB hub */ + /delete-property/regulator-always-on; + /delete-property/regulator-boot-on; +}; + +&pp3300_l7c { + regulator-always-on; + regulator-boot-on; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-r1.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-r1.dts index 59d67fb0efe8..2cb522d6962e 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-r1.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-r1.dts @@ -53,6 +53,17 @@ ap_ts_pen_1v8: &i2c4 { }; }; +&pp3300_hub { + /* pp3300_l7c is used to power the USB hub */ + /delete-property/regulator-always-on; + /delete-property/regulator-boot-on; +}; + +&pp3300_l7c { + regulator-always-on; + regulator-boot-on; +}; + &sdhc_2 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi index e9b1182b3715..8ed7dd39f6e3 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi @@ -191,6 +191,24 @@ vin-supply = <&pp3300_a>; }; + pp3300_hub: pp3300-hub { + compatible = "regulator-fixed"; + regulator-name = "pp3300_hub"; + + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 84 GPIO_ACTIVE_HIGH>; + enable-active-high; + pinctrl-names = "default"; + pinctrl-0 = <&en_pp3300_hub>; + + regulator-always-on; + regulator-boot-on; + + vin-supply = <&pp3300_a>; + }; + /* BOARD-SPECIFIC TOP LEVEL NODES */ backlight: backlight { @@ -495,13 +513,10 @@ regulator-initial-mode = ; }; - pp3300_hub: pp3300_l7c: ldo7 { regulator-min-microvolt = <3304000>; regulator-max-microvolt = <3304000>; regulator-initial-mode = ; - regulator-always-on; - regulator-boot-on; }; pp1800_brij_vccio: @@ -1221,6 +1236,19 @@ ap_spi_fp: &spi10 { }; }; + en_pp3300_hub: en-pp3300-hub { + pinmux { + pins = "gpio84"; + function = "gpio"; + }; + + pinconf { + pins = "gpio84"; + drive-strength = <2>; + bias-disable; + }; + }; + fpmcu_boot0: fpmcu-boot0 { pinmux { pins = "gpio10"; From 1f4079b626eb6d38cfc638fd88903c1a943d2d2d Mon Sep 17 00:00:00 2001 From: Alexandre GRIVEAUX Date: Thu, 26 Nov 2020 08:05:16 +0100 Subject: [PATCH 495/799] ARM: zynq: Add Z-turn board V5 Adding Z-turn board V5 to resolve the change between: "Z-TURNBOARD_schematic.pdf" schematics state version 1 to 4 has Atheros AR8035 "Z-Turn_Board_sch_V15_20160303.pdf" schematics state version 5 has Micrel KSZ9031 Changes v1 -> v2: Instead of using new board, the v2 using a common devicetree for z-turn boards (zynq-zturn-common.dtsi) and for each board a specific DT Signed-off-by: Alexandre GRIVEAUX Link: https://lore.kernel.org/r/20201126070516.85882-1-agriveaux@deutnet.info Signed-off-by: Michal Simek --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/zynq-zturn-common.dtsi | 112 +++++++++++++++++++++++ arch/arm/boot/dts/zynq-zturn-v5.dts | 15 +++ arch/arm/boot/dts/zynq-zturn.dts | 101 +------------------- 4 files changed, 129 insertions(+), 100 deletions(-) create mode 100644 arch/arm/boot/dts/zynq-zturn-common.dtsi create mode 100644 arch/arm/boot/dts/zynq-zturn-v5.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index ce66ffd5a1bb..3de85fe42f76 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1302,6 +1302,7 @@ dtb-$(CONFIG_ARCH_ZYNQ) += \ zynq-zc770-xm013.dtb \ zynq-zed.dtb \ zynq-zturn.dtb \ + zynq-zturn-v5.dtb \ zynq-zybo.dtb \ zynq-zybo-z7.dtb dtb-$(CONFIG_MACH_ARMADA_370) += \ diff --git a/arch/arm/boot/dts/zynq-zturn-common.dtsi b/arch/arm/boot/dts/zynq-zturn-common.dtsi new file mode 100644 index 000000000000..84f3c85c5bab --- /dev/null +++ b/arch/arm/boot/dts/zynq-zturn-common.dtsi @@ -0,0 +1,112 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2015 Andrea Merello + * Copyright (C) 2017 Alexander Graf + * + * Based on zynq-zed.dts which is: + * Copyright (C) 2011 - 2014 Xilinx + * Copyright (C) 2012 National Instruments Corp. + * + */ + +/dts-v1/; +/include/ "zynq-7000.dtsi" + +/ { + compatible = "xlnx,zynq-7000"; + + aliases { + ethernet0 = &gem0; + serial0 = &uart1; + serial1 = &uart0; + mmc0 = &sdhci0; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x40000000>; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + gpio-leds { + compatible = "gpio-leds"; + usr-led1 { + label = "usr-led1"; + gpios = <&gpio0 0x0 0x1>; + default-state = "off"; + }; + + usr-led2 { + label = "usr-led2"; + gpios = <&gpio0 0x9 0x1>; + default-state = "off"; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + autorepeat; + K1 { + label = "K1"; + gpios = <&gpio0 0x32 0x1>; + linux,code = <0x66>; + wakeup-source; + autorepeat; + }; + }; +}; + +&clkc { + ps-clk-frequency = <33333333>; +}; + +&gem0 { + status = "okay"; + phy-mode = "rgmii-id"; + phy-handle = <ðernet_phy>; + + ethernet_phy: ethernet-phy@0 { + }; +}; + +&sdhci0 { + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&usb0 { + status = "okay"; + dr_mode = "host"; +}; + +&can0 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + clock-frequency = <400000>; + + stlm75@49 { + status = "okay"; + compatible = "lm75"; + reg = <0x49>; + }; + + accelerometer@53 { + compatible = "adi,adxl345", "adxl345", "adi,adxl34x", "adxl34x"; + reg = <0x53>; + interrupt-parent = <&intc>; + interrupts = <0x0 0x1e 0x4>; + }; +}; diff --git a/arch/arm/boot/dts/zynq-zturn-v5.dts b/arch/arm/boot/dts/zynq-zturn-v5.dts new file mode 100644 index 000000000000..536632a09a25 --- /dev/null +++ b/arch/arm/boot/dts/zynq-zturn-v5.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0 + +/dts-v1/; +/include/ "zynq-zturn-common.dtsi" + +/ { + model = "Zynq Z-Turn MYIR Board V5"; + compatible = "myir,zynq-zturn-v5", "xlnx,zynq-7000"; +}; + +&gem0 { + ethernet_phy: ethernet-phy@0 { + reg = <0x3>; + }; +}; diff --git a/arch/arm/boot/dts/zynq-zturn.dts b/arch/arm/boot/dts/zynq-zturn.dts index 5ec616ebca08..620b24a25e06 100644 --- a/arch/arm/boot/dts/zynq-zturn.dts +++ b/arch/arm/boot/dts/zynq-zturn.dts @@ -1,114 +1,15 @@ // SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2015 Andrea Merello - * Copyright (C) 2017 Alexander Graf - * - * Based on zynq-zed.dts which is: - * Copyright (C) 2011 - 2014 Xilinx - * Copyright (C) 2012 National Instruments Corp. - * - */ /dts-v1/; -/include/ "zynq-7000.dtsi" +/include/ "zynq-zturn-common.dtsi" / { model = "Zynq Z-Turn MYIR Board"; compatible = "myir,zynq-zturn", "xlnx,zynq-7000"; - - aliases { - ethernet0 = &gem0; - serial0 = &uart1; - serial1 = &uart0; - mmc0 = &sdhci0; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x40000000>; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - gpio-leds { - compatible = "gpio-leds"; - usr-led1 { - label = "usr-led1"; - gpios = <&gpio0 0x0 0x1>; - default-state = "off"; - }; - - usr-led2 { - label = "usr-led2"; - gpios = <&gpio0 0x9 0x1>; - default-state = "off"; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - autorepeat; - K1 { - label = "K1"; - gpios = <&gpio0 0x32 0x1>; - linux,code = <0x66>; - wakeup-source; - autorepeat; - }; - }; -}; - -&clkc { - ps-clk-frequency = <33333333>; }; &gem0 { - status = "okay"; - phy-mode = "rgmii-id"; - phy-handle = <ðernet_phy>; - ethernet_phy: ethernet-phy@0 { reg = <0x0>; }; }; - -&sdhci0 { - status = "okay"; -}; - -&uart0 { - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; - -&usb0 { - status = "okay"; - dr_mode = "host"; -}; - -&can0 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - clock-frequency = <400000>; - - stlm75@49 { - status = "okay"; - compatible = "lm75"; - reg = <0x49>; - }; - - accelerometer@53 { - compatible = "adi,adxl345", "adxl345", "adi,adxl34x", "adxl34x"; - reg = <0x53>; - interrupt-parent = <&intc>; - interrupts = <0x0 0x1e 0x4>; - }; -}; From 4f551b7bba09114fb33ccfcd18a3874c7fbcebb4 Mon Sep 17 00:00:00 2001 From: Serge Semin Date: Tue, 20 Oct 2020 14:59:38 +0300 Subject: [PATCH 496/799] ARM: dts: stm32: Harmonize EHCI/OHCI DT nodes name on stm32mp15 In accordance with the Generic EHCI/OHCI bindings the corresponding node name is suppose to comply with the Generic USB HCD DT schema, which requires the USB nodes to have the name acceptable by the regexp: "^usb(@.*)?" . Make sure the "generic-ehci" and "generic-ohci"-compatible nodes are correctly named. Signed-off-by: Serge Semin Acked-by: Amelie Delaunay Acked-by: Krzysztof Kozlowski Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp151.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/stm32mp151.dtsi b/arch/arm/boot/dts/stm32mp151.dtsi index 00361d9f0187..f0efd51329f6 100644 --- a/arch/arm/boot/dts/stm32mp151.dtsi +++ b/arch/arm/boot/dts/stm32mp151.dtsi @@ -1426,7 +1426,7 @@ status = "disabled"; }; - usbh_ohci: usbh-ohci@5800c000 { + usbh_ohci: usb@5800c000 { compatible = "generic-ohci"; reg = <0x5800c000 0x1000>; clocks = <&rcc USBH>; @@ -1435,7 +1435,7 @@ status = "disabled"; }; - usbh_ehci: usbh-ehci@5800d000 { + usbh_ehci: usb@5800d000 { compatible = "generic-ehci"; reg = <0x5800d000 0x1000>; clocks = <&rcc USBH>; From 08f07e9a195adf8ad73a799dc88d47196ac14dea Mon Sep 17 00:00:00 2001 From: Yann Gautier Date: Tue, 20 Oct 2020 16:04:51 +0200 Subject: [PATCH 497/799] ARM: dts: stm32: update sdmmc IP version for STM32MP15 Update the IP version to v2.0, which supports linked lists in internal DMA, and is present in STM32MP1 SoCs. The mmci driver supports the v2.0 periph id since 7a2a98be672b ("mmc: mmci: Add support for sdmmc variant revision 2.0"), so it's now Ok to add it into the SoC device tree to benefit from the improved DMA support. Signed-off-by: Ludovic Barre Signed-off-by: Yann Gautier Signed-off-by: Ahmad Fatoum Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp151.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/stm32mp151.dtsi b/arch/arm/boot/dts/stm32mp151.dtsi index f0efd51329f6..6d01b7f8fa51 100644 --- a/arch/arm/boot/dts/stm32mp151.dtsi +++ b/arch/arm/boot/dts/stm32mp151.dtsi @@ -1047,7 +1047,7 @@ sdmmc3: sdmmc@48004000 { compatible = "arm,pl18x", "arm,primecell"; - arm,primecell-periphid = <0x10153180>; + arm,primecell-periphid = <0x00253180>; reg = <0x48004000 0x400>; interrupts = ; interrupt-names = "cmd_irq"; @@ -1360,7 +1360,7 @@ sdmmc1: sdmmc@58005000 { compatible = "arm,pl18x", "arm,primecell"; - arm,primecell-periphid = <0x10153180>; + arm,primecell-periphid = <0x00253180>; reg = <0x58005000 0x1000>; interrupts = ; interrupt-names = "cmd_irq"; @@ -1375,7 +1375,7 @@ sdmmc2: sdmmc@58007000 { compatible = "arm,pl18x", "arm,primecell"; - arm,primecell-periphid = <0x10153180>; + arm,primecell-periphid = <0x00253180>; reg = <0x58007000 0x1000>; interrupts = ; interrupt-names = "cmd_irq"; From f885fbca0f53bd6a38183c37518b425f0a6944b4 Mon Sep 17 00:00:00 2001 From: Fabrice Gasnier Date: Fri, 16 Oct 2020 16:40:18 +0200 Subject: [PATCH 498/799] ARM: dts: stm32: Add LP timer irqs on stm32mp151 Add all LP timer irqs on stm32mp151. Signed-off-by: Fabrice Gasnier Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp151.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/boot/dts/stm32mp151.dtsi b/arch/arm/boot/dts/stm32mp151.dtsi index 6d01b7f8fa51..05a00789e0d6 100644 --- a/arch/arm/boot/dts/stm32mp151.dtsi +++ b/arch/arm/boot/dts/stm32mp151.dtsi @@ -362,6 +362,7 @@ #size-cells = <0>; compatible = "st,stm32-lptimer"; reg = <0x40009000 0x400>; + interrupts-extended = <&exti 47 IRQ_TYPE_LEVEL_HIGH>; clocks = <&rcc LPTIM1_K>; clock-names = "mux"; status = "disabled"; @@ -1156,6 +1157,7 @@ #size-cells = <0>; compatible = "st,stm32-lptimer"; reg = <0x50021000 0x400>; + interrupts-extended = <&exti 48 IRQ_TYPE_LEVEL_HIGH>; clocks = <&rcc LPTIM2_K>; clock-names = "mux"; status = "disabled"; @@ -1183,6 +1185,7 @@ #size-cells = <0>; compatible = "st,stm32-lptimer"; reg = <0x50022000 0x400>; + interrupts-extended = <&exti 50 IRQ_TYPE_LEVEL_HIGH>; clocks = <&rcc LPTIM3_K>; clock-names = "mux"; status = "disabled"; @@ -1203,6 +1206,7 @@ lptimer4: timer@50023000 { compatible = "st,stm32-lptimer"; reg = <0x50023000 0x400>; + interrupts-extended = <&exti 52 IRQ_TYPE_LEVEL_HIGH>; clocks = <&rcc LPTIM4_K>; clock-names = "mux"; status = "disabled"; @@ -1217,6 +1221,7 @@ lptimer5: timer@50024000 { compatible = "st,stm32-lptimer"; reg = <0x50024000 0x400>; + interrupts-extended = <&exti 53 IRQ_TYPE_LEVEL_HIGH>; clocks = <&rcc LPTIM5_K>; clock-names = "mux"; status = "disabled"; From 928caf877d149318779f3b188e2e2df0725e60e4 Mon Sep 17 00:00:00 2001 From: Fabrice Gasnier Date: Fri, 16 Oct 2020 16:40:19 +0200 Subject: [PATCH 499/799] ARM: dts: stm32: Add LP timer wakeup-source on stm32mp151 LP timer can be used to wakeup from stop mode on stm32mp151. Add wakeup-source properties to all LP timer instances. Signed-off-by: Fabrice Gasnier Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp151.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/boot/dts/stm32mp151.dtsi b/arch/arm/boot/dts/stm32mp151.dtsi index 05a00789e0d6..6ffcf06dc0e8 100644 --- a/arch/arm/boot/dts/stm32mp151.dtsi +++ b/arch/arm/boot/dts/stm32mp151.dtsi @@ -365,6 +365,7 @@ interrupts-extended = <&exti 47 IRQ_TYPE_LEVEL_HIGH>; clocks = <&rcc LPTIM1_K>; clock-names = "mux"; + wakeup-source; status = "disabled"; pwm { @@ -1160,6 +1161,7 @@ interrupts-extended = <&exti 48 IRQ_TYPE_LEVEL_HIGH>; clocks = <&rcc LPTIM2_K>; clock-names = "mux"; + wakeup-source; status = "disabled"; pwm { @@ -1188,6 +1190,7 @@ interrupts-extended = <&exti 50 IRQ_TYPE_LEVEL_HIGH>; clocks = <&rcc LPTIM3_K>; clock-names = "mux"; + wakeup-source; status = "disabled"; pwm { @@ -1209,6 +1212,7 @@ interrupts-extended = <&exti 52 IRQ_TYPE_LEVEL_HIGH>; clocks = <&rcc LPTIM4_K>; clock-names = "mux"; + wakeup-source; status = "disabled"; pwm { @@ -1224,6 +1228,7 @@ interrupts-extended = <&exti 53 IRQ_TYPE_LEVEL_HIGH>; clocks = <&rcc LPTIM5_K>; clock-names = "mux"; + wakeup-source; status = "disabled"; pwm { From 304b5691bfd06c94fedff34a08ffbce0bfcfa0cb Mon Sep 17 00:00:00 2001 From: Lionel Debieve Date: Thu, 5 Nov 2020 11:23:29 +0100 Subject: [PATCH 500/799] ARM: dts: stm32: enable HASH by default on stm32mp15 Enable HASH1 device for HASH accelerated support on stm32mp15 STMicroelectronics platforms. Signed-off-by: Lionel Debieve Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp157c-ed1.dts | 4 ++++ arch/arm/boot/dts/stm32mp15xx-dkx.dtsi | 4 ++++ 2 files changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/stm32mp157c-ed1.dts b/arch/arm/boot/dts/stm32mp157c-ed1.dts index 2e77ccec3fc1..1a98a29b3283 100644 --- a/arch/arm/boot/dts/stm32mp157c-ed1.dts +++ b/arch/arm/boot/dts/stm32mp157c-ed1.dts @@ -136,6 +136,10 @@ contiguous-area = <&gpu_reserved>; }; +&hash1 { + status = "okay"; +}; + &i2c4 { pinctrl-names = "default", "sleep"; pinctrl-0 = <&i2c4_pins_a>; diff --git a/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi b/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi index 93398cfae97e..e92a18542306 100644 --- a/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi +++ b/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi @@ -151,6 +151,10 @@ contiguous-area = <&gpu_reserved>; }; +&hash1 { + status = "okay"; +}; + &i2c1 { pinctrl-names = "default", "sleep"; pinctrl-0 = <&i2c1_pins_a>; From ee0035b23327007c1455f47ab442e591f0eb8afe Mon Sep 17 00:00:00 2001 From: Nicolas Toromanoff Date: Thu, 5 Nov 2020 11:23:30 +0100 Subject: [PATCH 501/799] ARM: dts: stm32: enable CRC1 by default on stm32mp15 Enable CRC1 device for CRC-32 accelerated support on stm32mp15 STMicroelectronics platforms. Signed-off-by: Nicolas Toromanoff Signed-off-by: Lionel Debieve Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp157c-ed1.dts | 4 ++++ arch/arm/boot/dts/stm32mp15xx-dkx.dtsi | 4 ++++ 2 files changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/stm32mp157c-ed1.dts b/arch/arm/boot/dts/stm32mp157c-ed1.dts index 1a98a29b3283..99796ffa43bf 100644 --- a/arch/arm/boot/dts/stm32mp157c-ed1.dts +++ b/arch/arm/boot/dts/stm32mp157c-ed1.dts @@ -115,6 +115,10 @@ }; }; +&crc1 { + status = "okay"; +}; + &dac { pinctrl-names = "default"; pinctrl-0 = <&dac_ch1_pins_a &dac_ch2_pins_a>; diff --git a/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi b/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi index e92a18542306..4e74e55a4f07 100644 --- a/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi +++ b/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi @@ -124,6 +124,10 @@ status = "okay"; }; +&crc1 { + status = "okay"; +}; + &dts { status = "okay"; }; From b6aa35c7393680ee0a1286ca3b3237fd106ef896 Mon Sep 17 00:00:00 2001 From: Lionel Debieve Date: Thu, 5 Nov 2020 11:23:31 +0100 Subject: [PATCH 502/799] ARM: dts: stm32: enable CRYP by default on stm32mp15 Enable CRYP1 device for cryp accelerated support on stm32mp157C-EV1/DK2 STMicroelectronics platforms. Signed-off-by: Nicolas Toromanoff Signed-off-by: Lionel Debieve Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp157c-dk2.dts | 4 ++++ arch/arm/boot/dts/stm32mp157c-ed1.dts | 4 ++++ 2 files changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/stm32mp157c-dk2.dts b/arch/arm/boot/dts/stm32mp157c-dk2.dts index 045636555ddd..2bc92ef3aeb9 100644 --- a/arch/arm/boot/dts/stm32mp157c-dk2.dts +++ b/arch/arm/boot/dts/stm32mp157c-dk2.dts @@ -29,6 +29,10 @@ }; }; +&cryp1 { + status = "okay"; +}; + &dsi { status = "okay"; phy-dsi-supply = <®18>; diff --git a/arch/arm/boot/dts/stm32mp157c-ed1.dts b/arch/arm/boot/dts/stm32mp157c-ed1.dts index 99796ffa43bf..81a7d5849db4 100644 --- a/arch/arm/boot/dts/stm32mp157c-ed1.dts +++ b/arch/arm/boot/dts/stm32mp157c-ed1.dts @@ -119,6 +119,10 @@ status = "okay"; }; +&cryp1 { + status = "okay"; +}; + &dac { pinctrl-names = "default"; pinctrl-0 = <&dac_ch1_pins_a &dac_ch2_pins_a>; From 07e3454493e26fd5830c66a02eba705115748195 Mon Sep 17 00:00:00 2001 From: Hugues Fruchet Date: Wed, 4 Nov 2020 18:32:11 +0100 Subject: [PATCH 503/799] ARM: dts: stm32: set bus-type in DCMI endpoint for stm32mp157c-ev1 board Explicitly set bus-type to parallel mode in DCMI endpoint (bus-type=5). Signed-off-by: Hugues Fruchet Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp157c-ev1.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/stm32mp157c-ev1.dts b/arch/arm/boot/dts/stm32mp157c-ev1.dts index a55e80ce2602..5c5b1ddf7bfd 100644 --- a/arch/arm/boot/dts/stm32mp157c-ev1.dts +++ b/arch/arm/boot/dts/stm32mp157c-ev1.dts @@ -90,6 +90,7 @@ port { dcmi_0: endpoint { remote-endpoint = <&ov5640_0>; + bus-type = <5>; bus-width = <8>; hsync-active = <0>; vsync-active = <0>; From 096b0243fae36282bb774421e4bcaeb8387e87e1 Mon Sep 17 00:00:00 2001 From: Hugues Fruchet Date: Wed, 4 Nov 2020 18:32:12 +0100 Subject: [PATCH 504/799] ARM: dts: stm32: set bus-type in DCMI endpoint for stm32429i-eval board Explicitly set bus-type to parallel mode in DCMI endpoint (bus-type=5). Signed-off-by: Hugues Fruchet Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32429i-eval.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/stm32429i-eval.dts b/arch/arm/boot/dts/stm32429i-eval.dts index 67e7648de41e..7e10ae744c9d 100644 --- a/arch/arm/boot/dts/stm32429i-eval.dts +++ b/arch/arm/boot/dts/stm32429i-eval.dts @@ -188,6 +188,7 @@ port { dcmi_0: endpoint { remote-endpoint = <&ov2640_0>; + bus-type = <5>; bus-width = <8>; hsync-active = <0>; vsync-active = <0>; From dc37a51b258c13bf9dc8f34c5772cb45b93d35ae Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Thu, 22 Oct 2020 19:38:51 +0200 Subject: [PATCH 505/799] ARM: dts: stm32: reorder spi4 within stm32mp15-pinctrl Move spi4 at the right alphabetical place within stm32mp15-pinctrl Fixes: 4fe663890ac5 ("ARM: dts: stm32: Fix spi4 pins in stm32mp15-pinctrl") Signed-off-by: Patrick Delaunay Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp15-pinctrl.dtsi | 28 ++++++++++++------------ 1 file changed, 14 insertions(+), 14 deletions(-) diff --git a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi index 9dbefa77b03e..e595e103bcbd 100644 --- a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi +++ b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi @@ -1646,6 +1646,20 @@ }; }; + spi4_pins_a: spi4-0 { + pins { + pinmux = , /* SPI4_SCK */ + ; /* SPI4_MOSI */ + bias-disable; + drive-push-pull; + slew-rate = <1>; + }; + pins2 { + pinmux = ; /* SPI4_MISO */ + bias-disable; + }; + }; + uart4_pins_a: uart4-0 { pins1 { pinmux = ; /* UART4_TX */ @@ -1781,20 +1795,6 @@ }; }; - spi4_pins_a: spi4-0 { - pins { - pinmux = , /* SPI4_SCK */ - ; /* SPI4_MOSI */ - bias-disable; - drive-push-pull; - slew-rate = <1>; - }; - pins2 { - pinmux = ; /* SPI4_MISO */ - bias-disable; - }; - }; - usart2_pins_a: usart2-0 { pins1 { pinmux = , /* USART2_TX */ From 8e568db6020f13561a4e3e025a17a7572f80ed35 Mon Sep 17 00:00:00 2001 From: Amelie Delaunay Date: Fri, 6 Nov 2020 17:58:01 +0100 Subject: [PATCH 506/799] dt-bindings: connector: add typec-power-opmode property to usb-connector Power operation mode may depends on hardware design, so, add the optional property typec-power-opmode for usb-c connector to select the power operation mode capability. Signed-off-by: Amelie Delaunay Reviewed-by: Rob Herring Signed-off-by: Alexandre Torgue --- .../bindings/connector/usb-connector.yaml | 24 +++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/Documentation/devicetree/bindings/connector/usb-connector.yaml b/Documentation/devicetree/bindings/connector/usb-connector.yaml index 728f82db073d..ccf6eb22ba05 100644 --- a/Documentation/devicetree/bindings/connector/usb-connector.yaml +++ b/Documentation/devicetree/bindings/connector/usb-connector.yaml @@ -93,6 +93,24 @@ properties: - device - dual + typec-power-opmode: + description: Determines the power operation mode that the Type C connector + will support and will advertise through CC pins when it has no power + delivery support. + - "default" corresponds to default USB voltage and current defined by the + USB 2.0 and USB 3.2 specifications, 5V 500mA for USB 2.0 ports and + 5V 900mA or 1500mA for USB 3.2 ports in single-lane or dual-lane + operation respectively. + - "1.5A" and "3.0A", 5V 1.5A and 5V 3.0A respectively, as defined in USB + Type-C Cable and Connector specification, when Power Delivery is not + supported. + allOf: + - $ref: /schemas/types.yaml#definitions/string + enum: + - default + - 1.5A + - 3.0A + # The following are optional properties for "usb-c-connector" with power # delivery support. source-pdos: @@ -173,6 +191,12 @@ allOf: type: const: micro +anyOf: + - not: + required: + - typec-power-opmode + - new-source-frs-typec-current + additionalProperties: true examples: From 70966729b564cb7deb6aee1bd6212a1b594699f4 Mon Sep 17 00:00:00 2001 From: Amelie Delaunay Date: Fri, 6 Nov 2020 17:58:02 +0100 Subject: [PATCH 507/799] dt-bindings: usb: Add DT bindings for STUSB160x Type-C controller Add binding documentation for the STMicroelectronics STUSB160x Type-C port controller. Signed-off-by: Amelie Delaunay Reviewed-by: Rob Herring Signed-off-by: Alexandre Torgue --- .../devicetree/bindings/usb/st,stusb160x.yaml | 87 +++++++++++++++++++ 1 file changed, 87 insertions(+) create mode 100644 Documentation/devicetree/bindings/usb/st,stusb160x.yaml diff --git a/Documentation/devicetree/bindings/usb/st,stusb160x.yaml b/Documentation/devicetree/bindings/usb/st,stusb160x.yaml new file mode 100644 index 000000000000..9a51efa9d101 --- /dev/null +++ b/Documentation/devicetree/bindings/usb/st,stusb160x.yaml @@ -0,0 +1,87 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/usb/st,stusb160x.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: STMicroelectronics STUSB160x Type-C controller bindings + +maintainers: + - Amelie Delaunay + +properties: + compatible: + enum: + - st,stusb1600 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + vdd-supply: + description: main power supply (4.1V-22V) + + vsys-supply: + description: low power supply (3.0V-5.5V) + + vconn-supply: + description: power supply (2.7V-5.5V) used to supply VConn on CC pin in + source or dual power role + + connector: + type: object + + allOf: + - $ref: ../connector/usb-connector.yaml + + properties: + compatible: + const: usb-c-connector + + power-role: true + + typec-power-opmode: true + + required: + - compatible + +required: + - compatible + - reg + - connector + +additionalProperties: false + +examples: + - | + #include + i2c4 { + #address-cells = <1>; + #size-cells = <0>; + + typec: stusb1600@28 { + compatible = "st,stusb1600"; + reg = <0x28>; + vdd-supply = <&vbus_drd>; + vsys-supply = <&vdd_usb>; + interrupts = <11 IRQ_TYPE_EDGE_FALLING>; + interrupt-parent = <&gpioi>; + + typec_con: connector { + compatible = "usb-c-connector"; + label = "USB-C"; + power-role = "dual"; + data-role = "dual"; + typec-power-opmode = "default"; + + port { + typec_con_ep: endpoint { + remote-endpoint = <&usbotg_hs_ep>; + }; + }; + }; + }; + }; +... From 83686162c0eb9d94dcab5d6a4e34fc545c331c63 Mon Sep 17 00:00:00 2001 From: Amelie Delaunay Date: Fri, 6 Nov 2020 17:58:04 +0100 Subject: [PATCH 508/799] ARM: dts: stm32: add STUSB1600 Type-C using I2C4 on stm32mp15xx-dkx This patch adds support for STUSB1600 USB Type-C port controller, used on I2C4 on stm32mp15xx-dkx. The default configuration on this board, on Type-C connector, is: - Dual Power Role (DRP), so set power-role to "dual"; - Vbus limited to 500mA, so set typec-power-opmode to "default" (it means 500mA in USB 2.0). typec-power-opmode is used to reconfigure the STUSB1600 advertising of current capability when its NVM is not in line with the board layout. On stm32mp15xx-dkx, Vbus power source of STUSB1600 is 5V_VIN. So power operation mode depends on the power supply used. To avoid any power issues, it is better to limit Vbus to 500mA on this board. ALERT# is the interrupt pin of STUSB1600. It needs an external pull-up, and signal is active low. USB OTG controller ID and Vbus signals are not connected on stm32mp15xx-dkx boards, so disconnection are not detected. Without DWC2 usb-role-switch: - if you unplug the USB cable from the Type-C port, you have to manually disconnect the USB gadget: echo disconnect > /sys/devices/platform/soc/49000000.usb-otg/udc/49000000.usb-otg/soft_connect - Then you can plug the USB cable again in the Type-C port, and manually reconnect the USB gadget: echo connect > /sys/devices/platform/soc/49000000.usb-otg/udc/49000000.usb-otg/soft_connect With DWC2 usb-role-switch, USB gadget is dynamically disconnected or connected. Signed-off-by: Amelie Delaunay Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp15-pinctrl.dtsi | 7 ++++++ arch/arm/boot/dts/stm32mp15xx-dkx.dtsi | 30 ++++++++++++++++++++++++ 2 files changed, 37 insertions(+) diff --git a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi index e595e103bcbd..20a59e8f7a33 100644 --- a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi +++ b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi @@ -1660,6 +1660,13 @@ }; }; + stusb1600_pins_a: stusb1600-0 { + pins { + pinmux = ; + bias-pull-up; + }; + }; + uart4_pins_a: uart4-0 { pins1 { pinmux = ; /* UART4_TX */ diff --git a/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi b/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi index 4e74e55a4f07..89c0e1ddc387 100644 --- a/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi +++ b/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi @@ -246,6 +246,30 @@ /delete-property/dmas; /delete-property/dma-names; + stusb1600@28 { + compatible = "st,stusb1600"; + reg = <0x28>; + interrupts = <11 IRQ_TYPE_EDGE_FALLING>; + interrupt-parent = <&gpioi>; + pinctrl-names = "default"; + pinctrl-0 = <&stusb1600_pins_a>; + status = "okay"; + vdd-supply = <&vin>; + + connector { + compatible = "usb-c-connector"; + label = "USB-C"; + power-role = "dual"; + typec-power-opmode = "default"; + + port { + con_usbotg_hs_ep: endpoint { + remote-endpoint = <&usbotg_hs_ep>; + }; + }; + }; + }; + pmic: stpmic@33 { compatible = "st,stpmic1"; reg = <0x33>; @@ -656,6 +680,12 @@ phy-names = "usb2-phy"; usb-role-switch; status = "okay"; + + port { + usbotg_hs_ep: endpoint { + remote-endpoint = <&con_usbotg_hs_ep>; + }; + }; }; &usbphyc { From fc082d2bb2f4860e065ae4d7f50d123bf4861d66 Mon Sep 17 00:00:00 2001 From: Amelie Delaunay Date: Tue, 10 Nov 2020 15:36:41 +0100 Subject: [PATCH 509/799] ARM: dts: stm32: fix mdma1 clients channel priority level on stm32mp151 Update mdma1 clients channel priority level following stm32-mdma bindings. Signed-off-by: Amelie Delaunay Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp151.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/stm32mp151.dtsi b/arch/arm/boot/dts/stm32mp151.dtsi index 6ffcf06dc0e8..2ace7d6ef364 100644 --- a/arch/arm/boot/dts/stm32mp151.dtsi +++ b/arch/arm/boot/dts/stm32mp151.dtsi @@ -1294,7 +1294,7 @@ interrupts = ; clocks = <&rcc HASH1>; resets = <&rcc HASH1_R>; - dmas = <&mdma1 31 0x10 0x1000A02 0x0 0x0>; + dmas = <&mdma1 31 0x2 0x1000A02 0x0 0x0>; dma-names = "in"; dma-maxburst = <2>; status = "disabled"; @@ -1358,8 +1358,8 @@ reg = <0x58003000 0x1000>, <0x70000000 0x10000000>; reg-names = "qspi", "qspi_mm"; interrupts = ; - dmas = <&mdma1 22 0x10 0x100002 0x0 0x0>, - <&mdma1 22 0x10 0x100008 0x0 0x0>; + dmas = <&mdma1 22 0x2 0x100002 0x0 0x0>, + <&mdma1 22 0x2 0x100008 0x0 0x0>; dma-names = "tx", "rx"; clocks = <&rcc QSPI_K>; resets = <&rcc QSPI_R>; From e3b37ca311bb72411f97d269ee4c6a6738a1e9d9 Mon Sep 17 00:00:00 2001 From: Amelie Delaunay Date: Tue, 10 Nov 2020 15:27:36 +0100 Subject: [PATCH 510/799] ARM: dts: stm32: fix dmamux reg property on stm32mp151 Reg property length should cover all DMAMUX_CxCR registers. DMAMUX_CxCR Address offset: 0x000 + 0x04 * x (x = 0 to 15), so latest offset is at 0x3c, so length should be 0x40. Signed-off-by: Amelie Delaunay Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp151.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/stm32mp151.dtsi b/arch/arm/boot/dts/stm32mp151.dtsi index 2ace7d6ef364..7aec02f263ed 100644 --- a/arch/arm/boot/dts/stm32mp151.dtsi +++ b/arch/arm/boot/dts/stm32mp151.dtsi @@ -1001,7 +1001,7 @@ dmamux1: dma-router@48002000 { compatible = "st,stm32h7-dmamux"; - reg = <0x48002000 0x1c>; + reg = <0x48002000 0x40>; #dma-cells = <3>; dma-requests = <128>; dma-masters = <&dma1 &dma2>; From 7e4bc946db78ec0311b486fadc929965fda85808 Mon Sep 17 00:00:00 2001 From: Amelie Delaunay Date: Tue, 10 Nov 2020 15:27:37 +0100 Subject: [PATCH 511/799] ARM: dts: stm32: fix dmamux reg property on stm32h743 Reg property length should cover all DMAMUX_CxCR registers. DMAMUX_CxCR Address offset: 0x000 + 0x04 * x (x = 0 to 15), so latest offset is at 0x3c, so length should be 0x40. Signed-off-by: Amelie Delaunay Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32h743.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/stm32h743.dtsi b/arch/arm/boot/dts/stm32h743.dtsi index 7febe19e780d..b083afd0ebd6 100644 --- a/arch/arm/boot/dts/stm32h743.dtsi +++ b/arch/arm/boot/dts/stm32h743.dtsi @@ -274,7 +274,7 @@ dmamux1: dma-router@40020800 { compatible = "st,stm32h7-dmamux"; - reg = <0x40020800 0x1c>; + reg = <0x40020800 0x40>; #dma-cells = <3>; dma-channels = <16>; dma-requests = <128>; From d27209f04d7f0e388281ba04d3cb97772c0eecff Mon Sep 17 00:00:00 2001 From: Amelie Delaunay Date: Tue, 10 Nov 2020 14:10:59 +0100 Subject: [PATCH 512/799] ARM: dts: stm32: adjust USB OTG gadget fifo sizes in stm32mp151 Defaut use case on stm32mp151 USB OTG is ethernet gadget, using EP1 bulk endpoint (MPS=512 bytes) and EP2 interrupt endpoint (MPS=16 bytes). This patch optimizes USB OTG FIFO sizes accordingly. Signed-off-by: Amelie Delaunay Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp151.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/stm32mp151.dtsi b/arch/arm/boot/dts/stm32mp151.dtsi index 7aec02f263ed..b95c46c82223 100644 --- a/arch/arm/boot/dts/stm32mp151.dtsi +++ b/arch/arm/boot/dts/stm32mp151.dtsi @@ -1070,9 +1070,9 @@ resets = <&rcc USBO_R>; reset-names = "dwc2"; interrupts = ; - g-rx-fifo-size = <256>; + g-rx-fifo-size = <512>; g-np-tx-fifo-size = <32>; - g-tx-fifo-size = <128 128 64 64 64 64 32 32>; + g-tx-fifo-size = <256 16 16 16 16 16 16 16>; dr_mode = "otg"; usb33d-supply = <&usb33>; status = "disabled"; From 4c903a946404dd96c45947c619c42d03020f9097 Mon Sep 17 00:00:00 2001 From: Arnaud Pouliquen Date: Wed, 14 Oct 2020 14:54:41 +0200 Subject: [PATCH 513/799] ARM: dts: stm32: update stm32mp151 for remote proc synchronization support Two backup registers are used to store the Cortex-M4 state and the resource table address. Declare the tamp node and add associated properties in m4_rproc node to allow Linux to attach to a firmware loaded by the first boot stages. Associated driver implementation is available in commit 9276536f455b3 ("remoteproc: stm32: Parse syscon that will manage M4 synchronisation"). Signed-off-by: Arnaud Pouliquen Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp151.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/boot/dts/stm32mp151.dtsi b/arch/arm/boot/dts/stm32mp151.dtsi index b95c46c82223..a333c633a112 100644 --- a/arch/arm/boot/dts/stm32mp151.dtsi +++ b/arch/arm/boot/dts/stm32mp151.dtsi @@ -1573,6 +1573,11 @@ status = "disabled"; }; + tamp: tamp@5c00a000 { + compatible = "st,stm32-tamp", "syscon"; + reg = <0x5c00a000 0x400>; + }; + /* * Break node order to solve dependency probe issue between * pinctrl and exti. @@ -1749,6 +1754,8 @@ st,syscfg-holdboot = <&rcc 0x10C 0x1>; st,syscfg-tz = <&rcc 0x000 0x1>; st,syscfg-pdds = <&pwr_mcu 0x0 0x1>; + st,syscfg-rsc-tbl = <&tamp 0x144 0xFFFFFFFF>; + st,syscfg-m4-state = <&tamp 0x148 0xFFFFFFFF>; status = "disabled"; }; }; From 82765d149583730c943a5d23d0bad3e647364dc1 Mon Sep 17 00:00:00 2001 From: Ahmad Fatoum Date: Wed, 21 Oct 2020 12:28:55 +0200 Subject: [PATCH 514/799] dt-bindings: arm: stm32: add simple-mfd compatible for tamp node The stm32mp1 TAMP (Tamper and backup registers) does tamper detection and features 32 backup registers that, being in the RTC domain, may survive even with Vdd switched off. This makes it suitable for use to communicate a reboot mode from OS to bootloader via the syscon-reboot-mode binding. Add a "simple-mfd" to support probing such a child node. The actual reboot mode node could then be defined in a board.dts or fixed up by the bootloader. Signed-off-by: Ahmad Fatoum Reviewed-by: Rob Herring Signed-off-by: Alexandre Torgue --- .../devicetree/bindings/arm/stm32/st,stm32-syscon.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/stm32/st,stm32-syscon.yaml b/Documentation/devicetree/bindings/arm/stm32/st,stm32-syscon.yaml index 6f1cd0103c74..4684017a42e4 100644 --- a/Documentation/devicetree/bindings/arm/stm32/st,stm32-syscon.yaml +++ b/Documentation/devicetree/bindings/arm/stm32/st,stm32-syscon.yaml @@ -20,6 +20,10 @@ properties: - st,stm32-syscfg - st,stm32-power-config - const: syscon + - items: + - const: st,stm32-tamp + - const: syscon + - const: simple-mfd reg: maxItems: 1 From b19d3a55d4789a657c3c6b247ab5c9d8611a8a86 Mon Sep 17 00:00:00 2001 From: Ahmad Fatoum Date: Wed, 21 Oct 2020 12:28:56 +0200 Subject: [PATCH 515/799] ARM: dts: stm32: support child mfd cells for the stm32mp1 TAMP syscon The stm32mp1 TAMP peripheral has 32 backup registers that survive a warm reset. This makes them suitable for storing a reboot mode, which the vendor's kernel tree is already doing[0]. The actual syscon-reboot-mode child node can be added by a board.dts or fixed up by the bootloader. For the child node to be probed, the compatible needs to include simple-mfd. The binding now specifies this, so have the SoC dtsi adhere to it. [0]: https://github.com/STMicroelectronics/linux/commit/2e9bfc29dd Signed-off-by: Ahmad Fatoum Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp151.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/stm32mp151.dtsi b/arch/arm/boot/dts/stm32mp151.dtsi index a333c633a112..3c75abacb374 100644 --- a/arch/arm/boot/dts/stm32mp151.dtsi +++ b/arch/arm/boot/dts/stm32mp151.dtsi @@ -1574,7 +1574,7 @@ }; tamp: tamp@5c00a000 { - compatible = "st,stm32-tamp", "syscon"; + compatible = "st,stm32-tamp", "syscon", "simple-mfd"; reg = <0x5c00a000 0x400>; }; From 242639c0dc25728b94f5db3072635415d0c4cffa Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 8 Nov 2020 23:14:38 +0100 Subject: [PATCH 516/799] dt-bindings: arm: stm32: Add compatible strings for DH SoMs and boards Document devicetree compatible strings of the DH SoMs and boards. Signed-off-by: Marek Vasut Cc: Alexandre Torgue Cc: Maxime Coquelin Cc: Patrice Chotard Cc: Patrick Delaunay Cc: Rob Herring Cc: devicetree@vger.kernel.org Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org Acked-by: Rob Herring Signed-off-by: Alexandre Torgue --- .../devicetree/bindings/arm/stm32/stm32.yaml | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml index deacb4e686e8..74e0b42f5087 100644 --- a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml +++ b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml @@ -14,6 +14,20 @@ properties: const: "/" compatible: oneOf: + - description: DH STM32MP1 SoM based Boards + items: + - enum: + - arrow,stm32mp157a-avenger96 # Avenger96 + - dh,stm32mp153c-dhcom-drc02 + - dh,stm32mp157c-dhcom-pdk2 + - dh,stm32mp157c-dhcom-picoitx + - enum: + - dh,stm32mp153c-dhcom-som + - dh,stm32mp157a-dhcor-som + - dh,stm32mp157c-dhcom-som + - enum: + - st,stm32mp153 + - st,stm32mp157 - items: - enum: - st,stm32f429i-disco @@ -39,7 +53,6 @@ properties: - const: st,stm32h743 - items: - enum: - - arrow,stm32mp157a-avenger96 # Avenger96 - lxa,stm32mp157c-mc1 - shiratech,stm32mp157a-iot-box # IoT Box - shiratech,stm32mp157a-stinger96 # Stinger96 From ac68793f49de74c4046e760b6370f70c51d4aef9 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 3 Nov 2020 19:11:37 +0100 Subject: [PATCH 517/799] ARM: dts: stm32: Add DHCOM based PicoITX board Add DT for DH PicoITX unit, which is a bare-bones carrier board for the DHCOM. The board has ethernet port, USB, CAN, LEDs and a custom board-to-board expansion connector. Signed-off-by: Marek Vasut Cc: Alexandre Torgue Cc: Maxime Coquelin Cc: Patrice Chotard Cc: Patrick Delaunay Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/Makefile | 1 + .../boot/dts/stm32mp157c-dhcom-picoitx.dts | 35 +++++ .../boot/dts/stm32mp15xx-dhcom-picoitx.dtsi | 143 ++++++++++++++++++ 3 files changed, 179 insertions(+) create mode 100644 arch/arm/boot/dts/stm32mp157c-dhcom-picoitx.dts create mode 100644 arch/arm/boot/dts/stm32mp15xx-dhcom-picoitx.dtsi diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index ce66ffd5a1bb..c236c0f0adf6 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1066,6 +1066,7 @@ dtb-$(CONFIG_ARCH_STM32) += \ stm32mp157a-iot-box.dtb \ stm32mp157a-stinger96.dtb \ stm32mp157c-dhcom-pdk2.dtb \ + stm32mp157c-dhcom-picoitx.dtb \ stm32mp157c-dk2.dtb \ stm32mp157c-ed1.dtb \ stm32mp157c-ev1.dtb \ diff --git a/arch/arm/boot/dts/stm32mp157c-dhcom-picoitx.dts b/arch/arm/boot/dts/stm32mp157c-dhcom-picoitx.dts new file mode 100644 index 000000000000..cfb8f8a0c82d --- /dev/null +++ b/arch/arm/boot/dts/stm32mp157c-dhcom-picoitx.dts @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause +/* + * Copyright (C) 2020 Marek Vasut + * + * DHCOM STM32MP1 variant: + * DHCM-STM32MP157C-C065-R102-F0819-SPI-E-CAN2-SD-RTC-T-DSI-I-01D2 + * DHCOM PCB number: 587-200 or newer + * PicoITX PCB number: 487-600 or newer + */ +/dts-v1/; + +#include "stm32mp157.dtsi" +#include "stm32mp15xc.dtsi" +#include "stm32mp15xx-dhcom-som.dtsi" +#include "stm32mp15xx-dhcom-picoitx.dtsi" + +/ { + model = "DH electronics STM32MP157C DHCOM PicoITX"; + compatible = "dh,stm32mp157c-dhcom-picoitx", "dh,stm32mp157c-dhcom-som", + "st,stm32mp157"; +}; + +&m_can1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&m_can1_pins_a>; + pinctrl-1 = <&m_can1_sleep_pins_a>; + status = "okay"; +}; + +&m_can2 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&m_can2_pins_a>; + pinctrl-1 = <&m_can2_sleep_pins_a>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcom-picoitx.dtsi b/arch/arm/boot/dts/stm32mp15xx-dhcom-picoitx.dtsi new file mode 100644 index 000000000000..356150d28c42 --- /dev/null +++ b/arch/arm/boot/dts/stm32mp15xx-dhcom-picoitx.dtsi @@ -0,0 +1,143 @@ +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause +/* + * Copyright (C) 2020 Marek Vasut + */ + +#include +#include + +/ { + aliases { + serial0 = &uart4; + serial1 = &usart3; + serial2 = &uart8; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + led { + compatible = "gpio-leds"; + + led-0 { + label = "yellow:led"; + gpios = <&gpioi 3 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + }; +}; + +&adc { + status = "disabled"; +}; + +&dac { + status = "disabled"; +}; + +&gpioa { + /* + * NOTE: The USB Port on the PicoITX needs a PWR_EN signal to enable + * port power. This signal should be handled by USB power sequencing + * in order to turn on port power when USB bus is powered up, but so + * far there is no such functionality. + */ + usb-port-power { + gpio-hog; + gpios = <13 GPIO_ACTIVE_LOW>; + output-low; + line-name = "usb-port-power"; + }; +}; + +&gpioc { + gpio-line-names = "", "", "", "", + "", "", "In1", "", + "", "", "", "", + "", "", "", ""; +}; + +&gpiod { + gpio-line-names = "", "", "", "", + "", "", "", "", + "", "", "", "Out1", + "Out2", "", "", ""; +}; + +&gpiog { + gpio-line-names = "In2", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", ""; +}; + +&i2c2 { /* On board-to-board connector (optional) */ + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins_a>; + i2c-scl-rising-time-ns = <185>; + i2c-scl-falling-time-ns = <20>; + status = "okay"; + /* spare dmas for other usage */ + /delete-property/dmas; + /delete-property/dma-names; +}; + +&i2c5 { /* On board-to-board connector */ + pinctrl-names = "default"; + pinctrl-0 = <&i2c5_pins_a>; + i2c-scl-rising-time-ns = <185>; + i2c-scl-falling-time-ns = <20>; + status = "okay"; + /* spare dmas for other usage */ + /delete-property/dmas; + /delete-property/dma-names; +}; + +&usart3 { + pinctrl-names = "default"; + pinctrl-0 = <&usart3_pins_a>; + status = "okay"; +}; + +&uart8 { + pinctrl-names = "default"; + pinctrl-0 = <&uart8_pins_a &uart8_rtscts_pins_a>; + status = "okay"; +}; + +&usbh_ehci { + phys = <&usbphyc_port0>; + status = "okay"; +}; + +&usbh_ohci { + phys = <&usbphyc_port0>; + status = "okay"; +}; + +&usbotg_hs { + dr_mode = "otg"; + pinctrl-0 = <&usbotg_hs_pins_a>; + pinctrl-names = "default"; + phy-names = "usb2-phy"; + phys = <&usbphyc_port1 0>; + vbus-supply = <&vbus_otg>; + status = "okay"; +}; + +&usbphyc { + status = "okay"; +}; + +&usbphyc_port0 { + phy-supply = <&vdd_usb>; + vdda1v1-supply = <®11>; + vdda1v8-supply = <®18>; +}; + +&usbphyc_port1 { + phy-supply = <&vdd_usb>; + vdda1v1-supply = <®11>; + vdda1v8-supply = <®18>; +}; From a24bde12f949c7a694094126a0979b3807274cbb Mon Sep 17 00:00:00 2001 From: Ahmad Fatoum Date: Tue, 10 Nov 2020 11:25:49 +0100 Subject: [PATCH 518/799] dt-bindings: vendor-prefixes: document Octavo Systems oct prefix Octavo Systems is an American company specializing in design and manufacturing of System-in-Package devices. The prefix is already in use for the Octavo Systems OSD3358-SM-RED device tree, but was so far undocumented. Fix this. Signed-off-by: Ahmad Fatoum Acked-by: Rob Herring Cc: Neeraj Dantu Signed-off-by: Alexandre Torgue --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index 2735be1a8470..fdbf463be9bd 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -760,6 +760,8 @@ patternProperties: description: NXP Semiconductors "^oceanic,.*": description: Oceanic Systems (UK) Ltd. + "^oct,.*": + description: Octavo Systems LLC "^okaya,.*": description: Okaya Electric America, Inc. "^oki,.*": From acf6f3316376ea25d74bd8cf6f1f51ecdd67cee9 Mon Sep 17 00:00:00 2001 From: Ahmad Fatoum Date: Tue, 10 Nov 2020 11:25:50 +0100 Subject: [PATCH 519/799] dt-bindings: arm: stm32: add extra SiP compatible for lxa,stm32mp157c-mc1 The Linux Automation MC-1 is built around an OSD32MP15x SiP with CPU, RAM, PMIC, Oscillator and EEPROM. Adjust the binding, so the SiP compatible is contained as well. This allows boot firmware to match against it to apply fixups if necessary. Signed-off-by: Ahmad Fatoum Acked-by: Rob Herring Signed-off-by: Alexandre Torgue --- Documentation/devicetree/bindings/arm/stm32/stm32.yaml | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml index 74e0b42f5087..623944b3cb56 100644 --- a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml +++ b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml @@ -53,7 +53,6 @@ properties: - const: st,stm32h743 - items: - enum: - - lxa,stm32mp157c-mc1 - shiratech,stm32mp157a-iot-box # IoT Box - shiratech,stm32mp157a-stinger96 # Stinger96 - st,stm32mp157c-ed1 @@ -65,6 +64,13 @@ properties: - const: st,stm32mp157c-ev1 - const: st,stm32mp157c-ed1 - const: st,stm32mp157 + - description: Octavo OSD32MP15x System-in-Package based boards + items: + - enum: + - lxa,stm32mp157c-mc1 # Linux Automation MC-1 + - const: oct,stm32mp15xx-osd32 + - enum: + - st,stm32mp157 - description: Odyssey STM32MP1 SoM based Boards items: - enum: From 6660e2445523a57410de008a9b137d2c0a66e94a Mon Sep 17 00:00:00 2001 From: Ahmad Fatoum Date: Tue, 10 Nov 2020 11:25:51 +0100 Subject: [PATCH 520/799] ARM: dts: stm32: lxa-mc1: add OSD32MP15x to list of compatibles Earlier commit modified the binding, so the SiP is to be specified as well. Adjust the device tree accordingly. Signed-off-by: Ahmad Fatoum Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp157c-lxa-mc1.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/stm32mp157c-lxa-mc1.dts b/arch/arm/boot/dts/stm32mp157c-lxa-mc1.dts index 1e5333fd437f..cda8e871f999 100644 --- a/arch/arm/boot/dts/stm32mp157c-lxa-mc1.dts +++ b/arch/arm/boot/dts/stm32mp157c-lxa-mc1.dts @@ -15,7 +15,7 @@ / { model = "Linux Automation MC-1 board"; - compatible = "lxa,stm32mp157c-mc1", "st,stm32mp157"; + compatible = "lxa,stm32mp157c-mc1", "oct,stm32mp15xx-osd32", "st,stm32mp157"; aliases { ethernet0 = ðernet0; From 46957c06d35bb0caf07cc032600f6a3391eb47d1 Mon Sep 17 00:00:00 2001 From: Fabrice Gasnier Date: Fri, 16 Oct 2020 10:00:29 +0200 Subject: [PATCH 521/799] ARM: multi_v7_defconfig: enable counter subsystem and stm32 counter drivers This enables the counter subsystem and drivers for the stm32 timer and LP timer. Signed-off-by: Fabrice Gasnier Signed-off-by: Alexandre Torgue --- arch/arm/configs/multi_v7_defconfig | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig index e731cdf7c88c..54b54107eb29 100644 --- a/arch/arm/configs/multi_v7_defconfig +++ b/arch/arm/configs/multi_v7_defconfig @@ -1095,6 +1095,9 @@ CONFIG_FSI_MASTER_ASPEED=m CONFIG_FSI_SCOM=m CONFIG_FSI_SBEFIFO=m CONFIG_FSI_OCC=m +CONFIG_COUNTER=m +CONFIG_STM32_TIMER_CNT=m +CONFIG_STM32_LPTIMER_CNT=m CONFIG_EXT4_FS=y CONFIG_AUTOFS4_FS=y CONFIG_MSDOS_FS=y From 8e4eeb83a692a4d3be60854e9cf7a045e440db78 Mon Sep 17 00:00:00 2001 From: Lionel Debieve Date: Thu, 5 Nov 2020 10:47:30 +0100 Subject: [PATCH 522/799] ARM: multi_v7_defconfig: add STM32 crypto support Enable crypto controllers enabling following flags as module: CONFIG_CRYPTO_DEV_STM32_CRC CONFIG_CRYPTO_DEV_STM32_HASH CONFIG_CRYPTO_DEV_STM32_CRYP Signed-off-by: Lionel Debieve Signed-off-by: Alexandre Torgue --- arch/arm/configs/multi_v7_defconfig | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig index 54b54107eb29..17ff69674c6e 100644 --- a/arch/arm/configs/multi_v7_defconfig +++ b/arch/arm/configs/multi_v7_defconfig @@ -1135,6 +1135,9 @@ CONFIG_CRYPTO_DEV_ATMEL_AES=m CONFIG_CRYPTO_DEV_ATMEL_TDES=m CONFIG_CRYPTO_DEV_ATMEL_SHA=m CONFIG_CRYPTO_DEV_ROCKCHIP=m +CONFIG_CRYPTO_DEV_STM32_CRC=m +CONFIG_CRYPTO_DEV_STM32_HASH=m +CONFIG_CRYPTO_DEV_STM32_CRYP=m CONFIG_CMA_SIZE_MBYTES=64 CONFIG_PRINTK_TIME=y CONFIG_MAGIC_SYSRQ=y From 89391783174e12d621d82bc41b4b017363bf2827 Mon Sep 17 00:00:00 2001 From: Amelie Delaunay Date: Fri, 6 Nov 2020 17:58:05 +0100 Subject: [PATCH 523/799] ARM: multi_v7_defconfig: enable STUSB160X Type-C port controller support Enable support for the STMicroelectronics STUSB160X USB Type-C port controller driver by turning on CONFIG_TYPEC and CONFIG_TYPEC_STUSB160X as modules. Signed-off-by: Amelie Delaunay Signed-off-by: Alexandre Torgue --- arch/arm/configs/multi_v7_defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig index 17ff69674c6e..1fff2591e434 100644 --- a/arch/arm/configs/multi_v7_defconfig +++ b/arch/arm/configs/multi_v7_defconfig @@ -828,6 +828,8 @@ CONFIG_USB_CONFIGFS_F_HID=y CONFIG_USB_CONFIGFS_F_UVC=y CONFIG_USB_CONFIGFS_F_PRINTER=y CONFIG_USB_ETH=m +CONFIG_TYPEC=m +CONFIG_TYPEC_STUSB160X=m CONFIG_MMC=y CONFIG_MMC_BLOCK_MINORS=16 CONFIG_MMC_ARMMMCI=y From 1c6b157ba6bdfd309ce53819116601da230a1431 Mon Sep 17 00:00:00 2001 From: Olivier Moysan Date: Fri, 20 Nov 2020 10:15:05 +0100 Subject: [PATCH 524/799] ARM: multi_v7_defconfig: enable STM32 spdifrx support Add STM32 SPDIFRX support by enabling CONFIG_SND_SOC_STM32_SPDIFRX as module. Signed-off-by: Olivier Moysan Reviewed-by: Krzysztof Kozlowski Signed-off-by: Alexandre Torgue --- arch/arm/configs/multi_v7_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig index 1fff2591e434..b30a3bc6762b 100644 --- a/arch/arm/configs/multi_v7_defconfig +++ b/arch/arm/configs/multi_v7_defconfig @@ -742,6 +742,7 @@ CONFIG_SND_SOC_RCAR=m CONFIG_SND_SOC_STI=m CONFIG_SND_SOC_STM32_SAI=m CONFIG_SND_SOC_STM32_I2S=m +CONFIG_SND_SOC_STM32_SPDIFRX=m CONFIG_SND_SUN4I_CODEC=m CONFIG_SND_SOC_TEGRA=m CONFIG_SND_SOC_TEGRA20_I2S=m From 01d13862543d3a017270ad84170579848472589f Mon Sep 17 00:00:00 2001 From: Olivier Moysan Date: Fri, 20 Nov 2020 10:15:06 +0100 Subject: [PATCH 525/799] ARM: multi_v7_defconfig: enable STM32 dfsdm audio support Add STM32 DFSDM audio support by enabling CONFIG_SND_SOC_STM32_DFSDM as module. Signed-off-by: Olivier Moysan Reviewed-by: Krzysztof Kozlowski Signed-off-by: Alexandre Torgue --- arch/arm/configs/multi_v7_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig index b30a3bc6762b..083d5f4450f4 100644 --- a/arch/arm/configs/multi_v7_defconfig +++ b/arch/arm/configs/multi_v7_defconfig @@ -743,6 +743,7 @@ CONFIG_SND_SOC_STI=m CONFIG_SND_SOC_STM32_SAI=m CONFIG_SND_SOC_STM32_I2S=m CONFIG_SND_SOC_STM32_SPDIFRX=m +CONFIG_SND_SOC_STM32_DFSDM=m CONFIG_SND_SUN4I_CODEC=m CONFIG_SND_SOC_TEGRA=m CONFIG_SND_SOC_TEGRA20_I2S=m From 6450da3dab73e25e38b7efd57b0699d3d01bde26 Mon Sep 17 00:00:00 2001 From: JC Kuo Date: Thu, 19 Nov 2020 16:54:03 +0800 Subject: [PATCH 526/799] arm64: tegra: Add XUSB pad controller interrupt This commit adds "interrupts" property to Tegra210/Tegra186/Tegra194 XUSB PADCTL node. XUSB PADCTL interrupt will be raised when USB wake event happens. This is required for supporting XUSB host controller ELPG. Signed-off-by: JC Kuo Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra186.dtsi | 1 + arch/arm64/boot/dts/nvidia/tegra194.dtsi | 1 + arch/arm64/boot/dts/nvidia/tegra210.dtsi | 1 + 3 files changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi index 98544d16d01b..53ab8e5487e0 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi @@ -685,6 +685,7 @@ reg = <0x0 0x03520000 0x0 0x1000>, <0x0 0x03540000 0x0 0x1000>; reg-names = "padctl", "ao"; + interrupts = ; resets = <&bpmp TEGRA186_RESET_XUSB_PADCTL>; reset-names = "padctl"; diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index 6946fb210e48..c84d1f040111 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -801,6 +801,7 @@ reg = <0x03520000 0x1000>, <0x03540000 0x1000>; reg-names = "padctl", "ao"; + interrupts = ; resets = <&bpmp TEGRA194_RESET_XUSB_PADCTL>; reset-names = "padctl"; diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi index 6d2a9d259319..9a7c511913d8 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi @@ -1040,6 +1040,7 @@ padctl: padctl@7009f000 { compatible = "nvidia,tegra210-xusb-padctl"; reg = <0x0 0x7009f000 0x0 0x1000>; + interrupts = ; resets = <&tegra_car 142>; reset-names = "padctl"; From c84ebdfd26645731cc1d9255df94b66de489093e Mon Sep 17 00:00:00 2001 From: Sowjanya Komatineni Date: Mon, 23 Nov 2020 12:17:21 -0800 Subject: [PATCH 527/799] arm64: tegra: Change order of SATA resets for Tegra132 and Tegra210 Tegra AHCI dt-binding doc is converted from text based to yaml based. dtbs_check valdiation strictly follows reset-names order specified in yaml dt-binding. Tegra124 thru Tegra210 has 3 resets sata, sata-oob and sata-cold. Tegra186 has 2 resets sata and sata-cold. This patch changes order of SATA resets to maintain proper resets order for commonly available resets across Tegra124 thru Tegra186 for dtbs_check to pass. Signed-off-by: Sowjanya Komatineni Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra132.dtsi | 6 +++--- arch/arm64/boot/dts/nvidia/tegra210.dtsi | 6 +++--- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra132.dtsi b/arch/arm64/boot/dts/nvidia/tegra132.dtsi index 0ce958a4f879..9928a87f593a 100644 --- a/arch/arm64/boot/dts/nvidia/tegra132.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra132.dtsi @@ -629,9 +629,9 @@ <&tegra_car TEGRA124_CLK_PLL_E>; clock-names = "sata", "sata-oob", "cml1", "pll_e"; resets = <&tegra_car 124>, - <&tegra_car 123>, - <&tegra_car 129>; - reset-names = "sata", "sata-oob", "sata-cold"; + <&tegra_car 129>, + <&tegra_car 123>; + reset-names = "sata", "sata-cold", "sata-oob"; status = "disabled"; }; diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi index 9a7c511913d8..4fbf8c15b0a1 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi @@ -979,9 +979,9 @@ <&tegra_car TEGRA210_CLK_SATA_OOB>; clock-names = "sata", "sata-oob"; resets = <&tegra_car 124>, - <&tegra_car 123>, - <&tegra_car 129>; - reset-names = "sata", "sata-oob", "sata-cold"; + <&tegra_car 129>, + <&tegra_car 123>; + reset-names = "sata", "sata-cold", "sata-oob"; status = "disabled"; }; From e061fbdf7d78813a352a6c179fca837e1842883b Mon Sep 17 00:00:00 2001 From: Sowjanya Komatineni Date: Mon, 23 Nov 2020 12:17:24 -0800 Subject: [PATCH 528/799] arm64: tegra: Enable AHCI on Jetson TX2 This patch enables AHCI on Jetson TX2. Signed-off-by: Sowjanya Komatineni Signed-off-by: Thierry Reding --- .../boot/dts/nvidia/tegra186-p2771-0000.dts | 4 +++ arch/arm64/boot/dts/nvidia/tegra186.dtsi | 28 +++++++++++++++++++ 2 files changed, 32 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts b/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts index c28d51cc5797..6fd2e0542c27 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts @@ -285,6 +285,10 @@ }; }; + sata@3507000 { + status = "okay"; + }; + gpio-keys { compatible = "gpio-keys"; diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi index 53ab8e5487e0..58c51965df47 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi @@ -1504,6 +1504,34 @@ }; }; + sata@3507000 { + compatible = "nvidia,tegra186-ahci"; + reg = <0x0 0x03507000 0x0 0x00002000>, /* AHCI */ + <0x0 0x03500000 0x0 0x00007000>, /* SATA */ + <0x0 0x03A90000 0x0 0x00010000>; /* SATA AUX */ + interrupts = ; + + power-domains = <&bpmp TEGRA186_POWER_DOMAIN_SAX>; + interconnects = <&mc TEGRA186_MEMORY_CLIENT_SATAR &emc>, + <&mc TEGRA186_MEMORY_CLIENT_SATAW &emc>; + interconnect-names = "dma-mem", "write"; + iommus = <&smmu TEGRA186_SID_SATA>; + + clocks = <&bpmp TEGRA186_CLK_SATA>, + <&bpmp TEGRA186_CLK_SATA_OOB>; + clock-names = "sata", "sata-oob"; + assigned-clocks = <&bpmp TEGRA186_CLK_SATA>, + <&bpmp TEGRA186_CLK_SATA_OOB>; + assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLP_OUT0>, + <&bpmp TEGRA186_CLK_PLLP>; + assigned-clock-rates = <102000000>, + <204000000>; + resets = <&bpmp TEGRA186_RESET_SATA>, + <&bpmp TEGRA186_RESET_SATACOLD>; + reset-names = "sata", "sata-cold"; + status = "disabled"; + }; + bpmp: bpmp { compatible = "nvidia,tegra186-bpmp"; interconnects = <&mc TEGRA186_MEMORY_CLIENT_BPMPR &emc>, From 48f6e195039486bc303118948f49a9873acc888f Mon Sep 17 00:00:00 2001 From: Sameer Pujar Date: Wed, 18 Nov 2020 13:36:20 +0530 Subject: [PATCH 529/799] arm64: tegra: Fix Tegra194 HDA {clock,reset}-names ordering As per the HDA binding doc reorder {clock,reset}-names entries for Tegra194. This also serves as a preparation for converting existing binding doc to json-schema. Signed-off-by: Sameer Pujar Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra194.dtsi | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index c84d1f040111..25f36d6118f8 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -782,13 +782,13 @@ reg = <0x3510000 0x10000>; interrupts = ; clocks = <&bpmp TEGRA194_CLK_HDA>, - <&bpmp TEGRA194_CLK_HDA2CODEC_2X>, - <&bpmp TEGRA194_CLK_HDA2HDMICODEC>; - clock-names = "hda", "hda2codec_2x", "hda2hdmi"; + <&bpmp TEGRA194_CLK_HDA2HDMICODEC>, + <&bpmp TEGRA194_CLK_HDA2CODEC_2X>; + clock-names = "hda", "hda2hdmi", "hda2codec_2x"; resets = <&bpmp TEGRA194_RESET_HDA>, - <&bpmp TEGRA194_RESET_HDA2CODEC_2X>, - <&bpmp TEGRA194_RESET_HDA2HDMICODEC>; - reset-names = "hda", "hda2codec_2x", "hda2hdmi"; + <&bpmp TEGRA194_RESET_HDA2HDMICODEC>, + <&bpmp TEGRA194_RESET_HDA2CODEC_2X>; + reset-names = "hda", "hda2hdmi", "hda2codec_2x"; power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; interconnects = <&mc TEGRA194_MEMORY_CLIENT_HDAR &emc>, <&mc TEGRA194_MEMORY_CLIENT_HDAW &emc>; From da8d46992e672ec7300b5b6857d0a4eebf0727ac Mon Sep 17 00:00:00 2001 From: Iskren Chernev Date: Thu, 26 Nov 2020 16:11:43 +0200 Subject: [PATCH 530/799] ARM: dts: qcom: msm8974-klte: Add fuel gauge The Samsung Galaxy S5 uses a maxim17048 fuelgauge. The maxim,rcomp value is taken from downstream kernel. Model data and temperature-based compensation are not yet supported in the mainline driver, but the readings seem fine nevertheless. Signed-off-by: Iskren Chernev Link: https://lore.kernel.org/r/20201126141144.1763779-1-iskren.chernev@gmail.com Signed-off-by: Bjorn Andersson --- .../boot/dts/qcom-msm8974-samsung-klte.dts | 39 +++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/arch/arm/boot/dts/qcom-msm8974-samsung-klte.dts b/arch/arm/boot/dts/qcom-msm8974-samsung-klte.dts index b0899107f3ce..97352de91314 100644 --- a/arch/arm/boot/dts/qcom-msm8974-samsung-klte.dts +++ b/arch/arm/boot/dts/qcom-msm8974-samsung-klte.dts @@ -406,6 +406,16 @@ }; }; + i2c12_pins: i2c12 { + mux { + pins = "gpio87", "gpio88"; + function = "blsp_i2c12"; + + drive-strength = <2>; + bias-disable; + }; + }; + i2c_touchkey_pins: i2c-touchkey { mux { pins = "gpio95", "gpio96"; @@ -666,6 +676,27 @@ }; }; }; + + i2c@f9968000 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&i2c12_pins>; + + fuelgauge@36 { + compatible = "maxim,max17048"; + reg = <0x36>; + + maxim,double-soc; + maxim,rcomp = /bits/ 8 <0x56>; + + interrupt-parent = <&pma8084_gpios>; + interrupts = <21 IRQ_TYPE_EDGE_FALLING>; + + pinctrl-names = "default"; + pinctrl-0 = <&fuelgauge_pin>; + }; + }; }; &spmi_bus { @@ -703,6 +734,14 @@ power-source = ; qcom,drive-strength = ; }; + + fuelgauge_pin: fuelgauge-int-pin { + pins = "gpio21"; + function = "normal"; + bias-disable; + input-enable; + power-source = ; + }; }; }; }; From 45dfa741df8607ee4a45455c194ce654badb2478 Mon Sep 17 00:00:00 2001 From: Iskren Chernev Date: Thu, 26 Nov 2020 16:11:44 +0200 Subject: [PATCH 531/799] ARM: dts: qcom: msm8974-lge-nexus5: Add fuel gauge MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The LG Nexus 5 uses a maxim17048 fuelgauge. The maxim,rcomp value is taken from downstream dt. Temperature-based compensation is not yet supported in the mainline driver, but the readings seem fine nevertheless. Signed-off-by: Iskren Chernev Tested-by: Nícolas F. R. A. Prado Link: https://lore.kernel.org/r/20201126141144.1763779-2-iskren.chernev@gmail.com Signed-off-by: Bjorn Andersson --- .../qcom-msm8974-lge-nexus5-hammerhead.dts | 25 +++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts b/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts index 32b474bfeec3..e769f638f205 100644 --- a/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts +++ b/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts @@ -566,6 +566,22 @@ usb_otg_vbus: usb-otg-vbus { }; }; + + fuelgauge: max17048@36 { + compatible = "maxim,max17048"; + reg = <0x36>; + + maxim,double-soc; + maxim,rcomp = /bits/ 8 <0x4d>; + + interrupt-parent = <&msmgpio>; + interrupts = <9 IRQ_TYPE_EDGE_FALLING>; + + pinctrl-names = "default"; + pinctrl-0 = <&fuelgauge_pin>; + + maxim,alert-low-soc-level = <2>; + }; }; i2c@f9924000 { @@ -706,6 +722,15 @@ power-source = ; }; + fuelgauge_pin: fuelgauge-int { + pins = "gpio9"; + function = "normal"; + + bias-disable; + input-enable; + power-source = ; + }; + wlan_sleep_clk_pin: wl-sleep-clk { pins = "gpio16"; function = "func2"; From 24244cefeddef68da2030dabdcd8079f31c5be25 Mon Sep 17 00:00:00 2001 From: Sai Prakash Ranjan Date: Thu, 26 Nov 2020 10:54:22 +0530 Subject: [PATCH 532/799] arm64: dts: qcom: sm8150: Add Coresight support Add coresight components found on Qualcomm Technologies, Inc. SM8150 SoC. Signed-off-by: Sai Prakash Ranjan Reviewed-by: Mathieu Poirier Link: https://lore.kernel.org/r/20201126052422.24869-1-saiprakash.ranjan@codeaurora.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8150.dtsi | 591 +++++++++++++++++++++++++++ 1 file changed, 591 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi index 8dac11c6012e..5270bda7418f 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -798,6 +798,597 @@ }; }; + stm@6002000 { + compatible = "arm,coresight-stm", "arm,primecell"; + reg = <0 0x06002000 0 0x1000>, + <0 0x16280000 0 0x180000>; + reg-names = "stm-base", "stm-stimulus-base"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + stm_out: endpoint { + remote-endpoint = <&funnel0_in7>; + }; + }; + }; + }; + + funnel@6041000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0 0x06041000 0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + funnel0_out: endpoint { + remote-endpoint = <&merge_funnel_in0>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@7 { + reg = <7>; + funnel0_in7: endpoint { + remote-endpoint = <&stm_out>; + }; + }; + }; + }; + + funnel@6042000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0 0x06042000 0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + funnel1_out: endpoint { + remote-endpoint = <&merge_funnel_in1>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@4 { + reg = <4>; + funnel1_in4: endpoint { + remote-endpoint = <&swao_replicator_out>; + }; + }; + }; + }; + + funnel@6043000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0 0x06043000 0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + funnel2_out: endpoint { + remote-endpoint = <&merge_funnel_in2>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@2 { + reg = <2>; + funnel2_in2: endpoint { + remote-endpoint = <&apss_merge_funnel_out>; + }; + }; + }; + }; + + funnel@6045000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0 0x06045000 0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + merge_funnel_out: endpoint { + remote-endpoint = <&etf_in>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + merge_funnel_in0: endpoint { + remote-endpoint = <&funnel0_out>; + }; + }; + + port@1 { + reg = <1>; + merge_funnel_in1: endpoint { + remote-endpoint = <&funnel1_out>; + }; + }; + + port@2 { + reg = <2>; + merge_funnel_in2: endpoint { + remote-endpoint = <&funnel2_out>; + }; + }; + }; + }; + + replicator@6046000 { + compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; + reg = <0 0x06046000 0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + replicator_out0: endpoint { + remote-endpoint = <&etr_in>; + }; + }; + + port@1 { + reg = <1>; + replicator_out1: endpoint { + remote-endpoint = <&replicator1_in>; + }; + }; + }; + + in-ports { + port { + replicator_in0: endpoint { + remote-endpoint = <&etf_out>; + }; + }; + }; + }; + + etf@6047000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0 0x06047000 0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + etf_out: endpoint { + remote-endpoint = <&replicator_in0>; + }; + }; + }; + + in-ports { + port { + etf_in: endpoint { + remote-endpoint = <&merge_funnel_out>; + }; + }; + }; + }; + + etr@6048000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0 0x06048000 0 0x1000>; + iommus = <&apps_smmu 0x05e0 0x0>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + arm,scatter-gather; + + in-ports { + port { + etr_in: endpoint { + remote-endpoint = <&replicator_out0>; + }; + }; + }; + }; + + replicator@604a000 { + compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; + reg = <0 0x0604a000 0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + replicator1_out: endpoint { + remote-endpoint = <&swao_funnel_in>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + replicator1_in: endpoint { + remote-endpoint = <&replicator_out1>; + }; + }; + }; + }; + + funnel@6b08000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0 0x06b08000 0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + swao_funnel_out: endpoint { + remote-endpoint = <&swao_etf_in>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@6 { + reg = <6>; + swao_funnel_in: endpoint { + remote-endpoint = <&replicator1_out>; + }; + }; + }; + }; + + etf@6b09000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0 0x06b09000 0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + swao_etf_out: endpoint { + remote-endpoint = <&swao_replicator_in>; + }; + }; + }; + + in-ports { + port { + swao_etf_in: endpoint { + remote-endpoint = <&swao_funnel_out>; + }; + }; + }; + }; + + replicator@6b0a000 { + compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; + reg = <0 0x06b0a000 0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + qcom,replicator-loses-context; + + out-ports { + port { + swao_replicator_out: endpoint { + remote-endpoint = <&funnel1_in4>; + }; + }; + }; + + in-ports { + port { + swao_replicator_in: endpoint { + remote-endpoint = <&swao_etf_out>; + }; + }; + }; + }; + + etm@7040000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0 0x07040000 0 0x1000>; + + cpu = <&CPU0>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + arm,coresight-loses-context-with-cpu; + qcom,skip-power-up; + + out-ports { + port { + etm0_out: endpoint { + remote-endpoint = <&apss_funnel_in0>; + }; + }; + }; + }; + + etm@7140000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0 0x07140000 0 0x1000>; + + cpu = <&CPU1>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + arm,coresight-loses-context-with-cpu; + qcom,skip-power-up; + + out-ports { + port { + etm1_out: endpoint { + remote-endpoint = <&apss_funnel_in1>; + }; + }; + }; + }; + + etm@7240000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0 0x07240000 0 0x1000>; + + cpu = <&CPU2>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + arm,coresight-loses-context-with-cpu; + qcom,skip-power-up; + + out-ports { + port { + etm2_out: endpoint { + remote-endpoint = <&apss_funnel_in2>; + }; + }; + }; + }; + + etm@7340000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0 0x07340000 0 0x1000>; + + cpu = <&CPU3>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + arm,coresight-loses-context-with-cpu; + qcom,skip-power-up; + + out-ports { + port { + etm3_out: endpoint { + remote-endpoint = <&apss_funnel_in3>; + }; + }; + }; + }; + + etm@7440000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0 0x07440000 0 0x1000>; + + cpu = <&CPU4>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + arm,coresight-loses-context-with-cpu; + qcom,skip-power-up; + + out-ports { + port { + etm4_out: endpoint { + remote-endpoint = <&apss_funnel_in4>; + }; + }; + }; + }; + + etm@7540000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0 0x07540000 0 0x1000>; + + cpu = <&CPU5>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + arm,coresight-loses-context-with-cpu; + qcom,skip-power-up; + + out-ports { + port { + etm5_out: endpoint { + remote-endpoint = <&apss_funnel_in5>; + }; + }; + }; + }; + + etm@7640000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0 0x07640000 0 0x1000>; + + cpu = <&CPU6>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + arm,coresight-loses-context-with-cpu; + qcom,skip-power-up; + + out-ports { + port { + etm6_out: endpoint { + remote-endpoint = <&apss_funnel_in6>; + }; + }; + }; + }; + + etm@7740000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0 0x07740000 0 0x1000>; + + cpu = <&CPU7>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + arm,coresight-loses-context-with-cpu; + qcom,skip-power-up; + + out-ports { + port { + etm7_out: endpoint { + remote-endpoint = <&apss_funnel_in7>; + }; + }; + }; + }; + + funnel@7800000 { /* APSS Funnel */ + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0 0x07800000 0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + apss_funnel_out: endpoint { + remote-endpoint = <&apss_merge_funnel_in>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + apss_funnel_in0: endpoint { + remote-endpoint = <&etm0_out>; + }; + }; + + port@1 { + reg = <1>; + apss_funnel_in1: endpoint { + remote-endpoint = <&etm1_out>; + }; + }; + + port@2 { + reg = <2>; + apss_funnel_in2: endpoint { + remote-endpoint = <&etm2_out>; + }; + }; + + port@3 { + reg = <3>; + apss_funnel_in3: endpoint { + remote-endpoint = <&etm3_out>; + }; + }; + + port@4 { + reg = <4>; + apss_funnel_in4: endpoint { + remote-endpoint = <&etm4_out>; + }; + }; + + port@5 { + reg = <5>; + apss_funnel_in5: endpoint { + remote-endpoint = <&etm5_out>; + }; + }; + + port@6 { + reg = <6>; + apss_funnel_in6: endpoint { + remote-endpoint = <&etm6_out>; + }; + }; + + port@7 { + reg = <7>; + apss_funnel_in7: endpoint { + remote-endpoint = <&etm7_out>; + }; + }; + }; + }; + + funnel@7810000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0 0x07810000 0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + apss_merge_funnel_out: endpoint { + remote-endpoint = <&funnel2_in2>; + }; + }; + }; + + in-ports { + port { + apss_merge_funnel_in: endpoint { + remote-endpoint = <&apss_funnel_out>; + }; + }; + }; + }; + remoteproc_cdsp: remoteproc@8300000 { compatible = "qcom,sm8150-cdsp-pas"; reg = <0x0 0x08300000 0x0 0x4040>; From 8f34831d3659d38f480fddccb76d84c6c3e0ac0b Mon Sep 17 00:00:00 2001 From: Alex Elder Date: Wed, 25 Nov 2020 19:54:55 -0600 Subject: [PATCH 533/799] arm64: dts: qcom: sc7180: limit IPA iommu streams Recently we learned that Android and Windows firmware don't seem to like using 3 as an iommu mask value for IPA. A simple fix was to specify exactly the streams needed explicitly, rather than implying a range with the mask. Make the same change for the SC7180 platform. See also: https://lore.kernel.org/linux-arm-msm/20201123052305.157686-1-bjorn.andersson@linaro.org/ Fixes: d82fade846aa8 ("arm64: dts: qcom: sc7180: add IPA information") Reviewed-by: Bjorn Andersson Signed-off-by: Alex Elder Link: https://lore.kernel.org/r/20201126015457.6557-2-elder@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc7180.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index 98210fdcbe25..d24ebc64c8b8 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -1401,7 +1401,8 @@ ipa: ipa@1e40000 { compatible = "qcom,sc7180-ipa"; - iommus = <&apps_smmu 0x440 0x3>; + iommus = <&apps_smmu 0x440 0x0>, + <&apps_smmu 0x442 0x0>; reg = <0 0x1e40000 0 0x7000>, <0 0x1e47000 0 0x2000>, <0 0x1e04000 0 0x2c000>; From cfee3ea05cf2c28e24801811b0109689b3303caa Mon Sep 17 00:00:00 2001 From: Alex Elder Date: Wed, 25 Nov 2020 19:54:56 -0600 Subject: [PATCH 534/799] arm64: dts: qcom: sc7180: use GIC_SPI for IPA interrupts Use GIC_SPI rather than 0 in the specifiers for the two ARM GIC interrupts used by IPA. Signed-off-by: Alex Elder Link: https://lore.kernel.org/r/20201126015457.6557-3-elder@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc7180.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index d24ebc64c8b8..c7c701e32b9a 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -1410,8 +1410,8 @@ "ipa-shared", "gsi"; - interrupts-extended = <&intc 0 311 IRQ_TYPE_EDGE_RISING>, - <&intc 0 432 IRQ_TYPE_LEVEL_HIGH>, + interrupts-extended = <&intc GIC_SPI 311 IRQ_TYPE_EDGE_RISING>, + <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; interrupt-names = "ipa", From 0fc0f4b6aded9ac5316e1c0d49c3813586415e90 Mon Sep 17 00:00:00 2001 From: Alex Elder Date: Wed, 25 Nov 2020 19:54:57 -0600 Subject: [PATCH 535/799] arm64: dts: qcom: sdm845: use GIC_SPI for IPA interrupts Use GIC_SPI rather than 0 in the specifiers for the two ARM GIC interrupts used by IPA. Signed-off-by: Alex Elder Link: https://lore.kernel.org/r/20201126015457.6557-4-elder@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 957ee80704e7..256a698745ac 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -2152,8 +2152,8 @@ "ipa-shared", "gsi"; - interrupts-extended = <&intc 0 311 IRQ_TYPE_EDGE_RISING>, - <&intc 0 432 IRQ_TYPE_LEVEL_HIGH>, + interrupts-extended = <&intc GIC_SPI 311 IRQ_TYPE_EDGE_RISING>, + <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; interrupt-names = "ipa", From 825c7f4aa2866b77c0238855e2f58d56d2f13eae Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Wed, 4 Nov 2020 19:48:53 +0300 Subject: [PATCH 536/799] dt-bindings: memory: tegra20: Add memory client IDs Each memory client has unique hardware ID, add these IDs. Acked-by: Rob Herring Signed-off-by: Dmitry Osipenko Acked-by: Krzysztof Kozlowski Signed-off-by: Thierry Reding --- include/dt-bindings/memory/tegra20-mc.h | 53 +++++++++++++++++++++++++ 1 file changed, 53 insertions(+) diff --git a/include/dt-bindings/memory/tegra20-mc.h b/include/dt-bindings/memory/tegra20-mc.h index 35e131eee198..6f8829508ad0 100644 --- a/include/dt-bindings/memory/tegra20-mc.h +++ b/include/dt-bindings/memory/tegra20-mc.h @@ -18,4 +18,57 @@ #define TEGRA20_MC_RESET_VDE 13 #define TEGRA20_MC_RESET_VI 14 +#define TEGRA20_MC_DISPLAY0A 0 +#define TEGRA20_MC_DISPLAY0AB 1 +#define TEGRA20_MC_DISPLAY0B 2 +#define TEGRA20_MC_DISPLAY0BB 3 +#define TEGRA20_MC_DISPLAY0C 4 +#define TEGRA20_MC_DISPLAY0CB 5 +#define TEGRA20_MC_DISPLAY1B 6 +#define TEGRA20_MC_DISPLAY1BB 7 +#define TEGRA20_MC_EPPUP 8 +#define TEGRA20_MC_G2PR 9 +#define TEGRA20_MC_G2SR 10 +#define TEGRA20_MC_MPEUNIFBR 11 +#define TEGRA20_MC_VIRUV 12 +#define TEGRA20_MC_AVPCARM7R 13 +#define TEGRA20_MC_DISPLAYHC 14 +#define TEGRA20_MC_DISPLAYHCB 15 +#define TEGRA20_MC_FDCDRD 16 +#define TEGRA20_MC_G2DR 17 +#define TEGRA20_MC_HOST1XDMAR 18 +#define TEGRA20_MC_HOST1XR 19 +#define TEGRA20_MC_IDXSRD 20 +#define TEGRA20_MC_MPCORER 21 +#define TEGRA20_MC_MPE_IPRED 22 +#define TEGRA20_MC_MPEAMEMRD 23 +#define TEGRA20_MC_MPECSRD 24 +#define TEGRA20_MC_PPCSAHBDMAR 25 +#define TEGRA20_MC_PPCSAHBSLVR 26 +#define TEGRA20_MC_TEXSRD 27 +#define TEGRA20_MC_VDEBSEVR 28 +#define TEGRA20_MC_VDEMBER 29 +#define TEGRA20_MC_VDEMCER 30 +#define TEGRA20_MC_VDETPER 31 +#define TEGRA20_MC_EPPU 32 +#define TEGRA20_MC_EPPV 33 +#define TEGRA20_MC_EPPY 34 +#define TEGRA20_MC_MPEUNIFBW 35 +#define TEGRA20_MC_VIWSB 36 +#define TEGRA20_MC_VIWU 37 +#define TEGRA20_MC_VIWV 38 +#define TEGRA20_MC_VIWY 39 +#define TEGRA20_MC_G2DW 40 +#define TEGRA20_MC_AVPCARM7W 41 +#define TEGRA20_MC_FDCDWR 42 +#define TEGRA20_MC_HOST1XW 43 +#define TEGRA20_MC_ISPW 44 +#define TEGRA20_MC_MPCOREW 45 +#define TEGRA20_MC_MPECSWR 46 +#define TEGRA20_MC_PPCSAHBDMAW 47 +#define TEGRA20_MC_PPCSAHBSLVW 48 +#define TEGRA20_MC_VDEBSEVW 49 +#define TEGRA20_MC_VDEMBEW 50 +#define TEGRA20_MC_VDETPMW 51 + #endif From f25696bce9604dbfd8d956da6023d18a05ec8ed3 Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Wed, 4 Nov 2020 19:48:54 +0300 Subject: [PATCH 537/799] dt-bindings: memory: tegra30: Add memory client IDs Each memory client has unique hardware ID, add these IDs. Acked-by: Rob Herring Signed-off-by: Dmitry Osipenko Acked-by: Krzysztof Kozlowski Signed-off-by: Thierry Reding --- include/dt-bindings/memory/tegra30-mc.h | 67 +++++++++++++++++++++++++ 1 file changed, 67 insertions(+) diff --git a/include/dt-bindings/memory/tegra30-mc.h b/include/dt-bindings/memory/tegra30-mc.h index 169f005fbc78..930f708aca17 100644 --- a/include/dt-bindings/memory/tegra30-mc.h +++ b/include/dt-bindings/memory/tegra30-mc.h @@ -41,4 +41,71 @@ #define TEGRA30_MC_RESET_VDE 16 #define TEGRA30_MC_RESET_VI 17 +#define TEGRA30_MC_PTCR 0 +#define TEGRA30_MC_DISPLAY0A 1 +#define TEGRA30_MC_DISPLAY0AB 2 +#define TEGRA30_MC_DISPLAY0B 3 +#define TEGRA30_MC_DISPLAY0BB 4 +#define TEGRA30_MC_DISPLAY0C 5 +#define TEGRA30_MC_DISPLAY0CB 6 +#define TEGRA30_MC_DISPLAY1B 7 +#define TEGRA30_MC_DISPLAY1BB 8 +#define TEGRA30_MC_EPPUP 9 +#define TEGRA30_MC_G2PR 10 +#define TEGRA30_MC_G2SR 11 +#define TEGRA30_MC_MPEUNIFBR 12 +#define TEGRA30_MC_VIRUV 13 +#define TEGRA30_MC_AFIR 14 +#define TEGRA30_MC_AVPCARM7R 15 +#define TEGRA30_MC_DISPLAYHC 16 +#define TEGRA30_MC_DISPLAYHCB 17 +#define TEGRA30_MC_FDCDRD 18 +#define TEGRA30_MC_FDCDRD2 19 +#define TEGRA30_MC_G2DR 20 +#define TEGRA30_MC_HDAR 21 +#define TEGRA30_MC_HOST1XDMAR 22 +#define TEGRA30_MC_HOST1XR 23 +#define TEGRA30_MC_IDXSRD 24 +#define TEGRA30_MC_IDXSRD2 25 +#define TEGRA30_MC_MPE_IPRED 26 +#define TEGRA30_MC_MPEAMEMRD 27 +#define TEGRA30_MC_MPECSRD 28 +#define TEGRA30_MC_PPCSAHBDMAR 29 +#define TEGRA30_MC_PPCSAHBSLVR 30 +#define TEGRA30_MC_SATAR 31 +#define TEGRA30_MC_TEXSRD 32 +#define TEGRA30_MC_TEXSRD2 33 +#define TEGRA30_MC_VDEBSEVR 34 +#define TEGRA30_MC_VDEMBER 35 +#define TEGRA30_MC_VDEMCER 36 +#define TEGRA30_MC_VDETPER 37 +#define TEGRA30_MC_MPCORELPR 38 +#define TEGRA30_MC_MPCORER 39 +#define TEGRA30_MC_EPPU 40 +#define TEGRA30_MC_EPPV 41 +#define TEGRA30_MC_EPPY 42 +#define TEGRA30_MC_MPEUNIFBW 43 +#define TEGRA30_MC_VIWSB 44 +#define TEGRA30_MC_VIWU 45 +#define TEGRA30_MC_VIWV 46 +#define TEGRA30_MC_VIWY 47 +#define TEGRA30_MC_G2DW 48 +#define TEGRA30_MC_AFIW 49 +#define TEGRA30_MC_AVPCARM7W 50 +#define TEGRA30_MC_FDCDWR 51 +#define TEGRA30_MC_FDCDWR2 52 +#define TEGRA30_MC_HDAW 53 +#define TEGRA30_MC_HOST1XW 54 +#define TEGRA30_MC_ISPW 55 +#define TEGRA30_MC_MPCORELPW 56 +#define TEGRA30_MC_MPCOREW 57 +#define TEGRA30_MC_MPECSWR 58 +#define TEGRA30_MC_PPCSAHBDMAW 59 +#define TEGRA30_MC_PPCSAHBSLVW 60 +#define TEGRA30_MC_SATAW 61 +#define TEGRA30_MC_VDEBSEVW 62 +#define TEGRA30_MC_VDEDBGW 63 +#define TEGRA30_MC_VDEMBEW 64 +#define TEGRA30_MC_VDETPMW 65 + #endif From 9572399af3fd40fec85b0da55be37eff4e1498c9 Mon Sep 17 00:00:00 2001 From: Peter Geis Date: Sun, 4 Oct 2020 13:31:13 +0000 Subject: [PATCH 538/799] dt-bindings: Add vendor prefix for Ouya Inc. Ouya is a defunct company from 2012 to 2015. They produced a single device, the Ouya game console. In 2015 they were purchased by Razer Inc. and the Ouya was discontinued. All Ouya services were shuttered in 2019. Signed-off-by: Peter Geis Acked-by: Rob Herring Reviewed-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index 2735be1a8470..9225bc779fac 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -792,6 +792,8 @@ patternProperties: description: Ortus Technology Co., Ltd. "^osddisplays,.*": description: OSD Displays + "^ouya,.*": + description: Ouya Inc. "^overkiz,.*": description: Overkiz SAS "^ovti,.*": From 1f956a64301d5ef4ec8f87e17ef169a3edacfab8 Mon Sep 17 00:00:00 2001 From: Peter Geis Date: Sun, 4 Oct 2020 13:31:14 +0000 Subject: [PATCH 539/799] dt-bindings: ARM: tegra: Add Ouya game console Add a binding for the Tegra30-based Ouya game console. Signed-off-by: Peter Geis Acked-by: Rob Herring Reviewed-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- Documentation/devicetree/bindings/arm/tegra.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/tegra.yaml b/Documentation/devicetree/bindings/arm/tegra.yaml index 8ae44948e873..e4bc6feefc8e 100644 --- a/Documentation/devicetree/bindings/arm/tegra.yaml +++ b/Documentation/devicetree/bindings/arm/tegra.yaml @@ -71,6 +71,9 @@ properties: - const: asus,tilapia - const: asus,grouper - const: nvidia,tegra30 + - items: + - const: ouya,ouya + - const: nvidia,tegra30 - items: - enum: - nvidia,dalmore From 3394f98435b598e23cbe8d33f7b9e995535dd721 Mon Sep 17 00:00:00 2001 From: Vidya Sagar Date: Mon, 26 Oct 2020 12:09:01 +0530 Subject: [PATCH 540/799] dt-bindings: Fix entry name for I/O High Voltage property Correct the name of the I/O High Voltage Property from 'nvidia,io-high-voltage' to 'nvidia,io-hv'. Fixes: 2585a584f844 ("pinctrl: Add Tegra194 pinctrl DT bindings") Signed-off-by: Vidya Sagar Acked-by: Rob Herring Signed-off-by: Thierry Reding --- .../devicetree/bindings/pinctrl/nvidia,tegra194-pinmux.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra194-pinmux.txt b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra194-pinmux.txt index 8763f448c376..90d38f710635 100644 --- a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra194-pinmux.txt +++ b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra194-pinmux.txt @@ -99,7 +99,7 @@ Example: nvidia,schmitt = ; nvidia,lpdr = ; nvidia,enable-input = ; - nvidia,io-high-voltage = ; + nvidia,io-hv = ; nvidia,tristate = ; nvidia,pull = ; }; From 24a7eaea0a941c9e5e243ffb40073dcafecd3c11 Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Wed, 4 Nov 2020 19:48:55 +0300 Subject: [PATCH 541/799] dt-bindings: memory: tegra124: Add memory client IDs Each memory client has unique hardware ID, add these IDs. Reviewed-by: Rob Herring Signed-off-by: Dmitry Osipenko Acked-by: Krzysztof Kozlowski Signed-off-by: Thierry Reding --- include/dt-bindings/memory/tegra124-mc.h | 68 ++++++++++++++++++++++++ 1 file changed, 68 insertions(+) diff --git a/include/dt-bindings/memory/tegra124-mc.h b/include/dt-bindings/memory/tegra124-mc.h index 186e6b7e9b35..7e73bb400eca 100644 --- a/include/dt-bindings/memory/tegra124-mc.h +++ b/include/dt-bindings/memory/tegra124-mc.h @@ -54,4 +54,72 @@ #define TEGRA124_MC_RESET_ISP2B 22 #define TEGRA124_MC_RESET_GPU 23 +#define TEGRA124_MC_PTCR 0 +#define TEGRA124_MC_DISPLAY0A 1 +#define TEGRA124_MC_DISPLAY0AB 2 +#define TEGRA124_MC_DISPLAY0B 3 +#define TEGRA124_MC_DISPLAY0BB 4 +#define TEGRA124_MC_DISPLAY0C 5 +#define TEGRA124_MC_DISPLAY0CB 6 +#define TEGRA124_MC_AFIR 14 +#define TEGRA124_MC_AVPCARM7R 15 +#define TEGRA124_MC_DISPLAYHC 16 +#define TEGRA124_MC_DISPLAYHCB 17 +#define TEGRA124_MC_HDAR 21 +#define TEGRA124_MC_HOST1XDMAR 22 +#define TEGRA124_MC_HOST1XR 23 +#define TEGRA124_MC_MSENCSRD 28 +#define TEGRA124_MC_PPCSAHBDMAR 29 +#define TEGRA124_MC_PPCSAHBSLVR 30 +#define TEGRA124_MC_SATAR 31 +#define TEGRA124_MC_VDEBSEVR 34 +#define TEGRA124_MC_VDEMBER 35 +#define TEGRA124_MC_VDEMCER 36 +#define TEGRA124_MC_VDETPER 37 +#define TEGRA124_MC_MPCORELPR 38 +#define TEGRA124_MC_MPCORER 39 +#define TEGRA124_MC_MSENCSWR 43 +#define TEGRA124_MC_AFIW 49 +#define TEGRA124_MC_AVPCARM7W 50 +#define TEGRA124_MC_HDAW 53 +#define TEGRA124_MC_HOST1XW 54 +#define TEGRA124_MC_MPCORELPW 56 +#define TEGRA124_MC_MPCOREW 57 +#define TEGRA124_MC_PPCSAHBDMAW 59 +#define TEGRA124_MC_PPCSAHBSLVW 60 +#define TEGRA124_MC_SATAW 61 +#define TEGRA124_MC_VDEBSEVW 62 +#define TEGRA124_MC_VDEDBGW 63 +#define TEGRA124_MC_VDEMBEW 64 +#define TEGRA124_MC_VDETPMW 65 +#define TEGRA124_MC_ISPRA 68 +#define TEGRA124_MC_ISPWA 70 +#define TEGRA124_MC_ISPWB 71 +#define TEGRA124_MC_XUSB_HOSTR 74 +#define TEGRA124_MC_XUSB_HOSTW 75 +#define TEGRA124_MC_XUSB_DEVR 76 +#define TEGRA124_MC_XUSB_DEVW 77 +#define TEGRA124_MC_ISPRAB 78 +#define TEGRA124_MC_ISPWAB 80 +#define TEGRA124_MC_ISPWBB 81 +#define TEGRA124_MC_TSECSRD 84 +#define TEGRA124_MC_TSECSWR 85 +#define TEGRA124_MC_A9AVPSCR 86 +#define TEGRA124_MC_A9AVPSCW 87 +#define TEGRA124_MC_GPUSRD 88 +#define TEGRA124_MC_GPUSWR 89 +#define TEGRA124_MC_DISPLAYT 90 +#define TEGRA124_MC_SDMMCRA 96 +#define TEGRA124_MC_SDMMCRAA 97 +#define TEGRA124_MC_SDMMCR 98 +#define TEGRA124_MC_SDMMCRAB 99 +#define TEGRA124_MC_SDMMCWA 100 +#define TEGRA124_MC_SDMMCWAA 101 +#define TEGRA124_MC_SDMMCW 102 +#define TEGRA124_MC_SDMMCWAB 103 +#define TEGRA124_MC_VICSRD 108 +#define TEGRA124_MC_VICSWR 109 +#define TEGRA124_MC_VIW 114 +#define TEGRA124_MC_DISPLAYD 115 + #endif From 15f76096fabba229476b01c7890f3c3ff843cc11 Mon Sep 17 00:00:00 2001 From: Sameer Pujar Date: Fri, 6 Nov 2020 21:13:31 +0530 Subject: [PATCH 542/799] dt-bindings: dma: Convert ADMA doc to json-schema Move ADMA documentation to YAML format. Signed-off-by: Sameer Pujar Reviewed-by: Rob Herring Signed-off-by: Thierry Reding --- .../bindings/dma/nvidia,tegra210-adma.txt | 56 ----------- .../bindings/dma/nvidia,tegra210-adma.yaml | 99 +++++++++++++++++++ 2 files changed, 99 insertions(+), 56 deletions(-) delete mode 100644 Documentation/devicetree/bindings/dma/nvidia,tegra210-adma.txt create mode 100644 Documentation/devicetree/bindings/dma/nvidia,tegra210-adma.yaml diff --git a/Documentation/devicetree/bindings/dma/nvidia,tegra210-adma.txt b/Documentation/devicetree/bindings/dma/nvidia,tegra210-adma.txt deleted file mode 100644 index 245d3063715c..000000000000 --- a/Documentation/devicetree/bindings/dma/nvidia,tegra210-adma.txt +++ /dev/null @@ -1,56 +0,0 @@ -* NVIDIA Tegra Audio DMA (ADMA) controller - -The Tegra Audio DMA controller that is used for transferring data -between system memory and the Audio Processing Engine (APE). - -Required properties: -- compatible: Should contain one of the following: - - "nvidia,tegra210-adma": for Tegra210 - - "nvidia,tegra186-adma": for Tegra186 and Tegra194 -- reg: Should contain DMA registers location and length. This should be - a single entry that includes all of the per-channel registers in one - contiguous bank. -- interrupts: Should contain all of the per-channel DMA interrupts in - ascending order with respect to the DMA channel index. -- clocks: Must contain one entry for the ADMA module clock - (TEGRA210_CLK_D_AUDIO). -- clock-names: Must contain the name "d_audio" for the corresponding - 'clocks' entry. -- #dma-cells : Must be 1. The first cell denotes the receive/transmit - request number and should be between 1 and the maximum number of - requests supported. This value corresponds to the RX/TX_REQUEST_SELECT - fields in the ADMA_CHn_CTRL register. - - -Example: - -adma: dma@702e2000 { - compatible = "nvidia,tegra210-adma"; - reg = <0x0 0x702e2000 0x0 0x2000>; - interrupt-parent = <&tegra_agic>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>; - clock-names = "d_audio"; - #dma-cells = <1>; -}; diff --git a/Documentation/devicetree/bindings/dma/nvidia,tegra210-adma.yaml b/Documentation/devicetree/bindings/dma/nvidia,tegra210-adma.yaml new file mode 100644 index 000000000000..5c2e2f156e31 --- /dev/null +++ b/Documentation/devicetree/bindings/dma/nvidia,tegra210-adma.yaml @@ -0,0 +1,99 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/dma/nvidia,tegra210-adma.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra Audio DMA (ADMA) controller + +description: | + The Tegra Audio DMA controller is used for transferring data + between system memory and the Audio Processing Engine (APE). + +maintainers: + - Jon Hunter + +allOf: + - $ref: "dma-controller.yaml#" + +properties: + compatible: + oneOf: + - enum: + - nvidia,tegra210-adma + - nvidia,tegra186-adma + - items: + - const: nvidia,tegra194-adma + - const: nvidia,tegra186-adma + + reg: + maxItems: 1 + + interrupts: + description: | + Should contain all of the per-channel DMA interrupts in + ascending order with respect to the DMA channel index. + minItems: 1 + maxItems: 32 + + clocks: + description: Must contain one entry for the ADMA module clock + maxItems: 1 + + clock-names: + const: d_audio + + "#dma-cells": + description: | + The first cell denotes the receive/transmit request number and + should be between 1 and the maximum number of requests supported. + This value corresponds to the RX/TX_REQUEST_SELECT fields in the + ADMA_CHn_CTRL register. + const: 1 + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + #include + #include + + dma-controller@702e2000 { + compatible = "nvidia,tegra210-adma"; + reg = <0x702e2000 0x2000>; + interrupt-parent = <&tegra_agic>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>; + clock-names = "d_audio"; + #dma-cells = <1>; + }; + +... From d806cdaea133c0c4d66359e4398651be4715f51f Mon Sep 17 00:00:00 2001 From: Sameer Pujar Date: Fri, 6 Nov 2020 21:13:32 +0530 Subject: [PATCH 543/799] dt-bindings: interrupt-controller: arm,gic: Update Tegra compatibles Update Tegra compatibles to support newer Tegra chips and required combinations. Signed-off-by: Sameer Pujar Reviewed-by: Rob Herring Signed-off-by: Thierry Reding --- .../bindings/interrupt-controller/arm,gic.yaml | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/interrupt-controller/arm,gic.yaml b/Documentation/devicetree/bindings/interrupt-controller/arm,gic.yaml index 06889963dfb7..ba282f4c9fd0 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/arm,gic.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/arm,gic.yaml @@ -35,7 +35,6 @@ properties: - arm,gic-400 - arm,pl390 - arm,tc11mp-gic - - nvidia,tegra210-agic - qcom,msm-8660-qgic - qcom,msm-qgic2 @@ -53,6 +52,14 @@ properties: - const: brcm,brahma-b15-gic - const: arm,cortex-a15-gic + - oneOf: + - const: nvidia,tegra210-agic + - items: + - enum: + - nvidia,tegra186-agic + - nvidia,tegra194-agic + - const: nvidia,tegra210-agic + interrupt-controller: true "#address-cells": From e36f9381420b28e1785d7900d4c1d9db6149cbcd Mon Sep 17 00:00:00 2001 From: Sameer Pujar Date: Fri, 6 Nov 2020 21:13:33 +0530 Subject: [PATCH 544/799] dt-bindings: bus: Convert ACONNECT doc to json-schema Move ACONNECT documentation to YAML format. Signed-off-by: Sameer Pujar Reviewed-by: Rob Herring Signed-off-by: Thierry Reding --- .../bindings/bus/nvidia,tegra210-aconnect.txt | 44 ---------- .../bus/nvidia,tegra210-aconnect.yaml | 82 +++++++++++++++++++ 2 files changed, 82 insertions(+), 44 deletions(-) delete mode 100644 Documentation/devicetree/bindings/bus/nvidia,tegra210-aconnect.txt create mode 100644 Documentation/devicetree/bindings/bus/nvidia,tegra210-aconnect.yaml diff --git a/Documentation/devicetree/bindings/bus/nvidia,tegra210-aconnect.txt b/Documentation/devicetree/bindings/bus/nvidia,tegra210-aconnect.txt deleted file mode 100644 index 3108d03802ee..000000000000 --- a/Documentation/devicetree/bindings/bus/nvidia,tegra210-aconnect.txt +++ /dev/null @@ -1,44 +0,0 @@ -NVIDIA Tegra ACONNECT Bus - -The Tegra ACONNECT bus is an AXI switch which is used to connnect various -components inside the Audio Processing Engine (APE). All CPU accesses to -the APE subsystem go through the ACONNECT via an APB to AXI wrapper. - -Required properties: -- compatible: Must be "nvidia,tegra210-aconnect". -- clocks: Must contain the entries for the APE clock (TEGRA210_CLK_APE), - and APE interface clock (TEGRA210_CLK_APB2APE). -- clock-names: Must contain the names "ape" and "apb2ape" for the corresponding - 'clocks' entries. -- power-domains: Must contain a phandle that points to the audio powergate - (namely 'aud') for Tegra210. -- #address-cells: The number of cells used to represent physical base addresses - in the aconnect address space. Should be 1. -- #size-cells: The number of cells used to represent the size of an address - range in the aconnect address space. Should be 1. -- ranges: Mapping of the aconnect address space to the CPU address space. - -All devices accessed via the ACONNNECT are described by child-nodes. - -Example: - - aconnect@702c0000 { - compatible = "nvidia,tegra210-aconnect"; - clocks = <&tegra_car TEGRA210_CLK_APE>, - <&tegra_car TEGRA210_CLK_APB2APE>; - clock-names = "ape", "apb2ape"; - power-domains = <&pd_audio>; - - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x702c0000 0x0 0x702c0000 0x00040000>; - - - child1 { - ... - }; - - child2 { - ... - }; - }; diff --git a/Documentation/devicetree/bindings/bus/nvidia,tegra210-aconnect.yaml b/Documentation/devicetree/bindings/bus/nvidia,tegra210-aconnect.yaml new file mode 100644 index 000000000000..7b1a08c62aef --- /dev/null +++ b/Documentation/devicetree/bindings/bus/nvidia,tegra210-aconnect.yaml @@ -0,0 +1,82 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/bus/nvidia,tegra210-aconnect.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra ACONNECT Bus + +description: | + The Tegra ACONNECT bus is an AXI switch which is used to connnect various + components inside the Audio Processing Engine (APE). All CPU accesses to + the APE subsystem go through the ACONNECT via an APB to AXI wrapper. All + devices accessed via the ACONNNECT are described by child-nodes. + +maintainers: + - Jon Hunter + +properties: + compatible: + oneOf: + - const: nvidia,tegra210-aconnect + - items: + - enum: + - nvidia,tegra186-aconnect + - nvidia,tegra194-aconnect + - const: nvidia,tegra210-aconnect + + clocks: + items: + - description: Must contain the entry for APE clock + - description: Must contain the entry for APE interface clock + + clock-names: + items: + - const: ape + - const: apb2ape + + power-domains: + maxItems: 1 + + "#address-cells": + const: 1 + + "#size-cells": + const: 1 + + ranges: true + +patternProperties: + "@[0-9a-f]+$": + type: object + +required: + - compatible + - clocks + - clock-names + - power-domains + - "#address-cells" + - "#size-cells" + - ranges + +additionalProperties: false + +examples: + - | + #include + + aconnect@702c0000 { + compatible = "nvidia,tegra210-aconnect"; + clocks = <&tegra_car TEGRA210_CLK_APE>, + <&tegra_car TEGRA210_CLK_APB2APE>; + clock-names = "ape", "apb2ape"; + power-domains = <&pd_audio>; + + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x702c0000 0x702c0000 0x00040000>; + + // Child device nodes follow ... + }; + +... From d7195ac5c9c5356b7cda4668fb64fc537c6be833 Mon Sep 17 00:00:00 2001 From: Peter Geis Date: Sun, 4 Oct 2020 13:31:12 +0000 Subject: [PATCH 545/799] ARM: tegra: Add device-tree for Ouya The Ouya was the sole device produced by Ouya Inc in 2013. It was a game console originally running Android 5 on top of Linux 3.1.10. This patch adds the device tree supporting the Ouya. It has been tested on the original variant with Samsung ram. Signed-off-by: Peter Geis Reviewed-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- arch/arm/boot/dts/Makefile | 3 +- arch/arm/boot/dts/tegra30-ouya.dts | 4511 ++++++++++++++++++++++++++++ 2 files changed, 4513 insertions(+), 1 deletion(-) create mode 100644 arch/arm/boot/dts/tegra30-ouya.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index ce66ffd5a1bb..10d7da888ebb 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1241,7 +1241,8 @@ dtb-$(CONFIG_ARCH_TEGRA_3x_SOC) += \ tegra30-beaver.dtb \ tegra30-cardhu-a02.dtb \ tegra30-cardhu-a04.dtb \ - tegra30-colibri-eval-v3.dtb + tegra30-colibri-eval-v3.dtb \ + tegra30-ouya.dtb dtb-$(CONFIG_ARCH_TEGRA_114_SOC) += \ tegra114-dalmore.dtb \ tegra114-roth.dtb \ diff --git a/arch/arm/boot/dts/tegra30-ouya.dts b/arch/arm/boot/dts/tegra30-ouya.dts new file mode 100644 index 000000000000..a5f16ad6c8f4 --- /dev/null +++ b/arch/arm/boot/dts/tegra30-ouya.dts @@ -0,0 +1,4511 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include +#include +#include + +#include "tegra30.dtsi" +#include "tegra30-cpu-opp.dtsi" +#include "tegra30-cpu-opp-microvolt.dtsi" + +/ { + model = "Ouya Game Console"; + compatible = "ouya,ouya", "nvidia,tegra30"; + + aliases { + mmc0 = &sdmmc4; /* eMMC */ + mmc1 = &sdmmc3; /* WiFi */ + rtc0 = &pmic; + rtc1 = "/rtc@7000e000"; + serial0 = &uartd; /* Debug Port */ + serial1 = &uartc; /* Bluetooth */ + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@80000000 { + reg = <0x80000000 0x40000000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + linux,cma@80000000 { + compatible = "shared-dma-pool"; + alloc-ranges = <0x80000000 0x30000000>; + size = <0x10000000>; /* 256MiB */ + linux,cma-default; + reusable; + }; + + ramoops@bfdf0000 { + compatible = "ramoops"; + reg = <0xbfdf0000 0x10000>; /* 64kB */ + console-size = <0x8000>; /* 32kB */ + record-size = <0x400>; /* 1kB */ + ecc-size = <16>; + }; + + trustzone@bfe00000 { + reg = <0xbfe00000 0x200000>; + no-map; + }; + }; + + host1x@50000000 { + hdmi@54280000 { + status = "okay"; + vdd-supply = <&vdd_vid_reg>; + pll-supply = <&ldo7_reg>; + hdmi-supply = <&sys_3v3_reg>; + nvidia,ddc-i2c-bus = <&hdmi_ddc>; + nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>; + }; + }; + + gpio: gpio@6000d000 { + gpio-ranges = <&pinmux 0 0 248>; + #reset-cells = <1>; + }; + + pinmux@70000868 { + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + state_default: pinmux { + /* located at $state_default below */ + }; + }; + + uartc: serial@70006200 { + status = "okay"; + compatible = "nvidia,tegra30-hsuart"; + + nvidia,adjust-baud-rates = <0 9600 100>, + <9600 115200 200>, + <1000000 4000000 136>; + + /* Azurewave AW-NH660 BCM4330B1 */ + bluetooth { + compatible = "brcm,bcm4330-bt"; + + max-speed = <4000000>; + + clocks = <&tegra_pmc TEGRA_PMC_CLK_BLINK>; + clock-names = "txco"; + + vbat-supply = <&sys_3v3_reg>; + vddio-supply = <&vdd_1v8>; + + shutdown-gpios = <&gpio TEGRA_GPIO(U, 0) GPIO_ACTIVE_HIGH>; + device-wakeup-gpios = <&gpio TEGRA_GPIO(U, 1) GPIO_ACTIVE_HIGH>; + host-wakeup-gpios = <&gpio TEGRA_GPIO(U, 6) GPIO_ACTIVE_HIGH>; + }; + }; + + uartd: serial@70006300 { + status = "okay"; + }; + + hdmi_ddc: i2c@7000c700 { + status = "okay"; + clock-frequency = <100000>; + }; + + i2c@7000d000 { + status = "okay"; + clock-frequency = <400000>; + + cpu_temp: nct1008@4c { + compatible = "onnn,nct1008"; + reg = <0x4c>; + vcc-supply = <&sys_3v3_reg>; + #thermal-sensor-cells = <1>; +/* + * The interrupt is bugged, once triggered it never clears. + * interrupt-parent = <&gpio>; + * interrupts = ; + */ + }; + + pmic: pmic@2d { + compatible = "ti,tps65911"; + reg = <0x2d>; + + interrupts = ; + #interrupt-cells = <2>; + interrupt-controller; + + ti,en-gpio-sleep = <0 1 1 1 1 1 0 0 1>; + ti,system-power-controller; + ti,sleep-keep-ck32k; + ti,sleep-enable; + + #gpio-cells = <2>; + gpio-controller; + + vcc1-supply = <&vdd_5v0_reg>; + vcc2-supply = <&vdd_5v0_reg>; + vcc3-supply = <&vdd_1v8>; + vcc4-supply = <&vdd_5v0_reg>; + vcc5-supply = <&vdd_5v0_reg>; + vcc6-supply = <&vdd2_reg>; + vcc7-supply = <&vdd_5v0_reg>; + vccio-supply = <&vdd_5v0_reg>; + + regulators { + vdd1_reg: vdd1 { + regulator-name = "vddio_ddr_1v2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + vdd2_reg: vdd2 { + regulator-name = "vdd_1v5_gen"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + }; + + vdd_cpu: vddctrl { + regulator-name = "vdd_cpu,vdd_sys"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1270000>; + regulator-coupled-with = <&vdd_core>; + regulator-coupled-max-spread = <300000>; + regulator-max-step-microvolt = <100000>; + regulator-always-on; + + nvidia,tegra-cpu-regulator; + }; + + vdd_1v8: vio { + regulator-name = "vdd_1v8_gen"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo1_reg: ldo1 { + regulator-name = "vdd_pexa,vdd_pexb"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + regulator-always-on; + }; + + ldo2_reg: ldo2 { + regulator-name = "vdd_sata,avdd_plle"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + regulator-always-on; + }; + + /* LDO3 is not connected to anything */ + + ldo4_reg: ldo4 { + regulator-name = "vdd_rtc"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + ldo5_reg: ldo5 { + regulator-name = "vddio_sdmmc,avdd_vdac"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + ldo6_reg: ldo6 { + regulator-name = "avdd_dsi_csi,pwrdet_mipi"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + ldo7_reg: ldo7 { + regulator-name = "vdd_pllm,x,u,a_p_c_s"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + ldo8_reg: ldo8 { + regulator-name = "vdd_ddr_hs"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + }; + }; + + vdd_core: tps62361@60 { + compatible = "ti,tps62361"; + reg = <0x60>; + + regulator-name = "vdd_core"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1350000>; + regulator-coupled-with = <&vdd_cpu>; + regulator-coupled-max-spread = <300000>; + regulator-max-step-microvolt = <100000>; + regulator-boot-on; + regulator-always-on; + ti,vsel0-state-high; + ti,vsel1-state-high; + ti,enable-vout-discharge; + + nvidia,tegra-core-regulator; + }; + }; + + pmc@7000e400 { + status = "okay"; + nvidia,invert-interrupt; + nvidia,suspend-mode = <1>; + nvidia,cpu-pwr-good-time = <2000>; + nvidia,cpu-pwr-off-time = <200>; + nvidia,core-pwr-good-time = <3845 3845>; + nvidia,core-pwr-off-time = <458>; + nvidia,core-power-req-active-high; + nvidia,sys-clock-req-active-high; + }; + + mc_timings: memory-controller@7000f000 { + /* timings located at &mc_timings below */ + }; + + emc_timings: memory-controller@7000f400 { + /* timings located at &emc_timings below */ + }; + + hda@70030000 { + status = "okay"; + }; + + wifi_pwrseq: wifi_pwrseq { + compatible = "mmc-pwrseq-simple"; + + clocks = <&tegra_pmc TEGRA_PMC_CLK_BLINK>; + clock-names = "ext_clock"; + + reset-gpios = <&gpio TEGRA_GPIO(D, 3) GPIO_ACTIVE_LOW>; + post-power-on-delay-ms = <300>; + power-off-delay-us = <300>; + }; + + sdmmc3: mmc@78000400 { + status = "okay"; + + #address-cells = <1>; + #size-cells = <0>; + + assigned-clocks = <&tegra_car TEGRA30_CLK_SDMMC3>; + assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_C>; + assigned-clock-rates = <50000000>; + + max-frequency = <50000000>; + keep-power-in-suspend; + + bus-width = <4>; + non-removable; + + mmc-pwrseq = <&wifi_pwrseq>; + vmmc-supply = <&sdmmc_3v3_reg>; + vqmmc-supply = <&vdd_1v8>; + + /* Azurewave AW-NH660 BCM4330 */ + brcmf: wifi@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + interrupt-parent = <&gpio>; + interrupts = ; + interrupt-names = "host-wake"; + }; + }; + + sdmmc4: mmc@78000600 { + status = "okay"; + + keep-power-in-suspend; + bus-width = <8>; + non-removable; + vmmc-supply = <&sys_3v3_reg>; + vqmmc-supply = <&vdd_1v8>; + nvidia,default-tap = <0x0F>; + max-frequency = <25500000>; + }; + + usb@7d000000 { + compatible = "nvidia,tegra30-udc"; + status = "okay"; + }; + + usb-phy@7d000000 { + status = "okay"; + dr_mode = "peripheral"; + }; + + usb@7d004000 { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + smsc@2 { /* SMSC 10/100T Ethernet Controller */ + compatible = "usb424,9e00"; + reg = <2>; + local-mac-address = [00 11 22 33 44 55]; + }; + }; + + usb-phy@7d004000 { + vbus-supply = <&vdd_smsc>; + status = "okay"; + }; + + usb@7d008000 { + status = "okay"; + }; + + usb-phy@7d008000 { + vbus-supply = <&usb3_vbus_reg>; + status = "okay"; + }; + + /* PMIC has a built-in 32KHz oscillator which is used by PMC */ + clk32k_in: clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "pmic-oscillator"; + }; + + cpus { + cpu0: cpu@0 { + operating-points-v2 = <&cpu0_opp_table>; + cpu-supply = <&vdd_cpu>; + #cooling-cells = <2>; + }; + cpu@1 { + operating-points-v2 = <&cpu0_opp_table>; + cpu-supply = <&vdd_cpu>; + }; + + cpu@2 { + operating-points-v2 = <&cpu0_opp_table>; + cpu-supply = <&vdd_cpu>; + }; + + cpu@3 { + operating-points-v2 = <&cpu0_opp_table>; + cpu-supply = <&vdd_cpu>; + }; + }; + + firmware { + trusted-foundations { + compatible = "tlm,trusted-foundations"; + tlm,version-major = <0x0>; + tlm,version-minor = <0x0>; + }; + }; + + fan: gpio_fan { + compatible = "gpio-fan"; + gpios = <&gpio TEGRA_GPIO(J, 2) GPIO_ACTIVE_HIGH>; + gpio-fan,speed-map = <0 0 + 4500 1>; + #cooling-cells = <2>; + }; + + thermal-zones { + cpu_thermal: cpu-thermal { + polling-delay = <5000>; + polling-delay-passive = <5000>; + + thermal-sensors = <&cpu_temp 1>; + + trips { + cpu_alert0: cpu-alert0 { + temperature = <50000>; + hysteresis = <10000>; + type = "active"; + }; + cpu_alert1: cpu-alert1 { + temperature = <70000>; + hysteresis = <5000>; + type = "passive"; + }; + cpu_crit: cpu-crit { + temperature = <90000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu_alert0>; + cooling-device = <&fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + map1 { + trip = <&cpu_alert1>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + }; + + vdd_12v_in: vdd_12v_in { + compatible = "regulator-fixed"; + regulator-name = "vdd_12v_in"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + regulator-always-on; + }; + + sdmmc_3v3_reg: sdmmc_3v3_reg { + compatible = "regulator-fixed"; + regulator-name = "sdmmc_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + regulator-always-on; + gpio = <&gpio TEGRA_GPIO(D, 4) GPIO_ACTIVE_HIGH>; + vin-supply = <&sys_3v3_reg>; + }; + + vdd_fuse_3v3_reg: vdd_fuse_3v3_reg { + compatible = "regulator-fixed"; + regulator-name = "vdd_fuse_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpio = <&gpio TEGRA_GPIO(L, 6) GPIO_ACTIVE_HIGH>; + vin-supply = <&sys_3v3_reg>; + regulator-always-on; + }; + + vdd_vid_reg: vdd_vid_reg { + compatible = "regulator-fixed"; + regulator-name = "vddio_vid"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio TEGRA_GPIO(T, 0) GPIO_ACTIVE_HIGH>; + vin-supply = <&vdd_5v0_reg>; + regulator-boot-on; + }; + + ddr_reg: ddr_reg { + compatible = "regulator-fixed"; + regulator-name = "vdd_ddr"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + enable-active-high; + gpio = <&pmic 7 GPIO_ACTIVE_HIGH>; + regulator-boot-on; + vin-supply = <&vdd_12v_in>; + }; + + sys_3v3_reg: sys_3v3_reg { + compatible = "regulator-fixed"; + regulator-name = "sys_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpio = <&pmic 6 GPIO_ACTIVE_HIGH>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vdd_12v_in>; + }; + + vdd_5v0_reg: vdd_5v0_reg { + compatible = "regulator-fixed"; + regulator-name = "vdd_5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&pmic 0 GPIO_ACTIVE_HIGH>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vdd_12v_in>; + }; + + vdd_smsc: vdd_smsc { + compatible = "regulator-fixed"; + regulator-name = "vdd_smsc"; + enable-active-high; + gpio = <&gpio TEGRA_GPIO(DD, 5) GPIO_ACTIVE_HIGH>; + }; + + usb3_vbus_reg: usb3_vbus_reg { + compatible = "regulator-fixed"; + regulator-name = "usb3_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio TEGRA_GPIO(DD, 4) GPIO_ACTIVE_HIGH>; + vin-supply = <&vdd_5v0_reg>; + }; + + gpio-keys { + compatible = "gpio-keys"; + + power { + gpios = <&gpio TEGRA_GPIO(V, 0) GPIO_ACTIVE_LOW>; + debounce-interval = <10>; + linux,code = ; + wakeup-event-action = ; + wakeup-source; + }; + }; + + + leds { + compatible = "gpio-leds"; + + led-power { + label = "power-led"; + gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>; + default-state = "on"; + linux,default-trigger = "heartbeat"; + retain-state-suspended; + }; + }; +}; +&mc_timings { + emc-timings-0 { + nvidia,ram-code = <0>; /* Samsung RAM */ + timing-25500000 { + clock-frequency = <25500000>; + nvidia,emem-configuration = < + 0x00030003 /* MC_EMEM_ARB_CFG */ + 0xc0000010 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000001 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06020102 /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0502 /* MC_EMEM_ARB_DA_COVERS */ + 0x75830303 /* MC_EMEM_ARB_MISC0 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + timing-51000000 { + clock-frequency = <51000000>; + nvidia,emem-configuration = < + 0x00010003 /* MC_EMEM_ARB_CFG */ + 0xc0000010 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000001 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06020102 /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0502 /* MC_EMEM_ARB_DA_COVERS */ + 0x74630303 /* MC_EMEM_ARB_MISC0 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + timing-102000000 { + clock-frequency = <102000000>; + nvidia,emem-configuration = < + 0x00000003 /* MC_EMEM_ARB_CFG */ + 0xc0000018 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06020102 /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0503 /* MC_EMEM_ARB_DA_COVERS */ + 0x73c30504 /* MC_EMEM_ARB_MISC0 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + timing-204000000 { + clock-frequency = <204000000>; + nvidia,emem-configuration = < + 0x00000006 /* MC_EMEM_ARB_CFG */ + 0xc0000025 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000005 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000004 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06020102 /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0505 /* MC_EMEM_ARB_DA_COVERS */ + 0x73840a06 /* MC_EMEM_ARB_MISC0 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + timing-400000000 { + clock-frequency = <400000000>; + nvidia,emem-configuration = < + 0x0000000c /* MC_EMEM_ARB_CFG */ + 0xc0000048 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000009 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000005 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000007 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06030202 /* MC_EMEM_ARB_DA_TURNS */ + 0x000d0709 /* MC_EMEM_ARB_DA_COVERS */ + 0x7086120a /* MC_EMEM_ARB_MISC0 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + timing-800000000 { + clock-frequency = <800000000>; + nvidia,emem-configuration = < + 0x00000018 /* MC_EMEM_ARB_CFG */ + 0xc0000090 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000004 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000005 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000013 /* MC_EMEM_ARB_TIMING_RC */ + 0x0000000c /* MC_EMEM_ARB_TIMING_RAS */ + 0x0000000f /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x0000000c /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000004 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000008 /* MC_EMEM_ARB_TIMING_W2R */ + 0x08040202 /* MC_EMEM_ARB_DA_TURNS */ + 0x00160d13 /* MC_EMEM_ARB_DA_COVERS */ + 0x712c2414 /* MC_EMEM_ARB_MISC0 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + }; + emc-timings-1 { + nvidia,ram-code = <1>; /* Hynix M RAM */ + timing-25500000 { + clock-frequency = <25500000>; + nvidia,emem-configuration = < + 0x00030003 /* MC_EMEM_ARB_CFG */ + 0xc0000010 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000001 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06020102 /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0502 /* MC_EMEM_ARB_DA_COVERS */ + 0x75830303 /* MC_EMEM_ARB_MISC0 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + timing-51000000 { + clock-frequency = <51000000>; + nvidia,emem-configuration = < + 0x00010003 /* MC_EMEM_ARB_CFG */ + 0xc0000010 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000001 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06020102 /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0502 /* MC_EMEM_ARB_DA_COVERS */ + 0x74630303 /* MC_EMEM_ARB_MISC0 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + timing-102000000 { + clock-frequency = <102000000>; + nvidia,emem-configuration = < + 0x00000003 /* MC_EMEM_ARB_CFG */ + 0xc0000018 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06020102 /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0503 /* MC_EMEM_ARB_DA_COVERS */ + 0x73c30504 /* MC_EMEM_ARB_MISC0 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + timing-204000000 { + clock-frequency = <204000000>; + nvidia,emem-configuration = < + 0x00000006 /* MC_EMEM_ARB_CFG */ + 0xc0000025 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000005 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000004 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06020102 /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0505 /* MC_EMEM_ARB_DA_COVERS */ + 0x73840a06 /* MC_EMEM_ARB_MISC0 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + timing-400000000 { + clock-frequency = <400000000>; + nvidia,emem-configuration = < + 0x0000000c /* MC_EMEM_ARB_CFG */ + 0xc0000048 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000009 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000005 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000007 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06030202 /* MC_EMEM_ARB_DA_TURNS */ + 0x000d0709 /* MC_EMEM_ARB_DA_COVERS */ + 0x7086120a /* MC_EMEM_ARB_MISC0 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + timing-800000000 { + clock-frequency = <800000000>; + nvidia,emem-configuration = < + 0x00000018 /* MC_EMEM_ARB_CFG */ + 0xc0000090 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000004 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000005 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000013 /* MC_EMEM_ARB_TIMING_RC */ + 0x0000000c /* MC_EMEM_ARB_TIMING_RAS */ + 0x0000000f /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x0000000c /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000004 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000008 /* MC_EMEM_ARB_TIMING_W2R */ + 0x08040202 /* MC_EMEM_ARB_DA_TURNS */ + 0x00160d13 /* MC_EMEM_ARB_DA_COVERS */ + 0x712c2414 /* MC_EMEM_ARB_MISC0 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + }; + emc-timings-2 { + nvidia,ram-code = <2>; /* Hynix A RAM */ + timing-25500000 { + clock-frequency = <25500000>; + nvidia,emem-configuration = < + 0x00030003 /* MC_EMEM_ARB_CFG */ + 0xc0000010 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000001 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06020102 /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0502 /* MC_EMEM_ARB_DA_COVERS */ + 0x75e30303 /* MC_EMEM_ARB_MISC0 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + timing-51000000 { + clock-frequency = <51000000>; + nvidia,emem-configuration = < + 0x00010003 /* MC_EMEM_ARB_CFG */ + 0xc0000010 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000001 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06020102 /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0502 /* MC_EMEM_ARB_DA_COVERS */ + 0x74e30303 /* MC_EMEM_ARB_MISC0 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + timing-102000000 { + clock-frequency = <102000000>; + nvidia,emem-configuration = < + 0x00000003 /* MC_EMEM_ARB_CFG */ + 0xc0000018 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06020102 /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0503 /* MC_EMEM_ARB_DA_COVERS */ + 0x74430504 /* MC_EMEM_ARB_MISC0 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + timing-204000000 { + clock-frequency = <204000000>; + nvidia,emem-configuration = < + 0x00000006 /* MC_EMEM_ARB_CFG */ + 0xc0000025 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000005 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000004 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000001 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06020102 /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0505 /* MC_EMEM_ARB_DA_COVERS */ + 0x74040a06 /* MC_EMEM_ARB_MISC0 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + timing-400000000 { + clock-frequency = <400000000>; + nvidia,emem-configuration = < + 0x0000000c /* MC_EMEM_ARB_CFG */ + 0xc0000048 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000009 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000005 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000007 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06030202 /* MC_EMEM_ARB_DA_TURNS */ + 0x000d0709 /* MC_EMEM_ARB_DA_COVERS */ + 0x7086120a /* MC_EMEM_ARB_MISC0 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + timing-800000000 { + clock-frequency = <800000000>; + nvidia,emem-configuration = < + 0x00000018 /* MC_EMEM_ARB_CFG */ + 0xc0000090 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000004 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000005 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000013 /* MC_EMEM_ARB_TIMING_RC */ + 0x0000000c /* MC_EMEM_ARB_TIMING_RAS */ + 0x0000000f /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x0000000c /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000004 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000008 /* MC_EMEM_ARB_TIMING_W2R */ + 0x08040202 /* MC_EMEM_ARB_DA_TURNS */ + 0x00160d13 /* MC_EMEM_ARB_DA_COVERS */ + 0x712c2414 /* MC_EMEM_ARB_MISC0 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + }; +}; +&emc_timings { + emc-timings-0 { + nvidia,ram-code = <0>; /* Samsung RAM */ + timing-25500000 { + clock-frequency = <25500000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-periodic-qrst; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-configuration = < + 0x00000001 /* EMC_RC */ + 0x00000006 /* EMC_RFC */ + 0x00000000 /* EMC_RAS */ + 0x00000000 /* EMC_RP */ + 0x00000002 /* EMC_R2W */ + 0x0000000a /* EMC_W2R */ + 0x00000005 /* EMC_R2P */ + 0x0000000b /* EMC_W2P */ + 0x00000000 /* EMC_RD_RCD */ + 0x00000000 /* EMC_WR_RCD */ + 0x00000003 /* EMC_RRD */ + 0x00000001 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000005 /* EMC_WDV */ + 0x00000005 /* EMC_QUSE */ + 0x00000004 /* EMC_QRST */ + 0x0000000a /* EMC_QSAFE */ + 0x0000000b /* EMC_RDV */ + 0x000000c0 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x00000030 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002 /* EMC_PDEX2WR */ + 0x00000002 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000007 /* EMC_AR2PDEN */ + 0x0000000f /* EMC_RW2PDEN */ + 0x00000007 /* EMC_TXSR */ + 0x00000007 /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000002 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000004 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x000000c7 /* EMC_TREFBW */ + 0x00000006 /* EMC_QUSE_EXTRA */ + 0x00000004 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x00004288 /* EMC_FBIO_CFG5 */ + 0x007800a4 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x000fc000 /* EMC_DLL_XFORM_DQS0 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS1 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS2 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS3 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS4 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS5 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS6 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS7 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ + 0x000002a0 /* EMC_XM2CMDPADCTRL */ + 0x0800211c /* EMC_XM2DQSPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x77fff884 /* EMC_XM2CLKPADCTRL */ + 0x01f1f108 /* EMC_XM2COMPPADCTRL */ + 0x05057404 /* EMC_XM2VTTGENPADCTRL */ + 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ + 0x08000168 /* EMC_XM2QUSEPADCTRL */ + 0x08000000 /* EMC_XM2DQSPADCTRL3 */ + 0x00000802 /* EMC_CTT_TERM_CTRL */ + 0x00000000 /* EMC_ZCAL_INTERVAL */ + 0x00000040 /* EMC_ZCAL_WAIT_CNT */ + 0x000c000c /* EMC_MRS_WAIT_CNT */ + 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ + 0x00000000 /* EMC_CTT */ + 0x00000000 /* EMC_CTT_DURATION */ + 0x80000287 /* EMC_DYN_SELF_REF_CONTROL */ + 0xe8000000 /* EMC_FBIO_SPARE */ + 0xff00ff00 /* EMC_CFG_RSV */ + >; + }; + timing-51000000 { + clock-frequency = <51000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-periodic-qrst; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-configuration = < + 0x00000002 /* EMC_RC */ + 0x0000000d /* EMC_RFC */ + 0x00000001 /* EMC_RAS */ + 0x00000000 /* EMC_RP */ + 0x00000002 /* EMC_R2W */ + 0x0000000a /* EMC_W2R */ + 0x00000005 /* EMC_R2P */ + 0x0000000b /* EMC_W2P */ + 0x00000000 /* EMC_RD_RCD */ + 0x00000000 /* EMC_WR_RCD */ + 0x00000003 /* EMC_RRD */ + 0x00000001 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000005 /* EMC_WDV */ + 0x00000005 /* EMC_QUSE */ + 0x00000004 /* EMC_QRST */ + 0x0000000a /* EMC_QSAFE */ + 0x0000000b /* EMC_RDV */ + 0x00000181 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x00000060 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002 /* EMC_PDEX2WR */ + 0x00000002 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000007 /* EMC_AR2PDEN */ + 0x0000000f /* EMC_RW2PDEN */ + 0x0000000e /* EMC_TXSR */ + 0x0000000e /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000003 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000004 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x0000018e /* EMC_TREFBW */ + 0x00000006 /* EMC_QUSE_EXTRA */ + 0x00000004 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x00004288 /* EMC_FBIO_CFG5 */ + 0x007800a4 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x000fc000 /* EMC_DLL_XFORM_DQS0 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS1 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS2 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS3 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS4 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS5 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS6 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS7 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ + 0x000002a0 /* EMC_XM2CMDPADCTRL */ + 0x0800211c /* EMC_XM2DQSPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x77fff884 /* EMC_XM2CLKPADCTRL */ + 0x01f1f108 /* EMC_XM2COMPPADCTRL */ + 0x05057404 /* EMC_XM2VTTGENPADCTRL */ + 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ + 0x08000168 /* EMC_XM2QUSEPADCTRL */ + 0x08000000 /* EMC_XM2DQSPADCTRL3 */ + 0x00000802 /* EMC_CTT_TERM_CTRL */ + 0x00000000 /* EMC_ZCAL_INTERVAL */ + 0x00000040 /* EMC_ZCAL_WAIT_CNT */ + 0x000c000c /* EMC_MRS_WAIT_CNT */ + 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ + 0x00000000 /* EMC_CTT */ + 0x00000000 /* EMC_CTT_DURATION */ + 0x8000040b /* EMC_DYN_SELF_REF_CONTROL */ + 0xe8000000 /* EMC_FBIO_SPARE */ + 0xff00ff00 /* EMC_CFG_RSV */ + >; + }; + timing-102000000 { + clock-frequency = <102000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-periodic-qrst; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-configuration = < + 0x00000004 /* EMC_RC */ + 0x0000001a /* EMC_RFC */ + 0x00000003 /* EMC_RAS */ + 0x00000001 /* EMC_RP */ + 0x00000002 /* EMC_R2W */ + 0x0000000a /* EMC_W2R */ + 0x00000005 /* EMC_R2P */ + 0x0000000b /* EMC_W2P */ + 0x00000001 /* EMC_RD_RCD */ + 0x00000001 /* EMC_WR_RCD */ + 0x00000003 /* EMC_RRD */ + 0x00000001 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000005 /* EMC_WDV */ + 0x00000005 /* EMC_QUSE */ + 0x00000004 /* EMC_QRST */ + 0x0000000a /* EMC_QSAFE */ + 0x0000000b /* EMC_RDV */ + 0x00000303 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x000000c0 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002 /* EMC_PDEX2WR */ + 0x00000002 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000007 /* EMC_AR2PDEN */ + 0x0000000f /* EMC_RW2PDEN */ + 0x0000001c /* EMC_TXSR */ + 0x0000001c /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000005 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000004 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x0000031c /* EMC_TREFBW */ + 0x00000006 /* EMC_QUSE_EXTRA */ + 0x00000004 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x00004288 /* EMC_FBIO_CFG5 */ + 0x007800a4 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x000fc000 /* EMC_DLL_XFORM_DQS0 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS1 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS2 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS3 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS4 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS5 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS6 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS7 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ + 0x000002a0 /* EMC_XM2CMDPADCTRL */ + 0x0800211c /* EMC_XM2DQSPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x77fff884 /* EMC_XM2CLKPADCTRL */ + 0x01f1f108 /* EMC_XM2COMPPADCTRL */ + 0x05057404 /* EMC_XM2VTTGENPADCTRL */ + 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ + 0x08000168 /* EMC_XM2QUSEPADCTRL */ + 0x08000000 /* EMC_XM2DQSPADCTRL3 */ + 0x00000802 /* EMC_CTT_TERM_CTRL */ + 0x00000000 /* EMC_ZCAL_INTERVAL */ + 0x00000040 /* EMC_ZCAL_WAIT_CNT */ + 0x000c000c /* EMC_MRS_WAIT_CNT */ + 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ + 0x00000000 /* EMC_CTT */ + 0x00000000 /* EMC_CTT_DURATION */ + 0x80000713 /* EMC_DYN_SELF_REF_CONTROL */ + 0xe8000000 /* EMC_FBIO_SPARE */ + 0xff00ff00 /* EMC_CFG_RSV */ + >; + }; + timing-204000000 { + clock-frequency = <204000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-periodic-qrst; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-configuration = < + 0x00000009 /* EMC_RC */ + 0x00000035 /* EMC_RFC */ + 0x00000007 /* EMC_RAS */ + 0x00000002 /* EMC_RP */ + 0x00000002 /* EMC_R2W */ + 0x0000000a /* EMC_W2R */ + 0x00000005 /* EMC_R2P */ + 0x0000000b /* EMC_W2P */ + 0x00000002 /* EMC_RD_RCD */ + 0x00000002 /* EMC_WR_RCD */ + 0x00000003 /* EMC_RRD */ + 0x00000001 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000005 /* EMC_WDV */ + 0x00000005 /* EMC_QUSE */ + 0x00000004 /* EMC_QRST */ + 0x0000000a /* EMC_QSAFE */ + 0x0000000b /* EMC_RDV */ + 0x00000607 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x00000181 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002 /* EMC_PDEX2WR */ + 0x00000002 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000007 /* EMC_AR2PDEN */ + 0x0000000f /* EMC_RW2PDEN */ + 0x00000038 /* EMC_TXSR */ + 0x00000038 /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000009 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000004 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x00000638 /* EMC_TREFBW */ + 0x00000006 /* EMC_QUSE_EXTRA */ + 0x00000006 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x00004288 /* EMC_FBIO_CFG5 */ + 0x004400a4 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x00080000 /* EMC_DLL_XFORM_DQS0 */ + 0x00080000 /* EMC_DLL_XFORM_DQS1 */ + 0x00080000 /* EMC_DLL_XFORM_DQS2 */ + 0x00080000 /* EMC_DLL_XFORM_DQS3 */ + 0x00080000 /* EMC_DLL_XFORM_DQS4 */ + 0x00080000 /* EMC_DLL_XFORM_DQS5 */ + 0x00080000 /* EMC_DLL_XFORM_DQS6 */ + 0x00080000 /* EMC_DLL_XFORM_DQS7 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x00080000 /* EMC_DLL_XFORM_DQ0 */ + 0x00080000 /* EMC_DLL_XFORM_DQ1 */ + 0x00080000 /* EMC_DLL_XFORM_DQ2 */ + 0x00080000 /* EMC_DLL_XFORM_DQ3 */ + 0x000002a0 /* EMC_XM2CMDPADCTRL */ + 0x0800211c /* EMC_XM2DQSPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x77fff884 /* EMC_XM2CLKPADCTRL */ + 0x01f1f108 /* EMC_XM2COMPPADCTRL */ + 0x05057404 /* EMC_XM2VTTGENPADCTRL */ + 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ + 0x08000168 /* EMC_XM2QUSEPADCTRL */ + 0x08000000 /* EMC_XM2DQSPADCTRL3 */ + 0x00000802 /* EMC_CTT_TERM_CTRL */ + 0x00020000 /* EMC_ZCAL_INTERVAL */ + 0x00000100 /* EMC_ZCAL_WAIT_CNT */ + 0x000c000c /* EMC_MRS_WAIT_CNT */ + 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ + 0x00000000 /* EMC_CTT */ + 0x00000000 /* EMC_CTT_DURATION */ + 0x80000d22 /* EMC_DYN_SELF_REF_CONTROL */ + 0xe8000000 /* EMC_FBIO_SPARE */ + 0xff00ff00 /* EMC_CFG_RSV */ + >; + }; + timing-400000000 { + clock-frequency = <400000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200000>; + nvidia,emc-mode-reset = <0x80000521>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-configuration = < + 0x00000012 /* EMC_RC */ + 0x00000066 /* EMC_RFC */ + 0x0000000c /* EMC_RAS */ + 0x00000004 /* EMC_RP */ + 0x00000003 /* EMC_R2W */ + 0x00000008 /* EMC_W2R */ + 0x00000002 /* EMC_R2P */ + 0x0000000a /* EMC_W2P */ + 0x00000004 /* EMC_RD_RCD */ + 0x00000004 /* EMC_WR_RCD */ + 0x00000002 /* EMC_RRD */ + 0x00000001 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000004 /* EMC_WDV */ + 0x00000006 /* EMC_QUSE */ + 0x00000004 /* EMC_QRST */ + 0x0000000a /* EMC_QSAFE */ + 0x0000000c /* EMC_RDV */ + 0x00000bf0 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x000002fc /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000001 /* EMC_PDEX2WR */ + 0x00000008 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000008 /* EMC_AR2PDEN */ + 0x0000000f /* EMC_RW2PDEN */ + 0x0000006c /* EMC_TXSR */ + 0x00000200 /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000010 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000004 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x00000c30 /* EMC_TREFBW */ + 0x00000000 /* EMC_QUSE_EXTRA */ + 0x00000004 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x00007088 /* EMC_FBIO_CFG5 */ + 0x001d0084 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x0003c000 /* EMC_DLL_XFORM_DQS0 */ + 0x0003c000 /* EMC_DLL_XFORM_DQS1 */ + 0x0003c000 /* EMC_DLL_XFORM_DQS2 */ + 0x0003c000 /* EMC_DLL_XFORM_DQS3 */ + 0x0003c000 /* EMC_DLL_XFORM_DQS4 */ + 0x0003c000 /* EMC_DLL_XFORM_DQS5 */ + 0x0003c000 /* EMC_DLL_XFORM_DQS6 */ + 0x0003c000 /* EMC_DLL_XFORM_DQS7 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x00048000 /* EMC_DLL_XFORM_DQ0 */ + 0x00048000 /* EMC_DLL_XFORM_DQ1 */ + 0x00048000 /* EMC_DLL_XFORM_DQ2 */ + 0x00048000 /* EMC_DLL_XFORM_DQ3 */ + 0x000002a0 /* EMC_XM2CMDPADCTRL */ + 0x0800013d /* EMC_XM2DQSPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x77fff884 /* EMC_XM2CLKPADCTRL */ + 0x01f1f508 /* EMC_XM2COMPPADCTRL */ + 0x05057404 /* EMC_XM2VTTGENPADCTRL */ + 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ + 0x080001e8 /* EMC_XM2QUSEPADCTRL */ + 0x08000021 /* EMC_XM2DQSPADCTRL3 */ + 0x00000802 /* EMC_CTT_TERM_CTRL */ + 0x00020000 /* EMC_ZCAL_INTERVAL */ + 0x00000100 /* EMC_ZCAL_WAIT_CNT */ + 0x0158000c /* EMC_MRS_WAIT_CNT */ + 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ + 0x00000000 /* EMC_CTT */ + 0x00000000 /* EMC_CTT_DURATION */ + 0x800018c8 /* EMC_DYN_SELF_REF_CONTROL */ + 0xe8000000 /* EMC_FBIO_SPARE */ + 0xff00ff89 /* EMC_CFG_RSV */ + >; + }; + timing-800000000 { + clock-frequency = <800000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200018>; + nvidia,emc-mode-reset = <0x80000d71>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-periodic-qrst; + nvidia,emc-configuration = < + 0x00000025 /* EMC_RC */ + 0x000000ce /* EMC_RFC */ + 0x0000001a /* EMC_RAS */ + 0x00000009 /* EMC_RP */ + 0x00000005 /* EMC_R2W */ + 0x0000000d /* EMC_W2R */ + 0x00000004 /* EMC_R2P */ + 0x00000013 /* EMC_W2P */ + 0x00000009 /* EMC_RD_RCD */ + 0x00000009 /* EMC_WR_RCD */ + 0x00000004 /* EMC_RRD */ + 0x00000001 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000007 /* EMC_WDV */ + 0x0000000a /* EMC_QUSE */ + 0x00000009 /* EMC_QRST */ + 0x0000000b /* EMC_QSAFE */ + 0x00000011 /* EMC_RDV */ + 0x00001820 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x00000608 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000003 /* EMC_PDEX2WR */ + 0x00000012 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x0000000f /* EMC_AR2PDEN */ + 0x00000018 /* EMC_RW2PDEN */ + 0x000000d8 /* EMC_TXSR */ + 0x00000200 /* EMC_TXSRDLL */ + 0x00000005 /* EMC_TCKE */ + 0x00000020 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000007 /* EMC_TCLKSTABLE */ + 0x00000008 /* EMC_TCLKSTOP */ + 0x00001860 /* EMC_TREFBW */ + 0x0000000b /* EMC_QUSE_EXTRA */ + 0x00000006 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x00005088 /* EMC_FBIO_CFG5 */ + 0xf0070191 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x0000800a /* EMC_DLL_XFORM_DQS0 */ + 0x0000000a /* EMC_DLL_XFORM_DQS1 */ + 0x0000000a /* EMC_DLL_XFORM_DQS2 */ + 0x0000000a /* EMC_DLL_XFORM_DQS3 */ + 0x0000000a /* EMC_DLL_XFORM_DQS4 */ + 0x0000000a /* EMC_DLL_XFORM_DQS5 */ + 0x0000000a /* EMC_DLL_XFORM_DQS6 */ + 0x0000000a /* EMC_DLL_XFORM_DQS7 */ + 0x00018000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00018000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00018000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00018000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00018000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00018000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00018000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00018000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x0000000a /* EMC_DLL_XFORM_DQ0 */ + 0x0000000a /* EMC_DLL_XFORM_DQ1 */ + 0x0000000a /* EMC_DLL_XFORM_DQ2 */ + 0x0000000a /* EMC_DLL_XFORM_DQ3 */ + 0x000002a0 /* EMC_XM2CMDPADCTRL */ + 0x0600013d /* EMC_XM2DQSPADCTRL2 */ + 0x22220000 /* EMC_XM2DQPADCTRL2 */ + 0x77fff884 /* EMC_XM2CLKPADCTRL */ + 0x01f1f501 /* EMC_XM2COMPPADCTRL */ + 0x07077404 /* EMC_XM2VTTGENPADCTRL */ + 0x54000000 /* EMC_XM2VTTGENPADCTRL2 */ + 0x080001e8 /* EMC_XM2QUSEPADCTRL */ + 0x08000021 /* EMC_XM2DQSPADCTRL3 */ + 0x00000802 /* EMC_CTT_TERM_CTRL */ + 0x00020000 /* EMC_ZCAL_INTERVAL */ + 0x00000100 /* EMC_ZCAL_WAIT_CNT */ + 0x00f0000c /* EMC_MRS_WAIT_CNT */ + 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ + 0x00000000 /* EMC_CTT */ + 0x00000000 /* EMC_CTT_DURATION */ + 0x8000308c /* EMC_DYN_SELF_REF_CONTROL */ + 0xe8000000 /* EMC_FBIO_SPARE */ + 0xff00ff49 /* EMC_CFG_RSV */ + >; + }; + }; + emc-timings-1 { + nvidia,ram-code = <1>; /* Hynix M RAM */ + timing-25500000 { + clock-frequency = <25500000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-periodic-qrst; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-configuration = < + 0x00000001 /* EMC_RC */ + 0x00000006 /* EMC_RFC */ + 0x00000000 /* EMC_RAS */ + 0x00000000 /* EMC_RP */ + 0x00000002 /* EMC_R2W */ + 0x0000000a /* EMC_W2R */ + 0x00000005 /* EMC_R2P */ + 0x0000000b /* EMC_W2P */ + 0x00000000 /* EMC_RD_RCD */ + 0x00000000 /* EMC_WR_RCD */ + 0x00000003 /* EMC_RRD */ + 0x00000001 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000005 /* EMC_WDV */ + 0x00000005 /* EMC_QUSE */ + 0x00000004 /* EMC_QRST */ + 0x0000000a /* EMC_QSAFE */ + 0x0000000b /* EMC_RDV */ + 0x000000c0 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x00000030 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002 /* EMC_PDEX2WR */ + 0x00000002 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000007 /* EMC_AR2PDEN */ + 0x0000000f /* EMC_RW2PDEN */ + 0x00000007 /* EMC_TXSR */ + 0x00000007 /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000002 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000004 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x000000c7 /* EMC_TREFBW */ + 0x00000006 /* EMC_QUSE_EXTRA */ + 0x00000004 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x00004288 /* EMC_FBIO_CFG5 */ + 0x007800a4 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x000fc000 /* EMC_DLL_XFORM_DQS0 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS1 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS2 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS3 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS4 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS5 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS6 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS7 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ + 0x000002a0 /* EMC_XM2CMDPADCTRL */ + 0x0800211c /* EMC_XM2DQSPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x77fff884 /* EMC_XM2CLKPADCTRL */ + 0x01f1f108 /* EMC_XM2COMPPADCTRL */ + 0x05057404 /* EMC_XM2VTTGENPADCTRL */ + 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ + 0x08000168 /* EMC_XM2QUSEPADCTRL */ + 0x08000000 /* EMC_XM2DQSPADCTRL3 */ + 0x00000802 /* EMC_CTT_TERM_CTRL */ + 0x00000000 /* EMC_ZCAL_INTERVAL */ + 0x00000040 /* EMC_ZCAL_WAIT_CNT */ + 0x000c000c /* EMC_MRS_WAIT_CNT */ + 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ + 0x00000000 /* EMC_CTT */ + 0x00000000 /* EMC_CTT_DURATION */ + 0x80000287 /* EMC_DYN_SELF_REF_CONTROL */ + 0xe8000000 /* EMC_FBIO_SPARE */ + 0xff00ff00 /* EMC_CFG_RSV */ + >; + }; + timing-51000000 { + clock-frequency = <51000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-periodic-qrst; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-configuration = < + 0x00000002 /* EMC_RC */ + 0x0000000d /* EMC_RFC */ + 0x00000001 /* EMC_RAS */ + 0x00000000 /* EMC_RP */ + 0x00000002 /* EMC_R2W */ + 0x0000000a /* EMC_W2R */ + 0x00000005 /* EMC_R2P */ + 0x0000000b /* EMC_W2P */ + 0x00000000 /* EMC_RD_RCD */ + 0x00000000 /* EMC_WR_RCD */ + 0x00000003 /* EMC_RRD */ + 0x00000001 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000005 /* EMC_WDV */ + 0x00000005 /* EMC_QUSE */ + 0x00000004 /* EMC_QRST */ + 0x0000000a /* EMC_QSAFE */ + 0x0000000b /* EMC_RDV */ + 0x00000181 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x00000060 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002 /* EMC_PDEX2WR */ + 0x00000002 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000007 /* EMC_AR2PDEN */ + 0x0000000f /* EMC_RW2PDEN */ + 0x0000000e /* EMC_TXSR */ + 0x0000000e /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000003 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000004 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x0000018e /* EMC_TREFBW */ + 0x00000006 /* EMC_QUSE_EXTRA */ + 0x00000004 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x00004288 /* EMC_FBIO_CFG5 */ + 0x007800a4 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x000fc000 /* EMC_DLL_XFORM_DQS0 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS1 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS2 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS3 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS4 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS5 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS6 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS7 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ + 0x000002a0 /* EMC_XM2CMDPADCTRL */ + 0x0800211c /* EMC_XM2DQSPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x77fff884 /* EMC_XM2CLKPADCTRL */ + 0x01f1f108 /* EMC_XM2COMPPADCTRL */ + 0x05057404 /* EMC_XM2VTTGENPADCTRL */ + 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ + 0x08000168 /* EMC_XM2QUSEPADCTRL */ + 0x08000000 /* EMC_XM2DQSPADCTRL3 */ + 0x00000802 /* EMC_CTT_TERM_CTRL */ + 0x00000000 /* EMC_ZCAL_INTERVAL */ + 0x00000040 /* EMC_ZCAL_WAIT_CNT */ + 0x000c000c /* EMC_MRS_WAIT_CNT */ + 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ + 0x00000000 /* EMC_CTT */ + 0x00000000 /* EMC_CTT_DURATION */ + 0x8000040b /* EMC_DYN_SELF_REF_CONTROL */ + 0xe8000000 /* EMC_FBIO_SPARE */ + 0xff00ff00 /* EMC_CFG_RSV */ + >; + }; + timing-102000000 { + clock-frequency = <102000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-periodic-qrst; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-configuration = < + 0x00000004 /* EMC_RC */ + 0x0000001a /* EMC_RFC */ + 0x00000003 /* EMC_RAS */ + 0x00000001 /* EMC_RP */ + 0x00000002 /* EMC_R2W */ + 0x0000000a /* EMC_W2R */ + 0x00000005 /* EMC_R2P */ + 0x0000000b /* EMC_W2P */ + 0x00000001 /* EMC_RD_RCD */ + 0x00000001 /* EMC_WR_RCD */ + 0x00000003 /* EMC_RRD */ + 0x00000001 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000005 /* EMC_WDV */ + 0x00000005 /* EMC_QUSE */ + 0x00000004 /* EMC_QRST */ + 0x0000000a /* EMC_QSAFE */ + 0x0000000b /* EMC_RDV */ + 0x00000303 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x000000c0 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002 /* EMC_PDEX2WR */ + 0x00000002 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000007 /* EMC_AR2PDEN */ + 0x0000000f /* EMC_RW2PDEN */ + 0x0000001c /* EMC_TXSR */ + 0x0000001c /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000005 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000004 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x0000031c /* EMC_TREFBW */ + 0x00000006 /* EMC_QUSE_EXTRA */ + 0x00000004 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x00004288 /* EMC_FBIO_CFG5 */ + 0x007800a4 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x000fc000 /* EMC_DLL_XFORM_DQS0 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS1 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS2 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS3 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS4 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS5 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS6 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS7 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ + 0x000002a0 /* EMC_XM2CMDPADCTRL */ + 0x0800211c /* EMC_XM2DQSPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x77fff884 /* EMC_XM2CLKPADCTRL */ + 0x01f1f108 /* EMC_XM2COMPPADCTRL */ + 0x05057404 /* EMC_XM2VTTGENPADCTRL */ + 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ + 0x08000168 /* EMC_XM2QUSEPADCTRL */ + 0x08000000 /* EMC_XM2DQSPADCTRL3 */ + 0x00000802 /* EMC_CTT_TERM_CTRL */ + 0x00000000 /* EMC_ZCAL_INTERVAL */ + 0x00000040 /* EMC_ZCAL_WAIT_CNT */ + 0x000c000c /* EMC_MRS_WAIT_CNT */ + 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ + 0x00000000 /* EMC_CTT */ + 0x00000000 /* EMC_CTT_DURATION */ + 0x80000713 /* EMC_DYN_SELF_REF_CONTROL */ + 0xe8000000 /* EMC_FBIO_SPARE */ + 0xff00ff00 /* EMC_CFG_RSV */ + >; + }; + timing-204000000 { + clock-frequency = <204000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-periodic-qrst; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-configuration = < + 0x00000009 /* EMC_RC */ + 0x00000035 /* EMC_RFC */ + 0x00000007 /* EMC_RAS */ + 0x00000002 /* EMC_RP */ + 0x00000002 /* EMC_R2W */ + 0x0000000a /* EMC_W2R */ + 0x00000005 /* EMC_R2P */ + 0x0000000b /* EMC_W2P */ + 0x00000002 /* EMC_RD_RCD */ + 0x00000002 /* EMC_WR_RCD */ + 0x00000003 /* EMC_RRD */ + 0x00000001 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000005 /* EMC_WDV */ + 0x00000005 /* EMC_QUSE */ + 0x00000004 /* EMC_QRST */ + 0x0000000a /* EMC_QSAFE */ + 0x0000000b /* EMC_RDV */ + 0x00000607 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x00000181 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002 /* EMC_PDEX2WR */ + 0x00000002 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000007 /* EMC_AR2PDEN */ + 0x0000000f /* EMC_RW2PDEN */ + 0x00000038 /* EMC_TXSR */ + 0x00000038 /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000009 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000004 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x00000638 /* EMC_TREFBW */ + 0x00000006 /* EMC_QUSE_EXTRA */ + 0x00000006 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x00004288 /* EMC_FBIO_CFG5 */ + 0x004400a4 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x00080000 /* EMC_DLL_XFORM_DQS0 */ + 0x00080000 /* EMC_DLL_XFORM_DQS1 */ + 0x00080000 /* EMC_DLL_XFORM_DQS2 */ + 0x00080000 /* EMC_DLL_XFORM_DQS3 */ + 0x00080000 /* EMC_DLL_XFORM_DQS4 */ + 0x00080000 /* EMC_DLL_XFORM_DQS5 */ + 0x00080000 /* EMC_DLL_XFORM_DQS6 */ + 0x00080000 /* EMC_DLL_XFORM_DQS7 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x00080000 /* EMC_DLL_XFORM_DQ0 */ + 0x00080000 /* EMC_DLL_XFORM_DQ1 */ + 0x00080000 /* EMC_DLL_XFORM_DQ2 */ + 0x00080000 /* EMC_DLL_XFORM_DQ3 */ + 0x000002a0 /* EMC_XM2CMDPADCTRL */ + 0x0800211c /* EMC_XM2DQSPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x77fff884 /* EMC_XM2CLKPADCTRL */ + 0x01f1f108 /* EMC_XM2COMPPADCTRL */ + 0x05057404 /* EMC_XM2VTTGENPADCTRL */ + 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ + 0x08000168 /* EMC_XM2QUSEPADCTRL */ + 0x08000000 /* EMC_XM2DQSPADCTRL3 */ + 0x00000802 /* EMC_CTT_TERM_CTRL */ + 0x00020000 /* EMC_ZCAL_INTERVAL */ + 0x00000100 /* EMC_ZCAL_WAIT_CNT */ + 0x000c000c /* EMC_MRS_WAIT_CNT */ + 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ + 0x00000000 /* EMC_CTT */ + 0x00000000 /* EMC_CTT_DURATION */ + 0x80000d22 /* EMC_DYN_SELF_REF_CONTROL */ + 0xe8000000 /* EMC_FBIO_SPARE */ + 0xff00ff00 /* EMC_CFG_RSV */ + >; + }; + timing-400000000 { + clock-frequency = <400000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200000>; + nvidia,emc-mode-reset = <0x80000521>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-configuration = < + 0x00000012 /* EMC_RC */ + 0x00000066 /* EMC_RFC */ + 0x0000000c /* EMC_RAS */ + 0x00000004 /* EMC_RP */ + 0x00000003 /* EMC_R2W */ + 0x00000008 /* EMC_W2R */ + 0x00000002 /* EMC_R2P */ + 0x0000000a /* EMC_W2P */ + 0x00000004 /* EMC_RD_RCD */ + 0x00000004 /* EMC_WR_RCD */ + 0x00000002 /* EMC_RRD */ + 0x00000001 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000004 /* EMC_WDV */ + 0x00000006 /* EMC_QUSE */ + 0x00000004 /* EMC_QRST */ + 0x0000000a /* EMC_QSAFE */ + 0x0000000c /* EMC_RDV */ + 0x00000bf0 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x000002fc /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000001 /* EMC_PDEX2WR */ + 0x00000008 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000008 /* EMC_AR2PDEN */ + 0x0000000f /* EMC_RW2PDEN */ + 0x0000006c /* EMC_TXSR */ + 0x00000200 /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000010 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000004 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x00000c30 /* EMC_TREFBW */ + 0x00000000 /* EMC_QUSE_EXTRA */ + 0x00000004 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x00007088 /* EMC_FBIO_CFG5 */ + 0x001d0084 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x0003c000 /* EMC_DLL_XFORM_DQS0 */ + 0x0003c000 /* EMC_DLL_XFORM_DQS1 */ + 0x0003c000 /* EMC_DLL_XFORM_DQS2 */ + 0x0003c000 /* EMC_DLL_XFORM_DQS3 */ + 0x0003c000 /* EMC_DLL_XFORM_DQS4 */ + 0x0003c000 /* EMC_DLL_XFORM_DQS5 */ + 0x0003c000 /* EMC_DLL_XFORM_DQS6 */ + 0x0003c000 /* EMC_DLL_XFORM_DQS7 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x00048000 /* EMC_DLL_XFORM_DQ0 */ + 0x00048000 /* EMC_DLL_XFORM_DQ1 */ + 0x00048000 /* EMC_DLL_XFORM_DQ2 */ + 0x00048000 /* EMC_DLL_XFORM_DQ3 */ + 0x000002a0 /* EMC_XM2CMDPADCTRL */ + 0x0800013d /* EMC_XM2DQSPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x77fff884 /* EMC_XM2CLKPADCTRL */ + 0x01f1f508 /* EMC_XM2COMPPADCTRL */ + 0x05057404 /* EMC_XM2VTTGENPADCTRL */ + 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ + 0x080001e8 /* EMC_XM2QUSEPADCTRL */ + 0x08000021 /* EMC_XM2DQSPADCTRL3 */ + 0x00000802 /* EMC_CTT_TERM_CTRL */ + 0x00020000 /* EMC_ZCAL_INTERVAL */ + 0x00000100 /* EMC_ZCAL_WAIT_CNT */ + 0x0158000c /* EMC_MRS_WAIT_CNT */ + 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ + 0x00000000 /* EMC_CTT */ + 0x00000000 /* EMC_CTT_DURATION */ + 0x800018c8 /* EMC_DYN_SELF_REF_CONTROL */ + 0xe8000000 /* EMC_FBIO_SPARE */ + 0xff00ff89 /* EMC_CFG_RSV */ + >; + }; + timing-800000000 { + clock-frequency = <800000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200018>; + nvidia,emc-mode-reset = <0x80000d71>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-periodic-qrst; + nvidia,emc-configuration = < + 0x00000025 /* EMC_RC */ + 0x000000ce /* EMC_RFC */ + 0x0000001a /* EMC_RAS */ + 0x00000009 /* EMC_RP */ + 0x00000005 /* EMC_R2W */ + 0x0000000d /* EMC_W2R */ + 0x00000004 /* EMC_R2P */ + 0x00000013 /* EMC_W2P */ + 0x00000009 /* EMC_RD_RCD */ + 0x00000009 /* EMC_WR_RCD */ + 0x00000004 /* EMC_RRD */ + 0x00000001 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000007 /* EMC_WDV */ + 0x0000000a /* EMC_QUSE */ + 0x00000009 /* EMC_QRST */ + 0x0000000b /* EMC_QSAFE */ + 0x00000011 /* EMC_RDV */ + 0x00001820 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x00000608 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000003 /* EMC_PDEX2WR */ + 0x00000012 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x0000000f /* EMC_AR2PDEN */ + 0x00000018 /* EMC_RW2PDEN */ + 0x000000d8 /* EMC_TXSR */ + 0x00000200 /* EMC_TXSRDLL */ + 0x00000005 /* EMC_TCKE */ + 0x00000020 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000007 /* EMC_TCLKSTABLE */ + 0x00000008 /* EMC_TCLKSTOP */ + 0x00001860 /* EMC_TREFBW */ + 0x0000000b /* EMC_QUSE_EXTRA */ + 0x00000006 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x00005088 /* EMC_FBIO_CFG5 */ + 0xf0070191 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x0000800a /* EMC_DLL_XFORM_DQS0 */ + 0x0000000a /* EMC_DLL_XFORM_DQS1 */ + 0x0000000a /* EMC_DLL_XFORM_DQS2 */ + 0x0000000a /* EMC_DLL_XFORM_DQS3 */ + 0x0000000a /* EMC_DLL_XFORM_DQS4 */ + 0x0000000a /* EMC_DLL_XFORM_DQS5 */ + 0x0000000a /* EMC_DLL_XFORM_DQS6 */ + 0x0000000a /* EMC_DLL_XFORM_DQS7 */ + 0x00018000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00018000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00018000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00018000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00018000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00018000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00018000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00018000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x0000000a /* EMC_DLL_XFORM_DQ0 */ + 0x0000000a /* EMC_DLL_XFORM_DQ1 */ + 0x0000000a /* EMC_DLL_XFORM_DQ2 */ + 0x0000000a /* EMC_DLL_XFORM_DQ3 */ + 0x000002a0 /* EMC_XM2CMDPADCTRL */ + 0x0600013d /* EMC_XM2DQSPADCTRL2 */ + 0x22220000 /* EMC_XM2DQPADCTRL2 */ + 0x77fff884 /* EMC_XM2CLKPADCTRL */ + 0x01f1f501 /* EMC_XM2COMPPADCTRL */ + 0x07077404 /* EMC_XM2VTTGENPADCTRL */ + 0x54000000 /* EMC_XM2VTTGENPADCTRL2 */ + 0x080001e8 /* EMC_XM2QUSEPADCTRL */ + 0x08000021 /* EMC_XM2DQSPADCTRL3 */ + 0x00000802 /* EMC_CTT_TERM_CTRL */ + 0x00020000 /* EMC_ZCAL_INTERVAL */ + 0x00000100 /* EMC_ZCAL_WAIT_CNT */ + 0x00f0000c /* EMC_MRS_WAIT_CNT */ + 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ + 0x00000000 /* EMC_CTT */ + 0x00000000 /* EMC_CTT_DURATION */ + 0x8000308c /* EMC_DYN_SELF_REF_CONTROL */ + 0xe8000000 /* EMC_FBIO_SPARE */ + 0xff00ff49 /* EMC_CFG_RSV */ + >; + }; + }; + emc-timings-2 { + nvidia,ram-code = <2>; /* Hynix A RAM */ + timing-25500000 { + clock-frequency = <25500000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-periodic-qrst; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-configuration = < + 0x00000001 /* EMC_RC */ + 0x00000007 /* EMC_RFC */ + 0x00000000 /* EMC_RAS */ + 0x00000000 /* EMC_RP */ + 0x00000002 /* EMC_R2W */ + 0x0000000a /* EMC_W2R */ + 0x00000005 /* EMC_R2P */ + 0x0000000b /* EMC_W2P */ + 0x00000000 /* EMC_RD_RCD */ + 0x00000000 /* EMC_WR_RCD */ + 0x00000003 /* EMC_RRD */ + 0x00000001 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000005 /* EMC_WDV */ + 0x00000005 /* EMC_QUSE */ + 0x00000004 /* EMC_QRST */ + 0x0000000a /* EMC_QSAFE */ + 0x0000000b /* EMC_RDV */ + 0x000000c0 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x00000030 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002 /* EMC_PDEX2WR */ + 0x00000002 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000007 /* EMC_AR2PDEN */ + 0x0000000f /* EMC_RW2PDEN */ + 0x00000008 /* EMC_TXSR */ + 0x00000008 /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000002 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000004 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x000000c7 /* EMC_TREFBW */ + 0x00000006 /* EMC_QUSE_EXTRA */ + 0x00000004 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x00004288 /* EMC_FBIO_CFG5 */ + 0x007800a4 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x000fc000 /* EMC_DLL_XFORM_DQS0 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS1 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS2 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS3 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS4 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS5 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS6 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS7 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ + 0x000002a0 /* EMC_XM2CMDPADCTRL */ + 0x0800211c /* EMC_XM2DQSPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x77fff884 /* EMC_XM2CLKPADCTRL */ + 0x01f1f108 /* EMC_XM2COMPPADCTRL */ + 0x05057404 /* EMC_XM2VTTGENPADCTRL */ + 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ + 0x08000168 /* EMC_XM2QUSEPADCTRL */ + 0x08000000 /* EMC_XM2DQSPADCTRL3 */ + 0x00000802 /* EMC_CTT_TERM_CTRL */ + 0x00000000 /* EMC_ZCAL_INTERVAL */ + 0x00000040 /* EMC_ZCAL_WAIT_CNT */ + 0x000c000c /* EMC_MRS_WAIT_CNT */ + 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ + 0x00000000 /* EMC_CTT */ + 0x00000000 /* EMC_CTT_DURATION */ + 0x80000287 /* EMC_DYN_SELF_REF_CONTROL */ + 0xe8000000 /* EMC_FBIO_SPARE */ + 0xff00ff00 /* EMC_CFG_RSV */ + >; + }; + timing-51000000 { + clock-frequency = <51000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-periodic-qrst; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-configuration = < + 0x00000002 /* EMC_RC */ + 0x0000000f /* EMC_RFC */ + 0x00000001 /* EMC_RAS */ + 0x00000000 /* EMC_RP */ + 0x00000002 /* EMC_R2W */ + 0x0000000a /* EMC_W2R */ + 0x00000005 /* EMC_R2P */ + 0x0000000b /* EMC_W2P */ + 0x00000000 /* EMC_RD_RCD */ + 0x00000000 /* EMC_WR_RCD */ + 0x00000003 /* EMC_RRD */ + 0x00000001 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000005 /* EMC_WDV */ + 0x00000005 /* EMC_QUSE */ + 0x00000004 /* EMC_QRST */ + 0x0000000a /* EMC_QSAFE */ + 0x0000000b /* EMC_RDV */ + 0x00000181 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x00000060 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002 /* EMC_PDEX2WR */ + 0x00000002 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000007 /* EMC_AR2PDEN */ + 0x0000000f /* EMC_RW2PDEN */ + 0x00000010 /* EMC_TXSR */ + 0x00000010 /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000003 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000004 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x0000018e /* EMC_TREFBW */ + 0x00000006 /* EMC_QUSE_EXTRA */ + 0x00000004 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x00004288 /* EMC_FBIO_CFG5 */ + 0x007800a4 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x000fc000 /* EMC_DLL_XFORM_DQS0 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS1 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS2 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS3 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS4 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS5 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS6 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS7 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ + 0x000002a0 /* EMC_XM2CMDPADCTRL */ + 0x0800211c /* EMC_XM2DQSPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x77fff884 /* EMC_XM2CLKPADCTRL */ + 0x01f1f108 /* EMC_XM2COMPPADCTRL */ + 0x05057404 /* EMC_XM2VTTGENPADCTRL */ + 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ + 0x08000168 /* EMC_XM2QUSEPADCTRL */ + 0x08000000 /* EMC_XM2DQSPADCTRL3 */ + 0x00000802 /* EMC_CTT_TERM_CTRL */ + 0x00000000 /* EMC_ZCAL_INTERVAL */ + 0x00000040 /* EMC_ZCAL_WAIT_CNT */ + 0x000c000c /* EMC_MRS_WAIT_CNT */ + 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ + 0x00000000 /* EMC_CTT */ + 0x00000000 /* EMC_CTT_DURATION */ + 0x8000040b /* EMC_DYN_SELF_REF_CONTROL */ + 0xe8000000 /* EMC_FBIO_SPARE */ + 0xff00ff00 /* EMC_CFG_RSV */ + >; + }; + timing-102000000 { + clock-frequency = <102000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-periodic-qrst; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-configuration = < + 0x00000004 /* EMC_RC */ + 0x0000001e /* EMC_RFC */ + 0x00000003 /* EMC_RAS */ + 0x00000001 /* EMC_RP */ + 0x00000002 /* EMC_R2W */ + 0x0000000a /* EMC_W2R */ + 0x00000005 /* EMC_R2P */ + 0x0000000b /* EMC_W2P */ + 0x00000001 /* EMC_RD_RCD */ + 0x00000001 /* EMC_WR_RCD */ + 0x00000003 /* EMC_RRD */ + 0x00000001 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000005 /* EMC_WDV */ + 0x00000005 /* EMC_QUSE */ + 0x00000004 /* EMC_QRST */ + 0x0000000a /* EMC_QSAFE */ + 0x0000000b /* EMC_RDV */ + 0x00000303 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x000000c0 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002 /* EMC_PDEX2WR */ + 0x00000002 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000007 /* EMC_AR2PDEN */ + 0x0000000f /* EMC_RW2PDEN */ + 0x00000020 /* EMC_TXSR */ + 0x00000020 /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000005 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000004 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x0000031c /* EMC_TREFBW */ + 0x00000006 /* EMC_QUSE_EXTRA */ + 0x00000004 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x00004288 /* EMC_FBIO_CFG5 */ + 0x007800a4 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x000fc000 /* EMC_DLL_XFORM_DQS0 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS1 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS2 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS3 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS4 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS5 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS6 */ + 0x000fc000 /* EMC_DLL_XFORM_DQS7 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ0 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ1 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ2 */ + 0x000fc000 /* EMC_DLL_XFORM_DQ3 */ + 0x000002a0 /* EMC_XM2CMDPADCTRL */ + 0x0800211c /* EMC_XM2DQSPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x77fff884 /* EMC_XM2CLKPADCTRL */ + 0x01f1f108 /* EMC_XM2COMPPADCTRL */ + 0x05057404 /* EMC_XM2VTTGENPADCTRL */ + 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ + 0x08000168 /* EMC_XM2QUSEPADCTRL */ + 0x08000000 /* EMC_XM2DQSPADCTRL3 */ + 0x00000802 /* EMC_CTT_TERM_CTRL */ + 0x00000000 /* EMC_ZCAL_INTERVAL */ + 0x00000040 /* EMC_ZCAL_WAIT_CNT */ + 0x000c000c /* EMC_MRS_WAIT_CNT */ + 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ + 0x00000000 /* EMC_CTT */ + 0x00000000 /* EMC_CTT_DURATION */ + 0x80000713 /* EMC_DYN_SELF_REF_CONTROL */ + 0xe8000000 /* EMC_FBIO_SPARE */ + 0xff00ff00 /* EMC_CFG_RSV */ + >; + }; + timing-204000000 { + clock-frequency = <204000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100003>; + nvidia,emc-mode-2 = <0x80200008>; + nvidia,emc-mode-reset = <0x80001221>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-periodic-qrst; + nvidia,emc-cfg-dyn-self-ref; + nvidia,emc-configuration = < + 0x00000009 /* EMC_RC */ + 0x0000003d /* EMC_RFC */ + 0x00000007 /* EMC_RAS */ + 0x00000002 /* EMC_RP */ + 0x00000002 /* EMC_R2W */ + 0x0000000a /* EMC_W2R */ + 0x00000005 /* EMC_R2P */ + 0x0000000b /* EMC_W2P */ + 0x00000002 /* EMC_RD_RCD */ + 0x00000002 /* EMC_WR_RCD */ + 0x00000003 /* EMC_RRD */ + 0x00000001 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000005 /* EMC_WDV */ + 0x00000005 /* EMC_QUSE */ + 0x00000004 /* EMC_QRST */ + 0x0000000a /* EMC_QSAFE */ + 0x0000000b /* EMC_RDV */ + 0x00000607 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x00000181 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002 /* EMC_PDEX2WR */ + 0x00000002 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000007 /* EMC_AR2PDEN */ + 0x0000000f /* EMC_RW2PDEN */ + 0x00000040 /* EMC_TXSR */ + 0x00000040 /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000009 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000004 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x00000638 /* EMC_TREFBW */ + 0x00000006 /* EMC_QUSE_EXTRA */ + 0x00000006 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x00004288 /* EMC_FBIO_CFG5 */ + 0x004400a4 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x00080000 /* EMC_DLL_XFORM_DQS0 */ + 0x00080000 /* EMC_DLL_XFORM_DQS1 */ + 0x00080000 /* EMC_DLL_XFORM_DQS2 */ + 0x00080000 /* EMC_DLL_XFORM_DQS3 */ + 0x00080000 /* EMC_DLL_XFORM_DQS4 */ + 0x00080000 /* EMC_DLL_XFORM_DQS5 */ + 0x00080000 /* EMC_DLL_XFORM_DQS6 */ + 0x00080000 /* EMC_DLL_XFORM_DQS7 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x00080000 /* EMC_DLL_XFORM_DQ0 */ + 0x00080000 /* EMC_DLL_XFORM_DQ1 */ + 0x00080000 /* EMC_DLL_XFORM_DQ2 */ + 0x00080000 /* EMC_DLL_XFORM_DQ3 */ + 0x000002a0 /* EMC_XM2CMDPADCTRL */ + 0x0800211c /* EMC_XM2DQSPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x77fff884 /* EMC_XM2CLKPADCTRL */ + 0x01f1f108 /* EMC_XM2COMPPADCTRL */ + 0x05057404 /* EMC_XM2VTTGENPADCTRL */ + 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ + 0x08000168 /* EMC_XM2QUSEPADCTRL */ + 0x08000000 /* EMC_XM2DQSPADCTRL3 */ + 0x00000802 /* EMC_CTT_TERM_CTRL */ + 0x00020000 /* EMC_ZCAL_INTERVAL */ + 0x00000100 /* EMC_ZCAL_WAIT_CNT */ + 0x000c000c /* EMC_MRS_WAIT_CNT */ + 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ + 0x00000000 /* EMC_CTT */ + 0x00000000 /* EMC_CTT_DURATION */ + 0x80000d22 /* EMC_DYN_SELF_REF_CONTROL */ + 0xe8000000 /* EMC_FBIO_SPARE */ + 0xff00ff00 /* EMC_CFG_RSV */ + >; + }; + timing-400000000 { + clock-frequency = <400000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200000>; + nvidia,emc-mode-reset = <0x80000521>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-configuration = < + 0x00000012 /* EMC_RC */ + 0x00000076 /* EMC_RFC */ + 0x0000000c /* EMC_RAS */ + 0x00000004 /* EMC_RP */ + 0x00000003 /* EMC_R2W */ + 0x00000008 /* EMC_W2R */ + 0x00000002 /* EMC_R2P */ + 0x0000000a /* EMC_W2P */ + 0x00000004 /* EMC_RD_RCD */ + 0x00000004 /* EMC_WR_RCD */ + 0x00000002 /* EMC_RRD */ + 0x00000001 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000004 /* EMC_WDV */ + 0x00000006 /* EMC_QUSE */ + 0x00000004 /* EMC_QRST */ + 0x0000000a /* EMC_QSAFE */ + 0x0000000c /* EMC_RDV */ + 0x00000bf0 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x000002fc /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000001 /* EMC_PDEX2WR */ + 0x00000008 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x00000008 /* EMC_AR2PDEN */ + 0x0000000f /* EMC_RW2PDEN */ + 0x0000007c /* EMC_TXSR */ + 0x00000200 /* EMC_TXSRDLL */ + 0x00000004 /* EMC_TCKE */ + 0x00000010 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000004 /* EMC_TCLKSTABLE */ + 0x00000005 /* EMC_TCLKSTOP */ + 0x00000c30 /* EMC_TREFBW */ + 0x00000000 /* EMC_QUSE_EXTRA */ + 0x00000004 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x00007088 /* EMC_FBIO_CFG5 */ + 0x001d0084 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x00044000 /* EMC_DLL_XFORM_DQS0 */ + 0x00044000 /* EMC_DLL_XFORM_DQS1 */ + 0x00044000 /* EMC_DLL_XFORM_DQS2 */ + 0x00044000 /* EMC_DLL_XFORM_DQS3 */ + 0x00044000 /* EMC_DLL_XFORM_DQS4 */ + 0x00044000 /* EMC_DLL_XFORM_DQS5 */ + 0x00044000 /* EMC_DLL_XFORM_DQS6 */ + 0x00044000 /* EMC_DLL_XFORM_DQS7 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x00058000 /* EMC_DLL_XFORM_DQ0 */ + 0x00058000 /* EMC_DLL_XFORM_DQ1 */ + 0x00058000 /* EMC_DLL_XFORM_DQ2 */ + 0x00058000 /* EMC_DLL_XFORM_DQ3 */ + 0x000002a0 /* EMC_XM2CMDPADCTRL */ + 0x0800013d /* EMC_XM2DQSPADCTRL2 */ + 0x00000000 /* EMC_XM2DQPADCTRL2 */ + 0x77fff884 /* EMC_XM2CLKPADCTRL */ + 0x01f1f508 /* EMC_XM2COMPPADCTRL */ + 0x05057404 /* EMC_XM2VTTGENPADCTRL */ + 0x54000007 /* EMC_XM2VTTGENPADCTRL2 */ + 0x080001e8 /* EMC_XM2QUSEPADCTRL */ + 0x08000021 /* EMC_XM2DQSPADCTRL3 */ + 0x00000802 /* EMC_CTT_TERM_CTRL */ + 0x00020000 /* EMC_ZCAL_INTERVAL */ + 0x00000100 /* EMC_ZCAL_WAIT_CNT */ + 0x0148000c /* EMC_MRS_WAIT_CNT */ + 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ + 0x00000000 /* EMC_CTT */ + 0x00000000 /* EMC_CTT_DURATION */ + 0x800018c8 /* EMC_DYN_SELF_REF_CONTROL */ + 0xe8000000 /* EMC_FBIO_SPARE */ + 0xff00ff89 /* EMC_CFG_RSV */ + >; + }; + timing-800000000 { + clock-frequency = <800000000>; + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200018>; + nvidia,emc-mode-reset = <0x80000d71>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-periodic-qrst; + nvidia,emc-configuration = < + 0x00000025 /* EMC_RC */ + 0x000000ee /* EMC_RFC */ + 0x0000001a /* EMC_RAS */ + 0x00000009 /* EMC_RP */ + 0x00000005 /* EMC_R2W */ + 0x0000000d /* EMC_W2R */ + 0x00000004 /* EMC_R2P */ + 0x00000013 /* EMC_W2P */ + 0x00000009 /* EMC_RD_RCD */ + 0x00000009 /* EMC_WR_RCD */ + 0x00000003 /* EMC_RRD */ + 0x00000001 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000007 /* EMC_WDV */ + 0x0000000a /* EMC_QUSE */ + 0x00000009 /* EMC_QRST */ + 0x0000000b /* EMC_QSAFE */ + 0x00000011 /* EMC_RDV */ + 0x00001820 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x00000608 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000003 /* EMC_PDEX2WR */ + 0x00000012 /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x0000000f /* EMC_AR2PDEN */ + 0x00000018 /* EMC_RW2PDEN */ + 0x000000f8 /* EMC_TXSR */ + 0x00000200 /* EMC_TXSRDLL */ + 0x00000005 /* EMC_TCKE */ + 0x00000020 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000007 /* EMC_TCLKSTABLE */ + 0x00000008 /* EMC_TCLKSTOP */ + 0x00001860 /* EMC_TREFBW */ + 0x0000000b /* EMC_QUSE_EXTRA */ + 0x00000006 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x00005088 /* EMC_FBIO_CFG5 */ + 0xf0070191 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x0000000c /* EMC_DLL_XFORM_DQS0 */ + 0x007fc00a /* EMC_DLL_XFORM_DQS1 */ + 0x00000008 /* EMC_DLL_XFORM_DQS2 */ + 0x0000000a /* EMC_DLL_XFORM_DQS3 */ + 0x0000000a /* EMC_DLL_XFORM_DQS4 */ + 0x0000000a /* EMC_DLL_XFORM_DQS5 */ + 0x0000000a /* EMC_DLL_XFORM_DQS6 */ + 0x0000000a /* EMC_DLL_XFORM_DQS7 */ + 0x00018000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00018000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00018000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00018000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00018000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00018000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00018000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00018000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x0000000a /* EMC_DLL_XFORM_DQ0 */ + 0x0000000c /* EMC_DLL_XFORM_DQ1 */ + 0x0000000a /* EMC_DLL_XFORM_DQ2 */ + 0x0000000a /* EMC_DLL_XFORM_DQ3 */ + 0x000002a0 /* EMC_XM2CMDPADCTRL */ + 0x0600013d /* EMC_XM2DQSPADCTRL2 */ + 0x22220000 /* EMC_XM2DQPADCTRL2 */ + 0x77fff884 /* EMC_XM2CLKPADCTRL */ + 0x01f1f501 /* EMC_XM2COMPPADCTRL */ + 0x07077404 /* EMC_XM2VTTGENPADCTRL */ + 0x54000000 /* EMC_XM2VTTGENPADCTRL2 */ + 0x080001e8 /* EMC_XM2QUSEPADCTRL */ + 0x0a000021 /* EMC_XM2DQSPADCTRL3 */ + 0x00000802 /* EMC_CTT_TERM_CTRL */ + 0x00020000 /* EMC_ZCAL_INTERVAL */ + 0x00000100 /* EMC_ZCAL_WAIT_CNT */ + 0x00d0000c /* EMC_MRS_WAIT_CNT */ + 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ + 0x00000000 /* EMC_CTT */ + 0x00000000 /* EMC_CTT_DURATION */ + 0x8000308c /* EMC_DYN_SELF_REF_CONTROL */ + 0xe8000000 /* EMC_FBIO_SPARE */ + 0xff00ff49 /* EMC_CFG_RSV */ + >; + }; + }; +}; +&state_default { + clk_32k_out_pa0 { + nvidia,pins = "clk_32k_out_pa0"; + nvidia,function = "blink"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + uart3_cts_n_pa1 { + nvidia,pins = "uart3_cts_n_pa1"; + nvidia,function = "uartc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap2_fs_pa2 { + nvidia,pins = "dap2_fs_pa2"; + nvidia,function = "i2s1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap2_sclk_pa3 { + nvidia,pins = "dap2_sclk_pa3"; + nvidia,function = "i2s1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap2_din_pa4 { + nvidia,pins = "dap2_din_pa4"; + nvidia,function = "i2s1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap2_dout_pa5 { + nvidia,pins = "dap2_dout_pa5"; + nvidia,function = "i2s1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc3_clk_pa6 { + nvidia,pins = "sdmmc3_clk_pa6"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc3_cmd_pa7 { + nvidia,pins = "sdmmc3_cmd_pa7"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_a17_pb0 { + nvidia,pins = "gmi_a17_pb0"; + nvidia,function = "spi4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_a18_pb1 { + nvidia,pins = "gmi_a18_pb1"; + nvidia,function = "spi4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_pwr0_pb2 { + nvidia,pins = "lcd_pwr0_pb2"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_pclk_pb3 { + nvidia,pins = "lcd_pclk_pb3"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc3_dat3_pb4 { + nvidia,pins = "sdmmc3_dat3_pb4"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc3_dat2_pb5 { + nvidia,pins = "sdmmc3_dat2_pb5"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc3_dat1_pb6 { + nvidia,pins = "sdmmc3_dat1_pb6"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc3_dat0_pb7 { + nvidia,pins = "sdmmc3_dat0_pb7"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + uart3_rts_n_pc0 { + nvidia,pins = "uart3_rts_n_pc0"; + nvidia,function = "uartc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_pwr1_pc1 { + nvidia,pins = "lcd_pwr1_pc1"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + uart2_txd_pc2 { + nvidia,pins = "uart2_txd_pc2"; + nvidia,function = "uartb"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + uart2_rxd_pc3 { + nvidia,pins = "uart2_rxd_pc3"; + nvidia,function = "uartb"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gen1_i2c_scl_pc4 { + nvidia,pins = "gen1_i2c_scl_pc4"; + nvidia,function = "i2c1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + gen1_i2c_sda_pc5 { + nvidia,pins = "gen1_i2c_sda_pc5"; + nvidia,function = "i2c1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + lcd_pwr2_pc6 { + nvidia,pins = "lcd_pwr2_pc6"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_wp_n_pc7 { + nvidia,pins = "gmi_wp_n_pc7"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc3_dat5_pd0 { + nvidia,pins = "sdmmc3_dat5_pd0"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc3_dat4_pd1 { + nvidia,pins = "sdmmc3_dat4_pd1"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_dc1_pd2 { + nvidia,pins = "lcd_dc1_pd2"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc3_dat6_pd3 { + nvidia,pins = "sdmmc3_dat6_pd3"; + nvidia,function = "spi4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc3_dat7_pd4 { + nvidia,pins = "sdmmc3_dat7_pd4"; + nvidia,function = "spi4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + vi_d1_pd5 { + nvidia,pins = "vi_d1_pd5"; + nvidia,function = "sdmmc2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + vi_vsync_pd6 { + nvidia,pins = "vi_vsync_pd6"; + nvidia,function = "ddr"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + vi_hsync_pd7 { + nvidia,pins = "vi_hsync_pd7"; + nvidia,function = "ddr"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_d0_pe0 { + nvidia,pins = "lcd_d0_pe0"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_d1_pe1 { + nvidia,pins = "lcd_d1_pe1"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_d2_pe2 { + nvidia,pins = "lcd_d2_pe2"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_d3_pe3 { + nvidia,pins = "lcd_d3_pe3"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_d4_pe4 { + nvidia,pins = "lcd_d4_pe4"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_d5_pe5 { + nvidia,pins = "lcd_d5_pe5"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_d6_pe6 { + nvidia,pins = "lcd_d6_pe6"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_d7_pe7 { + nvidia,pins = "lcd_d7_pe7"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_d8_pf0 { + nvidia,pins = "lcd_d8_pf0"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_d9_pf1 { + nvidia,pins = "lcd_d9_pf1"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_d10_pf2 { + nvidia,pins = "lcd_d10_pf2"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_d11_pf3 { + nvidia,pins = "lcd_d11_pf3"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_d12_pf4 { + nvidia,pins = "lcd_d12_pf4"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_d13_pf5 { + nvidia,pins = "lcd_d13_pf5"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_d14_pf6 { + nvidia,pins = "lcd_d14_pf6"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_d15_pf7 { + nvidia,pins = "lcd_d15_pf7"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_ad0_pg0 { + nvidia,pins = "gmi_ad0_pg0"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_ad1_pg1 { + nvidia,pins = "gmi_ad1_pg1"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_ad2_pg2 { + nvidia,pins = "gmi_ad2_pg2"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_ad3_pg3 { + nvidia,pins = "gmi_ad3_pg3"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_ad4_pg4 { + nvidia,pins = "gmi_ad4_pg4"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_ad5_pg5 { + nvidia,pins = "gmi_ad5_pg5"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_ad6_pg6 { + nvidia,pins = "gmi_ad6_pg6"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_ad7_pg7 { + nvidia,pins = "gmi_ad7_pg7"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_ad8_ph0 { + nvidia,pins = "gmi_ad8_ph0"; + nvidia,function = "pwm0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_ad9_ph1 { + nvidia,pins = "gmi_ad9_ph1"; + nvidia,function = "pwm1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_ad10_ph2 { + nvidia,pins = "gmi_ad10_ph2"; + nvidia,function = "pwm2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_ad11_ph3 { + nvidia,pins = "gmi_ad11_ph3"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_ad12_ph4 { + nvidia,pins = "gmi_ad12_ph4"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_ad13_ph5 { + nvidia,pins = "gmi_ad13_ph5"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_ad14_ph6 { + nvidia,pins = "gmi_ad14_ph6"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_wr_n_pi0 { + nvidia,pins = "gmi_wr_n_pi0"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_oe_n_pi1 { + nvidia,pins = "gmi_oe_n_pi1"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_dqs_pi2 { + nvidia,pins = "gmi_dqs_pi2"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_iordy_pi5 { + nvidia,pins = "gmi_iordy_pi5"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_cs7_n_pi6 { + nvidia,pins = "gmi_cs7_n_pi6"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_wait_pi7 { + nvidia,pins = "gmi_wait_pi7"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_de_pj1 { + nvidia,pins = "lcd_de_pj1"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_cs1_n_pj2 { + nvidia,pins = "gmi_cs1_n_pj2"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_hsync_pj3 { + nvidia,pins = "lcd_hsync_pj3"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_vsync_pj4 { + nvidia,pins = "lcd_vsync_pj4"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + uart2_cts_n_pj5 { + nvidia,pins = "uart2_cts_n_pj5"; + nvidia,function = "uartb"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + uart2_rts_n_pj6 { + nvidia,pins = "uart2_rts_n_pj6"; + nvidia,function = "uartb"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_a16_pj7 { + nvidia,pins = "gmi_a16_pj7"; + nvidia,function = "spi4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_adv_n_pk0 { + nvidia,pins = "gmi_adv_n_pk0"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_clk_pk1 { + nvidia,pins = "gmi_clk_pk1"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_cs2_n_pk3 { + nvidia,pins = "gmi_cs2_n_pk3"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_cs3_n_pk4 { + nvidia,pins = "gmi_cs3_n_pk4"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + spdif_out_pk5 { + nvidia,pins = "spdif_out_pk5"; + nvidia,function = "spdif"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + spdif_in_pk6 { + nvidia,pins = "spdif_in_pk6"; + nvidia,function = "spdif"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi_a19_pk7 { + nvidia,pins = "gmi_a19_pk7"; + nvidia,function = "spi4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + vi_d2_pl0 { + nvidia,pins = "vi_d2_pl0"; + nvidia,function = "sdmmc2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + vi_d3_pl1 { + nvidia,pins = "vi_d3_pl1"; + nvidia,function = "sdmmc2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + vi_d4_pl2 { + nvidia,pins = "vi_d4_pl2"; + nvidia,function = "vi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + vi_d5_pl3 { + nvidia,pins = "vi_d5_pl3"; + nvidia,function = "sdmmc2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + vi_d6_pl4 { + nvidia,pins = "vi_d6_pl4"; + nvidia,function = "vi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + vi_d7_pl5 { + nvidia,pins = "vi_d7_pl5"; + nvidia,function = "sdmmc2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + vi_d8_pl6 { + nvidia,pins = "vi_d8_pl6"; + nvidia,function = "sdmmc2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + vi_d9_pl7 { + nvidia,pins = "vi_d9_pl7"; + nvidia,function = "sdmmc2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_d16_pm0 { + nvidia,pins = "lcd_d16_pm0"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_d17_pm1 { + nvidia,pins = "lcd_d17_pm1"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_d18_pm2 { + nvidia,pins = "lcd_d18_pm2"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_d19_pm3 { + nvidia,pins = "lcd_d19_pm3"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_d20_pm4 { + nvidia,pins = "lcd_d20_pm4"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_d21_pm5 { + nvidia,pins = "lcd_d21_pm5"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_d22_pm6 { + nvidia,pins = "lcd_d22_pm6"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_d23_pm7 { + nvidia,pins = "lcd_d23_pm7"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap1_fs_pn0 { + nvidia,pins = "dap1_fs_pn0"; + nvidia,function = "i2s0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap1_din_pn1 { + nvidia,pins = "dap1_din_pn1"; + nvidia,function = "i2s0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap1_dout_pn2 { + nvidia,pins = "dap1_dout_pn2"; + nvidia,function = "i2s0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap1_sclk_pn3 { + nvidia,pins = "dap1_sclk_pn3"; + nvidia,function = "i2s0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_cs0_n_pn4 { + nvidia,pins = "lcd_cs0_n_pn4"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_sdout_pn5 { + nvidia,pins = "lcd_sdout_pn5"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_dc0_pn6 { + nvidia,pins = "lcd_dc0_pn6"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + hdmi_int_pn7 { + nvidia,pins = "hdmi_int_pn7"; + nvidia,function = "hdmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi_data7_po0 { + nvidia,pins = "ulpi_data7_po0"; + nvidia,function = "uarta"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi_data0_po1 { + nvidia,pins = "ulpi_data0_po1"; + nvidia,function = "uarta"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi_data1_po2 { + nvidia,pins = "ulpi_data1_po2"; + nvidia,function = "uarta"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi_data2_po3 { + nvidia,pins = "ulpi_data2_po3"; + nvidia,function = "uarta"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi_data3_po4 { + nvidia,pins = "ulpi_data3_po4"; + nvidia,function = "uarta"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi_data4_po5 { + nvidia,pins = "ulpi_data4_po5"; + nvidia,function = "uarta"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi_data5_po6 { + nvidia,pins = "ulpi_data5_po6"; + nvidia,function = "uarta"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi_data6_po7 { + nvidia,pins = "ulpi_data6_po7"; + nvidia,function = "uarta"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap3_fs_pp0 { + nvidia,pins = "dap3_fs_pp0"; + nvidia,function = "i2s2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap3_din_pp1 { + nvidia,pins = "dap3_din_pp1"; + nvidia,function = "i2s2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap3_dout_pp2 { + nvidia,pins = "dap3_dout_pp2"; + nvidia,function = "i2s2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap3_sclk_pp3 { + nvidia,pins = "dap3_sclk_pp3"; + nvidia,function = "i2s2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap4_fs_pp4 { + nvidia,pins = "dap4_fs_pp4"; + nvidia,function = "i2s3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap4_din_pp5 { + nvidia,pins = "dap4_din_pp5"; + nvidia,function = "i2s3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap4_dout_pp6 { + nvidia,pins = "dap4_dout_pp6"; + nvidia,function = "i2s3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap4_sclk_pp7 { + nvidia,pins = "dap4_sclk_pp7"; + nvidia,function = "i2s3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_col0_pq0 { + nvidia,pins = "kb_col0_pq0"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_col1_pq1 { + nvidia,pins = "kb_col1_pq1"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_col2_pq2 { + nvidia,pins = "kb_col2_pq2"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_col3_pq3 { + nvidia,pins = "kb_col3_pq3"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_col4_pq4 { + nvidia,pins = "kb_col4_pq4"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_col5_pq5 { + nvidia,pins = "kb_col5_pq5"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_col6_pq6 { + nvidia,pins = "kb_col6_pq6"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_col7_pq7 { + nvidia,pins = "kb_col7_pq7"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row0_pr0 { + nvidia,pins = "kb_row0_pr0"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row1_pr1 { + nvidia,pins = "kb_row1_pr1"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row2_pr2 { + nvidia,pins = "kb_row2_pr2"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row3_pr3 { + nvidia,pins = "kb_row3_pr3"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row4_pr4 { + nvidia,pins = "kb_row4_pr4"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row5_pr5 { + nvidia,pins = "kb_row5_pr5"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row6_pr6 { + nvidia,pins = "kb_row6_pr6"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row7_pr7 { + nvidia,pins = "kb_row7_pr7"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row8_ps0 { + nvidia,pins = "kb_row8_ps0"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row9_ps1 { + nvidia,pins = "kb_row9_ps1"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row10_ps2 { + nvidia,pins = "kb_row10_ps2"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row11_ps3 { + nvidia,pins = "kb_row11_ps3"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row12_ps4 { + nvidia,pins = "kb_row12_ps4"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row13_ps5 { + nvidia,pins = "kb_row13_ps5"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row14_ps6 { + nvidia,pins = "kb_row14_ps6"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb_row15_ps7 { + nvidia,pins = "kb_row15_ps7"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + vi_pclk_pt0 { + nvidia,pins = "vi_pclk_pt0"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + vi_mclk_pt1 { + nvidia,pins = "vi_mclk_pt1"; + nvidia,function = "vi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + vi_d10_pt2 { + nvidia,pins = "vi_d10_pt2"; + nvidia,function = "ddr"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + vi_d11_pt3 { + nvidia,pins = "vi_d11_pt3"; + nvidia,function = "ddr"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + vi_d0_pt4 { + nvidia,pins = "vi_d0_pt4"; + nvidia,function = "ddr"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gen2_i2c_scl_pt5 { + nvidia,pins = "gen2_i2c_scl_pt5"; + nvidia,function = "i2c2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + gen2_i2c_sda_pt6 { + nvidia,pins = "gen2_i2c_sda_pt6"; + nvidia,function = "i2c2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + sdmmc4_cmd_pt7 { + nvidia,pins = "sdmmc4_cmd_pt7"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,io-reset = ; + }; + pu0 { + nvidia,pins = "pu0"; + nvidia,function = "owr"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pu1 { + nvidia,pins = "pu1"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pu2 { + nvidia,pins = "pu2"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pu3 { + nvidia,pins = "pu3"; + nvidia,function = "pwm0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pu4 { + nvidia,pins = "pu4"; + nvidia,function = "pwm1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pu5 { + nvidia,pins = "pu5"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pu6 { + nvidia,pins = "pu6"; + nvidia,function = "pwm3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + jtag_rtck_pu7 { + nvidia,pins = "jtag_rtck_pu7"; + nvidia,function = "rtck"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pv0 { + nvidia,pins = "pv0"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pv1 { + nvidia,pins = "pv1"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pv2 { + nvidia,pins = "pv2"; + nvidia,function = "owr"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pv3 { + nvidia,pins = "pv3"; + nvidia,function = "clk_12m_out"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ddc_scl_pv4 { + nvidia,pins = "ddc_scl_pv4"; + nvidia,function = "i2c4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ddc_sda_pv5 { + nvidia,pins = "ddc_sda_pv5"; + nvidia,function = "i2c4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + crt_hsync_pv6 { + nvidia,pins = "crt_hsync_pv6"; + nvidia,function = "crt"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + crt_vsync_pv7 { + nvidia,pins = "crt_vsync_pv7"; + nvidia,function = "crt"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_cs1_n_pw0 { + nvidia,pins = "lcd_cs1_n_pw0"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_m1_pw1 { + nvidia,pins = "lcd_m1_pw1"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + spi2_cs1_n_pw2 { + nvidia,pins = "spi2_cs1_n_pw2"; + nvidia,function = "spi2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + clk1_out_pw4 { + nvidia,pins = "clk1_out_pw4"; + nvidia,function = "extperiph1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + clk2_out_pw5 { + nvidia,pins = "clk2_out_pw5"; + nvidia,function = "extperiph2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + uart3_txd_pw6 { + nvidia,pins = "uart3_txd_pw6"; + nvidia,function = "uartc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + uart3_rxd_pw7 { + nvidia,pins = "uart3_rxd_pw7"; + nvidia,function = "uartc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + spi2_sck_px2 { + nvidia,pins = "spi2_sck_px2"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + spi1_mosi_px4 { + nvidia,pins = "spi1_mosi_px4"; + nvidia,function = "spi1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + spi1_sck_px5 { + nvidia,pins = "spi1_sck_px5"; + nvidia,function = "spi1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + spi1_cs0_n_px6 { + nvidia,pins = "spi1_cs0_n_px6"; + nvidia,function = "spi1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + spi1_miso_px7 { + nvidia,pins = "spi1_miso_px7"; + nvidia,function = "spi1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi_clk_py0 { + nvidia,pins = "ulpi_clk_py0"; + nvidia,function = "uartd"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi_dir_py1 { + nvidia,pins = "ulpi_dir_py1"; + nvidia,function = "uartd"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi_nxt_py2 { + nvidia,pins = "ulpi_nxt_py2"; + nvidia,function = "uartd"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi_stp_py3 { + nvidia,pins = "ulpi_stp_py3"; + nvidia,function = "uartd"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc1_dat3_py4 { + nvidia,pins = "sdmmc1_dat3_py4"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc1_dat2_py5 { + nvidia,pins = "sdmmc1_dat2_py5"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc1_dat1_py6 { + nvidia,pins = "sdmmc1_dat1_py6"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc1_dat0_py7 { + nvidia,pins = "sdmmc1_dat0_py7"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc1_clk_pz0 { + nvidia,pins = "sdmmc1_clk_pz0"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc1_cmd_pz1 { + nvidia,pins = "sdmmc1_cmd_pz1"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_sdin_pz2 { + nvidia,pins = "lcd_sdin_pz2"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_wr_n_pz3 { + nvidia,pins = "lcd_wr_n_pz3"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lcd_sck_pz4 { + nvidia,pins = "lcd_sck_pz4"; + nvidia,function = "displaya"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sys_clk_req_pz5 { + nvidia,pins = "sys_clk_req_pz5"; + nvidia,function = "sysclk"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pwr_i2c_scl_pz6 { + nvidia,pins = "pwr_i2c_scl_pz6"; + nvidia,function = "i2cpwr"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + pwr_i2c_sda_pz7 { + nvidia,pins = "pwr_i2c_sda_pz7"; + nvidia,function = "i2cpwr"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + sdmmc4_dat0_paa0 { + nvidia,pins = "sdmmc4_dat0_paa0"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,io-reset = ; + }; + sdmmc4_dat1_paa1 { + nvidia,pins = "sdmmc4_dat1_paa1"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,io-reset = ; + }; + sdmmc4_dat2_paa2 { + nvidia,pins = "sdmmc4_dat2_paa2"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,io-reset = ; + }; + sdmmc4_dat3_paa3 { + nvidia,pins = "sdmmc4_dat3_paa3"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,io-reset = ; + }; + sdmmc4_dat4_paa4 { + nvidia,pins = "sdmmc4_dat4_paa4"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,io-reset = ; + }; + sdmmc4_dat5_paa5 { + nvidia,pins = "sdmmc4_dat5_paa5"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,io-reset = ; + }; + sdmmc4_dat6_paa6 { + nvidia,pins = "sdmmc4_dat6_paa6"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,io-reset = ; + }; + sdmmc4_dat7_paa7 { + nvidia,pins = "sdmmc4_dat7_paa7"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,io-reset = ; + }; + pbb0 { + nvidia,pins = "pbb0"; + nvidia,function = "i2s4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + cam_i2c_scl_pbb1 { + nvidia,pins = "cam_i2c_scl_pbb1"; + nvidia,function = "i2c3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + cam_i2c_sda_pbb2 { + nvidia,pins = "cam_i2c_sda_pbb2"; + nvidia,function = "i2c3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + pbb3 { + nvidia,pins = "pbb3"; + nvidia,function = "vgp3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pbb4 { + nvidia,pins = "pbb4"; + nvidia,function = "vgp4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pbb5 { + nvidia,pins = "pbb5"; + nvidia,function = "vgp5"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pbb6 { + nvidia,pins = "pbb6"; + nvidia,function = "vgp6"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pbb7 { + nvidia,pins = "pbb7"; + nvidia,function = "i2s4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + cam_mclk_pcc0 { + nvidia,pins = "cam_mclk_pcc0"; + nvidia,function = "vi_alt3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pcc1 { + nvidia,pins = "pcc1"; + nvidia,function = "i2s4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pcc2 { + nvidia,pins = "pcc2"; + nvidia,function = "i2s4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc4_rst_n_pcc3 { + nvidia,pins = "sdmmc4_rst_n_pcc3"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,io-reset = ; + }; + sdmmc4_clk_pcc4 { + nvidia,pins = "sdmmc4_clk_pcc4"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,io-reset = ; + }; + clk2_req_pcc5 { + nvidia,pins = "clk2_req_pcc5"; + nvidia,function = "dap"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pex_l2_rst_n_pcc6 { + nvidia,pins = "pex_l2_rst_n_pcc6"; + nvidia,function = "pcie"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pex_l2_clkreq_n_pcc7 { + nvidia,pins = "pex_l2_clkreq_n_pcc7"; + nvidia,function = "pcie"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pex_l0_prsnt_n_pdd0 { + nvidia,pins = "pex_l0_prsnt_n_pdd0"; + nvidia,function = "pcie"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pex_l0_rst_n_pdd1 { + nvidia,pins = "pex_l0_rst_n_pdd1"; + nvidia,function = "pcie"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pex_l0_clkreq_n_pdd2 { + nvidia,pins = "pex_l0_clkreq_n_pdd2"; + nvidia,function = "pcie"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pex_wake_n_pdd3 { + nvidia,pins = "pex_wake_n_pdd3"; + nvidia,function = "pcie"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pex_l1_prsnt_n_pdd4 { + nvidia,pins = "pex_l1_prsnt_n_pdd4"; + nvidia,function = "pcie"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pex_l1_rst_n_pdd5 { + nvidia,pins = "pex_l1_rst_n_pdd5"; + nvidia,function = "pcie"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pex_l1_clkreq_n_pdd6 { + nvidia,pins = "pex_l1_clkreq_n_pdd6"; + nvidia,function = "pcie"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pex_l2_prsnt_n_pdd7 { + nvidia,pins = "pex_l2_prsnt_n_pdd7"; + nvidia,function = "pcie"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + clk3_out_pee0 { + nvidia,pins = "clk3_out_pee0"; + nvidia,function = "extperiph3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + clk3_req_pee1 { + nvidia,pins = "clk3_req_pee1"; + nvidia,function = "dev3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + clk1_req_pee2 { + nvidia,pins = "clk1_req_pee2"; + nvidia,function = "dap"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + hdmi_cec_pee3 { + nvidia,pins = "hdmi_cec_pee3"; + nvidia,function = "cec"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + owr { + nvidia,pins = "owr"; + nvidia,function = "owr"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + drive_groups { + nvidia,pins = "drive_gma", + "drive_gmb", + "drive_gmc", + "drive_gmd"; + nvidia,pull-down-strength = <9>; + nvidia,pull-up-strength = <9>; + nvidia,slew-rate-rising = ; + nvidia,slew-rate-falling = ; + }; +}; From 94f13b9ca38643e1a1acf3b546d70dea24a17981 Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Wed, 4 Nov 2020 17:12:44 +0300 Subject: [PATCH 546/799] ARM: tegra: acer-a500: Correct thermal zone names Rename thermal zones in order fix dt_binding_check warning telling that names do not match the expected pattern. Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra20-acer-a500-picasso.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts b/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts index a0b829738e8f..372cc1b17eaf 100644 --- a/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts +++ b/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts @@ -1020,14 +1020,14 @@ }; thermal-zones { - nct1008-local { + skin-thermal { polling-delay-passive = <1000>; /* milliseconds */ polling-delay = <0>; /* milliseconds */ thermal-sensors = <&nct1008 0>; }; - nct1008-remote { + cpu-thermal { polling-delay-passive = <1000>; /* milliseconds */ polling-delay = <5000>; /* milliseconds */ From 5b0455f82b791de3b76bfd220f63dae1ea6b2747 Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Wed, 4 Nov 2020 17:12:45 +0300 Subject: [PATCH 547/799] ARM: tegra: acer-a500: Add power-supply to lvds-encoder node The lvds-encoder binding now supports power-supply property, let's specify it in the device-tree for completeness. Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra20-acer-a500-picasso.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts b/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts index 372cc1b17eaf..dd6fb134ee39 100644 --- a/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts +++ b/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts @@ -907,6 +907,7 @@ compatible = "ti,sn75lvds83", "lvds-encoder"; powerdown-gpios = <&gpio TEGRA_GPIO(B, 2) GPIO_ACTIVE_LOW>; + power-supply = <&vdd_3v3_sys>; ports { #address-cells = <1>; From 8857779a9faba5789ad30ca1f944a17aaa747056 Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Wed, 4 Nov 2020 17:12:46 +0300 Subject: [PATCH 548/799] ARM: tegra: nexus7: Correct thermal zone names Rename thermal zones in order fix dt_binding_check warning telling that names do not match the expected pattern. Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi index 88ca03f57b3b..fa6bbec7cbc4 100644 --- a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi +++ b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi @@ -1240,14 +1240,14 @@ }; thermal-zones { - nct72-local { + skin-thermal { polling-delay-passive = <1000>; /* milliseconds */ polling-delay = <0>; /* milliseconds */ thermal-sensors = <&nct72 0>; }; - nct72-remote { + cpu-thermal { polling-delay-passive = <1000>; /* milliseconds */ polling-delay = <5000>; /* milliseconds */ From 2b22393b27670b45a2c870bce3df6579efd9a86a Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Wed, 4 Nov 2020 17:12:47 +0300 Subject: [PATCH 549/799] ARM: tegra: nexus7: Improve CPU passive-cooling threshold The current CPU thermal limit is a bit inappropriate for Nexus 7 once device is getting used on a daily bases. For example, currently it's may be impossible to watch a hardware accelerated 720p video without hitting a severe CPU throttling, which ruins user experience. This patch improves the thermal throttling thresholds. In my experience setting CPU thermal threshold to 57C provides the most reasonable result, where device is a bit warm under constant load and not getting overly hot, in the same time performance is okay. Let's bump the passive-cooling threshold from 50C to 57C and also lower the thermal hysteresis to 0.2C in order to make throttling more reactive. Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi index fa6bbec7cbc4..8d49860b135b 100644 --- a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi +++ b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi @@ -1255,9 +1255,9 @@ trips { trip0: cpu-alert0 { - /* start throttling at 50C */ - temperature = <50000>; - hysteresis = <3000>; + /* throttle at 57C until temperature drops to 56.8C */ + temperature = <57000>; + hysteresis = <200>; type = "passive"; }; From 810719453c623e6393cb0b1ca4e41efa08002c9d Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Wed, 4 Nov 2020 17:12:48 +0300 Subject: [PATCH 550/799] ARM: tegra: nexus7: Add power-supply to lvds-encoder node The lvds-encoder binding now supports power-supply property, let's specify it in the device-tree for completeness. Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi index 8d49860b135b..f8a531350998 100644 --- a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi +++ b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi @@ -1145,6 +1145,7 @@ compatible = "ti,sn75lvds83", "lvds-encoder"; powerdown-gpios = <&gpio TEGRA_GPIO(N, 6) GPIO_ACTIVE_LOW>; + power-supply = <&vdd_3v3_sys>; ports { #address-cells = <1>; From b8ae17150696a3f0f40c91d61103b74884e7ba0a Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Wed, 4 Nov 2020 17:12:49 +0300 Subject: [PATCH 551/799] ARM: tegra: nexus7: Rename gpio-hog nodes Devicetree schema now requires gpio-hog nodes to have a certain naming pattern, like a -hog suffix. This patch fixes dtbs_check warnings about the names. Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi | 4 ++-- arch/arm/boot/dts/tegra30-asus-nexus7-grouper-maxim-pmic.dtsi | 2 +- arch/arm/boot/dts/tegra30-asus-nexus7-tilapia.dtsi | 2 +- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi index f8a531350998..8def1d2e34f9 100644 --- a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi +++ b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi @@ -75,7 +75,7 @@ }; gpio@6000d000 { - init-mode { + init-mode-hog { gpio-hog; gpios = , , @@ -83,7 +83,7 @@ output-low; }; - init-low-power-mode { + init-low-power-mode-hog { gpio-hog; gpios = ; input; diff --git a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-maxim-pmic.dtsi b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-maxim-pmic.dtsi index b25b3fa90ac6..17b6682ffce8 100644 --- a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-maxim-pmic.dtsi +++ b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-maxim-pmic.dtsi @@ -29,7 +29,7 @@ }; }; - cpu-pwr-req { + cpu-pwr-req-hog { gpio-hog; gpios = <6 GPIO_ACTIVE_HIGH>; input; diff --git a/arch/arm/boot/dts/tegra30-asus-nexus7-tilapia.dtsi b/arch/arm/boot/dts/tegra30-asus-nexus7-tilapia.dtsi index e3da89f1941a..a681ad51fddd 100644 --- a/arch/arm/boot/dts/tegra30-asus-nexus7-tilapia.dtsi +++ b/arch/arm/boot/dts/tegra30-asus-nexus7-tilapia.dtsi @@ -23,7 +23,7 @@ }; gpio@6000d000 { - init-mode-3g { + init-mode-3g-hog { gpio-hog; gpios = , , From a21f18a993c56566db94ba836684bc32c070a82c Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Wed, 4 Nov 2020 17:12:51 +0300 Subject: [PATCH 552/799] ARM: tegra: nexus7: Use panel-lvds as the only panel compatible Depending on a driver probe order, panel-simple driver may probe first, which results in this error: panel-simple display-panel: Reject override mode: panel has a fixed mode We don't want to use panel-simple anyways because customized timings are preferred for Nexus 7, hence remove the panel-simple compatibles from the panel node. Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- .../boot/dts/tegra30-asus-nexus7-grouper-common.dtsi | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi index 8def1d2e34f9..ac1c1a63eb0e 100644 --- a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi +++ b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi @@ -1073,8 +1073,16 @@ }; display-panel { - compatible = "hydis,hv070wx2-1e0", "chunghwa,claa070wp03xg", - "panel-lvds"; + /* + * Nexus 7 supports two compatible panel models: + * + * 1. hydis,hv070wx2-1e0 + * 2. chunghwa,claa070wp03xg + * + * We want to use timing which is optimized for Nexus 7, + * hence we need to customize the timing. + */ + compatible = "panel-lvds"; power-supply = <&vdd_pnl>; backlight = <&backlight>; From bd7cd7e05a42491469ca19861da44abc3168cf5f Mon Sep 17 00:00:00 2001 From: Jon Hunter Date: Wed, 11 Nov 2020 10:38:47 +0000 Subject: [PATCH 553/799] ARM: tegra: Populate OPP table for Tegra20 Ventana Commit 9ce274630495 ("cpufreq: tegra20: Use generic cpufreq-dt driver (Tegra30 supported now)") update the Tegra20 CPUFREQ driver to use the generic CPUFREQ device-tree driver. Since this change CPUFREQ support on the Tegra20 Ventana platform has been broken because the necessary device-tree nodes with the operating point information are not populated for this platform. Fix this by updating device-tree for Venata to include the operating point informration for Tegra20. Fixes: 9ce274630495 ("cpufreq: tegra20: Use generic cpufreq-dt driver (Tegra30 supported now)") Cc: stable@vger.kernel.org Signed-off-by: Jon Hunter Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra20-ventana.dts | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm/boot/dts/tegra20-ventana.dts b/arch/arm/boot/dts/tegra20-ventana.dts index b158771ac0b7..055334ae3d28 100644 --- a/arch/arm/boot/dts/tegra20-ventana.dts +++ b/arch/arm/boot/dts/tegra20-ventana.dts @@ -3,6 +3,7 @@ #include #include "tegra20.dtsi" +#include "tegra20-cpu-opp.dtsi" / { model = "NVIDIA Tegra20 Ventana evaluation board"; @@ -592,6 +593,16 @@ #clock-cells = <0>; }; + cpus { + cpu0: cpu@0 { + operating-points-v2 = <&cpu0_opp_table>; + }; + + cpu@1 { + operating-points-v2 = <&cpu0_opp_table>; + }; + }; + gpio-keys { compatible = "gpio-keys"; From 37ac8c4c04c9441fe05f4215b330775b00df7a99 Mon Sep 17 00:00:00 2001 From: Nicolas Chauvet Date: Sun, 27 Sep 2020 17:09:51 +0200 Subject: [PATCH 554/799] ARM: tegra: Add missing gpu-throt-level to Tegra124 soctherm On Jetson TK1 the following message can be seen: tegra_soctherm 700e2000.thermal-sensor: throttle-cfg: heavy: no throt prop or invalid prop This patch will fix the invalid prop issue according to the binding. Signed-off-by: Nicolas Chauvet Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra124.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi index 64f488ba1e72..a0fa5821a232 100644 --- a/arch/arm/boot/dts/tegra124.dtsi +++ b/arch/arm/boot/dts/tegra124.dtsi @@ -910,6 +910,7 @@ throttle_heavy: heavy { nvidia,priority = <100>; nvidia,cpu-throt-percent = <85>; + nvidia,gpu-throt-level = ; #cooling-cells = <2>; }; From 252cc72af6a2017dae340b4136124d3e625e4e0f Mon Sep 17 00:00:00 2001 From: Nicolas Chauvet Date: Sun, 27 Sep 2020 17:09:52 +0200 Subject: [PATCH 555/799] ARM: tegra: Add missing hot temperatures to Tegra124 thermal-zones According to dmesg, thermal-zones for mem and cpu are missing hot temperatures properties. throttrip: pll: missing hot temperature ... throttrip: mem: missing hot temperature ... Adding them will clear the messages. Signed-off-by: Nicolas Chauvet Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra124.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi index a0fa5821a232..c71d597ace01 100644 --- a/arch/arm/boot/dts/tegra124.dtsi +++ b/arch/arm/boot/dts/tegra124.dtsi @@ -1248,6 +1248,11 @@ hysteresis = <0>; type = "critical"; }; + mem-throttle-trip { + temperature = <99000>; + hysteresis = <1000>; + type = "hot"; + }; }; cooling-maps { @@ -1299,6 +1304,11 @@ hysteresis = <0>; type = "critical"; }; + pllx-throttle-trip { + temperature = <99000>; + hysteresis = <1000>; + type = "hot"; + }; }; cooling-maps { From 17401ce98ec6105db8e351c12735b6cc20d73d7e Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 20 Nov 2020 16:18:08 +0100 Subject: [PATCH 556/799] ARM: tegra: Hook up edp interrupt on Tegra124 SOCTHERM For some reason this was never hooked up. Do it now so that over-current interrupts can be logged. Reported-by: Nicolas Chauvet Suggested-by: Jon Hunter Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra124.dtsi | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi index c71d597ace01..27fb6a49118f 100644 --- a/arch/arm/boot/dts/tegra124.dtsi +++ b/arch/arm/boot/dts/tegra124.dtsi @@ -898,7 +898,9 @@ reg = <0x0 0x700e2000 0x0 0x600>, /* SOC_THERM reg_base */ <0x0 0x60006000 0x0 0x400>; /* CAR reg_base */ reg-names = "soctherm-reg", "car-reg"; - interrupts = ; + interrupts = , + ; + interrupt-names = "thermal", "edp"; clocks = <&tegra_car TEGRA124_CLK_TSENSOR>, <&tegra_car TEGRA124_CLK_SOC_THERM>; clock-names = "tsensor", "soctherm"; From 6fb123f1f5a42136161b7782d9635a684f3036d2 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 20 Nov 2020 21:27:12 +0100 Subject: [PATCH 557/799] ARM: tegra: Properly align clocks for SOCTHERM Entries on subsequent lines should be aligned with the entry on the first line. Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra124.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi index 27fb6a49118f..d7001b27c3e6 100644 --- a/arch/arm/boot/dts/tegra124.dtsi +++ b/arch/arm/boot/dts/tegra124.dtsi @@ -902,7 +902,7 @@ ; interrupt-names = "thermal", "edp"; clocks = <&tegra_car TEGRA124_CLK_TSENSOR>, - <&tegra_car TEGRA124_CLK_SOC_THERM>; + <&tegra_car TEGRA124_CLK_SOC_THERM>; clock-names = "tsensor", "soctherm"; resets = <&tegra_car 78>; reset-names = "soctherm"; From 8b809ba66c29abb0203d43118c31027e43e43648 Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Mon, 23 Nov 2020 03:27:16 +0300 Subject: [PATCH 558/799] ARM: tegra: Correct EMC registers size in Tegra20 device-tree Fix the size of Tegra20 EMC registers, which should be twice bigger. Acked-by: Krzysztof Kozlowski Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra20.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi index 72a4211a618f..9347f7789245 100644 --- a/arch/arm/boot/dts/tegra20.dtsi +++ b/arch/arm/boot/dts/tegra20.dtsi @@ -634,7 +634,7 @@ memory-controller@7000f400 { compatible = "nvidia,tegra20-emc"; - reg = <0x7000f400 0x200>; + reg = <0x7000f400 0x400>; interrupts = ; clocks = <&tegra_car TEGRA20_CLK_EMC>; #address-cells = <1>; From dd2a21d0930b3f5b8d5643c8d41008f8f2557d73 Mon Sep 17 00:00:00 2001 From: Sowjanya Komatineni Date: Mon, 23 Nov 2020 12:17:20 -0800 Subject: [PATCH 559/799] ARM: tegra: Change order of SATA resets for Tegra124 Tegra AHCI dt-binding doc is converted from text based to yaml based. dtbs_check valdiation strictly follows reset-names order specified in yaml dt-binding. Tegra124 thru Tegra210 has 3 resets sata, sata-oob and sata-cold. Tegra186 has 2 resets sata and sata-cold. This patch changes order of SATA resets to maintain proper resets order for commonly available resets across Tegra124 thru Tegra186 for dtbs_check to pass. Signed-off-by: Sowjanya Komatineni Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra124.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi index d7001b27c3e6..e61e68a0bb58 100644 --- a/arch/arm/boot/dts/tegra124.dtsi +++ b/arch/arm/boot/dts/tegra124.dtsi @@ -650,9 +650,9 @@ <&tegra_car TEGRA124_CLK_PLL_E>; clock-names = "sata", "sata-oob", "cml1", "pll_e"; resets = <&tegra_car 124>, - <&tegra_car 123>, - <&tegra_car 129>; - reset-names = "sata", "sata-oob", "sata-cold"; + <&tegra_car 129>, + <&tegra_car 123>; + reset-names = "sata", "sata-cold", "sata-oob"; status = "disabled"; }; From d3e815eaab582398ac2257d73399c8cf741bf64b Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Mon, 16 Nov 2020 22:48:27 +0300 Subject: [PATCH 560/799] ARM: tegra: acer-a500: Add Embedded Controller This patch adds device-tree node for the Embedded Controller which is found on the Picasso board. The Embedded Controller itself is ENE KB930, it provides functions like battery-gauge/LED/GPIO/etc and it uses firmware that is specifically customized for the Acer A500 device. Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra20-acer-a500-picasso.dts | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts b/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts index dd6fb134ee39..9dafd3d57bf7 100644 --- a/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts +++ b/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts @@ -512,6 +512,16 @@ reg = <1>; #address-cells = <1>; #size-cells = <0>; + + embedded-controller@58 { + compatible = "acer,a500-iconia-ec", "ene,kb930"; + reg = <0x58>; + + system-power-controller; + + monitored-battery = <&bat1010>; + power-supplies = <&mains>; + }; }; }; @@ -794,6 +804,13 @@ default-brightness-level = <20>; }; + bat1010: battery-2s1p { + compatible = "simple-battery"; + charge-full-design-microamp-hours = <3260000>; + energy-full-design-microwatt-hours = <24000000>; + operating-range-celsius = <0 40>; + }; + /* PMIC has a built-in 32KHz oscillator which is used by PMC */ clk32k_in: clock@0 { compatible = "fixed-clock"; From 30b81e77a051e50c1b8d5f3bb697e915231d89a8 Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Mon, 23 Nov 2020 03:27:17 +0300 Subject: [PATCH 561/799] ARM: tegra: Add interconnect properties to Tegra20 device-tree Add interconnect properties to the Memory Controller, External Memory Controller and the Display Controller nodes in order to describe hardware interconnection. Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra20.dtsi | 26 +++++++++++++++++++++++++- 1 file changed, 25 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi index 9347f7789245..2e1304493f7d 100644 --- a/arch/arm/boot/dts/tegra20.dtsi +++ b/arch/arm/boot/dts/tegra20.dtsi @@ -111,6 +111,17 @@ nvidia,head = <0>; + interconnects = <&mc TEGRA20_MC_DISPLAY0A &emc>, + <&mc TEGRA20_MC_DISPLAY0B &emc>, + <&mc TEGRA20_MC_DISPLAY1B &emc>, + <&mc TEGRA20_MC_DISPLAY0C &emc>, + <&mc TEGRA20_MC_DISPLAYHC &emc>; + interconnect-names = "wina", + "winb", + "winb-vfilter", + "winc", + "cursor"; + rgb { status = "disabled"; }; @@ -128,6 +139,17 @@ nvidia,head = <1>; + interconnects = <&mc TEGRA20_MC_DISPLAY0AB &emc>, + <&mc TEGRA20_MC_DISPLAY0BB &emc>, + <&mc TEGRA20_MC_DISPLAY1BB &emc>, + <&mc TEGRA20_MC_DISPLAY0CB &emc>, + <&mc TEGRA20_MC_DISPLAYHCB &emc>; + interconnect-names = "wina", + "winb", + "winb-vfilter", + "winc", + "cursor"; + rgb { status = "disabled"; }; @@ -630,15 +652,17 @@ interrupts = ; #reset-cells = <1>; #iommu-cells = <0>; + #interconnect-cells = <1>; }; - memory-controller@7000f400 { + emc: memory-controller@7000f400 { compatible = "nvidia,tegra20-emc"; reg = <0x7000f400 0x400>; interrupts = ; clocks = <&tegra_car TEGRA20_CLK_EMC>; #address-cells = <1>; #size-cells = <0>; + #interconnect-cells = <0>; }; fuse@7000f800 { From 69ea8fa77f1c0ce2a726ab283db2472d8a4c3cb6 Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Mon, 23 Nov 2020 03:27:18 +0300 Subject: [PATCH 562/799] ARM: tegra: Add interconnect properties to Tegra30 device-tree Add interconnect properties to the Memory Controller, External Memory Controller and the Display Controller nodes in order to describe hardware interconnection. Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra30.dtsi | 27 ++++++++++++++++++++++++++- 1 file changed, 26 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi index aeae8c092d41..2caf6cc6f4b1 100644 --- a/arch/arm/boot/dts/tegra30.dtsi +++ b/arch/arm/boot/dts/tegra30.dtsi @@ -210,6 +210,17 @@ nvidia,head = <0>; + interconnects = <&mc TEGRA30_MC_DISPLAY0A &emc>, + <&mc TEGRA30_MC_DISPLAY0B &emc>, + <&mc TEGRA30_MC_DISPLAY1B &emc>, + <&mc TEGRA30_MC_DISPLAY0C &emc>, + <&mc TEGRA30_MC_DISPLAYHC &emc>; + interconnect-names = "wina", + "winb", + "winb-vfilter", + "winc", + "cursor"; + rgb { status = "disabled"; }; @@ -229,6 +240,17 @@ nvidia,head = <1>; + interconnects = <&mc TEGRA30_MC_DISPLAY0AB &emc>, + <&mc TEGRA30_MC_DISPLAY0BB &emc>, + <&mc TEGRA30_MC_DISPLAY1BB &emc>, + <&mc TEGRA30_MC_DISPLAY0CB &emc>, + <&mc TEGRA30_MC_DISPLAYHCB &emc>; + interconnect-names = "wina", + "winb", + "winb-vfilter", + "winc", + "cursor"; + rgb { status = "disabled"; }; @@ -748,15 +770,18 @@ #iommu-cells = <1>; #reset-cells = <1>; + #interconnect-cells = <1>; }; - memory-controller@7000f400 { + emc: memory-controller@7000f400 { compatible = "nvidia,tegra30-emc"; reg = <0x7000f400 0x400>; interrupts = ; clocks = <&tegra_car TEGRA30_CLK_EMC>; nvidia,memory-controller = <&mc>; + + #interconnect-cells = <0>; }; fuse@7000f800 { From 5cf0cdbd55892d96168016d097e5657eb9af4b1f Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Mon, 23 Nov 2020 03:27:19 +0300 Subject: [PATCH 563/799] ARM: tegra: Add interconnect properties to Tegra124 device-tree Add interconnect properties to the Memory Controller, External Memory Controller and the Display Controller nodes in order to describe hardware interconnection. Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra124.dtsi | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi index e61e68a0bb58..bf621f12ffb7 100644 --- a/arch/arm/boot/dts/tegra124.dtsi +++ b/arch/arm/boot/dts/tegra124.dtsi @@ -113,6 +113,19 @@ iommus = <&mc TEGRA_SWGROUP_DC>; nvidia,head = <0>; + + interconnects = <&mc TEGRA124_MC_DISPLAY0A &emc>, + <&mc TEGRA124_MC_DISPLAY0B &emc>, + <&mc TEGRA124_MC_DISPLAY0C &emc>, + <&mc TEGRA124_MC_DISPLAYHC &emc>, + <&mc TEGRA124_MC_DISPLAYD &emc>, + <&mc TEGRA124_MC_DISPLAYT &emc>; + interconnect-names = "wina", + "winb", + "winc", + "cursor", + "wind", + "wint"; }; dc@54240000 { @@ -127,6 +140,15 @@ iommus = <&mc TEGRA_SWGROUP_DCB>; nvidia,head = <1>; + + interconnects = <&mc TEGRA124_MC_DISPLAY0AB &emc>, + <&mc TEGRA124_MC_DISPLAY0BB &emc>, + <&mc TEGRA124_MC_DISPLAY0CB &emc>, + <&mc TEGRA124_MC_DISPLAYHCB &emc>; + interconnect-names = "wina", + "winb", + "winc", + "cursor"; }; hdmi: hdmi@54280000 { @@ -628,6 +650,7 @@ #iommu-cells = <1>; #reset-cells = <1>; + #interconnect-cells = <1>; }; emc: external-memory-controller@7001b000 { @@ -637,6 +660,8 @@ clock-names = "emc"; nvidia,memory-controller = <&mc>; + + #interconnect-cells = <0>; }; sata@70020000 { From b97967d7d5b73503c9e19557895281af731cdc6a Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Mon, 23 Nov 2020 03:27:20 +0300 Subject: [PATCH 564/799] ARM: tegra: Add nvidia,memory-controller phandle to Tegra20 EMC device-tree Add nvidia,memory-controller to the Tegra20 External Memory Controller node. This allows to perform a direct lookup of the Memory Controller instead of walking up the whole tree. This puts Tegra20 device-tree on par with Tegra30+. Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra20.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi index 2e1304493f7d..8f8ad81916e7 100644 --- a/arch/arm/boot/dts/tegra20.dtsi +++ b/arch/arm/boot/dts/tegra20.dtsi @@ -663,6 +663,8 @@ #address-cells = <1>; #size-cells = <0>; #interconnect-cells = <0>; + + nvidia,memory-controller = <&mc>; }; fuse@7000f800 { From f5204ac47b298a94eadf8b6c61b534bd9abe2e41 Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Mon, 23 Nov 2020 03:27:21 +0300 Subject: [PATCH 565/799] ARM: tegra: Add EMC OPP properties to Tegra20 device-trees Add EMC OPP DVFS tables and update board device-trees by removing unsupported OPPs. Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- .../boot/dts/tegra20-acer-a500-picasso.dts | 5 + arch/arm/boot/dts/tegra20-colibri.dtsi | 4 + arch/arm/boot/dts/tegra20-paz00.dts | 4 + .../arm/boot/dts/tegra20-peripherals-opp.dtsi | 109 ++++++++++++++++++ arch/arm/boot/dts/tegra20.dtsi | 3 + 5 files changed, 125 insertions(+) create mode 100644 arch/arm/boot/dts/tegra20-peripherals-opp.dtsi diff --git a/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts b/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts index 9dafd3d57bf7..3287ff8fe4aa 100644 --- a/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts +++ b/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts @@ -1468,3 +1468,8 @@ }; }; }; + +&emc_icc_dvfs_opp_table { + /delete-node/ opp@666000000; + /delete-node/ opp@760000000; +}; diff --git a/arch/arm/boot/dts/tegra20-colibri.dtsi b/arch/arm/boot/dts/tegra20-colibri.dtsi index 6162d193e12c..585a5b441cf6 100644 --- a/arch/arm/boot/dts/tegra20-colibri.dtsi +++ b/arch/arm/boot/dts/tegra20-colibri.dtsi @@ -742,6 +742,10 @@ }; }; +&emc_icc_dvfs_opp_table { + /delete-node/ opp@760000000; +}; + &gpio { lan-reset-n { gpio-hog; diff --git a/arch/arm/boot/dts/tegra20-paz00.dts b/arch/arm/boot/dts/tegra20-paz00.dts index ada2bed8b1b5..7e49112cd9a1 100644 --- a/arch/arm/boot/dts/tegra20-paz00.dts +++ b/arch/arm/boot/dts/tegra20-paz00.dts @@ -662,3 +662,7 @@ }; }; }; + +&emc_icc_dvfs_opp_table { + /delete-node/ opp@760000000; +}; diff --git a/arch/arm/boot/dts/tegra20-peripherals-opp.dtsi b/arch/arm/boot/dts/tegra20-peripherals-opp.dtsi new file mode 100644 index 000000000000..b84afecea154 --- /dev/null +++ b/arch/arm/boot/dts/tegra20-peripherals-opp.dtsi @@ -0,0 +1,109 @@ +// SPDX-License-Identifier: GPL-2.0 + +/ { + emc_icc_dvfs_opp_table: emc-dvfs-opp-table { + compatible = "operating-points-v2"; + + opp@36000000 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <36000000>; + opp-supported-hw = <0x000F>; + }; + + opp@47500000 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <47500000>; + opp-supported-hw = <0x000F>; + }; + + opp@50000000 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <50000000>; + opp-supported-hw = <0x000F>; + }; + + opp@54000000 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <54000000>; + opp-supported-hw = <0x000F>; + }; + + opp@57000000 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <57000000>; + opp-supported-hw = <0x000F>; + }; + + opp@100000000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-hz = /bits/ 64 <100000000>; + opp-supported-hw = <0x000F>; + }; + + opp@108000000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-hz = /bits/ 64 <108000000>; + opp-supported-hw = <0x000F>; + }; + + opp@126666000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-hz = /bits/ 64 <126666000>; + opp-supported-hw = <0x000F>; + }; + + opp@150000000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-hz = /bits/ 64 <150000000>; + opp-supported-hw = <0x000F>; + }; + + opp@190000000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-hz = /bits/ 64 <190000000>; + opp-supported-hw = <0x000F>; + }; + + opp@216000000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-hz = /bits/ 64 <216000000>; + opp-supported-hw = <0x000F>; + }; + + opp@300000000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-hz = /bits/ 64 <300000000>; + opp-supported-hw = <0x000F>; + }; + + opp@333000000 { + opp-microvolt = <1000000 1000000 1300000>; + opp-hz = /bits/ 64 <333000000>; + opp-supported-hw = <0x000F>; + }; + + opp@380000000 { + opp-microvolt = <1100000 1100000 1300000>; + opp-hz = /bits/ 64 <380000000>; + opp-supported-hw = <0x000F>; + }; + + opp@600000000 { + opp-microvolt = <1200000 1200000 1300000>; + opp-hz = /bits/ 64 <600000000>; + opp-supported-hw = <0x000F>; + }; + + opp@666000000 { + opp-microvolt = <1200000 1200000 1300000>; + opp-hz = /bits/ 64 <666000000>; + opp-supported-hw = <0x000F>; + }; + + opp@760000000 { + opp-microvolt = <1300000 1300000 1300000>; + opp-hz = /bits/ 64 <760000000>; + opp-supported-hw = <0x000F>; + }; + }; +}; diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi index 8f8ad81916e7..6ce498178105 100644 --- a/arch/arm/boot/dts/tegra20.dtsi +++ b/arch/arm/boot/dts/tegra20.dtsi @@ -6,6 +6,8 @@ #include #include +#include "tegra20-peripherals-opp.dtsi" + / { compatible = "nvidia,tegra20"; interrupt-parent = <&lic>; @@ -664,6 +666,7 @@ #size-cells = <0>; #interconnect-cells = <0>; + operating-points-v2 = <&emc_icc_dvfs_opp_table>; nvidia,memory-controller = <&mc>; }; From 881741fa447d56751fe6f5af66a5c3cae4140903 Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Mon, 23 Nov 2020 03:27:22 +0300 Subject: [PATCH 566/799] ARM: tegra: Add EMC OPP and ICC properties to Tegra30 EMC and ACTMON device-tree nodes Add EMC OPP tables and interconnect paths that will be used for dynamic memory bandwidth scaling based on memory utilization statistics. Update board device-trees by removing unsupported EMC OPPs. Note that ACTMON watches all memory interconnect paths, but we use a single CPU-READ interconnect path for driving memory bandwidth, for simplicity. Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- ...30-asus-nexus7-grouper-memory-timings.dtsi | 12 + arch/arm/boot/dts/tegra30-ouya.dts | 8 + .../arm/boot/dts/tegra30-peripherals-opp.dtsi | 383 ++++++++++++++++++ arch/arm/boot/dts/tegra30.dtsi | 6 + 4 files changed, 409 insertions(+) create mode 100644 arch/arm/boot/dts/tegra30-peripherals-opp.dtsi diff --git a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-memory-timings.dtsi b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-memory-timings.dtsi index bc0f6f29b956..bcff0997ee51 100644 --- a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-memory-timings.dtsi +++ b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-memory-timings.dtsi @@ -1563,3 +1563,15 @@ }; }; }; + +&emc_icc_dvfs_opp_table { + /delete-node/ opp@750000000,1300; + /delete-node/ opp@800000000,1300; + /delete-node/ opp@900000000,1350; +}; + +&emc_bw_dfs_opp_table { + /delete-node/ opp@750000000; + /delete-node/ opp@800000000; + /delete-node/ opp@900000000; +}; diff --git a/arch/arm/boot/dts/tegra30-ouya.dts b/arch/arm/boot/dts/tegra30-ouya.dts index a5f16ad6c8f4..74da1360d297 100644 --- a/arch/arm/boot/dts/tegra30-ouya.dts +++ b/arch/arm/boot/dts/tegra30-ouya.dts @@ -4509,3 +4509,11 @@ nvidia,slew-rate-falling = ; }; }; + +&emc_icc_dvfs_opp_table { + /delete-node/ opp@900000000,1350; +}; + +&emc_bw_dfs_opp_table { + /delete-node/ opp@900000000; +}; diff --git a/arch/arm/boot/dts/tegra30-peripherals-opp.dtsi b/arch/arm/boot/dts/tegra30-peripherals-opp.dtsi new file mode 100644 index 000000000000..cbe84d25e726 --- /dev/null +++ b/arch/arm/boot/dts/tegra30-peripherals-opp.dtsi @@ -0,0 +1,383 @@ +// SPDX-License-Identifier: GPL-2.0 + +/ { + emc_icc_dvfs_opp_table: emc-dvfs-opp-table { + compatible = "operating-points-v2"; + + opp@12750000,950 { + opp-microvolt = <950000 950000 1350000>; + opp-hz = /bits/ 64 <12750000>; + opp-supported-hw = <0x0006>; + }; + + opp@12750000,1000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-hz = /bits/ 64 <12750000>; + opp-supported-hw = <0x0001>; + }; + + opp@12750000,1250 { + opp-microvolt = <1250000 1250000 1350000>; + opp-hz = /bits/ 64 <12750000>; + opp-supported-hw = <0x0008>; + }; + + opp@25500000,950 { + opp-microvolt = <950000 950000 1350000>; + opp-hz = /bits/ 64 <25500000>; + opp-supported-hw = <0x0006>; + }; + + opp@25500000,1000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-hz = /bits/ 64 <25500000>; + opp-supported-hw = <0x0001>; + }; + + opp@25500000,1250 { + opp-microvolt = <1250000 1250000 1350000>; + opp-hz = /bits/ 64 <25500000>; + opp-supported-hw = <0x0008>; + }; + + opp@27000000,950 { + opp-microvolt = <950000 950000 1350000>; + opp-hz = /bits/ 64 <27000000>; + opp-supported-hw = <0x0006>; + }; + + opp@27000000,1000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-hz = /bits/ 64 <27000000>; + opp-supported-hw = <0x0001>; + }; + + opp@27000000,1250 { + opp-microvolt = <1250000 1250000 1350000>; + opp-hz = /bits/ 64 <27000000>; + opp-supported-hw = <0x0008>; + }; + + opp@51000000,950 { + opp-microvolt = <950000 950000 1350000>; + opp-hz = /bits/ 64 <51000000>; + opp-supported-hw = <0x0006>; + }; + + opp@51000000,1000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-hz = /bits/ 64 <51000000>; + opp-supported-hw = <0x0001>; + }; + + opp@51000000,1250 { + opp-microvolt = <1250000 1250000 1350000>; + opp-hz = /bits/ 64 <51000000>; + opp-supported-hw = <0x0008>; + }; + + opp@54000000,950 { + opp-microvolt = <950000 950000 1350000>; + opp-hz = /bits/ 64 <54000000>; + opp-supported-hw = <0x0006>; + }; + + opp@54000000,1000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-hz = /bits/ 64 <54000000>; + opp-supported-hw = <0x0001>; + }; + + opp@54000000,1250 { + opp-microvolt = <1250000 1250000 1350000>; + opp-hz = /bits/ 64 <54000000>; + opp-supported-hw = <0x0008>; + }; + + opp@102000000,950 { + opp-microvolt = <950000 950000 1350000>; + opp-hz = /bits/ 64 <102000000>; + opp-supported-hw = <0x0006>; + }; + + opp@102000000,1000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-hz = /bits/ 64 <102000000>; + opp-supported-hw = <0x0001>; + }; + + opp@102000000,1250 { + opp-microvolt = <1250000 1250000 1350000>; + opp-hz = /bits/ 64 <102000000>; + opp-supported-hw = <0x0008>; + }; + + opp@108000000,1000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-hz = /bits/ 64 <108000000>; + opp-supported-hw = <0x0007>; + }; + + opp@108000000,1250 { + opp-microvolt = <1250000 1250000 1350000>; + opp-hz = /bits/ 64 <108000000>; + opp-supported-hw = <0x0008>; + }; + + opp@204000000,1000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-hz = /bits/ 64 <204000000>; + opp-supported-hw = <0x0007>; + }; + + opp@204000000,1250 { + opp-microvolt = <1250000 1250000 1350000>; + opp-hz = /bits/ 64 <204000000>; + opp-supported-hw = <0x0008>; + }; + + opp@333500000,1000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-hz = /bits/ 64 <333500000>; + opp-supported-hw = <0x0006>; + }; + + opp@333500000,1200 { + opp-microvolt = <1200000 1200000 1350000>; + opp-hz = /bits/ 64 <333500000>; + opp-supported-hw = <0x0001>; + }; + + opp@333500000,1250 { + opp-microvolt = <1250000 1250000 1350000>; + opp-hz = /bits/ 64 <333500000>; + opp-supported-hw = <0x0008>; + }; + + opp@375000000,1000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-hz = /bits/ 64 <375000000>; + opp-supported-hw = <0x0006>; + }; + + opp@375000000,1200 { + opp-microvolt = <1200000 1200000 1350000>; + opp-hz = /bits/ 64 <375000000>; + opp-supported-hw = <0x0001>; + }; + + opp@375000000,1250 { + opp-microvolt = <1250000 1250000 1350000>; + opp-hz = /bits/ 64 <375000000>; + opp-supported-hw = <0x0008>; + }; + + opp@400000000,1000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-hz = /bits/ 64 <400000000>; + opp-supported-hw = <0x0006>; + }; + + opp@400000000,1200 { + opp-microvolt = <1200000 1200000 1350000>; + opp-hz = /bits/ 64 <400000000>; + opp-supported-hw = <0x0001>; + }; + + opp@400000000,1250 { + opp-microvolt = <1250000 1250000 1350000>; + opp-hz = /bits/ 64 <400000000>; + opp-supported-hw = <0x0008>; + }; + + opp@416000000,1200 { + opp-microvolt = <1200000 1200000 1350000>; + opp-hz = /bits/ 64 <416000000>; + opp-supported-hw = <0x0007>; + }; + + opp@416000000,1250 { + opp-microvolt = <1250000 1250000 1350000>; + opp-hz = /bits/ 64 <416000000>; + opp-supported-hw = <0x0008>; + }; + + opp@450000000,1200 { + opp-microvolt = <1200000 1200000 1350000>; + opp-hz = /bits/ 64 <450000000>; + opp-supported-hw = <0x0007>; + }; + + opp@450000000,1250 { + opp-microvolt = <1250000 1250000 1350000>; + opp-hz = /bits/ 64 <450000000>; + opp-supported-hw = <0x0008>; + }; + + opp@533000000,1200 { + opp-microvolt = <1200000 1200000 1350000>; + opp-hz = /bits/ 64 <533000000>; + opp-supported-hw = <0x0007>; + }; + + opp@533000000,1250 { + opp-microvolt = <1250000 1250000 1350000>; + opp-hz = /bits/ 64 <533000000>; + opp-supported-hw = <0x0008>; + }; + + opp@625000000,1200 { + opp-microvolt = <1200000 1200000 1350000>; + opp-hz = /bits/ 64 <625000000>; + opp-supported-hw = <0x0006>; + }; + + opp@625000000,1250 { + opp-microvolt = <1250000 1250000 1350000>; + opp-hz = /bits/ 64 <625000000>; + opp-supported-hw = <0x0008>; + }; + + opp@667000000,1200 { + opp-microvolt = <1200000 1200000 1350000>; + opp-hz = /bits/ 64 <667000000>; + opp-supported-hw = <0x0006>; + }; + + opp@750000000,1300 { + opp-microvolt = <1300000 1300000 1350000>; + opp-hz = /bits/ 64 <750000000>; + opp-supported-hw = <0x0004>; + }; + + opp@800000000,1300 { + opp-microvolt = <1300000 1300000 1350000>; + opp-hz = /bits/ 64 <800000000>; + opp-supported-hw = <0x0004>; + }; + + opp@900000000,1350 { + opp-microvolt = <1350000 1350000 1350000>; + opp-hz = /bits/ 64 <900000000>; + opp-supported-hw = <0x0004>; + }; + }; + + emc_bw_dfs_opp_table: emc-bandwidth-opp-table { + compatible = "operating-points-v2"; + + opp@12750000 { + opp-hz = /bits/ 64 <12750000>; + opp-supported-hw = <0x000F>; + opp-peak-kBps = <102000>; + }; + + opp@25500000 { + opp-hz = /bits/ 64 <25500000>; + opp-supported-hw = <0x000F>; + opp-peak-kBps = <204000>; + }; + + opp@27000000 { + opp-hz = /bits/ 64 <27000000>; + opp-supported-hw = <0x000F>; + opp-peak-kBps = <216000>; + }; + + opp@51000000 { + opp-hz = /bits/ 64 <51000000>; + opp-supported-hw = <0x000F>; + opp-peak-kBps = <408000>; + }; + + opp@54000000 { + opp-hz = /bits/ 64 <54000000>; + opp-supported-hw = <0x000F>; + opp-peak-kBps = <432000>; + }; + + opp@102000000 { + opp-hz = /bits/ 64 <102000000>; + opp-supported-hw = <0x000F>; + opp-peak-kBps = <816000>; + }; + + opp@108000000 { + opp-hz = /bits/ 64 <108000000>; + opp-supported-hw = <0x000F>; + opp-peak-kBps = <864000>; + }; + + opp@204000000 { + opp-hz = /bits/ 64 <204000000>; + opp-supported-hw = <0x000F>; + opp-peak-kBps = <1632000>; + }; + + opp@333500000 { + opp-hz = /bits/ 64 <333500000>; + opp-supported-hw = <0x000F>; + opp-peak-kBps = <2668000>; + }; + + opp@375000000 { + opp-hz = /bits/ 64 <375000000>; + opp-supported-hw = <0x000F>; + opp-peak-kBps = <3000000>; + }; + + opp@400000000 { + opp-hz = /bits/ 64 <400000000>; + opp-supported-hw = <0x000F>; + opp-peak-kBps = <3200000>; + }; + + opp@416000000 { + opp-hz = /bits/ 64 <416000000>; + opp-supported-hw = <0x000F>; + opp-peak-kBps = <3328000>; + }; + + opp@450000000 { + opp-hz = /bits/ 64 <450000000>; + opp-supported-hw = <0x000F>; + opp-peak-kBps = <3600000>; + }; + + opp@533000000 { + opp-hz = /bits/ 64 <533000000>; + opp-supported-hw = <0x000F>; + opp-peak-kBps = <4264000>; + }; + + opp@625000000 { + opp-hz = /bits/ 64 <625000000>; + opp-supported-hw = <0x000E>; + opp-peak-kBps = <5000000>; + }; + + opp@667000000 { + opp-hz = /bits/ 64 <667000000>; + opp-supported-hw = <0x0006>; + opp-peak-kBps = <5336000>; + }; + + opp@750000000 { + opp-hz = /bits/ 64 <750000000>; + opp-supported-hw = <0x0004>; + opp-peak-kBps = <6000000>; + }; + + opp@800000000 { + opp-hz = /bits/ 64 <800000000>; + opp-supported-hw = <0x0004>; + opp-peak-kBps = <6400000>; + }; + + opp@900000000 { + opp-hz = /bits/ 64 <900000000>; + opp-supported-hw = <0x0004>; + opp-peak-kBps = <7200000>; + }; + }; +}; diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi index 2caf6cc6f4b1..44a6dbba7081 100644 --- a/arch/arm/boot/dts/tegra30.dtsi +++ b/arch/arm/boot/dts/tegra30.dtsi @@ -6,6 +6,8 @@ #include #include +#include "tegra30-peripherals-opp.dtsi" + / { compatible = "nvidia,tegra30"; interrupt-parent = <&lic>; @@ -417,6 +419,9 @@ clock-names = "actmon", "emc"; resets = <&tegra_car TEGRA30_CLK_ACTMON>; reset-names = "actmon"; + operating-points-v2 = <&emc_bw_dfs_opp_table>; + interconnects = <&mc TEGRA30_MC_MPCORER &emc>; + interconnect-names = "cpu-read"; }; gpio: gpio@6000d000 { @@ -780,6 +785,7 @@ clocks = <&tegra_car TEGRA30_CLK_EMC>; nvidia,memory-controller = <&mc>; + operating-points-v2 = <&emc_icc_dvfs_opp_table>; #interconnect-cells = <0>; }; From d63250d7fd49503bac48099fcef24ba7985009a3 Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Mon, 23 Nov 2020 03:27:23 +0300 Subject: [PATCH 567/799] ARM: tegra: Add EMC OPP and ICC properties to Tegra124 EMC and ACTMON device-tree nodes Add EMC OPP DVFS/DFS tables and interconnect paths that will be used for dynamic memory bandwidth scaling based on memory utilization statistics. Update board device-trees by removing unsupported EMC OPPs. Note that ACTMON watches all memory interconnect paths, but we use a single CPU-READ interconnect path for driving memory bandwidth, for simplicity. Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra124-apalis-emc.dtsi | 8 + .../arm/boot/dts/tegra124-jetson-tk1-emc.dtsi | 8 + arch/arm/boot/dts/tegra124-nyan-big-emc.dtsi | 10 + .../arm/boot/dts/tegra124-nyan-blaze-emc.dtsi | 10 + .../boot/dts/tegra124-peripherals-opp.dtsi | 419 ++++++++++++++++++ arch/arm/boot/dts/tegra124.dtsi | 6 + 6 files changed, 461 insertions(+) create mode 100644 arch/arm/boot/dts/tegra124-peripherals-opp.dtsi diff --git a/arch/arm/boot/dts/tegra124-apalis-emc.dtsi b/arch/arm/boot/dts/tegra124-apalis-emc.dtsi index 32401457ae71..a7ac805eeed5 100644 --- a/arch/arm/boot/dts/tegra124-apalis-emc.dtsi +++ b/arch/arm/boot/dts/tegra124-apalis-emc.dtsi @@ -1465,3 +1465,11 @@ }; }; }; + +&emc_icc_dvfs_opp_table { + /delete-node/ opp@1200000000,1100; +}; + +&emc_bw_dfs_opp_table { + /delete-node/ opp@1200000000; +}; diff --git a/arch/arm/boot/dts/tegra124-jetson-tk1-emc.dtsi b/arch/arm/boot/dts/tegra124-jetson-tk1-emc.dtsi index 861d3f22116b..df4e463afbd1 100644 --- a/arch/arm/boot/dts/tegra124-jetson-tk1-emc.dtsi +++ b/arch/arm/boot/dts/tegra124-jetson-tk1-emc.dtsi @@ -2420,3 +2420,11 @@ }; }; }; + +&emc_icc_dvfs_opp_table { + /delete-node/ opp@1200000000,1100; +}; + +&emc_bw_dfs_opp_table { + /delete-node/ opp@1200000000; +}; diff --git a/arch/arm/boot/dts/tegra124-nyan-big-emc.dtsi b/arch/arm/boot/dts/tegra124-nyan-big-emc.dtsi index c91647d13a50..a0f56cc9da5c 100644 --- a/arch/arm/boot/dts/tegra124-nyan-big-emc.dtsi +++ b/arch/arm/boot/dts/tegra124-nyan-big-emc.dtsi @@ -6649,3 +6649,13 @@ }; }; }; + +&emc_icc_dvfs_opp_table { + /delete-node/ opp@924000000,1100; + /delete-node/ opp@1200000000,1100; +}; + +&emc_bw_dfs_opp_table { + /delete-node/ opp@924000000; + /delete-node/ opp@1200000000; +}; diff --git a/arch/arm/boot/dts/tegra124-nyan-blaze-emc.dtsi b/arch/arm/boot/dts/tegra124-nyan-blaze-emc.dtsi index d2beea0bd15f..35c98734d35f 100644 --- a/arch/arm/boot/dts/tegra124-nyan-blaze-emc.dtsi +++ b/arch/arm/boot/dts/tegra124-nyan-blaze-emc.dtsi @@ -2048,3 +2048,13 @@ }; }; }; + +&emc_icc_dvfs_opp_table { + /delete-node/ opp@924000000,1100; + /delete-node/ opp@1200000000,1100; +}; + +&emc_bw_dfs_opp_table { + /delete-node/ opp@924000000; + /delete-node/ opp@1200000000; +}; diff --git a/arch/arm/boot/dts/tegra124-peripherals-opp.dtsi b/arch/arm/boot/dts/tegra124-peripherals-opp.dtsi new file mode 100644 index 000000000000..49d9420a3289 --- /dev/null +++ b/arch/arm/boot/dts/tegra124-peripherals-opp.dtsi @@ -0,0 +1,419 @@ +// SPDX-License-Identifier: GPL-2.0 + +/ { + emc_icc_dvfs_opp_table: emc-dvfs-opp-table { + compatible = "operating-points-v2"; + + opp@12750000,800 { + opp-microvolt = <800000 800000 1150000>; + opp-hz = /bits/ 64 <12750000>; + opp-supported-hw = <0x0003>; + }; + + opp@12750000,950 { + opp-microvolt = <950000 950000 1150000>; + opp-hz = /bits/ 64 <12750000>; + opp-supported-hw = <0x0008>; + }; + + opp@12750000,1050 { + opp-microvolt = <1050000 1050000 1150000>; + opp-hz = /bits/ 64 <12750000>; + opp-supported-hw = <0x0010>; + }; + + opp@12750000,1110 { + opp-microvolt = <1110000 1110000 1150000>; + opp-hz = /bits/ 64 <12750000>; + opp-supported-hw = <0x0004>; + }; + + opp@20400000,800 { + opp-microvolt = <800000 800000 1150000>; + opp-hz = /bits/ 64 <20400000>; + opp-supported-hw = <0x0003>; + }; + + opp@20400000,950 { + opp-microvolt = <950000 950000 1150000>; + opp-hz = /bits/ 64 <20400000>; + opp-supported-hw = <0x0008>; + }; + + opp@20400000,1050 { + opp-microvolt = <1050000 1050000 1150000>; + opp-hz = /bits/ 64 <20400000>; + opp-supported-hw = <0x0010>; + }; + + opp@20400000,1110 { + opp-microvolt = <1110000 1110000 1150000>; + opp-hz = /bits/ 64 <20400000>; + opp-supported-hw = <0x0004>; + }; + + opp@40800000,800 { + opp-microvolt = <800000 800000 1150000>; + opp-hz = /bits/ 64 <40800000>; + opp-supported-hw = <0x0003>; + }; + + opp@40800000,950 { + opp-microvolt = <950000 950000 1150000>; + opp-hz = /bits/ 64 <40800000>; + opp-supported-hw = <0x0008>; + }; + + opp@40800000,1050 { + opp-microvolt = <1050000 1050000 1150000>; + opp-hz = /bits/ 64 <40800000>; + opp-supported-hw = <0x0010>; + }; + + opp@40800000,1110 { + opp-microvolt = <1110000 1110000 1150000>; + opp-hz = /bits/ 64 <40800000>; + opp-supported-hw = <0x0004>; + }; + + opp@68000000,800 { + opp-microvolt = <800000 800000 1150000>; + opp-hz = /bits/ 64 <68000000>; + opp-supported-hw = <0x0003>; + }; + + opp@68000000,950 { + opp-microvolt = <950000 950000 1150000>; + opp-hz = /bits/ 64 <68000000>; + opp-supported-hw = <0x0008>; + }; + + opp@68000000,1050 { + opp-microvolt = <1050000 1050000 1150000>; + opp-hz = /bits/ 64 <68000000>; + opp-supported-hw = <0x0010>; + }; + + opp@68000000,1110 { + opp-microvolt = <1110000 1110000 1150000>; + opp-hz = /bits/ 64 <68000000>; + opp-supported-hw = <0x0004>; + }; + + opp@102000000,800 { + opp-microvolt = <800000 800000 1150000>; + opp-hz = /bits/ 64 <102000000>; + opp-supported-hw = <0x0003>; + }; + + opp@102000000,950 { + opp-microvolt = <950000 950000 1150000>; + opp-hz = /bits/ 64 <102000000>; + opp-supported-hw = <0x0008>; + }; + + opp@102000000,1050 { + opp-microvolt = <1050000 1050000 1150000>; + opp-hz = /bits/ 64 <102000000>; + opp-supported-hw = <0x0010>; + }; + + opp@102000000,1110 { + opp-microvolt = <1110000 1110000 1150000>; + opp-hz = /bits/ 64 <102000000>; + opp-supported-hw = <0x0004>; + }; + + opp@204000000,800 { + opp-microvolt = <800000 800000 1150000>; + opp-hz = /bits/ 64 <204000000>; + opp-supported-hw = <0x0003>; + }; + + opp@204000000,950 { + opp-microvolt = <950000 950000 1150000>; + opp-hz = /bits/ 64 <204000000>; + opp-supported-hw = <0x0008>; + }; + + opp@204000000,1050 { + opp-microvolt = <1050000 1050000 1150000>; + opp-hz = /bits/ 64 <204000000>; + opp-supported-hw = <0x0010>; + }; + + opp@204000000,1110 { + opp-microvolt = <1110000 1110000 1150000>; + opp-hz = /bits/ 64 <204000000>; + opp-supported-hw = <0x0004>; + }; + + opp@264000000,800 { + opp-microvolt = <800000 800000 1150000>; + opp-hz = /bits/ 64 <264000000>; + opp-supported-hw = <0x0003>; + }; + + opp@264000000,950 { + opp-microvolt = <950000 950000 1150000>; + opp-hz = /bits/ 64 <264000000>; + opp-supported-hw = <0x0008>; + }; + + opp@264000000,1050 { + opp-microvolt = <1050000 1050000 1150000>; + opp-hz = /bits/ 64 <264000000>; + opp-supported-hw = <0x0010>; + }; + + opp@264000000,1110 { + opp-microvolt = <1110000 1110000 1150000>; + opp-hz = /bits/ 64 <264000000>; + opp-supported-hw = <0x0004>; + }; + + opp@300000000,850 { + opp-microvolt = <850000 850000 1150000>; + opp-hz = /bits/ 64 <300000000>; + opp-supported-hw = <0x0003>; + }; + + opp@300000000,950 { + opp-microvolt = <950000 950000 1150000>; + opp-hz = /bits/ 64 <300000000>; + opp-supported-hw = <0x0008>; + }; + + opp@300000000,1050 { + opp-microvolt = <1050000 1050000 1150000>; + opp-hz = /bits/ 64 <300000000>; + opp-supported-hw = <0x0010>; + }; + + opp@300000000,1110 { + opp-microvolt = <1110000 1110000 1150000>; + opp-hz = /bits/ 64 <300000000>; + opp-supported-hw = <0x0004>; + }; + + opp@348000000,850 { + opp-microvolt = <850000 850000 1150000>; + opp-hz = /bits/ 64 <348000000>; + opp-supported-hw = <0x0003>; + }; + + opp@348000000,950 { + opp-microvolt = <950000 950000 1150000>; + opp-hz = /bits/ 64 <348000000>; + opp-supported-hw = <0x0008>; + }; + + opp@348000000,1050 { + opp-microvolt = <1050000 1050000 1150000>; + opp-hz = /bits/ 64 <348000000>; + opp-supported-hw = <0x0010>; + }; + + opp@348000000,1110 { + opp-microvolt = <1110000 1110000 1150000>; + opp-hz = /bits/ 64 <348000000>; + opp-supported-hw = <0x0004>; + }; + + opp@396000000,950 { + opp-microvolt = <950000 950000 1150000>; + opp-hz = /bits/ 64 <396000000>; + opp-supported-hw = <0x0008>; + }; + + opp@396000000,1000 { + opp-microvolt = <1000000 1000000 1150000>; + opp-hz = /bits/ 64 <396000000>; + opp-supported-hw = <0x0003>; + }; + + opp@396000000,1050 { + opp-microvolt = <1050000 1050000 1150000>; + opp-hz = /bits/ 64 <396000000>; + opp-supported-hw = <0x0010>; + }; + + opp@396000000,1110 { + opp-microvolt = <1110000 1110000 1150000>; + opp-hz = /bits/ 64 <396000000>; + opp-supported-hw = <0x0004>; + }; + + opp@528000000,950 { + opp-microvolt = <950000 950000 1150000>; + opp-hz = /bits/ 64 <528000000>; + opp-supported-hw = <0x0008>; + }; + + opp@528000000,1000 { + opp-microvolt = <1000000 1000000 1150000>; + opp-hz = /bits/ 64 <528000000>; + opp-supported-hw = <0x0003>; + }; + + opp@528000000,1050 { + opp-microvolt = <1050000 1050000 1150000>; + opp-hz = /bits/ 64 <528000000>; + opp-supported-hw = <0x0010>; + }; + + opp@528000000,1110 { + opp-microvolt = <1110000 1110000 1150000>; + opp-hz = /bits/ 64 <528000000>; + opp-supported-hw = <0x0004>; + }; + + opp@600000000,950 { + opp-microvolt = <950000 950000 1150000>; + opp-hz = /bits/ 64 <600000000>; + opp-supported-hw = <0x0008>; + }; + + opp@600000000,1000 { + opp-microvolt = <1000000 1000000 1150000>; + opp-hz = /bits/ 64 <600000000>; + opp-supported-hw = <0x0003>; + }; + + opp@600000000,1050 { + opp-microvolt = <1050000 1050000 1150000>; + opp-hz = /bits/ 64 <600000000>; + opp-supported-hw = <0x0010>; + }; + + opp@600000000,1110 { + opp-microvolt = <1110000 1110000 1150000>; + opp-hz = /bits/ 64 <600000000>; + opp-supported-hw = <0x0004>; + }; + + opp@792000000,1000 { + opp-microvolt = <1000000 1000000 1150000>; + opp-hz = /bits/ 64 <792000000>; + opp-supported-hw = <0x000B>; + }; + + opp@792000000,1050 { + opp-microvolt = <1050000 1050000 1150000>; + opp-hz = /bits/ 64 <792000000>; + opp-supported-hw = <0x0010>; + }; + + opp@792000000,1110 { + opp-microvolt = <1110000 1110000 1150000>; + opp-hz = /bits/ 64 <792000000>; + opp-supported-hw = <0x0004>; + }; + + opp@924000000,1100 { + opp-microvolt = <1100000 1100000 1150000>; + opp-hz = /bits/ 64 <924000000>; + opp-supported-hw = <0x0013>; + }; + + opp@1200000000,1100 { + opp-microvolt = <1100000 1100000 1150000>; + opp-hz = /bits/ 64 <1200000000>; + opp-supported-hw = <0x0003>; + }; + }; + + emc_bw_dfs_opp_table: emc-bandwidth-opp-table { + compatible = "operating-points-v2"; + + opp@12750000 { + opp-hz = /bits/ 64 <12750000>; + opp-supported-hw = <0x001F>; + opp-peak-kBps = <204000>; + }; + + opp@20400000 { + opp-hz = /bits/ 64 <20400000>; + opp-supported-hw = <0x001F>; + opp-peak-kBps = <326400>; + }; + + opp@40800000 { + opp-hz = /bits/ 64 <40800000>; + opp-supported-hw = <0x001F>; + opp-peak-kBps = <652800>; + }; + + opp@68000000 { + opp-hz = /bits/ 64 <68000000>; + opp-supported-hw = <0x001F>; + opp-peak-kBps = <1088000>; + }; + + opp@102000000 { + opp-hz = /bits/ 64 <102000000>; + opp-supported-hw = <0x001F>; + opp-peak-kBps = <1632000>; + }; + + opp@204000000 { + opp-hz = /bits/ 64 <204000000>; + opp-supported-hw = <0x001F>; + opp-peak-kBps = <3264000>; + }; + + opp@264000000 { + opp-hz = /bits/ 64 <264000000>; + opp-supported-hw = <0x001F>; + opp-peak-kBps = <4224000>; + }; + + opp@300000000 { + opp-hz = /bits/ 64 <300000000>; + opp-supported-hw = <0x001F>; + opp-peak-kBps = <4800000>; + }; + + opp@348000000 { + opp-hz = /bits/ 64 <348000000>; + opp-supported-hw = <0x001F>; + opp-peak-kBps = <5568000>; + }; + + opp@396000000 { + opp-hz = /bits/ 64 <396000000>; + opp-supported-hw = <0x001F>; + opp-peak-kBps = <6336000>; + }; + + opp@528000000 { + opp-hz = /bits/ 64 <528000000>; + opp-supported-hw = <0x001F>; + opp-peak-kBps = <8448000>; + }; + + opp@600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-supported-hw = <0x001F>; + opp-peak-kBps = <9600000>; + }; + + opp@792000000 { + opp-hz = /bits/ 64 <792000000>; + opp-supported-hw = <0x001F>; + opp-peak-kBps = <12672000>; + }; + + opp@924000000 { + opp-hz = /bits/ 64 <924000000>; + opp-supported-hw = <0x0013>; + opp-peak-kBps = <14784000>; + }; + + opp@1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-supported-hw = <0x0003>; + opp-peak-kBps = <19200000>; + }; + }; +}; diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi index bf621f12ffb7..0b678afb2a5c 100644 --- a/arch/arm/boot/dts/tegra124.dtsi +++ b/arch/arm/boot/dts/tegra124.dtsi @@ -8,6 +8,8 @@ #include #include +#include "tegra124-peripherals-opp.dtsi" + / { compatible = "nvidia,tegra124"; interrupt-parent = <&lic>; @@ -290,6 +292,9 @@ clock-names = "actmon", "emc"; resets = <&tegra_car 119>; reset-names = "actmon"; + operating-points-v2 = <&emc_bw_dfs_opp_table>; + interconnects = <&mc TEGRA124_MC_MPCORER &emc>; + interconnect-names = "cpu-read"; }; gpio: gpio@6000d000 { @@ -660,6 +665,7 @@ clock-names = "emc"; nvidia,memory-controller = <&mc>; + operating-points-v2 = <&emc_icc_dvfs_opp_table>; #interconnect-cells = <0>; }; From 0f80b9b8126cf3e352aa6b270ed24c9cd9a6272b Mon Sep 17 00:00:00 2001 From: Yuya Hamamachi Date: Wed, 25 Nov 2020 16:33:03 +0900 Subject: [PATCH 568/799] arm64: dts: renesas: r8a77951: Add PCIe EP nodes Add PCIe EP nodes for R8A77951 SoC dtsi. Signed-off-by: Yuya Hamamachi Link: https://lore.kernel.org/r/20201125073303.19057-3-yuya.hamamachi.sx@renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a77951.dtsi | 38 +++++++++++++++++++++++ 1 file changed, 38 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a77951.dtsi b/arch/arm64/boot/dts/renesas/r8a77951.dtsi index 644308dd886c..9d60bcf69e4f 100644 --- a/arch/arm64/boot/dts/renesas/r8a77951.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77951.dtsi @@ -2727,6 +2727,44 @@ status = "disabled"; }; + pciec0_ep: pcie-ep@fe000000 { + compatible = "renesas,r8a7795-pcie-ep", + "renesas,rcar-gen3-pcie-ep"; + reg = <0x0 0xfe000000 0 0x80000>, + <0x0 0xfe100000 0 0x100000>, + <0x0 0xfe200000 0 0x200000>, + <0x0 0x30000000 0 0x8000000>, + <0x0 0x38000000 0 0x8000000>; + reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3"; + interrupts = , + , + ; + clocks = <&cpg CPG_MOD 319>; + clock-names = "pcie"; + resets = <&cpg 319>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + status = "disabled"; + }; + + pciec1_ep: pcie-ep@ee800000 { + compatible = "renesas,r8a7795-pcie-ep", + "renesas,rcar-gen3-pcie-ep"; + reg = <0x0 0xee800000 0 0x80000>, + <0x0 0xee900000 0 0x100000>, + <0x0 0xeea00000 0 0x200000>, + <0x0 0xc0000000 0 0x8000000>, + <0x0 0xc8000000 0 0x8000000>; + reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3"; + interrupts = , + , + ; + clocks = <&cpg CPG_MOD 318>; + clock-names = "pcie"; + resets = <&cpg 318>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + status = "disabled"; + }; + imr-lx4@fe860000 { compatible = "renesas,r8a7795-imr-lx4", "renesas,imr-lx4"; From 17fb46bf56864d7a2020f06ff549d5fa8b4426d7 Mon Sep 17 00:00:00 2001 From: Fabien Parent Date: Fri, 16 Oct 2020 19:18:37 +0200 Subject: [PATCH 569/799] arm64: dts: mediatek: mt8516: add efuse node Add node to support e-fuses on MT8516 Signed-off-by: Fabien Parent Link: https://lore.kernel.org/r/20201016171837.3261310-2-fparent@baylibre.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8516.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8516.dtsi b/arch/arm64/boot/dts/mediatek/mt8516.dtsi index eca7969e15ab..e6e4d9d60094 100644 --- a/arch/arm64/boot/dts/mediatek/mt8516.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8516.dtsi @@ -237,6 +237,13 @@ interrupts = ; }; + efuse: efuse@10009000 { + compatible = "mediatek,mt8516-efuse", "mediatek,efuse"; + reg = <0 0x10009000 0 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + }; + pwrap: pwrap@1000f000 { compatible = "mediatek,mt8516-pwrap"; reg = <0 0x1000f000 0 0x1000>; From 6d5af8c9062780889e66281a8dfbe4961b7a0cf5 Mon Sep 17 00:00:00 2001 From: Fabien Parent Date: Tue, 27 Oct 2020 20:48:13 +0100 Subject: [PATCH 570/799] dt-bindings: arm64: dts: mediatek: Add mt8167-pumpkin board Add binding documentation for the MT8167 Pumpkin board. Signed-off-by: Fabien Parent Acked-by: Rob Herring Link: https://lore.kernel.org/r/20201027194816.1227654-1-fparent@baylibre.com Signed-off-by: Matthias Brugger --- Documentation/devicetree/bindings/arm/mediatek.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/mediatek.yaml b/Documentation/devicetree/bindings/arm/mediatek.yaml index 30908963ae26..5c772b937efc 100644 --- a/Documentation/devicetree/bindings/arm/mediatek.yaml +++ b/Documentation/devicetree/bindings/arm/mediatek.yaml @@ -84,6 +84,10 @@ properties: - enum: - mediatek,mt8135-evbp1 - const: mediatek,mt8135 + - items: + - enum: + - mediatek,mt8167-pumpkin + - const: mediatek,mt8167 - description: Google Elm (Acer Chromebook R13) items: - const: google,elm-rev8 From 08d73b65abaf154a5d685d5dcd208d191115b24d Mon Sep 17 00:00:00 2001 From: Fabien Parent Date: Tue, 27 Oct 2020 20:48:14 +0100 Subject: [PATCH 571/799] arm64: dts: mediatek: add dtsi for MT8167 The MT8167 SoC provides the following peripherals: GPIO, UART, USB2, SPI, eMMC, SDIO, NAND, Flash, ADC, I2C, PWM, TImers, IR, Ethernet, Audio (I2S, SPDIF, TDM, HDMI), HDMI, DSI, CSI, MDP (Multimedia Data Path), Video encoding (H.264), Video Decoding (H.264, VP8). The MT8167 is compatible with MT8516 but provides multimedia IPs to it. This commit is just adding the basic dtsi file with the support of the following IOs: GPIO, Clocks. Signed-off-by: Fabien Parent Link: https://lore.kernel.org/r/20201027194816.1227654-2-fparent@baylibre.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8167-pinfunc.h | 744 ++++++++++++++++++ arch/arm64/boot/dts/mediatek/mt8167.dtsi | 61 ++ 2 files changed, 805 insertions(+) create mode 100644 arch/arm64/boot/dts/mediatek/mt8167-pinfunc.h create mode 100644 arch/arm64/boot/dts/mediatek/mt8167.dtsi diff --git a/arch/arm64/boot/dts/mediatek/mt8167-pinfunc.h b/arch/arm64/boot/dts/mediatek/mt8167-pinfunc.h new file mode 100644 index 000000000000..061c3255a973 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8167-pinfunc.h @@ -0,0 +1,744 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2020 MediaTek Inc. + */ +#ifndef __DTS_MT8167_PINFUNC_H +#define __DTS_MT8167_PINFUNC_H + +#include + +#define MT8167_PIN_0_EINT0__FUNC_GPIO0 (MTK_PIN_NO(0) | 0) +#define MT8167_PIN_0_EINT0__FUNC_PWM_B (MTK_PIN_NO(0) | 1) +#define MT8167_PIN_0_EINT0__FUNC_DPI_CK (MTK_PIN_NO(0) | 2) +#define MT8167_PIN_0_EINT0__FUNC_I2S2_BCK (MTK_PIN_NO(0) | 3) +#define MT8167_PIN_0_EINT0__FUNC_EXT_TXD0 (MTK_PIN_NO(0) | 4) +#define MT8167_PIN_0_EINT0__FUNC_SQICS (MTK_PIN_NO(0) | 6) +#define MT8167_PIN_0_EINT0__FUNC_DBG_MON_A_6 (MTK_PIN_NO(0) | 7) + +#define MT8167_PIN_1_EINT1__FUNC_GPIO1 (MTK_PIN_NO(1) | 0) +#define MT8167_PIN_1_EINT1__FUNC_PWM_C (MTK_PIN_NO(1) | 1) +#define MT8167_PIN_1_EINT1__FUNC_DPI_D12 (MTK_PIN_NO(1) | 2) +#define MT8167_PIN_1_EINT1__FUNC_I2S2_DI (MTK_PIN_NO(1) | 3) +#define MT8167_PIN_1_EINT1__FUNC_EXT_TXD1 (MTK_PIN_NO(1) | 4) +#define MT8167_PIN_1_EINT1__FUNC_CONN_MCU_TDO (MTK_PIN_NO(1) | 5) +#define MT8167_PIN_1_EINT1__FUNC_SQISO (MTK_PIN_NO(1) | 6) +#define MT8167_PIN_1_EINT1__FUNC_DBG_MON_A_7 (MTK_PIN_NO(1) | 7) + +#define MT8167_PIN_2_EINT2__FUNC_GPIO2 (MTK_PIN_NO(2) | 0) +#define MT8167_PIN_2_EINT2__FUNC_CLKM0 (MTK_PIN_NO(2) | 1) +#define MT8167_PIN_2_EINT2__FUNC_DPI_D13 (MTK_PIN_NO(2) | 2) +#define MT8167_PIN_2_EINT2__FUNC_I2S2_LRCK (MTK_PIN_NO(2) | 3) +#define MT8167_PIN_2_EINT2__FUNC_EXT_TXD2 (MTK_PIN_NO(2) | 4) +#define MT8167_PIN_2_EINT2__FUNC_CONN_MCU_DBGACK_N (MTK_PIN_NO(2) | 5) +#define MT8167_PIN_2_EINT2__FUNC_SQISI (MTK_PIN_NO(2) | 6) +#define MT8167_PIN_2_EINT2__FUNC_DBG_MON_A_8 (MTK_PIN_NO(2) | 7) + +#define MT8167_PIN_3_EINT3__FUNC_GPIO3 (MTK_PIN_NO(3) | 0) +#define MT8167_PIN_3_EINT3__FUNC_CLKM1 (MTK_PIN_NO(3) | 1) +#define MT8167_PIN_3_EINT3__FUNC_DPI_D14 (MTK_PIN_NO(3) | 2) +#define MT8167_PIN_3_EINT3__FUNC_SPI_MI (MTK_PIN_NO(3) | 3) +#define MT8167_PIN_3_EINT3__FUNC_EXT_TXD3 (MTK_PIN_NO(3) | 4) +#define MT8167_PIN_3_EINT3__FUNC_CONN_MCU_DBGI_N (MTK_PIN_NO(3) | 5) +#define MT8167_PIN_3_EINT3__FUNC_SQIWP (MTK_PIN_NO(3) | 6) +#define MT8167_PIN_3_EINT3__FUNC_DBG_MON_A_9 (MTK_PIN_NO(3) | 7) + +#define MT8167_PIN_4_EINT4__FUNC_GPIO4 (MTK_PIN_NO(4) | 0) +#define MT8167_PIN_4_EINT4__FUNC_CLKM2 (MTK_PIN_NO(4) | 1) +#define MT8167_PIN_4_EINT4__FUNC_DPI_D15 (MTK_PIN_NO(4) | 2) +#define MT8167_PIN_4_EINT4__FUNC_SPI_MO (MTK_PIN_NO(4) | 3) +#define MT8167_PIN_4_EINT4__FUNC_EXT_TXC (MTK_PIN_NO(4) | 4) +#define MT8167_PIN_4_EINT4__FUNC_CONN_MCU_TCK (MTK_PIN_NO(4) | 5) +#define MT8167_PIN_4_EINT4__FUNC_CONN_MCU_AICE_JCKC (MTK_PIN_NO(4) | 6) +#define MT8167_PIN_4_EINT4__FUNC_DBG_MON_A_10 (MTK_PIN_NO(4) | 7) + +#define MT8167_PIN_5_EINT5__FUNC_GPIO5 (MTK_PIN_NO(5) | 0) +#define MT8167_PIN_5_EINT5__FUNC_UCTS2 (MTK_PIN_NO(5) | 1) +#define MT8167_PIN_5_EINT5__FUNC_DPI_D16 (MTK_PIN_NO(5) | 2) +#define MT8167_PIN_5_EINT5__FUNC_SPI_CSB (MTK_PIN_NO(5) | 3) +#define MT8167_PIN_5_EINT5__FUNC_EXT_RXER (MTK_PIN_NO(5) | 4) +#define MT8167_PIN_5_EINT5__FUNC_CONN_MCU_TDI (MTK_PIN_NO(5) | 5) +#define MT8167_PIN_5_EINT5__FUNC_CONN_TEST_CK (MTK_PIN_NO(5) | 6) +#define MT8167_PIN_5_EINT5__FUNC_DBG_MON_A_11 (MTK_PIN_NO(5) | 7) + +#define MT8167_PIN_6_EINT6__FUNC_GPIO6 (MTK_PIN_NO(6) | 0) +#define MT8167_PIN_6_EINT6__FUNC_URTS2 (MTK_PIN_NO(6) | 1) +#define MT8167_PIN_6_EINT6__FUNC_DPI_D17 (MTK_PIN_NO(6) | 2) +#define MT8167_PIN_6_EINT6__FUNC_SPI_CLK (MTK_PIN_NO(6) | 3) +#define MT8167_PIN_6_EINT6__FUNC_EXT_RXC (MTK_PIN_NO(6) | 4) +#define MT8167_PIN_6_EINT6__FUNC_CONN_MCU_TRST_B (MTK_PIN_NO(6) | 5) +#define MT8167_PIN_6_EINT6__FUNC_MM_TEST_CK (MTK_PIN_NO(6) | 6) +#define MT8167_PIN_6_EINT6__FUNC_DBG_MON_A_12 (MTK_PIN_NO(6) | 7) + +#define MT8167_PIN_7_EINT7__FUNC_GPIO7 (MTK_PIN_NO(7) | 0) +#define MT8167_PIN_7_EINT7__FUNC_SQIRST (MTK_PIN_NO(7) | 1) +#define MT8167_PIN_7_EINT7__FUNC_DPI_D6 (MTK_PIN_NO(7) | 2) +#define MT8167_PIN_7_EINT7__FUNC_SDA1_0 (MTK_PIN_NO(7) | 3) +#define MT8167_PIN_7_EINT7__FUNC_EXT_RXDV (MTK_PIN_NO(7) | 4) +#define MT8167_PIN_7_EINT7__FUNC_CONN_MCU_TMS (MTK_PIN_NO(7) | 5) +#define MT8167_PIN_7_EINT7__FUNC_CONN_MCU_AICE_JMSC (MTK_PIN_NO(7) | 6) +#define MT8167_PIN_7_EINT7__FUNC_DBG_MON_A_13 (MTK_PIN_NO(7) | 7) + +#define MT8167_PIN_8_EINT8__FUNC_GPIO8 (MTK_PIN_NO(8) | 0) +#define MT8167_PIN_8_EINT8__FUNC_SQICK (MTK_PIN_NO(8) | 1) +#define MT8167_PIN_8_EINT8__FUNC_CLKM3 (MTK_PIN_NO(8) | 2) +#define MT8167_PIN_8_EINT8__FUNC_SCL1_0 (MTK_PIN_NO(8) | 3) +#define MT8167_PIN_8_EINT8__FUNC_EXT_RXD0 (MTK_PIN_NO(8) | 4) +#define MT8167_PIN_8_EINT8__FUNC_ANT_SEL0 (MTK_PIN_NO(8) | 5) +#define MT8167_PIN_8_EINT8__FUNC_DPI_D7 (MTK_PIN_NO(8) | 6) +#define MT8167_PIN_8_EINT8__FUNC_DBG_MON_A_14 (MTK_PIN_NO(8) | 7) + +#define MT8167_PIN_9_EINT9__FUNC_GPIO9 (MTK_PIN_NO(9) | 0) +#define MT8167_PIN_9_EINT9__FUNC_CLKM4 (MTK_PIN_NO(9) | 1) +#define MT8167_PIN_9_EINT9__FUNC_SDA2_0 (MTK_PIN_NO(9) | 2) +#define MT8167_PIN_9_EINT9__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(9) | 3) +#define MT8167_PIN_9_EINT9__FUNC_EXT_RXD1 (MTK_PIN_NO(9) | 4) +#define MT8167_PIN_9_EINT9__FUNC_ANT_SEL1 (MTK_PIN_NO(9) | 5) +#define MT8167_PIN_9_EINT9__FUNC_DPI_D8 (MTK_PIN_NO(9) | 6) +#define MT8167_PIN_9_EINT9__FUNC_DBG_MON_A_15 (MTK_PIN_NO(9) | 7) + +#define MT8167_PIN_10_EINT10__FUNC_GPIO10 (MTK_PIN_NO(10) | 0) +#define MT8167_PIN_10_EINT10__FUNC_CLKM5 (MTK_PIN_NO(10) | 1) +#define MT8167_PIN_10_EINT10__FUNC_SCL2_0 (MTK_PIN_NO(10) | 2) +#define MT8167_PIN_10_EINT10__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(10) | 3) +#define MT8167_PIN_10_EINT10__FUNC_EXT_RXD2 (MTK_PIN_NO(10) | 4) +#define MT8167_PIN_10_EINT10__FUNC_ANT_SEL2 (MTK_PIN_NO(10) | 5) +#define MT8167_PIN_10_EINT10__FUNC_DPI_D9 (MTK_PIN_NO(10) | 6) +#define MT8167_PIN_10_EINT10__FUNC_DBG_MON_A_16 (MTK_PIN_NO(10) | 7) + +#define MT8167_PIN_11_EINT11__FUNC_GPIO11 (MTK_PIN_NO(11) | 0) +#define MT8167_PIN_11_EINT11__FUNC_CLKM4 (MTK_PIN_NO(11) | 1) +#define MT8167_PIN_11_EINT11__FUNC_PWM_C (MTK_PIN_NO(11) | 2) +#define MT8167_PIN_11_EINT11__FUNC_CONN_TEST_CK (MTK_PIN_NO(11) | 3) +#define MT8167_PIN_11_EINT11__FUNC_ANT_SEL3 (MTK_PIN_NO(11) | 4) +#define MT8167_PIN_11_EINT11__FUNC_DPI_D10 (MTK_PIN_NO(11) | 5) +#define MT8167_PIN_11_EINT11__FUNC_EXT_RXD3 (MTK_PIN_NO(11) | 6) +#define MT8167_PIN_11_EINT11__FUNC_DBG_MON_A_17 (MTK_PIN_NO(11) | 7) + +#define MT8167_PIN_12_EINT12__FUNC_GPIO12 (MTK_PIN_NO(12) | 0) +#define MT8167_PIN_12_EINT12__FUNC_CLKM5 (MTK_PIN_NO(12) | 1) +#define MT8167_PIN_12_EINT12__FUNC_PWM_A (MTK_PIN_NO(12) | 2) +#define MT8167_PIN_12_EINT12__FUNC_SPDIF_OUT (MTK_PIN_NO(12) | 3) +#define MT8167_PIN_12_EINT12__FUNC_ANT_SEL4 (MTK_PIN_NO(12) | 4) +#define MT8167_PIN_12_EINT12__FUNC_DPI_D11 (MTK_PIN_NO(12) | 5) +#define MT8167_PIN_12_EINT12__FUNC_EXT_TXEN (MTK_PIN_NO(12) | 6) +#define MT8167_PIN_12_EINT12__FUNC_DBG_MON_A_18 (MTK_PIN_NO(12) | 7) + +#define MT8167_PIN_13_EINT13__FUNC_GPIO13 (MTK_PIN_NO(13) | 0) +#define MT8167_PIN_13_EINT13__FUNC_TSF_IN (MTK_PIN_NO(13) | 3) +#define MT8167_PIN_13_EINT13__FUNC_ANT_SEL5 (MTK_PIN_NO(13) | 4) +#define MT8167_PIN_13_EINT13__FUNC_DPI_D0 (MTK_PIN_NO(13) | 5) +#define MT8167_PIN_13_EINT13__FUNC_SPDIF_IN (MTK_PIN_NO(13) | 6) +#define MT8167_PIN_13_EINT13__FUNC_DBG_MON_A_19 (MTK_PIN_NO(13) | 7) + +#define MT8167_PIN_14_EINT14__FUNC_GPIO14 (MTK_PIN_NO(14) | 0) +#define MT8167_PIN_14_EINT14__FUNC_I2S_8CH_DO1 (MTK_PIN_NO(14) | 2) +#define MT8167_PIN_14_EINT14__FUNC_TDM_RX_MCK (MTK_PIN_NO(14) | 3) +#define MT8167_PIN_14_EINT14__FUNC_ANT_SEL1 (MTK_PIN_NO(14) | 4) +#define MT8167_PIN_14_EINT14__FUNC_CONN_MCU_DBGACK_N (MTK_PIN_NO(14) | 5) +#define MT8167_PIN_14_EINT14__FUNC_NCLE (MTK_PIN_NO(14) | 6) +#define MT8167_PIN_14_EINT14__FUNC_DBG_MON_B_8 (MTK_PIN_NO(14) | 7) + +#define MT8167_PIN_15_EINT15__FUNC_GPIO15 (MTK_PIN_NO(15) | 0) +#define MT8167_PIN_15_EINT15__FUNC_I2S_8CH_LRCK (MTK_PIN_NO(15) | 2) +#define MT8167_PIN_15_EINT15__FUNC_TDM_RX_BCK (MTK_PIN_NO(15) | 3) +#define MT8167_PIN_15_EINT15__FUNC_ANT_SEL2 (MTK_PIN_NO(15) | 4) +#define MT8167_PIN_15_EINT15__FUNC_CONN_MCU_DBGI_N (MTK_PIN_NO(15) | 5) +#define MT8167_PIN_15_EINT15__FUNC_NCEB1 (MTK_PIN_NO(15) | 6) +#define MT8167_PIN_15_EINT15__FUNC_DBG_MON_B_9 (MTK_PIN_NO(15) | 7) + +#define MT8167_PIN_16_EINT16__FUNC_GPIO16 (MTK_PIN_NO(16) | 0) +#define MT8167_PIN_16_EINT16__FUNC_I2S_8CH_BCK (MTK_PIN_NO(16) | 2) +#define MT8167_PIN_16_EINT16__FUNC_TDM_RX_LRCK (MTK_PIN_NO(16) | 3) +#define MT8167_PIN_16_EINT16__FUNC_ANT_SEL3 (MTK_PIN_NO(16) | 4) +#define MT8167_PIN_16_EINT16__FUNC_CONN_MCU_TRST_B (MTK_PIN_NO(16) | 5) +#define MT8167_PIN_16_EINT16__FUNC_NCEB0 (MTK_PIN_NO(16) | 6) +#define MT8167_PIN_16_EINT16__FUNC_DBG_MON_B_10 (MTK_PIN_NO(16) | 7) + +#define MT8167_PIN_17_EINT17__FUNC_GPIO17 (MTK_PIN_NO(17) | 0) +#define MT8167_PIN_17_EINT17__FUNC_I2S_8CH_MCK (MTK_PIN_NO(17) | 2) +#define MT8167_PIN_17_EINT17__FUNC_TDM_RX_DI (MTK_PIN_NO(17) | 3) +#define MT8167_PIN_17_EINT17__FUNC_IDDIG (MTK_PIN_NO(17) | 4) +#define MT8167_PIN_17_EINT17__FUNC_ANT_SEL4 (MTK_PIN_NO(17) | 5) +#define MT8167_PIN_17_EINT17__FUNC_NREB (MTK_PIN_NO(17) | 6) +#define MT8167_PIN_17_EINT17__FUNC_DBG_MON_B_11 (MTK_PIN_NO(17) | 7) + +#define MT8167_PIN_18_EINT18__FUNC_GPIO18 (MTK_PIN_NO(18) | 0) +#define MT8167_PIN_18_EINT18__FUNC_USB_DRVVBUS (MTK_PIN_NO(18) | 2) +#define MT8167_PIN_18_EINT18__FUNC_I2S3_LRCK (MTK_PIN_NO(18) | 3) +#define MT8167_PIN_18_EINT18__FUNC_CLKM1 (MTK_PIN_NO(18) | 4) +#define MT8167_PIN_18_EINT18__FUNC_ANT_SEL3 (MTK_PIN_NO(18) | 5) +#define MT8167_PIN_18_EINT18__FUNC_I2S2_BCK (MTK_PIN_NO(18) | 6) +#define MT8167_PIN_18_EINT18__FUNC_DBG_MON_A_20 (MTK_PIN_NO(18) | 7) + +#define MT8167_PIN_19_EINT19__FUNC_GPIO19 (MTK_PIN_NO(19) | 0) +#define MT8167_PIN_19_EINT19__FUNC_UCTS1 (MTK_PIN_NO(19) | 1) +#define MT8167_PIN_19_EINT19__FUNC_IDDIG (MTK_PIN_NO(19) | 2) +#define MT8167_PIN_19_EINT19__FUNC_I2S3_BCK (MTK_PIN_NO(19) | 3) +#define MT8167_PIN_19_EINT19__FUNC_CLKM2 (MTK_PIN_NO(19) | 4) +#define MT8167_PIN_19_EINT19__FUNC_ANT_SEL4 (MTK_PIN_NO(19) | 5) +#define MT8167_PIN_19_EINT19__FUNC_I2S2_DI (MTK_PIN_NO(19) | 6) +#define MT8167_PIN_19_EINT19__FUNC_DBG_MON_A_21 (MTK_PIN_NO(19) | 7) + +#define MT8167_PIN_20_EINT20__FUNC_GPIO20 (MTK_PIN_NO(20) | 0) +#define MT8167_PIN_20_EINT20__FUNC_URTS1 (MTK_PIN_NO(20) | 1) +#define MT8167_PIN_20_EINT20__FUNC_I2S3_DO (MTK_PIN_NO(20) | 3) +#define MT8167_PIN_20_EINT20__FUNC_CLKM3 (MTK_PIN_NO(20) | 4) +#define MT8167_PIN_20_EINT20__FUNC_ANT_SEL5 (MTK_PIN_NO(20) | 5) +#define MT8167_PIN_20_EINT20__FUNC_I2S2_LRCK (MTK_PIN_NO(20) | 6) +#define MT8167_PIN_20_EINT20__FUNC_DBG_MON_A_22 (MTK_PIN_NO(20) | 7) + +#define MT8167_PIN_21_EINT21__FUNC_GPIO21 (MTK_PIN_NO(21) | 0) +#define MT8167_PIN_21_EINT21__FUNC_NRNB (MTK_PIN_NO(21) | 1) +#define MT8167_PIN_21_EINT21__FUNC_ANT_SEL0 (MTK_PIN_NO(21) | 2) +#define MT8167_PIN_21_EINT21__FUNC_I2S_8CH_DO4 (MTK_PIN_NO(21) | 3) +#define MT8167_PIN_21_EINT21__FUNC_DBG_MON_B_31 (MTK_PIN_NO(21) | 7) + +#define MT8167_PIN_22_EINT22__FUNC_GPIO22 (MTK_PIN_NO(22) | 0) +#define MT8167_PIN_22_EINT22__FUNC_I2S_8CH_DO2 (MTK_PIN_NO(22) | 2) +#define MT8167_PIN_22_EINT22__FUNC_TSF_IN (MTK_PIN_NO(22) | 3) +#define MT8167_PIN_22_EINT22__FUNC_USB_DRVVBUS (MTK_PIN_NO(22) | 4) +#define MT8167_PIN_22_EINT22__FUNC_SPDIF_OUT (MTK_PIN_NO(22) | 5) +#define MT8167_PIN_22_EINT22__FUNC_NRE_C (MTK_PIN_NO(22) | 6) +#define MT8167_PIN_22_EINT22__FUNC_DBG_MON_B_12 (MTK_PIN_NO(22) | 7) + +#define MT8167_PIN_23_EINT23__FUNC_GPIO23 (MTK_PIN_NO(23) | 0) +#define MT8167_PIN_23_EINT23__FUNC_I2S_8CH_DO3 (MTK_PIN_NO(23) | 2) +#define MT8167_PIN_23_EINT23__FUNC_CLKM0 (MTK_PIN_NO(23) | 3) +#define MT8167_PIN_23_EINT23__FUNC_IR (MTK_PIN_NO(23) | 4) +#define MT8167_PIN_23_EINT23__FUNC_SPDIF_IN (MTK_PIN_NO(23) | 5) +#define MT8167_PIN_23_EINT23__FUNC_NDQS_C (MTK_PIN_NO(23) | 6) +#define MT8167_PIN_23_EINT23__FUNC_DBG_MON_B_13 (MTK_PIN_NO(23) | 7) + +#define MT8167_PIN_24_EINT24__FUNC_GPIO24 (MTK_PIN_NO(24) | 0) +#define MT8167_PIN_24_EINT24__FUNC_DPI_D20 (MTK_PIN_NO(24) | 1) +#define MT8167_PIN_24_EINT24__FUNC_DPI_DE (MTK_PIN_NO(24) | 2) +#define MT8167_PIN_24_EINT24__FUNC_ANT_SEL1 (MTK_PIN_NO(24) | 3) +#define MT8167_PIN_24_EINT24__FUNC_UCTS2 (MTK_PIN_NO(24) | 4) +#define MT8167_PIN_24_EINT24__FUNC_PWM_A (MTK_PIN_NO(24) | 5) +#define MT8167_PIN_24_EINT24__FUNC_I2S0_MCK (MTK_PIN_NO(24) | 6) +#define MT8167_PIN_24_EINT24__FUNC_DBG_MON_A_0 (MTK_PIN_NO(24) | 7) + +#define MT8167_PIN_25_EINT25__FUNC_GPIO25 (MTK_PIN_NO(25) | 0) +#define MT8167_PIN_25_EINT25__FUNC_DPI_D19 (MTK_PIN_NO(25) | 1) +#define MT8167_PIN_25_EINT25__FUNC_DPI_VSYNC (MTK_PIN_NO(25) | 2) +#define MT8167_PIN_25_EINT25__FUNC_ANT_SEL0 (MTK_PIN_NO(25) | 3) +#define MT8167_PIN_25_EINT25__FUNC_URTS2 (MTK_PIN_NO(25) | 4) +#define MT8167_PIN_25_EINT25__FUNC_PWM_B (MTK_PIN_NO(25) | 5) +#define MT8167_PIN_25_EINT25__FUNC_I2S_8CH_MCK (MTK_PIN_NO(25) | 6) +#define MT8167_PIN_25_EINT25__FUNC_DBG_MON_A_1 (MTK_PIN_NO(25) | 7) + +#define MT8167_PIN_26_PWRAP_SPI0_MI__FUNC_GPIO26 (MTK_PIN_NO(26) | 0) +#define MT8167_PIN_26_PWRAP_SPI0_MI__FUNC_PWRAP_SPI0_MO (MTK_PIN_NO(26) | 1) +#define MT8167_PIN_26_PWRAP_SPI0_MI__FUNC_PWRAP_SPI0_MI (MTK_PIN_NO(26) | 2) + +#define MT8167_PIN_27_PWRAP_SPI0_MO__FUNC_GPIO27 (MTK_PIN_NO(27) | 0) +#define MT8167_PIN_27_PWRAP_SPI0_MO__FUNC_PWRAP_SPI0_MI (MTK_PIN_NO(27) | 1) +#define MT8167_PIN_27_PWRAP_SPI0_MO__FUNC_PWRAP_SPI0_MO (MTK_PIN_NO(27) | 2) + +#define MT8167_PIN_28_PWRAP_INT__FUNC_GPIO28 (MTK_PIN_NO(28) | 0) +#define MT8167_PIN_28_PWRAP_INT__FUNC_I2S0_MCK (MTK_PIN_NO(28) | 1) +#define MT8167_PIN_28_PWRAP_INT__FUNC_I2S_8CH_MCK (MTK_PIN_NO(28) | 4) +#define MT8167_PIN_28_PWRAP_INT__FUNC_I2S2_MCK (MTK_PIN_NO(28) | 5) +#define MT8167_PIN_28_PWRAP_INT__FUNC_I2S3_MCK (MTK_PIN_NO(28) | 6) + +#define MT8167_PIN_29_PWRAP_SPI0_CK__FUNC_GPIO29 (MTK_PIN_NO(29) | 0) +#define MT8167_PIN_29_PWRAP_SPI0_CK__FUNC_PWRAP_SPI0_CK (MTK_PIN_NO(29) | 1) + +#define MT8167_PIN_30_PWRAP_SPI0_CSN__FUNC_GPIO30 (MTK_PIN_NO(30) | 0) +#define MT8167_PIN_30_PWRAP_SPI0_CSN__FUNC_PWRAP_SPI0_CSN (MTK_PIN_NO(30) | 1) + +#define MT8167_PIN_31_RTC32K_CK__FUNC_GPIO31 (MTK_PIN_NO(31) | 0) +#define MT8167_PIN_31_RTC32K_CK__FUNC_RTC32K_CK (MTK_PIN_NO(31) | 1) + +#define MT8167_PIN_32_WATCHDOG__FUNC_GPIO32 (MTK_PIN_NO(32) | 0) +#define MT8167_PIN_32_WATCHDOG__FUNC_WATCHDOG (MTK_PIN_NO(32) | 1) + +#define MT8167_PIN_33_SRCLKENA__FUNC_GPIO33 (MTK_PIN_NO(33) | 0) +#define MT8167_PIN_33_SRCLKENA__FUNC_SRCLKENA0 (MTK_PIN_NO(33) | 1) + +#define MT8167_PIN_34_URXD2__FUNC_GPIO34 (MTK_PIN_NO(34) | 0) +#define MT8167_PIN_34_URXD2__FUNC_URXD2 (MTK_PIN_NO(34) | 1) +#define MT8167_PIN_34_URXD2__FUNC_DPI_D5 (MTK_PIN_NO(34) | 2) +#define MT8167_PIN_34_URXD2__FUNC_UTXD2 (MTK_PIN_NO(34) | 3) +#define MT8167_PIN_34_URXD2__FUNC_DBG_SCL (MTK_PIN_NO(34) | 4) +#define MT8167_PIN_34_URXD2__FUNC_I2S2_MCK (MTK_PIN_NO(34) | 6) +#define MT8167_PIN_34_URXD2__FUNC_DBG_MON_B_0 (MTK_PIN_NO(34) | 7) + +#define MT8167_PIN_35_UTXD2__FUNC_GPIO35 (MTK_PIN_NO(35) | 0) +#define MT8167_PIN_35_UTXD2__FUNC_UTXD2 (MTK_PIN_NO(35) | 1) +#define MT8167_PIN_35_UTXD2__FUNC_DPI_HSYNC (MTK_PIN_NO(35) | 2) +#define MT8167_PIN_35_UTXD2__FUNC_URXD2 (MTK_PIN_NO(35) | 3) +#define MT8167_PIN_35_UTXD2__FUNC_DBG_SDA (MTK_PIN_NO(35) | 4) +#define MT8167_PIN_35_UTXD2__FUNC_DPI_D18 (MTK_PIN_NO(35) | 5) +#define MT8167_PIN_35_UTXD2__FUNC_I2S3_MCK (MTK_PIN_NO(35) | 6) +#define MT8167_PIN_35_UTXD2__FUNC_DBG_MON_B_1 (MTK_PIN_NO(35) | 7) + +#define MT8167_PIN_36_MRG_CLK__FUNC_GPIO36 (MTK_PIN_NO(36) | 0) +#define MT8167_PIN_36_MRG_CLK__FUNC_MRG_CLK (MTK_PIN_NO(36) | 1) +#define MT8167_PIN_36_MRG_CLK__FUNC_DPI_D4 (MTK_PIN_NO(36) | 2) +#define MT8167_PIN_36_MRG_CLK__FUNC_I2S0_BCK (MTK_PIN_NO(36) | 3) +#define MT8167_PIN_36_MRG_CLK__FUNC_I2S3_BCK (MTK_PIN_NO(36) | 4) +#define MT8167_PIN_36_MRG_CLK__FUNC_PCM0_CLK (MTK_PIN_NO(36) | 5) +#define MT8167_PIN_36_MRG_CLK__FUNC_IR (MTK_PIN_NO(36) | 6) +#define MT8167_PIN_36_MRG_CLK__FUNC_DBG_MON_A_2 (MTK_PIN_NO(36) | 7) + +#define MT8167_PIN_37_MRG_SYNC__FUNC_GPIO37 (MTK_PIN_NO(37) | 0) +#define MT8167_PIN_37_MRG_SYNC__FUNC_MRG_SYNC (MTK_PIN_NO(37) | 1) +#define MT8167_PIN_37_MRG_SYNC__FUNC_DPI_D3 (MTK_PIN_NO(37) | 2) +#define MT8167_PIN_37_MRG_SYNC__FUNC_I2S0_LRCK (MTK_PIN_NO(37) | 3) +#define MT8167_PIN_37_MRG_SYNC__FUNC_I2S3_LRCK (MTK_PIN_NO(37) | 4) +#define MT8167_PIN_37_MRG_SYNC__FUNC_PCM0_SYNC (MTK_PIN_NO(37) | 5) +#define MT8167_PIN_37_MRG_SYNC__FUNC_EXT_COL (MTK_PIN_NO(37) | 6) +#define MT8167_PIN_37_MRG_SYNC__FUNC_DBG_MON_A_3 (MTK_PIN_NO(37) | 7) + +#define MT8167_PIN_38_MRG_DI__FUNC_GPIO38 (MTK_PIN_NO(38) | 0) +#define MT8167_PIN_38_MRG_DI__FUNC_MRG_DI (MTK_PIN_NO(38) | 1) +#define MT8167_PIN_38_MRG_DI__FUNC_DPI_D1 (MTK_PIN_NO(38) | 2) +#define MT8167_PIN_38_MRG_DI__FUNC_I2S0_DI (MTK_PIN_NO(38) | 3) +#define MT8167_PIN_38_MRG_DI__FUNC_I2S3_DO (MTK_PIN_NO(38) | 4) +#define MT8167_PIN_38_MRG_DI__FUNC_PCM0_DI (MTK_PIN_NO(38) | 5) +#define MT8167_PIN_38_MRG_DI__FUNC_EXT_MDIO (MTK_PIN_NO(38) | 6) +#define MT8167_PIN_38_MRG_DI__FUNC_DBG_MON_A_4 (MTK_PIN_NO(38) | 7) + +#define MT8167_PIN_39_MRG_DO__FUNC_GPIO39 (MTK_PIN_NO(39) | 0) +#define MT8167_PIN_39_MRG_DO__FUNC_MRG_DO (MTK_PIN_NO(39) | 1) +#define MT8167_PIN_39_MRG_DO__FUNC_DPI_D2 (MTK_PIN_NO(39) | 2) +#define MT8167_PIN_39_MRG_DO__FUNC_I2S0_MCK (MTK_PIN_NO(39) | 3) +#define MT8167_PIN_39_MRG_DO__FUNC_I2S3_MCK (MTK_PIN_NO(39) | 4) +#define MT8167_PIN_39_MRG_DO__FUNC_PCM0_DO (MTK_PIN_NO(39) | 5) +#define MT8167_PIN_39_MRG_DO__FUNC_EXT_MDC (MTK_PIN_NO(39) | 6) +#define MT8167_PIN_39_MRG_DO__FUNC_DBG_MON_A_5 (MTK_PIN_NO(39) | 7) + +#define MT8167_PIN_40_KPROW0__FUNC_GPIO40 (MTK_PIN_NO(40) | 0) +#define MT8167_PIN_40_KPROW0__FUNC_KPROW0 (MTK_PIN_NO(40) | 1) +#define MT8167_PIN_40_KPROW0__FUNC_IMG_TEST_CK (MTK_PIN_NO(40) | 4) +#define MT8167_PIN_40_KPROW0__FUNC_DBG_MON_B_4 (MTK_PIN_NO(40) | 7) + +#define MT8167_PIN_41_KPROW1__FUNC_GPIO41 (MTK_PIN_NO(41) | 0) +#define MT8167_PIN_41_KPROW1__FUNC_KPROW1 (MTK_PIN_NO(41) | 1) +#define MT8167_PIN_41_KPROW1__FUNC_IDDIG (MTK_PIN_NO(41) | 2) +#define MT8167_PIN_41_KPROW1__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(41) | 3) +#define MT8167_PIN_41_KPROW1__FUNC_MFG_TEST_CK (MTK_PIN_NO(41) | 4) +#define MT8167_PIN_41_KPROW1__FUNC_DBG_MON_B_5 (MTK_PIN_NO(41) | 7) + +#define MT8167_PIN_42_KPCOL0__FUNC_GPIO42 (MTK_PIN_NO(42) | 0) +#define MT8167_PIN_42_KPCOL0__FUNC_KPCOL0 (MTK_PIN_NO(42) | 1) +#define MT8167_PIN_42_KPCOL0__FUNC_DBG_MON_B_6 (MTK_PIN_NO(42) | 7) + +#define MT8167_PIN_43_KPCOL1__FUNC_GPIO43 (MTK_PIN_NO(43) | 0) +#define MT8167_PIN_43_KPCOL1__FUNC_KPCOL1 (MTK_PIN_NO(43) | 1) +#define MT8167_PIN_43_KPCOL1__FUNC_USB_DRVVBUS (MTK_PIN_NO(43) | 2) +#define MT8167_PIN_43_KPCOL1__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(43) | 3) +#define MT8167_PIN_43_KPCOL1__FUNC_TSF_IN (MTK_PIN_NO(43) | 4) +#define MT8167_PIN_43_KPCOL1__FUNC_DFD_NTRST_XI (MTK_PIN_NO(43) | 5) +#define MT8167_PIN_43_KPCOL1__FUNC_UDI_NTRST_XI (MTK_PIN_NO(43) | 6) +#define MT8167_PIN_43_KPCOL1__FUNC_DBG_MON_B_7 (MTK_PIN_NO(43) | 7) + +#define MT8167_PIN_44_JTMS__FUNC_GPIO44 (MTK_PIN_NO(44) | 0) +#define MT8167_PIN_44_JTMS__FUNC_JTMS (MTK_PIN_NO(44) | 1) +#define MT8167_PIN_44_JTMS__FUNC_CONN_MCU_TMS (MTK_PIN_NO(44) | 2) +#define MT8167_PIN_44_JTMS__FUNC_CONN_MCU_AICE_JMSC (MTK_PIN_NO(44) | 3) +#define MT8167_PIN_44_JTMS__FUNC_GPUDFD_TMS_XI (MTK_PIN_NO(44) | 4) +#define MT8167_PIN_44_JTMS__FUNC_DFD_TMS_XI (MTK_PIN_NO(44) | 5) +#define MT8167_PIN_44_JTMS__FUNC_UDI_TMS_XI (MTK_PIN_NO(44) | 6) + +#define MT8167_PIN_45_JTCK__FUNC_GPIO45 (MTK_PIN_NO(45) | 0) +#define MT8167_PIN_45_JTCK__FUNC_JTCK (MTK_PIN_NO(45) | 1) +#define MT8167_PIN_45_JTCK__FUNC_CONN_MCU_TCK (MTK_PIN_NO(45) | 2) +#define MT8167_PIN_45_JTCK__FUNC_CONN_MCU_AICE_JCKC (MTK_PIN_NO(45) | 3) +#define MT8167_PIN_45_JTCK__FUNC_GPUDFD_TCK_XI (MTK_PIN_NO(45) | 4) +#define MT8167_PIN_45_JTCK__FUNC_DFD_TCK_XI (MTK_PIN_NO(45) | 5) +#define MT8167_PIN_45_JTCK__FUNC_UDI_TCK_XI (MTK_PIN_NO(45) | 6) + +#define MT8167_PIN_46_JTDI__FUNC_GPIO46 (MTK_PIN_NO(46) | 0) +#define MT8167_PIN_46_JTDI__FUNC_JTDI (MTK_PIN_NO(46) | 1) +#define MT8167_PIN_46_JTDI__FUNC_CONN_MCU_TDI (MTK_PIN_NO(46) | 2) +#define MT8167_PIN_46_JTDI__FUNC_GPUDFD_TDI_XI (MTK_PIN_NO(46) | 4) +#define MT8167_PIN_46_JTDI__FUNC_DFD_TDI_XI (MTK_PIN_NO(46) | 5) +#define MT8167_PIN_46_JTDI__FUNC_UDI_TDI_XI (MTK_PIN_NO(46) | 6) + +#define MT8167_PIN_47_JTDO__FUNC_GPIO47 (MTK_PIN_NO(47) | 0) +#define MT8167_PIN_47_JTDO__FUNC_JTDO (MTK_PIN_NO(47) | 1) +#define MT8167_PIN_47_JTDO__FUNC_CONN_MCU_TDO (MTK_PIN_NO(47) | 2) +#define MT8167_PIN_47_JTDO__FUNC_GPUDFD_TDO (MTK_PIN_NO(47) | 4) +#define MT8167_PIN_47_JTDO__FUNC_DFD_TDO (MTK_PIN_NO(47) | 5) +#define MT8167_PIN_47_JTDO__FUNC_UDI_TDO (MTK_PIN_NO(47) | 6) + +#define MT8167_PIN_48_SPI_CS__FUNC_GPIO48 (MTK_PIN_NO(48) | 0) +#define MT8167_PIN_48_SPI_CS__FUNC_SPI_CSB (MTK_PIN_NO(48) | 1) +#define MT8167_PIN_48_SPI_CS__FUNC_I2S0_DI (MTK_PIN_NO(48) | 3) +#define MT8167_PIN_48_SPI_CS__FUNC_I2S2_BCK (MTK_PIN_NO(48) | 4) +#define MT8167_PIN_48_SPI_CS__FUNC_DBG_MON_A_23 (MTK_PIN_NO(48) | 7) + +#define MT8167_PIN_49_SPI_CK__FUNC_GPIO49 (MTK_PIN_NO(49) | 0) +#define MT8167_PIN_49_SPI_CK__FUNC_SPI_CLK (MTK_PIN_NO(49) | 1) +#define MT8167_PIN_49_SPI_CK__FUNC_I2S0_LRCK (MTK_PIN_NO(49) | 3) +#define MT8167_PIN_49_SPI_CK__FUNC_I2S2_DI (MTK_PIN_NO(49) | 4) +#define MT8167_PIN_49_SPI_CK__FUNC_DBG_MON_A_24 (MTK_PIN_NO(49) | 7) + +#define MT8167_PIN_50_SPI_MI__FUNC_GPIO50 (MTK_PIN_NO(50) | 0) +#define MT8167_PIN_50_SPI_MI__FUNC_SPI_MI (MTK_PIN_NO(50) | 1) +#define MT8167_PIN_50_SPI_MI__FUNC_SPI_MO (MTK_PIN_NO(50) | 2) +#define MT8167_PIN_50_SPI_MI__FUNC_I2S0_BCK (MTK_PIN_NO(50) | 3) +#define MT8167_PIN_50_SPI_MI__FUNC_I2S2_LRCK (MTK_PIN_NO(50) | 4) +#define MT8167_PIN_50_SPI_MI__FUNC_DBG_MON_A_25 (MTK_PIN_NO(50) | 7) + +#define MT8167_PIN_51_SPI_MO__FUNC_GPIO51 (MTK_PIN_NO(51) | 0) +#define MT8167_PIN_51_SPI_MO__FUNC_SPI_MO (MTK_PIN_NO(51) | 1) +#define MT8167_PIN_51_SPI_MO__FUNC_SPI_MI (MTK_PIN_NO(51) | 2) +#define MT8167_PIN_51_SPI_MO__FUNC_I2S0_MCK (MTK_PIN_NO(51) | 3) +#define MT8167_PIN_51_SPI_MO__FUNC_I2S2_MCK (MTK_PIN_NO(51) | 4) +#define MT8167_PIN_51_SPI_MO__FUNC_DBG_MON_A_26 (MTK_PIN_NO(51) | 7) + +#define MT8167_PIN_52_SDA1__FUNC_GPIO52 (MTK_PIN_NO(52) | 0) +#define MT8167_PIN_52_SDA1__FUNC_SDA1_0 (MTK_PIN_NO(52) | 1) + +#define MT8167_PIN_53_SCL1__FUNC_GPIO53 (MTK_PIN_NO(53) | 0) +#define MT8167_PIN_53_SCL1__FUNC_SCL1_0 (MTK_PIN_NO(53) | 1) + +#define MT8167_PIN_54_DISP_PWM__FUNC_GPIO54 (MTK_PIN_NO(54) | 0) +#define MT8167_PIN_54_DISP_PWM__FUNC_DISP_PWM (MTK_PIN_NO(54) | 1) +#define MT8167_PIN_54_DISP_PWM__FUNC_PWM_B (MTK_PIN_NO(54) | 2) +#define MT8167_PIN_54_DISP_PWM__FUNC_DBG_MON_B_2 (MTK_PIN_NO(54) | 7) + +#define MT8167_PIN_55_I2S_DATA_IN__FUNC_GPIO55 (MTK_PIN_NO(55) | 0) +#define MT8167_PIN_55_I2S_DATA_IN__FUNC_I2S0_DI (MTK_PIN_NO(55) | 1) +#define MT8167_PIN_55_I2S_DATA_IN__FUNC_UCTS0 (MTK_PIN_NO(55) | 2) +#define MT8167_PIN_55_I2S_DATA_IN__FUNC_I2S3_DO (MTK_PIN_NO(55) | 3) +#define MT8167_PIN_55_I2S_DATA_IN__FUNC_I2S_8CH_DO1 (MTK_PIN_NO(55) | 4) +#define MT8167_PIN_55_I2S_DATA_IN__FUNC_PWM_A (MTK_PIN_NO(55) | 5) +#define MT8167_PIN_55_I2S_DATA_IN__FUNC_I2S2_BCK (MTK_PIN_NO(55) | 6) +#define MT8167_PIN_55_I2S_DATA_IN__FUNC_DBG_MON_A_28 (MTK_PIN_NO(55) | 7) + +#define MT8167_PIN_56_I2S_LRCK__FUNC_GPIO56 (MTK_PIN_NO(56) | 0) +#define MT8167_PIN_56_I2S_LRCK__FUNC_I2S0_LRCK (MTK_PIN_NO(56) | 1) +#define MT8167_PIN_56_I2S_LRCK__FUNC_I2S3_LRCK (MTK_PIN_NO(56) | 3) +#define MT8167_PIN_56_I2S_LRCK__FUNC_I2S_8CH_LRCK (MTK_PIN_NO(56) | 4) +#define MT8167_PIN_56_I2S_LRCK__FUNC_PWM_B (MTK_PIN_NO(56) | 5) +#define MT8167_PIN_56_I2S_LRCK__FUNC_I2S2_DI (MTK_PIN_NO(56) | 6) +#define MT8167_PIN_56_I2S_LRCK__FUNC_DBG_MON_A_29 (MTK_PIN_NO(56) | 7) + +#define MT8167_PIN_57_I2S_BCK__FUNC_GPIO57 (MTK_PIN_NO(57) | 0) +#define MT8167_PIN_57_I2S_BCK__FUNC_I2S0_BCK (MTK_PIN_NO(57) | 1) +#define MT8167_PIN_57_I2S_BCK__FUNC_URTS0 (MTK_PIN_NO(57) | 2) +#define MT8167_PIN_57_I2S_BCK__FUNC_I2S3_BCK (MTK_PIN_NO(57) | 3) +#define MT8167_PIN_57_I2S_BCK__FUNC_I2S_8CH_BCK (MTK_PIN_NO(57) | 4) +#define MT8167_PIN_57_I2S_BCK__FUNC_PWM_C (MTK_PIN_NO(57) | 5) +#define MT8167_PIN_57_I2S_BCK__FUNC_I2S2_LRCK (MTK_PIN_NO(57) | 6) +#define MT8167_PIN_57_I2S_BCK__FUNC_DBG_MON_A_30 (MTK_PIN_NO(57) | 7) + +#define MT8167_PIN_58_SDA0__FUNC_GPIO58 (MTK_PIN_NO(58) | 0) +#define MT8167_PIN_58_SDA0__FUNC_SDA0_0 (MTK_PIN_NO(58) | 1) + +#define MT8167_PIN_59_SCL0__FUNC_GPIO59 (MTK_PIN_NO(59) | 0) +#define MT8167_PIN_59_SCL0__FUNC_SCL0_0 (MTK_PIN_NO(59) | 1) + +#define MT8167_PIN_60_SDA2__FUNC_GPIO60 (MTK_PIN_NO(60) | 0) +#define MT8167_PIN_60_SDA2__FUNC_SDA2_0 (MTK_PIN_NO(60) | 1) +#define MT8167_PIN_60_SDA2__FUNC_PWM_B (MTK_PIN_NO(60) | 2) + +#define MT8167_PIN_61_SCL2__FUNC_GPIO61 (MTK_PIN_NO(61) | 0) +#define MT8167_PIN_61_SCL2__FUNC_SCL2_0 (MTK_PIN_NO(61) | 1) +#define MT8167_PIN_61_SCL2__FUNC_PWM_C (MTK_PIN_NO(61) | 2) + +#define MT8167_PIN_62_URXD0__FUNC_GPIO62 (MTK_PIN_NO(62) | 0) +#define MT8167_PIN_62_URXD0__FUNC_URXD0 (MTK_PIN_NO(62) | 1) +#define MT8167_PIN_62_URXD0__FUNC_UTXD0 (MTK_PIN_NO(62) | 2) + +#define MT8167_PIN_63_UTXD0__FUNC_GPIO63 (MTK_PIN_NO(63) | 0) +#define MT8167_PIN_63_UTXD0__FUNC_UTXD0 (MTK_PIN_NO(63) | 1) +#define MT8167_PIN_63_UTXD0__FUNC_URXD0 (MTK_PIN_NO(63) | 2) + +#define MT8167_PIN_64_URXD1__FUNC_GPIO64 (MTK_PIN_NO(64) | 0) +#define MT8167_PIN_64_URXD1__FUNC_URXD1 (MTK_PIN_NO(64) | 1) +#define MT8167_PIN_64_URXD1__FUNC_UTXD1 (MTK_PIN_NO(64) | 2) +#define MT8167_PIN_64_URXD1__FUNC_DBG_MON_A_27 (MTK_PIN_NO(64) | 7) + +#define MT8167_PIN_65_UTXD1__FUNC_GPIO65 (MTK_PIN_NO(65) | 0) +#define MT8167_PIN_65_UTXD1__FUNC_UTXD1 (MTK_PIN_NO(65) | 1) +#define MT8167_PIN_65_UTXD1__FUNC_URXD1 (MTK_PIN_NO(65) | 2) +#define MT8167_PIN_65_UTXD1__FUNC_DBG_MON_A_31 (MTK_PIN_NO(65) | 7) + +#define MT8167_PIN_66_LCM_RST__FUNC_GPIO66 (MTK_PIN_NO(66) | 0) +#define MT8167_PIN_66_LCM_RST__FUNC_LCM_RST (MTK_PIN_NO(66) | 1) +#define MT8167_PIN_66_LCM_RST__FUNC_I2S0_MCK (MTK_PIN_NO(66) | 3) +#define MT8167_PIN_66_LCM_RST__FUNC_DBG_MON_B_3 (MTK_PIN_NO(66) | 7) + +#define MT8167_PIN_67_DSI_TE__FUNC_GPIO67 (MTK_PIN_NO(67) | 0) +#define MT8167_PIN_67_DSI_TE__FUNC_DSI_TE (MTK_PIN_NO(67) | 1) +#define MT8167_PIN_67_DSI_TE__FUNC_I2S_8CH_MCK (MTK_PIN_NO(67) | 3) +#define MT8167_PIN_67_DSI_TE__FUNC_DBG_MON_B_14 (MTK_PIN_NO(67) | 7) + +#define MT8167_PIN_68_MSDC2_CMD__FUNC_GPIO68 (MTK_PIN_NO(68) | 0) +#define MT8167_PIN_68_MSDC2_CMD__FUNC_MSDC2_CMD (MTK_PIN_NO(68) | 1) +#define MT8167_PIN_68_MSDC2_CMD__FUNC_I2S_8CH_DO4 (MTK_PIN_NO(68) | 2) +#define MT8167_PIN_68_MSDC2_CMD__FUNC_SDA1_0 (MTK_PIN_NO(68) | 3) +#define MT8167_PIN_68_MSDC2_CMD__FUNC_USB_SDA (MTK_PIN_NO(68) | 5) +#define MT8167_PIN_68_MSDC2_CMD__FUNC_I2S3_BCK (MTK_PIN_NO(68) | 6) +#define MT8167_PIN_68_MSDC2_CMD__FUNC_DBG_MON_B_15 (MTK_PIN_NO(68) | 7) + +#define MT8167_PIN_69_MSDC2_CLK__FUNC_GPIO69 (MTK_PIN_NO(69) | 0) +#define MT8167_PIN_69_MSDC2_CLK__FUNC_MSDC2_CLK (MTK_PIN_NO(69) | 1) +#define MT8167_PIN_69_MSDC2_CLK__FUNC_I2S_8CH_DO3 (MTK_PIN_NO(69) | 2) +#define MT8167_PIN_69_MSDC2_CLK__FUNC_SCL1_0 (MTK_PIN_NO(69) | 3) +#define MT8167_PIN_69_MSDC2_CLK__FUNC_DPI_D21 (MTK_PIN_NO(69) | 4) +#define MT8167_PIN_69_MSDC2_CLK__FUNC_USB_SCL (MTK_PIN_NO(69) | 5) +#define MT8167_PIN_69_MSDC2_CLK__FUNC_I2S3_LRCK (MTK_PIN_NO(69) | 6) +#define MT8167_PIN_69_MSDC2_CLK__FUNC_DBG_MON_B_16 (MTK_PIN_NO(69) | 7) + +#define MT8167_PIN_70_MSDC2_DAT0__FUNC_GPIO70 (MTK_PIN_NO(70) | 0) +#define MT8167_PIN_70_MSDC2_DAT0__FUNC_MSDC2_DAT0 (MTK_PIN_NO(70) | 1) +#define MT8167_PIN_70_MSDC2_DAT0__FUNC_I2S_8CH_DO2 (MTK_PIN_NO(70) | 2) +#define MT8167_PIN_70_MSDC2_DAT0__FUNC_DPI_D22 (MTK_PIN_NO(70) | 4) +#define MT8167_PIN_70_MSDC2_DAT0__FUNC_UTXD0 (MTK_PIN_NO(70) | 5) +#define MT8167_PIN_70_MSDC2_DAT0__FUNC_I2S3_DO (MTK_PIN_NO(70) | 6) +#define MT8167_PIN_70_MSDC2_DAT0__FUNC_DBG_MON_B_17 (MTK_PIN_NO(70) | 7) + +#define MT8167_PIN_71_MSDC2_DAT1__FUNC_GPIO71 (MTK_PIN_NO(71) | 0) +#define MT8167_PIN_71_MSDC2_DAT1__FUNC_MSDC2_DAT1 (MTK_PIN_NO(71) | 1) +#define MT8167_PIN_71_MSDC2_DAT1__FUNC_I2S_8CH_DO1 (MTK_PIN_NO(71) | 2) +#define MT8167_PIN_71_MSDC2_DAT1__FUNC_PWM_A (MTK_PIN_NO(71) | 3) +#define MT8167_PIN_71_MSDC2_DAT1__FUNC_I2S3_MCK (MTK_PIN_NO(71) | 4) +#define MT8167_PIN_71_MSDC2_DAT1__FUNC_URXD0 (MTK_PIN_NO(71) | 5) +#define MT8167_PIN_71_MSDC2_DAT1__FUNC_PWM_B (MTK_PIN_NO(71) | 6) +#define MT8167_PIN_71_MSDC2_DAT1__FUNC_DBG_MON_B_18 (MTK_PIN_NO(71) | 7) + +#define MT8167_PIN_72_MSDC2_DAT2__FUNC_GPIO72 (MTK_PIN_NO(72) | 0) +#define MT8167_PIN_72_MSDC2_DAT2__FUNC_MSDC2_DAT2 (MTK_PIN_NO(72) | 1) +#define MT8167_PIN_72_MSDC2_DAT2__FUNC_I2S_8CH_LRCK (MTK_PIN_NO(72) | 2) +#define MT8167_PIN_72_MSDC2_DAT2__FUNC_SDA2_0 (MTK_PIN_NO(72) | 3) +#define MT8167_PIN_72_MSDC2_DAT2__FUNC_DPI_D23 (MTK_PIN_NO(72) | 4) +#define MT8167_PIN_72_MSDC2_DAT2__FUNC_UTXD1 (MTK_PIN_NO(72) | 5) +#define MT8167_PIN_72_MSDC2_DAT2__FUNC_PWM_C (MTK_PIN_NO(72) | 6) +#define MT8167_PIN_72_MSDC2_DAT2__FUNC_DBG_MON_B_19 (MTK_PIN_NO(72) | 7) + +#define MT8167_PIN_73_MSDC2_DAT3__FUNC_GPIO73 (MTK_PIN_NO(73) | 0) +#define MT8167_PIN_73_MSDC2_DAT3__FUNC_MSDC2_DAT3 (MTK_PIN_NO(73) | 1) +#define MT8167_PIN_73_MSDC2_DAT3__FUNC_I2S_8CH_BCK (MTK_PIN_NO(73) | 2) +#define MT8167_PIN_73_MSDC2_DAT3__FUNC_SCL2_0 (MTK_PIN_NO(73) | 3) +#define MT8167_PIN_73_MSDC2_DAT3__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(73) | 4) +#define MT8167_PIN_73_MSDC2_DAT3__FUNC_URXD1 (MTK_PIN_NO(73) | 5) +#define MT8167_PIN_73_MSDC2_DAT3__FUNC_PWM_A (MTK_PIN_NO(73) | 6) +#define MT8167_PIN_73_MSDC2_DAT3__FUNC_DBG_MON_B_20 (MTK_PIN_NO(73) | 7) + +#define MT8167_PIN_74_TDN3__FUNC_GPI74 (MTK_PIN_NO(74) | 0) +#define MT8167_PIN_74_TDN3__FUNC_TDN3 (MTK_PIN_NO(74) | 1) + +#define MT8167_PIN_75_TDP3__FUNC_GPI75 (MTK_PIN_NO(75) | 0) +#define MT8167_PIN_75_TDP3__FUNC_TDP3 (MTK_PIN_NO(75) | 1) + +#define MT8167_PIN_76_TDN2__FUNC_GPI76 (MTK_PIN_NO(76) | 0) +#define MT8167_PIN_76_TDN2__FUNC_TDN2 (MTK_PIN_NO(76) | 1) + +#define MT8167_PIN_77_TDP2__FUNC_GPI77 (MTK_PIN_NO(77) | 0) +#define MT8167_PIN_77_TDP2__FUNC_TDP2 (MTK_PIN_NO(77) | 1) + +#define MT8167_PIN_78_TCN__FUNC_GPI78 (MTK_PIN_NO(78) | 0) +#define MT8167_PIN_78_TCN__FUNC_TCN (MTK_PIN_NO(78) | 1) + +#define MT8167_PIN_79_TCP__FUNC_GPI79 (MTK_PIN_NO(79) | 0) +#define MT8167_PIN_79_TCP__FUNC_TCP (MTK_PIN_NO(79) | 1) + +#define MT8167_PIN_80_TDN1__FUNC_GPI80 (MTK_PIN_NO(80) | 0) +#define MT8167_PIN_80_TDN1__FUNC_TDN1 (MTK_PIN_NO(80) | 1) + +#define MT8167_PIN_81_TDP1__FUNC_GPI81 (MTK_PIN_NO(81) | 0) +#define MT8167_PIN_81_TDP1__FUNC_TDP1 (MTK_PIN_NO(81) | 1) + +#define MT8167_PIN_82_TDN0__FUNC_GPI82 (MTK_PIN_NO(82) | 0) +#define MT8167_PIN_82_TDN0__FUNC_TDN0 (MTK_PIN_NO(82) | 1) + +#define MT8167_PIN_83_TDP0__FUNC_GPI83 (MTK_PIN_NO(83) | 0) +#define MT8167_PIN_83_TDP0__FUNC_TDP0 (MTK_PIN_NO(83) | 1) + +#define MT8167_PIN_84_RDN0__FUNC_GPI84 (MTK_PIN_NO(84) | 0) +#define MT8167_PIN_84_RDN0__FUNC_RDN0 (MTK_PIN_NO(84) | 1) + +#define MT8167_PIN_85_RDP0__FUNC_GPI85 (MTK_PIN_NO(85) | 0) +#define MT8167_PIN_85_RDP0__FUNC_RDP0 (MTK_PIN_NO(85) | 1) + +#define MT8167_PIN_86_RDN1__FUNC_GPI86 (MTK_PIN_NO(86) | 0) +#define MT8167_PIN_86_RDN1__FUNC_RDN1 (MTK_PIN_NO(86) | 1) + +#define MT8167_PIN_87_RDP1__FUNC_GPI87 (MTK_PIN_NO(87) | 0) +#define MT8167_PIN_87_RDP1__FUNC_RDP1 (MTK_PIN_NO(87) | 1) + +#define MT8167_PIN_88_RCN__FUNC_GPI88 (MTK_PIN_NO(88) | 0) +#define MT8167_PIN_88_RCN__FUNC_RCN (MTK_PIN_NO(88) | 1) + +#define MT8167_PIN_89_RCP__FUNC_GPI89 (MTK_PIN_NO(89) | 0) +#define MT8167_PIN_89_RCP__FUNC_RCP (MTK_PIN_NO(89) | 1) + +#define MT8167_PIN_90_RDN2__FUNC_GPI90 (MTK_PIN_NO(90) | 0) +#define MT8167_PIN_90_RDN2__FUNC_RDN2 (MTK_PIN_NO(90) | 1) +#define MT8167_PIN_90_RDN2__FUNC_CMDAT8 (MTK_PIN_NO(90) | 2) + +#define MT8167_PIN_91_RDP2__FUNC_GPI91 (MTK_PIN_NO(91) | 0) +#define MT8167_PIN_91_RDP2__FUNC_RDP2 (MTK_PIN_NO(91) | 1) +#define MT8167_PIN_91_RDP2__FUNC_CMDAT9 (MTK_PIN_NO(91) | 2) + +#define MT8167_PIN_92_RDN3__FUNC_GPI92 (MTK_PIN_NO(92) | 0) +#define MT8167_PIN_92_RDN3__FUNC_RDN3 (MTK_PIN_NO(92) | 1) +#define MT8167_PIN_92_RDN3__FUNC_CMDAT4 (MTK_PIN_NO(92) | 2) + +#define MT8167_PIN_93_RDP3__FUNC_GPI93 (MTK_PIN_NO(93) | 0) +#define MT8167_PIN_93_RDP3__FUNC_RDP3 (MTK_PIN_NO(93) | 1) +#define MT8167_PIN_93_RDP3__FUNC_CMDAT5 (MTK_PIN_NO(93) | 2) + +#define MT8167_PIN_94_RCN_A__FUNC_GPI94 (MTK_PIN_NO(94) | 0) +#define MT8167_PIN_94_RCN_A__FUNC_RCN_A (MTK_PIN_NO(94) | 1) +#define MT8167_PIN_94_RCN_A__FUNC_CMDAT6 (MTK_PIN_NO(94) | 2) + +#define MT8167_PIN_95_RCP_A__FUNC_GPI95 (MTK_PIN_NO(95) | 0) +#define MT8167_PIN_95_RCP_A__FUNC_RCP_A (MTK_PIN_NO(95) | 1) +#define MT8167_PIN_95_RCP_A__FUNC_CMDAT7 (MTK_PIN_NO(95) | 2) + +#define MT8167_PIN_96_RDN1_A__FUNC_GPI96 (MTK_PIN_NO(96) | 0) +#define MT8167_PIN_96_RDN1_A__FUNC_RDN1_A (MTK_PIN_NO(96) | 1) +#define MT8167_PIN_96_RDN1_A__FUNC_CMDAT2 (MTK_PIN_NO(96) | 2) +#define MT8167_PIN_96_RDN1_A__FUNC_CMCSD2 (MTK_PIN_NO(96) | 3) + +#define MT8167_PIN_97_RDP1_A__FUNC_GPI97 (MTK_PIN_NO(97) | 0) +#define MT8167_PIN_97_RDP1_A__FUNC_RDP1_A (MTK_PIN_NO(97) | 1) +#define MT8167_PIN_97_RDP1_A__FUNC_CMDAT3 (MTK_PIN_NO(97) | 2) +#define MT8167_PIN_97_RDP1_A__FUNC_CMCSD3 (MTK_PIN_NO(97) | 3) + +#define MT8167_PIN_98_RDN0_A__FUNC_GPI98 (MTK_PIN_NO(98) | 0) +#define MT8167_PIN_98_RDN0_A__FUNC_RDN0_A (MTK_PIN_NO(98) | 1) +#define MT8167_PIN_98_RDN0_A__FUNC_CMHSYNC (MTK_PIN_NO(98) | 2) + +#define MT8167_PIN_99_RDP0_A__FUNC_GPI99 (MTK_PIN_NO(99) | 0) +#define MT8167_PIN_99_RDP0_A__FUNC_RDP0_A (MTK_PIN_NO(99) | 1) +#define MT8167_PIN_99_RDP0_A__FUNC_CMVSYNC (MTK_PIN_NO(99) | 2) + +#define MT8167_PIN_100_CMDAT0__FUNC_GPIO100 (MTK_PIN_NO(100) | 0) +#define MT8167_PIN_100_CMDAT0__FUNC_CMDAT0 (MTK_PIN_NO(100) | 1) +#define MT8167_PIN_100_CMDAT0__FUNC_CMCSD0 (MTK_PIN_NO(100) | 2) +#define MT8167_PIN_100_CMDAT0__FUNC_ANT_SEL2 (MTK_PIN_NO(100) | 3) +#define MT8167_PIN_100_CMDAT0__FUNC_TDM_RX_MCK (MTK_PIN_NO(100) | 5) +#define MT8167_PIN_100_CMDAT0__FUNC_DBG_MON_B_21 (MTK_PIN_NO(100) | 7) + +#define MT8167_PIN_101_CMDAT1__FUNC_GPIO101 (MTK_PIN_NO(101) | 0) +#define MT8167_PIN_101_CMDAT1__FUNC_CMDAT1 (MTK_PIN_NO(101) | 1) +#define MT8167_PIN_101_CMDAT1__FUNC_CMCSD1 (MTK_PIN_NO(101) | 2) +#define MT8167_PIN_101_CMDAT1__FUNC_ANT_SEL3 (MTK_PIN_NO(101) | 3) +#define MT8167_PIN_101_CMDAT1__FUNC_CMFLASH (MTK_PIN_NO(101) | 4) +#define MT8167_PIN_101_CMDAT1__FUNC_TDM_RX_BCK (MTK_PIN_NO(101) | 5) +#define MT8167_PIN_101_CMDAT1__FUNC_DBG_MON_B_22 (MTK_PIN_NO(101) | 7) + +#define MT8167_PIN_102_CMMCLK__FUNC_GPIO102 (MTK_PIN_NO(102) | 0) +#define MT8167_PIN_102_CMMCLK__FUNC_CMMCLK (MTK_PIN_NO(102) | 1) +#define MT8167_PIN_102_CMMCLK__FUNC_ANT_SEL4 (MTK_PIN_NO(102) | 3) +#define MT8167_PIN_102_CMMCLK__FUNC_TDM_RX_LRCK (MTK_PIN_NO(102) | 5) +#define MT8167_PIN_102_CMMCLK__FUNC_DBG_MON_B_23 (MTK_PIN_NO(102) | 7) + +#define MT8167_PIN_103_CMPCLK__FUNC_GPIO103 (MTK_PIN_NO(103) | 0) +#define MT8167_PIN_103_CMPCLK__FUNC_CMPCLK (MTK_PIN_NO(103) | 1) +#define MT8167_PIN_103_CMPCLK__FUNC_CMCSK (MTK_PIN_NO(103) | 2) +#define MT8167_PIN_103_CMPCLK__FUNC_ANT_SEL5 (MTK_PIN_NO(103) | 3) +#define MT8167_PIN_103_CMPCLK__FUNC_TDM_RX_DI (MTK_PIN_NO(103) | 5) +#define MT8167_PIN_103_CMPCLK__FUNC_DBG_MON_B_24 (MTK_PIN_NO(103) | 7) + +#define MT8167_PIN_104_MSDC1_CMD__FUNC_GPIO104 (MTK_PIN_NO(104) | 0) +#define MT8167_PIN_104_MSDC1_CMD__FUNC_MSDC1_CMD (MTK_PIN_NO(104) | 1) +#define MT8167_PIN_104_MSDC1_CMD__FUNC_SQICS (MTK_PIN_NO(104) | 4) +#define MT8167_PIN_104_MSDC1_CMD__FUNC_DBG_MON_B_25 (MTK_PIN_NO(104) | 7) + +#define MT8167_PIN_105_MSDC1_CLK__FUNC_GPIO105 (MTK_PIN_NO(105) | 0) +#define MT8167_PIN_105_MSDC1_CLK__FUNC_MSDC1_CLK (MTK_PIN_NO(105) | 1) +#define MT8167_PIN_105_MSDC1_CLK__FUNC_UDI_NTRST_XI (MTK_PIN_NO(105) | 2) +#define MT8167_PIN_105_MSDC1_CLK__FUNC_DFD_NTRST_XI (MTK_PIN_NO(105) | 3) +#define MT8167_PIN_105_MSDC1_CLK__FUNC_SQISO (MTK_PIN_NO(105) | 4) +#define MT8167_PIN_105_MSDC1_CLK__FUNC_GPUEJ_NTRST_XI (MTK_PIN_NO(105) | 5) +#define MT8167_PIN_105_MSDC1_CLK__FUNC_DBG_MON_B_26 (MTK_PIN_NO(105) | 7) + +#define MT8167_PIN_106_MSDC1_DAT0__FUNC_GPIO106 (MTK_PIN_NO(106) | 0) +#define MT8167_PIN_106_MSDC1_DAT0__FUNC_MSDC1_DAT0 (MTK_PIN_NO(106) | 1) +#define MT8167_PIN_106_MSDC1_DAT0__FUNC_UDI_TMS_XI (MTK_PIN_NO(106) | 2) +#define MT8167_PIN_106_MSDC1_DAT0__FUNC_DFD_TMS_XI (MTK_PIN_NO(106) | 3) +#define MT8167_PIN_106_MSDC1_DAT0__FUNC_SQISI (MTK_PIN_NO(106) | 4) +#define MT8167_PIN_106_MSDC1_DAT0__FUNC_GPUEJ_TMS_XI (MTK_PIN_NO(106) | 5) +#define MT8167_PIN_106_MSDC1_DAT0__FUNC_DBG_MON_B_27 (MTK_PIN_NO(106) | 7) + +#define MT8167_PIN_107_MSDC1_DAT1__FUNC_GPIO107 (MTK_PIN_NO(107) | 0) +#define MT8167_PIN_107_MSDC1_DAT1__FUNC_MSDC1_DAT1 (MTK_PIN_NO(107) | 1) +#define MT8167_PIN_107_MSDC1_DAT1__FUNC_UDI_TCK_XI (MTK_PIN_NO(107) | 2) +#define MT8167_PIN_107_MSDC1_DAT1__FUNC_DFD_TCK_XI (MTK_PIN_NO(107) | 3) +#define MT8167_PIN_107_MSDC1_DAT1__FUNC_SQIWP (MTK_PIN_NO(107) | 4) +#define MT8167_PIN_107_MSDC1_DAT1__FUNC_GPUEJ_TCK_XI (MTK_PIN_NO(107) | 5) +#define MT8167_PIN_107_MSDC1_DAT1__FUNC_DBG_MON_B_28 (MTK_PIN_NO(107) | 7) + +#define MT8167_PIN_108_MSDC1_DAT2__FUNC_GPIO108 (MTK_PIN_NO(108) | 0) +#define MT8167_PIN_108_MSDC1_DAT2__FUNC_MSDC1_DAT2 (MTK_PIN_NO(108) | 1) +#define MT8167_PIN_108_MSDC1_DAT2__FUNC_UDI_TDI_XI (MTK_PIN_NO(108) | 2) +#define MT8167_PIN_108_MSDC1_DAT2__FUNC_DFD_TDI_XI (MTK_PIN_NO(108) | 3) +#define MT8167_PIN_108_MSDC1_DAT2__FUNC_SQIRST (MTK_PIN_NO(108) | 4) +#define MT8167_PIN_108_MSDC1_DAT2__FUNC_GPUEJ_TDI_XI (MTK_PIN_NO(108) | 5) +#define MT8167_PIN_108_MSDC1_DAT2__FUNC_DBG_MON_B_29 (MTK_PIN_NO(108) | 7) + +#define MT8167_PIN_109_MSDC1_DAT3__FUNC_GPIO109 (MTK_PIN_NO(109) | 0) +#define MT8167_PIN_109_MSDC1_DAT3__FUNC_MSDC1_DAT3 (MTK_PIN_NO(109) | 1) +#define MT8167_PIN_109_MSDC1_DAT3__FUNC_UDI_TDO (MTK_PIN_NO(109) | 2) +#define MT8167_PIN_109_MSDC1_DAT3__FUNC_DFD_TDO (MTK_PIN_NO(109) | 3) +#define MT8167_PIN_109_MSDC1_DAT3__FUNC_SQICK (MTK_PIN_NO(109) | 4) +#define MT8167_PIN_109_MSDC1_DAT3__FUNC_GPUEJ_TDO (MTK_PIN_NO(109) | 5) +#define MT8167_PIN_109_MSDC1_DAT3__FUNC_DBG_MON_B_30 (MTK_PIN_NO(109) | 7) + +#define MT8167_PIN_110_MSDC0_DAT7__FUNC_GPIO110 (MTK_PIN_NO(110) | 0) +#define MT8167_PIN_110_MSDC0_DAT7__FUNC_MSDC0_DAT7 (MTK_PIN_NO(110) | 1) +#define MT8167_PIN_110_MSDC0_DAT7__FUNC_NLD7 (MTK_PIN_NO(110) | 4) + +#define MT8167_PIN_111_MSDC0_DAT6__FUNC_GPIO111 (MTK_PIN_NO(111) | 0) +#define MT8167_PIN_111_MSDC0_DAT6__FUNC_MSDC0_DAT6 (MTK_PIN_NO(111) | 1) +#define MT8167_PIN_111_MSDC0_DAT6__FUNC_NLD6 (MTK_PIN_NO(111) | 4) + +#define MT8167_PIN_112_MSDC0_DAT5__FUNC_GPIO112 (MTK_PIN_NO(112) | 0) +#define MT8167_PIN_112_MSDC0_DAT5__FUNC_MSDC0_DAT5 (MTK_PIN_NO(112) | 1) +#define MT8167_PIN_112_MSDC0_DAT5__FUNC_NLD4 (MTK_PIN_NO(112) | 4) + +#define MT8167_PIN_113_MSDC0_DAT4__FUNC_GPIO113 (MTK_PIN_NO(113) | 0) +#define MT8167_PIN_113_MSDC0_DAT4__FUNC_MSDC0_DAT4 (MTK_PIN_NO(113) | 1) +#define MT8167_PIN_113_MSDC0_DAT4__FUNC_NLD3 (MTK_PIN_NO(113) | 4) + +#define MT8167_PIN_114_MSDC0_RSTB__FUNC_GPIO114 (MTK_PIN_NO(114) | 0) +#define MT8167_PIN_114_MSDC0_RSTB__FUNC_MSDC0_RSTB (MTK_PIN_NO(114) | 1) +#define MT8167_PIN_114_MSDC0_RSTB__FUNC_NLD0 (MTK_PIN_NO(114) | 4) + +#define MT8167_PIN_115_MSDC0_CMD__FUNC_GPIO115 (MTK_PIN_NO(115) | 0) +#define MT8167_PIN_115_MSDC0_CMD__FUNC_MSDC0_CMD (MTK_PIN_NO(115) | 1) +#define MT8167_PIN_115_MSDC0_CMD__FUNC_NALE (MTK_PIN_NO(115) | 4) + +#define MT8167_PIN_116_MSDC0_CLK__FUNC_GPIO116 (MTK_PIN_NO(116) | 0) +#define MT8167_PIN_116_MSDC0_CLK__FUNC_MSDC0_CLK (MTK_PIN_NO(116) | 1) +#define MT8167_PIN_116_MSDC0_CLK__FUNC_NWEB (MTK_PIN_NO(116) | 4) + +#define MT8167_PIN_117_MSDC0_DAT3__FUNC_GPIO117 (MTK_PIN_NO(117) | 0) +#define MT8167_PIN_117_MSDC0_DAT3__FUNC_MSDC0_DAT3 (MTK_PIN_NO(117) | 1) +#define MT8167_PIN_117_MSDC0_DAT3__FUNC_NLD1 (MTK_PIN_NO(117) | 4) + +#define MT8167_PIN_118_MSDC0_DAT2__FUNC_GPIO118 (MTK_PIN_NO(118) | 0) +#define MT8167_PIN_118_MSDC0_DAT2__FUNC_MSDC0_DAT2 (MTK_PIN_NO(118) | 1) +#define MT8167_PIN_118_MSDC0_DAT2__FUNC_NLD5 (MTK_PIN_NO(118) | 4) + +#define MT8167_PIN_119_MSDC0_DAT1__FUNC_GPIO119 (MTK_PIN_NO(119) | 0) +#define MT8167_PIN_119_MSDC0_DAT1__FUNC_MSDC0_DAT1 (MTK_PIN_NO(119) | 1) +#define MT8167_PIN_119_MSDC0_DAT1__FUNC_NLD8 (MTK_PIN_NO(119) | 4) + +#define MT8167_PIN_120_MSDC0_DAT0__FUNC_GPIO120 (MTK_PIN_NO(120) | 0) +#define MT8167_PIN_120_MSDC0_DAT0__FUNC_MSDC0_DAT0 (MTK_PIN_NO(120) | 1) +#define MT8167_PIN_120_MSDC0_DAT0__FUNC_WATCHDOG (MTK_PIN_NO(120) | 4) +#define MT8167_PIN_120_MSDC0_DAT0__FUNC_NLD2 (MTK_PIN_NO(120) | 5) + +#define MT8167_PIN_121_CEC__FUNC_GPIO121 (MTK_PIN_NO(121) | 0) +#define MT8167_PIN_121_CEC__FUNC_CEC (MTK_PIN_NO(121) | 1) + +#define MT8167_PIN_122_HTPLG__FUNC_GPIO122 (MTK_PIN_NO(122) | 0) +#define MT8167_PIN_122_HTPLG__FUNC_HTPLG (MTK_PIN_NO(122) | 1) + +#define MT8167_PIN_123_HDMISCK__FUNC_GPIO123 (MTK_PIN_NO(123) | 0) +#define MT8167_PIN_123_HDMISCK__FUNC_HDMISCK (MTK_PIN_NO(123) | 1) + +#define MT8167_PIN_124_HDMISD__FUNC_GPIO124 (MTK_PIN_NO(124) | 0) +#define MT8167_PIN_124_HDMISD__FUNC_HDMISD (MTK_PIN_NO(124) | 1) + +#endif /* __DTS_MT8167_PINFUNC_H */ diff --git a/arch/arm64/boot/dts/mediatek/mt8167.dtsi b/arch/arm64/boot/dts/mediatek/mt8167.dtsi new file mode 100644 index 000000000000..1c5639ead622 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8167.dtsi @@ -0,0 +1,61 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2020 MediaTek Inc. + * Copyright (c) 2020 BayLibre, SAS. + * Author: Fabien Parent + */ + +#include +#include + +#include "mt8167-pinfunc.h" + +#include "mt8516.dtsi" + +/ { + compatible = "mediatek,mt8167"; + + soc { + topckgen: topckgen@10000000 { + compatible = "mediatek,mt8167-topckgen", "syscon"; + reg = <0 0x10000000 0 0x1000>; + #clock-cells = <1>; + }; + + infracfg: infracfg@10001000 { + compatible = "mediatek,mt8167-infracfg", "syscon"; + reg = <0 0x10001000 0 0x1000>; + #clock-cells = <1>; + }; + + apmixedsys: apmixedsys@10018000 { + compatible = "mediatek,mt8167-apmixedsys", "syscon"; + reg = <0 0x10018000 0 0x710>; + #clock-cells = <1>; + }; + + imgsys: syscon@15000000 { + compatible = "mediatek,mt8167-imgsys", "syscon"; + reg = <0 0x15000000 0 0x1000>; + #clock-cells = <1>; + }; + + vdecsys: syscon@16000000 { + compatible = "mediatek,mt8167-vdecsys", "syscon"; + reg = <0 0x16000000 0 0x1000>; + #clock-cells = <1>; + }; + + pio: pinctrl@1000b000 { + compatible = "mediatek,mt8167-pinctrl"; + reg = <0 0x1000b000 0 0x1000>; + mediatek,pctl-regmap = <&syscfg_pctl>; + pins-are-numbered; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = ; + }; + }; +}; From 7f1e3823ba03a60dd61731ed752f08790806e74d Mon Sep 17 00:00:00 2001 From: Fabien Parent Date: Tue, 27 Oct 2020 20:48:15 +0100 Subject: [PATCH 572/799] arm64: dts: mediatek: add MT8167 pumpkin board dts The pumpkin board is made by Gossamer Engineering and is using a MediaTek SoC. The board currently comes in two available version: MT8516 SoC and MT8167 SoC. The board provides the following IOs: eMMC, NAND, SD card, USB type-A, Ethernet, Wi-Fi, Bluetooth, Audio (jack out, 2 PDM port, 1 analog in), serial over USB, HDMI, DSI, CSI, and an expansion header. The board can be powered by battery and/or via a USB Type-C port and is using a PMIC MT6392. The eMMC and NAND are sharing pins and cannot be used together. This commit is adding the basic boot support for the Pumpkin MT8167 board. Signed-off-by: Fabien Parent Link: https://lore.kernel.org/r/20201027194816.1227654-3-fparent@baylibre.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/Makefile | 1 + .../boot/dts/mediatek/mt8167-pumpkin.dts | 20 +++++++++++++++++++ 2 files changed, 21 insertions(+) create mode 100644 arch/arm64/boot/dts/mediatek/mt8167-pumpkin.dts diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile index 66eeba60acac..db9dcbf5f245 100644 --- a/arch/arm64/boot/dts/mediatek/Makefile +++ b/arch/arm64/boot/dts/mediatek/Makefile @@ -7,6 +7,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-evb.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-x20-dev.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt7622-rfb1.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt7622-bananapi-bpi-r64.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8167-pumpkin.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-elm.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-elm-hana.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-elm-hana-rev7.dtb diff --git a/arch/arm64/boot/dts/mediatek/mt8167-pumpkin.dts b/arch/arm64/boot/dts/mediatek/mt8167-pumpkin.dts new file mode 100644 index 000000000000..774a2f3fb4b2 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8167-pumpkin.dts @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2020 BayLibre, SAS. + * Author: Fabien Parent + */ + +/dts-v1/; + +#include "mt8167.dtsi" +#include "pumpkin-common.dtsi" + +/ { + model = "Pumpkin MT8167"; + compatible = "mediatek,mt8167-pumpkin", "mediatek,mt8167"; + + memory@40000000 { + device_type = "memory"; + reg = <0 0x40000000 0 0x80000000>; + }; +}; From 48489980e27e091c9e871a48157ceda2db855974 Mon Sep 17 00:00:00 2001 From: Seiya Wang Date: Fri, 30 Oct 2020 17:22:07 +0800 Subject: [PATCH 573/799] arm64: dts: Add Mediatek SoC MT8192 and evaluation board dts and Makefile Add basic chip support for Mediatek MT8192 Signed-off-by: Seiya Wang Link: https://lore.kernel.org/r/20201030092207.26488-2-seiya.wang@mediatek.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/Makefile | 1 + arch/arm64/boot/dts/mediatek/mt8192-evb.dts | 29 ++ arch/arm64/boot/dts/mediatek/mt8192.dtsi | 512 ++++++++++++++++++++ 3 files changed, 542 insertions(+) create mode 100644 arch/arm64/boot/dts/mediatek/mt8192-evb.dts create mode 100644 arch/arm64/boot/dts/mediatek/mt8192.dtsi diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile index db9dcbf5f245..18f7b46c4095 100644 --- a/arch/arm64/boot/dts/mediatek/Makefile +++ b/arch/arm64/boot/dts/mediatek/Makefile @@ -14,4 +14,5 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-elm-hana-rev7.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-evb.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-evb.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-krane-sku176.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8192-evb.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8516-pumpkin.dtb diff --git a/arch/arm64/boot/dts/mediatek/mt8192-evb.dts b/arch/arm64/boot/dts/mediatek/mt8192-evb.dts new file mode 100644 index 000000000000..0205837fa698 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8192-evb.dts @@ -0,0 +1,29 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2020 MediaTek Inc. + * Author: Seiya Wang + */ +/dts-v1/; +#include "mt8192.dtsi" + +/ { + model = "MediaTek MT8192 evaluation board"; + compatible = "mediatek,mt8192-evb", "mediatek,mt8192"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:921600n8"; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0 0x40000000 0 0x80000000>; + }; +}; + +&uart0 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi new file mode 100644 index 000000000000..e12e024de122 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -0,0 +1,512 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2020 MediaTek Inc. + * Author: Seiya Wang + */ + +/dts-v1/; +#include +#include +#include + +/ { + compatible = "mediatek,mt8192"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + clk26m: oscillator0 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <26000000>; + clock-output-names = "clk26m"; + }; + + clk32k: oscillator1 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "clk32k"; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x000>; + enable-method = "psci"; + clock-frequency = <1701000000>; + next-level-cache = <&l2_0>; + capacity-dmips-mhz = <530>; + }; + + cpu1: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x100>; + enable-method = "psci"; + clock-frequency = <1701000000>; + next-level-cache = <&l2_0>; + capacity-dmips-mhz = <530>; + }; + + cpu2: cpu@200 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x200>; + enable-method = "psci"; + clock-frequency = <1701000000>; + next-level-cache = <&l2_0>; + capacity-dmips-mhz = <530>; + }; + + cpu3: cpu@300 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x300>; + enable-method = "psci"; + clock-frequency = <1701000000>; + next-level-cache = <&l2_0>; + capacity-dmips-mhz = <530>; + }; + + cpu4: cpu@400 { + device_type = "cpu"; + compatible = "arm,cortex-a76"; + reg = <0x400>; + enable-method = "psci"; + clock-frequency = <2171000000>; + next-level-cache = <&l2_1>; + capacity-dmips-mhz = <1024>; + }; + + cpu5: cpu@500 { + device_type = "cpu"; + compatible = "arm,cortex-a76"; + reg = <0x500>; + enable-method = "psci"; + clock-frequency = <2171000000>; + next-level-cache = <&l2_1>; + capacity-dmips-mhz = <1024>; + }; + + cpu6: cpu@600 { + device_type = "cpu"; + compatible = "arm,cortex-a76"; + reg = <0x600>; + enable-method = "psci"; + clock-frequency = <2171000000>; + next-level-cache = <&l2_1>; + capacity-dmips-mhz = <1024>; + }; + + cpu7: cpu@700 { + device_type = "cpu"; + compatible = "arm,cortex-a76"; + reg = <0x700>; + enable-method = "psci"; + clock-frequency = <2171000000>; + next-level-cache = <&l2_1>; + capacity-dmips-mhz = <1024>; + }; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu0>; + }; + core1 { + cpu = <&cpu1>; + }; + core2 { + cpu = <&cpu2>; + }; + core3 { + cpu = <&cpu3>; + }; + }; + + cluster1 { + core0 { + cpu = <&cpu4>; + }; + core1 { + cpu = <&cpu5>; + }; + core2 { + cpu = <&cpu6>; + }; + core3 { + cpu = <&cpu7>; + }; + }; + }; + + l2_0: l2-cache0 { + compatible = "cache"; + next-level-cache = <&l3_0>; + }; + + l2_1: l2-cache1 { + compatible = "cache"; + next-level-cache = <&l3_0>; + }; + + l3_0: l3-cache { + compatible = "cache"; + }; + }; + + pmu-a55 { + compatible = "arm,cortex-a55-pmu"; + interrupt-parent = <&gic>; + interrupts = ; + }; + + pmu-a76 { + compatible = "arm,cortex-a76-pmu"; + interrupt-parent = <&gic>; + interrupts = ; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + timer: timer { + compatible = "arm,armv8-timer"; + interrupt-parent = <&gic>; + interrupts = , + , + , + ; + clock-frequency = <13000000>; + }; + + soc { + #address-cells = <2>; + #size-cells = <2>; + compatible = "simple-bus"; + ranges; + + gic: interrupt-controller@c000000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <4>; + #redistributor-regions = <1>; + interrupt-parent = <&gic>; + interrupt-controller; + reg = <0 0x0c000000 0 0x40000>, + <0 0x0c040000 0 0x200000>; + interrupts = ; + + ppi-partitions { + ppi_cluster0: interrupt-partition-0 { + affinity = <&cpu0 &cpu1 &cpu2 &cpu3>; + }; + ppi_cluster1: interrupt-partition-1 { + affinity = <&cpu4 &cpu5 &cpu6 &cpu7>; + }; + }; + }; + + pio: pinctrl@10005000 { + compatible = "mediatek,mt8192-pinctrl"; + reg = <0 0x10005000 0 0x1000>, + <0 0x11c20000 0 0x1000>, + <0 0x11d10000 0 0x1000>, + <0 0x11d30000 0 0x1000>, + <0 0x11d40000 0 0x1000>, + <0 0x11e20000 0 0x1000>, + <0 0x11e70000 0 0x1000>, + <0 0x11ea0000 0 0x1000>, + <0 0x11f20000 0 0x1000>, + <0 0x11f30000 0 0x1000>, + <0 0x1000b000 0 0x1000>; + reg-names = "iocfg0", "iocfg_rm", "iocfg_bm", + "iocfg_bl", "iocfg_br", "iocfg_lm", + "iocfg_lb", "iocfg_rt", "iocfg_lt", + "iocfg_tl", "eint"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pio 0 0 220>; + interrupt-controller; + interrupts = ; + #interrupt-cells = <2>; + }; + + systimer: timer@10017000 { + compatible = "mediatek,mt8192-timer", + "mediatek,mt6765-timer"; + reg = <0 0x10017000 0 0x1000>; + interrupts = ; + clocks = <&clk26m>; + clock-names = "clk13m"; + }; + + uart0: serial@11002000 { + compatible = "mediatek,mt8192-uart", + "mediatek,mt6577-uart"; + reg = <0 0x11002000 0 0x1000>; + interrupts = ; + clocks = <&clk26m>, <&clk26m>; + clock-names = "baud", "bus"; + status = "disabled"; + }; + + uart1: serial@11003000 { + compatible = "mediatek,mt8192-uart", + "mediatek,mt6577-uart"; + reg = <0 0x11003000 0 0x1000>; + interrupts = ; + clocks = <&clk26m>, <&clk26m>; + clock-names = "baud", "bus"; + status = "disabled"; + }; + + spi0: spi@1100a000 { + compatible = "mediatek,mt8192-spi", + "mediatek,mt6765-spi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0 0x1100a000 0 0x1000>; + interrupts = ; + clocks = <&clk26m>, + <&clk26m>, + <&clk26m>; + clock-names = "parent-clk", "sel-clk", "spi-clk"; + status = "disabled"; + }; + + spi1: spi@11010000 { + compatible = "mediatek,mt8192-spi", + "mediatek,mt6765-spi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0 0x11010000 0 0x1000>; + interrupts = ; + clocks = <&clk26m>, + <&clk26m>, + <&clk26m>; + clock-names = "parent-clk", "sel-clk", "spi-clk"; + status = "disabled"; + }; + + spi2: spi@11012000 { + compatible = "mediatek,mt8192-spi", + "mediatek,mt6765-spi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0 0x11012000 0 0x1000>; + interrupts = ; + clocks = <&clk26m>, + <&clk26m>, + <&clk26m>; + clock-names = "parent-clk", "sel-clk", "spi-clk"; + status = "disabled"; + }; + + spi3: spi@11013000 { + compatible = "mediatek,mt8192-spi", + "mediatek,mt6765-spi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0 0x11013000 0 0x1000>; + interrupts = ; + clocks = <&clk26m>, + <&clk26m>, + <&clk26m>; + clock-names = "parent-clk", "sel-clk", "spi-clk"; + status = "disabled"; + }; + + spi4: spi@11018000 { + compatible = "mediatek,mt8192-spi", + "mediatek,mt6765-spi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0 0x11018000 0 0x1000>; + interrupts = ; + clocks = <&clk26m>, + <&clk26m>, + <&clk26m>; + clock-names = "parent-clk", "sel-clk", "spi-clk"; + status = "disabled"; + }; + + spi5: spi@11019000 { + compatible = "mediatek,mt8192-spi", + "mediatek,mt6765-spi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0 0x11019000 0 0x1000>; + interrupts = ; + clocks = <&clk26m>, + <&clk26m>, + <&clk26m>; + clock-names = "parent-clk", "sel-clk", "spi-clk"; + status = "disabled"; + }; + + spi6: spi@1101d000 { + compatible = "mediatek,mt8192-spi", + "mediatek,mt6765-spi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0 0x1101d000 0 0x1000>; + interrupts = ; + clocks = <&clk26m>, + <&clk26m>, + <&clk26m>; + clock-names = "parent-clk", "sel-clk", "spi-clk"; + status = "disabled"; + }; + + spi7: spi@1101e000 { + compatible = "mediatek,mt8192-spi", + "mediatek,mt6765-spi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0 0x1101e000 0 0x1000>; + interrupts = ; + clocks = <&clk26m>, + <&clk26m>, + <&clk26m>; + clock-names = "parent-clk", "sel-clk", "spi-clk"; + status = "disabled"; + }; + + i2c3: i2c3@11cb0000 { + compatible = "mediatek,mt8192-i2c"; + reg = <0 0x11cb0000 0 0x1000>, + <0 0x10217300 0 0x80>; + interrupts = ; + clocks = <&clk26m>, <&clk26m>; + clock-names = "main", "dma"; + clock-div = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c7: i2c7@11d00000 { + compatible = "mediatek,mt8192-i2c"; + reg = <0 0x11d00000 0 0x1000>, + <0 0x10217600 0 0x180>; + interrupts = ; + clocks = <&clk26m>, <&clk26m>; + clock-names = "main", "dma"; + clock-div = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c8: i2c8@11d01000 { + compatible = "mediatek,mt8192-i2c"; + reg = <0 0x11d01000 0 0x1000>, + <0 0x10217780 0 0x180>; + interrupts = ; + clocks = <&clk26m>, <&clk26m>; + clock-names = "main", "dma"; + clock-div = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c9: i2c9@11d02000 { + compatible = "mediatek,mt8192-i2c"; + reg = <0 0x11d02000 0 0x1000>, + <0 0x10217900 0 0x180>; + interrupts = ; + clocks = <&clk26m>, <&clk26m>; + clock-names = "main", "dma"; + clock-div = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c1: i2c1@11d20000 { + compatible = "mediatek,mt8192-i2c"; + reg = <0 0x11d20000 0 0x1000>, + <0 0x10217100 0 0x80>; + interrupts = ; + clocks = <&clk26m>, <&clk26m>; + clock-names = "main", "dma"; + clock-div = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c2@11d21000 { + compatible = "mediatek,mt8192-i2c"; + reg = <0 0x11d21000 0 0x1000>, + <0 0x10217180 0 0x180>; + interrupts = ; + clocks = <&clk26m>, <&clk26m>; + clock-names = "main", "dma"; + clock-div = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c4: i2c4@11d22000 { + compatible = "mediatek,mt8192-i2c"; + reg = <0 0x11d22000 0 0x1000>, + <0 0x10217380 0 0x180>; + interrupts = ; + clocks = <&clk26m>, <&clk26m>; + clock-names = "main", "dma"; + clock-div = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c5: i2c5@11e00000 { + compatible = "mediatek,mt8192-i2c"; + reg = <0 0x11e00000 0 0x1000>, + <0 0x10217500 0 0x80>; + interrupts = ; + clocks = <&clk26m>, <&clk26m>; + clock-names = "main", "dma"; + clock-div = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c0: i2c0@11f00000 { + compatible = "mediatek,mt8192-i2c"; + reg = <0 0x11f00000 0 0x1000>, + <0 0x10217080 0 0x80>; + interrupts = ; + clocks = <&clk26m>, <&clk26m>; + clock-names = "main", "dma"; + clock-div = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c6: i2c6@11f01000 { + compatible = "mediatek,mt8192-i2c"; + reg = <0 0x11f01000 0 0x1000>, + <0 0x10217580 0 0x80>; + interrupts = ; + clocks = <&clk26m>, <&clk26m>; + clock-names = "main", "dma"; + clock-div = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; +}; From d392fe78f50bc9e08ac6dfd976ad6e922704b1bf Mon Sep 17 00:00:00 2001 From: Enric Balletbo i Serra Date: Fri, 30 Oct 2020 12:36:07 +0100 Subject: [PATCH 574/799] dt-bindings: power: Add bindings for the Mediatek SCPSYS power domains controller The System Control Processor System (SCPSYS) has several power management related tasks in the system. Add the bindings to define the power domains for the SCPSYS power controller. Co-developed-by: Matthias Brugger Signed-off-by: Matthias Brugger Signed-off-by: Enric Balletbo i Serra Reviewed-by: Rob Herring Link: https://lore.kernel.org/r/20201030113622.201188-2-enric.balletbo@collabora.com Signed-off-by: Matthias Brugger --- .../power/mediatek,power-controller.yaml | 289 ++++++++++++++++++ 1 file changed, 289 insertions(+) create mode 100644 Documentation/devicetree/bindings/power/mediatek,power-controller.yaml diff --git a/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml b/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml new file mode 100644 index 000000000000..73b8988bd063 --- /dev/null +++ b/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml @@ -0,0 +1,289 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/power/mediatek,power-controller.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Mediatek Power Domains Controller + +maintainers: + - Weiyi Lu + - Matthias Brugger + +description: | + Mediatek processors include support for multiple power domains which can be + powered up/down by software based on different application scenes to save power. + + IP cores belonging to a power domain should contain a 'power-domains' + property that is a phandle for SCPSYS node representing the domain. + +properties: + $nodename: + const: power-controller + + compatible: + enum: + - mediatek,mt8173-power-controller + + '#power-domain-cells': + const: 1 + + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + +patternProperties: + "^power-domain@[0-9a-f]+$": + type: object + description: | + Represents the power domains within the power controller node as documented + in Documentation/devicetree/bindings/power/power-domain.yaml. + + properties: + + '#power-domain-cells': + description: + Must be 0 for nodes representing a single PM domain and 1 for nodes + providing multiple PM domains. + + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + + reg: + description: | + Power domain index. Valid values are defined in: + "include/dt-bindings/power/mt8173-power.h" - for MT8173 type power domain. + maxItems: 1 + + clocks: + description: | + A number of phandles to clocks that need to be enabled during domain + power-up sequencing. + + clock-names: + description: | + List of names of clocks, in order to match the power-up sequencing + for each power domain we need to group the clocks by name. BASIC + clocks need to be enabled before enabling the corresponding power + domain, and should not have a '-' in their name (i.e mm, mfg, venc). + SUSBYS clocks need to be enabled before releasing the bus protection, + and should contain a '-' in their name (i.e mm-0, isp-0, cam-0). + + In order to follow properly the power-up sequencing, the clocks must + be specified by order, adding first the BASIC clocks followed by the + SUSBSYS clocks. + + mediatek,infracfg: + $ref: /schemas/types.yaml#definitions/phandle + description: phandle to the device containing the INFRACFG register range. + + mediatek,smi: + $ref: /schemas/types.yaml#definitions/phandle + description: phandle to the device containing the SMI register range. + + patternProperties: + "^power-domain@[0-9a-f]+$": + type: object + description: | + Represents a power domain child within a power domain parent node. + + properties: + + '#power-domain-cells': + description: + Must be 0 for nodes representing a single PM domain and 1 for nodes + providing multiple PM domains. + + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + + reg: + maxItems: 1 + + clocks: + description: | + A number of phandles to clocks that need to be enabled during domain + power-up sequencing. + + clock-names: + description: | + List of names of clocks, in order to match the power-up sequencing + for each power domain we need to group the clocks by name. BASIC + clocks need to be enabled before enabling the corresponding power + domain, and should not have a '-' in their name (i.e mm, mfg, venc). + SUSBYS clocks need to be enabled before releasing the bus protection, + and should contain a '-' in their name (i.e mm-0, isp-0, cam-0). + + In order to follow properly the power-up sequencing, the clocks must + be specified by order, adding first the BASIC clocks followed by the + SUSBSYS clocks. + + mediatek,infracfg: + $ref: /schemas/types.yaml#definitions/phandle + description: phandle to the device containing the INFRACFG register range. + + mediatek,smi: + $ref: /schemas/types.yaml#definitions/phandle + description: phandle to the device containing the SMI register range. + + patternProperties: + "^power-domain@[0-9a-f]+$": + type: object + description: | + Represents a power domain child within a power domain parent node. + + properties: + + '#power-domain-cells': + description: + Must be 0 for nodes representing a single PM domain and 1 for nodes + providing multiple PM domains. + + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + + reg: + maxItems: 1 + + clocks: + description: | + A number of phandles to clocks that need to be enabled during domain + power-up sequencing. + + clock-names: + description: | + List of names of clocks, in order to match the power-up sequencing + for each power domain we need to group the clocks by name. BASIC + clocks need to be enabled before enabling the corresponding power + domain, and should not have a '-' in their name (i.e mm, mfg, venc). + SUSBYS clocks need to be enabled before releasing the bus protection, + and should contain a '-' in their name (i.e mm-0, isp-0, cam-0). + + In order to follow properly the power-up sequencing, the clocks must + be specified by order, adding first the BASIC clocks followed by the + SUSBSYS clocks. + + mediatek,infracfg: + $ref: /schemas/types.yaml#definitions/phandle + description: phandle to the device containing the INFRACFG register range. + + mediatek,smi: + $ref: /schemas/types.yaml#definitions/phandle + description: phandle to the device containing the SMI register range. + + required: + - reg + + additionalProperties: false + + required: + - reg + + additionalProperties: false + + required: + - reg + + additionalProperties: false + +required: + - compatible + +additionalProperties: false + +examples: + - | + #include + #include + + soc { + #address-cells = <2>; + #size-cells = <2>; + + scpsys: syscon@10006000 { + compatible = "syscon", "simple-mfd"; + reg = <0 0x10006000 0 0x1000>; + + spm: power-controller { + compatible = "mediatek,mt8173-power-controller"; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <1>; + + /* power domains of the SoC */ + power-domain@MT8173_POWER_DOMAIN_VDEC { + reg = ; + clocks = <&topckgen CLK_TOP_MM_SEL>; + clock-names = "mm"; + #power-domain-cells = <0>; + }; + power-domain@MT8173_POWER_DOMAIN_VENC { + reg = ; + clocks = <&topckgen CLK_TOP_MM_SEL>, + <&topckgen CLK_TOP_VENC_SEL>; + clock-names = "mm", "venc"; + #power-domain-cells = <0>; + }; + power-domain@MT8173_POWER_DOMAIN_ISP { + reg = ; + clocks = <&topckgen CLK_TOP_MM_SEL>; + clock-names = "mm"; + #power-domain-cells = <0>; + }; + power-domain@MT8173_POWER_DOMAIN_MM { + reg = ; + clocks = <&topckgen CLK_TOP_MM_SEL>; + clock-names = "mm"; + #power-domain-cells = <0>; + mediatek,infracfg = <&infracfg>; + }; + power-domain@MT8173_POWER_DOMAIN_VENC_LT { + reg = ; + clocks = <&topckgen CLK_TOP_MM_SEL>, + <&topckgen CLK_TOP_VENC_LT_SEL>; + clock-names = "mm", "venclt"; + #power-domain-cells = <0>; + }; + power-domain@MT8173_POWER_DOMAIN_AUDIO { + reg = ; + #power-domain-cells = <0>; + }; + power-domain@MT8173_POWER_DOMAIN_USB { + reg = ; + #power-domain-cells = <0>; + }; + power-domain@MT8173_POWER_DOMAIN_MFG_ASYNC { + reg = ; + clocks = <&clk26m>; + clock-names = "mfg"; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <1>; + + power-domain@MT8173_POWER_DOMAIN_MFG_2D { + reg = ; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <1>; + + power-domain@MT8173_POWER_DOMAIN_MFG { + reg = ; + #power-domain-cells = <0>; + mediatek,infracfg = <&infracfg>; + }; + }; + }; + }; + }; + }; From 86a378bb1e98793409e5decfef50edadbca659c5 Mon Sep 17 00:00:00 2001 From: Enric Balletbo i Serra Date: Fri, 30 Oct 2020 12:36:16 +0100 Subject: [PATCH 575/799] dt-bindings: power: Add MT8183 power domains Add power domains dt-bindings for MT8183. Signed-off-by: Matthias Brugger Signed-off-by: Enric Balletbo i Serra Acked-by: Rob Herring Link: https://lore.kernel.org/r/20201030113622.201188-11-enric.balletbo@collabora.com Signed-off-by: Matthias Brugger --- .../power/mediatek,power-controller.yaml | 2 ++ include/dt-bindings/power/mt8183-power.h | 26 +++++++++++++++++++ 2 files changed, 28 insertions(+) create mode 100644 include/dt-bindings/power/mt8183-power.h diff --git a/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml b/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml index 73b8988bd063..8cae43412327 100644 --- a/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml +++ b/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml @@ -24,6 +24,7 @@ properties: compatible: enum: - mediatek,mt8173-power-controller + - mediatek,mt8183-power-controller '#power-domain-cells': const: 1 @@ -58,6 +59,7 @@ patternProperties: description: | Power domain index. Valid values are defined in: "include/dt-bindings/power/mt8173-power.h" - for MT8173 type power domain. + "include/dt-bindings/power/mt8183-power.h" - for MT8183 type power domain. maxItems: 1 clocks: diff --git a/include/dt-bindings/power/mt8183-power.h b/include/dt-bindings/power/mt8183-power.h new file mode 100644 index 000000000000..d1ab387ba8c7 --- /dev/null +++ b/include/dt-bindings/power/mt8183-power.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2020 MediaTek Inc. + * Author: Weiyi Lu + */ + +#ifndef _DT_BINDINGS_POWER_MT8183_POWER_H +#define _DT_BINDINGS_POWER_MT8183_POWER_H + +#define MT8183_POWER_DOMAIN_AUDIO 0 +#define MT8183_POWER_DOMAIN_CONN 1 +#define MT8183_POWER_DOMAIN_MFG_ASYNC 2 +#define MT8183_POWER_DOMAIN_MFG 3 +#define MT8183_POWER_DOMAIN_MFG_CORE0 4 +#define MT8183_POWER_DOMAIN_MFG_CORE1 5 +#define MT8183_POWER_DOMAIN_MFG_2D 6 +#define MT8183_POWER_DOMAIN_DISP 7 +#define MT8183_POWER_DOMAIN_CAM 8 +#define MT8183_POWER_DOMAIN_ISP 9 +#define MT8183_POWER_DOMAIN_VDEC 10 +#define MT8183_POWER_DOMAIN_VENC 11 +#define MT8183_POWER_DOMAIN_VPU_TOP 12 +#define MT8183_POWER_DOMAIN_VPU_CORE0 13 +#define MT8183_POWER_DOMAIN_VPU_CORE1 14 + +#endif /* _DT_BINDINGS_POWER_MT8183_POWER_H */ From 343106d9e61260e4ac569c54dd19201b9e704d46 Mon Sep 17 00:00:00 2001 From: Weiyi Lu Date: Fri, 30 Oct 2020 12:36:20 +0100 Subject: [PATCH 576/799] dt-bindings: power: Add MT8192 power domains Add power domains dt-bindings for MT8192. Signed-off-by: Weiyi Lu Signed-off-by: Enric Balletbo i Serra Acked-by: Rob Herring Link: https://lore.kernel.org/r/20201030113622.201188-15-enric.balletbo@collabora.com Signed-off-by: Matthias Brugger --- .../power/mediatek,power-controller.yaml | 2 ++ include/dt-bindings/power/mt8192-power.h | 32 +++++++++++++++++++ 2 files changed, 34 insertions(+) create mode 100644 include/dt-bindings/power/mt8192-power.h diff --git a/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml b/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml index 8cae43412327..fd12bafe3548 100644 --- a/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml +++ b/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml @@ -25,6 +25,7 @@ properties: enum: - mediatek,mt8173-power-controller - mediatek,mt8183-power-controller + - mediatek,mt8192-power-controller '#power-domain-cells': const: 1 @@ -60,6 +61,7 @@ patternProperties: Power domain index. Valid values are defined in: "include/dt-bindings/power/mt8173-power.h" - for MT8173 type power domain. "include/dt-bindings/power/mt8183-power.h" - for MT8183 type power domain. + "include/dt-bindings/power/mt8192-power.h" - for MT8192 type power domain. maxItems: 1 clocks: diff --git a/include/dt-bindings/power/mt8192-power.h b/include/dt-bindings/power/mt8192-power.h new file mode 100644 index 000000000000..4eaa53d7270a --- /dev/null +++ b/include/dt-bindings/power/mt8192-power.h @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright (c) 2020 MediaTek Inc. + * Author: Weiyi Lu + */ + +#ifndef _DT_BINDINGS_POWER_MT8192_POWER_H +#define _DT_BINDINGS_POWER_MT8192_POWER_H + +#define MT8192_POWER_DOMAIN_AUDIO 0 +#define MT8192_POWER_DOMAIN_CONN 1 +#define MT8192_POWER_DOMAIN_MFG0 2 +#define MT8192_POWER_DOMAIN_MFG1 3 +#define MT8192_POWER_DOMAIN_MFG2 4 +#define MT8192_POWER_DOMAIN_MFG3 5 +#define MT8192_POWER_DOMAIN_MFG4 6 +#define MT8192_POWER_DOMAIN_MFG5 7 +#define MT8192_POWER_DOMAIN_MFG6 8 +#define MT8192_POWER_DOMAIN_DISP 9 +#define MT8192_POWER_DOMAIN_IPE 10 +#define MT8192_POWER_DOMAIN_ISP 11 +#define MT8192_POWER_DOMAIN_ISP2 12 +#define MT8192_POWER_DOMAIN_MDP 13 +#define MT8192_POWER_DOMAIN_VENC 14 +#define MT8192_POWER_DOMAIN_VDEC 15 +#define MT8192_POWER_DOMAIN_VDEC2 16 +#define MT8192_POWER_DOMAIN_CAM 17 +#define MT8192_POWER_DOMAIN_CAM_RAWA 18 +#define MT8192_POWER_DOMAIN_CAM_RAWB 19 +#define MT8192_POWER_DOMAIN_CAM_RAWC 20 + +#endif /* _DT_BINDINGS_POWER_MT8192_POWER_H */ From 8b6562644df9de4e01387635f4d8bf3852d7ad92 Mon Sep 17 00:00:00 2001 From: Enric Balletbo i Serra Date: Fri, 30 Oct 2020 12:36:09 +0100 Subject: [PATCH 577/799] arm64: dts: mediatek: Add mt8173 power domain controller Add power domain controller node for SoC mt8173. Signed-off-by: Enric Balletbo i Serra Link: https://lore.kernel.org/r/20201030113622.201188-4-enric.balletbo@collabora.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8173.dtsi | 164 ++++++++++++++++------- 1 file changed, 115 insertions(+), 49 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi index 5e046f9d48ce..7fa870e4386a 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi @@ -450,16 +450,82 @@ }; }; - scpsys: power-controller@10006000 { - compatible = "mediatek,mt8173-scpsys"; - #power-domain-cells = <1>; + scpsys: syscon@10006000 { + compatible = "syscon", "simple-mfd"; reg = <0 0x10006000 0 0x1000>; - clocks = <&clk26m>, - <&topckgen CLK_TOP_MM_SEL>, - <&topckgen CLK_TOP_VENC_SEL>, - <&topckgen CLK_TOP_VENC_LT_SEL>; - clock-names = "mfg", "mm", "venc", "venc_lt"; - infracfg = <&infracfg>; + #power-domain-cells = <1>; + + /* System Power Manager */ + spm: power-controller { + compatible = "mediatek,mt8173-power-controller"; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <1>; + + /* power domains of the SoC */ + power-domain@MT8173_POWER_DOMAIN_VDEC { + reg = ; + clocks = <&topckgen CLK_TOP_MM_SEL>; + clock-names = "mm"; + #power-domain-cells = <0>; + }; + power-domain@MT8173_POWER_DOMAIN_VENC { + reg = ; + clocks = <&topckgen CLK_TOP_MM_SEL>, + <&topckgen CLK_TOP_VENC_SEL>; + clock-names = "mm", "venc"; + #power-domain-cells = <0>; + }; + power-domain@MT8173_POWER_DOMAIN_ISP { + reg = ; + clocks = <&topckgen CLK_TOP_MM_SEL>; + clock-names = "mm"; + #power-domain-cells = <0>; + }; + power-domain@MT8173_POWER_DOMAIN_MM { + reg = ; + clocks = <&topckgen CLK_TOP_MM_SEL>; + clock-names = "mm"; + #power-domain-cells = <0>; + mediatek,infracfg = <&infracfg>; + }; + power-domain@MT8173_POWER_DOMAIN_VENC_LT { + reg = ; + clocks = <&topckgen CLK_TOP_MM_SEL>, + <&topckgen CLK_TOP_VENC_LT_SEL>; + clock-names = "mm", "venclt"; + #power-domain-cells = <0>; + }; + power-domain@MT8173_POWER_DOMAIN_AUDIO { + reg = ; + #power-domain-cells = <0>; + }; + power-domain@MT8173_POWER_DOMAIN_USB { + reg = ; + #power-domain-cells = <0>; + }; + power-domain@MT8173_POWER_DOMAIN_MFG_ASYNC { + reg = ; + clocks = <&clk26m>; + clock-names = "mfg"; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <1>; + + power-domain@MT8173_POWER_DOMAIN_MFG_2D { + reg = ; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <1>; + + power-domain@MT8173_POWER_DOMAIN_MFG { + reg = ; + #power-domain-cells = <0>; + mediatek,infracfg = <&infracfg>; + }; + }; + }; + }; }; watchdog: watchdog@10007000 { @@ -792,7 +858,7 @@ compatible = "mediatek,mt8173-afe-pcm"; reg = <0 0x11220000 0 0x1000>; interrupts = ; - power-domains = <&scpsys MT8173_POWER_DOMAIN_AUDIO>; + power-domains = <&spm MT8173_POWER_DOMAIN_AUDIO>; clocks = <&infracfg CLK_INFRA_AUDIO>, <&topckgen CLK_TOP_AUDIO_SEL>, <&topckgen CLK_TOP_AUD_INTBUS_SEL>, @@ -868,7 +934,7 @@ phys = <&u2port0 PHY_TYPE_USB2>, <&u3port0 PHY_TYPE_USB3>, <&u2port1 PHY_TYPE_USB2>; - power-domains = <&scpsys MT8173_POWER_DOMAIN_USB>; + power-domains = <&spm MT8173_POWER_DOMAIN_USB>; clocks = <&topckgen CLK_TOP_USB30_SEL>, <&clk26m>; clock-names = "sys_ck", "ref_ck"; mediatek,syscon-wakeup = <&pericfg 0x400 1>; @@ -882,7 +948,7 @@ reg = <0 0x11270000 0 0x1000>; reg-names = "mac"; interrupts = ; - power-domains = <&scpsys MT8173_POWER_DOMAIN_USB>; + power-domains = <&spm MT8173_POWER_DOMAIN_USB>; clocks = <&topckgen CLK_TOP_USB30_SEL>, <&clk26m>; clock-names = "sys_ck", "ref_ck"; status = "disabled"; @@ -925,7 +991,7 @@ mmsys: syscon@14000000 { compatible = "mediatek,mt8173-mmsys", "syscon"; reg = <0 0x14000000 0 0x1000>; - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; + power-domains = <&spm MT8173_POWER_DOMAIN_MM>; assigned-clocks = <&topckgen CLK_TOP_MM_SEL>; assigned-clock-rates = <400000000>; #clock-cells = <1>; @@ -940,7 +1006,7 @@ reg = <0 0x14001000 0 0x1000>; clocks = <&mmsys CLK_MM_MDP_RDMA0>, <&mmsys CLK_MM_MUTEX_32K>; - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; + power-domains = <&spm MT8173_POWER_DOMAIN_MM>; iommus = <&iommu M4U_PORT_MDP_RDMA0>; mediatek,larb = <&larb0>; mediatek,vpu = <&vpu>; @@ -951,7 +1017,7 @@ reg = <0 0x14002000 0 0x1000>; clocks = <&mmsys CLK_MM_MDP_RDMA1>, <&mmsys CLK_MM_MUTEX_32K>; - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; + power-domains = <&spm MT8173_POWER_DOMAIN_MM>; iommus = <&iommu M4U_PORT_MDP_RDMA1>; mediatek,larb = <&larb4>; }; @@ -960,28 +1026,28 @@ compatible = "mediatek,mt8173-mdp-rsz"; reg = <0 0x14003000 0 0x1000>; clocks = <&mmsys CLK_MM_MDP_RSZ0>; - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; + power-domains = <&spm MT8173_POWER_DOMAIN_MM>; }; mdp_rsz1: rsz@14004000 { compatible = "mediatek,mt8173-mdp-rsz"; reg = <0 0x14004000 0 0x1000>; clocks = <&mmsys CLK_MM_MDP_RSZ1>; - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; + power-domains = <&spm MT8173_POWER_DOMAIN_MM>; }; mdp_rsz2: rsz@14005000 { compatible = "mediatek,mt8173-mdp-rsz"; reg = <0 0x14005000 0 0x1000>; clocks = <&mmsys CLK_MM_MDP_RSZ2>; - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; + power-domains = <&spm MT8173_POWER_DOMAIN_MM>; }; mdp_wdma0: wdma@14006000 { compatible = "mediatek,mt8173-mdp-wdma"; reg = <0 0x14006000 0 0x1000>; clocks = <&mmsys CLK_MM_MDP_WDMA>; - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; + power-domains = <&spm MT8173_POWER_DOMAIN_MM>; iommus = <&iommu M4U_PORT_MDP_WDMA>; mediatek,larb = <&larb0>; }; @@ -990,7 +1056,7 @@ compatible = "mediatek,mt8173-mdp-wrot"; reg = <0 0x14007000 0 0x1000>; clocks = <&mmsys CLK_MM_MDP_WROT0>; - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; + power-domains = <&spm MT8173_POWER_DOMAIN_MM>; iommus = <&iommu M4U_PORT_MDP_WROT0>; mediatek,larb = <&larb0>; }; @@ -999,7 +1065,7 @@ compatible = "mediatek,mt8173-mdp-wrot"; reg = <0 0x14008000 0 0x1000>; clocks = <&mmsys CLK_MM_MDP_WROT1>; - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; + power-domains = <&spm MT8173_POWER_DOMAIN_MM>; iommus = <&iommu M4U_PORT_MDP_WROT1>; mediatek,larb = <&larb4>; }; @@ -1008,7 +1074,7 @@ compatible = "mediatek,mt8173-disp-ovl"; reg = <0 0x1400c000 0 0x1000>; interrupts = ; - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; + power-domains = <&spm MT8173_POWER_DOMAIN_MM>; clocks = <&mmsys CLK_MM_DISP_OVL0>; iommus = <&iommu M4U_PORT_DISP_OVL0>; mediatek,larb = <&larb0>; @@ -1019,7 +1085,7 @@ compatible = "mediatek,mt8173-disp-ovl"; reg = <0 0x1400d000 0 0x1000>; interrupts = ; - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; + power-domains = <&spm MT8173_POWER_DOMAIN_MM>; clocks = <&mmsys CLK_MM_DISP_OVL1>; iommus = <&iommu M4U_PORT_DISP_OVL1>; mediatek,larb = <&larb4>; @@ -1030,7 +1096,7 @@ compatible = "mediatek,mt8173-disp-rdma"; reg = <0 0x1400e000 0 0x1000>; interrupts = ; - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; + power-domains = <&spm MT8173_POWER_DOMAIN_MM>; clocks = <&mmsys CLK_MM_DISP_RDMA0>; iommus = <&iommu M4U_PORT_DISP_RDMA0>; mediatek,larb = <&larb0>; @@ -1041,7 +1107,7 @@ compatible = "mediatek,mt8173-disp-rdma"; reg = <0 0x1400f000 0 0x1000>; interrupts = ; - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; + power-domains = <&spm MT8173_POWER_DOMAIN_MM>; clocks = <&mmsys CLK_MM_DISP_RDMA1>; iommus = <&iommu M4U_PORT_DISP_RDMA1>; mediatek,larb = <&larb4>; @@ -1052,7 +1118,7 @@ compatible = "mediatek,mt8173-disp-rdma"; reg = <0 0x14010000 0 0x1000>; interrupts = ; - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; + power-domains = <&spm MT8173_POWER_DOMAIN_MM>; clocks = <&mmsys CLK_MM_DISP_RDMA2>; iommus = <&iommu M4U_PORT_DISP_RDMA2>; mediatek,larb = <&larb4>; @@ -1063,7 +1129,7 @@ compatible = "mediatek,mt8173-disp-wdma"; reg = <0 0x14011000 0 0x1000>; interrupts = ; - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; + power-domains = <&spm MT8173_POWER_DOMAIN_MM>; clocks = <&mmsys CLK_MM_DISP_WDMA0>; iommus = <&iommu M4U_PORT_DISP_WDMA0>; mediatek,larb = <&larb0>; @@ -1074,7 +1140,7 @@ compatible = "mediatek,mt8173-disp-wdma"; reg = <0 0x14012000 0 0x1000>; interrupts = ; - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; + power-domains = <&spm MT8173_POWER_DOMAIN_MM>; clocks = <&mmsys CLK_MM_DISP_WDMA1>; iommus = <&iommu M4U_PORT_DISP_WDMA1>; mediatek,larb = <&larb4>; @@ -1085,7 +1151,7 @@ compatible = "mediatek,mt8173-disp-color"; reg = <0 0x14013000 0 0x1000>; interrupts = ; - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; + power-domains = <&spm MT8173_POWER_DOMAIN_MM>; clocks = <&mmsys CLK_MM_DISP_COLOR0>; mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x3000 0x1000>; }; @@ -1094,7 +1160,7 @@ compatible = "mediatek,mt8173-disp-color"; reg = <0 0x14014000 0 0x1000>; interrupts = ; - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; + power-domains = <&spm MT8173_POWER_DOMAIN_MM>; clocks = <&mmsys CLK_MM_DISP_COLOR1>; mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x4000 0x1000>; }; @@ -1103,7 +1169,7 @@ compatible = "mediatek,mt8173-disp-aal"; reg = <0 0x14015000 0 0x1000>; interrupts = ; - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; + power-domains = <&spm MT8173_POWER_DOMAIN_MM>; clocks = <&mmsys CLK_MM_DISP_AAL>; mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x5000 0x1000>; }; @@ -1112,7 +1178,7 @@ compatible = "mediatek,mt8173-disp-gamma"; reg = <0 0x14016000 0 0x1000>; interrupts = ; - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; + power-domains = <&spm MT8173_POWER_DOMAIN_MM>; clocks = <&mmsys CLK_MM_DISP_GAMMA>; mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x6000 0x1000>; }; @@ -1120,21 +1186,21 @@ merge@14017000 { compatible = "mediatek,mt8173-disp-merge"; reg = <0 0x14017000 0 0x1000>; - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; + power-domains = <&spm MT8173_POWER_DOMAIN_MM>; clocks = <&mmsys CLK_MM_DISP_MERGE>; }; split0: split@14018000 { compatible = "mediatek,mt8173-disp-split"; reg = <0 0x14018000 0 0x1000>; - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; + power-domains = <&spm MT8173_POWER_DOMAIN_MM>; clocks = <&mmsys CLK_MM_DISP_SPLIT0>; }; split1: split@14019000 { compatible = "mediatek,mt8173-disp-split"; reg = <0 0x14019000 0 0x1000>; - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; + power-domains = <&spm MT8173_POWER_DOMAIN_MM>; clocks = <&mmsys CLK_MM_DISP_SPLIT1>; }; @@ -1142,7 +1208,7 @@ compatible = "mediatek,mt8173-disp-ufoe"; reg = <0 0x1401a000 0 0x1000>; interrupts = ; - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; + power-domains = <&spm MT8173_POWER_DOMAIN_MM>; clocks = <&mmsys CLK_MM_DISP_UFOE>; }; @@ -1150,7 +1216,7 @@ compatible = "mediatek,mt8173-dsi"; reg = <0 0x1401b000 0 0x1000>; interrupts = ; - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; + power-domains = <&spm MT8173_POWER_DOMAIN_MM>; clocks = <&mmsys CLK_MM_DSI0_ENGINE>, <&mmsys CLK_MM_DSI0_DIGITAL>, <&mipi_tx0>; @@ -1164,7 +1230,7 @@ compatible = "mediatek,mt8173-dsi"; reg = <0 0x1401c000 0 0x1000>; interrupts = ; - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; + power-domains = <&spm MT8173_POWER_DOMAIN_MM>; clocks = <&mmsys CLK_MM_DSI1_ENGINE>, <&mmsys CLK_MM_DSI1_DIGITAL>, <&mipi_tx1>; @@ -1178,7 +1244,7 @@ compatible = "mediatek,mt8173-dpi"; reg = <0 0x1401d000 0 0x1000>; interrupts = ; - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; + power-domains = <&spm MT8173_POWER_DOMAIN_MM>; clocks = <&mmsys CLK_MM_DPI_PIXEL>, <&mmsys CLK_MM_DPI_ENGINE>, <&apmixedsys CLK_APMIXED_TVDPLL>; @@ -1218,7 +1284,7 @@ compatible = "mediatek,mt8173-disp-mutex"; reg = <0 0x14020000 0 0x1000>; interrupts = ; - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; + power-domains = <&spm MT8173_POWER_DOMAIN_MM>; clocks = <&mmsys CLK_MM_MUTEX_32K>; mediatek,gce-events = , ; @@ -1228,7 +1294,7 @@ compatible = "mediatek,mt8173-smi-larb"; reg = <0 0x14021000 0 0x1000>; mediatek,smi = <&smi_common>; - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; + power-domains = <&spm MT8173_POWER_DOMAIN_MM>; clocks = <&mmsys CLK_MM_SMI_LARB0>, <&mmsys CLK_MM_SMI_LARB0>; clock-names = "apb", "smi"; @@ -1237,7 +1303,7 @@ smi_common: smi@14022000 { compatible = "mediatek,mt8173-smi-common"; reg = <0 0x14022000 0 0x1000>; - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; + power-domains = <&spm MT8173_POWER_DOMAIN_MM>; clocks = <&mmsys CLK_MM_SMI_COMMON>, <&mmsys CLK_MM_SMI_COMMON>; clock-names = "apb", "smi"; @@ -1285,7 +1351,7 @@ compatible = "mediatek,mt8173-smi-larb"; reg = <0 0x14027000 0 0x1000>; mediatek,smi = <&smi_common>; - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; + power-domains = <&spm MT8173_POWER_DOMAIN_MM>; clocks = <&mmsys CLK_MM_SMI_LARB4>, <&mmsys CLK_MM_SMI_LARB4>; clock-names = "apb", "smi"; @@ -1301,7 +1367,7 @@ compatible = "mediatek,mt8173-smi-larb"; reg = <0 0x15001000 0 0x1000>; mediatek,smi = <&smi_common>; - power-domains = <&scpsys MT8173_POWER_DOMAIN_ISP>; + power-domains = <&spm MT8173_POWER_DOMAIN_ISP>; clocks = <&imgsys CLK_IMG_LARB2_SMI>, <&imgsys CLK_IMG_LARB2_SMI>; clock-names = "apb", "smi"; @@ -1338,7 +1404,7 @@ <&iommu M4U_PORT_HW_VDEC_VLD_EXT>, <&iommu M4U_PORT_HW_VDEC_VLD2_EXT>; mediatek,vpu = <&vpu>; - power-domains = <&scpsys MT8173_POWER_DOMAIN_VDEC>; + power-domains = <&spm MT8173_POWER_DOMAIN_VDEC>; clocks = <&apmixedsys CLK_APMIXED_VCODECPLL>, <&topckgen CLK_TOP_UNIVPLL_D2>, <&topckgen CLK_TOP_CCI400_SEL>, @@ -1370,7 +1436,7 @@ compatible = "mediatek,mt8173-smi-larb"; reg = <0 0x16010000 0 0x1000>; mediatek,smi = <&smi_common>; - power-domains = <&scpsys MT8173_POWER_DOMAIN_VDEC>; + power-domains = <&spm MT8173_POWER_DOMAIN_VDEC>; clocks = <&vdecsys CLK_VDEC_CKEN>, <&vdecsys CLK_VDEC_LARB_CKEN>; clock-names = "apb", "smi"; @@ -1386,7 +1452,7 @@ compatible = "mediatek,mt8173-smi-larb"; reg = <0 0x18001000 0 0x1000>; mediatek,smi = <&smi_common>; - power-domains = <&scpsys MT8173_POWER_DOMAIN_VENC>; + power-domains = <&spm MT8173_POWER_DOMAIN_VENC>; clocks = <&vencsys CLK_VENC_CKE1>, <&vencsys CLK_VENC_CKE0>; clock-names = "apb", "smi"; @@ -1443,7 +1509,7 @@ <&vencsys CLK_VENC_CKE3>; clock-names = "jpgdec-smi", "jpgdec"; - power-domains = <&scpsys MT8173_POWER_DOMAIN_VENC>; + power-domains = <&spm MT8173_POWER_DOMAIN_VENC>; mediatek,larb = <&larb3>; iommus = <&iommu M4U_PORT_JPGDEC_WDMA>, <&iommu M4U_PORT_JPGDEC_BSDMA>; @@ -1459,7 +1525,7 @@ compatible = "mediatek,mt8173-smi-larb"; reg = <0 0x19001000 0 0x1000>; mediatek,smi = <&smi_common>; - power-domains = <&scpsys MT8173_POWER_DOMAIN_VENC_LT>; + power-domains = <&spm MT8173_POWER_DOMAIN_VENC_LT>; clocks = <&vencltsys CLK_VENCLT_CKE1>, <&vencltsys CLK_VENCLT_CKE0>; clock-names = "apb", "smi"; From ddebdbad8149af123574b87596927437339318f7 Mon Sep 17 00:00:00 2001 From: Enric Balletbo i Serra Date: Fri, 30 Oct 2020 12:36:18 +0100 Subject: [PATCH 578/799] arm64: dts: mediatek: Add smi_common node for MT8183 The SMI (Smart Multimedia Interface) Common is a bridge between the m4u (Multimedia Memory Management Unit) and the Multimedia HW. This block is needed to support different multimedia features, like display, video decode, and camera. Also is needed to control the power domains of such HW blocks. Signed-off-by: Enric Balletbo i Serra Link: https://lore.kernel.org/r/20201030113622.201188-13-enric.balletbo@collabora.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8183.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi index 08a914d3a643..360a638d6b87 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi @@ -765,6 +765,16 @@ #clock-cells = <1>; }; + smi_common: smi@14019000 { + compatible = "mediatek,mt8183-smi-common", "syscon"; + reg = <0 0x14019000 0 0x1000>; + clocks = <&mmsys CLK_MM_SMI_COMMON>, + <&mmsys CLK_MM_SMI_COMMON>, + <&mmsys CLK_MM_GALS_COMM0>, + <&mmsys CLK_MM_GALS_COMM1>; + clock-names = "apb", "smi", "gals0", "gals1"; + }; + imgsys: syscon@15020000 { compatible = "mediatek,mt8183-imgsys", "syscon"; reg = <0 0x15020000 0 0x1000>; From 37fb78b9aeb75d79f0bdfbbbdcb85ebb68ae1476 Mon Sep 17 00:00:00 2001 From: Matthias Brugger Date: Fri, 30 Oct 2020 12:36:19 +0100 Subject: [PATCH 579/799] arm64: dts: mediatek: Add mt8183 power domains controller Add power domains controller node for SoC mt8183 Signed-off-by: Matthias Brugger Signed-off-by: Enric Balletbo i Serra Link: https://lore.kernel.org/r/20201030113622.201188-14-enric.balletbo@collabora.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8183.dtsi | 162 +++++++++++++++++++++++ 1 file changed, 162 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi index 360a638d6b87..1ef39c5cc9fa 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi @@ -8,6 +8,7 @@ #include #include #include +#include #include #include #include "mt8183-pinfunc.h" @@ -316,6 +317,167 @@ #interrupt-cells = <2>; }; + scpsys: syscon@10006000 { + compatible = "syscon", "simple-mfd"; + reg = <0 0x10006000 0 0x1000>; + #power-domain-cells = <1>; + + /* System Power Manager */ + spm: power-controller { + compatible = "mediatek,mt8183-power-controller"; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <1>; + + /* power domain of the SoC */ + power-domain@MT8183_POWER_DOMAIN_AUDIO { + reg = ; + clocks = <&topckgen CLK_TOP_MUX_AUD_INTBUS>, + <&infracfg CLK_INFRA_AUDIO>, + <&infracfg CLK_INFRA_AUDIO_26M_BCLK>; + clock-names = "audio", "audio1", "audio2"; + #power-domain-cells = <0>; + }; + + power-domain@MT8183_POWER_DOMAIN_CONN { + reg = ; + mediatek,infracfg = <&infracfg>; + #power-domain-cells = <0>; + }; + + power-domain@MT8183_POWER_DOMAIN_MFG_ASYNC { + reg = ; + clocks = <&topckgen CLK_TOP_MUX_MFG>; + clock-names = "mfg"; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <1>; + + power-domain@MT8183_POWER_DOMAIN_MFG { + reg = ; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <1>; + + power-domain@MT8183_POWER_DOMAIN_MFG_CORE0 { + reg = ; + #power-domain-cells = <0>; + }; + + power-domain@MT8183_POWER_DOMAIN_MFG_CORE1 { + reg = ; + #power-domain-cells = <0>; + }; + + power-domain@MT8183_POWER_DOMAIN_MFG_2D { + reg = ; + mediatek,infracfg = <&infracfg>; + #power-domain-cells = <0>; + }; + }; + }; + + power-domain@MT8183_POWER_DOMAIN_DISP { + reg = ; + clocks = <&topckgen CLK_TOP_MUX_MM>, + <&mmsys CLK_MM_SMI_COMMON>, + <&mmsys CLK_MM_SMI_LARB0>, + <&mmsys CLK_MM_SMI_LARB1>, + <&mmsys CLK_MM_GALS_COMM0>, + <&mmsys CLK_MM_GALS_COMM1>, + <&mmsys CLK_MM_GALS_CCU2MM>, + <&mmsys CLK_MM_GALS_IPU12MM>, + <&mmsys CLK_MM_GALS_IMG2MM>, + <&mmsys CLK_MM_GALS_CAM2MM>, + <&mmsys CLK_MM_GALS_IPU2MM>; + clock-names = "mm", "mm-0", "mm-1", "mm-2", "mm-3", + "mm-4", "mm-5", "mm-6", "mm-7", + "mm-8", "mm-9"; + mediatek,infracfg = <&infracfg>; + mediatek,smi = <&smi_common>; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <1>; + + power-domain@MT8183_POWER_DOMAIN_CAM { + reg = ; + clocks = <&topckgen CLK_TOP_MUX_CAM>, + <&camsys CLK_CAM_LARB6>, + <&camsys CLK_CAM_LARB3>, + <&camsys CLK_CAM_SENINF>, + <&camsys CLK_CAM_CAMSV0>, + <&camsys CLK_CAM_CAMSV1>, + <&camsys CLK_CAM_CAMSV2>, + <&camsys CLK_CAM_CCU>; + clock-names = "cam", "cam-0", "cam-1", + "cam-2", "cam-3", "cam-4", + "cam-5", "cam-6"; + mediatek,infracfg = <&infracfg>; + mediatek,smi = <&smi_common>; + #power-domain-cells = <0>; + }; + + power-domain@MT8183_POWER_DOMAIN_ISP { + reg = ; + clocks = <&topckgen CLK_TOP_MUX_IMG>, + <&imgsys CLK_IMG_LARB5>, + <&imgsys CLK_IMG_LARB2>; + clock-names = "isp", "isp-0", "isp-1"; + mediatek,infracfg = <&infracfg>; + mediatek,smi = <&smi_common>; + #power-domain-cells = <0>; + }; + + power-domain@MT8183_POWER_DOMAIN_VDEC { + reg = ; + mediatek,smi = <&smi_common>; + #power-domain-cells = <0>; + }; + + power-domain@MT8183_POWER_DOMAIN_VENC { + reg = ; + mediatek,smi = <&smi_common>; + #power-domain-cells = <0>; + }; + + power-domain@MT8183_POWER_DOMAIN_VPU_TOP { + reg = ; + clocks = <&topckgen CLK_TOP_MUX_IPU_IF>, + <&topckgen CLK_TOP_MUX_DSP>, + <&ipu_conn CLK_IPU_CONN_IPU>, + <&ipu_conn CLK_IPU_CONN_AHB>, + <&ipu_conn CLK_IPU_CONN_AXI>, + <&ipu_conn CLK_IPU_CONN_ISP>, + <&ipu_conn CLK_IPU_CONN_CAM_ADL>, + <&ipu_conn CLK_IPU_CONN_IMG_ADL>; + clock-names = "vpu", "vpu1", "vpu-0", "vpu-1", + "vpu-2", "vpu-3", "vpu-4", "vpu-5"; + mediatek,infracfg = <&infracfg>; + mediatek,smi = <&smi_common>; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <1>; + + power-domain@MT8183_POWER_DOMAIN_VPU_CORE0 { + reg = ; + clocks = <&topckgen CLK_TOP_MUX_DSP1>; + clock-names = "vpu2"; + mediatek,infracfg = <&infracfg>; + #power-domain-cells = <0>; + }; + + power-domain@MT8183_POWER_DOMAIN_VPU_CORE1 { + reg = ; + clocks = <&topckgen CLK_TOP_MUX_DSP2>; + clock-names = "vpu3"; + mediatek,infracfg = <&infracfg>; + #power-domain-cells = <0>; + }; + }; + }; + }; + }; + watchdog: watchdog@10007000 { compatible = "mediatek,mt8183-wdt"; reg = <0 0x10007000 0 0x100>; From f15722c0fef05a62d64ca1b1fc682f6f7396c108 Mon Sep 17 00:00:00 2001 From: Hsin-Yi Wang Date: Tue, 24 Nov 2020 12:12:54 +0800 Subject: [PATCH 580/799] arm64: dts: mt8183: Add pwm and backlight node Add pwm to mt8183 and backlight to mt8183-kukui. Signed-off-by: Hsin-Yi Wang Tested-by: Enric Balletbo i Serra Link: https://lore.kernel.org/r/20201124041253.4181273-1-hsinyi@chromium.org Signed-off-by: Matthias Brugger --- .../arm64/boot/dts/mediatek/mt8183-kukui.dtsi | 28 +++++++++++++++++++ arch/arm64/boot/dts/mediatek/mt8183.dtsi | 10 +++++++ 2 files changed, 38 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi index 85f7c33ba446..bf2ad1294dd3 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi @@ -19,6 +19,17 @@ stdout-path = "serial0:115200n8"; }; + backlight_lcd0: backlight_lcd0 { + compatible = "pwm-backlight"; + pwms = <&pwm0 0 500000>; + power-supply = <&bl_pp5000>; + enable-gpios = <&pio 176 0>; + brightness-levels = <0 1023>; + num-interpolated-steps = <1023>; + default-brightness-level = <576>; + status = "okay"; + }; + memory@40000000 { device_type = "memory"; reg = <0 0x40000000 0 0x80000000>; @@ -536,6 +547,17 @@ }; }; + pwm0_pin_default: pwm0_pin_default { + pins1 { + pinmux = ; + output-high; + bias-pull-up; + }; + pins2 { + pinmux = ; + }; + }; + scp_pins: scp { pins_scp_uart { pinmux = , @@ -670,6 +692,12 @@ }; }; +&pwm0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pwm0_pin_default>; +}; + &scp { status = "okay"; pinctrl-names = "default"; diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi index 1ef39c5cc9fa..2a8832537027 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi @@ -641,6 +641,16 @@ status = "disabled"; }; + pwm0: pwm@1100e000 { + compatible = "mediatek,mt8183-disp-pwm"; + reg = <0 0x1100e000 0 0x1000>; + interrupts = ; + #pwm-cells = <2>; + clocks = <&topckgen CLK_TOP_MUX_DISP_PWM>, + <&infracfg CLK_INFRA_DISP_PWM>; + clock-names = "main", "mm"; + }; + i2c3: i2c@1100f000 { compatible = "mediatek,mt8183-i2c"; reg = <0 0x1100f000 0 0x1000>, From 88ec840270e62e18dac4bb678fb0823077378b8d Mon Sep 17 00:00:00 2001 From: Jitao Shi Date: Fri, 27 Nov 2020 11:49:28 +0100 Subject: [PATCH 581/799] arm64: dts: mt8183: Add dsi node Add dsi and mipitx nodes to the MT8183. Signed-off-by: Jitao Shi Signed-off-by: Enric Balletbo i Serra Link: https://lore.kernel.org/r/20201127104930.1981497-2-enric.balletbo@collabora.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8183.dtsi | 31 ++++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi index 2a8832537027..548026d0e977 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi @@ -892,10 +892,27 @@ status = "disabled"; }; + mipi_tx0: mipi-dphy@11e50000 { + compatible = "mediatek,mt8183-mipi-tx"; + reg = <0 0x11e50000 0 0x1000>; + clocks = <&apmixedsys CLK_APMIXED_MIPID0_26M>; + clock-names = "ref_clk"; + #clock-cells = <0>; + #phy-cells = <0>; + clock-output-names = "mipi_tx0_pll"; + nvmem-cells = <&mipi_tx_calibration>; + nvmem-cell-names = "calibration-data"; + }; + efuse: efuse@11f10000 { compatible = "mediatek,mt8183-efuse", "mediatek,efuse"; reg = <0 0x11f10000 0 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + mipi_tx_calibration: calib@190 { + reg = <0x190 0xc>; + }; }; u3phy: usb-phy@11f40000 { @@ -937,6 +954,20 @@ #clock-cells = <1>; }; + dsi0: dsi@14014000 { + compatible = "mediatek,mt8183-dsi"; + reg = <0 0x14014000 0 0x1000>; + interrupts = ; + power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; + mediatek,syscon-dsi = <&mmsys 0x140>; + clocks = <&mmsys CLK_MM_DSI0_MM>, + <&mmsys CLK_MM_DSI0_IF>, + <&mipi_tx0>; + clock-names = "engine", "digital", "hs"; + phys = <&mipi_tx0>; + phy-names = "dphy"; + }; + smi_common: smi@14019000 { compatible = "mediatek,mt8183-smi-common", "syscon"; reg = <0 0x14019000 0 0x1000>; From c6080916310b6d47bb7d75a5647a346ae7c4b56f Mon Sep 17 00:00:00 2001 From: Enric Balletbo i Serra Date: Fri, 27 Nov 2020 11:49:29 +0100 Subject: [PATCH 582/799] arm64: dts: mt8183: Add iommu and larb nodes Add iommu and larb nodes to the MT8183. Signed-off-by: Enric Balletbo i Serra Link: https://lore.kernel.org/r/20201127104930.1981497-3-enric.balletbo@collabora.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8183.dtsi | 79 ++++++++++++++++++++++++ 1 file changed, 79 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi index 548026d0e977..dfe80cb15c46 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi @@ -8,6 +8,7 @@ #include #include #include +#include #include #include #include @@ -521,6 +522,15 @@ clock-names = "clk13m"; }; + iommu: iommu@10205000 { + compatible = "mediatek,mt8183-m4u"; + reg = <0 0x10205000 0 0x1000>; + interrupts = ; + mediatek,larbs = <&larb0 &larb1 &larb2 &larb3 + &larb4 &larb5 &larb6>; + #iommu-cells = <1>; + }; + gce: mailbox@10238000 { compatible = "mediatek,mt8183-gce"; reg = <0 0x10238000 0 0x4000>; @@ -968,6 +978,16 @@ phy-names = "dphy"; }; + larb0: larb@14017000 { + compatible = "mediatek,mt8183-smi-larb"; + reg = <0 0x14017000 0 0x1000>; + mediatek,smi = <&smi_common>; + clocks = <&mmsys CLK_MM_SMI_LARB0>, + <&mmsys CLK_MM_SMI_LARB0>; + power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; + clock-names = "apb", "smi"; + }; + smi_common: smi@14019000 { compatible = "mediatek,mt8183-smi-common", "syscon"; reg = <0 0x14019000 0 0x1000>; @@ -984,18 +1004,57 @@ #clock-cells = <1>; }; + larb5: larb@15021000 { + compatible = "mediatek,mt8183-smi-larb"; + reg = <0 0x15021000 0 0x1000>; + mediatek,smi = <&smi_common>; + clocks = <&imgsys CLK_IMG_LARB5>, <&imgsys CLK_IMG_LARB5>, + <&mmsys CLK_MM_GALS_IMG2MM>; + clock-names = "apb", "smi", "gals"; + power-domains = <&spm MT8183_POWER_DOMAIN_ISP>; + }; + + larb2: larb@1502f000 { + compatible = "mediatek,mt8183-smi-larb"; + reg = <0 0x1502f000 0 0x1000>; + mediatek,smi = <&smi_common>; + clocks = <&imgsys CLK_IMG_LARB2>, <&imgsys CLK_IMG_LARB2>, + <&mmsys CLK_MM_GALS_IPU2MM>; + clock-names = "apb", "smi", "gals"; + power-domains = <&spm MT8183_POWER_DOMAIN_ISP>; + }; + vdecsys: syscon@16000000 { compatible = "mediatek,mt8183-vdecsys", "syscon"; reg = <0 0x16000000 0 0x1000>; #clock-cells = <1>; }; + larb1: larb@16010000 { + compatible = "mediatek,mt8183-smi-larb"; + reg = <0 0x16010000 0 0x1000>; + mediatek,smi = <&smi_common>; + clocks = <&vdecsys CLK_VDEC_VDEC>, <&vdecsys CLK_VDEC_LARB1>; + clock-names = "apb", "smi"; + power-domains = <&spm MT8183_POWER_DOMAIN_VDEC>; + }; + vencsys: syscon@17000000 { compatible = "mediatek,mt8183-vencsys", "syscon"; reg = <0 0x17000000 0 0x1000>; #clock-cells = <1>; }; + larb4: larb@17010000 { + compatible = "mediatek,mt8183-smi-larb"; + reg = <0 0x17010000 0 0x1000>; + mediatek,smi = <&smi_common>; + clocks = <&vencsys CLK_VENC_LARB>, + <&vencsys CLK_VENC_LARB>; + clock-names = "apb", "smi"; + power-domains = <&spm MT8183_POWER_DOMAIN_VENC>; + }; + ipu_conn: syscon@19000000 { compatible = "mediatek,mt8183-ipu_conn", "syscon"; reg = <0 0x19000000 0 0x1000>; @@ -1025,5 +1084,25 @@ reg = <0 0x1a000000 0 0x1000>; #clock-cells = <1>; }; + + larb6: larb@1a001000 { + compatible = "mediatek,mt8183-smi-larb"; + reg = <0 0x1a001000 0 0x1000>; + mediatek,smi = <&smi_common>; + clocks = <&camsys CLK_CAM_LARB6>, <&camsys CLK_CAM_LARB6>, + <&mmsys CLK_MM_GALS_CAM2MM>; + clock-names = "apb", "smi", "gals"; + power-domains = <&spm MT8183_POWER_DOMAIN_CAM>; + }; + + larb3: larb@1a002000 { + compatible = "mediatek,mt8183-smi-larb"; + reg = <0 0x1a002000 0 0x1000>; + mediatek,smi = <&smi_common>; + clocks = <&camsys CLK_CAM_LARB3>, <&camsys CLK_CAM_LARB3>, + <&mmsys CLK_MM_GALS_IPU12MM>; + clock-names = "apb", "smi", "gals"; + power-domains = <&spm MT8183_POWER_DOMAIN_CAM>; + }; }; }; From 91f9c963ce79fcc34577fc008d54f633c3e11d42 Mon Sep 17 00:00:00 2001 From: Enric Balletbo i Serra Date: Fri, 27 Nov 2020 11:49:30 +0100 Subject: [PATCH 583/799] arm64: dts: mt8183: Add display nodes for MT8183 Add display subsystem device nodes to allow video output. Signed-off-by: Enric Balletbo i Serra Link: https://lore.kernel.org/r/20201127104930.1981497-4-enric.balletbo@collabora.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8183.dtsi | 114 +++++++++++++++++++++++ 1 file changed, 114 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi index dfe80cb15c46..5b782a4769e7 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi @@ -6,6 +6,7 @@ */ #include +#include #include #include #include @@ -33,6 +34,11 @@ i2c9 = &i2c9; i2c10 = &i2c10; i2c11 = &i2c11; + ovl0 = &ovl0; + ovl-2l0 = &ovl_2l0; + ovl-2l1 = &ovl_2l1; + rdma0 = &rdma0; + rdma1 = &rdma1; }; cpus { @@ -964,6 +970,107 @@ #clock-cells = <1>; }; + ovl0: ovl@14008000 { + compatible = "mediatek,mt8183-disp-ovl"; + reg = <0 0x14008000 0 0x1000>; + interrupts = ; + power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; + clocks = <&mmsys CLK_MM_DISP_OVL0>; + iommus = <&iommu M4U_PORT_DISP_OVL0>; + mediatek,larb = <&larb0>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x8000 0x1000>; + }; + + ovl_2l0: ovl@14009000 { + compatible = "mediatek,mt8183-disp-ovl-2l"; + reg = <0 0x14009000 0 0x1000>; + interrupts = ; + power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; + clocks = <&mmsys CLK_MM_DISP_OVL0_2L>; + iommus = <&iommu M4U_PORT_DISP_2L_OVL0_LARB0>; + mediatek,larb = <&larb0>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x9000 0x1000>; + }; + + ovl_2l1: ovl@1400a000 { + compatible = "mediatek,mt8183-disp-ovl-2l"; + reg = <0 0x1400a000 0 0x1000>; + interrupts = ; + power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; + clocks = <&mmsys CLK_MM_DISP_OVL1_2L>; + iommus = <&iommu M4U_PORT_DISP_2L_OVL1_LARB0>; + mediatek,larb = <&larb0>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xa000 0x1000>; + }; + + rdma0: rdma@1400b000 { + compatible = "mediatek,mt8183-disp-rdma"; + reg = <0 0x1400b000 0 0x1000>; + interrupts = ; + power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; + clocks = <&mmsys CLK_MM_DISP_RDMA0>; + iommus = <&iommu M4U_PORT_DISP_RDMA0>; + mediatek,larb = <&larb0>; + mediatek,rdma_fifo_size = <5120>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xb000 0x1000>; + }; + + rdma1: rdma@1400c000 { + compatible = "mediatek,mt8183-disp-rdma"; + reg = <0 0x1400c000 0 0x1000>; + interrupts = ; + power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; + clocks = <&mmsys CLK_MM_DISP_RDMA1>; + iommus = <&iommu M4U_PORT_DISP_RDMA1>; + mediatek,larb = <&larb0>; + mediatek,rdma_fifo_size = <2048>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>; + }; + + color0: color@1400e000 { + compatible = "mediatek,mt8183-disp-color", + "mediatek,mt8173-disp-color"; + reg = <0 0x1400e000 0 0x1000>; + interrupts = ; + power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; + clocks = <&mmsys CLK_MM_DISP_COLOR0>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>; + }; + + ccorr0: ccorr@1400f000 { + compatible = "mediatek,mt8183-disp-ccorr"; + reg = <0 0x1400f000 0 0x1000>; + interrupts = ; + power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; + clocks = <&mmsys CLK_MM_DISP_CCORR0>; + }; + + aal0: aal@14010000 { + compatible = "mediatek,mt8183-disp-aal", + "mediatek,mt8173-disp-aal"; + reg = <0 0x14010000 0 0x1000>; + interrupts = ; + power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; + clocks = <&mmsys CLK_MM_DISP_AAL0>; + }; + + gamma0: gamma@14011000 { + compatible = "mediatek,mt8183-disp-gamma", + "mediatek,mt8173-disp-gamma"; + reg = <0 0x14011000 0 0x1000>; + interrupts = ; + power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; + clocks = <&mmsys CLK_MM_DISP_GAMMA0>; + }; + + dither0: dither@14012000 { + compatible = "mediatek,mt8183-disp-dither"; + reg = <0 0x14012000 0 0x1000>; + interrupts = ; + power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; + clocks = <&mmsys CLK_MM_DISP_DITHER0>; + }; + dsi0: dsi@14014000 { compatible = "mediatek,mt8183-dsi"; reg = <0 0x14014000 0 0x1000>; @@ -978,6 +1085,13 @@ phy-names = "dphy"; }; + mutex: mutex@14016000 { + compatible = "mediatek,mt8183-disp-mutex"; + reg = <0 0x14016000 0 0x1000>; + interrupts = ; + power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; + }; + larb0: larb@14017000 { compatible = "mediatek,mt8183-smi-larb"; reg = <0 0x14017000 0 0x1000>; From b6633d778675a58fba1d7f795169da212a76231d Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Fri, 20 Nov 2020 09:35:32 +0200 Subject: [PATCH 584/799] arm64: dts: ti: k3-j7200-som-p0: main_i2c0 have an ioexpander on the SOM The J7200 SOM have additional io expander which is used to control several SOM level muxes to make sure that the correct signals are routed to the correct pin on the SOM <-> CPB connectors. Signed-off-by: Peter Ujfalusi Signed-off-by: Nishanth Menon Reviewed-by: Vignesh Raghavendra Reviewed-by: Grygorii Strashko Link: https://lore.kernel.org/r/20201120073533.24486-2-peter.ujfalusi@ti.com --- .../dts/ti/k3-j7200-common-proc-board.dts | 11 -------- arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi | 26 +++++++++++++++++++ 2 files changed, 26 insertions(+), 11 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts index 96fa26365248..1a8dd23eda33 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts @@ -43,13 +43,6 @@ }; &main_pmx0 { - main_i2c0_pins_default: main-i2c0-pins-default { - pinctrl-single,pins = < - J721E_IOPAD(0xd4, PIN_INPUT_PULLUP, 0) /* (V3) I2C0_SCL */ - J721E_IOPAD(0xd8, PIN_INPUT_PULLUP, 0) /* (W2) I2C0_SDA */ - >; - }; - main_i2c1_pins_default: main-i2c1-pins-default { pinctrl-single,pins = < J721E_IOPAD(0xdc, PIN_INPUT_PULLUP, 3) /* (U3) ECAP0_IN_APWM_OUT.I2C1_SCL */ @@ -146,10 +139,6 @@ }; &main_i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&main_i2c0_pins_default>; - clock-frequency = <400000>; - exp1: gpio@20 { compatible = "ti,tca6416"; reg = <0x20>; diff --git a/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi index fbd17d38f6b6..7b5e9aa0324e 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi @@ -48,6 +48,15 @@ }; }; +&main_pmx0 { + main_i2c0_pins_default: main-i2c0-pins-default { + pinctrl-single,pins = < + J721E_IOPAD(0xd4, PIN_INPUT_PULLUP, 0) /* (V3) I2C0_SCL */ + J721E_IOPAD(0xd8, PIN_INPUT_PULLUP, 0) /* (W2) I2C0_SDA */ + >; + }; +}; + &hbmc { /* OSPI and HBMC are muxed inside FSS, Bootloader will enable * appropriate node based on board detection @@ -131,3 +140,20 @@ &mailbox0_cluster11 { status = "disabled"; }; + +&main_i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c0_pins_default>; + clock-frequency = <400000>; + + exp_som: gpio@21 { + compatible = "ti,tca6408"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = "USB2.0_MUX_SEL", "CANUART_MUX1_SEL0", + "CANUART_MUX2_SEL0", "CANUART_MUX_SEL1", + "UART/LIN_MUX_SEL", "TRC_D17/AUDIO_REFCLK_SEL", + "GPIO_LIN_EN", "CAN_STB"; + }; +}; From 2eefbf5f862ed98a043917fa54c7a79a56ec08f6 Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Fri, 20 Nov 2020 09:35:33 +0200 Subject: [PATCH 585/799] arm64: dts: ti: k3-j7200-common-proc-board: Correct the name of io expander on main_i2c1 J7200 main_i2c1 is connected to the i2c bus on the CPB marked as main_i2c3 The i2c1 devices on the CPB are _not_ connected to the SoC, they are not usable with the J7200 SOM. Correct the expander name from exp4 to exp3 and at the same time add the line names as well. Signed-off-by: Peter Ujfalusi Signed-off-by: Nishanth Menon Reviewed-by: Vignesh Raghavendra Reviewed-by: Grygorii Strashko Link: https://lore.kernel.org/r/20201120073533.24486-3-peter.ujfalusi@ti.com --- .../arm64/boot/dts/ti/k3-j7200-common-proc-board.dts | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts index 1a8dd23eda33..331b388e1d1b 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts @@ -154,16 +154,26 @@ }; }; +/* + * The j7200 CPB board is identical to the CPB used for J721E, the SOMs can be + * swapped on the CPB. + * + * main_i2c1 of J7200 is connected to the CPB i2c bus labeled as i2c3. + * The i2c1 of the CPB (as it is labeled) is not connected to j7200. + */ &main_i2c1 { pinctrl-names = "default"; pinctrl-0 = <&main_i2c1_pins_default>; clock-frequency = <400000>; - exp4: gpio@20 { + exp3: gpio@20 { compatible = "ti,tca6408"; reg = <0x20>; gpio-controller; #gpio-cells = <2>; + gpio-line-names = "CODEC_RSTz", "CODEC_SPARE1", "UB926_RESETn", + "UB926_LOCK", "UB926_PWR_SW_CNTRL", + "UB926_TUNER_RESET", "UB926_GPIO_SPARE", ""; }; }; From 6a0eaf5123e0e1223252b88cd5775f74105e27bd Mon Sep 17 00:00:00 2001 From: Dean Camera Date: Thu, 26 Nov 2020 09:39:34 +1100 Subject: [PATCH 586/799] HID: Increase HID maximum report size to 16KB Currently the maximum HID report size which can be buffered by the kernel is 8KB. This is sufficient for the vast majority of HID devices on the market, as most HID reports are fairly small. However, some unusual devices such as the Elgate Stream Deck exist which use a report size slightly over 8KB for the image data that is sent to the device. Reports these large cannot be buffered by the regular HID subsystem currently, thus the only way to use such device is to bypass the HID subsystem entirely. This increases the maximum HID report size to 16KB, which should cover all sanely designed HID devices. Signed-off-by: Dean Camera Signed-off-by: Jiri Kosina --- include/linux/hid.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/linux/hid.h b/include/linux/hid.h index b079146850e6..c39d71eb1fd0 100644 --- a/include/linux/hid.h +++ b/include/linux/hid.h @@ -494,7 +494,7 @@ struct hid_report_enum { }; #define HID_MIN_BUFFER_SIZE 64 /* make sure there is at least a packet size of space */ -#define HID_MAX_BUFFER_SIZE 8192 /* 8kb */ +#define HID_MAX_BUFFER_SIZE 16384 /* 16kb */ #define HID_CONTROL_FIFO_SIZE 256 /* to init devices with >100 reports */ #define HID_OUTPUT_FIFO_SIZE 64 From f43d3870cafa2a0f3854c1819c8385733db8f9ae Mon Sep 17 00:00:00 2001 From: Dean Camera Date: Thu, 26 Nov 2020 09:39:57 +1100 Subject: [PATCH 587/799] HID: hidraw: Add additional hidraw input/output report ioctls. Currently the hidraw module can only read and write feature HID reports on demand, via dedicated ioctls. Input reports are read from the device through the read() interface, while output reports are written through the write interface(). This is insufficient; it is desirable in many situations to be able to read and write input and output reports through the control interface to cover additional scenarios: - Reading an input report by its report ID, to get initial state - Writing an input report, to set initial input state in the device - Reading an output report by its report ID, to obtain current state - Writing an output report by its report ID, out of band This patch adds these missing ioctl requests to read and write the remaining HID report types. Note that not all HID backends will neccesarily support this (e.g. while the USB link layer supports setting Input reports, others may not). Also included are documentation and example updates. The current hidraw documentation states that feature reports read from the device does *not* include the report ID, however this is not the case and the returned report will have its report ID prepended by conforming HID devices, as the report data sent from the device over the control endpoint must be indentical in format to those sent over the regular transport. Signed-off-by: Dean Camera Signed-off-by: Jiri Kosina --- Documentation/hid/hidraw.rst | 45 ++++++++++++++++++++++++++++++++++-- drivers/hid/hidraw.c | 24 ++++++++++++++++++- include/uapi/linux/hidraw.h | 6 +++++ samples/hidraw/hid-example.c | 2 +- 4 files changed, 73 insertions(+), 4 deletions(-) diff --git a/Documentation/hid/hidraw.rst b/Documentation/hid/hidraw.rst index 4a4a0ba1f362..f41c1f0f6252 100644 --- a/Documentation/hid/hidraw.rst +++ b/Documentation/hid/hidraw.rst @@ -123,8 +123,49 @@ HIDIOCGFEATURE(len): This ioctl will request a feature report from the device using the control endpoint. The first byte of the supplied buffer should be set to the report number of the requested report. For devices which do not use numbered -reports, set the first byte to 0. The report will be returned starting at -the first byte of the buffer (ie: the report number is not returned). +reports, set the first byte to 0. The returned report buffer will contain the +report number in the first byte, followed by the report data read from the +device. For devices which do not use numbered reports, the report data will +begin at the first byte of the returned buffer. + +HIDIOCSINPUT(len): + Send an Input Report + +This ioctl will send an input report to the device, using the control endpoint. +In most cases, setting an input HID report on a device is meaningless and has +no effect, but some devices may choose to use this to set or reset an initial +state of a report. The format of the buffer issued with this report is identical +to that of HIDIOCSFEATURE. + +HIDIOCGINPUT(len): + Get an Input Report + +This ioctl will request an input report from the device using the control +endpoint. This is slower on most devices where a dedicated In endpoint exists +for regular input reports, but allows the host to request the value of a +specific report number. Typically, this is used to request the initial states of +an input report of a device, before an application listens for normal reports via +the regular device read() interface. The format of the buffer issued with this report +is identical to that of HIDIOCGFEATURE. + +HIDIOCSOUTPUT(len): + Send an Output Report + +This ioctl will send an output report to the device, using the control endpoint. +This is slower on most devices where a dedicated Out endpoint exists for regular +output reports, but is added for completeness. Typically, this is used to set +the initial states of an output report of a device, before an application sends +updates via the regular device write() interface. The format of the buffer issued +with this report is identical to that of HIDIOCSFEATURE. + +HIDIOCGOUTPUT(len): + Get an Output Report + +This ioctl will request an output report from the device using the control +endpoint. Typically, this is used to retrive the initial state of +an output report of a device, before an application updates it as necessary either +via a HIDIOCSOUTPUT request, or the regular device write() interface. The format +of the buffer issued with this report is identical to that of HIDIOCGFEATURE. Example ------- diff --git a/drivers/hid/hidraw.c b/drivers/hid/hidraw.c index 2eee5e31c2b7..79faac87a06f 100644 --- a/drivers/hid/hidraw.c +++ b/drivers/hid/hidraw.c @@ -170,7 +170,7 @@ static ssize_t hidraw_write(struct file *file, const char __user *buffer, size_t /* * This function performs a Get_Report transfer over the control endpoint * per section 7.2.1 of the HID specification, version 1.1. The first byte - * of buffer is the report number to request, or 0x0 if the defice does not + * of buffer is the report number to request, or 0x0 if the device does not * use numbered reports. The report_type parameter can be HID_FEATURE_REPORT * or HID_INPUT_REPORT. */ @@ -428,6 +428,28 @@ static long hidraw_ioctl(struct file *file, unsigned int cmd, break; } + if (_IOC_NR(cmd) == _IOC_NR(HIDIOCSINPUT(0))) { + int len = _IOC_SIZE(cmd); + ret = hidraw_send_report(file, user_arg, len, HID_INPUT_REPORT); + break; + } + if (_IOC_NR(cmd) == _IOC_NR(HIDIOCGINPUT(0))) { + int len = _IOC_SIZE(cmd); + ret = hidraw_get_report(file, user_arg, len, HID_INPUT_REPORT); + break; + } + + if (_IOC_NR(cmd) == _IOC_NR(HIDIOCSOUTPUT(0))) { + int len = _IOC_SIZE(cmd); + ret = hidraw_send_report(file, user_arg, len, HID_OUTPUT_REPORT); + break; + } + if (_IOC_NR(cmd) == _IOC_NR(HIDIOCGOUTPUT(0))) { + int len = _IOC_SIZE(cmd); + ret = hidraw_get_report(file, user_arg, len, HID_OUTPUT_REPORT); + break; + } + /* Begin Read-only ioctls. */ if (_IOC_DIR(cmd) != _IOC_READ) { ret = -EINVAL; diff --git a/include/uapi/linux/hidraw.h b/include/uapi/linux/hidraw.h index 4913539e5bcc..33ebad81720a 100644 --- a/include/uapi/linux/hidraw.h +++ b/include/uapi/linux/hidraw.h @@ -40,6 +40,12 @@ struct hidraw_devinfo { #define HIDIOCSFEATURE(len) _IOC(_IOC_WRITE|_IOC_READ, 'H', 0x06, len) #define HIDIOCGFEATURE(len) _IOC(_IOC_WRITE|_IOC_READ, 'H', 0x07, len) #define HIDIOCGRAWUNIQ(len) _IOC(_IOC_READ, 'H', 0x08, len) +/* The first byte of SINPUT and GINPUT is the report number */ +#define HIDIOCSINPUT(len) _IOC(_IOC_WRITE|_IOC_READ, 'H', 0x09, len) +#define HIDIOCGINPUT(len) _IOC(_IOC_WRITE|_IOC_READ, 'H', 0x0A, len) +/* The first byte of SOUTPUT and GOUTPUT is the report number */ +#define HIDIOCSOUTPUT(len) _IOC(_IOC_WRITE|_IOC_READ, 'H', 0x0B, len) +#define HIDIOCGOUTPUT(len) _IOC(_IOC_WRITE|_IOC_READ, 'H', 0x0C, len) #define HIDRAW_FIRST_MINOR 0 #define HIDRAW_MAX_DEVICES 64 diff --git a/samples/hidraw/hid-example.c b/samples/hidraw/hid-example.c index 37a0ffcb4d63..0f73ace3c6c3 100644 --- a/samples/hidraw/hid-example.c +++ b/samples/hidraw/hid-example.c @@ -128,7 +128,7 @@ int main(int argc, char **argv) perror("HIDIOCGFEATURE"); } else { printf("ioctl HIDIOCGFEATURE returned: %d\n", res); - printf("Report data (not containing the report number):\n\t"); + printf("Report data:\n\t"); for (i = 0; i < res; i++) printf("%hhx ", buf[i]); puts("\n"); From cc894ac553605c9193a7a94372ff2f8af5766f46 Mon Sep 17 00:00:00 2001 From: Pascal Giard Date: Wed, 25 Nov 2020 22:02:30 -0500 Subject: [PATCH 588/799] HID: sony: support for ghlive ps3/wii u dongles This commit adds support for the Guitar Hero Live PS3 and Wii U dongles. These dongles require a "magic" USB control message [1] to be sent approximately every 10 seconds otherwise the dongle will not report events where the strumbar is hit while a fret is being held. Also, inspired by a patch sent on linux-input by Sanjay Govind [2], the accelerometer is mapped to ABS_RY for tilt. Interestingly, the Wii U and PS3 dongles share the same VID and PID. [1] https://github.com/ghlre/GHLtarUtility/ [2] https://marc.info/?l=linux-input&m=157242835928542&w=2 Signed-off-by: Pascal Giard Signed-off-by: Jiri Kosina --- drivers/hid/Kconfig | 1 + drivers/hid/hid-ids.h | 3 ++ drivers/hid/hid-sony.c | 112 +++++++++++++++++++++++++++++++++++++++++ 3 files changed, 116 insertions(+) diff --git a/drivers/hid/Kconfig b/drivers/hid/Kconfig index 612629678c84..18b3ad50e1ca 100644 --- a/drivers/hid/Kconfig +++ b/drivers/hid/Kconfig @@ -907,6 +907,7 @@ config HID_SONY * Buzz controllers * Sony PS3 Blue-ray Disk Remote Control (Bluetooth) * Logitech Harmony adapter for Sony Playstation 3 (Bluetooth) + * Guitar Hero Live PS3 and Wii U guitar dongles config SONY_FF bool "Sony PS2/3/4 accessories force feedback support" diff --git a/drivers/hid/hid-ids.h b/drivers/hid/hid-ids.h index f170feaac40b..eee6e27d5f1e 100644 --- a/drivers/hid/hid-ids.h +++ b/drivers/hid/hid-ids.h @@ -1074,6 +1074,9 @@ #define USB_DEVICE_ID_SONY_BUZZ_CONTROLLER 0x0002 #define USB_DEVICE_ID_SONY_WIRELESS_BUZZ_CONTROLLER 0x1000 +#define USB_VENDOR_ID_SONY_GHLIVE 0x12ba +#define USB_DEVICE_ID_SONY_PS3WIIU_GHLIVE_DONGLE 0x074b + #define USB_VENDOR_ID_SINO_LITE 0x1345 #define USB_DEVICE_ID_SINO_LITE_CONTROLLER 0x3008 diff --git a/drivers/hid/hid-sony.c b/drivers/hid/hid-sony.c index 485455c300f2..326c4bdbd0ea 100644 --- a/drivers/hid/hid-sony.c +++ b/drivers/hid/hid-sony.c @@ -11,6 +11,7 @@ * Copyright (c) 2013 Colin Leitner * Copyright (c) 2014-2016 Frank Praznik * Copyright (c) 2018 Todd Kelner + * Copyright (c) 2020 Pascal Giard */ /* @@ -35,6 +36,8 @@ #include #include #include +#include +#include #include #include "hid-ids.h" @@ -56,6 +59,7 @@ #define NSG_MR5U_REMOTE_BT BIT(14) #define NSG_MR7U_REMOTE_BT BIT(15) #define SHANWAN_GAMEPAD BIT(16) +#define GHL_GUITAR_PS3WIIU BIT(17) #define SIXAXIS_CONTROLLER (SIXAXIS_CONTROLLER_USB | SIXAXIS_CONTROLLER_BT) #define MOTION_CONTROLLER (MOTION_CONTROLLER_USB | MOTION_CONTROLLER_BT) @@ -79,6 +83,17 @@ #define NSG_MRXU_MAX_X 1667 #define NSG_MRXU_MAX_Y 1868 +#define GHL_GUITAR_POKE_INTERVAL 10 /* In seconds */ +#define GHL_GUITAR_TILT_USAGE 44 + +/* Magic value and data taken from GHLtarUtility: + * https://github.com/ghlre/GHLtarUtility/blob/master/PS3Guitar.cs + * Note: The Wii U and PS3 dongles happen to share the same! + */ +static const u16 ghl_ps3wiiu_magic_value = 0x201; +static const char ghl_ps3wiiu_magic_data[] = { + 0x02, 0x08, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00 +}; /* PS/3 Motion controller */ static u8 motion_rdesc[] = { @@ -579,6 +594,10 @@ struct sony_sc { enum ds4_dongle_state ds4_dongle_state; /* DS4 calibration data */ struct ds4_calibration_data ds4_calib_data[6]; + /* GH Live */ + struct timer_list ghl_poke_timer; + struct usb_ctrlrequest *ghl_cr; + u8 *ghl_databuf; }; static void sony_set_leds(struct sony_sc *sc); @@ -602,6 +621,85 @@ static inline void sony_schedule_work(struct sony_sc *sc, } } +static void ghl_magic_poke_cb(struct urb *urb) +{ + if (urb) { + /* Free sc->ghl_cr and sc->ghl_databuf allocated in + * ghl_magic_poke() + */ + kfree(urb->setup_packet); + kfree(urb->transfer_buffer); + } +} + +static void ghl_magic_poke(struct timer_list *t) +{ + struct sony_sc *sc = from_timer(sc, t, ghl_poke_timer); + + int ret; + unsigned int pipe; + struct urb *urb; + struct usb_device *usbdev = to_usb_device(sc->hdev->dev.parent->parent); + const u16 poke_size = + ARRAY_SIZE(ghl_ps3wiiu_magic_data); + + pipe = usb_sndctrlpipe(usbdev, 0); + + if (!sc->ghl_cr) { + sc->ghl_cr = kzalloc(sizeof(*sc->ghl_cr), GFP_ATOMIC); + if (!sc->ghl_cr) + goto resched; + } + + if (!sc->ghl_databuf) { + sc->ghl_databuf = kzalloc(poke_size, GFP_ATOMIC); + if (!sc->ghl_databuf) + goto resched; + } + + urb = usb_alloc_urb(0, GFP_ATOMIC); + if (!urb) + goto resched; + + sc->ghl_cr->bRequestType = + USB_RECIP_INTERFACE | USB_TYPE_CLASS | USB_DIR_OUT; + sc->ghl_cr->bRequest = USB_REQ_SET_CONFIGURATION; + sc->ghl_cr->wValue = cpu_to_le16(ghl_ps3wiiu_magic_value); + sc->ghl_cr->wIndex = 0; + sc->ghl_cr->wLength = cpu_to_le16(poke_size); + memcpy(sc->ghl_databuf, ghl_ps3wiiu_magic_data, poke_size); + + usb_fill_control_urb( + urb, usbdev, pipe, + (unsigned char *) sc->ghl_cr, sc->ghl_databuf, + poke_size, ghl_magic_poke_cb, NULL); + ret = usb_submit_urb(urb, GFP_ATOMIC); + if (ret < 0) { + kfree(sc->ghl_databuf); + kfree(sc->ghl_cr); + } + usb_free_urb(urb); + +resched: + /* Reschedule for next time */ + mod_timer(&sc->ghl_poke_timer, jiffies + GHL_GUITAR_POKE_INTERVAL*HZ); +} + +static int guitar_mapping(struct hid_device *hdev, struct hid_input *hi, + struct hid_field *field, struct hid_usage *usage, + unsigned long **bit, int *max) +{ + if ((usage->hid & HID_USAGE_PAGE) == HID_UP_MSVENDOR) { + unsigned int abs = usage->hid & HID_USAGE; + + if (abs == GHL_GUITAR_TILT_USAGE) { + hid_map_usage_clear(hi, usage, bit, max, EV_ABS, ABS_RY); + return 1; + } + } + return 0; +} + static ssize_t ds4_show_poll_interval(struct device *dev, struct device_attribute *attr, char *buf) @@ -1383,6 +1481,8 @@ static int sony_mapping(struct hid_device *hdev, struct hid_input *hi, if (sc->quirks & DUALSHOCK4_CONTROLLER) return ds4_mapping(hdev, hi, field, usage, bit, max); + if (sc->quirks & GHL_GUITAR_PS3WIIU) + return guitar_mapping(hdev, hi, field, usage, bit, max); /* Let hid-core decide for the others */ return 0; @@ -2917,6 +3017,12 @@ static int sony_probe(struct hid_device *hdev, const struct hid_device_id *id) return -ENODEV; } + if (sc->quirks & GHL_GUITAR_PS3WIIU) { + timer_setup(&sc->ghl_poke_timer, ghl_magic_poke, 0); + mod_timer(&sc->ghl_poke_timer, + jiffies + GHL_GUITAR_POKE_INTERVAL*HZ); + } + return ret; } @@ -2924,6 +3030,9 @@ static void sony_remove(struct hid_device *hdev) { struct sony_sc *sc = hid_get_drvdata(hdev); + if (sc->quirks & GHL_GUITAR_PS3WIIU) + del_timer_sync(&sc->ghl_poke_timer); + hid_hw_close(hdev); if (sc->quirks & DUALSHOCK4_CONTROLLER_BT) @@ -3035,6 +3144,9 @@ static const struct hid_device_id sony_devices[] = { /* SMK-Link NSG-MR7U Remote Control */ { HID_BLUETOOTH_DEVICE(USB_VENDOR_ID_SMK, USB_DEVICE_ID_SMK_NSG_MR7U_REMOTE), .driver_data = NSG_MR7U_REMOTE_BT }, + /* Guitar Hero Live PS3 and Wii U guitar dongles */ + { HID_USB_DEVICE(USB_VENDOR_ID_SONY_GHLIVE, USB_DEVICE_ID_SONY_PS3WIIU_GHLIVE_DONGLE), + .driver_data = GHL_GUITAR_PS3WIIU}, { } }; MODULE_DEVICE_TABLE(hid, sony_devices); From c961facb5b19634eee5bcdd91fc5bf3f1c545bc5 Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Wed, 25 Nov 2020 23:37:45 +0100 Subject: [PATCH 589/799] HID: ite: Add support for Acer S1002 keyboard-dock Make the hid-ite driver handle the Acer S1002 keyboard-dock, this leads to 2 improvements: 1. The non working wifi-toggle hotkey now works. 2. Toggling the touchpad on of with the hotkey will no show OSD notifications in e.g. GNOME3. The actual toggling is handled inside the keyboard, this adds support for notifying evdev listeners about this. Signed-off-by: Hans de Goede Signed-off-by: Jiri Kosina --- drivers/hid/hid-ids.h | 1 + drivers/hid/hid-ite.c | 13 ++++++++++++- 2 files changed, 13 insertions(+), 1 deletion(-) diff --git a/drivers/hid/hid-ids.h b/drivers/hid/hid-ids.h index d1841fece116..787b20d02451 100644 --- a/drivers/hid/hid-ids.h +++ b/drivers/hid/hid-ids.h @@ -1134,6 +1134,7 @@ #define USB_DEVICE_ID_SYNAPTICS_DELL_K12A 0x2819 #define USB_DEVICE_ID_SYNAPTICS_ACER_SWITCH5_012 0x2968 #define USB_DEVICE_ID_SYNAPTICS_TP_V103 0x5710 +#define USB_DEVICE_ID_SYNAPTICS_ACER_ONE_S1002 0x73f4 #define USB_DEVICE_ID_SYNAPTICS_ACER_ONE_S1003 0x73f5 #define USB_DEVICE_ID_SYNAPTICS_ACER_SWITCH5 0x81a7 diff --git a/drivers/hid/hid-ite.c b/drivers/hid/hid-ite.c index 742c052b0110..22bfbebceaf4 100644 --- a/drivers/hid/hid-ite.c +++ b/drivers/hid/hid-ite.c @@ -18,10 +18,16 @@ static __u8 *ite_report_fixup(struct hid_device *hdev, __u8 *rdesc, unsigned int unsigned long quirks = (unsigned long)hid_get_drvdata(hdev); if (quirks & QUIRK_TOUCHPAD_ON_OFF_REPORT) { + /* For Acer Aspire Switch 10 SW5-012 keyboard-dock */ if (*rsize == 188 && rdesc[162] == 0x81 && rdesc[163] == 0x02) { - hid_info(hdev, "Fixing up ITE keyboard report descriptor\n"); + hid_info(hdev, "Fixing up Acer Sw5-012 ITE keyboard report descriptor\n"); rdesc[163] = HID_MAIN_ITEM_RELATIVE; } + /* For Acer One S1002 keyboard-dock */ + if (*rsize == 188 && rdesc[185] == 0x81 && rdesc[186] == 0x02) { + hid_info(hdev, "Fixing up Acer S1002 ITE keyboard report descriptor\n"); + rdesc[186] = HID_MAIN_ITEM_RELATIVE; + } } return rdesc; @@ -101,6 +107,11 @@ static const struct hid_device_id ite_devices[] = { USB_DEVICE_ID_SYNAPTICS_ACER_SWITCH5_012), .driver_data = QUIRK_TOUCHPAD_ON_OFF_REPORT }, /* ITE8910 USB kbd ctlr, with Synaptics touchpad connected to it. */ + { HID_DEVICE(BUS_USB, HID_GROUP_GENERIC, + USB_VENDOR_ID_SYNAPTICS, + USB_DEVICE_ID_SYNAPTICS_ACER_ONE_S1002), + .driver_data = QUIRK_TOUCHPAD_ON_OFF_REPORT }, + /* ITE8910 USB kbd ctlr, with Synaptics touchpad connected to it. */ { HID_DEVICE(BUS_USB, HID_GROUP_GENERIC, USB_VENDOR_ID_SYNAPTICS, USB_DEVICE_ID_SYNAPTICS_ACER_ONE_S1003) }, From c870d50ce387d84b6438211a7044c60afbd5d60a Mon Sep 17 00:00:00 2001 From: Julian Sax Date: Thu, 26 Nov 2020 18:51:58 +0100 Subject: [PATCH 590/799] HID: i2c-hid: add Vero K147 to descriptor override This device uses the SIPODEV SP1064 touchpad, which does not supply descriptors, so it has to be added to the override list. Cc: stable@vger.kernel.org Signed-off-by: Julian Sax Reviewed-by: Hans de Goede Signed-off-by: Jiri Kosina --- drivers/hid/i2c-hid/i2c-hid-dmi-quirks.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/hid/i2c-hid/i2c-hid-dmi-quirks.c b/drivers/hid/i2c-hid/i2c-hid-dmi-quirks.c index 35f3bfc3e6f5..8e0f67455c09 100644 --- a/drivers/hid/i2c-hid/i2c-hid-dmi-quirks.c +++ b/drivers/hid/i2c-hid/i2c-hid-dmi-quirks.c @@ -405,6 +405,14 @@ static const struct dmi_system_id i2c_hid_dmi_desc_override_table[] = { }, .driver_data = (void *)&sipodev_desc }, + { + .ident = "Vero K147", + .matches = { + DMI_EXACT_MATCH(DMI_SYS_VENDOR, "VERO"), + DMI_EXACT_MATCH(DMI_PRODUCT_NAME, "K147"), + }, + .driver_data = (void *)&sipodev_desc + }, { } /* Terminate list */ }; From 3f0716710ae93e467cd313855c1aa96dd40321d2 Mon Sep 17 00:00:00 2001 From: Frank Wunderlich Date: Fri, 16 Oct 2020 22:40:17 +0200 Subject: [PATCH 591/799] dts64: mt7622: enable all pwm for bananapi r64 mt7622 only supports 6 pwm-channels so drop pwm7 third pwm (pwm2) is inverted and connected to fan-socket Signed-off-by: Frank Wunderlich Link: https://lore.kernel.org/r/20201016204019.2606-2-linux@fw-web.de Signed-off-by: Matthias Brugger --- .../boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts index 9a11e5c60c26..ca8d5c7a1346 100644 --- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts +++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts @@ -412,10 +412,15 @@ }; }; - pwm7_pins: pwm1-2-pins { + pwm_pins: pwm-pins { mux { function = "pwm"; - groups = "pwm_ch7_2"; + groups = "pwm_ch1_0", /* mt7622_pwm_ch1_0_pins[] = { 51, }; */ + "pwm_ch2_0", /* mt7622_pwm_ch2_0_pins[] = { 52, }; */ + "pwm_ch3_2", /* mt7622_pwm_ch3_2_pins[] = { 97, }; */ + "pwm_ch4_1", /* mt7622_pwm_ch4_1_pins[] = { 67, }; */ + "pwm_ch5_0", /* mt7622_pwm_ch5_0_pins[] = { 68, }; */ + "pwm_ch6_0"; /* mt7622_pwm_ch6_0_pins[] = { 69, }; */ }; }; @@ -535,7 +540,7 @@ &pwm { pinctrl-names = "default"; - pinctrl-0 = <&pwm7_pins>; + pinctrl-0 = <&pwm_pins>; status = "okay"; }; From 5833bc6c7319dd59441562d853b8e435e3bc8ac2 Mon Sep 17 00:00:00 2001 From: Frank Wunderlich Date: Fri, 16 Oct 2020 22:40:18 +0200 Subject: [PATCH 592/799] dts64: mt7622: disable spi1 and uart2 because pins are used by pwm MDI_TP_P0 (gpio51) is used by pwm1 and uart2 (uart1 on gpio-header) MDI_RP_P4 (gpio67) is used by pwm4 and spi1 Signed-off-by: Frank Wunderlich Link: https://lore.kernel.org/r/20201016204019.2606-3-linux@fw-web.de Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts index ca8d5c7a1346..2f77dc40b9b8 100644 --- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts +++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts @@ -568,7 +568,6 @@ &spi1 { pinctrl-names = "default"; pinctrl-0 = <&spic1_pins>; - status = "okay"; }; &ssusb { @@ -590,7 +589,6 @@ &uart2 { pinctrl-names = "default"; pinctrl-0 = <&uart2_pins>; - status = "okay"; }; &watchdog { From 950be99fccffa920e148fd46e33db4d509e8af63 Mon Sep 17 00:00:00 2001 From: Florian Fainelli Date: Sun, 8 Nov 2020 20:42:27 -0800 Subject: [PATCH 593/799] ARM: multi_v7_defconfig: Enable ARM SCMI protocol and drivers Enable the ARM SCMI protocol and the common clock, cpufreq and sensors drivers. Broadcom STB platforms (ARCH_BRCMSTB) implement SCMI to provide support for CPU frequency scaling, clock configuration and temperature and current sensors. Signed-off-by: Florian Fainelli Acked-by: Sudeep Holla --- arch/arm/configs/multi_v7_defconfig | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig index e731cdf7c88c..f18e8f95c0eb 100644 --- a/arch/arm/configs/multi_v7_defconfig +++ b/arch/arm/configs/multi_v7_defconfig @@ -109,6 +109,7 @@ CONFIG_CPU_FREQ_GOV_CONSERVATIVE=m CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y CONFIG_CPUFREQ_DT=y CONFIG_ARM_IMX6Q_CPUFREQ=y +CONFIG_ARM_SCMI_CPUFREQ=y CONFIG_ARM_RASPBERRYPI_CPUFREQ=y CONFIG_QORIQ_CPUFREQ=y CONFIG_CPU_IDLE=y @@ -117,6 +118,7 @@ CONFIG_ARM_ZYNQ_CPUIDLE=y CONFIG_ARM_EXYNOS_CPUIDLE=y CONFIG_ARM_TEGRA_CPUIDLE=y CONFIG_KERNEL_MODE_NEON=y +CONFIG_ARM_SCMI_PROTOCOL=y CONFIG_RASPBERRYPI_FIRMWARE=y CONFIG_TRUSTED_FOUNDATIONS=y CONFIG_BCM47XX_NVRAM=y @@ -487,6 +489,7 @@ CONFIG_CHARGER_MAX77693=m CONFIG_CHARGER_MAX8997=m CONFIG_CHARGER_MAX8998=m CONFIG_CHARGER_TPS65090=y +CONFIG_SENSORS_ARM_SCMI=y CONFIG_SENSORS_ASPEED=m CONFIG_SENSORS_IIO_HWMON=y CONFIG_SENSORS_LM90=y @@ -958,6 +961,7 @@ CONFIG_CROS_EC_I2C=m CONFIG_CROS_EC_SPI=m CONFIG_COMMON_CLK_MAX77686=y CONFIG_COMMON_CLK_RK808=m +CONFIG_COMMON_CLK_SCMI=y CONFIG_COMMON_CLK_S2MPS11=m CONFIG_CLK_RASPBERRYPI=y CONFIG_COMMON_CLK_QCOM=y From 6a7dc2b3639adc7f9ff5c148aeaef0ee775f6c3a Mon Sep 17 00:00:00 2001 From: Florian Fainelli Date: Sun, 8 Nov 2020 20:42:28 -0800 Subject: [PATCH 594/799] arm64: defconfig: Enable ARM SCMI protocol and drivers Enable the ARM SCMI protocol and the common clock, cpufreq, reset and sensors drivers. Broadcom STB platforms (ARCH_BRCMSTB) implement SCMI to provide support for CPU frequency scaling, clock configuration and temperature and current sensors. Signed-off-by: Florian Fainelli Acked-by: Sudeep Holla --- arch/arm64/configs/defconfig | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 17a2df6a263e..4fdad094b44a 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -93,8 +93,10 @@ CONFIG_ARM_IMX_CPUFREQ_DT=m CONFIG_ARM_QCOM_CPUFREQ_NVMEM=y CONFIG_ARM_QCOM_CPUFREQ_HW=y CONFIG_ARM_RASPBERRYPI_CPUFREQ=m +CONFIG_ARM_SCMI_CPUFREQ=y CONFIG_ARM_TEGRA186_CPUFREQ=y CONFIG_QORIQ_CPUFREQ=y +CONFIG_ARM_SCMI_PROTOCOL=y CONFIG_ARM_SCPI_PROTOCOL=y CONFIG_RASPBERRYPI_FIRMWARE=y CONFIG_INTEL_STRATIX10_SERVICE=y @@ -521,6 +523,7 @@ CONFIG_POWER_RESET_SYSCON=y CONFIG_SYSCON_REBOOT_MODE=y CONFIG_BATTERY_SBS=m CONFIG_BATTERY_BQ27XXX=y +CONFIG_SENSORS_ARM_SCMI=y CONFIG_SENSORS_ARM_SCPI=y CONFIG_SENSORS_LM90=m CONFIG_SENSORS_PWM_FAN=m @@ -864,6 +867,7 @@ CONFIG_CROS_EC=y CONFIG_CROS_EC_I2C=y CONFIG_CROS_EC_SPI=y CONFIG_CROS_EC_CHARDEV=m +CONFIG_COMMON_CLK_SCMI=y CONFIG_COMMON_CLK_RK808=y CONFIG_COMMON_CLK_SCPI=y CONFIG_COMMON_CLK_CS2000_CP=y From 15ffd94a904bafcce6dd4babf8f26bd8fe965bff Mon Sep 17 00:00:00 2001 From: Sekhar Nori Date: Sat, 28 Nov 2020 02:31:28 +0530 Subject: [PATCH 595/799] arm64: dts: ti: k3: squelch warning about lack of #interrupt-cells There are couple of places where INTA interrupt controller lacks #interrupt-cells property. This leads to warnings of the type: arch/arm64/boot/dts/ti/k3-j721e-main.dtsi:147.51-156.5: Warning (interrupt_provider): /bus@100000/main-navss/interrupt-controller@33d00000: Missing #interrupt-cells in interrupt provider when building TI device-tree files with W=2 warning level. Fix these. Signed-off-by: Sekhar Nori Signed-off-by: Nishanth Menon Reviewed-by: Grygorii Strashko Link: https://lore.kernel.org/r/20201127210128.9151-1-nsekhar@ti.com --- arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 1 + arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi index 116818912ba2..12591a854020 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi @@ -472,6 +472,7 @@ interrupt-controller; interrupt-parent = <&intr_main_navss>; msi-controller; + #interrupt-cells = <0>; ti,sci = <&dmsc>; ti,sci-dev-id = <179>; ti,interrupt-ranges = <0 0 256>; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi index 19e602afdb05..4e189b34a99e 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi @@ -148,6 +148,7 @@ interrupt-controller; interrupt-parent = <&main_navss_intr>; msi-controller; + #interrupt-cells = <0>; ti,sci = <&dmsc>; ti,sci-dev-id = <209>; ti,interrupt-ranges = <0 0 256>; From fbdb20b1fcb1a252a70f31b35976cf79dc051f19 Mon Sep 17 00:00:00 2001 From: Jonathan Cameron Date: Sun, 15 Nov 2020 19:29:48 +0000 Subject: [PATCH 596/799] ARM: dts: qcom-pma8084: Drop incorrect use of io-channel-ranges This property is used by io-channel consumers, not providers so should not present here. Note dt_schema will now detect this error as there is a dependency between this property and io-channels. Signed-off-by: Jonathan Cameron Cc: Andy Gross Cc: Bjorn Andersson Link: https://lore.kernel.org/r/20201115192951.1073632-7-jic23@kernel.org Signed-off-by: Bjorn Andersson --- arch/arm/boot/dts/qcom-pma8084.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm/boot/dts/qcom-pma8084.dtsi b/arch/arm/boot/dts/qcom-pma8084.dtsi index ea1ca166165c..e921c5e93a5d 100644 --- a/arch/arm/boot/dts/qcom-pma8084.dtsi +++ b/arch/arm/boot/dts/qcom-pma8084.dtsi @@ -68,7 +68,6 @@ #address-cells = <1>; #size-cells = <0>; #io-channel-cells = <1>; - io-channel-ranges; die_temp { reg = ; From 5c44c564e4491758124050643f00c6bad9bfbea8 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Fri, 27 Nov 2020 23:00:44 +0530 Subject: [PATCH 597/799] arm64: dts: qcom: qrb5165-rb5: Add support for MCP2518FD Add support for onboard MCP2518FD SPI CAN transceiver attached to SPI0 of RB5. Tested-by: Dmitry Baryshkov Signed-off-by: Manivannan Sadhasivam Link: https://lore.kernel.org/r/20201127173044.55144-1-manivannan.sadhasivam@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qrb5165-rb5.dts | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts index d9f52703ba2a..ce22d4fa383e 100644 --- a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts +++ b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts @@ -25,6 +25,13 @@ stdout-path = "serial0:115200n8"; }; + /* Fixed crystal oscillator dedicated to MCP2518FD */ + clk40M: can_clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <40000000>; + }; + dc12v: dc12v-regulator { compatible = "regulator-fixed"; regulator-name = "DC12V"; @@ -493,6 +500,16 @@ /* CAN */ &spi0 { status = "okay"; + + can@0 { + compatible = "microchip,mcp2518fd"; + reg = <0>; + clocks = <&clk40M>; + interrupts-extended = <&tlmm 15 IRQ_TYPE_LEVEL_LOW>; + spi-max-frequency = <10000000>; + vdd-supply = <&vdc_5v>; + xceiver-supply = <&vdc_5v>; + }; }; &tlmm { From b08770ff622829285d5b113602b1454910b34044 Mon Sep 17 00:00:00 2001 From: Luka Kovacic Date: Fri, 24 Jul 2020 12:38:37 +0200 Subject: [PATCH 598/799] ARM: dts: mvebu: Add CRS326-24G-2S board MikroTik CRS326-24G-2S board has a switch chip with an integrated Marvell Prestera 98DX3236 CPU. This commit includes two board variants, namely the factory default one and a Bit variant. The Bit variant has a bigger Macronix flash. This device tree includes basic Linux support. Signed-off-by: Luka Kovacic Cc: Luka Perkov Cc: Jakov Petrina Reviewed-by: Andrew Lunn Signed-off-by: Gregory CLEMENT --- arch/arm/boot/dts/Makefile | 2 + .../boot/dts/armada-xp-crs326-24g-2s-bit.dts | 43 ++++++++ arch/arm/boot/dts/armada-xp-crs326-24g-2s.dts | 17 +++ .../arm/boot/dts/armada-xp-crs326-24g-2s.dtsi | 104 ++++++++++++++++++ 4 files changed, 166 insertions(+) create mode 100644 arch/arm/boot/dts/armada-xp-crs326-24g-2s-bit.dts create mode 100644 arch/arm/boot/dts/armada-xp-crs326-24g-2s.dts create mode 100644 arch/arm/boot/dts/armada-xp-crs326-24g-2s.dtsi diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index ce66ffd5a1bb..dcb1dc357810 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1340,6 +1340,8 @@ dtb-$(CONFIG_MACH_ARMADA_39X) += \ armada-398-db.dtb dtb-$(CONFIG_MACH_ARMADA_XP) += \ armada-xp-axpwifiap.dtb \ + armada-xp-crs326-24g-2s.dtb \ + armada-xp-crs326-24g-2s-bit.dtb \ armada-xp-db.dtb \ armada-xp-db-dxbc2.dtb \ armada-xp-db-xc3-24g4xg.dtb \ diff --git a/arch/arm/boot/dts/armada-xp-crs326-24g-2s-bit.dts b/arch/arm/boot/dts/armada-xp-crs326-24g-2s-bit.dts new file mode 100644 index 000000000000..21f442afab1f --- /dev/null +++ b/arch/arm/boot/dts/armada-xp-crs326-24g-2s-bit.dts @@ -0,0 +1,43 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree file for MikroTik CRS326-24G-2S+ Bit board + * + * Copyright (C) 2020 Sartura Ltd. + * Author: Luka Kovacic + */ + +#include "armada-xp-crs326-24g-2s.dtsi" + +/ { + model = "MikroTik CRS326-24G-2S+ Bit"; +}; + +&spi0 { + status = "okay"; + + spi-flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0>; /* Chip select 0 */ + spi-max-frequency = <108000000>; + m25p,fast-read; + + partition@u-boot { + reg = <0x00000000 0x001f0000>; + label = "u-boot"; + }; + partition@u-boot-env { + reg = <0x001f0000 0x00010000>; + label = "u-boot-env"; + }; + partition@ubi1 { + reg = <0x00200000 0x03f00000>; + label = "ubi1"; + }; + partition@ubi2 { + reg = <0x04100000 0x03f00000>; + label = "ubi2"; + }; + }; +}; diff --git a/arch/arm/boot/dts/armada-xp-crs326-24g-2s.dts b/arch/arm/boot/dts/armada-xp-crs326-24g-2s.dts new file mode 100644 index 000000000000..83aef43f66d5 --- /dev/null +++ b/arch/arm/boot/dts/armada-xp-crs326-24g-2s.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree file for MikroTik CRS326-24G-2S+ board + * + * Copyright (C) 2020 Sartura Ltd. + * Author: Luka Kovacic + */ + +#include "armada-xp-crs326-24g-2s.dtsi" + +/ { + model = "MikroTik CRS326-24G-2S+"; +}; + +&spi0 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/armada-xp-crs326-24g-2s.dtsi b/arch/arm/boot/dts/armada-xp-crs326-24g-2s.dtsi new file mode 100644 index 000000000000..f3e1a25ca5f2 --- /dev/null +++ b/arch/arm/boot/dts/armada-xp-crs326-24g-2s.dtsi @@ -0,0 +1,104 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree file for CRS326-24G-2S board + * + * Copyright (C) 2016 Allied Telesis Labs + * Copyright (C) 2020 Sartura Ltd. + * + * Based on armada-xp-db.dts + * + * Note: this Device Tree assumes that the bootloader has remapped the + * internal registers to 0xf1000000 (instead of the default + * 0xd0000000). The 0xf1000000 is the default used by the recent, + * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier + * boards were delivered with an older version of the bootloader that + * left internal registers mapped at 0xd0000000. If you are in this + * situation, you should either update your bootloader (preferred + * solution) or the below Device Tree should be adjusted. + */ + +/dts-v1/; +#include "armada-xp-98dx3236.dtsi" + +/ { + model = "CRS326-24G-2S+"; + compatible = "mikrotik,crs326-24g-2s", "marvell,armadaxp-98dx3236", "marvell,armada-370-xp"; + + chosen { + bootargs = "console=ttyS0,115200 earlyprintk"; + }; + + memory { + device_type = "memory"; + reg = <0 0x00000000 0 0x20000000>; /* 512 MB */ + }; +}; + +&L2 { + arm,parity-enable; + marvell,ecc-enable; +}; + +&devbus_bootcs { + status = "okay"; + + /* Device Bus parameters are required */ + + /* Read parameters */ + devbus,bus-width = <16>; + devbus,turn-off-ps = <60000>; + devbus,badr-skew-ps = <0>; + devbus,acc-first-ps = <124000>; + devbus,acc-next-ps = <248000>; + devbus,rd-setup-ps = <0>; + devbus,rd-hold-ps = <0>; + + /* Write parameters */ + devbus,sync-enable = <0>; + devbus,wr-high-ps = <60000>; + devbus,wr-low-ps = <60000>; + devbus,ale-wr-ps = <60000>; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&i2c0 { + clock-frequency = <100000>; + status = "okay"; +}; + +&usb0 { + status = "okay"; +}; + +&spi0 { + status = "okay"; + + spi-flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0>; /* Chip select 0 */ + spi-max-frequency = <108000000>; + m25p,fast-read; + + partition@u-boot { + reg = <0x00000000 0x001f0000>; + label = "u-boot"; + }; + partition@u-boot-env { + reg = <0x001f0000 0x00010000>; + label = "u-boot-env"; + }; + partition@ubi1 { + reg = <0x00200000 0x00e00000>; + label = "ubi1"; + }; + }; +}; From 1b7b86f68c24f372e6cf4af4874dc5df3b8aa61b Mon Sep 17 00:00:00 2001 From: Luka Kovacic Date: Fri, 24 Jul 2020 12:38:38 +0200 Subject: [PATCH 599/799] ARM: dts: mvebu: Add CRS305-1G-4S board MikroTik CRS305-1G-4S board has a switch chip with an integrated Marvell Prestera 98DX3236 CPU. This commit includes two board variants, namely the factory default one and a Bit variant. The Bit variant has a bigger Macronix flash. This device tree includes basic Linux support. Signed-off-by: Luka Kovacic Cc: Luka Perkov Cc: Jakov Petrina Reviewed-by: Andrew Lunn Signed-off-by: Gregory CLEMENT --- arch/arm/boot/dts/Makefile | 2 + .../boot/dts/armada-xp-crs305-1g-4s-bit.dts | 43 ++++++++ arch/arm/boot/dts/armada-xp-crs305-1g-4s.dts | 17 +++ arch/arm/boot/dts/armada-xp-crs305-1g-4s.dtsi | 104 ++++++++++++++++++ 4 files changed, 166 insertions(+) create mode 100644 arch/arm/boot/dts/armada-xp-crs305-1g-4s-bit.dts create mode 100644 arch/arm/boot/dts/armada-xp-crs305-1g-4s.dts create mode 100644 arch/arm/boot/dts/armada-xp-crs305-1g-4s.dtsi diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index dcb1dc357810..8d171ac51d1a 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1340,6 +1340,8 @@ dtb-$(CONFIG_MACH_ARMADA_39X) += \ armada-398-db.dtb dtb-$(CONFIG_MACH_ARMADA_XP) += \ armada-xp-axpwifiap.dtb \ + armada-xp-crs305-1g-4s.dtb \ + armada-xp-crs305-1g-4s-bit.dtb \ armada-xp-crs326-24g-2s.dtb \ armada-xp-crs326-24g-2s-bit.dtb \ armada-xp-db.dtb \ diff --git a/arch/arm/boot/dts/armada-xp-crs305-1g-4s-bit.dts b/arch/arm/boot/dts/armada-xp-crs305-1g-4s-bit.dts new file mode 100644 index 000000000000..a022c68dc943 --- /dev/null +++ b/arch/arm/boot/dts/armada-xp-crs305-1g-4s-bit.dts @@ -0,0 +1,43 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree file for MikroTik CRS305-1G-4S+ Bit board + * + * Copyright (C) 2020 Sartura Ltd. + * Author: Luka Kovacic + */ + +#include "armada-xp-crs305-1g-4s.dtsi" + +/ { + model = "MikroTik CRS305-1G-4S+ Bit"; +}; + +&spi0 { + status = "okay"; + + spi-flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0>; /* Chip select 0 */ + spi-max-frequency = <108000000>; + m25p,fast-read; + + partition@u-boot { + reg = <0x00000000 0x001f0000>; + label = "u-boot"; + }; + partition@u-boot-env { + reg = <0x001f0000 0x00010000>; + label = "u-boot-env"; + }; + partition@ubi1 { + reg = <0x00200000 0x03f00000>; + label = "ubi1"; + }; + partition@ubi2 { + reg = <0x04100000 0x03f00000>; + label = "ubi2"; + }; + }; +}; diff --git a/arch/arm/boot/dts/armada-xp-crs305-1g-4s.dts b/arch/arm/boot/dts/armada-xp-crs305-1g-4s.dts new file mode 100644 index 000000000000..010b83b54212 --- /dev/null +++ b/arch/arm/boot/dts/armada-xp-crs305-1g-4s.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree file for MikroTik CRS305-1G-4S+ board + * + * Copyright (C) 2020 Sartura Ltd. + * Author: Luka Kovacic + */ + +#include "armada-xp-crs305-1g-4s.dtsi" + +/ { + model = "MikroTik CRS305-1G-4S+"; +}; + +&spi0 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/armada-xp-crs305-1g-4s.dtsi b/arch/arm/boot/dts/armada-xp-crs305-1g-4s.dtsi new file mode 100644 index 000000000000..32fb21b2bf6a --- /dev/null +++ b/arch/arm/boot/dts/armada-xp-crs305-1g-4s.dtsi @@ -0,0 +1,104 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree file for CRS305-1G-4S board + * + * Copyright (C) 2016 Allied Telesis Labs + * Copyright (C) 2020 Sartura Ltd. + * + * Based on armada-xp-db.dts + * + * Note: this Device Tree assumes that the bootloader has remapped the + * internal registers to 0xf1000000 (instead of the default + * 0xd0000000). The 0xf1000000 is the default used by the recent, + * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier + * boards were delivered with an older version of the bootloader that + * left internal registers mapped at 0xd0000000. If you are in this + * situation, you should either update your bootloader (preferred + * solution) or the below Device Tree should be adjusted. + */ + +/dts-v1/; +#include "armada-xp-98dx3236.dtsi" + +/ { + model = "CRS305-1G-4S+"; + compatible = "mikrotik,crs305-1g-4s", "marvell,armadaxp-98dx3236", "marvell,armada-370-xp"; + + chosen { + bootargs = "console=ttyS0,115200 earlyprintk"; + }; + + memory { + device_type = "memory"; + reg = <0 0x00000000 0 0x20000000>; /* 512 MB */ + }; +}; + +&L2 { + arm,parity-enable; + marvell,ecc-enable; +}; + +&devbus_bootcs { + status = "okay"; + + /* Device Bus parameters are required */ + + /* Read parameters */ + devbus,bus-width = <16>; + devbus,turn-off-ps = <60000>; + devbus,badr-skew-ps = <0>; + devbus,acc-first-ps = <124000>; + devbus,acc-next-ps = <248000>; + devbus,rd-setup-ps = <0>; + devbus,rd-hold-ps = <0>; + + /* Write parameters */ + devbus,sync-enable = <0>; + devbus,wr-high-ps = <60000>; + devbus,wr-low-ps = <60000>; + devbus,ale-wr-ps = <60000>; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&i2c0 { + clock-frequency = <100000>; + status = "okay"; +}; + +&usb0 { + status = "okay"; +}; + +&spi0 { + status = "okay"; + + spi-flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0>; /* Chip select 0 */ + spi-max-frequency = <108000000>; + m25p,fast-read; + + partition@u-boot { + reg = <0x00000000 0x001f0000>; + label = "u-boot"; + }; + partition@u-boot-env { + reg = <0x001f0000 0x00010000>; + label = "u-boot-env"; + }; + partition@ubi1 { + reg = <0x00200000 0x00e00000>; + label = "ubi1"; + }; + }; +}; From d7c51bfa8664e91989f002af9e81983a4fd8326f Mon Sep 17 00:00:00 2001 From: Luka Kovacic Date: Fri, 24 Jul 2020 12:38:39 +0200 Subject: [PATCH 600/799] ARM: dts: mvebu: Add CRS328-4C-20S-4S board MikroTik CRS328-4C-20S-4S board has a switch chip with an integrated Marvell Prestera 98DX3236 CPU. This commit includes two board variants, namely the factory default one and a Bit variant. The Bit variant has a bigger Macronix flash. This device tree includes basic Linux support. Signed-off-by: Luka Kovacic Cc: Luka Perkov Cc: Jakov Petrina Reviewed-by: Andrew Lunn Signed-off-by: Gregory CLEMENT --- arch/arm/boot/dts/Makefile | 2 + .../dts/armada-xp-crs328-4c-20s-4s-bit.dts | 43 ++++++++ .../boot/dts/armada-xp-crs328-4c-20s-4s.dts | 17 +++ .../boot/dts/armada-xp-crs328-4c-20s-4s.dtsi | 104 ++++++++++++++++++ 4 files changed, 166 insertions(+) create mode 100644 arch/arm/boot/dts/armada-xp-crs328-4c-20s-4s-bit.dts create mode 100644 arch/arm/boot/dts/armada-xp-crs328-4c-20s-4s.dts create mode 100644 arch/arm/boot/dts/armada-xp-crs328-4c-20s-4s.dtsi diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 8d171ac51d1a..a89548efdd88 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1344,6 +1344,8 @@ dtb-$(CONFIG_MACH_ARMADA_XP) += \ armada-xp-crs305-1g-4s-bit.dtb \ armada-xp-crs326-24g-2s.dtb \ armada-xp-crs326-24g-2s-bit.dtb \ + armada-xp-crs328-4c-20s-4s.dtb \ + armada-xp-crs328-4c-20s-4s-bit.dtb \ armada-xp-db.dtb \ armada-xp-db-dxbc2.dtb \ armada-xp-db-xc3-24g4xg.dtb \ diff --git a/arch/arm/boot/dts/armada-xp-crs328-4c-20s-4s-bit.dts b/arch/arm/boot/dts/armada-xp-crs328-4c-20s-4s-bit.dts new file mode 100644 index 000000000000..e05aee6cdc04 --- /dev/null +++ b/arch/arm/boot/dts/armada-xp-crs328-4c-20s-4s-bit.dts @@ -0,0 +1,43 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree file for MikroTik CRS328-4C-20S-4S+ Bit board + * + * Copyright (C) 2020 Sartura Ltd. + * Author: Luka Kovacic + */ + +#include "armada-xp-crs328-4c-20s-4s.dtsi" + +/ { + model = "MikroTik CRS328-4C-20S-4S+ Bit"; +}; + +&spi0 { + status = "okay"; + + spi-flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0>; /* Chip select 0 */ + spi-max-frequency = <108000000>; + m25p,fast-read; + + partition@u-boot { + reg = <0x00000000 0x001f0000>; + label = "u-boot"; + }; + partition@u-boot-env { + reg = <0x001f0000 0x00010000>; + label = "u-boot-env"; + }; + partition@ubi1 { + reg = <0x00200000 0x03f00000>; + label = "ubi1"; + }; + partition@ubi2 { + reg = <0x04100000 0x03f00000>; + label = "ubi2"; + }; + }; +}; diff --git a/arch/arm/boot/dts/armada-xp-crs328-4c-20s-4s.dts b/arch/arm/boot/dts/armada-xp-crs328-4c-20s-4s.dts new file mode 100644 index 000000000000..665757f6e18e --- /dev/null +++ b/arch/arm/boot/dts/armada-xp-crs328-4c-20s-4s.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree file for MikroTik CRS328-4C-20S-4S+ board + * + * Copyright (C) 2020 Sartura Ltd. + * Author: Luka Kovacic + */ + +#include "armada-xp-crs328-4c-20s-4s.dtsi" + +/ { + model = "MikroTik CRS328-4C-20S-4S+"; +}; + +&spi0 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/armada-xp-crs328-4c-20s-4s.dtsi b/arch/arm/boot/dts/armada-xp-crs328-4c-20s-4s.dtsi new file mode 100644 index 000000000000..c8b1355ce15e --- /dev/null +++ b/arch/arm/boot/dts/armada-xp-crs328-4c-20s-4s.dtsi @@ -0,0 +1,104 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree file for CRS328-4C-20S-4S+ board + * + * Copyright (C) 2016 Allied Telesis Labs + * Copyright (C) 2020 Sartura Ltd. + * + * Based on armada-xp-db.dts + * + * Note: this Device Tree assumes that the bootloader has remapped the + * internal registers to 0xf1000000 (instead of the default + * 0xd0000000). The 0xf1000000 is the default used by the recent, + * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier + * boards were delivered with an older version of the bootloader that + * left internal registers mapped at 0xd0000000. If you are in this + * situation, you should either update your bootloader (preferred + * solution) or the below Device Tree should be adjusted. + */ + +/dts-v1/; +#include "armada-xp-98dx3236.dtsi" + +/ { + model = "CRS328-4C-20S-4S+"; + compatible = "mikrotik,crs328-4c-20s-4s", "marvell,armadaxp-98dx3236", "marvell,armada-370-xp"; + + chosen { + bootargs = "console=ttyS0,115200 earlyprintk"; + }; + + memory { + device_type = "memory"; + reg = <0 0x00000000 0 0x20000000>; /* 512 MB */ + }; +}; + +&L2 { + arm,parity-enable; + marvell,ecc-enable; +}; + +&devbus_bootcs { + status = "okay"; + + /* Device Bus parameters are required */ + + /* Read parameters */ + devbus,bus-width = <16>; + devbus,turn-off-ps = <60000>; + devbus,badr-skew-ps = <0>; + devbus,acc-first-ps = <124000>; + devbus,acc-next-ps = <248000>; + devbus,rd-setup-ps = <0>; + devbus,rd-hold-ps = <0>; + + /* Write parameters */ + devbus,sync-enable = <0>; + devbus,wr-high-ps = <60000>; + devbus,wr-low-ps = <60000>; + devbus,ale-wr-ps = <60000>; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&i2c0 { + clock-frequency = <100000>; + status = "okay"; +}; + +&usb0 { + status = "okay"; +}; + +&spi0 { + status = "okay"; + + spi-flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0>; /* Chip select 0 */ + spi-max-frequency = <108000000>; + m25p,fast-read; + + partition@u-boot { + reg = <0x00000000 0x001f0000>; + label = "u-boot"; + }; + partition@u-boot-env { + reg = <0x001f0000 0x00010000>; + label = "u-boot-env"; + }; + partition@ubi1 { + reg = <0x00200000 0x00e00000>; + label = "ubi1"; + }; + }; +}; From 8f32220969109b68d766f9b84a682cf3d07ecd33 Mon Sep 17 00:00:00 2001 From: Adrian Schmutzler Date: Sun, 30 Aug 2020 21:35:43 +0200 Subject: [PATCH 601/799] ARM: dts: kirkwood: replace status value "ok" by "okay" While the DT parser recognizes "ok" as a valid value for the "status" property, it is actually mentioned nowhere. Use the proper value "okay" instead, as done in the majority of files already. Signed-off-by: Adrian Schmutzler Reviewed-by: Andrew Lunn Signed-off-by: Gregory CLEMENT --- arch/arm/boot/dts/kirkwood-dockstar.dts | 2 +- arch/arm/boot/dts/kirkwood-dreamplug.dts | 2 +- arch/arm/boot/dts/kirkwood-goflexnet.dts | 2 +- arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts | 2 +- arch/arm/boot/dts/kirkwood-iconnect.dts | 2 +- arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts | 2 +- arch/arm/boot/dts/kirkwood-nsa3x0-common.dtsi | 2 +- arch/arm/boot/dts/kirkwood.dtsi | 4 ++-- 8 files changed, 9 insertions(+), 9 deletions(-) diff --git a/arch/arm/boot/dts/kirkwood-dockstar.dts b/arch/arm/boot/dts/kirkwood-dockstar.dts index 6a3f1bf6d9f1..264938dfa4d9 100644 --- a/arch/arm/boot/dts/kirkwood-dockstar.dts +++ b/arch/arm/boot/dts/kirkwood-dockstar.dts @@ -34,7 +34,7 @@ }; }; serial@12000 { - status = "ok"; + status = "okay"; }; }; gpio-leds { diff --git a/arch/arm/boot/dts/kirkwood-dreamplug.dts b/arch/arm/boot/dts/kirkwood-dreamplug.dts index 7f326e267494..328516351e84 100644 --- a/arch/arm/boot/dts/kirkwood-dreamplug.dts +++ b/arch/arm/boot/dts/kirkwood-dreamplug.dts @@ -34,7 +34,7 @@ }; }; serial@12000 { - status = "ok"; + status = "okay"; }; spi@10600 { diff --git a/arch/arm/boot/dts/kirkwood-goflexnet.dts b/arch/arm/boot/dts/kirkwood-goflexnet.dts index 02d87e0a1061..d4cb3cd3e2a2 100644 --- a/arch/arm/boot/dts/kirkwood-goflexnet.dts +++ b/arch/arm/boot/dts/kirkwood-goflexnet.dts @@ -66,7 +66,7 @@ }; }; serial@12000 { - status = "ok"; + status = "okay"; }; sata@80000 { diff --git a/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts b/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts index ff1260ee3fe8..dfb41393941d 100644 --- a/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts +++ b/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts @@ -38,7 +38,7 @@ }; }; serial@12000 { - status = "ok"; + status = "okay"; }; sata@80000 { diff --git a/arch/arm/boot/dts/kirkwood-iconnect.dts b/arch/arm/boot/dts/kirkwood-iconnect.dts index 4a512d80912c..95af7aa1fdcb 100644 --- a/arch/arm/boot/dts/kirkwood-iconnect.dts +++ b/arch/arm/boot/dts/kirkwood-iconnect.dts @@ -72,7 +72,7 @@ }; }; serial@12000 { - status = "ok"; + status = "okay"; }; }; diff --git a/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts b/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts index 62272d58664f..2338f495d517 100644 --- a/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts +++ b/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts @@ -112,7 +112,7 @@ }; serial@12000 { - status = "ok"; + status = "okay"; }; sata@80000 { diff --git a/arch/arm/boot/dts/kirkwood-nsa3x0-common.dtsi b/arch/arm/boot/dts/kirkwood-nsa3x0-common.dtsi index 2c4037b07282..8f73197f251a 100644 --- a/arch/arm/boot/dts/kirkwood-nsa3x0-common.dtsi +++ b/arch/arm/boot/dts/kirkwood-nsa3x0-common.dtsi @@ -45,7 +45,7 @@ }; serial@12000 { - status = "ok"; + status = "okay"; }; sata@80000 { diff --git a/arch/arm/boot/dts/kirkwood.dtsi b/arch/arm/boot/dts/kirkwood.dtsi index 6c8d94beae78..fca31a5d5ac7 100644 --- a/arch/arm/boot/dts/kirkwood.dtsi +++ b/arch/arm/boot/dts/kirkwood.dtsi @@ -369,7 +369,7 @@ clocks = <&gate_clk 14>; clock-names = "sata"; #phy-cells = <0>; - status = "ok"; + status = "okay"; }; sata_phy1: sata-phy@84000 { @@ -378,7 +378,7 @@ clocks = <&gate_clk 15>; clock-names = "sata"; #phy-cells = <0>; - status = "ok"; + status = "okay"; }; audio0: audio-controller@a0000 { From 6ac30b5c9956ff03fe8eed0a0ea5430426c99b89 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 16 Sep 2020 17:57:13 +0200 Subject: [PATCH 602/799] ARM: dts: dove: fix PCA95xx GPIO expander properties on A510 The PCA95xx GPIO expander requires GPIO controller properties to operate properly. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Linus Walleij Signed-off-by: Gregory CLEMENT --- arch/arm/boot/dts/dove-sbc-a510.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/dove-sbc-a510.dts b/arch/arm/boot/dts/dove-sbc-a510.dts index 2bb85a9b7614..df021f9b0117 100644 --- a/arch/arm/boot/dts/dove-sbc-a510.dts +++ b/arch/arm/boot/dts/dove-sbc-a510.dts @@ -143,6 +143,7 @@ gpio_ext: gpio@20 { compatible = "nxp,pca9555"; reg = <0x20>; + gpio-controller; #gpio-cells = <2>; }; }; From 493c6469a6dd911654f04a656ce2d91021e1e915 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 16 Sep 2020 17:57:14 +0200 Subject: [PATCH 603/799] ARM: dts: armada: align GPIO hog names with dtschema The convention for node names is to use hyphens, not underscores. dtschema for pca95xx expects GPIO hogs to end with 'hog' prefix. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Gregory CLEMENT --- arch/arm/boot/dts/armada-388-clearfog.dts | 4 ++-- arch/arm/boot/dts/armada-388-clearfog.dtsi | 10 +++++----- arch/arm/boot/dts/armada-388-helios4.dts | 6 +++--- 3 files changed, 10 insertions(+), 10 deletions(-) diff --git a/arch/arm/boot/dts/armada-388-clearfog.dts b/arch/arm/boot/dts/armada-388-clearfog.dts index 20f8d4667753..4140a5303b48 100644 --- a/arch/arm/boot/dts/armada-388-clearfog.dts +++ b/arch/arm/boot/dts/armada-388-clearfog.dts @@ -73,13 +73,13 @@ * 14-SFP_TX_DISABLE * 15-SFP_MOD_DEF0 */ - pcie2_0_clkreq { + pcie2-0-clkreq-hog { gpio-hog; gpios = <4 GPIO_ACTIVE_LOW>; input; line-name = "pcie2.0-clkreq"; }; - pcie2_0_w_disable { + pcie2-0-w-disable-hog { gpio-hog; gpios = <7 GPIO_ACTIVE_LOW>; output-low; diff --git a/arch/arm/boot/dts/armada-388-clearfog.dtsi b/arch/arm/boot/dts/armada-388-clearfog.dtsi index a0aa1d188f0c..f8a06ae4a3c9 100644 --- a/arch/arm/boot/dts/armada-388-clearfog.dtsi +++ b/arch/arm/boot/dts/armada-388-clearfog.dtsi @@ -141,31 +141,31 @@ #gpio-cells = <2>; reg = <0x20>; - pcie1_0_clkreq { + pcie1-0-clkreq-hog { gpio-hog; gpios = <0 GPIO_ACTIVE_LOW>; input; line-name = "pcie1.0-clkreq"; }; - pcie1_0_w_disable { + pcie1-0-w-disable-hog { gpio-hog; gpios = <3 GPIO_ACTIVE_LOW>; output-low; line-name = "pcie1.0-w-disable"; }; - usb3_ilimit { + usb3-ilimit-hog { gpio-hog; gpios = <5 GPIO_ACTIVE_LOW>; input; line-name = "usb3-current-limit"; }; - usb3_power { + usb3-power-hog { gpio-hog; gpios = <6 GPIO_ACTIVE_HIGH>; output-high; line-name = "usb3-power"; }; - m2_devslp { + m2-devslp-hog { gpio-hog; gpios = <11 GPIO_ACTIVE_HIGH>; output-low; diff --git a/arch/arm/boot/dts/armada-388-helios4.dts b/arch/arm/boot/dts/armada-388-helios4.dts index fb49df2a3bce..b3728de3bd3f 100644 --- a/arch/arm/boot/dts/armada-388-helios4.dts +++ b/arch/arm/boot/dts/armada-388-helios4.dts @@ -166,19 +166,19 @@ interrupt-controller; #interrupt-cells = <2>; - board_rev_bit_0 { + board-rev-bit-0-hog { gpio-hog; gpios = <0 GPIO_ACTIVE_LOW>; input; line-name = "board-rev-0"; }; - board_rev_bit_1 { + board-rev-bit-1-hog { gpio-hog; gpios = <1 GPIO_ACTIVE_LOW>; input; line-name = "board-rev-1"; }; - usb3_ilimit { + usb3-ilimit-hog { gpio-hog; gpios = <5 GPIO_ACTIVE_HIGH>; input; From 7f24479ead579459106bb55c2320a000135731f9 Mon Sep 17 00:00:00 2001 From: Chris Packham Date: Tue, 8 Sep 2020 09:17:11 +1200 Subject: [PATCH 604/799] ARM: dts: Remove non-existent i2c1 from 98dx3236 The switches with integrated CPUs have only got a single i2c controller. They incorrectly gained one when they were split from the Armada-XP. Fixes: 43e28ba87708 ("ARM: dts: Use armada-370-xp as a base for armada-xp-98dx3236") Signed-off-by: Chris Packham Reviewed-by: Andrew Lunn Signed-off-by: Gregory CLEMENT --- arch/arm/boot/dts/armada-xp-98dx3236.dtsi | 5 ----- 1 file changed, 5 deletions(-) diff --git a/arch/arm/boot/dts/armada-xp-98dx3236.dtsi b/arch/arm/boot/dts/armada-xp-98dx3236.dtsi index 654648b05c7c..aeccedd12574 100644 --- a/arch/arm/boot/dts/armada-xp-98dx3236.dtsi +++ b/arch/arm/boot/dts/armada-xp-98dx3236.dtsi @@ -266,11 +266,6 @@ reg = <0x11000 0x100>; }; -&i2c1 { - compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c"; - reg = <0x11100 0x100>; -}; - &mpic { reg = <0x20a00 0x2d0>, <0x21070 0x58>; }; From 44144cc948013a66e3f17269a23653a3d803264a Mon Sep 17 00:00:00 2001 From: Chris Packham Date: Tue, 8 Sep 2020 09:17:12 +1200 Subject: [PATCH 605/799] ARM: dts: Add i2c0 pinctrl information for 98dx3236 Add pinctrl information for the 98dx3236 (and variants). There is only one choice for i2c0 MPP14 and MPP15. Signed-off-by: Chris Packham Reviewed-by: Andrew Lunn Signed-off-by: Gregory CLEMENT --- arch/arm/boot/dts/armada-xp-98dx3236.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/boot/dts/armada-xp-98dx3236.dtsi b/arch/arm/boot/dts/armada-xp-98dx3236.dtsi index aeccedd12574..38a052a0312d 100644 --- a/arch/arm/boot/dts/armada-xp-98dx3236.dtsi +++ b/arch/arm/boot/dts/armada-xp-98dx3236.dtsi @@ -264,6 +264,8 @@ &i2c0 { compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c"; reg = <0x11000 0x100>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; }; &mpic { @@ -319,6 +321,11 @@ "mpp2", "mpp3"; marvell,function = "spi0"; }; + + i2c0_pins: i2c-pins-0 { + marvell,pins = "mpp14", "mpp15"; + marvell,function = "i2c0"; + }; }; &spi0 { From 8077f593d77cf53b0e0ee467b2de2f9e781ab437 Mon Sep 17 00:00:00 2001 From: Andre Heider Date: Tue, 8 Sep 2020 09:30:50 +0200 Subject: [PATCH 606/799] arm64: dts: marvell: espressobin: Simplify v7 ethernet port labeling MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Now that the switch ports have a label in the .dtsi, simplify the whole "switch0" block for the v7 dts files. Signed-off-by: Andre Heider Reviewed-by: Pali Rohár Reviewed-by: Andrew Lunn Signed-off-by: Gregory CLEMENT --- .../armada-3720-espressobin-v7-emmc.dts | 18 +++++------------ .../marvell/armada-3720-espressobin-v7.dts | 20 ++++++------------- 2 files changed, 11 insertions(+), 27 deletions(-) diff --git a/arch/arm64/boot/dts/marvell/armada-3720-espressobin-v7-emmc.dts b/arch/arm64/boot/dts/marvell/armada-3720-espressobin-v7-emmc.dts index 215d2f702623..61d49d6a2a2a 100644 --- a/arch/arm64/boot/dts/marvell/armada-3720-espressobin-v7-emmc.dts +++ b/arch/arm64/boot/dts/marvell/armada-3720-espressobin-v7-emmc.dts @@ -28,20 +28,12 @@ }; }; -&switch0 { - ports { - switch0port1: port@1 { - reg = <1>; - label = "lan1"; - phy-handle = <&switch0phy0>; - }; +&switch0port1 { + label = "lan1"; +}; - switch0port3: port@3 { - reg = <3>; - label = "wan"; - phy-handle = <&switch0phy2>; - }; - }; +&switch0port3 { + label = "wan"; }; /* U11 */ diff --git a/arch/arm64/boot/dts/marvell/armada-3720-espressobin-v7.dts b/arch/arm64/boot/dts/marvell/armada-3720-espressobin-v7.dts index b6f4af8ebafb..44dbe9a21cc7 100644 --- a/arch/arm64/boot/dts/marvell/armada-3720-espressobin-v7.dts +++ b/arch/arm64/boot/dts/marvell/armada-3720-espressobin-v7.dts @@ -27,18 +27,10 @@ }; }; -&switch0 { - ports { - switch0port1: port@1 { - reg = <1>; - label = "lan1"; - phy-handle = <&switch0phy0>; - }; - - switch0port3: port@3 { - reg = <3>; - label = "wan"; - phy-handle = <&switch0phy2>; - }; - }; +&switch0port1 { + label = "lan1"; +}; + +&switch0port3 { + label = "wan"; }; From d77998497783cab316acde46add4ee4cc70fb76f Mon Sep 17 00:00:00 2001 From: Andre Heider Date: Tue, 22 Sep 2020 06:31:41 +0200 Subject: [PATCH 607/799] arm64: dts: marvell: espressobin: Get rid of duplicate serial aliases MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The included armada-37xx.dtsi already defines these two aliases. Signed-off-by: Andre Heider Reviewed-by: Pali Rohár Signed-off-by: Gregory CLEMENT --- arch/arm64/boot/dts/marvell/armada-3720-espressobin.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dtsi b/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dtsi index 0775c16e0ec8..3169a820558f 100644 --- a/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dtsi @@ -17,8 +17,6 @@ ethernet1 = &switch0port1; ethernet2 = &switch0port2; ethernet3 = &switch0port3; - serial0 = &uart0; - serial1 = &uart1; }; chosen { From f9559f029ebe05a87e9689f4aa444e19cc7426e4 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Fri, 25 Sep 2020 10:50:43 +0200 Subject: [PATCH 608/799] arm64: dts: marvell: espressobin: De-duplicate eMMC definitions MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit eMMC definitions in files armada-3720-espressobin-emmc.dts and armada-3720-espressobin-v7-emmc.dts is same. So move it into common armada-3720-espressobin.dtsi file with status "disabled". This change simplifies eMMC variants of DTS files for Espressobin. Signed-off-by: Pali Rohár Reviewed-by: Andre Heider Tested-by: Andre Heider Signed-off-by: Gregory CLEMENT --- .../marvell/armada-3720-espressobin-emmc.dts | 18 -------------- .../armada-3720-espressobin-v7-emmc.dts | 18 -------------- .../dts/marvell/armada-3720-espressobin.dtsi | 24 +++++++++++++++++++ 3 files changed, 24 insertions(+), 36 deletions(-) diff --git a/arch/arm64/boot/dts/marvell/armada-3720-espressobin-emmc.dts b/arch/arm64/boot/dts/marvell/armada-3720-espressobin-emmc.dts index ec72a11ed80f..5c4d8f379704 100644 --- a/arch/arm64/boot/dts/marvell/armada-3720-espressobin-emmc.dts +++ b/arch/arm64/boot/dts/marvell/armada-3720-espressobin-emmc.dts @@ -21,24 +21,6 @@ "marvell,armada3720", "marvell,armada3710"; }; -/* U11 */ &sdhci0 { - non-removable; - bus-width = <8>; - mmc-ddr-1_8v; - mmc-hs400-1_8v; - marvell,xenon-emmc; - marvell,xenon-tun-count = <9>; - marvell,pad-type = "fixed-1-8v"; - - pinctrl-names = "default"; - pinctrl-0 = <&mmc_pins>; status = "okay"; - - #address-cells = <1>; - #size-cells = <0>; - mmccard: mmccard@0 { - compatible = "mmc-card"; - reg = <0>; - }; }; diff --git a/arch/arm64/boot/dts/marvell/armada-3720-espressobin-v7-emmc.dts b/arch/arm64/boot/dts/marvell/armada-3720-espressobin-v7-emmc.dts index 61d49d6a2a2a..e225dce64b9e 100644 --- a/arch/arm64/boot/dts/marvell/armada-3720-espressobin-v7-emmc.dts +++ b/arch/arm64/boot/dts/marvell/armada-3720-espressobin-v7-emmc.dts @@ -36,24 +36,6 @@ label = "wan"; }; -/* U11 */ &sdhci0 { - non-removable; - bus-width = <8>; - mmc-ddr-1_8v; - mmc-hs400-1_8v; - marvell,xenon-emmc; - marvell,xenon-tun-count = <9>; - marvell,pad-type = "fixed-1-8v"; - - pinctrl-names = "default"; - pinctrl-0 = <&mmc_pins>; status = "okay"; - - #address-cells = <1>; - #size-cells = <0>; - mmccard: mmccard@0 { - compatible = "mmc-card"; - reg = <0>; - }; }; diff --git a/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dtsi b/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dtsi index 3169a820558f..8a1c678bea5f 100644 --- a/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dtsi @@ -58,6 +58,30 @@ phy-names = "sata-phy"; }; +/* U11 */ +&sdhci0 { + /* Main DTS file for Espressobin is without eMMC */ + status = "disabled"; + + non-removable; + bus-width = <8>; + mmc-ddr-1_8v; + mmc-hs400-1_8v; + marvell,xenon-emmc; + marvell,xenon-tun-count = <9>; + marvell,pad-type = "fixed-1-8v"; + + pinctrl-names = "default"; + pinctrl-0 = <&mmc_pins>; + + #address-cells = <1>; + #size-cells = <0>; + mmccard: mmccard@0 { + compatible = "mmc-card"; + reg = <0>; + }; +}; + /* J1 */ &sdhci1 { wp-inverted; From 8c4e256e3d425e73e02b6e9fa18c0aa3425970d7 Mon Sep 17 00:00:00 2001 From: Luka Kovacic Date: Fri, 24 Jul 2020 12:38:40 +0200 Subject: [PATCH 609/799] MAINTAINERS: Add an entry for MikroTik CRS3xx 98DX3236 boards An entry is added for MikroTik CRS3xx 98DX3236 based switches. Signed-off-by: Luka Kovacic Cc: Luka Perkov Cc: Jakov Petrina Reviewed-by: Andrew Lunn Signed-off-by: Gregory CLEMENT --- MAINTAINERS | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index e73636b75f29..28e88b32180e 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -11661,6 +11661,17 @@ M: Oliver Neukum S: Maintained F: drivers/usb/image/microtek.* +MIKROTIK CRS3XX 98DX3236 BOARD SUPPORT +M: Luka Kovacic +M: Luka Perkov +S: Maintained +F: arch/arm/boot/dts/armada-xp-crs305-1g-4s-bit.dts +F: arch/arm/boot/dts/armada-xp-crs305-1g-4s.dts +F: arch/arm/boot/dts/armada-xp-crs326-24g-2s-bit.dts +F: arch/arm/boot/dts/armada-xp-crs326-24g-2s.dts +F: arch/arm/boot/dts/armada-xp-crs328-4c-20s-4s-bit.dts +F: arch/arm/boot/dts/armada-xp-crs328-4c-20s-4s.dts + MIPS M: Thomas Bogendoerfer L: linux-mips@vger.kernel.org From d7ce8739f50e9e8c55a3c7651ebfbca57199553f Mon Sep 17 00:00:00 2001 From: Gregory CLEMENT Date: Wed, 23 Sep 2020 15:59:18 +0200 Subject: [PATCH 610/799] MAINTAINERS: switch mvebu tree to kernel.org We have switched mvebu tree to kernel.org now, so update in MAINTAINERS file Reviewed-by: Andrew Lunn Signed-off-by: Gregory CLEMENT --- MAINTAINERS | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index 28e88b32180e..e9e4655e8c99 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2018,7 +2018,7 @@ M: Sebastian Hesselbarth M: Gregory Clement L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained -T: git git://git.infradead.org/linux-mvebu.git +T: git git://git.kernel.org/pub/scm/linux/kernel/git/gclement/mvebu.git F: Documentation/devicetree/bindings/soc/dove/ F: arch/arm/boot/dts/dove* F: arch/arm/boot/dts/orion5x* @@ -2035,7 +2035,7 @@ M: Gregory Clement M: Sebastian Hesselbarth L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained -T: git git://git.infradead.org/linux-mvebu.git +T: git git://git.kernel.org/pub/scm/linux/kernel/git/gclement/mvebu.git F: arch/arm/boot/dts/armada* F: arch/arm/boot/dts/kirkwood* F: arch/arm/configs/mvebu_*_defconfig From 6d96e11b777129d709096744e125bd866ff8b5a1 Mon Sep 17 00:00:00 2001 From: Luka Kovacic Date: Sun, 25 Oct 2020 02:13:51 +0100 Subject: [PATCH 611/799] arm64: dts: marvell: Add a device tree for the IEI Puzzle-M801 board Add initial support for the IEI Puzzle-M801 1U Rackmount Network Appliance board. The board is based on the quad-core Marvell Armada 8040 SoC and supports up to 16 GB of DDR4 2400 MHz ECC RAM. It has a PCIe x16 slot (x2 lanes only) and an M.2 type B slot. Main system hardware: 2x USB 3.0 4x Gigabit Ethernet 2x SFP+ 1x SATA 3.0 1x M.2 type B 1x RJ45 UART 1x SPI flash 1x IEI WT61P803 PUZZLE Microcontroller 1x EPSON RX8010 RTC (used instead of the integrated Marvell RTC controller) 6x SFP+ LED 1x HDD LED All of the hardware listed above is supported and tested in this port. Signed-off-by: Luka Kovacic Acked-by: Andrew Lunn Cc: Luka Perkov Cc: Robert Marko Signed-off-by: Gregory CLEMENT --- arch/arm64/boot/dts/marvell/Makefile | 1 + .../dts/marvell/armada-8040-puzzle-m801.dts | 523 ++++++++++++++++++ 2 files changed, 524 insertions(+) create mode 100644 arch/arm64/boot/dts/marvell/armada-8040-puzzle-m801.dts diff --git a/arch/arm64/boot/dts/marvell/Makefile b/arch/arm64/boot/dts/marvell/Makefile index 3e5f2e7a040c..e413c3261792 100644 --- a/arch/arm64/boot/dts/marvell/Makefile +++ b/arch/arm64/boot/dts/marvell/Makefile @@ -12,6 +12,7 @@ dtb-$(CONFIG_ARCH_MVEBU) += armada-8040-clearfog-gt-8k.dtb dtb-$(CONFIG_ARCH_MVEBU) += armada-8040-db.dtb dtb-$(CONFIG_ARCH_MVEBU) += armada-8040-mcbin.dtb dtb-$(CONFIG_ARCH_MVEBU) += armada-8040-mcbin-singleshot.dtb +dtb-$(CONFIG_ARCH_MVEBU) += armada-8040-puzzle-m801.dtb dtb-$(CONFIG_ARCH_MVEBU) += armada-8080-db.dtb dtb-$(CONFIG_ARCH_MVEBU) += cn9130-db.dtb dtb-$(CONFIG_ARCH_MVEBU) += cn9131-db.dtb diff --git a/arch/arm64/boot/dts/marvell/armada-8040-puzzle-m801.dts b/arch/arm64/boot/dts/marvell/armada-8040-puzzle-m801.dts new file mode 100644 index 000000000000..dac85fa748de --- /dev/null +++ b/arch/arm64/boot/dts/marvell/armada-8040-puzzle-m801.dts @@ -0,0 +1,523 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2016 Marvell Technology Group Ltd. + * Copyright (C) 2020 Sartura Ltd. + * + * Device Tree file for IEI Puzzle-M801 + */ + +#include "armada-8040.dtsi" + +#include +#include + +/ { + model = "IEI-Puzzle-M801"; + compatible = "marvell,armada8040", "marvell,armada-ap806-quad", "marvell,armada-ap806"; + + aliases { + ethernet0 = &cp0_eth0; + ethernet1 = &cp1_eth0; + ethernet2 = &cp0_eth1; + ethernet3 = &cp0_eth2; + ethernet4 = &cp1_eth1; + ethernet5 = &cp1_eth2; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x80000000>; + }; + + /* Regulator labels correspond with schematics */ + v_3_3: regulator-3-3v { + compatible = "regulator-fixed"; + regulator-name = "v_3_3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + status = "okay"; + }; + + v_5v0_usb3_hst_vbus: regulator-usb3-vbus0 { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&cp0_gpio2 15 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&cp0_xhci_vbus_pins>; + regulator-name = "v_5v0_usb3_hst_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + status = "okay"; + }; + + v_vddo_h: regulator-1-8v { + compatible = "regulator-fixed"; + regulator-name = "v_vddo_h"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + status = "okay"; + }; + + sfp_cp0_eth0: sfp-cp0-eth0 { + compatible = "sff,sfp"; + i2c-bus = <&sfpplus0_i2c>; + los-gpio = <&sfpplus_gpio 11 GPIO_ACTIVE_HIGH>; + mod-def0-gpio = <&sfpplus_gpio 10 GPIO_ACTIVE_LOW>; + tx-disable-gpio = <&sfpplus_gpio 9 GPIO_ACTIVE_HIGH>; + tx-fault-gpio = <&sfpplus_gpio 8 GPIO_ACTIVE_HIGH>; + maximum-power-milliwatt = <3000>; + }; + + sfp_cp1_eth0: sfp-cp1-eth0 { + compatible = "sff,sfp"; + i2c-bus = <&sfpplus1_i2c>; + los-gpio = <&sfpplus_gpio 3 GPIO_ACTIVE_HIGH>; + mod-def0-gpio = <&sfpplus_gpio 2 GPIO_ACTIVE_LOW>; + tx-disable-gpio = <&sfpplus_gpio 1 GPIO_ACTIVE_HIGH>; + tx-fault-gpio = <&sfpplus_gpio 0 GPIO_ACTIVE_HIGH>; + maximum-power-milliwatt = <3000>; + }; + + leds { + compatible = "gpio-leds"; + status = "okay"; + pinctrl-0 = <&cp0_sfpplus_led_pins &cp1_sfpplus_led_pins>; + pinctrl-names = "default"; + + led-0 { + /* SFP+ port 2: Activity */ + function = LED_FUNCTION_LAN; + function-enumerator = <0>; + gpios = <&cp1_gpio1 6 GPIO_ACTIVE_LOW>; + }; + + led-1 { + /* SFP+ port 1: Activity */ + function = LED_FUNCTION_LAN; + function-enumerator = <1>; + gpios = <&cp1_gpio1 14 GPIO_ACTIVE_LOW>; + }; + + led-2 { + /* SFP+ port 2: 10 Gbps indicator */ + function = LED_FUNCTION_LAN; + function-enumerator = <2>; + gpios = <&cp1_gpio1 7 GPIO_ACTIVE_LOW>; + }; + + led-3 { + /* SFP+ port 2: 1 Gbps indicator */ + function = LED_FUNCTION_LAN; + function-enumerator = <3>; + gpios = <&cp1_gpio1 8 GPIO_ACTIVE_LOW>; + }; + + led-4 { + /* SFP+ port 1: 10 Gbps indicator */ + function = LED_FUNCTION_LAN; + function-enumerator = <4>; + gpios = <&cp1_gpio1 10 GPIO_ACTIVE_LOW>; + }; + + led-5 { + /* SFP+ port 1: 1 Gbps indicator */ + function = LED_FUNCTION_LAN; + function-enumerator = <5>; + gpios = <&cp1_gpio1 31 GPIO_ACTIVE_LOW>; + }; + + led-6 { + function = LED_FUNCTION_DISK; + linux,default-trigger = "disk-activity"; + gpios = <&cp0_gpio2 22 GPIO_ACTIVE_HIGH>; + }; + + }; +}; + +&ap_sdhci0 { + bus-width = <8>; + /* + * Not stable in HS modes - phy needs "more calibration", so add + * the "slow-mode" and disable SDR104, SDR50 and DDR50 modes. + */ + marvell,xenon-phy-slow-mode; + no-1-8-v; + no-sd; + no-sdio; + non-removable; + status = "okay"; + vqmmc-supply = <&v_vddo_h>; +}; + +&ap_thermal_cpu1 { + trips { + cpu_active: cpu-active { + temperature = <44000>; + hysteresis = <2000>; + type = "active"; + }; + }; + cooling-maps { + fan-map { + trip = <&cpu_active>; + cooling-device = <&chassis_fan_group0 64 THERMAL_NO_LIMIT>, + <&chassis_fan_group1 64 THERMAL_NO_LIMIT>; + }; + }; +}; + +&i2c0 { + clock-frequency = <100000>; + status = "okay"; + + rtc@32 { + compatible = "epson,rx8010"; + reg = <0x32>; + }; +}; + +&spi0 { + status = "okay"; + spi-flash@0 { + #address-cells = <0x1>; + #size-cells = <0x1>; + compatible = "jedec,spi-nor"; + reg = <0x0>; + spi-max-frequency = <20000000>; + partition@u-boot { + label = "u-boot"; + reg = <0x00000000 0x001f0000>; + }; + partition@u-boot-env { + label = "u-boot-env"; + reg = <0x001f0000 0x00010000>; + }; + partition@ubi1 { + label = "ubi1"; + reg = <0x00200000 0x03f00000>; + }; + partition@ubi2 { + label = "ubi2"; + reg = <0x04100000 0x03f00000>; + }; + }; +}; + +&uart0 { + status = "okay"; + pinctrl-0 = <&uart0_pins>; + pinctrl-names = "default"; +}; + +&uart1 { + status = "okay"; + /* IEI WT61P803 PUZZLE MCU Controller */ + mcu { + compatible = "iei,wt61p803-puzzle"; + current-speed = <115200>; + enable-beep; + + leds { + compatible = "iei,wt61p803-puzzle-leds"; + #address-cells = <1>; + #size-cells = <0>; + + led@0 { + reg = <0>; + function = LED_FUNCTION_POWER; + color = ; + }; + }; + + hwmon { + compatible = "iei,wt61p803-puzzle-hwmon"; + #address-cells = <1>; + #size-cells = <0>; + + chassis_fan_group0:fan-group@0 { + #cooling-cells = <2>; + reg = <0x00>; + cooling-levels = <64 102 170 230 250>; + }; + + chassis_fan_group1:fan-group@1 { + #cooling-cells = <2>; + reg = <0x01>; + cooling-levels = <64 102 170 230 250>; + }; + }; + }; +}; + +&cp0_rtc { + status = "disabled"; +}; + +&cp0_i2c0 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&cp0_i2c0_pins>; + status = "okay"; + + sfpplus_gpio: gpio@21 { + compatible = "nxp,pca9555"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + }; + + eeprom@54 { + compatible = "atmel,24c04"; + reg = <0x54>; + }; +}; + +&cp0_i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&cp0_i2c1_pins>; + status = "okay"; + + i2c-switch@70 { + compatible = "nxp,pca9544"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x70>; + + sfpplus0_i2c: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + sfpplus1_i2c: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + }; +}; + +&cp0_uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&cp0_uart1_pins>; + status = "okay"; +}; + +&cp0_mdio { + #address-cells = <1>; + #size-cells = <0>; + + status = "okay"; + + ge_phy2: ethernet-phy@0 { + reg = <0>; + }; + + ge_phy3: ethernet-phy@1 { + reg = <1>; + }; +}; + +&cp0_pcie0 { + pinctrl-names = "default"; + pinctrl-0 = <&cp0_pcie_pins>; + num-lanes = <1>; + num-viewport = <8>; + reset-gpios = <&cp0_gpio2 20 GPIO_ACTIVE_LOW>; + ranges = <0x82000000 0x0 0xc0000000 0x0 0xc0000000 0x0 0x20000000>; + phys = <&cp0_comphy0 0>; + phy-names = "cp0-pcie0-x1-phy"; + status = "okay"; +}; + +&cp0_pinctrl { + cp0_ge_mdio_pins: ge-mdio-pins { + marvell,pins = "mpp32", "mpp34"; + marvell,function = "ge"; + }; + cp0_i2c1_pins: i2c1-pins { + marvell,pins = "mpp35", "mpp36"; + marvell,function = "i2c1"; + }; + cp0_i2c0_pins: i2c0-pins { + marvell,pins = "mpp37", "mpp38"; + marvell,function = "i2c0"; + }; + cp0_uart1_pins: uart1-pins { + marvell,pins = "mpp40", "mpp41"; + marvell,function = "uart1"; + }; + cp0_xhci_vbus_pins: xhci0-vbus-pins { + marvell,pins = "mpp47"; + marvell,function = "gpio"; + }; + cp0_pcie_pins: pcie-pins { + marvell,pins = "mpp52"; + marvell,function = "gpio"; + }; + cp0_sdhci_pins: sdhci-pins { + marvell,pins = "mpp55", "mpp56", "mpp57", "mpp58", "mpp59", + "mpp60", "mpp61"; + marvell,function = "sdio"; + }; + cp0_sfpplus_led_pins: sfpplus-led-pins { + marvell,pins = "mpp54"; + marvell,function = "gpio"; + }; +}; + +&cp0_ethernet { + status = "okay"; +}; + +&cp0_eth0 { + status = "okay"; + phy-mode = "10gbase-r"; + phys = <&cp0_comphy4 0>; + local-mac-address = [ae 00 00 00 ff 00]; + sfp = <&sfp_cp0_eth0>; + managed = "in-band-status"; +}; + +&cp0_eth1 { + status = "okay"; + phy = <&ge_phy2>; + phy-mode = "sgmii"; + local-mac-address = [ae 00 00 00 ff 01]; + phys = <&cp0_comphy3 1>; +}; + +&cp0_eth2 { + status = "okay"; + phy-mode = "sgmii"; + phys = <&cp0_comphy1 2>; + local-mac-address = [ae 00 00 00 ff 02]; + phy = <&ge_phy3>; +}; + +&cp0_sata0 { + status = "okay"; + + sata-port@0 { + phys = <&cp0_comphy2 0>; + phy-names = "cp0-sata0-0-phy"; + }; + + sata-port@1 { + phys = <&cp0_comphy5 1>; + phy-names = "cp0-sata0-1-phy"; + }; +}; + +&cp0_sdhci0 { + broken-cd; + bus-width = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&cp0_sdhci_pins>; + status = "okay"; + vqmmc-supply = <&v_3_3>; +}; + +&cp0_usb3_0 { + status = "okay"; +}; + +&cp0_usb3_1 { + status = "okay"; +}; + +&cp1_i2c0 { + clock-frequency = <100000>; + status = "disabled"; +}; + +&cp1_i2c1 { + clock-frequency = <100000>; + status = "disabled"; +}; + +&cp1_rtc { + status = "disabled"; +}; + +&cp1_ethernet { + status = "okay"; +}; + +&cp1_eth0 { + status = "okay"; + phy-mode = "10gbase-r"; + phys = <&cp1_comphy4 0>; + local-mac-address = [ae 00 00 00 ff 03]; + sfp = <&sfp_cp1_eth0>; + managed = "in-band-status"; +}; + +&cp1_eth1 { + status = "okay"; + phy = <&ge_phy4>; + phy-mode = "sgmii"; + local-mac-address = [ae 00 00 00 ff 04]; + phys = <&cp1_comphy3 1>; +}; + +&cp1_eth2 { + status = "okay"; + phy-mode = "sgmii"; + local-mac-address = [ae 00 00 00 ff 05]; + phys = <&cp1_comphy5 2>; + phy = <&ge_phy5>; +}; + +&cp1_pinctrl { + cp1_sfpplus_led_pins: sfpplus-led-pins { + marvell,pins = "mpp6", "mpp7", "mpp8", "mpp10", "mpp14", "mpp31"; + marvell,function = "gpio"; + }; +}; + +&cp1_uart0 { + status = "disabled"; +}; + +&cp1_comphy2 { + cp1_usbh0_con: connector { + compatible = "usb-a-connector"; + phy-supply = <&v_5v0_usb3_hst_vbus>; + }; +}; + +&cp1_usb3_0 { + phys = <&cp1_comphy2 0>; + phy-names = "cp1-usb3h0-comphy"; + status = "okay"; +}; + +&cp1_mdio { + #address-cells = <1>; + #size-cells = <0>; + + status = "okay"; + + ge_phy4: ethernet-phy@1 { + reg = <1>; + }; + ge_phy5: ethernet-phy@0 { + reg = <0>; + }; +}; + +&cp1_pcie0 { + num-lanes = <2>; + phys = <&cp1_comphy0 0>, <&cp1_comphy1 0>; + phy-names = "cp1-pcie0-x2-lane0-phy", "cp1-pcie0-x2-lane1-phy"; + status = "okay"; +}; From c1e9911fcc54afb2ccfe8bab213ec6679c455675 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Tue, 6 Oct 2020 14:44:55 +0200 Subject: [PATCH 612/799] arm64: dts: marvell: espressobin: Add support for LED2 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit LED2 is connected to MPP1_2 pin. It is working only on V7 boards. V5 boards have hw bug which cause that LED2 is non-working. So enable LED2 only for Espressobin V7 boards. Note that LED1 is connected to LED_WLAN# pin on miniPCIe card and LED3 to power supply. Therefore on Espressobin board only LED2 can be controlled directly from the host. LED1 is possible to control via WiFi card inserted in miniPCIe slot if driver for particular card supports it. Signed-off-by: Pali Rohár Tested-by: Gérald Kerma Signed-off-by: Gregory CLEMENT --- .../dts/marvell/armada-3720-espressobin-v7-emmc.dts | 4 ++++ .../boot/dts/marvell/armada-3720-espressobin-v7.dts | 4 ++++ .../boot/dts/marvell/armada-3720-espressobin.dtsi | 13 +++++++++++++ 3 files changed, 21 insertions(+) diff --git a/arch/arm64/boot/dts/marvell/armada-3720-espressobin-v7-emmc.dts b/arch/arm64/boot/dts/marvell/armada-3720-espressobin-v7-emmc.dts index e225dce64b9e..58b94db5f652 100644 --- a/arch/arm64/boot/dts/marvell/armada-3720-espressobin-v7-emmc.dts +++ b/arch/arm64/boot/dts/marvell/armada-3720-espressobin-v7-emmc.dts @@ -39,3 +39,7 @@ &sdhci0 { status = "okay"; }; + +&led2 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/marvell/armada-3720-espressobin-v7.dts b/arch/arm64/boot/dts/marvell/armada-3720-espressobin-v7.dts index 44dbe9a21cc7..b22ae550a45b 100644 --- a/arch/arm64/boot/dts/marvell/armada-3720-espressobin-v7.dts +++ b/arch/arm64/boot/dts/marvell/armada-3720-espressobin-v7.dts @@ -34,3 +34,7 @@ &switch0port3 { label = "wan"; }; + +&led2 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dtsi b/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dtsi index 8a1c678bea5f..daffe136c523 100644 --- a/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dtsi @@ -41,6 +41,19 @@ 3300000 0x0>; enable-active-high; }; + + led2: gpio-led2 { + /* led2 is working only on v7 board */ + status = "disabled"; + + compatible = "gpio-leds"; + + led2 { + label = "led2"; + gpios = <&gpionb 2 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + }; }; /* J9 */ From 3404fe15a60fe790799d6e1dd5de51997f338cc6 Mon Sep 17 00:00:00 2001 From: Vladimir Vid Date: Mon, 26 Oct 2020 19:44:42 +0100 Subject: [PATCH 613/799] arm64: dts: marvell: add DT for ESPRESSObin-Ultra This adds support for ESPRESSObin-Ultra from Globalscale. Specifications are similar to the base ESPRESSObin board, with main difference being being WAN port with PoE capability and 2 additional ethernet ports. Full specifications: 1x Marvell 64 bit Dual Core ARM A53 Armada 3700 SOC clocked up to 1.2Ghz 1x Topaz 6341 Networking Switch 1GB DDR4 8GB eMMC 1x WAN with 30W POE 4x Gb LAN 1x RTC Clock and battery 1x DC Jack 1x USB 3.0 Type A 1x USB 2.0 Type A 1x SIM NanoSIM card Slot 1x Power Button 4x LED 1x Reset button 1x microUSB for UART 1x M.2 2280 slot for memory 1x 2x2 802.11ac Wi-Fi 1x MiniPCIE slot for Wi-Fi (PCIe interface) Signed-off-by: Vladimir Vid Signed-off-by: Gregory CLEMENT --- arch/arm64/boot/dts/marvell/Makefile | 1 + .../marvell/armada-3720-espressobin-ultra.dts | 165 ++++++++++++++++++ 2 files changed, 166 insertions(+) create mode 100644 arch/arm64/boot/dts/marvell/armada-3720-espressobin-ultra.dts diff --git a/arch/arm64/boot/dts/marvell/Makefile b/arch/arm64/boot/dts/marvell/Makefile index e413c3261792..34efe0fb6f37 100644 --- a/arch/arm64/boot/dts/marvell/Makefile +++ b/arch/arm64/boot/dts/marvell/Makefile @@ -3,6 +3,7 @@ dtb-$(CONFIG_ARCH_MVEBU) += armada-3720-db.dtb dtb-$(CONFIG_ARCH_MVEBU) += armada-3720-espressobin.dtb dtb-$(CONFIG_ARCH_MVEBU) += armada-3720-espressobin-emmc.dtb +dtb-$(CONFIG_ARCH_MVEBU) += armada-3720-espressobin-ultra.dtb dtb-$(CONFIG_ARCH_MVEBU) += armada-3720-espressobin-v7.dtb dtb-$(CONFIG_ARCH_MVEBU) += armada-3720-espressobin-v7-emmc.dtb dtb-$(CONFIG_ARCH_MVEBU) += armada-3720-turris-mox.dtb diff --git a/arch/arm64/boot/dts/marvell/armada-3720-espressobin-ultra.dts b/arch/arm64/boot/dts/marvell/armada-3720-espressobin-ultra.dts new file mode 100644 index 000000000000..c5eb3604dd5b --- /dev/null +++ b/arch/arm64/boot/dts/marvell/armada-3720-espressobin-ultra.dts @@ -0,0 +1,165 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree file for ESPRESSObin-Ultra board. + * Copyright (C) 2019 Globalscale technologies, Inc. + * + * Jason Hung + */ + +/dts-v1/; + +#include "armada-3720-espressobin.dtsi" + +/ { + model = "Globalscale Marvell ESPRESSOBin Ultra Board"; + compatible = "globalscale,espressobin-ultra", "marvell,armada3720", + "marvell,armada3710"; + + aliases { + /* ethernet1 is WAN port */ + ethernet1 = &switch0port5; + ethernet2 = &switch0port1; + ethernet3 = &switch0port2; + ethernet4 = &switch0port3; + ethernet5 = &switch0port4; + }; + + reg_usb3_vbus: usb3-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb3-vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpionb 19 GPIO_ACTIVE_HIGH>; + }; + + usb3_phy: usb3-phy { + compatible = "usb-nop-xceiv"; + vcc-supply = <®_usb3_vbus>; + }; + + gpio-leds { + pinctrl-names = "default"; + compatible = "gpio-leds"; + /* No assigned functions to the LEDs by default */ + led1 { + label = "ebin-ultra:blue:led1"; + gpios = <&gpionb 11 GPIO_ACTIVE_LOW>; + }; + led2 { + label = "ebin-ultra:green:led2"; + gpios = <&gpionb 12 GPIO_ACTIVE_LOW>; + }; + led3 { + label = "ebin-ultra:red:led3"; + gpios = <&gpionb 13 GPIO_ACTIVE_LOW>; + }; + led4 { + label = "ebin-ultra:yellow:led4"; + gpios = <&gpionb 14 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&sdhci0 { + status = "okay"; +}; + +&sdhci1 { + status = "disabled"; +}; + +&spi0 { + flash@0 { + spi-max-frequency = <108000000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <4>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "firmware"; + reg = <0x0 0x3e0000>; + }; + partition@3e0000 { + label = "hw-info"; + reg = <0x3e0000 0x10000>; + read-only; + }; + partition@3f0000 { + label = "u-boot-env"; + reg = <0x3f0000 0x10000>; + }; + }; + }; +}; + +&i2c0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; + + clock-frequency = <100000>; + + rtc@51 { + compatible = "nxp,pcf8563"; + reg = <0x51>; + }; +}; + +&usb3 { + usb-phy = <&usb3_phy>; + status = "disabled"; +}; + +&mdio { + extphy: ethernet-phy@1 { + reg = <1>; + }; +}; + +&switch0 { + reg = <3>; + + ports { + switch0port1: port@1 { + reg = <1>; + label = "lan0"; + phy-handle = <&switch0phy0>; + }; + + switch0port2: port@2 { + reg = <2>; + label = "lan1"; + phy-handle = <&switch0phy1>; + }; + + switch0port3: port@3 { + reg = <3>; + label = "lan2"; + phy-handle = <&switch0phy2>; + }; + + switch0port4: port@4 { + reg = <4>; + label = "lan3"; + phy-handle = <&switch0phy3>; + }; + + switch0port5: port@5 { + reg = <5>; + label = "wan"; + phy-handle = <&extphy>; + phy-mode = "sgmii"; + }; + }; + + mdio { + switch0phy3: switch0phy3@14 { + reg = <0x14>; + }; + }; +}; From 53e950d597e3578da84238b86424bfcc9e101d87 Mon Sep 17 00:00:00 2001 From: Sven Auhagen Date: Mon, 9 Nov 2020 18:39:48 +0100 Subject: [PATCH 614/799] arm64: dts: marvell: armada-cp110: Switch to per-port SATA interrupts There are two SATA ports per CP110. Each of them has a dedicated interrupt. Describe the real hardware by adding two SATA ports to the CP110 SATA node. Reviewed-by: Hans de Goede Signed-off-by: Sven Auhagen Signed-off-by: Thomas Petazzoni Signed-off-by: Miquel Raynal Signed-off-by: Gregory CLEMENT --- arch/arm64/boot/dts/marvell/armada-cp11x.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi b/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi index 9dcf16beabf5..ec27294f097b 100644 --- a/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi @@ -300,11 +300,9 @@ }; CP11X_LABEL(sata0): sata@540000 { - compatible = "marvell,armada-8k-ahci", - "generic-ahci"; + compatible = "marvell,armada-8k-ahci"; reg = <0x540000 0x30000>; dma-coherent; - interrupts = <107 IRQ_TYPE_LEVEL_HIGH>; clocks = <&CP11X_LABEL(clk) 1 15>, <&CP11X_LABEL(clk) 1 16>; #address-cells = <1>; @@ -312,10 +310,12 @@ status = "disabled"; sata-port@0 { + interrupts = <109 IRQ_TYPE_LEVEL_HIGH>; reg = <0>; }; sata-port@1 { + interrupts = <107 IRQ_TYPE_LEVEL_HIGH>; reg = <1>; }; }; From 3aa669a994c9110a2dc7e08a5c0958a9ea5eb17c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marek=20Beh=C3=BAn?= Date: Sat, 14 Nov 2020 21:42:53 +0100 Subject: [PATCH 615/799] arm64: dts: armada-3720-turris-mox: update ethernet-phy handle name MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Use property name `phy-handle` instead of the deprecated `phy` to connect eth2 to the PHY. Signed-off-by: Marek Behún Fixes: 7109d817db2e ("arm64: dts: marvell: add DTS for Turris Mox") Cc: Gregory CLEMENT Cc: Andrew Lunn Cc: Rob Herring Cc: devicetree@vger.kernel.org Reviewed-by: Andrew Lunn Signed-off-by: Gregory CLEMENT --- arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts b/arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts index f3a678e0fd99..bf76ebe46379 100644 --- a/arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts +++ b/arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts @@ -146,7 +146,7 @@ pinctrl-names = "default"; pinctrl-0 = <&rgmii_pins>; phy-mode = "rgmii-id"; - phy = <&phy1>; + phy-handle = <&phy1>; status = "okay"; }; From 4076a007bd0f6171434bdb119a0b8797749b0502 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Thu, 26 Nov 2020 15:33:34 +0800 Subject: [PATCH 616/799] arm64: dts: rockchip: Set dr_mode to "host" for OTG on rk3328-roc-cc The board has a standard USB A female port connected to the USB OTG controller's data pins. Set dr_mode in the OTG controller node to indicate this usage, instead of having the implementation guess. Fixes: 2171f4fdac06 ("arm64: dts: rockchip: add roc-rk3328-cc board") Signed-off-by: Chen-Yu Tsai Link: https://lore.kernel.org/r/20201126073336.30794-2-wens@kernel.org Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts b/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts index b70ffb1c6a63..b76282e704de 100644 --- a/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts +++ b/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts @@ -334,6 +334,7 @@ }; &usb20_otg { + dr_mode = "host"; status = "okay"; }; From 65f0b420dea7e70d70cd6ef0f12f9ff81ab90d23 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Thu, 26 Nov 2020 15:33:35 +0800 Subject: [PATCH 617/799] arm64: dts: rockchip: Enable HDMI audio on rk3328-roc-cc The RK3328-ROC-CC already has HDMI display output enabled. Now that audio for the HDMI controller is supported, it can be enabled as well. Enable the simple-audio-card, and the I2S interface the audio is fed from. Signed-off-by: Chen-Yu Tsai Link: https://lore.kernel.org/r/20201126073336.30794-3-wens@kernel.org Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts b/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts index b76282e704de..697fce709031 100644 --- a/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts +++ b/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts @@ -161,6 +161,10 @@ status = "okay"; }; +&hdmi_sound { + status = "okay"; +}; + &i2c1 { status = "okay"; @@ -270,6 +274,10 @@ }; }; +&i2s0 { + status = "okay"; +}; + &io_domains { status = "okay"; From 5df4d4d16ce4c6e6a5cb9d4b684b187f28258219 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Thu, 26 Nov 2020 15:33:36 +0800 Subject: [PATCH 618/799] arm64: dts: rockchip: Enable analog audio on rk3328-roc-cc Now that driver support for the RK3328's audio codec, and the plumbing is defined at the SoC level, we can enable analog audio at the board level. Enable analog audio by enabling the codec and the I2S interface connected and the simple-audio-card that binds them together. Signed-off-by: Chen-Yu Tsai Link: https://lore.kernel.org/r/20201126073336.30794-4-wens@kernel.org Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts b/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts index 697fce709031..19959bfba451 100644 --- a/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts +++ b/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts @@ -104,6 +104,14 @@ }; }; +&analog_sound { + status = "okay"; +}; + +&codec { + status = "okay"; +}; + &cpu0 { cpu-supply = <&vdd_arm>; }; @@ -278,6 +286,10 @@ status = "okay"; }; +&i2s1 { + status = "okay"; +}; + &io_domains { status = "okay"; From 9a9f642784074d09efe9337e64b959f76c9f6913 Mon Sep 17 00:00:00 2001 From: Johan Jonker Date: Mon, 16 Nov 2020 14:23:11 +0100 Subject: [PATCH 619/799] arm64: dts: rockchip: rename sdhci nodename to mmc on rk3399 A test with the command below gives for example this error: /arch/arm64/boot/dts/rockchip/rk3399-evb.dt.yaml: sdhci@fe330000: $nodename:0: 'sdhci@fe330000' does not match '^mmc(@.*)?$' Fix it by renaming sdhci to mmc. make ARCH=arm64 dtbs_check DT_SCHEMA_FILES=Documentation/devicetree/bindings/ mmc/arasan,sdhci.yaml Signed-off-by: Johan Jonker Link: https://lore.kernel.org/r/20201116132311.8318-1-jbx6244@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3399.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi index ada724b12f01..1aa52ec938a1 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi @@ -328,7 +328,7 @@ status = "disabled"; }; - sdhci: sdhci@fe330000 { + sdhci: mmc@fe330000 { compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1"; reg = <0x0 0xfe330000 0x0 0x10000>; interrupts = ; From 4548ea027c900f1e0f07a292b8e10dc3d2725f44 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Mon, 9 Nov 2020 23:40:09 +0530 Subject: [PATCH 620/799] arm64: dts: rockchip: Enable USB Host, OTG on px30-enagicam Engicam EDIMM2.2 and C.Touch 2.0 Kits support USB Host and OTG ports. Add support to enable USB on these kits while mounting px30-core SOM. Signed-off-by: Jagan Teki Link: https://lore.kernel.org/r/20201109181017.206834-2-jagan@amarulasolutions.com Signed-off-by: Heiko Stuebner --- .../dts/rockchip/px30-engicam-common.dtsi | 24 +++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/px30-engicam-common.dtsi b/arch/arm64/boot/dts/rockchip/px30-engicam-common.dtsi index bd5bde989e8d..fbbdbb0a40af 100644 --- a/arch/arm64/boot/dts/rockchip/px30-engicam-common.dtsi +++ b/arch/arm64/boot/dts/rockchip/px30-engicam-common.dtsi @@ -33,7 +33,31 @@ status = "okay"; }; +&u2phy { + status = "okay"; + + u2phy_host: host-port { + status = "okay"; + }; + + u2phy_otg: otg-port { + status = "okay"; + }; +}; + &uart2 { pinctrl-0 = <&uart2m1_xfer>; status = "okay"; }; + +&usb20_otg { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; From 87761edeb2cd90b8251f269eb52c4b48152aace8 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Mon, 9 Nov 2020 23:40:10 +0530 Subject: [PATCH 621/799] arm64: dts: rockchip: Enable LVDS panel on px30-engicam-edimm2.2 Engicam PX30.Core EDIMM2.2 developement Kit has on board 10" LVDS panel from yes-optoelectronics. This patch adds panel enablement nodes on respective dts(i) files. Signed-off-by: Jagan Teki Link: https://lore.kernel.org/r/20201109181017.206834-3-jagan@amarulasolutions.com Signed-off-by: Heiko Stuebner --- .../dts/rockchip/px30-engicam-common.dtsi | 4 ++ .../dts/rockchip/px30-engicam-edimm2.2.dtsi | 59 +++++++++++++++++++ .../dts/rockchip/px30-engicam-px30-core.dtsi | 5 ++ 3 files changed, 68 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/px30-engicam-common.dtsi b/arch/arm64/boot/dts/rockchip/px30-engicam-common.dtsi index fbbdbb0a40af..8fdd7ff2fdf9 100644 --- a/arch/arm64/boot/dts/rockchip/px30-engicam-common.dtsi +++ b/arch/arm64/boot/dts/rockchip/px30-engicam-common.dtsi @@ -25,6 +25,10 @@ status = "okay"; }; +&pwm0 { + status = "okay"; +}; + &sdmmc { cap-sd-highspeed; card-detect-delay = <800>; diff --git a/arch/arm64/boot/dts/rockchip/px30-engicam-edimm2.2.dtsi b/arch/arm64/boot/dts/rockchip/px30-engicam-edimm2.2.dtsi index cb00988953e9..449b8eb6454e 100644 --- a/arch/arm64/boot/dts/rockchip/px30-engicam-edimm2.2.dtsi +++ b/arch/arm64/boot/dts/rockchip/px30-engicam-edimm2.2.dtsi @@ -5,3 +5,62 @@ */ #include "px30-engicam-common.dtsi" + +/ { + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm0 0 25000 0>; + }; + + panel { + compatible = "yes-optoelectronics,ytc700tlag-05-201c"; + backlight = <&backlight>; + data-mapping = "vesa-24"; + power-supply = <&vcc3v3_lcd>; + + port { + panel_in_lvds: endpoint { + remote-endpoint = <&lvds_out_panel>; + }; + }; + }; +}; + +&display_subsystem { + status = "okay"; +}; + +&dsi_dphy { + status = "okay"; +}; + +/* LVDS_B(secondary) */ +&lvds { + status = "okay"; + + ports { + port@1 { + reg = <1>; + + lvds_out_panel: endpoint { + remote-endpoint = <&panel_in_lvds>; + }; + }; + }; +}; + +&vopb { + status = "okay"; +}; + +&vopb_mmu { + status = "okay"; +}; + +&vopl { + status = "okay"; +}; + +&vopl_mmu { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/rockchip/px30-engicam-px30-core.dtsi b/arch/arm64/boot/dts/rockchip/px30-engicam-px30-core.dtsi index db22f776c68f..cdacd3483600 100644 --- a/arch/arm64/boot/dts/rockchip/px30-engicam-px30-core.dtsi +++ b/arch/arm64/boot/dts/rockchip/px30-engicam-px30-core.dtsi @@ -192,6 +192,11 @@ }; }; + vcc3v3_lcd: SWITCH_REG1 { + regulator-boot-on; + regulator-name = "vcc3v3_lcd"; + }; + vcc5v0_host: SWITCH_REG2 { regulator-name = "vcc5v0_host"; regulator-always-on; From 23708d46101b5d5538c88b84b764d0ed9d8957ca Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Mon, 9 Nov 2020 23:40:11 +0530 Subject: [PATCH 622/799] dt-bindings: arm: rockchip: Add Engicam PX30.Core C.TOUCH 2.0 10.1" OF PX30.Core is an EDIMM SOM based on Rockchip PX30 from Engicam. C.TOUCH 2.0 is a general purpose carrier board with capacitive touch interface support. 10.1" OF is a capacitive touch 10.1" Open Frame panel solutions. PX30.Core needs to mount on top of C.TOUCH 2.0 carrier with pluged 10.1" OF for creating complete PX30.Core C.TOUCH 2.0 10.1" Open Frame. Add bindings for it. Acked-by: Rob Herring Signed-off-by: Jagan Teki Link: https://lore.kernel.org/r/20201109181017.206834-4-jagan@amarulasolutions.com Signed-off-by: Heiko Stuebner --- Documentation/devicetree/bindings/arm/rockchip.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml index 798d83d04392..c18059ef50d3 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml @@ -76,6 +76,12 @@ properties: - const: engicam,px30-core - const: rockchip,px30 + - description: Engicam PX30.Core C.TOUCH 2.0 10.1" Open Frame + items: + - const: engicam,px30-core-ctouch2-of10 + - const: engicam,px30-core + - const: rockchip,px30 + - description: Engicam PX30.Core EDIMM2.2 Starter Kit items: - const: engicam,px30-core-edimm2.2 From 0e418423be1c824b2cda37fd00528f62231cd219 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Mon, 9 Nov 2020 23:40:12 +0530 Subject: [PATCH 623/799] arm64: dts: rockchip: Add Engicam PX30.Core C.TOUCH 2.0 10.1" OF PX30.Core is an EDIMM SOM based on Rockchip PX30 from Engicam. C.TOUCH 2.0 is a general purpose carrier board with capacitive touch interface support. 10.1" OF is a capacitive touch 10.1" Open Frame panel solutions. PX30.Core needs to mount on top of C.TOUCH 2.0 carrier with pluged 10.1" OF for creating complete PX30.Core C.TOUCH 2.0 10.1" Open Frame. Add support for it. Signed-off-by: Jagan Teki Link: https://lore.kernel.org/r/20201109181017.206834-5-jagan@amarulasolutions.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/Makefile | 1 + .../px30-engicam-px30-core-ctouch2-of10.dts | 77 +++++++++++++++++++ 2 files changed, 78 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/px30-engicam-px30-core-ctouch2-of10.dts diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile index 5a53979b7057..1ab55a124a87 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -1,6 +1,7 @@ # SPDX-License-Identifier: GPL-2.0 dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-evb.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-engicam-px30-core-ctouch2.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-engicam-px30-core-ctouch2-of10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-engicam-px30-core-edimm2.2.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3308-evb.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3308-roc-cc.dtb diff --git a/arch/arm64/boot/dts/rockchip/px30-engicam-px30-core-ctouch2-of10.dts b/arch/arm64/boot/dts/rockchip/px30-engicam-px30-core-ctouch2-of10.dts new file mode 100644 index 000000000000..47aa30505a42 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/px30-engicam-px30-core-ctouch2-of10.dts @@ -0,0 +1,77 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd + * Copyright (c) 2020 Engicam srl + * Copyright (c) 2020 Amarula Solutions(India) + */ + +/dts-v1/; +#include "px30.dtsi" +#include "px30-engicam-ctouch2.dtsi" +#include "px30-engicam-px30-core.dtsi" + +/ { + model = "Engicam PX30.Core C.TOUCH 2.0 10.1\" Open Frame"; + compatible = "engicam,px30-core-ctouch2-of10", "engicam,px30-core", + "rockchip,px30"; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm0 0 25000 0>; + }; + + chosen { + stdout-path = "serial2:115200n8"; + }; + + panel { + compatible = "ampire,am-1280800n3tzqw-t00h"; + backlight = <&backlight>; + power-supply = <&vcc3v3_lcd>; + data-mapping = "vesa-24"; + + port { + panel_in_lvds: endpoint { + remote-endpoint = <&lvds_out_panel>; + }; + }; + }; +}; + +&display_subsystem { + status = "okay"; +}; + +&dsi_dphy { + status = "okay"; +}; + +&lvds { + status = "okay"; + + ports { + port@1 { + reg = <1>; + + lvds_out_panel: endpoint { + remote-endpoint = <&panel_in_lvds>; + }; + }; + }; +}; + +&vopb { + status = "okay"; +}; + +&vopb_mmu { + status = "okay"; +}; + +&vopl { + status = "okay"; +}; + +&vopl_mmu { + status = "okay"; +}; From 93a4e7d12468b0ab46796f3ed8dc5838dc7f63bc Mon Sep 17 00:00:00 2001 From: Suniel Mahesh Date: Mon, 9 Nov 2020 23:40:13 +0530 Subject: [PATCH 624/799] arm64: dts: rockchip: Add WiFi support on px30-engicam Engicam PX30 carrier boards like EDIMM2.2 and C.TOUCH2.0 have an onboard Sterling-LWD Wifi/BT chip based on BCM43430 connected on the SDIO bus. The SDIO power sequnce is connacted with exteernal 32KHz oscillator and it require 3V3 regulator input. This patch adds WiFi enablement nodes for these respective boards. Signed-off-by: Michael Trimarchi Signed-off-by: Suniel Mahesh Signed-off-by: Jagan Teki Link: https://lore.kernel.org/r/20201109181017.206834-6-jagan@amarulasolutions.com Signed-off-by: Heiko Stuebner --- .../dts/rockchip/px30-engicam-common.dtsi | 45 +++++++++++++++++++ .../dts/rockchip/px30-engicam-ctouch2.dtsi | 12 +++++ .../px30-engicam-px30-core-edimm2.2.dts | 12 +++++ 3 files changed, 69 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/px30-engicam-common.dtsi b/arch/arm64/boot/dts/rockchip/px30-engicam-common.dtsi index 8fdd7ff2fdf9..0e1a93ec3234 100644 --- a/arch/arm64/boot/dts/rockchip/px30-engicam-common.dtsi +++ b/arch/arm64/boot/dts/rockchip/px30-engicam-common.dtsi @@ -14,6 +14,51 @@ regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&xin32k>; + clock-names = "ext_clock"; + post-power-on-delay-ms = <80>; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + }; + + vcc3v3_rf_aux_mod: vcc3v3-rf-aux-mod { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_rf_aux_mod"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc5v0_sys>; + }; + + xin32k: xin32k { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "xin32k"; + }; +}; + +&sdio { + #address-cells = <1>; + #size-cells = <0>; + bus-width = <4>; + clock-frequency = <50000000>; + cap-sdio-irq; + cap-sd-highspeed; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + sd-uhs-sdr104; + status = "okay"; + + brcmf: wifi@1 { + compatible = "brcm,bcm4329-fmac"; + reg = <1>; + }; }; &gmac { diff --git a/arch/arm64/boot/dts/rockchip/px30-engicam-ctouch2.dtsi b/arch/arm64/boot/dts/rockchip/px30-engicam-ctouch2.dtsi index 58425b1e559f..d5708779c285 100644 --- a/arch/arm64/boot/dts/rockchip/px30-engicam-ctouch2.dtsi +++ b/arch/arm64/boot/dts/rockchip/px30-engicam-ctouch2.dtsi @@ -6,3 +6,15 @@ */ #include "px30-engicam-common.dtsi" + +&pinctrl { + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&sdio_pwrseq { + reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; +}; diff --git a/arch/arm64/boot/dts/rockchip/px30-engicam-px30-core-edimm2.2.dts b/arch/arm64/boot/dts/rockchip/px30-engicam-px30-core-edimm2.2.dts index e54d1e480daa..913444548b59 100644 --- a/arch/arm64/boot/dts/rockchip/px30-engicam-px30-core-edimm2.2.dts +++ b/arch/arm64/boot/dts/rockchip/px30-engicam-px30-core-edimm2.2.dts @@ -19,3 +19,15 @@ stdout-path = "serial2:115200n8"; }; }; + +&pinctrl { + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&sdio_pwrseq { + reset-gpios = <&gpio1 RK_PC3 GPIO_ACTIVE_LOW>; +}; From 1cc1e851d15b4ebd4c6c5f741cfdb58b988a4445 Mon Sep 17 00:00:00 2001 From: Suniel Mahesh Date: Mon, 9 Nov 2020 23:40:14 +0530 Subject: [PATCH 625/799] arm64: dts: rockchip: Add BT support on px30-engicam Engicam PX30 carrier boards like EDIMM2.2 and C.TOUCH2.0 have an onboard Sterling-LWD Wifi/BT chip based on BCM43430 connected on the UART bus. UART bus on the design routed via USB to UART CP20x bridge. This bridge powered from 3V3 regualtor gpio. This patch adds BT enablement nodes for these respective boards. Signed-off-by: Michael Trimarchi Signed-off-by: Suniel Mahesh Signed-off-by: Jagan Teki Link: https://lore.kernel.org/r/20201109181017.206834-7-jagan@amarulasolutions.com Signed-off-by: Heiko Stuebner --- .../arm64/boot/dts/rockchip/px30-engicam-common.dtsi | 12 ++++++++++++ .../boot/dts/rockchip/px30-engicam-ctouch2.dtsi | 10 ++++++++++ .../dts/rockchip/px30-engicam-px30-core-edimm2.2.dts | 10 ++++++++++ 3 files changed, 32 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/px30-engicam-common.dtsi b/arch/arm64/boot/dts/rockchip/px30-engicam-common.dtsi index 0e1a93ec3234..08b0b9fbcbc9 100644 --- a/arch/arm64/boot/dts/rockchip/px30-engicam-common.dtsi +++ b/arch/arm64/boot/dts/rockchip/px30-engicam-common.dtsi @@ -24,6 +24,18 @@ pinctrl-0 = <&wifi_enable_h>; }; + vcc3v3_btreg: vcc3v3-btreg { + compatible = "regulator-gpio"; + enable-active-high; + pinctrl-names = "default"; + pinctrl-0 = <&bt_enable_h>; + regulator-name = "btreg-gpio-supply"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + states = <3300000 0x0>; + }; + vcc3v3_rf_aux_mod: vcc3v3-rf-aux-mod { compatible = "regulator-fixed"; regulator-name = "vcc3v3_rf_aux_mod"; diff --git a/arch/arm64/boot/dts/rockchip/px30-engicam-ctouch2.dtsi b/arch/arm64/boot/dts/rockchip/px30-engicam-ctouch2.dtsi index d5708779c285..bf10a3d29fca 100644 --- a/arch/arm64/boot/dts/rockchip/px30-engicam-ctouch2.dtsi +++ b/arch/arm64/boot/dts/rockchip/px30-engicam-ctouch2.dtsi @@ -8,6 +8,12 @@ #include "px30-engicam-common.dtsi" &pinctrl { + bt { + bt_enable_h: bt-enable-h { + rockchip,pins = <1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + sdio-pwrseq { wifi_enable_h: wifi-enable-h { rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; @@ -18,3 +24,7 @@ &sdio_pwrseq { reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; }; + +&vcc3v3_btreg { + enable-gpio = <&gpio1 RK_PC3 GPIO_ACTIVE_HIGH>; +}; diff --git a/arch/arm64/boot/dts/rockchip/px30-engicam-px30-core-edimm2.2.dts b/arch/arm64/boot/dts/rockchip/px30-engicam-px30-core-edimm2.2.dts index 913444548b59..d759478e1c84 100644 --- a/arch/arm64/boot/dts/rockchip/px30-engicam-px30-core-edimm2.2.dts +++ b/arch/arm64/boot/dts/rockchip/px30-engicam-px30-core-edimm2.2.dts @@ -21,6 +21,12 @@ }; &pinctrl { + bt { + bt_enable_h: bt-enable-h { + rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + sdio-pwrseq { wifi_enable_h: wifi-enable-h { rockchip,pins = <1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; @@ -31,3 +37,7 @@ &sdio_pwrseq { reset-gpios = <&gpio1 RK_PC3 GPIO_ACTIVE_LOW>; }; + +&vcc3v3_btreg { + enable-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_HIGH>; +}; From dbb378a59cb2bdb01454098513d9b61355fbe377 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Mon, 9 Nov 2020 23:40:15 +0530 Subject: [PATCH 626/799] arm64: defconfig: Enable ROCKCHIP_LVDS Now, some of the rockchip hardware platforms do enable lvds in mainline tree. So, enable Rockchip LVDS driver via default defconfig. Signed-off-by: Jagan Teki Link: https://lore.kernel.org/r/20201109181017.206834-8-jagan@amarulasolutions.com Signed-off-by: Heiko Stuebner --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 17a2df6a263e..65d6b59da7bd 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -645,6 +645,7 @@ CONFIG_ROCKCHIP_CDN_DP=y CONFIG_ROCKCHIP_DW_HDMI=y CONFIG_ROCKCHIP_DW_MIPI_DSI=y CONFIG_ROCKCHIP_INNO_HDMI=y +CONFIG_ROCKCHIP_LVDS=y CONFIG_DRM_RCAR_DU=m CONFIG_DRM_RCAR_DW_HDMI=m CONFIG_DRM_SUN4I=m From ec68a66395d9ccedc9b2b2f6452edfd7cb0fdfd5 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Mon, 9 Nov 2020 23:40:16 +0530 Subject: [PATCH 627/799] arm64: defconfig: Enable PHY_ROCKCHIP_INNO_DSIDPHY In order to work LDVS, DSI in mainline tree for Rockchip based hardware platforms, the associated PHY driver has to enable in default defconfig. Enable rockchip DSI phy driver. Signed-off-by: Jagan Teki Link: https://lore.kernel.org/r/20201109181017.206834-9-jagan@amarulasolutions.com Signed-off-by: Heiko Stuebner --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 65d6b59da7bd..e796c82cd2d3 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -1010,6 +1010,7 @@ CONFIG_PHY_RCAR_GEN3_USB3=m CONFIG_PHY_ROCKCHIP_EMMC=y CONFIG_PHY_ROCKCHIP_INNO_HDMI=m CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY=m CONFIG_PHY_ROCKCHIP_PCIE=m CONFIG_PHY_ROCKCHIP_TYPEC=y CONFIG_PHY_UNIPHIER_USB2=y From cf35bff64f79b4ca8785766d67b608b76404d43f Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Mon, 9 Nov 2020 23:40:17 +0530 Subject: [PATCH 628/799] arm64: defconfig: Enable USB_SERIAL_CP210X Some hardware platforms required CP20x USB to Serial converter in order to work onboard functionalities like Bluetooth. An example of such a platform is from Engicam's PX30 (ARM64). Mark it as module in defconfig. Signed-off-by: Jagan Teki Link: https://lore.kernel.org/r/20201109181017.206834-10-jagan@amarulasolutions.com Signed-off-by: Heiko Stuebner --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index e796c82cd2d3..15c2128e846a 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -750,6 +750,7 @@ CONFIG_USB_CHIPIDEA_UDC=y CONFIG_USB_CHIPIDEA_HOST=y CONFIG_USB_ISP1760=y CONFIG_USB_SERIAL=m +CONFIG_USB_SERIAL_CP210X=m CONFIG_USB_SERIAL_FTDI_SIO=m CONFIG_USB_HSIC_USB3503=y CONFIG_NOP_USB_XCEIV=y From 879e5b3f98bae035cf8e2f777cc3c64bde8d6d9b Mon Sep 17 00:00:00 2001 From: Joel Stanley Date: Thu, 19 Nov 2020 18:02:30 +1030 Subject: [PATCH 629/799] dt-bindings: vendor-prefixes: Add FII Adds Foxconn Industrial Internet, who have submitted a BMC device tree. Signed-off-by: Joel Stanley Reviewed-by: Benjamin Fair Link: https://lore.kernel.org/r/20201119073230.123888-1-joel@jms.id.au Signed-off-by: Joel Stanley --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index 2735be1a8470..5e69fbfe544c 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -377,6 +377,8 @@ patternProperties: description: Shenzhen Feixin Photoelectic Co., Ltd "^feiyang,.*": description: Shenzhen Fly Young Technology Co.,LTD. + "^fii,.*": + description: Foxconn Industrial Internet "^firefly,.*": description: Firefly "^focaltech,.*": From 7a1980567fa0b8f37c0fc7d9ca0c7c70724bae3d Mon Sep 17 00:00:00 2001 From: Ran Wang Date: Mon, 2 Nov 2020 15:26:51 +0800 Subject: [PATCH 630/799] ARM: dts: ls1021a: fix flextimer failed to wake system The data of property 'fsl,rcpm-wakeup' is not corrcet, which causing RCPM driver incorrectly program register IPPDEXPCR1, then flextimer is wrongly clock gated during system suspend, can't send interrupt to wake. Signed-off-by: Ran Wang Acked-by: Li Yang Signed-off-by: Shawn Guo --- arch/arm/boot/dts/ls1021a.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi index 827373ef1a54..e12809d646a2 100644 --- a/arch/arm/boot/dts/ls1021a.dtsi +++ b/arch/arm/boot/dts/ls1021a.dtsi @@ -1013,7 +1013,7 @@ compatible = "fsl,ls1021a-ftm-alarm"; reg = <0x0 0x29d0000 0x0 0x10000>; reg-names = "ftm"; - fsl,rcpm-wakeup = <&rcpm 0x20000 0x0>; + fsl,rcpm-wakeup = <&rcpm 0x0 0x20000000>; interrupts = ; big-endian; }; From 4ebd35bfb1831e549467a0deda99b39acb62cf50 Mon Sep 17 00:00:00 2001 From: Ran Wang Date: Mon, 2 Nov 2020 15:26:52 +0800 Subject: [PATCH 631/799] ARM: dts: ls1021a: fix rcpm failed to claim resource The range of dcfg reg is wrong, which overlap with other device, such as rcpm. This issue causing rcpm driver failed to claim reg resource when calling devm_ioremap_resource(). Signed-off-by: Ran Wang Acked-by: Li Yang Signed-off-by: Shawn Guo --- arch/arm/boot/dts/ls1021a.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi index e12809d646a2..16744f64e431 100644 --- a/arch/arm/boot/dts/ls1021a.dtsi +++ b/arch/arm/boot/dts/ls1021a.dtsi @@ -173,7 +173,7 @@ dcfg: dcfg@1ee0000 { compatible = "fsl,ls1021a-dcfg", "syscon"; - reg = <0x0 0x1ee0000 0x0 0x10000>; + reg = <0x0 0x1ee0000 0x0 0x1000>; big-endian; }; From 4ba79e25d7f1a7394021ba4c215a7ecdcc270fb6 Mon Sep 17 00:00:00 2001 From: Ivan Zaentsev Date: Mon, 16 Nov 2020 19:58:26 +0300 Subject: [PATCH 632/799] ARM: mxs: Add serial number support for i.MX23, i.MX28 SoCs i.MX23 and i.MX28 SoCs unique identifiers are factory-programmed in On-Chip OTP memory. i.MX28's 64-bit unique id is in HW_OCOTP_OPS2:HW_OCOTP_OPS3 (see MCIMX28 Ref. Man., sec. 20.4.22-23). i.MX23 provides 32-bit long unique id in HW_OCOTP_OPS3. Though not clearly documented, there is a clue in sec. 35.9.3. The unique id is reported in /sys/devices/soc0/serial_number and in /proc/cpuinfo Signed-off-by: Ivan Zaentsev Suggested-by: Evgeny Boger Signed-off-by: Shawn Guo --- arch/arm/mach-mxs/mach-mxs.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm/mach-mxs/mach-mxs.c b/arch/arm/mach-mxs/mach-mxs.c index c109f47e9cbc..25c9d184fa4c 100644 --- a/arch/arm/mach-mxs/mach-mxs.c +++ b/arch/arm/mach-mxs/mach-mxs.c @@ -22,6 +22,7 @@ #include #include #include +#include #include #include "pm.h" @@ -51,6 +52,9 @@ #define MXS_CLR_ADDR 0x8 #define MXS_TOG_ADDR 0xc +#define HW_OCOTP_OPS2 19 /* offset 0x150 */ +#define HW_OCOTP_OPS3 20 /* offset 0x160 */ + static u32 chipid; static u32 socid; @@ -379,6 +383,8 @@ static void __init mxs_machine_init(void) struct device *parent; struct soc_device *soc_dev; struct soc_device_attribute *soc_dev_attr; + u64 soc_uid = 0; + const u32 *ocotp = mxs_get_ocotp(); int ret; soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL); @@ -394,8 +400,21 @@ static void __init mxs_machine_init(void) soc_dev_attr->soc_id = mxs_get_soc_id(); soc_dev_attr->revision = mxs_get_revision(); + if (socid == HW_DIGCTL_CHIPID_MX23) { + soc_uid = system_serial_low = ocotp[HW_OCOTP_OPS3]; + } else if (socid == HW_DIGCTL_CHIPID_MX28) { + soc_uid = system_serial_high = ocotp[HW_OCOTP_OPS2]; + soc_uid <<= 32; + system_serial_low = ocotp[HW_OCOTP_OPS3]; + soc_uid |= system_serial_low; + } + + if (soc_uid) + soc_dev_attr->serial_number = kasprintf(GFP_KERNEL, "%016llX", soc_uid); + soc_dev = soc_device_register(soc_dev_attr); if (IS_ERR(soc_dev)) { + kfree(soc_dev_attr->serial_number); kfree(soc_dev_attr->revision); kfree(soc_dev_attr); return; From b675aaee5464ca8384853145578e662e54debf7a Mon Sep 17 00:00:00 2001 From: Yuantian Tang Date: Tue, 17 Nov 2020 11:43:05 +0800 Subject: [PATCH 633/799] ARM: dts: ls1021a: update calibration table for TMU module Update the calibration table to make the temperature more accurate. Signed-off-by: Yuantian Tang Signed-off-by: Shawn Guo --- arch/arm/boot/dts/ls1021a.dtsi | 71 ++++++++++++++++------------------ 1 file changed, 34 insertions(+), 37 deletions(-) diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi index 16744f64e431..007dd2bd0595 100644 --- a/arch/arm/boot/dts/ls1021a.dtsi +++ b/arch/arm/boot/dts/ls1021a.dtsi @@ -288,46 +288,43 @@ compatible = "fsl,qoriq-tmu"; reg = <0x0 0x1f00000 0x0 0x10000>; interrupts = ; - fsl,tmu-range = <0xb0000 0xa0026 0x80048 0x30061>; - fsl,tmu-calibration = <0x00000000 0x0000000f - 0x00000001 0x00000017 - 0x00000002 0x0000001e - 0x00000003 0x00000026 - 0x00000004 0x0000002e - 0x00000005 0x00000035 - 0x00000006 0x0000003d - 0x00000007 0x00000044 - 0x00000008 0x0000004c - 0x00000009 0x00000053 - 0x0000000a 0x0000005b - 0x0000000b 0x00000064 + fsl,tmu-range = <0xb0000 0x9002c 0x6004e 0x30066>; + fsl,tmu-calibration = <0x00000000 0x00000020 + 0x00000001 0x00000024 + 0x00000002 0x0000002a + 0x00000003 0x00000032 + 0x00000004 0x00000038 + 0x00000005 0x0000003e + 0x00000006 0x00000043 + 0x00000007 0x0000004a + 0x00000008 0x00000050 + 0x00000009 0x00000059 + 0x0000000a 0x0000005f + 0x0000000b 0x00000066 - 0x00010000 0x00000011 - 0x00010001 0x0000001c - 0x00010002 0x00000024 - 0x00010003 0x0000002b - 0x00010004 0x00000034 - 0x00010005 0x00000039 - 0x00010006 0x00000042 - 0x00010007 0x0000004c - 0x00010008 0x00000051 - 0x00010009 0x0000005a - 0x0001000a 0x00000063 + 0x00010000 0x00000023 + 0x00010001 0x0000002b + 0x00010002 0x00000033 + 0x00010003 0x0000003a + 0x00010004 0x00000042 + 0x00010005 0x0000004a + 0x00010006 0x00000054 + 0x00010007 0x0000005c + 0x00010008 0x00000065 + 0x00010009 0x0000006f - 0x00020000 0x00000013 - 0x00020001 0x00000019 - 0x00020002 0x00000024 - 0x00020003 0x0000002c - 0x00020004 0x00000035 - 0x00020005 0x0000003d - 0x00020006 0x00000046 - 0x00020007 0x00000050 - 0x00020008 0x00000059 + 0x00020000 0x00000029 + 0x00020001 0x00000033 + 0x00020002 0x0000003d + 0x00020003 0x00000048 + 0x00020004 0x00000054 + 0x00020005 0x00000060 + 0x00020006 0x0000006c - 0x00030000 0x00000002 - 0x00030001 0x0000000d - 0x00030002 0x00000019 - 0x00030003 0x00000024>; + 0x00030000 0x00000025 + 0x00030001 0x00000033 + 0x00030002 0x00000043 + 0x00030003 0x00000055>; #thermal-sensor-cells = <1>; }; From 11916ecb8363e3661635fe66d4b25e27451853ee Mon Sep 17 00:00:00 2001 From: Bruno Thomsen Date: Wed, 18 Nov 2020 11:21:18 +0100 Subject: [PATCH 634/799] dt-bindings: fsl: add kamstrup flex concentrator to schema Add Kamstrup OMNIA Flex Concentrator compatibles to the schema so we can make use of them for the validation. Signed-off-by: Bruno Thomsen Acked-by: Rob Herring Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/arm/fsl.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index 0cf302867376..ca1d927b7493 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -605,6 +605,8 @@ properties: - compulab,cl-som-imx7 # CompuLab CL-SOM-iMX7 - fsl,imx7d-sdb # i.MX7 SabreSD Board - fsl,imx7d-sdb-reva # i.MX7 SabreSD Rev-A Board + - kam,imx7d-flex-concentrator # Kamstrup OMNIA Flex Concentrator + - kam,imx7d-flex-concentrator-mfg # Kamstrup OMNIA Flex Concentrator in manufacturing mode - novtech,imx7d-meerkat96 # i.MX7 Meerkat96 Board - technexion,imx7d-pico-dwarf # TechNexion i.MX7D Pico-Dwarf - technexion,imx7d-pico-hobbit # TechNexion i.MX7D Pico-Hobbit From 1e1a5afde9f79386815233aacf48e188a6710fc2 Mon Sep 17 00:00:00 2001 From: Bruno Thomsen Date: Wed, 18 Nov 2020 11:21:19 +0100 Subject: [PATCH 635/799] ARM: dts: imx7: add support for kamstrup flex concentrator This adds support for the OMNIA Flex Concentrator product from Kamstrup A/S. It's providing radio mesh communication infrastructure for smart electricity meters. Kamstrup OMNIA is a modular and scalable smart grid platform. Signed-off-by: Bruno Thomsen Signed-off-by: Shawn Guo --- arch/arm/boot/dts/Makefile | 2 + .../boot/dts/imx7d-flex-concentrator-mfg.dts | 25 ++ arch/arm/boot/dts/imx7d-flex-concentrator.dts | 314 ++++++++++++++++++ 3 files changed, 341 insertions(+) create mode 100644 arch/arm/boot/dts/imx7d-flex-concentrator-mfg.dts create mode 100644 arch/arm/boot/dts/imx7d-flex-concentrator.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index d3275fe3095f..0a7544e01f02 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -644,6 +644,8 @@ dtb-$(CONFIG_SOC_IMX7D) += \ imx7d-colibri-emmc-aster.dtb \ imx7d-colibri-emmc-eval-v3.dtb \ imx7d-colibri-eval-v3.dtb \ + imx7d-flex-concentrator.dtb \ + imx7d-flex-concentrator-mfg.dtb \ imx7d-mba7.dtb \ imx7d-meerkat96.dtb \ imx7d-nitrogen7.dtb \ diff --git a/arch/arm/boot/dts/imx7d-flex-concentrator-mfg.dts b/arch/arm/boot/dts/imx7d-flex-concentrator-mfg.dts new file mode 100644 index 000000000000..a6d68165fb1e --- /dev/null +++ b/arch/arm/boot/dts/imx7d-flex-concentrator-mfg.dts @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for Kamstrup OMNIA Flex Concentrator in + * manufacturing/debugging mode. + * + * Copyright (C) 2020 Kamstrup A/S + * Author: Bruno Thomsen + */ + +/dts-v1/; + +#include "imx7d-flex-concentrator.dts" + +/ { + model = "Kamstrup OMNIA Flex Concentrator - Manufacturing"; + compatible = "kam,imx7d-flex-concentrator-mfg", "fsl,imx7d"; + + chosen { + stdout-path = &uart4; + }; +}; + +&uart4 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx7d-flex-concentrator.dts b/arch/arm/boot/dts/imx7d-flex-concentrator.dts new file mode 100644 index 000000000000..84b095279e65 --- /dev/null +++ b/arch/arm/boot/dts/imx7d-flex-concentrator.dts @@ -0,0 +1,314 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for Kamstrup OMNIA Flex Concentrator. + * + * Copyright (C) 2020 Kamstrup A/S + * Author: Bruno Thomsen + */ + +/dts-v1/; + +#include "imx7d-tqma7.dtsi" + +/* One I2C device on TQMa7 SoM is not mounted */ +/delete-node/ &ds1339; + +/ { + model = "Kamstrup OMNIA Flex Concentrator"; + compatible = "kam,imx7d-flex-concentrator", "fsl,imx7d"; + + memory@80000000 { + device_type = "memory"; + /* 1024 MB - TQMa7D board configuration */ + reg = <0x80000000 0x40000000>; + }; + + reg_usb_otg2_vbus: regulator-usb-otg2-vbus { + compatible = "regulator-fixed"; + regulator-name = "VBUS_USBOTG2"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_vref_1v8: regulator-vref-1v8 { + compatible = "regulator-fixed"; + regulator-name = "VCC1V8_REF"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + vin-supply = <&sw2_reg>; + }; + + /* + * Human Machine Interface consists of 4 dual red/green LEDs. + * hmi-a:green is controlled directly by the switch-mode power supply. + * hmi-a:red is not used. + */ + gpio-leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_leds>; + + led-0 { + label = "hmi-b:red:heartbeat-degraded"; + gpios = <&gpio3 6 GPIO_ACTIVE_HIGH>; + }; + + led-1 { + label = "hmi-b:green:heartbeat-running"; + gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + + led-2 { + label = "hmi-c:red:mesh-error"; + gpios = <&gpio2 29 GPIO_ACTIVE_HIGH>; + }; + + led-3 { + label = "hmi-c:green:mesh-activity"; + gpios = <&gpio2 30 GPIO_ACTIVE_HIGH>; + }; + + led-4 { + label = "hmi-d:red:omnia-error"; + gpios = <&gpio2 31 GPIO_ACTIVE_HIGH>; + }; + + led-5 { + label = "hmi-d:green:omnia-activity"; + gpios = <&gpio4 3 GPIO_ACTIVE_HIGH>; + }; + }; + + /* + * Errata e10574 board restart workaround. + */ + gpio-restart { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_restart>; + compatible = "gpio-restart"; + gpios = <&gpio7 12 GPIO_ACTIVE_LOW>; + priority = <200>; + }; +}; + +/* + * Analog signals + * ADC1_IN0: SMPS - 5V output monitor (voltage divider: 1/0.2806) + */ +&adc1 { + vref-supply = <®_vref_1v8>; + status = "okay"; +}; + +&ecspi2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi2>; + num-chipselects = <1>; + cs-gpios = <&gpio4 23 GPIO_ACTIVE_LOW>; + status = "okay"; + + pcf2127: rtc@0 { + compatible = "nxp,pcf2127"; + reg = <0>; + spi-max-frequency = <2000000>; + }; +}; + +&ecspi4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi4>; + num-chipselects = <1>; + cs-gpios = <&gpio3 3 GPIO_ACTIVE_LOW>; + status = "okay"; + + /* + * ST chip maximum SPI clock frequency is 33 MHz. + * + * TCG specification - Section 6.4.1 Clocking: + * TPM shall support a SPI clock frequency range of 10-24 MHz. + */ + st33htph: tpm-tis@0 { + compatible = "st,st33htpm-spi", "tcg,tpm_tis-spi"; + reg = <0>; + spi-max-frequency = <24000000>; + }; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet1>; + phy-mode = "rmii"; + phy-handle = <ðphy>; + status = "okay"; + + /* + * MDIO bus reset is used to generate PHY device reset before + * Ethernet PHY type ID auto-detection. Otherwise this communication + * fails as device does not answer when recommended reset circuit + * is used. + */ + mdio { + #address-cells = <1>; + #size-cells = <0>; + + reset-delay-us = <100000>; + reset-post-delay-us = <500000>; + reset-gpios = <&gpio7 15 GPIO_ACTIVE_LOW>; + + /* Microchip/Micrel KSZ8081RNB */ + ethphy: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + interrupt-parent = <&gpio1>; + interrupts = <9 IRQ_TYPE_LEVEL_LOW>; + reg = <1>; + }; + }; +}; + +/* + * Detection signals for internal USB modules. + * Used for robust USB plug and play handling such as USB downstream port + * power-cycle and USB hub reset in case of misbehaving or crashed modules. + * + * SMPS - AC input monitor based on zero crossing. + * Used for last gasp notification. + */ +&gpio3 { + gpio-line-names = "", "", "", "", "", "", "", "", + "", "", "", "", "smps-ac-monitor", "", "usb-hub-reset", "", + "", "", "", "", "", "", "", "", + "", "module-b-detection", "", "module-a-detection", "", "", "", ""; +}; + +/* + * Tamper IRQ trigger timestamp reading. + * Used for sealed cover opened/closed notification. + */ +&gpio5 { + gpio-line-names = "", "", "", "", "", "", "", "", + "", "", "", "", "rtc-tamper-irq", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_misc>; + + pinctrl_ecspi2: ecspi2grp { + fsl,pins = < + MX7D_PAD_ECSPI2_MISO__ECSPI2_MISO 0x7c /* X2-15 */ + MX7D_PAD_ECSPI2_MOSI__ECSPI2_MOSI 0x74 /* X2-18 */ + MX7D_PAD_ECSPI2_SCLK__ECSPI2_SCLK 0x74 /* X2-13 */ + MX7D_PAD_ECSPI2_SS0__GPIO4_IO23 0x74 /* X2-20 */ + /* RTC - Tamper IRQ */ + MX7D_PAD_SD2_CLK__GPIO5_IO12 0x3c /* X1-92 */ + >; + }; + + pinctrl_ecspi4: ecspi4grp { + fsl,pins = < + MX7D_PAD_LCD_CLK__ECSPI4_MISO 0x7c /* X2-72 */ + MX7D_PAD_LCD_ENABLE__ECSPI4_MOSI 0x74 /* X2-68 */ + MX7D_PAD_LCD_HSYNC__ECSPI4_SCLK 0x74 /* X2-76 */ + MX7D_PAD_LCD_VSYNC__GPIO3_IO3 0x74 /* X2-78 */ + >; + }; + + pinctrl_enet1: enet1grp { + fsl,pins = < + MX7D_PAD_GPIO1_IO10__ENET1_MDIO 0x03 /* X2-48 */ + MX7D_PAD_GPIO1_IO11__ENET1_MDC 0x03 /* X2-46 */ + MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x71 /* X2-53 */ + MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x71 /* X2-55 */ + MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x71 /* X2-61 */ + MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x79 /* X2-56 */ + MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x79 /* X2-58 */ + MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x79 /* X2-64 */ + MX7D_PAD_ENET1_RGMII_RXC__ENET1_RX_ER 0x73 /* X2-52 */ + /* PHY reset: SRE_FAST, DSE_X1 */ + MX7D_PAD_ENET1_COL__GPIO7_IO15 0x00 /* X1-96 */ + /* Clock from PHY to MAC: 100kPU */ + MX7D_PAD_GPIO1_IO12__CCM_ENET_REF_CLK1 0x70 /* X3-4 */ + /* PHY interrupt: 100kPU, HYS */ + MX7D_PAD_GPIO1_IO09__GPIO1_IO9 0x78 /* X1-80 */ + >; + }; + + pinctrl_leds: ledsgrp { + fsl,pins = < + MX7D_PAD_LCD_DATA01__GPIO3_IO6 0x14 /* X2-82 */ + MX7D_PAD_EPDC_BDR0__GPIO2_IO28 0x14 /* X1-82 */ + MX7D_PAD_EPDC_BDR1__GPIO2_IO29 0x14 /* X1-84 */ + MX7D_PAD_EPDC_PWR_COM__GPIO2_IO30 0x14 /* X1-86 */ + MX7D_PAD_EPDC_PWR_STAT__GPIO2_IO31 0x14 /* X1-88 */ + MX7D_PAD_UART2_TX_DATA__GPIO4_IO3 0x14 /* X1-90 */ + >; + }; + + pinctrl_misc: miscgrp { + fsl,pins = < + /* Module A detection (low = present) */ + MX7D_PAD_LCD_DATA22__GPIO3_IO27 0x7c /* X2-105 */ + /* Module B detection (low = present) */ + MX7D_PAD_LCD_DATA20__GPIO3_IO25 0x7c /* X2-103 */ + /* SMPS - AC input monitor (high = failure) */ + MX7D_PAD_LCD_DATA07__GPIO3_IO12 0x7c /* X2-88 */ + /* USB - Hub reset */ + MX7D_PAD_LCD_DATA09__GPIO3_IO14 0x74 /* X2-92 */ + >; + }; + + pinctrl_restart: restartgrp { + fsl,pins = < + MX7D_PAD_ENET1_TX_CLK__GPIO7_IO12 0x74 /* X1-94 */ + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX7D_PAD_SAI2_TX_SYNC__UART4_DCE_RX 0x7e /* X3-14 */ + MX7D_PAD_SAI2_TX_BCLK__UART4_DCE_TX 0x76 /* X3-16 */ + >; + }; +}; + +&iomuxc_lpsr { + pinctrl_usbotg2: usbotg2grp { + fsl,pins = < + MX7D_PAD_LPSR_GPIO1_IO06__USB_OTG2_OC 0x5c /* X3-11 */ + MX7D_PAD_LPSR_GPIO1_IO07__GPIO1_IO7 0x59 /* X3-9 */ + >; + }; + +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + assigned-clocks = <&clks IMX7D_UART4_ROOT_SRC>; + assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>; +}; + +&usbotg2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg2>; + vbus-supply = <®_usb_otg2_vbus>; + srp-disable; + hnp-disable; + adp-disable; + over-current-active-low; + dr_mode = "host"; + status = "okay"; +}; + +/* + * External watchdog feature provided by pcf2127. + */ +&wdog1 { + status = "disabled"; +}; From cbc4a395dcc730be9114ef077a67e07b32a029a4 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Mon, 5 Oct 2020 15:35:13 +0200 Subject: [PATCH 636/799] arm64: dts: marvell: espressobin: Update link to V7 schematic MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Up-to-date version of V7 schematic is on new URL linked from official tech-spec webpage http://espressobin.net/tech-spec/ Signed-off-by: Pali Rohár Signed-off-by: Gregory CLEMENT --- arch/arm64/boot/dts/marvell/armada-3720-espressobin-v7-emmc.dts | 2 +- arch/arm64/boot/dts/marvell/armada-3720-espressobin-v7.dts | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/marvell/armada-3720-espressobin-v7-emmc.dts b/arch/arm64/boot/dts/marvell/armada-3720-espressobin-v7-emmc.dts index 58b94db5f652..75401eab4d42 100644 --- a/arch/arm64/boot/dts/marvell/armada-3720-espressobin-v7-emmc.dts +++ b/arch/arm64/boot/dts/marvell/armada-3720-espressobin-v7-emmc.dts @@ -8,7 +8,7 @@ * */ /* - * Schematic available at http://wiki.espressobin.net/tiki-download_file.php?fileId=200 + * Schematic available at http://espressobin.net/wp-content/uploads/2020/05/ESPRESSObin_V7-0_Schematic.pdf */ /dts-v1/; diff --git a/arch/arm64/boot/dts/marvell/armada-3720-espressobin-v7.dts b/arch/arm64/boot/dts/marvell/armada-3720-espressobin-v7.dts index b22ae550a45b..48a7f50fb427 100644 --- a/arch/arm64/boot/dts/marvell/armada-3720-espressobin-v7.dts +++ b/arch/arm64/boot/dts/marvell/armada-3720-espressobin-v7.dts @@ -8,7 +8,7 @@ * */ /* - * Schematic available at http://wiki.espressobin.net/tiki-download_file.php?fileId=200 + * Schematic available at http://espressobin.net/wp-content/uploads/2020/05/ESPRESSObin_V7-0_Schematic.pdf */ /dts-v1/; From 018b88eee1a2efda26ed2f09aab33ccdc40ef18f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marek=20Beh=C3=BAn?= Date: Sun, 15 Nov 2020 14:59:17 +0100 Subject: [PATCH 637/799] ARM: dts: turris-omnia: enable HW buffer management MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The buffer manager is available on Turris Omnia but needs to be described in device-tree to be used. Signed-off-by: Marek Behún Fixes: 26ca8b52d6e1 ("ARM: dts: add support for Turris Omnia") Cc: linux-arm-kernel@lists.infradead.org Cc: Uwe Kleine-König Cc: Jason Cooper Cc: Gregory CLEMENT Cc: Andreas Färber Cc: Andrew Lunn Cc: Rob Herring Cc: devicetree@vger.kernel.org Signed-off-by: Gregory CLEMENT --- arch/arm/boot/dts/armada-385-turris-omnia.dts | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm/boot/dts/armada-385-turris-omnia.dts b/arch/arm/boot/dts/armada-385-turris-omnia.dts index 768b6c5d2129..b6bd73d8f2ba 100644 --- a/arch/arm/boot/dts/armada-385-turris-omnia.dts +++ b/arch/arm/boot/dts/armada-385-turris-omnia.dts @@ -84,12 +84,23 @@ }; }; +&bm { + status = "okay"; +}; + +&bm_bppi { + status = "okay"; +}; + /* Connected to 88E6176 switch, port 6 */ ð0 { pinctrl-names = "default"; pinctrl-0 = <&ge0_rgmii_pins>; status = "okay"; phy-mode = "rgmii"; + buffer-manager = <&bm>; + bm,pool-long = <0>; + bm,pool-short = <3>; fixed-link { speed = <1000>; @@ -103,6 +114,9 @@ pinctrl-0 = <&ge1_rgmii_pins>; status = "okay"; phy-mode = "rgmii"; + buffer-manager = <&bm>; + bm,pool-long = <1>; + bm,pool-short = <3>; fixed-link { speed = <1000>; @@ -115,6 +129,9 @@ status = "okay"; phy-mode = "sgmii"; phy = <&phy1>; + buffer-manager = <&bm>; + bm,pool-long = <2>; + bm,pool-short = <3>; }; &i2c0 { From 9ec25ef84832209a8326f9a71fe3ba14f4bcf301 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marek=20Beh=C3=BAn?= Date: Sun, 15 Nov 2020 14:59:18 +0100 Subject: [PATCH 638/799] ARM: dts: turris-omnia: add comphy handle to eth2 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The eth2 controller on Turris Omnia is connected to SerDes. For SFP to be able to switch between 1G and 2.5G modes the comphy link has to be defined. Signed-off-by: Marek Behún Fixes: f3a6a9f3704a ("ARM: dts: add description for Armada 38x ...") Reviewed-by: Andrew Lunn Reviewed-by: Andreas Färber Cc: linux-arm-kernel@lists.infradead.org Cc: Uwe Kleine-König Cc: Jason Cooper Cc: Gregory CLEMENT Cc: Rob Herring Cc: devicetree@vger.kernel.org Signed-off-by: Gregory CLEMENT --- arch/arm/boot/dts/armada-385-turris-omnia.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/armada-385-turris-omnia.dts b/arch/arm/boot/dts/armada-385-turris-omnia.dts index b6bd73d8f2ba..9de26c78ec4c 100644 --- a/arch/arm/boot/dts/armada-385-turris-omnia.dts +++ b/arch/arm/boot/dts/armada-385-turris-omnia.dts @@ -129,6 +129,7 @@ status = "okay"; phy-mode = "sgmii"; phy = <&phy1>; + phys = <&comphy5 2>; buffer-manager = <&bm>; bm,pool-long = <2>; bm,pool-short = <3>; From d29b67c220caf5f4905e1f1576e71bcb6de4af9e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marek=20Beh=C3=BAn?= Date: Sun, 15 Nov 2020 14:59:19 +0100 Subject: [PATCH 639/799] ARM: dts: turris-omnia: describe switch interrupt MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Describe switch interrupt for Turris Omnia so that the CPU does not have to poll the switch. We also need to to set mpp45 pin to gpio function for this. Signed-off-by: Marek Behún Fixes: 26ca8b52d6e1 ("ARM: dts: add support for Turris Omnia") Cc: linux-arm-kernel@lists.infradead.org Cc: Uwe Kleine-König Cc: Jason Cooper Cc: Gregory CLEMENT Cc: Andreas Färber Cc: Andrew Lunn Cc: Rob Herring Cc: devicetree@vger.kernel.org Signed-off-by: Gregory CLEMENT --- arch/arm/boot/dts/armada-385-turris-omnia.dts | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/armada-385-turris-omnia.dts b/arch/arm/boot/dts/armada-385-turris-omnia.dts index 9de26c78ec4c..7ccebf7d1757 100644 --- a/arch/arm/boot/dts/armada-385-turris-omnia.dts +++ b/arch/arm/boot/dts/armada-385-turris-omnia.dts @@ -260,13 +260,18 @@ /* Switch MV88E6176 at address 0x10 */ switch@10 { + pinctrl-names = "default"; + pinctrl-0 = <&swint_pins>; compatible = "marvell,mv88e6085"; #address-cells = <1>; #size-cells = <0>; - dsa,member = <0 0>; + dsa,member = <0 0>; reg = <0x10>; + interrupt-parent = <&gpio1>; + interrupts = <13 IRQ_TYPE_LEVEL_LOW>; + ports { #address-cells = <1>; #size-cells = <0>; @@ -319,6 +324,11 @@ marvell,function = "gpio"; }; + swint_pins: swint-pins { + marvell,pins = "mpp45"; + marvell,function = "gpio"; + }; + spi0cs0_pins: spi0cs0-pins { marvell,pins = "mpp25"; marvell,function = "spi0"; From add2d65962977caf23ca2fa21a2457d31b636574 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marek=20Beh=C3=BAn?= Date: Mon, 16 Nov 2020 13:24:22 +0100 Subject: [PATCH 640/799] ARM: dts: turris-omnia: add SFP node MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Turris Omnia has an SFP cage that, together with WAN PHY, is connected to eth2 SerDes via a SerDes multiplexor. When a SFP module is present, the multiplexor switches the SerDes signal from PHY to SFP. Describe the SFP cage, but leave it disabled. Until phylink has support for such configuration, we are leaving it to U-Boot to enable SFP and disable WAN PHY at boot time depending on whether a SFP module is present. Signed-off-by: Marek Behún Fixes: 26ca8b52d6e1 ("ARM: dts: add support for Turris Omnia") Reviewed-by: Andrew Lunn Cc: Russell King - ARM Linux admin Cc: linux-arm-kernel@lists.infradead.org Cc: Uwe Kleine-König Cc: Jason Cooper Cc: Gregory CLEMENT Cc: Andreas Färber Cc: Rob Herring Cc: devicetree@vger.kernel.org Signed-off-by: Gregory CLEMENT --- arch/arm/boot/dts/armada-385-turris-omnia.dts | 30 ++++++++++++++++++- 1 file changed, 29 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/armada-385-turris-omnia.dts b/arch/arm/boot/dts/armada-385-turris-omnia.dts index 7ccebf7d1757..aea07b352d24 100644 --- a/arch/arm/boot/dts/armada-385-turris-omnia.dts +++ b/arch/arm/boot/dts/armada-385-turris-omnia.dts @@ -82,6 +82,24 @@ }; }; }; + + sfp: sfp { + compatible = "sff,sfp"; + i2c-bus = <&sfp_i2c>; + tx-fault-gpios = <&pcawan 0 GPIO_ACTIVE_HIGH>; + tx-disable-gpios = <&pcawan 1 GPIO_ACTIVE_HIGH>; + rate-select0-gpios = <&pcawan 2 GPIO_ACTIVE_HIGH>; + los-gpios = <&pcawan 3 GPIO_ACTIVE_HIGH>; + mod-def0-gpios = <&pcawan 4 GPIO_ACTIVE_LOW>; + maximum-power-milliwatt = <3000>; + + /* + * For now this has to be enabled at boot time by U-Boot when + * a SFP module is present. Read more in the comment in the + * eth2 node below. + */ + status = "disabled"; + }; }; &bm { @@ -126,10 +144,20 @@ /* WAN port */ ð2 { + /* + * eth2 is connected via a multiplexor to both the SFP cage and to + * ethernet-phy@1. The multiplexor switches the signal to SFP cage when + * a SFP module is present, as determined by the mode-def0 GPIO. + * + * Until kernel supports this configuration properly, in case SFP module + * is present, U-Boot has to enable the sfp node above, remove phy + * handle and add managed = "in-band-status" property. + */ status = "okay"; phy-mode = "sgmii"; phy = <&phy1>; phys = <&comphy5 2>; + sfp = <&sfp>; buffer-manager = <&bm>; bm,pool-long = <2>; bm,pool-short = <3>; @@ -195,7 +223,7 @@ /* routed to PCIe2 connector (CN62A) */ }; - i2c@4 { + sfp_i2c: i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; From 91dd42d0e30fdbb250c61d1192af569f07e6ada4 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marek=20Beh=C3=BAn?= Date: Sun, 15 Nov 2020 14:59:21 +0100 Subject: [PATCH 641/799] ARM: dts: turris-omnia: add LED controller node MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Linux now has incomplete support for the LED controller on Turris Omnia: it can set brightness and colors for each LED. The controller can also put these LEDs into HW controlled mode, in which the LEDs are controlled by HW: for example the WAN LED is connected via MCU to the WAN PHY LED pin. The driver does not support these HW controlled modes yet, and on probe puts the LEDs into SW controlled mode. Add node describing the LED controller, but disable it for now. Signed-off-by: Marek Behún Cc: linux-arm-kernel@lists.infradead.org Cc: Uwe Kleine-König Cc: Jason Cooper Cc: Gregory CLEMENT Cc: Andreas Färber Cc: Rob Herring Cc: devicetree@vger.kernel.org Signed-off-by: Gregory CLEMENT --- arch/arm/boot/dts/armada-385-turris-omnia.dts | 111 +++++++++++++++++- 1 file changed, 110 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/armada-385-turris-omnia.dts b/arch/arm/boot/dts/armada-385-turris-omnia.dts index aea07b352d24..3c80f0beb09c 100644 --- a/arch/arm/boot/dts/armada-385-turris-omnia.dts +++ b/arch/arm/boot/dts/armada-385-turris-omnia.dts @@ -12,6 +12,7 @@ #include #include +#include #include "armada-385.dtsi" / { @@ -181,7 +182,115 @@ reg = <0>; /* STM32F0 command interface at address 0x2a */ - /* leds device (in STM32F0) at address 0x2b */ + + led-controller@2b { + compatible = "cznic,turris-omnia-leds"; + reg = <0x2b>; + #address-cells = <1>; + #size-cells = <0>; + + /* + * LEDs are controlled by MCU (STM32F0) at + * address 0x2b. + * + * The driver does not support HW control mode + * for the LEDs yet. Disable the LEDs for now. + * + * Also LED functions are not stable yet: + * - there are 3 LEDs connected via MCU to PCIe + * ports. One of these ports supports mSATA. + * There is no mSATA nor PCIe function. + * For now we use LED_FUNCTION_WLAN, since + * in most cases users have wifi cards in + * these slots + * - there are 2 LEDs dedicated for user: A and + * B. Again there is no such function defined. + * For now we use LED_FUNCTION_INDICATOR + */ + status = "disabled"; + + multi-led@0 { + reg = <0x0>; + color = ; + function = LED_FUNCTION_INDICATOR; + function-enumerator = <2>; + }; + + multi-led@1 { + reg = <0x1>; + color = ; + function = LED_FUNCTION_INDICATOR; + function-enumerator = <1>; + }; + + multi-led@2 { + reg = <0x2>; + color = ; + function = LED_FUNCTION_WLAN; + function-enumerator = <3>; + }; + + multi-led@3 { + reg = <0x3>; + color = ; + function = LED_FUNCTION_WLAN; + function-enumerator = <2>; + }; + + multi-led@4 { + reg = <0x4>; + color = ; + function = LED_FUNCTION_WLAN; + function-enumerator = <1>; + }; + + multi-led@5 { + reg = <0x5>; + color = ; + function = LED_FUNCTION_WAN; + }; + + multi-led@6 { + reg = <0x6>; + color = ; + function = LED_FUNCTION_LAN; + function-enumerator = <4>; + }; + + multi-led@7 { + reg = <0x7>; + color = ; + function = LED_FUNCTION_LAN; + function-enumerator = <3>; + }; + + multi-led@8 { + reg = <0x8>; + color = ; + function = LED_FUNCTION_LAN; + function-enumerator = <2>; + }; + + multi-led@9 { + reg = <0x9>; + color = ; + function = LED_FUNCTION_LAN; + function-enumerator = <1>; + }; + + multi-led@a { + reg = <0xa>; + color = ; + function = LED_FUNCTION_LAN; + function-enumerator = <0>; + }; + + multi-led@b { + reg = <0xb>; + color = ; + function = LED_FUNCTION_POWER; + }; + }; eeprom@54 { compatible = "atmel,24c64"; From 8ee4a5f4f40da60bb85e13d9dd218a3c9197e3e3 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marek=20Beh=C3=BAn?= Date: Sun, 15 Nov 2020 14:59:22 +0100 Subject: [PATCH 642/799] ARM: dts: turris-omnia: update ethernet-phy node and handle name MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Use property name `phy-handle` instead of the deprecated `phy` to connect eth2 to the PHY. Rename the node from "phy@1" to "ethernet-phy@1", since "phy@1" is incorrect according to device-tree bindings documentation. Also remove the "ethernet-phy-id0141.0DD1" compatible string, it is not needed. Kernel can read the PHY identifier itself. Signed-off-by: Marek Behún Reviewed-by: Andrew Lunn Cc: linux-arm-kernel@lists.infradead.org Cc: Uwe Kleine-König Cc: Jason Cooper Cc: Gregory CLEMENT Cc: Andreas Färber Cc: Rob Herring Cc: devicetree@vger.kernel.org Signed-off-by: Gregory CLEMENT --- arch/arm/boot/dts/armada-385-turris-omnia.dts | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/armada-385-turris-omnia.dts b/arch/arm/boot/dts/armada-385-turris-omnia.dts index 3c80f0beb09c..77bbd1ad3328 100644 --- a/arch/arm/boot/dts/armada-385-turris-omnia.dts +++ b/arch/arm/boot/dts/armada-385-turris-omnia.dts @@ -156,7 +156,7 @@ */ status = "okay"; phy-mode = "sgmii"; - phy = <&phy1>; + phy-handle = <&phy1>; phys = <&comphy5 2>; sfp = <&sfp>; buffer-manager = <&bm>; @@ -387,9 +387,9 @@ pinctrl-0 = <&mdio_pins>; status = "okay"; - phy1: phy@1 { + phy1: ethernet-phy@1 { status = "okay"; - compatible = "ethernet-phy-id0141.0DD1", "ethernet-phy-ieee802.3-c22"; + compatible = "ethernet-phy-ieee802.3-c22"; reg = <1>; /* irq is connected to &pcawan pin 7 */ From 983b95e9ab76766a5a13ed64b5b0fe716b80e939 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marek=20Beh=C3=BAn?= Date: Sun, 15 Nov 2020 14:59:23 +0100 Subject: [PATCH 643/799] ARM: dts: turris-omnia: remove unneeded status = "okay" properties MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Only nodes which have status = "disabled" defined from included files need status = "okay". The ethernet-phy node and the i2cmux node do not need it, since they are wholly defined here. Signed-off-by: Marek Behún Cc: linux-arm-kernel@lists.infradead.org Cc: Uwe Kleine-König Cc: Jason Cooper Cc: Gregory CLEMENT Cc: Andreas Färber Cc: Andrew Lunn Cc: Rob Herring Cc: devicetree@vger.kernel.org Signed-off-by: Gregory CLEMENT --- arch/arm/boot/dts/armada-385-turris-omnia.dts | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm/boot/dts/armada-385-turris-omnia.dts b/arch/arm/boot/dts/armada-385-turris-omnia.dts index 77bbd1ad3328..646a06420c77 100644 --- a/arch/arm/boot/dts/armada-385-turris-omnia.dts +++ b/arch/arm/boot/dts/armada-385-turris-omnia.dts @@ -174,7 +174,6 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x70>; - status = "okay"; i2c@0 { #address-cells = <1>; @@ -388,7 +387,6 @@ status = "okay"; phy1: ethernet-phy@1 { - status = "okay"; compatible = "ethernet-phy-ieee802.3-c22"; reg = <1>; From 06bccda2c13c07d4ac7ebfef766a968c788cbdbf Mon Sep 17 00:00:00 2001 From: Johan Jonker Date: Mon, 16 Nov 2020 16:07:56 +0100 Subject: [PATCH 644/799] ARM: dts: rockchip: rename wdt nodename to watchdog on rv1108 A test with the command below gives for example this error: /arch/arm/boot/dts/rv1108-evb.dt.yaml: wdt@10360000: $nodename:0: 'wdt@10360000' does not match '^watchdog(@.*|-[0-9a-f])?$' Fix it by renaming the wdt nodename to watchdog in the rv1108.dtsi file. make ARCH=arm dtbs_check DT_SCHEMA_FILES=Documentation/devicetree/bindings/watchdog/snps,dw-wdt.yaml Signed-off-by: Johan Jonker Link: https://lore.kernel.org/r/20201116150756.14265-1-jbx6244@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rv1108.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/rv1108.dtsi b/arch/arm/boot/dts/rv1108.dtsi index a1a08cb9364e..e491964b1c3d 100644 --- a/arch/arm/boot/dts/rv1108.dtsi +++ b/arch/arm/boot/dts/rv1108.dtsi @@ -299,7 +299,7 @@ clock-names = "timer", "pclk"; }; - watchdog: wdt@10360000 { + watchdog: watchdog@10360000 { compatible = "snps,dw-wdt"; reg = <0x10360000 0x100>; interrupts = ; From 09ff4e90e041485f7562d9baec340a9824af4f45 Mon Sep 17 00:00:00 2001 From: Faiz Abbas Date: Sun, 29 Nov 2020 23:22:22 +0530 Subject: [PATCH 645/799] arm64: dts: ti: k3-j721e-main: Add output tap delay values Add output tap delay values as given in the latest Data Manual[1], SPRSP36E, revised December 2019. [1] https://www.ti.com/lit/gpn/tda4vm Signed-off-by: Faiz Abbas Signed-off-by: Sekhar Nori Signed-off-by: Nishanth Menon Link: https://lore.kernel.org/r/20201129175223.21751-2-nsekhar@ti.com --- arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 20 +++++++++++++++++--- 1 file changed, 17 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi index 4e189b34a99e..556bc317b866 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi @@ -1080,7 +1080,11 @@ bus-width = <8>; mmc-hs400-1_8v; mmc-ddr-1_8v; - ti,otap-del-sel = <0x2>; + ti,otap-del-sel-legacy = <0xf>; + ti,otap-del-sel-mmc-hs = <0xf>; + ti,otap-del-sel-ddr52 = <0x5>; + ti,otap-del-sel-hs200 = <0x6>; + ti,otap-del-sel-hs400 = <0x0>; ti,trm-icp = <0x8>; ti,strobe-sel = <0x77>; dma-coherent; @@ -1095,7 +1099,12 @@ clocks = <&k3_clks 92 0>, <&k3_clks 92 5>; assigned-clocks = <&k3_clks 92 0>; assigned-clock-parents = <&k3_clks 92 1>; - ti,otap-del-sel = <0x2>; + ti,otap-del-sel-legacy = <0x0>; + ti,otap-del-sel-sd-hs = <0xf>; + ti,otap-del-sel-sdr12 = <0xf>; + ti,otap-del-sel-sdr25 = <0xf>; + ti,otap-del-sel-sdr50 = <0xc>; + ti,otap-del-sel-ddr50 = <0xc>; ti,trm-icp = <0x8>; ti,clkbuf-sel = <0x7>; dma-coherent; @@ -1111,7 +1120,12 @@ clocks = <&k3_clks 93 0>, <&k3_clks 93 5>; assigned-clocks = <&k3_clks 93 0>; assigned-clock-parents = <&k3_clks 93 1>; - ti,otap-del-sel = <0x2>; + ti,otap-del-sel-legacy = <0x0>; + ti,otap-del-sel-sd-hs = <0xf>; + ti,otap-del-sel-sdr12 = <0xf>; + ti,otap-del-sel-sdr25 = <0xf>; + ti,otap-del-sel-sdr50 = <0xc>; + ti,otap-del-sel-ddr50 = <0xc>; ti,trm-icp = <0x8>; ti,clkbuf-sel = <0x7>; dma-coherent; From cd48ce86a4d0c1ffec86aa46a26da993c9af5f53 Mon Sep 17 00:00:00 2001 From: Faiz Abbas Date: Sun, 29 Nov 2020 23:22:23 +0530 Subject: [PATCH 646/799] arm64: dts: ti: k3-j721e-common-proc-board: Add support for SD card UHS modes Add support for UHS modes for the SD card connected at sdhci1. This involves adding regulators for voltage switching and power cycling the SD card and removing the no-1-8-v property. Signed-off-by: Faiz Abbas Signed-off-by: Sekhar Nori Signed-off-by: Nishanth Menon Link: https://lore.kernel.org/r/20201129175223.21751-3-nsekhar@ti.com --- .../dts/ti/k3-j721e-common-proc-board.dts | 33 +++++++++++++++++++ arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 2 -- 2 files changed, 33 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts index 5754892f8501..60764366e22b 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts @@ -67,6 +67,31 @@ regulator-boot-on; }; + vdd_mmc1: fixedregulator-sd { + compatible = "regulator-fixed"; + regulator-name = "vdd_mmc1"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + enable-active-high; + vin-supply = <&vsys_3v3>; + gpio = <&exp2 2 GPIO_ACTIVE_HIGH>; + }; + + vdd_sd_dv_alt: gpio-regulator-TLV71033 { + compatible = "regulator-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&vdd_sd_dv_alt_pins_default>; + regulator-name = "tlv71033"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + vin-supply = <&vsys_5v0>; + gpios = <&main_gpio0 117 GPIO_ACTIVE_HIGH>; + states = <1800000 0x0>, + <3300000 0x1>; + }; + sound0: sound@0 { compatible = "ti,j721e-cpb-audio"; model = "j721e-cpb"; @@ -106,6 +131,12 @@ >; }; + vdd_sd_dv_alt_pins_default: vdd-sd-dv-alt-pins-default { + pinctrl-single,pins = < + J721E_IOPAD(0x1d8, PIN_INPUT, 7) /* (W4) SPI1_CS1.GPIO0_117 */ + >; + }; + main_usbss0_pins_default: main-usbss0-pins-default { pinctrl-single,pins = < J721E_IOPAD(0x290, PIN_OUTPUT, 0) /* (U6) USB0_DRVVBUS */ @@ -295,6 +326,8 @@ &main_sdhci1 { /* SD/MMC */ + vmmc-supply = <&vdd_mmc1>; + vqmmc-supply = <&vdd_sd_dv_alt>; pinctrl-names = "default"; pinctrl-0 = <&main_mmc1_pins_default>; ti,driver-strength-ohm = <50>; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi index 556bc317b866..b32df591c766 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi @@ -1108,7 +1108,6 @@ ti,trm-icp = <0x8>; ti,clkbuf-sel = <0x7>; dma-coherent; - no-1-8-v; }; main_sdhci2: sdhci@4f98000 { @@ -1129,7 +1128,6 @@ ti,trm-icp = <0x8>; ti,clkbuf-sel = <0x7>; dma-coherent; - no-1-8-v; }; usbss0: cdns-usb@4104000 { From 3f4f3bdadd802dfa1cbb5b905507fdb2e940e830 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Mon, 30 Nov 2020 14:28:14 +0100 Subject: [PATCH 647/799] ARM: dts: rockchip: Add rtc node for VMARC SOM Add the hym8563 rtc found on the rk3288 variant of the VMARC SOM. Signed-off-by: Jagan Teki Link: https://lore.kernel.org/r/20201023181814.220974-2-jagan@amarulasolutions.com [split out of the original patch, as it was a change unrelated to the commit description] Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3288-vmarc-som.dtsi | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/arch/arm/boot/dts/rk3288-vmarc-som.dtsi b/arch/arm/boot/dts/rk3288-vmarc-som.dtsi index 4a373f5aa600..da80bfd5f2d5 100644 --- a/arch/arm/boot/dts/rk3288-vmarc-som.dtsi +++ b/arch/arm/boot/dts/rk3288-vmarc-som.dtsi @@ -231,6 +231,23 @@ }; }; +&i2c1 { + clock-frequency = <400000>; + status = "okay"; + + hym8563: rtc@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + interrupt-parent = <&gpio5>; + interrupts = ; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "hym8563"; + pinctrl-names = "default"; + pinctrl-0 = <&hym8563_int>; + }; +}; + &i2c5 { status = "okay"; }; @@ -245,6 +262,12 @@ }; &pinctrl { + hym8563 { + hym8563_int: hym8563-int { + rockchip,pins = <5 RK_PC3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma { drive-strength = <8>; }; From 29952fea5e85083374d19cb0a33206962e087d5b Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Fri, 23 Oct 2020 23:48:14 +0530 Subject: [PATCH 648/799] ARM: dts: rockchip: Add SDIO0 node for VMARC SOM Rockchip RK3288 and RK3399Pro based VMARC SOM has sdio0 for connecting WiFi/BT devices as a pluggable card via M.2 E-Key. Add associated sdio0 nodes, properties. Signed-off-by: Jagan Teki Link: https://lore.kernel.org/r/20201023181814.220974-2-jagan@amarulasolutions.com [moved the unrelated rtc addition to a separate patch] Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3288-vmarc-som.dtsi | 17 +++++++++++++++ .../dts/rockchip-radxa-dalang-carrier.dtsi | 21 +++++++++++++++++++ .../dts/rockchip/rk3399pro-vmarc-som.dtsi | 16 ++++++++++++++ 3 files changed, 54 insertions(+) diff --git a/arch/arm/boot/dts/rk3288-vmarc-som.dtsi b/arch/arm/boot/dts/rk3288-vmarc-som.dtsi index da80bfd5f2d5..0ae2bd150e37 100644 --- a/arch/arm/boot/dts/rk3288-vmarc-som.dtsi +++ b/arch/arm/boot/dts/rk3288-vmarc-som.dtsi @@ -258,6 +258,7 @@ gpio1830-supply = <&vcc_18>; gpio30-supply = <&vcc_io>; sdcard-supply = <&vccio_sd>; + wifi-supply = <&vcc_wl>; status = "okay"; }; @@ -283,6 +284,12 @@ }; }; + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <4 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + sdmmc { sdmmc_bus4: sdmmc-bus4 { rockchip,pins = @@ -314,6 +321,16 @@ }; }; +&sdio_pwrseq { + /* + * On the module itself this is one of these (depending + * on the actual card populated): + * - SDIO_RESET_L_WL_REG_ON + * - PDN (power down when low) + */ + reset-gpios = <&gpio4 RK_PD4 GPIO_ACTIVE_LOW>; /* WIFI_REG_ON */ +}; + &usbphy { status = "okay"; }; diff --git a/arch/arm/boot/dts/rockchip-radxa-dalang-carrier.dtsi b/arch/arm/boot/dts/rockchip-radxa-dalang-carrier.dtsi index 26b53eac4706..da1d548b7330 100644 --- a/arch/arm/boot/dts/rockchip-radxa-dalang-carrier.dtsi +++ b/arch/arm/boot/dts/rockchip-radxa-dalang-carrier.dtsi @@ -15,6 +15,14 @@ #clock-cells = <0>; }; + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&hym8563>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + }; + vcc12v_dcin: vcc12v-dcin-regulator { compatible = "regulator-fixed"; regulator-name = "vcc12v_dcin"; @@ -78,6 +86,19 @@ status = "okay"; }; +&sdio0 { + bus-width = <4>; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>; + sd-uhs-sdr104; + status = "okay"; +}; + &sdmmc { bus-width = <4>; cap-mmc-highspeed; diff --git a/arch/arm64/boot/dts/rockchip/rk3399pro-vmarc-som.dtsi b/arch/arm64/boot/dts/rockchip/rk3399pro-vmarc-som.dtsi index 5d087be04af8..7257494d2831 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399pro-vmarc-som.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399pro-vmarc-som.dtsi @@ -353,6 +353,12 @@ }; }; + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + vbus_host { usb1_en_oc: usb1-en-oc { rockchip,pins = <4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_up>; @@ -371,6 +377,16 @@ pmu1830-supply = <&vcc_1v8>; }; +&sdio_pwrseq { + /* + * On the module itself this is one of these (depending + * on the actual card populated): + * - SDIO_RESET_L_WL_REG_ON + * - PDN (power down when low) + */ + reset-gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_LOW>; +}; + &sdhci { bus-width = <8>; mmc-hs400-1_8v; From e56ed188c83053a505041e1a8ad4fba0f3b39089 Mon Sep 17 00:00:00 2001 From: Alexis Ballier Date: Thu, 22 Oct 2020 13:35:32 +0200 Subject: [PATCH 649/799] arm64: dts: rockchip: Properly define the type C connector on rk3399-orangepi Tested: - USB3 Gigabit adapter - USB2 mass storage The wiring is the same as the pinebook pro according to the schematics, thus this patch is heavily based on its dts. Signed-off-by: Alexis Ballier Cc: devicetree@vger.kernel.org Cc: Heiko Stuebner Cc: linux-arm-kernel@lists.infradead.org Cc: linux-rockchip@lists.infradead.org Cc: linux-kernel@vger.kernel.org Link: https://lore.kernel.org/r/20201022113532.18470-1-aballier@gentoo.org Signed-off-by: Heiko Stuebner --- .../boot/dts/rockchip/rk3399-orangepi.dts | 62 ++++++++++++++++++- 1 file changed, 61 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3399-orangepi.dts b/arch/arm64/boot/dts/rockchip/rk3399-orangepi.dts index 6163ae8063a7..ad7c4d00888f 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-orangepi.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-orangepi.dts @@ -7,6 +7,7 @@ #include "dt-bindings/pwm/pwm.h" #include "dt-bindings/input/input.h" +#include "dt-bindings/usb/pd.h" #include "rk3399.dtsi" #include "rk3399-opp.dtsi" @@ -531,6 +532,43 @@ pinctrl-names = "default"; pinctrl-0 = <&chg_cc_int_l>; vbus-supply = <&vbus_typec>; + + typec_con: connector { + compatible = "usb-c-connector"; + data-role = "host"; + label = "USB-C"; + op-sink-microwatt = <1000000>; + power-role = "dual"; + sink-pdos = + ; + source-pdos = + ; + try-power-role = "sink"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + typec_hs: endpoint { + remote-endpoint = <&u2phy0_typec_hs>; + }; + }; + port@1 { + reg = <1>; + typec_ss: endpoint { + remote-endpoint = <&tcphy0_typec_ss>; + }; + }; + port@2 { + reg = <2>; + typec_dp: endpoint { + remote-endpoint = <&tcphy0_typec_dp>; + }; + }; + }; + }; }; }; @@ -717,6 +755,22 @@ status = "okay"; }; +&tcphy0_dp { + port { + tcphy0_typec_dp: endpoint { + remote-endpoint = <&typec_dp>; + }; + }; +}; + +&tcphy0_usb3 { + port { + tcphy0_typec_ss: endpoint { + remote-endpoint = <&typec_ss>; + }; + }; +}; + &tcphy1 { status = "okay"; }; @@ -739,6 +793,12 @@ phy-supply = <&vcc5v0_host>; status = "okay"; }; + + port { + u2phy0_typec_hs: endpoint { + remote-endpoint = <&typec_hs>; + }; + }; }; &u2phy1 { @@ -799,7 +859,7 @@ &usbdrd_dwc3_0 { status = "okay"; - dr_mode = "otg"; + dr_mode = "host"; }; &usbdrd3_1 { From 98ac141b96034c5d79b512c2db61cd4b0442939d Mon Sep 17 00:00:00 2001 From: Serge Semin Date: Wed, 11 Nov 2020 12:15:46 +0300 Subject: [PATCH 650/799] arm: dts: marvell: armada-375: Harmonize DWC USB3 DT nodes name In accordance with the DWC USB3 bindings the corresponding node name is suppose to comply with the Generic USB HCD DT schema, which requires the USB nodes to have the name acceptable by the regexp: "^usb(@.*)?" . Make sure the "snps,dwc3"-compatible nodes are correctly named. Signed-off-by: Serge Semin Acked-by: Krzysztof Kozlowski Signed-off-by: Gregory CLEMENT --- arch/arm/boot/dts/armada-375.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/armada-375.dtsi b/arch/arm/boot/dts/armada-375.dtsi index 9805e507c695..7f2f24a29e6c 100644 --- a/arch/arm/boot/dts/armada-375.dtsi +++ b/arch/arm/boot/dts/armada-375.dtsi @@ -426,7 +426,7 @@ status = "disabled"; }; - usb2: usb3@58000 { + usb2: usb@58000 { compatible = "marvell,armada-375-xhci"; reg = <0x58000 0x20000>,<0x5b880 0x80>; interrupts = ; From 51b632c713d50586a844259c56048a280f375406 Mon Sep 17 00:00:00 2001 From: Aryan Srivastava Date: Thu, 26 Nov 2020 17:45:44 +1300 Subject: [PATCH 651/799] ARM: dts: mvebu: Add device tree for RD-AC3X-48G4X2XL board Add device tree for RD-AC3X-48G4X2XL board. This has a Armada 382 SoC on a interposer board connected to a baseboard with a Prestera AC3X ASIC connected via PCI. Signed-off-by: Aryan Srivastava Reviewed-by: Chris Packham Reviewed-by: Andrew Lunn Signed-off-by: Gregory CLEMENT --- arch/arm/boot/dts/Makefile | 1 + .../boot/dts/armada-382-rd-ac3x-48g4x2xl.dts | 112 ++++++++++++++++++ 2 files changed, 113 insertions(+) create mode 100644 arch/arm/boot/dts/armada-382-rd-ac3x-48g4x2xl.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index a89548efdd88..0a68c66f4e38 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1319,6 +1319,7 @@ dtb-$(CONFIG_MACH_ARMADA_370) += \ dtb-$(CONFIG_MACH_ARMADA_375) += \ armada-375-db.dtb dtb-$(CONFIG_MACH_ARMADA_38X) += \ + armada-382-rd-ac3x-48g4x2xl.dtb \ armada-385-clearfog-gtr-s4.dtb \ armada-385-clearfog-gtr-l8.dtb \ armada-385-db-88f6820-amc.dtb \ diff --git a/arch/arm/boot/dts/armada-382-rd-ac3x-48g4x2xl.dts b/arch/arm/boot/dts/armada-382-rd-ac3x-48g4x2xl.dts new file mode 100644 index 000000000000..584f0d0398a5 --- /dev/null +++ b/arch/arm/boot/dts/armada-382-rd-ac3x-48g4x2xl.dts @@ -0,0 +1,112 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Device Tree file for Marvell Armada 382 reference board + * (RD-AC3X-48G4X2XL) + * + * Copyright (C) 2020 Allied Telesis Labs + */ + +/dts-v1/; +#include "armada-385.dtsi" + +#include + +/ { + model = "Marvell Armada 382 RD-AC3X"; + compatible = "marvell,rd-ac3x-48g4x2xl", "marvell,rd-ac3x", + "marvell,armada385", "marvell,armada380"; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + aliases { + ethernet0 = ð1; + }; + + memory { + device_type = "memory"; + reg = <0x00000000 0x20000000>; /* 512MB */ + }; + + soc { + ranges = ; + }; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + status = "okay"; + + eeprom@53{ + compatible = "atmel,24c64"; + reg = <0x53>; + }; + + /* CPLD device present at 0x3c. Function unknown */ +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; + status = "okay"; +}; + +ð1 { + status = "okay"; + phy = <&phy0>; + phy-mode = "rgmii-id"; +}; + +&mdio { + pinctrl-names = "default"; + pinctrl-0 = <&mdio_pins>; + + phy0: ethernet-phy@0 { + reg = <0>; + }; +}; + +&pciec { + status = "okay"; +}; + +&pcie1 { + /* Port 0, Lane 0 */ + status = "okay"; +}; + +&nand_controller { + status = "okay"; + + nand@0 { + reg = <0>; + label = "pxa3xx_nand-0"; + nand-rb = <0>; + nand-on-flash-bbt; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + partition@0 { + reg = <0x00000000 0x00500000>; + label = "u-boot"; + }; + partition@500000{ + reg = <0x00500000 0x00400000>; + label = "u-boot env"; + }; + partition@900000{ + reg = <0x00900000 0x3F700000>; + label = "user"; + }; + }; + }; +}; + +&refclk { + clock-frequency = <200000000>; +}; From 60a9d6ab2fdd5cac6366eb27de2469c7abee5696 Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Sat, 31 Oct 2020 07:31:14 -0500 Subject: [PATCH 652/799] arm64: dts: imx8mm-beacon-som: Fix whitespace issue The pinmux subnodes are indented too much. This patch does nothing more than remove an extra tab. There are no functional changes. Signed-off-by: Adam Ford Signed-off-by: Shawn Guo --- .../boot/dts/freescale/imx8mm-beacon-som.dtsi | 296 +++++++++--------- 1 file changed, 148 insertions(+), 148 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi index c74e006ad0e8..6b53830ddf74 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi @@ -284,166 +284,166 @@ }; &iomuxc { - pinctrl_fec1: fec1grp { - fsl,pins = < - MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3 - MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 - MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f - MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f - MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f - MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f - MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 - MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 - MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 - MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 - MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f - MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 - MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 - MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f - MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19 - >; - }; + pinctrl_fec1: fec1grp { + fsl,pins = < + MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3 + MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 + MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f + MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f + MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f + MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f + MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 + MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 + MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 + MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 + MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f + MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 + MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 + MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f + MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19 + >; + }; - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 - MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 - >; - }; + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 + MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 + >; + }; - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 - MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 - >; - }; + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 + MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 + >; + }; - pinctrl_flexspi: flexspigrp { - fsl,pins = < - MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c2 - MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82 - MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82 - MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82 - MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82 - MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82 - >; - }; + pinctrl_flexspi: flexspigrp { + fsl,pins = < + MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c2 + MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82 + MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82 + MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82 + MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82 + MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82 + >; + }; - pinctrl_pmic: pmicirqgrp { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x141 - >; - }; + pinctrl_pmic: pmicirqgrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x141 + >; + }; - pinctrl_uart1: uart1grp { - fsl,pins = < - MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140 - MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140 - MX8MM_IOMUXC_UART3_RXD_UART1_DCE_CTS_B 0x140 - MX8MM_IOMUXC_UART3_TXD_UART1_DCE_RTS_B 0x140 - MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6 0x19 - MX8MM_IOMUXC_SD1_DATA5_GPIO2_IO7 0x19 - MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8 0x19 - MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x141 - >; - }; + pinctrl_uart1: uart1grp { + fsl,pins = < + MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140 + MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140 + MX8MM_IOMUXC_UART3_RXD_UART1_DCE_CTS_B 0x140 + MX8MM_IOMUXC_UART3_TXD_UART1_DCE_RTS_B 0x140 + MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6 0x19 + MX8MM_IOMUXC_SD1_DATA5_GPIO2_IO7 0x19 + MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8 0x19 + MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x141 + >; + }; - pinctrl_usdhc1_gpio: usdhc1gpiogrp { - fsl,pins = < - MX8MM_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x41 - >; - }; + pinctrl_usdhc1_gpio: usdhc1gpiogrp { + fsl,pins = < + MX8MM_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x41 + >; + }; - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190 - MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0 - MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0 - MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0 - MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0 - MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0 - >; - }; + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190 + MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0 + MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0 + MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0 + MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0 + MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0 + >; + }; - pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { - fsl,pins = < - MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x194 - MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4 - MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4 - MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4 - MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4 - MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4 - >; - }; + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { + fsl,pins = < + MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x194 + MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4 + MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4 + MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4 + MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4 + MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4 + >; + }; - pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { - fsl,pins = < - MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x196 - MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6 - MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6 - MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6 - MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6 - MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6 - >; - }; + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { + fsl,pins = < + MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x196 + MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6 + MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6 + MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6 + MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6 + MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6 + >; + }; - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190 - MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 - MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 - MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 - MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 - MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 - MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 - MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 - MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 - MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 - MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 - >; - }; + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190 + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 + MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 + MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 + MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 + MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 + MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 + >; + }; - pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { - fsl,pins = < - MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194 - MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 - MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 - MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 - MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 - MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 - MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 - MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 - MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 - MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 - MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 - >; - }; + pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { + fsl,pins = < + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194 + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 + MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 + MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 + MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 + MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 + MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 + >; + }; - pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { - fsl,pins = < - MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196 - MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 - MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 - MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 - MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 - MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 - MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 - MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 - MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 - MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 - MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 - >; - }; + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { + fsl,pins = < + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196 + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 + MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 + MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 + MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 + MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 + MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 + >; + }; - pinctrl_wdog: wdoggrp { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x166 - >; - }; + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x166 + >; + }; - pinctrl_wlan: wlangrp { - fsl,pins = < - MX8MM_IOMUXC_SD1_DATA7_GPIO2_IO9 0x111 - >; - }; + pinctrl_wlan: wlangrp { + fsl,pins = < + MX8MM_IOMUXC_SD1_DATA7_GPIO2_IO9 0x111 + >; + }; }; From 87f7ba165168ee0bff0baf6ded6d4dfa5bba1217 Mon Sep 17 00:00:00 2001 From: Meenakshi Aggarwal Date: Mon, 2 Nov 2020 11:29:41 +0530 Subject: [PATCH 653/799] arm64: dts: lx2160a: add device tree for lx2162aqds board Add device tree support for LX2162AQDS board. LX2162A has same die as of LX2160A with different packaging. Signed-off-by: Ioana Ciornei Signed-off-by: Kuldeep Singh Signed-off-by: Meenakshi Aggarwal Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/Makefile | 1 + .../boot/dts/freescale/fsl-lx2162a-qds.dts | 334 ++++++++++++++++++ 2 files changed, 335 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/fsl-lx2162a-qds.dts diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index e43254f1294d..876bf484bbe6 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -27,6 +27,7 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-clearfog-cx.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-honeycomb.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-qds.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-rdb.dtb +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2162a-qds.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-beacon-kit.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-evk.dtb diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2162a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-lx2162a-qds.dts new file mode 100644 index 000000000000..91786848bd30 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-lx2162a-qds.dts @@ -0,0 +1,334 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +// +// Device Tree file for LX2162AQDS +// +// Copyright 2020 NXP + +/dts-v1/; + +#include "fsl-lx2160a.dtsi" + +/ { + model = "NXP Layerscape LX2162AQDS"; + compatible = "fsl,lx2162a-qds", "fsl,lx2160a"; + + aliases { + crypto = &crypto; + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + sb_3v3: regulator-sb3v3 { + compatible = "regulator-fixed"; + regulator-name = "LTM4619-3.3VSB"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + mdio-mux-1 { + compatible = "mdio-mux-multiplexer"; + mux-controls = <&mux 0>; + mdio-parent-bus = <&emdio1>; + #address-cells=<1>; + #size-cells = <0>; + + mdio@0 { /* On-board RTL8211F PHY #1 RGMII1 */ + reg = <0x00>; + #address-cells = <1>; + #size-cells = <0>; + + rgmii_phy1: ethernet-phy@1 { + compatible = "ethernet-phy-id001c.c916"; + reg = <0x1>; + eee-broken-1000t; + }; + }; + + mdio@8 { /* On-board RTL8211F PHY #2 RGMII2 */ + reg = <0x8>; + #address-cells = <1>; + #size-cells = <0>; + + rgmii_phy2: ethernet-phy@2 { + compatible = "ethernet-phy-id001c.c916"; + reg = <0x2>; + eee-broken-1000t; + }; + }; + + mdio@18 { /* Slot #1 */ + reg = <0x18>; + #address-cells = <1>; + #size-cells = <0>; + }; + + mdio@19 { /* Slot #2 */ + reg = <0x19>; + #address-cells = <1>; + #size-cells = <0>; + }; + + mdio@1a { /* Slot #3 */ + reg = <0x1a>; + #address-cells = <1>; + #size-cells = <0>; + }; + + mdio@1b { /* Slot #4 */ + reg = <0x1b>; + #address-cells = <1>; + #size-cells = <0>; + }; + + mdio@1c { /* Slot #5 */ + reg = <0x1c>; + #address-cells = <1>; + #size-cells = <0>; + }; + + mdio@1d { /* Slot #6 */ + reg = <0x1d>; + #address-cells = <1>; + #size-cells = <0>; + }; + + mdio@1e { /* Slot #7 */ + reg = <0x1e>; + #address-cells = <1>; + #size-cells = <0>; + }; + + mdio@1f { /* Slot #8 */ + reg = <0x1f>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + mdio-mux-2 { + compatible = "mdio-mux-multiplexer"; + mux-controls = <&mux 1>; + mdio-parent-bus = <&emdio2>; + #address-cells=<1>; + #size-cells = <0>; + + mdio@0 { /* Slot #1 (secondary EMI) */ + reg = <0x00>; + #address-cells = <1>; + #size-cells = <0>; + }; + + mdio@1 { /* Slot #2 (secondary EMI) */ + reg = <0x01>; + #address-cells = <1>; + #size-cells = <0>; + }; + + mdio@2 { /* Slot #3 (secondary EMI) */ + reg = <0x02>; + #address-cells = <1>; + #size-cells = <0>; + }; + + mdio@3 { /* Slot #4 (secondary EMI) */ + reg = <0x03>; + #address-cells = <1>; + #size-cells = <0>; + }; + + mdio@4 { /* Slot #5 (secondary EMI) */ + reg = <0x04>; + #address-cells = <1>; + #size-cells = <0>; + }; + + mdio@5 { /* Slot #6 (secondary EMI) */ + reg = <0x05>; + #address-cells = <1>; + #size-cells = <0>; + }; + + mdio@6 { /* Slot #7 (secondary EMI) */ + reg = <0x06>; + #address-cells = <1>; + #size-cells = <0>; + }; + + mdio@7 { /* Slot #8 (secondary EMI) */ + reg = <0x07>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; +}; + +&crypto { + status = "okay"; +}; + +&dpmac17 { + phy-handle = <&rgmii_phy1>; + phy-connection-type = "rgmii-id"; +}; + +&dpmac18 { + phy-handle = <&rgmii_phy2>; + phy-connection-type = "rgmii-id"; +}; + +&dspi0 { + status = "okay"; + + dflash0: flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <1000000>; + }; +}; + +&dspi1 { + status = "okay"; + + dflash1: flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <1000000>; + }; +}; + +&dspi2 { + status = "okay"; + + dflash2: flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <1000000>; + }; +}; + +&emdio1 { + status = "okay"; +}; + +&emdio2 { + status = "okay"; +}; + +&esdhc0 { + status = "okay"; +}; + +&esdhc1 { + status = "okay"; +}; + +&fspi { + status = "okay"; + + mt35xu512aba0: flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + m25p,fast-read; + spi-max-frequency = <50000000>; + reg = <0>; + spi-rx-bus-width = <8>; + spi-tx-bus-width = <8>; + }; +}; + +&i2c0 { + status = "okay"; + + fpga@66 { + compatible = "fsl,lx2160aqds-fpga", "fsl,fpga-qixis-i2c", + "simple-mfd"; + reg = <0x66>; + + mux: mux-controller { + compatible = "reg-mux"; + #mux-control-cells = <1>; + mux-reg-masks = <0x54 0xf8>, /* 0: reg 0x54, bits 7:3 */ + <0x54 0x07>; /* 1: reg 0x54, bit 2:0 */ + }; + }; + + i2c-mux@77 { + compatible = "nxp,pca9547"; + reg = <0x77>; + #address-cells = <1>; + #size-cells = <0>; + + i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x2>; + + power-monitor@40 { + compatible = "ti,ina220"; + reg = <0x40>; + shunt-resistor = <500>; + }; + + power-monitor@41 { + compatible = "ti,ina220"; + reg = <0x41>; + shunt-resistor = <1000>; + }; + }; + + i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x3>; + + temperature-sensor@4c { + compatible = "nxp,sa56004"; + reg = <0x4c>; + vcc-supply = <&sb_3v3>; + }; + + rtc@51 { + compatible = "nxp,pcf2129"; + reg = <0x51>; + }; + }; + }; +}; + +&sata0 { + status = "okay"; +}; + +&sata1 { + status = "okay"; +}; + +&sata2 { + status = "okay"; +}; + +&sata3 { + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&usb0 { + status = "okay"; +}; From bbe75af7b092f2d15a146328c107a3ebb5d1e25f Mon Sep 17 00:00:00 2001 From: Ioana Ciornei Date: Fri, 30 Oct 2020 13:35:47 +0200 Subject: [PATCH 654/799] arm64: dts: ls1088a: add external MDIO device nodes Add the external MDIO device nodes found in the WRIOP global memory region. This is needed for management of external PHYs. Signed-off-by: Ioana Ciornei Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi index b2c5189e59fa..42563c9c9e04 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi @@ -672,6 +672,24 @@ fsl,extts-fifo; }; + emdio1: mdio@8b96000 { + compatible = "fsl,fman-memac-mdio"; + reg = <0x0 0x8b96000 0x0 0x1000>; + little-endian; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + emdio2: mdio@8b97000 { + compatible = "fsl,fman-memac-mdio"; + reg = <0x0 0x8b97000 0x0 0x1000>; + little-endian; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + cluster1_core0_watchdog: wdt@c000000 { compatible = "arm,sp805-wdt", "arm,primecell"; reg = <0x0 0xc000000 0x0 0x1000>; From 73f034cc45e9bd554003919873066a2acbe0cf22 Mon Sep 17 00:00:00 2001 From: Ioana Ciornei Date: Fri, 30 Oct 2020 13:35:48 +0200 Subject: [PATCH 655/799] arm64: dts: ls1088ardb: add QSGMII PHY nodes Annotate the external MDIO1 node and describe the 8 QSGMII PHYs found on the LS1088ARDB board and add phy-handles for DPMACs 3-10 to its associated PHY. Also, add the internal PCS MDIO nodes for the internal MDIO buses found on the LS1088A SoC along with their internal PCS PHY and link the corresponding DPMAC to the PCS through the pcs-handle. Also, rename the dpmac@x nodes to ethernet@x in order to be compliant with the naming convention used by ethernet controllers. Signed-off-by: Ioana Ciornei Signed-off-by: Shawn Guo --- .../boot/dts/freescale/fsl-ls1088a-rdb.dts | 100 ++++++++++++++++++ .../arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 70 ++++++++++-- 2 files changed, 160 insertions(+), 10 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts index 5633e59febc3..e28443ba2633 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts @@ -17,6 +17,98 @@ compatible = "fsl,ls1088a-rdb", "fsl,ls1088a"; }; +&dpmac3 { + phy-handle = <&mdio1_phy5>; + phy-connection-type = "qsgmii"; + managed = "in-band-status"; + pcs-handle = <&pcs3_0>; +}; + +&dpmac4 { + phy-handle = <&mdio1_phy6>; + phy-connection-type = "qsgmii"; + managed = "in-band-status"; + pcs-handle = <&pcs3_1>; +}; + +&dpmac5 { + phy-handle = <&mdio1_phy7>; + phy-connection-type = "qsgmii"; + managed = "in-band-status"; + pcs-handle = <&pcs3_2>; +}; + +&dpmac6 { + phy-handle = <&mdio1_phy8>; + phy-connection-type = "qsgmii"; + managed = "in-band-status"; + pcs-handle = <&pcs3_3>; +}; + +&dpmac7 { + phy-handle = <&mdio1_phy1>; + phy-connection-type = "qsgmii"; + managed = "in-band-status"; + pcs-handle = <&pcs7_0>; +}; + +&dpmac8 { + phy-handle = <&mdio1_phy2>; + phy-connection-type = "qsgmii"; + managed = "in-band-status"; + pcs-handle = <&pcs7_1>; +}; + +&dpmac9 { + phy-handle = <&mdio1_phy3>; + phy-connection-type = "qsgmii"; + managed = "in-band-status"; + pcs-handle = <&pcs7_2>; +}; + +&dpmac10 { + phy-handle = <&mdio1_phy4>; + phy-connection-type = "qsgmii"; + managed = "in-band-status"; + pcs-handle = <&pcs7_3>; +}; + +&emdio1 { + status = "okay"; + + mdio1_phy5: ethernet-phy@c { + reg = <0xc>; + }; + + mdio1_phy6: ethernet-phy@d { + reg = <0xd>; + }; + + mdio1_phy7: ethernet-phy@e { + reg = <0xe>; + }; + + mdio1_phy8: ethernet-phy@f { + reg = <0xf>; + }; + + mdio1_phy1: ethernet-phy@1c { + reg = <0x1c>; + }; + + mdio1_phy2: ethernet-phy@1d { + reg = <0x1d>; + }; + + mdio1_phy3: ethernet-phy@1e { + reg = <0x1e>; + }; + + mdio1_phy4: ethernet-phy@1f { + reg = <0x1f>; + }; +}; + &i2c0 { status = "okay"; @@ -87,6 +179,14 @@ status = "okay"; }; +&pcs_mdio3 { + status = "okay"; +}; + +&pcs_mdio7 { + status = "okay"; +}; + &qspi { status = "okay"; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi index 42563c9c9e04..80ed64cdb73e 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi @@ -690,6 +690,56 @@ status = "disabled"; }; + pcs_mdio3: mdio@8c0f000 { + compatible = "fsl,fman-memac-mdio"; + reg = <0x0 0x8c0f000 0x0 0x1000>; + little-endian; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + pcs3_0: ethernet-phy@0 { + reg = <0>; + }; + + pcs3_1: ethernet-phy@1 { + reg = <1>; + }; + + pcs3_2: ethernet-phy@2 { + reg = <2>; + }; + + pcs3_3: ethernet-phy@3 { + reg = <3>; + }; + }; + + pcs_mdio7: mdio@8c1f000 { + compatible = "fsl,fman-memac-mdio"; + reg = <0x0 0x8c1f000 0x0 0x1000>; + little-endian; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + pcs7_0: ethernet-phy@0 { + reg = <0>; + }; + + pcs7_1: ethernet-phy@1 { + reg = <1>; + }; + + pcs7_2: ethernet-phy@2 { + reg = <2>; + }; + + pcs7_3: ethernet-phy@3 { + reg = <3>; + }; + }; + cluster1_core0_watchdog: wdt@c000000 { compatible = "arm,sp805-wdt", "arm,primecell"; reg = <0x0 0xc000000 0x0 0x1000>; @@ -767,52 +817,52 @@ #address-cells = <1>; #size-cells = <0>; - dpmac1: dpmac@1 { + dpmac1: ethernet@1 { compatible = "fsl,qoriq-mc-dpmac"; reg = <1>; }; - dpmac2: dpmac@2 { + dpmac2: ethernet@2 { compatible = "fsl,qoriq-mc-dpmac"; reg = <2>; }; - dpmac3: dpmac@3 { + dpmac3: ethernet@3 { compatible = "fsl,qoriq-mc-dpmac"; reg = <3>; }; - dpmac4: dpmac@4 { + dpmac4: ethernet@4 { compatible = "fsl,qoriq-mc-dpmac"; reg = <4>; }; - dpmac5: dpmac@5 { + dpmac5: ethernet@5 { compatible = "fsl,qoriq-mc-dpmac"; reg = <5>; }; - dpmac6: dpmac@6 { + dpmac6: ethernet@6 { compatible = "fsl,qoriq-mc-dpmac"; reg = <6>; }; - dpmac7: dpmac@7 { + dpmac7: ethernet@7 { compatible = "fsl,qoriq-mc-dpmac"; reg = <7>; }; - dpmac8: dpmac@8 { + dpmac8: ethernet@8 { compatible = "fsl,qoriq-mc-dpmac"; reg = <8>; }; - dpmac9: dpmac@9 { + dpmac9: ethernet@9 { compatible = "fsl,qoriq-mc-dpmac"; reg = <9>; }; - dpmac10: dpmac@a { + dpmac10: ethernet@a { compatible = "fsl,qoriq-mc-dpmac"; reg = <0xa>; }; From 379b4f764563c094c00aa547c1ff8f4aeda72e23 Mon Sep 17 00:00:00 2001 From: Ioana Ciornei Date: Fri, 30 Oct 2020 13:35:49 +0200 Subject: [PATCH 656/799] arm64: dts: ls1088ardb: add necessary DTS nodes for DPMAC2 Annotate the external MDIO2 node and describe the 10GBASER PHY found on the LS1088ARDB board and add a phy-handle for DPMAC2 to link it. Also, add the internal PCS MDIO node for the internal MDIO buses found on the LS1088A SoC along with its internal PCS PHY and link the corresponding DPMAC to the PCS through the pcs-handle. Signed-off-by: Ioana Ciornei Signed-off-by: Shawn Guo --- .../boot/dts/freescale/fsl-ls1088a-rdb.dts | 19 +++++++++++++++++++ .../arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 13 +++++++++++++ 2 files changed, 32 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts index e28443ba2633..528ec72d0b83 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts @@ -17,6 +17,12 @@ compatible = "fsl,ls1088a-rdb", "fsl,ls1088a"; }; +&dpmac2 { + phy-handle = <&mdio2_aquantia_phy>; + phy-connection-type = "10gbase-r"; + pcs-handle = <&pcs2>; +}; + &dpmac3 { phy-handle = <&mdio1_phy5>; phy-connection-type = "qsgmii"; @@ -109,6 +115,15 @@ }; }; +&emdio2 { + status = "okay"; + + mdio2_aquantia_phy: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <0x0>; + }; +}; + &i2c0 { status = "okay"; @@ -179,6 +194,10 @@ status = "okay"; }; +&pcs_mdio2 { + status = "okay"; +}; + &pcs_mdio3 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi index 80ed64cdb73e..9c9c323cc3cd 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi @@ -690,6 +690,19 @@ status = "disabled"; }; + pcs_mdio2: mdio@8c0b000 { + compatible = "fsl,fman-memac-mdio"; + reg = <0x0 0x8c0b000 0x0 0x1000>; + little-endian; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + pcs2: ethernet-phy@0 { + reg = <0>; + }; + }; + pcs_mdio3: mdio@8c0f000 { compatible = "fsl,fman-memac-mdio"; reg = <0x0 0x8c0f000 0x0 0x1000>; From 0420dde30a90534d7272847aea3f55845b3af22c Mon Sep 17 00:00:00 2001 From: Ioana Ciornei Date: Fri, 30 Oct 2020 13:35:50 +0200 Subject: [PATCH 657/799] arm64: dts: ls208xa: add the external MDIO nodes Add the external MDIO device nodes found in the WRIOP global memory region. This is needed for management of external PHYs. Signed-off-by: Ioana Ciornei Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi index 4d3f72d126e7..ba0877d1e261 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi @@ -458,6 +458,24 @@ fsl,extts-fifo; }; + emdio1: mdio@8b96000 { + compatible = "fsl,fman-memac-mdio"; + reg = <0x0 0x8b96000 0x0 0x1000>; + little-endian; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + emdio2: mdio@8b97000 { + compatible = "fsl,fman-memac-mdio"; + reg = <0x0 0x8b97000 0x0 0x1000>; + little-endian; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + fsl_mc: fsl-mc@80c000000 { compatible = "fsl,qoriq-mc"; reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */ From 173fb0a3f9fb3ce416d2cb78476e0406a6db7490 Mon Sep 17 00:00:00 2001 From: Ioana Ciornei Date: Fri, 30 Oct 2020 13:35:51 +0200 Subject: [PATCH 658/799] arm64: dts: ls2088ardb: add PHY nodes for the CS4340 PHYs Annotate the EMDIO1 node and describe the 4 10GBASER PHYs found on the LS2088ARDB board. Also, add phy-handles for DPMACs 1-4 to their associated PHY. Signed-off-by: Ioana Ciornei Signed-off-by: Shawn Guo --- .../boot/dts/freescale/fsl-ls2088a-rdb.dts | 44 +++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2088a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls2088a-rdb.dts index f6b4d75a258b..a4b0dcab6e8e 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls2088a-rdb.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls2088a-rdb.dts @@ -22,3 +22,47 @@ stdout-path = "serial1:115200n8"; }; }; + +&dpmac1 { + phy-handle = <&mdio1_phy1>; + phy-connection-type = "10gbase-r"; +}; + +&dpmac2 { + phy-handle = <&mdio1_phy2>; + phy-connection-type = "10gbase-r"; +}; + +&dpmac3 { + phy-handle = <&mdio1_phy3>; + phy-connection-type = "10gbase-r"; +}; + +&dpmac4 { + phy-handle = <&mdio1_phy4>; + phy-connection-type = "10gbase-r"; +}; + +&emdio1 { + status = "okay"; + + mdio1_phy1: ethernet-phy@10 { + compatible = "ethernet-phy-id13e5.1002"; + reg = <0x10>; + }; + + mdio1_phy2: ethernet-phy@11 { + compatible = "ethernet-phy-id13e5.1002"; + reg = <0x11>; + }; + + mdio1_phy3: ethernet-phy@12 { + compatible = "ethernet-phy-id13e5.1002"; + reg = <0x12>; + }; + + mdio1_phy4: ethernet-phy@13 { + compatible = "ethernet-phy-id13e5.1002"; + reg = <0x13>; + }; +}; From dd2ab5c8b81e23847db5477033fc14f9b8783db2 Mon Sep 17 00:00:00 2001 From: Ioana Ciornei Date: Fri, 30 Oct 2020 13:35:52 +0200 Subject: [PATCH 659/799] arm64: dts: ls2088ardb: add PHY nodes for the AQR405 PHYs Annotate the EMDIO2 node and describe the other 4 10GBASER PHYs found on the LS2088ARDB board. Also, add phy-handles for DPMACs 5-8 to their associated PHY. Signed-off-by: Ioana Ciornei Signed-off-by: Shawn Guo --- .../boot/dts/freescale/fsl-ls2088a-rdb.dts | 44 +++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2088a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls2088a-rdb.dts index a4b0dcab6e8e..854f604049ca 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls2088a-rdb.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls2088a-rdb.dts @@ -43,6 +43,26 @@ phy-connection-type = "10gbase-r"; }; +&dpmac5 { + phy-handle = <&mdio2_phy1>; + phy-connection-type = "10gbase-r"; +}; + +&dpmac6 { + phy-handle = <&mdio2_phy2>; + phy-connection-type = "10gbase-r"; +}; + +&dpmac7 { + phy-handle = <&mdio2_phy3>; + phy-connection-type = "10gbase-r"; +}; + +&dpmac8 { + phy-handle = <&mdio2_phy4>; + phy-connection-type = "10gbase-r"; +}; + &emdio1 { status = "okay"; @@ -66,3 +86,27 @@ reg = <0x13>; }; }; + +&emdio2 { + status = "okay"; + + mdio2_phy1: ethernet-phy@0 { + compatible = "ethernet-phy-id03a1.b4b0", "ethernet-phy-ieee802.3-c45"; + reg = <0x0>; + }; + + mdio2_phy2: ethernet-phy@1 { + compatible = "ethernet-phy-id03a1.b4b0", "ethernet-phy-ieee802.3-c45"; + reg = <0x1>; + }; + + mdio2_phy3: ethernet-phy@2 { + compatible = "ethernet-phy-id03a1.b4b0", "ethernet-phy-ieee802.3-c45"; + reg = <0x2>; + }; + + mdio2_phy4: ethernet-phy@3 { + compatible = "ethernet-phy-id03a1.b4b0", "ethernet-phy-ieee802.3-c45"; + reg = <0x3>; + }; +}; From 2e7c4c3c2fe7da00bd4061b32307dad4eeb9b39e Mon Sep 17 00:00:00 2001 From: Ioana Ciornei Date: Fri, 30 Oct 2020 13:35:53 +0200 Subject: [PATCH 660/799] arm64: dts: ls208xa: add PCS MDIO and PCS PHY nodes Add PCS MDIO nodes for the internal MDIO buses on the LS208x SoCs, along with their internal PCS PHYs which will be used when the DPMAC object is in TYPE_PHY mode. Also, rename the dpmac@x nodes to ethernet@x in order to be compliant with the naming convention used by ethernet controllers. Signed-off-by: Ioana Ciornei Signed-off-by: Shawn Guo --- .../boot/dts/freescale/fsl-ls2088a-rdb.dts | 32 +++ .../arm64/boot/dts/freescale/fsl-ls208xa.dtsi | 256 ++++++++++++++++-- 2 files changed, 272 insertions(+), 16 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2088a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls2088a-rdb.dts index 854f604049ca..60563917be44 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls2088a-rdb.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls2088a-rdb.dts @@ -110,3 +110,35 @@ reg = <0x3>; }; }; + +&pcs_mdio1 { + status = "okay"; +}; + +&pcs_mdio2 { + status = "okay"; +}; + +&pcs_mdio3 { + status = "okay"; +}; + +&pcs_mdio4 { + status = "okay"; +}; + +&pcs_mdio5 { + status = "okay"; +}; + +&pcs_mdio6 { + status = "okay"; +}; + +&pcs_mdio7 { + status = "okay"; +}; + +&pcs_mdio8 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi index ba0877d1e261..02ad16b1bfe3 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi @@ -476,6 +476,214 @@ status = "disabled"; }; + pcs_mdio1: mdio@8c07000 { + compatible = "fsl,fman-memac-mdio"; + reg = <0x0 0x8c07000 0x0 0x1000>; + little-endian; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + pcs1: ethernet-phy@0 { + reg = <0>; + }; + }; + + pcs_mdio2: mdio@8c0b000 { + compatible = "fsl,fman-memac-mdio"; + reg = <0x0 0x8c0b000 0x0 0x1000>; + little-endian; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + pcs2: ethernet-phy@0 { + reg = <0>; + }; + }; + + pcs_mdio3: mdio@8c0f000 { + compatible = "fsl,fman-memac-mdio"; + reg = <0x0 0x8c0f000 0x0 0x1000>; + little-endian; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + pcs3: ethernet-phy@0 { + reg = <0>; + }; + }; + + pcs_mdio4: mdio@8c13000 { + compatible = "fsl,fman-memac-mdio"; + reg = <0x0 0x8c13000 0x0 0x1000>; + little-endian; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + pcs4: ethernet-phy@0 { + reg = <0>; + }; + }; + + pcs_mdio5: mdio@8c17000 { + compatible = "fsl,fman-memac-mdio"; + reg = <0x0 0x8c17000 0x0 0x1000>; + little-endian; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + pcs5: ethernet-phy@0 { + reg = <0>; + }; + }; + + pcs_mdio6: mdio@8c1b000 { + compatible = "fsl,fman-memac-mdio"; + reg = <0x0 0x8c1b000 0x0 0x1000>; + little-endian; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + pcs6: ethernet-phy@0 { + reg = <0>; + }; + }; + + pcs_mdio7: mdio@8c1f000 { + compatible = "fsl,fman-memac-mdio"; + reg = <0x0 0x8c1f000 0x0 0x1000>; + little-endian; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + pcs7: ethernet-phy@0 { + reg = <0>; + }; + }; + + pcs_mdio8: mdio@8c23000 { + compatible = "fsl,fman-memac-mdio"; + reg = <0x0 0x8c23000 0x0 0x1000>; + little-endian; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + pcs8: ethernet-phy@0 { + reg = <0>; + }; + }; + + pcs_mdio9: mdio@8c27000 { + compatible = "fsl,fman-memac-mdio"; + reg = <0x0 0x8c27000 0x0 0x1000>; + little-endian; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + pcs9: ethernet-phy@0 { + reg = <0>; + }; + }; + + pcs_mdio10: mdio@8c2b000 { + compatible = "fsl,fman-memac-mdio"; + reg = <0x0 0x8c2b000 0x0 0x1000>; + little-endian; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + pcs10: ethernet-phy@0 { + reg = <0>; + }; + }; + + pcs_mdio11: mdio@8c2f000 { + compatible = "fsl,fman-memac-mdio"; + reg = <0x0 0x8c2f000 0x0 0x1000>; + little-endian; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + pcs11: ethernet-phy@0 { + reg = <0>; + }; + }; + + pcs_mdio12: mdio@8c33000 { + compatible = "fsl,fman-memac-mdio"; + reg = <0x0 0x8c33000 0x0 0x1000>; + little-endian; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + pcs12: ethernet-phy@0 { + reg = <0>; + }; + }; + + pcs_mdio13: mdio@8c37000 { + compatible = "fsl,fman-memac-mdio"; + reg = <0x0 0x8c37000 0x0 0x1000>; + little-endian; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + pcs13: ethernet-phy@0 { + reg = <0>; + }; + }; + + pcs_mdio14: mdio@8c3b000 { + compatible = "fsl,fman-memac-mdio"; + reg = <0x0 0x8c3b000 0x0 0x1000>; + little-endian; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + pcs14: ethernet-phy@0 { + reg = <0>; + }; + }; + + pcs_mdio15: mdio@8c3f000 { + compatible = "fsl,fman-memac-mdio"; + reg = <0x0 0x8c3f000 0x0 0x1000>; + little-endian; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + pcs15: ethernet-phy@0 { + reg = <0>; + }; + }; + + pcs_mdio16: mdio@8c43000 { + compatible = "fsl,fman-memac-mdio"; + reg = <0x0 0x8c43000 0x0 0x1000>; + little-endian; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + pcs16: ethernet-phy@0 { + reg = <0>; + }; + }; + fsl_mc: fsl-mc@80c000000 { compatible = "fsl,qoriq-mc"; reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */ @@ -500,84 +708,100 @@ #address-cells = <1>; #size-cells = <0>; - dpmac1: dpmac@1 { + dpmac1: ethernet@1 { compatible = "fsl,qoriq-mc-dpmac"; reg = <0x1>; + pcs-handle = <&pcs1>; }; - dpmac2: dpmac@2 { + dpmac2: ethernet@2 { compatible = "fsl,qoriq-mc-dpmac"; reg = <0x2>; + pcs-handle = <&pcs2>; }; - dpmac3: dpmac@3 { + dpmac3: ethernet@3 { compatible = "fsl,qoriq-mc-dpmac"; reg = <0x3>; + pcs-handle = <&pcs3>; }; - dpmac4: dpmac@4 { + dpmac4: ethernet@4 { compatible = "fsl,qoriq-mc-dpmac"; reg = <0x4>; + pcs-handle = <&pcs4>; }; - dpmac5: dpmac@5 { + dpmac5: ethernet@5 { compatible = "fsl,qoriq-mc-dpmac"; reg = <0x5>; + pcs-handle = <&pcs5>; }; - dpmac6: dpmac@6 { + dpmac6: ethernet@6 { compatible = "fsl,qoriq-mc-dpmac"; reg = <0x6>; + pcs-handle = <&pcs6>; }; - dpmac7: dpmac@7 { + dpmac7: ethernet@7 { compatible = "fsl,qoriq-mc-dpmac"; reg = <0x7>; + pcs-handle = <&pcs7>; }; - dpmac8: dpmac@8 { + dpmac8: ethernet@8 { compatible = "fsl,qoriq-mc-dpmac"; reg = <0x8>; + pcs-handle = <&pcs8>; }; - dpmac9: dpmac@9 { + dpmac9: ethernet@9 { compatible = "fsl,qoriq-mc-dpmac"; reg = <0x9>; + pcs-handle = <&pcs9>; }; - dpmac10: dpmac@a { + dpmac10: ethernet@a { compatible = "fsl,qoriq-mc-dpmac"; reg = <0xa>; + pcs-handle = <&pcs10>; }; - dpmac11: dpmac@b { + dpmac11: ethernet@b { compatible = "fsl,qoriq-mc-dpmac"; reg = <0xb>; + pcs-handle = <&pcs11>; }; - dpmac12: dpmac@c { + dpmac12: ethernet@c { compatible = "fsl,qoriq-mc-dpmac"; reg = <0xc>; + pcs-handle = <&pcs12>; }; - dpmac13: dpmac@d { + dpmac13: ethernet@d { compatible = "fsl,qoriq-mc-dpmac"; reg = <0xd>; + pcs-handle = <&pcs13>; }; - dpmac14: dpmac@e { + dpmac14: ethernet@e { compatible = "fsl,qoriq-mc-dpmac"; reg = <0xe>; + pcs-handle = <&pcs14>; }; - dpmac15: dpmac@f { + dpmac15: ethernet@f { compatible = "fsl,qoriq-mc-dpmac"; reg = <0xf>; + pcs-handle = <&pcs15>; }; - dpmac16: dpmac@10 { + dpmac16: ethernet@10 { compatible = "fsl,qoriq-mc-dpmac"; reg = <0x10>; + pcs-handle = <&pcs16>; }; }; }; From f94cfe322f3c9f15e8b0fd0e75bb3acdf5927b84 Mon Sep 17 00:00:00 2001 From: Ioana Ciornei Date: Fri, 30 Oct 2020 13:35:54 +0200 Subject: [PATCH 661/799] arm64: dts: lx2160a: add PCS MDIO and PCS PHY nodes Add PCS MDIO nodes for the internal MDIO buses on the LX2160A, along with their internal PCS PHYs, which will be used when the DPMAC is in TYPE_PHY mode. Also, rename the dpmac@x nodes to ethernet@x in order to be compliant with the naming convention used by ethernet controllers. Signed-off-by: Ioana Ciornei Signed-off-by: Shawn Guo --- .../arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 288 ++++++++++++++++-- 1 file changed, 270 insertions(+), 18 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi index 83072da6f6c6..197397777c83 100644 --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi @@ -1305,6 +1305,240 @@ status = "disabled"; }; + pcs_mdio1: mdio@8c07000 { + compatible = "fsl,fman-memac-mdio"; + reg = <0x0 0x8c07000 0x0 0x1000>; + little-endian; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + pcs1: ethernet-phy@0 { + reg = <0>; + }; + }; + + pcs_mdio2: mdio@8c0b000 { + compatible = "fsl,fman-memac-mdio"; + reg = <0x0 0x8c0b000 0x0 0x1000>; + little-endian; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + pcs2: ethernet-phy@0 { + reg = <0>; + }; + }; + + pcs_mdio3: mdio@8c0f000 { + compatible = "fsl,fman-memac-mdio"; + reg = <0x0 0x8c0f000 0x0 0x1000>; + little-endian; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + pcs3: ethernet-phy@0 { + reg = <0>; + }; + }; + + pcs_mdio4: mdio@8c13000 { + compatible = "fsl,fman-memac-mdio"; + reg = <0x0 0x8c13000 0x0 0x1000>; + little-endian; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + pcs4: ethernet-phy@0 { + reg = <0>; + }; + }; + + pcs_mdio5: mdio@8c17000 { + compatible = "fsl,fman-memac-mdio"; + reg = <0x0 0x8c17000 0x0 0x1000>; + little-endian; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + pcs5: ethernet-phy@0 { + reg = <0>; + }; + }; + + pcs_mdio6: mdio@8c1b000 { + compatible = "fsl,fman-memac-mdio"; + reg = <0x0 0x8c1b000 0x0 0x1000>; + little-endian; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + pcs6: ethernet-phy@0 { + reg = <0>; + }; + }; + + pcs_mdio7: mdio@8c1f000 { + compatible = "fsl,fman-memac-mdio"; + reg = <0x0 0x8c1f000 0x0 0x1000>; + little-endian; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + pcs7: ethernet-phy@0 { + reg = <0>; + }; + }; + + pcs_mdio8: mdio@8c23000 { + compatible = "fsl,fman-memac-mdio"; + reg = <0x0 0x8c23000 0x0 0x1000>; + little-endian; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + pcs8: ethernet-phy@0 { + reg = <0>; + }; + }; + + pcs_mdio9: mdio@8c27000 { + compatible = "fsl,fman-memac-mdio"; + reg = <0x0 0x8c27000 0x0 0x1000>; + little-endian; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + pcs9: ethernet-phy@0 { + reg = <0>; + }; + }; + + pcs_mdio10: mdio@8c2b000 { + compatible = "fsl,fman-memac-mdio"; + reg = <0x0 0x8c2b000 0x0 0x1000>; + little-endian; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + pcs10: ethernet-phy@0 { + reg = <0>; + }; + }; + + pcs_mdio11: mdio@8c2f000 { + compatible = "fsl,fman-memac-mdio"; + reg = <0x0 0x8c2f000 0x0 0x1000>; + little-endian; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + pcs11: ethernet-phy@0 { + reg = <0>; + }; + }; + + pcs_mdio12: mdio@8c33000 { + compatible = "fsl,fman-memac-mdio"; + reg = <0x0 0x8c33000 0x0 0x1000>; + little-endian; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + pcs12: ethernet-phy@0 { + reg = <0>; + }; + }; + + pcs_mdio13: mdio@8c37000 { + compatible = "fsl,fman-memac-mdio"; + reg = <0x0 0x8c37000 0x0 0x1000>; + little-endian; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + pcs13: ethernet-phy@0 { + reg = <0>; + }; + }; + + pcs_mdio14: mdio@8c3b000 { + compatible = "fsl,fman-memac-mdio"; + reg = <0x0 0x8c3b000 0x0 0x1000>; + little-endian; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + pcs14: ethernet-phy@0 { + reg = <0>; + }; + }; + + pcs_mdio15: mdio@8c3f000 { + compatible = "fsl,fman-memac-mdio"; + reg = <0x0 0x8c3f000 0x0 0x1000>; + little-endian; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + pcs15: ethernet-phy@0 { + reg = <0>; + }; + }; + + pcs_mdio16: mdio@8c43000 { + compatible = "fsl,fman-memac-mdio"; + reg = <0x0 0x8c43000 0x0 0x1000>; + little-endian; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + pcs16: ethernet-phy@0 { + reg = <0>; + }; + }; + + pcs_mdio17: mdio@8c47000 { + compatible = "fsl,fman-memac-mdio"; + reg = <0x0 0x8c47000 0x0 0x1000>; + little-endian; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + pcs17: ethernet-phy@0 { + reg = <0>; + }; + }; + + pcs_mdio18: mdio@8c4b000 { + compatible = "fsl,fman-memac-mdio"; + reg = <0x0 0x8c4b000 0x0 0x1000>; + little-endian; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + pcs18: ethernet-phy@0 { + reg = <0>; + }; + }; + fsl_mc: fsl-mc@80c000000 { compatible = "fsl,qoriq-mc"; reg = <0x00000008 0x0c000000 0 0x40>, @@ -1330,94 +1564,112 @@ #address-cells = <1>; #size-cells = <0>; - dpmac1: dpmac@1 { + dpmac1: ethernet@1 { compatible = "fsl,qoriq-mc-dpmac"; reg = <0x1>; + pcs-handle = <&pcs1>; }; - dpmac2: dpmac@2 { + dpmac2: ethernet@2 { compatible = "fsl,qoriq-mc-dpmac"; reg = <0x2>; + pcs-handle = <&pcs2>; }; - dpmac3: dpmac@3 { + dpmac3: ethernet@3 { compatible = "fsl,qoriq-mc-dpmac"; reg = <0x3>; + pcs-handle = <&pcs3>; }; - dpmac4: dpmac@4 { + dpmac4: ethernet@4 { compatible = "fsl,qoriq-mc-dpmac"; reg = <0x4>; + pcs-handle = <&pcs4>; }; - dpmac5: dpmac@5 { + dpmac5: ethernet@5 { compatible = "fsl,qoriq-mc-dpmac"; reg = <0x5>; + pcs-handle = <&pcs5>; }; - dpmac6: dpmac@6 { + dpmac6: ethernet@6 { compatible = "fsl,qoriq-mc-dpmac"; reg = <0x6>; + pcs-handle = <&pcs6>; }; - dpmac7: dpmac@7 { + dpmac7: ethernet@7 { compatible = "fsl,qoriq-mc-dpmac"; reg = <0x7>; + pcs-handle = <&pcs7>; }; - dpmac8: dpmac@8 { + dpmac8: ethernet@8 { compatible = "fsl,qoriq-mc-dpmac"; reg = <0x8>; + pcs-handle = <&pcs8>; }; - dpmac9: dpmac@9 { + dpmac9: ethernet@9 { compatible = "fsl,qoriq-mc-dpmac"; reg = <0x9>; + pcs-handle = <&pcs9>; }; - dpmac10: dpmac@a { + dpmac10: ethernet@a { compatible = "fsl,qoriq-mc-dpmac"; reg = <0xa>; + pcs-handle = <&pcs10>; }; - dpmac11: dpmac@b { + dpmac11: ethernet@b { compatible = "fsl,qoriq-mc-dpmac"; reg = <0xb>; + pcs-handle = <&pcs11>; }; - dpmac12: dpmac@c { + dpmac12: ethernet@c { compatible = "fsl,qoriq-mc-dpmac"; reg = <0xc>; + pcs-handle = <&pcs12>; }; - dpmac13: dpmac@d { + dpmac13: ethernet@d { compatible = "fsl,qoriq-mc-dpmac"; reg = <0xd>; + pcs-handle = <&pcs13>; }; - dpmac14: dpmac@e { + dpmac14: ethernet@e { compatible = "fsl,qoriq-mc-dpmac"; reg = <0xe>; + pcs-handle = <&pcs14>; }; - dpmac15: dpmac@f { + dpmac15: ethernet@f { compatible = "fsl,qoriq-mc-dpmac"; reg = <0xf>; + pcs-handle = <&pcs15>; }; - dpmac16: dpmac@10 { + dpmac16: ethernet@10 { compatible = "fsl,qoriq-mc-dpmac"; reg = <0x10>; + pcs-handle = <&pcs16>; }; - dpmac17: dpmac@11 { + dpmac17: ethernet@11 { compatible = "fsl,qoriq-mc-dpmac"; reg = <0x11>; + pcs-handle = <&pcs17>; }; - dpmac18: dpmac@12 { + dpmac18: ethernet@12 { compatible = "fsl,qoriq-mc-dpmac"; reg = <0x12>; + pcs-handle = <&pcs18>; }; }; }; From f0f3531f3a540b7d6effa451873b0fefd073e182 Mon Sep 17 00:00:00 2001 From: Ioana Ciornei Date: Fri, 30 Oct 2020 13:35:55 +0200 Subject: [PATCH 662/799] arm64: dts: lx2160ardb: add nodes for the AQR107 PHYs Annotate the EMDIO1 node and describe the 2 AQR107 PHYs found on the LX2160ARDB board. Also, add the necessary phy-handles for DPMACs 3 and 4 to their associated PHY. Signed-off-by: Ioana Ciornei Signed-off-by: Shawn Guo --- .../boot/dts/freescale/fsl-lx2160a-rdb.dts | 32 +++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts index 54fe8cd3a711..7723ad5efd37 100644 --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts @@ -35,6 +35,18 @@ status = "okay"; }; +&dpmac3 { + phy-handle = <&aquantia_phy1>; + phy-connection-type = "usxgmii"; + managed = "in-band-status"; +}; + +&dpmac4 { + phy-handle = <&aquantia_phy2>; + phy-connection-type = "usxgmii"; + managed = "in-band-status"; +}; + &dpmac17 { phy-handle = <&rgmii_phy1>; phy-connection-type = "rgmii-id"; @@ -61,6 +73,18 @@ reg = <0x2>; eee-broken-1000t; }; + + aquantia_phy1: ethernet-phy@4 { + /* AQR107 PHY */ + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <0x4>; + }; + + aquantia_phy2: ethernet-phy@5 { + /* AQR107 PHY */ + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <0x5>; + }; }; &esdhc0 { @@ -156,6 +180,14 @@ }; }; +&pcs_mdio3 { + status = "okay"; +}; + +&pcs_mdio4 { + status = "okay"; +}; + &sata0 { status = "okay"; }; From b6abb31375ededd7d87d5a9b117ee77ca9817fc1 Mon Sep 17 00:00:00 2001 From: Xiaowei Bao Date: Mon, 2 Nov 2020 13:44:17 +0800 Subject: [PATCH 663/799] arm64: dts: layerscape: Add PCIe EP node for ls1088a Add PCIe EP node for ls1088a to support EP mode. Signed-off-by: Xiaowei Bao Signed-off-by: Hou Zhiqiang Reviewed-by: Andrew Murray Signed-off-by: Shawn Guo --- .../arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 31 +++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi index 9c9c323cc3cd..cfd341ee48bf 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi @@ -517,6 +517,17 @@ status = "disabled"; }; + pcie_ep1: pcie-ep@3400000 { + compatible = "fsl,ls1088a-pcie-ep", "fsl,ls-pcie-ep"; + reg = <0x00 0x03400000 0x0 0x00100000 + 0x20 0x00000000 0x8 0x00000000>; + reg-names = "regs", "addr_space"; + num-ib-windows = <24>; + num-ob-windows = <256>; + max-functions = /bits/ 8 <2>; + status = "disabled"; + }; + pcie2: pcie@3500000 { compatible = "fsl,ls1088a-pcie"; reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */ @@ -543,6 +554,16 @@ status = "disabled"; }; + pcie_ep2: pcie-ep@3500000 { + compatible = "fsl,ls1088a-pcie-ep", "fsl,ls-pcie-ep"; + reg = <0x00 0x03500000 0x0 0x00100000 + 0x28 0x00000000 0x8 0x00000000>; + reg-names = "regs", "addr_space"; + num-ib-windows = <6>; + num-ob-windows = <6>; + status = "disabled"; + }; + pcie3: pcie@3600000 { compatible = "fsl,ls1088a-pcie"; reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */ @@ -569,6 +590,16 @@ status = "disabled"; }; + pcie_ep3: pcie-ep@3600000 { + compatible = "fsl,ls1088a-pcie-ep", "fsl,ls-pcie-ep"; + reg = <0x00 0x03600000 0x0 0x00100000 + 0x30 0x00000000 0x8 0x00000000>; + reg-names = "regs", "addr_space"; + num-ib-windows = <6>; + num-ob-windows = <6>; + status = "disabled"; + }; + smmu: iommu@5000000 { compatible = "arm,mmu-500"; reg = <0 0x5000000 0 0x800000>; From 71fa01d3a909446ca70c3b751f5a1124b2552329 Mon Sep 17 00:00:00 2001 From: Shengjiu Wang Date: Mon, 2 Nov 2020 10:11:16 +0800 Subject: [PATCH 664/799] arm64: dts: imx8mq: Configure clock rate for audio plls Configure clock rate for audio plls. audio pll1 is used as parent clock for clocks that is multiple of 8kHz. audio pll2 is used as parent clock for clocks that is multiple of 11kHz. Signed-off-by: Shengjiu Wang Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mq.dtsi | 20 +++++++++++++++++--- 1 file changed, 17 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi index 5e0e7d0f1bc4..49cc79246288 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi @@ -606,11 +606,25 @@ "clk_ext3", "clk_ext4"; assigned-clocks = <&clk IMX8MQ_CLK_A53_SRC>, <&clk IMX8MQ_CLK_A53_CORE>, - <&clk IMX8MQ_CLK_NOC>; + <&clk IMX8MQ_CLK_NOC>, + <&clk IMX8MQ_CLK_AUDIO_AHB>, + <&clk IMX8MQ_AUDIO_PLL1_BYPASS>, + <&clk IMX8MQ_AUDIO_PLL2_BYPASS>, + <&clk IMX8MQ_AUDIO_PLL1>, + <&clk IMX8MQ_AUDIO_PLL2>; assigned-clock-rates = <0>, <0>, - <800000000>; + <800000000>, + <0>, + <0>, + <0>, + <786432000>, + <722534400>; assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_800M>, - <&clk IMX8MQ_ARM_PLL_OUT>; + <&clk IMX8MQ_ARM_PLL_OUT>, + <0>, + <&clk IMX8MQ_SYS2_PLL_500M>, + <&clk IMX8MQ_AUDIO_PLL1>, + <&clk IMX8MQ_AUDIO_PLL2>; }; src: reset-controller@30390000 { From 08a1a2e205e3a5159a9dcc2c0019e6f9c1e04f90 Mon Sep 17 00:00:00 2001 From: Shengjiu Wang Date: Mon, 2 Nov 2020 10:11:17 +0800 Subject: [PATCH 665/799] arm64: dts: imx8mq-evk: Add spdif sound card support There are two spdif IP on imx8mq, spdif1 is for normal spdif device, spdif2 is for HDMI ARC interface. Enable these spdif sound card in this patch. Signed-off-by: Shengjiu Wang Reviewed-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mq-evk.dts | 38 ++++++++++++++++ arch/arm64/boot/dts/freescale/imx8mq.dtsi | 48 ++++++++++++++++++++ 2 files changed, 86 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts index 2418cca00bc5..e4250812586b 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts @@ -87,6 +87,21 @@ clocks = <&clk IMX8MQ_CLK_SAI2_ROOT>; }; }; + + sound-spdif { + compatible = "fsl,imx-audio-spdif"; + model = "imx-spdif"; + spdif-controller = <&spdif1>; + spdif-out; + spdif-in; + }; + + sound-hdmi-arc { + compatible = "fsl,imx-audio-spdif"; + model = "imx-hdmi-arc"; + spdif-controller = <&spdif2>; + spdif-in; + }; }; &A53_0 { @@ -336,6 +351,22 @@ status = "okay"; }; +&spdif1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spdif1>; + assigned-clocks = <&clk IMX8MQ_CLK_SPDIF1>; + assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>; + assigned-clock-rates = <24576000>; + status = "okay"; +}; + +&spdif2 { + assigned-clocks = <&clk IMX8MQ_CLK_SPDIF2>; + assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>; + assigned-clock-rates = <24576000>; + status = "okay"; +}; + &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; @@ -467,6 +498,13 @@ >; }; + pinctrl_spdif1: spdif1grp { + fsl,pins = < + MX8MQ_IOMUXC_SPDIF_TX_SPDIF1_OUT 0xd6 + MX8MQ_IOMUXC_SPDIF_RX_SPDIF1_IN 0xd6 + >; + }; + pinctrl_uart1: uart1grp { fsl,pins = < MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x49 diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi index 49cc79246288..a841a023e8e0 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi @@ -793,6 +793,30 @@ ranges = <0x30800000 0x30800000 0x400000>, <0x08000000 0x08000000 0x10000000>; + spdif1: spdif@30810000 { + compatible = "fsl,imx35-spdif"; + reg = <0x30810000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MQ_CLK_IPG_ROOT>, /* core */ + <&clk IMX8MQ_CLK_25M>, /* rxtx0 */ + <&clk IMX8MQ_CLK_SPDIF1>, /* rxtx1 */ + <&clk IMX8MQ_CLK_DUMMY>, /* rxtx2 */ + <&clk IMX8MQ_CLK_DUMMY>, /* rxtx3 */ + <&clk IMX8MQ_CLK_DUMMY>, /* rxtx4 */ + <&clk IMX8MQ_CLK_IPG_ROOT>, /* rxtx5 */ + <&clk IMX8MQ_CLK_DUMMY>, /* rxtx6 */ + <&clk IMX8MQ_CLK_DUMMY>, /* rxtx7 */ + <&clk IMX8MQ_CLK_DUMMY>; /* spba */ + clock-names = "core", "rxtx0", + "rxtx1", "rxtx2", + "rxtx3", "rxtx4", + "rxtx5", "rxtx6", + "rxtx7", "spba"; + dmas = <&sdma1 8 18 0>, <&sdma1 9 18 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + ecspi1: spi@30820000 { #address-cells = <1>; #size-cells = <0>; @@ -862,6 +886,30 @@ status = "disabled"; }; + spdif2: spdif@308a0000 { + compatible = "fsl,imx35-spdif"; + reg = <0x308a0000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MQ_CLK_IPG_ROOT>, /* core */ + <&clk IMX8MQ_CLK_25M>, /* rxtx0 */ + <&clk IMX8MQ_CLK_SPDIF2>, /* rxtx1 */ + <&clk IMX8MQ_CLK_DUMMY>, /* rxtx2 */ + <&clk IMX8MQ_CLK_DUMMY>, /* rxtx3 */ + <&clk IMX8MQ_CLK_DUMMY>, /* rxtx4 */ + <&clk IMX8MQ_CLK_IPG_ROOT>, /* rxtx5 */ + <&clk IMX8MQ_CLK_DUMMY>, /* rxtx6 */ + <&clk IMX8MQ_CLK_DUMMY>, /* rxtx7 */ + <&clk IMX8MQ_CLK_DUMMY>; /* spba */ + clock-names = "core", "rxtx0", + "rxtx1", "rxtx2", + "rxtx3", "rxtx4", + "rxtx5", "rxtx6", + "rxtx7", "spba"; + dmas = <&sdma1 16 18 0>, <&sdma1 17 18 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + sai2: sai@308b0000 { #sound-dai-cells = <0>; compatible = "fsl,imx8mq-sai"; From 3a7d56b3cdc90cbc1d854e0dbde4f2de83bbe6d7 Mon Sep 17 00:00:00 2001 From: Joakim Zhang Date: Mon, 2 Nov 2020 10:16:34 +0800 Subject: [PATCH 666/799] arm64: dts: imx8mp-evk: add CAN support Add CAN device node and pinctrl on i.MX8MP evk board. Signed-off-by: Joakim Zhang Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 62 ++++++++++++++++++++ arch/arm64/boot/dts/freescale/imx8mp.dtsi | 30 ++++++++++ 2 files changed, 92 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts index 908b92bb4dcd..b10dce8767a4 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts @@ -33,6 +33,28 @@ <0x1 0x00000000 0 0xc0000000>; }; + reg_can1_stby: regulator-can1-stby { + compatible = "regulator-fixed"; + regulator-name = "can1-stby"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1_reg>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio5 5 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_can2_stby: regulator-can2-stby { + compatible = "regulator-fixed"; + regulator-name = "can2-stby"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2_reg>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio4 27 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + reg_usdhc2_vmmc: regulator-usdhc2 { compatible = "regulator-fixed"; pinctrl-names = "default"; @@ -45,6 +67,20 @@ }; }; +&flexcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + xceiver-supply = <®_can1_stby>; + status = "okay"; +}; + +&flexcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + xceiver-supply = <®_can2_stby>; + status = "disabled";/* can2 pin conflict with pdm */ +}; + &fec { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_fec>; @@ -144,6 +180,32 @@ >; }; + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX8MP_IOMUXC_SPDIF_RX__CAN1_RX 0x154 + MX8MP_IOMUXC_SPDIF_TX__CAN1_TX 0x154 + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX 0x154 + MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX 0x154 + >; + }; + + pinctrl_flexcan1_reg: flexcan1reggrp { + fsl,pins = < + MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05 0x154 /* CAN1_STBY */ + >; + }; + + pinctrl_flexcan2_reg: flexcan2reggrp { + fsl,pins = < + MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27 0x154 /* CAN2_STBY */ + >; + }; + pinctrl_gpio_led: gpioledgrp { fsl,pins = < MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x19 diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index 479312293036..ecccfbb4f5ad 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -552,6 +552,36 @@ status = "disabled"; }; + flexcan1: can@308c0000 { + compatible = "fsl,imx8mp-flexcan", "fsl,imx6q-flexcan"; + reg = <0x308c0000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MP_CLK_IPG_ROOT>, + <&clk IMX8MP_CLK_CAN1_ROOT>; + clock-names = "ipg", "per"; + assigned-clocks = <&clk IMX8MP_CLK_CAN1>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>; + assigned-clock-rates = <40000000>; + fsl,clk-source = /bits/ 8 <0>; + fsl,stop-mode = <&gpr 0x10 4>; + status = "disabled"; + }; + + flexcan2: can@308d0000 { + compatible = "fsl,imx8mp-flexcan", "fsl,imx6q-flexcan"; + reg = <0x308d0000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MP_CLK_IPG_ROOT>, + <&clk IMX8MP_CLK_CAN2_ROOT>; + clock-names = "ipg", "per"; + assigned-clocks = <&clk IMX8MP_CLK_CAN2>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>; + assigned-clock-rates = <40000000>; + fsl,clk-source = /bits/ 8 <0>; + fsl,stop-mode = <&gpr 0x10 5>; + status = "disabled"; + }; + crypto: crypto@30900000 { compatible = "fsl,sec-v4.0"; #address-cells = <1>; From 4d583263f4c9e6aded6f56f4963fa53f747c83c5 Mon Sep 17 00:00:00 2001 From: Joakim Zhang Date: Mon, 2 Nov 2020 10:25:25 +0800 Subject: [PATCH 667/799] arm64: dts: imx8mq-evk: add linux,autosuspend-period property for IR Add linux,autosuspend-period property for IR, details please refer to: commit ff1c9223b7b8 ("media: rc: gpio-ir-recv: add QoS support for cpuidle system") Signed-off-by: Joakim Zhang Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mq-evk.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts index e4250812586b..85b045253a0e 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts @@ -57,6 +57,7 @@ gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ir>; + linux,autosuspend-period = <125>; }; wm8524: audio-codec { From 56e08dc3a62d27531fea16a92797573525ddf3f0 Mon Sep 17 00:00:00 2001 From: Joakim Zhang Date: Mon, 2 Nov 2020 10:25:26 +0800 Subject: [PATCH 668/799] arm64: dts: imx8mm-evk: add IR support Add IR support on i.MX8MM EVK board. Signed-off-by: Joakim Zhang Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi index 469d5703250b..8c5aa2d8f4a0 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi @@ -41,6 +41,14 @@ enable-active-high; }; + ir-receiver { + compatible = "gpio-ir-receiver"; + gpios = <&gpio1 13 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ir>; + linux,autosuspend-period = <125>; + }; + wm8524: audio-codec { #sound-dai-cells = <0>; compatible = "wlf,wm8524"; @@ -363,6 +371,12 @@ >; }; + pinctrl_ir: irgrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x4f + >; + }; + pinctrl_gpio_wlf: gpiowlfgrp { fsl,pins = < MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21 0xd6 From 29939851a633cd2be1a6e78e3349169a017d0f73 Mon Sep 17 00:00:00 2001 From: Joakim Zhang Date: Mon, 2 Nov 2020 10:25:27 +0800 Subject: [PATCH 669/799] arm64: dts: imx8mn-evk: add IR support Add IR support on i.MX8MN EVK board. Signed-off-by: Joakim Zhang Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi index fda890589a09..76d042a4cf09 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi @@ -38,6 +38,14 @@ gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; enable-active-high; }; + + ir-receiver { + compatible = "gpio-ir-receiver"; + gpios = <&gpio1 13 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ir>; + linux,autosuspend-period = <125>; + }; }; &fec1 { @@ -202,6 +210,12 @@ >; }; + pinctrl_ir: irgrp { + fsl,pins = < + MX8MN_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x4f + >; + }; + pinctrl_i2c1: i2c1grp { fsl,pins = < MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 From bd5840df916dc57929af727ff99b63a93be096c6 Mon Sep 17 00:00:00 2001 From: Nathan Chancellor Date: Sun, 8 Nov 2020 12:16:15 -0700 Subject: [PATCH 670/799] arm64: dts: imx: Fix imx8mm-kontron-n801x-s.dtb target While running 'make dtbs_install', the following error occurs: make[3]: *** No rule to make target 'rootfs/freescale/imx8mm-kontron-n801x-s.dts', needed by '__dtbs_install'. It should be .dtb, not .dts. Fixes: 8668d8b2e67f ("arm64: dts: Add the Kontron i.MX8M Mini SoMs and baseboards") Reviewed-by: Krzysztof Kozlowski Signed-off-by: Nathan Chancellor Reviewed-by: Frieder Schrempf Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 876bf484bbe6..6f0777ee6cd6 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -32,7 +32,7 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2162a-qds.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-beacon-kit.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-ddr4-evk.dtb -dtb-$(CONFIG_ARCH_MXC) += imx8mm-kontron-n801x-s.dts +dtb-$(CONFIG_ARCH_MXC) += imx8mm-kontron-n801x-s.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-var-som-symphony.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mn-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mn-ddr4-evk.dtb From d0570a575aa83116bd0f6a99c4de548af773d950 Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Sun, 8 Nov 2020 19:51:05 +0100 Subject: [PATCH 671/799] arm64: dts: ls1028a: fix ENETC PTP clock input On the LS1028A the ENETC reference clock is connected to 4th HWA output, see Figure 7 "Clock subsystem block diagram". The PHC may run with a wrong frequency. ptp_qoriq_auto_config() will read the clock speed of the clock given in the device tree. It is likely that, on the reference board this wasn't noticed because both clocks have the same frequency. But this must not be always the case. Fix it. Fixes: 49401003e260 ("arm64: dts: fsl: ls1028a: add ENETC 1588 timer node") Signed-off-by: Michael Walle Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi index ac17752ab3ec..ae5769cf4e95 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi @@ -952,7 +952,7 @@ ethernet@0,4 { compatible = "fsl,enetc-ptp"; reg = <0x000400 0 0 0 0>; - clocks = <&clockgen 4 0>; + clocks = <&clockgen 2 3>; little-endian; fsl,extts-fifo; }; From 588b17eda1356e06efa4b888d0af02c80a2788f6 Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Sun, 8 Nov 2020 19:51:06 +0100 Subject: [PATCH 672/799] arm64: dts: ls1028a: fix FlexSPI clock input On the LS1028A the FlexSPI clock is connected to the first HWA output, see Figure 7 "Clock subsystem block diagram". Fixes: c77fae5ba09a ("arm64: dts: ls1028a: Add FlexSPI support") Signed-off-by: Michael Walle Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi index ae5769cf4e95..f166c6689452 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi @@ -309,7 +309,7 @@ <0x0 0x20000000 0x0 0x10000000>; reg-names = "fspi_base", "fspi_mmap"; interrupts = ; - clocks = <&clockgen 4 3>, <&clockgen 4 3>; + clocks = <&clockgen 2 0>, <&clockgen 2 0>; clock-names = "fspi_en", "fspi"; status = "disabled"; }; From f90931aeefe3f3edd2556806bbe59df3a5a9790d Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Sun, 15 Nov 2020 23:53:14 +0100 Subject: [PATCH 673/799] arm64: dts: ls1028a: add optee node Add the optee node which can either be enabled by a specific board or by the bootloader. Signed-off-by: Michael Walle Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi index f166c6689452..7cb603497d65 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi @@ -90,6 +90,14 @@ clocks = <&osc_27m>; }; + firmware { + optee { + compatible = "linaro,optee-tz"; + method = "smc"; + status = "disabled"; + }; + }; + reboot { compatible ="syscon-reboot"; regmap = <&rst>; From 91ab1c12285c9999afe56c09aa296d8b96862976 Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Sun, 15 Nov 2020 23:54:35 +0100 Subject: [PATCH 674/799] arm64: dts: freescale: sl28: combine SPI MTD partitions The upstream port, doesn't really follow the vendor partitioning. The bootloader partition has one U-Boot FIT image containing all needed bits and pieces. Even today the bootloader is already larger than the current "bootloader" partition. Thus, fold all the partitions into one and keep the environment one. The latter is still valid. We keep the failsafe partitions because the first half of the SPI flash is preinstalled by the vendor and immutable. Fixes: 815364d0424e ("arm64: dts: freescale: add Kontron sl28 support") Signed-off-by: Michael Walle Signed-off-by: Shawn Guo --- .../boot/dts/freescale/fsl-ls1028a-kontron-sl28.dts | 12 +----------- 1 file changed, 1 insertion(+), 11 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28.dts index 17a2f5dacc3f..6b1ec50d6a65 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28.dts @@ -158,20 +158,10 @@ }; partition@210000 { - reg = <0x210000 0x0f0000>; + reg = <0x210000 0x1d0000>; label = "bootloader"; }; - partition@300000 { - reg = <0x300000 0x040000>; - label = "DP firmware"; - }; - - partition@340000 { - reg = <0x340000 0x0a0000>; - label = "trusted firmware"; - }; - partition@3e0000 { reg = <0x3e0000 0x020000>; label = "bootloader environment"; From 64d81113931b3f73ce2f5783c1032892c5046f93 Mon Sep 17 00:00:00 2001 From: Yuantian Tang Date: Tue, 17 Nov 2020 11:43:04 +0800 Subject: [PATCH 675/799] arm64: dts: freescale: update calibration table for TMU module Update the calibration table to make the temperature more accurate. Three platforms have been updated: ls1012a, ls1043a and ls1046a. Signed-off-by: Yuantian Tang Signed-off-by: Shawn Guo --- .../arm64/boot/dts/freescale/fsl-ls1012a.dtsi | 57 ++++++++------- .../arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 72 ++++++++++--------- .../arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 72 ++++++++++--------- 3 files changed, 106 insertions(+), 95 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi index a168e06ac50a..626b709d1fb9 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi @@ -291,43 +291,46 @@ compatible = "fsl,qoriq-tmu"; reg = <0x0 0x1f00000 0x0 0x10000>; interrupts = <0 33 0x4>; - fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>; - fsl,tmu-calibration = <0x00000000 0x00000026 - 0x00000001 0x0000002d + fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x60062>; + fsl,tmu-calibration = <0x00000000 0x00000025 + 0x00000001 0x0000002c 0x00000002 0x00000032 0x00000003 0x00000039 0x00000004 0x0000003f 0x00000005 0x00000046 - 0x00000006 0x0000004d - 0x00000007 0x00000054 - 0x00000008 0x0000005a - 0x00000009 0x00000061 - 0x0000000a 0x0000006a - 0x0000000b 0x00000071 + 0x00000006 0x0000004c + 0x00000007 0x00000053 + 0x00000008 0x00000059 + 0x00000009 0x0000005f + 0x0000000a 0x00000066 + 0x0000000b 0x0000006c - 0x00010000 0x00000025 - 0x00010001 0x0000002c + 0x00010000 0x00000026 + 0x00010001 0x0000002d 0x00010002 0x00000035 0x00010003 0x0000003d 0x00010004 0x00000045 - 0x00010005 0x0000004e - 0x00010006 0x00000057 - 0x00010007 0x00000061 - 0x00010008 0x0000006b - 0x00010009 0x00000076 + 0x00010005 0x0000004d + 0x00010006 0x00000055 + 0x00010007 0x0000005d + 0x00010008 0x00000065 + 0x00010009 0x0000006d - 0x00020000 0x00000029 - 0x00020001 0x00000033 - 0x00020002 0x0000003d - 0x00020003 0x00000049 - 0x00020004 0x00000056 - 0x00020005 0x00000061 - 0x00020006 0x0000006d + 0x00020000 0x00000026 + 0x00020001 0x00000030 + 0x00020002 0x0000003a + 0x00020003 0x00000044 + 0x00020004 0x0000004e + 0x00020005 0x00000059 + 0x00020006 0x00000063 - 0x00030000 0x00000021 - 0x00030001 0x0000002a - 0x00030002 0x0000003c - 0x00030003 0x0000004e>; + 0x00030000 0x00000014 + 0x00030001 0x00000021 + 0x00030002 0x0000002e + 0x00030003 0x0000003a + 0x00030004 0x00000047 + 0x00030005 0x00000053 + 0x00030006 0x00000060>; big-endian; #thermal-sensor-cells = <1>; }; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi index d5d219311161..bbae4b353d3f 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi @@ -403,43 +403,47 @@ compatible = "fsl,qoriq-tmu"; reg = <0x0 0x1f00000 0x0 0x10000>; interrupts = <0 33 0x4>; - fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>; - fsl,tmu-calibration = <0x00000000 0x00000026 - 0x00000001 0x0000002d - 0x00000002 0x00000032 - 0x00000003 0x00000039 - 0x00000004 0x0000003f - 0x00000005 0x00000046 - 0x00000006 0x0000004d - 0x00000007 0x00000054 - 0x00000008 0x0000005a - 0x00000009 0x00000061 - 0x0000000a 0x0000006a - 0x0000000b 0x00000071 + fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x70062>; + fsl,tmu-calibration = <0x00000000 0x00000023 + 0x00000001 0x0000002a + 0x00000002 0x00000031 + 0x00000003 0x00000037 + 0x00000004 0x0000003e + 0x00000005 0x00000044 + 0x00000006 0x0000004b + 0x00000007 0x00000051 + 0x00000008 0x00000058 + 0x00000009 0x0000005e + 0x0000000a 0x00000065 + 0x0000000b 0x0000006b - 0x00010000 0x00000025 - 0x00010001 0x0000002c - 0x00010002 0x00000035 - 0x00010003 0x0000003d - 0x00010004 0x00000045 - 0x00010005 0x0000004e - 0x00010006 0x00000057 - 0x00010007 0x00000061 - 0x00010008 0x0000006b - 0x00010009 0x00000076 + 0x00010000 0x00000023 + 0x00010001 0x0000002b + 0x00010002 0x00000033 + 0x00010003 0x0000003b + 0x00010004 0x00000043 + 0x00010005 0x0000004b + 0x00010006 0x00000054 + 0x00010007 0x0000005c + 0x00010008 0x00000064 + 0x00010009 0x0000006c - 0x00020000 0x00000029 - 0x00020001 0x00000033 - 0x00020002 0x0000003d - 0x00020003 0x00000049 - 0x00020004 0x00000056 - 0x00020005 0x00000061 - 0x00020006 0x0000006d + 0x00020000 0x00000021 + 0x00020001 0x0000002c + 0x00020002 0x00000036 + 0x00020003 0x00000040 + 0x00020004 0x0000004b + 0x00020005 0x00000055 + 0x00020006 0x0000005f - 0x00030000 0x00000021 - 0x00030001 0x0000002a - 0x00030002 0x0000003c - 0x00030003 0x0000004e>; + 0x00030000 0x00000013 + 0x00030001 0x0000001d + 0x00030002 0x00000028 + 0x00030003 0x00000032 + 0x00030004 0x0000003d + 0x00030005 0x00000047 + 0x00030006 0x00000052 + 0x00030007 0x0000005c>; #thermal-sensor-cells = <1>; }; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi index 1fa39bacff4b..025e1f587662 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi @@ -400,45 +400,49 @@ compatible = "fsl,qoriq-tmu"; reg = <0x0 0x1f00000 0x0 0x10000>; interrupts = <0 33 0x4>; - fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>; + fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x70062>; fsl,tmu-calibration = /* Calibration data group 1 */ - <0x00000000 0x00000026 - 0x00000001 0x0000002d - 0x00000002 0x00000032 - 0x00000003 0x00000039 - 0x00000004 0x0000003f - 0x00000005 0x00000046 - 0x00000006 0x0000004d - 0x00000007 0x00000054 - 0x00000008 0x0000005a - 0x00000009 0x00000061 - 0x0000000a 0x0000006a - 0x0000000b 0x00000071 + <0x00000000 0x00000023 + 0x00000001 0x00000029 + 0x00000002 0x0000002f + 0x00000003 0x00000036 + 0x00000004 0x0000003c + 0x00000005 0x00000042 + 0x00000006 0x00000049 + 0x00000007 0x0000004f + 0x00000008 0x00000055 + 0x00000009 0x0000005c + 0x0000000a 0x00000062 + 0x0000000b 0x00000068 /* Calibration data group 2 */ - 0x00010000 0x00000025 - 0x00010001 0x0000002c - 0x00010002 0x00000035 - 0x00010003 0x0000003d - 0x00010004 0x00000045 - 0x00010005 0x0000004e - 0x00010006 0x00000057 - 0x00010007 0x00000061 - 0x00010008 0x0000006b - 0x00010009 0x00000076 + 0x00010000 0x00000022 + 0x00010001 0x0000002a + 0x00010002 0x00000032 + 0x00010003 0x0000003a + 0x00010004 0x00000042 + 0x00010005 0x0000004a + 0x00010006 0x00000052 + 0x00010007 0x0000005a + 0x00010008 0x00000062 + 0x00010009 0x0000006a /* Calibration data group 3 */ - 0x00020000 0x00000029 - 0x00020001 0x00000033 - 0x00020002 0x0000003d - 0x00020003 0x00000049 - 0x00020004 0x00000056 - 0x00020005 0x00000061 - 0x00020006 0x0000006d + 0x00020000 0x00000021 + 0x00020001 0x0000002b + 0x00020002 0x00000035 + 0x00020003 0x0000003e + 0x00020004 0x00000048 + 0x00020005 0x00000052 + 0x00020006 0x0000005c /* Calibration data group 4 */ - 0x00030000 0x00000021 - 0x00030001 0x0000002a - 0x00030002 0x0000003c - 0x00030003 0x0000004e>; + 0x00030000 0x00000011 + 0x00030001 0x0000001a + 0x00030002 0x00000024 + 0x00030003 0x0000002e + 0x00030004 0x00000038 + 0x00030005 0x00000042 + 0x00030006 0x0000004c + 0x00030007 0x00000056>; big-endian; #thermal-sensor-cells = <1>; }; From 83afd0b3e0279107ff06945bad4b63a1fbe83224 Mon Sep 17 00:00:00 2001 From: Serge Semin Date: Wed, 11 Nov 2020 12:15:45 +0300 Subject: [PATCH 676/799] arm64: dts: marvell: cp11x: Harmonize xHCI DT nodes name In accordance with the Generic xHCI bindings the corresponding node name is suppose to comply with the Generic USB HCD DT schema, which requires the USB nodes to have the name acceptable by the regexp: "^usb(@.*)?" . Make sure the "generic-xhci"-compatible nodes are correctly named. Signed-off-by: Serge Semin Acked-by: Krzysztof Kozlowski Signed-off-by: Gregory CLEMENT --- arch/arm64/boot/dts/marvell/armada-cp11x.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi b/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi index ec27294f097b..994a2fce449a 100644 --- a/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi @@ -275,7 +275,7 @@ }; }; - CP11X_LABEL(usb3_0): usb3@500000 { + CP11X_LABEL(usb3_0): usb@500000 { compatible = "marvell,armada-8k-xhci", "generic-xhci"; reg = <0x500000 0x4000>; @@ -287,7 +287,7 @@ status = "disabled"; }; - CP11X_LABEL(usb3_1): usb3@510000 { + CP11X_LABEL(usb3_1): usb@510000 { compatible = "marvell,armada-8k-xhci", "generic-xhci"; reg = <0x510000 0x4000>; From da57203dc7fd556fbb3f0ec7d7d7c0b0e893b386 Mon Sep 17 00:00:00 2001 From: Tomasz Maciej Nowak Date: Tue, 10 Nov 2020 16:38:31 +0100 Subject: [PATCH 677/799] arm64: dts: mcbin-singleshot: add heartbeat LED With board revision 1.3, SolidRun moved the power LED to the middle of the board. In old place of power LED a GPIO controllable heartbeat LED was added. This commit only touches Single Shot variant, since only this variant is all revision 1.3. Reported-by: Alexandra Alth Signed-off-by: Tomasz Maciej Nowak Signed-off-by: Gregory CLEMENT --- .../marvell/armada-8040-mcbin-singleshot.dts | 22 +++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm64/boot/dts/marvell/armada-8040-mcbin-singleshot.dts b/arch/arm64/boot/dts/marvell/armada-8040-mcbin-singleshot.dts index 2e6832d02a59..411d20064271 100644 --- a/arch/arm64/boot/dts/marvell/armada-8040-mcbin-singleshot.dts +++ b/arch/arm64/boot/dts/marvell/armada-8040-mcbin-singleshot.dts @@ -5,6 +5,8 @@ * Device Tree file for MACCHIATOBin Armada 8040 community board platform */ +#include + #include "armada-8040-mcbin.dtsi" / { @@ -12,6 +14,19 @@ compatible = "marvell,armada8040-mcbin-singleshot", "marvell,armada8040-mcbin", "marvell,armada8040", "marvell,armada-ap806-quad", "marvell,armada-ap806"; + + leds { + compatible = "gpio-leds"; + pinctrl-0 = <&cp0_led18_pins>; + pinctrl-names = "default"; + + led18 { + gpios = <&cp0_gpio2 1 GPIO_ACTIVE_LOW>; + function = LED_FUNCTION_HEARTBEAT; + color = ; + linux,default-trigger = "heartbeat"; + }; + }; }; &cp0_eth0 { @@ -27,3 +42,10 @@ managed = "in-band-status"; sfp = <&sfp_eth1>; }; + +&cp0_pinctrl { + cp0_led18_pins: led18-pins { + marvell,pins = "mpp33"; + marvell,function = "gpio"; + }; +}; From f43cadef2df260101497a6aace05e24201f00202 Mon Sep 17 00:00:00 2001 From: Tomasz Nowicki Date: Thu, 5 Nov 2020 12:26:02 +0100 Subject: [PATCH 678/799] arm64: dts: marvell: keep SMMU disabled by default for Armada 7040 and 8040 FW has to configure devices' StreamIDs so that SMMU is able to lookup context and do proper translation later on. For Armada 7040 & 8040 and publicly available FW, most of the devices are configured properly, but some like ap_sdhci0, PCIe, NIC still remain unassigned which results in SMMU faults about unmatched StreamID (assuming ARM_SMMU_DISABLE_BYPASS_BY_DEFAUL=y). Since there is dependency on custom FW let SMMU be disabled by default. People who still willing to use SMMU need to enable manually and use ARM_SMMU_DISABLE_BYPASS_BY_DEFAUL=n (or via kernel command line) with extra caution. Fixes: 83a3545d9c37 ("arm64: dts: marvell: add SMMU support") Cc: # 5.9+ Signed-off-by: Tomasz Nowicki Signed-off-by: Gregory CLEMENT --- arch/arm64/boot/dts/marvell/armada-7040.dtsi | 4 ---- arch/arm64/boot/dts/marvell/armada-8040.dtsi | 4 ---- 2 files changed, 8 deletions(-) diff --git a/arch/arm64/boot/dts/marvell/armada-7040.dtsi b/arch/arm64/boot/dts/marvell/armada-7040.dtsi index 7a3198cd7a07..2f440711d21d 100644 --- a/arch/arm64/boot/dts/marvell/armada-7040.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-7040.dtsi @@ -15,10 +15,6 @@ "marvell,armada-ap806"; }; -&smmu { - status = "okay"; -}; - &cp0_pcie0 { iommu-map = <0x0 &smmu 0x480 0x20>, diff --git a/arch/arm64/boot/dts/marvell/armada-8040.dtsi b/arch/arm64/boot/dts/marvell/armada-8040.dtsi index 79e8ce59baa8..22c2d6ebf381 100644 --- a/arch/arm64/boot/dts/marvell/armada-8040.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-8040.dtsi @@ -15,10 +15,6 @@ "marvell,armada-ap806"; }; -&smmu { - status = "okay"; -}; - &cp0_pcie0 { iommu-map = <0x0 &smmu 0x480 0x20>, From a2081c09d7410c3e55d902a09602b833dc96c58a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marek=20Beh=C3=BAn?= Date: Mon, 16 Nov 2020 13:33:03 +0100 Subject: [PATCH 679/799] arm64: dts: armada-3720-turris-mox: add 3W power capability to SFP cage MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add maximum-power-milliwatt = 3000 to SFP node of Turris MOX. Signed-off-by: Marek Behún Fixes: 7109d817db2e ("arm64: dts: marvell: add DTS for Turris Mox") Cc: Gregory CLEMENT Cc: Andrew Lunn Cc: Rob Herring Cc: devicetree@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Signed-off-by: Gregory CLEMENT --- arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts b/arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts index bf76ebe46379..f5ec3b644769 100644 --- a/arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts +++ b/arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts @@ -102,6 +102,7 @@ mod-def0-gpio = <&moxtet_sfp 2 GPIO_ACTIVE_LOW>; tx-disable-gpio = <&moxtet_sfp 4 GPIO_ACTIVE_HIGH>; rate-select0-gpio = <&moxtet_sfp 5 GPIO_ACTIVE_HIGH>; + maximum-power-milliwatt = <3000>; /* enabled by U-Boot if SFP module is present */ status = "disabled"; From 97a0115cd96a173369ef30eee2290184921b3f24 Mon Sep 17 00:00:00 2001 From: Shunqian Zheng Date: Tue, 20 Oct 2020 16:38:49 -0300 Subject: [PATCH 680/799] arm64: dts: rockchip: add isp0 node for rk3399 RK3399 has two ISPs, but only isp0 was tested. Add isp0 node in rk3399 dtsi Verified with: make ARCH=arm64 dtbs_check DT_SCHEMA_FILES=Documentation/devicetree/bindings/media/rockchip-isp1.yaml Signed-off-by: Shunqian Zheng Signed-off-by: Jacob Chen Signed-off-by: Helen Koike Link: https://lore.kernel.org/r/20201020193850.1460644-9-helen.koike@collabora.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3399.dtsi | 26 ++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi index 1aa52ec938a1..248de7b5d724 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi @@ -1723,6 +1723,32 @@ status = "disabled"; }; + isp0: isp0@ff910000 { + compatible = "rockchip,rk3399-cif-isp"; + reg = <0x0 0xff910000 0x0 0x4000>; + interrupts = ; + clocks = <&cru SCLK_ISP0>, + <&cru ACLK_ISP0_WRAPPER>, + <&cru HCLK_ISP0_WRAPPER>; + clock-names = "isp", "aclk", "hclk"; + iommus = <&isp0_mmu>; + phys = <&mipi_dphy_rx0>; + phy-names = "dphy"; + power-domains = <&power RK3399_PD_ISP0>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + }; + isp0_mmu: iommu@ff914000 { compatible = "rockchip,iommu"; reg = <0x0 0xff914000 0x0 0x100>, <0x0 0xff915000 0x0 0x100>; From ef098edc9c245dd1c150001e22c78e6a3ffd7ff8 Mon Sep 17 00:00:00 2001 From: Eddie Cai Date: Tue, 20 Oct 2020 16:38:50 -0300 Subject: [PATCH 681/799] arm64: dts: rockchip: add isp and sensors for Scarlet Enable ISP and camera sensor ov2685 and ov5695 for Scarlet Chromebook Verified with: make ARCH=arm64 dtbs_check Signed-off-by: Shunqian Zheng Signed-off-by: Eddie Cai Signed-off-by: Tomasz Figa Signed-off-by: Helen Koike Reviewed-by: Tomasz Figa Link: https://lore.kernel.org/r/20201020193850.1460644-10-helen.koike@collabora.com Signed-off-by: Heiko Stuebner --- .../boot/dts/rockchip/rk3399-gru-scarlet.dtsi | 74 +++++++++++++++++++ 1 file changed, 74 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet.dtsi index 60cd1c18cd4e..beee5fbb3443 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet.dtsi @@ -296,6 +296,52 @@ camera: &i2c7 { /* 24M mclk is shared between world and user cameras */ pinctrl-0 = <&i2c7_xfer &test_clkout1>; + + /* Rear-facing camera */ + wcam: camera@36 { + compatible = "ovti,ov5695"; + reg = <0x36>; + pinctrl-names = "default"; + pinctrl-0 = <&wcam_rst>; + + clocks = <&cru SCLK_TESTCLKOUT1>; + clock-names = "xvclk"; + + avdd-supply = <&pp2800_cam>; + dvdd-supply = <&pp1250_cam>; + dovdd-supply = <&pp1800_s0>; + reset-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>; + + port { + wcam_out: endpoint { + remote-endpoint = <&mipi_in_wcam>; + data-lanes = <1 2>; + }; + }; + }; + + /* Front-facing camera */ + ucam: camera@3c { + compatible = "ovti,ov2685"; + reg = <0x3c>; + pinctrl-names = "default"; + pinctrl-0 = <&ucam_rst>; + + clocks = <&cru SCLK_TESTCLKOUT1>; + clock-names = "xvclk"; + + avdd-supply = <&pp2800_cam>; + dovdd-supply = <&pp1800_s0>; + dvdd-supply = <&pp1800_s0>; + reset-gpios = <&gpio2 3 GPIO_ACTIVE_LOW>; + + port { + ucam_out: endpoint { + remote-endpoint = <&mipi_in_ucam>; + data-lanes = <1>; + }; + }; + }; }; &cdn_dp { @@ -353,10 +399,38 @@ camera: &i2c7 { gpio1830-supply = <&pp1800_s0>; /* APIO4_VDD; 4c 4d */ }; +&isp0 { + status = "okay"; + + ports { + port@0 { + mipi_in_wcam: endpoint@0 { + reg = <0>; + remote-endpoint = <&wcam_out>; + data-lanes = <1 2>; + }; + + mipi_in_ucam: endpoint@1 { + reg = <1>; + remote-endpoint = <&ucam_out>; + data-lanes = <1>; + }; + }; + }; +}; + +&isp0_mmu { + status = "okay"; +}; + &max98357a { sdmode-gpios = <&gpio0 2 GPIO_ACTIVE_HIGH>; }; +&mipi_dphy_rx0 { + status = "okay"; +}; + &mipi_dsi { status = "okay"; clock-master; From 3e482859f1ef73244849ea56e08933b2a8d21882 Mon Sep 17 00:00:00 2001 From: Thara Gopinath Date: Thu, 19 Nov 2020 10:52:32 -0500 Subject: [PATCH 682/799] dts: qcom: sdm845: Add dt entries to support crypto engine. Add crypto engine (CE) and CE BAM related nodes and definitions to "sdm845.dtsi". Signed-off-by: Thara Gopinath Link: https://lore.kernel.org/r/20201119155233.3974286-6-thara.gopinath@linaro.org [bjorn: Replaced RPMH_CE_CLK constant, for now] Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 30 ++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 256a698745ac..de542862748d 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -2140,6 +2140,36 @@ }; }; + cryptobam: dma@1dc4000 { + compatible = "qcom,bam-v1.7.0"; + reg = <0 0x01dc4000 0 0x24000>; + interrupts = ; + clocks = <&rpmhcc 15>; + clock-names = "bam_clk"; + #dma-cells = <1>; + qcom,ee = <0>; + qcom,controlled-remotely = <1>; + iommus = <&apps_smmu 0x704 0x1>, + <&apps_smmu 0x706 0x1>, + <&apps_smmu 0x714 0x1>, + <&apps_smmu 0x716 0x1>; + }; + + crypto: crypto@1dfa000 { + compatible = "qcom,crypto-v5.4"; + reg = <0 0x01dfa000 0 0x6000>; + clocks = <&gcc GCC_CE1_AHB_CLK>, + <&gcc GCC_CE1_AHB_CLK>, + <&rpmhcc 15>; + clock-names = "iface", "bus", "core"; + dmas = <&cryptobam 6>, <&cryptobam 7>; + dma-names = "rx", "tx"; + iommus = <&apps_smmu 0x704 0x1>, + <&apps_smmu 0x706 0x1>, + <&apps_smmu 0x714 0x1>, + <&apps_smmu 0x716 0x1>; + }; + ipa: ipa@1e40000 { compatible = "qcom,sdm845-ipa"; From 683227e5a34e4ca40bb13bca47952b48516ea87d Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Tue, 24 Nov 2020 12:44:14 -0600 Subject: [PATCH 683/799] arm64: dts: qcom: c630: Re-enable apps_smmu Re-enable the apps_smmu now that the arm-smmu driver supports stream mapping handoff from firmware. Tested-by: Steev Klimaszewski Acked-by: Shawn Guo Link: https://lore.kernel.org/r/20201124184414.380796-1-bjorn.andersson@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts | 5 ----- 1 file changed, 5 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts b/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts index d03ca3190746..f5b98845fa90 100644 --- a/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts +++ b/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts @@ -232,11 +232,6 @@ }; }; -&apps_smmu { - /* TODO: Figure out how to survive booting with this enabled */ - status = "disabled"; -}; - &cdsp_pas { firmware-name = "qcom/LENOVO/81JL/qccdsp850.mbn"; status = "okay"; From 71b83b74cca3f6b583b7c343896be3922ea80466 Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Wed, 25 Nov 2020 00:08:38 -0600 Subject: [PATCH 684/799] arm64: dts: qcom: c630: Expose LID events The LID state can be read from GPIO 124 and the "tablet mode" from GPIO 95, expose these to the system using gpio-keys and mark the falling edge of the LID state as a wakeup-source - to wake the system from suspend. Tested-by: Steev Klimaszewski Acked-by: Shawn Guo Link: https://lore.kernel.org/r/20201125060838.165576-1-bjorn.andersson@linaro.org Signed-off-by: Bjorn Andersson --- .../boot/dts/qcom/sdm850-lenovo-yoga-c630.dts | 39 +++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts b/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts index f5b98845fa90..3850e74ed653 100644 --- a/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts +++ b/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts @@ -8,6 +8,8 @@ /dts-v1/; #include +#include +#include #include #include #include @@ -21,6 +23,27 @@ aliases { hsuart0 = &uart6; }; + + gpio-keys { + compatible = "gpio-keys"; + + pinctrl-names = "default"; + pinctrl-0 = <&lid_pin_active>, <&mode_pin_active>; + + lid { + gpios = <&tlmm 124 GPIO_ACTIVE_HIGH>; + linux,input-type = ; + linux,code = ; + wakeup-source; + wakeup-event-action = ; + }; + + mode { + gpios = <&tlmm 95 GPIO_ACTIVE_HIGH>; + linux,input-type = ; + linux,code = ; + }; + }; }; &adsp_pas { @@ -456,6 +479,22 @@ bias-pull-down; drive-strength = <2>; }; + + lid_pin_active: lid-pin { + pins = "gpio124"; + function = "gpio"; + + input-enable; + bias-disable; + }; + + mode_pin_active: mode-pin { + pins = "gpio95"; + function = "gpio"; + + input-enable; + bias-disable; + }; }; &uart6 { From 8742bb4bf203814b09572b615b5aeab000bf6248 Mon Sep 17 00:00:00 2001 From: Georgi Djakov Date: Thu, 5 Nov 2020 15:52:09 +0200 Subject: [PATCH 685/799] dt-bindings: interconnect: sdm845: Add IDs for the QUP ports The QUP ports exist in the topology, but are not exposed as an endpoints in DT. Fix this by creating IDs and attach them to their NoCs, so that the various QUP drivers (i2c/spi/uart etc.) are able to request their interconnect paths and scale their bandwidth. Reviewed-by: Bjorn Andersson Acked-by: Rob Herring Signed-off-by: Georgi Djakov Link: https://lore.kernel.org/r/20201105135211.7160-1-georgi.djakov@linaro.org Signed-off-by: Bjorn Andersson --- include/dt-bindings/interconnect/qcom,sdm845.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/dt-bindings/interconnect/qcom,sdm845.h b/include/dt-bindings/interconnect/qcom,sdm845.h index 290be38f40e6..67b500e24915 100644 --- a/include/dt-bindings/interconnect/qcom,sdm845.h +++ b/include/dt-bindings/interconnect/qcom,sdm845.h @@ -19,6 +19,7 @@ #define SLAVE_A1NOC_SNOC 7 #define SLAVE_SERVICE_A1NOC 8 #define SLAVE_ANOC_PCIE_A1NOC_SNOC 9 +#define MASTER_QUP_1 10 #define MASTER_A2NOC_CFG 0 #define MASTER_QDSS_BAM 1 @@ -32,6 +33,7 @@ #define SLAVE_A2NOC_SNOC 9 #define SLAVE_ANOC_PCIE_SNOC 10 #define SLAVE_SERVICE_A2NOC 11 +#define MASTER_QUP_2 12 #define MASTER_SPDM 0 #define MASTER_TIC 1 From cd5fc457e5d2b8faf28c45f4beedc05f107a4268 Mon Sep 17 00:00:00 2001 From: Georgi Djakov Date: Thu, 5 Nov 2020 15:52:10 +0200 Subject: [PATCH 686/799] interconnect: qcom: sdm845: Add the missing nodes for QUP The QUP nodes are currently defined just as entries in the topology, but they are not referenced by any of the NoCs. Let's fix this and "attach" them to their NoCs, so that the QUP drivers are able to use them as path endpoints and scale their bandwidth. This is based on the information from the downstream msm-4.9 kernel. Reviewed-by: Bjorn Andersson Signed-off-by: Georgi Djakov Link: https://lore.kernel.org/r/20201105135211.7160-2-georgi.djakov@linaro.org Signed-off-by: Bjorn Andersson --- drivers/interconnect/qcom/sdm845.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/interconnect/qcom/sdm845.c b/drivers/interconnect/qcom/sdm845.c index d79e3163e2c3..c892d5858396 100644 --- a/drivers/interconnect/qcom/sdm845.c +++ b/drivers/interconnect/qcom/sdm845.c @@ -177,6 +177,7 @@ DEFINE_QBCM(bcm_sn15, "SN15", false, &qnm_memnoc); static struct qcom_icc_bcm *aggre1_noc_bcms[] = { &bcm_sn9, + &bcm_qup0, }; static struct qcom_icc_node *aggre1_noc_nodes[] = { @@ -190,6 +191,7 @@ static struct qcom_icc_node *aggre1_noc_nodes[] = { [SLAVE_A1NOC_SNOC] = &qns_a1noc_snoc, [SLAVE_SERVICE_A1NOC] = &srvc_aggre1_noc, [SLAVE_ANOC_PCIE_A1NOC_SNOC] = &qns_pcie_a1noc_snoc, + [MASTER_QUP_1] = &qhm_qup1, }; static const struct qcom_icc_desc sdm845_aggre1_noc = { @@ -218,6 +220,7 @@ static struct qcom_icc_node *aggre2_noc_nodes[] = { [SLAVE_A2NOC_SNOC] = &qns_a2noc_snoc, [SLAVE_ANOC_PCIE_SNOC] = &qns_pcie_snoc, [SLAVE_SERVICE_A2NOC] = &srvc_aggre2_noc, + [MASTER_QUP_2] = &qhm_qup2, }; static const struct qcom_icc_desc sdm845_aggre2_noc = { From 05b801afb7d7eb569bfe5bdf9c192e2a5306473a Mon Sep 17 00:00:00 2001 From: Georgi Djakov Date: Thu, 5 Nov 2020 15:52:11 +0200 Subject: [PATCH 687/799] arm64: dts: sdm845: Add interconnect properties for QUP Add the interconnects DT property to describe the ports for GENI QUPs on the sdm845 platform. Signed-off-by: Georgi Djakov Link: https://lore.kernel.org/r/20201105135211.7160-3-georgi.djakov@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 160 +++++++++++++++++++++++++++ 1 file changed, 160 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index de542862748d..bcf888381f14 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -1124,6 +1124,8 @@ #address-cells = <2>; #size-cells = <2>; ranges; + interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>; + interconnect-names = "qup-core"; status = "disabled"; i2c0: i2c@880000 { @@ -1138,6 +1140,10 @@ #size-cells = <0>; power-domains = <&rpmhpd SDM845_CX>; operating-points-v2 = <&qup_opp_table>; + interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>, + <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; status = "disabled"; }; @@ -1151,6 +1157,9 @@ interrupts = ; #address-cells = <1>; #size-cells = <0>; + interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; + interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; @@ -1164,6 +1173,9 @@ interrupts = ; power-domains = <&rpmhpd SDM845_CX>; operating-points-v2 = <&qup_opp_table>; + interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; + interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; @@ -1179,6 +1191,10 @@ #size-cells = <0>; power-domains = <&rpmhpd SDM845_CX>; operating-points-v2 = <&qup_opp_table>; + interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>, + <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; status = "disabled"; }; @@ -1192,6 +1208,9 @@ interrupts = ; #address-cells = <1>; #size-cells = <0>; + interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; + interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; @@ -1205,6 +1224,9 @@ interrupts = ; power-domains = <&rpmhpd SDM845_CX>; operating-points-v2 = <&qup_opp_table>; + interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; + interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; @@ -1220,6 +1242,10 @@ #size-cells = <0>; power-domains = <&rpmhpd SDM845_CX>; operating-points-v2 = <&qup_opp_table>; + interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>, + <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; status = "disabled"; }; @@ -1233,6 +1259,9 @@ interrupts = ; #address-cells = <1>; #size-cells = <0>; + interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; + interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; @@ -1246,6 +1275,9 @@ interrupts = ; power-domains = <&rpmhpd SDM845_CX>; operating-points-v2 = <&qup_opp_table>; + interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; + interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; @@ -1261,6 +1293,10 @@ #size-cells = <0>; power-domains = <&rpmhpd SDM845_CX>; operating-points-v2 = <&qup_opp_table>; + interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>, + <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; status = "disabled"; }; @@ -1274,6 +1310,9 @@ interrupts = ; #address-cells = <1>; #size-cells = <0>; + interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; + interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; @@ -1287,6 +1326,9 @@ interrupts = ; power-domains = <&rpmhpd SDM845_CX>; operating-points-v2 = <&qup_opp_table>; + interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; + interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; @@ -1302,6 +1344,10 @@ #size-cells = <0>; power-domains = <&rpmhpd SDM845_CX>; operating-points-v2 = <&qup_opp_table>; + interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>, + <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; status = "disabled"; }; @@ -1315,6 +1361,9 @@ interrupts = ; #address-cells = <1>; #size-cells = <0>; + interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; + interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; @@ -1328,6 +1377,9 @@ interrupts = ; power-domains = <&rpmhpd SDM845_CX>; operating-points-v2 = <&qup_opp_table>; + interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; + interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; @@ -1343,6 +1395,10 @@ #size-cells = <0>; power-domains = <&rpmhpd SDM845_CX>; operating-points-v2 = <&qup_opp_table>; + interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>, + <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; status = "disabled"; }; @@ -1356,6 +1412,9 @@ interrupts = ; #address-cells = <1>; #size-cells = <0>; + interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; + interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; @@ -1369,6 +1428,9 @@ interrupts = ; power-domains = <&rpmhpd SDM845_CX>; operating-points-v2 = <&qup_opp_table>; + interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; + interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; @@ -1384,6 +1446,10 @@ #size-cells = <0>; power-domains = <&rpmhpd SDM845_CX>; operating-points-v2 = <&qup_opp_table>; + interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>, + <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; status = "disabled"; }; @@ -1397,6 +1463,9 @@ interrupts = ; #address-cells = <1>; #size-cells = <0>; + interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; + interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; @@ -1410,6 +1479,9 @@ interrupts = ; power-domains = <&rpmhpd SDM845_CX>; operating-points-v2 = <&qup_opp_table>; + interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; + interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; @@ -1438,6 +1510,9 @@ interrupts = ; #address-cells = <1>; #size-cells = <0>; + interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; + interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; @@ -1451,6 +1526,9 @@ interrupts = ; power-domains = <&rpmhpd SDM845_CX>; operating-points-v2 = <&qup_opp_table>; + interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; + interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; }; @@ -1465,6 +1543,8 @@ #address-cells = <2>; #size-cells = <2>; ranges; + interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>; + interconnect-names = "qup-core"; status = "disabled"; i2c8: i2c@a80000 { @@ -1479,6 +1559,10 @@ #size-cells = <0>; power-domains = <&rpmhpd SDM845_CX>; operating-points-v2 = <&qup_opp_table>; + interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, + <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; status = "disabled"; }; @@ -1492,6 +1576,9 @@ interrupts = ; #address-cells = <1>; #size-cells = <0>; + interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; + interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; @@ -1505,6 +1592,9 @@ interrupts = ; power-domains = <&rpmhpd SDM845_CX>; operating-points-v2 = <&qup_opp_table>; + interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; + interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; @@ -1520,6 +1610,10 @@ #size-cells = <0>; power-domains = <&rpmhpd SDM845_CX>; operating-points-v2 = <&qup_opp_table>; + interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, + <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; status = "disabled"; }; @@ -1533,6 +1627,9 @@ interrupts = ; #address-cells = <1>; #size-cells = <0>; + interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; + interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; @@ -1546,6 +1643,9 @@ interrupts = ; power-domains = <&rpmhpd SDM845_CX>; operating-points-v2 = <&qup_opp_table>; + interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; + interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; @@ -1561,6 +1661,10 @@ #size-cells = <0>; power-domains = <&rpmhpd SDM845_CX>; operating-points-v2 = <&qup_opp_table>; + interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, + <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; status = "disabled"; }; @@ -1574,6 +1678,9 @@ interrupts = ; #address-cells = <1>; #size-cells = <0>; + interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; + interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; @@ -1587,6 +1694,9 @@ interrupts = ; power-domains = <&rpmhpd SDM845_CX>; operating-points-v2 = <&qup_opp_table>; + interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; + interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; @@ -1602,6 +1712,10 @@ #size-cells = <0>; power-domains = <&rpmhpd SDM845_CX>; operating-points-v2 = <&qup_opp_table>; + interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, + <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; status = "disabled"; }; @@ -1615,6 +1729,9 @@ interrupts = ; #address-cells = <1>; #size-cells = <0>; + interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; + interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; @@ -1628,6 +1745,9 @@ interrupts = ; power-domains = <&rpmhpd SDM845_CX>; operating-points-v2 = <&qup_opp_table>; + interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; + interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; @@ -1643,6 +1763,10 @@ #size-cells = <0>; power-domains = <&rpmhpd SDM845_CX>; operating-points-v2 = <&qup_opp_table>; + interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, + <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; status = "disabled"; }; @@ -1656,6 +1780,9 @@ interrupts = ; #address-cells = <1>; #size-cells = <0>; + interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; + interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; @@ -1669,6 +1796,9 @@ interrupts = ; power-domains = <&rpmhpd SDM845_CX>; operating-points-v2 = <&qup_opp_table>; + interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; + interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; @@ -1684,6 +1814,10 @@ #size-cells = <0>; power-domains = <&rpmhpd SDM845_CX>; operating-points-v2 = <&qup_opp_table>; + interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, + <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; status = "disabled"; }; @@ -1697,6 +1831,9 @@ interrupts = ; #address-cells = <1>; #size-cells = <0>; + interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; + interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; @@ -1710,6 +1847,9 @@ interrupts = ; power-domains = <&rpmhpd SDM845_CX>; operating-points-v2 = <&qup_opp_table>; + interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; + interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; @@ -1725,6 +1865,10 @@ #size-cells = <0>; power-domains = <&rpmhpd SDM845_CX>; operating-points-v2 = <&qup_opp_table>; + interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, + <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; status = "disabled"; }; @@ -1738,6 +1882,9 @@ interrupts = ; #address-cells = <1>; #size-cells = <0>; + interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; + interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; @@ -1751,6 +1898,9 @@ interrupts = ; power-domains = <&rpmhpd SDM845_CX>; operating-points-v2 = <&qup_opp_table>; + interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; + interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; @@ -1767,6 +1917,10 @@ power-domains = <&rpmhpd SDM845_CX>; operating-points-v2 = <&qup_opp_table>; status = "disabled"; + interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, + <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; }; spi15: spi@a9c000 { @@ -1779,6 +1933,9 @@ interrupts = ; #address-cells = <1>; #size-cells = <0>; + interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; + interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; @@ -1792,6 +1949,9 @@ interrupts = ; power-domains = <&rpmhpd SDM845_CX>; operating-points-v2 = <&qup_opp_table>; + interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; + interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; }; From 74ab8ccfb8f3133acf8b2a2a7bcfba9c1710960d Mon Sep 17 00:00:00 2001 From: Kathiravan T Date: Mon, 30 Nov 2020 16:31:45 +0530 Subject: [PATCH 688/799] arm64: dts: ipq6018: Add the QPIC peripheral nodes Add the QPIC BAM and QPIC NAND controller support and enable the same in board DTS file. Co-developed-by: Anusha Canchi Ramachandra Rao Signed-off-by: Anusha Canchi Ramachandra Rao Signed-off-by: Kathiravan T Link: https://lore.kernel.org/r/1606734105-12414-2-git-send-email-kathirav@codeaurora.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts | 16 ++++++++ arch/arm64/boot/dts/qcom/ipq6018.dtsi | 41 ++++++++++++++++++++ 2 files changed, 57 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts b/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts index e8eaa958c199..99cefe88f6f2 100644 --- a/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts +++ b/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts @@ -62,3 +62,19 @@ bias-pull-down; }; }; + +&qpic_bam { + status = "okay"; +}; + +&qpic_nand { + status = "okay"; + + nand@0 { + reg = <0>; + + nand-ecc-strength = <4>; + nand-ecc-step-size = <512>; + nand-bus-width = <8>; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi index a94dac76bf3f..a366a05128c2 100644 --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi @@ -231,6 +231,17 @@ drive-strength = <8>; bias-pull-down; }; + + qpic_pins: qpic-pins { + pins = "gpio1", "gpio3", "gpio4", + "gpio5", "gpio6", "gpio7", + "gpio8", "gpio10", "gpio11", + "gpio12", "gpio13", "gpio14", + "gpio15", "gpio17"; + function = "qpic_pad"; + drive-strength = <8>; + bias-disable; + }; }; gcc: gcc@1800000 { @@ -332,6 +343,36 @@ status = "disabled"; }; + qpic_bam: dma-controller@7984000 { + compatible = "qcom,bam-v1.7.0"; + reg = <0x0 0x07984000 0x0 0x1a000>; + interrupts = ; + clocks = <&gcc GCC_QPIC_CLK>, + <&gcc GCC_QPIC_AHB_CLK>; + clock-names = "iface_clk", "bam_clk"; + #dma-cells = <1>; + qcom,ee = <0>; + status = "disabled"; + }; + + qpic_nand: nand@79b0000 { + compatible = "qcom,ipq6018-nand"; + reg = <0x0 0x079b0000 0x0 0x10000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&gcc GCC_QPIC_CLK>, + <&gcc GCC_QPIC_AHB_CLK>; + clock-names = "core", "aon"; + + dmas = <&qpic_bam 0>, + <&qpic_bam 1>, + <&qpic_bam 2>; + dma-names = "tx", "rx", "cmd"; + pinctrl-0 = <&qpic_pins>; + pinctrl-names = "default"; + status = "disabled"; + }; + intc: interrupt-controller@b000000 { compatible = "qcom,msm-qgic2"; interrupt-controller; From 96ddfbf46a35d75cd496efbd23d714271c0c0d46 Mon Sep 17 00:00:00 2001 From: Ajit Pandey Date: Fri, 18 Sep 2020 23:03:46 +0530 Subject: [PATCH 689/799] arm64: dts: qcom: sc7180: Add lpass cpu node for I2S driver Add the I2S controller node to sc7180 dtsi. Add pinmux for primary and secondary I2S. Reviewed-by: Srinivas Kandagatla Signed-off-by: Ajit Pandey Signed-off-by: Cheng-Yi Chiang Signed-off-by: V Sujith Kumar Reddy Signed-off-by: Srinivasa Rao Mandadapu Link: https://lore.kernel.org/r/1600450426-14063-1-git-send-email-srivasam@codeaurora.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc7180.dtsi | 69 ++++++++++++++++++++++++++++ 1 file changed, 69 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index c7c701e32b9a..22b832fc62e3 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -1854,6 +1854,45 @@ }; }; + sec_mi2s_active: sec-mi2s-active { + pinmux { + pins = "gpio49", "gpio50", "gpio51"; + function = "mi2s_1"; + }; + + pinconf { + pins = "gpio49", "gpio50", "gpio51"; + drive-strength = <8>; + bias-pull-up; + }; + }; + + pri_mi2s_active: pri-mi2s-active { + pinmux { + pins = "gpio53", "gpio54", "gpio55", "gpio56"; + function = "mi2s_0"; + }; + + pinconf { + pins = "gpio53", "gpio54", "gpio55", "gpio56"; + drive-strength = <8>; + bias-pull-up; + }; + }; + + pri_mi2s_mclk_active: pri-mi2s-mclk-active { + pinmux { + pins = "gpio57"; + function = "lpass_ext"; + }; + + pinconf { + pins = "gpio57"; + drive-strength = <8>; + bias-pull-up; + }; + }; + sdc1_on: sdc1-on { pinconf-clk { pins = "sdc1_clk"; @@ -3515,6 +3554,36 @@ #power-domain-cells = <1>; }; + lpass_cpu: lpass@62f00000 { + compatible = "qcom,sc7180-lpass-cpu"; + + reg = <0 0x62f00000 0 0x29000>; + reg-names = "lpass-lpaif"; + + iommus = <&apps_smmu 0x1020 0>; + + power-domains = <&lpass_hm LPASS_CORE_HM_GDSCR>; + + clocks = <&gcc GCC_LPASS_CFG_NOC_SWAY_CLK>, + <&lpasscc LPASS_AUDIO_CORE_CORE_CLK>, + <&lpasscc LPASS_AUDIO_CORE_EXT_MCLK0_CLK>, + <&lpasscc LPASS_AUDIO_CORE_SYSNOC_MPORT_CORE_CLK>, + <&lpasscc LPASS_AUDIO_CORE_LPAIF_PRI_IBIT_CLK>, + <&lpasscc LPASS_AUDIO_CORE_LPAIF_SEC_IBIT_CLK>; + + clock-names = "pcnoc-sway-clk", "audio-core", + "mclk0", "pcnoc-mport-clk", + "mi2s-bit-clk0", "mi2s-bit-clk1"; + + + #sound-dai-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + + interrupts = ; + interrupt-names = "lpass-irq-lpaif"; + }; + lpass_hm: clock-controller@63000000 { compatible = "qcom,sc7180-lpasshm"; reg = <0 0x63000000 0 0x28>; From 11d0e4f281565ef757479764ce7fd8d35eeb01b0 Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Mon, 30 Nov 2020 10:59:24 -0600 Subject: [PATCH 690/799] arm64: dts: qcom: c630: Polish i2c-hid devices The numbering of the i2c busses differs from ACPI and a number of typos was made in the original patch. Further more the irq flags for the various resources was not correct and i2c3 only has one of the two client devices active in any one device. Also label the various devices, for easier comparison with the ACPI tables. Tested-by: Steev Klimaszewski Fixes: 44acee207844 ("arm64: dts: qcom: Add Lenovo Yoga C630") Link: https://lore.kernel.org/r/20201130165924.319708-1-bjorn.andersson@linaro.org Signed-off-by: Bjorn Andersson --- .../boot/dts/qcom/sdm850-lenovo-yoga-c630.dts | 31 +++++++++++-------- 1 file changed, 18 insertions(+), 13 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts b/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts index 3850e74ed653..f8a371078a08 100644 --- a/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts +++ b/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts @@ -282,23 +282,28 @@ status = "okay"; clock-frequency = <400000>; - hid@15 { + tsel: hid@15 { compatible = "hid-over-i2c"; reg = <0x15>; hid-descr-addr = <0x1>; - interrupts-extended = <&tlmm 37 IRQ_TYPE_EDGE_RISING>; + interrupts-extended = <&tlmm 37 IRQ_TYPE_LEVEL_HIGH>; + + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_hid_active>; }; - hid@2c { + tsc2: hid@2c { compatible = "hid-over-i2c"; reg = <0x2c>; hid-descr-addr = <0x20>; - interrupts-extended = <&tlmm 37 IRQ_TYPE_EDGE_RISING>; + interrupts-extended = <&tlmm 37 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default"; - pinctrl-0 = <&i2c2_hid_active>; + pinctrl-0 = <&i2c3_hid_active>; + + status = "disabled"; }; }; @@ -306,15 +311,15 @@ status = "okay"; clock-frequency = <400000>; - hid@10 { + tsc1: hid@10 { compatible = "hid-over-i2c"; reg = <0x10>; hid-descr-addr = <0x1>; - interrupts-extended = <&tlmm 125 IRQ_TYPE_EDGE_FALLING>; + interrupts-extended = <&tlmm 125 IRQ_TYPE_LEVEL_LOW>; pinctrl-names = "default"; - pinctrl-0 = <&i2c6_hid_active>; + pinctrl-0 = <&i2c5_hid_active>; }; }; @@ -322,7 +327,7 @@ status = "okay"; clock-frequency = <400000>; - hid@5c { + ecsh: hid@5c { compatible = "hid-over-i2c"; reg = <0x5c>; hid-descr-addr = <0x1>; @@ -330,7 +335,7 @@ interrupts-extended = <&tlmm 92 IRQ_TYPE_LEVEL_LOW>; pinctrl-names = "default"; - pinctrl-0 = <&i2c12_hid_active>; + pinctrl-0 = <&i2c11_hid_active>; }; }; @@ -444,7 +449,7 @@ &tlmm { gpio-reserved-ranges = <0 4>, <81 4>; - i2c2_hid_active: i2c2-hid-active { + i2c3_hid_active: i2c2-hid-active { pins = <37>; function = "gpio"; @@ -453,7 +458,7 @@ drive-strength = <2>; }; - i2c6_hid_active: i2c6-hid-active { + i2c5_hid_active: i2c5-hid-active { pins = <125>; function = "gpio"; @@ -462,7 +467,7 @@ drive-strength = <2>; }; - i2c12_hid_active: i2c12-hid-active { + i2c11_hid_active: i2c11-hid-active { pins = <92>; function = "gpio"; From f55d373f7953909160cb4c1398f62123cdbe7650 Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Mon, 30 Nov 2020 11:00:28 -0600 Subject: [PATCH 691/799] arm64: dts: qcom: c630: Fix pinctrl pins properties The "pins" property takes an array of pin _names_, not pin numbers. Fix this. Tested-by: Steev Klimaszewski Fixes: 44acee207844 ("arm64: dts: qcom: Add Lenovo Yoga C630") Link: https://lore.kernel.org/r/20201130170028.319798-1-bjorn.andersson@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts b/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts index f8a371078a08..44fc5aaaf1c6 100644 --- a/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts +++ b/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts @@ -450,7 +450,7 @@ gpio-reserved-ranges = <0 4>, <81 4>; i2c3_hid_active: i2c2-hid-active { - pins = <37>; + pins = "gpio37"; function = "gpio"; input-enable; @@ -459,7 +459,7 @@ }; i2c5_hid_active: i2c5-hid-active { - pins = <125>; + pins = "gpio125"; function = "gpio"; input-enable; @@ -468,7 +468,7 @@ }; i2c11_hid_active: i2c11-hid-active { - pins = <92>; + pins = "gpio92"; function = "gpio"; input-enable; @@ -477,7 +477,7 @@ }; wcd_intr_default: wcd_intr_default { - pins = <54>; + pins = "gpio54"; function = "gpio"; input-enable; From 956e9c85f47bfe874d58d96c85471f2e2ebae626 Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Fri, 27 Nov 2020 21:42:31 -0600 Subject: [PATCH 692/799] arm64: dts: qcom: c630: Define eDP bridge and panel The Lenovo Yoga C630 drives the Boe NV133FHM-N61 eDP display from DSI using a TI SN65DSI86 bridge chip on I2C 10. Define the bridge and eDP panel and enable the display blocks. Tested-by: Steev Klimaszewski Acked-by: Shawn Guo Link: https://lore.kernel.org/r/20201128034231.89750-1-bjorn.andersson@linaro.org Signed-off-by: Bjorn Andersson --- .../boot/dts/qcom/sdm850-lenovo-yoga-c630.dts | 100 ++++++++++++++++++ 1 file changed, 100 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts b/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts index 44fc5aaaf1c6..13fdd02cffe6 100644 --- a/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts +++ b/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts @@ -44,6 +44,26 @@ linux,code = ; }; }; + + panel { + compatible = "boe,nv133fhm-n61"; + no-hpd; + + ports { + port { + panel_in_edp: endpoint { + remote-endpoint = <&sn65dsi86_out>; + }; + }; + }; + }; + + sn65dsi86_refclk: sn65dsi86-refclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + + clock-frequency = <19200000>; + }; }; &adsp_pas { @@ -260,6 +280,25 @@ status = "okay"; }; +&dsi0 { + status = "okay"; + vdda-supply = <&vreg_l26a_1p2>; + + ports { + port@1 { + endpoint { + remote-endpoint = <&sn65dsi86_in_a>; + data-lanes = <0 1 2 3>; + }; + }; + }; +}; + +&dsi0_phy { + status = "okay"; + vdds-supply = <&vreg_l1a_0p875>; +}; + &gcc { protected-clocks = , , @@ -323,6 +362,45 @@ }; }; +&i2c10 { + status = "okay"; + clock-frequency = <400000>; + + sn65dsi86: bridge@2c { + compatible = "ti,sn65dsi86"; + reg = <0x2c>; + pinctrl-names = "default"; + pinctrl-0 = <&sn65dsi86_pin_active>; + + enable-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>; + + vpll-supply = <&vreg_l14a_1p88>; + vccio-supply = <&vreg_l14a_1p88>; + + clocks = <&sn65dsi86_refclk>; + clock-names = "refclk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + sn65dsi86_in_a: endpoint { + remote-endpoint = <&dsi0_out>; + }; + }; + + port@1 { + reg = <1>; + sn65dsi86_out: endpoint { + remote-endpoint = <&panel_in_edp>; + }; + }; + }; + }; +}; + &i2c11 { status = "okay"; clock-frequency = <400000>; @@ -339,10 +417,26 @@ }; }; +&mdss { + status = "okay"; +}; + +&mdss_mdp { + status = "okay"; +}; + &mss_pil { firmware-name = "qcom/LENOVO/81JL/qcdsp1v2850.mbn", "qcom/LENOVO/81JL/qcdsp2850.mbn"; }; +&qup_i2c10_default { + pinconf { + pins = "gpio55", "gpio56"; + drive-strength = <2>; + bias-disable; + }; +}; + &qup_i2c12_default { drive-strength = <2>; bias-disable; @@ -449,6 +543,12 @@ &tlmm { gpio-reserved-ranges = <0 4>, <81 4>; + sn65dsi86_pin_active: sn65dsi86-enable { + pins = "gpio96"; + drive-strength = <2>; + bias-disable; + }; + i2c3_hid_active: i2c2-hid-active { pins = "gpio37"; function = "gpio"; From eeffc0fbd022422777b91cdfa0e12ba2bcd6c5e7 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Fri, 23 Oct 2020 23:48:13 +0530 Subject: [PATCH 693/799] arm64: defconfig: Enable RTC_DRV_HYM8563 RTC HYM8563 used in the ARM64 Rockchip SoC's SDIO power sequence enablement. Enable it as module. Signed-off-by: Jagan Teki Link: https://lore.kernel.org/r/20201023181814.220974-1-jagan@amarulasolutions.com Signed-off-by: Heiko Stuebner --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 15c2128e846a..24ce73369fc9 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -815,6 +815,7 @@ CONFIG_EDAC=y CONFIG_EDAC_GHES=y CONFIG_RTC_CLASS=y CONFIG_RTC_DRV_DS1307=m +CONFIG_RTC_DRV_HYM8563=m CONFIG_RTC_DRV_MAX77686=y CONFIG_RTC_DRV_RK808=m CONFIG_RTC_DRV_PCF85363=m From 287eb2be4037c3d8d96b5d9490fa0e695e4553b9 Mon Sep 17 00:00:00 2001 From: Christian Hewitt Date: Mon, 16 Nov 2020 06:41:47 +0000 Subject: [PATCH 694/799] arm64: dts: meson: enable rtc node on Khadas VIM1/VIM2 boards Enable the rtc node on VIM1/VIM2 boards so users can simply attach a power cell and use the on-board RTC without modifying the device-tree. Cold boot with no cell attached is gracefully handled: VIM2:~ # dmesg | grep rtc [ 7.716150] rtc-hym8563 1-0051: no valid clock/calendar values available [ 7.716957] rtc-hym8563 1-0051: registered as rtc0 [ 7.729850] rtc-hym8563 1-0051: no valid clock/calendar values available [ 7.729877] rtc-hym8563 1-0051: hctosys: unable to read the hardware clock [ 8.126768] rtc-hym8563 1-0051: no valid clock/calendar values available Warm boot (and any boot with cell attached) recalls stored values resulting in consistently faster (re)boot times: VIM2:~ # dmesg | grep rtc [ 7.441671] rtc-hym8563 1-0051: registered as rtc0 [ 7.442663] rtc-hym8563 1-0051: setting system clock to 2020-11-16T05:49:59 UTC (1605505799) Suggested-by: Artem Lapkin Signed-off-by: Christian Hewitt Reviewed-by: Neil Armstrong Signed-off-by: Kevin Hilman Link: https://lore.kernel.org/r/20201116064147.12062-1-christianshewitt@gmail.com --- arch/arm64/boot/dts/amlogic/meson-gxl-s905x-khadas-vim.dts | 3 +-- arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts | 3 +-- 2 files changed, 2 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-khadas-vim.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-khadas-vim.dts index 8bcdffdf55d0..638a5992d760 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-khadas-vim.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-khadas-vim.dts @@ -97,8 +97,7 @@ pinctrl-names = "default"; rtc: rtc@51 { - /* has to be enabled manually when a battery is connected: */ - status = "disabled"; + status = "okay"; compatible = "haoyu,hym8563"; reg = <0x51>; #clock-cells = <0>; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts b/arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts index bff8ec2c1c70..da000c10b945 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts @@ -228,8 +228,7 @@ pinctrl-names = "default"; rtc: rtc@51 { - /* has to be enabled manually when a battery is connected: */ - status = "disabled"; + status = "okay"; compatible = "haoyu,hym8563"; reg = <0x51>; #clock-cells = <0>; From 78a6dcb52736da4d54e0b42788a4c5f13da9a8e1 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Fri, 20 Nov 2020 16:21:30 +0100 Subject: [PATCH 695/799] arm64: dts: meson-axg: add PWRC node This adds the power controller PWRC node and the corresponding ethernet power domain. Signed-off-by: Neil Armstrong Signed-off-by: Kevin Hilman Link: https://lore.kernel.org/r/20201120152131.3918814-2-narmstrong@baylibre.com --- arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 42 ++++++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi index 724ee179b316..fed9e6edbfa9 100644 --- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi @@ -12,6 +12,7 @@ #include #include #include +#include / { compatible = "amlogic,meson-axg"; @@ -229,6 +230,7 @@ tx-fifo-depth = <2048>; resets = <&reset RESET_ETHERNET>; reset-names = "stmmaceth"; + power-domains = <&pwrc PWRC_AXG_ETHERNET_MEM_ID>; status = "disabled"; }; @@ -1159,6 +1161,46 @@ clocks = <&xtal>; clock-names = "xtal"; }; + + pwrc: power-controller { + compatible = "amlogic,meson-axg-pwrc"; + #power-domain-cells = <1>; + amlogic,ao-sysctrl = <&sysctrl_AO>; + resets = <&reset RESET_VIU>, + <&reset RESET_VENC>, + <&reset RESET_VCBUS>, + <&reset RESET_VENCL>, + <&reset RESET_VID_LOCK>; + reset-names = "viu", "venc", "vcbus", + "vencl", "vid_lock"; + clocks = <&clkc CLKID_VPU>, + <&clkc CLKID_VAPB>; + clock-names = "vpu", "vapb"; + /* + * VPU clocking is provided by two identical clock paths + * VPU_0 and VPU_1 muxed to a single clock by a glitch + * free mux to safely change frequency while running. + * Same for VAPB but with a final gate after the glitch free mux. + */ + assigned-clocks = <&clkc CLKID_VPU_0_SEL>, + <&clkc CLKID_VPU_0>, + <&clkc CLKID_VPU>, /* Glitch free mux */ + <&clkc CLKID_VAPB_0_SEL>, + <&clkc CLKID_VAPB_0>, + <&clkc CLKID_VAPB_SEL>; /* Glitch free mux */ + assigned-clock-parents = <&clkc CLKID_FCLK_DIV4>, + <0>, /* Do Nothing */ + <&clkc CLKID_VPU_0>, + <&clkc CLKID_FCLK_DIV4>, + <0>, /* Do Nothing */ + <&clkc CLKID_VAPB_0>; + assigned-clock-rates = <0>, /* Do Nothing */ + <250000000>, + <0>, /* Do Nothing */ + <0>, /* Do Nothing */ + <250000000>, + <0>; /* Do Nothing */ + }; }; }; From 3d3f1dfa0897bd14eebc3e79b38ae90a2eac67c5 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Fri, 20 Nov 2020 16:21:31 +0100 Subject: [PATCH 696/799] arm64: dts: meson-axg: add MIPI DSI PHY nodes This adds the nodes for : - MIPI DSI+PCIe analog phy - MIPI D-PHY Signed-off-by: Neil Armstrong Signed-off-by: Kevin Hilman Link: https://lore.kernel.org/r/20201120152131.3918814-3-narmstrong@baylibre.com --- arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi index fed9e6edbfa9..f22481c4054f 100644 --- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi @@ -1201,6 +1201,12 @@ <250000000>, <0>; /* Do Nothing */ }; + + mipi_pcie_analog_dphy: phy { + compatible = "amlogic,axg-mipi-pcie-analog-phy"; + #phy-cells = <0>; + status = "disabled"; + }; }; }; @@ -1213,6 +1219,19 @@ #mbox-cells = <1>; }; + mipi_dphy: phy@ff640000 { + compatible = "amlogic,axg-mipi-dphy"; + reg = <0x0 0xff640000 0x0 0x100>; + clocks = <&clkc CLKID_MIPI_DSI_PHY>; + clock-names = "pclk"; + resets = <&reset RESET_MIPI_PHY>; + reset-names = "phy"; + phys = <&mipi_pcie_analog_dphy>; + phy-names = "analog"; + #phy-cells = <0>; + status = "disabled"; + }; + audio: bus@ff642000 { compatible = "simple-bus"; reg = <0x0 0xff642000 0x0 0x2000>; From 5b3a9c20926e78f9d226b1853386dee6d22df9c3 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Fri, 20 Nov 2020 16:32:28 +0100 Subject: [PATCH 697/799] arm64: dts: meson-axg: add PCIe nodes This adds the nodes for the : - AXG PCIe PHY, using the shared analog PCIe/MIPI DSI PHY - 2x AXG PCIe controllers Signed-off-by: Neil Armstrong Signed-off-by: Kevin Hilman Link: https://lore.kernel.org/r/20201120153229.3920123-4-narmstrong@baylibre.com --- arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 61 ++++++++++++++++++++++ 1 file changed, 61 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi index f22481c4054f..bd8c4ac128a8 100644 --- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi @@ -172,6 +172,58 @@ #size-cells = <2>; ranges; + pcieA: pcie@f9800000 { + compatible = "amlogic,axg-pcie", "snps,dw-pcie"; + reg = <0x0 0xf9800000 0x0 0x400000>, + <0x0 0xff646000 0x0 0x2000>, + <0x0 0xf9f00000 0x0 0x100000>; + reg-names = "elbi", "cfg", "config"; + interrupts = ; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 179 IRQ_TYPE_EDGE_RISING>; + bus-range = <0x0 0xff>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges = <0x82000000 0 0xf9c00000 0x0 0xf9c00000 0 0x00300000>; + + clocks = <&clkc CLKID_USB>, <&clkc CLKID_PCIE_A>, <&clkc CLKID_PCIE_CML_EN0>; + clock-names = "general", "pclk", "port"; + resets = <&reset RESET_PCIE_A>, <&reset RESET_PCIE_APB>; + reset-names = "port", "apb"; + num-lanes = <1>; + phys = <&pcie_phy>; + phy-names = "pcie"; + status = "disabled"; + }; + + pcieB: pcie@fa000000 { + compatible = "amlogic,axg-pcie", "snps,dw-pcie"; + reg = <0x0 0xfa000000 0x0 0x400000>, + <0x0 0xff648000 0x0 0x2000>, + <0x0 0xfa400000 0x0 0x100000>; + reg-names = "elbi", "cfg", "config"; + interrupts = ; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 169 IRQ_TYPE_EDGE_RISING>; + bus-range = <0x0 0xff>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges = <0x82000000 0 0xfa500000 0x0 0xfa500000 0 0x00300000>; + + clocks = <&clkc CLKID_USB>, <&clkc CLKID_PCIE_B>, <&clkc CLKID_PCIE_CML_EN1>; + clock-names = "general", "pclk", "port"; + resets = <&reset RESET_PCIE_B>, <&reset RESET_PCIE_APB>; + reset-names = "port", "apb"; + num-lanes = <1>; + phys = <&pcie_phy>; + phy-names = "pcie"; + status = "disabled"; + }; + usb: usb@ffe09080 { compatible = "amlogic,meson-axg-usb-ctrl"; reg = <0x0 0xffe09080 0x0 0x20>; @@ -234,6 +286,15 @@ status = "disabled"; }; + pcie_phy: phy@ff644000 { + compatible = "amlogic,axg-pcie-phy"; + reg = <0x0 0xff644000 0x0 0x1c>; + resets = <&reset RESET_PCIE_PHY>; + phys = <&mipi_pcie_analog_dphy>; + phy-names = "analog"; + #phy-cells = <0>; + }; + pdm: audio-controller@ff632000 { compatible = "amlogic,axg-pdm"; reg = <0x0 0xff632000 0x0 0x34>; From 9715b01da6cfb361b2a09fe2ad94287d6fa72261 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Fri, 20 Nov 2020 16:32:29 +0100 Subject: [PATCH 698/799] arm64: dts: meson-axg-s400: enable PCIe M.2 Key E slots Signed-off-by: Neil Armstrong Signed-off-by: Kevin Hilman Link: https://lore.kernel.org/r/20201120153229.3920123-5-narmstrong@baylibre.com --- arch/arm64/boot/dts/amlogic/meson-axg-s400.dts | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts index 7740f97c240f..359589d1dfa9 100644 --- a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts +++ b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts @@ -441,6 +441,16 @@ status = "okay"; }; +&pcieA { + reset-gpios = <&gpio GPIOX_19 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&pcieB { + reset-gpios = <&gpio GPIOZ_10 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>; + status = "okay"; +}; + &pwm_ab { status = "okay"; pinctrl-0 = <&pwm_a_x20_pins>; From 4592bfe9d9f3359ae9db4620a405441530207733 Mon Sep 17 00:00:00 2001 From: Christian Hewitt Date: Tue, 24 Nov 2020 12:17:40 +0000 Subject: [PATCH 699/799] arm64: dts: meson: Add capacity-dmips-mhz attributes to GXM GXM (S912) is a big-little design with CPUs 0-3 clocked at 1.5GHz and CPUs 4-7 at 1.0GHz. Adding capacity-dmips-mhz attributes allows the scheduler to factor the different clock speeds into capacity calculations and prefer the higher-clocked cluster to improve overall performance. This was inspired by the similar change for G12B [0] boards. The diference here is that all cores are A53's so the same dmips-mhz value is used. VIM2:~ # cat /sys/devices/system/cpu/cpu*/cpufreq/scaling_cur_freq 1512000 1512000 1512000 1512000 1000000 1000000 1000000 1000000 before: VIM2:~ # cat /sys/devices/system/cpu/cpu*/cpu_capacity 1024 1024 1024 1024 1024 1024 1024 1024 after: VIM2:~ # cat /sys/devices/system/cpu/cpu*/cpu_capacity 1024 1024 1024 1024 677 677 677 677 The after value matches my table-napkin calculation: (1000000 / 1512000 = 0.661) * 1024 = 677 [0] https://github.com/torvalds/linux/commit/6eeaf4d2452ec8b1ece58776812140734fc2e088 Signed-off-by: Christian Hewitt Reviewed-by: Neil Armstrong Signed-off-by: Kevin Hilman Link: https://lore.kernel.org/r/20201124121740.25704-1-christianshewitt@gmail.com --- arch/arm64/boot/dts/amlogic/meson-gxm.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxm.dtsi index fe4145112295..411cc312fc62 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxm.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gxm.dtsi @@ -42,11 +42,28 @@ }; }; + cpu0: cpu@0 { + capacity-dmips-mhz = <1024>; + }; + + cpu1: cpu@1 { + capacity-dmips-mhz = <1024>; + }; + + cpu2: cpu@2 { + capacity-dmips-mhz = <1024>; + }; + + cpu3: cpu@3 { + capacity-dmips-mhz = <1024>; + }; + cpu4: cpu@100 { device_type = "cpu"; compatible = "arm,cortex-a53"; reg = <0x0 0x100>; enable-method = "psci"; + capacity-dmips-mhz = <1024>; next-level-cache = <&l2>; clocks = <&scpi_dvfs 1>; #cooling-cells = <2>; @@ -57,6 +74,7 @@ compatible = "arm,cortex-a53"; reg = <0x0 0x101>; enable-method = "psci"; + capacity-dmips-mhz = <1024>; next-level-cache = <&l2>; clocks = <&scpi_dvfs 1>; #cooling-cells = <2>; @@ -67,6 +85,7 @@ compatible = "arm,cortex-a53"; reg = <0x0 0x102>; enable-method = "psci"; + capacity-dmips-mhz = <1024>; next-level-cache = <&l2>; clocks = <&scpi_dvfs 1>; #cooling-cells = <2>; @@ -77,6 +96,7 @@ compatible = "arm,cortex-a53"; reg = <0x0 0x103>; enable-method = "psci"; + capacity-dmips-mhz = <1024>; next-level-cache = <&l2>; clocks = <&scpi_dvfs 1>; #cooling-cells = <2>; From a6077652cb6595b1d668af41a3978dd965d57b9e Mon Sep 17 00:00:00 2001 From: Christian Hewitt Date: Tue, 24 Nov 2020 14:53:38 +0000 Subject: [PATCH 700/799] arm64: dts: meson: add rtc aliases to meson-khadas-vim3.dtsi Tweak the node name to make it aliasable, then add aliases for the on-board RTC chip and meson-vrtc timer so they probe as rtc0 and rtc1 respectively. before: VIM3:~ # dmesg | grep rtc [ 3.622530] meson-vrtc ff8000a8.rtc: registered as rtc0 [ 3.622574] meson-vrtc ff8000a8.rtc: setting system clock to 1970-01-01T00:00:03 UTC (3) [ 3.646936] rtc-hym8563 0-0051: no valid clock/calendar values available [ 3.647125] rtc-hym8563 0-0051: registered as rtc1 [ 3.852382] rtc-hym8563 0-0051: no valid clock/calendar values available after: VIM3:~ # dmesg | grep rtc [ 3.583735] meson-vrtc ff8000a8.rtc: registered as rtc1 [ 3.633888] rtc-hym8563 0-0051: no valid clock/calendar values available [ 3.634120] rtc-hym8563 0-0051: registered as rtc0 [ 3.635250] rtc-hym8563 0-0051: no valid clock/calendar values available [ 3.635267] rtc-hym8563 0-0051: hctosys: unable to read the hardware clock [ 3.852632] rtc-hym8563 0-0051: no valid clock/calendar values available Signed-off-by: Christian Hewitt Signed-off-by: Kevin Hilman Link: https://lore.kernel.org/r/20201124145338.17137-1-christianshewitt@gmail.com --- arch/arm64/boot/dts/amlogic/meson-khadas-vim3.dtsi | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/amlogic/meson-khadas-vim3.dtsi b/arch/arm64/boot/dts/amlogic/meson-khadas-vim3.dtsi index 7b46555ac55a..87bd8c9516f2 100644 --- a/arch/arm64/boot/dts/amlogic/meson-khadas-vim3.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-khadas-vim3.dtsi @@ -13,6 +13,8 @@ aliases { serial0 = &uart_AO; ethernet0 = ðmac; + rtc0 = &rtc; + rtc1 = &vrtc; }; chosen { @@ -330,7 +332,7 @@ #gpio-cells = <2>; }; - rtc@51 { + rtc: rtc@51 { compatible = "haoyu,hym8563"; reg = <0x51>; #clock-cells = <0>; From b6c605e00ce8910d7ec3d9a54725d78b14db49b9 Mon Sep 17 00:00:00 2001 From: Artem Lapkin Date: Wed, 25 Nov 2020 02:40:01 +0000 Subject: [PATCH 701/799] arm64: dts: meson: fix spi-max-frequency on Khadas VIM2 The max frequency for the w25q32 (VIM v1.2) and w25q128 (VIM v1.4) spifc chip should be 104Mhz not 30MHz. Fixes: b8b74dda3908 ("ARM64: dts: meson-gxm: Add support for Khadas VIM2") Signed-off-by: Artem Lapkin Reviewed-by: Neil Armstrong Signed-off-by: Kevin Hilman Link: https://lore.kernel.org/r/20201125024001.19036-1-christianshewitt@gmail.com --- arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts b/arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts index da000c10b945..c5ee55caae0a 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts @@ -340,7 +340,7 @@ #size-cells = <1>; compatible = "winbond,w25q16", "jedec,spi-nor"; reg = <0>; - spi-max-frequency = <3000000>; + spi-max-frequency = <104000000>; }; }; From 6714f28178889da983d020fd9cf3bf7ae1a8c49d Mon Sep 17 00:00:00 2001 From: Christian Hewitt Date: Wed, 25 Nov 2020 05:29:14 +0000 Subject: [PATCH 702/799] arm64: dts: meson: update the Khadas VIM3/3L LED bindings Update the VIM3/3L common dtsi to use the new function/color bindings. Suggested-by: Artem Lapkin Signed-off-by: Christian Hewitt Reviewed-by: Neil Armstrong Signed-off-by: Kevin Hilman Link: https://lore.kernel.org/r/20201125052914.4092-1-christianshewitt@gmail.com --- arch/arm64/boot/dts/amlogic/meson-khadas-vim3.dtsi | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/amlogic/meson-khadas-vim3.dtsi b/arch/arm64/boot/dts/amlogic/meson-khadas-vim3.dtsi index 87bd8c9516f2..8f8656262ae7 100644 --- a/arch/arm64/boot/dts/amlogic/meson-khadas-vim3.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-khadas-vim3.dtsi @@ -6,6 +6,7 @@ */ #include +#include #include #include @@ -42,14 +43,16 @@ leds { compatible = "gpio-leds"; - led-white { - label = "vim3:white:sys"; + white { + color = ; + function = LED_FUNCTION_STATUS; gpios = <&gpio_ao GPIOAO_4 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; - led-red { - label = "vim3:red"; + red { + color = ; + function = LED_FUNCTION_STATUS; gpios = <&gpio_expander 5 GPIO_ACTIVE_HIGH>; }; }; From 2493a9a515cf2bfa958d1d68beab507a1c7f5962 Mon Sep 17 00:00:00 2001 From: Christian Hewitt Date: Thu, 26 Nov 2020 05:04:40 +0000 Subject: [PATCH 703/799] arm64: dts: meson: add KHAMSIN IR remote node to SML5442TW Set the IR keymap to the KHAMSIN remote shipped with the SML5442TW. Signed-off-by: Christian Hewitt Signed-off-by: Kevin Hilman Link: https://lore.kernel.org/r/20201126050440.6273-1-christianshewitt@gmail.com --- arch/arm64/boot/dts/amlogic/meson-gxl-s905d-sml5442tw.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-sml5442tw.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-sml5442tw.dts index 0b95e9ecbef0..ad6d72254150 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-sml5442tw.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-sml5442tw.dts @@ -63,6 +63,10 @@ pinctrl-names = "default"; }; +&ir { + linux,rc-map-name = "rc-khamsin"; +}; + /* This is connected to the Bluetooth module: */ &uart_A { status = "okay"; From b6a1c8a1eaa73b1e2ae251399308e9445d74cef7 Mon Sep 17 00:00:00 2001 From: Dongjin Kim Date: Mon, 30 Nov 2020 15:03:20 +0900 Subject: [PATCH 704/799] arm64: dts: meson-sm1: fix typo in opp table The freqency 1512000000 should be 1500000000. Signed-off-by: Dongjin Kim Fixes: 3d9e76483049 ("arm64: dts: meson-sm1-sei610: enable DVFS") Reviewed-by: Neil Armstrong Signed-off-by: Kevin Hilman Link: https://lore.kernel.org/r/20201130060320.GA30098@anyang-linuxfactory-or-kr --- arch/arm64/boot/dts/amlogic/meson-sm1.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi b/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi index 71317f5aada1..c309517abae3 100644 --- a/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi @@ -130,7 +130,7 @@ opp-microvolt = <790000>; }; - opp-1512000000 { + opp-1500000000 { opp-hz = /bits/ 64 <1500000000>; opp-microvolt = <800000>; }; From eecc662ff38b498e1fcd971caec3ce448e711d0e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Guido=20G=C3=BCnther?= Date: Sat, 28 Nov 2020 19:56:23 +0100 Subject: [PATCH 705/799] arm64: defconfig: Enable more Librem 5 hardware MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This enables - CONFIG_BATTERY_MAX17042: battery chip - CONFIG_CHARGER_BQ25980: charge controller - CONFIG_DRM_PANEL_MANTIX_MLAF057WE5: LCD panel - CONFIG_GNSS/CONFIG_GNSS_MTK_SERIAL: GNSS receiver - CONFIG_IIO_ST_LSM6DSX: IMU - CONFIG_IMX_DCSS: 2nd display controller - CONFIG_LEDS_LM3692X: LCD backlight - CONFIG_REGULATOR_TPS65132: regulator for the LCD panel - CONFIG_TOUCHSCREEN_EDT_FT5X06: touch controller - CONFIG_TYPEC_TPS6598X: USB PD controller - CONFIG_VCNL4000: ambient light and proximity sensor as modules. Signed-off-by: Guido Günther Signed-off-by: Shawn Guo --- arch/arm64/configs/defconfig | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 270d326d5f28..34b837b866c2 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -240,6 +240,8 @@ CONFIG_HISILICON_LPC=y CONFIG_SIMPLE_PM_BUS=y CONFIG_FSL_MC_BUS=y CONFIG_TEGRA_ACONNECT=m +CONFIG_GNSS=m +CONFIG_GNSS_MTK_SERIAL=m CONFIG_MTD=y CONFIG_MTD_BLOCK=y CONFIG_MTD_CFI=y @@ -381,6 +383,7 @@ CONFIG_KEYBOARD_IMX_SC_KEY=m CONFIG_KEYBOARD_CROS_EC=y CONFIG_INPUT_TOUCHSCREEN=y CONFIG_TOUCHSCREEN_ATMEL_MXT=m +CONFIG_TOUCHSCREEN_EDT_FT5X06=m CONFIG_INPUT_MISC=y CONFIG_INPUT_PM8941_PWRKEY=y CONFIG_INPUT_PM8XXX_VIBRATOR=m @@ -521,6 +524,8 @@ CONFIG_POWER_RESET_SYSCON=y CONFIG_SYSCON_REBOOT_MODE=y CONFIG_BATTERY_SBS=m CONFIG_BATTERY_BQ27XXX=y +CONFIG_BATTERY_MAX17042=m +CONFIG_CHARGER_BQ25980=m CONFIG_SENSORS_ARM_SCPI=y CONFIG_SENSORS_LM90=m CONFIG_SENSORS_PWM_FAN=m @@ -595,6 +600,7 @@ CONFIG_REGULATOR_QCOM_SMD_RPM=y CONFIG_REGULATOR_QCOM_SPMI=y CONFIG_REGULATOR_RK808=y CONFIG_REGULATOR_S2MPS11=y +CONFIG_REGULATOR_TPS65132=m CONFIG_REGULATOR_VCTRL=m CONFIG_RC_CORE=m CONFIG_RC_DECODERS=y @@ -655,6 +661,7 @@ CONFIG_DRM_MSM=m CONFIG_DRM_TEGRA=m CONFIG_DRM_PANEL_LVDS=m CONFIG_DRM_PANEL_SIMPLE=m +CONFIG_DRM_PANEL_MANTIX_MLAF057WE51=m CONFIG_DRM_PANEL_RAYDIUM_RM67191=m CONFIG_DRM_PANEL_SITRONIX_ST7703=m CONFIG_DRM_PANEL_TRULY_NT35597_WQXGA=m @@ -669,6 +676,7 @@ CONFIG_DRM_I2C_ADV7511=m CONFIG_DRM_I2C_ADV7511_AUDIO=y CONFIG_DRM_DW_HDMI_AHB_AUDIO=m CONFIG_DRM_DW_HDMI_CEC=m +CONFIG_DRM_IMX_DCSS=m CONFIG_DRM_VC4=m CONFIG_DRM_ETNAVIV=m CONFIG_DRM_HISI_HIBMC=m @@ -777,6 +785,7 @@ CONFIG_TYPEC=m CONFIG_TYPEC_TCPM=m CONFIG_TYPEC_FUSB302=m CONFIG_TYPEC_HD3SS3220=m +CONFIG_TYPEC_TPS6598X=m CONFIG_MMC=y CONFIG_MMC_BLOCK_MINORS=32 CONFIG_MMC_ARMMMCI=y @@ -806,6 +815,7 @@ CONFIG_MMC_SDHCI_AM654=y CONFIG_MMC_OWL=y CONFIG_NEW_LEDS=y CONFIG_LEDS_CLASS=y +CONFIG_LEDS_LM3692X=m CONFIG_LEDS_GPIO=y CONFIG_LEDS_PWM=y CONFIG_LEDS_SYSCON=y @@ -978,8 +988,10 @@ CONFIG_QCOM_SPMI_ADC5=m CONFIG_ROCKCHIP_SARADC=m CONFIG_IIO_CROS_EC_SENSORS_CORE=m CONFIG_IIO_CROS_EC_SENSORS=m +CONFIG_IIO_ST_LSM6DSX=m CONFIG_IIO_CROS_EC_LIGHT_PROX=m CONFIG_SENSORS_ISL29018=m +CONFIG_VCNL4000=m CONFIG_IIO_CROS_EC_BARO=m CONFIG_MPL3115=m CONFIG_PWM=y From 708ed2649ad86dad2284acac6e4e6829a3cfd604 Mon Sep 17 00:00:00 2001 From: Marco Felsch Date: Thu, 26 Nov 2020 20:22:52 +0100 Subject: [PATCH 706/799] ARM: dts: imx6qdl-kontron-samx6i: increase i2c-frequency Set it to max. allowed 375kHz for faster transfers. The limit is given by the erratum [1]. [1] https://www.nxp.com/docs/en/errata/IMX6DQCE.pdf Signed-off-by: Marco Felsch Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-kontron-samx6i.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/imx6qdl-kontron-samx6i.dtsi b/arch/arm/boot/dts/imx6qdl-kontron-samx6i.dtsi index 265f5f3dbff6..b6a0b8809e74 100644 --- a/arch/arm/boot/dts/imx6qdl-kontron-samx6i.dtsi +++ b/arch/arm/boot/dts/imx6qdl-kontron-samx6i.dtsi @@ -390,21 +390,21 @@ /* I2C_GP */ &i2c1 { - clock-frequency = <100000>; + clock-frequency = <375000>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c1>; }; /* HDMI_CTRL */ &i2c2 { - clock-frequency = <100000>; + clock-frequency = <375000>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c2>; }; /* I2C_PM */ &i2c3 { - clock-frequency = <100000>; + clock-frequency = <375000>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c3>; status = "okay"; From af038154171ae22642596ebaff5f2e273fc2b602 Mon Sep 17 00:00:00 2001 From: Oleksij Rempel Date: Tue, 17 Nov 2020 14:13:52 +0100 Subject: [PATCH 707/799] dt-bindings: vendor-prefixes: add "virtual" prefix "virtual" is used for vendor-less "devices". For example for the GPIO based MDIO bus "virtual,mdio-gpio". This patch is needed to fix the checkpatch warning for the Protonic WD3 board. Signed-off-by: Oleksij Rempel Acked-by: Rob Herring Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index 8db0ab3b2012..6a9be2bbbcb6 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -1158,6 +1158,8 @@ patternProperties: description: Videostrong Technology Co., Ltd. "^virtio,.*": description: Virtual I/O Device Specification, developed by the OASIS consortium + "^virtual,.*": + description: Used for virtual device without specific vendor. "^vishay,.*": description: Vishay Intertechnology, Inc "^vitesse,.*": From 747ec53ea72a548693d0664817776d3634e9b63a Mon Sep 17 00:00:00 2001 From: Oleksij Rempel Date: Tue, 17 Nov 2020 14:13:53 +0100 Subject: [PATCH 708/799] dt-bindings: arm: fsl: add Protonic WD3 board Add Protonic Holland WD3 iMX6qp based board Signed-off-by: Oleksij Rempel Acked-by: Rob Herring Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/arm/fsl.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index ca1d927b7493..4772f64c4463 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -331,6 +331,7 @@ properties: - fsl,imx6qp-sabreauto # i.MX6 Quad Plus SABRE Automotive Board - fsl,imx6qp-sabresd # i.MX6 Quad Plus SABRE Smart Device Board - karo,imx6qp-tx6qp # Ka-Ro electronics TX6QP-8037 Module + - prt,prtwd3 # Protonic WD3 board - wand,imx6qp-wandboard # Wandboard i.MX6 QuadPlus Board - zii,imx6qp-zii-rdu2 # ZII RDU2+ Board - const: fsl,imx6qp From 35771b33dd987783171058e7db901f98ddd4c097 Mon Sep 17 00:00:00 2001 From: Oleksij Rempel Date: Tue, 17 Nov 2020 14:13:54 +0100 Subject: [PATCH 709/799] ARM: dts: add Protonic WD3 board Protonic WD3 is a proof of concept platform for tractor e-cockpit applications Signed-off-by: Oleksij Rempel Signed-off-by: Shawn Guo --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/imx6qp-prtwd3.dts | 553 ++++++++++++++++++++++++++++ 2 files changed, 554 insertions(+) create mode 100644 arch/arm/boot/dts/imx6qp-prtwd3.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 0a7544e01f02..3ab9d58428cf 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -583,6 +583,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \ imx6qp-nitrogen6_max.dtb \ imx6qp-nitrogen6_som2.dtb \ imx6qp-phytec-mira-rdk-nand.dtb \ + imx6qp-prtwd3.dtb \ imx6qp-sabreauto.dtb \ imx6qp-sabresd.dtb \ imx6qp-tx6qp-8037.dtb \ diff --git a/arch/arm/boot/dts/imx6qp-prtwd3.dts b/arch/arm/boot/dts/imx6qp-prtwd3.dts new file mode 100644 index 000000000000..c42723989bc0 --- /dev/null +++ b/arch/arm/boot/dts/imx6qp-prtwd3.dts @@ -0,0 +1,553 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) 2018 Protonic Holland + * Copyright (c) 2020 Oleksij Rempel , Pengutronix + */ + +/dts-v1/; +#include +#include "imx6qp.dtsi" + +/ { + model = "Protonic WD3 board"; + compatible = "prt,prtwd3", "fsl,imx6qp"; + + chosen { + stdout-path = &uart4; + }; + + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0x20000000>; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x20000000>; + }; + + clock_ksz8081: clock-ksz8081 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <50000000>; + }; + + clock_ksz9031: clock-ksz9031 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; + + clock_mcp251xfd: clock-mcp251xfd { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <20000000>; + }; + + clock_sja1105: clock-sja1105 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; + + mdio { + compatible = "virtual,mdio-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mdio>; + + #address-cells = <1>; + #size-cells = <0>; + gpios = <&gpio5 6 GPIO_ACTIVE_HIGH + &gpio5 7 GPIO_ACTIVE_HIGH>; + + /* Microchip KSZ8081 */ + usbeth_phy: ethernet-phy@3 { + reg = <0x3>; + + interrupts-extended = <&gpio5 12 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&gpio5 11 GPIO_ACTIVE_LOW>; + reset-assert-us = <500>; + reset-deassert-us = <1000>; + clocks = <&clock_ksz8081>; + clock-names = "rmii-ref"; + micrel,led-mode = <0>; + }; + + tja1102_phy0: ethernet-phy@4 { + reg = <0x4>; + + interrupts-extended = <&gpio5 8 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; + reset-assert-us = <20>; + reset-deassert-us = <2000>; + #address-cells = <1>; + #size-cells = <0>; + + tja1102_phy1: ethernet-phy@5 { + reg = <0x5>; + + interrupts-extended = <&gpio5 8 IRQ_TYPE_LEVEL_LOW>; + }; + }; + }; + + reg_5v0: regulator-5v0 { + compatible = "regulator-fixed"; + regulator-name = "5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + reg_otg_vbus: regulator-otg-vbus { + compatible = "regulator-fixed"; + regulator-name = "otg-vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + usdhc2_wifi_pwrseq: usdhc2-wifi-pwrseq { + compatible = "mmc-pwrseq-simple"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wifi_npd>; + reset-gpios = <&gpio6 10 GPIO_ACTIVE_LOW>; + }; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can1>; + xceiver-supply = <®_5v0>; + status = "okay"; +}; + +&ecspi2 { + cs-gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi2>; + status = "okay"; + + switch@0 { + compatible = "nxp,sja1105q"; + reg = <0>; + spi-max-frequency = <4000000>; + spi-rx-delay-us = <1>; + spi-tx-delay-us = <1>; + spi-cpha; + + reset-gpios = <&gpio5 5 GPIO_ACTIVE_LOW>; + + clocks = <&clock_sja1105>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "usb"; + phy-handle = <&usbeth_phy>; + phy-mode = "rmii"; + }; + + port@1 { + reg = <1>; + label = "t1slave"; + phy-handle = <&tja1102_phy1>; + phy-mode = "rmii"; + }; + + port@2 { + reg = <2>; + label = "t1master"; + phy-handle = <&tja1102_phy0>; + phy-mode = "rmii"; + + }; + + port@3 { + reg = <3>; + label = "rj45"; + phy-handle = <&rgmii_phy>; + phy-mode = "rgmii-id"; + }; + + port@4 { + reg = <4>; + label = "cpu"; + ethernet = <&fec>; + phy-mode = "rgmii-id"; + + fixed-link { + speed = <100>; + full-duplex; + }; + }; + }; + }; +}; + +&ecspi3 { + cs-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi3>; + status = "okay"; + + can@0 { + compatible = "microchip,mcp251xfd"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can2>; + reg = <0>; + clocks = <&clock_mcp251xfd>; + spi-max-frequency = <10000000>; + interrupts-extended = <&gpio4 25 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + status = "okay"; + + phy-mode = "rgmii"; + + fixed-link { + speed = <100>; + full-duplex; + }; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + /* Microchip KSZ9031 */ + rgmii_phy: ethernet-phy@2 { + reg = <2>; + + interrupts-extended = <&gpio1 28 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <1000>; + + clocks = <&clock_ksz9031>; + }; + }; +}; + +&gpio1 { + gpio-line-names = + "", "SD1_CD", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "PHY3_RESET", "", "", "PHY3_INT", "", "", ""; +}; + +&gpio2 { + gpio-line-names = + "", "", "", "", "", "", "", "", + "REV_ID0", "REV_ID1", "REV_ID2", "REV_ID3", "BOARD_ID3", + "BOARD_ID0", "BOARD_ID1", "BOARD_ID2", + "", "", "", "", "", "", "", "", + "", "", "ECSPI2_SS0", "", "", "", "", ""; +}; + +&gpio3 { + gpio-line-names = + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "USB_OTG_OC", "USB_OTG_PWR", "", + "", "", "", "", "", "", "", ""; +}; + +&gpio4 { + gpio-line-names = + "", "", "", "", "", "", "", "", + "", "", "", "", "CAN1_SR", "CAN2_SR", "", "", + "", "", "", "", "", "", "", "", + "ECSPI3_SS0", "CANFD_INT", "USB_ETH_RESET", "", "", "", "", ""; +}; + +&gpio5 { + gpio-line-names = + "", "", "", "", "", "SW_RESET", "", "", + "PHY12_INT", "PHY12_RESET", "PHY12_EN", "PHY0_RESET", + "PHY0_INT", "", "", "", + "", "", "DISP1_EN", "DISP1_LR", "DISP1_TS_IRQ", "LVDS1_PD", + "", "", + "", "LVDS1_INT", "", "", "DISP0_LR", "DISP0_TS_IRQ", + "DISP0_EN", "CAM_GPIO0"; +}; + +&gpio6 { + gpio-line-names = + "LVDS0_INT", "LVDS0_PD", "CAM_INT", "CAM_GPIO1", "CAM_PD", + "CAM_LOCK", "", "POWER_TG", + "POWER_VSEL", "", "WLAN_REG_ON", "USB_ETH_CHG", "", "", + "USB_ETH_CHG_ID0", "USB_ETH_CHG_ID1", + "USB_ETH_CHG_ID2", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + /* additional i2c devices are added automatically by the boot loader */ +}; + +&i2c3 { + adc@49 { + compatible = "ti,ads1015"; + reg = <0x49>; + #address-cells = <1>; + #size-cells = <0>; + + /* VIN */ + channel@4 { + reg = <4>; + ti,gain = <1>; + ti,datarate = <3>; + }; + + /* VBUS */ + channel@5 { + reg = <5>; + ti,gain = <1>; + ti,datarate = <3>; + }; + + /* ICHG */ + channel@6 { + reg = <6>; + ti,gain = <1>; + ti,datarate = <3>; + }; + + channel@7 { + reg = <7>; + ti,gain = <1>; + ti,datarate = <3>; + }; + }; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_otg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + phy_type = "utmi"; + dr_mode = "host"; + disable-over-current; + status = "okay"; +}; + +&usbphynop1 { + status = "disabled"; +}; + +&usbphynop2 { + status = "disabled"; +}; + +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; + no-1-8-v; + disable-wp; + cap-sd-highspeed; + no-mmc; + no-sdio; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + no-1-8-v; + non-removable; + mmc-pwrseq = <&usdhc2_wifi_pwrseq>; + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + brcmf: bcrmf@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + }; +}; + +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3>; + bus-width = <8>; + no-1-8-v; + non-removable; + no-sd; + no-sdio; + status = "okay"; +}; + +&iomuxc { + pinctrl_can1: can1grp { + fsl,pins = < + MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b000 + MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x3008 + /* CAN1_SR */ + MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x13008 + >; + }; + + pinctrl_can2: can2grp { + fsl,pins = < + /* CAN2_nINT */ + MX6QDL_PAD_DISP0_DAT4__GPIO4_IO25 0x1b0b1 + /* CAN2_SR */ + MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x13070 + >; + }; + + pinctrl_ecspi2: ecspi2grp { + fsl,pins = < + MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1 + MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1 + MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1 + MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x000b1 + >; + }; + + pinctrl_ecspi3: ecspi3grp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1 + MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1 + MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1 + /* CS */ + MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x000b1 + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x10030 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x10030 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x10030 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x10030 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x10030 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x10030 + + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x10030 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x10030 + + /* Configure clock provider for RGMII ref clock */ + MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0b0 + /* Configure clock consumer for RGMII ref clock */ + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x10030 + + /* SJA1105Q switch reset */ + MX6QDL_PAD_DISP0_DAT11__GPIO5_IO05 0x10030 + + /* phy3/rgmii_phy reset */ + MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x10030 + /* phy3/rgmii_phy int */ + MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x40010000 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001f8b1 + MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001f8b1 + >; + }; + + pinctrl_mdio: mdiogrp { + fsl,pins = < + /* phy0/usbeth_phy reset */ + MX6QDL_PAD_DISP0_DAT17__GPIO5_IO11 0x10030 + /* phy0/usbeth_phy int */ + MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x100b1 + + /* phy12/tja1102_phy0 reset */ + MX6QDL_PAD_DISP0_DAT15__GPIO5_IO09 0x10030 + /* phy12/tja1102_phy0 int */ + MX6QDL_PAD_DISP0_DAT14__GPIO5_IO08 0x100b1 + /* phy12/tja1102_phy0 enable. Set 100K pull-up */ + MX6QDL_PAD_DISP0_DAT16__GPIO5_IO10 0x1f030 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x1b0b0 + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__SD1_CMD 0x170f9 + MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100f9 + MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x170f9 + MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x170f9 + MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x170f9 + MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170f9 + MX6QDL_PAD_GPIO_1__GPIO1_IO01 0x1b0b0 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170b9 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100b9 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170b9 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170b9 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170b9 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170b9 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17099 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10099 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17099 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17099 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17099 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17099 + MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17099 + MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17099 + MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17099 + MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17099 + MX6QDL_PAD_SD3_RST__SD3_RESET 0x1b0b1 + >; + }; + + pinctrl_wifi_npd: wifinpd { + fsl,pins = < + /* WL_REG_ON */ + MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x13069 + >; + }; +}; From 2e6cde96873253fd9eb0f20afd8ffd18278cff75 Mon Sep 17 00:00:00 2001 From: Vladimir Oltean Date: Thu, 19 Nov 2020 18:38:21 +0200 Subject: [PATCH 710/799] arm64: dts: ls1028a: make the eMMC and SD card controllers use fixed indices As the boot order in the kernel continues to change, sometimes it may happen that the eSDHC controller mmc@2150000 (the one for eMMC) gets probed before the one at mmc@2140000 (for external SD cards). The effect is that the eMMC controller gets the /dev/mmcblk0 name, and the SD card gets /dev/mmcblk1. Since the introduction of this SoC, that has never happened in practice, even though it was never guaranteed in theory. Setting "root=/dev/mmcblk0p2" in /proc/cmdline has always caused the kernel to use the second partition from the SD card as the rootfs. The NXP development boards are typically shipped with either - LSDK, which uses "root=UUID=", or - OpenIL, which uses "root=/dev/mmcblkNp2" So for OpenIL, let's preserve that old behavior by adding some aliases which create naming consistency (for LSDK it doesn't matter): - the SD card controller uses /dev/mmcblk0 - the eMMC controller uses /dev/mmcblk1 For the Kontron SL28 boards, Michael Walle says that they are shipped with "root=UUID=" already, so the probing order doesn't matter, but it is more natural to him for /dev/mmcblk0 to be the eMMC, so let's do it the other way around there. The aliases are parsed by mmc_alloc_host() in drivers/mmc/core/host.c. Cc: Ashish Kumar Cc: Yangbo Lu Cc: Michael Walle Signed-off-by: Vladimir Oltean Acked-by: Michael Walle Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28.dts | 2 ++ arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts | 2 ++ arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts | 2 ++ 3 files changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28.dts index 6b1ec50d6a65..3123e4173c62 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28.dts @@ -23,6 +23,8 @@ serial2 = &lpuart1; spi0 = &fspi; spi1 = &dspi2; + mmc0 = &esdhc1; + mmc1 = &esdhc; }; buttons0 { diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts index 13cdc958ba3e..c0786b713791 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts @@ -23,6 +23,8 @@ gpio2 = &gpio3; serial0 = &duart0; serial1 = &duart1; + mmc0 = &esdhc; + mmc1 = &esdhc1; }; chosen { diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts index 1efb61cff454..c1d1ba459307 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts @@ -19,6 +19,8 @@ crypto = &crypto; serial0 = &duart0; serial1 = &duart1; + mmc0 = &esdhc; + mmc1 = &esdhc1; }; chosen { From 970406eaef3a5304cc1513d8a4aae23e183f7ba8 Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Sat, 7 Nov 2020 05:58:05 -0600 Subject: [PATCH 711/799] arm64: dts: imx8mn: Enable Asynchronous Sample Rate Converter The driver exists for the Enhanced Asynchronous Sample Rate Converter (EASRC) Controller, but there isn't a device tree entry for it. On the vendor kernel, they put this on a spba-bus for SDMA support. Add the node for the spba-bus with the easrc node inside. Signed-off-by: Adam Ford Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mn.dtsi | 28 +++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi index d5cb8abb13e8..412e4a7773ef 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi @@ -253,6 +253,34 @@ #size-cells = <1>; ranges; + spba: bus@30000000 { + compatible = "fsl,spba-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x30000000 0x100000>; + ranges; + + easrc: easrc@300c0000 { + compatible = "fsl,imx8mn-easrc"; + reg = <0x300c0000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MN_CLK_ASRC_ROOT>; + clock-names = "mem"; + dmas = <&sdma2 16 23 0> , <&sdma2 17 23 0>, + <&sdma2 18 23 0> , <&sdma2 19 23 0>, + <&sdma2 20 23 0> , <&sdma2 21 23 0>, + <&sdma2 22 23 0> , <&sdma2 23 23 0>; + dma-names = "ctx0_rx", "ctx0_tx", + "ctx1_rx", "ctx1_tx", + "ctx2_rx", "ctx2_tx", + "ctx3_rx", "ctx3_tx"; + firmware-name = "imx/easrc/easrc-imx8mn.bin"; + fsl,asrc-rate = <8000>; + fsl,asrc-format = <2>; + status = "disabled"; + }; + }; + gpio1: gpio@30200000 { compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio"; reg = <0x30200000 0x10000>; From 9e9860069725f81a97571f565a1e93a4734b6dd7 Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Sat, 7 Nov 2020 05:58:06 -0600 Subject: [PATCH 712/799] arm64: dts: imx8mn: Add SAI nodes The i.MX8M Nano has several SAI nodes available to it. Enable them. Signed-off-by: Adam Ford Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mn.dtsi | 72 +++++++++++++++++++++++ 1 file changed, 72 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi index 412e4a7773ef..bc80b0201408 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi @@ -260,6 +260,78 @@ reg = <0x30000000 0x100000>; ranges; + sai2: sai@30020000 { + compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; + reg = <0x30020000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MN_CLK_SAI2_IPG>, + <&clk IMX8MN_CLK_DUMMY>, + <&clk IMX8MN_CLK_SAI2_ROOT>, + <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dmas = <&sdma2 2 2 0>, <&sdma2 3 2 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + sai3: sai@30030000 { + compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; + reg = <0x30030000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MN_CLK_SAI3_IPG>, + <&clk IMX8MN_CLK_DUMMY>, + <&clk IMX8MN_CLK_SAI3_ROOT>, + <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dmas = <&sdma2 4 2 0>, <&sdma2 5 2 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + sai5: sai@30050000 { + compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; + reg = <0x30050000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MN_CLK_SAI5_IPG>, + <&clk IMX8MN_CLK_DUMMY>, + <&clk IMX8MN_CLK_SAI5_ROOT>, + <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dmas = <&sdma2 8 2 0>, <&sdma2 9 2 0>; + dma-names = "rx", "tx"; + fsl,shared-interrupt; + fsl,dataline = <0 0xf 0xf>; + status = "disabled"; + }; + + sai6: sai@30060000 { + compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; + reg = <0x30060000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MN_CLK_SAI6_IPG>, + <&clk IMX8MN_CLK_DUMMY>, + <&clk IMX8MN_CLK_SAI6_ROOT>, + <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dmas = <&sdma2 10 2 0>, <&sdma2 11 2 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + sai7: sai@300b0000 { + compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; + reg = <0x300b0000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MN_CLK_SAI7_IPG>, + <&clk IMX8MN_CLK_DUMMY>, + <&clk IMX8MN_CLK_SAI7_ROOT>, + <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dmas = <&sdma2 12 2 0>, <&sdma2 13 2 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + easrc: easrc@300c0000 { compatible = "fsl,imx8mn-easrc"; reg = <0x300c0000 0x10000>; From cca69ef6eba514e04717dec49a1dac2a7db221ec Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Sat, 7 Nov 2020 05:58:07 -0600 Subject: [PATCH 713/799] arm64: dts: imx8mn: Add support for micfil The i.MX8M Nano has supports the MICFIL digital interface. It's a 16-bit audio signal from a PDM microphone bitstream. The driver is already in the kernel, but the node is missing. Add the micfil node. Signed-off-by: Adam Ford Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mn.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi index bc80b0201408..2087fe84c7cf 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi @@ -318,6 +318,25 @@ status = "disabled"; }; + micfil: audio-controller@30080000 { + compatible = "fsl,imx8mm-micfil"; + reg = <0x30080000 0x10000>; + interrupts = , + , + , + ; + clocks = <&clk IMX8MN_CLK_PDM_IPG>, + <&clk IMX8MN_CLK_PDM_ROOT>, + <&clk IMX8MN_AUDIO_PLL1_OUT>, + <&clk IMX8MN_AUDIO_PLL2_OUT>, + <&clk IMX8MN_CLK_EXT3>; + clock-names = "ipg_clk", "ipg_clk_app", + "pll8k", "pll11k", "clkext3"; + dmas = <&sdma2 24 25 0x80000000>; + dma-names = "rx"; + status = "disabled"; + }; + sai7: sai@300b0000 { compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; reg = <0x300b0000 0x10000>; From b9cf7d3b6592561e2a9f123a989f7dd5708a61d3 Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Sat, 7 Nov 2020 05:58:08 -0600 Subject: [PATCH 714/799] arm64: dts: imx8mn: Add node for SPDIF The i.MX8M Nano can support SPDIF which is compatible to the IP used on the i.MX35. Add the node. Signed-off-by: Adam Ford Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mn.dtsi | 24 +++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi index 2087fe84c7cf..31ca1f3bfece 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi @@ -337,6 +337,30 @@ status = "disabled"; }; + spdif1: spdif@30090000 { + compatible = "fsl,imx35-spdif"; + reg = <0x30090000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MN_CLK_AUDIO_AHB>, /* core */ + <&clk IMX8MN_CLK_24M>, /* rxtx0 */ + <&clk IMX8MN_CLK_SPDIF1>, /* rxtx1 */ + <&clk IMX8MN_CLK_DUMMY>, /* rxtx2 */ + <&clk IMX8MN_CLK_DUMMY>, /* rxtx3 */ + <&clk IMX8MN_CLK_DUMMY>, /* rxtx4 */ + <&clk IMX8MN_CLK_AUDIO_AHB>, /* rxtx5 */ + <&clk IMX8MN_CLK_DUMMY>, /* rxtx6 */ + <&clk IMX8MN_CLK_DUMMY>, /* rxtx7 */ + <&clk IMX8MN_CLK_DUMMY>; /* spba */ + clock-names = "core", "rxtx0", + "rxtx1", "rxtx2", + "rxtx3", "rxtx4", + "rxtx5", "rxtx6", + "rxtx7", "spba"; + dmas = <&sdma2 28 18 0>, <&sdma2 29 18 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + sai7: sai@300b0000 { compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; reg = <0x300b0000 0x10000>; From 327106e4217b8ef4f74640d7de15a0a287690aba Mon Sep 17 00:00:00 2001 From: Lukasz Majewski Date: Wed, 25 Nov 2020 17:18:13 +0100 Subject: [PATCH 715/799] ARM: dts: imx28: Fix label name for L2 switch The 'eth_switch' name has been misspelled in the imx28.dtsi file, so this change fixes it. Signed-off-by: Lukasz Majewski Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx28.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi index 94dfbf5b3f34..bbe52150b165 100644 --- a/arch/arm/boot/dts/imx28.dtsi +++ b/arch/arm/boot/dts/imx28.dtsi @@ -1317,7 +1317,7 @@ status = "disabled"; }; - etn_switch: switch@800f8000 { + eth_switch: switch@800f8000 { reg = <0x800f8000 0x8000>; status = "disabled"; }; From 6b5cd77371e5e34769284bfb058ff332ae278cc5 Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Thu, 26 Nov 2020 04:45:34 -0600 Subject: [PATCH 716/799] arm64: dts: imx8mm-beacon-som: Configure RTC aliases On the i.MX8MM Beacon SOM, there is an RTC chip which is fed power from the baseboard during power off. The SNVS RTC integrated into the SoC is not fed power. Depending on the order the modules are loaded, this can be a problem if the external RTC isn't rtc0. Make the alias for rtc0 point to the external RTC all the time and rtc1 point to the SVNS in order to correctly hold date/time over a power-cycle. Signed-off-by: Adam Ford Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi index 6b53830ddf74..8380fd4047d4 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi @@ -4,6 +4,11 @@ */ / { + aliases { + rtc0 = &rtc; + rtc1 = &snvs_rtc; + }; + usdhc1_pwrseq: usdhc1_pwrseq { compatible = "mmc-pwrseq-simple"; pinctrl-names = "default"; @@ -218,7 +223,7 @@ reg = <0x50>; }; - rtc@51 { + rtc: rtc@51 { compatible = "nxp,pcf85263"; reg = <0x51>; }; From 0b84862688951ad5f6ad8990dd9a44e1363c4a2b Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Thu, 26 Nov 2020 04:45:35 -0600 Subject: [PATCH 717/799] arm64: dts: imx8mm-beacon-som: Assign PMIC clock The PMIC throws an errors because the clock isn't assigned to it. Fix this by assigning the clocks info. Signed-off-by: Adam Ford Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi index 8380fd4047d4..c14add99bfa4 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi @@ -110,6 +110,10 @@ interrupts = <3 IRQ_TYPE_LEVEL_LOW>; rohm,reset-snvs-powered; + #clock-cells = <0>; + clocks = <&osc_32k 0>; + clock-output-names = "clk-32k-out"; + regulators { buck1_reg: BUCK1 { regulator-name = "buck1"; From 8caaf0610fb9948b1f3ad220f83fccfc24e33333 Mon Sep 17 00:00:00 2001 From: Alexandre Belloni Date: Fri, 30 Oct 2020 19:36:58 +0100 Subject: [PATCH 718/799] ARM: dts: at91: kizbox: switch to new pwm-atmel-tcb binding Switch to the new pwm-atmel-tcb binding that avoid wasting TCB channels. Signed-off-by: Alexandre Belloni Cc: Antoine Aubert Link: https://lore.kernel.org/r/20201030183658.1007395-5-alexandre.belloni@bootlin.com --- arch/arm/boot/dts/at91-kizbox.dts | 45 ++++++++++++++++++++----------- 1 file changed, 30 insertions(+), 15 deletions(-) diff --git a/arch/arm/boot/dts/at91-kizbox.dts b/arch/arm/boot/dts/at91-kizbox.dts index 8b33fe5564fe..3b8812fcd854 100644 --- a/arch/arm/boot/dts/at91-kizbox.dts +++ b/arch/arm/boot/dts/at91-kizbox.dts @@ -53,43 +53,32 @@ led-1 { label = "pwm:green:network"; - pwms = <&tcb_pwm 2 10000000 PWM_POLARITY_INVERTED>; + pwms = <&tcb1_pwm1 0 10000000 PWM_POLARITY_INVERTED>; max-brightness = <255>; linux,default-trigger = "default-on"; }; led-2 { label = "pwm:red:network"; - pwms = <&tcb_pwm 4 10000000 PWM_POLARITY_INVERTED>; + pwms = <&tcb1_pwm2 0 10000000 PWM_POLARITY_INVERTED>; max-brightness = <255>; linux,default-trigger = "default-on"; }; led-3 { label = "pwm:green:user"; - pwms = <&tcb_pwm 0 10000000 PWM_POLARITY_INVERTED>; + pwms = <&tcb1_pwm0 0 10000000 PWM_POLARITY_INVERTED>; max-brightness = <255>; linux,default-trigger = "default-on"; }; led-4 { label = "pwm:red:user"; - pwms = <&tcb_pwm 1 10000000 PWM_POLARITY_INVERTED>; + pwms = <&tcb1_pwm0 1 10000000 PWM_POLARITY_INVERTED>; max-brightness = <255>; linux,default-trigger = "default-on"; }; }; - - tcb_pwm: pwm { - compatible = "atmel,tcb-pwm"; - #pwm-cells = <3>; - tc-block = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_tcb1_tioa0 - &pinctrl_tcb1_tioa1 - &pinctrl_tcb1_tioa2 - &pinctrl_tcb1_tiob0>; - }; }; &tcb0 { @@ -104,6 +93,32 @@ }; }; +&tcb1 { + tcb1_pwm0: pwm@0 { + compatible = "atmel,tcb-pwm"; + reg = <0>; + #pwm-cells = <3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tcb1_tioa0 &pinctrl_tcb1_tiob0>; + }; + + tcb1_pwm1: pwm@1 { + compatible = "atmel,tcb-pwm"; + reg = <1>; + #pwm-cells = <3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tcb1_tioa1>; + }; + + tcb1_pwm2: pwm@2 { + compatible = "atmel,tcb-pwm"; + reg = <2>; + #pwm-cells = <3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tcb1_tioa2>; + }; +}; + &ebi { status = "okay"; }; From 53de2d127430d0b5300de5d6ada0f17df0379511 Mon Sep 17 00:00:00 2001 From: Alexandre Belloni Date: Sat, 28 Nov 2020 23:28:16 +0100 Subject: [PATCH 719/799] ARM: dts: at91: sama5d3: use proper ADC compatible The ADC is different from the at91sam9x5 ADC. Not only it doesn't have the same resolution but it even has only one and the LOWRES bit doesn't exist. Signed-off-by: Alexandre Belloni Reviewed-by: Ludovic Desroches Link: https://lore.kernel.org/r/20201128222818.1910764-9-alexandre.belloni@bootlin.com --- arch/arm/boot/dts/sama5d3.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/sama5d3.dtsi b/arch/arm/boot/dts/sama5d3.dtsi index 86137f8d2b45..bba2a3f41c42 100644 --- a/arch/arm/boot/dts/sama5d3.dtsi +++ b/arch/arm/boot/dts/sama5d3.dtsi @@ -307,7 +307,7 @@ adc0: adc@f8018000 { #address-cells = <1>; #size-cells = <0>; - compatible = "atmel,at91sam9x5-adc"; + compatible = "atmel,sama5d3-adc"; reg = <0xf8018000 0x100>; interrupts = <29 IRQ_TYPE_LEVEL_HIGH 5>; pinctrl-names = "default"; From 851a95da583c26e2ddeb7281e9b61f0d76ea5aba Mon Sep 17 00:00:00 2001 From: Alexandre Belloni Date: Sat, 28 Nov 2020 23:28:17 +0100 Subject: [PATCH 720/799] ARM: dts: at91: at91sam9rl: fix ADC triggers The triggers for the ADC were taken from at91sam9260 dtsi but are not correct. Fixes: a4c1d6c75822 ("ARM: at91/dt: sam9rl: add lcd, adc, usb gadget and pwm support") Signed-off-by: Alexandre Belloni Link: https://lore.kernel.org/r/20201128222818.1910764-10-alexandre.belloni@bootlin.com --- arch/arm/boot/dts/at91sam9rl.dtsi | 19 +++++++++++-------- 1 file changed, 11 insertions(+), 8 deletions(-) diff --git a/arch/arm/boot/dts/at91sam9rl.dtsi b/arch/arm/boot/dts/at91sam9rl.dtsi index 5653e70c84b4..36a42a9fe195 100644 --- a/arch/arm/boot/dts/at91sam9rl.dtsi +++ b/arch/arm/boot/dts/at91sam9rl.dtsi @@ -282,23 +282,26 @@ atmel,adc-use-res = "highres"; trigger0 { - trigger-name = "timer-counter-0"; + trigger-name = "external-rising"; trigger-value = <0x1>; + trigger-external; }; + trigger1 { - trigger-name = "timer-counter-1"; - trigger-value = <0x3>; + trigger-name = "external-falling"; + trigger-value = <0x2>; + trigger-external; }; trigger2 { - trigger-name = "timer-counter-2"; - trigger-value = <0x5>; + trigger-name = "external-any"; + trigger-value = <0x3>; + trigger-external; }; trigger3 { - trigger-name = "external"; - trigger-value = <0x13>; - trigger-external; + trigger-name = "continuous"; + trigger-value = <0x6>; }; }; From 32b7cfbd4bb2d63fffc34a781e1f3cd911190aef Mon Sep 17 00:00:00 2001 From: Alexandre Belloni Date: Sat, 28 Nov 2020 23:28:18 +0100 Subject: [PATCH 721/799] ARM: dts: at91: remove deprecated ADC properties atmel,adc-res, atmel,adc-res-names and the trigger nodes are not parsed by the driver anymore and the information is now defined in the driver data. Also remove the leftover #address-cells and #size-cells that were used when the trigger nodes had a unit-address. Finally, the default is already to use the highest resoution. Remove atmel,adc-use-res from the SoC dtsi. Signed-off-by: Alexandre Belloni Reviewed-by: Ludovic Desroches Link: https://lore.kernel.org/r/20201128222818.1910764-11-alexandre.belloni@bootlin.com --- arch/arm/boot/dts/at91sam9260.dtsi | 25 ------------------------- arch/arm/boot/dts/at91sam9g45.dtsi | 27 --------------------------- arch/arm/boot/dts/at91sam9rl.dtsi | 28 ---------------------------- arch/arm/boot/dts/at91sam9x5.dtsi | 28 ---------------------------- arch/arm/boot/dts/sama5d3.dtsi | 24 ------------------------ arch/arm/boot/dts/sama5d4.dtsi | 22 ---------------------- 6 files changed, 154 deletions(-) diff --git a/arch/arm/boot/dts/at91sam9260.dtsi b/arch/arm/boot/dts/at91sam9260.dtsi index 82c5d7fd9811..019f1c3d4d30 100644 --- a/arch/arm/boot/dts/at91sam9260.dtsi +++ b/arch/arm/boot/dts/at91sam9260.dtsi @@ -697,8 +697,6 @@ }; adc0: adc@fffe0000 { - #address-cells = <1>; - #size-cells = <0>; compatible = "atmel,at91sam9260-adc"; reg = <0xfffe0000 0x100>; interrupts = <5 IRQ_TYPE_LEVEL_HIGH 0>; @@ -708,29 +706,6 @@ atmel,adc-channels-used = <0xf>; atmel,adc-vref = <3300>; atmel,adc-startup-time = <15>; - atmel,adc-res = <8 10>; - atmel,adc-res-names = "lowres", "highres"; - atmel,adc-use-res = "highres"; - - trigger0 { - trigger-name = "timer-counter-0"; - trigger-value = <0x1>; - }; - trigger1 { - trigger-name = "timer-counter-1"; - trigger-value = <0x3>; - }; - - trigger2 { - trigger-name = "timer-counter-2"; - trigger-value = <0x5>; - }; - - trigger3 { - trigger-name = "external"; - trigger-value = <0xd>; - trigger-external; - }; }; rtc@fffffd20 { diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi index 19fc748a87c5..2ab730fd6472 100644 --- a/arch/arm/boot/dts/at91sam9g45.dtsi +++ b/arch/arm/boot/dts/at91sam9g45.dtsi @@ -812,8 +812,6 @@ }; adc0: adc@fffb0000 { - #address-cells = <1>; - #size-cells = <0>; compatible = "atmel,at91sam9g45-adc"; reg = <0xfffb0000 0x100>; interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>; @@ -822,31 +820,6 @@ atmel,adc-channels-used = <0xff>; atmel,adc-vref = <3300>; atmel,adc-startup-time = <40>; - atmel,adc-res = <8 10>; - atmel,adc-res-names = "lowres", "highres"; - atmel,adc-use-res = "highres"; - - trigger0 { - trigger-name = "external-rising"; - trigger-value = <0x1>; - trigger-external; - }; - trigger1 { - trigger-name = "external-falling"; - trigger-value = <0x2>; - trigger-external; - }; - - trigger2 { - trigger-name = "external-any"; - trigger-value = <0x3>; - trigger-external; - }; - - trigger3 { - trigger-name = "continuous"; - trigger-value = <0x6>; - }; }; isi@fffb4000 { diff --git a/arch/arm/boot/dts/at91sam9rl.dtsi b/arch/arm/boot/dts/at91sam9rl.dtsi index 36a42a9fe195..730d1182c73e 100644 --- a/arch/arm/boot/dts/at91sam9rl.dtsi +++ b/arch/arm/boot/dts/at91sam9rl.dtsi @@ -266,8 +266,6 @@ }; adc0: adc@fffd0000 { - #address-cells = <1>; - #size-cells = <0>; compatible = "atmel,at91sam9rl-adc"; reg = <0xfffd0000 0x100>; interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>; @@ -277,32 +275,6 @@ atmel,adc-channels-used = <0x3f>; atmel,adc-vref = <3300>; atmel,adc-startup-time = <40>; - atmel,adc-res = <8 10>; - atmel,adc-res-names = "lowres", "highres"; - atmel,adc-use-res = "highres"; - - trigger0 { - trigger-name = "external-rising"; - trigger-value = <0x1>; - trigger-external; - }; - - trigger1 { - trigger-name = "external-falling"; - trigger-value = <0x2>; - trigger-external; - }; - - trigger2 { - trigger-name = "external-any"; - trigger-value = <0x3>; - trigger-external; - }; - - trigger3 { - trigger-name = "continuous"; - trigger-value = <0x6>; - }; }; usb0: gadget@fffd4000 { diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi index 4cdb05079cc7..395e883644cd 100644 --- a/arch/arm/boot/dts/at91sam9x5.dtsi +++ b/arch/arm/boot/dts/at91sam9x5.dtsi @@ -795,8 +795,6 @@ }; adc0: adc@f804c000 { - #address-cells = <1>; - #size-cells = <0>; compatible = "atmel,at91sam9x5-adc"; reg = <0xf804c000 0x100>; interrupts = <19 IRQ_TYPE_LEVEL_HIGH 0>; @@ -808,32 +806,6 @@ atmel,adc-vref = <3300>; atmel,adc-startup-time = <40>; atmel,adc-sample-hold-time = <11>; - atmel,adc-res = <8 10>; - atmel,adc-res-names = "lowres", "highres"; - atmel,adc-use-res = "highres"; - - trigger0 { - trigger-name = "external-rising"; - trigger-value = <0x1>; - trigger-external; - }; - - trigger1 { - trigger-name = "external-falling"; - trigger-value = <0x2>; - trigger-external; - }; - - trigger2 { - trigger-name = "external-any"; - trigger-value = <0x3>; - trigger-external; - }; - - trigger3 { - trigger-name = "continuous"; - trigger-value = <0x6>; - }; }; spi0: spi@f0000000 { diff --git a/arch/arm/boot/dts/sama5d3.dtsi b/arch/arm/boot/dts/sama5d3.dtsi index bba2a3f41c42..7c979652f330 100644 --- a/arch/arm/boot/dts/sama5d3.dtsi +++ b/arch/arm/boot/dts/sama5d3.dtsi @@ -305,8 +305,6 @@ }; adc0: adc@f8018000 { - #address-cells = <1>; - #size-cells = <0>; compatible = "atmel,sama5d3-adc"; reg = <0xf8018000 0x100>; interrupts = <29 IRQ_TYPE_LEVEL_HIGH 5>; @@ -333,30 +331,8 @@ atmel,adc-startup-time = <40>; atmel,adc-use-external-triggers; atmel,adc-vref = <3000>; - atmel,adc-res = <10 12>; atmel,adc-sample-hold-time = <11>; - atmel,adc-res-names = "lowres", "highres"; status = "disabled"; - - trigger0 { - trigger-name = "external-rising"; - trigger-value = <0x1>; - trigger-external; - }; - trigger1 { - trigger-name = "external-falling"; - trigger-value = <0x2>; - trigger-external; - }; - trigger2 { - trigger-name = "external-any"; - trigger-value = <0x3>; - trigger-external; - }; - trigger3 { - trigger-name = "continuous"; - trigger-value = <0x6>; - }; }; i2c2: i2c@f801c000 { diff --git a/arch/arm/boot/dts/sama5d4.dtsi b/arch/arm/boot/dts/sama5d4.dtsi index 04f24cf752d3..05c55875835d 100644 --- a/arch/arm/boot/dts/sama5d4.dtsi +++ b/arch/arm/boot/dts/sama5d4.dtsi @@ -661,31 +661,9 @@ atmel,adc-startup-time = <40>; atmel,adc-use-external-triggers; atmel,adc-vref = <3000>; - atmel,adc-res = <8 10>; atmel,adc-sample-hold-time = <11>; - atmel,adc-res-names = "lowres", "highres"; atmel,adc-ts-pressure-threshold = <10000>; status = "disabled"; - - trigger0 { - trigger-name = "external-rising"; - trigger-value = <0x1>; - trigger-external; - }; - trigger1 { - trigger-name = "external-falling"; - trigger-value = <0x2>; - trigger-external; - }; - trigger2 { - trigger-name = "external-any"; - trigger-value = <0x3>; - trigger-external; - }; - trigger3 { - trigger-name = "continuous"; - trigger-value = <0x6>; - }; }; aes@fc044000 { From 8523df80815bc438b6e6aa9db959c0eed0185695 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 17 Nov 2020 21:11:03 +0100 Subject: [PATCH 722/799] dt-bindings: arm: samsung: document SMDK2416 board binding Add binding for the SMDK2416 board. Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20201117201106.128813-1-krzk@kernel.org --- .../devicetree/bindings/arm/samsung/samsung-boards.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml b/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml index dbc401984152..a6a3e38cfdf2 100644 --- a/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml +++ b/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml @@ -14,6 +14,12 @@ properties: const: '/' compatible: oneOf: + - description: S3C2416 based boards + items: + - enum: + - samsung,smdk2416 # Samsung SMDK2416 + - const: samsung,s3c2416 + - description: S5PV210 based boards items: - enum: From 1aa386106b445b95b4a1f485d3a76fa8bca21ba3 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 17 Nov 2020 21:11:04 +0100 Subject: [PATCH 723/799] dt-bindings: arm: samsung: document S3C6410-based boards binding Add bindings for the FriendlyARM Mini6410 and Samsung SMDK6410 boards. Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20201117201106.128813-2-krzk@kernel.org --- .../devicetree/bindings/arm/samsung/samsung-boards.yaml | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml b/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml index a6a3e38cfdf2..bdcfc990fbd7 100644 --- a/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml +++ b/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml @@ -20,6 +20,13 @@ properties: - samsung,smdk2416 # Samsung SMDK2416 - const: samsung,s3c2416 + - description: S3C6410 based boards + items: + - enum: + - friendlyarm,mini6410 # FriendlyARM Mini6410 + - samsung,smdk6410 # Samsung SMDK6410 + - const: samsung,s3c6410 + - description: S5PV210 based boards items: - enum: From 16b8fe4caf499ae8e12d2ab1b1324497e36a7b83 Mon Sep 17 00:00:00 2001 From: Eric Auger Date: Fri, 13 Nov 2020 18:52:02 +0100 Subject: [PATCH 724/799] vfio/pci: Move dummy_resources_list init in vfio_pci_probe() In case an error occurs in vfio_pci_enable() before the call to vfio_pci_probe_mmaps(), vfio_pci_disable() will try to iterate on an uninitialized list and cause a kernel panic. Lets move to the initialization to vfio_pci_probe() to fix the issue. Signed-off-by: Eric Auger Fixes: 05f0c03fbac1 ("vfio-pci: Allow to mmap sub-page MMIO BARs if the mmio page is exclusive") CC: Stable # v4.7+ Signed-off-by: Alex Williamson --- drivers/vfio/pci/vfio_pci.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/vfio/pci/vfio_pci.c b/drivers/vfio/pci/vfio_pci.c index e6190173482c..47ebc5c49ca4 100644 --- a/drivers/vfio/pci/vfio_pci.c +++ b/drivers/vfio/pci/vfio_pci.c @@ -161,8 +161,6 @@ static void vfio_pci_probe_mmaps(struct vfio_pci_device *vdev) int i; struct vfio_pci_dummy_resource *dummy_res; - INIT_LIST_HEAD(&vdev->dummy_resources_list); - for (i = 0; i < PCI_STD_NUM_BARS; i++) { int bar = i + PCI_STD_RESOURCES; @@ -1966,6 +1964,7 @@ static int vfio_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) mutex_init(&vdev->igate); spin_lock_init(&vdev->irqlock); mutex_init(&vdev->ioeventfds_lock); + INIT_LIST_HEAD(&vdev->dummy_resources_list); INIT_LIST_HEAD(&vdev->ioeventfds_list); mutex_init(&vdev->vma_lock); INIT_LIST_HEAD(&vdev->vma_list); From 7b06a56d468b756ad6bb43ac21b11e474ebc54a0 Mon Sep 17 00:00:00 2001 From: Jason Gunthorpe Date: Thu, 5 Nov 2020 12:34:58 -0400 Subject: [PATCH 725/799] vfio-pci: Use io_remap_pfn_range() for PCI IO memory commit f8f6ae5d077a ("mm: always have io_remap_pfn_range() set pgprot_decrypted()") allows drivers using mmap to put PCI memory mapped BAR space into userspace to work correctly on AMD SME systems that default to all memory encrypted. Since vfio_pci_mmap_fault() is working with PCI memory mapped BAR space it should be calling io_remap_pfn_range() otherwise it will not work on SME systems. Fixes: 11c4cd07ba11 ("vfio-pci: Fault mmaps to enable vma tracking") Signed-off-by: Jason Gunthorpe Acked-by: Peter Xu Tested-by: Tom Lendacky Signed-off-by: Alex Williamson --- drivers/vfio/pci/vfio_pci.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/vfio/pci/vfio_pci.c b/drivers/vfio/pci/vfio_pci.c index 47ebc5c49ca4..706de3ef94bb 100644 --- a/drivers/vfio/pci/vfio_pci.c +++ b/drivers/vfio/pci/vfio_pci.c @@ -1633,8 +1633,8 @@ static vm_fault_t vfio_pci_mmap_fault(struct vm_fault *vmf) mutex_unlock(&vdev->vma_lock); - if (remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff, - vma->vm_end - vma->vm_start, vma->vm_page_prot)) + if (io_remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff, + vma->vm_end - vma->vm_start, vma->vm_page_prot)) ret = VM_FAULT_SIGBUS; up_out: From 7dc4c0b42d82d9b633663eadcd821f3a109af4e4 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 17 Nov 2020 21:11:05 +0100 Subject: [PATCH 726/799] ARM: dts: s3c24xx: add SMDK2416 board compatible Add a compatible for SMDK2416 board next to the SoC compatible. Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20201117201106.128813-3-krzk@kernel.org --- arch/arm/boot/dts/s3c2416-smdk2416.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/s3c2416-smdk2416.dts b/arch/arm/boot/dts/s3c2416-smdk2416.dts index 47626ede6fdd..e7c379a9842e 100644 --- a/arch/arm/boot/dts/s3c2416-smdk2416.dts +++ b/arch/arm/boot/dts/s3c2416-smdk2416.dts @@ -10,7 +10,7 @@ / { model = "SMDK2416"; - compatible = "samsung,s3c2416"; + compatible = "samsung,smdk2416", "samsung,s3c2416"; memory@30000000 { device_type = "memory"; From 32ccdde0a794700f29d190eae77eb41f1b8926ce Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 17 Nov 2020 21:11:06 +0100 Subject: [PATCH 727/799] ARM: dts: s3c6410: correct SMDK6410 board compatible The SMDK6410 DTS was incorrectly called mini6410, probably copy-paste from FriendlyARM Mini6410 board. Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20201117201106.128813-4-krzk@kernel.org --- arch/arm/boot/dts/s3c6410-smdk6410.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/s3c6410-smdk6410.dts b/arch/arm/boot/dts/s3c6410-smdk6410.dts index 69c9ec4cf381..581309e7f15e 100644 --- a/arch/arm/boot/dts/s3c6410-smdk6410.dts +++ b/arch/arm/boot/dts/s3c6410-smdk6410.dts @@ -17,7 +17,7 @@ / { model = "Samsung SMDK6410 board based on S3C6410"; - compatible = "samsung,mini6410", "samsung,s3c6410"; + compatible = "samsung,smdk6410", "samsung,s3c6410"; memory@50000000 { device_type = "memory"; From d22f9a6c92de96304c81792942ae7c306f08ac77 Mon Sep 17 00:00:00 2001 From: Alexey Kardashevskiy Date: Sun, 22 Nov 2020 18:39:50 +1100 Subject: [PATCH 728/799] vfio/pci/nvlink2: Do not attempt NPU2 setup on POWER8NVL NPU We execute certain NPU2 setup code (such as mapping an LPID to a device in NPU2) unconditionally if an Nvlink bridge is detected. However this cannot succeed on POWER8NVL machines as the init helpers return an error other than ENODEV which means the device is there is and setup failed so vfio_pci_enable() fails and pass through is not possible. This changes the two NPU2 related init helpers to return -ENODEV if there is no "memory-region" device tree property as this is the distinction between NPU and NPU2. Tested on - POWER9 pvr=004e1201, Ubuntu 19.04 host, Ubuntu 18.04 vm, NVIDIA GV100 10de:1db1 driver 418.39 - POWER8 pvr=004c0100, RHEL 7.6 host, Ubuntu 16.10 vm, NVIDIA P100 10de:15f9 driver 396.47 Fixes: 7f92891778df ("vfio_pci: Add NVIDIA GV100GL [Tesla V100 SXM2] subdriver") Cc: stable@vger.kernel.org # 5.0 Signed-off-by: Alexey Kardashevskiy Signed-off-by: Alex Williamson --- drivers/vfio/pci/vfio_pci_nvlink2.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/vfio/pci/vfio_pci_nvlink2.c b/drivers/vfio/pci/vfio_pci_nvlink2.c index 65c61710c0e9..9adcf6a8f888 100644 --- a/drivers/vfio/pci/vfio_pci_nvlink2.c +++ b/drivers/vfio/pci/vfio_pci_nvlink2.c @@ -231,7 +231,7 @@ int vfio_pci_nvdia_v100_nvlink2_init(struct vfio_pci_device *vdev) return -EINVAL; if (of_property_read_u32(npu_node, "memory-region", &mem_phandle)) - return -EINVAL; + return -ENODEV; mem_node = of_find_node_by_phandle(mem_phandle); if (!mem_node) @@ -393,7 +393,7 @@ int vfio_pci_ibm_npu2_init(struct vfio_pci_device *vdev) int ret; struct vfio_pci_npu2_data *data; struct device_node *nvlink_dn; - u32 nvlink_index = 0; + u32 nvlink_index = 0, mem_phandle = 0; struct pci_dev *npdev = vdev->pdev; struct device_node *npu_node = pci_device_to_OF_node(npdev); struct pci_controller *hose = pci_bus_to_host(npdev->bus); @@ -408,6 +408,9 @@ int vfio_pci_ibm_npu2_init(struct vfio_pci_device *vdev) if (!pnv_pci_get_gpu_dev(vdev->pdev)) return -ENODEV; + if (of_property_read_u32(npu_node, "memory-region", &mem_phandle)) + return -ENODEV; + /* * NPU2 normally has 8 ATSD registers (for concurrency) and 6 links * so we can allocate one register per link, using nvlink index as From 7995fb896b9637a5f59a56ae0d8f2b7ca71a040d Mon Sep 17 00:00:00 2001 From: Marek Szyprowski Date: Wed, 2 Dec 2020 13:20:29 +0100 Subject: [PATCH 729/799] ARM: dts: exynos: Reduce assigned-clocks entries for SPI0 on Artik5 board Commit 2024b130b0c8 ("ARM: dts: exynos: Add Ethernet to Artik 5 board") added ethernet chip on SPI0 bus and the whole bunch of assigned clock entries to ensure proper clock rates and topology. Limit the assigned clock parents only to the direct clocks of the SPI0 device and assume that MPLL clock is already properly configured. The applied clock topology was incorrect as some clocks between were missing, what resulted in the following warning: clk: failed to reparent div_mpll_pre to mout_mpll: -22 Fixes: 2024b130b0c8 ("ARM: dts: exynos: Add Ethernet to Artik 5 board") Signed-off-by: Marek Szyprowski Link: https://lore.kernel.org/r/20201202122029.22198-1-m.szyprowski@samsung.com Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos3250-artik5-eval.dts | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/arch/arm/boot/dts/exynos3250-artik5-eval.dts b/arch/arm/boot/dts/exynos3250-artik5-eval.dts index 5461949d833e..a1e22f630638 100644 --- a/arch/arm/boot/dts/exynos3250-artik5-eval.dts +++ b/arch/arm/boot/dts/exynos3250-artik5-eval.dts @@ -42,12 +42,9 @@ status = "okay"; cs-gpios = <&gpx3 4 GPIO_ACTIVE_LOW>, <0>; - assigned-clocks = <&cmu CLK_MOUT_MPLL>, <&cmu CLK_DIV_MPLL_PRE>, - <&cmu CLK_MOUT_SPI0>, <&cmu CLK_DIV_SPI0>, + assigned-clocks = <&cmu CLK_MOUT_SPI0>, <&cmu CLK_DIV_SPI0>, <&cmu CLK_DIV_SPI0_PRE>, <&cmu CLK_SCLK_SPI0>; - assigned-clock-parents = <&cmu CLK_FOUT_MPLL>, /* for: CLK_MOUT_MPLL */ - <&cmu CLK_MOUT_MPLL>, /* for: CLK_DIV_MPLL_PRE */ - <&cmu CLK_DIV_MPLL_PRE>, /* for: CLK_MOUT_SPI0 */ + assigned-clock-parents = <&cmu CLK_DIV_MPLL_PRE>, /* for: CLK_MOUT_SPI0 */ <&cmu CLK_MOUT_SPI0>, /* for: CLK_DIV_SPI0 */ <&cmu CLK_DIV_SPI0>, /* for: CLK_DIV_SPI0_PRE */ <&cmu CLK_DIV_SPI0_PRE>; /* for: CLK_SCLK_SPI0 */ From ab8a9bb41b2c330a0b280280bf37b6f3b1dd1e58 Mon Sep 17 00:00:00 2001 From: Claudiu Beznea Date: Wed, 2 Dec 2020 11:57:04 +0200 Subject: [PATCH 730/799] ARM: dts: at91: sam9x60ek: remove bypass property atmel,osc-bypass property sets the bit 1 at main oscillator register. On SAM9X60 this bit is not valid according to datasheet (chapter 28.16.9 PMC Clock Generator Main Oscillator Register). Fixes: 1e5f532c2737 ("ARM: dts: at91: sam9x60: add device tree for soc and board") Signed-off-by: Claudiu Beznea Signed-off-by: Alexandre Belloni Acked-by: Nicolas Ferre Cc: Marco Cardellini Link: https://lore.kernel.org/r/1606903025-14197-2-git-send-email-claudiu.beznea@microchip.com --- arch/arm/boot/dts/at91-sam9x60ek.dts | 4 ---- 1 file changed, 4 deletions(-) diff --git a/arch/arm/boot/dts/at91-sam9x60ek.dts b/arch/arm/boot/dts/at91-sam9x60ek.dts index 0e3b6147069f..73b6b1f89de9 100644 --- a/arch/arm/boot/dts/at91-sam9x60ek.dts +++ b/arch/arm/boot/dts/at91-sam9x60ek.dts @@ -578,10 +578,6 @@ }; }; /* pinctrl */ -&pmc { - atmel,osc-bypass; -}; - &pwm0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm0_0 &pinctrl_pwm0_1 &pinctrl_pwm0_2 &pinctrl_pwm0_3>; From 9b5dcc8d427e2bcb84c49eb03ffefe11e7537a55 Mon Sep 17 00:00:00 2001 From: Claudiu Beznea Date: Wed, 2 Dec 2020 11:57:05 +0200 Subject: [PATCH 731/799] ARM: dts: at91: sama5d2: map securam as device Due to strobe signal not being propagated from CPU to securam the securam needs to be mapped as device or strongly ordered memory to work properly. Otherwise, updating to one offset may affect the adjacent locations in securam. Fixes: d4ce5f44d4409 ("ARM: dts: at91: sama5d2: Add securam node") Signed-off-by: Claudiu Beznea Signed-off-by: Alexandre Belloni Acked-by: Nicolas Ferre Link: https://lore.kernel.org/r/1606903025-14197-3-git-send-email-claudiu.beznea@microchip.com --- arch/arm/boot/dts/sama5d2.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/sama5d2.dtsi b/arch/arm/boot/dts/sama5d2.dtsi index 2ddc85dff8ce..6d399ac0385d 100644 --- a/arch/arm/boot/dts/sama5d2.dtsi +++ b/arch/arm/boot/dts/sama5d2.dtsi @@ -656,6 +656,7 @@ clocks = <&pmc PMC_TYPE_PERIPHERAL 51>; #address-cells = <1>; #size-cells = <1>; + no-memory-wc; ranges = <0 0xf8044000 0x1420>; }; From 85b8350ae99d1300eb6dc072459246c2649a8e50 Mon Sep 17 00:00:00 2001 From: Nicolas Ferre Date: Thu, 3 Dec 2020 10:19:49 +0100 Subject: [PATCH 732/799] ARM: dts: at91: sama5d2: fix CAN message ram offset and size CAN0 and CAN1 instances share the same message ram configured at 0x210000 on sama5d2 Linux systems. According to current configuration of CAN0, we need 0x1c00 bytes so that the CAN1 don't overlap its message ram: 64 x RX FIFO0 elements => 64 x 72 bytes 32 x TXE (TX Event FIFO) elements => 32 x 8 bytes 32 x TXB (TX Buffer) elements => 32 x 72 bytes So a total of 7168 bytes (0x1C00). Fix offset to match this needed size. Make the CAN0 message ram ioremap match exactly this size so that is easily understandable. Adapt CAN1 size accordingly. Fixes: bc6d5d7666b7 ("ARM: dts: at91: sama5d2: add m_can nodes") Reported-by: Dan Sneddon Signed-off-by: Nicolas Ferre Signed-off-by: Alexandre Belloni Tested-by: Cristian Birsan Cc: stable@vger.kernel.org # v4.13+ Link: https://lore.kernel.org/r/20201203091949.9015-1-nicolas.ferre@microchip.com --- arch/arm/boot/dts/sama5d2.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/sama5d2.dtsi b/arch/arm/boot/dts/sama5d2.dtsi index 6d399ac0385d..2c4952427296 100644 --- a/arch/arm/boot/dts/sama5d2.dtsi +++ b/arch/arm/boot/dts/sama5d2.dtsi @@ -725,7 +725,7 @@ can0: can@f8054000 { compatible = "bosch,m_can"; - reg = <0xf8054000 0x4000>, <0x210000 0x4000>; + reg = <0xf8054000 0x4000>, <0x210000 0x1c00>; reg-names = "m_can", "message_ram"; interrupts = <56 IRQ_TYPE_LEVEL_HIGH 7>, <64 IRQ_TYPE_LEVEL_HIGH 7>; @@ -1131,7 +1131,7 @@ can1: can@fc050000 { compatible = "bosch,m_can"; - reg = <0xfc050000 0x4000>, <0x210000 0x4000>; + reg = <0xfc050000 0x4000>, <0x210000 0x3800>; reg-names = "m_can", "message_ram"; interrupts = <57 IRQ_TYPE_LEVEL_HIGH 7>, <65 IRQ_TYPE_LEVEL_HIGH 7>; @@ -1141,7 +1141,7 @@ assigned-clocks = <&pmc PMC_TYPE_GCK 57>; assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>; assigned-clock-rates = <40000000>; - bosch,mram-cfg = <0x1100 0 0 64 0 0 32 32>; + bosch,mram-cfg = <0x1c00 0 0 64 0 0 32 32>; status = "disabled"; }; From a15ac665b9e9c90b1557499f2a46c1e89d29154a Mon Sep 17 00:00:00 2001 From: Eric Farman Date: Thu, 3 Dec 2020 22:35:11 +0100 Subject: [PATCH 733/799] vfio-mdev: Wire in a request handler for mdev parent While performing some destructive tests with vfio-ccw, where the paths to a device are forcible removed and thus the device itself is unreachable, it is rather easy to end up in an endless loop in vfio_del_group_dev() due to the lack of a request callback for the associated device. In this example, one MDEV (77c) is used by a guest, while another (77b) is not. The symptom is that the iommu is detached from the mdev for 77b, but not 77c, until that guest is shutdown: [ 238.794867] vfio_ccw 0.0.077b: MDEV: Unregistering [ 238.794996] vfio_mdev 11f2d2bc-4083-431d-a023-eff72715c4f0: Removing from iommu group 2 [ 238.795001] vfio_mdev 11f2d2bc-4083-431d-a023-eff72715c4f0: MDEV: detaching iommu [ 238.795036] vfio_ccw 0.0.077c: MDEV: Unregistering ...silence... Let's wire in the request call back to the mdev device, so that a device being physically removed from the host can be (gracefully?) handled by the parent device at the time the device is removed. Add a message when registering the device if a driver doesn't provide this callback, so a clue is given that this same loop may be encountered in a similar situation, and a message when this occurs instead of the awkward silence noted above. Signed-off-by: Eric Farman Reviewed-by: Cornelia Huck Signed-off-by: Alex Williamson --- drivers/vfio/mdev/mdev_core.c | 4 ++++ drivers/vfio/mdev/vfio_mdev.c | 13 +++++++++++++ include/linux/mdev.h | 4 ++++ 3 files changed, 21 insertions(+) diff --git a/drivers/vfio/mdev/mdev_core.c b/drivers/vfio/mdev/mdev_core.c index b558d4cfd082..6de97d25a3f8 100644 --- a/drivers/vfio/mdev/mdev_core.c +++ b/drivers/vfio/mdev/mdev_core.c @@ -154,6 +154,10 @@ int mdev_register_device(struct device *dev, const struct mdev_parent_ops *ops) if (!dev) return -EINVAL; + /* Not mandatory, but its absence could be a problem */ + if (!ops->request) + dev_info(dev, "Driver cannot be asked to release device\n"); + mutex_lock(&parent_list_lock); /* Check for duplicate */ diff --git a/drivers/vfio/mdev/vfio_mdev.c b/drivers/vfio/mdev/vfio_mdev.c index 30964a4e0a28..b52eea128549 100644 --- a/drivers/vfio/mdev/vfio_mdev.c +++ b/drivers/vfio/mdev/vfio_mdev.c @@ -98,6 +98,18 @@ static int vfio_mdev_mmap(void *device_data, struct vm_area_struct *vma) return parent->ops->mmap(mdev, vma); } +static void vfio_mdev_request(void *device_data, unsigned int count) +{ + struct mdev_device *mdev = device_data; + struct mdev_parent *parent = mdev->parent; + + if (parent->ops->request) + parent->ops->request(mdev, count); + else if (count == 0) + dev_notice(mdev_dev(mdev), + "No mdev vendor driver request callback support, blocked until released by user\n"); +} + static const struct vfio_device_ops vfio_mdev_dev_ops = { .name = "vfio-mdev", .open = vfio_mdev_open, @@ -106,6 +118,7 @@ static const struct vfio_device_ops vfio_mdev_dev_ops = { .read = vfio_mdev_read, .write = vfio_mdev_write, .mmap = vfio_mdev_mmap, + .request = vfio_mdev_request, }; static int vfio_mdev_probe(struct device *dev) diff --git a/include/linux/mdev.h b/include/linux/mdev.h index 0ce30ca78db0..9004375c462e 100644 --- a/include/linux/mdev.h +++ b/include/linux/mdev.h @@ -72,6 +72,9 @@ struct device *mdev_get_iommu_device(struct device *dev); * @mmap: mmap callback * @mdev: mediated device structure * @vma: vma structure + * @request: request callback to release device + * @mdev: mediated device structure + * @count: request sequence number * Parent device that support mediated device should be registered with mdev * module with mdev_parent_ops structure. **/ @@ -92,6 +95,7 @@ struct mdev_parent_ops { long (*ioctl)(struct mdev_device *mdev, unsigned int cmd, unsigned long arg); int (*mmap)(struct mdev_device *mdev, struct vm_area_struct *vma); + void (*request)(struct mdev_device *mdev, unsigned int count); }; /* interface for exporting mdev supported type attributes */ From bccce80bbd44ab50bbec761a51c6293c1ce47e34 Mon Sep 17 00:00:00 2001 From: Eric Farman Date: Thu, 3 Dec 2020 22:35:12 +0100 Subject: [PATCH 734/799] vfio-ccw: Wire in the request callback The device is being unplugged, so pass the request to userspace to ask for a graceful cleanup. This should free up the thread that would otherwise loop waiting for the device to be fully released. Signed-off-by: Eric Farman Reviewed-by: Cornelia Huck Signed-off-by: Alex Williamson --- drivers/s390/cio/vfio_ccw_ops.c | 26 ++++++++++++++++++++++++++ drivers/s390/cio/vfio_ccw_private.h | 4 ++++ include/uapi/linux/vfio.h | 1 + 3 files changed, 31 insertions(+) diff --git a/drivers/s390/cio/vfio_ccw_ops.c b/drivers/s390/cio/vfio_ccw_ops.c index 8b3ed5b45277..68106be4ba7a 100644 --- a/drivers/s390/cio/vfio_ccw_ops.c +++ b/drivers/s390/cio/vfio_ccw_ops.c @@ -394,6 +394,7 @@ static int vfio_ccw_mdev_get_irq_info(struct vfio_irq_info *info) switch (info->index) { case VFIO_CCW_IO_IRQ_INDEX: case VFIO_CCW_CRW_IRQ_INDEX: + case VFIO_CCW_REQ_IRQ_INDEX: info->count = 1; info->flags = VFIO_IRQ_INFO_EVENTFD; break; @@ -424,6 +425,9 @@ static int vfio_ccw_mdev_set_irqs(struct mdev_device *mdev, case VFIO_CCW_CRW_IRQ_INDEX: ctx = &private->crw_trigger; break; + case VFIO_CCW_REQ_IRQ_INDEX: + ctx = &private->req_trigger; + break; default: return -EINVAL; } @@ -607,6 +611,27 @@ static ssize_t vfio_ccw_mdev_ioctl(struct mdev_device *mdev, } } +/* Request removal of the device*/ +static void vfio_ccw_mdev_request(struct mdev_device *mdev, unsigned int count) +{ + struct vfio_ccw_private *private = dev_get_drvdata(mdev_parent_dev(mdev)); + + if (!private) + return; + + if (private->req_trigger) { + if (!(count % 10)) + dev_notice_ratelimited(mdev_dev(private->mdev), + "Relaying device request to user (#%u)\n", + count); + + eventfd_signal(private->req_trigger, 1); + } else if (count == 0) { + dev_notice(mdev_dev(private->mdev), + "No device request channel registered, blocked until released by user\n"); + } +} + static const struct mdev_parent_ops vfio_ccw_mdev_ops = { .owner = THIS_MODULE, .supported_type_groups = mdev_type_groups, @@ -617,6 +642,7 @@ static const struct mdev_parent_ops vfio_ccw_mdev_ops = { .read = vfio_ccw_mdev_read, .write = vfio_ccw_mdev_write, .ioctl = vfio_ccw_mdev_ioctl, + .request = vfio_ccw_mdev_request, }; int vfio_ccw_mdev_reg(struct subchannel *sch) diff --git a/drivers/s390/cio/vfio_ccw_private.h b/drivers/s390/cio/vfio_ccw_private.h index 8723156b29ea..b2c762eb42b9 100644 --- a/drivers/s390/cio/vfio_ccw_private.h +++ b/drivers/s390/cio/vfio_ccw_private.h @@ -84,7 +84,10 @@ struct vfio_ccw_crw { * @irb: irb info received from interrupt * @scsw: scsw info * @io_trigger: eventfd ctx for signaling userspace I/O results + * @crw_trigger: eventfd ctx for signaling userspace CRW information + * @req_trigger: eventfd ctx for signaling userspace to return device * @io_work: work for deferral process of I/O handling + * @crw_work: work for deferral process of CRW handling */ struct vfio_ccw_private { struct subchannel *sch; @@ -108,6 +111,7 @@ struct vfio_ccw_private { struct eventfd_ctx *io_trigger; struct eventfd_ctx *crw_trigger; + struct eventfd_ctx *req_trigger; struct work_struct io_work; struct work_struct crw_work; } __aligned(8); diff --git a/include/uapi/linux/vfio.h b/include/uapi/linux/vfio.h index 2f313a238a8f..d1812777139f 100644 --- a/include/uapi/linux/vfio.h +++ b/include/uapi/linux/vfio.h @@ -820,6 +820,7 @@ enum { enum { VFIO_CCW_IO_IRQ_INDEX, VFIO_CCW_CRW_IRQ_INDEX, + VFIO_CCW_REQ_IRQ_INDEX, VFIO_CCW_NUM_IRQS }; From 94dad6bed3c86c00050bf7c2b2ad6b630facae31 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Fri, 4 Dec 2020 14:48:05 +0800 Subject: [PATCH 735/799] arm64: dts: rockchip: Fix UART pull-ups on rk3328 For UARTs, the local pull-ups should be on the RX pin, not the TX pin. UARTs transmit active-low, so a disconnected RX pin should be pulled high instead of left floating to prevent noise being interpreted as transmissions. This gets rid of bogus sysrq events when the UART console is not connected. Fixes: 52e02d377a72 ("arm64: dts: rockchip: add core dtsi file for RK3328 SoCs") Signed-off-by: Chen-Yu Tsai Link: https://lore.kernel.org/r/20201204064805.6480-1-wens@kernel.org Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3328.dtsi | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi index bbdb19a3e85d..db0d5c8e5f96 100644 --- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi @@ -1237,8 +1237,8 @@ uart0 { uart0_xfer: uart0-xfer { - rockchip,pins = <1 RK_PB1 1 &pcfg_pull_up>, - <1 RK_PB0 1 &pcfg_pull_none>; + rockchip,pins = <1 RK_PB1 1 &pcfg_pull_none>, + <1 RK_PB0 1 &pcfg_pull_up>; }; uart0_cts: uart0-cts { @@ -1256,8 +1256,8 @@ uart1 { uart1_xfer: uart1-xfer { - rockchip,pins = <3 RK_PA4 4 &pcfg_pull_up>, - <3 RK_PA6 4 &pcfg_pull_none>; + rockchip,pins = <3 RK_PA4 4 &pcfg_pull_none>, + <3 RK_PA6 4 &pcfg_pull_up>; }; uart1_cts: uart1-cts { @@ -1275,15 +1275,15 @@ uart2-0 { uart2m0_xfer: uart2m0-xfer { - rockchip,pins = <1 RK_PA0 2 &pcfg_pull_up>, - <1 RK_PA1 2 &pcfg_pull_none>; + rockchip,pins = <1 RK_PA0 2 &pcfg_pull_none>, + <1 RK_PA1 2 &pcfg_pull_up>; }; }; uart2-1 { uart2m1_xfer: uart2m1-xfer { - rockchip,pins = <2 RK_PA0 1 &pcfg_pull_up>, - <2 RK_PA1 1 &pcfg_pull_none>; + rockchip,pins = <2 RK_PA0 1 &pcfg_pull_none>, + <2 RK_PA1 1 &pcfg_pull_up>; }; }; From 328c6112787bf7562dbea638840366cd197868d6 Mon Sep 17 00:00:00 2001 From: Vicente Bergas Date: Tue, 1 Dec 2020 16:41:30 +0100 Subject: [PATCH 736/799] arm64: dts: rockchip: fix supplies on rk3399-rock-pi-4 Based on the board schematics at https://dl.radxa.com/rockpi4/docs/hw/rockpi4/rockpi_4c_v12_sch_20200620.pdf on page 18: vcc_lan is not controllable by software, it is just an analog LC filter. Because of this, it can not be turned off-in-suspend. and on page 17: vcc_cam and vcc_mipi are not voltage regulators, they are just switches. So, the voltage range is not applicable. This silences an error message about not being able to adjust the voltage. Signed-off-by: Vicente Bergas Link: https://lore.kernel.org/r/20201201154132.1286-2-vicencb@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi | 8 -------- 1 file changed, 8 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi index 678a336010bf..06df2397bbb4 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi @@ -111,10 +111,6 @@ regulator-boot-on; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; }; vdd_log: vdd-log { @@ -362,8 +358,6 @@ regulator-name = "vcc_cam"; regulator-always-on; regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; regulator-state-mem { regulator-off-in-suspend; }; @@ -373,8 +367,6 @@ regulator-name = "vcc_mipi"; regulator-always-on; regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; regulator-state-mem { regulator-off-in-suspend; }; From eff57d38b546b3a50588e447a41ff3571a407c9f Mon Sep 17 00:00:00 2001 From: Vicente Bergas Date: Tue, 1 Dec 2020 16:41:31 +0100 Subject: [PATCH 737/799] arm64: dts: rockchip: fix I2S conflict on rk3399-rock-pi-4 Based on the board schematics at https://dl.radxa.com/rockpi4/docs/hw/rockpi4/rockpi_4c_v12_sch_20200620.pdf on page 14: Only two channels of I2S are connected and the extra I2S pins are in conflict with other functions like USB power. Signed-off-by: Vicente Bergas Link: https://lore.kernel.org/r/20201201154132.1286-3-vicencb@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi index 06df2397bbb4..63b029a543c1 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi @@ -432,8 +432,9 @@ }; &i2s0 { - rockchip,playback-channels = <8>; - rockchip,capture-channels = <8>; + pinctrl-0 = <&i2s0_2ch_bus>; + rockchip,capture-channels = <2>; + rockchip,playback-channels = <2>; status = "okay"; }; From e12f67fe83446432ef16704c22ec23bd1dbcd094 Mon Sep 17 00:00:00 2001 From: Vicente Bergas Date: Tue, 1 Dec 2020 16:41:32 +0100 Subject: [PATCH 738/799] arm64: dts: rockchip: use USB host by default on rk3399-rock-pi-4 Based on the board schematics at https://dl.radxa.com/rockpi4/docs/hw/rockpi4/rockpi_4c_v12_sch_20200620.pdf on page 19 there is an USB Type-A receptacle being used as an USB-OTG port. But the Type-A connector is not valid for OTG operation, for this reason there is a switch to select host or device role. This is non-compliant and error prone because switching is manual. So, use host mode as it corresponds for a Type-A receptacle. Signed-off-by: Vicente Bergas Link: https://lore.kernel.org/r/20201201154132.1286-4-vicencb@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi index 63b029a543c1..fb7599f07af4 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi @@ -673,7 +673,7 @@ &usbdrd_dwc3_0 { status = "okay"; - dr_mode = "otg"; + dr_mode = "host"; }; &usbdrd3_1 { From b03455ae3c8a7e7999f9cc43ad87c63b44a89344 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Wed, 2 Dec 2020 18:44:17 +0100 Subject: [PATCH 739/799] arm64: dts: meson-axg: add GE2D node This adds the node for the GE2D accelerator unit. Signed-off-by: Neil Armstrong Signed-off-by: Kevin Hilman Link: https://lore.kernel.org/r/20201202174417.3778306-5-narmstrong@baylibre.com --- arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi index bd8c4ac128a8..ba1c6dfdc4b6 100644 --- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi @@ -1727,6 +1727,15 @@ }; }; + ge2d: ge2d@ff940000 { + compatible = "amlogic,axg-ge2d"; + reg = <0x0 0xff940000 0x0 0x10000>; + interrupts = ; + clocks = <&clkc CLKID_VAPB>; + resets = <&reset RESET_GE2D>; + reset-names = "core"; + }; + gic: interrupt-controller@ffc01000 { compatible = "arm,gic-400"; reg = <0x0 0xffc01000 0 0x1000>, From ec78dc8964bbc68d76d0e9b132379bc3f22c72a6 Mon Sep 17 00:00:00 2001 From: Christian Hewitt Date: Thu, 3 Dec 2020 06:00:17 +0000 Subject: [PATCH 740/799] arm64: dts: meson: add audio playback to a95x Add initial audio support limited to HDMI i2s. Signed-off-by: Christian Hewitt Acked-by: Jerome Brunet Signed-off-by: Kevin Hilman Link: https://lore.kernel.org/r/20201203060023.9454-2-christianshewitt@gmail.com --- .../dts/amlogic/meson-gxbb-nexbox-a95x.dts | 40 +++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-nexbox-a95x.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-nexbox-a95x.dts index 67d901ed2fa3..b5b11cb9f393 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb-nexbox-a95x.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-nexbox-a95x.dts @@ -10,6 +10,7 @@ #include "meson-gxbb.dtsi" #include #include +#include / { compatible = "nexbox,a95x", "amlogic,meson-gxbb"; @@ -139,6 +140,45 @@ }; }; }; + + sound { + compatible = "amlogic,gx-sound-card"; + model = "GXBB-NEXBOX-A95X"; + assigned-clocks = <&clkc CLKID_MPLL0>, + <&clkc CLKID_MPLL1>, + <&clkc CLKID_MPLL2>; + assigned-clock-parents = <0>, <0>, <0>; + assigned-clock-rates = <294912000>, + <270950400>, + <393216000>; + status = "okay"; + + dai-link-0 { + sound-dai = <&aiu AIU_CPU CPU_I2S_FIFO>; + }; + + dai-link-1 { + sound-dai = <&aiu AIU_CPU CPU_I2S_ENCODER>; + dai-format = "i2s"; + mclk-fs = <256>; + + codec-0 { + sound-dai = <&aiu AIU_HDMI CTRL_I2S>; + }; + }; + + dai-link-2 { + sound-dai = <&aiu AIU_HDMI CTRL_OUT>; + + codec-0 { + sound-dai = <&hdmi_tx>; + }; + }; + }; +}; + +&aiu { + status = "okay"; }; &cvbs_vdac_port { From 4e0649f4957436cbce20ffc26239fdbe19638444 Mon Sep 17 00:00:00 2001 From: Christian Hewitt Date: Thu, 3 Dec 2020 06:00:18 +0000 Subject: [PATCH 741/799] arm64: dts: meson: add audio playback to khadas-vim Add initial audio support limited to HDMI i2s. Signed-off-by: Christian Hewitt Acked-by: Jerome Brunet Signed-off-by: Kevin Hilman Link: https://lore.kernel.org/r/20201203060023.9454-3-christianshewitt@gmail.com --- .../amlogic/meson-gxl-s905x-khadas-vim.dts | 40 +++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-khadas-vim.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-khadas-vim.dts index 638a5992d760..7aa08f74c49b 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-khadas-vim.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-khadas-vim.dts @@ -8,6 +8,7 @@ #include #include "meson-gxl-s905x-p212.dtsi" +#include / { compatible = "khadas,vim", "amlogic,s905x", "amlogic,meson-gxl"; @@ -63,6 +64,45 @@ }; }; }; + + sound { + compatible = "amlogic,gx-sound-card"; + model = "GXL-KHADAS-VIM1"; + assigned-clocks = <&clkc CLKID_MPLL0>, + <&clkc CLKID_MPLL1>, + <&clkc CLKID_MPLL2>; + assigned-clock-parents = <0>, <0>, <0>; + assigned-clock-rates = <294912000>, + <270950400>, + <393216000>; + status = "okay"; + + dai-link-0 { + sound-dai = <&aiu AIU_CPU CPU_I2S_FIFO>; + }; + + dai-link-1 { + sound-dai = <&aiu AIU_CPU CPU_I2S_ENCODER>; + dai-format = "i2s"; + mclk-fs = <256>; + + codec-0 { + sound-dai = <&aiu AIU_HDMI CTRL_I2S>; + }; + }; + + dai-link-2 { + sound-dai = <&aiu AIU_HDMI CTRL_OUT>; + + codec-0 { + sound-dai = <&hdmi_tx>; + }; + }; + }; +}; + +&aiu { + status = "okay"; }; &cec_AO { From 0157e1a63c7685dfeee4e7cfd22635ebf104f64f Mon Sep 17 00:00:00 2001 From: Christian Hewitt Date: Thu, 3 Dec 2020 06:00:19 +0000 Subject: [PATCH 742/799] arm64: dts: meson: add audio playback to khadas-vim2 Add initial audio support limited to HDMI i2s. Signed-off-by: Christian Hewitt Acked-by: Jerome Brunet Signed-off-by: Kevin Hilman Link: https://lore.kernel.org/r/20201203060023.9454-4-christianshewitt@gmail.com --- .../dts/amlogic/meson-gxm-khadas-vim2.dts | 40 +++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts b/arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts index c5ee55caae0a..0250c98dbe9e 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts @@ -10,6 +10,7 @@ #include #include "meson-gxm.dtsi" +#include / { compatible = "khadas,vim2", "amlogic,s912", "amlogic,meson-gxm"; @@ -145,6 +146,45 @@ clock-frequency = <32768>; pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */ }; + + sound { + compatible = "amlogic,gx-sound-card"; + model = "GXM-KHADAS-VIM2"; + assigned-clocks = <&clkc CLKID_MPLL0>, + <&clkc CLKID_MPLL1>, + <&clkc CLKID_MPLL2>; + assigned-clock-parents = <0>, <0>, <0>; + assigned-clock-rates = <294912000>, + <270950400>, + <393216000>; + status = "okay"; + + dai-link-0 { + sound-dai = <&aiu AIU_CPU CPU_I2S_FIFO>; + }; + + dai-link-1 { + sound-dai = <&aiu AIU_CPU CPU_I2S_ENCODER>; + dai-format = "i2s"; + mclk-fs = <256>; + + codec-0 { + sound-dai = <&aiu AIU_HDMI CTRL_I2S>; + }; + }; + + dai-link-2 { + sound-dai = <&aiu AIU_HDMI CTRL_OUT>; + + codec-0 { + sound-dai = <&hdmi_tx>; + }; + }; + }; +}; + +&aiu { + status = "okay"; }; &cec_AO { From 6a74f78c34e7503e35da724cdc555f26ea8d1cd1 Mon Sep 17 00:00:00 2001 From: Christian Hewitt Date: Thu, 3 Dec 2020 06:00:20 +0000 Subject: [PATCH 743/799] arm64: dts: meson: add audio playback to nanopi-k2 Add initial audio support limited to HDMI i2s. Signed-off-by: Christian Hewitt Acked-by: Jerome Brunet Signed-off-by: Kevin Hilman Link: https://lore.kernel.org/r/20201203060023.9454-5-christianshewitt@gmail.com --- .../boot/dts/amlogic/meson-gxbb-nanopi-k2.dts | 40 +++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-nanopi-k2.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-nanopi-k2.dts index 7be3e354093b..8e5df00b06a2 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb-nanopi-k2.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-nanopi-k2.dts @@ -7,6 +7,7 @@ #include "meson-gxbb.dtsi" #include +#include / { compatible = "friendlyarm,nanopi-k2", "amlogic,meson-gxbb"; @@ -130,6 +131,45 @@ }; }; }; + + sound { + compatible = "amlogic,gx-sound-card"; + model = "GXBB-NANOPI-K2"; + assigned-clocks = <&clkc CLKID_MPLL0>, + <&clkc CLKID_MPLL1>, + <&clkc CLKID_MPLL2>; + assigned-clock-parents = <0>, <0>, <0>; + assigned-clock-rates = <294912000>, + <270950400>, + <393216000>; + status = "okay"; + + dai-link-0 { + sound-dai = <&aiu AIU_CPU CPU_I2S_FIFO>; + }; + + dai-link-1 { + sound-dai = <&aiu AIU_CPU CPU_I2S_ENCODER>; + dai-format = "i2s"; + mclk-fs = <256>; + + codec-0 { + sound-dai = <&aiu AIU_HDMI CTRL_I2S>; + }; + }; + + dai-link-2 { + sound-dai = <&aiu AIU_HDMI CTRL_OUT>; + + codec-0 { + sound-dai = <&hdmi_tx>; + }; + }; + }; +}; + +&aiu { + status = "okay"; }; &cec_AO { From ba414bc5484873bb157e63ba8684d59e27feaeb2 Mon Sep 17 00:00:00 2001 From: Christian Hewitt Date: Thu, 3 Dec 2020 06:00:21 +0000 Subject: [PATCH 744/799] arm64: dts: meson: add audio playback to odroid-c2 Add initial audio support limited to HDMI i2s. Signed-off-by: Christian Hewitt Acked-by: Jerome Brunet Signed-off-by: Kevin Hilman Link: https://lore.kernel.org/r/20201203060023.9454-6-christianshewitt@gmail.com --- .../boot/dts/amlogic/meson-gxbb-odroidc2.dts | 40 +++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts index 70fcfb7b0683..9d8c919c6e19 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts @@ -9,6 +9,7 @@ #include "meson-gxbb.dtsi" #include +#include / { compatible = "hardkernel,odroid-c2", "amlogic,meson-gxbb"; @@ -172,6 +173,45 @@ }; }; }; + + sound { + compatible = "amlogic,gx-sound-card"; + model = "GXBB-ODROID-C2"; + assigned-clocks = <&clkc CLKID_MPLL0>, + <&clkc CLKID_MPLL1>, + <&clkc CLKID_MPLL2>; + assigned-clock-parents = <0>, <0>, <0>; + assigned-clock-rates = <294912000>, + <270950400>, + <393216000>; + status = "okay"; + + dai-link-0 { + sound-dai = <&aiu AIU_CPU CPU_I2S_FIFO>; + }; + + dai-link-1 { + sound-dai = <&aiu AIU_CPU CPU_I2S_ENCODER>; + dai-format = "i2s"; + mclk-fs = <256>; + + codec-0 { + sound-dai = <&aiu AIU_HDMI CTRL_I2S>; + }; + }; + + dai-link-2 { + sound-dai = <&aiu AIU_HDMI CTRL_OUT>; + + codec-0 { + sound-dai = <&hdmi_tx>; + }; + }; + }; +}; + +&aiu { + status = "okay"; }; &cec_AO { From e0d9e6eead35be9842aae14f424f2d2ab0be0678 Mon Sep 17 00:00:00 2001 From: Christian Hewitt Date: Thu, 3 Dec 2020 06:00:22 +0000 Subject: [PATCH 745/799] arm64: dts: meson: add audio playback to wetek-hub Add initial audio support limited to HDMI i2s. Signed-off-by: Christian Hewitt Acked-by: Jerome Brunet Signed-off-by: Kevin Hilman Link: https://lore.kernel.org/r/20201203060023.9454-7-christianshewitt@gmail.com --- .../boot/dts/amlogic/meson-gxbb-wetek-hub.dts | 40 +++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-wetek-hub.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-wetek-hub.dts index 83b985bb015e..0c1570153842 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb-wetek-hub.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-wetek-hub.dts @@ -7,10 +7,50 @@ /dts-v1/; #include "meson-gxbb-wetek.dtsi" +#include / { compatible = "wetek,hub", "amlogic,meson-gxbb"; model = "WeTek Hub"; + + sound { + compatible = "amlogic,gx-sound-card"; + model = "GXBB-WETEK-HUB"; + assigned-clocks = <&clkc CLKID_MPLL0>, + <&clkc CLKID_MPLL1>, + <&clkc CLKID_MPLL2>; + assigned-clock-parents = <0>, <0>, <0>; + assigned-clock-rates = <294912000>, + <270950400>, + <393216000>; + status = "okay"; + + dai-link-0 { + sound-dai = <&aiu AIU_CPU CPU_I2S_FIFO>; + }; + + dai-link-1 { + sound-dai = <&aiu AIU_CPU CPU_I2S_ENCODER>; + dai-format = "i2s"; + mclk-fs = <256>; + + codec-0 { + sound-dai = <&aiu AIU_HDMI CTRL_I2S>; + }; + }; + + dai-link-2 { + sound-dai = <&aiu AIU_HDMI CTRL_OUT>; + + codec-0 { + sound-dai = <&hdmi_tx>; + }; + }; + }; +}; + +&aiu { + status = "okay"; }; &ir { From 5e3ee48ea072a6fd2c46c552d013e047dc54d1c6 Mon Sep 17 00:00:00 2001 From: Christian Hewitt Date: Thu, 3 Dec 2020 06:00:23 +0000 Subject: [PATCH 746/799] arm64: dts: meson: add audio playback to wetek-play2 Add initial support limited to HDMI i2s and SPDIF (LPCM). Signed-off-by: Christian Hewitt Acked-by: Jerome Brunet Signed-off-by: Kevin Hilman Link: https://lore.kernel.org/r/20201203060023.9454-8-christianshewitt@gmail.com --- .../dts/amlogic/meson-gxbb-wetek-play2.dts | 61 +++++++++++++++++++ 1 file changed, 61 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-wetek-play2.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-wetek-play2.dts index 2ab8a3d10079..f2562c7de67c 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb-wetek-play2.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-wetek-play2.dts @@ -8,11 +8,19 @@ #include "meson-gxbb-wetek.dtsi" #include +#include / { compatible = "wetek,play2", "amlogic,meson-gxbb"; model = "WeTek Play 2"; + spdif_dit: audio-codec-0 { + #sound-dai-cells = <0>; + compatible = "linux,spdif-dit"; + status = "okay"; + sound-name-prefix = "DIT"; + }; + leds { led-wifi { label = "wetek-play:wifi-status"; @@ -39,6 +47,59 @@ gpios = <&gpio_ao GPIOAO_3 GPIO_ACTIVE_LOW>; }; }; + + sound { + compatible = "amlogic,gx-sound-card"; + model = "GXBB-WETEK-PLAY2"; + assigned-clocks = <&clkc CLKID_MPLL0>, + <&clkc CLKID_MPLL1>, + <&clkc CLKID_MPLL2>; + assigned-clock-parents = <0>, <0>, <0>; + assigned-clock-rates = <294912000>, + <270950400>, + <393216000>; + status = "okay"; + + dai-link-0 { + sound-dai = <&aiu AIU_CPU CPU_I2S_FIFO>; + }; + + dai-link-1 { + sound-dai = <&aiu AIU_CPU CPU_SPDIF_FIFO>; + }; + + dai-link-2 { + sound-dai = <&aiu AIU_CPU CPU_I2S_ENCODER>; + dai-format = "i2s"; + mclk-fs = <256>; + + codec-0 { + sound-dai = <&aiu AIU_HDMI CTRL_I2S>; + }; + }; + + dai-link-3 { + sound-dai = <&aiu AIU_CPU CPU_SPDIF_ENCODER>; + + codec-0 { + sound-dai = <&spdif_dit>; + }; + }; + + dai-link-4 { + sound-dai = <&aiu AIU_HDMI CTRL_OUT>; + + codec-0 { + sound-dai = <&hdmi_tx>; + }; + }; + }; +}; + +&aiu { + status = "okay"; + pinctrl-0 = <&spdif_out_y_pins>; + pinctrl-names = "default"; }; &i2c_A { From c993c4e84369acf5686a6f345ebb0efb0107f73e Mon Sep 17 00:00:00 2001 From: Christian Hewitt Date: Thu, 3 Dec 2020 06:16:05 +0000 Subject: [PATCH 747/799] arm64: dts: meson: minor fixups for Khadas VIM/VIM2 dts Reorder the VIM/VIM2 includes/bindings to follow the format of other dts in the Amlogic tree and remove a stray empty line in the VIM2 dts. Signed-off-by: Christian Hewitt Reviewed-by: Neil Armstrong Signed-off-by: Kevin Hilman Link: https://lore.kernel.org/r/20201203061605.9603-1-christianshewitt@gmail.com --- arch/arm64/boot/dts/amlogic/meson-gxl-s905x-khadas-vim.dts | 3 +-- arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts | 4 +--- 2 files changed, 2 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-khadas-vim.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-khadas-vim.dts index 7aa08f74c49b..6fe589cd2ba2 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-khadas-vim.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-khadas-vim.dts @@ -5,9 +5,8 @@ /dts-v1/; -#include - #include "meson-gxl-s905x-p212.dtsi" +#include #include / { diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts b/arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts index 0250c98dbe9e..955a63aaa5ed 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts @@ -7,9 +7,8 @@ /dts-v1/; -#include - #include "meson-gxm.dtsi" +#include #include / { @@ -194,7 +193,6 @@ hdmi-phandle = <&hdmi_tx>; }; - &cpu_cooling_maps { map0 { cooling-device = <&gpio_fan THERMAL_NO_LIMIT 1>; From 1c7412530d5d0e0a0b27f1642f5c13c8b9f36f05 Mon Sep 17 00:00:00 2001 From: Stefan Agner Date: Mon, 7 Dec 2020 18:57:59 +0100 Subject: [PATCH 748/799] arm64: dts: meson: g12b: odroid-n2: fix PHY deassert timing requirements According to the datasheet (Rev. 1.9) the RTL8211F requires at least 72ms "for internal circuits settling time" before accessing the PHY registers. This fixes an issue where the Ethernet link doesn't come up when using ip link set down/up: [ 29.360965] meson8b-dwmac ff3f0000.ethernet eth0: Link is Down [ 34.569012] meson8b-dwmac ff3f0000.ethernet eth0: PHY [0.0:00] driver [RTL8211F Gigabit Ethernet] (irq=31) [ 34.676732] meson8b-dwmac ff3f0000.ethernet: Failed to reset the dma [ 34.678874] meson8b-dwmac ff3f0000.ethernet eth0: stmmac_hw_setup: DMA engine initialization failed [ 34.687850] meson8b-dwmac ff3f0000.ethernet eth0: stmmac_open: Hw setup failed Fixes: 658e4129bb81 ("arm64: dts: meson: g12b: odroid-n2: add the Ethernet PHY reset line") Reviewed-by: Martin Blumenstingl Signed-off-by: Stefan Agner Signed-off-by: Kevin Hilman Link: https://lore.kernel.org/r/df3f5c4fc6e43c55429fd3662a636036a21eed49.1607363522.git.stefan@agner.ch --- arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dtsi index 6982632ae646..39a09661c5f6 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dtsi @@ -413,7 +413,7 @@ max-speed = <1000>; reset-assert-us = <10000>; - reset-deassert-us = <30000>; + reset-deassert-us = <80000>; reset-gpios = <&gpio GPIOZ_15 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>; interrupt-parent = <&gpio_intc>; From c183c406c4321002fe85b345b51bc1a3a04b6d33 Mon Sep 17 00:00:00 2001 From: Stefan Agner Date: Mon, 7 Dec 2020 18:58:00 +0100 Subject: [PATCH 749/799] arm64: dts: meson: fix PHY deassert timing requirements According to the datasheet (Rev. 1.9) the RTL8211F requires at least 72ms "for internal circuits settling time" before accessing the PHY registers. This fixes an issue seen on ODROID-C2 where the Ethernet link doesn't come up when using ip link set down/up: [ 6630.714855] meson8b-dwmac c9410000.ethernet eth0: Link is Down [ 6630.785775] meson8b-dwmac c9410000.ethernet eth0: PHY [stmmac-0:00] driver [RTL8211F Gigabit Ethernet] (irq=36) [ 6630.893071] meson8b-dwmac c9410000.ethernet: Failed to reset the dma [ 6630.893800] meson8b-dwmac c9410000.ethernet eth0: stmmac_hw_setup: DMA engine initialization failed [ 6630.902835] meson8b-dwmac c9410000.ethernet eth0: stmmac_open: Hw setup failed Fixes: f29cabf240ed ("arm64: dts: meson: use the generic Ethernet PHY reset GPIO bindings") Reviewed-by: Martin Blumenstingl Signed-off-by: Stefan Agner Signed-off-by: Kevin Hilman Link: https://lore.kernel.org/r/4a322c198b86e4c8b3dda015560a683babea4d63.1607363522.git.stefan@agner.ch --- arch/arm64/boot/dts/amlogic/meson-gxbb-nanopi-k2.dts | 2 +- arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts | 2 +- arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi | 2 +- arch/arm64/boot/dts/amlogic/meson-gxbb-wetek.dtsi | 2 +- arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p230.dts | 2 +- arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts | 2 +- arch/arm64/boot/dts/amlogic/meson-gxm-nexbox-a1.dts | 2 +- arch/arm64/boot/dts/amlogic/meson-gxm-q200.dts | 2 +- arch/arm64/boot/dts/amlogic/meson-gxm-rbox-pro.dts | 2 +- 9 files changed, 9 insertions(+), 9 deletions(-) diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-nanopi-k2.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-nanopi-k2.dts index 8e5df00b06a2..089e0636ba8a 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb-nanopi-k2.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-nanopi-k2.dts @@ -205,7 +205,7 @@ reg = <0>; reset-assert-us = <10000>; - reset-deassert-us = <30000>; + reset-deassert-us = <80000>; reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>; interrupt-parent = <&gpio_intc>; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts index 9d8c919c6e19..c04ef57f7b3b 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts @@ -240,7 +240,7 @@ reg = <0>; reset-assert-us = <10000>; - reset-deassert-us = <30000>; + reset-deassert-us = <80000>; reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>; interrupt-parent = <&gpio_intc>; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi index 222ee8069cfa..9b0b81f191f1 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi @@ -126,7 +126,7 @@ reg = <0>; reset-assert-us = <10000>; - reset-deassert-us = <30000>; + reset-deassert-us = <80000>; reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>; interrupt-parent = <&gpio_intc>; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-wetek.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb-wetek.dtsi index ad812854a107..a350fee1264d 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb-wetek.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-wetek.dtsi @@ -147,7 +147,7 @@ reg = <0>; reset-assert-us = <10000>; - reset-deassert-us = <30000>; + reset-deassert-us = <80000>; reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>; interrupt-parent = <&gpio_intc>; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p230.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p230.dts index b08c4537f260..b2ab05c22090 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p230.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p230.dts @@ -82,7 +82,7 @@ /* External PHY reset is shared with internal PHY Led signal */ reset-assert-us = <10000>; - reset-deassert-us = <30000>; + reset-deassert-us = <80000>; reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>; interrupt-parent = <&gpio_intc>; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts b/arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts index 955a63aaa5ed..bf9877d33427 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts @@ -232,7 +232,7 @@ reg = <0>; reset-assert-us = <10000>; - reset-deassert-us = <30000>; + reset-deassert-us = <80000>; reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>; interrupt-parent = <&gpio_intc>; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm-nexbox-a1.dts b/arch/arm64/boot/dts/amlogic/meson-gxm-nexbox-a1.dts index 83eca3af44ce..dfa7a37a1281 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxm-nexbox-a1.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxm-nexbox-a1.dts @@ -112,7 +112,7 @@ max-speed = <1000>; reset-assert-us = <10000>; - reset-deassert-us = <30000>; + reset-deassert-us = <80000>; reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>; }; }; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm-q200.dts b/arch/arm64/boot/dts/amlogic/meson-gxm-q200.dts index ea45ae0c71b7..8edbfe040805 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxm-q200.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxm-q200.dts @@ -64,7 +64,7 @@ /* External PHY reset is shared with internal PHY Led signal */ reset-assert-us = <10000>; - reset-deassert-us = <30000>; + reset-deassert-us = <80000>; reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>; interrupt-parent = <&gpio_intc>; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm-rbox-pro.dts b/arch/arm64/boot/dts/amlogic/meson-gxm-rbox-pro.dts index c89c9f846fb1..dde7cfe12cff 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxm-rbox-pro.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxm-rbox-pro.dts @@ -114,7 +114,7 @@ max-speed = <1000>; reset-assert-us = <10000>; - reset-deassert-us = <30000>; + reset-deassert-us = <80000>; reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>; }; }; From 656ab1bdcd2b755dc161a9774201100d5bf74b8d Mon Sep 17 00:00:00 2001 From: Stefan Agner Date: Mon, 7 Dec 2020 18:58:01 +0100 Subject: [PATCH 750/799] ARM: dts: meson: fix PHY deassert timing requirements According to the datasheet (Rev. 1.9) the RTL8211F requires at least 72ms "for internal circuits settling time" before accessing the PHY registers. On similar boards with the same PHY this fixes an issue where Ethernet link would not come up when using ip link set down/up. Fixes: a2c6e82e5341 ("ARM: dts: meson: switch to the generic Ethernet PHY reset bindings") Reviewed-by: Martin Blumenstingl Tested-by: Martin Blumenstingl # on Odroid-C1+ Signed-off-by: Stefan Agner Signed-off-by: Kevin Hilman Link: https://lore.kernel.org/r/ff78772b306411e145769c46d4090554344db41e.1607363522.git.stefan@agner.ch --- arch/arm/boot/dts/meson8b-odroidc1.dts | 2 +- arch/arm/boot/dts/meson8m2-mxiii-plus.dts | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/meson8b-odroidc1.dts b/arch/arm/boot/dts/meson8b-odroidc1.dts index 0c26467de4d0..5963566dbcc9 100644 --- a/arch/arm/boot/dts/meson8b-odroidc1.dts +++ b/arch/arm/boot/dts/meson8b-odroidc1.dts @@ -224,7 +224,7 @@ reg = <0>; reset-assert-us = <10000>; - reset-deassert-us = <30000>; + reset-deassert-us = <80000>; reset-gpios = <&gpio GPIOH_4 GPIO_ACTIVE_LOW>; interrupt-parent = <&gpio_intc>; diff --git a/arch/arm/boot/dts/meson8m2-mxiii-plus.dts b/arch/arm/boot/dts/meson8m2-mxiii-plus.dts index cc498191ddd1..8f4eb1ed4581 100644 --- a/arch/arm/boot/dts/meson8m2-mxiii-plus.dts +++ b/arch/arm/boot/dts/meson8m2-mxiii-plus.dts @@ -81,7 +81,7 @@ reg = <0>; reset-assert-us = <10000>; - reset-deassert-us = <30000>; + reset-deassert-us = <80000>; reset-gpios = <&gpio GPIOH_4 GPIO_ACTIVE_LOW>; }; }; From 3d07c3b3a886fefd583c1b485b5e4e3c4e2da493 Mon Sep 17 00:00:00 2001 From: Stefan Agner Date: Mon, 7 Dec 2020 18:58:02 +0100 Subject: [PATCH 751/799] arm64: dts: meson: g12a: x96-max: fix PHY deassert timing requirements According to the datasheet (Rev. 1.9) the RTL8211F requires at least 72ms "for internal circuits settling time" before accessing the PHY registers. On similar boards with the same PHY this fixes an issue where Ethernet link would not come up when using ip link set down/up. Fixes: ed5e8f689154 ("arm64: dts: meson: g12a: x96-max: fix the Ethernet PHY reset line") Reviewed-by: Martin Blumenstingl Signed-off-by: Stefan Agner Signed-off-by: Kevin Hilman Link: https://lore.kernel.org/r/12506964ca5d5f936579a280ad0a7e7f9a0a2d4c.1607363522.git.stefan@agner.ch --- arch/arm64/boot/dts/amlogic/meson-g12a-x96-max.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a-x96-max.dts b/arch/arm64/boot/dts/amlogic/meson-g12a-x96-max.dts index 1b07c8c06eac..463a72d6bb7c 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12a-x96-max.dts +++ b/arch/arm64/boot/dts/amlogic/meson-g12a-x96-max.dts @@ -340,7 +340,7 @@ eee-broken-1000t; reset-assert-us = <10000>; - reset-deassert-us = <30000>; + reset-deassert-us = <80000>; reset-gpios = <&gpio GPIOZ_15 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>; interrupt-parent = <&gpio_intc>; From 9e454e37dc7c0ee9e108d70b983e7a71332aedff Mon Sep 17 00:00:00 2001 From: Stefan Agner Date: Mon, 7 Dec 2020 18:58:03 +0100 Subject: [PATCH 752/799] arm64: dts: meson: g12b: w400: fix PHY deassert timing requirements According to the datasheet (Rev. 1.9) the RTL8211F requires at least 72ms "for internal circuits settling time" before accessing the PHY egisters. On similar boards with the same PHY this fixes an issue where Ethernet link would not come up when using ip link set down/up. Fixes: 2cd2310fca4c ("arm64: dts: meson-g12b-ugoos-am6: add initial device-tree") Reviewed-by: Martin Blumenstingl Signed-off-by: Stefan Agner Signed-off-by: Kevin Hilman Link: https://lore.kernel.org/r/46298e66572784c44f873f1b71cc4ab3d8fc5aa6.1607363522.git.stefan@agner.ch --- arch/arm64/boot/dts/amlogic/meson-g12b-w400.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-w400.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12b-w400.dtsi index 2802ddbb83ac..feb088504740 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12b-w400.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-g12b-w400.dtsi @@ -264,7 +264,7 @@ max-speed = <1000>; reset-assert-us = <10000>; - reset-deassert-us = <30000>; + reset-deassert-us = <80000>; reset-gpios = <&gpio GPIOZ_15 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>; interrupt-parent = <&gpio_intc>; From 332dde0a5864bc3f00898b24bf3a21f46f702076 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 17 Nov 2020 21:17:52 +0100 Subject: [PATCH 753/799] dt-bindings: arm: vt8500: remove redundant white-spaces Remove redundant white-spaces, no functional change. Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20201117201752.129766-1-krzk@kernel.org Signed-off-by: Rob Herring --- Documentation/devicetree/bindings/arm/vt8500.yaml | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/vt8500.yaml b/Documentation/devicetree/bindings/arm/vt8500.yaml index 29ff399551ca..7b762bfc11e7 100644 --- a/Documentation/devicetree/bindings/arm/vt8500.yaml +++ b/Documentation/devicetree/bindings/arm/vt8500.yaml @@ -21,6 +21,5 @@ properties: - wm,wm8650 - wm,wm8750 - wm,wm8850 - -additionalProperties: true +additionalProperties: true From 96993a59f94db89a3ff0110dc9e3a2af03a1da8b Mon Sep 17 00:00:00 2001 From: Cristian Ciocaltea Date: Wed, 18 Nov 2020 17:20:50 +0200 Subject: [PATCH 754/799] dt-bindings: Fix error in 'make dtbs_check' when using DT_SCHEMA_FILES If DT_SCHEMA_FILES is specified and contains more than one file paths, 'make dtbs_check' fails with the following message: $ make dtbs_check DT_SCHEMA_FILES="path/to/schema1.yaml path/to/schema2.yaml" SCHEMA Documentation/devicetree/bindings/processed-schema.json Documentation/devicetree/bindings/Makefile:77: recipe for target 'Documentation/devicetree/bindings/processed-schema.json' failed make[1]: *** [Documentation/devicetree/bindings/processed-schema.json] Error 255 make[1]: *** Deleting file 'Documentation/devicetree/bindings/processed-schema.json' Makefile:1364: recipe for target 'dt_binding_check' failed make: *** [dt_binding_check] Error 2 The error code 255 is returned by 'dt-mk-schema' when invoked as 'dt-mk-schema -j -u @', where '' is a temporary file that is generated to contain a list of SPACE delimited schema file paths, as indicated via DT_SCHEMA_FILES. However, it seems the file format has been recently changed in 'dt-mk-schema', which now expects each schema path to be provided on a separate line: $ dt-mk-schema --version 2020.12.dev4+g6de1c45 Therefore, let's change '' content format from path/to/schema1.yaml path/to/schema2.yaml ... path/to/schemaN.yaml to path/to/schema1.yaml path/to/schema2.yaml ... path/to/schemaN.yaml Signed-off-by: Cristian Ciocaltea Link: https://lore.kernel.org/r/2519b8bde507ca6ccea9765ea197adaaa69a66d5.1605712328.git.cristian.ciocaltea@gmail.com Signed-off-by: Rob Herring --- Documentation/devicetree/bindings/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/Makefile b/Documentation/devicetree/bindings/Makefile index 285d814369db..8f2b054bec5a 100644 --- a/Documentation/devicetree/bindings/Makefile +++ b/Documentation/devicetree/bindings/Makefile @@ -37,7 +37,7 @@ quiet_cmd_chk_bindings = CHKDT $@ quiet_cmd_mk_schema = SCHEMA $@ cmd_mk_schema = f=$$(mktemp) ; \ $(if $(DT_MK_SCHEMA_FLAGS), \ - echo $(real-prereqs), \ + printf '%s\n' $(real-prereqs), \ $(find_cmd)) > $$f ; \ $(DT_MK_SCHEMA) -j $(DT_MK_SCHEMA_FLAGS) @$$f > $@ ; \ rm -f $$f From 3af2c1a48c037adc1e4da92315e72f023d9b3370 Mon Sep 17 00:00:00 2001 From: Gustavo Pimentel Date: Thu, 19 Nov 2020 00:18:39 +0100 Subject: [PATCH 755/799] dt-bindings: Fix typo on the DesignWare IP reset bindings documentation This patch removes a loose "i" character is present on the current documentation. Signed-off-by: Gustavo Pimentel Link: https://lore.kernel.org/r/89719d8d40048e9b7baa0cd984b5bb108d056de4.1605741519.git.gustavo.pimentel@synopsys.com Signed-off-by: Rob Herring --- Documentation/devicetree/bindings/reset/snps,dw-reset.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/reset/snps,dw-reset.txt b/Documentation/devicetree/bindings/reset/snps,dw-reset.txt index f94f911dd98d..0c241d4aae76 100644 --- a/Documentation/devicetree/bindings/reset/snps,dw-reset.txt +++ b/Documentation/devicetree/bindings/reset/snps,dw-reset.txt @@ -23,7 +23,7 @@ example: #reset-cells = <1>; }; - dw_rst_2: reset-controller@1000 {i + dw_rst_2: reset-controller@1000 { compatible = "snps,dw-low-reset"; reg = <0x1000 0x8>; #reset-cells = <1>; From 1e95c81104e32e9f46b5a6085fee7e6ced25cad9 Mon Sep 17 00:00:00 2001 From: Joel Stanley Date: Thu, 19 Nov 2020 18:02:30 +1030 Subject: [PATCH 756/799] dt-bindings: vendor-prefixes: Add FII Adds Foxconn Industrial Internet, who have submitted a BMC device tree. Reviewed-by: Benjamin Fair Signed-off-by: Joel Stanley Link: https://lore.kernel.org/r/20201119073230.123888-1-joel@jms.id.au Signed-off-by: Rob Herring --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index 2735be1a8470..5e69fbfe544c 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -377,6 +377,8 @@ patternProperties: description: Shenzhen Feixin Photoelectic Co., Ltd "^feiyang,.*": description: Shenzhen Fly Young Technology Co.,LTD. + "^fii,.*": + description: Foxconn Industrial Internet "^firefly,.*": description: Firefly "^focaltech,.*": From d89886eb76f601b6cd78f96a1cebee073d12bf58 Mon Sep 17 00:00:00 2001 From: Jon Hunter Date: Tue, 24 Nov 2020 12:18:42 +0000 Subject: [PATCH 757/799] dt-bindings: Correct GV11B GPU register sizes Commit 90a09178f309 ("dt-bindings: Add documentation for GV11B GPU") added the GV11B GPU device-tree bindings information but incorrectly added an additional 0 to the size of the addresses in the example. Fixes: 90a09178f309 ("dt-bindings: Add documentation for GV11B GPU") Acked-by: Thierry Reding Signed-off-by: Jon Hunter Link: https://lore.kernel.org/r/20201124121842.1037035-1-jonathanh@nvidia.com Signed-off-by: Rob Herring --- Documentation/devicetree/bindings/gpu/nvidia,gk20a.txt | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/gpu/nvidia,gk20a.txt b/Documentation/devicetree/bindings/gpu/nvidia,gk20a.txt index 662a3c8a7d29..cc6ce5221a38 100644 --- a/Documentation/devicetree/bindings/gpu/nvidia,gk20a.txt +++ b/Documentation/devicetree/bindings/gpu/nvidia,gk20a.txt @@ -97,8 +97,8 @@ Example for GV11B: gpu@17000000 { compatible = "nvidia,gv11b"; - reg = <0x17000000 0x10000000>, - <0x18000000 0x10000000>; + reg = <0x17000000 0x1000000>, + <0x18000000 0x1000000>; interrupts = , ; interrupt-names = "stall", "nonstall"; From 0437141b4e2233ae0109a9584e7a003cd05b0a20 Mon Sep 17 00:00:00 2001 From: Andrey Zhizhikin Date: Tue, 1 Dec 2020 22:29:18 +0000 Subject: [PATCH 758/799] ARM: configs: drop unused BACKLIGHT_GENERIC option Commit 7ecdea4a0226 ("backlight: generic_bl: Remove this driver as it is unused") removed geenric_bl driver from the tree, together with corresponding config option. Remove BACKLIGHT_GENERIC config item from all ARM configurations. Fixes: 7ecdea4a0226 ("backlight: generic_bl: Remove this driver as it is unused") Signed-off-by: Andrey Zhizhikin Reviewed-by: Krzysztof Kozlowski Acked-by: Alexandre Belloni Acked-by: Daniel Thompson Acked-by: Sam Ravnborg Cc: Sam Ravnborg Link: https://lore.kernel.org/r/20201201222922.3183-2-andrey.zhizhikin@leica-geosystems.com' Signed-off-by: Arnd Bergmann --- arch/arm/configs/at91_dt_defconfig | 1 - arch/arm/configs/cm_x300_defconfig | 1 - arch/arm/configs/colibri_pxa300_defconfig | 1 - arch/arm/configs/jornada720_defconfig | 1 - arch/arm/configs/magician_defconfig | 1 - arch/arm/configs/mini2440_defconfig | 1 - arch/arm/configs/omap2plus_defconfig | 1 - arch/arm/configs/pxa3xx_defconfig | 1 - arch/arm/configs/qcom_defconfig | 1 - arch/arm/configs/sama5_defconfig | 1 - arch/arm/configs/sunxi_defconfig | 1 - arch/arm/configs/tegra_defconfig | 1 - 12 files changed, 12 deletions(-) diff --git a/arch/arm/configs/at91_dt_defconfig b/arch/arm/configs/at91_dt_defconfig index 91f0f2c41841..c0c219d53b24 100644 --- a/arch/arm/configs/at91_dt_defconfig +++ b/arch/arm/configs/at91_dt_defconfig @@ -137,7 +137,6 @@ CONFIG_DRM_ATMEL_HLCDC=y CONFIG_DRM_PANEL_SIMPLE=y CONFIG_FB_ATMEL=y CONFIG_BACKLIGHT_ATMEL_LCDC=y -# CONFIG_BACKLIGHT_GENERIC is not set CONFIG_BACKLIGHT_PWM=y CONFIG_FRAMEBUFFER_CONSOLE=y CONFIG_LOGO=y diff --git a/arch/arm/configs/cm_x300_defconfig b/arch/arm/configs/cm_x300_defconfig index 2f7acde2d921..502a9d870ca4 100644 --- a/arch/arm/configs/cm_x300_defconfig +++ b/arch/arm/configs/cm_x300_defconfig @@ -87,7 +87,6 @@ CONFIG_FB=y CONFIG_FB_PXA=y CONFIG_LCD_CLASS_DEVICE=y CONFIG_LCD_TDO24M=y -# CONFIG_BACKLIGHT_GENERIC is not set CONFIG_BACKLIGHT_DA903X=m CONFIG_FRAMEBUFFER_CONSOLE=y CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y diff --git a/arch/arm/configs/colibri_pxa300_defconfig b/arch/arm/configs/colibri_pxa300_defconfig index 0dae3b185284..26e5a67f8e2d 100644 --- a/arch/arm/configs/colibri_pxa300_defconfig +++ b/arch/arm/configs/colibri_pxa300_defconfig @@ -34,7 +34,6 @@ CONFIG_FB=y CONFIG_FB_PXA=y # CONFIG_LCD_CLASS_DEVICE is not set CONFIG_BACKLIGHT_CLASS_DEVICE=y -# CONFIG_BACKLIGHT_GENERIC is not set # CONFIG_VGA_CONSOLE is not set CONFIG_FRAMEBUFFER_CONSOLE=y CONFIG_LOGO=y diff --git a/arch/arm/configs/jornada720_defconfig b/arch/arm/configs/jornada720_defconfig index 9f079be2b84b..069f60ffdcd8 100644 --- a/arch/arm/configs/jornada720_defconfig +++ b/arch/arm/configs/jornada720_defconfig @@ -48,7 +48,6 @@ CONFIG_FB=y CONFIG_FB_S1D13XXX=y CONFIG_LCD_CLASS_DEVICE=y CONFIG_BACKLIGHT_CLASS_DEVICE=y -# CONFIG_BACKLIGHT_GENERIC is not set # CONFIG_VGA_CONSOLE is not set CONFIG_FRAMEBUFFER_CONSOLE=y CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y diff --git a/arch/arm/configs/magician_defconfig b/arch/arm/configs/magician_defconfig index d2e684f6565a..b4670d42f378 100644 --- a/arch/arm/configs/magician_defconfig +++ b/arch/arm/configs/magician_defconfig @@ -95,7 +95,6 @@ CONFIG_FB_PXA_OVERLAY=y CONFIG_FB_W100=y CONFIG_LCD_CLASS_DEVICE=y CONFIG_BACKLIGHT_CLASS_DEVICE=y -# CONFIG_BACKLIGHT_GENERIC is not set CONFIG_BACKLIGHT_PWM=y # CONFIG_VGA_CONSOLE is not set CONFIG_FRAMEBUFFER_CONSOLE=y diff --git a/arch/arm/configs/mini2440_defconfig b/arch/arm/configs/mini2440_defconfig index 301f29a1fcc3..898490aaa39e 100644 --- a/arch/arm/configs/mini2440_defconfig +++ b/arch/arm/configs/mini2440_defconfig @@ -158,7 +158,6 @@ CONFIG_FB_S3C2410=y CONFIG_LCD_CLASS_DEVICE=y CONFIG_LCD_PLATFORM=y CONFIG_BACKLIGHT_CLASS_DEVICE=y -# CONFIG_BACKLIGHT_GENERIC is not set CONFIG_BACKLIGHT_PWM=y CONFIG_FRAMEBUFFER_CONSOLE=y CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y diff --git a/arch/arm/configs/omap2plus_defconfig b/arch/arm/configs/omap2plus_defconfig index 77716f500813..ba2b3f89c0fa 100644 --- a/arch/arm/configs/omap2plus_defconfig +++ b/arch/arm/configs/omap2plus_defconfig @@ -390,7 +390,6 @@ CONFIG_FB_TILEBLITTING=y CONFIG_LCD_CLASS_DEVICE=y CONFIG_LCD_PLATFORM=y CONFIG_BACKLIGHT_CLASS_DEVICE=y -CONFIG_BACKLIGHT_GENERIC=m CONFIG_BACKLIGHT_PWM=m CONFIG_BACKLIGHT_PANDORA=m CONFIG_BACKLIGHT_GPIO=m diff --git a/arch/arm/configs/pxa3xx_defconfig b/arch/arm/configs/pxa3xx_defconfig index 06bbc7a59b60..f0c34017f2aa 100644 --- a/arch/arm/configs/pxa3xx_defconfig +++ b/arch/arm/configs/pxa3xx_defconfig @@ -74,7 +74,6 @@ CONFIG_FB_PXA=y CONFIG_LCD_CLASS_DEVICE=y CONFIG_LCD_TDO24M=y CONFIG_BACKLIGHT_CLASS_DEVICE=y -# CONFIG_BACKLIGHT_GENERIC is not set CONFIG_BACKLIGHT_DA903X=y # CONFIG_VGA_CONSOLE is not set CONFIG_FRAMEBUFFER_CONSOLE=y diff --git a/arch/arm/configs/qcom_defconfig b/arch/arm/configs/qcom_defconfig index c882167e1496..d6733e745b80 100644 --- a/arch/arm/configs/qcom_defconfig +++ b/arch/arm/configs/qcom_defconfig @@ -159,7 +159,6 @@ CONFIG_FB=y CONFIG_FRAMEBUFFER_CONSOLE=y # CONFIG_LCD_CLASS_DEVICE is not set CONFIG_BACKLIGHT_CLASS_DEVICE=y -# CONFIG_BACKLIGHT_GENERIC is not set CONFIG_BACKLIGHT_LM3630A=y CONFIG_BACKLIGHT_LP855X=y CONFIG_SOUND=y diff --git a/arch/arm/configs/sama5_defconfig b/arch/arm/configs/sama5_defconfig index 2c8a621a8f1f..5f6297e6c549 100644 --- a/arch/arm/configs/sama5_defconfig +++ b/arch/arm/configs/sama5_defconfig @@ -170,7 +170,6 @@ CONFIG_DRM_ATMEL_HLCDC=y CONFIG_DRM_PANEL_SIMPLE=y CONFIG_LCD_CLASS_DEVICE=y CONFIG_BACKLIGHT_CLASS_DEVICE=y -# CONFIG_BACKLIGHT_GENERIC is not set CONFIG_BACKLIGHT_PWM=y CONFIG_FRAMEBUFFER_CONSOLE=y CONFIG_SOUND=y diff --git a/arch/arm/configs/sunxi_defconfig b/arch/arm/configs/sunxi_defconfig index 05f7f4ed8ded..a60c134c5e04 100644 --- a/arch/arm/configs/sunxi_defconfig +++ b/arch/arm/configs/sunxi_defconfig @@ -112,7 +112,6 @@ CONFIG_DRM_SIMPLE_BRIDGE=y CONFIG_DRM_LIMA=y CONFIG_FB_SIMPLE=y CONFIG_BACKLIGHT_CLASS_DEVICE=y -# CONFIG_BACKLIGHT_GENERIC is not set CONFIG_BACKLIGHT_PWM=y CONFIG_SOUND=y CONFIG_SND=y diff --git a/arch/arm/configs/tegra_defconfig b/arch/arm/configs/tegra_defconfig index fff5fae0db30..74739a52a8ad 100644 --- a/arch/arm/configs/tegra_defconfig +++ b/arch/arm/configs/tegra_defconfig @@ -205,7 +205,6 @@ CONFIG_DRM_PANEL_SIMPLE=y CONFIG_DRM_LVDS_CODEC=y # CONFIG_LCD_CLASS_DEVICE is not set CONFIG_BACKLIGHT_CLASS_DEVICE=y -# CONFIG_BACKLIGHT_GENERIC is not set CONFIG_BACKLIGHT_PWM=y CONFIG_FRAMEBUFFER_CONSOLE=y CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y From 717c4c8336486781630893508b3347ae18953fae Mon Sep 17 00:00:00 2001 From: Andrey Zhizhikin Date: Tue, 1 Dec 2020 22:29:19 +0000 Subject: [PATCH 759/799] arm64: defconfig: drop unused BACKLIGHT_GENERIC option Commit 7ecdea4a0226 ("backlight: generic_bl: Remove this driver as it is unused") removed geenric_bl driver from the tree, together with corresponding config option. Remove BACKLIGHT_GENERIC config item from arm64 configuration. Fixes: 7ecdea4a0226 ("backlight: generic_bl: Remove this driver as it is unused") Signed-off-by: Andrey Zhizhikin Reviewed-by: Krzysztof Kozlowski Acked-by: Daniel Thompson Acked-by: Sam Ravnborg Cc: Sam Ravnborg Link: https://lore.kernel.org/r/20201201222922.3183-3-andrey.zhizhikin@leica-geosystems.com' Signed-off-by: Arnd Bergmann --- arch/arm64/configs/defconfig | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 98e15de04c5d..6493079e2c54 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -698,7 +698,6 @@ CONFIG_DRM_PANFROST=m CONFIG_FB=y CONFIG_FB_MODE_HELPERS=y CONFIG_FB_EFI=y -CONFIG_BACKLIGHT_GENERIC=m CONFIG_BACKLIGHT_PWM=m CONFIG_BACKLIGHT_LP855X=m CONFIG_LOGO=y From 7704b100719cf0fead976a1bc839c60ee552d045 Mon Sep 17 00:00:00 2001 From: Christian Hewitt Date: Tue, 1 Dec 2020 06:21:35 +0000 Subject: [PATCH 760/799] arm64: dts: meson: add i2c3/rtc nodes and vrtc alias to GT-King/GT-King-Pro The GT-King and GT-King-Pro boxes have an RTC chip and power cell, so enable it. GTKING:~ # dmesg | grep rtc [ 5.237245] meson-vrtc ff8000a8.rtc: registered as rtc1 [ 5.261869] rtc-hym8563 0-0051: registered as rtc0 [ 5.265016] rtc-hym8563 0-0051: setting system clock to 2020-11-30T09:16:54 UTC (1606727814) Signed-off-by: Christian Hewitt Signed-off-by: Kevin Hilman Link: https://lore.kernel.org/r/20201201062135.18241-1-christianshewitt@gmail.com --- .../boot/dts/amlogic/meson-g12b-gtking-pro.dts | 17 +++++++++++++++++ .../boot/dts/amlogic/meson-g12b-gtking.dts | 18 ++++++++++++++++++ 2 files changed, 35 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-gtking-pro.dts b/arch/arm64/boot/dts/amlogic/meson-g12b-gtking-pro.dts index f0c56a16af3d..0e5c500fb78f 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12b-gtking-pro.dts +++ b/arch/arm64/boot/dts/amlogic/meson-g12b-gtking-pro.dts @@ -14,6 +14,11 @@ compatible = "azw,gtking", "amlogic,g12b"; model = "Beelink GT-King Pro"; + aliases { + rtc0 = &rtc; + rtc1 = &vrtc; + }; + gpio-keys-polled { compatible = "gpio-keys-polled"; #address-cells = <1>; @@ -112,6 +117,18 @@ status = "okay"; }; +&i2c3 { + status = "okay"; + pinctrl-0 = <&i2c3_sda_a_pins>, <&i2c3_sck_a_pins>; + pinctrl-names = "default"; + + rtc: rtc@51 { + compatible = "nxp,pcf8563"; + reg = <0x51>; + wakeup-source; + }; +}; + &tdmif_b { status = "okay"; }; diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-gtking.dts b/arch/arm64/boot/dts/amlogic/meson-g12b-gtking.dts index eeb7bc5539ef..10b87eb97b14 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12b-gtking.dts +++ b/arch/arm64/boot/dts/amlogic/meson-g12b-gtking.dts @@ -14,6 +14,11 @@ compatible = "azw,gtking", "amlogic,g12b"; model = "Beelink GT-King"; + aliases { + rtc0 = &rtc; + rtc1 = &vrtc; + }; + spdif_dit: audio-codec-1 { #sound-dai-cells = <0>; compatible = "linux,spdif-dit"; @@ -122,6 +127,19 @@ status = "okay"; }; + +&i2c3 { + status = "okay"; + pinctrl-0 = <&i2c3_sda_a_pins>, <&i2c3_sck_a_pins>; + pinctrl-names = "default"; + + rtc: rtc@51 { + compatible = "nxp,pcf8563"; + reg = <0x51>; + wakeup-source; + }; +}; + &spdifout { pinctrl-0 = <&spdif_out_h_pins>; pinctrl-names = "default"; From e5dddbedfe09df69ca819eb98f6dcccb006c6bc9 Mon Sep 17 00:00:00 2001 From: Alexandru Ardelean Date: Fri, 27 Nov 2020 13:14:20 +0200 Subject: [PATCH 761/799] dt-bindings: add ADP5585/ADP5589 entries to trivial-devices This change adds the device-tree entries for the Analog Devices ADP5585 and ADP5589 devices to the trivial devices list. Signed-off-by: Alexandru Ardelean Link: https://lore.kernel.org/r/20201127111420.96500-4-alexandru.ardelean@analog.com Signed-off-by: Rob Herring --- Documentation/devicetree/bindings/trivial-devices.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/trivial-devices.yaml b/Documentation/devicetree/bindings/trivial-devices.yaml index ab623ba930d5..4096802499a7 100644 --- a/Documentation/devicetree/bindings/trivial-devices.yaml +++ b/Documentation/devicetree/bindings/trivial-devices.yaml @@ -30,6 +30,12 @@ properties: - ad,ad7414 # ADM9240: Complete System Hardware Monitor for uProcessor-Based Systems - ad,adm9240 + # Analog Devices ADP5585 Keypad Decoder and I/O Expansion + - adi,adp5585 + # Analog Devices ADP5585 Keypad Decoder and I/O Expansion with support for Row5 + - adi,adp5585-02 + # Analog Devices ADP5589 Keypad Decoder and I/O Expansion + - adi,adp5589 # +/-1C TDM Extended Temp Range I.C - adi,adt7461 # +/-1C TDM Extended Temp Range I.C From 58d91ac9da06ea1d6da7085e6d273870784e146b Mon Sep 17 00:00:00 2001 From: Andrey Zhizhikin Date: Tue, 1 Dec 2020 22:29:21 +0000 Subject: [PATCH 762/799] parisc: configs: drop unused BACKLIGHT_GENERIC option Commit 7ecdea4a0226 ("backlight: generic_bl: Remove this driver as it is unused") removed geenric_bl driver from the tree, together with corresponding config option. Remove BACKLIGHT_GENERIC config item from generic-64bit_defconfig. Fixes: 7ecdea4a0226 ("backlight: generic_bl: Remove this driver as it is unused") Signed-off-by: Andrey Zhizhikin Reviewed-by: Krzysztof Kozlowski Acked-by: Daniel Thompson Acked-by: Sam Ravnborg Cc: Sam Ravnborg Link: https://lore.kernel.org/r/20201201222922.3183-5-andrey.zhizhikin@leica-geosystems.com' Signed-off-by: Arnd Bergmann --- arch/parisc/configs/generic-64bit_defconfig | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/parisc/configs/generic-64bit_defconfig b/arch/parisc/configs/generic-64bit_defconfig index 7e2d7026285e..8f81fcbf04c4 100644 --- a/arch/parisc/configs/generic-64bit_defconfig +++ b/arch/parisc/configs/generic-64bit_defconfig @@ -191,7 +191,6 @@ CONFIG_DRM=y CONFIG_DRM_RADEON=y CONFIG_FIRMWARE_EDID=y CONFIG_FB_MODE_HELPERS=y -# CONFIG_BACKLIGHT_GENERIC is not set CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y CONFIG_HIDRAW=y CONFIG_HID_PID=y From acf689134a66cc9c85e571d33b6bd5d72e4078cf Mon Sep 17 00:00:00 2001 From: Andrey Zhizhikin Date: Tue, 1 Dec 2020 22:29:22 +0000 Subject: [PATCH 763/799] powerpc/configs: drop unused BACKLIGHT_GENERIC option Commit 7ecdea4a0226 ("backlight: generic_bl: Remove this driver as it is unused") removed geenric_bl driver from the tree, together with corresponding config option. Remove BACKLIGHT_GENERIC config item from generic-64bit_defconfig. Fixes: 7ecdea4a0226 ("backlight: generic_bl: Remove this driver as it is unused") Signed-off-by: Andrey Zhizhikin Reviewed-by: Krzysztof Kozlowski Acked-by: Daniel Thompson Acked-by: Sam Ravnborg Acked-by: Michael Ellerman Cc: Sam Ravnborg Link: https://lore.kernel.org/r/20201201222922.3183-6-andrey.zhizhikin@leica-geosystems.com' Signed-off-by: Arnd Bergmann --- arch/powerpc/configs/powernv_defconfig | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/powerpc/configs/powernv_defconfig b/arch/powerpc/configs/powernv_defconfig index cf30fc24413b..60a30fffeda0 100644 --- a/arch/powerpc/configs/powernv_defconfig +++ b/arch/powerpc/configs/powernv_defconfig @@ -208,7 +208,6 @@ CONFIG_FB_MATROX_G=y CONFIG_FB_RADEON=m CONFIG_FB_IBM_GXT4500=m CONFIG_LCD_PLATFORM=m -CONFIG_BACKLIGHT_GENERIC=m # CONFIG_VGA_CONSOLE is not set CONFIG_LOGO=y CONFIG_HID_A4TECH=m From 9c8421e298d6efff38bbd7a6f97b081bd43b2137 Mon Sep 17 00:00:00 2001 From: Jonathan Cameron Date: Sat, 28 Nov 2020 17:33:41 +0000 Subject: [PATCH 764/799] dt-bindings:i2c:i2c-gate: txt to yaml conversion This file provides very little in the way of actual schema but does provide a convenient intro to what an i2c-gate node actually represents. Signed-off-by: Jonathan Cameron Cc: Peter Rosin Cc: Wolfram Sang Link: https://lore.kernel.org/r/20201031181801.742585-2-jic23@kernel.org Link: https://lore.kernel.org/r/20201128173343.390165-2-jic23@kernel.org Signed-off-by: Rob Herring --- .../devicetree/bindings/i2c/i2c-gate.txt | 41 ------------------- .../devicetree/bindings/i2c/i2c-gate.yaml | 39 ++++++++++++++++++ 2 files changed, 39 insertions(+), 41 deletions(-) delete mode 100644 Documentation/devicetree/bindings/i2c/i2c-gate.txt create mode 100644 Documentation/devicetree/bindings/i2c/i2c-gate.yaml diff --git a/Documentation/devicetree/bindings/i2c/i2c-gate.txt b/Documentation/devicetree/bindings/i2c/i2c-gate.txt deleted file mode 100644 index 1846d236e656..000000000000 --- a/Documentation/devicetree/bindings/i2c/i2c-gate.txt +++ /dev/null @@ -1,41 +0,0 @@ -An i2c gate is useful to e.g. reduce the digital noise for RF tuners connected -to the i2c bus. Gates are similar to arbitrators in that you need to perform -some kind of operation to access the i2c bus past the arbitrator/gate, but -there are no competing masters to consider for gates and therefore there is -no arbitration happening for gates. - -Common i2c gate properties. - -- i2c-gate child node - -Required properties for the i2c-gate child node: -- #address-cells = <1>; -- #size-cells = <0>; - -Optional properties for i2c-gate child node: -- Child nodes conforming to i2c bus binding - - -Example : - - /* - An Invensense mpu9150 at address 0x68 featuring an on-chip Asahi - Kasei ak8975 compass behind a gate. - */ - - mpu9150@68 { - compatible = "invensense,mpu9150"; - reg = <0x68>; - interrupt-parent = <&gpio1>; - interrupts = <18 1>; - - i2c-gate { - #address-cells = <1>; - #size-cells = <0>; - - ax8975@c { - compatible = "ak,ak8975"; - reg = <0x0c>; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/i2c/i2c-gate.yaml b/Documentation/devicetree/bindings/i2c/i2c-gate.yaml new file mode 100644 index 000000000000..66472f12a7e2 --- /dev/null +++ b/Documentation/devicetree/bindings/i2c/i2c-gate.yaml @@ -0,0 +1,39 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/i2c/i2c-gate.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Common i2c gate properties + +maintainers: + - Peter Rosin + +description: | + An i2c gate is useful to e.g. reduce the digital noise for RF tuners connected + to the i2c bus. Gates are similar to arbitrators in that you need to perform + some kind of operation to access the i2c bus past the arbitrator/gate, but + there are no competing masters to consider for gates and therefore there is + no arbitration happening for gates. + +allOf: + - $ref: /schemas/i2c/i2c-controller.yaml + +properties: + $nodename: + const: i2c-gate + +additionalProperties: true + +examples: + - | + i2c-gate { + #address-cells = <1>; + #size-cells = <0>; + ak8975@c { + compatible = "ak,ak8975"; + reg = <0x0c>; + }; + }; +... + From 23ab93a1480002fd289071e08f7b4960fdfa76d8 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 26 Nov 2020 14:25:00 +0100 Subject: [PATCH 765/799] ARM: zynq: Fix compatible string for adi,adxl345 chip The commit e359a29225dd ("dt-bindings: iio: accel: adxl345: switch to YAML bindings") switched binding to yaml and the following error pop up: ../zynq-zturn-v5.dt.yaml: accelerometer@53: compatible: 'oneOf' conditional failed, one must be fixed: ['adi,adxl345', 'adxl345', 'adi,adxl34x', 'adxl34x'] is too long Additional items are not allowed ('adi,adxl34x', 'adxl34x' were unexpected) Additional items are not allowed ('adxl345', 'adi,adxl34x', 'adxl34x' were unexpected) 'adi,adxl346' was expected 'adi,adxl345' was expected Use only one compatible string to be aligned with the binding. Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/a9075ab54df13461380e46d3002302d3672325b5.1606397101.git.michal.simek@xilinx.com --- arch/arm/boot/dts/zynq-zturn-common.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/zynq-zturn-common.dtsi b/arch/arm/boot/dts/zynq-zturn-common.dtsi index 84f3c85c5bab..bf5d1c4568b0 100644 --- a/arch/arm/boot/dts/zynq-zturn-common.dtsi +++ b/arch/arm/boot/dts/zynq-zturn-common.dtsi @@ -104,7 +104,7 @@ }; accelerometer@53 { - compatible = "adi,adxl345", "adxl345", "adi,adxl34x", "adxl34x"; + compatible = "adi,adxl345"; reg = <0x53>; interrupt-parent = <&intc>; interrupts = <0x0 0x1e 0x4>; From 3880c39a80abf6bbbebafa58e69f830bdac1ab3a Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 26 Nov 2020 14:25:01 +0100 Subject: [PATCH 766/799] ARM: zynq: Rename bus to be align with simple-bus yaml Rename amba to AXI. Based on Xilinx Zynq TRM (Chapter 5) chip is "AXI point-to-point channels for communicating addresses, data, and response transactions between master and slave clients. This ARM AMBA 3.0..." Issues are reported as: .. amba: $nodename:0: 'amba' does not match '^([a-z][a-z0-9\\-]+-bus|bus|soc|axi|ahb|apb)(@[0-9a-f]+)?$' >From schema: ../github.com/devicetree-org/dt-schema/dtschema/schemas/simple-bus.yaml Similar change has been done for Xilinx ZynqMP SoC. Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/8a4bc80debfbb79c296e76fc1e4c173e62657286.1606397101.git.michal.simek@xilinx.com --- arch/arm/boot/dts/zynq-7000.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/zynq-7000.dtsi b/arch/arm/boot/dts/zynq-7000.dtsi index db3899b07992..df9ad831cf05 100644 --- a/arch/arm/boot/dts/zynq-7000.dtsi +++ b/arch/arm/boot/dts/zynq-7000.dtsi @@ -92,7 +92,7 @@ }; }; - amba: amba { + amba: axi { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; From 38d1985fdfcf20dc246b552580479ae602f735d1 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 26 Nov 2020 14:25:02 +0100 Subject: [PATCH 767/799] ARM: zynq: Fix leds subnode name for zc702/zybo-z7 Fix the leds subnode names to match (^led-[0-9a-f]$|led). Similar change has been also done by commit 9a19a39ee48b ("arm64: dts: zynqmp: Fix leds subnode name for zcu100/ultra96 v1"). The patch is fixing these warnings: .../zynq-zc702.dt.yaml: leds: 'ds23' does not match any of the regexes: '(^led-[0-9a-f]$|led)', 'pinctrl-[0-9]+' >From schema: .../Documentation/devicetree/bindings/leds/leds-gpio.yaml .../zynq-zybo-z7.dt.yaml: gpio-leds: 'ld4' does not match any of the regexes: '(^led-[0-9a-f]$|led)', 'pinctrl-[0-9]+' >From schema: .../Documentation/devicetree/bindings/leds/leds-gpio.yaml Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/607a66783b129294364abf09a6fc8abd241ff4ee.1606397101.git.michal.simek@xilinx.com --- arch/arm/boot/dts/zynq-zc702.dts | 2 +- arch/arm/boot/dts/zynq-zybo-z7.dts | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/zynq-zc702.dts b/arch/arm/boot/dts/zynq-zc702.dts index 27cd6cb52f1b..10a7d0b8cf8b 100644 --- a/arch/arm/boot/dts/zynq-zc702.dts +++ b/arch/arm/boot/dts/zynq-zc702.dts @@ -49,7 +49,7 @@ leds { compatible = "gpio-leds"; - ds23 { + led-ds23 { label = "ds23"; gpios = <&gpio0 10 0>; linux,default-trigger = "heartbeat"; diff --git a/arch/arm/boot/dts/zynq-zybo-z7.dts b/arch/arm/boot/dts/zynq-zybo-z7.dts index 357b78a5c11b..7b87e10d3953 100644 --- a/arch/arm/boot/dts/zynq-zybo-z7.dts +++ b/arch/arm/boot/dts/zynq-zybo-z7.dts @@ -25,7 +25,7 @@ gpio-leds { compatible = "gpio-leds"; - ld4 { + led-ld4 { label = "zynq-zybo-z7:green:ld4"; gpios = <&gpio0 7 GPIO_ACTIVE_HIGH>; }; From 225c13237732bba4b6714b43a3c4fe803da3166c Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 26 Nov 2020 14:25:03 +0100 Subject: [PATCH 768/799] ARM: zynq: Fix OCM mapping to be aligned with binding on zc702 The commit f69629919942 ("dt-bindings: sram: Convert SRAM bindings to json-schema") converted binding to yaml and some missing required properties started to be reported. Align binding based on it. The patch is fixing these warnings: .../zynq-zc702.dt.yaml: sram@fffc0000: '#address-cells' is a required property .../zynq-zc702.dt.yaml: sram@fffc0000: '#size-cells' is a required property .../zynq-zc702.dt.yaml: sram@fffc0000: 'ranges' is a required property >From schema: .../Documentation/devicetree/bindings/sram/sram.yaml Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/87c02786ccd8d7827827a9d95a8737bb300caeb0.1606397101.git.michal.simek@xilinx.com --- arch/arm/boot/dts/zynq-zc702.dts | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/boot/dts/zynq-zc702.dts b/arch/arm/boot/dts/zynq-zc702.dts index 10a7d0b8cf8b..cf70aff26c66 100644 --- a/arch/arm/boot/dts/zynq-zc702.dts +++ b/arch/arm/boot/dts/zynq-zc702.dts @@ -66,6 +66,12 @@ ocm: sram@fffc0000 { compatible = "mmio-sram"; reg = <0xfffc0000 0x10000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0xfffc0000 0x10000>; + ocm-sram@0 { + reg = <0x0 0x10000>; + }; }; }; From 536fada0cc72c6eb6082bbfbbd90127e8ab9b40c Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 26 Nov 2020 14:25:04 +0100 Subject: [PATCH 769/799] ARM: zynq: Convert at25 binding to new description on zc770-xm013 The commit f8f79fa6bb25 ("dt-bindings: at25: convert the binding document to yaml") converted binding to yaml and 3 deprecated properties pop up. The patch is fixing these warnings: .../zynq-zc770-xm013.dt.yaml: eeprom@2: 'pagesize' is a required property .../zynq-zc770-xm013.dt.yaml: eeprom@2: 'size' is a required property .../zynq-zc770-xm013.dt.yaml: eeprom@2: 'address-width' is a required property >From schema: .../Documentation/devicetree/bindings/eeprom/at25.yaml by converting them to new binding. Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/be2c1125d98386033e182012eb08986924707a76.1606397101.git.michal.simek@xilinx.com --- arch/arm/boot/dts/zynq-zc770-xm013.dts | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/zynq-zc770-xm013.dts b/arch/arm/boot/dts/zynq-zc770-xm013.dts index 4ae2c85df3a0..38d96adc870c 100644 --- a/arch/arm/boot/dts/zynq-zc770-xm013.dts +++ b/arch/arm/boot/dts/zynq-zc770-xm013.dts @@ -63,13 +63,12 @@ num-cs = <4>; is-decoded-cs = <0>; eeprom: eeprom@2 { - at25,byte-len = <8192>; - at25,addr-mode = <2>; - at25,page-size = <32>; - compatible = "atmel,at25"; reg = <2>; spi-max-frequency = <1000000>; + size = <8192>; + address-width = <16>; + pagesize = <32>; }; }; From a508f620b5a6e9b359a2baa46ec9a714c3e2f420 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 26 Nov 2020 15:05:02 +0100 Subject: [PATCH 770/799] ARM: zynq: Fix incorrect reference to XM013 instead of XM011 Fix comment about targeted extension card. It was likely just c&p error. Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/39e16e667aa8f132496092d4fa554935ddd5a55f.1606399500.git.michal.simek@xilinx.com --- arch/arm/boot/dts/zynq-zc770-xm011.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/zynq-zc770-xm011.dts b/arch/arm/boot/dts/zynq-zc770-xm011.dts index b7f65862c022..56732e8f6ca1 100644 --- a/arch/arm/boot/dts/zynq-zc770-xm011.dts +++ b/arch/arm/boot/dts/zynq-zc770-xm011.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Xilinx ZC770 XM013 board DTS + * Xilinx ZC770 XM011 board DTS * * Copyright (C) 2013-2018 Xilinx, Inc. */ From dcb11100cd5d3f5a191b7fba75422e3df792f3ff Mon Sep 17 00:00:00 2001 From: Kevin Hilman Date: Mon, 7 Dec 2020 15:01:56 -0800 Subject: [PATCH 771/799] arm64: Kconfig: meson: drop pinctrl Don't automatically select pinctrl drivers, leave it up to defaults in drivers/pinctrl/meson, which default to built-in, but are also now optionally configurable as modules as of commit 9c65441ec823 ("pinctrl/meson: enable building as modules") Signed-off-by: Kevin Hilman Reviewed-by: Jerome Brunet Link: https://lore.kernel.org/r/20201207230156.10198-1-khilman@baylibre.com' Signed-off-by: Arnd Bergmann --- arch/arm64/Kconfig.platforms | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms index a75513b4ce6b..d8a4c4a9292c 100644 --- a/arch/arm64/Kconfig.platforms +++ b/arch/arm64/Kconfig.platforms @@ -152,8 +152,6 @@ config ARCH_MEDIATEK config ARCH_MESON bool "Amlogic Platforms" - select PINCTRL - select PINCTRL_MESON select MESON_IRQ_GPIO help This enables support for the arm64 based Amlogic SoCs From 74530d645126c2934b16db135edaef16eff9e35b Mon Sep 17 00:00:00 2001 From: Daniel Palmer Date: Sun, 29 Nov 2020 20:08:01 +0900 Subject: [PATCH 772/799] ARM: mstar: Add gpio controller to MStar base dtsi The GPIO controller is at the same address in all of the currently known chips so create a node for it in the base dtsi. Some extra properties are needed to actually use it so disable it by default. Signed-off-by: Daniel Palmer Acked-by: Linus Walleij Link: https://lore.kernel.org/r/20201129110803.2461700-5-daniel@0x0f.com' Signed-off-by: Arnd Bergmann --- arch/arm/boot/dts/mstar-v7.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm/boot/dts/mstar-v7.dtsi b/arch/arm/boot/dts/mstar-v7.dtsi index f07880561e11..81369bc07f78 100644 --- a/arch/arm/boot/dts/mstar-v7.dtsi +++ b/arch/arm/boot/dts/mstar-v7.dtsi @@ -109,6 +109,16 @@ reg = <0x204400 0x200>; }; + gpio: gpio@207800 { + #gpio-cells = <2>; + reg = <0x207800 0x200>; + gpio-controller; + #interrupt-cells = <2>; + interrupt-controller; + interrupt-parent = <&intc_fiq>; + status = "disabled"; + }; + pm_uart: uart@221000 { compatible = "ns16550a"; reg = <0x221000 0x100>; From 5b8a05b9e8d10c8df29bb719e73ea8ed916a1eea Mon Sep 17 00:00:00 2001 From: Daniel Palmer Date: Sun, 29 Nov 2020 20:08:02 +0900 Subject: [PATCH 773/799] ARM: mstar: Fill in GPIO controller properties for infinity Fill in the properties needed to use the GPIO controller in the infinity and infinity3 chips. Signed-off-by: Daniel Palmer Acked-by: Linus Walleij Link: https://lore.kernel.org/r/20201129110803.2461700-6-daniel@0x0f.com' Signed-off-by: Arnd Bergmann --- arch/arm/boot/dts/mstar-infinity.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/boot/dts/mstar-infinity.dtsi b/arch/arm/boot/dts/mstar-infinity.dtsi index cd911adef014..0bee517797f4 100644 --- a/arch/arm/boot/dts/mstar-infinity.dtsi +++ b/arch/arm/boot/dts/mstar-infinity.dtsi @@ -6,6 +6,13 @@ #include "mstar-v7.dtsi" +#include + &imi { reg = <0xa0000000 0x16000>; }; + +&gpio { + compatible = "mstar,msc313-gpio"; + status = "okay"; +}; From 80e73332ee829cd55d86272b7d3d4d5f0fc4c4ff Mon Sep 17 00:00:00 2001 From: Daniel Palmer Date: Tue, 1 Dec 2020 22:43:21 +0900 Subject: [PATCH 774/799] dt-bindings: mstar: Add binding details for mstar,smpctrl This adds a YAML description of the smpctrl node needed by the platform code for the MStar/SigmaStar Armv7 SoCs to boot secondary cpus. Signed-off-by: Daniel Palmer Link: https://lore.kernel.org/r/20201201134330.3037007-2-daniel@0x0f.com' Signed-off-by: Arnd Bergmann --- .../bindings/arm/mstar/mstar,smpctrl.yaml | 40 +++++++++++++++++++ 1 file changed, 40 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/mstar/mstar,smpctrl.yaml diff --git a/Documentation/devicetree/bindings/arm/mstar/mstar,smpctrl.yaml b/Documentation/devicetree/bindings/arm/mstar/mstar,smpctrl.yaml new file mode 100644 index 000000000000..599c65980f5d --- /dev/null +++ b/Documentation/devicetree/bindings/arm/mstar/mstar,smpctrl.yaml @@ -0,0 +1,40 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +# Copyright 2020 thingy.jp. +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/arm/mstar/mstar,smpctrl.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: MStar/SigmaStar Armv7 SoC SMP control registers + +maintainers: + - Daniel Palmer + +description: | + MStar/SigmaStar's Armv7 SoCs that have more than one processor + have a region of registers that allow setting the boot address + and a magic number that allows secondary processors to leave + the loop they are parked in by the boot ROM. + +properties: + compatible: + items: + - enum: + - sstar,ssd201-smpctrl # SSD201/SSD202D + - const: mstar,smpctrl + + reg: + maxItems: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + smpctrl@204000 { + compatible = "sstar,ssd201-smpctrl", "mstar,smpctrl"; + reg = <0x204000 0x200>; + }; From 43181b5d8072dd92513dca995789a1a1123ffc8a Mon Sep 17 00:00:00 2001 From: Daniel Palmer Date: Tue, 1 Dec 2020 22:43:22 +0900 Subject: [PATCH 775/799] dt-bindings: vendor-prefixes: Add honestar vendor prefix Add prefix for Honestar Technologies Co., Ltd. Signed-off-by: Daniel Palmer Link: https://lore.kernel.org/r/20201201134330.3037007-3-daniel@0x0f.com' Signed-off-by: Arnd Bergmann --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index 93b30c51f0eb..058b904c3f88 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -461,6 +461,8 @@ patternProperties: description: Holt Integrated Circuits, Inc. "^honeywell,.*": description: Honeywell + "^honestar,.*": + description: Honestar Technologies Co., Ltd. "^hoperun,.*": description: Jiangsu HopeRun Software Co., Ltd. "^hp,.*": From 8c50a8b359c4f262a05ed5fb05373177d11bd20c Mon Sep 17 00:00:00 2001 From: Daniel Palmer Date: Tue, 1 Dec 2020 22:43:23 +0900 Subject: [PATCH 776/799] dt-bindings: mstar: Add Honestar SSD201_HT_V2 to mstar boards The Honestar SSD201_HT_V2 is a full size devkit for the SigmaStar SSD201 or SSD202D (they are pin compatible). Currently only the SSD202D version is supported as that's the one I have. Signed-off-by: Daniel Palmer Reviewed-by: Rob Herring Link: https://linux-chenxing.org/infinity2/ssd201_ht_v2/ Link: https://lore.kernel.org/r/20201201134330.3037007-4-daniel@0x0f.com' Signed-off-by: Arnd Bergmann --- Documentation/devicetree/bindings/arm/mstar/mstar.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/mstar/mstar.yaml b/Documentation/devicetree/bindings/arm/mstar/mstar.yaml index 7c787405bb2f..61d08c473eb8 100644 --- a/Documentation/devicetree/bindings/arm/mstar/mstar.yaml +++ b/Documentation/devicetree/bindings/arm/mstar/mstar.yaml @@ -20,6 +20,12 @@ properties: - thingyjp,breadbee-crust # thingy.jp BreadBee Crust - const: mstar,infinity + - description: infinity2m boards + items: + - enum: + - honestar,ssd201htv2 # Honestar SSD201_HT_V2 devkit + - const: mstar,infinity2m + - description: infinity3 boards items: - enum: From ba2290b1b7505b28912092a0976e071a447ee18c Mon Sep 17 00:00:00 2001 From: Daniel Palmer Date: Tue, 1 Dec 2020 22:43:24 +0900 Subject: [PATCH 777/799] ARM: mstar: Add infinity2m support The infinity2m series of chips are like the other Mstar/Sigmastar chips in that they have a Cortex A7 system with DDR memory integrated in a single package. The infinity2m chips are intended for recording the incoming streams from IP cameras. So instead of video encoders they have video decoders, instead of a camera interface they have display hardware and so on. Aside from the above points the big difference about these chips is that they include a second Cortex A7 core. Signed-off-by: Daniel Palmer Link: https://lore.kernel.org/r/20201201134330.3037007-5-daniel@0x0f.com' Signed-off-by: Arnd Bergmann --- arch/arm/boot/dts/mstar-infinity2m.dtsi | 15 +++++++++++++++ arch/arm/boot/dts/mstar-v7.dtsi | 2 +- arch/arm/mach-mstar/mstarv7.c | 1 + 3 files changed, 17 insertions(+), 1 deletion(-) create mode 100644 arch/arm/boot/dts/mstar-infinity2m.dtsi diff --git a/arch/arm/boot/dts/mstar-infinity2m.dtsi b/arch/arm/boot/dts/mstar-infinity2m.dtsi new file mode 100644 index 000000000000..02adb9fe9d3c --- /dev/null +++ b/arch/arm/boot/dts/mstar-infinity2m.dtsi @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2020 thingy.jp. + * Author: Daniel Palmer + */ + +#include "mstar-infinity.dtsi" + +&cpus { + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x1>; + }; +}; diff --git a/arch/arm/boot/dts/mstar-v7.dtsi b/arch/arm/boot/dts/mstar-v7.dtsi index 81369bc07f78..b0a21b0b731f 100644 --- a/arch/arm/boot/dts/mstar-v7.dtsi +++ b/arch/arm/boot/dts/mstar-v7.dtsi @@ -12,7 +12,7 @@ #size-cells = <1>; interrupt-parent = <&gic>; - cpus { + cpus: cpus { #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/mach-mstar/mstarv7.c b/arch/arm/mach-mstar/mstarv7.c index 81a4cbcab206..1aa748fa006e 100644 --- a/arch/arm/mach-mstar/mstarv7.c +++ b/arch/arm/mach-mstar/mstarv7.c @@ -35,6 +35,7 @@ static void __iomem *l3bridge; static const char * const mstarv7_board_dt_compat[] __initconst = { "mstar,infinity", + "mstar,infinity2m", "mstar,infinity3", "mstar,mercury5", NULL, From 572ef97bc7341b45c721d79f98262c4adb25919c Mon Sep 17 00:00:00 2001 From: Daniel Palmer Date: Tue, 1 Dec 2020 22:43:25 +0900 Subject: [PATCH 778/799] ARM: mstar: Add common dtsi for SSD201/SSD202D The SSD201 and SSD202D are basically the same chip with a different DDR die packaged (64MB DDR2 or 128MB DDR3). This patch adds a shared dtsi for the common parts of these chips like gpio, pinctrl etc. Signed-off-by: Daniel Palmer Link: https://lore.kernel.org/r/20201201134330.3037007-6-daniel@0x0f.com' Signed-off-by: Arnd Bergmann --- arch/arm/boot/dts/mstar-infinity2m-ssd20xd.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) create mode 100644 arch/arm/boot/dts/mstar-infinity2m-ssd20xd.dtsi diff --git a/arch/arm/boot/dts/mstar-infinity2m-ssd20xd.dtsi b/arch/arm/boot/dts/mstar-infinity2m-ssd20xd.dtsi new file mode 100644 index 000000000000..0811220f0a79 --- /dev/null +++ b/arch/arm/boot/dts/mstar-infinity2m-ssd20xd.dtsi @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2020 thingy.jp. + * Author: Daniel Palmer + */ + +#include "mstar-infinity2m.dtsi" From dbbaf35d589e554d5956780282feb5d62d7f2af6 Mon Sep 17 00:00:00 2001 From: Daniel Palmer Date: Tue, 1 Dec 2020 22:43:26 +0900 Subject: [PATCH 779/799] ARM: mstar: Add chip level dtsi for SSD202D Add a chip level dtsi for the SigmaStar SSD202D Signed-off-by: Daniel Palmer Link: https://lore.kernel.org/r/20201201134330.3037007-7-daniel@0x0f.com' Signed-off-by: Arnd Bergmann --- arch/arm/boot/dts/mstar-infinity2m-ssd202d.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) create mode 100644 arch/arm/boot/dts/mstar-infinity2m-ssd202d.dtsi diff --git a/arch/arm/boot/dts/mstar-infinity2m-ssd202d.dtsi b/arch/arm/boot/dts/mstar-infinity2m-ssd202d.dtsi new file mode 100644 index 000000000000..176e10a29896 --- /dev/null +++ b/arch/arm/boot/dts/mstar-infinity2m-ssd202d.dtsi @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2020 thingy.jp. + * Author: Daniel Palmer + */ + +#include "mstar-infinity2m-ssd20xd.dtsi" + +/ { + memory { + device_type = "memory"; + reg = <0x20000000 0x8000000>; + }; +}; From 418cb58b45661724ba145bd769e53910ad9324b0 Mon Sep 17 00:00:00 2001 From: Daniel Palmer Date: Tue, 1 Dec 2020 22:43:27 +0900 Subject: [PATCH 780/799] ARM: mstar: Add dts for Honestar ssd201htv2 Add a dts for the Honestar ssd201htv2 devkit. This is for the board populated with a SSD202D. Signed-off-by: Daniel Palmer Link: https://lore.kernel.org/r/20201201134330.3037007-8-daniel@0x0f.com' Signed-off-by: Arnd Bergmann --- arch/arm/boot/dts/Makefile | 1 + .../mstar-infinity2m-ssd202d-ssd201htv2.dts | 25 +++++++++++++++++++ 2 files changed, 26 insertions(+) create mode 100644 arch/arm/boot/dts/mstar-infinity2m-ssd202d-ssd201htv2.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index ef2be2390c75..9a6ffef1b651 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1394,6 +1394,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \ dtb-$(CONFIG_ARCH_MILBEAUT) += milbeaut-m10v-evb.dtb dtb-$(CONFIG_ARCH_MSTARV7) += \ mstar-infinity-msc313-breadbee_crust.dtb \ + mstar-infinity2m-ssd202d-ssd201htv2.dtb \ mstar-infinity3-msc313e-breadbee.dtb \ mstar-mercury5-ssc8336n-midrived08.dtb dtb-$(CONFIG_ARCH_ZX) += zx296702-ad1.dtb diff --git a/arch/arm/boot/dts/mstar-infinity2m-ssd202d-ssd201htv2.dts b/arch/arm/boot/dts/mstar-infinity2m-ssd202d-ssd201htv2.dts new file mode 100644 index 000000000000..5d81641414a2 --- /dev/null +++ b/arch/arm/boot/dts/mstar-infinity2m-ssd202d-ssd201htv2.dts @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2020 thingy.jp. + * Author: Daniel Palmer + */ + +/dts-v1/; +#include "mstar-infinity2m-ssd202d.dtsi" + +/ { + model = "SSD201_HT_V2"; + compatible = "honestar,ssd201htv2", "mstar,infinity2m"; + + aliases { + serial0 = &pm_uart; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&pm_uart { + status = "okay"; +}; From 570e471ce0540165aed5bc638e462de7c1110a28 Mon Sep 17 00:00:00 2001 From: Daniel Palmer Date: Tue, 1 Dec 2020 22:43:28 +0900 Subject: [PATCH 781/799] ARM: mstar: Add smp ctrl registers to infinity2m dtsi Add the smpctrl registers to the infinity2m dtsi so that the second CPU can be enabled on chips in this family. Signed-off-by: Daniel Palmer Link: https://lore.kernel.org/r/20201201134330.3037007-9-daniel@0x0f.com' Signed-off-by: Arnd Bergmann --- arch/arm/boot/dts/mstar-infinity2m.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/boot/dts/mstar-infinity2m.dtsi b/arch/arm/boot/dts/mstar-infinity2m.dtsi index 02adb9fe9d3c..6d4d1d224e96 100644 --- a/arch/arm/boot/dts/mstar-infinity2m.dtsi +++ b/arch/arm/boot/dts/mstar-infinity2m.dtsi @@ -13,3 +13,10 @@ reg = <0x1>; }; }; + +&riu { + smpctrl: smpctrl@204000 { + reg = <0x204000 0x200>; + status = "disabled"; + }; +}; From ecaafac1eb73de8209680ec030769a2def4801e5 Mon Sep 17 00:00:00 2001 From: Daniel Palmer Date: Tue, 1 Dec 2020 22:43:29 +0900 Subject: [PATCH 782/799] ARM: mstar: Wire up smpctrl for SSD201/SSD202D Add the specific compat string for the smpctrl registers to the SSD201/SSD202D common dtsi. Signed-off-by: Daniel Palmer Link: https://lore.kernel.org/r/20201201134330.3037007-10-daniel@0x0f.com' Signed-off-by: Arnd Bergmann --- arch/arm/boot/dts/mstar-infinity2m-ssd20xd.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/boot/dts/mstar-infinity2m-ssd20xd.dtsi b/arch/arm/boot/dts/mstar-infinity2m-ssd20xd.dtsi index 0811220f0a79..7a5e28b33f96 100644 --- a/arch/arm/boot/dts/mstar-infinity2m-ssd20xd.dtsi +++ b/arch/arm/boot/dts/mstar-infinity2m-ssd20xd.dtsi @@ -5,3 +5,8 @@ */ #include "mstar-infinity2m.dtsi" + +&smpctrl { + compatible = "sstar,ssd201-smpctrl", "mstar,smpctrl"; + status = "okay"; +}; From 5919eec0f09214901b09faeaf6341addebc57a89 Mon Sep 17 00:00:00 2001 From: Daniel Palmer Date: Tue, 1 Dec 2020 22:43:30 +0900 Subject: [PATCH 783/799] ARM: mstar: SMP support This patch adds SMP support for MStar/Sigmastar chips that have a second core like those in the infinity2m family. So far only single and dual core chips have been found so this does the bare minimum to boot the second core. From what I can tell not having the "holding pen" code to handle multiple cores is fine if there is only one core the will get booted. This might need to be reconsidered if chips with more cores turn up. Signed-off-by: Daniel Palmer Link: https://lore.kernel.org/r/20201201134330.3037007-11-daniel@0x0f.com' Signed-off-by: Arnd Bergmann --- arch/arm/mach-mstar/mstarv7.c | 48 +++++++++++++++++++++++++++++++++++ 1 file changed, 48 insertions(+) diff --git a/arch/arm/mach-mstar/mstarv7.c b/arch/arm/mach-mstar/mstarv7.c index 1aa748fa006e..274c4f0df270 100644 --- a/arch/arm/mach-mstar/mstarv7.c +++ b/arch/arm/mach-mstar/mstarv7.c @@ -31,6 +31,13 @@ #define MSTARV7_L3BRIDGE_FLUSH_TRIGGER BIT(0) #define MSTARV7_L3BRIDGE_STATUS_DONE BIT(12) +#ifdef CONFIG_SMP +#define MSTARV7_CPU1_BOOT_ADDR_HIGH 0x4c +#define MSTARV7_CPU1_BOOT_ADDR_LOW 0x50 +#define MSTARV7_CPU1_UNLOCK 0x58 +#define MSTARV7_CPU1_UNLOCK_MAGIC 0xbabe +#endif + static void __iomem *l3bridge; static const char * const mstarv7_board_dt_compat[] __initconst = { @@ -63,6 +70,46 @@ static void mstarv7_mb(void) } } +#ifdef CONFIG_SMP +static int mstarv7_boot_secondary(unsigned int cpu, struct task_struct *idle) +{ + struct device_node *np; + u32 bootaddr = (u32) __pa_symbol(secondary_startup_arm); + void __iomem *smpctrl; + + /* + * right now we don't know how to boot anything except + * cpu 1. + */ + if (cpu != 1) + return -EINVAL; + + np = of_find_compatible_node(NULL, NULL, "mstar,smpctrl"); + smpctrl = of_iomap(np, 0); + + if (!smpctrl) + return -ENODEV; + + /* set the boot address for the second cpu */ + writew(bootaddr & 0xffff, smpctrl + MSTARV7_CPU1_BOOT_ADDR_LOW); + writew((bootaddr >> 16) & 0xffff, smpctrl + MSTARV7_CPU1_BOOT_ADDR_HIGH); + + /* unlock the second cpu */ + writew(MSTARV7_CPU1_UNLOCK_MAGIC, smpctrl + MSTARV7_CPU1_UNLOCK); + + /* and away we go...*/ + arch_send_wakeup_ipi_mask(cpumask_of(cpu)); + + iounmap(smpctrl); + + return 0; +} + +static const struct smp_operations __initdata mstarv7_smp_ops = { + .smp_boot_secondary = mstarv7_boot_secondary, +}; +#endif + static void __init mstarv7_init(void) { struct device_node *np; @@ -78,4 +125,5 @@ static void __init mstarv7_init(void) DT_MACHINE_START(MSTARV7_DT, "MStar/Sigmastar Armv7 (Device Tree)") .dt_compat = mstarv7_board_dt_compat, .init_machine = mstarv7_init, + .smp = smp_ops(mstarv7_smp_ops), MACHINE_END From 675fc18900e9c4199ed51342be16b60eeac8c0b1 Mon Sep 17 00:00:00 2001 From: "xiao.ma" Date: Tue, 1 Dec 2020 21:26:10 -1000 Subject: [PATCH 784/799] dt-bindings: trivial-devices: Add delta,q54sj108a2 Add delta,q54sj108a2 to trivial-devices.yaml. Signed-off-by: xiao.ma Link: https://lore.kernel.org/r/20201202072610.1666-1-max701@126.com Signed-off-by: Rob Herring --- Documentation/devicetree/bindings/trivial-devices.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/trivial-devices.yaml b/Documentation/devicetree/bindings/trivial-devices.yaml index 4096802499a7..a338f9ca8440 100644 --- a/Documentation/devicetree/bindings/trivial-devices.yaml +++ b/Documentation/devicetree/bindings/trivial-devices.yaml @@ -66,6 +66,8 @@ properties: - dallas,ds4510 # Digital Thermometer and Thermostat - dallas,ds75 + # 1/4 Brick DC/DC Regulated Power Module + - delta,q54sj108a2 # Devantech SRF02 ultrasonic ranger in I2C mode - devantech,srf02 # Devantech SRF08 ultrasonic ranger From 8f7e68bb3d4c482faa223ffa3838f7d39129afec Mon Sep 17 00:00:00 2001 From: Fabrice Gasnier Date: Wed, 2 Dec 2020 13:45:14 +0100 Subject: [PATCH 785/799] dt-bindings: mfd: fix stm32 timers example The stm32 timers example name should match the pattern timer@. Also, the example is based on stm32mp1 timer 2, so the identifier should be '1' instead of '0' (e.g. timer 1). Fixes: bfbcbf88f9db ("dt-bindings: timer: Convert stm32 timer bindings to json-schema") Signed-off-by: Fabrice Gasnier Link: https://lore.kernel.org/r/1606913114-25693-1-git-send-email-fabrice.gasnier@foss.st.com Signed-off-by: Rob Herring --- Documentation/devicetree/bindings/mfd/st,stm32-timers.yaml | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/mfd/st,stm32-timers.yaml b/Documentation/devicetree/bindings/mfd/st,stm32-timers.yaml index f212fc6e1661..0f16c8864a87 100644 --- a/Documentation/devicetree/bindings/mfd/st,stm32-timers.yaml +++ b/Documentation/devicetree/bindings/mfd/st,stm32-timers.yaml @@ -131,7 +131,7 @@ additionalProperties: false examples: - | #include - timers2: timers@40000000 { + timers2: timer@40000000 { #address-cells = <1>; #size-cells = <0>; compatible = "st,stm32-timers"; @@ -149,9 +149,9 @@ examples: #pwm-cells = <3>; st,breakinput = <0 1 5>; }; - timer@0 { + timer@1 { compatible = "st,stm32-timer-trigger"; - reg = <0>; + reg = <1>; }; counter { compatible = "st,stm32-timer-counter"; From 2bf39ddd77937ab2123bbf186e44f484610536d9 Mon Sep 17 00:00:00 2001 From: Daniel Palmer Date: Sun, 29 Nov 2020 20:07:58 +0900 Subject: [PATCH 786/799] dt-bindings: gpio: Add a binding header for the MSC313 GPIO driver Header adds defines for the gpio number of each pad from the driver view. The gpio block seems to have enough registers for 128 lines but what line is mapped to a physical pin depends on the chip. The gpio block also seems to contain some registers that are not related to gpio but needed somewhere to go. Because of the above the driver itself uses the index of a pin's offset in an array of the possible offsets for a chip as the gpio number. Signed-off-by: Daniel Palmer Reviewed-by: Rob Herring Signed-off-by: Arnd Bergmann --- MAINTAINERS | 1 + include/dt-bindings/gpio/msc313-gpio.h | 53 ++++++++++++++++++++++++++ 2 files changed, 54 insertions(+) create mode 100644 include/dt-bindings/gpio/msc313-gpio.h diff --git a/MAINTAINERS b/MAINTAINERS index ae78b54d4a4f..8805b484e436 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2133,6 +2133,7 @@ W: http://linux-chenxing.org/ F: Documentation/devicetree/bindings/arm/mstar/* F: arch/arm/boot/dts/mstar-* F: arch/arm/mach-mstar/ +F: include/dt-bindings/gpio/msc313-gpio.h ARM/NEC MOBILEPRO 900/c MACHINE SUPPORT M: Michael Petchkovsky diff --git a/include/dt-bindings/gpio/msc313-gpio.h b/include/dt-bindings/gpio/msc313-gpio.h new file mode 100644 index 000000000000..2dd56683d3c1 --- /dev/null +++ b/include/dt-bindings/gpio/msc313-gpio.h @@ -0,0 +1,53 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ +/* + * GPIO definitions for MStar/SigmaStar MSC313 and later SoCs + * + * Copyright (C) 2020 Daniel Palmer + */ + +#ifndef _DT_BINDINGS_MSC313_GPIO_H +#define _DT_BINDINGS_MSC313_GPIO_H + +#define MSC313_GPIO_FUART 0 +#define MSC313_GPIO_FUART_RX (MSC313_GPIO_FUART + 0) +#define MSC313_GPIO_FUART_TX (MSC313_GPIO_FUART + 1) +#define MSC313_GPIO_FUART_CTS (MSC313_GPIO_FUART + 2) +#define MSC313_GPIO_FUART_RTS (MSC313_GPIO_FUART + 3) + +#define MSC313_GPIO_SR (MSC313_GPIO_FUART_RTS + 1) +#define MSC313_GPIO_SR_IO2 (MSC313_GPIO_SR + 0) +#define MSC313_GPIO_SR_IO3 (MSC313_GPIO_SR + 1) +#define MSC313_GPIO_SR_IO4 (MSC313_GPIO_SR + 2) +#define MSC313_GPIO_SR_IO5 (MSC313_GPIO_SR + 3) +#define MSC313_GPIO_SR_IO6 (MSC313_GPIO_SR + 4) +#define MSC313_GPIO_SR_IO7 (MSC313_GPIO_SR + 5) +#define MSC313_GPIO_SR_IO8 (MSC313_GPIO_SR + 6) +#define MSC313_GPIO_SR_IO9 (MSC313_GPIO_SR + 7) +#define MSC313_GPIO_SR_IO10 (MSC313_GPIO_SR + 8) +#define MSC313_GPIO_SR_IO11 (MSC313_GPIO_SR + 9) +#define MSC313_GPIO_SR_IO12 (MSC313_GPIO_SR + 10) +#define MSC313_GPIO_SR_IO13 (MSC313_GPIO_SR + 11) +#define MSC313_GPIO_SR_IO14 (MSC313_GPIO_SR + 12) +#define MSC313_GPIO_SR_IO15 (MSC313_GPIO_SR + 13) +#define MSC313_GPIO_SR_IO16 (MSC313_GPIO_SR + 14) +#define MSC313_GPIO_SR_IO17 (MSC313_GPIO_SR + 15) + +#define MSC313_GPIO_SD (MSC313_GPIO_SR_IO17 + 1) +#define MSC313_GPIO_SD_CLK (MSC313_GPIO_SD + 0) +#define MSC313_GPIO_SD_CMD (MSC313_GPIO_SD + 1) +#define MSC313_GPIO_SD_D0 (MSC313_GPIO_SD + 2) +#define MSC313_GPIO_SD_D1 (MSC313_GPIO_SD + 3) +#define MSC313_GPIO_SD_D2 (MSC313_GPIO_SD + 4) +#define MSC313_GPIO_SD_D3 (MSC313_GPIO_SD + 5) + +#define MSC313_GPIO_I2C1 (MSC313_GPIO_SD_D3 + 1) +#define MSC313_GPIO_I2C1_SCL (MSC313_GPIO_I2C1 + 0) +#define MSC313_GPIO_I2C1_SDA (MSC313_GPIO_I2C1 + 1) + +#define MSC313_GPIO_SPI0 (MSC313_GPIO_I2C1_SDA + 1) +#define MSC313_GPIO_SPI0_CZ (MSC313_GPIO_SPI0 + 0) +#define MSC313_GPIO_SPI0_CK (MSC313_GPIO_SPI0 + 1) +#define MSC313_GPIO_SPI0_DI (MSC313_GPIO_SPI0 + 2) +#define MSC313_GPIO_SPI0_DO (MSC313_GPIO_SPI0 + 3) + +#endif /* _DT_BINDINGS_MSC313_GPIO_H */ From 5ef399aa5c5f9c4c2ac9208d1f00e935f13012ce Mon Sep 17 00:00:00 2001 From: Lars Povlsen Date: Tue, 6 Oct 2020 22:03:16 +0200 Subject: [PATCH 787/799] arm64: dts: sparx5: Add reset support This adds reset support to the Sparx5 SoC DT. Signed-off-by: Lars Povlsen Link: https://lore.kernel.org/r/20201006200316.2261245-4-lars.povlsen@microchip.com --- arch/arm64/boot/dts/microchip/sparx5.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/microchip/sparx5.dtsi b/arch/arm64/boot/dts/microchip/sparx5.dtsi index 3cb01c39c3c8..1def30e6b728 100644 --- a/arch/arm64/boot/dts/microchip/sparx5.dtsi +++ b/arch/arm64/boot/dts/microchip/sparx5.dtsi @@ -135,6 +135,11 @@ }; }; + reset@611010008 { + compatible = "microchip,sparx5-chip-reset"; + reg = <0x6 0x11010008 0x4>; + }; + uart0: serial@600100000 { pinctrl-0 = <&uart_pins>; pinctrl-names = "default"; From 7e1f91cbfa0d330fad61c621389373cff81898fd Mon Sep 17 00:00:00 2001 From: Lars Povlsen Date: Fri, 13 Nov 2020 15:51:51 +0100 Subject: [PATCH 788/799] arm64: dts: sparx5: Add SGPIO devices This adds SGPIO devices for the Sparx5 SoC and configures it for the applicable reference boards. Signed-off-by: Lars Povlsen Reviewed-by: Linus Walleij Link: https://lore.kernel.org/r/20201113145151.68900-4-lars.povlsen@microchip.com --- arch/arm64/boot/dts/microchip/sparx5.dtsi | 91 ++++++ .../boot/dts/microchip/sparx5_pcb125.dts | 5 + .../dts/microchip/sparx5_pcb134_board.dtsi | 258 ++++++++++++++++++ .../dts/microchip/sparx5_pcb135_board.dtsi | 55 ++++ 4 files changed, 409 insertions(+) diff --git a/arch/arm64/boot/dts/microchip/sparx5.dtsi b/arch/arm64/boot/dts/microchip/sparx5.dtsi index 1def30e6b728..d64621d1213b 100644 --- a/arch/arm64/boot/dts/microchip/sparx5.dtsi +++ b/arch/arm64/boot/dts/microchip/sparx5.dtsi @@ -231,6 +231,22 @@ function = "si2"; }; + sgpio0_pins: sgpio-pins { + pins = "GPIO_0", "GPIO_1", "GPIO_2", "GPIO_3"; + function = "sg0"; + }; + + sgpio1_pins: sgpio1-pins { + pins = "GPIO_4", "GPIO_5", "GPIO_12", "GPIO_13"; + function = "sg1"; + }; + + sgpio2_pins: sgpio2-pins { + pins = "GPIO_30", "GPIO_31", "GPIO_32", + "GPIO_33"; + function = "sg2"; + }; + uart_pins: uart-pins { pins = "GPIO_10", "GPIO_11"; function = "uart"; @@ -261,6 +277,81 @@ }; }; + sgpio0: gpio@61101036c { + #address-cells = <1>; + #size-cells = <0>; + compatible = "microchip,sparx5-sgpio"; + status = "disabled"; + clocks = <&sys_clk>; + pinctrl-0 = <&sgpio0_pins>; + pinctrl-names = "default"; + reg = <0x6 0x1101036c 0x100>; + sgpio_in0: gpio@0 { + compatible = "microchip,sparx5-sgpio-bank"; + reg = <0>; + gpio-controller; + #gpio-cells = <3>; + ngpios = <96>; + }; + sgpio_out0: gpio@1 { + compatible = "microchip,sparx5-sgpio-bank"; + reg = <1>; + gpio-controller; + #gpio-cells = <3>; + ngpios = <96>; + }; + }; + + sgpio1: gpio@611010484 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "microchip,sparx5-sgpio"; + status = "disabled"; + clocks = <&sys_clk>; + pinctrl-0 = <&sgpio1_pins>; + pinctrl-names = "default"; + reg = <0x6 0x11010484 0x100>; + sgpio_in1: gpio@0 { + compatible = "microchip,sparx5-sgpio-bank"; + reg = <0>; + gpio-controller; + #gpio-cells = <3>; + ngpios = <96>; + }; + sgpio_out1: gpio@1 { + compatible = "microchip,sparx5-sgpio-bank"; + reg = <1>; + gpio-controller; + #gpio-cells = <3>; + ngpios = <96>; + }; + }; + + sgpio2: gpio@61101059c { + #address-cells = <1>; + #size-cells = <0>; + compatible = "microchip,sparx5-sgpio"; + status = "disabled"; + clocks = <&sys_clk>; + pinctrl-0 = <&sgpio2_pins>; + pinctrl-names = "default"; + reg = <0x6 0x1101059c 0x100>; + sgpio_in2: gpio@0 { + reg = <0>; + compatible = "microchip,sparx5-sgpio-bank"; + gpio-controller; + #gpio-cells = <3>; + ngpios = <96>; + }; + sgpio_out2: gpio@1 { + compatible = "microchip,sparx5-sgpio-bank"; + reg = <1>; + gpio-controller; + #gpio-cells = <3>; + ngpios = <96>; + }; + }; + i2c0: i2c@600101000 { compatible = "snps,designware-i2c"; status = "disabled"; diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb125.dts b/arch/arm64/boot/dts/microchip/sparx5_pcb125.dts index 6b2da7c7520c..9baa085d7861 100644 --- a/arch/arm64/boot/dts/microchip/sparx5_pcb125.dts +++ b/arch/arm64/boot/dts/microchip/sparx5_pcb125.dts @@ -69,6 +69,11 @@ }; }; +&sgpio0 { + status = "okay"; + microchip,sgpio-port-ranges = <0 23>; +}; + &i2c1 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi b/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi index f37b478d6534..f0c915160990 100644 --- a/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi +++ b/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi @@ -36,6 +36,264 @@ gpios = <&gpio 37 GPIO_ACTIVE_LOW>; priority = <200>; }; + + leds { + compatible = "gpio-leds"; + led@0 { + label = "twr0:green"; + gpios = <&sgpio_out0 8 0 GPIO_ACTIVE_LOW>; + }; + led@1 { + label = "twr0:yellow"; + gpios = <&sgpio_out0 8 1 GPIO_ACTIVE_LOW>; + }; + led@2 { + label = "twr1:green"; + gpios = <&sgpio_out0 9 0 GPIO_ACTIVE_LOW>; + }; + led@3 { + label = "twr1:yellow"; + gpios = <&sgpio_out0 9 1 GPIO_ACTIVE_LOW>; + }; + led@4 { + label = "twr2:green"; + gpios = <&sgpio_out0 10 0 GPIO_ACTIVE_LOW>; + }; + led@5 { + label = "twr2:yellow"; + gpios = <&sgpio_out0 10 1 GPIO_ACTIVE_LOW>; + }; + led@6 { + label = "twr3:green"; + gpios = <&sgpio_out0 11 0 GPIO_ACTIVE_LOW>; + }; + led@7 { + label = "twr3:yellow"; + gpios = <&sgpio_out0 11 1 GPIO_ACTIVE_LOW>; + }; + led@8 { + label = "eth12:green"; + gpios = <&sgpio_out0 12 0 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + led@9 { + label = "eth12:yellow"; + gpios = <&sgpio_out0 12 1 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + led@10 { + label = "eth13:green"; + gpios = <&sgpio_out0 13 0 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + led@11 { + label = "eth13:yellow"; + gpios = <&sgpio_out0 13 1 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + led@12 { + label = "eth14:green"; + gpios = <&sgpio_out0 14 0 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + led@13 { + label = "eth14:yellow"; + gpios = <&sgpio_out0 14 1 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + led@14 { + label = "eth15:green"; + gpios = <&sgpio_out0 15 0 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + led@15 { + label = "eth15:yellow"; + gpios = <&sgpio_out0 15 1 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + led@16 { + label = "eth48:green"; + gpios = <&sgpio_out1 16 0 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + led@17 { + label = "eth48:yellow"; + gpios = <&sgpio_out1 16 1 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + led@18 { + label = "eth49:green"; + gpios = <&sgpio_out1 17 0 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + led@19 { + label = "eth49:yellow"; + gpios = <&sgpio_out1 17 1 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + led@20 { + label = "eth50:green"; + gpios = <&sgpio_out1 18 0 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + led@21 { + label = "eth50:yellow"; + gpios = <&sgpio_out1 18 1 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + led@22 { + label = "eth51:green"; + gpios = <&sgpio_out1 19 0 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + led@23 { + label = "eth51:yellow"; + gpios = <&sgpio_out1 19 1 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + led@24 { + label = "eth52:green"; + gpios = <&sgpio_out1 20 0 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + led@25 { + label = "eth52:yellow"; + gpios = <&sgpio_out1 20 1 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + led@26 { + label = "eth53:green"; + gpios = <&sgpio_out1 21 0 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + led@27 { + label = "eth53:yellow"; + gpios = <&sgpio_out1 21 1 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + led@28 { + label = "eth54:green"; + gpios = <&sgpio_out1 22 0 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + led@29 { + label = "eth54:yellow"; + gpios = <&sgpio_out1 22 1 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + led@30 { + label = "eth55:green"; + gpios = <&sgpio_out1 23 0 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + led@31 { + label = "eth55:yellow"; + gpios = <&sgpio_out1 23 1 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + led@32 { + label = "eth56:green"; + gpios = <&sgpio_out1 24 0 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + led@33 { + label = "eth56:yellow"; + gpios = <&sgpio_out1 24 1 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + led@34 { + label = "eth57:green"; + gpios = <&sgpio_out1 25 0 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + led@35 { + label = "eth57:yellow"; + gpios = <&sgpio_out1 25 1 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + led@36 { + label = "eth58:green"; + gpios = <&sgpio_out1 26 0 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + led@37 { + label = "eth58:yellow"; + gpios = <&sgpio_out1 26 1 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + led@38 { + label = "eth59:green"; + gpios = <&sgpio_out1 27 0 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + led@39 { + label = "eth59:yellow"; + gpios = <&sgpio_out1 27 1 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + led@40 { + label = "eth60:green"; + gpios = <&sgpio_out1 28 0 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + led@41 { + label = "eth60:yellow"; + gpios = <&sgpio_out1 28 1 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + led@42 { + label = "eth61:green"; + gpios = <&sgpio_out1 29 0 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + led@43 { + label = "eth61:yellow"; + gpios = <&sgpio_out1 29 1 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + led@44 { + label = "eth62:green"; + gpios = <&sgpio_out1 30 0 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + led@45 { + label = "eth62:yellow"; + gpios = <&sgpio_out1 30 1 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + led@46 { + label = "eth63:green"; + gpios = <&sgpio_out1 31 0 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + led@47 { + label = "eth63:yellow"; + gpios = <&sgpio_out1 31 1 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + }; +}; + +&sgpio0 { + status = "okay"; + microchip,sgpio-port-ranges = <8 15>; + gpio@0 { + ngpios = <64>; + }; + gpio@1 { + ngpios = <64>; + }; +}; + +&sgpio1 { + status = "okay"; + microchip,sgpio-port-ranges = <24 31>; + gpio@0 { + ngpios = <64>; + }; + gpio@1 { + ngpios = <64>; + }; }; &spi0 { diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi b/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi index b02b8c8ce44d..e28c6dd16377 100644 --- a/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi +++ b/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi @@ -20,6 +20,50 @@ gpios = <&gpio 37 GPIO_ACTIVE_LOW>; priority = <200>; }; + + leds { + compatible = "gpio-leds"; + led@0 { + label = "eth60:yellow"; + gpios = <&sgpio_out1 28 0 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + led@1 { + label = "eth60:green"; + gpios = <&sgpio_out1 28 1 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + led@2 { + label = "eth61:yellow"; + gpios = <&sgpio_out1 29 0 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + led@3 { + label = "eth61:green"; + gpios = <&sgpio_out1 29 1 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + led@4 { + label = "eth62:yellow"; + gpios = <&sgpio_out1 30 0 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + led@5 { + label = "eth62:green"; + gpios = <&sgpio_out1 30 1 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + led@6 { + label = "eth63:yellow"; + gpios = <&sgpio_out1 31 0 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + led@7 { + label = "eth63:green"; + gpios = <&sgpio_out1 31 1 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + }; }; &gpio { @@ -83,6 +127,17 @@ }; }; +&sgpio1 { + status = "okay"; + microchip,sgpio-port-ranges = <24 31>; + gpio@0 { + ngpios = <64>; + }; + gpio@1 { + ngpios = <64>; + }; +}; + &axi { i2c0_imux: i2c0-imux@0 { compatible = "i2c-mux-pinctrl"; From 4c71373162e8b62d8dc0b86bec61a9f047be7683 Mon Sep 17 00:00:00 2001 From: Max Merchel Date: Mon, 7 Dec 2020 10:30:36 +0100 Subject: [PATCH 789/799] dt-bindings: vendor-prefixes: correct the spelling of TQ-Systems GmbH "TQ-Systems" is written with a dash, as can be seen on https://www.tq-group.com/en/imprint/ Signed-off-by: Max Merchel Signed-off-by: Matthias Schiffer Link: https://lore.kernel.org/r/20201207093036.29824-1-matthias.schiffer@ew.tq-group.com Signed-off-by: Rob Herring --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index 5e69fbfe544c..4e2c527160ef 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -1099,7 +1099,7 @@ patternProperties: "^tpo,.*": description: TPO "^tq,.*": - description: TQ Systems GmbH + description: TQ-Systems GmbH "^tronfy,.*": description: Tronfy "^tronsmart,.*": From b407771668334c3268d5320217ca2b46055c5232 Mon Sep 17 00:00:00 2001 From: Quan Nguyen Date: Tue, 8 Dec 2020 11:36:59 +0700 Subject: [PATCH 790/799] dt-bindings: vendor-prefixes: Add an entry for AmpereComputing.com Add "ampere" entry for Ampere Computing LLC: amperecomputing.com Reviewed-by: Andrew Jeffery Reviewed-by: Joel Stanley Signed-off-by: Quan Nguyen Signed-off-by: Phong Vo Signed-off-by: Thang Q. Nguyen Link: https://lore.kernel.org/r/20201208043700.23098-2-quan@os.amperecomputing.com Signed-off-by: Rob Herring --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index 4e2c527160ef..c0c21be520e9 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -79,6 +79,8 @@ patternProperties: description: Shenzhen Amediatech Technology Co., Ltd "^amlogic,.*": description: Amlogic, Inc. + "^ampere,.*": + description: Ampere Computing LLC "^ampire,.*": description: Ampire Co., Ltd. "^ams,.*": From bdfae1c9a913930eae5ea506733aa7c285e12a06 Mon Sep 17 00:00:00 2001 From: Lu Baolu Date: Wed, 9 Dec 2020 09:44:44 +0800 Subject: [PATCH 791/799] vfio/type1: Add vfio_group_iommu_domain() Add the API for getting the domain from a vfio group. This could be used by the physical device drivers which rely on the vfio/mdev framework for mediated device user level access. The typical use case like below: unsigned int pasid; struct vfio_group *vfio_group; struct iommu_domain *iommu_domain; struct device *dev = mdev_dev(mdev); struct device *iommu_device = mdev_get_iommu_device(dev); if (!iommu_device || !iommu_dev_feature_enabled(iommu_device, IOMMU_DEV_FEAT_AUX)) return -EINVAL; vfio_group = vfio_group_get_external_user_from_dev(dev); if (IS_ERR_OR_NULL(vfio_group)) return -EFAULT; iommu_domain = vfio_group_iommu_domain(vfio_group); if (IS_ERR_OR_NULL(iommu_domain)) { vfio_group_put_external_user(vfio_group); return -EFAULT; } pasid = iommu_aux_get_pasid(iommu_domain, iommu_device); if (pasid < 0) { vfio_group_put_external_user(vfio_group); return -EFAULT; } /* Program device context with pasid value. */ ... Signed-off-by: Lu Baolu Signed-off-by: Alex Williamson --- drivers/vfio/vfio.c | 18 ++++++++++++++++++ drivers/vfio/vfio_iommu_type1.c | 24 ++++++++++++++++++++++++ include/linux/vfio.h | 4 ++++ 3 files changed, 46 insertions(+) diff --git a/drivers/vfio/vfio.c b/drivers/vfio/vfio.c index 2151bc7f87ab..4ad8a35667a7 100644 --- a/drivers/vfio/vfio.c +++ b/drivers/vfio/vfio.c @@ -2331,6 +2331,24 @@ int vfio_unregister_notifier(struct device *dev, enum vfio_notify_type type, } EXPORT_SYMBOL(vfio_unregister_notifier); +struct iommu_domain *vfio_group_iommu_domain(struct vfio_group *group) +{ + struct vfio_container *container; + struct vfio_iommu_driver *driver; + + if (!group) + return ERR_PTR(-EINVAL); + + container = group->container; + driver = container->iommu_driver; + if (likely(driver && driver->ops->group_iommu_domain)) + return driver->ops->group_iommu_domain(container->iommu_data, + group->iommu_group); + + return ERR_PTR(-ENOTTY); +} +EXPORT_SYMBOL_GPL(vfio_group_iommu_domain); + /** * Module/class support */ diff --git a/drivers/vfio/vfio_iommu_type1.c b/drivers/vfio/vfio_iommu_type1.c index 67e827638995..0b4dedaa9128 100644 --- a/drivers/vfio/vfio_iommu_type1.c +++ b/drivers/vfio/vfio_iommu_type1.c @@ -2980,6 +2980,29 @@ static int vfio_iommu_type1_dma_rw(void *iommu_data, dma_addr_t user_iova, return ret; } +static struct iommu_domain * +vfio_iommu_type1_group_iommu_domain(void *iommu_data, + struct iommu_group *iommu_group) +{ + struct iommu_domain *domain = ERR_PTR(-ENODEV); + struct vfio_iommu *iommu = iommu_data; + struct vfio_domain *d; + + if (!iommu || !iommu_group) + return ERR_PTR(-EINVAL); + + mutex_lock(&iommu->lock); + list_for_each_entry(d, &iommu->domain_list, next) { + if (find_iommu_group(d, iommu_group)) { + domain = d->domain; + break; + } + } + mutex_unlock(&iommu->lock); + + return domain; +} + static const struct vfio_iommu_driver_ops vfio_iommu_driver_ops_type1 = { .name = "vfio-iommu-type1", .owner = THIS_MODULE, @@ -2993,6 +3016,7 @@ static const struct vfio_iommu_driver_ops vfio_iommu_driver_ops_type1 = { .register_notifier = vfio_iommu_type1_register_notifier, .unregister_notifier = vfio_iommu_type1_unregister_notifier, .dma_rw = vfio_iommu_type1_dma_rw, + .group_iommu_domain = vfio_iommu_type1_group_iommu_domain, }; static int __init vfio_iommu_type1_init(void) diff --git a/include/linux/vfio.h b/include/linux/vfio.h index 38d3c6a8dc7e..f45940b38a02 100644 --- a/include/linux/vfio.h +++ b/include/linux/vfio.h @@ -90,6 +90,8 @@ struct vfio_iommu_driver_ops { struct notifier_block *nb); int (*dma_rw)(void *iommu_data, dma_addr_t user_iova, void *data, size_t count, bool write); + struct iommu_domain *(*group_iommu_domain)(void *iommu_data, + struct iommu_group *group); }; extern int vfio_register_iommu_driver(const struct vfio_iommu_driver_ops *ops); @@ -126,6 +128,8 @@ extern int vfio_group_unpin_pages(struct vfio_group *group, extern int vfio_dma_rw(struct vfio_group *group, dma_addr_t user_iova, void *data, size_t len, bool write); +extern struct iommu_domain *vfio_group_iommu_domain(struct vfio_group *group); + /* each type has independent events */ enum vfio_notify_type { VFIO_IOMMU_NOTIFY = 0, From f3c6c120614cfb02827ee7bbe6c4240847cc5f12 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Wed, 9 Dec 2020 11:12:31 +0100 Subject: [PATCH 792/799] dt-bindings: pci: rcar-pci-ep: Document missing interrupts property The R-Car PCIe controller does not use interrupts when configured for endpoint mode, hence the bindings do not document the interrupts property. However, all DTS files provide interrupts properties, and thus fail to validate. Fix this by documenting the interrupts property. Fixes: 4c0f80920923f103 ("dt-bindings: PCI: rcar: Add bindings for R-Car PCIe endpoint controller") Signed-off-by: Geert Uytterhoeven Reviewed-by: Lad Prabhakar Link: https://lore.kernel.org/r/20201209101231.2206479-1-geert+renesas@glider.be Signed-off-by: Rob Herring --- Documentation/devicetree/bindings/pci/rcar-pci-ep.yaml | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/rcar-pci-ep.yaml b/Documentation/devicetree/bindings/pci/rcar-pci-ep.yaml index 84eeb7fe6e01..295840cf612f 100644 --- a/Documentation/devicetree/bindings/pci/rcar-pci-ep.yaml +++ b/Documentation/devicetree/bindings/pci/rcar-pci-ep.yaml @@ -32,6 +32,10 @@ properties: - const: memory2 - const: memory3 + interrupts: + minItems: 3 + maxItems: 3 + power-domains: maxItems: 1 @@ -53,6 +57,7 @@ required: - compatible - reg - reg-names + - interrupts - resets - power-domains - clocks @@ -64,6 +69,7 @@ additionalProperties: false examples: - | #include + #include #include pcie0_ep: pcie-ep@fe000000 { @@ -75,6 +81,9 @@ examples: <0x30000000 0x8000000>, <0x38000000 0x8000000>; reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3"; + interrupts = , + , + ; resets = <&cpg 319>; power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; clocks = <&cpg CPG_MOD 319>; From 60a2a8ff3380d42090dd9f9c9ed0987c527254dc Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Thu, 10 Dec 2020 12:47:49 -0600 Subject: [PATCH 793/799] dt-bindings: vendor-prefixes: Add undocumented bm, gpio-key, and mentor prefixes Add bm, gpio-key, and mentor as vendor prefixes which are in use, but undocumented. Signed-off-by: Rob Herring --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index c0c21be520e9..0b52b58aedcc 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -16,7 +16,7 @@ properties: {} patternProperties: # Prefixes which are not vendors, but followed the pattern # DO NOT ADD NEW PROPERTIES TO THIS LIST - "^(at25|devbus|dmacap|dsa|exynos|fsi[ab]|gpio-fan|gpio|gpmc|hdmi|i2c-gpio),.*": true + "^(at25|bm|devbus|dmacap|dsa|exynos|fsi[ab]|gpio-fan|gpio-key|gpio|gpmc|hdmi|i2c-gpio),.*": true "^(keypad|m25p|max8952|max8997|max8998|mpmc),.*": true "^(pinctrl-single|#pinctrl-single|PowerPC),.*": true "^(pl022|pxa-mmc|rcar_sound|rotary-encoder|s5m8767|sdhci),.*": true @@ -659,6 +659,8 @@ patternProperties: description: MEMSIC Inc. "^menlo,.*": description: Menlo Systems GmbH + "^mentor,.*": + description: Mentor Graphics "^meraki,.*": description: Cisco Meraki, LLC "^merrii,.*": From 04e9ab75267489224364fa510a88ada83e11c325 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= Date: Thu, 10 Dec 2020 18:23:52 +0100 Subject: [PATCH 794/799] dt-bindings: mtd: convert "fixed-partitions" to the json-schema MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This standardizes its documentation, allows validating with Makefile checks and helps writing DTS files. Noticeable changes: 1. Dropped "Partitions can be represented by sub-nodes of a flash device." as we also support subpartitions (don't have to be part of flash device node) 2. Dropped "to Linux" as bindings are meant to be os agnostic. Signed-off-by: Rafał Miłecki Link: https://lore.kernel.org/r/20201210172352.31632-1-zajec5@gmail.com Signed-off-by: Rob Herring --- .../devicetree/bindings/mtd/partition.txt | 131 +-------------- .../mtd/partitions/fixed-partitions.yaml | 152 ++++++++++++++++++ 2 files changed, 154 insertions(+), 129 deletions(-) create mode 100644 Documentation/devicetree/bindings/mtd/partitions/fixed-partitions.yaml diff --git a/Documentation/devicetree/bindings/mtd/partition.txt b/Documentation/devicetree/bindings/mtd/partition.txt index 4a39698221a2..ead90e8274d6 100644 --- a/Documentation/devicetree/bindings/mtd/partition.txt +++ b/Documentation/devicetree/bindings/mtd/partition.txt @@ -24,137 +24,10 @@ another partitioning method. Available bindings are listed in the "partitions" subdirectory. -Fixed Partitions -================ - -Partitions can be represented by sub-nodes of a flash device. This can be used -on platforms which have strong conventions about which portions of a flash are -used for what purposes, but which don't use an on-flash partition table such -as RedBoot. - -The partition table should be a subnode of the flash node and should be named -'partitions'. This node should have the following property: -- compatible : (required) must be "fixed-partitions" -Partitions are then defined in subnodes of the partitions node. +Deprecated: partitions defined in flash node +============================================ For backwards compatibility partitions as direct subnodes of the flash device are supported. This use is discouraged. NOTE: also for backwards compatibility, direct subnodes that have a compatible string are not considered partitions, as they may be used for other bindings. - -#address-cells & #size-cells must both be present in the partitions subnode of the -flash device. There are two valid values for both: -<1>: for partitions that require a single 32-bit cell to represent their - size/address (aka the value is below 4 GiB) -<2>: for partitions that require two 32-bit cells to represent their - size/address (aka the value is 4 GiB or greater). - -Required properties: -- reg : The partition's offset and size within the flash - -Optional properties: -- label : The label / name for this partition. If omitted, the label is taken - from the node name (excluding the unit address). -- read-only : This parameter, if present, is a hint to Linux that this - partition should only be mounted read-only. This is usually used for flash - partitions containing early-boot firmware images or data which should not be - clobbered. -- lock : Do not unlock the partition at initialization time (not supported on - all devices) -- slc-mode: This parameter, if present, allows one to emulate SLC mode on a - partition attached to an MLC NAND thus making this partition immune to - paired-pages corruptions - -Examples: - - -flash@0 { - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "u-boot"; - reg = <0x0000000 0x100000>; - read-only; - }; - - uimage@100000 { - reg = <0x0100000 0x200000>; - }; - }; -}; - -flash@1 { - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <2>; - - /* a 4 GiB partition */ - partition@0 { - label = "filesystem"; - reg = <0x00000000 0x1 0x00000000>; - }; - }; -}; - -flash@2 { - partitions { - compatible = "fixed-partitions"; - #address-cells = <2>; - #size-cells = <2>; - - /* an 8 GiB partition */ - partition@0 { - label = "filesystem #1"; - reg = <0x0 0x00000000 0x2 0x00000000>; - }; - - /* a 4 GiB partition */ - partition@200000000 { - label = "filesystem #2"; - reg = <0x2 0x00000000 0x1 0x00000000>; - }; - }; -}; - -flash@3 { - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "bootloader"; - reg = <0x000000 0x100000>; - read-only; - }; - - firmware@100000 { - label = "firmware"; - reg = <0x100000 0xe00000>; - compatible = "brcm,trx"; - }; - - calibration@f00000 { - label = "calibration"; - reg = <0xf00000 0x100000>; - compatible = "fixed-partitions"; - ranges = <0 0xf00000 0x100000>; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "wifi0"; - reg = <0x000000 0x080000>; - }; - - partition@80000 { - label = "wifi1"; - reg = <0x080000 0x080000>; - }; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/mtd/partitions/fixed-partitions.yaml b/Documentation/devicetree/bindings/mtd/partitions/fixed-partitions.yaml new file mode 100644 index 000000000000..6d4a3450e064 --- /dev/null +++ b/Documentation/devicetree/bindings/mtd/partitions/fixed-partitions.yaml @@ -0,0 +1,152 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mtd/partitions/fixed-partitions.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Fixed partitions + +description: | + This binding can be used on platforms which have strong conventions about + which portions of a flash are used for what purposes, but which don't use an + on-flash partition table such as RedBoot. + + The partition table should be a node named "partitions". Partitions are then + defined as subnodes. + +maintainers: + - Rafał Miłecki + +properties: + compatible: + const: fixed-partitions + + "#address-cells": true + + "#size-cells": true + +patternProperties: + "@[0-9a-f]+$": + description: node describing a single flash partition + type: object + + properties: + reg: + description: partition's offset and size within the flash + maxItems: 1 + + label: + description: The label / name for this partition. If omitted, the label + is taken from the node name (excluding the unit address). + + read-only: + description: This parameter, if present, is a hint that this partition + should only be mounted read-only. This is usually used for flash + partitions containing early-boot firmware images or data which should + not be clobbered. + type: boolean + + lock: + description: Do not unlock the partition at initialization time (not + supported on all devices) + type: boolean + + slc-mode: + description: This parameter, if present, allows one to emulate SLC mode + on a partition attached to an MLC NAND thus making this partition + immune to paired-pages corruptions + type: boolean + + required: + - reg + +required: + - "#address-cells" + - "#size-cells" + +additionalProperties: true + +examples: + - | + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "u-boot"; + reg = <0x0000000 0x100000>; + read-only; + }; + + uimage@100000 { + reg = <0x0100000 0x200000>; + }; + }; + - | + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <2>; + + /* a 4 GiB partition */ + partition@0 { + label = "filesystem"; + reg = <0x00000000 0x1 0x00000000>; + }; + }; + - | + partitions { + compatible = "fixed-partitions"; + #address-cells = <2>; + #size-cells = <2>; + + /* an 8 GiB partition */ + partition@0 { + label = "filesystem #1"; + reg = <0x0 0x00000000 0x2 0x00000000>; + }; + + /* a 4 GiB partition */ + partition@200000000 { + label = "filesystem #2"; + reg = <0x2 0x00000000 0x1 0x00000000>; + }; + }; + - | + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "bootloader"; + reg = <0x000000 0x100000>; + read-only; + }; + + firmware@100000 { + compatible = "brcm,trx"; + label = "firmware"; + reg = <0x100000 0xe00000>; + }; + + calibration@f00000 { + compatible = "fixed-partitions"; + label = "calibration"; + reg = <0xf00000 0x100000>; + ranges = <0 0xf00000 0x100000>; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "wifi0"; + reg = <0x000000 0x080000>; + }; + + partition@80000 { + label = "wifi1"; + reg = <0x080000 0x080000>; + }; + }; + }; From 18ce7f4fde3149c729f53a987dbbbba92e08ae24 Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Thu, 10 Dec 2020 10:29:03 -0600 Subject: [PATCH 795/799] ARM: dts: lpc32xx: Remove unused and undocumented 'pnx,timeout' 'pnx,timeout' is unused, undocumented and 'pnx' is not a vendor prefix, so let's remove it. Acked-by: Vladimir Zapolskiy Cc: Sylvain Lemieux Link: https://lore.kernel.org/r/20201210175238.2721550-1-robh@kernel.org Signed-off-by: Rob Herring --- arch/arm/boot/dts/lpc32xx.dtsi | 3 --- 1 file changed, 3 deletions(-) diff --git a/arch/arm/boot/dts/lpc32xx.dtsi b/arch/arm/boot/dts/lpc32xx.dtsi index 7b7ec7b1217b..3a5cfb0ddb20 100644 --- a/arch/arm/boot/dts/lpc32xx.dtsi +++ b/arch/arm/boot/dts/lpc32xx.dtsi @@ -123,7 +123,6 @@ clocks = <&usbclk LPC32XX_USB_CLK_I2C>; #address-cells = <1>; #size-cells = <0>; - pnx,timeout = <0x64>; }; usbclk: clock-controller@f00 { @@ -286,7 +285,6 @@ interrupts = <19 IRQ_TYPE_LEVEL_LOW>; #address-cells = <1>; #size-cells = <0>; - pnx,timeout = <0x64>; clocks = <&clk LPC32XX_CLK_I2C1>; }; @@ -297,7 +295,6 @@ interrupts = <18 IRQ_TYPE_LEVEL_LOW>; #address-cells = <1>; #size-cells = <0>; - pnx,timeout = <0x64>; clocks = <&clk LPC32XX_CLK_I2C2>; }; From a217d8711da5c87fd2862fc36759b6fafa1c4905 Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Thu, 10 Dec 2020 14:03:15 -0600 Subject: [PATCH 796/799] dt-bindings: Remove PicoXcell bindings PicoXcell has had nothing but treewide cleanups for at least the last 8 years and no signs of activity. The most recent activity is a yocto vendor kernel based on v3.0 in 2015. Cc: linux-crypto@vger.kernel.org Acked-by: Jamie Iles Link: https://lore.kernel.org/r/20201210200315.2965567-5-robh@kernel.org Signed-off-by: Rob Herring --- .../devicetree/bindings/arm/picoxcell.txt | 24 ------------------- .../bindings/crypto/picochip-spacc.txt | 21 ---------------- .../devicetree/bindings/net/macb.txt | 2 -- .../bindings/timer/snps,dw-apb-timer.yaml | 7 ------ 4 files changed, 54 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/picoxcell.txt delete mode 100644 Documentation/devicetree/bindings/crypto/picochip-spacc.txt diff --git a/Documentation/devicetree/bindings/arm/picoxcell.txt b/Documentation/devicetree/bindings/arm/picoxcell.txt deleted file mode 100644 index e75c0ef51e69..000000000000 --- a/Documentation/devicetree/bindings/arm/picoxcell.txt +++ /dev/null @@ -1,24 +0,0 @@ -Picochip picoXcell device tree bindings. -======================================== - -Required root node properties: - - compatible: - - "picochip,pc7302-pc3x3" : PC7302 development board with PC3X3 device. - - "picochip,pc7302-pc3x2" : PC7302 development board with PC3X2 device. - - "picochip,pc3x3" : picoXcell PC3X3 device based board. - - "picochip,pc3x2" : picoXcell PC3X2 device based board. - -Timers required properties: - - compatible = "picochip,pc3x2-timer" - - interrupts : The single IRQ line for the timer. - - clock-freq : The frequency in HZ of the timer. - - reg : The register bank for the timer. - -Note: two timers are required - one for the scheduler clock and one for the -event tick/NOHZ. - -VIC required properties: - - compatible = "arm,pl192-vic". - - interrupt-controller. - - reg : The register bank for the device. - - #interrupt-cells : Must be 1. diff --git a/Documentation/devicetree/bindings/crypto/picochip-spacc.txt b/Documentation/devicetree/bindings/crypto/picochip-spacc.txt deleted file mode 100644 index df1151f87745..000000000000 --- a/Documentation/devicetree/bindings/crypto/picochip-spacc.txt +++ /dev/null @@ -1,21 +0,0 @@ -Picochip picoXcell SPAcc (Security Protocol Accelerator) bindings - -Picochip picoXcell devices contain crypto offload engines that may be used for -IPSEC and femtocell layer 2 ciphering. - -Required properties: - - compatible : "picochip,spacc-ipsec" for the IPSEC offload engine - "picochip,spacc-l2" for the femtocell layer 2 ciphering engine. - - reg : Offset and length of the register set for this device - - interrupts : The interrupt line from the SPAcc. - - ref-clock : The input clock that drives the SPAcc. - -Example SPAcc node: - -spacc@10000 { - compatible = "picochip,spacc-ipsec"; - reg = <0x100000 0x10000>; - interrupt-parent = <&vic0>; - interrupts = <24>; - ref-clock = <&ipsec_clk>, "ref"; -}; diff --git a/Documentation/devicetree/bindings/net/macb.txt b/Documentation/devicetree/bindings/net/macb.txt index 0b61a90f1592..46dc52c0739a 100644 --- a/Documentation/devicetree/bindings/net/macb.txt +++ b/Documentation/devicetree/bindings/net/macb.txt @@ -7,8 +7,6 @@ Required properties: Use "cdns,sam9x60-macb" for Microchip sam9x60 SoC. Use "cdns,np4-macb" for NP4 SoC devices. Use "cdns,at32ap7000-macb" for other 10/100 usage or use the generic form: "cdns,macb". - Use "cdns,pc302-gem" for Picochip picoXcell pc302 and later devices based on - the Cadence GEM, or the generic form: "cdns,gem". Use "atmel,sama5d2-gem" for the GEM IP (10/100) available on Atmel sama5d2 SoCs. Use "atmel,sama5d3-macb" for the 10/100Mbit IP available on Atmel sama5d3 SoCs. Use "atmel,sama5d3-gem" for the Gigabit IP available on Atmel sama5d3 SoCs. diff --git a/Documentation/devicetree/bindings/timer/snps,dw-apb-timer.yaml b/Documentation/devicetree/bindings/timer/snps,dw-apb-timer.yaml index 2fc617377e2c..d65faf289a83 100644 --- a/Documentation/devicetree/bindings/timer/snps,dw-apb-timer.yaml +++ b/Documentation/devicetree/bindings/timer/snps,dw-apb-timer.yaml @@ -38,13 +38,6 @@ properties: clock-frequency: true - clock-freq: - $ref: "/schemas/types.yaml#/definitions/uint32" - description: | - Has the same meaning as the 'clock-frequency' property - timer clock - frequency in HZ, but is defined only for the backwards compatibility - with the picoxcell platform. - additionalProperties: false required: From 4aa5b78fb5460adbb876e450ec844e7c1991372d Mon Sep 17 00:00:00 2001 From: Zhen Lei Date: Mon, 14 Dec 2020 20:43:47 +0800 Subject: [PATCH 797/799] dt-bindings: i2c: dw: cancel mandatory requirements for "#address-cells" and "#size-cells" The "#address-cells" and "#size-cells" are required only when the I2C controller has subnodes. However, some I2C controllers defined in "arch/arm64/boot/dts/amd/" and "arch/arm64/boot/dts/hisilicon/" directories do not have child nodes. So they don't need these two properties and don't write them explicitly. Therefore, setting properties "#address-cells" and "#size-cells" as "required" in this yaml file causes the following warnings: /root/linux-next/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dt.yaml: \ i2c@f7100000: '#address-cells' is a required property /root/linux-next/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dt.yaml: \ i2c@f7100000: '#size-cells' is a required property Signed-off-by: Zhen Lei Link: https://lore.kernel.org/r/20201214124347.2120-2-thunder.leizhen@huawei.com Signed-off-by: Rob Herring --- .../devicetree/bindings/i2c/snps,designware-i2c.yaml | 8 -------- 1 file changed, 8 deletions(-) diff --git a/Documentation/devicetree/bindings/i2c/snps,designware-i2c.yaml b/Documentation/devicetree/bindings/i2c/snps,designware-i2c.yaml index 4f746bef2374..c22b66b6219e 100644 --- a/Documentation/devicetree/bindings/i2c/snps,designware-i2c.yaml +++ b/Documentation/devicetree/bindings/i2c/snps,designware-i2c.yaml @@ -101,8 +101,6 @@ unevaluatedProperties: false required: - compatible - reg - - "#address-cells" - - "#size-cells" - interrupts examples: @@ -110,8 +108,6 @@ examples: i2c@f0000 { compatible = "snps,designware-i2c"; reg = <0xf0000 0x1000>; - #address-cells = <1>; - #size-cells = <0>; interrupts = <11>; clock-frequency = <400000>; }; @@ -119,8 +115,6 @@ examples: i2c@1120000 { compatible = "snps,designware-i2c"; reg = <0x1120000 0x1000>; - #address-cells = <1>; - #size-cells = <0>; interrupts = <12 1>; clock-frequency = <400000>; i2c-sda-hold-time-ns = <300>; @@ -148,8 +142,6 @@ examples: reg = <0x100400 0x100>, <0x198 0x8>; pinctrl-0 = <&i2c_pins>; pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; interrupts = <8>; clocks = <&ahb_clk>; }; From 23dd6845c2cfc2f4aabe6d21a6ed013e0927bf89 Mon Sep 17 00:00:00 2001 From: Lukasz Luba Date: Wed, 9 Dec 2020 11:51:42 +0000 Subject: [PATCH 798/799] dt-bindings: mali-midgard: Add dynamic-power-coefficient Add a property dynamic-power-coefficient which allows to register Energy Model for the Mali Midgard devices. Signed-off-by: Lukasz Luba Link: https://lore.kernel.org/r/20201209115143.15321-2-lukasz.luba@arm.com Signed-off-by: Rob Herring --- .../bindings/gpu/arm,mali-midgard.yaml | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-midgard.yaml b/Documentation/devicetree/bindings/gpu/arm,mali-midgard.yaml index e9c42b59f30f..696c17aedbbe 100644 --- a/Documentation/devicetree/bindings/gpu/arm,mali-midgard.yaml +++ b/Documentation/devicetree/bindings/gpu/arm,mali-midgard.yaml @@ -90,6 +90,23 @@ properties: dma-coherent: true + dynamic-power-coefficient: + $ref: '/schemas/types.yaml#/definitions/uint32' + description: + A u32 value that represents the running time dynamic + power coefficient in units of uW/MHz/V^2. The + coefficient can either be calculated from power + measurements or derived by analysis. + + The dynamic power consumption of the GPU is + proportional to the square of the Voltage (V) and + the clock frequency (f). The coefficient is used to + calculate the dynamic power as below - + + Pdyn = dynamic-power-coefficient * V^2 * f + + where voltage is in V, frequency is in MHz. + required: - compatible - reg From e33dc2f3636749c2f949a59c2ff8acd4a69c9c78 Mon Sep 17 00:00:00 2001 From: Lukasz Luba Date: Wed, 9 Dec 2020 11:51:43 +0000 Subject: [PATCH 799/799] dt-bindings: mali-bifrost: Add dynamic-power-coefficient Add a property dynamic-power-coefficient which allows to register Energy Model for the Mali Bifrost devices. Signed-off-by: Lukasz Luba Link: https://lore.kernel.org/r/20201209115143.15321-3-lukasz.luba@arm.com Signed-off-by: Rob Herring --- .../bindings/gpu/arm,mali-bifrost.yaml | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml b/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml index b1844b9c295d..184492162e7e 100644 --- a/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml +++ b/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml @@ -52,6 +52,23 @@ properties: "#cooling-cells": const: 2 + dynamic-power-coefficient: + $ref: '/schemas/types.yaml#/definitions/uint32' + description: + A u32 value that represents the running time dynamic + power coefficient in units of uW/MHz/V^2. The + coefficient can either be calculated from power + measurements or derived by analysis. + + The dynamic power consumption of the GPU is + proportional to the square of the Voltage (V) and + the clock frequency (f). The coefficient is used to + calculate the dynamic power as below - + + Pdyn = dynamic-power-coefficient * V^2 * f + + where voltage is in V, frequency is in MHz. + required: - compatible - reg