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Merge commit '914877f7c16228434d09b83f65b59b2503e8b3cf'

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* commit '914877f7c16228434d09b83f65b59b2503e8b3cf': (235 commits)
  arm64: configs: rockchip_gki: Enable CONFIG_PWRSEQ_SIMPLE
  arm64: rockchip_gki.config: Enable CONFIG_CPU_RK3568
  irqchip/gic-v3: get free page instead of kmalloc for itt
  drm/rockchip: dsi: driver may retry bind when panel or bridge not register
  soc: rockchip: debug: rockchip_show_interrupts print all cpu
  arm64: dts: rockchip: rk3588s: Add hardware version for rk3588m and rk3588j
  driver: rknpu: Implement set_soc_info and set_soc_info for rk3588
  MALI: bifrost: Implement set_soc_info and set_soc_info for rk3588
  soc: rockchip: opp_select: Add support to set soc info
  cpufreq: rockchip: Add support for rk3588j
  usb: dwc2: fix waiting time for host only mode
  clk: rockchip: update the frac clk parent
  video: rockchip: mpp: vepu2: Fix core id limit
  drm/rockchip: drv: split pre mapping into two mapping
  drm/rockchip: vop: add support for cvbs interface on rk3036
  drm/rockchip: drv: register rockchip tve driver
  drm/rockchip: add config options of TVE driver
  ARM: configs: rockchip_linux_defconfig: enable tve
  drm/rockchip: tve: add tve support for rk3036/rk312x/rk322x
  ARM: dts: rockchip: rk3036: add tve node
  ...

Change-Id: I2b0b6c6f87074ef18e56014245a8d1151c667c8f
This commit is contained in:
Tao Huang
2022-12-07 18:46:52 +08:00
parent 22f27b0400 914877f7c1
commit 70278d5f56
192 changed files with 23770 additions and 8355 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
Documentation/devicetree/bindings/phy/phy-rockchip-inno-usb2.yaml
View File

@@ -166,6 +166,10 @@ properties:
controller. It's used when the usb3 phy is disabled, and it needs
to combine with the usbctrl-grf.
rockchip,dis-u2-susphy:
$ref: /schemas/types.yaml#/definitions/flag
description: when set, disable the usb2 phy enter suspend automatically.
required:
- "#phy-cells"
- interrupts

6
MAINTAINERS
View File

@@ -11844,6 +11844,12 @@ F: Documentation/userspace-api/media/drivers/meye*
F: drivers/media/pci/meye/
F: include/uapi/linux/meye.h
MOTORCOMM PHY DRIVER
M: Peter Geis <pgwipeout@gmail.com>
L: netdev@vger.kernel.org
S: Maintained
F: drivers/net/phy/motorcomm.c
MOXA SMARTIO/INDUSTIO/INTELLIO SERIAL CARD
M: Jiri Slaby <jirislaby@kernel.org>
S: Maintained

2
arch/arm/boot/dts/Makefile
View File

@@ -993,7 +993,9 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \
rv1106g-evb1-v10-spi-nand.dtb \
rv1106g-evb1-v10-spi-nor.dtb \
rv1106g-evb2-v10.dtb \
rv1106g-evb2-v11-emmc.dtb \
rv1106g-smart-door-lock-rmsl-v10.dtb \
rv1106g-smart-door-lock-rmsl-v12.dtb \
rv1106g-uvc-demo-v10.dtb \
rv1106g-uvc-demo-v10-spi-nor.dtb \
rv1108-elgin-r1.dtb \

24
arch/arm/boot/dts/rk3036-echo.dts
View File

@@ -167,6 +167,10 @@
status = "okay";
};
&hevc {
status = "okay";
};
&hevc_mmu {
status = "okay";
};
@@ -644,6 +648,10 @@
status = "okay";
};
&mpp_srv {
status = "okay";
};
&sdio {
status = "okay";
@@ -693,6 +701,14 @@
status = "okay";
};
&vdpu {
status = "okay";
};
&vpu_mmu {
status = "okay";
};
&vop {
status = "okay";
};
@@ -701,14 +717,6 @@
status = "okay";
};
&vpu_combo {
status = "okay";
};
&vpu_mmu {
status = "okay";
};
&wdt {
status = "okay";
};

24
arch/arm/boot/dts/rk3036-kylin.dts
View File

@@ -175,6 +175,10 @@
status = "okay";
};
&hevc {
status = "okay";
};
&hevc_mmu {
status = "okay";
};
@@ -372,6 +376,10 @@
status = "okay";
};
&mpp_srv {
status = "okay";
};
&sdio {
status = "okay";
@@ -421,6 +429,14 @@
status = "okay";
};
&vdpu {
status = "okay";
};
&vpu_mmu {
status = "okay";
};
&vop {
status = "okay";
};
@@ -429,14 +445,6 @@
status = "okay";
};
&vpu_combo {
status = "okay";
};
&vpu_mmu {
status = "okay";
};
&wdt {
status = "okay";
};

196
arch/arm/boot/dts/rk3036.dtsi
View File

@@ -155,24 +155,40 @@
};
gpu: gpu@10090000 {
compatible = "rockchip,rk3036-mali", "arm,mali-400";
compatible = "arm,mali400";
reg = <0x10090000 0x10000>;
upthreshold = <40>;
downdifferential = <10>;
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "gp",
"gpmmu",
"pp0",
"ppmmu0";
<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "Mali_GP_IRQ",
"Mali_GP_MMU_IRQ",
"Mali_PP0_IRQ",
"Mali_PP0_MMU_IRQ";
clocks = <&cru SCLK_GPU>;
clock-names = "clk_mali";
assigned-clocks = <&cru SCLK_GPU>;
assigned-clock-rates = <400000000>;
assigned-clock-parents = <&cru PLL_DPLL>;
power-domains = <&power RK3036_PD_GPU>;
operating-points-v2 = <&gpu_opp_table>;
clocks = <&cru SCLK_GPU>, <&cru SCLK_GPU>;
clock-names = "bus", "core";
resets = <&cru SRST_GPU>;
status = "disabled";
gpu_power_model: power_model {
compatible = "arm,mali-simple-power-model";
voltage = <900>;
frequency = <500>;
static-power = <300>;
dynamic-power = <396>;
ts = <32000 4700 (-80) 2>;
thermal-zone = "soc-thermal";
};
};
gpu_opp_table: opp-table1 {
@@ -188,34 +204,32 @@
};
};
vpu: video-codec@10108000 {
compatible = "rockchip,rk3036-vpu", "rockchip,rk3288-vpu";
reg = <0x10108000 0x800>;
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "vepu", "vdpu";
clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
clock-names = "aclk", "hclk";
iommus = <&vpu_mmu>;
/*
* 3036's vpu could not run higher than 300M
*/
assigned-clocks = <&cru ACLK_VCODEC>;
assigned-clock-rates = <297000000>;
assigned-clock-parents = <&cru PLL_GPLL>;
power-domains = <&power RK3036_PD_VPU>;
mpp_srv: mpp-srv {
compatible = "rockchip,mpp-service";
rockchip,taskqueue-count = <1>;
rockchip,resetgroup-count = <1>;
status = "disabled";
};
vpu_service: vpu-service@10108400 {
compatible = "rockchip,sub";
vdpu: vdpu@10108400 {
compatible = "rockchip,vpu-decoder-v1";
reg = <0x10108400 0x400>;
dev_mode = <0>;
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "irq_dec";
clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
clock-names = "aclk_vcodec", "hclk_vcodec";
rockchip,normal-rates = <297000000>, <0>;
assigned-clocks = <&cru ACLK_VCODEC>;
assigned-clock-rates = <297000000>;
assigned-clock-parents = <&cru PLL_GPLL>;
resets = <&cru SRST_VCODEC_A>, <&cru SRST_VCODEC_H>;
reset-names = "shared_video_a", "shared_video_h";
iommus = <&vpu_mmu>;
allocator = <1>;
power-domains = <&power RK3036_PD_VPU>;
rockchip,srv = <&mpp_srv>;
rockchip,taskqueue-node = <0>;
rockchip,resetgroup-node = <0>;
status = "disabled";
};
vpu_mmu: iommu@10108800 {
@@ -223,20 +237,32 @@
reg = <0x10108800 0x100>;
interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "vpu_mmu";
clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
clock-names = "aclk", "iface";
#iommu-cells = <0>;
power-domains = <&power RK3036_PD_VPU>;
status = "disabled";
};
hevc_service: hevc-service@1010c000 {
compatible = "rockchip,sub";
hevc: hevc_service@1010c000 {
compatible = "rockchip,hevc-decoder";
reg = <0x1010c000 0x400>;
dev_mode = <1>;
interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "irq_dec";
allocator = <1>;
clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>, <&cru ACLK_HEVC>;
clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core";
rockchip,normal-rates = <297000000>, <0>, <200000000>;
assigned-clocks = <&cru ACLK_VCODEC>;
assigned-clock-rates = <297000000>;
assigned-clock-parents = <&cru PLL_GPLL>;
resets = <&cru SRST_VCODEC_A>, <&cru SRST_VCODEC_H>, <&cru SRST_HEVC>;
reset-names = "shared_video_a", "shared_video_h", "video_core";
iommus = <&hevc_mmu>;
rockchip,srv = <&mpp_srv>;
rockchip,taskqueue-node = <0>;
rockchip,resetgroup-node = <0>;
power-domains = <&power RK3036_PD_VPU>;
status = "disabled";
};
hevc_mmu: iommu@1010c440 {
@@ -244,32 +270,13 @@
reg = <0x1010c440 0x40>, <0x1010c480 0x40>;
interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hevc_mmu";
clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
clock-names = "aclk", "iface";
#iommu-cells = <0>;
power-domains = <&power RK3036_PD_VPU>;
status = "disabled";
};
vpu_combo: vpu-combo {
compatible = "rockchip,vpu_combo";
rockchip,grf = <&grf>;
subcnt = <2>;
rockchip,sub = <&hevc_service>, <&vpu_service>;
mode_bit = <3>;
mode_ctrl = <0x144>;
clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>,
<&cru ACLK_HEVC>;
clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core";
/* RK3036's vpu could not run higher than 300M */
assigned-clocks = <&cru ACLK_VCODEC>;
assigned-clock-rates = <297000000>;
assigned-clock-parents = <&cru PLL_GPLL>;
resets = <&cru SRST_VCODEC_A>, <&cru SRST_VCODEC_H>,
<&cru SRST_HEVC>;
reset-names = "video_a", "video_h", "video";
power-domains = <&power RK3036_PD_VPU>;
status = "disabled";
};
vop: vop@10118000 {
compatible = "rockchip,rk3036-vop";
reg = <0x10118000 0x19c>;
@@ -288,6 +295,37 @@
reg = <0>;
remote-endpoint = <&hdmi_in_vop>;
};
vop_out_tve: endpoint@1 {
reg = <1>;
remote-endpoint = <&tve_in_vop>;
};
};
};
tve: tve@10118200 {
compatible = "rockchip,rk3036-tve";
reg = <0x10118200 0x100>;
clocks = <&cru ACLK_VIO>;
clock-names = "aclk";
rockchip,saturation = <0x00386346>;
rockchip,brightcontrast = <0x00008b00>;
rockchip,adjtiming = <0xa6c00880>;
rockchip,lumafilter0 = <0x02ff0000>;
rockchip,lumafilter1 = <0xf40202fd>;
rockchip,lumafilter2 = <0xf332d919>;
rockchip,daclevel = <0x3e>;
rockchip,grf = <&grf>;
status = "disabled";
ports {
tve_in: port {
#address-cells = <1>;
#size-cells = <0>;
tve_in_vop: endpoint@0 {
reg = <0>;
remote-endpoint = <&vop_out_tve>;
};
};
};
};
@@ -386,6 +424,8 @@
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
resets = <&cru SRST_MMC0>;
reset-names = "reset";
no-mmc;
no-sdio;
status = "disabled";
};
@@ -400,6 +440,8 @@
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
resets = <&cru SRST_SDIO>;
reset-names = "reset";
no-mmc;
no-sd;
status = "disabled";
};
@@ -420,6 +462,8 @@
dma-names = "rx-tx";
fifo-depth = <0x100>;
non-removable;
no-sdio;
no-sd;
pinctrl-names = "default";
pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
resets = <&cru SRST_EMMC>;
@@ -482,7 +526,10 @@
<&cru ACLK_HEVC>;
pm_qos = <&qos_vpu>;
};
pd_gpu@RK3036_PD_GPU {
reg = <RK3036_PD_GPU>;
clocks = <&cru SCLK_GPU>;
};
};
};
@@ -554,7 +601,7 @@
};
pwm0: pwm@20050000 {
compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
compatible = "rockchip,rk3036-pwm", "rockchip,rk3288-pwm";
reg = <0x20050000 0x10>;
#pwm-cells = <3>;
clocks = <&cru PCLK_PWM>;
@@ -565,7 +612,7 @@
};
pwm1: pwm@20050010 {
compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
compatible = "rockchip,rk3036-pwm", "rockchip,rk3288-pwm";
reg = <0x20050010 0x10>;
#pwm-cells = <3>;
clocks = <&cru PCLK_PWM>;
@@ -576,7 +623,7 @@
};
pwm2: pwm@20050020 {
compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
compatible = "rockchip,rk3036-pwm", "rockchip,rk3288-pwm";
reg = <0x20050020 0x10>;
#pwm-cells = <3>;
clocks = <&cru PCLK_PWM>;
@@ -587,9 +634,10 @@
};
pwm3: pwm@20050030 {
compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
compatible = "rockchip,rk3036-pwm", "rockchip,rk3288-pwm";
reg = <0x20050030 0x10>;
#pwm-cells = <2>;
interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
#pwm-cells = <3>;
clocks = <&cru PCLK_PWM>;
clock-names = "pwm";
pinctrl-names = "active";
@@ -746,35 +794,31 @@
bias-pull-pin-default;
};
pcfg_pull_up: pcfg-pull-up {
bias-pull-up;
};
pcfg_pull_none: pcfg-pull-none {
bias-disable;
};
pwm0 {
pwm0_pin: pwm0-pin {
rockchip,pins = <0 RK_PA0 2 &pcfg_pull_none>;
rockchip,pins = <0 RK_PA0 2 &pcfg_pull_default>;
};
};
pwm1 {
pwm1_pin: pwm1-pin {
rockchip,pins = <0 RK_PA1 2 &pcfg_pull_none>;
rockchip,pins = <0 RK_PA1 2 &pcfg_pull_default>;
};
};
pwm2 {
pwm2_pin: pwm2-pin {
rockchip,pins = <0 RK_PA1 2 &pcfg_pull_none>;
rockchip,pins = <0 RK_PA1 2 &pcfg_pull_default>;
};
};
pwm3 {
pwm3_pin: pwm3-pin {
rockchip,pins = <0 RK_PD3 1 &pcfg_pull_none>;
rockchip,pins = <0 RK_PD3 1 &pcfg_pull_default>;
};
};
@@ -910,8 +954,8 @@
uart0 {
uart0_xfer: uart0-xfer {
rockchip,pins = <0 RK_PC0 1 &pcfg_pull_up>,
<0 RK_PC1 1 &pcfg_pull_up>;
rockchip,pins = <0 RK_PC0 1 &pcfg_pull_default>,
<0 RK_PC1 1 &pcfg_pull_default>;
};
uart0_cts: uart0-cts {
@@ -925,16 +969,16 @@
uart1 {
uart1_xfer: uart1-xfer {
rockchip,pins = <2 RK_PC6 1 &pcfg_pull_up>,
<2 RK_PC7 1 &pcfg_pull_up>;
rockchip,pins = <2 RK_PC6 1 &pcfg_pull_default>,
<2 RK_PC7 1 &pcfg_pull_default>;
};
/* no rts / cts for uart1 */
};
uart2 {
uart2_xfer: uart2-xfer {
rockchip,pins = <1 RK_PC2 2 &pcfg_pull_up>,
<1 RK_PC3 2 &pcfg_pull_up>;
rockchip,pins = <1 RK_PC2 2 &pcfg_pull_default>,
<1 RK_PC3 2 &pcfg_pull_default>;
};
/* no rts / cts for uart2 */
};

20
arch/arm/boot/dts/rk3066a.dtsi
View File

@@ -503,10 +503,6 @@
bias-pull-pin-default;
};
pcfg_pull_up: pcfg-pull-up {
bias-pull-up;
};
pcfg_pull_none: pcfg_pull_none {
bias-disable;
};
@@ -658,8 +654,8 @@
uart0 {
uart0_xfer: uart0-xfer {
rockchip,pins = <1 RK_PA0 1 &pcfg_pull_up>,
<1 RK_PA1 1 &pcfg_pull_up>;
rockchip,pins = <1 RK_PA0 1 &pcfg_pull_default>,
<1 RK_PA1 1 &pcfg_pull_default>;
};
uart0_cts: uart0-cts {
@@ -673,8 +669,8 @@
uart1 {
uart1_xfer: uart1-xfer {
rockchip,pins = <1 RK_PA4 1 &pcfg_pull_up>,
<1 RK_PA5 1 &pcfg_pull_up>;
rockchip,pins = <1 RK_PA4 1 &pcfg_pull_default>,
<1 RK_PA5 1 &pcfg_pull_default>;
};
uart1_cts: uart1-cts {
@@ -688,16 +684,16 @@
uart2 {
uart2_xfer: uart2-xfer {
rockchip,pins = <1 RK_PB0 1 &pcfg_pull_up>,
<1 RK_PB1 1 &pcfg_pull_up>;
rockchip,pins = <1 RK_PB0 1 &pcfg_pull_default>,
<1 RK_PB1 1 &pcfg_pull_default>;
};
/* no rts / cts for uart2 */
};
uart3 {
uart3_xfer: uart3-xfer {
rockchip,pins = <3 RK_PD3 1 &pcfg_pull_up>,
<3 RK_PD4 1 &pcfg_pull_up>;
rockchip,pins = <3 RK_PD3 1 &pcfg_pull_default>,
<3 RK_PD4 1 &pcfg_pull_default>;
};
uart3_cts: uart3-cts {

78
arch/arm/boot/dts/rk3126c-evb-ddr3-v10-linux.dts
View File

@@ -139,25 +139,6 @@
};
};
&codec {
#sound-dai-cells = <0>;
spk-ctl-gpios = <&gpio2 9 GPIO_ACTIVE_HIGH>;
spk-mute-delay = <200>;
hp-mute-delay = <100>;
rk312x_for_mid = <0>;
is_rk3128 = <0>;
spk_volume = <25>;
hp_volume = <25>;
capture_volume = <26>;
gpio_debug = <1>;
codec_hp_det = <0>;
status = "okay";
};
&cpu0 {
cpu-supply = <&vdd_arm>;
};
&cif_new {
status = "okay";
@@ -178,6 +159,25 @@
};
};
&codec {
#sound-dai-cells = <0>;
spk-ctl-gpios = <&gpio2 9 GPIO_ACTIVE_HIGH>;
spk-mute-delay = <200>;
hp-mute-delay = <100>;
rk312x_for_mid = <0>;
is_rk3128 = <0>;
spk_volume = <25>;
hp_volume = <25>;
capture_volume = <26>;
gpio_debug = <1>;
codec_hp_det = <0>;
status = "okay";
};
&cpu0 {
cpu-supply = <&vdd_arm>;
};
&display_subsystem {
status = "okay";
};
@@ -751,6 +751,10 @@
status = "okay";
};
&mpp_srv {
status = "okay";
};
&nandc {
status = "okay";
};
@@ -792,16 +796,6 @@
vref-supply = <&vccadc_ref>;
};
&sdmmc {
cap-mmc-highspeed;
supports-sd;
card-detect-delay = <800>;
ignore-pm-notify;
keep-power-in-suspend;
cd-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; /* CD GPIO */
status = "disabled";
};
&sdio {
bus-width = <4>;
max-frequency = <50000000>;
@@ -814,6 +808,16 @@
status = "okay";
};
&sdmmc {
cap-mmc-highspeed;
supports-sd;
card-detect-delay = <800>;
ignore-pm-notify;
keep-power-in-suspend;
cd-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; /* CD GPIO */
status = "disabled";
};
&tsadc {
status = "okay";
};
@@ -849,6 +853,14 @@
status = "okay";
};
&vdpu {
status = "okay";
};
&vepu {
status = "okay";
};
&video_phy {
status = "okay";
};
@@ -861,14 +873,6 @@
status = "okay";
};
&vdpu {
status = "okay";
};
&vepu {
status = "okay";
};
&vpu_mmu {
status = "okay";
};

107
arch/arm/boot/dts/rk3128-evb-ddr3-v10-linux.dts
View File

@@ -242,6 +242,20 @@
};
};
&cif_new {
status = "okay";
ports {
port@0 {
cif_in_bcam: endpoint@0 {
remote-endpoint = <&gc2145_out>;
vsync-active = <0>;
hsync-active = <1>;
};
};
};
};
&codec{
spk-ctl-gpios = <&gpio0 RK_PD6 GPIO_ACTIVE_HIGH>;
hp-ctl-gpios = <&gpio3 RK_PC4 GPIO_ACTIVE_LOW>;
@@ -264,20 +278,6 @@
cpu-supply = <&vdd_arm>;
};
&cif_new {
status = "okay";
ports {
port@0 {
cif_in_bcam: endpoint@0 {
remote-endpoint = <&gc2145_out>;
vsync-active = <0>;
hsync-active = <1>;
};
};
};
};
&display_subsystem {
status = "okay";
};
@@ -615,6 +615,13 @@
#clock-cells = <1>;
clock-output-names = "rk805-clkout1", "rk805-clkout2";
vcc1-supply = <&vcc5v0_sys>;
vcc2-supply = <&vcc5v0_sys>;
vcc3-supply = <&vcc5v0_sys>;
vcc4-supply = <&vcc5v0_sys>;
vcc5-supply = <&vcc_io>;
vcc6-supply = <&vcc_io>;
rtc {
status = "okay";
};
@@ -633,7 +640,7 @@
#address-cells = <1>;
#size-cells = <0>;
vdd_arm: RK805_DCDC1@0 {
vdd_arm: DCDC_REG1 {
regulator-name = "vdd_arm";
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1500000>;
@@ -648,7 +655,7 @@
};
};
vdd_logic: RK805_DCDC2@1 {
vdd_logic: DCDC_REG2 {
regulator-name = "vdd_logic";
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1500000>;
@@ -663,7 +670,7 @@
};
};
vcc_ddr: RK805_DCDC3@2 {
vcc_ddr: DCDC_REG3 {
regulator-name = "vcc_ddr";
regulator-initial-mode = <0x1>;
regulator-boot-on;
@@ -674,7 +681,7 @@
};
};
vcc_io: RK805_DCDC4@3 {
vcc_io: DCDC_REG4 {
regulator-name = "vcc_io";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
@@ -688,7 +695,7 @@
};
};
vcca_33: RK805_LDO1@4 {
vcca_33: LDO_REG1 {
regulator-name = "vcca_33";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
@@ -701,7 +708,7 @@
};
};
vcc_1v8_cam: RK805_LDO2@5 {
vcc_1v8_cam: LDO_REG2 {
regulator-name = "vcc_1v8_cam";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
@@ -713,7 +720,7 @@
};
};
vdd10_pmu: RK805_LDO3@6 {
vdd10_pmu: LDO_REG3 {
regulator-name = "vdd10_pmu";
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1100000>;
@@ -785,6 +792,10 @@
#sound-dai-cells = <0>;
};
&mpp_srv {
status = "okay";
};
&pinctrl {
codec{
spk_ctl_h: spk-ctl-h{
@@ -895,19 +906,6 @@
vref-supply = <&vcc_io>;
};
&sdmmc {
cap-mmc-highspeed;
cap-sd-highspeed;
supports-sd;
vmmc-supply = <&vcc_sdmmc>;
broken-cd;
card-detect-delay = <800>;
ignore-pm-notify;
keep-power-in-suspend;
cd-gpios = <&gpio1 RK_PC1 GPIO_ACTIVE_HIGH>; /* CD GPIO */
status = "disabled";
};
&sdio {
max-frequency = <50000000>;
supports-sdio;
@@ -923,6 +921,19 @@
status = "okay";
};
&sdmmc {
cap-mmc-highspeed;
cap-sd-highspeed;
supports-sd;
vmmc-supply = <&vcc_sdmmc>;
broken-cd;
card-detect-delay = <800>;
ignore-pm-notify;
keep-power-in-suspend;
cd-gpios = <&gpio1 RK_PC1 GPIO_ACTIVE_HIGH>; /* CD GPIO */
status = "disabled";
};
&spdif{
compatible = "rockchip,rk3188-spdif";
status = "okay";
@@ -931,12 +942,6 @@
#sound-dai-cells = <0>;
};
&uart0{
pinctrl-names = "default";
pinctrl-0 = <&uart0_xfer &uart0_cts>;
status = "okay";
};
&u2phy {
status = "okay";
@@ -950,6 +955,12 @@
};
};
&uart0{
pinctrl-names = "default";
pinctrl-0 = <&uart0_xfer &uart0_cts>;
status = "okay";
};
&usb_host_ehci {
status = "okay";
};
@@ -962,14 +973,6 @@
status = "okay";
};
&vop {
status = "okay";
};
&vop_mmu {
status = "okay";
};
&vdpu {
status = "okay";
};
@@ -978,6 +981,14 @@
status = "okay";
};
&vop {
status = "okay";
};
&vop_mmu {
status = "okay";
};
&vpu_mmu {
status = "okay";
};

2
arch/arm/boot/dts/rk312x-android.dtsi
View File

@@ -24,7 +24,7 @@
rockchip,signal-irq = <159>;
rockchip,wake-irq = <0>;
/* If enable uart uses irq instead of fiq */
rockchip,irq-mode-enable = <0>;
rockchip,irq-mode-enable = <1>;
rockchip,baudrate = <115200>; /* Only 115200 and 1500000 */
interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_LOW>;
status = "okay";

20
arch/arm/boot/dts/rk312x.dtsi
View File

@@ -234,7 +234,7 @@
system-status-freq = <
/*system status freq(KHz)*/
SYS_STATUS_NORMAL 456000
SYS_STATUS_SUSPEND 456000
SYS_STATUS_SUSPEND 300000
SYS_STATUS_REBOOT 456000
>;
auto-min-freq = <456000>;
@@ -248,6 +248,7 @@
opp-200000000 {
opp-hz = /bits/ 64 <200000000>;
opp-microvolt = <1025000>;
status = "disabled";
};
opp-300000000 {
opp-hz = /bits/ 64 <300000000>;
@@ -616,7 +617,6 @@
clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>;
clock-names = "aclk_rga", "hclk_rga", "sclk_rga";
power-domains = <&power RK3128_PD_VIO>;
dma-coherent;
status = "disabled";
};
@@ -1294,10 +1294,6 @@
bias-pull-pin-default;
};
pcfg_pull_up: pcfg-pull-up {
bias-pull-up;
};
pcfg_output_high: pcfg-output-high {
output-high;
};
@@ -1422,8 +1418,8 @@
uart0 {
uart0_xfer: uart0-xfer {
rockchip,pins = <2 RK_PD2 2 &pcfg_pull_up>,
<2 RK_PD3 2 &pcfg_pull_up>;
rockchip,pins = <2 RK_PD2 2 &pcfg_pull_default>,
<2 RK_PD3 2 &pcfg_pull_none>;
};
uart0_cts: uart0-cts {
@@ -1437,8 +1433,8 @@
uart1 {
uart1_xfer: uart1-xfer {
rockchip,pins = <1 RK_PB1 2 &pcfg_pull_up>,
<1 RK_PB2 2 &pcfg_pull_up>;
rockchip,pins = <1 RK_PB1 2 &pcfg_pull_default>,
<1 RK_PB2 2 &pcfg_pull_default>;
};
uart1_cts: uart1-cts {
@@ -1452,8 +1448,8 @@
uart2 {
uart2_xfer: uart2-xfer {
rockchip,pins = <1 RK_PC2 2 &pcfg_pull_up>,
<1 RK_PC3 2 &pcfg_pull_up>;
rockchip,pins = <1 RK_PC2 2 &pcfg_pull_default>,
<1 RK_PC3 2 &pcfg_pull_none>;
};
uart2_cts: uart2-cts {

21
arch/arm/boot/dts/rk3288-android.dtsi
View File

@@ -152,11 +152,6 @@
};
};
psci {
compatible = "arm,psci-1.0";
method = "smc";
};
/delete-node/ timer@ff810000;
display-subsystem {
@@ -243,22 +238,6 @@
};
};
&cpu0 {
enable-method = "psci";
};
&cpu1 {
enable-method = "psci";
};
&cpu2 {
enable-method = "psci";
};
&cpu3 {
enable-method = "psci";
};
&dmac_bus_s {
/* change to non-secure dmac */
reg = <0x0 0xff600000 0x0 0x4000>;

20
arch/arm/boot/dts/rk3288-evb-act8846.dts
View File

@@ -7,6 +7,22 @@
model = "Rockchip RK3288 EVB ACT8846";
compatible = "rockchip,rk3288-evb-act8846", "rockchip,rk3288";
sdio_pwrseq: sdio-pwrseq {
compatible = "mmc-pwrseq-simple";
clocks = <&hym8563>;
clock-names = "ext_clock";
pinctrl-names = "default";
pinctrl-0 = <&wifi_enable_h>;
/*
* On the module itself this is one of these (depending
* on the actual card populated):
* - SDIO_RESET_L_WL_REG_ON
* - PDN (power down when low)
*/
reset-gpios = <&gpio4 28 GPIO_ACTIVE_LOW>;
};
vcc_lcd: vcc-lcd {
compatible = "regulator-fixed";
enable-active-high;
@@ -54,12 +70,12 @@
vin-supply = <&vcc_sys>;
};
hym8563@51 {
hym8563: hym8563@51 {
compatible = "haoyu,hym8563";
reg = <0x51>;
interrupt-parent = <&gpio0>;
interrupts = <RK_PA4 IRQ_TYPE_EDGE_FALLING>;
interrupts = <4 IRQ_TYPE_EDGE_FALLING>;
pinctrl-names = "default";
pinctrl-0 = <&pmic_int>;

135
arch/arm/boot/dts/rk3288-evb-rk808-linux.dts
View File

@@ -41,44 +41,10 @@
/dts-v1/;
#include "rk3288-evb.dtsi"
#include "rk3288-linux.dtsi"
#include "rk3288-rkisp1.dtsi"
/ {
compatible = "rockchip,rk3288-evb-rk808-linux", "rockchip,rk3288";
panel {
compatible = "simple-panel";
backlight = <&backlight>;
enable-gpios = <&gpio7 RK_PA4 GPIO_ACTIVE_HIGH>;
prepare-delay-ms = <120>;
display-timings {
native-mode = <&timing0>;
timing0: timing0 {
clock-frequency = <200000000>;
hactive = <1536>;
vactive = <2048>;
hfront-porch = <12>;
hsync-len = <16>;
hback-porch = <48>;
vfront-porch = <8>;
vsync-len = <4>;
vback-porch = <8>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <0>;
pixelclk-active = <0>;
};
};
port {
panel_in_edp: endpoint {
remote-endpoint = <&edp_out_panel>;
};
};
};
adc-keys {
compatible = "adc-keys";
io-channels = <&saradc 1>;
@@ -191,21 +157,6 @@
status = "okay";
};
&edp {
force-hpd;
status = "okay";
ports {
port@1 {
reg = <1>;
edp_out_panel: endpoint {
remote-endpoint = <&panel_in_edp>;
};
};
};
};
&edp_in_vopb {
status = "disabled";
};
@@ -220,7 +171,7 @@
};
&hdmi {
pinctrl-0 = <&hdmi_ddc>, <&hdmi_cec>;
pinctrl-0 = <&hdmi_ddc>, <&hdmi_cec_c0>;
};
&i2c0 {
@@ -477,29 +428,50 @@
ov13850: ov13850@10 {
compatible = "ovti,ov13850";
status = "okay";
reg = <0x10>;
clocks = <&cru SCLK_VIP_OUT>;
clock-names = "xvclk";
reset-gpios = <&gpio7 21 GPIO_ACTIVE_HIGH>;
pwdn-gpios = <&gpio2 15 GPIO_ACTIVE_HIGH>;
/* avdd-supply = <>; */
/* dvdd-supply = <>; */
/* dovdd-supply = <>; */
/* reset-gpios = <>; */
pinctrl-names = "rockchip,camera_default";
pinctrl-0 = <&isp_mipi>;
power-gpio = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>;
reset-gpio = <&gpio7 RK_PC5 GPIO_ACTIVE_HIGH>;
pwdn-gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>;
rockchip,camera-module-index = <0>;
rockchip,camera-module-facing = "back";
rockchip,camera-module-name = "CMK-CT0116";
rockchip,camera-module-lens-name = "Largan-50013A1";
port {
cam_out: endpoint {
remote-endpoint = <&mipi_in_cam>;
ov13850_out: endpoint {
remote-endpoint = <&mipi_in_ucam0>;
data-lanes = <1 2>;
};
};
};
};
&isp {
status = "okay";
port {
isp_mipi_in: endpoint {
remote-endpoint = <&dphy_rx0_out>;
gc8034: gc8034@37 {
compatible = "galaxycore,gc8034";
status = "okay";
reg = <0x37>;
clocks = <&cru SCLK_VIP_OUT>;
clock-names = "xvclk";
pinctrl-names = "rockchip,camera_default";
pinctrl-0 = <&isp_mipi>;
power-gpio = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>;
reset-gpios = <&gpio7 RK_PC5 GPIO_ACTIVE_LOW>;
pwdn-gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_LOW>;
rockchip,camera-module-index = <0>;
rockchip,camera-module-facing = "back";
rockchip,camera-module-name = "LH-RK-8034-v1.0";
rockchip,camera-module-lens-name = "CK8401";
port {
gc8034_out: endpoint {
remote-endpoint = <&mipi_in_gc8034>;
data-lanes = <1 2 3 4>;
};
};
};
};
@@ -517,23 +489,48 @@
port@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
mipi_in_cam: endpoint {
remote-endpoint = <&cam_out>;
mipi_in_ucam0: endpoint@1 {
reg = <1>;
remote-endpoint = <&ov13850_out>;
data-lanes = <1 2>;
};
mipi_in_gc8034: endpoint@0 {
reg = <0>;
remote-endpoint = <&gc8034_out>;
data-lanes = <1 2 3 4>;
};
};
port@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
dphy_rx0_out: endpoint {
dphy_rx_out: endpoint@0 {
reg = <0>;
remote-endpoint = <&isp_mipi_in>;
};
};
};
};
&rkisp1 {
status = "okay";
port {
#address-cells = <1>;
#size-cells = <0>;
isp_mipi_in: endpoint@0 {
reg = <0>;
remote-endpoint = <&dphy_rx_out>;
};
};
};
&rga {
status = "okay";
};
@@ -546,10 +543,6 @@
status = "okay";
};
&sound {
status = "okay";
};
&uart2 {
status = "disabled";
};

16
arch/arm/boot/dts/rk3288-evb-rk808.dts
View File

@@ -6,6 +6,22 @@
/ {
model = "Rockchip RK3288 EVB RK808";
compatible = "rockchip,rk3288-evb-rk808", "rockchip,rk3288";
sdio_pwrseq: sdio-pwrseq {
compatible = "mmc-pwrseq-simple";
clocks = <&rk808 1>;
clock-names = "ext_clock";
pinctrl-names = "default";
pinctrl-0 = <&wifi_enable_h>;
/*
* On the module itself this is one of these (depending
* on the actual card populated):
* - SDIO_RESET_L_WL_REG_ON
* - PDN (power down when low)
*/
reset-gpios = <&gpio4 28 GPIO_ACTIVE_LOW>;
};
};
&i2c0 {

180
arch/arm/boot/dts/rk3288-evb.dtsi
View File

@@ -47,6 +47,45 @@
};
};
sound: sound {
compatible = "simple-audio-card";
simple-audio-card,format = "i2s";
simple-audio-card,name = "rockchip,rt5640-codec";
simple-audio-card,mclk-fs = <512>;
status = "okay";
simple-audio-card,dai-link@0 {
format = "i2s";
cpu {
sound-dai = <&i2s>;
};
codec {
sound-dai = <&rt5640>;
};
};
simple-audio-card,dai-link@1 {
format = "i2s";
cpu {
sound-dai = <&i2s>;
};
codec {
sound-dai = <&hdmi>;
};
};
};
hdmi_analog_sound: hdmi-analog-sound {
compatible = "rockchip,rk3288-hdmi-analog",
"rockchip,rk3368-hdmi-analog";
rockchip,model = "rockchip,rt5640-codec";
rockchip,cpu = <&i2s>;
rockchip,codec = <&rt5640>, <&hdmi>;
status = "disabled";
};
backlight: backlight {
compatible = "pwm-backlight";
brightness-levels = <
@@ -97,10 +136,28 @@
};
panel: panel {
compatible = "lg,lp079qx1-sp0v";
compatible = "simple-panel";
backlight = <&backlight>;
enable-gpios = <&gpio7 RK_PA4 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&lcd_cs>;
prepare-delay-ms = <120>;
panel-timing {
clock-frequency = <200000000>;
hactive = <1536>;
hfront-porch = <12>;
hback-porch = <48>;
hsync-len = <16>;
vactive = <2048>;
vfront-porch = <8>;
vback-porch = <8>;
vsync-len = <4>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <0>;
pixelclk-active = <0>;
};
ports {
panel_in: port {
@@ -140,6 +197,15 @@
regulator-boot-on;
};
vcc_otg_vbus: otg-vbus-regulator {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&otg_vbus_drv>;
regulator-name = "vcc_otg_vbus";
};
vcc_phy: vcc-phy-regulator {
compatible = "regulator-fixed";
enable-active-high;
@@ -178,6 +244,27 @@
startup-delay-us = <100000>;
vin-supply = <&vcc_io>;
};
wireless-bluetooth {
compatible = "bluetooth-platdata";
uart_rts_gpios = <&gpio4 19 GPIO_ACTIVE_LOW>;
pinctrl-names = "default", "rts_gpio";
pinctrl-0 = <&uart0_rts>;
pinctrl-1 = <&uart0_gpios>;
BT,reset_gpio = <&gpio4 29 GPIO_ACTIVE_HIGH>;
BT,wake_gpio = <&gpio4 26 GPIO_ACTIVE_HIGH>;
BT,wake_host_irq = <&gpio4 31 GPIO_ACTIVE_HIGH>;
status = "okay";
};
wireless-wlan {
compatible = "wlan-platdata";
rockchip,grf = <&grf>;
wifi_chip_type = "ap6335";
sdio_vref = <1800>;
WIFI,host_wake_irq = <&gpio4 30 GPIO_ACTIVE_HIGH>;
status = "okay";
};
};
&cpu0 {
@@ -226,6 +313,10 @@
&sdmmc {
bus-width = <4>;
cap-mmc-highspeed;
sd-uhs-sdr12;
sd-uhs-sdr25;
sd-uhs-sdr50;
sd-uhs-sdr104;
cap-sd-highspeed;
no-mmc;
no-sdio;
@@ -261,7 +352,6 @@
};
&hdmi {
ddc-i2c-bus = <&i2c5>;
status = "okay";
};
@@ -269,7 +359,39 @@
status = "okay";
};
&i2c5 {
&i2c2 {
status = "okay";
rt5640: rt5640@1c {
#sound-dai-cells = <0>;
compatible = "realtek,rt5640";
reg = <0x1c>;
clocks = <&cru SCLK_I2S0_OUT>;
clock-names = "mclk";
interrupt-parent = <&gpio7>;
interrupts = <7 IRQ_TYPE_EDGE_FALLING>;
pinctrl-names = "default";
pinctrl-0 = <&i2s0_mclk>;
};
};
&i2c4 {
status = "okay";
clock-frequency = <400000>;
gsl3673@40 {
compatible = "GSL,GSL3673";
reg = <0x40>;
screen_max_x = <1536>;
screen_max_y = <2048>;
irq_gpio_number = <&gpio7 6 IRQ_TYPE_LEVEL_LOW>;
rst_gpio_number = <&gpio7 5 GPIO_ACTIVE_HIGH>;
status = "okay";
};
};
&i2s {
#sound-dai-cells = <0>;
status = "okay";
};
@@ -281,11 +403,25 @@
status = "okay";
};
&uart0 {
&sdio0 {
status = "okay";
max-frequency = <150000000>;
bus-width = <4>;
cap-sd-highspeed;
no-mmc;
no-sd;
cap-sdio-irq;
mmc-pwrseq = <&sdio_pwrseq>;
keep-power-in-suspend;
non-removable;
pinctrl-names = "default";
pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk &sdio0_int>;
sd-uhs-sdr104;
};
&uart1 {
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_xfer &uart0_cts>;
status = "okay";
};
@@ -293,14 +429,6 @@
status = "okay";
};
&uart3 {
status = "okay";
};
&uart4 {
status = "okay";
};
&tsadc {
rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */
rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */
@@ -341,6 +469,12 @@
};
};
sdio-pwrseq {
wifi_enable_h: wifi-enable-h {
rockchip,pins = <4 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
sdmmc {
/*
* Default drive strength isn't enough to achieve even
@@ -370,6 +504,10 @@
host_vbus_drv: host-vbus-drv {
rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
};
otg_vbus_drv: otg-bus-drv {
rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
eth_phy {
@@ -377,6 +515,12 @@
rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
wireless-bluetooth {
uart0_gpios: uart0-gpios {
rockchip,pins = <4 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
};
&usbphy {
@@ -384,6 +528,11 @@
};
&usb_host0_ehci {
rockchip-relinquish-port;
status = "okay";
};
&usb_host0_ohci {
status = "okay";
};
@@ -391,6 +540,11 @@
status = "okay";
};
&usb_otg {
vbus-supply = <&vcc_otg_vbus>;
status = "okay";
};
&vopb {
status = "okay";
};

21
arch/arm/boot/dts/rk3288-firefly-rk808.dts
View File

@@ -217,11 +217,6 @@
clock-names = "ext_clock";
};
psci {
compatible = "arm,psci-1.0";
method = "smc";
};
rk_key: rockchip-key {
compatible = "rockchip,key";
status = "okay";
@@ -632,22 +627,6 @@
status = "okay";
};
&cpu0 {
enable-method = "psci";
};
&cpu1 {
enable-method = "psci";
};
&cpu2 {
enable-method = "psci";
};
&cpu3 {
enable-method = "psci";
};
&dfi {
status = "okay";
};

44
arch/arm/boot/dts/rk3288-linux.dtsi
View File

@@ -8,7 +8,7 @@
/ {
chosen {
bootargs = "earlycon=uart8250,mmio32,0xff690000 vmalloc=496M rw root=PARTUUID=614e0000-0000 rootfstype=ext4 rootwait";
bootargs = "earlycon=uart8250,mmio32,0xff690000 console=ttyFIQ0 vmalloc=496M rw root=PARTUUID=614e0000-0000 rootfstype=ext4 rootwait";
};
/delete-node/ dmc@ff610000;
@@ -89,17 +89,12 @@
interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
rockchip,serial-id = <2>;
rockchip,wake-irq = <0>;
rockchip,irq-mode-enable = <0>; /* If enable uart uses irq instead of fiq */
rockchip,irq-mode-enable = <1>; /* If enable uart uses irq instead of fiq */
rockchip,baudrate = <115200>; /* Only 115200 and 1500000 */
pinctrl-names = "default";
pinctrl-0 = <&uart2_xfer>;
};
psci {
compatible = "arm,psci-1.0";
method = "smc";
};
/delete-node/ timer@ff810000;
display-subsystem {
@@ -157,22 +152,6 @@
};
};
&cpu0 {
enable-method = "psci";
};
&cpu1 {
enable-method = "psci";
};
&cpu2 {
enable-method = "psci";
};
&cpu3 {
enable-method = "psci";
};
&dmac_bus_s {
/* change to non-secure dmac */
reg = <0x0 0xff600000 0x0 0x4000>;
@@ -194,6 +173,25 @@
status = "okay";
};
&iep {
status = "okay";
};
&iep_mmu {
status = "okay";
};
&rga {
compatible = "rockchip,rga2";
clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>;
clock-names = "aclk_rga", "hclk_rga", "clk_rga";
status = "okay";
};
&rng {
status = "okay";
};
&uart2 {
status = "disabled";
};

678
arch/arm/boot/dts/rk3288-pinctrl.dtsi Normal file
View File

@@ -0,0 +1,678 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2022 Rockchip Electronics Co., Ltd.
*/
#include <dt-bindings/pinctrl/rockchip.h>
#include "rockchip-pinconf.dtsi"
&pinctrl {
hdmi {
hdmi_gpio: hdmi-gpio {
rockchip,pins =
<7 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>,
<7 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>;
};
hdmi_cec_c0: hdmi-cec-c0 {
rockchip,pins =
<7 RK_PC0 2 &pcfg_pull_none>;
};
hdmi_cec_c7: hdmi-cec-c7 {
rockchip,pins =
<7 RK_PC7 4 &pcfg_pull_none>;
};
hdmi_ddc: hdmi-ddc {
rockchip,pins =
<7 RK_PC3 2 &pcfg_pull_none>,
<7 RK_PC4 2 &pcfg_pull_none>;
};
hdmi_ddc_unwedge: hdmi-ddc-unwedge {
rockchip,pins =
<7 RK_PC3 RK_FUNC_GPIO &pcfg_output_low>,
<7 RK_PC4 2 &pcfg_pull_none>;
};
};
suspend {
global_pwroff: global-pwroff {
rockchip,pins =
<0 RK_PA0 1 &pcfg_pull_none>;
};
ddrio_pwroff: ddrio-pwroff {
rockchip,pins =
<0 RK_PA1 1 &pcfg_pull_none>;
};
ddr0_retention: ddr0-retention {
rockchip,pins =
<0 RK_PA2 1 &pcfg_pull_up>;
};
ddr1_retention: ddr1-retention {
rockchip,pins =
<0 RK_PA3 1 &pcfg_pull_up>;
};
};
edp {
edp_hpd: edp-hpd {
rockchip,pins =
<7 RK_PB3 2 &pcfg_pull_down>;
};
};
i2c0 {
i2c0_xfer: i2c0-xfer {
rockchip,pins =
<0 RK_PB7 1 &pcfg_pull_none>,
<0 RK_PC0 1 &pcfg_pull_none>;
};
};
i2c1 {
i2c1_xfer: i2c1-xfer {
rockchip,pins =
<8 RK_PA4 1 &pcfg_pull_none>,
<8 RK_PA5 1 &pcfg_pull_none>;
};
};
i2c2 {
i2c2_xfer: i2c2-xfer {
rockchip,pins =
<6 RK_PB1 1 &pcfg_pull_none>,
<6 RK_PB2 1 &pcfg_pull_none>;
};
};
i2c3 {
i2c3_xfer: i2c3-xfer {
rockchip,pins =
<2 RK_PC0 1 &pcfg_pull_none>,
<2 RK_PC1 1 &pcfg_pull_none>;
};
};
i2c4 {
i2c4_xfer: i2c4-xfer {
rockchip,pins =
<7 RK_PC1 1 &pcfg_pull_none>,
<7 RK_PC2 1 &pcfg_pull_none>;
};
};
i2c5 {
i2c5_xfer: i2c5-xfer {
rockchip,pins =
<7 RK_PC3 1 &pcfg_pull_none>,
<7 RK_PC4 1 &pcfg_pull_none>;
};
};
i2s0 {
i2s0_bus: i2s0-bus {
rockchip,pins =
<6 RK_PA0 1 &pcfg_pull_none>,
<6 RK_PA1 1 &pcfg_pull_none>,
<6 RK_PA2 1 &pcfg_pull_none>,
<6 RK_PA3 1 &pcfg_pull_none>,
<6 RK_PA4 1 &pcfg_pull_none>;
};
i2s0_mclk: i2s0-mclk {
rockchip,pins =
<6 RK_PB0 1 &pcfg_pull_none>;
};
};
lcdc {
lcdc_rgb_pins: lcdc-rgb-pins {
rockchip,pins =
<1 RK_PD3 1 &pcfg_pull_none>, /* LCDC_DCLK */
<1 RK_PD2 1 &pcfg_pull_none>, /* LCDC_DEN */
<1 RK_PD1 1 &pcfg_pull_none>, /* LCDC_VSYNC */
<1 RK_PD0 1 &pcfg_pull_none>; /* LCDC_HSYNC */
};
lcdc_sleep_pins: lcdc-sleep-pins {
rockchip,pins =
<1 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_DCLK */
<1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_DEN */
<1 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_VSYNC */
<1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; /* LCDC_HSYNC */
};
};
sdmmc {
sdmmc_clk: sdmmc-clk {
rockchip,pins =
<6 RK_PC4 1 &pcfg_pull_none>;
};
sdmmc_cmd: sdmmc-cmd {
rockchip,pins =
<6 RK_PC5 1 &pcfg_pull_up>;
};
sdmmc_cd: sdmmc-cd {
rockchip,pins =
<6 RK_PC6 1 &pcfg_pull_up>;
};
sdmmc_bus1: sdmmc-bus1 {
rockchip,pins =
<6 RK_PC0 1 &pcfg_pull_up>;
};
sdmmc_bus4: sdmmc-bus4 {
rockchip,pins =
<6 RK_PC0 1 &pcfg_pull_up>,
<6 RK_PC1 1 &pcfg_pull_up>,
<6 RK_PC2 1 &pcfg_pull_up>,
<6 RK_PC3 1 &pcfg_pull_up>;
};
};
sdio0 {
sdio0_bus1: sdio0-bus1 {
rockchip,pins =
<4 RK_PC4 1 &pcfg_pull_up>;
};
sdio0_bus4: sdio0-bus4 {
rockchip,pins =
<4 RK_PC4 1 &pcfg_pull_up>,
<4 RK_PC5 1 &pcfg_pull_up>,
<4 RK_PC6 1 &pcfg_pull_up>,
<4 RK_PC7 1 &pcfg_pull_up>;
};
sdio0_cmd: sdio0-cmd {
rockchip,pins =
<4 RK_PD0 1 &pcfg_pull_up>;
};
sdio0_clk: sdio0-clk {
rockchip,pins =
<4 RK_PD1 1 &pcfg_pull_none>;
};
sdio0_cd: sdio0-cd {
rockchip,pins =
<4 RK_PD2 1 &pcfg_pull_up>;
};
sdio0_wp: sdio0-wp {
rockchip,pins =
<4 RK_PD3 1 &pcfg_pull_up>;
};
sdio0_pwr: sdio0-pwr {
rockchip,pins =
<4 RK_PD4 1 &pcfg_pull_up>;
};
sdio0_bkpwr: sdio0-bkpwr {
rockchip,pins =
<4 RK_PD5 1 &pcfg_pull_up>;
};
sdio0_int: sdio0-int {
rockchip,pins =
<4 RK_PD6 1 &pcfg_pull_up>;
};
};
sdio1 {
sdio1_bus1: sdio1-bus1 {
rockchip,pins =
<3 RK_PD0 4 &pcfg_pull_up>;
};
sdio1_bus4: sdio1-bus4 {
rockchip,pins =
<3 RK_PD0 4 &pcfg_pull_up>,
<3 RK_PD1 4 &pcfg_pull_up>,
<3 RK_PD2 4 &pcfg_pull_up>,
<3 RK_PD3 4 &pcfg_pull_up>;
};
sdio1_cd: sdio1-cd {
rockchip,pins =
<3 RK_PD4 4 &pcfg_pull_up>;
};
sdio1_wp: sdio1-wp {
rockchip,pins =
<3 RK_PD5 4 &pcfg_pull_up>;
};
sdio1_bkpwr: sdio1-bkpwr {
rockchip,pins =
<3 RK_PD6 4 &pcfg_pull_up>;
};
sdio1_int: sdio1-int {
rockchip,pins =
<3 RK_PD7 4 &pcfg_pull_up>;
};
sdio1_cmd: sdio1-cmd {
rockchip,pins =
<4 RK_PA6 4 &pcfg_pull_up>;
};
sdio1_clk: sdio1-clk {
rockchip,pins =
<4 RK_PA7 4 &pcfg_pull_none>;
};
sdio1_pwr: sdio1-pwr {
rockchip,pins =
<4 RK_PB1 4 &pcfg_pull_up>;
};
};
emmc {
emmc_clk: emmc-clk {
rockchip,pins =
<3 RK_PC2 2 &pcfg_pull_none>;
};
emmc_cmd: emmc-cmd {
rockchip,pins =
<3 RK_PC0 2 &pcfg_pull_up>;
};
emmc_pwr: emmc-pwr {
rockchip,pins =
<3 RK_PB1 2 &pcfg_pull_up>;
};
emmc_bus1: emmc-bus1 {
rockchip,pins =
<3 RK_PA0 2 &pcfg_pull_up>;
};
emmc_bus4: emmc-bus4 {
rockchip,pins =
<3 RK_PA0 2 &pcfg_pull_up>,
<3 RK_PA1 2 &pcfg_pull_up>,
<3 RK_PA2 2 &pcfg_pull_up>,
<3 RK_PA3 2 &pcfg_pull_up>;
};
emmc_bus8: emmc-bus8 {
rockchip,pins =
<3 RK_PA0 2 &pcfg_pull_up>,
<3 RK_PA1 2 &pcfg_pull_up>,
<3 RK_PA2 2 &pcfg_pull_up>,
<3 RK_PA3 2 &pcfg_pull_up>,
<3 RK_PA4 2 &pcfg_pull_up>,
<3 RK_PA5 2 &pcfg_pull_up>,
<3 RK_PA6 2 &pcfg_pull_up>,
<3 RK_PA7 2 &pcfg_pull_up>;
};
};
spi0 {
spi0_clk: spi0-clk {
rockchip,pins =
<5 RK_PB4 1 &pcfg_pull_up>;
};
spi0_cs0: spi0-cs0 {
rockchip,pins =
<5 RK_PB5 1 &pcfg_pull_up>;
};
spi0_tx: spi0-tx {
rockchip,pins =
<5 RK_PB6 1 &pcfg_pull_up>;
};
spi0_rx: spi0-rx {
rockchip,pins =
<5 RK_PB7 1 &pcfg_pull_up>;
};
spi0_cs1: spi0-cs1 {
rockchip,pins =
<5 RK_PC0 1 &pcfg_pull_up>;
};
};
spi1 {
spi1_clk: spi1-clk {
rockchip,pins =
<7 RK_PB4 2 &pcfg_pull_up>;
};
spi1_cs0: spi1-cs0 {
rockchip,pins =
<7 RK_PB5 2 &pcfg_pull_up>;
};
spi1_rx: spi1-rx {
rockchip,pins =
<7 RK_PB6 2 &pcfg_pull_up>;
};
spi1_tx: spi1-tx {
rockchip,pins =
<7 RK_PB7 2 &pcfg_pull_up>;
};
};
spi2 {
spi2_cs1: spi2-cs1 {
rockchip,pins =
<8 RK_PA3 1 &pcfg_pull_up>;
};
spi2_clk: spi2-clk {
rockchip,pins =
<8 RK_PA6 1 &pcfg_pull_up>;
};
spi2_cs0: spi2-cs0 {
rockchip,pins =
<8 RK_PA7 1 &pcfg_pull_up>;
};
spi2_rx: spi2-rx {
rockchip,pins =
<8 RK_PB0 1 &pcfg_pull_up>;
};
spi2_tx: spi2-tx {
rockchip,pins =
<8 RK_PB1 1 &pcfg_pull_up>;
};
};
uart0 {
uart0_xfer: uart0-xfer {
rockchip,pins =
<4 RK_PC0 1 &pcfg_pull_up>,
<4 RK_PC1 1 &pcfg_pull_up>;
};
uart0_cts: uart0-cts {
rockchip,pins =
<4 RK_PC2 1 &pcfg_pull_up>;
};
uart0_rts: uart0-rts {
rockchip,pins =
<4 RK_PC3 1 &pcfg_pull_none>;
};
};
uart1 {
uart1_xfer: uart1-xfer {
rockchip,pins =
<5 RK_PB0 1 &pcfg_pull_up>,
<5 RK_PB1 1 &pcfg_pull_up>;
};
uart1_cts: uart1-cts {
rockchip,pins =
<5 RK_PB2 1 &pcfg_pull_up>;
};
uart1_rts: uart1-rts {
rockchip,pins =
<5 RK_PB3 1 &pcfg_pull_none>;
};
};
uart2 {
uart2_xfer: uart2-xfer {
rockchip,pins =
<7 RK_PC6 1 &pcfg_pull_up>,
<7 RK_PC7 1 &pcfg_pull_up>;
};
/* no rts / cts for uart2 */
};
uart3 {
uart3_xfer: uart3-xfer {
rockchip,pins =
<7 RK_PA7 1 &pcfg_pull_up>,
<7 RK_PB0 1 &pcfg_pull_up>;
};
uart3_cts: uart3-cts {
rockchip,pins =
<7 RK_PB1 1 &pcfg_pull_up>;
};
uart3_rts: uart3-rts {
rockchip,pins =
<7 RK_PB2 1 &pcfg_pull_none>;
};
};
uart4 {
uart4_xfer: uart4-xfer {
rockchip,pins =
<5 RK_PB7 3 &pcfg_pull_up>,
<5 RK_PB6 3 &pcfg_pull_up>;
};
uart4_cts: uart4-cts {
rockchip,pins =
<5 RK_PB4 3 &pcfg_pull_up>;
};
uart4_rts: uart4-rts {
rockchip,pins =
<5 RK_PB5 3 &pcfg_pull_none>;
};
};
tsadc {
otp_pin: otp-pin {
rockchip,pins =
<0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
};
otp_out: otp-out {
rockchip,pins =
<0 RK_PB2 1 &pcfg_pull_none>;
};
};
pwm0 {
pwm0_pin: pwm0-pin {
rockchip,pins =
<7 RK_PA0 1 &pcfg_pull_none>;
};
pwm0_pin_pull_down: pwm0-pin-pull-down {
rockchip,pins =
<7 RK_PA0 1 &pcfg_pull_down>;
};
};
pwm1 {
pwm1_pin: pwm1-pin {
rockchip,pins =
<7 RK_PA1 1 &pcfg_pull_none>;
};
pwm1_pin_pull_down: pwm1-pin-pull-down {
rockchip,pins =
<7 RK_PA1 1 &pcfg_pull_down>;
};
};
pwm2 {
pwm2_pin: pwm2-pin {
rockchip,pins =
<7 RK_PC6 3 &pcfg_pull_none>;
};
pwm2_pin_pull_down: pwm2-pin-pull-down {
rockchip,pins =
<7 RK_PC6 3 &pcfg_pull_down>;
};
};
pwm3 {
pwm3_pin: pwm3-pin {
rockchip,pins =
<7 RK_PC7 3 &pcfg_pull_none>;
};
pwm3_pin_pull_down: pwm3-pin-pull-down {
rockchip,pins =
<7 RK_PC7 3 &pcfg_pull_down>;
};
};
gmac {
rgmii_pins: rgmii-pins {
rockchip,pins =
<3 RK_PD6 3 &pcfg_pull_none>,
<3 RK_PD7 3 &pcfg_pull_none>,
<3 RK_PD2 3 &pcfg_pull_none>,
<3 RK_PD3 3 &pcfg_pull_none>,
<3 RK_PD4 3 &pcfg_pull_none_drv_level_12>,
<3 RK_PD5 3 &pcfg_pull_none_drv_level_12>,
<3 RK_PD0 3 &pcfg_pull_none_drv_level_12>,
<3 RK_PD1 3 &pcfg_pull_none_drv_level_12>,
<4 RK_PA0 3 &pcfg_pull_none>,
<4 RK_PA5 3 &pcfg_pull_none>,
<4 RK_PA6 3 &pcfg_pull_none>,
<4 RK_PB1 3 &pcfg_pull_none_drv_level_12>,
<4 RK_PA4 3 &pcfg_pull_none_drv_level_12>,
<4 RK_PA1 3 &pcfg_pull_none>,
<4 RK_PA3 3 &pcfg_pull_none>;
};
rmii_pins: rmii-pins {
rockchip,pins =
<3 RK_PD6 3 &pcfg_pull_none>,
<3 RK_PD7 3 &pcfg_pull_none>,
<3 RK_PD4 3 &pcfg_pull_none>,
<3 RK_PD5 3 &pcfg_pull_none>,
<4 RK_PA0 3 &pcfg_pull_none>,
<4 RK_PA5 3 &pcfg_pull_none>,
<4 RK_PA4 3 &pcfg_pull_none>,
<4 RK_PA1 3 &pcfg_pull_none>,
<4 RK_PA2 3 &pcfg_pull_none>,
<4 RK_PA3 3 &pcfg_pull_none>;
};
};
spdif {
spdif_tx: spdif-tx {
rockchip,pins =
<6 RK_PB3 1 &pcfg_pull_none>;
};
};
isp_pin {
isp_mipi: isp-mipi {
rockchip,pins =
/* cif_clkout */
<2 RK_PB3 1 &pcfg_pull_none>;
};
isp_dvp_d2d9: isp-d2d9 {
rockchip,pins =
/* cif_data2 ... cif_data9 */
<2 RK_PA0 1 &pcfg_pull_none>,
<2 RK_PA1 1 &pcfg_pull_none>,
<2 RK_PA2 1 &pcfg_pull_none>,
<2 RK_PA3 1 &pcfg_pull_none>,
<2 RK_PA4 1 &pcfg_pull_none>,
<2 RK_PA5 1 &pcfg_pull_none>,
<2 RK_PA6 1 &pcfg_pull_none>,
<2 RK_PA7 1 &pcfg_pull_none>,
/* cif_sync, cif_href */
<2 RK_PB0 1 &pcfg_pull_none>,
<2 RK_PB1 1 &pcfg_pull_none>,
/* cif_clkin */
<2 RK_PB2 1 &pcfg_pull_none>;
};
isp_dvp_d0d1: isp-d0d1 {
rockchip,pins =
/* cif_data0, cif_data1 */
<2 RK_PB4 1 &pcfg_pull_none>,
<2 RK_PB5 1 &pcfg_pull_none>;
};
isp_dvp_d10d11: isp-d10d11 {
rockchip,pins =
/* cif_data10, cif_data11 */
<2 RK_PB6 1 &pcfg_pull_none>,
<2 RK_PB7 1 &pcfg_pull_none>;
};
isp_dvp_d0d7: isp-d0d7 {
rockchip,pins =
/* cif_data0 ... cif_data7 */
<2 RK_PB4 1 &pcfg_pull_none>,
<2 RK_PB5 1 &pcfg_pull_none>,
<2 RK_PA0 1 &pcfg_pull_none>,
<2 RK_PA1 1 &pcfg_pull_none>,
<2 RK_PA2 1 &pcfg_pull_none>,
<2 RK_PA3 1 &pcfg_pull_none>,
<2 RK_PA4 1 &pcfg_pull_none>,
<2 RK_PA5 1 &pcfg_pull_none>;
};
isp_shutter: isp-shutter {
rockchip,pins =
/* SHUTTEREN, SHUTTERTRIG */
<7 RK_PB4 2 &pcfg_pull_none>,
<7 RK_PB7 2 &pcfg_pull_none>;
};
isp_flash_trigger: isp-flash-trigger {
rockchip,pins =
/* ISP_FLASHTRIGOU */
<7 RK_PB5 2 &pcfg_pull_none>;
};
isp_prelight: isp-prelight {
rockchip,pins =
/* ISP_PRELIGHTTRIG */
<7 RK_PB6 2 &pcfg_pull_none>;
};
isp_flash_trigger_as_gpio: isp-flash-trigger-as-gpio {
rockchip,pins =
/* ISP_FLASHTRIGOU */
<7 RK_PB5 2 &pcfg_pull_none>;
};
};
cif_pin {
cif_dvp_d0d1: cif-dvp-d0d1 {
rockchip,pins =
<2 RK_PB4 1 &pcfg_pull_none>, /* cif_data0 */
<2 RK_PB5 1 &pcfg_pull_none>; /* cif_data1 */
};
cif_dvp_d2d9: cif-dvp-d2d9 {
rockchip,pins =
<2 RK_PA0 1 &pcfg_pull_none>, /* cif_data2 */
<2 RK_PA1 1 &pcfg_pull_none>, /* cif_data3 */
<2 RK_PA2 1 &pcfg_pull_none>, /* cif_data4 */
<2 RK_PA3 1 &pcfg_pull_none>, /* cif_data5 */
<2 RK_PA4 1 &pcfg_pull_none>, /* cif_data6 */
<2 RK_PA5 1 &pcfg_pull_none>, /* cif_data7 */
<2 RK_PA6 1 &pcfg_pull_none>, /* cif_data8 */
<2 RK_PA7 1 &pcfg_pull_none>, /* cif_data9 */
<2 RK_PB0 1 &pcfg_pull_none>, /* cif_sync */
<2 RK_PB1 1 &pcfg_pull_none>, /* cif_href */
<2 RK_PB2 1 &pcfg_pull_none>, /* cif_clkin */
<2 RK_PB3 1 &pcfg_pull_none>; /* cif_clkout */
};
cif_dvp_d10d11: cif-dvp-d10d11 {
rockchip,pins =
<2 RK_PB6 1 &pcfg_pull_none>, /* cif_data10 */
<2 RK_PB7 1 &pcfg_pull_none>; /* cif_data11 */
};
};
};

1067
arch/arm/boot/dts/rk3288.dtsi
View File

File diff suppressed because it is too large Load Diff

7
arch/arm/boot/dts/rv1106-pinctrl.dtsi
View File

@@ -734,6 +734,13 @@
};
sdmmc1 {
/omit-if-no-ref/
sdmmc1m0_bus1: sdmmc1m0-bus1 {
rockchip,pins =
/* sdmmc1_d0_m0 */
<2 RK_PA1 1 &pcfg_pull_up_drv_level_2>;
};
/omit-if-no-ref/
sdmmc1m0_bus4: sdmmc1m0-bus4 {
rockchip,pins =

18
arch/arm/boot/dts/rv1106-smd-cam.dtsi
View File

@@ -9,6 +9,8 @@
/ {
vcc1v2_dvdd: vcc1v8_dovdd: vcc2v8_avdd: vcc-camera {
compatible = "regulator-fixed";
regulator-boot-on;
regulator-always-on;
regulator-name = "vcc_camera";
pinctrl-names = "default";
pinctrl-0 = <&cam_pwren>;
@@ -151,6 +153,8 @@
};
&i2c4 {
rockchip,amp-shared;
status = "okay";
clock-frequency = <400000>;
pinctrl-names = "default";
@@ -227,6 +231,7 @@
&rkcif_mipi_lvds {
status = "okay";
memory-region-thunderboot = <&rkisp_thunderboot>;
port {
/* MIPI CSI-2 endpoint */
cif_mipi0_in: endpoint {
@@ -313,6 +318,19 @@
max-input = <1920 1280 30>;
};
&mailbox {
status = "okay";
};
&thunder_boot_service {
status = "okay";
};
&rkisp_thunderboot {
/* vicap, capture raw10, ceil(w*10/8/256)*256*h *4(buf num) */
reg = <0x00860000 0xa8c000>;
};
&rkisp_vir0 {
status = "okay";

7
arch/arm/boot/dts/rv1106.dtsi
View File

@@ -810,13 +810,12 @@
compatible = "rockchip,rv1106-codec";
reg = <0xff480000 0x1000>;
rockchip,grf = <&grf>;
clocks = <&cru PCLK_ACODEC>,
<&cru MCLK_ACODEC_TX>,
<&cru MCLK_I2S0_8CH_TX>;
clock-names = "pclk_acodec", "mclk_acodec", "mclk_cpu";
clocks = <&cru PCLK_ACODEC>, <&cru MCLK_ACODEC_TX>;
clock-names = "pclk_acodec", "mclk_acodec";
resets = <&cru SRST_P_ACODEC>;
reset-names = "acodec-reset";
acodec,micbias;
init-mic-gain = <0x22>; /* Left:20dB Right:20dB */
status = "disabled";
};

1
arch/arm/boot/dts/rv1106g-evb1-v11-cvr.dts
View File

@@ -6,7 +6,6 @@
/dts-v1/;
#include "rv1106g-evb1-v11.dts"
#include "rv1106-evb-ext-rgb-v10.dtsi"
/ {
model = "Rockchip RV1106G EVB1 V11 Board For CVR";

283
arch/arm/boot/dts/rv1106g-evb2-v11-emmc.dts Normal file
View File

@@ -0,0 +1,283 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2022 Rockchip Electronics Co., Ltd.
*/
/dts-v1/;
#include "rv1106.dtsi"
#include "rv1106-evb-v10.dtsi"
#include "rv1106-thunder-boot-emmc.dtsi"
/ {
model = "Rockchip RV1106G EVB2 V11 EMMC Board";
compatible = "rockchip,rv1106g-evb2-v11-emmc", "rockchip,rv1106";
chosen {
bootargs = "loglevel=0 rootfstype=erofs rootflags=dax console=ttyFIQ0 root=/dev/rd0 snd_soc_core.prealloc_buffer_size_kbytes=16 coherent_pool=0 driver_async_probe=dwmmc_rockchip";
};
vcc_1v8: vcc-1v8 {
compatible = "regulator-fixed";
regulator-name = "vcc_1v8";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
vcc_3v3: vcc-3v3 {
compatible = "regulator-fixed";
regulator-name = "vcc_3v3";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
vcc3v3_sd: vcc3v3-sd {
compatible = "regulator-fixed";
gpio = <&gpio2 RK_PA7 GPIO_ACTIVE_LOW>;
regulator-name = "vcc3v3_sd";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc_pwren>;
};
};
&csi2_dphy_hw {
status = "okay";
};
&csi2_dphy0 {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
csi_dphy_input0: endpoint@0 {
reg = <0>;
remote-endpoint = <&sc3338_out>;
data-lanes = <1 2>;
};
};
port@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
csi_dphy_output: endpoint@0 {
reg = <0>;
remote-endpoint = <&mipi_csi2_input>;
};
};
};
};
&emmc {
status = "okay";
};
&fiq_debugger {
rockchip,baudrate = <1500000>;
pinctrl-names = "default";
pinctrl-0 = <&uart2m1_xfer>;
};
&i2c4 {
rockchip,amp-shared;
sc3338: sc3338@30 {
compatible = "smartsens,sc3338";
status = "okay";
reg = <0x30>;
clocks = <&cru MCLK_REF_MIPI0>;
clock-names = "xvclk";
pwdn-gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&mipi_refclk_out0>;
rockchip,camera-module-index = <0>;
rockchip,camera-module-facing = "back";
rockchip,camera-module-name = "FKO1";
rockchip,camera-module-lens-name = "30IRC-F16";
port {
sc3338_out: endpoint {
remote-endpoint = <&csi_dphy_input0>;
data-lanes = <1 2>;
};
};
};
};
&mipi0_csi2 {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
mipi_csi2_input: endpoint@1 {
reg = <1>;
remote-endpoint = <&csi_dphy_output>;
};
};
port@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
mipi_csi2_output: endpoint@0 {
reg = <0>;
remote-endpoint = <&cif_mipi_in>;
};
};
};
};
&mailbox {
status = "okay";
};
&rkcif {
status = "okay";
};
&rkcif_mipi_lvds {
status = "okay";
memory-region-thunderboot = <&rkisp_thunderboot>;
pinctrl-names = "default";
pinctrl-0 = <&mipi_pins>;
port {
/* MIPI CSI-2 endpoint */
cif_mipi_in: endpoint {
remote-endpoint = <&mipi_csi2_output>;
};
};
};
&rkcif_mipi_lvds_sditf {
status = "okay";
port {
/* MIPI CSI-2 endpoint */
mipi_lvds_sditf: endpoint {
remote-endpoint = <&isp_in>;
};
};
};
&rkisp {
status = "okay";
};
&rkisp_vir0 {
status = "okay";
port@0 {
isp_in: endpoint {
remote-endpoint = <&mipi_lvds_sditf>;
};
};
};
&thunder_boot_service {
status = "okay";
};
&rkisp_thunderboot {
/* reg's offset MUST match with RTOS */
/*
* vicap, capture raw10, ceil(w*10/8/256)*256*h *4(buf num)
* e.g. 2304x1296: 0xf30000
*/
reg = <0x00860000 0xf30000>;
};
&ramdisk_r {
reg = <0x1790000 (20 * 0x00100000)>;
};
&ramdisk_c {
reg = <0x2b90000 (10 * 0x00100000)>;
};
&pinctrl {
sdmmc {
/omit-if-no-ref/
sdmmc_pwren: sdmmc-pwren {
rockchip,pins = <2 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
};
&pwm10 {
status = "okay";
};
&pwm11 {
status = "okay";
};
&sdio {
max-frequency = <50000000>;
bus-width = <1>;
cap-sd-highspeed;
cap-sdio-irq;
keep-power-in-suspend;
non-removable;
rockchip,default-sample-phase = <90>;
no-sd;
no-mmc;
supports-sdio;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc1m0_cmd &sdmmc1m0_clk &sdmmc1m0_bus4>;
status = "okay";
};
&sdmmc {
max-frequency = <200000000>;
no-sdio;
no-mmc;
bus-width = <4>;
cap-mmc-highspeed;
cap-sd-highspeed;
disable-wp;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_det &sdmmc0_bus4>;
vmmc-supply = <&vcc3v3_sd>;
status = "okay";
};
&sfc {
assigned-clocks = <&cru SCLK_SFC>;
assigned-clock-rates = <125000000>;
status = "disabled";
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <125000000>;
spi-rx-bus-width = <4>;
spi-tx-bus-width = <1>;
};
};
&usbdrd_dwc3 {
dr_mode = "peripheral";
};

5
arch/arm/boot/dts/rv1106g-smart-door-lock-rmsl-v10.dts
View File

@@ -14,6 +14,7 @@
model = "Rockchip RV1106G Smart Door Lock RMSL V10 Board";
compatible = "rockchip,rv1106g-smart-door-lock-rmsl-v10", "rockchip,rv1106";
/* rkaiq_prd_type: 1 for one camera, 2 for multi camera */
chosen {
bootargs = "loglevel=0 rootfstype=erofs rootflags=dax console=ttyFIQ0 root=/dev/rd0 snd_soc_core.prealloc_buffer_size_kbytes=16 coherent_pool=0 driver_async_probe=dwmmc_rockchip";
};
@@ -146,6 +147,10 @@
};
};
&thunder_boot_service {
status = "okay";
};
&u2phy_otg {
status = "okay";
};

37
arch/arm/boot/dts/rv1106g-smart-door-lock-rmsl-v12.dts Normal file
View File

@@ -0,0 +1,37 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2022 Rockchip Electronics Co., Ltd.
*/
/dts-v1/;
#include "rv1106g-smart-door-lock-rmsl-v10.dts"
/ {
model = "Rockchip RV1106G Smart Door Lock RMSL V12 Board";
compatible = "rockchip,rv1106g-smart-door-lock-rmsl-v12", "rockchip,rv1106";
};
&sdio {
max-frequency = <50000000>;
bus-width = <1>;
cap-sd-highspeed;
cap-sdio-irq;
keep-power-in-suspend;
non-removable;
rockchip,default-sample-phase = <90>;
no-mmc;
no-sd;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc1m0_cmd &sdmmc1m0_clk &sdmmc1m0_bus1>;
status = "okay";
};
&sdmmc {
status = "disabled";
};
&vcsel_rk803 {
gpio-encc1-gpios = <&gpio2 RK_PA7 GPIO_ACTIVE_HIGH>; //Flood
gpio-encc2-gpios = <&gpio2 RK_PA0 GPIO_ACTIVE_HIGH>; //PRO
};

281
arch/arm/configs/rk3126_linux.config Normal file
View File

@@ -0,0 +1,281 @@
# CONFIG_ALLOW_DEV_COREDUMP is not set
# CONFIG_ASHMEM is not set
# CONFIG_BATTERY_SBS is not set
# CONFIG_BLK_CGROUP is not set
# CONFIG_BLK_DEV_IO_TRACE is not set
# CONFIG_BT is not set
# CONFIG_BUG_ON_DATA_CORRUPTION is not set
# CONFIG_CGROUP_CPUACCT is not set
# CONFIG_CGROUP_DEVICE is not set
# CONFIG_CGROUP_FREEZER is not set
# CONFIG_CGROUP_SCHED is not set
# CONFIG_CHARGER_BQ24735 is not set
# CONFIG_CHARGER_GPIO is not set
# CONFIG_CPUSETS is not set
# CONFIG_CPU_FREQ_STAT is not set
# CONFIG_CPU_FREQ_TIMES is not set
# CONFIG_CPU_RK3036 is not set
# CONFIG_CPU_RK30XX is not set
# CONFIG_CPU_RK3188 is not set
# CONFIG_CPU_RK322X is not set
# CONFIG_CPU_RK3288 is not set
# CONFIG_CRC7 is not set
# CONFIG_CRC_ITU_T is not set
# CONFIG_CRC_T10DIF is not set
# CONFIG_CRYPTO_CFB is not set
# CONFIG_CRYPTO_CRCT10DIF is not set
# CONFIG_CRYPTO_DES is not set
# CONFIG_CRYPTO_ECB is not set
# CONFIG_CRYPTO_ECDH is not set
# CONFIG_CRYPTO_HW is not set
# CONFIG_CRYPTO_MICHAEL_MIC is not set
# CONFIG_CRYPTO_OFB is not set
# CONFIG_CRYPTO_SHA1 is not set
# CONFIG_CRYPTO_SHA512 is not set
# CONFIG_CRYPTO_SM3 is not set
# CONFIG_CRYPTO_SM4 is not set
# CONFIG_CRYPTO_USER_API_HASH is not set
# CONFIG_CRYPTO_USER_API_SKCIPHER is not set
# CONFIG_CRYPTO_XTS is not set
# CONFIG_DEBUG_CREDENTIALS is not set
CONFIG_DEBUG_GPIO=y
# CONFIG_DEBUG_INFO is not set
# CONFIG_DEBUG_LIST is not set
# CONFIG_DEBUG_SPINLOCK is not set
# CONFIG_DNS_RESOLVER is not set
# CONFIG_DRM_IGNORE_IOTCL_PERMIT is not set
# CONFIG_DRM_LOAD_EDID_FIRMWARE is not set
# CONFIG_ECRYPT_FS is not set
# CONFIG_ETHERNET is not set
# CONFIG_FB_MODE_HELPERS is not set
# CONFIG_FIQ_DEBUGGER_TRUST_ZONE is not set
# CONFIG_FUNCTION_TRACER is not set
# CONFIG_HFSPLUS_FS is not set
# CONFIG_HID_APPLE is not set
# CONFIG_HID_BATTERY_STRENGTH is not set
# CONFIG_HID_CHERRY is not set
# CONFIG_HID_KENSINGTON is not set
# CONFIG_HID_MAGICMOUSE is not set
# CONFIG_HID_MICROSOFT is not set
# CONFIG_HID_MULTITOUCH is not set
# CONFIG_HID_PLANTRONICS is not set
# CONFIG_HID_PRIMAX is not set
# CONFIG_HID_RMI is not set
# CONFIG_HOSTAP is not set
# CONFIG_HWMON is not set
# CONFIG_I2C_HID is not set
# CONFIG_I2C_STUB is not set
# CONFIG_IKCONFIG is not set
# CONFIG_INITRD_ASYNC is not set
# CONFIG_INPUT_FF_MEMLESS is not set
# CONFIG_INPUT_JOYDEV is not set
# CONFIG_INPUT_JOYSTICK is not set
# CONFIG_INPUT_TABLET is not set
# CONFIG_INPUT_UINPUT is not set
# CONFIG_IOSCHED_BFQ is not set
# CONFIG_IPV6 is not set
# CONFIG_ISO9660_FS is not set
# CONFIG_KERNEL_GZIP is not set
CONFIG_KERNEL_LZ4=y
# CONFIG_KEYBOARD_GPIO is not set
# CONFIG_KEYBOARD_GPIO_POLLED is not set
# CONFIG_MAC80211_DEBUGFS is not set
# CONFIG_MAC80211_DEBUG_MENU is not set
# CONFIG_MAC_PARTITION is not set
# CONFIG_MALI_MIDGARD is not set
# CONFIG_MDIO_DEVICE is not set
# CONFIG_MEDIA_CEC_SUPPORT is not set
# CONFIG_MEDIA_USB_SUPPORT is not set
# CONFIG_MFD_TPS6586X is not set
# CONFIG_MFD_TPS65910 is not set
# CONFIG_MMC_TEST is not set
# CONFIG_MODULE_FORCE_LOAD is not set
# CONFIG_MODULE_FORCE_UNLOAD is not set
# CONFIG_MOUSE_CYAPA is not set
# CONFIG_MOUSE_ELAN_I2C is not set
# CONFIG_MWIFIEX is not set
CONFIG_NAMESPACES=y
# CONFIG_NETFILTER is not set
# CONFIG_NETWORK_FILESYSTEMS is not set
# CONFIG_NET_KEY is not set
# CONFIG_NEW_LEDS is not set
# CONFIG_NL80211_TESTMODE is not set
# CONFIG_NLS_ASCII is not set
CONFIG_NLS_DEFAULT="iso8859-1"
# CONFIG_NLS_UTF8 is not set
# CONFIG_PHYLIB is not set
# CONFIG_PHY_ROCKCHIP_DP is not set
# CONFIG_PHY_ROCKCHIP_INNO_HDMI is not set
# CONFIG_PHY_ROCKCHIP_USB is not set
# CONFIG_PINCTRL_RK805 is not set
# CONFIG_PM_DEBUG is not set
# CONFIG_POWER_RESET_GPIO_RESTART is not set
# CONFIG_PPS is not set
# CONFIG_PSI is not set
# CONFIG_PTP_1588_CLOCK is not set
# CONFIG_RD_XZ is not set
# CONFIG_REGULATOR_ACT8865 is not set
# CONFIG_REGULATOR_FAN53555 is not set
# CONFIG_RELAY is not set
# CONFIG_RFKILL_RK is not set
CONFIG_RK_CONSOLE_THREAD=y
CONFIG_RK_HEADSET=y
# CONFIG_RMI4_CORE is not set
# CONFIG_ROCKCHIP_ANALOGIX_DP is not set
# CONFIG_ROCKCHIP_DDRCLK_SIP_V2 is not set
# CONFIG_ROCKCHIP_DW_HDMI is not set
# CONFIG_ROCKCHIP_INNO_HDMI is not set
# CONFIG_ROCKCHIP_MPP_RKVDEC is not set
# CONFIG_ROCKCHIP_MPP_RKVENC is not set
# CONFIG_ROCKCHIP_MPP_VDPU2 is not set
# CONFIG_ROCKCHIP_MPP_VEPU2 is not set
# CONFIG_ROCKCHIP_PLL_RK3066 is not set
# CONFIG_ROCKCHIP_VENDOR_STORAGE_UPDATE_LOADER is not set
# CONFIG_RT2X00 is not set
# CONFIG_RTC_DRV_HYM8563 is not set
CONFIG_RUNTIME_TESTING_MENU=y
# CONFIG_SCHED_DEBUG is not set
# CONFIG_SCHED_STACK_END_CHECK is not set
# CONFIG_SECURITY is not set
# CONFIG_SECURITYFS is not set
# CONFIG_SENSORS_ISL29018 is not set
# CONFIG_SENSORS_TSL2563 is not set
CONFIG_SENSOR_DEVICE=y
# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set
# CONFIG_SERIAL_OF_PLATFORM is not set
# CONFIG_SLUB_DEBUG is not set
# CONFIG_SND_SOC_ES8323 is not set
# CONFIG_SND_SOC_ES8396 is not set
# CONFIG_SND_SOC_ROCKCHIP_MAX98090 is not set
# CONFIG_SND_SOC_ROCKCHIP_RT5645 is not set
# CONFIG_SND_SOC_RT5616 is not set
# CONFIG_SND_SOC_RT5640 is not set
# CONFIG_SND_SOC_TS3A227E is not set
# CONFIG_SND_USB_AUDIO is not set
# CONFIG_SPI_SPIDEV is not set
CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU=y
# CONFIG_SQUASHFS_DECOMP_SINGLE is not set
CONFIG_STAGING_MEDIA=y
# CONFIG_TCG_TPM is not set
# CONFIG_TEE is not set
# CONFIG_TMPFS_POSIX_ACL is not set
# CONFIG_TMPFS_XATTR is not set
# CONFIG_TOUCHSCREEN_ATMEL_MXT is not set
# CONFIG_TOUCHSCREEN_ELAN is not set
# CONFIG_TOUCHSCREEN_GSL3673 is not set
# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
# CONFIG_TSL2583 is not set
# CONFIG_UDF_FS is not set
# CONFIG_UNWINDER_FRAME_POINTER is not set
# CONFIG_USB_ACM is not set
# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
# CONFIG_USB_CONFIGFS_ACM is not set
CONFIG_USB_DEFAULT_PERSIST=y
# CONFIG_USB_EHCI_ROOT_HUB_TT is not set
# CONFIG_USB_EZUSB_FX2 is not set
# CONFIG_USB_HIDDEV is not set
# CONFIG_USB_MON is not set
# CONFIG_USB_NET_RNDIS_WLAN is not set
# CONFIG_USB_OTG is not set
# CONFIG_USB_PEGASUS is not set
# CONFIG_USB_RTL8150 is not set
# CONFIG_USB_RTL8152 is not set
# CONFIG_USB_SERIAL is not set
# CONFIG_USB_USBNET is not set
# CONFIG_USB_WDM is not set
# CONFIG_V4L_TEST_DRIVERS is not set
CONFIG_VIDEO_GC2145=y
# CONFIG_VIDEO_IMX219 is not set
# CONFIG_VIDEO_OV13850 is not set
# CONFIG_VIDEO_OV5647 is not set
# CONFIG_VIDEO_OV8858 is not set
# CONFIG_VIDEO_SGM3784 is not set
CONFIG_WIFI_GENERATE_RANDOM_MAC_ADDR=y
# CONFIG_XZ_DEC is not set
# CONFIG_ANGLE_DEVICE is not set
CONFIG_ARM_UNWIND=y
# CONFIG_ATOMIC64_SELFTEST is not set
# CONFIG_BACKTRACE_SELF_TEST is not set
# CONFIG_BMA2XX_ACC is not set
# CONFIG_COMPASS_DEVICE is not set
CONFIG_ENABLE_DEFAULT_TRACERS=y
# CONFIG_FIND_BIT_BENCHMARK is not set
CONFIG_GSENSOR_DEVICE=y
# CONFIG_GS_BMA023 is not set
# CONFIG_GS_DA215S is not set
# CONFIG_GS_DA223 is not set
# CONFIG_GS_DA228E is not set
# CONFIG_GS_DMT10 is not set
# CONFIG_GS_KXTIK is not set
# CONFIG_GS_KXTJ9 is not set
# CONFIG_GS_LIS3DH is not set
# CONFIG_GS_LSM303D is not set
# CONFIG_GS_MC3230 is not set
CONFIG_GS_MMA7660=y
# CONFIG_GS_MMA8452 is not set
# CONFIG_GS_MXC6225 is not set
# CONFIG_GS_MXC6655XA is not set
# CONFIG_GS_SC7660 is not set
# CONFIG_GS_SC7A20 is not set
# CONFIG_GS_SC7A30 is not set
# CONFIG_GYROSCOPE_DEVICE is not set
# CONFIG_HALL_DEVICE is not set
# CONFIG_ICM2060X_ACC is not set
CONFIG_INLINE_READ_UNLOCK=y
CONFIG_INLINE_READ_UNLOCK_IRQ=y
CONFIG_INLINE_SPIN_UNLOCK_IRQ=y
CONFIG_INLINE_WRITE_UNLOCK=y
CONFIG_INLINE_WRITE_UNLOCK_IRQ=y
# CONFIG_INTERVAL_TREE_TEST is not set
CONFIG_IPC_NS=y
# CONFIG_LIGHT_DEVICE is not set
# CONFIG_LKDTM is not set
# CONFIG_LSM330_ACC is not set
# CONFIG_MPU6500_ACC is not set
# CONFIG_MPU6880_ACC is not set
CONFIG_NET_NS=y
# CONFIG_PERCPU_TEST is not set
CONFIG_PID_NS=y
# CONFIG_PRESSURE_DEVICE is not set
# CONFIG_PROXIMITY_DEVICE is not set
# CONFIG_RBTREE_TEST is not set
# CONFIG_REED_SOLOMON_TEST is not set
# CONFIG_STK8BAXX_ACC is not set
# CONFIG_TEMPERATURE_DEVICE is not set
# CONFIG_TEST_BITMAP is not set
# CONFIG_TEST_BITOPS is not set
# CONFIG_TEST_BLACKHOLE_DEV is not set
# CONFIG_TEST_BPF is not set
# CONFIG_TEST_FIRMWARE is not set
# CONFIG_TEST_FREE_PAGES is not set
# CONFIG_TEST_HASH is not set
# CONFIG_TEST_HEXDUMP is not set
# CONFIG_TEST_IDA is not set
# CONFIG_TEST_KMOD is not set
# CONFIG_TEST_KSTRTOX is not set
# CONFIG_TEST_LIST_SORT is not set
# CONFIG_TEST_LKM is not set
# CONFIG_TEST_MEMCAT_P is not set
# CONFIG_TEST_MEMINIT is not set
# CONFIG_TEST_MIN_HEAP is not set
# CONFIG_TEST_OVERFLOW is not set
# CONFIG_TEST_PRINTF is not set
# CONFIG_TEST_RHASHTABLE is not set
# CONFIG_TEST_SORT is not set
# CONFIG_TEST_STACKINIT is not set
# CONFIG_TEST_STATIC_KEYS is not set
# CONFIG_TEST_STRING_HELPERS is not set
# CONFIG_TEST_STRSCPY is not set
# CONFIG_TEST_SYSCTL is not set
# CONFIG_TEST_UDELAY is not set
# CONFIG_TEST_USER_COPY is not set
# CONFIG_TEST_UUID is not set
# CONFIG_TEST_VMALLOC is not set
# CONFIG_TEST_XARRAY is not set
CONFIG_UNWINDER_ARM=y
CONFIG_USER_NS=y
CONFIG_UTS_NS=y
CONFIG_VIDEOBUF2_DMA_CONTIG=y
# CONFIG_VIDEO_HANTRO is not set
CONFIG_VIDEO_ROCKCHIP_ISP1=y
# CONFIG_VIDEO_ROCKCHIP_VDEC is not set

348
arch/arm/configs/rk3126_linux_slc_nand.config Normal file
View File

@@ -0,0 +1,348 @@
# CONFIG_ALLOW_DEV_COREDUMP is not set
# CONFIG_ASHMEM is not set
# CONFIG_BATTERY_SBS is not set
# CONFIG_BLK_CGROUP is not set
CONFIG_BLK_CMDLINE_PARSER=y
# CONFIG_BLK_DEV_IO_TRACE is not set
# CONFIG_BT is not set
# CONFIG_BUG_ON_DATA_CORRUPTION is not set
# CONFIG_CGROUP_CPUACCT is not set
# CONFIG_CGROUP_DEVICE is not set
# CONFIG_CGROUP_FREEZER is not set
# CONFIG_CGROUP_SCHED is not set
# CONFIG_CHARGER_BQ24735 is not set
# CONFIG_CHARGER_GPIO is not set
CONFIG_CMDLINE_PARTITION=y
# CONFIG_CPUSETS is not set
# CONFIG_CPU_FREQ_STAT is not set
# CONFIG_CPU_FREQ_TIMES is not set
# CONFIG_CPU_RK3036 is not set
# CONFIG_CPU_RK30XX is not set
# CONFIG_CPU_RK3188 is not set
# CONFIG_CPU_RK322X is not set
# CONFIG_CPU_RK3288 is not set
# CONFIG_CRC7 is not set
# CONFIG_CRC_ITU_T is not set
# CONFIG_CRC_T10DIF is not set
# CONFIG_CRYPTO_CFB is not set
# CONFIG_CRYPTO_CRCT10DIF is not set
# CONFIG_CRYPTO_DES is not set
# CONFIG_CRYPTO_ECB is not set
# CONFIG_CRYPTO_ECDH is not set
# CONFIG_CRYPTO_HW is not set
# CONFIG_CRYPTO_MICHAEL_MIC is not set
# CONFIG_CRYPTO_OFB is not set
# CONFIG_CRYPTO_SHA1 is not set
# CONFIG_CRYPTO_SHA512 is not set
# CONFIG_CRYPTO_SM3 is not set
# CONFIG_CRYPTO_SM4 is not set
# CONFIG_CRYPTO_USER_API_HASH is not set
# CONFIG_CRYPTO_USER_API_SKCIPHER is not set
# CONFIG_CRYPTO_XTS is not set
CONFIG_CRYPTO_ZSTD=y
# CONFIG_DEBUG_CREDENTIALS is not set
CONFIG_DEBUG_GPIO=y
# CONFIG_DEBUG_INFO is not set
# CONFIG_DEBUG_LIST is not set
# CONFIG_DEBUG_SPINLOCK is not set
# CONFIG_DNS_RESOLVER is not set
# CONFIG_DRM_IGNORE_IOTCL_PERMIT is not set
# CONFIG_DRM_LOAD_EDID_FIRMWARE is not set
# CONFIG_ECRYPT_FS is not set
# CONFIG_ETHERNET is not set
# CONFIG_FB_MODE_HELPERS is not set
# CONFIG_FIQ_DEBUGGER_TRUST_ZONE is not set
# CONFIG_FUNCTION_TRACER is not set
# CONFIG_HFSPLUS_FS is not set
# CONFIG_HID_APPLE is not set
# CONFIG_HID_BATTERY_STRENGTH is not set
# CONFIG_HID_CHERRY is not set
# CONFIG_HID_KENSINGTON is not set
# CONFIG_HID_MAGICMOUSE is not set
# CONFIG_HID_MICROSOFT is not set
# CONFIG_HID_MULTITOUCH is not set
# CONFIG_HID_PLANTRONICS is not set
# CONFIG_HID_PRIMAX is not set
# CONFIG_HID_RMI is not set
# CONFIG_HOSTAP is not set
# CONFIG_HWMON is not set
# CONFIG_I2C_HID is not set
# CONFIG_I2C_STUB is not set
# CONFIG_IKCONFIG is not set
# CONFIG_INITRD_ASYNC is not set
# CONFIG_INPUT_FF_MEMLESS is not set
# CONFIG_INPUT_JOYDEV is not set
# CONFIG_INPUT_JOYSTICK is not set
# CONFIG_INPUT_TABLET is not set
# CONFIG_INPUT_UINPUT is not set
# CONFIG_IOSCHED_BFQ is not set
# CONFIG_IPV6 is not set
# CONFIG_ISO9660_FS is not set
# CONFIG_KERNEL_GZIP is not set
CONFIG_KERNEL_LZ4=y
# CONFIG_KEYBOARD_GPIO is not set
# CONFIG_KEYBOARD_GPIO_POLLED is not set
# CONFIG_MAC80211_DEBUGFS is not set
# CONFIG_MAC80211_DEBUG_MENU is not set
# CONFIG_MAC_PARTITION is not set
# CONFIG_MALI_MIDGARD is not set
# CONFIG_MDIO_DEVICE is not set
# CONFIG_MEDIA_CEC_SUPPORT is not set
# CONFIG_MEDIA_USB_SUPPORT is not set
# CONFIG_MFD_TPS6586X is not set
# CONFIG_MFD_TPS65910 is not set
# CONFIG_MMC_TEST is not set
# CONFIG_MODULE_FORCE_LOAD is not set
# CONFIG_MODULE_FORCE_UNLOAD is not set
# CONFIG_MOUSE_CYAPA is not set
# CONFIG_MOUSE_ELAN_I2C is not set
CONFIG_MTD=y
# CONFIG_MWIFIEX is not set
CONFIG_NAMESPACES=y
# CONFIG_NETFILTER is not set
# CONFIG_NETWORK_FILESYSTEMS is not set
# CONFIG_NET_KEY is not set
# CONFIG_NEW_LEDS is not set
# CONFIG_NL80211_TESTMODE is not set
# CONFIG_NLS_ASCII is not set
CONFIG_NLS_DEFAULT="iso8859-1"
# CONFIG_NLS_UTF8 is not set
# CONFIG_PHYLIB is not set
# CONFIG_PHY_ROCKCHIP_DP is not set
# CONFIG_PHY_ROCKCHIP_INNO_HDMI is not set
# CONFIG_PHY_ROCKCHIP_USB is not set
# CONFIG_PINCTRL_RK805 is not set
# CONFIG_PM_DEBUG is not set
# CONFIG_POWER_RESET_GPIO_RESTART is not set
# CONFIG_PPS is not set
# CONFIG_PSI is not set
# CONFIG_PTP_1588_CLOCK is not set
# CONFIG_RD_XZ is not set
# CONFIG_REGULATOR_ACT8865 is not set
# CONFIG_REGULATOR_FAN53555 is not set
# CONFIG_RELAY is not set
# CONFIG_RFKILL_RK is not set
CONFIG_RK_CONSOLE_THREAD=y
CONFIG_RK_HEADSET=y
# CONFIG_RK_NAND is not set
# CONFIG_RMI4_CORE is not set
# CONFIG_ROCKCHIP_ANALOGIX_DP is not set
# CONFIG_ROCKCHIP_DDRCLK_SIP_V2 is not set
# CONFIG_ROCKCHIP_DW_HDMI is not set
# CONFIG_ROCKCHIP_EFUSE is not set
# CONFIG_ROCKCHIP_INNO_HDMI is not set
# CONFIG_ROCKCHIP_MPP_RKVDEC is not set
# CONFIG_ROCKCHIP_MPP_RKVENC is not set
# CONFIG_ROCKCHIP_MPP_VDPU2 is not set
# CONFIG_ROCKCHIP_MPP_VEPU2 is not set
# CONFIG_ROCKCHIP_PLL_RK3066 is not set
# CONFIG_ROCKCHIP_VENDOR_STORAGE_UPDATE_LOADER is not set
# CONFIG_RT2X00 is not set
# CONFIG_RTC_DRV_HYM8563 is not set
CONFIG_RUNTIME_TESTING_MENU=y
# CONFIG_SCHED_DEBUG is not set
# CONFIG_SCHED_STACK_END_CHECK is not set
# CONFIG_SECURITY is not set
# CONFIG_SECURITYFS is not set
# CONFIG_SENSORS_ISL29018 is not set
# CONFIG_SENSORS_TSL2563 is not set
CONFIG_SENSOR_DEVICE=y
# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set
# CONFIG_SERIAL_OF_PLATFORM is not set
# CONFIG_SLUB_DEBUG is not set
# CONFIG_SND_SOC_ES8323 is not set
# CONFIG_SND_SOC_ES8396 is not set
# CONFIG_SND_SOC_ROCKCHIP_MAX98090 is not set
# CONFIG_SND_SOC_ROCKCHIP_RT5645 is not set
# CONFIG_SND_SOC_RT5616 is not set
# CONFIG_SND_SOC_RT5640 is not set
# CONFIG_SND_SOC_TS3A227E is not set
# CONFIG_SND_USB_AUDIO is not set
# CONFIG_SPI_SPIDEV is not set
CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU=y
# CONFIG_SQUASHFS_DECOMP_SINGLE is not set
CONFIG_STAGING_MEDIA=y
# CONFIG_TCG_TPM is not set
# CONFIG_TEE is not set
# CONFIG_TMPFS_POSIX_ACL is not set
# CONFIG_TMPFS_XATTR is not set
# CONFIG_TOUCHSCREEN_ATMEL_MXT is not set
# CONFIG_TOUCHSCREEN_ELAN is not set
# CONFIG_TOUCHSCREEN_GSL3673 is not set
# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
# CONFIG_TSL2583 is not set
# CONFIG_UDF_FS is not set
# CONFIG_UNWINDER_FRAME_POINTER is not set
# CONFIG_USB_ACM is not set
# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
# CONFIG_USB_CONFIGFS_ACM is not set
CONFIG_USB_DEFAULT_PERSIST=y
# CONFIG_USB_EHCI_ROOT_HUB_TT is not set
# CONFIG_USB_EZUSB_FX2 is not set
# CONFIG_USB_HIDDEV is not set
# CONFIG_USB_MON is not set
# CONFIG_USB_NET_RNDIS_WLAN is not set
# CONFIG_USB_OTG is not set
# CONFIG_USB_PEGASUS is not set
# CONFIG_USB_RTL8150 is not set
# CONFIG_USB_RTL8152 is not set
# CONFIG_USB_SERIAL is not set
# CONFIG_USB_USBNET is not set
# CONFIG_USB_WDM is not set
# CONFIG_V4L_TEST_DRIVERS is not set
CONFIG_VIDEO_GC2145=y
# CONFIG_VIDEO_IMX219 is not set
# CONFIG_VIDEO_OV13850 is not set
# CONFIG_VIDEO_OV5647 is not set
# CONFIG_VIDEO_OV8858 is not set
# CONFIG_VIDEO_SGM3784 is not set
CONFIG_WIFI_GENERATE_RANDOM_MAC_ADDR=y
# CONFIG_XZ_DEC is not set
# CONFIG_ANGLE_DEVICE is not set
CONFIG_ARM_UNWIND=y
# CONFIG_ATOMIC64_SELFTEST is not set
# CONFIG_BACKTRACE_SELF_TEST is not set
# CONFIG_BMA2XX_ACC is not set
# CONFIG_COMPASS_DEVICE is not set
CONFIG_ENABLE_DEFAULT_TRACERS=y
# CONFIG_FIND_BIT_BENCHMARK is not set
# CONFIG_FTL is not set
CONFIG_GSENSOR_DEVICE=y
# CONFIG_GS_BMA023 is not set
# CONFIG_GS_DA215S is not set
# CONFIG_GS_DA223 is not set
# CONFIG_GS_DA228E is not set
# CONFIG_GS_DMT10 is not set
# CONFIG_GS_KXTIK is not set
# CONFIG_GS_KXTJ9 is not set
# CONFIG_GS_LIS3DH is not set
# CONFIG_GS_LSM303D is not set
# CONFIG_GS_MC3230 is not set
CONFIG_GS_MMA7660=y
# CONFIG_GS_MMA8452 is not set
# CONFIG_GS_MXC6225 is not set
# CONFIG_GS_MXC6655XA is not set
# CONFIG_GS_SC7660 is not set
# CONFIG_GS_SC7A20 is not set
# CONFIG_GS_SC7A30 is not set
# CONFIG_GYROSCOPE_DEVICE is not set
# CONFIG_HALL_DEVICE is not set
# CONFIG_ICM2060X_ACC is not set
# CONFIG_INFTL is not set
CONFIG_INLINE_READ_UNLOCK=y
CONFIG_INLINE_READ_UNLOCK_IRQ=y
CONFIG_INLINE_SPIN_UNLOCK_IRQ=y
CONFIG_INLINE_WRITE_UNLOCK=y
CONFIG_INLINE_WRITE_UNLOCK_IRQ=y
# CONFIG_INTERVAL_TREE_TEST is not set
CONFIG_IPC_NS=y
# CONFIG_JFFS2_FS is not set
# CONFIG_LIGHT_DEVICE is not set
# CONFIG_LKDTM is not set
# CONFIG_LSM330_ACC is not set
# CONFIG_MPU6500_ACC is not set
# CONFIG_MPU6880_ACC is not set
# CONFIG_MTD_ABSENT is not set
# CONFIG_MTD_AFS_PARTS is not set
# CONFIG_MTD_AR7_PARTS is not set
CONFIG_MTD_BLKDEVS=y
CONFIG_MTD_BLOCK=y
# CONFIG_MTD_BLOCK2MTD is not set
# CONFIG_MTD_CFI is not set
CONFIG_MTD_CFI_I1=y
CONFIG_MTD_CFI_I2=y
CONFIG_MTD_CMDLINE_PARTS=y
# CONFIG_MTD_COMPLEX_MAPPINGS is not set
# CONFIG_MTD_DATAFLASH is not set
# CONFIG_MTD_DOCG3 is not set
# CONFIG_MTD_HYPERBUS is not set
# CONFIG_MTD_JEDECPROBE is not set
# CONFIG_MTD_LPDDR is not set
# CONFIG_MTD_LPDDR2_NVM is not set
CONFIG_MTD_MAP_BANK_WIDTH_1=y
CONFIG_MTD_MAP_BANK_WIDTH_2=y
CONFIG_MTD_MAP_BANK_WIDTH_4=y
# CONFIG_MTD_MCHP23K256 is not set
# CONFIG_MTD_MTDRAM is not set
# CONFIG_MTD_OF_PARTS is not set
# CONFIG_MTD_ONENAND is not set
# CONFIG_MTD_OOPS is not set
CONFIG_MTD_PARTITIONED_MASTER=y
# CONFIG_MTD_PHRAM is not set
# CONFIG_MTD_PLATRAM is not set
# CONFIG_MTD_RAM is not set
# CONFIG_MTD_RAW_NAND is not set
# CONFIG_MTD_REDBOOT_PARTS is not set
# CONFIG_MTD_ROM is not set
# CONFIG_MTD_SLRAM is not set
# CONFIG_MTD_SPI_NAND is not set
# CONFIG_MTD_SPI_NOR is not set
# CONFIG_MTD_SST25L is not set
# CONFIG_MTD_SWAP is not set
# CONFIG_MTD_TESTS is not set
CONFIG_MTD_UBI=y
CONFIG_MTD_UBI_BEB_LIMIT=20
CONFIG_MTD_UBI_BLOCK=y
# CONFIG_MTD_UBI_FASTMAP is not set
# CONFIG_MTD_UBI_GLUEBI is not set
CONFIG_MTD_UBI_WL_THRESHOLD=4096
CONFIG_NET_NS=y
# CONFIG_NFTL is not set
# CONFIG_PERCPU_TEST is not set
CONFIG_PID_NS=y
# CONFIG_PRESSURE_DEVICE is not set
# CONFIG_PROXIMITY_DEVICE is not set
# CONFIG_RBTREE_TEST is not set
# CONFIG_REED_SOLOMON_TEST is not set
# CONFIG_RFD_FTL is not set
# CONFIG_SM_FTL is not set
# CONFIG_SSFDC is not set
# CONFIG_STK8BAXX_ACC is not set
# CONFIG_TEMPERATURE_DEVICE is not set
# CONFIG_TEST_BITMAP is not set
# CONFIG_TEST_BITOPS is not set
# CONFIG_TEST_BLACKHOLE_DEV is not set
# CONFIG_TEST_BPF is not set
# CONFIG_TEST_FIRMWARE is not set
# CONFIG_TEST_FREE_PAGES is not set
# CONFIG_TEST_HASH is not set
# CONFIG_TEST_HEXDUMP is not set
# CONFIG_TEST_IDA is not set
# CONFIG_TEST_KMOD is not set
# CONFIG_TEST_KSTRTOX is not set
# CONFIG_TEST_LIST_SORT is not set
# CONFIG_TEST_LKM is not set
# CONFIG_TEST_MEMCAT_P is not set
# CONFIG_TEST_MEMINIT is not set
# CONFIG_TEST_MIN_HEAP is not set
# CONFIG_TEST_OVERFLOW is not set
# CONFIG_TEST_PRINTF is not set
# CONFIG_TEST_RHASHTABLE is not set
# CONFIG_TEST_SORT is not set
# CONFIG_TEST_STACKINIT is not set
# CONFIG_TEST_STATIC_KEYS is not set
# CONFIG_TEST_STRING_HELPERS is not set
# CONFIG_TEST_STRSCPY is not set
# CONFIG_TEST_SYSCTL is not set
# CONFIG_TEST_UDELAY is not set
# CONFIG_TEST_USER_COPY is not set
# CONFIG_TEST_UUID is not set
# CONFIG_TEST_VMALLOC is not set
# CONFIG_TEST_XARRAY is not set
# CONFIG_UBIFS_ATIME_SUPPORT is not set
CONFIG_UBIFS_FS=y
CONFIG_UBIFS_FS_ADVANCED_COMPR=y
# CONFIG_UBIFS_FS_AUTHENTICATION is not set
CONFIG_UBIFS_FS_LZO=y
CONFIG_UBIFS_FS_SECURITY=y
CONFIG_UBIFS_FS_XATTR=y
CONFIG_UBIFS_FS_ZLIB=y
CONFIG_UBIFS_FS_ZSTD=y
CONFIG_UNWINDER_ARM=y
CONFIG_USER_NS=y
CONFIG_UTS_NS=y
CONFIG_VIDEOBUF2_DMA_CONTIG=y
# CONFIG_VIDEO_HANTRO is not set
CONFIG_VIDEO_ROCKCHIP_ISP1=y
# CONFIG_VIDEO_ROCKCHIP_VDEC is not set
CONFIG_ZSTD_COMPRESS=y

166
arch/arm/configs/rk3128_linux.config Normal file
View File

@@ -0,0 +1,166 @@
# CONFIG_BLK_CGROUP is not set
# CONFIG_BUG_ON_DATA_CORRUPTION is not set
# CONFIG_CGROUP_CPUACCT is not set
# CONFIG_CGROUP_DEVICE is not set
# CONFIG_CGROUP_FREEZER is not set
# CONFIG_CGROUP_SCHED is not set
# CONFIG_CPUSETS is not set
# CONFIG_CPU_FREQ_STAT is not set
# CONFIG_CPU_FREQ_TIMES is not set
# CONFIG_CPU_RK3036 is not set
# CONFIG_CPU_RK30XX is not set
# CONFIG_CPU_RK3188 is not set
# CONFIG_CPU_RK322X is not set
# CONFIG_CPU_RK3288 is not set
# CONFIG_CRYPTO_CFB is not set
# CONFIG_CRYPTO_DES is not set
# CONFIG_CRYPTO_DEV_ROCKCHIP is not set
# CONFIG_CRYPTO_OFB is not set
# CONFIG_CRYPTO_SHA1 is not set
# CONFIG_CRYPTO_SM3 is not set
# CONFIG_CRYPTO_SM4 is not set
# CONFIG_CRYPTO_XTS is not set
CONFIG_DEBUG_GPIO=y
# CONFIG_DEBUG_LIST is not set
CONFIG_DETECT_HUNG_TASK=y
# CONFIG_DNS_RESOLVER is not set
# CONFIG_DRM_IGNORE_IOTCL_PERMIT is not set
# CONFIG_DRM_LOAD_EDID_FIRMWARE is not set
CONFIG_DRM_UDL=y
# CONFIG_ECRYPT_FS is not set
# CONFIG_IEP is not set
# CONFIG_IKCONFIG is not set
# CONFIG_INITRD_ASYNC is not set
# CONFIG_INPUT_TABLET is not set
# CONFIG_IOSCHED_BFQ is not set
# CONFIG_MALI_MIDGARD is not set
# CONFIG_MODULE_FORCE_LOAD is not set
# CONFIG_MODULE_FORCE_UNLOAD is not set
CONFIG_NAMESPACES=y
# CONFIG_NETWORK_FILESYSTEMS is not set
# CONFIG_PINCTRL_RK805 is not set
# CONFIG_PM_DEBUG is not set
# CONFIG_PSI is not set
# CONFIG_RFKILL_RK is not set
CONFIG_RK_HEADSET=y
# CONFIG_ROCKCHIP_ANALOGIX_DP is not set
# CONFIG_ROCKCHIP_DDRCLK_SIP_V2 is not set
# CONFIG_ROCKCHIP_DW_HDMI is not set
# CONFIG_ROCKCHIP_MPP_SERVICE is not set
# CONFIG_ROCKCHIP_MULTI_RGA is not set
# CONFIG_ROCKCHIP_PLL_RK3066 is not set
CONFIG_ROCKCHIP_REMOTECTL=y
CONFIG_ROCKCHIP_RGA=y
# CONFIG_ROCKCHIP_VENDOR_STORAGE_UPDATE_LOADER is not set
CONFIG_RUNTIME_TESTING_MENU=y
# CONFIG_SCHED_STACK_END_CHECK is not set
CONFIG_SENSOR_DEVICE=y
# CONFIG_SERIAL_OF_PLATFORM is not set
CONFIG_SND_SOC_ROCKCHIP_MULTICODECS=y
CONFIG_SOFTLOCKUP_DETECTOR=y
# CONFIG_SPI_SPIDEV is not set
CONFIG_STAGING_MEDIA=y
# CONFIG_TEE is not set
# CONFIG_TOUCHSCREEN_ATMEL_MXT is not set
# CONFIG_TOUCHSCREEN_ELAN is not set
# CONFIG_TOUCHSCREEN_GSL3673 is not set
# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
# CONFIG_USB_ACM is not set
# CONFIG_USB_EZUSB_FX2 is not set
# CONFIG_USB_SERIAL is not set
# CONFIG_V4L_TEST_DRIVERS is not set
CONFIG_VIDEO_GC2145=y
# CONFIG_VIDEO_IMX219 is not set
# CONFIG_VIDEO_OV13850 is not set
# CONFIG_VIDEO_OV5647 is not set
# CONFIG_VIDEO_OV8858 is not set
# CONFIG_VIDEO_SGM3784 is not set
CONFIG_WIFI_GENERATE_RANDOM_MAC_ADDR=y
# CONFIG_ANGLE_DEVICE is not set
# CONFIG_ATOMIC64_SELFTEST is not set
# CONFIG_BACKTRACE_SELF_TEST is not set
# CONFIG_BMA2XX_ACC is not set
CONFIG_BOOTPARAM_HUNG_TASK_PANIC=y
CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=1
CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC=y
CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=1
# CONFIG_COMPASS_DEVICE is not set
CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=120
CONFIG_DRM_GEM_SHMEM_HELPER=y
# CONFIG_FIND_BIT_BENCHMARK is not set
CONFIG_GSENSOR_DEVICE=y
# CONFIG_GS_BMA023 is not set
# CONFIG_GS_DA215S is not set
# CONFIG_GS_DA223 is not set
# CONFIG_GS_DA228E is not set
# CONFIG_GS_DMT10 is not set
# CONFIG_GS_KXTIK is not set
# CONFIG_GS_KXTJ9 is not set
# CONFIG_GS_LIS3DH is not set
# CONFIG_GS_LSM303D is not set
# CONFIG_GS_MC3230 is not set
CONFIG_GS_MMA7660=y
# CONFIG_GS_MMA8452 is not set
# CONFIG_GS_MXC6225 is not set
# CONFIG_GS_MXC6655XA is not set
# CONFIG_GS_SC7660 is not set
# CONFIG_GS_SC7A20 is not set
# CONFIG_GS_SC7A30 is not set
# CONFIG_GYROSCOPE_DEVICE is not set
# CONFIG_HALL_DEVICE is not set
# CONFIG_ICM2060X_ACC is not set
# CONFIG_INTERVAL_TREE_TEST is not set
CONFIG_IPC_NS=y
# CONFIG_LIGHT_DEVICE is not set
CONFIG_LKDTM=y
CONFIG_LOCKUP_DETECTOR=y
# CONFIG_LSM330_ACC is not set
# CONFIG_MPU6500_ACC is not set
# CONFIG_MPU6880_ACC is not set
CONFIG_NET_NS=y
# CONFIG_PERCPU_TEST is not set
CONFIG_PID_NS=y
# CONFIG_PRESSURE_DEVICE is not set
# CONFIG_PROXIMITY_DEVICE is not set
# CONFIG_RBTREE_TEST is not set
# CONFIG_REED_SOLOMON_TEST is not set
CONFIG_ROCKCHIP_REMOTECTL_PWM=y
# CONFIG_ROCKCHIP_RGA2 is not set
# CONFIG_STK8BAXX_ACC is not set
# CONFIG_TEMPERATURE_DEVICE is not set
# CONFIG_TEST_BITMAP is not set
# CONFIG_TEST_BITOPS is not set
# CONFIG_TEST_BLACKHOLE_DEV is not set
# CONFIG_TEST_BPF is not set
# CONFIG_TEST_FIRMWARE is not set
# CONFIG_TEST_FREE_PAGES is not set
# CONFIG_TEST_HASH is not set
# CONFIG_TEST_HEXDUMP is not set
# CONFIG_TEST_IDA is not set
# CONFIG_TEST_KMOD is not set
# CONFIG_TEST_KSTRTOX is not set
# CONFIG_TEST_LIST_SORT is not set
# CONFIG_TEST_LKM is not set
# CONFIG_TEST_MEMCAT_P is not set
# CONFIG_TEST_MEMINIT is not set
# CONFIG_TEST_MIN_HEAP is not set
# CONFIG_TEST_OVERFLOW is not set
# CONFIG_TEST_PRINTF is not set
# CONFIG_TEST_RHASHTABLE is not set
# CONFIG_TEST_SORT is not set
# CONFIG_TEST_STACKINIT is not set
# CONFIG_TEST_STATIC_KEYS is not set
# CONFIG_TEST_STRING_HELPERS is not set
# CONFIG_TEST_STRSCPY is not set
# CONFIG_TEST_SYSCTL is not set
CONFIG_TEST_UDELAY=y
# CONFIG_TEST_USER_COPY is not set
# CONFIG_TEST_UUID is not set
# CONFIG_TEST_VMALLOC is not set
# CONFIG_TEST_XARRAY is not set
CONFIG_USER_NS=y
CONFIG_UTS_NS=y
CONFIG_VIDEOBUF2_DMA_CONTIG=y
# CONFIG_VIDEO_HANTRO is not set
CONFIG_VIDEO_ROCKCHIP_ISP1=y
# CONFIG_VIDEO_ROCKCHIP_VDEC is not set

1
arch/arm/configs/rockchip_defconfig
View File

@@ -298,6 +298,7 @@ CONFIG_STMMAC_ETH=y
# CONFIG_NET_VENDOR_SYNOPSYS is not set
# CONFIG_NET_VENDOR_VIA is not set
# CONFIG_NET_VENDOR_WIZNET is not set
CONFIG_MOTORCOMM_PHY=y
CONFIG_ROCKCHIP_PHY=y
CONFIG_PPP=y
CONFIG_PPP_BSDCOMP=y

6
arch/arm/configs/rockchip_linux_defconfig
View File

@@ -174,6 +174,7 @@ CONFIG_TUN=y
CONFIG_VETH=y
CONFIG_EMAC_ROCKCHIP=y
CONFIG_STMMAC_ETH=y
CONFIG_MOTORCOMM_PHY=y
CONFIG_ROCKCHIP_PHY=y
CONFIG_PPP=y
CONFIG_PPP_ASYNC=y
@@ -219,6 +220,8 @@ CONFIG_TOUCHSCREEN_GSL3673=y
CONFIG_TOUCHSCREEN_GT1X=y
CONFIG_TOUCHSCREEN_ELAN=y
CONFIG_TOUCHSCREEN_USB_COMPOSITE=y
CONFIG_ROCKCHIP_REMOTECTL=y
CONFIG_ROCKCHIP_REMOTECTL_PWM=y
CONFIG_INPUT_MISC=y
CONFIG_INPUT_UINPUT=y
CONFIG_INPUT_RK805_PWRKEY=y
@@ -272,8 +275,10 @@ CONFIG_USB_VIDEO_CLASS=y
# CONFIG_USB_GSPCA is not set
CONFIG_V4L_PLATFORM_DRIVERS=y
CONFIG_VIDEO_ROCKCHIP_CIF=y
CONFIG_VIDEO_ROCKCHIP_RKISP1=y
CONFIG_V4L_MEM2MEM_DRIVERS=y
CONFIG_V4L_TEST_DRIVERS=y
CONFIG_VIDEO_GC8034=y
CONFIG_VIDEO_IMX219=y
CONFIG_VIDEO_OV5647=y
CONFIG_VIDEO_OV8858=y
@@ -284,6 +289,7 @@ CONFIG_DRM_IGNORE_IOTCL_PERMIT=y
CONFIG_DRM_LOAD_EDID_FIRMWARE=y
CONFIG_DRM_ROCKCHIP=y
CONFIG_ROCKCHIP_ANALOGIX_DP=y
CONFIG_ROCKCHIP_DRM_TVE=y
CONFIG_ROCKCHIP_DW_HDMI=y
CONFIG_ROCKCHIP_DW_MIPI_DSI=y
CONFIG_ROCKCHIP_INNO_HDMI=y

10
arch/arm/configs/rv1106-battery-ipc.config
View File

@@ -1,3 +1,5 @@
CONFIG_CRC16=m
CONFIG_EXT4_FS=m
CONFIG_FILE_LOCKING=y
CONFIG_JFFS2_FS=y
CONFIG_MAILBOX=y
@@ -87,11 +89,16 @@ CONFIG_VIDEO_SC3338=y
# CONFIG_BSD_DISKLABEL is not set
# CONFIG_EEPROM_93XX46 is not set
# CONFIG_EEPROM_AT25 is not set
# CONFIG_EXT4_DEBUG is not set
# CONFIG_EXT4_FS_POSIX_ACL is not set
# CONFIG_EXT4_FS_SECURITY is not set
CONFIG_EXT4_USE_FOR_EXT2=y
# CONFIG_EZX_PCAP is not set
CONFIG_FAT_DEFAULT_CODEPAGE=936
CONFIG_FAT_DEFAULT_IOCHARSET="cp936"
CONFIG_FAT_DEFAULT_UTF8=y
CONFIG_FAT_FS=m
CONFIG_FS_MBCACHE=m
# CONFIG_FXOS8700_SPI is not set
# CONFIG_GPIO_74X164 is not set
# CONFIG_GPIO_MAX3191X is not set
@@ -103,6 +110,8 @@ CONFIG_FAT_FS=m
# CONFIG_IIO_SSP_SENSORHUB is not set
# CONFIG_INV_ICM42600_SPI is not set
# CONFIG_INV_MPU6050_SPI is not set
CONFIG_JBD2=m
# CONFIG_JBD2_DEBUG is not set
# CONFIG_JFFS2_CMODE_FAVOURLZO is not set
# CONFIG_JFFS2_CMODE_NONE is not set
CONFIG_JFFS2_CMODE_PRIORITY=y
@@ -156,6 +165,7 @@ CONFIG_MANDATORY_FILE_LOCKING=y
# CONFIG_MTD_MCHP23K256 is not set
# CONFIG_MTD_SPI_NAND is not set
CONFIG_MTD_SPI_NOR=m
CONFIG_MTD_SPI_NOR_MISC=y
# CONFIG_MTD_SPI_NOR_USE_4K_SECTORS is not set
# CONFIG_MTD_SST25L is not set
# CONFIG_PI433 is not set

998
arch/arm/configs/rv1106-cvr.config Normal file
View File

@@ -0,0 +1,998 @@
CONFIG_BACKLIGHT_CLASS_DEVICE=y
CONFIG_CONFIGFS_FS=y
CONFIG_CRC16=y
CONFIG_CRYPTO=y
CONFIG_DEBUG_FS=y
CONFIG_DRM=y
CONFIG_ELF_CORE=y
CONFIG_EXPORTFS_BLOCK_OPS=y
CONFIG_EXT4_FS=y
CONFIG_EXTCON=y
CONFIG_FB=y
CONFIG_FILE_LOCKING=y
CONFIG_I2C_GPIO=y
CONFIG_I2C_MUX=y
CONFIG_INPUT=y
CONFIG_IPV6=m
CONFIG_JFFS2_FS=y
CONFIG_KCMP=y
CONFIG_KEYS=y
CONFIG_MMC=y
CONFIG_MSDOS_PARTITION=y
CONFIG_MTD_BLOCK=y
CONFIG_MTD_UBI=y
CONFIG_NETWORK_FILESYSTEMS=y
CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_ISO8859_1=y
CONFIG_NVMEM_SYSFS=y
CONFIG_RK_CMA_PROCFS=y
CONFIG_RK_DMABUF_PROCFS=y
CONFIG_RK_MEMBLOCK_PROCFS=y
CONFIG_ROCKCHIP_OPP=y
CONFIG_ROCKCHIP_RGA_PROC_FS=y
CONFIG_ROCKCHIP_RVE_PROC_FS=y
CONFIG_ROCKCHIP_VENDOR_STORAGE=y
CONFIG_RTC_DRV_ROCKCHIP=y
CONFIG_SPI=y
CONFIG_USB_SUPPORT=y
CONFIG_VFAT_FS=y
CONFIG_VIDEO_OS04A10=m
CONFIG_VIDEO_SC3336=m
CONFIG_VIDEO_SC4336=m
CONFIG_VIDEO_SC530AI=m
CONFIG_WIRELESS=y
CONFIG_WLAN=y
# CONFIG_6LOWPAN is not set
# CONFIG_AD2S1200 is not set
# CONFIG_AD2S1210 is not set
# CONFIG_AD2S90 is not set
# CONFIG_AD5360 is not set
# CONFIG_AD5421 is not set
# CONFIG_AD5449 is not set
# CONFIG_AD5504 is not set
# CONFIG_AD5592R is not set
# CONFIG_AD5624R_SPI is not set
# CONFIG_AD5686_SPI is not set
# CONFIG_AD5755 is not set
# CONFIG_AD5758 is not set
# CONFIG_AD5761 is not set
# CONFIG_AD5764 is not set
# CONFIG_AD5770R is not set
# CONFIG_AD5791 is not set
# CONFIG_AD7124 is not set
# CONFIG_AD7192 is not set
# CONFIG_AD7266 is not set
# CONFIG_AD7280 is not set
# CONFIG_AD7292 is not set
# CONFIG_AD7298 is not set
# CONFIG_AD7303 is not set
# CONFIG_AD7476 is not set
# CONFIG_AD7606_IFACE_SPI is not set
# CONFIG_AD7766 is not set
# CONFIG_AD7768_1 is not set
# CONFIG_AD7780 is not set
# CONFIG_AD7791 is not set
# CONFIG_AD7793 is not set
# CONFIG_AD7816 is not set
# CONFIG_AD7887 is not set
# CONFIG_AD7923 is not set
# CONFIG_AD7949 is not set
# CONFIG_AD8366 is not set
# CONFIG_AD8801 is not set
# CONFIG_AD9523 is not set
# CONFIG_AD9832 is not set
# CONFIG_AD9834 is not set
# CONFIG_ADF4350 is not set
# CONFIG_ADF4371 is not set
# CONFIG_ADIS16080 is not set
# CONFIG_ADIS16130 is not set
# CONFIG_ADIS16136 is not set
# CONFIG_ADIS16201 is not set
# CONFIG_ADIS16203 is not set
# CONFIG_ADIS16209 is not set
# CONFIG_ADIS16240 is not set
# CONFIG_ADIS16260 is not set
# CONFIG_ADIS16400 is not set
# CONFIG_ADIS16460 is not set
# CONFIG_ADIS16475 is not set
# CONFIG_ADIS16480 is not set
# CONFIG_ADXL345_SPI is not set
# CONFIG_ADXL372_SPI is not set
# CONFIG_ADXRS290 is not set
# CONFIG_ADXRS450 is not set
# CONFIG_AFE4403 is not set
# CONFIG_AFS_FS is not set
# CONFIG_APPLE_MFI_FASTCHARGE is not set
# CONFIG_ARM_CRYPTO is not set
# CONFIG_AS3935 is not set
CONFIG_ASN1=y
CONFIG_ASSOCIATIVE_ARRAY=y
CONFIG_ASYMMETRIC_KEY_TYPE=y
CONFIG_ASYMMETRIC_PUBLIC_KEY_SUBTYPE=y
# CONFIG_BACKLIGHT_ADP8860 is not set
# CONFIG_BACKLIGHT_ADP8870 is not set
# CONFIG_BACKLIGHT_ARCXCNN is not set
# CONFIG_BACKLIGHT_BD6107 is not set
# CONFIG_BACKLIGHT_GPIO is not set
# CONFIG_BACKLIGHT_KTD253 is not set
# CONFIG_BACKLIGHT_LM3630A is not set
# CONFIG_BACKLIGHT_LM3639 is not set
# CONFIG_BACKLIGHT_LP855X is not set
# CONFIG_BACKLIGHT_LV5207LP is not set
CONFIG_BACKLIGHT_PWM=y
# CONFIG_BACKLIGHT_QCOM_WLED is not set
# CONFIG_BCMDHD is not set
CONFIG_BLK_DEBUG_FS=y
# CONFIG_BMA220 is not set
# CONFIG_BMC150_MAGN_SPI is not set
# CONFIG_BMI160_SPI is not set
# CONFIG_BSD_DISKLABEL is not set
# CONFIG_CEPH_FS is not set
CONFIG_CFG80211=m
# CONFIG_CFG80211_CERTIFICATION_ONUS is not set
CONFIG_CFG80211_CRDA_SUPPORT=y
# CONFIG_CFG80211_DEBUGFS is not set
CONFIG_CFG80211_DEFAULT_PS=y
# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set
CONFIG_CFG80211_REQUIRE_SIGNED_REGDB=y
CONFIG_CFG80211_USE_KERNEL_REGDB_KEYS=y
# CONFIG_CFG80211_WEXT is not set
# CONFIG_CHARGER_BQ24190 is not set
# CONFIG_CIFS is not set
CONFIG_CLZ_TAB=y
# CONFIG_CMA_DEBUGFS is not set
# CONFIG_CODA_FS is not set
CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y
# CONFIG_CRYPTO_842 is not set
CONFIG_CRYPTO_ACOMP2=y
# CONFIG_CRYPTO_ADIANTUM is not set
CONFIG_CRYPTO_AEAD=m
CONFIG_CRYPTO_AEAD2=y
# CONFIG_CRYPTO_AEGIS128 is not set
CONFIG_CRYPTO_AES=m
# CONFIG_CRYPTO_AES_TI is not set
CONFIG_CRYPTO_AKCIPHER=y
CONFIG_CRYPTO_AKCIPHER2=y
CONFIG_CRYPTO_ALGAPI=y
CONFIG_CRYPTO_ALGAPI2=y
# CONFIG_CRYPTO_ANSI_CPRNG is not set
# CONFIG_CRYPTO_AUTHENC is not set
# CONFIG_CRYPTO_BLAKE2B is not set
# CONFIG_CRYPTO_BLAKE2S is not set
# CONFIG_CRYPTO_BLOWFISH is not set
# CONFIG_CRYPTO_CAMELLIA is not set
# CONFIG_CRYPTO_CAST5 is not set
# CONFIG_CRYPTO_CAST6 is not set
# CONFIG_CRYPTO_CBC is not set
CONFIG_CRYPTO_CCM=m
# CONFIG_CRYPTO_CFB is not set
# CONFIG_CRYPTO_CHACHA20 is not set
# CONFIG_CRYPTO_CHACHA20POLY1305 is not set
CONFIG_CRYPTO_CMAC=m
# CONFIG_CRYPTO_CRC32 is not set
CONFIG_CRYPTO_CRC32C=y
# CONFIG_CRYPTO_CRCT10DIF is not set
# CONFIG_CRYPTO_CRYPTD is not set
CONFIG_CRYPTO_CTR=m
# CONFIG_CRYPTO_CTS is not set
# CONFIG_CRYPTO_CURVE25519 is not set
CONFIG_CRYPTO_DEFLATE=y
# CONFIG_CRYPTO_DES is not set
# CONFIG_CRYPTO_DH is not set
# CONFIG_CRYPTO_DRBG_MENU is not set
# CONFIG_CRYPTO_ECB is not set
# CONFIG_CRYPTO_ECDH is not set
# CONFIG_CRYPTO_ECHAINIV is not set
# CONFIG_CRYPTO_ECRDSA is not set
# CONFIG_CRYPTO_ESSIV is not set
# CONFIG_CRYPTO_FCRYPT is not set
CONFIG_CRYPTO_GCM=m
CONFIG_CRYPTO_GF128MUL=m
CONFIG_CRYPTO_GHASH=m
CONFIG_CRYPTO_HASH=y
CONFIG_CRYPTO_HASH2=y
CONFIG_CRYPTO_HASH_INFO=y
# CONFIG_CRYPTO_HMAC is not set
# CONFIG_CRYPTO_HW is not set
# CONFIG_CRYPTO_JITTERENTROPY is not set
# CONFIG_CRYPTO_KEYWRAP is not set
CONFIG_CRYPTO_KPP2=y
CONFIG_CRYPTO_LIB_AES=m
CONFIG_CRYPTO_LIB_ARC4=m
# CONFIG_CRYPTO_LIB_BLAKE2S is not set
# CONFIG_CRYPTO_LIB_CHACHA is not set
# CONFIG_CRYPTO_LIB_CHACHA20POLY1305 is not set
# CONFIG_CRYPTO_LIB_CURVE25519 is not set
# CONFIG_CRYPTO_LIB_POLY1305 is not set
CONFIG_CRYPTO_LIB_POLY1305_RSIZE=9
CONFIG_CRYPTO_LIB_SHA256=m
# CONFIG_CRYPTO_LRW is not set
# CONFIG_CRYPTO_LZ4 is not set
# CONFIG_CRYPTO_LZ4HC is not set
CONFIG_CRYPTO_LZO=y
CONFIG_CRYPTO_MANAGER=y
CONFIG_CRYPTO_MANAGER2=y
CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y
# CONFIG_CRYPTO_MD4 is not set
# CONFIG_CRYPTO_MD5 is not set
# CONFIG_CRYPTO_MICHAEL_MIC is not set
CONFIG_CRYPTO_NULL=m
CONFIG_CRYPTO_NULL2=y
# CONFIG_CRYPTO_OFB is not set
# CONFIG_CRYPTO_PCBC is not set
# CONFIG_CRYPTO_POLY1305 is not set
# CONFIG_CRYPTO_RMD128 is not set
# CONFIG_CRYPTO_RMD160 is not set
# CONFIG_CRYPTO_RMD256 is not set
# CONFIG_CRYPTO_RMD320 is not set
CONFIG_CRYPTO_RNG2=y
CONFIG_CRYPTO_RSA=y
# CONFIG_CRYPTO_SALSA20 is not set
# CONFIG_CRYPTO_SEQIV is not set
# CONFIG_CRYPTO_SERPENT is not set
# CONFIG_CRYPTO_SHA1 is not set
CONFIG_CRYPTO_SHA256=m
# CONFIG_CRYPTO_SHA3 is not set
# CONFIG_CRYPTO_SHA512 is not set
CONFIG_CRYPTO_SKCIPHER=m
CONFIG_CRYPTO_SKCIPHER2=y
# CONFIG_CRYPTO_SM2 is not set
# CONFIG_CRYPTO_SM3 is not set
# CONFIG_CRYPTO_SM4 is not set
# CONFIG_CRYPTO_STREEBOG is not set
# CONFIG_CRYPTO_TEST is not set
# CONFIG_CRYPTO_TGR192 is not set
# CONFIG_CRYPTO_TWOFISH is not set
# CONFIG_CRYPTO_USER is not set
# CONFIG_CRYPTO_USER_API_AEAD is not set
# CONFIG_CRYPTO_USER_API_HASH is not set
# CONFIG_CRYPTO_USER_API_RNG is not set
# CONFIG_CRYPTO_USER_API_SKCIPHER is not set
# CONFIG_CRYPTO_VMAC is not set
# CONFIG_CRYPTO_WP512 is not set
# CONFIG_CRYPTO_XCBC is not set
# CONFIG_CRYPTO_XTS is not set
# CONFIG_CRYPTO_XXHASH is not set
CONFIG_CRYPTO_ZSTD=y
# CONFIG_CYW_BCMDHD is not set
CONFIG_DEBUG_FS_ALLOW_ALL=y
# CONFIG_DEBUG_FS_ALLOW_NONE is not set
# CONFIG_DEBUG_FS_DISALLOW_MOUNT is not set
# CONFIG_DLM is not set
CONFIG_DNS_RESOLVER=y
# CONFIG_DRM_ANALOGIX_ANX6345 is not set
# CONFIG_DRM_ANALOGIX_ANX78XX is not set
# CONFIG_DRM_ARCPGU is not set
# CONFIG_DRM_ARMADA is not set
CONFIG_DRM_BRIDGE=y
# CONFIG_DRM_CDNS_DSI is not set
# CONFIG_DRM_CDNS_MHDP8546 is not set
# CONFIG_DRM_CHRONTEL_CH7033 is not set
# CONFIG_DRM_DEBUG_DP_MST_TOPOLOGY_REFS is not set
# CONFIG_DRM_DEBUG_MM is not set
# CONFIG_DRM_DEBUG_SELFTEST is not set
# CONFIG_DRM_DISPLAY_CONNECTOR is not set
# CONFIG_DRM_DP is not set
# CONFIG_DRM_DP_AUX_CHARDEV is not set
# CONFIG_DRM_DP_CEC is not set
CONFIG_DRM_EDID=y
# CONFIG_DRM_ETNAVIV is not set
# CONFIG_DRM_EXYNOS is not set
CONFIG_DRM_FBDEV_EMULATION=y
# CONFIG_DRM_FBDEV_LEAK_PHYS_SMEM is not set
CONFIG_DRM_FBDEV_OVERALLOC=100
# CONFIG_DRM_FSL_DCU is not set
CONFIG_DRM_GEM_CMA_HELPER=y
# CONFIG_DRM_GM12U320 is not set
# CONFIG_DRM_HDLCD is not set
# CONFIG_DRM_I2C_ADV7511 is not set
# CONFIG_DRM_I2C_CH7006 is not set
# CONFIG_DRM_I2C_NXP_TDA9950 is not set
# CONFIG_DRM_I2C_NXP_TDA998X is not set
# CONFIG_DRM_I2C_SIL164 is not set
# CONFIG_DRM_IGNORE_IOTCL_PERMIT is not set
# CONFIG_DRM_ITE_IT6161 is not set
CONFIG_DRM_KMS_FB_HELPER=y
CONFIG_DRM_KMS_HELPER=y
# CONFIG_DRM_KOMEDA is not set
# CONFIG_DRM_LEGACY is not set
# CONFIG_DRM_LIMA is not set
# CONFIG_DRM_LOAD_EDID_FIRMWARE is not set
# CONFIG_DRM_LONTIUM_LT9611 is not set
# CONFIG_DRM_LVDS_CODEC is not set
# CONFIG_DRM_MALI_DISPLAY is not set
# CONFIG_DRM_MAXIM_MAX96745 is not set
# CONFIG_DRM_MAXIM_MAX96752F is not set
# CONFIG_DRM_MAXIM_MAX96755F is not set
# CONFIG_DRM_MAXIM_MAX96776 is not set
# CONFIG_DRM_MCDE is not set
# CONFIG_DRM_MEGACHIPS_STDPXXXX_GE_B850V3_FW is not set
# CONFIG_DRM_MXSFB is not set
# CONFIG_DRM_NWL_MIPI_DSI is not set
# CONFIG_DRM_NXP_PTN3460 is not set
# CONFIG_DRM_OMAP is not set
CONFIG_DRM_PANEL=y
# CONFIG_DRM_PANEL_ARM_VERSATILE is not set
CONFIG_DRM_PANEL_BRIDGE=y
# CONFIG_DRM_PANEL_ILITEK_IL9322 is not set
# CONFIG_DRM_PANEL_LG_LB035Q02 is not set
# CONFIG_DRM_PANEL_LG_LG4573 is not set
# CONFIG_DRM_PANEL_LVDS is not set
# CONFIG_DRM_PANEL_MAXIM_DESERIALIZER is not set
# CONFIG_DRM_PANEL_NEC_NL8048HL11 is not set
# CONFIG_DRM_PANEL_NOVATEK_NT39016 is not set
# CONFIG_DRM_PANEL_OLIMEX_LCD_OLINUXINO is not set
CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y
# CONFIG_DRM_PANEL_SAMSUNG_LD9040 is not set
# CONFIG_DRM_PANEL_SAMSUNG_S6E63M0 is not set
# CONFIG_DRM_PANEL_SAMSUNG_S6E88A0_AMS452EF01 is not set
# CONFIG_DRM_PANEL_SAMSUNG_S6E8AA0 is not set
# CONFIG_DRM_PANEL_SEIKO_43WVF1G is not set
# CONFIG_DRM_PANEL_SHARP_LS037V7DW01 is not set
CONFIG_DRM_PANEL_SIMPLE=y
# CONFIG_DRM_PANEL_SITRONIX_ST7789V is not set
# CONFIG_DRM_PANEL_SONY_ACX565AKM is not set
# CONFIG_DRM_PANEL_TPO_TD028TTEC1 is not set
# CONFIG_DRM_PANEL_TPO_TD043MTEA1 is not set
# CONFIG_DRM_PANEL_TPO_TPG110 is not set
# CONFIG_DRM_PANFROST is not set
# CONFIG_DRM_PARADE_PS8622 is not set
# CONFIG_DRM_PARADE_PS8640 is not set
# CONFIG_DRM_PL111 is not set
# CONFIG_DRM_RCAR_DW_HDMI is not set
# CONFIG_DRM_RCAR_LVDS is not set
# CONFIG_DRM_RK1000_TVE is not set
CONFIG_DRM_ROCKCHIP=y
# CONFIG_DRM_ROCKCHIP_VVOP is not set
# CONFIG_DRM_ROHM_BU18XL82 is not set
CONFIG_DRM_SII902X=y
# CONFIG_DRM_SII9234 is not set
# CONFIG_DRM_SIL_SII8620 is not set
# CONFIG_DRM_SIMPLE_BRIDGE is not set
# CONFIG_DRM_STI is not set
# CONFIG_DRM_STM is not set
# CONFIG_DRM_THINE_THC63LVD1024 is not set
# CONFIG_DRM_TIDSS is not set
# CONFIG_DRM_TILCDC is not set
# CONFIG_DRM_TI_SN65DSI86 is not set
# CONFIG_DRM_TI_TFP410 is not set
# CONFIG_DRM_TI_TPD12S015 is not set
# CONFIG_DRM_TOSHIBA_TC358762 is not set
# CONFIG_DRM_TOSHIBA_TC358764 is not set
# CONFIG_DRM_TOSHIBA_TC358767 is not set
# CONFIG_DRM_TOSHIBA_TC358768 is not set
# CONFIG_DRM_TOSHIBA_TC358775 is not set
# CONFIG_DRM_TVE200 is not set
# CONFIG_DRM_UDL is not set
# CONFIG_DRM_VGEM is not set
# CONFIG_DRM_VKMS is not set
# CONFIG_ECRYPT_FS is not set
# CONFIG_EEPROM_93XX46 is not set
# CONFIG_EEPROM_AT25 is not set
# CONFIG_ENCRYPTED_KEYS is not set
# CONFIG_EXT4_DEBUG is not set
# CONFIG_EXT4_FS_POSIX_ACL is not set
# CONFIG_EXT4_FS_SECURITY is not set
CONFIG_EXT4_USE_FOR_EXT2=y
# CONFIG_EXTCON_ADC_JACK is not set
# CONFIG_EXTCON_FSA9480 is not set
# CONFIG_EXTCON_GPIO is not set
# CONFIG_EXTCON_MAX3355 is not set
# CONFIG_EXTCON_PTN5150 is not set
# CONFIG_EXTCON_RT8973A is not set
# CONFIG_EXTCON_SM5502 is not set
# CONFIG_EXTCON_USB_GPIO is not set
# CONFIG_EZX_PCAP is not set
CONFIG_FAT_DEFAULT_CODEPAGE=437
CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
# CONFIG_FAT_DEFAULT_UTF8 is not set
CONFIG_FAT_FS=y
# CONFIG_FB_ARMCLCD is not set
CONFIG_FB_CFB_COPYAREA=y
CONFIG_FB_CFB_FILLRECT=y
CONFIG_FB_CFB_IMAGEBLIT=y
CONFIG_FB_CMDLINE=y
CONFIG_FB_DEFERRED_IO=y
# CONFIG_FB_FOREIGN_ENDIAN is not set
# CONFIG_FB_IBM_GXT4500 is not set
# CONFIG_FB_METRONOME is not set
# CONFIG_FB_MODE_HELPERS is not set
CONFIG_FB_NOTIFY=y
# CONFIG_FB_OPENCORES is not set
# CONFIG_FB_S1D13XXX is not set
# CONFIG_FB_SIMPLE is not set
# CONFIG_FB_SMSCUFX is not set
# CONFIG_FB_SSD1307 is not set
CONFIG_FB_SYS_COPYAREA=y
CONFIG_FB_SYS_FILLRECT=y
CONFIG_FB_SYS_FOPS=y
CONFIG_FB_SYS_IMAGEBLIT=y
# CONFIG_FB_TFT is not set
# CONFIG_FB_TILEBLITTING is not set
# CONFIG_FB_UDL is not set
# CONFIG_FB_VIRTUAL is not set
# CONFIG_FIRMWARE_EDID is not set
CONFIG_FS_IOMAP=y
CONFIG_FS_MBCACHE=y
CONFIG_FS_POSIX_ACL=y
# CONFIG_FXOS8700_SPI is not set
# CONFIG_GCOV_KERNEL is not set
# CONFIG_GENERIC_IRQ_DEBUGFS is not set
# CONFIG_GPIO_74X164 is not set
# CONFIG_GPIO_MAX3191X is not set
# CONFIG_GPIO_MAX7301 is not set
# CONFIG_GPIO_MC33880 is not set
# CONFIG_GPIO_PISOSR is not set
# CONFIG_GPIO_XRA1403 is not set
CONFIG_GRACE_PERIOD=y
CONFIG_HDMI=y
# CONFIG_HI8435 is not set
# CONFIG_HID is not set
# CONFIG_HID_PID is not set
# CONFIG_HISI_HIKEY_USB is not set
CONFIG_I2C_ALGOBIT=y
# CONFIG_I2C_ARB_GPIO_CHALLENGE is not set
# CONFIG_I2C_DEMUX_PINCTRL is not set
# CONFIG_I2C_DIOLAN_U2C is not set
# CONFIG_I2C_GPIO_FAULT_INJECTOR is not set
# CONFIG_I2C_HID is not set
# CONFIG_I2C_MUX_GPIO is not set
# CONFIG_I2C_MUX_GPMUX is not set
# CONFIG_I2C_MUX_LTC4306 is not set
# CONFIG_I2C_MUX_MLXCPLD is not set
# CONFIG_I2C_MUX_PCA9541 is not set
# CONFIG_I2C_MUX_PCA954x is not set
# CONFIG_I2C_MUX_PINCTRL is not set
# CONFIG_I2C_MUX_REG is not set
# CONFIG_I2C_ROBOTFUZZ_OSIF is not set
# CONFIG_I2C_TINY_USB is not set
# CONFIG_IIO_SSP_SENSORHUB is not set
# CONFIG_INET6_AH is not set
# CONFIG_INET6_ESP is not set
# CONFIG_INET6_IPCOMP is not set
# CONFIG_INFINEON_DHD is not set
# CONFIG_INPUT_EVBUG is not set
CONFIG_INPUT_EVDEV=y
# CONFIG_INPUT_FF_MEMLESS is not set
# CONFIG_INPUT_JOYDEV is not set
# CONFIG_INPUT_JOYSTICK is not set
CONFIG_INPUT_KEYBOARD=y
# CONFIG_INPUT_MATRIXKMAP is not set
# CONFIG_INPUT_MISC is not set
# CONFIG_INPUT_MOUSE is not set
# CONFIG_INPUT_MOUSEDEV is not set
# CONFIG_INPUT_POLLDEV is not set
# CONFIG_INPUT_SPARSEKMAP is not set
# CONFIG_INPUT_TABLET is not set
# CONFIG_INPUT_TOUCHSCREEN is not set
# CONFIG_INV_ICM42600_SPI is not set
# CONFIG_INV_MPU6050_SPI is not set
# CONFIG_IPV6_MIP6 is not set
# CONFIG_IPV6_MROUTE is not set
# CONFIG_IPV6_MULTIPLE_TABLES is not set
# CONFIG_IPV6_OPTIMISTIC_DAD is not set
# CONFIG_IPV6_ROUTER_PREF is not set
# CONFIG_IPV6_RPL_LWTUNNEL is not set
# CONFIG_IPV6_SEG6_HMAC is not set
# CONFIG_IPV6_SEG6_LWTUNNEL is not set
# CONFIG_IPV6_SIT is not set
# CONFIG_IPV6_TUNNEL is not set
# CONFIG_IPV6_VTI is not set
CONFIG_JBD2=y
# CONFIG_JBD2_DEBUG is not set
# CONFIG_JFFS2_CMODE_FAVOURLZO is not set
# CONFIG_JFFS2_CMODE_NONE is not set
CONFIG_JFFS2_CMODE_PRIORITY=y
# CONFIG_JFFS2_CMODE_SIZE is not set
CONFIG_JFFS2_COMPRESSION_OPTIONS=y
CONFIG_JFFS2_FS_DEBUG=0
# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
CONFIG_JFFS2_FS_WRITEBUFFER=y
# CONFIG_JFFS2_FS_XATTR is not set
# CONFIG_JFFS2_LZO is not set
# CONFIG_JFFS2_RTIME is not set
# CONFIG_JFFS2_RUBIN is not set
# CONFIG_JFFS2_SUMMARY is not set
CONFIG_JFFS2_ZLIB=y
CONFIG_KEYBOARD_ADC=y
# CONFIG_KEYBOARD_ADP5588 is not set
# CONFIG_KEYBOARD_ADP5589 is not set
# CONFIG_KEYBOARD_ATKBD is not set
# CONFIG_KEYBOARD_BCM is not set
# CONFIG_KEYBOARD_CAP11XX is not set
# CONFIG_KEYBOARD_DLINK_DIR685 is not set
# CONFIG_KEYBOARD_GPIO is not set
# CONFIG_KEYBOARD_GPIO_POLLED is not set
# CONFIG_KEYBOARD_LKKBD is not set
# CONFIG_KEYBOARD_LM8333 is not set
# CONFIG_KEYBOARD_MATRIX is not set
# CONFIG_KEYBOARD_MAX7359 is not set
# CONFIG_KEYBOARD_MCS is not set
# CONFIG_KEYBOARD_MPR121 is not set
# CONFIG_KEYBOARD_NEWTON is not set
# CONFIG_KEYBOARD_OMAP4 is not set
# CONFIG_KEYBOARD_OPENCORES is not set
# CONFIG_KEYBOARD_QT1050 is not set
# CONFIG_KEYBOARD_QT1070 is not set
# CONFIG_KEYBOARD_QT2160 is not set
# CONFIG_KEYBOARD_SAMSUNG is not set
# CONFIG_KEYBOARD_STOWAWAY is not set
# CONFIG_KEYBOARD_SUNKBD is not set
# CONFIG_KEYBOARD_TCA6416 is not set
# CONFIG_KEYBOARD_TCA8418 is not set
# CONFIG_KEYBOARD_XTKBD is not set
# CONFIG_KEYS_REQUEST_CACHE is not set
# CONFIG_KEY_DH_OPERATIONS is not set
# CONFIG_KS7010 is not set
# CONFIG_LATTICE_ECP3_CONFIG is not set
CONFIG_LOCKD=y
CONFIG_LOCKD_V4=y
# CONFIG_LOCK_EVENT_COUNTS is not set
# CONFIG_LOGO is not set
# CONFIG_LTC1660 is not set
# CONFIG_LTC2496 is not set
# CONFIG_LTC2632 is not set
# CONFIG_LTC2983 is not set
# CONFIG_LTE_GDM724X is not set
CONFIG_LZO_COMPRESS=y
CONFIG_LZO_DECOMPRESS=y
CONFIG_MAC80211=m
# CONFIG_MAC80211_DEBUGFS is not set
# CONFIG_MAC80211_DEBUG_MENU is not set
CONFIG_MAC80211_HAS_RC=y
# CONFIG_MAC80211_HWSIM is not set
# CONFIG_MAC80211_MESH is not set
# CONFIG_MAC80211_MESSAGE_TRACING is not set
CONFIG_MAC80211_RC_DEFAULT="minstrel_ht"
CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y
CONFIG_MAC80211_RC_MINSTREL=y
CONFIG_MAC80211_STA_HASH_MAX_SIZE=0
# CONFIG_MANAGER_SBS is not set
CONFIG_MANDATORY_FILE_LOCKING=y
# CONFIG_MAX1027 is not set
# CONFIG_MAX11100 is not set
# CONFIG_MAX1118 is not set
# CONFIG_MAX1241 is not set
# CONFIG_MAX31856 is not set
# CONFIG_MAX5481 is not set
# CONFIG_MAX5487 is not set
# CONFIG_MAXIM_THERMOCOUPLE is not set
# CONFIG_MCP320X is not set
# CONFIG_MCP3911 is not set
# CONFIG_MCP41010 is not set
# CONFIG_MCP4131 is not set
# CONFIG_MCP4922 is not set
# CONFIG_MDIO_MVUSB is not set
# CONFIG_MEDIA_USB_SUPPORT is not set
# CONFIG_MFD_ARIZONA_SPI is not set
# CONFIG_MFD_CPCAP is not set
# CONFIG_MFD_DA9052_SPI is not set
# CONFIG_MFD_DLN2 is not set
# CONFIG_MFD_INTEL_M10_BMC is not set
# CONFIG_MFD_MC13XXX_SPI is not set
# CONFIG_MFD_RK806_SPI is not set
# CONFIG_MFD_TPS65912_SPI is not set
# CONFIG_MFD_VIPERBOARD is not set
# CONFIG_MFD_WM831X_SPI is not set
# CONFIG_MICREL_KS8995MA is not set
# CONFIG_MINIX_SUBPARTITION is not set
# CONFIG_MISC_RTSX_USB is not set
# CONFIG_MMA7455_SPI is not set
# CONFIG_MMC_ARMMMCI is not set
CONFIG_MMC_BLOCK=y
CONFIG_MMC_BLOCK_MINORS=32
# CONFIG_MMC_CQHCI is not set
# CONFIG_MMC_DEBUG is not set
CONFIG_MMC_DW=y
# CONFIG_MMC_DW_BLUEFIELD is not set
# CONFIG_MMC_DW_EXYNOS is not set
# CONFIG_MMC_DW_HI3798CV200 is not set
# CONFIG_MMC_DW_K3 is not set
CONFIG_MMC_DW_PLTFM=y
CONFIG_MMC_DW_ROCKCHIP=y
# CONFIG_MMC_HSQ is not set
# CONFIG_MMC_MTK is not set
CONFIG_MMC_QUEUE_DEPTH=1
# CONFIG_MMC_SDHCI is not set
# CONFIG_MMC_SPI is not set
# CONFIG_MMC_TEST is not set
# CONFIG_MMC_USDHI6ROL0 is not set
# CONFIG_MMC_USHC is not set
# CONFIG_MMC_VUB300 is not set
# CONFIG_MOST is not set
# CONFIG_MOXTET is not set
CONFIG_MPILIB=y
# CONFIG_MPL115_SPI is not set
CONFIG_MTD_BLKDEVS=y
# CONFIG_MTD_DATAFLASH is not set
# CONFIG_MTD_MCHP23K256 is not set
CONFIG_MTD_NAND_BBT_USING_FLASH=y
CONFIG_MTD_NAND_CORE=y
CONFIG_MTD_SPI_NAND=y
CONFIG_MTD_SPI_NOR=y
# CONFIG_MTD_SPI_NOR_USE_4K_SECTORS is not set
# CONFIG_MTD_SST25L is not set
CONFIG_MTD_UBI_BEB_LIMIT=20
CONFIG_MTD_UBI_BLOCK=y
# CONFIG_MTD_UBI_FASTMAP is not set
# CONFIG_MTD_UBI_GLUEBI is not set
CONFIG_MTD_UBI_WL_THRESHOLD=4096
# CONFIG_NETDEVSIM is not set
# CONFIG_NFSD is not set
CONFIG_NFS_ACL_SUPPORT=y
CONFIG_NFS_COMMON=y
CONFIG_NFS_DISABLE_UDP_SUPPORT=y
CONFIG_NFS_FS=y
CONFIG_NFS_USE_KERNEL_DNS=y
# CONFIG_NFS_USE_LEGACY_DNS is not set
CONFIG_NFS_V2=y
CONFIG_NFS_V3=y
CONFIG_NFS_V3_ACL=y
CONFIG_NFS_V4=y
# CONFIG_NFS_V4_1 is not set
# CONFIG_NL80211_TESTMODE is not set
# CONFIG_NOP_USB_XCEIV is not set
# CONFIG_NVME_TARGET is not set
# CONFIG_OCFS2_FS is not set
CONFIG_OID_REGISTRY=y
# CONFIG_PERSISTENT_KEYRINGS is not set
# CONFIG_PHY_CPCAP_USB is not set
# CONFIG_PHY_MAPPHONE_MDM6600 is not set
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
# CONFIG_PHY_ROCKCHIP_NANENG_USB2 is not set
# CONFIG_PI433 is not set
CONFIG_PKCS7_MESSAGE_PARSER=y
# CONFIG_PKCS7_TEST_KEY is not set
# CONFIG_PKCS8_PRIVATE_KEY_PARSER is not set
# CONFIG_PRISM2_USB is not set
# CONFIG_PWRSEQ_EMMC is not set
CONFIG_PWRSEQ_SIMPLE=y
# CONFIG_R8188EU is not set
# CONFIG_R8712U is not set
# CONFIG_RC_CORE is not set
CONFIG_REGMAP_SPI=y
# CONFIG_REGULATOR_RASPBERRYPI_TOUCHSCREEN_ATTINY is not set
# CONFIG_REGULATOR_TPS6524X is not set
# CONFIG_RMI4_CORE is not set
# CONFIG_ROCKCHIP_ANALOGIX_DP is not set
# CONFIG_ROCKCHIP_CDN_DP is not set
# CONFIG_ROCKCHIP_DRM_CUBIC_LUT is not set
# CONFIG_ROCKCHIP_DRM_DEBUG is not set
# CONFIG_ROCKCHIP_DRM_DIRECT_SHOW is not set
# CONFIG_ROCKCHIP_DW_DP is not set
# CONFIG_ROCKCHIP_DW_HDCP2 is not set
# CONFIG_ROCKCHIP_DW_HDMI is not set
# CONFIG_ROCKCHIP_DW_MIPI_DSI is not set
# CONFIG_ROCKCHIP_INNO_HDMI is not set
# CONFIG_ROCKCHIP_LVDS is not set
# CONFIG_ROCKCHIP_MMC_VENDOR_STORAGE is not set
CONFIG_ROCKCHIP_MTD_VENDOR_STORAGE=y
# CONFIG_ROCKCHIP_REMOTECTL is not set
CONFIG_ROCKCHIP_RGA_DEBUGGER=y
# CONFIG_ROCKCHIP_RGA_DEBUG_FS is not set
CONFIG_ROCKCHIP_RGB=y
# CONFIG_ROCKCHIP_RK3066_HDMI is not set
# CONFIG_ROCKCHIP_RKNPU_DEBUG_FS is not set
# CONFIG_ROCKCHIP_RKNPU_DRM_GEM is not set
CONFIG_ROCKCHIP_RVE_DEBUGGER=y
# CONFIG_ROCKCHIP_RVE_DEBUG_FS is not set
# CONFIG_ROCKCHIP_VCONN is not set
CONFIG_ROCKCHIP_VOP=y
# CONFIG_ROCKCHIP_VOP2 is not set
# CONFIG_RTC_DRV_DS1302 is not set
# CONFIG_RTC_DRV_DS1305 is not set
# CONFIG_RTC_DRV_DS1343 is not set
# CONFIG_RTC_DRV_DS1347 is not set
# CONFIG_RTC_DRV_DS1390 is not set
# CONFIG_RTC_DRV_M41T93 is not set
# CONFIG_RTC_DRV_M41T94 is not set
# CONFIG_RTC_DRV_MAX6902 is not set
# CONFIG_RTC_DRV_MAX6916 is not set
# CONFIG_RTC_DRV_MCP795 is not set
# CONFIG_RTC_DRV_PCF2123 is not set
# CONFIG_RTC_DRV_R9701 is not set
# CONFIG_RTC_DRV_RS5C348 is not set
# CONFIG_RTC_DRV_RX4581 is not set
# CONFIG_RTC_DRV_RX6110 is not set
# CONFIG_RTL8723BS is not set
# CONFIG_RTLLIB is not set
# CONFIG_SCA3000 is not set
# CONFIG_SDIO_UART is not set
# CONFIG_SECONDARY_TRUSTED_KEYRING is not set
# CONFIG_SENSORS_HMC5843_SPI is not set
# CONFIG_SENSORS_LIS3_I2C is not set
# CONFIG_SENSORS_LIS3_SPI is not set
# CONFIG_SENSORS_RM3100_SPI is not set
# CONFIG_SENSOR_DEVICE is not set
# CONFIG_SERIAL_IFX6X60 is not set
# CONFIG_SERIAL_MAX3100 is not set
# CONFIG_SERIAL_MAX310X is not set
CONFIG_SGL_ALLOC=y
# CONFIG_SIGNED_PE_FILE_VERIFICATION is not set
# CONFIG_SND_BCD2000 is not set
CONFIG_SND_JACK_INPUT_DEV=y
# CONFIG_SND_SOC_ADAU1761_SPI is not set
# CONFIG_SND_SOC_AK4104 is not set
# CONFIG_SND_SOC_CS4271_SPI is not set
# CONFIG_SND_SOC_CS42L52 is not set
# CONFIG_SND_SOC_CS42L56 is not set
# CONFIG_SND_SOC_ES8328_SPI is not set
# CONFIG_SND_SOC_PCM179X_SPI is not set
# CONFIG_SND_SOC_PCM186X_SPI is not set
# CONFIG_SND_SOC_PCM3060_SPI is not set
# CONFIG_SND_SOC_PCM3168A_SPI is not set
# CONFIG_SND_SOC_PCM512x_SPI is not set
# CONFIG_SND_SOC_RK3399_GRU_SOUND is not set
# CONFIG_SND_SOC_SSM2602_SPI is not set
# CONFIG_SND_SOC_TLV320AIC23_SPI is not set
# CONFIG_SND_SOC_TLV320AIC32X4_SPI is not set
# CONFIG_SND_SOC_WM8770 is not set
# CONFIG_SND_SOC_WM8804_SPI is not set
# CONFIG_SND_SOC_WM8962 is not set
# CONFIG_SND_SOC_ZL38060 is not set
# CONFIG_SND_SPI is not set
CONFIG_SND_USB=y
# CONFIG_SND_USB_6FIRE is not set
# CONFIG_SND_USB_AUDIO is not set
# CONFIG_SND_USB_CAIAQ is not set
# CONFIG_SND_USB_HIFACE is not set
# CONFIG_SND_USB_POD is not set
# CONFIG_SND_USB_PODHD is not set
# CONFIG_SND_USB_TONEPORT is not set
# CONFIG_SND_USB_UA101 is not set
# CONFIG_SND_USB_VARIAX is not set
# CONFIG_SOLARIS_X86_PARTITION is not set
# CONFIG_SPI_ALTERA is not set
# CONFIG_SPI_AMD is not set
# CONFIG_SPI_AXI_SPI_ENGINE is not set
# CONFIG_SPI_BITBANG is not set
# CONFIG_SPI_CADENCE is not set
# CONFIG_SPI_CADENCE_QUADSPI is not set
# CONFIG_SPI_DEBUG is not set
# CONFIG_SPI_DESIGNWARE is not set
# CONFIG_SPI_FSL_SPI is not set
# CONFIG_SPI_GPIO is not set
# CONFIG_SPI_LOOPBACK_TEST is not set
CONFIG_SPI_MASTER=y
CONFIG_SPI_MEM=y
# CONFIG_SPI_MUX is not set
# CONFIG_SPI_MXIC is not set
# CONFIG_SPI_NXP_FLEXSPI is not set
# CONFIG_SPI_OC_TINY is not set
# CONFIG_SPI_PL022 is not set
CONFIG_SPI_ROCKCHIP=y
# CONFIG_SPI_ROCKCHIP_MISCDEV is not set
CONFIG_SPI_ROCKCHIP_SFC=y
# CONFIG_SPI_SC18IS602 is not set
# CONFIG_SPI_SIFIVE is not set
# CONFIG_SPI_SLAVE is not set
CONFIG_SPI_SPIDEV=y
# CONFIG_SPI_TLE62X0 is not set
# CONFIG_SPI_XCOMM is not set
# CONFIG_SPI_XILINX is not set
# CONFIG_SPI_ZYNQMP_GQSPI is not set
CONFIG_SUNRPC=y
# CONFIG_SUNRPC_DEBUG is not set
CONFIG_SUNRPC_GSS=y
# CONFIG_SYSTEM_BLACKLIST_KEYRING is not set
CONFIG_SYSTEM_DATA_VERIFICATION=y
# CONFIG_SYSTEM_EXTRA_CERTIFICATE is not set
CONFIG_SYSTEM_TRUSTED_KEYRING=y
CONFIG_SYSTEM_TRUSTED_KEYS=""
# CONFIG_TINYDRM_HX8357D is not set
# CONFIG_TINYDRM_ILI9225 is not set
# CONFIG_TINYDRM_ILI9341 is not set
# CONFIG_TINYDRM_ILI9486 is not set
# CONFIG_TINYDRM_MI0283QT is not set
# CONFIG_TINYDRM_REPAPER is not set
# CONFIG_TINYDRM_ST7586 is not set
# CONFIG_TINYDRM_ST7735R is not set
# CONFIG_TI_ADC0832 is not set
# CONFIG_TI_ADC084S021 is not set
# CONFIG_TI_ADC108S102 is not set
# CONFIG_TI_ADC12138 is not set
# CONFIG_TI_ADC128S052 is not set
# CONFIG_TI_ADC161S626 is not set
# CONFIG_TI_ADS124S08 is not set
# CONFIG_TI_ADS7950 is not set
# CONFIG_TI_ADS8344 is not set
# CONFIG_TI_ADS8688 is not set
# CONFIG_TI_DAC082S085 is not set
# CONFIG_TI_DAC7311 is not set
# CONFIG_TI_DAC7612 is not set
# CONFIG_TI_TLC4541 is not set
# CONFIG_TYPEC is not set
# CONFIG_UBIFS_ATIME_SUPPORT is not set
CONFIG_UBIFS_FS=y
CONFIG_UBIFS_FS_ADVANCED_COMPR=y
# CONFIG_UBIFS_FS_AUTHENTICATION is not set
CONFIG_UBIFS_FS_LZO=y
CONFIG_UBIFS_FS_SECURITY=y
CONFIG_UBIFS_FS_XATTR=y
CONFIG_UBIFS_FS_ZLIB=y
# CONFIG_UBIFS_FS_ZSTD is not set
# CONFIG_UNIXWARE_DISKLABEL is not set
CONFIG_USB=y
# CONFIG_USBIP_CORE is not set
# CONFIG_USBPCWATCHDOG is not set
# CONFIG_USB_ACM is not set
# CONFIG_USB_ADUTUX is not set
# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
# CONFIG_USB_APPLEDISPLAY is not set
CONFIG_USB_ARCH_HAS_HCD=y
# CONFIG_USB_AUDIO is not set
CONFIG_USB_AUTOSUSPEND_DELAY=2
# CONFIG_USB_BDC_UDC is not set
# CONFIG_USB_C67X00_HCD is not set
# CONFIG_USB_CDC_COMPOSITE is not set
# CONFIG_USB_CDNS3 is not set
# CONFIG_USB_CHAOSKEY is not set
# CONFIG_USB_CHIPIDEA is not set
CONFIG_USB_COMMON=y
CONFIG_USB_CONFIGFS=y
# CONFIG_USB_CONFIGFS_ACM is not set
# CONFIG_USB_CONFIGFS_ECM is not set
# CONFIG_USB_CONFIGFS_ECM_SUBSET is not set
# CONFIG_USB_CONFIGFS_EEM is not set
# CONFIG_USB_CONFIGFS_F_AUDIO_SRC is not set
CONFIG_USB_CONFIGFS_F_FS=y
CONFIG_USB_CONFIGFS_F_HID=y
# CONFIG_USB_CONFIGFS_F_LB_SS is not set
# CONFIG_USB_CONFIGFS_F_MIDI is not set
# CONFIG_USB_CONFIGFS_F_PRINTER is not set
CONFIG_USB_CONFIGFS_F_UAC1=y
# CONFIG_USB_CONFIGFS_F_UAC1_LEGACY is not set
CONFIG_USB_CONFIGFS_F_UAC2=y
CONFIG_USB_CONFIGFS_F_UVC=y
CONFIG_USB_CONFIGFS_MASS_STORAGE=y
# CONFIG_USB_CONFIGFS_NCM is not set
# CONFIG_USB_CONFIGFS_OBEX is not set
# CONFIG_USB_CONFIGFS_RNDIS is not set
# CONFIG_USB_CONFIGFS_SERIAL is not set
CONFIG_USB_CONFIGFS_UEVENT=y
# CONFIG_USB_CONN_GPIO is not set
# CONFIG_USB_CYPRESS_CY7C63 is not set
# CONFIG_USB_CYTHERM is not set
CONFIG_USB_DEFAULT_PERSIST=y
# CONFIG_USB_DUMMY_HCD is not set
# CONFIG_USB_DWC2 is not set
CONFIG_USB_DWC3=y
CONFIG_USB_DWC3_DUAL_ROLE=y
# CONFIG_USB_DWC3_GADGET is not set
# CONFIG_USB_DWC3_HOST is not set
CONFIG_USB_DWC3_OF_SIMPLE=y
# CONFIG_USB_DYNAMIC_MINORS is not set
# CONFIG_USB_EHCI_HCD is not set
# CONFIG_USB_EHSET_TEST_FIXTURE is not set
# CONFIG_USB_EMI26 is not set
# CONFIG_USB_EMI62 is not set
# CONFIG_USB_ETH is not set
# CONFIG_USB_EZUSB_FX2 is not set
# CONFIG_USB_FEW_INIT_RETRIES is not set
# CONFIG_USB_FOTG210_HCD is not set
# CONFIG_USB_FOTG210_UDC is not set
# CONFIG_USB_FTDI_ELAN is not set
# CONFIG_USB_FUNCTIONFS is not set
# CONFIG_USB_FUSB300 is not set
CONFIG_USB_F_FS=y
CONFIG_USB_F_HID=y
CONFIG_USB_F_UAC1=y
CONFIG_USB_F_UAC2=y
CONFIG_USB_F_UVC=y
CONFIG_USB_F_MASS_STORAGE=y
CONFIG_USB_GADGET=y
# CONFIG_USB_GADGETFS is not set
# CONFIG_USB_GADGET_DEBUG is not set
# CONFIG_USB_GADGET_DEBUG_FILES is not set
# CONFIG_USB_GADGET_DEBUG_FS is not set
CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS=2
CONFIG_USB_GADGET_VBUS_DRAW=2
# CONFIG_USB_GADGET_XILINX is not set
# CONFIG_USB_GPIO_VBUS is not set
# CONFIG_USB_GR_UDC is not set
# CONFIG_USB_G_ACM_MS is not set
# CONFIG_USB_G_DBGP is not set
# CONFIG_USB_G_HID is not set
# CONFIG_USB_G_MULTI is not set
# CONFIG_USB_G_NCM is not set
# CONFIG_USB_G_PRINTER is not set
# CONFIG_USB_G_SERIAL is not set
# CONFIG_USB_G_WEBCAM is not set
# CONFIG_USB_HCD_TEST_MODE is not set
# CONFIG_USB_HID is not set
# CONFIG_USB_HSIC_USB3503 is not set
# CONFIG_USB_HSIC_USB4604 is not set
# CONFIG_USB_HUB_USB251XB is not set
# CONFIG_USB_IDMOUSE is not set
# CONFIG_USB_IOWARRIOR is not set
# CONFIG_USB_ISIGHTFW is not set
# CONFIG_USB_ISP116X_HCD is not set
# CONFIG_USB_ISP1301 is not set
# CONFIG_USB_ISP1760 is not set
# CONFIG_USB_KBD is not set
# CONFIG_USB_LCD is not set
# CONFIG_USB_LD is not set
# CONFIG_USB_LEGOTOWER is not set
CONFIG_USB_LIBCOMPOSITE=y
# CONFIG_USB_LINK_LAYER_TEST is not set
# CONFIG_USB_M66592 is not set
# CONFIG_USB_MASS_STORAGE is not set
# CONFIG_USB_MAX3420_UDC is not set
# CONFIG_USB_MAX3421_HCD is not set
# CONFIG_USB_MDC800 is not set
# CONFIG_USB_MIDI_GADGET is not set
# CONFIG_USB_MON is not set
# CONFIG_USB_MOUSE is not set
# CONFIG_USB_MUSB_HDRC is not set
# CONFIG_USB_MV_U3D is not set
# CONFIG_USB_MV_UDC is not set
# CONFIG_USB_NET2272 is not set
# CONFIG_USB_NET_DRIVERS is not set
# CONFIG_USB_NET_RNDIS_WLAN is not set
# CONFIG_USB_OHCI_HCD is not set
# CONFIG_USB_OTG is not set
# CONFIG_USB_OTG_DISABLE_EXTERNAL_HUB is not set
# CONFIG_USB_OTG_PRODUCTLIST is not set
# CONFIG_USB_OXU210HP_HCD is not set
# CONFIG_USB_PRINTER is not set
# CONFIG_USB_PXA27X is not set
# CONFIG_USB_R8A66597 is not set
# CONFIG_USB_R8A66597_HCD is not set
# CONFIG_USB_RAW_GADGET is not set
CONFIG_USB_ROLE_SWITCH=y
# CONFIG_USB_SERIAL is not set
# CONFIG_USB_SEVSEG is not set
# CONFIG_USB_SL811_HCD is not set
# CONFIG_USB_SNP_UDC_PLAT is not set
# CONFIG_USB_TEST is not set
# CONFIG_USB_TMC is not set
# CONFIG_USB_TRANCEVIBRATOR is not set
# CONFIG_USB_ULPI is not set
# CONFIG_USB_ULPI_BUS is not set
CONFIG_USB_U_AUDIO=y
# CONFIG_USB_WDM is not set
# CONFIG_USB_XHCI_DBGCAP is not set
CONFIG_USB_XHCI_HCD=y
# CONFIG_USB_XHCI_PCI_RENESAS is not set
CONFIG_USB_XHCI_PLATFORM=y
# CONFIG_USB_YUREX is not set
# CONFIG_USB_ZERO is not set
CONFIG_VIDEOMODE_HELPERS=y
# CONFIG_VIDEO_GS1662 is not set
# CONFIG_VIDEO_MAX9286 is not set
# CONFIG_VIDEO_ROCKCHIP_PREISP is not set
# CONFIG_VIDEO_S5C73M3 is not set
# CONFIG_VIRT_WIFI is not set
# CONFIG_VT6656 is not set
CONFIG_WEXT_CORE=y
CONFIG_WEXT_PRIV=y
CONFIG_WEXT_PROC=y
# CONFIG_WFX is not set
CONFIG_WIFI_BUILD_MODULE=y
# CONFIG_WIFI_GENERATE_RANDOM_MAC_ADDR is not set
# CONFIG_WIFI_LOAD_DRIVER_WHEN_KERNEL_BOOTUP is not set
CONFIG_WIRELESS_EXT=y
# CONFIG_WIRELESS_WDS is not set
# CONFIG_WLAN_VENDOR_ADMTEK is not set
# CONFIG_WLAN_VENDOR_ATH is not set
# CONFIG_WLAN_VENDOR_ATMEL is not set
# CONFIG_WLAN_VENDOR_BROADCOM is not set
# CONFIG_WLAN_VENDOR_CISCO is not set
# CONFIG_WLAN_VENDOR_INTEL is not set
# CONFIG_WLAN_VENDOR_INTERSIL is not set
# CONFIG_WLAN_VENDOR_MARVELL is not set
# CONFIG_WLAN_VENDOR_MEDIATEK is not set
# CONFIG_WLAN_VENDOR_MICROCHIP is not set
# CONFIG_WLAN_VENDOR_QUANTENNA is not set
# CONFIG_WLAN_VENDOR_RALINK is not set
# CONFIG_WLAN_VENDOR_REALTEK is not set
# CONFIG_WLAN_VENDOR_RSI is not set
# CONFIG_WLAN_VENDOR_ST is not set
# CONFIG_WLAN_VENDOR_TI is not set
# CONFIG_WLAN_VENDOR_ZYDAS is not set
CONFIG_WL_ROCKCHIP=m
CONFIG_X509_CERTIFICATE_PARSER=y
CONFIG_ZLIB_DEFLATE=y
CONFIG_ZLIB_INFLATE=y
CONFIG_ZSTD_COMPRESS=y
CONFIG_ZSTD_DECOMPRESS=y

3
arch/arm/configs/rv1106-evb.config
View File

@@ -302,9 +302,7 @@ CONFIG_DRM_KMS_HELPER=y
# CONFIG_DRM_LVDS_CODEC is not set
# CONFIG_DRM_MALI_DISPLAY is not set
# CONFIG_DRM_MAXIM_MAX96745 is not set
# CONFIG_DRM_MAXIM_MAX96752F is not set
# CONFIG_DRM_MAXIM_MAX96755F is not set
# CONFIG_DRM_MAXIM_MAX96776 is not set
# CONFIG_DRM_MCDE is not set
# CONFIG_DRM_MEGACHIPS_STDPXXXX_GE_B850V3_FW is not set
# CONFIG_DRM_MXSFB is not set
@@ -610,6 +608,7 @@ CONFIG_MTD_NAND_BBT_USING_FLASH=y
CONFIG_MTD_NAND_CORE=y
CONFIG_MTD_SPI_NAND=y
CONFIG_MTD_SPI_NOR=y
CONFIG_MTD_SPI_NOR_MISC=y
# CONFIG_MTD_SPI_NOR_USE_4K_SECTORS is not set
# CONFIG_MTD_SST25L is not set
CONFIG_MTD_UBI_BEB_LIMIT=20

1
arch/arm/configs/rv1106-ipc.config
View File

@@ -161,6 +161,7 @@ CONFIG_MTD_BLKDEVS=y
# CONFIG_MTD_MCHP23K256 is not set
# CONFIG_MTD_SPI_NAND is not set
CONFIG_MTD_SPI_NOR=y
CONFIG_MTD_SPI_NOR_MISC=y
# CONFIG_MTD_SPI_NOR_USE_4K_SECTORS is not set
# CONFIG_MTD_SST25L is not set
# CONFIG_PI433 is not set

20
arch/arm/configs/rv1106-smart-door.config
View File

@@ -14,11 +14,14 @@ CONFIG_EEPROM_AT24=y
CONFIG_EXTCON=m
CONFIG_JFFS2_FS=y
CONFIG_KEYS=y
CONFIG_MAILBOX=y
CONFIG_MTD_BLKDEVS=m
CONFIG_MTD_BLOCK=m
CONFIG_NVMEM_SYSFS=y
CONFIG_RFKILL=y
CONFIG_RK803=y
CONFIG_ROCKCHIP_HW_DECOMPRESS_USER=y
CONFIG_ROCKCHIP_VENDOR_STORAGE=y
CONFIG_ROCKCHIP_VENDOR_STORAGE=m
CONFIG_SPI=y
# CONFIG_SQUASHFS is not set
CONFIG_USB_SUPPORT=y
@@ -85,6 +88,10 @@ CONFIG_WLAN=y
# CONFIG_ADXRS290 is not set
# CONFIG_ADXRS450 is not set
# CONFIG_AFE4403 is not set
# CONFIG_ALTERA_MBOX is not set
# CONFIG_ARM_MHU is not set
# CONFIG_ARM_SCMI_PROTOCOL is not set
# CONFIG_ARM_SCPI_PROTOCOL is not set
# CONFIG_AS3935 is not set
CONFIG_ASN1=y
CONFIG_ASSOCIATIVE_ARRAY=y
@@ -183,6 +190,7 @@ CONFIG_MAC80211_RC_DEFAULT="minstrel_ht"
CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y
CONFIG_MAC80211_RC_MINSTREL=y
CONFIG_MAC80211_STA_HASH_MAX_SIZE=0
# CONFIG_MAILBOX_TEST is not set
# CONFIG_MAX1027 is not set
# CONFIG_MAX11100 is not set
# CONFIG_MAX1118 is not set
@@ -211,10 +219,11 @@ CONFIG_MAC80211_STA_HASH_MAX_SIZE=0
# CONFIG_MOXTET is not set
CONFIG_MPILIB=y
# CONFIG_MPL115_SPI is not set
# CONFIG_MTD_BLOCK_RO is not set
# CONFIG_MTD_DATAFLASH is not set
# CONFIG_MTD_MCHP23K256 is not set
# CONFIG_MTD_SPI_NAND is not set
CONFIG_MTD_SPI_NOR=y
CONFIG_MTD_SPI_NOR=m
# CONFIG_MTD_SPI_NOR_USE_4K_SECTORS is not set
# CONFIG_MTD_SST25L is not set
# CONFIG_NL80211_TESTMODE is not set
@@ -230,12 +239,17 @@ CONFIG_PHY_ROCKCHIP_INNO_USB2=m
# CONFIG_PI433 is not set
CONFIG_PKCS7_MESSAGE_PARSER=y
# CONFIG_PKCS8_PRIVATE_KEY_PARSER is not set
# CONFIG_PL320_MBOX is not set
# CONFIG_PLATFORM_MHU is not set
CONFIG_REGMAP_SPI=y
# CONFIG_REGULATOR_TPS6524X is not set
# CONFIG_RFKILL_GPIO is not set
CONFIG_RFKILL_RK=y
CONFIG_ROCKCHIP_MBOX=y
# CONFIG_ROCKCHIP_MMC_VENDOR_STORAGE is not set
CONFIG_ROCKCHIP_MTD_VENDOR_STORAGE=y
CONFIG_ROCKCHIP_MTD_VENDOR_STORAGE=m
CONFIG_ROCKCHIP_THUNDER_BOOT_SERVICE=y
# CONFIG_RPMSG_QCOM_GLINK_RPM is not set
# CONFIG_RTC_DRV_DS1302 is not set
# CONFIG_RTC_DRV_DS1305 is not set
# CONFIG_RTC_DRV_DS1343 is not set

3
arch/arm64/boot/dts/rockchip/Makefile
View File

@@ -115,6 +115,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-evb1-lp4-v10.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-evb1-lp4-v10-ipc-6x-linux.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-evb1-lp4-v10-linux.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-evb1-lp4-v10-linux-ipc.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-evb1-lp4-v10-lt6911uxe.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-evb2-lp4-v10.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-evb2-lp4-v10-edp.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-evb2-lp4-v10-edp2dp.dtb
@@ -132,6 +133,8 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-evb6-lp4-v10-linux.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-evb7-lp4-v10.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-evb7-lp4-v10-linux.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-evb7-lp4-v10-rk1608-ipc-8x-linux.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-h0-v10.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-h0-v10-linux.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-nvr-demo-v10.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-nvr-demo-v10-android.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-nvr-demo-v10-spi-nand.dtb

2
arch/arm64/boot/dts/rockchip/px30-mini-evb-ddr3-v11-avb.dts
View File

@@ -246,7 +246,7 @@
15 00 02 d2 32
15 00 02 d3 00
39 00 04 ff 98 81 00
05 00 01 11
05 78 01 11
05 01 01 29
];

32
arch/arm64/boot/dts/rockchip/px30.dtsi
View File

@@ -41,6 +41,7 @@
serial5 = &uart5;
spi0 = &spi0;
spi1 = &spi1;
spi2 = &sfc;
};
cpus {
@@ -674,7 +675,8 @@
clocks = <&pmucru SCLK_UART0_PMU>, <&pmucru PCLK_UART0_PMU>;
clock-names = "baudclk", "apb_pclk";
dmas = <&dmac 0>, <&dmac 1>;
dma-names = "tx", "rx";
/*You can add it to enable dma*/
/*dma-names = "tx", "rx";*/
reg-shift = <2>;
reg-io-width = <4>;
pinctrl-names = "default";
@@ -877,7 +879,8 @@
clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
clock-names = "baudclk", "apb_pclk";
dmas = <&dmac 2>, <&dmac 3>;
dma-names = "tx", "rx";
/*You can add it to enable dma*/
/*dma-names = "tx", "rx";*/
reg-shift = <2>;
reg-io-width = <4>;
pinctrl-names = "default";
@@ -892,7 +895,8 @@
clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
clock-names = "baudclk", "apb_pclk";
dmas = <&dmac 4>, <&dmac 5>;
dma-names = "tx", "rx";
/*You can add it to enable dma*/
/*dma-names = "tx", "rx";*/
reg-shift = <2>;
reg-io-width = <4>;
pinctrl-names = "default";
@@ -907,7 +911,8 @@
clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
clock-names = "baudclk", "apb_pclk";
dmas = <&dmac 6>, <&dmac 7>;
dma-names = "tx", "rx";
/*You can add it to enable dma*/
/*dma-names = "tx", "rx";*/
reg-shift = <2>;
reg-io-width = <4>;
pinctrl-names = "default";
@@ -922,7 +927,8 @@
clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
clock-names = "baudclk", "apb_pclk";
dmas = <&dmac 8>, <&dmac 9>;
dma-names = "tx", "rx";
/*You can add it to enable dma*/
/*dma-names = "tx", "rx";*/
reg-shift = <2>;
reg-io-width = <4>;
pinctrl-names = "default";
@@ -937,7 +943,8 @@
clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>;
clock-names = "baudclk", "apb_pclk";
dmas = <&dmac 10>, <&dmac 11>;
dma-names = "tx", "rx";
/*You can add it to enable dma*/
/*dma-names = "tx", "rx";*/
reg-shift = <2>;
reg-io-width = <4>;
pinctrl-names = "default";
@@ -1416,6 +1423,17 @@
status = "disabled";
};
sfc: spi@ff3a0000 {
compatible = "rockchip,sfc";
reg = <0x0 0xff3a0000 0x0 0x4000>;
interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
clock-names = "clk_sfc", "hclk_sfc";
assigned-clocks = <&cru SCLK_SFC>;
assigned-clock-rates = <100000000>;
status = "disabled";
};
nandc0: nandc@ff3b0000 {
compatible = "rockchip,rk-nandc";
reg = <0x0 0xff3b0000 0x0 0x4000>;
@@ -1580,6 +1598,7 @@
clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
clock-names = "aclk", "iface";
power-domains = <&power PX30_PD_VPU>;
rockchip,shootdown-entire;
#iommu-cells = <0>;
status = "disabled";
};
@@ -1630,6 +1649,7 @@
clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
clock-names = "aclk", "iface";
power-domains = <&power PX30_PD_VPU>;
rockchip,shootdown-entire;
#iommu-cells = <0>;
status = "disabled";
};

1
arch/arm64/boot/dts/rockchip/rk1808.dtsi
View File

@@ -379,6 +379,7 @@
snps,dis-del-phy-power-chg-quirk;
snps,tx-ipgap-linecheck-dis-quirk;
snps,xhci-trb-ent-quirk;
snps,parkmode-disable-ss-quirk;
status = "disabled";
};
};

2
arch/arm64/boot/dts/rockchip/rk3326-evb-lp3-v11-avb.dts
View File

@@ -242,7 +242,7 @@
15 00 02 d2 32
15 00 02 d3 00
39 00 04 ff 98 81 00
05 00 01 11
05 78 01 11
05 01 01 29
];

1
arch/arm64/boot/dts/rockchip/rk3328.dtsi
View File

@@ -1003,6 +1003,7 @@
snps,dis-u2-freeclk-exists-quirk;
snps,dis_u2_susphy_quirk;
snps,dis_u3_susphy_quirk;
snps,parkmode-disable-ss-quirk;
status = "disabled";
};

6
arch/arm64/boot/dts/rockchip/rk3399-opp.dtsi
View File

@@ -11,7 +11,7 @@
opp-shared;
rockchip,temp-hysteresis = <5000>;
rockchip,low-temp = <0>;
rockchip,low-temp = <10000>;
rockchip,low-temp-min-volt = <900000>;
nvmem-cells = <&cpul_leakage>, <&specification_serial_number>,
@@ -104,7 +104,7 @@
opp-shared;
rockchip,temp-hysteresis = <5000>;
rockchip,low-temp = <0>;
rockchip,low-temp = <10000>;
rockchip,low-temp-min-volt = <900000>;
nvmem-cells = <&cpub_leakage>, <&specification_serial_number>,
@@ -224,7 +224,7 @@
rockchip,thermal-zone = "soc-thermal";
rockchip,temp-hysteresis = <5000>;
rockchip,low-temp = <0>;
rockchip,low-temp = <10000>;
rockchip,low-temp-min-volt = <900000>;
nvmem-cells = <&gpu_leakage>;

2
arch/arm64/boot/dts/rockchip/rk3399.dtsi
View File

@@ -455,6 +455,7 @@
snps,dis_u2_susphy_quirk;
snps,dis-del-phy-power-chg-quirk;
snps,dis-tx-ipgap-linecheck-quirk;
snps,parkmode-disable-ss-quirk;
power-domains = <&power RK3399_PD_USB3>;
status = "disabled";
};
@@ -491,6 +492,7 @@
snps,dis_u2_susphy_quirk;
snps,dis-del-phy-power-chg-quirk;
snps,dis-tx-ipgap-linecheck-quirk;
snps,parkmode-disable-ss-quirk;
power-domains = <&power RK3399_PD_USB3>;
status = "disabled";
};

50
arch/arm64/boot/dts/rockchip/rk3399pro-evb-lp4-v11-linux.dts
View File

@@ -8,6 +8,7 @@
#include <dt-bindings/display/drm_mipi_dsi.h>
#include <dt-bindings/sensor-dev.h>
#include <dt-bindings/pwm/pwm.h>
#include "dt-bindings/usb/pd.h"
#include "rk3399pro.dtsi"
#include "rk3399-linux.dtsi"
#include "rk3399-opp.dtsi"
@@ -208,6 +209,16 @@
regulator-boot-on;
};
vbus_typec: vbus-typec-regulator {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio1 18 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&vcc5v0_typec0_en>;
regulator-name = "vbus_typec";
vin-supply = <&vcc5v0_sys>;
};
vcc5v0_sys: vccsys {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_sys";
@@ -243,7 +254,6 @@
&cdn_dp {
status = "okay";
extcon = <&fusb0>;
phys = <&tcphy0_dp>;
};
@@ -746,7 +756,6 @@
bq25700: bq25700@6b {
compatible = "ti,bq25703";
reg = <0x6b>;
extcon = <&fusb0>;
interrupt-parent = <&gpio1>;
interrupts = <RK_PA1 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
@@ -1072,8 +1081,16 @@
};
&tcphy0 {
extcon = <&fusb0>;
status = "okay";
orientation-switch;
port {
#address-cells = <1>;
#size-cells = <0>;
tcphy0_orientation_switch: endpoint@0 {
reg = <0>;
remote-endpoint = <&usbc0_orien_sw>;
};
};
};
&tcphy1 {
@@ -1144,7 +1161,15 @@
&usbdrd_dwc3_0 {
status = "okay";
extcon = <&fusb0>;
usb-role-switch;
port {
#address-cells = <1>;
#size-cells = <0>;
dwc3_0_role_switch: endpoint@0 {
reg = <0>;
remote-endpoint = <&usbc0_role_sw>;
};
};
};
&usbdrd_dwc3_1 {
@@ -1178,13 +1203,6 @@
};
};
fusb30x {
fusb0_int: fusb0-int {
rockchip,pins =
<1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
headphone {
hp_det: hp-det {
rockchip,pins =
@@ -1275,6 +1293,16 @@
};
};
usb-typec {
usbc0_int: usbc0-int {
rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>;
};
vcc5v0_typec0_en: vcc5v0-typec0-en {
rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
wireless-bluetooth {
bt_irq_gpio: bt-irq-gpio {
rockchip,pins =

98
arch/arm64/boot/dts/rockchip/rk3399pro-evb-v10-linux.dts
View File

@@ -8,6 +8,7 @@
#include <dt-bindings/display/drm_mipi_dsi.h>
#include <dt-bindings/sensor-dev.h>
#include <dt-bindings/pwm/pwm.h>
#include "dt-bindings/usb/pd.h"
#include "rk3399pro.dtsi"
#include "rk3399-linux.dtsi"
#include "rk3399-opp.dtsi"
@@ -196,6 +197,16 @@
reset-gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_LOW>;
};
vbus_typec: vbus-typec-regulator {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio1 18 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&vcc5v0_typec0_en>;
regulator-name = "vbus_typec";
vin-supply = <&vcc5v0_sys>;
};
vcc_phy: vcc-phy-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc_phy";
@@ -238,7 +249,6 @@
&cdn_dp {
status = "okay";
extcon = <&fusb0>;
phys = <&tcphy0_dp>;
};
@@ -647,7 +657,6 @@
bq25700: bq25700@6b {
compatible = "ti,bq25703";
reg = <0x6b>;
extcon = <&fusb0>;
interrupt-parent = <&gpio1>;
interrupts = <RK_PA1 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
@@ -774,13 +783,52 @@
i2c-scl-falling-time-ns = <11>;
clock-frequency = <100000>;
fusb0: fusb30x@22 {
compatible = "fairchild,fusb302";
usbc0: fusb302@22 {
compatible = "fcs,fusb302";
reg = <0x22>;
interrupt-parent = <&gpio1>;
interrupts = <RK_PA2 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&fusb0_int>;
int-n-gpios = <&gpio1 RK_PA2 GPIO_ACTIVE_HIGH>;
pinctrl-0 = <&usbc0_int>;
vbus-supply = <&vbus_typec>;
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
usbc0_role_sw: endpoint@0 {
remote-endpoint = <&dwc3_0_role_switch>;
};
};
};
usb_con: connector {
compatible = "usb-c-connector";
label = "USB-C";
data-role = "dual";
power-role = "dual";
try-power-role = "sink";
op-sink-microwatt = <1000000>;
sink-pdos =
<PDO_FIXED(5000, 2500, PDO_FIXED_USB_COMM)>;
source-pdos =
<PDO_FIXED(5000, 1500, PDO_FIXED_USB_COMM)>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
usbc0_orien_sw: endpoint {
remote-endpoint = <&tcphy0_orientation_switch>;
};
};
};
};
};
};
@@ -982,8 +1030,16 @@
};
&tcphy0 {
extcon = <&fusb0>;
status = "okay";
orientation-switch;
port {
#address-cells = <1>;
#size-cells = <0>;
tcphy0_orientation_switch: endpoint@0 {
reg = <0>;
remote-endpoint = <&usbc0_orien_sw>;
};
};
};
&tcphy1 {
@@ -998,7 +1054,6 @@
&u2phy0 {
status = "okay";
extcon = <&fusb0>;
u2phy0_otg: otg-port {
status = "okay";
@@ -1054,7 +1109,15 @@
&usbdrd_dwc3_0 {
status = "okay";
extcon = <&fusb0>;
usb-role-switch;
port {
#address-cells = <1>;
#size-cells = <0>;
dwc3_0_role_switch: endpoint@0 {
reg = <0>;
remote-endpoint = <&usbc0_role_sw>;
};
};
};
&usbdrd_dwc3_1 {
@@ -1088,13 +1151,6 @@
};
};
fusb30x {
fusb0_int: fusb0-int {
rockchip,pins =
<1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
headphone {
hp_det: hp-det {
rockchip,pins =
@@ -1146,6 +1202,16 @@
};
};
usb-typec {
usbc0_int: usbc0-int {
rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>;
};
vcc5v0_typec0_en: vcc5v0-typec0-en {
rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
sdio-pwrseq {
wifi_enable_h: wifi-enable-h {
rockchip,pins =

98
arch/arm64/boot/dts/rockchip/rk3399pro-evb-v10.dts
View File

@@ -197,6 +197,16 @@
reset-gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_LOW>;
};
vbus_typec: vbus-typec-regulator {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio1 18 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&vcc5v0_typec0_en>;
regulator-name = "vbus_typec";
vin-supply = <&vcc5v0_sys>;
};
vcc_phy: vcc-phy-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc_phy";
@@ -239,7 +249,6 @@
&cdn_dp {
status = "okay";
extcon = <&fusb0>;
phys = <&tcphy0_dp>;
};
@@ -676,7 +685,6 @@
bq25700: bq25700@6b {
compatible = "ti,bq25703";
reg = <0x6b>;
extcon = <&fusb0>;
interrupt-parent = <&gpio1>;
interrupts = <RK_PA1 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
@@ -750,15 +758,53 @@
i2c-scl-falling-time-ns = <11>;
clock-frequency = <100000>;
fusb0: fusb30x@22 {
compatible = "fairchild,fusb302";
usbc0: fusb302@22 {
compatible = "fcs,fusb302";
reg = <0x22>;
interrupt-parent = <&gpio1>;
interrupts = <RK_PA2 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&fusb0_int>;
int-n-gpios = <&gpio1 RK_PA2 GPIO_ACTIVE_HIGH>;
pinctrl-0 = <&usbc0_int>;
vbus-supply = <&vbus_typec>;
status = "okay";
};
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
usbc0_role_sw: endpoint@0 {
remote-endpoint = <&dwc3_0_role_switch>;
};
};
};
usb_con: connector {
compatible = "usb-c-connector";
label = "USB-C";
data-role = "dual";
power-role = "dual";
try-power-role = "sink";
op-sink-microwatt = <1000000>;
sink-pdos =
<PDO_FIXED(5000, 2500, PDO_FIXED_USB_COMM)>;
source-pdos =
<PDO_FIXED(5000, 1500, PDO_FIXED_USB_COMM)>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
usbc0_orien_sw: endpoint {
remote-endpoint = <&tcphy0_orientation_switch>;
};
};
};
};
};
};
&i2s1 {
@@ -856,8 +902,16 @@
};
&tcphy0 {
extcon = <&fusb0>;
status = "okay";
orientation-switch;
port {
#address-cells = <1>;
#size-cells = <0>;
tcphy0_orientation_switch: endpoint@0 {
reg = <0>;
remote-endpoint = <&usbc0_orien_sw>;
};
};
};
&tcphy1 {
@@ -872,7 +926,6 @@
&u2phy0 {
status = "okay";
extcon = <&fusb0>;
u2phy0_otg: otg-port {
status = "okay";
@@ -928,7 +981,15 @@
&usbdrd_dwc3_0 {
status = "okay";
extcon = <&fusb0>;
usb-role-switch;
port {
#address-cells = <1>;
#size-cells = <0>;
dwc3_0_role_switch: endpoint@0 {
reg = <0>;
remote-endpoint = <&usbc0_role_sw>;
};
};
};
&usbdrd_dwc3_1 {
@@ -956,13 +1017,6 @@
};
};
fusb30x {
fusb0_int: fusb0-int {
rockchip,pins =
<1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
headphone {
hp_det: hp-det {
rockchip,pins =
@@ -1048,6 +1102,16 @@
};
};
usb-typec {
usbc0_int: usbc0-int {
rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>;
};
vcc5v0_typec0_en: vcc5v0-typec0-en {
rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
wireless-bluetooth {
uart0_gpios: uart0-gpios {
rockchip,pins =

110
arch/arm64/boot/dts/rockchip/rk3399pro-evb-v11-linux.dts
View File

@@ -8,6 +8,7 @@
#include <dt-bindings/display/drm_mipi_dsi.h>
#include <dt-bindings/sensor-dev.h>
#include <dt-bindings/pwm/pwm.h>
#include "dt-bindings/usb/pd.h"
#include "rk3399pro.dtsi"
#include "rk3399-linux.dtsi"
#include "rk3399-opp.dtsi"
@@ -201,6 +202,26 @@
status = "disabled";
};
vbus_typec: vbus-typec-regulator {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio1 18 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&vcc5v0_typec0_en>;
regulator-name = "vbus_typec";
vin-supply = <&vcc5v0_sys>;
};
vbus_typec: vbus-typec-regulator {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio1 18 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&vcc5v0_typec0_en>;
regulator-name = "vbus_typec";
vin-supply = <&vcc5v0_sys>;
};
vcc_phy: vcc-phy-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc_phy";
@@ -243,7 +264,6 @@
&cdn_dp {
status = "okay";
extcon = <&fusb0>;
phys = <&tcphy0_dp>;
};
@@ -657,7 +677,6 @@
bq25700: bq25700@6b {
compatible = "ti,bq25703";
reg = <0x6b>;
extcon = <&fusb0>;
interrupt-parent = <&gpio1>;
interrupts = <RK_PA1 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
@@ -786,16 +805,53 @@
i2c-scl-falling-time-ns = <11>;
clock-frequency = <100000>;
fusb0: fusb30x@22 {
compatible = "fairchild,fusb302";
usbc0: fusb302@22 {
compatible = "fcs,fusb302";
reg = <0x22>;
interrupt-parent = <&gpio1>;
interrupts = <RK_PA2 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&fusb0_int>;
int-n-gpios = <&gpio1 RK_PA2 GPIO_ACTIVE_HIGH>;
vbus-5v-gpios = <&gpio0 RK_PA1 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&usbc0_int>;
vbus-supply = <&vbus_typec>;
status = "okay";
};
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
usbc0_role_sw: endpoint@0 {
remote-endpoint = <&dwc3_0_role_switch>;
};
};
};
usb_con: connector {
compatible = "usb-c-connector";
label = "USB-C";
data-role = "dual";
power-role = "dual";
try-power-role = "sink";
op-sink-microwatt = <1000000>;
sink-pdos =
<PDO_FIXED(5000, 2500, PDO_FIXED_USB_COMM)>;
source-pdos =
<PDO_FIXED(5000, 1500, PDO_FIXED_USB_COMM)>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
usbc0_orien_sw: endpoint {
remote-endpoint = <&tcphy0_orientation_switch>;
};
};
};
};
};
};
&i2s1 {
@@ -995,8 +1051,16 @@
};
&tcphy0 {
extcon = <&fusb0>;
status = "okay";
orientation-switch;
port {
#address-cells = <1>;
#size-cells = <0>;
tcphy0_orientation_switch: endpoint@0 {
reg = <0>;
remote-endpoint = <&usbc0_orien_sw>;
};
};
};
&tcphy1 {
@@ -1011,7 +1075,6 @@
&u2phy0 {
status = "okay";
extcon = <&fusb0>;
u2phy0_otg: otg-port {
status = "okay";
@@ -1067,7 +1130,15 @@
&usbdrd_dwc3_0 {
status = "okay";
extcon = <&fusb0>;
usb-role-switch;
port {
#address-cells = <1>;
#size-cells = <0>;
dwc3_0_role_switch: endpoint@0 {
reg = <0>;
remote-endpoint = <&usbc0_role_sw>;
};
};
};
&usbdrd_dwc3_1 {
@@ -1108,13 +1179,6 @@
};
};
fusb30x {
fusb0_int: fusb0-int {
rockchip,pins =
<1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
headphone {
hp_det: hp-det {
rockchip,pins =
@@ -1205,6 +1269,16 @@
};
};
usb-typec {
usbc0_int: usbc0-int {
rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>;
};
vcc5v0_typec0_en: vcc5v0-typec0-en {
rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
wireless-bluetooth {
bt_irq_gpio: bt-irq-gpio {
rockchip,pins =

100
arch/arm64/boot/dts/rockchip/rk3399pro-evb-v11.dts
View File

@@ -8,6 +8,7 @@
#include <dt-bindings/display/drm_mipi_dsi.h>
#include <dt-bindings/sensor-dev.h>
#include <dt-bindings/pwm/pwm.h>
#include "dt-bindings/usb/pd.h"
#include "rk3399pro.dtsi"
#include "rk3399-android.dtsi"
#include "rk3399-opp.dtsi"
@@ -198,6 +199,16 @@
reset-gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_LOW>;
};
vbus_typec: vbus-typec-regulator {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio1 18 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&vcc5v0_typec0_en>;
regulator-name = "vbus_typec";
vin-supply = <&vcc5v0_sys>;
};
vcc_phy: vcc-phy-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc_phy";
@@ -240,7 +251,6 @@
&cdn_dp {
status = "okay";
extcon = <&fusb0>;
phys = <&tcphy0_dp>;
};
@@ -661,7 +671,6 @@
bq25700: bq25700@6b {
compatible = "ti,bq25703";
reg = <0x6b>;
extcon = <&fusb0>;
interrupt-parent = <&gpio1>;
interrupts = <RK_PA1 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
@@ -735,16 +744,53 @@
i2c-scl-falling-time-ns = <11>;
clock-frequency = <100000>;
fusb0: fusb30x@22 {
compatible = "fairchild,fusb302";
usbc0: fusb302@22 {
compatible = "fcs,fusb302";
reg = <0x22>;
interrupt-parent = <&gpio1>;
interrupts = <RK_PA2 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&fusb0_int>;
int-n-gpios = <&gpio1 RK_PA2 GPIO_ACTIVE_HIGH>;
vbus-5v-gpios = <&gpio0 RK_PA1 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&usbc0_int>;
vbus-supply = <&vbus_typec>;
status = "okay";
};
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
usbc0_role_sw: endpoint@0 {
remote-endpoint = <&dwc3_0_role_switch>;
};
};
};
usb_con: connector {
compatible = "usb-c-connector";
label = "USB-C";
data-role = "dual";
power-role = "dual";
try-power-role = "sink";
op-sink-microwatt = <1000000>;
sink-pdos =
<PDO_FIXED(5000, 2500, PDO_FIXED_USB_COMM)>;
source-pdos =
<PDO_FIXED(5000, 1500, PDO_FIXED_USB_COMM)>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
usbc0_orien_sw: endpoint {
remote-endpoint = <&tcphy0_orientation_switch>;
};
};
};
};
};
};
&i2s1 {
@@ -838,8 +884,16 @@
};
&tcphy0 {
extcon = <&fusb0>;
status = "okay";
orientation-switch;
port {
#address-cells = <1>;
#size-cells = <0>;
tcphy0_orientation_switch: endpoint@0 {
reg = <0>;
remote-endpoint = <&usbc0_orien_sw>;
};
};
};
&tcphy1 {
@@ -854,7 +908,6 @@
&u2phy0 {
status = "okay";
extcon = <&fusb0>;
u2phy0_otg: otg-port {
status = "okay";
@@ -911,7 +964,15 @@
&usbdrd_dwc3_0 {
status = "okay";
extcon = <&fusb0>;
usb-role-switch;
port {
#address-cells = <1>;
#size-cells = <0>;
dwc3_0_role_switch: endpoint@0 {
reg = <0>;
remote-endpoint = <&usbc0_role_sw>;
};
};
};
&usbdrd_dwc3_1 {
@@ -939,13 +1000,6 @@
};
};
fusb30x {
fusb0_int: fusb0-int {
rockchip,pins =
<1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
headphone {
hp_det: hp-det {
rockchip,pins =
@@ -1031,6 +1085,16 @@
};
};
usb-typec {
usbc0_int: usbc0-int {
rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>;
};
vcc5v0_typec0_en: vcc5v0-typec0-en {
rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
wireless-bluetooth {
uart0_gpios: uart0-gpios {
rockchip,pins =

11
arch/arm64/boot/dts/rockchip/rk3568.dtsi
View File

@@ -584,6 +584,8 @@
snps,dis-tx-ipgap-linecheck-quirk;
snps,dis_rxdet_inp3_quirk;
snps,xhci-trb-ent-quirk;
snps,parkmode-disable-ss-quirk;
quirk-skip-phy-init;
status = "disabled";
};
};
@@ -617,6 +619,7 @@
snps,dis-tx-ipgap-linecheck-quirk;
snps,dis_rxdet_inp3_quirk;
snps,xhci-trb-ent-quirk;
snps,parkmode-disable-ss-quirk;
status = "disabled";
};
};
@@ -1775,12 +1778,12 @@
<&cru SCLK_GMAC1_RX_TX>, <&cru CLK_MAC1_REFOUT>,
<&cru ACLK_GMAC1>, <&cru PCLK_GMAC1>,
<&cru SCLK_GMAC1_RX_TX>, <&cru CLK_GMAC1_PTP_REF>,
<&cru PCLK_XPCS>;
<&cru PCLK_XPCS>, <&cru CLK_XPCS_EEE>;
clock-names = "stmmaceth", "mac_clk_rx",
"mac_clk_tx", "clk_mac_refout",
"aclk_mac", "pclk_mac",
"clk_mac_speed", "ptp_ref",
"pclk_xpcs";
"pclk_xpcs", "clk_xpcs_eee";
resets = <&cru SRST_A_GMAC1>;
reset-names = "stmmaceth";
@@ -2520,12 +2523,12 @@
<&cru SCLK_GMAC0_RX_TX>, <&cru CLK_MAC0_REFOUT>,
<&cru ACLK_GMAC0>, <&cru PCLK_GMAC0>,
<&cru SCLK_GMAC0_RX_TX>, <&cru CLK_GMAC0_PTP_REF>,
<&cru PCLK_XPCS>;
<&cru PCLK_XPCS>, <&cru CLK_XPCS_EEE>;
clock-names = "stmmaceth", "mac_clk_rx",
"mac_clk_tx", "clk_mac_refout",
"aclk_mac", "pclk_mac",
"clk_mac_speed", "ptp_ref",
"pclk_xpcs";
"pclk_xpcs", "clk_xpcs_eee";
resets = <&cru SRST_A_GMAC0>;
reset-names = "stmmaceth";

4
arch/arm64/boot/dts/rockchip/rk3588-evb.dtsi
View File

@@ -218,6 +218,10 @@
status = "okay";
};
&avsd {
status = "okay";
};
&cpu_l0 {
cpu-supply = <&vdd_cpu_lit_s0>;
mem-supply = <&vdd_cpu_lit_mem_s0>;

277
arch/arm64/boot/dts/rockchip/rk3588-evb1-lp4-v10-lt6911uxe.dts Normal file
View File

@@ -0,0 +1,277 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2022 Rockchip Electronics Co., Ltd.
*
*/
/dts-v1/;
#include "rk3588-evb1-lp4.dtsi"
#include "rk3588-android.dtsi"
/ {
model = "Rockchip RK3588 EVB1 LP4 V10 Board + Rockchip RK3588 EVB V10 Extboard";
compatible = "rockchip,rk3588-evb1-lp4-v10-lt6911uxe", "rockchip,rk3588";
vcc_mipicsi0: vcc-mipicsi0-regulator {
compatible = "regulator-fixed";
gpio = <&gpio1 RK_PB1 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&mipicsi0_pwr>;
regulator-name = "vcc_mipicsi0";
enable-active-high;
regulator-boot-on;
regulator-always-on;
};
vcc_mipidcphy0: vcc-mipidcphy0-regulator {
compatible = "regulator-fixed";
gpio = <&gpio2 RK_PC4 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&mipidcphy0_pwr>;
regulator-name = "vcc_mipidcphy0";
enable-active-high;
regulator-boot-on;
regulator-always-on;
};
ext_cam_clk: external-camera-clock {
compatible = "fixed-clock";
clock-frequency = <24000000>;
clock-output-names = "CLK_CAMERA_24MHZ";
#clock-cells = <0>;
};
};
&csi2_dphy0 {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
hdmi_mipi2_in: endpoint@1 {
reg = <1>;
remote-endpoint = <&lt6911uxe_out1>;
data-lanes = <1 2 3 4>;
};
};
port@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
csidphy0_out: endpoint@0 {
reg = <0>;
remote-endpoint = <&mipi2_csi2_input>;
};
};
};
};
&csi2_dphy0_hw {
status = "okay";
};
&csi2_dcphy0 {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
hdmi_mipi0_in: endpoint@1 {
reg = <1>;
remote-endpoint = <&lt6911uxe_out0>;
data-lanes = <1 2 3 4>;
};
};
port@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
csidcphy0_out: endpoint@0 {
reg = <0>;
remote-endpoint = <&mipi0_csi2_input>;
};
};
};
};
&i2c3 {
status = "okay";
lt6911uxe_1: lt6911uxe_1@2b {
compatible = "lontium,lt6911uxe";
status = "okay";
reg = <0x2b>;
clocks = <&ext_cam_clk>;
clock-names = "xvclk";
power-domains = <&power RK3588_PD_VI>;
pinctrl-names = "default";
pinctrl-0 = <&lt6911uxe_pin_1>;
interrupt-parent = <&gpio1>;
interrupts = <RK_PB3 IRQ_TYPE_LEVEL_LOW>;
// reset-gpios = <&gpio1 RK_PB1 GPIO_ACTIVE_LOW>;
// power-gpios = <&gpio1 RK_PA6 GPIO_ACTIVE_HIGH>;
plugin-det-gpios = <&gpio1 RK_PB4 GPIO_ACTIVE_HIGH>;
rockchip,camera-module-index = <0>;
rockchip,camera-module-facing = "back";
rockchip,camera-module-name = "HDMI-MIPI2";
rockchip,camera-module-lens-name = "LT6911UXE-2";
port {
lt6911uxe_out1: endpoint {
remote-endpoint = <&hdmi_mipi2_in>;
data-lanes = <1 2 3 4>;
};
};
};
};
&i2c5 {
status = "okay";
lt6911uxe: lt6911uxe@2b {
compatible = "lontium,lt6911uxe";
status = "okay";
reg = <0x2b>;
clocks = <&ext_cam_clk>;
clock-names = "xvclk";
power-domains = <&power RK3588_PD_VI>;
pinctrl-names = "default";
pinctrl-0 = <&lt6911uxe_pin>;
interrupt-parent = <&gpio1>;
interrupts = <RK_PA0 IRQ_TYPE_LEVEL_LOW>;
// reset-gpios = <&gpio1 RK_PB1 GPIO_ACTIVE_LOW>;
// power-gpios = <&gpio1 RK_PA6 GPIO_ACTIVE_HIGH>;
// plugin-det-gpios = <&gpio1 RK_PB4 GPIO_ACTIVE_LOW>;
plugin-det-gpios = <&gpio1 RK_PA1 GPIO_ACTIVE_HIGH>;
rockchip,camera-module-index = <1>;
rockchip,camera-module-facing = "front";
rockchip,camera-module-name = "HDMI-MIPI0";
rockchip,camera-module-lens-name = "LT6911UXC-0";
port {
lt6911uxe_out0: endpoint {
remote-endpoint = <&hdmi_mipi0_in>;
data-lanes = <1 2 3 4>;
};
};
};
};
&mipi_dcphy0 {
status = "okay";
};
&mipi0_csi2 {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
mipi0_csi2_input: endpoint@1 {
reg = <1>;
remote-endpoint = <&csidcphy0_out>;
};
};
port@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
mipi0_csi2_output: endpoint@0 {
reg = <0>;
remote-endpoint = <&cif_mipi_in0>;
};
};
};
};
&mipi2_csi2 {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
mipi2_csi2_input: endpoint@1 {
reg = <1>;
remote-endpoint = <&csidphy0_out>;
};
};
port@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
mipi2_csi2_output: endpoint@0 {
reg = <0>;
remote-endpoint = <&cif_mipi_in2>;
};
};
};
};
&rkcif {
status = "okay";
};
&rkcif_mipi_lvds {
status = "okay";
port {
cif_mipi_in0: endpoint {
remote-endpoint = <&mipi0_csi2_output>;
};
};
};
&rkcif_mipi_lvds2 {
status = "okay";
port {
cif_mipi_in2: endpoint {
remote-endpoint = <&mipi2_csi2_output>;
};
};
};
&rkcif_mmu {
status = "okay";
};
&pinctrl {
hdmiin {
lt6911uxe_pin: lt6911uxe-pin {
rockchip,pins = <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>,
<1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>;
};
lt6911uxe_pin_1: lt6911uxe-pin-1 {
rockchip,pins = <1 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>,
<1 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
};

176
arch/arm64/boot/dts/rockchip/rk3588-h0-imx415.dtsi Normal file
View File

@@ -0,0 +1,176 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2022 Rockchip Electronics Co., Ltd.
*
*/
/ {
cam_ircut0: cam_ircut {
status = "okay";
compatible = "rockchip,ircut";
ircut-open-gpios = <&gpio4 RK_PA0 GPIO_ACTIVE_HIGH>;
ircut-close-gpios = <&gpio4 RK_PA1 GPIO_ACTIVE_HIGH>;
rockchip,camera-module-index = <0>;
rockchip,camera-module-facing = "back";
};
vcc_mipidphy0: vcc-mipidcphy0-regulator {
compatible = "regulator-fixed";
gpio = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&mipidphy0_pwr>;
regulator-name = "vcc_mipidphy0";
enable-active-high;
};
};
&csi2_dphy0 {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
mipidphy0_in_ucam0: endpoint@1 {
reg = <1>;
remote-endpoint = <&imx415_out0>;
data-lanes = <1 2 3 4>;
};
};
port@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
csidphy0_out: endpoint@0 {
reg = <0>;
remote-endpoint = <&mipi2_csi2_input>;
};
};
};
};
&csi2_dphy0_hw {
status = "okay";
};
&i2c3 {
status = "okay";
imx415: imx415@1a {
compatible = "sony,imx415";
reg = <0x1a>;
clocks = <&cru CLK_MIPI_CAMARAOUT_M3>;
clock-names = "xvclk";
pinctrl-names = "default";
pinctrl-0 = <&mipim0_camera3_clk>;
power-domains = <&power RK3588_PD_VI>;
pwdn-gpios = <&gpio1 RK_PA7 GPIO_ACTIVE_HIGH>;
avdd-supply = <&vcc_mipidphy0>;
rockchip,camera-module-index = <0>;
rockchip,camera-module-facing = "back";
rockchip,camera-module-name = "CMK-OT2022-PX1";
rockchip,camera-module-lens-name = "IR0147-50IRC-8M-F20";
lens-focus = <&cam_ircut0>;
port {
imx415_out0: endpoint {
remote-endpoint = <&mipidphy0_in_ucam0>;
data-lanes = <1 2 3 4>;
};
};
};
};
&mipi2_csi2 {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
mipi2_csi2_input: endpoint@1 {
reg = <1>;
remote-endpoint = <&csidphy0_out>;
};
};
port@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
mipi2_csi2_output: endpoint@0 {
reg = <0>;
remote-endpoint = <&cif_mipi2_in0>;
};
};
};
};
&pinctrl {
cam {
mipidphy0_pwr: mipidphy0-pwr {
rockchip,pins =
/* camera power en */
<1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
};
&rkcif {
status = "okay";
};
&rkcif_mipi_lvds2 {
status = "okay";
port {
cif_mipi2_in0: endpoint {
remote-endpoint = <&mipi2_csi2_output>;
};
};
};
&rkcif_mipi_lvds2_sditf {
status = "okay";
port {
mipi_lvds2_sditf: endpoint {
remote-endpoint = <&isp0_vir0>;
};
};
};
&rkcif_mmu {
status = "okay";
};
&rkisp0 {
status = "okay";
};
&isp0_mmu {
status = "okay";
};
&rkisp0_vir0 {
status = "okay";
port {
#address-cells = <1>;
#size-cells = <0>;
isp0_vir0: endpoint@0 {
reg = <0>;
remote-endpoint = <&mipi_lvds2_sditf>;
};
};
};

16
arch/arm64/boot/dts/rockchip/rk3588-h0-v10-linux.dts Normal file
View File

@@ -0,0 +1,16 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2022 Rockchip Electronics Co., Ltd.
*
*/
/dts-v1/;
#include "rk3588-h0.dtsi"
#include "rk3588-h0-imx415.dtsi"
#include "rk3588-linux.dtsi"
/ {
model = "Rockchip RK3588 H0 V10 Board";
compatible = "rockchip,rk3588-h0-v10", "rockchip,rk3588";
};

16
arch/arm64/boot/dts/rockchip/rk3588-h0-v10.dts Normal file
View File

@@ -0,0 +1,16 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2022 Rockchip Electronics Co., Ltd.
*
*/
/dts-v1/;
#include "rk3588-h0.dtsi"
#include "rk3588-h0-imx415.dtsi"
#include "rk3588-android.dtsi"
/ {
model = "Rockchip RK3588 H0 V10 Board";
compatible = "rockchip,rk3588-h0-v10", "rockchip,rk3588";
};

935
arch/arm64/boot/dts/rockchip/rk3588-h0.dtsi Normal file
View File

@@ -0,0 +1,935 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2022 Rockchip Electronics Co., Ltd.
*
*/
#include "dt-bindings/usb/pd.h"
#include "rk3588.dtsi"
#include "rk3588-evb.dtsi"
#include "rk3588-rk806-single.dtsi"
/ {
/* If hdmirx node is disabled, delete the reserved-memory node here. */
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
/* Reserve 128MB memory for hdmirx-controller@fdee0000 */
cma {
compatible = "shared-dma-pool";
reusable;
reg = <0x0 (256 * 0x100000) 0x0 (128 * 0x100000)>;
linux,cma-default;
};
};
es8388_sound: es8388-sound {
status = "okay";
compatible = "rockchip,multicodecs-card";
rockchip,card-name = "rockchip-es8388";
hp-det-gpio = <&gpio1 RK_PC4 GPIO_ACTIVE_LOW>;
io-channels = <&saradc 3>;
io-channel-names = "adc-detect";
keyup-threshold-microvolt = <1800000>;
poll-interval = <100>;
spk-con-gpio = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>;
hp-con-gpio = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>;
rockchip,format = "i2s";
rockchip,mclk-fs = <256>;
rockchip,cpu = <&i2s0_8ch>;
rockchip,codec = <&es8388>;
rockchip,audio-routing =
"Headphone", "LOUT1",
"Headphone", "ROUT1",
"Speaker", "LOUT2",
"Speaker", "ROUT2",
"Headphone", "Headphone Power",
"Headphone", "Headphone Power",
"Speaker", "Speaker Power",
"Speaker", "Speaker Power",
"LINPUT1", "Main Mic",
"LINPUT2", "Main Mic",
"RINPUT1", "Headset Mic",
"RINPUT2", "Headset Mic";
pinctrl-names = "default";
pinctrl-0 = <&hp_det>;
play-pause-key {
label = "playpause";
linux,code = <KEY_PLAYPAUSE>;
press-threshold-microvolt = <2000>;
};
};
fan: pwm-fan {
compatible = "pwm-fan";
#cooling-cells = <2>;
pwms = <&pwm3 0 50000 0>;
cooling-levels = <0 50 100 150 200 255>;
rockchip,temp-trips = <
50000 1
55000 2
60000 3
65000 4
70000 5
>;
};
hdmiin-sound {
compatible = "rockchip,hdmi";
rockchip,mclk-fs = <128>;
rockchip,format = "i2s";
rockchip,bitclock-master = <&hdmirx_ctrler>;
rockchip,frame-master = <&hdmirx_ctrler>;
rockchip,card-name = "rockchip,hdmiin";
rockchip,cpu = <&i2s7_8ch>;
rockchip,codec = <&hdmirx_ctrler 0>;
rockchip,jack-det;
};
pcie20_avdd0v85: pcie20-avdd0v85 {
compatible = "regulator-fixed";
regulator-name = "pcie20_avdd0v85";
regulator-boot-on;
regulator-always-on;
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <850000>;
vin-supply = <&vdd_0v85_s0>;
};
pcie20_avdd1v8: pcie20-avdd1v8 {
compatible = "regulator-fixed";
regulator-name = "pcie20_avdd1v8";
regulator-boot-on;
regulator-always-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
vin-supply = <&avcc_1v8_s0>;
};
pcie30_avdd0v75: pcie30-avdd0v75 {
compatible = "regulator-fixed";
regulator-name = "pcie30_avdd0v75";
regulator-boot-on;
regulator-always-on;
regulator-min-microvolt = <750000>;
regulator-max-microvolt = <750000>;
vin-supply = <&avdd_0v75_s0>;
};
pcie30_avdd1v8: pcie30-avdd1v8 {
compatible = "regulator-fixed";
regulator-name = "pcie30_avdd1v8";
regulator-boot-on;
regulator-always-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
vin-supply = <&avcc_1v8_s0>;
};
sdio_pwrseq: sdio-pwrseq {
compatible = "mmc-pwrseq-simple";
clocks = <&hym8563>;
clock-names = "ext_clock";
pinctrl-names = "default";
pinctrl-0 = <&wifi_enable_h>;
/*
* On the module itself this is one of these (depending
* on the actual card populated):
* - SDIO_RESET_L_WL_REG_ON
* - PDN (power down when low)
*/
post-power-on-delay-ms = <200>;
reset-gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_LOW>;
};
rk_headset: rk-headset {
status = "disabled";
compatible = "rockchip_headset";
headset_gpio = <&gpio1 RK_PD5 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&hp_det>;
io-channels = <&saradc 3>;
};
vcc_1v1_nldo_s3: vcc-1v1-nldo-s3 {
compatible = "regulator-fixed";
regulator-name = "vcc_1v1_nldo_s3";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1100000>;
vin-supply = <&vcc5v0_sys>;
};
vbus5v0_typec: vbus5v0-typec {
compatible = "regulator-fixed";
regulator-name = "vbus5v0_typec";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
enable-active-high;
gpio = <&gpio3 RK_PA6 GPIO_ACTIVE_HIGH>;
vin-supply = <&vcc5v0_usb>;
pinctrl-names = "default";
pinctrl-0 = <&typec5v_pwren>;
};
vcc3v3_lcd_n: vcc3v3-lcd0-n {
compatible = "regulator-fixed";
regulator-name = "vcc3v3_lcd0_n";
regulator-boot-on;
enable-active-high;
gpio = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>;
vin-supply = <&vcc_1v8_s0>;
};
vcc3v3_pcie30: vcc3v3-pcie30 {
compatible = "regulator-fixed";
regulator-name = "vcc3v3_pcie30";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
enable-active-high;
gpios = <&gpio2 RK_PC5 GPIO_ACTIVE_HIGH>;
startup-delay-us = <5000>;
vin-supply = <&vcc12v_dcin>;
};
vcc5v0_host: vcc5v0-host {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_host";
regulator-boot-on;
regulator-always-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
enable-active-high;
gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>;
vin-supply = <&vcc5v0_usb>;
pinctrl-names = "default";
pinctrl-0 = <&vcc5v0_host_en>;
};
vcc_mipicsi0: vcc-mipicsi0-regulator {
compatible = "regulator-fixed";
gpio = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&mipicsi0_pwr>;
regulator-name = "vcc_mipicsi0";
enable-active-high;
};
vcc_mipicsi1: vcc-mipicsi1-regulator {
compatible = "regulator-fixed";
gpio = <&gpio1 RK_PD3 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&mipicsi1_pwr>;
regulator-name = "vcc_mipicsi1";
enable-active-high;
};
vcc_mipidcphy0: vcc-mipidcphy0-regulator {
compatible = "regulator-fixed";
gpio = <&gpio2 RK_PC4 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&mipidcphy0_pwr>;
regulator-name = "vcc_mipidcphy0";
enable-active-high;
};
vcc_3v3_sd_s0: vcc-3v3-sd-s0-regulator {
compatible = "regulator-fixed";
gpio = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&sd_s0_pwr>;
regulator-name = "vcc_3v3_sd_s0";
enable-active-high;
};
wireless_bluetooth: wireless-bluetooth {
compatible = "bluetooth-platdata";
clocks = <&hym8563>;
clock-names = "ext_clock";
uart_rts_gpios = <&gpio4 RK_PC4 GPIO_ACTIVE_LOW>;
pinctrl-names = "default", "rts_gpio";
pinctrl-0 = <&uart9m0_rtsn>, <&bt_reset_gpio>, <&bt_wake_gpio>, <&bt_irq_gpio>;
pinctrl-1 = <&uart9_gpios>;
BT,reset_gpio = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>;
BT,wake_gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>;
BT,wake_host_irq = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>;
status = "okay";
};
wireless_wlan: wireless-wlan {
compatible = "wlan-platdata";
wifi_chip_type = "ap6398s";
pinctrl-names = "default";
pinctrl-0 = <&wifi_host_wake_irq>;
WIFI,host_wake_irq = <&gpio0 RK_PB2 GPIO_ACTIVE_HIGH>;
WIFI,poweren_gpio = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>;
status = "okay";
};
};
&backlight {
pwms = <&pwm1 0 25000 0>;
status = "okay";
};
&combphy0_ps {
status = "okay";
};
&combphy1_ps {
status = "okay";
};
&combphy2_psu {
status = "okay";
};
&dp0 {
status = "okay";
};
&dp0_in_vp2 {
status = "okay";
};
&dp0_sound{
status = "okay";
};
&dp1 {
pinctrl-names = "default";
pinctrl-0 = <&dp1m0_pins>;
status = "okay";
};
&dp1_in_vp2 {
status = "okay";
};
/*
* mipi_dcphy0 needs to be enabled
* when dsi0 is enabled
*/
&dsi0 {
status = "okay";
};
&dsi0_in_vp2 {
status = "disabled";
};
&dsi0_in_vp3 {
status = "okay";
};
&dsi0_panel {
power-supply = <&vcc3v3_lcd_n>;
reset-gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&lcd_rst_gpio>;
};
/*
* mipi_dcphy1 needs to be enabled
* when dsi1 is enabled
*/
&dsi1 {
status = "disabled";
};
&dsi1_in_vp2 {
status = "disabled";
};
&dsi1_in_vp3 {
status = "disabled";
};
&dsi1_panel {
power-supply = <&vcc3v3_lcd_n>;
/*
* because in hardware, the two screens share the reset pin,
* so reset-gpios need only in dsi1 enable and dsi0 disabled
* case.
*/
//reset-gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_LOW>;
//pinctrl-names = "default";
//pinctrl-0 = <&lcd_rst_gpio>;
};
&gmac1 {
/* Use rgmii-rxid mode to disable rx delay inside Soc */
phy-mode = "rgmii-rxid";
clock_in_out = "output";
snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
snps,reset-active-low;
/* Reset time is 20ms, 100ms for rtl8211f */
snps,reset-delays-us = <0 20000 100000>;
pinctrl-names = "default";
pinctrl-0 = <&gmac1_miim
&gmac1_tx_bus2
&gmac1_rx_bus2
&gmac1_rgmii_clk
&gmac1_rgmii_bus>;
tx_delay = <0x43>;
/* rx_delay = <0x3f>; */
phy-handle = <&rgmii_phy>;
status = "okay";
};
&hdmi0 {
enable-gpios = <&gpio4 RK_PB1 GPIO_ACTIVE_HIGH>;
status = "okay";
};
&hdmi0_in_vp0 {
status = "okay";
};
&hdmi0_sound {
status = "okay";
};
&hdmi1 {
enable-gpios = <&gpio4 RK_PB2 GPIO_ACTIVE_HIGH>;
status = "okay";
};
&hdmi1_in_vp1 {
status = "okay";
};
&hdmi1_sound {
status = "okay";
};
/* Should work with at least 128MB cma reserved above. */
&hdmirx_ctrler {
status = "okay";
#sound-dai-cells = <1>;
/* Effective level used to trigger HPD: 0-low, 1-high */
hpd-trigger-level = <1>;
hdmirx-det-gpios = <&gpio1 RK_PD5 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&hdmim1_rx &hdmirx_det>;
};
&hdptxphy_hdmi0 {
status = "okay";
};
&hdptxphy_hdmi1 {
status = "okay";
};
&i2c0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&i2c0m2_xfer>;
vdd_cpu_big0_s0: vdd_cpu_big0_mem_s0: rk8602@42 {
compatible = "rockchip,rk8602";
reg = <0x42>;
vin-supply = <&vcc5v0_sys>;
regulator-compatible = "rk860x-reg";
regulator-name = "vdd_cpu_big0_s0";
regulator-min-microvolt = <550000>;
regulator-max-microvolt = <1050000>;
regulator-ramp-delay = <2300>;
rockchip,suspend-voltage-selector = <1>;
regulator-boot-on;
regulator-always-on;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vdd_cpu_big1_s0: vdd_cpu_big1_mem_s0: rk8603@43 {
compatible = "rockchip,rk8603";
reg = <0x43>;
vin-supply = <&vcc5v0_sys>;
regulator-compatible = "rk860x-reg";
regulator-name = "vdd_cpu_big1_s0";
regulator-min-microvolt = <550000>;
regulator-max-microvolt = <1050000>;
regulator-ramp-delay = <2300>;
rockchip,suspend-voltage-selector = <1>;
regulator-boot-on;
regulator-always-on;
regulator-state-mem {
regulator-off-in-suspend;
};
};
};
&i2c1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&i2c1m2_xfer>;
vdd_npu_s0: vdd_npu_mem_s0: rk8602@42 {
compatible = "rockchip,rk8602";
reg = <0x42>;
vin-supply = <&vcc5v0_sys>;
regulator-compatible = "rk860x-reg";
regulator-name = "vdd_npu_s0";
regulator-min-microvolt = <550000>;
regulator-max-microvolt = <950000>;
regulator-ramp-delay = <2300>;
rockchip,suspend-voltage-selector = <1>;
regulator-boot-on;
regulator-always-on;
regulator-state-mem {
regulator-off-in-suspend;
};
};
};
&i2c4 {
status = "okay";
pinctrl-0 = <&i2c4m1_xfer>;
ls_stk3332: light@47 {
compatible = "ls_stk3332";
status = "disabled";
reg = <0x47>;
type = <SENSOR_TYPE_LIGHT>;
irq_enable = <0>;
als_threshold_high = <100>;
als_threshold_low = <10>;
als_ctrl_gain = <2>; /* 0:x1 1:x4 2:x16 3:x64 */
poll_delay_ms = <100>;
};
ps_stk3332: proximity@47 {
compatible = "ps_stk3332";
status = "disabled";
reg = <0x47>;
type = <SENSOR_TYPE_PROXIMITY>;
//pinctrl-names = "default";
//pinctrl-0 = <&gpio3_c6>;
//irq-gpio = <&gpio3 RK_PC6 IRQ_TYPE_LEVEL_LOW>;
//irq_enable = <1>;
ps_threshold_high = <0x200>;
ps_threshold_low = <0x100>;
ps_ctrl_gain = <3>; /* 0:x1 1:x2 2:x5 3:x8 */
ps_led_current = <4>; /* 0:3.125mA 1:6.25mA 2:12.5mA 3:25mA 4:50mA 5:100mA*/
poll_delay_ms = <100>;
};
mpu6500_acc: mpu_acc@68 {
compatible = "mpu6500_acc";
reg = <0x68>;
irq-gpio = <&gpio4 RK_PC2 IRQ_TYPE_EDGE_RISING>;
irq_enable = <0>;
poll_delay_ms = <30>;
type = <SENSOR_TYPE_ACCEL>;
layout = <5>;
};
mpu6500_gyro: mpu_gyro@68 {
compatible = "mpu6500_gyro";
reg = <0x68>;
poll_delay_ms = <30>;
type = <SENSOR_TYPE_GYROSCOPE>;
layout = <5>;
};
};
&i2c5 {
status = "okay";
gt1x: gt1x@14 {
compatible = "goodix,gt1x";
reg = <0x14>;
pinctrl-names = "default";
pinctrl-0 = <&touch_gpio>;
goodix,rst-gpio = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>;
goodix,irq-gpio = <&gpio3 RK_PC0 IRQ_TYPE_LEVEL_LOW>;
power-supply = <&vcc3v3_lcd_n>;
};
};
&i2c6 {
status = "okay";
usbc0: fusb302@22 {
compatible = "fcs,fusb302";
reg = <0x22>;
interrupt-parent = <&gpio3>;
interrupts = <RK_PB6 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&usbc0_int>;
vbus-supply = <&vbus5v0_typec>;
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
usbc0_role_sw: endpoint@0 {
remote-endpoint = <&dwc3_0_role_switch>;
};
};
};
usb_con: connector {
compatible = "usb-c-connector";
label = "USB-C";
data-role = "dual";
power-role = "dual";
try-power-role = "sink";
op-sink-microwatt = <1000000>;
sink-pdos =
<PDO_FIXED(5000, 1000, PDO_FIXED_USB_COMM)>;
source-pdos =
<PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
altmodes {
#address-cells = <1>;
#size-cells = <0>;
altmode@0 {
reg = <0>;
svid = <0xff01>;
vdo = <0xffffffff>;
};
};
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
usbc0_orien_sw: endpoint {
remote-endpoint = <&usbdp_phy0_orientation_switch>;
};
};
port@1 {
reg = <1>;
dp_altmode_mux: endpoint {
remote-endpoint = <&usbdp_phy0_dp_altmode_mux>;
};
};
};
};
};
hym8563: hym8563@51 {
compatible = "haoyu,hym8563";
reg = <0x51>;
#clock-cells = <0>;
clock-frequency = <32768>;
clock-output-names = "hym8563";
pinctrl-names = "default";
pinctrl-0 = <&hym8563_int>;
interrupt-parent = <&gpio0>;
interrupts = <RK_PB0 IRQ_TYPE_LEVEL_LOW>;
wakeup-source;
};
};
&i2c7 {
status = "okay";
es8388: es8388@11 {
status = "okay";
#sound-dai-cells = <0>;
compatible = "everest,es8388", "everest,es8323";
reg = <0x11>;
clocks = <&cru I2S0_8CH_MCLKOUT>;
clock-names = "mclk";
assigned-clocks = <&cru I2S0_8CH_MCLKOUT>;
assigned-clock-rates = <12288000>;
pinctrl-names = "default";
pinctrl-0 = <&i2s0_mclk>;
};
};
&i2s5_8ch {
status = "okay";
};
&i2s6_8ch {
status = "okay";
};
&i2s7_8ch {
status = "okay";
};
&mdio1 {
rgmii_phy: phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0x1>;
};
};
&mipi_dcphy0 {
status = "okay";
};
&mipi_dcphy1 {
status = "disabled";
};
&pcie2x1l0 {
reset-gpios = <&gpio1 RK_PB4 GPIO_ACTIVE_HIGH>;
status = "okay";
};
&pcie30phy {
rockchip,pcie30-phymode = <PHY_MODE_PCIE_AGGREGATION>;
status = "okay";
};
&pcie3x4 {
reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>;
vpcie3v3-supply = <&vcc3v3_pcie30>;
pinctrl-names = "default";
pinctrl-0 = <&pcie20x1_0_clkreqn_m1>;
status = "okay";
};
&pinctrl {
cam {
mipicsi0_pwr: mipicsi0-pwr {
rockchip,pins =
/* camera power en */
<1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
};
mipicsi1_pwr: mipicsi1-pwr {
rockchip,pins =
/* camera power en */
<1 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
};
mipidcphy0_pwr: mipidcphy0-pwr {
rockchip,pins =
/* camera power en */
<2 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
hdmi {
hdmirx_det: hdmirx-det {
rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
headphone {
hp_det: hp-det {
rockchip,pins = <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
hym8563 {
hym8563_int: hym8563-int {
rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
lcd {
lcd_rst_gpio: lcd-rst-gpio {
rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
sdio-pwrseq {
wifi_enable_h: wifi-enable-h {
rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
sdmmc {
sd_s0_pwr: sd-s0-pwr {
rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
touch {
touch_gpio: touch-gpio {
rockchip,pins =
<3 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>,
<3 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
usb {
vcc5v0_host_en: vcc5v0-host-en {
rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
usb-typec {
usbc0_int: usbc0-int {
rockchip,pins = <3 RK_PB6 RK_FUNC_GPIO &pcfg_pull_up>;
};
typec5v_pwren: typec5v-pwren {
rockchip,pins = <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
wireless-bluetooth {
uart9_gpios: uart9-gpios {
rockchip,pins = <4 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>;
};
bt_reset_gpio: bt-reset-gpio {
rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
};
bt_wake_gpio: bt-wake-gpio {
rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
};
bt_irq_gpio: bt-irq-gpio {
rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
wireless-wlan {
wifi_host_wake_irq: wifi-host-wake-irq {
rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_down>;
};
};
pcie {
pcie20x1_0_clkreqn_m1: pcie20x1-0-clkreqn-m1 {
rockchip,pins = <4 RK_PB4 RK_FUNC_GPIO &pcfg_output_low>;
};
};
};
&pwm1 {
status = "okay";
};
&pwm3 {
pinctrl-0 = <&pwm3m1_pins>;
status = "okay";
};
&route_dsi0 {
status = "okay";
connect = <&vp3_out_dsi0>;
};
&route_dsi1 {
status = "disabled";
connect = <&vp3_out_dsi1>;
};
&route_hdmi0 {
status = "okay";
};
&route_hdmi1 {
status = "okay";
};
&sata0 {
status = "okay";
};
&sdio {
max-frequency = <150000000>;
no-sd;
no-mmc;
bus-width = <4>;
disable-wp;
cap-sd-highspeed;
cap-sdio-irq;
keep-power-in-suspend;
mmc-pwrseq = <&sdio_pwrseq>;
non-removable;
pinctrl-names = "default";
pinctrl-0 = <&sdiom0_pins>;
sd-uhs-sdr104;
status = "okay";
};
&sdmmc {
status = "okay";
vmmc-supply = <&vcc_3v3_sd_s0>;
};
&uart9 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&uart9m0_xfer &uart9m0_ctsn>;
};
&u2phy0_otg {
rockchip,typec-vbus-det;
};
&u2phy1_otg {
phy-supply = <&vcc5v0_host>;
};
&u2phy2_host {
phy-supply = <&vcc5v0_host>;
};
&u2phy3_host {
phy-supply = <&vcc5v0_host>;
};
&usbdp_phy0 {
orientation-switch;
svid = <0xff01>;
sbu1-dc-gpios = <&gpio4 RK_PA0 GPIO_ACTIVE_HIGH>;
sbu2-dc-gpios = <&gpio4 RK_PA1 GPIO_ACTIVE_HIGH>;
port {
#address-cells = <1>;
#size-cells = <0>;
usbdp_phy0_orientation_switch: endpoint@0 {
reg = <0>;
remote-endpoint = <&usbc0_orien_sw>;
};
usbdp_phy0_dp_altmode_mux: endpoint@1 {
reg = <1>;
remote-endpoint = <&dp_altmode_mux>;
};
};
};
&usbdp_phy1 {
rockchip,dp-lane-mux = <0 1 2 3>;
};
&usbdrd_dwc3_0 {
dr_mode = "otg";
usb-role-switch;
port {
#address-cells = <1>;
#size-cells = <0>;
dwc3_0_role_switch: endpoint@0 {
reg = <0>;
remote-endpoint = <&usbc0_role_sw>;
};
};
};
&usbhost3_0 {
status = "disabled";
};
&usbhost_dwc3_0 {
status = "disabled";
};

1
arch/arm64/boot/dts/rockchip/rk3588.dtsi
View File

@@ -139,6 +139,7 @@
snps,dis-u2-freeclk-exists-quirk;
snps,dis-del-phy-power-chg-quirk;
snps,dis-tx-ipgap-linecheck-quirk;
snps,parkmode-disable-ss-quirk;
status = "disabled";
};
};

1
arch/arm64/boot/dts/rockchip/rk3588j.dtsi
View File

@@ -8,6 +8,7 @@
&cluster0_opp_table {
/delete-node/ opp-1608000000;
/delete-node/ opp-1704000000;
/delete-node/ opp-1800000000;
};

20
arch/arm64/boot/dts/rockchip/rk3588m.dtsi
View File

@@ -8,26 +8,6 @@
&cluster0_opp_table {
/delete-node/ opp-1800000000;
opp-1704000000 {
opp-supported-hw = <0x02 0xffff>;
opp-hz = /bits/ 64 <1704000000>;
opp-microvolt = <900000 900000 950000>,
<900000 900000 950000>;
opp-microvolt-L1 = <887500 887500 950000>,
<887500 887500 950000>;
opp-microvolt-L2 = <875000 875000 950000>,
<875000 875000 950000>;
opp-microvolt-L3 = <862500 862500 950000>,
<862500 862500 950000>;
opp-microvolt-L4 = <850000 850000 950000>,
<850000 850000 950000>;
opp-microvolt-L5 = <837500 837500 950000>,
<837500 837500 950000>;
opp-microvolt-L6 = <825000 825000 950000>,
<825000 825000 950000>;
clock-latency-ns = <40000>;
};
};
&cluster1_opp_table {

92
arch/arm64/boot/dts/rockchip/rk3588s.dtsi
View File

@@ -596,8 +596,16 @@
rockchip,pvtm-thermal-zone = "soc-thermal";
rockchip,grf = <&litcore_grf>;
rockchip,reboot-freq = <1416000>;
rockchip,dsu-grf = <&dsu_grf>;
volt-mem-read-margin = <
855000 1
765000 2
675000 3
495000 4
>;
low-volt-mem-read-margin = <4>;
intermediate-threshold-freq = <1008000>; /* KHz */
rockchip,reboot-freq = <1416000>; /* KHz */
rockchip,temp-hysteresis = <5000>;
rockchip,low-temp = <10000>;
@@ -673,7 +681,7 @@
opp-suspend;
};
opp-1608000000 {
opp-supported-hw = <0xff 0xffff>;
opp-supported-hw = <0xfb 0xffff>;
opp-hz = /bits/ 64 <1608000000>;
opp-microvolt = <850000 850000 950000>,
<850000 850000 950000>;
@@ -691,8 +699,27 @@
<787500 787500 950000>;
clock-latency-ns = <40000>;
};
opp-1704000000 {
opp-supported-hw = <0x02 0xffff>;
opp-hz = /bits/ 64 <1704000000>;
opp-microvolt = <900000 900000 950000>,
<900000 900000 950000>;
opp-microvolt-L1 = <887500 887500 950000>,
<887500 887500 950000>;
opp-microvolt-L2 = <875000 875000 950000>,
<875000 875000 950000>;
opp-microvolt-L3 = <862500 862500 950000>,
<862500 862500 950000>;
opp-microvolt-L4 = <850000 850000 950000>,
<850000 850000 950000>;
opp-microvolt-L5 = <837500 837500 950000>,
<837500 837500 950000>;
opp-microvolt-L6 = <825000 825000 950000>,
<825000 825000 950000>;
clock-latency-ns = <40000>;
};
opp-1800000000 {
opp-supported-hw = <0xfd 0xffff>;
opp-supported-hw = <0xf9 0xffff>;
opp-hz = /bits/ 64 <1800000000>;
opp-microvolt = <950000 950000 950000>,
<950000 950000 950000>;
@@ -833,7 +860,7 @@
clock-latency-ns = <40000>;
};
opp-1800000000 {
opp-supported-hw = <0xff 0xffff>;
opp-supported-hw = <0xfb 0xffff>;
opp-hz = /bits/ 64 <1800000000>;
opp-microvolt = <850000 850000 1000000>,
<850000 850000 1000000>;
@@ -854,7 +881,7 @@
clock-latency-ns = <40000>;
};
opp-2016000000 {
opp-supported-hw = <0xff 0xffff>;
opp-supported-hw = <0xfb 0xffff>;
opp-hz = /bits/ 64 <2016000000>;
opp-microvolt = <925000 925000 1000000>,
<925000 925000 1000000>;
@@ -875,7 +902,7 @@
clock-latency-ns = <40000>;
};
opp-2208000000 {
opp-supported-hw = <0xfd 0xffff>;
opp-supported-hw = <0xf9 0xffff>;
opp-hz = /bits/ 64 <2208000000>;
opp-microvolt = <987500 987500 1000000>,
<987500 987500 1000000>;
@@ -896,28 +923,28 @@
clock-latency-ns = <40000>;
};
opp-2256000000 {
opp-supported-hw = <0xfd 0x13>;
opp-supported-hw = <0xf9 0x13>;
opp-hz = /bits/ 64 <2256000000>;
opp-microvolt = <1000000 1000000 1000000>,
<1000000 1000000 1000000>;
clock-latency-ns = <40000>;
};
opp-2304000000 {
opp-supported-hw = <0xfd 0x24>;
opp-supported-hw = <0xf9 0x24>;
opp-hz = /bits/ 64 <2304000000>;
opp-microvolt = <1000000 1000000 1000000>,
<1000000 1000000 1000000>;
clock-latency-ns = <40000>;
};
opp-2352000000 {
opp-supported-hw = <0xfd 0x48>;
opp-supported-hw = <0xf9 0x48>;
opp-hz = /bits/ 64 <2352000000>;
opp-microvolt = <1000000 1000000 1000000>,
<1000000 1000000 1000000>;
clock-latency-ns = <40000>;
};
opp-2400000000 {
opp-supported-hw = <0xfd 0x80>;
opp-supported-hw = <0xf9 0x80>;
opp-hz = /bits/ 64 <2400000000>;
opp-microvolt = <1000000 1000000 1000000>,
<1000000 1000000 1000000>;
@@ -1046,7 +1073,7 @@
clock-latency-ns = <40000>;
};
opp-1800000000 {
opp-supported-hw = <0xff 0xffff>;
opp-supported-hw = <0xfb 0xffff>;
opp-hz = /bits/ 64 <1800000000>;
opp-microvolt = <850000 850000 1000000>,
<850000 850000 1000000>;
@@ -1067,7 +1094,7 @@
clock-latency-ns = <40000>;
};
opp-2016000000 {
opp-supported-hw = <0xff 0xffff>;
opp-supported-hw = <0xfb 0xffff>;
opp-hz = /bits/ 64 <2016000000>;
opp-microvolt = <925000 925000 1000000>,
<925000 925000 1000000>;
@@ -1088,7 +1115,7 @@
clock-latency-ns = <40000>;
};
opp-2208000000 {
opp-supported-hw = <0xfd 0xffff>;
opp-supported-hw = <0xf9 0xffff>;
opp-hz = /bits/ 64 <2208000000>;
opp-microvolt = <987500 987500 1000000>,
<987500 987500 1000000>;
@@ -1105,28 +1132,28 @@
clock-latency-ns = <40000>;
};
opp-2256000000 {
opp-supported-hw = <0xfd 0x13>;
opp-supported-hw = <0xf9 0x13>;
opp-hz = /bits/ 64 <2256000000>;
opp-microvolt = <1000000 1000000 1000000>,
<1000000 1000000 1000000>;
clock-latency-ns = <40000>;
};
opp-2304000000 {
opp-supported-hw = <0xfd 0x24>;
opp-supported-hw = <0xf9 0x24>;
opp-hz = /bits/ 64 <2304000000>;
opp-microvolt = <1000000 1000000 1000000>,
<1000000 1000000 1000000>;
clock-latency-ns = <40000>;
};
opp-2352000000 {
opp-supported-hw = <0xfd 0x48>;
opp-supported-hw = <0xf9 0x48>;
opp-hz = /bits/ 64 <2352000000>;
opp-microvolt = <1000000 1000000 1000000>,
<1000000 1000000 1000000>;
clock-latency-ns = <40000>;
};
opp-2400000000 {
opp-supported-hw = <0xfd 0x80>;
opp-supported-hw = <0xf9 0x80>;
opp-hz = /bits/ 64 <2400000000>;
opp-microvolt = <1000000 1000000 1000000>,
<1000000 1000000 1000000>;
@@ -1757,8 +1784,9 @@
gpu_opp_table: gpu-opp-table {
compatible = "operating-points-v2";
nvmem-cells = <&gpu_leakage>;
nvmem-cell-names = "leakage";
nvmem-cells = <&gpu_leakage>, <&specification_serial_number>;
nvmem-cell-names = "leakage", "specification_serial_number";
rockchip,supported-hw;
rockchip,pvtm-voltage-sel = <
0 815 0
@@ -1796,26 +1824,31 @@
rockchip,high-temp-max-freq = <800000>;
opp-300000000 {
opp-supported-hw = <0xff 0xffff>;
opp-hz = /bits/ 64 <300000000>;
opp-microvolt = <675000 675000 850000>,
<675000 675000 850000>;
};
opp-400000000 {
opp-supported-hw = <0xff 0xffff>;
opp-hz = /bits/ 64 <400000000>;
opp-microvolt = <675000 675000 850000>,
<675000 675000 850000>;
};
opp-500000000 {
opp-supported-hw = <0xff 0xffff>;
opp-hz = /bits/ 64 <500000000>;
opp-microvolt = <675000 675000 850000>,
<675000 675000 850000>;
};
opp-600000000 {
opp-supported-hw = <0xff 0xffff>;
opp-hz = /bits/ 64 <600000000>;
opp-microvolt = <675000 675000 850000>,
<675000 675000 850000>;
};
opp-700000000 {
opp-supported-hw = <0xff 0xffff>;
opp-hz = /bits/ 64 <700000000>;
opp-microvolt = <700000 700000 850000>,
<700000 700000 850000>;
@@ -1829,6 +1862,7 @@
<675000 675000 850000>;
};
opp-800000000 {
opp-supported-hw = <0xff 0xffff>;
opp-hz = /bits/ 64 <800000000>;
opp-microvolt = <750000 750000 850000>,
<750000 750000 850000>;
@@ -1844,6 +1878,7 @@
<700000 700000 850000>;
};
opp-900000000 {
opp-supported-hw = <0xfb 0xffff>;
opp-hz = /bits/ 64 <900000000>;
opp-microvolt = <800000 800000 850000>,
<800000 800000 850000>;
@@ -1859,6 +1894,7 @@
<737500 737500 850000>;
};
opp-1000000000 {
opp-supported-hw = <0xfb 0xffff>;
opp-hz = /bits/ 64 <1000000000>;
opp-microvolt = <850000 850000 850000>,
<850000 850000 850000>;
@@ -1903,6 +1939,7 @@
snps,dis-u2-freeclk-exists-quirk;
snps,dis-del-phy-power-chg-quirk;
snps,dis-tx-ipgap-linecheck-quirk;
snps,parkmode-disable-ss-quirk;
quirk-skip-phy-init;
status = "disabled";
};
@@ -2008,6 +2045,7 @@
snps,dis-del-phy-power-chg-quirk;
snps,dis-tx-ipgap-linecheck-quirk;
snps,dis_rxdet_inp3_quirk;
snps,parkmode-disable-ss-quirk;
status = "disabled";
};
};
@@ -2728,8 +2766,9 @@
npu_opp_table: npu-opp-table {
compatible = "operating-points-v2";
nvmem-cells = <&npu_leakage>;
nvmem-cell-names = "leakage";
nvmem-cells = <&npu_leakage>, <&specification_serial_number>;
nvmem-cell-names = "leakage", "specification_serial_number";
rockchip,supported-hw;
rockchip,pvtm-voltage-sel = <
0 815 0
@@ -2768,6 +2807,7 @@
rockchip,high-temp-max-freq = <800000>;
opp-300000000 {
opp-supported-hw = <0xff 0xffff>;
opp-hz = /bits/ 64 <300000000>;
opp-microvolt = <700000 700000 850000>,
<700000 700000 850000>;
@@ -2783,6 +2823,7 @@
<675000 675000 850000>;
};
opp-400000000 {
opp-supported-hw = <0xff 0xffff>;
opp-hz = /bits/ 64 <400000000>;
opp-microvolt = <700000 700000 850000>,
<700000 700000 850000>;
@@ -2798,6 +2839,7 @@
<675000 675000 850000>;
};
opp-500000000 {
opp-supported-hw = <0xff 0xffff>;
opp-hz = /bits/ 64 <500000000>;
opp-microvolt = <700000 700000 850000>,
<700000 700000 850000>;
@@ -2813,6 +2855,7 @@
<675000 675000 850000>;
};
opp-600000000 {
opp-supported-hw = <0xff 0xffff>;
opp-hz = /bits/ 64 <600000000>;
opp-microvolt = <700000 700000 850000>,
<700000 700000 850000>;
@@ -2828,6 +2871,7 @@
<675000 675000 850000>;
};
opp-700000000 {
opp-supported-hw = <0xff 0xffff>;
opp-hz = /bits/ 64 <700000000>;
opp-microvolt = <700000 700000 850000>,
<700000 700000 850000>;
@@ -2839,6 +2883,7 @@
<675000 675000 850000>;
};
opp-800000000 {
opp-supported-hw = <0xff 0xffff>;
opp-hz = /bits/ 64 <800000000>;
opp-microvolt = <750000 750000 850000>,
<750000 750000 850000>;
@@ -2852,6 +2897,7 @@
<700000 700000 850000>;
};
opp-900000000 {
opp-supported-hw = <0xfb 0xffff>;
opp-hz = /bits/ 64 <900000000>;
opp-microvolt = <800000 800000 850000>,
<800000 800000 850000>;
@@ -2867,6 +2913,7 @@
<737500 737500 850000>;
};
opp-1000000000 {
opp-supported-hw = <0xfb 0xffff>;
opp-hz = /bits/ 64 <1000000000>;
opp-microvolt = <850000 850000 850000>,
<850000 850000 850000>;
@@ -2964,6 +3011,7 @@
clock-names = "aclk_vcodec", "hclk_vcodec";
resets = <&cru SRST_A_VPU>, <&cru SRST_H_VPU>;
reset-names = "shared_video_a", "shared_video_h";
rockchip,skip-pmu-idle-request;
iommus = <&vdpu_mmu>;
power-domains = <&power RK3588_PD_VDPU>;
rockchip,srv = <&mpp_srv>;

6
arch/arm64/configs/rockchip_defconfig
View File

@@ -363,6 +363,7 @@ CONFIG_STMMAC_ETH=y
# CONFIG_NET_VENDOR_TI is not set
# CONFIG_NET_VENDOR_VIA is not set
# CONFIG_NET_VENDOR_WIZNET is not set
CONFIG_MOTORCOMM_PHY=y
CONFIG_ROCKCHIP_PHY=y
CONFIG_PPP=y
CONFIG_PPP_BSDCOMP=y
@@ -574,6 +575,7 @@ CONFIG_VIDEO_ROCKCHIP_ISP=y
CONFIG_VIDEO_ROCKCHIP_ISPP=y
CONFIG_VIDEO_ROCKCHIP_HDMIRX=y
CONFIG_VIDEO_LT6911UXC=y
CONFIG_VIDEO_LT6911UXE=y
CONFIG_VIDEO_LT7911D=y
CONFIG_VIDEO_NVP6188=y
CONFIG_VIDEO_RK628_CSI=y
@@ -582,6 +584,8 @@ CONFIG_VIDEO_TC35874X=y
CONFIG_VIDEO_THCV244=y
CONFIG_VIDEO_RK_IRCUT=y
CONFIG_VIDEO_GC0312=y
CONFIG_VIDEO_GC2053=y
CONFIG_VIDEO_GC2093=y
CONFIG_VIDEO_GC2145=y
CONFIG_VIDEO_GC2385=y
CONFIG_VIDEO_GC4C33=y
@@ -626,7 +630,6 @@ CONFIG_DRM_PANEL_SIMPLE=y
CONFIG_DRM_PANEL_MAXIM_DESERIALIZER=y
CONFIG_DRM_DISPLAY_CONNECTOR=y
CONFIG_DRM_MAXIM_MAX96745=y
CONFIG_DRM_MAXIM_MAX96752F=y
CONFIG_DRM_MAXIM_MAX96755F=y
CONFIG_DRM_RK630_TVE=y
CONFIG_DRM_RK1000_TVE=y
@@ -877,6 +880,7 @@ CONFIG_CPU_PX30=y
CONFIG_CPU_RK3328=y
CONFIG_CPU_RK3368=y
CONFIG_CPU_RK3399=y
CONFIG_CPU_RK3528=y
CONFIG_CPU_RK3568=y
CONFIG_CPU_RK3588=y
CONFIG_ROCKCHIP_CPUINFO=y

3
arch/arm64/configs/rockchip_gki.config
View File

@@ -1,3 +1,4 @@
CONFIG_PWRSEQ_SIMPLE=m
CONFIG_AP6XXX=m
CONFIG_ARCH_ROCKCHIP=y
CONFIG_ARM_ROCKCHIP_BUS_DEVFREQ=m
@@ -29,6 +30,7 @@ CONFIG_COMPASS_DEVICE=m
CONFIG_CPUFREQ_DT=m
CONFIG_CPU_FREQ_GOV_ONDEMAND=m
CONFIG_CPU_FREQ_GOV_USERSPACE=m
CONFIG_CPU_RK3568=y
CONFIG_CPU_RK3588=y
CONFIG_CRYPTO_AES_ARM64_CE_CCM=m
CONFIG_CRYPTO_DEV_ROCKCHIP=m
@@ -44,7 +46,6 @@ CONFIG_DRM_DISPLAY_CONNECTOR=m
CONFIG_DRM_DW_HDMI_CEC=m
CONFIG_DRM_DW_HDMI_I2S_AUDIO=m
CONFIG_DRM_MAXIM_MAX96745=m
CONFIG_DRM_MAXIM_MAX96752F=m
CONFIG_DRM_MAXIM_MAX96755F=m
CONFIG_DRM_PANEL_SIMPLE=m
CONFIG_DRM_RK1000_TVE=m

1
arch/arm64/configs/rockchip_linux_defconfig
View File

@@ -177,6 +177,7 @@ CONFIG_STMMAC_ETH=y
# CONFIG_NET_VENDOR_TI is not set
# CONFIG_NET_VENDOR_VIA is not set
# CONFIG_NET_VENDOR_WIZNET is not set
CONFIG_MOTORCOMM_PHY=y
CONFIG_ROCKCHIP_PHY=y
CONFIG_USB_RTL8150=y
CONFIG_USB_RTL8152=y

36
drivers/clk/rockchip/clk-rk3036.c
View File

@@ -119,15 +119,17 @@ static const struct rockchip_cpuclk_reg_data rk3036_cpuclk_data = {
PNAME(mux_pll_p) = { "xin24m", "xin24m" };
PNAME(mux_busclk_p) = { "apll", "dpll_cpu", "gpll_cpu" };
PNAME(mux_busclk_p) = { "dummy_apll", "dpll_cpu", "gpll_cpu" };
PNAME(mux_ddrphy_p) = { "dpll_ddr", "gpll_ddr" };
PNAME(mux_pll_src_3plls_p) = { "apll", "dpll", "gpll" };
PNAME(mux_pll_src_apll_dpll_gpll_p) = { "apll", "dpll", "gpll" };
PNAME(mux_pll_src_dmyapll_dpll_gpll_p) = { "dummy_apll", "dpll", "gpll" };
PNAME(mux_timer_p) = { "xin24m", "pclk_peri_src" };
PNAME(mux_pll_src_apll_dpll_gpll_usb480m_p) = { "apll", "dpll", "gpll", "usb480m" };
PNAME(mux_pll_src_dmyapll_dpll_gpll_usb480m_p) = { "dummy_apll", "dpll", "gpll", "usb480m" };
PNAME(mux_pll_src_dmyapll_dpll_gpll_xin24_p) = { "dummy_apll", "dpll", "gpll", "xin24m" };
PNAME(mux_mmc_src_p) = { "apll", "dpll", "gpll", "xin24m" };
PNAME(mux_mmc_src_p) = { "dummy_apll", "dpll", "gpll", "xin24m" };
PNAME(mux_i2s_pre_p) = { "i2s_src", "i2s_frac", "ext_i2s", "xin12m" };
PNAME(mux_i2s_clkout_p) = { "i2s_pre", "xin12m" };
PNAME(mux_spdif_p) = { "spdif_src", "spdif_frac", "xin12m" };
@@ -212,7 +214,7 @@ static struct rockchip_clk_branch rk3036_clk_branches[] __initdata = {
RK2928_CLKSEL_CON(1), 8, 2, DFLAGS | CLK_DIVIDER_READ_ONLY,
RK2928_CLKGATE_CON(0), 4, GFLAGS),
COMPOSITE(0, "aclk_peri_src", mux_pll_src_3plls_p, CLK_IS_CRITICAL,
COMPOSITE(0, "aclk_peri_src", mux_pll_src_dmyapll_dpll_gpll_p, 0,
RK2928_CLKSEL_CON(10), 14, 2, MFLAGS, 0, 5, DFLAGS,
RK2928_CLKGATE_CON(2), 0, GFLAGS),
@@ -240,7 +242,7 @@ static struct rockchip_clk_branch rk3036_clk_branches[] __initdata = {
RK2928_CLKSEL_CON(2), 7, 1, MFLAGS,
RK2928_CLKGATE_CON(2), 5, GFLAGS),
MUX(0, "uart_pll_clk", mux_pll_src_apll_dpll_gpll_usb480m_p, 0,
MUX(0, "uart_pll_clk", mux_pll_src_dmyapll_dpll_gpll_usb480m_p, 0,
RK2928_CLKSEL_CON(13), 10, 2, MFLAGS),
COMPOSITE_NOMUX(0, "uart0_src", "uart_pll_clk", 0,
RK2928_CLKSEL_CON(13), 0, 7, DFLAGS,
@@ -264,23 +266,23 @@ static struct rockchip_clk_branch rk3036_clk_branches[] __initdata = {
RK2928_CLKGATE_CON(1), 13, GFLAGS,
&rk3036_uart2_fracmux),
COMPOSITE(0, "aclk_vcodec", mux_pll_src_3plls_p, 0,
COMPOSITE(ACLK_VCODEC, "aclk_vcodec", mux_pll_src_dmyapll_dpll_gpll_p, 0,
RK2928_CLKSEL_CON(32), 14, 2, MFLAGS, 8, 5, DFLAGS,
RK2928_CLKGATE_CON(3), 11, GFLAGS),
FACTOR_GATE(HCLK_VCODEC, "hclk_vcodec", "aclk_vcodec", 0, 1, 4,
RK2928_CLKGATE_CON(3), 12, GFLAGS),
COMPOSITE(ACLK_HEVC, "aclk_hevc", mux_pll_src_3plls_p, 0,
COMPOSITE(ACLK_HEVC, "aclk_hevc", mux_pll_src_dmyapll_dpll_gpll_p, 0,
RK2928_CLKSEL_CON(20), 0, 2, MFLAGS, 2, 5, DFLAGS,
RK2928_CLKGATE_CON(10), 6, GFLAGS),
COMPOSITE(0, "aclk_disp1_pre", mux_pll_src_3plls_p, 0,
COMPOSITE(0, "aclk_disp1_pre", mux_pll_src_dmyapll_dpll_gpll_p, 0,
RK2928_CLKSEL_CON(31), 14, 2, MFLAGS, 8, 5, DFLAGS,
RK2928_CLKGATE_CON(1), 4, GFLAGS),
COMPOSITE(0, "hclk_disp_pre", mux_pll_src_3plls_p, 0,
COMPOSITE(0, "hclk_disp_pre", mux_pll_src_dmyapll_dpll_gpll_p, 0,
RK2928_CLKSEL_CON(30), 14, 2, MFLAGS, 8, 5, DFLAGS,
RK2928_CLKGATE_CON(0), 11, GFLAGS),
COMPOSITE(SCLK_LCDC, "dclk_lcdc", mux_pll_src_3plls_p, 0,
COMPOSITE(SCLK_LCDC, "dclk_lcdc", mux_pll_src_apll_dpll_gpll_p, 0,
RK2928_CLKSEL_CON(28), 0, 2, MFLAGS, 8, 8, DFLAGS,
RK2928_CLKGATE_CON(3), 2, GFLAGS),
@@ -309,7 +311,7 @@ static struct rockchip_clk_branch rk3036_clk_branches[] __initdata = {
MMC(SCLK_EMMC_DRV, "emmc_drv", "sclk_emmc", RK3036_EMMC_CON0, 1),
MMC(SCLK_EMMC_SAMPLE, "emmc_sample", "sclk_emmc", RK3036_EMMC_CON1, 0),
COMPOSITE(0, "i2s_src", mux_pll_src_3plls_p, 0,
COMPOSITE(0, "i2s_src", mux_pll_src_dmyapll_dpll_gpll_p, 0,
RK2928_CLKSEL_CON(3), 14, 2, MFLAGS, 0, 7, DFLAGS,
RK2928_CLKGATE_CON(0), 9, GFLAGS),
COMPOSITE_FRACMUX(SCLK_I2S_FRAC, "i2s_frac", "i2s_src", CLK_SET_RATE_PARENT,
@@ -322,7 +324,7 @@ static struct rockchip_clk_branch rk3036_clk_branches[] __initdata = {
GATE(SCLK_I2S, "sclk_i2s", "i2s_pre", CLK_SET_RATE_PARENT,
RK2928_CLKGATE_CON(0), 14, GFLAGS),
COMPOSITE(0, "spdif_src", mux_pll_src_3plls_p, 0,
COMPOSITE(0, "spdif_src", mux_pll_src_dmyapll_dpll_gpll_p, 0,
RK2928_CLKSEL_CON(5), 10, 2, MFLAGS, 0, 7, DFLAGS,
RK2928_CLKGATE_CON(2), 10, GFLAGS),
COMPOSITE_FRACMUX(0, "spdif_frac", "spdif_src", 0,
@@ -333,15 +335,15 @@ static struct rockchip_clk_branch rk3036_clk_branches[] __initdata = {
GATE(SCLK_OTGPHY0, "sclk_otgphy0", "xin12m", CLK_IGNORE_UNUSED,
RK2928_CLKGATE_CON(1), 5, GFLAGS),
COMPOSITE(SCLK_GPU, "sclk_gpu", mux_pll_src_3plls_p, 0,
COMPOSITE(SCLK_GPU, "sclk_gpu", mux_pll_src_dmyapll_dpll_gpll_p, 0,
RK2928_CLKSEL_CON(34), 8, 2, MFLAGS, 0, 5, DFLAGS,
RK2928_CLKGATE_CON(3), 13, GFLAGS),
COMPOSITE(SCLK_SPI, "sclk_spi", mux_pll_src_3plls_p, 0,
COMPOSITE(SCLK_SPI, "sclk_spi", mux_pll_src_dmyapll_dpll_gpll_p, 0,
RK2928_CLKSEL_CON(25), 8, 2, MFLAGS, 0, 7, DFLAGS,
RK2928_CLKGATE_CON(2), 9, GFLAGS),
COMPOSITE(SCLK_NANDC, "sclk_nandc", mux_pll_src_3plls_p, 0,
COMPOSITE(SCLK_NANDC, "sclk_nandc", mux_pll_src_dmyapll_dpll_gpll_p, 0,
RK2928_CLKSEL_CON(16), 8, 2, MFLAGS, 10, 5, DFLAGS,
RK2928_CLKGATE_CON(10), 4, GFLAGS),
@@ -349,7 +351,7 @@ static struct rockchip_clk_branch rk3036_clk_branches[] __initdata = {
RK2928_CLKSEL_CON(16), 0, 2, MFLAGS, 2, 5, DFLAGS,
RK2928_CLKGATE_CON(10), 5, GFLAGS),
COMPOSITE_NOGATE(SCLK_MACPLL, "mac_pll_src", mux_pll_src_3plls_p, CLK_SET_RATE_NO_REPARENT,
COMPOSITE_NOGATE(SCLK_MACPLL, "mac_pll_src", mux_pll_src_apll_dpll_gpll_p, CLK_SET_RATE_NO_REPARENT,
RK2928_CLKSEL_CON(21), 0, 2, MFLAGS, 9, 5, DFLAGS),
MUX(SCLK_MACREF, "mac_clk_ref", mux_mac_p, CLK_SET_RATE_PARENT,
RK2928_CLKSEL_CON(21), 3, 1, MFLAGS),

6
drivers/clk/rockchip/clk-rk3128.c
View File

@@ -212,9 +212,9 @@ static struct rockchip_clk_branch common_clk_branches[] __initdata = {
RK2928_CLKGATE_CON(0), 2, GFLAGS),
GATE(0, "gpll_div2_ddr", "gpll_div2", CLK_IGNORE_UNUSED,
RK2928_CLKGATE_CON(0), 2, GFLAGS),
COMPOSITE_NOGATE(0, "ddrphy2x", mux_ddrphy_p, CLK_IGNORE_UNUSED,
RK2928_CLKSEL_CON(26), 8, 2, MFLAGS, 0, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO),
FACTOR(SCLK_DDRC, "clk_ddrc", "ddrphy2x", 0, 1, 2),
COMPOSITE_DDRCLK(SCLK_DDRC, "clk_ddrc", mux_ddrphy_p, 0,
RK2928_CLKSEL_CON(26), 8, 2, 0, 2,
ROCKCHIP_DDRCLK_SIP_V2),
FACTOR(0, "clk_ddrphy", "ddrphy2x", 0, 1, 2),
/* PD_CORE */

4
drivers/clk/rockchip/clk-rk3288.c
View File

@@ -339,7 +339,7 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
RK3288_CLKGATE_CON(0), 9, GFLAGS),
COMPOSITE_DDRCLK(SCLK_DDRCLK, "sclk_ddrc", mux_ddrphy_p, 0,
RK3288_CLKSEL_CON(26), 2, 1, 0, 0,
ROCKCHIP_DDRCLK_SIP),
ROCKCHIP_DDRCLK_SIP_V2),
COMPOSITE_NOGATE(0, "ddrphy", mux_ddrphy_p, CLK_IGNORE_UNUSED,
RK3288_CLKSEL_CON(26), 2, 1, MFLAGS, 0, 2,
DFLAGS | CLK_DIVIDER_POWER_OF_TWO),
@@ -724,7 +724,7 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
/* aclk_peri gates */
GATE(0, "aclk_peri_axi_matrix", "aclk_peri", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(6), 2, GFLAGS),
GATE(ACLK_DMAC2, "aclk_dmac2", "aclk_peri", 0, RK3288_CLKGATE_CON(6), 3, GFLAGS),
GATE(0, "aclk_peri_niu", "aclk_peri", 0, RK3288_CLKGATE_CON(7), 11, GFLAGS),
GATE(0, "aclk_peri_niu", "aclk_peri", CLK_IS_CRITICAL, RK3288_CLKGATE_CON(7), 11, GFLAGS),
GATE(ACLK_MMU, "aclk_mmu", "aclk_peri", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(8), 12, GFLAGS),
GATE(ACLK_GMAC, "aclk_gmac", "aclk_peri", 0, RK3288_CLKGATE_CON(8), 0, GFLAGS),
GATE(HCLK_GPS, "hclk_gps", "aclk_peri", 0, RK3288_CLKGATE_CON(8), 2, GFLAGS),

7
drivers/clk/rockchip/clk-rk3568.c
View File

@@ -1699,6 +1699,7 @@ static void __init rk3568_clk_init(struct device_node *np)
CLK_OF_DECLARE(rk3568_cru, "rockchip,rk3568-cru", rk3568_clk_init);
#ifdef MODULE
struct clk_rk3568_inits {
void (*inits)(struct device_node *np);
};
@@ -1723,7 +1724,7 @@ static const struct of_device_id clk_rk3568_match_table[] = {
};
MODULE_DEVICE_TABLE(of, clk_rk3568_match_table);
static int __init clk_rk3568_probe(struct platform_device *pdev)
static int clk_rk3568_probe(struct platform_device *pdev)
{
struct device_node *np = pdev->dev.of_node;
const struct of_device_id *match;
@@ -1741,14 +1742,16 @@ static int __init clk_rk3568_probe(struct platform_device *pdev)
}
static struct platform_driver clk_rk3568_driver = {
.probe = clk_rk3568_probe,
.driver = {
.name = "clk-rk3568",
.of_match_table = clk_rk3568_match_table,
.suppress_bind_attrs = true,
},
};
builtin_platform_driver_probe(clk_rk3568_driver, clk_rk3568_probe);
module_platform_driver(clk_rk3568_driver);
MODULE_DESCRIPTION("Rockchip RK3568 Clock Driver");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:clk-rk3568");
#endif /* MODULE */

7
drivers/clk/rockchip/clk-rk3588.c
View File

@@ -2456,6 +2456,7 @@ static void __init rk3588_clk_init(struct device_node *np)
CLK_OF_DECLARE(rk3588_cru, "rockchip,rk3588-cru", rk3588_clk_init);
#ifdef MODULE
struct clk_rk3588_inits {
void (*inits)(struct device_node *np);
};
@@ -2473,7 +2474,7 @@ static const struct of_device_id clk_rk3588_match_table[] = {
};
MODULE_DEVICE_TABLE(of, clk_rk3588_match_table);
static int __init clk_rk3588_probe(struct platform_device *pdev)
static int clk_rk3588_probe(struct platform_device *pdev)
{
struct device_node *np = pdev->dev.of_node;
const struct of_device_id *match;
@@ -2491,13 +2492,15 @@ static int __init clk_rk3588_probe(struct platform_device *pdev)
}
static struct platform_driver clk_rk3588_driver = {
.probe = clk_rk3588_probe,
.driver = {
.name = "clk-rk3588",
.of_match_table = clk_rk3588_match_table,
.suppress_bind_attrs = true,
},
};
builtin_platform_driver_probe(clk_rk3588_driver, clk_rk3588_probe);
module_platform_driver(clk_rk3588_driver);
MODULE_DESCRIPTION("Rockchip RK3588 Clock Driver");
MODULE_LICENSE("GPL");
#endif /* MODULE */

6
drivers/clk/rockchip/clk.c
View File

@@ -154,6 +154,9 @@ static int rockchip_clk_frac_notifier_cb(struct notifier_block *nb,
frac->mux_ops->set_parent(&frac_mux->hw,
frac->mux_frac_idx);
frac->rate_change_remuxed = 1;
clk_hw_set_parent(&frac_mux->hw,
clk_hw_get_parent_by_index(&frac_mux->hw,
frac->mux_frac_idx));
}
} else if (event == POST_RATE_CHANGE) {
/*
@@ -165,6 +168,9 @@ static int rockchip_clk_frac_notifier_cb(struct notifier_block *nb,
if (frac->rate_change_remuxed) {
frac->mux_ops->set_parent(&frac_mux->hw,
frac->rate_change_idx);
clk_hw_set_parent(&frac_mux->hw,
clk_hw_get_parent_by_index(&frac_mux->hw,
frac->rate_change_idx));
frac->rate_change_remuxed = 0;
}
}

2
drivers/cpufreq/Kconfig
View File

@@ -247,7 +247,7 @@ comment "CPU frequency scaling drivers"
config CPUFREQ_DT
tristate "Generic DT based cpufreq driver"
depends on HAVE_CLK && OF
select CPUFREQ_DT_PLATDEV
select CPUFREQ_DT_PLATDEV if !ARM_ROCKCHIP_CPUFREQ
select PM_OPP
help
This adds a generic DT based cpufreq driver for frequency management.

4
drivers/cpufreq/rockchip-cpufreq.c
View File

@@ -206,6 +206,9 @@ static int rk3588_get_soc_info(struct device *dev, struct device_node *np,
/* RK3588M */
if (value == 0xd)
*bin = 1;
/* RK3588J */
else if (value == 0xa)
*bin = 2;
}
if (*bin < 0)
*bin = 0;
@@ -213,6 +216,7 @@ static int rk3588_get_soc_info(struct device *dev, struct device_node *np,
return ret;
}
static int rk3588_change_length(struct device *dev, struct device_node *np,
int bin, int process, int volt_sel)
{

5
drivers/devfreq/event/rockchip-dfi.c
View File

@@ -537,7 +537,10 @@ static __maybe_unused __init int rk3588_dfi_init(struct platform_device *pdev,
data->dram_type = READ_DRAMTYPE_INFO(val_2);
data->mon_idx = 0x4000;
data->count_rate = 2;
if (data->dram_type == LPDDR5)
data->count_rate = 1;
else
data->count_rate = 2;
data->dram_dynamic_info_reg = RK3588_PMUGRF_OS_REG(6);
data->ch_msk = READ_CH_INFO(val_2) | READ_CH_INFO(val_4) << 2;
data->clk = NULL;

49
drivers/devfreq/rockchip_bus.c
View File

@@ -73,7 +73,9 @@ static int rockchip_bus_smc_config(struct rockchip_bus *bus)
struct device_node *np = dev->of_node;
struct device_node *child;
unsigned int enable_msk, bus_id, cfg;
int ret;
char *prp_name = "rockchip,soc-bus-table";
u32 *table = NULL;
int ret = 0, config_cnt, i;
for_each_available_child_of_node(np, child) {
ret = of_property_read_u32_index(child, "bus-id", 0,
@@ -108,7 +110,49 @@ static int rockchip_bus_smc_config(struct rockchip_bus *bus)
}
}
return 0;
config_cnt = of_property_count_u32_elems(np, prp_name);
if (config_cnt <= 0) {
return 0;
} else if (config_cnt % 3) {
dev_err(dev, "Invalid count of %s\n", prp_name);
return -EINVAL;
}
table = kmalloc_array(config_cnt, sizeof(u32), GFP_KERNEL);
if (!table)
return -ENOMEM;
ret = of_property_read_u32_array(np, prp_name, table, config_cnt);
if (ret) {
dev_err(dev, "get %s error\n", prp_name);
goto free_table;
}
/* table[3n]: bus_id
* table[3n + 1]: config
* table[3n + 2]: enable_mask
*/
for (i = 0; i < config_cnt; i += 3) {
bus_id = table[i];
cfg = table[i + 1];
enable_msk = table[i + 2];
if (!cfg) {
dev_info(dev, "cfg-val invalid in %s-%d\n", prp_name, bus_id);
continue;
}
ret = rockchip_sip_bus_smc_config(bus_id, cfg, enable_msk);
if (ret) {
dev_err(dev, "bus smc config error: %x!\n", ret);
goto free_table;
}
}
free_table:
kfree(table);
return ret;
}
static int rockchip_bus_set_freq_table(struct rockchip_bus *bus)
@@ -448,6 +492,7 @@ static const struct of_device_id rockchip_busfreq_of_match[] = {
{ .compatible = "rockchip,rk3368-bus", },
{ .compatible = "rockchip,rk3399-bus", },
{ .compatible = "rockchip,rk3568-bus", },
{ .compatible = "rockchip,rk3588-bus", },
{ .compatible = "rockchip,rv1126-bus", },
{ },
};

11
drivers/devfreq/rockchip_dmc.c
View File

@@ -136,6 +136,7 @@ struct rockchip_dmcfreq {
unsigned long video_1080p_rate;
unsigned long video_4k_rate;
unsigned long video_4k_10b_rate;
unsigned long video_4k_60p_rate;
unsigned long video_svep_rate;
unsigned long performance_rate;
unsigned long hdmi_rate;
@@ -2461,6 +2462,11 @@ static int rockchip_get_system_status_level(struct device_node *np,
dev_info(dmcfreq->dev, "video_4k_10b_rate = %ld\n",
dmcfreq->video_4k_10b_rate);
break;
case SYS_STATUS_VIDEO_4K_60P:
dmcfreq->video_4k_60p_rate = rockchip_freq_level_2_rate(dmcfreq, level);
dev_info(dmcfreq->dev, "video_4k_60p_rate = %ld\n",
dmcfreq->video_4k_60p_rate);
break;
case SYS_STATUS_VIDEO_SVEP:
dmcfreq->video_svep_rate = rockchip_freq_level_2_rate(dmcfreq, level);
dev_info(dmcfreq->dev, "video_svep_rate = %ld\n",
@@ -2584,6 +2590,11 @@ static int rockchip_dmcfreq_system_status_notifier(struct notifier_block *nb,
target_rate = dmcfreq->video_4k_10b_rate;
}
if (dmcfreq->video_4k_60p_rate && (status & SYS_STATUS_VIDEO_4K_60P)) {
if (dmcfreq->video_4k_60p_rate > target_rate)
target_rate = dmcfreq->video_4k_60p_rate;
}
if (dmcfreq->video_1080p_rate && (status & SYS_STATUS_VIDEO_1080P)) {
if (dmcfreq->video_1080p_rate > target_rate)
target_rate = dmcfreq->video_1080p_rate;

7
drivers/gpio/Kconfig
View File

@@ -1250,13 +1250,6 @@ config GPIO_MAX77650
GPIO driver for MAX77650/77651 PMIC from Maxim Semiconductor.
These chips have a single pin that can be configured as GPIO.
config GPIO_MAX96752F
tristate "MAX96752F GPIO"
depends on MFD_MAX96752F
help
Select this option to enable GPIO driver for the MAX96752F
chip.
config GPIO_MSIC
bool "Intel MSIC mixed signal gpio support"
depends on (X86 || COMPILE_TEST) && MFD_INTEL_MSIC

1
drivers/gpio/Makefile
View File

@@ -89,7 +89,6 @@ obj-$(CONFIG_GPIO_MAX730X) += gpio-max730x.o
obj-$(CONFIG_GPIO_MAX732X) += gpio-max732x.o
obj-$(CONFIG_GPIO_MAX77620) += gpio-max77620.o
obj-$(CONFIG_GPIO_MAX77650) += gpio-max77650.o
obj-$(CONFIG_GPIO_MAX96752F) += gpio-max96752f.o
obj-$(CONFIG_GPIO_MB86S7X) += gpio-mb86s7x.o
obj-$(CONFIG_GPIO_MC33880) += gpio-mc33880.o
obj-$(CONFIG_GPIO_MC9S08DZ60) += gpio-mc9s08dz60.o

104
drivers/gpio/gpio-max96752f.c
View File

@@ -1,104 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Maxim MAX96752F GPIO driver
*
* Copyright (C) 2022 Rockchip Electronics Co. Ltd.
*/
#include <linux/gpio/driver.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/mfd/max96752f.h>
struct max96752f_gpio {
struct device *dev;
struct regmap *regmap;
struct gpio_chip gpio_chip;
};
static int max96752f_gpio_direction_output(struct gpio_chip *gc,
unsigned int offset, int value)
{
struct max96752f_gpio *gpio = gpiochip_get_data(gc);
regmap_update_bits(gpio->regmap, GPIO_A_REG(offset),
GPIO_OUT_DIS | GPIO_OUT,
FIELD_PREP(GPIO_OUT_DIS, 0) |
FIELD_PREP(GPIO_OUT, value));
return 0;
}
static void max96752f_gpio_set(struct gpio_chip *gc, unsigned int offset,
int value)
{
struct max96752f_gpio *gpio = gpiochip_get_data(gc);
regmap_update_bits(gpio->regmap, GPIO_A_REG(offset), GPIO_OUT,
FIELD_PREP(GPIO_OUT, value));
}
static int max96752f_gpio_get(struct gpio_chip *gc, unsigned int offset)
{
struct max96752f_gpio *gpio = gpiochip_get_data(gc);
unsigned int value;
regmap_read(gpio->regmap, GPIO_A_REG(offset), &value);
return !!FIELD_GET(GPIO_OUT, value);
}
static int max96752f_gpio_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct max96752f_gpio *gpio;
int ret;
gpio = devm_kzalloc(dev, sizeof(*gpio), GFP_KERNEL);
if (!gpio)
return -ENOMEM;
gpio->dev = dev;
platform_set_drvdata(pdev, gpio);
gpio->regmap = dev_get_regmap(dev->parent, NULL);
if (!gpio->regmap)
return dev_err_probe(dev, -ENODEV, "failed to get regmap\n");
gpio->gpio_chip.of_node = dev->of_node;
gpio->gpio_chip.label = dev_name(dev);
gpio->gpio_chip.parent = dev->parent;
gpio->gpio_chip.direction_output = max96752f_gpio_direction_output;
gpio->gpio_chip.set = max96752f_gpio_set;
gpio->gpio_chip.get = max96752f_gpio_get;
gpio->gpio_chip.ngpio = 16;
gpio->gpio_chip.can_sleep = true;
gpio->gpio_chip.base = -1;
ret = devm_gpiochip_add_data(dev, &gpio->gpio_chip, gpio);
if (ret)
return dev_err_probe(dev, ret, "failed to add gpio chip\n");
return 0;
}
static const struct of_device_id max96752f_gpio_of_match[] = {
{ .name = "maxim,max96752f-gpio", },
{}
};
MODULE_DEVICE_TABLE(of, max96752f_gpio_of_match);
static struct platform_driver max96752f_gpio_driver = {
.driver = {
.name = "max96752f-gpio",
.of_match_table = max96752f_gpio_of_match,
},
.probe = max96752f_gpio_probe,
};
module_platform_driver(max96752f_gpio_driver);
MODULE_AUTHOR("Wyon Bi <bivvy.bi@rock-chips.com>");
MODULE_DESCRIPTION("Maxim MAX96752F GPIO driver");
MODULE_LICENSE("GPL");

62
drivers/gpu/arm/bifrost/platform/rk/mali_kbase_config_rk.c
View File

@@ -506,6 +506,66 @@ static void kbase_platform_rk_remove_sysfs_files(struct device *dev)
device_remove_file(dev, &dev_attr_utilisation);
}
static int rk3588_gpu_get_soc_info(struct device *dev, struct device_node *np,
int *bin, int *process)
{
int ret = 0;
u8 value = 0;
if (!bin)
return 0;
if (of_property_match_string(np, "nvmem-cell-names",
"specification_serial_number") >= 0) {
ret = rockchip_nvmem_cell_read_u8(np,
"specification_serial_number",
&value);
if (ret) {
dev_err(dev,
"Failed to get specification_serial_number\n");
return ret;
}
/* RK3588M */
if (value == 0xd)
*bin = 1;
/* RK3588J */
else if (value == 0xa)
*bin = 2;
}
if (*bin < 0)
*bin = 0;
dev_info(dev, "bin=%d\n", *bin);
return ret;
}
static int rk3588_gpu_set_soc_info(struct device *dev, struct device_node *np,
int bin, int process, int volt_sel)
{
struct opp_table *opp_table;
u32 supported_hw[2];
if (volt_sel < 0)
return 0;
if (bin < 0)
bin = 0;
if (!of_property_read_bool(np, "rockchip,supported-hw"))
return 0;
/* SoC Version */
supported_hw[0] = BIT(bin);
/* Speed Grade */
supported_hw[1] = BIT(volt_sel);
opp_table = dev_pm_opp_set_supported_hw(dev, supported_hw, 2);
if (IS_ERR(opp_table)) {
dev_err(dev, "failed to set supported opp\n");
return PTR_ERR(opp_table);
}
return 0;
}
static int rk3588_gpu_set_read_margin(struct device *dev,
struct rockchip_opp_info *opp_info,
u32 rm)
@@ -542,6 +602,8 @@ static int rk3588_gpu_set_read_margin(struct device *dev,
}
static const struct rockchip_opp_data rk3588_gpu_opp_data = {
.get_soc_info = rk3588_gpu_get_soc_info,
.set_soc_info = rk3588_gpu_set_soc_info,
.set_read_margin = rk3588_gpu_set_read_margin,
};

20
drivers/gpu/drm/bridge/Kconfig
View File

@@ -93,17 +93,6 @@ config DRM_MAXIM_MAX96745
help
Driver for Maxim MAX96745 GMSL2 Serializer with eDP1.4a/DP1.4 Input.
config DRM_MAXIM_MAX96752F
tristate "Maxim max96752F GMSL2 Deserializer"
depends on OF
select MFD_MAX96752F
select PINCTRL_MAX96752F
select GPIO_MAX96752F
select DRM_KMS_HELPER
select DRM_PANEL
help
Driver for Maxim MAX96752F GMSL2 Deserializer with Dual LVDS Output.
config DRM_MAXIM_MAX96755F
tristate "Maxim max96755 GMSL2 Serializer"
depends on OF
@@ -114,15 +103,6 @@ config DRM_MAXIM_MAX96755F
help
Driver for Maxim MAX96755F GMSL2 Serializer with MIPI-DSI Input.
config DRM_MAXIM_MAX96776
tristate "Maxim max96776 GMSL2 Deserializer"
depends on OF
select MFD_MAX96776
select DRM_KMS_HELPER
select DRM_PANEL
help
Driver for Maxim MAX96776 GMSL2 Deserializer with eDP Output.
config DRM_MEGACHIPS_STDPXXXX_GE_B850V3_FW
tristate "MegaChips stdp4028-ge-b850v3-fw and stdp2690-ge-b850v3-fw"
depends on OF

3
drivers/gpu/drm/bridge/Makefile
View File

@@ -6,9 +6,7 @@ obj-$(CONFIG_DRM_ITE_IT6161) += ite-it6161.o
obj-$(CONFIG_DRM_LONTIUM_LT9611) += lontium-lt9611.o
obj-$(CONFIG_DRM_LVDS_CODEC) += lvds-codec.o
obj-$(CONFIG_DRM_MAXIM_MAX96745) += maxim-max96745.o
obj-$(CONFIG_DRM_MAXIM_MAX96752F) += maxim-max96752f.o
obj-$(CONFIG_DRM_MAXIM_MAX96755F) += maxim-max96755f.o
obj-$(CONFIG_DRM_MAXIM_MAX96776) += maxim-max96776.o
obj-$(CONFIG_DRM_MEGACHIPS_STDPXXXX_GE_B850V3_FW) += megachips-stdpxxxx-ge-b850v3-fw.o
obj-$(CONFIG_DRM_NXP_PTN3460) += nxp-ptn3460.o
obj-$(CONFIG_DRM_PARADE_PS8622) += parade-ps8622.o
@@ -31,6 +29,7 @@ obj-$(CONFIG_DRM_TI_SN65DSI86) += ti-sn65dsi86.o
obj-$(CONFIG_DRM_TI_TFP410) += ti-tfp410.o
obj-$(CONFIG_DRM_TI_TPD12S015) += ti-tpd12s015.o
obj-$(CONFIG_DRM_NWL_MIPI_DSI) += nwl-dsi.o
obj-y += analogix/
obj-y += cadence/
obj-y += synopsys/

8
drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
View File

@@ -56,8 +56,16 @@ static bool analogix_dp_bandwidth_ok(struct analogix_dp_device *dp,
const struct drm_display_mode *mode,
unsigned int rate, unsigned int lanes)
{
const struct drm_display_info *info;
u32 max_bw, req_bw, bpp = 24;
if (dp->plat_data->skip_connector)
return true;
info = &dp->connector.display_info;
if (info->bpc)
bpp = 3 * info->bpc;
req_bw = mode->clock * bpp / 8;
max_bw = lanes * rate;
if (req_bw > max_bw)

251
drivers/gpu/drm/bridge/maxim-max96752f.c
View File

@@ -1,251 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Maxim MAX96752F GMSL2 Deserializer with Dual LVDS (OLDI) Output
*
* Copyright (c) 2022 Rockchip Electronics Co. Ltd.
*/
#include <drm/drm_atomic_helper.h>
#include <drm/drm_bridge.h>
#include <drm/drm_connector.h>
#include <drm/drm_of.h>
#include <drm/drm_probe_helper.h>
#include <drm/drm_print.h>
#include <drm/drm_panel.h>
#include <linux/platform_device.h>
#include <linux/kernel.h>
#include <linux/delay.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/regmap.h>
#include <linux/mfd/max96752f.h>
struct max96752f_bridge {
struct drm_bridge bridge;
struct drm_bridge *next_bridge;
struct drm_panel *panel;
struct device *dev;
struct max96752f *parent;
struct regmap *regmap;
};
#define to_max96752f_bridge(x) container_of(x, struct max96752f_bridge, x)
static int max96752f_bridge_get_modes(struct drm_bridge *bridge,
struct drm_connector *connector)
{
struct max96752f_bridge *des = to_max96752f_bridge(bridge);
if (des->next_bridge)
return drm_bridge_get_modes(des->next_bridge, connector);
return drm_panel_get_modes(des->panel, connector);
}
static void
max96752f_bridge_atomic_pre_enable(struct drm_bridge *bridge,
struct drm_bridge_state *old_bridge_state)
{
struct max96752f_bridge *des = to_max96752f_bridge(bridge);
struct drm_atomic_state *state = old_bridge_state->base.state;
const struct drm_bridge_state *bridge_state;
bool oldi_format;
max96752f_init(des->parent);
bridge_state = drm_atomic_get_new_bridge_state(state, bridge);
switch (bridge_state->output_bus_cfg.format) {
case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA:
case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG:
oldi_format = 0x0;
break;
case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG:
oldi_format = 0x1;
break;
default:
oldi_format = 0x1;
dev_warn(des->dev,
"unsupported LVDS bus format 0x%04x, using VESA\n",
bridge_state->output_bus_cfg.format);
break;
}
regmap_update_bits(des->regmap, OLDI_REG(1), OLDI_FORMAT,
FIELD_PREP(OLDI_FORMAT, oldi_format));
if (des->panel)
drm_panel_prepare(des->panel);
}
static void
max96752f_bridge_atomic_enable(struct drm_bridge *bridge,
struct drm_bridge_state *old_bridge_state)
{
struct max96752f_bridge *des = to_max96752f_bridge(bridge);
regmap_update_bits(des->regmap, 0x0002, VID_EN,
FIELD_PREP(VID_EN, 1));
if (des->panel)
drm_panel_enable(des->panel);
}
static void
max96752f_bridge_atomic_disable(struct drm_bridge *bridge,
struct drm_bridge_state *old_bridge_state)
{
struct max96752f_bridge *des = to_max96752f_bridge(bridge);
if (des->panel)
drm_panel_disable(des->panel);
regmap_update_bits(des->regmap, 0x0002, VID_EN,
FIELD_PREP(VID_EN, 0));
}
static void
max96752f_bridge_atomic_post_disable(struct drm_bridge *bridge,
struct drm_bridge_state *old_bridge_state)
{
struct max96752f_bridge *des = to_max96752f_bridge(bridge);
if (des->panel)
drm_panel_unprepare(des->panel);
}
static u32 *
max96752f_bridge_atomic_get_output_bus_fmts(struct drm_bridge *bridge,
struct drm_bridge_state *bridge_state,
struct drm_crtc_state *crtc_state,
struct drm_connector_state *conn_state,
unsigned int *num_output_fmts)
{
struct drm_connector *connector = conn_state->connector;
u32 *out_bus_fmts;
out_bus_fmts = kzalloc(sizeof(*out_bus_fmts), GFP_KERNEL);
if (!out_bus_fmts) {
*num_output_fmts = 0;
return NULL;
}
*num_output_fmts = 1;
if (connector->display_info.num_bus_formats && connector->display_info.bus_formats)
out_bus_fmts[0] = connector->display_info.bus_formats[0];
else
out_bus_fmts[0] = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG;
return out_bus_fmts;
}
static bool max96752f_bridge_video_locked(struct max96752f_bridge *des)
{
u32 val;
if (regmap_read(des->regmap, 0x0003, &val))
return false;
if (!FIELD_GET(VIDEO_LOCK, val))
return false;
return true;
}
static int max96752f_bridge_attach(struct drm_bridge *bridge,
enum drm_bridge_attach_flags flags)
{
struct max96752f_bridge *des = to_max96752f_bridge(bridge);
int ret;
ret = drm_of_find_panel_or_bridge(bridge->of_node, 1, -1, &des->panel,
&des->next_bridge);
if (ret)
return ret;
if (max96752f_bridge_video_locked(des)) {
if (des->panel) {
drm_panel_prepare(des->panel);
drm_panel_enable(des->panel);
}
}
if (des->next_bridge)
return drm_bridge_attach(bridge->encoder, des->next_bridge,
bridge, 0);
return 0;
}
static const struct drm_bridge_funcs max96752f_bridge_funcs = {
.attach = max96752f_bridge_attach,
.get_modes = max96752f_bridge_get_modes,
.atomic_pre_enable = max96752f_bridge_atomic_pre_enable,
.atomic_post_disable = max96752f_bridge_atomic_post_disable,
.atomic_enable = max96752f_bridge_atomic_enable,
.atomic_disable = max96752f_bridge_atomic_disable,
.atomic_get_input_bus_fmts = drm_atomic_helper_bridge_propagate_bus_fmt,
.atomic_get_output_bus_fmts = max96752f_bridge_atomic_get_output_bus_fmts,
.atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
.atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
.atomic_reset = drm_atomic_helper_bridge_reset,
};
static int max96752f_bridge_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct max96752f_bridge *des;
des = devm_kzalloc(dev, sizeof(*des), GFP_KERNEL);
if (!des)
return -ENOMEM;
des->dev = dev;
des->parent = dev_get_drvdata(dev->parent);
platform_set_drvdata(pdev, des);
des->regmap = dev_get_regmap(dev->parent, NULL);
if (!des->regmap)
return dev_err_probe(dev, -ENODEV, "failed to get regmap\n");
des->bridge.funcs = &max96752f_bridge_funcs;
des->bridge.of_node = dev->of_node;
des->bridge.ops = DRM_BRIDGE_OP_MODES;
des->bridge.type = DRM_MODE_CONNECTOR_LVDS;
drm_bridge_add(&des->bridge);
return 0;
}
static int max96752f_bridge_remove(struct platform_device *pdev)
{
struct max96752f_bridge *des = platform_get_drvdata(pdev);
drm_bridge_remove(&des->bridge);
return 0;
}
static const struct of_device_id max96752f_bridge_of_match[] = {
{ .compatible = "maxim,max96752f-bridge" },
{}
};
MODULE_DEVICE_TABLE(of, max96752f_bridge_of_match);
static struct platform_driver max96752f_bridge_driver = {
.driver = {
.name = "max96752f-bridge",
.of_match_table = max96752f_bridge_of_match,
},
.probe = max96752f_bridge_probe,
.remove = max96752f_bridge_remove,
};
module_platform_driver(max96752f_bridge_driver);
MODULE_AUTHOR("Wyon Bi <bivvy.bi@rock-chips.com>");
MODULE_DESCRIPTION("Maxim MAX96752F GMSL2 Deserializer with Dual LVDS (OLDI) Output");
MODULE_LICENSE("GPL");

587
drivers/gpu/drm/bridge/maxim-max96776.c
View File

@@ -1,587 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Maxim max96776 GMSL2 Deserializer with eDP Output
*
* Copyright (c) 2022 Rockchip Electronics Co. Ltd.
*/
#include <drm/drm_atomic_helper.h>
#include <drm/drm_bridge.h>
#include <drm/drm_connector.h>
#include <drm/drm_dp_helper.h>
#include <drm/drm_of.h>
#include <drm/drm_probe_helper.h>
#include <drm/drm_print.h>
#include <drm/drm_panel.h>
#include <linux/platform_device.h>
#include <linux/kernel.h>
#include <linux/delay.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/regmap.h>
#include <linux/mfd/max96776.h>
#define AUX_ADDR_7_0(x) (((x) >> 0) & 0xff)
#define AUX_ADDR_15_8(x) (((x) >> 8) & 0xff)
#define AUX_ADDR_19_16(x) (((x) >> 16) & 0x0f)
#define DPCD_MAX_LANE_COUNT(x) ((x) & 0x1f)
enum link_lane_count {
USE_ONE_LINK = 1,
USE_TWO_LINK = 2,
USE_FOUR_LINK = 4
};
enum link_rate {
BW_1_62,
BW_2_7,
BW_5_4,
};
struct max96776_bridge {
struct drm_bridge bridge;
struct drm_bridge *next_bridge;
struct drm_panel *panel;
struct drm_display_mode mode;
struct device *dev;
struct max96776 *parent;
struct regmap *regmap;
struct drm_dp_aux aux;
u8 link_rate;
u8 lane_count;
int max_link_rate;
enum link_lane_count max_lane_count;
};
static const struct reg_sequence max96776_clk_ref[3][14] = {
/* 1.62Gbps */
{
{ 0xe7b2, 0x50 },
{ 0xe7b3, 0x00 },
{ 0xe7b4, 0xcc },
{ 0xe7b5, 0x44 },
{ 0xe7b6, 0x81 },
{ 0xe7b7, 0x30 },
{ 0xe7b8, 0x07 },
{ 0xe7b9, 0x10 },
{ 0xe7ba, 0x01 },
{ 0xe7bb, 0x00 },
{ 0xe7bc, 0x00 },
{ 0xe7bd, 0x00 },
{ 0xe7be, 0x52 },
{ 0xe7bf, 0x00 },
},
/* 2.7Gbps */
{
{ 0xe7b2, 0x50 },
{ 0xe7b3, 0x00 },
{ 0xe7b4, 0x00 },
{ 0xe7b5, 0x40 },
{ 0xe7b6, 0x6c },
{ 0xe7b7, 0x20 },
{ 0xe7b8, 0x07 },
{ 0xe7b9, 0x00 },
{ 0xe7ba, 0x01 },
{ 0xe7bb, 0x00 },
{ 0xe7bc, 0x00 },
{ 0xe7bd, 0x00 },
{ 0xe7be, 0x52 },
{ 0xe7bf, 0x00 },
},
/* 5.4Gbps */
{
{ 0xe7b2, 0x30 },
{ 0xe7b3, 0x00 },
{ 0xe7b4, 0x00 },
{ 0xe7b5, 0x40 },
{ 0xe7b6, 0x6c },
{ 0xe7b7, 0x20 },
{ 0xe7b8, 0x14 },
{ 0xe7b9, 0x00 },
{ 0xe7ba, 0x2e },
{ 0xe7bb, 0x00 },
{ 0xe7bc, 0x00 },
{ 0xe7bd, 0x01 },
{ 0xe7be, 0x32 },
{ 0xe7bf, 0x00 },
},
};
#define to_max96776_bridge(x) container_of(x, struct max96776_bridge, x)
static void
max96776_dp_aux_dpcd_addr_sel(struct max96776_bridge *des, unsigned int addr)
{
u32 reg;
reg = AUX_ADDR_7_0(addr);
regmap_write(des->regmap, 0xe778, FIELD_PREP(USER_DATA1_B0, reg));
reg = AUX_ADDR_15_8(addr);
regmap_write(des->regmap, 0xe779, FIELD_PREP(USER_DATA1_B1, reg));
/*
* Most significant four bits of DPCD register address when performing
* a twenty bit AUX read or write command.
*/
reg = AUX_ADDR_19_16(addr);
regmap_write(des->regmap, 0xe77c, FIELD_PREP(USER_DATA3_B0, reg));
}
static ssize_t max96776_dp_aux_transfer(struct drm_dp_aux *aux,
struct drm_dp_aux_msg *msg)
{
struct max96776_bridge *des = to_max96776_bridge(aux);
int num_transferred = 0;
u8 *buffer = msg->buffer;
u32 reg;
int i;
/*
* as Spec if Burst data transfer is supported,
* The burst data size must be limited to a maximum
* of 16 bytes.
*/
if (WARN_ON(msg->size > 16))
return -E2BIG;
/*
* Write AUX channel
*
* this command writes a DPCD register on the eDP/DP sink device. The register
* address is specified by the user in address 0xe778 and 0xe779. The data (a byte)
* to be written is specified in 0xe77a. The AUX channel must be configured prior to
* using the command(this occurs at power-up). The example below writes DPCD sink
* register 0x0100 with data 0x0a, To issue command, write the following registers:
*
* 1. LSBs of write address: 0xe778 0x00
* 2. MSBs of write address: 0xe779 0x01
* 3. LSBs of data to write: 0xe77a 0x0a
* 4. command select: 0xe776 0x20
* 5. Execute command: 0xe777 0x80
*/
if (!(msg->request & DP_AUX_I2C_READ)) {
for (i = 0; i < msg->size; i++) {
max96776_dp_aux_dpcd_addr_sel(des, msg->address + i);
reg = buffer[i];
regmap_write(des->regmap, 0xe77a,
FIELD_PREP(USER_DATA2_B0, reg));
regmap_update_bits(des->regmap, 0xe776, AUX_WRITE,
FIELD_PREP(AUX_WRITE, 1));
regmap_update_bits(des->regmap, 0xe777, RUN_COMMAND,
FIELD_PREP(RUN_COMMAND, 1));
mdelay(10);
num_transferred++;
}
}
/*
* Read AUX channel
*
* this command read DPCD register on the eDP/DP sink device. The register
* address is specified by the user in address 0xe778 and 0xe779. Once the
* command has executed, the return data (a byte) is stored in 0xe77a. The
* AUX channel must be configured prior to using the command(this occurs
* at power-up). The example, to read DPCD sink register 0x100 (main link
* bandwidth setting), write the following registers:
*
* 1. LSBs of write address: 0xe778 0x00
* 2. MSBs of write address: 0xe779 0x01
* 3. command select: 0xe776 0x10
* 4. Execute command: 0xe777 0x80
* 5. LSBs of return value read: 0xe77a
*/
if (msg->request & DP_AUX_I2C_READ) {
for (i = 0; i < msg->size; i++) {
max96776_dp_aux_dpcd_addr_sel(des, msg->address + i);
regmap_update_bits(des->regmap, 0xe776, AUX_READ,
FIELD_PREP(AUX_READ, 1));
regmap_update_bits(des->regmap, 0xe777, RUN_COMMAND,
FIELD_PREP(RUN_COMMAND, 1));
mdelay(10);
regmap_read(des->regmap, 0xe77a, &reg);
buffer[i] = (u8)reg;
num_transferred++;
}
}
msg->reply = DP_AUX_I2C_REPLY_ACK;
return (num_transferred == msg->size) ? num_transferred : -EBUSY;
}
static int max96776_bridge_get_modes(struct drm_bridge *bridge,
struct drm_connector *connector)
{
struct max96776_bridge *des = to_max96776_bridge(bridge);
if (des->next_bridge)
return drm_bridge_get_modes(des->next_bridge, connector);
if (des->panel)
return drm_panel_get_modes(des->panel, connector);
return drm_add_modes_noedid(connector, 1920, 1080);
}
static void max96776_edp_timing_config(struct max96776_bridge *des)
{
struct drm_display_mode *mode = &des->mode;
u32 hfp, hsa, hbp, hact;
u32 vact, vsa, vfp, vbp;
u64 hwords, mvid, link_rate;
bool hsync_pol, vsync_pol;
vact = mode->vdisplay;
vsa = mode->vsync_end - mode->vsync_start;
vfp = mode->vsync_start - mode->vdisplay;
vbp = mode->vtotal - mode->vsync_end;
hact = mode->hdisplay;
hsa = mode->hsync_end - mode->hsync_start;
hfp = mode->hsync_start - mode->hdisplay;
hbp = mode->htotal - mode->hsync_end;
regmap_write(des->regmap, 0xe794, FIELD_PREP(HRES_B0, hact));
regmap_write(des->regmap, 0xe795, FIELD_PREP(HRES_B1, hact >> 8));
regmap_write(des->regmap, 0xe796, FIELD_PREP(HFP_B0, hfp));
regmap_write(des->regmap, 0xe797, FIELD_PREP(HFP_B1, hfp >> 8));
regmap_write(des->regmap, 0xe798, FIELD_PREP(HSW_B0, hsa));
regmap_write(des->regmap, 0xe799, FIELD_PREP(HSW_B1, hsa >> 8));
regmap_write(des->regmap, 0xe79a, FIELD_PREP(HBP_B0, hbp));
regmap_write(des->regmap, 0xe79b, FIELD_PREP(HBP_B1, hbp >> 8));
regmap_write(des->regmap, 0xe79c, FIELD_PREP(VRES_B0, vact));
regmap_write(des->regmap, 0xe79d, FIELD_PREP(VRES_B1, vact >> 8));
regmap_write(des->regmap, 0xe79e, FIELD_PREP(VFP_B0, vfp));
regmap_write(des->regmap, 0xe79f, FIELD_PREP(VFP_B1, vfp >> 8));
regmap_write(des->regmap, 0xe7a0, FIELD_PREP(VSW_B0, vsa));
regmap_write(des->regmap, 0xe7a1, FIELD_PREP(VSW_B1, vsa >> 8));
regmap_write(des->regmap, 0xe7a2, FIELD_PREP(VBP_B0, vbp));
regmap_write(des->regmap, 0xe7a3, FIELD_PREP(VBP_B1, vbp >> 8));
hsync_pol = !!(mode->flags & DRM_MODE_FLAG_NHSYNC);
vsync_pol = !!(mode->flags & DRM_MODE_FLAG_NVSYNC);
regmap_update_bits(des->regmap, 0xe7ac, HSYNC_POL | VSYNC_POL,
FIELD_PREP(HSYNC_POL, hsync_pol) |
FIELD_PREP(VSYNC_POL, vsync_pol));
/* NVID should always be set to 0x8000 */
regmap_write(des->regmap, 0xe7a8, FIELD_PREP(NVID_B0, 0));
regmap_write(des->regmap, 0xe7a9, FIELD_PREP(NVID_B1, 0x80));
/* HWORDS = ((HRES x bits/pixel)/16) - LANE_COUNT */
hwords = DIV_ROUND_CLOSEST_ULL(hact * 24, 16) - des->lane_count;
regmap_write(des->regmap, 0xe7a4, FIELD_PREP(HWORDS_B0, hwords));
regmap_write(des->regmap, 0xe7a5, FIELD_PREP(HWORDS_B1, hwords >> 8));
/* MVID = (PCLK x NVID) x 10 / Link Rate */
link_rate = drm_dp_bw_code_to_link_rate(des->link_rate);
mvid = DIV_ROUND_CLOSEST_ULL((u64)mode->clock * 32768, link_rate);
regmap_write(des->regmap, 0xe7a6, FIELD_PREP(HWORDS_B0, mvid));
regmap_write(des->regmap, 0xe7a7, FIELD_PREP(HWORDS_B1, mvid >> 8));
regmap_write(des->regmap, 0xe7aa, FIELD_PREP(TUC_VALUE_B0, 0x40));
regmap_write(des->regmap, 0xe7ab, FIELD_PREP(TUC_VALUE_B1, 0));
}
static void max96776_get_edp_sink_max_lane_count(struct max96776_bridge *des)
{
u8 data;
/*
* For DP rev.1.1, Maximum number of Main Link lanes
* 0x01 = 1 lane, 0x02 = 2 lanes, 0x04 = 4 lanes
*/
drm_dp_dpcd_readb(&des->aux, DP_MAX_LANE_COUNT, &data);
des->lane_count = DPCD_MAX_LANE_COUNT(data);
}
static void max96776_get_edp_sink_max_bw(struct max96776_bridge *des)
{
u8 data;
/*
* For DP rev.1.1, Maximum link rate of Main Link lanes
* 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps
* For DP rev.1.2, Maximum link rate of Main Link lanes
* 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps, 0x14 = 5.4Gbps
* For DP rev.1.4, Maximum link rate of Main Link lanes
* 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps, 0x14 = 5.4Gbps 0x1e = 8.1 Gbps
*/
drm_dp_dpcd_readb(&des->aux, DP_MAX_LINK_RATE, &data);
des->link_rate = data;
}
static void max96776_edp_link_config(struct max96776_bridge *des)
{
max96776_get_edp_sink_max_bw(des);
max96776_get_edp_sink_max_lane_count(des);
if ((des->link_rate != DP_LINK_BW_1_62) &&
(des->link_rate != DP_LINK_BW_2_7) &&
(des->link_rate != DP_LINK_BW_5_4) &&
(des->link_rate != DP_LINK_BW_8_1)) {
dev_err(des->dev, "Rx Max Link Rate is abnormal :%x !\n",
des->link_rate);
des->link_rate = DP_LINK_BW_1_62;
}
if (des->lane_count == 0) {
dev_err(des->dev, "Rx Max Lane count is abnormal :%x !\n",
des->lane_count);
des->lane_count = (u8)USE_ONE_LINK;
}
/* Setup TX lane count & rate */
if (des->lane_count > (u8)des->max_lane_count)
des->lane_count = (u8)des->max_lane_count;
if (des->link_rate > des->max_link_rate)
des->link_rate = des->max_link_rate;
regmap_write(des->regmap, 0xe790, FIELD_PREP(LINK_RATE, des->link_rate));
regmap_write(des->regmap, 0xe792, FIELD_PREP(LANE_COUNT, des->lane_count));
dev_info(des->dev, "final bandwidth: 0x%02x, lane count: 0x%02x\n",
des->link_rate, des->lane_count);
}
static void max96776_edp_pll_config(struct max96776_bridge *des)
{
/* provides control for eDP PLL */
switch (des->link_rate) {
case DP_LINK_BW_5_4:
regmap_multi_reg_write(des->regmap, max96776_clk_ref[BW_5_4],
ARRAY_SIZE(max96776_clk_ref[BW_5_4]));
break;
case DP_LINK_BW_2_7:
regmap_multi_reg_write(des->regmap, max96776_clk_ref[BW_2_7],
ARRAY_SIZE(max96776_clk_ref[BW_2_7]));
break;
case DP_LINK_BW_1_62:
default:
regmap_multi_reg_write(des->regmap, max96776_clk_ref[BW_1_62],
ARRAY_SIZE(max96776_clk_ref[BW_1_62]));
break;
}
}
static void max96776_edp_full_training(struct max96776_bridge *des)
{
u8 status[2];
u32 sts;
int ret;
regmap_update_bits(des->regmap, 0xe776, RUN_LINK_TRAINING,
FIELD_PREP(RUN_LINK_TRAINING, 0x1));
regmap_update_bits(des->regmap, 0xe777, RUN_COMMAND,
FIELD_PREP(RUN_COMMAND, 0x1));
ret = regmap_read_poll_timeout(des->regmap, 0x07f0, sts,
FIELD_PREP(TRAINING_SUCCESSFUL, sts),
MSEC_PER_SEC, 200 * MSEC_PER_SEC);
if (ret < 0)
dev_err(des->dev, "Link Training not successful\n");
drm_dp_dpcd_read(&des->aux, DP_LANE0_1_STATUS, status, 2);
dev_info(des->dev, "SINK LANE0_1_STATUS:0x%02x LANE2_3_STATUS:0x%02x\n",
status[0], status[1]);
}
static void
max96776_bridge_atomic_pre_enable(struct drm_bridge *bridge,
struct drm_bridge_state *old_bridge_state)
{
struct max96776_bridge *des = to_max96776_bridge(bridge);
u8 dpcd;
/* disable HDCP 2.2 on eDP Deserializer */
regmap_update_bits(des->regmap, 0x1700, CMD_RESET,
FIELD_PREP(CMD_RESET, 0x01));
/*
* This bit must be set to allow waiting for the
* CMU to lock. It also should be set when using
* SSC. Otherwise, a fixed wait time of 20μS is
* used.
*/
regmap_update_bits(des->regmap, 0xe7b0, SS_ENABLE,
FIELD_PREP(SS_ENABLE, 0x01));
/*
* Determines whether spread spectrum clocking (SSC)
* is used with the DP sink device.
*/
drm_dp_dpcd_readb(&des->aux, DP_MAX_DOWNSPREAD, &dpcd);
if (!!(dpcd & DP_MAX_DOWNSPREAD_0_5))
regmap_update_bits(des->regmap, 0xe7b1, SSC_ENABLE,
FIELD_PREP(SSC_ENABLE, 0x01));
max96776_edp_link_config(des);
max96776_edp_pll_config(des);
max96776_edp_timing_config(des);
if (des->panel)
drm_panel_prepare(des->panel);
}
static void
max96776_bridge_atomic_enable(struct drm_bridge *bridge,
struct drm_bridge_state *old_bridge_state)
{
struct max96776_bridge *des = to_max96776_bridge(bridge);
max96776_edp_full_training(des);
if (des->panel)
drm_panel_enable(des->panel);
}
static void
max96776_bridge_atomic_disable(struct drm_bridge *bridge,
struct drm_bridge_state *old_bridge_state)
{
struct max96776_bridge *des = to_max96776_bridge(bridge);
if (des->panel)
drm_panel_disable(des->panel);
}
static void
max96776_bridge_atomic_post_disable(struct drm_bridge *bridge,
struct drm_bridge_state *old_bridge_state)
{
struct max96776_bridge *des = to_max96776_bridge(bridge);
if (des->panel)
drm_panel_unprepare(des->panel);
}
static int max96776_bridge_attach(struct drm_bridge *bridge,
enum drm_bridge_attach_flags flags)
{
struct max96776_bridge *des = to_max96776_bridge(bridge);
int ret;
ret = drm_of_find_panel_or_bridge(bridge->of_node, 1, -1, &des->panel,
&des->next_bridge);
if (ret < 0 && ret != -ENODEV)
return ret;
if (des->next_bridge)
return drm_bridge_attach(bridge->encoder, des->next_bridge,
bridge, 0);
return 0;
}
static void max96776_bridge_mode_set(struct drm_bridge *bridge,
const struct drm_display_mode *mode,
const struct drm_display_mode *adj_mode)
{
struct max96776_bridge *des = to_max96776_bridge(bridge);
drm_mode_copy(&des->mode, adj_mode);
}
static enum drm_connector_status
max96776_bridge_detect(struct drm_bridge *bridge)
{
struct max96776_bridge *des = to_max96776_bridge(bridge);
u32 hpd;
if (regmap_read(des->regmap, 0x6230, &hpd))
return connector_status_disconnected;
if (!FIELD_PREP(HPD_PRESENT, hpd))
return connector_status_disconnected;
return connector_status_connected;
}
static const struct drm_bridge_funcs max96776_bridge_funcs = {
.attach = max96776_bridge_attach,
.detect = max96776_bridge_detect,
.get_modes = max96776_bridge_get_modes,
.atomic_pre_enable = max96776_bridge_atomic_pre_enable,
.atomic_post_disable = max96776_bridge_atomic_post_disable,
.atomic_enable = max96776_bridge_atomic_enable,
.atomic_disable = max96776_bridge_atomic_disable,
.atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
.atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
.atomic_reset = drm_atomic_helper_bridge_reset,
.mode_set = max96776_bridge_mode_set,
};
static int max96776_bridge_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct max96776_bridge *des;
int ret;
des = devm_kzalloc(dev, sizeof(*des), GFP_KERNEL);
if (!des)
return -ENOMEM;
des->dev = dev;
des->parent = dev_get_drvdata(dev->parent);
platform_set_drvdata(pdev, des);
des->regmap = dev_get_regmap(dev->parent, NULL);
if (!des->regmap)
return dev_err_probe(dev, -ENODEV, "failed to get regmap\n");
des->max_link_rate = DP_LINK_BW_5_4;
des->max_lane_count = USE_FOUR_LINK;
des->aux.name = "DP-AUX";
des->aux.transfer = max96776_dp_aux_transfer;
des->aux.dev = des->dev;
ret = drm_dp_aux_register(&des->aux);
if (ret) {
dev_err(dev, "failed to register dp aux\n");
return ret;
}
des->bridge.funcs = &max96776_bridge_funcs;
des->bridge.of_node = dev->of_node;
des->bridge.ops = DRM_BRIDGE_OP_MODES | DRM_BRIDGE_OP_DETECT;
des->bridge.type = DRM_MODE_CONNECTOR_eDP;
drm_bridge_add(&des->bridge);
return 0;
}
static int max96776_bridge_remove(struct platform_device *pdev)
{
struct max96776_bridge *des = platform_get_drvdata(pdev);
drm_bridge_remove(&des->bridge);
return 0;
}
static const struct of_device_id max96776_bridge_of_match[] = {
{ .compatible = "maxim,max96776-bridge" },
{}
};
MODULE_DEVICE_TABLE(of, max96776_bridge_of_match);
static struct platform_driver max96776_bridge_driver = {
.driver = {
.name = "max96776-bridge",
.of_match_table = max96776_bridge_of_match,
},
.probe = max96776_bridge_probe,
.remove = max96776_bridge_remove,
};
module_platform_driver(max96776_bridge_driver);
MODULE_AUTHOR("Guochun Huang <hero.huang@rock-chips.com>");
MODULE_DESCRIPTION("Maxim max96776 GMSL2 Deserializer with eDP Output");
MODULE_LICENSE("GPL");

7
drivers/gpu/drm/rockchip/Kconfig
View File

@@ -82,6 +82,13 @@ config ROCKCHIP_CDN_DP
RK3399 based SoC, you should select this
option.
config ROCKCHIP_DRM_TVE
bool "Rockchip TVE support"
depends on DRM_ROCKCHIP
help
Choose this option to enable support for Rockchip TVE controllers.
say Y to enable its driver.
config ROCKCHIP_DW_HDMI
bool "Rockchip specific extensions for Synopsys DW HDMI"
help

1
drivers/gpu/drm/rockchip/Makefile
View File

@@ -17,6 +17,7 @@ rockchipdrm-$(CONFIG_ROCKCHIP_DRM_SELF_TEST) += rockchip_drm_display_pattern.o \
rockchipdrm-$(CONFIG_ROCKCHIP_ANALOGIX_DP) += analogix_dp-rockchip.o
rockchipdrm-$(CONFIG_ROCKCHIP_CDN_DP) += cdn-dp-core.o cdn-dp-reg.o
rockchipdrm-$(CONFIG_ROCKCHIP_DRM_TVE) += rockchip_drm_tve.o
rockchipdrm-$(CONFIG_ROCKCHIP_DW_HDMI) += dw_hdmi-rockchip.o
rockchipdrm-$(CONFIG_ROCKCHIP_DW_MIPI_DSI) += dw-mipi-dsi-rockchip.o \
dw-mipi-dsi2-rockchip.o

25
drivers/gpu/drm/rockchip/dw-dp.c
View File

@@ -1854,6 +1854,26 @@ static void dw_dp_encoder_disable(struct drm_encoder *encoder)
s->output_if &= ~(dp->id ? VOP_OUTPUT_IF_DP1 : VOP_OUTPUT_IF_DP0);
}
static void dw_dp_mode_fixup(struct dw_dp *dp, struct drm_display_mode *adjusted_mode)
{
int min_hbp = 16;
int min_hsync = 9;
if (dp->split_mode) {
min_hbp *= 2;
min_hsync *= 2;
}
if (adjusted_mode->hsync_end - adjusted_mode->hsync_start < min_hsync) {
adjusted_mode->hsync_end = adjusted_mode->hsync_start + min_hsync;
dev_warn(dp->dev, "hsync is too narrow, fixup to min hsync:%d\n", min_hsync);
}
if (adjusted_mode->htotal - adjusted_mode->hsync_end < min_hbp) {
adjusted_mode->htotal = adjusted_mode->hsync_end + min_hbp;
dev_warn(dp->dev, "hbp is too narrow, fixup to min hbp:%d\n", min_hbp);
}
}
static int dw_dp_encoder_atomic_check(struct drm_encoder *encoder,
struct drm_crtc_state *crtc_state,
struct drm_connector_state *conn_state)
@@ -1892,6 +1912,8 @@ static int dw_dp_encoder_atomic_check(struct drm_encoder *encoder,
s->eotf = HDMI_EOTF_TRADITIONAL_GAMMA_SDR;
s->color_space = V4L2_COLORSPACE_DEFAULT;
dw_dp_mode_fixup(dp, &crtc_state->adjusted_mode);
return 0;
}
@@ -2032,9 +2054,6 @@ static int dw_dp_bridge_mode_valid(struct drm_bridge *bridge,
if (dp->split_mode)
drm_mode_convert_to_origin_mode(&m);
if (m.hsync_end - m.hsync_start <= 8)
return MODE_HSYNC_NARROW;
if (info->color_formats & DRM_COLOR_FORMAT_YCRCB420 &&
link->vsc_sdp_extension_for_colorimetry_supported &&
(drm_mode_is_420_only(info, &m) || drm_mode_is_420_also(info, &m)))

39
drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c
View File

@@ -296,6 +296,7 @@ struct dw_mipi_dsi_rockchip {
int devcnt;
struct rockchip_drm_sub_dev sub_dev;
struct drm_panel *panel;
struct drm_bridge *bridge;
};
struct dphy_pll_parameter_map {
@@ -974,6 +975,13 @@ static int dw_mipi_dsi_rockchip_bind(struct device *dev,
struct device *second;
int ret;
ret = drm_of_find_panel_or_bridge(dsi->dev->of_node, 1, 0,
&dsi->panel, &dsi->bridge);
if (ret) {
dev_err(dsi->dev, "failed to find panel or bridge: %d\n", ret);
return ret;
}
second = dw_mipi_dsi_rockchip_find_second(dsi);
if (IS_ERR(second))
return PTR_ERR(second);
@@ -1012,12 +1020,8 @@ static int dw_mipi_dsi_rockchip_bind(struct device *dev,
return ret;
}
ret = drm_of_find_panel_or_bridge(dsi->dev->of_node, 1, 0,
&dsi->panel, NULL);
if (ret)
dev_err(dsi->dev, "failed to find panel\n");
dw_mipi_dsi_get_dsc_info_from_sink(dsi, dsi->panel, NULL);
if (dsi->panel)
dw_mipi_dsi_get_dsc_info_from_sink(dsi, dsi->panel, NULL);
dsi->sub_dev.connector = dw_mipi_dsi_get_connector(dsi->dmd);
if (dsi->sub_dev.connector) {
@@ -1051,10 +1055,8 @@ static const struct component_ops dw_mipi_dsi_rockchip_ops = {
.unbind = dw_mipi_dsi_rockchip_unbind,
};
static int dw_mipi_dsi_rockchip_host_attach(void *priv_data,
struct mipi_dsi_device *device)
static int dw_mipi_dsi_rockchip_component_add(struct dw_mipi_dsi_rockchip *dsi)
{
struct dw_mipi_dsi_rockchip *dsi = priv_data;
struct device *second;
int ret;
@@ -1081,10 +1083,8 @@ static int dw_mipi_dsi_rockchip_host_attach(void *priv_data,
return 0;
}
static int dw_mipi_dsi_rockchip_host_detach(void *priv_data,
struct mipi_dsi_device *device)
static int dw_mipi_dsi_rockchip_component_del(struct dw_mipi_dsi_rockchip *dsi)
{
struct dw_mipi_dsi_rockchip *dsi = priv_data;
struct device *second;
second = dw_mipi_dsi_rockchip_find_second(dsi);
@@ -1096,11 +1096,6 @@ static int dw_mipi_dsi_rockchip_host_detach(void *priv_data,
return 0;
}
static const struct dw_mipi_dsi_host_ops dw_mipi_dsi_rockchip_host_ops = {
.attach = dw_mipi_dsi_rockchip_host_attach,
.detach = dw_mipi_dsi_rockchip_host_detach,
};
static int dw_mipi_dsi_rockchip_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
@@ -1208,7 +1203,6 @@ static int dw_mipi_dsi_rockchip_probe(struct platform_device *pdev)
dsi->pdata.base = dsi->base;
dsi->pdata.max_data_lanes = dsi->cdata->max_data_lanes;
dsi->pdata.phy_ops = &dw_mipi_dsi_rockchip_phy_ops;
dsi->pdata.host_ops = &dw_mipi_dsi_rockchip_host_ops;
dsi->pdata.priv_data = dsi;
platform_set_drvdata(pdev, dsi);
@@ -1221,6 +1215,12 @@ static int dw_mipi_dsi_rockchip_probe(struct platform_device *pdev)
goto err_clkdisable;
}
ret = dw_mipi_dsi_rockchip_component_add(dsi);
if (ret < 0) {
dw_mipi_dsi_remove(dsi->dmd);
goto err_clkdisable;
}
return 0;
err_clkdisable:
@@ -1232,9 +1232,8 @@ static int dw_mipi_dsi_rockchip_remove(struct platform_device *pdev)
{
struct dw_mipi_dsi_rockchip *dsi = platform_get_drvdata(pdev);
if (dsi->devcnt == 0)
component_del(dsi->dev, &dw_mipi_dsi_rockchip_ops);
dw_mipi_dsi_rockchip_component_del(dsi);
dw_mipi_dsi_remove(dsi->dmd);
return 0;

50
drivers/gpu/drm/rockchip/rockchip_drm_drv.c
View File

@@ -53,6 +53,36 @@ static bool iommu_reserve_map;
static struct drm_driver rockchip_drm_driver;
static unsigned int drm_debug;
module_param_named(debug, drm_debug, int, 0600);
static inline bool rockchip_drm_debug_enabled(enum rockchip_drm_debug_category category)
{
return unlikely(drm_debug & category);
}
__printf(3, 4)
void rockchip_drm_dbg(const struct device *dev, enum rockchip_drm_debug_category category,
const char *format, ...)
{
struct va_format vaf;
va_list args;
if (!rockchip_drm_debug_enabled(category))
return;
va_start(args, format);
vaf.fmt = format;
vaf.va = &args;
if (dev)
dev_printk(KERN_DEBUG, dev, "%pV", &vaf);
else
printk(KERN_DEBUG "%pV", &vaf);
va_end(args);
}
/**
* rockchip_drm_wait_vact_end
* @crtc: CRTC to enable line flag
@@ -1025,10 +1055,19 @@ static int rockchip_drm_init_iommu(struct drm_device *drm_dev)
drm_dev);
if (iommu_reserve_map) {
ret = iommu_map(private->domain, 0, 0, (size_t)SZ_4G,
/*
* At 32 bit platform size_t maximum value is 0xffffffff, SZ_4G(0x100000000) will be
* cliped to 0, so we split into two mapping
*/
ret = iommu_map(private->domain, 0, 0, (size_t)SZ_2G,
IOMMU_WRITE | IOMMU_READ | IOMMU_PRIV);
if (ret)
dev_err(drm_dev->dev, "failed to create pre mapping\n");
dev_err(drm_dev->dev, "failed to create 0-2G pre mapping\n");
ret = iommu_map(private->domain, SZ_2G, SZ_2G, (size_t)SZ_2G,
IOMMU_WRITE | IOMMU_READ | IOMMU_PRIV);
if (ret)
dev_err(drm_dev->dev, "failed to create 2G-4G pre mapping\n");
}
return ret;
@@ -1041,8 +1080,10 @@ static void rockchip_iommu_cleanup(struct drm_device *drm_dev)
if (!is_support_iommu)
return;
if (iommu_reserve_map)
iommu_unmap(private->domain, 0, (size_t)SZ_4G);
if (iommu_reserve_map) {
iommu_unmap(private->domain, 0, (size_t)SZ_2G);
iommu_unmap(private->domain, SZ_2G, (size_t)SZ_2G);
}
drm_mm_takedown(&private->mm);
iommu_domain_free(private->domain);
}
@@ -1947,6 +1988,7 @@ static int __init rockchip_drm_init(void)
ADD_ROCKCHIP_SUB_DRIVER(rk3066_hdmi_driver,
CONFIG_ROCKCHIP_RK3066_HDMI);
ADD_ROCKCHIP_SUB_DRIVER(rockchip_rgb_driver, CONFIG_ROCKCHIP_RGB);
ADD_ROCKCHIP_SUB_DRIVER(rockchip_tve_driver, CONFIG_ROCKCHIP_DRM_TVE);
ADD_ROCKCHIP_SUB_DRIVER(dw_dp_driver, CONFIG_ROCKCHIP_DW_DP);
#endif

12
drivers/gpu/drm/rockchip/rockchip_drm_drv.h
View File

@@ -64,6 +64,14 @@ struct iommu_domain;
#define RK_IF_PROP_COLOR_DEPTH_CAPS "color_depth_caps"
#define RK_IF_PROP_COLOR_FORMAT_CAPS "color_format_caps"
enum rockchip_drm_debug_category {
VOP_DEBUG_PLANE = BIT(0),
VOP_DEBUG_OVERLAY = BIT(1),
VOP_DEBUG_WB = BIT(2),
VOP_DEBUG_CFG_DONE = BIT(3),
VOP_DEBUG_VSYNC = BIT(7),
};
enum rk_if_color_depth {
RK_IF_DEPTH_8,
RK_IF_DEPTH_10,
@@ -490,6 +498,9 @@ int rockchip_drm_parse_cea_ext(struct rockchip_drm_dsc_cap *dsc_cap,
const struct edid *edid);
int rockchip_drm_parse_next_hdr(struct next_hdr_sink_data *sink_data,
const struct edid *edid);
__printf(3, 4)
void rockchip_drm_dbg(const struct device *dev, enum rockchip_drm_debug_category category,
const char *format, ...);
extern struct platform_driver cdn_dp_driver;
extern struct platform_driver dw_hdmi_rockchip_pltfm_driver;
@@ -502,6 +513,7 @@ extern struct platform_driver vop_platform_driver;
extern struct platform_driver vop2_platform_driver;
extern struct platform_driver rk3066_hdmi_driver;
extern struct platform_driver rockchip_rgb_driver;
extern struct platform_driver rockchip_tve_driver;
extern struct platform_driver dw_dp_driver;
extern struct platform_driver vconn_platform_driver;
extern struct platform_driver vvop_platform_driver;

21
drivers/gpu/drm/rockchip/rockchip_drm_logo.c
View File

@@ -148,17 +148,19 @@ static int rockchip_drm_reserve_vm(struct drm_device *drm, struct drm_mm *mm,
}
static unsigned long
rockchip_drm_free_reserved_area(void *start, void *end, int poison, const char *s)
rockchip_drm_free_reserved_area(phys_addr_t start, phys_addr_t end, int poison, const char *s)
{
void *pos;
unsigned long pages = 0;
start = (void *)PAGE_ALIGN((unsigned long)start);
end = (void *)((unsigned long)end & PAGE_MASK);
for (pos = start; pos < end; pos += PAGE_SIZE, pages++) {
struct page *page = virt_to_page(pos);
start = ALIGN_DOWN(start, PAGE_SIZE);
end = PAGE_ALIGN(end);
for (; start < end; start += PAGE_SIZE) {
struct page *page = phys_to_page(start);
void *direct_map_addr;
if (!pfn_valid(__phys_to_pfn(start)))
continue;
/*
* 'direct_map_addr' might be different from 'pos'
* because some architectures' virt_to_page()
@@ -176,6 +178,7 @@ rockchip_drm_free_reserved_area(void *start, void *end, int poison, const char *
memset(direct_map_addr, poison, PAGE_SIZE);
free_reserved_page(page);
pages++;
}
if (pages && s)
@@ -188,14 +191,11 @@ void rockchip_free_loader_memory(struct drm_device *drm)
{
struct rockchip_drm_private *private = drm->dev_private;
struct rockchip_logo *logo;
void *start, *end;
if (!private || !private->logo || --private->logo->count)
return;
logo = private->logo;
start = phys_to_virt(logo->dma_addr);
end = phys_to_virt(logo->dma_addr + logo->size);
if (private->domain) {
u32 pg_size = 1UL << __ffs(private->domain->pgsize_bitmap);
@@ -205,7 +205,8 @@ void rockchip_free_loader_memory(struct drm_device *drm)
}
memblock_free(logo->start, logo->size);
rockchip_drm_free_reserved_area(start, end, -1, "drm_logo");
rockchip_drm_free_reserved_area(logo->dma_addr, logo->dma_addr + logo->size,
-1, "drm_logo");
kfree(logo);
private->logo = NULL;
private->loader_protect = false;

204
drivers/gpu/drm/rockchip/rockchip_drm_tve.c
View File

@@ -1,17 +1,20 @@
/* SPDX-License-Identifier: GPL-2.0 */
#include <linux/module.h>
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/hdmi.h>
#include <linux/mutex.h>
#include <linux/mfd/syscon.h>
#include <linux/nvmem-consumer.h>
#include <linux/of_device.h>
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
#include <drm/drmP.h>
#include <drm/drm_atomic_helper.h>
#include <drm/drm_crtc_helper.h>
#include <drm/drm_of.h>
#include <drm/drm_probe_helper.h>
#include <uapi/linux/videodev2.h>
@@ -26,23 +29,31 @@ static const struct drm_display_mode cvbs_mode[] = {
816, 864, 0, 576, 580, 586, 625, 0,
DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
.vrefresh = 50, 0, },
0, },
{ DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 753,
815, 858, 0, 480, 480, 486, 525, 0,
DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
.vrefresh = 60, 0, },
0, },
};
#define tve_writel(offset, v) writel_relaxed(v, tve->regbase + (offset))
#define tve_readl(offset) readl_relaxed(tve->regbase + (offset))
#define tve_writel(offset, v) writel_relaxed(v, tve->regbase + (offset))
#define tve_readl(offset) readl_relaxed(tve->regbase + (offset))
#define tve_dac_writel(offset, v) writel_relaxed(v, tve->vdacbase + (offset))
#define tve_dac_readl(offset) readl_relaxed(tve->vdacbase + (offset))
#define tve_dac_writel(offset, v) writel_relaxed(v, tve->vdacbase + (offset))
#define tve_dac_readl(offset) readl_relaxed(tve->vdacbase + (offset))
#define connector_to_tve(x) container_of(x, struct rockchip_tve, connector)
#define encoder_to_tve(x) container_of(x, struct rockchip_tve, encoder)
#define tve_dac_grf_writel(offset, v) regmap_write(tve->dac_grf, offset, v)
#define tve_dac_grf_readl(offset, v) regmap_read(tve->dac_grf, offset, v)
#define connector_to_tve(x) container_of(x, struct rockchip_tve, connector)
#define encoder_to_tve(x) container_of(x, struct rockchip_tve, encoder)
struct rockchip_tve_data {
int input_format;
int soc_type;
};
static int
rockchip_tve_get_modes(struct drm_connector *connector)
@@ -99,7 +110,7 @@ static void tve_set_mode(struct rockchip_tve *tve)
int mode = tve->tv_format;
dev_dbg(tve->dev, "tve set mode:%d\n", mode);
if (tve->inputformat == INPUT_FORMAT_RGB)
if (tve->input_format == INPUT_FORMAT_RGB)
tve_writel(TV_CTRL, v_CVBS_MODE(mode) | v_CLK_UPSTREAM_EN(2) |
v_TIMING_EN(2) | v_LUMA_FILTER_GAIN(0) |
v_LUMA_FILTER_UPSAMPLE(1) | v_CSC_PATH(0));
@@ -164,17 +175,38 @@ static void dac_init(struct rockchip_tve *tve)
static void dac_enable(struct rockchip_tve *tve, bool enable)
{
u32 val;
u32 mask = 0;
u32 val = 0;
u32 grfreg = 0;
if (enable) {
dev_dbg(tve->dev, "dac enable\n");
val = 0x70;
mask = m_VBG_EN | m_DAC_EN | m_DAC_GAIN;
if (tve->soc_type == SOC_RK3036) {
val = m_VBG_EN | m_DAC_EN | v_DAC_GAIN(tve->daclevel);
grfreg = RK3036_GRF_SOC_CON3;
} else if (tve->soc_type == SOC_RK312X) {
val = m_VBG_EN | m_DAC_EN | v_DAC_GAIN(tve->daclevel);
grfreg = RK312X_GRF_TVE_CON;
} else if (tve->soc_type == SOC_RK322X || tve->soc_type == SOC_RK3328) {
val = v_CUR_REG(tve->dac1level) | v_DR_PWR_DOWN(0) | v_BG_PWR_DOWN(0);
}
} else {
dev_dbg(tve->dev, "dac disable\n");
val = v_CUR_REG(0x7) | m_DR_PWR_DOWN | m_BG_PWR_DOWN;
mask = m_VBG_EN | m_DAC_EN;
if (tve->soc_type == SOC_RK312X)
grfreg = RK312X_GRF_TVE_CON;
else if (tve->soc_type == SOC_RK3036)
grfreg = RK3036_GRF_SOC_CON3;
else if (tve->soc_type == SOC_RK322X || tve->soc_type == SOC_RK3328)
val = v_CUR_REG(tve->dac1level) | m_DR_PWR_DOWN | m_BG_PWR_DOWN;
}
if (tve->vdacbase)
if (grfreg)
tve_dac_grf_writel(grfreg, (mask << 16) | val);
else if (tve->vdacbase)
tve_dac_writel(VDAC_VDAC1, val);
}
@@ -375,33 +407,37 @@ static int tve_parse_dt(struct device_node *np,
return -EINVAL;
} else {
tve->daclevel = val;
cell = nvmem_cell_get(tve->dev, "tve_dac_adj");
if (IS_ERR(cell)) {
dev_dbg(tve->dev,
"failed to get id cell: %ld\n", PTR_ERR(cell));
} else {
efuse_buf = nvmem_cell_read(cell, &len);
nvmem_cell_put(cell);
if (len == 1)
getdac = efuse_buf[0];
kfree(efuse_buf);
if (tve->soc_type == SOC_RK322X || tve->soc_type == SOC_RK3328) {
cell = nvmem_cell_get(tve->dev, "tve_dac_adj");
if (IS_ERR(cell)) {
dev_dbg(tve->dev, "failed to get id cell: %ld\n", PTR_ERR(cell));
} else {
efuse_buf = nvmem_cell_read(cell, &len);
nvmem_cell_put(cell);
if (IS_ERR(efuse_buf))
return PTR_ERR(efuse_buf);
if (len == 1)
getdac = efuse_buf[0];
kfree(efuse_buf);
if (getdac > 0) {
tve->daclevel =
getdac + 5 + val - RK322X_VDAC_STANDARD;
if (tve->daclevel > 0x3f) {
dev_err(tve->dev,
"rk322x daclevel error!\n");
tve->daclevel = val;
if (getdac > 0) {
tve->daclevel = getdac + 5 + val - RK322X_VDAC_STANDARD;
if (tve->daclevel > 0x3f) {
dev_err(tve->dev, "rk322x daclevel error!\n");
tve->daclevel = val;
}
}
}
}
}
ret = of_property_read_u32(np, "rockchip,dac1level", &val);
if ((val == 0) || (ret < 0))
return -EINVAL;
tve->dac1level = val;
if (tve->soc_type == SOC_RK322X || tve->soc_type == SOC_RK3328) {
ret = of_property_read_u32(np, "rockchip,dac1level", &val);
if ((val == 0) || (ret < 0))
return -EINVAL;
tve->dac1level = val;
}
return 0;
}
@@ -410,11 +446,13 @@ static void check_uboot_logo(struct rockchip_tve *tve)
{
int lumafilter0, lumafilter1, lumafilter2, vdac;
vdac = tve_dac_readl(VDAC_VDAC1);
/* Whether the dac power has been turned down. */
if (vdac & m_DR_PWR_DOWN) {
tve->connector.dpms = DRM_MODE_DPMS_OFF;
return;
if (tve->soc_type == SOC_RK322X || tve->soc_type == SOC_RK3328) {
vdac = tve_dac_readl(VDAC_VDAC1);
/* Whether the dac power has been turned down. */
if (vdac & m_DR_PWR_DOWN) {
tve->connector.dpms = DRM_MODE_DPMS_OFF;
return;
}
}
lumafilter0 = tve_readl(TV_LUMA_FILTER0);
@@ -432,14 +470,37 @@ static void check_uboot_logo(struct rockchip_tve *tve)
return;
}
dac_init(tve);
if (tve->soc_type == SOC_RK322X || tve->soc_type == SOC_RK3328)
dac_init(tve);
tve->connector.dpms = DRM_MODE_DPMS_OFF;
}
static const struct rockchip_tve_data rk3036_tve = {
.soc_type = SOC_RK3036,
.input_format = INPUT_FORMAT_RGB,
};
static const struct rockchip_tve_data rk312x_tve = {
.soc_type = SOC_RK312X,
.input_format = INPUT_FORMAT_RGB,
};
static const struct rockchip_tve_data rk322x_tve = {
.soc_type = SOC_RK322X,
.input_format = INPUT_FORMAT_YUV,
};
static const struct rockchip_tve_data rk3328_tve = {
.soc_type = SOC_RK3328,
.input_format = INPUT_FORMAT_YUV,
};
static const struct of_device_id rockchip_tve_dt_ids[] = {
{
.compatible = "rockchip,rk3328-tve",
},
{ .compatible = "rockchip,rk3036-tve", .data = &rk3036_tve },
{ .compatible = "rockchip,rk312x-tve", .data = &rk312x_tve },
{ .compatible = "rockchip,rk322x-tve", .data = &rk322x_tve },
{ .compatible = "rockchip,rk3328-tve", .data = &rk3328_tve },
{}
};
@@ -452,6 +513,7 @@ static int rockchip_tve_bind(struct device *dev, struct device *master,
struct drm_device *drm_dev = data;
struct device_node *np = dev->of_node;
const struct of_device_id *match;
const struct rockchip_tve_data *tve_data;
struct rockchip_tve *tve;
struct resource *res;
struct drm_encoder *encoder;
@@ -469,11 +531,10 @@ static int rockchip_tve_bind(struct device *dev, struct device *master,
}
tve->dev = &pdev->dev;
if (!strcmp(match->compatible, "rockchip,rk3328-tve")) {
tve->inputformat = INPUT_FORMAT_YUV;
} else {
dev_err(tve->dev, "It is not a valid tv encoder! ");
return -ENOMEM;
tve_data = of_device_get_match_data(dev);
if (tve_data) {
tve->soc_type = tve_data->soc_type;
tve->input_format = tve_data->input_format;
}
ret = tve_parse_dt(np, tve);
@@ -483,7 +544,6 @@ static int rockchip_tve_bind(struct device *dev, struct device *master,
}
tve->enable = 0;
platform_set_drvdata(pdev, tve);
tve->drm_dev = drm_dev;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
tve->reg_phy_base = res->start;
@@ -491,19 +551,36 @@ static int rockchip_tve_bind(struct device *dev, struct device *master,
tve->regbase = devm_ioremap(tve->dev, res->start, tve->len);
if (IS_ERR(tve->regbase)) {
dev_err(tve->dev,
"rk3328 tv encoder device map registers failed!");
"tv encoder device map registers failed!");
return PTR_ERR(tve->regbase);
}
res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
tve->len = resource_size(res);
tve->vdacbase = devm_ioremap(tve->dev, res->start, tve->len);
if (IS_ERR(tve->vdacbase)) {
dev_err(tve->dev,
"rk3328 tv encoder device dac map registers failed!");
return PTR_ERR(tve->vdacbase);
if (tve->soc_type == SOC_RK322X || tve->soc_type == SOC_RK3328) {
res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
tve->len = resource_size(res);
tve->vdacbase = devm_ioremap(tve->dev, res->start, tve->len);
if (IS_ERR(tve->vdacbase)) {
dev_err(tve->dev, "tv encoder device dac map registers failed!");
return PTR_ERR(tve->vdacbase);
}
}
if (tve->soc_type == SOC_RK3036) {
tve->aclk = devm_clk_get(tve->dev, "aclk");
if (IS_ERR(tve->aclk)) {
dev_err(tve->dev, "Unable to get tve aclk\n");
return PTR_ERR(tve->aclk);
}
ret = clk_prepare_enable(tve->aclk);
if (ret) {
dev_err(tve->dev, "Cannot enable tve aclk: %d\n", ret);
return ret;
}
}
tve->dac_grf = syscon_regmap_lookup_by_phandle(dev->of_node, "rockchip,grf");
mutex_init(&tve->suspend_lock);
check_uboot_logo(tve);
tve->tv_format = TVOUT_CVBS_PAL;
@@ -516,7 +593,7 @@ static int rockchip_tve_bind(struct device *dev, struct device *master,
DRM_MODE_ENCODER_TVDAC, NULL);
if (ret < 0) {
dev_err(tve->dev, "failed to initialize encoder with drm\n");
return ret;
goto err_disable_aclk;
}
drm_encoder_helper_add(encoder, &rockchip_tve_encoder_helper_funcs);
@@ -544,6 +621,7 @@ static int rockchip_tve_bind(struct device *dev, struct device *master,
rockchip_drm_register_sub_dev(&tve->sub_dev);
pm_runtime_enable(dev);
dev_set_drvdata(dev, tve);
dev_dbg(tve->dev, "%s tv encoder probe ok\n", match->compatible);
return 0;
@@ -552,6 +630,10 @@ err_free_connector:
drm_connector_cleanup(connector);
err_free_encoder:
drm_encoder_cleanup(encoder);
err_disable_aclk:
if (tve->soc_type == SOC_RK3036)
clk_disable_unprepare(tve->aclk);
return ret;
}
@@ -567,6 +649,7 @@ static void rockchip_tve_unbind(struct device *dev, struct device *master,
drm_encoder_cleanup(&tve->encoder);
pm_runtime_disable(dev);
dev_set_drvdata(dev, NULL);
}
static const struct component_ops rockchip_tve_component_ops = {
@@ -585,6 +668,9 @@ static void rockchip_tve_shutdown(struct platform_device *pdev)
{
struct rockchip_tve *tve = dev_get_drvdata(&pdev->dev);
if (!tve)
return;
mutex_lock(&tve->suspend_lock);
dev_dbg(tve->dev, "tve shutdown\n");

15
drivers/gpu/drm/rockchip/rockchip_drm_tve.h
View File

@@ -15,6 +15,9 @@
#ifndef __ROCKCHIP_DRM_TVE_H__
#define __ROCKCHIP_DRM_TVE_H__
#define RK3036_GRF_SOC_CON3 0x0154
#define RK312X_GRF_TVE_CON 0x0170
#define TV_CTRL (0x00)
#define m_CVBS_MODE BIT(24)
#define m_CLK_UPSTREAM_EN (3 << 18)
@@ -129,6 +132,13 @@ enum {
INPUT_FORMAT_YUV
};
enum {
SOC_RK3036 = 0,
SOC_RK312X,
SOC_RK322X,
SOC_RK3328
};
#define grf_writel(offset, v) do { \
writel_relaxed(v, RK_GRF_VIRT + (offset)); \
dsb(sy); \
@@ -143,10 +153,13 @@ struct rockchip_tve {
u32 tv_format;
void __iomem *regbase;
void __iomem *vdacbase;
struct clk *aclk;
struct clk *dac_clk;
struct regmap *dac_grf;
u32 reg_phy_base;
u32 len;
int inputformat;
int input_format;
int soc_type;
bool enable;
u32 test_mode;
u32 saturation;

17
drivers/gpu/drm/rockchip/rockchip_drm_vop.c
View File

@@ -826,11 +826,22 @@ static void scl_vop_cal_scl_fac(struct vop *vop, const struct vop_win *win,
uint16_t lb_mode;
uint32_t val;
const struct vop_data *vop_data = vop->data;
struct drm_display_mode *adjusted_mode = &vop->rockchip_crtc.crtc.state->adjusted_mode;
int vskiplines;
if (!win->phy->scl)
return;
if ((adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) && vop->version == VOP_VERSION(2, 2)) {
VOP_SCL_SET(vop, win, scale_yrgb_x, ((src_w << 12) / dst_w));
VOP_SCL_SET(vop, win, scale_yrgb_y, ((src_h << 12) / dst_h));
if (is_yuv) {
VOP_SCL_SET(vop, win, scale_cbcr_x, ((cbcr_src_w << 12) / dst_w));
VOP_SCL_SET(vop, win, scale_cbcr_y, ((cbcr_src_h << 12) / dst_h));
}
return;
}
if (!(vop_data->feature & VOP_FEATURE_ALPHA_SCALE)) {
if (is_alpha_support(pixel_format) &&
(src_w != dst_w || src_h != dst_h))
@@ -2011,6 +2022,8 @@ static void vop_plane_atomic_update(struct drm_plane *plane,
dsp_h = 4;
actual_h = dsp_h * actual_h / drm_rect_height(dest);
}
if ((adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) && vop->version == VOP_VERSION(2, 2))
dsp_h = dsp_h / 2;
act_info = (actual_h - 1) << 16 | ((actual_w - 1) & 0xffff);
@@ -2019,6 +2032,8 @@ static void vop_plane_atomic_update(struct drm_plane *plane,
dsp_stx = dest->x1 + mode->crtc_htotal - mode->crtc_hsync_start;
dsp_sty = dest->y1 + mode->crtc_vtotal - mode->crtc_vsync_start;
if ((adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) && vop->version == VOP_VERSION(2, 2))
dsp_sty = dest->y1 / 2 + mode->crtc_vtotal - mode->crtc_vsync_start;
dsp_st = dsp_sty << 16 | (dsp_stx & 0xffff);
s = to_rockchip_crtc_state(crtc->state);
@@ -2046,7 +2061,7 @@ static void vop_plane_atomic_update(struct drm_plane *plane,
if (win->phy->scl)
scl_vop_cal_scl_fac(vop, win, actual_w, actual_h,
drm_rect_width(dest), drm_rect_height(dest),
drm_rect_width(dest), dsp_h,
fb->format->format);
if (VOP_WIN_SUPPORT(vop, win, color_key))

1
drivers/gpu/drm/rockchip/rockchip_drm_vop.h
View File

@@ -254,6 +254,7 @@ struct vop_ctrl {
struct vop_reg post_scl_factor;
struct vop_reg post_scl_ctrl;
struct vop_reg dsp_interlace;
struct vop_reg dsp_interlace_pol;
struct vop_reg global_regdone_en;
struct vop_reg auto_gate_en;
struct vop_reg post_lb_mode;

34
drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
View File

@@ -1488,6 +1488,9 @@ static inline void rk3568_vop2_cfg_done(struct drm_crtc *crtc)
* This is rather low probability for miss some done bit.
*/
val |= vop2_readl(vop2, RK3568_REG_CFG_DONE) & 0x7;
rockchip_drm_dbg(vop2->dev, VOP_DEBUG_CFG_DONE, "cfg_done: 0x%x\n", val);
vop2_writel(vop2, 0, val);
/**
@@ -1513,6 +1516,8 @@ static inline void rk3588_vop2_cfg_done(struct drm_crtc *crtc)
if (vcstate->splice_mode)
val |= BIT(vp_data->splice_vp_id) | (BIT(vp_data->splice_vp_id) << 16);
rockchip_drm_dbg(vop2->dev, VOP_DEBUG_CFG_DONE, "cfg_done: 0x%x\n", val);
vop2_writel(vop2, 0, val);
}
@@ -3156,8 +3161,10 @@ static void vop2_wb_commit(struct drm_crtc *crtc)
if (conn_state->writeback_job && conn_state->writeback_job->fb) {
struct drm_framebuffer *fb = conn_state->writeback_job->fb;
DRM_DEV_DEBUG(vop2->dev, "Enable wb %ux%u fmt: %u pitches: %d addr: %pad\n",
fb->width, fb->height, wb_state->format, fb->pitches[0], &wb_state->yrgb_addr);
rockchip_drm_dbg(vop2->dev, VOP_DEBUG_WB,
"Enable wb %ux%u fmt: %u pitches: %d addr: %pad\n",
fb->width, fb->height, wb_state->format,
fb->pitches[0], &wb_state->yrgb_addr);
drm_writeback_queue_job(wb_conn, conn_state);
conn_state->writeback_job = NULL;
@@ -4611,7 +4618,8 @@ static void vop2_plane_atomic_disable(struct drm_plane *plane, struct drm_plane_
struct vop2_plane_state *vpstate = to_vop2_plane_state(plane->state);
#endif
DRM_DEV_DEBUG(vop2->dev, "%s disable\n", win->name);
rockchip_drm_dbg(vop2->dev, VOP_DEBUG_PLANE, "%s disable %s\n",
win->name, current->comm);
if (!old_state->crtc)
return;
@@ -4896,11 +4904,12 @@ static void vop2_win_atomic_update(struct vop2_win *win, struct drm_rect *src, s
vop2_win_enable(win);
spin_lock(&vop2->reg_lock);
DRM_DEV_DEBUG(vop2->dev, "vp%d update %s[%dx%d->%dx%d@(%d, %d)] fmt[%.4s%s] addr[%pad]\n",
vp->id, win->name, actual_w, actual_h, dsp_w, dsp_h,
dsp_stx, dsp_sty,
drm_get_format_name(fb->format->format, &format_name),
modifier_to_string(fb->modifier), &vpstate->yrgb_mst);
rockchip_drm_dbg(vop2->dev, VOP_DEBUG_PLANE,
"vp%d update %s[%dx%d->%dx%d@(%d, %d)] fmt[%.4s%s] addr[%pad] by %s\n",
vp->id, win->name, actual_w, actual_h, dsp_w, dsp_h,
dsp_stx, dsp_sty,
drm_get_format_name(fb->format->format, &format_name),
modifier_to_string(fb->modifier), &vpstate->yrgb_mst, current->comm);
if (vop2->version != VOP_VERSION_RK3568)
rk3588_vop2_win_cfg_axi(win);
@@ -8478,8 +8487,8 @@ static void vop2_crtc_atomic_begin(struct drm_crtc *crtc, struct drm_crtc_state
vop2_zpos[nr_layers].zpos = vpstate->zpos;
vop2_zpos[nr_layers].plane = plane;
DRM_DEV_DEBUG(vop2->dev, "%s active zpos:%d for vp%d from vp%d\n",
win->name, vpstate->zpos, vp->id, old_vp->id);
rockchip_drm_dbg(vop2->dev, VOP_DEBUG_OVERLAY, "%s active zpos:%d for vp%d from vp%d\n",
win->name, vpstate->zpos, vp->id, old_vp->id);
/* left and right win may have different number */
if (vcstate->splice_mode) {
splice_win = vop2_find_win_by_phys_id(vop2, win->splice_win_id);
@@ -8512,8 +8521,8 @@ static void vop2_crtc_atomic_begin(struct drm_crtc *crtc, struct drm_crtc_state
}
vp->hdr10_at_splice_mode = hdr10_at_splice_mode;
DRM_DEV_DEBUG(vop2->dev, "vp%d: %d windows, active layers %d\n",
vp->id, hweight32(vp->win_mask), nr_layers);
rockchip_drm_dbg(vop2->dev, VOP_DEBUG_OVERLAY, "vp%d: %d windows, active layers %d\n",
vp->id, hweight32(vp->win_mask), nr_layers);
if (nr_layers) {
vp->nr_layers = nr_layers;
@@ -9345,6 +9354,7 @@ static irqreturn_t vop2_isr(int irq, void *data)
}
if (active_irqs & FS_FIELD_INTR) {
rockchip_drm_dbg(vop2->dev, VOP_DEBUG_VSYNC, "vsync_vp%d\n", vp->id);
vop2_wb_handler(vp);
if (likely(!vp->skip_vsync) || (vp->layer_sel_update == false)) {
drm_crtc_handle_vblank(crtc);

10
drivers/gpu/drm/rockchip/rockchip_vop_reg.c
View File

@@ -1239,19 +1239,27 @@ static const struct vop_intr rk3036_intr = {
static const struct vop_ctrl rk3036_ctrl_data = {
.standby = VOP_REG(RK3036_SYS_CTRL, 0x1, 30),
.sw_dac_sel = VOP_REG(RK3036_SYS_CTRL, 0x1, 29),
.out_mode = VOP_REG(RK3036_DSP_CTRL0, 0xf, 0),
.dsp_interlace = VOP_REG(RK3036_DSP_CTRL0, 0x1, 12),
.dsp_blank = VOP_REG(RK3036_DSP_CTRL1, 0x1, 24),
.dsp_background = VOP_REG(RK3036_DSP_CTRL1, 0xffffff, 0),
.dclk_pol = VOP_REG(RK3036_DSP_CTRL0, 0x1, 7),
.pin_pol = VOP_REG(RK3036_DSP_CTRL0, 0x7, 4),
.dither_down_sel = VOP_REG(RK3036_DSP_CTRL0, 0x1, 27),
.tve_sw_mode = VOP_REG(RK3036_DSP_CTRL0, 0x1, 25),
.dsp_interlace_pol = VOP_REG(RK3036_DSP_CTRL0, 0x1, 13),
.dither_down_en = VOP_REG(RK3036_DSP_CTRL0, 0x1, 11),
.dither_down_mode = VOP_REG(RK3036_DSP_CTRL0, 0x1, 10),
.dither_up_en = VOP_REG(RK3036_DSP_CTRL0, 0x1, 9),
.dsp_layer_sel = VOP_REG(RK3036_DSP_CTRL0, 0x1, 8),
.htotal_pw = VOP_REG(RK3036_DSP_HTOTAL_HS_END, 0x1fff1fff, 0),
.hact_st_end = VOP_REG(RK3036_DSP_HACT_ST_END, 0x1fff1fff, 0),
.tve_dclk_en = VOP_REG(RK3036_AXI_BUS_CTRL, 0x1, 20),
.tve_dclk_pol = VOP_REG(RK3036_AXI_BUS_CTRL, 0x1, 21),
.hdmi_en = VOP_REG(RK3036_AXI_BUS_CTRL, 0x1, 22),
.hdmi_dclk_pol = VOP_REG(RK3036_AXI_BUS_CTRL, 0x1, 23),
.core_dclk_div = VOP_REG(RK3036_AXI_BUS_CTRL, 0x1, 30),
.hdmi_pin_pol = VOP_REG(RK3036_INT_SCALER, 0x7, 4),
.rgb_en = VOP_REG(RK3036_AXI_BUS_CTRL, 0x1, 24),
.rgb_dclk_pol = VOP_REG(RK3036_AXI_BUS_CTRL, 0x1, 25),
@@ -1261,6 +1269,8 @@ static const struct vop_ctrl rk3036_ctrl_data = {
.mipi_dclk_pol = VOP_REG(RK3036_AXI_BUS_CTRL, 0x1, 29),
.vtotal_pw = VOP_REG(RK3036_DSP_VTOTAL_VS_END, 0x1fff1fff, 0),
.vact_st_end = VOP_REG(RK3036_DSP_VACT_ST_END, 0x1fff1fff, 0),
.vs_st_end_f1 = VOP_REG(RK3036_DSP_VS_ST_END_F1, 0x1fff1fff, 0),
.vact_st_end_f1 = VOP_REG(RK3036_DSP_VACT_ST_END_F1, 0x1fff1fff, 0),
.cfg_done = VOP_REG(RK3036_REG_CFG_DONE, 0x1, 0),
};

4
drivers/iommu/rockchip-iommu.c
View File

@@ -1960,12 +1960,16 @@ static void rk_iommu_shutdown(struct platform_device *pdev)
struct rk_iommu *iommu = platform_get_drvdata(pdev);
int i;
if (iommu->skip_read)
goto skip_free_irq;
for (i = 0; i < iommu->num_irq; i++) {
int irq = platform_get_irq(pdev, i);
devm_free_irq(iommu->dev, irq, iommu);
}
skip_free_irq:
pm_runtime_force_suspend(&pdev->dev);
}

26
drivers/irqchip/irq-gic-v3-its.c
View File

@@ -163,6 +163,7 @@ struct its_device {
struct its_node *its;
struct event_lpi_map event_map;
void *itt;
u32 itt_sz;
u32 nr_ites;
u32 device_id;
bool shared;
@@ -3430,9 +3431,13 @@ static struct its_device *its_create_device(struct its_node *its, u32 dev_id,
sz = nr_ites * (FIELD_GET(GITS_TYPER_ITT_ENTRY_SIZE, its->typer) + 1);
sz = max(sz, ITS_ITT_ALIGN) + ITS_ITT_ALIGN - 1;
gfp_flags = GFP_KERNEL;
if (of_machine_is_compatible("rockchip,rk3568") || of_machine_is_compatible("rockchip,rk3566"))
if (of_machine_is_compatible("rockchip,rk3568") || of_machine_is_compatible("rockchip,rk3566")) {
gfp_flags |= GFP_DMA32;
itt = kzalloc_node(sz, gfp_flags, its->numa_node);
itt = (void *)__get_free_pages(gfp_flags, get_order(sz));
} else {
itt = kzalloc_node(sz, gfp_flags, its->numa_node);
}
if (alloc_lpis) {
lpi_map = its_lpi_alloc(nvecs, &lpi_base, &nr_lpis);
if (lpi_map)
@@ -3446,7 +3451,13 @@ static struct its_device *its_create_device(struct its_node *its, u32 dev_id,
if (!dev || !itt || !col_map || (!lpi_map && alloc_lpis)) {
kfree(dev);
kfree(itt);
if (of_machine_is_compatible("rockchip,rk3568") ||
of_machine_is_compatible("rockchip,rk3566"))
free_pages((unsigned long)itt, get_order(sz));
else
kfree(itt);
kfree(lpi_map);
kfree(col_map);
return NULL;
@@ -3456,6 +3467,7 @@ static struct its_device *its_create_device(struct its_node *its, u32 dev_id,
dev->its = its;
dev->itt = itt;
dev->itt_sz = sz;
dev->nr_ites = nr_ites;
dev->event_map.lpi_map = lpi_map;
dev->event_map.col_map = col_map;
@@ -3483,7 +3495,13 @@ static void its_free_device(struct its_device *its_dev)
list_del(&its_dev->entry);
raw_spin_unlock_irqrestore(&its_dev->its->lock, flags);
kfree(its_dev->event_map.col_map);
kfree(its_dev->itt);
if (of_machine_is_compatible("rockchip,rk3568") ||
of_machine_is_compatible("rockchip,rk3566"))
free_pages((unsigned long)its_dev->itt, get_order(its_dev->itt_sz));
else
kfree(its_dev->itt);
kfree(its_dev);
}

22
drivers/media/i2c/Kconfig
View File

@@ -368,6 +368,17 @@ config VIDEO_LT6911UXC
To compile this driver as a module, choose M here: the
module will be called lt6911uxc.
config VIDEO_LT6911UXE
tristate "Lontium LT6911UXE decoder"
depends on VIDEO_V4L2 && I2C && VIDEO_V4L2_SUBDEV_API
select HDMI
select V4L2_FWNODE
help
Support for the Lontium LT6911UXE series HDMI to MIPI CSI-2 bridge.
To compile this driver as a module, choose M here: the
module will be called lt6911uxe.
config VIDEO_LT7911D
tristate "Lontium LT7911D decoder"
depends on VIDEO_V4L2 && I2C && VIDEO_V4L2_SUBDEV_API
@@ -920,6 +931,17 @@ config VIDEO_GC08A3
To compile this driver as a module, choose M here: the
module will be called gc08a3.
config VIDEO_GC1084
tristate "GalaxyCore GC1084 sensor support"
depends on I2C && VIDEO_V4L2 && VIDEO_V4L2_SUBDEV_API
depends on MEDIA_CAMERA_SUPPORT
select V4L2_FWNODE
help
Support for the GalaxyCore GC1084 sensor.
To compile this driver as a module, choose M here: the
module will be called gc1084.
config VIDEO_GC2053
tristate "GalaxyCore GC2053 sensor support"
depends on I2C && VIDEO_V4L2 && VIDEO_V4L2_SUBDEV_API

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