diff --git a/Documentation/devicetree/bindings/phy/phy-rockchip-inno-usb2.yaml b/Documentation/devicetree/bindings/phy/phy-rockchip-inno-usb2.yaml
index 731f9a1f8dbf..dc4ca36a62c2 100644
--- a/Documentation/devicetree/bindings/phy/phy-rockchip-inno-usb2.yaml
+++ b/Documentation/devicetree/bindings/phy/phy-rockchip-inno-usb2.yaml
@@ -166,6 +166,10 @@ properties:
          controller. It's used when the usb3 phy is disabled, and it needs
          to combine with the usbctrl-grf.
 
+     rockchip,dis-u2-susphy:
+       $ref: /schemas/types.yaml#/definitions/flag
+       description: when set, disable the usb2 phy enter suspend automatically.
+
     required:
       - "#phy-cells"
       - interrupts
diff --git a/MAINTAINERS b/MAINTAINERS
index 3dc294427f65..2d38ecf09480 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -11844,6 +11844,12 @@ F:	Documentation/userspace-api/media/drivers/meye*
 F:	drivers/media/pci/meye/
 F:	include/uapi/linux/meye.h
 
+MOTORCOMM PHY DRIVER
+M:	Peter Geis <pgwipeout@gmail.com>
+L:	netdev@vger.kernel.org
+S:	Maintained
+F:	drivers/net/phy/motorcomm.c
+
 MOXA SMARTIO/INDUSTIO/INTELLIO SERIAL CARD
 M:	Jiri Slaby <jirislaby@kernel.org>
 S:	Maintained
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index c4e531c1b0f6..c9c729eb3243 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -993,7 +993,9 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \
 	rv1106g-evb1-v10-spi-nand.dtb \
 	rv1106g-evb1-v10-spi-nor.dtb \
 	rv1106g-evb2-v10.dtb \
+	rv1106g-evb2-v11-emmc.dtb \
 	rv1106g-smart-door-lock-rmsl-v10.dtb \
+	rv1106g-smart-door-lock-rmsl-v12.dtb \
 	rv1106g-uvc-demo-v10.dtb \
 	rv1106g-uvc-demo-v10-spi-nor.dtb \
 	rv1108-elgin-r1.dtb \
diff --git a/arch/arm/boot/dts/rk3036-echo.dts b/arch/arm/boot/dts/rk3036-echo.dts
index 0d0b43829162..140c93c6c444 100644
--- a/arch/arm/boot/dts/rk3036-echo.dts
+++ b/arch/arm/boot/dts/rk3036-echo.dts
@@ -167,6 +167,10 @@
 	status = "okay";
 };
 
+&hevc {
+	status = "okay";
+};
+
 &hevc_mmu {
 	status = "okay";
 };
@@ -644,6 +648,10 @@
 	status = "okay";
 };
 
+&mpp_srv {
+	status = "okay";
+};
+
 &sdio {
 	status = "okay";
 
@@ -693,6 +701,14 @@
 	status = "okay";
 };
 
+&vdpu {
+	status = "okay";
+};
+
+&vpu_mmu {
+	status = "okay";
+};
+
 &vop {
 	status = "okay";
 };
@@ -701,14 +717,6 @@
 	status = "okay";
 };
 
-&vpu_combo {
-	status = "okay";
-};
-
-&vpu_mmu {
-	status = "okay";
-};
-
 &wdt {
 	status = "okay";
 };
diff --git a/arch/arm/boot/dts/rk3036-kylin.dts b/arch/arm/boot/dts/rk3036-kylin.dts
index 0b11411ea75c..41480890bb6a 100644
--- a/arch/arm/boot/dts/rk3036-kylin.dts
+++ b/arch/arm/boot/dts/rk3036-kylin.dts
@@ -175,6 +175,10 @@
 	status = "okay";
 };
 
+&hevc {
+	status = "okay";
+};
+
 &hevc_mmu {
 	status = "okay";
 };
@@ -372,6 +376,10 @@
 	status = "okay";
 };
 
+&mpp_srv {
+	status = "okay";
+};
+
 &sdio {
 	status = "okay";
 
@@ -421,6 +429,14 @@
 	status = "okay";
 };
 
+&vdpu {
+	status = "okay";
+};
+
+&vpu_mmu {
+	status = "okay";
+};
+
 &vop {
 	status = "okay";
 };
@@ -429,14 +445,6 @@
 	status = "okay";
 };
 
-&vpu_combo {
-	status = "okay";
-};
-
-&vpu_mmu {
-	status = "okay";
-};
-
 &wdt {
 	status = "okay";
 };
diff --git a/arch/arm/boot/dts/rk3036.dtsi b/arch/arm/boot/dts/rk3036.dtsi
index 351e4b1631a7..98427574b674 100644
--- a/arch/arm/boot/dts/rk3036.dtsi
+++ b/arch/arm/boot/dts/rk3036.dtsi
@@ -155,24 +155,40 @@
 	};
 
 	gpu: gpu@10090000 {
-		compatible = "rockchip,rk3036-mali", "arm,mali-400";
+		compatible = "arm,mali400";
 		reg = <0x10090000 0x10000>;
+		upthreshold = <40>;
+		downdifferential = <10>;
+
 		interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
-		interrupt-names = "gp",
-				  "gpmmu",
-				  "pp0",
-				  "ppmmu0";
+			    <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
+			    <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
+			    <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+
+		interrupt-names = "Mali_GP_IRQ",
+				  "Mali_GP_MMU_IRQ",
+				  "Mali_PP0_IRQ",
+				  "Mali_PP0_MMU_IRQ";
+
+		clocks = <&cru SCLK_GPU>;
+		clock-names = "clk_mali";
 		assigned-clocks = <&cru SCLK_GPU>;
 		assigned-clock-rates = <400000000>;
 		assigned-clock-parents = <&cru PLL_DPLL>;
+		power-domains = <&power RK3036_PD_GPU>;
 		operating-points-v2 = <&gpu_opp_table>;
-		clocks = <&cru SCLK_GPU>, <&cru SCLK_GPU>;
-		clock-names = "bus", "core";
-		resets = <&cru SRST_GPU>;
+
 		status = "disabled";
+
+		gpu_power_model: power_model {
+			compatible = "arm,mali-simple-power-model";
+			voltage = <900>;
+			frequency = <500>;
+			static-power = <300>;
+			dynamic-power = <396>;
+			ts = <32000 4700 (-80) 2>;
+			thermal-zone = "soc-thermal";
+		};
 	};
 
 	gpu_opp_table: opp-table1 {
@@ -188,34 +204,32 @@
 		};
 	};
 
-	vpu: video-codec@10108000 {
-		compatible = "rockchip,rk3036-vpu", "rockchip,rk3288-vpu";
-		reg = <0x10108000 0x800>;
-		interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
-		interrupt-names = "vepu", "vdpu";
-		clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
-		clock-names = "aclk", "hclk";
-		iommus = <&vpu_mmu>;
-		/*
-		 * 3036's vpu could not run higher than 300M
-		 */
-		assigned-clocks = <&cru ACLK_VCODEC>;
-		assigned-clock-rates = <297000000>;
-		assigned-clock-parents = <&cru PLL_GPLL>;
-		power-domains = <&power RK3036_PD_VPU>;
+	mpp_srv: mpp-srv {
+		compatible = "rockchip,mpp-service";
+		rockchip,taskqueue-count = <1>;
+		rockchip,resetgroup-count = <1>;
 		status = "disabled";
 	};
 
-	vpu_service: vpu-service@10108400 {
-		compatible = "rockchip,sub";
+	vdpu: vdpu@10108400 {
+		compatible = "rockchip,vpu-decoder-v1";
 		reg = <0x10108400 0x400>;
-		dev_mode = <0>;
 		interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 		interrupt-names = "irq_dec";
+		clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
+		clock-names = "aclk_vcodec", "hclk_vcodec";
+		rockchip,normal-rates = <297000000>, <0>;
+		assigned-clocks = <&cru ACLK_VCODEC>;
+		assigned-clock-rates = <297000000>;
+		assigned-clock-parents = <&cru PLL_GPLL>;
+		resets = <&cru SRST_VCODEC_A>, <&cru SRST_VCODEC_H>;
+		reset-names = "shared_video_a", "shared_video_h";
 		iommus = <&vpu_mmu>;
-		allocator = <1>;
 		power-domains = <&power RK3036_PD_VPU>;
+		rockchip,srv = <&mpp_srv>;
+		rockchip,taskqueue-node = <0>;
+		rockchip,resetgroup-node = <0>;
+		status = "disabled";
 	};
 
 	vpu_mmu: iommu@10108800 {
@@ -223,20 +237,32 @@
 		reg = <0x10108800 0x100>;
 		interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 		interrupt-names = "vpu_mmu";
+		clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
+		clock-names = "aclk", "iface";
 		#iommu-cells = <0>;
 		power-domains = <&power RK3036_PD_VPU>;
 		status = "disabled";
 	};
 
-	hevc_service: hevc-service@1010c000 {
-		compatible = "rockchip,sub";
+	hevc: hevc_service@1010c000 {
+		compatible = "rockchip,hevc-decoder";
 		reg = <0x1010c000 0x400>;
-		dev_mode = <1>;
 		interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 		interrupt-names = "irq_dec";
-		allocator = <1>;
+		clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>, <&cru ACLK_HEVC>;
+		clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core";
+		rockchip,normal-rates = <297000000>, <0>, <200000000>;
+		assigned-clocks = <&cru ACLK_VCODEC>;
+		assigned-clock-rates = <297000000>;
+		assigned-clock-parents = <&cru PLL_GPLL>;
+		resets = <&cru SRST_VCODEC_A>, <&cru SRST_VCODEC_H>, <&cru SRST_HEVC>;
+		reset-names = "shared_video_a", "shared_video_h", "video_core";
 		iommus = <&hevc_mmu>;
+		rockchip,srv = <&mpp_srv>;
+		rockchip,taskqueue-node = <0>;
+		rockchip,resetgroup-node = <0>;
 		power-domains = <&power RK3036_PD_VPU>;
+		status = "disabled";
 	};
 
 	hevc_mmu: iommu@1010c440 {
@@ -244,32 +270,13 @@
 		reg = <0x1010c440 0x40>, <0x1010c480 0x40>;
 		interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 		interrupt-names = "hevc_mmu";
+		clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
+		clock-names = "aclk", "iface";
 		#iommu-cells = <0>;
 		power-domains = <&power RK3036_PD_VPU>;
 		status = "disabled";
 	};
 
-	vpu_combo: vpu-combo {
-		compatible = "rockchip,vpu_combo";
-		rockchip,grf = <&grf>;
-		subcnt = <2>;
-		rockchip,sub = <&hevc_service>, <&vpu_service>;
-		mode_bit = <3>;
-		mode_ctrl = <0x144>;
-		clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>,
-			 <&cru ACLK_HEVC>;
-		clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core";
-		/* RK3036's vpu could not run higher than 300M */
-		assigned-clocks = <&cru ACLK_VCODEC>;
-		assigned-clock-rates = <297000000>;
-		assigned-clock-parents = <&cru PLL_GPLL>;
-		resets = <&cru SRST_VCODEC_A>, <&cru SRST_VCODEC_H>,
-			 <&cru SRST_HEVC>;
-		reset-names = "video_a", "video_h", "video";
-		power-domains = <&power RK3036_PD_VPU>;
-		status = "disabled";
-	};
-
 	vop: vop@10118000 {
 		compatible = "rockchip,rk3036-vop";
 		reg = <0x10118000 0x19c>;
@@ -288,6 +295,37 @@
 				reg = <0>;
 				remote-endpoint = <&hdmi_in_vop>;
 			};
+			vop_out_tve: endpoint@1 {
+				reg = <1>;
+				remote-endpoint = <&tve_in_vop>;
+			};
+		};
+	};
+
+	tve: tve@10118200 {
+		compatible = "rockchip,rk3036-tve";
+		reg = <0x10118200 0x100>;
+		clocks = <&cru ACLK_VIO>;
+		clock-names = "aclk";
+		rockchip,saturation = <0x00386346>;
+		rockchip,brightcontrast = <0x00008b00>;
+		rockchip,adjtiming = <0xa6c00880>;
+		rockchip,lumafilter0 = <0x02ff0000>;
+		rockchip,lumafilter1 = <0xf40202fd>;
+		rockchip,lumafilter2 = <0xf332d919>;
+		rockchip,daclevel = <0x3e>;
+		rockchip,grf = <&grf>;
+		status = "disabled";
+
+		ports {
+			tve_in: port {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				tve_in_vop: endpoint@0 {
+					reg = <0>;
+					remote-endpoint = <&vop_out_tve>;
+				};
+			};
 		};
 	};
 
@@ -386,6 +424,8 @@
 		interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 		resets = <&cru SRST_MMC0>;
 		reset-names = "reset";
+		no-mmc;
+		no-sdio;
 		status = "disabled";
 	};
 
@@ -400,6 +440,8 @@
 		interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 		resets = <&cru SRST_SDIO>;
 		reset-names = "reset";
+		no-mmc;
+		no-sd;
 		status = "disabled";
 	};
 
@@ -420,6 +462,8 @@
 		dma-names = "rx-tx";
 		fifo-depth = <0x100>;
 		non-removable;
+		no-sdio;
+		no-sd;
 		pinctrl-names = "default";
 		pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
 		resets = <&cru SRST_EMMC>;
@@ -482,7 +526,10 @@
 					 <&cru ACLK_HEVC>;
 				pm_qos = <&qos_vpu>;
 			};
-
+			pd_gpu@RK3036_PD_GPU {
+				reg = <RK3036_PD_GPU>;
+				clocks = <&cru SCLK_GPU>;
+			};
 		};
 	};
 
@@ -554,7 +601,7 @@
 	};
 
 	pwm0: pwm@20050000 {
-		compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
+		compatible = "rockchip,rk3036-pwm", "rockchip,rk3288-pwm";
 		reg = <0x20050000 0x10>;
 		#pwm-cells = <3>;
 		clocks = <&cru PCLK_PWM>;
@@ -565,7 +612,7 @@
 	};
 
 	pwm1: pwm@20050010 {
-		compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
+		compatible = "rockchip,rk3036-pwm", "rockchip,rk3288-pwm";
 		reg = <0x20050010 0x10>;
 		#pwm-cells = <3>;
 		clocks = <&cru PCLK_PWM>;
@@ -576,7 +623,7 @@
 	};
 
 	pwm2: pwm@20050020 {
-		compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
+		compatible = "rockchip,rk3036-pwm", "rockchip,rk3288-pwm";
 		reg = <0x20050020 0x10>;
 		#pwm-cells = <3>;
 		clocks = <&cru PCLK_PWM>;
@@ -587,9 +634,10 @@
 	};
 
 	pwm3: pwm@20050030 {
-		compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
+		compatible = "rockchip,rk3036-pwm", "rockchip,rk3288-pwm";
 		reg = <0x20050030 0x10>;
-		#pwm-cells = <2>;
+		interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+		#pwm-cells = <3>;
 		clocks = <&cru PCLK_PWM>;
 		clock-names = "pwm";
 		pinctrl-names = "active";
@@ -746,35 +794,31 @@
 			bias-pull-pin-default;
 		};
 
-		pcfg_pull_up: pcfg-pull-up {
-			bias-pull-up;
-		};
-
 		pcfg_pull_none: pcfg-pull-none {
 			bias-disable;
 		};
 
 		pwm0 {
 			pwm0_pin: pwm0-pin {
-				rockchip,pins = <0 RK_PA0 2 &pcfg_pull_none>;
+				rockchip,pins = <0 RK_PA0 2 &pcfg_pull_default>;
 			};
 		};
 
 		pwm1 {
 			pwm1_pin: pwm1-pin {
-				rockchip,pins = <0 RK_PA1 2 &pcfg_pull_none>;
+				rockchip,pins = <0 RK_PA1 2 &pcfg_pull_default>;
 			};
 		};
 
 		pwm2 {
 			pwm2_pin: pwm2-pin {
-				rockchip,pins = <0 RK_PA1 2 &pcfg_pull_none>;
+				rockchip,pins = <0 RK_PA1 2 &pcfg_pull_default>;
 			};
 		};
 
 		pwm3 {
 			pwm3_pin: pwm3-pin {
-				rockchip,pins = <0 RK_PD3 1 &pcfg_pull_none>;
+				rockchip,pins = <0 RK_PD3 1 &pcfg_pull_default>;
 			};
 		};
 
@@ -910,8 +954,8 @@
 
 		uart0 {
 			uart0_xfer: uart0-xfer {
-				rockchip,pins = <0 RK_PC0 1 &pcfg_pull_up>,
-						<0 RK_PC1 1 &pcfg_pull_up>;
+				rockchip,pins = <0 RK_PC0 1 &pcfg_pull_default>,
+						<0 RK_PC1 1 &pcfg_pull_default>;
 			};
 
 			uart0_cts: uart0-cts {
@@ -925,16 +969,16 @@
 
 		uart1 {
 			uart1_xfer: uart1-xfer {
-				rockchip,pins = <2 RK_PC6 1 &pcfg_pull_up>,
-						<2 RK_PC7 1 &pcfg_pull_up>;
+				rockchip,pins = <2 RK_PC6 1 &pcfg_pull_default>,
+						<2 RK_PC7 1 &pcfg_pull_default>;
 			};
 			/* no rts / cts for uart1 */
 		};
 
 		uart2 {
 			uart2_xfer: uart2-xfer {
-				rockchip,pins = <1 RK_PC2 2 &pcfg_pull_up>,
-						<1 RK_PC3 2 &pcfg_pull_up>;
+				rockchip,pins = <1 RK_PC2 2 &pcfg_pull_default>,
+						<1 RK_PC3 2 &pcfg_pull_default>;
 			};
 			/* no rts / cts for uart2 */
 		};
diff --git a/arch/arm/boot/dts/rk3066a.dtsi b/arch/arm/boot/dts/rk3066a.dtsi
index 71e2495d78b2..3993abc9468f 100644
--- a/arch/arm/boot/dts/rk3066a.dtsi
+++ b/arch/arm/boot/dts/rk3066a.dtsi
@@ -503,10 +503,6 @@
 			bias-pull-pin-default;
 		};
 
-		pcfg_pull_up: pcfg-pull-up {
-			bias-pull-up;
-		};
-
 		pcfg_pull_none: pcfg_pull_none {
 			bias-disable;
 		};
@@ -658,8 +654,8 @@
 
 		uart0 {
 			uart0_xfer: uart0-xfer {
-				rockchip,pins = <1 RK_PA0 1 &pcfg_pull_up>,
-						<1 RK_PA1 1 &pcfg_pull_up>;
+				rockchip,pins = <1 RK_PA0 1 &pcfg_pull_default>,
+						<1 RK_PA1 1 &pcfg_pull_default>;
 			};
 
 			uart0_cts: uart0-cts {
@@ -673,8 +669,8 @@
 
 		uart1 {
 			uart1_xfer: uart1-xfer {
-				rockchip,pins = <1 RK_PA4 1 &pcfg_pull_up>,
-						<1 RK_PA5 1 &pcfg_pull_up>;
+				rockchip,pins = <1 RK_PA4 1 &pcfg_pull_default>,
+						<1 RK_PA5 1 &pcfg_pull_default>;
 			};
 
 			uart1_cts: uart1-cts {
@@ -688,16 +684,16 @@
 
 		uart2 {
 			uart2_xfer: uart2-xfer {
-				rockchip,pins = <1 RK_PB0 1 &pcfg_pull_up>,
-						<1 RK_PB1 1 &pcfg_pull_up>;
+				rockchip,pins = <1 RK_PB0 1 &pcfg_pull_default>,
+						<1 RK_PB1 1 &pcfg_pull_default>;
 			};
 			/* no rts / cts for uart2 */
 		};
 
 		uart3 {
 			uart3_xfer: uart3-xfer {
-				rockchip,pins = <3 RK_PD3 1 &pcfg_pull_up>,
-						<3 RK_PD4 1 &pcfg_pull_up>;
+				rockchip,pins = <3 RK_PD3 1 &pcfg_pull_default>,
+						<3 RK_PD4 1 &pcfg_pull_default>;
 			};
 
 			uart3_cts: uart3-cts {
diff --git a/arch/arm/boot/dts/rk3126c-evb-ddr3-v10-linux.dts b/arch/arm/boot/dts/rk3126c-evb-ddr3-v10-linux.dts
index 599b02d37bca..8f406ed7db2e 100644
--- a/arch/arm/boot/dts/rk3126c-evb-ddr3-v10-linux.dts
+++ b/arch/arm/boot/dts/rk3126c-evb-ddr3-v10-linux.dts
@@ -139,25 +139,6 @@
 	};
 };
 
-&codec {
-	#sound-dai-cells = <0>;
-	spk-ctl-gpios = <&gpio2 9 GPIO_ACTIVE_HIGH>;
-	spk-mute-delay = <200>;
-	hp-mute-delay = <100>;
-	rk312x_for_mid = <0>;
-	is_rk3128 = <0>;
-	spk_volume = <25>;
-	hp_volume = <25>;
-	capture_volume = <26>;
-	gpio_debug = <1>;
-	codec_hp_det = <0>;
-	status = "okay";
-};
-
-&cpu0 {
-	cpu-supply = <&vdd_arm>;
-};
-
 &cif_new {
 	status = "okay";
 
@@ -178,6 +159,25 @@
 	};
 };
 
+&codec {
+	#sound-dai-cells = <0>;
+	spk-ctl-gpios = <&gpio2 9 GPIO_ACTIVE_HIGH>;
+	spk-mute-delay = <200>;
+	hp-mute-delay = <100>;
+	rk312x_for_mid = <0>;
+	is_rk3128 = <0>;
+	spk_volume = <25>;
+	hp_volume = <25>;
+	capture_volume = <26>;
+	gpio_debug = <1>;
+	codec_hp_det = <0>;
+	status = "okay";
+};
+
+&cpu0 {
+	cpu-supply = <&vdd_arm>;
+};
+
 &display_subsystem {
 	status = "okay";
 };
@@ -751,6 +751,10 @@
 	status = "okay";
 };
 
+&mpp_srv {
+	status = "okay";
+};
+
 &nandc {
 	status = "okay";
 };
@@ -792,16 +796,6 @@
 	vref-supply = <&vccadc_ref>;
 };
 
-&sdmmc {
-	cap-mmc-highspeed;
-	supports-sd;
-	card-detect-delay = <800>;
-	ignore-pm-notify;
-	keep-power-in-suspend;
-	cd-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; /* CD GPIO */
-	status = "disabled";
-};
-
 &sdio {
 	bus-width = <4>;
 	max-frequency = <50000000>;
@@ -814,6 +808,16 @@
 	status = "okay";
 };
 
+&sdmmc {
+	cap-mmc-highspeed;
+	supports-sd;
+	card-detect-delay = <800>;
+	ignore-pm-notify;
+	keep-power-in-suspend;
+	cd-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; /* CD GPIO */
+	status = "disabled";
+};
+
 &tsadc {
 	status = "okay";
 };
@@ -849,6 +853,14 @@
 	status = "okay";
 };
 
+&vdpu {
+	status = "okay";
+};
+
+&vepu {
+	status = "okay";
+};
+
 &video_phy {
 	status = "okay";
 };
@@ -861,14 +873,6 @@
 	status = "okay";
 };
 
-&vdpu {
-	status = "okay";
-};
-
-&vepu {
-	status = "okay";
-};
-
 &vpu_mmu {
 	status = "okay";
 };
diff --git a/arch/arm/boot/dts/rk3128-evb-ddr3-v10-linux.dts b/arch/arm/boot/dts/rk3128-evb-ddr3-v10-linux.dts
index 5766da0b5514..7fe966946769 100644
--- a/arch/arm/boot/dts/rk3128-evb-ddr3-v10-linux.dts
+++ b/arch/arm/boot/dts/rk3128-evb-ddr3-v10-linux.dts
@@ -242,6 +242,20 @@
 	};
 };
 
+&cif_new {
+	status = "okay";
+
+	ports {
+		port@0 {
+			cif_in_bcam: endpoint@0 {
+				remote-endpoint = <&gc2145_out>;
+				vsync-active = <0>;
+				hsync-active = <1>;
+			};
+		};
+	};
+};
+
 &codec{
 	spk-ctl-gpios = <&gpio0 RK_PD6 GPIO_ACTIVE_HIGH>;
 	hp-ctl-gpios = <&gpio3 RK_PC4 GPIO_ACTIVE_LOW>;
@@ -264,20 +278,6 @@
 	cpu-supply = <&vdd_arm>;
 };
 
-&cif_new {
-	status = "okay";
-
-	ports {
-		port@0 {
-			cif_in_bcam: endpoint@0 {
-				remote-endpoint = <&gc2145_out>;
-				vsync-active = <0>;
-				hsync-active = <1>;
-			};
-		};
-	};
-};
-
 &display_subsystem {
 	status = "okay";
 };
@@ -615,6 +615,13 @@
 		#clock-cells = <1>;
 		clock-output-names = "rk805-clkout1", "rk805-clkout2";
 
+		vcc1-supply = <&vcc5v0_sys>;
+		vcc2-supply = <&vcc5v0_sys>;
+		vcc3-supply = <&vcc5v0_sys>;
+		vcc4-supply = <&vcc5v0_sys>;
+		vcc5-supply = <&vcc_io>;
+		vcc6-supply = <&vcc_io>;
+
 		rtc {
 			status = "okay";
 		};
@@ -633,7 +640,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 
-			vdd_arm: RK805_DCDC1@0 {
+			vdd_arm: DCDC_REG1 {
 				regulator-name = "vdd_arm";
 				regulator-min-microvolt = <700000>;
 				regulator-max-microvolt = <1500000>;
@@ -648,7 +655,7 @@
 				};
 			};
 
-			vdd_logic: RK805_DCDC2@1 {
+			vdd_logic: DCDC_REG2 {
 				regulator-name = "vdd_logic";
 				regulator-min-microvolt = <700000>;
 				regulator-max-microvolt = <1500000>;
@@ -663,7 +670,7 @@
 				};
 			};
 
-			vcc_ddr: RK805_DCDC3@2 {
+			vcc_ddr: DCDC_REG3 {
 				regulator-name = "vcc_ddr";
 				regulator-initial-mode = <0x1>;
 				regulator-boot-on;
@@ -674,7 +681,7 @@
 				};
 			};
 
-			vcc_io: RK805_DCDC4@3 {
+			vcc_io: DCDC_REG4 {
 				regulator-name = "vcc_io";
 				regulator-min-microvolt = <3300000>;
 				regulator-max-microvolt = <3300000>;
@@ -688,7 +695,7 @@
 				};
 			};
 
-			vcca_33: RK805_LDO1@4 {
+			vcca_33: LDO_REG1 {
 				regulator-name = "vcca_33";
 				regulator-min-microvolt = <3300000>;
 				regulator-max-microvolt = <3300000>;
@@ -701,7 +708,7 @@
 				};
 			};
 
-			vcc_1v8_cam: RK805_LDO2@5 {
+			vcc_1v8_cam: LDO_REG2 {
 				regulator-name = "vcc_1v8_cam";
 				regulator-min-microvolt = <1800000>;
 				regulator-max-microvolt = <1800000>;
@@ -713,7 +720,7 @@
 				};
 			};
 
-			vdd10_pmu: RK805_LDO3@6 {
+			vdd10_pmu: LDO_REG3 {
 				regulator-name = "vdd10_pmu";
 				regulator-min-microvolt = <1100000>;
 				regulator-max-microvolt = <1100000>;
@@ -785,6 +792,10 @@
 	#sound-dai-cells = <0>;
 };
 
+&mpp_srv {
+	status = "okay";
+};
+
 &pinctrl {
 	codec{
 		spk_ctl_h: spk-ctl-h{
@@ -895,19 +906,6 @@
 	vref-supply = <&vcc_io>;
 };
 
-&sdmmc {
-	cap-mmc-highspeed;
-	cap-sd-highspeed;
-	supports-sd;
-	vmmc-supply = <&vcc_sdmmc>;
-	broken-cd;
-	card-detect-delay = <800>;
-	ignore-pm-notify;
-	keep-power-in-suspend;
-	cd-gpios = <&gpio1 RK_PC1 GPIO_ACTIVE_HIGH>; /* CD GPIO */
-	status = "disabled";
-};
-
 &sdio {
 	max-frequency = <50000000>;
 	supports-sdio;
@@ -923,6 +921,19 @@
 	status = "okay";
 };
 
+&sdmmc {
+	cap-mmc-highspeed;
+	cap-sd-highspeed;
+	supports-sd;
+	vmmc-supply = <&vcc_sdmmc>;
+	broken-cd;
+	card-detect-delay = <800>;
+	ignore-pm-notify;
+	keep-power-in-suspend;
+	cd-gpios = <&gpio1 RK_PC1 GPIO_ACTIVE_HIGH>; /* CD GPIO */
+	status = "disabled";
+};
+
 &spdif{
 	compatible = "rockchip,rk3188-spdif";
 	status = "okay";
@@ -931,12 +942,6 @@
 	#sound-dai-cells = <0>;
 };
 
-&uart0{
-	pinctrl-names = "default";
-	pinctrl-0 = <&uart0_xfer &uart0_cts>;
-	status = "okay";
-};
-
 &u2phy {
 	status = "okay";
 
@@ -950,6 +955,12 @@
 	};
 };
 
+&uart0{
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart0_xfer &uart0_cts>;
+	status = "okay";
+};
+
 &usb_host_ehci {
 	status = "okay";
 };
@@ -962,14 +973,6 @@
 	status = "okay";
 };
 
-&vop {
-	status = "okay";
-};
-
-&vop_mmu {
-	status = "okay";
-};
-
 &vdpu {
 	status = "okay";
 };
@@ -978,6 +981,14 @@
 	status = "okay";
 };
 
+&vop {
+	status = "okay";
+};
+
+&vop_mmu {
+	status = "okay";
+};
+
 &vpu_mmu {
 	status = "okay";
 };
diff --git a/arch/arm/boot/dts/rk312x-android.dtsi b/arch/arm/boot/dts/rk312x-android.dtsi
index ab026fa9f53a..6c9ec7e604f3 100644
--- a/arch/arm/boot/dts/rk312x-android.dtsi
+++ b/arch/arm/boot/dts/rk312x-android.dtsi
@@ -24,7 +24,7 @@
 		rockchip,signal-irq = <159>;
 		rockchip,wake-irq = <0>;
 		/* If enable uart uses irq instead of fiq */
-		rockchip,irq-mode-enable = <0>;
+		rockchip,irq-mode-enable = <1>;
 		rockchip,baudrate = <115200>;  /* Only 115200 and 1500000 */
 		interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_LOW>;
 		status = "okay";
diff --git a/arch/arm/boot/dts/rk312x.dtsi b/arch/arm/boot/dts/rk312x.dtsi
index 484bec18b00b..528df389ba52 100644
--- a/arch/arm/boot/dts/rk312x.dtsi
+++ b/arch/arm/boot/dts/rk312x.dtsi
@@ -234,7 +234,7 @@
 		system-status-freq = <
 			/*system status		freq(KHz)*/
 			SYS_STATUS_NORMAL	456000
-			SYS_STATUS_SUSPEND	456000
+			SYS_STATUS_SUSPEND	300000
 			SYS_STATUS_REBOOT	456000
 		>;
 		auto-min-freq = <456000>;
@@ -248,6 +248,7 @@
 		opp-200000000 {
 			opp-hz = /bits/ 64 <200000000>;
 			opp-microvolt = <1025000>;
+			status = "disabled";
 		};
 		opp-300000000 {
 			opp-hz = /bits/ 64 <300000000>;
@@ -616,7 +617,6 @@
 		clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>;
 		clock-names = "aclk_rga", "hclk_rga", "sclk_rga";
 		power-domains = <&power RK3128_PD_VIO>;
-		dma-coherent;
 		status = "disabled";
 	};
 
@@ -1294,10 +1294,6 @@
 			bias-pull-pin-default;
 		};
 
-		pcfg_pull_up: pcfg-pull-up {
-			bias-pull-up;
-		};
-
 		pcfg_output_high: pcfg-output-high {
 			output-high;
 		};
@@ -1422,8 +1418,8 @@
 
 		uart0 {
 			uart0_xfer: uart0-xfer {
-				rockchip,pins = <2 RK_PD2 2 &pcfg_pull_up>,
-						<2 RK_PD3 2 &pcfg_pull_up>;
+				rockchip,pins = <2 RK_PD2 2 &pcfg_pull_default>,
+						<2 RK_PD3 2 &pcfg_pull_none>;
 			};
 
 			uart0_cts: uart0-cts {
@@ -1437,8 +1433,8 @@
 
 		uart1 {
 			uart1_xfer: uart1-xfer {
-				rockchip,pins = <1 RK_PB1 2 &pcfg_pull_up>,
-						<1 RK_PB2 2 &pcfg_pull_up>;
+				rockchip,pins = <1 RK_PB1 2 &pcfg_pull_default>,
+						<1 RK_PB2 2 &pcfg_pull_default>;
 			};
 
 			uart1_cts: uart1-cts {
@@ -1452,8 +1448,8 @@
 
 		uart2 {
 			uart2_xfer: uart2-xfer {
-				rockchip,pins = <1 RK_PC2 2 &pcfg_pull_up>,
-						<1 RK_PC3 2 &pcfg_pull_up>;
+				rockchip,pins = <1 RK_PC2 2 &pcfg_pull_default>,
+						<1 RK_PC3 2 &pcfg_pull_none>;
 			};
 
 			uart2_cts: uart2-cts {
diff --git a/arch/arm/boot/dts/rk3288-android.dtsi b/arch/arm/boot/dts/rk3288-android.dtsi
index b1d9d742c835..4922f3c00bae 100644
--- a/arch/arm/boot/dts/rk3288-android.dtsi
+++ b/arch/arm/boot/dts/rk3288-android.dtsi
@@ -152,11 +152,6 @@
 		};
 	};
 
-	psci {
-		compatible = "arm,psci-1.0";
-		method = "smc";
-	};
-
 	/delete-node/ timer@ff810000;
 
 	display-subsystem {
@@ -243,22 +238,6 @@
 	};
 };
 
-&cpu0 {
-	enable-method = "psci";
-};
-
-&cpu1 {
-	enable-method = "psci";
-};
-
-&cpu2 {
-	enable-method = "psci";
-};
-
-&cpu3 {
-	enable-method = "psci";
-};
-
 &dmac_bus_s {
 	/* change to non-secure dmac */
 	reg = <0x0 0xff600000 0x0 0x4000>;
diff --git a/arch/arm/boot/dts/rk3288-evb-act8846.dts b/arch/arm/boot/dts/rk3288-evb-act8846.dts
index be695b8c1f67..3e9393f1c12a 100644
--- a/arch/arm/boot/dts/rk3288-evb-act8846.dts
+++ b/arch/arm/boot/dts/rk3288-evb-act8846.dts
@@ -7,6 +7,22 @@
 	model = "Rockchip RK3288 EVB ACT8846";
 	compatible = "rockchip,rk3288-evb-act8846", "rockchip,rk3288";
 
+	sdio_pwrseq: sdio-pwrseq {
+		compatible = "mmc-pwrseq-simple";
+		clocks = <&hym8563>;
+		clock-names = "ext_clock";
+		pinctrl-names = "default";
+		pinctrl-0 = <&wifi_enable_h>;
+
+		/*
+		 * On the module itself this is one of these (depending
+		 * on the actual card populated):
+		 * - SDIO_RESET_L_WL_REG_ON
+		 * - PDN (power down when low)
+		 */
+		reset-gpios = <&gpio4 28 GPIO_ACTIVE_LOW>;
+	};
+
 	vcc_lcd: vcc-lcd {
 		compatible = "regulator-fixed";
 		enable-active-high;
@@ -54,12 +70,12 @@
 		vin-supply = <&vcc_sys>;
 	};
 
-	hym8563@51 {
+	hym8563: hym8563@51 {
 		compatible = "haoyu,hym8563";
 		reg = <0x51>;
 
 		interrupt-parent = <&gpio0>;
-		interrupts = <RK_PA4 IRQ_TYPE_EDGE_FALLING>;
+		interrupts = <4 IRQ_TYPE_EDGE_FALLING>;
 
 		pinctrl-names = "default";
 		pinctrl-0 = <&pmic_int>;
diff --git a/arch/arm/boot/dts/rk3288-evb-rk808-linux.dts b/arch/arm/boot/dts/rk3288-evb-rk808-linux.dts
index c8c2dfafe4f4..50f1e8134db8 100644
--- a/arch/arm/boot/dts/rk3288-evb-rk808-linux.dts
+++ b/arch/arm/boot/dts/rk3288-evb-rk808-linux.dts
@@ -41,44 +41,10 @@
 /dts-v1/;
 #include "rk3288-evb.dtsi"
 #include "rk3288-linux.dtsi"
-#include "rk3288-rkisp1.dtsi"
 
 / {
 	compatible = "rockchip,rk3288-evb-rk808-linux", "rockchip,rk3288";
 
-	panel {
-		compatible = "simple-panel";
-		backlight = <&backlight>;
-		enable-gpios = <&gpio7 RK_PA4 GPIO_ACTIVE_HIGH>;
-		prepare-delay-ms = <120>;
-
-		display-timings {
-			native-mode = <&timing0>;
-
-			timing0: timing0 {
-				clock-frequency = <200000000>;
-				hactive = <1536>;
-				vactive = <2048>;
-				hfront-porch = <12>;
-				hsync-len = <16>;
-				hback-porch = <48>;
-				vfront-porch = <8>;
-				vsync-len = <4>;
-				vback-porch = <8>;
-				hsync-active = <0>;
-				vsync-active = <0>;
-				de-active = <0>;
-				pixelclk-active = <0>;
-			};
-		};
-
-		port {
-			panel_in_edp: endpoint {
-				remote-endpoint = <&edp_out_panel>;
-			};
-		};
-	};
-
 	adc-keys {
 		compatible = "adc-keys";
 		io-channels = <&saradc 1>;
@@ -191,21 +157,6 @@
 	status = "okay";
 };
 
-&edp {
-	force-hpd;
-	status = "okay";
-
-	ports {
-		port@1 {
-			reg = <1>;
-
-			edp_out_panel: endpoint {
-				remote-endpoint = <&panel_in_edp>;
-			};
-		};
-	};
-};
-
 &edp_in_vopb {
 	status = "disabled";
 };
@@ -220,7 +171,7 @@
 };
 
 &hdmi {
-	pinctrl-0 = <&hdmi_ddc>, <&hdmi_cec>;
+	pinctrl-0 = <&hdmi_ddc>, <&hdmi_cec_c0>;
 };
 
 &i2c0 {
@@ -477,29 +428,50 @@
 
 	ov13850: ov13850@10 {
 		compatible = "ovti,ov13850";
-		status = "okay";
 		reg = <0x10>;
 		clocks = <&cru SCLK_VIP_OUT>;
 		clock-names = "xvclk";
-
-		reset-gpios = <&gpio7 21 GPIO_ACTIVE_HIGH>;
-		pwdn-gpios = <&gpio2 15 GPIO_ACTIVE_HIGH>;
-
+		/* avdd-supply = <>; */
+		/* dvdd-supply = <>; */
+		/* dovdd-supply = <>; */
+		/* reset-gpios = <>; */
+		pinctrl-names = "rockchip,camera_default";
+		pinctrl-0 = <&isp_mipi>;
+		power-gpio = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>;
+		reset-gpio = <&gpio7 RK_PC5 GPIO_ACTIVE_HIGH>;
+		pwdn-gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>;
+		rockchip,camera-module-index = <0>;
+		rockchip,camera-module-facing = "back";
+		rockchip,camera-module-name = "CMK-CT0116";
+		rockchip,camera-module-lens-name = "Largan-50013A1";
 		port {
-			cam_out: endpoint {
-				remote-endpoint = <&mipi_in_cam>;
+			ov13850_out: endpoint {
+				remote-endpoint = <&mipi_in_ucam0>;
 				data-lanes = <1 2>;
 			};
 		};
 	};
-};
 
-&isp {
-	status = "okay";
-
-	port {
-		isp_mipi_in: endpoint {
-			remote-endpoint = <&dphy_rx0_out>;
+	gc8034: gc8034@37 {
+		compatible = "galaxycore,gc8034";
+		status = "okay";
+		reg = <0x37>;
+		clocks = <&cru SCLK_VIP_OUT>;
+		clock-names = "xvclk";
+		pinctrl-names = "rockchip,camera_default";
+		pinctrl-0 = <&isp_mipi>;
+		power-gpio = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>;
+		reset-gpios = <&gpio7 RK_PC5 GPIO_ACTIVE_LOW>;
+		pwdn-gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_LOW>;
+		rockchip,camera-module-index = <0>;
+		rockchip,camera-module-facing = "back";
+		rockchip,camera-module-name = "LH-RK-8034-v1.0";
+		rockchip,camera-module-lens-name = "CK8401";
+		port {
+			gc8034_out: endpoint {
+				remote-endpoint = <&mipi_in_gc8034>;
+				data-lanes = <1 2 3 4>;
+			};
 		};
 	};
 };
@@ -517,23 +489,48 @@
 
 		port@0 {
 			reg = <0>;
+			#address-cells = <1>;
+			#size-cells = <0>;
 
-			mipi_in_cam: endpoint {
-				remote-endpoint = <&cam_out>;
+			mipi_in_ucam0: endpoint@1 {
+				reg = <1>;
+				remote-endpoint = <&ov13850_out>;
 				data-lanes = <1 2>;
 			};
+			mipi_in_gc8034: endpoint@0 {
+				reg = <0>;
+				remote-endpoint = <&gc8034_out>;
+				data-lanes = <1 2 3 4>;
+			};
 		};
 
 		port@1 {
 			reg = <1>;
+			#address-cells = <1>;
+			#size-cells = <0>;
 
-			dphy_rx0_out: endpoint {
+			dphy_rx_out: endpoint@0 {
+				reg = <0>;
 				remote-endpoint = <&isp_mipi_in>;
 			};
 		};
 	};
 };
 
+&rkisp1 {
+	status = "okay";
+	port {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		isp_mipi_in: endpoint@0 {
+			reg = <0>;
+			remote-endpoint = <&dphy_rx_out>;
+		};
+
+	};
+};
+
 &rga {
 	status = "okay";
 };
@@ -546,10 +543,6 @@
 	status = "okay";
 };
 
-&sound {
-	status = "okay";
-};
-
 &uart2 {
 	status = "disabled";
 };
diff --git a/arch/arm/boot/dts/rk3288-evb-rk808.dts b/arch/arm/boot/dts/rk3288-evb-rk808.dts
index 42384ea4ca21..e9f3cdf8fa4e 100644
--- a/arch/arm/boot/dts/rk3288-evb-rk808.dts
+++ b/arch/arm/boot/dts/rk3288-evb-rk808.dts
@@ -6,6 +6,22 @@
 / {
 	model = "Rockchip RK3288 EVB RK808";
 	compatible = "rockchip,rk3288-evb-rk808", "rockchip,rk3288";
+
+	sdio_pwrseq: sdio-pwrseq {
+		compatible = "mmc-pwrseq-simple";
+		clocks = <&rk808 1>;
+		clock-names = "ext_clock";
+		pinctrl-names = "default";
+		pinctrl-0 = <&wifi_enable_h>;
+
+		/*
+		 * On the module itself this is one of these (depending
+		 * on the actual card populated):
+		 * - SDIO_RESET_L_WL_REG_ON
+		 * - PDN (power down when low)
+		 */
+		reset-gpios = <&gpio4 28 GPIO_ACTIVE_LOW>;
+	};
 };
 
 &i2c0 {
diff --git a/arch/arm/boot/dts/rk3288-evb.dtsi b/arch/arm/boot/dts/rk3288-evb.dtsi
index 33c98c30a604..0b1cda728171 100644
--- a/arch/arm/boot/dts/rk3288-evb.dtsi
+++ b/arch/arm/boot/dts/rk3288-evb.dtsi
@@ -47,6 +47,45 @@
 		};
 	};
 
+	sound: sound {
+		compatible = "simple-audio-card";
+		simple-audio-card,format = "i2s";
+		simple-audio-card,name = "rockchip,rt5640-codec";
+		simple-audio-card,mclk-fs = <512>;
+		status = "okay";
+
+		simple-audio-card,dai-link@0 {
+			format = "i2s";
+			cpu {
+				sound-dai = <&i2s>;
+			};
+
+			codec {
+				sound-dai = <&rt5640>;
+			};
+		};
+
+		simple-audio-card,dai-link@1 {
+			format = "i2s";
+			cpu {
+				sound-dai = <&i2s>;
+			};
+
+			codec {
+				sound-dai = <&hdmi>;
+			};
+		};
+	};
+
+	hdmi_analog_sound: hdmi-analog-sound {
+		compatible = "rockchip,rk3288-hdmi-analog",
+			     "rockchip,rk3368-hdmi-analog";
+		rockchip,model = "rockchip,rt5640-codec";
+		rockchip,cpu = <&i2s>;
+		rockchip,codec = <&rt5640>, <&hdmi>;
+		status = "disabled";
+	};
+
 	backlight: backlight {
 		compatible = "pwm-backlight";
 		brightness-levels = <
@@ -97,10 +136,28 @@
 	};
 
 	panel: panel {
-		compatible = "lg,lp079qx1-sp0v";
+		compatible = "simple-panel";
 		backlight = <&backlight>;
 		enable-gpios = <&gpio7 RK_PA4 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
 		pinctrl-0 = <&lcd_cs>;
+		prepare-delay-ms = <120>;
+
+		panel-timing {
+			clock-frequency = <200000000>;
+			hactive = <1536>;
+			hfront-porch = <12>;
+			hback-porch = <48>;
+			hsync-len = <16>;
+			vactive = <2048>;
+			vfront-porch = <8>;
+			vback-porch = <8>;
+			vsync-len = <4>;
+			hsync-active = <0>;
+			vsync-active = <0>;
+			de-active = <0>;
+			pixelclk-active = <0>;
+		};
 
 		ports {
 			panel_in: port {
@@ -140,6 +197,15 @@
 		regulator-boot-on;
 	};
 
+	vcc_otg_vbus: otg-vbus-regulator {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&otg_vbus_drv>;
+		regulator-name = "vcc_otg_vbus";
+	};
+
 	vcc_phy: vcc-phy-regulator {
 		compatible = "regulator-fixed";
 		enable-active-high;
@@ -178,6 +244,27 @@
 		startup-delay-us = <100000>;
 		vin-supply = <&vcc_io>;
 	};
+
+	wireless-bluetooth {
+		compatible = "bluetooth-platdata";
+		uart_rts_gpios = <&gpio4 19 GPIO_ACTIVE_LOW>;
+		pinctrl-names = "default", "rts_gpio";
+		pinctrl-0 = <&uart0_rts>;
+		pinctrl-1 = <&uart0_gpios>;
+		BT,reset_gpio    = <&gpio4 29 GPIO_ACTIVE_HIGH>;
+		BT,wake_gpio     = <&gpio4 26 GPIO_ACTIVE_HIGH>;
+		BT,wake_host_irq = <&gpio4 31 GPIO_ACTIVE_HIGH>;
+		status = "okay";
+	};
+
+	wireless-wlan {
+		compatible = "wlan-platdata";
+		rockchip,grf = <&grf>;
+		wifi_chip_type = "ap6335";
+		sdio_vref = <1800>;
+		WIFI,host_wake_irq = <&gpio4 30 GPIO_ACTIVE_HIGH>;
+		status = "okay";
+	};
 };
 
 &cpu0 {
@@ -226,6 +313,10 @@
 &sdmmc {
 	bus-width = <4>;
 	cap-mmc-highspeed;
+	sd-uhs-sdr12;
+	sd-uhs-sdr25;
+	sd-uhs-sdr50;
+	sd-uhs-sdr104;
 	cap-sd-highspeed;
 	no-mmc;
 	no-sdio;
@@ -261,7 +352,6 @@
 };
 
 &hdmi {
-	ddc-i2c-bus = <&i2c5>;
 	status = "okay";
 };
 
@@ -269,7 +359,39 @@
 	status = "okay";
 };
 
-&i2c5 {
+&i2c2 {
+	status = "okay";
+
+	rt5640: rt5640@1c {
+		#sound-dai-cells = <0>;
+		compatible = "realtek,rt5640";
+		reg = <0x1c>;
+		clocks = <&cru SCLK_I2S0_OUT>;
+		clock-names = "mclk";
+		interrupt-parent = <&gpio7>;
+		interrupts = <7 IRQ_TYPE_EDGE_FALLING>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&i2s0_mclk>;
+	};
+};
+
+&i2c4 {
+	status = "okay";
+	clock-frequency = <400000>;
+
+	gsl3673@40 {
+		compatible = "GSL,GSL3673";
+		reg = <0x40>;
+		screen_max_x = <1536>;
+		screen_max_y = <2048>;
+		irq_gpio_number = <&gpio7 6 IRQ_TYPE_LEVEL_LOW>;
+		rst_gpio_number = <&gpio7 5 GPIO_ACTIVE_HIGH>;
+		status = "okay";
+	};
+};
+
+&i2s {
+	#sound-dai-cells = <0>;
 	status = "okay";
 };
 
@@ -281,11 +403,25 @@
 	status = "okay";
 };
 
-&uart0 {
+&sdio0 {
 	status = "okay";
+	max-frequency = <150000000>;
+	bus-width = <4>;
+	cap-sd-highspeed;
+	no-mmc;
+	no-sd;
+	cap-sdio-irq;
+	mmc-pwrseq = <&sdio_pwrseq>;
+	keep-power-in-suspend;
+	non-removable;
+	pinctrl-names = "default";
+	pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk &sdio0_int>;
+	sd-uhs-sdr104;
 };
 
-&uart1 {
+&uart0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart0_xfer &uart0_cts>;
 	status = "okay";
 };
 
@@ -293,14 +429,6 @@
 	status = "okay";
 };
 
-&uart3 {
-	status = "okay";
-};
-
-&uart4 {
-	status = "okay";
-};
-
 &tsadc {
 	rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */
 	rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */
@@ -341,6 +469,12 @@
 		};
 	};
 
+	sdio-pwrseq {
+		wifi_enable_h: wifi-enable-h {
+			rockchip,pins = <4 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
 	sdmmc {
 		/*
 		 * Default drive strength isn't enough to achieve even
@@ -370,6 +504,10 @@
 		host_vbus_drv: host-vbus-drv {
 			rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
 		};
+
+		otg_vbus_drv: otg-bus-drv {
+			rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
 	};
 
 	eth_phy {
@@ -377,6 +515,12 @@
 			rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
 		};
 	};
+
+	wireless-bluetooth {
+		uart0_gpios: uart0-gpios {
+			rockchip,pins = <4 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
 };
 
 &usbphy {
@@ -384,6 +528,11 @@
 };
 
 &usb_host0_ehci {
+	rockchip-relinquish-port;
+	status = "okay";
+};
+
+&usb_host0_ohci {
 	status = "okay";
 };
 
@@ -391,6 +540,11 @@
 	status = "okay";
 };
 
+&usb_otg {
+	vbus-supply = <&vcc_otg_vbus>;
+	status = "okay";
+};
+
 &vopb {
 	status = "okay";
 };
diff --git a/arch/arm/boot/dts/rk3288-firefly-rk808.dts b/arch/arm/boot/dts/rk3288-firefly-rk808.dts
index 0990c326f465..dc418937de2d 100644
--- a/arch/arm/boot/dts/rk3288-firefly-rk808.dts
+++ b/arch/arm/boot/dts/rk3288-firefly-rk808.dts
@@ -217,11 +217,6 @@
 		clock-names = "ext_clock";
 	};
 
-	psci {
-		compatible = "arm,psci-1.0";
-		method = "smc";
-	};
-
 	rk_key: rockchip-key {
 		compatible = "rockchip,key";
 		status = "okay";
@@ -632,22 +627,6 @@
 	status = "okay";
 };
 
-&cpu0 {
-	enable-method = "psci";
-};
-
-&cpu1 {
-	enable-method = "psci";
-};
-
-&cpu2 {
-	enable-method = "psci";
-};
-
-&cpu3 {
-	enable-method = "psci";
-};
-
 &dfi {
 	status = "okay";
 };
diff --git a/arch/arm/boot/dts/rk3288-linux.dtsi b/arch/arm/boot/dts/rk3288-linux.dtsi
index 80844a7c6a50..8262a19d8b52 100644
--- a/arch/arm/boot/dts/rk3288-linux.dtsi
+++ b/arch/arm/boot/dts/rk3288-linux.dtsi
@@ -8,7 +8,7 @@
 
 / {
 	chosen {
-		bootargs = "earlycon=uart8250,mmio32,0xff690000 vmalloc=496M rw root=PARTUUID=614e0000-0000 rootfstype=ext4 rootwait";
+		bootargs = "earlycon=uart8250,mmio32,0xff690000 console=ttyFIQ0 vmalloc=496M rw root=PARTUUID=614e0000-0000 rootfstype=ext4 rootwait";
 	};
 
 	/delete-node/ dmc@ff610000;
@@ -89,17 +89,12 @@
 		interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
 		rockchip,serial-id = <2>;
 		rockchip,wake-irq = <0>;
-		rockchip,irq-mode-enable = <0>; /* If enable uart uses irq instead of fiq */
+		rockchip,irq-mode-enable = <1>; /* If enable uart uses irq instead of fiq */
 		rockchip,baudrate = <115200>;  /* Only 115200 and 1500000 */
 		pinctrl-names = "default";
 		pinctrl-0 = <&uart2_xfer>;
 	};
 
-	psci {
-		compatible = "arm,psci-1.0";
-		method = "smc";
-	};
-
 	/delete-node/ timer@ff810000;
 
 	display-subsystem {
@@ -157,22 +152,6 @@
 	};
 };
 
-&cpu0 {
-	enable-method = "psci";
-};
-
-&cpu1 {
-	enable-method = "psci";
-};
-
-&cpu2 {
-	enable-method = "psci";
-};
-
-&cpu3 {
-	enable-method = "psci";
-};
-
 &dmac_bus_s {
 	/* change to non-secure dmac */
 	reg = <0x0 0xff600000 0x0 0x4000>;
@@ -194,6 +173,25 @@
 	status = "okay";
 };
 
+&iep {
+	status = "okay";
+};
+
+&iep_mmu {
+	status = "okay";
+};
+
+&rga {
+	compatible = "rockchip,rga2";
+	clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>;
+	clock-names = "aclk_rga", "hclk_rga", "clk_rga";
+	status = "okay";
+};
+
+&rng {
+	status = "okay";
+};
+
 &uart2 {
 	status = "disabled";
 };
diff --git a/arch/arm/boot/dts/rk3288-pinctrl.dtsi b/arch/arm/boot/dts/rk3288-pinctrl.dtsi
new file mode 100644
index 000000000000..42882bbfbc4d
--- /dev/null
+++ b/arch/arm/boot/dts/rk3288-pinctrl.dtsi
@@ -0,0 +1,678 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2022 Rockchip Electronics Co., Ltd.
+ */
+
+#include <dt-bindings/pinctrl/rockchip.h>
+#include "rockchip-pinconf.dtsi"
+
+&pinctrl {
+	hdmi {
+		hdmi_gpio: hdmi-gpio {
+			rockchip,pins =
+				<7 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>,
+				<7 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		hdmi_cec_c0: hdmi-cec-c0 {
+			rockchip,pins =
+				<7 RK_PC0 2 &pcfg_pull_none>;
+		};
+
+		hdmi_cec_c7: hdmi-cec-c7 {
+			rockchip,pins =
+				<7 RK_PC7 4 &pcfg_pull_none>;
+		};
+
+		hdmi_ddc: hdmi-ddc {
+			rockchip,pins =
+				<7 RK_PC3 2 &pcfg_pull_none>,
+				<7 RK_PC4 2 &pcfg_pull_none>;
+		};
+
+		hdmi_ddc_unwedge: hdmi-ddc-unwedge {
+			rockchip,pins =
+				<7 RK_PC3 RK_FUNC_GPIO &pcfg_output_low>,
+				<7 RK_PC4 2 &pcfg_pull_none>;
+		};
+	};
+
+	suspend {
+		global_pwroff: global-pwroff {
+			rockchip,pins =
+				<0 RK_PA0 1 &pcfg_pull_none>;
+		};
+
+		ddrio_pwroff: ddrio-pwroff {
+			rockchip,pins =
+				<0 RK_PA1 1 &pcfg_pull_none>;
+		};
+
+		ddr0_retention: ddr0-retention {
+			rockchip,pins =
+				<0 RK_PA2 1 &pcfg_pull_up>;
+		};
+
+		ddr1_retention: ddr1-retention {
+			rockchip,pins =
+				<0 RK_PA3 1 &pcfg_pull_up>;
+		};
+	};
+
+	edp {
+		edp_hpd: edp-hpd {
+			rockchip,pins =
+				<7 RK_PB3 2 &pcfg_pull_down>;
+		};
+	};
+
+	i2c0 {
+		i2c0_xfer: i2c0-xfer {
+			rockchip,pins =
+				<0 RK_PB7 1 &pcfg_pull_none>,
+				<0 RK_PC0 1 &pcfg_pull_none>;
+		};
+	};
+
+	i2c1 {
+		i2c1_xfer: i2c1-xfer {
+			rockchip,pins =
+				<8 RK_PA4 1 &pcfg_pull_none>,
+				<8 RK_PA5 1 &pcfg_pull_none>;
+		};
+	};
+
+	i2c2 {
+		i2c2_xfer: i2c2-xfer {
+			rockchip,pins =
+				<6 RK_PB1 1 &pcfg_pull_none>,
+				<6 RK_PB2 1 &pcfg_pull_none>;
+		};
+	};
+
+	i2c3 {
+		i2c3_xfer: i2c3-xfer {
+			rockchip,pins =
+				<2 RK_PC0 1 &pcfg_pull_none>,
+				<2 RK_PC1 1 &pcfg_pull_none>;
+		};
+	};
+
+	i2c4 {
+		i2c4_xfer: i2c4-xfer {
+			rockchip,pins =
+				<7 RK_PC1 1 &pcfg_pull_none>,
+				<7 RK_PC2 1 &pcfg_pull_none>;
+		};
+	};
+
+	i2c5 {
+		i2c5_xfer: i2c5-xfer {
+			rockchip,pins =
+				<7 RK_PC3 1 &pcfg_pull_none>,
+				<7 RK_PC4 1 &pcfg_pull_none>;
+		};
+	};
+
+	i2s0 {
+		i2s0_bus: i2s0-bus {
+			rockchip,pins =
+				<6 RK_PA0 1 &pcfg_pull_none>,
+				<6 RK_PA1 1 &pcfg_pull_none>,
+				<6 RK_PA2 1 &pcfg_pull_none>,
+				<6 RK_PA3 1 &pcfg_pull_none>,
+				<6 RK_PA4 1 &pcfg_pull_none>;
+		};
+
+		i2s0_mclk: i2s0-mclk {
+			rockchip,pins =
+				<6 RK_PB0 1 &pcfg_pull_none>;
+		};
+	};
+
+	lcdc {
+		lcdc_rgb_pins: lcdc-rgb-pins {
+			rockchip,pins =
+				<1 RK_PD3 1 &pcfg_pull_none>, /* LCDC_DCLK */
+				<1 RK_PD2 1 &pcfg_pull_none>, /* LCDC_DEN */
+				<1 RK_PD1 1 &pcfg_pull_none>, /* LCDC_VSYNC */
+				<1 RK_PD0 1 &pcfg_pull_none>; /* LCDC_HSYNC */
+		};
+
+		lcdc_sleep_pins: lcdc-sleep-pins {
+			rockchip,pins =
+				<1 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_DCLK */
+				<1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_DEN */
+				<1 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_VSYNC */
+				<1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; /* LCDC_HSYNC */
+		};
+	};
+
+	sdmmc {
+		sdmmc_clk: sdmmc-clk {
+			rockchip,pins =
+				<6 RK_PC4 1 &pcfg_pull_none>;
+		};
+
+		sdmmc_cmd: sdmmc-cmd {
+			rockchip,pins =
+				<6 RK_PC5 1 &pcfg_pull_up>;
+		};
+
+		sdmmc_cd: sdmmc-cd {
+			rockchip,pins =
+				<6 RK_PC6 1 &pcfg_pull_up>;
+		};
+
+		sdmmc_bus1: sdmmc-bus1 {
+			rockchip,pins =
+				<6 RK_PC0 1 &pcfg_pull_up>;
+		};
+
+		sdmmc_bus4: sdmmc-bus4 {
+			rockchip,pins =
+				<6 RK_PC0 1 &pcfg_pull_up>,
+				<6 RK_PC1 1 &pcfg_pull_up>,
+				<6 RK_PC2 1 &pcfg_pull_up>,
+				<6 RK_PC3 1 &pcfg_pull_up>;
+		};
+	};
+
+	sdio0 {
+		sdio0_bus1: sdio0-bus1 {
+			rockchip,pins =
+				<4 RK_PC4 1 &pcfg_pull_up>;
+		};
+
+		sdio0_bus4: sdio0-bus4 {
+			rockchip,pins =
+				<4 RK_PC4 1 &pcfg_pull_up>,
+				<4 RK_PC5 1 &pcfg_pull_up>,
+				<4 RK_PC6 1 &pcfg_pull_up>,
+				<4 RK_PC7 1 &pcfg_pull_up>;
+		};
+
+		sdio0_cmd: sdio0-cmd {
+			rockchip,pins =
+				<4 RK_PD0 1 &pcfg_pull_up>;
+		};
+
+		sdio0_clk: sdio0-clk {
+			rockchip,pins =
+				<4 RK_PD1 1 &pcfg_pull_none>;
+		};
+
+		sdio0_cd: sdio0-cd {
+			rockchip,pins =
+				<4 RK_PD2 1 &pcfg_pull_up>;
+		};
+
+		sdio0_wp: sdio0-wp {
+			rockchip,pins =
+				<4 RK_PD3 1 &pcfg_pull_up>;
+		};
+
+		sdio0_pwr: sdio0-pwr {
+			rockchip,pins =
+				<4 RK_PD4 1 &pcfg_pull_up>;
+		};
+
+		sdio0_bkpwr: sdio0-bkpwr {
+			rockchip,pins =
+				<4 RK_PD5 1 &pcfg_pull_up>;
+		};
+
+		sdio0_int: sdio0-int {
+			rockchip,pins =
+				<4 RK_PD6 1 &pcfg_pull_up>;
+		};
+	};
+
+	sdio1 {
+		sdio1_bus1: sdio1-bus1 {
+			rockchip,pins =
+				<3 RK_PD0 4 &pcfg_pull_up>;
+		};
+
+		sdio1_bus4: sdio1-bus4 {
+			rockchip,pins =
+				<3 RK_PD0 4 &pcfg_pull_up>,
+				<3 RK_PD1 4 &pcfg_pull_up>,
+				<3 RK_PD2 4 &pcfg_pull_up>,
+				<3 RK_PD3 4 &pcfg_pull_up>;
+		};
+
+		sdio1_cd: sdio1-cd {
+			rockchip,pins =
+				<3 RK_PD4 4 &pcfg_pull_up>;
+		};
+
+		sdio1_wp: sdio1-wp {
+			rockchip,pins =
+				<3 RK_PD5 4 &pcfg_pull_up>;
+		};
+
+		sdio1_bkpwr: sdio1-bkpwr {
+			rockchip,pins =
+				<3 RK_PD6 4 &pcfg_pull_up>;
+		};
+
+		sdio1_int: sdio1-int {
+			rockchip,pins =
+				<3 RK_PD7 4 &pcfg_pull_up>;
+		};
+
+		sdio1_cmd: sdio1-cmd {
+			rockchip,pins =
+				<4 RK_PA6 4 &pcfg_pull_up>;
+		};
+
+		sdio1_clk: sdio1-clk {
+			rockchip,pins =
+				<4 RK_PA7 4 &pcfg_pull_none>;
+		};
+
+		sdio1_pwr: sdio1-pwr {
+			rockchip,pins =
+				<4 RK_PB1 4 &pcfg_pull_up>;
+		};
+	};
+
+	emmc {
+		emmc_clk: emmc-clk {
+			rockchip,pins =
+				<3 RK_PC2 2 &pcfg_pull_none>;
+		};
+
+		emmc_cmd: emmc-cmd {
+			rockchip,pins =
+				<3 RK_PC0 2 &pcfg_pull_up>;
+		};
+
+		emmc_pwr: emmc-pwr {
+			rockchip,pins =
+				<3 RK_PB1 2 &pcfg_pull_up>;
+		};
+
+		emmc_bus1: emmc-bus1 {
+			rockchip,pins =
+				<3 RK_PA0 2 &pcfg_pull_up>;
+		};
+
+		emmc_bus4: emmc-bus4 {
+			rockchip,pins =
+				<3 RK_PA0 2 &pcfg_pull_up>,
+				<3 RK_PA1 2 &pcfg_pull_up>,
+				<3 RK_PA2 2 &pcfg_pull_up>,
+				<3 RK_PA3 2 &pcfg_pull_up>;
+		};
+
+		emmc_bus8: emmc-bus8 {
+			rockchip,pins =
+				<3 RK_PA0 2 &pcfg_pull_up>,
+				<3 RK_PA1 2 &pcfg_pull_up>,
+				<3 RK_PA2 2 &pcfg_pull_up>,
+				<3 RK_PA3 2 &pcfg_pull_up>,
+				<3 RK_PA4 2 &pcfg_pull_up>,
+				<3 RK_PA5 2 &pcfg_pull_up>,
+				<3 RK_PA6 2 &pcfg_pull_up>,
+				<3 RK_PA7 2 &pcfg_pull_up>;
+		};
+	};
+
+	spi0 {
+		spi0_clk: spi0-clk {
+			rockchip,pins =
+				<5 RK_PB4 1 &pcfg_pull_up>;
+		};
+		spi0_cs0: spi0-cs0 {
+			rockchip,pins =
+				<5 RK_PB5 1 &pcfg_pull_up>;
+		};
+		spi0_tx: spi0-tx {
+			rockchip,pins =
+				<5 RK_PB6 1 &pcfg_pull_up>;
+		};
+		spi0_rx: spi0-rx {
+			rockchip,pins =
+				<5 RK_PB7 1 &pcfg_pull_up>;
+		};
+		spi0_cs1: spi0-cs1 {
+			rockchip,pins =
+				<5 RK_PC0 1 &pcfg_pull_up>;
+		};
+	};
+	spi1 {
+		spi1_clk: spi1-clk {
+			rockchip,pins =
+				<7 RK_PB4 2 &pcfg_pull_up>;
+		};
+		spi1_cs0: spi1-cs0 {
+			rockchip,pins =
+				<7 RK_PB5 2 &pcfg_pull_up>;
+		};
+		spi1_rx: spi1-rx {
+			rockchip,pins =
+				<7 RK_PB6 2 &pcfg_pull_up>;
+		};
+		spi1_tx: spi1-tx {
+			rockchip,pins =
+				<7 RK_PB7 2 &pcfg_pull_up>;
+		};
+	};
+
+	spi2 {
+		spi2_cs1: spi2-cs1 {
+			rockchip,pins =
+				<8 RK_PA3 1 &pcfg_pull_up>;
+		};
+		spi2_clk: spi2-clk {
+			rockchip,pins =
+				<8 RK_PA6 1 &pcfg_pull_up>;
+		};
+		spi2_cs0: spi2-cs0 {
+			rockchip,pins =
+				<8 RK_PA7 1 &pcfg_pull_up>;
+		};
+		spi2_rx: spi2-rx {
+			rockchip,pins =
+				<8 RK_PB0 1 &pcfg_pull_up>;
+		};
+		spi2_tx: spi2-tx {
+			rockchip,pins =
+				<8 RK_PB1 1 &pcfg_pull_up>;
+		};
+	};
+
+	uart0 {
+		uart0_xfer: uart0-xfer {
+			rockchip,pins =
+				<4 RK_PC0 1 &pcfg_pull_up>,
+				<4 RK_PC1 1 &pcfg_pull_up>;
+		};
+
+		uart0_cts: uart0-cts {
+			rockchip,pins =
+				<4 RK_PC2 1 &pcfg_pull_up>;
+		};
+
+		uart0_rts: uart0-rts {
+			rockchip,pins =
+				<4 RK_PC3 1 &pcfg_pull_none>;
+		};
+	};
+
+	uart1 {
+		uart1_xfer: uart1-xfer {
+			rockchip,pins =
+				<5 RK_PB0 1 &pcfg_pull_up>,
+				<5 RK_PB1 1 &pcfg_pull_up>;
+		};
+
+		uart1_cts: uart1-cts {
+			rockchip,pins =
+				<5 RK_PB2 1 &pcfg_pull_up>;
+		};
+
+		uart1_rts: uart1-rts {
+			rockchip,pins =
+				<5 RK_PB3 1 &pcfg_pull_none>;
+		};
+	};
+
+	uart2 {
+		uart2_xfer: uart2-xfer {
+			rockchip,pins =
+				<7 RK_PC6 1 &pcfg_pull_up>,
+				<7 RK_PC7 1 &pcfg_pull_up>;
+		};
+		/* no rts / cts for uart2 */
+	};
+
+	uart3 {
+		uart3_xfer: uart3-xfer {
+			rockchip,pins =
+				<7 RK_PA7 1 &pcfg_pull_up>,
+				<7 RK_PB0 1 &pcfg_pull_up>;
+		};
+
+		uart3_cts: uart3-cts {
+			rockchip,pins =
+				<7 RK_PB1 1 &pcfg_pull_up>;
+		};
+
+		uart3_rts: uart3-rts {
+			rockchip,pins =
+				<7 RK_PB2 1 &pcfg_pull_none>;
+		};
+	};
+
+	uart4 {
+		uart4_xfer: uart4-xfer {
+			rockchip,pins =
+				<5 RK_PB7 3 &pcfg_pull_up>,
+				<5 RK_PB6 3 &pcfg_pull_up>;
+		};
+
+		uart4_cts: uart4-cts {
+			rockchip,pins =
+				<5 RK_PB4 3 &pcfg_pull_up>;
+		};
+
+		uart4_rts: uart4-rts {
+			rockchip,pins =
+				<5 RK_PB5 3 &pcfg_pull_none>;
+		};
+	};
+
+	tsadc {
+		otp_pin: otp-pin {
+			rockchip,pins =
+				<0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		otp_out: otp-out {
+			rockchip,pins =
+				<0 RK_PB2 1 &pcfg_pull_none>;
+		};
+	};
+
+	pwm0 {
+		pwm0_pin: pwm0-pin {
+			rockchip,pins =
+				<7 RK_PA0 1 &pcfg_pull_none>;
+		};
+
+		pwm0_pin_pull_down: pwm0-pin-pull-down {
+			rockchip,pins =
+				<7 RK_PA0 1 &pcfg_pull_down>;
+		};
+
+	};
+
+	pwm1 {
+		pwm1_pin: pwm1-pin {
+			rockchip,pins =
+				<7 RK_PA1 1 &pcfg_pull_none>;
+		};
+
+		pwm1_pin_pull_down: pwm1-pin-pull-down {
+			rockchip,pins =
+				<7 RK_PA1 1 &pcfg_pull_down>;
+		};
+	};
+
+	pwm2 {
+		pwm2_pin: pwm2-pin {
+			rockchip,pins =
+				<7 RK_PC6 3 &pcfg_pull_none>;
+		};
+
+		pwm2_pin_pull_down: pwm2-pin-pull-down {
+			rockchip,pins =
+				<7 RK_PC6 3 &pcfg_pull_down>;
+		};
+	};
+
+	pwm3 {
+		pwm3_pin: pwm3-pin {
+			rockchip,pins =
+				<7 RK_PC7 3 &pcfg_pull_none>;
+		};
+
+		pwm3_pin_pull_down: pwm3-pin-pull-down {
+			rockchip,pins =
+				<7 RK_PC7 3 &pcfg_pull_down>;
+		};
+	};
+
+	gmac {
+		rgmii_pins: rgmii-pins {
+			rockchip,pins =
+				<3 RK_PD6 3 &pcfg_pull_none>,
+				<3 RK_PD7 3 &pcfg_pull_none>,
+				<3 RK_PD2 3 &pcfg_pull_none>,
+				<3 RK_PD3 3 &pcfg_pull_none>,
+				<3 RK_PD4 3 &pcfg_pull_none_drv_level_12>,
+				<3 RK_PD5 3 &pcfg_pull_none_drv_level_12>,
+				<3 RK_PD0 3 &pcfg_pull_none_drv_level_12>,
+				<3 RK_PD1 3 &pcfg_pull_none_drv_level_12>,
+				<4 RK_PA0 3 &pcfg_pull_none>,
+				<4 RK_PA5 3 &pcfg_pull_none>,
+				<4 RK_PA6 3 &pcfg_pull_none>,
+				<4 RK_PB1 3 &pcfg_pull_none_drv_level_12>,
+				<4 RK_PA4 3 &pcfg_pull_none_drv_level_12>,
+				<4 RK_PA1 3 &pcfg_pull_none>,
+				<4 RK_PA3 3 &pcfg_pull_none>;
+		};
+
+		rmii_pins: rmii-pins {
+			rockchip,pins =
+				<3 RK_PD6 3 &pcfg_pull_none>,
+				<3 RK_PD7 3 &pcfg_pull_none>,
+				<3 RK_PD4 3 &pcfg_pull_none>,
+				<3 RK_PD5 3 &pcfg_pull_none>,
+				<4 RK_PA0 3 &pcfg_pull_none>,
+				<4 RK_PA5 3 &pcfg_pull_none>,
+				<4 RK_PA4 3 &pcfg_pull_none>,
+				<4 RK_PA1 3 &pcfg_pull_none>,
+				<4 RK_PA2 3 &pcfg_pull_none>,
+				<4 RK_PA3 3 &pcfg_pull_none>;
+		};
+	};
+
+	spdif {
+		spdif_tx: spdif-tx {
+			rockchip,pins =
+				<6 RK_PB3 1 &pcfg_pull_none>;
+		};
+	};
+
+	isp_pin {
+		isp_mipi: isp-mipi {
+			rockchip,pins =
+				/* cif_clkout */
+				<2 RK_PB3 1 &pcfg_pull_none>;
+		};
+
+		isp_dvp_d2d9: isp-d2d9 {
+			rockchip,pins =
+				/* cif_data2 ... cif_data9 */
+				<2 RK_PA0 1 &pcfg_pull_none>,
+				<2 RK_PA1 1 &pcfg_pull_none>,
+				<2 RK_PA2 1 &pcfg_pull_none>,
+				<2 RK_PA3 1 &pcfg_pull_none>,
+				<2 RK_PA4 1 &pcfg_pull_none>,
+				<2 RK_PA5 1 &pcfg_pull_none>,
+				<2 RK_PA6 1 &pcfg_pull_none>,
+				<2 RK_PA7 1 &pcfg_pull_none>,
+				/* cif_sync, cif_href */
+				<2 RK_PB0 1 &pcfg_pull_none>,
+				<2 RK_PB1 1 &pcfg_pull_none>,
+				/* cif_clkin */
+				<2 RK_PB2 1 &pcfg_pull_none>;
+		};
+
+		isp_dvp_d0d1: isp-d0d1 {
+			rockchip,pins =
+				/* cif_data0, cif_data1 */
+				<2 RK_PB4 1 &pcfg_pull_none>,
+				<2 RK_PB5 1 &pcfg_pull_none>;
+		};
+
+		isp_dvp_d10d11: isp-d10d11 {
+			rockchip,pins =
+				/* cif_data10, cif_data11 */
+				<2 RK_PB6 1 &pcfg_pull_none>,
+				<2 RK_PB7 1 &pcfg_pull_none>;
+		};
+
+		isp_dvp_d0d7: isp-d0d7 {
+			rockchip,pins =
+				/* cif_data0 ... cif_data7 */
+				<2 RK_PB4 1 &pcfg_pull_none>,
+				<2 RK_PB5 1 &pcfg_pull_none>,
+				<2 RK_PA0 1 &pcfg_pull_none>,
+				<2 RK_PA1 1 &pcfg_pull_none>,
+				<2 RK_PA2 1 &pcfg_pull_none>,
+				<2 RK_PA3 1 &pcfg_pull_none>,
+				<2 RK_PA4 1 &pcfg_pull_none>,
+				<2 RK_PA5 1 &pcfg_pull_none>;
+		};
+
+		isp_shutter: isp-shutter {
+			rockchip,pins =
+				/* SHUTTEREN, SHUTTERTRIG */
+				<7 RK_PB4 2 &pcfg_pull_none>,
+				<7 RK_PB7 2 &pcfg_pull_none>;
+		};
+
+		isp_flash_trigger: isp-flash-trigger {
+			rockchip,pins =
+				/* ISP_FLASHTRIGOU */
+				<7 RK_PB5 2 &pcfg_pull_none>;
+		};
+
+		isp_prelight: isp-prelight {
+			rockchip,pins =
+				/* ISP_PRELIGHTTRIG */
+				<7 RK_PB6 2 &pcfg_pull_none>;
+		};
+
+		isp_flash_trigger_as_gpio: isp-flash-trigger-as-gpio {
+			rockchip,pins =
+				/* ISP_FLASHTRIGOU */
+				<7 RK_PB5 2 &pcfg_pull_none>;
+		};
+	};
+
+	cif_pin {
+		cif_dvp_d0d1: cif-dvp-d0d1 {
+			rockchip,pins =
+				<2 RK_PB4 1 &pcfg_pull_none>, /* cif_data0 */
+				<2 RK_PB5 1 &pcfg_pull_none>; /* cif_data1 */
+		};
+
+		cif_dvp_d2d9: cif-dvp-d2d9 {
+			rockchip,pins =
+				<2 RK_PA0 1 &pcfg_pull_none>, /* cif_data2 */
+				<2 RK_PA1 1 &pcfg_pull_none>, /* cif_data3 */
+				<2 RK_PA2 1 &pcfg_pull_none>, /* cif_data4 */
+				<2 RK_PA3 1 &pcfg_pull_none>, /* cif_data5 */
+				<2 RK_PA4 1 &pcfg_pull_none>, /* cif_data6 */
+				<2 RK_PA5 1 &pcfg_pull_none>, /* cif_data7 */
+				<2 RK_PA6 1 &pcfg_pull_none>, /* cif_data8 */
+				<2 RK_PA7 1 &pcfg_pull_none>, /* cif_data9 */
+				<2 RK_PB0 1 &pcfg_pull_none>, /* cif_sync */
+				<2 RK_PB1 1 &pcfg_pull_none>, /* cif_href */
+				<2 RK_PB2 1 &pcfg_pull_none>, /* cif_clkin */
+				<2 RK_PB3 1 &pcfg_pull_none>; /* cif_clkout */
+		};
+
+		cif_dvp_d10d11: cif-dvp-d10d11 {
+			rockchip,pins =
+				<2 RK_PB6 1 &pcfg_pull_none>, /* cif_data10 */
+				<2 RK_PB7 1 &pcfg_pull_none>; /* cif_data11 */
+		};
+	};
+};
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index 078c151ee854..2ed45b0d03d2 100644
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -8,6 +8,7 @@
 #include <dt-bindings/power/rk3288-power.h>
 #include <dt-bindings/thermal/thermal.h>
 #include <dt-bindings/soc/rockchip,boot-mode.h>
+#include <dt-bindings/suspend/rockchip-rk3288.h>
 
 / {
 	#address-cells = <2>;
@@ -18,6 +19,8 @@
 	interrupt-parent = <&gic>;
 
 	aliases {
+		dsi0 = &dsi0;
+		dsi1 = &dsi1;
 		ethernet0 = &gmac;
 		gpio0 = &gpio0;
 		gpio1 = &gpio1;
@@ -57,6 +60,11 @@
 		interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
 	};
 
+	psci {
+		compatible = "arm,psci-1.0";
+		method = "smc";
+	};
+
 	cpus {
 		#address-cells = <1>;
 		#size-cells = <0>;
@@ -67,6 +75,7 @@
 			device_type = "cpu";
 			compatible = "arm,cortex-a12";
 			reg = <0x500>;
+			enable-method = "psci";
 			resets = <&cru SRST_CORE0>;
 			operating-points-v2 = <&cpu_opp_table>;
 			#cooling-cells = <2>; /* min followed by max */
@@ -78,6 +87,7 @@
 			device_type = "cpu";
 			compatible = "arm,cortex-a12";
 			reg = <0x501>;
+			enable-method = "psci";
 			resets = <&cru SRST_CORE1>;
 			operating-points-v2 = <&cpu_opp_table>;
 			#cooling-cells = <2>; /* min followed by max */
@@ -89,6 +99,7 @@
 			device_type = "cpu";
 			compatible = "arm,cortex-a12";
 			reg = <0x502>;
+			enable-method = "psci";
 			resets = <&cru SRST_CORE2>;
 			operating-points-v2 = <&cpu_opp_table>;
 			#cooling-cells = <2>; /* min followed by max */
@@ -100,6 +111,7 @@
 			device_type = "cpu";
 			compatible = "arm,cortex-a12";
 			reg = <0x503>;
+			enable-method = "psci";
 			resets = <&cru SRST_CORE3>;
 			operating-points-v2 = <&cpu_opp_table>;
 			#cooling-cells = <2>; /* min followed by max */
@@ -113,53 +125,136 @@
 		compatible = "operating-points-v2";
 		opp-shared;
 
+		clocks = <&cru PLL_APLL>;
+		rockchip,avs-scale = <17>;
+		rockchip,max-volt = <1350000>;
+		nvmem-cells = <&cpu_leakage>, <&special_function>,
+			      <&performance>, <&process_version>,
+			      <&performance_w>, <&package_info>;
+		nvmem-cell-names = "leakage", "special",
+				   "performance", "process",
+				   "performance-w", "package";
+		rockchip,bin-scaling-sel = <
+			0               17
+			1               25
+			2               27
+			3               31
+		>;
+		rockchip,pvtm-voltage-sel = <
+			0        15300   0
+			15301    16000   1
+			16001    17000   2
+			17001    99999   3
+		>;
+		rockchip,pvtm-freq = <408000>;
+		rockchip,pvtm-volt = <1000000>;
+		rockchip,pvtm-ch = <0 0>;
+		rockchip,pvtm-sample-time = <1000>;
+		rockchip,pvtm-number = <10>;
+		rockchip,pvtm-error = <1000>;
+		rockchip,pvtm-ref-temp = <35>;
+		rockchip,pvtm-temp-prop = <(-18) (-18)>;
+		rockchip,thermal-zone = "soc-thermal";
+
 		opp-126000000 {
 			opp-hz = /bits/ 64 <126000000>;
-			opp-microvolt = <900000>;
+			opp-microvolt = <950000 950000 1350000>;
+			opp-microvolt-L0 = <950000 950000 1350000>;
+			opp-microvolt-L1 = <950000 950000 1350000>;
+			opp-microvolt-L2 = <950000 950000 1350000>;
+			opp-microvolt-L3 = <950000 950000 1350000>;
+			clock-latency-ns = <40000>;
 		};
 		opp-216000000 {
 			opp-hz = /bits/ 64 <216000000>;
-			opp-microvolt = <900000>;
-		};
-		opp-312000000 {
-			opp-hz = /bits/ 64 <312000000>;
-			opp-microvolt = <900000>;
+			opp-microvolt = <950000 950000 1350000>;
+			opp-microvolt-L0 = <950000 950000 1350000>;
+			opp-microvolt-L1 = <950000 950000 1350000>;
+			opp-microvolt-L2 = <950000 950000 1350000>;
+			opp-microvolt-L3 = <950000 950000 1350000>;
+			clock-latency-ns = <40000>;
 		};
 		opp-408000000 {
 			opp-hz = /bits/ 64 <408000000>;
-			opp-microvolt = <900000>;
+			opp-microvolt = <975000 975000 1350000>;
+			opp-microvolt-L0 = <975000 975000 1350000>;
+			opp-microvolt-L1 = <950000 950000 1350000>;
+			opp-microvolt-L2 = <950000 950000 1350000>;
+			opp-microvolt-L3 = <950000 950000 1350000>;
+			clock-latency-ns = <40000>;
 		};
 		opp-600000000 {
 			opp-hz = /bits/ 64 <600000000>;
-			opp-microvolt = <900000>;
+			opp-microvolt = <975000 975000 1350000>;
+			opp-microvolt-L0 = <975000 975000 1350000>;
+			opp-microvolt-L1 = <950000 950000 1350000>;
+			opp-microvolt-L2 = <950000 950000 1350000>;
+			opp-microvolt-L3 = <950000 950000 1350000>;
+			clock-latency-ns = <40000>;
 		};
 		opp-696000000 {
 			opp-hz = /bits/ 64 <696000000>;
-			opp-microvolt = <950000>;
+			opp-microvolt = <975000 975000 1350000>;
+			opp-microvolt-L0 = <975000 975000 1350000>;
+			opp-microvolt-L1 = <950000 950000 1350000>;
+			opp-microvolt-L2 = <950000 950000 1350000>;
+			opp-microvolt-L3 = <950000 950000 1350000>;
+			clock-latency-ns = <40000>;
 		};
 		opp-816000000 {
 			opp-hz = /bits/ 64 <816000000>;
-			opp-microvolt = <1000000>;
+			opp-microvolt = <1075000 1075000 1350000>;
+			opp-microvolt-L0 = <1075000 1075000 1350000>;
+			opp-microvolt-L1 = <1050000 1050000 1350000>;
+			opp-microvolt-L2 = <1000000 1000000 1350000>;
+			opp-microvolt-L3 = <950000 950000 1350000>;
+			clock-latency-ns = <40000>;
+			opp-suspend;
 		};
 		opp-1008000000 {
 			opp-hz = /bits/ 64 <1008000000>;
-			opp-microvolt = <1050000>;
+			opp-microvolt = <1150000 1150000 1350000>;
+			opp-microvolt-L0 = <1150000 1150000 1350000>;
+			opp-microvolt-L1 = <1100000 1100000 1350000>;
+			opp-microvolt-L2 = <1050000 1050000 1350000>;
+			opp-microvolt-L3 = <1000000 1000000 1350000>;
+			clock-latency-ns = <40000>;
 		};
 		opp-1200000000 {
 			opp-hz = /bits/ 64 <1200000000>;
-			opp-microvolt = <1100000>;
+			opp-microvolt = <1200000 1200000 1350000>;
+			opp-microvolt-L0 = <1200000 1200000 1350000>;
+			opp-microvolt-L1 = <1150000 1150000 1350000>;
+			opp-microvolt-L2 = <1100000 1100000 1350000>;
+			opp-microvolt-L3 = <1050000 1050000 1350000>;
+			clock-latency-ns = <40000>;
 		};
 		opp-1416000000 {
 			opp-hz = /bits/ 64 <1416000000>;
-			opp-microvolt = <1200000>;
+			opp-microvolt = <1300000 1300000 1350000>;
+			opp-microvolt-L0 = <1300000 1300000 1350000>;
+			opp-microvolt-L1 = <1250000 1250000 1350000>;
+			opp-microvolt-L2 = <1200000 1200000 1350000>;
+			opp-microvolt-L3 = <1150000 1150000 1350000>;
+			clock-latency-ns = <40000>;
 		};
 		opp-1512000000 {
 			opp-hz = /bits/ 64 <1512000000>;
-			opp-microvolt = <1300000>;
+			opp-microvolt = <1350000 1350000 1350000>;
+			opp-microvolt-L0 = <1350000 1350000 1350000>;
+			opp-microvolt-L1 = <1300000 1300000 1350000>;
+			opp-microvolt-L2 = <1250000 1250000 1350000>;
+			opp-microvolt-L3 = <1200000 1200000 1350000>;
+			clock-latency-ns = <40000>;
 		};
 		opp-1608000000 {
 			opp-hz = /bits/ 64 <1608000000>;
-			opp-microvolt = <1350000>;
+			opp-microvolt = <1350000 1350000 1350000>;
+			opp-microvolt-L0 = <1350000 1350000 1350000>;
+			opp-microvolt-L1 = <1350000 1350000 1350000>;
+			opp-microvolt-L2 = <1300000 1300000 1350000>;
+			opp-microvolt-L3 = <1250000 1250000 1350000>;
+			clock-latency-ns = <40000>;
 		};
 	};
 
@@ -207,6 +302,13 @@
 		};
 	};
 
+	firmware {
+		optee: optee {
+			compatible = "linaro,optee-tz";
+			method = "smc";
+		};
+	};
+
 	reserved-memory {
 		#address-cells = <2>;
 		#size-cells = <2>;
@@ -245,14 +347,6 @@
 		arm,no-tick-in-suspend;
 	};
 
-	timer: timer@ff810000 {
-		compatible = "rockchip,rk3288-timer";
-		reg = <0x0 0xff810000 0x0 0x20>;
-		interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&cru PCLK_TIMER>, <&xin24m>;
-		clock-names = "pclk", "timer";
-	};
-
 	display-subsystem {
 		compatible = "rockchip,display-subsystem";
 		ports = <&vopl_out>, <&vopb_out>;
@@ -561,7 +655,7 @@
 			};
 		};
 
-		gpu_thermal: gpu_thermal {
+		gpu_thermal: gpu-thermal {
 			polling-delay-passive = <100>; /* milliseconds */
 			polling-delay = <5000>; /* milliseconds */
 
@@ -596,6 +690,8 @@
 		interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 		clock-names = "tsadc", "apb_pclk";
+		assigned-clocks = <&cru SCLK_TSADC>;
+		assigned-clock-rates = <5000>;
 		resets = <&cru SRST_TSADC>;
 		reset-names = "tsadc-apb";
 		pinctrl-names = "gpio", "otpout";
@@ -629,9 +725,10 @@
 
 	usb_host0_ehci: usb@ff500000 {
 		compatible = "generic-ehci";
-		reg = <0x0 0xff500000 0x0 0x100>;
+		reg = <0x0 0xff500000 0x0 0x20000>;
 		interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&cru HCLK_USBHOST0>;
+		clocks = <&cru HCLK_USBHOST0>, <&usbphy1>;
+		clock-names = "usbhost", "utmi";
 		phys = <&usbphy1>;
 		phy-names = "usb";
 		status = "disabled";
@@ -642,7 +739,8 @@
 		compatible = "generic-ohci";
 		reg = <0x0 0xff520000 0x0 0x100>;
 		interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&cru HCLK_USBHOST0>;
+		clocks = <&cru HCLK_USBHOST0>, <&usbphy1>;
+		clock-names = "usbhost", "utmi";
 		phys = <&usbphy1>;
 		phy-names = "usb";
 		status = "disabled";
@@ -743,6 +841,14 @@
 		status = "disabled";
 	};
 
+	timer: timer@ff6b0000 {
+		compatible = "rockchip,rk3288-timer";
+		reg = <0x0 0xff6b0000 0x0 0x20>;
+		interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&cru PCLK_TIMER>, <&xin24m>;
+		clock-names = "pclk", "timer";
+	};
+
 	bus_intmem: sram@ff700000 {
 		compatible = "mmio-sram";
 		reg = <0x0 0xff700000 0x0 0x18000>;
@@ -820,6 +926,7 @@
 					 <&cru PCLK_MIPI_DSI1>,
 					 <&cru SCLK_EDP_24M>,
 					 <&cru SCLK_EDP>,
+					 <&cru SCLK_HDMI_CEC>,
 					 <&cru SCLK_ISP_JPE>,
 					 <&cru SCLK_ISP>,
 					 <&cru SCLK_RGA>;
@@ -893,16 +1000,16 @@
 		rockchip,grf = <&grf>;
 		#clock-cells = <1>;
 		#reset-cells = <1>;
-		assigned-clocks = <&cru PLL_GPLL>, <&cru PLL_CPLL>,
-				  <&cru PLL_NPLL>, <&cru ACLK_CPU>,
-				  <&cru HCLK_CPU>, <&cru PCLK_CPU>,
-				  <&cru ACLK_PERI>, <&cru HCLK_PERI>,
-				  <&cru PCLK_PERI>;
-		assigned-clock-rates = <594000000>, <400000000>,
-				       <500000000>, <300000000>,
-				       <150000000>, <75000000>,
+		assigned-clocks = <&cru PLL_GPLL>, <&cru PLL_NPLL>,
+				  <&cru ACLK_CPU>, <&cru HCLK_CPU>,
+				  <&cru PCLK_CPU>, <&cru ACLK_PERI>,
+				  <&cru HCLK_PERI>, <&cru PCLK_PERI>,
+				  <&cru ACLK_VIO0>, <&cru ACLK_VIO1>;
+		assigned-clock-rates = <594000000>, <500000000>,
 				       <300000000>, <150000000>,
-				       <75000000>;
+				       <75000000>, <300000000>,
+				       <150000000>, <75000000>,
+				       <594000000>, <297000000>;
 	};
 
 	grf: syscon@ff770000 {
@@ -922,6 +1029,72 @@
 			status = "disabled";
 		};
 
+		mipi_phy_rx0: mipi-phy-rx0 {
+			compatible = "rockchip,rk3288-mipi-dphy";
+			clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_MIPI_CSI>;
+			clock-names = "dphy-ref", "pclk";
+			status = "disabled";
+		};
+
+		lvds: lvds {
+			compatible = "rockchip,rk3288-lvds";
+			phys = <&video_phy>;
+			phy-names = "phy";
+			status = "disabled";
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					lvds_in_vopb: endpoint@0 {
+						reg = <0>;
+						remote-endpoint = <&vopb_out_lvds>;
+					};
+
+					lvds_in_vopl: endpoint@1 {
+						reg = <1>;
+						remote-endpoint = <&vopl_out_lvds>;
+					};
+				};
+			};
+		};
+
+		rgb: rgb {
+			compatible = "rockchip,rk3288-rgb";
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&lcdc_rgb_pins>;
+			pinctrl-1 = <&lcdc_sleep_pins>;
+			phys = <&video_phy>;
+			phy-names = "phy";
+			status = "disabled";
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					rgb_in_vopb: endpoint@0 {
+						reg = <0>;
+						remote-endpoint = <&vopb_out_rgb>;
+					};
+
+					rgb_in_vopl: endpoint@1 {
+						reg = <1>;
+						remote-endpoint = <&vopl_out_rgb>;
+					};
+				};
+			};
+		};
+
 		usbphy: usbphy {
 			compatible = "rockchip,rk3288-usb-phy";
 			#address-cells = <1>;
@@ -936,6 +1109,8 @@
 				#clock-cells = <0>;
 				resets = <&cru SRST_USBOTG_PHY>;
 				reset-names = "phy-reset";
+				interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-names = "otg-bvalid";
 			};
 
 			usbphy1: usb-phy@334 {
@@ -958,6 +1133,28 @@
 				reset-names = "phy-reset";
 			};
 		};
+
+		pvtm: pvtm {
+			compatible = "rockchip,rk3288-pvtm";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "okay";
+
+			pvtm@0 {
+				reg = <0>;
+				clocks = <&cru SCLK_PVTM_CORE>;
+				clock-names = "clk";
+				resets = <&cru SRST_CORE_PVTM>;
+				reset-names = "rst";
+			};
+			pvtm@1 {
+				reg = <1>;
+				clocks = <&cru SCLK_PVTM_GPU>;
+				clock-names = "clk";
+				resets = <&cru SRST_GPU_PVTM>;
+				reset-names = "rst";
+			};
+		};
 	};
 
 	wdt: watchdog@ff800000 {
@@ -968,13 +1165,13 @@
 		status = "disabled";
 	};
 
-	spdif: sound@ff88b0000 {
+	spdif_2ch: sound@ff880000 {
 		compatible = "rockchip,rk3288-spdif", "rockchip,rk3066-spdif";
-		reg = <0x0 0xff8b0000 0x0 0x10000>;
+		reg = <0x0 0xff880000 0x0 0x10000>;
 		#sound-dai-cells = <0>;
-		clocks = <&cru SCLK_SPDIF8CH>, <&cru HCLK_SPDIF8CH>;
+		clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF>;
 		clock-names = "mclk", "hclk";
-		dmas = <&dmac_bus_s 3>;
+		dmas = <&dmac_bus_s 2>;
 		dma-names = "tx";
 		interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 		pinctrl-names = "default";
@@ -990,6 +1187,8 @@
 		interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0>;
 		clock-names = "i2s_clk", "i2s_hclk";
+		assigned-clocks = <&cru SCLK_I2S_SRC>;
+		assigned-clock-parents = <&cru PLL_GPLL>;
 		dmas = <&dmac_bus_s 0>, <&dmac_bus_s 1>;
 		dma-names = "tx", "rx";
 		pinctrl-names = "default";
@@ -1001,6 +1200,16 @@
 		status = "disabled";
 	};
 
+	rng: rng@ff8a0000 {
+		compatible = "rockchip,cryptov1-rng";
+		reg = <0x0 0xff8a0000 0x0 0x4000>;
+		clocks = <&cru SCLK_CRYPTO>, <&cru HCLK_CRYPTO>;
+		clock-names = "clk_crypto", "hclk_crypto";
+		assigned-clocks = <&cru SCLK_CRYPTO>, <&cru HCLK_CRYPTO>;
+		assigned-clock-rates = <150000000>, <100000000>;
+		status = "disabled";
+	};
+
 	crypto: crypto@ff8a0000 {
 		compatible = "rockchip,rk3288-crypto";
 		reg = <0x0 0xff8a0000 0x0 0x4000>;
@@ -1010,7 +1219,36 @@
 		clock-names = "aclk", "hclk", "sclk", "apb_pclk";
 		resets = <&cru SRST_CRYPTO>;
 		reset-names = "crypto-rst";
-		status = "okay";
+		status = "disabled";
+	};
+
+	spdif: sound@ff8b0000 {
+		compatible = "rockchip,rk3288-spdif", "rockchip,rk3066-spdif";
+		reg = <0x0 0xff8b0000 0x0 0x10000>;
+		#sound-dai-cells = <0>;
+		clocks = <&cru SCLK_SPDIF8CH>, <&cru HCLK_SPDIF8CH>;
+		clock-names = "mclk", "hclk";
+		dmas = <&dmac_bus_s 3>;
+		dma-names = "tx";
+		interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&spdif_tx>;
+		rockchip,grf = <&grf>;
+		status = "disabled";
+	};
+
+	iep: iep@ff90000 {
+		compatible = "rockchip,iep";
+		iommu_enabled = <1>;
+		iommus = <&iep_mmu>;
+		reg = <0x0 0xff900000 0x0 0x800>;
+		interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
+		clock-names = "aclk_iep", "hclk_iep";
+		power-domains = <&power RK3288_PD_VIO>;
+		allocator = <1>;
+		version = <1>;
+		status = "disabled";
 	};
 
 	iep_mmu: iommu@ff900800 {
@@ -1024,6 +1262,64 @@
 		status = "disabled";
 	};
 
+	isp: isp@ff910000 {
+		compatible = "rockchip,rk3288-isp", "rockchip,isp";
+		reg = <0x0 0xff910000 0x0 0x4000>;
+		interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+		power-domains = <&power RK3288_PD_VIO>;
+		clocks =
+			<&cru ACLK_ISP>, <&cru HCLK_ISP>, <&cru SCLK_ISP>,
+			<&cru SCLK_ISP_JPE>, <&cru PCLK_ISP_IN>,
+			<&cru SCLK_VIP_OUT>, <&cru SCLK_MIPIDSI_24M>,
+			<&cru SCLK_VIP_OUT>, <&cru PCLK_MIPI_CSI>;
+		clock-names =
+			"aclk_isp", "hclk_isp", "clk_isp",
+			"clk_isp_jpe", "pclkin_isp", "clk_cif_out",
+			"clk_mipi_24m", "clk_cif_pll", "hclk_mipiphy1";
+		pinctrl-names =
+			"default", "isp_dvp8bit2", "isp_dvp10bit",
+			"isp_dvp12bit", "isp_dvp8bit0", "isp_mipi_fl",
+			"isp_mipi_fl_prefl", "isp_flash_as_gpio",
+			"isp_flash_as_trigger_out";
+		pinctrl-0 = <&isp_mipi>;
+		pinctrl-1 = <&isp_mipi &isp_dvp_d2d9>;
+		pinctrl-2 = <&isp_mipi &isp_dvp_d2d9 &isp_dvp_d0d1>;
+		pinctrl-3 = <&isp_mipi &isp_dvp_d2d9 &isp_dvp_d0d1
+					&isp_dvp_d10d11>;
+		pinctrl-4 = <&isp_mipi &isp_dvp_d0d7>;
+		pinctrl-5 = <&isp_mipi>;
+		pinctrl-6 = <&isp_mipi &isp_prelight>;
+		pinctrl-7 = <&isp_flash_trigger_as_gpio>;
+		pinctrl-8 = <&isp_flash_trigger>;
+		rockchip,isp,mipiphy = <2>;
+		rockchip,isp,cifphy = <1>;
+		rockchip,isp,mipiphy1,reg = <0xff968000 0x4000>;
+		rockchip,grf = <&grf>;
+		rockchip,cru = <&cru>;
+		rockchip,gpios = <&gpio7 13 GPIO_ACTIVE_HIGH>;
+		rockchip,isp,iommu_enable = <1>;
+		iommus = <&isp_mmu>;
+		status = "disabled";
+	};
+
+	rkisp1: rkisp1@ff910000 {
+		compatible = "rockchip,rk3288-rkisp1";
+		reg = <0x0 0xff910000 0x0 0x4000>;
+		interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "isp_irq";
+		clocks = <&cru SCLK_ISP>, <&cru ACLK_ISP>,
+			<&cru HCLK_ISP>, <&cru PCLK_ISP_IN>,
+			<&cru SCLK_ISP_JPE>;
+		clock-names = "clk_isp", "aclk_isp",
+			"hclk_isp", "pclk_isp_in",
+			"sclk_isp_jpe";
+		assigned-clocks = <&cru SCLK_ISP>, <&cru SCLK_ISP_JPE>;
+		assigned-clock-rates = <400000000>, <400000000>;
+		power-domains = <&power RK3288_PD_VIO>;
+		iommus = <&isp_mmu>;
+		status = "disabled";
+	};
+
 	isp_mmu: iommu@ff914000 {
 		compatible = "rockchip,iommu";
 		reg = <0x0 0xff914000 0x0 0x100>, <0x0 0xff915000 0x0 0x100>;
@@ -1048,8 +1344,9 @@
 	};
 
 	vopb: vop@ff930000 {
-		compatible = "rockchip,rk3288-vop";
+		compatible = "rockchip,rk3288-vop-big";
 		reg = <0x0 0xff930000 0x0 0x19c>, <0x0 0xff931000 0x0 0x1000>;
+		reg-names = "regs", "gamma_lut";
 		interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
 		clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
@@ -1073,15 +1370,25 @@
 				remote-endpoint = <&edp_in_vopb>;
 			};
 
-			vopb_out_mipi: endpoint@2 {
+			vopb_out_dsi0: endpoint@2 {
 				reg = <2>;
-				remote-endpoint = <&mipi_in_vopb>;
+				remote-endpoint = <&dsi0_in_vopb>;
 			};
 
-			vopb_out_lvds: endpoint@3 {
+			vopb_out_dsi1: endpoint@3 {
 				reg = <3>;
+				remote-endpoint = <&dsi1_in_vopb>;
+			};
+
+			vopb_out_lvds: endpoint@4 {
+				reg = <4>;
 				remote-endpoint = <&lvds_in_vopb>;
 			};
+
+			vopb_out_rgb: endpoint@5 {
+				reg = <5>;
+				remote-endpoint = <&rgb_in_vopb>;
+			};
 		};
 	};
 
@@ -1094,12 +1401,14 @@
 		clock-names = "aclk", "iface";
 		power-domains = <&power RK3288_PD_VIO>;
 		#iommu-cells = <0>;
+		rockchip,disable-device-link-resume;
 		status = "disabled";
 	};
 
 	vopl: vop@ff940000 {
-		compatible = "rockchip,rk3288-vop";
+		compatible = "rockchip,rk3288-vop-lit";
 		reg = <0x0 0xff940000 0x0 0x19c>, <0x0 0xff941000 0x0 0x1000>;
+		reg-names = "regs", "gamma_lut";
 		interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
 		clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
@@ -1123,15 +1432,25 @@
 				remote-endpoint = <&edp_in_vopl>;
 			};
 
-			vopl_out_mipi: endpoint@2 {
+			vopl_out_dsi0: endpoint@2 {
 				reg = <2>;
-				remote-endpoint = <&mipi_in_vopl>;
+				remote-endpoint = <&dsi0_in_vopl>;
 			};
 
-			vopl_out_lvds: endpoint@3 {
+			vopl_out_dsi1: endpoint@3 {
 				reg = <3>;
+				remote-endpoint = <&dsi1_in_vopl>;
+			};
+
+			vopl_out_lvds: endpoint@4 {
+				reg = <4>;
 				remote-endpoint = <&lvds_in_vopl>;
 			};
+
+			vopl_out_rgb: endpoint@5 {
+				reg = <5>;
+				remote-endpoint = <&rgb_in_vopl>;
+			};
 		};
 	};
 
@@ -1144,76 +1463,114 @@
 		clock-names = "aclk", "iface";
 		power-domains = <&power RK3288_PD_VIO>;
 		#iommu-cells = <0>;
+		rockchip,disable-device-link-resume;
 		status = "disabled";
 	};
 
-	mipi_dsi: mipi@ff960000 {
+	cif: cif@ff950000 {
+		compatible = "rockchip,cif", "rockchip,rk3288-cif";
+		reg = <0x0 0xff950000 0x0 0x400>;
+		interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&cru ACLK_VIP>, <&cru HCLK_VIP>,
+			<&cru PCLK_VIP_IN>, <&cru SCLK_VIP_OUT>;
+		clock-names = "aclk_cif0", "hclk_cif0",
+				"cif0_in", "cif0_out";
+		resets = <&cru SRST_VIP>;
+		reset-names = "rst_cif";
+		pinctrl-names = "cif_pin_all";
+		pinctrl-0 = <&isp_mipi &isp_dvp_d2d9 &isp_dvp_d10d11>;
+		rockchip,grf = <&grf>;
+		rockchip,cru = <&cru>;
+		power-domains = <&power RK3288_PD_VIO>;
+		status = "disabled";
+	};
+
+	dsi0: dsi@ff960000 {
 		compatible = "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi";
 		reg = <0x0 0xff960000 0x0 0x4000>;
 		interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_MIPI_DSI0>;
 		clock-names = "ref", "pclk";
+		resets = <&cru SRST_MIPIDSI0>;
+		reset-names = "apb";
 		power-domains = <&power RK3288_PD_VIO>;
 		rockchip,grf = <&grf>;
+		#address-cells = <1>;
+		#size-cells = <0>;
 		status = "disabled";
 
 		ports {
 			mipi_in: port {
 				#address-cells = <1>;
 				#size-cells = <0>;
-				mipi_in_vopb: endpoint@0 {
+				dsi0_in_vopb: endpoint@0 {
 					reg = <0>;
-					remote-endpoint = <&vopb_out_mipi>;
+					remote-endpoint = <&vopb_out_dsi0>;
 				};
-				mipi_in_vopl: endpoint@1 {
+				dsi0_in_vopl: endpoint@1 {
 					reg = <1>;
-					remote-endpoint = <&vopl_out_mipi>;
+					remote-endpoint = <&vopl_out_dsi0>;
 				};
 			};
 		};
 	};
 
-	lvds: lvds@ff96c000 {
-		compatible = "rockchip,rk3288-lvds";
-		reg = <0x0 0xff96c000 0x0 0x4000>;
-		clocks = <&cru PCLK_LVDS_PHY>;
-		clock-names = "pclk_lvds";
-		pinctrl-names = "lcdc";
-		pinctrl-0 = <&lcdc_ctl>;
+	dsi1: dsi@ff964000 {
+		compatible = "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi";
+		reg = <0x0 0xff964000 0x0 0x4000>;
+		interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_MIPI_DSI1>;
+		clock-names = "ref", "pclk";
+		resets = <&cru SRST_MIPIDSI1>;
+		reset-names = "apb";
 		power-domains = <&power RK3288_PD_VIO>;
 		rockchip,grf = <&grf>;
+		#address-cells = <1>;
+		#size-cells = <0>;
 		status = "disabled";
 
 		ports {
 			#address-cells = <1>;
 			#size-cells = <0>;
 
-			lvds_in: port@0 {
-				reg = <0>;
-
+			dsi1_in: port {
 				#address-cells = <1>;
 				#size-cells = <0>;
 
-				lvds_in_vopb: endpoint@0 {
+				dsi1_in_vopb: endpoint@0 {
 					reg = <0>;
-					remote-endpoint = <&vopb_out_lvds>;
+					remote-endpoint = <&vopb_out_dsi1>;
 				};
-				lvds_in_vopl: endpoint@1 {
+				dsi1_in_vopl: endpoint@1 {
 					reg = <1>;
-					remote-endpoint = <&vopl_out_lvds>;
+					remote-endpoint = <&vopl_out_dsi1>;
 				};
 			};
 		};
 	};
 
+	video_phy: video-phy@ff96c000 {
+		compatible = "rockchip,rk3288-video-phy";
+		reg = <0x0 0xff96c000 0x0 0x4000>;
+		clocks = <&cru PCLK_LVDS_PHY>;
+		clock-names = "pclk";
+		resets = <&cru SRST_LVDS_PHY>;
+		reset-names = "rst";
+		power-domains = <&power RK3288_PD_VIO>;
+		#phy-cells = <0>;
+		status = "disabled";
+	};
+
 	edp: dp@ff970000 {
 		compatible = "rockchip,rk3288-dp";
 		reg = <0x0 0xff970000 0x0 0x4000>;
 		interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&cru SCLK_EDP>, <&cru PCLK_EDP_CTRL>;
-		clock-names = "dp", "pclk";
-		phys = <&edp_phy>;
-		phy-names = "dp";
+		clocks = <&cru SCLK_EDP_24M>, <&cru PCLK_EDP_CTRL>,
+			 <&cru SCLK_EDP>;
+		clock-names = "dp", "pclk", "spdif";
+		assigned-clocks = <&cru SCLK_EDP_24M>;
+		assigned-clock-parents = <&xin24m>;
+		power-domains = <&power RK3288_PD_VIO>;
 		resets = <&cru SRST_EDP>;
 		reset-names = "dp";
 		rockchip,grf = <&grf>;
@@ -1247,7 +1604,11 @@
 		interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&cru  PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>, <&cru SCLK_HDMI_CEC>;
 		clock-names = "iahb", "isfr", "cec";
+		pinctrl-names = "default", "sleep";
+		pinctrl-0 = <&hdmi_ddc>;
+		pinctrl-1 = <&hdmi_gpio>;
 		power-domains = <&power RK3288_PD_VIO>;
+		unsupported-yuv-input;
 		status = "disabled";
 
 		ports {
@@ -1306,12 +1667,14 @@
 	};
 
 	vdpu: vdpu@ff9a0400 {
-		compatible = "rockchip,vpu-decoder-v1";
+		compatible = "rockchip,vpu-decoder-rk3288", "rockchip,vpu-decoder-v1";
 		reg = <0x0 0xff9a0400 0x0 0x400>;
 		interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 		interrupt-names = "irq_dec";
 		clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
 		clock-names = "aclk_vcodec", "hclk_vcodec";
+		rockchip,normal-rates = <300000000>, <0>;
+		rockchip,advanced-rates = <600000000>, <0>;
 		resets = <&cru SRST_VCODEC_AXI>, <&cru SRST_VCODEC_AHB>;
 		reset-names = "shared_video_a", "shared_video_h";
 		assigned-clocks = <&cru ACLK_VCODEC>;
@@ -1345,6 +1708,11 @@
 			 <&cru SCLK_HEVC_CABAC>;
 		clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core",
 			      "clk_cabac";
+		rockchip,normal-rates = <300000000>, <0>, <200000000>,
+				<200000000>;
+		rockchip,advanced-rates = <500000000>, <0>, <400000000>,
+				<400000000>;
+		rockchip,default-max-load = <2088960>;
 		resets =  <&cru SRST_HEVC>;
 		reset-names = "video_core";
 
@@ -1378,26 +1746,46 @@
 	};
 
 	gpu: gpu@ffa30000 {
-		compatible = "rockchip,rk3288-mali", "arm,mali-t760";
+		compatible = "rockchip,rk3288-mali", "arm,mali-t760",
+			     "arm,malit764", "arm,malit76x", "arm,malit7xx",
+			     "arm,mali-midgard";
 		reg = <0x0 0xffa30000 0x0 0x10000>;
 		interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
 			     <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
 			     <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 		interrupt-names = "job", "mmu", "gpu";
 		clocks = <&cru ACLK_GPU>;
+		clock-names = "clk_mali";
 		operating-points-v2 = <&gpu_opp_table>;
 		#cooling-cells = <2>; /* min followed by max */
 		power-domains = <&power RK3288_PD_GPU>;
 		status = "disabled";
+
+		upthreshold = <75>;
+		downdifferential = <10>;
+
+		gpu_power_model: power_model {
+			compatible = "arm,mali-simple-power-model";
+			static-coefficient = <411000>;
+			dynamic-coefficient = <733>;
+			ts = <32000 4700 (-80) 2>;
+			thermal-zone = "gpu-thermal";
+		};
 	};
 
 	gpu_opp_table: gpu-opp-table {
 		compatible = "operating-points-v2";
 
-		opp-100000000 {
-			opp-hz = /bits/ 64 <100000000>;
-			opp-microvolt = <950000>;
-		};
+		clocks = <&cru PLL_GPLL>;
+		nvmem-cells = <&performance>, <&performance_w>;
+		nvmem-cell-names = "performance", "performance-w";
+		rockchip,bin-scaling-sel = <
+			0               55
+			1               59
+			2               61
+			3               61
+		>;
+
 		opp-200000000 {
 			opp-hz = /bits/ 64 <200000000>;
 			opp-microvolt = <950000>;
@@ -1406,8 +1794,8 @@
 			opp-hz = /bits/ 64 <300000000>;
 			opp-microvolt = <1000000>;
 		};
-		opp-400000000 {
-			opp-hz = /bits/ 64 <400000000>;
+		opp-420000000 {
+			opp-hz = /bits/ 64 <420000000>;
 			opp-microvolt = <1100000>;
 		};
 		opp-600000000 {
@@ -1494,12 +1882,32 @@
 		clocks = <&cru PCLK_EFUSE256>;
 		clock-names = "pclk_efuse";
 
+		special_function: special-function@5 {
+			reg = <0x5 0x1>;
+			bits = <4 4>;
+		};
+		package_info: package-info@5 {
+			reg = <0x5 0x1>;
+			bits = <2 2>;
+		};
+		process_version: process-version@6 {
+			reg = <0x6 0x1>;
+			bits = <0 4>;
+		};
 		cpu_id: cpu-id@7 {
 			reg = <0x07 0x10>;
 		};
 		cpu_leakage: cpu_leakage@17 {
 			reg = <0x17 0x1>;
 		};
+		performance_w: performance@1c {
+			reg = <0x1c 0x1>;
+			bits = <4 3>;
+		};
+		performance: performance@1d {
+			reg = <0x1d 0x1>;
+			bits = <4 3>;
+		};
 	};
 
 	gic: interrupt-controller@ffc01000 {
@@ -1519,6 +1927,30 @@
 		compatible = "rockchip,system-monitor";
 	};
 
+	rockchip_suspend: rockchip-suspend {
+		compatible = "rockchip,pm-rk3288";
+		status = "disabled";
+		rockchip,sleep-mode-config = <
+			(0
+			|RKPM_CTR_PWR_DMNS
+			|RKPM_CTR_GTCLKS
+			|RKPM_CTR_PLLS
+			|RKPM_CTR_ARMOFF_LPMD
+			|RKPM_CTR_SYSCLK_OSC_DIS
+			)
+		>;
+		rockchip,wakeup-config = <
+			(0
+			| RKPM_GPIO_WKUP_EN
+			)
+		>;
+		rockchip,pwm-regulator-config = <
+			(0
+			| PWM2_REGULATOR_EN
+			)
+		>;
+	};
+
 	pinctrl: pinctrl {
 		compatible = "rockchip,rk3288-pinctrl";
 		rockchip,grf = <&grf>;
@@ -1644,482 +2076,11 @@
 			#interrupt-cells = <2>;
 		};
 
-		hdmi {
-			hdmi_cec_c0: hdmi-cec-c0 {
-				rockchip,pins = <7 RK_PC0 2 &pcfg_pull_none>;
-			};
-
-			hdmi_cec_c7: hdmi-cec-c7 {
-				rockchip,pins = <7 RK_PC7 4 &pcfg_pull_none>;
-			};
-
-			hdmi_ddc: hdmi-ddc {
-				rockchip,pins = <7 RK_PC3 2 &pcfg_pull_none>,
-						<7 RK_PC4 2 &pcfg_pull_none>;
-			};
-
-			hdmi_ddc_unwedge: hdmi-ddc-unwedge {
-				rockchip,pins = <7 RK_PC3 RK_FUNC_GPIO &pcfg_output_low>,
-						<7 RK_PC4 2 &pcfg_pull_none>;
-			};
-		};
-
-		pcfg_output_low: pcfg-output-low {
-			output-low;
-		};
-
-		pcfg_pull_up: pcfg-pull-up {
-			bias-pull-up;
-		};
-
-		pcfg_pull_down: pcfg-pull-down {
-			bias-pull-down;
-		};
-
-		pcfg_pull_none: pcfg-pull-none {
-			bias-disable;
-		};
-
 		pcfg_pull_none_12ma: pcfg-pull-none-12ma {
 			bias-disable;
 			drive-strength = <12>;
 		};
-
-		suspend {
-			global_pwroff: global-pwroff {
-				rockchip,pins = <0 RK_PA0 1 &pcfg_pull_none>;
-			};
-
-			ddrio_pwroff: ddrio-pwroff {
-				rockchip,pins = <0 RK_PA1 1 &pcfg_pull_none>;
-			};
-
-			ddr0_retention: ddr0-retention {
-				rockchip,pins = <0 RK_PA2 1 &pcfg_pull_up>;
-			};
-
-			ddr1_retention: ddr1-retention {
-				rockchip,pins = <0 RK_PA3 1 &pcfg_pull_up>;
-			};
-		};
-
-		edp {
-			edp_hpd: edp-hpd {
-				rockchip,pins = <7 RK_PB3 2 &pcfg_pull_down>;
-			};
-		};
-
-		i2c0 {
-			i2c0_xfer: i2c0-xfer {
-				rockchip,pins = <0 RK_PB7 1 &pcfg_pull_none>,
-						<0 RK_PC0 1 &pcfg_pull_none>;
-			};
-		};
-
-		i2c1 {
-			i2c1_xfer: i2c1-xfer {
-				rockchip,pins = <8 RK_PA4 1 &pcfg_pull_none>,
-						<8 RK_PA5 1 &pcfg_pull_none>;
-			};
-		};
-
-		i2c2 {
-			i2c2_xfer: i2c2-xfer {
-				rockchip,pins = <6 RK_PB1 1 &pcfg_pull_none>,
-						<6 RK_PB2 1 &pcfg_pull_none>;
-			};
-		};
-
-		i2c3 {
-			i2c3_xfer: i2c3-xfer {
-				rockchip,pins = <2 RK_PC0 1 &pcfg_pull_none>,
-						<2 RK_PC1 1 &pcfg_pull_none>;
-			};
-		};
-
-		i2c4 {
-			i2c4_xfer: i2c4-xfer {
-				rockchip,pins = <7 RK_PC1 1 &pcfg_pull_none>,
-						<7 RK_PC2 1 &pcfg_pull_none>;
-			};
-		};
-
-		i2c5 {
-			i2c5_xfer: i2c5-xfer {
-				rockchip,pins = <7 RK_PC3 1 &pcfg_pull_none>,
-						<7 RK_PC4 1 &pcfg_pull_none>;
-			};
-		};
-
-		i2s0 {
-			i2s0_bus: i2s0-bus {
-				rockchip,pins = <6 RK_PA0 1 &pcfg_pull_none>,
-						<6 RK_PA1 1 &pcfg_pull_none>,
-						<6 RK_PA2 1 &pcfg_pull_none>,
-						<6 RK_PA3 1 &pcfg_pull_none>,
-						<6 RK_PA4 1 &pcfg_pull_none>,
-						<6 RK_PB0 1 &pcfg_pull_none>;
-			};
-		};
-
-		lcdc {
-			lcdc_ctl: lcdc-ctl {
-				rockchip,pins = <1 RK_PD0 1 &pcfg_pull_none>,
-						<1 RK_PD1 1 &pcfg_pull_none>,
-						<1 RK_PD2 1 &pcfg_pull_none>,
-						<1 RK_PD3 1 &pcfg_pull_none>;
-			};
-		};
-
-		sdmmc {
-			sdmmc_clk: sdmmc-clk {
-				rockchip,pins = <6 RK_PC4 1 &pcfg_pull_none>;
-			};
-
-			sdmmc_cmd: sdmmc-cmd {
-				rockchip,pins = <6 RK_PC5 1 &pcfg_pull_up>;
-			};
-
-			sdmmc_cd: sdmmc-cd {
-				rockchip,pins = <6 RK_PC6 1 &pcfg_pull_up>;
-			};
-
-			sdmmc_bus1: sdmmc-bus1 {
-				rockchip,pins = <6 RK_PC0 1 &pcfg_pull_up>;
-			};
-
-			sdmmc_bus4: sdmmc-bus4 {
-				rockchip,pins = <6 RK_PC0 1 &pcfg_pull_up>,
-						<6 RK_PC1 1 &pcfg_pull_up>,
-						<6 RK_PC2 1 &pcfg_pull_up>,
-						<6 RK_PC3 1 &pcfg_pull_up>;
-			};
-		};
-
-		sdio0 {
-			sdio0_bus1: sdio0-bus1 {
-				rockchip,pins = <4 RK_PC4 1 &pcfg_pull_up>;
-			};
-
-			sdio0_bus4: sdio0-bus4 {
-				rockchip,pins = <4 RK_PC4 1 &pcfg_pull_up>,
-						<4 RK_PC5 1 &pcfg_pull_up>,
-						<4 RK_PC6 1 &pcfg_pull_up>,
-						<4 RK_PC7 1 &pcfg_pull_up>;
-			};
-
-			sdio0_cmd: sdio0-cmd {
-				rockchip,pins = <4 RK_PD0 1 &pcfg_pull_up>;
-			};
-
-			sdio0_clk: sdio0-clk {
-				rockchip,pins = <4 RK_PD1 1 &pcfg_pull_none>;
-			};
-
-			sdio0_cd: sdio0-cd {
-				rockchip,pins = <4 RK_PD2 1 &pcfg_pull_up>;
-			};
-
-			sdio0_wp: sdio0-wp {
-				rockchip,pins = <4 RK_PD3 1 &pcfg_pull_up>;
-			};
-
-			sdio0_pwr: sdio0-pwr {
-				rockchip,pins = <4 RK_PD4 1 &pcfg_pull_up>;
-			};
-
-			sdio0_bkpwr: sdio0-bkpwr {
-				rockchip,pins = <4 RK_PD5 1 &pcfg_pull_up>;
-			};
-
-			sdio0_int: sdio0-int {
-				rockchip,pins = <4 RK_PD6 1 &pcfg_pull_up>;
-			};
-		};
-
-		sdio1 {
-			sdio1_bus1: sdio1-bus1 {
-				rockchip,pins = <3 RK_PD0 4 &pcfg_pull_up>;
-			};
-
-			sdio1_bus4: sdio1-bus4 {
-				rockchip,pins = <3 RK_PD0 4 &pcfg_pull_up>,
-						<3 RK_PD1 4 &pcfg_pull_up>,
-						<3 RK_PD2 4 &pcfg_pull_up>,
-						<3 RK_PD3 4 &pcfg_pull_up>;
-			};
-
-			sdio1_cd: sdio1-cd {
-				rockchip,pins = <3 RK_PD4 4 &pcfg_pull_up>;
-			};
-
-			sdio1_wp: sdio1-wp {
-				rockchip,pins = <3 RK_PD5 4 &pcfg_pull_up>;
-			};
-
-			sdio1_bkpwr: sdio1-bkpwr {
-				rockchip,pins = <3 RK_PD6 4 &pcfg_pull_up>;
-			};
-
-			sdio1_int: sdio1-int {
-				rockchip,pins = <3 RK_PD7 4 &pcfg_pull_up>;
-			};
-
-			sdio1_cmd: sdio1-cmd {
-				rockchip,pins = <4 RK_PA6 4 &pcfg_pull_up>;
-			};
-
-			sdio1_clk: sdio1-clk {
-				rockchip,pins = <4 RK_PA7 4 &pcfg_pull_none>;
-			};
-
-			sdio1_pwr: sdio1-pwr {
-				rockchip,pins = <4 RK_PB1 4 &pcfg_pull_up>;
-			};
-		};
-
-		emmc {
-			emmc_clk: emmc-clk {
-				rockchip,pins = <3 RK_PC2 2 &pcfg_pull_none>;
-			};
-
-			emmc_cmd: emmc-cmd {
-				rockchip,pins = <3 RK_PC0 2 &pcfg_pull_up>;
-			};
-
-			emmc_pwr: emmc-pwr {
-				rockchip,pins = <3 RK_PB1 2 &pcfg_pull_up>;
-			};
-
-			emmc_bus1: emmc-bus1 {
-				rockchip,pins = <3 RK_PA0 2 &pcfg_pull_up>;
-			};
-
-			emmc_bus4: emmc-bus4 {
-				rockchip,pins = <3 RK_PA0 2 &pcfg_pull_up>,
-						<3 RK_PA1 2 &pcfg_pull_up>,
-						<3 RK_PA2 2 &pcfg_pull_up>,
-						<3 RK_PA3 2 &pcfg_pull_up>;
-			};
-
-			emmc_bus8: emmc-bus8 {
-				rockchip,pins = <3 RK_PA0 2 &pcfg_pull_up>,
-						<3 RK_PA1 2 &pcfg_pull_up>,
-						<3 RK_PA2 2 &pcfg_pull_up>,
-						<3 RK_PA3 2 &pcfg_pull_up>,
-						<3 RK_PA4 2 &pcfg_pull_up>,
-						<3 RK_PA5 2 &pcfg_pull_up>,
-						<3 RK_PA6 2 &pcfg_pull_up>,
-						<3 RK_PA7 2 &pcfg_pull_up>;
-			};
-		};
-
-		spi0 {
-			spi0_clk: spi0-clk {
-				rockchip,pins = <5 RK_PB4 1 &pcfg_pull_up>;
-			};
-			spi0_cs0: spi0-cs0 {
-				rockchip,pins = <5 RK_PB5 1 &pcfg_pull_up>;
-			};
-			spi0_tx: spi0-tx {
-				rockchip,pins = <5 RK_PB6 1 &pcfg_pull_up>;
-			};
-			spi0_rx: spi0-rx {
-				rockchip,pins = <5 RK_PB7 1 &pcfg_pull_up>;
-			};
-			spi0_cs1: spi0-cs1 {
-				rockchip,pins = <5 RK_PC0 1 &pcfg_pull_up>;
-			};
-		};
-		spi1 {
-			spi1_clk: spi1-clk {
-				rockchip,pins = <7 RK_PB4 2 &pcfg_pull_up>;
-			};
-			spi1_cs0: spi1-cs0 {
-				rockchip,pins = <7 RK_PB5 2 &pcfg_pull_up>;
-			};
-			spi1_rx: spi1-rx {
-				rockchip,pins = <7 RK_PB6 2 &pcfg_pull_up>;
-			};
-			spi1_tx: spi1-tx {
-				rockchip,pins = <7 RK_PB7 2 &pcfg_pull_up>;
-			};
-		};
-
-		spi2 {
-			spi2_cs1: spi2-cs1 {
-				rockchip,pins = <8 RK_PA3 1 &pcfg_pull_up>;
-			};
-			spi2_clk: spi2-clk {
-				rockchip,pins = <8 RK_PA6 1 &pcfg_pull_up>;
-			};
-			spi2_cs0: spi2-cs0 {
-				rockchip,pins = <8 RK_PA7 1 &pcfg_pull_up>;
-			};
-			spi2_rx: spi2-rx {
-				rockchip,pins = <8 RK_PB0 1 &pcfg_pull_up>;
-			};
-			spi2_tx: spi2-tx {
-				rockchip,pins = <8 RK_PB1 1 &pcfg_pull_up>;
-			};
-		};
-
-		uart0 {
-			uart0_xfer: uart0-xfer {
-				rockchip,pins = <4 RK_PC0 1 &pcfg_pull_up>,
-						<4 RK_PC1 1 &pcfg_pull_none>;
-			};
-
-			uart0_cts: uart0-cts {
-				rockchip,pins = <4 RK_PC2 1 &pcfg_pull_up>;
-			};
-
-			uart0_rts: uart0-rts {
-				rockchip,pins = <4 RK_PC3 1 &pcfg_pull_none>;
-			};
-		};
-
-		uart1 {
-			uart1_xfer: uart1-xfer {
-				rockchip,pins = <5 RK_PB0 1 &pcfg_pull_up>,
-						<5 RK_PB1 1 &pcfg_pull_none>;
-			};
-
-			uart1_cts: uart1-cts {
-				rockchip,pins = <5 RK_PB2 1 &pcfg_pull_up>;
-			};
-
-			uart1_rts: uart1-rts {
-				rockchip,pins = <5 RK_PB3 1 &pcfg_pull_none>;
-			};
-		};
-
-		uart2 {
-			uart2_xfer: uart2-xfer {
-				rockchip,pins = <7 RK_PC6 1 &pcfg_pull_up>,
-						<7 RK_PC7 1 &pcfg_pull_none>;
-			};
-			/* no rts / cts for uart2 */
-		};
-
-		uart3 {
-			uart3_xfer: uart3-xfer {
-				rockchip,pins = <7 RK_PA7 1 &pcfg_pull_up>,
-						<7 RK_PB0 1 &pcfg_pull_none>;
-			};
-
-			uart3_cts: uart3-cts {
-				rockchip,pins = <7 RK_PB1 1 &pcfg_pull_up>;
-			};
-
-			uart3_rts: uart3-rts {
-				rockchip,pins = <7 RK_PB2 1 &pcfg_pull_none>;
-			};
-		};
-
-		uart4 {
-			uart4_xfer: uart4-xfer {
-				rockchip,pins = <5 RK_PB7 3 &pcfg_pull_up>,
-						<5 RK_PB6 3 &pcfg_pull_none>;
-			};
-
-			uart4_cts: uart4-cts {
-				rockchip,pins = <5 RK_PB4 3 &pcfg_pull_up>;
-			};
-
-			uart4_rts: uart4-rts {
-				rockchip,pins = <5 RK_PB5 3 &pcfg_pull_none>;
-			};
-		};
-
-		tsadc {
-			otp_pin: otp-pin {
-				rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
-			};
-
-			otp_out: otp-out {
-				rockchip,pins = <0 RK_PB2 1 &pcfg_pull_none>;
-			};
-		};
-
-		pwm0 {
-			pwm0_pin: pwm0-pin {
-				rockchip,pins = <7 RK_PA0 1 &pcfg_pull_none>;
-			};
-
-			pwm0_pin_pull_down: pwm0-pin-pull-down {
-				rockchip,pins = <7 RK_PA0 1 &pcfg_pull_down>;
-			};
-
-		};
-
-		pwm1 {
-			pwm1_pin: pwm1-pin {
-				rockchip,pins = <7 RK_PA1 1 &pcfg_pull_none>;
-			};
-
-			pwm1_pin_pull_down: pwm1-pin-pull-down {
-				rockchip,pins = <7 RK_PA1 1 &pcfg_pull_down>;
-			};
-		};
-
-		pwm2 {
-			pwm2_pin: pwm2-pin {
-				rockchip,pins = <7 RK_PC6 3 &pcfg_pull_none>;
-			};
-
-			pwm2_pin_pull_down: pwm2-pin-pull-down {
-				rockchip,pins = <7 RK_PC6 3 &pcfg_pull_down>;
-			};
-		};
-
-		pwm3 {
-			pwm3_pin: pwm3-pin {
-				rockchip,pins = <7 RK_PC7 3 &pcfg_pull_none>;
-			};
-
-			pwm3_pin_pull_down: pwm3-pin-pull-down {
-				rockchip,pins = <7 RK_PC7 3 &pcfg_pull_down>;
-			};
-		};
-
-		gmac {
-			rgmii_pins: rgmii-pins {
-				rockchip,pins = <3 RK_PD6 3 &pcfg_pull_none>,
-						<3 RK_PD7 3 &pcfg_pull_none>,
-						<3 RK_PD2 3 &pcfg_pull_none>,
-						<3 RK_PD3 3 &pcfg_pull_none>,
-						<3 RK_PD4 3 &pcfg_pull_none_12ma>,
-						<3 RK_PD5 3 &pcfg_pull_none_12ma>,
-						<3 RK_PD0 3 &pcfg_pull_none_12ma>,
-						<3 RK_PD1 3 &pcfg_pull_none_12ma>,
-						<4 RK_PA0 3 &pcfg_pull_none>,
-						<4 RK_PA5 3 &pcfg_pull_none>,
-						<4 RK_PA6 3 &pcfg_pull_none>,
-						<4 RK_PB1 3 &pcfg_pull_none_12ma>,
-						<4 RK_PA4 3 &pcfg_pull_none_12ma>,
-						<4 RK_PA1 3 &pcfg_pull_none>,
-						<4 RK_PA3 3 &pcfg_pull_none>;
-			};
-
-			rmii_pins: rmii-pins {
-				rockchip,pins = <3 RK_PD6 3 &pcfg_pull_none>,
-						<3 RK_PD7 3 &pcfg_pull_none>,
-						<3 RK_PD4 3 &pcfg_pull_none>,
-						<3 RK_PD5 3 &pcfg_pull_none>,
-						<4 RK_PA0 3 &pcfg_pull_none>,
-						<4 RK_PA5 3 &pcfg_pull_none>,
-						<4 RK_PA4 3 &pcfg_pull_none>,
-						<4 RK_PA1 3 &pcfg_pull_none>,
-						<4 RK_PA2 3 &pcfg_pull_none>,
-						<4 RK_PA3 3 &pcfg_pull_none>;
-			};
-		};
-
-		spdif {
-			spdif_tx: spdif-tx {
-				rockchip,pins = <6 RK_PB3 1 &pcfg_pull_none>;
-			};
-		};
 	};
 };
+
+#include "rk3288-pinctrl.dtsi"
diff --git a/arch/arm/boot/dts/rv1106-pinctrl.dtsi b/arch/arm/boot/dts/rv1106-pinctrl.dtsi
index dfbfbb3bf70d..37a46383174b 100644
--- a/arch/arm/boot/dts/rv1106-pinctrl.dtsi
+++ b/arch/arm/boot/dts/rv1106-pinctrl.dtsi
@@ -734,6 +734,13 @@
 	};
 
 	sdmmc1 {
+		/omit-if-no-ref/
+		sdmmc1m0_bus1: sdmmc1m0-bus1 {
+			rockchip,pins =
+				/* sdmmc1_d0_m0 */
+				<2 RK_PA1 1 &pcfg_pull_up_drv_level_2>;
+		};
+
 		/omit-if-no-ref/
 		sdmmc1m0_bus4: sdmmc1m0-bus4 {
 			rockchip,pins =
diff --git a/arch/arm/boot/dts/rv1106-smd-cam.dtsi b/arch/arm/boot/dts/rv1106-smd-cam.dtsi
index 7238b22f6a05..ee12cd83c919 100644
--- a/arch/arm/boot/dts/rv1106-smd-cam.dtsi
+++ b/arch/arm/boot/dts/rv1106-smd-cam.dtsi
@@ -9,6 +9,8 @@
 / {
 	vcc1v2_dvdd: vcc1v8_dovdd: vcc2v8_avdd: vcc-camera {
 		compatible = "regulator-fixed";
+		regulator-boot-on;
+		regulator-always-on;
 		regulator-name = "vcc_camera";
 		pinctrl-names = "default";
 		pinctrl-0 = <&cam_pwren>;
@@ -151,6 +153,8 @@
 };
 
 &i2c4 {
+	rockchip,amp-shared;
+
 	status = "okay";
 	clock-frequency = <400000>;
 	pinctrl-names = "default";
@@ -227,6 +231,7 @@
 &rkcif_mipi_lvds {
 	status = "okay";
 
+	memory-region-thunderboot = <&rkisp_thunderboot>;
 	port {
 		/* MIPI CSI-2 endpoint */
 		cif_mipi0_in: endpoint {
@@ -313,6 +318,19 @@
 	max-input = <1920 1280 30>;
 };
 
+&mailbox {
+	status = "okay";
+};
+
+&thunder_boot_service {
+	status = "okay";
+};
+
+&rkisp_thunderboot {
+	/* vicap, capture raw10, ceil(w*10/8/256)*256*h *4(buf num) */
+	reg = <0x00860000 0xa8c000>;
+};
+
 &rkisp_vir0 {
 	status = "okay";
 
diff --git a/arch/arm/boot/dts/rv1106.dtsi b/arch/arm/boot/dts/rv1106.dtsi
index 54361446933e..4564909db8b2 100644
--- a/arch/arm/boot/dts/rv1106.dtsi
+++ b/arch/arm/boot/dts/rv1106.dtsi
@@ -810,13 +810,12 @@
 		compatible = "rockchip,rv1106-codec";
 		reg = <0xff480000 0x1000>;
 		rockchip,grf = <&grf>;
-		clocks = <&cru PCLK_ACODEC>,
-			 <&cru MCLK_ACODEC_TX>,
-			 <&cru MCLK_I2S0_8CH_TX>;
-		clock-names = "pclk_acodec", "mclk_acodec", "mclk_cpu";
+		clocks = <&cru PCLK_ACODEC>, <&cru MCLK_ACODEC_TX>;
+		clock-names = "pclk_acodec", "mclk_acodec";
 		resets = <&cru SRST_P_ACODEC>;
 		reset-names = "acodec-reset";
 		acodec,micbias;
+		init-mic-gain = <0x22>; /* Left:20dB Right:20dB */
 		status = "disabled";
 	};
 
diff --git a/arch/arm/boot/dts/rv1106g-evb1-v11-cvr.dts b/arch/arm/boot/dts/rv1106g-evb1-v11-cvr.dts
index 035d2abd19ca..576559bcfb39 100644
--- a/arch/arm/boot/dts/rv1106g-evb1-v11-cvr.dts
+++ b/arch/arm/boot/dts/rv1106g-evb1-v11-cvr.dts
@@ -6,7 +6,6 @@
 /dts-v1/;
 
 #include "rv1106g-evb1-v11.dts"
-#include "rv1106-evb-ext-rgb-v10.dtsi"
 
 / {
 	model = "Rockchip RV1106G EVB1 V11 Board For CVR";
diff --git a/arch/arm/boot/dts/rv1106g-evb2-v11-emmc.dts b/arch/arm/boot/dts/rv1106g-evb2-v11-emmc.dts
new file mode 100644
index 000000000000..50b7378a7b72
--- /dev/null
+++ b/arch/arm/boot/dts/rv1106g-evb2-v11-emmc.dts
@@ -0,0 +1,283 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2022 Rockchip Electronics Co., Ltd.
+ */
+
+/dts-v1/;
+
+#include "rv1106.dtsi"
+#include "rv1106-evb-v10.dtsi"
+#include "rv1106-thunder-boot-emmc.dtsi"
+
+/ {
+	model = "Rockchip RV1106G EVB2 V11 EMMC Board";
+	compatible = "rockchip,rv1106g-evb2-v11-emmc", "rockchip,rv1106";
+
+	chosen {
+		bootargs = "loglevel=0 rootfstype=erofs rootflags=dax console=ttyFIQ0 root=/dev/rd0 snd_soc_core.prealloc_buffer_size_kbytes=16 coherent_pool=0 driver_async_probe=dwmmc_rockchip";
+	};
+
+	vcc_1v8: vcc-1v8 {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_1v8";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+	};
+
+	vcc_3v3: vcc-3v3 {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_3v3";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+	};
+
+	vcc3v3_sd: vcc3v3-sd {
+		compatible = "regulator-fixed";
+		gpio = <&gpio2 RK_PA7 GPIO_ACTIVE_LOW>;
+		regulator-name = "vcc3v3_sd";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&sdmmc_pwren>;
+	};
+
+};
+
+&csi2_dphy_hw {
+	status = "okay";
+};
+
+&csi2_dphy0 {
+	status = "okay";
+
+	ports {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		port@0 {
+			reg = <0>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			csi_dphy_input0: endpoint@0 {
+				reg = <0>;
+				remote-endpoint = <&sc3338_out>;
+				data-lanes = <1 2>;
+			};
+		};
+
+		port@1 {
+			reg = <1>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			csi_dphy_output: endpoint@0 {
+				reg = <0>;
+				remote-endpoint = <&mipi_csi2_input>;
+			};
+		};
+	};
+};
+
+&emmc {
+	status = "okay";
+};
+
+&fiq_debugger {
+	rockchip,baudrate = <1500000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart2m1_xfer>;
+};
+
+&i2c4 {
+	rockchip,amp-shared;
+
+	sc3338: sc3338@30 {
+		compatible = "smartsens,sc3338";
+		status = "okay";
+		reg = <0x30>;
+		clocks = <&cru MCLK_REF_MIPI0>;
+		clock-names = "xvclk";
+		pwdn-gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&mipi_refclk_out0>;
+		rockchip,camera-module-index = <0>;
+		rockchip,camera-module-facing = "back";
+		rockchip,camera-module-name = "FKO1";
+		rockchip,camera-module-lens-name = "30IRC-F16";
+		port {
+			sc3338_out: endpoint {
+				remote-endpoint = <&csi_dphy_input0>;
+				data-lanes = <1 2>;
+			};
+		};
+	};
+};
+
+&mipi0_csi2 {
+	status = "okay";
+
+	ports {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		port@0 {
+			reg = <0>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			mipi_csi2_input: endpoint@1 {
+				reg = <1>;
+				remote-endpoint = <&csi_dphy_output>;
+			};
+		};
+
+		port@1 {
+			reg = <1>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			mipi_csi2_output: endpoint@0 {
+				reg = <0>;
+				remote-endpoint = <&cif_mipi_in>;
+			};
+		};
+	};
+};
+
+&mailbox {
+	status = "okay";
+};
+
+&rkcif {
+	status = "okay";
+};
+
+&rkcif_mipi_lvds {
+	status = "okay";
+	memory-region-thunderboot = <&rkisp_thunderboot>;
+
+	pinctrl-names = "default";
+	pinctrl-0 = <&mipi_pins>;
+	port {
+		/* MIPI CSI-2 endpoint */
+		cif_mipi_in: endpoint {
+			remote-endpoint = <&mipi_csi2_output>;
+		};
+	};
+};
+
+&rkcif_mipi_lvds_sditf {
+	status = "okay";
+
+	port {
+		/* MIPI CSI-2 endpoint */
+		mipi_lvds_sditf: endpoint {
+			remote-endpoint = <&isp_in>;
+		};
+	};
+};
+
+&rkisp {
+	status = "okay";
+};
+
+&rkisp_vir0 {
+	status = "okay";
+
+	port@0 {
+		isp_in: endpoint {
+			remote-endpoint = <&mipi_lvds_sditf>;
+		};
+	};
+};
+
+&thunder_boot_service {
+	status = "okay";
+};
+
+&rkisp_thunderboot {
+	/* reg's offset MUST match with RTOS */
+	/*
+	 * vicap, capture raw10, ceil(w*10/8/256)*256*h *4(buf num)
+	 * e.g. 2304x1296: 0xf30000
+	 */
+	reg = <0x00860000 0xf30000>;
+};
+
+&ramdisk_r {
+	reg = <0x1790000 (20 * 0x00100000)>;
+};
+
+&ramdisk_c {
+	reg = <0x2b90000 (10 * 0x00100000)>;
+};
+
+&pinctrl {
+	sdmmc {
+		/omit-if-no-ref/
+		sdmmc_pwren: sdmmc-pwren {
+			rockchip,pins = <2 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+};
+
+&pwm10 {
+	status = "okay";
+};
+
+&pwm11 {
+	status = "okay";
+};
+
+&sdio {
+	max-frequency = <50000000>;
+	bus-width = <1>;
+	cap-sd-highspeed;
+	cap-sdio-irq;
+	keep-power-in-suspend;
+	non-removable;
+	rockchip,default-sample-phase = <90>;
+	no-sd;
+	no-mmc;
+	supports-sdio;
+	pinctrl-names = "default";
+	pinctrl-0 = <&sdmmc1m0_cmd &sdmmc1m0_clk &sdmmc1m0_bus4>;
+	status = "okay";
+};
+
+&sdmmc {
+	max-frequency = <200000000>;
+	no-sdio;
+	no-mmc;
+	bus-width = <4>;
+	cap-mmc-highspeed;
+	cap-sd-highspeed;
+	disable-wp;
+	pinctrl-names = "default";
+	pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_det &sdmmc0_bus4>;
+	vmmc-supply = <&vcc3v3_sd>;
+	status = "okay";
+};
+
+&sfc {
+	assigned-clocks = <&cru SCLK_SFC>;
+	assigned-clock-rates = <125000000>;
+	status = "disabled";
+
+	flash@0 {
+		compatible = "jedec,spi-nor";
+		reg = <0>;
+		spi-max-frequency = <125000000>;
+		spi-rx-bus-width = <4>;
+		spi-tx-bus-width = <1>;
+	};
+};
+
+&usbdrd_dwc3 {
+	dr_mode = "peripheral";
+};
diff --git a/arch/arm/boot/dts/rv1106g-smart-door-lock-rmsl-v10.dts b/arch/arm/boot/dts/rv1106g-smart-door-lock-rmsl-v10.dts
index 16b9fb261d17..258cff792f76 100644
--- a/arch/arm/boot/dts/rv1106g-smart-door-lock-rmsl-v10.dts
+++ b/arch/arm/boot/dts/rv1106g-smart-door-lock-rmsl-v10.dts
@@ -14,6 +14,7 @@
 	model = "Rockchip RV1106G Smart Door Lock RMSL V10 Board";
 	compatible = "rockchip,rv1106g-smart-door-lock-rmsl-v10", "rockchip,rv1106";
 
+	/* rkaiq_prd_type: 1 for one camera, 2 for multi camera */
 	chosen {
 		bootargs = "loglevel=0 rootfstype=erofs rootflags=dax console=ttyFIQ0 root=/dev/rd0 snd_soc_core.prealloc_buffer_size_kbytes=16 coherent_pool=0 driver_async_probe=dwmmc_rockchip";
 	};
@@ -146,6 +147,10 @@
 	};
 };
 
+&thunder_boot_service {
+	status = "okay";
+};
+
 &u2phy_otg {
 	status = "okay";
 };
diff --git a/arch/arm/boot/dts/rv1106g-smart-door-lock-rmsl-v12.dts b/arch/arm/boot/dts/rv1106g-smart-door-lock-rmsl-v12.dts
new file mode 100644
index 000000000000..416592ee052d
--- /dev/null
+++ b/arch/arm/boot/dts/rv1106g-smart-door-lock-rmsl-v12.dts
@@ -0,0 +1,37 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2022 Rockchip Electronics Co., Ltd.
+ */
+
+/dts-v1/;
+
+#include "rv1106g-smart-door-lock-rmsl-v10.dts"
+
+/ {
+	model = "Rockchip RV1106G Smart Door Lock RMSL V12 Board";
+	compatible = "rockchip,rv1106g-smart-door-lock-rmsl-v12", "rockchip,rv1106";
+};
+
+&sdio {
+	max-frequency = <50000000>;
+	bus-width = <1>;
+	cap-sd-highspeed;
+	cap-sdio-irq;
+	keep-power-in-suspend;
+	non-removable;
+	rockchip,default-sample-phase = <90>;
+	no-mmc;
+	no-sd;
+	pinctrl-names = "default";
+	pinctrl-0 = <&sdmmc1m0_cmd &sdmmc1m0_clk &sdmmc1m0_bus1>;
+	status = "okay";
+};
+
+&sdmmc {
+	status = "disabled";
+};
+
+&vcsel_rk803 {
+	gpio-encc1-gpios = <&gpio2 RK_PA7 GPIO_ACTIVE_HIGH>; //Flood
+	gpio-encc2-gpios = <&gpio2 RK_PA0 GPIO_ACTIVE_HIGH>; //PRO
+};
diff --git a/arch/arm/configs/rk3126_linux.config b/arch/arm/configs/rk3126_linux.config
new file mode 100644
index 000000000000..6408ae272e57
--- /dev/null
+++ b/arch/arm/configs/rk3126_linux.config
@@ -0,0 +1,281 @@
+# CONFIG_ALLOW_DEV_COREDUMP is not set
+# CONFIG_ASHMEM is not set
+# CONFIG_BATTERY_SBS is not set
+# CONFIG_BLK_CGROUP is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_BT is not set
+# CONFIG_BUG_ON_DATA_CORRUPTION is not set
+# CONFIG_CGROUP_CPUACCT is not set
+# CONFIG_CGROUP_DEVICE is not set
+# CONFIG_CGROUP_FREEZER is not set
+# CONFIG_CGROUP_SCHED is not set
+# CONFIG_CHARGER_BQ24735 is not set
+# CONFIG_CHARGER_GPIO is not set
+# CONFIG_CPUSETS is not set
+# CONFIG_CPU_FREQ_STAT is not set
+# CONFIG_CPU_FREQ_TIMES is not set
+# CONFIG_CPU_RK3036 is not set
+# CONFIG_CPU_RK30XX is not set
+# CONFIG_CPU_RK3188 is not set
+# CONFIG_CPU_RK322X is not set
+# CONFIG_CPU_RK3288 is not set
+# CONFIG_CRC7 is not set
+# CONFIG_CRC_ITU_T is not set
+# CONFIG_CRC_T10DIF is not set
+# CONFIG_CRYPTO_CFB is not set
+# CONFIG_CRYPTO_CRCT10DIF is not set
+# CONFIG_CRYPTO_DES is not set
+# CONFIG_CRYPTO_ECB is not set
+# CONFIG_CRYPTO_ECDH is not set
+# CONFIG_CRYPTO_HW is not set
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_OFB is not set
+# CONFIG_CRYPTO_SHA1 is not set
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_SM3 is not set
+# CONFIG_CRYPTO_SM4 is not set
+# CONFIG_CRYPTO_USER_API_HASH is not set
+# CONFIG_CRYPTO_USER_API_SKCIPHER is not set
+# CONFIG_CRYPTO_XTS is not set
+# CONFIG_DEBUG_CREDENTIALS is not set
+CONFIG_DEBUG_GPIO=y
+# CONFIG_DEBUG_INFO is not set
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DNS_RESOLVER is not set
+# CONFIG_DRM_IGNORE_IOTCL_PERMIT is not set
+# CONFIG_DRM_LOAD_EDID_FIRMWARE is not set
+# CONFIG_ECRYPT_FS is not set
+# CONFIG_ETHERNET is not set
+# CONFIG_FB_MODE_HELPERS is not set
+# CONFIG_FIQ_DEBUGGER_TRUST_ZONE is not set
+# CONFIG_FUNCTION_TRACER is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_HID_APPLE is not set
+# CONFIG_HID_BATTERY_STRENGTH is not set
+# CONFIG_HID_CHERRY is not set
+# CONFIG_HID_KENSINGTON is not set
+# CONFIG_HID_MAGICMOUSE is not set
+# CONFIG_HID_MICROSOFT is not set
+# CONFIG_HID_MULTITOUCH is not set
+# CONFIG_HID_PLANTRONICS is not set
+# CONFIG_HID_PRIMAX is not set
+# CONFIG_HID_RMI is not set
+# CONFIG_HOSTAP is not set
+# CONFIG_HWMON is not set
+# CONFIG_I2C_HID is not set
+# CONFIG_I2C_STUB is not set
+# CONFIG_IKCONFIG is not set
+# CONFIG_INITRD_ASYNC is not set
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+# CONFIG_INPUT_UINPUT is not set
+# CONFIG_IOSCHED_BFQ is not set
+# CONFIG_IPV6 is not set
+# CONFIG_ISO9660_FS is not set
+# CONFIG_KERNEL_GZIP is not set
+CONFIG_KERNEL_LZ4=y
+# CONFIG_KEYBOARD_GPIO is not set
+# CONFIG_KEYBOARD_GPIO_POLLED is not set
+# CONFIG_MAC80211_DEBUGFS is not set
+# CONFIG_MAC80211_DEBUG_MENU is not set
+# CONFIG_MAC_PARTITION is not set
+# CONFIG_MALI_MIDGARD is not set
+# CONFIG_MDIO_DEVICE is not set
+# CONFIG_MEDIA_CEC_SUPPORT is not set
+# CONFIG_MEDIA_USB_SUPPORT is not set
+# CONFIG_MFD_TPS6586X is not set
+# CONFIG_MFD_TPS65910 is not set
+# CONFIG_MMC_TEST is not set
+# CONFIG_MODULE_FORCE_LOAD is not set
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+# CONFIG_MOUSE_CYAPA is not set
+# CONFIG_MOUSE_ELAN_I2C is not set
+# CONFIG_MWIFIEX is not set
+CONFIG_NAMESPACES=y
+# CONFIG_NETFILTER is not set
+# CONFIG_NETWORK_FILESYSTEMS is not set
+# CONFIG_NET_KEY is not set
+# CONFIG_NEW_LEDS is not set
+# CONFIG_NL80211_TESTMODE is not set
+# CONFIG_NLS_ASCII is not set
+CONFIG_NLS_DEFAULT="iso8859-1"
+# CONFIG_NLS_UTF8 is not set
+# CONFIG_PHYLIB is not set
+# CONFIG_PHY_ROCKCHIP_DP is not set
+# CONFIG_PHY_ROCKCHIP_INNO_HDMI is not set
+# CONFIG_PHY_ROCKCHIP_USB is not set
+# CONFIG_PINCTRL_RK805 is not set
+# CONFIG_PM_DEBUG is not set
+# CONFIG_POWER_RESET_GPIO_RESTART is not set
+# CONFIG_PPS is not set
+# CONFIG_PSI is not set
+# CONFIG_PTP_1588_CLOCK is not set
+# CONFIG_RD_XZ is not set
+# CONFIG_REGULATOR_ACT8865 is not set
+# CONFIG_REGULATOR_FAN53555 is not set
+# CONFIG_RELAY is not set
+# CONFIG_RFKILL_RK is not set
+CONFIG_RK_CONSOLE_THREAD=y
+CONFIG_RK_HEADSET=y
+# CONFIG_RMI4_CORE is not set
+# CONFIG_ROCKCHIP_ANALOGIX_DP is not set
+# CONFIG_ROCKCHIP_DDRCLK_SIP_V2 is not set
+# CONFIG_ROCKCHIP_DW_HDMI is not set
+# CONFIG_ROCKCHIP_INNO_HDMI is not set
+# CONFIG_ROCKCHIP_MPP_RKVDEC is not set
+# CONFIG_ROCKCHIP_MPP_RKVENC is not set
+# CONFIG_ROCKCHIP_MPP_VDPU2 is not set
+# CONFIG_ROCKCHIP_MPP_VEPU2 is not set
+# CONFIG_ROCKCHIP_PLL_RK3066 is not set
+# CONFIG_ROCKCHIP_VENDOR_STORAGE_UPDATE_LOADER is not set
+# CONFIG_RT2X00 is not set
+# CONFIG_RTC_DRV_HYM8563 is not set
+CONFIG_RUNTIME_TESTING_MENU=y
+# CONFIG_SCHED_DEBUG is not set
+# CONFIG_SCHED_STACK_END_CHECK is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITYFS is not set
+# CONFIG_SENSORS_ISL29018 is not set
+# CONFIG_SENSORS_TSL2563 is not set
+CONFIG_SENSOR_DEVICE=y
+# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set
+# CONFIG_SERIAL_OF_PLATFORM is not set
+# CONFIG_SLUB_DEBUG is not set
+# CONFIG_SND_SOC_ES8323 is not set
+# CONFIG_SND_SOC_ES8396 is not set
+# CONFIG_SND_SOC_ROCKCHIP_MAX98090 is not set
+# CONFIG_SND_SOC_ROCKCHIP_RT5645 is not set
+# CONFIG_SND_SOC_RT5616 is not set
+# CONFIG_SND_SOC_RT5640 is not set
+# CONFIG_SND_SOC_TS3A227E is not set
+# CONFIG_SND_USB_AUDIO is not set
+# CONFIG_SPI_SPIDEV is not set
+CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU=y
+# CONFIG_SQUASHFS_DECOMP_SINGLE is not set
+CONFIG_STAGING_MEDIA=y
+# CONFIG_TCG_TPM is not set
+# CONFIG_TEE is not set
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_TMPFS_XATTR is not set
+# CONFIG_TOUCHSCREEN_ATMEL_MXT is not set
+# CONFIG_TOUCHSCREEN_ELAN is not set
+# CONFIG_TOUCHSCREEN_GSL3673 is not set
+# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
+# CONFIG_TSL2583 is not set
+# CONFIG_UDF_FS is not set
+# CONFIG_UNWINDER_FRAME_POINTER is not set
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
+# CONFIG_USB_CONFIGFS_ACM is not set
+CONFIG_USB_DEFAULT_PERSIST=y
+# CONFIG_USB_EHCI_ROOT_HUB_TT is not set
+# CONFIG_USB_EZUSB_FX2 is not set
+# CONFIG_USB_HIDDEV is not set
+# CONFIG_USB_MON is not set
+# CONFIG_USB_NET_RNDIS_WLAN is not set
+# CONFIG_USB_OTG is not set
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_RTL8150 is not set
+# CONFIG_USB_RTL8152 is not set
+# CONFIG_USB_SERIAL is not set
+# CONFIG_USB_USBNET is not set
+# CONFIG_USB_WDM is not set
+# CONFIG_V4L_TEST_DRIVERS is not set
+CONFIG_VIDEO_GC2145=y
+# CONFIG_VIDEO_IMX219 is not set
+# CONFIG_VIDEO_OV13850 is not set
+# CONFIG_VIDEO_OV5647 is not set
+# CONFIG_VIDEO_OV8858 is not set
+# CONFIG_VIDEO_SGM3784 is not set
+CONFIG_WIFI_GENERATE_RANDOM_MAC_ADDR=y
+# CONFIG_XZ_DEC is not set
+# CONFIG_ANGLE_DEVICE is not set
+CONFIG_ARM_UNWIND=y
+# CONFIG_ATOMIC64_SELFTEST is not set
+# CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_BMA2XX_ACC is not set
+# CONFIG_COMPASS_DEVICE is not set
+CONFIG_ENABLE_DEFAULT_TRACERS=y
+# CONFIG_FIND_BIT_BENCHMARK is not set
+CONFIG_GSENSOR_DEVICE=y
+# CONFIG_GS_BMA023 is not set
+# CONFIG_GS_DA215S is not set
+# CONFIG_GS_DA223 is not set
+# CONFIG_GS_DA228E is not set
+# CONFIG_GS_DMT10 is not set
+# CONFIG_GS_KXTIK is not set
+# CONFIG_GS_KXTJ9 is not set
+# CONFIG_GS_LIS3DH is not set
+# CONFIG_GS_LSM303D is not set
+# CONFIG_GS_MC3230 is not set
+CONFIG_GS_MMA7660=y
+# CONFIG_GS_MMA8452 is not set
+# CONFIG_GS_MXC6225 is not set
+# CONFIG_GS_MXC6655XA is not set
+# CONFIG_GS_SC7660 is not set
+# CONFIG_GS_SC7A20 is not set
+# CONFIG_GS_SC7A30 is not set
+# CONFIG_GYROSCOPE_DEVICE is not set
+# CONFIG_HALL_DEVICE is not set
+# CONFIG_ICM2060X_ACC is not set
+CONFIG_INLINE_READ_UNLOCK=y
+CONFIG_INLINE_READ_UNLOCK_IRQ=y
+CONFIG_INLINE_SPIN_UNLOCK_IRQ=y
+CONFIG_INLINE_WRITE_UNLOCK=y
+CONFIG_INLINE_WRITE_UNLOCK_IRQ=y
+# CONFIG_INTERVAL_TREE_TEST is not set
+CONFIG_IPC_NS=y
+# CONFIG_LIGHT_DEVICE is not set
+# CONFIG_LKDTM is not set
+# CONFIG_LSM330_ACC is not set
+# CONFIG_MPU6500_ACC is not set
+# CONFIG_MPU6880_ACC is not set
+CONFIG_NET_NS=y
+# CONFIG_PERCPU_TEST is not set
+CONFIG_PID_NS=y
+# CONFIG_PRESSURE_DEVICE is not set
+# CONFIG_PROXIMITY_DEVICE is not set
+# CONFIG_RBTREE_TEST is not set
+# CONFIG_REED_SOLOMON_TEST is not set
+# CONFIG_STK8BAXX_ACC is not set
+# CONFIG_TEMPERATURE_DEVICE is not set
+# CONFIG_TEST_BITMAP is not set
+# CONFIG_TEST_BITOPS is not set
+# CONFIG_TEST_BLACKHOLE_DEV is not set
+# CONFIG_TEST_BPF is not set
+# CONFIG_TEST_FIRMWARE is not set
+# CONFIG_TEST_FREE_PAGES is not set
+# CONFIG_TEST_HASH is not set
+# CONFIG_TEST_HEXDUMP is not set
+# CONFIG_TEST_IDA is not set
+# CONFIG_TEST_KMOD is not set
+# CONFIG_TEST_KSTRTOX is not set
+# CONFIG_TEST_LIST_SORT is not set
+# CONFIG_TEST_LKM is not set
+# CONFIG_TEST_MEMCAT_P is not set
+# CONFIG_TEST_MEMINIT is not set
+# CONFIG_TEST_MIN_HEAP is not set
+# CONFIG_TEST_OVERFLOW is not set
+# CONFIG_TEST_PRINTF is not set
+# CONFIG_TEST_RHASHTABLE is not set
+# CONFIG_TEST_SORT is not set
+# CONFIG_TEST_STACKINIT is not set
+# CONFIG_TEST_STATIC_KEYS is not set
+# CONFIG_TEST_STRING_HELPERS is not set
+# CONFIG_TEST_STRSCPY is not set
+# CONFIG_TEST_SYSCTL is not set
+# CONFIG_TEST_UDELAY is not set
+# CONFIG_TEST_USER_COPY is not set
+# CONFIG_TEST_UUID is not set
+# CONFIG_TEST_VMALLOC is not set
+# CONFIG_TEST_XARRAY is not set
+CONFIG_UNWINDER_ARM=y
+CONFIG_USER_NS=y
+CONFIG_UTS_NS=y
+CONFIG_VIDEOBUF2_DMA_CONTIG=y
+# CONFIG_VIDEO_HANTRO is not set
+CONFIG_VIDEO_ROCKCHIP_ISP1=y
+# CONFIG_VIDEO_ROCKCHIP_VDEC is not set
diff --git a/arch/arm/configs/rk3126_linux_slc_nand.config b/arch/arm/configs/rk3126_linux_slc_nand.config
new file mode 100644
index 000000000000..acc66a32ccea
--- /dev/null
+++ b/arch/arm/configs/rk3126_linux_slc_nand.config
@@ -0,0 +1,348 @@
+# CONFIG_ALLOW_DEV_COREDUMP is not set
+# CONFIG_ASHMEM is not set
+# CONFIG_BATTERY_SBS is not set
+# CONFIG_BLK_CGROUP is not set
+CONFIG_BLK_CMDLINE_PARSER=y
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_BT is not set
+# CONFIG_BUG_ON_DATA_CORRUPTION is not set
+# CONFIG_CGROUP_CPUACCT is not set
+# CONFIG_CGROUP_DEVICE is not set
+# CONFIG_CGROUP_FREEZER is not set
+# CONFIG_CGROUP_SCHED is not set
+# CONFIG_CHARGER_BQ24735 is not set
+# CONFIG_CHARGER_GPIO is not set
+CONFIG_CMDLINE_PARTITION=y
+# CONFIG_CPUSETS is not set
+# CONFIG_CPU_FREQ_STAT is not set
+# CONFIG_CPU_FREQ_TIMES is not set
+# CONFIG_CPU_RK3036 is not set
+# CONFIG_CPU_RK30XX is not set
+# CONFIG_CPU_RK3188 is not set
+# CONFIG_CPU_RK322X is not set
+# CONFIG_CPU_RK3288 is not set
+# CONFIG_CRC7 is not set
+# CONFIG_CRC_ITU_T is not set
+# CONFIG_CRC_T10DIF is not set
+# CONFIG_CRYPTO_CFB is not set
+# CONFIG_CRYPTO_CRCT10DIF is not set
+# CONFIG_CRYPTO_DES is not set
+# CONFIG_CRYPTO_ECB is not set
+# CONFIG_CRYPTO_ECDH is not set
+# CONFIG_CRYPTO_HW is not set
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_OFB is not set
+# CONFIG_CRYPTO_SHA1 is not set
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_SM3 is not set
+# CONFIG_CRYPTO_SM4 is not set
+# CONFIG_CRYPTO_USER_API_HASH is not set
+# CONFIG_CRYPTO_USER_API_SKCIPHER is not set
+# CONFIG_CRYPTO_XTS is not set
+CONFIG_CRYPTO_ZSTD=y
+# CONFIG_DEBUG_CREDENTIALS is not set
+CONFIG_DEBUG_GPIO=y
+# CONFIG_DEBUG_INFO is not set
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DNS_RESOLVER is not set
+# CONFIG_DRM_IGNORE_IOTCL_PERMIT is not set
+# CONFIG_DRM_LOAD_EDID_FIRMWARE is not set
+# CONFIG_ECRYPT_FS is not set
+# CONFIG_ETHERNET is not set
+# CONFIG_FB_MODE_HELPERS is not set
+# CONFIG_FIQ_DEBUGGER_TRUST_ZONE is not set
+# CONFIG_FUNCTION_TRACER is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_HID_APPLE is not set
+# CONFIG_HID_BATTERY_STRENGTH is not set
+# CONFIG_HID_CHERRY is not set
+# CONFIG_HID_KENSINGTON is not set
+# CONFIG_HID_MAGICMOUSE is not set
+# CONFIG_HID_MICROSOFT is not set
+# CONFIG_HID_MULTITOUCH is not set
+# CONFIG_HID_PLANTRONICS is not set
+# CONFIG_HID_PRIMAX is not set
+# CONFIG_HID_RMI is not set
+# CONFIG_HOSTAP is not set
+# CONFIG_HWMON is not set
+# CONFIG_I2C_HID is not set
+# CONFIG_I2C_STUB is not set
+# CONFIG_IKCONFIG is not set
+# CONFIG_INITRD_ASYNC is not set
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+# CONFIG_INPUT_UINPUT is not set
+# CONFIG_IOSCHED_BFQ is not set
+# CONFIG_IPV6 is not set
+# CONFIG_ISO9660_FS is not set
+# CONFIG_KERNEL_GZIP is not set
+CONFIG_KERNEL_LZ4=y
+# CONFIG_KEYBOARD_GPIO is not set
+# CONFIG_KEYBOARD_GPIO_POLLED is not set
+# CONFIG_MAC80211_DEBUGFS is not set
+# CONFIG_MAC80211_DEBUG_MENU is not set
+# CONFIG_MAC_PARTITION is not set
+# CONFIG_MALI_MIDGARD is not set
+# CONFIG_MDIO_DEVICE is not set
+# CONFIG_MEDIA_CEC_SUPPORT is not set
+# CONFIG_MEDIA_USB_SUPPORT is not set
+# CONFIG_MFD_TPS6586X is not set
+# CONFIG_MFD_TPS65910 is not set
+# CONFIG_MMC_TEST is not set
+# CONFIG_MODULE_FORCE_LOAD is not set
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+# CONFIG_MOUSE_CYAPA is not set
+# CONFIG_MOUSE_ELAN_I2C is not set
+CONFIG_MTD=y
+# CONFIG_MWIFIEX is not set
+CONFIG_NAMESPACES=y
+# CONFIG_NETFILTER is not set
+# CONFIG_NETWORK_FILESYSTEMS is not set
+# CONFIG_NET_KEY is not set
+# CONFIG_NEW_LEDS is not set
+# CONFIG_NL80211_TESTMODE is not set
+# CONFIG_NLS_ASCII is not set
+CONFIG_NLS_DEFAULT="iso8859-1"
+# CONFIG_NLS_UTF8 is not set
+# CONFIG_PHYLIB is not set
+# CONFIG_PHY_ROCKCHIP_DP is not set
+# CONFIG_PHY_ROCKCHIP_INNO_HDMI is not set
+# CONFIG_PHY_ROCKCHIP_USB is not set
+# CONFIG_PINCTRL_RK805 is not set
+# CONFIG_PM_DEBUG is not set
+# CONFIG_POWER_RESET_GPIO_RESTART is not set
+# CONFIG_PPS is not set
+# CONFIG_PSI is not set
+# CONFIG_PTP_1588_CLOCK is not set
+# CONFIG_RD_XZ is not set
+# CONFIG_REGULATOR_ACT8865 is not set
+# CONFIG_REGULATOR_FAN53555 is not set
+# CONFIG_RELAY is not set
+# CONFIG_RFKILL_RK is not set
+CONFIG_RK_CONSOLE_THREAD=y
+CONFIG_RK_HEADSET=y
+# CONFIG_RK_NAND is not set
+# CONFIG_RMI4_CORE is not set
+# CONFIG_ROCKCHIP_ANALOGIX_DP is not set
+# CONFIG_ROCKCHIP_DDRCLK_SIP_V2 is not set
+# CONFIG_ROCKCHIP_DW_HDMI is not set
+# CONFIG_ROCKCHIP_EFUSE is not set
+# CONFIG_ROCKCHIP_INNO_HDMI is not set
+# CONFIG_ROCKCHIP_MPP_RKVDEC is not set
+# CONFIG_ROCKCHIP_MPP_RKVENC is not set
+# CONFIG_ROCKCHIP_MPP_VDPU2 is not set
+# CONFIG_ROCKCHIP_MPP_VEPU2 is not set
+# CONFIG_ROCKCHIP_PLL_RK3066 is not set
+# CONFIG_ROCKCHIP_VENDOR_STORAGE_UPDATE_LOADER is not set
+# CONFIG_RT2X00 is not set
+# CONFIG_RTC_DRV_HYM8563 is not set
+CONFIG_RUNTIME_TESTING_MENU=y
+# CONFIG_SCHED_DEBUG is not set
+# CONFIG_SCHED_STACK_END_CHECK is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITYFS is not set
+# CONFIG_SENSORS_ISL29018 is not set
+# CONFIG_SENSORS_TSL2563 is not set
+CONFIG_SENSOR_DEVICE=y
+# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set
+# CONFIG_SERIAL_OF_PLATFORM is not set
+# CONFIG_SLUB_DEBUG is not set
+# CONFIG_SND_SOC_ES8323 is not set
+# CONFIG_SND_SOC_ES8396 is not set
+# CONFIG_SND_SOC_ROCKCHIP_MAX98090 is not set
+# CONFIG_SND_SOC_ROCKCHIP_RT5645 is not set
+# CONFIG_SND_SOC_RT5616 is not set
+# CONFIG_SND_SOC_RT5640 is not set
+# CONFIG_SND_SOC_TS3A227E is not set
+# CONFIG_SND_USB_AUDIO is not set
+# CONFIG_SPI_SPIDEV is not set
+CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU=y
+# CONFIG_SQUASHFS_DECOMP_SINGLE is not set
+CONFIG_STAGING_MEDIA=y
+# CONFIG_TCG_TPM is not set
+# CONFIG_TEE is not set
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_TMPFS_XATTR is not set
+# CONFIG_TOUCHSCREEN_ATMEL_MXT is not set
+# CONFIG_TOUCHSCREEN_ELAN is not set
+# CONFIG_TOUCHSCREEN_GSL3673 is not set
+# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
+# CONFIG_TSL2583 is not set
+# CONFIG_UDF_FS is not set
+# CONFIG_UNWINDER_FRAME_POINTER is not set
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
+# CONFIG_USB_CONFIGFS_ACM is not set
+CONFIG_USB_DEFAULT_PERSIST=y
+# CONFIG_USB_EHCI_ROOT_HUB_TT is not set
+# CONFIG_USB_EZUSB_FX2 is not set
+# CONFIG_USB_HIDDEV is not set
+# CONFIG_USB_MON is not set
+# CONFIG_USB_NET_RNDIS_WLAN is not set
+# CONFIG_USB_OTG is not set
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_RTL8150 is not set
+# CONFIG_USB_RTL8152 is not set
+# CONFIG_USB_SERIAL is not set
+# CONFIG_USB_USBNET is not set
+# CONFIG_USB_WDM is not set
+# CONFIG_V4L_TEST_DRIVERS is not set
+CONFIG_VIDEO_GC2145=y
+# CONFIG_VIDEO_IMX219 is not set
+# CONFIG_VIDEO_OV13850 is not set
+# CONFIG_VIDEO_OV5647 is not set
+# CONFIG_VIDEO_OV8858 is not set
+# CONFIG_VIDEO_SGM3784 is not set
+CONFIG_WIFI_GENERATE_RANDOM_MAC_ADDR=y
+# CONFIG_XZ_DEC is not set
+# CONFIG_ANGLE_DEVICE is not set
+CONFIG_ARM_UNWIND=y
+# CONFIG_ATOMIC64_SELFTEST is not set
+# CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_BMA2XX_ACC is not set
+# CONFIG_COMPASS_DEVICE is not set
+CONFIG_ENABLE_DEFAULT_TRACERS=y
+# CONFIG_FIND_BIT_BENCHMARK is not set
+# CONFIG_FTL is not set
+CONFIG_GSENSOR_DEVICE=y
+# CONFIG_GS_BMA023 is not set
+# CONFIG_GS_DA215S is not set
+# CONFIG_GS_DA223 is not set
+# CONFIG_GS_DA228E is not set
+# CONFIG_GS_DMT10 is not set
+# CONFIG_GS_KXTIK is not set
+# CONFIG_GS_KXTJ9 is not set
+# CONFIG_GS_LIS3DH is not set
+# CONFIG_GS_LSM303D is not set
+# CONFIG_GS_MC3230 is not set
+CONFIG_GS_MMA7660=y
+# CONFIG_GS_MMA8452 is not set
+# CONFIG_GS_MXC6225 is not set
+# CONFIG_GS_MXC6655XA is not set
+# CONFIG_GS_SC7660 is not set
+# CONFIG_GS_SC7A20 is not set
+# CONFIG_GS_SC7A30 is not set
+# CONFIG_GYROSCOPE_DEVICE is not set
+# CONFIG_HALL_DEVICE is not set
+# CONFIG_ICM2060X_ACC is not set
+# CONFIG_INFTL is not set
+CONFIG_INLINE_READ_UNLOCK=y
+CONFIG_INLINE_READ_UNLOCK_IRQ=y
+CONFIG_INLINE_SPIN_UNLOCK_IRQ=y
+CONFIG_INLINE_WRITE_UNLOCK=y
+CONFIG_INLINE_WRITE_UNLOCK_IRQ=y
+# CONFIG_INTERVAL_TREE_TEST is not set
+CONFIG_IPC_NS=y
+# CONFIG_JFFS2_FS is not set
+# CONFIG_LIGHT_DEVICE is not set
+# CONFIG_LKDTM is not set
+# CONFIG_LSM330_ACC is not set
+# CONFIG_MPU6500_ACC is not set
+# CONFIG_MPU6880_ACC is not set
+# CONFIG_MTD_ABSENT is not set
+# CONFIG_MTD_AFS_PARTS is not set
+# CONFIG_MTD_AR7_PARTS is not set
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_MTD_BLOCK2MTD is not set
+# CONFIG_MTD_CFI is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+CONFIG_MTD_CMDLINE_PARTS=y
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+# CONFIG_MTD_DATAFLASH is not set
+# CONFIG_MTD_DOCG3 is not set
+# CONFIG_MTD_HYPERBUS is not set
+# CONFIG_MTD_JEDECPROBE is not set
+# CONFIG_MTD_LPDDR is not set
+# CONFIG_MTD_LPDDR2_NVM is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MCHP23K256 is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_OF_PARTS is not set
+# CONFIG_MTD_ONENAND is not set
+# CONFIG_MTD_OOPS is not set
+CONFIG_MTD_PARTITIONED_MASTER=y
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_PLATRAM is not set
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_RAW_NAND is not set
+# CONFIG_MTD_REDBOOT_PARTS is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_SPI_NAND is not set
+# CONFIG_MTD_SPI_NOR is not set
+# CONFIG_MTD_SST25L is not set
+# CONFIG_MTD_SWAP is not set
+# CONFIG_MTD_TESTS is not set
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_BEB_LIMIT=20
+CONFIG_MTD_UBI_BLOCK=y
+# CONFIG_MTD_UBI_FASTMAP is not set
+# CONFIG_MTD_UBI_GLUEBI is not set
+CONFIG_MTD_UBI_WL_THRESHOLD=4096
+CONFIG_NET_NS=y
+# CONFIG_NFTL is not set
+# CONFIG_PERCPU_TEST is not set
+CONFIG_PID_NS=y
+# CONFIG_PRESSURE_DEVICE is not set
+# CONFIG_PROXIMITY_DEVICE is not set
+# CONFIG_RBTREE_TEST is not set
+# CONFIG_REED_SOLOMON_TEST is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SM_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_STK8BAXX_ACC is not set
+# CONFIG_TEMPERATURE_DEVICE is not set
+# CONFIG_TEST_BITMAP is not set
+# CONFIG_TEST_BITOPS is not set
+# CONFIG_TEST_BLACKHOLE_DEV is not set
+# CONFIG_TEST_BPF is not set
+# CONFIG_TEST_FIRMWARE is not set
+# CONFIG_TEST_FREE_PAGES is not set
+# CONFIG_TEST_HASH is not set
+# CONFIG_TEST_HEXDUMP is not set
+# CONFIG_TEST_IDA is not set
+# CONFIG_TEST_KMOD is not set
+# CONFIG_TEST_KSTRTOX is not set
+# CONFIG_TEST_LIST_SORT is not set
+# CONFIG_TEST_LKM is not set
+# CONFIG_TEST_MEMCAT_P is not set
+# CONFIG_TEST_MEMINIT is not set
+# CONFIG_TEST_MIN_HEAP is not set
+# CONFIG_TEST_OVERFLOW is not set
+# CONFIG_TEST_PRINTF is not set
+# CONFIG_TEST_RHASHTABLE is not set
+# CONFIG_TEST_SORT is not set
+# CONFIG_TEST_STACKINIT is not set
+# CONFIG_TEST_STATIC_KEYS is not set
+# CONFIG_TEST_STRING_HELPERS is not set
+# CONFIG_TEST_STRSCPY is not set
+# CONFIG_TEST_SYSCTL is not set
+# CONFIG_TEST_UDELAY is not set
+# CONFIG_TEST_USER_COPY is not set
+# CONFIG_TEST_UUID is not set
+# CONFIG_TEST_VMALLOC is not set
+# CONFIG_TEST_XARRAY is not set
+# CONFIG_UBIFS_ATIME_SUPPORT is not set
+CONFIG_UBIFS_FS=y
+CONFIG_UBIFS_FS_ADVANCED_COMPR=y
+# CONFIG_UBIFS_FS_AUTHENTICATION is not set
+CONFIG_UBIFS_FS_LZO=y
+CONFIG_UBIFS_FS_SECURITY=y
+CONFIG_UBIFS_FS_XATTR=y
+CONFIG_UBIFS_FS_ZLIB=y
+CONFIG_UBIFS_FS_ZSTD=y
+CONFIG_UNWINDER_ARM=y
+CONFIG_USER_NS=y
+CONFIG_UTS_NS=y
+CONFIG_VIDEOBUF2_DMA_CONTIG=y
+# CONFIG_VIDEO_HANTRO is not set
+CONFIG_VIDEO_ROCKCHIP_ISP1=y
+# CONFIG_VIDEO_ROCKCHIP_VDEC is not set
+CONFIG_ZSTD_COMPRESS=y
diff --git a/arch/arm/configs/rk3128_linux.config b/arch/arm/configs/rk3128_linux.config
new file mode 100644
index 000000000000..ec0f007d2a41
--- /dev/null
+++ b/arch/arm/configs/rk3128_linux.config
@@ -0,0 +1,166 @@
+# CONFIG_BLK_CGROUP is not set
+# CONFIG_BUG_ON_DATA_CORRUPTION is not set
+# CONFIG_CGROUP_CPUACCT is not set
+# CONFIG_CGROUP_DEVICE is not set
+# CONFIG_CGROUP_FREEZER is not set
+# CONFIG_CGROUP_SCHED is not set
+# CONFIG_CPUSETS is not set
+# CONFIG_CPU_FREQ_STAT is not set
+# CONFIG_CPU_FREQ_TIMES is not set
+# CONFIG_CPU_RK3036 is not set
+# CONFIG_CPU_RK30XX is not set
+# CONFIG_CPU_RK3188 is not set
+# CONFIG_CPU_RK322X is not set
+# CONFIG_CPU_RK3288 is not set
+# CONFIG_CRYPTO_CFB is not set
+# CONFIG_CRYPTO_DES is not set
+# CONFIG_CRYPTO_DEV_ROCKCHIP is not set
+# CONFIG_CRYPTO_OFB is not set
+# CONFIG_CRYPTO_SHA1 is not set
+# CONFIG_CRYPTO_SM3 is not set
+# CONFIG_CRYPTO_SM4 is not set
+# CONFIG_CRYPTO_XTS is not set
+CONFIG_DEBUG_GPIO=y
+# CONFIG_DEBUG_LIST is not set
+CONFIG_DETECT_HUNG_TASK=y
+# CONFIG_DNS_RESOLVER is not set
+# CONFIG_DRM_IGNORE_IOTCL_PERMIT is not set
+# CONFIG_DRM_LOAD_EDID_FIRMWARE is not set
+CONFIG_DRM_UDL=y
+# CONFIG_ECRYPT_FS is not set
+# CONFIG_IEP is not set
+# CONFIG_IKCONFIG is not set
+# CONFIG_INITRD_ASYNC is not set
+# CONFIG_INPUT_TABLET is not set
+# CONFIG_IOSCHED_BFQ is not set
+# CONFIG_MALI_MIDGARD is not set
+# CONFIG_MODULE_FORCE_LOAD is not set
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+CONFIG_NAMESPACES=y
+# CONFIG_NETWORK_FILESYSTEMS is not set
+# CONFIG_PINCTRL_RK805 is not set
+# CONFIG_PM_DEBUG is not set
+# CONFIG_PSI is not set
+# CONFIG_RFKILL_RK is not set
+CONFIG_RK_HEADSET=y
+# CONFIG_ROCKCHIP_ANALOGIX_DP is not set
+# CONFIG_ROCKCHIP_DDRCLK_SIP_V2 is not set
+# CONFIG_ROCKCHIP_DW_HDMI is not set
+# CONFIG_ROCKCHIP_MPP_SERVICE is not set
+# CONFIG_ROCKCHIP_MULTI_RGA is not set
+# CONFIG_ROCKCHIP_PLL_RK3066 is not set
+CONFIG_ROCKCHIP_REMOTECTL=y
+CONFIG_ROCKCHIP_RGA=y
+# CONFIG_ROCKCHIP_VENDOR_STORAGE_UPDATE_LOADER is not set
+CONFIG_RUNTIME_TESTING_MENU=y
+# CONFIG_SCHED_STACK_END_CHECK is not set
+CONFIG_SENSOR_DEVICE=y
+# CONFIG_SERIAL_OF_PLATFORM is not set
+CONFIG_SND_SOC_ROCKCHIP_MULTICODECS=y
+CONFIG_SOFTLOCKUP_DETECTOR=y
+# CONFIG_SPI_SPIDEV is not set
+CONFIG_STAGING_MEDIA=y
+# CONFIG_TEE is not set
+# CONFIG_TOUCHSCREEN_ATMEL_MXT is not set
+# CONFIG_TOUCHSCREEN_ELAN is not set
+# CONFIG_TOUCHSCREEN_GSL3673 is not set
+# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_EZUSB_FX2 is not set
+# CONFIG_USB_SERIAL is not set
+# CONFIG_V4L_TEST_DRIVERS is not set
+CONFIG_VIDEO_GC2145=y
+# CONFIG_VIDEO_IMX219 is not set
+# CONFIG_VIDEO_OV13850 is not set
+# CONFIG_VIDEO_OV5647 is not set
+# CONFIG_VIDEO_OV8858 is not set
+# CONFIG_VIDEO_SGM3784 is not set
+CONFIG_WIFI_GENERATE_RANDOM_MAC_ADDR=y
+# CONFIG_ANGLE_DEVICE is not set
+# CONFIG_ATOMIC64_SELFTEST is not set
+# CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_BMA2XX_ACC is not set
+CONFIG_BOOTPARAM_HUNG_TASK_PANIC=y
+CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=1
+CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC=y
+CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=1
+# CONFIG_COMPASS_DEVICE is not set
+CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=120
+CONFIG_DRM_GEM_SHMEM_HELPER=y
+# CONFIG_FIND_BIT_BENCHMARK is not set
+CONFIG_GSENSOR_DEVICE=y
+# CONFIG_GS_BMA023 is not set
+# CONFIG_GS_DA215S is not set
+# CONFIG_GS_DA223 is not set
+# CONFIG_GS_DA228E is not set
+# CONFIG_GS_DMT10 is not set
+# CONFIG_GS_KXTIK is not set
+# CONFIG_GS_KXTJ9 is not set
+# CONFIG_GS_LIS3DH is not set
+# CONFIG_GS_LSM303D is not set
+# CONFIG_GS_MC3230 is not set
+CONFIG_GS_MMA7660=y
+# CONFIG_GS_MMA8452 is not set
+# CONFIG_GS_MXC6225 is not set
+# CONFIG_GS_MXC6655XA is not set
+# CONFIG_GS_SC7660 is not set
+# CONFIG_GS_SC7A20 is not set
+# CONFIG_GS_SC7A30 is not set
+# CONFIG_GYROSCOPE_DEVICE is not set
+# CONFIG_HALL_DEVICE is not set
+# CONFIG_ICM2060X_ACC is not set
+# CONFIG_INTERVAL_TREE_TEST is not set
+CONFIG_IPC_NS=y
+# CONFIG_LIGHT_DEVICE is not set
+CONFIG_LKDTM=y
+CONFIG_LOCKUP_DETECTOR=y
+# CONFIG_LSM330_ACC is not set
+# CONFIG_MPU6500_ACC is not set
+# CONFIG_MPU6880_ACC is not set
+CONFIG_NET_NS=y
+# CONFIG_PERCPU_TEST is not set
+CONFIG_PID_NS=y
+# CONFIG_PRESSURE_DEVICE is not set
+# CONFIG_PROXIMITY_DEVICE is not set
+# CONFIG_RBTREE_TEST is not set
+# CONFIG_REED_SOLOMON_TEST is not set
+CONFIG_ROCKCHIP_REMOTECTL_PWM=y
+# CONFIG_ROCKCHIP_RGA2 is not set
+# CONFIG_STK8BAXX_ACC is not set
+# CONFIG_TEMPERATURE_DEVICE is not set
+# CONFIG_TEST_BITMAP is not set
+# CONFIG_TEST_BITOPS is not set
+# CONFIG_TEST_BLACKHOLE_DEV is not set
+# CONFIG_TEST_BPF is not set
+# CONFIG_TEST_FIRMWARE is not set
+# CONFIG_TEST_FREE_PAGES is not set
+# CONFIG_TEST_HASH is not set
+# CONFIG_TEST_HEXDUMP is not set
+# CONFIG_TEST_IDA is not set
+# CONFIG_TEST_KMOD is not set
+# CONFIG_TEST_KSTRTOX is not set
+# CONFIG_TEST_LIST_SORT is not set
+# CONFIG_TEST_LKM is not set
+# CONFIG_TEST_MEMCAT_P is not set
+# CONFIG_TEST_MEMINIT is not set
+# CONFIG_TEST_MIN_HEAP is not set
+# CONFIG_TEST_OVERFLOW is not set
+# CONFIG_TEST_PRINTF is not set
+# CONFIG_TEST_RHASHTABLE is not set
+# CONFIG_TEST_SORT is not set
+# CONFIG_TEST_STACKINIT is not set
+# CONFIG_TEST_STATIC_KEYS is not set
+# CONFIG_TEST_STRING_HELPERS is not set
+# CONFIG_TEST_STRSCPY is not set
+# CONFIG_TEST_SYSCTL is not set
+CONFIG_TEST_UDELAY=y
+# CONFIG_TEST_USER_COPY is not set
+# CONFIG_TEST_UUID is not set
+# CONFIG_TEST_VMALLOC is not set
+# CONFIG_TEST_XARRAY is not set
+CONFIG_USER_NS=y
+CONFIG_UTS_NS=y
+CONFIG_VIDEOBUF2_DMA_CONTIG=y
+# CONFIG_VIDEO_HANTRO is not set
+CONFIG_VIDEO_ROCKCHIP_ISP1=y
+# CONFIG_VIDEO_ROCKCHIP_VDEC is not set
diff --git a/arch/arm/configs/rockchip_defconfig b/arch/arm/configs/rockchip_defconfig
index 2c6e91b4c70c..fb7398f745a9 100644
--- a/arch/arm/configs/rockchip_defconfig
+++ b/arch/arm/configs/rockchip_defconfig
@@ -298,6 +298,7 @@ CONFIG_STMMAC_ETH=y
 # CONFIG_NET_VENDOR_SYNOPSYS is not set
 # CONFIG_NET_VENDOR_VIA is not set
 # CONFIG_NET_VENDOR_WIZNET is not set
+CONFIG_MOTORCOMM_PHY=y
 CONFIG_ROCKCHIP_PHY=y
 CONFIG_PPP=y
 CONFIG_PPP_BSDCOMP=y
diff --git a/arch/arm/configs/rockchip_linux_defconfig b/arch/arm/configs/rockchip_linux_defconfig
index b76d47e8528e..6e356c7533a3 100644
--- a/arch/arm/configs/rockchip_linux_defconfig
+++ b/arch/arm/configs/rockchip_linux_defconfig
@@ -174,6 +174,7 @@ CONFIG_TUN=y
 CONFIG_VETH=y
 CONFIG_EMAC_ROCKCHIP=y
 CONFIG_STMMAC_ETH=y
+CONFIG_MOTORCOMM_PHY=y
 CONFIG_ROCKCHIP_PHY=y
 CONFIG_PPP=y
 CONFIG_PPP_ASYNC=y
@@ -219,6 +220,8 @@ CONFIG_TOUCHSCREEN_GSL3673=y
 CONFIG_TOUCHSCREEN_GT1X=y
 CONFIG_TOUCHSCREEN_ELAN=y
 CONFIG_TOUCHSCREEN_USB_COMPOSITE=y
+CONFIG_ROCKCHIP_REMOTECTL=y
+CONFIG_ROCKCHIP_REMOTECTL_PWM=y
 CONFIG_INPUT_MISC=y
 CONFIG_INPUT_UINPUT=y
 CONFIG_INPUT_RK805_PWRKEY=y
@@ -272,8 +275,10 @@ CONFIG_USB_VIDEO_CLASS=y
 # CONFIG_USB_GSPCA is not set
 CONFIG_V4L_PLATFORM_DRIVERS=y
 CONFIG_VIDEO_ROCKCHIP_CIF=y
+CONFIG_VIDEO_ROCKCHIP_RKISP1=y
 CONFIG_V4L_MEM2MEM_DRIVERS=y
 CONFIG_V4L_TEST_DRIVERS=y
+CONFIG_VIDEO_GC8034=y
 CONFIG_VIDEO_IMX219=y
 CONFIG_VIDEO_OV5647=y
 CONFIG_VIDEO_OV8858=y
@@ -284,6 +289,7 @@ CONFIG_DRM_IGNORE_IOTCL_PERMIT=y
 CONFIG_DRM_LOAD_EDID_FIRMWARE=y
 CONFIG_DRM_ROCKCHIP=y
 CONFIG_ROCKCHIP_ANALOGIX_DP=y
+CONFIG_ROCKCHIP_DRM_TVE=y
 CONFIG_ROCKCHIP_DW_HDMI=y
 CONFIG_ROCKCHIP_DW_MIPI_DSI=y
 CONFIG_ROCKCHIP_INNO_HDMI=y
diff --git a/arch/arm/configs/rv1106-battery-ipc.config b/arch/arm/configs/rv1106-battery-ipc.config
index 73a839747d62..926a1e727a6a 100644
--- a/arch/arm/configs/rv1106-battery-ipc.config
+++ b/arch/arm/configs/rv1106-battery-ipc.config
@@ -1,3 +1,5 @@
+CONFIG_CRC16=m
+CONFIG_EXT4_FS=m
 CONFIG_FILE_LOCKING=y
 CONFIG_JFFS2_FS=y
 CONFIG_MAILBOX=y
@@ -87,11 +89,16 @@ CONFIG_VIDEO_SC3338=y
 # CONFIG_BSD_DISKLABEL is not set
 # CONFIG_EEPROM_93XX46 is not set
 # CONFIG_EEPROM_AT25 is not set
+# CONFIG_EXT4_DEBUG is not set
+# CONFIG_EXT4_FS_POSIX_ACL is not set
+# CONFIG_EXT4_FS_SECURITY is not set
+CONFIG_EXT4_USE_FOR_EXT2=y
 # CONFIG_EZX_PCAP is not set
 CONFIG_FAT_DEFAULT_CODEPAGE=936
 CONFIG_FAT_DEFAULT_IOCHARSET="cp936"
 CONFIG_FAT_DEFAULT_UTF8=y
 CONFIG_FAT_FS=m
+CONFIG_FS_MBCACHE=m
 # CONFIG_FXOS8700_SPI is not set
 # CONFIG_GPIO_74X164 is not set
 # CONFIG_GPIO_MAX3191X is not set
@@ -103,6 +110,8 @@ CONFIG_FAT_FS=m
 # CONFIG_IIO_SSP_SENSORHUB is not set
 # CONFIG_INV_ICM42600_SPI is not set
 # CONFIG_INV_MPU6050_SPI is not set
+CONFIG_JBD2=m
+# CONFIG_JBD2_DEBUG is not set
 # CONFIG_JFFS2_CMODE_FAVOURLZO is not set
 # CONFIG_JFFS2_CMODE_NONE is not set
 CONFIG_JFFS2_CMODE_PRIORITY=y
@@ -156,6 +165,7 @@ CONFIG_MANDATORY_FILE_LOCKING=y
 # CONFIG_MTD_MCHP23K256 is not set
 # CONFIG_MTD_SPI_NAND is not set
 CONFIG_MTD_SPI_NOR=m
+CONFIG_MTD_SPI_NOR_MISC=y
 # CONFIG_MTD_SPI_NOR_USE_4K_SECTORS is not set
 # CONFIG_MTD_SST25L is not set
 # CONFIG_PI433 is not set
diff --git a/arch/arm/configs/rv1106-cvr.config b/arch/arm/configs/rv1106-cvr.config
new file mode 100644
index 000000000000..b299b26a6f27
--- /dev/null
+++ b/arch/arm/configs/rv1106-cvr.config
@@ -0,0 +1,998 @@
+CONFIG_BACKLIGHT_CLASS_DEVICE=y
+CONFIG_CONFIGFS_FS=y
+CONFIG_CRC16=y
+CONFIG_CRYPTO=y
+CONFIG_DEBUG_FS=y
+CONFIG_DRM=y
+CONFIG_ELF_CORE=y
+CONFIG_EXPORTFS_BLOCK_OPS=y
+CONFIG_EXT4_FS=y
+CONFIG_EXTCON=y
+CONFIG_FB=y
+CONFIG_FILE_LOCKING=y
+CONFIG_I2C_GPIO=y
+CONFIG_I2C_MUX=y
+CONFIG_INPUT=y
+CONFIG_IPV6=m
+CONFIG_JFFS2_FS=y
+CONFIG_KCMP=y
+CONFIG_KEYS=y
+CONFIG_MMC=y
+CONFIG_MSDOS_PARTITION=y
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_UBI=y
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_NVMEM_SYSFS=y
+CONFIG_RK_CMA_PROCFS=y
+CONFIG_RK_DMABUF_PROCFS=y
+CONFIG_RK_MEMBLOCK_PROCFS=y
+CONFIG_ROCKCHIP_OPP=y
+CONFIG_ROCKCHIP_RGA_PROC_FS=y
+CONFIG_ROCKCHIP_RVE_PROC_FS=y
+CONFIG_ROCKCHIP_VENDOR_STORAGE=y
+CONFIG_RTC_DRV_ROCKCHIP=y
+CONFIG_SPI=y
+CONFIG_USB_SUPPORT=y
+CONFIG_VFAT_FS=y
+CONFIG_VIDEO_OS04A10=m
+CONFIG_VIDEO_SC3336=m
+CONFIG_VIDEO_SC4336=m
+CONFIG_VIDEO_SC530AI=m
+CONFIG_WIRELESS=y
+CONFIG_WLAN=y
+# CONFIG_6LOWPAN is not set
+# CONFIG_AD2S1200 is not set
+# CONFIG_AD2S1210 is not set
+# CONFIG_AD2S90 is not set
+# CONFIG_AD5360 is not set
+# CONFIG_AD5421 is not set
+# CONFIG_AD5449 is not set
+# CONFIG_AD5504 is not set
+# CONFIG_AD5592R is not set
+# CONFIG_AD5624R_SPI is not set
+# CONFIG_AD5686_SPI is not set
+# CONFIG_AD5755 is not set
+# CONFIG_AD5758 is not set
+# CONFIG_AD5761 is not set
+# CONFIG_AD5764 is not set
+# CONFIG_AD5770R is not set
+# CONFIG_AD5791 is not set
+# CONFIG_AD7124 is not set
+# CONFIG_AD7192 is not set
+# CONFIG_AD7266 is not set
+# CONFIG_AD7280 is not set
+# CONFIG_AD7292 is not set
+# CONFIG_AD7298 is not set
+# CONFIG_AD7303 is not set
+# CONFIG_AD7476 is not set
+# CONFIG_AD7606_IFACE_SPI is not set
+# CONFIG_AD7766 is not set
+# CONFIG_AD7768_1 is not set
+# CONFIG_AD7780 is not set
+# CONFIG_AD7791 is not set
+# CONFIG_AD7793 is not set
+# CONFIG_AD7816 is not set
+# CONFIG_AD7887 is not set
+# CONFIG_AD7923 is not set
+# CONFIG_AD7949 is not set
+# CONFIG_AD8366 is not set
+# CONFIG_AD8801 is not set
+# CONFIG_AD9523 is not set
+# CONFIG_AD9832 is not set
+# CONFIG_AD9834 is not set
+# CONFIG_ADF4350 is not set
+# CONFIG_ADF4371 is not set
+# CONFIG_ADIS16080 is not set
+# CONFIG_ADIS16130 is not set
+# CONFIG_ADIS16136 is not set
+# CONFIG_ADIS16201 is not set
+# CONFIG_ADIS16203 is not set
+# CONFIG_ADIS16209 is not set
+# CONFIG_ADIS16240 is not set
+# CONFIG_ADIS16260 is not set
+# CONFIG_ADIS16400 is not set
+# CONFIG_ADIS16460 is not set
+# CONFIG_ADIS16475 is not set
+# CONFIG_ADIS16480 is not set
+# CONFIG_ADXL345_SPI is not set
+# CONFIG_ADXL372_SPI is not set
+# CONFIG_ADXRS290 is not set
+# CONFIG_ADXRS450 is not set
+# CONFIG_AFE4403 is not set
+# CONFIG_AFS_FS is not set
+# CONFIG_APPLE_MFI_FASTCHARGE is not set
+# CONFIG_ARM_CRYPTO is not set
+# CONFIG_AS3935 is not set
+CONFIG_ASN1=y
+CONFIG_ASSOCIATIVE_ARRAY=y
+CONFIG_ASYMMETRIC_KEY_TYPE=y
+CONFIG_ASYMMETRIC_PUBLIC_KEY_SUBTYPE=y
+# CONFIG_BACKLIGHT_ADP8860 is not set
+# CONFIG_BACKLIGHT_ADP8870 is not set
+# CONFIG_BACKLIGHT_ARCXCNN is not set
+# CONFIG_BACKLIGHT_BD6107 is not set
+# CONFIG_BACKLIGHT_GPIO is not set
+# CONFIG_BACKLIGHT_KTD253 is not set
+# CONFIG_BACKLIGHT_LM3630A is not set
+# CONFIG_BACKLIGHT_LM3639 is not set
+# CONFIG_BACKLIGHT_LP855X is not set
+# CONFIG_BACKLIGHT_LV5207LP is not set
+CONFIG_BACKLIGHT_PWM=y
+# CONFIG_BACKLIGHT_QCOM_WLED is not set
+# CONFIG_BCMDHD is not set
+CONFIG_BLK_DEBUG_FS=y
+# CONFIG_BMA220 is not set
+# CONFIG_BMC150_MAGN_SPI is not set
+# CONFIG_BMI160_SPI is not set
+# CONFIG_BSD_DISKLABEL is not set
+# CONFIG_CEPH_FS is not set
+CONFIG_CFG80211=m
+# CONFIG_CFG80211_CERTIFICATION_ONUS is not set
+CONFIG_CFG80211_CRDA_SUPPORT=y
+# CONFIG_CFG80211_DEBUGFS is not set
+CONFIG_CFG80211_DEFAULT_PS=y
+# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set
+CONFIG_CFG80211_REQUIRE_SIGNED_REGDB=y
+CONFIG_CFG80211_USE_KERNEL_REGDB_KEYS=y
+# CONFIG_CFG80211_WEXT is not set
+# CONFIG_CHARGER_BQ24190 is not set
+# CONFIG_CIFS is not set
+CONFIG_CLZ_TAB=y
+# CONFIG_CMA_DEBUGFS is not set
+# CONFIG_CODA_FS is not set
+CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y
+# CONFIG_CRYPTO_842 is not set
+CONFIG_CRYPTO_ACOMP2=y
+# CONFIG_CRYPTO_ADIANTUM is not set
+CONFIG_CRYPTO_AEAD=m
+CONFIG_CRYPTO_AEAD2=y
+# CONFIG_CRYPTO_AEGIS128 is not set
+CONFIG_CRYPTO_AES=m
+# CONFIG_CRYPTO_AES_TI is not set
+CONFIG_CRYPTO_AKCIPHER=y
+CONFIG_CRYPTO_AKCIPHER2=y
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_ALGAPI2=y
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
+# CONFIG_CRYPTO_AUTHENC is not set
+# CONFIG_CRYPTO_BLAKE2B is not set
+# CONFIG_CRYPTO_BLAKE2S is not set
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+# CONFIG_CRYPTO_CBC is not set
+CONFIG_CRYPTO_CCM=m
+# CONFIG_CRYPTO_CFB is not set
+# CONFIG_CRYPTO_CHACHA20 is not set
+# CONFIG_CRYPTO_CHACHA20POLY1305 is not set
+CONFIG_CRYPTO_CMAC=m
+# CONFIG_CRYPTO_CRC32 is not set
+CONFIG_CRYPTO_CRC32C=y
+# CONFIG_CRYPTO_CRCT10DIF is not set
+# CONFIG_CRYPTO_CRYPTD is not set
+CONFIG_CRYPTO_CTR=m
+# CONFIG_CRYPTO_CTS is not set
+# CONFIG_CRYPTO_CURVE25519 is not set
+CONFIG_CRYPTO_DEFLATE=y
+# CONFIG_CRYPTO_DES is not set
+# CONFIG_CRYPTO_DH is not set
+# CONFIG_CRYPTO_DRBG_MENU is not set
+# CONFIG_CRYPTO_ECB is not set
+# CONFIG_CRYPTO_ECDH is not set
+# CONFIG_CRYPTO_ECHAINIV is not set
+# CONFIG_CRYPTO_ECRDSA is not set
+# CONFIG_CRYPTO_ESSIV is not set
+# CONFIG_CRYPTO_FCRYPT is not set
+CONFIG_CRYPTO_GCM=m
+CONFIG_CRYPTO_GF128MUL=m
+CONFIG_CRYPTO_GHASH=m
+CONFIG_CRYPTO_HASH=y
+CONFIG_CRYPTO_HASH2=y
+CONFIG_CRYPTO_HASH_INFO=y
+# CONFIG_CRYPTO_HMAC is not set
+# CONFIG_CRYPTO_HW is not set
+# CONFIG_CRYPTO_JITTERENTROPY is not set
+# CONFIG_CRYPTO_KEYWRAP is not set
+CONFIG_CRYPTO_KPP2=y
+CONFIG_CRYPTO_LIB_AES=m
+CONFIG_CRYPTO_LIB_ARC4=m
+# CONFIG_CRYPTO_LIB_BLAKE2S is not set
+# CONFIG_CRYPTO_LIB_CHACHA is not set
+# CONFIG_CRYPTO_LIB_CHACHA20POLY1305 is not set
+# CONFIG_CRYPTO_LIB_CURVE25519 is not set
+# CONFIG_CRYPTO_LIB_POLY1305 is not set
+CONFIG_CRYPTO_LIB_POLY1305_RSIZE=9
+CONFIG_CRYPTO_LIB_SHA256=m
+# CONFIG_CRYPTO_LRW is not set
+# CONFIG_CRYPTO_LZ4 is not set
+# CONFIG_CRYPTO_LZ4HC is not set
+CONFIG_CRYPTO_LZO=y
+CONFIG_CRYPTO_MANAGER=y
+CONFIG_CRYPTO_MANAGER2=y
+CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y
+# CONFIG_CRYPTO_MD4 is not set
+# CONFIG_CRYPTO_MD5 is not set
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+CONFIG_CRYPTO_NULL=m
+CONFIG_CRYPTO_NULL2=y
+# CONFIG_CRYPTO_OFB is not set
+# CONFIG_CRYPTO_PCBC is not set
+# CONFIG_CRYPTO_POLY1305 is not set
+# CONFIG_CRYPTO_RMD128 is not set
+# CONFIG_CRYPTO_RMD160 is not set
+# CONFIG_CRYPTO_RMD256 is not set
+# CONFIG_CRYPTO_RMD320 is not set
+CONFIG_CRYPTO_RNG2=y
+CONFIG_CRYPTO_RSA=y
+# CONFIG_CRYPTO_SALSA20 is not set
+# CONFIG_CRYPTO_SEQIV is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_SHA1 is not set
+CONFIG_CRYPTO_SHA256=m
+# CONFIG_CRYPTO_SHA3 is not set
+# CONFIG_CRYPTO_SHA512 is not set
+CONFIG_CRYPTO_SKCIPHER=m
+CONFIG_CRYPTO_SKCIPHER2=y
+# CONFIG_CRYPTO_SM2 is not set
+# CONFIG_CRYPTO_SM3 is not set
+# CONFIG_CRYPTO_SM4 is not set
+# CONFIG_CRYPTO_STREEBOG is not set
+# CONFIG_CRYPTO_TEST is not set
+# CONFIG_CRYPTO_TGR192 is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+# CONFIG_CRYPTO_USER is not set
+# CONFIG_CRYPTO_USER_API_AEAD is not set
+# CONFIG_CRYPTO_USER_API_HASH is not set
+# CONFIG_CRYPTO_USER_API_RNG is not set
+# CONFIG_CRYPTO_USER_API_SKCIPHER is not set
+# CONFIG_CRYPTO_VMAC is not set
+# CONFIG_CRYPTO_WP512 is not set
+# CONFIG_CRYPTO_XCBC is not set
+# CONFIG_CRYPTO_XTS is not set
+# CONFIG_CRYPTO_XXHASH is not set
+CONFIG_CRYPTO_ZSTD=y
+# CONFIG_CYW_BCMDHD is not set
+CONFIG_DEBUG_FS_ALLOW_ALL=y
+# CONFIG_DEBUG_FS_ALLOW_NONE is not set
+# CONFIG_DEBUG_FS_DISALLOW_MOUNT is not set
+# CONFIG_DLM is not set
+CONFIG_DNS_RESOLVER=y
+# CONFIG_DRM_ANALOGIX_ANX6345 is not set
+# CONFIG_DRM_ANALOGIX_ANX78XX is not set
+# CONFIG_DRM_ARCPGU is not set
+# CONFIG_DRM_ARMADA is not set
+CONFIG_DRM_BRIDGE=y
+# CONFIG_DRM_CDNS_DSI is not set
+# CONFIG_DRM_CDNS_MHDP8546 is not set
+# CONFIG_DRM_CHRONTEL_CH7033 is not set
+# CONFIG_DRM_DEBUG_DP_MST_TOPOLOGY_REFS is not set
+# CONFIG_DRM_DEBUG_MM is not set
+# CONFIG_DRM_DEBUG_SELFTEST is not set
+# CONFIG_DRM_DISPLAY_CONNECTOR is not set
+# CONFIG_DRM_DP is not set
+# CONFIG_DRM_DP_AUX_CHARDEV is not set
+# CONFIG_DRM_DP_CEC is not set
+CONFIG_DRM_EDID=y
+# CONFIG_DRM_ETNAVIV is not set
+# CONFIG_DRM_EXYNOS is not set
+CONFIG_DRM_FBDEV_EMULATION=y
+# CONFIG_DRM_FBDEV_LEAK_PHYS_SMEM is not set
+CONFIG_DRM_FBDEV_OVERALLOC=100
+# CONFIG_DRM_FSL_DCU is not set
+CONFIG_DRM_GEM_CMA_HELPER=y
+# CONFIG_DRM_GM12U320 is not set
+# CONFIG_DRM_HDLCD is not set
+# CONFIG_DRM_I2C_ADV7511 is not set
+# CONFIG_DRM_I2C_CH7006 is not set
+# CONFIG_DRM_I2C_NXP_TDA9950 is not set
+# CONFIG_DRM_I2C_NXP_TDA998X is not set
+# CONFIG_DRM_I2C_SIL164 is not set
+# CONFIG_DRM_IGNORE_IOTCL_PERMIT is not set
+# CONFIG_DRM_ITE_IT6161 is not set
+CONFIG_DRM_KMS_FB_HELPER=y
+CONFIG_DRM_KMS_HELPER=y
+# CONFIG_DRM_KOMEDA is not set
+# CONFIG_DRM_LEGACY is not set
+# CONFIG_DRM_LIMA is not set
+# CONFIG_DRM_LOAD_EDID_FIRMWARE is not set
+# CONFIG_DRM_LONTIUM_LT9611 is not set
+# CONFIG_DRM_LVDS_CODEC is not set
+# CONFIG_DRM_MALI_DISPLAY is not set
+# CONFIG_DRM_MAXIM_MAX96745 is not set
+# CONFIG_DRM_MAXIM_MAX96752F is not set
+# CONFIG_DRM_MAXIM_MAX96755F is not set
+# CONFIG_DRM_MAXIM_MAX96776 is not set
+# CONFIG_DRM_MCDE is not set
+# CONFIG_DRM_MEGACHIPS_STDPXXXX_GE_B850V3_FW is not set
+# CONFIG_DRM_MXSFB is not set
+# CONFIG_DRM_NWL_MIPI_DSI is not set
+# CONFIG_DRM_NXP_PTN3460 is not set
+# CONFIG_DRM_OMAP is not set
+CONFIG_DRM_PANEL=y
+# CONFIG_DRM_PANEL_ARM_VERSATILE is not set
+CONFIG_DRM_PANEL_BRIDGE=y
+# CONFIG_DRM_PANEL_ILITEK_IL9322 is not set
+# CONFIG_DRM_PANEL_LG_LB035Q02 is not set
+# CONFIG_DRM_PANEL_LG_LG4573 is not set
+# CONFIG_DRM_PANEL_LVDS is not set
+# CONFIG_DRM_PANEL_MAXIM_DESERIALIZER is not set
+# CONFIG_DRM_PANEL_NEC_NL8048HL11 is not set
+# CONFIG_DRM_PANEL_NOVATEK_NT39016 is not set
+# CONFIG_DRM_PANEL_OLIMEX_LCD_OLINUXINO is not set
+CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y
+# CONFIG_DRM_PANEL_SAMSUNG_LD9040 is not set
+# CONFIG_DRM_PANEL_SAMSUNG_S6E63M0 is not set
+# CONFIG_DRM_PANEL_SAMSUNG_S6E88A0_AMS452EF01 is not set
+# CONFIG_DRM_PANEL_SAMSUNG_S6E8AA0 is not set
+# CONFIG_DRM_PANEL_SEIKO_43WVF1G is not set
+# CONFIG_DRM_PANEL_SHARP_LS037V7DW01 is not set
+CONFIG_DRM_PANEL_SIMPLE=y
+# CONFIG_DRM_PANEL_SITRONIX_ST7789V is not set
+# CONFIG_DRM_PANEL_SONY_ACX565AKM is not set
+# CONFIG_DRM_PANEL_TPO_TD028TTEC1 is not set
+# CONFIG_DRM_PANEL_TPO_TD043MTEA1 is not set
+# CONFIG_DRM_PANEL_TPO_TPG110 is not set
+# CONFIG_DRM_PANFROST is not set
+# CONFIG_DRM_PARADE_PS8622 is not set
+# CONFIG_DRM_PARADE_PS8640 is not set
+# CONFIG_DRM_PL111 is not set
+# CONFIG_DRM_RCAR_DW_HDMI is not set
+# CONFIG_DRM_RCAR_LVDS is not set
+# CONFIG_DRM_RK1000_TVE is not set
+CONFIG_DRM_ROCKCHIP=y
+# CONFIG_DRM_ROCKCHIP_VVOP is not set
+# CONFIG_DRM_ROHM_BU18XL82 is not set
+CONFIG_DRM_SII902X=y
+# CONFIG_DRM_SII9234 is not set
+# CONFIG_DRM_SIL_SII8620 is not set
+# CONFIG_DRM_SIMPLE_BRIDGE is not set
+# CONFIG_DRM_STI is not set
+# CONFIG_DRM_STM is not set
+# CONFIG_DRM_THINE_THC63LVD1024 is not set
+# CONFIG_DRM_TIDSS is not set
+# CONFIG_DRM_TILCDC is not set
+# CONFIG_DRM_TI_SN65DSI86 is not set
+# CONFIG_DRM_TI_TFP410 is not set
+# CONFIG_DRM_TI_TPD12S015 is not set
+# CONFIG_DRM_TOSHIBA_TC358762 is not set
+# CONFIG_DRM_TOSHIBA_TC358764 is not set
+# CONFIG_DRM_TOSHIBA_TC358767 is not set
+# CONFIG_DRM_TOSHIBA_TC358768 is not set
+# CONFIG_DRM_TOSHIBA_TC358775 is not set
+# CONFIG_DRM_TVE200 is not set
+# CONFIG_DRM_UDL is not set
+# CONFIG_DRM_VGEM is not set
+# CONFIG_DRM_VKMS is not set
+# CONFIG_ECRYPT_FS is not set
+# CONFIG_EEPROM_93XX46 is not set
+# CONFIG_EEPROM_AT25 is not set
+# CONFIG_ENCRYPTED_KEYS is not set
+# CONFIG_EXT4_DEBUG is not set
+# CONFIG_EXT4_FS_POSIX_ACL is not set
+# CONFIG_EXT4_FS_SECURITY is not set
+CONFIG_EXT4_USE_FOR_EXT2=y
+# CONFIG_EXTCON_ADC_JACK is not set
+# CONFIG_EXTCON_FSA9480 is not set
+# CONFIG_EXTCON_GPIO is not set
+# CONFIG_EXTCON_MAX3355 is not set
+# CONFIG_EXTCON_PTN5150 is not set
+# CONFIG_EXTCON_RT8973A is not set
+# CONFIG_EXTCON_SM5502 is not set
+# CONFIG_EXTCON_USB_GPIO is not set
+# CONFIG_EZX_PCAP is not set
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+# CONFIG_FAT_DEFAULT_UTF8 is not set
+CONFIG_FAT_FS=y
+# CONFIG_FB_ARMCLCD is not set
+CONFIG_FB_CFB_COPYAREA=y
+CONFIG_FB_CFB_FILLRECT=y
+CONFIG_FB_CFB_IMAGEBLIT=y
+CONFIG_FB_CMDLINE=y
+CONFIG_FB_DEFERRED_IO=y
+# CONFIG_FB_FOREIGN_ENDIAN is not set
+# CONFIG_FB_IBM_GXT4500 is not set
+# CONFIG_FB_METRONOME is not set
+# CONFIG_FB_MODE_HELPERS is not set
+CONFIG_FB_NOTIFY=y
+# CONFIG_FB_OPENCORES is not set
+# CONFIG_FB_S1D13XXX is not set
+# CONFIG_FB_SIMPLE is not set
+# CONFIG_FB_SMSCUFX is not set
+# CONFIG_FB_SSD1307 is not set
+CONFIG_FB_SYS_COPYAREA=y
+CONFIG_FB_SYS_FILLRECT=y
+CONFIG_FB_SYS_FOPS=y
+CONFIG_FB_SYS_IMAGEBLIT=y
+# CONFIG_FB_TFT is not set
+# CONFIG_FB_TILEBLITTING is not set
+# CONFIG_FB_UDL is not set
+# CONFIG_FB_VIRTUAL is not set
+# CONFIG_FIRMWARE_EDID is not set
+CONFIG_FS_IOMAP=y
+CONFIG_FS_MBCACHE=y
+CONFIG_FS_POSIX_ACL=y
+# CONFIG_FXOS8700_SPI is not set
+# CONFIG_GCOV_KERNEL is not set
+# CONFIG_GENERIC_IRQ_DEBUGFS is not set
+# CONFIG_GPIO_74X164 is not set
+# CONFIG_GPIO_MAX3191X is not set
+# CONFIG_GPIO_MAX7301 is not set
+# CONFIG_GPIO_MC33880 is not set
+# CONFIG_GPIO_PISOSR is not set
+# CONFIG_GPIO_XRA1403 is not set
+CONFIG_GRACE_PERIOD=y
+CONFIG_HDMI=y
+# CONFIG_HI8435 is not set
+# CONFIG_HID is not set
+# CONFIG_HID_PID is not set
+# CONFIG_HISI_HIKEY_USB is not set
+CONFIG_I2C_ALGOBIT=y
+# CONFIG_I2C_ARB_GPIO_CHALLENGE is not set
+# CONFIG_I2C_DEMUX_PINCTRL is not set
+# CONFIG_I2C_DIOLAN_U2C is not set
+# CONFIG_I2C_GPIO_FAULT_INJECTOR is not set
+# CONFIG_I2C_HID is not set
+# CONFIG_I2C_MUX_GPIO is not set
+# CONFIG_I2C_MUX_GPMUX is not set
+# CONFIG_I2C_MUX_LTC4306 is not set
+# CONFIG_I2C_MUX_MLXCPLD is not set
+# CONFIG_I2C_MUX_PCA9541 is not set
+# CONFIG_I2C_MUX_PCA954x is not set
+# CONFIG_I2C_MUX_PINCTRL is not set
+# CONFIG_I2C_MUX_REG is not set
+# CONFIG_I2C_ROBOTFUZZ_OSIF is not set
+# CONFIG_I2C_TINY_USB is not set
+# CONFIG_IIO_SSP_SENSORHUB is not set
+# CONFIG_INET6_AH is not set
+# CONFIG_INET6_ESP is not set
+# CONFIG_INET6_IPCOMP is not set
+# CONFIG_INFINEON_DHD is not set
+# CONFIG_INPUT_EVBUG is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_JOYSTICK is not set
+CONFIG_INPUT_KEYBOARD=y
+# CONFIG_INPUT_MATRIXKMAP is not set
+# CONFIG_INPUT_MISC is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_POLLDEV is not set
+# CONFIG_INPUT_SPARSEKMAP is not set
+# CONFIG_INPUT_TABLET is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INV_ICM42600_SPI is not set
+# CONFIG_INV_MPU6050_SPI is not set
+# CONFIG_IPV6_MIP6 is not set
+# CONFIG_IPV6_MROUTE is not set
+# CONFIG_IPV6_MULTIPLE_TABLES is not set
+# CONFIG_IPV6_OPTIMISTIC_DAD is not set
+# CONFIG_IPV6_ROUTER_PREF is not set
+# CONFIG_IPV6_RPL_LWTUNNEL is not set
+# CONFIG_IPV6_SEG6_HMAC is not set
+# CONFIG_IPV6_SEG6_LWTUNNEL is not set
+# CONFIG_IPV6_SIT is not set
+# CONFIG_IPV6_TUNNEL is not set
+# CONFIG_IPV6_VTI is not set
+CONFIG_JBD2=y
+# CONFIG_JBD2_DEBUG is not set
+# CONFIG_JFFS2_CMODE_FAVOURLZO is not set
+# CONFIG_JFFS2_CMODE_NONE is not set
+CONFIG_JFFS2_CMODE_PRIORITY=y
+# CONFIG_JFFS2_CMODE_SIZE is not set
+CONFIG_JFFS2_COMPRESSION_OPTIONS=y
+CONFIG_JFFS2_FS_DEBUG=0
+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
+CONFIG_JFFS2_FS_WRITEBUFFER=y
+# CONFIG_JFFS2_FS_XATTR is not set
+# CONFIG_JFFS2_LZO is not set
+# CONFIG_JFFS2_RTIME is not set
+# CONFIG_JFFS2_RUBIN is not set
+# CONFIG_JFFS2_SUMMARY is not set
+CONFIG_JFFS2_ZLIB=y
+CONFIG_KEYBOARD_ADC=y
+# CONFIG_KEYBOARD_ADP5588 is not set
+# CONFIG_KEYBOARD_ADP5589 is not set
+# CONFIG_KEYBOARD_ATKBD is not set
+# CONFIG_KEYBOARD_BCM is not set
+# CONFIG_KEYBOARD_CAP11XX is not set
+# CONFIG_KEYBOARD_DLINK_DIR685 is not set
+# CONFIG_KEYBOARD_GPIO is not set
+# CONFIG_KEYBOARD_GPIO_POLLED is not set
+# CONFIG_KEYBOARD_LKKBD is not set
+# CONFIG_KEYBOARD_LM8333 is not set
+# CONFIG_KEYBOARD_MATRIX is not set
+# CONFIG_KEYBOARD_MAX7359 is not set
+# CONFIG_KEYBOARD_MCS is not set
+# CONFIG_KEYBOARD_MPR121 is not set
+# CONFIG_KEYBOARD_NEWTON is not set
+# CONFIG_KEYBOARD_OMAP4 is not set
+# CONFIG_KEYBOARD_OPENCORES is not set
+# CONFIG_KEYBOARD_QT1050 is not set
+# CONFIG_KEYBOARD_QT1070 is not set
+# CONFIG_KEYBOARD_QT2160 is not set
+# CONFIG_KEYBOARD_SAMSUNG is not set
+# CONFIG_KEYBOARD_STOWAWAY is not set
+# CONFIG_KEYBOARD_SUNKBD is not set
+# CONFIG_KEYBOARD_TCA6416 is not set
+# CONFIG_KEYBOARD_TCA8418 is not set
+# CONFIG_KEYBOARD_XTKBD is not set
+# CONFIG_KEYS_REQUEST_CACHE is not set
+# CONFIG_KEY_DH_OPERATIONS is not set
+# CONFIG_KS7010 is not set
+# CONFIG_LATTICE_ECP3_CONFIG is not set
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+# CONFIG_LOCK_EVENT_COUNTS is not set
+# CONFIG_LOGO is not set
+# CONFIG_LTC1660 is not set
+# CONFIG_LTC2496 is not set
+# CONFIG_LTC2632 is not set
+# CONFIG_LTC2983 is not set
+# CONFIG_LTE_GDM724X is not set
+CONFIG_LZO_COMPRESS=y
+CONFIG_LZO_DECOMPRESS=y
+CONFIG_MAC80211=m
+# CONFIG_MAC80211_DEBUGFS is not set
+# CONFIG_MAC80211_DEBUG_MENU is not set
+CONFIG_MAC80211_HAS_RC=y
+# CONFIG_MAC80211_HWSIM is not set
+# CONFIG_MAC80211_MESH is not set
+# CONFIG_MAC80211_MESSAGE_TRACING is not set
+CONFIG_MAC80211_RC_DEFAULT="minstrel_ht"
+CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y
+CONFIG_MAC80211_RC_MINSTREL=y
+CONFIG_MAC80211_STA_HASH_MAX_SIZE=0
+# CONFIG_MANAGER_SBS is not set
+CONFIG_MANDATORY_FILE_LOCKING=y
+# CONFIG_MAX1027 is not set
+# CONFIG_MAX11100 is not set
+# CONFIG_MAX1118 is not set
+# CONFIG_MAX1241 is not set
+# CONFIG_MAX31856 is not set
+# CONFIG_MAX5481 is not set
+# CONFIG_MAX5487 is not set
+# CONFIG_MAXIM_THERMOCOUPLE is not set
+# CONFIG_MCP320X is not set
+# CONFIG_MCP3911 is not set
+# CONFIG_MCP41010 is not set
+# CONFIG_MCP4131 is not set
+# CONFIG_MCP4922 is not set
+# CONFIG_MDIO_MVUSB is not set
+# CONFIG_MEDIA_USB_SUPPORT is not set
+# CONFIG_MFD_ARIZONA_SPI is not set
+# CONFIG_MFD_CPCAP is not set
+# CONFIG_MFD_DA9052_SPI is not set
+# CONFIG_MFD_DLN2 is not set
+# CONFIG_MFD_INTEL_M10_BMC is not set
+# CONFIG_MFD_MC13XXX_SPI is not set
+# CONFIG_MFD_RK806_SPI is not set
+# CONFIG_MFD_TPS65912_SPI is not set
+# CONFIG_MFD_VIPERBOARD is not set
+# CONFIG_MFD_WM831X_SPI is not set
+# CONFIG_MICREL_KS8995MA is not set
+# CONFIG_MINIX_SUBPARTITION is not set
+# CONFIG_MISC_RTSX_USB is not set
+# CONFIG_MMA7455_SPI is not set
+# CONFIG_MMC_ARMMMCI is not set
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_BLOCK_MINORS=32
+# CONFIG_MMC_CQHCI is not set
+# CONFIG_MMC_DEBUG is not set
+CONFIG_MMC_DW=y
+# CONFIG_MMC_DW_BLUEFIELD is not set
+# CONFIG_MMC_DW_EXYNOS is not set
+# CONFIG_MMC_DW_HI3798CV200 is not set
+# CONFIG_MMC_DW_K3 is not set
+CONFIG_MMC_DW_PLTFM=y
+CONFIG_MMC_DW_ROCKCHIP=y
+# CONFIG_MMC_HSQ is not set
+# CONFIG_MMC_MTK is not set
+CONFIG_MMC_QUEUE_DEPTH=1
+# CONFIG_MMC_SDHCI is not set
+# CONFIG_MMC_SPI is not set
+# CONFIG_MMC_TEST is not set
+# CONFIG_MMC_USDHI6ROL0 is not set
+# CONFIG_MMC_USHC is not set
+# CONFIG_MMC_VUB300 is not set
+# CONFIG_MOST is not set
+# CONFIG_MOXTET is not set
+CONFIG_MPILIB=y
+# CONFIG_MPL115_SPI is not set
+CONFIG_MTD_BLKDEVS=y
+# CONFIG_MTD_DATAFLASH is not set
+# CONFIG_MTD_MCHP23K256 is not set
+CONFIG_MTD_NAND_BBT_USING_FLASH=y
+CONFIG_MTD_NAND_CORE=y
+CONFIG_MTD_SPI_NAND=y
+CONFIG_MTD_SPI_NOR=y
+# CONFIG_MTD_SPI_NOR_USE_4K_SECTORS is not set
+# CONFIG_MTD_SST25L is not set
+CONFIG_MTD_UBI_BEB_LIMIT=20
+CONFIG_MTD_UBI_BLOCK=y
+# CONFIG_MTD_UBI_FASTMAP is not set
+# CONFIG_MTD_UBI_GLUEBI is not set
+CONFIG_MTD_UBI_WL_THRESHOLD=4096
+# CONFIG_NETDEVSIM is not set
+# CONFIG_NFSD is not set
+CONFIG_NFS_ACL_SUPPORT=y
+CONFIG_NFS_COMMON=y
+CONFIG_NFS_DISABLE_UDP_SUPPORT=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_USE_KERNEL_DNS=y
+# CONFIG_NFS_USE_LEGACY_DNS is not set
+CONFIG_NFS_V2=y
+CONFIG_NFS_V3=y
+CONFIG_NFS_V3_ACL=y
+CONFIG_NFS_V4=y
+# CONFIG_NFS_V4_1 is not set
+# CONFIG_NL80211_TESTMODE is not set
+# CONFIG_NOP_USB_XCEIV is not set
+# CONFIG_NVME_TARGET is not set
+# CONFIG_OCFS2_FS is not set
+CONFIG_OID_REGISTRY=y
+# CONFIG_PERSISTENT_KEYRINGS is not set
+# CONFIG_PHY_CPCAP_USB is not set
+# CONFIG_PHY_MAPPHONE_MDM6600 is not set
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
+# CONFIG_PHY_ROCKCHIP_NANENG_USB2 is not set
+# CONFIG_PI433 is not set
+CONFIG_PKCS7_MESSAGE_PARSER=y
+# CONFIG_PKCS7_TEST_KEY is not set
+# CONFIG_PKCS8_PRIVATE_KEY_PARSER is not set
+# CONFIG_PRISM2_USB is not set
+# CONFIG_PWRSEQ_EMMC is not set
+CONFIG_PWRSEQ_SIMPLE=y
+# CONFIG_R8188EU is not set
+# CONFIG_R8712U is not set
+# CONFIG_RC_CORE is not set
+CONFIG_REGMAP_SPI=y
+# CONFIG_REGULATOR_RASPBERRYPI_TOUCHSCREEN_ATTINY is not set
+# CONFIG_REGULATOR_TPS6524X is not set
+# CONFIG_RMI4_CORE is not set
+# CONFIG_ROCKCHIP_ANALOGIX_DP is not set
+# CONFIG_ROCKCHIP_CDN_DP is not set
+# CONFIG_ROCKCHIP_DRM_CUBIC_LUT is not set
+# CONFIG_ROCKCHIP_DRM_DEBUG is not set
+# CONFIG_ROCKCHIP_DRM_DIRECT_SHOW is not set
+# CONFIG_ROCKCHIP_DW_DP is not set
+# CONFIG_ROCKCHIP_DW_HDCP2 is not set
+# CONFIG_ROCKCHIP_DW_HDMI is not set
+# CONFIG_ROCKCHIP_DW_MIPI_DSI is not set
+# CONFIG_ROCKCHIP_INNO_HDMI is not set
+# CONFIG_ROCKCHIP_LVDS is not set
+# CONFIG_ROCKCHIP_MMC_VENDOR_STORAGE is not set
+CONFIG_ROCKCHIP_MTD_VENDOR_STORAGE=y
+# CONFIG_ROCKCHIP_REMOTECTL is not set
+CONFIG_ROCKCHIP_RGA_DEBUGGER=y
+# CONFIG_ROCKCHIP_RGA_DEBUG_FS is not set
+CONFIG_ROCKCHIP_RGB=y
+# CONFIG_ROCKCHIP_RK3066_HDMI is not set
+# CONFIG_ROCKCHIP_RKNPU_DEBUG_FS is not set
+# CONFIG_ROCKCHIP_RKNPU_DRM_GEM is not set
+CONFIG_ROCKCHIP_RVE_DEBUGGER=y
+# CONFIG_ROCKCHIP_RVE_DEBUG_FS is not set
+# CONFIG_ROCKCHIP_VCONN is not set
+CONFIG_ROCKCHIP_VOP=y
+# CONFIG_ROCKCHIP_VOP2 is not set
+# CONFIG_RTC_DRV_DS1302 is not set
+# CONFIG_RTC_DRV_DS1305 is not set
+# CONFIG_RTC_DRV_DS1343 is not set
+# CONFIG_RTC_DRV_DS1347 is not set
+# CONFIG_RTC_DRV_DS1390 is not set
+# CONFIG_RTC_DRV_M41T93 is not set
+# CONFIG_RTC_DRV_M41T94 is not set
+# CONFIG_RTC_DRV_MAX6902 is not set
+# CONFIG_RTC_DRV_MAX6916 is not set
+# CONFIG_RTC_DRV_MCP795 is not set
+# CONFIG_RTC_DRV_PCF2123 is not set
+# CONFIG_RTC_DRV_R9701 is not set
+# CONFIG_RTC_DRV_RS5C348 is not set
+# CONFIG_RTC_DRV_RX4581 is not set
+# CONFIG_RTC_DRV_RX6110 is not set
+# CONFIG_RTL8723BS is not set
+# CONFIG_RTLLIB is not set
+# CONFIG_SCA3000 is not set
+# CONFIG_SDIO_UART is not set
+# CONFIG_SECONDARY_TRUSTED_KEYRING is not set
+# CONFIG_SENSORS_HMC5843_SPI is not set
+# CONFIG_SENSORS_LIS3_I2C is not set
+# CONFIG_SENSORS_LIS3_SPI is not set
+# CONFIG_SENSORS_RM3100_SPI is not set
+# CONFIG_SENSOR_DEVICE is not set
+# CONFIG_SERIAL_IFX6X60 is not set
+# CONFIG_SERIAL_MAX3100 is not set
+# CONFIG_SERIAL_MAX310X is not set
+CONFIG_SGL_ALLOC=y
+# CONFIG_SIGNED_PE_FILE_VERIFICATION is not set
+# CONFIG_SND_BCD2000 is not set
+CONFIG_SND_JACK_INPUT_DEV=y
+# CONFIG_SND_SOC_ADAU1761_SPI is not set
+# CONFIG_SND_SOC_AK4104 is not set
+# CONFIG_SND_SOC_CS4271_SPI is not set
+# CONFIG_SND_SOC_CS42L52 is not set
+# CONFIG_SND_SOC_CS42L56 is not set
+# CONFIG_SND_SOC_ES8328_SPI is not set
+# CONFIG_SND_SOC_PCM179X_SPI is not set
+# CONFIG_SND_SOC_PCM186X_SPI is not set
+# CONFIG_SND_SOC_PCM3060_SPI is not set
+# CONFIG_SND_SOC_PCM3168A_SPI is not set
+# CONFIG_SND_SOC_PCM512x_SPI is not set
+# CONFIG_SND_SOC_RK3399_GRU_SOUND is not set
+# CONFIG_SND_SOC_SSM2602_SPI is not set
+# CONFIG_SND_SOC_TLV320AIC23_SPI is not set
+# CONFIG_SND_SOC_TLV320AIC32X4_SPI is not set
+# CONFIG_SND_SOC_WM8770 is not set
+# CONFIG_SND_SOC_WM8804_SPI is not set
+# CONFIG_SND_SOC_WM8962 is not set
+# CONFIG_SND_SOC_ZL38060 is not set
+# CONFIG_SND_SPI is not set
+CONFIG_SND_USB=y
+# CONFIG_SND_USB_6FIRE is not set
+# CONFIG_SND_USB_AUDIO is not set
+# CONFIG_SND_USB_CAIAQ is not set
+# CONFIG_SND_USB_HIFACE is not set
+# CONFIG_SND_USB_POD is not set
+# CONFIG_SND_USB_PODHD is not set
+# CONFIG_SND_USB_TONEPORT is not set
+# CONFIG_SND_USB_UA101 is not set
+# CONFIG_SND_USB_VARIAX is not set
+# CONFIG_SOLARIS_X86_PARTITION is not set
+# CONFIG_SPI_ALTERA is not set
+# CONFIG_SPI_AMD is not set
+# CONFIG_SPI_AXI_SPI_ENGINE is not set
+# CONFIG_SPI_BITBANG is not set
+# CONFIG_SPI_CADENCE is not set
+# CONFIG_SPI_CADENCE_QUADSPI is not set
+# CONFIG_SPI_DEBUG is not set
+# CONFIG_SPI_DESIGNWARE is not set
+# CONFIG_SPI_FSL_SPI is not set
+# CONFIG_SPI_GPIO is not set
+# CONFIG_SPI_LOOPBACK_TEST is not set
+CONFIG_SPI_MASTER=y
+CONFIG_SPI_MEM=y
+# CONFIG_SPI_MUX is not set
+# CONFIG_SPI_MXIC is not set
+# CONFIG_SPI_NXP_FLEXSPI is not set
+# CONFIG_SPI_OC_TINY is not set
+# CONFIG_SPI_PL022 is not set
+CONFIG_SPI_ROCKCHIP=y
+# CONFIG_SPI_ROCKCHIP_MISCDEV is not set
+CONFIG_SPI_ROCKCHIP_SFC=y
+# CONFIG_SPI_SC18IS602 is not set
+# CONFIG_SPI_SIFIVE is not set
+# CONFIG_SPI_SLAVE is not set
+CONFIG_SPI_SPIDEV=y
+# CONFIG_SPI_TLE62X0 is not set
+# CONFIG_SPI_XCOMM is not set
+# CONFIG_SPI_XILINX is not set
+# CONFIG_SPI_ZYNQMP_GQSPI is not set
+CONFIG_SUNRPC=y
+# CONFIG_SUNRPC_DEBUG is not set
+CONFIG_SUNRPC_GSS=y
+# CONFIG_SYSTEM_BLACKLIST_KEYRING is not set
+CONFIG_SYSTEM_DATA_VERIFICATION=y
+# CONFIG_SYSTEM_EXTRA_CERTIFICATE is not set
+CONFIG_SYSTEM_TRUSTED_KEYRING=y
+CONFIG_SYSTEM_TRUSTED_KEYS=""
+# CONFIG_TINYDRM_HX8357D is not set
+# CONFIG_TINYDRM_ILI9225 is not set
+# CONFIG_TINYDRM_ILI9341 is not set
+# CONFIG_TINYDRM_ILI9486 is not set
+# CONFIG_TINYDRM_MI0283QT is not set
+# CONFIG_TINYDRM_REPAPER is not set
+# CONFIG_TINYDRM_ST7586 is not set
+# CONFIG_TINYDRM_ST7735R is not set
+# CONFIG_TI_ADC0832 is not set
+# CONFIG_TI_ADC084S021 is not set
+# CONFIG_TI_ADC108S102 is not set
+# CONFIG_TI_ADC12138 is not set
+# CONFIG_TI_ADC128S052 is not set
+# CONFIG_TI_ADC161S626 is not set
+# CONFIG_TI_ADS124S08 is not set
+# CONFIG_TI_ADS7950 is not set
+# CONFIG_TI_ADS8344 is not set
+# CONFIG_TI_ADS8688 is not set
+# CONFIG_TI_DAC082S085 is not set
+# CONFIG_TI_DAC7311 is not set
+# CONFIG_TI_DAC7612 is not set
+# CONFIG_TI_TLC4541 is not set
+# CONFIG_TYPEC is not set
+# CONFIG_UBIFS_ATIME_SUPPORT is not set
+CONFIG_UBIFS_FS=y
+CONFIG_UBIFS_FS_ADVANCED_COMPR=y
+# CONFIG_UBIFS_FS_AUTHENTICATION is not set
+CONFIG_UBIFS_FS_LZO=y
+CONFIG_UBIFS_FS_SECURITY=y
+CONFIG_UBIFS_FS_XATTR=y
+CONFIG_UBIFS_FS_ZLIB=y
+# CONFIG_UBIFS_FS_ZSTD is not set
+# CONFIG_UNIXWARE_DISKLABEL is not set
+CONFIG_USB=y
+# CONFIG_USBIP_CORE is not set
+# CONFIG_USBPCWATCHDOG is not set
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_ADUTUX is not set
+# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
+# CONFIG_USB_APPLEDISPLAY is not set
+CONFIG_USB_ARCH_HAS_HCD=y
+# CONFIG_USB_AUDIO is not set
+CONFIG_USB_AUTOSUSPEND_DELAY=2
+# CONFIG_USB_BDC_UDC is not set
+# CONFIG_USB_C67X00_HCD is not set
+# CONFIG_USB_CDC_COMPOSITE is not set
+# CONFIG_USB_CDNS3 is not set
+# CONFIG_USB_CHAOSKEY is not set
+# CONFIG_USB_CHIPIDEA is not set
+CONFIG_USB_COMMON=y
+CONFIG_USB_CONFIGFS=y
+# CONFIG_USB_CONFIGFS_ACM is not set
+# CONFIG_USB_CONFIGFS_ECM is not set
+# CONFIG_USB_CONFIGFS_ECM_SUBSET is not set
+# CONFIG_USB_CONFIGFS_EEM is not set
+# CONFIG_USB_CONFIGFS_F_AUDIO_SRC is not set
+CONFIG_USB_CONFIGFS_F_FS=y
+CONFIG_USB_CONFIGFS_F_HID=y
+# CONFIG_USB_CONFIGFS_F_LB_SS is not set
+# CONFIG_USB_CONFIGFS_F_MIDI is not set
+# CONFIG_USB_CONFIGFS_F_PRINTER is not set
+CONFIG_USB_CONFIGFS_F_UAC1=y
+# CONFIG_USB_CONFIGFS_F_UAC1_LEGACY is not set
+CONFIG_USB_CONFIGFS_F_UAC2=y
+CONFIG_USB_CONFIGFS_F_UVC=y
+CONFIG_USB_CONFIGFS_MASS_STORAGE=y
+# CONFIG_USB_CONFIGFS_NCM is not set
+# CONFIG_USB_CONFIGFS_OBEX is not set
+# CONFIG_USB_CONFIGFS_RNDIS is not set
+# CONFIG_USB_CONFIGFS_SERIAL is not set
+CONFIG_USB_CONFIGFS_UEVENT=y
+# CONFIG_USB_CONN_GPIO is not set
+# CONFIG_USB_CYPRESS_CY7C63 is not set
+# CONFIG_USB_CYTHERM is not set
+CONFIG_USB_DEFAULT_PERSIST=y
+# CONFIG_USB_DUMMY_HCD is not set
+# CONFIG_USB_DWC2 is not set
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_DUAL_ROLE=y
+# CONFIG_USB_DWC3_GADGET is not set
+# CONFIG_USB_DWC3_HOST is not set
+CONFIG_USB_DWC3_OF_SIMPLE=y
+# CONFIG_USB_DYNAMIC_MINORS is not set
+# CONFIG_USB_EHCI_HCD is not set
+# CONFIG_USB_EHSET_TEST_FIXTURE is not set
+# CONFIG_USB_EMI26 is not set
+# CONFIG_USB_EMI62 is not set
+# CONFIG_USB_ETH is not set
+# CONFIG_USB_EZUSB_FX2 is not set
+# CONFIG_USB_FEW_INIT_RETRIES is not set
+# CONFIG_USB_FOTG210_HCD is not set
+# CONFIG_USB_FOTG210_UDC is not set
+# CONFIG_USB_FTDI_ELAN is not set
+# CONFIG_USB_FUNCTIONFS is not set
+# CONFIG_USB_FUSB300 is not set
+CONFIG_USB_F_FS=y
+CONFIG_USB_F_HID=y
+CONFIG_USB_F_UAC1=y
+CONFIG_USB_F_UAC2=y
+CONFIG_USB_F_UVC=y
+CONFIG_USB_F_MASS_STORAGE=y
+CONFIG_USB_GADGET=y
+# CONFIG_USB_GADGETFS is not set
+# CONFIG_USB_GADGET_DEBUG is not set
+# CONFIG_USB_GADGET_DEBUG_FILES is not set
+# CONFIG_USB_GADGET_DEBUG_FS is not set
+CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS=2
+CONFIG_USB_GADGET_VBUS_DRAW=2
+# CONFIG_USB_GADGET_XILINX is not set
+# CONFIG_USB_GPIO_VBUS is not set
+# CONFIG_USB_GR_UDC is not set
+# CONFIG_USB_G_ACM_MS is not set
+# CONFIG_USB_G_DBGP is not set
+# CONFIG_USB_G_HID is not set
+# CONFIG_USB_G_MULTI is not set
+# CONFIG_USB_G_NCM is not set
+# CONFIG_USB_G_PRINTER is not set
+# CONFIG_USB_G_SERIAL is not set
+# CONFIG_USB_G_WEBCAM is not set
+# CONFIG_USB_HCD_TEST_MODE is not set
+# CONFIG_USB_HID is not set
+# CONFIG_USB_HSIC_USB3503 is not set
+# CONFIG_USB_HSIC_USB4604 is not set
+# CONFIG_USB_HUB_USB251XB is not set
+# CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_IOWARRIOR is not set
+# CONFIG_USB_ISIGHTFW is not set
+# CONFIG_USB_ISP116X_HCD is not set
+# CONFIG_USB_ISP1301 is not set
+# CONFIG_USB_ISP1760 is not set
+# CONFIG_USB_KBD is not set
+# CONFIG_USB_LCD is not set
+# CONFIG_USB_LD is not set
+# CONFIG_USB_LEGOTOWER is not set
+CONFIG_USB_LIBCOMPOSITE=y
+# CONFIG_USB_LINK_LAYER_TEST is not set
+# CONFIG_USB_M66592 is not set
+# CONFIG_USB_MASS_STORAGE is not set
+# CONFIG_USB_MAX3420_UDC is not set
+# CONFIG_USB_MAX3421_HCD is not set
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_MIDI_GADGET is not set
+# CONFIG_USB_MON is not set
+# CONFIG_USB_MOUSE is not set
+# CONFIG_USB_MUSB_HDRC is not set
+# CONFIG_USB_MV_U3D is not set
+# CONFIG_USB_MV_UDC is not set
+# CONFIG_USB_NET2272 is not set
+# CONFIG_USB_NET_DRIVERS is not set
+# CONFIG_USB_NET_RNDIS_WLAN is not set
+# CONFIG_USB_OHCI_HCD is not set
+# CONFIG_USB_OTG is not set
+# CONFIG_USB_OTG_DISABLE_EXTERNAL_HUB is not set
+# CONFIG_USB_OTG_PRODUCTLIST is not set
+# CONFIG_USB_OXU210HP_HCD is not set
+# CONFIG_USB_PRINTER is not set
+# CONFIG_USB_PXA27X is not set
+# CONFIG_USB_R8A66597 is not set
+# CONFIG_USB_R8A66597_HCD is not set
+# CONFIG_USB_RAW_GADGET is not set
+CONFIG_USB_ROLE_SWITCH=y
+# CONFIG_USB_SERIAL is not set
+# CONFIG_USB_SEVSEG is not set
+# CONFIG_USB_SL811_HCD is not set
+# CONFIG_USB_SNP_UDC_PLAT is not set
+# CONFIG_USB_TEST is not set
+# CONFIG_USB_TMC is not set
+# CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_ULPI is not set
+# CONFIG_USB_ULPI_BUS is not set
+CONFIG_USB_U_AUDIO=y
+# CONFIG_USB_WDM is not set
+# CONFIG_USB_XHCI_DBGCAP is not set
+CONFIG_USB_XHCI_HCD=y
+# CONFIG_USB_XHCI_PCI_RENESAS is not set
+CONFIG_USB_XHCI_PLATFORM=y
+# CONFIG_USB_YUREX is not set
+# CONFIG_USB_ZERO is not set
+CONFIG_VIDEOMODE_HELPERS=y
+# CONFIG_VIDEO_GS1662 is not set
+# CONFIG_VIDEO_MAX9286 is not set
+# CONFIG_VIDEO_ROCKCHIP_PREISP is not set
+# CONFIG_VIDEO_S5C73M3 is not set
+# CONFIG_VIRT_WIFI is not set
+# CONFIG_VT6656 is not set
+CONFIG_WEXT_CORE=y
+CONFIG_WEXT_PRIV=y
+CONFIG_WEXT_PROC=y
+# CONFIG_WFX is not set
+CONFIG_WIFI_BUILD_MODULE=y
+# CONFIG_WIFI_GENERATE_RANDOM_MAC_ADDR is not set
+# CONFIG_WIFI_LOAD_DRIVER_WHEN_KERNEL_BOOTUP is not set
+CONFIG_WIRELESS_EXT=y
+# CONFIG_WIRELESS_WDS is not set
+# CONFIG_WLAN_VENDOR_ADMTEK is not set
+# CONFIG_WLAN_VENDOR_ATH is not set
+# CONFIG_WLAN_VENDOR_ATMEL is not set
+# CONFIG_WLAN_VENDOR_BROADCOM is not set
+# CONFIG_WLAN_VENDOR_CISCO is not set
+# CONFIG_WLAN_VENDOR_INTEL is not set
+# CONFIG_WLAN_VENDOR_INTERSIL is not set
+# CONFIG_WLAN_VENDOR_MARVELL is not set
+# CONFIG_WLAN_VENDOR_MEDIATEK is not set
+# CONFIG_WLAN_VENDOR_MICROCHIP is not set
+# CONFIG_WLAN_VENDOR_QUANTENNA is not set
+# CONFIG_WLAN_VENDOR_RALINK is not set
+# CONFIG_WLAN_VENDOR_REALTEK is not set
+# CONFIG_WLAN_VENDOR_RSI is not set
+# CONFIG_WLAN_VENDOR_ST is not set
+# CONFIG_WLAN_VENDOR_TI is not set
+# CONFIG_WLAN_VENDOR_ZYDAS is not set
+CONFIG_WL_ROCKCHIP=m
+CONFIG_X509_CERTIFICATE_PARSER=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZSTD_COMPRESS=y
+CONFIG_ZSTD_DECOMPRESS=y
diff --git a/arch/arm/configs/rv1106-evb.config b/arch/arm/configs/rv1106-evb.config
index 4d120e187565..10716e6f5117 100644
--- a/arch/arm/configs/rv1106-evb.config
+++ b/arch/arm/configs/rv1106-evb.config
@@ -302,9 +302,7 @@ CONFIG_DRM_KMS_HELPER=y
 # CONFIG_DRM_LVDS_CODEC is not set
 # CONFIG_DRM_MALI_DISPLAY is not set
 # CONFIG_DRM_MAXIM_MAX96745 is not set
-# CONFIG_DRM_MAXIM_MAX96752F is not set
 # CONFIG_DRM_MAXIM_MAX96755F is not set
-# CONFIG_DRM_MAXIM_MAX96776 is not set
 # CONFIG_DRM_MCDE is not set
 # CONFIG_DRM_MEGACHIPS_STDPXXXX_GE_B850V3_FW is not set
 # CONFIG_DRM_MXSFB is not set
@@ -610,6 +608,7 @@ CONFIG_MTD_NAND_BBT_USING_FLASH=y
 CONFIG_MTD_NAND_CORE=y
 CONFIG_MTD_SPI_NAND=y
 CONFIG_MTD_SPI_NOR=y
+CONFIG_MTD_SPI_NOR_MISC=y
 # CONFIG_MTD_SPI_NOR_USE_4K_SECTORS is not set
 # CONFIG_MTD_SST25L is not set
 CONFIG_MTD_UBI_BEB_LIMIT=20
diff --git a/arch/arm/configs/rv1106-ipc.config b/arch/arm/configs/rv1106-ipc.config
index 663eafdb5a8f..fbd21938a8b7 100644
--- a/arch/arm/configs/rv1106-ipc.config
+++ b/arch/arm/configs/rv1106-ipc.config
@@ -161,6 +161,7 @@ CONFIG_MTD_BLKDEVS=y
 # CONFIG_MTD_MCHP23K256 is not set
 # CONFIG_MTD_SPI_NAND is not set
 CONFIG_MTD_SPI_NOR=y
+CONFIG_MTD_SPI_NOR_MISC=y
 # CONFIG_MTD_SPI_NOR_USE_4K_SECTORS is not set
 # CONFIG_MTD_SST25L is not set
 # CONFIG_PI433 is not set
diff --git a/arch/arm/configs/rv1106-smart-door.config b/arch/arm/configs/rv1106-smart-door.config
index 054a0a8cb5de..a6e88490018c 100644
--- a/arch/arm/configs/rv1106-smart-door.config
+++ b/arch/arm/configs/rv1106-smart-door.config
@@ -14,11 +14,14 @@ CONFIG_EEPROM_AT24=y
 CONFIG_EXTCON=m
 CONFIG_JFFS2_FS=y
 CONFIG_KEYS=y
+CONFIG_MAILBOX=y
+CONFIG_MTD_BLKDEVS=m
+CONFIG_MTD_BLOCK=m
 CONFIG_NVMEM_SYSFS=y
 CONFIG_RFKILL=y
 CONFIG_RK803=y
 CONFIG_ROCKCHIP_HW_DECOMPRESS_USER=y
-CONFIG_ROCKCHIP_VENDOR_STORAGE=y
+CONFIG_ROCKCHIP_VENDOR_STORAGE=m
 CONFIG_SPI=y
 # CONFIG_SQUASHFS is not set
 CONFIG_USB_SUPPORT=y
@@ -85,6 +88,10 @@ CONFIG_WLAN=y
 # CONFIG_ADXRS290 is not set
 # CONFIG_ADXRS450 is not set
 # CONFIG_AFE4403 is not set
+# CONFIG_ALTERA_MBOX is not set
+# CONFIG_ARM_MHU is not set
+# CONFIG_ARM_SCMI_PROTOCOL is not set
+# CONFIG_ARM_SCPI_PROTOCOL is not set
 # CONFIG_AS3935 is not set
 CONFIG_ASN1=y
 CONFIG_ASSOCIATIVE_ARRAY=y
@@ -183,6 +190,7 @@ CONFIG_MAC80211_RC_DEFAULT="minstrel_ht"
 CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y
 CONFIG_MAC80211_RC_MINSTREL=y
 CONFIG_MAC80211_STA_HASH_MAX_SIZE=0
+# CONFIG_MAILBOX_TEST is not set
 # CONFIG_MAX1027 is not set
 # CONFIG_MAX11100 is not set
 # CONFIG_MAX1118 is not set
@@ -211,10 +219,11 @@ CONFIG_MAC80211_STA_HASH_MAX_SIZE=0
 # CONFIG_MOXTET is not set
 CONFIG_MPILIB=y
 # CONFIG_MPL115_SPI is not set
+# CONFIG_MTD_BLOCK_RO is not set
 # CONFIG_MTD_DATAFLASH is not set
 # CONFIG_MTD_MCHP23K256 is not set
 # CONFIG_MTD_SPI_NAND is not set
-CONFIG_MTD_SPI_NOR=y
+CONFIG_MTD_SPI_NOR=m
 # CONFIG_MTD_SPI_NOR_USE_4K_SECTORS is not set
 # CONFIG_MTD_SST25L is not set
 # CONFIG_NL80211_TESTMODE is not set
@@ -230,12 +239,17 @@ CONFIG_PHY_ROCKCHIP_INNO_USB2=m
 # CONFIG_PI433 is not set
 CONFIG_PKCS7_MESSAGE_PARSER=y
 # CONFIG_PKCS8_PRIVATE_KEY_PARSER is not set
+# CONFIG_PL320_MBOX is not set
+# CONFIG_PLATFORM_MHU is not set
 CONFIG_REGMAP_SPI=y
 # CONFIG_REGULATOR_TPS6524X is not set
 # CONFIG_RFKILL_GPIO is not set
 CONFIG_RFKILL_RK=y
+CONFIG_ROCKCHIP_MBOX=y
 # CONFIG_ROCKCHIP_MMC_VENDOR_STORAGE is not set
-CONFIG_ROCKCHIP_MTD_VENDOR_STORAGE=y
+CONFIG_ROCKCHIP_MTD_VENDOR_STORAGE=m
+CONFIG_ROCKCHIP_THUNDER_BOOT_SERVICE=y
+# CONFIG_RPMSG_QCOM_GLINK_RPM is not set
 # CONFIG_RTC_DRV_DS1302 is not set
 # CONFIG_RTC_DRV_DS1305 is not set
 # CONFIG_RTC_DRV_DS1343 is not set
diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile
index fc4ecac37e81..68fd62d6b572 100644
--- a/arch/arm64/boot/dts/rockchip/Makefile
+++ b/arch/arm64/boot/dts/rockchip/Makefile
@@ -115,6 +115,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-evb1-lp4-v10.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-evb1-lp4-v10-ipc-6x-linux.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-evb1-lp4-v10-linux.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-evb1-lp4-v10-linux-ipc.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-evb1-lp4-v10-lt6911uxe.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-evb2-lp4-v10.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-evb2-lp4-v10-edp.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-evb2-lp4-v10-edp2dp.dtb
@@ -132,6 +133,8 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-evb6-lp4-v10-linux.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-evb7-lp4-v10.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-evb7-lp4-v10-linux.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-evb7-lp4-v10-rk1608-ipc-8x-linux.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-h0-v10.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-h0-v10-linux.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-nvr-demo-v10.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-nvr-demo-v10-android.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-nvr-demo-v10-spi-nand.dtb
diff --git a/arch/arm64/boot/dts/rockchip/px30-mini-evb-ddr3-v11-avb.dts b/arch/arm64/boot/dts/rockchip/px30-mini-evb-ddr3-v11-avb.dts
index c47101d4e7f9..bcaea43fdc18 100644
--- a/arch/arm64/boot/dts/rockchip/px30-mini-evb-ddr3-v11-avb.dts
+++ b/arch/arm64/boot/dts/rockchip/px30-mini-evb-ddr3-v11-avb.dts
@@ -246,7 +246,7 @@
 			15 00 02 d2 32
 			15 00 02 d3 00
 			39 00 04 ff 98 81 00
-			05 00 01 11
+			05 78 01 11
 			05 01 01 29
 		];
 
diff --git a/arch/arm64/boot/dts/rockchip/px30.dtsi b/arch/arm64/boot/dts/rockchip/px30.dtsi
index ea9ab107fe3d..5a43a617a30f 100644
--- a/arch/arm64/boot/dts/rockchip/px30.dtsi
+++ b/arch/arm64/boot/dts/rockchip/px30.dtsi
@@ -41,6 +41,7 @@
 		serial5 = &uart5;
 		spi0 = &spi0;
 		spi1 = &spi1;
+		spi2 = &sfc;
 	};
 
 	cpus {
@@ -674,7 +675,8 @@
 		clocks = <&pmucru SCLK_UART0_PMU>, <&pmucru PCLK_UART0_PMU>;
 		clock-names = "baudclk", "apb_pclk";
 		dmas = <&dmac 0>, <&dmac 1>;
-		dma-names = "tx", "rx";
+		/*You can add it to enable dma*/
+		/*dma-names = "tx", "rx";*/
 		reg-shift = <2>;
 		reg-io-width = <4>;
 		pinctrl-names = "default";
@@ -877,7 +879,8 @@
 		clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 		clock-names = "baudclk", "apb_pclk";
 		dmas = <&dmac 2>, <&dmac 3>;
-		dma-names = "tx", "rx";
+		/*You can add it to enable dma*/
+		/*dma-names = "tx", "rx";*/
 		reg-shift = <2>;
 		reg-io-width = <4>;
 		pinctrl-names = "default";
@@ -892,7 +895,8 @@
 		clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 		clock-names = "baudclk", "apb_pclk";
 		dmas = <&dmac 4>, <&dmac 5>;
-		dma-names = "tx", "rx";
+		/*You can add it to enable dma*/
+		/*dma-names = "tx", "rx";*/
 		reg-shift = <2>;
 		reg-io-width = <4>;
 		pinctrl-names = "default";
@@ -907,7 +911,8 @@
 		clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 		clock-names = "baudclk", "apb_pclk";
 		dmas = <&dmac 6>, <&dmac 7>;
-		dma-names = "tx", "rx";
+		/*You can add it to enable dma*/
+		/*dma-names = "tx", "rx";*/
 		reg-shift = <2>;
 		reg-io-width = <4>;
 		pinctrl-names = "default";
@@ -922,7 +927,8 @@
 		clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
 		clock-names = "baudclk", "apb_pclk";
 		dmas = <&dmac 8>, <&dmac 9>;
-		dma-names = "tx", "rx";
+		/*You can add it to enable dma*/
+		/*dma-names = "tx", "rx";*/
 		reg-shift = <2>;
 		reg-io-width = <4>;
 		pinctrl-names = "default";
@@ -937,7 +943,8 @@
 		clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>;
 		clock-names = "baudclk", "apb_pclk";
 		dmas = <&dmac 10>, <&dmac 11>;
-		dma-names = "tx", "rx";
+		/*You can add it to enable dma*/
+		/*dma-names = "tx", "rx";*/
 		reg-shift = <2>;
 		reg-io-width = <4>;
 		pinctrl-names = "default";
@@ -1416,6 +1423,17 @@
 		status = "disabled";
 	};
 
+	sfc: spi@ff3a0000 {
+		compatible = "rockchip,sfc";
+		reg = <0x0 0xff3a0000 0x0 0x4000>;
+		interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
+		clock-names = "clk_sfc", "hclk_sfc";
+		assigned-clocks = <&cru SCLK_SFC>;
+		assigned-clock-rates = <100000000>;
+		status = "disabled";
+	};
+
 	nandc0: nandc@ff3b0000 {
 		compatible = "rockchip,rk-nandc";
 		reg = <0x0 0xff3b0000 0x0 0x4000>;
@@ -1580,6 +1598,7 @@
 		clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
 		clock-names = "aclk", "iface";
 		power-domains = <&power PX30_PD_VPU>;
+		rockchip,shootdown-entire;
 		#iommu-cells = <0>;
 		status = "disabled";
 	};
@@ -1630,6 +1649,7 @@
 		clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
 		clock-names = "aclk", "iface";
 		power-domains = <&power PX30_PD_VPU>;
+		rockchip,shootdown-entire;
 		#iommu-cells = <0>;
 		status = "disabled";
 	};
diff --git a/arch/arm64/boot/dts/rockchip/rk1808.dtsi b/arch/arm64/boot/dts/rockchip/rk1808.dtsi
index 16d8fabe20f2..67f93f0c9d01 100644
--- a/arch/arm64/boot/dts/rockchip/rk1808.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk1808.dtsi
@@ -379,6 +379,7 @@
 			snps,dis-del-phy-power-chg-quirk;
 			snps,tx-ipgap-linecheck-dis-quirk;
 			snps,xhci-trb-ent-quirk;
+			snps,parkmode-disable-ss-quirk;
 			status = "disabled";
 		};
 	};
diff --git a/arch/arm64/boot/dts/rockchip/rk3326-evb-lp3-v11-avb.dts b/arch/arm64/boot/dts/rockchip/rk3326-evb-lp3-v11-avb.dts
index 88dc225f4f01..4b1c4ea13fcf 100644
--- a/arch/arm64/boot/dts/rockchip/rk3326-evb-lp3-v11-avb.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3326-evb-lp3-v11-avb.dts
@@ -242,7 +242,7 @@
 			15 00 02 d2 32
 			15 00 02 d3 00
 			39 00 04 ff 98 81 00
-			05 00 01 11
+			05 78 01 11
 			05 01 01 29
 		];
 
diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
index 503dba319e73..bcbadbae2910 100644
--- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
@@ -1003,6 +1003,7 @@
 		snps,dis-u2-freeclk-exists-quirk;
 		snps,dis_u2_susphy_quirk;
 		snps,dis_u3_susphy_quirk;
+		snps,parkmode-disable-ss-quirk;
 		status = "disabled";
 	};
 
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-opp.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-opp.dtsi
index f9f2cc8abec7..645c2d479969 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399-opp.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399-opp.dtsi
@@ -11,7 +11,7 @@
 		opp-shared;
 
 		rockchip,temp-hysteresis = <5000>;
-		rockchip,low-temp = <0>;
+		rockchip,low-temp = <10000>;
 		rockchip,low-temp-min-volt = <900000>;
 
 		nvmem-cells = <&cpul_leakage>, <&specification_serial_number>,
@@ -104,7 +104,7 @@
 		opp-shared;
 
 		rockchip,temp-hysteresis = <5000>;
-		rockchip,low-temp = <0>;
+		rockchip,low-temp = <10000>;
 		rockchip,low-temp-min-volt = <900000>;
 
 		nvmem-cells = <&cpub_leakage>, <&specification_serial_number>,
@@ -224,7 +224,7 @@
 
 		rockchip,thermal-zone = "soc-thermal";
 		rockchip,temp-hysteresis = <5000>;
-		rockchip,low-temp = <0>;
+		rockchip,low-temp = <10000>;
 		rockchip,low-temp-min-volt = <900000>;
 
 		nvmem-cells = <&gpu_leakage>;
diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
index b97879e82a11..e0ce7a3e053f 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
@@ -455,6 +455,7 @@
 			snps,dis_u2_susphy_quirk;
 			snps,dis-del-phy-power-chg-quirk;
 			snps,dis-tx-ipgap-linecheck-quirk;
+			snps,parkmode-disable-ss-quirk;
 			power-domains = <&power RK3399_PD_USB3>;
 			status = "disabled";
 		};
@@ -491,6 +492,7 @@
 			snps,dis_u2_susphy_quirk;
 			snps,dis-del-phy-power-chg-quirk;
 			snps,dis-tx-ipgap-linecheck-quirk;
+			snps,parkmode-disable-ss-quirk;
 			power-domains = <&power RK3399_PD_USB3>;
 			status = "disabled";
 		};
diff --git a/arch/arm64/boot/dts/rockchip/rk3399pro-evb-lp4-v11-linux.dts b/arch/arm64/boot/dts/rockchip/rk3399pro-evb-lp4-v11-linux.dts
index f975f47b76d6..e0a75ed92439 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399pro-evb-lp4-v11-linux.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3399pro-evb-lp4-v11-linux.dts
@@ -8,6 +8,7 @@
 #include <dt-bindings/display/drm_mipi_dsi.h>
 #include <dt-bindings/sensor-dev.h>
 #include <dt-bindings/pwm/pwm.h>
+#include "dt-bindings/usb/pd.h"
 #include "rk3399pro.dtsi"
 #include "rk3399-linux.dtsi"
 #include "rk3399-opp.dtsi"
@@ -208,6 +209,16 @@
 		regulator-boot-on;
 	};
 
+	vbus_typec: vbus-typec-regulator {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio1 18 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vcc5v0_typec0_en>;
+		regulator-name = "vbus_typec";
+		vin-supply = <&vcc5v0_sys>;
+	};
+
 	vcc5v0_sys: vccsys {
 		compatible = "regulator-fixed";
 		regulator-name = "vcc5v0_sys";
@@ -243,7 +254,6 @@
 
 &cdn_dp {
 	status = "okay";
-	extcon = <&fusb0>;
 	phys = <&tcphy0_dp>;
 };
 
@@ -746,7 +756,6 @@
 	bq25700: bq25700@6b {
 		compatible = "ti,bq25703";
 		reg = <0x6b>;
-		extcon = <&fusb0>;
 		interrupt-parent = <&gpio1>;
 		interrupts = <RK_PA1 IRQ_TYPE_LEVEL_LOW>;
 		pinctrl-names = "default";
@@ -1072,8 +1081,16 @@
 };
 
 &tcphy0 {
-	extcon = <&fusb0>;
 	status = "okay";
+	orientation-switch;
+	port {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		tcphy0_orientation_switch: endpoint@0 {
+			reg = <0>;
+			remote-endpoint = <&usbc0_orien_sw>;
+		};
+	};
 };
 
 &tcphy1 {
@@ -1144,7 +1161,15 @@
 
 &usbdrd_dwc3_0 {
 	status = "okay";
-	extcon = <&fusb0>;
+	usb-role-switch;
+	port {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		dwc3_0_role_switch: endpoint@0 {
+			reg = <0>;
+			remote-endpoint = <&usbc0_role_sw>;
+		};
+	};
 };
 
 &usbdrd_dwc3_1 {
@@ -1178,13 +1203,6 @@
 			};
 	};
 
-	fusb30x {
-		fusb0_int: fusb0-int {
-			rockchip,pins =
-				<1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>;
-			};
-	};
-
 	headphone {
 		hp_det: hp-det {
 			rockchip,pins =
@@ -1275,6 +1293,16 @@
 		};
 	};
 
+	usb-typec {
+		usbc0_int: usbc0-int {
+			rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+
+	vcc5v0_typec0_en: vcc5v0-typec0-en {
+		rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
 	wireless-bluetooth {
 		bt_irq_gpio: bt-irq-gpio {
 			rockchip,pins =
diff --git a/arch/arm64/boot/dts/rockchip/rk3399pro-evb-v10-linux.dts b/arch/arm64/boot/dts/rockchip/rk3399pro-evb-v10-linux.dts
index 08ac2a477852..004ccbc3d8d6 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399pro-evb-v10-linux.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3399pro-evb-v10-linux.dts
@@ -8,6 +8,7 @@
 #include <dt-bindings/display/drm_mipi_dsi.h>
 #include <dt-bindings/sensor-dev.h>
 #include <dt-bindings/pwm/pwm.h>
+#include "dt-bindings/usb/pd.h"
 #include "rk3399pro.dtsi"
 #include "rk3399-linux.dtsi"
 #include "rk3399-opp.dtsi"
@@ -196,6 +197,16 @@
 		reset-gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_LOW>;
 	};
 
+	vbus_typec: vbus-typec-regulator {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio1 18 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vcc5v0_typec0_en>;
+		regulator-name = "vbus_typec";
+		vin-supply = <&vcc5v0_sys>;
+	};
+
 	vcc_phy: vcc-phy-regulator {
 		compatible = "regulator-fixed";
 		regulator-name = "vcc_phy";
@@ -238,7 +249,6 @@
 
 &cdn_dp {
 	status = "okay";
-	extcon = <&fusb0>;
 	phys = <&tcphy0_dp>;
 };
 
@@ -647,7 +657,6 @@
 	bq25700: bq25700@6b {
 		compatible = "ti,bq25703";
 		reg = <0x6b>;
-		extcon = <&fusb0>;
 		interrupt-parent = <&gpio1>;
 		interrupts = <RK_PA1 IRQ_TYPE_LEVEL_LOW>;
 		pinctrl-names = "default";
@@ -774,13 +783,52 @@
 	i2c-scl-falling-time-ns = <11>;
 	clock-frequency = <100000>;
 
-	fusb0: fusb30x@22 {
-		compatible = "fairchild,fusb302";
+	usbc0: fusb302@22 {
+		compatible = "fcs,fusb302";
 		reg = <0x22>;
+		interrupt-parent = <&gpio1>;
+		interrupts = <RK_PA2 IRQ_TYPE_LEVEL_LOW>;
 		pinctrl-names = "default";
-		pinctrl-0 = <&fusb0_int>;
-		int-n-gpios = <&gpio1 RK_PA2 GPIO_ACTIVE_HIGH>;
+		pinctrl-0 = <&usbc0_int>;
+		vbus-supply = <&vbus_typec>;
 		status = "okay";
+
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+				usbc0_role_sw: endpoint@0 {
+					remote-endpoint = <&dwc3_0_role_switch>;
+				};
+			};
+		};
+
+		usb_con: connector {
+			compatible = "usb-c-connector";
+			label = "USB-C";
+			data-role = "dual";
+			power-role = "dual";
+			try-power-role = "sink";
+			op-sink-microwatt = <1000000>;
+			sink-pdos =
+				<PDO_FIXED(5000, 2500, PDO_FIXED_USB_COMM)>;
+			source-pdos =
+				<PDO_FIXED(5000, 1500, PDO_FIXED_USB_COMM)>;
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+					usbc0_orien_sw: endpoint {
+						remote-endpoint = <&tcphy0_orientation_switch>;
+					};
+				};
+			};
+		};
 	};
 
 };
@@ -982,8 +1030,16 @@
 };
 
 &tcphy0 {
-	extcon = <&fusb0>;
 	status = "okay";
+	orientation-switch;
+	port {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		tcphy0_orientation_switch: endpoint@0 {
+			reg = <0>;
+			remote-endpoint = <&usbc0_orien_sw>;
+		};
+	};
 };
 
 &tcphy1 {
@@ -998,7 +1054,6 @@
 
 &u2phy0 {
 	status = "okay";
-	extcon = <&fusb0>;
 
 	u2phy0_otg: otg-port {
 		status = "okay";
@@ -1054,7 +1109,15 @@
 
 &usbdrd_dwc3_0 {
 	status = "okay";
-	extcon = <&fusb0>;
+	usb-role-switch;
+	port {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		dwc3_0_role_switch: endpoint@0 {
+			reg = <0>;
+			remote-endpoint = <&usbc0_role_sw>;
+		};
+	};
 };
 
 &usbdrd_dwc3_1 {
@@ -1088,13 +1151,6 @@
 			};
 	};
 
-	fusb30x {
-		fusb0_int: fusb0-int {
-			rockchip,pins =
-				<1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>;
-			};
-	};
-
 	headphone {
 		hp_det: hp-det {
 			rockchip,pins =
@@ -1146,6 +1202,16 @@
 		};
 	};
 
+	usb-typec {
+		usbc0_int: usbc0-int {
+			rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+
+		vcc5v0_typec0_en: vcc5v0-typec0-en {
+			rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
 	sdio-pwrseq {
 		wifi_enable_h: wifi-enable-h {
 			rockchip,pins =
diff --git a/arch/arm64/boot/dts/rockchip/rk3399pro-evb-v10.dts b/arch/arm64/boot/dts/rockchip/rk3399pro-evb-v10.dts
index 398f962114cf..8eb9ac1ae383 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399pro-evb-v10.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3399pro-evb-v10.dts
@@ -197,6 +197,16 @@
 		reset-gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_LOW>;
 	};
 
+	vbus_typec: vbus-typec-regulator {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio1 18 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vcc5v0_typec0_en>;
+		regulator-name = "vbus_typec";
+		vin-supply = <&vcc5v0_sys>;
+	};
+
 	vcc_phy: vcc-phy-regulator {
 		compatible = "regulator-fixed";
 		regulator-name = "vcc_phy";
@@ -239,7 +249,6 @@
 
 &cdn_dp {
 	status = "okay";
-	extcon = <&fusb0>;
 	phys = <&tcphy0_dp>;
 };
 
@@ -676,7 +685,6 @@
 	bq25700: bq25700@6b {
 		compatible = "ti,bq25703";
 		reg = <0x6b>;
-		extcon = <&fusb0>;
 		interrupt-parent = <&gpio1>;
 		interrupts = <RK_PA1 IRQ_TYPE_LEVEL_LOW>;
 		pinctrl-names = "default";
@@ -750,15 +758,53 @@
 	i2c-scl-falling-time-ns = <11>;
 	clock-frequency = <100000>;
 
-	fusb0: fusb30x@22 {
-		compatible = "fairchild,fusb302";
+	usbc0: fusb302@22 {
+		compatible = "fcs,fusb302";
 		reg = <0x22>;
+		interrupt-parent = <&gpio1>;
+		interrupts = <RK_PA2 IRQ_TYPE_LEVEL_LOW>;
 		pinctrl-names = "default";
-		pinctrl-0 = <&fusb0_int>;
-		int-n-gpios = <&gpio1 RK_PA2 GPIO_ACTIVE_HIGH>;
+		pinctrl-0 = <&usbc0_int>;
+		vbus-supply = <&vbus_typec>;
 		status = "okay";
-	};
 
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+				usbc0_role_sw: endpoint@0 {
+					remote-endpoint = <&dwc3_0_role_switch>;
+				};
+			};
+		};
+
+		usb_con: connector {
+			compatible = "usb-c-connector";
+			label = "USB-C";
+			data-role = "dual";
+			power-role = "dual";
+			try-power-role = "sink";
+			op-sink-microwatt = <1000000>;
+			sink-pdos =
+				<PDO_FIXED(5000, 2500, PDO_FIXED_USB_COMM)>;
+			source-pdos =
+				<PDO_FIXED(5000, 1500, PDO_FIXED_USB_COMM)>;
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+					usbc0_orien_sw: endpoint {
+						remote-endpoint = <&tcphy0_orientation_switch>;
+					};
+				};
+			};
+		};
+	};
 };
 
 &i2s1 {
@@ -856,8 +902,16 @@
 };
 
 &tcphy0 {
-	extcon = <&fusb0>;
 	status = "okay";
+	orientation-switch;
+	port {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		tcphy0_orientation_switch: endpoint@0 {
+			reg = <0>;
+			remote-endpoint = <&usbc0_orien_sw>;
+		};
+	};
 };
 
 &tcphy1 {
@@ -872,7 +926,6 @@
 
 &u2phy0 {
 	status = "okay";
-	extcon = <&fusb0>;
 
 	u2phy0_otg: otg-port {
 		status = "okay";
@@ -928,7 +981,15 @@
 
 &usbdrd_dwc3_0 {
 	status = "okay";
-	extcon = <&fusb0>;
+	usb-role-switch;
+	port {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		dwc3_0_role_switch: endpoint@0 {
+			reg = <0>;
+			remote-endpoint = <&usbc0_role_sw>;
+		};
+	};
 };
 
 &usbdrd_dwc3_1 {
@@ -956,13 +1017,6 @@
 			};
 	};
 
-	fusb30x {
-		fusb0_int: fusb0-int {
-			rockchip,pins =
-				<1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>;
-			};
-	};
-
 	headphone {
 		hp_det: hp-det {
 			rockchip,pins =
@@ -1048,6 +1102,16 @@
 		};
 	};
 
+	usb-typec {
+		usbc0_int: usbc0-int {
+			rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+
+		vcc5v0_typec0_en: vcc5v0-typec0-en {
+			rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
 	wireless-bluetooth {
 		uart0_gpios: uart0-gpios {
 			rockchip,pins =
diff --git a/arch/arm64/boot/dts/rockchip/rk3399pro-evb-v11-linux.dts b/arch/arm64/boot/dts/rockchip/rk3399pro-evb-v11-linux.dts
index c3faaa1ba4d3..84fc2c743c57 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399pro-evb-v11-linux.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3399pro-evb-v11-linux.dts
@@ -8,6 +8,7 @@
 #include <dt-bindings/display/drm_mipi_dsi.h>
 #include <dt-bindings/sensor-dev.h>
 #include <dt-bindings/pwm/pwm.h>
+#include "dt-bindings/usb/pd.h"
 #include "rk3399pro.dtsi"
 #include "rk3399-linux.dtsi"
 #include "rk3399-opp.dtsi"
@@ -201,6 +202,26 @@
 		status = "disabled";
 	};
 
+	vbus_typec: vbus-typec-regulator {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio1 18 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vcc5v0_typec0_en>;
+		regulator-name = "vbus_typec";
+		vin-supply = <&vcc5v0_sys>;
+	};
+
+	vbus_typec: vbus-typec-regulator {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio1 18 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vcc5v0_typec0_en>;
+		regulator-name = "vbus_typec";
+		vin-supply = <&vcc5v0_sys>;
+	};
+
 	vcc_phy: vcc-phy-regulator {
 		compatible = "regulator-fixed";
 		regulator-name = "vcc_phy";
@@ -243,7 +264,6 @@
 
 &cdn_dp {
 	status = "okay";
-	extcon = <&fusb0>;
 	phys = <&tcphy0_dp>;
 };
 
@@ -657,7 +677,6 @@
 	bq25700: bq25700@6b {
 		compatible = "ti,bq25703";
 		reg = <0x6b>;
-		extcon = <&fusb0>;
 		interrupt-parent = <&gpio1>;
 		interrupts = <RK_PA1 IRQ_TYPE_LEVEL_LOW>;
 		pinctrl-names = "default";
@@ -786,16 +805,53 @@
 	i2c-scl-falling-time-ns = <11>;
 	clock-frequency = <100000>;
 
-	fusb0: fusb30x@22 {
-		compatible = "fairchild,fusb302";
+	usbc0: fusb302@22 {
+		compatible = "fcs,fusb302";
 		reg = <0x22>;
+		interrupt-parent = <&gpio1>;
+		interrupts = <RK_PA2 IRQ_TYPE_LEVEL_LOW>;
 		pinctrl-names = "default";
-		pinctrl-0 = <&fusb0_int>;
-		int-n-gpios = <&gpio1 RK_PA2 GPIO_ACTIVE_HIGH>;
-		vbus-5v-gpios = <&gpio0 RK_PA1 GPIO_ACTIVE_LOW>;
+		pinctrl-0 = <&usbc0_int>;
+		vbus-supply = <&vbus_typec>;
 		status = "okay";
-	};
 
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+				usbc0_role_sw: endpoint@0 {
+					remote-endpoint = <&dwc3_0_role_switch>;
+				};
+			};
+		};
+
+		usb_con: connector {
+			compatible = "usb-c-connector";
+			label = "USB-C";
+			data-role = "dual";
+			power-role = "dual";
+			try-power-role = "sink";
+			op-sink-microwatt = <1000000>;
+			sink-pdos =
+				<PDO_FIXED(5000, 2500, PDO_FIXED_USB_COMM)>;
+			source-pdos =
+				<PDO_FIXED(5000, 1500, PDO_FIXED_USB_COMM)>;
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+					usbc0_orien_sw: endpoint {
+						remote-endpoint = <&tcphy0_orientation_switch>;
+					};
+				};
+			};
+		};
+	};
 };
 
 &i2s1 {
@@ -995,8 +1051,16 @@
 };
 
 &tcphy0 {
-	extcon = <&fusb0>;
 	status = "okay";
+	orientation-switch;
+	port {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		tcphy0_orientation_switch: endpoint@0 {
+			reg = <0>;
+			remote-endpoint = <&usbc0_orien_sw>;
+		};
+	};
 };
 
 &tcphy1 {
@@ -1011,7 +1075,6 @@
 
 &u2phy0 {
 	status = "okay";
-	extcon = <&fusb0>;
 
 	u2phy0_otg: otg-port {
 		status = "okay";
@@ -1067,7 +1130,15 @@
 
 &usbdrd_dwc3_0 {
 	status = "okay";
-	extcon = <&fusb0>;
+	usb-role-switch;
+	port {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		dwc3_0_role_switch: endpoint@0 {
+			reg = <0>;
+			remote-endpoint = <&usbc0_role_sw>;
+		};
+	};
 };
 
 &usbdrd_dwc3_1 {
@@ -1108,13 +1179,6 @@
 			};
 	};
 
-	fusb30x {
-		fusb0_int: fusb0-int {
-			rockchip,pins =
-				<1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>;
-			};
-	};
-
 	headphone {
 		hp_det: hp-det {
 			rockchip,pins =
@@ -1205,6 +1269,16 @@
 		};
 	};
 
+	usb-typec {
+		usbc0_int: usbc0-int {
+			rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+
+		vcc5v0_typec0_en: vcc5v0-typec0-en {
+			rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
 	wireless-bluetooth {
 		bt_irq_gpio: bt-irq-gpio {
 			rockchip,pins =
diff --git a/arch/arm64/boot/dts/rockchip/rk3399pro-evb-v11.dts b/arch/arm64/boot/dts/rockchip/rk3399pro-evb-v11.dts
index 7d118a783353..6fea49960e39 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399pro-evb-v11.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3399pro-evb-v11.dts
@@ -8,6 +8,7 @@
 #include <dt-bindings/display/drm_mipi_dsi.h>
 #include <dt-bindings/sensor-dev.h>
 #include <dt-bindings/pwm/pwm.h>
+#include "dt-bindings/usb/pd.h"
 #include "rk3399pro.dtsi"
 #include "rk3399-android.dtsi"
 #include "rk3399-opp.dtsi"
@@ -198,6 +199,16 @@
 		reset-gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_LOW>;
 	};
 
+	vbus_typec: vbus-typec-regulator {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio1 18 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vcc5v0_typec0_en>;
+		regulator-name = "vbus_typec";
+		vin-supply = <&vcc5v0_sys>;
+	};
+
 	vcc_phy: vcc-phy-regulator {
 		compatible = "regulator-fixed";
 		regulator-name = "vcc_phy";
@@ -240,7 +251,6 @@
 
 &cdn_dp {
 	status = "okay";
-	extcon = <&fusb0>;
 	phys = <&tcphy0_dp>;
 };
 
@@ -661,7 +671,6 @@
 	bq25700: bq25700@6b {
 		compatible = "ti,bq25703";
 		reg = <0x6b>;
-		extcon = <&fusb0>;
 		interrupt-parent = <&gpio1>;
 		interrupts = <RK_PA1 IRQ_TYPE_LEVEL_LOW>;
 		pinctrl-names = "default";
@@ -735,16 +744,53 @@
 	i2c-scl-falling-time-ns = <11>;
 	clock-frequency = <100000>;
 
-	fusb0: fusb30x@22 {
-		compatible = "fairchild,fusb302";
+	usbc0: fusb302@22 {
+		compatible = "fcs,fusb302";
 		reg = <0x22>;
+		interrupt-parent = <&gpio1>;
+		interrupts = <RK_PA2 IRQ_TYPE_LEVEL_LOW>;
 		pinctrl-names = "default";
-		pinctrl-0 = <&fusb0_int>;
-		int-n-gpios = <&gpio1 RK_PA2 GPIO_ACTIVE_HIGH>;
-		vbus-5v-gpios = <&gpio0 RK_PA1 GPIO_ACTIVE_LOW>;
+		pinctrl-0 = <&usbc0_int>;
+		vbus-supply = <&vbus_typec>;
 		status = "okay";
-	};
 
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+				usbc0_role_sw: endpoint@0 {
+					remote-endpoint = <&dwc3_0_role_switch>;
+				};
+			};
+		};
+
+		usb_con: connector {
+			compatible = "usb-c-connector";
+			label = "USB-C";
+			data-role = "dual";
+			power-role = "dual";
+			try-power-role = "sink";
+			op-sink-microwatt = <1000000>;
+			sink-pdos =
+				<PDO_FIXED(5000, 2500, PDO_FIXED_USB_COMM)>;
+			source-pdos =
+				<PDO_FIXED(5000, 1500, PDO_FIXED_USB_COMM)>;
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+					usbc0_orien_sw: endpoint {
+						remote-endpoint = <&tcphy0_orientation_switch>;
+					};
+				};
+			};
+		};
+	};
 };
 
 &i2s1 {
@@ -838,8 +884,16 @@
 };
 
 &tcphy0 {
-	extcon = <&fusb0>;
 	status = "okay";
+	orientation-switch;
+	port {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		tcphy0_orientation_switch: endpoint@0 {
+			reg = <0>;
+			remote-endpoint = <&usbc0_orien_sw>;
+		};
+	};
 };
 
 &tcphy1 {
@@ -854,7 +908,6 @@
 
 &u2phy0 {
 	status = "okay";
-	extcon = <&fusb0>;
 
 	u2phy0_otg: otg-port {
 		status = "okay";
@@ -911,7 +964,15 @@
 
 &usbdrd_dwc3_0 {
 	status = "okay";
-	extcon = <&fusb0>;
+	usb-role-switch;
+	port {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		dwc3_0_role_switch: endpoint@0 {
+			reg = <0>;
+			remote-endpoint = <&usbc0_role_sw>;
+		};
+	};
 };
 
 &usbdrd_dwc3_1 {
@@ -939,13 +1000,6 @@
 			};
 	};
 
-	fusb30x {
-		fusb0_int: fusb0-int {
-			rockchip,pins =
-				<1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>;
-			};
-	};
-
 	headphone {
 		hp_det: hp-det {
 			rockchip,pins =
@@ -1031,6 +1085,16 @@
 		};
 	};
 
+	usb-typec {
+		usbc0_int: usbc0-int {
+			rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+
+		vcc5v0_typec0_en: vcc5v0-typec0-en {
+			rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
 	wireless-bluetooth {
 		uart0_gpios: uart0-gpios {
 			rockchip,pins =
diff --git a/arch/arm64/boot/dts/rockchip/rk3568.dtsi b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
index 74fe31cba109..d7ff3bda8145 100644
--- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
@@ -584,6 +584,8 @@
 			snps,dis-tx-ipgap-linecheck-quirk;
 			snps,dis_rxdet_inp3_quirk;
 			snps,xhci-trb-ent-quirk;
+			snps,parkmode-disable-ss-quirk;
+			quirk-skip-phy-init;
 			status = "disabled";
 		};
 	};
@@ -617,6 +619,7 @@
 			snps,dis-tx-ipgap-linecheck-quirk;
 			snps,dis_rxdet_inp3_quirk;
 			snps,xhci-trb-ent-quirk;
+			snps,parkmode-disable-ss-quirk;
 			status = "disabled";
 		};
 	};
@@ -1775,12 +1778,12 @@
 			 <&cru SCLK_GMAC1_RX_TX>, <&cru CLK_MAC1_REFOUT>,
 			 <&cru ACLK_GMAC1>, <&cru PCLK_GMAC1>,
 			 <&cru SCLK_GMAC1_RX_TX>, <&cru CLK_GMAC1_PTP_REF>,
-			 <&cru PCLK_XPCS>;
+			 <&cru PCLK_XPCS>, <&cru CLK_XPCS_EEE>;
 		clock-names = "stmmaceth", "mac_clk_rx",
 			      "mac_clk_tx", "clk_mac_refout",
 			      "aclk_mac", "pclk_mac",
 			      "clk_mac_speed", "ptp_ref",
-			      "pclk_xpcs";
+			      "pclk_xpcs", "clk_xpcs_eee";
 		resets = <&cru SRST_A_GMAC1>;
 		reset-names = "stmmaceth";
 
@@ -2520,12 +2523,12 @@
 			 <&cru SCLK_GMAC0_RX_TX>, <&cru CLK_MAC0_REFOUT>,
 			 <&cru ACLK_GMAC0>, <&cru PCLK_GMAC0>,
 			 <&cru SCLK_GMAC0_RX_TX>, <&cru CLK_GMAC0_PTP_REF>,
-			 <&cru PCLK_XPCS>;
+			 <&cru PCLK_XPCS>, <&cru CLK_XPCS_EEE>;
 		clock-names = "stmmaceth", "mac_clk_rx",
 			      "mac_clk_tx", "clk_mac_refout",
 			      "aclk_mac", "pclk_mac",
 			      "clk_mac_speed", "ptp_ref",
-			      "pclk_xpcs";
+			      "pclk_xpcs", "clk_xpcs_eee";
 		resets = <&cru SRST_A_GMAC0>;
 		reset-names = "stmmaceth";
 
diff --git a/arch/arm64/boot/dts/rockchip/rk3588-evb.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-evb.dtsi
index 4882092c2ea5..412b2b3f889e 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588-evb.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588-evb.dtsi
@@ -218,6 +218,10 @@
 	status = "okay";
 };
 
+&avsd {
+	status = "okay";
+};
+
 &cpu_l0 {
 	cpu-supply = <&vdd_cpu_lit_s0>;
 	mem-supply = <&vdd_cpu_lit_mem_s0>;
diff --git a/arch/arm64/boot/dts/rockchip/rk3588-evb1-lp4-v10-lt6911uxe.dts b/arch/arm64/boot/dts/rockchip/rk3588-evb1-lp4-v10-lt6911uxe.dts
new file mode 100644
index 000000000000..d33e2bf449c2
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3588-evb1-lp4-v10-lt6911uxe.dts
@@ -0,0 +1,277 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2022 Rockchip Electronics Co., Ltd.
+ *
+ */
+/dts-v1/;
+
+#include "rk3588-evb1-lp4.dtsi"
+#include "rk3588-android.dtsi"
+
+/ {
+	model = "Rockchip RK3588 EVB1 LP4 V10 Board + Rockchip RK3588 EVB V10 Extboard";
+	compatible = "rockchip,rk3588-evb1-lp4-v10-lt6911uxe", "rockchip,rk3588";
+
+	vcc_mipicsi0: vcc-mipicsi0-regulator {
+		compatible = "regulator-fixed";
+		gpio = <&gpio1 RK_PB1 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&mipicsi0_pwr>;
+		regulator-name = "vcc_mipicsi0";
+		enable-active-high;
+		regulator-boot-on;
+		regulator-always-on;
+	};
+
+	vcc_mipidcphy0: vcc-mipidcphy0-regulator {
+		compatible = "regulator-fixed";
+		gpio = <&gpio2 RK_PC4 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&mipidcphy0_pwr>;
+		regulator-name = "vcc_mipidcphy0";
+		enable-active-high;
+		regulator-boot-on;
+		regulator-always-on;
+	};
+
+	ext_cam_clk: external-camera-clock {
+		compatible = "fixed-clock";
+		clock-frequency = <24000000>;
+		clock-output-names = "CLK_CAMERA_24MHZ";
+		#clock-cells = <0>;
+	};
+};
+
+&csi2_dphy0 {
+	status = "okay";
+
+	ports {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		port@0 {
+			reg = <0>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			hdmi_mipi2_in: endpoint@1 {
+				reg = <1>;
+				remote-endpoint = <&lt6911uxe_out1>;
+				data-lanes = <1 2 3 4>;
+			};
+		};
+		port@1 {
+			reg = <1>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			csidphy0_out: endpoint@0 {
+				reg = <0>;
+				remote-endpoint = <&mipi2_csi2_input>;
+			};
+		};
+	};
+};
+
+&csi2_dphy0_hw {
+	status = "okay";
+};
+
+&csi2_dcphy0 {
+	status = "okay";
+
+	ports {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		port@0 {
+			reg = <0>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			hdmi_mipi0_in: endpoint@1 {
+				reg = <1>;
+				remote-endpoint = <&lt6911uxe_out0>;
+				data-lanes = <1 2 3 4>;
+			};
+		};
+		port@1 {
+			reg = <1>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			csidcphy0_out: endpoint@0 {
+				reg = <0>;
+				remote-endpoint = <&mipi0_csi2_input>;
+			};
+		};
+	};
+};
+
+&i2c3 {
+	status = "okay";
+
+	lt6911uxe_1: lt6911uxe_1@2b {
+		compatible = "lontium,lt6911uxe";
+		status = "okay";
+		reg = <0x2b>;
+		clocks = <&ext_cam_clk>;
+		clock-names = "xvclk";
+		power-domains = <&power RK3588_PD_VI>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&lt6911uxe_pin_1>;
+		interrupt-parent = <&gpio1>;
+		interrupts = <RK_PB3 IRQ_TYPE_LEVEL_LOW>;
+		// reset-gpios = <&gpio1 RK_PB1 GPIO_ACTIVE_LOW>;
+		// power-gpios = <&gpio1 RK_PA6 GPIO_ACTIVE_HIGH>;
+		plugin-det-gpios = <&gpio1 RK_PB4 GPIO_ACTIVE_HIGH>;
+		rockchip,camera-module-index = <0>;
+		rockchip,camera-module-facing = "back";
+		rockchip,camera-module-name = "HDMI-MIPI2";
+		rockchip,camera-module-lens-name = "LT6911UXE-2";
+		port {
+			lt6911uxe_out1: endpoint {
+				remote-endpoint = <&hdmi_mipi2_in>;
+				data-lanes = <1 2 3 4>;
+			};
+		};
+	};
+};
+
+&i2c5 {
+	status = "okay";
+
+	lt6911uxe: lt6911uxe@2b {
+		compatible = "lontium,lt6911uxe";
+		status = "okay";
+		reg = <0x2b>;
+		clocks = <&ext_cam_clk>;
+		clock-names = "xvclk";
+		power-domains = <&power RK3588_PD_VI>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&lt6911uxe_pin>;
+		interrupt-parent = <&gpio1>;
+		interrupts = <RK_PA0 IRQ_TYPE_LEVEL_LOW>;
+		// reset-gpios = <&gpio1 RK_PB1 GPIO_ACTIVE_LOW>;
+		// power-gpios = <&gpio1 RK_PA6 GPIO_ACTIVE_HIGH>;
+		// plugin-det-gpios = <&gpio1 RK_PB4 GPIO_ACTIVE_LOW>;
+		plugin-det-gpios = <&gpio1 RK_PA1 GPIO_ACTIVE_HIGH>;
+		rockchip,camera-module-index = <1>;
+		rockchip,camera-module-facing = "front";
+		rockchip,camera-module-name = "HDMI-MIPI0";
+		rockchip,camera-module-lens-name = "LT6911UXC-0";
+
+		port {
+			lt6911uxe_out0: endpoint {
+				remote-endpoint = <&hdmi_mipi0_in>;
+				data-lanes = <1 2 3 4>;
+			};
+		};
+	};
+};
+
+&mipi_dcphy0 {
+	status = "okay";
+};
+
+&mipi0_csi2 {
+	status = "okay";
+
+	ports {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		port@0 {
+			reg = <0>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			mipi0_csi2_input: endpoint@1 {
+				reg = <1>;
+				remote-endpoint = <&csidcphy0_out>;
+			};
+		};
+
+		port@1 {
+			reg = <1>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			mipi0_csi2_output: endpoint@0 {
+				reg = <0>;
+				remote-endpoint = <&cif_mipi_in0>;
+			};
+		};
+	};
+};
+
+&mipi2_csi2 {
+	status = "okay";
+
+	ports {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		port@0 {
+			reg = <0>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			mipi2_csi2_input: endpoint@1 {
+				reg = <1>;
+				remote-endpoint = <&csidphy0_out>;
+			};
+		};
+
+		port@1 {
+			reg = <1>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			mipi2_csi2_output: endpoint@0 {
+				reg = <0>;
+				remote-endpoint = <&cif_mipi_in2>;
+			};
+		};
+	};
+};
+
+&rkcif {
+	status = "okay";
+};
+
+&rkcif_mipi_lvds {
+	status = "okay";
+
+	port {
+		cif_mipi_in0: endpoint {
+			remote-endpoint = <&mipi0_csi2_output>;
+		};
+	};
+};
+
+&rkcif_mipi_lvds2 {
+	status = "okay";
+
+	port {
+		cif_mipi_in2: endpoint {
+			remote-endpoint = <&mipi2_csi2_output>;
+		};
+	};
+};
+
+&rkcif_mmu {
+	status = "okay";
+};
+
+&pinctrl {
+	hdmiin {
+		lt6911uxe_pin: lt6911uxe-pin {
+			rockchip,pins = <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>,
+					<1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		lt6911uxe_pin_1: lt6911uxe-pin-1 {
+			rockchip,pins = <1 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>,
+					<1 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+};
diff --git a/arch/arm64/boot/dts/rockchip/rk3588-h0-imx415.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-h0-imx415.dtsi
new file mode 100644
index 000000000000..f5389891113d
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3588-h0-imx415.dtsi
@@ -0,0 +1,176 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2022 Rockchip Electronics Co., Ltd.
+ *
+ */
+
+/ {
+	cam_ircut0: cam_ircut {
+		status = "okay";
+		compatible = "rockchip,ircut";
+		ircut-open-gpios = <&gpio4 RK_PA0 GPIO_ACTIVE_HIGH>;
+		ircut-close-gpios  = <&gpio4 RK_PA1 GPIO_ACTIVE_HIGH>;
+		rockchip,camera-module-index = <0>;
+		rockchip,camera-module-facing = "back";
+	};
+	vcc_mipidphy0: vcc-mipidcphy0-regulator {
+		compatible = "regulator-fixed";
+		gpio = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&mipidphy0_pwr>;
+		regulator-name = "vcc_mipidphy0";
+		enable-active-high;
+	};
+};
+
+&csi2_dphy0 {
+	status = "okay";
+
+	ports {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		port@0 {
+			reg = <0>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			mipidphy0_in_ucam0: endpoint@1 {
+				reg = <1>;
+				remote-endpoint = <&imx415_out0>;
+				data-lanes = <1 2 3 4>;
+			};
+		};
+		port@1 {
+			reg = <1>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			csidphy0_out: endpoint@0 {
+				reg = <0>;
+				remote-endpoint = <&mipi2_csi2_input>;
+			};
+		};
+	};
+};
+
+&csi2_dphy0_hw {
+	status = "okay";
+};
+
+&i2c3 {
+	status = "okay";
+
+	imx415: imx415@1a {
+		compatible = "sony,imx415";
+		reg = <0x1a>;
+		clocks = <&cru CLK_MIPI_CAMARAOUT_M3>;
+		clock-names = "xvclk";
+		pinctrl-names = "default";
+		pinctrl-0 = <&mipim0_camera3_clk>;
+		power-domains = <&power RK3588_PD_VI>;
+		pwdn-gpios = <&gpio1 RK_PA7 GPIO_ACTIVE_HIGH>;
+		avdd-supply = <&vcc_mipidphy0>;
+		rockchip,camera-module-index = <0>;
+		rockchip,camera-module-facing = "back";
+		rockchip,camera-module-name = "CMK-OT2022-PX1";
+		rockchip,camera-module-lens-name = "IR0147-50IRC-8M-F20";
+		lens-focus = <&cam_ircut0>;
+		port {
+			imx415_out0: endpoint {
+				remote-endpoint = <&mipidphy0_in_ucam0>;
+				data-lanes = <1 2 3 4>;
+			};
+		};
+	};
+};
+
+&mipi2_csi2 {
+	status = "okay";
+
+	ports {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		port@0 {
+			reg = <0>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			mipi2_csi2_input: endpoint@1 {
+				reg = <1>;
+				remote-endpoint = <&csidphy0_out>;
+			};
+		};
+
+		port@1 {
+			reg = <1>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			mipi2_csi2_output: endpoint@0 {
+				reg = <0>;
+				remote-endpoint = <&cif_mipi2_in0>;
+			};
+		};
+	};
+};
+
+&pinctrl {
+	cam {
+		mipidphy0_pwr: mipidphy0-pwr {
+			rockchip,pins =
+				/* camera power en */
+				<1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+};
+
+&rkcif {
+	status = "okay";
+};
+
+&rkcif_mipi_lvds2 {
+	status = "okay";
+
+	port {
+		cif_mipi2_in0: endpoint {
+			remote-endpoint = <&mipi2_csi2_output>;
+		};
+	};
+};
+
+&rkcif_mipi_lvds2_sditf {
+	status = "okay";
+
+	port {
+		mipi_lvds2_sditf: endpoint {
+			remote-endpoint = <&isp0_vir0>;
+		};
+	};
+};
+
+&rkcif_mmu {
+	status = "okay";
+};
+
+&rkisp0 {
+	status = "okay";
+};
+
+&isp0_mmu {
+	status = "okay";
+};
+
+&rkisp0_vir0 {
+	status = "okay";
+
+	port {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		isp0_vir0: endpoint@0 {
+			reg = <0>;
+			remote-endpoint = <&mipi_lvds2_sditf>;
+		};
+	};
+};
diff --git a/arch/arm64/boot/dts/rockchip/rk3588-h0-v10-linux.dts b/arch/arm64/boot/dts/rockchip/rk3588-h0-v10-linux.dts
new file mode 100644
index 000000000000..047c51448985
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3588-h0-v10-linux.dts
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2022 Rockchip Electronics Co., Ltd.
+ *
+ */
+
+/dts-v1/;
+
+#include "rk3588-h0.dtsi"
+#include "rk3588-h0-imx415.dtsi"
+#include "rk3588-linux.dtsi"
+
+/ {
+	model = "Rockchip RK3588 H0 V10 Board";
+	compatible = "rockchip,rk3588-h0-v10", "rockchip,rk3588";
+};
diff --git a/arch/arm64/boot/dts/rockchip/rk3588-h0-v10.dts b/arch/arm64/boot/dts/rockchip/rk3588-h0-v10.dts
new file mode 100644
index 000000000000..8037e39cdef9
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3588-h0-v10.dts
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2022 Rockchip Electronics Co., Ltd.
+ *
+ */
+
+/dts-v1/;
+
+#include "rk3588-h0.dtsi"
+#include "rk3588-h0-imx415.dtsi"
+#include "rk3588-android.dtsi"
+
+/ {
+	model = "Rockchip RK3588 H0 V10 Board";
+	compatible = "rockchip,rk3588-h0-v10", "rockchip,rk3588";
+};
diff --git a/arch/arm64/boot/dts/rockchip/rk3588-h0.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-h0.dtsi
new file mode 100644
index 000000000000..2ff1c7629638
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3588-h0.dtsi
@@ -0,0 +1,935 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2022 Rockchip Electronics Co., Ltd.
+ *
+ */
+
+#include "dt-bindings/usb/pd.h"
+#include "rk3588.dtsi"
+#include "rk3588-evb.dtsi"
+#include "rk3588-rk806-single.dtsi"
+
+/ {
+	/* If hdmirx node is disabled, delete the reserved-memory node here. */
+	reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		/* Reserve 128MB memory for hdmirx-controller@fdee0000 */
+		cma {
+			compatible = "shared-dma-pool";
+			reusable;
+			reg = <0x0 (256 * 0x100000) 0x0 (128 * 0x100000)>;
+			linux,cma-default;
+		};
+	};
+
+	es8388_sound: es8388-sound {
+		status = "okay";
+		compatible = "rockchip,multicodecs-card";
+		rockchip,card-name = "rockchip-es8388";
+		hp-det-gpio = <&gpio1 RK_PC4 GPIO_ACTIVE_LOW>;
+		io-channels = <&saradc 3>;
+		io-channel-names = "adc-detect";
+		keyup-threshold-microvolt = <1800000>;
+		poll-interval = <100>;
+		spk-con-gpio = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>;
+		hp-con-gpio = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>;
+		rockchip,format = "i2s";
+		rockchip,mclk-fs = <256>;
+		rockchip,cpu = <&i2s0_8ch>;
+		rockchip,codec = <&es8388>;
+		rockchip,audio-routing =
+			"Headphone", "LOUT1",
+			"Headphone", "ROUT1",
+			"Speaker", "LOUT2",
+			"Speaker", "ROUT2",
+			"Headphone", "Headphone Power",
+			"Headphone", "Headphone Power",
+			"Speaker", "Speaker Power",
+			"Speaker", "Speaker Power",
+			"LINPUT1", "Main Mic",
+			"LINPUT2", "Main Mic",
+			"RINPUT1", "Headset Mic",
+			"RINPUT2", "Headset Mic";
+		pinctrl-names = "default";
+		pinctrl-0 = <&hp_det>;
+		play-pause-key {
+			label = "playpause";
+			linux,code = <KEY_PLAYPAUSE>;
+			press-threshold-microvolt = <2000>;
+		};
+	};
+
+	fan: pwm-fan {
+		compatible = "pwm-fan";
+		#cooling-cells = <2>;
+		pwms = <&pwm3 0 50000 0>;
+		cooling-levels = <0 50 100 150 200 255>;
+		rockchip,temp-trips = <
+			50000	1
+			55000	2
+			60000	3
+			65000	4
+			70000	5
+		>;
+	};
+
+	hdmiin-sound {
+		compatible = "rockchip,hdmi";
+		rockchip,mclk-fs = <128>;
+		rockchip,format = "i2s";
+		rockchip,bitclock-master = <&hdmirx_ctrler>;
+		rockchip,frame-master = <&hdmirx_ctrler>;
+		rockchip,card-name = "rockchip,hdmiin";
+		rockchip,cpu = <&i2s7_8ch>;
+		rockchip,codec = <&hdmirx_ctrler 0>;
+		rockchip,jack-det;
+	};
+
+	pcie20_avdd0v85: pcie20-avdd0v85 {
+		compatible = "regulator-fixed";
+		regulator-name = "pcie20_avdd0v85";
+		regulator-boot-on;
+		regulator-always-on;
+		regulator-min-microvolt = <850000>;
+		regulator-max-microvolt = <850000>;
+		vin-supply = <&vdd_0v85_s0>;
+	};
+
+	pcie20_avdd1v8: pcie20-avdd1v8 {
+		compatible = "regulator-fixed";
+		regulator-name = "pcie20_avdd1v8";
+		regulator-boot-on;
+		regulator-always-on;
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		vin-supply = <&avcc_1v8_s0>;
+	};
+
+	pcie30_avdd0v75: pcie30-avdd0v75 {
+		compatible = "regulator-fixed";
+		regulator-name = "pcie30_avdd0v75";
+		regulator-boot-on;
+		regulator-always-on;
+		regulator-min-microvolt = <750000>;
+		regulator-max-microvolt = <750000>;
+		vin-supply = <&avdd_0v75_s0>;
+	};
+
+	pcie30_avdd1v8: pcie30-avdd1v8 {
+		compatible = "regulator-fixed";
+		regulator-name = "pcie30_avdd1v8";
+		regulator-boot-on;
+		regulator-always-on;
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		vin-supply = <&avcc_1v8_s0>;
+	};
+
+	sdio_pwrseq: sdio-pwrseq {
+		compatible = "mmc-pwrseq-simple";
+		clocks = <&hym8563>;
+		clock-names = "ext_clock";
+		pinctrl-names = "default";
+		pinctrl-0 = <&wifi_enable_h>;
+		/*
+		 * On the module itself this is one of these (depending
+		 * on the actual card populated):
+		 * - SDIO_RESET_L_WL_REG_ON
+		 * - PDN (power down when low)
+		 */
+		post-power-on-delay-ms = <200>;
+		reset-gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_LOW>;
+	};
+
+	rk_headset: rk-headset {
+		status = "disabled";
+		compatible = "rockchip_headset";
+		headset_gpio = <&gpio1 RK_PD5 GPIO_ACTIVE_LOW>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&hp_det>;
+		io-channels = <&saradc 3>;
+	};
+
+
+	vcc_1v1_nldo_s3: vcc-1v1-nldo-s3 {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_1v1_nldo_s3";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <1100000>;
+		regulator-max-microvolt = <1100000>;
+		vin-supply = <&vcc5v0_sys>;
+	};
+
+	vbus5v0_typec: vbus5v0-typec {
+		compatible = "regulator-fixed";
+		regulator-name = "vbus5v0_typec";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		enable-active-high;
+		gpio = <&gpio3 RK_PA6 GPIO_ACTIVE_HIGH>;
+		vin-supply = <&vcc5v0_usb>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&typec5v_pwren>;
+	};
+
+	vcc3v3_lcd_n: vcc3v3-lcd0-n {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc3v3_lcd0_n";
+		regulator-boot-on;
+		enable-active-high;
+		gpio = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>;
+		vin-supply = <&vcc_1v8_s0>;
+	};
+
+	vcc3v3_pcie30: vcc3v3-pcie30 {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc3v3_pcie30";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		enable-active-high;
+		gpios = <&gpio2 RK_PC5 GPIO_ACTIVE_HIGH>;
+		startup-delay-us = <5000>;
+		vin-supply = <&vcc12v_dcin>;
+	};
+
+	vcc5v0_host: vcc5v0-host {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v0_host";
+		regulator-boot-on;
+		regulator-always-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		enable-active-high;
+		gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>;
+		vin-supply = <&vcc5v0_usb>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vcc5v0_host_en>;
+	};
+
+	vcc_mipicsi0: vcc-mipicsi0-regulator {
+		compatible = "regulator-fixed";
+		gpio = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&mipicsi0_pwr>;
+		regulator-name = "vcc_mipicsi0";
+		enable-active-high;
+	};
+
+	vcc_mipicsi1: vcc-mipicsi1-regulator {
+		compatible = "regulator-fixed";
+		gpio = <&gpio1 RK_PD3 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&mipicsi1_pwr>;
+		regulator-name = "vcc_mipicsi1";
+		enable-active-high;
+	};
+
+	vcc_mipidcphy0: vcc-mipidcphy0-regulator {
+		compatible = "regulator-fixed";
+		gpio = <&gpio2 RK_PC4 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&mipidcphy0_pwr>;
+		regulator-name = "vcc_mipidcphy0";
+		enable-active-high;
+	};
+
+	vcc_3v3_sd_s0: vcc-3v3-sd-s0-regulator {
+		compatible = "regulator-fixed";
+		gpio = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&sd_s0_pwr>;
+		regulator-name = "vcc_3v3_sd_s0";
+		enable-active-high;
+	};
+
+	wireless_bluetooth: wireless-bluetooth {
+		compatible = "bluetooth-platdata";
+		clocks = <&hym8563>;
+		clock-names = "ext_clock";
+		uart_rts_gpios = <&gpio4 RK_PC4 GPIO_ACTIVE_LOW>;
+		pinctrl-names = "default", "rts_gpio";
+		pinctrl-0 = <&uart9m0_rtsn>, <&bt_reset_gpio>, <&bt_wake_gpio>, <&bt_irq_gpio>;
+		pinctrl-1 = <&uart9_gpios>;
+		BT,reset_gpio    = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>;
+		BT,wake_gpio     = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>;
+		BT,wake_host_irq = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>;
+		status = "okay";
+	};
+
+	wireless_wlan: wireless-wlan {
+		compatible = "wlan-platdata";
+		wifi_chip_type = "ap6398s";
+		pinctrl-names = "default";
+		pinctrl-0 = <&wifi_host_wake_irq>;
+		WIFI,host_wake_irq = <&gpio0 RK_PB2 GPIO_ACTIVE_HIGH>;
+		WIFI,poweren_gpio = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>;
+		status = "okay";
+	};
+};
+
+&backlight {
+	pwms = <&pwm1 0 25000 0>;
+	status = "okay";
+};
+
+&combphy0_ps {
+	status = "okay";
+};
+
+&combphy1_ps {
+	status = "okay";
+};
+
+&combphy2_psu {
+	status = "okay";
+};
+
+&dp0 {
+	status = "okay";
+};
+&dp0_in_vp2 {
+	status = "okay";
+};
+
+&dp0_sound{
+	status = "okay";
+};
+&dp1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&dp1m0_pins>;
+	status = "okay";
+};
+
+&dp1_in_vp2 {
+	status = "okay";
+};
+
+/*
+ * mipi_dcphy0 needs to be enabled
+ * when dsi0 is enabled
+ */
+&dsi0 {
+	status = "okay";
+};
+
+&dsi0_in_vp2 {
+	status = "disabled";
+};
+
+&dsi0_in_vp3 {
+	status = "okay";
+};
+
+&dsi0_panel {
+	power-supply = <&vcc3v3_lcd_n>;
+	reset-gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_LOW>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&lcd_rst_gpio>;
+};
+
+/*
+ * mipi_dcphy1 needs to be enabled
+ * when dsi1 is enabled
+ */
+&dsi1 {
+	status = "disabled";
+};
+
+&dsi1_in_vp2 {
+	status = "disabled";
+};
+
+&dsi1_in_vp3 {
+	status = "disabled";
+};
+
+&dsi1_panel {
+	power-supply = <&vcc3v3_lcd_n>;
+
+	/*
+	 * because in hardware, the two screens share the reset pin,
+	 * so reset-gpios need only in dsi1 enable and dsi0 disabled
+	 * case.
+	 */
+
+	//reset-gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_LOW>;
+	//pinctrl-names = "default";
+	//pinctrl-0 = <&lcd_rst_gpio>;
+};
+
+&gmac1 {
+	/* Use rgmii-rxid mode to disable rx delay inside Soc */
+	phy-mode = "rgmii-rxid";
+	clock_in_out = "output";
+
+	snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
+	snps,reset-active-low;
+	/* Reset time is 20ms, 100ms for rtl8211f */
+	snps,reset-delays-us = <0 20000 100000>;
+
+	pinctrl-names = "default";
+	pinctrl-0 = <&gmac1_miim
+		     &gmac1_tx_bus2
+		     &gmac1_rx_bus2
+		     &gmac1_rgmii_clk
+		     &gmac1_rgmii_bus>;
+
+	tx_delay = <0x43>;
+	/* rx_delay = <0x3f>; */
+
+	phy-handle = <&rgmii_phy>;
+	status = "okay";
+};
+
+&hdmi0 {
+	enable-gpios = <&gpio4 RK_PB1 GPIO_ACTIVE_HIGH>;
+	status = "okay";
+};
+
+&hdmi0_in_vp0 {
+	status = "okay";
+};
+
+&hdmi0_sound {
+	status = "okay";
+};
+
+&hdmi1 {
+	enable-gpios = <&gpio4 RK_PB2 GPIO_ACTIVE_HIGH>;
+	status = "okay";
+};
+
+&hdmi1_in_vp1 {
+	status = "okay";
+};
+
+&hdmi1_sound {
+	status = "okay";
+};
+
+/* Should work with at least 128MB cma reserved above. */
+&hdmirx_ctrler {
+	status = "okay";
+
+	#sound-dai-cells = <1>;
+	/* Effective level used to trigger HPD: 0-low, 1-high */
+	hpd-trigger-level = <1>;
+	hdmirx-det-gpios = <&gpio1 RK_PD5 GPIO_ACTIVE_LOW>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&hdmim1_rx &hdmirx_det>;
+};
+
+&hdptxphy_hdmi0 {
+	status = "okay";
+};
+
+&hdptxphy_hdmi1 {
+	status = "okay";
+};
+
+&i2c0 {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c0m2_xfer>;
+
+	vdd_cpu_big0_s0: vdd_cpu_big0_mem_s0: rk8602@42 {
+		compatible = "rockchip,rk8602";
+		reg = <0x42>;
+		vin-supply = <&vcc5v0_sys>;
+		regulator-compatible = "rk860x-reg";
+		regulator-name = "vdd_cpu_big0_s0";
+		regulator-min-microvolt = <550000>;
+		regulator-max-microvolt = <1050000>;
+		regulator-ramp-delay = <2300>;
+		rockchip,suspend-voltage-selector = <1>;
+		regulator-boot-on;
+		regulator-always-on;
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+	};
+
+	vdd_cpu_big1_s0: vdd_cpu_big1_mem_s0: rk8603@43 {
+		compatible = "rockchip,rk8603";
+		reg = <0x43>;
+		vin-supply = <&vcc5v0_sys>;
+		regulator-compatible = "rk860x-reg";
+		regulator-name = "vdd_cpu_big1_s0";
+		regulator-min-microvolt = <550000>;
+		regulator-max-microvolt = <1050000>;
+		regulator-ramp-delay = <2300>;
+		rockchip,suspend-voltage-selector = <1>;
+		regulator-boot-on;
+		regulator-always-on;
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+	};
+};
+
+&i2c1 {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c1m2_xfer>;
+
+	vdd_npu_s0: vdd_npu_mem_s0: rk8602@42 {
+		compatible = "rockchip,rk8602";
+		reg = <0x42>;
+		vin-supply = <&vcc5v0_sys>;
+		regulator-compatible = "rk860x-reg";
+		regulator-name = "vdd_npu_s0";
+		regulator-min-microvolt = <550000>;
+		regulator-max-microvolt = <950000>;
+		regulator-ramp-delay = <2300>;
+		rockchip,suspend-voltage-selector = <1>;
+		regulator-boot-on;
+		regulator-always-on;
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+	};
+};
+
+&i2c4 {
+	status = "okay";
+	pinctrl-0 = <&i2c4m1_xfer>;
+
+	ls_stk3332: light@47 {
+		compatible = "ls_stk3332";
+		status = "disabled";
+		reg = <0x47>;
+		type = <SENSOR_TYPE_LIGHT>;
+		irq_enable = <0>;
+		als_threshold_high = <100>;
+		als_threshold_low = <10>;
+		als_ctrl_gain = <2>; /* 0:x1 1:x4 2:x16 3:x64 */
+		poll_delay_ms = <100>;
+	};
+
+	ps_stk3332: proximity@47 {
+		compatible = "ps_stk3332";
+		status = "disabled";
+		reg = <0x47>;
+		type = <SENSOR_TYPE_PROXIMITY>;
+		//pinctrl-names = "default";
+		//pinctrl-0 = <&gpio3_c6>;
+		//irq-gpio = <&gpio3 RK_PC6 IRQ_TYPE_LEVEL_LOW>;
+		//irq_enable = <1>;
+		ps_threshold_high = <0x200>;
+		ps_threshold_low = <0x100>;
+		ps_ctrl_gain = <3>; /* 0:x1 1:x2 2:x5 3:x8 */
+		ps_led_current = <4>; /* 0:3.125mA 1:6.25mA 2:12.5mA 3:25mA 4:50mA 5:100mA*/
+		poll_delay_ms = <100>;
+	};
+
+	mpu6500_acc: mpu_acc@68 {
+		compatible = "mpu6500_acc";
+		reg = <0x68>;
+		irq-gpio = <&gpio4 RK_PC2 IRQ_TYPE_EDGE_RISING>;
+		irq_enable = <0>;
+		poll_delay_ms = <30>;
+		type = <SENSOR_TYPE_ACCEL>;
+		layout = <5>;
+	};
+
+	mpu6500_gyro: mpu_gyro@68 {
+		compatible = "mpu6500_gyro";
+		reg = <0x68>;
+		poll_delay_ms = <30>;
+		type = <SENSOR_TYPE_GYROSCOPE>;
+		layout = <5>;
+	};
+};
+
+&i2c5 {
+	status = "okay";
+	gt1x: gt1x@14 {
+		compatible = "goodix,gt1x";
+		reg = <0x14>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&touch_gpio>;
+		goodix,rst-gpio = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>;
+		goodix,irq-gpio = <&gpio3 RK_PC0 IRQ_TYPE_LEVEL_LOW>;
+		power-supply = <&vcc3v3_lcd_n>;
+	};
+};
+
+&i2c6 {
+	status = "okay";
+
+	usbc0: fusb302@22 {
+		compatible = "fcs,fusb302";
+		reg = <0x22>;
+		interrupt-parent = <&gpio3>;
+		interrupts = <RK_PB6 IRQ_TYPE_LEVEL_LOW>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&usbc0_int>;
+		vbus-supply = <&vbus5v0_typec>;
+		status = "okay";
+
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+				usbc0_role_sw: endpoint@0 {
+					remote-endpoint = <&dwc3_0_role_switch>;
+				};
+			};
+		};
+
+		usb_con: connector {
+			compatible = "usb-c-connector";
+			label = "USB-C";
+			data-role = "dual";
+			power-role = "dual";
+			try-power-role = "sink";
+			op-sink-microwatt = <1000000>;
+			sink-pdos =
+				<PDO_FIXED(5000, 1000, PDO_FIXED_USB_COMM)>;
+			source-pdos =
+				<PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
+
+			altmodes {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				altmode@0 {
+					reg = <0>;
+					svid = <0xff01>;
+					vdo = <0xffffffff>;
+				};
+			};
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+					usbc0_orien_sw: endpoint {
+						remote-endpoint = <&usbdp_phy0_orientation_switch>;
+					};
+				};
+
+				port@1 {
+					reg = <1>;
+					dp_altmode_mux: endpoint {
+						remote-endpoint = <&usbdp_phy0_dp_altmode_mux>;
+					};
+				};
+			};
+		};
+	};
+
+	hym8563: hym8563@51 {
+		compatible = "haoyu,hym8563";
+		reg = <0x51>;
+		#clock-cells = <0>;
+		clock-frequency = <32768>;
+		clock-output-names = "hym8563";
+		pinctrl-names = "default";
+		pinctrl-0 = <&hym8563_int>;
+		interrupt-parent = <&gpio0>;
+		interrupts = <RK_PB0 IRQ_TYPE_LEVEL_LOW>;
+		wakeup-source;
+	};
+};
+
+&i2c7 {
+	status = "okay";
+	es8388: es8388@11 {
+		status = "okay";
+		#sound-dai-cells = <0>;
+		compatible = "everest,es8388", "everest,es8323";
+		reg = <0x11>;
+		clocks = <&cru I2S0_8CH_MCLKOUT>;
+		clock-names = "mclk";
+		assigned-clocks = <&cru I2S0_8CH_MCLKOUT>;
+		assigned-clock-rates = <12288000>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&i2s0_mclk>;
+	};
+};
+
+&i2s5_8ch {
+	status = "okay";
+};
+
+&i2s6_8ch {
+	status = "okay";
+};
+
+&i2s7_8ch {
+	status = "okay";
+};
+
+&mdio1 {
+	rgmii_phy: phy@1 {
+		compatible = "ethernet-phy-ieee802.3-c22";
+		reg = <0x1>;
+	};
+};
+
+&mipi_dcphy0 {
+	status = "okay";
+};
+
+&mipi_dcphy1 {
+	status = "disabled";
+};
+
+&pcie2x1l0 {
+	reset-gpios = <&gpio1 RK_PB4 GPIO_ACTIVE_HIGH>;
+	status = "okay";
+};
+
+&pcie30phy {
+	rockchip,pcie30-phymode = <PHY_MODE_PCIE_AGGREGATION>;
+	status = "okay";
+};
+
+&pcie3x4 {
+	reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>;
+	vpcie3v3-supply = <&vcc3v3_pcie30>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pcie20x1_0_clkreqn_m1>;
+	status = "okay";
+};
+
+&pinctrl {
+	cam {
+		mipicsi0_pwr: mipicsi0-pwr {
+			rockchip,pins =
+				/* camera power en */
+				<1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+		mipicsi1_pwr: mipicsi1-pwr {
+			rockchip,pins =
+				/* camera power en */
+				<1 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+		mipidcphy0_pwr: mipidcphy0-pwr {
+			rockchip,pins =
+				/* camera power en */
+				<2 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+
+	hdmi {
+		hdmirx_det: hdmirx-det {
+			rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+
+	headphone {
+		hp_det: hp-det {
+			rockchip,pins = <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	hym8563 {
+		hym8563_int: hym8563-int {
+			rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+
+	lcd {
+		lcd_rst_gpio: lcd-rst-gpio {
+			rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	sdio-pwrseq {
+		wifi_enable_h: wifi-enable-h {
+			rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+
+	sdmmc {
+		sd_s0_pwr: sd-s0-pwr {
+			rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+
+	touch {
+		touch_gpio: touch-gpio {
+			rockchip,pins =
+				<3 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>,
+				<3 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+
+	usb {
+		vcc5v0_host_en: vcc5v0-host-en {
+			rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	usb-typec {
+		usbc0_int: usbc0-int {
+			rockchip,pins = <3 RK_PB6 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+
+		typec5v_pwren: typec5v-pwren {
+			rockchip,pins = <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	wireless-bluetooth {
+		uart9_gpios: uart9-gpios {
+			rockchip,pins = <4 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		bt_reset_gpio: bt-reset-gpio {
+			rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		bt_wake_gpio: bt-wake-gpio {
+			rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		bt_irq_gpio: bt-irq-gpio {
+			rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	wireless-wlan {
+		wifi_host_wake_irq: wifi-host-wake-irq {
+			rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_down>;
+		};
+	};
+
+	pcie {
+		pcie20x1_0_clkreqn_m1: pcie20x1-0-clkreqn-m1 {
+			rockchip,pins = <4 RK_PB4 RK_FUNC_GPIO &pcfg_output_low>;
+		};
+	};
+};
+
+&pwm1 {
+	status = "okay";
+};
+
+&pwm3 {
+	pinctrl-0 = <&pwm3m1_pins>;
+	status = "okay";
+};
+
+&route_dsi0 {
+	status = "okay";
+	connect = <&vp3_out_dsi0>;
+};
+
+&route_dsi1 {
+	status = "disabled";
+	connect = <&vp3_out_dsi1>;
+};
+
+&route_hdmi0 {
+	status = "okay";
+};
+
+&route_hdmi1 {
+	status = "okay";
+};
+
+&sata0 {
+	status = "okay";
+};
+
+&sdio {
+	max-frequency = <150000000>;
+	no-sd;
+	no-mmc;
+	bus-width = <4>;
+	disable-wp;
+	cap-sd-highspeed;
+	cap-sdio-irq;
+	keep-power-in-suspend;
+	mmc-pwrseq = <&sdio_pwrseq>;
+	non-removable;
+	pinctrl-names = "default";
+	pinctrl-0 = <&sdiom0_pins>;
+	sd-uhs-sdr104;
+	status = "okay";
+};
+
+&sdmmc {
+	status = "okay";
+	vmmc-supply = <&vcc_3v3_sd_s0>;
+};
+
+&uart9 {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart9m0_xfer &uart9m0_ctsn>;
+};
+
+&u2phy0_otg {
+	rockchip,typec-vbus-det;
+};
+
+&u2phy1_otg {
+	phy-supply = <&vcc5v0_host>;
+};
+
+&u2phy2_host {
+	phy-supply = <&vcc5v0_host>;
+};
+
+&u2phy3_host {
+	phy-supply = <&vcc5v0_host>;
+};
+
+&usbdp_phy0 {
+	orientation-switch;
+	svid = <0xff01>;
+	sbu1-dc-gpios = <&gpio4 RK_PA0 GPIO_ACTIVE_HIGH>;
+	sbu2-dc-gpios = <&gpio4 RK_PA1 GPIO_ACTIVE_HIGH>;
+
+	port {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		usbdp_phy0_orientation_switch: endpoint@0 {
+			reg = <0>;
+			remote-endpoint = <&usbc0_orien_sw>;
+		};
+
+		usbdp_phy0_dp_altmode_mux: endpoint@1 {
+			reg = <1>;
+			remote-endpoint = <&dp_altmode_mux>;
+		};
+	};
+};
+
+&usbdp_phy1 {
+	rockchip,dp-lane-mux = <0 1 2 3>;
+};
+
+&usbdrd_dwc3_0 {
+	dr_mode = "otg";
+	usb-role-switch;
+	port {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		dwc3_0_role_switch: endpoint@0 {
+			reg = <0>;
+			remote-endpoint = <&usbc0_role_sw>;
+		};
+	};
+};
+
+&usbhost3_0 {
+	status = "disabled";
+};
+
+&usbhost_dwc3_0 {
+	status = "disabled";
+};
diff --git a/arch/arm64/boot/dts/rockchip/rk3588.dtsi b/arch/arm64/boot/dts/rockchip/rk3588.dtsi
index cb78040568c7..20d95661fd70 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588.dtsi
@@ -139,6 +139,7 @@
 			snps,dis-u2-freeclk-exists-quirk;
 			snps,dis-del-phy-power-chg-quirk;
 			snps,dis-tx-ipgap-linecheck-quirk;
+			snps,parkmode-disable-ss-quirk;
 			status = "disabled";
 		};
 	};
diff --git a/arch/arm64/boot/dts/rockchip/rk3588j.dtsi b/arch/arm64/boot/dts/rockchip/rk3588j.dtsi
index 6f8b262965be..097c7ce386b7 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588j.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588j.dtsi
@@ -8,6 +8,7 @@
 
 &cluster0_opp_table {
 	/delete-node/ opp-1608000000;
+	/delete-node/ opp-1704000000;
 	/delete-node/ opp-1800000000;
 };
 
diff --git a/arch/arm64/boot/dts/rockchip/rk3588m.dtsi b/arch/arm64/boot/dts/rockchip/rk3588m.dtsi
index ca2250be0dd9..1a30a0375033 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588m.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588m.dtsi
@@ -8,26 +8,6 @@
 
 &cluster0_opp_table {
 	/delete-node/ opp-1800000000;
-
-	opp-1704000000 {
-		opp-supported-hw = <0x02 0xffff>;
-		opp-hz = /bits/ 64 <1704000000>;
-		opp-microvolt = <900000 900000 950000>,
-				<900000 900000 950000>;
-		opp-microvolt-L1 = <887500 887500 950000>,
-				   <887500 887500 950000>;
-		opp-microvolt-L2 = <875000 875000 950000>,
-				   <875000 875000 950000>;
-		opp-microvolt-L3 = <862500 862500 950000>,
-				   <862500 862500 950000>;
-		opp-microvolt-L4 = <850000 850000 950000>,
-				   <850000 850000 950000>;
-		opp-microvolt-L5 = <837500 837500 950000>,
-				   <837500 837500 950000>;
-		opp-microvolt-L6 = <825000 825000 950000>,
-				   <825000 825000 950000>;
-		clock-latency-ns = <40000>;
-	};
 };
 
 &cluster1_opp_table {
diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
index 68fce5bbc0e0..d9eb000ee3e0 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
@@ -596,8 +596,16 @@
 		rockchip,pvtm-thermal-zone = "soc-thermal";
 
 		rockchip,grf = <&litcore_grf>;
-
-		rockchip,reboot-freq = <1416000>;
+		rockchip,dsu-grf = <&dsu_grf>;
+		volt-mem-read-margin = <
+			855000	1
+			765000	2
+			675000	3
+			495000	4
+		>;
+		low-volt-mem-read-margin = <4>;
+		intermediate-threshold-freq = <1008000>;	/* KHz */
+		rockchip,reboot-freq = <1416000>;		/* KHz */
 
 		rockchip,temp-hysteresis = <5000>;
 		rockchip,low-temp = <10000>;
@@ -673,7 +681,7 @@
 			opp-suspend;
 		};
 		opp-1608000000 {
-			opp-supported-hw = <0xff 0xffff>;
+			opp-supported-hw = <0xfb 0xffff>;
 			opp-hz = /bits/ 64 <1608000000>;
 			opp-microvolt = <850000 850000 950000>,
 					<850000 850000 950000>;
@@ -691,8 +699,27 @@
 					   <787500 787500 950000>;
 			clock-latency-ns = <40000>;
 		};
+		opp-1704000000 {
+			opp-supported-hw = <0x02 0xffff>;
+			opp-hz = /bits/ 64 <1704000000>;
+			opp-microvolt = <900000 900000 950000>,
+					<900000 900000 950000>;
+			opp-microvolt-L1 = <887500 887500 950000>,
+					   <887500 887500 950000>;
+			opp-microvolt-L2 = <875000 875000 950000>,
+					   <875000 875000 950000>;
+			opp-microvolt-L3 = <862500 862500 950000>,
+					   <862500 862500 950000>;
+			opp-microvolt-L4 = <850000 850000 950000>,
+					   <850000 850000 950000>;
+			opp-microvolt-L5 = <837500 837500 950000>,
+					   <837500 837500 950000>;
+			opp-microvolt-L6 = <825000 825000 950000>,
+					   <825000 825000 950000>;
+			clock-latency-ns = <40000>;
+		};
 		opp-1800000000 {
-			opp-supported-hw = <0xfd 0xffff>;
+			opp-supported-hw = <0xf9 0xffff>;
 			opp-hz = /bits/ 64 <1800000000>;
 			opp-microvolt = <950000 950000 950000>,
 					<950000 950000 950000>;
@@ -833,7 +860,7 @@
 			clock-latency-ns = <40000>;
 		};
 		opp-1800000000 {
-			opp-supported-hw = <0xff 0xffff>;
+			opp-supported-hw = <0xfb 0xffff>;
 			opp-hz = /bits/ 64 <1800000000>;
 			opp-microvolt = <850000 850000 1000000>,
 					<850000 850000 1000000>;
@@ -854,7 +881,7 @@
 			clock-latency-ns = <40000>;
 		};
 		opp-2016000000 {
-			opp-supported-hw = <0xff 0xffff>;
+			opp-supported-hw = <0xfb 0xffff>;
 			opp-hz = /bits/ 64 <2016000000>;
 			opp-microvolt = <925000 925000 1000000>,
 					<925000 925000 1000000>;
@@ -875,7 +902,7 @@
 			clock-latency-ns = <40000>;
 		};
 		opp-2208000000 {
-			opp-supported-hw = <0xfd 0xffff>;
+			opp-supported-hw = <0xf9 0xffff>;
 			opp-hz = /bits/ 64 <2208000000>;
 			opp-microvolt = <987500 987500 1000000>,
 					<987500 987500 1000000>;
@@ -896,28 +923,28 @@
 			clock-latency-ns = <40000>;
 		};
 		opp-2256000000 {
-			opp-supported-hw = <0xfd 0x13>;
+			opp-supported-hw = <0xf9 0x13>;
 			opp-hz = /bits/ 64 <2256000000>;
 			opp-microvolt = <1000000 1000000 1000000>,
 					<1000000 1000000 1000000>;
 			clock-latency-ns = <40000>;
 		};
 		opp-2304000000 {
-			opp-supported-hw = <0xfd 0x24>;
+			opp-supported-hw = <0xf9 0x24>;
 			opp-hz = /bits/ 64 <2304000000>;
 			opp-microvolt = <1000000 1000000 1000000>,
 					<1000000 1000000 1000000>;
 			clock-latency-ns = <40000>;
 		};
 		opp-2352000000 {
-			opp-supported-hw = <0xfd 0x48>;
+			opp-supported-hw = <0xf9 0x48>;
 			opp-hz = /bits/ 64 <2352000000>;
 			opp-microvolt = <1000000 1000000 1000000>,
 					<1000000 1000000 1000000>;
 			clock-latency-ns = <40000>;
 		};
 		opp-2400000000 {
-			opp-supported-hw = <0xfd 0x80>;
+			opp-supported-hw = <0xf9 0x80>;
 			opp-hz = /bits/ 64 <2400000000>;
 			opp-microvolt = <1000000 1000000 1000000>,
 					<1000000 1000000 1000000>;
@@ -1046,7 +1073,7 @@
 			clock-latency-ns = <40000>;
 		};
 		opp-1800000000 {
-			opp-supported-hw = <0xff 0xffff>;
+			opp-supported-hw = <0xfb 0xffff>;
 			opp-hz = /bits/ 64 <1800000000>;
 			opp-microvolt = <850000 850000 1000000>,
 					<850000 850000 1000000>;
@@ -1067,7 +1094,7 @@
 			clock-latency-ns = <40000>;
 		};
 		opp-2016000000 {
-			opp-supported-hw = <0xff 0xffff>;
+			opp-supported-hw = <0xfb 0xffff>;
 			opp-hz = /bits/ 64 <2016000000>;
 			opp-microvolt = <925000 925000 1000000>,
 					<925000 925000 1000000>;
@@ -1088,7 +1115,7 @@
 			clock-latency-ns = <40000>;
 		};
 		opp-2208000000 {
-			opp-supported-hw = <0xfd 0xffff>;
+			opp-supported-hw = <0xf9 0xffff>;
 			opp-hz = /bits/ 64 <2208000000>;
 			opp-microvolt = <987500 987500 1000000>,
 					<987500 987500 1000000>;
@@ -1105,28 +1132,28 @@
 			clock-latency-ns = <40000>;
 		};
 		opp-2256000000 {
-			opp-supported-hw = <0xfd 0x13>;
+			opp-supported-hw = <0xf9 0x13>;
 			opp-hz = /bits/ 64 <2256000000>;
 			opp-microvolt = <1000000 1000000 1000000>,
 					<1000000 1000000 1000000>;
 			clock-latency-ns = <40000>;
 		};
 		opp-2304000000 {
-			opp-supported-hw = <0xfd 0x24>;
+			opp-supported-hw = <0xf9 0x24>;
 			opp-hz = /bits/ 64 <2304000000>;
 			opp-microvolt = <1000000 1000000 1000000>,
 					<1000000 1000000 1000000>;
 			clock-latency-ns = <40000>;
 		};
 		opp-2352000000 {
-			opp-supported-hw = <0xfd 0x48>;
+			opp-supported-hw = <0xf9 0x48>;
 			opp-hz = /bits/ 64 <2352000000>;
 			opp-microvolt = <1000000 1000000 1000000>,
 					<1000000 1000000 1000000>;
 			clock-latency-ns = <40000>;
 		};
 		opp-2400000000 {
-			opp-supported-hw = <0xfd 0x80>;
+			opp-supported-hw = <0xf9 0x80>;
 			opp-hz = /bits/ 64 <2400000000>;
 			opp-microvolt = <1000000 1000000 1000000>,
 					<1000000 1000000 1000000>;
@@ -1757,8 +1784,9 @@
 	gpu_opp_table: gpu-opp-table {
 		compatible = "operating-points-v2";
 
-		nvmem-cells = <&gpu_leakage>;
-		nvmem-cell-names = "leakage";
+		nvmem-cells = <&gpu_leakage>, <&specification_serial_number>;
+		nvmem-cell-names = "leakage", "specification_serial_number";
+		rockchip,supported-hw;
 
 		rockchip,pvtm-voltage-sel = <
 			0	815	0
@@ -1796,26 +1824,31 @@
 		rockchip,high-temp-max-freq = <800000>;
 
 		opp-300000000 {
+			opp-supported-hw = <0xff 0xffff>;
 			opp-hz = /bits/ 64 <300000000>;
 			opp-microvolt = <675000 675000 850000>,
 					<675000 675000 850000>;
 		};
 		opp-400000000 {
+			opp-supported-hw = <0xff 0xffff>;
 			opp-hz = /bits/ 64 <400000000>;
 			opp-microvolt = <675000 675000 850000>,
 					<675000 675000 850000>;
 		};
 		opp-500000000 {
+			opp-supported-hw = <0xff 0xffff>;
 			opp-hz = /bits/ 64 <500000000>;
 			opp-microvolt = <675000 675000 850000>,
 					<675000 675000 850000>;
 		};
 		opp-600000000 {
+			opp-supported-hw = <0xff 0xffff>;
 			opp-hz = /bits/ 64 <600000000>;
 			opp-microvolt = <675000 675000 850000>,
 					<675000 675000 850000>;
 		};
 		opp-700000000 {
+			opp-supported-hw = <0xff 0xffff>;
 			opp-hz = /bits/ 64 <700000000>;
 			opp-microvolt = <700000 700000 850000>,
 					<700000 700000 850000>;
@@ -1829,6 +1862,7 @@
 					   <675000 675000 850000>;
 		};
 		opp-800000000 {
+			opp-supported-hw = <0xff 0xffff>;
 			opp-hz = /bits/ 64 <800000000>;
 			opp-microvolt = <750000 750000 850000>,
 					<750000 750000 850000>;
@@ -1844,6 +1878,7 @@
 					   <700000 700000 850000>;
 		};
 		opp-900000000 {
+			opp-supported-hw = <0xfb 0xffff>;
 			opp-hz = /bits/ 64 <900000000>;
 			opp-microvolt = <800000 800000 850000>,
 					<800000 800000 850000>;
@@ -1859,6 +1894,7 @@
 					   <737500 737500 850000>;
 		};
 		opp-1000000000 {
+			opp-supported-hw = <0xfb 0xffff>;
 			opp-hz = /bits/ 64 <1000000000>;
 			opp-microvolt = <850000 850000 850000>,
 					<850000 850000 850000>;
@@ -1903,6 +1939,7 @@
 			snps,dis-u2-freeclk-exists-quirk;
 			snps,dis-del-phy-power-chg-quirk;
 			snps,dis-tx-ipgap-linecheck-quirk;
+			snps,parkmode-disable-ss-quirk;
 			quirk-skip-phy-init;
 			status = "disabled";
 		};
@@ -2008,6 +2045,7 @@
 			snps,dis-del-phy-power-chg-quirk;
 			snps,dis-tx-ipgap-linecheck-quirk;
 			snps,dis_rxdet_inp3_quirk;
+			snps,parkmode-disable-ss-quirk;
 			status = "disabled";
 		};
 	};
@@ -2728,8 +2766,9 @@
 	npu_opp_table: npu-opp-table {
 		compatible = "operating-points-v2";
 
-		nvmem-cells = <&npu_leakage>;
-		nvmem-cell-names = "leakage";
+		nvmem-cells = <&npu_leakage>, <&specification_serial_number>;
+		nvmem-cell-names = "leakage", "specification_serial_number";
+		rockchip,supported-hw;
 
 		rockchip,pvtm-voltage-sel = <
 			0	815	0
@@ -2768,6 +2807,7 @@
 		rockchip,high-temp-max-freq = <800000>;
 
 		opp-300000000 {
+			opp-supported-hw = <0xff 0xffff>;
 			opp-hz = /bits/ 64 <300000000>;
 			opp-microvolt = <700000 700000 850000>,
 					<700000 700000 850000>;
@@ -2783,6 +2823,7 @@
 					   <675000 675000 850000>;
 		};
 		opp-400000000 {
+			opp-supported-hw = <0xff 0xffff>;
 			opp-hz = /bits/ 64 <400000000>;
 			opp-microvolt = <700000 700000 850000>,
 					<700000 700000 850000>;
@@ -2798,6 +2839,7 @@
 					   <675000 675000 850000>;
 		};
 		opp-500000000 {
+			opp-supported-hw = <0xff 0xffff>;
 			opp-hz = /bits/ 64 <500000000>;
 			opp-microvolt = <700000 700000 850000>,
 					<700000 700000 850000>;
@@ -2813,6 +2855,7 @@
 					   <675000 675000 850000>;
 		};
 		opp-600000000 {
+			opp-supported-hw = <0xff 0xffff>;
 			opp-hz = /bits/ 64 <600000000>;
 			opp-microvolt = <700000 700000 850000>,
 					<700000 700000 850000>;
@@ -2828,6 +2871,7 @@
 					   <675000 675000 850000>;
 		};
 		opp-700000000 {
+			opp-supported-hw = <0xff 0xffff>;
 			opp-hz = /bits/ 64 <700000000>;
 			opp-microvolt = <700000 700000 850000>,
 					<700000 700000 850000>;
@@ -2839,6 +2883,7 @@
 					   <675000 675000 850000>;
 		};
 		opp-800000000 {
+			opp-supported-hw = <0xff 0xffff>;
 			opp-hz = /bits/ 64 <800000000>;
 			opp-microvolt = <750000 750000 850000>,
 					<750000 750000 850000>;
@@ -2852,6 +2897,7 @@
 					   <700000 700000 850000>;
 		};
 		opp-900000000 {
+			opp-supported-hw = <0xfb 0xffff>;
 			opp-hz = /bits/ 64 <900000000>;
 			opp-microvolt = <800000 800000 850000>,
 					<800000 800000 850000>;
@@ -2867,6 +2913,7 @@
 					   <737500 737500 850000>;
 		};
 		opp-1000000000 {
+			opp-supported-hw = <0xfb 0xffff>;
 			opp-hz = /bits/ 64 <1000000000>;
 			opp-microvolt = <850000 850000 850000>,
 					<850000 850000 850000>;
@@ -2964,6 +3011,7 @@
 		clock-names = "aclk_vcodec", "hclk_vcodec";
 		resets = <&cru SRST_A_VPU>, <&cru SRST_H_VPU>;
 		reset-names = "shared_video_a", "shared_video_h";
+		rockchip,skip-pmu-idle-request;
 		iommus = <&vdpu_mmu>;
 		power-domains = <&power RK3588_PD_VDPU>;
 		rockchip,srv = <&mpp_srv>;
diff --git a/arch/arm64/configs/rockchip_defconfig b/arch/arm64/configs/rockchip_defconfig
index 8108f9adbbcd..867b4cecf809 100644
--- a/arch/arm64/configs/rockchip_defconfig
+++ b/arch/arm64/configs/rockchip_defconfig
@@ -363,6 +363,7 @@ CONFIG_STMMAC_ETH=y
 # CONFIG_NET_VENDOR_TI is not set
 # CONFIG_NET_VENDOR_VIA is not set
 # CONFIG_NET_VENDOR_WIZNET is not set
+CONFIG_MOTORCOMM_PHY=y
 CONFIG_ROCKCHIP_PHY=y
 CONFIG_PPP=y
 CONFIG_PPP_BSDCOMP=y
@@ -574,6 +575,7 @@ CONFIG_VIDEO_ROCKCHIP_ISP=y
 CONFIG_VIDEO_ROCKCHIP_ISPP=y
 CONFIG_VIDEO_ROCKCHIP_HDMIRX=y
 CONFIG_VIDEO_LT6911UXC=y
+CONFIG_VIDEO_LT6911UXE=y
 CONFIG_VIDEO_LT7911D=y
 CONFIG_VIDEO_NVP6188=y
 CONFIG_VIDEO_RK628_CSI=y
@@ -582,6 +584,8 @@ CONFIG_VIDEO_TC35874X=y
 CONFIG_VIDEO_THCV244=y
 CONFIG_VIDEO_RK_IRCUT=y
 CONFIG_VIDEO_GC0312=y
+CONFIG_VIDEO_GC2053=y
+CONFIG_VIDEO_GC2093=y
 CONFIG_VIDEO_GC2145=y
 CONFIG_VIDEO_GC2385=y
 CONFIG_VIDEO_GC4C33=y
@@ -626,7 +630,6 @@ CONFIG_DRM_PANEL_SIMPLE=y
 CONFIG_DRM_PANEL_MAXIM_DESERIALIZER=y
 CONFIG_DRM_DISPLAY_CONNECTOR=y
 CONFIG_DRM_MAXIM_MAX96745=y
-CONFIG_DRM_MAXIM_MAX96752F=y
 CONFIG_DRM_MAXIM_MAX96755F=y
 CONFIG_DRM_RK630_TVE=y
 CONFIG_DRM_RK1000_TVE=y
@@ -877,6 +880,7 @@ CONFIG_CPU_PX30=y
 CONFIG_CPU_RK3328=y
 CONFIG_CPU_RK3368=y
 CONFIG_CPU_RK3399=y
+CONFIG_CPU_RK3528=y
 CONFIG_CPU_RK3568=y
 CONFIG_CPU_RK3588=y
 CONFIG_ROCKCHIP_CPUINFO=y
diff --git a/arch/arm64/configs/rockchip_gki.config b/arch/arm64/configs/rockchip_gki.config
index e7fbedd7372b..d726d030a647 100644
--- a/arch/arm64/configs/rockchip_gki.config
+++ b/arch/arm64/configs/rockchip_gki.config
@@ -1,3 +1,4 @@
+CONFIG_PWRSEQ_SIMPLE=m
 CONFIG_AP6XXX=m
 CONFIG_ARCH_ROCKCHIP=y
 CONFIG_ARM_ROCKCHIP_BUS_DEVFREQ=m
@@ -29,6 +30,7 @@ CONFIG_COMPASS_DEVICE=m
 CONFIG_CPUFREQ_DT=m
 CONFIG_CPU_FREQ_GOV_ONDEMAND=m
 CONFIG_CPU_FREQ_GOV_USERSPACE=m
+CONFIG_CPU_RK3568=y
 CONFIG_CPU_RK3588=y
 CONFIG_CRYPTO_AES_ARM64_CE_CCM=m
 CONFIG_CRYPTO_DEV_ROCKCHIP=m
@@ -44,7 +46,6 @@ CONFIG_DRM_DISPLAY_CONNECTOR=m
 CONFIG_DRM_DW_HDMI_CEC=m
 CONFIG_DRM_DW_HDMI_I2S_AUDIO=m
 CONFIG_DRM_MAXIM_MAX96745=m
-CONFIG_DRM_MAXIM_MAX96752F=m
 CONFIG_DRM_MAXIM_MAX96755F=m
 CONFIG_DRM_PANEL_SIMPLE=m
 CONFIG_DRM_RK1000_TVE=m
diff --git a/arch/arm64/configs/rockchip_linux_defconfig b/arch/arm64/configs/rockchip_linux_defconfig
index aacc4dc45e12..2c8e31b4a2ba 100644
--- a/arch/arm64/configs/rockchip_linux_defconfig
+++ b/arch/arm64/configs/rockchip_linux_defconfig
@@ -177,6 +177,7 @@ CONFIG_STMMAC_ETH=y
 # CONFIG_NET_VENDOR_TI is not set
 # CONFIG_NET_VENDOR_VIA is not set
 # CONFIG_NET_VENDOR_WIZNET is not set
+CONFIG_MOTORCOMM_PHY=y
 CONFIG_ROCKCHIP_PHY=y
 CONFIG_USB_RTL8150=y
 CONFIG_USB_RTL8152=y
diff --git a/drivers/clk/rockchip/clk-rk3036.c b/drivers/clk/rockchip/clk-rk3036.c
index 9872eb15864e..ed05eb6c51f3 100644
--- a/drivers/clk/rockchip/clk-rk3036.c
+++ b/drivers/clk/rockchip/clk-rk3036.c
@@ -119,15 +119,17 @@ static const struct rockchip_cpuclk_reg_data rk3036_cpuclk_data = {
 
 PNAME(mux_pll_p)		= { "xin24m", "xin24m" };
 
-PNAME(mux_busclk_p)		= { "apll", "dpll_cpu", "gpll_cpu" };
+PNAME(mux_busclk_p)		= { "dummy_apll", "dpll_cpu", "gpll_cpu" };
 PNAME(mux_ddrphy_p)		= { "dpll_ddr", "gpll_ddr" };
-PNAME(mux_pll_src_3plls_p)	= { "apll", "dpll", "gpll" };
+PNAME(mux_pll_src_apll_dpll_gpll_p)	= { "apll", "dpll", "gpll" };
+PNAME(mux_pll_src_dmyapll_dpll_gpll_p)	= { "dummy_apll", "dpll", "gpll" };
+
 PNAME(mux_timer_p)		= { "xin24m", "pclk_peri_src" };
 
-PNAME(mux_pll_src_apll_dpll_gpll_usb480m_p)	= { "apll", "dpll", "gpll", "usb480m" };
+PNAME(mux_pll_src_dmyapll_dpll_gpll_usb480m_p)	= { "dummy_apll", "dpll", "gpll", "usb480m" };
 PNAME(mux_pll_src_dmyapll_dpll_gpll_xin24_p)   = { "dummy_apll", "dpll", "gpll", "xin24m" };
 
-PNAME(mux_mmc_src_p)	= { "apll", "dpll", "gpll", "xin24m" };
+PNAME(mux_mmc_src_p)	= { "dummy_apll", "dpll", "gpll", "xin24m" };
 PNAME(mux_i2s_pre_p)	= { "i2s_src", "i2s_frac", "ext_i2s", "xin12m" };
 PNAME(mux_i2s_clkout_p)	= { "i2s_pre", "xin12m" };
 PNAME(mux_spdif_p)	= { "spdif_src", "spdif_frac", "xin12m" };
@@ -212,7 +214,7 @@ static struct rockchip_clk_branch rk3036_clk_branches[] __initdata = {
 			RK2928_CLKSEL_CON(1), 8, 2, DFLAGS | CLK_DIVIDER_READ_ONLY,
 			RK2928_CLKGATE_CON(0), 4, GFLAGS),
 
-	COMPOSITE(0, "aclk_peri_src", mux_pll_src_3plls_p, CLK_IS_CRITICAL,
+	COMPOSITE(0, "aclk_peri_src", mux_pll_src_dmyapll_dpll_gpll_p, 0,
 			RK2928_CLKSEL_CON(10), 14, 2, MFLAGS, 0, 5, DFLAGS,
 			RK2928_CLKGATE_CON(2), 0, GFLAGS),
 
@@ -240,7 +242,7 @@ static struct rockchip_clk_branch rk3036_clk_branches[] __initdata = {
 			RK2928_CLKSEL_CON(2), 7, 1, MFLAGS,
 			RK2928_CLKGATE_CON(2), 5, GFLAGS),
 
-	MUX(0, "uart_pll_clk", mux_pll_src_apll_dpll_gpll_usb480m_p, 0,
+	MUX(0, "uart_pll_clk", mux_pll_src_dmyapll_dpll_gpll_usb480m_p, 0,
 			RK2928_CLKSEL_CON(13), 10, 2, MFLAGS),
 	COMPOSITE_NOMUX(0, "uart0_src", "uart_pll_clk", 0,
 			RK2928_CLKSEL_CON(13), 0, 7, DFLAGS,
@@ -264,23 +266,23 @@ static struct rockchip_clk_branch rk3036_clk_branches[] __initdata = {
 			RK2928_CLKGATE_CON(1), 13, GFLAGS,
 			&rk3036_uart2_fracmux),
 
-	COMPOSITE(0, "aclk_vcodec", mux_pll_src_3plls_p, 0,
+	COMPOSITE(ACLK_VCODEC, "aclk_vcodec", mux_pll_src_dmyapll_dpll_gpll_p, 0,
 			RK2928_CLKSEL_CON(32), 14, 2, MFLAGS, 8, 5, DFLAGS,
 			RK2928_CLKGATE_CON(3), 11, GFLAGS),
 	FACTOR_GATE(HCLK_VCODEC, "hclk_vcodec", "aclk_vcodec", 0, 1, 4,
 			RK2928_CLKGATE_CON(3), 12, GFLAGS),
 
-	COMPOSITE(ACLK_HEVC, "aclk_hevc", mux_pll_src_3plls_p, 0,
+	COMPOSITE(ACLK_HEVC, "aclk_hevc", mux_pll_src_dmyapll_dpll_gpll_p, 0,
 			RK2928_CLKSEL_CON(20), 0, 2, MFLAGS, 2, 5, DFLAGS,
 			RK2928_CLKGATE_CON(10), 6, GFLAGS),
 
-	COMPOSITE(0, "aclk_disp1_pre", mux_pll_src_3plls_p, 0,
+	COMPOSITE(0, "aclk_disp1_pre", mux_pll_src_dmyapll_dpll_gpll_p, 0,
 			RK2928_CLKSEL_CON(31), 14, 2, MFLAGS, 8, 5, DFLAGS,
 			RK2928_CLKGATE_CON(1), 4, GFLAGS),
-	COMPOSITE(0, "hclk_disp_pre", mux_pll_src_3plls_p, 0,
+	COMPOSITE(0, "hclk_disp_pre", mux_pll_src_dmyapll_dpll_gpll_p, 0,
 			RK2928_CLKSEL_CON(30), 14, 2, MFLAGS, 8, 5, DFLAGS,
 			RK2928_CLKGATE_CON(0), 11, GFLAGS),
-	COMPOSITE(SCLK_LCDC, "dclk_lcdc", mux_pll_src_3plls_p, 0,
+	COMPOSITE(SCLK_LCDC, "dclk_lcdc", mux_pll_src_apll_dpll_gpll_p, 0,
 			RK2928_CLKSEL_CON(28), 0, 2, MFLAGS, 8, 8, DFLAGS,
 			RK2928_CLKGATE_CON(3), 2, GFLAGS),
 
@@ -309,7 +311,7 @@ static struct rockchip_clk_branch rk3036_clk_branches[] __initdata = {
 	MMC(SCLK_EMMC_DRV,     "emmc_drv",     "sclk_emmc",  RK3036_EMMC_CON0,  1),
 	MMC(SCLK_EMMC_SAMPLE,  "emmc_sample",  "sclk_emmc",  RK3036_EMMC_CON1,  0),
 
-	COMPOSITE(0, "i2s_src", mux_pll_src_3plls_p, 0,
+	COMPOSITE(0, "i2s_src", mux_pll_src_dmyapll_dpll_gpll_p, 0,
 			RK2928_CLKSEL_CON(3), 14, 2, MFLAGS, 0, 7, DFLAGS,
 			RK2928_CLKGATE_CON(0), 9, GFLAGS),
 	COMPOSITE_FRACMUX(SCLK_I2S_FRAC, "i2s_frac", "i2s_src", CLK_SET_RATE_PARENT,
@@ -322,7 +324,7 @@ static struct rockchip_clk_branch rk3036_clk_branches[] __initdata = {
 	GATE(SCLK_I2S, "sclk_i2s", "i2s_pre", CLK_SET_RATE_PARENT,
 			RK2928_CLKGATE_CON(0), 14, GFLAGS),
 
-	COMPOSITE(0, "spdif_src", mux_pll_src_3plls_p, 0,
+	COMPOSITE(0, "spdif_src", mux_pll_src_dmyapll_dpll_gpll_p, 0,
 			RK2928_CLKSEL_CON(5), 10, 2, MFLAGS, 0, 7, DFLAGS,
 			RK2928_CLKGATE_CON(2), 10, GFLAGS),
 	COMPOSITE_FRACMUX(0, "spdif_frac", "spdif_src", 0,
@@ -333,15 +335,15 @@ static struct rockchip_clk_branch rk3036_clk_branches[] __initdata = {
 	GATE(SCLK_OTGPHY0, "sclk_otgphy0", "xin12m", CLK_IGNORE_UNUSED,
 			RK2928_CLKGATE_CON(1), 5, GFLAGS),
 
-	COMPOSITE(SCLK_GPU, "sclk_gpu", mux_pll_src_3plls_p, 0,
+	COMPOSITE(SCLK_GPU, "sclk_gpu", mux_pll_src_dmyapll_dpll_gpll_p, 0,
 			RK2928_CLKSEL_CON(34), 8, 2, MFLAGS, 0, 5, DFLAGS,
 			RK2928_CLKGATE_CON(3), 13, GFLAGS),
 
-	COMPOSITE(SCLK_SPI, "sclk_spi", mux_pll_src_3plls_p, 0,
+	COMPOSITE(SCLK_SPI, "sclk_spi", mux_pll_src_dmyapll_dpll_gpll_p, 0,
 			RK2928_CLKSEL_CON(25), 8, 2, MFLAGS, 0, 7, DFLAGS,
 			RK2928_CLKGATE_CON(2), 9, GFLAGS),
 
-	COMPOSITE(SCLK_NANDC, "sclk_nandc", mux_pll_src_3plls_p, 0,
+	COMPOSITE(SCLK_NANDC, "sclk_nandc", mux_pll_src_dmyapll_dpll_gpll_p, 0,
 			RK2928_CLKSEL_CON(16), 8, 2, MFLAGS, 10, 5, DFLAGS,
 			RK2928_CLKGATE_CON(10), 4, GFLAGS),
 
@@ -349,7 +351,7 @@ static struct rockchip_clk_branch rk3036_clk_branches[] __initdata = {
 			RK2928_CLKSEL_CON(16), 0, 2, MFLAGS, 2, 5, DFLAGS,
 			RK2928_CLKGATE_CON(10), 5, GFLAGS),
 
-	COMPOSITE_NOGATE(SCLK_MACPLL, "mac_pll_src", mux_pll_src_3plls_p, CLK_SET_RATE_NO_REPARENT,
+	COMPOSITE_NOGATE(SCLK_MACPLL, "mac_pll_src", mux_pll_src_apll_dpll_gpll_p, CLK_SET_RATE_NO_REPARENT,
 			RK2928_CLKSEL_CON(21), 0, 2, MFLAGS, 9, 5, DFLAGS),
 	MUX(SCLK_MACREF, "mac_clk_ref", mux_mac_p, CLK_SET_RATE_PARENT,
 			RK2928_CLKSEL_CON(21), 3, 1, MFLAGS),
diff --git a/drivers/clk/rockchip/clk-rk3128.c b/drivers/clk/rockchip/clk-rk3128.c
index 2bcbfe0a9795..34b3695ef582 100644
--- a/drivers/clk/rockchip/clk-rk3128.c
+++ b/drivers/clk/rockchip/clk-rk3128.c
@@ -212,9 +212,9 @@ static struct rockchip_clk_branch common_clk_branches[] __initdata = {
 			RK2928_CLKGATE_CON(0), 2, GFLAGS),
 	GATE(0, "gpll_div2_ddr", "gpll_div2", CLK_IGNORE_UNUSED,
 			RK2928_CLKGATE_CON(0), 2, GFLAGS),
-	COMPOSITE_NOGATE(0, "ddrphy2x", mux_ddrphy_p, CLK_IGNORE_UNUSED,
-			RK2928_CLKSEL_CON(26), 8, 2, MFLAGS, 0, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO),
-	FACTOR(SCLK_DDRC, "clk_ddrc", "ddrphy2x", 0, 1, 2),
+	COMPOSITE_DDRCLK(SCLK_DDRC, "clk_ddrc", mux_ddrphy_p, 0,
+			RK2928_CLKSEL_CON(26), 8, 2, 0, 2,
+			ROCKCHIP_DDRCLK_SIP_V2),
 	FACTOR(0, "clk_ddrphy", "ddrphy2x", 0, 1, 2),
 
 	/* PD_CORE */
diff --git a/drivers/clk/rockchip/clk-rk3288.c b/drivers/clk/rockchip/clk-rk3288.c
index 01838b61659d..f9c4678fcd73 100644
--- a/drivers/clk/rockchip/clk-rk3288.c
+++ b/drivers/clk/rockchip/clk-rk3288.c
@@ -339,7 +339,7 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
 			RK3288_CLKGATE_CON(0), 9, GFLAGS),
 	COMPOSITE_DDRCLK(SCLK_DDRCLK, "sclk_ddrc", mux_ddrphy_p, 0,
 			 RK3288_CLKSEL_CON(26), 2, 1, 0, 0,
-			 ROCKCHIP_DDRCLK_SIP),
+			 ROCKCHIP_DDRCLK_SIP_V2),
 	COMPOSITE_NOGATE(0, "ddrphy", mux_ddrphy_p, CLK_IGNORE_UNUSED,
 			RK3288_CLKSEL_CON(26), 2, 1, MFLAGS, 0, 2,
 					DFLAGS | CLK_DIVIDER_POWER_OF_TWO),
@@ -724,7 +724,7 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
 	/* aclk_peri gates */
 	GATE(0, "aclk_peri_axi_matrix", "aclk_peri", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(6), 2, GFLAGS),
 	GATE(ACLK_DMAC2, "aclk_dmac2", "aclk_peri", 0, RK3288_CLKGATE_CON(6), 3, GFLAGS),
-	GATE(0, "aclk_peri_niu", "aclk_peri", 0, RK3288_CLKGATE_CON(7), 11, GFLAGS),
+	GATE(0, "aclk_peri_niu", "aclk_peri", CLK_IS_CRITICAL, RK3288_CLKGATE_CON(7), 11, GFLAGS),
 	GATE(ACLK_MMU, "aclk_mmu", "aclk_peri", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(8), 12, GFLAGS),
 	GATE(ACLK_GMAC, "aclk_gmac", "aclk_peri", 0, RK3288_CLKGATE_CON(8), 0, GFLAGS),
 	GATE(HCLK_GPS, "hclk_gps", "aclk_peri", 0, RK3288_CLKGATE_CON(8), 2, GFLAGS),
diff --git a/drivers/clk/rockchip/clk-rk3568.c b/drivers/clk/rockchip/clk-rk3568.c
index 66076d68bb39..fa4dd1e39205 100644
--- a/drivers/clk/rockchip/clk-rk3568.c
+++ b/drivers/clk/rockchip/clk-rk3568.c
@@ -1699,6 +1699,7 @@ static void __init rk3568_clk_init(struct device_node *np)
 
 CLK_OF_DECLARE(rk3568_cru, "rockchip,rk3568-cru", rk3568_clk_init);
 
+#ifdef MODULE
 struct clk_rk3568_inits {
 	void (*inits)(struct device_node *np);
 };
@@ -1723,7 +1724,7 @@ static const struct of_device_id clk_rk3568_match_table[] = {
 };
 MODULE_DEVICE_TABLE(of, clk_rk3568_match_table);
 
-static int __init clk_rk3568_probe(struct platform_device *pdev)
+static int clk_rk3568_probe(struct platform_device *pdev)
 {
 	struct device_node *np = pdev->dev.of_node;
 	const struct of_device_id *match;
@@ -1741,14 +1742,16 @@ static int __init clk_rk3568_probe(struct platform_device *pdev)
 }
 
 static struct platform_driver clk_rk3568_driver = {
+	.probe		= clk_rk3568_probe,
 	.driver		= {
 		.name	= "clk-rk3568",
 		.of_match_table = clk_rk3568_match_table,
 		.suppress_bind_attrs = true,
 	},
 };
-builtin_platform_driver_probe(clk_rk3568_driver, clk_rk3568_probe);
+module_platform_driver(clk_rk3568_driver);
 
 MODULE_DESCRIPTION("Rockchip RK3568 Clock Driver");
 MODULE_LICENSE("GPL");
 MODULE_ALIAS("platform:clk-rk3568");
+#endif /* MODULE */
diff --git a/drivers/clk/rockchip/clk-rk3588.c b/drivers/clk/rockchip/clk-rk3588.c
index a7b25c1d309b..1331452fbd46 100644
--- a/drivers/clk/rockchip/clk-rk3588.c
+++ b/drivers/clk/rockchip/clk-rk3588.c
@@ -2456,6 +2456,7 @@ static void __init rk3588_clk_init(struct device_node *np)
 
 CLK_OF_DECLARE(rk3588_cru, "rockchip,rk3588-cru", rk3588_clk_init);
 
+#ifdef MODULE
 struct clk_rk3588_inits {
 	void (*inits)(struct device_node *np);
 };
@@ -2473,7 +2474,7 @@ static const struct of_device_id clk_rk3588_match_table[] = {
 };
 MODULE_DEVICE_TABLE(of, clk_rk3588_match_table);
 
-static int __init clk_rk3588_probe(struct platform_device *pdev)
+static int clk_rk3588_probe(struct platform_device *pdev)
 {
 	struct device_node *np = pdev->dev.of_node;
 	const struct of_device_id *match;
@@ -2491,13 +2492,15 @@ static int __init clk_rk3588_probe(struct platform_device *pdev)
 }
 
 static struct platform_driver clk_rk3588_driver = {
+	.probe		= clk_rk3588_probe,
 	.driver		= {
 		.name	= "clk-rk3588",
 		.of_match_table = clk_rk3588_match_table,
 		.suppress_bind_attrs = true,
 	},
 };
-builtin_platform_driver_probe(clk_rk3588_driver, clk_rk3588_probe);
+module_platform_driver(clk_rk3588_driver);
 
 MODULE_DESCRIPTION("Rockchip RK3588 Clock Driver");
 MODULE_LICENSE("GPL");
+#endif /* MODULE */
diff --git a/drivers/clk/rockchip/clk.c b/drivers/clk/rockchip/clk.c
index 2e41b346ea31..09762ce82d67 100644
--- a/drivers/clk/rockchip/clk.c
+++ b/drivers/clk/rockchip/clk.c
@@ -154,6 +154,9 @@ static int rockchip_clk_frac_notifier_cb(struct notifier_block *nb,
 			frac->mux_ops->set_parent(&frac_mux->hw,
 						  frac->mux_frac_idx);
 			frac->rate_change_remuxed = 1;
+			clk_hw_set_parent(&frac_mux->hw,
+					  clk_hw_get_parent_by_index(&frac_mux->hw,
+								     frac->mux_frac_idx));
 		}
 	} else if (event == POST_RATE_CHANGE) {
 		/*
@@ -165,6 +168,9 @@ static int rockchip_clk_frac_notifier_cb(struct notifier_block *nb,
 		if (frac->rate_change_remuxed) {
 			frac->mux_ops->set_parent(&frac_mux->hw,
 						  frac->rate_change_idx);
+			clk_hw_set_parent(&frac_mux->hw,
+					  clk_hw_get_parent_by_index(&frac_mux->hw,
+								     frac->rate_change_idx));
 			frac->rate_change_remuxed = 0;
 		}
 	}
diff --git a/drivers/cpufreq/Kconfig b/drivers/cpufreq/Kconfig
index 434e3d0371ea..6f2b6c17c948 100644
--- a/drivers/cpufreq/Kconfig
+++ b/drivers/cpufreq/Kconfig
@@ -247,7 +247,7 @@ comment "CPU frequency scaling drivers"
 config CPUFREQ_DT
 	tristate "Generic DT based cpufreq driver"
 	depends on HAVE_CLK && OF
-	select CPUFREQ_DT_PLATDEV
+	select CPUFREQ_DT_PLATDEV if !ARM_ROCKCHIP_CPUFREQ
 	select PM_OPP
 	help
 	  This adds a generic DT based cpufreq driver for frequency management.
diff --git a/drivers/cpufreq/rockchip-cpufreq.c b/drivers/cpufreq/rockchip-cpufreq.c
index 699f53e15ece..179999a37b8c 100644
--- a/drivers/cpufreq/rockchip-cpufreq.c
+++ b/drivers/cpufreq/rockchip-cpufreq.c
@@ -206,6 +206,9 @@ static int rk3588_get_soc_info(struct device *dev, struct device_node *np,
 		/* RK3588M */
 		if (value == 0xd)
 			*bin = 1;
+		/* RK3588J */
+		else if (value == 0xa)
+			*bin = 2;
 	}
 	if (*bin < 0)
 		*bin = 0;
@@ -213,6 +216,7 @@ static int rk3588_get_soc_info(struct device *dev, struct device_node *np,
 
 	return ret;
 }
+
 static int rk3588_change_length(struct device *dev, struct device_node *np,
 				int bin, int process, int volt_sel)
 {
diff --git a/drivers/devfreq/event/rockchip-dfi.c b/drivers/devfreq/event/rockchip-dfi.c
index 80bdfea5bb7b..0708535bda18 100644
--- a/drivers/devfreq/event/rockchip-dfi.c
+++ b/drivers/devfreq/event/rockchip-dfi.c
@@ -537,7 +537,10 @@ static __maybe_unused __init int rk3588_dfi_init(struct platform_device *pdev,
 		data->dram_type = READ_DRAMTYPE_INFO(val_2);
 
 	data->mon_idx = 0x4000;
-	data->count_rate = 2;
+	if (data->dram_type == LPDDR5)
+		data->count_rate = 1;
+	else
+		data->count_rate = 2;
 	data->dram_dynamic_info_reg = RK3588_PMUGRF_OS_REG(6);
 	data->ch_msk = READ_CH_INFO(val_2) | READ_CH_INFO(val_4) << 2;
 	data->clk = NULL;
diff --git a/drivers/devfreq/rockchip_bus.c b/drivers/devfreq/rockchip_bus.c
index 7032b4815c5a..6dd20a6e2b0e 100644
--- a/drivers/devfreq/rockchip_bus.c
+++ b/drivers/devfreq/rockchip_bus.c
@@ -73,7 +73,9 @@ static int rockchip_bus_smc_config(struct rockchip_bus *bus)
 	struct device_node *np = dev->of_node;
 	struct device_node *child;
 	unsigned int enable_msk, bus_id, cfg;
-	int ret;
+	char *prp_name = "rockchip,soc-bus-table";
+	u32 *table = NULL;
+	int ret = 0, config_cnt, i;
 
 	for_each_available_child_of_node(np, child) {
 		ret = of_property_read_u32_index(child, "bus-id", 0,
@@ -108,7 +110,49 @@ static int rockchip_bus_smc_config(struct rockchip_bus *bus)
 		}
 	}
 
-	return 0;
+	config_cnt = of_property_count_u32_elems(np, prp_name);
+	if (config_cnt <= 0) {
+		return 0;
+	} else if (config_cnt % 3) {
+		dev_err(dev, "Invalid count of %s\n", prp_name);
+		return -EINVAL;
+	}
+
+	table = kmalloc_array(config_cnt, sizeof(u32), GFP_KERNEL);
+	if (!table)
+		return -ENOMEM;
+
+	ret = of_property_read_u32_array(np, prp_name, table, config_cnt);
+	if (ret) {
+		dev_err(dev, "get %s error\n", prp_name);
+		goto free_table;
+	}
+
+	/* table[3n]: bus_id
+	 * table[3n + 1]: config
+	 * table[3n + 2]: enable_mask
+	 */
+	for (i = 0; i < config_cnt; i += 3) {
+		bus_id = table[i];
+		cfg = table[i + 1];
+		enable_msk = table[i + 2];
+
+		if (!cfg) {
+			dev_info(dev, "cfg-val invalid in %s-%d\n", prp_name, bus_id);
+			continue;
+		}
+
+		ret = rockchip_sip_bus_smc_config(bus_id, cfg, enable_msk);
+		if (ret) {
+			dev_err(dev, "bus smc config error: %x!\n", ret);
+			goto free_table;
+		}
+	}
+
+free_table:
+	kfree(table);
+
+	return ret;
 }
 
 static int rockchip_bus_set_freq_table(struct rockchip_bus *bus)
@@ -448,6 +492,7 @@ static const struct of_device_id rockchip_busfreq_of_match[] = {
 	{ .compatible = "rockchip,rk3368-bus", },
 	{ .compatible = "rockchip,rk3399-bus", },
 	{ .compatible = "rockchip,rk3568-bus", },
+	{ .compatible = "rockchip,rk3588-bus", },
 	{ .compatible = "rockchip,rv1126-bus", },
 	{ },
 };
diff --git a/drivers/devfreq/rockchip_dmc.c b/drivers/devfreq/rockchip_dmc.c
index 0b3625010747..f2579aff9781 100644
--- a/drivers/devfreq/rockchip_dmc.c
+++ b/drivers/devfreq/rockchip_dmc.c
@@ -136,6 +136,7 @@ struct rockchip_dmcfreq {
 	unsigned long video_1080p_rate;
 	unsigned long video_4k_rate;
 	unsigned long video_4k_10b_rate;
+	unsigned long video_4k_60p_rate;
 	unsigned long video_svep_rate;
 	unsigned long performance_rate;
 	unsigned long hdmi_rate;
@@ -2461,6 +2462,11 @@ static int rockchip_get_system_status_level(struct device_node *np,
 			dev_info(dmcfreq->dev, "video_4k_10b_rate = %ld\n",
 				 dmcfreq->video_4k_10b_rate);
 			break;
+		case SYS_STATUS_VIDEO_4K_60P:
+			dmcfreq->video_4k_60p_rate = rockchip_freq_level_2_rate(dmcfreq, level);
+			dev_info(dmcfreq->dev, "video_4k_60p_rate = %ld\n",
+				 dmcfreq->video_4k_60p_rate);
+			break;
 		case SYS_STATUS_VIDEO_SVEP:
 			dmcfreq->video_svep_rate = rockchip_freq_level_2_rate(dmcfreq, level);
 			dev_info(dmcfreq->dev, "video_svep_rate = %ld\n",
@@ -2584,6 +2590,11 @@ static int rockchip_dmcfreq_system_status_notifier(struct notifier_block *nb,
 			target_rate = dmcfreq->video_4k_10b_rate;
 	}
 
+	if (dmcfreq->video_4k_60p_rate && (status & SYS_STATUS_VIDEO_4K_60P)) {
+		if (dmcfreq->video_4k_60p_rate > target_rate)
+			target_rate = dmcfreq->video_4k_60p_rate;
+	}
+
 	if (dmcfreq->video_1080p_rate && (status & SYS_STATUS_VIDEO_1080P)) {
 		if (dmcfreq->video_1080p_rate > target_rate)
 			target_rate = dmcfreq->video_1080p_rate;
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index 88edf9d46b37..20bff29c27ff 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -1250,13 +1250,6 @@ config GPIO_MAX77650
 	  GPIO driver for MAX77650/77651 PMIC from Maxim Semiconductor.
 	  These chips have a single pin that can be configured as GPIO.
 
-config GPIO_MAX96752F
-	tristate "MAX96752F GPIO"
-	depends on MFD_MAX96752F
-	help
-	  Select this option to enable GPIO driver for the MAX96752F
-	  chip.
-
 config GPIO_MSIC
 	bool "Intel MSIC mixed signal gpio support"
 	depends on (X86 || COMPILE_TEST) && MFD_INTEL_MSIC
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index 87c2046799cf..0a905ed33d0e 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -89,7 +89,6 @@ obj-$(CONFIG_GPIO_MAX730X)		+= gpio-max730x.o
 obj-$(CONFIG_GPIO_MAX732X)		+= gpio-max732x.o
 obj-$(CONFIG_GPIO_MAX77620)		+= gpio-max77620.o
 obj-$(CONFIG_GPIO_MAX77650)		+= gpio-max77650.o
-obj-$(CONFIG_GPIO_MAX96752F)		+= gpio-max96752f.o
 obj-$(CONFIG_GPIO_MB86S7X)		+= gpio-mb86s7x.o
 obj-$(CONFIG_GPIO_MC33880)		+= gpio-mc33880.o
 obj-$(CONFIG_GPIO_MC9S08DZ60)		+= gpio-mc9s08dz60.o
diff --git a/drivers/gpio/gpio-max96752f.c b/drivers/gpio/gpio-max96752f.c
deleted file mode 100644
index 1c3816737c55..000000000000
--- a/drivers/gpio/gpio-max96752f.c
+++ /dev/null
@@ -1,104 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Maxim MAX96752F GPIO driver
- *
- * Copyright (C) 2022 Rockchip Electronics Co. Ltd.
- */
-
-#include <linux/gpio/driver.h>
-#include <linux/module.h>
-#include <linux/platform_device.h>
-#include <linux/regmap.h>
-#include <linux/mfd/max96752f.h>
-
-struct max96752f_gpio {
-	struct device *dev;
-	struct regmap *regmap;
-	struct gpio_chip gpio_chip;
-};
-
-static int max96752f_gpio_direction_output(struct gpio_chip *gc,
-					   unsigned int offset, int value)
-{
-	struct max96752f_gpio *gpio = gpiochip_get_data(gc);
-
-	regmap_update_bits(gpio->regmap, GPIO_A_REG(offset),
-			   GPIO_OUT_DIS | GPIO_OUT,
-			   FIELD_PREP(GPIO_OUT_DIS, 0) |
-			   FIELD_PREP(GPIO_OUT, value));
-
-	return 0;
-}
-
-static void max96752f_gpio_set(struct gpio_chip *gc, unsigned int offset,
-			       int value)
-{
-	struct max96752f_gpio *gpio = gpiochip_get_data(gc);
-
-	regmap_update_bits(gpio->regmap, GPIO_A_REG(offset), GPIO_OUT,
-			   FIELD_PREP(GPIO_OUT, value));
-}
-
-static int max96752f_gpio_get(struct gpio_chip *gc, unsigned int offset)
-{
-	struct max96752f_gpio *gpio = gpiochip_get_data(gc);
-	unsigned int value;
-
-	regmap_read(gpio->regmap, GPIO_A_REG(offset), &value);
-
-	return !!FIELD_GET(GPIO_OUT, value);
-}
-
-static int max96752f_gpio_probe(struct platform_device *pdev)
-{
-	struct device *dev = &pdev->dev;
-	struct max96752f_gpio *gpio;
-	int ret;
-
-	gpio = devm_kzalloc(dev, sizeof(*gpio), GFP_KERNEL);
-	if (!gpio)
-		return -ENOMEM;
-
-	gpio->dev = dev;
-	platform_set_drvdata(pdev, gpio);
-
-	gpio->regmap = dev_get_regmap(dev->parent, NULL);
-	if (!gpio->regmap)
-		return dev_err_probe(dev, -ENODEV, "failed to get regmap\n");
-
-	gpio->gpio_chip.of_node = dev->of_node;
-	gpio->gpio_chip.label = dev_name(dev);
-	gpio->gpio_chip.parent = dev->parent;
-	gpio->gpio_chip.direction_output = max96752f_gpio_direction_output;
-	gpio->gpio_chip.set = max96752f_gpio_set;
-	gpio->gpio_chip.get = max96752f_gpio_get;
-	gpio->gpio_chip.ngpio = 16;
-	gpio->gpio_chip.can_sleep = true;
-	gpio->gpio_chip.base = -1;
-
-	ret = devm_gpiochip_add_data(dev, &gpio->gpio_chip, gpio);
-	if (ret)
-		return dev_err_probe(dev, ret, "failed to add gpio chip\n");
-
-	return 0;
-}
-
-static const struct of_device_id max96752f_gpio_of_match[] = {
-	{ .name = "maxim,max96752f-gpio", },
-	{}
-};
-MODULE_DEVICE_TABLE(of, max96752f_gpio_of_match);
-
-static struct platform_driver max96752f_gpio_driver = {
-	.driver = {
-		.name	= "max96752f-gpio",
-		.of_match_table = max96752f_gpio_of_match,
-	},
-	.probe = max96752f_gpio_probe,
-};
-
-module_platform_driver(max96752f_gpio_driver);
-
-MODULE_AUTHOR("Wyon Bi <bivvy.bi@rock-chips.com>");
-MODULE_DESCRIPTION("Maxim MAX96752F GPIO driver");
-MODULE_LICENSE("GPL");
diff --git a/drivers/gpu/arm/bifrost/platform/rk/mali_kbase_config_rk.c b/drivers/gpu/arm/bifrost/platform/rk/mali_kbase_config_rk.c
index 4452c3f3ed0f..495bcc36b1df 100755
--- a/drivers/gpu/arm/bifrost/platform/rk/mali_kbase_config_rk.c
+++ b/drivers/gpu/arm/bifrost/platform/rk/mali_kbase_config_rk.c
@@ -506,6 +506,66 @@ static void kbase_platform_rk_remove_sysfs_files(struct device *dev)
 	device_remove_file(dev, &dev_attr_utilisation);
 }
 
+static int rk3588_gpu_get_soc_info(struct device *dev, struct device_node *np,
+			       int *bin, int *process)
+{
+	int ret = 0;
+	u8 value = 0;
+
+	if (!bin)
+		return 0;
+
+	if (of_property_match_string(np, "nvmem-cell-names",
+				     "specification_serial_number") >= 0) {
+		ret = rockchip_nvmem_cell_read_u8(np,
+						  "specification_serial_number",
+						  &value);
+		if (ret) {
+			dev_err(dev,
+				"Failed to get specification_serial_number\n");
+			return ret;
+		}
+		/* RK3588M */
+		if (value == 0xd)
+			*bin = 1;
+		/* RK3588J */
+		else if (value == 0xa)
+			*bin = 2;
+	}
+	if (*bin < 0)
+		*bin = 0;
+	dev_info(dev, "bin=%d\n", *bin);
+
+	return ret;
+}
+
+static int rk3588_gpu_set_soc_info(struct device *dev, struct device_node *np,
+			       int bin, int process, int volt_sel)
+{
+	struct opp_table *opp_table;
+	u32 supported_hw[2];
+
+	if (volt_sel < 0)
+		return 0;
+	if (bin < 0)
+		bin = 0;
+
+	if (!of_property_read_bool(np, "rockchip,supported-hw"))
+		return 0;
+
+	/* SoC Version */
+	supported_hw[0] = BIT(bin);
+	/* Speed Grade */
+	supported_hw[1] = BIT(volt_sel);
+	opp_table = dev_pm_opp_set_supported_hw(dev, supported_hw, 2);
+	if (IS_ERR(opp_table)) {
+		dev_err(dev, "failed to set supported opp\n");
+		return PTR_ERR(opp_table);
+	}
+
+	return 0;
+}
+
 static int rk3588_gpu_set_read_margin(struct device *dev,
 				      struct rockchip_opp_info *opp_info,
 				      u32 rm)
@@ -542,6 +602,8 @@ static int rk3588_gpu_set_read_margin(struct device *dev,
 }
 
 static const struct rockchip_opp_data rk3588_gpu_opp_data = {
+	.get_soc_info = rk3588_gpu_get_soc_info,
+	.set_soc_info = rk3588_gpu_set_soc_info,
 	.set_read_margin = rk3588_gpu_set_read_margin,
 };
 
diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig
index 736dfc12e321..3748bff9ba83 100644
--- a/drivers/gpu/drm/bridge/Kconfig
+++ b/drivers/gpu/drm/bridge/Kconfig
@@ -93,17 +93,6 @@ config DRM_MAXIM_MAX96745
 	help
 	  Driver for Maxim MAX96745 GMSL2 Serializer with eDP1.4a/DP1.4 Input.
 
-config DRM_MAXIM_MAX96752F
-	tristate "Maxim max96752F GMSL2 Deserializer"
-	depends on OF
-	select MFD_MAX96752F
-	select PINCTRL_MAX96752F
-	select GPIO_MAX96752F
-	select DRM_KMS_HELPER
-	select DRM_PANEL
-	help
-	  Driver for Maxim MAX96752F GMSL2 Deserializer with Dual LVDS Output.
-
 config DRM_MAXIM_MAX96755F
 	tristate "Maxim max96755 GMSL2 Serializer"
 	depends on OF
@@ -114,15 +103,6 @@ config DRM_MAXIM_MAX96755F
 	help
 	  Driver for Maxim MAX96755F GMSL2 Serializer with MIPI-DSI Input.
 
-config DRM_MAXIM_MAX96776
-	tristate "Maxim max96776 GMSL2 Deserializer"
-	depends on OF
-	select MFD_MAX96776
-	select DRM_KMS_HELPER
-	select DRM_PANEL
-	help
-	  Driver for Maxim MAX96776 GMSL2 Deserializer with eDP Output.
-
 config DRM_MEGACHIPS_STDPXXXX_GE_B850V3_FW
 	tristate "MegaChips stdp4028-ge-b850v3-fw and stdp2690-ge-b850v3-fw"
 	depends on OF
diff --git a/drivers/gpu/drm/bridge/Makefile b/drivers/gpu/drm/bridge/Makefile
index bf384678fc6d..834d4d3b812e 100644
--- a/drivers/gpu/drm/bridge/Makefile
+++ b/drivers/gpu/drm/bridge/Makefile
@@ -6,9 +6,7 @@ obj-$(CONFIG_DRM_ITE_IT6161) += ite-it6161.o
 obj-$(CONFIG_DRM_LONTIUM_LT9611) += lontium-lt9611.o
 obj-$(CONFIG_DRM_LVDS_CODEC) += lvds-codec.o
 obj-$(CONFIG_DRM_MAXIM_MAX96745) += maxim-max96745.o
-obj-$(CONFIG_DRM_MAXIM_MAX96752F) += maxim-max96752f.o
 obj-$(CONFIG_DRM_MAXIM_MAX96755F) += maxim-max96755f.o
-obj-$(CONFIG_DRM_MAXIM_MAX96776) += maxim-max96776.o
 obj-$(CONFIG_DRM_MEGACHIPS_STDPXXXX_GE_B850V3_FW) += megachips-stdpxxxx-ge-b850v3-fw.o
 obj-$(CONFIG_DRM_NXP_PTN3460) += nxp-ptn3460.o
 obj-$(CONFIG_DRM_PARADE_PS8622) += parade-ps8622.o
@@ -31,6 +29,7 @@ obj-$(CONFIG_DRM_TI_SN65DSI86) += ti-sn65dsi86.o
 obj-$(CONFIG_DRM_TI_TFP410) += ti-tfp410.o
 obj-$(CONFIG_DRM_TI_TPD12S015) += ti-tpd12s015.o
 obj-$(CONFIG_DRM_NWL_MIPI_DSI) += nwl-dsi.o
+
 obj-y += analogix/
 obj-y += cadence/
 obj-y += synopsys/
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
index bf41d8244fb4..fa0fb7bb3458 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
@@ -56,8 +56,16 @@ static bool analogix_dp_bandwidth_ok(struct analogix_dp_device *dp,
 				     const struct drm_display_mode *mode,
 				     unsigned int rate, unsigned int lanes)
 {
+	const struct drm_display_info *info;
 	u32 max_bw, req_bw, bpp = 24;
 
+	if (dp->plat_data->skip_connector)
+		return true;
+
+	info = &dp->connector.display_info;
+	if (info->bpc)
+		bpp = 3 * info->bpc;
+
 	req_bw = mode->clock * bpp / 8;
 	max_bw = lanes * rate;
 	if (req_bw > max_bw)
diff --git a/drivers/gpu/drm/bridge/maxim-max96752f.c b/drivers/gpu/drm/bridge/maxim-max96752f.c
deleted file mode 100644
index c0980c03daaf..000000000000
--- a/drivers/gpu/drm/bridge/maxim-max96752f.c
+++ /dev/null
@@ -1,251 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Maxim MAX96752F GMSL2 Deserializer with Dual LVDS (OLDI) Output
- *
- * Copyright (c) 2022 Rockchip Electronics Co. Ltd.
- */
-
-#include <drm/drm_atomic_helper.h>
-#include <drm/drm_bridge.h>
-#include <drm/drm_connector.h>
-#include <drm/drm_of.h>
-#include <drm/drm_probe_helper.h>
-#include <drm/drm_print.h>
-#include <drm/drm_panel.h>
-
-#include <linux/platform_device.h>
-#include <linux/kernel.h>
-#include <linux/delay.h>
-#include <linux/module.h>
-#include <linux/of.h>
-#include <linux/regmap.h>
-#include <linux/mfd/max96752f.h>
-
-struct max96752f_bridge {
-	struct drm_bridge bridge;
-	struct drm_bridge *next_bridge;
-	struct drm_panel *panel;
-
-	struct device *dev;
-	struct max96752f *parent;
-	struct regmap *regmap;
-};
-
-#define to_max96752f_bridge(x)	container_of(x, struct max96752f_bridge, x)
-
-static int max96752f_bridge_get_modes(struct drm_bridge *bridge,
-				      struct drm_connector *connector)
-{
-	struct max96752f_bridge *des = to_max96752f_bridge(bridge);
-
-	if (des->next_bridge)
-		return drm_bridge_get_modes(des->next_bridge, connector);
-
-	return drm_panel_get_modes(des->panel, connector);
-}
-
-static void
-max96752f_bridge_atomic_pre_enable(struct drm_bridge *bridge,
-				   struct drm_bridge_state *old_bridge_state)
-{
-	struct max96752f_bridge *des = to_max96752f_bridge(bridge);
-	struct drm_atomic_state *state = old_bridge_state->base.state;
-	const struct drm_bridge_state *bridge_state;
-	bool oldi_format;
-
-	max96752f_init(des->parent);
-
-	bridge_state = drm_atomic_get_new_bridge_state(state, bridge);
-	switch (bridge_state->output_bus_cfg.format) {
-	case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA:
-	case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG:
-		oldi_format = 0x0;
-		break;
-	case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG:
-		oldi_format = 0x1;
-		break;
-	default:
-		oldi_format = 0x1;
-		dev_warn(des->dev,
-			 "unsupported LVDS bus format 0x%04x, using VESA\n",
-			 bridge_state->output_bus_cfg.format);
-		break;
-	}
-
-	regmap_update_bits(des->regmap, OLDI_REG(1), OLDI_FORMAT,
-			   FIELD_PREP(OLDI_FORMAT, oldi_format));
-
-	if (des->panel)
-		drm_panel_prepare(des->panel);
-}
-
-static void
-max96752f_bridge_atomic_enable(struct drm_bridge *bridge,
-			       struct drm_bridge_state *old_bridge_state)
-{
-	struct max96752f_bridge *des = to_max96752f_bridge(bridge);
-
-	regmap_update_bits(des->regmap, 0x0002, VID_EN,
-			   FIELD_PREP(VID_EN, 1));
-
-	if (des->panel)
-		drm_panel_enable(des->panel);
-}
-
-static void
-max96752f_bridge_atomic_disable(struct drm_bridge *bridge,
-				struct drm_bridge_state *old_bridge_state)
-{
-	struct max96752f_bridge *des = to_max96752f_bridge(bridge);
-
-	if (des->panel)
-		drm_panel_disable(des->panel);
-
-	regmap_update_bits(des->regmap, 0x0002, VID_EN,
-			   FIELD_PREP(VID_EN, 0));
-}
-
-static void
-max96752f_bridge_atomic_post_disable(struct drm_bridge *bridge,
-				     struct drm_bridge_state *old_bridge_state)
-{
-	struct max96752f_bridge *des = to_max96752f_bridge(bridge);
-
-	if (des->panel)
-		drm_panel_unprepare(des->panel);
-}
-
-static u32 *
-max96752f_bridge_atomic_get_output_bus_fmts(struct drm_bridge *bridge,
-					    struct drm_bridge_state *bridge_state,
-					    struct drm_crtc_state *crtc_state,
-					    struct drm_connector_state *conn_state,
-					    unsigned int *num_output_fmts)
-{
-	struct drm_connector *connector = conn_state->connector;
-	u32 *out_bus_fmts;
-
-	out_bus_fmts = kzalloc(sizeof(*out_bus_fmts), GFP_KERNEL);
-	if (!out_bus_fmts) {
-		*num_output_fmts = 0;
-		return NULL;
-	}
-
-	*num_output_fmts = 1;
-
-	if (connector->display_info.num_bus_formats && connector->display_info.bus_formats)
-		out_bus_fmts[0] = connector->display_info.bus_formats[0];
-	else
-		out_bus_fmts[0] = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG;
-
-	return out_bus_fmts;
-}
-
-static bool max96752f_bridge_video_locked(struct max96752f_bridge *des)
-{
-	u32 val;
-
-	if (regmap_read(des->regmap, 0x0003, &val))
-		return false;
-
-	if (!FIELD_GET(VIDEO_LOCK, val))
-		return false;
-
-	return true;
-}
-
-static int max96752f_bridge_attach(struct drm_bridge *bridge,
-				   enum drm_bridge_attach_flags flags)
-{
-	struct max96752f_bridge *des = to_max96752f_bridge(bridge);
-	int ret;
-
-	ret = drm_of_find_panel_or_bridge(bridge->of_node, 1, -1, &des->panel,
-					  &des->next_bridge);
-	if (ret)
-		return ret;
-
-	if (max96752f_bridge_video_locked(des)) {
-		if (des->panel) {
-			drm_panel_prepare(des->panel);
-			drm_panel_enable(des->panel);
-		}
-	}
-
-	if (des->next_bridge)
-		return drm_bridge_attach(bridge->encoder, des->next_bridge,
-					 bridge, 0);
-
-	return 0;
-}
-
-static const struct drm_bridge_funcs max96752f_bridge_funcs = {
-	.attach = max96752f_bridge_attach,
-	.get_modes = max96752f_bridge_get_modes,
-	.atomic_pre_enable = max96752f_bridge_atomic_pre_enable,
-	.atomic_post_disable = max96752f_bridge_atomic_post_disable,
-	.atomic_enable = max96752f_bridge_atomic_enable,
-	.atomic_disable = max96752f_bridge_atomic_disable,
-	.atomic_get_input_bus_fmts = drm_atomic_helper_bridge_propagate_bus_fmt,
-	.atomic_get_output_bus_fmts = max96752f_bridge_atomic_get_output_bus_fmts,
-	.atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
-	.atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
-	.atomic_reset = drm_atomic_helper_bridge_reset,
-};
-
-static int max96752f_bridge_probe(struct platform_device *pdev)
-{
-	struct device *dev = &pdev->dev;
-	struct max96752f_bridge *des;
-
-	des = devm_kzalloc(dev, sizeof(*des), GFP_KERNEL);
-	if (!des)
-		return -ENOMEM;
-
-	des->dev = dev;
-	des->parent = dev_get_drvdata(dev->parent);
-	platform_set_drvdata(pdev, des);
-
-	des->regmap = dev_get_regmap(dev->parent, NULL);
-	if (!des->regmap)
-		return dev_err_probe(dev, -ENODEV, "failed to get regmap\n");
-
-	des->bridge.funcs = &max96752f_bridge_funcs;
-	des->bridge.of_node = dev->of_node;
-	des->bridge.ops = DRM_BRIDGE_OP_MODES;
-	des->bridge.type = DRM_MODE_CONNECTOR_LVDS;
-
-	drm_bridge_add(&des->bridge);
-
-	return 0;
-}
-
-static int max96752f_bridge_remove(struct platform_device *pdev)
-{
-	struct max96752f_bridge *des = platform_get_drvdata(pdev);
-
-	drm_bridge_remove(&des->bridge);
-
-	return 0;
-}
-
-static const struct of_device_id max96752f_bridge_of_match[] = {
-	{ .compatible = "maxim,max96752f-bridge" },
-	{}
-};
-MODULE_DEVICE_TABLE(of, max96752f_bridge_of_match);
-
-static struct platform_driver max96752f_bridge_driver = {
-	.driver = {
-		.name = "max96752f-bridge",
-		.of_match_table = max96752f_bridge_of_match,
-	},
-	.probe = max96752f_bridge_probe,
-	.remove = max96752f_bridge_remove,
-};
-
-module_platform_driver(max96752f_bridge_driver);
-
-MODULE_AUTHOR("Wyon Bi <bivvy.bi@rock-chips.com>");
-MODULE_DESCRIPTION("Maxim MAX96752F GMSL2 Deserializer with Dual LVDS (OLDI) Output");
-MODULE_LICENSE("GPL");
diff --git a/drivers/gpu/drm/bridge/maxim-max96776.c b/drivers/gpu/drm/bridge/maxim-max96776.c
deleted file mode 100644
index 11afc02425df..000000000000
--- a/drivers/gpu/drm/bridge/maxim-max96776.c
+++ /dev/null
@@ -1,587 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Maxim max96776 GMSL2 Deserializer with eDP Output
- *
- * Copyright (c) 2022 Rockchip Electronics Co. Ltd.
- */
-
-#include <drm/drm_atomic_helper.h>
-#include <drm/drm_bridge.h>
-#include <drm/drm_connector.h>
-#include <drm/drm_dp_helper.h>
-#include <drm/drm_of.h>
-#include <drm/drm_probe_helper.h>
-#include <drm/drm_print.h>
-#include <drm/drm_panel.h>
-
-#include <linux/platform_device.h>
-#include <linux/kernel.h>
-#include <linux/delay.h>
-#include <linux/module.h>
-#include <linux/of.h>
-#include <linux/regmap.h>
-#include <linux/mfd/max96776.h>
-
-#define AUX_ADDR_7_0(x)				(((x) >> 0) & 0xff)
-#define AUX_ADDR_15_8(x)			(((x) >> 8) & 0xff)
-#define AUX_ADDR_19_16(x)			(((x) >> 16) & 0x0f)
-#define DPCD_MAX_LANE_COUNT(x)			((x) & 0x1f)
-
-enum link_lane_count {
-	USE_ONE_LINK = 1,
-	USE_TWO_LINK = 2,
-	USE_FOUR_LINK = 4
-};
-
-enum link_rate {
-	BW_1_62,
-	BW_2_7,
-	BW_5_4,
-};
-
-struct max96776_bridge {
-	struct drm_bridge bridge;
-	struct drm_bridge *next_bridge;
-	struct drm_panel *panel;
-	struct drm_display_mode mode;
-
-	struct device *dev;
-	struct max96776 *parent;
-	struct regmap *regmap;
-	struct drm_dp_aux aux;
-	u8 link_rate;
-	u8 lane_count;
-	int max_link_rate;
-	enum link_lane_count max_lane_count;
-};
-
-static const struct reg_sequence max96776_clk_ref[3][14] = {
-	/* 1.62Gbps */
-	{
-		{ 0xe7b2, 0x50 },
-		{ 0xe7b3, 0x00 },
-		{ 0xe7b4, 0xcc },
-		{ 0xe7b5, 0x44 },
-		{ 0xe7b6, 0x81 },
-		{ 0xe7b7, 0x30 },
-		{ 0xe7b8, 0x07 },
-		{ 0xe7b9, 0x10 },
-		{ 0xe7ba, 0x01 },
-		{ 0xe7bb, 0x00 },
-		{ 0xe7bc, 0x00 },
-		{ 0xe7bd, 0x00 },
-		{ 0xe7be, 0x52 },
-		{ 0xe7bf, 0x00 },
-	},
-
-	/* 2.7Gbps */
-	{
-		{ 0xe7b2, 0x50 },
-		{ 0xe7b3, 0x00 },
-		{ 0xe7b4, 0x00 },
-		{ 0xe7b5, 0x40 },
-		{ 0xe7b6, 0x6c },
-		{ 0xe7b7, 0x20 },
-		{ 0xe7b8, 0x07 },
-		{ 0xe7b9, 0x00 },
-		{ 0xe7ba, 0x01 },
-		{ 0xe7bb, 0x00 },
-		{ 0xe7bc, 0x00 },
-		{ 0xe7bd, 0x00 },
-		{ 0xe7be, 0x52 },
-		{ 0xe7bf, 0x00 },
-	},
-
-	/* 5.4Gbps */
-	{
-		{ 0xe7b2, 0x30 },
-		{ 0xe7b3, 0x00 },
-		{ 0xe7b4, 0x00 },
-		{ 0xe7b5, 0x40 },
-		{ 0xe7b6, 0x6c },
-		{ 0xe7b7, 0x20 },
-		{ 0xe7b8, 0x14 },
-		{ 0xe7b9, 0x00 },
-		{ 0xe7ba, 0x2e },
-		{ 0xe7bb, 0x00 },
-		{ 0xe7bc, 0x00 },
-		{ 0xe7bd, 0x01 },
-		{ 0xe7be, 0x32 },
-		{ 0xe7bf, 0x00 },
-	},
-
-};
-
-#define to_max96776_bridge(x)	container_of(x, struct max96776_bridge, x)
-
-static void
-max96776_dp_aux_dpcd_addr_sel(struct max96776_bridge *des, unsigned int addr)
-{
-	u32 reg;
-
-	reg = AUX_ADDR_7_0(addr);
-	regmap_write(des->regmap, 0xe778, FIELD_PREP(USER_DATA1_B0, reg));
-	reg = AUX_ADDR_15_8(addr);
-	regmap_write(des->regmap, 0xe779, FIELD_PREP(USER_DATA1_B1, reg));
-
-	/*
-	 * Most significant four bits of DPCD register address when performing
-	 * a twenty bit AUX read or write command.
-	 */
-	reg = AUX_ADDR_19_16(addr);
-	regmap_write(des->regmap, 0xe77c, FIELD_PREP(USER_DATA3_B0, reg));
-}
-
-static ssize_t max96776_dp_aux_transfer(struct drm_dp_aux *aux,
-					struct drm_dp_aux_msg *msg)
-{
-	struct max96776_bridge *des = to_max96776_bridge(aux);
-	int num_transferred = 0;
-	u8 *buffer = msg->buffer;
-	u32 reg;
-	int i;
-
-	/*
-	 * as Spec if Burst data transfer is supported,
-	 * The burst data size must be limited to a maximum
-	 * of 16 bytes.
-	 */
-	if (WARN_ON(msg->size > 16))
-		return -E2BIG;
-
-	/*
-	 * Write AUX channel
-	 *
-	 * this command writes a DPCD register on the eDP/DP sink device. The register
-	 * address is specified by the user in address 0xe778 and 0xe779. The data (a byte)
-	 * to be written is specified in 0xe77a. The AUX channel must be configured prior to
-	 * using the command(this occurs at power-up). The example below writes DPCD sink
-	 * register 0x0100 with data 0x0a, To issue command, write the following registers:
-	 *
-	 * 1. LSBs of write address: 0xe778 0x00
-	 * 2. MSBs of write address: 0xe779 0x01
-	 * 3. LSBs of data to write: 0xe77a 0x0a
-	 * 4. command select: 0xe776 0x20
-	 * 5. Execute command: 0xe777 0x80
-	 */
-	if (!(msg->request & DP_AUX_I2C_READ)) {
-		for (i = 0; i < msg->size; i++) {
-			max96776_dp_aux_dpcd_addr_sel(des, msg->address + i);
-			reg = buffer[i];
-			regmap_write(des->regmap, 0xe77a,
-				     FIELD_PREP(USER_DATA2_B0, reg));
-			regmap_update_bits(des->regmap, 0xe776, AUX_WRITE,
-					   FIELD_PREP(AUX_WRITE, 1));
-			regmap_update_bits(des->regmap, 0xe777, RUN_COMMAND,
-					   FIELD_PREP(RUN_COMMAND, 1));
-			mdelay(10);
-			num_transferred++;
-		}
-	}
-
-	/*
-	 * Read AUX channel
-	 *
-	 * this command read DPCD register on the eDP/DP sink device. The register
-	 * address is specified by the user in address 0xe778 and 0xe779. Once the
-	 * command has executed, the return data (a byte) is stored in 0xe77a. The
-	 * AUX channel must be configured prior to using the command(this occurs
-	 * at power-up). The example, to read DPCD sink register 0x100 (main link
-	 * bandwidth setting), write the following registers:
-	 *
-	 * 1. LSBs of write address: 0xe778 0x00
-	 * 2. MSBs of write address: 0xe779 0x01
-	 * 3. command select: 0xe776 0x10
-	 * 4. Execute command: 0xe777 0x80
-	 * 5. LSBs of return value read: 0xe77a
-	 */
-	if (msg->request & DP_AUX_I2C_READ) {
-		for (i = 0; i < msg->size; i++) {
-			max96776_dp_aux_dpcd_addr_sel(des, msg->address + i);
-			regmap_update_bits(des->regmap, 0xe776, AUX_READ,
-					   FIELD_PREP(AUX_READ, 1));
-			regmap_update_bits(des->regmap, 0xe777, RUN_COMMAND,
-					   FIELD_PREP(RUN_COMMAND, 1));
-			mdelay(10);
-			regmap_read(des->regmap, 0xe77a, &reg);
-			buffer[i] = (u8)reg;
-
-			num_transferred++;
-		}
-	}
-
-	msg->reply = DP_AUX_I2C_REPLY_ACK;
-	return (num_transferred == msg->size) ? num_transferred : -EBUSY;
-}
-
-static int max96776_bridge_get_modes(struct drm_bridge *bridge,
-				      struct drm_connector *connector)
-{
-	struct max96776_bridge *des = to_max96776_bridge(bridge);
-
-	if (des->next_bridge)
-		return drm_bridge_get_modes(des->next_bridge, connector);
-
-	if (des->panel)
-		return drm_panel_get_modes(des->panel, connector);
-
-	return drm_add_modes_noedid(connector, 1920, 1080);
-}
-
-static void max96776_edp_timing_config(struct max96776_bridge *des)
-{
-	struct drm_display_mode *mode = &des->mode;
-	u32 hfp, hsa, hbp, hact;
-	u32 vact, vsa, vfp, vbp;
-	u64 hwords, mvid, link_rate;
-	bool hsync_pol, vsync_pol;
-
-	vact = mode->vdisplay;
-	vsa = mode->vsync_end - mode->vsync_start;
-	vfp = mode->vsync_start - mode->vdisplay;
-	vbp = mode->vtotal - mode->vsync_end;
-	hact = mode->hdisplay;
-	hsa = mode->hsync_end - mode->hsync_start;
-	hfp = mode->hsync_start - mode->hdisplay;
-	hbp = mode->htotal - mode->hsync_end;
-
-	regmap_write(des->regmap, 0xe794, FIELD_PREP(HRES_B0, hact));
-	regmap_write(des->regmap, 0xe795, FIELD_PREP(HRES_B1, hact >> 8));
-	regmap_write(des->regmap, 0xe796, FIELD_PREP(HFP_B0, hfp));
-	regmap_write(des->regmap, 0xe797, FIELD_PREP(HFP_B1, hfp >> 8));
-	regmap_write(des->regmap, 0xe798, FIELD_PREP(HSW_B0, hsa));
-	regmap_write(des->regmap, 0xe799, FIELD_PREP(HSW_B1, hsa >> 8));
-	regmap_write(des->regmap, 0xe79a, FIELD_PREP(HBP_B0, hbp));
-	regmap_write(des->regmap, 0xe79b, FIELD_PREP(HBP_B1, hbp >> 8));
-	regmap_write(des->regmap, 0xe79c, FIELD_PREP(VRES_B0, vact));
-	regmap_write(des->regmap, 0xe79d, FIELD_PREP(VRES_B1, vact >> 8));
-	regmap_write(des->regmap, 0xe79e, FIELD_PREP(VFP_B0, vfp));
-	regmap_write(des->regmap, 0xe79f, FIELD_PREP(VFP_B1, vfp >> 8));
-	regmap_write(des->regmap, 0xe7a0, FIELD_PREP(VSW_B0, vsa));
-	regmap_write(des->regmap, 0xe7a1, FIELD_PREP(VSW_B1, vsa >> 8));
-	regmap_write(des->regmap, 0xe7a2, FIELD_PREP(VBP_B0, vbp));
-	regmap_write(des->regmap, 0xe7a3, FIELD_PREP(VBP_B1, vbp >> 8));
-
-	hsync_pol = !!(mode->flags & DRM_MODE_FLAG_NHSYNC);
-	vsync_pol = !!(mode->flags & DRM_MODE_FLAG_NVSYNC);
-	regmap_update_bits(des->regmap, 0xe7ac, HSYNC_POL | VSYNC_POL,
-			   FIELD_PREP(HSYNC_POL, hsync_pol) |
-			   FIELD_PREP(VSYNC_POL, vsync_pol));
-
-	/* NVID should always be set to 0x8000 */
-	regmap_write(des->regmap, 0xe7a8, FIELD_PREP(NVID_B0, 0));
-	regmap_write(des->regmap, 0xe7a9, FIELD_PREP(NVID_B1, 0x80));
-
-	/* HWORDS = ((HRES x bits/pixel)/16) - LANE_COUNT */
-	hwords = DIV_ROUND_CLOSEST_ULL(hact * 24, 16) - des->lane_count;
-	regmap_write(des->regmap, 0xe7a4, FIELD_PREP(HWORDS_B0, hwords));
-	regmap_write(des->regmap, 0xe7a5, FIELD_PREP(HWORDS_B1, hwords >> 8));
-
-	/* MVID = (PCLK x NVID) x 10 / Link Rate */
-	link_rate = drm_dp_bw_code_to_link_rate(des->link_rate);
-	mvid = DIV_ROUND_CLOSEST_ULL((u64)mode->clock * 32768, link_rate);
-	regmap_write(des->regmap, 0xe7a6, FIELD_PREP(HWORDS_B0, mvid));
-	regmap_write(des->regmap, 0xe7a7, FIELD_PREP(HWORDS_B1, mvid >> 8));
-
-	regmap_write(des->regmap, 0xe7aa, FIELD_PREP(TUC_VALUE_B0, 0x40));
-	regmap_write(des->regmap, 0xe7ab, FIELD_PREP(TUC_VALUE_B1, 0));
-}
-
-static void max96776_get_edp_sink_max_lane_count(struct max96776_bridge *des)
-{
-	u8 data;
-
-	/*
-	 * For DP rev.1.1, Maximum number of Main Link lanes
-	 * 0x01 = 1 lane, 0x02 = 2 lanes, 0x04 = 4 lanes
-	 */
-	drm_dp_dpcd_readb(&des->aux, DP_MAX_LANE_COUNT, &data);
-	des->lane_count = DPCD_MAX_LANE_COUNT(data);
-}
-
-static void max96776_get_edp_sink_max_bw(struct max96776_bridge *des)
-{
-	u8 data;
-
-	/*
-	 * For DP rev.1.1, Maximum link rate of Main Link lanes
-	 * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps
-	 * For DP rev.1.2, Maximum link rate of Main Link lanes
-	 * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps, 0x14 = 5.4Gbps
-	 * For DP rev.1.4, Maximum link rate of Main Link lanes
-	 * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps, 0x14 = 5.4Gbps 0x1e = 8.1 Gbps
-	 */
-	drm_dp_dpcd_readb(&des->aux, DP_MAX_LINK_RATE, &data);
-	des->link_rate = data;
-}
-
-static void max96776_edp_link_config(struct max96776_bridge *des)
-{
-
-	max96776_get_edp_sink_max_bw(des);
-	max96776_get_edp_sink_max_lane_count(des);
-
-	if ((des->link_rate != DP_LINK_BW_1_62) &&
-	    (des->link_rate != DP_LINK_BW_2_7) &&
-	    (des->link_rate != DP_LINK_BW_5_4) &&
-	    (des->link_rate != DP_LINK_BW_8_1)) {
-		dev_err(des->dev, "Rx Max Link Rate is abnormal :%x !\n",
-			des->link_rate);
-		des->link_rate = DP_LINK_BW_1_62;
-	}
-
-	if (des->lane_count == 0) {
-		dev_err(des->dev, "Rx Max Lane count is abnormal :%x !\n",
-			des->lane_count);
-		des->lane_count = (u8)USE_ONE_LINK;
-	}
-
-	/* Setup TX lane count & rate */
-	if (des->lane_count > (u8)des->max_lane_count)
-		des->lane_count = (u8)des->max_lane_count;
-	if (des->link_rate > des->max_link_rate)
-		des->link_rate = des->max_link_rate;
-
-	regmap_write(des->regmap, 0xe790, FIELD_PREP(LINK_RATE, des->link_rate));
-	regmap_write(des->regmap, 0xe792, FIELD_PREP(LANE_COUNT, des->lane_count));
-	dev_info(des->dev, "final bandwidth: 0x%02x, lane count: 0x%02x\n",
-		 des->link_rate, des->lane_count);
-}
-
-static void max96776_edp_pll_config(struct max96776_bridge *des)
-{
-	/* provides control for eDP PLL */
-	switch (des->link_rate) {
-	case DP_LINK_BW_5_4:
-		regmap_multi_reg_write(des->regmap, max96776_clk_ref[BW_5_4],
-				       ARRAY_SIZE(max96776_clk_ref[BW_5_4]));
-		break;
-	case DP_LINK_BW_2_7:
-		regmap_multi_reg_write(des->regmap, max96776_clk_ref[BW_2_7],
-				       ARRAY_SIZE(max96776_clk_ref[BW_2_7]));
-		break;
-	case DP_LINK_BW_1_62:
-	default:
-		regmap_multi_reg_write(des->regmap, max96776_clk_ref[BW_1_62],
-				       ARRAY_SIZE(max96776_clk_ref[BW_1_62]));
-		break;
-	}
-}
-
-static void max96776_edp_full_training(struct max96776_bridge *des)
-{
-	u8 status[2];
-	u32 sts;
-	int ret;
-
-	regmap_update_bits(des->regmap, 0xe776, RUN_LINK_TRAINING,
-			   FIELD_PREP(RUN_LINK_TRAINING, 0x1));
-	regmap_update_bits(des->regmap, 0xe777, RUN_COMMAND,
-			   FIELD_PREP(RUN_COMMAND, 0x1));
-	ret = regmap_read_poll_timeout(des->regmap, 0x07f0, sts,
-				       FIELD_PREP(TRAINING_SUCCESSFUL, sts),
-				       MSEC_PER_SEC, 200 * MSEC_PER_SEC);
-	if (ret < 0)
-		dev_err(des->dev, "Link Training not successful\n");
-
-	drm_dp_dpcd_read(&des->aux, DP_LANE0_1_STATUS, status, 2);
-	dev_info(des->dev, "SINK LANE0_1_STATUS:0x%02x LANE2_3_STATUS:0x%02x\n",
-		 status[0], status[1]);
-}
-
-static void
-max96776_bridge_atomic_pre_enable(struct drm_bridge *bridge,
-				   struct drm_bridge_state *old_bridge_state)
-{
-	struct max96776_bridge *des = to_max96776_bridge(bridge);
-	u8 dpcd;
-
-	/* disable HDCP 2.2 on eDP Deserializer */
-	regmap_update_bits(des->regmap, 0x1700, CMD_RESET,
-			   FIELD_PREP(CMD_RESET, 0x01));
-
-	/*
-	 * This bit must be set to allow waiting for the
-	 * CMU to lock. It also should be set when using
-	 * SSC. Otherwise, a fixed wait time of 20μS is
-	 * used.
-	 */
-	regmap_update_bits(des->regmap, 0xe7b0, SS_ENABLE,
-			   FIELD_PREP(SS_ENABLE, 0x01));
-
-	/*
-	 * Determines whether spread spectrum clocking (SSC)
-	 * is used with the DP sink device.
-	 */
-	drm_dp_dpcd_readb(&des->aux, DP_MAX_DOWNSPREAD, &dpcd);
-	if (!!(dpcd & DP_MAX_DOWNSPREAD_0_5))
-		regmap_update_bits(des->regmap, 0xe7b1, SSC_ENABLE,
-				   FIELD_PREP(SSC_ENABLE, 0x01));
-
-	max96776_edp_link_config(des);
-	max96776_edp_pll_config(des);
-	max96776_edp_timing_config(des);
-
-	if (des->panel)
-		drm_panel_prepare(des->panel);
-}
-
-static void
-max96776_bridge_atomic_enable(struct drm_bridge *bridge,
-			       struct drm_bridge_state *old_bridge_state)
-{
-	struct max96776_bridge *des = to_max96776_bridge(bridge);
-
-	max96776_edp_full_training(des);
-
-	if (des->panel)
-		drm_panel_enable(des->panel);
-}
-
-static void
-max96776_bridge_atomic_disable(struct drm_bridge *bridge,
-				struct drm_bridge_state *old_bridge_state)
-{
-	struct max96776_bridge *des = to_max96776_bridge(bridge);
-
-	if (des->panel)
-		drm_panel_disable(des->panel);
-}
-
-static void
-max96776_bridge_atomic_post_disable(struct drm_bridge *bridge,
-				     struct drm_bridge_state *old_bridge_state)
-{
-	struct max96776_bridge *des = to_max96776_bridge(bridge);
-
-	if (des->panel)
-		drm_panel_unprepare(des->panel);
-}
-
-
-static int max96776_bridge_attach(struct drm_bridge *bridge,
-				   enum drm_bridge_attach_flags flags)
-{
-	struct max96776_bridge *des = to_max96776_bridge(bridge);
-	int ret;
-
-	ret = drm_of_find_panel_or_bridge(bridge->of_node, 1, -1, &des->panel,
-					  &des->next_bridge);
-	if (ret < 0 && ret != -ENODEV)
-		return ret;
-
-	if (des->next_bridge)
-		return drm_bridge_attach(bridge->encoder, des->next_bridge,
-					 bridge, 0);
-
-	return 0;
-}
-
-static void max96776_bridge_mode_set(struct drm_bridge *bridge,
-				   const struct drm_display_mode *mode,
-				   const struct drm_display_mode *adj_mode)
-{
-	struct max96776_bridge *des  = to_max96776_bridge(bridge);
-
-	drm_mode_copy(&des->mode, adj_mode);
-}
-
-static enum drm_connector_status
-max96776_bridge_detect(struct drm_bridge *bridge)
-{
-	struct max96776_bridge *des = to_max96776_bridge(bridge);
-	u32 hpd;
-
-	if (regmap_read(des->regmap, 0x6230, &hpd))
-		return connector_status_disconnected;
-
-	if (!FIELD_PREP(HPD_PRESENT, hpd))
-		return connector_status_disconnected;
-
-	return connector_status_connected;
-}
-
-static const struct drm_bridge_funcs max96776_bridge_funcs = {
-	.attach = max96776_bridge_attach,
-	.detect = max96776_bridge_detect,
-	.get_modes = max96776_bridge_get_modes,
-	.atomic_pre_enable = max96776_bridge_atomic_pre_enable,
-	.atomic_post_disable = max96776_bridge_atomic_post_disable,
-	.atomic_enable = max96776_bridge_atomic_enable,
-	.atomic_disable = max96776_bridge_atomic_disable,
-	.atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
-	.atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
-	.atomic_reset = drm_atomic_helper_bridge_reset,
-	.mode_set = max96776_bridge_mode_set,
-};
-
-static int max96776_bridge_probe(struct platform_device *pdev)
-{
-	struct device *dev = &pdev->dev;
-	struct max96776_bridge *des;
-	int ret;
-
-	des = devm_kzalloc(dev, sizeof(*des), GFP_KERNEL);
-	if (!des)
-		return -ENOMEM;
-
-	des->dev = dev;
-	des->parent = dev_get_drvdata(dev->parent);
-	platform_set_drvdata(pdev, des);
-
-	des->regmap = dev_get_regmap(dev->parent, NULL);
-	if (!des->regmap)
-		return dev_err_probe(dev, -ENODEV, "failed to get regmap\n");
-
-	des->max_link_rate = DP_LINK_BW_5_4;
-	des->max_lane_count = USE_FOUR_LINK;
-
-	des->aux.name = "DP-AUX";
-	des->aux.transfer = max96776_dp_aux_transfer;
-	des->aux.dev = des->dev;
-
-	ret = drm_dp_aux_register(&des->aux);
-	if (ret) {
-		dev_err(dev, "failed to register dp aux\n");
-		return ret;
-	}
-
-	des->bridge.funcs = &max96776_bridge_funcs;
-	des->bridge.of_node = dev->of_node;
-	des->bridge.ops = DRM_BRIDGE_OP_MODES | DRM_BRIDGE_OP_DETECT;
-	des->bridge.type = DRM_MODE_CONNECTOR_eDP;
-
-	drm_bridge_add(&des->bridge);
-
-	return 0;
-}
-
-static int max96776_bridge_remove(struct platform_device *pdev)
-{
-	struct max96776_bridge *des = platform_get_drvdata(pdev);
-
-	drm_bridge_remove(&des->bridge);
-
-	return 0;
-}
-
-static const struct of_device_id max96776_bridge_of_match[] = {
-	{ .compatible = "maxim,max96776-bridge" },
-	{}
-};
-MODULE_DEVICE_TABLE(of, max96776_bridge_of_match);
-
-static struct platform_driver max96776_bridge_driver = {
-	.driver = {
-		.name = "max96776-bridge",
-		.of_match_table = max96776_bridge_of_match,
-	},
-	.probe = max96776_bridge_probe,
-	.remove = max96776_bridge_remove,
-};
-
-module_platform_driver(max96776_bridge_driver);
-
-MODULE_AUTHOR("Guochun Huang <hero.huang@rock-chips.com>");
-MODULE_DESCRIPTION("Maxim max96776 GMSL2 Deserializer with eDP Output");
-MODULE_LICENSE("GPL");
diff --git a/drivers/gpu/drm/rockchip/Kconfig b/drivers/gpu/drm/rockchip/Kconfig
index ca02c1804e81..b772476ee7c0 100644
--- a/drivers/gpu/drm/rockchip/Kconfig
+++ b/drivers/gpu/drm/rockchip/Kconfig
@@ -82,6 +82,13 @@ config ROCKCHIP_CDN_DP
 	  RK3399 based SoC, you should select this
 	  option.
 
+config ROCKCHIP_DRM_TVE
+	bool "Rockchip TVE support"
+	depends on DRM_ROCKCHIP
+	help
+	  Choose this option to enable support for Rockchip TVE controllers.
+	  say Y to enable its driver.
+
 config ROCKCHIP_DW_HDMI
 	bool "Rockchip specific extensions for Synopsys DW HDMI"
 	help
diff --git a/drivers/gpu/drm/rockchip/Makefile b/drivers/gpu/drm/rockchip/Makefile
index 97116e397de4..4d730f9d7d3c 100644
--- a/drivers/gpu/drm/rockchip/Makefile
+++ b/drivers/gpu/drm/rockchip/Makefile
@@ -17,6 +17,7 @@ rockchipdrm-$(CONFIG_ROCKCHIP_DRM_SELF_TEST) += rockchip_drm_display_pattern.o	\
 
 rockchipdrm-$(CONFIG_ROCKCHIP_ANALOGIX_DP) += analogix_dp-rockchip.o
 rockchipdrm-$(CONFIG_ROCKCHIP_CDN_DP) += cdn-dp-core.o cdn-dp-reg.o
+rockchipdrm-$(CONFIG_ROCKCHIP_DRM_TVE) += rockchip_drm_tve.o
 rockchipdrm-$(CONFIG_ROCKCHIP_DW_HDMI) += dw_hdmi-rockchip.o
 rockchipdrm-$(CONFIG_ROCKCHIP_DW_MIPI_DSI) += dw-mipi-dsi-rockchip.o \
 					      dw-mipi-dsi2-rockchip.o
diff --git a/drivers/gpu/drm/rockchip/dw-dp.c b/drivers/gpu/drm/rockchip/dw-dp.c
index b0f2c05f4c83..1330a149cdee 100644
--- a/drivers/gpu/drm/rockchip/dw-dp.c
+++ b/drivers/gpu/drm/rockchip/dw-dp.c
@@ -1854,6 +1854,26 @@ static void dw_dp_encoder_disable(struct drm_encoder *encoder)
 		s->output_if &= ~(dp->id ? VOP_OUTPUT_IF_DP1 : VOP_OUTPUT_IF_DP0);
 }
 
+static void dw_dp_mode_fixup(struct dw_dp *dp, struct drm_display_mode *adjusted_mode)
+{
+	int min_hbp = 16;
+	int min_hsync = 9;
+
+	if (dp->split_mode) {
+		min_hbp *= 2;
+		min_hsync *= 2;
+	}
+
+	if (adjusted_mode->hsync_end - adjusted_mode->hsync_start < min_hsync) {
+		adjusted_mode->hsync_end = adjusted_mode->hsync_start + min_hsync;
+		dev_warn(dp->dev, "hsync is too narrow, fixup to min hsync:%d\n", min_hsync);
+	}
+	if (adjusted_mode->htotal - adjusted_mode->hsync_end < min_hbp) {
+		adjusted_mode->htotal = adjusted_mode->hsync_end + min_hbp;
+		dev_warn(dp->dev, "hbp is too narrow, fixup to min hbp:%d\n", min_hbp);
+	}
+}
+
 static int dw_dp_encoder_atomic_check(struct drm_encoder *encoder,
 				      struct drm_crtc_state *crtc_state,
 				      struct drm_connector_state *conn_state)
@@ -1892,6 +1912,8 @@ static int dw_dp_encoder_atomic_check(struct drm_encoder *encoder,
 	s->eotf = HDMI_EOTF_TRADITIONAL_GAMMA_SDR;
 	s->color_space = V4L2_COLORSPACE_DEFAULT;
 
+	dw_dp_mode_fixup(dp, &crtc_state->adjusted_mode);
+
 	return 0;
 }
 
@@ -2032,9 +2054,6 @@ static int dw_dp_bridge_mode_valid(struct drm_bridge *bridge,
 	if (dp->split_mode)
 		drm_mode_convert_to_origin_mode(&m);
 
-	if (m.hsync_end - m.hsync_start <= 8)
-		return MODE_HSYNC_NARROW;
-
 	if (info->color_formats & DRM_COLOR_FORMAT_YCRCB420 &&
 	    link->vsc_sdp_extension_for_colorimetry_supported &&
 	    (drm_mode_is_420_only(info, &m) || drm_mode_is_420_also(info, &m)))
diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c
index 015f983ad39e..3d6a1ed7599e 100644
--- a/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c
+++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c
@@ -296,6 +296,7 @@ struct dw_mipi_dsi_rockchip {
 	int devcnt;
 	struct rockchip_drm_sub_dev sub_dev;
 	struct drm_panel *panel;
+	struct drm_bridge *bridge;
 };
 
 struct dphy_pll_parameter_map {
@@ -974,6 +975,13 @@ static int dw_mipi_dsi_rockchip_bind(struct device *dev,
 	struct device *second;
 	int ret;
 
+	ret = drm_of_find_panel_or_bridge(dsi->dev->of_node, 1, 0,
+					  &dsi->panel, &dsi->bridge);
+	if (ret) {
+		dev_err(dsi->dev, "failed to find panel or bridge: %d\n", ret);
+		return ret;
+	}
+
 	second = dw_mipi_dsi_rockchip_find_second(dsi);
 	if (IS_ERR(second))
 		return PTR_ERR(second);
@@ -1012,12 +1020,8 @@ static int dw_mipi_dsi_rockchip_bind(struct device *dev,
 		return ret;
 	}
 
-	ret = drm_of_find_panel_or_bridge(dsi->dev->of_node, 1, 0,
-					  &dsi->panel, NULL);
-	if (ret)
-		dev_err(dsi->dev, "failed to find panel\n");
-
-	dw_mipi_dsi_get_dsc_info_from_sink(dsi, dsi->panel, NULL);
+	if (dsi->panel)
+		dw_mipi_dsi_get_dsc_info_from_sink(dsi, dsi->panel, NULL);
 
 	dsi->sub_dev.connector = dw_mipi_dsi_get_connector(dsi->dmd);
 	if (dsi->sub_dev.connector) {
@@ -1051,10 +1055,8 @@ static const struct component_ops dw_mipi_dsi_rockchip_ops = {
 	.unbind	= dw_mipi_dsi_rockchip_unbind,
 };
 
-static int dw_mipi_dsi_rockchip_host_attach(void *priv_data,
-					    struct mipi_dsi_device *device)
+static int dw_mipi_dsi_rockchip_component_add(struct dw_mipi_dsi_rockchip *dsi)
 {
-	struct dw_mipi_dsi_rockchip *dsi = priv_data;
 	struct device *second;
 	int ret;
 
@@ -1081,10 +1083,8 @@ static int dw_mipi_dsi_rockchip_host_attach(void *priv_data,
 	return 0;
 }
 
-static int dw_mipi_dsi_rockchip_host_detach(void *priv_data,
-					    struct mipi_dsi_device *device)
+static int dw_mipi_dsi_rockchip_component_del(struct dw_mipi_dsi_rockchip *dsi)
 {
-	struct dw_mipi_dsi_rockchip *dsi = priv_data;
 	struct device *second;
 
 	second = dw_mipi_dsi_rockchip_find_second(dsi);
@@ -1096,11 +1096,6 @@ static int dw_mipi_dsi_rockchip_host_detach(void *priv_data,
 	return 0;
 }
 
-static const struct dw_mipi_dsi_host_ops dw_mipi_dsi_rockchip_host_ops = {
-	.attach = dw_mipi_dsi_rockchip_host_attach,
-	.detach = dw_mipi_dsi_rockchip_host_detach,
-};
-
 static int dw_mipi_dsi_rockchip_probe(struct platform_device *pdev)
 {
 	struct device *dev = &pdev->dev;
@@ -1208,7 +1203,6 @@ static int dw_mipi_dsi_rockchip_probe(struct platform_device *pdev)
 	dsi->pdata.base = dsi->base;
 	dsi->pdata.max_data_lanes = dsi->cdata->max_data_lanes;
 	dsi->pdata.phy_ops = &dw_mipi_dsi_rockchip_phy_ops;
-	dsi->pdata.host_ops = &dw_mipi_dsi_rockchip_host_ops;
 	dsi->pdata.priv_data = dsi;
 	platform_set_drvdata(pdev, dsi);
 
@@ -1221,6 +1215,12 @@ static int dw_mipi_dsi_rockchip_probe(struct platform_device *pdev)
 		goto err_clkdisable;
 	}
 
+	ret = dw_mipi_dsi_rockchip_component_add(dsi);
+	if (ret < 0) {
+		dw_mipi_dsi_remove(dsi->dmd);
+		goto err_clkdisable;
+	}
+
 	return 0;
 
 err_clkdisable:
@@ -1232,9 +1232,8 @@ static int dw_mipi_dsi_rockchip_remove(struct platform_device *pdev)
 {
 	struct dw_mipi_dsi_rockchip *dsi = platform_get_drvdata(pdev);
 
-	if (dsi->devcnt == 0)
-		component_del(dsi->dev, &dw_mipi_dsi_rockchip_ops);
 
+	dw_mipi_dsi_rockchip_component_del(dsi);
 	dw_mipi_dsi_remove(dsi->dmd);
 
 	return 0;
diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_drv.c b/drivers/gpu/drm/rockchip/rockchip_drm_drv.c
index 7531cdc6f313..edb540d34cb7 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_drv.c
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_drv.c
@@ -53,6 +53,36 @@ static bool iommu_reserve_map;
 
 static struct drm_driver rockchip_drm_driver;
 
+static unsigned int drm_debug;
+module_param_named(debug, drm_debug, int, 0600);
+
+static inline bool rockchip_drm_debug_enabled(enum rockchip_drm_debug_category category)
+{
+	return unlikely(drm_debug & category);
+}
+
+__printf(3, 4)
+void rockchip_drm_dbg(const struct device *dev, enum rockchip_drm_debug_category category,
+		      const char *format, ...)
+{
+	struct va_format vaf;
+	va_list args;
+
+	if (!rockchip_drm_debug_enabled(category))
+		return;
+
+	va_start(args, format);
+	vaf.fmt = format;
+	vaf.va = &args;
+
+	if (dev)
+		dev_printk(KERN_DEBUG, dev, "%pV", &vaf);
+	else
+		printk(KERN_DEBUG "%pV", &vaf);
+
+	va_end(args);
+}
+
 /**
  * rockchip_drm_wait_vact_end
  * @crtc: CRTC to enable line flag
@@ -1025,10 +1055,19 @@ static int rockchip_drm_init_iommu(struct drm_device *drm_dev)
 				drm_dev);
 
 	if (iommu_reserve_map) {
-		ret = iommu_map(private->domain, 0, 0, (size_t)SZ_4G,
+		/*
+		 * At 32 bit platform size_t maximum value is 0xffffffff, SZ_4G(0x100000000) will be
+		 * cliped to 0, so we split into two mapping
+		 */
+		ret = iommu_map(private->domain, 0, 0, (size_t)SZ_2G,
 				IOMMU_WRITE | IOMMU_READ | IOMMU_PRIV);
 		if (ret)
-			dev_err(drm_dev->dev, "failed to create pre mapping\n");
+			dev_err(drm_dev->dev, "failed to create 0-2G pre mapping\n");
+
+		ret = iommu_map(private->domain, SZ_2G, SZ_2G, (size_t)SZ_2G,
+				IOMMU_WRITE | IOMMU_READ | IOMMU_PRIV);
+		if (ret)
+			dev_err(drm_dev->dev, "failed to create 2G-4G pre mapping\n");
 	}
 
 	return ret;
@@ -1041,8 +1080,10 @@ static void rockchip_iommu_cleanup(struct drm_device *drm_dev)
 	if (!is_support_iommu)
 		return;
 
-	if (iommu_reserve_map)
-		iommu_unmap(private->domain, 0, (size_t)SZ_4G);
+	if (iommu_reserve_map) {
+		iommu_unmap(private->domain, 0, (size_t)SZ_2G);
+		iommu_unmap(private->domain, SZ_2G, (size_t)SZ_2G);
+	}
 	drm_mm_takedown(&private->mm);
 	iommu_domain_free(private->domain);
 }
@@ -1947,6 +1988,7 @@ static int __init rockchip_drm_init(void)
 	ADD_ROCKCHIP_SUB_DRIVER(rk3066_hdmi_driver,
 				CONFIG_ROCKCHIP_RK3066_HDMI);
 	ADD_ROCKCHIP_SUB_DRIVER(rockchip_rgb_driver, CONFIG_ROCKCHIP_RGB);
+	ADD_ROCKCHIP_SUB_DRIVER(rockchip_tve_driver, CONFIG_ROCKCHIP_DRM_TVE);
 	ADD_ROCKCHIP_SUB_DRIVER(dw_dp_driver, CONFIG_ROCKCHIP_DW_DP);
 
 #endif
diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_drv.h b/drivers/gpu/drm/rockchip/rockchip_drm_drv.h
index 434d3c93271b..3dd30880f6a2 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_drv.h
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_drv.h
@@ -64,6 +64,14 @@ struct iommu_domain;
 #define RK_IF_PROP_COLOR_DEPTH_CAPS	"color_depth_caps"
 #define RK_IF_PROP_COLOR_FORMAT_CAPS	"color_format_caps"
 
+enum rockchip_drm_debug_category {
+	VOP_DEBUG_PLANE		= BIT(0),
+	VOP_DEBUG_OVERLAY	= BIT(1),
+	VOP_DEBUG_WB		= BIT(2),
+	VOP_DEBUG_CFG_DONE	= BIT(3),
+	VOP_DEBUG_VSYNC		= BIT(7),
+};
+
 enum rk_if_color_depth {
 	RK_IF_DEPTH_8,
 	RK_IF_DEPTH_10,
@@ -490,6 +498,9 @@ int rockchip_drm_parse_cea_ext(struct rockchip_drm_dsc_cap *dsc_cap,
 			       const struct edid *edid);
 int rockchip_drm_parse_next_hdr(struct next_hdr_sink_data *sink_data,
 				const struct edid *edid);
+__printf(3, 4)
+void rockchip_drm_dbg(const struct device *dev, enum rockchip_drm_debug_category category,
+		      const char *format, ...);
 
 extern struct platform_driver cdn_dp_driver;
 extern struct platform_driver dw_hdmi_rockchip_pltfm_driver;
@@ -502,6 +513,7 @@ extern struct platform_driver vop_platform_driver;
 extern struct platform_driver vop2_platform_driver;
 extern struct platform_driver rk3066_hdmi_driver;
 extern struct platform_driver rockchip_rgb_driver;
+extern struct platform_driver rockchip_tve_driver;
 extern struct platform_driver dw_dp_driver;
 extern struct platform_driver vconn_platform_driver;
 extern struct platform_driver vvop_platform_driver;
diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_logo.c b/drivers/gpu/drm/rockchip/rockchip_drm_logo.c
index e50453ebae8d..f1dd87f9fb0f 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_logo.c
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_logo.c
@@ -148,17 +148,19 @@ static int rockchip_drm_reserve_vm(struct drm_device *drm, struct drm_mm *mm,
 }
 
 static unsigned long
-rockchip_drm_free_reserved_area(void *start, void *end, int poison, const char *s)
+rockchip_drm_free_reserved_area(phys_addr_t start, phys_addr_t end, int poison, const char *s)
 {
-	void *pos;
 	unsigned long pages = 0;
 
-	start = (void *)PAGE_ALIGN((unsigned long)start);
-	end = (void *)((unsigned long)end & PAGE_MASK);
-	for (pos = start; pos < end; pos += PAGE_SIZE, pages++) {
-		struct page *page = virt_to_page(pos);
+	start = ALIGN_DOWN(start, PAGE_SIZE);
+	end = PAGE_ALIGN(end);
+	for (; start < end; start += PAGE_SIZE) {
+		struct page *page = phys_to_page(start);
 		void *direct_map_addr;
 
+		if (!pfn_valid(__phys_to_pfn(start)))
+			continue;
+
 		/*
 		 * 'direct_map_addr' might be different from 'pos'
 		 * because some architectures' virt_to_page()
@@ -176,6 +178,7 @@ rockchip_drm_free_reserved_area(void *start, void *end, int poison, const char *
 			memset(direct_map_addr, poison, PAGE_SIZE);
 
 		free_reserved_page(page);
+		pages++;
 	}
 
 	if (pages && s)
@@ -188,14 +191,11 @@ void rockchip_free_loader_memory(struct drm_device *drm)
 {
 	struct rockchip_drm_private *private = drm->dev_private;
 	struct rockchip_logo *logo;
-	void *start, *end;
 
 	if (!private || !private->logo || --private->logo->count)
 		return;
 
 	logo = private->logo;
-	start = phys_to_virt(logo->dma_addr);
-	end = phys_to_virt(logo->dma_addr + logo->size);
 
 	if (private->domain) {
 		u32 pg_size = 1UL << __ffs(private->domain->pgsize_bitmap);
@@ -205,7 +205,8 @@ void rockchip_free_loader_memory(struct drm_device *drm)
 	}
 
 	memblock_free(logo->start, logo->size);
-	rockchip_drm_free_reserved_area(start, end, -1, "drm_logo");
+	rockchip_drm_free_reserved_area(logo->dma_addr, logo->dma_addr + logo->size,
+					-1, "drm_logo");
 	kfree(logo);
 	private->logo = NULL;
 	private->loader_protect = false;
diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_tve.c b/drivers/gpu/drm/rockchip/rockchip_drm_tve.c
index 0acf55916056..e919b57d1cb2 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_tve.c
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_tve.c
@@ -1,17 +1,20 @@
 /* SPDX-License-Identifier: GPL-2.0 */
 #include <linux/module.h>
+#include <linux/clk.h>
 #include <linux/delay.h>
 #include <linux/err.h>
 #include <linux/hdmi.h>
 #include <linux/mutex.h>
+#include <linux/mfd/syscon.h>
 #include <linux/nvmem-consumer.h>
 #include <linux/of_device.h>
 #include <linux/pm_runtime.h>
+#include <linux/regmap.h>
 
-#include <drm/drmP.h>
 #include <drm/drm_atomic_helper.h>
 #include <drm/drm_crtc_helper.h>
 #include <drm/drm_of.h>
+#include <drm/drm_probe_helper.h>
 
 #include <uapi/linux/videodev2.h>
 
@@ -26,23 +29,31 @@ static const struct drm_display_mode cvbs_mode[] = {
 		   816, 864, 0, 576, 580, 586, 625, 0,
 		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
 		   DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
-		   .vrefresh = 50, 0, },
+		   0, },
 
 	{ DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 753,
 		   815, 858, 0, 480, 480, 486, 525, 0,
 		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
 		   DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
-		   .vrefresh = 60, 0, },
+		   0, },
 };
 
-#define tve_writel(offset, v)	writel_relaxed(v, tve->regbase + (offset))
-#define tve_readl(offset)	readl_relaxed(tve->regbase + (offset))
+#define tve_writel(offset, v)		writel_relaxed(v, tve->regbase + (offset))
+#define tve_readl(offset)		readl_relaxed(tve->regbase + (offset))
 
-#define tve_dac_writel(offset, v)   writel_relaxed(v, tve->vdacbase + (offset))
-#define tve_dac_readl(offset)	readl_relaxed(tve->vdacbase + (offset))
+#define tve_dac_writel(offset, v)	writel_relaxed(v, tve->vdacbase + (offset))
+#define tve_dac_readl(offset)		readl_relaxed(tve->vdacbase + (offset))
 
-#define connector_to_tve(x) container_of(x, struct rockchip_tve, connector)
-#define encoder_to_tve(x) container_of(x, struct rockchip_tve, encoder)
+#define tve_dac_grf_writel(offset, v)	regmap_write(tve->dac_grf, offset, v)
+#define tve_dac_grf_readl(offset, v)	regmap_read(tve->dac_grf, offset, v)
+
+#define connector_to_tve(x)		container_of(x, struct rockchip_tve, connector)
+#define encoder_to_tve(x)		container_of(x, struct rockchip_tve, encoder)
+
+struct rockchip_tve_data {
+	int input_format;
+	int soc_type;
+};
 
 static int
 rockchip_tve_get_modes(struct drm_connector *connector)
@@ -99,7 +110,7 @@ static void tve_set_mode(struct rockchip_tve *tve)
 	int mode = tve->tv_format;
 
 	dev_dbg(tve->dev, "tve set mode:%d\n", mode);
-	if (tve->inputformat == INPUT_FORMAT_RGB)
+	if (tve->input_format == INPUT_FORMAT_RGB)
 		tve_writel(TV_CTRL, v_CVBS_MODE(mode) | v_CLK_UPSTREAM_EN(2) |
 			   v_TIMING_EN(2) | v_LUMA_FILTER_GAIN(0) |
 			   v_LUMA_FILTER_UPSAMPLE(1) | v_CSC_PATH(0));
@@ -164,17 +175,38 @@ static void dac_init(struct rockchip_tve *tve)
 
 static void dac_enable(struct rockchip_tve *tve, bool enable)
 {
-	u32 val;
+	u32 mask = 0;
+	u32 val = 0;
+	u32 grfreg = 0;
 
 	if (enable) {
 		dev_dbg(tve->dev, "dac enable\n");
-		val = 0x70;
+
+		mask = m_VBG_EN | m_DAC_EN | m_DAC_GAIN;
+		if (tve->soc_type == SOC_RK3036) {
+			val = m_VBG_EN | m_DAC_EN | v_DAC_GAIN(tve->daclevel);
+			grfreg = RK3036_GRF_SOC_CON3;
+		} else if (tve->soc_type == SOC_RK312X) {
+			val = m_VBG_EN | m_DAC_EN | v_DAC_GAIN(tve->daclevel);
+			grfreg = RK312X_GRF_TVE_CON;
+		} else if (tve->soc_type == SOC_RK322X || tve->soc_type == SOC_RK3328) {
+			val = v_CUR_REG(tve->dac1level) | v_DR_PWR_DOWN(0) | v_BG_PWR_DOWN(0);
+		}
 	} else {
 		dev_dbg(tve->dev, "dac disable\n");
-		val = v_CUR_REG(0x7) | m_DR_PWR_DOWN | m_BG_PWR_DOWN;
+
+		mask = m_VBG_EN | m_DAC_EN;
+		if (tve->soc_type == SOC_RK312X)
+			grfreg = RK312X_GRF_TVE_CON;
+		else if (tve->soc_type == SOC_RK3036)
+			grfreg = RK3036_GRF_SOC_CON3;
+		else if (tve->soc_type == SOC_RK322X || tve->soc_type == SOC_RK3328)
+			val = v_CUR_REG(tve->dac1level) | m_DR_PWR_DOWN | m_BG_PWR_DOWN;
 	}
 
-	if (tve->vdacbase)
+	if (grfreg)
+		tve_dac_grf_writel(grfreg, (mask << 16) | val);
+	else if (tve->vdacbase)
 		tve_dac_writel(VDAC_VDAC1, val);
 }
 
@@ -375,33 +407,37 @@ static int tve_parse_dt(struct device_node *np,
 		return -EINVAL;
 	} else {
 		tve->daclevel = val;
-		cell = nvmem_cell_get(tve->dev, "tve_dac_adj");
-		if (IS_ERR(cell)) {
-			dev_dbg(tve->dev,
-				"failed to get id cell: %ld\n", PTR_ERR(cell));
-		} else {
-			efuse_buf = nvmem_cell_read(cell, &len);
-			nvmem_cell_put(cell);
-			if (len == 1)
-				getdac = efuse_buf[0];
-			kfree(efuse_buf);
+		if (tve->soc_type == SOC_RK322X || tve->soc_type == SOC_RK3328) {
+			cell = nvmem_cell_get(tve->dev, "tve_dac_adj");
+			if (IS_ERR(cell)) {
+				dev_dbg(tve->dev, "failed to get id cell: %ld\n", PTR_ERR(cell));
+			} else {
+				efuse_buf = nvmem_cell_read(cell, &len);
+				nvmem_cell_put(cell);
+				if (IS_ERR(efuse_buf))
+					return PTR_ERR(efuse_buf);
+				if (len == 1)
+					getdac = efuse_buf[0];
+				kfree(efuse_buf);
 
-			if (getdac > 0) {
-				tve->daclevel =
-				getdac + 5 + val - RK322X_VDAC_STANDARD;
-				if (tve->daclevel > 0x3f) {
-					dev_err(tve->dev,
-						"rk322x daclevel error!\n");
-					tve->daclevel = val;
+				if (getdac > 0) {
+					tve->daclevel = getdac + 5 + val - RK322X_VDAC_STANDARD;
+					if (tve->daclevel > 0x3f) {
+						dev_err(tve->dev, "rk322x daclevel error!\n");
+						tve->daclevel = val;
+					}
 				}
 			}
 		}
 	}
 
-	ret = of_property_read_u32(np, "rockchip,dac1level", &val);
-	if ((val == 0) || (ret < 0))
-		return -EINVAL;
-	tve->dac1level = val;
+	if (tve->soc_type == SOC_RK322X || tve->soc_type == SOC_RK3328) {
+		ret = of_property_read_u32(np, "rockchip,dac1level", &val);
+		if ((val == 0) || (ret < 0))
+			return -EINVAL;
+		tve->dac1level = val;
+	}
+
 
 	return 0;
 }
@@ -410,11 +446,13 @@ static void check_uboot_logo(struct rockchip_tve *tve)
 {
 	int lumafilter0, lumafilter1, lumafilter2, vdac;
 
-	vdac = tve_dac_readl(VDAC_VDAC1);
-	/* Whether the dac power has been turned down. */
-	if (vdac & m_DR_PWR_DOWN) {
-		tve->connector.dpms = DRM_MODE_DPMS_OFF;
-		return;
+	if (tve->soc_type == SOC_RK322X || tve->soc_type == SOC_RK3328) {
+		vdac = tve_dac_readl(VDAC_VDAC1);
+		/* Whether the dac power has been turned down. */
+		if (vdac & m_DR_PWR_DOWN) {
+			tve->connector.dpms = DRM_MODE_DPMS_OFF;
+			return;
+		}
 	}
 
 	lumafilter0 = tve_readl(TV_LUMA_FILTER0);
@@ -432,14 +470,37 @@ static void check_uboot_logo(struct rockchip_tve *tve)
 		return;
 	}
 
-	dac_init(tve);
+	if (tve->soc_type == SOC_RK322X || tve->soc_type == SOC_RK3328)
+		dac_init(tve);
+
 	tve->connector.dpms = DRM_MODE_DPMS_OFF;
 }
 
+static const struct rockchip_tve_data rk3036_tve = {
+	.soc_type = SOC_RK3036,
+	.input_format = INPUT_FORMAT_RGB,
+};
+
+static const struct rockchip_tve_data rk312x_tve = {
+	.soc_type = SOC_RK312X,
+	.input_format = INPUT_FORMAT_RGB,
+};
+
+static const struct rockchip_tve_data rk322x_tve = {
+	.soc_type = SOC_RK322X,
+	.input_format = INPUT_FORMAT_YUV,
+};
+
+static const struct rockchip_tve_data rk3328_tve = {
+	.soc_type = SOC_RK3328,
+	.input_format = INPUT_FORMAT_YUV,
+};
+
 static const struct of_device_id rockchip_tve_dt_ids[] = {
-	{
-		.compatible = "rockchip,rk3328-tve",
-	},
+	{ .compatible = "rockchip,rk3036-tve", .data = &rk3036_tve },
+	{ .compatible = "rockchip,rk312x-tve", .data = &rk312x_tve },
+	{ .compatible = "rockchip,rk322x-tve", .data = &rk322x_tve },
+	{ .compatible = "rockchip,rk3328-tve", .data = &rk3328_tve },
 	{}
 };
 
@@ -452,6 +513,7 @@ static int rockchip_tve_bind(struct device *dev, struct device *master,
 	struct drm_device *drm_dev = data;
 	struct device_node *np = dev->of_node;
 	const struct of_device_id *match;
+	const struct rockchip_tve_data *tve_data;
 	struct rockchip_tve *tve;
 	struct resource *res;
 	struct drm_encoder *encoder;
@@ -469,11 +531,10 @@ static int rockchip_tve_bind(struct device *dev, struct device *master,
 	}
 
 	tve->dev = &pdev->dev;
-	if (!strcmp(match->compatible, "rockchip,rk3328-tve")) {
-		tve->inputformat = INPUT_FORMAT_YUV;
-	} else {
-		dev_err(tve->dev, "It is not a valid tv encoder! ");
-		return -ENOMEM;
+	tve_data = of_device_get_match_data(dev);
+	if (tve_data) {
+		tve->soc_type = tve_data->soc_type;
+		tve->input_format = tve_data->input_format;
 	}
 
 	ret = tve_parse_dt(np, tve);
@@ -483,7 +544,6 @@ static int rockchip_tve_bind(struct device *dev, struct device *master,
 	}
 
 	tve->enable = 0;
-	platform_set_drvdata(pdev, tve);
 	tve->drm_dev = drm_dev;
 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 	tve->reg_phy_base = res->start;
@@ -491,19 +551,36 @@ static int rockchip_tve_bind(struct device *dev, struct device *master,
 	tve->regbase = devm_ioremap(tve->dev, res->start, tve->len);
 	if (IS_ERR(tve->regbase)) {
 		dev_err(tve->dev,
-			"rk3328 tv encoder device map registers failed!");
+			"tv encoder device map registers failed!");
 		return PTR_ERR(tve->regbase);
 	}
 
-	res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
-	tve->len = resource_size(res);
-	tve->vdacbase = devm_ioremap(tve->dev, res->start, tve->len);
-	if (IS_ERR(tve->vdacbase)) {
-		dev_err(tve->dev,
-			"rk3328 tv encoder device dac map registers failed!");
-		return PTR_ERR(tve->vdacbase);
+	if (tve->soc_type == SOC_RK322X || tve->soc_type == SOC_RK3328) {
+		res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+		tve->len = resource_size(res);
+		tve->vdacbase = devm_ioremap(tve->dev, res->start, tve->len);
+		if (IS_ERR(tve->vdacbase)) {
+			dev_err(tve->dev, "tv encoder device dac map registers failed!");
+			return PTR_ERR(tve->vdacbase);
+		}
 	}
 
+	if (tve->soc_type == SOC_RK3036) {
+		tve->aclk = devm_clk_get(tve->dev, "aclk");
+		if (IS_ERR(tve->aclk)) {
+			dev_err(tve->dev, "Unable to get tve aclk\n");
+			return PTR_ERR(tve->aclk);
+		}
+
+		ret = clk_prepare_enable(tve->aclk);
+		if (ret) {
+			dev_err(tve->dev, "Cannot enable tve aclk: %d\n", ret);
+			return ret;
+		}
+	}
+
+	tve->dac_grf = syscon_regmap_lookup_by_phandle(dev->of_node, "rockchip,grf");
+
 	mutex_init(&tve->suspend_lock);
 	check_uboot_logo(tve);
 	tve->tv_format = TVOUT_CVBS_PAL;
@@ -516,7 +593,7 @@ static int rockchip_tve_bind(struct device *dev, struct device *master,
 			       DRM_MODE_ENCODER_TVDAC, NULL);
 	if (ret < 0) {
 		dev_err(tve->dev, "failed to initialize encoder with drm\n");
-		return ret;
+		goto err_disable_aclk;
 	}
 
 	drm_encoder_helper_add(encoder, &rockchip_tve_encoder_helper_funcs);
@@ -544,6 +621,7 @@ static int rockchip_tve_bind(struct device *dev, struct device *master,
 	rockchip_drm_register_sub_dev(&tve->sub_dev);
 
 	pm_runtime_enable(dev);
+	dev_set_drvdata(dev, tve);
 	dev_dbg(tve->dev, "%s tv encoder probe ok\n", match->compatible);
 
 	return 0;
@@ -552,6 +630,10 @@ err_free_connector:
 	drm_connector_cleanup(connector);
 err_free_encoder:
 	drm_encoder_cleanup(encoder);
+err_disable_aclk:
+	if (tve->soc_type == SOC_RK3036)
+		clk_disable_unprepare(tve->aclk);
+
 	return ret;
 }
 
@@ -567,6 +649,7 @@ static void rockchip_tve_unbind(struct device *dev, struct device *master,
 	drm_encoder_cleanup(&tve->encoder);
 
 	pm_runtime_disable(dev);
+	dev_set_drvdata(dev, NULL);
 }
 
 static const struct component_ops rockchip_tve_component_ops = {
@@ -585,6 +668,9 @@ static void rockchip_tve_shutdown(struct platform_device *pdev)
 {
 	struct rockchip_tve *tve = dev_get_drvdata(&pdev->dev);
 
+	if (!tve)
+		return;
+
 	mutex_lock(&tve->suspend_lock);
 
 	dev_dbg(tve->dev, "tve shutdown\n");
diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_tve.h b/drivers/gpu/drm/rockchip/rockchip_drm_tve.h
index cd0bcb1a32fc..e7d3acc3fd52 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_tve.h
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_tve.h
@@ -15,6 +15,9 @@
 #ifndef __ROCKCHIP_DRM_TVE_H__
 #define __ROCKCHIP_DRM_TVE_H__
 
+#define RK3036_GRF_SOC_CON3	0x0154
+#define RK312X_GRF_TVE_CON	0x0170
+
 #define TV_CTRL			(0x00)
 	#define m_CVBS_MODE			BIT(24)
 	#define m_CLK_UPSTREAM_EN		(3 << 18)
@@ -129,6 +132,13 @@ enum {
 	INPUT_FORMAT_YUV
 };
 
+enum {
+	SOC_RK3036 = 0,
+	SOC_RK312X,
+	SOC_RK322X,
+	SOC_RK3328
+};
+
 #define grf_writel(offset, v)	do { \
 	writel_relaxed(v, RK_GRF_VIRT + (offset)); \
 	dsb(sy); \
@@ -143,10 +153,13 @@ struct rockchip_tve {
 	u32 tv_format;
 	void __iomem			*regbase;
 	void __iomem			*vdacbase;
+	struct clk			*aclk;
 	struct clk			*dac_clk;
+	struct regmap			*dac_grf;
 	u32				reg_phy_base;
 	u32				len;
-	int				inputformat;
+	int				input_format;
+	int				soc_type;
 	bool				enable;
 	u32 test_mode;
 	u32 saturation;
diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
index 9cbb35c289de..d7ea1f80ea12 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
@@ -826,11 +826,22 @@ static void scl_vop_cal_scl_fac(struct vop *vop, const struct vop_win *win,
 	uint16_t lb_mode;
 	uint32_t val;
 	const struct vop_data *vop_data = vop->data;
+	struct drm_display_mode *adjusted_mode = &vop->rockchip_crtc.crtc.state->adjusted_mode;
 	int vskiplines;
 
 	if (!win->phy->scl)
 		return;
 
+	if ((adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) && vop->version == VOP_VERSION(2, 2)) {
+		VOP_SCL_SET(vop, win, scale_yrgb_x, ((src_w << 12) / dst_w));
+		VOP_SCL_SET(vop, win, scale_yrgb_y, ((src_h << 12) / dst_h));
+		if (is_yuv) {
+			VOP_SCL_SET(vop, win, scale_cbcr_x, ((cbcr_src_w << 12) / dst_w));
+			VOP_SCL_SET(vop, win, scale_cbcr_y, ((cbcr_src_h << 12) / dst_h));
+		}
+		return;
+	}
+
 	if (!(vop_data->feature & VOP_FEATURE_ALPHA_SCALE)) {
 		if (is_alpha_support(pixel_format) &&
 		    (src_w != dst_w || src_h != dst_h))
@@ -2011,6 +2022,8 @@ static void vop_plane_atomic_update(struct drm_plane *plane,
 			dsp_h = 4;
 		actual_h = dsp_h * actual_h / drm_rect_height(dest);
 	}
+	if ((adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) && vop->version == VOP_VERSION(2, 2))
+		dsp_h = dsp_h / 2;
 
 	act_info = (actual_h - 1) << 16 | ((actual_w - 1) & 0xffff);
 
@@ -2019,6 +2032,8 @@ static void vop_plane_atomic_update(struct drm_plane *plane,
 
 	dsp_stx = dest->x1 + mode->crtc_htotal - mode->crtc_hsync_start;
 	dsp_sty = dest->y1 + mode->crtc_vtotal - mode->crtc_vsync_start;
+	if ((adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) && vop->version == VOP_VERSION(2, 2))
+		dsp_sty = dest->y1 / 2 + mode->crtc_vtotal - mode->crtc_vsync_start;
 	dsp_st = dsp_sty << 16 | (dsp_stx & 0xffff);
 
 	s = to_rockchip_crtc_state(crtc->state);
@@ -2046,7 +2061,7 @@ static void vop_plane_atomic_update(struct drm_plane *plane,
 
 	if (win->phy->scl)
 		scl_vop_cal_scl_fac(vop, win, actual_w, actual_h,
-				    drm_rect_width(dest), drm_rect_height(dest),
+				    drm_rect_width(dest), dsp_h,
 				    fb->format->format);
 
 	if (VOP_WIN_SUPPORT(vop, win, color_key))
diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
index bedf2a99a793..280faffeded9 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
@@ -254,6 +254,7 @@ struct vop_ctrl {
 	struct vop_reg post_scl_factor;
 	struct vop_reg post_scl_ctrl;
 	struct vop_reg dsp_interlace;
+	struct vop_reg dsp_interlace_pol;
 	struct vop_reg global_regdone_en;
 	struct vop_reg auto_gate_en;
 	struct vop_reg post_lb_mode;
diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
index 7ea5a356e16e..c61598e28dbe 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
@@ -1488,6 +1488,9 @@ static inline void rk3568_vop2_cfg_done(struct drm_crtc *crtc)
 	 * This is rather low probability for miss some done bit.
 	 */
 	val |= vop2_readl(vop2, RK3568_REG_CFG_DONE) & 0x7;
+
+	rockchip_drm_dbg(vop2->dev, VOP_DEBUG_CFG_DONE, "cfg_done: 0x%x\n", val);
+
 	vop2_writel(vop2, 0, val);
 
 	/**
@@ -1513,6 +1516,8 @@ static inline void rk3588_vop2_cfg_done(struct drm_crtc *crtc)
 	if (vcstate->splice_mode)
 		val |= BIT(vp_data->splice_vp_id) | (BIT(vp_data->splice_vp_id) << 16);
 
+	rockchip_drm_dbg(vop2->dev, VOP_DEBUG_CFG_DONE, "cfg_done: 0x%x\n", val);
+
 	vop2_writel(vop2, 0, val);
 }
 
@@ -3156,8 +3161,10 @@ static void vop2_wb_commit(struct drm_crtc *crtc)
 	if (conn_state->writeback_job && conn_state->writeback_job->fb) {
 		struct drm_framebuffer *fb = conn_state->writeback_job->fb;
 
-		DRM_DEV_DEBUG(vop2->dev, "Enable wb %ux%u  fmt: %u pitches: %d  addr: %pad\n",
-			      fb->width, fb->height, wb_state->format, fb->pitches[0], &wb_state->yrgb_addr);
+		rockchip_drm_dbg(vop2->dev, VOP_DEBUG_WB,
+				 "Enable wb %ux%u fmt: %u pitches: %d addr: %pad\n",
+				 fb->width, fb->height, wb_state->format,
+				 fb->pitches[0], &wb_state->yrgb_addr);
 
 		drm_writeback_queue_job(wb_conn, conn_state);
 		conn_state->writeback_job = NULL;
@@ -4611,7 +4618,8 @@ static void vop2_plane_atomic_disable(struct drm_plane *plane, struct drm_plane_
 	struct vop2_plane_state *vpstate = to_vop2_plane_state(plane->state);
 #endif
 
-	DRM_DEV_DEBUG(vop2->dev, "%s disable\n", win->name);
+	rockchip_drm_dbg(vop2->dev, VOP_DEBUG_PLANE, "%s disable %s\n",
+			 win->name, current->comm);
 
 	if (!old_state->crtc)
 		return;
@@ -4896,11 +4904,12 @@ static void vop2_win_atomic_update(struct vop2_win *win, struct drm_rect *src, s
 
 	vop2_win_enable(win);
 	spin_lock(&vop2->reg_lock);
-	DRM_DEV_DEBUG(vop2->dev, "vp%d update %s[%dx%d->%dx%d@(%d, %d)] fmt[%.4s%s] addr[%pad]\n",
-		      vp->id, win->name, actual_w, actual_h, dsp_w, dsp_h,
-		      dsp_stx, dsp_sty,
-		      drm_get_format_name(fb->format->format, &format_name),
-		      modifier_to_string(fb->modifier), &vpstate->yrgb_mst);
+	rockchip_drm_dbg(vop2->dev, VOP_DEBUG_PLANE,
+			 "vp%d update %s[%dx%d->%dx%d@(%d, %d)] fmt[%.4s%s] addr[%pad] by %s\n",
+			 vp->id, win->name, actual_w, actual_h, dsp_w, dsp_h,
+			 dsp_stx, dsp_sty,
+			 drm_get_format_name(fb->format->format, &format_name),
+			 modifier_to_string(fb->modifier), &vpstate->yrgb_mst, current->comm);
 
 	if (vop2->version != VOP_VERSION_RK3568)
 		rk3588_vop2_win_cfg_axi(win);
@@ -8478,8 +8487,8 @@ static void vop2_crtc_atomic_begin(struct drm_crtc *crtc, struct drm_crtc_state
 		vop2_zpos[nr_layers].zpos = vpstate->zpos;
 		vop2_zpos[nr_layers].plane = plane;
 
-		DRM_DEV_DEBUG(vop2->dev, "%s active zpos:%d for vp%d from vp%d\n",
-			     win->name, vpstate->zpos, vp->id, old_vp->id);
+		rockchip_drm_dbg(vop2->dev, VOP_DEBUG_OVERLAY, "%s active zpos:%d for vp%d from vp%d\n",
+				 win->name, vpstate->zpos, vp->id, old_vp->id);
 		/* left and right win may have different number */
 		if (vcstate->splice_mode) {
 			splice_win = vop2_find_win_by_phys_id(vop2, win->splice_win_id);
@@ -8512,8 +8521,8 @@ static void vop2_crtc_atomic_begin(struct drm_crtc *crtc, struct drm_crtc_state
 	}
 	vp->hdr10_at_splice_mode = hdr10_at_splice_mode;
 
-	DRM_DEV_DEBUG(vop2->dev, "vp%d: %d windows, active layers %d\n",
-		      vp->id, hweight32(vp->win_mask), nr_layers);
+	rockchip_drm_dbg(vop2->dev, VOP_DEBUG_OVERLAY, "vp%d: %d windows, active layers %d\n",
+			 vp->id, hweight32(vp->win_mask), nr_layers);
 	if (nr_layers) {
 		vp->nr_layers = nr_layers;
 
@@ -9345,6 +9354,7 @@ static irqreturn_t vop2_isr(int irq, void *data)
 		}
 
 		if (active_irqs & FS_FIELD_INTR) {
+			rockchip_drm_dbg(vop2->dev, VOP_DEBUG_VSYNC, "vsync_vp%d\n", vp->id);
 			vop2_wb_handler(vp);
 			if (likely(!vp->skip_vsync) || (vp->layer_sel_update == false)) {
 				drm_crtc_handle_vblank(crtc);
diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
index ba43530af653..e47f5e865537 100644
--- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
+++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
@@ -1239,19 +1239,27 @@ static const struct vop_intr rk3036_intr = {
 
 static const struct vop_ctrl rk3036_ctrl_data = {
 	.standby = VOP_REG(RK3036_SYS_CTRL, 0x1, 30),
+	.sw_dac_sel = VOP_REG(RK3036_SYS_CTRL, 0x1, 29),
 	.out_mode = VOP_REG(RK3036_DSP_CTRL0, 0xf, 0),
+	.dsp_interlace = VOP_REG(RK3036_DSP_CTRL0, 0x1, 12),
 	.dsp_blank = VOP_REG(RK3036_DSP_CTRL1, 0x1, 24),
+	.dsp_background = VOP_REG(RK3036_DSP_CTRL1, 0xffffff, 0),
 	.dclk_pol = VOP_REG(RK3036_DSP_CTRL0, 0x1, 7),
 	.pin_pol = VOP_REG(RK3036_DSP_CTRL0, 0x7, 4),
 	.dither_down_sel = VOP_REG(RK3036_DSP_CTRL0, 0x1, 27),
+	.tve_sw_mode = VOP_REG(RK3036_DSP_CTRL0, 0x1, 25),
+	.dsp_interlace_pol = VOP_REG(RK3036_DSP_CTRL0, 0x1, 13),
 	.dither_down_en = VOP_REG(RK3036_DSP_CTRL0, 0x1, 11),
 	.dither_down_mode = VOP_REG(RK3036_DSP_CTRL0, 0x1, 10),
 	.dither_up_en = VOP_REG(RK3036_DSP_CTRL0, 0x1, 9),
 	.dsp_layer_sel = VOP_REG(RK3036_DSP_CTRL0, 0x1, 8),
 	.htotal_pw = VOP_REG(RK3036_DSP_HTOTAL_HS_END, 0x1fff1fff, 0),
 	.hact_st_end = VOP_REG(RK3036_DSP_HACT_ST_END, 0x1fff1fff, 0),
+	.tve_dclk_en = VOP_REG(RK3036_AXI_BUS_CTRL, 0x1, 20),
+	.tve_dclk_pol = VOP_REG(RK3036_AXI_BUS_CTRL, 0x1, 21),
 	.hdmi_en = VOP_REG(RK3036_AXI_BUS_CTRL, 0x1, 22),
 	.hdmi_dclk_pol = VOP_REG(RK3036_AXI_BUS_CTRL, 0x1, 23),
+	.core_dclk_div = VOP_REG(RK3036_AXI_BUS_CTRL, 0x1, 30),
 	.hdmi_pin_pol = VOP_REG(RK3036_INT_SCALER, 0x7, 4),
 	.rgb_en = VOP_REG(RK3036_AXI_BUS_CTRL, 0x1, 24),
 	.rgb_dclk_pol = VOP_REG(RK3036_AXI_BUS_CTRL, 0x1, 25),
@@ -1261,6 +1269,8 @@ static const struct vop_ctrl rk3036_ctrl_data = {
 	.mipi_dclk_pol = VOP_REG(RK3036_AXI_BUS_CTRL, 0x1, 29),
 	.vtotal_pw = VOP_REG(RK3036_DSP_VTOTAL_VS_END, 0x1fff1fff, 0),
 	.vact_st_end = VOP_REG(RK3036_DSP_VACT_ST_END, 0x1fff1fff, 0),
+	.vs_st_end_f1 = VOP_REG(RK3036_DSP_VS_ST_END_F1, 0x1fff1fff, 0),
+	.vact_st_end_f1 = VOP_REG(RK3036_DSP_VACT_ST_END_F1, 0x1fff1fff, 0),
 	.cfg_done = VOP_REG(RK3036_REG_CFG_DONE, 0x1, 0),
 };
 
diff --git a/drivers/iommu/rockchip-iommu.c b/drivers/iommu/rockchip-iommu.c
index 5d22c575b295..541fbf22ce56 100644
--- a/drivers/iommu/rockchip-iommu.c
+++ b/drivers/iommu/rockchip-iommu.c
@@ -1960,12 +1960,16 @@ static void rk_iommu_shutdown(struct platform_device *pdev)
 	struct rk_iommu *iommu = platform_get_drvdata(pdev);
 	int i;
 
+	if (iommu->skip_read)
+		goto skip_free_irq;
+
 	for (i = 0; i < iommu->num_irq; i++) {
 		int irq = platform_get_irq(pdev, i);
 
 		devm_free_irq(iommu->dev, irq, iommu);
 	}
 
+skip_free_irq:
 	pm_runtime_force_suspend(&pdev->dev);
 }
 
diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c
index fb1bcf832482..3e54ca29e1b8 100644
--- a/drivers/irqchip/irq-gic-v3-its.c
+++ b/drivers/irqchip/irq-gic-v3-its.c
@@ -163,6 +163,7 @@ struct its_device {
 	struct its_node		*its;
 	struct event_lpi_map	event_map;
 	void			*itt;
+	u32			itt_sz;
 	u32			nr_ites;
 	u32			device_id;
 	bool			shared;
@@ -3430,9 +3431,13 @@ static struct its_device *its_create_device(struct its_node *its, u32 dev_id,
 	sz = nr_ites * (FIELD_GET(GITS_TYPER_ITT_ENTRY_SIZE, its->typer) + 1);
 	sz = max(sz, ITS_ITT_ALIGN) + ITS_ITT_ALIGN - 1;
 	gfp_flags = GFP_KERNEL;
-	if (of_machine_is_compatible("rockchip,rk3568") || of_machine_is_compatible("rockchip,rk3566"))
+	if (of_machine_is_compatible("rockchip,rk3568") || of_machine_is_compatible("rockchip,rk3566")) {
 		gfp_flags |= GFP_DMA32;
-	itt = kzalloc_node(sz, gfp_flags, its->numa_node);
+		itt = (void *)__get_free_pages(gfp_flags, get_order(sz));
+	} else {
+		itt = kzalloc_node(sz, gfp_flags, its->numa_node);
+	}
+
 	if (alloc_lpis) {
 		lpi_map = its_lpi_alloc(nvecs, &lpi_base, &nr_lpis);
 		if (lpi_map)
@@ -3446,7 +3451,13 @@ static struct its_device *its_create_device(struct its_node *its, u32 dev_id,
 
 	if (!dev || !itt ||  !col_map || (!lpi_map && alloc_lpis)) {
 		kfree(dev);
-		kfree(itt);
+
+		if (of_machine_is_compatible("rockchip,rk3568") ||
+		    of_machine_is_compatible("rockchip,rk3566"))
+			free_pages((unsigned long)itt, get_order(sz));
+		else
+			kfree(itt);
+
 		kfree(lpi_map);
 		kfree(col_map);
 		return NULL;
@@ -3456,6 +3467,7 @@ static struct its_device *its_create_device(struct its_node *its, u32 dev_id,
 
 	dev->its = its;
 	dev->itt = itt;
+	dev->itt_sz = sz;
 	dev->nr_ites = nr_ites;
 	dev->event_map.lpi_map = lpi_map;
 	dev->event_map.col_map = col_map;
@@ -3483,7 +3495,13 @@ static void its_free_device(struct its_device *its_dev)
 	list_del(&its_dev->entry);
 	raw_spin_unlock_irqrestore(&its_dev->its->lock, flags);
 	kfree(its_dev->event_map.col_map);
-	kfree(its_dev->itt);
+
+	if (of_machine_is_compatible("rockchip,rk3568") ||
+	    of_machine_is_compatible("rockchip,rk3566"))
+		free_pages((unsigned long)its_dev->itt, get_order(its_dev->itt_sz));
+	else
+		kfree(its_dev->itt);
+
 	kfree(its_dev);
 }
 
diff --git a/drivers/media/i2c/Kconfig b/drivers/media/i2c/Kconfig
index a94efb9a6bc0..f4981e72c46d 100644
--- a/drivers/media/i2c/Kconfig
+++ b/drivers/media/i2c/Kconfig
@@ -368,6 +368,17 @@ config VIDEO_LT6911UXC
 	  To compile this driver as a module, choose M here: the
 	  module will be called lt6911uxc.
 
+config VIDEO_LT6911UXE
+	tristate "Lontium LT6911UXE decoder"
+	depends on VIDEO_V4L2 && I2C && VIDEO_V4L2_SUBDEV_API
+	select HDMI
+	select V4L2_FWNODE
+	help
+	  Support for the Lontium LT6911UXE series HDMI to MIPI CSI-2 bridge.
+
+	  To compile this driver as a module, choose M here: the
+	  module will be called lt6911uxe.
+
 config VIDEO_LT7911D
 	tristate "Lontium LT7911D decoder"
 	depends on VIDEO_V4L2 && I2C && VIDEO_V4L2_SUBDEV_API
@@ -920,6 +931,17 @@ config VIDEO_GC08A3
 	  To compile this driver as a module, choose M here: the
 	  module will be called gc08a3.
 
+config VIDEO_GC1084
+	tristate "GalaxyCore GC1084 sensor support"
+	depends on I2C && VIDEO_V4L2 && VIDEO_V4L2_SUBDEV_API
+	depends on MEDIA_CAMERA_SUPPORT
+	select V4L2_FWNODE
+	help
+	  Support for the GalaxyCore GC1084 sensor.
+
+	  To compile this driver as a module, choose M here: the
+	  module will be called gc1084.
+
 config VIDEO_GC2053
 	tristate "GalaxyCore GC2053 sensor support"
 	depends on I2C && VIDEO_V4L2 && VIDEO_V4L2_SUBDEV_API
diff --git a/drivers/media/i2c/Makefile b/drivers/media/i2c/Makefile
index a366d81e5197..6d11fdfa478f 100644
--- a/drivers/media/i2c/Makefile
+++ b/drivers/media/i2c/Makefile
@@ -155,6 +155,7 @@ obj-$(CONFIG_VIDEO_LM3560)	+= lm3560.o
 obj-$(CONFIG_VIDEO_LM3646)	+= lm3646.o
 obj-$(CONFIG_VIDEO_SGM3784)	+= sgm3784.o
 obj-$(CONFIG_VIDEO_LT6911UXC)	+= lt6911uxc.o
+obj-$(CONFIG_VIDEO_LT6911UXE)	+= lt6911uxe.o
 obj-$(CONFIG_VIDEO_IT6616)	+= it6616.o
 obj-$(CONFIG_VIDEO_LT7911D)	+= lt7911d.o
 obj-$(CONFIG_VIDEO_LT7911UXC)	+= lt7911uxc.o
@@ -173,6 +174,7 @@ obj-$(CONFIG_VIDEO_RK628)	+= rk628/
 obj-$(CONFIG_VIDEO_AR0230)	+= ar0230.o
 obj-$(CONFIG_VIDEO_GC02M2)	+= gc02m2.o
 obj-$(CONFIG_VIDEO_GC08A3)	+= gc08a3.o
+obj-$(CONFIG_VIDEO_GC1084)	+= gc1084.o
 obj-$(CONFIG_VIDEO_GC2053)	+= gc2053.o
 obj-$(CONFIG_VIDEO_GC2093)	+= gc2093.o
 obj-$(CONFIG_VIDEO_GC2145)	+= gc2145.o
diff --git a/drivers/media/i2c/gc1084.c b/drivers/media/i2c/gc1084.c
new file mode 100644
index 000000000000..d91da4fb401d
--- /dev/null
+++ b/drivers/media/i2c/gc1084.c
@@ -0,0 +1,1275 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * gc1084 sensor driver
+ *
+ * Copyright (C) 2022 Rockchip Electronics Co., Ltd.
+ *
+ * V0.0X01.0X00 first version.
+ * V0.0X01.0X01 Add HDR support.
+ * V0.0X01.0X02 update sensor driver
+ * 1. fix linear mode ae flicker issue.
+ * 2. add hdr mode exposure limit issue.
+ * 3. fix hdr mode highlighting pink issue.
+ * 4. add some debug info.
+ */
+//#define DEBUG
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/gpio/consumer.h>
+#include <linux/i2c.h>
+#include <linux/module.h>
+#include <linux/pm_runtime.h>
+#include <linux/of_graph.h>
+#include <linux/regmap.h>
+#include <linux/regulator/consumer.h>
+#include <linux/version.h>
+#include <linux/rk-camera-module.h>
+#include <linux/rk-preisp.h>
+
+#include <media/v4l2-async.h>
+#include <media/media-entity.h>
+#include <media/v4l2-ctrls.h>
+#include <media/v4l2-device.h>
+#include <media/v4l2-fwnode.h>
+#include <media/v4l2-subdev.h>
+
+#define DRIVER_VERSION		KERNEL_VERSION(0, 0x01, 0x02)
+#define GC1084_NAME		"gc1084"
+#define GC1084_MEDIA_BUS_FMT	MEDIA_BUS_FMT_SGRBG10_1X10
+
+#define MIPI_FREQ_400M		400000000
+
+#define GC1084_XVCLK_FREQ	27000000
+
+#define GC1084_REG_CHIP_ID_H	0x03F0
+#define GC1084_REG_CHIP_ID_L	0x03F1
+
+#define GC1084_REG_EXP_H	0x0d03
+#define GC1084_REG_EXP_L	0x0d04
+
+#define GC1084_REG_VTS_H	0x0000
+#define GC1084_REG_VTS_L	0x0001
+
+#define GC1084_REG_CTRL_MODE	0x003E
+#define GC1084_MODE_SW_STANDBY	0x11
+#define GC1084_MODE_STREAMING	0x91
+
+#define GC1084_CHIP_ID		0x1084
+
+#define GC1084_VTS_MAX		0x3FFF
+#define GC1084_HTS_MAX		0xFFF
+
+#define GC1084_EXPOSURE_MAX	0x3FFF
+#define GC1084_EXPOSURE_MIN	1
+#define GC1084_EXPOSURE_STEP	1
+
+#define GC1084_GAIN_MIN		0x40
+#define GC1084_GAIN_MAX		0x2000
+#define GC1084_GAIN_STEP	1
+#define GC1084_GAIN_DEFAULT	64
+#define REG_NULL		0xFFFF
+
+#define GC1084_LANES		1
+
+static const char * const gc1084_supply_names[] = {
+	"dovdd",    /* Digital I/O power */
+	"avdd",     /* Analog power */
+	"dvdd",     /* Digital power */
+};
+
+#define GC1084_NUM_SUPPLIES ARRAY_SIZE(gc1084_supply_names)
+
+#define to_gc1084(sd) container_of(sd, struct gc1084, subdev)
+
+enum {
+	LINK_FREQ_400M_INDEX,
+};
+
+struct gain_reg_config {
+	u32 value;
+	u16 analog_gain;
+	u16 col_gain;
+	u16 reserved;
+};
+
+struct gc1084_mode {
+	u32 width;
+	u32 height;
+	struct v4l2_fract max_fps;
+	u32 hts_def;
+	u32 vts_def;
+	u32 exp_def;
+	u32 link_freq_index;
+	const struct reg_sequence *reg_list;
+	u32 reg_num;
+	u32 hdr_mode;
+	u32 vc[PAD_MAX];
+};
+
+struct gc1084 {
+	struct device	*dev;
+	struct clk	*xvclk;
+	struct regmap	*regmap;
+	struct gpio_desc *reset_gpio;
+	struct gpio_desc *pwdn_gpio;
+	struct regulator_bulk_data supplies[GC1084_NUM_SUPPLIES];
+
+	struct v4l2_subdev  subdev;
+	struct media_pad    pad;
+	struct v4l2_ctrl_handler ctrl_handler;
+	struct v4l2_ctrl    *exposure;
+	struct v4l2_ctrl    *anal_gain;
+	struct v4l2_ctrl    *hblank;
+	struct v4l2_ctrl    *vblank;
+	struct v4l2_ctrl    *h_flip;
+	struct v4l2_ctrl    *v_flip;
+	struct v4l2_ctrl    *link_freq;
+	struct v4l2_ctrl    *pixel_rate;
+
+	struct mutex        lock;
+	bool		    streaming;
+	bool		    power_on;
+	unsigned int        cfg_num;
+	const struct gc1084_mode *cur_mode;
+
+	u32		module_index;
+	const char      *module_facing;
+	const char      *module_name;
+	const char      *len_name;
+	u32		cur_vts;
+
+	bool			  has_init_exp;
+	struct preisp_hdrae_exp_s init_hdrae_exp;
+};
+
+static const struct regmap_config gc1084_regmap_config = {
+	.reg_bits = 16,
+	.val_bits = 8,
+	.max_register = 0x1000,
+};
+
+static const s64 link_freq_menu_items[] = {
+	MIPI_FREQ_400M,
+};
+
+/*
+ * window size=1280*720 mipi@1lane
+ * mclk=27M mipi_clk=400Mbps
+ * pixel_line_total=2200 line_frame_total=1125
+ * row_time=44.4444us frame_rate=30fps
+ */
+static const struct reg_sequence gc1084_1280x720_liner_settings[] = {
+	{0x03fe, 0xf0},
+	{0x03fe, 0xf0},
+	{0x03fe, 0xf0},
+	{0x03fe, 0x00},
+	{0x03f2, 0x00},
+	{0x03f3, 0x00},
+	{0x03f4, 0x36},
+	{0x03f5, 0xc0},
+	{0x03f6, 0x13},
+	{0x03f7, 0x01},
+	{0x03f8, 0x32},
+	{0x03f9, 0x21},
+	{0x03fc, 0xae},
+	{0x0d05, 0x08},
+	{0x0d06, 0xae},
+	{0x0d08, 0x10},
+	{0x0d0a, 0x02},
+	{0x000c, 0x03},
+	{0x0d0d, 0x02},
+	{0x0d0e, 0xd4},
+	{0x000f, 0x05},
+	{0x0010, 0x08},
+	{0x0017, 0x08},
+	{0x0d73, 0x92},
+	{0x0076, 0x00},
+	{0x0d76, 0x00},
+	{0x0d41, 0x02},
+	{0x0d42, 0xee},
+	{0x0d7a, 0x0a},
+	{0x006b, 0x18},
+	{0x0db0, 0x9d},
+	{0x0db1, 0x00},
+	{0x0db2, 0xac},
+	{0x0db3, 0xd5},
+	{0x0db4, 0x00},
+	{0x0db5, 0x97},
+	{0x0db6, 0x09},
+	{0x00d2, 0xfc},
+	{0x0d19, 0x31},
+	{0x0d20, 0x40},
+	{0x0d25, 0xcb},
+	{0x0d27, 0x03},
+	{0x0d29, 0x40},
+	{0x0d43, 0x20},
+	{0x0058, 0x60},
+	{0x00d6, 0x66},
+	{0x00d7, 0x19},
+	{0x0093, 0x02},
+	{0x00d9, 0x14},
+	{0x00da, 0xc1},
+	{0x0d2a, 0x00},
+	{0x0d28, 0x04},
+	{0x0dc2, 0x84},
+	{0x0050, 0x30},
+	{0x0080, 0x07},
+	{0x008c, 0x05},
+	{0x008d, 0xa8},
+	{0x0077, 0x01},
+	{0x0078, 0xee},
+	{0x0079, 0x02},
+	{0x0067, 0xc0},
+	{0x0054, 0xff},
+	{0x0055, 0x02},
+	{0x0056, 0x00},
+	{0x0057, 0x04},
+	{0x005a, 0xff},
+	{0x005b, 0x07},
+	{0x00d5, 0x03},
+	{0x0102, 0xa9},
+	{0x0d03, 0x02},
+	{0x0d04, 0xd0},
+	{0x007a, 0x60},
+	{0x04e0, 0xff},
+	{0x0414, 0x75},
+	{0x0415, 0x75},
+	{0x0416, 0x75},
+	{0x0417, 0x75},
+	{0x0122, 0x00},
+	{0x0121, 0x80},
+	{0x0428, 0x10},
+	{0x0429, 0x10},
+	{0x042a, 0x10},
+	{0x042b, 0x10},
+	{0x042c, 0x14},
+	{0x042d, 0x14},
+	{0x042e, 0x18},
+	{0x042f, 0x18},
+	{0x0430, 0x05},
+	{0x0431, 0x05},
+	{0x0432, 0x05},
+	{0x0433, 0x05},
+	{0x0434, 0x05},
+	{0x0435, 0x05},
+	{0x0436, 0x05},
+	{0x0437, 0x05},
+	{0x0153, 0x00},
+	{0x0190, 0x01},
+	{0x0192, 0x02},
+	{0x0194, 0x04},
+	{0x0195, 0x02},
+	{0x0196, 0xd0},
+	{0x0197, 0x05},
+	{0x0198, 0x00},
+	{0x0201, 0x23},
+	{0x0202, 0x53},
+	{0x0203, 0xce},
+	{0x0208, 0x39},
+	{0x0212, 0x06},
+	{0x0213, 0x40},
+	{0x0215, 0x12},
+	{0x0229, 0x05},
+	{0x023e, 0x98},
+	{0x031e, 0x3e},
+};
+
+static const struct gc1084_mode supported_modes[] = {
+	{
+		.width = 1280,
+		.height = 720,
+		.max_fps = {
+			.numerator = 10000,
+			.denominator = 300000,
+		},
+		.exp_def = 0x460,
+		.hts_def = 0x898,
+		.vts_def = 0x465,
+		.link_freq_index = LINK_FREQ_400M_INDEX,
+		.reg_list = gc1084_1280x720_liner_settings,
+		.reg_num = ARRAY_SIZE(gc1084_1280x720_liner_settings),
+		.hdr_mode = NO_HDR,
+		.vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
+	},
+};
+
+/* pixel rate = link frequency * 2 * lanes / BITS_PER_SAMPLE */
+/* * 2, to match suitable isp freq */
+static u64 to_pixel_rate(u32 index)
+{
+	u64 pixel_rate = link_freq_menu_items[index] * 2 * GC1084_LANES * 2;
+
+	do_div(pixel_rate, 10);
+
+	return pixel_rate;
+}
+
+static inline int gc1084_read_reg(struct gc1084 *gc1084, u16 addr, u8 *value)
+{
+	unsigned int val;
+	int ret;
+
+	ret = regmap_read(gc1084->regmap, addr, &val);
+	if (ret) {
+		dev_err(gc1084->dev, "i2c read failed at addr: %x\n", addr);
+		return ret;
+	}
+
+	*value = val & 0xff;
+
+	return 0;
+}
+
+static inline int gc1084_write_reg(struct gc1084 *gc1084, u16 addr, u8 value)
+{
+	int ret;
+
+	ret = regmap_write(gc1084->regmap, addr, value);
+	if (ret) {
+		dev_err(gc1084->dev, "i2c write failed at addr: %x\n", addr);
+		return ret;
+	}
+
+	return ret;
+}
+
+static const struct gain_reg_config gain_reg_configs[] = {
+	{  64, 0x0000, 0x0100, 0x0080},
+	{  76, 0x0a00, 0x010b, 0x0080},
+	{  90, 0x0001, 0x0119, 0x0080},
+	{ 106, 0x0a01, 0x012a, 0x0080},
+	{ 128, 0x0002, 0x0200, 0x0080},
+	{ 152, 0x0a02, 0x0217, 0x0080},
+	{ 179, 0x0003, 0x0233, 0x0080},
+	{ 212, 0x0a03, 0x0314, 0x0080},
+	{ 256, 0x0004, 0x0400, 0x0090},
+	{ 303, 0x0a04, 0x042f, 0x0090},
+	{ 358, 0x0005, 0x0526, 0x0090},
+	{ 425, 0x0a05, 0x0628, 0x0090},
+	{ 512, 0x0006, 0x0800, 0x00a0},
+	{ 607, 0x0a06, 0x091e, 0x00a0},
+	{ 716, 0x1246, 0x0b0c, 0x00a0},
+	{ 848, 0x1966, 0x0d10, 0x00a0},
+	{1024, 0x4004, 0x1000, 0x00a0},
+	{1214, 0x4a04, 0x123d, 0x00a0},
+	{1434, 0x4005, 0x1619, 0x00b0},
+	{1699, 0x4a05, 0x1a23, 0x00c0},
+	{2048, 0x4006, 0x2000, 0x00c0},
+	{2427, 0x4a06, 0x253b, 0x00c0},
+	{2865, 0x5246, 0x2c30, 0x00c0},
+	{3393, 0x5946, 0x3501, 0x00d0},
+	{4096, 0x6006, 0x3f3f, 0x00e0},
+};
+
+static int gc1084_set_gain(struct gc1084 *gc1084, u32 gain)
+{
+	int ret, i = 0;
+	u16 pre_gain = 0;
+
+	for (i = 0; i < ARRAY_SIZE(gain_reg_configs) - 1; i++)
+		if ((gain_reg_configs[i].value <= gain) && (gain < gain_reg_configs[i+1].value))
+			break;
+
+	ret = gc1084_write_reg(gc1084, 0x00d1, (gain_reg_configs[i].analog_gain >> 8) & 0x3f);
+	ret |= gc1084_write_reg(gc1084, 0x00d0, gain_reg_configs[i].analog_gain & 0xff);
+
+	ret |= gc1084_write_reg(gc1084, 0x031d, 0x2e);
+
+	ret |= gc1084_write_reg(gc1084, 0x0dc1, (gain_reg_configs[i].analog_gain >> 14) & 1);
+
+	ret |= gc1084_write_reg(gc1084, 0x031d, 0x28);
+
+	ret |= gc1084_write_reg(gc1084, 0x0155, gain_reg_configs[i].reserved & 0xff);
+
+	ret |= gc1084_write_reg(gc1084, 0x00b8, gain_reg_configs[i].col_gain >> 8);
+	ret |= gc1084_write_reg(gc1084, 0x00b9, gain_reg_configs[i].col_gain & 0xff);
+
+	pre_gain = 64 * gain / gain_reg_configs[i].value;
+
+	ret |= gc1084_write_reg(gc1084, 0x00b1, (pre_gain >> 6));
+	ret |= gc1084_write_reg(gc1084, 0x00b2, ((pre_gain & 0x3f) << 2));
+
+	return ret;
+}
+
+static int gc1084_set_ctrl(struct v4l2_ctrl *ctrl)
+{
+	struct gc1084 *gc1084 = container_of(ctrl->handler,
+					     struct gc1084, ctrl_handler);
+	s64 max;
+	int ret = 0;
+	u32 vts = 0;
+
+	/* Propagate change of current control to all related controls */
+	switch (ctrl->id) {
+	case V4L2_CID_VBLANK:
+		/* Update max exposure while meeting expected vblanking */
+		max = gc1084->cur_mode->height + ctrl->val - 4;
+		__v4l2_ctrl_modify_range(gc1084->exposure,
+					 gc1084->exposure->minimum, max,
+					 gc1084->exposure->step,
+					 gc1084->exposure->default_value);
+		break;
+	}
+	if (!pm_runtime_get_if_in_use(gc1084->dev))
+		return 0;
+
+	switch (ctrl->id) {
+	case V4L2_CID_EXPOSURE:
+		if (gc1084->cur_mode->hdr_mode != NO_HDR)
+			goto ctrl_end;
+		dev_dbg(gc1084->dev, "set exposure value 0x%x\n", ctrl->val);
+		ret = gc1084_write_reg(gc1084, GC1084_REG_EXP_H,
+				       (ctrl->val >> 8) & 0x3f);
+		ret |= gc1084_write_reg(gc1084, GC1084_REG_EXP_L,
+					ctrl->val & 0xff);
+		break;
+	case V4L2_CID_ANALOGUE_GAIN:
+		if (gc1084->cur_mode->hdr_mode != NO_HDR)
+			goto ctrl_end;
+		dev_dbg(gc1084->dev, "set gain value 0x%x\n", ctrl->val);
+		gc1084_set_gain(gc1084, ctrl->val);
+		break;
+	case V4L2_CID_VBLANK:
+		vts = gc1084->cur_mode->height + ctrl->val;
+		gc1084->cur_vts = vts;
+		ret = gc1084_write_reg(gc1084, GC1084_REG_VTS_H,
+				       (vts >> 8) & 0x3f);
+		ret |= gc1084_write_reg(gc1084, GC1084_REG_VTS_L,
+					vts & 0xff);
+		dev_dbg(gc1084->dev, " set blank value 0x%x\n", ctrl->val);
+		break;
+	default:
+		dev_warn(gc1084->dev, "%s Unhandled id:0x%x, val:0x%x\n",
+			 __func__, ctrl->id, ctrl->val);
+		break;
+	}
+
+ctrl_end:
+	pm_runtime_put(gc1084->dev);
+	return ret;
+}
+
+static const struct v4l2_ctrl_ops gc1084_ctrl_ops = {
+	.s_ctrl = gc1084_set_ctrl,
+};
+
+static int gc1084_get_regulators(struct gc1084 *gc1084)
+{
+	unsigned int i;
+
+	for (i = 0; i < GC1084_NUM_SUPPLIES; i++)
+		gc1084->supplies[i].supply = gc1084_supply_names[i];
+
+	return devm_regulator_bulk_get(gc1084->dev,
+				       GC1084_NUM_SUPPLIES,
+				       gc1084->supplies);
+}
+
+static int gc1084_initialize_controls(struct gc1084 *gc1084)
+{
+	const struct gc1084_mode *mode;
+	struct v4l2_ctrl_handler *handler;
+	s64 exposure_max, vblank_def;
+	u32 h_blank;
+	int ret;
+
+	handler = &gc1084->ctrl_handler;
+	mode = gc1084->cur_mode;
+	ret = v4l2_ctrl_handler_init(handler, 8);
+	if (ret)
+		return ret;
+	handler->lock = &gc1084->lock;
+
+	gc1084->link_freq = v4l2_ctrl_new_int_menu(handler, NULL, V4L2_CID_LINK_FREQ,
+						   ARRAY_SIZE(link_freq_menu_items) - 1, 0,
+						   link_freq_menu_items);
+
+	gc1084->pixel_rate = v4l2_ctrl_new_std(handler, NULL, V4L2_CID_PIXEL_RATE,
+					       0, to_pixel_rate(LINK_FREQ_400M_INDEX),
+					       1, to_pixel_rate(LINK_FREQ_400M_INDEX));
+
+	h_blank = mode->hts_def - mode->width;
+	gc1084->hblank = v4l2_ctrl_new_std(handler, NULL, V4L2_CID_HBLANK,
+					   h_blank, h_blank, 1, h_blank);
+	if (gc1084->hblank)
+		gc1084->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
+
+	vblank_def = mode->vts_def - mode->height;
+	gc1084->cur_vts = mode->vts_def;
+	gc1084->vblank = v4l2_ctrl_new_std(handler, &gc1084_ctrl_ops,
+					   V4L2_CID_VBLANK, vblank_def,
+					   GC1084_VTS_MAX - mode->height,
+					   1, vblank_def);
+
+	exposure_max = mode->vts_def - 4;
+	gc1084->exposure = v4l2_ctrl_new_std(handler, &gc1084_ctrl_ops,
+					     V4L2_CID_EXPOSURE, GC1084_EXPOSURE_MIN,
+					     exposure_max, GC1084_EXPOSURE_STEP,
+					     mode->exp_def);
+
+	gc1084->anal_gain = v4l2_ctrl_new_std(handler, &gc1084_ctrl_ops,
+					      V4L2_CID_ANALOGUE_GAIN, GC1084_GAIN_MIN,
+					      GC1084_GAIN_MAX, GC1084_GAIN_STEP,
+					      GC1084_GAIN_DEFAULT);
+
+	gc1084->h_flip = v4l2_ctrl_new_std(handler, &gc1084_ctrl_ops,
+					   V4L2_CID_HFLIP, 0, 1, 1, 0);
+
+	gc1084->v_flip = v4l2_ctrl_new_std(handler, &gc1084_ctrl_ops,
+					   V4L2_CID_VFLIP, 0, 1, 1, 0);
+
+	if (handler->error) {
+		ret = handler->error;
+		dev_err(gc1084->dev, "Failed to init controls(%d)\n", ret);
+		goto err_free_handler;
+	}
+
+	gc1084->subdev.ctrl_handler = handler;
+	gc1084->has_init_exp = false;
+
+	return 0;
+
+err_free_handler:
+	v4l2_ctrl_handler_free(handler);
+	return ret;
+}
+
+static int __gc1084_power_on(struct gc1084 *gc1084)
+{
+	int ret;
+	struct device *dev = gc1084->dev;
+
+	ret = clk_set_rate(gc1084->xvclk, GC1084_XVCLK_FREQ);
+	if (ret < 0)
+		dev_warn(dev, "Failed to set xvclk rate\n");
+
+	if (clk_get_rate(gc1084->xvclk) != GC1084_XVCLK_FREQ)
+		dev_warn(dev, "xvclk mismatched, modes are based on 27MHz\n");
+
+	ret = clk_prepare_enable(gc1084->xvclk);
+	if (ret < 0) {
+		dev_err(dev, "Failed to enable xvclk\n");
+		return ret;
+	}
+
+	ret = regulator_bulk_enable(GC1084_NUM_SUPPLIES, gc1084->supplies);
+	if (ret < 0) {
+		dev_err(dev, "Failed to enable regulators\n");
+		goto disable_clk;
+	}
+
+	if (!IS_ERR(gc1084->reset_gpio))
+		gpiod_set_value_cansleep(gc1084->reset_gpio, 1);
+
+	usleep_range(1000, 2000);
+
+	if (!IS_ERR(gc1084->pwdn_gpio))
+		gpiod_set_value_cansleep(gc1084->pwdn_gpio, 1);
+	if (!IS_ERR(gc1084->reset_gpio))
+		gpiod_set_value_cansleep(gc1084->reset_gpio, 0);
+
+	usleep_range(10000, 20000);
+
+	return 0;
+
+disable_clk:
+	clk_disable_unprepare(gc1084->xvclk);
+	return ret;
+}
+
+static void __gc1084_power_off(struct gc1084 *gc1084)
+{
+	if (!IS_ERR(gc1084->reset_gpio))
+		gpiod_set_value_cansleep(gc1084->reset_gpio, 1);
+	if (!IS_ERR(gc1084->pwdn_gpio))
+		gpiod_set_value_cansleep(gc1084->pwdn_gpio, 0);
+
+	regulator_bulk_disable(GC1084_NUM_SUPPLIES, gc1084->supplies);
+	clk_disable_unprepare(gc1084->xvclk);
+}
+
+static int gc1084_check_sensor_id(struct gc1084 *gc1084)
+{
+	u8 id_h = 0, id_l = 0;
+	u16 id = 0;
+	int ret = 0;
+
+	ret = gc1084_read_reg(gc1084, GC1084_REG_CHIP_ID_H, &id_h);
+	ret |= gc1084_read_reg(gc1084, GC1084_REG_CHIP_ID_L, &id_l);
+	if (ret) {
+		dev_err(gc1084->dev, "Failed to read sensor id, (%d)\n", ret);
+		return ret;
+	}
+
+	id = id_h << 8 | id_l;
+	if (id != GC1084_CHIP_ID) {
+		dev_err(gc1084->dev, "sensor id: %04X mismatched\n", id);
+		return -ENODEV;
+	}
+
+	dev_info(gc1084->dev, "Detected GC1084 sensor\n");
+	return 0;
+}
+
+static void gc1084_get_module_inf(struct gc1084 *gc1084,
+				  struct rkmodule_inf *inf)
+{
+	memset(inf, 0, sizeof(*inf));
+	strlcpy(inf->base.lens, gc1084->len_name, sizeof(inf->base.lens));
+	strlcpy(inf->base.sensor, GC1084_NAME, sizeof(inf->base.sensor));
+	strlcpy(inf->base.module, gc1084->module_name, sizeof(inf->base.module));
+}
+
+static long gc1084_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
+{
+	struct gc1084 *gc1084 = to_gc1084(sd);
+	struct rkmodule_hdr_cfg *hdr_cfg;
+	long ret = 0;
+	u32 stream = 0;
+	u64 delay_us = 0;
+	u32 fps = 0;
+
+	switch (cmd) {
+	case RKMODULE_GET_HDR_CFG:
+		hdr_cfg = (struct rkmodule_hdr_cfg *)arg;
+		hdr_cfg->esp.mode = HDR_NORMAL_VC;
+		hdr_cfg->hdr_mode = gc1084->cur_mode->hdr_mode;
+		break;
+	case RKMODULE_GET_MODULE_INFO:
+		gc1084_get_module_inf(gc1084, (struct rkmodule_inf *)arg);
+		break;
+	case RKMODULE_SET_QUICK_STREAM:
+
+		stream = *((u32 *)arg);
+
+		if (stream) {
+			ret = gc1084_write_reg(gc1084, GC1084_REG_CTRL_MODE,
+				GC1084_MODE_STREAMING);
+		} else {
+			ret = gc1084_write_reg(gc1084, GC1084_REG_CTRL_MODE,
+				GC1084_MODE_SW_STANDBY);
+			fps = gc1084->cur_mode->max_fps.denominator /
+				  gc1084->cur_mode->max_fps.numerator;
+			delay_us = 1000000 / (gc1084->cur_mode->vts_def * fps / gc1084->cur_vts);
+			usleep_range(delay_us, delay_us + 2000);
+		}
+		break;
+	default:
+		ret = -ENOIOCTLCMD;
+		break;
+	}
+	return ret;
+}
+
+static int __gc1084_start_stream(struct gc1084 *gc1084)
+{
+	int ret;
+
+	ret = regmap_multi_reg_write(gc1084->regmap,
+				     gc1084->cur_mode->reg_list,
+				     gc1084->cur_mode->reg_num);
+	if (ret)
+		return ret;
+
+	/* Apply customized control from user */
+	mutex_unlock(&gc1084->lock);
+	v4l2_ctrl_handler_setup(&gc1084->ctrl_handler);
+	mutex_lock(&gc1084->lock);
+
+	if (gc1084->has_init_exp && gc1084->cur_mode->hdr_mode != NO_HDR) {
+		ret = gc1084_ioctl(&gc1084->subdev, PREISP_CMD_SET_HDRAE_EXP,
+				   &gc1084->init_hdrae_exp);
+		if (ret) {
+			dev_err(gc1084->dev, "init exp fail in hdr mode\n");
+			return ret;
+		}
+	}
+
+	return gc1084_write_reg(gc1084, GC1084_REG_CTRL_MODE,
+				GC1084_MODE_STREAMING);
+}
+
+static int __gc1084_stop_stream(struct gc1084 *gc1084)
+{
+	gc1084->has_init_exp = false;
+	return gc1084_write_reg(gc1084, GC1084_REG_CTRL_MODE,
+				GC1084_MODE_SW_STANDBY);
+}
+
+#ifdef CONFIG_COMPAT
+static long gc1084_compat_ioctl32(struct v4l2_subdev *sd,
+				  unsigned int cmd, unsigned long arg)
+{
+	void __user *up = compat_ptr(arg);
+	struct rkmodule_inf *inf;
+	struct rkmodule_hdr_cfg *hdr;
+	struct preisp_hdrae_exp_s *hdrae;
+	long ret = 0;
+	u32 stream = 0;
+
+	switch (cmd) {
+	case RKMODULE_GET_MODULE_INFO:
+		inf = kzalloc(sizeof(*inf), GFP_KERNEL);
+		if (!inf) {
+			ret = -ENOMEM;
+			return ret;
+		}
+
+		ret = gc1084_ioctl(sd, cmd, inf);
+		if (!ret) {
+			ret = copy_to_user(up, inf, sizeof(*inf));
+			if (ret)
+				ret = -EFAULT;
+		}
+		kfree(inf);
+		break;
+	case RKMODULE_GET_HDR_CFG:
+		hdr = kzalloc(sizeof(*hdr), GFP_KERNEL);
+		if (!hdr) {
+			ret = -ENOMEM;
+			return ret;
+		}
+
+		ret = gc1084_ioctl(sd, cmd, hdr);
+		if (!ret) {
+			ret = copy_to_user(up, hdr, sizeof(*hdr));
+			if (ret)
+				ret = -EFAULT;
+		}
+		kfree(hdr);
+		break;
+	case RKMODULE_SET_HDR_CFG:
+		hdr = kzalloc(sizeof(*hdr), GFP_KERNEL);
+		if (!hdr) {
+			ret = -ENOMEM;
+			return ret;
+		}
+
+		ret = copy_from_user(hdr, up, sizeof(*hdr));
+		if (!ret)
+			ret = gc1084_ioctl(sd, cmd, hdr);
+		else
+			ret = -EFAULT;
+		kfree(hdr);
+		break;
+	case PREISP_CMD_SET_HDRAE_EXP:
+		hdrae = kzalloc(sizeof(*hdrae), GFP_KERNEL);
+		if (!hdrae) {
+			ret = -ENOMEM;
+			return ret;
+		}
+
+		ret = copy_from_user(hdrae, up, sizeof(*hdrae));
+		if (!ret)
+			ret = gc1084_ioctl(sd, cmd, hdrae);
+		else
+			ret = -EFAULT;
+		kfree(hdrae);
+		break;
+	case RKMODULE_SET_QUICK_STREAM:
+		ret = copy_from_user(&stream, up, sizeof(u32));
+		if (!ret)
+			ret = gc1084_ioctl(sd, cmd, &stream);
+		else
+			ret = -EFAULT;
+		break;
+	default:
+		ret = -ENOIOCTLCMD;
+		break;
+	}
+	return ret;
+}
+#endif
+
+static int gc1084_s_stream(struct v4l2_subdev *sd, int on)
+{
+	struct gc1084 *gc1084 = to_gc1084(sd);
+	int ret = 0;
+	unsigned int fps;
+	unsigned int delay_us;
+
+	fps = DIV_ROUND_CLOSEST(gc1084->cur_mode->max_fps.denominator,
+					gc1084->cur_mode->max_fps.numerator);
+
+	dev_info(gc1084->dev, "%s: on: %d, %dx%d@%d\n", __func__, on,
+				gc1084->cur_mode->width,
+				gc1084->cur_mode->height,
+				fps);
+
+	mutex_lock(&gc1084->lock);
+	on = !!on;
+	if (on == gc1084->streaming)
+		goto unlock_and_return;
+
+	if (on) {
+		ret = pm_runtime_get_sync(gc1084->dev);
+		if (ret < 0) {
+			pm_runtime_put_noidle(gc1084->dev);
+			goto unlock_and_return;
+		}
+
+		ret = __gc1084_start_stream(gc1084);
+		if (ret) {
+			dev_err(gc1084->dev, "Failed to start gc1084 stream\n");
+			pm_runtime_put(gc1084->dev);
+			goto unlock_and_return;
+		}
+	} else {
+		__gc1084_stop_stream(gc1084);
+		/* delay to enable oneframe complete */
+		delay_us = 1000 * 1000 / fps;
+		usleep_range(delay_us, delay_us+10);
+		dev_info(gc1084->dev, "%s: on: %d, sleep(%dus)\n",
+				__func__, on, delay_us);
+
+		pm_runtime_put(gc1084->dev);
+	}
+
+	gc1084->streaming = on;
+
+unlock_and_return:
+	mutex_unlock(&gc1084->lock);
+	return 0;
+}
+
+static int gc1084_g_frame_interval(struct v4l2_subdev *sd,
+				   struct v4l2_subdev_frame_interval *fi)
+{
+	struct gc1084 *gc1084 = to_gc1084(sd);
+	const struct gc1084_mode *mode = gc1084->cur_mode;
+
+	mutex_lock(&gc1084->lock);
+	fi->interval = mode->max_fps;
+	mutex_unlock(&gc1084->lock);
+
+	return 0;
+}
+
+static int gc1084_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad_id,
+				struct v4l2_mbus_config *config)
+{
+	struct gc1084 *gc1084 = to_gc1084(sd);
+	u32 val = 1 << (GC1084_LANES - 1) | V4L2_MBUS_CSI2_CHANNEL_0 |
+		  V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
+
+	config->type = V4L2_MBUS_CSI2_DPHY;
+	config->flags = (gc1084->cur_mode->hdr_mode == NO_HDR) ?
+			val : (val | V4L2_MBUS_CSI2_CHANNEL_1);
+
+	return 0;
+}
+
+static int gc1084_enum_mbus_code(struct v4l2_subdev *sd,
+				 struct v4l2_subdev_pad_config *cfg,
+				 struct v4l2_subdev_mbus_code_enum *code)
+{
+	if (code->index != 0)
+		return -EINVAL;
+	code->code = GC1084_MEDIA_BUS_FMT;
+	return 0;
+}
+
+static int gc1084_enum_frame_sizes(struct v4l2_subdev *sd,
+				   struct v4l2_subdev_pad_config *cfg,
+				   struct v4l2_subdev_frame_size_enum *fse)
+{
+	struct gc1084 *gc1084 = to_gc1084(sd);
+
+	if (fse->index >= gc1084->cfg_num)
+		return -EINVAL;
+
+	if (fse->code != GC1084_MEDIA_BUS_FMT)
+		return -EINVAL;
+
+	fse->min_width  = supported_modes[fse->index].width;
+	fse->max_width  = supported_modes[fse->index].width;
+	fse->max_height = supported_modes[fse->index].height;
+	fse->min_height = supported_modes[fse->index].height;
+	return 0;
+}
+
+static int gc1084_enum_frame_interval(struct v4l2_subdev *sd,
+						  struct v4l2_subdev_pad_config *cfg,
+						  struct v4l2_subdev_frame_interval_enum *fie)
+{
+	struct gc1084 *gc1084 = to_gc1084(sd);
+
+	if (fie->index >= gc1084->cfg_num)
+		return -EINVAL;
+
+	fie->code = GC1084_MEDIA_BUS_FMT;
+	fie->width = supported_modes[fie->index].width;
+	fie->height = supported_modes[fie->index].height;
+	fie->interval = supported_modes[fie->index].max_fps;
+	fie->reserved[0] = supported_modes[fie->index].hdr_mode;
+	return 0;
+}
+
+static int gc1084_set_fmt(struct v4l2_subdev *sd,
+			  struct v4l2_subdev_pad_config *cfg,
+			  struct v4l2_subdev_format *fmt)
+{
+	struct gc1084 *gc1084 = to_gc1084(sd);
+	const struct gc1084_mode *mode;
+	s64 h_blank, vblank_def;
+
+	mutex_lock(&gc1084->lock);
+
+	mode = v4l2_find_nearest_size(supported_modes,
+				      ARRAY_SIZE(supported_modes),
+				      width, height,
+				      fmt->format.width, fmt->format.height);
+
+	fmt->format.code = GC1084_MEDIA_BUS_FMT;
+	fmt->format.width = mode->width;
+	fmt->format.height = mode->height;
+	fmt->format.field = V4L2_FIELD_NONE;
+	if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
+#ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
+		*v4l2_subdev_get_try_format(sd, cfg, fmt->pad) = fmt->format;
+#else
+		mutex_unlock(&gc1084->lock);
+		return -ENOTTY;
+#endif
+	} else {
+		gc1084->cur_mode = mode;
+		__v4l2_ctrl_s_ctrl(gc1084->link_freq, mode->link_freq_index);
+		__v4l2_ctrl_s_ctrl_int64(gc1084->pixel_rate,
+					 to_pixel_rate(mode->link_freq_index));
+		h_blank = mode->hts_def - mode->width;
+		__v4l2_ctrl_modify_range(gc1084->hblank, h_blank,
+					 h_blank, 1, h_blank);
+		vblank_def = mode->vts_def - mode->height;
+		__v4l2_ctrl_modify_range(gc1084->vblank, vblank_def,
+					 GC1084_VTS_MAX - mode->height,
+					 1, vblank_def);
+	}
+
+	mutex_unlock(&gc1084->lock);
+	return 0;
+}
+
+static int gc1084_get_fmt(struct v4l2_subdev *sd,
+			  struct v4l2_subdev_pad_config *cfg,
+			  struct v4l2_subdev_format *fmt)
+{
+	struct gc1084 *gc1084 = to_gc1084(sd);
+	const struct gc1084_mode *mode = gc1084->cur_mode;
+
+	mutex_lock(&gc1084->lock);
+	if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
+#ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
+		fmt->format = *v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
+#else
+		mutex_unlock(&gc1084->lock);
+		return -ENOTTY;
+#endif
+	} else {
+		fmt->format.width = mode->width;
+		fmt->format.height = mode->height;
+		fmt->format.code = GC1084_MEDIA_BUS_FMT;
+		fmt->format.field = V4L2_FIELD_NONE;
+
+		/* format info: width/height/data type/virctual channel */
+		if (fmt->pad < PAD_MAX && mode->hdr_mode != NO_HDR)
+			fmt->reserved[0] = mode->vc[fmt->pad];
+		else
+			fmt->reserved[0] = mode->vc[PAD0];
+
+	}
+	mutex_unlock(&gc1084->lock);
+	return 0;
+}
+
+#ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
+static int gc1084_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
+{
+	struct gc1084 *gc1084 = to_gc1084(sd);
+	struct v4l2_mbus_framefmt *try_fmt =
+				v4l2_subdev_get_try_format(sd, fh->pad, 0);
+	const struct gc1084_mode *def_mode = &supported_modes[0];
+
+	mutex_lock(&gc1084->lock);
+	/* Initialize try_fmt */
+	try_fmt->width = def_mode->width;
+	try_fmt->height = def_mode->height;
+	try_fmt->code = GC1084_MEDIA_BUS_FMT;
+	try_fmt->field = V4L2_FIELD_NONE;
+	mutex_unlock(&gc1084->lock);
+
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
+static const struct v4l2_subdev_internal_ops gc1084_internal_ops = {
+	.open = gc1084_open,
+};
+#endif
+
+static int gc1084_s_power(struct v4l2_subdev *sd, int on)
+{
+	struct gc1084 *gc1084 = to_gc1084(sd);
+	int ret = 0;
+
+	mutex_lock(&gc1084->lock);
+
+	if (gc1084->power_on == !!on)
+		goto unlock_and_return;
+
+	if (on) {
+		ret = pm_runtime_get_sync(gc1084->dev);
+		if (ret < 0) {
+			pm_runtime_put_noidle(gc1084->dev);
+			goto unlock_and_return;
+		}
+		gc1084->power_on = true;
+	} else {
+		pm_runtime_put(gc1084->dev);
+		gc1084->power_on = false;
+	}
+
+unlock_and_return:
+	mutex_unlock(&gc1084->lock);
+
+	return ret;
+}
+
+static const struct v4l2_subdev_core_ops gc1084_core_ops = {
+	.s_power = gc1084_s_power,
+	.ioctl = gc1084_ioctl,
+#ifdef CONFIG_COMPAT
+	.compat_ioctl32 = gc1084_compat_ioctl32,
+#endif
+};
+
+static const struct v4l2_subdev_video_ops gc1084_video_ops = {
+	.s_stream = gc1084_s_stream,
+	.g_frame_interval = gc1084_g_frame_interval,
+};
+
+static const struct v4l2_subdev_pad_ops gc1084_pad_ops = {
+	.enum_mbus_code = gc1084_enum_mbus_code,
+	.enum_frame_size = gc1084_enum_frame_sizes,
+	.enum_frame_interval = gc1084_enum_frame_interval,
+	.get_fmt = gc1084_get_fmt,
+	.set_fmt = gc1084_set_fmt,
+	.get_mbus_config = gc1084_g_mbus_config,
+};
+
+static const struct v4l2_subdev_ops gc1084_subdev_ops = {
+	.core   = &gc1084_core_ops,
+	.video  = &gc1084_video_ops,
+	.pad    = &gc1084_pad_ops,
+};
+
+static int gc1084_runtime_resume(struct device *dev)
+{
+	struct i2c_client *client = to_i2c_client(dev);
+	struct v4l2_subdev *sd = i2c_get_clientdata(client);
+	struct gc1084 *gc1084 = to_gc1084(sd);
+
+	__gc1084_power_on(gc1084);
+	return 0;
+}
+
+static int gc1084_runtime_suspend(struct device *dev)
+{
+	struct i2c_client *client = to_i2c_client(dev);
+	struct v4l2_subdev *sd = i2c_get_clientdata(client);
+	struct gc1084 *gc1084 = to_gc1084(sd);
+
+	__gc1084_power_off(gc1084);
+	return 0;
+}
+
+static const struct dev_pm_ops gc1084_pm_ops = {
+	SET_RUNTIME_PM_OPS(gc1084_runtime_suspend,
+			   gc1084_runtime_resume, NULL)
+};
+
+static int gc1084_probe(struct i2c_client *client,
+			 const struct i2c_device_id *id)
+{
+	struct device *dev = &client->dev;
+	struct device_node *node = dev->of_node;
+	struct gc1084 *gc1084;
+	struct v4l2_subdev *sd;
+	char facing[2];
+	int ret;
+
+	dev_info(dev, "driver version: %02x.%02x.%02x",
+		 DRIVER_VERSION >> 16,
+		 (DRIVER_VERSION & 0xff00) >> 8,
+		 DRIVER_VERSION & 0x00ff);
+
+	gc1084 = devm_kzalloc(dev, sizeof(*gc1084), GFP_KERNEL);
+	if (!gc1084)
+		return -ENOMEM;
+
+	gc1084->dev = dev;
+	gc1084->regmap = devm_regmap_init_i2c(client, &gc1084_regmap_config);
+	if (IS_ERR(gc1084->regmap)) {
+		dev_err(dev, "Failed to initialize I2C\n");
+		return -ENODEV;
+	}
+
+	ret = of_property_read_u32(node, RKMODULE_CAMERA_MODULE_INDEX,
+				   &gc1084->module_index);
+	ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_FACING,
+				       &gc1084->module_facing);
+	ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_NAME,
+				       &gc1084->module_name);
+	ret |= of_property_read_string(node, RKMODULE_CAMERA_LENS_NAME,
+				       &gc1084->len_name);
+	if (ret) {
+		dev_err(dev, "Failed to get module information\n");
+		return -EINVAL;
+	}
+
+	gc1084->xvclk = devm_clk_get(gc1084->dev, "xvclk");
+	if (IS_ERR(gc1084->xvclk)) {
+		dev_err(gc1084->dev, "Failed to get xvclk\n");
+		return -EINVAL;
+	}
+
+	gc1084->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
+	if (IS_ERR(gc1084->reset_gpio))
+		dev_warn(dev, "Failed to get reset-gpios\n");
+
+	gc1084->pwdn_gpio = devm_gpiod_get(dev, "pwdn", GPIOD_OUT_HIGH);
+	if (IS_ERR(gc1084->pwdn_gpio))
+		dev_warn(dev, "Failed to get pwdn-gpios\n");
+
+	ret = gc1084_get_regulators(gc1084);
+	if (ret) {
+		dev_err(dev, "Failed to get regulators\n");
+		return ret;
+	}
+
+	mutex_init(&gc1084->lock);
+
+	/* set default mode */
+	gc1084->cur_mode = &supported_modes[0];
+	gc1084->cfg_num = ARRAY_SIZE(supported_modes);
+	gc1084->cur_vts = gc1084->cur_mode->vts_def;
+
+	sd = &gc1084->subdev;
+	v4l2_i2c_subdev_init(sd, client, &gc1084_subdev_ops);
+	ret = gc1084_initialize_controls(gc1084);
+	if (ret)
+		goto err_destroy_mutex;
+
+	ret = __gc1084_power_on(gc1084);
+	if (ret)
+		goto err_free_handler;
+
+	ret = gc1084_check_sensor_id(gc1084);
+	if (ret)
+		goto err_power_off;
+
+#ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
+	sd->internal_ops = &gc1084_internal_ops;
+	sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
+#endif
+
+#ifdef CONFIG_MEDIA_CONTROLLER
+	gc1084->pad.flags = MEDIA_PAD_FL_SOURCE;
+	sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
+	ret = media_entity_pads_init(&sd->entity, 1, &gc1084->pad);
+	if (ret < 0)
+		goto err_power_off;
+#endif
+
+	memset(facing, 0, sizeof(facing));
+	if (strcmp(gc1084->module_facing, "back") == 0)
+		facing[0] = 'b';
+	else
+		facing[0] = 'f';
+
+	snprintf(sd->name, sizeof(sd->name), "m%02d_%s_%s %s",
+		 gc1084->module_index, facing,
+		 GC1084_NAME, dev_name(sd->dev));
+
+	ret = v4l2_async_register_subdev_sensor_common(sd);
+	if (ret) {
+		dev_err(dev, "Failed to register v4l2 async subdev\n");
+		goto err_clean_entity;
+	}
+
+	pm_runtime_set_active(dev);
+	pm_runtime_enable(dev);
+	pm_runtime_idle(dev);
+
+	return 0;
+
+err_clean_entity:
+#ifdef CONFIG_MEDIA_CONTROLLER
+	media_entity_cleanup(&sd->entity);
+#endif
+err_power_off:
+	__gc1084_power_off(gc1084);
+err_free_handler:
+	v4l2_ctrl_handler_free(&gc1084->ctrl_handler);
+err_destroy_mutex:
+	mutex_destroy(&gc1084->lock);
+
+	return ret;
+}
+
+static int gc1084_remove(struct i2c_client *client)
+{
+	struct v4l2_subdev *sd = i2c_get_clientdata(client);
+	struct gc1084 *gc1084 = to_gc1084(sd);
+
+	v4l2_async_unregister_subdev(sd);
+#ifdef CONFIG_MEDIA_CONTROLLER
+	media_entity_cleanup(&sd->entity);
+#endif
+	v4l2_ctrl_handler_free(&gc1084->ctrl_handler);
+	mutex_destroy(&gc1084->lock);
+
+	pm_runtime_disable(&client->dev);
+	if (!pm_runtime_status_suspended(&client->dev))
+		__gc1084_power_off(gc1084);
+	pm_runtime_set_suspended(&client->dev);
+	return 0;
+}
+
+static const struct i2c_device_id gc1084_match_id[] = {
+	{ "gc1084", 0 },
+	{ },
+};
+
+static const struct of_device_id gc1084_of_match[] = {
+	{ .compatible = "galaxycore,gc1084" },
+	{},
+};
+MODULE_DEVICE_TABLE(of, gc1084_of_match);
+
+static struct i2c_driver gc1084_i2c_driver = {
+	.driver = {
+		.name = GC1084_NAME,
+		.pm = &gc1084_pm_ops,
+		.of_match_table = of_match_ptr(gc1084_of_match),
+	},
+	.probe      = &gc1084_probe,
+	.remove     = &gc1084_remove,
+	.id_table   = gc1084_match_id,
+};
+
+static int __init sensor_mod_init(void)
+{
+	return i2c_add_driver(&gc1084_i2c_driver);
+}
+static void __exit sensor_mod_exit(void)
+{
+	i2c_del_driver(&gc1084_i2c_driver);
+}
+
+device_initcall_sync(sensor_mod_init);
+module_exit(sensor_mod_exit);
+
+MODULE_DESCRIPTION("Galaxycore GC1084 Image Sensor driver");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/media/i2c/gc2093.c b/drivers/media/i2c/gc2093.c
index 00018279b8b9..a85a2a696bab 100644
--- a/drivers/media/i2c/gc2093.c
+++ b/drivers/media/i2c/gc2093.c
@@ -32,6 +32,7 @@
 #include <media/v4l2-device.h>
 #include <media/v4l2-fwnode.h>
 #include <media/v4l2-subdev.h>
+#include "../platform/rockchip/isp/rkisp_tb_helper.h"
 
 #define DRIVER_VERSION		KERNEL_VERSION(0, 0x01, 0x02)
 #define GC2093_NAME		"gc2093"
@@ -148,9 +149,13 @@ struct gc2093 {
 	const char      *module_facing;
 	const char      *module_name;
 	const char      *len_name;
-	u32		cur_vts;
 
-	bool			  has_init_exp;
+	struct v4l2_fract	cur_fps;
+	u32			cur_vts;
+
+	bool			has_init_exp;
+	bool			is_thunderboot;
+	bool			is_first_streamoff;
 	struct preisp_hdrae_exp_s init_hdrae_exp;
 };
 
@@ -548,6 +553,14 @@ static int gc2093_set_gain(struct gc2093 *gc2093, u32 gain)
 	return ret;
 }
 
+static void gc2093_modify_fps_info(struct gc2093 *gc2093)
+{
+	const struct gc2093_mode *mode = gc2093->cur_mode;
+
+	gc2093->cur_fps.denominator = mode->max_fps.denominator * mode->vts_def /
+				      gc2093->cur_vts;
+}
+
 static int gc2093_set_ctrl(struct v4l2_ctrl *ctrl)
 {
 	struct gc2093 *gc2093 = container_of(ctrl->handler,
@@ -593,6 +606,8 @@ static int gc2093_set_ctrl(struct v4l2_ctrl *ctrl)
 				       (vts >> 8) & 0x3f);
 		ret |= gc2093_write_reg(gc2093, GC2093_REG_VTS_L,
 					vts & 0xff);
+		if (gc2093->cur_vts != gc2093->cur_mode->vts_def)
+			gc2093_modify_fps_info(gc2093);
 		dev_dbg(gc2093->dev, " set blank value 0x%x\n", ctrl->val);
 		break;
 	case V4L2_CID_HFLIP:
@@ -691,6 +706,8 @@ static int gc2093_initialize_controls(struct gc2093 *gc2093)
 
 	gc2093->subdev.ctrl_handler = handler;
 	gc2093->has_init_exp = false;
+	gc2093->cur_vts = mode->vts_def;
+	gc2093->cur_fps = mode->max_fps;
 
 	return 0;
 
@@ -717,6 +734,9 @@ static int __gc2093_power_on(struct gc2093 *gc2093)
 		return ret;
 	}
 
+	if (gc2093->is_thunderboot)
+		return 0;
+
 	ret = regulator_bulk_enable(GC2093_NUM_SUPPLIES, gc2093->supplies);
 	if (ret < 0) {
 		dev_err(dev, "Failed to enable regulators\n");
@@ -744,6 +764,16 @@ disable_clk:
 
 static void __gc2093_power_off(struct gc2093 *gc2093)
 {
+	clk_disable_unprepare(gc2093->xvclk);
+	if (gc2093->is_thunderboot) {
+		if (gc2093->is_first_streamoff) {
+			gc2093->is_thunderboot = false;
+			gc2093->is_first_streamoff = false;
+		} else {
+			return;
+		}
+	}
+
 	if (!IS_ERR(gc2093->reset_gpio))
 		gpiod_set_value_cansleep(gc2093->reset_gpio, 1);
 	if (!IS_ERR(gc2093->pwdn_gpio))
@@ -755,10 +785,16 @@ static void __gc2093_power_off(struct gc2093 *gc2093)
 
 static int gc2093_check_sensor_id(struct gc2093 *gc2093)
 {
+	struct device *dev = gc2093->dev;
 	u8 id_h = 0, id_l = 0;
 	u16 id = 0;
 	int ret = 0;
 
+	if (gc2093->is_thunderboot) {
+		dev_info(dev, "Enable thunderboot mode, skip sensor id check\n");
+		return 0;
+	}
+
 	ret = gc2093_read_reg(gc2093, GC2093_REG_CHIP_ID_H, &id_h);
 	ret |= gc2093_read_reg(gc2093, GC2093_REG_CHIP_ID_L, &id_l);
 	if (ret) {
@@ -899,6 +935,7 @@ static long gc2093_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
 						 GC2093_VTS_MAX - gc2093->cur_mode->height,
 						 1, h);
 			gc2093->cur_vts = gc2093->cur_mode->vts_def;
+			gc2093->cur_fps = gc2093->cur_mode->max_fps;
 			dev_info(gc2093->dev, "sensor mode: %d\n",
 				 gc2093->cur_mode->hdr_mode);
 		}
@@ -933,26 +970,27 @@ static int __gc2093_start_stream(struct gc2093 *gc2093)
 {
 	int ret;
 
-	ret = regmap_multi_reg_write(gc2093->regmap,
-				     gc2093->cur_mode->reg_list,
-				     gc2093->cur_mode->reg_num);
-	if (ret)
-		return ret;
-
-	/* Apply customized control from user */
-	mutex_unlock(&gc2093->lock);
-	v4l2_ctrl_handler_setup(&gc2093->ctrl_handler);
-	mutex_lock(&gc2093->lock);
-
-	if (gc2093->has_init_exp && gc2093->cur_mode->hdr_mode != NO_HDR) {
-		ret = gc2093_ioctl(&gc2093->subdev, PREISP_CMD_SET_HDRAE_EXP,
-				   &gc2093->init_hdrae_exp);
-		if (ret) {
-			dev_err(gc2093->dev, "init exp fail in hdr mode\n");
+	if (!gc2093->is_thunderboot) {
+		ret = regmap_multi_reg_write(gc2093->regmap,
+						gc2093->cur_mode->reg_list,
+						gc2093->cur_mode->reg_num);
+		if (ret)
 			return ret;
+
+		/* Apply customized control from user */
+		mutex_unlock(&gc2093->lock);
+		v4l2_ctrl_handler_setup(&gc2093->ctrl_handler);
+		mutex_lock(&gc2093->lock);
+
+		if (gc2093->has_init_exp && gc2093->cur_mode->hdr_mode != NO_HDR) {
+			ret = gc2093_ioctl(&gc2093->subdev, PREISP_CMD_SET_HDRAE_EXP,
+					&gc2093->init_hdrae_exp);
+			if (ret) {
+				dev_err(gc2093->dev, "init exp fail in hdr mode\n");
+				return ret;
+			}
 		}
 	}
-
 	return gc2093_write_reg(gc2093, GC2093_REG_CTRL_MODE,
 				GC2093_MODE_STREAMING);
 }
@@ -960,6 +998,10 @@ static int __gc2093_start_stream(struct gc2093 *gc2093)
 static int __gc2093_stop_stream(struct gc2093 *gc2093)
 {
 	gc2093->has_init_exp = false;
+	if (gc2093->is_thunderboot) {
+		gc2093->is_first_streamoff = true;
+		pm_runtime_put(gc2093->dev);
+	}
 	return gc2093_write_reg(gc2093, GC2093_REG_CTRL_MODE,
 				GC2093_MODE_SW_STANDBY);
 }
@@ -1070,6 +1112,10 @@ static int gc2093_s_stream(struct v4l2_subdev *sd, int on)
 		goto unlock_and_return;
 
 	if (on) {
+		if (gc2093->is_thunderboot && rkisp_tb_get_state() == RKISP_TB_NG) {
+			gc2093->is_thunderboot = false;
+			__gc2093_power_on(gc2093);
+		}
 		ret = pm_runtime_get_sync(gc2093->dev);
 		if (ret < 0) {
 			pm_runtime_put_noidle(gc2093->dev);
@@ -1211,6 +1257,8 @@ static int gc2093_set_fmt(struct v4l2_subdev *sd,
 		__v4l2_ctrl_modify_range(gc2093->vblank, vblank_def,
 					 GC2093_VTS_MAX - mode->height,
 					 1, vblank_def);
+		gc2093->cur_vts = mode->vts_def;
+		gc2093->cur_fps = mode->max_fps;
 	}
 
 	mutex_unlock(&gc2093->lock);
@@ -1395,17 +1443,19 @@ static int gc2093_probe(struct i2c_client *client,
 		return -EINVAL;
 	}
 
+	gc2093->is_thunderboot = IS_ENABLED(CONFIG_VIDEO_ROCKCHIP_THUNDER_BOOT_ISP);
+
 	gc2093->xvclk = devm_clk_get(gc2093->dev, "xvclk");
 	if (IS_ERR(gc2093->xvclk)) {
 		dev_err(gc2093->dev, "Failed to get xvclk\n");
 		return -EINVAL;
 	}
 
-	gc2093->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
+	gc2093->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_ASIS);
 	if (IS_ERR(gc2093->reset_gpio))
 		dev_warn(dev, "Failed to get reset-gpios\n");
 
-	gc2093->pwdn_gpio = devm_gpiod_get(dev, "pwdn", GPIOD_OUT_HIGH);
+	gc2093->pwdn_gpio = devm_gpiod_get(dev, "pwdn", GPIOD_ASIS);
 	if (IS_ERR(gc2093->pwdn_gpio))
 		dev_warn(dev, "Failed to get pwdn-gpios\n");
 
@@ -1467,7 +1517,10 @@ static int gc2093_probe(struct i2c_client *client,
 
 	pm_runtime_set_active(dev);
 	pm_runtime_enable(dev);
-	pm_runtime_idle(dev);
+	if (gc2093->is_thunderboot)
+		pm_runtime_get_sync(dev);
+	else
+		pm_runtime_idle(dev);
 
 	return 0;
 
@@ -1535,7 +1588,11 @@ static void __exit sensor_mod_exit(void)
 	i2c_del_driver(&gc2093_i2c_driver);
 }
 
+#if defined(CONFIG_VIDEO_ROCKCHIP_THUNDER_BOOT_ISP) && !defined(CONFIG_INITCALL_ASYNC)
+subsys_initcall(sensor_mod_init);
+#else
 device_initcall_sync(sensor_mod_init);
+#endif
 module_exit(sensor_mod_exit);
 
 MODULE_DESCRIPTION("Galaxycore GC2093 Image Sensor driver");
diff --git a/drivers/media/i2c/gc3003.c b/drivers/media/i2c/gc3003.c
index cf5c652141cc..6bfe04d5acc1 100644
--- a/drivers/media/i2c/gc3003.c
+++ b/drivers/media/i2c/gc3003.c
@@ -1332,10 +1332,10 @@ static int __gc3003_stop_stream(struct gc3003 *gc3003)
 	int ret;
 
 	gc3003->has_init_exp = false;
-
-	if (gc3003->is_thunderboot)
+	if (gc3003->is_thunderboot) {
 		gc3003->is_first_streamoff = true;
-
+		pm_runtime_put(&gc3003->client->dev);
+	}
 	ret = gc3003_write_array(gc3003->client, gc3003->cur_mode->stand_by_reg_list);
 
 	return ret;
@@ -1994,7 +1994,10 @@ static int gc3003_probe(struct i2c_client *client,
 
 	pm_runtime_set_active(dev);
 	pm_runtime_enable(dev);
-	pm_runtime_idle(dev);
+	if (gc3003->is_thunderboot)
+		pm_runtime_get_sync(dev);
+	else
+		pm_runtime_idle(dev);
 
 	return 0;
 
diff --git a/drivers/media/i2c/lt6911uxc.c b/drivers/media/i2c/lt6911uxc.c
index 86e2c93a0909..07ada7454eca 100644
--- a/drivers/media/i2c/lt6911uxc.c
+++ b/drivers/media/i2c/lt6911uxc.c
@@ -42,6 +42,12 @@
 
 #define I2C_MAX_XFER_SIZE		128
 
+#ifdef LT6911UXC_OUT_RGB
+#define LT6911UXC_MEDIA_BUS_FMT		MEDIA_BUS_FMT_BGR888_1X24
+#else
+#define LT6911UXC_MEDIA_BUS_FMT		MEDIA_BUS_FMT_UYVY8_2X8
+#endif
+
 static int debug;
 module_param(debug, int, 0644);
 MODULE_PARM_DESC(debug, "debug level (0-2)");
@@ -784,7 +790,7 @@ static int lt6911uxc_enum_mbus_code(struct v4l2_subdev *sd,
 {
 	switch (code->index) {
 	case 0:
-		code->code = MEDIA_BUS_FMT_UYVY8_2X8;
+		code->code = LT6911UXC_MEDIA_BUS_FMT;
 		break;
 
 	default:
@@ -801,7 +807,7 @@ static int lt6911uxc_enum_frame_sizes(struct v4l2_subdev *sd,
 	if (fse->index >= ARRAY_SIZE(supported_modes))
 		return -EINVAL;
 
-	if (fse->code != MEDIA_BUS_FMT_UYVY8_2X8)
+	if (fse->code != LT6911UXC_MEDIA_BUS_FMT)
 		return -EINVAL;
 
 	fse->min_width  = supported_modes[fse->index].width;
@@ -819,7 +825,7 @@ static int lt6911uxc_enum_frame_interval(struct v4l2_subdev *sd,
 	if (fie->index >= ARRAY_SIZE(supported_modes))
 		return -EINVAL;
 
-	if (fie->code != MEDIA_BUS_FMT_UYVY8_2X8)
+	if (fie->code != LT6911UXC_MEDIA_BUS_FMT)
 		return -EINVAL;
 
 	fie->width = supported_modes[fie->index].width;
@@ -897,7 +903,7 @@ static int lt6911uxc_set_fmt(struct v4l2_subdev *sd,
 		return ret;
 
 	switch (code) {
-	case MEDIA_BUS_FMT_UYVY8_2X8:
+	case LT6911UXC_MEDIA_BUS_FMT:
 		break;
 
 	default:
@@ -1295,7 +1301,7 @@ static int lt6911uxc_probe(struct i2c_client *client,
 	sd = &lt6911uxc->sd;
 	lt6911uxc->i2c_client = client;
 	lt6911uxc->cur_mode = &supported_modes[0];
-	lt6911uxc->mbus_fmt_code = MEDIA_BUS_FMT_UYVY8_2X8;
+	lt6911uxc->mbus_fmt_code = LT6911UXC_MEDIA_BUS_FMT;
 
 	err = lt6911uxc_parse_of(lt6911uxc);
 	if (err) {
diff --git a/drivers/media/i2c/lt6911uxe.c b/drivers/media/i2c/lt6911uxe.c
new file mode 100644
index 000000000000..1ec879b3d92b
--- /dev/null
+++ b/drivers/media/i2c/lt6911uxe.c
@@ -0,0 +1,1560 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2022 Rockchip Electronics Co. Ltd.
+ *
+ * lt6911uxe HDMI to MIPI CSI-2 bridge driver.
+ *
+ * Author: Jianwei Fan <jianwei.fan@rock-chips.com>
+ *
+ * V0.0X01.0X00 first version.
+ * V0.0X01.0X01 support DPHY 4K60.
+ * V0.0X01.0X02 support BGR888 format.
+ *
+ */
+// #define DEBUG
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/gpio/consumer.h>
+#include <linux/hdmi.h>
+#include <linux/i2c.h>
+#include <linux/interrupt.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of_graph.h>
+#include <linux/rk-camera-module.h>
+#include <linux/slab.h>
+#include <linux/timer.h>
+#include <linux/v4l2-dv-timings.h>
+#include <linux/version.h>
+#include <linux/videodev2.h>
+#include <linux/workqueue.h>
+#include <linux/compat.h>
+#include <media/v4l2-controls_rockchip.h>
+#include <media/v4l2-ctrls.h>
+#include <media/v4l2-device.h>
+#include <media/v4l2-dv-timings.h>
+#include <media/v4l2-event.h>
+#include <media/v4l2-fwnode.h>
+
+#define DRIVER_VERSION			KERNEL_VERSION(0, 0x01, 0x02)
+
+static int debug;
+module_param(debug, int, 0644);
+MODULE_PARM_DESC(debug, "debug level (0-3)");
+
+#define I2C_MAX_XFER_SIZE	128
+#define POLL_INTERVAL_MS	1000
+
+#define LT6911UXE_LINK_FREQ_HIGH	1250000000
+#define LT6911UXE_LINK_FREQ_MID		400000000
+#define LT6911UXE_LINK_FREQ_LOW		200000000
+#define LT6911UXE_PIXEL_RATE		800000000
+
+#define LT6911UXE_CHIPID	0x0221
+#define CHIPID_REGH		0xe101
+#define CHIPID_REGL		0xe100
+#define I2C_EN_REG		0xe0ee
+#define I2C_ENABLE		0x1
+#define I2C_DISABLE		0x0
+
+#define HTOTAL_H		0xe088
+#define HTOTAL_L		0xe089
+#define HACT_H			0xe08c
+#define HACT_L			0xe08d
+
+#define VTOTAL_H		0xe08a
+#define VTOTAL_L		0xe08b
+#define VACT_H			0xe08e
+#define VACT_L			0xe08f
+
+#define PCLK_H			0xe085
+#define PCLK_M			0xe086
+#define PCLK_L			0xe087
+
+#define BYTE_PCLK_H		0xe092
+#define BYTE_PCLK_M		0xe093
+#define BYTE_PCLK_L		0xe094
+
+#define AUDIO_FS_VALUE_H	0xe090
+#define AUDIO_FS_VALUE_L	0xe091
+
+#define LNAE_NUM		0xe095
+#define BUS_FMT			0xe096
+
+#define STREAM_CTL		0xe0b0
+#define ENABLE_STREAM		0x01
+#define DISABLE_STREAM		0x00
+
+// #define LT6911UXE_OUT_RGB
+#ifdef LT6911UXE_OUT_RGB
+#define LT6911UXE_MEDIA_BUS_FMT		MEDIA_BUS_FMT_BGR888_1X24
+#else
+#define LT6911UXE_MEDIA_BUS_FMT		MEDIA_BUS_FMT_UYVY8_2X8
+#endif
+
+#define LT6911UXE_NAME			"LT6911UXE"
+
+static const s64 link_freq_menu_items[] = {
+	LT6911UXE_LINK_FREQ_HIGH,
+	LT6911UXE_LINK_FREQ_MID,
+	LT6911UXE_LINK_FREQ_LOW,
+};
+
+struct lt6911uxe {
+	struct v4l2_fwnode_bus_mipi_csi2 bus;
+	struct v4l2_subdev sd;
+	struct media_pad pad;
+	struct v4l2_ctrl_handler hdl;
+	struct i2c_client *i2c_client;
+	struct mutex confctl_mutex;
+	struct v4l2_ctrl *detect_tx_5v_ctrl;
+	struct v4l2_ctrl *audio_sampling_rate_ctrl;
+	struct v4l2_ctrl *audio_present_ctrl;
+	struct v4l2_ctrl *link_freq;
+	struct v4l2_ctrl *pixel_rate;
+	struct delayed_work delayed_work_hotplug;
+	struct delayed_work delayed_work_res_change;
+	struct v4l2_dv_timings timings;
+	struct clk *xvclk;
+	struct gpio_desc *reset_gpio;
+	struct gpio_desc *plugin_det_gpio;
+	struct gpio_desc *power_gpio;
+	struct work_struct work_i2c_poll;
+	struct timer_list timer;
+	const char *module_facing;
+	const char *module_name;
+	const char *len_name;
+	const struct lt6911uxe_mode *cur_mode;
+	const struct lt6911uxe_mode *support_modes;
+	u32 cfg_num;
+	struct v4l2_fwnode_endpoint bus_cfg;
+	bool nosignal;
+	bool enable_hdcp;
+	bool is_audio_present;
+	bool power_on;
+	int plugin_irq;
+	u32 mbus_fmt_code;
+	u32 module_index;
+	u32 audio_sampling_rate;
+	int lane_in_use;
+};
+
+static const struct v4l2_dv_timings_cap lt6911uxe_timings_cap = {
+	.type = V4L2_DV_BT_656_1120,
+	.reserved = { 0 },
+	V4L2_INIT_BT_TIMINGS(1, 10000, 1, 10000, 0, 800000000,
+			V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |
+			V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT,
+			V4L2_DV_BT_CAP_PROGRESSIVE | V4L2_DV_BT_CAP_INTERLACED |
+			V4L2_DV_BT_CAP_REDUCED_BLANKING |
+			V4L2_DV_BT_CAP_CUSTOM)
+};
+
+struct lt6911uxe_mode {
+	u32 width;
+	u32 height;
+	struct v4l2_fract max_fps;
+	u32 hts_def;
+	u32 vts_def;
+	u32 exp_def;
+	u32 mipi_freq_idx;
+};
+
+static struct rkmodule_csi_dphy_param rk3588_dcphy_param = {
+	.vendor = PHY_VENDOR_SAMSUNG,
+	.lp_vol_ref = 3,
+	.lp_hys_sw = {0, 0, 0, 0},
+	.lp_escclk_pol_sel = {1, 0, 0, 0},
+	.skew_data_cal_clk = {0, 0, 0, 0},
+	.clk_hs_term_sel = 2,
+	.data_hs_term_sel = {2, 2, 2, 2},
+	.reserved = {0},
+};
+
+static const struct lt6911uxe_mode supported_modes_dphy[] = {
+	{
+		.width = 3840,
+		.height = 2160,
+		.max_fps = {
+			.numerator = 10000,
+			.denominator = 600000,
+		},
+		.hts_def = 4400,
+		.vts_def = 2250,
+		.mipi_freq_idx = 0,
+	}, {
+		.width = 1920,
+		.height = 1080,
+		.max_fps = {
+			.numerator = 10000,
+			.denominator = 600000,
+		},
+		.hts_def = 2200,
+		.vts_def = 1125,
+		.mipi_freq_idx = 1,
+	}, {
+		.width = 1280,
+		.height = 720,
+		.max_fps = {
+			.numerator = 10000,
+			.denominator = 600000,
+		},
+		.hts_def = 1650,
+		.vts_def = 750,
+		.mipi_freq_idx = 1,
+	}, {
+		.width = 720,
+		.height = 576,
+		.max_fps = {
+			.numerator = 10000,
+			.denominator = 500000,
+		},
+		.hts_def = 864,
+		.vts_def = 625,
+		.mipi_freq_idx = 2,
+	}, {
+		.width = 720,
+		.height = 480,
+		.max_fps = {
+			.numerator = 10000,
+			.denominator = 600000,
+		},
+		.hts_def = 858,
+		.vts_def = 525,
+		.mipi_freq_idx = 2,
+	},
+};
+
+static void lt6911uxe_format_change(struct v4l2_subdev *sd);
+static int lt6911uxe_s_ctrl_detect_tx_5v(struct v4l2_subdev *sd);
+static int lt6911uxe_s_dv_timings(struct v4l2_subdev *sd,
+				struct v4l2_dv_timings *timings);
+
+static inline struct lt6911uxe *to_lt6911uxe(struct v4l2_subdev *sd)
+{
+	return container_of(sd, struct lt6911uxe, sd);
+}
+
+static void i2c_rd(struct v4l2_subdev *sd, u16 reg, u8 *values, u32 n)
+{
+	struct lt6911uxe *lt6911uxe = to_lt6911uxe(sd);
+	struct i2c_client *client = lt6911uxe->i2c_client;
+	int err;
+	u8 buf[2] = { 0xFF, reg >> 8};
+	u8 reg_addr = reg & 0xFF;
+	struct i2c_msg msgs[3];
+
+	msgs[0].addr = client->addr;
+	msgs[0].flags = 0;
+	msgs[0].len = 2;
+	msgs[0].buf = buf;
+
+	msgs[1].addr = client->addr;
+	msgs[1].flags = 0;
+	msgs[1].len = 1;
+	msgs[1].buf = &reg_addr;
+
+	msgs[2].addr = client->addr;
+	msgs[2].flags = I2C_M_RD;
+	msgs[2].len = n;
+	msgs[2].buf = values;
+
+	err = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
+	if (err != ARRAY_SIZE(msgs)) {
+		v4l2_err(sd, "%s: reading register 0x%x from 0x%x failed\n",
+				__func__, reg, client->addr);
+	}
+
+	if (!debug)
+		return;
+
+	switch (n) {
+	case 1:
+		v4l2_info(sd, "I2C read 0x%04x = 0x%02x\n",
+			reg, values[0]);
+		break;
+	case 2:
+		v4l2_info(sd, "I2C read 0x%04x = 0x%02x%02x\n",
+			reg, values[1], values[0]);
+		break;
+	case 4:
+		v4l2_info(sd, "I2C read 0x%04x = 0x%02x%02x%02x%02x\n",
+			reg, values[3], values[2], values[1], values[0]);
+		break;
+	default:
+		v4l2_info(sd, "I2C read %d bytes from address 0x%04x\n",
+			n, reg);
+	}
+}
+
+static void i2c_wr(struct v4l2_subdev *sd, u16 reg, u8 *values, u32 n)
+{
+	struct lt6911uxe *lt6911uxe = to_lt6911uxe(sd);
+	struct i2c_client *client = lt6911uxe->i2c_client;
+	int err, i;
+	struct i2c_msg msgs[2];
+	u8 data[I2C_MAX_XFER_SIZE];
+	u8 buf[2] = { 0xFF, reg >> 8};
+
+	if ((1 + n) > I2C_MAX_XFER_SIZE) {
+		n = I2C_MAX_XFER_SIZE - 1;
+		v4l2_warn(sd, "i2c wr reg=%04x: len=%d is too big!\n",
+			  reg, 1 + n);
+	}
+
+	msgs[0].addr = client->addr;
+	msgs[0].flags = 0;
+	msgs[0].len = 2;
+	msgs[0].buf = buf;
+
+	msgs[1].addr = client->addr;
+	msgs[1].flags = 0;
+	msgs[1].len = 1 + n;
+	msgs[1].buf = data;
+
+	data[0] = reg & 0xff;
+	for (i = 0; i < n; i++)
+		data[1 + i] = values[i];
+
+	err = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
+	if (err < 0) {
+		v4l2_err(sd, "%s: writing register 0x%x from 0x%x failed\n",
+				__func__, reg, client->addr);
+		return;
+	}
+
+	if (!debug)
+		return;
+
+	switch (n) {
+	case 1:
+		v4l2_info(sd, "I2C write 0x%04x = 0x%02x\n",
+				reg, data[1]);
+		break;
+	case 2:
+		v4l2_info(sd, "I2C write 0x%04x = 0x%02x%02x\n",
+				reg, data[2], data[1]);
+		break;
+	case 4:
+		v4l2_info(sd, "I2C write 0x%04x = 0x%02x%02x%02x%02x\n",
+				reg, data[4], data[3], data[2], data[1]);
+		break;
+	default:
+		v4l2_info(sd, "I2C write %d bytes from address 0x%04x\n",
+				n, reg);
+	}
+}
+
+static u8 i2c_rd8(struct v4l2_subdev *sd, u16 reg)
+{
+	u32 val;
+
+	i2c_rd(sd, reg, (u8 __force *)&val, 1);
+	return val;
+}
+
+static void i2c_wr8(struct v4l2_subdev *sd, u16 reg, u8 val)
+{
+	i2c_wr(sd, reg, &val, 1);
+}
+
+static void lt6911uxe_i2c_enable(struct v4l2_subdev *sd)
+{
+	i2c_wr8(sd, I2C_EN_REG, I2C_ENABLE);
+}
+
+static void lt6911uxe_i2c_disable(struct v4l2_subdev *sd)
+{
+	i2c_wr8(sd, I2C_EN_REG, I2C_DISABLE);
+}
+
+static inline bool tx_5v_power_present(struct v4l2_subdev *sd)
+{
+	bool ret;
+	int val, i, cnt;
+	struct lt6911uxe *lt6911uxe = to_lt6911uxe(sd);
+
+	/* if not use plugin det gpio */
+	if (!lt6911uxe->plugin_det_gpio)
+		return true;
+
+	cnt = 0;
+	for (i = 0; i < 5; i++) {
+		val = gpiod_get_value(lt6911uxe->plugin_det_gpio);
+		if (val > 0)
+			cnt++;
+		usleep_range(500, 600);
+	}
+
+	ret = (cnt >= 4) ? true : false;
+	v4l2_dbg(1, debug, sd, "%s: %d\n", __func__, ret);
+
+	return ret;
+}
+
+static inline bool no_signal(struct v4l2_subdev *sd)
+{
+	struct lt6911uxe *lt6911uxe = to_lt6911uxe(sd);
+
+	v4l2_dbg(1, debug, sd, "%s no signal:%d\n", __func__,
+			lt6911uxe->nosignal);
+
+	return lt6911uxe->nosignal;
+}
+
+static inline bool audio_present(struct v4l2_subdev *sd)
+{
+	struct lt6911uxe *lt6911uxe = to_lt6911uxe(sd);
+
+	return lt6911uxe->is_audio_present;
+}
+
+static int get_audio_sampling_rate(struct v4l2_subdev *sd)
+{
+	static const int code_to_rate[] = {
+		44100, 0, 48000, 32000, 22050, 384000, 24000, 352800,
+		88200, 768000, 96000, 705600, 176400, 0, 192000, 0
+	};
+
+	if (no_signal(sd))
+		return 0;
+
+	return code_to_rate[2];
+}
+
+static inline unsigned int fps_calc(const struct v4l2_bt_timings *t)
+{
+	if (!V4L2_DV_BT_FRAME_HEIGHT(t) || !V4L2_DV_BT_FRAME_WIDTH(t))
+		return 0;
+
+	return DIV_ROUND_CLOSEST((unsigned int)t->pixelclock,
+			V4L2_DV_BT_FRAME_HEIGHT(t) * V4L2_DV_BT_FRAME_WIDTH(t));
+}
+
+static bool lt6911uxe_rcv_supported_res(struct v4l2_subdev *sd, u32 width,
+		u32 height)
+{
+	struct lt6911uxe *lt6911uxe = to_lt6911uxe(sd);
+	u32 i;
+
+	for (i = 0; i < lt6911uxe->cfg_num; i++) {
+		if ((lt6911uxe->support_modes[i].width == width) &&
+		    (lt6911uxe->support_modes[i].height == height)) {
+			break;
+		}
+	}
+
+	if (i == lt6911uxe->cfg_num) {
+		v4l2_err(sd, "%s do not support res wxh: %dx%d\n", __func__,
+				width, height);
+		return false;
+	} else {
+		return true;
+	}
+}
+
+static int lt6911uxe_get_detected_timings(struct v4l2_subdev *sd,
+				     struct v4l2_dv_timings *timings)
+{
+	struct lt6911uxe *lt6911uxe = to_lt6911uxe(sd);
+	struct v4l2_bt_timings *bt = &timings->bt;
+	u32 hact, vact, htotal, vtotal;
+	u32 pixel_clock, fps, halt_pix_clk;
+	u8 clk_h, clk_m, clk_l;
+	u8 val_h, val_l;
+	u32 byte_clk, mipi_clk, mipi_data_rate;
+
+	memset(timings, 0, sizeof(struct v4l2_dv_timings));
+
+	clk_h = i2c_rd8(sd, PCLK_H);
+	clk_m = i2c_rd8(sd, PCLK_M);
+	clk_l = i2c_rd8(sd, PCLK_L);
+	halt_pix_clk = ((clk_h << 16) | (clk_m << 8) | clk_l);
+	pixel_clock = halt_pix_clk * 1000 * 2;
+
+	clk_h = i2c_rd8(sd, BYTE_PCLK_H);
+	clk_m = i2c_rd8(sd, BYTE_PCLK_M);
+	clk_l = i2c_rd8(sd, BYTE_PCLK_L);
+	byte_clk = ((clk_h << 16) | (clk_m << 8) | clk_l) * 1000;
+	mipi_clk = byte_clk * 4;
+	mipi_data_rate = byte_clk * 8;
+
+	val_h = i2c_rd8(sd, HTOTAL_H);
+	val_l = i2c_rd8(sd, HTOTAL_L);
+	htotal = ((val_h << 8) | val_l) * 2;
+
+	val_h = i2c_rd8(sd, VTOTAL_H);
+	val_l = i2c_rd8(sd, VTOTAL_L);
+	vtotal = (val_h << 8) | val_l;
+
+	val_h = i2c_rd8(sd, HACT_H);
+	val_l = i2c_rd8(sd, HACT_L);
+	hact = ((val_h << 8) | val_l) * 2;
+
+	val_h = i2c_rd8(sd, VACT_H);
+	val_l = i2c_rd8(sd, VACT_L);
+	vact = (val_h << 8) | val_l;
+
+	if (!lt6911uxe_rcv_supported_res(sd, hact, vact)) {
+		lt6911uxe->nosignal = true;
+		v4l2_err(sd, "%s: rcv err res, return no signal!\n", __func__);
+		return -EINVAL;
+	}
+
+	lt6911uxe->nosignal = false;
+	lt6911uxe->is_audio_present = true;
+	timings->type = V4L2_DV_BT_656_1120;
+	bt->interlaced = V4L2_DV_PROGRESSIVE;
+	bt->width = hact;
+	bt->height = vact;
+	bt->pixelclock = pixel_clock;
+	fps = pixel_clock / (htotal * vtotal);
+
+	v4l2_info(sd, "act:%dx%d, total:%dx%d, pixclk:%d, fps:%d\n",
+			hact, vact, htotal, vtotal, pixel_clock, fps);
+	v4l2_info(sd, "byte_clk:%d, mipi_clk:%d, mipi_data_rate:%d\n",
+			byte_clk, mipi_clk, mipi_data_rate);
+	v4l2_info(sd, "inerlaced:%d\n", bt->interlaced);
+
+	return 0;
+}
+
+static void lt6911uxe_delayed_work_hotplug(struct work_struct *work)
+{
+	struct delayed_work *dwork = to_delayed_work(work);
+	struct lt6911uxe *lt6911uxe = container_of(dwork,
+			struct lt6911uxe, delayed_work_hotplug);
+	struct v4l2_subdev *sd = &lt6911uxe->sd;
+
+	lt6911uxe_s_ctrl_detect_tx_5v(sd);
+}
+
+static void lt6911uxe_delayed_work_res_change(struct work_struct *work)
+{
+	struct delayed_work *dwork = to_delayed_work(work);
+	struct lt6911uxe *lt6911uxe = container_of(dwork,
+			struct lt6911uxe, delayed_work_res_change);
+	struct v4l2_subdev *sd = &lt6911uxe->sd;
+
+	lt6911uxe_format_change(sd);
+}
+
+static int lt6911uxe_s_ctrl_detect_tx_5v(struct v4l2_subdev *sd)
+{
+	struct lt6911uxe *lt6911uxe = to_lt6911uxe(sd);
+
+	return v4l2_ctrl_s_ctrl(lt6911uxe->detect_tx_5v_ctrl,
+			tx_5v_power_present(sd));
+}
+
+static int lt6911uxe_s_ctrl_audio_sampling_rate(struct v4l2_subdev *sd)
+{
+	struct lt6911uxe *lt6911uxe = to_lt6911uxe(sd);
+
+	return v4l2_ctrl_s_ctrl(lt6911uxe->audio_sampling_rate_ctrl,
+			get_audio_sampling_rate(sd));
+}
+
+static int lt6911uxe_s_ctrl_audio_present(struct v4l2_subdev *sd)
+{
+	struct lt6911uxe *lt6911uxe = to_lt6911uxe(sd);
+
+	return v4l2_ctrl_s_ctrl(lt6911uxe->audio_present_ctrl,
+			audio_present(sd));
+}
+
+static int lt6911uxe_update_controls(struct v4l2_subdev *sd)
+{
+	int ret = 0;
+
+	ret |= lt6911uxe_s_ctrl_detect_tx_5v(sd);
+	ret |= lt6911uxe_s_ctrl_audio_sampling_rate(sd);
+	ret |= lt6911uxe_s_ctrl_audio_present(sd);
+
+	return ret;
+}
+
+static bool lt6911uxe_match_timings(const struct v4l2_dv_timings *t1,
+					const struct v4l2_dv_timings *t2)
+{
+	if (t1->type != t2->type || t1->type != V4L2_DV_BT_656_1120)
+		return false;
+	if (t1->bt.width == t2->bt.width &&
+		t1->bt.height == t2->bt.height &&
+		t1->bt.interlaced == t2->bt.interlaced)
+		return true;
+
+	return false;
+}
+
+static inline void enable_stream(struct v4l2_subdev *sd, bool enable)
+{
+	struct lt6911uxe *lt6911uxe = to_lt6911uxe(sd);
+
+	if (enable)
+		i2c_wr8(&lt6911uxe->sd, STREAM_CTL, ENABLE_STREAM);
+	else
+		i2c_wr8(&lt6911uxe->sd, STREAM_CTL, DISABLE_STREAM);
+	msleep(50);
+
+	v4l2_dbg(2, debug, sd, "%s: %sable\n",
+			__func__, enable ? "en" : "dis");
+}
+
+static void lt6911uxe_format_change(struct v4l2_subdev *sd)
+{
+	struct lt6911uxe *lt6911uxe = to_lt6911uxe(sd);
+	struct v4l2_dv_timings timings;
+	const struct v4l2_event lt6911uxe_ev_fmt = {
+		.type = V4L2_EVENT_SOURCE_CHANGE,
+		.u.src_change.changes = V4L2_EVENT_SRC_CH_RESOLUTION,
+	};
+
+	if (lt6911uxe_get_detected_timings(sd, &timings)) {
+		enable_stream(sd, false);
+		v4l2_dbg(1, debug, sd, "%s: No signal\n", __func__);
+	}
+
+	if (!lt6911uxe_match_timings(&lt6911uxe->timings, &timings)) {
+		enable_stream(sd, false);
+		/* automatically set timing rather than set by user */
+		lt6911uxe_s_dv_timings(sd, &timings);
+		v4l2_print_dv_timings(sd->name,
+				"Format_change: New format: ",
+				&timings, false);
+	}
+	if (sd->devnode)
+		v4l2_subdev_notify_event(sd, &lt6911uxe_ev_fmt);
+}
+
+static int lt6911uxe_isr(struct v4l2_subdev *sd, u32 status, bool *handled)
+{
+	struct lt6911uxe *lt6911uxe = to_lt6911uxe(sd);
+
+	schedule_delayed_work(&lt6911uxe->delayed_work_res_change, HZ / 20);
+	*handled = true;
+
+	return 0;
+}
+
+static irqreturn_t lt6911uxe_res_change_irq_handler(int irq, void *dev_id)
+{
+	struct lt6911uxe *lt6911uxe = dev_id;
+	bool handled;
+
+	lt6911uxe_isr(&lt6911uxe->sd, 0, &handled);
+
+	return handled ? IRQ_HANDLED : IRQ_NONE;
+}
+
+static irqreturn_t plugin_detect_irq_handler(int irq, void *dev_id)
+{
+	struct lt6911uxe *lt6911uxe = dev_id;
+
+	/* control hpd output level after 25ms */
+	schedule_delayed_work(&lt6911uxe->delayed_work_hotplug,
+			HZ / 40);
+
+	return IRQ_HANDLED;
+}
+
+static void lt6911uxe_irq_poll_timer(struct timer_list *t)
+{
+	struct lt6911uxe *lt6911uxe = from_timer(lt6911uxe, t, timer);
+
+	schedule_work(&lt6911uxe->work_i2c_poll);
+	mod_timer(&lt6911uxe->timer, jiffies + msecs_to_jiffies(POLL_INTERVAL_MS));
+}
+
+static void lt6911uxe_work_i2c_poll(struct work_struct *work)
+{
+	struct lt6911uxe *lt6911uxe = container_of(work,
+			struct lt6911uxe, work_i2c_poll);
+	struct v4l2_subdev *sd = &lt6911uxe->sd;
+
+	lt6911uxe_format_change(sd);
+}
+
+static int lt6911uxe_subscribe_event(struct v4l2_subdev *sd, struct v4l2_fh *fh,
+				    struct v4l2_event_subscription *sub)
+{
+	switch (sub->type) {
+	case V4L2_EVENT_SOURCE_CHANGE:
+		return v4l2_src_change_event_subdev_subscribe(sd, fh, sub);
+	case V4L2_EVENT_CTRL:
+		return v4l2_ctrl_subdev_subscribe_event(sd, fh, sub);
+	default:
+		return -EINVAL;
+	}
+}
+
+static int lt6911uxe_g_input_status(struct v4l2_subdev *sd, u32 *status)
+{
+	*status = 0;
+	*status |= no_signal(sd) ? V4L2_IN_ST_NO_SIGNAL : 0;
+
+	v4l2_dbg(1, debug, sd, "%s: status = 0x%x\n", __func__, *status);
+
+	return 0;
+}
+
+static int lt6911uxe_s_dv_timings(struct v4l2_subdev *sd,
+				 struct v4l2_dv_timings *timings)
+{
+	struct lt6911uxe *lt6911uxe = to_lt6911uxe(sd);
+
+	if (!timings)
+		return -EINVAL;
+
+	if (debug)
+		v4l2_print_dv_timings(sd->name, "s_dv_timings: ",
+				timings, false);
+
+	if (lt6911uxe_match_timings(&lt6911uxe->timings, timings)) {
+		v4l2_dbg(1, debug, sd, "%s: no change\n", __func__);
+		return 0;
+	}
+
+	if (!v4l2_valid_dv_timings(timings,
+				&lt6911uxe_timings_cap, NULL, NULL)) {
+		v4l2_dbg(1, debug, sd, "%s: timings out of range\n", __func__);
+		return -ERANGE;
+	}
+
+	lt6911uxe->timings = *timings;
+
+	enable_stream(sd, false);
+
+	return 0;
+}
+
+static int lt6911uxe_g_dv_timings(struct v4l2_subdev *sd,
+				struct v4l2_dv_timings *timings)
+{
+	struct lt6911uxe *lt6911uxe = to_lt6911uxe(sd);
+
+	*timings = lt6911uxe->timings;
+
+	return 0;
+}
+
+static int lt6911uxe_enum_dv_timings(struct v4l2_subdev *sd,
+				struct v4l2_enum_dv_timings *timings)
+{
+	if (timings->pad != 0)
+		return -EINVAL;
+
+	return v4l2_enum_dv_timings_cap(timings,
+			&lt6911uxe_timings_cap, NULL, NULL);
+}
+
+static int lt6911uxe_query_dv_timings(struct v4l2_subdev *sd,
+				struct v4l2_dv_timings *timings)
+{
+	struct lt6911uxe *lt6911uxe = to_lt6911uxe(sd);
+
+	*timings = lt6911uxe->timings;
+	if (debug)
+		v4l2_print_dv_timings(sd->name,
+				"query_dv_timings: ", timings, false);
+
+	if (!v4l2_valid_dv_timings(timings, &lt6911uxe_timings_cap, NULL,
+				NULL)) {
+		v4l2_dbg(1, debug, sd, "%s: timings out of range\n",
+				__func__);
+
+		return -ERANGE;
+	}
+
+	return 0;
+}
+
+static int lt6911uxe_dv_timings_cap(struct v4l2_subdev *sd,
+				struct v4l2_dv_timings_cap *cap)
+{
+	if (cap->pad != 0)
+		return -EINVAL;
+
+	*cap = lt6911uxe_timings_cap;
+
+	return 0;
+}
+
+static int lt6911uxe_g_mbus_config(struct v4l2_subdev *sd,
+			unsigned int pad, struct v4l2_mbus_config *cfg)
+{
+	struct lt6911uxe *lt6911uxe = to_lt6911uxe(sd);
+	u32 lane_num = lt6911uxe->bus_cfg.bus.mipi_csi2.num_data_lanes;
+	u32 val = 0;
+
+	val = 1 << (lane_num - 1) |
+		V4L2_MBUS_CSI2_CHANNEL_0 |
+		V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
+
+	cfg->type = lt6911uxe->bus_cfg.bus_type;
+	cfg->flags = val;
+
+	return 0;
+}
+
+static int lt6911uxe_s_stream(struct v4l2_subdev *sd, int on)
+{
+	enable_stream(sd, on);
+
+	return 0;
+}
+
+static int lt6911uxe_enum_mbus_code(struct v4l2_subdev *sd,
+			struct v4l2_subdev_pad_config *cfg,
+			struct v4l2_subdev_mbus_code_enum *code)
+{
+	switch (code->index) {
+	case 0:
+		code->code = LT6911UXE_MEDIA_BUS_FMT;
+		break;
+
+	default:
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static int lt6911uxe_enum_frame_sizes(struct v4l2_subdev *sd,
+				   struct v4l2_subdev_pad_config *cfg,
+				   struct v4l2_subdev_frame_size_enum *fse)
+{
+	struct lt6911uxe *lt6911uxe = to_lt6911uxe(sd);
+
+	if (fse->index >= lt6911uxe->cfg_num)
+		return -EINVAL;
+
+	if (fse->code != LT6911UXE_MEDIA_BUS_FMT)
+		return -EINVAL;
+
+	fse->min_width  = lt6911uxe->support_modes[fse->index].width;
+	fse->max_width  = lt6911uxe->support_modes[fse->index].width;
+	fse->max_height = lt6911uxe->support_modes[fse->index].height;
+	fse->min_height = lt6911uxe->support_modes[fse->index].height;
+
+	return 0;
+}
+
+static int lt6911uxe_enum_frame_interval(struct v4l2_subdev *sd,
+				struct v4l2_subdev_pad_config *cfg,
+				struct v4l2_subdev_frame_interval_enum *fie)
+{
+	struct lt6911uxe *lt6911uxe = to_lt6911uxe(sd);
+
+	if (fie->index >= lt6911uxe->cfg_num)
+		return -EINVAL;
+
+	if (fie->code != LT6911UXE_MEDIA_BUS_FMT)
+		return -EINVAL;
+
+	fie->width = lt6911uxe->support_modes[fie->index].width;
+	fie->height = lt6911uxe->support_modes[fie->index].height;
+	fie->interval = lt6911uxe->support_modes[fie->index].max_fps;
+
+	return 0;
+}
+
+static int lt6911uxe_get_reso_dist(const struct lt6911uxe_mode *mode,
+				struct v4l2_mbus_framefmt *framefmt)
+{
+	return abs(mode->width - framefmt->width) +
+		abs(mode->height - framefmt->height);
+}
+
+static const struct lt6911uxe_mode *
+lt6911uxe_find_best_fit(struct lt6911uxe *lt6911uxe, struct v4l2_subdev_format *fmt)
+{
+	struct v4l2_mbus_framefmt *framefmt = &fmt->format;
+	int dist;
+	int cur_best_fit = 0;
+	int cur_best_fit_dist = -1;
+	unsigned int i;
+
+	for (i = 0; i < lt6911uxe->cfg_num; i++) {
+		dist = lt6911uxe_get_reso_dist(&lt6911uxe->support_modes[i], framefmt);
+		if (cur_best_fit_dist == -1 || dist < cur_best_fit_dist) {
+			cur_best_fit_dist = dist;
+			cur_best_fit = i;
+		}
+	}
+
+	return &lt6911uxe->support_modes[cur_best_fit];
+}
+
+static int lt6911uxe_get_fmt(struct v4l2_subdev *sd,
+			struct v4l2_subdev_pad_config *cfg,
+			struct v4l2_subdev_format *format)
+{
+	struct lt6911uxe *lt6911uxe = to_lt6911uxe(sd);
+	const struct lt6911uxe_mode *mode;
+
+	mutex_lock(&lt6911uxe->confctl_mutex);
+	format->format.code = lt6911uxe->mbus_fmt_code;
+	format->format.width = lt6911uxe->timings.bt.width;
+	format->format.height = lt6911uxe->timings.bt.height;
+	format->format.field =
+		lt6911uxe->timings.bt.interlaced ?
+		V4L2_FIELD_INTERLACED : V4L2_FIELD_NONE;
+	format->format.colorspace = V4L2_COLORSPACE_SRGB;
+
+	mode = lt6911uxe_find_best_fit(lt6911uxe, format);
+	__v4l2_ctrl_s_ctrl_int64(lt6911uxe->pixel_rate,
+				LT6911UXE_PIXEL_RATE);
+	__v4l2_ctrl_s_ctrl(lt6911uxe->link_freq,
+				mode->mipi_freq_idx);
+	mutex_unlock(&lt6911uxe->confctl_mutex);
+
+	v4l2_dbg(1, debug, sd, "%s: fmt code:%d, w:%d, h:%d, field code:%d\n",
+			__func__, format->format.code, format->format.width,
+			format->format.height, format->format.field);
+
+	return 0;
+}
+
+static int lt6911uxe_set_fmt(struct v4l2_subdev *sd,
+			struct v4l2_subdev_pad_config *cfg,
+			struct v4l2_subdev_format *format)
+{
+	struct lt6911uxe *lt6911uxe = to_lt6911uxe(sd);
+	const struct lt6911uxe_mode *mode;
+
+	/* is overwritten by get_fmt */
+	u32 code = format->format.code;
+	int ret = lt6911uxe_get_fmt(sd, cfg, format);
+
+	format->format.code = code;
+
+	if (ret)
+		return ret;
+
+	switch (code) {
+	case LT6911UXE_MEDIA_BUS_FMT:
+		break;
+
+	default:
+		return -EINVAL;
+	}
+
+	if (format->which == V4L2_SUBDEV_FORMAT_TRY)
+		return 0;
+
+	lt6911uxe->mbus_fmt_code = format->format.code;
+	mode = lt6911uxe_find_best_fit(lt6911uxe, format);
+	lt6911uxe->cur_mode = mode;
+
+	enable_stream(sd, false);
+
+	dev_info(&lt6911uxe->i2c_client->dev, "%s: mode->mipi_freq_idx(%d)",
+		 __func__, mode->mipi_freq_idx);
+
+	return 0;
+}
+
+static int lt6911uxe_g_frame_interval(struct v4l2_subdev *sd,
+			struct v4l2_subdev_frame_interval *fi)
+{
+	struct lt6911uxe *lt6911uxe = to_lt6911uxe(sd);
+	const struct lt6911uxe_mode *mode = lt6911uxe->cur_mode;
+
+	mutex_lock(&lt6911uxe->confctl_mutex);
+	fi->interval = mode->max_fps;
+	mutex_unlock(&lt6911uxe->confctl_mutex);
+
+	return 0;
+}
+
+static void lt6911uxe_get_module_inf(struct lt6911uxe *lt6911uxe,
+				  struct rkmodule_inf *inf)
+{
+	memset(inf, 0, sizeof(*inf));
+	strscpy(inf->base.sensor, LT6911UXE_NAME, sizeof(inf->base.sensor));
+	strscpy(inf->base.module, lt6911uxe->module_name, sizeof(inf->base.module));
+	strscpy(inf->base.lens, lt6911uxe->len_name, sizeof(inf->base.lens));
+}
+
+static long lt6911uxe_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
+{
+	struct lt6911uxe *lt6911uxe = to_lt6911uxe(sd);
+	long ret = 0;
+	struct rkmodule_csi_dphy_param *dphy_param;
+
+	switch (cmd) {
+	case RKMODULE_GET_MODULE_INFO:
+		lt6911uxe_get_module_inf(lt6911uxe, (struct rkmodule_inf *)arg);
+		break;
+	case RKMODULE_GET_HDMI_MODE:
+		*(int *)arg = RKMODULE_HDMIIN_MODE;
+		break;
+	case RKMODULE_SET_CSI_DPHY_PARAM:
+		dphy_param = (struct rkmodule_csi_dphy_param *)arg;
+		if (dphy_param->vendor == rk3588_dcphy_param.vendor)
+			rk3588_dcphy_param = *dphy_param;
+		dev_dbg(&lt6911uxe->i2c_client->dev,
+			"sensor set dphy param\n");
+		break;
+	case RKMODULE_GET_CSI_DPHY_PARAM:
+		dphy_param = (struct rkmodule_csi_dphy_param *)arg;
+		if (dphy_param->vendor == rk3588_dcphy_param.vendor)
+			*dphy_param = rk3588_dcphy_param;
+		dev_dbg(&lt6911uxe->i2c_client->dev,
+			"sensor get dphy param\n");
+		break;
+	default:
+		ret = -ENOIOCTLCMD;
+		break;
+	}
+
+	return ret;
+}
+
+static int lt6911uxe_s_power(struct v4l2_subdev *sd, int on)
+{
+	struct lt6911uxe *lt6911uxe = to_lt6911uxe(sd);
+	int ret = 0;
+
+	mutex_lock(&lt6911uxe->confctl_mutex);
+
+	if (lt6911uxe->power_on == !!on)
+		goto unlock_and_return;
+
+	if (on)
+		lt6911uxe->power_on = true;
+	else
+		lt6911uxe->power_on = false;
+
+unlock_and_return:
+	mutex_unlock(&lt6911uxe->confctl_mutex);
+
+	return ret;
+}
+
+#ifdef CONFIG_COMPAT
+static long lt6911uxe_compat_ioctl32(struct v4l2_subdev *sd,
+				  unsigned int cmd, unsigned long arg)
+{
+	void __user *up = compat_ptr(arg);
+	struct rkmodule_inf *inf;
+	long ret;
+	int *seq;
+	struct rkmodule_csi_dphy_param *dphy_param;
+
+	switch (cmd) {
+	case RKMODULE_GET_MODULE_INFO:
+		inf = kzalloc(sizeof(*inf), GFP_KERNEL);
+		if (!inf) {
+			ret = -ENOMEM;
+			return ret;
+		}
+
+		ret = lt6911uxe_ioctl(sd, cmd, inf);
+		if (!ret) {
+			ret = copy_to_user(up, inf, sizeof(*inf));
+			if (ret)
+				ret = -EFAULT;
+		}
+		kfree(inf);
+		break;
+	case RKMODULE_GET_HDMI_MODE:
+		seq = kzalloc(sizeof(*seq), GFP_KERNEL);
+		if (!seq) {
+			ret = -ENOMEM;
+			return ret;
+		}
+
+		ret = lt6911uxe_ioctl(sd, cmd, seq);
+		if (!ret) {
+			ret = copy_to_user(up, seq, sizeof(*seq));
+			if (ret)
+				ret = -EFAULT;
+		}
+		kfree(seq);
+		break;
+	case RKMODULE_SET_CSI_DPHY_PARAM:
+		dphy_param = kzalloc(sizeof(*dphy_param), GFP_KERNEL);
+		if (!dphy_param) {
+			ret = -ENOMEM;
+			return ret;
+		}
+
+		ret = copy_from_user(dphy_param, up, sizeof(*dphy_param));
+		if (!ret)
+			ret = lt6911uxe_ioctl(sd, cmd, dphy_param);
+		else
+			ret = -EFAULT;
+		kfree(dphy_param);
+		break;
+	case RKMODULE_GET_CSI_DPHY_PARAM:
+		dphy_param = kzalloc(sizeof(*dphy_param), GFP_KERNEL);
+		if (!dphy_param) {
+			ret = -ENOMEM;
+			return ret;
+		}
+
+		ret = lt6911uxe_ioctl(sd, cmd, dphy_param);
+		if (!ret) {
+			ret = copy_to_user(up, dphy_param, sizeof(*dphy_param));
+			if (ret)
+				ret = -EFAULT;
+		}
+		kfree(dphy_param);
+		break;
+	default:
+		ret = -ENOIOCTLCMD;
+		break;
+	}
+
+	return ret;
+}
+#endif
+
+#ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
+static int lt6911uxe_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
+{
+	struct lt6911uxe *lt6911uxe = to_lt6911uxe(sd);
+	struct v4l2_mbus_framefmt *try_fmt =
+				v4l2_subdev_get_try_format(sd, fh->pad, 0);
+	const struct lt6911uxe_mode *def_mode = &lt6911uxe->support_modes[0];
+
+	mutex_lock(&lt6911uxe->confctl_mutex);
+	/* Initialize try_fmt */
+	try_fmt->width = def_mode->width;
+	try_fmt->height = def_mode->height;
+	try_fmt->code = LT6911UXE_MEDIA_BUS_FMT;
+	try_fmt->field = V4L2_FIELD_NONE;
+	mutex_unlock(&lt6911uxe->confctl_mutex);
+
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
+static const struct v4l2_subdev_internal_ops lt6911uxe_internal_ops = {
+	.open = lt6911uxe_open,
+};
+#endif
+
+static const struct v4l2_subdev_core_ops lt6911uxe_core_ops = {
+	.s_power = lt6911uxe_s_power,
+	.interrupt_service_routine = lt6911uxe_isr,
+	.subscribe_event = lt6911uxe_subscribe_event,
+	.unsubscribe_event = v4l2_event_subdev_unsubscribe,
+	.ioctl = lt6911uxe_ioctl,
+#ifdef CONFIG_COMPAT
+	.compat_ioctl32 = lt6911uxe_compat_ioctl32,
+#endif
+};
+
+static const struct v4l2_subdev_video_ops lt6911uxe_video_ops = {
+	.g_input_status = lt6911uxe_g_input_status,
+	.s_dv_timings = lt6911uxe_s_dv_timings,
+	.g_dv_timings = lt6911uxe_g_dv_timings,
+	.query_dv_timings = lt6911uxe_query_dv_timings,
+	.s_stream = lt6911uxe_s_stream,
+	.g_frame_interval = lt6911uxe_g_frame_interval,
+};
+
+static const struct v4l2_subdev_pad_ops lt6911uxe_pad_ops = {
+	.enum_mbus_code = lt6911uxe_enum_mbus_code,
+	.enum_frame_size = lt6911uxe_enum_frame_sizes,
+	.enum_frame_interval = lt6911uxe_enum_frame_interval,
+	.set_fmt = lt6911uxe_set_fmt,
+	.get_fmt = lt6911uxe_get_fmt,
+	.enum_dv_timings = lt6911uxe_enum_dv_timings,
+	.dv_timings_cap = lt6911uxe_dv_timings_cap,
+	.get_mbus_config = lt6911uxe_g_mbus_config,
+};
+
+static const struct v4l2_subdev_ops lt6911uxe_ops = {
+	.core = &lt6911uxe_core_ops,
+	.video = &lt6911uxe_video_ops,
+	.pad = &lt6911uxe_pad_ops,
+};
+
+static const struct v4l2_ctrl_config lt6911uxe_ctrl_audio_sampling_rate = {
+	.id = RK_V4L2_CID_AUDIO_SAMPLING_RATE,
+	.name = "Audio sampling rate",
+	.type = V4L2_CTRL_TYPE_INTEGER,
+	.min = 0,
+	.max = 768000,
+	.step = 1,
+	.def = 0,
+	.flags = V4L2_CTRL_FLAG_READ_ONLY,
+};
+
+static const struct v4l2_ctrl_config lt6911uxe_ctrl_audio_present = {
+	.id = RK_V4L2_CID_AUDIO_PRESENT,
+	.name = "Audio present",
+	.type = V4L2_CTRL_TYPE_BOOLEAN,
+	.min = 0,
+	.max = 1,
+	.step = 1,
+	.def = 0,
+	.flags = V4L2_CTRL_FLAG_READ_ONLY,
+};
+
+static void lt6911uxe_reset(struct lt6911uxe *lt6911uxe)
+{
+	gpiod_set_value(lt6911uxe->reset_gpio, 0);
+	usleep_range(2000, 2100);
+	gpiod_set_value(lt6911uxe->reset_gpio, 1);
+	usleep_range(120*1000, 121*1000);
+	gpiod_set_value(lt6911uxe->reset_gpio, 0);
+	usleep_range(300*1000, 310*1000);
+}
+
+static int lt6911uxe_init_v4l2_ctrls(struct lt6911uxe *lt6911uxe)
+{
+	const struct lt6911uxe_mode *mode;
+	struct v4l2_subdev *sd;
+	int ret;
+
+	mode = lt6911uxe->cur_mode;
+	sd = &lt6911uxe->sd;
+	ret = v4l2_ctrl_handler_init(&lt6911uxe->hdl, 5);
+	if (ret)
+		return ret;
+
+	lt6911uxe->link_freq = v4l2_ctrl_new_int_menu(&lt6911uxe->hdl, NULL,
+			V4L2_CID_LINK_FREQ,
+			ARRAY_SIZE(link_freq_menu_items) - 1, 0,
+			link_freq_menu_items);
+	lt6911uxe->pixel_rate = v4l2_ctrl_new_std(&lt6911uxe->hdl, NULL,
+			V4L2_CID_PIXEL_RATE,
+			0, LT6911UXE_PIXEL_RATE, 1, LT6911UXE_PIXEL_RATE);
+
+	lt6911uxe->detect_tx_5v_ctrl = v4l2_ctrl_new_std(&lt6911uxe->hdl,
+			NULL, V4L2_CID_DV_RX_POWER_PRESENT,
+			0, 1, 0, 0);
+
+	lt6911uxe->audio_sampling_rate_ctrl =
+		v4l2_ctrl_new_custom(&lt6911uxe->hdl,
+				&lt6911uxe_ctrl_audio_sampling_rate, NULL);
+	lt6911uxe->audio_present_ctrl = v4l2_ctrl_new_custom(&lt6911uxe->hdl,
+			&lt6911uxe_ctrl_audio_present, NULL);
+
+	sd->ctrl_handler = &lt6911uxe->hdl;
+	if (lt6911uxe->hdl.error) {
+		ret = lt6911uxe->hdl.error;
+		v4l2_err(sd, "cfg v4l2 ctrls failed! ret:%d\n", ret);
+		return ret;
+	}
+
+	__v4l2_ctrl_s_ctrl(lt6911uxe->link_freq, mode->mipi_freq_idx);
+	__v4l2_ctrl_s_ctrl_int64(lt6911uxe->pixel_rate, LT6911UXE_PIXEL_RATE);
+
+	if (lt6911uxe_update_controls(sd)) {
+		ret = -ENODEV;
+		v4l2_err(sd, "update v4l2 ctrls failed! ret:%d\n", ret);
+		return ret;
+	}
+
+	return 0;
+}
+
+#ifdef CONFIG_OF
+static int lt6911uxe_probe_of(struct lt6911uxe *lt6911uxe)
+{
+	struct device *dev = &lt6911uxe->i2c_client->dev;
+	struct device_node *node = dev->of_node;
+	struct device_node *ep;
+	int ret;
+
+	ret = of_property_read_u32(node, RKMODULE_CAMERA_MODULE_INDEX,
+			&lt6911uxe->module_index);
+	ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_FACING,
+			&lt6911uxe->module_facing);
+	ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_NAME,
+			&lt6911uxe->module_name);
+	ret |= of_property_read_string(node, RKMODULE_CAMERA_LENS_NAME,
+			&lt6911uxe->len_name);
+	if (ret) {
+		dev_err(dev, "could not get module information!\n");
+		return -EINVAL;
+	}
+
+	lt6911uxe->power_gpio = devm_gpiod_get_optional(dev, "power",
+			GPIOD_OUT_LOW);
+	if (IS_ERR(lt6911uxe->power_gpio)) {
+		dev_err(dev, "failed to get power gpio\n");
+		ret = PTR_ERR(lt6911uxe->power_gpio);
+		return ret;
+	}
+
+	lt6911uxe->reset_gpio = devm_gpiod_get_optional(dev, "reset",
+			GPIOD_OUT_HIGH);
+	if (IS_ERR(lt6911uxe->reset_gpio)) {
+		dev_err(dev, "failed to get reset gpio\n");
+		ret = PTR_ERR(lt6911uxe->reset_gpio);
+		return ret;
+	}
+
+	lt6911uxe->plugin_det_gpio = devm_gpiod_get_optional(dev, "plugin-det",
+			GPIOD_IN);
+	if (IS_ERR(lt6911uxe->plugin_det_gpio)) {
+		dev_err(dev, "failed to get plugin det gpio\n");
+		ret = PTR_ERR(lt6911uxe->plugin_det_gpio);
+		return ret;
+	}
+
+	ep = of_graph_get_next_endpoint(dev->of_node, NULL);
+	if (!ep) {
+		dev_err(dev, "missing endpoint node\n");
+		return -EINVAL;
+	}
+
+	ret = v4l2_fwnode_endpoint_parse(of_fwnode_handle(ep),
+					&lt6911uxe->bus_cfg);
+	if (ret) {
+		dev_err(dev, "failed to parse endpoint\n");
+		goto put_node;
+	}
+
+	lt6911uxe->support_modes = supported_modes_dphy;
+	lt6911uxe->cfg_num = ARRAY_SIZE(supported_modes_dphy);
+
+	lt6911uxe->xvclk = devm_clk_get(dev, "xvclk");
+	if (IS_ERR(lt6911uxe->xvclk)) {
+		dev_err(dev, "failed to get xvclk\n");
+		ret = -EINVAL;
+		goto put_node;
+	}
+
+	ret = clk_prepare_enable(lt6911uxe->xvclk);
+	if (ret) {
+		dev_err(dev, "Failed! to enable xvclk\n");
+		goto put_node;
+	}
+
+	lt6911uxe->enable_hdcp = false;
+
+	gpiod_set_value(lt6911uxe->power_gpio, 1);
+	lt6911uxe_reset(lt6911uxe);
+
+	ret = 0;
+
+put_node:
+	of_node_put(ep);
+	return ret;
+}
+#else
+static inline int lt6911uxe_probe_of(struct lt6911uxe *state)
+{
+	return -ENODEV;
+}
+#endif
+static int lt6911uxe_check_chip_id(struct lt6911uxe *lt6911uxe)
+{
+	struct device *dev = &lt6911uxe->i2c_client->dev;
+	struct v4l2_subdev *sd = &lt6911uxe->sd;
+	u8 id_h, id_l;
+	u32 chipid;
+	int ret = 0;
+
+	lt6911uxe_i2c_enable(sd);
+	id_l  = i2c_rd8(sd, CHIPID_REGL);
+	id_h  = i2c_rd8(sd, CHIPID_REGH);
+	lt6911uxe_i2c_disable(sd);
+
+	chipid = (id_h << 8) | id_l;
+	if (chipid != LT6911UXE_CHIPID) {
+		dev_err(dev, "chipid err, read:%#x, expect:%#x\n",
+				chipid, LT6911UXE_CHIPID);
+		return -EINVAL;
+	}
+	dev_info(dev, "check chipid ok, id:%#x", chipid);
+
+	return ret;
+}
+
+static int lt6911uxe_probe(struct i2c_client *client,
+			  const struct i2c_device_id *id)
+{
+	struct lt6911uxe *lt6911uxe;
+	struct v4l2_subdev *sd;
+	struct device *dev = &client->dev;
+	char facing[2];
+	int err;
+
+	dev_info(dev, "driver version: %02x.%02x.%02x",
+		DRIVER_VERSION >> 16,
+		(DRIVER_VERSION & 0xff00) >> 8,
+		DRIVER_VERSION & 0x00ff);
+
+	lt6911uxe = devm_kzalloc(dev, sizeof(struct lt6911uxe), GFP_KERNEL);
+	if (!lt6911uxe)
+		return -ENOMEM;
+
+	sd = &lt6911uxe->sd;
+	lt6911uxe->i2c_client = client;
+	lt6911uxe->mbus_fmt_code = LT6911UXE_MEDIA_BUS_FMT;
+
+	err = lt6911uxe_probe_of(lt6911uxe);
+	if (err) {
+		v4l2_err(sd, "lt6911uxe_parse_of failed! err:%d\n", err);
+		return err;
+	}
+
+	lt6911uxe->cur_mode = &lt6911uxe->support_modes[0];
+	err = lt6911uxe_check_chip_id(lt6911uxe);
+	if (err < 0)
+		return err;
+
+	mutex_init(&lt6911uxe->confctl_mutex);
+	err = lt6911uxe_init_v4l2_ctrls(lt6911uxe);
+	if (err)
+		goto err_free_hdl;
+
+	client->flags |= I2C_CLIENT_SCCB;
+#ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
+	v4l2_i2c_subdev_init(sd, client, &lt6911uxe_ops);
+	sd->internal_ops = &lt6911uxe_internal_ops;
+	sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_HAS_EVENTS;
+#endif
+
+#if defined(CONFIG_MEDIA_CONTROLLER)
+	lt6911uxe->pad.flags = MEDIA_PAD_FL_SOURCE;
+	sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
+	err = media_entity_pads_init(&sd->entity, 1, &lt6911uxe->pad);
+	if (err < 0) {
+		v4l2_err(sd, "media entity init failed! err:%d\n", err);
+		goto err_free_hdl;
+	}
+#endif
+	memset(facing, 0, sizeof(facing));
+	if (strcmp(lt6911uxe->module_facing, "back") == 0)
+		facing[0] = 'b';
+	else
+		facing[0] = 'f';
+
+	snprintf(sd->name, sizeof(sd->name), "m%02d_%s_%s %s",
+		 lt6911uxe->module_index, facing,
+		 LT6911UXE_NAME, dev_name(sd->dev));
+	err = v4l2_async_register_subdev_sensor_common(sd);
+	if (err < 0) {
+		v4l2_err(sd, "v4l2 register subdev failed! err:%d\n", err);
+		goto err_clean_entity;
+	}
+
+	INIT_DELAYED_WORK(&lt6911uxe->delayed_work_hotplug,
+			lt6911uxe_delayed_work_hotplug);
+	INIT_DELAYED_WORK(&lt6911uxe->delayed_work_res_change,
+			lt6911uxe_delayed_work_res_change);
+
+	if (lt6911uxe->i2c_client->irq) {
+		v4l2_dbg(1, debug, sd, "cfg lt6911uxe irq!\n");
+		err = devm_request_threaded_irq(dev,
+				lt6911uxe->i2c_client->irq,
+				NULL, lt6911uxe_res_change_irq_handler,
+				IRQF_TRIGGER_RISING | IRQF_ONESHOT,
+				"lt6911uxe", lt6911uxe);
+		if (err) {
+			v4l2_err(sd, "request irq failed! err:%d\n", err);
+			goto err_work_queues;
+		}
+	} else {
+		v4l2_dbg(1, debug, sd, "no irq, cfg poll!\n");
+		INIT_WORK(&lt6911uxe->work_i2c_poll, lt6911uxe_work_i2c_poll);
+		timer_setup(&lt6911uxe->timer, lt6911uxe_irq_poll_timer, 0);
+		lt6911uxe->timer.expires = jiffies +
+				       msecs_to_jiffies(POLL_INTERVAL_MS);
+		add_timer(&lt6911uxe->timer);
+	}
+
+	lt6911uxe->plugin_irq = gpiod_to_irq(lt6911uxe->plugin_det_gpio);
+	if (lt6911uxe->plugin_irq < 0)
+		dev_err(dev, "failed to get plugin det irq, maybe no use\n");
+
+	err = devm_request_threaded_irq(dev, lt6911uxe->plugin_irq, NULL,
+			plugin_detect_irq_handler, IRQF_TRIGGER_FALLING |
+			IRQF_TRIGGER_RISING | IRQF_ONESHOT, "lt6911uxe",
+			lt6911uxe);
+	if (err)
+		dev_err(dev, "failed to register plugin det irq (%d), maybe no use\n", err);
+
+	err = v4l2_ctrl_handler_setup(sd->ctrl_handler);
+	if (err) {
+		v4l2_err(sd, "v4l2 ctrl handler setup failed! err:%d\n", err);
+		goto err_work_queues;
+	}
+
+	v4l2_info(sd, "%s found @ 0x%x (%s)\n", client->name,
+			client->addr << 1, client->adapter->name);
+
+	return 0;
+
+err_work_queues:
+	if (!lt6911uxe->i2c_client->irq)
+		flush_work(&lt6911uxe->work_i2c_poll);
+	cancel_delayed_work(&lt6911uxe->delayed_work_hotplug);
+	cancel_delayed_work(&lt6911uxe->delayed_work_res_change);
+err_clean_entity:
+#if defined(CONFIG_MEDIA_CONTROLLER)
+	media_entity_cleanup(&sd->entity);
+#endif
+err_free_hdl:
+	v4l2_ctrl_handler_free(&lt6911uxe->hdl);
+	mutex_destroy(&lt6911uxe->confctl_mutex);
+	return err;
+}
+
+static int lt6911uxe_remove(struct i2c_client *client)
+{
+	struct v4l2_subdev *sd = i2c_get_clientdata(client);
+	struct lt6911uxe *lt6911uxe = to_lt6911uxe(sd);
+
+	if (!lt6911uxe->i2c_client->irq) {
+		del_timer_sync(&lt6911uxe->timer);
+		flush_work(&lt6911uxe->work_i2c_poll);
+	}
+	cancel_delayed_work_sync(&lt6911uxe->delayed_work_hotplug);
+	cancel_delayed_work_sync(&lt6911uxe->delayed_work_res_change);
+	v4l2_async_unregister_subdev(sd);
+	v4l2_device_unregister_subdev(sd);
+#if defined(CONFIG_MEDIA_CONTROLLER)
+	media_entity_cleanup(&sd->entity);
+#endif
+	v4l2_ctrl_handler_free(&lt6911uxe->hdl);
+	mutex_destroy(&lt6911uxe->confctl_mutex);
+	clk_disable_unprepare(lt6911uxe->xvclk);
+
+	return 0;
+}
+
+#if IS_ENABLED(CONFIG_OF)
+static const struct of_device_id lt6911uxe_of_match[] = {
+	{ .compatible = "lontium,lt6911uxe" },
+	{},
+};
+MODULE_DEVICE_TABLE(of, lt6911uxe_of_match);
+#endif
+
+static struct i2c_driver lt6911uxe_driver = {
+	.driver = {
+		.name = LT6911UXE_NAME,
+		.of_match_table = of_match_ptr(lt6911uxe_of_match),
+	},
+	.probe = lt6911uxe_probe,
+	.remove = lt6911uxe_remove,
+};
+
+static int __init lt6911uxe_driver_init(void)
+{
+	return i2c_add_driver(&lt6911uxe_driver);
+}
+
+static void __exit lt6911uxe_driver_exit(void)
+{
+	i2c_del_driver(&lt6911uxe_driver);
+}
+
+device_initcall_sync(lt6911uxe_driver_init);
+module_exit(lt6911uxe_driver_exit);
+
+MODULE_DESCRIPTION("Lontium lt6911uxe HDMI to CSI-2 bridge driver");
+MODULE_AUTHOR("Jianwei Fan <jianwei.fan@rock-chips.com>");
+MODULE_LICENSE("GPL");
diff --git a/drivers/media/i2c/lt7911d.c b/drivers/media/i2c/lt7911d.c
index 1803f681fede..f2a479946174 100644
--- a/drivers/media/i2c/lt7911d.c
+++ b/drivers/media/i2c/lt7911d.c
@@ -49,6 +49,12 @@ MODULE_PARM_DESC(debug, "debug level (0-3)");
 #define LT7911D_LINK_FREQ	400000000
 #define LT7911D_PIXEL_RATE	400000000
 
+#ifdef LT7911D_OUT_RGB
+#define LT7911D_MEDIA_BUS_FMT		MEDIA_BUS_FMT_BGR888_1X24
+#else
+#define LT7911D_MEDIA_BUS_FMT		MEDIA_BUS_FMT_UYVY8_2X8
+#endif
+
 #define LT7911D_NAME			"LT7911D"
 
 static const s64 link_freq_menu_items[] = {
@@ -756,7 +762,7 @@ static int lt7911d_enum_mbus_code(struct v4l2_subdev *sd,
 {
 	switch (code->index) {
 	case 0:
-		code->code = MEDIA_BUS_FMT_UYVY8_2X8;
+		code->code = LT7911D_MEDIA_BUS_FMT;
 		break;
 
 	default:
@@ -773,7 +779,7 @@ static int lt7911d_enum_frame_sizes(struct v4l2_subdev *sd,
 	if (fse->index >= ARRAY_SIZE(supported_modes))
 		return -EINVAL;
 
-	if (fse->code != MEDIA_BUS_FMT_UYVY8_2X8)
+	if (fse->code != LT7911D_MEDIA_BUS_FMT)
 		return -EINVAL;
 
 	fse->min_width  = supported_modes[fse->index].width;
@@ -814,7 +820,7 @@ static int lt7911d_enum_frame_interval(struct v4l2_subdev *sd,
 	if (fie->index >= ARRAY_SIZE(supported_modes))
 		return -EINVAL;
 
-	if (fie->code != MEDIA_BUS_FMT_UYVY8_2X8)
+	if (fie->code != LT7911D_MEDIA_BUS_FMT)
 		return -EINVAL;
 
 	fie->width = supported_modes[fie->index].width;
@@ -868,7 +874,7 @@ static int lt7911d_set_fmt(struct v4l2_subdev *sd,
 		return ret;
 
 	switch (code) {
-	case MEDIA_BUS_FMT_UYVY8_2X8:
+	case LT7911D_MEDIA_BUS_FMT:
 		break;
 
 	default:
@@ -1035,16 +1041,6 @@ static const struct v4l2_ctrl_config lt7911d_ctrl_audio_present = {
 	.flags = V4L2_CTRL_FLAG_READ_ONLY,
 };
 
-static void lt7911d_reset(struct lt7911d_state *lt7911d)
-{
-	gpiod_set_value(lt7911d->reset_gpio, 0);
-	usleep_range(2000, 2100);
-	gpiod_set_value(lt7911d->reset_gpio, 1);
-	usleep_range(120*1000, 121*1000);
-	gpiod_set_value(lt7911d->reset_gpio, 0);
-	usleep_range(300*1000, 310*1000);
-}
-
 static int lt7911d_init_v4l2_ctrls(struct lt7911d_state *lt7911d)
 {
 	struct v4l2_subdev *sd;
@@ -1175,7 +1171,8 @@ static int lt7911d_probe_of(struct lt7911d_state *lt7911d)
 	lt7911d->enable_hdcp = false;
 
 	gpiod_set_value(lt7911d->power_gpio, 1);
-	lt7911d_reset(lt7911d);
+	usleep_range(2000, 3000);
+	gpiod_set_value(lt7911d->reset_gpio, 0);
 
 	ret = 0;
 
@@ -1236,7 +1233,7 @@ static int lt7911d_probe(struct i2c_client *client,
 	sd = &lt7911d->sd;
 	lt7911d->i2c_client = client;
 	lt7911d->cur_mode = &supported_modes[0];
-	lt7911d->mbus_fmt_code = MEDIA_BUS_FMT_UYVY8_2X8;
+	lt7911d->mbus_fmt_code = LT7911D_MEDIA_BUS_FMT;
 
 	err = lt7911d_probe_of(lt7911d);
 	if (err) {
@@ -1248,8 +1245,6 @@ static int lt7911d_probe(struct i2c_client *client,
 	if (err < 0)
 		return err;
 
-	lt7911d_reset(lt7911d);
-
 	mutex_init(&lt7911d->confctl_mutex);
 	err = lt7911d_init_v4l2_ctrls(lt7911d);
 	if (err)
diff --git a/drivers/media/i2c/lt7911uxc.c b/drivers/media/i2c/lt7911uxc.c
index 8fea3659d1cd..df91719199eb 100644
--- a/drivers/media/i2c/lt7911uxc.c
+++ b/drivers/media/i2c/lt7911uxc.c
@@ -11,6 +11,7 @@
  * V0.0X01.0X02 add CPHY support.
  * V0.0X01.0X03 add rk3588 dcphy param.
  * V0.0X01.0X04 add 5K60 support for CPHY.
+ * V0.0X01.0X05 add CSI BGR888 fmt.
  *
  */
 
@@ -38,7 +39,7 @@
 #include <media/v4l2-event.h>
 #include <media/v4l2-fwnode.h>
 
-#define DRIVER_VERSION			KERNEL_VERSION(0, 0x01, 0x04)
+#define DRIVER_VERSION			KERNEL_VERSION(0, 0x01, 0x05)
 
 static int debug;
 module_param(debug, int, 0644);
@@ -93,6 +94,12 @@ MODULE_PARM_DESC(debug, "debug level (0-3)");
 #define ENABLE_STREAM		0x01
 #define DISABLE_STREAM		0x00
 
+#ifdef LT7911UXC_OUT_RGB
+#define LT7911UXC_MEDIA_BUS_FMT		MEDIA_BUS_FMT_BGR888_1X24
+#else
+#define LT7911UXC_MEDIA_BUS_FMT		MEDIA_BUS_FMT_UYVY8_2X8
+#endif
+
 #define LT7911UXC_NAME			"LT7911UXC"
 
 static const s64 link_freq_menu_items[] = {
@@ -705,9 +712,9 @@ static void lt7911uxc_format_change(struct v4l2_subdev *sd)
 		v4l2_print_dv_timings(sd->name,
 				"Format_change: New format: ",
 				&timings, false);
-		if (sd->devnode)
-			v4l2_subdev_notify_event(sd, &lt7911uxc_ev_fmt);
 	}
+	if (sd->devnode)
+		v4l2_subdev_notify_event(sd, &lt7911uxc_ev_fmt);
 }
 
 static int lt7911uxc_isr(struct v4l2_subdev *sd, u32 status, bool *handled)
@@ -893,7 +900,7 @@ static int lt7911uxc_enum_mbus_code(struct v4l2_subdev *sd,
 {
 	switch (code->index) {
 	case 0:
-		code->code = MEDIA_BUS_FMT_UYVY8_2X8;
+		code->code = LT7911UXC_MEDIA_BUS_FMT;
 		break;
 
 	default:
@@ -912,7 +919,7 @@ static int lt7911uxc_enum_frame_sizes(struct v4l2_subdev *sd,
 	if (fse->index >= lt7911uxc->cfg_num)
 		return -EINVAL;
 
-	if (fse->code != MEDIA_BUS_FMT_UYVY8_2X8)
+	if (fse->code != LT7911UXC_MEDIA_BUS_FMT)
 		return -EINVAL;
 
 	fse->min_width  = lt7911uxc->support_modes[fse->index].width;
@@ -955,7 +962,7 @@ static int lt7911uxc_enum_frame_interval(struct v4l2_subdev *sd,
 	if (fie->index >= lt7911uxc->cfg_num)
 		return -EINVAL;
 
-	if (fie->code != MEDIA_BUS_FMT_UYVY8_2X8)
+	if (fie->code != LT7911UXC_MEDIA_BUS_FMT)
 		return -EINVAL;
 
 	fie->width = lt7911uxc->support_modes[fie->index].width;
@@ -1009,7 +1016,7 @@ static int lt7911uxc_set_fmt(struct v4l2_subdev *sd,
 		return ret;
 
 	switch (code) {
-	case MEDIA_BUS_FMT_UYVY8_2X8:
+	case LT7911UXC_MEDIA_BUS_FMT:
 		break;
 
 	default:
@@ -1205,7 +1212,7 @@ static int lt7911uxc_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
 	/* Initialize try_fmt */
 	try_fmt->width = def_mode->width;
 	try_fmt->height = def_mode->height;
-	try_fmt->code = MEDIA_BUS_FMT_UYVY8_2X8;
+	try_fmt->code = LT7911UXC_MEDIA_BUS_FMT;
 	try_fmt->field = V4L2_FIELD_NONE;
 	mutex_unlock(&lt7911uxc->confctl_mutex);
 
@@ -1278,16 +1285,6 @@ static const struct v4l2_ctrl_config lt7911uxc_ctrl_audio_present = {
 	.flags = V4L2_CTRL_FLAG_READ_ONLY,
 };
 
-static void lt7911uxc_reset(struct lt7911uxc *lt7911uxc)
-{
-	gpiod_set_value(lt7911uxc->reset_gpio, 0);
-	usleep_range(2000, 2100);
-	gpiod_set_value(lt7911uxc->reset_gpio, 1);
-	usleep_range(120*1000, 121*1000);
-	gpiod_set_value(lt7911uxc->reset_gpio, 0);
-	usleep_range(300*1000, 310*1000);
-}
-
 static int lt7911uxc_init_v4l2_ctrls(struct lt7911uxc *lt7911uxc)
 {
 	const struct lt7911uxc_mode *mode;
@@ -1419,7 +1416,9 @@ static int lt7911uxc_probe_of(struct lt7911uxc *lt7911uxc)
 	lt7911uxc->enable_hdcp = false;
 
 	gpiod_set_value(lt7911uxc->power_gpio, 1);
-	lt7911uxc_reset(lt7911uxc);
+	//delay 2~3ms before reset
+	usleep_range(2000, 3000);
+	gpiod_set_value(lt7911uxc->reset_gpio, 0);
 
 	ret = 0;
 
@@ -1477,7 +1476,7 @@ static int lt7911uxc_probe(struct i2c_client *client,
 
 	sd = &lt7911uxc->sd;
 	lt7911uxc->i2c_client = client;
-	lt7911uxc->mbus_fmt_code = MEDIA_BUS_FMT_UYVY8_2X8;
+	lt7911uxc->mbus_fmt_code = LT7911UXC_MEDIA_BUS_FMT;
 
 	err = lt7911uxc_probe_of(lt7911uxc);
 	if (err) {
diff --git a/drivers/media/i2c/s5kjn1.c b/drivers/media/i2c/s5kjn1.c
index 8172cdfb2416..0fcc9d27017d 100644
--- a/drivers/media/i2c/s5kjn1.c
+++ b/drivers/media/i2c/s5kjn1.c
@@ -9,6 +9,9 @@
  * V0.0X01.0X02
  * 1. set binning output 32 pixel aligned.
  * 2. fix channel info omitted copy from user issue.
+ * V0.0X01.0X03
+ * 1. add delays in setting to fix probability wrong reg write.
+ * 2. add register setting readback check support.
  */
 //#define DEBUG
 #include <linux/clk.h>
@@ -34,7 +37,10 @@
 #include <linux/of_graph.h>
 #include "otp_eeprom.h"
 
-#define DRIVER_VERSION			KERNEL_VERSION(0, 0x01, 0x02)
+#define DRIVER_VERSION			KERNEL_VERSION(0, 0x01, 0x03)
+
+/* verify default register values */
+//#define CHECK_REG_VALUE
 
 #ifndef V4L2_CID_DIGITAL_GAIN
 #define V4L2_CID_DIGITAL_GAIN		V4L2_CID_GAIN
@@ -184,9 +190,9 @@ static const struct regval s5kjn1_10bit_4080x3072_dphy_30fps_regs[] = {
 
 	{0x6028, 0x4000}, // Init setting
 	{0x6010, 0x0001},
-	//p5
+	{DELAY_MS, 5}, //Delay 5ms
 	{0x6226, 0x0001},
-	//p10
+	{DELAY_MS, 10}, //Delay 10ms
 
 	{0x6028, 0x2400}, //Global, Analog setting
 	{0x602A, 0x1354},
@@ -510,9 +516,9 @@ static const struct regval s5kjn1_10bit_8128x6144_dphy_10fps_regs[] = {
 
 	{0x6028, 0x4000}, // Init setting
 	{0x6010, 0x0001},
-	//p5
+	{DELAY_MS, 5}, //Delay 5ms
 	{0x6226, 0x0001},
-	//p10
+	{DELAY_MS, 10}, //Delay 10ms
 	{0x6028, 0x2400}, //Global, Analog setting
 	{0x11d2, 0x00FF}, //Global, Analog setting
 
@@ -987,6 +993,46 @@ static int s5kjn1_read_reg(struct i2c_client *client,
 	return 0;
 }
 
+/* Check Register value */
+#ifdef CHECK_REG_VALUE
+static int s5kjn1_reg_verify(struct i2c_client *client,
+			     const struct regval *regs)
+{
+	u32 i;
+	int ret = 0;
+	u32 value;
+
+	for (i = 0; ret == 0 && regs[i].addr != REG_NULL; i++) {
+		if (regs[i].addr == 0x6028 && regs[i].val == 0x4000) {
+			ret = s5kjn1_write_reg(client, regs[i].addr,
+					       S5KJN1_REG_VALUE_16BIT, regs[i].val);
+			if (ret)
+				dev_err(&client->dev, "%s failed !\n", __func__);
+			continue;
+		} else if (regs[i].addr == 0x6028 && regs[i].val == 0x2400) {
+			ret = s5kjn1_write_reg(client, 0x602C,
+					       S5KJN1_REG_VALUE_16BIT, regs[i].val);
+			if (ret)
+				dev_err(&client->dev, "%s failed !\n", __func__);
+			continue;
+		} else if (regs[i].addr == 0x602A) {
+			ret = s5kjn1_write_reg(client, 0x602E,
+					       S5KJN1_REG_VALUE_16BIT, regs[i].val);
+			if (ret)
+				dev_err(&client->dev, "%s failed !\n", __func__);
+			continue;
+		}
+		ret = s5kjn1_read_reg(client, regs[i].addr,
+			  S5KJN1_REG_VALUE_16BIT, &value);
+		if (value != regs[i].val) {
+			dev_info(&client->dev, "%s: 0x%04x is 0x%x instead of 0x%x\n",
+				 __func__, regs[i].addr, value, regs[i].val);
+		}
+	}
+	return ret;
+}
+#endif
+
 static int s5kjn1_get_reso_dist(const struct s5kjn1_mode *mode,
 				struct v4l2_mbus_framefmt *framefmt)
 {
@@ -1481,6 +1527,14 @@ static int __s5kjn1_start_stream(struct s5kjn1 *s5kjn1)
 			return ret;
 	}
 
+#ifdef CHECK_REG_VALUE
+	/* verify default values to make sure everything has */
+	/* been written correctly as expected */
+	dev_info(&s5kjn1->client->dev, "%s:Check register value!\n", __func__);
+	ret = s5kjn1_reg_verify(s5kjn1->client, s5kjn1->cur_mode->reg_list);
+	if (ret)
+		return ret;
+#endif
 	/* In case these controls are set before streaming */
 	ret = __v4l2_ctrl_handler_setup(&s5kjn1->ctrl_handler);
 	if (ret)
diff --git a/drivers/media/i2c/sc200ai.c b/drivers/media/i2c/sc200ai.c
index 0eca27f3b01c..e47fa1abb81b 100644
--- a/drivers/media/i2c/sc200ai.c
+++ b/drivers/media/i2c/sc200ai.c
@@ -1394,8 +1394,10 @@ static int __sc200ai_start_stream(struct sc200ai *sc200ai)
 static int __sc200ai_stop_stream(struct sc200ai *sc200ai)
 {
 	sc200ai->has_init_exp = false;
-	if (sc200ai->is_thunderboot)
+	if (sc200ai->is_thunderboot) {
 		sc200ai->is_first_streamoff = true;
+		pm_runtime_put(&sc200ai->client->dev);
+	}
 	return sc200ai_write_reg(sc200ai->client, SC200AI_REG_CTRL_MODE,
 				 SC200AI_REG_VALUE_08BIT, SC200AI_MODE_SW_STANDBY);
 }
@@ -2133,7 +2135,10 @@ static int sc200ai_probe(struct i2c_client *client,
 
 	pm_runtime_set_active(dev);
 	pm_runtime_enable(dev);
-	pm_runtime_idle(dev);
+	if (sc200ai->is_thunderboot)
+		pm_runtime_get_sync(dev);
+	else
+		pm_runtime_idle(dev);
 
 	return 0;
 
diff --git a/drivers/media/i2c/sc230ai.c b/drivers/media/i2c/sc230ai.c
index e7975c80fa85..bfd76fcfca2e 100644
--- a/drivers/media/i2c/sc230ai.c
+++ b/drivers/media/i2c/sc230ai.c
@@ -1107,8 +1107,10 @@ static int __sc230ai_start_stream(struct sc230ai *sc230ai)
 static int __sc230ai_stop_stream(struct sc230ai *sc230ai)
 {
 	sc230ai->has_init_exp = false;
-	if (sc230ai->is_thunderboot)
+	if (sc230ai->is_thunderboot) {
 		sc230ai->is_first_streamoff = true;
+		pm_runtime_put(&sc230ai->client->dev);
+	}
 	return sc230ai_write_reg(sc230ai->client, SC230AI_REG_CTRL_MODE,
 				 SC230AI_REG_VALUE_08BIT, SC230AI_MODE_SW_STANDBY);
 }
@@ -1744,7 +1746,10 @@ static int sc230ai_probe(struct i2c_client *client,
 
 	pm_runtime_set_active(dev);
 	pm_runtime_enable(dev);
-	pm_runtime_idle(dev);
+	if (sc230ai->is_thunderboot)
+		pm_runtime_get_sync(dev);
+	else
+		pm_runtime_idle(dev);
 
 	return 0;
 
diff --git a/drivers/media/i2c/sc3338.c b/drivers/media/i2c/sc3338.c
index d3435802fd03..9af90ce0cd24 100644
--- a/drivers/media/i2c/sc3338.c
+++ b/drivers/media/i2c/sc3338.c
@@ -855,8 +855,10 @@ static int __sc3338_start_stream(struct sc3338 *sc3338)
 static int __sc3338_stop_stream(struct sc3338 *sc3338)
 {
 	sc3338->has_init_exp = false;
-	if (sc3338->is_thunderboot)
+	if (sc3338->is_thunderboot) {
 		sc3338->is_first_streamoff = true;
+		pm_runtime_put(&sc3338->client->dev);
+	}
 	return sc3338_write_reg(sc3338->client, SC3338_REG_CTRL_MODE,
 				 SC3338_REG_VALUE_08BIT, SC3338_MODE_SW_STANDBY);
 }
@@ -1470,7 +1472,10 @@ static int sc3338_probe(struct i2c_client *client,
 
 	pm_runtime_set_active(dev);
 	pm_runtime_enable(dev);
-	pm_runtime_idle(dev);
+	if (sc3338->is_thunderboot)
+		pm_runtime_get_sync(dev);
+	else
+		pm_runtime_idle(dev);
 
 	return 0;
 
diff --git a/drivers/media/platform/rockchip/cif/capture.c b/drivers/media/platform/rockchip/cif/capture.c
index 75aaa69a74d4..6ead58576621 100644
--- a/drivers/media/platform/rockchip/cif/capture.c
+++ b/drivers/media/platform/rockchip/cif/capture.c
@@ -149,6 +149,13 @@ static const struct cif_output_fmt out_fmts[] = {
 		.bpp = { 24 },
 		.csi_fmt_val = CSI_WRDDR_TYPE_RGB888,
 		.fmt_type = CIF_FMT_TYPE_RAW,
+	}, {
+		.fourcc = V4L2_PIX_FMT_BGR24,
+		.cplanes = 1,
+		.mplanes = 1,
+		.bpp = { 24 },
+		.csi_fmt_val = CSI_WRDDR_TYPE_RGB888,
+		.fmt_type = CIF_FMT_TYPE_RAW,
 	}, {
 		.fourcc = V4L2_PIX_FMT_RGB565,
 		.cplanes = 1,
@@ -476,6 +483,10 @@ static const struct cif_input_fmt in_fmts[] = {
 		.mbus_code	= MEDIA_BUS_FMT_RGB888_1X24,
 		.csi_fmt_val	= CSI_WRDDR_TYPE_RGB888,
 		.field		= V4L2_FIELD_NONE,
+	}, {
+		.mbus_code	= MEDIA_BUS_FMT_BGR888_1X24,
+		.csi_fmt_val	= CSI_WRDDR_TYPE_RGB888,
+		.field		= V4L2_FIELD_NONE,
 	}, {
 		.mbus_code	= MEDIA_BUS_FMT_RGB565_1X16,
 		.csi_fmt_val	= CSI_WRDDR_TYPE_RGB565,
@@ -607,18 +618,21 @@ static unsigned char get_data_type(u32 pixelformat, u8 cmd_mode_en, u8 dsi_input
 	case MEDIA_BUS_FMT_SGBRG8_1X8:
 	case MEDIA_BUS_FMT_SGRBG8_1X8:
 	case MEDIA_BUS_FMT_SRGGB8_1X8:
+	case MEDIA_BUS_FMT_Y8_1X8:
 		return 0x2a;
 	/* csi raw10 */
 	case MEDIA_BUS_FMT_SBGGR10_1X10:
 	case MEDIA_BUS_FMT_SGBRG10_1X10:
 	case MEDIA_BUS_FMT_SGRBG10_1X10:
 	case MEDIA_BUS_FMT_SRGGB10_1X10:
+	case MEDIA_BUS_FMT_Y10_1X10:
 		return 0x2b;
 	/* csi raw12 */
 	case MEDIA_BUS_FMT_SBGGR12_1X12:
 	case MEDIA_BUS_FMT_SGBRG12_1X12:
 	case MEDIA_BUS_FMT_SGRBG12_1X12:
 	case MEDIA_BUS_FMT_SRGGB12_1X12:
+	case MEDIA_BUS_FMT_Y12_1X12:
 		return 0x2c;
 	/* csi uyvy 422 */
 	case MEDIA_BUS_FMT_UYVY8_2X8:
@@ -627,6 +641,7 @@ static unsigned char get_data_type(u32 pixelformat, u8 cmd_mode_en, u8 dsi_input
 	case MEDIA_BUS_FMT_YVYU8_2X8:
 		return 0x1e;
 	case MEDIA_BUS_FMT_RGB888_1X24:
+	case MEDIA_BUS_FMT_BGR888_1X24:
 		if (dsi_input) {
 			if (cmd_mode_en) /* dsi command mode*/
 				return 0x39;
@@ -2999,6 +3014,7 @@ static int rkcif_csi_get_output_type_mask(struct rkcif_stream *stream)
 		mask = CSI_WRDDR_TYPE_YUV_PACKET | CSI_YUV_OUTPUT_ORDER_VYUY;
 		break;
 	case V4L2_PIX_FMT_RGB24:
+	case V4L2_PIX_FMT_BGR24:
 	case V4L2_PIX_FMT_RGB565:
 	case V4L2_PIX_FMT_BGR666:
 		mask = CSI_WRDDR_TYPE_RAW_COMPACT;
@@ -3083,6 +3099,7 @@ static int rkcif_lvds_get_output_type_mask(struct rkcif_stream *stream)
 			(CSI_YUV_OUTPUT_ORDER_VYUY << yuvout_offset);
 		break;
 	case V4L2_PIX_FMT_RGB24:
+	case V4L2_PIX_FMT_BGR24:
 	case V4L2_PIX_FMT_RGB565:
 	case V4L2_PIX_FMT_BGR666:
 		mask = CSI_WRDDR_TYPE_RAW_COMPACT << wr_type_offset;
@@ -3872,7 +3889,8 @@ static int rkcif_create_dummy_buf(struct rkcif_stream *stream)
 				if (tmp_dev->terminal_sensor.sd) {
 					input_fmt = get_input_fmt(tmp_dev->terminal_sensor.sd,
 								  &rect, i, &csi_info);
-					if (input_fmt && input_fmt->mbus_code == MEDIA_BUS_FMT_RGB888_1X24)
+					if (input_fmt && (input_fmt->mbus_code == MEDIA_BUS_FMT_RGB888_1X24 ||
+						input_fmt->mbus_code == MEDIA_BUS_FMT_BGR888_1X24))
 						size = rect.width * rect.height * 3;
 					else
 						size = rect.width * rect.height * 2;
@@ -4372,6 +4390,7 @@ static u32 rkcif_align_bits_per_pixel(struct rkcif_stream *stream,
 				bpp = fmt->bpp[plane_index + 1];
 			break;
 		case V4L2_PIX_FMT_RGB24:
+		case V4L2_PIX_FMT_BGR24:
 		case V4L2_PIX_FMT_RGB565:
 		case V4L2_PIX_FMT_BGR666:
 		case V4L2_PIX_FMT_SRGGB8:
@@ -4676,6 +4695,7 @@ static int rkcif_dvp_get_output_type_mask(struct rkcif_stream *stream)
 		       (CSI_YUV_OUTPUT_ORDER_VYUY << 1);
 		break;
 	case V4L2_PIX_FMT_RGB24:
+	case V4L2_PIX_FMT_BGR24:
 	case V4L2_PIX_FMT_RGB565:
 	case V4L2_PIX_FMT_BGR666:
 		mask = CSI_WRDDR_TYPE_RAW_COMPACT << 11;
@@ -8590,13 +8610,12 @@ void rkcif_enable_dma_capture(struct rkcif_stream *stream, bool is_only_enable)
 							       RKCIF_YUV_ADDR_STATE_INIT,
 							       stream->id);
 		}
-	} else if (stream->cur_stream_mode == RKCIF_STREAM_MODE_CAPTURE) {
-		if (mbus_cfg->type == V4L2_MBUS_CSI2_DPHY ||
-		    mbus_cfg->type == V4L2_MBUS_CSI2_CPHY)
-			rkcif_write_register_or(cif_dev, CIF_REG_MIPI_LVDS_CTRL, 0x000A0000);
-		else
-			rkcif_write_register_or(cif_dev, CIF_REG_DVP_CTRL, 0x000A0000);
 	}
+	if (mbus_cfg->type == V4L2_MBUS_CSI2_DPHY ||
+	    mbus_cfg->type == V4L2_MBUS_CSI2_CPHY)
+		rkcif_write_register_or(cif_dev, CIF_REG_MIPI_LVDS_CTRL, 0x00010000);
+	else
+		rkcif_write_register_or(cif_dev, CIF_REG_DVP_CTRL, 0x00010000);
 	if (mbus_cfg->type == V4L2_MBUS_CSI2_DPHY ||
 	    mbus_cfg->type == V4L2_MBUS_CSI2_CPHY) {
 		val = rkcif_read_register(cif_dev, get_reg_index_of_id_ctrl0(stream->id));
@@ -9071,8 +9090,7 @@ void rkcif_irq_pingpong_v1(struct rkcif_device *cif_dev)
 			    cif_dev->sditf[0]->mode.rdbk_mode)
 				stream->buf_wake_up_cnt++;
 
-			if (stream->stopping &&
-			    !(stream->cur_stream_mode & RKCIF_STREAM_MODE_TOISP)) {
+			if (stream->stopping && (!stream->dma_en)) {
 				rkcif_stream_stop(stream);
 				stream->stopping = false;
 				wake_up(&stream->wq_stopped);
@@ -9181,6 +9199,12 @@ void rkcif_irq_pingpong_v1(struct rkcif_device *cif_dev)
 					spin_unlock_irqrestore(&stream->fps_lock, flags);
 				}
 				stream->is_in_vblank = false;
+				if (stream->stopping && stream->dma_en) {
+					if (stream->dma_en & RKCIF_DMAEN_BY_VICAP)
+						stream->to_stop_dma = RKCIF_DMAEN_BY_VICAP;
+					else if (stream->dma_en & RKCIF_DMAEN_BY_ISP)
+						stream->to_stop_dma = RKCIF_DMAEN_BY_ISP;
+				}
 				if (stream->to_stop_dma) {
 					ret = rkcif_stop_dma_capture(stream);
 					if (!ret)
diff --git a/drivers/media/platform/rockchip/cif/subdev-itf.c b/drivers/media/platform/rockchip/cif/subdev-itf.c
index 5c838395570a..d37a5a713689 100644
--- a/drivers/media/platform/rockchip/cif/subdev-itf.c
+++ b/drivers/media/platform/rockchip/cif/subdev-itf.c
@@ -450,7 +450,7 @@ static int sditf_channel_enable(struct sditf_priv *priv, int user)
 	if (user == 0) {
 		if (priv->toisp_inf.link_mode == TOISP_UNITE)
 			width = priv->cap_info.width / 2 + RKMOUDLE_UNITE_EXTEND_PIXEL;
-		rkcif_write_register_or(cif_dev, CIF_REG_TOISP0_CTRL, ctrl_val);
+		rkcif_write_register(cif_dev, CIF_REG_TOISP0_CTRL, ctrl_val);
 		if (width && height) {
 			rkcif_write_register(cif_dev, CIF_REG_TOISP0_CROP,
 				offset_x | (offset_y << 16));
@@ -464,7 +464,7 @@ static int sditf_channel_enable(struct sditf_priv *priv, int user)
 			offset_x = priv->cap_info.width / 2 - RKMOUDLE_UNITE_EXTEND_PIXEL;
 			width = priv->cap_info.width / 2 + RKMOUDLE_UNITE_EXTEND_PIXEL;
 		}
-		rkcif_write_register_or(cif_dev, CIF_REG_TOISP1_CTRL, ctrl_val);
+		rkcif_write_register(cif_dev, CIF_REG_TOISP1_CTRL, ctrl_val);
 		if (width && height) {
 			rkcif_write_register(cif_dev, CIF_REG_TOISP1_CROP,
 				offset_x | (offset_y << 16));
@@ -531,12 +531,22 @@ void sditf_change_to_online(struct sditf_priv *priv)
 		sditf_channel_enable(priv, 0);
 		sditf_channel_enable(priv, 1);
 	}
-	if (priv->hdr_cfg.hdr_mode == NO_HDR)
+	if (priv->hdr_cfg.hdr_mode == NO_HDR) {
 		rkcif_free_rx_buf(&cif_dev->stream[0], priv->buf_num);
-	else if (priv->hdr_cfg.hdr_mode == HDR_X2)
+		cif_dev->stream[0].is_line_wake_up = false;
+	} else if (priv->hdr_cfg.hdr_mode == HDR_X2) {
 		rkcif_free_rx_buf(&cif_dev->stream[1], priv->buf_num);
-	else if (priv->hdr_cfg.hdr_mode == HDR_X3)
+		cif_dev->stream[0].is_line_wake_up = false;
+		cif_dev->stream[1].is_line_wake_up = false;
+	} else if (priv->hdr_cfg.hdr_mode == HDR_X3) {
 		rkcif_free_rx_buf(&cif_dev->stream[2], priv->buf_num);
+		cif_dev->stream[0].is_line_wake_up = false;
+		cif_dev->stream[1].is_line_wake_up = false;
+		cif_dev->stream[2].is_line_wake_up = false;
+	}
+	cif_dev->wait_line_cache = 0;
+	cif_dev->wait_line = 0;
+	cif_dev->wait_line_bak = 0;
 }
 
 static void sditf_check_capture_mode(struct rkcif_device *cif_dev)
diff --git a/drivers/media/platform/rockchip/isp/capture.c b/drivers/media/platform/rockchip/isp/capture.c
index 7bb7a8f6cd67..f186229c807f 100644
--- a/drivers/media/platform/rockchip/isp/capture.c
+++ b/drivers/media/platform/rockchip/isp/capture.c
@@ -366,7 +366,7 @@ void rkisp_config_dmatx_valid_buf(struct rkisp_device *dev)
 			continue;
 		for (j = RKISP_STREAM_DMATX0; j < RKISP_MAX_STREAM; j++) {
 			stream = &isp->cap_dev.stream[j];
-			if (!stream->linked || stream->u.dmatx.is_config)
+			if (!stream->linked || stream->curr_buf || stream->next_buf)
 				continue;
 			mi_set_y_addr(stream, hw->dummy_buf.dma_addr);
 		}
diff --git a/drivers/media/platform/rockchip/isp/capture_v30.c b/drivers/media/platform/rockchip/isp/capture_v30.c
index f11c99a3e4dc..0f1353774126 100644
--- a/drivers/media/platform/rockchip/isp/capture_v30.c
+++ b/drivers/media/platform/rockchip/isp/capture_v30.c
@@ -917,7 +917,7 @@ static void stream_self_update(struct rkisp_stream *stream)
 		return;
 	}
 
-	rkisp_unite_set_bits(dev, ISP3X_MI_WR_XTD_FORMAT_CTRL, mask, val, false, is_unite);
+	rkisp_unite_set_bits(dev, ISP3X_MI_WR_CTRL2, mask, val, false, is_unite);
 }
 
 static int mi_frame_start(struct rkisp_stream *stream, u32 mis)
diff --git a/drivers/media/platform/rockchip/isp/capture_v32.c b/drivers/media/platform/rockchip/isp/capture_v32.c
index b3b35eb327bf..6ef94a149be3 100644
--- a/drivers/media/platform/rockchip/isp/capture_v32.c
+++ b/drivers/media/platform/rockchip/isp/capture_v32.c
@@ -1357,7 +1357,8 @@ static int rkisp_start(struct rkisp_stream *stream)
 		if (ret)
 			return ret;
 	}
-	stream_self_update(stream);
+	if (dev->hw_dev->is_single)
+		stream_self_update(stream);
 	if (stream->ops->enable_mi)
 		stream->ops->enable_mi(stream);
 
diff --git a/drivers/media/platform/rockchip/isp/isp_rockit.c b/drivers/media/platform/rockchip/isp/isp_rockit.c
index 149fbda73376..32fed276e21f 100644
--- a/drivers/media/platform/rockchip/isp/isp_rockit.c
+++ b/drivers/media/platform/rockchip/isp/isp_rockit.c
@@ -369,6 +369,10 @@ int rkisp_rockit_resume_stream(struct rockit_cfg *input_rockit_cfg)
 		pr_err("stream id %d start failed\n", stream->id);
 		return -EINVAL;
 	}
+	if (stream->ispdev->isp_state == ISP_STOP) {
+		stream->ispdev->isp_state = ISP_START;
+		rkisp_rdbk_trigger_event(stream->ispdev, T_CMD_QUEUE, NULL);
+	}
 
 	return 0;
 }
diff --git a/drivers/media/platform/rockchip/isp/rkisp.c b/drivers/media/platform/rockchip/isp/rkisp.c
index 5859c1d85439..6afa85ce16b8 100644
--- a/drivers/media/platform/rockchip/isp/rkisp.c
+++ b/drivers/media/platform/rockchip/isp/rkisp.c
@@ -2722,10 +2722,10 @@ static void rkisp_global_update_mi(struct rkisp_device *dev)
 	struct rkisp_stream *stream;
 	int i;
 
+	rkisp_stats_first_ddr_config(&dev->stats_vdev);
 	if (dev->hw_dev->is_mi_update)
 		return;
 
-	rkisp_stats_first_ddr_config(&dev->stats_vdev);
 	rkisp_config_dmatx_valid_buf(dev);
 
 	force_cfg_update(dev);
@@ -2737,7 +2737,7 @@ static void rkisp_global_update_mi(struct rkisp_device *dev)
 			if (stream->id == RKISP_STREAM_VIR ||
 			    stream->id == RKISP_STREAM_LUMA)
 				continue;
-			if (stream->streaming)
+			if (stream->streaming && !stream->next_buf)
 				stream->ops->frame_end(stream);
 		}
 	}
diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
index 9d3d6ca083c2..1ec588cae247 100644
--- a/drivers/mfd/Kconfig
+++ b/drivers/mfd/Kconfig
@@ -930,15 +930,6 @@ config MFD_MAX96745
 	help
 	  Say yes here to add support for Maxim Semiconductor MAX96745.
 
-config MFD_MAX96752F
-	tristate "Maxim Semiconductor MAX96752F GMSL2 Deserializer Support"
-	depends on I2C
-	select MFD_CORE
-	select REGMAP_I2C
-	select I2C_MUX
-	help
-	  Say yes here to add support for Maxim Semiconductor MAX96752F.
-
 config MFD_MAX96755F
 	tristate "Maxim Semiconductor MAX96755 GMSL2 Serializer Support"
 	depends on I2C
@@ -947,15 +938,6 @@ config MFD_MAX96755F
 	help
 	  Say yes here to add support for Maxim Semiconductor MAX96755.
 
-config MFD_MAX96776
-	tristate "Maxim Semiconductor MAX96776 GMSL2 Deserializer Support"
-	depends on I2C
-	select MFD_CORE
-	select REGMAP_I2C
-	select I2C_MUX
-	help
-	  Say yes here to add support for Maxim Semiconductor MAX96776.
-
 config MFD_MT6360
 	tristate "Mediatek MT6360 SubPMIC"
 	select MFD_CORE
diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
index 6ae9047e3652..1b45f971e083 100644
--- a/drivers/mfd/Makefile
+++ b/drivers/mfd/Makefile
@@ -171,9 +171,7 @@ obj-$(CONFIG_MFD_MAX8925)	+= max8925.o
 obj-$(CONFIG_MFD_MAX8997)	+= max8997.o max8997-irq.o
 obj-$(CONFIG_MFD_MAX8998)	+= max8998.o max8998-irq.o
 obj-$(CONFIG_MFD_MAX96745)	+= max96745.o
-obj-$(CONFIG_MFD_MAX96752F)	+= max96752f.o
 obj-$(CONFIG_MFD_MAX96755F)	+= max96755f.o
-obj-$(CONFIG_MFD_MAX96776)	+= max96776.o
 
 obj-$(CONFIG_MFD_MP2629)	+= mp2629.o
 
diff --git a/drivers/mfd/max96752f.c b/drivers/mfd/max96752f.c
deleted file mode 100644
index 4fe239f10fb5..000000000000
--- a/drivers/mfd/max96752f.c
+++ /dev/null
@@ -1,205 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Maxim MAX96752F MFD driver
- *
- * Copyright (C) 2022 Rockchip Electronics Co. Ltd.
- */
-
-#include <linux/module.h>
-#include <linux/init.h>
-#include <linux/i2c.h>
-#include <linux/i2c-mux.h>
-#include <linux/gpio/consumer.h>
-#include <linux/regmap.h>
-#include <linux/mfd/core.h>
-#include <linux/mfd/max96752f.h>
-
-static const struct mfd_cell max96752f_devs[] = {
-	{
-		.name = "max96752f-pinctrl",
-		.of_compatible = "maxim,max96752f-pinctrl",
-	}, {
-		.name = "max96752f-gpio",
-		.of_compatible = "maxim,max96752f-gpio",
-	}, {
-		.name = "max96752f-bridge",
-		.of_compatible = "maxim,max96752f-bridge",
-	},
-};
-
-static int max96752f_select(struct i2c_mux_core *muxc, u32 chan)
-{
-	return 0;
-}
-
-static const struct regmap_config max96752f_regmap_config = {
-	.name = "max96752f",
-	.reg_bits = 16,
-	.val_bits = 8,
-	.max_register = 0x25d,
-};
-
-static const unsigned short addr_list[] = {
-	0x48, 0x4a, 0x4c, 0x68, 0x6a, 0x6c, 0x28, 0x2a, I2C_CLIENT_END
-};
-
-void max96752f_init(struct max96752f *max96752f)
-{
-	struct i2c_client *client = max96752f->client;
-	u16 addr = client->addr;
-	u32 id;
-	int i, ret;
-
-	for (i = 0; addr_list[i] != I2C_CLIENT_END; i++) {
-		client->addr = addr_list[i];
-		ret = regmap_read(max96752f->regmap, 0x000d, &id);
-		if (ret < 0)
-			continue;
-
-		if (id == 0x82) {
-			regmap_write(max96752f->regmap, 0x0000, addr << 1);
-			break;
-		}
-	}
-
-	client->addr = addr;
-
-	regmap_update_bits(max96752f->regmap, 0x0050, STR_SEL,
-			   FIELD_PREP(STR_SEL, max96752f->stream_id));
-	regmap_update_bits(max96752f->regmap, 0x0073, TX_SRC_ID,
-			   FIELD_PREP(TX_SRC_ID, max96752f->stream_id));
-}
-EXPORT_SYMBOL(max96752f_init);
-
-static void max96752f_power_on(struct max96752f *max96752f)
-{
-	if (max96752f->enable_gpio) {
-		gpiod_direction_output(max96752f->enable_gpio, 1);
-		msleep(500);
-	}
-}
-
-static void max96752f_power_off(struct max96752f *max96752f)
-{
-	if (max96752f->enable_gpio)
-		gpiod_direction_output(max96752f->enable_gpio, 0);
-}
-
-static int max96752f_i2c_probe(struct i2c_client *client)
-{
-	struct device *dev = &client->dev;
-	struct device_node *child;
-	struct max96752f *max96752f;
-	unsigned int nr = 0;
-	int ret;
-
-	for_each_available_child_of_node(dev->of_node, child) {
-		if (!of_find_property(child, "reg", NULL))
-			continue;
-
-		nr++;
-	}
-
-	max96752f = devm_kzalloc(dev, sizeof(*max96752f), GFP_KERNEL);
-	if (!max96752f)
-		return -ENOMEM;
-
-	max96752f->muxc = i2c_mux_alloc(client->adapter, dev, nr, 0,
-				       I2C_MUX_LOCKED, max96752f_select, NULL);
-	if (!max96752f->muxc)
-		return -ENOMEM;
-
-	max96752f->dev = dev;
-	max96752f->client = client;
-
-	max96752f->enable_gpio = devm_gpiod_get_optional(dev, "enable",
-							 GPIOD_ASIS);
-	if (IS_ERR(max96752f->enable_gpio))
-		return dev_err_probe(dev, PTR_ERR(max96752f->enable_gpio),
-				     "failed to get enable GPIO\n");
-
-	ret = device_property_read_u32(dev->parent, "reg", &max96752f->stream_id);
-	if (ret)
-		return dev_err_probe(dev, ret, "failed to get gmsl id\n");
-
-	i2c_set_clientdata(client, max96752f);
-
-	max96752f->regmap = devm_regmap_init_i2c(client,
-						 &max96752f_regmap_config);
-	if (IS_ERR(max96752f->regmap))
-		return dev_err_probe(dev, PTR_ERR(max96752f->regmap),
-				     "failed to initialize regmap\n");
-
-	max96752f_power_on(max96752f);
-	max96752f_init(max96752f);
-
-	ret = devm_mfd_add_devices(dev, PLATFORM_DEVID_AUTO, max96752f_devs,
-				   ARRAY_SIZE(max96752f_devs), NULL, 0, NULL);
-	if (ret)
-		return ret;
-
-	for_each_available_child_of_node(dev->of_node, child) {
-		if (of_property_read_u32(child, "reg", &nr))
-			continue;
-
-		ret = i2c_mux_add_adapter(max96752f->muxc, 0, nr, 0);
-		if (ret) {
-			i2c_mux_del_adapters(max96752f->muxc);
-			return ret;
-		}
-	}
-
-	return 0;
-}
-
-static void max96752f_i2c_shutdown(struct i2c_client *client)
-{
-	struct max96752f *max96752f = i2c_get_clientdata(client);
-
-	regmap_update_bits(max96752f->regmap, 0x0010, RESET_ALL,
-			   FIELD_PREP(RESET_ALL, 1));
-
-	max96752f_power_off(max96752f);
-}
-
-static int __maybe_unused max96752f_suspend(struct device *dev)
-{
-	struct max96752f *max96752f = dev_get_drvdata(dev);
-
-	max96752f_power_off(max96752f);
-
-	return 0;
-}
-
-static int __maybe_unused max96752f_resume(struct device *dev)
-{
-	struct max96752f *max96752f = dev_get_drvdata(dev);
-
-	max96752f_power_on(max96752f);
-
-	return 0;
-}
-
-static SIMPLE_DEV_PM_OPS(max96752f_pm_ops, max96752f_suspend, max96752f_resume);
-
-static const struct of_device_id max96752f_of_match[] = {
-	{ .compatible = "maxim,max96752f", },
-	{}
-};
-MODULE_DEVICE_TABLE(of, max96752f_of_match);
-
-static struct i2c_driver max96752f_i2c_driver = {
-	.driver = {
-		.name = "max96752f",
-		.of_match_table = of_match_ptr(max96752f_of_match),
-		.pm = &max96752f_pm_ops,
-	},
-	.probe_new = max96752f_i2c_probe,
-	.shutdown = max96752f_i2c_shutdown,
-};
-
-module_i2c_driver(max96752f_i2c_driver);
-
-MODULE_AUTHOR("Wyon Bi <bivvy.bi@rock-chips.com>");
-MODULE_DESCRIPTION("Maxim MAX96752F MFD driver");
-MODULE_LICENSE("GPL");
diff --git a/drivers/mfd/max96776.c b/drivers/mfd/max96776.c
deleted file mode 100644
index abea0a25bfec..000000000000
--- a/drivers/mfd/max96776.c
+++ /dev/null
@@ -1,194 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Maxim MAX96776 MFD driver
- *
- * Copyright (C) 2022 Rockchip Electronics Co. Ltd.
- */
-
-#include <linux/module.h>
-#include <linux/init.h>
-#include <linux/i2c.h>
-#include <linux/i2c-mux.h>
-#include <linux/gpio/consumer.h>
-#include <linux/regmap.h>
-#include <linux/mfd/core.h>
-#include <linux/mfd/max96752f.h>
-
-struct max96776 {
-	struct device *dev;
-	struct regmap *regmap;
-	struct i2c_client *client;
-	struct i2c_mux_core *muxc;
-	struct gpio_desc *enable_gpio;
-	u32 stream_id;
-};
-
-static const struct mfd_cell max96776_devs[] = {
-	{
-		.name = "max96776-bridge",
-		.of_compatible = "maxim,max96776-bridge",
-	},
-};
-
-static int max96776_select(struct i2c_mux_core *muxc, u32 chan)
-{
-	return 0;
-}
-
-static const struct regmap_range max96776_readable_ranges[] = {
-	regmap_reg_range(0x0000, 0x0026),
-	regmap_reg_range(0x0029, 0x002c),
-	regmap_reg_range(0x0050, 0x0050),
-	regmap_reg_range(0x0100, 0x0100),
-	regmap_reg_range(0x0103, 0x0103),
-	regmap_reg_range(0x0108, 0x0108),
-	regmap_reg_range(0x0600, 0x0600),
-	regmap_reg_range(0x07f0, 0x07f1),
-	regmap_reg_range(0x1700, 0x1700),
-	regmap_reg_range(0x4100, 0x4100),
-	regmap_reg_range(0x6230, 0x6230),
-	regmap_reg_range(0xe75e, 0xe75e),
-	regmap_reg_range(0xe776, 0xe7bf),
-};
-
-static const struct regmap_access_table max96776_readable_table = {
-	.yes_ranges = max96776_readable_ranges,
-	.n_yes_ranges = ARRAY_SIZE(max96776_readable_ranges),
-};
-
-static const struct regmap_config max96776_regmap_config = {
-	.name = "max96776",
-	.reg_bits = 16,
-	.val_bits = 8,
-	.rd_table = &max96776_readable_table,
-	.max_register = 0xff02,
-};
-
-static void max96776_power_on(struct max96776 *max96776)
-{
-	if (max96776->enable_gpio) {
-		gpiod_direction_output(max96776->enable_gpio, 1);
-		msleep(500);
-	}
-}
-
-static void max96776_power_off(struct max96776 *max96776)
-{
-	if (max96776->enable_gpio)
-		gpiod_direction_output(max96776->enable_gpio, 0);
-}
-
-static int max96776_i2c_probe(struct i2c_client *client)
-{
-	struct device *dev = &client->dev;
-	struct device_node *child;
-	struct max96776 *max96776;
-	unsigned int nr = 0;
-	int ret;
-
-	for_each_available_child_of_node(dev->of_node, child) {
-		if (!of_find_property(child, "reg", NULL))
-			continue;
-
-		nr++;
-	}
-
-	max96776 = devm_kzalloc(dev, sizeof(*max96776), GFP_KERNEL);
-	if (!max96776)
-		return -ENOMEM;
-
-	max96776->muxc = i2c_mux_alloc(client->adapter, dev, nr, 0,
-				       I2C_MUX_LOCKED, max96776_select, NULL);
-	if (!max96776->muxc)
-		return -ENOMEM;
-
-	max96776->dev = dev;
-	max96776->client = client;
-
-	max96776->enable_gpio = devm_gpiod_get_optional(dev, "enable",
-							 GPIOD_ASIS);
-	if (IS_ERR(max96776->enable_gpio))
-		return dev_err_probe(dev, PTR_ERR(max96776->enable_gpio),
-				     "failed to get enable GPIO\n");
-
-	ret = device_property_read_u32(dev->parent, "reg", &max96776->stream_id);
-	if (ret)
-		return dev_err_probe(dev, ret, "failed to get gmsl id\n");
-
-	i2c_set_clientdata(client, max96776);
-
-	max96776->regmap = devm_regmap_init_i2c(client,
-						 &max96776_regmap_config);
-	if (IS_ERR(max96776->regmap))
-		return dev_err_probe(dev, PTR_ERR(max96776->regmap),
-				     "failed to initialize regmap\n");
-
-	max96776_power_on(max96776);
-
-	ret = devm_mfd_add_devices(dev, PLATFORM_DEVID_AUTO, max96776_devs,
-				   ARRAY_SIZE(max96776_devs), NULL, 0, NULL);
-	if (ret)
-		return ret;
-
-	for_each_available_child_of_node(dev->of_node, child) {
-		if (of_property_read_u32(child, "reg", &nr))
-			continue;
-
-		ret = i2c_mux_add_adapter(max96776->muxc, 0, nr, 0);
-		if (ret) {
-			i2c_mux_del_adapters(max96776->muxc);
-			return ret;
-		}
-	}
-
-	return 0;
-}
-
-static void max96776_i2c_shutdown(struct i2c_client *client)
-{
-	struct max96776 *max96776 = i2c_get_clientdata(client);
-
-	max96776_power_off(max96776);
-}
-
-static int __maybe_unused max96776_suspend(struct device *dev)
-{
-	struct max96776 *max96776 = dev_get_drvdata(dev);
-
-	max96776_power_off(max96776);
-
-	return 0;
-}
-
-static int __maybe_unused max96776_resume(struct device *dev)
-{
-	struct max96776 *max96776 = dev_get_drvdata(dev);
-
-	max96776_power_on(max96776);
-
-	return 0;
-}
-
-static SIMPLE_DEV_PM_OPS(max96776_pm_ops, max96776_suspend, max96776_resume);
-
-static const struct of_device_id max96776_of_match[] = {
-	{ .compatible = "maxim,max96776", },
-	{}
-};
-MODULE_DEVICE_TABLE(of, max96776_of_match);
-
-static struct i2c_driver max96776_i2c_driver = {
-	.driver = {
-		.name = "max96776",
-		.of_match_table = of_match_ptr(max96776_of_match),
-		.pm = &max96776_pm_ops,
-	},
-	.probe_new = max96776_i2c_probe,
-	.shutdown = max96776_i2c_shutdown,
-};
-
-module_i2c_driver(max96776_i2c_driver);
-
-MODULE_AUTHOR("Guochun Huang <hero.huang@rock-chips.com>");
-MODULE_DESCRIPTION("Maxim max96776 MFD driver");
-MODULE_LICENSE("GPL");
diff --git a/drivers/mmc/core/mmc_ops.c b/drivers/mmc/core/mmc_ops.c
index 2715e5031843..db9474c9b740 100644
--- a/drivers/mmc/core/mmc_ops.c
+++ b/drivers/mmc/core/mmc_ops.c
@@ -184,6 +184,12 @@ int mmc_send_op_cond(struct mmc_host *host, u32 ocr, u32 *rocr)
 		if (err)
 			break;
 
+#ifdef CONFIG_ROCKCHIP_THUNDER_BOOT
+		/* if we're just probing, do a single pass */
+		if (ocr == 0)
+			break;
+#endif
+
 		/*
 		 * According to eMMC specification v5.1 section A6.1, the R3
 		 * response value should be 0x00FF8080, 0x40FF8080, 0x80FF8080
diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
index 9daef0237382..3c308ba3aaeb 100644
--- a/drivers/mmc/host/Kconfig
+++ b/drivers/mmc/host/Kconfig
@@ -207,6 +207,7 @@ config MMC_SDHCI_OF_DWCMSHC
 	depends on MMC_SDHCI_PLTFM
 	depends on OF
 	depends on COMMON_CLK
+	select MMC_HSQ
 	help
 	  This selects Synopsys DesignWare Cores Mobile Storage Controller
 	  support.
diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c
index a77e439f35ca..df385fe6dd13 100644
--- a/drivers/mmc/host/dw_mmc.c
+++ b/drivers/mmc/host/dw_mmc.c
@@ -3618,9 +3618,7 @@ int dw_mci_runtime_resume(struct device *dev)
 	mci_writel(host, TMOUT, 0xFFFFFFFF);
 
 	mci_writel(host, RINTSTS, 0xFFFFFFFF);
-	mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER |
-		   SDMMC_INT_TXDR | SDMMC_INT_RXDR |
-		   DW_MCI_ERROR_FLAGS);
+	mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER | DW_MCI_ERROR_FLAGS);
 	mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE);
 
 	if (host->is_rv1106_sd) {
diff --git a/drivers/mmc/host/mmc_hsq.c b/drivers/mmc/host/mmc_hsq.c
index a5e05ed0fda3..9d35453e7371 100644
--- a/drivers/mmc/host/mmc_hsq.c
+++ b/drivers/mmc/host/mmc_hsq.c
@@ -34,7 +34,7 @@ static void mmc_hsq_pump_requests(struct mmc_hsq *hsq)
 	spin_lock_irqsave(&hsq->lock, flags);
 
 	/* Make sure we are not already running a request now */
-	if (hsq->mrq) {
+	if (hsq->mrq || hsq->recovery_halt) {
 		spin_unlock_irqrestore(&hsq->lock, flags);
 		return;
 	}
diff --git a/drivers/mmc/host/sdhci-of-dwcmshc.c b/drivers/mmc/host/sdhci-of-dwcmshc.c
index 3cb631766b80..fc3b19e87542 100644
--- a/drivers/mmc/host/sdhci-of-dwcmshc.c
+++ b/drivers/mmc/host/sdhci-of-dwcmshc.c
@@ -20,6 +20,7 @@
 #include <linux/sizes.h>
 
 #include "sdhci-pltfm.h"
+#include "mmc_hsq.h"
 
 #define SDHCI_DWCMSHC_ARG2_STUFF	GENMASK(31, 16)
 
@@ -331,6 +332,14 @@ static void rockchip_sdhci_reset(struct sdhci_host *host, u8 mask)
 	sdhci_reset(host, mask);
 }
 
+static void sdhci_dwcmshc_request_done(struct sdhci_host *host, struct mmc_request *mrq)
+{
+	if (mmc_hsq_finalize_request(host->mmc, mrq))
+		return;
+
+	mmc_request_done(host->mmc, mrq);
+}
+
 static const struct sdhci_ops sdhci_dwcmshc_ops = {
 	.set_clock		= sdhci_set_clock,
 	.set_bus_width		= sdhci_set_bus_width,
@@ -347,6 +356,7 @@ static const struct sdhci_ops sdhci_dwcmshc_rk_ops = {
 	.get_max_clock		= sdhci_pltfm_clk_get_max_clock,
 	.reset			= rockchip_sdhci_reset,
 	.adma_write_desc	= dwcmshc_adma_write_desc,
+	.request_done		= sdhci_dwcmshc_request_done,
 };
 
 static const struct sdhci_pltfm_data sdhci_dwcmshc_pdata = {
@@ -441,6 +451,7 @@ static int dwcmshc_probe(struct platform_device *pdev)
 	struct sdhci_host *host;
 	struct dwcmshc_priv *priv;
 	const struct dwcmshc_driver_data *drv_data;
+	struct mmc_hsq *hsq;
 	int err;
 	u32 extra;
 
@@ -494,6 +505,16 @@ static int dwcmshc_probe(struct platform_device *pdev)
 	host->mmc_host_ops.request = dwcmshc_request;
 	host->mmc_host_ops.hs400_enhanced_strobe = dwcmshc_hs400_enhanced_strobe;
 
+	hsq = devm_kzalloc(&pdev->dev, sizeof(*hsq), GFP_KERNEL);
+	if (!hsq) {
+		err = -ENOMEM;
+		goto err_clk;
+	}
+
+	err = mmc_hsq_init(hsq, host->mmc);
+	if (err)
+		goto err_clk;
+
 	err = sdhci_add_host(host);
 	if (err)
 		goto err_clk;
@@ -550,6 +571,8 @@ static int dwcmshc_suspend(struct device *dev)
 	struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host);
 	int ret;
 
+	mmc_hsq_suspend(host->mmc);
+
 	ret = sdhci_suspend_host(host);
 	if (ret)
 		return ret;
@@ -583,7 +606,11 @@ static int dwcmshc_resume(struct device *dev)
 	if (ret)
 		return ret;
 
-	return sdhci_resume_host(host);
+	ret = sdhci_resume_host(host);
+	if (ret)
+		return ret;
+
+	return mmc_hsq_resume(host->mmc);
 }
 
 static int dwcmshc_runtime_suspend(struct device *dev)
diff --git a/drivers/mtd/spi-nor/Kconfig b/drivers/mtd/spi-nor/Kconfig
index ffc4b380f2b1..ed4a5640866a 100644
--- a/drivers/mtd/spi-nor/Kconfig
+++ b/drivers/mtd/spi-nor/Kconfig
@@ -24,6 +24,13 @@ config MTD_SPI_NOR_USE_4K_SECTORS
 	  Please note that some tools/drivers/filesystems may not work with
 	  4096 B erase size (e.g. UBIFS requires 15 KiB as a minimum).
 
+config MTD_SPI_NOR_MISC
+	bool "Support SPI NOR misc device"
+	default n
+	help
+	  Support obtaining flash information through the ioctl interface
+	  of the misc device.
+
 source "drivers/mtd/spi-nor/controllers/Kconfig"
 
 endif # MTD_SPI_NOR
diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c
index 2f38ca1e5568..fdec7c815937 100644
--- a/drivers/mtd/spi-nor/core.c
+++ b/drivers/mtd/spi-nor/core.c
@@ -21,9 +21,17 @@
 #include <linux/sched/task_stack.h>
 #include <linux/spi/flash.h>
 #include <linux/mtd/spi-nor.h>
+#include <linux/miscdevice.h>
+
+#include <uapi/linux/spi_nor_misc.h>
 
 #include "core.h"
 
+struct spi_nor_misc_dev {
+	struct miscdevice dev;
+	struct spi_nor *nor;
+};
+
 /* Define max times to check status register before we give up. */
 
 /*
@@ -3462,6 +3470,78 @@ static int spi_nor_create_write_dirmap(struct spi_nor *nor)
 	return PTR_ERR_OR_ZERO(nor->dirmap.wdesc);
 }
 
+static int spi_nor_misc_open(struct inode *inode, struct file *file)
+{
+	struct miscdevice *miscdev = file->private_data;
+	struct spi_nor_misc_dev *nor_dev;
+
+	nor_dev = container_of(miscdev, struct spi_nor_misc_dev, dev);
+	file->private_data = nor_dev->nor;
+
+	return 0;
+}
+
+static long spi_nor_misc_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
+{
+	struct spi_nor *nor = (struct spi_nor *)file->private_data;
+	struct nor_flash_user_info info;
+	void __user *uarg = (void __user *)arg;
+	int i, ret;
+
+	switch (cmd) {
+	case NOR_GET_FLASH_INFO:
+		for (i = 0; i < SPI_NOR_MAX_ID_LEN; i++)
+			info.id[i] = nor->info->id[i];
+
+		ret = copy_to_user(uarg, &info, sizeof(info));
+		if (ret) {
+			dev_err(nor->dev, "failed to get elbi data\n");
+			return -EFAULT;
+		}
+		break;
+	default:
+		break;
+	}
+	return 0;
+}
+
+static const struct file_operations spi_nor_misc_ops = {
+	.owner = THIS_MODULE,
+	.open = spi_nor_misc_open,
+	.unlocked_ioctl = spi_nor_misc_ioctl,
+};
+
+static int spi_nor_add_misc(struct spi_nor *nor)
+{
+	int ret;
+	struct spi_nor_misc_dev *nor_dev;
+	char name[24];
+
+	nor_dev = devm_kzalloc(nor->dev, sizeof(struct spi_nor_misc_dev),
+				GFP_KERNEL);
+	if (!nor_dev)
+		return -ENOMEM;
+
+	nor_dev->dev.minor = MISC_DYNAMIC_MINOR;
+	snprintf(name, sizeof(name), "%s%s", "nor_misc_", dev_name(nor->dev));
+	nor_dev->dev.name = devm_kstrdup(nor->dev, name, GFP_KERNEL);
+	nor_dev->dev.fops = &spi_nor_misc_ops;
+	nor_dev->dev.parent = nor->dev;
+
+	ret = misc_register(&nor_dev->dev);
+	if (ret) {
+		dev_err(nor->dev, "failed to register misc device.\n");
+		return ret;
+	}
+
+	nor_dev->nor = nor;
+	nor->misc_dev = &nor_dev->dev;
+
+	dev_info(nor->dev, "register misc device\n");
+
+	return 0;
+}
+
 static int spi_nor_probe(struct spi_mem *spimem)
 {
 	struct spi_device *spi = spimem->spi;
@@ -3531,6 +3611,9 @@ static int spi_nor_probe(struct spi_mem *spimem)
 	if (ret)
 		return ret;
 
+	if (IS_ENABLED(CONFIG_MTD_SPI_NOR_MISC))
+		spi_nor_add_misc(nor);
+
 	return mtd_device_register(&nor->mtd, data ? data->parts : NULL,
 				   data ? data->nr_parts : 0);
 }
@@ -3541,6 +3624,9 @@ static int spi_nor_remove(struct spi_mem *spimem)
 
 	spi_nor_restore(nor);
 
+	if (IS_ENABLED(CONFIG_MTD_SPI_NOR_MISC) && nor->misc_dev)
+		misc_deregister(nor->misc_dev);
+
 	/* Clean up MTD stuff. */
 	return mtd_device_unregister(&nor->mtd);
 }
diff --git a/drivers/net/ethernet/arc/emac_main.c b/drivers/net/ethernet/arc/emac_main.c
index bdd7a06e8eb5..f1263a258708 100644
--- a/drivers/net/ethernet/arc/emac_main.c
+++ b/drivers/net/ethernet/arc/emac_main.c
@@ -140,7 +140,7 @@ static void arc_emac_tx_clean(struct net_device *ndev)
 			stats->tx_bytes += skb->len;
 		}
 
-		dma_unmap_single(&ndev->dev, dma_unmap_addr(tx_buff, addr),
+		dma_unmap_single(ndev->dev.parent, dma_unmap_addr(tx_buff, addr),
 				 dma_unmap_len(tx_buff, len), DMA_TO_DEVICE);
 
 		/* return the sk_buff to system */
@@ -223,9 +223,9 @@ static int arc_emac_rx(struct net_device *ndev, int budget)
 			continue;
 		}
 
-		addr = dma_map_single(&ndev->dev, (void *)skb->data,
+		addr = dma_map_single(ndev->dev.parent, (void *)skb->data,
 				      EMAC_BUFFER_SIZE, DMA_FROM_DEVICE);
-		if (dma_mapping_error(&ndev->dev, addr)) {
+		if (dma_mapping_error(ndev->dev.parent, addr)) {
 			if (net_ratelimit())
 				netdev_err(ndev, "cannot map dma buffer\n");
 			dev_kfree_skb(skb);
@@ -237,7 +237,7 @@ static int arc_emac_rx(struct net_device *ndev, int budget)
 		}
 
 		/* unmap previosly mapped skb */
-		dma_unmap_single(&ndev->dev, dma_unmap_addr(rx_buff, addr),
+		dma_unmap_single(ndev->dev.parent, dma_unmap_addr(rx_buff, addr),
 				 dma_unmap_len(rx_buff, len), DMA_FROM_DEVICE);
 
 		pktlen = info & LEN_MASK;
@@ -444,9 +444,9 @@ static int arc_emac_open(struct net_device *ndev)
 		if (unlikely(!rx_buff->skb))
 			return -ENOMEM;
 
-		addr = dma_map_single(&ndev->dev, (void *)rx_buff->skb->data,
+		addr = dma_map_single(ndev->dev.parent, (void *)rx_buff->skb->data,
 				      EMAC_BUFFER_SIZE, DMA_FROM_DEVICE);
-		if (dma_mapping_error(&ndev->dev, addr)) {
+		if (dma_mapping_error(ndev->dev.parent, addr)) {
 			netdev_err(ndev, "cannot dma map\n");
 			dev_kfree_skb(rx_buff->skb);
 			return -ENOMEM;
@@ -554,7 +554,7 @@ static void arc_free_tx_queue(struct net_device *ndev)
 		struct buffer_state *tx_buff = &priv->tx_buff[i];
 
 		if (tx_buff->skb) {
-			dma_unmap_single(&ndev->dev,
+			dma_unmap_single(ndev->dev.parent,
 					 dma_unmap_addr(tx_buff, addr),
 					 dma_unmap_len(tx_buff, len),
 					 DMA_TO_DEVICE);
@@ -585,7 +585,7 @@ static void arc_free_rx_queue(struct net_device *ndev)
 		struct buffer_state *rx_buff = &priv->rx_buff[i];
 
 		if (rx_buff->skb) {
-			dma_unmap_single(&ndev->dev,
+			dma_unmap_single(ndev->dev.parent,
 					 dma_unmap_addr(rx_buff, addr),
 					 dma_unmap_len(rx_buff, len),
 					 DMA_FROM_DEVICE);
@@ -693,10 +693,10 @@ static netdev_tx_t arc_emac_tx(struct sk_buff *skb, struct net_device *ndev)
 		return NETDEV_TX_BUSY;
 	}
 
-	addr = dma_map_single(&ndev->dev, (void *)skb->data, len,
+	addr = dma_map_single(ndev->dev.parent, (void *)skb->data, len,
 			      DMA_TO_DEVICE);
 
-	if (unlikely(dma_mapping_error(&ndev->dev, addr))) {
+	if (unlikely(dma_mapping_error(ndev->dev.parent, addr))) {
 		stats->tx_dropped++;
 		stats->tx_errors++;
 		dev_kfree_skb_any(skb);
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
index 46811926f5c4..05748b22deef 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
@@ -67,6 +67,7 @@ struct rk_priv_data {
 	struct clk *pclk_mac;
 	struct clk *clk_phy;
 	struct clk *pclk_xpcs;
+	struct clk *clk_xpcs_eee;
 
 	struct reset_control *phy_reset;
 
@@ -1908,8 +1909,10 @@ static int rk_gmac_clk_init(struct plat_stmmacenet_data *plat)
 		   bsp_priv->phy_iface == PHY_INTERFACE_MODE_QSGMII) {
 		bsp_priv->pclk_xpcs = devm_clk_get(dev, "pclk_xpcs");
 		if (IS_ERR(bsp_priv->pclk_xpcs))
-			dev_err(dev, "cannot get clock %s\n",
-				"pclk_xpcs");
+			dev_err(dev, "cannot get clock %s\n", "pclk_xpcs");
+		bsp_priv->clk_xpcs_eee = devm_clk_get(dev, "clk_xpcs_eee");
+		if (IS_ERR(bsp_priv->clk_xpcs_eee))
+			dev_err(dev, "cannot get clock %s\n", "clk_xpcs_eee");
 	}
 
 	bsp_priv->clk_mac_speed = devm_clk_get(dev, "clk_mac_speed");
@@ -1977,6 +1980,9 @@ static int gmac_clk_enable(struct rk_priv_data *bsp_priv, bool enable)
 			if (!IS_ERR(bsp_priv->pclk_xpcs))
 				clk_prepare_enable(bsp_priv->pclk_xpcs);
 
+			if (!IS_ERR(bsp_priv->clk_xpcs_eee))
+				clk_prepare_enable(bsp_priv->clk_xpcs_eee);
+
 			if (bsp_priv->ops && bsp_priv->ops->set_clock_selection)
 				bsp_priv->ops->set_clock_selection(bsp_priv,
 					       bsp_priv->clock_input, true);
@@ -2014,6 +2020,8 @@ static int gmac_clk_enable(struct rk_priv_data *bsp_priv, bool enable)
 
 			clk_disable_unprepare(bsp_priv->pclk_xpcs);
 
+			clk_disable_unprepare(bsp_priv->clk_xpcs_eee);
+
 			/**
 			 * if (!IS_ERR(bsp_priv->clk_mac))
 			 *	clk_disable_unprepare(bsp_priv->clk_mac);
diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig
index 77c8fd3b6799..1f94d0e85b9d 100644
--- a/drivers/net/phy/Kconfig
+++ b/drivers/net/phy/Kconfig
@@ -223,6 +223,12 @@ config MICROSEMI_PHY
 	help
 	  Currently supports VSC8514, VSC8530, VSC8531, VSC8540 and VSC8541 PHYs
 
+config MOTORCOMM_PHY
+	tristate "Motorcomm PHYs"
+	help
+	  Enables support for Motorcomm network PHYs.
+	  Currently supports the YT8511, YT8521, YT8531, RK631 gigabit PHY.
+
 config NATIONAL_PHY
 	tristate "National Semiconductor PHYs"
 	help
diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile
index bcc1c1267d0c..8423e4a6fb3d 100644
--- a/drivers/net/phy/Makefile
+++ b/drivers/net/phy/Makefile
@@ -69,6 +69,7 @@ obj-$(CONFIG_MICREL_PHY)	+= micrel.o
 obj-$(CONFIG_MICROCHIP_PHY)	+= microchip.o
 obj-$(CONFIG_MICROCHIP_T1_PHY)	+= microchip_t1.o
 obj-$(CONFIG_MICROSEMI_PHY)	+= mscc/
+obj-$(CONFIG_MOTORCOMM_PHY)	+= motorcomm.o
 obj-$(CONFIG_NATIONAL_PHY)	+= national.o
 obj-$(CONFIG_NXP_TJA11XX_PHY)	+= nxp-tja11xx.o
 obj-$(CONFIG_QSEMI_PHY)		+= qsemi.o
diff --git a/drivers/net/phy/motorcomm.c b/drivers/net/phy/motorcomm.c
new file mode 100644
index 000000000000..dbae7daefe3a
--- /dev/null
+++ b/drivers/net/phy/motorcomm.c
@@ -0,0 +1,653 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Driver for Motorcomm PHYs
+ *
+ * Author: Peter Geis <pgwipeout@gmail.com>
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/netdevice.h>
+#include <linux/phy.h>
+
+#define PHY_ID_YT8511		0x0000010a
+#define PHY_ID_YT8531S		0x4f51e91a
+#define PHY_ID_YT8531		0x4f51e91b
+
+#define YT8511_PAGE_SELECT	0x1e
+#define YT8511_PAGE		0x1f
+#define YT8511_EXT_CLK_GATE	0x0c
+#define YT8511_EXT_DELAY_DRIVE	0x0d
+#define YT8511_EXT_SLEEP_CTRL	0x27
+
+/* 2b00 25m from pll
+ * 2b01 25m from xtl *default*
+ * 2b10 62.m from pll
+ * 2b11 125m from pll
+ */
+#define YT8511_CLK_125M		(BIT(2) | BIT(1))
+#define YT8511_PLLON_SLP	BIT(14)
+
+/* RX Delay enabled = 1.8ns 1000T, 8ns 10/100T */
+#define YT8511_DELAY_RX		BIT(0)
+
+/* TX Gig-E Delay is bits 7:4, default 0x5
+ * TX Fast-E Delay is bits 15:12, default 0xf
+ * Delay = 150ps * N - 250ps
+ * On = 2000ps, off = 50ps
+ */
+#define YT8511_DELAY_GE_TX_EN	(0xf << 4)
+#define YT8511_DELAY_GE_TX_DIS	(0x2 << 4)
+#define YT8511_DELAY_FE_TX_EN	(0xf << 12)
+#define YT8511_DELAY_FE_TX_DIS	(0x2 << 12)
+
+/* if system depends on ethernet packet to restore from sleep,
+ * please define this macro to 1 otherwise, define it to 0.
+ */
+#define SYS_WAKEUP_BASED_ON_ETH_PKT	1
+
+/* to enable system WOL feature of phy, please define this macro to 1
+ * otherwise, define it to 0.
+ */
+#define YTPHY_WOL_FEATURE_ENABLE	0
+
+#if (YTPHY_WOL_FEATURE_ENABLE)
+#undef SYS_WAKEUP_BASED_ON_ETH_PKT
+#define SYS_WAKEUP_BASED_ON_ETH_PKT	1
+#endif
+
+/* for YT8531 package A xtal init config */
+#define YTPHY8531A_XTAL_INIT		0
+
+#define REG_PHY_SPEC_STATUS		0x11
+#define REG_DEBUG_ADDR_OFFSET		0x1e
+#define REG_DEBUG_DATA			0x1f
+
+#define YT8521_EXTREG_SLEEP_CONTROL1	0x27
+#define YT8521_EN_SLEEP_SW_BIT		15
+
+#define YT8521_SPEED_MODE		0xc000
+#define YT8521_DUPLEX			0x2000
+#define YT8521_SPEED_MODE_BIT		14
+#define YT8521_DUPLEX_BIT		13
+#define YT8521_LINK_STATUS_BIT		10
+
+/* YT8521 polling mode */
+#define YT8521_PHY_MODE_FIBER		1 /* fiber mode only */
+#define YT8521_PHY_MODE_UTP		2 /* utp mode only */
+#define YT8521_PHY_MODE_POLL		3 /* fiber and utp, poll mode */
+
+static int yt8521_hw_strap_polling(struct phy_device *phydev);
+#define YT8521_PHY_MODE_CURR		yt8521_hw_strap_polling(phydev)
+
+static int yt8511_read_page(struct phy_device *phydev)
+{
+	return __phy_read(phydev, YT8511_PAGE_SELECT);
+};
+
+static int yt8511_write_page(struct phy_device *phydev, int page)
+{
+	return __phy_write(phydev, YT8511_PAGE_SELECT, page);
+};
+
+static int yt8511_config_init(struct phy_device *phydev)
+{
+	int oldpage, ret = 0;
+	unsigned int ge, fe;
+
+	oldpage = phy_select_page(phydev, YT8511_EXT_CLK_GATE);
+	if (oldpage < 0)
+		goto err_restore_page;
+
+	/* set rgmii delay mode */
+	switch (phydev->interface) {
+	case PHY_INTERFACE_MODE_RGMII:
+		ge = YT8511_DELAY_GE_TX_DIS;
+		fe = YT8511_DELAY_FE_TX_DIS;
+		break;
+	case PHY_INTERFACE_MODE_RGMII_RXID:
+		ge = YT8511_DELAY_RX | YT8511_DELAY_GE_TX_DIS;
+		fe = YT8511_DELAY_FE_TX_DIS;
+		break;
+	case PHY_INTERFACE_MODE_RGMII_TXID:
+		ge = YT8511_DELAY_GE_TX_EN;
+		fe = YT8511_DELAY_FE_TX_EN;
+		break;
+	case PHY_INTERFACE_MODE_RGMII_ID:
+		ge = YT8511_DELAY_RX | YT8511_DELAY_GE_TX_EN;
+		fe = YT8511_DELAY_FE_TX_EN;
+		break;
+	default: /* do not support other modes */
+		ret = -EOPNOTSUPP;
+		goto err_restore_page;
+	}
+
+	ret = __phy_modify(phydev, YT8511_PAGE, (YT8511_DELAY_RX | YT8511_DELAY_GE_TX_EN), ge);
+	if (ret < 0)
+		goto err_restore_page;
+
+	/* set clock mode to 125mhz */
+	ret = __phy_modify(phydev, YT8511_PAGE, 0, YT8511_CLK_125M);
+	if (ret < 0)
+		goto err_restore_page;
+
+	/* fast ethernet delay is in a separate page */
+	ret = __phy_write(phydev, YT8511_PAGE_SELECT, YT8511_EXT_DELAY_DRIVE);
+	if (ret < 0)
+		goto err_restore_page;
+
+	ret = __phy_modify(phydev, YT8511_PAGE, YT8511_DELAY_FE_TX_EN, fe);
+	if (ret < 0)
+		goto err_restore_page;
+
+	/* leave pll enabled in sleep */
+	ret = __phy_write(phydev, YT8511_PAGE_SELECT, YT8511_EXT_SLEEP_CTRL);
+	if (ret < 0)
+		goto err_restore_page;
+
+	ret = __phy_modify(phydev, YT8511_PAGE, 0, YT8511_PLLON_SLP);
+	if (ret < 0)
+		goto err_restore_page;
+
+err_restore_page:
+	return phy_restore_page(phydev, oldpage, ret);
+}
+
+static u32 ytphy_read_ext(struct phy_device *phydev, u32 regnum)
+{
+	int ret;
+
+	phy_lock_mdio_bus(phydev);
+	ret = __phy_write(phydev, REG_DEBUG_ADDR_OFFSET, regnum);
+	if (ret < 0)
+		goto err_handle;
+
+	ret = __phy_read(phydev, REG_DEBUG_DATA);
+	if (ret < 0)
+		goto err_handle;
+
+err_handle:
+	phy_unlock_mdio_bus(phydev);
+	return ret;
+}
+
+static int ytphy_write_ext(struct phy_device *phydev, u32 regnum, u16 val)
+{
+	int ret;
+
+	phy_lock_mdio_bus(phydev);
+	ret = __phy_write(phydev, REG_DEBUG_ADDR_OFFSET, regnum);
+	if (ret < 0)
+		goto err_handle;
+
+	ret = __phy_write(phydev, REG_DEBUG_DATA, val);
+	if (ret < 0)
+		goto err_handle;
+
+err_handle:
+	phy_unlock_mdio_bus(phydev);
+	return ret;
+}
+
+static int ytphy_soft_reset(struct phy_device *phydev)
+{
+	int ret = 0, val = 0;
+
+	val = phy_read(phydev, MII_BMCR);
+	if (val < 0)
+		return val;
+
+	ret = phy_write(phydev, MII_BMCR, val | BMCR_RESET);
+	if (ret < 0)
+		return ret;
+
+	return ret;
+}
+
+static int yt8521_soft_reset(struct phy_device *phydev)
+{
+	int ret = 0, val;
+
+	if (YT8521_PHY_MODE_CURR == YT8521_PHY_MODE_UTP) {
+		ytphy_write_ext(phydev, 0xa000, 0);
+		ret = ytphy_soft_reset(phydev);
+		if (ret < 0)
+			return ret;
+	}
+
+	if (YT8521_PHY_MODE_CURR == YT8521_PHY_MODE_FIBER) {
+		ytphy_write_ext(phydev, 0xa000, 2);
+		ret = ytphy_soft_reset(phydev);
+		if (ret < 0)
+			return ret;
+
+		ytphy_write_ext(phydev, 0xa000, 0);
+	}
+
+	if (YT8521_PHY_MODE_CURR == YT8521_PHY_MODE_POLL) {
+		val = ytphy_read_ext(phydev, 0xa001);
+		ytphy_write_ext(phydev, 0xa001, (val & ~0x8000));
+
+		ytphy_write_ext(phydev, 0xa000, 0);
+		ret = ytphy_soft_reset(phydev);
+		if (ret < 0)
+			return ret;
+	}
+
+	return 0;
+}
+
+static int yt8521_hw_strap_polling(struct phy_device *phydev)
+{
+	int val = 0;
+
+	val = ytphy_read_ext(phydev, 0xa001) & 0x7;
+	switch (val) {
+	case 1:
+	case 4:
+	case 5:
+		return YT8521_PHY_MODE_FIBER;
+	case 2:
+	case 6:
+	case 7:
+		return YT8521_PHY_MODE_POLL;
+	case 3:
+	case 0:
+	default:
+		return YT8521_PHY_MODE_UTP;
+	}
+}
+
+static int yt8521_config_init(struct phy_device *phydev)
+{
+	int ret, hw_strap_mode;
+	int val;
+
+#if (YTPHY_WOL_FEATURE_ENABLE)
+	struct ethtool_wolinfo wol;
+
+	/* set phy wol enable */
+	memset(&wol, 0x0, sizeof(struct ethtool_wolinfo));
+	wol.wolopts |= WAKE_MAGIC;
+	ytphy_wol_feature_set(phydev, &wol);
+#endif
+
+	phydev->irq = PHY_POLL;
+	/* NOTE: this function should not be called more than one for each chip. */
+	hw_strap_mode = ytphy_read_ext(phydev, 0xa001) & 0x7;
+
+	ytphy_write_ext(phydev, 0xa000, 0);
+
+	/* disable auto sleep */
+	val = ytphy_read_ext(phydev, YT8521_EXTREG_SLEEP_CONTROL1);
+	if (val < 0)
+		return val;
+
+	val &= (~BIT(YT8521_EN_SLEEP_SW_BIT));
+	ret = ytphy_write_ext(phydev, YT8521_EXTREG_SLEEP_CONTROL1, val);
+	if (ret < 0)
+		return ret;
+
+	/* enable RXC clock when no wire plug */
+	val = ytphy_read_ext(phydev, 0xc);
+	if (val < 0)
+		return val;
+	val &= ~(1 << 12);
+	ret = ytphy_write_ext(phydev, 0xc, val);
+	if (ret < 0)
+		return ret;
+
+	netdev_info(phydev->attached_dev, "%s done, phy addr: %d, strap mode = %d, polling mode = %d\n",
+		    __func__, phydev->mdio.addr, hw_strap_mode, yt8521_hw_strap_polling(phydev));
+
+	return ret;
+}
+
+/* for fiber mode, there is no 10M speed mode and
+ * this function is for this purpose.
+ */
+static int yt8521_adjust_status(struct phy_device *phydev, int val, int is_utp)
+{
+	int speed = SPEED_UNKNOWN;
+	int speed_mode, duplex;
+
+	if (is_utp)
+		duplex = (val & YT8521_DUPLEX) >> YT8521_DUPLEX_BIT;
+	else
+		duplex = 1;
+	speed_mode = (val & YT8521_SPEED_MODE) >> YT8521_SPEED_MODE_BIT;
+	switch (speed_mode) {
+	case 0:
+		if (is_utp)
+			speed = SPEED_10;
+		break;
+	case 1:
+		speed = SPEED_100;
+		break;
+	case 2:
+		speed = SPEED_1000;
+		break;
+	case 3:
+		break;
+	default:
+		speed = SPEED_UNKNOWN;
+		break;
+	}
+
+	phydev->speed = speed;
+	phydev->duplex = duplex;
+
+	return 0;
+}
+
+/* for fiber mode, when speed is 100M, there is no definition for
+ * autonegotiation, and this function handles this case and return
+ * 1 per linux kernel's polling.
+ */
+static int yt8521_aneg_done(struct phy_device *phydev)
+{
+	int link_fiber = 0, link_utp = 0;
+
+	/* reading Fiber */
+	ytphy_write_ext(phydev, 0xa000, 2);
+	link_fiber = !!(phy_read(phydev, REG_PHY_SPEC_STATUS) & (BIT(YT8521_LINK_STATUS_BIT)));
+
+	/* reading UTP */
+	ytphy_write_ext(phydev, 0xa000, 0);
+	if (!link_fiber)
+		link_utp = !!(phy_read(phydev, REG_PHY_SPEC_STATUS) & (BIT(YT8521_LINK_STATUS_BIT)));
+
+	netdev_info(phydev->attached_dev, "%s, phy addr: %d, link_fiber: %d, link_utp: %d\n",
+		    __func__, phydev->mdio.addr, link_fiber, link_utp);
+	return !!(link_fiber | link_utp);
+}
+
+static int yt8521_read_status(struct phy_device *phydev)
+{
+	int link_utp = 0, link_fiber = 0;
+	int yt8521_fiber_latch_val;
+	int yt8521_fiber_curr_val;
+	int link, ret;
+	int val;
+
+	if (YT8521_PHY_MODE_CURR != YT8521_PHY_MODE_FIBER) {
+		/* reading UTP */
+		ret = ytphy_write_ext(phydev, 0xa000, 0);
+		if (ret < 0)
+			return ret;
+
+		val = phy_read(phydev, REG_PHY_SPEC_STATUS);
+		if (val < 0)
+			return val;
+
+		link = val & (BIT(YT8521_LINK_STATUS_BIT));
+		if (link) {
+			link_utp = 1;
+			yt8521_adjust_status(phydev, val, 1);
+		} else {
+			link_utp = 0;
+		}
+	}
+
+	if (YT8521_PHY_MODE_CURR != YT8521_PHY_MODE_UTP) {
+		/* reading Fiber */
+		ret = ytphy_write_ext(phydev, 0xa000, 2);
+		if (ret < 0)
+			return ret;
+
+		val = phy_read(phydev, REG_PHY_SPEC_STATUS);
+		if (val < 0)
+			return val;
+
+		/* note: below debug information is used to check multiple PHy ports. */
+
+		/* for fiber, from 1000m to 100m, there is not link down from 0x11,
+		 * and check reg 1 to identify such case this is important for Linux
+		 * kernel for that, missing linkdown event will cause problem.
+		 */
+		yt8521_fiber_latch_val = phy_read(phydev, MII_BMSR);
+		yt8521_fiber_curr_val = phy_read(phydev, MII_BMSR);
+		link = val & (BIT(YT8521_LINK_STATUS_BIT));
+		if (link && yt8521_fiber_latch_val != yt8521_fiber_curr_val) {
+			link = 0;
+			netdev_info(phydev->attached_dev, "%s, phy addr: %d, fiber link down detect, latch = %04x, curr = %04x\n",
+				    __func__, phydev->mdio.addr, yt8521_fiber_latch_val,
+				    yt8521_fiber_curr_val);
+		}
+
+		if (link) {
+			link_fiber = 1;
+			yt8521_adjust_status(phydev, val, 0);
+		} else {
+			link_fiber = 0;
+		}
+	}
+
+	if (link_utp || link_fiber) {
+		if (phydev->link == 0)
+			netdev_info(phydev->attached_dev, "%s, phy addr: %d, link up, media: %s, mii reg 0x11 = 0x%x\n",
+				    __func__, phydev->mdio.addr,
+				    (link_utp && link_fiber) ? "UNKNOWN MEDIA" : (link_utp ? "UTP" : "Fiber"),
+				    (unsigned int)val);
+		phydev->link = 1;
+	} else {
+		if (phydev->link == 1)
+			netdev_info(phydev->attached_dev, "%s, phy addr: %d, link down\n",
+				    __func__, phydev->mdio.addr);
+		phydev->link = 0;
+	}
+
+	/* utp or combo */
+	if (YT8521_PHY_MODE_CURR != YT8521_PHY_MODE_FIBER) {
+		if (link_fiber)
+			ytphy_write_ext(phydev, 0xa000, 2);
+		if (link_utp)
+			ytphy_write_ext(phydev, 0xa000, 0);
+	}
+
+	return 0;
+}
+
+static int yt8521_suspend(struct phy_device *phydev)
+{
+#if !(SYS_WAKEUP_BASED_ON_ETH_PKT)
+	int value;
+
+	ytphy_write_ext(phydev, 0xa000, 0);
+	value = phy_read(phydev, MII_BMCR);
+	phy_write(phydev, MII_BMCR, value | BMCR_PDOWN);
+
+	ytphy_write_ext(phydev, 0xa000, 2);
+	value = phy_read(phydev, MII_BMCR);
+	phy_write(phydev, MII_BMCR, value | BMCR_PDOWN);
+
+	ytphy_write_ext(phydev, 0xa000, 0);
+#endif /*!(SYS_WAKEUP_BASED_ON_ETH_PKT)*/
+
+	return 0;
+}
+
+static int yt8521_resume(struct phy_device *phydev)
+{
+	int value, ret;
+
+	/* disable auto sleep */
+	value = ytphy_read_ext(phydev, YT8521_EXTREG_SLEEP_CONTROL1);
+	if (value < 0)
+		return value;
+
+	value &= (~BIT(YT8521_EN_SLEEP_SW_BIT));
+
+	ret = ytphy_write_ext(phydev, YT8521_EXTREG_SLEEP_CONTROL1, value);
+	if (ret < 0)
+		return ret;
+
+#if !(SYS_WAKEUP_BASED_ON_ETH_PKT)
+	if (YT8521_PHY_MODE_CURR != YT8521_PHY_MODE_FIBER) {
+		ytphy_write_ext(phydev, 0xa000, 0);
+		value = phy_read(phydev, MII_BMCR);
+		phy_write(phydev, MII_BMCR, value & ~BMCR_PDOWN);
+	}
+
+	if (YT8521_PHY_MODE_CURR != YT8521_PHY_MODE_UTP) {
+		ytphy_write_ext(phydev, 0xa000, 2);
+		value = phy_read(phydev, MII_BMCR);
+		phy_write(phydev, MII_BMCR, value & ~BMCR_PDOWN);
+
+		ytphy_write_ext(phydev, 0xa000, 0);
+	}
+#endif /*!(SYS_WAKEUP_BASED_ON_ETH_PKT)*/
+
+	return 0;
+}
+
+static int yt8531_rxclk_duty_init(struct phy_device *phydev)
+{
+	unsigned int value = 0x9696;
+	int ret = 0;
+
+	ret = ytphy_write_ext(phydev, 0xa040, 0xffff);
+	if (ret < 0)
+		return ret;
+
+	ret = ytphy_write_ext(phydev, 0xa041, 0xff);
+	if (ret < 0)
+		return ret;
+
+	ret = ytphy_write_ext(phydev, 0xa039, 0xbf00);
+	if (ret < 0)
+		return ret;
+
+	/* nodelay duty = 0x9696 (default)
+	 * fixed delay duty = 0x4040
+	 * step delay 0xf duty = 0x4041
+	 */
+	if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
+	    phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
+		value = 0x4040;
+
+	ret = ytphy_write_ext(phydev, 0xa03a, value);
+	if (ret < 0)
+		return ret;
+	ret = ytphy_write_ext(phydev, 0xa03b, value);
+	if (ret < 0)
+		return ret;
+	ret = ytphy_write_ext(phydev, 0xa03c, value);
+	if (ret < 0)
+		return ret;
+	ret = ytphy_write_ext(phydev, 0xa03d, value);
+	if (ret < 0)
+		return ret;
+	ret = ytphy_write_ext(phydev, 0xa03e, value);
+	if (ret < 0)
+		return ret;
+	ret = ytphy_write_ext(phydev, 0xa03f, value);
+	if (ret < 0)
+		return ret;
+
+	return ret;
+}
+
+static int yt8531S_config_init(struct phy_device *phydev)
+{
+#if (YTPHY8531A_XTAL_INIT)
+	int ret = 0;
+
+	ret = yt8531a_xtal_init(phydev);
+	if (ret < 0)
+		return ret;
+#endif
+
+	return yt8521_config_init(phydev);
+}
+
+static int yt8531_config_init(struct phy_device *phydev)
+{
+	int ret = 0, val;
+
+#if (YTPHY8531A_XTAL_INIT)
+	ret = yt8531a_xtal_init(phydev);
+	if (ret < 0)
+		return ret;
+#endif
+
+	/* PHY_CLK_OUT 125M enabled (default) */
+	ret = ytphy_write_ext(phydev, 0xa012, 0xd0);
+	if (ret < 0)
+		return ret;
+
+	ret = yt8531_rxclk_duty_init(phydev);
+	if (ret < 0)
+		return ret;
+
+	/* RXC, PHY_CLK_OUT and RXData Drive strength:
+	 * Drive strength of RXC = 4, PHY_CLK_OUT = 3, RXD0 = 4 (default)
+	 * If the io voltage is 3.3v, PHY_CLK_OUT = 2, set 0xa010 = 0x9acf
+	 */
+	ret = ytphy_write_ext(phydev, 0xa010, 0x9bcf);
+	if (ret < 0)
+		return ret;
+
+	/* Change 100M default BGS voltage from 0x294c to 0x274c */
+	val = ytphy_read_ext(phydev, 0x57);
+	val = (val & ~(0xf << 8)) | (7 << 8);
+	ret = ytphy_write_ext(phydev, 0x57, val);
+	if (ret < 0)
+		return ret;
+
+	return ret;
+}
+
+static struct phy_driver motorcomm_phy_drvs[] = {
+	{
+		PHY_ID_MATCH_EXACT(PHY_ID_YT8511),
+		.name		= "YT8511 Gigabit Ethernet",
+		.config_init	= yt8511_config_init,
+		.suspend	= genphy_suspend,
+		.resume		= genphy_resume,
+		.read_page	= yt8511_read_page,
+		.write_page	= yt8511_write_page,
+	}, {
+		/* same as 8521 */
+		PHY_ID_MATCH_EXACT(PHY_ID_YT8531S),
+		.name          = "YT8531S Gigabit Ethernet",
+		.features      = PHY_GBIT_FEATURES,
+		.soft_reset    = yt8521_soft_reset,
+		.aneg_done     = yt8521_aneg_done,
+		.config_init   = yt8531S_config_init,
+		.read_status   = yt8521_read_status,
+		.suspend       = yt8521_suspend,
+		.resume        = yt8521_resume,
+#if (YTPHY_WOL_FEATURE_ENABLE)
+		.get_wol       = &ytphy_wol_feature_get,
+		.set_wol       = &ytphy_wol_feature_set,
+#endif
+	}, {
+		/* same as 8511 */
+		PHY_ID_MATCH_EXACT(PHY_ID_YT8531),
+		.name          = "YT8531 Gigabit Ethernet",
+		.features      = PHY_GBIT_FEATURES,
+		.config_init   = yt8531_config_init,
+		.suspend       = genphy_suspend,
+		.resume        = genphy_resume,
+#if (YTPHY_WOL_FEATURE_ENABLE)
+		.get_wol       = &ytphy_wol_feature_get,
+		.set_wol       = &ytphy_wol_feature_set,
+#endif
+	},
+};
+
+module_phy_driver(motorcomm_phy_drvs);
+
+MODULE_DESCRIPTION("Motorcomm PHY driver");
+MODULE_AUTHOR("Peter Geis");
+MODULE_LICENSE("GPL");
+
+static const struct mdio_device_id __maybe_unused motorcomm_tbl[] = {
+	{ PHY_ID_MATCH_EXACT(PHY_ID_YT8511) },
+	{ PHY_ID_MATCH_EXACT(PHY_ID_YT8531S) },
+	{ PHY_ID_MATCH_EXACT(PHY_ID_YT8531) },
+	{ /* sentinal */ }
+};
+
+MODULE_DEVICE_TABLE(mdio, motorcomm_tbl);
diff --git a/drivers/net/phy/rk630phy.c b/drivers/net/phy/rk630phy.c
index 23ab0b1f9d11..8d7265e891cd 100644
--- a/drivers/net/phy/rk630phy.c
+++ b/drivers/net/phy/rk630phy.c
@@ -53,6 +53,7 @@
 #define REG_PAGE6_CP_CURRENT			0x17
 #define REG_PAGE6_ADC_OP_BIAS			0x18
 #define REG_PAGE6_RX_DECTOR			0x19
+#define REG_PAGE6_TX_MOS_DRV			0x1B
 #define REG_PAGE6_AFE_PDCW			0x1c
 
 /* PAGE 8 */
@@ -207,6 +208,8 @@ static void rk630_phy_t22_config_init(struct phy_device *phydev)
 
 	/* Switch to page 1 */
 	phy_write(phydev, REG_PAGE_SEL, 0x0100);
+	/* Enable offset clock */
+	phy_write(phydev, 0x10, 0xfbfe);
 	/* Disable APS */
 	phy_write(phydev, REG_PAGE1_APS_CTRL, 0x4824);
 	/* Switch to page 2 */
@@ -236,11 +239,15 @@ static void rk630_phy_t22_config_init(struct phy_device *phydev)
 	phy_write(phydev, REG_PAGE6_RX_DECTOR, 0x0408);
 	/* PHYAFE PDCW optimization */
 	phy_write(phydev, REG_PAGE6_AFE_PDCW, 0x8880);
+	/* Add PHY Tx mos drive, reduce power noise/jitter */
+	phy_write(phydev, REG_PAGE6_TX_MOS_DRV, 0x888e);
 
 	/* Switch to page 8 */
 	phy_write(phydev, REG_PAGE_SEL, 0x0800);
 	/* Disable auto-cal */
 	phy_write(phydev, REG_PAGE8_AUTO_CAL, 0x0844);
+	/* Reatart offset calibration */
+	phy_write(phydev, 0x13, 0xc096);
 
 	/* Switch to page 0 */
 	phy_write(phydev, REG_PAGE_SEL, 0x0000);
diff --git a/drivers/net/wireless/rockchip_wlan/rkwifi/bcmdhd/Makefile b/drivers/net/wireless/rockchip_wlan/rkwifi/bcmdhd/Makefile
index ef239e75a737..d5145294b73f 100755
--- a/drivers/net/wireless/rockchip_wlan/rkwifi/bcmdhd/Makefile
+++ b/drivers/net/wireless/rockchip_wlan/rkwifi/bcmdhd/Makefile
@@ -113,7 +113,7 @@ BUS_TYPE := "pcie"
 DHDCFLAGS += -DPCIE_FULL_DONGLE -DBCMPCIE -DCUSTOM_DPC_PRIO_SETTING=-1    \
 	-DDONGLE_ENABLE_ISOLATION
 DHDCFLAGS += -DDHD_LB -DDHD_LB_RXP -DDHD_LB_STATS -DDHD_LB_TXP
-DHDCFLAGS += -DDHD_PKTID_AUDIT_ENABLED
+#DHDCFLAGS += -DDHD_PKTID_AUDIT_ENABLED
 DHDCFLAGS += -DINSMOD_FW_LOAD
 DHDCFLAGS += -DCHIP_INTR_CONTROL
 #DHDCFLAGS += -DDHD_PCIE_RUNTIMEPM -DMAX_IDLE_COUNT=11 -DCUSTOM_DHD_RUNTIME_MS=100
diff --git a/drivers/pci/controller/dwc/pcie-dw-dmatest.c b/drivers/pci/controller/dwc/pcie-dw-dmatest.c
index f6d2cbe159b1..79af779a2e6a 100644
--- a/drivers/pci/controller/dwc/pcie-dw-dmatest.c
+++ b/drivers/pci/controller/dwc/pcie-dw-dmatest.c
@@ -312,6 +312,14 @@ static int dma_test(struct pcie_dw_dmatest_dev *dmatest_dev, u32 chn,
 	long long us = 0;
 	struct dma_trx_obj *obj = dmatest_dev->obj;
 
+	/*
+	 * Clean the cache to ensure memory consistency. The CPU writes to the normal memory
+	 * cache before the transmission is initiated, which may cause IO consistency problems,
+	 * such as IO commands.
+	 */
+	if (rd_en)
+		dma_sync_single_for_device(obj->dev, local_paddr, size, DMA_TO_DEVICE);
+
 	start_time = ktime_get();
 	for (i = 0; i < loop; i++) {
 		if (rd_en) {
diff --git a/drivers/pci/controller/dwc/pcie-dw-rockchip.c b/drivers/pci/controller/dwc/pcie-dw-rockchip.c
index e084f37c4edc..f3511c91e865 100644
--- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c
+++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c
@@ -847,6 +847,8 @@ static int rk_pcie_init_dma_trx(struct rk_pcie *rk_pcie)
 	if (IS_ERR(rk_pcie->dma_obj)) {
 		dev_err(rk_pcie->pci->dev, "failed to prepare dma object\n");
 		return -EINVAL;
+	} else if (rk_pcie->dma_obj) {
+		goto out;
 	}
 
 	rk_pcie->dma_obj = pcie_dw_dmatest_register(rk_pcie->pci, true);
@@ -854,7 +856,7 @@ static int rk_pcie_init_dma_trx(struct rk_pcie *rk_pcie)
 		dev_err(rk_pcie->pci->dev, "failed to prepare dmatest\n");
 		return -EINVAL;
 	}
-
+out:
 	/* Enable client write and read interrupt */
 	rk_pcie_writel_apb(rk_pcie, PCIE_CLIENT_INTR_MASK, 0xc000000);
 
@@ -1192,12 +1194,6 @@ static int rk_pcie_add_ep(struct rk_pcie *rk_pcie)
 	if (!rk_pcie_udma_enabled(rk_pcie))
 		return 0;
 
-	rk_pcie->dma_obj = rk_pcie_dma_obj_probe(dev);
-	if (IS_ERR(rk_pcie->dma_obj)) {
-		dev_err(dev, "failed to prepare dma object\n");
-		return -EINVAL;
-	}
-
 	return 0;
 }
 
diff --git a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
index 2b3dec923248..66e5e10c0321 100644
--- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
+++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
@@ -243,6 +243,7 @@ struct rockchip_usb2phy_cfg {
  * @vbus_enabled: vbus regulator status.
  * @bypass_uart_en: usb bypass uart enable, passed from DT.
  * @host_disconnect: usb host disconnect status.
+ * @dis_u2_susphy: disable usb2 phy suspend.
  * @bvalid_irq: IRQ number assigned for vbus valid rise detection.
  * @ls_irq: IRQ number assigned for linestate detection.
  * @id_irq: IRQ number assigned for id fall or rise detection.
@@ -275,6 +276,7 @@ struct rockchip_usb2phy_port {
 	bool		vbus_enabled;
 	bool		bypass_uart_en;
 	bool		host_disconnect;
+	bool		dis_u2_susphy;
 	int		bvalid_irq;
 	int		ls_irq;
 	int             id_irq;
@@ -1184,7 +1186,8 @@ static void rockchip_usb2phy_otg_sm_work(struct work_struct *work)
 		rport->state = OTG_STATE_B_IDLE;
 		if (!rport->vbus_attached) {
 			mutex_unlock(&rport->mutex);
-			rockchip_usb2phy_power_off(rport->phy);
+			if (!rport->dis_u2_susphy)
+				rockchip_usb2phy_power_off(rport->phy);
 			mutex_lock(&rport->mutex);
 		}
 		fallthrough;
@@ -1245,7 +1248,8 @@ static void rockchip_usb2phy_otg_sm_work(struct work_struct *work)
 			rphy->chg_state = USB_CHG_STATE_UNDEFINED;
 			rphy->chg_type = POWER_SUPPLY_TYPE_UNKNOWN;
 			mutex_unlock(&rport->mutex);
-			rockchip_usb2phy_power_off(rport->phy);
+			if (!rport->dis_u2_susphy)
+				rockchip_usb2phy_power_off(rport->phy);
 			mutex_lock(&rport->mutex);
 		}
 		break;
@@ -2054,6 +2058,8 @@ static int rockchip_usb2phy_otg_port_init(struct rockchip_usb2phy *rphy,
 		of_property_read_bool(child_np, "rockchip,vbus-always-on");
 	rport->utmi_avalid =
 		of_property_read_bool(child_np, "rockchip,utmi-avalid");
+	rport->dis_u2_susphy =
+		of_property_read_bool(child_np, "rockchip,dis-u2-susphy");
 
 	/* enter lower power state when suspend */
 	rport->low_power_en =
diff --git a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
index f32b831b941b..08ce2eb7f513 100644
--- a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
+++ b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
@@ -154,8 +154,19 @@ static int rockchip_combphy_pcie_init(struct rockchip_combphy_priv *priv)
 
 static int rockchip_combphy_usb3_init(struct rockchip_combphy_priv *priv)
 {
+	const struct rockchip_combphy_cfg *phy_cfg = priv->cfg;
 	int ret = 0;
 
+	if (device_property_present(priv->dev, "rockchip,dis-u3otg0-port")) {
+		ret = param_write(priv->pipe_grf, &phy_cfg->grfcfg->u3otg0_port_en,
+				  false);
+		return ret;
+	} else if (device_property_present(priv->dev, "rockchip,dis-u3otg1-port")) {
+		ret = param_write(priv->pipe_grf, &phy_cfg->grfcfg->u3otg1_port_en,
+				  false);
+		return ret;
+	}
+
 	if (priv->cfg->combphy_cfg) {
 		ret = priv->cfg->combphy_cfg(priv);
 		if (ret) {
diff --git a/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c b/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c
index bb5fed0c03ca..aff349b75c9f 100644
--- a/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c
+++ b/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c
@@ -21,6 +21,7 @@
 
 /* Register for RK3568 */
 #define GRF_PCIE30PHY_CON1 0x4
+#define GRF_PCIE30PHY_CON4 0x10
 #define GRF_PCIE30PHY_CON6 0x18
 #define GRF_PCIE30PHY_CON9 0x24
 #define GRF_PCIE30PHY_STATUS0 0x80
@@ -78,8 +79,13 @@ static int rockchip_p3phy_set_mode(struct phy *phy, enum phy_mode mode, int subm
 	return 0;
 }
 
+static const u16 phy_fw[] = {
+	#include "phy-rockchip-snps-pcie3.fw"
+};
+
 static int rockchip_p3phy_rk3568_init(struct rockchip_p3phy_priv *priv)
 {
+	int i;
 	int ret = 0;
 	u32 reg;
 
@@ -93,22 +99,34 @@ static int rockchip_p3phy_rk3568_init(struct rockchip_p3phy_priv *priv)
 		regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON1,
 			     (0x1 << 15) | (0x1 << 31));
 	}
+	regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON4,
+		     (0x0 << 14) | (0x1 << (14 + 16))); //sdram_ld_done
+	regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON4,
+		     (0x0 << 13) | (0x1 << (13 + 16))); //sdram_bypass
 
 	reset_control_deassert(priv->p30phy);
-
-	udelay(10);
-	/* Updata RX VCO calibration controls */
-	writel(0x2800, priv->mmio + (0x104a << 2));
-	writel(0x2800, priv->mmio + (0x114a << 2));
-	udelay(10);
-
 	ret = regmap_read_poll_timeout(priv->phy_grf,
 				       GRF_PCIE30PHY_STATUS0,
 				       reg, SRAM_INIT_DONE(reg),
 				       0, 500);
-	if (ret)
+	if (ret) {
 		pr_err("%s: lock failed 0x%x, check input refclk and power supply\n",
 		       __func__, reg);
+		goto out;
+	}
+
+	regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON9,
+		     (0x3 << 8) | (0x3 << (8 + 16))); //map to access sram
+	for (i = 0; i < ARRAY_SIZE(phy_fw); i++)
+		writel(phy_fw[i], priv->mmio + (i<<2));
+	pr_info("snps pcie3phy FW update! size %ld\n", ARRAY_SIZE(phy_fw));
+
+	regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON9,
+		     (0x0 << 8) | (0x3 << (8 + 16)));
+	regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON4,
+		     (0x1 << 14) | (0x1 << (14 + 16))); //sdram_ld_done
+
+out:
 	return ret;
 }
 
diff --git a/drivers/phy/rockchip/phy-rockchip-snps-pcie3.fw b/drivers/phy/rockchip/phy-rockchip-snps-pcie3.fw
new file mode 100644
index 000000000000..301c42837ad9
--- /dev/null
+++ b/drivers/phy/rockchip/phy-rockchip-snps-pcie3.fw
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diff --git a/drivers/phy/rockchip/phy-rockchip-usbdp.c b/drivers/phy/rockchip/phy-rockchip-usbdp.c
index 202ffc8c8ebf..f1a5169e16d3 100644
--- a/drivers/phy/rockchip/phy-rockchip-usbdp.c
+++ b/drivers/phy/rockchip/phy-rockchip-usbdp.c
@@ -668,14 +668,15 @@ static int udphy_disable(struct rockchip_udphy *udphy)
 	return 0;
 }
 
-static int udphy_parse_lane_mux_data(struct rockchip_udphy *udphy, struct device_node *np)
+static int udphy_parse_lane_mux_data(struct rockchip_udphy *udphy, struct device *dev)
 {
+	struct device_node *np = dev->of_node;
 	struct property *prop;
 	int ret, i, len, num_lanes;
 
 	prop = of_find_property(np, "rockchip,dp-lane-mux", &len);
 	if (!prop) {
-		dev_dbg(udphy->dev, "failed to find dp lane mux, following dp alt mode\n");
+		dev_dbg(dev, "failed to find dp lane mux, following dp alt mode\n");
 		udphy->mode = UDPHY_MODE_USB;
 		return 0;
 	}
@@ -683,13 +684,13 @@ static int udphy_parse_lane_mux_data(struct rockchip_udphy *udphy, struct device
 	num_lanes = len / sizeof(u32);
 
 	if (num_lanes != 2 && num_lanes != 4) {
-		dev_err(udphy->dev, "invalid number of lane mux\n");
+		dev_err(dev, "invalid number of lane mux\n");
 		return -EINVAL;
 	}
 
 	ret = of_property_read_u32_array(np, "rockchip,dp-lane-mux", udphy->dp_lane_sel, num_lanes);
 	if (ret) {
-		dev_err(udphy->dev, "get dp lane mux failed\n");
+		dev_err(dev, "get dp lane mux failed\n");
 		return -EINVAL;
 	}
 
@@ -697,7 +698,7 @@ static int udphy_parse_lane_mux_data(struct rockchip_udphy *udphy, struct device
 		int j;
 
 		if (udphy->dp_lane_sel[i] > 3) {
-			dev_err(udphy->dev, "lane mux between 0 and 3, exceeding the range\n");
+			dev_err(dev, "lane mux between 0 and 3, exceeding the range\n");
 			return -EINVAL;
 		}
 
@@ -705,15 +706,17 @@ static int udphy_parse_lane_mux_data(struct rockchip_udphy *udphy, struct device
 
 		for (j = i + 1; j < num_lanes; j++) {
 			if (udphy->dp_lane_sel[i] == udphy->dp_lane_sel[j]) {
-				dev_err(udphy->dev, "set repeat lane mux value\n");
+				dev_err(dev, "set repeat lane mux value\n");
 				return -EINVAL;
 			}
 		}
 	}
 
 	udphy->mode = UDPHY_MODE_DP;
-	if (num_lanes == 2)
+	if (num_lanes == 2) {
 		udphy->mode |= UDPHY_MODE_USB;
+		udphy->flip = udphy->lane_mux_sel[0] == PHY_LANE_MUX_DP ? true : false;
+	}
 
 	return 0;
 }
@@ -788,7 +791,7 @@ static int udphy_parse_dt(struct rockchip_udphy *udphy, struct device *dev)
 		}
 	}
 
-	ret = udphy_parse_lane_mux_data(udphy, np);
+	ret = udphy_parse_lane_mux_data(udphy, dev);
 	if (ret)
 		return ret;
 
@@ -1341,14 +1344,14 @@ static int rk3588_udphy_status_check(struct rockchip_udphy *udphy)
 						       val & TRSV_LN0_MON_RX_CDR_LOCK_DONE,
 						       200, 100000);
 			if (ret)
-				dev_err(udphy->dev, "trsv ln0 mon rx cdr lock timeout\n");
+				dev_notice(udphy->dev, "trsv ln0 mon rx cdr lock timeout\n");
 		} else {
 			ret = regmap_read_poll_timeout(udphy->pma_regmap,
 						       TRSV_LN2_MON_RX_CDR_DONE_OFFSET, val,
 						       val & TRSV_LN2_MON_RX_CDR_LOCK_DONE,
 						       200, 100000);
 			if (ret)
-				dev_err(udphy->dev, "trsv ln2 mon rx cdr lock timeout\n");
+				dev_notice(udphy->dev, "trsv ln2 mon rx cdr lock timeout\n");
 		}
 	}
 
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index f38f98fe55a7..fda4a167684c 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -320,17 +320,6 @@ config PINCTRL_MAX96745
 	help
 	  Say Yes here to enable Pin control support for Maxim MAX96745.
 
-config PINCTRL_MAX96752F
-	tristate "MAX96752F Pincontrol support"
-	depends on MFD_MAX96752F && OF
-	select PINMUX
-	select PINCONF
-	select GENERIC_PINMUX_FUNCTIONS
-	select GENERIC_PINCTRL_GROUPS
-	select GENERIC_PINCONF
-	help
-	  Say Yes here to enable Pin control support for Maxim MAX96752F.
-
 config PINCTRL_MAX96755F
 	tristate "MAX96755F Pincontrol support"
 	depends on MFD_MAX96755F && OF
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index a3501477abc9..d8b32105bb4b 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -22,7 +22,6 @@ obj-$(CONFIG_PINCTRL_FALCON)	+= pinctrl-falcon.o
 obj-$(CONFIG_PINCTRL_GEMINI)	+= pinctrl-gemini.o
 obj-$(CONFIG_PINCTRL_MAX77620)	+= pinctrl-max77620.o
 obj-$(CONFIG_PINCTRL_MAX96745)	+= pinctrl-max96745.o
-obj-$(CONFIG_PINCTRL_MAX96752F)	+= pinctrl-max96752f.o
 obj-$(CONFIG_PINCTRL_MAX96755F)	+= pinctrl-max96755f.o
 obj-$(CONFIG_PINCTRL_MCP23S08_I2C)	+= pinctrl-mcp23s08_i2c.o
 obj-$(CONFIG_PINCTRL_MCP23S08_SPI)	+= pinctrl-mcp23s08_spi.o
diff --git a/drivers/pinctrl/pinctrl-max96752f.c b/drivers/pinctrl/pinctrl-max96752f.c
deleted file mode 100644
index c2f815906137..000000000000
--- a/drivers/pinctrl/pinctrl-max96752f.c
+++ /dev/null
@@ -1,642 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Maxim MAX96752F pin control driver.
- *
- * Copyright (c) 2022 Rockchip Electronics Co. Ltd.
- */
-
-#include <linux/module.h>
-#include <linux/of.h>
-#include <linux/pinctrl/pinctrl.h>
-#include <linux/pinctrl/pinconf-generic.h>
-#include <linux/pinctrl/pinconf.h>
-#include <linux/pinctrl/pinmux.h>
-#include <linux/platform_device.h>
-#include <linux/regmap.h>
-#include <linux/mfd/max96752f.h>
-
-#include "core.h"
-#include "pinconf.h"
-#include "pinmux.h"
-
-struct max96752f_pinctrl {
-	struct device *dev;
-	struct pinctrl_dev *pctl;
-	struct regmap *regmap;
-};
-
-struct config_desc {
-	u16 reg;
-	u8 mask;
-	u8 val;
-};
-
-struct max96752f_group_data {
-	const struct config_desc *configs;
-	int num_configs;
-};
-
-struct max96752f_function_data {
-	u8 gpio_out_dis:1;
-	u8 gpio_tx_en:1;
-	u8 gpio_rx_en:1;
-	u8 gpio_tx_id;
-	u8 gpio_rx_id;
-};
-
-static int max96752f_pinmux_set_mux(struct pinctrl_dev *pctldev,
-				    unsigned int function, unsigned int group)
-{
-	struct max96752f_pinctrl *mpctl = pinctrl_dev_get_drvdata(pctldev);
-	struct function_desc *func;
-	struct group_desc *grp;
-	int i;
-
-	func = pinmux_generic_get_function(pctldev, function);
-	if (!func)
-		return -EINVAL;
-
-	grp = pinctrl_generic_get_group(pctldev, group);
-	if (!grp)
-		return -EINVAL;
-
-	if (func->data) {
-		struct max96752f_function_data *fdata = func->data;
-
-		for (i = 0; i < grp->num_pins; i++) {
-			regmap_update_bits(mpctl->regmap, GPIO_A_REG(grp->pins[i]),
-					   GPIO_OUT_DIS | GPIO_RX_EN | GPIO_TX_EN,
-					   FIELD_PREP(GPIO_OUT_DIS, fdata->gpio_out_dis) |
-					   FIELD_PREP(GPIO_RX_EN, fdata->gpio_rx_en) |
-					   FIELD_PREP(GPIO_TX_EN, fdata->gpio_tx_en));
-
-			if (fdata->gpio_tx_en)
-				regmap_update_bits(mpctl->regmap, GPIO_B_REG(grp->pins[i]),
-						   GPIO_TX_ID,
-						   FIELD_PREP(GPIO_TX_ID, fdata->gpio_tx_id));
-
-			if (fdata->gpio_rx_en)
-				regmap_update_bits(mpctl->regmap, GPIO_C_REG(grp->pins[i]),
-						   GPIO_RX_ID,
-						   FIELD_PREP(GPIO_RX_ID, fdata->gpio_rx_id));
-		}
-	}
-
-	if (grp->data) {
-		struct max96752f_group_data *gdata = grp->data;
-
-		for (i = 0; i < gdata->num_configs; i++) {
-			const struct config_desc *config = &gdata->configs[i];
-
-			regmap_update_bits(mpctl->regmap, config->reg,
-					   config->mask, config->val);
-		}
-	}
-
-	dev_info(mpctl->dev, "enable function %s group %s\n",
-		 func->name, grp->name);
-
-	return 0;
-}
-
-#define PIN_CONFIG_OLDI_SPL_EN		(PIN_CONFIG_END + 1)
-#define PIN_CONFIG_OLDI_SWAP_AB		(PIN_CONFIG_END + 2)
-
-static const struct pinconf_generic_params max96752f_custom_params[] = {
-	{ "oldi-spl-en", PIN_CONFIG_OLDI_SPL_EN, 0 },
-	{ "oldi-swap-ab", PIN_CONFIG_OLDI_SWAP_AB, 0 },
-};
-
-#ifdef CONFIG_DEBUG_FS
-static const struct pin_config_item
-max96752f_custom_conf_items[ARRAY_SIZE(max96752f_custom_params)] = {
-	PCONFDUMP(PIN_CONFIG_OLDI_SPL_EN, "OLDI Splitter Enable", NULL, false),
-	PCONFDUMP(PIN_CONFIG_OLDI_SWAP_AB, "Swaps OLDI ports A and B", NULL, false),
-};
-#endif
-
-static int max96752f_pinconf_get(struct pinctrl_dev *pctldev,
-				 unsigned int pin, unsigned long *config)
-{
-	struct max96752f_pinctrl *mpctl = pinctrl_dev_get_drvdata(pctldev);
-	unsigned int param = pinconf_to_config_param(*config);
-	unsigned int gpio_a_reg, gpio_b_reg, oldi;
-	u16 arg = 0;
-
-	regmap_read(mpctl->regmap, GPIO_A_REG(pin), &gpio_a_reg);
-	regmap_read(mpctl->regmap, GPIO_B_REG(pin), &gpio_b_reg);
-	if (pin == 0)
-		regmap_read(mpctl->regmap, OLDI_REG(1), &oldi);
-
-	switch (param) {
-	case PIN_CONFIG_DRIVE_OPEN_DRAIN:
-		if (FIELD_GET(OUT_TYPE, gpio_b_reg))
-			return -EINVAL;
-		break;
-	case PIN_CONFIG_DRIVE_PUSH_PULL:
-		if (!FIELD_GET(OUT_TYPE, gpio_b_reg))
-			return -EINVAL;
-		break;
-	case PIN_CONFIG_BIAS_DISABLE:
-		if (FIELD_GET(PULL_UPDN_SEL, gpio_b_reg) != 0)
-			return -EINVAL;
-		break;
-	case PIN_CONFIG_BIAS_PULL_UP:
-		if (FIELD_GET(PULL_UPDN_SEL, gpio_b_reg) != 1)
-			return -EINVAL;
-		switch (FIELD_GET(RES_CFG, gpio_a_reg)) {
-		case 0:
-			arg = 40000;
-			break;
-		case 1:
-			arg = 10000;
-			break;
-		}
-		break;
-	case PIN_CONFIG_BIAS_PULL_DOWN:
-		if (FIELD_GET(PULL_UPDN_SEL, gpio_b_reg) != 2)
-			return -EINVAL;
-		switch (FIELD_GET(RES_CFG, gpio_a_reg)) {
-		case 0:
-			arg = 40000;
-			break;
-		case 1:
-			arg = 10000;
-			break;
-		}
-		break;
-	case PIN_CONFIG_OUTPUT:
-		if (FIELD_GET(GPIO_OUT_DIS, gpio_a_reg))
-			return -EINVAL;
-
-		arg = FIELD_GET(GPIO_OUT, gpio_a_reg);
-		break;
-	case PIN_CONFIG_OLDI_SPL_EN:
-		if (pin > 0)
-			return -EINVAL;
-
-		if (!FIELD_GET(OLDI_SPL_EN, oldi))
-			return -EINVAL;
-		break;
-	case PIN_CONFIG_OLDI_SWAP_AB:
-		if (pin > 0)
-			return -EINVAL;
-
-		if (!FIELD_GET(OLDI_SWAP_AB, oldi))
-			return -EINVAL;
-		break;
-	default:
-		return -ENOTSUPP;
-	}
-
-	*config = pinconf_to_config_packed(param, arg);
-
-	return 0;
-}
-
-static int max96752f_pinconf_set(struct pinctrl_dev *pctldev,
-				 unsigned int pin, unsigned long *configs,
-				 unsigned int num_configs)
-{
-	struct max96752f_pinctrl *mpctl = pinctrl_dev_get_drvdata(pctldev);
-	unsigned int param;
-	u32 arg;
-	u8 res_cfg;
-	int i;
-
-	for (i = 0; i < num_configs; i++) {
-		param = pinconf_to_config_param(configs[i]);
-		arg = pinconf_to_config_argument(configs[i]);
-
-		switch (param) {
-		case PIN_CONFIG_DRIVE_OPEN_DRAIN:
-			regmap_update_bits(mpctl->regmap, GPIO_B_REG(pin),
-					   OUT_TYPE, FIELD_PREP(OUT_TYPE, 0));
-			break;
-		case PIN_CONFIG_DRIVE_PUSH_PULL:
-			regmap_update_bits(mpctl->regmap, GPIO_B_REG(pin),
-					   OUT_TYPE, FIELD_PREP(OUT_TYPE, 1));
-			break;
-		case PIN_CONFIG_BIAS_DISABLE:
-			regmap_update_bits(mpctl->regmap, GPIO_C_REG(pin),
-					   PULL_UPDN_SEL,
-					   FIELD_PREP(PULL_UPDN_SEL, 0));
-			break;
-		case PIN_CONFIG_BIAS_PULL_UP:
-			switch (arg) {
-			case 40000:
-				res_cfg = 0;
-				break;
-			case 1000000:
-				res_cfg = 1;
-				break;
-			default:
-				return -EINVAL;
-			}
-
-			regmap_update_bits(mpctl->regmap, GPIO_A_REG(pin),
-					   RES_CFG, FIELD_PREP(RES_CFG, res_cfg));
-			regmap_update_bits(mpctl->regmap, GPIO_C_REG(pin),
-					   PULL_UPDN_SEL,
-					   FIELD_PREP(PULL_UPDN_SEL, 1));
-			break;
-		case PIN_CONFIG_BIAS_PULL_DOWN:
-			switch (arg) {
-			case 40000:
-				res_cfg = 0;
-				break;
-			case 1000000:
-				res_cfg = 1;
-				break;
-			default:
-				return -EINVAL;
-			}
-
-			regmap_update_bits(mpctl->regmap, GPIO_A_REG(pin),
-					   RES_CFG, FIELD_PREP(RES_CFG, res_cfg));
-			regmap_update_bits(mpctl->regmap, GPIO_C_REG(pin),
-					   PULL_UPDN_SEL,
-					   FIELD_PREP(PULL_UPDN_SEL, 2));
-			break;
-		case PIN_CONFIG_OUTPUT:
-			regmap_update_bits(mpctl->regmap, GPIO_A_REG(pin),
-					   GPIO_OUT_DIS | GPIO_OUT,
-					   FIELD_PREP(GPIO_OUT_DIS, 0) |
-					   FIELD_PREP(GPIO_OUT, arg));
-			break;
-		case PIN_CONFIG_OLDI_SPL_EN:
-			if (pin > 0)
-				return -ENOTSUPP;
-
-			regmap_update_bits(mpctl->regmap, OLDI_REG(1),
-					   OLDI_SPL_EN | OLDI_SPL_POL,
-					   FIELD_PREP(OLDI_SPL_EN, 1) |
-					   FIELD_PREP(OLDI_SPL_POL, 0));
-			break;
-		case PIN_CONFIG_OLDI_SWAP_AB:
-			if (pin > 0)
-				return -ENOTSUPP;
-
-			regmap_update_bits(mpctl->regmap, OLDI_REG(1),
-					   OLDI_SWAP_AB,
-					   FIELD_PREP(OLDI_SWAP_AB, 1));
-			break;
-		default:
-			return -ENOTSUPP;
-		}
-	}
-
-	return 0;
-}
-
-static const struct pinconf_ops max96752f_pinconf_ops = {
-	.is_generic = true,
-	.pin_config_get = max96752f_pinconf_get,
-	.pin_config_set = max96752f_pinconf_set,
-};
-
-static const struct pinmux_ops max96752f_pinmux_ops = {
-	.get_functions_count = pinmux_generic_get_function_count,
-	.get_function_name = pinmux_generic_get_function_name,
-	.get_function_groups = pinmux_generic_get_function_groups,
-	.set_mux = max96752f_pinmux_set_mux,
-};
-
-static const struct pinctrl_ops max96752f_pinctrl_ops = {
-	.get_groups_count = pinctrl_generic_get_group_count,
-	.get_group_name = pinctrl_generic_get_group_name,
-	.get_group_pins = pinctrl_generic_get_group_pins,
-	.dt_node_to_map = pinconf_generic_dt_node_to_map_all,
-	.dt_free_map = pinconf_generic_dt_free_map,
-};
-
-static const struct pinctrl_pin_desc max96752f_pins_desc[] = {
-	PINCTRL_PIN(0, "oldi"),
-	PINCTRL_PIN(1, "gpio1"),
-	PINCTRL_PIN(2, "gpio2"),
-	PINCTRL_PIN(3, "gpio3"),
-	PINCTRL_PIN(4, "gpio4"),
-	PINCTRL_PIN(5, "gpio5"),
-	PINCTRL_PIN(6, "gpio6"),
-	PINCTRL_PIN(7, "gpio7"),
-	PINCTRL_PIN(8, "gpio8"),
-	PINCTRL_PIN(9, "gpio9"),
-	PINCTRL_PIN(10, "gpio10"),
-	PINCTRL_PIN(11, "gpio11"),
-	PINCTRL_PIN(12, "gpio12"),
-	PINCTRL_PIN(13, "gpio13"),
-	PINCTRL_PIN(14, "gpio14"),
-	PINCTRL_PIN(15, "gpio15"),
-};
-
-static int oldi_pins[] = {0};
-static int gpio1_pins[] = {1};
-static int gpio2_pins[] = {2};
-static int gpio3_pins[] = {3};
-static int gpio4_pins[] = {4};
-static int gpio5_pins[] = {5};
-static int gpio6_pins[] = {6};
-static int gpio7_pins[] = {7};
-static int gpio8_pins[] = {8};
-static int gpio9_pins[] = {9};
-static int gpio10_pins[] = {10};
-static int gpio11_pins[] = {11};
-static int gpio12_pins[] = {12};
-static int gpio13_pins[] = {13};
-static int gpio14_pins[] = {14};
-static int gpio15_pins[] = {15};
-static int aud_rx_pins[] = {6, 7, 8};
-static int aud_tx_pins[] = {11, 12, 13};
-static int i2c_pins[] = {14, 15};
-static int uart_pins[] = {14, 15};
-
-#define GROUP_DESC(nm) \
-{ \
-	.name = #nm, \
-	.pins = nm ## _pins, \
-	.num_pins = ARRAY_SIZE(nm ## _pins), \
-}
-
-#define GROUP_DESC_CONFIG(nm) \
-{ \
-	.name = #nm, \
-	.pins = nm ## _pins, \
-	.num_pins = ARRAY_SIZE(nm ## _pins), \
-	.data = (void *)(const struct max96752f_group_data []) { \
-		{ \
-			.configs = nm ## _configs, \
-			.num_configs = ARRAY_SIZE(nm ## _configs), \
-		} \
-	}, \
-}
-
-static const struct config_desc gpio6_configs[] = {
-	{ 0x0001, IIC_2_EN, 0 },
-	{ 0x0002, AUD_TX_EN, 0 },
-};
-static const struct config_desc gpio7_configs[] = {
-	{ 0x0002, AUD_TX_EN, 0 },
-};
-static const struct config_desc gpio8_configs[] = {
-	{ 0x0001, IIC_2_EN, 0 },
-	{ 0x0002, AUD_TX_EN, 0 },
-};
-static const struct config_desc gpio11_configs[] = {
-	{ 0x0140, AUD_RX_EN, 0 },
-};
-static const struct config_desc gpio12_configs[] = {
-	{ 0x0140, AUD_RX_EN, 0 },
-};
-static const struct config_desc gpio13_configs[] = {
-	{ 0x0140, AUD_RX_EN, 0 },
-};
-static const struct config_desc gpio14_configs[] = {
-	{ 0x0002, DIS_LOCAL_CC, DIS_LOCAL_CC },
-};
-static const struct config_desc gpio15_configs[] = {
-	{ 0x0002, DIS_LOCAL_CC, DIS_LOCAL_CC },
-};
-static const struct config_desc aud_tx_configs[] = {
-	{ 0x0002, AUD_TX_EN, AUD_TX_EN },
-};
-static const struct config_desc aud_rx_configs[] = {
-	{ 0x0140, AUD_RX_EN, AUD_RX_EN },
-};
-static const struct config_desc i2c_configs[] = {
-	{ 0x0002, DIS_LOCAL_CC, 0 },
-	{ 0x0003, I2CSEL, I2CSEL },
-};
-static const struct config_desc uart_configs[] = {
-	{ 0x0002, DIS_LOCAL_CC, 0 },
-	{ 0x0003, I2CSEL, 0 },
-};
-
-static const struct group_desc max96752f_groups[] = {
-	GROUP_DESC(gpio1),
-	GROUP_DESC(gpio2),
-	GROUP_DESC(gpio3),
-	GROUP_DESC(gpio4),
-	GROUP_DESC(gpio5),
-	GROUP_DESC_CONFIG(gpio6),
-	GROUP_DESC_CONFIG(gpio7),
-	GROUP_DESC_CONFIG(gpio8),
-	GROUP_DESC(gpio9),
-	GROUP_DESC(gpio10),
-	GROUP_DESC_CONFIG(gpio11),
-	GROUP_DESC_CONFIG(gpio12),
-	GROUP_DESC_CONFIG(gpio13),
-	GROUP_DESC_CONFIG(gpio14),
-	GROUP_DESC_CONFIG(gpio15),
-	GROUP_DESC_CONFIG(aud_rx),
-	GROUP_DESC_CONFIG(aud_tx),
-	GROUP_DESC_CONFIG(i2c),
-	GROUP_DESC_CONFIG(uart),
-	GROUP_DESC(oldi),
-};
-static const char *gpio_groups[] = {
-	"reserved", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5",
-	"gpio6", "gpio7", "gpio8", "gpio9", "gpio10",
-	"gpio11", "gpio12", "gpio13", "gpio14", "gpio15",
-};
-static const char *aud_rx_groups[] = { "aud_rx" };
-static const char *aud_tx_groups[] = { "aud_tx" };
-static const char *i2c_groups[] = { "i2c" };
-static const char *uart_groups[] = { "uart" };
-static const char *oldi_groups[] = { "oldi" };
-
-#define FUNCTION_DESC(fname, gname) \
-{ \
-	.name = #fname, \
-	.group_names = gname##_groups, \
-	.num_group_names = ARRAY_SIZE(gname##_groups), \
-} \
-
-#define FUNCTION_DESC_GPIO() \
-{ \
-	.name = "GPIO", \
-	.group_names = gpio_groups, \
-	.num_group_names = ARRAY_SIZE(gpio_groups), \
-	.data = (void *)(const struct max96752f_function_data []) { \
-		{ } \
-	}, \
-} \
-
-#define FUNCTION_DESC_GPIO_RX(id) \
-{ \
-	.name = "GPIO_RX_"#id, \
-	.group_names = gpio_groups, \
-	.num_group_names = ARRAY_SIZE(gpio_groups), \
-	.data = (void *)(const struct max96752f_function_data []) { \
-		{ .gpio_rx_en = 1, .gpio_rx_id = id } \
-	}, \
-} \
-
-#define FUNCTION_DESC_GPIO_TX(id) \
-{ \
-	.name = "GPIO_TX_"#id, \
-	.group_names = gpio_groups, \
-	.num_group_names = ARRAY_SIZE(gpio_groups), \
-	.data = (void *)(const struct max96752f_function_data []) { \
-		{ .gpio_out_dis = 1, .gpio_tx_en = 1, .gpio_tx_id = id } \
-	}, \
-} \
-
-static const struct function_desc max96752f_functions[] = {
-	FUNCTION_DESC_GPIO_TX(0),
-	FUNCTION_DESC_GPIO_TX(1),
-	FUNCTION_DESC_GPIO_TX(2),
-	FUNCTION_DESC_GPIO_TX(3),
-	FUNCTION_DESC_GPIO_TX(4),
-	FUNCTION_DESC_GPIO_TX(5),
-	FUNCTION_DESC_GPIO_TX(6),
-	FUNCTION_DESC_GPIO_TX(7),
-	FUNCTION_DESC_GPIO_TX(8),
-	FUNCTION_DESC_GPIO_TX(9),
-	FUNCTION_DESC_GPIO_TX(10),
-	FUNCTION_DESC_GPIO_TX(11),
-	FUNCTION_DESC_GPIO_TX(12),
-	FUNCTION_DESC_GPIO_TX(13),
-	FUNCTION_DESC_GPIO_TX(14),
-	FUNCTION_DESC_GPIO_TX(15),
-	FUNCTION_DESC_GPIO_TX(16),
-	FUNCTION_DESC_GPIO_TX(17),
-	FUNCTION_DESC_GPIO_TX(18),
-	FUNCTION_DESC_GPIO_TX(19),
-	FUNCTION_DESC_GPIO_TX(20),
-	FUNCTION_DESC_GPIO_TX(21),
-	FUNCTION_DESC_GPIO_TX(22),
-	FUNCTION_DESC_GPIO_TX(23),
-	FUNCTION_DESC_GPIO_TX(24),
-	FUNCTION_DESC_GPIO_TX(25),
-	FUNCTION_DESC_GPIO_TX(26),
-	FUNCTION_DESC_GPIO_TX(27),
-	FUNCTION_DESC_GPIO_TX(28),
-	FUNCTION_DESC_GPIO_TX(29),
-	FUNCTION_DESC_GPIO_TX(30),
-	FUNCTION_DESC_GPIO_TX(31),
-	FUNCTION_DESC_GPIO_RX(0),
-	FUNCTION_DESC_GPIO_RX(1),
-	FUNCTION_DESC_GPIO_RX(2),
-	FUNCTION_DESC_GPIO_RX(3),
-	FUNCTION_DESC_GPIO_RX(4),
-	FUNCTION_DESC_GPIO_RX(5),
-	FUNCTION_DESC_GPIO_RX(6),
-	FUNCTION_DESC_GPIO_RX(7),
-	FUNCTION_DESC_GPIO_RX(8),
-	FUNCTION_DESC_GPIO_RX(9),
-	FUNCTION_DESC_GPIO_RX(10),
-	FUNCTION_DESC_GPIO_RX(11),
-	FUNCTION_DESC_GPIO_RX(12),
-	FUNCTION_DESC_GPIO_RX(13),
-	FUNCTION_DESC_GPIO_RX(14),
-	FUNCTION_DESC_GPIO_RX(15),
-	FUNCTION_DESC_GPIO_RX(16),
-	FUNCTION_DESC_GPIO_RX(17),
-	FUNCTION_DESC_GPIO_RX(18),
-	FUNCTION_DESC_GPIO_RX(19),
-	FUNCTION_DESC_GPIO_RX(20),
-	FUNCTION_DESC_GPIO_RX(21),
-	FUNCTION_DESC_GPIO_RX(22),
-	FUNCTION_DESC_GPIO_RX(23),
-	FUNCTION_DESC_GPIO_RX(24),
-	FUNCTION_DESC_GPIO_RX(25),
-	FUNCTION_DESC_GPIO_RX(26),
-	FUNCTION_DESC_GPIO_RX(27),
-	FUNCTION_DESC_GPIO_RX(28),
-	FUNCTION_DESC_GPIO_RX(29),
-	FUNCTION_DESC_GPIO_RX(30),
-	FUNCTION_DESC_GPIO_RX(31),
-	FUNCTION_DESC_GPIO(),
-	FUNCTION_DESC(AUD_RX, aud_rx),
-	FUNCTION_DESC(AUD_TX, aud_tx),
-	FUNCTION_DESC(I2C, i2c),
-	FUNCTION_DESC(UART, uart),
-	FUNCTION_DESC(OLDI, oldi),
-};
-
-static int max96752f_pinctrl_probe(struct platform_device *pdev)
-{
-	struct device *dev = &pdev->dev;
-	struct max96752f_pinctrl *mpctl;
-	struct pinctrl_desc *pctl_desc;
-	int i, ret;
-
-	mpctl = devm_kzalloc(dev, sizeof(*mpctl), GFP_KERNEL);
-	if (!mpctl)
-		return -ENOMEM;
-
-	mpctl->dev = dev;
-	platform_set_drvdata(pdev, mpctl);
-
-	mpctl->regmap = dev_get_regmap(dev->parent, NULL);
-	if (!mpctl->regmap)
-		return dev_err_probe(dev, -ENODEV, "failed to get regmap\n");
-
-	pctl_desc = devm_kzalloc(dev, sizeof(*pctl_desc), GFP_KERNEL);
-	if (!pctl_desc)
-		return -ENOMEM;
-
-	pctl_desc->name = dev_name(dev);
-	pctl_desc->owner = THIS_MODULE;
-	pctl_desc->pctlops = &max96752f_pinctrl_ops;
-	pctl_desc->pmxops = &max96752f_pinmux_ops;
-	pctl_desc->confops = &max96752f_pinconf_ops;
-	pctl_desc->pins = max96752f_pins_desc;
-	pctl_desc->npins = ARRAY_SIZE(max96752f_pins_desc);
-	pctl_desc->custom_params = max96752f_custom_params;
-	pctl_desc->num_custom_params = ARRAY_SIZE(max96752f_custom_params);
-#ifdef CONFIG_DEBUG_FS
-	pctl_desc->custom_conf_items = max96752f_custom_conf_items,
-#endif
-	ret = devm_pinctrl_register_and_init(dev, pctl_desc, mpctl,
-					     &mpctl->pctl);
-	if (ret)
-		return dev_err_probe(dev, ret, "failed to register pinctrl\n");
-
-	for (i = 0; i < ARRAY_SIZE(max96752f_groups); i++) {
-		const struct group_desc *group = &max96752f_groups[i];
-
-		ret = pinctrl_generic_add_group(mpctl->pctl, group->name,
-						group->pins, group->num_pins,
-						group->data);
-		if (ret < 0)
-			return dev_err_probe(dev, ret,
-					     "failed to register group %s\n",
-					     group->name);
-	}
-
-	for (i = 0; i < ARRAY_SIZE(max96752f_functions); i++) {
-		const struct function_desc *func = &max96752f_functions[i];
-
-		ret = pinmux_generic_add_function(mpctl->pctl, func->name,
-						  func->group_names,
-						  func->num_group_names,
-						  func->data);
-		if (ret < 0)
-			return dev_err_probe(dev, ret,
-					     "failed to register function %s\n",
-					     func->name);
-	}
-
-	return pinctrl_enable(mpctl->pctl);
-}
-
-static const struct of_device_id max96752f_pinctrl_of_match[] = {
-	{ .compatible = "maxim,max96752f-pinctrl" },
-	{}
-};
-MODULE_DEVICE_TABLE(of, max96752f_pinctrl_of_match);
-
-static struct platform_driver max96752f_pinctrl_driver = {
-	.driver = {
-		.name = "max96752f-pinctrl",
-		.of_match_table = max96752f_pinctrl_of_match,
-	},
-	.probe = max96752f_pinctrl_probe,
-};
-
-module_platform_driver(max96752f_pinctrl_driver);
-
-MODULE_AUTHOR("Wyon Bi <bivvy.bi@rock-chips.com>");
-MODULE_DESCRIPTION("Maxim MAX96752F pin control driver");
-MODULE_LICENSE("GPL");
diff --git a/drivers/rk_nand/rk_ftl_arm_v7.S b/drivers/rk_nand/rk_ftl_arm_v7.S
index db549c3b269e..da6f8a9667e3 100644
--- a/drivers/rk_nand/rk_ftl_arm_v7.S
+++ b/drivers/rk_nand/rk_ftl_arm_v7.S
@@ -16,7 +16,6 @@
 	.eabi_attribute 26, 2
 	.eabi_attribute 30, 4
 	.eabi_attribute 34, 1
-	.eabi_attribute 18, 4
 	.file	"rk_ftl_arm_v7.c"
 	.syntax unified
 	.text
diff --git a/drivers/rk_nand/rk_ftl_arm_v7_thumb.S b/drivers/rk_nand/rk_ftl_arm_v7_thumb.S
index a67898acb677..4cf752e4b834 100644
--- a/drivers/rk_nand/rk_ftl_arm_v7_thumb.S
+++ b/drivers/rk_nand/rk_ftl_arm_v7_thumb.S
@@ -17,7 +17,6 @@
 	.eabi_attribute 26, 2
 	.eabi_attribute 30, 4
 	.eabi_attribute 34, 1
-	.eabi_attribute 18, 4
 	.file	"rk_ftl_arm_v7.c"
 	.thumb
 	.text
diff --git a/drivers/rk_nand/rk_ftlv5_arm32.S b/drivers/rk_nand/rk_ftlv5_arm32.S
index 26e2a694fb6d..28d165342153 100644
--- a/drivers/rk_nand/rk_ftlv5_arm32.S
+++ b/drivers/rk_nand/rk_ftlv5_arm32.S
@@ -17,7 +17,6 @@
 	.eabi_attribute 26, 2
 	.eabi_attribute 30, 4
 	.eabi_attribute 34, 1
-	.eabi_attribute 18, 4
 	.file	"rk_ftlv5_arm_v8.c"
 	.text
 	.align	2
diff --git a/drivers/rk_nand/rk_zftl_arm32.S b/drivers/rk_nand/rk_zftl_arm32.S
index ec6959a4c9c9..4af2ab302d33 100644
--- a/drivers/rk_nand/rk_zftl_arm32.S
+++ b/drivers/rk_nand/rk_zftl_arm32.S
@@ -18,7 +18,6 @@
 	.eabi_attribute 26, 2
 	.eabi_attribute 30, 4
 	.eabi_attribute 34, 1
-	.eabi_attribute 18, 4
 	.file	"rk_zftl_arm_v7.c"
 	.syntax unified
 	.text
diff --git a/drivers/rkflash/sfc.h b/drivers/rkflash/sfc.h
index 703072d52086..8e91c376acf0 100644
--- a/drivers/rkflash/sfc.h
+++ b/drivers/rkflash/sfc.h
@@ -68,8 +68,8 @@
 
 /* SFC_DLL_CTRL Register */
 #define SCLK_SMP_SEL_EN		BIT(15)	/* SCLK Sampling Selection */
-#define SCLK_SMP_SEL_MAX_V4	0x1FF
-#define SCLK_SMP_SEL_MAX_V5	0xFF
+#define SCLK_SMP_SEL_MAX_V4	0xFF
+#define SCLK_SMP_SEL_MAX_V5	0x1FF
 
 #define SFC_DLL_TRANING_STEP		10	/* Training step */
 #define SFC_DLL_TRANING_VALID_WINDOW	80	/* Valid DLL winbow */
diff --git a/drivers/rknpu/rknpu_drv.c b/drivers/rknpu/rknpu_drv.c
index 30dfc38f76c9..26d10c233cc9 100644
--- a/drivers/rknpu/rknpu_drv.c
+++ b/drivers/rknpu/rknpu_drv.c
@@ -1107,6 +1107,66 @@ static struct devfreq_cooling_power npu_cooling_power = {
 };
 
 #if KERNEL_VERSION(5, 10, 0) <= LINUX_VERSION_CODE
+static int rk3588_npu_get_soc_info(struct device *dev, struct device_node *np,
+			       int *bin, int *process)
+{
+	int ret = 0;
+	u8 value = 0;
+
+	if (!bin)
+		return 0;
+
+	if (of_property_match_string(np, "nvmem-cell-names",
+				     "specification_serial_number") >= 0) {
+		ret = rockchip_nvmem_cell_read_u8(np,
+						  "specification_serial_number",
+						  &value);
+		if (ret) {
+			dev_err(dev,
+				"Failed to get specification_serial_number\n");
+			return ret;
+		}
+		/* RK3588M */
+		if (value == 0xd)
+			*bin = 1;
+		/* RK3588J */
+		else if (value == 0xa)
+			*bin = 2;
+	}
+	if (*bin < 0)
+		*bin = 0;
+	dev_info(dev, "bin=%d\n", *bin);
+
+	return ret;
+}
+
+static int rk3588_npu_set_soc_info(struct device *dev, struct device_node *np,
+			       int bin, int process, int volt_sel)
+{
+	struct opp_table *opp_table;
+	u32 supported_hw[2];
+
+	if (volt_sel < 0)
+		return 0;
+	if (bin < 0)
+		bin = 0;
+
+	if (!of_property_read_bool(np, "rockchip,supported-hw"))
+		return 0;
+
+	/* SoC Version */
+	supported_hw[0] = BIT(bin);
+	/* Speed Grade */
+	supported_hw[1] = BIT(volt_sel);
+	opp_table = dev_pm_opp_set_supported_hw(dev, supported_hw, 2);
+	if (IS_ERR(opp_table)) {
+		dev_err(dev, "failed to set supported opp\n");
+		return PTR_ERR(opp_table);
+	}
+
+	return 0;
+}
+
 static int rk3588_npu_set_read_margin(struct device *dev,
 				      struct rockchip_opp_info *opp_info,
 				      u32 rm)
@@ -1139,6 +1199,8 @@ static int rk3588_npu_set_read_margin(struct device *dev,
 }
 
 static const struct rockchip_opp_data rk3588_npu_opp_data = {
+	.get_soc_info = rk3588_npu_get_soc_info,
+	.set_soc_info = rk3588_npu_set_soc_info,
 	.set_read_margin = rk3588_npu_set_read_margin,
 };
 
diff --git a/drivers/rknpu/rknpu_job.c b/drivers/rknpu/rknpu_job.c
index 6f601ab5fe6d..9e50467b22ec 100644
--- a/drivers/rknpu/rknpu_job.c
+++ b/drivers/rknpu/rknpu_job.c
@@ -166,10 +166,10 @@ static inline int rknpu_job_wait(struct rknpu_job *job)
 	subcore_data = &rknpu_dev->subcore_datas[core_index];
 
 	do {
-		ret = wait_event_interruptible_timeout(
-			subcore_data->job_done_wq,
-			job->flags & RKNPU_JOB_DONE || rknpu_dev->soft_reseting,
-			msecs_to_jiffies(args->timeout));
+		ret = wait_event_timeout(subcore_data->job_done_wq,
+					 job->flags & RKNPU_JOB_DONE ||
+						 rknpu_dev->soft_reseting,
+					 msecs_to_jiffies(args->timeout));
 		if (++wait_count >= 3)
 			break;
 	} while (ret == 0 && job->in_queue[core_index]);
diff --git a/drivers/soc/rockchip/Kconfig.cpu b/drivers/soc/rockchip/Kconfig.cpu
index 3775e73e32cb..368fa6f9ad44 100644
--- a/drivers/soc/rockchip/Kconfig.cpu
+++ b/drivers/soc/rockchip/Kconfig.cpu
@@ -57,6 +57,9 @@ config CPU_RK3368
 config CPU_RK3399
 	bool "RK3399"
 
+config CPU_RK3528
+	bool "RK3528"
+
 config CPU_RK3568
 	bool "RK3566/8"
 
diff --git a/drivers/soc/rockchip/grf.c b/drivers/soc/rockchip/grf.c
index 97c276b6b416..7b1f24d279b4 100644
--- a/drivers/soc/rockchip/grf.c
+++ b/drivers/soc/rockchip/grf.c
@@ -319,7 +319,7 @@ static int __init rockchip_grf_init(void)
 	np = of_find_matching_node_and_match(NULL, rockchip_grf_dt_match,
 					     &match);
 	if (!np)
-		return -ENODEV;
+		return 0;
 	if (!match || !match->data) {
 		pr_err("%s: missing grf data\n", __func__);
 		return -EINVAL;
diff --git a/drivers/soc/rockchip/rockchip_debug.c b/drivers/soc/rockchip/rockchip_debug.c
index 37abfb79a483..1599b7a29808 100644
--- a/drivers/soc/rockchip/rockchip_debug.c
+++ b/drivers/soc/rockchip/rockchip_debug.c
@@ -433,7 +433,7 @@ static int rockchip_show_interrupts(char *p, int irq)
 			j *= 10;
 
 		buf += sprintf(buf, "%*s", prec + 8, "");
-		for_each_online_cpu(j)
+		for_each_possible_cpu(j)
 			buf += sprintf(buf, "CPU%-8d", j);
 		buf += sprintf(buf, "\n");
 	}
@@ -443,14 +443,14 @@ static int rockchip_show_interrupts(char *p, int irq)
 		goto outsparse;
 
 	if (desc->kstat_irqs)
-		for_each_online_cpu(j)
+		for_each_possible_cpu(j)
 			any_count |= *per_cpu_ptr(desc->kstat_irqs, j);
 
 	if ((!desc->action) && !any_count)
 		goto outsparse;
 
 	buf += sprintf(buf, "%*d: ", prec, i);
-	for_each_online_cpu(j)
+	for_each_possible_cpu(j)
 		buf += sprintf(buf, "%10u ", desc->kstat_irqs ?
 					*per_cpu_ptr(desc->kstat_irqs, j) : 0);
 
diff --git a/drivers/soc/rockchip/rockchip_opp_select.c b/drivers/soc/rockchip/rockchip_opp_select.c
index 4a50b4a6a347..34a19c753730 100644
--- a/drivers/soc/rockchip/rockchip_opp_select.c
+++ b/drivers/soc/rockchip/rockchip_opp_select.c
@@ -1709,6 +1709,8 @@ int rockchip_init_opp_table(struct device *dev, struct rockchip_opp_info *info,
 next:
 	rockchip_get_scale_volt_sel(dev, lkg_name, reg_name, bin, process,
 				    &scale, &volt_sel);
+	if (info && info->data && info->data->set_soc_info)
+		info->data->set_soc_info(dev, np, bin, process, volt_sel);
 	rockchip_set_opp_prop_name(dev, process, volt_sel);
 	ret = dev_pm_opp_of_add_table(dev);
 	if (ret) {
diff --git a/drivers/soc/rockchip/rockchip_system_monitor.c b/drivers/soc/rockchip/rockchip_system_monitor.c
index 4f3f46364355..e5350b3dd60e 100644
--- a/drivers/soc/rockchip/rockchip_system_monitor.c
+++ b/drivers/soc/rockchip/rockchip_system_monitor.c
@@ -297,6 +297,7 @@ static void rockchip_update_video_info(void)
 {
 	struct video_info *video_info;
 	unsigned int max_res = 0, max_stream_bitrate = 0, res = 0;
+	unsigned int max_video_framerate = 0;
 
 	mutex_lock(&video_info_mutex);
 	if (list_empty(&video_info_list)) {
@@ -311,6 +312,8 @@ static void rockchip_update_video_info(void)
 			max_res = res;
 		if (video_info->streamBitrate > max_stream_bitrate)
 			max_stream_bitrate = video_info->streamBitrate;
+		if (video_info->videoFramerate > max_video_framerate)
+			max_video_framerate = video_info->videoFramerate;
 	}
 	mutex_unlock(&video_info_mutex);
 
@@ -319,8 +322,9 @@ static void rockchip_update_video_info(void)
 	} else {
 		if (max_stream_bitrate == 10)
 			rockchip_set_system_status(SYS_STATUS_VIDEO_4K_10B);
-		else
-			rockchip_set_system_status(SYS_STATUS_VIDEO_4K);
+		if (max_video_framerate == 60)
+			rockchip_set_system_status(SYS_STATUS_VIDEO_4K_60P);
+		rockchip_set_system_status(SYS_STATUS_VIDEO_4K);
 	}
 }
 
diff --git a/drivers/usb/dwc2/core.c b/drivers/usb/dwc2/core.c
index 15911ac7582b..cbd5f1142f35 100644
--- a/drivers/usb/dwc2/core.c
+++ b/drivers/usb/dwc2/core.c
@@ -656,14 +656,24 @@ static void dwc2_clear_force_mode(struct dwc2_hsotg *hsotg)
  */
 void dwc2_force_dr_mode(struct dwc2_hsotg *hsotg)
 {
+	u32 count = 0;
+
 	switch (hsotg->dr_mode) {
 	case USB_DR_MODE_HOST:
 		/*
 		 * NOTE: This is required for some rockchip soc based
 		 * platforms on their host-only dwc2.
 		 */
-		if (!dwc2_hw_is_otg(hsotg))
-			msleep(50);
+		if (!dwc2_hw_is_otg(hsotg)) {
+			while (dwc2_readl(hsotg, GOTGCTL) & GOTGCTL_CONID_B) {
+				msleep(20);
+				if (++count > 10)
+					break;
+			}
+			if (count > 10)
+				dev_err(hsotg->dev,
+					"Waiting for Host Mode timed out");
+		}
 
 		break;
 	case USB_DR_MODE_PERIPHERAL:
diff --git a/drivers/video/rockchip/mpp/mpp_common.c b/drivers/video/rockchip/mpp/mpp_common.c
index 2ac23651b26f..e7c7e50a994c 100644
--- a/drivers/video/rockchip/mpp/mpp_common.c
+++ b/drivers/video/rockchip/mpp/mpp_common.c
@@ -806,6 +806,15 @@ static int mpp_task_run(struct mpp_dev *mpp,
 	} else {
 		mpp_set_grf(mpp->grf_info);
 	}
+	/*
+	 * for iommu share hardware, should attach to ensure
+	 * working in current device
+	 */
+	ret = mpp_iommu_attach(mpp->iommu_info);
+	if (ret) {
+		dev_err(mpp->dev, "mpp_iommu_attach failed\n");
+		return -ENODATA;
+	}
 
 	mpp_power_on(mpp);
 	mpp_debug_func(DEBUG_TASK_INFO, "pid %d run %s\n",
diff --git a/drivers/video/rockchip/mpp/mpp_iommu.c b/drivers/video/rockchip/mpp/mpp_iommu.c
index db98386da6cd..5ba44f54f5fe 100644
--- a/drivers/video/rockchip/mpp/mpp_iommu.c
+++ b/drivers/video/rockchip/mpp/mpp_iommu.c
@@ -388,6 +388,9 @@ int mpp_iommu_attach(struct mpp_iommu_info *info)
 	if (!info)
 		return 0;
 
+	if (info->domain == iommu_get_domain_for_dev(info->dev))
+		return 0;
+
 	return iommu_attach_group(info->domain, info->group);
 }
 
diff --git a/drivers/video/rockchip/mpp/mpp_rkvdec.c b/drivers/video/rockchip/mpp/mpp_rkvdec.c
index 7b8c8176f8e3..57694df86365 100644
--- a/drivers/video/rockchip/mpp/mpp_rkvdec.c
+++ b/drivers/video/rockchip/mpp/mpp_rkvdec.c
@@ -976,6 +976,13 @@ static int rkvdec_1126_run(struct mpp_dev *mpp, struct mpp_task *mpp_task)
 	return rkvdec_run(mpp, mpp_task);
 }
 
+static int rkvdec_px30_run(struct mpp_dev *mpp,
+		    struct mpp_task *mpp_task)
+{
+	mpp_iommu_flush_tlb(mpp->iommu_info);
+	return rkvdec_run(mpp, mpp_task);
+}
+
 static int rkvdec_irq(struct mpp_dev *mpp)
 {
 	mpp->irq_status = mpp_read(mpp, RKVDEC_REG_INT_EN);
@@ -1728,6 +1735,16 @@ static struct mpp_dev_ops rkvdec_v1_dev_ops = {
 	.free_task = rkvdec_free_task,
 };
 
+static struct mpp_dev_ops rkvdec_px30_dev_ops = {
+	.alloc_task = rkvdec_alloc_task,
+	.run = rkvdec_px30_run,
+	.irq = rkvdec_irq,
+	.isr = rkvdec_isr,
+	.finish = rkvdec_finish,
+	.result = rkvdec_result,
+	.free_task = rkvdec_free_task,
+};
+
 static struct mpp_hw_ops rkvdec_3328_hw_ops = {
 	.init = rkvdec_3328_init,
 	.exit = rkvdec_3328_exit,
@@ -1790,7 +1807,7 @@ static const struct mpp_dev_var rk_hevcdec_px30_data = {
 	.hw_info = &rk_hevcdec_hw_info,
 	.trans_info = rk_hevcdec_trans,
 	.hw_ops = &rkvdec_px30_hw_ops,
-	.dev_ops = &rkvdec_v1_dev_ops,
+	.dev_ops = &rkvdec_px30_dev_ops,
 };
 
 static const struct mpp_dev_var rkvdec_v1_data = {
diff --git a/drivers/video/rockchip/mpp/mpp_service.c b/drivers/video/rockchip/mpp/mpp_service.c
index ffd30b33f053..beba6c3c18c4 100644
--- a/drivers/video/rockchip/mpp/mpp_service.c
+++ b/drivers/video/rockchip/mpp/mpp_service.c
@@ -98,7 +98,7 @@ static int mpp_add_driver(struct mpp_service *srv,
 		     &srv->grf_infos[type],
 		     grf_name);
 
-	if (type == MPP_DRIVER_AV1DEC)
+	if (IS_ENABLED(CONFIG_ROCKCHIP_MPP_AV1DEC) && type == MPP_DRIVER_AV1DEC)
 		ret = av1dec_driver_register(driver);
 	else
 		ret = platform_driver_register(driver);
@@ -116,11 +116,9 @@ static int mpp_remove_driver(struct mpp_service *srv, int i)
 		if (i != MPP_DRIVER_AV1DEC) {
 			mpp_set_grf(&srv->grf_infos[i]);
 			platform_driver_unregister(srv->sub_drivers[i]);
-		}
-#if IS_ENABLED(CONFIG_ROCKCHIP_MPP_AV1DEC)
-		else
+		} else if (IS_ENABLED(CONFIG_ROCKCHIP_MPP_AV1DEC)) {
 			av1dec_driver_unregister(srv->sub_drivers[i]);
-#endif
+		}
 		srv->sub_drivers[i] = NULL;
 	}
 
diff --git a/drivers/video/rockchip/mpp/mpp_vdpu2.c b/drivers/video/rockchip/mpp/mpp_vdpu2.c
index b63fc48c4568..af9817570e53 100644
--- a/drivers/video/rockchip/mpp/mpp_vdpu2.c
+++ b/drivers/video/rockchip/mpp/mpp_vdpu2.c
@@ -375,6 +375,13 @@ static int vdpu_run(struct mpp_dev *mpp,
 	return 0;
 }
 
+static int vdpu_px30_run(struct mpp_dev *mpp,
+		    struct mpp_task *mpp_task)
+{
+	mpp_iommu_flush_tlb(mpp->iommu_info);
+	return vdpu_run(mpp, mpp_task);
+}
+
 static int vdpu_finish(struct mpp_dev *mpp,
 		       struct mpp_task *mpp_task)
 {
@@ -658,6 +665,16 @@ static struct mpp_dev_ops vdpu_v2_dev_ops = {
 	.free_task = vdpu_free_task,
 };
 
+static struct mpp_dev_ops vdpu_px30_dev_ops = {
+	.alloc_task = vdpu_alloc_task,
+	.run = vdpu_px30_run,
+	.irq = vdpu_irq,
+	.isr = vdpu_isr,
+	.finish = vdpu_finish,
+	.result = vdpu_result,
+	.free_task = vdpu_free_task,
+};
+
 static const struct mpp_dev_var vdpu_v2_data = {
 	.device_type = MPP_DEVICE_VDPU2,
 	.hw_info = &vdpu_v2_hw_info,
@@ -671,7 +688,7 @@ static const struct mpp_dev_var vdpu_px30_data = {
 	.hw_info = &vdpu_v2_hw_info,
 	.trans_info = vdpu_v2_trans,
 	.hw_ops = &vdpu_px30_hw_ops,
-	.dev_ops = &vdpu_v2_dev_ops,
+	.dev_ops = &vdpu_px30_dev_ops,
 };
 
 static const struct of_device_id mpp_vdpu2_dt_match[] = {
diff --git a/drivers/video/rockchip/mpp/mpp_vepu2.c b/drivers/video/rockchip/mpp/mpp_vepu2.c
index cb61fc044b6a..d87f7788dbc0 100644
--- a/drivers/video/rockchip/mpp/mpp_vepu2.c
+++ b/drivers/video/rockchip/mpp/mpp_vepu2.c
@@ -202,12 +202,13 @@ static int vepu_process_reg_fd(struct mpp_session *session,
 	if (fmt == VEPU2_FMT_JPEGE) {
 		task->offset_bs = mpp_query_reg_offset_info(&task->off_inf, VEPU2_REG_OUT_INDEX);
 
-		if (task->offset_bs > 0)
-			task->dmabuf_bs = dma_buf_get(fd_bs);
+		task->dmabuf_bs = dma_buf_get(fd_bs);
 
-		if (IS_ERR_OR_NULL(task->dmabuf_bs))
+		if (IS_ERR_OR_NULL(task->dmabuf_bs)) {
 			task->dmabuf_bs = NULL;
-		else
+			return 0;
+		}
+		if (task->offset_bs > 0)
 			dma_buf_end_cpu_access_partial(task->dmabuf_bs, DMA_TO_DEVICE, 0,
 						       task->offset_bs);
 	}
@@ -318,16 +319,30 @@ fail:
 
 static void *vepu_prepare(struct mpp_dev *mpp, struct mpp_task *mpp_task)
 {
-	unsigned long flags;
-	s32 core_id;
+	struct mpp_taskqueue *queue = mpp->queue;
 	struct vepu_dev *enc = to_vepu_dev(mpp);
 	struct vepu_ccu *ccu = enc->ccu;
+	unsigned long core_idle;
+	unsigned long flags;
+	u32 core_id_max;
+	s32 core_id;
+	u32 i;
 
 	spin_lock_irqsave(&ccu->lock, flags);
 
+	core_idle = queue->core_idle;
+	core_id_max = queue->core_id_max;
+
+	for (i = 0; i <= core_id_max; i++) {
+		struct mpp_dev *mpp = queue->cores[i];
+
+		if (mpp && mpp->disable)
+			clear_bit(i, &core_idle);
+	}
+
 	core_id = find_first_bit(&ccu->core_idle, ccu->core_num);
 
-	if (core_id >= ccu->core_num) {
+	if (core_id >= core_id_max + 1 || !queue->cores[core_id]) {
 		mpp_task = NULL;
 		mpp_dbg_core("core %d all busy %lx\n", core_id, ccu->core_idle);
 	} else {
@@ -388,6 +403,13 @@ static int vepu_run(struct mpp_dev *mpp,
 	return 0;
 }
 
+static int vepu_px30_run(struct mpp_dev *mpp,
+		    struct mpp_task *mpp_task)
+{
+	mpp_iommu_flush_tlb(mpp->iommu_info);
+	return vepu_run(mpp, mpp_task);
+}
+
 static int vepu_irq(struct mpp_dev *mpp)
 {
 	mpp->irq_status = mpp_read(mpp, VEPU2_REG_INT);
@@ -902,6 +924,20 @@ static struct mpp_dev_ops vepu_v2_dev_ops = {
 	.dump_session = vepu_dump_session,
 };
 
+static struct mpp_dev_ops vepu_px30_dev_ops = {
+	.alloc_task = vepu_alloc_task,
+	.run = vepu_px30_run,
+	.irq = vepu_irq,
+	.isr = vepu_isr,
+	.finish = vepu_finish,
+	.result = vepu_result,
+	.free_task = vepu_free_task,
+	.ioctl = vepu_control,
+	.init_session = vepu_init_session,
+	.free_session = vepu_free_session,
+	.dump_session = vepu_dump_session,
+};
+
 static struct mpp_dev_ops vepu_ccu_dev_ops = {
 	.alloc_task = vepu_alloc_task,
 	.prepare = vepu_prepare,
@@ -931,7 +967,7 @@ static const struct mpp_dev_var vepu_px30_data = {
 	.hw_info = &vepu_v2_hw_info,
 	.trans_info = trans_rk_vepu2,
 	.hw_ops = &vepu_px30_hw_ops,
-	.dev_ops = &vepu_v2_dev_ops,
+	.dev_ops = &vepu_px30_dev_ops,
 };
 
 static const struct mpp_dev_var vepu_ccu_data = {
diff --git a/drivers/video/rockchip/rga/RGA_API.c b/drivers/video/rockchip/rga/RGA_API.c
index 947a9b925f60..4359a6d50379 100644
--- a/drivers/video/rockchip/rga/RGA_API.c
+++ b/drivers/video/rockchip/rga/RGA_API.c
@@ -1,201 +1,201 @@
 /* SPDX-License-Identifier: GPL-2.0 */
-
-#include <linux/memory.h>
-#include "RGA_API.h"
-#include "rga.h"
-//#include "rga_angle.h"
-
-#define IS_YUV_420(format) \
-     ((format == RK_FORMAT_YCbCr_420_P) | (format == RK_FORMAT_YCbCr_420_SP) | \
-      (format == RK_FORMAT_YCrCb_420_P) | (format == RK_FORMAT_YCrCb_420_SP))
-
-#define IS_YUV_422(format) \
-     ((format == RK_FORMAT_YCbCr_422_P) | (format == RK_FORMAT_YCbCr_422_SP) | \
-      (format == RK_FORMAT_YCrCb_422_P) | (format == RK_FORMAT_YCrCb_422_SP))
-
-#define IS_YUV(format) \
-     ((format == RK_FORMAT_YCbCr_420_P) | (format == RK_FORMAT_YCbCr_420_SP) | \
-      (format == RK_FORMAT_YCrCb_420_P) | (format == RK_FORMAT_YCrCb_420_SP) | \
-      (format == RK_FORMAT_YCbCr_422_P) | (format == RK_FORMAT_YCbCr_422_SP) | \
-      (format == RK_FORMAT_YCrCb_422_P) | (format == RK_FORMAT_YCrCb_422_SP))
-
-
-extern rga_service_info rga_service;
-
-
-void
-matrix_cal(const struct rga_req *msg, TILE_INFO *tile)
-{
-    uint64_t x_time, y_time;
-    uint64_t sina, cosa;
-
-    int s_act_w, s_act_h, d_act_w, d_act_h;
-
-    s_act_w = msg->src.act_w;
-    s_act_h = msg->src.act_h;
-    d_act_w = msg->dst.act_w;
-    d_act_h = msg->dst.act_h;
-
-    if (s_act_w == 1) s_act_w += 1;
-    if (s_act_h == 1) s_act_h += 1;
-    if (d_act_h == 1) d_act_h += 1;
-    if (d_act_w == 1) d_act_w += 1;
-
-    x_time = ((s_act_w - 1)<<16) / (d_act_w - 1);
-    y_time = ((s_act_h - 1)<<16) / (d_act_h - 1);
-
-    sina = msg->sina;
-    cosa = msg->cosa;
-
-    switch(msg->rotate_mode)
-    {
-        /* 16.16 x 16.16 */
-        /* matrix[] is 64 bit wide */
-        case 1 :
-            tile->matrix[0] =  cosa*x_time;
-            tile->matrix[1] = -sina*y_time;
-            tile->matrix[2] =  sina*x_time;
-            tile->matrix[3] =  cosa*y_time;
-            break;
-        case 2 :
-            tile->matrix[0] = -(x_time<<16);
-            tile->matrix[1] = 0;
-            tile->matrix[2] = 0;
-            tile->matrix[3] = (y_time<<16);
-            break;
-        case 3 :
-            tile->matrix[0] = (x_time<<16);
-            tile->matrix[1] = 0;
-            tile->matrix[2] = 0;
-            tile->matrix[3] = -(y_time<<16);
-            break;
-        default :
-            tile->matrix[0] =  (uint64_t)1<<32;
-            tile->matrix[1] =  0;
-            tile->matrix[2] =  0;
-            tile->matrix[3] =  (uint64_t)1<<32;
-            break;
-    }
-}
-
-
-int32_t RGA_gen_two_pro(struct rga_req *msg, struct rga_req *msg1)
-{
-
-    struct rga_req *mp;
-    uint32_t w_ratio, h_ratio;
-    uint32_t stride;
-
-    uint32_t daw, dah;
-    uint32_t pl;
-
-    daw = dah = 0;
-
-    mp = msg1;
-
-    if(msg->dst.act_w == 0)
-    {
-        printk("%s, [%d] rga dst act_w is zero\n", __FUNCTION__, __LINE__);
-        return -EINVAL;
-    }
-
-    if (msg->dst.act_h == 0)
-    {
-        printk("%s, [%d] rga dst act_w is zero\n", __FUNCTION__, __LINE__);
-        return -EINVAL;
-    }
-    w_ratio = (msg->src.act_w << 16) / msg->dst.act_w;
-    h_ratio = (msg->src.act_h << 16) / msg->dst.act_h;
-
-    memcpy(msg1, msg, sizeof(struct rga_req));
-
-    msg->dst.format = msg->src.format;
-
-    /*pre_scale_w cal*/
-    if ((w_ratio >= (2<<16)) && (w_ratio < (4<<16))) {
-        daw = (msg->src.act_w + 1) >> 1;
-        if((IS_YUV_420(msg->dst.format)) && (daw & 1)) {
-            daw -= 1;
-            msg->src.act_w = daw << 1;
-        }
-    }
-    else if ((w_ratio >= (4<<16)) && (w_ratio < (8<<16))) {
-        daw = (msg->src.act_w + 3) >> 2;
-        if((IS_YUV_420(msg->dst.format)) && (daw & 1)) {
-            daw -= 1;
-            msg->src.act_w = daw << 2;
-        }
-    }
-    else if ((w_ratio >= (8<<16)) && (w_ratio < (16<<16))) {
-        daw = (msg->src.act_w + 7) >> 3;
-        if((IS_YUV_420(msg->dst.format)) && (daw & 1)) {
-            daw -= 1;
-            msg->src.act_w = daw << 3;
-        }
-    }
-    else
-    {
-        daw = msg->src.act_w;
-    }
-
-    pl = (RGA_pixel_width_init(msg->src.format));
-    stride = (pl * daw + 3) & (~3);
-    msg->dst.act_w = daw;
-    msg->dst.vir_w = stride / pl;
-
-    /*pre_scale_h cal*/
-    if ((h_ratio >= (2<<16)) && (h_ratio < (4<<16))) {
-        dah = (msg->src.act_h + 1) >> 1;
-        if((IS_YUV(msg->dst.format)) && (dah & 1)) {
-            dah -= 1;
-            msg->src.act_h = dah << 1;
-        }
-    }
-    else if ((h_ratio >= (4<<16)) && (h_ratio < (8<<16))) {
-        dah = (msg->src.act_h + 3) >> 2;
-        if((IS_YUV(msg->dst.format)) && (dah & 1)) {
-            dah -= 1;
-            msg->src.act_h = dah << 2;
-
-        }
-    }
-    else if ((h_ratio >= (8<<16)) && (h_ratio < (16<<16))) {
-        dah = (msg->src.act_h + 7) >> 3;
-        if((IS_YUV(msg->dst.format)) && (dah & 1)) {
-            dah -= 1;
-            msg->src.act_h = dah << 3;
-        }
-    }
-    else
-    {
-        dah = msg->src.act_h;
-    }
-
-    msg->dst.act_h = dah;
-    msg->dst.vir_h = dah;
-
-    msg->dst.x_offset = 0;
-    msg->dst.y_offset = 0;
-
-    msg->dst.yrgb_addr = (unsigned long)rga_service.pre_scale_buf;
-    msg->dst.uv_addr = msg->dst.yrgb_addr + stride * dah;
-    msg->dst.v_addr = msg->dst.uv_addr + ((stride * dah) >> 1);
-
-    msg->render_mode = pre_scaling_mode;
-
-    msg1->src.yrgb_addr = msg->dst.yrgb_addr;
-    msg1->src.uv_addr = msg->dst.uv_addr;
-    msg1->src.v_addr = msg->dst.v_addr;
-
-    msg1->src.act_w = msg->dst.act_w;
-    msg1->src.act_h = msg->dst.act_h;
-    msg1->src.vir_w = msg->dst.vir_w;
-    msg1->src.vir_h = msg->dst.vir_h;
-
-    msg1->src.x_offset = 0;
-    msg1->src.y_offset = 0;
-
-    return 0;
-}
-
-
+
+#include <linux/memory.h>
+#include "RGA_API.h"
+#include "rga.h"
+//#include "rga_angle.h"
+
+#define IS_YUV_420(format) \
+     ((format == RK_FORMAT_YCbCr_420_P) | (format == RK_FORMAT_YCbCr_420_SP) | \
+      (format == RK_FORMAT_YCrCb_420_P) | (format == RK_FORMAT_YCrCb_420_SP))
+
+#define IS_YUV_422(format) \
+     ((format == RK_FORMAT_YCbCr_422_P) | (format == RK_FORMAT_YCbCr_422_SP) | \
+      (format == RK_FORMAT_YCrCb_422_P) | (format == RK_FORMAT_YCrCb_422_SP))
+
+#define IS_YUV(format) \
+     ((format == RK_FORMAT_YCbCr_420_P) | (format == RK_FORMAT_YCbCr_420_SP) | \
+      (format == RK_FORMAT_YCrCb_420_P) | (format == RK_FORMAT_YCrCb_420_SP) | \
+      (format == RK_FORMAT_YCbCr_422_P) | (format == RK_FORMAT_YCbCr_422_SP) | \
+      (format == RK_FORMAT_YCrCb_422_P) | (format == RK_FORMAT_YCrCb_422_SP))
+
+
+extern rga_service_info rga_service;
+
+
+void
+matrix_cal(const struct rga_req *msg, TILE_INFO *tile)
+{
+    uint64_t x_time, y_time;
+    uint64_t sina, cosa;
+
+    int s_act_w, s_act_h, d_act_w, d_act_h;
+
+    s_act_w = msg->src.act_w;
+    s_act_h = msg->src.act_h;
+    d_act_w = msg->dst.act_w;
+    d_act_h = msg->dst.act_h;
+
+    if (s_act_w == 1) s_act_w += 1;
+    if (s_act_h == 1) s_act_h += 1;
+    if (d_act_h == 1) d_act_h += 1;
+    if (d_act_w == 1) d_act_w += 1;
+
+    x_time = ((s_act_w - 1)<<16) / (d_act_w - 1);
+    y_time = ((s_act_h - 1)<<16) / (d_act_h - 1);
+
+    sina = msg->sina;
+    cosa = msg->cosa;
+
+    switch(msg->rotate_mode)
+    {
+        /* 16.16 x 16.16 */
+        /* matrix[] is 64 bit wide */
+        case 1 :
+            tile->matrix[0] =  cosa*x_time;
+            tile->matrix[1] = -sina*y_time;
+            tile->matrix[2] =  sina*x_time;
+            tile->matrix[3] =  cosa*y_time;
+            break;
+        case 2 :
+            tile->matrix[0] = -(x_time<<16);
+            tile->matrix[1] = 0;
+            tile->matrix[2] = 0;
+            tile->matrix[3] = (y_time<<16);
+            break;
+        case 3 :
+            tile->matrix[0] = (x_time<<16);
+            tile->matrix[1] = 0;
+            tile->matrix[2] = 0;
+            tile->matrix[3] = -(y_time<<16);
+            break;
+        default :
+            tile->matrix[0] =  (uint64_t)1<<32;
+            tile->matrix[1] =  0;
+            tile->matrix[2] =  0;
+            tile->matrix[3] =  (uint64_t)1<<32;
+            break;
+    }
+}
+
+
+int32_t RGA_gen_two_pro(struct rga_req *msg, struct rga_req *msg1)
+{
+
+    struct rga_req *mp;
+    uint32_t w_ratio, h_ratio;
+    uint32_t stride;
+
+    uint32_t daw, dah;
+    uint32_t pl;
+
+    daw = dah = 0;
+
+    mp = msg1;
+
+    if(msg->dst.act_w == 0)
+    {
+        printk("%s, [%d] rga dst act_w is zero\n", __FUNCTION__, __LINE__);
+        return -EINVAL;
+    }
+
+    if (msg->dst.act_h == 0)
+    {
+        printk("%s, [%d] rga dst act_w is zero\n", __FUNCTION__, __LINE__);
+        return -EINVAL;
+    }
+    w_ratio = (msg->src.act_w << 16) / msg->dst.act_w;
+    h_ratio = (msg->src.act_h << 16) / msg->dst.act_h;
+
+    memcpy(msg1, msg, sizeof(struct rga_req));
+
+    msg->dst.format = msg->src.format;
+
+    /*pre_scale_w cal*/
+    if ((w_ratio >= (2<<16)) && (w_ratio < (4<<16))) {
+        daw = (msg->src.act_w + 1) >> 1;
+        if((IS_YUV_420(msg->dst.format)) && (daw & 1)) {
+            daw -= 1;
+            msg->src.act_w = daw << 1;
+        }
+    }
+    else if ((w_ratio >= (4<<16)) && (w_ratio < (8<<16))) {
+        daw = (msg->src.act_w + 3) >> 2;
+        if((IS_YUV_420(msg->dst.format)) && (daw & 1)) {
+            daw -= 1;
+            msg->src.act_w = daw << 2;
+        }
+    }
+    else if ((w_ratio >= (8<<16)) && (w_ratio < (16<<16))) {
+        daw = (msg->src.act_w + 7) >> 3;
+        if((IS_YUV_420(msg->dst.format)) && (daw & 1)) {
+            daw -= 1;
+            msg->src.act_w = daw << 3;
+        }
+    }
+    else
+    {
+        daw = msg->src.act_w;
+    }
+
+    pl = (RGA_pixel_width_init(msg->src.format));
+    stride = (pl * daw + 3) & (~3);
+    msg->dst.act_w = daw;
+    msg->dst.vir_w = stride / pl;
+
+    /*pre_scale_h cal*/
+    if ((h_ratio >= (2<<16)) && (h_ratio < (4<<16))) {
+        dah = (msg->src.act_h + 1) >> 1;
+        if((IS_YUV(msg->dst.format)) && (dah & 1)) {
+            dah -= 1;
+            msg->src.act_h = dah << 1;
+        }
+    }
+    else if ((h_ratio >= (4<<16)) && (h_ratio < (8<<16))) {
+        dah = (msg->src.act_h + 3) >> 2;
+        if((IS_YUV(msg->dst.format)) && (dah & 1)) {
+            dah -= 1;
+            msg->src.act_h = dah << 2;
+
+        }
+    }
+    else if ((h_ratio >= (8<<16)) && (h_ratio < (16<<16))) {
+        dah = (msg->src.act_h + 7) >> 3;
+        if((IS_YUV(msg->dst.format)) && (dah & 1)) {
+            dah -= 1;
+            msg->src.act_h = dah << 3;
+        }
+    }
+    else
+    {
+        dah = msg->src.act_h;
+    }
+
+    msg->dst.act_h = dah;
+    msg->dst.vir_h = dah;
+
+    msg->dst.x_offset = 0;
+    msg->dst.y_offset = 0;
+
+    msg->dst.yrgb_addr = (unsigned long)rga_service.pre_scale_buf;
+    msg->dst.uv_addr = msg->dst.yrgb_addr + stride * dah;
+    msg->dst.v_addr = msg->dst.uv_addr + ((stride * dah) >> 1);
+
+    msg->render_mode = pre_scaling_mode;
+
+    msg1->src.yrgb_addr = msg->dst.yrgb_addr;
+    msg1->src.uv_addr = msg->dst.uv_addr;
+    msg1->src.v_addr = msg->dst.v_addr;
+
+    msg1->src.act_w = msg->dst.act_w;
+    msg1->src.act_h = msg->dst.act_h;
+    msg1->src.vir_w = msg->dst.vir_w;
+    msg1->src.vir_h = msg->dst.vir_h;
+
+    msg1->src.x_offset = 0;
+    msg1->src.y_offset = 0;
+
+    return 0;
+}
+
+
diff --git a/drivers/video/rockchip/rga/RGA_API.h b/drivers/video/rockchip/rga/RGA_API.h
index ade17d03e85c..96ca5240ad83 100644
--- a/drivers/video/rockchip/rga/RGA_API.h
+++ b/drivers/video/rockchip/rga/RGA_API.h
@@ -1,14 +1,14 @@
 /* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __RGA_API_H__
-#define __RGA_API_H__
+#ifndef __RGA_API_H__
+#define __RGA_API_H__
 
 #include <linux/miscdevice.h>
 #include <linux/wakelock.h>
-
-#include "rga_reg_info.h"
-#include "rga.h"
-
-#define ENABLE      1
+
+#include "rga_reg_info.h"
+#include "rga.h"
+
+#define ENABLE      1
 #define DISABLE     0
 
 struct rga_drvdata {
@@ -31,10 +31,10 @@ struct rga_drvdata {
 	char *version;
 };
 
-int32_t RGA_gen_two_pro(struct rga_req *msg, struct rga_req *msg1);
-
-
-
-
-
-#endif
+int32_t RGA_gen_two_pro(struct rga_req *msg, struct rga_req *msg1);
+
+
+
+
+
+#endif
diff --git a/drivers/video/rockchip/rga/rga.h b/drivers/video/rockchip/rga/rga.h
index e54a6efba39f..9e39dc2aa2d1 100644
--- a/drivers/video/rockchip/rga/rga.h
+++ b/drivers/video/rockchip/rga/rga.h
@@ -1,508 +1,508 @@
 /* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _RGA_DRIVER_H_
-#define _RGA_DRIVER_H_
-
-#include <linux/mutex.h>
-#include <linux/scatterlist.h>
-
-
-#define RGA_BLIT_SYNC	0x5017
-#define RGA_BLIT_ASYNC  0x5018
-#define RGA_FLUSH       0x5019
-#define RGA_GET_RESULT  0x501a
-#define RGA_GET_VERSION 0x501b
-
-
-#define RGA_REG_CTRL_LEN    0x8    /* 8  */
-#define RGA_REG_CMD_LEN     0x20   /* 32 */
-#define RGA_CMD_BUF_SIZE    0x700  /* 16*28*4 */
-
-#define RGA_OUT_OF_RESOURCES    -10
-#define RGA_MALLOC_ERROR        -11
-
+#ifndef _RGA_DRIVER_H_
+#define _RGA_DRIVER_H_
+
+#include <linux/mutex.h>
+#include <linux/scatterlist.h>
+
+
+#define RGA_BLIT_SYNC	0x5017
+#define RGA_BLIT_ASYNC  0x5018
+#define RGA_FLUSH       0x5019
+#define RGA_GET_RESULT  0x501a
+#define RGA_GET_VERSION 0x501b
+
+
+#define RGA_REG_CTRL_LEN    0x8    /* 8  */
+#define RGA_REG_CMD_LEN     0x20   /* 32 */
+#define RGA_CMD_BUF_SIZE    0x700  /* 16*28*4 */
+
+#define RGA_OUT_OF_RESOURCES    -10
+#define RGA_MALLOC_ERROR        -11
+
 #define RGA_BUF_GEM_TYPE_MASK	0xC0
-
-#define rgaIS_ERROR(status)			(status < 0)
-#define rgaNO_ERROR(status)			(status >= 0)
-#define rgaIS_SUCCESS(status)		(status == 0)
-
+
+#define rgaIS_ERROR(status)			(status < 0)
+#define rgaNO_ERROR(status)			(status >= 0)
+#define rgaIS_SUCCESS(status)		(status == 0)
+
 #define RGA_DEBUGFS 1
-
-/* RGA process mode enum */
-enum
-{
-    bitblt_mode               = 0x0,
-    color_palette_mode        = 0x1,
-    color_fill_mode           = 0x2,
-    line_point_drawing_mode   = 0x3,
-    blur_sharp_filter_mode    = 0x4,
-    pre_scaling_mode          = 0x5,
-    update_palette_table_mode = 0x6,
-    update_patten_buff_mode   = 0x7,
-};
-
-
-enum
-{
-    rop_enable_mask          = 0x2,
-    dither_enable_mask       = 0x8,
-    fading_enable_mask       = 0x10,
-    PD_enbale_mask           = 0x20,
-};
-
-enum
-{
-    yuv2rgb_mode0            = 0x0,     /* BT.601 MPEG */
-    yuv2rgb_mode1            = 0x1,     /* BT.601 JPEG */
-    yuv2rgb_mode2            = 0x2,     /* BT.709      */
-};
-
-
-/* RGA rotate mode */
-enum
-{
-    rotate_mode0             = 0x0,     /* no rotate */
-    rotate_mode1             = 0x1,     /* rotate    */
-    rotate_mode2             = 0x2,     /* x_mirror  */
-    rotate_mode3             = 0x3,     /* y_mirror  */
-};
-
-enum
-{
-    color_palette_mode0      = 0x0,     /* 1K */
-    color_palette_mode1      = 0x1,     /* 2K */
-    color_palette_mode2      = 0x2,     /* 4K */
-    color_palette_mode3      = 0x3,     /* 8K */
-};
-
-
-
-/*
-//          Alpha    Red     Green   Blue
-{  4, 32, {{32,24,   8, 0,  16, 8,  24,16 }}, GGL_RGBA },   // RK_FORMAT_RGBA_8888
-{  4, 24, {{ 0, 0,   8, 0,  16, 8,  24,16 }}, GGL_RGB  },   // RK_FORMAT_RGBX_8888
-{  3, 24, {{ 0, 0,   8, 0,  16, 8,  24,16 }}, GGL_RGB  },   // RK_FORMAT_RGB_888
-{  4, 32, {{32,24,  24,16,  16, 8,   8, 0 }}, GGL_BGRA },   // RK_FORMAT_BGRA_8888
-{  2, 16, {{ 0, 0,  16,11,  11, 5,   5, 0 }}, GGL_RGB  },   // RK_FORMAT_RGB_565
-{  2, 16, {{ 1, 0,  16,11,  11, 6,   6, 1 }}, GGL_RGBA },   // RK_FORMAT_RGBA_5551
-{  2, 16, {{ 4, 0,  16,12,  12, 8,   8, 4 }}, GGL_RGBA },   // RK_FORMAT_RGBA_4444
-{  3, 24, {{ 0, 0,  24,16,  16, 8,   8, 0 }}, GGL_BGR  },   // RK_FORMAT_BGB_888
-
-*/
-enum
-{
-	RK_FORMAT_RGBA_8888    = 0x0,
-    RK_FORMAT_RGBX_8888    = 0x1,
-    RK_FORMAT_RGB_888      = 0x2,
-    RK_FORMAT_BGRA_8888    = 0x3,
-    RK_FORMAT_RGB_565      = 0x4,
-    RK_FORMAT_RGBA_5551    = 0x5,
-    RK_FORMAT_RGBA_4444    = 0x6,
-    RK_FORMAT_BGR_888      = 0x7,
-
-    RK_FORMAT_YCbCr_422_SP = 0x8,
-    RK_FORMAT_YCbCr_422_P  = 0x9,
-    RK_FORMAT_YCbCr_420_SP = 0xa,
-    RK_FORMAT_YCbCr_420_P  = 0xb,
-
-    RK_FORMAT_YCrCb_422_SP = 0xc,
-    RK_FORMAT_YCrCb_422_P  = 0xd,
-    RK_FORMAT_YCrCb_420_SP = 0xe,
-    RK_FORMAT_YCrCb_420_P  = 0xf,
-
-    RK_FORMAT_BPP1         = 0x10,
-    RK_FORMAT_BPP2         = 0x11,
-    RK_FORMAT_BPP4         = 0x12,
-    RK_FORMAT_BPP8         = 0x13,
-    RK_FORMAT_YCbCr_420_SP_10B = 0x20,
-    RK_FORMAT_YCrCb_420_SP_10B = 0x21,
-};
-
-
-typedef struct rga_img_info_t
-{
-    unsigned long yrgb_addr;      /* yrgb    mem addr         */
-    unsigned long uv_addr;        /* cb/cr   mem addr         */
-    unsigned long v_addr;         /* cr      mem addr         */
-    unsigned int format;         //definition by RK_FORMAT
-
-    unsigned short act_w;
-    unsigned short act_h;
-    unsigned short x_offset;
-    unsigned short y_offset;
-
-    unsigned short vir_w;
-    unsigned short vir_h;
-
-    unsigned short endian_mode; //for BPP
-    unsigned short alpha_swap;
-}
-rga_img_info_t;
-
-
-typedef struct mdp_img_act
-{
-    unsigned short w;         // width
-    unsigned short h;         // height
-    short x_off;     // x offset for the vir
-    short y_off;     // y offset for the vir
-}
-mdp_img_act;
-
-
-
-typedef struct RANGE
-{
-    unsigned short min;
-    unsigned short max;
-}
-RANGE;
-
-typedef struct POINT
-{
-    unsigned short x;
-    unsigned short y;
-}
-POINT;
-
-typedef struct RECT
-{
-    unsigned short xmin;
-    unsigned short xmax; // width - 1
-    unsigned short ymin;
-    unsigned short ymax; // height - 1
-} RECT;
-
-typedef struct RGB
-{
-    unsigned char r;
-    unsigned char g;
-    unsigned char b;
-    unsigned char res;
-}RGB;
-
-
-typedef struct MMU
-{
-    unsigned char mmu_en;
-    unsigned long base_addr;
+
+/* RGA process mode enum */
+enum
+{
+    bitblt_mode               = 0x0,
+    color_palette_mode        = 0x1,
+    color_fill_mode           = 0x2,
+    line_point_drawing_mode   = 0x3,
+    blur_sharp_filter_mode    = 0x4,
+    pre_scaling_mode          = 0x5,
+    update_palette_table_mode = 0x6,
+    update_patten_buff_mode   = 0x7,
+};
+
+
+enum
+{
+    rop_enable_mask          = 0x2,
+    dither_enable_mask       = 0x8,
+    fading_enable_mask       = 0x10,
+    PD_enbale_mask           = 0x20,
+};
+
+enum
+{
+    yuv2rgb_mode0            = 0x0,     /* BT.601 MPEG */
+    yuv2rgb_mode1            = 0x1,     /* BT.601 JPEG */
+    yuv2rgb_mode2            = 0x2,     /* BT.709      */
+};
+
+
+/* RGA rotate mode */
+enum
+{
+    rotate_mode0             = 0x0,     /* no rotate */
+    rotate_mode1             = 0x1,     /* rotate    */
+    rotate_mode2             = 0x2,     /* x_mirror  */
+    rotate_mode3             = 0x3,     /* y_mirror  */
+};
+
+enum
+{
+    color_palette_mode0      = 0x0,     /* 1K */
+    color_palette_mode1      = 0x1,     /* 2K */
+    color_palette_mode2      = 0x2,     /* 4K */
+    color_palette_mode3      = 0x3,     /* 8K */
+};
+
+
+
+/*
+//          Alpha    Red     Green   Blue
+{  4, 32, {{32,24,   8, 0,  16, 8,  24,16 }}, GGL_RGBA },   // RK_FORMAT_RGBA_8888
+{  4, 24, {{ 0, 0,   8, 0,  16, 8,  24,16 }}, GGL_RGB  },   // RK_FORMAT_RGBX_8888
+{  3, 24, {{ 0, 0,   8, 0,  16, 8,  24,16 }}, GGL_RGB  },   // RK_FORMAT_RGB_888
+{  4, 32, {{32,24,  24,16,  16, 8,   8, 0 }}, GGL_BGRA },   // RK_FORMAT_BGRA_8888
+{  2, 16, {{ 0, 0,  16,11,  11, 5,   5, 0 }}, GGL_RGB  },   // RK_FORMAT_RGB_565
+{  2, 16, {{ 1, 0,  16,11,  11, 6,   6, 1 }}, GGL_RGBA },   // RK_FORMAT_RGBA_5551
+{  2, 16, {{ 4, 0,  16,12,  12, 8,   8, 4 }}, GGL_RGBA },   // RK_FORMAT_RGBA_4444
+{  3, 24, {{ 0, 0,  24,16,  16, 8,   8, 0 }}, GGL_BGR  },   // RK_FORMAT_BGB_888
+
+*/
+enum
+{
+	RK_FORMAT_RGBA_8888    = 0x0,
+    RK_FORMAT_RGBX_8888    = 0x1,
+    RK_FORMAT_RGB_888      = 0x2,
+    RK_FORMAT_BGRA_8888    = 0x3,
+    RK_FORMAT_RGB_565      = 0x4,
+    RK_FORMAT_RGBA_5551    = 0x5,
+    RK_FORMAT_RGBA_4444    = 0x6,
+    RK_FORMAT_BGR_888      = 0x7,
+
+    RK_FORMAT_YCbCr_422_SP = 0x8,
+    RK_FORMAT_YCbCr_422_P  = 0x9,
+    RK_FORMAT_YCbCr_420_SP = 0xa,
+    RK_FORMAT_YCbCr_420_P  = 0xb,
+
+    RK_FORMAT_YCrCb_422_SP = 0xc,
+    RK_FORMAT_YCrCb_422_P  = 0xd,
+    RK_FORMAT_YCrCb_420_SP = 0xe,
+    RK_FORMAT_YCrCb_420_P  = 0xf,
+
+    RK_FORMAT_BPP1         = 0x10,
+    RK_FORMAT_BPP2         = 0x11,
+    RK_FORMAT_BPP4         = 0x12,
+    RK_FORMAT_BPP8         = 0x13,
+    RK_FORMAT_YCbCr_420_SP_10B = 0x20,
+    RK_FORMAT_YCrCb_420_SP_10B = 0x21,
+};
+
+
+typedef struct rga_img_info_t
+{
+    unsigned long yrgb_addr;      /* yrgb    mem addr         */
+    unsigned long uv_addr;        /* cb/cr   mem addr         */
+    unsigned long v_addr;         /* cr      mem addr         */
+    unsigned int format;         //definition by RK_FORMAT
+
+    unsigned short act_w;
+    unsigned short act_h;
+    unsigned short x_offset;
+    unsigned short y_offset;
+
+    unsigned short vir_w;
+    unsigned short vir_h;
+
+    unsigned short endian_mode; //for BPP
+    unsigned short alpha_swap;
+}
+rga_img_info_t;
+
+
+typedef struct mdp_img_act
+{
+    unsigned short w;         // width
+    unsigned short h;         // height
+    short x_off;     // x offset for the vir
+    short y_off;     // y offset for the vir
+}
+mdp_img_act;
+
+
+
+typedef struct RANGE
+{
+    unsigned short min;
+    unsigned short max;
+}
+RANGE;
+
+typedef struct POINT
+{
+    unsigned short x;
+    unsigned short y;
+}
+POINT;
+
+typedef struct RECT
+{
+    unsigned short xmin;
+    unsigned short xmax; // width - 1
+    unsigned short ymin;
+    unsigned short ymax; // height - 1
+} RECT;
+
+typedef struct RGB
+{
+    unsigned char r;
+    unsigned char g;
+    unsigned char b;
+    unsigned char res;
+}RGB;
+
+
+typedef struct MMU
+{
+    unsigned char mmu_en;
+    unsigned long base_addr;
 	uint32_t mmu_flag;
-} MMU;
-
-
-
-
-typedef struct COLOR_FILL
-{
-    short gr_x_a;
-    short gr_y_a;
-    short gr_x_b;
-    short gr_y_b;
-    short gr_x_g;
-    short gr_y_g;
-    short gr_x_r;
-    short gr_y_r;
-
-    //u8  cp_gr_saturation;
-}
-COLOR_FILL;
-
-typedef struct FADING
-{
-    uint8_t b;
-    uint8_t g;
-    uint8_t r;
-    uint8_t res;
-}
-FADING;
-
-
-typedef struct line_draw_t
-{
-    POINT start_point;              /* LineDraw_start_point                */
-    POINT end_point;                /* LineDraw_end_point                  */
-    uint32_t   color;               /* LineDraw_color                      */
-    uint32_t   flag;                /* (enum) LineDrawing mode sel         */
-    uint32_t   line_width;          /* range 1~16 */
-}
-line_draw_t;
-
-
-
-struct rga_req {
-    uint8_t render_mode;            /* (enum) process mode sel */
-
-    rga_img_info_t src;             /* src image info */
-    rga_img_info_t dst;             /* dst image info */
-    rga_img_info_t pat;             /* patten image info */
-
-    unsigned long rop_mask_addr;         /* rop4 mask addr */
-    unsigned long LUT_addr;              /* LUT addr */
-
-    RECT clip;                      /* dst clip window default value is dst_vir */
-                                    /* value from [0, w-1] / [0, h-1]*/
-
-    int32_t sina;                   /* dst angle  default value 0  16.16 scan from table */
-    int32_t cosa;                   /* dst angle  default value 0  16.16 scan from table */
-
-    uint16_t alpha_rop_flag;        /* alpha rop process flag           */
-                                    /* ([0] = 1 alpha_rop_enable)       */
-                                    /* ([1] = 1 rop enable)             */
-                                    /* ([2] = 1 fading_enable)          */
-                                    /* ([3] = 1 PD_enable)              */
-                                    /* ([4] = 1 alpha cal_mode_sel)     */
-                                    /* ([5] = 1 dither_enable)          */
-                                    /* ([6] = 1 gradient fill mode sel) */
-                                    /* ([7] = 1 AA_enable)              */
-
-    uint8_t  scale_mode;            /* 0 nearst / 1 bilnear / 2 bicubic */
-
-    uint32_t color_key_max;         /* color key max */
-    uint32_t color_key_min;         /* color key min */
-
-    uint32_t fg_color;              /* foreground color */
-    uint32_t bg_color;              /* background color */
-
-    COLOR_FILL gr_color;            /* color fill use gradient */
-
-    line_draw_t line_draw_info;
-
-    FADING fading;
-
-    uint8_t PD_mode;                /* porter duff alpha mode sel */
-
-    uint8_t alpha_global_value;     /* global alpha value */
-
-    uint16_t rop_code;              /* rop2/3/4 code  scan from rop code table*/
-
-    uint8_t bsfilter_flag;          /* [2] 0 blur 1 sharp / [1:0] filter_type*/
-
-    uint8_t palette_mode;           /* (enum) color palatte  0/1bpp, 1/2bpp 2/4bpp 3/8bpp*/
-
-    uint8_t yuv2rgb_mode;           /* (enum) BT.601 MPEG / BT.601 JPEG / BT.709  */
-
-    uint8_t endian_mode;            /* 0/big endian 1/little endian*/
-
-    uint8_t rotate_mode;            /* (enum) rotate mode  */
-                                    /* 0x0,     no rotate  */
-                                    /* 0x1,     rotate     */
-                                    /* 0x2,     x_mirror   */
-                                    /* 0x3,     y_mirror   */
-
-    uint8_t color_fill_mode;        /* 0 solid color / 1 patten color */
-
-    MMU mmu_info;                   /* mmu information */
-
-    uint8_t  alpha_rop_mode;        /* ([0~1] alpha mode)       */
-                                    /* ([2~3] rop   mode)       */
-                                    /* ([4]   zero  mode en)    */
-                                    /* ([5]   dst   alpha mode) */
-
-    uint8_t  src_trans_mode;
-
-    struct sg_table *sg_src;
+} MMU;
+
+
+
+
+typedef struct COLOR_FILL
+{
+    short gr_x_a;
+    short gr_y_a;
+    short gr_x_b;
+    short gr_y_b;
+    short gr_x_g;
+    short gr_y_g;
+    short gr_x_r;
+    short gr_y_r;
+
+    //u8  cp_gr_saturation;
+}
+COLOR_FILL;
+
+typedef struct FADING
+{
+    uint8_t b;
+    uint8_t g;
+    uint8_t r;
+    uint8_t res;
+}
+FADING;
+
+
+typedef struct line_draw_t
+{
+    POINT start_point;              /* LineDraw_start_point                */
+    POINT end_point;                /* LineDraw_end_point                  */
+    uint32_t   color;               /* LineDraw_color                      */
+    uint32_t   flag;                /* (enum) LineDrawing mode sel         */
+    uint32_t   line_width;          /* range 1~16 */
+}
+line_draw_t;
+
+
+
+struct rga_req {
+    uint8_t render_mode;            /* (enum) process mode sel */
+
+    rga_img_info_t src;             /* src image info */
+    rga_img_info_t dst;             /* dst image info */
+    rga_img_info_t pat;             /* patten image info */
+
+    unsigned long rop_mask_addr;         /* rop4 mask addr */
+    unsigned long LUT_addr;              /* LUT addr */
+
+    RECT clip;                      /* dst clip window default value is dst_vir */
+                                    /* value from [0, w-1] / [0, h-1]*/
+
+    int32_t sina;                   /* dst angle  default value 0  16.16 scan from table */
+    int32_t cosa;                   /* dst angle  default value 0  16.16 scan from table */
+
+    uint16_t alpha_rop_flag;        /* alpha rop process flag           */
+                                    /* ([0] = 1 alpha_rop_enable)       */
+                                    /* ([1] = 1 rop enable)             */
+                                    /* ([2] = 1 fading_enable)          */
+                                    /* ([3] = 1 PD_enable)              */
+                                    /* ([4] = 1 alpha cal_mode_sel)     */
+                                    /* ([5] = 1 dither_enable)          */
+                                    /* ([6] = 1 gradient fill mode sel) */
+                                    /* ([7] = 1 AA_enable)              */
+
+    uint8_t  scale_mode;            /* 0 nearst / 1 bilnear / 2 bicubic */
+
+    uint32_t color_key_max;         /* color key max */
+    uint32_t color_key_min;         /* color key min */
+
+    uint32_t fg_color;              /* foreground color */
+    uint32_t bg_color;              /* background color */
+
+    COLOR_FILL gr_color;            /* color fill use gradient */
+
+    line_draw_t line_draw_info;
+
+    FADING fading;
+
+    uint8_t PD_mode;                /* porter duff alpha mode sel */
+
+    uint8_t alpha_global_value;     /* global alpha value */
+
+    uint16_t rop_code;              /* rop2/3/4 code  scan from rop code table*/
+
+    uint8_t bsfilter_flag;          /* [2] 0 blur 1 sharp / [1:0] filter_type*/
+
+    uint8_t palette_mode;           /* (enum) color palatte  0/1bpp, 1/2bpp 2/4bpp 3/8bpp*/
+
+    uint8_t yuv2rgb_mode;           /* (enum) BT.601 MPEG / BT.601 JPEG / BT.709  */
+
+    uint8_t endian_mode;            /* 0/big endian 1/little endian*/
+
+    uint8_t rotate_mode;            /* (enum) rotate mode  */
+                                    /* 0x0,     no rotate  */
+                                    /* 0x1,     rotate     */
+                                    /* 0x2,     x_mirror   */
+                                    /* 0x3,     y_mirror   */
+
+    uint8_t color_fill_mode;        /* 0 solid color / 1 patten color */
+
+    MMU mmu_info;                   /* mmu information */
+
+    uint8_t  alpha_rop_mode;        /* ([0~1] alpha mode)       */
+                                    /* ([2~3] rop   mode)       */
+                                    /* ([4]   zero  mode en)    */
+                                    /* ([5]   dst   alpha mode) */
+
+    uint8_t  src_trans_mode;
+
+    struct sg_table *sg_src;
 	struct sg_table *sg_dst;
 	struct dma_buf_attachment *attach_src;
 	struct dma_buf_attachment *attach_dst;
-};
-
-
-typedef struct TILE_INFO
-{
-    int64_t matrix[4];
-
-    uint16_t tile_x_num;     /* x axis tile num / tile size is 8x8 pixel */
-    uint16_t tile_y_num;     /* y axis tile num */
-
-    int16_t dst_x_tmp;      /* dst pos x = (xstart - xoff) default value 0 */
-    int16_t dst_y_tmp;      /* dst pos y = (ystart - yoff) default value 0 */
-
-    uint16_t tile_w;
-    uint16_t tile_h;
-    int16_t tile_start_x_coor;
-    int16_t tile_start_y_coor;
-    int32_t tile_xoff;
-    int32_t tile_yoff;
-
-    int32_t tile_temp_xstart;
-    int32_t tile_temp_ystart;
-
-    /* src tile incr */
-    int32_t x_dx;
-    int32_t x_dy;
-    int32_t y_dx;
-    int32_t y_dy;
-
-    mdp_img_act dst_ctrl;
-
-}
-TILE_INFO;
-
-struct rga_mmu_buf_t {
-    int32_t front;
-    int32_t back;
-    int32_t size;
-    int32_t curr;
-    unsigned int *buf;
-    unsigned int *buf_virtual;
-
-    struct page **pages;
-};
-
-/**
- * struct for process session which connect to rga
- *
- * @author ZhangShengqin (2012-2-15)
- */
-typedef struct rga_session {
-	/* a linked list of data so we can access them for debugging */
-	struct list_head    list_session;
-	/* a linked list of register data waiting for process */
-	struct list_head    waiting;
-	/* a linked list of register data in processing */
-	struct list_head    running;
-	/* all coommand this thread done */
-    atomic_t            done;
-	wait_queue_head_t   wait;
-	pid_t           pid;
-	atomic_t        task_running;
-    atomic_t        num_done;
-} rga_session;
-
-struct rga_reg {
-    rga_session 		*session;
-	struct list_head	session_link;		/* link to rga service session */
-	struct list_head	status_link;		/* link to register set list */
-	uint32_t  sys_reg[RGA_REG_CTRL_LEN];
-    uint32_t  cmd_reg[RGA_REG_CMD_LEN];
-
-    uint32_t *MMU_base;
-    uint32_t MMU_len;
-    //atomic_t int_enable;
-
-    //struct rga_req      req;
+};
+
+
+typedef struct TILE_INFO
+{
+    int64_t matrix[4];
+
+    uint16_t tile_x_num;     /* x axis tile num / tile size is 8x8 pixel */
+    uint16_t tile_y_num;     /* y axis tile num */
+
+    int16_t dst_x_tmp;      /* dst pos x = (xstart - xoff) default value 0 */
+    int16_t dst_y_tmp;      /* dst pos y = (ystart - yoff) default value 0 */
+
+    uint16_t tile_w;
+    uint16_t tile_h;
+    int16_t tile_start_x_coor;
+    int16_t tile_start_y_coor;
+    int32_t tile_xoff;
+    int32_t tile_yoff;
+
+    int32_t tile_temp_xstart;
+    int32_t tile_temp_ystart;
+
+    /* src tile incr */
+    int32_t x_dx;
+    int32_t x_dy;
+    int32_t y_dx;
+    int32_t y_dy;
+
+    mdp_img_act dst_ctrl;
+
+}
+TILE_INFO;
+
+struct rga_mmu_buf_t {
+    int32_t front;
+    int32_t back;
+    int32_t size;
+    int32_t curr;
+    unsigned int *buf;
+    unsigned int *buf_virtual;
+
+    struct page **pages;
+};
+
+/**
+ * struct for process session which connect to rga
+ *
+ * @author ZhangShengqin (2012-2-15)
+ */
+typedef struct rga_session {
+	/* a linked list of data so we can access them for debugging */
+	struct list_head    list_session;
+	/* a linked list of register data waiting for process */
+	struct list_head    waiting;
+	/* a linked list of register data in processing */
+	struct list_head    running;
+	/* all coommand this thread done */
+    atomic_t            done;
+	wait_queue_head_t   wait;
+	pid_t           pid;
+	atomic_t        task_running;
+    atomic_t        num_done;
+} rga_session;
+
+struct rga_reg {
+    rga_session 		*session;
+	struct list_head	session_link;		/* link to rga service session */
+	struct list_head	status_link;		/* link to register set list */
+	uint32_t  sys_reg[RGA_REG_CTRL_LEN];
+    uint32_t  cmd_reg[RGA_REG_CMD_LEN];
+
+    uint32_t *MMU_base;
+    uint32_t MMU_len;
+    //atomic_t int_enable;
+
+    //struct rga_req      req;
 
 	struct sg_table *sg_src;
 	struct sg_table *sg_dst;
 
 	struct dma_buf_attachment *attach_src;
 	struct dma_buf_attachment *attach_dst;
-};
-
-
-
-typedef struct rga_service_info {
-    struct mutex	lock;
-    struct timer_list	timer;			/* timer for power off */
-    struct list_head	waiting;		/* link to link_reg in struct vpu_reg */
-    struct list_head	running;		/* link to link_reg in struct vpu_reg */
-    struct list_head	done;			/* link to link_reg in struct vpu_reg */
-    struct list_head	session;		/* link to list_session in struct vpu_session */
-    atomic_t		total_running;
-
-    struct rga_reg        *reg;
-
-    uint32_t            cmd_buff[28*8];/* cmd_buff for rga */
-    uint32_t            *pre_scale_buf;
-    unsigned long       *pre_scale_buf_virtual;
+};
+
+
+
+typedef struct rga_service_info {
+    struct mutex	lock;
+    struct timer_list	timer;			/* timer for power off */
+    struct list_head	waiting;		/* link to link_reg in struct vpu_reg */
+    struct list_head	running;		/* link to link_reg in struct vpu_reg */
+    struct list_head	done;			/* link to link_reg in struct vpu_reg */
+    struct list_head	session;		/* link to list_session in struct vpu_session */
+    atomic_t		total_running;
+
+    struct rga_reg        *reg;
+
+    uint32_t            cmd_buff[28*8];/* cmd_buff for rga */
+    uint32_t            *pre_scale_buf;
+    unsigned long       *pre_scale_buf_virtual;
 	atomic_t            int_disable;     /* 0 int enable 1 int disable  */
-    atomic_t            cmd_num;
+    atomic_t            cmd_num;
 	atomic_t src_format_swt;
 	int last_prc_src_format;
 	atomic_t            rga_working;
-    bool                enable;
+    bool                enable;
 	u32 dev_mode;
-
-    //struct rga_req      req[10];
-
-    struct mutex	mutex;	// mutex
-} rga_service_info;
-
-
-
-#if defined(CONFIG_ARCH_RK2928) || defined(CONFIG_ARCH_RK3026) || defined(CONFIG_ARCH_RK312x)
-#define RGA_BASE                 0x1010c000
-#elif defined(CONFIG_ARCH_RK30)
-#define RGA_BASE                 0x10114000
-#endif
-
-//General Registers
-#define RGA_SYS_CTRL             0x000
-#define RGA_CMD_CTRL             0x004
-#define RGA_CMD_ADDR             0x008
-#define RGA_STATUS               0x00c
-#define RGA_INT                  0x010
-#define RGA_AXI_ID               0x014
-#define RGA_MMU_STA_CTRL         0x018
-#define RGA_MMU_STA              0x01c
+
+    //struct rga_req      req[10];
+
+    struct mutex	mutex;	// mutex
+} rga_service_info;
+
+
+
+#if defined(CONFIG_ARCH_RK2928) || defined(CONFIG_ARCH_RK3026) || defined(CONFIG_ARCH_RK312x)
+#define RGA_BASE                 0x1010c000
+#elif defined(CONFIG_ARCH_RK30)
+#define RGA_BASE                 0x10114000
+#endif
+
+//General Registers
+#define RGA_SYS_CTRL             0x000
+#define RGA_CMD_CTRL             0x004
+#define RGA_CMD_ADDR             0x008
+#define RGA_STATUS               0x00c
+#define RGA_INT                  0x010
+#define RGA_AXI_ID               0x014
+#define RGA_MMU_STA_CTRL         0x018
+#define RGA_MMU_STA              0x01c
 #define RGA_VERSION              0x028
-
-//Command code start
-#define RGA_MODE_CTRL            0x100
-
-//Source Image Registers
-#define RGA_SRC_Y_MST            0x104
-#define RGA_SRC_CB_MST           0x108
-#define RGA_MASK_READ_MST        0x108  //repeat
-#define RGA_SRC_CR_MST           0x10c
-#define RGA_SRC_VIR_INFO         0x110
-#define RGA_SRC_ACT_INFO         0x114
-#define RGA_SRC_X_PARA           0x118
-#define RGA_SRC_Y_PARA           0x11c
-#define RGA_SRC_TILE_XINFO       0x120
-#define RGA_SRC_TILE_YINFO       0x124
-#define RGA_SRC_TILE_H_INCR      0x128
-#define RGA_SRC_TILE_V_INCR      0x12c
-#define RGA_SRC_TILE_OFFSETX     0x130
-#define RGA_SRC_TILE_OFFSETY     0x134
-#define RGA_SRC_BG_COLOR         0x138
-#define RGA_SRC_FG_COLOR         0x13c
-#define RGA_LINE_DRAWING_COLOR   0x13c  //repeat
-#define RGA_SRC_TR_COLOR0        0x140
-#define RGA_CP_GR_A              0x140  //repeat
-#define RGA_SRC_TR_COLOR1        0x144
-#define RGA_CP_GR_B              0x144  //repeat
-
-#define RGA_LINE_DRAW            0x148
-#define RGA_PAT_START_POINT      0x148  //repeat
-
-//Destination Image Registers
-#define RGA_DST_MST              0x14c
-#define RGA_LUT_MST              0x14c  //repeat
-#define RGA_PAT_MST              0x14c  //repeat
-#define RGA_LINE_DRAWING_MST     0x14c  //repeat
-
-#define RGA_DST_VIR_INFO         0x150
-
-#define RGA_DST_CTR_INFO         0x154
-#define RGA_LINE_DRAW_XY_INFO    0x154  //repeat
-
-//Alpha/ROP Registers
-#define RGA_ALPHA_CON            0x158
-
-#define RGA_PAT_CON              0x15c
-#define RGA_DST_VIR_WIDTH_PIX    0x15c  //repeat
-
-#define RGA_ROP_CON0             0x160
-#define RGA_CP_GR_G              0x160  //repeat
-#define RGA_PRESCL_CB_MST        0x160  //repeat
-
-#define RGA_ROP_CON1             0x164
-#define RGA_CP_GR_R              0x164  //repeat
-#define RGA_PRESCL_CR_MST        0x164  //repeat
-
-//MMU Register
-#define RGA_FADING_CON           0x168
-#define RGA_MMU_CTRL             0x168  //repeat
-
-#define RGA_MMU_TBL              0x16c  //repeat
-
-#define RGA_YUV_OUT_CFG          0x170
-#define RGA_DST_UV_MST           0x174
-
-
-#define RGA_BLIT_COMPLETE_EVENT 1
-
-long rga_ioctl_kernel(struct rga_req *req);
-
-#endif /*_RK29_IPP_DRIVER_H_*/
+
+//Command code start
+#define RGA_MODE_CTRL            0x100
+
+//Source Image Registers
+#define RGA_SRC_Y_MST            0x104
+#define RGA_SRC_CB_MST           0x108
+#define RGA_MASK_READ_MST        0x108  //repeat
+#define RGA_SRC_CR_MST           0x10c
+#define RGA_SRC_VIR_INFO         0x110
+#define RGA_SRC_ACT_INFO         0x114
+#define RGA_SRC_X_PARA           0x118
+#define RGA_SRC_Y_PARA           0x11c
+#define RGA_SRC_TILE_XINFO       0x120
+#define RGA_SRC_TILE_YINFO       0x124
+#define RGA_SRC_TILE_H_INCR      0x128
+#define RGA_SRC_TILE_V_INCR      0x12c
+#define RGA_SRC_TILE_OFFSETX     0x130
+#define RGA_SRC_TILE_OFFSETY     0x134
+#define RGA_SRC_BG_COLOR         0x138
+#define RGA_SRC_FG_COLOR         0x13c
+#define RGA_LINE_DRAWING_COLOR   0x13c  //repeat
+#define RGA_SRC_TR_COLOR0        0x140
+#define RGA_CP_GR_A              0x140  //repeat
+#define RGA_SRC_TR_COLOR1        0x144
+#define RGA_CP_GR_B              0x144  //repeat
+
+#define RGA_LINE_DRAW            0x148
+#define RGA_PAT_START_POINT      0x148  //repeat
+
+//Destination Image Registers
+#define RGA_DST_MST              0x14c
+#define RGA_LUT_MST              0x14c  //repeat
+#define RGA_PAT_MST              0x14c  //repeat
+#define RGA_LINE_DRAWING_MST     0x14c  //repeat
+
+#define RGA_DST_VIR_INFO         0x150
+
+#define RGA_DST_CTR_INFO         0x154
+#define RGA_LINE_DRAW_XY_INFO    0x154  //repeat
+
+//Alpha/ROP Registers
+#define RGA_ALPHA_CON            0x158
+
+#define RGA_PAT_CON              0x15c
+#define RGA_DST_VIR_WIDTH_PIX    0x15c  //repeat
+
+#define RGA_ROP_CON0             0x160
+#define RGA_CP_GR_G              0x160  //repeat
+#define RGA_PRESCL_CB_MST        0x160  //repeat
+
+#define RGA_ROP_CON1             0x164
+#define RGA_CP_GR_R              0x164  //repeat
+#define RGA_PRESCL_CR_MST        0x164  //repeat
+
+//MMU Register
+#define RGA_FADING_CON           0x168
+#define RGA_MMU_CTRL             0x168  //repeat
+
+#define RGA_MMU_TBL              0x16c  //repeat
+
+#define RGA_YUV_OUT_CFG          0x170
+#define RGA_DST_UV_MST           0x174
+
+
+#define RGA_BLIT_COMPLETE_EVENT 1
+
+long rga_ioctl_kernel(struct rga_req *req);
+
+#endif /*_RK29_IPP_DRIVER_H_*/
diff --git a/drivers/video/rockchip/rga/rga_drv.c b/drivers/video/rockchip/rga/rga_drv.c
index a5d43f90f21b..4cda1908a9c5 100644
--- a/drivers/video/rockchip/rga/rga_drv.c
+++ b/drivers/video/rockchip/rga/rga_drv.c
@@ -1,47 +1,47 @@
-/*
- * Copyright (C) 2012 ROCKCHIP, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#define pr_fmt(fmt) "rga: " fmt
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/platform_device.h>
-#include <linux/sched.h>
-#include <linux/mutex.h>
-#include <linux/err.h>
-#include <linux/clk.h>
-#include <asm/delay.h>
-#include <linux/dma-mapping.h>
-#include <linux/delay.h>
-#include <asm/io.h>
-#include <linux/irq.h>
-#include <linux/interrupt.h>
-//#include <mach/io.h>
-//#include <mach/irqs.h>
-#include <linux/fs.h>
-#include <linux/uaccess.h>
-#include <linux/miscdevice.h>
-#include <linux/poll.h>
-#include <linux/delay.h>
-#include <linux/wait.h>
-#include <linux/syscalls.h>
-#include <linux/timer.h>
-#include <linux/time.h>
-#include <asm/cacheflush.h>
-#include <linux/slab.h>
-#include <linux/fb.h>
-#include <linux/wakelock.h>
+/*
+ * Copyright (C) 2012 ROCKCHIP, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#define pr_fmt(fmt) "rga: " fmt
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/sched.h>
+#include <linux/mutex.h>
+#include <linux/err.h>
+#include <linux/clk.h>
+#include <asm/delay.h>
+#include <linux/dma-mapping.h>
+#include <linux/delay.h>
+#include <asm/io.h>
+#include <linux/irq.h>
+#include <linux/interrupt.h>
+//#include <mach/io.h>
+//#include <mach/irqs.h>
+#include <linux/fs.h>
+#include <linux/uaccess.h>
+#include <linux/miscdevice.h>
+#include <linux/poll.h>
+#include <linux/delay.h>
+#include <linux/wait.h>
+#include <linux/syscalls.h>
+#include <linux/timer.h>
+#include <linux/time.h>
+#include <asm/cacheflush.h>
+#include <linux/slab.h>
+#include <linux/fb.h>
+#include <linux/wakelock.h>
 #include <linux/version.h>
 #include <linux/debugfs.h>
 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 4, 0))
@@ -53,41 +53,41 @@
 #include <linux/rockchip_ion.h>
 #endif
 
-#include "rga.h"
-#include "rga_reg_info.h"
-#include "rga_mmu_info.h"
-#include "RGA_API.h"
-
-#define RGA_TEST_CASE 0
-
-#define RGA_TEST_FLUSH_TIME 0
-#define RGA_INFO_BUS_ERROR 1
-
-#define PRE_SCALE_BUF_SIZE  2048*1024*4
-
-#define RGA_POWER_OFF_DELAY	4*HZ /* 4s */
-#define RGA_TIMEOUT_DELAY	2*HZ /* 2s */
-
-#define RGA_MAJOR		255
-
-#if defined(CONFIG_ARCH_RK2928) || defined(CONFIG_ARCH_RK3026)
-#define RK30_RGA_PHYS		RK2928_RGA_PHYS
-#define RK30_RGA_SIZE		RK2928_RGA_SIZE
-#endif
-#define RGA_RESET_TIMEOUT	1000
-
-/* Driver information */
-#define DRIVER_DESC		"RGA Device Driver"
-#define DRIVER_NAME		"rga"
-
-
-ktime_t rga_start;
-ktime_t rga_end;
-
-rga_session rga_session_global;
-
-long (*rga_ioctl_kernel_p)(struct rga_req *);
-
+#include "rga.h"
+#include "rga_reg_info.h"
+#include "rga_mmu_info.h"
+#include "RGA_API.h"
+
+#define RGA_TEST_CASE 0
+
+#define RGA_TEST_FLUSH_TIME 0
+#define RGA_INFO_BUS_ERROR 1
+
+#define PRE_SCALE_BUF_SIZE  2048*1024*4
+
+#define RGA_POWER_OFF_DELAY	4*HZ /* 4s */
+#define RGA_TIMEOUT_DELAY	2*HZ /* 2s */
+
+#define RGA_MAJOR		255
+
+#if defined(CONFIG_ARCH_RK2928) || defined(CONFIG_ARCH_RK3026)
+#define RK30_RGA_PHYS		RK2928_RGA_PHYS
+#define RK30_RGA_SIZE		RK2928_RGA_SIZE
+#endif
+#define RGA_RESET_TIMEOUT	1000
+
+/* Driver information */
+#define DRIVER_DESC		"RGA Device Driver"
+#define DRIVER_NAME		"rga"
+
+
+ktime_t rga_start;
+ktime_t rga_end;
+
+static rga_session rga_session_global;
+
+long (*rga_ioctl_kernel_p)(struct rga_req *);
+
 #if RGA_DEBUGFS
 unsigned char RGA_TEST_REG;
 unsigned char RGA_TEST_MSG;
@@ -96,36 +96,36 @@ unsigned char RGA_CHECK_MODE;
 unsigned char RGA_NONUSE;
 unsigned char RGA_INT_FLAG;
 #endif
-
-struct rga_drvdata *drvdata;
-rga_service_info rga_service;
-struct rga_mmu_buf_t rga_mmu_buf;
-
-
-#if defined(CONFIG_ION_ROCKCHIP)
-extern struct ion_client *rockchip_ion_client_create(const char * name);
-#endif
-
-static int rga_blit_async(rga_session *session, struct rga_req *req);
-static void rga_del_running_list(void);
-static void rga_del_running_list_timeout(void);
-static void rga_try_set_reg(void);
-
-
-/* Logging */
-#define RGA_DEBUG 1
-#if RGA_DEBUG
-#define DBG(format, args...) printk(KERN_DEBUG "%s: " format, DRIVER_NAME, ## args)
-#define ERR(format, args...) printk(KERN_ERR "%s: " format, DRIVER_NAME, ## args)
-#define WARNING(format, args...) printk(KERN_WARN "%s: " format, DRIVER_NAME, ## args)
-#define INFO(format, args...) printk(KERN_INFO "%s: " format, DRIVER_NAME, ## args)
-#else
-#define DBG(format, args...)
-#define ERR(format, args...)
-#define WARNING(format, args...)
-#define INFO(format, args...)
-#endif
-
+
+struct rga_drvdata *rga_drvdata;
+rga_service_info rga_service;
+struct rga_mmu_buf_t rga_mmu_buf;
+
+
+#if defined(CONFIG_ION_ROCKCHIP)
+extern struct ion_client *rockchip_ion_client_create(const char * name);
+#endif
+
+static int rga_blit_async(rga_session *session, struct rga_req *req);
+static void rga_del_running_list(void);
+static void rga_del_running_list_timeout(void);
+static void rga_try_set_reg(void);
+
+
+/* Logging */
+#define RGA_DEBUG 1
+#if RGA_DEBUG
+#define DBG(format, args...) printk(KERN_DEBUG "%s: " format, DRIVER_NAME, ## args)
+#define ERR(format, args...) printk(KERN_ERR "%s: " format, DRIVER_NAME, ## args)
+#define WARNING(format, args...) printk(KERN_WARN "%s: " format, DRIVER_NAME, ## args)
+#define INFO(format, args...) printk(KERN_INFO "%s: " format, DRIVER_NAME, ## args)
+#else
+#define DBG(format, args...)
+#define ERR(format, args...)
+#define WARNING(format, args...)
+#define INFO(format, args...)
+#endif
+
 #if RGA_DEBUGFS
 static const char *rga_get_cmd_mode_str(u32 cmd)
 {
@@ -408,180 +408,180 @@ static int rga_memory_check(void *vaddr, u32 w, u32 h, u32 format, int fd)
 }
 #endif
 
-static inline void rga_write(u32 b, u32 r)
-{
-	__raw_writel(b, drvdata->rga_base + r);
-}
-
-static inline u32 rga_read(u32 r)
-{
-	return __raw_readl(drvdata->rga_base + r);
-}
-
-static void rga_soft_reset(void)
-{
-	u32 i;
-	u32 reg;
-
-	rga_write(1, RGA_SYS_CTRL); //RGA_SYS_CTRL
-
-	for(i = 0; i < RGA_RESET_TIMEOUT; i++)
-	{
-		reg = rga_read(RGA_SYS_CTRL) & 1; //RGA_SYS_CTRL
-
-		if(reg == 0)
-			break;
-
-		udelay(1);
-	}
-
-	if(i == RGA_RESET_TIMEOUT)
-		ERR("soft reset timeout.\n");
-}
-
-static void rga_dump(void)
-{
-	int running;
-    struct rga_reg *reg, *reg_tmp;
-    rga_session *session, *session_tmp;
-
-	running = atomic_read(&rga_service.total_running);
-	printk("rga total_running %d\n", running);
-
-    #if 0
-
-    /* Dump waiting list info */
-    if (!list_empty(&rga_service.waiting))
-    {
-        list_head	*next;
-
-        next = &rga_service.waiting;
-
-        printk("rga_service dump waiting list\n");
-
-        do
-        {
-            reg = list_entry(next->next, struct rga_reg, status_link);
-            running = atomic_read(&reg->session->task_running);
-            num_done = atomic_read(&reg->session->num_done);
-            printk("rga session pid %d, done %d, running %d\n", reg->session->pid, num_done, running);
-            next = next->next;
-        }
-        while(!list_empty(next));
-    }
-
-    /* Dump running list info */
-    if (!list_empty(&rga_service.running))
-    {
-        printk("rga_service dump running list\n");
-
-        list_head	*next;
-
-        next = &rga_service.running;
-        do
-        {
-            reg = list_entry(next->next, struct rga_reg, status_link);
-            running = atomic_read(&reg->session->task_running);
-            num_done = atomic_read(&reg->session->num_done);
-            printk("rga session pid %d, done %d, running %d:\n", reg->session->pid, num_done, running);
-            next = next->next;
-        }
-        while(!list_empty(next));
-    }
-    #endif
-
-	list_for_each_entry_safe(session, session_tmp, &rga_service.session, list_session)
-    {
-		printk("session pid %d:\n", session->pid);
-		running = atomic_read(&session->task_running);
-		printk("task_running %d\n", running);
-		list_for_each_entry_safe(reg, reg_tmp, &session->waiting, session_link)
-        {
+static inline void rga_write(u32 b, u32 r)
+{
+	__raw_writel(b, rga_drvdata->rga_base + r);
+}
+
+static inline u32 rga_read(u32 r)
+{
+	return __raw_readl(rga_drvdata->rga_base + r);
+}
+
+static void rga_soft_reset(void)
+{
+	u32 i;
+	u32 reg;
+
+	rga_write(1, RGA_SYS_CTRL); //RGA_SYS_CTRL
+
+	for(i = 0; i < RGA_RESET_TIMEOUT; i++)
+	{
+		reg = rga_read(RGA_SYS_CTRL) & 1; //RGA_SYS_CTRL
+
+		if(reg == 0)
+			break;
+
+		udelay(1);
+	}
+
+	if(i == RGA_RESET_TIMEOUT)
+		ERR("soft reset timeout.\n");
+}
+
+static void rga_dump(void)
+{
+	int running;
+    struct rga_reg *reg, *reg_tmp;
+    rga_session *session, *session_tmp;
+
+	running = atomic_read(&rga_service.total_running);
+	printk("rga total_running %d\n", running);
+
+    #if 0
+
+    /* Dump waiting list info */
+    if (!list_empty(&rga_service.waiting))
+    {
+        list_head	*next;
+
+        next = &rga_service.waiting;
+
+        printk("rga_service dump waiting list\n");
+
+        do
+        {
+            reg = list_entry(next->next, struct rga_reg, status_link);
+            running = atomic_read(&reg->session->task_running);
+            num_done = atomic_read(&reg->session->num_done);
+            printk("rga session pid %d, done %d, running %d\n", reg->session->pid, num_done, running);
+            next = next->next;
+        }
+        while(!list_empty(next));
+    }
+
+    /* Dump running list info */
+    if (!list_empty(&rga_service.running))
+    {
+        printk("rga_service dump running list\n");
+
+        list_head	*next;
+
+        next = &rga_service.running;
+        do
+        {
+            reg = list_entry(next->next, struct rga_reg, status_link);
+            running = atomic_read(&reg->session->task_running);
+            num_done = atomic_read(&reg->session->num_done);
+            printk("rga session pid %d, done %d, running %d:\n", reg->session->pid, num_done, running);
+            next = next->next;
+        }
+        while(!list_empty(next));
+    }
+    #endif
+
+	list_for_each_entry_safe(session, session_tmp, &rga_service.session, list_session)
+    {
+		printk("session pid %d:\n", session->pid);
+		running = atomic_read(&session->task_running);
+		printk("task_running %d\n", running);
+		list_for_each_entry_safe(reg, reg_tmp, &session->waiting, session_link)
+        {
 			printk("waiting register set 0x %.lu\n", (unsigned long)reg);
-		}
-		list_for_each_entry_safe(reg, reg_tmp, &session->running, session_link)
-        {
+		}
+		list_for_each_entry_safe(reg, reg_tmp, &session->running, session_link)
+        {
 			printk("running register set 0x %.lu\n", (unsigned long)reg);
-		}
-	}
-}
-
-static inline void rga_queue_power_off_work(void)
-{
+		}
+	}
+}
+
+static inline void rga_queue_power_off_work(void)
+{
 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 4, 0))
-	queue_delayed_work(system_wq, &drvdata->power_off_work, RGA_POWER_OFF_DELAY);
+	queue_delayed_work(system_wq, &rga_drvdata->power_off_work, RGA_POWER_OFF_DELAY);
 #else
-	queue_delayed_work(system_nrt_wq, &drvdata->power_off_work, RGA_POWER_OFF_DELAY);
+	queue_delayed_work(system_nrt_wq, &rga_drvdata->power_off_work, RGA_POWER_OFF_DELAY);
 #endif
-}
-
-/* Caller must hold rga_service.lock */
-static void rga_power_on(void)
-{
-	static ktime_t last;
-	ktime_t now = ktime_get();
-
-	if (ktime_to_ns(ktime_sub(now, last)) > NSEC_PER_SEC) {
-		cancel_delayed_work_sync(&drvdata->power_off_work);
-		rga_queue_power_off_work();
-		last = now;
-	}
-	if (rga_service.enable)
-		return;
-
+}
+
+/* Caller must hold rga_service.lock */
+static void rga_power_on(void)
+{
+	static ktime_t last;
+	ktime_t now = ktime_get();
+
+	if (ktime_to_ns(ktime_sub(now, last)) > NSEC_PER_SEC) {
+		cancel_delayed_work_sync(&rga_drvdata->power_off_work);
+		rga_queue_power_off_work();
+		last = now;
+	}
+	if (rga_service.enable)
+		return;
+
 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 4, 0))
-	clk_prepare_enable(drvdata->aclk_rga);
-	clk_prepare_enable(drvdata->hclk_rga);
-	pm_runtime_get_sync(drvdata->dev);
+	clk_prepare_enable(rga_drvdata->aclk_rga);
+	clk_prepare_enable(rga_drvdata->hclk_rga);
+	pm_runtime_get_sync(rga_drvdata->dev);
 #else
-	clk_prepare_enable(drvdata->aclk_rga);
-	clk_prepare_enable(drvdata->hclk_rga);
-	if (drvdata->pd_rga)
-		clk_prepare_enable(drvdata->pd_rga);
+	clk_prepare_enable(rga_drvdata->aclk_rga);
+	clk_prepare_enable(rga_drvdata->hclk_rga);
+	if (rga_drvdata->pd_rga)
+		clk_prepare_enable(rga_drvdata->pd_rga);
 #endif
 
-	wake_lock(&drvdata->wake_lock);
-	rga_service.enable = true;
-}
+	wake_lock(&rga_drvdata->wake_lock);
+	rga_service.enable = true;
+}
+
+/* Caller must hold rga_service.lock */
+static void rga_power_off(void)
+{
+	int total_running;
+
+	if (!rga_service.enable) {
+		return;
+	}
+
+	total_running = atomic_read(&rga_service.total_running);
+	if (total_running) {
+		pr_err("power off when %d task running!!\n", total_running);
+		mdelay(50);
+		pr_err("delay 50 ms for running task\n");
+		rga_dump();
+	}
 
-/* Caller must hold rga_service.lock */
-static void rga_power_off(void)
-{
-	int total_running;
-
-	if (!rga_service.enable) {
-		return;
-	}
-
-	total_running = atomic_read(&rga_service.total_running);
-	if (total_running) {
-		pr_err("power off when %d task running!!\n", total_running);
-		mdelay(50);
-		pr_err("delay 50 ms for running task\n");
-		rga_dump();
-	}
-
 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 4, 0))
-	pm_runtime_put(drvdata->dev);
-	clk_disable_unprepare(drvdata->aclk_rga);
-	clk_disable_unprepare(drvdata->hclk_rga);
+	pm_runtime_put(rga_drvdata->dev);
+	clk_disable_unprepare(rga_drvdata->aclk_rga);
+	clk_disable_unprepare(rga_drvdata->hclk_rga);
 #else
-	if (drvdata->pd_rga)
-		clk_disable_unprepare(drvdata->pd_rga);
-	clk_disable_unprepare(drvdata->aclk_rga);
-	clk_disable_unprepare(drvdata->hclk_rga);
+	if (rga_drvdata->pd_rga)
+		clk_disable_unprepare(rga_drvdata->pd_rga);
+	clk_disable_unprepare(rga_drvdata->aclk_rga);
+	clk_disable_unprepare(rga_drvdata->hclk_rga);
 #endif
-	wake_unlock(&drvdata->wake_lock);
-	rga_service.enable = false;
-}
-
-static void rga_power_off_work(struct work_struct *work)
-{
-	if (mutex_trylock(&rga_service.lock)) {
-		rga_power_off();
-		mutex_unlock(&rga_service.lock);
-	} else {
-		/* Come back later if the device is busy... */
+	wake_unlock(&rga_drvdata->wake_lock);
+	rga_service.enable = false;
+}
+
+static void rga_power_off_work(struct work_struct *work)
+{
+	if (mutex_trylock(&rga_service.lock)) {
+		rga_power_off();
+		mutex_unlock(&rga_service.lock);
+	} else {
+		/* Come back later if the device is busy... */
 
 		rga_queue_power_off_work();
 	}
@@ -628,7 +628,7 @@ static int rga_flush(rga_session *session, unsigned long arg)
 
 static int rga_get_result(rga_session *session, unsigned long arg)
 {
-	//printk("rga_get_result %d\n",drvdata->rga_result);
+	//printk("rga_get_result %d\n",rga_drvdata->rga_result);
 
     int ret = 0;
 
@@ -715,7 +715,7 @@ static void rga_copy_reg(struct rga_reg *reg, uint32_t offset)
     cmd_buf = (uint32_t *)rga_service.cmd_buff + offset*32;
     reg_p = (uint32_t *)reg->cmd_reg;
 
-    for(i=0; i<32; i++)
+    for(i=0; i<32; i++)
         cmd_buf[i] = reg_p[i];
 }
 
@@ -853,7 +853,7 @@ static void rga_try_set_reg(void)
             rga_write(rga_read(RGA_INT)|(0x1<<10)|(0x1<<8), RGA_INT);
 
 #if RGA_DEBUGFS
-	if (RGA_TEST_REG)
+	if (RGA_TEST_TIME)
 		rga_start = ktime_get();
 #endif
 
@@ -1010,7 +1010,7 @@ static int rga_convert_dma_buf(struct rga_req *req)
 	dst_offset = req->line_draw_info.line_width;
 
 	if (req->src.yrgb_addr) {
-		hdl = ion_import_dma_buf(drvdata->ion_client, req->src.yrgb_addr);
+		hdl = ion_import_dma_buf(rga_drvdata->ion_client, req->src.yrgb_addr);
 		if (IS_ERR(hdl)) {
 		ret = PTR_ERR(hdl);
 		pr_err("RGA ERROR ion buf handle\n");
@@ -1025,26 +1025,26 @@ static int rga_convert_dma_buf(struct rga_req *req)
 
 #if RGA_DEBUGFS
 	if (RGA_CHECK_MODE) {
-		vaddr = ion_map_kernel(drvdata->ion_client, hdl);
+		vaddr = ion_map_kernel(rga_drvdata->ion_client, hdl);
 		if (vaddr)
 			rga_memory_check(vaddr, req->src.vir_h, req->src.vir_w,
 					req->src.format, req->src.yrgb_addr);
-		ion_unmap_kernel(drvdata->ion_client, hdl);
+		ion_unmap_kernel(rga_drvdata->ion_client, hdl);
 	}
 #endif
         if ((req->mmu_info.mmu_flag >> 8) & 1) {
-            req->sg_src = ion_sg_table(drvdata->ion_client, hdl);
+            req->sg_src = ion_sg_table(rga_drvdata->ion_client, hdl);
             req->src.yrgb_addr = req->src.uv_addr;
             req->src.uv_addr = req->src.yrgb_addr + (req->src.vir_w * req->src.vir_h);
             req->src.v_addr = req->src.uv_addr + (req->src.vir_w * req->src.vir_h)/4;
         }
         else {
-            ion_phys(drvdata->ion_client, hdl, &phy_addr, &len);
+            ion_phys(rga_drvdata->ion_client, hdl, &phy_addr, &len);
             req->src.yrgb_addr = phy_addr + src_offset;
             req->src.uv_addr = req->src.yrgb_addr + (req->src.vir_w * req->src.vir_h);
             req->src.v_addr = req->src.uv_addr + (req->src.vir_w * req->src.vir_h)/4;
         }
-        ion_free(drvdata->ion_client, hdl);
+        ion_free(rga_drvdata->ion_client, hdl);
     }
     else {
         req->src.yrgb_addr = req->src.uv_addr;
@@ -1053,7 +1053,7 @@ static int rga_convert_dma_buf(struct rga_req *req)
     }
 
     if(req->dst.yrgb_addr) {
-        hdl = ion_import_dma_buf(drvdata->ion_client, req->dst.yrgb_addr);
+        hdl = ion_import_dma_buf(rga_drvdata->ion_client, req->dst.yrgb_addr);
         if (IS_ERR(hdl)) {
             ret = PTR_ERR(hdl);
             printk("RGA2 ERROR ion buf handle\n");
@@ -1068,26 +1068,26 @@ static int rga_convert_dma_buf(struct rga_req *req)
 
 #if RGA_DEBUGFS
 	if (RGA_CHECK_MODE) {
-		vaddr = ion_map_kernel(drvdata->ion_client, hdl);
+		vaddr = ion_map_kernel(rga_drvdata->ion_client, hdl);
 		if (vaddr)
 			rga_memory_check(vaddr, req->src.vir_h, req->src.vir_w,
 				 req->src.format, req->src.yrgb_addr);
-		ion_unmap_kernel(drvdata->ion_client, hdl);
+		ion_unmap_kernel(rga_drvdata->ion_client, hdl);
 	}
 #endif
         if ((req->mmu_info.mmu_flag >> 10) & 1) {
-            req->sg_dst = ion_sg_table(drvdata->ion_client, hdl);
+            req->sg_dst = ion_sg_table(rga_drvdata->ion_client, hdl);
             req->dst.yrgb_addr = req->dst.uv_addr;
             req->dst.uv_addr = req->dst.yrgb_addr + (req->dst.vir_w * req->dst.vir_h);
             req->dst.v_addr = req->dst.uv_addr + (req->dst.vir_w * req->dst.vir_h)/4;
         }
         else {
-            ion_phys(drvdata->ion_client, hdl, &phy_addr, &len);
+            ion_phys(rga_drvdata->ion_client, hdl, &phy_addr, &len);
             req->dst.yrgb_addr = phy_addr + dst_offset;
             req->dst.uv_addr = req->dst.yrgb_addr + (req->dst.vir_w * req->dst.vir_h);
             req->dst.v_addr = req->dst.uv_addr + (req->dst.vir_w * req->dst.vir_h)/4;
         }
-        ion_free(drvdata->ion_client, hdl);
+        ion_free(rga_drvdata->ion_client, hdl);
     }
     else {
         req->dst.yrgb_addr = req->dst.uv_addr;
@@ -1114,7 +1114,7 @@ static int rga_get_img_info(rga_img_info_t *img,
 	int ret = 0;
 	void *vaddr = NULL;
 
-	rga_dev = drvdata->dev;
+	rga_dev = rga_drvdata->dev;
 	yrgb_addr = (int)img->yrgb_addr;
 	vir_w = img->vir_w;
 	vir_h = img->vir_h;
@@ -1566,7 +1566,7 @@ static int rga_blit_sync(rga_session *session, struct rga_req *req)
 	if (RGA_TEST_TIME) {
 		rga_end = ktime_get();
 		rga_end = ktime_sub(rga_end, rga_start);
-		DBG("sync one cmd end time %d\n", (int)ktime_to_us(rga_end));
+		DBG("sync one cmd end time %d us\n", (int)ktime_to_us(rga_end));
 	}
 #endif
 
@@ -1634,21 +1634,21 @@ static long rga_ioctl(struct file *file, uint32_t cmd, unsigned long arg)
             ret = rga_get_result(session, arg);
             break;
         case RGA_GET_VERSION:
-		if (!drvdata->version) {
-			drvdata->version = kzalloc(16, GFP_KERNEL);
-			if (!drvdata->version) {
+		if (!rga_drvdata->version) {
+			rga_drvdata->version = kzalloc(16, GFP_KERNEL);
+			if (!rga_drvdata->version) {
 				ret = -ENOMEM;
 				break;
 			}
 			rga_power_on();
 			udelay(1);
 			if (rga_read(RGA_VERSION) == 0x02018632)
-				snprintf(drvdata->version, 16, "1.6");
+				snprintf(rga_drvdata->version, 16, "1.6");
 			else
-				snprintf(drvdata->version, 16, "1.003");
+				snprintf(rga_drvdata->version, 16, "1.003");
 		}
 
-			ret = copy_to_user((void *)arg, drvdata->version, 16);
+			ret = copy_to_user((void *)arg, rga_drvdata->version, 16);
             break;
 		default:
 			ERR("unknown ioctl cmd!\n");
@@ -1740,7 +1740,6 @@ static int rga_release(struct inode *inode, struct file *file)
     {
 		pr_err("rga_service session %d still has %d task running when closing\n", session->pid, task_running);
 		msleep(100);
-        /*ͬ²½*/
 	}
 
 	wake_up(&session->wait);
@@ -1868,7 +1867,7 @@ static int rga_drv_probe(struct platform_device *pdev)
 
 	platform_set_drvdata(pdev, data);
 	data->dev = &pdev->dev;
-	drvdata = data;
+	rga_drvdata = data;
 
     #if defined(CONFIG_ION_ROCKCHIP)
 	data->ion_client = rockchip_ion_client_create("rga");
@@ -2070,7 +2069,7 @@ void rga_slt(void)
 	unsigned int *pstd;
 	unsigned int *pnow;
 
-	data = drvdata;
+	data = rga_drvdata;
 	srcW = 1280;
 	srcH = 720;
 	dstW = 1280;
@@ -2272,279 +2271,279 @@ void rga_slt(void)
 }
 #endif
 #endif
-
-void rga_test_0(void);
-void rga_test_1(void);
-
-static int __init rga_init(void)
-{
-	int ret;
-    uint32_t *mmu_buf;
-    unsigned long *mmu_buf_virtual;
-    uint32_t i;
-    uint32_t *buf_p;
+
+void rga_test_0(void);
+void rga_test_1(void);
+
+static int __init rga_init(void)
+{
+	int ret;
+    uint32_t *mmu_buf;
+    unsigned long *mmu_buf_virtual;
+    uint32_t i;
+    uint32_t *buf_p;
     uint32_t *buf;
 
-    /* malloc pre scale mid buf mmu table */
-    mmu_buf = kzalloc(1024*8, GFP_KERNEL);
-    mmu_buf_virtual = kzalloc(1024*2*sizeof(unsigned long), GFP_KERNEL);
-    if(mmu_buf == NULL) {
-        printk(KERN_ERR "RGA get Pre Scale buff failed. \n");
-        return -1;
-    }
-	if (mmu_buf_virtual == NULL) {
-		return -1;
-	}
-
-    /* malloc 4 M buf */
-    for(i=0; i<1024; i++) {
-        buf_p = (uint32_t *)__get_free_page(GFP_KERNEL|__GFP_ZERO);
-        if(buf_p == NULL) {
-            printk(KERN_ERR "RGA init pre scale buf falied\n");
-            return -ENOMEM;
-        }
-        mmu_buf[i] = virt_to_phys((void *)((unsigned long)buf_p));
-        mmu_buf_virtual[i] = (unsigned long)buf_p;
-    }
-
-    rga_service.pre_scale_buf = (uint32_t *)mmu_buf;
-    rga_service.pre_scale_buf_virtual = (unsigned long *)mmu_buf_virtual;
-
-    buf_p = kmalloc(1024*256, GFP_KERNEL);
-    rga_mmu_buf.buf_virtual = buf_p;
+    /* malloc pre scale mid buf mmu table */
+    mmu_buf = kzalloc(1024*8, GFP_KERNEL);
+    mmu_buf_virtual = kzalloc(1024*2*sizeof(unsigned long), GFP_KERNEL);
+    if(mmu_buf == NULL) {
+        printk(KERN_ERR "RGA get Pre Scale buff failed. \n");
+        return -1;
+    }
+	if (mmu_buf_virtual == NULL) {
+		return -1;
+	}
+
+    /* malloc 4 M buf */
+    for(i=0; i<1024; i++) {
+        buf_p = (uint32_t *)__get_free_page(GFP_KERNEL|__GFP_ZERO);
+        if(buf_p == NULL) {
+            printk(KERN_ERR "RGA init pre scale buf falied\n");
+            return -ENOMEM;
+        }
+        mmu_buf[i] = virt_to_phys((void *)((unsigned long)buf_p));
+        mmu_buf_virtual[i] = (unsigned long)buf_p;
+    }
+
+    rga_service.pre_scale_buf = (uint32_t *)mmu_buf;
+    rga_service.pre_scale_buf_virtual = (unsigned long *)mmu_buf_virtual;
+
+    buf_p = kmalloc(1024*256, GFP_KERNEL);
+    rga_mmu_buf.buf_virtual = buf_p;
 #if (defined(CONFIG_ARM) && defined(CONFIG_ARM_LPAE))
     buf = (uint32_t *)(uint32_t)virt_to_phys((void *)((unsigned long)buf_p));
 #else
     buf = (uint32_t *)virt_to_phys((void *)((unsigned long)buf_p));
 #endif
     rga_mmu_buf.buf = buf;
-    rga_mmu_buf.front = 0;
-    rga_mmu_buf.back = 64*1024;
-    rga_mmu_buf.size = 64*1024;
-
-    rga_mmu_buf.pages = kmalloc((32768)* sizeof(struct page *), GFP_KERNEL);
-
-	if ((ret = platform_driver_register(&rga_driver)) != 0)
-	{
-        printk(KERN_ERR "Platform device register failed (%d).\n", ret);
-			return ret;
-	}
-
-    {
-        rga_session_global.pid = 0x0000ffff;
-        INIT_LIST_HEAD(&rga_session_global.waiting);
-        INIT_LIST_HEAD(&rga_session_global.running);
-        INIT_LIST_HEAD(&rga_session_global.list_session);
-
-        INIT_LIST_HEAD(&rga_service.waiting);
-	    INIT_LIST_HEAD(&rga_service.running);
-	    INIT_LIST_HEAD(&rga_service.done);
-	    INIT_LIST_HEAD(&rga_service.session);
-
-        init_waitqueue_head(&rga_session_global.wait);
-        //mutex_lock(&rga_service.lock);
-        list_add_tail(&rga_session_global.list_session, &rga_service.session);
-        //mutex_unlock(&rga_service.lock);
-        atomic_set(&rga_session_global.task_running, 0);
-        atomic_set(&rga_session_global.num_done, 0);
-    }
-
+    rga_mmu_buf.front = 0;
+    rga_mmu_buf.back = 64*1024;
+    rga_mmu_buf.size = 64*1024;
+
+    rga_mmu_buf.pages = kmalloc((32768)* sizeof(struct page *), GFP_KERNEL);
+
+	if ((ret = platform_driver_register(&rga_driver)) != 0)
+	{
+        printk(KERN_ERR "Platform device register failed (%d).\n", ret);
+			return ret;
+	}
+
+    {
+        rga_session_global.pid = 0x0000ffff;
+        INIT_LIST_HEAD(&rga_session_global.waiting);
+        INIT_LIST_HEAD(&rga_session_global.running);
+        INIT_LIST_HEAD(&rga_session_global.list_session);
+
+        INIT_LIST_HEAD(&rga_service.waiting);
+	    INIT_LIST_HEAD(&rga_service.running);
+	    INIT_LIST_HEAD(&rga_service.done);
+	    INIT_LIST_HEAD(&rga_service.session);
+
+        init_waitqueue_head(&rga_session_global.wait);
+        //mutex_lock(&rga_service.lock);
+        list_add_tail(&rga_session_global.list_session, &rga_service.session);
+        //mutex_unlock(&rga_service.lock);
+        atomic_set(&rga_session_global.task_running, 0);
+        atomic_set(&rga_session_global.num_done, 0);
+    }
+
     #if RGA_TEST_CASE
 	rga_test_0();
 #endif
 #if RGA_DEBUGFS
 	rga_debugfs_add();
 #endif
-
-	INFO("Module initialized.\n");
-
-	return 0;
-}
-
-static void __exit rga_exit(void)
-{
-    uint32_t i;
-
-    rga_power_off();
-
-    for(i=0; i<1024; i++)
-    {
-        if((unsigned long)rga_service.pre_scale_buf_virtual[i])
-        {
-            __free_page((void *)rga_service.pre_scale_buf_virtual[i]);
-        }
-    }
-
-    if(rga_service.pre_scale_buf != NULL) {
-        kfree((uint8_t *)rga_service.pre_scale_buf);
-    }
-
+
+	INFO("RGA Module initialized.\n");
+
+	return 0;
+}
+
+static void __exit rga_exit(void)
+{
+    uint32_t i;
+
+    rga_power_off();
+
+    for(i=0; i<1024; i++)
+    {
+        if((unsigned long)rga_service.pre_scale_buf_virtual[i])
+        {
+            __free_page((void *)rga_service.pre_scale_buf_virtual[i]);
+        }
+    }
+
+    if(rga_service.pre_scale_buf != NULL) {
+        kfree((uint8_t *)rga_service.pre_scale_buf);
+    }
+
 	kfree(rga_mmu_buf.buf_virtual);
 
 	kfree(rga_mmu_buf.pages);
 
-	platform_driver_unregister(&rga_driver);
-}
+	platform_driver_unregister(&rga_driver);
+}
 
 #if RGA_TEST_CASE
 
-extern struct fb_info * rk_get_fb(int fb_id);
-EXPORT_SYMBOL(rk_get_fb);
-
-extern void rk_direct_fb_show(struct fb_info * fbi);
-EXPORT_SYMBOL(rk_direct_fb_show);
-
-unsigned int src_buf[1920*1080];
-unsigned int dst_buf[1920*1080];
-//unsigned int tmp_buf[1920*1080 * 2];
-
-void rga_test_0(void)
-{
-    struct rga_req req;
-    rga_session session;
-    unsigned int *src, *dst;
-    uint32_t i, j;
-    uint8_t *p;
-    uint8_t t;
-    uint32_t *dst0, *dst1, *dst2;
-
-    struct fb_info *fb;
-
-    session.pid	= current->pid;
-	INIT_LIST_HEAD(&session.waiting);
-	INIT_LIST_HEAD(&session.running);
-	INIT_LIST_HEAD(&session.list_session);
-	init_waitqueue_head(&session.wait);
-	/* no need to protect */
-	list_add_tail(&session.list_session, &rga_service.session);
-	atomic_set(&session.task_running, 0);
-    atomic_set(&session.num_done, 0);
-	//file->private_data = (void *)session;
-
-    fb = rk_get_fb(0);
-
-    memset(&req, 0, sizeof(struct rga_req));
-    src = src_buf;
-    dst = dst_buf;
-
-    memset(src_buf, 0x80, 1024*600*4);
-
-    dmac_flush_range(&src_buf[0], &src_buf[1024*600]);
-    outer_flush_range(virt_to_phys(&src_buf[0]),virt_to_phys(&src_buf[1024*600]));
-
-
-    #if 0
-    memset(src_buf, 0x80, 800*480*4);
-    memset(dst_buf, 0xcc, 800*480*4);
-
-    dmac_flush_range(&dst_buf[0], &dst_buf[800*480]);
-    outer_flush_range(virt_to_phys(&dst_buf[0]),virt_to_phys(&dst_buf[800*480]));
-    #endif
-
-    dst0 = &dst_buf[0];
-    //dst1 = &dst_buf[1280*800*4];
-    //dst2 = &dst_buf[1280*800*4*2];
-
-    i = j = 0;
-
-    printk("\n********************************\n");
-    printk("************ RGA_TEST ************\n");
-    printk("********************************\n\n");
-
-    req.src.act_w = 1024;
-    req.src.act_h = 600;
-
-    req.src.vir_w = 1024;
-    req.src.vir_h = 600;
-    req.src.yrgb_addr = (uint32_t)virt_to_phys(src);
-    req.src.uv_addr = (uint32_t)(req.src.yrgb_addr + 1080*1920);
-    req.src.v_addr = (uint32_t)virt_to_phys(src);
-    req.src.format = RK_FORMAT_RGBA_8888;
-
-    req.dst.act_w = 600;
-    req.dst.act_h = 352;
-
-    req.dst.vir_w = 1280;
-    req.dst.vir_h = 800;
-    req.dst.x_offset = 600;
-    req.dst.y_offset = 0;
-
-    dst = dst0;
-
-    req.dst.yrgb_addr = ((uint32_t)virt_to_phys(dst));
-
-    //req.dst.format = RK_FORMAT_RGB_565;
-
-    req.clip.xmin = 0;
-    req.clip.xmax = 1279;
-    req.clip.ymin = 0;
-    req.clip.ymax = 799;
-
-    //req.render_mode = color_fill_mode;
-    //req.fg_color = 0x80ffffff;
-
-    req.rotate_mode = 1;
-    //req.scale_mode = 2;
-
-    //req.alpha_rop_flag = 0;
-    //req.alpha_rop_mode = 0x19;
-    //req.PD_mode = 3;
-
-    req.sina = 65536;
-    req.cosa = 0;
-
-    //req.mmu_info.mmu_flag = 0x21;
-    //req.mmu_info.mmu_en = 1;
-
-    //printk("src = %.8x\n", req.src.yrgb_addr);
-    //printk("src = %.8x\n", req.src.uv_addr);
-    //printk("dst = %.8x\n", req.dst.yrgb_addr);
-
-
-    rga_blit_sync(&session, &req);
-
-    #if 1
-    fb->var.bits_per_pixel = 32;
-
-    fb->var.xres = 1280;
-    fb->var.yres = 800;
-
-    fb->var.red.length = 8;
-    fb->var.red.offset = 0;
-    fb->var.red.msb_right = 0;
-
-    fb->var.green.length = 8;
-    fb->var.green.offset = 8;
-    fb->var.green.msb_right = 0;
-
-    fb->var.blue.length = 8;
-
-    fb->var.blue.offset = 16;
-    fb->var.blue.msb_right = 0;
-
-    fb->var.transp.length = 8;
-    fb->var.transp.offset = 24;
-    fb->var.transp.msb_right = 0;
-
-    fb->var.nonstd &= (~0xff);
-    fb->var.nonstd |= 1;
-
-    fb->fix.smem_start = virt_to_phys(dst);
-
-    rk_direct_fb_show(fb);
-    #endif
-
-}
-
-#endif
+extern struct fb_info * rk_get_fb(int fb_id);
+EXPORT_SYMBOL(rk_get_fb);
+
+extern void rk_direct_fb_show(struct fb_info * fbi);
+EXPORT_SYMBOL(rk_direct_fb_show);
+
+unsigned int src_buf[1920*1080];
+unsigned int dst_buf[1920*1080];
+//unsigned int tmp_buf[1920*1080 * 2];
+
+void rga_test_0(void)
+{
+    struct rga_req req;
+    rga_session session;
+    unsigned int *src, *dst;
+    uint32_t i, j;
+    uint8_t *p;
+    uint8_t t;
+    uint32_t *dst0, *dst1, *dst2;
+
+    struct fb_info *fb;
+
+    session.pid	= current->pid;
+	INIT_LIST_HEAD(&session.waiting);
+	INIT_LIST_HEAD(&session.running);
+	INIT_LIST_HEAD(&session.list_session);
+	init_waitqueue_head(&session.wait);
+	/* no need to protect */
+	list_add_tail(&session.list_session, &rga_service.session);
+	atomic_set(&session.task_running, 0);
+    atomic_set(&session.num_done, 0);
+	//file->private_data = (void *)session;
+
+    fb = rk_get_fb(0);
+
+    memset(&req, 0, sizeof(struct rga_req));
+    src = src_buf;
+    dst = dst_buf;
+
+    memset(src_buf, 0x80, 1024*600*4);
+
+    dmac_flush_range(&src_buf[0], &src_buf[1024*600]);
+    outer_flush_range(virt_to_phys(&src_buf[0]),virt_to_phys(&src_buf[1024*600]));
+
+
+    #if 0
+    memset(src_buf, 0x80, 800*480*4);
+    memset(dst_buf, 0xcc, 800*480*4);
+
+    dmac_flush_range(&dst_buf[0], &dst_buf[800*480]);
+    outer_flush_range(virt_to_phys(&dst_buf[0]),virt_to_phys(&dst_buf[800*480]));
+    #endif
+
+    dst0 = &dst_buf[0];
+    //dst1 = &dst_buf[1280*800*4];
+    //dst2 = &dst_buf[1280*800*4*2];
+
+    i = j = 0;
+
+    printk("\n********************************\n");
+    printk("************ RGA_TEST ************\n");
+    printk("********************************\n\n");
+
+    req.src.act_w = 1024;
+    req.src.act_h = 600;
+
+    req.src.vir_w = 1024;
+    req.src.vir_h = 600;
+    req.src.yrgb_addr = (uint32_t)virt_to_phys(src);
+    req.src.uv_addr = (uint32_t)(req.src.yrgb_addr + 1080*1920);
+    req.src.v_addr = (uint32_t)virt_to_phys(src);
+    req.src.format = RK_FORMAT_RGBA_8888;
+
+    req.dst.act_w = 600;
+    req.dst.act_h = 352;
+
+    req.dst.vir_w = 1280;
+    req.dst.vir_h = 800;
+    req.dst.x_offset = 600;
+    req.dst.y_offset = 0;
+
+    dst = dst0;
+
+    req.dst.yrgb_addr = ((uint32_t)virt_to_phys(dst));
+
+    //req.dst.format = RK_FORMAT_RGB_565;
+
+    req.clip.xmin = 0;
+    req.clip.xmax = 1279;
+    req.clip.ymin = 0;
+    req.clip.ymax = 799;
+
+    //req.render_mode = color_fill_mode;
+    //req.fg_color = 0x80ffffff;
+
+    req.rotate_mode = 1;
+    //req.scale_mode = 2;
+
+    //req.alpha_rop_flag = 0;
+    //req.alpha_rop_mode = 0x19;
+    //req.PD_mode = 3;
+
+    req.sina = 65536;
+    req.cosa = 0;
+
+    //req.mmu_info.mmu_flag = 0x21;
+    //req.mmu_info.mmu_en = 1;
+
+    //printk("src = %.8x\n", req.src.yrgb_addr);
+    //printk("src = %.8x\n", req.src.uv_addr);
+    //printk("dst = %.8x\n", req.dst.yrgb_addr);
+
+
+    rga_blit_sync(&session, &req);
+
+    #if 1
+    fb->var.bits_per_pixel = 32;
+
+    fb->var.xres = 1280;
+    fb->var.yres = 800;
+
+    fb->var.red.length = 8;
+    fb->var.red.offset = 0;
+    fb->var.red.msb_right = 0;
+
+    fb->var.green.length = 8;
+    fb->var.green.offset = 8;
+    fb->var.green.msb_right = 0;
+
+    fb->var.blue.length = 8;
+
+    fb->var.blue.offset = 16;
+    fb->var.blue.msb_right = 0;
+
+    fb->var.transp.length = 8;
+    fb->var.transp.offset = 24;
+    fb->var.transp.msb_right = 0;
+
+    fb->var.nonstd &= (~0xff);
+    fb->var.nonstd |= 1;
+
+    fb->fix.smem_start = virt_to_phys(dst);
+
+    rk_direct_fb_show(fb);
+    #endif
+
+}
+
+#endif
 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 1, 0))
 fs_initcall(rga_init);
 #else
 module_init(rga_init);
 #endif
-module_exit(rga_exit);
-
-/* Module information */
-MODULE_AUTHOR("zsq@rock-chips.com");
-MODULE_DESCRIPTION("Driver for rga device");
-MODULE_LICENSE("GPL");
+module_exit(rga_exit);
+
+/* Module information */
+MODULE_AUTHOR("zsq@rock-chips.com");
+MODULE_DESCRIPTION("Driver for rga device");
+MODULE_LICENSE("GPL");
diff --git a/drivers/video/rockchip/rga/rga_mmu_info.c b/drivers/video/rockchip/rga/rga_mmu_info.c
index 8825183d92fc..9dcffa50a1e2 100644
--- a/drivers/video/rockchip/rga/rga_mmu_info.c
+++ b/drivers/video/rockchip/rga/rga_mmu_info.c
@@ -1,258 +1,298 @@
 /* SPDX-License-Identifier: GPL-2.0 */
-
-
-#include <linux/version.h>
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/fs.h>
-#include <linux/sched.h>
-#include <linux/signal.h>
-#include <linux/pagemap.h>
-#include <linux/seq_file.h>
-#include <linux/mm.h>
-#include <linux/mman.h>
-#include <linux/sched.h>
-#include <linux/slab.h>
-#include <linux/memory.h>
-#include <linux/dma-mapping.h>
-#include <asm/memory.h>
-#include <asm/atomic.h>
-#include <asm/cacheflush.h>
-#include "rga_mmu_info.h"
-#include <linux/delay.h>
-
-extern rga_service_info rga_service;
-extern struct rga_mmu_buf_t rga_mmu_buf;
+
+
+#include <linux/version.h>
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/fs.h>
+#include <linux/sched.h>
+#include <linux/signal.h>
+#include <linux/pagemap.h>
+#include <linux/seq_file.h>
+#include <linux/mm.h>
+#include <linux/mman.h>
+#include <linux/sched.h>
+#include <linux/slab.h>
+#include <linux/memory.h>
+#include <linux/dma-mapping.h>
+#include <asm/memory.h>
+#include <asm/atomic.h>
+#include <asm/cacheflush.h>
+#include "rga_mmu_info.h"
+#include <linux/delay.h>
+
+extern rga_service_info rga_service;
+extern struct rga_mmu_buf_t rga_mmu_buf;
 
 #if RGA_DEBUGFS
 extern int RGA_CHECK_MODE;
 #endif
-
+
 #define KERNEL_SPACE_VALID    0xc0000000
 
 void rga_dma_flush_range(void *pstart, void *pend)
 {
-	dma_sync_single_for_device(drvdata->dev, virt_to_phys(pstart), pend - pstart, DMA_TO_DEVICE);
+	dma_sync_single_for_device(rga_drvdata->dev, virt_to_phys(pstart), pend - pstart, DMA_TO_DEVICE);
 }
-
-static int rga_mmu_buf_get(struct rga_mmu_buf_t *t, uint32_t size)
-{
-    mutex_lock(&rga_service.lock);
-    t->front += size;
-    mutex_unlock(&rga_service.lock);
-
-    return 0;
-}
-
-static int rga_mmu_buf_get_try(struct rga_mmu_buf_t *t, uint32_t size)
-{
-	int ret = 0;
-
-	mutex_lock(&rga_service.lock);
-	if ((t->back - t->front) > t->size) {
-		if(t->front + size > t->back - t->size) {
-			ret = -ENOMEM;
-			goto out;
-		}
-	} else {
-		if ((t->front + size) > t->back) {
-			ret = -ENOMEM;
-			goto out;
-		}
-		if (t->front + size > t->size) {
-			if (size > (t->back - t->size)) {
-				ret = -ENOMEM;
-				goto out;
-			}
-			t->front = 0;
-		}
-	}
-
-out:
-	mutex_unlock(&rga_service.lock);
-	return ret;
-}
-
-static int rga_mem_size_cal(unsigned long Mem, uint32_t MemSize, unsigned long *StartAddr)
-{
-    unsigned long start, end;
-    uint32_t pageCount;
-
-    end = (Mem + (MemSize + PAGE_SIZE - 1)) >> PAGE_SHIFT;
-    start = Mem >> PAGE_SHIFT;
-    pageCount = end - start;
-    *StartAddr = start;
-    return pageCount;
-}
-
-static int rga_buf_size_cal(unsigned long yrgb_addr, unsigned long uv_addr, unsigned long v_addr,
-                                        int format, uint32_t w, uint32_t h, unsigned long *StartAddr )
-{
-    uint32_t size_yrgb = 0;
-    uint32_t size_uv = 0;
-    uint32_t size_v = 0;
-    uint32_t stride = 0;
-    unsigned long start, end;
-    uint32_t pageCount;
-
-    switch(format)
-    {
-        case RK_FORMAT_RGBA_8888 :
-            stride = (w * 4 + 3) & (~3);
-            size_yrgb = stride*h;
-            start = yrgb_addr >> PAGE_SHIFT;
-            pageCount = (size_yrgb + PAGE_SIZE - 1) >> PAGE_SHIFT;
-            break;
-        case RK_FORMAT_RGBX_8888 :
-            stride = (w * 4 + 3) & (~3);
-            size_yrgb = stride*h;
-            start = yrgb_addr >> PAGE_SHIFT;
-            pageCount = (size_yrgb + PAGE_SIZE - 1) >> PAGE_SHIFT;
-            break;
-        case RK_FORMAT_RGB_888 :
-            stride = (w * 3 + 3) & (~3);
-            size_yrgb = stride*h;
-            start = yrgb_addr >> PAGE_SHIFT;
-            pageCount = (size_yrgb + PAGE_SIZE - 1) >> PAGE_SHIFT;
-            break;
-        case RK_FORMAT_BGRA_8888 :
-            size_yrgb = w*h*4;
-            start = yrgb_addr >> PAGE_SHIFT;
-            pageCount = (size_yrgb + PAGE_SIZE - 1) >> PAGE_SHIFT;
-            break;
-        case RK_FORMAT_RGB_565 :
-            stride = (w*2 + 3) & (~3);
-            size_yrgb = stride * h;
-            start = yrgb_addr >> PAGE_SHIFT;
-            pageCount = (size_yrgb + PAGE_SIZE - 1) >> PAGE_SHIFT;
-            break;
-        case RK_FORMAT_RGBA_5551 :
-            stride = (w*2 + 3) & (~3);
-            size_yrgb = stride * h;
-            start = yrgb_addr >> PAGE_SHIFT;
-            pageCount = (size_yrgb + PAGE_SIZE - 1) >> PAGE_SHIFT;
-            break;
-        case RK_FORMAT_RGBA_4444 :
-            stride = (w*2 + 3) & (~3);
-            size_yrgb = stride * h;
-            start = yrgb_addr >> PAGE_SHIFT;
-            pageCount = (size_yrgb + PAGE_SIZE - 1) >> PAGE_SHIFT;
-            break;
-        case RK_FORMAT_BGR_888 :
-            stride = (w*3 + 3) & (~3);
-            size_yrgb = stride * h;
-            start = yrgb_addr >> PAGE_SHIFT;
-            pageCount = (size_yrgb + PAGE_SIZE - 1) >> PAGE_SHIFT;
-            break;
-
-        /* YUV FORMAT */
-        case RK_FORMAT_YCbCr_422_SP :
-            stride = (w + 3) & (~3);
-            size_yrgb = stride * h;
-            size_uv = stride * h;
-            start = MIN(yrgb_addr, uv_addr);
-
-            start >>= PAGE_SHIFT;
-            end = MAX((yrgb_addr + size_yrgb), (uv_addr + size_uv));
-            end = (end + (PAGE_SIZE - 1)) >> PAGE_SHIFT;
-            pageCount = end - start;
-            break;
-        case RK_FORMAT_YCbCr_422_P :
-            stride = (w + 3) & (~3);
-            size_yrgb = stride * h;
-            size_uv = ((stride >> 1) * h);
-            size_v = ((stride >> 1) * h);
-            start = MIN(MIN(yrgb_addr, uv_addr), v_addr);
-            start = start >> PAGE_SHIFT;
-            end = MAX(MAX((yrgb_addr + size_yrgb), (uv_addr + size_uv)), (v_addr + size_v));
-            end = (end + (PAGE_SIZE - 1)) >> PAGE_SHIFT;
-            pageCount = end - start;
-            break;
-        case RK_FORMAT_YCbCr_420_SP :
-            stride = (w + 3) & (~3);
-            size_yrgb = stride * h;
-            size_uv = (stride * (h >> 1));
-            start = MIN(yrgb_addr, uv_addr);
-            start >>= PAGE_SHIFT;
-            end = MAX((yrgb_addr + size_yrgb), (uv_addr + size_uv));
-            end = (end + (PAGE_SIZE - 1)) >> PAGE_SHIFT;
-            pageCount = end - start;
-            break;
-        case RK_FORMAT_YCbCr_420_P :
-            stride = (w + 3) & (~3);
-            size_yrgb = stride * h;
-            size_uv = ((stride >> 1) * (h >> 1));
-            size_v = ((stride >> 1) * (h >> 1));
-            start = MIN(MIN(yrgb_addr, uv_addr), v_addr);
-            start >>= PAGE_SHIFT;
-            end = MAX(MAX((yrgb_addr + size_yrgb), (uv_addr + size_uv)), (v_addr + size_v));
-            end = (end + (PAGE_SIZE - 1)) >> PAGE_SHIFT;
-            pageCount = end - start;
-            break;
-
-        case RK_FORMAT_YCrCb_422_SP :
-            stride = (w + 3) & (~3);
-            size_yrgb = stride * h;
-            size_uv = stride * h;
-            start = MIN(yrgb_addr, uv_addr);
-            start >>= PAGE_SHIFT;
-            end = MAX((yrgb_addr + size_yrgb), (uv_addr + size_uv));
-            end = (end + (PAGE_SIZE - 1)) >> PAGE_SHIFT;
-            pageCount = end - start;
-            break;
-        case RK_FORMAT_YCrCb_422_P :
-            stride = (w + 3) & (~3);
-            size_yrgb = stride * h;
-            size_uv = ((stride >> 1) * h);
-            size_v = ((stride >> 1) * h);
-            start = MIN(MIN(yrgb_addr, uv_addr), v_addr);
-            start >>= PAGE_SHIFT;
-            end = MAX(MAX((yrgb_addr + size_yrgb), (uv_addr + size_uv)), (v_addr + size_v));
-            end = (end + (PAGE_SIZE - 1)) >> PAGE_SHIFT;
-            pageCount = end - start;
-            break;
-
-        case RK_FORMAT_YCrCb_420_SP :
-            stride = (w + 3) & (~3);
-            size_yrgb = stride * h;
-            size_uv = (stride * (h >> 1));
-            start = MIN(yrgb_addr, uv_addr);
-            start >>= PAGE_SHIFT;
-            end = MAX((yrgb_addr + size_yrgb), (uv_addr + size_uv));
-            end = (end + (PAGE_SIZE - 1)) >> PAGE_SHIFT;
-            pageCount = end - start;
-            break;
-        case RK_FORMAT_YCrCb_420_P :
-            stride = (w + 3) & (~3);
-            size_yrgb = stride * h;
-            size_uv = ((stride >> 1) * (h >> 1));
-            size_v = ((stride >> 1) * (h >> 1));
-            start = MIN(MIN(yrgb_addr, uv_addr), v_addr);
-            start >>= PAGE_SHIFT;
-            end = MAX(MAX((yrgb_addr + size_yrgb), (uv_addr + size_uv)), (v_addr + size_v));
-            end = (end + (PAGE_SIZE - 1)) >> PAGE_SHIFT;
-            pageCount = end - start;
-            break;
-        #if 0
-        case RK_FORMAT_BPP1 :
-            break;
-        case RK_FORMAT_BPP2 :
-            break;
-        case RK_FORMAT_BPP4 :
-            break;
-        case RK_FORMAT_BPP8 :
-            break;
-        #endif
-        default :
-            pageCount = 0;
-            start = 0;
-            break;
-    }
-
-    *StartAddr = start;
-    return pageCount;
-}
-
+
+static int rga_mmu_buf_get(struct rga_mmu_buf_t *t, uint32_t size)
+{
+    mutex_lock(&rga_service.lock);
+    t->front += size;
+    mutex_unlock(&rga_service.lock);
+
+    return 0;
+}
+
+static void rga_current_mm_read_lock(struct mm_struct *mm)
+{
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 10, 0)
+	mmap_read_lock(mm);
+#else
+	down_read(&mm->mmap_sem);
+#endif
+}
+
+static void rga_current_mm_read_unlock(struct mm_struct *mm)
+{
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 10, 0)
+	mmap_read_unlock(mm);
+#else
+	up_read(&mm->mmap_sem);
+#endif
+}
+
+static long rga_get_user_pages(struct page **pages, unsigned long Memory,
+			       uint32_t pageCount, int writeFlag,
+			       struct mm_struct *current_mm)
+{
+	#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 4, 168) && \
+		LINUX_VERSION_CODE < KERNEL_VERSION(4, 5, 0)
+		return get_user_pages(current, current_mm, Memory << PAGE_SHIFT,
+				      pageCount, writeFlag ? FOLL_WRITE : 0, pages, NULL);
+	#elif LINUX_VERSION_CODE < KERNEL_VERSION(4, 6, 0)
+		return get_user_pages(current, current_mm, Memory << PAGE_SHIFT,
+				      pageCount, writeFlag ? FOLL_WRITE : 0, 0, pages, NULL);
+	#elif LINUX_VERSION_CODE < KERNEL_VERSION(5, 10, 0)
+		return get_user_pages_remote(current, current_mm, Memory << PAGE_SHIFT,
+					     pageCount, writeFlag ? FOLL_WRITE : 0, pages,
+					     NULL, NULL);
+	#else
+		return get_user_pages_remote(current_mm, Memory << PAGE_SHIFT,
+					     pageCount, writeFlag ? FOLL_WRITE : 0, pages,
+					     NULL, NULL);
+	#endif
+}
+
+static int rga_mmu_buf_get_try(struct rga_mmu_buf_t *t, uint32_t size)
+{
+	int ret = 0;
+
+	mutex_lock(&rga_service.lock);
+	if ((t->back - t->front) > t->size) {
+		if(t->front + size > t->back - t->size) {
+			ret = -ENOMEM;
+			goto out;
+		}
+	} else {
+		if ((t->front + size) > t->back) {
+			ret = -ENOMEM;
+			goto out;
+		}
+		if (t->front + size > t->size) {
+			if (size > (t->back - t->size)) {
+				ret = -ENOMEM;
+				goto out;
+			}
+			t->front = 0;
+		}
+	}
+
+out:
+	mutex_unlock(&rga_service.lock);
+	return ret;
+}
+
+static int rga_mem_size_cal(unsigned long Mem, uint32_t MemSize, unsigned long *StartAddr)
+{
+    unsigned long start, end;
+    uint32_t pageCount;
+
+    end = (Mem + (MemSize + PAGE_SIZE - 1)) >> PAGE_SHIFT;
+    start = Mem >> PAGE_SHIFT;
+    pageCount = end - start;
+    *StartAddr = start;
+    return pageCount;
+}
+
+static int rga_buf_size_cal(unsigned long yrgb_addr, unsigned long uv_addr, unsigned long v_addr,
+                                        int format, uint32_t w, uint32_t h, unsigned long *StartAddr )
+{
+    uint32_t size_yrgb = 0;
+    uint32_t size_uv = 0;
+    uint32_t size_v = 0;
+    uint32_t stride = 0;
+    unsigned long start, end;
+    uint32_t pageCount;
+
+    switch(format)
+    {
+        case RK_FORMAT_RGBA_8888 :
+            stride = (w * 4 + 3) & (~3);
+            size_yrgb = stride*h;
+            start = yrgb_addr >> PAGE_SHIFT;
+            pageCount = (size_yrgb + PAGE_SIZE - 1) >> PAGE_SHIFT;
+            break;
+        case RK_FORMAT_RGBX_8888 :
+            stride = (w * 4 + 3) & (~3);
+            size_yrgb = stride*h;
+            start = yrgb_addr >> PAGE_SHIFT;
+            pageCount = (size_yrgb + PAGE_SIZE - 1) >> PAGE_SHIFT;
+            break;
+        case RK_FORMAT_RGB_888 :
+            stride = (w * 3 + 3) & (~3);
+            size_yrgb = stride*h;
+            start = yrgb_addr >> PAGE_SHIFT;
+            pageCount = (size_yrgb + PAGE_SIZE - 1) >> PAGE_SHIFT;
+            break;
+        case RK_FORMAT_BGRA_8888 :
+            size_yrgb = w*h*4;
+            start = yrgb_addr >> PAGE_SHIFT;
+            pageCount = (size_yrgb + PAGE_SIZE - 1) >> PAGE_SHIFT;
+            break;
+        case RK_FORMAT_RGB_565 :
+            stride = (w*2 + 3) & (~3);
+            size_yrgb = stride * h;
+            start = yrgb_addr >> PAGE_SHIFT;
+            pageCount = (size_yrgb + PAGE_SIZE - 1) >> PAGE_SHIFT;
+            break;
+        case RK_FORMAT_RGBA_5551 :
+            stride = (w*2 + 3) & (~3);
+            size_yrgb = stride * h;
+            start = yrgb_addr >> PAGE_SHIFT;
+            pageCount = (size_yrgb + PAGE_SIZE - 1) >> PAGE_SHIFT;
+            break;
+        case RK_FORMAT_RGBA_4444 :
+            stride = (w*2 + 3) & (~3);
+            size_yrgb = stride * h;
+            start = yrgb_addr >> PAGE_SHIFT;
+            pageCount = (size_yrgb + PAGE_SIZE - 1) >> PAGE_SHIFT;
+            break;
+        case RK_FORMAT_BGR_888 :
+            stride = (w*3 + 3) & (~3);
+            size_yrgb = stride * h;
+            start = yrgb_addr >> PAGE_SHIFT;
+            pageCount = (size_yrgb + PAGE_SIZE - 1) >> PAGE_SHIFT;
+            break;
+
+        /* YUV FORMAT */
+        case RK_FORMAT_YCbCr_422_SP :
+            stride = (w + 3) & (~3);
+            size_yrgb = stride * h;
+            size_uv = stride * h;
+            start = MIN(yrgb_addr, uv_addr);
+
+            start >>= PAGE_SHIFT;
+            end = MAX((yrgb_addr + size_yrgb), (uv_addr + size_uv));
+            end = (end + (PAGE_SIZE - 1)) >> PAGE_SHIFT;
+            pageCount = end - start;
+            break;
+        case RK_FORMAT_YCbCr_422_P :
+            stride = (w + 3) & (~3);
+            size_yrgb = stride * h;
+            size_uv = ((stride >> 1) * h);
+            size_v = ((stride >> 1) * h);
+            start = MIN(MIN(yrgb_addr, uv_addr), v_addr);
+            start = start >> PAGE_SHIFT;
+            end = MAX(MAX((yrgb_addr + size_yrgb), (uv_addr + size_uv)), (v_addr + size_v));
+            end = (end + (PAGE_SIZE - 1)) >> PAGE_SHIFT;
+            pageCount = end - start;
+            break;
+        case RK_FORMAT_YCbCr_420_SP :
+            stride = (w + 3) & (~3);
+            size_yrgb = stride * h;
+            size_uv = (stride * (h >> 1));
+            start = MIN(yrgb_addr, uv_addr);
+            start >>= PAGE_SHIFT;
+            end = MAX((yrgb_addr + size_yrgb), (uv_addr + size_uv));
+            end = (end + (PAGE_SIZE - 1)) >> PAGE_SHIFT;
+            pageCount = end - start;
+            break;
+        case RK_FORMAT_YCbCr_420_P :
+            stride = (w + 3) & (~3);
+            size_yrgb = stride * h;
+            size_uv = ((stride >> 1) * (h >> 1));
+            size_v = ((stride >> 1) * (h >> 1));
+            start = MIN(MIN(yrgb_addr, uv_addr), v_addr);
+            start >>= PAGE_SHIFT;
+            end = MAX(MAX((yrgb_addr + size_yrgb), (uv_addr + size_uv)), (v_addr + size_v));
+            end = (end + (PAGE_SIZE - 1)) >> PAGE_SHIFT;
+            pageCount = end - start;
+            break;
+
+        case RK_FORMAT_YCrCb_422_SP :
+            stride = (w + 3) & (~3);
+            size_yrgb = stride * h;
+            size_uv = stride * h;
+            start = MIN(yrgb_addr, uv_addr);
+            start >>= PAGE_SHIFT;
+            end = MAX((yrgb_addr + size_yrgb), (uv_addr + size_uv));
+            end = (end + (PAGE_SIZE - 1)) >> PAGE_SHIFT;
+            pageCount = end - start;
+            break;
+        case RK_FORMAT_YCrCb_422_P :
+            stride = (w + 3) & (~3);
+            size_yrgb = stride * h;
+            size_uv = ((stride >> 1) * h);
+            size_v = ((stride >> 1) * h);
+            start = MIN(MIN(yrgb_addr, uv_addr), v_addr);
+            start >>= PAGE_SHIFT;
+            end = MAX(MAX((yrgb_addr + size_yrgb), (uv_addr + size_uv)), (v_addr + size_v));
+            end = (end + (PAGE_SIZE - 1)) >> PAGE_SHIFT;
+            pageCount = end - start;
+            break;
+
+        case RK_FORMAT_YCrCb_420_SP :
+            stride = (w + 3) & (~3);
+            size_yrgb = stride * h;
+            size_uv = (stride * (h >> 1));
+            start = MIN(yrgb_addr, uv_addr);
+            start >>= PAGE_SHIFT;
+            end = MAX((yrgb_addr + size_yrgb), (uv_addr + size_uv));
+            end = (end + (PAGE_SIZE - 1)) >> PAGE_SHIFT;
+            pageCount = end - start;
+            break;
+        case RK_FORMAT_YCrCb_420_P :
+            stride = (w + 3) & (~3);
+            size_yrgb = stride * h;
+            size_uv = ((stride >> 1) * (h >> 1));
+            size_v = ((stride >> 1) * (h >> 1));
+            start = MIN(MIN(yrgb_addr, uv_addr), v_addr);
+            start >>= PAGE_SHIFT;
+            end = MAX(MAX((yrgb_addr + size_yrgb), (uv_addr + size_uv)), (v_addr + size_v));
+            end = (end + (PAGE_SIZE - 1)) >> PAGE_SHIFT;
+            pageCount = end - start;
+            break;
+        #if 0
+        case RK_FORMAT_BPP1 :
+            break;
+        case RK_FORMAT_BPP2 :
+            break;
+        case RK_FORMAT_BPP4 :
+            break;
+        case RK_FORMAT_BPP8 :
+            break;
+        #endif
+        default :
+            pageCount = 0;
+            start = 0;
+            break;
+    }
+
+    *StartAddr = start;
+    return pageCount;
+}
+
 #if RGA_DEBUGFS
 static int rga_usermemory_cheeck(struct page **pages, u32 w, u32 h, u32 format, int flag)
 {
@@ -319,109 +359,85 @@ static int rga_usermemory_cheeck(struct page **pages, u32 w, u32 h, u32 format,
 }
 #endif
 
-static int rga_MapUserMemory(struct page **pages,
-                                            uint32_t *pageTable,
-                                            unsigned long Memory,
-                                            uint32_t pageCount)
-{
-    int32_t result;
-    uint32_t i;
-    uint32_t status;
-    unsigned long Address;
-
-    status = 0;
-    Address = 0;
-
-    do {
-#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 10, 0)
-        mmap_read_lock(current->mm);
-#else
-        down_read(&current->mm->mmap_sem);
-#endif
+static int rga_MapUserMemory(struct page **pages,
+                                            uint32_t *pageTable,
+                                            unsigned long Memory,
+                                            uint32_t pageCount)
+{
+    int32_t result;
+    uint32_t i;
+    uint32_t status;
+    unsigned long Address;
 
-#if LINUX_VERSION_CODE < KERNEL_VERSION(4, 6, 0)
-        result = get_user_pages(current, current->mm,
-            Memory << PAGE_SHIFT, pageCount, 1, 0,
-            pages, NULL);
-#elif LINUX_VERSION_CODE < KERNEL_VERSION(5, 10, 0)
-		result = get_user_pages_remote(current, current->mm,
-			Memory << PAGE_SHIFT, pageCount, 1, pages, NULL, NULL);
-#else
-		result = get_user_pages_remote(current->mm, Memory << PAGE_SHIFT,
-									   pageCount, 1, pages, NULL, NULL);
-#endif
+    status = 0;
+    Address = 0;
 
-#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 10, 0)
-		mmap_read_unlock(current->mm);
-#else
-		up_read(&current->mm->mmap_sem);
-#endif
-
-        #if 0
-        if(result <= 0 || result < pageCount)
-        {
-            status = 0;
-
-            for(i=0; i<pageCount; i++)
-            {
-                temp = armv7_va_to_pa((Memory + i) << PAGE_SHIFT);
-                if (temp == 0xffffffff)
-                {
-                    printk("rga find mmu phy ddr error\n ");
-                    status = RGA_OUT_OF_RESOURCES;
-                    break;
-                }
-
-                pageTable[i] = temp;
-            }
-
-            return status;
-        }
-        #else
-        if(result <= 0 || result < pageCount)
-        {
-            struct vm_area_struct *vma;
-
-            if (result>0) {
-#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 10, 0)
-				mmap_read_lock(current->mm);
-#else
-				down_read(&current->mm->mmap_sem);
-#endif
-			    for (i = 0; i < result; i++)
-				    put_page(pages[i]);
-#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 10, 0)
-				mmap_read_unlock(current->mm);
-#else
-				up_read(&current->mm->mmap_sem);
-#endif
-		    }
-
-            for(i=0; i<pageCount; i++)
-            {
-                vma = find_vma(current->mm, (Memory + i) << PAGE_SHIFT);
-
-                if (vma)//&& (vma->vm_flags & VM_PFNMAP) )
-                {
-                    do
-                    {
-                        pte_t       * pte;
-                        spinlock_t  * ptl;
-                        unsigned long pfn;
+    do {
+        rga_current_mm_read_lock(current->mm);
+
+	result = rga_get_user_pages(pages, Memory, pageCount, 1, current->mm);
+
+        rga_current_mm_read_unlock(current->mm);
+
+        #if 0
+        if(result <= 0 || result < pageCount)
+        {
+            status = 0;
+
+            for(i=0; i<pageCount; i++)
+            {
+                temp = armv7_va_to_pa((Memory + i) << PAGE_SHIFT);
+                if (temp == 0xffffffff)
+                {
+                    printk("rga find mmu phy ddr error\n ");
+                    status = RGA_OUT_OF_RESOURCES;
+                    break;
+                }
+
+                pageTable[i] = temp;
+            }
+
+            return status;
+        }
+        #else
+        if(result <= 0 || result < pageCount)
+        {
+            struct vm_area_struct *vma;
+
+            if (result>0) {
+		rga_current_mm_read_lock(current->mm);
+
+		for (i = 0; i < result; i++)
+			put_page(pages[i]);
+
+		rga_current_mm_read_unlock(current->mm);
+	    }
+
+            for(i=0; i<pageCount; i++)
+            {
+                vma = find_vma(current->mm, (Memory + i) << PAGE_SHIFT);
+
+                if (vma)//&& (vma->vm_flags & VM_PFNMAP) )
+                {
+                    do
+                    {
+                        pte_t       * pte;
+                        spinlock_t  * ptl;
+                        unsigned long pfn;
                         pgd_t * pgd;
 #if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 10, 0)
 						p4d_t * p4d;
 #endif
-                        pud_t * pud;
-
-                        pgd = pgd_offset(current->mm, (Memory + i) << PAGE_SHIFT);
-
-                        if(pgd_val(*pgd) == 0)
-                        {
-                            //printk("rga pgd value is zero \n");
-                            break;
-                        }
-
+                        pud_t * pud;
+
+                        pgd = pgd_offset(current->mm, (Memory + i) << PAGE_SHIFT);
+
+                        if(pgd_val(*pgd) == 0)
+                        {
+                            //printk("rga pgd value is zero \n");
+                            break;
+                        }
+
 #if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 10, 0)
 						/* In the four-level page table, it will do nothing and return pgd. */
 						p4d = p4d_offset(pgd, (Memory + i) << PAGE_SHIFT);
@@ -436,217 +452,211 @@ static int rga_MapUserMemory(struct page **pages,
 #else
 						pud = pud_offset(pgd, (Memory + i) << PAGE_SHIFT);
 #endif
-                        if (pud)
-                        {
-                            pmd_t * pmd = pmd_offset(pud, (Memory + i) << PAGE_SHIFT);
-                            if (pmd)
-                            {
-                                pte = pte_offset_map_lock(current->mm, pmd, (Memory + i) << PAGE_SHIFT, &ptl);
-                                if (!pte)
-                                {
-                                    pte_unmap_unlock(pte, ptl);
-                                    break;
-                                }
-                            }
-                            else
-                            {
-                                break;
-                            }
-                        }
-                        else
-                        {
-                            break;
-                        }
-
-                        pfn = pte_pfn(*pte);
-                        Address = ((pfn << PAGE_SHIFT) | (((unsigned long)((Memory + i) << PAGE_SHIFT)) & ~PAGE_MASK));
-                        pte_unmap_unlock(pte, ptl);
-                    }
-                    while (0);
-
-                    pageTable[i] = Address;
-                }
-                else
-                {
-                    status = RGA_OUT_OF_RESOURCES;
-                    break;
-                }
-            }
-
-            return status;
-        }
-        #endif
-
-        /* Fill the page table. */
-        for(i=0; i<pageCount; i++)
-        {
-            /* Get the physical address from page struct. */
-            pageTable[i] = page_to_phys(pages[i]);
-        }
-
-#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 10, 0)
-        mmap_read_lock(current->mm);
-#else
-        down_read(&current->mm->mmap_sem);
-#endif
-		for (i = 0; i < result; i++)
-			put_page(pages[i]);
-#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 10, 0)
-		mmap_read_unlock(current->mm);
-#else
-		up_read(&current->mm->mmap_sem);
-#endif
-
-        return 0;
-    }
-    while(0);
-
-    return status;
-}
-
-static int rga_MapION(struct sg_table *sg,
-                               uint32_t *Memory,
-                               int32_t  pageCount,
-                               uint32_t offset)
-{
-    uint32_t i;
-    uint32_t status;
-    unsigned long Address;
-    uint32_t mapped_size = 0;
-    uint32_t len = 0;
-    struct scatterlist *sgl = sg->sgl;
-    uint32_t sg_num = 0;
-
-    status = 0;
-    Address = 0;
-    offset = offset >> PAGE_SHIFT;
-    if (offset != 0) {
-        do {
-            len += (sg_dma_len(sgl) >> PAGE_SHIFT);
-	        if (len == offset) {
-	    	    sg_num += 1;
-		    break;
-    	    }
-    	    else {
-                if (len > offset)
-                     break;
-    	    }
-                sg_num += 1;
-        }
-        while((sgl = sg_next(sgl)) && (mapped_size < pageCount) && (sg_num < sg->nents));
-
-        sgl = sg->sgl;
-    	len = 0;
-        do {
-            len += (sg_dma_len(sgl) >> PAGE_SHIFT);
-            sgl = sg_next(sgl);
-        }
-        while(--sg_num);
-
-        offset -= len;
-
-        len = sg_dma_len(sgl) >> PAGE_SHIFT;
-        Address = sg_phys(sgl);
-    	Address += offset;
-
-        for(i=offset; i<len; i++) {
-             Memory[i - offset] = Address + (i << PAGE_SHIFT);
-        }
-        mapped_size += (len - offset);
-        sg_num = 1;
-        sgl = sg_next(sgl);
-        do {
-            len = sg_dma_len(sgl) >> PAGE_SHIFT;
-            Address = sg_phys(sgl);
-
-            for(i=0; i<len; i++) {
-                Memory[mapped_size + i] = Address + (i << PAGE_SHIFT);
-            }
-
-            mapped_size += len;
-            sg_num += 1;
-        }
-        while((sgl = sg_next(sgl)) && (mapped_size < pageCount) && (sg_num < sg->nents));
-    }
-    else {
-        do {
-            len = sg_dma_len(sgl) >> PAGE_SHIFT;
-            Address = sg_phys(sgl);
-            for(i=0; i<len; i++) {
-                Memory[mapped_size + i] = Address + (i << PAGE_SHIFT);
-            }
-            mapped_size += len;
-            sg_num += 1;
-        }
-        while((sgl = sg_next(sgl)) && (mapped_size < pageCount) && (sg_num < sg->nents));
-    }
-    return 0;
-}
-
-
-static int rga_mmu_info_BitBlt_mode(struct rga_reg *reg, struct rga_req *req)
-{
-    int SrcMemSize, DstMemSize;
-    unsigned long SrcStart, DstStart;
-    uint32_t i;
-    uint32_t AllSize;
-    uint32_t *MMU_Base, *MMU_p, *MMU_Base_phys;
-    int ret;
-    int status;
-    uint32_t uv_size, v_size;
-
-    struct page **pages = NULL;
-
-    MMU_Base = NULL;
-
-    SrcMemSize = 0;
-    DstMemSize = 0;
-
-    do {
-        /* cal src buf mmu info */
-        SrcMemSize = rga_buf_size_cal(req->src.yrgb_addr, req->src.uv_addr, req->src.v_addr,
-                                        req->src.format, req->src.vir_w, req->src.act_h + req->src.y_offset,
-                                        &SrcStart);
-        if(SrcMemSize == 0) {
-            return -EINVAL;
-        }
-
-        /* cal dst buf mmu info */
-
-        DstMemSize = rga_buf_size_cal(req->dst.yrgb_addr, req->dst.uv_addr, req->dst.v_addr,
-                                        req->dst.format, req->dst.vir_w, req->dst.vir_h,
-                                        &DstStart);
-        if(DstMemSize == 0)
-            return -EINVAL;
-
-        /* Cal out the needed mem size */
-        SrcMemSize = (SrcMemSize + 15) & (~15);
-        DstMemSize = (DstMemSize + 15) & (~15);
-        AllSize = SrcMemSize + DstMemSize;
-
-        if (rga_mmu_buf_get_try(&rga_mmu_buf, AllSize + 16)) {
-            pr_err("RGA Get MMU mem failed\n");
-            status = RGA_MALLOC_ERROR;
-            break;
-        }
-
-        mutex_lock(&rga_service.lock);
-        MMU_Base = rga_mmu_buf.buf_virtual + (rga_mmu_buf.front & (rga_mmu_buf.size - 1));
-        MMU_Base_phys = rga_mmu_buf.buf + (rga_mmu_buf.front & (rga_mmu_buf.size - 1));
-        mutex_unlock(&rga_service.lock);
-
-        pages = rga_mmu_buf.pages;
-
-        if((req->mmu_info.mmu_flag >> 8) & 1) {
-            if (req->sg_src) {
-                ret = rga_MapION(req->sg_src, &MMU_Base[0], SrcMemSize, req->line_draw_info.flag);
-            }
-            else {
-                ret = rga_MapUserMemory(&pages[0], &MMU_Base[0], SrcStart, SrcMemSize);
-                if (ret < 0) {
-                    pr_err("rga map src memory failed\n");
-                    status = ret;
-                    break;
+                        if (pud)
+                        {
+                            pmd_t * pmd = pmd_offset(pud, (Memory + i) << PAGE_SHIFT);
+                            if (pmd)
+                            {
+                                pte = pte_offset_map_lock(current->mm, pmd, (Memory + i) << PAGE_SHIFT, &ptl);
+                                if (!pte)
+                                {
+                                    pte_unmap_unlock(pte, ptl);
+                                    break;
+                                }
+                            }
+                            else
+                            {
+                                break;
+                            }
+                        }
+                        else
+                        {
+                            break;
+                        }
+
+                        pfn = pte_pfn(*pte);
+                        Address = ((pfn << PAGE_SHIFT) | (((unsigned long)((Memory + i) << PAGE_SHIFT)) & ~PAGE_MASK));
+                        pte_unmap_unlock(pte, ptl);
+                    }
+                    while (0);
+
+                    pageTable[i] = Address;
+                }
+                else
+                {
+                    status = RGA_OUT_OF_RESOURCES;
+                    break;
+                }
+            }
+
+            return status;
+        }
+        #endif
+
+        /* Fill the page table. */
+        for(i=0; i<pageCount; i++)
+        {
+            /* Get the physical address from page struct. */
+            pageTable[i] = page_to_phys(pages[i]);
+        }
+
+	rga_current_mm_read_lock(current->mm);
+
+	for (i = 0; i < result; i++)
+		put_page(pages[i]);
+
+	rga_current_mm_read_unlock(current->mm);
+
+        return 0;
+    }
+    while(0);
+
+    return status;
+}
+
+static int rga_MapION(struct sg_table *sg,
+                               uint32_t *Memory,
+                               int32_t  pageCount,
+                               uint32_t offset)
+{
+    uint32_t i;
+    uint32_t status;
+    unsigned long Address;
+    uint32_t mapped_size = 0;
+    uint32_t len = 0;
+    struct scatterlist *sgl = sg->sgl;
+    uint32_t sg_num = 0;
+
+    status = 0;
+    Address = 0;
+    offset = offset >> PAGE_SHIFT;
+    if (offset != 0) {
+        do {
+            len += (sg_dma_len(sgl) >> PAGE_SHIFT);
+	        if (len == offset) {
+	    	    sg_num += 1;
+		    break;
+    	    }
+    	    else {
+                if (len > offset)
+                     break;
+    	    }
+                sg_num += 1;
+        }
+        while((sgl = sg_next(sgl)) && (mapped_size < pageCount) && (sg_num < sg->nents));
+
+        sgl = sg->sgl;
+    	len = 0;
+        do {
+            len += (sg_dma_len(sgl) >> PAGE_SHIFT);
+            sgl = sg_next(sgl);
+        }
+        while(--sg_num);
+
+        offset -= len;
+
+        len = sg_dma_len(sgl) >> PAGE_SHIFT;
+        Address = sg_phys(sgl);
+    	Address += offset;
+
+        for(i=offset; i<len; i++) {
+             Memory[i - offset] = Address + (i << PAGE_SHIFT);
+        }
+        mapped_size += (len - offset);
+        sg_num = 1;
+        sgl = sg_next(sgl);
+        do {
+            len = sg_dma_len(sgl) >> PAGE_SHIFT;
+            Address = sg_phys(sgl);
+
+            for(i=0; i<len; i++) {
+                Memory[mapped_size + i] = Address + (i << PAGE_SHIFT);
+            }
+
+            mapped_size += len;
+            sg_num += 1;
+        }
+        while((sgl = sg_next(sgl)) && (mapped_size < pageCount) && (sg_num < sg->nents));
+    }
+    else {
+        do {
+            len = sg_dma_len(sgl) >> PAGE_SHIFT;
+            Address = sg_phys(sgl);
+            for(i=0; i<len; i++) {
+                Memory[mapped_size + i] = Address + (i << PAGE_SHIFT);
+            }
+            mapped_size += len;
+            sg_num += 1;
+        }
+        while((sgl = sg_next(sgl)) && (mapped_size < pageCount) && (sg_num < sg->nents));
+    }
+    return 0;
+}
+
+
+static int rga_mmu_info_BitBlt_mode(struct rga_reg *reg, struct rga_req *req)
+{
+    int SrcMemSize, DstMemSize;
+    unsigned long SrcStart, DstStart;
+    uint32_t i;
+    uint32_t AllSize;
+    uint32_t *MMU_Base, *MMU_p, *MMU_Base_phys;
+    int ret;
+    int status;
+    uint32_t uv_size, v_size;
+
+    struct page **pages = NULL;
+
+    MMU_Base = NULL;
+
+    SrcMemSize = 0;
+    DstMemSize = 0;
+
+    do {
+        /* cal src buf mmu info */
+        SrcMemSize = rga_buf_size_cal(req->src.yrgb_addr, req->src.uv_addr, req->src.v_addr,
+                                        req->src.format, req->src.vir_w, req->src.act_h + req->src.y_offset,
+                                        &SrcStart);
+        if(SrcMemSize == 0) {
+            return -EINVAL;
+        }
+
+        /* cal dst buf mmu info */
+
+        DstMemSize = rga_buf_size_cal(req->dst.yrgb_addr, req->dst.uv_addr, req->dst.v_addr,
+                                        req->dst.format, req->dst.vir_w, req->dst.vir_h,
+                                        &DstStart);
+        if(DstMemSize == 0)
+            return -EINVAL;
+
+        /* Cal out the needed mem size */
+        SrcMemSize = (SrcMemSize + 15) & (~15);
+        DstMemSize = (DstMemSize + 15) & (~15);
+        AllSize = SrcMemSize + DstMemSize;
+
+        if (rga_mmu_buf_get_try(&rga_mmu_buf, AllSize + 16)) {
+            pr_err("RGA Get MMU mem failed\n");
+            status = RGA_MALLOC_ERROR;
+            break;
+        }
+
+        mutex_lock(&rga_service.lock);
+        MMU_Base = rga_mmu_buf.buf_virtual + (rga_mmu_buf.front & (rga_mmu_buf.size - 1));
+        MMU_Base_phys = rga_mmu_buf.buf + (rga_mmu_buf.front & (rga_mmu_buf.size - 1));
+        mutex_unlock(&rga_service.lock);
+
+        pages = rga_mmu_buf.pages;
+
+        if((req->mmu_info.mmu_flag >> 8) & 1) {
+            if (req->sg_src) {
+                ret = rga_MapION(req->sg_src, &MMU_Base[0], SrcMemSize, req->line_draw_info.flag);
+            }
+            else {
+                ret = rga_MapUserMemory(&pages[0], &MMU_Base[0], SrcStart, SrcMemSize);
+                if (ret < 0) {
+                    pr_err("rga map src memory failed\n");
+                    status = ret;
+                    break;
                 }
 
 #if RGA_DEBUGFS
@@ -654,662 +664,662 @@ static int rga_mmu_info_BitBlt_mode(struct rga_reg *reg, struct rga_req *req)
 		rga_usermemory_cheeck(&pages[0], req->src.vir_w,
 				      req->src.vir_h, req->src.format, 1);
 #endif
-            }
-        }
-        else {
-            MMU_p = MMU_Base;
-
-            if(req->src.yrgb_addr == (unsigned long)rga_service.pre_scale_buf) {
-                for(i=0; i<SrcMemSize; i++)
-                    MMU_p[i] = rga_service.pre_scale_buf[i];
-            }
-            else {
-                for(i=0; i<SrcMemSize; i++)
-                    MMU_p[i] = (uint32_t)((SrcStart + i) << PAGE_SHIFT);
-            }
-        }
-
-        if ((req->mmu_info.mmu_flag >> 10) & 1) {
-            if (req->sg_dst) {
-                ret = rga_MapION(req->sg_dst, &MMU_Base[SrcMemSize], DstMemSize, req->line_draw_info.line_width);
-            }
-            else {
-                ret = rga_MapUserMemory(&pages[SrcMemSize], &MMU_Base[SrcMemSize], DstStart, DstMemSize);
-                if (ret < 0) {
-                    pr_err("rga map dst memory failed\n");
-                    status = ret;
-                    break;
-                }
+            }
+        }
+        else {
+            MMU_p = MMU_Base;
+
+            if(req->src.yrgb_addr == (unsigned long)rga_service.pre_scale_buf) {
+                for(i=0; i<SrcMemSize; i++)
+                    MMU_p[i] = rga_service.pre_scale_buf[i];
+            }
+            else {
+                for(i=0; i<SrcMemSize; i++)
+                    MMU_p[i] = (uint32_t)((SrcStart + i) << PAGE_SHIFT);
+            }
+        }
+
+        if ((req->mmu_info.mmu_flag >> 10) & 1) {
+            if (req->sg_dst) {
+                ret = rga_MapION(req->sg_dst, &MMU_Base[SrcMemSize], DstMemSize, req->line_draw_info.line_width);
+            }
+            else {
+                ret = rga_MapUserMemory(&pages[SrcMemSize], &MMU_Base[SrcMemSize], DstStart, DstMemSize);
+                if (ret < 0) {
+                    pr_err("rga map dst memory failed\n");
+                    status = ret;
+                    break;
+                }
 
 #if RGA_DEBUGFS
 	if (RGA_CHECK_MODE)
 		rga_usermemory_cheeck(&pages[0], req->src.vir_w,
 				      req->src.vir_h, req->src.format, 2);
 #endif
-            }
-        }
-        else {
-            MMU_p = MMU_Base + SrcMemSize;
-            for(i=0; i<DstMemSize; i++)
-                MMU_p[i] = (uint32_t)((DstStart + i) << PAGE_SHIFT);
-        }
-
-        MMU_Base[AllSize] = MMU_Base[AllSize-1];
-
-        /* zsq
-         * change the buf address in req struct
-         */
-
-        req->mmu_info.base_addr = (unsigned long)MMU_Base_phys >> 2;
-
-        uv_size = (req->src.uv_addr - (SrcStart << PAGE_SHIFT)) >> PAGE_SHIFT;
-        v_size = (req->src.v_addr - (SrcStart << PAGE_SHIFT)) >> PAGE_SHIFT;
-
-        req->src.yrgb_addr = (req->src.yrgb_addr & (~PAGE_MASK));
-        req->src.uv_addr = (req->src.uv_addr & (~PAGE_MASK)) | (uv_size << PAGE_SHIFT);
-        req->src.v_addr = (req->src.v_addr & (~PAGE_MASK)) | (v_size << PAGE_SHIFT);
-
-        uv_size = (req->dst.uv_addr - (DstStart << PAGE_SHIFT)) >> PAGE_SHIFT;
-
-        req->dst.yrgb_addr = (req->dst.yrgb_addr & (~PAGE_MASK)) | (SrcMemSize << PAGE_SHIFT);
-        req->dst.uv_addr = (req->dst.uv_addr & (~PAGE_MASK)) | ((SrcMemSize + uv_size) << PAGE_SHIFT);
-
-        /* flush data to DDR */
+            }
+        }
+        else {
+            MMU_p = MMU_Base + SrcMemSize;
+            for(i=0; i<DstMemSize; i++)
+                MMU_p[i] = (uint32_t)((DstStart + i) << PAGE_SHIFT);
+        }
+
+        MMU_Base[AllSize] = MMU_Base[AllSize-1];
+
+        /* zsq
+         * change the buf address in req struct
+         */
+
+        req->mmu_info.base_addr = (unsigned long)MMU_Base_phys >> 2;
+
+        uv_size = (req->src.uv_addr - (SrcStart << PAGE_SHIFT)) >> PAGE_SHIFT;
+        v_size = (req->src.v_addr - (SrcStart << PAGE_SHIFT)) >> PAGE_SHIFT;
+
+        req->src.yrgb_addr = (req->src.yrgb_addr & (~PAGE_MASK));
+        req->src.uv_addr = (req->src.uv_addr & (~PAGE_MASK)) | (uv_size << PAGE_SHIFT);
+        req->src.v_addr = (req->src.v_addr & (~PAGE_MASK)) | (v_size << PAGE_SHIFT);
+
+        uv_size = (req->dst.uv_addr - (DstStart << PAGE_SHIFT)) >> PAGE_SHIFT;
+
+        req->dst.yrgb_addr = (req->dst.yrgb_addr & (~PAGE_MASK)) | (SrcMemSize << PAGE_SHIFT);
+        req->dst.uv_addr = (req->dst.uv_addr & (~PAGE_MASK)) | ((SrcMemSize + uv_size) << PAGE_SHIFT);
+
+        /* flush data to DDR */
         rga_dma_flush_range(MMU_Base, (MMU_Base + AllSize + 1));
-
-        rga_mmu_buf_get(&rga_mmu_buf, AllSize + 16);
-        reg->MMU_len = AllSize + 16;
-
-        status = 0;
-
-        return status;
-    }
-    while(0);
-
-    return status;
-}
-
-static int rga_mmu_info_color_palette_mode(struct rga_reg *reg, struct rga_req *req)
-{
-    int SrcMemSize, DstMemSize, CMDMemSize;
-    unsigned long SrcStart, DstStart, CMDStart;
-    struct page **pages = NULL;
-    uint32_t i;
-    uint32_t AllSize;
-    uint32_t *MMU_Base = NULL, *MMU_Base_phys = NULL;
-    uint32_t *MMU_p;
-    int ret, status = 0;
-    uint32_t stride;
-
-    uint8_t shift;
-    uint16_t sw, byte_num;
-
-    shift = 3 - (req->palette_mode & 3);
-    sw = req->src.vir_w;
-    byte_num = sw >> shift;
-    stride = (byte_num + 3) & (~3);
-
-    do {
-        SrcMemSize = rga_mem_size_cal(req->src.yrgb_addr, stride, &SrcStart);
-        if(SrcMemSize == 0) {
-            return -EINVAL;
-        }
-
-        DstMemSize = rga_buf_size_cal(req->dst.yrgb_addr, req->dst.uv_addr, req->dst.v_addr,
-                                        req->dst.format, req->dst.vir_w, req->dst.vir_h,
-                                        &DstStart);
-        if(DstMemSize == 0) {
-            return -EINVAL;
-        }
-
-        CMDMemSize = rga_mem_size_cal((unsigned long)rga_service.cmd_buff, RGA_CMD_BUF_SIZE, &CMDStart);
-        if(CMDMemSize == 0) {
-            return -EINVAL;
-        }
-
-        SrcMemSize = (SrcMemSize + 15) & (~15);
-        DstMemSize = (DstMemSize + 15) & (~15);
-        CMDMemSize = (CMDMemSize + 15) & (~15);
-
-        AllSize = SrcMemSize + DstMemSize + CMDMemSize;
-
-        if (rga_mmu_buf_get_try(&rga_mmu_buf, AllSize + 16)) {
-            pr_err("RGA Get MMU mem failed\n");
-            status = RGA_MALLOC_ERROR;
-            break;
-        }
-
-        mutex_lock(&rga_service.lock);
-        MMU_Base = rga_mmu_buf.buf_virtual + (rga_mmu_buf.front & (rga_mmu_buf.size - 1));
-        MMU_Base_phys = rga_mmu_buf.buf + (rga_mmu_buf.front & (rga_mmu_buf.size - 1));
-        mutex_unlock(&rga_service.lock);
-
-        pages = rga_mmu_buf.pages;
-
-        /* map CMD addr */
-        for(i=0; i<CMDMemSize; i++) {
-            MMU_Base[i] = (uint32_t)virt_to_phys((uint32_t *)((CMDStart + i)<<PAGE_SHIFT));
-        }
-
-        /* map src addr */
-        if (req->src.yrgb_addr < KERNEL_SPACE_VALID) {
-            ret = rga_MapUserMemory(&pages[CMDMemSize], &MMU_Base[CMDMemSize], SrcStart, SrcMemSize);
-            if (ret < 0) {
-                pr_err("rga map src memory failed\n");
-                status = ret;
-                break;
-            }
-        }
-        else {
-            MMU_p = MMU_Base + CMDMemSize;
-
-            for(i=0; i<SrcMemSize; i++)
-            {
-                MMU_p[i] = (uint32_t)virt_to_phys((uint32_t *)((SrcStart + i) << PAGE_SHIFT));
-            }
-        }
-
-        /* map dst addr */
-        if (req->src.yrgb_addr < KERNEL_SPACE_VALID) {
-            ret = rga_MapUserMemory(&pages[CMDMemSize + SrcMemSize], &MMU_Base[CMDMemSize + SrcMemSize], DstStart, DstMemSize);
-            if (ret < 0) {
-                pr_err("rga map dst memory failed\n");
-                status = ret;
-                break;
-            }
-        }
-        else {
-            MMU_p = MMU_Base + CMDMemSize + SrcMemSize;
-            for(i=0; i<DstMemSize; i++)
-                MMU_p[i] = (uint32_t)virt_to_phys((uint32_t *)((DstStart + i) << PAGE_SHIFT));
-        }
-
-
-        /* zsq
-         * change the buf address in req struct
-         * for the reason of lie to MMU
-         */
-        req->mmu_info.base_addr = (virt_to_phys(MMU_Base)>>2);
-        req->src.yrgb_addr = (req->src.yrgb_addr & (~PAGE_MASK)) | (CMDMemSize << PAGE_SHIFT);
-        req->dst.yrgb_addr = (req->dst.yrgb_addr & (~PAGE_MASK)) | ((CMDMemSize + SrcMemSize) << PAGE_SHIFT);
-
-        /*record the malloc buf for the cmd end to release*/
-        reg->MMU_base = MMU_Base;
-
-        /* flush data to DDR */
-        rga_dma_flush_range(MMU_Base, (MMU_Base + AllSize + 1));
-
-        rga_mmu_buf_get(&rga_mmu_buf, AllSize + 16);
-        reg->MMU_len = AllSize + 16;
-
+
+        rga_mmu_buf_get(&rga_mmu_buf, AllSize + 16);
+        reg->MMU_len = AllSize + 16;
+
+        status = 0;
+
         return status;
-
-    }
-    while(0);
-
-    return 0;
-}
-
-static int rga_mmu_info_color_fill_mode(struct rga_reg *reg, struct rga_req *req)
-{
-    int DstMemSize;
-    unsigned long DstStart;
-    struct page **pages = NULL;
-    uint32_t i;
-    uint32_t AllSize;
-    uint32_t *MMU_Base, *MMU_p, *MMU_Base_phys;
-    int ret;
-    int status;
-
-    MMU_Base = NULL;
-
-    do {
-        DstMemSize = rga_buf_size_cal(req->dst.yrgb_addr, req->dst.uv_addr, req->dst.v_addr,
-                                        req->dst.format, req->dst.vir_w, req->dst.vir_h,
-                                        &DstStart);
-        if(DstMemSize == 0) {
-            return -EINVAL;
-        }
-
-        AllSize = (DstMemSize + 15) & (~15);
-
-        pages = rga_mmu_buf.pages;
-
-        if (rga_mmu_buf_get_try(&rga_mmu_buf, AllSize + 16)) {
-            pr_err("RGA Get MMU mem failed\n");
-            status = RGA_MALLOC_ERROR;
-            break;
-        }
-
-        mutex_lock(&rga_service.lock);
-        MMU_Base = rga_mmu_buf.buf_virtual + (rga_mmu_buf.front & (rga_mmu_buf.size - 1));
-        MMU_Base_phys = rga_mmu_buf.buf + (rga_mmu_buf.front & (rga_mmu_buf.size - 1));
-        mutex_unlock(&rga_service.lock);
-
-        if (req->dst.yrgb_addr < KERNEL_SPACE_VALID) {
-            if (req->sg_dst) {
-                ret = rga_MapION(req->sg_dst, &MMU_Base[0], DstMemSize, req->line_draw_info.line_width);
-            }
-            else {
-                ret = rga_MapUserMemory(&pages[0], &MMU_Base[0], DstStart, DstMemSize);
-                if (ret < 0) {
-                    pr_err("rga map dst memory failed\n");
-                    status = ret;
-                    break;
-                }
-            }
-        }
-        else {
-            MMU_p = MMU_Base;
-            for(i=0; i<DstMemSize; i++)
-                MMU_p[i] = (uint32_t)((DstStart + i) << PAGE_SHIFT);
-        }
-
-        MMU_Base[AllSize] = MMU_Base[AllSize - 1];
-
-        /* zsq
-         * change the buf address in req struct
-         */
-
-        req->mmu_info.base_addr = ((unsigned long)(MMU_Base_phys)>>2);
-        req->dst.yrgb_addr = (req->dst.yrgb_addr & (~PAGE_MASK));
-
-        /*record the malloc buf for the cmd end to release*/
-        reg->MMU_base = MMU_Base;
-
-        /* flush data to DDR */
+    }
+    while(0);
+
+    return status;
+}
+
+static int rga_mmu_info_color_palette_mode(struct rga_reg *reg, struct rga_req *req)
+{
+    int SrcMemSize, DstMemSize, CMDMemSize;
+    unsigned long SrcStart, DstStart, CMDStart;
+    struct page **pages = NULL;
+    uint32_t i;
+    uint32_t AllSize;
+    uint32_t *MMU_Base = NULL, *MMU_Base_phys = NULL;
+    uint32_t *MMU_p;
+    int ret, status = 0;
+    uint32_t stride;
+
+    uint8_t shift;
+    uint16_t sw, byte_num;
+
+    shift = 3 - (req->palette_mode & 3);
+    sw = req->src.vir_w;
+    byte_num = sw >> shift;
+    stride = (byte_num + 3) & (~3);
+
+    do {
+        SrcMemSize = rga_mem_size_cal(req->src.yrgb_addr, stride, &SrcStart);
+        if(SrcMemSize == 0) {
+            return -EINVAL;
+        }
+
+        DstMemSize = rga_buf_size_cal(req->dst.yrgb_addr, req->dst.uv_addr, req->dst.v_addr,
+                                        req->dst.format, req->dst.vir_w, req->dst.vir_h,
+                                        &DstStart);
+        if(DstMemSize == 0) {
+            return -EINVAL;
+        }
+
+        CMDMemSize = rga_mem_size_cal((unsigned long)rga_service.cmd_buff, RGA_CMD_BUF_SIZE, &CMDStart);
+        if(CMDMemSize == 0) {
+            return -EINVAL;
+        }
+
+        SrcMemSize = (SrcMemSize + 15) & (~15);
+        DstMemSize = (DstMemSize + 15) & (~15);
+        CMDMemSize = (CMDMemSize + 15) & (~15);
+
+        AllSize = SrcMemSize + DstMemSize + CMDMemSize;
+
+        if (rga_mmu_buf_get_try(&rga_mmu_buf, AllSize + 16)) {
+            pr_err("RGA Get MMU mem failed\n");
+            status = RGA_MALLOC_ERROR;
+            break;
+        }
+
+        mutex_lock(&rga_service.lock);
+        MMU_Base = rga_mmu_buf.buf_virtual + (rga_mmu_buf.front & (rga_mmu_buf.size - 1));
+        MMU_Base_phys = rga_mmu_buf.buf + (rga_mmu_buf.front & (rga_mmu_buf.size - 1));
+        mutex_unlock(&rga_service.lock);
+
+        pages = rga_mmu_buf.pages;
+
+        /* map CMD addr */
+        for(i=0; i<CMDMemSize; i++) {
+            MMU_Base[i] = (uint32_t)virt_to_phys((uint32_t *)((CMDStart + i)<<PAGE_SHIFT));
+        }
+
+        /* map src addr */
+        if (req->src.yrgb_addr < KERNEL_SPACE_VALID) {
+            ret = rga_MapUserMemory(&pages[CMDMemSize], &MMU_Base[CMDMemSize], SrcStart, SrcMemSize);
+            if (ret < 0) {
+                pr_err("rga map src memory failed\n");
+                status = ret;
+                break;
+            }
+        }
+        else {
+            MMU_p = MMU_Base + CMDMemSize;
+
+            for(i=0; i<SrcMemSize; i++)
+            {
+                MMU_p[i] = (uint32_t)virt_to_phys((uint32_t *)((SrcStart + i) << PAGE_SHIFT));
+            }
+        }
+
+        /* map dst addr */
+        if (req->src.yrgb_addr < KERNEL_SPACE_VALID) {
+            ret = rga_MapUserMemory(&pages[CMDMemSize + SrcMemSize], &MMU_Base[CMDMemSize + SrcMemSize], DstStart, DstMemSize);
+            if (ret < 0) {
+                pr_err("rga map dst memory failed\n");
+                status = ret;
+                break;
+            }
+        }
+        else {
+            MMU_p = MMU_Base + CMDMemSize + SrcMemSize;
+            for(i=0; i<DstMemSize; i++)
+                MMU_p[i] = (uint32_t)virt_to_phys((uint32_t *)((DstStart + i) << PAGE_SHIFT));
+        }
+
+
+        /* zsq
+         * change the buf address in req struct
+         * for the reason of lie to MMU
+         */
+        req->mmu_info.base_addr = (virt_to_phys(MMU_Base)>>2);
+        req->src.yrgb_addr = (req->src.yrgb_addr & (~PAGE_MASK)) | (CMDMemSize << PAGE_SHIFT);
+        req->dst.yrgb_addr = (req->dst.yrgb_addr & (~PAGE_MASK)) | ((CMDMemSize + SrcMemSize) << PAGE_SHIFT);
+
+        /*record the malloc buf for the cmd end to release*/
+        reg->MMU_base = MMU_Base;
+
+        /* flush data to DDR */
         rga_dma_flush_range(MMU_Base, (MMU_Base + AllSize + 1));
-
-        rga_mmu_buf_get(&rga_mmu_buf, AllSize + 16);
-        reg->MMU_len = AllSize + 16;
-
-        return 0;
-    }
-    while(0);
-
-    return status;
-}
-
-
-static int rga_mmu_info_line_point_drawing_mode(struct rga_reg *reg, struct rga_req *req)
-{
-    return 0;
-}
-
-static int rga_mmu_info_blur_sharp_filter_mode(struct rga_reg *reg, struct rga_req *req)
-{
-    return 0;
-}
-
-
-
-static int rga_mmu_info_pre_scale_mode(struct rga_reg *reg, struct rga_req *req)
-{
-    int SrcMemSize, DstMemSize;
-    unsigned long SrcStart, DstStart;
-    struct page **pages = NULL;
-    uint32_t i;
-    uint32_t AllSize;
-    uint32_t *MMU_Base, *MMU_p, *MMU_Base_phys;
-    int ret;
-    int status;
-    uint32_t uv_size, v_size;
-
-    MMU_Base = NULL;
-
-    do {
-        /* cal src buf mmu info */
-        SrcMemSize = rga_buf_size_cal(req->src.yrgb_addr, req->src.uv_addr, req->src.v_addr,
-                                        req->src.format, req->src.vir_w, req->src.vir_h,
-                                        &SrcStart);
-        if(SrcMemSize == 0) {
-            return -EINVAL;
-        }
-
-        /* cal dst buf mmu info */
-        DstMemSize = rga_buf_size_cal(req->dst.yrgb_addr, req->dst.uv_addr, req->dst.v_addr,
-                                        req->dst.format, req->dst.vir_w, req->dst.vir_h,
-                                        &DstStart);
-        if(DstMemSize == 0) {
-            return -EINVAL;
-        }
-
-	    SrcMemSize = (SrcMemSize + 15) & (~15);
-	    DstMemSize = (DstMemSize + 15) & (~15);
-
-        AllSize = SrcMemSize + DstMemSize;
-
-        pages = rga_mmu_buf.pages;
-
-        if (rga_mmu_buf_get_try(&rga_mmu_buf, AllSize + 16)) {
-            pr_err("RGA Get MMU mem failed\n");
-            status = RGA_MALLOC_ERROR;
-            break;
-        }
-
-        mutex_lock(&rga_service.lock);
-        MMU_Base = rga_mmu_buf.buf_virtual + (rga_mmu_buf.front & (rga_mmu_buf.size - 1));
-        MMU_Base_phys = rga_mmu_buf.buf + (rga_mmu_buf.front & (rga_mmu_buf.size - 1));
-        mutex_unlock(&rga_service.lock);
-
-        /* map src pages */
-        if ((req->mmu_info.mmu_flag >> 8) & 1) {
-            if (req->sg_src) {
-                ret = rga_MapION(req->sg_src, &MMU_Base[0], SrcMemSize,req->line_draw_info.flag);
-            }
-            else {
-                ret = rga_MapUserMemory(&pages[0], &MMU_Base[0], SrcStart, SrcMemSize);
-                if (ret < 0) {
-                    pr_err("rga map src memory failed\n");
-                    status = ret;
-                    break;
-                }
-            }
-        }
-        else {
-            MMU_p = MMU_Base;
-
-            for(i=0; i<SrcMemSize; i++)
-                MMU_p[i] = (uint32_t)((SrcStart + i) << PAGE_SHIFT);
-        }
-
-        if((req->mmu_info.mmu_flag >> 10) & 1) {
-            if (req->sg_dst) {
-                ret = rga_MapION(req->sg_dst, &MMU_Base[SrcMemSize], DstMemSize, req->line_draw_info.line_width);
-            }
-            else {
-                ret = rga_MapUserMemory(&pages[SrcMemSize], &MMU_Base[SrcMemSize], DstStart, DstMemSize);
-                if (ret < 0) {
-                    pr_err("rga map dst memory failed\n");
-                    status = ret;
-                    break;
-                }
-            }
-        }
-        else
-        {
-            /* kernel space */
-            MMU_p = MMU_Base + SrcMemSize;
-
-            if(req->dst.yrgb_addr == (unsigned long)rga_service.pre_scale_buf) {
-                for(i=0; i<DstMemSize; i++)
-                    MMU_p[i] = rga_service.pre_scale_buf[i];
-            }
-            else {
-                for(i=0; i<DstMemSize; i++)
-                    MMU_p[i] = (uint32_t)((DstStart + i) << PAGE_SHIFT);
-            }
-        }
-
-        MMU_Base[AllSize] = MMU_Base[AllSize];
-
-        /* zsq
-         * change the buf address in req struct
-         * for the reason of lie to MMU
-         */
-
-        req->mmu_info.base_addr = ((unsigned long)(MMU_Base_phys)>>2);
-
-        uv_size = (req->src.uv_addr - (SrcStart << PAGE_SHIFT)) >> PAGE_SHIFT;
-        v_size = (req->src.v_addr - (SrcStart << PAGE_SHIFT)) >> PAGE_SHIFT;
-
-        req->src.yrgb_addr = (req->src.yrgb_addr & (~PAGE_MASK));
-        req->src.uv_addr = (req->src.uv_addr & (~PAGE_MASK)) | (uv_size << PAGE_SHIFT);
-        req->src.v_addr = (req->src.v_addr & (~PAGE_MASK)) | (v_size << PAGE_SHIFT);
-
-        uv_size = (req->dst.uv_addr - (DstStart << PAGE_SHIFT)) >> PAGE_SHIFT;
-        v_size = (req->dst.v_addr - (DstStart << PAGE_SHIFT)) >> PAGE_SHIFT;
-
-        req->dst.yrgb_addr = (req->dst.yrgb_addr & (~PAGE_MASK)) | ((SrcMemSize) << PAGE_SHIFT);
-        req->dst.uv_addr = (req->dst.uv_addr & (~PAGE_MASK)) | ((SrcMemSize + uv_size) << PAGE_SHIFT);
-        req->dst.v_addr = (req->dst.v_addr & (~PAGE_MASK)) | ((SrcMemSize + v_size) << PAGE_SHIFT);
-
-        /*record the malloc buf for the cmd end to release*/
-        reg->MMU_base = MMU_Base;
-
-        /* flush data to DDR */
+
+        rga_mmu_buf_get(&rga_mmu_buf, AllSize + 16);
+        reg->MMU_len = AllSize + 16;
+
+        return status;
+
+    }
+    while(0);
+
+    return 0;
+}
+
+static int rga_mmu_info_color_fill_mode(struct rga_reg *reg, struct rga_req *req)
+{
+    int DstMemSize;
+    unsigned long DstStart;
+    struct page **pages = NULL;
+    uint32_t i;
+    uint32_t AllSize;
+    uint32_t *MMU_Base, *MMU_p, *MMU_Base_phys;
+    int ret;
+    int status;
+
+    MMU_Base = NULL;
+
+    do {
+        DstMemSize = rga_buf_size_cal(req->dst.yrgb_addr, req->dst.uv_addr, req->dst.v_addr,
+                                        req->dst.format, req->dst.vir_w, req->dst.vir_h,
+                                        &DstStart);
+        if(DstMemSize == 0) {
+            return -EINVAL;
+        }
+
+        AllSize = (DstMemSize + 15) & (~15);
+
+        pages = rga_mmu_buf.pages;
+
+        if (rga_mmu_buf_get_try(&rga_mmu_buf, AllSize + 16)) {
+            pr_err("RGA Get MMU mem failed\n");
+            status = RGA_MALLOC_ERROR;
+            break;
+        }
+
+        mutex_lock(&rga_service.lock);
+        MMU_Base = rga_mmu_buf.buf_virtual + (rga_mmu_buf.front & (rga_mmu_buf.size - 1));
+        MMU_Base_phys = rga_mmu_buf.buf + (rga_mmu_buf.front & (rga_mmu_buf.size - 1));
+        mutex_unlock(&rga_service.lock);
+
+        if (req->dst.yrgb_addr < KERNEL_SPACE_VALID) {
+            if (req->sg_dst) {
+                ret = rga_MapION(req->sg_dst, &MMU_Base[0], DstMemSize, req->line_draw_info.line_width);
+            }
+            else {
+                ret = rga_MapUserMemory(&pages[0], &MMU_Base[0], DstStart, DstMemSize);
+                if (ret < 0) {
+                    pr_err("rga map dst memory failed\n");
+                    status = ret;
+                    break;
+                }
+            }
+        }
+        else {
+            MMU_p = MMU_Base;
+            for(i=0; i<DstMemSize; i++)
+                MMU_p[i] = (uint32_t)((DstStart + i) << PAGE_SHIFT);
+        }
+
+        MMU_Base[AllSize] = MMU_Base[AllSize - 1];
+
+        /* zsq
+         * change the buf address in req struct
+         */
+
+        req->mmu_info.base_addr = ((unsigned long)(MMU_Base_phys)>>2);
+        req->dst.yrgb_addr = (req->dst.yrgb_addr & (~PAGE_MASK));
+
+        /*record the malloc buf for the cmd end to release*/
+        reg->MMU_base = MMU_Base;
+
+        /* flush data to DDR */
         rga_dma_flush_range(MMU_Base, (MMU_Base + AllSize + 1));
-
-	    rga_mmu_buf_get(&rga_mmu_buf, AllSize + 16);
-        reg->MMU_len = AllSize + 16;
-
-        return 0;
-    }
-    while(0);
-
-    return status;
-}
-
-
-static int rga_mmu_info_update_palette_table_mode(struct rga_reg *reg, struct rga_req *req)
-{
-    int SrcMemSize, CMDMemSize;
-    unsigned long SrcStart, CMDStart;
-    struct page **pages = NULL;
-    uint32_t i;
-    uint32_t AllSize;
-    uint32_t *MMU_Base, *MMU_p;
-    int ret, status;
-
-    MMU_Base = NULL;
-
-    do {
-        /* cal src buf mmu info */
-        SrcMemSize = rga_mem_size_cal(req->src.yrgb_addr, req->src.vir_w * req->src.vir_h, &SrcStart);
-        if(SrcMemSize == 0) {
-            return -EINVAL;
-        }
-
-        /* cal cmd buf mmu info */
-        CMDMemSize = rga_mem_size_cal((unsigned long)rga_service.cmd_buff, RGA_CMD_BUF_SIZE, &CMDStart);
-        if(CMDMemSize == 0) {
-            return -EINVAL;
-        }
-
-        AllSize = SrcMemSize + CMDMemSize;
-
-        pages = kzalloc(AllSize * sizeof(struct page *), GFP_KERNEL);
-        if(pages == NULL) {
-            pr_err("RGA MMU malloc pages mem failed\n");
-            status = RGA_MALLOC_ERROR;
-            break;
-        }
-
-        MMU_Base = kzalloc((AllSize + 1)* sizeof(uint32_t), GFP_KERNEL);
-        if(pages == NULL) {
-            pr_err("RGA MMU malloc MMU_Base point failed\n");
-            status = RGA_MALLOC_ERROR;
-            break;
-        }
-
-        for(i=0; i<CMDMemSize; i++) {
-            MMU_Base[i] = (uint32_t)virt_to_phys((uint32_t *)((CMDStart + i) << PAGE_SHIFT));
-        }
-
-        if (req->src.yrgb_addr < KERNEL_SPACE_VALID)
-        {
-            ret = rga_MapUserMemory(&pages[CMDMemSize], &MMU_Base[CMDMemSize], SrcStart, SrcMemSize);
-            if (ret < 0) {
-                pr_err("rga map src memory failed\n");
-                return -EINVAL;
-            }
-        }
-        else
-        {
-            MMU_p = MMU_Base + CMDMemSize;
-
-                for(i=0; i<SrcMemSize; i++)
-                {
-                    MMU_p[i] = (uint32_t)virt_to_phys((uint32_t *)((SrcStart + i) << PAGE_SHIFT));
-                }
-        }
-
-        /* zsq
-         * change the buf address in req struct
-         * for the reason of lie to MMU
-         */
-        req->mmu_info.base_addr = (virt_to_phys(MMU_Base) >> 2);
-
-        req->src.yrgb_addr = (req->src.yrgb_addr & (~PAGE_MASK)) | (CMDMemSize << PAGE_SHIFT);
-
-        /*record the malloc buf for the cmd end to release*/
-        reg->MMU_base = MMU_Base;
-
-        /* flush data to DDR */
+
+        rga_mmu_buf_get(&rga_mmu_buf, AllSize + 16);
+        reg->MMU_len = AllSize + 16;
+
+        return 0;
+    }
+    while(0);
+
+    return status;
+}
+
+
+static int rga_mmu_info_line_point_drawing_mode(struct rga_reg *reg, struct rga_req *req)
+{
+    return 0;
+}
+
+static int rga_mmu_info_blur_sharp_filter_mode(struct rga_reg *reg, struct rga_req *req)
+{
+    return 0;
+}
+
+
+
+static int rga_mmu_info_pre_scale_mode(struct rga_reg *reg, struct rga_req *req)
+{
+    int SrcMemSize, DstMemSize;
+    unsigned long SrcStart, DstStart;
+    struct page **pages = NULL;
+    uint32_t i;
+    uint32_t AllSize;
+    uint32_t *MMU_Base, *MMU_p, *MMU_Base_phys;
+    int ret;
+    int status;
+    uint32_t uv_size, v_size;
+
+    MMU_Base = NULL;
+
+    do {
+        /* cal src buf mmu info */
+        SrcMemSize = rga_buf_size_cal(req->src.yrgb_addr, req->src.uv_addr, req->src.v_addr,
+                                        req->src.format, req->src.vir_w, req->src.vir_h,
+                                        &SrcStart);
+        if(SrcMemSize == 0) {
+            return -EINVAL;
+        }
+
+        /* cal dst buf mmu info */
+        DstMemSize = rga_buf_size_cal(req->dst.yrgb_addr, req->dst.uv_addr, req->dst.v_addr,
+                                        req->dst.format, req->dst.vir_w, req->dst.vir_h,
+                                        &DstStart);
+        if(DstMemSize == 0) {
+            return -EINVAL;
+        }
+
+	    SrcMemSize = (SrcMemSize + 15) & (~15);
+	    DstMemSize = (DstMemSize + 15) & (~15);
+
+        AllSize = SrcMemSize + DstMemSize;
+
+        pages = rga_mmu_buf.pages;
+
+        if (rga_mmu_buf_get_try(&rga_mmu_buf, AllSize + 16)) {
+            pr_err("RGA Get MMU mem failed\n");
+            status = RGA_MALLOC_ERROR;
+            break;
+        }
+
+        mutex_lock(&rga_service.lock);
+        MMU_Base = rga_mmu_buf.buf_virtual + (rga_mmu_buf.front & (rga_mmu_buf.size - 1));
+        MMU_Base_phys = rga_mmu_buf.buf + (rga_mmu_buf.front & (rga_mmu_buf.size - 1));
+        mutex_unlock(&rga_service.lock);
+
+        /* map src pages */
+        if ((req->mmu_info.mmu_flag >> 8) & 1) {
+            if (req->sg_src) {
+                ret = rga_MapION(req->sg_src, &MMU_Base[0], SrcMemSize,req->line_draw_info.flag);
+            }
+            else {
+                ret = rga_MapUserMemory(&pages[0], &MMU_Base[0], SrcStart, SrcMemSize);
+                if (ret < 0) {
+                    pr_err("rga map src memory failed\n");
+                    status = ret;
+                    break;
+                }
+            }
+        }
+        else {
+            MMU_p = MMU_Base;
+
+            for(i=0; i<SrcMemSize; i++)
+                MMU_p[i] = (uint32_t)((SrcStart + i) << PAGE_SHIFT);
+        }
+
+        if((req->mmu_info.mmu_flag >> 10) & 1) {
+            if (req->sg_dst) {
+                ret = rga_MapION(req->sg_dst, &MMU_Base[SrcMemSize], DstMemSize, req->line_draw_info.line_width);
+            }
+            else {
+                ret = rga_MapUserMemory(&pages[SrcMemSize], &MMU_Base[SrcMemSize], DstStart, DstMemSize);
+                if (ret < 0) {
+                    pr_err("rga map dst memory failed\n");
+                    status = ret;
+                    break;
+                }
+            }
+        }
+        else
+        {
+            /* kernel space */
+            MMU_p = MMU_Base + SrcMemSize;
+
+            if(req->dst.yrgb_addr == (unsigned long)rga_service.pre_scale_buf) {
+                for(i=0; i<DstMemSize; i++)
+                    MMU_p[i] = rga_service.pre_scale_buf[i];
+            }
+            else {
+                for(i=0; i<DstMemSize; i++)
+                    MMU_p[i] = (uint32_t)((DstStart + i) << PAGE_SHIFT);
+            }
+        }
+
+        MMU_Base[AllSize] = MMU_Base[AllSize];
+
+        /* zsq
+         * change the buf address in req struct
+         * for the reason of lie to MMU
+         */
+
+        req->mmu_info.base_addr = ((unsigned long)(MMU_Base_phys)>>2);
+
+        uv_size = (req->src.uv_addr - (SrcStart << PAGE_SHIFT)) >> PAGE_SHIFT;
+        v_size = (req->src.v_addr - (SrcStart << PAGE_SHIFT)) >> PAGE_SHIFT;
+
+        req->src.yrgb_addr = (req->src.yrgb_addr & (~PAGE_MASK));
+        req->src.uv_addr = (req->src.uv_addr & (~PAGE_MASK)) | (uv_size << PAGE_SHIFT);
+        req->src.v_addr = (req->src.v_addr & (~PAGE_MASK)) | (v_size << PAGE_SHIFT);
+
+        uv_size = (req->dst.uv_addr - (DstStart << PAGE_SHIFT)) >> PAGE_SHIFT;
+        v_size = (req->dst.v_addr - (DstStart << PAGE_SHIFT)) >> PAGE_SHIFT;
+
+        req->dst.yrgb_addr = (req->dst.yrgb_addr & (~PAGE_MASK)) | ((SrcMemSize) << PAGE_SHIFT);
+        req->dst.uv_addr = (req->dst.uv_addr & (~PAGE_MASK)) | ((SrcMemSize + uv_size) << PAGE_SHIFT);
+        req->dst.v_addr = (req->dst.v_addr & (~PAGE_MASK)) | ((SrcMemSize + v_size) << PAGE_SHIFT);
+
+        /*record the malloc buf for the cmd end to release*/
+        reg->MMU_base = MMU_Base;
+
+        /* flush data to DDR */
+        rga_dma_flush_range(MMU_Base, (MMU_Base + AllSize + 1));
+
+	    rga_mmu_buf_get(&rga_mmu_buf, AllSize + 16);
+        reg->MMU_len = AllSize + 16;
+
+        return 0;
+    }
+    while(0);
+
+    return status;
+}
+
+
+static int rga_mmu_info_update_palette_table_mode(struct rga_reg *reg, struct rga_req *req)
+{
+    int SrcMemSize, CMDMemSize;
+    unsigned long SrcStart, CMDStart;
+    struct page **pages = NULL;
+    uint32_t i;
+    uint32_t AllSize;
+    uint32_t *MMU_Base, *MMU_p;
+    int ret, status;
+
+    MMU_Base = NULL;
+
+    do {
+        /* cal src buf mmu info */
+        SrcMemSize = rga_mem_size_cal(req->src.yrgb_addr, req->src.vir_w * req->src.vir_h, &SrcStart);
+        if(SrcMemSize == 0) {
+            return -EINVAL;
+        }
+
+        /* cal cmd buf mmu info */
+        CMDMemSize = rga_mem_size_cal((unsigned long)rga_service.cmd_buff, RGA_CMD_BUF_SIZE, &CMDStart);
+        if(CMDMemSize == 0) {
+            return -EINVAL;
+        }
+
+        AllSize = SrcMemSize + CMDMemSize;
+
+        pages = kzalloc(AllSize * sizeof(struct page *), GFP_KERNEL);
+        if(pages == NULL) {
+            pr_err("RGA MMU malloc pages mem failed\n");
+            status = RGA_MALLOC_ERROR;
+            break;
+        }
+
+        MMU_Base = kzalloc((AllSize + 1)* sizeof(uint32_t), GFP_KERNEL);
+        if(pages == NULL) {
+            pr_err("RGA MMU malloc MMU_Base point failed\n");
+            status = RGA_MALLOC_ERROR;
+            break;
+        }
+
+        for(i=0; i<CMDMemSize; i++) {
+            MMU_Base[i] = (uint32_t)virt_to_phys((uint32_t *)((CMDStart + i) << PAGE_SHIFT));
+        }
+
+        if (req->src.yrgb_addr < KERNEL_SPACE_VALID)
+        {
+            ret = rga_MapUserMemory(&pages[CMDMemSize], &MMU_Base[CMDMemSize], SrcStart, SrcMemSize);
+            if (ret < 0) {
+                pr_err("rga map src memory failed\n");
+                return -EINVAL;
+            }
+        }
+        else
+        {
+            MMU_p = MMU_Base + CMDMemSize;
+
+                for(i=0; i<SrcMemSize; i++)
+                {
+                    MMU_p[i] = (uint32_t)virt_to_phys((uint32_t *)((SrcStart + i) << PAGE_SHIFT));
+                }
+        }
+
+        /* zsq
+         * change the buf address in req struct
+         * for the reason of lie to MMU
+         */
+        req->mmu_info.base_addr = (virt_to_phys(MMU_Base) >> 2);
+
+        req->src.yrgb_addr = (req->src.yrgb_addr & (~PAGE_MASK)) | (CMDMemSize << PAGE_SHIFT);
+
+        /*record the malloc buf for the cmd end to release*/
+        reg->MMU_base = MMU_Base;
+
+        /* flush data to DDR */
         rga_dma_flush_range(MMU_Base, (MMU_Base + AllSize));
-
-
-        if (pages != NULL) {
-            /* Free the page table */
-            kfree(pages);
-        }
-
-        return 0;
-    }
-    while(0);
-
-    if (pages != NULL)
-        kfree(pages);
-
-    if (MMU_Base != NULL)
-        kfree(MMU_Base);
-
-    return status;
-}
-
-static int rga_mmu_info_update_patten_buff_mode(struct rga_reg *reg, struct rga_req *req)
-{
-    int SrcMemSize, CMDMemSize;
-    unsigned long SrcStart, CMDStart;
-    struct page **pages = NULL;
-    uint32_t i;
-    uint32_t AllSize;
-    uint32_t *MMU_Base, *MMU_p;
-    int ret, status;
-
-    MMU_Base = MMU_p = 0;
-
-    do
-    {
-
-        /* cal src buf mmu info */
-        SrcMemSize = rga_mem_size_cal(req->pat.yrgb_addr, req->pat.vir_w * req->pat.vir_h * 4, &SrcStart);
-        if(SrcMemSize == 0) {
-            return -EINVAL;
-        }
-
-        /* cal cmd buf mmu info */
-        CMDMemSize = rga_mem_size_cal((unsigned long)rga_service.cmd_buff, RGA_CMD_BUF_SIZE, &CMDStart);
-        if(CMDMemSize == 0) {
-            return -EINVAL;
-        }
-
-        AllSize = SrcMemSize + CMDMemSize;
-
-        pages = kzalloc(AllSize * sizeof(struct page *), GFP_KERNEL);
-        if(pages == NULL) {
-            pr_err("RGA MMU malloc pages mem failed\n");
-            status = RGA_MALLOC_ERROR;
-            break;
-        }
-
-        MMU_Base = kzalloc(AllSize * sizeof(uint32_t), GFP_KERNEL);
-        if(MMU_Base == NULL) {
-            pr_err("RGA MMU malloc MMU_Base point failed\n");
-            status = RGA_MALLOC_ERROR;
-            break;
-        }
-
-        for(i=0; i<CMDMemSize; i++) {
-            MMU_Base[i] = virt_to_phys((uint32_t *)((CMDStart + i) << PAGE_SHIFT));
-        }
-
-        if (req->src.yrgb_addr < KERNEL_SPACE_VALID)
-        {
-            ret = rga_MapUserMemory(&pages[CMDMemSize], &MMU_Base[CMDMemSize], SrcStart, SrcMemSize);
-            if (ret < 0) {
-                pr_err("rga map src memory failed\n");
-                status = ret;
-                break;
-            }
-        }
-        else
-        {
-            MMU_p = MMU_Base + CMDMemSize;
-
-            for(i=0; i<SrcMemSize; i++)
-            {
-                MMU_p[i] = (uint32_t)virt_to_phys((uint32_t *)((SrcStart + i) << PAGE_SHIFT));
-            }
-        }
-
-        /* zsq
-         * change the buf address in req struct
-         * for the reason of lie to MMU
-         */
-        req->mmu_info.base_addr = (virt_to_phys(MMU_Base) >> 2);
-
-        req->src.yrgb_addr = (req->src.yrgb_addr & (~PAGE_MASK)) | (CMDMemSize << PAGE_SHIFT);
-
-        /*record the malloc buf for the cmd end to release*/
-        reg->MMU_base = MMU_Base;
-
-        /* flush data to DDR */
+
+
+        if (pages != NULL) {
+            /* Free the page table */
+            kfree(pages);
+        }
+
+        return 0;
+    }
+    while(0);
+
+    if (pages != NULL)
+        kfree(pages);
+
+    if (MMU_Base != NULL)
+        kfree(MMU_Base);
+
+    return status;
+}
+
+static int rga_mmu_info_update_patten_buff_mode(struct rga_reg *reg, struct rga_req *req)
+{
+    int SrcMemSize, CMDMemSize;
+    unsigned long SrcStart, CMDStart;
+    struct page **pages = NULL;
+    uint32_t i;
+    uint32_t AllSize;
+    uint32_t *MMU_Base, *MMU_p;
+    int ret, status;
+
+    MMU_Base = MMU_p = 0;
+
+    do
+    {
+
+        /* cal src buf mmu info */
+        SrcMemSize = rga_mem_size_cal(req->pat.yrgb_addr, req->pat.vir_w * req->pat.vir_h * 4, &SrcStart);
+        if(SrcMemSize == 0) {
+            return -EINVAL;
+        }
+
+        /* cal cmd buf mmu info */
+        CMDMemSize = rga_mem_size_cal((unsigned long)rga_service.cmd_buff, RGA_CMD_BUF_SIZE, &CMDStart);
+        if(CMDMemSize == 0) {
+            return -EINVAL;
+        }
+
+        AllSize = SrcMemSize + CMDMemSize;
+
+        pages = kzalloc(AllSize * sizeof(struct page *), GFP_KERNEL);
+        if(pages == NULL) {
+            pr_err("RGA MMU malloc pages mem failed\n");
+            status = RGA_MALLOC_ERROR;
+            break;
+        }
+
+        MMU_Base = kzalloc(AllSize * sizeof(uint32_t), GFP_KERNEL);
+        if(MMU_Base == NULL) {
+            pr_err("RGA MMU malloc MMU_Base point failed\n");
+            status = RGA_MALLOC_ERROR;
+            break;
+        }
+
+        for(i=0; i<CMDMemSize; i++) {
+            MMU_Base[i] = virt_to_phys((uint32_t *)((CMDStart + i) << PAGE_SHIFT));
+        }
+
+        if (req->src.yrgb_addr < KERNEL_SPACE_VALID)
+        {
+            ret = rga_MapUserMemory(&pages[CMDMemSize], &MMU_Base[CMDMemSize], SrcStart, SrcMemSize);
+            if (ret < 0) {
+                pr_err("rga map src memory failed\n");
+                status = ret;
+                break;
+            }
+        }
+        else
+        {
+            MMU_p = MMU_Base + CMDMemSize;
+
+            for(i=0; i<SrcMemSize; i++)
+            {
+                MMU_p[i] = (uint32_t)virt_to_phys((uint32_t *)((SrcStart + i) << PAGE_SHIFT));
+            }
+        }
+
+        /* zsq
+         * change the buf address in req struct
+         * for the reason of lie to MMU
+         */
+        req->mmu_info.base_addr = (virt_to_phys(MMU_Base) >> 2);
+
+        req->src.yrgb_addr = (req->src.yrgb_addr & (~PAGE_MASK)) | (CMDMemSize << PAGE_SHIFT);
+
+        /*record the malloc buf for the cmd end to release*/
+        reg->MMU_base = MMU_Base;
+
+        /* flush data to DDR */
         rga_dma_flush_range(MMU_Base, (MMU_Base + AllSize));
-
-        if (pages != NULL) {
-            /* Free the page table */
-            kfree(pages);
-        }
-
-        return 0;
-
-    }
-    while(0);
-
-    if (pages != NULL)
-        kfree(pages);
-
-    if (MMU_Base != NULL)
-        kfree(MMU_Base);
-
-    return status;
-}
-
-int rga_set_mmu_info(struct rga_reg *reg, struct rga_req *req)
-{
-    int ret;
-
-    switch (req->render_mode) {
-        case bitblt_mode :
-            ret = rga_mmu_info_BitBlt_mode(reg, req);
-            break;
-        case color_palette_mode :
-            ret = rga_mmu_info_color_palette_mode(reg, req);
-            break;
-        case color_fill_mode :
-            ret = rga_mmu_info_color_fill_mode(reg, req);
-            break;
-        case line_point_drawing_mode :
-            ret = rga_mmu_info_line_point_drawing_mode(reg, req);
-            break;
-        case blur_sharp_filter_mode :
-            ret = rga_mmu_info_blur_sharp_filter_mode(reg, req);
-            break;
-        case pre_scaling_mode :
-            ret = rga_mmu_info_pre_scale_mode(reg, req);
-            break;
-        case update_palette_table_mode :
-            ret = rga_mmu_info_update_palette_table_mode(reg, req);
-            break;
-        case update_patten_buff_mode :
-            ret = rga_mmu_info_update_patten_buff_mode(reg, req);
-            break;
-        default :
-            ret = -1;
-            break;
-    }
-
-    return ret;
-}
-
+
+        if (pages != NULL) {
+            /* Free the page table */
+            kfree(pages);
+        }
+
+        return 0;
+
+    }
+    while(0);
+
+    if (pages != NULL)
+        kfree(pages);
+
+    if (MMU_Base != NULL)
+        kfree(MMU_Base);
+
+    return status;
+}
+
+int rga_set_mmu_info(struct rga_reg *reg, struct rga_req *req)
+{
+    int ret;
+
+    switch (req->render_mode) {
+        case bitblt_mode :
+            ret = rga_mmu_info_BitBlt_mode(reg, req);
+            break;
+        case color_palette_mode :
+            ret = rga_mmu_info_color_palette_mode(reg, req);
+            break;
+        case color_fill_mode :
+            ret = rga_mmu_info_color_fill_mode(reg, req);
+            break;
+        case line_point_drawing_mode :
+            ret = rga_mmu_info_line_point_drawing_mode(reg, req);
+            break;
+        case blur_sharp_filter_mode :
+            ret = rga_mmu_info_blur_sharp_filter_mode(reg, req);
+            break;
+        case pre_scaling_mode :
+            ret = rga_mmu_info_pre_scale_mode(reg, req);
+            break;
+        case update_palette_table_mode :
+            ret = rga_mmu_info_update_palette_table_mode(reg, req);
+            break;
+        case update_patten_buff_mode :
+            ret = rga_mmu_info_update_patten_buff_mode(reg, req);
+            break;
+        default :
+            ret = -1;
+            break;
+    }
+
+    return ret;
+}
+
diff --git a/drivers/video/rockchip/rga/rga_mmu_info.h b/drivers/video/rockchip/rga/rga_mmu_info.h
index 3e70894c7ee7..502f6594c29d 100644
--- a/drivers/video/rockchip/rga/rga_mmu_info.h
+++ b/drivers/video/rockchip/rga/rga_mmu_info.h
@@ -1,24 +1,24 @@
 /* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __RGA_MMU_INFO_H__
-#define __RGA_MMU_INFO_H__
-
+#ifndef __RGA_MMU_INFO_H__
+#define __RGA_MMU_INFO_H__
+
 #include "rga.h"
 #include "RGA_API.h"
-
-#ifndef MIN
-#define MIN(X, Y)           ((X)<(Y)?(X):(Y))
-#endif
-
-#ifndef MAX
-#define MAX(X, Y)           ((X)>(Y)?(X):(Y))
-#endif
 
-extern struct rga_drvdata *drvdata;
+#ifndef MIN
+#define MIN(X, Y)           ((X)<(Y)?(X):(Y))
+#endif
+
+#ifndef MAX
+#define MAX(X, Y)           ((X)>(Y)?(X):(Y))
+#endif
+
+extern struct rga_drvdata *rga_drvdata;
 
 void rga_dma_flush_range(void *pstart, void *pend);
-int rga_set_mmu_info(struct rga_reg *reg, struct rga_req *req);
-
-
-#endif
-
-
+int rga_set_mmu_info(struct rga_reg *reg, struct rga_req *req);
+
+
+#endif
+
+
diff --git a/drivers/video/rockchip/rga/rga_reg_info.c b/drivers/video/rockchip/rga/rga_reg_info.c
index 94a6305b870b..563eaab7bb9a 100644
--- a/drivers/video/rockchip/rga/rga_reg_info.c
+++ b/drivers/video/rockchip/rga/rga_reg_info.c
@@ -1,708 +1,708 @@
 /* SPDX-License-Identifier: GPL-2.0 */
-
-//#include <linux/kernel.h>
-#include <linux/memory.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/platform_device.h>
-#include <linux/sched.h>
-#include <linux/mutex.h>
-#include <linux/err.h>
-#include <linux/clk.h>
-#include <asm/delay.h>
-#include <linux/dma-mapping.h>
-#include <linux/delay.h>
-#include <asm/io.h>
-#include <linux/irq.h>
-#include <linux/interrupt.h>
-//#include <mach/io.h>
-//#include <mach/irqs.h>
-#include <linux/fs.h>
-#include <linux/uaccess.h>
-#include <linux/miscdevice.h>
-#include <linux/poll.h>
-#include <linux/delay.h>
-#include <linux/wait.h>
-#include <linux/syscalls.h>
-#include <linux/timer.h>
-#include <linux/time.h>
-#include <asm/cacheflush.h>
-#include <linux/slab.h>
-#include <linux/fb.h>
-#include <linux/wakelock.h>
+
+//#include <linux/kernel.h>
+#include <linux/memory.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/sched.h>
+#include <linux/mutex.h>
+#include <linux/err.h>
+#include <linux/clk.h>
+#include <asm/delay.h>
+#include <linux/dma-mapping.h>
+#include <linux/delay.h>
+#include <asm/io.h>
+#include <linux/irq.h>
+#include <linux/interrupt.h>
+//#include <mach/io.h>
+//#include <mach/irqs.h>
+#include <linux/fs.h>
+#include <linux/uaccess.h>
+#include <linux/miscdevice.h>
+#include <linux/poll.h>
+#include <linux/delay.h>
+#include <linux/wait.h>
+#include <linux/syscalls.h>
+#include <linux/timer.h>
+#include <linux/time.h>
+#include <asm/cacheflush.h>
+#include <linux/slab.h>
+#include <linux/fb.h>
+#include <linux/wakelock.h>
 #include <linux/version.h>
-
-#include "rga_reg_info.h"
-#include "rga_rop.h"
-#include "rga.h"
-
-
-/*************************************************************
-Func:
-    RGA_pixel_width_init
-Description:
-    select pixel_width form data format
-Author:
-    ZhangShengqin
-Date:
-    20012-2-2 10:59:25
-**************************************************************/
-unsigned char
-RGA_pixel_width_init(unsigned int format)
-{
-    unsigned char pixel_width;
-
-    pixel_width = 0;
-
-    switch(format)
-    {
-        /* RGB FORMAT */
-        case RK_FORMAT_RGBA_8888 :   pixel_width = 4;   break;
-        case RK_FORMAT_RGBX_8888 :   pixel_width = 4;   break;
-        case RK_FORMAT_RGB_888   :   pixel_width = 3;   break;
-        case RK_FORMAT_BGRA_8888 :   pixel_width = 4;   break;
-        case RK_FORMAT_RGB_565   :   pixel_width = 2;   break;
-        case RK_FORMAT_RGBA_5551 :   pixel_width = 2;   break;
-        case RK_FORMAT_RGBA_4444 :   pixel_width = 2;   break;
-        case RK_FORMAT_BGR_888   :   pixel_width = 3;   break;
-
-        /* YUV FORMAT */
-        case RK_FORMAT_YCbCr_422_SP :   pixel_width = 1;  break;
-        case RK_FORMAT_YCbCr_422_P  :   pixel_width = 1;  break;
-        case RK_FORMAT_YCbCr_420_SP :   pixel_width = 1;  break;
-        case RK_FORMAT_YCbCr_420_P  :   pixel_width = 1;  break;
-        case RK_FORMAT_YCrCb_422_SP :   pixel_width = 1;  break;
-        case RK_FORMAT_YCrCb_422_P  :   pixel_width = 1;  break;
-        case RK_FORMAT_YCrCb_420_SP :   pixel_width = 1;  break;
-        case RK_FORMAT_YCrCb_420_P :    pixel_width = 1;  break;
-        //case default :                  pixel_width = 0;  break;
-    }
-
-    return pixel_width;
-}
-
-/*************************************************************
-Func:
-    dst_ctrl_cal
-Description:
-    calculate dst act window position / width / height
-    and set the tile struct
-Author:
-    ZhangShengqin
-Date:
-    20012-2-2 10:59:25
-**************************************************************/
+
+#include "rga_reg_info.h"
+#include "rga_rop.h"
+#include "rga.h"
+
+
+/*************************************************************
+Func:
+    RGA_pixel_width_init
+Description:
+    select pixel_width form data format
+Author:
+    ZhangShengqin
+Date:
+    20012-2-2 10:59:25
+**************************************************************/
+unsigned char
+RGA_pixel_width_init(unsigned int format)
+{
+    unsigned char pixel_width;
+
+    pixel_width = 0;
+
+    switch(format)
+    {
+        /* RGB FORMAT */
+        case RK_FORMAT_RGBA_8888 :   pixel_width = 4;   break;
+        case RK_FORMAT_RGBX_8888 :   pixel_width = 4;   break;
+        case RK_FORMAT_RGB_888   :   pixel_width = 3;   break;
+        case RK_FORMAT_BGRA_8888 :   pixel_width = 4;   break;
+        case RK_FORMAT_RGB_565   :   pixel_width = 2;   break;
+        case RK_FORMAT_RGBA_5551 :   pixel_width = 2;   break;
+        case RK_FORMAT_RGBA_4444 :   pixel_width = 2;   break;
+        case RK_FORMAT_BGR_888   :   pixel_width = 3;   break;
+
+        /* YUV FORMAT */
+        case RK_FORMAT_YCbCr_422_SP :   pixel_width = 1;  break;
+        case RK_FORMAT_YCbCr_422_P  :   pixel_width = 1;  break;
+        case RK_FORMAT_YCbCr_420_SP :   pixel_width = 1;  break;
+        case RK_FORMAT_YCbCr_420_P  :   pixel_width = 1;  break;
+        case RK_FORMAT_YCrCb_422_SP :   pixel_width = 1;  break;
+        case RK_FORMAT_YCrCb_422_P  :   pixel_width = 1;  break;
+        case RK_FORMAT_YCrCb_420_SP :   pixel_width = 1;  break;
+        case RK_FORMAT_YCrCb_420_P :    pixel_width = 1;  break;
+        //case default :                  pixel_width = 0;  break;
+    }
+
+    return pixel_width;
+}
+
+/*************************************************************
+Func:
+    dst_ctrl_cal
+Description:
+    calculate dst act window position / width / height
+    and set the tile struct
+Author:
+    ZhangShengqin
+Date:
+    20012-2-2 10:59:25
+**************************************************************/
 static void
-dst_ctrl_cal(const struct rga_req *msg, TILE_INFO *tile)
-{
-    u32 width   = msg->dst.act_w;
-    u32 height  = msg->dst.act_h;
-    s32 xoff    = msg->dst.x_offset;
-    s32 yoff    = msg->dst.y_offset;
-
-    s32 x0, y0, x1, y1, x2, y2;
-    s32 x00,y00,x10,y10,x20,y20;
-    s32 xx, xy, yx, yy;
-    s32 pos[8];
-
-    s32 xmax, xmin, ymax, ymin;
-
-    s32 sina = msg->sina; /* 16.16 */
-    s32 cosa = msg->cosa; /* 16.16 */
-
-    xmax = xmin = ymax = ymin = 0;
-
-    if((msg->rotate_mode == 0)||(msg->rotate_mode == 2)||(msg->rotate_mode == 3))
-    {
-        pos[0] = xoff;
-        pos[1] = yoff;
-
-        pos[2] = xoff;
-        pos[3] = yoff + height - 1;
-
-        pos[4] = xoff + width - 1;
-        pos[5] = yoff + height - 1;
-
-        pos[6] = xoff + width - 1;
-        pos[7] = yoff;
-
-        xmax = MIN(MAX(MAX(MAX(pos[0], pos[2]), pos[4]), pos[6]), msg->clip.xmax);
-        xmin = MAX(MIN(MIN(MIN(pos[0], pos[2]), pos[4]), pos[6]), msg->clip.xmin);
-
-        ymax = MIN(MAX(MAX(MAX(pos[1], pos[3]), pos[5]), pos[7]), msg->clip.ymax);
-        ymin = MAX(MIN(MIN(MIN(pos[1], pos[3]), pos[5]), pos[7]), msg->clip.ymin);
-
-        //printk("xmax = %d, xmin = %d, ymin = %d, ymax = %d\n", xmax, xmin, ymin, ymax);
-    }
-    else if(msg->rotate_mode == 1)
-    {
-        if((sina == 0) || (cosa == 0))
-        {
-            if((sina == 0) && (cosa == -65536))
-            {
-                /* 180 */
-                pos[0] = xoff - width + 1;
-                pos[1] = yoff - height + 1;
-
-                pos[2] = xoff - width  + 1;
-                pos[3] = yoff;
-
-                pos[4] = xoff;
-                pos[5] = yoff;
-
-                pos[6] = xoff;
-                pos[7] = yoff - height + 1;
-            }
-            else if((cosa == 0)&&(sina == 65536))
-            {
-                /* 90 */
-                pos[0] = xoff - height + 1;
-                pos[1] = yoff;
-
-                pos[2] = xoff - height + 1;
-                pos[3] = yoff + width - 1;
-
-                pos[4] = xoff;
-                pos[5] = yoff + width - 1;
-
-                pos[6] = xoff;
-                pos[7] = yoff;
-            }
-            else if((cosa == 0)&&(sina == -65536))
-            {
-                /* 270 */
-                pos[0] = xoff;
-                pos[1] = yoff - width + 1;
-
-                pos[2] = xoff;
-                pos[3] = yoff;
-
-                pos[4] = xoff + height - 1;
-                pos[5] = yoff;
-
-                pos[6] = xoff + height - 1;
-                pos[7] = yoff - width + 1;
-            }
-            else
-            {
-                /* 0 */
-                pos[0] = xoff;
-                pos[1] = yoff;
-
-                pos[2] = xoff;
-                pos[3] = yoff + height - 1;
-
-                pos[4] = xoff + width - 1;
-                pos[5] = yoff + height - 1;
-
-                pos[6] = xoff + width - 1;
-                pos[7] = yoff;
-            }
-
-            xmax = MIN(MAX(MAX(MAX(pos[0], pos[2]), pos[4]), pos[6]), msg->clip.xmax);
-            xmin = MAX(MIN(MIN(MIN(pos[0], pos[2]), pos[4]), pos[6]), msg->clip.xmin);
-
-            ymax = MIN(MAX(MAX(MAX(pos[1], pos[3]), pos[5]), pos[7]), msg->clip.ymax);
-            ymin = MAX(MIN(MIN(MIN(pos[1], pos[3]), pos[5]), pos[7]), msg->clip.ymin);
-        }
-        else
-        {
-            xx = msg->cosa;
-            xy = msg->sina;
-            yx = xy;
-            yy = xx;
-
-            x0 = width + xoff;
-            y0 = yoff;
-
-            x1 = xoff;
-            y1 = height + yoff;
-
-            x2 = width + xoff;
-            y2 = height + yoff;
-
-            pos[0] = xoff;
-            pos[1] = yoff;
-
-            pos[2] = x00 = (((x0 - xoff)*xx - (y0 - yoff)*xy)>>16) + xoff;
-            pos[3] = y00 = (((x0 - xoff)*yx + (y0 - yoff)*yy)>>16) + yoff;
-
-            pos[4] = x10 = (((x1 - xoff)*xx - (y1 - yoff)*xy)>>16) + xoff;
-            pos[5] = y10 = (((x1 - xoff)*yx + (y1 - yoff)*yy)>>16) + yoff;
-
-            pos[6] = x20 = (((x2 - xoff)*xx - (y2 - yoff)*xy)>>16) + xoff;
-            pos[7] = y20 = (((x2 - xoff)*yx + (y2 - yoff)*yy)>>16) + yoff;
-
-            xmax = MAX(MAX(MAX(x00, xoff), x10), x20) + 2;
-            xmin = MIN(MIN(MIN(x00, xoff), x10), x20) - 1;
-
-            ymax = MAX(MAX(MAX(y00, yoff), y10), y20) + 2;
-            ymin = MIN(MIN(MIN(y00, yoff), y10), y20) - 1;
-
-            xmax = MIN(xmax, msg->clip.xmax);
-            xmin = MAX(xmin, msg->clip.xmin);
-
-            ymax = MIN(ymax, msg->clip.ymax);
-            ymin = MAX(ymin, msg->clip.ymin);
-
-            //printk("xmin = %d, xmax = %d, ymin = %d, ymax = %d\n", xmin, xmax, ymin, ymax);
-        }
-    }
-
-    if ((xmax < xmin) || (ymax < ymin)) {
-        xmin = xmax;
-        ymin = ymax;
-    }
-
-    if ((xmin >= msg->dst.vir_w)||(xmax < 0)||(ymin >= msg->dst.vir_h)||(ymax < 0)) {
-        xmin = xmax = ymin = ymax = 0;
-    }
-
-    //printk("xmin = %d, xmax = %d, ymin = %d, ymax = %d\n", xmin, xmax, ymin, ymax);
-
-    tile->dst_ctrl.w = (xmax - xmin);
-    tile->dst_ctrl.h = (ymax - ymin);
-    tile->dst_ctrl.x_off = xmin;
-    tile->dst_ctrl.y_off = ymin;
-
-    //printk("tile->dst_ctrl.w = %x, tile->dst_ctrl.h = %x\n", tile->dst_ctrl.w, tile->dst_ctrl.h);
-
-    tile->tile_x_num = (xmax - xmin + 1 + 7)>>3;
-    tile->tile_y_num = (ymax - ymin + 1 + 7)>>3;
-
-    tile->dst_x_tmp = xmin - msg->dst.x_offset;
-    tile->dst_y_tmp = ymin - msg->dst.y_offset;
-}
-
-/*************************************************************
-Func:
-    src_tile_info_cal
-Description:
-    calculate src remap window position / width / height
-    and set the tile struct
-Author:
-    ZhangShengqin
-Date:
-    20012-2-2 10:59:25
-**************************************************************/
-
+dst_ctrl_cal(const struct rga_req *msg, TILE_INFO *tile)
+{
+    u32 width   = msg->dst.act_w;
+    u32 height  = msg->dst.act_h;
+    s32 xoff    = msg->dst.x_offset;
+    s32 yoff    = msg->dst.y_offset;
+
+    s32 x0, y0, x1, y1, x2, y2;
+    s32 x00,y00,x10,y10,x20,y20;
+    s32 xx, xy, yx, yy;
+    s32 pos[8];
+
+    s32 xmax, xmin, ymax, ymin;
+
+    s32 sina = msg->sina; /* 16.16 */
+    s32 cosa = msg->cosa; /* 16.16 */
+
+    xmax = xmin = ymax = ymin = 0;
+
+    if((msg->rotate_mode == 0)||(msg->rotate_mode == 2)||(msg->rotate_mode == 3))
+    {
+        pos[0] = xoff;
+        pos[1] = yoff;
+
+        pos[2] = xoff;
+        pos[3] = yoff + height - 1;
+
+        pos[4] = xoff + width - 1;
+        pos[5] = yoff + height - 1;
+
+        pos[6] = xoff + width - 1;
+        pos[7] = yoff;
+
+        xmax = MIN(MAX(MAX(MAX(pos[0], pos[2]), pos[4]), pos[6]), msg->clip.xmax);
+        xmin = MAX(MIN(MIN(MIN(pos[0], pos[2]), pos[4]), pos[6]), msg->clip.xmin);
+
+        ymax = MIN(MAX(MAX(MAX(pos[1], pos[3]), pos[5]), pos[7]), msg->clip.ymax);
+        ymin = MAX(MIN(MIN(MIN(pos[1], pos[3]), pos[5]), pos[7]), msg->clip.ymin);
+
+        //printk("xmax = %d, xmin = %d, ymin = %d, ymax = %d\n", xmax, xmin, ymin, ymax);
+    }
+    else if(msg->rotate_mode == 1)
+    {
+        if((sina == 0) || (cosa == 0))
+        {
+            if((sina == 0) && (cosa == -65536))
+            {
+                /* 180 */
+                pos[0] = xoff - width + 1;
+                pos[1] = yoff - height + 1;
+
+                pos[2] = xoff - width  + 1;
+                pos[3] = yoff;
+
+                pos[4] = xoff;
+                pos[5] = yoff;
+
+                pos[6] = xoff;
+                pos[7] = yoff - height + 1;
+            }
+            else if((cosa == 0)&&(sina == 65536))
+            {
+                /* 90 */
+                pos[0] = xoff - height + 1;
+                pos[1] = yoff;
+
+                pos[2] = xoff - height + 1;
+                pos[3] = yoff + width - 1;
+
+                pos[4] = xoff;
+                pos[5] = yoff + width - 1;
+
+                pos[6] = xoff;
+                pos[7] = yoff;
+            }
+            else if((cosa == 0)&&(sina == -65536))
+            {
+                /* 270 */
+                pos[0] = xoff;
+                pos[1] = yoff - width + 1;
+
+                pos[2] = xoff;
+                pos[3] = yoff;
+
+                pos[4] = xoff + height - 1;
+                pos[5] = yoff;
+
+                pos[6] = xoff + height - 1;
+                pos[7] = yoff - width + 1;
+            }
+            else
+            {
+                /* 0 */
+                pos[0] = xoff;
+                pos[1] = yoff;
+
+                pos[2] = xoff;
+                pos[3] = yoff + height - 1;
+
+                pos[4] = xoff + width - 1;
+                pos[5] = yoff + height - 1;
+
+                pos[6] = xoff + width - 1;
+                pos[7] = yoff;
+            }
+
+            xmax = MIN(MAX(MAX(MAX(pos[0], pos[2]), pos[4]), pos[6]), msg->clip.xmax);
+            xmin = MAX(MIN(MIN(MIN(pos[0], pos[2]), pos[4]), pos[6]), msg->clip.xmin);
+
+            ymax = MIN(MAX(MAX(MAX(pos[1], pos[3]), pos[5]), pos[7]), msg->clip.ymax);
+            ymin = MAX(MIN(MIN(MIN(pos[1], pos[3]), pos[5]), pos[7]), msg->clip.ymin);
+        }
+        else
+        {
+            xx = msg->cosa;
+            xy = msg->sina;
+            yx = xy;
+            yy = xx;
+
+            x0 = width + xoff;
+            y0 = yoff;
+
+            x1 = xoff;
+            y1 = height + yoff;
+
+            x2 = width + xoff;
+            y2 = height + yoff;
+
+            pos[0] = xoff;
+            pos[1] = yoff;
+
+            pos[2] = x00 = (((x0 - xoff)*xx - (y0 - yoff)*xy)>>16) + xoff;
+            pos[3] = y00 = (((x0 - xoff)*yx + (y0 - yoff)*yy)>>16) + yoff;
+
+            pos[4] = x10 = (((x1 - xoff)*xx - (y1 - yoff)*xy)>>16) + xoff;
+            pos[5] = y10 = (((x1 - xoff)*yx + (y1 - yoff)*yy)>>16) + yoff;
+
+            pos[6] = x20 = (((x2 - xoff)*xx - (y2 - yoff)*xy)>>16) + xoff;
+            pos[7] = y20 = (((x2 - xoff)*yx + (y2 - yoff)*yy)>>16) + yoff;
+
+            xmax = MAX(MAX(MAX(x00, xoff), x10), x20) + 2;
+            xmin = MIN(MIN(MIN(x00, xoff), x10), x20) - 1;
+
+            ymax = MAX(MAX(MAX(y00, yoff), y10), y20) + 2;
+            ymin = MIN(MIN(MIN(y00, yoff), y10), y20) - 1;
+
+            xmax = MIN(xmax, msg->clip.xmax);
+            xmin = MAX(xmin, msg->clip.xmin);
+
+            ymax = MIN(ymax, msg->clip.ymax);
+            ymin = MAX(ymin, msg->clip.ymin);
+
+            //printk("xmin = %d, xmax = %d, ymin = %d, ymax = %d\n", xmin, xmax, ymin, ymax);
+        }
+    }
+
+    if ((xmax < xmin) || (ymax < ymin)) {
+        xmin = xmax;
+        ymin = ymax;
+    }
+
+    if ((xmin >= msg->dst.vir_w)||(xmax < 0)||(ymin >= msg->dst.vir_h)||(ymax < 0)) {
+        xmin = xmax = ymin = ymax = 0;
+    }
+
+    //printk("xmin = %d, xmax = %d, ymin = %d, ymax = %d\n", xmin, xmax, ymin, ymax);
+
+    tile->dst_ctrl.w = (xmax - xmin);
+    tile->dst_ctrl.h = (ymax - ymin);
+    tile->dst_ctrl.x_off = xmin;
+    tile->dst_ctrl.y_off = ymin;
+
+    //printk("tile->dst_ctrl.w = %x, tile->dst_ctrl.h = %x\n", tile->dst_ctrl.w, tile->dst_ctrl.h);
+
+    tile->tile_x_num = (xmax - xmin + 1 + 7)>>3;
+    tile->tile_y_num = (ymax - ymin + 1 + 7)>>3;
+
+    tile->dst_x_tmp = xmin - msg->dst.x_offset;
+    tile->dst_y_tmp = ymin - msg->dst.y_offset;
+}
+
+/*************************************************************
+Func:
+    src_tile_info_cal
+Description:
+    calculate src remap window position / width / height
+    and set the tile struct
+Author:
+    ZhangShengqin
+Date:
+    20012-2-2 10:59:25
+**************************************************************/
+
 static void
-src_tile_info_cal(const struct rga_req *msg, TILE_INFO *tile)
-{
-    s32 x0, x1, x2, x3, y0, y1, y2, y3;
-
-    int64_t xx, xy, yx, yy;
-
-    int64_t pos[8];
-    int64_t epos[8];
-
-    int64_t x_dx, x_dy, y_dx, y_dy;
-    int64_t x_temp_start, y_temp_start;
-    int64_t xmax, xmin, ymax, ymin;
-
-    int64_t t_xoff, t_yoff;
-
-    xx = tile->matrix[0]; /* 32.32 */
-    xy = tile->matrix[1]; /* 32.32 */
-    yx = tile->matrix[2]; /* 32.32 */
-    yy = tile->matrix[3]; /* 32.32 */
-
-    if(msg->rotate_mode == 1)
-    {
-        x0 = tile->dst_x_tmp;
-        y0 = tile->dst_y_tmp;
-
-        x1 = x0;
-        y1 = y0 + 8;
-
-        x2 = x0 + 8;
-        y2 = y0 + 8;
-
-        x3 = x0 + 8;
-        y3 = y0;
-
-        pos[0] = (x0*xx + y0*yx);
-        pos[1] = (x0*xy + y0*yy);
-
-        pos[2] = (x1*xx + y1*yx);
-        pos[3] = (x1*xy + y1*yy);
-
-        pos[4] = (x2*xx + y2*yx);
-        pos[5] = (x2*xy + y2*yy);
-
-        pos[6] = (x3*xx + y3*yx);
-        pos[7] = (x3*xy + y3*yy);
-
-        y1 = y0 + 7;
-        x2 = x0 + 7;
-        y2 = y0 + 7;
-        x3 = x0 + 7;
-
-        epos[0] = pos[0];
-        epos[1] = pos[1];
-
-        epos[2] = (x1*xx + y1*yx);
-        epos[3] = (x1*xy + y1*yy);
-
-        epos[4] = (x2*xx + y2*yx);
-        epos[5] = (x2*xy + y2*yy);
-
-        epos[6] = (x3*xx + y3*yx);
-        epos[7] = (x3*xy + y3*yy);
-
-        x_dx = pos[6] - pos[0];
-        x_dy = pos[7] - pos[1];
-
-        y_dx = pos[2] - pos[0];
-        y_dy = pos[3] - pos[1];
-
-        tile->x_dx = (s32)(x_dx >> 22 );
-        tile->x_dy = (s32)(x_dy >> 22 );
-        tile->y_dx = (s32)(y_dx >> 22 );
-        tile->y_dy = (s32)(y_dy >> 22 );
-
-        x_temp_start = x0*xx + y0*yx;
-        y_temp_start = x0*xy + y0*yy;
-
-        xmax = (MAX(MAX(MAX(epos[0], epos[2]), epos[4]), epos[6]));
-        xmin = (MIN(MIN(MIN(epos[0], epos[2]), epos[4]), epos[6]));
-
-        ymax = (MAX(MAX(MAX(epos[1], epos[3]), epos[5]), epos[7]));
-        ymin = (MIN(MIN(MIN(epos[1], epos[3]), epos[5]), epos[7]));
-
-        t_xoff = (x_temp_start - xmin)>>18;
-        t_yoff = (y_temp_start - ymin)>>18;
-
-        tile->tile_xoff = (s32)t_xoff;
-        tile->tile_yoff = (s32)t_yoff;
-
-        tile->tile_w = (u16)((xmax - xmin)>>21); //.11
-        tile->tile_h = (u16)((ymax - ymin)>>21); //.11
-
-        tile->tile_start_x_coor = (s16)(xmin>>29); //.3
-        tile->tile_start_y_coor = (s16)(ymin>>29); //.3
-    }
-    else if (msg->rotate_mode == 2)
-    {
-        tile->x_dx = (s32)((8*xx)>>22);
-        tile->x_dy = 0;
-        tile->y_dx = 0;
-        tile->y_dy = (s32)((8*yy)>>22);
-
-        tile->tile_w = ABS((s32)((7*xx)>>21));
-        tile->tile_h = ABS((s32)((7*yy)>>21));
-
-        tile->tile_xoff = ABS((s32)((7*xx)>>18));
-        tile->tile_yoff = 0;
-
-        tile->tile_start_x_coor = (((msg->src.act_w - 1)<<11) - (tile->tile_w))>>8;
-        tile->tile_start_y_coor = 0;
-    }
-    else if (msg->rotate_mode == 3)
-    {
-        tile->x_dx = (s32)((8*xx)>>22);
-        tile->x_dy = 0;
-        tile->y_dx = 0;
-        tile->y_dy = (s32)((8*yy)>>22);
-
-        tile->tile_w = ABS((s32)((7*xx)>>21));
-        tile->tile_h = ABS((s32)((7*yy)>>21));
-
-        tile->tile_xoff = 0;
-        tile->tile_yoff = ABS((s32)((7*yy)>>18));
-
-        tile->tile_start_x_coor = 0;
-        tile->tile_start_y_coor = (((msg->src.act_h - 1)<<11) - (tile->tile_h))>>8;
-    }
-
-    if ((msg->scale_mode == 2)||(msg->alpha_rop_flag >> 7))
-    {
-        tile->tile_start_x_coor -= (1<<3);
-        tile->tile_start_y_coor -= (1<<3);
-        tile->tile_w += (2 << 11);
-        tile->tile_h += (2 << 11);
-        tile->tile_xoff += (1<<14);
-        tile->tile_yoff += (1<<14);
-    }
-}
-
-
-/*************************************************************
-Func:
-    RGA_set_mode_ctrl
-Description:
-    fill mode ctrl reg info
-Author:
-    ZhangShengqin
-Date:
-    20012-2-2 10:59:25
-**************************************************************/
-
+src_tile_info_cal(const struct rga_req *msg, TILE_INFO *tile)
+{
+    s32 x0, x1, x2, x3, y0, y1, y2, y3;
+
+    int64_t xx, xy, yx, yy;
+
+    int64_t pos[8];
+    int64_t epos[8];
+
+    int64_t x_dx, x_dy, y_dx, y_dy;
+    int64_t x_temp_start, y_temp_start;
+    int64_t xmax, xmin, ymax, ymin;
+
+    int64_t t_xoff, t_yoff;
+
+    xx = tile->matrix[0]; /* 32.32 */
+    xy = tile->matrix[1]; /* 32.32 */
+    yx = tile->matrix[2]; /* 32.32 */
+    yy = tile->matrix[3]; /* 32.32 */
+
+    if(msg->rotate_mode == 1)
+    {
+        x0 = tile->dst_x_tmp;
+        y0 = tile->dst_y_tmp;
+
+        x1 = x0;
+        y1 = y0 + 8;
+
+        x2 = x0 + 8;
+        y2 = y0 + 8;
+
+        x3 = x0 + 8;
+        y3 = y0;
+
+        pos[0] = (x0*xx + y0*yx);
+        pos[1] = (x0*xy + y0*yy);
+
+        pos[2] = (x1*xx + y1*yx);
+        pos[3] = (x1*xy + y1*yy);
+
+        pos[4] = (x2*xx + y2*yx);
+        pos[5] = (x2*xy + y2*yy);
+
+        pos[6] = (x3*xx + y3*yx);
+        pos[7] = (x3*xy + y3*yy);
+
+        y1 = y0 + 7;
+        x2 = x0 + 7;
+        y2 = y0 + 7;
+        x3 = x0 + 7;
+
+        epos[0] = pos[0];
+        epos[1] = pos[1];
+
+        epos[2] = (x1*xx + y1*yx);
+        epos[3] = (x1*xy + y1*yy);
+
+        epos[4] = (x2*xx + y2*yx);
+        epos[5] = (x2*xy + y2*yy);
+
+        epos[6] = (x3*xx + y3*yx);
+        epos[7] = (x3*xy + y3*yy);
+
+        x_dx = pos[6] - pos[0];
+        x_dy = pos[7] - pos[1];
+
+        y_dx = pos[2] - pos[0];
+        y_dy = pos[3] - pos[1];
+
+        tile->x_dx = (s32)(x_dx >> 22 );
+        tile->x_dy = (s32)(x_dy >> 22 );
+        tile->y_dx = (s32)(y_dx >> 22 );
+        tile->y_dy = (s32)(y_dy >> 22 );
+
+        x_temp_start = x0*xx + y0*yx;
+        y_temp_start = x0*xy + y0*yy;
+
+        xmax = (MAX(MAX(MAX(epos[0], epos[2]), epos[4]), epos[6]));
+        xmin = (MIN(MIN(MIN(epos[0], epos[2]), epos[4]), epos[6]));
+
+        ymax = (MAX(MAX(MAX(epos[1], epos[3]), epos[5]), epos[7]));
+        ymin = (MIN(MIN(MIN(epos[1], epos[3]), epos[5]), epos[7]));
+
+        t_xoff = (x_temp_start - xmin)>>18;
+        t_yoff = (y_temp_start - ymin)>>18;
+
+        tile->tile_xoff = (s32)t_xoff;
+        tile->tile_yoff = (s32)t_yoff;
+
+        tile->tile_w = (u16)((xmax - xmin)>>21); //.11
+        tile->tile_h = (u16)((ymax - ymin)>>21); //.11
+
+        tile->tile_start_x_coor = (s16)(xmin>>29); //.3
+        tile->tile_start_y_coor = (s16)(ymin>>29); //.3
+    }
+    else if (msg->rotate_mode == 2)
+    {
+        tile->x_dx = (s32)((8*xx)>>22);
+        tile->x_dy = 0;
+        tile->y_dx = 0;
+        tile->y_dy = (s32)((8*yy)>>22);
+
+        tile->tile_w = ABS((s32)((7*xx)>>21));
+        tile->tile_h = ABS((s32)((7*yy)>>21));
+
+        tile->tile_xoff = ABS((s32)((7*xx)>>18));
+        tile->tile_yoff = 0;
+
+        tile->tile_start_x_coor = (((msg->src.act_w - 1)<<11) - (tile->tile_w))>>8;
+        tile->tile_start_y_coor = 0;
+    }
+    else if (msg->rotate_mode == 3)
+    {
+        tile->x_dx = (s32)((8*xx)>>22);
+        tile->x_dy = 0;
+        tile->y_dx = 0;
+        tile->y_dy = (s32)((8*yy)>>22);
+
+        tile->tile_w = ABS((s32)((7*xx)>>21));
+        tile->tile_h = ABS((s32)((7*yy)>>21));
+
+        tile->tile_xoff = 0;
+        tile->tile_yoff = ABS((s32)((7*yy)>>18));
+
+        tile->tile_start_x_coor = 0;
+        tile->tile_start_y_coor = (((msg->src.act_h - 1)<<11) - (tile->tile_h))>>8;
+    }
+
+    if ((msg->scale_mode == 2)||(msg->alpha_rop_flag >> 7))
+    {
+        tile->tile_start_x_coor -= (1<<3);
+        tile->tile_start_y_coor -= (1<<3);
+        tile->tile_w += (2 << 11);
+        tile->tile_h += (2 << 11);
+        tile->tile_xoff += (1<<14);
+        tile->tile_yoff += (1<<14);
+    }
+}
+
+
+/*************************************************************
+Func:
+    RGA_set_mode_ctrl
+Description:
+    fill mode ctrl reg info
+Author:
+    ZhangShengqin
+Date:
+    20012-2-2 10:59:25
+**************************************************************/
+
 static void
-RGA_set_mode_ctrl(u8 *base, const struct rga_req *msg)
-{
-    u32 *bRGA_MODE_CTL;
-    u32 reg = 0;
-
-    u8 src_rgb_pack = 0;
-    u8 src_format = 0;
-    u8 src_rb_swp = 0;
-    u8 src_a_swp = 0;
-    u8 src_cbcr_swp = 0;
-
-    u8 dst_rgb_pack = 0;
-    u8 dst_format = 0;
-    u8 dst_rb_swp = 0;
-    u8 dst_a_swp = 0;
-
-    bRGA_MODE_CTL = (u32 *)(base + RGA_MODE_CTRL_OFFSET);
-
-    reg = ((reg & (~m_RGA_MODE_CTRL_2D_RENDER_MODE)) | (s_RGA_MODE_CTRL_2D_RENDER_MODE(msg->render_mode)));
-
-    /* src info set */
-
-    if (msg->render_mode == color_palette_mode || msg->render_mode == update_palette_table_mode)
-    {
-        src_format = 0x10 | (msg->palette_mode & 3);
-    }
-    else
-    {
-        switch (msg->src.format)
-        {
-            case RK_FORMAT_RGBA_8888    : src_format = 0x0; break;
-            case RK_FORMAT_RGBA_4444    : src_format = 0x3; break;
-            case RK_FORMAT_RGBA_5551    : src_format = 0x2; break;
-            case RK_FORMAT_BGRA_8888    : src_format = 0x0; src_rb_swp = 0x1; break;
-            case RK_FORMAT_RGBX_8888    : src_format = 0x0; break;
-            case RK_FORMAT_RGB_565      : src_format = 0x1; break;
-            case RK_FORMAT_RGB_888      : src_format = 0x0; src_rgb_pack = 1; break;
-            case RK_FORMAT_BGR_888      : src_format = 0x0; src_rgb_pack = 1; src_rb_swp = 1; break;
-
-            case RK_FORMAT_YCbCr_422_SP : src_format = 0x4; break;
-            case RK_FORMAT_YCbCr_422_P  : src_format = 0x5; break;
-            case RK_FORMAT_YCbCr_420_SP : src_format = 0x6; break;
-            case RK_FORMAT_YCbCr_420_P  : src_format = 0x7; break;
-
-            case RK_FORMAT_YCrCb_422_SP : src_format = 0x4; src_cbcr_swp = 1; break;
-            case RK_FORMAT_YCrCb_422_P  : src_format = 0x5; src_cbcr_swp = 1; break;
-            case RK_FORMAT_YCrCb_420_SP : src_format = 0x6; src_cbcr_swp = 1; break;
-            case RK_FORMAT_YCrCb_420_P  : src_format = 0x7; src_cbcr_swp = 1; break;
-        }
-    }
-
-    src_a_swp = msg->src.alpha_swap & 1;
-
-    reg = ((reg & (~m_RGA_MODE_CTRL_SRC_RGB_PACK))      | (s_RGA_MODE_CTRL_SRC_RGB_PACK(src_rgb_pack)));
-    reg = ((reg & (~m_RGA_MODE_CTRL_SRC_FORMAT))        | (s_RGA_MODE_CTRL_SRC_FORMAT(src_format)));
-    reg = ((reg & (~m_RGA_MODE_CTRL_SRC_RB_SWAP))       | (s_RGA_MODE_CTRL_SRC_RB_SWAP(src_rb_swp)));
-    reg = ((reg & (~m_RGA_MODE_CTRL_SRC_ALPHA_SWAP))    | (s_RGA_MODE_CTRL_SRC_ALPHA_SWAP(src_a_swp)));
-    reg = ((reg & (~m_RGA_MODE_CTRL_SRC_UV_SWAP_MODE )) | (s_RGA_MODE_CTRL_SRC_UV_SWAP_MODE (src_cbcr_swp)));
-
-
-    /* YUV2RGB MODE */
-    reg = ((reg & (~m_RGA_MODE_CTRL_YUV2RGB_CON_MODE)) | (s_RGA_MODE_CTRL_YUV2RGB_CON_MODE(msg->yuv2rgb_mode)));
-
-    /* ROTATE MODE */
-    reg = ((reg & (~m_RGA_MODE_CTRL_ROTATE_MODE)) | (s_RGA_MODE_CTRL_ROTATE_MODE(msg->rotate_mode)));
-
-    /* SCALE MODE */
-    reg = ((reg & (~m_RGA_MODE_CTRL_SCALE_MODE)) | (s_RGA_MODE_CTRL_SCALE_MODE(msg->scale_mode)));
-
-    /* COLOR FILL MODE */
-    reg = ((reg & (~m_RGA_MODE_CTRL_PAT_SEL)) | (s_RGA_MODE_CTRL_PAT_SEL(msg->color_fill_mode)));
-
-
-    if ((msg->render_mode == update_palette_table_mode)||(msg->render_mode == update_patten_buff_mode))
-    {
-        dst_format = msg->pat.format;
-    }
-    else
-    {
-        dst_format = (u8)msg->dst.format;
-    }
-
-    /* dst info set */
-    switch (dst_format)
-    {
-        case RK_FORMAT_BGRA_8888 : dst_format = 0x0; dst_rb_swp = 0x1; break;
-        case RK_FORMAT_RGBA_4444 : dst_format = 0x3; break;
-        case RK_FORMAT_RGBA_5551 : dst_format = 0x2; break;
-        case RK_FORMAT_RGBA_8888 : dst_format = 0x0; break;
-        case RK_FORMAT_RGB_565   : dst_format = 0x1; break;
-        case RK_FORMAT_RGB_888   : dst_format = 0x0; dst_rgb_pack = 0x1; break;
-        case RK_FORMAT_BGR_888   : dst_format = 0x0; dst_rgb_pack = 0x1; dst_rb_swp = 1; break;
-        case RK_FORMAT_RGBX_8888 : dst_format = 0x0; break;
-    }
-
-    dst_a_swp = msg->dst.alpha_swap & 1;
-
-    reg = ((reg & (~m_RGA_MODE_CTRL_DST_FORMAT))       | (s_RGA_MODE_CTRL_DST_FORMAT(dst_format)));
-    reg = ((reg & (~m_RGA_MODE_CTRL_DST_RGB_PACK))     | (s_RGA_MODE_CTRL_DST_RGB_PACK(dst_rgb_pack)));
-    reg = ((reg & (~m_RGA_MODE_CTRL_DST_RB_SWAP))      | (s_RGA_MODE_CTRL_DST_RB_SWAP(dst_rb_swp)));
-    reg = ((reg & (~m_RGA_MODE_CTRL_DST_ALPHA_SWAP))   | (s_RGA_MODE_CTRL_DST_ALPHA_SWAP(dst_a_swp)));
-    reg = ((reg & (~m_RGA_MODE_CTRL_LUT_ENDIAN_MODE))  | (s_RGA_MODE_CTRL_LUT_ENDIAN_MODE(msg->endian_mode & 1)));
-    reg = ((reg & (~m_RGA_MODE_CTRL_SRC_TRANS_MODE))   | (s_RGA_MODE_CTRL_SRC_TRANS_MODE(msg->src_trans_mode)));
-    reg = ((reg & (~m_RGA_MODE_CTRL_ZERO_MODE_ENABLE)) | (s_RGA_MODE_CTRL_ZERO_MODE_ENABLE(msg->alpha_rop_mode >> 4)));
-    reg = ((reg & (~m_RGA_MODE_CTRL_DST_ALPHA_ENABLE)) | (s_RGA_MODE_CTRL_DST_ALPHA_ENABLE(msg->alpha_rop_mode >> 5)));
-
-    *bRGA_MODE_CTL = reg;
-
-}
-
-
-
-/*************************************************************
-Func:
-    RGA_set_src
-Description:
-    fill src relate reg info
-Author:
-    ZhangShengqin
-Date:
-    20012-2-2 10:59:25
-**************************************************************/
-
+RGA_set_mode_ctrl(u8 *base, const struct rga_req *msg)
+{
+    u32 *bRGA_MODE_CTL;
+    u32 reg = 0;
+
+    u8 src_rgb_pack = 0;
+    u8 src_format = 0;
+    u8 src_rb_swp = 0;
+    u8 src_a_swp = 0;
+    u8 src_cbcr_swp = 0;
+
+    u8 dst_rgb_pack = 0;
+    u8 dst_format = 0;
+    u8 dst_rb_swp = 0;
+    u8 dst_a_swp = 0;
+
+    bRGA_MODE_CTL = (u32 *)(base + RGA_MODE_CTRL_OFFSET);
+
+    reg = ((reg & (~m_RGA_MODE_CTRL_2D_RENDER_MODE)) | (s_RGA_MODE_CTRL_2D_RENDER_MODE(msg->render_mode)));
+
+    /* src info set */
+
+    if (msg->render_mode == color_palette_mode || msg->render_mode == update_palette_table_mode)
+    {
+        src_format = 0x10 | (msg->palette_mode & 3);
+    }
+    else
+    {
+        switch (msg->src.format)
+        {
+            case RK_FORMAT_RGBA_8888    : src_format = 0x0; break;
+            case RK_FORMAT_RGBA_4444    : src_format = 0x3; break;
+            case RK_FORMAT_RGBA_5551    : src_format = 0x2; break;
+            case RK_FORMAT_BGRA_8888    : src_format = 0x0; src_rb_swp = 0x1; break;
+            case RK_FORMAT_RGBX_8888    : src_format = 0x0; break;
+            case RK_FORMAT_RGB_565      : src_format = 0x1; break;
+            case RK_FORMAT_RGB_888      : src_format = 0x0; src_rgb_pack = 1; break;
+            case RK_FORMAT_BGR_888      : src_format = 0x0; src_rgb_pack = 1; src_rb_swp = 1; break;
+
+            case RK_FORMAT_YCbCr_422_SP : src_format = 0x4; break;
+            case RK_FORMAT_YCbCr_422_P  : src_format = 0x5; break;
+            case RK_FORMAT_YCbCr_420_SP : src_format = 0x6; break;
+            case RK_FORMAT_YCbCr_420_P  : src_format = 0x7; break;
+
+            case RK_FORMAT_YCrCb_422_SP : src_format = 0x4; src_cbcr_swp = 1; break;
+            case RK_FORMAT_YCrCb_422_P  : src_format = 0x5; src_cbcr_swp = 1; break;
+            case RK_FORMAT_YCrCb_420_SP : src_format = 0x6; src_cbcr_swp = 1; break;
+            case RK_FORMAT_YCrCb_420_P  : src_format = 0x7; src_cbcr_swp = 1; break;
+        }
+    }
+
+    src_a_swp = msg->src.alpha_swap & 1;
+
+    reg = ((reg & (~m_RGA_MODE_CTRL_SRC_RGB_PACK))      | (s_RGA_MODE_CTRL_SRC_RGB_PACK(src_rgb_pack)));
+    reg = ((reg & (~m_RGA_MODE_CTRL_SRC_FORMAT))        | (s_RGA_MODE_CTRL_SRC_FORMAT(src_format)));
+    reg = ((reg & (~m_RGA_MODE_CTRL_SRC_RB_SWAP))       | (s_RGA_MODE_CTRL_SRC_RB_SWAP(src_rb_swp)));
+    reg = ((reg & (~m_RGA_MODE_CTRL_SRC_ALPHA_SWAP))    | (s_RGA_MODE_CTRL_SRC_ALPHA_SWAP(src_a_swp)));
+    reg = ((reg & (~m_RGA_MODE_CTRL_SRC_UV_SWAP_MODE )) | (s_RGA_MODE_CTRL_SRC_UV_SWAP_MODE (src_cbcr_swp)));
+
+
+    /* YUV2RGB MODE */
+    reg = ((reg & (~m_RGA_MODE_CTRL_YUV2RGB_CON_MODE)) | (s_RGA_MODE_CTRL_YUV2RGB_CON_MODE(msg->yuv2rgb_mode)));
+
+    /* ROTATE MODE */
+    reg = ((reg & (~m_RGA_MODE_CTRL_ROTATE_MODE)) | (s_RGA_MODE_CTRL_ROTATE_MODE(msg->rotate_mode)));
+
+    /* SCALE MODE */
+    reg = ((reg & (~m_RGA_MODE_CTRL_SCALE_MODE)) | (s_RGA_MODE_CTRL_SCALE_MODE(msg->scale_mode)));
+
+    /* COLOR FILL MODE */
+    reg = ((reg & (~m_RGA_MODE_CTRL_PAT_SEL)) | (s_RGA_MODE_CTRL_PAT_SEL(msg->color_fill_mode)));
+
+
+    if ((msg->render_mode == update_palette_table_mode)||(msg->render_mode == update_patten_buff_mode))
+    {
+        dst_format = msg->pat.format;
+    }
+    else
+    {
+        dst_format = (u8)msg->dst.format;
+    }
+
+    /* dst info set */
+    switch (dst_format)
+    {
+        case RK_FORMAT_BGRA_8888 : dst_format = 0x0; dst_rb_swp = 0x1; break;
+        case RK_FORMAT_RGBA_4444 : dst_format = 0x3; break;
+        case RK_FORMAT_RGBA_5551 : dst_format = 0x2; break;
+        case RK_FORMAT_RGBA_8888 : dst_format = 0x0; break;
+        case RK_FORMAT_RGB_565   : dst_format = 0x1; break;
+        case RK_FORMAT_RGB_888   : dst_format = 0x0; dst_rgb_pack = 0x1; break;
+        case RK_FORMAT_BGR_888   : dst_format = 0x0; dst_rgb_pack = 0x1; dst_rb_swp = 1; break;
+        case RK_FORMAT_RGBX_8888 : dst_format = 0x0; break;
+    }
+
+    dst_a_swp = msg->dst.alpha_swap & 1;
+
+    reg = ((reg & (~m_RGA_MODE_CTRL_DST_FORMAT))       | (s_RGA_MODE_CTRL_DST_FORMAT(dst_format)));
+    reg = ((reg & (~m_RGA_MODE_CTRL_DST_RGB_PACK))     | (s_RGA_MODE_CTRL_DST_RGB_PACK(dst_rgb_pack)));
+    reg = ((reg & (~m_RGA_MODE_CTRL_DST_RB_SWAP))      | (s_RGA_MODE_CTRL_DST_RB_SWAP(dst_rb_swp)));
+    reg = ((reg & (~m_RGA_MODE_CTRL_DST_ALPHA_SWAP))   | (s_RGA_MODE_CTRL_DST_ALPHA_SWAP(dst_a_swp)));
+    reg = ((reg & (~m_RGA_MODE_CTRL_LUT_ENDIAN_MODE))  | (s_RGA_MODE_CTRL_LUT_ENDIAN_MODE(msg->endian_mode & 1)));
+    reg = ((reg & (~m_RGA_MODE_CTRL_SRC_TRANS_MODE))   | (s_RGA_MODE_CTRL_SRC_TRANS_MODE(msg->src_trans_mode)));
+    reg = ((reg & (~m_RGA_MODE_CTRL_ZERO_MODE_ENABLE)) | (s_RGA_MODE_CTRL_ZERO_MODE_ENABLE(msg->alpha_rop_mode >> 4)));
+    reg = ((reg & (~m_RGA_MODE_CTRL_DST_ALPHA_ENABLE)) | (s_RGA_MODE_CTRL_DST_ALPHA_ENABLE(msg->alpha_rop_mode >> 5)));
+
+    *bRGA_MODE_CTL = reg;
+
+}
+
+
+
+/*************************************************************
+Func:
+    RGA_set_src
+Description:
+    fill src relate reg info
+Author:
+    ZhangShengqin
+Date:
+    20012-2-2 10:59:25
+**************************************************************/
+
 static void
-RGA_set_src(u8 *base, const struct rga_req *msg)
-{
-    u32 *bRGA_SRC_VIR_INFO;
-    u32 *bRGA_SRC_ACT_INFO;
-    u32 *bRGA_SRC_Y_MST;
-    u32 *bRGA_SRC_CB_MST;
-    u32 *bRGA_SRC_CR_MST;
-
-    s16 x_off, y_off, stride;
-    s16 uv_x_off, uv_y_off, uv_stride;
-    u32 pixel_width;
-
-    uv_x_off = uv_y_off = uv_stride = 0;
-
-    bRGA_SRC_Y_MST = (u32 *)(base + RGA_SRC_Y_MST_OFFSET);
-    bRGA_SRC_CB_MST = (u32 *)(base + RGA_SRC_CB_MST_OFFSET);
-    bRGA_SRC_CR_MST = (u32 *)(base + RGA_SRC_CR_MST_OFFSET);
-    bRGA_SRC_VIR_INFO = (u32 *)(base + RGA_SRC_VIR_INFO_OFFSET);
-    bRGA_SRC_ACT_INFO = (u32 *)(base + RGA_SRC_ACT_INFO_OFFSET);
-
-    x_off  = msg->src.x_offset;
-    y_off  = msg->src.y_offset;
-
-    pixel_width = RGA_pixel_width_init(msg->src.format);
-
-    stride = ((msg->src.vir_w * pixel_width) + 3) & (~3);
-
-    switch(msg->src.format)
-    {
-        case RK_FORMAT_YCbCr_422_SP :
-            uv_stride = stride;
-            uv_x_off = x_off;
-            uv_y_off = y_off;
-            break;
-        case RK_FORMAT_YCbCr_422_P  :
-            uv_stride = stride >> 1;
-            uv_x_off = x_off >> 1;
-            uv_y_off = y_off;
-            break;
-        case RK_FORMAT_YCbCr_420_SP :
-            uv_stride = stride;
-            uv_x_off = x_off;
-            uv_y_off = y_off >> 1;
-            break;
-        case RK_FORMAT_YCbCr_420_P :
-            uv_stride = stride >> 1;
-            uv_x_off = x_off >> 1;
-            uv_y_off = y_off >> 1;
-            break;
-        case RK_FORMAT_YCrCb_422_SP :
-            uv_stride = stride;
-            uv_x_off = x_off;
-            uv_y_off = y_off;
-            break;
-        case RK_FORMAT_YCrCb_422_P  :
-            uv_stride = stride >> 1;
-            uv_x_off = x_off >> 1;
-            uv_y_off = y_off;
-            break;
-        case RK_FORMAT_YCrCb_420_SP :
-            uv_stride = stride;
-            uv_x_off = x_off;
-            uv_y_off = y_off >> 1;
-            break;
-        case RK_FORMAT_YCrCb_420_P :
-            uv_stride = stride >> 1;
-            uv_x_off = x_off >> 1;
-            uv_y_off = y_off >> 1;
-            break;
-    }
-
-
-    /* src addr set */
-    *bRGA_SRC_Y_MST = msg->src.yrgb_addr + (y_off * stride) + (x_off * pixel_width);
-    *bRGA_SRC_CB_MST = msg->src.uv_addr + uv_y_off * uv_stride + uv_x_off;
-    *bRGA_SRC_CR_MST = msg->src.v_addr + uv_y_off * uv_stride + uv_x_off;
-
-    if((msg->alpha_rop_flag >> 1) & 1)
-        *bRGA_SRC_CB_MST = (u32)msg->rop_mask_addr;
-
-    if (msg->render_mode == color_palette_mode)
-    {
-        u8 shift;
-        u16 sw, byte_num;
-        shift = 3 - (msg->palette_mode & 3);
-        sw = msg->src.vir_w;
-
-        byte_num = sw >> shift;
-        stride = (byte_num + 3) & (~3);
-    }
-
-    /* src act window / vir window set */
-    *bRGA_SRC_VIR_INFO = ((stride >> 2) | (msg->src.vir_h)<<16);
-    *bRGA_SRC_ACT_INFO = ((msg->src.act_w-1) | (msg->src.act_h-1)<<16);
-}
-
-
-/*************************************************************
-Func:
-    RGA_set_dst
-Description:
-    fill dst relate reg info
-Author:
-    ZhangShengqin
-Date:
-    20012-2-2 10:59:25
-**************************************************************/
+RGA_set_src(u8 *base, const struct rga_req *msg)
+{
+    u32 *bRGA_SRC_VIR_INFO;
+    u32 *bRGA_SRC_ACT_INFO;
+    u32 *bRGA_SRC_Y_MST;
+    u32 *bRGA_SRC_CB_MST;
+    u32 *bRGA_SRC_CR_MST;
+
+    s16 x_off, y_off, stride;
+    s16 uv_x_off, uv_y_off, uv_stride;
+    u32 pixel_width;
+
+    uv_x_off = uv_y_off = uv_stride = 0;
+
+    bRGA_SRC_Y_MST = (u32 *)(base + RGA_SRC_Y_MST_OFFSET);
+    bRGA_SRC_CB_MST = (u32 *)(base + RGA_SRC_CB_MST_OFFSET);
+    bRGA_SRC_CR_MST = (u32 *)(base + RGA_SRC_CR_MST_OFFSET);
+    bRGA_SRC_VIR_INFO = (u32 *)(base + RGA_SRC_VIR_INFO_OFFSET);
+    bRGA_SRC_ACT_INFO = (u32 *)(base + RGA_SRC_ACT_INFO_OFFSET);
+
+    x_off  = msg->src.x_offset;
+    y_off  = msg->src.y_offset;
+
+    pixel_width = RGA_pixel_width_init(msg->src.format);
+
+    stride = ((msg->src.vir_w * pixel_width) + 3) & (~3);
+
+    switch(msg->src.format)
+    {
+        case RK_FORMAT_YCbCr_422_SP :
+            uv_stride = stride;
+            uv_x_off = x_off;
+            uv_y_off = y_off;
+            break;
+        case RK_FORMAT_YCbCr_422_P  :
+            uv_stride = stride >> 1;
+            uv_x_off = x_off >> 1;
+            uv_y_off = y_off;
+            break;
+        case RK_FORMAT_YCbCr_420_SP :
+            uv_stride = stride;
+            uv_x_off = x_off;
+            uv_y_off = y_off >> 1;
+            break;
+        case RK_FORMAT_YCbCr_420_P :
+            uv_stride = stride >> 1;
+            uv_x_off = x_off >> 1;
+            uv_y_off = y_off >> 1;
+            break;
+        case RK_FORMAT_YCrCb_422_SP :
+            uv_stride = stride;
+            uv_x_off = x_off;
+            uv_y_off = y_off;
+            break;
+        case RK_FORMAT_YCrCb_422_P  :
+            uv_stride = stride >> 1;
+            uv_x_off = x_off >> 1;
+            uv_y_off = y_off;
+            break;
+        case RK_FORMAT_YCrCb_420_SP :
+            uv_stride = stride;
+            uv_x_off = x_off;
+            uv_y_off = y_off >> 1;
+            break;
+        case RK_FORMAT_YCrCb_420_P :
+            uv_stride = stride >> 1;
+            uv_x_off = x_off >> 1;
+            uv_y_off = y_off >> 1;
+            break;
+    }
+
+
+    /* src addr set */
+    *bRGA_SRC_Y_MST = msg->src.yrgb_addr + (y_off * stride) + (x_off * pixel_width);
+    *bRGA_SRC_CB_MST = msg->src.uv_addr + uv_y_off * uv_stride + uv_x_off;
+    *bRGA_SRC_CR_MST = msg->src.v_addr + uv_y_off * uv_stride + uv_x_off;
+
+    if((msg->alpha_rop_flag >> 1) & 1)
+        *bRGA_SRC_CB_MST = (u32)msg->rop_mask_addr;
+
+    if (msg->render_mode == color_palette_mode)
+    {
+        u8 shift;
+        u16 sw, byte_num;
+        shift = 3 - (msg->palette_mode & 3);
+        sw = msg->src.vir_w;
+
+        byte_num = sw >> shift;
+        stride = (byte_num + 3) & (~3);
+    }
+
+    /* src act window / vir window set */
+    *bRGA_SRC_VIR_INFO = ((stride >> 2) | (msg->src.vir_h)<<16);
+    *bRGA_SRC_ACT_INFO = ((msg->src.act_w-1) | (msg->src.act_h-1)<<16);
+}
+
+
+/*************************************************************
+Func:
+    RGA_set_dst
+Description:
+    fill dst relate reg info
+Author:
+    ZhangShengqin
+Date:
+    20012-2-2 10:59:25
+**************************************************************/
 
 static s32 RGA_set_dst(u8 *base, const struct rga_req *msg)
-{
-    u32 *bRGA_DST_MST;
-    u32 *bRGA_DST_UV_MST;
-    u32 *bRGA_DST_VIR_INFO;
-    u32 *bRGA_DST_CTR_INFO;
-    u32 *bRGA_PRESCL_CB_MST;
-    u32 *bRGA_PRESCL_CR_MST;
-    u32 *bRGA_YUV_OUT_CFG;
-
-    u32 reg = 0;
-
-    u8 pw;
-    s16 x_off = msg->dst.x_offset;
-    s16 y_off = msg->dst.y_offset;
-    u16 stride, rop_mask_stride;
-
-    bRGA_DST_MST = (u32 *)(base + RGA_DST_MST_OFFSET);
-    bRGA_DST_UV_MST = (u32 *)(base + RGA_DST_UV_MST_OFFSET);
-    bRGA_DST_VIR_INFO = (u32 *)(base + RGA_DST_VIR_INFO_OFFSET);
-    bRGA_DST_CTR_INFO = (u32 *)(base + RGA_DST_CTR_INFO_OFFSET);
-    bRGA_PRESCL_CB_MST = (u32 *)(base + RGA_PRESCL_CB_MST_OFFSET);
-    bRGA_PRESCL_CR_MST = (u32 *)(base + RGA_PRESCL_CR_MST_OFFSET);
-    bRGA_YUV_OUT_CFG = (u32 *)(base + RGA_YUV_OUT_CFG_OFFSET);
-
-    pw = RGA_pixel_width_init(msg->dst.format);
-
-    stride = (msg->dst.vir_w * pw + 3) & (~3);
-
-    *bRGA_DST_MST = (u32)msg->dst.yrgb_addr + (y_off * stride) + (x_off * pw);
-
+{
+    u32 *bRGA_DST_MST;
+    u32 *bRGA_DST_UV_MST;
+    u32 *bRGA_DST_VIR_INFO;
+    u32 *bRGA_DST_CTR_INFO;
+    u32 *bRGA_PRESCL_CB_MST;
+    u32 *bRGA_PRESCL_CR_MST;
+    u32 *bRGA_YUV_OUT_CFG;
+
+    u32 reg = 0;
+
+    u8 pw;
+    s16 x_off = msg->dst.x_offset;
+    s16 y_off = msg->dst.y_offset;
+    u16 stride, rop_mask_stride;
+
+    bRGA_DST_MST = (u32 *)(base + RGA_DST_MST_OFFSET);
+    bRGA_DST_UV_MST = (u32 *)(base + RGA_DST_UV_MST_OFFSET);
+    bRGA_DST_VIR_INFO = (u32 *)(base + RGA_DST_VIR_INFO_OFFSET);
+    bRGA_DST_CTR_INFO = (u32 *)(base + RGA_DST_CTR_INFO_OFFSET);
+    bRGA_PRESCL_CB_MST = (u32 *)(base + RGA_PRESCL_CB_MST_OFFSET);
+    bRGA_PRESCL_CR_MST = (u32 *)(base + RGA_PRESCL_CR_MST_OFFSET);
+    bRGA_YUV_OUT_CFG = (u32 *)(base + RGA_YUV_OUT_CFG_OFFSET);
+
+    pw = RGA_pixel_width_init(msg->dst.format);
+
+    stride = (msg->dst.vir_w * pw + 3) & (~3);
+
+    *bRGA_DST_MST = (u32)msg->dst.yrgb_addr + (y_off * stride) + (x_off * pw);
+
     *bRGA_DST_UV_MST = 0;
     *bRGA_YUV_OUT_CFG = 0;
 	if (msg->rotate_mode == 1) {
@@ -719,869 +719,869 @@ static s32 RGA_set_dst(u8 *base, const struct rga_req *msg)
 		}
 	}
 
-    switch(msg->dst.format)
-    {
-        case RK_FORMAT_YCbCr_422_SP :
-            *bRGA_PRESCL_CB_MST = (u32)msg->dst.uv_addr + ((y_off) * stride) + ((x_off) * pw);
+    switch(msg->dst.format)
+    {
+        case RK_FORMAT_YCbCr_422_SP :
+            *bRGA_PRESCL_CB_MST = (u32)msg->dst.uv_addr + ((y_off) * stride) + ((x_off) * pw);
 			*bRGA_DST_UV_MST = (u32)msg->dst.uv_addr + (y_off * stride) + x_off;
 			*bRGA_YUV_OUT_CFG |= (((msg->yuv2rgb_mode >> 2) & 3) << 4) | (0 << 3) | (0 << 1) | 1;
-            break;
-        case RK_FORMAT_YCbCr_422_P  :
-            *bRGA_PRESCL_CB_MST = (u32)msg->dst.uv_addr + ((y_off) * stride) + ((x_off>>1) * pw);
-            *bRGA_PRESCL_CR_MST = (u32)msg->dst.v_addr  + ((y_off) * stride) + ((x_off>>1) * pw);
-            break;
-        case RK_FORMAT_YCbCr_420_SP :
-            *bRGA_PRESCL_CB_MST = (u32)msg->dst.uv_addr + ((y_off>>1) * stride) + ((x_off) * pw);
+            break;
+        case RK_FORMAT_YCbCr_422_P  :
+            *bRGA_PRESCL_CB_MST = (u32)msg->dst.uv_addr + ((y_off) * stride) + ((x_off>>1) * pw);
+            *bRGA_PRESCL_CR_MST = (u32)msg->dst.v_addr  + ((y_off) * stride) + ((x_off>>1) * pw);
+            break;
+        case RK_FORMAT_YCbCr_420_SP :
+            *bRGA_PRESCL_CB_MST = (u32)msg->dst.uv_addr + ((y_off>>1) * stride) + ((x_off) * pw);
 			*bRGA_DST_UV_MST = (u32)msg->dst.uv_addr + ((y_off>>1) * stride) + x_off;
 			*bRGA_YUV_OUT_CFG |= (((msg->yuv2rgb_mode >> 2) & 3) << 4) | (0 << 3) | (1 << 1) | 1;
-            break;
-        case RK_FORMAT_YCbCr_420_P :
-            *bRGA_PRESCL_CB_MST = (u32)msg->dst.uv_addr + ((y_off>>1) * stride) + ((x_off>>1) * pw);
-            *bRGA_PRESCL_CR_MST = (u32)msg->dst.v_addr  + ((y_off>>1) * stride) + ((x_off>>1) * pw);
-            break;
-        case RK_FORMAT_YCrCb_422_SP :
-            *bRGA_PRESCL_CB_MST = (u32)msg->dst.uv_addr + ((y_off) * stride) + ((x_off) * pw);
+            break;
+        case RK_FORMAT_YCbCr_420_P :
+            *bRGA_PRESCL_CB_MST = (u32)msg->dst.uv_addr + ((y_off>>1) * stride) + ((x_off>>1) * pw);
+            *bRGA_PRESCL_CR_MST = (u32)msg->dst.v_addr  + ((y_off>>1) * stride) + ((x_off>>1) * pw);
+            break;
+        case RK_FORMAT_YCrCb_422_SP :
+            *bRGA_PRESCL_CB_MST = (u32)msg->dst.uv_addr + ((y_off) * stride) + ((x_off) * pw);
 			*bRGA_DST_UV_MST = (u32)msg->dst.uv_addr + (y_off * stride) + x_off;
 			*bRGA_YUV_OUT_CFG |= (((msg->yuv2rgb_mode >> 2) & 3) << 4) | (1 << 3) | (0 << 1) | 1;
-            break;
-        case RK_FORMAT_YCrCb_422_P  :
-            *bRGA_PRESCL_CB_MST = (u32)msg->dst.uv_addr + ((y_off) * stride) + ((x_off>>1) * pw);
-            *bRGA_PRESCL_CR_MST = (u32)msg->dst.v_addr  + ((y_off) * stride) + ((x_off>>1) * pw);
-            break;
-        case RK_FORMAT_YCrCb_420_SP :
-            *bRGA_PRESCL_CB_MST = (u32)msg->dst.uv_addr + ((y_off>>1) * stride) + ((x_off) * pw);
+            break;
+        case RK_FORMAT_YCrCb_422_P  :
+            *bRGA_PRESCL_CB_MST = (u32)msg->dst.uv_addr + ((y_off) * stride) + ((x_off>>1) * pw);
+            *bRGA_PRESCL_CR_MST = (u32)msg->dst.v_addr  + ((y_off) * stride) + ((x_off>>1) * pw);
+            break;
+        case RK_FORMAT_YCrCb_420_SP :
+            *bRGA_PRESCL_CB_MST = (u32)msg->dst.uv_addr + ((y_off>>1) * stride) + ((x_off) * pw);
 			*bRGA_DST_UV_MST = (u32)msg->dst.uv_addr + ((y_off>>1) * stride) + x_off;
 			*bRGA_YUV_OUT_CFG |= (((msg->yuv2rgb_mode >> 2) & 3) << 4) | (1 << 3) | (1 << 1) | 1;
-            break;
-        case RK_FORMAT_YCrCb_420_P :
-            *bRGA_PRESCL_CB_MST = (u32)msg->dst.uv_addr + ((y_off>>1) * stride) + ((x_off>>1) * pw);
-            *bRGA_PRESCL_CR_MST = (u32)msg->dst.v_addr  + ((y_off>>1) * stride) + ((x_off>>1) * pw);
-            break;
-    }
-
-    rop_mask_stride = (((msg->src.vir_w + 7)>>3) + 3) & (~3);//not dst_vir.w,hxx,2011.7.21
-
-    reg = (stride >> 2) & 0xffff;
-    reg = reg | ((rop_mask_stride>>2) << 16);
-
-    #if defined(CONFIG_ARCH_RK2928) || defined(CONFIG_ARCH_RK3188)
-    //reg = reg | ((msg->alpha_rop_mode & 3) << 28);
-    reg = reg | (1 << 28);
-    #endif
-
-    if (msg->render_mode == line_point_drawing_mode)
-    {
-        reg &= 0xffff;
-        reg = reg | (msg->dst.vir_h << 16);
-    }
-
-    *bRGA_DST_VIR_INFO = reg;
-    *bRGA_DST_CTR_INFO = (msg->dst.act_w - 1) | ((msg->dst.act_h - 1) << 16);
+            break;
+        case RK_FORMAT_YCrCb_420_P :
+            *bRGA_PRESCL_CB_MST = (u32)msg->dst.uv_addr + ((y_off>>1) * stride) + ((x_off>>1) * pw);
+            *bRGA_PRESCL_CR_MST = (u32)msg->dst.v_addr  + ((y_off>>1) * stride) + ((x_off>>1) * pw);
+            break;
+    }
+
+    rop_mask_stride = (((msg->src.vir_w + 7)>>3) + 3) & (~3);//not dst_vir.w,hxx,2011.7.21
+
+    reg = (stride >> 2) & 0xffff;
+    reg = reg | ((rop_mask_stride>>2) << 16);
+
+    #if defined(CONFIG_ARCH_RK2928) || defined(CONFIG_ARCH_RK3188)
+    //reg = reg | ((msg->alpha_rop_mode & 3) << 28);
+    reg = reg | (1 << 28);
+    #endif
+
+    if (msg->render_mode == line_point_drawing_mode)
+    {
+        reg &= 0xffff;
+        reg = reg | (msg->dst.vir_h << 16);
+    }
+
+    *bRGA_DST_VIR_INFO = reg;
+    *bRGA_DST_CTR_INFO = (msg->dst.act_w - 1) | ((msg->dst.act_h - 1) << 16);
 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 1, 0))
-    if (msg->render_mode == pre_scaling_mode) {
-        *bRGA_YUV_OUT_CFG &= 0xfffffffe;
-    }
+    if (msg->render_mode == pre_scaling_mode) {
+        *bRGA_YUV_OUT_CFG &= 0xfffffffe;
+    }
 #endif
-    return 0;
-}
-
-
-/*************************************************************
-Func:
-    RGA_set_alpha_rop
-Description:
-    fill alpha rop some relate reg bit
-Author:
-    ZhangShengqin
-Date:
-    20012-2-2 10:59:25
-**************************************************************/
+    return 0;
+}
+
+
+/*************************************************************
+Func:
+    RGA_set_alpha_rop
+Description:
+    fill alpha rop some relate reg bit
+Author:
+    ZhangShengqin
+Date:
+    20012-2-2 10:59:25
+**************************************************************/
 static void
-RGA_set_alpha_rop(u8 *base, const struct rga_req *msg)
-{
-    u32 *bRGA_ALPHA_CON;
-    u32 *bRGA_ROP_CON0;
-    u32 *bRGA_ROP_CON1;
-    u32 reg = 0;
-    u32 rop_con0, rop_con1;
-
-    u8 rop_mode = (msg->alpha_rop_mode) & 3;
-    u8 alpha_mode = msg->alpha_rop_mode & 3;
-
-    rop_con0 = rop_con1 = 0;
-
-    bRGA_ALPHA_CON = (u32 *)(base + RGA_ALPHA_CON_OFFSET);
-
-    reg = ((reg & (~m_RGA_ALPHA_CON_ENABLE) )| (s_RGA_ALPHA_CON_ENABLE(msg->alpha_rop_flag & 1)));
-    reg = ((reg & (~m_RGA_ALPHA_CON_A_OR_R_SEL)) | (s_RGA_ALPHA_CON_A_OR_R_SEL((msg->alpha_rop_flag >> 1) & 1)));
-    reg = ((reg & (~m_RGA_ALPHA_CON_ALPHA_MODE)) | (s_RGA_ALPHA_CON_ALPHA_MODE(alpha_mode)));
-    reg = ((reg & (~m_RGA_ALPHA_CON_PD_MODE)) | (s_RGA_ALPHA_CON_PD_MODE(msg->PD_mode)));
-    reg = ((reg & (~m_RGA_ALPHA_CON_SET_CONSTANT_VALUE)) | (s_RGA_ALPHA_CON_SET_CONSTANT_VALUE(msg->alpha_global_value)));
-    reg = ((reg & (~m_RGA_ALPHA_CON_PD_M_SEL)) | (s_RGA_ALPHA_CON_PD_M_SEL(msg->alpha_rop_flag >> 3)));
-    reg = ((reg & (~m_RGA_ALPHA_CON_FADING_ENABLE)) | (s_RGA_ALPHA_CON_FADING_ENABLE(msg->alpha_rop_flag >> 2)));
-    reg = ((reg & (~m_RGA_ALPHA_CON_ROP_MODE_SEL)) | (s_RGA_ALPHA_CON_ROP_MODE_SEL(rop_mode)));
-    reg = ((reg & (~m_RGA_ALPHA_CON_CAL_MODE_SEL)) | (s_RGA_ALPHA_CON_CAL_MODE_SEL(msg->alpha_rop_flag >> 4)));
-    reg = ((reg & (~m_RGA_ALPHA_CON_DITHER_ENABLE)) | (s_RGA_ALPHA_CON_DITHER_ENABLE(msg->alpha_rop_flag >> 5)));
-    reg = ((reg & (~m_RGA_ALPHA_CON_GRADIENT_CAL_MODE)) | (s_RGA_ALPHA_CON_GRADIENT_CAL_MODE(msg->alpha_rop_flag >> 6)));
-    reg = ((reg & (~m_RGA_ALPHA_CON_AA_SEL)) | (s_RGA_ALPHA_CON_AA_SEL(msg->alpha_rop_flag >> 7)));
-
-    *bRGA_ALPHA_CON = reg;
-
-    if(rop_mode == 0) {
-        rop_con0 =  ROP3_code[(msg->rop_code & 0xff)];
-    }
-    else if(rop_mode == 1) {
-        rop_con0 =  ROP3_code[(msg->rop_code & 0xff)];
-    }
-    else if(rop_mode == 2) {
-        rop_con0 =  ROP3_code[(msg->rop_code & 0xff)];
-        rop_con1 =  ROP3_code[(msg->rop_code & 0xff00)>>8];
-    }
-
-    bRGA_ROP_CON0 = (u32 *)(base + RGA_ROP_CON0_OFFSET);
-    bRGA_ROP_CON1 = (u32 *)(base + RGA_ROP_CON1_OFFSET);
-
-    *bRGA_ROP_CON0 = (u32)rop_con0;
-    *bRGA_ROP_CON1 = (u32)rop_con1;
-}
-
-
-/*************************************************************
-Func:
-    RGA_set_color
-Description:
-    fill color some relate reg bit
-    bg_color/fg_color
-Author:
-    ZhangShengqin
-Date:
-    20012-2-2 10:59:25
-**************************************************************/
+RGA_set_alpha_rop(u8 *base, const struct rga_req *msg)
+{
+    u32 *bRGA_ALPHA_CON;
+    u32 *bRGA_ROP_CON0;
+    u32 *bRGA_ROP_CON1;
+    u32 reg = 0;
+    u32 rop_con0, rop_con1;
+
+    u8 rop_mode = (msg->alpha_rop_mode) & 3;
+    u8 alpha_mode = msg->alpha_rop_mode & 3;
+
+    rop_con0 = rop_con1 = 0;
+
+    bRGA_ALPHA_CON = (u32 *)(base + RGA_ALPHA_CON_OFFSET);
+
+    reg = ((reg & (~m_RGA_ALPHA_CON_ENABLE) )| (s_RGA_ALPHA_CON_ENABLE(msg->alpha_rop_flag & 1)));
+    reg = ((reg & (~m_RGA_ALPHA_CON_A_OR_R_SEL)) | (s_RGA_ALPHA_CON_A_OR_R_SEL((msg->alpha_rop_flag >> 1) & 1)));
+    reg = ((reg & (~m_RGA_ALPHA_CON_ALPHA_MODE)) | (s_RGA_ALPHA_CON_ALPHA_MODE(alpha_mode)));
+    reg = ((reg & (~m_RGA_ALPHA_CON_PD_MODE)) | (s_RGA_ALPHA_CON_PD_MODE(msg->PD_mode)));
+    reg = ((reg & (~m_RGA_ALPHA_CON_SET_CONSTANT_VALUE)) | (s_RGA_ALPHA_CON_SET_CONSTANT_VALUE(msg->alpha_global_value)));
+    reg = ((reg & (~m_RGA_ALPHA_CON_PD_M_SEL)) | (s_RGA_ALPHA_CON_PD_M_SEL(msg->alpha_rop_flag >> 3)));
+    reg = ((reg & (~m_RGA_ALPHA_CON_FADING_ENABLE)) | (s_RGA_ALPHA_CON_FADING_ENABLE(msg->alpha_rop_flag >> 2)));
+    reg = ((reg & (~m_RGA_ALPHA_CON_ROP_MODE_SEL)) | (s_RGA_ALPHA_CON_ROP_MODE_SEL(rop_mode)));
+    reg = ((reg & (~m_RGA_ALPHA_CON_CAL_MODE_SEL)) | (s_RGA_ALPHA_CON_CAL_MODE_SEL(msg->alpha_rop_flag >> 4)));
+    reg = ((reg & (~m_RGA_ALPHA_CON_DITHER_ENABLE)) | (s_RGA_ALPHA_CON_DITHER_ENABLE(msg->alpha_rop_flag >> 5)));
+    reg = ((reg & (~m_RGA_ALPHA_CON_GRADIENT_CAL_MODE)) | (s_RGA_ALPHA_CON_GRADIENT_CAL_MODE(msg->alpha_rop_flag >> 6)));
+    reg = ((reg & (~m_RGA_ALPHA_CON_AA_SEL)) | (s_RGA_ALPHA_CON_AA_SEL(msg->alpha_rop_flag >> 7)));
+
+    *bRGA_ALPHA_CON = reg;
+
+    if(rop_mode == 0) {
+        rop_con0 =  ROP3_code[(msg->rop_code & 0xff)];
+    }
+    else if(rop_mode == 1) {
+        rop_con0 =  ROP3_code[(msg->rop_code & 0xff)];
+    }
+    else if(rop_mode == 2) {
+        rop_con0 =  ROP3_code[(msg->rop_code & 0xff)];
+        rop_con1 =  ROP3_code[(msg->rop_code & 0xff00)>>8];
+    }
+
+    bRGA_ROP_CON0 = (u32 *)(base + RGA_ROP_CON0_OFFSET);
+    bRGA_ROP_CON1 = (u32 *)(base + RGA_ROP_CON1_OFFSET);
+
+    *bRGA_ROP_CON0 = (u32)rop_con0;
+    *bRGA_ROP_CON1 = (u32)rop_con1;
+}
+
+
+/*************************************************************
+Func:
+    RGA_set_color
+Description:
+    fill color some relate reg bit
+    bg_color/fg_color
+Author:
+    ZhangShengqin
+Date:
+    20012-2-2 10:59:25
+**************************************************************/
 
 static void
-RGA_set_color(u8 *base, const struct rga_req *msg)
-{
-    u32 *bRGA_SRC_TR_COLOR0;
-    u32 *bRGA_SRC_TR_COLOR1;
-    u32 *bRGA_SRC_BG_COLOR;
-    u32 *bRGA_SRC_FG_COLOR;
-
-
-    bRGA_SRC_BG_COLOR  = (u32 *)(base + RGA_SRC_BG_COLOR_OFFSET);
-    bRGA_SRC_FG_COLOR  = (u32 *)(base + RGA_SRC_FG_COLOR_OFFSET);
-
-    *bRGA_SRC_BG_COLOR = msg->bg_color;    /* 1bpp 0 */
-    *bRGA_SRC_FG_COLOR = msg->fg_color;    /* 1bpp 1 */
-
-    bRGA_SRC_TR_COLOR0 = (u32 *)(base + RGA_SRC_TR_COLOR0_OFFSET);
-    bRGA_SRC_TR_COLOR1 = (u32 *)(base + RGA_SRC_TR_COLOR1_OFFSET);
-
-    *bRGA_SRC_TR_COLOR0 = msg->color_key_min;
-    *bRGA_SRC_TR_COLOR1 = msg->color_key_max;
-}
-
-
-/*************************************************************
-Func:
-    RGA_set_fading
-Description:
-    fill fading some relate reg bit
-Author:
-    ZhangShengqin
-Date:
-    20012-2-2 10:59:25
-**************************************************************/
+RGA_set_color(u8 *base, const struct rga_req *msg)
+{
+    u32 *bRGA_SRC_TR_COLOR0;
+    u32 *bRGA_SRC_TR_COLOR1;
+    u32 *bRGA_SRC_BG_COLOR;
+    u32 *bRGA_SRC_FG_COLOR;
+
+
+    bRGA_SRC_BG_COLOR  = (u32 *)(base + RGA_SRC_BG_COLOR_OFFSET);
+    bRGA_SRC_FG_COLOR  = (u32 *)(base + RGA_SRC_FG_COLOR_OFFSET);
+
+    *bRGA_SRC_BG_COLOR = msg->bg_color;    /* 1bpp 0 */
+    *bRGA_SRC_FG_COLOR = msg->fg_color;    /* 1bpp 1 */
+
+    bRGA_SRC_TR_COLOR0 = (u32 *)(base + RGA_SRC_TR_COLOR0_OFFSET);
+    bRGA_SRC_TR_COLOR1 = (u32 *)(base + RGA_SRC_TR_COLOR1_OFFSET);
+
+    *bRGA_SRC_TR_COLOR0 = msg->color_key_min;
+    *bRGA_SRC_TR_COLOR1 = msg->color_key_max;
+}
+
+
+/*************************************************************
+Func:
+    RGA_set_fading
+Description:
+    fill fading some relate reg bit
+Author:
+    ZhangShengqin
+Date:
+    20012-2-2 10:59:25
+**************************************************************/
 
 static s32
-RGA_set_fading(u8 *base, const struct rga_req *msg)
-{
-    u32 *bRGA_FADING_CON;
-    u8 r, g, b;
-    u32 reg = 0;
-
-    bRGA_FADING_CON = (u32 *)(base + RGA_FADING_CON_OFFSET);
-
-    b = msg->fading.b;
-    g = msg->fading.g;
-    r = msg->fading.r;
-
-    reg = (r<<8) | (g<<16) | (b<<24) | reg;
-
-    *bRGA_FADING_CON = reg;
-
-    return 0;
-}
-
-
-/*************************************************************
-Func:
-    RGA_set_pat
-Description:
-    fill patten some relate reg bit
-Author:
-    ZhangShengqin
-Date:
-    20012-2-2 10:59:25
-**************************************************************/
+RGA_set_fading(u8 *base, const struct rga_req *msg)
+{
+    u32 *bRGA_FADING_CON;
+    u8 r, g, b;
+    u32 reg = 0;
+
+    bRGA_FADING_CON = (u32 *)(base + RGA_FADING_CON_OFFSET);
+
+    b = msg->fading.b;
+    g = msg->fading.g;
+    r = msg->fading.r;
+
+    reg = (r<<8) | (g<<16) | (b<<24) | reg;
+
+    *bRGA_FADING_CON = reg;
+
+    return 0;
+}
+
+
+/*************************************************************
+Func:
+    RGA_set_pat
+Description:
+    fill patten some relate reg bit
+Author:
+    ZhangShengqin
+Date:
+    20012-2-2 10:59:25
+**************************************************************/
 
 static s32
-RGA_set_pat(u8 *base, const struct rga_req *msg)
-{
-    u32 *bRGA_PAT_CON;
-    u32 *bRGA_PAT_START_POINT;
-    u32 reg = 0;
-
-    bRGA_PAT_START_POINT = (u32 *)(base + RGA_PAT_START_POINT_OFFSET);
-
-    bRGA_PAT_CON = (u32 *)(base + RGA_PAT_CON_OFFSET);
-
-    *bRGA_PAT_START_POINT = (msg->pat.act_w * msg->pat.y_offset) + msg->pat.x_offset;
-
-    reg = (msg->pat.act_w - 1) | ((msg->pat.act_h - 1) << 8) | (msg->pat.x_offset << 16) | (msg->pat.y_offset << 24);
-    *bRGA_PAT_CON = reg;
-
-    return 0;
-}
-
-
-
-
-/*************************************************************
-Func:
-    RGA_set_bitblt_reg_info
-Description:
-    fill bitblt mode relate ren info
-Author:
-    ZhangShengqin
-Date:
-    20012-2-2 10:59:25
-**************************************************************/
+RGA_set_pat(u8 *base, const struct rga_req *msg)
+{
+    u32 *bRGA_PAT_CON;
+    u32 *bRGA_PAT_START_POINT;
+    u32 reg = 0;
+
+    bRGA_PAT_START_POINT = (u32 *)(base + RGA_PAT_START_POINT_OFFSET);
+
+    bRGA_PAT_CON = (u32 *)(base + RGA_PAT_CON_OFFSET);
+
+    *bRGA_PAT_START_POINT = (msg->pat.act_w * msg->pat.y_offset) + msg->pat.x_offset;
+
+    reg = (msg->pat.act_w - 1) | ((msg->pat.act_h - 1) << 8) | (msg->pat.x_offset << 16) | (msg->pat.y_offset << 24);
+    *bRGA_PAT_CON = reg;
+
+    return 0;
+}
+
+
+
+
+/*************************************************************
+Func:
+    RGA_set_bitblt_reg_info
+Description:
+    fill bitblt mode relate ren info
+Author:
+    ZhangShengqin
+Date:
+    20012-2-2 10:59:25
+**************************************************************/
 
 static void
-RGA_set_bitblt_reg_info(u8 *base, const struct rga_req * msg, TILE_INFO *tile)
-{
-    u32 *bRGA_SRC_Y_MST;
-    u32 *bRGA_SRC_CB_MST;
-    u32 *bRGA_SRC_CR_MST;
-    u32 *bRGA_SRC_X_PARA;
-    u32 *bRGA_SRC_Y_PARA;
-    u32 *bRGA_SRC_TILE_XINFO;
-    u32 *bRGA_SRC_TILE_YINFO;
-    u32 *bRGA_SRC_TILE_H_INCR;
-    u32 *bRGA_SRC_TILE_V_INCR;
-    u32 *bRGA_SRC_TILE_OFFSETX;
-    u32 *bRGA_SRC_TILE_OFFSETY;
-
-    u32 *bRGA_DST_MST;
-    u32 *bRGA_DST_CTR_INFO;
-
-    s32 m0, m1, m2, m3;
-    s32 pos[8];
-    //s32 x_dx, x_dy, y_dx, y_dy;
-    s32 xmin, xmax, ymin, ymax;
-    s32 xp, yp;
-    u32 y_addr, u_addr, v_addr;
-    u32 pixel_width, stride;
-
-    u_addr = v_addr = 0;
-
-    /* src info */
-
-    bRGA_SRC_Y_MST = (u32 *)(base + RGA_SRC_Y_MST_OFFSET);
-    bRGA_SRC_CB_MST = (u32 *)(base + RGA_SRC_CB_MST_OFFSET);
-    bRGA_SRC_CR_MST = (u32 *)(base + RGA_SRC_CR_MST_OFFSET);
-
-    bRGA_SRC_X_PARA = (u32 *)(base + RGA_SRC_X_PARA_OFFSET);
-    bRGA_SRC_Y_PARA = (u32 *)(base + RGA_SRC_Y_PARA_OFFSET);
-
-    bRGA_SRC_TILE_XINFO = (u32 *)(base + RGA_SRC_TILE_XINFO_OFFSET);
-    bRGA_SRC_TILE_YINFO = (u32 *)(base + RGA_SRC_TILE_YINFO_OFFSET);
-    bRGA_SRC_TILE_H_INCR = (u32 *)(base + RGA_SRC_TILE_H_INCR_OFFSET);
-    bRGA_SRC_TILE_V_INCR = (u32 *)(base + RGA_SRC_TILE_V_INCR_OFFSET);
-    bRGA_SRC_TILE_OFFSETX = (u32 *)(base + RGA_SRC_TILE_OFFSETX_OFFSET);
-    bRGA_SRC_TILE_OFFSETY = (u32 *)(base + RGA_SRC_TILE_OFFSETY_OFFSET);
-
-    bRGA_DST_MST = (u32 *)(base + RGA_DST_MST_OFFSET);
-    bRGA_DST_CTR_INFO = (u32 *)(base + RGA_DST_CTR_INFO_OFFSET);
-
-    /* Matrix reg fill */
-    m0 = (s32)(tile->matrix[0] >> 18);
-    m1 = (s32)(tile->matrix[1] >> 18);
-    m2 = (s32)(tile->matrix[2] >> 18);
-    m3 = (s32)(tile->matrix[3] >> 18);
-
-    *bRGA_SRC_X_PARA = (m0 & 0xffff) | (m2 << 16);
-    *bRGA_SRC_Y_PARA = (m1 & 0xffff) | (m3 << 16);
-
-    /* src tile information setting */
-    if(msg->rotate_mode != 0)//add by hxx,2011.7.12,for rtl0707,when line scanning ,do not calc src tile info
-    {
-        *bRGA_SRC_TILE_XINFO = (tile->tile_start_x_coor & 0xffff) | (tile->tile_w << 16);
-        *bRGA_SRC_TILE_YINFO = (tile->tile_start_y_coor & 0xffff) | (tile->tile_h << 16);
-
-        *bRGA_SRC_TILE_H_INCR = ((tile->x_dx) & 0xffff) | ((tile->x_dy) << 16);
-        *bRGA_SRC_TILE_V_INCR = ((tile->y_dx) & 0xffff) | ((tile->y_dy) << 16);
-
-        *bRGA_SRC_TILE_OFFSETX = tile->tile_xoff;
-        *bRGA_SRC_TILE_OFFSETY = tile->tile_yoff;
-    }
-
-    pixel_width = RGA_pixel_width_init(msg->src.format);
-
-    stride = ((msg->src.vir_w * pixel_width) + 3) & (~3);
-
-    if ((msg->rotate_mode == 1)||(msg->rotate_mode == 2)||(msg->rotate_mode == 3))
-    {
-        pos[0] = tile->tile_start_x_coor<<8;
-        pos[1] = tile->tile_start_y_coor<<8;
-
-        pos[2] = pos[0];
-        pos[3] = pos[1] + tile->tile_h;
-
-        pos[4] = pos[0] + tile->tile_w;
-        pos[5] = pos[1] + tile->tile_h;
-
-        pos[6] = pos[0] + tile->tile_w;
-        pos[7] = pos[1];
-
-        pos[0] >>= 11;
-        pos[1] >>= 11;
-
-        pos[2] >>= 11;
-        pos[3] >>= 11;
-
-        pos[4] >>= 11;
-        pos[5] >>= 11;
-
-        pos[6] >>= 11;
-        pos[7] >>= 11;
-
-        xmax = (MAX(MAX(MAX(pos[0], pos[2]), pos[4]), pos[6]) + 1);
-        xmin = (MIN(MIN(MIN(pos[0], pos[2]), pos[4]), pos[6]));
-
-        ymax = (MAX(MAX(MAX(pos[1], pos[3]), pos[5]), pos[7]) + 1);
-        ymin = (MIN(MIN(MIN(pos[1], pos[3]), pos[5]), pos[7]));
-
-        xp = xmin + msg->src.x_offset;
-        yp = ymin + msg->src.y_offset;
-
-        if (!((xmax < 0)||(xmin > msg->src.act_w - 1)||(ymax < 0)||(ymin > msg->src.act_h - 1)))
-        {
-            xp = CLIP(xp, msg->src.x_offset, msg->src.x_offset + msg->src.act_w - 1);
-            yp = CLIP(yp, msg->src.y_offset, msg->src.y_offset + msg->src.act_h - 1);
-        }
-
-        switch(msg->src.format)
-        {
-            case RK_FORMAT_YCbCr_420_P :
-                y_addr = msg->src.yrgb_addr + yp*stride + xp;
-                u_addr = msg->src.uv_addr + (yp>>1)*(stride>>1) + (xp>>1);
-                v_addr = msg->src.v_addr  + (yp>>1)*(stride>>1) + (xp>>1);
-                break;
-            case RK_FORMAT_YCbCr_420_SP :
-                y_addr = msg->src.yrgb_addr + yp*stride + xp;
-                u_addr = msg->src.uv_addr + (yp>>1)*stride + ((xp>>1)<<1);
-                break;
-            case RK_FORMAT_YCbCr_422_P :
-                y_addr = msg->src.yrgb_addr + yp*stride + xp;
-                u_addr = msg->src.uv_addr + (yp)*(stride>>1) + (xp>>1);
-                v_addr = msg->src.v_addr  + (yp)*(stride>>1) + (xp>>1);
-                break;
-            case RK_FORMAT_YCbCr_422_SP:
-                y_addr = msg->src.yrgb_addr + yp*stride + xp;
-                u_addr = msg->src.uv_addr  + yp*stride + ((xp>>1)<<1);
-                break;
-            case RK_FORMAT_YCrCb_420_P :
-                y_addr = msg->src.yrgb_addr + yp*stride + xp;
-                u_addr = msg->src.uv_addr + (yp>>1)*(stride>>1) + (xp>>1);
-                v_addr = msg->src.v_addr  + (yp>>1)*(stride>>1) + (xp>>1);
-                break;
-            case RK_FORMAT_YCrCb_420_SP :
-                y_addr = msg->src.yrgb_addr + yp*stride + xp;
-                u_addr = msg->src.uv_addr + (yp>>1)*stride + ((xp>>1)<<1);
-                break;
-            case RK_FORMAT_YCrCb_422_P :
-                y_addr = msg->src.yrgb_addr + yp*stride + xp;
-                u_addr = msg->src.uv_addr + (yp)*(stride>>1) + (xp>>1);
-                v_addr = msg->src.v_addr  + (yp)*(stride>>1) + (xp>>1);
-                break;
-            case RK_FORMAT_YCrCb_422_SP:
-                y_addr = msg->src.yrgb_addr + yp*stride + xp;
-                u_addr = msg->src.uv_addr  + yp*stride + ((xp>>1)<<1);
-                break;
-            default :
-                y_addr = msg->src.yrgb_addr + yp*stride + xp*pixel_width;
-                break;
-        }
-
-        *bRGA_SRC_Y_MST = y_addr;
-        *bRGA_SRC_CB_MST = u_addr;
-        *bRGA_SRC_CR_MST = v_addr;
-    }
-
-    /*dst info*/
-    pixel_width = RGA_pixel_width_init(msg->dst.format);
-    stride = (msg->dst.vir_w * pixel_width + 3) & (~3);
-    *bRGA_DST_MST = (u32)msg->dst.yrgb_addr + (tile->dst_ctrl.y_off * stride) + (tile->dst_ctrl.x_off * pixel_width);
-    *bRGA_DST_CTR_INFO = (tile->dst_ctrl.w) | ((tile->dst_ctrl.h) << 16);
-
-    *bRGA_DST_CTR_INFO |= ((1<<29) | (1<<28));
-}
-
-
-
-
-/*************************************************************
-Func:
-    RGA_set_color_palette_reg_info
-Description:
-    fill color palette process some relate reg bit
-Author:
-    ZhangShengqin
-Date:
-    20012-2-2 10:59:25
-**************************************************************/
+RGA_set_bitblt_reg_info(u8 *base, const struct rga_req * msg, TILE_INFO *tile)
+{
+    u32 *bRGA_SRC_Y_MST;
+    u32 *bRGA_SRC_CB_MST;
+    u32 *bRGA_SRC_CR_MST;
+    u32 *bRGA_SRC_X_PARA;
+    u32 *bRGA_SRC_Y_PARA;
+    u32 *bRGA_SRC_TILE_XINFO;
+    u32 *bRGA_SRC_TILE_YINFO;
+    u32 *bRGA_SRC_TILE_H_INCR;
+    u32 *bRGA_SRC_TILE_V_INCR;
+    u32 *bRGA_SRC_TILE_OFFSETX;
+    u32 *bRGA_SRC_TILE_OFFSETY;
+
+    u32 *bRGA_DST_MST;
+    u32 *bRGA_DST_CTR_INFO;
+
+    s32 m0, m1, m2, m3;
+    s32 pos[8];
+    //s32 x_dx, x_dy, y_dx, y_dy;
+    s32 xmin, xmax, ymin, ymax;
+    s32 xp, yp;
+    u32 y_addr, u_addr, v_addr;
+    u32 pixel_width, stride;
+
+    u_addr = v_addr = 0;
+
+    /* src info */
+
+    bRGA_SRC_Y_MST = (u32 *)(base + RGA_SRC_Y_MST_OFFSET);
+    bRGA_SRC_CB_MST = (u32 *)(base + RGA_SRC_CB_MST_OFFSET);
+    bRGA_SRC_CR_MST = (u32 *)(base + RGA_SRC_CR_MST_OFFSET);
+
+    bRGA_SRC_X_PARA = (u32 *)(base + RGA_SRC_X_PARA_OFFSET);
+    bRGA_SRC_Y_PARA = (u32 *)(base + RGA_SRC_Y_PARA_OFFSET);
+
+    bRGA_SRC_TILE_XINFO = (u32 *)(base + RGA_SRC_TILE_XINFO_OFFSET);
+    bRGA_SRC_TILE_YINFO = (u32 *)(base + RGA_SRC_TILE_YINFO_OFFSET);
+    bRGA_SRC_TILE_H_INCR = (u32 *)(base + RGA_SRC_TILE_H_INCR_OFFSET);
+    bRGA_SRC_TILE_V_INCR = (u32 *)(base + RGA_SRC_TILE_V_INCR_OFFSET);
+    bRGA_SRC_TILE_OFFSETX = (u32 *)(base + RGA_SRC_TILE_OFFSETX_OFFSET);
+    bRGA_SRC_TILE_OFFSETY = (u32 *)(base + RGA_SRC_TILE_OFFSETY_OFFSET);
+
+    bRGA_DST_MST = (u32 *)(base + RGA_DST_MST_OFFSET);
+    bRGA_DST_CTR_INFO = (u32 *)(base + RGA_DST_CTR_INFO_OFFSET);
+
+    /* Matrix reg fill */
+    m0 = (s32)(tile->matrix[0] >> 18);
+    m1 = (s32)(tile->matrix[1] >> 18);
+    m2 = (s32)(tile->matrix[2] >> 18);
+    m3 = (s32)(tile->matrix[3] >> 18);
+
+    *bRGA_SRC_X_PARA = (m0 & 0xffff) | (m2 << 16);
+    *bRGA_SRC_Y_PARA = (m1 & 0xffff) | (m3 << 16);
+
+    /* src tile information setting */
+    if(msg->rotate_mode != 0)//add by hxx,2011.7.12,for rtl0707,when line scanning ,do not calc src tile info
+    {
+        *bRGA_SRC_TILE_XINFO = (tile->tile_start_x_coor & 0xffff) | (tile->tile_w << 16);
+        *bRGA_SRC_TILE_YINFO = (tile->tile_start_y_coor & 0xffff) | (tile->tile_h << 16);
+
+        *bRGA_SRC_TILE_H_INCR = ((tile->x_dx) & 0xffff) | ((tile->x_dy) << 16);
+        *bRGA_SRC_TILE_V_INCR = ((tile->y_dx) & 0xffff) | ((tile->y_dy) << 16);
+
+        *bRGA_SRC_TILE_OFFSETX = tile->tile_xoff;
+        *bRGA_SRC_TILE_OFFSETY = tile->tile_yoff;
+    }
+
+    pixel_width = RGA_pixel_width_init(msg->src.format);
+
+    stride = ((msg->src.vir_w * pixel_width) + 3) & (~3);
+
+    if ((msg->rotate_mode == 1)||(msg->rotate_mode == 2)||(msg->rotate_mode == 3))
+    {
+        pos[0] = tile->tile_start_x_coor<<8;
+        pos[1] = tile->tile_start_y_coor<<8;
+
+        pos[2] = pos[0];
+        pos[3] = pos[1] + tile->tile_h;
+
+        pos[4] = pos[0] + tile->tile_w;
+        pos[5] = pos[1] + tile->tile_h;
+
+        pos[6] = pos[0] + tile->tile_w;
+        pos[7] = pos[1];
+
+        pos[0] >>= 11;
+        pos[1] >>= 11;
+
+        pos[2] >>= 11;
+        pos[3] >>= 11;
+
+        pos[4] >>= 11;
+        pos[5] >>= 11;
+
+        pos[6] >>= 11;
+        pos[7] >>= 11;
+
+        xmax = (MAX(MAX(MAX(pos[0], pos[2]), pos[4]), pos[6]) + 1);
+        xmin = (MIN(MIN(MIN(pos[0], pos[2]), pos[4]), pos[6]));
+
+        ymax = (MAX(MAX(MAX(pos[1], pos[3]), pos[5]), pos[7]) + 1);
+        ymin = (MIN(MIN(MIN(pos[1], pos[3]), pos[5]), pos[7]));
+
+        xp = xmin + msg->src.x_offset;
+        yp = ymin + msg->src.y_offset;
+
+        if (!((xmax < 0)||(xmin > msg->src.act_w - 1)||(ymax < 0)||(ymin > msg->src.act_h - 1)))
+        {
+            xp = CLIP(xp, msg->src.x_offset, msg->src.x_offset + msg->src.act_w - 1);
+            yp = CLIP(yp, msg->src.y_offset, msg->src.y_offset + msg->src.act_h - 1);
+        }
+
+        switch(msg->src.format)
+        {
+            case RK_FORMAT_YCbCr_420_P :
+                y_addr = msg->src.yrgb_addr + yp*stride + xp;
+                u_addr = msg->src.uv_addr + (yp>>1)*(stride>>1) + (xp>>1);
+                v_addr = msg->src.v_addr  + (yp>>1)*(stride>>1) + (xp>>1);
+                break;
+            case RK_FORMAT_YCbCr_420_SP :
+                y_addr = msg->src.yrgb_addr + yp*stride + xp;
+                u_addr = msg->src.uv_addr + (yp>>1)*stride + ((xp>>1)<<1);
+                break;
+            case RK_FORMAT_YCbCr_422_P :
+                y_addr = msg->src.yrgb_addr + yp*stride + xp;
+                u_addr = msg->src.uv_addr + (yp)*(stride>>1) + (xp>>1);
+                v_addr = msg->src.v_addr  + (yp)*(stride>>1) + (xp>>1);
+                break;
+            case RK_FORMAT_YCbCr_422_SP:
+                y_addr = msg->src.yrgb_addr + yp*stride + xp;
+                u_addr = msg->src.uv_addr  + yp*stride + ((xp>>1)<<1);
+                break;
+            case RK_FORMAT_YCrCb_420_P :
+                y_addr = msg->src.yrgb_addr + yp*stride + xp;
+                u_addr = msg->src.uv_addr + (yp>>1)*(stride>>1) + (xp>>1);
+                v_addr = msg->src.v_addr  + (yp>>1)*(stride>>1) + (xp>>1);
+                break;
+            case RK_FORMAT_YCrCb_420_SP :
+                y_addr = msg->src.yrgb_addr + yp*stride + xp;
+                u_addr = msg->src.uv_addr + (yp>>1)*stride + ((xp>>1)<<1);
+                break;
+            case RK_FORMAT_YCrCb_422_P :
+                y_addr = msg->src.yrgb_addr + yp*stride + xp;
+                u_addr = msg->src.uv_addr + (yp)*(stride>>1) + (xp>>1);
+                v_addr = msg->src.v_addr  + (yp)*(stride>>1) + (xp>>1);
+                break;
+            case RK_FORMAT_YCrCb_422_SP:
+                y_addr = msg->src.yrgb_addr + yp*stride + xp;
+                u_addr = msg->src.uv_addr  + yp*stride + ((xp>>1)<<1);
+                break;
+            default :
+                y_addr = msg->src.yrgb_addr + yp*stride + xp*pixel_width;
+                break;
+        }
+
+        *bRGA_SRC_Y_MST = y_addr;
+        *bRGA_SRC_CB_MST = u_addr;
+        *bRGA_SRC_CR_MST = v_addr;
+    }
+
+    /*dst info*/
+    pixel_width = RGA_pixel_width_init(msg->dst.format);
+    stride = (msg->dst.vir_w * pixel_width + 3) & (~3);
+    *bRGA_DST_MST = (u32)msg->dst.yrgb_addr + (tile->dst_ctrl.y_off * stride) + (tile->dst_ctrl.x_off * pixel_width);
+    *bRGA_DST_CTR_INFO = (tile->dst_ctrl.w) | ((tile->dst_ctrl.h) << 16);
+
+    *bRGA_DST_CTR_INFO |= ((1<<29) | (1<<28));
+}
+
+
+
+
+/*************************************************************
+Func:
+    RGA_set_color_palette_reg_info
+Description:
+    fill color palette process some relate reg bit
+Author:
+    ZhangShengqin
+Date:
+    20012-2-2 10:59:25
+**************************************************************/
 
 static void
-RGA_set_color_palette_reg_info(u8 *base, const struct rga_req *msg)
-{
-    u32 *bRGA_SRC_Y_MST;
-    u32 p;
-    s16 x_off, y_off;
-    u16 src_stride;
-    u8  shift;
-    u16 sw, byte_num;
-
-    x_off = msg->src.x_offset;
-    y_off = msg->src.y_offset;
-
-    sw = msg->src.vir_w;
-    shift = 3 - (msg->palette_mode & 3);
-    byte_num = sw >> shift;
-    src_stride = (byte_num + 3) & (~3);
-
-    p = msg->src.yrgb_addr;
-    p = p + (x_off>>shift) + y_off*src_stride;
-
-    bRGA_SRC_Y_MST = (u32 *)(base + RGA_SRC_Y_MST_OFFSET);
-    *bRGA_SRC_Y_MST = (u32)p;
-}
-
-
-/*************************************************************
-Func:
-    RGA_set_color_fill_reg_info
-Description:
-    fill color fill process some relate reg bit
-Author:
-    ZhangShengqin
-Date:
-    20012-2-2 10:59:25
-**************************************************************/
+RGA_set_color_palette_reg_info(u8 *base, const struct rga_req *msg)
+{
+    u32 *bRGA_SRC_Y_MST;
+    u32 p;
+    s16 x_off, y_off;
+    u16 src_stride;
+    u8  shift;
+    u16 sw, byte_num;
+
+    x_off = msg->src.x_offset;
+    y_off = msg->src.y_offset;
+
+    sw = msg->src.vir_w;
+    shift = 3 - (msg->palette_mode & 3);
+    byte_num = sw >> shift;
+    src_stride = (byte_num + 3) & (~3);
+
+    p = msg->src.yrgb_addr;
+    p = p + (x_off>>shift) + y_off*src_stride;
+
+    bRGA_SRC_Y_MST = (u32 *)(base + RGA_SRC_Y_MST_OFFSET);
+    *bRGA_SRC_Y_MST = (u32)p;
+}
+
+
+/*************************************************************
+Func:
+    RGA_set_color_fill_reg_info
+Description:
+    fill color fill process some relate reg bit
+Author:
+    ZhangShengqin
+Date:
+    20012-2-2 10:59:25
+**************************************************************/
 static void
-RGA_set_color_fill_reg_info(u8 *base, const struct rga_req *msg)
-{
-
-    u32 *bRGA_CP_GR_A;
-    u32 *bRGA_CP_GR_B;
-    u32 *bRGA_CP_GR_G;
-    u32 *bRGA_CP_GR_R;
-
-    u32 *bRGA_PAT_CON;
-
-    bRGA_CP_GR_A = (u32 *)(base + RGA_CP_GR_A_OFFSET);
-    bRGA_CP_GR_B = (u32 *)(base + RGA_CP_GR_B_OFFSET);
-    bRGA_CP_GR_G = (u32 *)(base + RGA_CP_GR_G_OFFSET);
-    bRGA_CP_GR_R = (u32 *)(base + RGA_CP_GR_R_OFFSET);
-
-    bRGA_PAT_CON = (u32 *)(base + RGA_PAT_CON_OFFSET);
-
-    *bRGA_CP_GR_A = (msg->gr_color.gr_x_a & 0xffff) | (msg->gr_color.gr_y_a << 16);
-    *bRGA_CP_GR_B = (msg->gr_color.gr_x_b & 0xffff) | (msg->gr_color.gr_y_b << 16);
-    *bRGA_CP_GR_G = (msg->gr_color.gr_x_g & 0xffff) | (msg->gr_color.gr_y_g << 16);
-    *bRGA_CP_GR_R = (msg->gr_color.gr_x_r & 0xffff) | (msg->gr_color.gr_y_r << 16);
-
-    *bRGA_PAT_CON = (msg->pat.vir_w-1) | ((msg->pat.vir_h-1) << 8) | (msg->pat.x_offset << 16) | (msg->pat.y_offset << 24);
-
-}
-
-
-/*************************************************************
-Func:
-    RGA_set_line_drawing_reg_info
-Description:
-    fill line drawing process some relate reg bit
-Author:
-    ZhangShengqin
-Date:
-    20012-2-2 10:59:25
-**************************************************************/
+RGA_set_color_fill_reg_info(u8 *base, const struct rga_req *msg)
+{
+
+    u32 *bRGA_CP_GR_A;
+    u32 *bRGA_CP_GR_B;
+    u32 *bRGA_CP_GR_G;
+    u32 *bRGA_CP_GR_R;
+
+    u32 *bRGA_PAT_CON;
+
+    bRGA_CP_GR_A = (u32 *)(base + RGA_CP_GR_A_OFFSET);
+    bRGA_CP_GR_B = (u32 *)(base + RGA_CP_GR_B_OFFSET);
+    bRGA_CP_GR_G = (u32 *)(base + RGA_CP_GR_G_OFFSET);
+    bRGA_CP_GR_R = (u32 *)(base + RGA_CP_GR_R_OFFSET);
+
+    bRGA_PAT_CON = (u32 *)(base + RGA_PAT_CON_OFFSET);
+
+    *bRGA_CP_GR_A = (msg->gr_color.gr_x_a & 0xffff) | (msg->gr_color.gr_y_a << 16);
+    *bRGA_CP_GR_B = (msg->gr_color.gr_x_b & 0xffff) | (msg->gr_color.gr_y_b << 16);
+    *bRGA_CP_GR_G = (msg->gr_color.gr_x_g & 0xffff) | (msg->gr_color.gr_y_g << 16);
+    *bRGA_CP_GR_R = (msg->gr_color.gr_x_r & 0xffff) | (msg->gr_color.gr_y_r << 16);
+
+    *bRGA_PAT_CON = (msg->pat.vir_w-1) | ((msg->pat.vir_h-1) << 8) | (msg->pat.x_offset << 16) | (msg->pat.y_offset << 24);
+
+}
+
+
+/*************************************************************
+Func:
+    RGA_set_line_drawing_reg_info
+Description:
+    fill line drawing process some relate reg bit
+Author:
+    ZhangShengqin
+Date:
+    20012-2-2 10:59:25
+**************************************************************/
 
 static s32 RGA_set_line_drawing_reg_info(u8 *base, const struct rga_req *msg)
-{
-    u32 *bRGA_LINE_DRAW;
-    u32 *bRGA_DST_VIR_INFO;
-    u32 *bRGA_LINE_DRAW_XY_INFO;
-    u32 *bRGA_LINE_DRAW_WIDTH;
-    u32 *bRGA_LINE_DRAWING_COLOR;
-    u32 *bRGA_LINE_DRAWING_MST;
-
-    u32  reg = 0;
-
-    s16 x_width, y_width;
-    u16 abs_x, abs_y, delta;
-    u16 stride;
-    u8 pw;
-    u32 start_addr;
-    u8 line_dir, dir_major, dir_semi_major;
-    u16 major_width;
-
-    bRGA_LINE_DRAW = (u32 *)(base + RGA_LINE_DRAW_OFFSET);
-    bRGA_DST_VIR_INFO = (u32 *)(base + RGA_DST_VIR_INFO_OFFSET);
-    bRGA_LINE_DRAW_XY_INFO = (u32 *)(base + RGA_LINE_DRAW_XY_INFO_OFFSET);
-    bRGA_LINE_DRAW_WIDTH = (u32 *)(base + RGA_LINE_DRAWING_WIDTH_OFFSET);
-    bRGA_LINE_DRAWING_COLOR = (u32 *)(base + RGA_LINE_DRAWING_COLOR_OFFSET);
-    bRGA_LINE_DRAWING_MST = (u32 *)(base + RGA_LINE_DRAWING_MST_OFFSET);
-
-    pw = RGA_pixel_width_init(msg->dst.format);
-
-    stride = (msg->dst.vir_w * pw + 3) & (~3);
-
-    start_addr = msg->dst.yrgb_addr
-                + (msg->line_draw_info.start_point.y * stride)
-                + (msg->line_draw_info.start_point.x * pw);
-
-    x_width = msg->line_draw_info.start_point.x - msg->line_draw_info.end_point.x;
-    y_width = msg->line_draw_info.start_point.y - msg->line_draw_info.end_point.y;
-
-    abs_x = abs(x_width);
-    abs_y = abs(y_width);
-
-    if (abs_x >= abs_y)
-    {
-        if (y_width > 0)
-            dir_semi_major = 1;
-        else
-            dir_semi_major = 0;
-
-        if (x_width > 0)
-            dir_major = 1;
-        else
-            dir_major = 0;
-
-        if((abs_x == 0)||(abs_y == 0))
-            delta = 0;
-        else
-            delta = (abs_y<<12)/abs_x;
-
-        if (delta >> 12)
-            delta -= 1;
-
-        major_width = abs_x;
-        line_dir = 0;
-    }
-    else
-    {
-        if (x_width > 0)
-            dir_semi_major = 1;
-        else
-            dir_semi_major = 0;
-
-        if (y_width > 0)
-            dir_major = 1;
-        else
-            dir_major = 0;
-
-        delta = (abs_x<<12)/abs_y;
-        major_width = abs_y;
-        line_dir = 1;
-    }
-
-    reg = (reg & (~m_RGA_LINE_DRAW_MAJOR_WIDTH))     | (s_RGA_LINE_DRAW_MAJOR_WIDTH(major_width));
-    reg = (reg & (~m_RGA_LINE_DRAW_LINE_DIRECTION))  | (s_RGA_LINE_DRAW_LINE_DIRECTION(line_dir));
-    reg = (reg & (~m_RGA_LINE_DRAW_LINE_WIDTH))      | (s_RGA_LINE_DRAW_LINE_WIDTH(msg->line_draw_info.line_width - 1));
-    reg = (reg & (~m_RGA_LINE_DRAW_INCR_VALUE))      | (s_RGA_LINE_DRAW_INCR_VALUE(delta));
-    reg = (reg & (~m_RGA_LINE_DRAW_DIR_SEMI_MAJOR))  | (s_RGA_LINE_DRAW_DIR_SEMI_MAJOR(dir_semi_major));
-    reg = (reg & (~m_RGA_LINE_DRAW_DIR_MAJOR))       | (s_RGA_LINE_DRAW_DIR_MAJOR(dir_major));
-    reg = (reg & (~m_RGA_LINE_DRAW_LAST_POINT))      | (s_RGA_LINE_DRAW_LAST_POINT(msg->line_draw_info.flag >> 1));
-    reg = (reg & (~m_RGA_LINE_DRAW_ANTI_ALISING))    | (s_RGA_LINE_DRAW_ANTI_ALISING(msg->line_draw_info.flag));
-
-    *bRGA_LINE_DRAW = reg;
-
-    reg = (msg->line_draw_info.start_point.x & 0xfff) | ((msg->line_draw_info.start_point.y & 0xfff) << 16);
-    *bRGA_LINE_DRAW_XY_INFO = reg;
-
-    *bRGA_LINE_DRAW_WIDTH = msg->dst.vir_w;
-
-    *bRGA_LINE_DRAWING_COLOR = msg->line_draw_info.color;
-
-    *bRGA_LINE_DRAWING_MST = (u32)start_addr;
-
-    return 0;
-}
-
-
+{
+    u32 *bRGA_LINE_DRAW;
+    u32 *bRGA_DST_VIR_INFO;
+    u32 *bRGA_LINE_DRAW_XY_INFO;
+    u32 *bRGA_LINE_DRAW_WIDTH;
+    u32 *bRGA_LINE_DRAWING_COLOR;
+    u32 *bRGA_LINE_DRAWING_MST;
+
+    u32  reg = 0;
+
+    s16 x_width, y_width;
+    u16 abs_x, abs_y, delta;
+    u16 stride;
+    u8 pw;
+    u32 start_addr;
+    u8 line_dir, dir_major, dir_semi_major;
+    u16 major_width;
+
+    bRGA_LINE_DRAW = (u32 *)(base + RGA_LINE_DRAW_OFFSET);
+    bRGA_DST_VIR_INFO = (u32 *)(base + RGA_DST_VIR_INFO_OFFSET);
+    bRGA_LINE_DRAW_XY_INFO = (u32 *)(base + RGA_LINE_DRAW_XY_INFO_OFFSET);
+    bRGA_LINE_DRAW_WIDTH = (u32 *)(base + RGA_LINE_DRAWING_WIDTH_OFFSET);
+    bRGA_LINE_DRAWING_COLOR = (u32 *)(base + RGA_LINE_DRAWING_COLOR_OFFSET);
+    bRGA_LINE_DRAWING_MST = (u32 *)(base + RGA_LINE_DRAWING_MST_OFFSET);
+
+    pw = RGA_pixel_width_init(msg->dst.format);
+
+    stride = (msg->dst.vir_w * pw + 3) & (~3);
+
+    start_addr = msg->dst.yrgb_addr
+                + (msg->line_draw_info.start_point.y * stride)
+                + (msg->line_draw_info.start_point.x * pw);
+
+    x_width = msg->line_draw_info.start_point.x - msg->line_draw_info.end_point.x;
+    y_width = msg->line_draw_info.start_point.y - msg->line_draw_info.end_point.y;
+
+    abs_x = abs(x_width);
+    abs_y = abs(y_width);
+
+    if (abs_x >= abs_y)
+    {
+        if (y_width > 0)
+            dir_semi_major = 1;
+        else
+            dir_semi_major = 0;
+
+        if (x_width > 0)
+            dir_major = 1;
+        else
+            dir_major = 0;
+
+        if((abs_x == 0)||(abs_y == 0))
+            delta = 0;
+        else
+            delta = (abs_y<<12)/abs_x;
+
+        if (delta >> 12)
+            delta -= 1;
+
+        major_width = abs_x;
+        line_dir = 0;
+    }
+    else
+    {
+        if (x_width > 0)
+            dir_semi_major = 1;
+        else
+            dir_semi_major = 0;
+
+        if (y_width > 0)
+            dir_major = 1;
+        else
+            dir_major = 0;
+
+        delta = (abs_x<<12)/abs_y;
+        major_width = abs_y;
+        line_dir = 1;
+    }
+
+    reg = (reg & (~m_RGA_LINE_DRAW_MAJOR_WIDTH))     | (s_RGA_LINE_DRAW_MAJOR_WIDTH(major_width));
+    reg = (reg & (~m_RGA_LINE_DRAW_LINE_DIRECTION))  | (s_RGA_LINE_DRAW_LINE_DIRECTION(line_dir));
+    reg = (reg & (~m_RGA_LINE_DRAW_LINE_WIDTH))      | (s_RGA_LINE_DRAW_LINE_WIDTH(msg->line_draw_info.line_width - 1));
+    reg = (reg & (~m_RGA_LINE_DRAW_INCR_VALUE))      | (s_RGA_LINE_DRAW_INCR_VALUE(delta));
+    reg = (reg & (~m_RGA_LINE_DRAW_DIR_SEMI_MAJOR))  | (s_RGA_LINE_DRAW_DIR_SEMI_MAJOR(dir_semi_major));
+    reg = (reg & (~m_RGA_LINE_DRAW_DIR_MAJOR))       | (s_RGA_LINE_DRAW_DIR_MAJOR(dir_major));
+    reg = (reg & (~m_RGA_LINE_DRAW_LAST_POINT))      | (s_RGA_LINE_DRAW_LAST_POINT(msg->line_draw_info.flag >> 1));
+    reg = (reg & (~m_RGA_LINE_DRAW_ANTI_ALISING))    | (s_RGA_LINE_DRAW_ANTI_ALISING(msg->line_draw_info.flag));
+
+    *bRGA_LINE_DRAW = reg;
+
+    reg = (msg->line_draw_info.start_point.x & 0xfff) | ((msg->line_draw_info.start_point.y & 0xfff) << 16);
+    *bRGA_LINE_DRAW_XY_INFO = reg;
+
+    *bRGA_LINE_DRAW_WIDTH = msg->dst.vir_w;
+
+    *bRGA_LINE_DRAWING_COLOR = msg->line_draw_info.color;
+
+    *bRGA_LINE_DRAWING_MST = (u32)start_addr;
+
+    return 0;
+}
+
+
 /*full*/
 static s32
 RGA_set_filter_reg_info(u8 *base, const struct rga_req *msg)
-{
-    u32 *bRGA_BLUR_SHARP_INFO;
-    u32  reg = 0;
-
-    bRGA_BLUR_SHARP_INFO = (u32 *)(base + RGA_ALPHA_CON_OFFSET);
-
-    reg = *bRGA_BLUR_SHARP_INFO;
-
-    reg = ((reg & (~m_RGA_BLUR_SHARP_FILTER_TYPE)) | (s_RGA_BLUR_SHARP_FILTER_TYPE(msg->bsfilter_flag & 3)));
-    reg = ((reg & (~m_RGA_BLUR_SHARP_FILTER_MODE)) | (s_RGA_BLUR_SHARP_FILTER_MODE(msg->bsfilter_flag >>2)));
-
-    *bRGA_BLUR_SHARP_INFO = reg;
-
-    return 0;
-}
-
-
-/*full*/
+{
+    u32 *bRGA_BLUR_SHARP_INFO;
+    u32  reg = 0;
+
+    bRGA_BLUR_SHARP_INFO = (u32 *)(base + RGA_ALPHA_CON_OFFSET);
+
+    reg = *bRGA_BLUR_SHARP_INFO;
+
+    reg = ((reg & (~m_RGA_BLUR_SHARP_FILTER_TYPE)) | (s_RGA_BLUR_SHARP_FILTER_TYPE(msg->bsfilter_flag & 3)));
+    reg = ((reg & (~m_RGA_BLUR_SHARP_FILTER_MODE)) | (s_RGA_BLUR_SHARP_FILTER_MODE(msg->bsfilter_flag >>2)));
+
+    *bRGA_BLUR_SHARP_INFO = reg;
+
+    return 0;
+}
+
+
+/*full*/
 static s32
-RGA_set_pre_scale_reg_info(u8 *base, const struct rga_req *msg)
-{
-   u32 *bRGA_PRE_SCALE_INFO;
-   u32 reg = 0;
-   u32 h_ratio = 0;
-   u32 v_ratio = 0;
-   u32 ps_yuv_flag = 0;
-   u32 src_width, src_height;
-   u32 dst_width, dst_height;
-
-   src_width = msg->src.act_w;
-   src_height = msg->src.act_h;
-
-   dst_width = msg->dst.act_w;
-   dst_height = msg->dst.act_h;
-
-   if((dst_width == 0) || (dst_height == 0))
-   {
-        printk("pre scale reg info error ratio is divide zero\n");
-        return -EINVAL;
-   }
-
-   h_ratio = (src_width <<16) / dst_width;
-   v_ratio = (src_height<<16) / dst_height;
-
-   if (h_ratio <= (1<<16))
-       h_ratio = 0;
-   else if (h_ratio <= (2<<16))
-       h_ratio = 1;
-   else if (h_ratio <= (4<<16))
-       h_ratio = 2;
-   else if (h_ratio <= (8<<16))
-       h_ratio = 3;
-
-   if (v_ratio <= (1<<16))
-       v_ratio = 0;
-   else if (v_ratio <= (2<<16))
-       v_ratio = 1;
-   else if (v_ratio <= (4<<16))
-       v_ratio = 2;
-   else if (v_ratio <= (8<<16))
-       v_ratio = 3;
-
-   if(msg->src.format == msg->dst.format)
-        ps_yuv_flag = 0;
-    else
-        ps_yuv_flag = 1;
-
-   bRGA_PRE_SCALE_INFO = (u32 *)(base + RGA_ALPHA_CON_OFFSET);
-
-   reg = *bRGA_PRE_SCALE_INFO;
-   reg = ((reg & (~m_RGA_PRE_SCALE_HOR_RATIO)) | (s_RGA_PRE_SCALE_HOR_RATIO((u8)h_ratio)));
-   reg = ((reg & (~m_RGA_PRE_SCALE_VER_RATIO)) | (s_RGA_PRE_SCALE_VER_RATIO((u8)v_ratio)));
-   reg = ((reg & (~m_RGA_PRE_SCALE_OUTPUT_FORMAT)) | (s_RGA_PRE_SCALE_OUTPUT_FORMAT(ps_yuv_flag)));
-
-   *bRGA_PRE_SCALE_INFO = reg;
-
-   return 0;
-}
-
-
-
+RGA_set_pre_scale_reg_info(u8 *base, const struct rga_req *msg)
+{
+   u32 *bRGA_PRE_SCALE_INFO;
+   u32 reg = 0;
+   u32 h_ratio = 0;
+   u32 v_ratio = 0;
+   u32 ps_yuv_flag = 0;
+   u32 src_width, src_height;
+   u32 dst_width, dst_height;
+
+   src_width = msg->src.act_w;
+   src_height = msg->src.act_h;
+
+   dst_width = msg->dst.act_w;
+   dst_height = msg->dst.act_h;
+
+   if((dst_width == 0) || (dst_height == 0))
+   {
+        printk("pre scale reg info error ratio is divide zero\n");
+        return -EINVAL;
+   }
+
+   h_ratio = (src_width <<16) / dst_width;
+   v_ratio = (src_height<<16) / dst_height;
+
+   if (h_ratio <= (1<<16))
+       h_ratio = 0;
+   else if (h_ratio <= (2<<16))
+       h_ratio = 1;
+   else if (h_ratio <= (4<<16))
+       h_ratio = 2;
+   else if (h_ratio <= (8<<16))
+       h_ratio = 3;
+
+   if (v_ratio <= (1<<16))
+       v_ratio = 0;
+   else if (v_ratio <= (2<<16))
+       v_ratio = 1;
+   else if (v_ratio <= (4<<16))
+       v_ratio = 2;
+   else if (v_ratio <= (8<<16))
+       v_ratio = 3;
+
+   if(msg->src.format == msg->dst.format)
+        ps_yuv_flag = 0;
+    else
+        ps_yuv_flag = 1;
+
+   bRGA_PRE_SCALE_INFO = (u32 *)(base + RGA_ALPHA_CON_OFFSET);
+
+   reg = *bRGA_PRE_SCALE_INFO;
+   reg = ((reg & (~m_RGA_PRE_SCALE_HOR_RATIO)) | (s_RGA_PRE_SCALE_HOR_RATIO((u8)h_ratio)));
+   reg = ((reg & (~m_RGA_PRE_SCALE_VER_RATIO)) | (s_RGA_PRE_SCALE_VER_RATIO((u8)v_ratio)));
+   reg = ((reg & (~m_RGA_PRE_SCALE_OUTPUT_FORMAT)) | (s_RGA_PRE_SCALE_OUTPUT_FORMAT(ps_yuv_flag)));
+
+   *bRGA_PRE_SCALE_INFO = reg;
+
+   return 0;
+}
+
+
+
 /*full*/
 static int
-RGA_set_update_palette_table_reg_info(u8 *base, const struct rga_req *msg)
-{
-    u32 *bRGA_LUT_MST;
-
-    if (!msg->LUT_addr) {
-        return -1;
-    }
-
-    bRGA_LUT_MST  = (u32 *)(base + RGA_LUT_MST_OFFSET);
-
-    *bRGA_LUT_MST = (u32)msg->LUT_addr;
-
-    return 0;
-}
-
-
-
+RGA_set_update_palette_table_reg_info(u8 *base, const struct rga_req *msg)
+{
+    u32 *bRGA_LUT_MST;
+
+    if (!msg->LUT_addr) {
+        return -1;
+    }
+
+    bRGA_LUT_MST  = (u32 *)(base + RGA_LUT_MST_OFFSET);
+
+    *bRGA_LUT_MST = (u32)msg->LUT_addr;
+
+    return 0;
+}
+
+
+
 /*full*/
 static int
-RGA_set_update_patten_buff_reg_info(u8 *base, const struct rga_req *msg)
-{
-    u32 *bRGA_PAT_MST;
-    u32 *bRGA_PAT_CON;
-    u32 *bRGA_PAT_START_POINT;
-    u32 reg = 0;
-    rga_img_info_t *pat;
-
-    pat = (rga_img_info_t *)&msg->pat;
-
-    bRGA_PAT_START_POINT = (u32 *)(base + RGA_PAT_START_POINT_OFFSET);
-    bRGA_PAT_MST = (u32 *)(base + RGA_PAT_MST_OFFSET);
-    bRGA_PAT_CON = (u32 *)(base + RGA_PAT_CON_OFFSET);
-
-    if ( !pat->yrgb_addr ) {
-        return -1;
-    }
-    *bRGA_PAT_MST = (u32)pat->yrgb_addr;
-
-    if ((pat->vir_w > 256)||(pat->x_offset > 256)||(pat->y_offset > 256)) {
-        return -1;
-    }
-    *bRGA_PAT_START_POINT = (pat->vir_w * pat->y_offset) + pat->x_offset;
-
-    reg = (pat->vir_w-1) | ((pat->vir_h-1) << 8) | (pat->x_offset << 16) | (pat->y_offset << 24);
-    *bRGA_PAT_CON = reg;
-
-    return 0;
-}
-
-
-/*************************************************************
-Func:
-    RGA_set_mmu_ctrl_reg_info
-Description:
-    fill mmu relate some reg info
-Author:
-    ZhangShengqin
-Date:
-    20012-2-2 10:59:25
-**************************************************************/
+RGA_set_update_patten_buff_reg_info(u8 *base, const struct rga_req *msg)
+{
+    u32 *bRGA_PAT_MST;
+    u32 *bRGA_PAT_CON;
+    u32 *bRGA_PAT_START_POINT;
+    u32 reg = 0;
+    rga_img_info_t *pat;
+
+    pat = (rga_img_info_t *)&msg->pat;
+
+    bRGA_PAT_START_POINT = (u32 *)(base + RGA_PAT_START_POINT_OFFSET);
+    bRGA_PAT_MST = (u32 *)(base + RGA_PAT_MST_OFFSET);
+    bRGA_PAT_CON = (u32 *)(base + RGA_PAT_CON_OFFSET);
+
+    if ( !pat->yrgb_addr ) {
+        return -1;
+    }
+    *bRGA_PAT_MST = (u32)pat->yrgb_addr;
+
+    if ((pat->vir_w > 256)||(pat->x_offset > 256)||(pat->y_offset > 256)) {
+        return -1;
+    }
+    *bRGA_PAT_START_POINT = (pat->vir_w * pat->y_offset) + pat->x_offset;
+
+    reg = (pat->vir_w-1) | ((pat->vir_h-1) << 8) | (pat->x_offset << 16) | (pat->y_offset << 24);
+    *bRGA_PAT_CON = reg;
+
+    return 0;
+}
+
+
+/*************************************************************
+Func:
+    RGA_set_mmu_ctrl_reg_info
+Description:
+    fill mmu relate some reg info
+Author:
+    ZhangShengqin
+Date:
+    20012-2-2 10:59:25
+**************************************************************/
 
 static s32
-RGA_set_mmu_ctrl_reg_info(u8 *base, const struct rga_req *msg)
-{
-    u32 *RGA_MMU_TLB, *RGA_MMU_CTRL_ADDR;
-    u32  mmu_addr;
-    u8   TLB_size, mmu_enable, src_flag, dst_flag, CMD_flag;
-    u32  reg = 0;
-
-    mmu_addr = (u32)msg->mmu_info.base_addr;
-    TLB_size = (msg->mmu_info.mmu_flag >> 4) & 0x3;
-    mmu_enable = msg->mmu_info.mmu_flag & 0x1;
-
-    src_flag = (msg->mmu_info.mmu_flag >> 1) & 0x1;
-    dst_flag = (msg->mmu_info.mmu_flag >> 2) & 0x1;
-    CMD_flag = (msg->mmu_info.mmu_flag >> 3) & 0x1;
-
-    RGA_MMU_TLB = (u32 *)(base + RGA_MMU_TLB_OFFSET);
-    RGA_MMU_CTRL_ADDR = (u32 *)(base + RGA_FADING_CON_OFFSET);
-
-    reg = ((reg & (~m_RGA_MMU_CTRL_TLB_ADDR)) | s_RGA_MMU_CTRL_TLB_ADDR(mmu_addr));
-    *RGA_MMU_TLB = reg;
-
-    reg = *RGA_MMU_CTRL_ADDR;
-    reg = ((reg & (~m_RGA_MMU_CTRL_PAGE_TABLE_SIZE)) | s_RGA_MMU_CTRL_PAGE_TABLE_SIZE(TLB_size));
-    reg = ((reg & (~m_RGA_MMU_CTRL_MMU_ENABLE)) | s_RGA_MMU_CTRL_MMU_ENABLE(mmu_enable));
-    reg = ((reg & (~m_RGA_MMU_CTRL_SRC_FLUSH)) | s_RGA_MMU_CTRL_SRC_FLUSH(1));
-    reg = ((reg & (~m_RGA_MMU_CTRL_DST_FLUSH)) | s_RGA_MMU_CTRL_DST_FLUSH(1));
-    reg = ((reg & (~m_RGA_MMU_CTRL_CMD_CHAN_FLUSH)) | s_RGA_MMU_CTRL_CMD_CHAN_FLUSH(1));
-    *RGA_MMU_CTRL_ADDR = reg;
-
-    return 0;
-}
-
-
-
-/*************************************************************
-Func:
-    RGA_gen_reg_info
-Description:
-    Generate RGA command reg list from rga_req struct.
-Author:
-    ZhangShengqin
-Date:
-    20012-2-2 10:59:25
-**************************************************************/
-int
-RGA_gen_reg_info(const struct rga_req *msg, unsigned char *base)
-{
-    TILE_INFO tile;
-
-    memset(base, 0x0, 28*4);
-    RGA_set_mode_ctrl(base, msg);
-
-    switch(msg->render_mode)
-    {
-        case bitblt_mode :
-            RGA_set_alpha_rop(base, msg);
-            RGA_set_src(base, msg);
-            RGA_set_dst(base, msg);
-            RGA_set_color(base, msg);
-            RGA_set_fading(base, msg);
-            RGA_set_pat(base, msg);
-            matrix_cal(msg, &tile);
-            dst_ctrl_cal(msg, &tile);
-            src_tile_info_cal(msg, &tile);
-            RGA_set_bitblt_reg_info(base, msg, &tile);
-            break;
-        case color_palette_mode :
-            RGA_set_src(base, msg);
-            RGA_set_dst(base, msg);
-            RGA_set_color(base, msg);
-            RGA_set_color_palette_reg_info(base, msg);
-            break;
-        case color_fill_mode :
-            RGA_set_alpha_rop(base, msg);
-            RGA_set_dst(base, msg);
-            RGA_set_color(base, msg);
-            RGA_set_pat(base, msg);
-            RGA_set_color_fill_reg_info(base, msg);
-            break;
-        case line_point_drawing_mode :
-            RGA_set_alpha_rop(base, msg);
-            RGA_set_dst(base, msg);
-            RGA_set_color(base, msg);
-            RGA_set_line_drawing_reg_info(base, msg);
-            break;
-        case blur_sharp_filter_mode :
-            RGA_set_src(base, msg);
-            RGA_set_dst(base, msg);
-            RGA_set_filter_reg_info(base, msg);
-            break;
-        case pre_scaling_mode :
-            RGA_set_src(base, msg);
-            RGA_set_dst(base, msg);
-            if(RGA_set_pre_scale_reg_info(base, msg) == -EINVAL)
-                return -1;
-            break;
-        case update_palette_table_mode :
-            if (RGA_set_update_palette_table_reg_info(base, msg)) {
-                return -1;
-            }
-			break;
-        case update_patten_buff_mode:
-            if (RGA_set_update_patten_buff_reg_info(base, msg)){
-                return -1;
-            }
-
-            break;
-    }
-
-    RGA_set_mmu_ctrl_reg_info(base, msg);
-
-    return 0;
-}
-
-
-
+RGA_set_mmu_ctrl_reg_info(u8 *base, const struct rga_req *msg)
+{
+    u32 *RGA_MMU_TLB, *RGA_MMU_CTRL_ADDR;
+    u32  mmu_addr;
+    u8   TLB_size, mmu_enable, src_flag, dst_flag, CMD_flag;
+    u32  reg = 0;
+
+    mmu_addr = (u32)msg->mmu_info.base_addr;
+    TLB_size = (msg->mmu_info.mmu_flag >> 4) & 0x3;
+    mmu_enable = msg->mmu_info.mmu_flag & 0x1;
+
+    src_flag = (msg->mmu_info.mmu_flag >> 1) & 0x1;
+    dst_flag = (msg->mmu_info.mmu_flag >> 2) & 0x1;
+    CMD_flag = (msg->mmu_info.mmu_flag >> 3) & 0x1;
+
+    RGA_MMU_TLB = (u32 *)(base + RGA_MMU_TLB_OFFSET);
+    RGA_MMU_CTRL_ADDR = (u32 *)(base + RGA_FADING_CON_OFFSET);
+
+    reg = ((reg & (~m_RGA_MMU_CTRL_TLB_ADDR)) | s_RGA_MMU_CTRL_TLB_ADDR(mmu_addr));
+    *RGA_MMU_TLB = reg;
+
+    reg = *RGA_MMU_CTRL_ADDR;
+    reg = ((reg & (~m_RGA_MMU_CTRL_PAGE_TABLE_SIZE)) | s_RGA_MMU_CTRL_PAGE_TABLE_SIZE(TLB_size));
+    reg = ((reg & (~m_RGA_MMU_CTRL_MMU_ENABLE)) | s_RGA_MMU_CTRL_MMU_ENABLE(mmu_enable));
+    reg = ((reg & (~m_RGA_MMU_CTRL_SRC_FLUSH)) | s_RGA_MMU_CTRL_SRC_FLUSH(1));
+    reg = ((reg & (~m_RGA_MMU_CTRL_DST_FLUSH)) | s_RGA_MMU_CTRL_DST_FLUSH(1));
+    reg = ((reg & (~m_RGA_MMU_CTRL_CMD_CHAN_FLUSH)) | s_RGA_MMU_CTRL_CMD_CHAN_FLUSH(1));
+    *RGA_MMU_CTRL_ADDR = reg;
+
+    return 0;
+}
+
+
+
+/*************************************************************
+Func:
+    RGA_gen_reg_info
+Description:
+    Generate RGA command reg list from rga_req struct.
+Author:
+    ZhangShengqin
+Date:
+    20012-2-2 10:59:25
+**************************************************************/
+int
+RGA_gen_reg_info(const struct rga_req *msg, unsigned char *base)
+{
+    TILE_INFO tile;
+
+    memset(base, 0x0, 28*4);
+    RGA_set_mode_ctrl(base, msg);
+
+    switch(msg->render_mode)
+    {
+        case bitblt_mode :
+            RGA_set_alpha_rop(base, msg);
+            RGA_set_src(base, msg);
+            RGA_set_dst(base, msg);
+            RGA_set_color(base, msg);
+            RGA_set_fading(base, msg);
+            RGA_set_pat(base, msg);
+            matrix_cal(msg, &tile);
+            dst_ctrl_cal(msg, &tile);
+            src_tile_info_cal(msg, &tile);
+            RGA_set_bitblt_reg_info(base, msg, &tile);
+            break;
+        case color_palette_mode :
+            RGA_set_src(base, msg);
+            RGA_set_dst(base, msg);
+            RGA_set_color(base, msg);
+            RGA_set_color_palette_reg_info(base, msg);
+            break;
+        case color_fill_mode :
+            RGA_set_alpha_rop(base, msg);
+            RGA_set_dst(base, msg);
+            RGA_set_color(base, msg);
+            RGA_set_pat(base, msg);
+            RGA_set_color_fill_reg_info(base, msg);
+            break;
+        case line_point_drawing_mode :
+            RGA_set_alpha_rop(base, msg);
+            RGA_set_dst(base, msg);
+            RGA_set_color(base, msg);
+            RGA_set_line_drawing_reg_info(base, msg);
+            break;
+        case blur_sharp_filter_mode :
+            RGA_set_src(base, msg);
+            RGA_set_dst(base, msg);
+            RGA_set_filter_reg_info(base, msg);
+            break;
+        case pre_scaling_mode :
+            RGA_set_src(base, msg);
+            RGA_set_dst(base, msg);
+            if(RGA_set_pre_scale_reg_info(base, msg) == -EINVAL)
+                return -1;
+            break;
+        case update_palette_table_mode :
+            if (RGA_set_update_palette_table_reg_info(base, msg)) {
+                return -1;
+            }
+			break;
+        case update_patten_buff_mode:
+            if (RGA_set_update_patten_buff_reg_info(base, msg)){
+                return -1;
+            }
+
+            break;
+    }
+
+    RGA_set_mmu_ctrl_reg_info(base, msg);
+
+    return 0;
+}
+
+
+
diff --git a/drivers/video/rockchip/rga/rga_reg_info.h b/drivers/video/rockchip/rga/rga_reg_info.h
index 565e8f72d7f0..8edbd5c3d419 100644
--- a/drivers/video/rockchip/rga/rga_reg_info.h
+++ b/drivers/video/rockchip/rga/rga_reg_info.h
@@ -1,467 +1,467 @@
 /* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __REG_INFO_H__
-#define __REG_INFO_H__
-
-
-//#include "chip_register.h"
-
-//#include "rga_struct.h"
-#include "rga.h"
-
-#ifndef MIN
-#define MIN(X, Y)           ((X)<(Y)?(X):(Y))
-#endif
-
-#ifndef MAX
-#define MAX(X, Y)           ((X)>(Y)?(X):(Y))
-#endif
-
-#ifndef ABS
-#define ABS(X)              (((X) < 0) ? (-(X)) : (X))
-#endif
-
-#ifndef CLIP
-#define CLIP(x, a,  b)				((x) < (a)) ? (a) : (((x) > (b)) ? (b) : (x))
-#endif
-
-//RGA register map
-
-//General Registers
-#define rRGA_SYS_CTRL             (*(volatile uint32_t *)(RGA_BASE + RGA_SYS_CTRL))
-#define rRGA_CMD_CTRL             (*(volatile uint32_t *)(RGA_BASE + RGA_CMD_CTRL))
-#define rRGA_CMD_ADDR             (*(volatile uint32_t *)(RGA_BASE + RGA_CMD_ADDR))
-#define rRGA_STATUS               (*(volatile uint32_t *)(RGA_BASE + RGA_STATUS))
-#define rRGA_INT                  (*(volatile uint32_t *)(RGA_BASE + RGA_INT))
-#define rRGA_AXI_ID               (*(volatile uint32_t *)(RGA_BASE + RGA_AXI_ID))
-#define rRGA_MMU_STA_CTRL         (*(volatile uint32_t *)(RGA_BASE + RGA_MMU_STA_CTRL))
-#define rRGA_MMU_STA              (*(volatile uint32_t *)(RGA_BASE + RGA_MMU_STA))
-
-//Command code start
-#define rRGA_MODE_CTRL            (*(volatile uint32_t *)(RGA_BASE + RGA_MODE_CTRL))
-
-//Source Image Registers
-#define rRGA_SRC_Y_MST            (*(volatile uint32_t *)(RGA_BASE + RGA_SRC_Y_MST))
-#define rRGA_SRC_CB_MST           (*(volatile uint32_t *)(RGA_BASE + RGA_SRC_CB_MST))
-#define rRGA_MASK_READ_MST        (*(volatile uint32_t *)(RGA_BASE + RGA_MASK_READ_MST))  //repeat
-#define rRGA_SRC_CR_MST           (*(volatile uint32_t *)(RGA_BASE + RGA_SRC_CR_MST))
-#define rRGA_SRC_VIR_INFO         (*(volatile uint32_t *)(RGA_BASE + RGA_SRC_VIR_INFO))
-#define rRGA_SRC_ACT_INFO         (*(volatile uint32_t *)(RGA_BASE + RGA_SRC_ACT_INFO))
-#define rRGA_SRC_X_PARA           (*(volatile uint32_t *)(RGA_BASE + RGA_SRC_X_PARA))
-#define rRGA_SRC_Y_PARA           (*(volatile uint32_t *)(RGA_BASE + RGA_SRC_Y_PARA))
-#define rRGA_SRC_TILE_XINFO       (*(volatile uint32_t *)(RGA_BASE + RGA_SRC_TILE_XINFO))
-#define rRGA_SRC_TILE_YINFO       (*(volatile uint32_t *)(RGA_BASE + RGA_SRC_TILE_YINFO))
-#define rRGA_SRC_TILE_H_INCR      (*(volatile uint32_t *)(RGA_BASE + RGA_SRC_TILE_H_INCR))
-#define rRGA_SRC_TILE_V_INCR      (*(volatile uint32_t *)(RGA_BASE + RGA_SRC_TILE_V_INCR))
-#define rRGA_SRC_TILE_OFFSETX     (*(volatile uint32_t *)(RGA_BASE + RGA_SRC_TILE_OFFSETX))
-#define rRGA_SRC_TILE_OFFSETY     (*(volatile uint32_t *)(RGA_BASE + RGA_SRC_TILE_OFFSETY))
-#define rRGA_SRC_BG_COLOR         (*(volatile uint32_t *)(RGA_BASE + RGA_SRC_BG_COLOR))
-#define rRGA_SRC_FG_COLOR         (*(volatile uint32_t *)(RGA_BASE + RGA_SRC_FG_COLOR))
-#define rRGA_LINE_DRAWING_COLOR   (*(volatile uint32_t *)(RGA_BASE + RGA_LINE_DRAWING_COLOR))  //repeat
-#define rRGA_SRC_TR_COLOR0        (*(volatile uint32_t *)(RGA_BASE + RGA_SRC_TR_COLOR0))
-#define rRGA_CP_GR_A              (*(volatile uint32_t *)(RGA_BASE + RGA_CP_GR_A))  //repeat
-#define rRGA_SRC_TR_COLOR1        (*(volatile uint32_t *)(RGA_BASE + RGA_SRC_TR_COLOR1))
-#define rRGA_CP_GR_B              (*(volatile uint32_t *)(RGA_BASE + RGA_CP_GR_B))  //repeat
-
-#define rRGA_LINE_DRAW            (*(volatile uint32_t *)(RGA_BASE + RGA_LINE_DRAW))
-#define rRGA_PAT_START_POINT      (*(volatile uint32_t *)(RGA_BASE + RGA_PAT_START_POINT))  //repeat
-
-//Destination Image Registers
-#define rRGA_DST_MST              (*(volatile uint32_t *)(RGA_BASE + RGA_DST_MST))
-#define rRGA_LUT_MST              (*(volatile uint32_t *)(RGA_BASE + RGA_LUT_MST))  //repeat
-#define rRGA_PAT_MST              (*(volatile uint32_t *)(RGA_BASE + RGA_PAT_MST))  //repeat
-#define rRGA_LINE_DRAWING_MST     (*(volatile uint32_t *)(RGA_BASE + RGA_LINE_DRAWING_MST))  //repeat
-
-#define rRGA_DST_VIR_INFO         (*(volatile uint32_t *)(RGA_BASE + RGA_DST_VIR_INFO))
-
-#define rRGA_DST_CTR_INFO         (*(volatile uint32_t *)(RGA_BASE + RGA_DST_CTR_INFO))
-#define rRGA_LINE_DRAW_XY_INFO    (*(volatile uint32_t *)(RGA_BASE + RGA_LINE_DRAW_XY_INFO))  //repeat
-
-//Alpha/ROP Registers
-#define rRGA_ALPHA_CON            (*(volatile uint32_t *)(RGA_BASE + RGA_ALPHA_CON))
-#define rRGA_FADING_CON           (*(volatile uint32_t *)(RGA_BASE + RGA_FADING_CON))
-
-#define rRGA_PAT_CON              (*(volatile uint32_t *)(RGA_BASE + RGA_PAT_CON))
-#define rRGA_DST_VIR_WIDTH_PIX    (*(volatile uint32_t *)(RGA_BASE + RGA_DST_VIR_WIDTH_PIX))  //repeat
-
-#define rRGA_ROP_CON0             (*(volatile uint32_t *)(RGA_BASE + RGA_ROP_CON0))
-#define rRGA_CP_GR_G              (*(volatile uint32_t *)(RGA_BASE + RGA_CP_GR_G))  //repeat
-#define rRGA_PRESCL_CB_MST        (*(volatile uint32_t *)(RGA_BASE + RGA_PRESCL_CB_MST))  //repeat
-
-#define rRGA_ROP_CON1             (*(volatile uint32_t *)(RGA_BASE + RGA_ROP_CON1))
-#define rRGA_CP_GR_R              (*(volatile uint32_t *)(RGA_BASE + RGA_CP_GR_R))  //repeat
-#define rRGA_PRESCL_CR_MST        (*(volatile uint32_t *)(RGA_BASE + RGA_PRESCL_CR_MST))  //repeat
-
-//MMU Register
-#define rRGA_MMU_CTRL             (*(volatile uint32_t *)(RGA_BASE + RGA_MMU_CTRL))
-
-
-
-
-//-----------------------------------------------------------------
-//reg detail definition
-//-----------------------------------------------------------------
-/*RGA_SYS_CTRL*/
-#define m_RGA_SYS_CTRL_CMD_MODE                   ( 1<<2 )
-#define m_RGA_SYS_CTRL_OP_ST_SLV                  ( 1<<1 )
-#define m_RGA_sys_CTRL_SOFT_RESET                 ( 1<<0 )
-
-#define s_RGA_SYS_CTRL_CMD_MODE(x)                ( (x&0x1)<<2 )
-#define s_RGA_SYS_CTRL_OP_ST_SLV(x)               ( (x&0x1)<<1 )
-#define s_RGA_sys_CTRL_SOFT_RESET(x)              ( (x&0x1)<<0 )
-
-
-/*RGA_CMD_CTRL*/
-#define m_RGA_CMD_CTRL_CMD_INCR_NUM               ( 0x3ff<<3 )
-#define m_RGA_CMD_CTRL_CMD_STOP_MODE              (     1<<2 )
-#define m_RGA_CMD_CTRL_CMD_INCR_VALID             (     1<<1 )
-#define m_RGA_CMD_CTRL_CMD_LINE_FET_ST            (     1<<0 )
-
-#define s_RGA_CMD_CTRL_CMD_INCR_NUM(x)            ( (x&0x3ff)<<3 )
-#define s_RGA_CMD_CTRL_CMD_STOP_MODE(x)           (   (x&0x1)<<2 )
-#define s_RGA_CMD_CTRL_CMD_INCR_VALID(x)          (   (x&0x1)<<1 )
-#define s_RGA_CMD_CTRL_CMD_LINE_FET_ST(x)         (   (x*0x1)<<0 )
-
-
-/*RGA_STATUS*/
-#define m_RGA_CMD_STATUS_CMD_TOTAL_NUM            ( 0xfff<<20 )
-#define m_RGA_CMD_STATUS_NOW_CMD_NUM              ( 0xfff<<8  )
-#define m_RGA_CMD_STATUS_ENGINE_STATUS            (     1<<0  )
-
-
-/*RGA_INT*/
-#define m_RGA_INT_ALL_CMD_DONE_INT_EN             ( 1<<10 )
-#define m_RGA_INT_MMU_INT_EN                      ( 1<<9  )
-#define m_RGA_INT_ERROR_INT_EN                    ( 1<<8  )
-#define m_RGA_INT_NOW_CMD_DONE_INT_CLEAR          ( 1<<7  )
-#define m_RGA_INT_ALL_CMD_DONE_INT_CLEAR          ( 1<<6  )
-#define m_RGA_INT_MMU_INT_CLEAR                   ( 1<<5  )
-#define m_RGA_INT_ERROR_INT_CLEAR                 ( 1<<4  )
-#define m_RGA_INT_NOW_CMD_DONE_INT_FLAG           ( 1<<3  )
-#define m_RGA_INT_ALL_CMD_DONE_INT_FLAG           ( 1<<2  )
-#define m_RGA_INT_MMU_INT_FLAG                    ( 1<<1  )
-#define m_RGA_INT_ERROR_INT_FLAG                  ( 1<<0  )
-
-#define s_RGA_INT_ALL_CMD_DONE_INT_EN(x)          ( (x&0x1)<<10 )
-#define s_RGA_INT_MMU_INT_EN(x)                   ( (x&0x1)<<9  )
-#define s_RGA_INT_ERROR_INT_EN(x)                 ( (x&0x1)<<8  )
-#define s_RGA_INT_NOW_CMD_DONE_INT_CLEAR(x)       ( (x&0x1)<<7  )
-#define s_RGA_INT_ALL_CMD_DONE_INT_CLEAR(x)       ( (x&0x1)<<6  )
-#define s_RGA_INT_MMU_INT_CLEAR(x)                ( (x&0x1)<<5  )
-#define s_RGA_INT_ERROR_INT_CLEAR(x)              ( (x&0x1)<<4  )
-
-
-/*RGA_AXI_ID*/
-#define m_RGA_AXI_ID_MMU_READ                     ( 3<<30 )
-#define m_RGA_AXI_ID_MMU_WRITE                    ( 3<<28 )
-#define m_RGA_AXI_ID_MASK_READ                    ( 0xf<<24 )
-#define m_RGA_AXI_ID_CMD_FET                      ( 0xf<<20 )
-#define m_RGA_AXI_ID_DST_WRITE                    ( 0xf<<16 )
-#define m_RGA_AXI_ID_DST_READ                     ( 0xf<<12 )
-#define m_RGA_AXI_ID_SRC_CR_READ                  ( 0xf<<8  )
-#define m_RGA_AXI_ID_SRC_CB_READ                  ( 0xf<<4  )
-#define m_RGA_AXI_ID_SRC_Y_READ                   ( 0xf<<0  )
-
-#define s_RGA_AXI_ID_MMU_READ(x)                  ( (x&0x3)<<30 )
-#define s_RGA_AXI_ID_MMU_WRITE(x)                 ( (x&0x3)<<28 )
-#define s_RGA_AXI_ID_MASK_READ(x)                 ( (x&0xf)<<24 )
-#define s_RGA_AXI_ID_CMD_FET(x)                   ( (x&0xf)<<20 )
-#define s_RGA_AXI_ID_DST_WRITE(x)                 ( (x&0xf)<<16 )
-#define s_RGA_AXI_ID_DST_READ(x)                  ( (x&0xf)<<12 )
-#define s_RGA_AXI_ID_SRC_CR_READ(x)               ( (x&0xf)<<8  )
-#define s_RGA_AXI_ID_SRC_CB_READ(x)               ( (x&0xf)<<4  )
-#define s_RGA_AXI_ID_SRC_Y_READ(x)                ( (x&0xf)<<0  )
-
-
-/*RGA_MMU_STA_CTRL*/
-#define m_RGA_MMU_STA_CTRL_TLB_STA_CLEAR          ( 1<<3 )
-#define m_RGA_MMU_STA_CTRL_TLB_STA_RESUME         ( 1<<2 )
-#define m_RGA_MMU_STA_CTRL_TLB_STA_PAUSE          ( 1<<1 )
-#define m_RGA_MMU_STA_CTRL_TLB_STA_EN             ( 1<<0 )
-
-#define s_RGA_MMU_STA_CTRL_TLB_STA_CLEAR(x)       ( (x&0x1)<<3 )
-#define s_RGA_MMU_STA_CTRL_TLB_STA_RESUME(x)      ( (x&0x1)<<2 )
-#define s_RGA_MMU_STA_CTRL_TLB_STA_PAUSE(x)       ( (x&0x1)<<1 )
-#define s_RGA_MMU_STA_CTRL_TLB_STA_EN(x)          ( (x&0x1)<<0 )
-
-
-
-/* RGA_MODE_CTRL */
-#define m_RGA_MODE_CTRL_2D_RENDER_MODE            (  7<<0  )
-#define m_RGA_MODE_CTRL_SRC_RGB_PACK              (  1<<3  )
-#define m_RGA_MODE_CTRL_SRC_FORMAT                ( 15<<4  )
-#define m_RGA_MODE_CTRL_SRC_RB_SWAP               (  1<<8  )
-#define m_RGA_MODE_CTRL_SRC_ALPHA_SWAP            (  1<<9  )
-#define m_RGA_MODE_CTRL_SRC_UV_SWAP_MODE          (  1<<10 )
-#define m_RGA_MODE_CTRL_YUV2RGB_CON_MODE          (  3<<11 )
-#define m_RGA_MODE_CTRL_SRC_TRANS_MODE           (0x1f<<13 )
-#define m_RGA_MODE_CTRL_SRC_TR_MODE               (  1<<13 )
-#define m_RGA_MODE_CTRL_SRC_TR_R_EN               (  1<<14 )
-#define m_RGA_MODE_CTRL_SRC_TR_G_EN               (  1<<15 )
-#define m_RGA_MODE_CTRL_SRC_TR_B_EN               (  1<<16 )
-#define m_RGA_MODE_CTRL_SRC_TR_A_EN               (  1<<17 )
-#define m_RGA_MODE_CTRL_ROTATE_MODE               (  3<<18 )
-#define m_RGA_MODE_CTRL_SCALE_MODE                (  3<<20 )
-#define m_RGA_MODE_CTRL_PAT_SEL                   (  1<<22 )
-#define m_RGA_MODE_CTRL_DST_FORMAT                (  3<<23 )
-#define m_RGA_MODE_CTRL_DST_RGB_PACK              (  1<<25 )
-#define m_RGA_MODE_CTRL_DST_RB_SWAP               (  1<<26 )
-#define m_RGA_MODE_CTRL_DST_ALPHA_SWAP            (  1<<27 )
-#define m_RGA_MODE_CTRL_LUT_ENDIAN_MODE           (  1<<28 )
-#define m_RGA_MODE_CTRL_CMD_INT_ENABLE            (  1<<29 )
-#define m_RGA_MODE_CTRL_ZERO_MODE_ENABLE          (  1<<30 )
-#define m_RGA_MODE_CTRL_DST_ALPHA_ENABLE          (  1<<30 )
-
-
-
-#define s_RGA_MODE_CTRL_2D_RENDER_MODE(x)         (  (x&0x7)<<0  )
-#define s_RGA_MODE_CTRL_SRC_RGB_PACK(x)           (  (x&0x1)<<3  )
-#define s_RGA_MODE_CTRL_SRC_FORMAT(x)             (  (x&0xf)<<4  )
-#define s_RGA_MODE_CTRL_SRC_RB_SWAP(x)            (  (x&0x1)<<8  )
-#define s_RGA_MODE_CTRL_SRC_ALPHA_SWAP(x)         (  (x&0x1)<<9  )
-#define s_RGA_MODE_CTRL_SRC_UV_SWAP_MODE(x)       (  (x&0x1)<<10 )
-#define s_RGA_MODE_CTRL_YUV2RGB_CON_MODE(x)       (  (x&0x3)<<11 )
-#define s_RGA_MODE_CTRL_SRC_TRANS_MODE(x)         ( (x&0x1f)<<13 )
-#define s_RGA_MODE_CTRL_SRC_TR_MODE(x)            (  (x&0x1)<<13 )
-#define s_RGA_MODE_CTRL_SRC_TR_R_EN(x)            (  (x&0x1)<<14 )
-#define s_RGA_MODE_CTRL_SRC_TR_G_EN(x)            (  (x&0x1)<<15 )
-#define s_RGA_MODE_CTRL_SRC_TR_B_EN(x)            (  (x&0x1)<<16 )
-#define s_RGA_MODE_CTRL_SRC_TR_A_EN(x)            (  (x&0x1)<<17 )
-#define s_RGA_MODE_CTRL_ROTATE_MODE(x)            (  (x&0x3)<<18 )
-#define s_RGA_MODE_CTRL_SCALE_MODE(x)             (  (x&0x3)<<20 )
-#define s_RGA_MODE_CTRL_PAT_SEL(x)                (  (x&0x1)<<22 )
-#define s_RGA_MODE_CTRL_DST_FORMAT(x)             (  (x&0x3)<<23 )
-#define s_RGA_MODE_CTRL_DST_RGB_PACK(x)           (  (x&0x1)<<25 )
-#define s_RGA_MODE_CTRL_DST_RB_SWAP(x)            (  (x&0x1)<<26 )
-#define s_RGA_MODE_CTRL_DST_ALPHA_SWAP(x)         (  (x&0x1)<<27 )
-#define s_RGA_MODE_CTRL_LUT_ENDIAN_MODE(x)        (  (x&0x1)<<28 )
-#define s_RGA_MODE_CTRL_CMD_INT_ENABLE(x)         (  (x&0x1)<<29 )
-#define s_RGA_MODE_CTRL_ZERO_MODE_ENABLE(x)       (  (x&0x1)<<30 )
-#define s_RGA_MODE_CTRL_DST_ALPHA_ENABLE(x)       (  (x&0x1)<<31 )
-
-
-
-/* RGA_LINE_DRAW */
-#define m_RGA_LINE_DRAW_MAJOR_WIDTH            ( 0x7ff<<0 )
-#define m_RGA_LINE_DRAW_LINE_DIRECTION         (   0x1<<11)
-#define m_RGA_LINE_DRAW_LINE_WIDTH             (   0xf<<12)
-#define m_RGA_LINE_DRAW_INCR_VALUE             ( 0xfff<<16)
-#define m_RGA_LINE_DRAW_DIR_MAJOR              (   0x1<<28)
-#define m_RGA_LINE_DRAW_DIR_SEMI_MAJOR         (   0x1<<29)
-#define m_RGA_LINE_DRAW_LAST_POINT             (   0x1<<30)
-#define m_RGA_LINE_DRAW_ANTI_ALISING           (   0x1<<31)
-
-#define s_RGA_LINE_DRAW_MAJOR_WIDTH(x)            (((x)&0x7ff)<<0 )
-#define s_RGA_LINE_DRAW_LINE_DIRECTION(x)         (  ((x)&0x1)<<11)
-#define s_RGA_LINE_DRAW_LINE_WIDTH(x)             (  ((x)&0xf)<<12)
-#define s_RGA_LINE_DRAW_INCR_VALUE(x)             (((x)&0xfff)<<16)
-#define s_RGA_LINE_DRAW_DIR_MAJOR(x)              (  ((x)&0x1)<<28)
-#define s_RGA_LINE_DRAW_DIR_SEMI_MAJOR(x)         (  ((x)&0x1)<<29)
-#define s_RGA_LINE_DRAW_LAST_POINT(x)             (  ((x)&0x1)<<30)
-#define s_RGA_LINE_DRAW_ANTI_ALISING(x)           (  ((x)&0x1)<<31)
-
-
-/* RGA_ALPHA_CON */
-#define m_RGA_ALPHA_CON_ENABLE                  ( 0x1<<0 )
-#define m_RGA_ALPHA_CON_A_OR_R_SEL              ( 0x1<<1 )
-#define m_RGA_ALPHA_CON_ALPHA_MODE              ( 0x3<<2 )
-#define m_RGA_ALPHA_CON_PD_MODE                 ( 0xf<<4 )
-#define m_RGA_ALPHA_CON_SET_CONSTANT_VALUE      (0xff<<8 )
-#define m_RGA_ALPHA_CON_PD_M_SEL                ( 0x1<<16)
-#define m_RGA_ALPHA_CON_FADING_ENABLE           ( 0x1<<17)
-#define m_RGA_ALPHA_CON_ROP_MODE_SEL            ( 0x3<<18)
-#define m_RGA_ALPHA_CON_CAL_MODE_SEL            ( 0x1<<28)
-#define m_RGA_ALPHA_CON_DITHER_ENABLE           ( 0x1<<29)
-#define m_RGA_ALPHA_CON_GRADIENT_CAL_MODE       ( 0x1<<30)
-#define m_RGA_ALPHA_CON_AA_SEL                  ( 0x1<<31)
-
-#define s_RGA_ALPHA_CON_ENABLE(x)                  ( (x&0x1)<<0 )
-#define s_RGA_ALPHA_CON_A_OR_R_SEL(x)              ( (x&0x1)<<1 )
-#define s_RGA_ALPHA_CON_ALPHA_MODE(x)              ( (x&0x3)<<2 )
-#define s_RGA_ALPHA_CON_PD_MODE(x)                 ( (x&0xf)<<4 )
-#define s_RGA_ALPHA_CON_SET_CONSTANT_VALUE(x)      ((x&0xff)<<8 )
-#define s_RGA_ALPHA_CON_PD_M_SEL(x)                ( (x&0x1)<<16)
-#define s_RGA_ALPHA_CON_FADING_ENABLE(x)           ( (x&0x1)<<17)
-#define s_RGA_ALPHA_CON_ROP_MODE_SEL(x)            ( (x&0x3)<<18)
-#define s_RGA_ALPHA_CON_CAL_MODE_SEL(x)            ( (x&0x1)<<28)
-#define s_RGA_ALPHA_CON_DITHER_ENABLE(x)           ( (x&0x1)<<29)
-#define s_RGA_ALPHA_CON_GRADIENT_CAL_MODE(x)       ( (x&0x1)<<30)
-#define s_RGA_ALPHA_CON_AA_SEL(x)                  ( (x&0x1)<<31)
-
-
-/* blur sharp mode */
-#define m_RGA_BLUR_SHARP_FILTER_MODE                    (  0x1<<25 )
-#define m_RGA_BLUR_SHARP_FILTER_TYPE                    (  0x3<<26 )
-
-#define s_RGA_BLUR_SHARP_FILTER_MODE(x)                 ( (x&0x1)<<25 )
-#define s_RGA_BLUR_SHARP_FILTER_TYPE(x)                 ( (x&0x3)<<26 )
-
-
-/* pre scale mode */
-#define m_RGA_PRE_SCALE_HOR_RATIO                       ( 0x3 <<20 )
-#define m_RGA_PRE_SCALE_VER_RATIO                       ( 0x3 <<22 )
-#define m_RGA_PRE_SCALE_OUTPUT_FORMAT                   ( 0x1 <<24 )
-
-#define s_RGA_PRE_SCALE_HOR_RATIO(x)                    ( (x&0x3) <<20 )
-#define s_RGA_PRE_SCALE_VER_RATIO(x)                    ( (x&0x3) <<22 )
-#define s_RGA_PRE_SCALE_OUTPUT_FORMAT(x)                ( (x&0x1) <<24 )
-
-
-
-/* RGA_MMU_CTRL*/
-#define m_RGA_MMU_CTRL_TLB_ADDR                         ( 0xffffffff<<0)
-#define m_RGA_MMU_CTRL_PAGE_TABLE_SIZE                  ( 0x3<<4 )
-#define m_RGA_MMU_CTRL_MMU_ENABLE                       ( 0x1<<0 )
-#define m_RGA_MMU_CTRL_SRC_FLUSH                        ( 0x1<<1 )
-#define m_RGA_MMU_CTRL_DST_FLUSH                        ( 0x1<<2 )
-#define m_RGA_MMU_CTRL_CMD_CHAN_FLUSH                   ( 0x1<<3 )
-
-#define s_RGA_MMU_CTRL_TLB_ADDR(x)                      ((x&0xffffffff))
-#define s_RGA_MMU_CTRL_PAGE_TABLE_SIZE(x)               ((x&0x3)<<4)
-#define s_RGA_MMU_CTRL_MMU_ENABLE(x)                    ((x&0x1)<<0)
-#define s_RGA_MMU_CTRL_SRC_FLUSH(x)                     ((x&0x1)<<1)
-#define s_RGA_MMU_CTRL_DST_FLUSH(x)                     ((x&0x1)<<2)
-#define s_RGA_MMU_CTRL_CMD_CHAN_FLUSH(x)                ((x&0x1)<<3)
-
-#endif
-
-/*
-#define RGA_MODE_CTRL_OFFSET            0x0
-#define RGA_SRC_Y_MST_OFFSET            0x4
-#define RGA_SRC_CB_MST_OFFSET           0x8
-#define RGA_SRC_CR_MST_OFFSET           0xc
-#define RGA_SRC_VIR_INFO_OFFSET         0x10
-#define RGA_SRC_ACT_INFO_OFFSET         0x14
-#define RGA_SRC_X_PARA_OFFSET           0x18
-#define RGA_SRC_Y_PARA_OFFSET           0x1c
-#define RGA_SRC_TILE_XINFO_OFFSET       0x20
-#define RGA_SRC_TILE_YINFO_OFFSET       0x24
-#define RGA_SRC_TILE_H_INCR_OFFSET      0x28
-#define RGA_SRC_TILE_V_INCR_OFFSET      0x2c
-#define RGA_SRC_TILE_OFFSETX_OFFSET     0x30
-#define RGA_SRC_TILE_OFFSETY_OFFSET     0x34
-#define RGA_SRC_BG_COLOR_OFFSET         0x38
-
-#define RGA_SRC_FG_COLOR_OFFSET         0x3c
-#define RGA_LINE_DRAWING_COLOR_OFFSET   0x3c
-
-#define RGA_SRC_TR_COLOR0_OFFSET        0x40
-#define RGA_CP_GR_A_OFFSET              0x40  //repeat
-
-#define RGA_SRC_TR_COLOR1_OFFSET        0x44
-#define RGA_CP_GR_B_OFFSET              0x44  //repeat
-
-#define RGA_LINE_DRAW_OFFSET            0x48
-#define RGA_PAT_START_POINT_OFFSET      0x48  //repeat
-
-#define RGA_DST_MST_OFFSET              0x4c
-#define RGA_LUT_MST_OFFSET              0x4c  //repeat
-#define RGA_PAT_MST_OFFSET              0x4c  //repeat
-#define RGA_LINE_DRAWING_MST_OFFSET     0x4c  //repeat
-
-#define RGA_DST_VIR_INFO_OFFSET         0x50
-
-#define RGA_DST_CTR_INFO_OFFSET         0x54
-#define RGA_LINE_DRAW_XY_INFO_OFFSET    0x54  //repeat
-
-#define RGA_ALPHA_CON_OFFSET            0x58
-#define RGA_FADING_CON_OFFSET           0x5c
-
-#define RGA_PAT_CON_OFFSET              0x60
-#define RGA_LINE_DRAWING_WIDTH_OFFSET   0x60  //repeat
-
-#define RGA_ROP_CON0_OFFSET             0x64
-#define RGA_CP_GR_G_OFFSET              0x64  //repeat
-#define RGA_PRESCL_CB_MST_OFFSET        0x64  //repeat
-
-#define RGA_ROP_CON1_OFFSET             0x68
-#define RGA_CP_GR_R_OFFSET              0x68  //repeat
-#define RGA_PRESCL_CR_MST_OFFSET        0x68  //repeat
-
-#define RGA_MMU_CTRL_OFFSET             0x6c
-
-
-#define RGA_SYS_CTRL_OFFSET             0x000
-#define RGA_CMD_CTRL_OFFSET             0x004
-#define RGA_CMD_ADDR_OFFSET             0x008
-#define RGA_STATUS_OFFSET               0x00c
-#define RGA_INT_OFFSET                  0x010
-#define RGA_AXI_ID_OFFSET               0x014
-#define RGA_MMU_STA_CTRL_OFFSET         0x018
-#define RGA_MMU_STA_OFFSET              0x01c
-*/
-//hxx
-
-#define RGA_SYS_CTRL_OFFSET             (RGA_SYS_CTRL-0x100)
-#define RGA_CMD_CTRL_OFFSET             (RGA_CMD_CTRL-0x100)
-#define RGA_CMD_ADDR_OFFSET             (RGA_CMD_ADDR-0x100)
-#define RGA_STATUS_OFFSET               (RGA_STATUS-0x100)
-#define RGA_INT_OFFSET                  (RGA_INT-0x100)
-#define RGA_AXI_ID_OFFSET               (RGA_AXI_ID-0x100)
-#define RGA_MMU_STA_CTRL_OFFSET         (RGA_MMU_STA_CTRL-0x100)
-#define RGA_MMU_STA_OFFSET              (RGA_MMU_STA-0x100)
-
-#define RGA_MODE_CTRL_OFFSET            (RGA_MODE_CTRL-0x100)
-#define RGA_SRC_Y_MST_OFFSET            (RGA_SRC_Y_MST-0x100)
-#define RGA_SRC_CB_MST_OFFSET           (RGA_SRC_CB_MST-0x100)
-#define RGA_SRC_CR_MST_OFFSET           (RGA_SRC_CR_MST-0x100)
-#define RGA_SRC_VIR_INFO_OFFSET         (RGA_SRC_VIR_INFO-0x100)
-#define RGA_SRC_ACT_INFO_OFFSET         (RGA_SRC_ACT_INFO-0x100)
-#define RGA_SRC_X_PARA_OFFSET           (RGA_SRC_X_PARA-0x100)
-#define RGA_SRC_Y_PARA_OFFSET           (RGA_SRC_Y_PARA-0x100)
-#define RGA_SRC_TILE_XINFO_OFFSET       (RGA_SRC_TILE_XINFO-0x100)
-#define RGA_SRC_TILE_YINFO_OFFSET       (RGA_SRC_TILE_YINFO-0x100)
-#define RGA_SRC_TILE_H_INCR_OFFSET      (RGA_SRC_TILE_H_INCR-0x100)
-#define RGA_SRC_TILE_V_INCR_OFFSET      (RGA_SRC_TILE_V_INCR-0x100)
-#define RGA_SRC_TILE_OFFSETX_OFFSET     (RGA_SRC_TILE_OFFSETX-0x100)
-#define RGA_SRC_TILE_OFFSETY_OFFSET     (RGA_SRC_TILE_OFFSETY-0x100)
-#define RGA_SRC_BG_COLOR_OFFSET         (RGA_SRC_BG_COLOR-0x100)
-
-#define RGA_SRC_FG_COLOR_OFFSET         (RGA_SRC_FG_COLOR-0x100)
-#define RGA_LINE_DRAWING_COLOR_OFFSET   (RGA_LINE_DRAWING_COLOR-0x100)
-
-#define RGA_SRC_TR_COLOR0_OFFSET        (RGA_SRC_TR_COLOR0-0x100)
-#define RGA_CP_GR_A_OFFSET              (RGA_CP_GR_A-0x100)  //repeat
-
-#define RGA_SRC_TR_COLOR1_OFFSET        (RGA_SRC_TR_COLOR1-0x100)
-#define RGA_CP_GR_B_OFFSET              (RGA_CP_GR_B-0x100)  //repeat
-
-#define RGA_LINE_DRAW_OFFSET            (RGA_LINE_DRAW-0x100)
-#define RGA_PAT_START_POINT_OFFSET      (RGA_PAT_START_POINT-0x100)  //repeat
-
-#define RGA_DST_MST_OFFSET              (RGA_DST_MST-0x100)
-#define RGA_LUT_MST_OFFSET              (RGA_LUT_MST-0x100)  //repeat
-#define RGA_PAT_MST_OFFSET              (RGA_PAT_MST-0x100)  //repeat
-#define RGA_LINE_DRAWING_MST_OFFSET     (RGA_LINE_DRAWING_MST-0x100)  //repeat
-
-#define RGA_DST_VIR_INFO_OFFSET         (RGA_DST_VIR_INFO-0x100)
-
-#define RGA_DST_CTR_INFO_OFFSET         (RGA_DST_CTR_INFO-0x100)
-#define RGA_LINE_DRAW_XY_INFO_OFFSET    (RGA_LINE_DRAW_XY_INFO-0x100)  //repeat
-
-#define RGA_ALPHA_CON_OFFSET            (RGA_ALPHA_CON-0x100)
-
-#define RGA_PAT_CON_OFFSET              (RGA_PAT_CON-0x100)
-#define RGA_LINE_DRAWING_WIDTH_OFFSET   (RGA_DST_VIR_WIDTH_PIX-0x100)  //repeat
-
-#define RGA_ROP_CON0_OFFSET             (RGA_ROP_CON0-0x100)
-#define RGA_CP_GR_G_OFFSET              (RGA_CP_GR_G-0x100)  //repeat
-#define RGA_PRESCL_CB_MST_OFFSET        (RGA_PRESCL_CB_MST-0x100)  //repeat
-
-#define RGA_ROP_CON1_OFFSET             (RGA_ROP_CON1-0x100)
-#define RGA_CP_GR_R_OFFSET              (RGA_CP_GR_R-0x100)  //repeat
-#define RGA_PRESCL_CR_MST_OFFSET        (RGA_PRESCL_CR_MST-0x100)  //repeat
-
-#define RGA_FADING_CON_OFFSET           (RGA_FADING_CON-0x100)
-#define RGA_MMU_TLB_OFFSET              (RGA_MMU_TBL-0x100)
-
-#define RGA_YUV_OUT_CFG_OFFSET         (RGA_YUV_OUT_CFG-0x100)
-#define RGA_DST_UV_MST_OFFSET          (RGA_DST_UV_MST-0x100)
-
-
-
-void matrix_cal(const struct rga_req *msg, TILE_INFO *tile);
-
-
-int RGA_gen_reg_info(const struct rga_req *msg, unsigned char *base);
-uint8_t   RGA_pixel_width_init(uint32_t format);
-
+#ifndef __REG_INFO_H__
+#define __REG_INFO_H__
+
+
+//#include "chip_register.h"
+
+//#include "rga_struct.h"
+#include "rga.h"
+
+#ifndef MIN
+#define MIN(X, Y)           ((X)<(Y)?(X):(Y))
+#endif
+
+#ifndef MAX
+#define MAX(X, Y)           ((X)>(Y)?(X):(Y))
+#endif
+
+#ifndef ABS
+#define ABS(X)              (((X) < 0) ? (-(X)) : (X))
+#endif
+
+#ifndef CLIP
+#define CLIP(x, a,  b)				((x) < (a)) ? (a) : (((x) > (b)) ? (b) : (x))
+#endif
+
+//RGA register map
+
+//General Registers
+#define rRGA_SYS_CTRL             (*(volatile uint32_t *)(RGA_BASE + RGA_SYS_CTRL))
+#define rRGA_CMD_CTRL             (*(volatile uint32_t *)(RGA_BASE + RGA_CMD_CTRL))
+#define rRGA_CMD_ADDR             (*(volatile uint32_t *)(RGA_BASE + RGA_CMD_ADDR))
+#define rRGA_STATUS               (*(volatile uint32_t *)(RGA_BASE + RGA_STATUS))
+#define rRGA_INT                  (*(volatile uint32_t *)(RGA_BASE + RGA_INT))
+#define rRGA_AXI_ID               (*(volatile uint32_t *)(RGA_BASE + RGA_AXI_ID))
+#define rRGA_MMU_STA_CTRL         (*(volatile uint32_t *)(RGA_BASE + RGA_MMU_STA_CTRL))
+#define rRGA_MMU_STA              (*(volatile uint32_t *)(RGA_BASE + RGA_MMU_STA))
+
+//Command code start
+#define rRGA_MODE_CTRL            (*(volatile uint32_t *)(RGA_BASE + RGA_MODE_CTRL))
+
+//Source Image Registers
+#define rRGA_SRC_Y_MST            (*(volatile uint32_t *)(RGA_BASE + RGA_SRC_Y_MST))
+#define rRGA_SRC_CB_MST           (*(volatile uint32_t *)(RGA_BASE + RGA_SRC_CB_MST))
+#define rRGA_MASK_READ_MST        (*(volatile uint32_t *)(RGA_BASE + RGA_MASK_READ_MST))  //repeat
+#define rRGA_SRC_CR_MST           (*(volatile uint32_t *)(RGA_BASE + RGA_SRC_CR_MST))
+#define rRGA_SRC_VIR_INFO         (*(volatile uint32_t *)(RGA_BASE + RGA_SRC_VIR_INFO))
+#define rRGA_SRC_ACT_INFO         (*(volatile uint32_t *)(RGA_BASE + RGA_SRC_ACT_INFO))
+#define rRGA_SRC_X_PARA           (*(volatile uint32_t *)(RGA_BASE + RGA_SRC_X_PARA))
+#define rRGA_SRC_Y_PARA           (*(volatile uint32_t *)(RGA_BASE + RGA_SRC_Y_PARA))
+#define rRGA_SRC_TILE_XINFO       (*(volatile uint32_t *)(RGA_BASE + RGA_SRC_TILE_XINFO))
+#define rRGA_SRC_TILE_YINFO       (*(volatile uint32_t *)(RGA_BASE + RGA_SRC_TILE_YINFO))
+#define rRGA_SRC_TILE_H_INCR      (*(volatile uint32_t *)(RGA_BASE + RGA_SRC_TILE_H_INCR))
+#define rRGA_SRC_TILE_V_INCR      (*(volatile uint32_t *)(RGA_BASE + RGA_SRC_TILE_V_INCR))
+#define rRGA_SRC_TILE_OFFSETX     (*(volatile uint32_t *)(RGA_BASE + RGA_SRC_TILE_OFFSETX))
+#define rRGA_SRC_TILE_OFFSETY     (*(volatile uint32_t *)(RGA_BASE + RGA_SRC_TILE_OFFSETY))
+#define rRGA_SRC_BG_COLOR         (*(volatile uint32_t *)(RGA_BASE + RGA_SRC_BG_COLOR))
+#define rRGA_SRC_FG_COLOR         (*(volatile uint32_t *)(RGA_BASE + RGA_SRC_FG_COLOR))
+#define rRGA_LINE_DRAWING_COLOR   (*(volatile uint32_t *)(RGA_BASE + RGA_LINE_DRAWING_COLOR))  //repeat
+#define rRGA_SRC_TR_COLOR0        (*(volatile uint32_t *)(RGA_BASE + RGA_SRC_TR_COLOR0))
+#define rRGA_CP_GR_A              (*(volatile uint32_t *)(RGA_BASE + RGA_CP_GR_A))  //repeat
+#define rRGA_SRC_TR_COLOR1        (*(volatile uint32_t *)(RGA_BASE + RGA_SRC_TR_COLOR1))
+#define rRGA_CP_GR_B              (*(volatile uint32_t *)(RGA_BASE + RGA_CP_GR_B))  //repeat
+
+#define rRGA_LINE_DRAW            (*(volatile uint32_t *)(RGA_BASE + RGA_LINE_DRAW))
+#define rRGA_PAT_START_POINT      (*(volatile uint32_t *)(RGA_BASE + RGA_PAT_START_POINT))  //repeat
+
+//Destination Image Registers
+#define rRGA_DST_MST              (*(volatile uint32_t *)(RGA_BASE + RGA_DST_MST))
+#define rRGA_LUT_MST              (*(volatile uint32_t *)(RGA_BASE + RGA_LUT_MST))  //repeat
+#define rRGA_PAT_MST              (*(volatile uint32_t *)(RGA_BASE + RGA_PAT_MST))  //repeat
+#define rRGA_LINE_DRAWING_MST     (*(volatile uint32_t *)(RGA_BASE + RGA_LINE_DRAWING_MST))  //repeat
+
+#define rRGA_DST_VIR_INFO         (*(volatile uint32_t *)(RGA_BASE + RGA_DST_VIR_INFO))
+
+#define rRGA_DST_CTR_INFO         (*(volatile uint32_t *)(RGA_BASE + RGA_DST_CTR_INFO))
+#define rRGA_LINE_DRAW_XY_INFO    (*(volatile uint32_t *)(RGA_BASE + RGA_LINE_DRAW_XY_INFO))  //repeat
+
+//Alpha/ROP Registers
+#define rRGA_ALPHA_CON            (*(volatile uint32_t *)(RGA_BASE + RGA_ALPHA_CON))
+#define rRGA_FADING_CON           (*(volatile uint32_t *)(RGA_BASE + RGA_FADING_CON))
+
+#define rRGA_PAT_CON              (*(volatile uint32_t *)(RGA_BASE + RGA_PAT_CON))
+#define rRGA_DST_VIR_WIDTH_PIX    (*(volatile uint32_t *)(RGA_BASE + RGA_DST_VIR_WIDTH_PIX))  //repeat
+
+#define rRGA_ROP_CON0             (*(volatile uint32_t *)(RGA_BASE + RGA_ROP_CON0))
+#define rRGA_CP_GR_G              (*(volatile uint32_t *)(RGA_BASE + RGA_CP_GR_G))  //repeat
+#define rRGA_PRESCL_CB_MST        (*(volatile uint32_t *)(RGA_BASE + RGA_PRESCL_CB_MST))  //repeat
+
+#define rRGA_ROP_CON1             (*(volatile uint32_t *)(RGA_BASE + RGA_ROP_CON1))
+#define rRGA_CP_GR_R              (*(volatile uint32_t *)(RGA_BASE + RGA_CP_GR_R))  //repeat
+#define rRGA_PRESCL_CR_MST        (*(volatile uint32_t *)(RGA_BASE + RGA_PRESCL_CR_MST))  //repeat
+
+//MMU Register
+#define rRGA_MMU_CTRL             (*(volatile uint32_t *)(RGA_BASE + RGA_MMU_CTRL))
+
+
+
+
+//-----------------------------------------------------------------
+//reg detail definition
+//-----------------------------------------------------------------
+/*RGA_SYS_CTRL*/
+#define m_RGA_SYS_CTRL_CMD_MODE                   ( 1<<2 )
+#define m_RGA_SYS_CTRL_OP_ST_SLV                  ( 1<<1 )
+#define m_RGA_sys_CTRL_SOFT_RESET                 ( 1<<0 )
+
+#define s_RGA_SYS_CTRL_CMD_MODE(x)                ( (x&0x1)<<2 )
+#define s_RGA_SYS_CTRL_OP_ST_SLV(x)               ( (x&0x1)<<1 )
+#define s_RGA_sys_CTRL_SOFT_RESET(x)              ( (x&0x1)<<0 )
+
+
+/*RGA_CMD_CTRL*/
+#define m_RGA_CMD_CTRL_CMD_INCR_NUM               ( 0x3ff<<3 )
+#define m_RGA_CMD_CTRL_CMD_STOP_MODE              (     1<<2 )
+#define m_RGA_CMD_CTRL_CMD_INCR_VALID             (     1<<1 )
+#define m_RGA_CMD_CTRL_CMD_LINE_FET_ST            (     1<<0 )
+
+#define s_RGA_CMD_CTRL_CMD_INCR_NUM(x)            ( (x&0x3ff)<<3 )
+#define s_RGA_CMD_CTRL_CMD_STOP_MODE(x)           (   (x&0x1)<<2 )
+#define s_RGA_CMD_CTRL_CMD_INCR_VALID(x)          (   (x&0x1)<<1 )
+#define s_RGA_CMD_CTRL_CMD_LINE_FET_ST(x)         (   (x*0x1)<<0 )
+
+
+/*RGA_STATUS*/
+#define m_RGA_CMD_STATUS_CMD_TOTAL_NUM            ( 0xfff<<20 )
+#define m_RGA_CMD_STATUS_NOW_CMD_NUM              ( 0xfff<<8  )
+#define m_RGA_CMD_STATUS_ENGINE_STATUS            (     1<<0  )
+
+
+/*RGA_INT*/
+#define m_RGA_INT_ALL_CMD_DONE_INT_EN             ( 1<<10 )
+#define m_RGA_INT_MMU_INT_EN                      ( 1<<9  )
+#define m_RGA_INT_ERROR_INT_EN                    ( 1<<8  )
+#define m_RGA_INT_NOW_CMD_DONE_INT_CLEAR          ( 1<<7  )
+#define m_RGA_INT_ALL_CMD_DONE_INT_CLEAR          ( 1<<6  )
+#define m_RGA_INT_MMU_INT_CLEAR                   ( 1<<5  )
+#define m_RGA_INT_ERROR_INT_CLEAR                 ( 1<<4  )
+#define m_RGA_INT_NOW_CMD_DONE_INT_FLAG           ( 1<<3  )
+#define m_RGA_INT_ALL_CMD_DONE_INT_FLAG           ( 1<<2  )
+#define m_RGA_INT_MMU_INT_FLAG                    ( 1<<1  )
+#define m_RGA_INT_ERROR_INT_FLAG                  ( 1<<0  )
+
+#define s_RGA_INT_ALL_CMD_DONE_INT_EN(x)          ( (x&0x1)<<10 )
+#define s_RGA_INT_MMU_INT_EN(x)                   ( (x&0x1)<<9  )
+#define s_RGA_INT_ERROR_INT_EN(x)                 ( (x&0x1)<<8  )
+#define s_RGA_INT_NOW_CMD_DONE_INT_CLEAR(x)       ( (x&0x1)<<7  )
+#define s_RGA_INT_ALL_CMD_DONE_INT_CLEAR(x)       ( (x&0x1)<<6  )
+#define s_RGA_INT_MMU_INT_CLEAR(x)                ( (x&0x1)<<5  )
+#define s_RGA_INT_ERROR_INT_CLEAR(x)              ( (x&0x1)<<4  )
+
+
+/*RGA_AXI_ID*/
+#define m_RGA_AXI_ID_MMU_READ                     ( 3<<30 )
+#define m_RGA_AXI_ID_MMU_WRITE                    ( 3<<28 )
+#define m_RGA_AXI_ID_MASK_READ                    ( 0xf<<24 )
+#define m_RGA_AXI_ID_CMD_FET                      ( 0xf<<20 )
+#define m_RGA_AXI_ID_DST_WRITE                    ( 0xf<<16 )
+#define m_RGA_AXI_ID_DST_READ                     ( 0xf<<12 )
+#define m_RGA_AXI_ID_SRC_CR_READ                  ( 0xf<<8  )
+#define m_RGA_AXI_ID_SRC_CB_READ                  ( 0xf<<4  )
+#define m_RGA_AXI_ID_SRC_Y_READ                   ( 0xf<<0  )
+
+#define s_RGA_AXI_ID_MMU_READ(x)                  ( (x&0x3)<<30 )
+#define s_RGA_AXI_ID_MMU_WRITE(x)                 ( (x&0x3)<<28 )
+#define s_RGA_AXI_ID_MASK_READ(x)                 ( (x&0xf)<<24 )
+#define s_RGA_AXI_ID_CMD_FET(x)                   ( (x&0xf)<<20 )
+#define s_RGA_AXI_ID_DST_WRITE(x)                 ( (x&0xf)<<16 )
+#define s_RGA_AXI_ID_DST_READ(x)                  ( (x&0xf)<<12 )
+#define s_RGA_AXI_ID_SRC_CR_READ(x)               ( (x&0xf)<<8  )
+#define s_RGA_AXI_ID_SRC_CB_READ(x)               ( (x&0xf)<<4  )
+#define s_RGA_AXI_ID_SRC_Y_READ(x)                ( (x&0xf)<<0  )
+
+
+/*RGA_MMU_STA_CTRL*/
+#define m_RGA_MMU_STA_CTRL_TLB_STA_CLEAR          ( 1<<3 )
+#define m_RGA_MMU_STA_CTRL_TLB_STA_RESUME         ( 1<<2 )
+#define m_RGA_MMU_STA_CTRL_TLB_STA_PAUSE          ( 1<<1 )
+#define m_RGA_MMU_STA_CTRL_TLB_STA_EN             ( 1<<0 )
+
+#define s_RGA_MMU_STA_CTRL_TLB_STA_CLEAR(x)       ( (x&0x1)<<3 )
+#define s_RGA_MMU_STA_CTRL_TLB_STA_RESUME(x)      ( (x&0x1)<<2 )
+#define s_RGA_MMU_STA_CTRL_TLB_STA_PAUSE(x)       ( (x&0x1)<<1 )
+#define s_RGA_MMU_STA_CTRL_TLB_STA_EN(x)          ( (x&0x1)<<0 )
+
+
+
+/* RGA_MODE_CTRL */
+#define m_RGA_MODE_CTRL_2D_RENDER_MODE            (  7<<0  )
+#define m_RGA_MODE_CTRL_SRC_RGB_PACK              (  1<<3  )
+#define m_RGA_MODE_CTRL_SRC_FORMAT                ( 15<<4  )
+#define m_RGA_MODE_CTRL_SRC_RB_SWAP               (  1<<8  )
+#define m_RGA_MODE_CTRL_SRC_ALPHA_SWAP            (  1<<9  )
+#define m_RGA_MODE_CTRL_SRC_UV_SWAP_MODE          (  1<<10 )
+#define m_RGA_MODE_CTRL_YUV2RGB_CON_MODE          (  3<<11 )
+#define m_RGA_MODE_CTRL_SRC_TRANS_MODE           (0x1f<<13 )
+#define m_RGA_MODE_CTRL_SRC_TR_MODE               (  1<<13 )
+#define m_RGA_MODE_CTRL_SRC_TR_R_EN               (  1<<14 )
+#define m_RGA_MODE_CTRL_SRC_TR_G_EN               (  1<<15 )
+#define m_RGA_MODE_CTRL_SRC_TR_B_EN               (  1<<16 )
+#define m_RGA_MODE_CTRL_SRC_TR_A_EN               (  1<<17 )
+#define m_RGA_MODE_CTRL_ROTATE_MODE               (  3<<18 )
+#define m_RGA_MODE_CTRL_SCALE_MODE                (  3<<20 )
+#define m_RGA_MODE_CTRL_PAT_SEL                   (  1<<22 )
+#define m_RGA_MODE_CTRL_DST_FORMAT                (  3<<23 )
+#define m_RGA_MODE_CTRL_DST_RGB_PACK              (  1<<25 )
+#define m_RGA_MODE_CTRL_DST_RB_SWAP               (  1<<26 )
+#define m_RGA_MODE_CTRL_DST_ALPHA_SWAP            (  1<<27 )
+#define m_RGA_MODE_CTRL_LUT_ENDIAN_MODE           (  1<<28 )
+#define m_RGA_MODE_CTRL_CMD_INT_ENABLE            (  1<<29 )
+#define m_RGA_MODE_CTRL_ZERO_MODE_ENABLE          (  1<<30 )
+#define m_RGA_MODE_CTRL_DST_ALPHA_ENABLE          (  1<<30 )
+
+
+
+#define s_RGA_MODE_CTRL_2D_RENDER_MODE(x)         (  (x&0x7)<<0  )
+#define s_RGA_MODE_CTRL_SRC_RGB_PACK(x)           (  (x&0x1)<<3  )
+#define s_RGA_MODE_CTRL_SRC_FORMAT(x)             (  (x&0xf)<<4  )
+#define s_RGA_MODE_CTRL_SRC_RB_SWAP(x)            (  (x&0x1)<<8  )
+#define s_RGA_MODE_CTRL_SRC_ALPHA_SWAP(x)         (  (x&0x1)<<9  )
+#define s_RGA_MODE_CTRL_SRC_UV_SWAP_MODE(x)       (  (x&0x1)<<10 )
+#define s_RGA_MODE_CTRL_YUV2RGB_CON_MODE(x)       (  (x&0x3)<<11 )
+#define s_RGA_MODE_CTRL_SRC_TRANS_MODE(x)         ( (x&0x1f)<<13 )
+#define s_RGA_MODE_CTRL_SRC_TR_MODE(x)            (  (x&0x1)<<13 )
+#define s_RGA_MODE_CTRL_SRC_TR_R_EN(x)            (  (x&0x1)<<14 )
+#define s_RGA_MODE_CTRL_SRC_TR_G_EN(x)            (  (x&0x1)<<15 )
+#define s_RGA_MODE_CTRL_SRC_TR_B_EN(x)            (  (x&0x1)<<16 )
+#define s_RGA_MODE_CTRL_SRC_TR_A_EN(x)            (  (x&0x1)<<17 )
+#define s_RGA_MODE_CTRL_ROTATE_MODE(x)            (  (x&0x3)<<18 )
+#define s_RGA_MODE_CTRL_SCALE_MODE(x)             (  (x&0x3)<<20 )
+#define s_RGA_MODE_CTRL_PAT_SEL(x)                (  (x&0x1)<<22 )
+#define s_RGA_MODE_CTRL_DST_FORMAT(x)             (  (x&0x3)<<23 )
+#define s_RGA_MODE_CTRL_DST_RGB_PACK(x)           (  (x&0x1)<<25 )
+#define s_RGA_MODE_CTRL_DST_RB_SWAP(x)            (  (x&0x1)<<26 )
+#define s_RGA_MODE_CTRL_DST_ALPHA_SWAP(x)         (  (x&0x1)<<27 )
+#define s_RGA_MODE_CTRL_LUT_ENDIAN_MODE(x)        (  (x&0x1)<<28 )
+#define s_RGA_MODE_CTRL_CMD_INT_ENABLE(x)         (  (x&0x1)<<29 )
+#define s_RGA_MODE_CTRL_ZERO_MODE_ENABLE(x)       (  (x&0x1)<<30 )
+#define s_RGA_MODE_CTRL_DST_ALPHA_ENABLE(x)       (  (x&0x1)<<31 )
+
+
+
+/* RGA_LINE_DRAW */
+#define m_RGA_LINE_DRAW_MAJOR_WIDTH            ( 0x7ff<<0 )
+#define m_RGA_LINE_DRAW_LINE_DIRECTION         (   0x1<<11)
+#define m_RGA_LINE_DRAW_LINE_WIDTH             (   0xf<<12)
+#define m_RGA_LINE_DRAW_INCR_VALUE             ( 0xfff<<16)
+#define m_RGA_LINE_DRAW_DIR_MAJOR              (   0x1<<28)
+#define m_RGA_LINE_DRAW_DIR_SEMI_MAJOR         (   0x1<<29)
+#define m_RGA_LINE_DRAW_LAST_POINT             (   0x1<<30)
+#define m_RGA_LINE_DRAW_ANTI_ALISING           (   0x1<<31)
+
+#define s_RGA_LINE_DRAW_MAJOR_WIDTH(x)            (((x)&0x7ff)<<0 )
+#define s_RGA_LINE_DRAW_LINE_DIRECTION(x)         (  ((x)&0x1)<<11)
+#define s_RGA_LINE_DRAW_LINE_WIDTH(x)             (  ((x)&0xf)<<12)
+#define s_RGA_LINE_DRAW_INCR_VALUE(x)             (((x)&0xfff)<<16)
+#define s_RGA_LINE_DRAW_DIR_MAJOR(x)              (  ((x)&0x1)<<28)
+#define s_RGA_LINE_DRAW_DIR_SEMI_MAJOR(x)         (  ((x)&0x1)<<29)
+#define s_RGA_LINE_DRAW_LAST_POINT(x)             (  ((x)&0x1)<<30)
+#define s_RGA_LINE_DRAW_ANTI_ALISING(x)           (  ((x)&0x1)<<31)
+
+
+/* RGA_ALPHA_CON */
+#define m_RGA_ALPHA_CON_ENABLE                  ( 0x1<<0 )
+#define m_RGA_ALPHA_CON_A_OR_R_SEL              ( 0x1<<1 )
+#define m_RGA_ALPHA_CON_ALPHA_MODE              ( 0x3<<2 )
+#define m_RGA_ALPHA_CON_PD_MODE                 ( 0xf<<4 )
+#define m_RGA_ALPHA_CON_SET_CONSTANT_VALUE      (0xff<<8 )
+#define m_RGA_ALPHA_CON_PD_M_SEL                ( 0x1<<16)
+#define m_RGA_ALPHA_CON_FADING_ENABLE           ( 0x1<<17)
+#define m_RGA_ALPHA_CON_ROP_MODE_SEL            ( 0x3<<18)
+#define m_RGA_ALPHA_CON_CAL_MODE_SEL            ( 0x1<<28)
+#define m_RGA_ALPHA_CON_DITHER_ENABLE           ( 0x1<<29)
+#define m_RGA_ALPHA_CON_GRADIENT_CAL_MODE       ( 0x1<<30)
+#define m_RGA_ALPHA_CON_AA_SEL                  ( 0x1<<31)
+
+#define s_RGA_ALPHA_CON_ENABLE(x)                  ( (x&0x1)<<0 )
+#define s_RGA_ALPHA_CON_A_OR_R_SEL(x)              ( (x&0x1)<<1 )
+#define s_RGA_ALPHA_CON_ALPHA_MODE(x)              ( (x&0x3)<<2 )
+#define s_RGA_ALPHA_CON_PD_MODE(x)                 ( (x&0xf)<<4 )
+#define s_RGA_ALPHA_CON_SET_CONSTANT_VALUE(x)      ((x&0xff)<<8 )
+#define s_RGA_ALPHA_CON_PD_M_SEL(x)                ( (x&0x1)<<16)
+#define s_RGA_ALPHA_CON_FADING_ENABLE(x)           ( (x&0x1)<<17)
+#define s_RGA_ALPHA_CON_ROP_MODE_SEL(x)            ( (x&0x3)<<18)
+#define s_RGA_ALPHA_CON_CAL_MODE_SEL(x)            ( (x&0x1)<<28)
+#define s_RGA_ALPHA_CON_DITHER_ENABLE(x)           ( (x&0x1)<<29)
+#define s_RGA_ALPHA_CON_GRADIENT_CAL_MODE(x)       ( (x&0x1)<<30)
+#define s_RGA_ALPHA_CON_AA_SEL(x)                  ( (x&0x1)<<31)
+
+
+/* blur sharp mode */
+#define m_RGA_BLUR_SHARP_FILTER_MODE                    (  0x1<<25 )
+#define m_RGA_BLUR_SHARP_FILTER_TYPE                    (  0x3<<26 )
+
+#define s_RGA_BLUR_SHARP_FILTER_MODE(x)                 ( (x&0x1)<<25 )
+#define s_RGA_BLUR_SHARP_FILTER_TYPE(x)                 ( (x&0x3)<<26 )
+
+
+/* pre scale mode */
+#define m_RGA_PRE_SCALE_HOR_RATIO                       ( 0x3 <<20 )
+#define m_RGA_PRE_SCALE_VER_RATIO                       ( 0x3 <<22 )
+#define m_RGA_PRE_SCALE_OUTPUT_FORMAT                   ( 0x1 <<24 )
+
+#define s_RGA_PRE_SCALE_HOR_RATIO(x)                    ( (x&0x3) <<20 )
+#define s_RGA_PRE_SCALE_VER_RATIO(x)                    ( (x&0x3) <<22 )
+#define s_RGA_PRE_SCALE_OUTPUT_FORMAT(x)                ( (x&0x1) <<24 )
+
+
+
+/* RGA_MMU_CTRL*/
+#define m_RGA_MMU_CTRL_TLB_ADDR                         ( 0xffffffff<<0)
+#define m_RGA_MMU_CTRL_PAGE_TABLE_SIZE                  ( 0x3<<4 )
+#define m_RGA_MMU_CTRL_MMU_ENABLE                       ( 0x1<<0 )
+#define m_RGA_MMU_CTRL_SRC_FLUSH                        ( 0x1<<1 )
+#define m_RGA_MMU_CTRL_DST_FLUSH                        ( 0x1<<2 )
+#define m_RGA_MMU_CTRL_CMD_CHAN_FLUSH                   ( 0x1<<3 )
+
+#define s_RGA_MMU_CTRL_TLB_ADDR(x)                      ((x&0xffffffff))
+#define s_RGA_MMU_CTRL_PAGE_TABLE_SIZE(x)               ((x&0x3)<<4)
+#define s_RGA_MMU_CTRL_MMU_ENABLE(x)                    ((x&0x1)<<0)
+#define s_RGA_MMU_CTRL_SRC_FLUSH(x)                     ((x&0x1)<<1)
+#define s_RGA_MMU_CTRL_DST_FLUSH(x)                     ((x&0x1)<<2)
+#define s_RGA_MMU_CTRL_CMD_CHAN_FLUSH(x)                ((x&0x1)<<3)
+
+#endif
+
+/*
+#define RGA_MODE_CTRL_OFFSET            0x0
+#define RGA_SRC_Y_MST_OFFSET            0x4
+#define RGA_SRC_CB_MST_OFFSET           0x8
+#define RGA_SRC_CR_MST_OFFSET           0xc
+#define RGA_SRC_VIR_INFO_OFFSET         0x10
+#define RGA_SRC_ACT_INFO_OFFSET         0x14
+#define RGA_SRC_X_PARA_OFFSET           0x18
+#define RGA_SRC_Y_PARA_OFFSET           0x1c
+#define RGA_SRC_TILE_XINFO_OFFSET       0x20
+#define RGA_SRC_TILE_YINFO_OFFSET       0x24
+#define RGA_SRC_TILE_H_INCR_OFFSET      0x28
+#define RGA_SRC_TILE_V_INCR_OFFSET      0x2c
+#define RGA_SRC_TILE_OFFSETX_OFFSET     0x30
+#define RGA_SRC_TILE_OFFSETY_OFFSET     0x34
+#define RGA_SRC_BG_COLOR_OFFSET         0x38
+
+#define RGA_SRC_FG_COLOR_OFFSET         0x3c
+#define RGA_LINE_DRAWING_COLOR_OFFSET   0x3c
+
+#define RGA_SRC_TR_COLOR0_OFFSET        0x40
+#define RGA_CP_GR_A_OFFSET              0x40  //repeat
+
+#define RGA_SRC_TR_COLOR1_OFFSET        0x44
+#define RGA_CP_GR_B_OFFSET              0x44  //repeat
+
+#define RGA_LINE_DRAW_OFFSET            0x48
+#define RGA_PAT_START_POINT_OFFSET      0x48  //repeat
+
+#define RGA_DST_MST_OFFSET              0x4c
+#define RGA_LUT_MST_OFFSET              0x4c  //repeat
+#define RGA_PAT_MST_OFFSET              0x4c  //repeat
+#define RGA_LINE_DRAWING_MST_OFFSET     0x4c  //repeat
+
+#define RGA_DST_VIR_INFO_OFFSET         0x50
+
+#define RGA_DST_CTR_INFO_OFFSET         0x54
+#define RGA_LINE_DRAW_XY_INFO_OFFSET    0x54  //repeat
+
+#define RGA_ALPHA_CON_OFFSET            0x58
+#define RGA_FADING_CON_OFFSET           0x5c
+
+#define RGA_PAT_CON_OFFSET              0x60
+#define RGA_LINE_DRAWING_WIDTH_OFFSET   0x60  //repeat
+
+#define RGA_ROP_CON0_OFFSET             0x64
+#define RGA_CP_GR_G_OFFSET              0x64  //repeat
+#define RGA_PRESCL_CB_MST_OFFSET        0x64  //repeat
+
+#define RGA_ROP_CON1_OFFSET             0x68
+#define RGA_CP_GR_R_OFFSET              0x68  //repeat
+#define RGA_PRESCL_CR_MST_OFFSET        0x68  //repeat
+
+#define RGA_MMU_CTRL_OFFSET             0x6c
+
+
+#define RGA_SYS_CTRL_OFFSET             0x000
+#define RGA_CMD_CTRL_OFFSET             0x004
+#define RGA_CMD_ADDR_OFFSET             0x008
+#define RGA_STATUS_OFFSET               0x00c
+#define RGA_INT_OFFSET                  0x010
+#define RGA_AXI_ID_OFFSET               0x014
+#define RGA_MMU_STA_CTRL_OFFSET         0x018
+#define RGA_MMU_STA_OFFSET              0x01c
+*/
+//hxx
+
+#define RGA_SYS_CTRL_OFFSET             (RGA_SYS_CTRL-0x100)
+#define RGA_CMD_CTRL_OFFSET             (RGA_CMD_CTRL-0x100)
+#define RGA_CMD_ADDR_OFFSET             (RGA_CMD_ADDR-0x100)
+#define RGA_STATUS_OFFSET               (RGA_STATUS-0x100)
+#define RGA_INT_OFFSET                  (RGA_INT-0x100)
+#define RGA_AXI_ID_OFFSET               (RGA_AXI_ID-0x100)
+#define RGA_MMU_STA_CTRL_OFFSET         (RGA_MMU_STA_CTRL-0x100)
+#define RGA_MMU_STA_OFFSET              (RGA_MMU_STA-0x100)
+
+#define RGA_MODE_CTRL_OFFSET            (RGA_MODE_CTRL-0x100)
+#define RGA_SRC_Y_MST_OFFSET            (RGA_SRC_Y_MST-0x100)
+#define RGA_SRC_CB_MST_OFFSET           (RGA_SRC_CB_MST-0x100)
+#define RGA_SRC_CR_MST_OFFSET           (RGA_SRC_CR_MST-0x100)
+#define RGA_SRC_VIR_INFO_OFFSET         (RGA_SRC_VIR_INFO-0x100)
+#define RGA_SRC_ACT_INFO_OFFSET         (RGA_SRC_ACT_INFO-0x100)
+#define RGA_SRC_X_PARA_OFFSET           (RGA_SRC_X_PARA-0x100)
+#define RGA_SRC_Y_PARA_OFFSET           (RGA_SRC_Y_PARA-0x100)
+#define RGA_SRC_TILE_XINFO_OFFSET       (RGA_SRC_TILE_XINFO-0x100)
+#define RGA_SRC_TILE_YINFO_OFFSET       (RGA_SRC_TILE_YINFO-0x100)
+#define RGA_SRC_TILE_H_INCR_OFFSET      (RGA_SRC_TILE_H_INCR-0x100)
+#define RGA_SRC_TILE_V_INCR_OFFSET      (RGA_SRC_TILE_V_INCR-0x100)
+#define RGA_SRC_TILE_OFFSETX_OFFSET     (RGA_SRC_TILE_OFFSETX-0x100)
+#define RGA_SRC_TILE_OFFSETY_OFFSET     (RGA_SRC_TILE_OFFSETY-0x100)
+#define RGA_SRC_BG_COLOR_OFFSET         (RGA_SRC_BG_COLOR-0x100)
+
+#define RGA_SRC_FG_COLOR_OFFSET         (RGA_SRC_FG_COLOR-0x100)
+#define RGA_LINE_DRAWING_COLOR_OFFSET   (RGA_LINE_DRAWING_COLOR-0x100)
+
+#define RGA_SRC_TR_COLOR0_OFFSET        (RGA_SRC_TR_COLOR0-0x100)
+#define RGA_CP_GR_A_OFFSET              (RGA_CP_GR_A-0x100)  //repeat
+
+#define RGA_SRC_TR_COLOR1_OFFSET        (RGA_SRC_TR_COLOR1-0x100)
+#define RGA_CP_GR_B_OFFSET              (RGA_CP_GR_B-0x100)  //repeat
+
+#define RGA_LINE_DRAW_OFFSET            (RGA_LINE_DRAW-0x100)
+#define RGA_PAT_START_POINT_OFFSET      (RGA_PAT_START_POINT-0x100)  //repeat
+
+#define RGA_DST_MST_OFFSET              (RGA_DST_MST-0x100)
+#define RGA_LUT_MST_OFFSET              (RGA_LUT_MST-0x100)  //repeat
+#define RGA_PAT_MST_OFFSET              (RGA_PAT_MST-0x100)  //repeat
+#define RGA_LINE_DRAWING_MST_OFFSET     (RGA_LINE_DRAWING_MST-0x100)  //repeat
+
+#define RGA_DST_VIR_INFO_OFFSET         (RGA_DST_VIR_INFO-0x100)
+
+#define RGA_DST_CTR_INFO_OFFSET         (RGA_DST_CTR_INFO-0x100)
+#define RGA_LINE_DRAW_XY_INFO_OFFSET    (RGA_LINE_DRAW_XY_INFO-0x100)  //repeat
+
+#define RGA_ALPHA_CON_OFFSET            (RGA_ALPHA_CON-0x100)
+
+#define RGA_PAT_CON_OFFSET              (RGA_PAT_CON-0x100)
+#define RGA_LINE_DRAWING_WIDTH_OFFSET   (RGA_DST_VIR_WIDTH_PIX-0x100)  //repeat
+
+#define RGA_ROP_CON0_OFFSET             (RGA_ROP_CON0-0x100)
+#define RGA_CP_GR_G_OFFSET              (RGA_CP_GR_G-0x100)  //repeat
+#define RGA_PRESCL_CB_MST_OFFSET        (RGA_PRESCL_CB_MST-0x100)  //repeat
+
+#define RGA_ROP_CON1_OFFSET             (RGA_ROP_CON1-0x100)
+#define RGA_CP_GR_R_OFFSET              (RGA_CP_GR_R-0x100)  //repeat
+#define RGA_PRESCL_CR_MST_OFFSET        (RGA_PRESCL_CR_MST-0x100)  //repeat
+
+#define RGA_FADING_CON_OFFSET           (RGA_FADING_CON-0x100)
+#define RGA_MMU_TLB_OFFSET              (RGA_MMU_TBL-0x100)
+
+#define RGA_YUV_OUT_CFG_OFFSET         (RGA_YUV_OUT_CFG-0x100)
+#define RGA_DST_UV_MST_OFFSET          (RGA_DST_UV_MST-0x100)
+
+
+
+void matrix_cal(const struct rga_req *msg, TILE_INFO *tile);
+
+
+int RGA_gen_reg_info(const struct rga_req *msg, unsigned char *base);
+uint8_t   RGA_pixel_width_init(uint32_t format);
+
diff --git a/drivers/video/rockchip/rga/rga_rop.h b/drivers/video/rockchip/rga/rga_rop.h
index ed9758711022..c38f05a13dfe 100644
--- a/drivers/video/rockchip/rga/rga_rop.h
+++ b/drivers/video/rockchip/rga/rga_rop.h
@@ -1,56 +1,56 @@
 /* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __RGA_ROP_H__
-#define __RGA_ROP_H__
-
-unsigned int ROP3_code[256] =
-{
-    0x00000007, 0x00000451, 0x00006051, 0x00800051, 0x00007041, 0x00800041, 0x00804830, 0x000004f0,//0
-    0x00800765, 0x000004b0, 0x00000065, 0x000004f4, 0x00000075, 0x000004e6, 0x00804850, 0x00800005,
-
-    0x00006850, 0x00800050, 0x00805028, 0x00000568, 0x00804031, 0x00000471, 0x002b6071, 0x018037aa,//1
-    0x008007aa, 0x00036071, 0x00002c6a, 0x00803631, 0x00002d68, 0x00802721, 0x008002d0, 0x000006d0,
-
-    0x0080066e, 0x00000528, 0x00000066, 0x0000056c, 0x018007aa, 0x0002e06a, 0x00003471, 0x00834031,//2
-    0x00800631, 0x0002b471, 0x00006071, 0x008037aa, 0x000036d0, 0x008002d4, 0x00002d28, 0x000006d4,
-
-    0x0000006e, 0x00000565, 0x00003451, 0x00800006, 0x000034f0, 0x00834830, 0x00800348, 0x00000748,//3
-    0x00002f48, 0x0080034c, 0x000034b0, 0x0000074c, 0x00000031, 0x00834850, 0x000034e6, 0x00800071,
-
-    0x008006f4, 0x00000431, 0x018007a1, 0x00b6e870, 0x00000074, 0x0000046e, 0x00002561, 0x00802f28,//4
-    0x00800728, 0x0002a561, 0x000026c2, 0x008002c6, 0x00007068, 0x018035aa, 0x00002c2a, 0x000006c6,
-
-    0x0000006c, 0x00000475, 0x000024e2, 0x008036b0, 0x00804051, 0x00800004, 0x00800251, 0x00000651,
-    0x00002e4a, 0x0080024e, 0x00000028, 0x00824842, 0x000024a2, 0x0000064e, 0x000024f4, 0x00800068,//5
-
-    0x008006b0, 0x000234f0, 0x00002741, 0x00800345, 0x00003651, 0x00800255, 0x00000030, 0x00834051,
-    0x00a34842, 0x000002b0, 0x00800271, 0x0002b651, 0x00800368, 0x0002a741, 0x0000364e, 0x00806830,//6
-
-    0x00006870, 0x008037a2, 0x00003431, 0x00000745, 0x00002521, 0x00000655, 0x0000346e, 0x00800062,
-    0x008002f0, 0x000236d0, 0x000026d4, 0x00807028, 0x000036c6, 0x00806031, 0x008005aa, 0x00000671,//7
-
-    0x00800671, 0x000005aa, 0x00006031, 0x008036c6, 0x00007028, 0x00802e55, 0x008236d0, 0x000002f0,
-    0x00000070, 0x0080346e, 0x00800655, 0x00802521, 0x00800745, 0x00803431, 0x000037a2, 0x00806870,//8
-
-    0x00006830, 0x0080364e, 0x00822f48, 0x00000361, 0x0082b651, 0x00000271, 0x00800231, 0x002b4051,
-    0x00034051, 0x00800030, 0x0080026e, 0x00803651, 0x0080036c, 0x00802741, 0x008234f0, 0x000006b0,//9
-
-    0x00000068, 0x00802c75, 0x0080064e, 0x008024a2, 0x0002c04a, 0x00800021, 0x00800275, 0x00802e51,
-    0x00800651, 0x00000251, 0x00800000, 0x00004051, 0x000036b0, 0x008024e2, 0x00800475, 0x00000045,//a
-
-    0x008006c6, 0x00802c2a, 0x000035aa, 0x00807068, 0x008002f4, 0x008026c2, 0x00822d68, 0x00000728,
-    0x00002f28, 0x00802561, 0x0080046e, 0x00000046, 0x00836870, 0x000007a2, 0x00800431, 0x00004071,//b
-
-    0x00000071, 0x008034e6, 0x00034850, 0x00800031, 0x0080074c, 0x008034b0, 0x00800365, 0x00802f48,
-    0x00800748, 0x00000341, 0x000026a2, 0x008034f0, 0x00800002, 0x00005048, 0x00800565, 0x00000055,//c
-
-    0x008006d4, 0x00802d28, 0x008002e6, 0x008036d0, 0x000037aa, 0x00806071, 0x0082b471, 0x00000631,
-    0x00002e2a, 0x00803471, 0x00826862, 0x010007aa, 0x0080056c, 0x00000054, 0x00800528, 0x00005068,//d
-
-    0x008006d0, 0x000002d0, 0x00002721, 0x00802d68, 0x00003631, 0x00802c6a, 0x00836071, 0x000007aa,
-    0x010037aa, 0x00a36870, 0x00800471, 0x00004031, 0x00800568, 0x00005028, 0x00000050, 0x00800545,//e
-
-    0x00800001, 0x00004850, 0x008004e6, 0x0000004e, 0x008004f4, 0x0000004c, 0x008004b0, 0x00004870,
-    0x008004f0, 0x00004830, 0x00000048, 0x0080044e, 0x00000051, 0x008004d4, 0x00800451, 0x00800007,//f
-};
-
-#endif
+#ifndef __RGA_ROP_H__
+#define __RGA_ROP_H__
+
+unsigned int ROP3_code[256] =
+{
+    0x00000007, 0x00000451, 0x00006051, 0x00800051, 0x00007041, 0x00800041, 0x00804830, 0x000004f0,//0
+    0x00800765, 0x000004b0, 0x00000065, 0x000004f4, 0x00000075, 0x000004e6, 0x00804850, 0x00800005,
+
+    0x00006850, 0x00800050, 0x00805028, 0x00000568, 0x00804031, 0x00000471, 0x002b6071, 0x018037aa,//1
+    0x008007aa, 0x00036071, 0x00002c6a, 0x00803631, 0x00002d68, 0x00802721, 0x008002d0, 0x000006d0,
+
+    0x0080066e, 0x00000528, 0x00000066, 0x0000056c, 0x018007aa, 0x0002e06a, 0x00003471, 0x00834031,//2
+    0x00800631, 0x0002b471, 0x00006071, 0x008037aa, 0x000036d0, 0x008002d4, 0x00002d28, 0x000006d4,
+
+    0x0000006e, 0x00000565, 0x00003451, 0x00800006, 0x000034f0, 0x00834830, 0x00800348, 0x00000748,//3
+    0x00002f48, 0x0080034c, 0x000034b0, 0x0000074c, 0x00000031, 0x00834850, 0x000034e6, 0x00800071,
+
+    0x008006f4, 0x00000431, 0x018007a1, 0x00b6e870, 0x00000074, 0x0000046e, 0x00002561, 0x00802f28,//4
+    0x00800728, 0x0002a561, 0x000026c2, 0x008002c6, 0x00007068, 0x018035aa, 0x00002c2a, 0x000006c6,
+
+    0x0000006c, 0x00000475, 0x000024e2, 0x008036b0, 0x00804051, 0x00800004, 0x00800251, 0x00000651,
+    0x00002e4a, 0x0080024e, 0x00000028, 0x00824842, 0x000024a2, 0x0000064e, 0x000024f4, 0x00800068,//5
+
+    0x008006b0, 0x000234f0, 0x00002741, 0x00800345, 0x00003651, 0x00800255, 0x00000030, 0x00834051,
+    0x00a34842, 0x000002b0, 0x00800271, 0x0002b651, 0x00800368, 0x0002a741, 0x0000364e, 0x00806830,//6
+
+    0x00006870, 0x008037a2, 0x00003431, 0x00000745, 0x00002521, 0x00000655, 0x0000346e, 0x00800062,
+    0x008002f0, 0x000236d0, 0x000026d4, 0x00807028, 0x000036c6, 0x00806031, 0x008005aa, 0x00000671,//7
+
+    0x00800671, 0x000005aa, 0x00006031, 0x008036c6, 0x00007028, 0x00802e55, 0x008236d0, 0x000002f0,
+    0x00000070, 0x0080346e, 0x00800655, 0x00802521, 0x00800745, 0x00803431, 0x000037a2, 0x00806870,//8
+
+    0x00006830, 0x0080364e, 0x00822f48, 0x00000361, 0x0082b651, 0x00000271, 0x00800231, 0x002b4051,
+    0x00034051, 0x00800030, 0x0080026e, 0x00803651, 0x0080036c, 0x00802741, 0x008234f0, 0x000006b0,//9
+
+    0x00000068, 0x00802c75, 0x0080064e, 0x008024a2, 0x0002c04a, 0x00800021, 0x00800275, 0x00802e51,
+    0x00800651, 0x00000251, 0x00800000, 0x00004051, 0x000036b0, 0x008024e2, 0x00800475, 0x00000045,//a
+
+    0x008006c6, 0x00802c2a, 0x000035aa, 0x00807068, 0x008002f4, 0x008026c2, 0x00822d68, 0x00000728,
+    0x00002f28, 0x00802561, 0x0080046e, 0x00000046, 0x00836870, 0x000007a2, 0x00800431, 0x00004071,//b
+
+    0x00000071, 0x008034e6, 0x00034850, 0x00800031, 0x0080074c, 0x008034b0, 0x00800365, 0x00802f48,
+    0x00800748, 0x00000341, 0x000026a2, 0x008034f0, 0x00800002, 0x00005048, 0x00800565, 0x00000055,//c
+
+    0x008006d4, 0x00802d28, 0x008002e6, 0x008036d0, 0x000037aa, 0x00806071, 0x0082b471, 0x00000631,
+    0x00002e2a, 0x00803471, 0x00826862, 0x010007aa, 0x0080056c, 0x00000054, 0x00800528, 0x00005068,//d
+
+    0x008006d0, 0x000002d0, 0x00002721, 0x00802d68, 0x00003631, 0x00802c6a, 0x00836071, 0x000007aa,
+    0x010037aa, 0x00a36870, 0x00800471, 0x00004031, 0x00800568, 0x00005028, 0x00000050, 0x00800545,//e
+
+    0x00800001, 0x00004850, 0x008004e6, 0x0000004e, 0x008004f4, 0x0000004c, 0x008004b0, 0x00004870,
+    0x008004f0, 0x00004830, 0x00000048, 0x0080044e, 0x00000051, 0x008004d4, 0x00800451, 0x00800007,//f
+};
+
+#endif
diff --git a/drivers/video/rockchip/rga/rga_type.h b/drivers/video/rockchip/rga/rga_type.h
index ce3610ab9b67..30f5df2f38e5 100644
--- a/drivers/video/rockchip/rga/rga_type.h
+++ b/drivers/video/rockchip/rga/rga_type.h
@@ -1,49 +1,49 @@
 /* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __RGA_TYPE_H__
-#define __RGA_TYPE_H__
-
-
-#ifdef __cplusplus
-#if __cplusplus
-}
-#endif
-#endif /* __cplusplus */
-
-typedef  unsigned int     UWORD32;
-typedef  unsigned int     uint32;
-typedef  unsigned int     RK_U32;
-
-typedef  unsigned short   UWORD16;
-typedef  unsigned short   RK_U16;
-
-typedef  unsigned char    UBYTE;
-typedef  unsigned char    RK_U8;
-
-typedef  int              WORD32;
-typedef  int              RK_S32;
-
-typedef  short            WORD16;
-typedef  short            RK_S16;
-
-typedef  char             BYTE;
-typedef  char             RK_S8;
-
-
-#ifndef NULL
-#define NULL              0L
-#endif
-
-#ifndef TRUE
-#define TRUE              1L
-#endif
-
-
-#ifdef __cplusplus
-#if __cplusplus
-}
-#endif
-#endif /* __cplusplus */
-
-
-#endif /* __RGA_TYPR_H__ */
-
+#ifndef __RGA_TYPE_H__
+#define __RGA_TYPE_H__
+
+
+#ifdef __cplusplus
+#if __cplusplus
+}
+#endif
+#endif /* __cplusplus */
+
+typedef  unsigned int     UWORD32;
+typedef  unsigned int     uint32;
+typedef  unsigned int     RK_U32;
+
+typedef  unsigned short   UWORD16;
+typedef  unsigned short   RK_U16;
+
+typedef  unsigned char    UBYTE;
+typedef  unsigned char    RK_U8;
+
+typedef  int              WORD32;
+typedef  int              RK_S32;
+
+typedef  short            WORD16;
+typedef  short            RK_S16;
+
+typedef  char             BYTE;
+typedef  char             RK_S8;
+
+
+#ifndef NULL
+#define NULL              0L
+#endif
+
+#ifndef TRUE
+#define TRUE              1L
+#endif
+
+
+#ifdef __cplusplus
+#if __cplusplus
+}
+#endif
+#endif /* __cplusplus */
+
+
+#endif /* __RGA_TYPR_H__ */
+
diff --git a/drivers/video/rockchip/rga3/include/rga2_reg_info.h b/drivers/video/rockchip/rga3/include/rga2_reg_info.h
index 4c134793d744..66c467d4df46 100644
--- a/drivers/video/rockchip/rga3/include/rga2_reg_info.h
+++ b/drivers/video/rockchip/rga3/include/rga2_reg_info.h
@@ -4,8 +4,6 @@
 
 #include "rga_drv.h"
 
-#define RGA2_USE_MASTER_MODE 1
-
 #define RGA2_SYS_REG_BASE			0x000
 #define RGA2_CSC_REG_BASE			0x060
 #define RGA2_CMD_REG_BASE			0x100
@@ -43,19 +41,6 @@
 #define RGA2_OSD_CUR_FLAGS0			0x090
 #define RGA2_OSD_CUR_FLAGS1			0x09c
 
-/* iommu reg */
-#define RGA2_MMU_DTE_ADDR			0xf00
-#define RGA2_MMU_STATUS				0xf04
-#define RGA2_MMU_COMMAND			0xf08
-#define RGA2_MMU_PAGE_FAULT_ADDR		0xf0c
-#define RGA2_MMU_ZAP_ONE_LINE			0xf10
-#define RGA2_MMU_INT_RAWSTAT			0xf14
-#define RGA2_MMU_INT_CLEAR			0xf18
-#define RGA2_MMU_INT_MASK			0xf1c
-#define RGA2_MMU_INT_STATUS			0xf20
-#define RGA2_MMU_AUTO_GATING			0xf24
-#define RGA2_MMU_REG_LOAD_EN			0xf28
-
 /* mode ctrl */
 #define RGA2_MODE_CTRL_OFFSET			0x000
 #define RGA2_SRC_INFO_OFFSET			0x004
diff --git a/drivers/video/rockchip/rga3/include/rga3_reg_info.h b/drivers/video/rockchip/rga3/include/rga3_reg_info.h
index 78baf74460e8..88d05a5beccb 100644
--- a/drivers/video/rockchip/rga3/include/rga3_reg_info.h
+++ b/drivers/video/rockchip/rga3/include/rga3_reg_info.h
@@ -21,19 +21,6 @@
 #define RGA3_SCAN_CNT				0x038
 #define RGA3_CMD_STATE				0x040
 
-/* iommu reg */
-#define RGA3_MMU_DTE_ADDR			0xf00
-#define RGA3_MMU_STATUS				0xf04
-#define RGA3_MMU_COMMAND			0xf08
-#define RGA3_MMU_PAGE_FAULT_ADDR		0xf0c
-#define RGA3_MMU_ZAP_ONE_LINE			0xf10
-#define RGA3_MMU_INT_RAWSTAT			0xf14
-#define RGA3_MMU_INT_CLEAR			0xf18
-#define RGA3_MMU_INT_MASK			0xf1c
-#define RGA3_MMU_INT_STATUS			0xf20
-#define RGA3_MMU_AUTO_GATING			0xf24
-#define RGA3_MMU_REG_LOAD_EN			0xf28
-
 /* cmd reg */
 #define RGA3_WIN0_RD_CTRL_OFFSET		0x000
 #define RGA3_WIN0_Y_BASE_OFFSET			0x010
@@ -152,6 +139,9 @@
 #define m_RGA3_CMD_CTRL_CMD_INCR_VALID_P			(0x1 << 1)
 #define m_RGA3_CMD_CTRL_CMD_LINE_ST_P				(0x1 << 0)
 
+/* RGA3_RO_SRST */
+#define m_RGA3_RO_SRST_RO_RST_DONE				(0x3f << 0)
+
 /* RGA3_CMD_STATE */
 #define m_RGA3_CMD_STATE_CMD_CNT_CUR				(0xfff << 16)
 #define m_RGA3_CMD_STATE_CMD_WORKING				(0x1 << 0)
diff --git a/drivers/video/rockchip/rga3/include/rga_iommu.h b/drivers/video/rockchip/rga3/include/rga_iommu.h
index fd37377a74ad..b80a1f48bb25 100644
--- a/drivers/video/rockchip/rga3/include/rga_iommu.h
+++ b/drivers/video/rockchip/rga3/include/rga_iommu.h
@@ -4,6 +4,42 @@
 
 #include "rga_drv.h"
 
+/* RGA_IOMMU register offsets */
+#define RGA_IOMMU_BASE				0xf00
+#define RGA_IOMMU_DTE_ADDR			(RGA_IOMMU_BASE + 0x00) /* Directory table address */
+#define RGA_IOMMU_STATUS			(RGA_IOMMU_BASE + 0x04)
+#define RGA_IOMMU_COMMAND			(RGA_IOMMU_BASE + 0x08)
+#define RGA_IOMMU_PAGE_FAULT_ADDR		(RGA_IOMMU_BASE + 0x0C) /* IOVA of last page fault */
+#define RGA_IOMMU_ZAP_ONE_LINE			(RGA_IOMMU_BASE + 0x10) /* Shootdown one IOTLB entry */
+#define RGA_IOMMU_INT_RAWSTAT			(RGA_IOMMU_BASE + 0x14) /* IRQ status ignoring mask */
+#define RGA_IOMMU_INT_CLEAR			(RGA_IOMMU_BASE + 0x18) /* Acknowledge and re-arm irq */
+#define RGA_IOMMU_INT_MASK			(RGA_IOMMU_BASE + 0x1C) /* IRQ enable */
+#define RGA_IOMMU_INT_STATUS			(RGA_IOMMU_BASE + 0x20) /* IRQ status after masking */
+#define RGA_IOMMU_AUTO_GATING			(RGA_IOMMU_BASE + 0x24)
+
+/* RGA_IOMMU_STATUS fields */
+#define RGA_IOMMU_STATUS_PAGING_ENABLED		BIT(0)
+#define RGA_IOMMU_STATUS_PAGE_FAULT_ACTIVE	BIT(1)
+#define RGA_IOMMU_STATUS_STALL_ACTIVE		BIT(2)
+#define RGA_IOMMU_STATUS_IDLE			BIT(3)
+#define RGA_IOMMU_STATUS_REPLAY_BUFFER_EMPTY	BIT(4)
+#define RGA_IOMMU_STATUS_PAGE_FAULT_IS_WRITE	BIT(5)
+#define RGA_IOMMU_STATUS_STALL_NOT_ACTIVE	BIT(31)
+
+/* RGA_IOMMU_COMMAND command values */
+#define RGA_IOMMU_CMD_ENABLE_PAGING		0 /* Enable memory translation */
+#define RGA_IOMMU_CMD_DISABLE_PAGING		1 /* Disable memory translation */
+#define RGA_IOMMU_CMD_ENABLE_STALL		2 /* Stall paging to allow other cmds */
+#define RGA_IOMMU_CMD_DISABLE_STALL		3 /* Stop stall re-enables paging */
+#define RGA_IOMMU_CMD_ZAP_CACHE			4 /* Shoot down entire IOTLB */
+#define RGA_IOMMU_CMD_PAGE_FAULT_DONE		5 /* Clear page fault */
+#define RGA_IOMMU_CMD_FORCE_RESET		6 /* Reset all registers */
+
+/* RGA_IOMMU_INT_* register fields */
+#define RGA_IOMMU_IRQ_PAGE_FAULT		0x01 /* page fault */
+#define RGA_IOMMU_IRQ_BUS_ERROR			0x02 /* bus read error */
+#define RGA_IOMMU_IRQ_MASK			(RGA_IOMMU_IRQ_PAGE_FAULT | RGA_IOMMU_IRQ_BUS_ERROR)
+
 /*
  * The maximum input is 8192*8192, the maximum output is 4096*4096
  * The size of physical pages requested is:
diff --git a/drivers/video/rockchip/rga3/rga2_reg_info.c b/drivers/video/rockchip/rga3/rga2_reg_info.c
index 0d433138bbd0..c95ea04be224 100644
--- a/drivers/video/rockchip/rga3/rga2_reg_info.c
+++ b/drivers/video/rockchip/rga3/rga2_reg_info.c
@@ -164,12 +164,8 @@ static void RGA2_set_mode_ctrl(u8 *base, struct rga2_req *msg)
 
 	bRGA_MODE_CTL = (u32 *) (base + RGA2_MODE_CTRL_OFFSET);
 
-	if (msg->render_mode == 4)
-		render_mode = 3;
-
-	/* In slave mode, the current frame completion interrupt must be enabled. */
-	if (!RGA2_USE_MASTER_MODE)
-		msg->CMD_fin_int_enable = 1;
+	if (msg->render_mode == UPDATE_PALETTE_TABLE_MODE)
+		render_mode = 0x3;
 
 	reg =
 		((reg & (~m_RGA2_MODE_CTRL_SW_RENDER_MODE)) |
@@ -2066,7 +2062,7 @@ static void rga2_soft_reset(struct rga_scheduler_t *scheduler)
 	u32 iommu_dte_addr;
 
 	if (scheduler->data->mmu == RGA_IOMMU)
-		iommu_dte_addr = rga_read(0xf00, scheduler);
+		iommu_dte_addr = rga_read(RGA_IOMMU_DTE_ADDR, scheduler);
 
 	rga_write(m_RGA2_SYS_CTRL_ACLK_SRESET_P | m_RGA2_SYS_CTRL_CCLK_SRESET_P |
 		  m_RGA2_SYS_CTRL_RST_PROTECT_P,
@@ -2083,13 +2079,16 @@ static void rga2_soft_reset(struct rga_scheduler_t *scheduler)
 	}
 
 	if (scheduler->data->mmu == RGA_IOMMU) {
-		rga_write(iommu_dte_addr, RGA2_MMU_DTE_ADDR, scheduler);
+		rga_write(iommu_dte_addr, RGA_IOMMU_DTE_ADDR, scheduler);
 		/* enable iommu */
-		rga_write(0, RGA2_MMU_COMMAND, scheduler);
+		rga_write(RGA_IOMMU_CMD_ENABLE_PAGING, RGA_IOMMU_COMMAND, scheduler);
 	}
 
 	if (i == RGA_RESET_TIMEOUT)
-		pr_err("soft reset timeout.\n");
+		pr_err("RAG2 soft reset timeout.\n");
+	else
+		pr_info("RGA2 soft reset complete.\n");
+
 }
 
 static int rga2_check_param(const struct rga_hw_data *data, const struct rga2_req *req)
@@ -2268,6 +2267,10 @@ static int rga2_init_reg(struct rga_job *job)
 		}
 	}
 
+	/* In slave mode, the current frame completion interrupt must be enabled. */
+	if (scheduler->data->mmu == RGA_IOMMU)
+		req.CMD_fin_int_enable = 1;
+
 	if (rga2_gen_reg_info((uint8_t *)job->cmd_reg, &req) == -1) {
 		pr_err("gen reg info error\n");
 		return -EINVAL;
@@ -2411,9 +2414,19 @@ static void rga2_set_reg_full_csc(struct rga_job *job, struct rga_scheduler_t *s
 static int rga2_set_reg(struct rga_job *job, struct rga_scheduler_t *scheduler)
 {
 	int i;
+	bool master_mode_en;
 	uint32_t sys_ctrl;
 	ktime_t now = ktime_get();
 
+	/*
+	 * Currently there is no iova allocated for storing cmd for the IOMMU device,
+	 * so the iommu device needs to use the slave mode.
+	 */
+	if (scheduler->data->mmu != RGA_IOMMU)
+		master_mode_en = true;
+	else
+		master_mode_en = false;
+
 	if (job->pre_intr_info.enable)
 		rga2_set_pre_intr_reg(job, scheduler);
 
@@ -2444,7 +2457,7 @@ static int rga2_set_reg(struct rga_job *job, struct rga_scheduler_t *scheduler)
 		   m_RGA2_SYS_CTRL_RST_PROTECT_P | m_RGA2_SYS_CTRL_DST_WR_OPT_DIS |
 		   m_RGA2_SYS_CTRL_SRC0YUV420SP_RD_OPT_DIS;
 
-	if (RGA2_USE_MASTER_MODE) {
+	if (master_mode_en) {
 		/* master mode */
 		sys_ctrl |= s_RGA2_SYS_CTRL_CMD_MODE(1);
 
@@ -2536,6 +2549,9 @@ static int rga2_irq(struct rga_scheduler_t *scheduler)
 	if (job == NULL)
 		return IRQ_HANDLED;
 
+	if (test_bit(RGA_JOB_STATE_INTR_ERR, &job->state))
+		return IRQ_WAKE_THREAD;
+
 	job->intr_status = rga_read(RGA2_INT, scheduler);
 	job->hw_status = rga_read(RGA2_STATUS2, scheduler);
 	job->cmd_status = rga_read(RGA2_STATUS1, scheduler);
@@ -2586,6 +2602,11 @@ static int rga2_isr_thread(struct rga_job *job, struct rga_scheduler_t *schedule
 			pr_err("mmu failed, please check size of the buffer or whether the buffer has been freed.\n");
 			job->ret = -EACCES;
 		}
+
+		if (job->ret == 0) {
+			pr_err("rga intr error[0x%x]!\n", job->intr_status);
+			job->ret = -EFAULT;
+		}
 	}
 
 	return IRQ_HANDLED;
diff --git a/drivers/video/rockchip/rga3/rga3_reg_info.c b/drivers/video/rockchip/rga3/rga3_reg_info.c
index efb579b6b532..bc9fa49baa45 100644
--- a/drivers/video/rockchip/rga3/rga3_reg_info.c
+++ b/drivers/video/rockchip/rga3/rga3_reg_info.c
@@ -8,6 +8,8 @@
 #define pr_fmt(fmt) "rga3_reg: " fmt
 
 #include "rga3_reg_info.h"
+#include "rga_dma_buf.h"
+#include "rga_iommu.h"
 #include "rga_common.h"
 #include "rga_debugger.h"
 #include "rga_hw_config.h"
@@ -1592,54 +1594,35 @@ static void rga_cmd_to_rga3_cmd(struct rga_req *req_rga, struct rga3_req *req)
 static void rga3_soft_reset(struct rga_scheduler_t *scheduler)
 {
 	u32 i;
-	u32 reg;
-	u32 mmu_addr;
+	u32 iommu_dte_addr;
 
-	mmu_addr = rga_read(0xf00, scheduler);
+	if (scheduler->data->mmu == RGA_IOMMU)
+		iommu_dte_addr = rga_read(RGA_IOMMU_DTE_ADDR, scheduler);
 
 	rga_write(s_RGA3_SYS_CTRL_CCLK_SRESET(1) | s_RGA3_SYS_CTRL_ACLK_SRESET(1),
 		  RGA3_SYS_CTRL, scheduler);
 
-	pr_err("soft reset sys_ctrl = %x, ro_rest = %x",
-		rga_read(RGA3_SYS_CTRL, scheduler),
-		rga_read(RGA3_RO_SRST, scheduler));
-
-	mdelay(20);
-
-	pr_err("soft reset sys_ctrl = %x, ro_rest = %x",
-		rga_read(RGA3_SYS_CTRL, scheduler),
-		rga_read(RGA3_RO_SRST, scheduler));
-
-	rga_write(s_RGA3_SYS_CTRL_CCLK_SRESET(0) | s_RGA3_SYS_CTRL_ACLK_SRESET(0),
-		  RGA3_SYS_CTRL, scheduler);
-
-	pr_err("soft after reset sys_ctrl = %x, ro_rest = %x",
-		rga_read(RGA3_SYS_CTRL, scheduler),
-		rga_read(RGA3_RO_SRST, scheduler));
-
-	rga_write(m_RGA3_INT_FRM_DONE | m_RGA3_INT_CMD_LINE_FINISH | m_RGA3_INT_ERROR_MASK,
-		  RGA3_INT_CLR, scheduler);
-
-	rga_write(mmu_addr, RGA3_MMU_DTE_ADDR, scheduler);
-	rga_write(0, RGA3_MMU_COMMAND, scheduler);
-
-	if (DEBUGGER_EN(INT_FLAG))
-		pr_info("soft reset, INTR[0x%x], HW_STATUS[0x%x], CMD_STATUS[0x%x]\n",
-			rga_read(RGA3_INT_RAW, scheduler),
-			rga_read(RGA3_STATUS0, scheduler),
-			rga_read(RGA3_CMD_STATE, scheduler));
-
 	for (i = 0; i < RGA_RESET_TIMEOUT; i++) {
-		reg = rga_read(RGA3_SYS_CTRL, scheduler) & 1;
-
-		if (reg == 0)
+		if (rga_read(RGA3_RO_SRST, scheduler) & m_RGA3_RO_SRST_RO_RST_DONE)
 			break;
 
 		udelay(1);
 	}
 
+	rga_write(s_RGA3_SYS_CTRL_CCLK_SRESET(0) | s_RGA3_SYS_CTRL_ACLK_SRESET(0),
+		  RGA3_SYS_CTRL, scheduler);
+
+	if (scheduler->data->mmu == RGA_IOMMU) {
+		rga_write(iommu_dte_addr, RGA_IOMMU_DTE_ADDR, scheduler);
+		/* enable iommu */
+		rga_write(RGA_IOMMU_CMD_ENABLE_PAGING, RGA_IOMMU_COMMAND, scheduler);
+	}
+
 	if (i == RGA_RESET_TIMEOUT)
-		pr_err("soft reset timeout.\n");
+		pr_err("RGA3 soft reset timeout. SYS_CTRL[0x%x], RO_SRST[0x%x]\n",
+		       rga_read(RGA3_SYS_CTRL, scheduler), rga_read(RGA3_RO_SRST, scheduler));
+	else
+		pr_info("RGA3 soft reset complete.\n");
 }
 
 static int rga3_scale_check(const struct rga3_req *req)
@@ -1899,9 +1882,19 @@ static void rga3_dump_read_back_reg(struct rga_scheduler_t *scheduler)
 static int rga3_set_reg(struct rga_job *job, struct rga_scheduler_t *scheduler)
 {
 	int i;
+	bool master_mode_en;
 	uint32_t sys_ctrl;
 	ktime_t now = ktime_get();
 
+	/*
+	 * Currently there is no iova allocated for storing cmd for the IOMMU device,
+	 * so the iommu device needs to use the slave mode.
+	 */
+	if (scheduler->data->mmu != RGA_IOMMU)
+		master_mode_en = true;
+	else
+		master_mode_en = false;
+
 	if (DEBUGGER_EN(REG)) {
 		uint32_t *p;
 
@@ -1917,24 +1910,25 @@ static int rga3_set_reg(struct rga_job *job, struct rga_scheduler_t *scheduler)
 	rga_write(m_RGA3_INT_FRM_DONE | m_RGA3_INT_CMD_LINE_FINISH | m_RGA3_INT_ERROR_MASK,
 		  RGA3_INT_EN, scheduler);
 
-#if 0
-	/* master mode */
-	sys_ctrl = s_RGA3_SYS_CTRL_CMD_MODE(1);
+	if (master_mode_en) {
+		/* master mode */
+		sys_ctrl = s_RGA3_SYS_CTRL_CMD_MODE(1);
 
-	rga_dma_flush_range(&job->cmd_reg[0], &job->cmd_reg[50], scheduler);
+		/* cmd buffer flush cache to ddr */
+		rga_dma_sync_flush_range(&job->cmd_reg[0], &job->cmd_reg[50], scheduler);
 
-	rga_write(virt_to_phys(job->cmd_reg), RGA3_CMD_ADDR, scheduler);
-	rga_write(sys_ctrl, RGA3_SYS_CTRL, scheduler);
-	rga_write(m_RGA3_CMD_CTRL_CMD_LINE_ST_P, RGA3_CMD_CTRL, scheduler);
-#else
-	/* slave mode */
-	sys_ctrl = s_RGA3_SYS_CTRL_CMD_MODE(0) | m_RGA3_SYS_CTRL_RGA_SART;
+		rga_write(virt_to_phys(job->cmd_reg), RGA3_CMD_ADDR, scheduler);
+		rga_write(sys_ctrl, RGA3_SYS_CTRL, scheduler);
+		rga_write(m_RGA3_CMD_CTRL_CMD_LINE_ST_P, RGA3_CMD_CTRL, scheduler);
+	} else {
+		/* slave mode */
+		sys_ctrl = s_RGA3_SYS_CTRL_CMD_MODE(0) | m_RGA3_SYS_CTRL_RGA_SART;
 
-	for (i = 0; i <= 50; i++)
-		rga_write(job->cmd_reg[i], 0x100 + i * 4, scheduler);
+		for (i = 0; i <= 50; i++)
+			rga_write(job->cmd_reg[i], 0x100 + i * 4, scheduler);
 
-	rga_write(sys_ctrl, RGA3_SYS_CTRL, scheduler);
-#endif
+		rga_write(sys_ctrl, RGA3_SYS_CTRL, scheduler);
+	}
 
 	if (DEBUGGER_EN(REG)) {
 		pr_info("sys_ctrl = 0x%x, int_en = 0x%x, int_raw = 0x%x\n",
@@ -1992,6 +1986,9 @@ static int rga3_irq(struct rga_scheduler_t *scheduler)
 	if (job == NULL)
 		return IRQ_HANDLED;
 
+	if (test_bit(RGA_JOB_STATE_INTR_ERR, &job->state))
+		return IRQ_WAKE_THREAD;
+
 	job->intr_status = rga_read(RGA3_INT_RAW, scheduler);
 	job->hw_status = rga_read(RGA3_STATUS0, scheduler);
 	job->cmd_status = rga_read(RGA3_CMD_STATE, scheduler);
@@ -2026,10 +2023,7 @@ static int rga3_isr_thread(struct rga_job *job, struct rga_scheduler_t *schedule
 			rga_read(RGA3_CMD_STATE, scheduler));
 
 	if (test_bit(RGA_JOB_STATE_INTR_ERR, &job->state)) {
-		if (job->intr_status & m_RGA3_INT_RGA_MMU_INTR) {
-			pr_err("iommu error, please check size of the buffer or whether the buffer has been freed.\n");
-			job->ret = -EACCES;
-		} else if (job->intr_status & m_RGA3_INT_RAG_MI_RD_BUS_ERR) {
+		if (job->intr_status & m_RGA3_INT_RAG_MI_RD_BUS_ERR) {
 			pr_err("DMA read bus error, please check size of the input_buffer or whether the buffer has been freed.\n");
 			job->ret = -EFAULT;
 		} else if (job->intr_status & m_RGA3_INT_WIN0_FBCD_DEC_ERR) {
@@ -2041,7 +2035,9 @@ static int rga3_isr_thread(struct rga_job *job, struct rga_scheduler_t *schedule
 		} else if (job->intr_status & m_RGA3_INT_RGA_MI_WR_BUS_ERR) {
 			pr_err("wr buss error, please check size of the output_buffer or whether the buffer has been freed.\n");
 			job->ret = -EFAULT;
-		} else {
+		}
+
+		if (job->ret == 0) {
 			pr_err("rga intr error[0x%x]!\n", job->intr_status);
 			job->ret = -EFAULT;
 		}
diff --git a/drivers/video/rockchip/rga3/rga_iommu.c b/drivers/video/rockchip/rga3/rga_iommu.c
index 3b7a4ef88aa2..f4fb84aec604 100644
--- a/drivers/video/rockchip/rga3/rga_iommu.c
+++ b/drivers/video/rockchip/rga3/rga_iommu.c
@@ -5,7 +5,7 @@
  * Author: Huang Lee <Putin.li@rock-chips.com>
  */
 
-#define pr_fmt(fmt) "rga2_mmu: " fmt
+#define pr_fmt(fmt) "rga_iommu: " fmt
 
 #include "rga_iommu.h"
 #include "rga_dma_buf.h"
@@ -221,6 +221,38 @@ void rga_mmu_base_free(struct rga_mmu_base **mmu_base)
 	*mmu_base = NULL;
 }
 
+static int rga_iommu_intr_fault_handler(struct iommu_domain *iommu, struct device *iommu_dev,
+					unsigned long iova, int status, void *arg)
+{
+	struct rga_scheduler_t *scheduler = (struct rga_scheduler_t *)arg;
+	struct rga_job *job = scheduler->running_job;
+
+	if (job == NULL)
+		return 0;
+
+	pr_err("IOMMU intr fault, IOVA[0x%lx], STATUS[0x%x]\n", iova, status);
+	if (scheduler->ops->irq)
+		scheduler->ops->irq(scheduler);
+
+	/* iommu interrupts on rga2 do not affect rga2 itself. */
+	if (!test_bit(RGA_JOB_STATE_INTR_ERR, &job->state)) {
+		set_bit(RGA_JOB_STATE_INTR_ERR, &job->state);
+		scheduler->ops->soft_reset(scheduler);
+	}
+
+	if (status & RGA_IOMMU_IRQ_PAGE_FAULT) {
+		pr_err("RGA IOMMU: page fault! Please check the memory size.\n");
+		job->ret = -EACCES;
+	} else if (status & RGA_IOMMU_IRQ_BUS_ERROR) {
+		pr_err("RGA IOMMU: bus error! Please check if the memory is invalid or has been freed.\n");
+		job->ret = -EACCES;
+	} else {
+		pr_err("RGA IOMMU: Wrong IOMMU interrupt signal!\n");
+	}
+
+	return 0;
+}
+
 int rga_iommu_detach(struct rga_iommu_info *info)
 {
 	if (!info)
@@ -306,6 +338,9 @@ int rga_iommu_bind(void)
 			if (main_iommu == NULL) {
 				main_iommu = scheduler->iommu_info;
 				main_iommu_index = i;
+				iommu_set_fault_handler(main_iommu->domain,
+							rga_iommu_intr_fault_handler,
+							(void *)scheduler);
 			} else {
 				scheduler->iommu_info->domain = main_iommu->domain;
 				scheduler->iommu_info->default_dev = main_iommu->default_dev;
diff --git a/fs/cifs/dir.c b/fs/cifs/dir.c
index 0d7238cb45b5..7a67d47034e2 100644
--- a/fs/cifs/dir.c
+++ b/fs/cifs/dir.c
@@ -467,7 +467,7 @@ cifs_atomic_open(struct inode *inode, struct dentry *direntry,
 	struct tcon_link *tlink;
 	struct cifs_tcon *tcon;
 	struct TCP_Server_Info *server;
-	struct cifs_fid fid;
+	struct cifs_fid fid = {};
 	struct cifs_pending_open open;
 	__u32 oplock;
 	struct cifsFileInfo *file_info;
diff --git a/fs/cifs/inode.c b/fs/cifs/inode.c
index b11a919b9cab..b31a977522d2 100644
--- a/fs/cifs/inode.c
+++ b/fs/cifs/inode.c
@@ -360,9 +360,12 @@ cifs_get_file_info_unix(struct file *filp)
 	} else if (rc == -EREMOTE) {
 		cifs_create_dfs_fattr(&fattr, inode->i_sb);
 		rc = 0;
-	}
+	} else
+		goto cifs_gfiunix_out;
 
 	cifs_fattr_to_inode(inode, &fattr);
+
+cifs_gfiunix_out:
 	free_xid(xid);
 	return rc;
 }
diff --git a/include/dt-bindings/soc/rockchip-system-status.h b/include/dt-bindings/soc/rockchip-system-status.h
index b6689e969672..fefd62642e42 100644
--- a/include/dt-bindings/soc/rockchip-system-status.h
+++ b/include/dt-bindings/soc/rockchip-system-status.h
@@ -36,10 +36,12 @@
 #define SYS_STATUS_LOW_POWER	(1 << 17)
 #define SYS_STATUS_HDMIRX	(1 << 18)
 #define SYS_STATUS_VIDEO_SVEP	(1 << 19)
+#define SYS_STATUS_VIDEO_4K_60P	(1 << 20)
 
 #define SYS_STATUS_VIDEO	(SYS_STATUS_VIDEO_4K | \
 				 SYS_STATUS_VIDEO_1080P | \
-				 SYS_STATUS_VIDEO_4K_10B)
+				 SYS_STATUS_VIDEO_4K_10B | \
+				 SYS_STATUS_VIDEO_4K_60P)
 #define SYS_STATUS_DUALVIEW	(SYS_STATUS_LCDC0 | SYS_STATUS_LCDC1)
 
 #define DMC_FREQ_LEVEL_LOW	(0x1 << 0)
diff --git a/include/linux/mfd/max96752f.h b/include/linux/mfd/max96752f.h
deleted file mode 100644
index 78cc3f6b7dae..000000000000
--- a/include/linux/mfd/max96752f.h
+++ /dev/null
@@ -1,114 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * Defining registers address and its bit definitions of MAX96752F
- *
- * Copyright (c) 2022 Rockchip Electronics Co. Ltd.
- */
-
-#ifndef _MFD_MAX96752F_H_
-#define _MFD_MAX96752F_H_
-
-#include <linux/bitfield.h>
-
-#define GPIO_A_REG(gpio)	(0x0200 + ((gpio) * 3))
-#define GPIO_B_REG(gpio)	(0x0201 + ((gpio) * 3))
-#define GPIO_C_REG(gpio)	(0x0202 + ((gpio) * 3))
-#define OLDI_REG(x)		(0x01cd + (x))
-
-/* 0000h */
-#define DEV_ADDR		GENMASK(7, 1)
-#define CFG_BLOCK		BIT(0)
-
-/* 0001h */
-#define LVDS_HALFSW		BIT(7)
-#define IIC_2_EN		BIT(5)
-#define IIC_1_EN		BIT(4)
-#define TX_RATE			GENMASK(3, 2)
-#define RX_RATE			GENMASK(1, 0)
-
-/* 0002h */
-#define LOCK_CFG		BIT(7)
-#define VID_EN			BIT(6)
-#define DIS_LOCAL_CC		BIT(5)
-#define DIS_REM_CC		BIT(4)
-#define AUD_TX_EN		BIT(2)
-
-/* 0003h */
-#define GMSL2			BIT(5)
-#define I2CSEL			BIT(4)
-#define UART_2_EN		BIT(3)
-#define UART_1_EN		BIT(2)
-#define VIDEO_LOCK		BIT(0)
-
-/* 000Dh */
-#define DEV_ID			GENMASK(7, 0)
-
-/* 000Eh */
-#define DEV_REV			GENMASK(3, 0)
-
-/* 0010h */
-#define RESET_ALL		BIT(7)
-#define RESET_LINK		BIT(6)
-#define RESET_ONESHOT		BIT(5)
-#define AUTO_LINK		BIT(4)
-#define SLEEP			BIT(3)
-#define LINK_CFG		GENMASK(1, 0)
-
-/* 0050h */
-#define STR_SEL			GENMASK(1, 0)
-
-/* 0073h */
-#define TX_SRC_ID		GENMASK(2, 0)
-
-/* 0108h */
-#define VID_LOCK		BIT(6)
-
-/* 0140h */
-#define AUD_RX_EN		BIT(0)
-
-/* 01CEh */
-#define OLDI_OUTSEL		BIT(7)
-#define OLDI_FORMAT		BIT(6)
-#define OLDI_4TH_LANE		BIT(5)
-#define OLDI_SWAP_AB		BIT(4)
-#define OLDI_SPL_EN		BIT(3)
-#define OLDI_SPL_MODE		GENMASK(2, 1)
-#define OLDI_SPL_POL		BIT(0)
-
-/* 01CFh */
-#define PD_LVDS_B		BIT(7)
-#define PD_LVDS_A		BIT(6)
-#define OLDI_DUP		BIT(1)
-#define SSEN			BIT(0)
-
-/* 0200h */
-#define RES_CFG			BIT(7)
-#define TX_PRIO			BIT(6)
-#define TX_COMP_EN		BIT(5)
-#define GPIO_OUT		BIT(4)
-#define GPIO_IN			BIT(3)
-#define GPIO_RX_EN		BIT(2)
-#define GPIO_TX_EN		BIT(1)
-#define GPIO_OUT_DIS		BIT(0)
-
-/* 0201h */
-#define PULL_UPDN_SEL		GENMASK(7, 6)
-#define OUT_TYPE		BIT(5)
-#define GPIO_TX_ID		GENMASK(4, 0)
-
-/* 0202h */
-#define OVR_RES_CFG		BIT(7)
-#define GPIO_RX_ID		GENMASK(4, 0)
-
-struct max96752f {
-	struct device *dev;
-	struct regmap *regmap;
-	struct i2c_client *client;
-	struct i2c_mux_core *muxc;
-	struct gpio_desc *enable_gpio;
-	u32 stream_id;
-};
-
-void max96752f_init(struct max96752f *max96752f);
-
-#endif /* _MFD_MAX96752F_H_ */
diff --git a/include/linux/mfd/max96776.h b/include/linux/mfd/max96776.h
deleted file mode 100644
index fd445a7ac4b5..000000000000
--- a/include/linux/mfd/max96776.h
+++ /dev/null
@@ -1,131 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * Defining registers address and its bit definitions of MAX96776
- *
- * Copyright (c) 2022 Rockchip Electronics Co. Ltd.
- */
-
-#ifndef _MFD_MAX96776_H_
-#define _MFD_MAX96776_H_
-
-#include <linux/bitfield.h>
-
-/* 07f0h */
-#define TRAINING_SUCCESSFUL	BIT(0)
-
-/* 1700h */
-#define CMD_RESET		BIT(7)
-
-/* 6230h */
-#define HPD_PRESENT		BIT(0)
-
-/* e776h */
-#define REBOOT_TRAINNING	BIT(0)
-#define RUN_LINK_TRAINING	BIT(1)
-#define AUX_READ		BIT(4)
-#define AUX_WRITE		BIT(5)
-
-/* e777h */
-#define RUN_COMMAND		BIT(7)
-
-/* e778h */
-#define USER_DATA1_B0		GENMASK(7, 0)
-
-/* e779h */
-#define USER_DATA1_B1		GENMASK(7, 0)
-
-/* e77ah */
-#define USER_DATA2_B0		GENMASK(7, 0)
-
-/* e77ch */
-#define USER_DATA3_B0		GENMASK(7, 0)
-
-/* e790h */
-#define LINK_RATE		GENMASK(4, 0)
-
-/* e792h */
-#define LANE_COUNT		GENMASK(2, 0)
-
-/* e794h */
-#define HRES_B0			GENMASK(7, 0)
-
-/* e795h */
-#define HRES_B1			GENMASK(7, 0)
-
-/* e796h */
-#define HFP_B0			GENMASK(7, 0)
-
-/* e797h */
-#define HFP_B1			GENMASK(7, 0)
-
-/* e798h */
-#define HSW_B0			GENMASK(7, 0)
-
-/* e799h */
-#define HSW_B1			GENMASK(7, 0)
-
-/* e79ah */
-#define HBP_B0			GENMASK(7, 0)
-
-/* e79bh */
-#define HBP_B1			GENMASK(7, 0)
-
-/* e79ch */
-#define VRES_B0			GENMASK(7, 0)
-
-/* e79dh */
-#define VRES_B1			GENMASK(7, 0)
-
-/* e79eh */
-#define VFP_B0			GENMASK(7, 0)
-
-/* e79fh */
-#define VFP_B1			GENMASK(7, 0)
-
-/* e7a0h */
-#define VSW_B0			GENMASK(7, 0)
-
-/* e7a1h */
-#define VSW_B1			GENMASK(7, 0)
-
-/* e7a2h */
-#define VBP_B0			GENMASK(7, 0)
-
-/* e7a3h */
-#define VBP_B1			GENMASK(7, 0)
-
-/* e7a4h */
-#define HWORDS_B0		GENMASK(7, 0)
-
-/* e7a5h */
-#define HWORDS_B1		GENMASK(7, 0)
-
-/* e7a6h */
-#define MVID_B0			GENMASK(7, 0)
-
-/* e7a7h */
-#define MVID_B1			GENMASK(7, 0)
-
-/* e7a8h */
-#define NVID_B0			GENMASK(7, 0)
-
-/* e7a9h */
-#define NVID_B1			GENMASK(7, 0)
-
-/* e7aah */
-#define TUC_VALUE_B0		GENMASK(7, 0)
-
-/* e7abh */
-#define TUC_VALUE_B1		GENMASK(7, 0)
-
-/* e7ach */
-#define HSYNC_POL		BIT(0)
-#define VSYNC_POL               BIT(1)
-
-/* e7b0h */
-#define SS_ENABLE		BIT(0)
-
-/* e7b1h */
-#define SSC_ENABLE		BIT(4)
-
-#endif /* _MFD_MAX96776_H_ */
diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h
index bfe4d492c6bf..36d354a36077 100644
--- a/include/linux/mtd/spi-nor.h
+++ b/include/linux/mtd/spi-nor.h
@@ -388,6 +388,7 @@ struct spi_nor {
 		struct spi_mem_dirmap_desc *wdesc;
 	} dirmap;
 
+	struct miscdevice *misc_dev;
 	void *priv;
 };
 
diff --git a/include/uapi/linux/spi_nor_misc.h b/include/uapi/linux/spi_nor_misc.h
new file mode 100644
index 000000000000..4b6e604cc0fc
--- /dev/null
+++ b/include/uapi/linux/spi_nor_misc.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
+/*
+ * Copyright (c) 2022 Rockchip Electronics Co., Ltd.
+ */
+
+#ifndef _UAPI__SPI_NOR_MISC_H__
+#define _UAPI__SPI_NOR_MISC_H__
+
+#include <linux/types.h>
+
+#define SPI_NOR_MAX_ID_LEN	6
+
+struct nor_flash_user_info {
+	__u8	id[SPI_NOR_MAX_ID_LEN];
+};
+
+#define NOR_BASE	'P'
+#define NOR_GET_FLASH_INFO		_IOR(NOR_BASE, 0, struct nor_flash_user_info)
+
+#endif
diff --git a/net/rfkill/rfkill-wlan.c b/net/rfkill/rfkill-wlan.c
index b25fe96db09c..89d9787b9ad9 100644
--- a/net/rfkill/rfkill-wlan.c
+++ b/net/rfkill/rfkill-wlan.c
@@ -436,7 +436,7 @@ static int get_wifi_addr_vendor(unsigned char *addr)
 		    addr[5]);
 		ret = rk_vendor_write(WIFI_MAC_ID, addr, 6);
 		if (ret != 0) {
-			LOG("%s: rk_vendor_write failed %d\n"
+			LOG("%s: rk_vendor_write failed %d\n",
 			    __func__, ret);
 			memset(addr, 0, 6);
 			return -1;
diff --git a/sound/soc/codecs/rv1106_codec.c b/sound/soc/codecs/rv1106_codec.c
index d84dbff79fff..3714bdcf0199 100644
--- a/sound/soc/codecs/rv1106_codec.c
+++ b/sound/soc/codecs/rv1106_codec.c
@@ -50,6 +50,8 @@
 #define ADCL				(1 << 0)
 #define ADCR				(1 << 1)
 
+#define NOT_SPECIFIED			(-1)
+
 enum soc_id_e {
 	SOC_RV1103 = 0x1103,
 	SOC_RV1106 = 0x1106,
@@ -73,7 +75,6 @@ struct rv1106_codec_priv {
 	struct regmap *grf;
 	struct clk *pclk_acodec;
 	struct clk *mclk_acodec;
-	struct clk *mclk_cpu;
 	struct gpio_desc *pa_ctl_gpio;
 	struct snd_soc_component *component;
 
@@ -98,6 +99,11 @@ struct rv1106_codec_priv {
 	/* For the high pass filter */
 	unsigned int hpf_cutoff;
 
+	/* Specify init gains after codec startup */
+	unsigned int init_mic_gain;
+	unsigned int init_alc_gain;
+	unsigned int init_lineout_gain;
+
 	bool adc_enable;
 	bool dac_enable;
 	bool micbias_enable;
@@ -1607,11 +1613,29 @@ static void rv1106_pcm_shutdown(struct snd_pcm_substream *substream,
 	regcache_sync(rv1106->regmap);
 }
 
+static int rv1106_set_sysclk(struct snd_soc_dai *dai, int clk_id,
+			     unsigned int freq, int dir)
+{
+	struct snd_soc_component *component = dai->component;
+	struct rv1106_codec_priv *rv1106 = snd_soc_component_get_drvdata(component);
+	int ret;
+
+	if (!freq)
+		return 0;
+
+	ret = clk_set_rate(rv1106->mclk_acodec, freq);
+	if (ret)
+		dev_err(&rv1106->dev, "Failed to set mclk %d\n", ret);
+
+	return ret;
+}
+
 static const struct snd_soc_dai_ops rv1106_dai_ops = {
 	.hw_params = rv1106_hw_params,
 	.set_fmt = rv1106_set_dai_fmt,
 	.mute_stream = rv1106_mute_stream,
 	.shutdown = rv1106_pcm_shutdown,
+	.set_sysclk = rv1106_set_sysclk,
 };
 
 static struct snd_soc_dai_driver rv1106_dai[] = {
@@ -1680,31 +1704,68 @@ out:
 
 static int rv1106_codec_default_gains(struct rv1106_codec_priv *rv1106)
 {
+	int gainl, gainr;
+
+	/**
+	 * MIC Gain
+	 *  0dB (0x01)
+	 * 20dB (0x02)
+	 * 12dB (0x03)
+	 */
+	if (rv1106->init_mic_gain == NOT_SPECIFIED) {
+		gainl = ACODEC_ADC_L_MIC_GAIN_0DB;
+		gainr = ACODEC_ADC_R_MIC_GAIN_0DB;
+	} else {
+		gainl = ((rv1106->init_mic_gain >> 4) & 0x03) << ACODEC_ADC_L_MIC_GAIN_SFT;
+		gainr = ((rv1106->init_mic_gain >> 0) & 0x03) << ACODEC_ADC_R_MIC_GAIN_SFT;
+	}
+
 	/* Prepare ADC gains */
 	/* vendor step 12, set MIC PGA default gains */
 	regmap_update_bits(rv1106->regmap, ACODEC_ADC_ANA_CTL2,
 			   ACODEC_ADC_L_MIC_GAIN_MSK |
 			   ACODEC_ADC_R_MIC_GAIN_MSK,
-			   ACODEC_ADC_L_MIC_GAIN_20DB |
-			   ACODEC_ADC_R_MIC_GAIN_20DB); // TODO: using 20dB
+			   gainl | gainr);
 
+	/**
+	 * ALC Gain (0dB: 0x06)
+	 *  min: -9.0dB (0x00)
+	 *  max: +37.5dB (0x1f)
+	 * step: +1.5dB
+	 */
+	if (rv1106->init_alc_gain == NOT_SPECIFIED) {
+		gainl = ACODEC_ADC_L_ALC_GAIN_0DB;
+		gainr = ACODEC_ADC_R_ALC_GAIN_0DB;
+	} else {
+		gainl = ((rv1106->init_alc_gain >> 4) & 0x1f);
+		gainr = ((rv1106->init_alc_gain >> 0) & 0x1f);
+	}
 	/* vendor step 13, set ALC default gains */
 	regmap_update_bits(rv1106->regmap, ACODEC_ADC_ANA_CTL4,
 			   ACODEC_ADC_L_ALC_GAIN_MSK,
-			   ACODEC_ADC_L_ALC_GAIN_0DB);
+			   gainl);
 	regmap_update_bits(rv1106->regmap, ACODEC_ADC_ANA_CTL5,
 			   ACODEC_ADC_R_ALC_GAIN_MSK,
-			   ACODEC_ADC_R_ALC_GAIN_0DB);
+			   gainr);
 
 	/* Prepare DAC gains */
 	/* Step 19, set LINEOUT default gains */
 	regmap_update_bits(rv1106->regmap, ACODEC_DAC_GAIN_SEL,
 			   ACODEC_DAC_DIG_GAIN_MSK,
-			   ACODEC_DAC_DIG_GAIN(ACODEC_DAC_DIG_0DB));
+			   ACODEC_DAC_DIG_GAIN(ACODEC_DAC_DIG_0DB)); /* The calibrated fixed gain */
+	/**
+	 * Lineout Gain (0dB: 0x1a)
+	 *  min: -39.0dB (0x00)
+	 *  max: +6.0dB (0x1f)
+	 * step: +1.5dB
+	 */
+	if (rv1106->init_lineout_gain == NOT_SPECIFIED)
+		gainl = ACODEC_DAC_LINEOUT_GAIN_0DB;
+	else
+		gainl = rv1106->init_lineout_gain & 0x1f;
 	regmap_update_bits(rv1106->regmap, ACODEC_DAC_ANA_CTL2,
 			   ACODEC_DAC_LINEOUT_GAIN_MSK,
-			   ACODEC_DAC_LINEOUT_GAIN_0DB);
-
+			   gainl);
 	return 0;
 }
 
@@ -2048,6 +2109,15 @@ static int rv1106_platform_probe(struct platform_device *pdev)
 		rv1106->reset = NULL;
 	}
 
+	rv1106->init_mic_gain = NOT_SPECIFIED;
+	of_property_read_u32(np, "init-mic-gain", &rv1106->init_mic_gain);
+
+	rv1106->init_alc_gain = NOT_SPECIFIED;
+	of_property_read_u32(np, "init-alc-gain", &rv1106->init_alc_gain);
+
+	rv1106->init_lineout_gain = NOT_SPECIFIED;
+	of_property_read_u32(np, "init-lineout-gain", &rv1106->init_lineout_gain);
+
 	rv1106->pa_ctl_gpio = devm_gpiod_get_optional(&pdev->dev, "pa-ctl",
 						       GPIOD_OUT_LOW);
 	if (IS_ERR(rv1106->pa_ctl_gpio))
@@ -2075,11 +2145,6 @@ static int rv1106_platform_probe(struct platform_device *pdev)
 		return dev_err_probe(&pdev->dev, PTR_ERR(rv1106->mclk_acodec),
 				    "Can't get acodec mclk_acodec\n");
 
-	rv1106->mclk_cpu = devm_clk_get(&pdev->dev, "mclk_cpu");
-	if (IS_ERR(rv1106->mclk_cpu))
-		return dev_err_probe(&pdev->dev, PTR_ERR(rv1106->mclk_cpu),
-				    "Can't get acodec mclk_cpu\n");
-
 	ret = rv1106_codec_sysfs_init(pdev, rv1106);
 	if (ret < 0)
 		return dev_err_probe(&pdev->dev, ret, "Sysfs init failed\n");
@@ -2106,15 +2171,6 @@ static int rv1106_platform_probe(struct platform_device *pdev)
 		goto failed_1;
 	}
 
-	/**
-	 * In PERICRU_PERICLKSEL_CON08, the mclk_acodec_t/rx_div are div 4
-	 * by default, we need to calibrate once, make the div is 1 and keep
-	 * the rate of mclk_acodec is the same with mclk_i2s.
-	 *
-	 * FIXME: need to handle div dynamically if the DSMAUDIO is enabled.
-	 */
-	clk_set_rate(rv1106->mclk_acodec, clk_get_rate(rv1106->mclk_cpu));
-
 	rv1106_codec_check_micbias(rv1106, np);
 
 	ret = rv1106_codec_adc_i2s_route(rv1106);
diff --git a/sound/soc/rockchip/rockchip_pdm.c b/sound/soc/rockchip/rockchip_pdm.c
index 703219e9c42c..5ec3fe8c1f33 100644
--- a/sound/soc/rockchip/rockchip_pdm.c
+++ b/sound/soc/rockchip/rockchip_pdm.c
@@ -7,6 +7,7 @@
 
 #include <linux/module.h>
 #include <linux/clk.h>
+#include <linux/clk/rockchip.h>
 #include <linux/of.h>
 #include <linux/of_device.h>
 #include <linux/pm_runtime.h>
@@ -29,6 +30,8 @@
 #define PDM_FILTER_DELAY_MS_MIN		(20)
 #define PDM_FILTER_DELAY_MS_MAX		(1000)
 #define PDM_CLK_SHIFT_PPM_MAX		(1000000) /* 1 ppm */
+#define CLK_PPM_MIN		(-1000)
+#define CLK_PPM_MAX		(1000)
 
 enum rk_pdm_version {
 	RK_PDM_RK3229,
@@ -40,6 +43,7 @@ enum rk_pdm_version {
 struct rk_pdm_dev {
 	struct device *dev;
 	struct clk *clk;
+	struct clk *clk_root;
 	struct clk *hclk;
 	struct regmap *regmap;
 	struct snd_dmaengine_dai_dma_data capture_dma_data;
@@ -47,6 +51,10 @@ struct rk_pdm_dev {
 	unsigned int start_delay_ms;
 	unsigned int filter_delay_ms;
 	enum rk_pdm_version version;
+	unsigned int clk_root_rate;
+	unsigned int clk_root_initial_rate;
+	int clk_ppm;
+	bool clk_calibrate;
 };
 
 struct rk_pdm_clkref {
@@ -103,6 +111,11 @@ static unsigned int get_pdm_clk(struct rk_pdm_dev *pdm, unsigned int sr,
 		div = sr / clkref[i].sr;
 		if ((div & (div - 1)) == 0) {
 			*clk_out = clkref[i].clk_out;
+			if (pdm->clk_calibrate) {
+				clk = clkref[i].clk;
+				*clk_src = clk;
+				break;
+			}
 			rate = clk_round_rate(pdm->clk, clkref[i].clk);
 			delta = clkref[i].clk / PDM_CLK_SHIFT_PPM_MAX;
 			if (rate < clkref[i].clk - delta ||
@@ -216,13 +229,46 @@ static void rockchip_pdm_rxctrl(struct rk_pdm_dev *pdm, int on)
 	}
 }
 
+static int rockchip_pdm_clk_set_rate(struct rk_pdm_dev *pdm,
+				     struct clk *clk, unsigned long rate,
+				     int ppm)
+{
+	unsigned long rate_target;
+	int delta, ret;
+
+	if (ppm == pdm->clk_ppm)
+		return 0;
+
+	ret = rockchip_pll_clk_compensation(clk, ppm);
+	if (ret != -ENOSYS)
+		goto out;
+
+	delta = (ppm < 0) ? -1 : 1;
+	delta *= (int)div64_u64((uint64_t)rate * (uint64_t)abs(ppm) + 500000, 1000000);
+
+	rate_target = rate + delta;
+
+	if (!rate_target)
+		return -EINVAL;
+
+	ret = clk_set_rate(clk, rate_target);
+	if (ret)
+		return ret;
+out:
+	if (!ret)
+		pdm->clk_ppm = ppm;
+
+	return ret;
+}
+
 static int rockchip_pdm_set_samplerate(struct rk_pdm_dev *pdm, unsigned int samplerate)
 {
 
-	unsigned int val = 0;
-	unsigned int clk_rate, clk_div;
+	unsigned int val = 0, div = 0;
+	unsigned int clk_rate, clk_div, rate, delta;
 	unsigned int clk_src = 0, clk_out = 0, signoff = PDM_SIGNOFF_CLK_100M;
 	unsigned long m, n;
+	uint64_t ppm;
 	bool change;
 	int ret;
 
@@ -232,9 +278,37 @@ static int rockchip_pdm_set_samplerate(struct rk_pdm_dev *pdm, unsigned int samp
 	if (!clk_rate)
 		return -EINVAL;
 
+	if (pdm->clk_calibrate) {
+		ret = clk_set_parent(pdm->clk, pdm->clk_root);
+		if (ret)
+			return ret;
+
+		ret = rockchip_pdm_clk_set_rate(pdm, pdm->clk_root,
+						pdm->clk_root_rate, 0);
+		if (ret)
+			return ret;
+
+		rate = pdm->clk_root_rate;
+		delta = abs(rate % clk_src - clk_src);
+		ppm = div64_u64((uint64_t)delta * 1000000, (uint64_t)rate);
+
+		if (ppm) {
+			div = DIV_ROUND_CLOSEST(pdm->clk_root_initial_rate, clk_src);
+			if (!div)
+				return -EINVAL;
+
+			rate = clk_src * round_up(div, 2);
+			ret = clk_set_rate(pdm->clk_root, rate);
+			if (ret)
+				return ret;
+
+			pdm->clk_root_rate = clk_get_rate(pdm->clk_root);
+		}
+	}
+
 	ret = clk_set_rate(pdm->clk, clk_src);
 	if (ret)
-		return -EINVAL;
+		return ret;
 
 	if (pdm->version == RK_PDM_RK3308 ||
 	    pdm->version == RK_PDM_RK3588 ||
@@ -496,6 +570,55 @@ static const struct snd_kcontrol_new rockchip_pdm_controls[] = {
 	},
 };
 
+static int rockchip_pdm_clk_compensation_info(struct snd_kcontrol *kcontrol,
+					      struct snd_ctl_elem_info *uinfo)
+{
+	uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
+	uinfo->count = 1;
+	uinfo->value.integer.min = CLK_PPM_MIN;
+	uinfo->value.integer.max = CLK_PPM_MAX;
+	uinfo->value.integer.step = 1;
+
+	return 0;
+}
+
+
+static int rockchip_pdm_clk_compensation_get(struct snd_kcontrol *kcontrol,
+					     struct snd_ctl_elem_value *ucontrol)
+
+{
+	struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol);
+	struct rk_pdm_dev *pdm = snd_soc_dai_get_drvdata(dai);
+
+	ucontrol->value.integer.value[0] = pdm->clk_ppm;
+
+	return 0;
+}
+
+static int rockchip_pdm_clk_compensation_put(struct snd_kcontrol *kcontrol,
+					     struct snd_ctl_elem_value *ucontrol)
+{
+	struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol);
+	struct rk_pdm_dev *pdm = snd_soc_dai_get_drvdata(dai);
+
+	int ppm = ucontrol->value.integer.value[0];
+
+	if ((ucontrol->value.integer.value[0] < CLK_PPM_MIN) ||
+	    (ucontrol->value.integer.value[0] > CLK_PPM_MAX))
+		return -EINVAL;
+
+	return rockchip_pdm_clk_set_rate(pdm, pdm->clk_root, pdm->clk_root_rate, ppm);
+}
+
+static struct snd_kcontrol_new rockchip_pdm_compensation_control = {
+	.iface = SNDRV_CTL_ELEM_IFACE_PCM,
+	.name = "PDM PCM Clk Compensation In PPM",
+	.info = rockchip_pdm_clk_compensation_info,
+	.get = rockchip_pdm_clk_compensation_get,
+	.put = rockchip_pdm_clk_compensation_put,
+
+};
+
 static int rockchip_pdm_dai_probe(struct snd_soc_dai *dai)
 {
 	struct rk_pdm_dev *pdm = to_info(dai);
@@ -503,6 +626,8 @@ static int rockchip_pdm_dai_probe(struct snd_soc_dai *dai)
 	dai->capture_dma_data = &pdm->capture_dma_data;
 	snd_soc_add_dai_controls(dai, rockchip_pdm_controls,
 				 ARRAY_SIZE(rockchip_pdm_controls));
+	if (pdm->clk_calibrate)
+		snd_soc_add_dai_controls(dai, &rockchip_pdm_compensation_control, 1);
 	return 0;
 }
 
@@ -798,6 +923,17 @@ static int rockchip_pdm_probe(struct platform_device *pdev)
 	pdm->start_delay_ms = PDM_START_DELAY_MS_DEFAULT;
 	pdm->filter_delay_ms = PDM_FILTER_DELAY_MS_MIN;
 
+	pdm->clk_calibrate =
+		of_property_read_bool(node, "rockchip,mclk-calibrate");
+	if (pdm->clk_calibrate) {
+		pdm->clk_root = devm_clk_get(&pdev->dev, "pdm_clk_root");
+		if (IS_ERR(pdm->clk_root))
+			return PTR_ERR(pdm->clk_root);
+
+		pdm->clk_root_initial_rate = clk_get_rate(pdm->clk_root);
+		pdm->clk_root_rate = pdm->clk_root_initial_rate;
+	}
+
 	pdm->clk = devm_clk_get(&pdev->dev, "pdm_clk");
 	if (IS_ERR(pdm->clk))
 		return PTR_ERR(pdm->clk);