diff --git a/drivers/soc/rockchip/rockchip_pm_debug.c b/drivers/soc/rockchip/rockchip_pm_debug.c index 9da7d91c4960..58933c26282e 100644 --- a/drivers/soc/rockchip/rockchip_pm_debug.c +++ b/drivers/soc/rockchip/rockchip_pm_debug.c @@ -11,7 +11,13 @@ #include #include -#define RK_IOC_CFG(NAME, REG, LEN, ID, TABLE) \ +#define RK_SUB_REG_RGN(OFF, LEN) \ + { \ + .offset = OFF, \ + .len = LEN, \ + } + +#define RK_REG_RGN(NAME, REG, LEN, ID, TABLE) \ { \ .name = NAME, \ .reg_base = REG, \ @@ -20,50 +26,53 @@ .table = TABLE, \ } -struct rk_gpio_table { +#define RK_REG_CFG_SIMPLE(NAME, REG, LEN) \ + RK_REG_RGN(NAME, REG, LEN, 0, NULL) + +struct rk_sub_rgn { u32 offset; u32 len; }; -struct rk_gpio_chip { +struct rk_reg_rgn { char *name; u32 reg_base; u32 len; int bank_id; - const struct rk_gpio_table *table; + const struct rk_sub_rgn *table; }; -static const struct rk_gpio_table rk3506_gpio_table[] = { - { .offset = 0, .len = 0x20,}, - { .offset = 0x100, .len = 0x40,}, - { .offset = 0x200, .len = 0x10,}, - { .offset = 0x300, .len = 0x10,}, - { .offset = 0x400, .len = 0x10,}, - { .offset = 0x500, .len = 0x10,}, - { .offset = 0x600, .len = 0x10,}, +static const struct rk_sub_rgn rk3506_gpio_table[] = { + RK_SUB_REG_RGN(0, 0x20), + RK_SUB_REG_RGN(0x100, 0x40), + RK_SUB_REG_RGN(0x200, 0x10), + RK_SUB_REG_RGN(0x300, 0x10), + RK_SUB_REG_RGN(0x400, 0x10), + RK_SUB_REG_RGN(0x500, 0x10), + RK_SUB_REG_RGN(0x600, 0x10), { }, }; -static const struct rk_gpio_chip rk3506_table[] = { - RK_IOC_CFG("gpio0_ioc", 0xff950000, 0x700, 0, rk3506_gpio_table), - RK_IOC_CFG("gpio1_ioc", 0xff660000, 0x700, 1, rk3506_gpio_table), - RK_IOC_CFG("gpio2_ioc", 0xff4d8000, 0x700, 2, rk3506_gpio_table), - RK_IOC_CFG("gpio3_ioc", 0xff4d8000, 0x700, 3, rk3506_gpio_table), - { .name = "gpio4_ioc", .reg_base = 0xff4d8840, .len = 0x10}, - { .name = "rm_io", .reg_base = 0xff910080, .len = 0x80}, - { .name = "gpio0", .reg_base = 0xff940000, .len = 0x80}, - { .name = "gpio1", .reg_base = 0xff870000, .len = 0x80}, - { .name = "gpio2", .reg_base = 0xff1c0000, .len = 0x80}, - { .name = "gpio3", .reg_base = 0xff1d0000, .len = 0x80}, - { .name = "gpio4", .reg_base = 0xff1e0000, .len = 0x80}, +static const struct rk_reg_rgn rk3506_table[] = { + RK_REG_RGN("gpio0_ioc", 0xff950000, 0x700, 0, rk3506_gpio_table), + RK_REG_RGN("gpio1_ioc", 0xff660000, 0x700, 1, rk3506_gpio_table), + RK_REG_RGN("gpio2_ioc", 0xff4d8000, 0x700, 2, rk3506_gpio_table), + RK_REG_RGN("gpio3_ioc", 0xff4d8000, 0x700, 3, rk3506_gpio_table), + RK_REG_CFG_SIMPLE("gpio4_ioc", 0xff4d8840, 0x10), + RK_REG_CFG_SIMPLE("rm_io", 0xff910080, 0x80), + RK_REG_CFG_SIMPLE("gpio0", 0xff940000, 0x80), + RK_REG_CFG_SIMPLE("gpio1", 0xff870000, 0x80), + RK_REG_CFG_SIMPLE("gpio2", 0xff1c0000, 0x80), + RK_REG_CFG_SIMPLE("gpio3", 0xff1d0000, 0x80), + RK_REG_CFG_SIMPLE("gpio4", 0xff1e0000, 0x80), { }, }; -static const struct rk_gpio_chip *chip_table; +static const struct rk_reg_rgn *chip_table; -static void rk_gpio_dump(const struct rk_gpio_chip *chip) +static void rk_regs_dump(const struct rk_reg_rgn *chip) { - const struct rk_gpio_table *table = chip->table; + const struct rk_sub_rgn *table = chip->table; void __iomem *reg = ioremap(chip->reg_base, chip->len); char prefix[16]; int cnt, end; @@ -98,7 +107,7 @@ static void rk_gpio_dump(const struct rk_gpio_chip *chip) static int rockchip_pm_syscore_suspend(void) { for (; chip_table && chip_table->name; chip_table++) - rk_gpio_dump(chip_table); + rk_regs_dump(chip_table); return 0; } @@ -107,14 +116,31 @@ static struct syscore_ops rockchip_pm_syscore_ops = { .suspend = rockchip_pm_syscore_suspend, }; +static const struct chip_data_t { + const char *compat; + const struct rk_reg_rgn *table; +} compat_list[] = { +#ifdef CONFIG_CPU_RK3506 + { .compat = "rockchip,rk3502", .table = rk3506_table }, + { .compat = "rockchip,rk3506", .table = rk3506_table }, +#endif +}; + static int __init rockchip_pm_syscore_init(void) { - if (of_machine_is_compatible("rockchip,rk3502") || - of_machine_is_compatible("rockchip,rk3506")) - chip_table = rk3506_table; + int i; - if (chip_table) - register_syscore_ops(&rockchip_pm_syscore_ops); + if (ARRAY_SIZE(compat_list) > 0) { + for (i = 0; i < ARRAY_SIZE(compat_list); i++) { + if (of_machine_is_compatible(compat_list[i].compat)) { + chip_table = compat_list[i].table; + break; + } + } + + if (chip_table) + register_syscore_ops(&rockchip_pm_syscore_ops); + } return 0; }