From 7052d7de3c8cdcbda581a5cfb6d8548c50bc3c0f Mon Sep 17 00:00:00 2001 From: Sugar Zhang Date: Fri, 27 Aug 2021 17:22:27 +0800 Subject: [PATCH] arm64: dts: rockchip: rk3588s: Add i2s/pdm/spdifrx/spdiftx nodes Signed-off-by: Sugar Zhang Change-Id: Ia967e33488241e509283bb4732d4651dbc069515 --- arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 342 ++++++++++++++++++++++ 1 file changed, 342 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi index f4c246868250..7ea6a1ce3695 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi @@ -582,6 +582,194 @@ status = "disabled"; }; + spdif_tx2: spdif-tx@fddb0000 { + compatible = "rockchip,rk3588-spdif", "rockchip,rk3568-spdif"; + reg = <0x0 0xfddb0000 0x0 0x1000>; + interrupts = ; + dmas = <&dmac1 6>; + dma-names = "tx"; + clock-names = "mclk", "hclk"; + clocks = <&cru MCLK_SPDIF2_DP0>, <&cru HCLK_SPDIF2_DP0>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + spdif_tx5: spdif-tx@fddb8000 { + compatible = "rockchip,rk3588-spdif", "rockchip,rk3568-spdif"; + reg = <0x0 0xfddb8000 0x0 0x1000>; + interrupts = ; + dmas = <&dmac1 22>; + dma-names = "tx"; + clock-names = "mclk", "hclk"; + clocks = <&cru MCLK_SPDIF5_DP1>, <&cru HCLK_SPDIF5_DP1>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + i2s4_8ch: i2s@fddc0000 { + compatible = "rockchip,rk3588-i2s-tdm"; + reg = <0x0 0xfddc0000 0x0 0x1000>; + interrupts = ; + clocks = <&cru MCLK_I2S4_8CH_TX>, <&cru HCLK_I2S4_8CH>; + clock-names = "mclk_tx", "hclk"; + dmas = <&dmac2 0>; + dma-names = "tx"; + resets = <&cru SRST_M_I2S4_8CH_TX>; + reset-names = "tx-m"; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + i2s8_8ch: i2s@fddc8000 { + compatible = "rockchip,rk3588-i2s-tdm"; + reg = <0x0 0xfddc8000 0x0 0x1000>; + interrupts = ; + clocks = <&cru MCLK_I2S8_8CH_TX>, <&cru HCLK_I2S8_8CH>; + clock-names = "mclk_tx", "hclk"; + dmas = <&dmac2 22>; + dma-names = "tx"; + resets = <&cru SRST_M_I2S8_8CH_TX>; + reset-names = "tx-m"; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + spdif_tx3: spdif-tx@fdde0000 { + compatible = "rockchip,rk3588-spdif", "rockchip,rk3568-spdif"; + reg = <0x0 0xfdde0000 0x0 0x1000>; + interrupts = ; + dmas = <&dmac1 7>; + dma-names = "tx"; + clock-names = "mclk", "hclk"; + clocks = <&cru MCLK_SPDIF3>, <&cru HCLK_SPDIF3>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + spdif_tx4: spdif-tx@fdde8000 { + compatible = "rockchip,rk3588-spdif", "rockchip,rk3568-spdif"; + reg = <0x0 0xfdde8000 0x0 0x1000>; + interrupts = ; + dmas = <&dmac1 8>; + dma-names = "tx"; + clock-names = "mclk", "hclk"; + clocks = <&cru MCLK_SPDIF4>, <&cru HCLK_SPDIF4>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + i2s5_8ch: i2s@fddf0000 { + compatible = "rockchip,rk3588-i2s-tdm"; + reg = <0x0 0xfddf0000 0x0 0x1000>; + interrupts = ; + clocks = <&cru MCLK_I2S5_8CH_TX>, <&cru HCLK_I2S5_8CH>; + clock-names = "mclk_tx", "hclk"; + dmas = <&dmac2 2>; + dma-names = "tx"; + resets = <&cru SRST_M_I2S5_8CH_TX>; + reset-names = "tx-m"; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + i2s6_8ch: i2s@fddf4000 { + compatible = "rockchip,rk3588-i2s-tdm"; + reg = <0x0 0xfddf4000 0x0 0x1000>; + interrupts = ; + clocks = <&cru MCLK_I2S6_8CH_TX>, <&cru HCLK_I2S6_8CH>; + clock-names = "mclk_tx", "hclk"; + dmas = <&dmac2 4>; + dma-names = "tx"; + resets = <&cru SRST_M_I2S6_8CH_TX>; + reset-names = "tx-m"; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + i2s7_8ch: i2s@fddf8000 { + compatible = "rockchip,rk3588-i2s-tdm"; + reg = <0x0 0xfddf8000 0x0 0x1000>; + interrupts = ; + clocks = <&cru MCLK_I2S7_8CH_RX>, <&cru HCLK_I2S7_8CH>; + clock-names = "mclk_rx", "hclk"; + dmas = <&dmac2 21>; + dma-names = "rx"; + resets = <&cru SRST_M_I2S7_8CH_RX>; + reset-names = "rx-m"; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + i2s9_8ch: i2s@fddfc000 { + compatible = "rockchip,rk3588-i2s-tdm"; + reg = <0x0 0xfddfc000 0x0 0x1000>; + interrupts = ; + clocks = <&cru MCLK_I2S9_8CH_RX>, <&cru HCLK_I2S9_8CH>; + clock-names = "mclk_rx", "hclk"; + dmas = <&dmac2 23>; + dma-names = "rx"; + resets = <&cru SRST_M_I2S9_8CH_RX>; + reset-names = "rx-m"; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + i2s10_8ch: i2s@fde00000 { + compatible = "rockchip,rk3588-i2s-tdm"; + reg = <0x0 0xfde00000 0x0 0x1000>; + interrupts = ; + clocks = <&cru MCLK_I2S10_8CH_RX>, <&cru HCLK_I2S10_8CH>; + clock-names = "mclk_rx", "hclk"; + dmas = <&dmac2 24>; + dma-names = "rx"; + resets = <&cru SRST_M_I2S10_8CH_RX>; + reset-names = "rx-m"; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + spdif_rx0: spdif-rx@fde08000 { + compatible = "rockchip,rk3588-spdifrx", "rockchip,rk3308-spdifrx"; + reg = <0x0 0xfde08000 0x0 0x1000>; + interrupts = ; + clocks = <&cru MCLK_SPDIFRX0>, <&cru HCLK_SPDIFRX0>; + clock-names = "mclk", "hclk"; + dmas = <&dmac0 21>; + dma-names = "rx"; + resets = <&cru SRST_M_SPDIFRX0>; + reset-names = "spdifrx-m"; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + spdif_rx1: spdif-rx@fde10000 { + compatible = "rockchip,rk3588-spdifrx", "rockchip,rk3308-spdifrx"; + reg = <0x0 0xfde10000 0x0 0x1000>; + interrupts = ; + clocks = <&cru MCLK_SPDIFRX1>, <&cru HCLK_SPDIFRX1>; + clock-names = "mclk", "hclk"; + dmas = <&dmac0 22>; + dma-names = "rx"; + resets = <&cru SRST_M_SPDIFRX1>; + reset-names = "spdifrx-m"; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + spdif_rx2: spdif-rx@fde18000 { + compatible = "rockchip,rk3588-spdifrx", "rockchip,rk3308-spdifrx"; + reg = <0x0 0xfde18000 0x0 0x1000>; + interrupts = ; + clocks = <&cru MCLK_SPDIFRX2>, <&cru HCLK_SPDIFRX2>; + clock-names = "mclk", "hclk"; + dmas = <&dmac0 23>; + dma-names = "rx"; + resets = <&cru SRST_M_SPDIFRX2>; + reset-names = "spdifrx-m"; + #sound-dai-cells = <0>; + status = "disabled"; + }; + sdmmc: mmc@fe2c0000 { compatible = "rockchip,rk3588-dw-mshc", "rockchip,rk3288-dw-mshc"; reg = <0x0 0xfe2c0000 0x0 0x4000>; @@ -622,6 +810,160 @@ status = "disabled"; }; + i2s0_8ch: i2s@fe470000 { + compatible = "rockchip,rk3588-i2s-tdm"; + reg = <0x0 0xfe470000 0x0 0x1000>; + interrupts = ; + clocks = <&cru MCLK_I2S0_8CH_TX>, <&cru MCLK_I2S0_8CH_RX>, <&cru HCLK_I2S0_8CH>; + clock-names = "mclk_tx", "mclk_rx", "hclk"; + dmas = <&dmac0 0>, <&dmac0 1>; + dma-names = "tx", "rx"; + resets = <&cru SRST_M_I2S0_8CH_TX>, <&cru SRST_M_I2S0_8CH_RX>; + reset-names = "tx-m", "rx-m"; + pinctrl-names = "default"; + pinctrl-0 = <&i2s0_lrck_rx + &i2s0_lrck_tx + &i2s0_sclk_rx + &i2s0_sclk_tx + &i2s0_sdi0 + &i2s0_sdi1 + &i2s0_sdi2 + &i2s0_sdi3 + &i2s0_sdo0 + &i2s0_sdo1 + &i2s0_sdo2 + &i2s0_sdo3>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + i2s1_8ch: i2s@fe480000 { + compatible = "rockchip,rk3588-i2s-tdm"; + reg = <0x0 0xfe480000 0x0 0x1000>; + interrupts = ; + clocks = <&cru MCLK_I2S1_8CH_TX>, <&cru MCLK_I2S1_8CH_RX>, <&cru HCLK_I2S1_8CH>; + clock-names = "mclk_tx", "mclk_rx", "hclk"; + dmas = <&dmac0 2>, <&dmac0 3>; + dma-names = "tx", "rx"; + resets = <&cru SRST_M_I2S1_8CH_TX>, <&cru SRST_M_I2S1_8CH_RX>; + reset-names = "tx-m", "rx-m"; + pinctrl-names = "default"; + pinctrl-0 = <&i2s1m0_lrck_rx + &i2s1m0_lrck_tx + &i2s1m0_sclk_rx + &i2s1m0_sclk_tx + &i2s1m0_sdi0 + &i2s1m0_sdi1 + &i2s1m0_sdi2 + &i2s1m0_sdi3 + &i2s1m0_sdo0 + &i2s1m0_sdo1 + &i2s1m0_sdo2 + &i2s1m0_sdo3>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + i2s2_2ch: i2s@fe490000 { + compatible = "rockchip,rk3588-i2s", "rockchip,rk3066-i2s"; + reg = <0x0 0xfe490000 0x0 0x1000>; + interrupts = ; + clocks = <&cru MCLK_I2S2_2CH>, <&cru HCLK_I2S2_2CH>; + clock-names = "i2s_clk", "i2s_hclk"; + dmas = <&dmac1 0>, <&dmac1 1>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&i2s2m0_lrck_rx + &i2s2m0_lrck_tx + &i2s2m0_sclk_rx + &i2s2m0_sclk_tx + &i2s2m0_sdi + &i2s2m0_sdo>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + i2s3_2ch: i2s@fe4a0000 { + compatible = "rockchip,rk3588-i2s", "rockchip,rk3066-i2s"; + reg = <0x0 0xfe4a0000 0x0 0x1000>; + interrupts = ; + clocks = <&cru MCLK_I2S3_2CH>, <&cru HCLK_I2S3_2CH>; + clock-names = "i2s_clk", "i2s_hclk"; + dmas = <&dmac1 2>, <&dmac1 3>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&i2s3_lrck + &i2s3_sclk + &i2s3_sdi + &i2s3_sdo>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + pdm0: pdm@fe4b0000 { + compatible = "rockchip,rk3588-pdm"; + reg = <0x0 0xfe4b0000 0x0 0x1000>; + clocks = <&cru MCLK_PDM0>, <&cru HCLK_PDM0>; + clock-names = "pdm_clk", "pdm_hclk"; + dmas = <&dmac0 4>; + dma-names = "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&pdm0m0_clk + &pdm0m0_clk1 + &pdm0m0_sdi0 + &pdm0m0_sdi1 + &pdm0m0_sdi2 + &pdm0m0_sdi3>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + pdm1: pdm@fe4c0000 { + compatible = "rockchip,rk3588-pdm"; + reg = <0x0 0xfe4c0000 0x0 0x1000>; + clocks = <&cru MCLK_PDM1>, <&cru HCLK_PDM1>; + clock-names = "pdm_clk", "pdm_hclk"; + dmas = <&dmac1 4>; + dma-names = "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&pdm1m0_clk + &pdm1m0_clk1 + &pdm1m0_sdi0 + &pdm1m0_sdi1 + &pdm1m0_sdi2 + &pdm1m0_sdi3>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + spdif_tx0: spdif-tx@fe4e0000 { + compatible = "rockchip,rk3588-spdif", "rockchip,rk3568-spdif"; + reg = <0x0 0xfe4e0000 0x0 0x1000>; + interrupts = ; + dmas = <&dmac0 5>; + dma-names = "tx"; + clock-names = "mclk", "hclk"; + clocks = <&cru MCLK_SPDIF0>, <&cru HCLK_SPDIF0>; + pinctrl-names = "default"; + pinctrl-0 = <&spdif0m0_tx>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + spdif_tx1: spdif-tx@fe4f0000 { + compatible = "rockchip,rk3588-spdif", "rockchip,rk3568-spdif"; + reg = <0x0 0xfe4f0000 0x0 0x1000>; + interrupts = ; + dmas = <&dmac1 5>; + dma-names = "tx"; + clock-names = "mclk", "hclk"; + clocks = <&cru MCLK_SPDIF1>, <&cru HCLK_SPDIF1>; + pinctrl-names = "default"; + pinctrl-0 = <&spdif1m0_tx>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + gic: interrupt-controller@fe600000 { compatible = "arm,gic-v3"; #interrupt-cells = <3>;