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clk: meson-txlx: add clock tree driver
PD#154260: clk: meson-txlx: add clock tree driver Change clkc driver init order The loading order of vpu driver is postcore_initcall, but clock order is device_initcall.clock order should be higher,change macro CLK_OF_DECLARE instead Optimizing mux/div/gate descriptions. Change-Id: I20cd8111ac6bd60f350cdddc224bad48c13fcfb1 Signed-off-by: Jian Hu <jian.hu@amlogic.com>
This commit is contained in:
Jian Hu
@@ -10,6 +10,8 @@ Required Properties:
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"amlogic,gxl-clkc" - for gxl ee clock
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"amlogic,axg-clkc" - for axg ee clock
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"amlogic,axg-aoclkc" - for axg ao clock
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"amlogic,txlx-clkc" - for txlx ee clock
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"amlogic,txlx-aoclkc" - for txlx ao clock
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- reg: physical base address of the clock controller and length of memory
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mapped region.
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@@ -14169,3 +14169,9 @@ F: scripts/amlogic/mkimage_64.sh
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AMLOGIC ledring driver
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M: Renjun Xu <renjun.xu@amlogic.com>
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F: drivers/amlogic/ledring/ledring.c
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AMLOGIC TXLX CLK
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M: Jian Hu <jian.hu@amlogic.com>
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F: drivers/amlogic/clk/*
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F: drivers/amlogic/clk/txlx/*
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@@ -5,10 +5,14 @@
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obj-$(CONFIG_AMLOGIC_COMMON_CLK_SCPI) += clk-scpi.o
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obj-$(CONFIG_AMLOGIC_RESET) += rstc.o
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obj-$(CONFIG_AMLOGIC_CLK) += clk-pll.o clk-mux.o clk_measure.o
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obj-$(CONFIG_AMLOGIC_CLK) += clk-pll.o
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obj-$(CONFIG_AMLOGIC_CLK) += clk-mux.o
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obj-$(CONFIG_AMLOGIC_CLK) += clk_measure.o
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obj-$(CONFIG_AMLOGIC_CLK) += clk-meson-register.o
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obj-$(CONFIG_AMLOGIC_GX_CLK) += clk-cpu.o clk-mpll.o clk_test.o
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obj-$(CONFIG_AMLOGIC_GX_CLK) += gxl/
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obj-$(CONFIG_AMLOGIC_GX_CLK) += axg/
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obj-$(CONFIG_AMLOGIC_GX_CLK) += txlx/
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obj-$(CONFIG_AMLOGIC_M8B_CLK) += m8b/
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obj-$(CONFIG_AMLOGIC_M8B_CLK) += m8b/
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51
drivers/amlogic/clk/clk-meson-register.c
Normal file
51
drivers/amlogic/clk/clk-meson-register.c
Normal file
@@ -0,0 +1,51 @@
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/*
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* drivers/amlogic/clk/clk-meson-register.c
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*
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* Copyright (C) 2017 Amlogic, Inc. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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*/
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#include <linux/clk-provider.h>
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#include "clkc.h"
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/*register composite clock*/
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void meson_clk_register_composite(struct clk **soc_clks,
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struct meson_composite *composite,
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unsigned int length)
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{
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int i = 0;
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for (i = 0; i < length; i++) {
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soc_clks[composite[i].composite_id] = clk_register_composite(
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NULL, composite[i].name, composite[i].parent_names,
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composite[i].num_parents,
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composite[i].mux_hw, &clk_mux_ops,
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composite[i].rate_hw, &clk_divider_ops,
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composite[i].gate_hw, &clk_gate_ops, composite[i].flags);
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if (IS_ERR(soc_clks[composite[i].composite_id]))
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pr_err("%s: %s error\n", __func__, composite[i].name);
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}
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}
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/*register single clock*/
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void meson_hw_clk_register(struct clk **soc_clks,
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struct meson_hw *m,
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unsigned int length)
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{
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int i = 0;
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for (i = 0; i < length; i++) {
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soc_clks[m[i].hw_id] = clk_register(NULL, m[i].hw);
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WARN_ON(soc_clks[m[i].hw_id]);
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}
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}
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@@ -62,6 +62,11 @@
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#define GXL_GP0_CNTL4 0xc000004d
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#define GXL_GP0_CNTL5 0x00078000
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/* TXLX */
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/* CNTL2-5 the same to GXL*/
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#define TXLL_GP0_CNTL5 0x00058000
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#define to_meson_clk_pll(_hw) container_of(_hw, struct meson_clk_pll, hw)
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static unsigned long meson_clk_pll_recalc_rate(struct clk_hw *hw,
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@@ -180,18 +185,28 @@ static int meson_clk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
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writel(GXBB_GP0_CNTL2, cntlbase + (u64)1*4);
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writel(GXBB_GP0_CNTL3, cntlbase + (u64)2*4);
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writel(GXBB_GP0_CNTL4, cntlbase + (u64)3*4);
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}
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if (get_cpu_type() >= MESON_CPU_MAJOR_ID_GXL) {
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} else if (get_cpu_type() >= MESON_CPU_MAJOR_ID_GXL) {
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writel(GXL_GP0_CNTL1, cntlbase + (u64)6*4);
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writel(GXL_GP0_CNTL2, cntlbase + (u64)1*4);
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writel(GXL_GP0_CNTL3, cntlbase + (u64)2*4);
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writel(GXL_GP0_CNTL4, cntlbase + (u64)3*4);
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writel(GXL_GP0_CNTL5, cntlbase + (u64)4*4);
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reg = readl(pll->base + p->reg_off);
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writel(((reg | (MESON_PLL_ENABLE)) &
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(~MESON_PLL_RESET)), pll->base + p->reg_off);
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} else if (get_cpu_type() >= MESON_CPU_MAJOR_ID_TXLX) {
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writel(GXL_GP0_CNTL1, cntlbase + (u64)6*4);
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writel(GXL_GP0_CNTL2, cntlbase + (u64)1*4);
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writel(GXL_GP0_CNTL3, cntlbase + (u64)2*4);
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writel(GXL_GP0_CNTL4, cntlbase + (u64)3*4);
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writel(TXLL_GP0_CNTL5, cntlbase + (u64)4*4);
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reg = readl(pll->base + p->reg_off);
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writel(((reg | (MESON_PLL_ENABLE)) &
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(~MESON_PLL_RESET)), pll->base + p->reg_off);
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}
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}
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reg = readl(pll->base + p->reg_off);
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@@ -564,6 +564,136 @@ int axg_clk_measure(struct seq_file *s, void *what, unsigned int index)
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return 0;
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}
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int txlx_clk_measure(struct seq_file *s, void *what, unsigned int index)
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{
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static const char * const clk_table[] = {
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[109] = "cts_alocker_in_clk",
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[108] = "cts_alocker_out_clk",
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[107] = "am_ring_osc_clk_out_ee[11]",
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[106] = "am_ring_osc_clk_out_ee[10]",
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[105] = "am_ring_osc_clk_out_ee[9]",
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[104] = "am_ring_osc_clk_out_ee[8]",
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[103] = "am_ring_osc_clk_out_ee[7]",
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[102] = "am_ring_osc_clk_out_ee[6]",
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[101] = "am_ring_osc_clk_out_ee[5]",
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[100] = "am_ring_osc_clk_out_ee[4]",
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[99] = "am_ring_osc_clk_out_ee[3]",
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[98] = "cts_hdmirx_aud_pll_clk",
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[97] = "cts_vpu_clkb_tmp ",
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[96] = "cts_vpu_clkb ",
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[95] = "ethphy_test_clk_out",
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[94] = "atv_dmd_mono_clk_32",
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[93] = "cts_audin_lrclk",
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[92] = "cts_audin_sclk ",
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[91] = "cts_audin_mclk ",
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[90] = "cts_hdmitx_sys_clk ",
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[89] = "HDMI_CLK_TODIG ",
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[88] = "hdmirx_vid_clk ",
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[87] = "lvds_fifo_clk ",
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[86] = "hdmirx_phy_dtb[3] ",
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[85] = "hdmirx_phy_dtb[2] ",
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[84] = "hdmirx_phy_dtb[1] ",
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[83] = "hdmirx_phy_dtb[0] ",
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[82] = "Cts_ge2d_clk ",
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[81] = "Cts_vapbclk ",
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[80] = "Rng_ring_osc_clk[3]",
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[79] = "Rng_ring_osc_clk[2]",
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[78] = "Rng_ring_osc_clk[1]",
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[77] = "Rng_ring_osc_clk[0]",
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[76] = "cts_aoclk_int ",
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[75] = "cts_aoclkx2_int ",
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[74] = "cts_atv_dmd_vdac_clk",
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[73] = "cts_pwm_C_clk ",
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[72] = "cts_pwm_D_clk ",
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[71] = "cts_pwm_E_clk ",
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[70] = "cts_pwm_F_clk ",
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[69] = "Cts_hdcp22_skp ",
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[68] = "Cts_hdcp22_esm ",
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[67] = "tvfe_sample_clk ",
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[66] = "cts_vid_lock_clk ",
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[65] = "cts_atv_dmd_sys_clk",
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[64] = "Cts_hdmirx_cfg_clk ",
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[63] = "adc_dpll_intclk ",
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[62] = "cts_hevc_clk ",
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[61] = "gpio_clk_msr ",
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[60] = "alt_32k_clk ",
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[59] = "cts_hcodec_clk ",
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[58] = "Hdmirx_aud_clk ",
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[57] = "Cts_hdmirx_audmeas ",
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[56] = "Cts_hdmirx_modet_clk",
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[55] = "vid_pll_div_clk_out ",
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[54] = "Cts_hdmirx_arc_ref_clk",
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[53] = "sd_emmc_clk_A ",
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[52] = "sd_emmc_clk_B ",
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[51] = "sd_emmc_clk_C ",
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[50] = "mp3_clk_out ",
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[49] = "mp2_clk_out ",
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[48] = "mp1_clk_out ",
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[47] = "ddr_dpll_pt_clk ",
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[46] = "cts_vpu_clk ",
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[45] = "cts_pwm_A_clk ",
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[44] = "cts_pwm_B_clk ",
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[43] = "fclk_div5 ",
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[42] = "mp0_clk_out ",
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[41] = "eth_rx_clk_rmii ",
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[40] = "cts_pcm_mclk ",
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[39] = "cts_pcm_sclk ",
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[38] = "Cts_vdin_meas_clk ",
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[37] = "cts_clk_i958 ",
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[36] = "cts_hdmi_tx_pixel_clk",
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[35] = "cts_mali_clk ",
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[34] = "adc_dpll_clk_b3 ",
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[33] = "adc_dpll_clk_b2 ",
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[32] = "cts_vdec_clk ",
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[31] = "MPLL_CLK_TEST_OUT ",
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[30] = "Hdmirx_audmeas_clk ",
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[29] = "Hdmirx_pix_clk ",
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[28] = "Cts_sar_adc_clk ",
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[27] = "Hdmirx_mpll_div_clk ",
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[26] = "sc_clk_int ",
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[25] = "Hdmirx_tmds_clk ",
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[24] = "Hdmirx_aud_pll_clk ",
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[23] = "mmc_clk ",
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[22] = "eth_phy_ref_clk ",
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[21] = "i2s_clk_in_src0 ",
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[20] = "rtc_osc_clk_out ",
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[19] = "adc_dpll_clka2 ",
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[18] = "sys_cpu_clk_div16 ",
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[17] = "sys_pll_div16 ",
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[16] = "cts_FEC_CLK_2 ",
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[15] = "cts_FEC_CLK_1 ",
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[14] = "cts_FEC_CLK_0 ",
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[13] = "cts_amclk ",
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[12] = "Cts_demod_core_clk ",
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[11] = "mac_eth_tx_clk ",
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[10] = "cts_vdac_clk ",
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[9] = "cts_encl_clk ",
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[8] = "cts_encp_clk ",
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[7] = "clk81 ",
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[6] = "cts_enci_clk ",
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[5] = "gp1_pll_clk ",
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[4] = "gp0_pll_clk ",
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[3] = "A53_ring_osc_clk ",
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[2] = "am_ring_osc_clk_out_ee[2]",
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[1] = "am_ring_osc_clk_out_ee[1]",
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[0] = "am_ring_osc_clk_out_ee[0]",
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};
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int i;
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int len = sizeof(clk_table)/sizeof(char *);
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if (index == 0xff) {
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for (i = 0; i < len; i++)
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seq_printf(s, "[%2d][%10d]%s\n",
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i, gxbb_clk_util_clk_msr(i),
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clk_table[i]);
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return 0;
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}
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seq_printf(s, "[%10d]%s\n", gxbb_clk_util_clk_msr(index),
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clk_table[index]);
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clk_msr_index = 0xff;
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return 0;
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}
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int meson_clk_measure(unsigned int clk_mux)
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{
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int clk_val;
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@@ -574,6 +704,7 @@ int meson_clk_measure(unsigned int clk_mux)
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break;
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case MESON_CPU_MAJOR_ID_GXL:
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case MESON_CPU_MAJOR_ID_GXM:
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case MESON_CPU_MAJOR_ID_TXLX:
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clk_val = gxbb_clk_util_clk_msr(clk_mux);
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break;
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case MESON_CPU_MAJOR_ID_AXG:
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@@ -599,6 +730,8 @@ static int dump_clk(struct seq_file *s, void *what)
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gxm_clk_measure(s, what, clk_msr_index);
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else if (get_cpu_type() == MESON_CPU_MAJOR_ID_AXG)
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axg_clk_measure(s, what, clk_msr_index);
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else if (get_cpu_type() == MESON_CPU_MAJOR_ID_TXLX)
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txlx_clk_measure(s, what, clk_msr_index);
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return 0;
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}
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@@ -32,6 +32,9 @@
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#define MESON_PARM_APPLICABLE(p) (!!((p)->width))
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#define PNAME(x) \
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static const char *x[] __initconst
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struct parm {
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u16 reg_off;
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u8 shift;
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@@ -121,6 +124,84 @@ struct clk_gate _name = { \
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}, \
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}
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/*mux/div/gate macro*/
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#define GATE(_name, _reg, _bit, _pname, _flags) \
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struct clk_gate _name = { \
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.reg = (void __iomem *) _reg, \
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.bit_idx = (_bit), \
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.lock = &clk_lock, \
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.hw.init = &(struct clk_init_data) {\
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.name = #_name, \
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.ops = &clk_gate_ops, \
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.parent_names = (const char *[]){ _pname }, \
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.num_parents = 1, \
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.flags = (_flags),\
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}, \
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}
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#define DIV(_name, _reg, _shift, _width, _pname, _flags) \
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struct clk_divider _name = { \
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.reg = (void __iomem *) _reg, \
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.shift = _shift, \
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.width = _width, \
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.lock = &clk_lock, \
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.hw.init = &(struct clk_init_data) {\
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.name = #_name, \
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.ops = &clk_divider_ops, \
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.parent_names = (const char *[]){ _pname }, \
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.num_parents = 1, \
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.flags = (_flags),\
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}, \
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}
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#define MUX(_name, _reg, _mask, _shift, _pname, _flags) \
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struct clk_mux _name = { \
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.reg = (void __iomem *) _reg, \
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.mask = _mask, \
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.shift = _shift, \
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.hw.init = &(struct clk_init_data) {\
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.name = #_name, \
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.ops = &clk_mux_ops, \
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.parent_names = _pname, \
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.num_parents = ARRAY_SIZE(_pname), \
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.flags = (_flags),\
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}, \
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}
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#define MESON_MUX(_name, _reg, _mask, _shift, _pname, _flags)\
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struct clk_mux _name = { \
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.reg = (void __iomem *) _reg, \
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.mask = _mask, \
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.shift = _shift, \
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.flags = CLK_PARENT_ALTERNATE, \
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.hw.init = &(struct clk_init_data) {\
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.name = #_name, \
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.ops = &meson_clk_mux_ops, \
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.parent_names = _pname, \
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.num_parents = ARRAY_SIZE(_pname), \
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.flags = (_flags),\
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}, \
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}
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/*composite clock*/
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struct meson_composite {
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||||
unsigned int composite_id;
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||||
const char *name;
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||||
const char * const *parent_names;
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||||
int num_parents;
|
||||
struct clk_hw *mux_hw;
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||||
struct clk_hw *rate_hw;
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||||
struct clk_hw *gate_hw;
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||||
unsigned long flags;
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||||
};
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||||
|
||||
/*single clock,mux/div/gate*/
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||||
struct meson_hw {
|
||||
unsigned int hw_id;
|
||||
struct clk_hw *hw;
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||||
};
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||||
|
||||
/* clk_ops */
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extern const struct clk_ops meson_clk_pll_ro_ops;
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extern const struct clk_ops meson_clk_pll_ops;
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@@ -131,6 +212,13 @@ extern const struct clk_ops meson_clk_mux_ops;
|
||||
extern const struct clk_ops meson_axg_pll_ro_ops;
|
||||
extern const struct clk_ops meson_axg_pll_ops;
|
||||
|
||||
extern void meson_clk_register_composite(struct clk **soc_clks,
|
||||
struct meson_composite *composite,
|
||||
unsigned int length);
|
||||
extern void meson_hw_clk_register(struct clk **soc_clks,
|
||||
struct meson_hw *m,
|
||||
unsigned int length);
|
||||
|
||||
extern spinlock_t clk_lock;
|
||||
extern void __iomem *clk_base;
|
||||
extern struct clk **clks;
|
||||
@@ -141,4 +229,10 @@ void amlogic_init_misc(void);
|
||||
void axg_amlogic_init_sdemmc(void);
|
||||
void axg_amlogic_init_media(void);
|
||||
void axg_amlogic_init_misc(void);
|
||||
|
||||
/*txlx*/
|
||||
void meson_txlx_sdemmc_init(void);
|
||||
void meson_txlx_media_init(void);
|
||||
void meson_init_gpu(void);
|
||||
|
||||
#endif /* __CLKC_H */
|
||||
|
||||
8
drivers/amlogic/clk/txlx/Makefile
Normal file
8
drivers/amlogic/clk/txlx/Makefile
Normal file
@@ -0,0 +1,8 @@
|
||||
#
|
||||
# Makefile for Meson AXG clk
|
||||
#
|
||||
|
||||
obj-$(CONFIG_AMLOGIC_GX_CLK) += txlx.o txlx_ao.o \
|
||||
txlx_clk_sdemmc.o \
|
||||
txlx_clk_media.o \
|
||||
txlx_clk_gpu.o
|
||||
1017
drivers/amlogic/clk/txlx/txlx.c
Normal file
1017
drivers/amlogic/clk/txlx/txlx.c
Normal file
File diff suppressed because it is too large
Load Diff
300
drivers/amlogic/clk/txlx/txlx.h
Normal file
300
drivers/amlogic/clk/txlx/txlx.h
Normal file
@@ -0,0 +1,300 @@
|
||||
/*
|
||||
* drivers/amlogic/clk/txlx/txlx.h
|
||||
*
|
||||
* Copyright (C) 2017 Amlogic, Inc. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __TXLX_H
|
||||
#define __TXLX_H
|
||||
|
||||
/*
|
||||
* Clock controller register offsets
|
||||
*
|
||||
* Register offsets from the data sheet are listed in comment blocks below.
|
||||
* Those offsets must be multiplied by 4 before adding them to the base address
|
||||
* to get the right value
|
||||
*/
|
||||
/*ok*/
|
||||
#define HHI_GP0_PLL_CNTL 0x40 /* 0x10 offset in data sheet */
|
||||
/*new*/
|
||||
#define HHI_GP1_PLL_CNTL 0x60 /* 0x18 offset in data sheet */
|
||||
/*not define in spec*/
|
||||
#define HHI_HIFI_PLL_CNTL 0x80 /* 0x20 offset in data sheet */
|
||||
|
||||
#define HHI_PCIE_PLL_CNTL 0xd8 /* 0x36 offset in data sheet */
|
||||
#define HHI_PCIE_PLL_CNTL1 0xdc /* 0x37 offset in data sheet */
|
||||
#define HHI_PCIE_PLL_CNTL6 0xf0 /* 0x3c offset in data sheet */
|
||||
|
||||
#define HHI_GCLK_MPEG0 0x140 /* 0x50 offset in data sheet */
|
||||
#define HHI_GCLK_MPEG1 0x144 /* 0x51 offset in data sheet */
|
||||
#define HHI_GCLK_MPEG2 0x148 /* 0x52 offset in data sheet */
|
||||
#define HHI_GCLK_OTHER 0x150 /* 0x54 offset in data sheet */
|
||||
|
||||
#define HHI_GCLK_AO 0x154 /* 0x55 offset in data sheet */
|
||||
|
||||
#define HHI_VID_CLK_DIV 0x164 /* 0x59 offset in data sheet */
|
||||
#define HHI_SPICC_HCLK_CNTL 0x168 /* 0x5a offset in data sheet */
|
||||
|
||||
#define HHI_MPEG_CLK_CNTL 0x174 /* 0x5d offset in data sheet */
|
||||
#define HHI_AUD_CLK_CNTL 0x178 /* 0x5e offset in data sheet */
|
||||
#define HHI_VID_CLK_CNTL 0x17c /* 0x5f offset in data sheet */
|
||||
#define HHI_AUD_CLK_CNTL2 0x190 /* 0x64 offset in data sheet */
|
||||
#define HHI_VID_CLK_CNTL2 0x194 /* 0x65 offset in data sheet */
|
||||
#define HHI_SYS_CPU_CLK_CNTL0 0x19c /* 0x67 offset in data sheet */
|
||||
#define HHI_AUD_CLK_CNTL3 0x1A4 /* 0x69 offset in data sheet */
|
||||
#define HHI_AUD_CLK_CNTL4 0x1A8 /* 0x6a offset in data sheet */
|
||||
#define HHI_MALI_CLK_CNTL 0x1b0 /* 0x6c offset in data sheet */
|
||||
#define HHI_VPU_CLK_CNTL 0x1bC /* 0x6f offset in data sheet */
|
||||
|
||||
#define HHI_VDEC_CLK_CNTL 0x1E0 /* 0x78 offset in data sheet */
|
||||
#define HHI_VDEC2_CLK_CNTL 0x1E4 /* 0x79 offset in data sheet */
|
||||
#define HHI_VDEC3_CLK_CNTL 0x1E8 /* 0x7a offset in data sheet */
|
||||
#define HHI_VDEC4_CLK_CNTL 0x1EC /* 0x7b offset in data sheet */
|
||||
#define HHI_HDCP22_CLK_CNTL 0x1F0 /* 0x7c offset in data sheet */
|
||||
#define HHI_VAPBCLK_CNTL 0x1F4 /* 0x7d offset in data sheet */
|
||||
#define HHI_HDMIRX_CLK_CNTL 0x200 /* 0x80 offset in data sheet */
|
||||
#define HHI_HDMIRX_AUD_CLK_CNTL 0x204 /* 0x81 offset in data sheet */
|
||||
#define HHI_VPU_CLKB_CNTL 0x20C /* 0x83 offset in data sheet */
|
||||
#define HHI_ALOCKER_CLK_CNTL 0x234 /* 0x8d offset in data sheet */
|
||||
|
||||
#define HHI_VDIN_MEAS_CLK_CNTL 0x250 /* 0x94 offset in data sheet */
|
||||
#define HHI_PCM_CLK_CNTL 0x258 /* 0x96 offset in data sheet */
|
||||
#define HHI_NAND_CLK_CNTL 0x25C /* 0x97 offset in data sheet */
|
||||
#define HHI_SD_EMMC_CLK_CNTL 0x264 /* 0x99 offset in data sheet */
|
||||
|
||||
#define HHI_MPLL_CNTL 0x280 /* 0xa0 offset in data sheet */
|
||||
#define HHI_MPLL_CNTL2 0x284 /* 0xa1 offset in data sheet */
|
||||
#define HHI_MPLL_CNTL3 0x288 /* 0xa2 offset in data sheet */
|
||||
#define HHI_MPLL_CNTL4 0x28C /* 0xa3 offset in data sheet */
|
||||
#define HHI_MPLL_CNTL5 0x290 /* 0xa4 offset in data sheet */
|
||||
#define HHI_MPLL_CNTL6 0x294 /* 0xa5 offset in data sheet */
|
||||
#define HHI_MPLL_CNTL7 0x298 /* MP0, 0xa6 offset */
|
||||
#define HHI_MPLL_CNTL8 0x29C /* MP1, 0xa7 offset */
|
||||
#define HHI_MPLL_CNTL9 0x2A0 /* MP2, 0xa8 offset */
|
||||
#define HHI_MPLL_CNTL10 0x2A4 /* MP2, 0xa9 offset */
|
||||
|
||||
#define HHI_MPLL3_CNTL0 0x2E0 /* 0xb8 offset in data sheet */
|
||||
#define HHI_MPLL3_CNTL1 0x2E4 /* 0xb9 offset in data sheet */
|
||||
#define HHI_PLL_TOP_MISC 0x2E8 /* 0xba offset in data sheet */
|
||||
|
||||
#define HHI_ADC_PLL_CNTL 0x2A8 /* 0xaa offset in data sheet */
|
||||
#define HHI_ADC_PLL_CNTL2 0x2AC /* 0xab offset in data sheet */
|
||||
#define HHI_ADC_PLL_CNTL3 0x2B0 /* 0xac offset in data sheet */
|
||||
#define HHI_ADC_PLL_CNTL4 0x2B4 /* 0xad offset in data sheet */
|
||||
|
||||
#define HHI_SYS_PLL_CNTL 0x300 /* 0xc0 offset in data sheet */
|
||||
#define HHI_SYS_PLL_CNTL2 0x304 /* 0xc1 offset in data sheet */
|
||||
#define HHI_SYS_PLL_CNTL3 0x308 /* 0xc2 offset in data sheet */
|
||||
#define HHI_SYS_PLL_CNTL4 0x30c /* 0xc3 offset in data sheet */
|
||||
#define HHI_SYS_PLL_CNTL5 0x310 /* 0xc4 offset in data sheet */
|
||||
|
||||
#define HHI_HDMI_PLL_CNTL 0x320 /* 0xc8 offset in data sheet */
|
||||
#define HHI_HDMI_PLL_CNTL2 0x324 /* 0xc9 offset in data sheet */
|
||||
#define HHI_HDMI_PLL_CNTL3 0x328 /* 0xca offset in data sheet */
|
||||
#define HHI_HDMI_PLL_CNTL4 0x32C /* 0xcb offset in data sheet */
|
||||
#define HHI_HDMI_PLL_CNTL5 0x330 /* 0xcc offset in data sheet */
|
||||
|
||||
/* AO registers*/
|
||||
#define AO_RTI_PWR_CNTL_REG0 0x10 /* 0x4 offset in data sheet */
|
||||
#define AO_SAR_CLK 0x90 /* 0x24 offset in data sheet */
|
||||
|
||||
static const struct pll_rate_table sys_pll_rate_table[] = {
|
||||
PLL_RATE(24000000, 56, 1, 2),
|
||||
PLL_RATE(48000000, 64, 1, 2),
|
||||
PLL_RATE(72000000, 72, 1, 2),
|
||||
PLL_RATE(96000000, 64, 1, 2),
|
||||
PLL_RATE(120000000, 80, 1, 2),
|
||||
PLL_RATE(144000000, 96, 1, 2),
|
||||
PLL_RATE(168000000, 56, 1, 1),
|
||||
PLL_RATE(192000000, 64, 1, 1),
|
||||
PLL_RATE(216000000, 72, 1, 1),
|
||||
PLL_RATE(240000000, 80, 1, 1),
|
||||
PLL_RATE(264000000, 88, 1, 1),
|
||||
PLL_RATE(288000000, 96, 1, 1),
|
||||
PLL_RATE(312000000, 52, 1, 2),
|
||||
PLL_RATE(336000000, 56, 1, 2),
|
||||
PLL_RATE(360000000, 60, 1, 2),
|
||||
PLL_RATE(384000000, 64, 1, 2),
|
||||
PLL_RATE(408000000, 68, 1, 2),
|
||||
PLL_RATE(432000000, 72, 1, 2),
|
||||
PLL_RATE(456000000, 76, 1, 2),
|
||||
PLL_RATE(480000000, 80, 1, 2),
|
||||
PLL_RATE(504000000, 84, 1, 2),
|
||||
PLL_RATE(528000000, 88, 1, 2),
|
||||
PLL_RATE(552000000, 92, 1, 2),
|
||||
PLL_RATE(576000000, 96, 1, 2),
|
||||
PLL_RATE(600000000, 50, 1, 1),
|
||||
PLL_RATE(624000000, 52, 1, 1),
|
||||
PLL_RATE(648000000, 54, 1, 1),
|
||||
PLL_RATE(672000000, 56, 1, 1),
|
||||
PLL_RATE(696000000, 58, 1, 1),
|
||||
PLL_RATE(720000000, 60, 1, 1),
|
||||
PLL_RATE(744000000, 62, 1, 1),
|
||||
PLL_RATE(768000000, 64, 1, 1),
|
||||
PLL_RATE(792000000, 66, 1, 1),
|
||||
PLL_RATE(816000000, 68, 1, 1),
|
||||
PLL_RATE(840000000, 70, 1, 1),
|
||||
PLL_RATE(864000000, 72, 1, 1),
|
||||
PLL_RATE(888000000, 74, 1, 1),
|
||||
PLL_RATE(912000000, 76, 1, 1),
|
||||
PLL_RATE(936000000, 78, 1, 1),
|
||||
PLL_RATE(960000000, 80, 1, 1),
|
||||
PLL_RATE(984000000, 82, 1, 1),
|
||||
PLL_RATE(1008000000, 84, 1, 1),
|
||||
PLL_RATE(1032000000, 86, 1, 1),
|
||||
PLL_RATE(1056000000, 88, 1, 1),
|
||||
PLL_RATE(1080000000, 90, 1, 1),
|
||||
PLL_RATE(1104000000, 92, 1, 1),
|
||||
PLL_RATE(1128000000, 94, 1, 1),
|
||||
PLL_RATE(1152000000, 96, 1, 1),
|
||||
PLL_RATE(1176000000, 98, 1, 1),
|
||||
PLL_RATE(1200000000, 50, 1, 0),
|
||||
PLL_RATE(1224000000, 51, 1, 0),
|
||||
PLL_RATE(1248000000, 52, 1, 0),
|
||||
PLL_RATE(1272000000, 53, 1, 0),
|
||||
PLL_RATE(1296000000, 54, 1, 0),
|
||||
PLL_RATE(1320000000, 55, 1, 0),
|
||||
PLL_RATE(1344000000, 56, 1, 0),
|
||||
PLL_RATE(1368000000, 57, 1, 0),
|
||||
PLL_RATE(1392000000, 58, 1, 0),
|
||||
PLL_RATE(1416000000, 59, 1, 0),
|
||||
PLL_RATE(1440000000, 60, 1, 0),
|
||||
PLL_RATE(1464000000, 61, 1, 0),
|
||||
PLL_RATE(1488000000, 62, 1, 0),
|
||||
PLL_RATE(1512000000, 63, 1, 0),
|
||||
PLL_RATE(1536000000, 64, 1, 0),
|
||||
PLL_RATE(1560000000, 65, 1, 0),
|
||||
PLL_RATE(1584000000, 66, 1, 0),
|
||||
PLL_RATE(1608000000, 67, 1, 0),
|
||||
PLL_RATE(1632000000, 68, 1, 0),
|
||||
PLL_RATE(1656000000, 68, 1, 0),
|
||||
PLL_RATE(1680000000, 68, 1, 0),
|
||||
PLL_RATE(1704000000, 68, 1, 0),
|
||||
PLL_RATE(1728000000, 69, 1, 0),
|
||||
PLL_RATE(1752000000, 69, 1, 0),
|
||||
PLL_RATE(1776000000, 69, 1, 0),
|
||||
PLL_RATE(1800000000, 69, 1, 0),
|
||||
PLL_RATE(1824000000, 70, 1, 0),
|
||||
PLL_RATE(1848000000, 70, 1, 0),
|
||||
PLL_RATE(1872000000, 70, 1, 0),
|
||||
PLL_RATE(1896000000, 70, 1, 0),
|
||||
PLL_RATE(1920000000, 71, 1, 0),
|
||||
PLL_RATE(1944000000, 71, 1, 0),
|
||||
PLL_RATE(1968000000, 71, 1, 0),
|
||||
PLL_RATE(1992000000, 71, 1, 0),
|
||||
PLL_RATE(2016000000, 72, 1, 0),
|
||||
PLL_RATE(2040000000, 72, 1, 0),
|
||||
PLL_RATE(2064000000, 72, 1, 0),
|
||||
PLL_RATE(2088000000, 72, 1, 0),
|
||||
PLL_RATE(2112000000, 73, 1, 0),
|
||||
{ /* sentinel */ },
|
||||
};
|
||||
|
||||
/*TXLX: gp0_pll: Fdco: 0.96G~1.632G Fdco = 24*(M+frac)/N
|
||||
*N: recommend is 1
|
||||
*gp0_clk_out = Fdco /Fod
|
||||
*od=0 Fod=1 od=1 Fod=2 od=2 Fod=4 od=3 Fod=4
|
||||
*/
|
||||
static const struct pll_rate_table txlx_gp0_pll_rate_table[] = {
|
||||
PLL_RATE(240000000, 40, 1, 2),
|
||||
PLL_RATE(246000000, 41, 1, 2),
|
||||
PLL_RATE(252000000, 42, 1, 2),
|
||||
PLL_RATE(258000000, 43, 1, 2),
|
||||
PLL_RATE(264000000, 44, 1, 2),
|
||||
PLL_RATE(270000000, 45, 1, 2),
|
||||
PLL_RATE(276000000, 46, 1, 2),
|
||||
PLL_RATE(282000000, 47, 1, 2),
|
||||
PLL_RATE(288000000, 48, 1, 2),
|
||||
PLL_RATE(294000000, 49, 1, 2),
|
||||
PLL_RATE(300000000, 50, 1, 2),
|
||||
PLL_RATE(306000000, 51, 1, 2),
|
||||
PLL_RATE(312000000, 52, 1, 2),
|
||||
PLL_RATE(318000000, 53, 1, 2),
|
||||
PLL_RATE(324000000, 54, 1, 2),
|
||||
PLL_RATE(330000000, 55, 1, 2),
|
||||
PLL_RATE(336000000, 56, 1, 2),
|
||||
PLL_RATE(342000000, 57, 1, 2),
|
||||
PLL_RATE(348000000, 58, 1, 2),
|
||||
PLL_RATE(354000000, 59, 1, 2),
|
||||
PLL_RATE(360000000, 60, 1, 2),
|
||||
PLL_RATE(366000000, 61, 1, 2),
|
||||
PLL_RATE(372000000, 62, 1, 2),
|
||||
PLL_RATE(378000000, 63, 1, 2),
|
||||
PLL_RATE(384000000, 64, 1, 2),
|
||||
PLL_RATE(390000000, 65, 1, 3),
|
||||
PLL_RATE(396000000, 66, 1, 3),
|
||||
PLL_RATE(402000000, 67, 1, 3),
|
||||
PLL_RATE(408000000, 68, 1, 3),
|
||||
PLL_RATE(480000000, 40, 1, 1),
|
||||
PLL_RATE(492000000, 41, 1, 1),
|
||||
PLL_RATE(504000000, 42, 1, 1),
|
||||
PLL_RATE(516000000, 43, 1, 1),
|
||||
PLL_RATE(528000000, 44, 1, 1),
|
||||
PLL_RATE(540000000, 45, 1, 1),
|
||||
PLL_RATE(552000000, 46, 1, 1),
|
||||
PLL_RATE(564000000, 47, 1, 1),
|
||||
PLL_RATE(576000000, 48, 1, 1),
|
||||
PLL_RATE(588000000, 49, 1, 1),
|
||||
PLL_RATE(600000000, 50, 1, 1),
|
||||
PLL_RATE(612000000, 51, 1, 1),
|
||||
PLL_RATE(624000000, 52, 1, 1),
|
||||
PLL_RATE(636000000, 53, 1, 1),
|
||||
PLL_RATE(648000000, 54, 1, 1),
|
||||
PLL_RATE(660000000, 55, 1, 1),
|
||||
PLL_RATE(672000000, 56, 1, 1),
|
||||
PLL_RATE(684000000, 57, 1, 1),
|
||||
PLL_RATE(696000000, 58, 1, 1),
|
||||
PLL_RATE(708000000, 59, 1, 1),
|
||||
PLL_RATE(720000000, 60, 1, 1),
|
||||
PLL_RATE(732000000, 61, 1, 1),
|
||||
PLL_RATE(744000000, 62, 1, 1),
|
||||
PLL_RATE(756000000, 63, 1, 1),
|
||||
PLL_RATE(768000000, 64, 1, 1),
|
||||
PLL_RATE(780000000, 65, 1, 1),
|
||||
PLL_RATE(792000000, 66, 1, 1),
|
||||
PLL_RATE(804000000, 67, 1, 1),
|
||||
PLL_RATE(816000000, 68, 1, 1),
|
||||
PLL_RATE(960000000, 40, 1, 0),
|
||||
PLL_RATE(984000000, 41, 1, 0),
|
||||
PLL_RATE(1008000000, 42, 1, 0),
|
||||
PLL_RATE(1032000000, 43, 1, 0),
|
||||
PLL_RATE(1056000000, 44, 1, 0),
|
||||
PLL_RATE(1080000000, 45, 1, 0),
|
||||
PLL_RATE(1104000000, 46, 1, 0),
|
||||
PLL_RATE(1128000000, 47, 1, 0),
|
||||
PLL_RATE(1152000000, 48, 1, 0),
|
||||
PLL_RATE(1176000000, 49, 1, 0),
|
||||
PLL_RATE(1200000000, 50, 1, 0),
|
||||
PLL_RATE(1224000000, 51, 1, 0),
|
||||
PLL_RATE(1248000000, 52, 1, 0),
|
||||
PLL_RATE(1272000000, 53, 1, 0),
|
||||
PLL_RATE(1296000000, 54, 1, 0),
|
||||
PLL_RATE(1320000000, 55, 1, 0),
|
||||
PLL_RATE(1344000000, 56, 1, 0),
|
||||
PLL_RATE(1368000000, 57, 1, 0),
|
||||
PLL_RATE(1392000000, 58, 1, 0),
|
||||
PLL_RATE(1416000000, 59, 1, 0),
|
||||
PLL_RATE(1440000000, 60, 1, 0),
|
||||
PLL_RATE(1464000000, 61, 1, 0),
|
||||
PLL_RATE(1488000000, 62, 1, 0),
|
||||
PLL_RATE(1512000000, 63, 1, 0),
|
||||
PLL_RATE(1536000000, 64, 1, 0),
|
||||
PLL_RATE(1560000000, 65, 1, 0),
|
||||
PLL_RATE(1584000000, 66, 1, 0),
|
||||
PLL_RATE(1608000000, 67, 1, 0),
|
||||
PLL_RATE(1632000000, 68, 1, 0),
|
||||
{ /* sentinel */ },
|
||||
};
|
||||
|
||||
#endif /* __TXLX_H */
|
||||
141
drivers/amlogic/clk/txlx/txlx_ao.c
Normal file
141
drivers/amlogic/clk/txlx/txlx_ao.c
Normal file
@@ -0,0 +1,141 @@
|
||||
/*
|
||||
* drivers/amlogic/clk/txlx/txlx_ao.c
|
||||
*
|
||||
* Copyright (C) 2017 Amlogic, Inc. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*/
|
||||
|
||||
#include <linux/clk.h>
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/slab.h>
|
||||
#include <dt-bindings/clock/amlogic,txlx-clkc.h>
|
||||
|
||||
#include "../clkc.h"
|
||||
#include "txlx.h"
|
||||
|
||||
static struct clk_mux aoclk81 = {
|
||||
.reg = (void *)AO_RTI_PWR_CNTL_REG0,
|
||||
.mask = 0x1,
|
||||
.shift = 8,
|
||||
.flags = CLK_MUX_READ_ONLY,
|
||||
.lock = &clk_lock,
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "aoclk81",
|
||||
.ops = &clk_mux_ops,
|
||||
.parent_names = (const char *[]){ "clk81", "ao_slow_clk" },
|
||||
.num_parents = 2,
|
||||
.flags = (CLK_SET_RATE_NO_REPARENT),
|
||||
},
|
||||
};
|
||||
|
||||
/* sar_adc_clk */
|
||||
static struct clk_mux txlx_saradc_mux = {
|
||||
.reg = (void *)AO_SAR_CLK,
|
||||
.mask = 0x3,
|
||||
.shift = 9,
|
||||
.lock = &clk_lock,
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "txlx_saradc_mux",
|
||||
.ops = &clk_mux_ops,
|
||||
.parent_names = (const char *[]){ "xtal", "aoclk81"},
|
||||
.num_parents = 2,
|
||||
.flags = (CLK_GET_RATE_NOCACHE),
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_divider txlx_saradc_div = {
|
||||
.reg = (void *)AO_SAR_CLK,
|
||||
.shift = 0,
|
||||
.width = 8,
|
||||
.lock = &clk_lock,
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "txlx_saradc_div",
|
||||
.ops = &clk_divider_ops,
|
||||
.parent_names = (const char *[]){ "txlx_saradc_mux" },
|
||||
.num_parents = 1,
|
||||
.flags = (CLK_DIVIDER_ROUND_CLOSEST),
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_gate txlx_saradc_gate = {
|
||||
.reg = (void *)AO_SAR_CLK,
|
||||
.bit_idx = 8,
|
||||
.lock = &clk_lock,
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "txlx_saradc_gate",
|
||||
.ops = &clk_gate_ops,
|
||||
.parent_names = (const char *[]){ "txlx_saradc_div" },
|
||||
.num_parents = 1,
|
||||
.flags = (CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED),
|
||||
},
|
||||
};
|
||||
|
||||
/* Array of all clocks provided by this provider */
|
||||
|
||||
static struct clk_hw *txlx_ao_clk_hws[] = {
|
||||
[CLKID_AO_CLK81 - CLKID_AO_CLK81]
|
||||
= &aoclk81.hw,
|
||||
[CLKID_SARADC_MUX - CLKID_AO_CLK81]
|
||||
= &txlx_saradc_mux.hw,
|
||||
[CLKID_SARADC_DIV - CLKID_AO_CLK81]
|
||||
= &txlx_saradc_div.hw,
|
||||
[CLKID_SARADC_GATE - CLKID_AO_CLK81]
|
||||
= &txlx_saradc_gate.hw,
|
||||
};
|
||||
|
||||
static int txlx_aoclkc_probe(struct platform_device *pdev)
|
||||
{
|
||||
void __iomem *aoclk_base;
|
||||
int clkid;
|
||||
struct device *dev = &pdev->dev;
|
||||
|
||||
/* Generic clocks and PLLs */
|
||||
aoclk_base = of_iomap(dev->of_node, 0);
|
||||
if (!aoclk_base) {
|
||||
pr_err("%s: Unable to map clk base\n", __func__);
|
||||
return -ENXIO;
|
||||
}
|
||||
/* Populate the base address for ao clk */
|
||||
aoclk81.reg = aoclk_base + (u64)aoclk81.reg;
|
||||
txlx_saradc_mux.reg = aoclk_base + (u64)txlx_saradc_mux.reg;
|
||||
txlx_saradc_div.reg = aoclk_base + (u64)txlx_saradc_div.reg;
|
||||
txlx_saradc_gate.reg = aoclk_base + (u64)txlx_saradc_gate.reg;
|
||||
|
||||
for (clkid = CLKID_AO_BASE; clkid < NR_CLKS; clkid++) {
|
||||
if (txlx_ao_clk_hws[clkid-CLKID_AO_BASE]) {
|
||||
clks[clkid] = clk_register(NULL,
|
||||
txlx_ao_clk_hws[clkid-CLKID_AO_BASE]);
|
||||
WARN_ON(IS_ERR(clks[clkid]));
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct of_device_id txlx_aoclkc_match_table[] = {
|
||||
{ .compatible = "amlogic,txlx-aoclkc" },
|
||||
{ }
|
||||
};
|
||||
|
||||
static struct platform_driver txlx_aoclk_driver = {
|
||||
.probe = txlx_aoclkc_probe,
|
||||
.driver = {
|
||||
.name = "txlx-aoclkc",
|
||||
.of_match_table = txlx_aoclkc_match_table,
|
||||
},
|
||||
};
|
||||
|
||||
builtin_platform_driver(txlx_aoclk_driver);
|
||||
105
drivers/amlogic/clk/txlx/txlx_clk_gpu.c
Normal file
105
drivers/amlogic/clk/txlx/txlx_clk_gpu.c
Normal file
@@ -0,0 +1,105 @@
|
||||
/*
|
||||
* drivers/amlogic/clk/txlx/txlx_clk_gpu.c
|
||||
*
|
||||
* Copyright (C) 2017 Amlogic, Inc. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*/
|
||||
|
||||
#include <linux/clk.h>
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/slab.h>
|
||||
#include <dt-bindings/clock/amlogic,txlx-clkc.h>
|
||||
|
||||
#include "../clkc.h"
|
||||
#include "txlx.h"
|
||||
|
||||
PNAME(gpus_parent_names) = { "xtal", "gp0_pll", "mpll2", "mpll1",
|
||||
"fclk_div7", "fclk_div4", "fclk_div3", "fclk_div5"};
|
||||
PNAME(gpumux_parent_names) = { "gpu_p0_composite", "gpu_p1_composite"};
|
||||
|
||||
/* gpu p0 */
|
||||
static MUX(gpu_p0_mux, HHI_MALI_CLK_CNTL, 0x7, 9, gpus_parent_names,
|
||||
CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED);
|
||||
static DIV(gpu_p0_div, HHI_MALI_CLK_CNTL, 0, 7, "gpu_p0_mux",
|
||||
CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED);
|
||||
static GATE(gpu_p0_gate, HHI_MALI_CLK_CNTL, 8, "gpu_p0_div",
|
||||
CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED);
|
||||
/* gpu p1 */
|
||||
static MUX(gpu_p1_mux, HHI_MALI_CLK_CNTL, 0x7, 25, gpus_parent_names,
|
||||
CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED);
|
||||
static DIV(gpu_p1_div, HHI_MALI_CLK_CNTL, 16, 7, "gpu_p1_mux",
|
||||
CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED);
|
||||
static GATE(gpu_p1_gate, HHI_MALI_CLK_CNTL, 24, "gpu_p1_div",
|
||||
CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED);
|
||||
|
||||
static MESON_MUX(gpu_mux, HHI_MALI_CLK_CNTL, 0x1, 31,
|
||||
gpumux_parent_names, CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED);
|
||||
|
||||
/* for init mux/div/gate clocks reg base*/
|
||||
static struct clk_mux *txlx_gpu_clk_muxes[] = {
|
||||
&gpu_p0_mux,
|
||||
&gpu_p1_mux,
|
||||
&gpu_mux,
|
||||
};
|
||||
|
||||
static struct clk_divider *txlx_gpu_clk_divs[] = {
|
||||
&gpu_p0_div,
|
||||
&gpu_p1_div,
|
||||
};
|
||||
|
||||
static struct clk_gate *txlx_gpu_clk_gates[] = {
|
||||
&gpu_p0_gate,
|
||||
&gpu_p1_gate,
|
||||
};
|
||||
|
||||
static struct meson_composite gpu_composite[] = {
|
||||
{CLKID_GPU_P0_COMP, "gpu_p0_composite",
|
||||
gpus_parent_names, ARRAY_SIZE(gpus_parent_names),
|
||||
&gpu_p0_mux.hw, &gpu_p0_div.hw,
|
||||
&gpu_p0_gate.hw, 0
|
||||
},/*gpu_p0*/
|
||||
|
||||
{CLKID_GPU_P1_COMP, "gpu_p1_composite",
|
||||
gpus_parent_names, ARRAY_SIZE(gpus_parent_names),
|
||||
&gpu_p1_mux.hw, &gpu_p1_div.hw, &gpu_p1_gate.hw, 0
|
||||
},/*gpu_p1*/
|
||||
};
|
||||
void meson_init_gpu(void)
|
||||
{
|
||||
int i, length;
|
||||
|
||||
length = ARRAY_SIZE(gpu_composite);
|
||||
/* Populate base address for gpu muxes, divs,gates */
|
||||
for (i = 0; i < ARRAY_SIZE(txlx_gpu_clk_muxes); i++)
|
||||
txlx_gpu_clk_muxes[i]->reg = clk_base +
|
||||
(u64)txlx_gpu_clk_muxes[i]->reg;
|
||||
for (i = 0; i < ARRAY_SIZE(txlx_gpu_clk_divs); i++)
|
||||
txlx_gpu_clk_divs[i]->reg = clk_base +
|
||||
(u64)txlx_gpu_clk_divs[i]->reg;
|
||||
for (i = 0; i < ARRAY_SIZE(txlx_gpu_clk_gates); i++)
|
||||
txlx_gpu_clk_gates[i]->reg = clk_base +
|
||||
(u64)txlx_gpu_clk_gates[i]->reg;
|
||||
|
||||
meson_clk_register_composite(clks, gpu_composite, length);
|
||||
|
||||
clks[CLKID_GPU_MUX] = clk_register(NULL, &gpu_mux.hw);
|
||||
WARN_ON(IS_ERR(clks[CLKID_GPU_MUX]));
|
||||
|
||||
clk_set_parent(clks[CLKID_GPU_MUX], clks[CLKID_GPU_P0_COMP]);
|
||||
clk_prepare_enable(clks[CLKID_GPU_P0_COMP]);
|
||||
clk_prepare_enable(clks[CLKID_GPU_P1_COMP]);
|
||||
clk_set_rate(clks[CLKID_GPU_MUX], 400000000);
|
||||
}
|
||||
654
drivers/amlogic/clk/txlx/txlx_clk_media.c
Normal file
654
drivers/amlogic/clk/txlx/txlx_clk_media.c
Normal file
@@ -0,0 +1,654 @@
|
||||
/*
|
||||
* drivers/amlogic/clk/txlx/txlx_clk_media.c
|
||||
*
|
||||
* Copyright (C) 2017 Amlogic, Inc. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*/
|
||||
|
||||
#include <linux/clk.h>
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/slab.h>
|
||||
#include <dt-bindings/clock/amlogic,txlx-clkc.h>
|
||||
|
||||
#include "../clkc.h"
|
||||
#include "txlx.h"
|
||||
|
||||
/* cts_vdin_meas_clk */
|
||||
PNAME(meas_parent_names) = { "xtal", "fclk_div4",
|
||||
"fclk_div3", "fclk_div5", "vid_pll", "vid2_pll", "null", "null" };
|
||||
static MUX(vdin_meas_mux, HHI_VDIN_MEAS_CLK_CNTL, 0x7, 9, meas_parent_names,
|
||||
CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED);
|
||||
static DIV(vdin_meas_div, HHI_VDIN_MEAS_CLK_CNTL, 0, 7, "vdin_meas_mux",
|
||||
CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED);
|
||||
static GATE(vdin_meas_gate, HHI_VDIN_MEAS_CLK_CNTL, 20, "vdin_meas_div",
|
||||
CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED);
|
||||
/* cts_vpu_p0_clk */
|
||||
PNAME(vpu_parent_names) = { "fclk_div4", "fclk_div3", "fclk_div5",
|
||||
"fclk_div7", "null", "null", "null", "null"};
|
||||
static MUX(vpu_p0_mux, HHI_VPU_CLK_CNTL, 0x7, 9, vpu_parent_names,
|
||||
CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED);
|
||||
static DIV(vpu_p0_div, HHI_VPU_CLK_CNTL, 0, 7, "vpu_p0_mux",
|
||||
CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED);
|
||||
static GATE(vpu_p0_gate, HHI_VPU_CLK_CNTL, 8, "vpu_p0_div",
|
||||
CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED);
|
||||
/* cts_vpu_p1_clk */
|
||||
static MUX(vpu_p1_mux, HHI_VPU_CLK_CNTL, 0x7, 25, vpu_parent_names,
|
||||
CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED);
|
||||
static DIV(vpu_p1_div, HHI_VPU_CLK_CNTL, 16, 7, "vpu_p1_mux",
|
||||
CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED);
|
||||
static GATE(vpu_p1_gate, HHI_VPU_CLK_CNTL, 24, "vpu_p1_div",
|
||||
CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED);
|
||||
/* vpu_clkb_tmp */
|
||||
PNAME(vpu_clkb_parent_names) = { "vpu_mux",
|
||||
"fclk_div5", "vid_pll", "fclk_div4" };
|
||||
static MUX(vpu_clkb_tmp_mux, HHI_VPU_CLKB_CNTL, 0x3, 20,
|
||||
vpu_clkb_parent_names, CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED);
|
||||
static DIV(vpu_clkb_tmp_div, HHI_VPU_CLKB_CNTL, 16, 4, "vpu_clkb_tmp_mux",
|
||||
CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED);
|
||||
static GATE(vpu_clkb_tmp_gate, HHI_VPU_CLKB_CNTL, 24, "vpu_clkb_tmp_div",
|
||||
CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED);
|
||||
/* vpu_clkb */
|
||||
PNAME(vpu_clkb_nomux_parent_names) = { "vpu_clkb_tmp_composite" };
|
||||
static DIV(vpu_clkb_div, HHI_VPU_CLKB_CNTL, 0, 8, "vpu_clkb_tmp_composite",
|
||||
CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED);
|
||||
static GATE(vpu_clkb_gate, HHI_VPU_CLKB_CNTL, 8, "vpu_clkb_div",
|
||||
CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED);
|
||||
/* vpu mux clk */
|
||||
PNAME(vpu_mux_parent_names) = { "vpu_p0_composite", "vpu_p1_composite" };
|
||||
static MESON_MUX(vpu_mux, HHI_VPU_CLK_CNTL, 0x1, 31,
|
||||
vpu_mux_parent_names, CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED);
|
||||
|
||||
/* cts_vapb p0 clk */
|
||||
static MUX(vapb_p0_mux, HHI_VAPBCLK_CNTL, 0x7, 9, vpu_parent_names,
|
||||
CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED);
|
||||
static DIV(vapb_p0_div, HHI_VAPBCLK_CNTL, 0, 7, "vapb_p0_mux",
|
||||
CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED);
|
||||
static GATE(vapb_p0_gate, HHI_VAPBCLK_CNTL, 8, "vapb_p0_div",
|
||||
CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED);
|
||||
/* cts_vapb p1 clk */
|
||||
static MUX(vapb_p1_mux, HHI_VAPBCLK_CNTL, 0x7, 25, vpu_parent_names,
|
||||
CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED);
|
||||
static DIV(vapb_p1_div, HHI_VAPBCLK_CNTL, 16, 7, "vapb_p1_mux",
|
||||
CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED);
|
||||
static GATE(vapb_p1_gate, HHI_VAPBCLK_CNTL, 24, "vapb_p1_div",
|
||||
CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED);
|
||||
|
||||
/* cts_vapb mux clk */
|
||||
PNAME(vapb_mux_parent_names) = { "vapb_p0_composite", "vapb_p1_composite" };
|
||||
static MESON_MUX(vapb_mux, HHI_VAPBCLK_CNTL, 0x1, 31,
|
||||
vapb_mux_parent_names, CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED);
|
||||
static GATE(ge2d_gate, HHI_VAPBCLK_CNTL, 30, "vapb_mux",
|
||||
CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED);
|
||||
|
||||
/*hdmirx cfg clock*/
|
||||
PNAME(hdmirx_parent_names) = { "xtal", "fclk_div4", "fclk_div3", "fclk_div5" };
|
||||
static MUX(hdmirx_cfg_mux, HHI_HDMIRX_CLK_CNTL, 0x3, 9, hdmirx_parent_names,
|
||||
CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED);
|
||||
static DIV(hdmirx_cfg_div, HHI_HDMIRX_CLK_CNTL, 0, 7, "hdmirx_cfg_mux",
|
||||
CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED);
|
||||
static GATE(hdmirx_cfg_gate, HHI_HDMIRX_CLK_CNTL, 8, "hdmirx_cfg_div",
|
||||
CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED);
|
||||
/*hdmirx modet clock*/
|
||||
static MUX(hdmirx_modet_mux, HHI_HDMIRX_CLK_CNTL,
|
||||
0x3, 25, hdmirx_parent_names, CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED);
|
||||
static DIV(hdmirx_modet_div, HHI_HDMIRX_CLK_CNTL, 16, 7, "hdmirx_modet_mux",
|
||||
CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED);
|
||||
static GATE(hdmirx_modet_gate, HHI_HDMIRX_CLK_CNTL, 24, "hdmirx_modet_div",
|
||||
CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED);
|
||||
|
||||
/*hdmirx audmeas clock*/
|
||||
PNAME(hdmirx_ref_parent_names) = { "fclk_div4",
|
||||
"fclk_div3", "fclk_div5", "fclk_div7" };
|
||||
static MUX(hdmirx_audmeas_mux, HHI_HDMIRX_AUD_CLK_CNTL, 0x3, 9,
|
||||
hdmirx_ref_parent_names, CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED);
|
||||
static DIV(hdmirx_audmeas_div, HHI_HDMIRX_AUD_CLK_CNTL, 0, 7,
|
||||
"hdmirx_audmeas_mux", CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED);
|
||||
static GATE(hdmirx_audmeas_gate, HHI_HDMIRX_AUD_CLK_CNTL, 8,
|
||||
"hdmirx_audmeas_div", CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED);
|
||||
/* hdmirx acr clock*/
|
||||
static MUX(hdmirx_acr_mux, HHI_HDMIRX_AUD_CLK_CNTL, 0x3, 25,
|
||||
hdmirx_ref_parent_names, CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED);
|
||||
static DIV(hdmirx_acr_div, HHI_HDMIRX_AUD_CLK_CNTL, 16, 7, "hdmirx_acr_mux",
|
||||
CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED);
|
||||
static GATE(hdmirx_acr_gate, HHI_HDMIRX_AUD_CLK_CNTL, 24, "hdmirx_acr_div",
|
||||
CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED);
|
||||
/* hdcp22 skpclk*/
|
||||
PNAME(hdcp22_skp_parent_names) = { "xtal",
|
||||
"fclk_div4", "fclk_div3", "fclk_div5" };
|
||||
static MUX(hdcp22_skp_mux, HHI_HDCP22_CLK_CNTL,
|
||||
0x3, 25, hdcp22_skp_parent_names, CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED);
|
||||
static DIV(hdcp22_skp_div, HHI_HDCP22_CLK_CNTL, 16, 7, "hdcp22_skp_mux",
|
||||
CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED);
|
||||
static GATE(hdcp22_skp_gate, HHI_HDCP22_CLK_CNTL, 24, "hdcp22_skp_div",
|
||||
CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED);
|
||||
/* hdcp22 esm clock */
|
||||
PNAME(hdcp22_esm_parent_names) = { "fclk_div7",
|
||||
"fclk_div4", "fclk_div3", "fclk_div5" };
|
||||
static MUX(hdcp22_esm_mux, HHI_HDCP22_CLK_CNTL, 0x3, 9,
|
||||
hdcp22_esm_parent_names, CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED);
|
||||
static DIV(hdcp22_esm_div, HHI_HDCP22_CLK_CNTL, 0, 7, "hdcp22_esm_mux",
|
||||
CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED);
|
||||
static GATE(hdcp22_esm_gate, HHI_HDCP22_CLK_CNTL, 8, "hdcp22_esm_div",
|
||||
CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED);
|
||||
|
||||
/*vdec clock*/
|
||||
/* cts_vdec_clk */
|
||||
PNAME(dec_parent_names) = { "fclk_div4", "fclk_div3",
|
||||
"fclk_div5", "fclk_div7", "mpll1", "mpll2", "gp0_pll", "xtal" };
|
||||
static MUX(vdec_p0_mux, HHI_VDEC_CLK_CNTL, 0x7, 9, dec_parent_names,
|
||||
CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED);
|
||||
static DIV(vdec_p0_div, HHI_VDEC_CLK_CNTL, 0, 7, "vdec_p0_mux",
|
||||
CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED);
|
||||
static GATE(vdec_p0_gate, HHI_VDEC_CLK_CNTL, 8, "vdec_p0_div",
|
||||
CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED);
|
||||
static MUX(vdec_p1_mux, HHI_VDEC3_CLK_CNTL, 0x7, 9, dec_parent_names,
|
||||
CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED);
|
||||
static DIV(vdec_p1_div, HHI_VDEC3_CLK_CNTL, 0, 7, "vdec_p1_mux",
|
||||
CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED);
|
||||
static GATE(vdec_p1_gate, HHI_VDEC3_CLK_CNTL, 8, "vdec_p1_div",
|
||||
CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED);
|
||||
|
||||
/* vdec_mux clk */
|
||||
PNAME(vdec_mux_parent_names) = { "vdec_p0_composite", "vdec_p1_composite" };
|
||||
static MESON_MUX(vdec_mux, HHI_VDEC3_CLK_CNTL, 0x1, 15,
|
||||
vdec_mux_parent_names, CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED);
|
||||
|
||||
/* hcodev clock*/
|
||||
static MUX(hcodec_p0_mux, HHI_VDEC_CLK_CNTL, 0x7, 25, dec_parent_names,
|
||||
CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED);
|
||||
static DIV(hcodec_p0_div, HHI_VDEC_CLK_CNTL, 16, 7, "hcodec_p0_mux",
|
||||
CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED);
|
||||
static GATE(hcodec_p0_gate, HHI_VDEC_CLK_CNTL, 24, "hcodec_p0_div",
|
||||
CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED);
|
||||
static MUX(hcodec_p1_mux, HHI_VDEC3_CLK_CNTL, 0x7, 25, dec_parent_names,
|
||||
CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED);
|
||||
static DIV(hcodec_p1_div, HHI_VDEC3_CLK_CNTL, 16, 7, "hcodec_p1_mux",
|
||||
CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED);
|
||||
static GATE(hcodec_p1_gate, HHI_VDEC3_CLK_CNTL, 24, "hcodec_p1_div",
|
||||
CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED);
|
||||
|
||||
/* hcodec_mux clk */
|
||||
PNAME(hcodec_mux_parent_names) = {
|
||||
"hcodec_p0_composite", "hcodec_p1_composite" };
|
||||
static MESON_MUX(hcodec_mux, HHI_VDEC3_CLK_CNTL, 0x1, 31,
|
||||
hcodec_mux_parent_names, CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED);
|
||||
|
||||
|
||||
/* hevc clock */
|
||||
static MUX(hevc_p0_mux, HHI_VDEC2_CLK_CNTL, 0x7, 25, dec_parent_names,
|
||||
CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED);
|
||||
static DIV(hevc_p0_div, HHI_VDEC2_CLK_CNTL, 16, 7, "hevc_p0_mux",
|
||||
CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED);
|
||||
static GATE(hevc_p0_gate, HHI_VDEC2_CLK_CNTL, 24, "hevc_p0_div",
|
||||
CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED);
|
||||
static MUX(hevc_p1_mux, HHI_VDEC4_CLK_CNTL, 0x7, 25, dec_parent_names,
|
||||
CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED);
|
||||
static DIV(hevc_p1_div, HHI_VDEC4_CLK_CNTL, 16, 7, "hevc_p1_mux",
|
||||
CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED);
|
||||
static GATE(hevc_p1_gate, HHI_VDEC4_CLK_CNTL, 24, "hevc_p1_div",
|
||||
CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED);
|
||||
|
||||
/* hevc_mux clk */
|
||||
PNAME(hevc_mux_parent_names) = { "hevc_p0_composite", "hevc_p1_composite" };
|
||||
static MESON_MUX(hevc_mux, HHI_VDEC4_CLK_CNTL, 0x1, 31,
|
||||
hevc_mux_parent_names, CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED);
|
||||
|
||||
/* audio clocks */
|
||||
/* cts amclk */
|
||||
PNAME(cts_amclk_parent_names) = { "hdmirx_aud_pll_clk",
|
||||
"mpll0", "mpll1", "mpll2", "mpll3", "gp0_pll", "gp0_pll", "null" };
|
||||
static MUX(cts_amclk_mux, HHI_AUD_CLK_CNTL, 0x7, 9, cts_amclk_parent_names,
|
||||
CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED);
|
||||
static DIV(cts_amclk_div, HHI_AUD_CLK_CNTL, 0, 7, "cts_amclk_mux",
|
||||
CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED);
|
||||
static GATE(cts_amclk_gate, HHI_AUD_CLK_CNTL, 8, "cts_amclk_div",
|
||||
CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED);
|
||||
|
||||
/* cts_iec958_spdif clock
|
||||
* |\
|
||||
* 0 | \
|
||||
* | |-------
|
||||
* 1 | /
|
||||
* |/
|
||||
* offset 0x64
|
||||
* when bit[27] = 0, cts_amclk_composite
|
||||
* when bit[27] = 1, iec958_int_composite
|
||||
*/
|
||||
PNAME(cts_iec958_spdif_parent_names) = {
|
||||
"cts_amclk_composite", "iec958_int_composite" };
|
||||
static MUX(cts_iec958_spdif, HHI_AUD_CLK_CNTL2, 0x1, 27,
|
||||
cts_iec958_spdif_parent_names, CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED);
|
||||
|
||||
/* iec958_int_composite, bit27 = 1
|
||||
*PNAME(cts_iec958_int_parent_names) = { "hdmirx_aud_pll_clk", "mpll0",
|
||||
*"mpll1", "mpll2", "mpll3", "gp0_pll", "gp1_pll", "null"};
|
||||
*/
|
||||
PNAME(cts_iec958_int_parent_names) = { "hdmirx_aud_pll_clk", "mpll0",
|
||||
"mpll1", "mpll2" };
|
||||
static MUX(cts_iec958_int_mux, HHI_AUD_CLK_CNTL2, 0x3, 25,
|
||||
cts_iec958_int_parent_names, CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED);
|
||||
static DIV(cts_iec958_int_div, HHI_AUD_CLK_CNTL2,
|
||||
16, 8, "cts_iec958_int_mux", CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED);
|
||||
static GATE(cts_iec958_int_gate, HHI_AUD_CLK_CNTL2,
|
||||
24, "cts_iec958_int_div", CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED);
|
||||
|
||||
/* cts pdm*/
|
||||
PNAME(cts_pdm_parent_names) = { "cts_amclk_composite", "mpll0",
|
||||
"mpll1", "mpll2", "mpll3", "gp0_pll", "gp1_pll", "hdmirx_aud_pll_clk"};
|
||||
static MUX(cts_pdm_mux, HHI_AUD_CLK_CNTL3, 0x7, 17, cts_pdm_parent_names,
|
||||
CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED);
|
||||
static DIV(cts_pdm_div, HHI_AUD_CLK_CNTL3, 0, 16, "cts_pdm_mux",
|
||||
CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED);
|
||||
static GATE(cts_pdm_gate, HHI_AUD_CLK_CNTL3, 16, "cts_pdm_div",
|
||||
CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED);
|
||||
/* cts audin mclk */
|
||||
PNAME(cts_audin_mclk_parent_names) = { "vid2_pll", "mpll0", "mpll1",
|
||||
"mpll2", "gp0_pll", "gp1_pll", "hdmirx_aud_pll_clk", "vid_pll"};
|
||||
static MUX(cts_audin_mclk_mux, HHI_AUD_CLK_CNTL4, 0x7, 12,
|
||||
cts_audin_mclk_parent_names, CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED);
|
||||
static DIV(cts_audin_mclk_div, HHI_AUD_CLK_CNTL4,
|
||||
0, 10, "cts_audin_mclk_mux", CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED);
|
||||
static GATE(cts_audin_mclk_gate, HHI_AUD_CLK_CNTL4,
|
||||
15, "cts_audin_mclk_div", CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED);
|
||||
/* cts audin sclk */
|
||||
PNAME(cts_audin_sclk_parent_names) = { "cts_audin_mclk_composite" };
|
||||
static DIV(cts_audin_sclk_div, HHI_AUD_CLK_CNTL4,
|
||||
16, 7, "cts_audin_mclk_composite", CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED);
|
||||
static GATE(cts_audin_sclk_gate, HHI_AUD_CLK_CNTL4,
|
||||
23, "cts_audin_sclk_div", CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED);
|
||||
/* cts audin lrclk */
|
||||
PNAME(cts_audin_lrclk_parent_names) = { "cts_audin_sclk_composite" };
|
||||
static DIV(cts_audin_lrclk_div, HHI_AUD_CLK_CNTL4,
|
||||
24, 7, "cts_audin_sclk_composite", CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED);
|
||||
static GATE(cts_audin_lrclk_gate, HHI_AUD_CLK_CNTL4,
|
||||
31, "cts_audin_lrclk_div", CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED);
|
||||
|
||||
|
||||
/* cts alocker in clk*/
|
||||
PNAME(cts_alocker_in_parent_names) = { "cts_hdmirx_aud_pll_clk",
|
||||
"cts_audin_mclk_composite", "audin_pcm_clk_in", "audin_hdmirx_aud_clk",
|
||||
"audin_i2s_sclk_in_0", "audin_i2s_sclk_in_1", "audin_i2s_sclk_in_2",
|
||||
"audin_i2s_sclk_in_3"};
|
||||
static MUX(cts_alocker_in_mux, HHI_ALOCKER_CLK_CNTL, 0x7, 9,
|
||||
cts_alocker_in_parent_names, CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED);
|
||||
static DIV(cts_alocker_in_div, HHI_ALOCKER_CLK_CNTL,
|
||||
0, 8, "cts_alocker_in_mux", CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED);
|
||||
static GATE(cts_alocker_in_gate, HHI_ALOCKER_CLK_CNTL,
|
||||
8, "cts_alocker_in_div", CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED);
|
||||
/* cts alocker out clk*/
|
||||
PNAME(cts_alocker_out_parent_names) = {
|
||||
"cts_amclk_composite", "cts_clk_i958", "cts_aoclk_int",
|
||||
"cts_pdm_composite", "cts_pcm_mclk_composite",
|
||||
"cts_audin_mclk_composite", "cts_encp_clk", "cts_enci_clk" };
|
||||
static MUX(cts_alocker_out_mux, HHI_ALOCKER_CLK_CNTL, 0x7, 25,
|
||||
cts_alocker_out_parent_names, CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED);
|
||||
static DIV(cts_alocker_out_div, HHI_ALOCKER_CLK_CNTL,
|
||||
16, 8, "cts_alocker_out_mux", CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED);
|
||||
static GATE(cts_alocker_out_gate, HHI_ALOCKER_CLK_CNTL,
|
||||
24, "cts_alocker_out_div", CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED);
|
||||
/* cts pcm mclk */
|
||||
PNAME(cts_pcm_mclk_parent_names) = {
|
||||
"mpll0", "mpll1", "mpll2", "fclk_div5" };
|
||||
static MUX(cts_pcm_mclk_mux, HHI_PCM_CLK_CNTL, 0x3, 10,
|
||||
cts_pcm_mclk_parent_names, CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED);
|
||||
static DIV(cts_pcm_mclk_div, HHI_PCM_CLK_CNTL, 0, 9, "cts_pcm_mclk_mux",
|
||||
CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED);
|
||||
static GATE(cts_pcm_mclk_gate, HHI_PCM_CLK_CNTL, 9, "cts_pcm_mclk_div",
|
||||
CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED);
|
||||
/* cts pcm sclk */
|
||||
PNAME(cts_pcm_sclk_parent_names) = { "cts_pcm_mclk_composite" };
|
||||
static DIV(cts_pcm_sclk_div, HHI_PCM_CLK_CNTL,
|
||||
16, 6, "cts_pcm_mclk_composite", CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED);
|
||||
static GATE(cts_pcm_sclk_gate, HHI_PCM_CLK_CNTL, 22, "cts_pcm_sclk_div",
|
||||
CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED);
|
||||
|
||||
#if 0
|
||||
static struct clk_hw *media_vhec_mux[] = {
|
||||
[CLKID_VDEC_MUX - CLKID_VDEC_MUX] = &vdec_mux.hw,
|
||||
[CLKID_HCODEC_MUX - CLKID_VDEC_MUX] = &hcodec_mux.hw,
|
||||
[CLKID_HEVC_MUX - CLKID_VDEC_MUX] = &hevc_mux.hw,
|
||||
};
|
||||
#endif
|
||||
|
||||
/* for init mux clocks reg base*/
|
||||
static struct clk_mux *txlx_media_clk_muxes[] = {
|
||||
&vdin_meas_mux,
|
||||
&vpu_p0_mux,
|
||||
&vpu_p1_mux,
|
||||
&vpu_mux,
|
||||
&vapb_p0_mux,
|
||||
&vapb_p1_mux,
|
||||
&vapb_mux,
|
||||
&vpu_clkb_tmp_mux,
|
||||
&hdmirx_cfg_mux,
|
||||
&hdmirx_modet_mux,
|
||||
&hdmirx_audmeas_mux,
|
||||
&hdmirx_acr_mux,
|
||||
&hdcp22_skp_mux,
|
||||
&hdcp22_esm_mux,
|
||||
&vdec_p0_mux,
|
||||
&vdec_p1_mux,
|
||||
&vdec_mux,
|
||||
&hcodec_p0_mux,
|
||||
&hcodec_p1_mux,
|
||||
&hcodec_mux,
|
||||
&hevc_p0_mux,
|
||||
&hevc_p1_mux,
|
||||
&hevc_mux,
|
||||
&cts_amclk_mux,
|
||||
&cts_iec958_int_mux,
|
||||
&cts_iec958_spdif,
|
||||
&cts_pdm_mux,
|
||||
&cts_audin_mclk_mux,
|
||||
&cts_alocker_in_mux,
|
||||
&cts_alocker_out_mux,
|
||||
&cts_pcm_mclk_mux,
|
||||
};
|
||||
|
||||
/* for init div clocks reg base*/
|
||||
static struct clk_divider *txlx_media_clk_divs[] = {
|
||||
&vdin_meas_div,
|
||||
&vpu_p0_div,
|
||||
&vpu_p1_div,
|
||||
&vapb_p0_div,
|
||||
&vapb_p1_div,
|
||||
&vpu_clkb_tmp_div,
|
||||
&vpu_clkb_div,
|
||||
&hdmirx_cfg_div,
|
||||
&hdmirx_modet_div,
|
||||
&hdmirx_audmeas_div,
|
||||
&hdmirx_acr_div,
|
||||
&hdcp22_skp_div,
|
||||
&hdcp22_esm_div,
|
||||
&vdec_p0_div,
|
||||
&vdec_p1_div,
|
||||
&hcodec_p0_div,
|
||||
&hcodec_p1_div,
|
||||
&hevc_p0_div,
|
||||
&hevc_p1_div,
|
||||
&cts_amclk_div,
|
||||
&cts_iec958_int_div,
|
||||
&cts_pdm_div,
|
||||
&cts_audin_mclk_div,
|
||||
&cts_audin_sclk_div,
|
||||
&cts_audin_lrclk_div,
|
||||
&cts_alocker_in_div,
|
||||
&cts_alocker_out_div,
|
||||
&cts_pcm_mclk_div,
|
||||
&cts_pcm_sclk_div,
|
||||
};
|
||||
|
||||
/* for init gate clocks reg base*/
|
||||
static struct clk_gate *txlx_media_clk_gates[] = {
|
||||
&vdin_meas_gate,
|
||||
&vpu_p0_gate,
|
||||
&vpu_p1_gate,
|
||||
&vapb_p0_gate,
|
||||
&vapb_p1_gate,
|
||||
&ge2d_gate,
|
||||
&vpu_clkb_tmp_gate,
|
||||
&vpu_clkb_gate,
|
||||
&hdmirx_cfg_gate,
|
||||
&hdmirx_modet_gate,
|
||||
&hdmirx_audmeas_gate,
|
||||
&hdmirx_acr_gate,
|
||||
&hdcp22_skp_gate,
|
||||
&hdcp22_esm_gate,
|
||||
&vdec_p0_gate,
|
||||
&vdec_p1_gate,
|
||||
&hcodec_p0_gate,
|
||||
&hcodec_p1_gate,
|
||||
&hevc_p0_gate,
|
||||
&hevc_p1_gate,
|
||||
&cts_amclk_gate,
|
||||
&cts_iec958_int_gate,
|
||||
&cts_pdm_gate,
|
||||
&cts_audin_mclk_gate,
|
||||
&cts_audin_sclk_gate,
|
||||
&cts_audin_lrclk_gate,
|
||||
&cts_alocker_in_gate,
|
||||
&cts_alocker_out_gate,
|
||||
&cts_pcm_mclk_gate,
|
||||
&cts_pcm_sclk_gate,
|
||||
};
|
||||
|
||||
static struct meson_composite m_composite[] = {
|
||||
{CLKID_VPU_CLKB_TMP_COMP, "vpu_clkb_tmp_composite",
|
||||
vpu_clkb_parent_names, ARRAY_SIZE(vpu_clkb_parent_names),
|
||||
&vpu_clkb_tmp_mux.hw, &vpu_clkb_tmp_div.hw,
|
||||
&vpu_clkb_tmp_gate.hw, 0
|
||||
},/*vpu_clkb_tmp*/
|
||||
|
||||
{CLKID_VPU_CLKB_COMP, "vpu_clkb_composite",
|
||||
vpu_clkb_nomux_parent_names, ARRAY_SIZE(vpu_clkb_nomux_parent_names),
|
||||
NULL, &vpu_clkb_div.hw, &vpu_clkb_gate.hw, 0
|
||||
},/*vpu_clkb*/
|
||||
|
||||
{CLKID_VDIN_MEAS_COMP, "vdin_meas_composite",
|
||||
meas_parent_names, ARRAY_SIZE(meas_parent_names),
|
||||
&vdin_meas_mux.hw, &vdin_meas_div.hw,
|
||||
&vdin_meas_gate.hw, 0
|
||||
},/*vdin_meas*/
|
||||
|
||||
{CLKID_VPU_P0_COMP, "vpu_p0_composite",
|
||||
vpu_parent_names, ARRAY_SIZE(vpu_parent_names),
|
||||
&vpu_p0_mux.hw, &vpu_p0_div.hw,
|
||||
&vpu_p0_gate.hw, 0
|
||||
},/* cts_vpu_clk p0*/
|
||||
|
||||
{CLKID_VPU_P1_COMP, "vpu_p1_composite",
|
||||
vpu_parent_names, ARRAY_SIZE(vpu_parent_names),
|
||||
&vpu_p1_mux.hw, &vpu_p1_div.hw,
|
||||
&vpu_p1_gate.hw, 0
|
||||
},
|
||||
|
||||
{CLKID_VAPB_P0_COMP, "vapb_p0_composite",
|
||||
vpu_parent_names, ARRAY_SIZE(vpu_parent_names),
|
||||
&vapb_p0_mux.hw, &vapb_p0_div.hw,
|
||||
&vapb_p0_gate.hw, 0
|
||||
},
|
||||
|
||||
{CLKID_VAPB_P1_COMP, "vapb_p1_composite",
|
||||
vpu_parent_names, ARRAY_SIZE(vpu_parent_names),
|
||||
&vapb_p1_mux.hw, &vapb_p1_div.hw,
|
||||
&vapb_p1_gate.hw, 0
|
||||
},
|
||||
|
||||
{CLKID_HDMIRX_CFG_COMP, "hdmirx_cfg_composite",
|
||||
hdmirx_parent_names, ARRAY_SIZE(hdmirx_parent_names),
|
||||
&hdmirx_cfg_mux.hw, &hdmirx_cfg_div.hw,
|
||||
&hdmirx_cfg_gate.hw, 0
|
||||
},
|
||||
|
||||
{CLKID_HDMIRX_MODET_COMP, "hdmirx_modet_composite",
|
||||
hdmirx_parent_names, ARRAY_SIZE(hdmirx_parent_names),
|
||||
&hdmirx_modet_mux.hw, &hdmirx_modet_div.hw,
|
||||
&hdmirx_modet_gate.hw, 0
|
||||
},
|
||||
|
||||
{CLKID_HDMIRX_AUDMEAS_COMP, "hdmirx_audmeas_composite",
|
||||
hdmirx_ref_parent_names, ARRAY_SIZE(hdmirx_ref_parent_names),
|
||||
&hdmirx_audmeas_mux.hw, &hdmirx_audmeas_div.hw,
|
||||
&hdmirx_audmeas_gate.hw, 0
|
||||
},
|
||||
|
||||
{CLKID_HDMIRX_ACR_COMP, "hdmirx_acr_composite",
|
||||
hdmirx_ref_parent_names, ARRAY_SIZE(hdmirx_ref_parent_names),
|
||||
&hdmirx_acr_mux.hw, &hdmirx_acr_div.hw,
|
||||
&hdmirx_acr_gate.hw, 0
|
||||
},
|
||||
|
||||
{CLKID_HDCP22_SKP_COMP, "hdcp22_skp_composite",
|
||||
hdcp22_skp_parent_names, ARRAY_SIZE(hdcp22_skp_parent_names),
|
||||
&hdcp22_skp_mux.hw, &hdcp22_skp_div.hw,
|
||||
&hdcp22_skp_gate.hw, 0
|
||||
},
|
||||
|
||||
{CLKID_HDCP22_ESM_COMP, "hdcp22_esm_composite",
|
||||
hdcp22_esm_parent_names, ARRAY_SIZE(hdcp22_esm_parent_names),
|
||||
&hdcp22_esm_mux.hw, &hdcp22_esm_div.hw,
|
||||
&hdcp22_esm_gate.hw, 0
|
||||
},
|
||||
|
||||
{CLKID_VDEC_P0_COMP, "vdec_p0_composite",
|
||||
dec_parent_names, ARRAY_SIZE(dec_parent_names),
|
||||
&vdec_p0_mux.hw, &vdec_p0_div.hw,
|
||||
&vdec_p0_gate.hw, 0
|
||||
},
|
||||
|
||||
{CLKID_VDEC_P1_COMP, "vdec_p1_composite",
|
||||
dec_parent_names, ARRAY_SIZE(dec_parent_names),
|
||||
&vdec_p1_mux.hw, &vdec_p1_div.hw,
|
||||
&vdec_p1_gate.hw, 0
|
||||
},
|
||||
|
||||
{CLKID_HCODEC_P0_COMP, "hcodec_p0_composite",
|
||||
dec_parent_names, ARRAY_SIZE(dec_parent_names),
|
||||
&hcodec_p0_mux.hw, &hcodec_p0_div.hw,
|
||||
&hcodec_p0_gate.hw, 0
|
||||
},
|
||||
|
||||
{CLKID_HCODEC_P1_COMP, "hcodec_p1_composite",
|
||||
dec_parent_names, ARRAY_SIZE(dec_parent_names),
|
||||
&hcodec_p1_mux.hw, &hcodec_p1_div.hw,
|
||||
&hcodec_p1_gate.hw, 0
|
||||
},
|
||||
|
||||
{CLKID_HEVC_P0_COMP, "hevc_p0_composite",
|
||||
dec_parent_names, ARRAY_SIZE(dec_parent_names),
|
||||
&hevc_p0_mux.hw, &hevc_p0_div.hw,
|
||||
&hevc_p0_gate.hw, 0
|
||||
},
|
||||
|
||||
{CLKID_HEVC_P1_COMP, "hevc_p1_composite",
|
||||
dec_parent_names, ARRAY_SIZE(dec_parent_names),
|
||||
&hevc_p1_mux.hw, &hevc_p1_div.hw,
|
||||
&hevc_p1_gate.hw, 0
|
||||
},
|
||||
|
||||
{CLKID_AMCLK_COMP, "cts_amclk_composite",
|
||||
cts_amclk_parent_names, ARRAY_SIZE(cts_amclk_parent_names),
|
||||
&cts_amclk_mux.hw, &cts_amclk_div.hw,
|
||||
&cts_amclk_gate.hw, 0
|
||||
},/* cts_amclk in clktress doc*/
|
||||
|
||||
{CLKID_IEC958_INT_COMP, "iec958_int_composite",
|
||||
cts_iec958_int_parent_names, ARRAY_SIZE(cts_iec958_int_parent_names),
|
||||
&cts_iec958_int_mux.hw, &cts_iec958_int_div.hw,
|
||||
&cts_iec958_int_gate.hw, 0
|
||||
},
|
||||
|
||||
{CLKID_PDM_COMP, "cts_pdm_composite",
|
||||
cts_pdm_parent_names, ARRAY_SIZE(cts_pdm_parent_names),
|
||||
&cts_pdm_mux.hw, &cts_pdm_div.hw,
|
||||
&cts_pdm_gate.hw, 0
|
||||
},/* cts_pdm in clktrees doc */
|
||||
|
||||
{CLKID_AUDIN_MCLK_COMP, "cts_audin_mclk_composite",
|
||||
cts_audin_mclk_parent_names, ARRAY_SIZE(cts_audin_mclk_parent_names),
|
||||
&cts_audin_mclk_mux.hw, &cts_audin_mclk_div.hw,
|
||||
&cts_audin_mclk_gate.hw, 0
|
||||
},/* cts_audin_mclk in clktrees doc */
|
||||
|
||||
{CLKID_AUDIN_SCLK_COMP, "cts_audin_sclk_composite",
|
||||
cts_audin_sclk_parent_names, ARRAY_SIZE(cts_audin_sclk_parent_names),
|
||||
NULL, &cts_audin_sclk_div.hw, &cts_audin_sclk_gate.hw, 0
|
||||
},/* cts_audin_sclk in clktrees doc */
|
||||
|
||||
{CLKID_AUDIN_LRCLK_COMP, "cts_audin_lrclk_composite",
|
||||
cts_audin_lrclk_parent_names, ARRAY_SIZE(cts_audin_lrclk_parent_names),
|
||||
NULL, &cts_audin_lrclk_div.hw, &cts_audin_lrclk_gate.hw, 0
|
||||
},/* cts_audin_lrclk in clktrees doc */
|
||||
|
||||
{CLKID_ALOCKER_IN_COMP, "cts_alocker_in_composite",
|
||||
cts_alocker_in_parent_names, ARRAY_SIZE(cts_alocker_in_parent_names),
|
||||
&cts_alocker_in_mux.hw, &cts_alocker_in_div.hw,
|
||||
&cts_alocker_in_gate.hw, 0
|
||||
},/* cts_alocker_in_clk in clktrees doc */
|
||||
|
||||
{CLKID_ALOCKER_OUT_COMP, "cts_alocker_out_composite",
|
||||
cts_alocker_out_parent_names, ARRAY_SIZE(cts_alocker_out_parent_names),
|
||||
&cts_alocker_out_mux.hw, &cts_alocker_out_div.hw,
|
||||
&cts_alocker_out_gate.hw, 0
|
||||
},/* cts_alocker_out_clk in clktrees doc */
|
||||
|
||||
{CLKID_PCM_MCLK_COMP, "cts_pcm_mclk_composite",
|
||||
cts_pcm_mclk_parent_names, ARRAY_SIZE(cts_pcm_mclk_parent_names),
|
||||
&cts_pcm_mclk_mux.hw, &cts_pcm_mclk_div.hw,
|
||||
&cts_pcm_mclk_gate.hw, 0
|
||||
},/* cts_pcm_mclk in clktrees doc */
|
||||
|
||||
{CLKID_PCM_SCLK_COMP, "cts_pcm_sclk_composite",
|
||||
cts_pcm_sclk_parent_names, ARRAY_SIZE(cts_pcm_sclk_parent_names),
|
||||
NULL, &cts_pcm_sclk_div.hw, &cts_pcm_sclk_gate.hw, 0
|
||||
},/* cts_pcm_sclk in clktrees doc */
|
||||
};
|
||||
|
||||
/* array for single hw*/
|
||||
static struct meson_hw m_hw[] = {
|
||||
{CLKID_VDEC_MUX, &vdec_mux.hw},
|
||||
{CLKID_HCODEC_MUX, &hcodec_mux.hw},
|
||||
{CLKID_HEVC_MUX, &hevc_mux.hw},
|
||||
};
|
||||
void meson_txlx_media_init(void)
|
||||
{
|
||||
int i;
|
||||
int length, lengthhw;
|
||||
|
||||
length = ARRAY_SIZE(m_composite);
|
||||
lengthhw = ARRAY_SIZE(m_hw);
|
||||
|
||||
/* Populate base address for media muxes */
|
||||
for (i = 0; i < ARRAY_SIZE(txlx_media_clk_muxes); i++)
|
||||
txlx_media_clk_muxes[i]->reg = clk_base +
|
||||
(u64)txlx_media_clk_muxes[i]->reg;
|
||||
|
||||
/* Populate base address for media divs */
|
||||
for (i = 0; i < ARRAY_SIZE(txlx_media_clk_divs); i++)
|
||||
txlx_media_clk_divs[i]->reg = clk_base +
|
||||
(u64)txlx_media_clk_divs[i]->reg;
|
||||
|
||||
/* Populate base address for media gates */
|
||||
for (i = 0; i < ARRAY_SIZE(txlx_media_clk_gates); i++)
|
||||
txlx_media_clk_gates[i]->reg = clk_base +
|
||||
(u64)txlx_media_clk_gates[i]->reg;
|
||||
|
||||
meson_clk_register_composite(clks, m_composite, length);
|
||||
|
||||
clks[CLKID_VPU_MUX] = clk_register(NULL, &vpu_mux.hw);
|
||||
WARN_ON(IS_ERR(clks[CLKID_VPU_MUX]));
|
||||
clk_prepare_enable(clks[CLKID_VPU_MUX]);
|
||||
|
||||
clks[CLKID_VAPB_MUX] = clk_register(NULL, &vapb_mux.hw);
|
||||
WARN_ON(IS_ERR(clks[CLKID_VAPB_MUX]));
|
||||
clk_prepare_enable(clks[CLKID_VAPB_MUX]);
|
||||
|
||||
clks[CLKID_GE2D_GATE] = clk_register(NULL, &ge2d_gate.hw);
|
||||
WARN_ON(IS_ERR(clks[CLKID_GE2D_GATE]));
|
||||
|
||||
/*mux*/
|
||||
clks[CLKID_VDEC_MUX] = clk_register(NULL, &vdec_mux.hw);
|
||||
WARN_ON(IS_ERR(clks[CLKID_VDEC_MUX]));
|
||||
|
||||
clks[CLKID_HCODEC_MUX] = clk_register(NULL, &hcodec_mux.hw);
|
||||
WARN_ON(IS_ERR(clks[CLKID_HCODEC_MUX]));
|
||||
|
||||
clks[CLKID_HEVC_MUX] = clk_register(NULL, &hevc_mux.hw);
|
||||
WARN_ON(IS_ERR(clks[CLKID_HEVC_MUX]));
|
||||
|
||||
clks[CLKID_IEC958_MUX] = clk_register(NULL, &cts_iec958_spdif.hw);
|
||||
WARN_ON(IS_ERR(clks[CLKID_IEC958_MUX]));
|
||||
}
|
||||
73
drivers/amlogic/clk/txlx/txlx_clk_sdemmc.c
Normal file
73
drivers/amlogic/clk/txlx/txlx_clk_sdemmc.c
Normal file
@@ -0,0 +1,73 @@
|
||||
/*
|
||||
* drivers/amlogic/clk/txlx/txlx_clk_sdemmc.c
|
||||
*
|
||||
* Copyright (C) 2017 Amlogic, Inc. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*/
|
||||
|
||||
#include <linux/clk.h>
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/slab.h>
|
||||
#include <dt-bindings/clock/amlogic,txlx-clkc.h>
|
||||
|
||||
#include "../clkc.h"
|
||||
#include "txlx.h"
|
||||
|
||||
PNAME(sd_emmc_parent_names) = { "xtal", "fclk_div2",
|
||||
"fclk_div3", "fclk_div5", "fclk_div7", "mpll2", "mpll3", "gp0" };
|
||||
/*sd_emmc B*/
|
||||
static MUX(sd_emmc_p0_mux_B, HHI_NAND_CLK_CNTL, 0x7, 25,
|
||||
sd_emmc_parent_names, CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED);
|
||||
static DIV(sd_emmc_p0_div_B, HHI_NAND_CLK_CNTL, 16, 7, "sd_emmc_p0_mux_B",
|
||||
CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED);
|
||||
static GATE(sd_emmc_p0_gate_B, HHI_NAND_CLK_CNTL, 23, "sd_emmc_p0_div_B",
|
||||
CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED);
|
||||
/*sd_emmc C*/
|
||||
static MUX(sd_emmc_p0_mux_C, HHI_NAND_CLK_CNTL, 0x7, 9,
|
||||
sd_emmc_parent_names, CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED);
|
||||
static DIV(sd_emmc_p0_div_C, HHI_NAND_CLK_CNTL, 0, 7, "sd_emmc_p0_mux_C",
|
||||
CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED);
|
||||
static GATE(sd_emmc_p0_gate_C, HHI_NAND_CLK_CNTL, 7, "sd_emmc_p0_div_C",
|
||||
CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED);
|
||||
|
||||
static struct meson_composite sdemmc_comp[] = {
|
||||
{CLKID_SD_EMMC_B_P0_COMP, "sd_emmc_p0_B_comp",
|
||||
sd_emmc_parent_names, ARRAY_SIZE(sd_emmc_parent_names),
|
||||
&sd_emmc_p0_mux_B.hw, &sd_emmc_p0_div_B.hw,
|
||||
&sd_emmc_p0_gate_B.hw, 0
|
||||
},/* sd_emmc_B */
|
||||
|
||||
{CLKID_SD_EMMC_C_P0_COMP, "sd_emmc_p0_C_comp",
|
||||
sd_emmc_parent_names, ARRAY_SIZE(sd_emmc_parent_names),
|
||||
&sd_emmc_p0_mux_C.hw, &sd_emmc_p0_div_C.hw,
|
||||
&sd_emmc_p0_gate_C.hw, 0
|
||||
},/* sd_emmc_C */
|
||||
};
|
||||
|
||||
void meson_txlx_sdemmc_init(void)
|
||||
{
|
||||
int length = ARRAY_SIZE(sdemmc_comp);
|
||||
|
||||
/* Populate base address for reg */
|
||||
sd_emmc_p0_mux_B.reg = clk_base + (u64)(sd_emmc_p0_mux_B.reg);
|
||||
sd_emmc_p0_div_B.reg = clk_base + (u64)(sd_emmc_p0_div_B.reg);
|
||||
sd_emmc_p0_gate_B.reg = clk_base + (u64)(sd_emmc_p0_gate_B.reg);
|
||||
sd_emmc_p0_mux_C.reg = clk_base + (u64)(sd_emmc_p0_mux_C.reg);
|
||||
sd_emmc_p0_div_C.reg = clk_base + (u64)(sd_emmc_p0_div_C.reg);
|
||||
sd_emmc_p0_gate_C.reg = clk_base + (u64)(sd_emmc_p0_gate_C.reg);
|
||||
|
||||
meson_clk_register_composite(clks, sdemmc_comp, length);
|
||||
}
|
||||
280
include/dt-bindings/clock/amlogic,txlx-clkc.h
Normal file
280
include/dt-bindings/clock/amlogic,txlx-clkc.h
Normal file
@@ -0,0 +1,280 @@
|
||||
/*
|
||||
* include/dt-bindings/clock/txlx-clkc.h
|
||||
*
|
||||
* Copyright (C) 2017 Amlogic, Inc. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __TXLX_CLKC_H
|
||||
#define __TXLX_CLKC_H
|
||||
|
||||
/*
|
||||
* CLKID index values
|
||||
*/
|
||||
#define CLKID_SYS_PLL 0
|
||||
#define CLKID_FIXED_PLL 1
|
||||
#define CLKID_FCLK_DIV2 2
|
||||
#define CLKID_FCLK_DIV3 3
|
||||
#define CLKID_FCLK_DIV4 4
|
||||
#define CLKID_FCLK_DIV5 5
|
||||
#define CLKID_FCLK_DIV7 6
|
||||
#define CLKID_GP0_PLL 7
|
||||
#define CLKID_GP1_PLL 8
|
||||
#define CLKID_MPEG_SEL 9
|
||||
#define CLKID_MPEG_DIV 10
|
||||
#define CLKID_CLK81 11
|
||||
#define CLKID_MPLL0 12
|
||||
#define CLKID_MPLL1 13
|
||||
#define CLKID_MPLL2 14
|
||||
#define CLKID_MPLL3 15
|
||||
#define CLKID_CPU_FCLK_P00 16
|
||||
#define CLKID_CPU_FCLK_P01 17
|
||||
#define CLKID_CPU_FCLK_P0 18
|
||||
#define CLKID_CPU_FCLK_P10 19
|
||||
#define CLKID_CPU_FCLK_P11 20
|
||||
#define CLKID_CPU_FCLK_P1 21
|
||||
#define CLKID_CPU_FCLK_P 22
|
||||
#define CLKID_CPU_CLK 23
|
||||
/*#define CLKID_ADC_PLL 24*/
|
||||
|
||||
/*HHI_GCLK_MPEG0: 0x50*/
|
||||
#define GATE_BASE0 (25 - 1)
|
||||
|
||||
#define CLKID_DDR (GATE_BASE0 + 0)
|
||||
#define CLKID_DOS (GATE_BASE0 + 1)
|
||||
#define CLKID_AUDIO_LOCKER (GATE_BASE0 + 2)
|
||||
#define CLKID_ISA (GATE_BASE0 + 3)
|
||||
#define CLKID_PL301 (GATE_BASE0 + 4)
|
||||
#define CLKID_PERIPHS (GATE_BASE0 + 5)
|
||||
#define CLKID_SPICC0 (GATE_BASE0 + 6)
|
||||
#define CLKID_I2C (GATE_BASE0 + 7)
|
||||
#define CLKID_SANA (GATE_BASE0 + 8)
|
||||
#define CLKID_SMART_CARD (GATE_BASE0 + 9)
|
||||
#define CLKID_RNG0 (GATE_BASE0 + 10)
|
||||
#define CLKID_UART0 (GATE_BASE0 + 11)
|
||||
#define CLKID_SPICC1 (GATE_BASE0 + 12)
|
||||
#define CLKID_STREAM (GATE_BASE0 + 13)
|
||||
#define CLKID_ASYNC_FIFO (GATE_BASE0 + 14)
|
||||
#define CLKID_HIU_REG (GATE_BASE0 + 15)
|
||||
#define CLKID_HDMIRX_APB (GATE_BASE0 + 16)
|
||||
#define CLKID_ASSIST_MISC (GATE_BASE0 + 17)
|
||||
#define CLKID_SD_EMMC_B (GATE_BASE0 + 18)
|
||||
#define CLKID_SD_EMMC_C (GATE_BASE0 + 19)
|
||||
#define CLKID_DMA (GATE_BASE0 + 20)
|
||||
#define CLKID_ACODEC (GATE_BASE0 + 21)
|
||||
#define CLKID_ATV_DEMOD (GATE_BASE0 + 22)
|
||||
#define CLKID_SPI (GATE_BASE0 + 23)
|
||||
#define CLKID_ADEC (GATE_BASE0 + 24)
|
||||
|
||||
/*HHI_GCLK_MPEG1: 0x51*/
|
||||
/*above: 25+25*/
|
||||
#define GATE_BASE1 (GATE_BASE0 + 25)
|
||||
|
||||
#define CLKID_PCLK_TVFE (GATE_BASE1 + 0)
|
||||
#define CLKID_I2S_SPDIF (GATE_BASE1 + 1)
|
||||
#define CLKID_ETH_CORE (GATE_BASE1 + 2)
|
||||
#define CLKID_DEMUX (GATE_BASE1 + 3)
|
||||
#define CLKID_AIU_GLUE (GATE_BASE1 + 4)
|
||||
#define CLKID_IEC958 (GATE_BASE1 + 5)
|
||||
#define CLKID_I2S_OUT (GATE_BASE1 + 6)
|
||||
#define CLKID_AMCLK_MEASURE (GATE_BASE1 + 7)
|
||||
#define CLKID_AIFIFO2 (GATE_BASE1 + 8)
|
||||
#define CLKID_MIXER (GATE_BASE1 + 9)
|
||||
#define CLKID_MIXER_IFACE (GATE_BASE1 + 10)
|
||||
#define CLKID_ADC (GATE_BASE1 + 11)
|
||||
#define CLKID_AIU_TOP (GATE_BASE1 + 12)
|
||||
#define CLKID_UART1 (GATE_BASE1 + 13)
|
||||
#define CLKID_G2D (GATE_BASE1 + 14)
|
||||
#define CLKID_RESET (GATE_BASE1 + 15)
|
||||
#define CLKID_DOS_PARSER (GATE_BASE1 + 16)
|
||||
#define CLKID_USB_GENERAL (GATE_BASE1 + 17)
|
||||
#define CLKID_AHB_ARB0 (GATE_BASE1 + 18)
|
||||
#define CLKID_EFUSE (GATE_BASE1 + 19)
|
||||
#define CLKID_BOOT_ROM (GATE_BASE1 + 20)
|
||||
|
||||
/*HHI_GCLK_MPEG2: 0x52*/
|
||||
/*above: 25+25+21*/
|
||||
#define GATE_BASE2 (GATE_BASE1 + 21)
|
||||
|
||||
#define CLKID_AHB_DATA_BUS (GATE_BASE2 + 0)
|
||||
#define CLKID_AHB_CTRL_BUS (GATE_BASE2 + 1)
|
||||
#define CLKID_HDCP22_PCLK (GATE_BASE2 + 2)
|
||||
#define CLKID_HDMITX_PCLK (GATE_BASE2 + 3)
|
||||
#define CLKID_USB1_TO_DDR (GATE_BASE2 + 4)
|
||||
#define CLKID_MMC_PCLK (GATE_BASE2 + 5)
|
||||
#define CLKID_HDMI_HDCP22 (GATE_BASE2 + 6)
|
||||
#define CLKID_UART2 (GATE_BASE2 + 7)
|
||||
#define CLKID_VPU_INTR (GATE_BASE2 + 8)
|
||||
#define CLKID_SEC_AHB_AHB3_BRIDGE (GATE_BASE2 + 9)
|
||||
#define CLKID_DEMOD_TVFE (GATE_BASE2 + 10)
|
||||
#define CLKID_GIC (GATE_BASE2 + 11)
|
||||
|
||||
/*HHI_GCLK_OTHER: 0x55*/
|
||||
/*above: 25+25+21+12*/
|
||||
#define GATE_OTHER (GATE_BASE2 + 12)
|
||||
|
||||
#define CLKID_VCLK2_VENCI0 (GATE_OTHER + 0)
|
||||
#define CLKID_VCLK2_VENCI1 (GATE_OTHER + 1)
|
||||
#define CLKID_VCLK2_VENCP0 (GATE_OTHER + 2)
|
||||
#define CLKID_VCLK2_VENCP1 (GATE_OTHER + 3)
|
||||
#define CLKID_VCLK2_VENCT0 (GATE_OTHER + 4)
|
||||
#define CLKID_VCLK2_VENCT1 (GATE_OTHER + 5)
|
||||
#define CLKID_VCLK2_OTHER (GATE_OTHER + 6)
|
||||
#define CLKID_VCLK2_ENCI (GATE_OTHER + 7)
|
||||
#define CLKID_VCLK2_ENCP (GATE_OTHER + 8)
|
||||
#define CLKID_DAC_CLK (GATE_OTHER + 9)
|
||||
#define CLKID_AOCLK_GATE (GATE_OTHER + 10)
|
||||
#define CLKID_IEC958_GATE (GATE_OTHER + 11)
|
||||
#define CLKID_ENC480P (GATE_OTHER + 12)
|
||||
#define CLKID_RNG1 (GATE_OTHER + 13)
|
||||
#define CLKID_VCLK2_ENCT (GATE_OTHER + 14)
|
||||
#define CLKID_VCLK2_ENCL (GATE_OTHER + 15)
|
||||
#define CLKID_VCLK2_VENCLMMC (GATE_OTHER + 16)
|
||||
#define CLKID_VCLK2_VENCL (GATE_OTHER + 17)
|
||||
#define CLKID_VCLK2_OTHER1 (GATE_OTHER + 18)
|
||||
|
||||
/*HHI_GCLK_OTHER: 0x55*/
|
||||
/*above: 25+25+21+12+19*/
|
||||
#define GATE_AO_BASE (GATE_OTHER + 19)
|
||||
|
||||
#define CLKID_AO_MEDIA_CPU (GATE_AO_BASE + 0)
|
||||
#define CLKID_AO_AHB_SRAM (GATE_AO_BASE + 1)
|
||||
#define CLKID_AO_AHB_BUS (GATE_AO_BASE + 2)
|
||||
#define CLKID_AO_IFACE (GATE_AO_BASE + 3)
|
||||
#define CLKID_AO_I2C (GATE_AO_BASE + 4)
|
||||
|
||||
/*above: 25+25+21+12+19+5=107*/
|
||||
#define CLOCK_GATE (GATE_AO_BASE + 5)
|
||||
|
||||
#define CLKID_SD_EMMC_B_P0_MUX (CLOCK_GATE + 0)
|
||||
#define CLKID_SD_EMMC_B_P0_DIV (CLOCK_GATE + 1)
|
||||
#define CLKID_SD_EMMC_B_P0_GATE (CLOCK_GATE + 2)
|
||||
#define CLKID_SD_EMMC_B_P0_COMP (CLOCK_GATE + 3)
|
||||
#define CLKID_SD_EMMC_C_P0_MUX (CLOCK_GATE + 4)
|
||||
#define CLKID_SD_EMMC_C_P0_DIV (CLOCK_GATE + 5)
|
||||
#define CLKID_SD_EMMC_C_P0_GATE (CLOCK_GATE + 6)
|
||||
#define CLKID_SD_EMMC_C_P0_COMP (CLOCK_GATE + 7)
|
||||
#define CLKID_SD_EMMC_B_MUX (CLOCK_GATE + 8)
|
||||
#define CLKID_SD_EMMC_B_DIV (CLOCK_GATE + 9)
|
||||
#define CLKID_SD_EMMC_B_GATE (CLOCK_GATE + 10)
|
||||
#define CLKID_SD_EMMC_B_COMP (CLOCK_GATE + 11)
|
||||
#define CLKID_SD_EMMC_C_MUX (CLOCK_GATE + 12)
|
||||
#define CLKID_SD_EMMC_C_DIV (CLOCK_GATE + 13)
|
||||
#define CLKID_SD_EMMC_C_GATE (CLOCK_GATE + 14)
|
||||
#define CLKID_SD_EMMC_C_COMP (CLOCK_GATE + 15)
|
||||
|
||||
/*above: 25+25+21+12+19+5+16*/
|
||||
#define CLKID_MEDIA_BASE (CLOCK_GATE + 16)
|
||||
|
||||
#define CLKID_VPU_P0_MUX (CLKID_MEDIA_BASE + 0)
|
||||
#define CLKID_VPU_P0_DIV (CLKID_MEDIA_BASE + 1)
|
||||
#define CLKID_VPU_P0_GATE (CLKID_MEDIA_BASE + 2)
|
||||
#define CLKID_VPU_P0_COMP (CLKID_MEDIA_BASE + 3)
|
||||
#define CLKID_VPU_P1_MUX (CLKID_MEDIA_BASE + 4)
|
||||
#define CLKID_VPU_P1_DIV (CLKID_MEDIA_BASE + 5)
|
||||
#define CLKID_VPU_P1_GATE (CLKID_MEDIA_BASE + 6)
|
||||
#define CLKID_VPU_P1_COMP (CLKID_MEDIA_BASE + 7)
|
||||
#define CLKID_VPU_MUX (CLKID_MEDIA_BASE + 8)
|
||||
#define CLKID_VAPB_P0_MUX (CLKID_MEDIA_BASE + 9)
|
||||
#define CLKID_VAPB_P0_DIV (CLKID_MEDIA_BASE + 10)
|
||||
#define CLKID_VAPB_P0_GATE (CLKID_MEDIA_BASE + 11)
|
||||
#define CLKID_VAPB_P0_COMP (CLKID_MEDIA_BASE + 12)
|
||||
#define CLKID_VAPB_P1_MUX (CLKID_MEDIA_BASE + 13)
|
||||
#define CLKID_VAPB_P1_DIV (CLKID_MEDIA_BASE + 14)
|
||||
#define CLKID_VAPB_P1_GATE (CLKID_MEDIA_BASE + 15)
|
||||
#define CLKID_VAPB_P1_COMP (CLKID_MEDIA_BASE + 16)
|
||||
#define CLKID_VAPB_MUX (CLKID_MEDIA_BASE + 17)
|
||||
#define CLKID_GE2D_GATE (CLKID_MEDIA_BASE + 18)
|
||||
#define CLKID_VDIN_MEAS_MUX (CLKID_MEDIA_BASE + 19)
|
||||
#define CLKID_VDIN_MEAS_DIV (CLKID_MEDIA_BASE + 20)
|
||||
#define CLKID_VDIN_MEAS_GATE (CLKID_MEDIA_BASE + 21)
|
||||
#define CLKID_VDIN_MEAS_COMP (CLKID_MEDIA_BASE + 22)
|
||||
|
||||
#define CLKID_VPU_CLKB_TMP_MUX (CLKID_MEDIA_BASE + 23)
|
||||
#define CLKID_VPU_CLKB_TMP_DIV (CLKID_MEDIA_BASE + 24)
|
||||
#define CLKID_VPU_CLKB_TMP_GATE (CLKID_MEDIA_BASE + 25)
|
||||
#define CLKID_VPU_CLKB_DIV (CLKID_MEDIA_BASE + 26)
|
||||
#define CLKID_VPU_CLKB_GATE (CLKID_MEDIA_BASE + 27)
|
||||
#define CLKID_VPU_CLKB_TMP_COMP (CLKID_MEDIA_BASE + 28)
|
||||
#define CLKID_VPU_CLKB_COMP (CLKID_MEDIA_BASE + 29)
|
||||
|
||||
#define CLKID_HDMIRX_BASE (CLKID_MEDIA_BASE + 30)
|
||||
|
||||
#define CLKID_HDMIRX_CFG_COMP (CLKID_HDMIRX_BASE + 0)
|
||||
#define CLKID_HDMIRX_MODET_COMP (CLKID_HDMIRX_BASE + 1)
|
||||
#define CLKID_HDMIRX_AUDMEAS_COMP (CLKID_HDMIRX_BASE + 2)
|
||||
#define CLKID_HDMIRX_ACR_COMP (CLKID_HDMIRX_BASE + 3)
|
||||
#define CLKID_HDCP22_SKP_COMP (CLKID_HDMIRX_BASE + 4)
|
||||
#define CLKID_HDCP22_ESM_COMP (CLKID_HDMIRX_BASE + 5)
|
||||
|
||||
#define CLKID_VHDEC_BASE (CLKID_HDMIRX_BASE + 6)
|
||||
|
||||
#define CLKID_VDEC_P0_MUX (CLKID_VHDEC_BASE + 0)
|
||||
#define CLKID_VDEC_P0_DIV (CLKID_VHDEC_BASE + 1)
|
||||
#define CLKID_VDEC_P0_GATE (CLKID_VHDEC_BASE + 2)
|
||||
#define CLKID_VDEC_P0_COMP (CLKID_VHDEC_BASE + 3)
|
||||
#define CLKID_VDEC_P1_MUX (CLKID_VHDEC_BASE + 4)
|
||||
#define CLKID_VDEC_P1_DIV (CLKID_VHDEC_BASE + 5)
|
||||
#define CLKID_VDEC_P1_GATE (CLKID_VHDEC_BASE + 6)
|
||||
#define CLKID_VDEC_P1_COMP (CLKID_VHDEC_BASE + 7)
|
||||
#define CLKID_HCODEC_P0_MUX (CLKID_VHDEC_BASE + 8)
|
||||
#define CLKID_HCODEC_P0_DIV (CLKID_VHDEC_BASE + 9)
|
||||
#define CLKID_HCODEC_P0_GATE (CLKID_VHDEC_BASE + 10)
|
||||
#define CLKID_HCODEC_P0_COMP (CLKID_VHDEC_BASE + 11)
|
||||
#define CLKID_HCODEC_P1_MUX (CLKID_VHDEC_BASE + 12)
|
||||
#define CLKID_HCODEC_P1_DIV (CLKID_VHDEC_BASE + 13)
|
||||
#define CLKID_HCODEC_P1_GATE (CLKID_VHDEC_BASE + 14)
|
||||
#define CLKID_HCODEC_P1_COMP (CLKID_VHDEC_BASE + 15)
|
||||
#define CLKID_HEVC_P0_MUX (CLKID_VHDEC_BASE + 16)
|
||||
#define CLKID_HEVC_P0_DIV (CLKID_VHDEC_BASE + 17)
|
||||
#define CLKID_HEVC_P0_GATE (CLKID_VHDEC_BASE + 18)
|
||||
#define CLKID_HEVC_P0_COMP (CLKID_VHDEC_BASE + 19)
|
||||
#define CLKID_HEVC_P1_MUX (CLKID_VHDEC_BASE + 20)
|
||||
#define CLKID_HEVC_P1_DIV (CLKID_VHDEC_BASE + 21)
|
||||
#define CLKID_HEVC_P1_GATE (CLKID_VHDEC_BASE + 22)
|
||||
#define CLKID_HEVC_P1_COMP (CLKID_VHDEC_BASE + 23)
|
||||
#define CLKID_VDEC_MUX (CLKID_VHDEC_BASE + 24)
|
||||
#define CLKID_HCODEC_MUX (CLKID_VHDEC_BASE + 25)
|
||||
#define CLKID_HEVC_MUX (CLKID_VHDEC_BASE + 26)
|
||||
|
||||
#define CLKID_AUDIO_BASE (CLKID_VHDEC_BASE + 27)
|
||||
|
||||
#define CLKID_AMCLK_COMP (CLKID_AUDIO_BASE + 0)
|
||||
#define CLKID_IEC958_INT_COMP (CLKID_AUDIO_BASE + 1)
|
||||
#define CLKID_IEC958_MUX (CLKID_AUDIO_BASE + 2)
|
||||
#define CLKID_PDM_COMP (CLKID_AUDIO_BASE + 3)
|
||||
#define CLKID_AUDIN_MCLK_COMP (CLKID_AUDIO_BASE + 4)
|
||||
#define CLKID_AUDIN_SCLK_COMP (CLKID_AUDIO_BASE + 5)
|
||||
#define CLKID_AUDIN_LRCLK_COMP (CLKID_AUDIO_BASE + 6)
|
||||
#define CLKID_ALOCKER_IN_COMP (CLKID_AUDIO_BASE + 7)
|
||||
#define CLKID_ALOCKER_OUT_COMP (CLKID_AUDIO_BASE + 8)
|
||||
#define CLKID_PCM_MCLK_COMP (CLKID_AUDIO_BASE + 9)
|
||||
#define CLKID_PCM_SCLK_COMP (CLKID_AUDIO_BASE + 10)
|
||||
|
||||
#define CLKID_GPU_BASE (CLKID_AUDIO_BASE + 11)
|
||||
|
||||
#define CLKID_GPU_P0_COMP (CLKID_GPU_BASE + 0)
|
||||
#define CLKID_GPU_P1_COMP (CLKID_GPU_BASE + 1)
|
||||
#define CLKID_GPU_MUX (CLKID_GPU_BASE + 2)
|
||||
|
||||
/*above: 25+25+21+12+19+5+16+30*/
|
||||
#define CLKID_AO_BASE (CLKID_GPU_BASE + 3)
|
||||
#define CLKID_AO_CLK81 (CLKID_AO_BASE + 0)
|
||||
#define CLKID_SARADC_MUX (CLKID_AO_BASE + 1)
|
||||
#define CLKID_SARADC_DIV (CLKID_AO_BASE + 2)
|
||||
#define CLKID_SARADC_GATE (CLKID_AO_BASE + 3)
|
||||
|
||||
/*above: 25+25+21+12+19+5+16+30+6+4 +27 +11 +3=204*/
|
||||
|
||||
#define NR_CLKS (CLKID_AO_BASE + 4)
|
||||
#endif /* __TXLX_CLKC_H */
|
||||
Reference in New Issue
Block a user