diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
index 1cd8f2f120f0..35e456b46f72 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
@@ -3370,6 +3370,7 @@
 		rockchip,taskqueue-node = <7>;
 		rockchip,task-capacity = <8>;
 		power-domains = <&power RK3588_PD_VENC0>;
+		operating-points-v2 = <&venc_opp_table>;
 		status = "disabled";
 	};
 
@@ -3408,6 +3409,7 @@
 		rockchip,taskqueue-node = <7>;
 		rockchip,task-capacity = <8>;
 		power-domains = <&power RK3588_PD_VENC1>;
+		operating-points-v2 = <&venc_opp_table>;
 		status = "disabled";
 	};
 
@@ -3427,6 +3429,38 @@
 		status = "disabled";
 	};
 
+	venc_opp_table: venc-opp-table {
+		compatible = "operating-points-v2";
+
+		nvmem-cells = <&codec_leakage>;
+		nvmem-cell-names = "leakage";
+		rockchip,leakage-voltage-sel = <
+			1	8	0
+			9	20	1
+			21	254	2
+		>;
+
+		rockchip,grf = <&sys_grf>;
+		volt-mem-read-margin = <
+			855000	1
+			765000	2
+			675000	3
+			495000	4
+		>;
+
+		opp-800000000 {
+			opp-hz = /bits/ 64 <800000000>;
+			opp-microvolt = <750000 750000 850000>,
+					<750000 750000 850000>;
+			opp-microvolt-L0 = <800000 800000 850000>,
+					   <800000 800000 850000>;
+			opp-microvolt-L1 = <775000 775000 850000>,
+					   <775000 775000 850000>;
+			opp-microvolt-L2 = <750000 750000 850000>,
+					   <750000 750000 850000>;
+		};
+	};
+
 	rkvdec_ccu: rkvdec-ccu@fdc30000 {
 		compatible = "rockchip,rkv-decoder-v2-ccu";
 		reg = <0x0 0xfdc30000 0x0 0x100>;