From 719446d5ffa67fb9864a9bb95f5e28da1226c9ba Mon Sep 17 00:00:00 2001 From: Allon Huang Date: Wed, 3 Mar 2021 10:14:09 +0800 Subject: [PATCH] media: rockchip: cif: fix rk356x dvp pclk polarity Signed-off-by: Allon Huang Change-Id: Ia5a41bf7b428c61d4b79911a88f9b93928de0ac6 Signed-off-by: Zefa Chen --- drivers/media/platform/rockchip/cif/regs.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/media/platform/rockchip/cif/regs.h b/drivers/media/platform/rockchip/cif/regs.h index 4954cb34fe63..28f6f4240735 100644 --- a/drivers/media/platform/rockchip/cif/regs.h +++ b/drivers/media/platform/rockchip/cif/regs.h @@ -596,7 +596,7 @@ enum cif_reg_index { #define CIF_SAMPLING_EDGE_SINGLE (0x01000000) #define CIF_PCLK_DELAY_NUM(num) (0x00ff0000 | ((num) & 0xff)) #define CIF_GRF_VI_CON0 (0x340) -#define RK3568_CIF_PCLK_SAMPLING_EDGE_RISING (0x10001000) -#define RK3568_CIF_PCLK_SAMPLING_EDGE_FALLING (0x10000000) +#define RK3568_CIF_PCLK_SAMPLING_EDGE_RISING (0x10000000) +#define RK3568_CIF_PCLK_SAMPLING_EDGE_FALLING (0x10001000) #endif