From 71d6553e2f2a8ff2a14576ae5c7923e3f612a481 Mon Sep 17 00:00:00 2001
From: Sugar Zhang <sugar.zhang@rock-chips.com>
Date: Wed, 19 Mar 2025 15:01:17 +0800
Subject: [PATCH] arm64: dts: rockchip: rv1126b: Add sai clk device nodes

Mark it disabled default.

Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: If929206b5d987737b74baf5b49eebc3dcc7fac2f
---
 arch/arm64/boot/dts/rockchip/rv1126b.dtsi | 81 +++++++++++++++++++++++
 1 file changed, 81 insertions(+)

diff --git a/arch/arm64/boot/dts/rockchip/rv1126b.dtsi b/arch/arm64/boot/dts/rockchip/rv1126b.dtsi
index 641b1d1f165b..74b0af753f15 100644
--- a/arch/arm64/boot/dts/rockchip/rv1126b.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rv1126b.dtsi
@@ -62,6 +62,54 @@
 		#size-cells = <1>;
 		ranges;
 
+		sai0_mclkin: sai0-mclkin {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <0>;
+			clock-output-names = "mclk_sai0_from_io";
+			status = "disabled";
+		};
+
+		sai1_mclkin: sai1-mclkin {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <0>;
+			clock-output-names = "mclk_sai1_from_io";
+			status = "disabled";
+		};
+
+		sai2_mclkin: sai2-mclkin {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <0>;
+			clock-output-names = "mclk_sai2_from_io";
+			status = "disabled";
+		};
+
+		sai0_sclkin: sai0-sclkin {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <0>;
+			clock-output-names = "sclk_sai0_from_io";
+			status = "disabled";
+		};
+
+		sai1_sclkin: sai1-sclkin {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <0>;
+			clock-output-names = "sclk_sai1_from_io";
+			status = "disabled";
+		};
+
+		sai2_sclkin: sai2-sclkin {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <0>;
+			clock-output-names = "sclk_sai2_from_io";
+			status = "disabled";
+		};
+
 		xin32k: xin32k {
 			compatible = "fixed-clock";
 			#clock-cells = <0>;
@@ -82,6 +130,39 @@
 			clock-frequency = <96000000>;
 			clock-output-names = "clk_rcosc";
 		};
+
+		sai0_mclkout: sai0-mclkout@20100048 {
+			compatible = "rockchip,clk-out";
+			reg = <0x20100048 0x4>;
+			clocks = <&cru MCLK_SAI0_OUT2IO>;
+			#clock-cells = <0>;
+			clock-output-names = "mclk_sai0_to_io";
+			rockchip,bit-shift = <0>;
+			rockchip,bit-set-to-disable;
+			status = "disabled";
+		};
+
+		sai1_mclkout: sai1-mclkout@20100048 {
+			compatible = "rockchip,clk-out";
+			reg = <0x20100048 0x4>;
+			clocks = <&cru MCLK_SAI1_OUT2IO>;
+			#clock-cells = <0>;
+			clock-output-names = "mclk_sai1_to_io";
+			rockchip,bit-shift = <1>;
+			rockchip,bit-set-to-disable;
+			status = "disabled";
+		};
+
+		sai2_mclkout: sai2-mclkout@20100048 {
+			compatible = "rockchip,clk-out";
+			reg = <0x20100048 0x4>;
+			clocks = <&cru MCLK_SAI2_OUT2IO>;
+			#clock-cells = <0>;
+			clock-output-names = "mclk_sai2_to_io";
+			rockchip,bit-shift = <2>;
+			rockchip,bit-set-to-disable;
+			status = "disabled";
+		};
 	};
 
 	cpus {