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arm64: dts: rockchip: rk3399-android: fix clk_cif_pll use wrong clk

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Change-Id: I66e04ede6b528a0b016171ab05363e8a74d9ec0b
Signed-off-by: Chaoqing Xu <shawn.xu@rock-chips.com>
This commit is contained in:
Chaoqing Xu
2019-02-25 17:59:45 +08:00
committed by Tao Huang
parent af40bf2604
commit 7229af9d0c
1 changed files with 5 additions and 2 deletions
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7
arch/arm64/boot/dts/rockchip/rk3399-android.dtsi
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@@ -170,8 +170,11 @@
compatible = "rockchip,rk3399-isp", "rockchip,isp";
reg = <0x0 0xff910000 0x0 0x4000>;
interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH 0>;
assigned-clocks = <&cru SCLK_CIF_OUT_SRC>;
assigned-clock-parents = <&cru PLL_GPLL>;
assigned-clock-rates = <800000000>;
clocks =
<&cru SCLK_CIF_OUT>, <&cru SCLK_CIF_OUT>,
<&cru SCLK_CIF_OUT>, <&cru SCLK_CIF_OUT_SRC>,
<&cru SCLK_DPHY_TX1RX1_CFG>, <&cru SCLK_MIPIDPHY_REF>,
<&cru ACLK_ISP0_NOC>, <&cru ACLK_ISP0_WRAPPER>,
<&cru HCLK_ISP0_NOC>, <&cru HCLK_ISP0_WRAPPER>,
@@ -212,7 +215,7 @@
<&cru ACLK_ISP1_NOC>, <&cru ACLK_ISP1_WRAPPER>,
<&cru HCLK_ISP1_NOC>, <&cru HCLK_ISP1_WRAPPER>,
<&cru SCLK_ISP1>, <&cru SCLK_CIF_OUT>,
<&cru SCLK_CIF_OUT>, <&cru SCLK_DPHY_TX1RX1_CFG>,
<&cru SCLK_CIF_OUT_SRC>, <&cru SCLK_DPHY_TX1RX1_CFG>,
<&cru SCLK_MIPIDPHY_REF>, <&cru PCLK_ISP1_WRAPPER>,
<&cru SCLK_DPHY_RX0_CFG>, <&cru PCLK_MIPI_DSI1>,
<&cru SCLK_MIPIDPHY_CFG>;