From 72c304699f38268b01d0925c230a1012ac4e2835 Mon Sep 17 00:00:00 2001 From: Sugar Zhang Date: Tue, 16 Nov 2021 19:37:57 +0800 Subject: [PATCH] clk: rockchip: rk3588: Add audio fracpll freq 983040000 for SR: 8k, 16k, 24k, 48k, 96k, 192k 903168000 for SR: 11.025k 22.05k, 44.1k, 88.2k, 176.4k Signed-off-by: Sugar Zhang Change-Id: Ibd4ab8e18cfc1e973d62b920084cfbe8d3000b0d --- drivers/clk/rockchip/clk-rk3588.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/clk/rockchip/clk-rk3588.c b/drivers/clk/rockchip/clk-rk3588.c index 309ab4424f96..8d53c7e54a74 100644 --- a/drivers/clk/rockchip/clk-rk3588.c +++ b/drivers/clk/rockchip/clk-rk3588.c @@ -76,6 +76,8 @@ static struct rockchip_pll_rate_table rk3588_pll_rates[] = { RK3588_PLL_RATE(1188000000, 2, 198, 1, 0), RK3588_PLL_RATE(1008000000, 2, 336, 2, 0), RK3588_PLL_RATE(1000000000, 3, 500, 2, 0), + RK3588_PLL_RATE(983040000, 3, 491, 2, 34078), + RK3588_PLL_RATE(903168000, 3, 451, 2, 38272), RK3588_PLL_RATE(900000000, 2, 300, 2, 0), RK3588_PLL_RATE(816000000, 2, 272, 2, 0), RK3588_PLL_RATE(786000000, 1, 131, 2, 0),