From 72d459a4621befa68136e4acfb826d4948e781e0 Mon Sep 17 00:00:00 2001 From: Liang Chen Date: Tue, 27 May 2025 11:44:04 +0800 Subject: [PATCH] arm64: dts: rockchip: rk3576-cpu-swap: add cache info for A53 Change-Id: Ib1908adacedb69836159179f8226d6a4e0202550 Signed-off-by: Liang Chen --- .../boot/dts/rockchip/rk3576-cpu-swap.dtsi | 28 +++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3576-cpu-swap.dtsi b/arch/arm64/boot/dts/rockchip/rk3576-cpu-swap.dtsi index 83b9d79a129b..342403eb0b81 100644 --- a/arch/arm64/boot/dts/rockchip/rk3576-cpu-swap.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3576-cpu-swap.dtsi @@ -21,6 +21,13 @@ #cooling-cells = <2>; dynamic-power-coefficient = <120>; cpu-idle-states = <&CPU_SLEEP>; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l2_cache_l>; }; cpu_l1: cpu@001 { @@ -32,6 +39,13 @@ clocks = <&scmi_clk ARMCLK_L>; operating-points-v2 = <&cluster0_opp_table>; cpu-idle-states = <&CPU_SLEEP>; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l2_cache_l>; }; cpu_l2: cpu@002 { @@ -43,6 +57,13 @@ clocks = <&scmi_clk ARMCLK_L>; operating-points-v2 = <&cluster0_opp_table>; cpu-idle-states = <&CPU_SLEEP>; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l2_cache_l>; }; cpu_l3: cpu@003 { @@ -54,6 +75,13 @@ clocks = <&scmi_clk ARMCLK_L>; operating-points-v2 = <&cluster0_opp_table>; cpu-idle-states = <&CPU_SLEEP>; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l2_cache_l>; }; }; };