From 73403cf5b2cea690ea39982cc22a856215e50f60 Mon Sep 17 00:00:00 2001 From: Finley Xiao Date: Wed, 21 Feb 2018 17:53:56 +0800 Subject: [PATCH] clk: rockchip: px30: fix gpll enable_cnt and prepare_cnt error The gpll clock has not yet been created when its children do enable and prepare in cru critical talbe, so move its children into pmucru critical talbe that the gpll clock has been created before its children do enable and prepare. Change-Id: If5243326bf1d3c926bb1bb12e56e4b9fc9282762 Signed-off-by: Finley Xiao --- drivers/clk/rockchip/clk-px30.c | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a/drivers/clk/rockchip/clk-px30.c b/drivers/clk/rockchip/clk-px30.c index 91afa26d6568..5c2d69ffa8a3 100644 --- a/drivers/clk/rockchip/clk-px30.c +++ b/drivers/clk/rockchip/clk-px30.c @@ -1004,7 +1004,7 @@ static struct rockchip_clk_branch px30_clk_pmu_branches[] __initdata = { GATE(0, "pclk_cru_pmu", "pclk_pmu_pre", CLK_IGNORE_UNUSED, PX30_PMU_CLKGATE_CON(0), 8, GFLAGS), }; -static const char *const px30_critical_clocks[] __initconst = { +static const char *const px30_pmucru_critical_clocks[] __initconst = { "aclk_bus_pre", "pclk_bus_pre", "hclk_bus_pre", @@ -1012,9 +1012,6 @@ static const char *const px30_critical_clocks[] __initconst = { "hclk_peri_pre", "aclk_gpu_niu", "pclk_top_pre", -}; - -static const char *const px30_pmucru_critical_clocks[] __initconst = { "pclk_pmu_pre", }; @@ -1083,8 +1080,6 @@ static void __init px30_clk_init(struct device_node *np) PX30_GRF_SOC_STATUS0); rockchip_clk_register_branches(ctx, px30_clk_branches, ARRAY_SIZE(px30_clk_branches)); - rockchip_clk_protect_critical(px30_critical_clocks, - ARRAY_SIZE(px30_critical_clocks)); rockchip_clk_register_armclk(ctx, ARMCLK, "armclk", mux_armclk_p, ARRAY_SIZE(mux_armclk_p),