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UPSTREAM: KVM: arm64: Fix CPU interface MMIO compatibility detection
In order to detect whether a GICv3 CPU interface is MMIO capable, we switch ICC_SRE_EL1.SRE to 0 and check whether it sticks. However, this is only possible if *ALL* of the HCR_EL2 interrupt overrides are set, and the CPU is perfectly allowed to ignore the write to ICC_SRE_EL1 otherwise. This leads KVM to pretend that a whole bunch of ARMv8.0 CPUs aren't MMIO-capable, and breaks VMs that should work correctly otherwise. Fix this by setting IMO/FMO/IMO before touching ICC_SRE_EL1, and clear them afterwards. This allows us to reliably detect the CPU interface capabilities. Tested-by: Shameerali Kolothum Thodi <shameerali.kolothum.thodi@huawei.com> Fixes:9739f6ef05("KVM: arm64: Workaround firmware wrongly advertising GICv2-on-v3 compatibility") Signed-off-by: Marc Zyngier <maz@kernel.org> (cherry picked from commitaf22df997d) Bug: 178098380 Signed-off-by: Will Deacon <willdeacon@google.com> Change-Id: I188304844d50de9e47a0634e0b0179ca96cbf275
This commit is contained in:
committed by
Will Deacon
parent
52840dfa57
commit
73be6141e9
@@ -429,6 +429,13 @@ u64 __vgic_v3_get_gic_config(void)
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if (has_vhe())
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flags = local_daif_save();
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/*
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* Table 11-2 "Permitted ICC_SRE_ELx.SRE settings" indicates
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* that to be able to set ICC_SRE_EL1.SRE to 0, all the
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* interrupt overrides must be set. You've got to love this.
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*/
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sysreg_clear_set(hcr_el2, 0, HCR_AMO | HCR_FMO | HCR_IMO);
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isb();
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write_gicreg(0, ICC_SRE_EL1);
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isb();
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@@ -436,6 +443,8 @@ u64 __vgic_v3_get_gic_config(void)
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write_gicreg(sre, ICC_SRE_EL1);
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isb();
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sysreg_clear_set(hcr_el2, HCR_AMO | HCR_FMO | HCR_IMO, 0);
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isb();
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if (has_vhe())
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local_daif_restore(flags);
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